diff --git a/.ci/compute_projects.py b/.ci/compute_projects.py index 9c2a9bc15cce9..0ea4a84cccf2d 100644 --- a/.ci/compute_projects.py +++ b/.ci/compute_projects.py @@ -64,7 +64,6 @@ "mlir", "polly", "flang", - "libclc", "openmp", }, } @@ -83,7 +82,7 @@ "compiler-rt": {"compiler-rt"}, "flang": {"flang-rt"}, "flang-rt": {"flang-rt"}, - ".ci": {"compiler-rt", "libc", "flang-rt"}, + ".ci": {"compiler-rt", "libc", "flang-rt", "libclc"}, } DEPENDENT_RUNTIMES_TO_TEST_NEEDS_RECONFIG = { "llvm": {"libcxx", "libcxxabi", "libunwind"}, diff --git a/.ci/compute_projects_test.py b/.ci/compute_projects_test.py index fe1bf07eae8ff..21cc2e7bc0bbc 100644 --- a/.ci/compute_projects_test.py +++ b/.ci/compute_projects_test.py @@ -285,7 +285,7 @@ def test_ci(self): ) self.assertEqual( env_variables["projects_to_build"], - "bolt;clang;clang-tools-extra;flang;libclc;lld;lldb;llvm;mlir;polly", + "bolt;clang;clang-tools-extra;flang;lld;lldb;llvm;mlir;polly", ) self.assertEqual( env_variables["project_check_targets"], @@ -293,7 +293,7 @@ def test_ci(self): ) self.assertEqual( env_variables["runtimes_to_build"], - "compiler-rt;flang-rt;libc;libcxx;libcxxabi;libunwind", + "compiler-rt;flang-rt;libc;libclc;libcxx;libcxxabi;libunwind", ) self.assertEqual( env_variables["runtimes_check_targets"], @@ -310,7 +310,7 @@ def test_windows_ci(self): ) self.assertEqual( env_variables["projects_to_build"], - "clang;clang-tools-extra;libclc;lld;llvm;mlir;polly", + "clang;clang-tools-extra;lld;llvm;mlir;polly", ) self.assertEqual( env_variables["project_check_targets"], @@ -318,7 +318,7 @@ def test_windows_ci(self): ) self.assertEqual( env_variables["runtimes_to_build"], - "compiler-rt", + "compiler-rt;libclc", ) self.assertEqual( env_variables["runtimes_check_targets"], @@ -359,7 +359,7 @@ def test_premerge_workflow(self): ) self.assertEqual( env_variables["projects_to_build"], - "bolt;clang;clang-tools-extra;flang;libclc;lld;lldb;llvm;mlir;polly", + "bolt;clang;clang-tools-extra;flang;lld;lldb;llvm;mlir;polly", ) self.assertEqual( env_variables["project_check_targets"], @@ -367,7 +367,7 @@ def test_premerge_workflow(self): ) self.assertEqual( env_variables["runtimes_to_build"], - "compiler-rt;flang-rt;libc;libcxx;libcxxabi;libunwind", + "compiler-rt;flang-rt;libc;libclc;libcxx;libcxxabi;libunwind", ) self.assertEqual( env_variables["runtimes_check_targets"], @@ -394,7 +394,7 @@ def test_third_party_benchmark(self): ) self.assertEqual( env_variables["projects_to_build"], - "bolt;clang;clang-tools-extra;flang;libclc;lld;lldb;llvm;mlir;polly", + "bolt;clang;clang-tools-extra;flang;lld;lldb;llvm;mlir;polly", ) self.assertEqual( env_variables["project_check_targets"], @@ -402,7 +402,7 @@ def test_third_party_benchmark(self): ) self.assertEqual( env_variables["runtimes_to_build"], - "compiler-rt;flang-rt;libc;libcxx;libcxxabi;libunwind", + "compiler-rt;flang-rt;libc;libclc;libcxx;libcxxabi;libunwind", ) self.assertEqual( env_variables["runtimes_check_targets"], diff --git a/.ci/premerge_advisor_explain.py b/.ci/premerge_advisor_explain.py index 6046905284cc4..f4153fa4a635c 100644 --- a/.ci/premerge_advisor_explain.py +++ b/.ci/premerge_advisor_explain.py @@ -33,7 +33,9 @@ def get_comment( pr_number: int, body: str, ) -> dict[str, str]: - repo = github.Github(github_token).get_repo("llvm/llvm-project") + repo = github.Github(auth=github.Auth.Token(github_token)).get_repo( + "llvm/llvm-project" + ) pr = repo.get_issue(pr_number).as_pull_request() body = COMMENT_TAG.format(platform=platform.system()) + "\n" + body comment = {"body": body} diff --git a/.github/renovate.json b/.github/renovate.json index 8e89ba8c4b32a..40609814c0363 100644 --- a/.github/renovate.json +++ b/.github/renovate.json @@ -14,6 +14,12 @@ "matchPackageNames": ["windows", "macos"], "matchManagers": ["github-actions"], "enabled": false + }, + { + "matchPackageNames": ["python"], + "matchManagers": ["github-actions"], + "matchFileNames": ["release-binaries.yml"], + "enabled": false } ] } diff --git a/.github/workflows/commit-create-issue.py b/.github/workflows/commit-create-issue.py index 62bc76cd1b9b6..5ffed8ad799ab 100644 --- a/.github/workflows/commit-create-issue.py +++ b/.github/workflows/commit-create-issue.py @@ -2,7 +2,7 @@ import sys token = sys.argv[1] -gh = github.Github(login_or_token=token) +gh = github.Github(auth=github.Auth.Token(token)) repo = gh.get_repo("llvm/llvm-project") length = "4 weeks" diff --git a/.github/workflows/issue-release-workflow.yml b/.github/workflows/issue-release-workflow.yml index 818dacc90b2d9..630d107e20313 100644 --- a/.github/workflows/issue-release-workflow.yml +++ b/.github/workflows/issue-release-workflow.yml @@ -33,6 +33,7 @@ jobs: backport-commits: name: Backport Commits runs-on: ubuntu-24.04 + environment: main-branch-only permissions: issues: write pull-requests: write diff --git a/.github/workflows/libc-fullbuild-tests.yml b/.github/workflows/libc-fullbuild-tests.yml index 8b04783011372..d9445a6407ccf 100644 --- a/.github/workflows/libc-fullbuild-tests.yml +++ b/.github/workflows/libc-fullbuild-tests.yml @@ -20,68 +20,68 @@ jobs: include: - os: ubuntu-24.04 build_type: Debug - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: x86_64-unknown-linux-llvm include_scudo: ON - os: ubuntu-24.04 build_type: Release - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: x86_64-unknown-linux-llvm include_scudo: ON - os: ubuntu-24.04 build_type: MinSizeRel - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: x86_64-unknown-linux-llvm include_scudo: ON - os: ubuntu-24.04-arm build_type: Debug - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: aarch64-unknown-linux-llvm include_scudo: ON - os: ubuntu-24.04 build_type: Debug - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: x86_64-unknown-uefi-llvm include_scudo: OFF - os: ubuntu-24.04 build_type: MinSizeRel - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: armv6m-none-eabi include_scudo: OFF - os: ubuntu-24.04 build_type: MinSizeRel - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: armv7m-none-eabi include_scudo: OFF - os: ubuntu-24.04 build_type: MinSizeRel - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: armv7em-none-eabi include_scudo: OFF - os: ubuntu-24.04 build_type: MinSizeRel - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: armv8m.main-none-eabi include_scudo: OFF - os: ubuntu-24.04 build_type: MinSizeRel - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: armv8.1m.main-none-eabi include_scudo: OFF - os: ubuntu-24.04 build_type: MinSizeRel - c_compiler: clang-22 - cpp_compiler: clang++-22 + c_compiler: clang-21 + cpp_compiler: clang++-21 target: riscv32-unknown-elf include_scudo: OFF # TODO: add back gcc build when it is fixed @@ -111,7 +111,7 @@ jobs: run: | wget https://apt.llvm.org/llvm.sh chmod +x llvm.sh - sudo ./llvm.sh 22 + sudo ./llvm.sh 21 sudo apt-get update sudo apt-get install -y libmpfr-dev libgmp-dev libmpc-dev ninja-build linux-libc-dev sudo ln -sf /usr/include/$(uname -p)-linux-gnu/asm /usr/include/asm diff --git a/.github/workflows/libcxx-run-benchmarks.yml b/.github/workflows/libcxx-run-benchmarks.yml index eb7793039235d..c686a3b735a2b 100644 --- a/.github/workflows/libcxx-run-benchmarks.yml +++ b/.github/workflows/libcxx-run-benchmarks.yml @@ -48,7 +48,7 @@ jobs: cat <> ${GITHUB_OUTPUT} import github - repo = github.Github("${{ github.token }}").get_repo("${{ github.repository }}") + repo = github.Github(auth=github.Auth.Token("${{ github.token }}")).get_repo("${{ github.repository }}") pr = repo.get_pull(${{ github.event.issue.number }}) print(f"pr_base={pr.base.sha}") print(f"pr_head={pr.head.sha}") @@ -63,23 +63,25 @@ jobs: fetch-tags: true # This job requires access to all the Git branches so it can diff against (usually) main path: repo # Avoid nuking the workspace, where we have the Python virtualenv - - name: Run baseline + - name: Build and run baseline env: BENCHMARKS: ${{ steps.vars.outputs.benchmarks }} run: | source .venv/bin/activate && cd repo python -m pip install -r libcxx/utils/requirements.txt baseline_commit=$(git merge-base ${{ steps.vars.outputs.pr_base }} ${{ steps.vars.outputs.pr_head }}) - ./libcxx/utils/test-at-commit --commit ${baseline_commit} -B build/baseline -- -sv -j1 --param optimization=speed "$BENCHMARKS" - ./libcxx/utils/consolidate-benchmarks build/baseline | tee baseline.lnt + ./libcxx/utils/build-at-commit --commit ${baseline_commit} --install-dir install/baseline -- -DCMAKE_BUILD_TYPE=RelWithDebInfo + ./libcxx/utils/test-at-commit --libcxx-installation install/baseline -B benchmarks/baseline -- -sv -j1 --param optimization=speed "$BENCHMARKS" + ./libcxx/utils/consolidate-benchmarks benchmarks/baseline | tee baseline.lnt - - name: Run candidate + - name: Build and run candidate env: BENCHMARKS: ${{ steps.vars.outputs.benchmarks }} run: | source .venv/bin/activate && cd repo - ./libcxx/utils/test-at-commit --commit ${{ steps.vars.outputs.pr_head }} -B build/candidate -- -sv -j1 --param optimization=speed "$BENCHMARKS" - ./libcxx/utils/consolidate-benchmarks build/candidate | tee candidate.lnt + ./libcxx/utils/build-at-commit --commit ${{ steps.vars.outputs.pr_head }} --install-dir install/candidate -- -DCMAKE_BUILD_TYPE=RelWithDebInfo + ./libcxx/utils/test-at-commit --libcxx-installation install/candidate -B benchmarks/candidate -- -sv -j1 --param optimization=speed "$BENCHMARKS" + ./libcxx/utils/consolidate-benchmarks benchmarks/candidate | tee candidate.lnt - name: Compare baseline and candidate runs run: | @@ -91,7 +93,7 @@ jobs: source .venv/bin/activate && cd repo cat <- + github.repository == 'llvm/llvm-project' && + github.event_name != 'pull_request' && + failure() + needs: + - audit + steps: + - name: Download Comment + uses: actions/download-artifact@37930b1c2abaa49bbe596cd826c3c89aef350131 # v7.0.0 + with: + name: comment - name: "File Issue" - if: >- - github.event_name != 'pull_request' && - failure() uses: actions/github-script@ed597411d8f924073f98dfc5c65a23a2325f34cd # v8.0.0 with: github-token: ${{ secrets.ISSUE_SUBSCRIBER_TOKEN }} diff --git a/.github/workflows/release-binaries-all.yml b/.github/workflows/release-binaries-all.yml index 656ed80b357ea..5a775082f4586 100644 --- a/.github/workflows/release-binaries-all.yml +++ b/.github/workflows/release-binaries-all.yml @@ -94,6 +94,7 @@ jobs: - ubuntu-22.04-arm - macos-14 - windows-2022 + - windows-11-arm uses: ./.github/workflows/release-binaries.yml with: diff --git a/.github/workflows/release-binaries.yml b/.github/workflows/release-binaries.yml index 3bf6860d4e537..a8188289412a0 100644 --- a/.github/workflows/release-binaries.yml +++ b/.github/workflows/release-binaries.yml @@ -62,7 +62,7 @@ jobs: release-binary-filename: ${{ steps.vars.outputs.release-binary-filename }} build-runs-on: ${{ steps.vars.outputs.build-runs-on }} test-runs-on: ${{ steps.vars.outputs.build-runs-on }} - attestation-name: ${{ steps.vars.outptus.attestation-name }} + attestation-name: ${{ steps.vars.outputs.attestation-name }} steps: # It's good practice to use setup-python, but this is also required on macos-14 @@ -71,6 +71,13 @@ jobs: with: python-version: '3.14' + - name: Install Windows ARM64 dependencies + if: runner.os == 'Windows' && runner.arch == 'ARM64' + run: | + # Some of the python modules we install require this package to be installed on the system. + vcpkg install openssl:arm64-windows-static-md + echo "OPENSSL_DIR=$env:VCPKG_INSTALLATION_ROOT\installed\arm64-windows-static-md" >> $env:GITHUB_ENV + - name: Checkout LLVM uses: actions/checkout@8e8c483db84b4bee98b60c0593521ed34d9990e8 # v6.0.1 @@ -168,6 +175,10 @@ jobs: build_runs_on="depot-${{ inputs.runs-on }}-16" test_runs_on=$build_runs_on ;; + windows-11-arm) + build_runs_on="windows-11-arm-16core" + test_runs_on=$build_runs_on + ;; macos-14) if [ "$GITHUB_EVENT_NAME" = "pull_request" ]; then build_runs_on="${{ inputs.runs-on }}" @@ -223,7 +234,7 @@ jobs: - name: Setup Python library path if: runner.os == 'Windows' run: | - echo "LIB=$env:LIB;C:\hostedtoolcache\windows\Python\3.11.9\x64\libs" >> $env:GITHUB_ENV + echo "LIB=$env:LIB;C:\hostedtoolcache\windows\Python\3.11.9\$($env:RUNNER_ARCH.ToLower())\libs" >> $env:GITHUB_ENV - name: Setup crlf if: runner.os == 'Windows' diff --git a/.gitignore b/.gitignore index 85b5caa162124..9ce99993e767c 100644 --- a/.gitignore +++ b/.gitignore @@ -20,8 +20,8 @@ # vim swap files .*.sw? .sw? -#OS X specific files. -.DS_store +#macOS specific +.DS_Store # Ignore the user specified CMake presets in subproject directories. /*/CMakeUserPresets.json diff --git a/.mailmap b/.mailmap index a3f9dbcab0198..a92224c9da370 100644 --- a/.mailmap +++ b/.mailmap @@ -32,7 +32,7 @@ Min Hsu Min Hsu - + Jianjian GUAN Jianjian GUAN diff --git a/bolt/include/bolt/Profile/DataAggregator.h b/bolt/include/bolt/Profile/DataAggregator.h index db0f6903185b7..666df9eb18ed8 100644 --- a/bolt/include/bolt/Profile/DataAggregator.h +++ b/bolt/include/bolt/Profile/DataAggregator.h @@ -19,6 +19,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/Support/Error.h" #include "llvm/Support/Program.h" +#include #include namespace llvm { @@ -108,10 +109,14 @@ class DataAggregator : public DataReader { /// (FT_ONLY, FT_EXTERNAL_ORIGIN, or FT_EXTERNAL_RETURN). struct Trace { static constexpr const uint64_t EXTERNAL = 0ULL; - static constexpr const uint64_t BR_ONLY = -1ULL; - static constexpr const uint64_t FT_ONLY = -1ULL; - static constexpr const uint64_t FT_EXTERNAL_ORIGIN = -2ULL; - static constexpr const uint64_t FT_EXTERNAL_RETURN = -3ULL; + static constexpr const uint64_t BR_ONLY = + std::numeric_limits::max(); + static constexpr const uint64_t FT_ONLY = + std::numeric_limits::max(); + static constexpr const uint64_t FT_EXTERNAL_ORIGIN = + std::numeric_limits::max() - 1; + static constexpr const uint64_t FT_EXTERNAL_RETURN = + std::numeric_limits::max() - 2; uint64_t Branch; uint64_t From; diff --git a/bolt/lib/Passes/IdenticalCodeFolding.cpp b/bolt/lib/Passes/IdenticalCodeFolding.cpp index b63bab75540be..1c99a60bfaad3 100644 --- a/bolt/lib/Passes/IdenticalCodeFolding.cpp +++ b/bolt/lib/Passes/IdenticalCodeFolding.cpp @@ -33,6 +33,8 @@ namespace opts { extern cl::OptionCategory BoltOptCategory; +extern bool isHotTextMover(const BinaryFunction &Function); + static cl::opt ICFUseDFS("icf-dfs", cl::desc("use DFS ordering when using -icf option"), cl::ReallyHidden, cl::cat(BoltOptCategory)); @@ -186,6 +188,11 @@ static bool isIdenticalWith(const BinaryFunction &A, const BinaryFunction &B, bool CongruentSymbols) { assert(A.hasCFG() && B.hasCFG() && "both functions should have CFG"); + // Hot text mover functions should not be folded. They need to stay in their + // original section to avoid being placed on hot/huge pages. + if (opts::isHotTextMover(A) || opts::isHotTextMover(B)) + return false; + // Compare the two functions, one basic block at a time. // Currently we require two identical basic blocks to have identical // instruction sequences and the same index in their corresponding diff --git a/bolt/lib/Profile/DataAggregator.cpp b/bolt/lib/Profile/DataAggregator.cpp index cce08658fefb9..a616d9db9db0e 100644 --- a/bolt/lib/Profile/DataAggregator.cpp +++ b/bolt/lib/Profile/DataAggregator.cpp @@ -1729,10 +1729,10 @@ std::error_code DataAggregator::parseMemEvents() { if (std::error_code EC = Sample.getError()) return EC; - if (BinaryFunction *BF = getBinaryFunctionContainingAddress(Sample->PC)) + if (BinaryFunction *BF = getBinaryFunctionContainingAddress(Sample->PC)) { BF->setHasProfileAvailable(); - - MemSamples.emplace_back(std::move(Sample.get())); + MemSamples.emplace_back(std::move(Sample.get())); + } } return std::error_code(); diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index 3953653caf5c8..b475c6e137909 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -3136,10 +3136,11 @@ void RewriteInstance::handleRelocation(const SectionRef &RelocatedSection, ReferencedSymbol = nullptr; ExtractedValue = Address; } else if (RefFunctionOffset) { - if (ContainingBF && ContainingBF != ReferencedBF && - !ReferencedBF->isInConstantIsland(Address)) { + if (ContainingBF && ContainingBF != ReferencedBF) { ReferencedSymbol = - ReferencedBF->addEntryPointAtOffset(RefFunctionOffset); + ReferencedBF->isInConstantIsland(Address) + ? ReferencedBF->getOrCreateIslandAccess(Address) + : ReferencedBF->addEntryPointAtOffset(RefFunctionOffset); } else { ReferencedSymbol = ReferencedBF->getOrCreateLocalLabel(Address); diff --git a/bolt/test/AArch64/constant-island-reference.s b/bolt/test/AArch64/constant-island-reference.s new file mode 100644 index 0000000000000..7148bbb296127 --- /dev/null +++ b/bolt/test/AArch64/constant-island-reference.s @@ -0,0 +1,20 @@ +// Test BOLT won't ignore function having reference to constant island +// that is defined in another function. + +// RUN: %clang %cxxflags -fuse-ld=lld %s -o %t.so -Wl,-q -no-pie +// RUN: llvm-bolt %t.so -o %t.bolt.so --strict + + .text + .type foo,@function +foo: + adrp x9, :got:_global_func_ptr + ldr x9, [x9, #:got_lo12:_global_func_ptr] + blr x9 + .size foo, .-foo + + .type bar,@function +bar: + nop +_global_func_ptr: + .quad 0 + .size bar, .-bar diff --git a/bolt/test/icf-hot-text-mover.c b/bolt/test/icf-hot-text-mover.c new file mode 100644 index 0000000000000..3ecfe9b2c135b --- /dev/null +++ b/bolt/test/icf-hot-text-mover.c @@ -0,0 +1,24 @@ +// Check that ICF does not fold hot text mover functions. +// Hot text mover functions are placed in special sections (e.g., .never_hugify) +// to avoid being placed on hot/huge pages. + +// clang-format off + +// REQUIRES: system-linux, asserts +// RUN: %clang %cflags -O0 %s -o %t.exe -Wl,-q +// RUN: llvm-bolt %t.exe --icf --hot-text-move-sections=.never_hugify \ +// RUN: -debug-only=bolt-icf -o %t.bolt 2>&1 | FileCheck %s + +// FuncA is in .text, FuncB is in .never_hugify (a hot text mover section). +// They are identical, but FuncB should NOT be folded because it is a hot text mover. +// CHECK: ICF iteration 1 +// CHECK-NOT: folding FuncB into FuncA +// CHECK-NOT: folding FuncA into FuncB + +__attribute__((noinline)) int FuncA(void) { return 42; } + +__attribute__((section(".never_hugify"), noinline)) int FuncB(void) { + return 42; +} + +int main(void) { return FuncA() + FuncB(); } diff --git a/clang-tools-extra/Maintainers.rst b/clang-tools-extra/Maintainers.rst index 7ed08577ec4bb..fa1343a28942d 100644 --- a/clang-tools-extra/Maintainers.rst +++ b/clang-tools-extra/Maintainers.rst @@ -57,9 +57,6 @@ clangd | Chris Bieneman | chris.bieneman@gmail.com (email), llvm-beanz (GitHub), beanz (Discord), beanz (Discourse) -| Kadir Çetinkaya -| kadircet@google.com (email), kadircet (GitHub) kadircet (Discourse), kadircet (Discord) - Inactive Maintainers ==================== @@ -79,3 +76,4 @@ Inactive component maintainers | Sam McCall (sammccall@google.com (email), sam-mccall (GitHub, Discourse, Discord)) -- clangd | Peter Chou (peterchou411@gmail.com (email), PeterChou1 (GitHub, Discourse), .peterchou (Discord)) -- clang-doc | Piotr Zegar (me@piotrzegar.pl (email), PiotrZSL (GitHub), PiotrZSL (Discourse), PiotrZSL (Discord)) -- clang-tidy +| Kadir Çetinkaya (kadircet@google.com (email), kadircet (GitHub) kadircet (Discourse), kadircet (Discord)) -- clangd diff --git a/clang-tools-extra/clang-apply-replacements/tool/ClangApplyReplacementsMain.cpp b/clang-tools-extra/clang-apply-replacements/tool/ClangApplyReplacementsMain.cpp index 76de8bd877d03..83e47d09f5b53 100644 --- a/clang-tools-extra/clang-apply-replacements/tool/ClangApplyReplacementsMain.cpp +++ b/clang-tools-extra/clang-apply-replacements/tool/ClangApplyReplacementsMain.cpp @@ -139,7 +139,7 @@ int main(int argc, char **argv) { return 1; tooling::ApplyChangesSpec Spec; - Spec.Cleanup = true; + Spec.Cleanup = DoFormat; Spec.Format = DoFormat ? tooling::ApplyChangesSpec::kAll : tooling::ApplyChangesSpec::kNone; Spec.Style = DoFormat ? FormatStyle : format::getNoStyle(); diff --git a/clang-tools-extra/clang-tidy/add_new_check.py b/clang-tools-extra/clang-tidy/add_new_check.py index 2f284a30ab4cf..53a9e49f8e4f2 100755 --- a/clang-tools-extra/clang-tidy/add_new_check.py +++ b/clang-tools-extra/clang-tidy/add_new_check.py @@ -452,6 +452,7 @@ def has_fixits(code: str) -> bool: "FixItHint", "ReplacementText", "fixit", + "FixIt", "TransformerClangTidyCheck", ]: if needle in code: diff --git a/clang-tools-extra/clang-tidy/android/ComparisonInTempFailureRetryCheck.cpp b/clang-tools-extra/clang-tidy/android/ComparisonInTempFailureRetryCheck.cpp index c42f069b487c3..ba399efa4a8a6 100644 --- a/clang-tools-extra/clang-tidy/android/ComparisonInTempFailureRetryCheck.cpp +++ b/clang-tools-extra/clang-tidy/android/ComparisonInTempFailureRetryCheck.cpp @@ -83,7 +83,7 @@ void ComparisonInTempFailureRetryCheck::check( const auto &Inner = *Result.Nodes.getNodeAs("inner"); diag(Inner.getOperatorLoc(), "top-level comparison in %0") << RetryMacroName; - // FIXME: FixIts would be nice, but potentially nontrivial when nested macros + // FIXME: Fix-its would be nice, but potentially nontrivial when nested macros // happen, e.g. `TEMP_FAILURE_RETRY(IS_ZERO(foo()))` } diff --git a/clang-tools-extra/clang-tidy/bugprone/ArgumentCommentCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/ArgumentCommentCheck.cpp index 2e963cd995f74..d46896808bd09 100644 --- a/clang-tools-extra/clang-tidy/bugprone/ArgumentCommentCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/ArgumentCommentCheck.cpp @@ -268,6 +268,11 @@ void ArgumentCommentCheck::checkCallArgs(ASTContext *Ctx, return; Callee = Callee->getFirstDecl(); + if (const auto *Ctor = dyn_cast(Callee); + Ctor && Ctor->isInheritingConstructor()) { + if (const auto *BaseCtor = Ctor->getInheritedConstructor().getConstructor()) + Callee = BaseCtor->getFirstDecl(); + } const unsigned NumArgs = std::min(Args.size(), Callee->getNumParams()); if ((NumArgs == 0) || (IgnoreSingleArgument && NumArgs == 1)) diff --git a/clang-tools-extra/clang-tidy/bugprone/StringConstructorCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/StringConstructorCheck.cpp index d2e631e539b78..d6bc4caf23879 100644 --- a/clang-tools-extra/clang-tidy/bugprone/StringConstructorCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/StringConstructorCheck.cpp @@ -81,7 +81,8 @@ void StringConstructorCheck::registerMatchers(MatchFinder *Finder) { Finder->addMatcher( cxxConstructExpr( hasDeclaration(cxxMethodDecl(hasName("basic_string"))), - argumentCountIs(2), hasArgument(0, hasType(qualType(isInteger()))), + anyOf(argumentCountIs(2), argumentCountIs(3)), + hasArgument(0, hasType(qualType(isInteger()))), hasArgument(1, hasType(qualType(isInteger()))), anyOf( // Detect the expression: string('x', 40); @@ -101,7 +102,10 @@ void StringConstructorCheck::registerMatchers(MatchFinder *Finder) { cxxConstructExpr( hasDeclaration(cxxConstructorDecl(ofClass( cxxRecordDecl(hasAnyName(removeNamespaces(StringNames)))))), - argumentCountIs(2), hasArgument(0, hasType(CharPtrType)), + anyOf(argumentCountIs(2), + allOf(argumentCountIs(3), + hasArgument(2, unless(hasType(qualType(isInteger())))))), + hasArgument(0, hasType(CharPtrType)), hasArgument(1, hasType(isInteger())), anyOf( // Detect the expression: string("...", 0); @@ -123,7 +127,8 @@ void StringConstructorCheck::registerMatchers(MatchFinder *Finder) { cxxConstructExpr( hasDeclaration(cxxConstructorDecl(ofClass( cxxRecordDecl(hasAnyName(removeNamespaces(StringNames)))))), - argumentCountIs(3), hasArgument(0, hasType(CharPtrType)), + anyOf(argumentCountIs(3), argumentCountIs(4)), + hasArgument(0, hasType(CharPtrType)), hasArgument(1, hasType(qualType(isInteger()))), hasArgument(2, hasType(qualType(isInteger()))), anyOf( diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeVarargCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeVarargCheck.cpp index d5ff4af84b0b7..daa9f983b7886 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeVarargCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeVarargCheck.cpp @@ -178,6 +178,16 @@ void ProTypeVarargCheck::check(const MatchFinder::MatchResult &Result) { if (const auto *Matched = Result.Nodes.getNodeAs("callvararg")) { if (hasSingleVariadicArgumentWithValue(Matched, 0)) return; + + // Skip builtins with custom type checking - they use variadics as an + // implementation detail to accept multiple types, not for C-style varargs. + // TODO: Remove some of the entries from the `AllowedVariadics` list. + if (const auto *FD = Matched->getDirectCallee()) + if (const unsigned BuiltinID = FD->getBuiltinID(); + BuiltinID && + Result.Context->BuiltinInfo.hasCustomTypechecking(BuiltinID)) + return; + diag(Matched->getExprLoc(), "do not call c-style vararg functions"); } diff --git a/clang-tools-extra/clang-tidy/modernize/UseStructuredBindingCheck.cpp b/clang-tools-extra/clang-tidy/modernize/UseStructuredBindingCheck.cpp index b56fb0579f1e3..8dd6bbfa3d2ab 100644 --- a/clang-tools-extra/clang-tidy/modernize/UseStructuredBindingCheck.cpp +++ b/clang-tools-extra/clang-tidy/modernize/UseStructuredBindingCheck.cpp @@ -348,6 +348,7 @@ void UseStructuredBindingCheck::check(const MatchFinder::MatchResult &Result) { case TT_ByConstRef: return "const auto&"; } + llvm_unreachable("Unhandled TransferType enum"); }(); const std::string ReplacementText = diff --git a/clang-tools-extra/clang-tidy/performance/StringViewConversionsCheck.cpp b/clang-tools-extra/clang-tidy/performance/StringViewConversionsCheck.cpp index f09f6f203bf3a..aebbec5e9b913 100644 --- a/clang-tools-extra/clang-tidy/performance/StringViewConversionsCheck.cpp +++ b/clang-tools-extra/clang-tidy/performance/StringViewConversionsCheck.cpp @@ -78,13 +78,13 @@ void StringViewConversionsCheck::registerMatchers(MatchFinder *Finder) { .bind("redundantExpr")), // Exclude cases of std::string methods or operator+ calls unless(anyOf(HasStringOperatorCall, HasStringMethodCall))) - .bind("expr"), + .bind("paramExpr"), parmVarDecl(hasType(IsStdStringView)))), this); } void StringViewConversionsCheck::check(const MatchFinder::MatchResult &Result) { - const auto *ParamExpr = Result.Nodes.getNodeAs("expr"); + const auto *ParamExpr = Result.Nodes.getNodeAs("paramExpr"); const auto *RedundantExpr = Result.Nodes.getNodeAs("redundantExpr"); const auto *OriginalExpr = Result.Nodes.getNodeAs("originalStringView"); assert(RedundantExpr && ParamExpr && OriginalExpr); @@ -92,7 +92,10 @@ void StringViewConversionsCheck::check(const MatchFinder::MatchResult &Result) { // Sanity check. Verify that the redundant expression is the direct source of // the argument, not part of a larger expression (e.g., std::string(sv) + // "bar"). - assert(ParamExpr->getSourceRange() == RedundantExpr->getSourceRange()); + // FIXME: This is a temporary solution to avoid assertions. Instead the + // matcher must be fixed. + if (ParamExpr->getSourceRange() != RedundantExpr->getSourceRange()) + return; const StringRef OriginalText = Lexer::getSourceText( CharSourceRange::getTokenRange(OriginalExpr->getSourceRange()), diff --git a/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp b/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp index e8c1e3a610fae..83fc3727cb5c8 100644 --- a/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp @@ -634,7 +634,7 @@ std::string IdentifierNamingCheck::HungarianNotation::getDataTypePrefix( return PrefixStr; } -std::string IdentifierNamingCheck::HungarianNotation::getClassPrefix( +llvm::StringRef IdentifierNamingCheck::HungarianNotation::getClassPrefix( const CXXRecordDecl *CRD, const IdentifierNamingCheck::HungarianNotationOption &HNOption) const { if (CRD->isUnion()) diff --git a/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h b/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h index 87735808dff39..b016556cc2ab8 100644 --- a/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h +++ b/clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.h @@ -116,7 +116,7 @@ class IdentifierNamingCheck final : public RenamerClangTidyCheck { StringRef TypeName, const NamedDecl *ND, const IdentifierNamingCheck::HungarianNotationOption &HNOption) const; - std::string getClassPrefix( + llvm::StringRef getClassPrefix( const CXXRecordDecl *CRD, const IdentifierNamingCheck::HungarianNotationOption &HNOption) const; diff --git a/clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp b/clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp index e1a73aa47919e..576603a978e3f 100644 --- a/clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/SuspiciousCallArgumentCheck.cpp @@ -528,7 +528,11 @@ SuspiciousCallArgumentCheck::SuspiciousCallArgumentCheck( for (const StringRef Abbreviation : optutils::parseStringList( Options.get("Abbreviations", DefaultAbbreviations))) { const auto [Key, Value] = Abbreviation.split("="); - assert(!Key.empty() && !Value.empty()); + if (Key.empty() || Value.empty()) { + configurationDiag("Invalid abbreviation configuration '%0', ignoring.") + << Abbreviation; + continue; + } AbbreviationDictionary.try_emplace(Key, Value.str()); } } diff --git a/clang-tools-extra/clangd/ClangdLSPServer.cpp b/clang-tools-extra/clangd/ClangdLSPServer.cpp index 761b07eceec83..ebd42abd2dd61 100644 --- a/clang-tools-extra/clangd/ClangdLSPServer.cpp +++ b/clang-tools-extra/clangd/ClangdLSPServer.cpp @@ -1833,7 +1833,7 @@ void ClangdLSPServer::onDiagnosticsReady(PathRef File, llvm::StringRef Version, // Cache DiagRefMap { std::lock_guard Lock(DiagRefMutex); - DiagRefMap[File] = LocalDiagMap; + DiagRefMap[File] = std::move(LocalDiagMap); } // Send a notification to the LSP client. diff --git a/clang-tools-extra/clangd/Protocol.cpp b/clang-tools-extra/clangd/Protocol.cpp index 9926f2dd63de5..a697486d48f9c 100644 --- a/clang-tools-extra/clangd/Protocol.cpp +++ b/clang-tools-extra/clangd/Protocol.cpp @@ -1511,7 +1511,7 @@ bool fromJSON(const llvm::json::Value &Params, CallHierarchyItem &I, bool fromJSON(const llvm::json::Value &Params, CallHierarchyIncomingCallsParams &C, llvm::json::Path P) { llvm::json::ObjectMapper O(Params, P); - return O.map("item", C.item); + return O && O.map("item", C.item); } llvm::json::Value toJSON(const CallHierarchyIncomingCall &C) { @@ -1521,7 +1521,7 @@ llvm::json::Value toJSON(const CallHierarchyIncomingCall &C) { bool fromJSON(const llvm::json::Value &Params, CallHierarchyOutgoingCallsParams &C, llvm::json::Path P) { llvm::json::ObjectMapper O(Params, P); - return O.map("item", C.item); + return O && O.map("item", C.item); } llvm::json::Value toJSON(const CallHierarchyOutgoingCall &C) { diff --git a/clang-tools-extra/clangd/test/call-hierarchy.test b/clang-tools-extra/clangd/test/call-hierarchy.test index 6548ea0068a8d..f0d57b60421a4 100644 --- a/clang-tools-extra/clangd/test/call-hierarchy.test +++ b/clang-tools-extra/clangd/test/call-hierarchy.test @@ -34,6 +34,18 @@ # CHECK-NEXT: "uri": "file://{{.*}}/clangd-test/main.cpp" # CHECK-NEXT: } --- -{"jsonrpc":"2.0","id":3,"method":"shutdown"} +{"jsonrpc":"2.0","id":3,"method":"callHierarchy/incomingCalls","params":[]} +# CHECK: "error": { +# CHECK-NEXT: "code": -32602, +# CHECK-NEXT: "message": "failed to decode callHierarchy/incomingCalls request: expected object" +# CHECK-NEXT: } +--- +{"jsonrpc":"2.0","id":4,"method":"callHierarchy/outgoingCalls","params":4} +# CHECK: "error": { +# CHECK-NEXT: "code": -32602, +# CHECK-NEXT: "message": "failed to decode callHierarchy/outgoingCalls request: expected object" +# CHECK-NEXT: } +--- +{"jsonrpc":"2.0","id":5,"method":"shutdown"} --- {"jsonrpc":"2.0","method":"exit"} diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 8cf2006172d3f..7b5b332bdb8a2 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -115,7 +115,7 @@ New checks Looks for functions returning ``std::[w|u8|u16|u32]string`` and suggests to change it to ``std::[...]string_view`` for performance reasons if possible. - + - New :doc:`modernize-use-structured-binding ` check. @@ -140,10 +140,19 @@ New check aliases Changes in existing checks ^^^^^^^^^^^^^^^^^^^^^^^^^^ +- Improved :doc:`bugprone-argument-comment + ` to also check for C++11 + inherited constructors. + - Improved :doc:`bugprone-macro-parentheses ` check by printing the macro definition in the warning message if the macro is defined on command line. +- Improved :doc:`bugprone-string-constructor + ` check to detect suspicious + string constructor calls when the string class constructor has a default + allocator argument. + - Improved :doc:`bugprone-unsafe-functions ` check by adding the function ``std::get_temporary_buffer`` to the default list of unsafe functions. (This @@ -154,6 +163,12 @@ Changes in existing checks the invalidating function in the warning message when a custom invalidation function is used (via the `InvalidationFunctions` option). +- Improved :doc:`cppcoreguidelines-pro-type-vararg + ` check by no longer + warning on builtins with custom type checking (e.g., type-generic builtins + like ``__builtin_clzg``) that use variadic declarations as an implementation + detail. + - Improved :doc:`llvm-use-ranges ` check by adding support for the following algorithms: ``std::accumulate``, ``std::replace_copy``, and @@ -193,6 +208,10 @@ Changes in existing checks ` check by avoiding false positives on parameters used in dependent expressions. +- Improved :doc:`readability-suspicious-call-argument + ` check by avoiding a + crash from invalid ``Abbreviations`` option. + Removed checks ^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst b/clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst index 325f5697481b6..7aef674724b08 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst @@ -382,3 +382,21 @@ accessed: } } } + +Reasoning about integers +------------------------ + +Because it uses a simple SAT solver, the check cannot reason about integer +inequalities. For instance, the following will result in a false positive: + +.. code:: cpp + + void f(int n, absl::StatusOr x) { + if (n > 0) + CHECK_OK(x); + if (n > 1) + return *x; // false positive + return 0; + } + +In fact, currently this is also the case if the two conditions are identical. diff --git a/clang-tools-extra/docs/clang-tidy/checks/cert/dcl58-cpp.rst b/clang-tools-extra/docs/clang-tidy/checks/cert/dcl58-cpp.rst index f584e88413b13..d77a82aa5b687 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cert/dcl58-cpp.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cert/dcl58-cpp.rst @@ -1,4 +1,6 @@ .. title:: clang-tidy - cert-dcl58-cpp +.. meta:: + :http-equiv=refresh: 5;URL=../bugprone/std-namespace-modification.html cert-dcl58-cpp ============== diff --git a/clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst b/clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst index 33fa7f1c3dd57..2a955fc15b2f9 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst @@ -1,4 +1,6 @@ .. title:: clang-tidy - cert-env33-c +.. meta:: + :http-equiv=refresh: 5;URL=../bugprone/command-processor.html cert-env33-c ============ diff --git a/clang-tools-extra/docs/clang-tidy/checks/cert/err52-cpp.rst b/clang-tools-extra/docs/clang-tidy/checks/cert/err52-cpp.rst index 4b726d8115662..091c7a8e278df 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cert/err52-cpp.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cert/err52-cpp.rst @@ -1,4 +1,6 @@ .. title:: clang-tidy - cert-err52-cpp +.. meta:: + :http-equiv=refresh: 5;URL=../modernize/avoid-setjmp-longjmp.html cert-err52-cpp ============== diff --git a/clang-tools-extra/docs/clang-tidy/checks/cert/flp30-c.rst b/clang-tools-extra/docs/clang-tidy/checks/cert/flp30-c.rst index 8bd23f6cdd29d..72889d688335e 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cert/flp30-c.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cert/flp30-c.rst @@ -1,4 +1,6 @@ .. title:: clang-tidy - cert-flp30-c +.. meta:: + :http-equiv=refresh: 5;URL=../bugprone/float-loop-counter.html cert-flp30-c ============ diff --git a/clang-tools-extra/docs/clang-tidy/checks/cert/mem57-cpp.rst b/clang-tools-extra/docs/clang-tidy/checks/cert/mem57-cpp.rst index aeeffecac0011..4ef3e4a9d9e34 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cert/mem57-cpp.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cert/mem57-cpp.rst @@ -1,4 +1,6 @@ .. title:: clang-tidy - cert-mem57-cpp +.. meta:: + :http-equiv=refresh: 5;URL=../bugprone/default-operator-new-on-overaligned-type.html cert-mem57-cpp ============== diff --git a/clang-tools-extra/docs/clang-tidy/checks/fuchsia/multiple-inheritance.rst b/clang-tools-extra/docs/clang-tidy/checks/fuchsia/multiple-inheritance.rst index c5ae6a2efb2cb..6e651a770e391 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/fuchsia/multiple-inheritance.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/fuchsia/multiple-inheritance.rst @@ -1,4 +1,6 @@ .. title:: clang-tidy - fuchsia-multiple-inheritance +.. meta:: + :http-equiv=refresh: 5;URL=../misc/multiple-inheritance.html fuchsia-multiple-inheritance ============================ diff --git a/clang-tools-extra/docs/clang-tidy/checks/google/readability-casting.rst b/clang-tools-extra/docs/clang-tidy/checks/google/readability-casting.rst index 77983c400053d..55a17a69742c3 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/google/readability-casting.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/google/readability-casting.rst @@ -1,4 +1,6 @@ .. title:: clang-tidy - google-readability-casting +.. meta:: + :http-equiv=refresh: 5;URL=../modernize/avoid-c-style-cast.html google-readability-casting ========================== diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index 34d1c2ce0a174..0eabd9929dc39 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -182,10 +182,6 @@ Clang-Tidy Checks :doc:`bugprone-use-after-move `, :doc:`bugprone-virtual-near-miss `, "Yes" :doc:`cert-err33-c `, - :doc:`cert-err60-cpp `, - :doc:`cert-flp30-c `, - :doc:`cert-msc50-cpp `, - :doc:`cert-oop58-cpp `, :doc:`concurrency-mt-unsafe `, :doc:`concurrency-thread-canceltype-asynchronous `, :doc:`cppcoreguidelines-avoid-capturing-lambda-coroutines `, @@ -293,7 +289,7 @@ Clang-Tidy Checks :doc:`misc-use-internal-linkage `, "Yes" :doc:`modernize-avoid-bind `, "Yes" :doc:`modernize-avoid-c-arrays `, - :doc:`modernize-avoid-c-style-cast `, + :doc:`modernize-avoid-c-style-cast `, "Yes" :doc:`modernize-avoid-setjmp-longjmp `, :doc:`modernize-avoid-variadic-functions `, :doc:`modernize-concat-nested-namespaces `, "Yes" @@ -595,7 +591,7 @@ Check aliases :doc:`fuchsia-multiple-inheritance `, :doc:`misc-multiple-inheritance `, :doc:`google-build-namespaces `, :doc:`misc-anonymous-namespace-in-header `, :doc:`google-readability-braces-around-statements `, :doc:`readability-braces-around-statements `, "Yes" - :doc:`google-readability-casting `, :doc:`modernize-avoid-c-style-cast `, + :doc:`google-readability-casting `, :doc:`modernize-avoid-c-style-cast `, "Yes" :doc:`google-readability-function-size `, :doc:`readability-function-size `, :doc:`google-readability-namespace-comments `, :doc:`llvm-namespace-comment `, :doc:`hicpp-avoid-c-arrays `, :doc:`modernize-avoid-c-arrays `, diff --git a/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string b/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string index c3fd2cf6c1ff7..7de709d07f2df 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string +++ b/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string @@ -27,6 +27,7 @@ struct basic_string { basic_string(const C *p, size_type count); basic_string(const C *b, const C *e); basic_string(size_t, C); + operator basic_string_view() const; ~basic_string(); @@ -108,7 +109,6 @@ struct basic_string_view { const C *str; constexpr basic_string_view(const C* s) : str(s) {} - basic_string_view(const basic_string&) {} const C *data() const; diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/argument-comment-cxx-11-inherited-constructors.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/argument-comment-cxx-11-inherited-constructors.cpp new file mode 100644 index 0000000000000..679cbb2df681d --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/argument-comment-cxx-11-inherited-constructors.cpp @@ -0,0 +1,32 @@ +// RUN: %check_clang_tidy -std=c++11-or-later %s bugprone-argument-comment %t + +struct Base { + explicit Base(int val) {} +}; + +struct Over : public Base { + using Base::Base; +}; + +struct Derived : public Over { + using Over::Over; +}; + +int wrong() { + Base b{/*val2=*/2}; +// CHECK-NOTES: [[@LINE-1]]:10: warning: argument name 'val2' in comment does not match parameter name 'val' +// CHECK-NOTES: [[@LINE-14]]:21: note: 'val' declared here +// CHECK-FIXES: Base b{/*val=*/2}; + + Over o{/*val3=*/3}; +// CHECK-NOTES: [[@LINE-1]]:10: warning: argument name 'val3' in comment does not match parameter name 'val' +// CHECK-NOTES: [[@LINE-19]]:21: note: 'val' declared here +// CHECK-NOTES: [[@LINE-16]]:15: note: actual callee ('Base') is declared here +// CHECK-FIXES: Over o{/*val=*/3}; + + Derived d{/*val4=*/4}; +// CHECK-NOTES: [[@LINE-1]]:13: warning: argument name 'val4' in comment does not match parameter name 'val' +// CHECK-NOTES: [[@LINE-25]]:21: note: 'val' declared here +// CHECK-NOTES: [[@LINE-18]]:15: note: actual callee ('Base') is declared here +// CHECK-FIXES: Derived d{/*val=*/4}; +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp index 2576d19916250..af844b04aa438 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor.cpp @@ -8,10 +8,10 @@ class char_traits {}; template , typename A = std::allocator > struct basic_string { basic_string(); - basic_string(const C*, unsigned int size); + basic_string(const C*, unsigned int size, const A &a = A()); basic_string(const C *, const A &allocator = A()); - basic_string(unsigned int size, C c); - basic_string(const C*, unsigned int pos, unsigned int size); + basic_string(unsigned int size, C c, const A &a = A()); + basic_string(const C*, unsigned int pos, unsigned int size, const A &a = A()); }; typedef basic_string string; typedef basic_string wstring; @@ -119,6 +119,44 @@ std::string_view StringViewFromZero() { // CHECK-MESSAGES: [[@LINE-1]]:10: warning: constructing string from nullptr is undefined behaviour } +void TestExplicitAllocator() { + std::allocator a; + + std::string s1('x', 5, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: string constructor parameters are probably swapped; expecting string(count, character) [bugprone-string-constructor] + // CHECK-FIXES: std::string s1(5, 'x', a); + std::string s2(0, 'x', a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: constructor creating an empty string + std::string s3(-4, 'x', a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: negative value used as length parameter + std::string s4(0x1000000, 'x', a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: suspicious large length parameter + + std::string q0("test", 0, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: constructor creating an empty string + std::string q1(kText, -4, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: negative value used as length parameter + std::string q2("test", 200, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: length is bigger than string literal size + std::string q3(kText3, 0x1000000, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: suspicious large length parameter + + std::string r1("test", 1, 0, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: constructor creating an empty string + std::string r2("test", 0, -4, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: negative value used as length parameter + std::string r3("test", -4, 1, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: negative value used as position of the first character parameter + std::string r4("test", 0, 0x1000000, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: suspicious large length parameter + std::string r5("test", 0, 5, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: length is bigger than string literal size + std::string r6("test", 3, 2, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: length is bigger than remaining string literal size + std::string r7("test", 4, 1, a); + // CHECK-MESSAGES: [[@LINE-1]]:15: warning: position of the first character parameter is bigger than string literal character range +} + void Valid() { std::string empty(); std::string str(4, 'x'); @@ -132,6 +170,13 @@ void Valid() { std::string s8("test", 3, 1); std::string s9("te" "st", 1, 2); + std::allocator a; + std::string sa1(4, 'x', a); + std::string sa2("test", 4, a); + std::string sa3("test", 3, a); + std::string sa4("test", 0, 4, a); + std::string sa5("test", 3, 1, a); + std::string_view emptyv(); std::string_view sv1("test", 4); std::string_view sv2("test", 3); diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-vararg.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-vararg.cpp index 3f73d1de333f4..1a5a5fb7dd93c 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-vararg.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/pro-type-vararg.cpp @@ -57,6 +57,12 @@ void ignoredBuiltinsTest(void *ptr) { (void)__builtin_fpclassify(0, 0, 0, 0, 0, 0.f); (void)__builtin_isinf_sign(0.f); (void)__builtin_prefetch(nullptr); + + // GH#178629: Type-generic builtins should not warn. + (void)__builtin_clzg(1u); + (void)__builtin_ctzg(1u); + (void)__builtin_popcountg(1u); + (void)__builtin_bswapg(1u); } // Some implementations of __builtin_va_list and __builtin_ms_va_list desugared diff --git a/clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions-cxx20.cpp b/clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions-cxx20.cpp index 1a49883dad100..3b7883ec80a56 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions-cxx20.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions-cxx20.cpp @@ -14,14 +14,14 @@ void positive(std::string_view sv, std::wstring_view wsv) { // [u8|u16|32]string([u8|u16|32]string_view) // foo_u8sv(42, std::u8string(u8"Hello, world"), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: redundant conversion to 'std::u8string' (aka 'basic_string') and then back to 'std::u8string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:16: warning: redundant conversion to 'std::u8string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_u8sv(42, u8"Hello, world", 3.14); foo_u16sv(42, std::u16string(u"Hello, world"), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:17: warning: redundant conversion to 'std::u16string' (aka 'basic_string') and then back to 'std::u16string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:17: warning: redundant conversion to 'std::u16string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_u16sv(42, u"Hello, world", 3.14); foo_u32sv(42, std::u32string(U"Hello, world"), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:17: warning: redundant conversion to 'std::u32string' (aka 'basic_string') and then back to 'std::u32string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:17: warning: redundant conversion to 'std::u32string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_u32sv(42, U"Hello, world", 3.14); } diff --git a/clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions.cpp b/clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions.cpp index bfd5521b39d72..69365a064c611 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/performance/string-view-conversions.cpp @@ -46,52 +46,56 @@ void positive(std::string_view sv, std::wstring_view wsv) { // string(string_view) // foo_sv(42, std::string(sv), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'std::string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_sv(42, sv, 3.14); foo_sv(42, std::string("Hello, world"), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'std::string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] + // CHECK-FIXES: foo_sv(42, "Hello, world", 3.14); + + foo_sv(42, std::string( ( "Hello, world" ) ), 3.14); + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_sv(42, "Hello, world", 3.14); // TODO: support for ""sv literals foo_sv(42, "Hello, world"s, 3.14); foo_sv(42, std::string{"Hello, world"}, 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'std::string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_sv(42, "Hello, world", 3.14); const char *ptr = "Hello, world"; foo_sv(42, std::string(ptr), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'std::string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_sv(42, ptr, 3.14); char arr[] = "Hello, world"; foo_sv(42, std::string(arr), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'std::string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_sv(42, arr, 3.14); foo_sv(42, std::string(foo_sv(42)), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'std::string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_sv(42, foo_sv(42), 3.14); std::string s = "hello"; foo_sv(42, std::string(s), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'std::string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_sv(42, s, 3.14); foo_sv(42, std::string{s}, 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'std::string_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:14: warning: redundant conversion to 'std::string' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_sv(42, s, 3.14); // wstring(wstring_view) // foo_wsv(42, std::wstring(wsv), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:15: warning: redundant conversion to 'std::wstring' (aka 'basic_string') and then back to 'std::wstring_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:15: warning: redundant conversion to 'std::wstring' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_wsv(42, wsv, 3.14); const wchar_t *wptr = L"Hello, world"; foo_wsv(42, std::wstring(wptr), 3.14); - // CHECK-MESSAGES: :[[@LINE-1]]:15: warning: redundant conversion to 'std::wstring' (aka 'basic_string') and then back to 'std::wstring_view' (aka 'basic_string_view') [performance-string-view-conversions] + // CHECK-MESSAGES: :[[@LINE-1]]:15: warning: redundant conversion to 'std::wstring' (aka 'basic_string') and then back to 'basic_string_view>' [performance-string-view-conversions] // CHECK-FIXES: foo_wsv(42, wptr, 3.14); } diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/suspicious-call-argument-option.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/suspicious-call-argument-option.cpp new file mode 100644 index 0000000000000..7788feef8ce2c --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/suspicious-call-argument-option.cpp @@ -0,0 +1,7 @@ +// RUN: %check_clang_tidy %s readability-suspicious-call-argument %t \ +// RUN: -config="{CheckOptions: {readability-suspicious-call-argument.Abbreviations: 'crash='}}" -- -std=c++11-or-later + +void f() {} +// CHECK-MESSAGES: warning: Invalid abbreviation configuration 'crash=', ignoring. + +// TODO: Add testcases for other options diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/suspicious-call-argument.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/suspicious-call-argument.cpp index 27db92be21f20..27c007ea278b2 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/suspicious-call-argument.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/suspicious-call-argument.cpp @@ -1,4 +1,4 @@ -// RUN: %check_clang_tidy %s readability-suspicious-call-argument %t -- -- -std=c++11 +// RUN: %check_clang_tidy %s readability-suspicious-call-argument %t -- -- -std=c++11-or-later void foo_1(int aaaaaa, int bbbbbb) {} diff --git a/clang/AreaTeamMembers.txt b/clang/AreaTeamMembers.txt index 2928943f47533..44b1f2cc41503 100644 --- a/clang/AreaTeamMembers.txt +++ b/clang/AreaTeamMembers.txt @@ -8,7 +8,7 @@ aaron@aaronballman.com (email), AaronBallman (Discourse), AaronBallman (GitHub), Secretary --------- Reid Kleckner -rnk@google.com (email), rnk (Discourse), rnk (GitHub), rnk (Discord) +rnk@llvm.org (email), rnk (Discourse), rnk (GitHub), rnk (Discord) Other Members ------------- diff --git a/clang/Maintainers.rst b/clang/Maintainers.rst index d3fc249774be4..85a0618a99c4d 100644 --- a/clang/Maintainers.rst +++ b/clang/Maintainers.rst @@ -61,9 +61,6 @@ Clang MLIR generation Analysis & CFG ~~~~~~~~~~~~~~ -| Dmitri Gribenko -| gribozavr\@gmail.com (email), gribozavr (Phabricator), gribozavr (GitHub) - | Yitzhak Mandelbaum | yitzhakm\@google.com (email), ymandel (Phabricator), ymand (GitHub) @@ -247,14 +244,12 @@ The following people are responsible for decisions involving ABI. Itanium ABI ~~~~~~~~~~~ -| John McCall -| rjmccall\@apple.com (email), rjmccall (Phabricator), rjmccall (GitHub) Microsoft ABI ~~~~~~~~~~~~~ | Reid Kleckner -| rnk\@google.com (email), rnk (Phabricator), rnk (GitHub) +| rnk\@llvm.org (email), rnk (GitHub), rnk (Discourse), rnk (Discord), rnk (Phabricator) ARM EABI @@ -298,14 +293,11 @@ CMake integration | Petr Hosek | phosek\@google.com (email), phosek (Phabricator), petrhosek (GitHub) -| John Ericson -| git\@johnericson.me (email), Ericson2314 (Phabricator), Ericson2314 (GitHub) - General Windows support ~~~~~~~~~~~~~~~~~~~~~~~ | Reid Kleckner -| rnk\@google.com (email), rnk (Phabricator), rnk (GitHub) +| rnk\@llvm.org (email), rnk (GitHub), rnk (Discourse), rnk (Discord), rnk (Phabricator) Incremental compilation, REPLs, clang-repl @@ -346,8 +338,8 @@ C++ Defect Reports Objective-C/C++ conformance ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -| John McCall -| rjmccall\@apple.com (email), rjmccall (Phabricator), rjmccall (GitHub) +| Akira Hatanaka +| ahatanak\@gmail.com, ahatanak (GitHub), ahatanak4220 (Discord), ahatanak (Discourse) OpenMP conformance @@ -407,5 +399,7 @@ Inactive component maintainers | Chandler Carruth (chandlerc\@gmail.com, chandlerc\@google.com) -- CMake, library layering | Devin Coughlin (dcoughlin\@apple.com) -- Clang static analyzer | Manuel Klimek (klimek\@google.com (email), klimek (Phabricator), r4nt (GitHub)) -- Tooling, AST matchers +| Dmitri Gribenko (gribozavr\@gmail.com (email), gribozavr (Phabricator), gribozavr (GitHub)) -- Analysis & CFG | Tom Honermann (tom\@honermann.net (email), tahonermann (Phabricator), tahonermann (GitHub)) -- Text Encodings -| John McCall (rjmccall\@apple.com (email), rjmccall (Phabricator), rjmccall (GitHub)) -- Clang LLVM IR generation +| John McCall (rjmccall\@apple.com (email), rjmccall (Phabricator), rjmccall (GitHub)) -- Clang LLVM IR generation, Objective-C/C++ conformance, Itanium ABI +| John Ericson (git\@johnericson.me (email), Ericson2314 (Phabricator), Ericson2314 (GitHub)) -- CMake Integration diff --git a/clang/bindings/python/clang/cindex.py b/clang/bindings/python/clang/cindex.py index ec077d4154187..f4d7f4fe68966 100644 --- a/clang/bindings/python/clang/cindex.py +++ b/clang/bindings/python/clang/cindex.py @@ -278,23 +278,25 @@ class SourceLocation(Structure): """ _fields_ = [("ptr_data", c_void_p * 2), ("int_data", c_uint)] - _data = None + _data: tuple[File | None, int, int, int] | None = None - def _get_instantiation(self): + def _get_instantiation(self) -> tuple[File | None, int, int, int]: if self._data is None: f, l, c, o = c_object_p(), c_uint(), c_uint(), c_uint() conf.lib.clang_getInstantiationLocation( self, byref(f), byref(l), byref(c), byref(o) ) if f: - f = File(f) + file = File(f) else: - f = None - self._data = (f, int(l.value), int(c.value), int(o.value)) + file = None + self._data = (file, int(l.value), int(c.value), int(o.value)) return self._data @staticmethod - def from_position(tu, file, line, column): + def from_position( + tu: TranslationUnit, file: File, line: int, column: int + ) -> SourceLocation: """ Retrieve the source location associated with a given file/line/column in a particular translation unit. @@ -302,7 +304,7 @@ def from_position(tu, file, line, column): return conf.lib.clang_getLocation(tu, file, line, column) # type: ignore [no-any-return] @staticmethod - def from_offset(tu, file, offset): + def from_offset(tu: TranslationUnit, file: File, offset: int) -> SourceLocation: """Retrieve a SourceLocation from a given character offset. tu -- TranslationUnit file belongs to @@ -312,36 +314,36 @@ def from_offset(tu, file, offset): return conf.lib.clang_getLocationForOffset(tu, file, offset) # type: ignore [no-any-return] @property - def file(self): + def file(self) -> File | None: """Get the file represented by this source location.""" return self._get_instantiation()[0] @property - def line(self): + def line(self) -> int: """Get the line represented by this source location.""" return self._get_instantiation()[1] @property - def column(self): + def column(self) -> int: """Get the column represented by this source location.""" return self._get_instantiation()[2] @property - def offset(self): + def offset(self) -> int: """Get the file offset represented by this source location.""" return self._get_instantiation()[3] @property - def is_in_system_header(self): + def is_in_system_header(self) -> bool: """Returns true if the given source location is in a system header.""" return bool(conf.lib.clang_Location_isInSystemHeader(self)) - def __eq__(self, other): - return isinstance(other, SourceLocation) and bool( - conf.lib.clang_equalLocations(self, other) - ) + def __eq__(self, other: object) -> bool: + if not isinstance(other, SourceLocation): + return NotImplemented + return bool(conf.lib.clang_equalLocations(self, other)) - def __ne__(self, other): + def __ne__(self, other: object) -> bool: return not self.__eq__(other) def __lt__(self, other: SourceLocation) -> bool: @@ -350,7 +352,7 @@ def __lt__(self, other: SourceLocation) -> bool: def __le__(self, other: SourceLocation) -> bool: return self < other or self == other - def __repr__(self): + def __repr__(self) -> str: if self.file: filename = self.file.name else: @@ -377,11 +379,11 @@ class SourceRange(Structure): # FIXME: Eliminate this and make normal constructor? Requires hiding ctypes # object. @staticmethod - def from_locations(start, end): + def from_locations(start: SourceLocation, end: SourceLocation) -> SourceRange: return conf.lib.clang_getRange(start, end) # type: ignore [no-any-return] @property - def start(self): + def start(self) -> SourceLocation: """ Return a SourceLocation representing the first character within a source range. @@ -389,28 +391,28 @@ def start(self): return conf.lib.clang_getRangeStart(self) # type: ignore [no-any-return] @property - def end(self): + def end(self) -> SourceLocation: """ Return a SourceLocation representing the last character within a source range. """ return conf.lib.clang_getRangeEnd(self) # type: ignore [no-any-return] - def __eq__(self, other): - return isinstance(other, SourceRange) and bool( - conf.lib.clang_equalRanges(self, other) - ) + def __eq__(self, other: object) -> bool: + if not isinstance(other, SourceRange): + return NotImplemented + return bool(conf.lib.clang_equalRanges(self, other)) - def __ne__(self, other): + def __ne__(self, other: object) -> bool: return not self.__eq__(other) - def __contains__(self, other): + def __contains__(self, other: object) -> bool: """Useful to detect the Token/Lexer bug""" if not isinstance(other, SourceLocation): return False return self.start <= other <= self.end - def __repr__(self): + def __repr__(self) -> str: return "" % (self.start, self.end) diff --git a/clang/bindings/python/tests/cindex/test_location.py b/clang/bindings/python/tests/cindex/test_location.py index 8d43d5012321a..35652782cf59d 100644 --- a/clang/bindings/python/tests/cindex/test_location.py +++ b/clang/bindings/python/tests/cindex/test_location.py @@ -168,4 +168,4 @@ def test_equality(self): self.assertEqual(location1, location1_2) self.assertNotEqual(location1, location2) self.assertNotEqual(location1, file2_location1) - self.assertNotEqual(location1, "foo") + self.assertFalse(location1 == "foo") diff --git a/clang/bindings/python/tests/cindex/test_source_range.py b/clang/bindings/python/tests/cindex/test_source_range.py index f1f2694b5820c..23589453d79d0 100644 --- a/clang/bindings/python/tests/cindex/test_source_range.py +++ b/clang/bindings/python/tests/cindex/test_source_range.py @@ -95,4 +95,4 @@ def test_equality(self): self.assertEqual(r1, r1) self.assertEqual(r1, r1_2) self.assertNotEqual(r1, r2) - self.assertNotEqual(r1, "foo") + self.assertFalse(r1 == "foo") diff --git a/clang/cmake/caches/cross-linux-toolchain.cmake b/clang/cmake/caches/cross-linux-toolchain.cmake new file mode 100644 index 0000000000000..8065961f7fcfe --- /dev/null +++ b/clang/cmake/caches/cross-linux-toolchain.cmake @@ -0,0 +1,360 @@ +# cross-linux-toolchain.cmake +# +# Set up a CMakeCache for a cross ARM Linux toolchain build on Windows/Linux hosts. +# +# This cache file can be used to build a multi-target cross toolchain to Linux +# on Windows/Linux platforms. +# +# NOTE: replaces CrossWinToARMLinux.cmake +# +# NOTE: the build requires a development ARM Linux root filesystem to use +# proper target platform depended library and header files. +# +# The build generates a proper clang configuration file with stored +# --sysroot argument for specified target triple. Also it is possible +# to specify configuration path via CMake arguments, such as +# -DCLANG_CONFIG_FILE_USER_DIR= +# and/or +# -DCLANG_CONFIG_FILE_SYSTEM_DIR= +# +# See more details here: https://clang.llvm.org/docs/UsersManual.html#configuration-files +# +# Configure: +# cmake -G Ninja \ +# -DTOOLCHAIN_TARGET_TRIPLE=aarch64-unknown-linux-gnu \ +# -DTOOLCHAIN_TARGET_SYSROOTFS= \ +# -DTOOLCHAIN_SHARED_LIBS=OFF \ +# -DCMAKE_INSTALL_PREFIX=../install \ +# -DCMAKE_CXX_FLAGS="-D__OPTIMIZE__" \ +# -DREMOTE_TEST_HOST="" \ +# -DREMOTE_TEST_USER="" \ +# -C /llvm-project/clang/cmake/caches/cross-linux-toolchain.cmake \ +# /llvm-project/llvm +# Build: +# cmake --build . --target install +# Tests: +# cmake --build . --target check-llvm +# cmake --build . --target check-clang +# cmake --build . --target check-lld +# cmake --build . --target check-compiler-rt- +# cmake --build . --target check-cxxabi- +# cmake --build . --target check-unwind- +# cmake --build . --target check-cxx- +# +# The custom parameters: +# TOOLCHAIN_TARGET_TRIPLE (default: aarch64-unknown-linux-gnu) - a list of target triples to support +# TOOLCHAIN_TARGET_SYSROOTFS- - sysroot for the specific target triple (must be matched TOOLCHAIN_TARGET_TRIPLE) +# TOOLCHAIN_TARGET_SYSROOTFS - sysroot for other targets. +# TOOLCHAIN_TARGET_COMPILER_FLAGS- +# TOOLCHAIN_TARGET_COMPILER_FLAGS +# TOOLCHAIN_TARGET_LINKER_FLAGS- +# TOOLCHAIN_TARGET_LINKER_FLAGS +# TOOLCHAIN_SHARED_LIBS (default: OFF) +# TOOLCHAIN_STATIC_LIBS (default: NOT DEFINED) +# TOOLCHAIN_USE_STATIC_LIBS (default: ON) +# + + +# LLVM_PROJECT_DIR is the path to the llvm-project directory. +# The right way to compute it would probably be to use "${CMAKE_SOURCE_DIR}/../", +# but CMAKE_SOURCE_DIR is set to the wrong value on earlier CMake versions +# that we still need to support (for instance, 3.10.2). +get_filename_component(LLVM_PROJECT_DIR + "${CMAKE_CURRENT_LIST_DIR}/../../../" + ABSOLUTE) +# Store the passed defs to use them later. +get_cmake_property(vars_ VARIABLES) + +# Avoid searching for the python3 interpreter during the runtimes configuration for the cross builds. +# It starts searching the python3 package using the target's sysroot path, that usually is not compatible with the build host. +find_package(Python3 COMPONENTS Interpreter) + +# Allow override with the custom values. +if(NOT DEFINED DEFAULT_TEST_EXECUTOR) + set(DEFAULT_TEST_EXECUTOR "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/libcxx/utils/ssh.py\\\" --host=${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}") +endif() + +if (NOT DEFINED LLVM_ENABLE_ASSERTIONS) + set(LLVM_ENABLE_ASSERTIONS ON CACHE BOOL "") +endif() +if (NOT DEFINED LLVM_ENABLE_PROJECTS) + set(LLVM_ENABLE_PROJECTS "clang;clang-tools-extra;lld" CACHE STRING "") +endif() +if (NOT DEFINED LLVM_ENABLE_RUNTIMES) + set(LLVM_ENABLE_RUNTIMES "compiler-rt;libunwind;libcxxabi;libcxx" CACHE STRING "") +endif() + +#Note: this is a list by default +if (NOT DEFINED TOOLCHAIN_TARGET_TRIPLE) + set(TOOLCHAIN_TARGET_TRIPLE "aarch64-unknown-linux-gnu") +endif() + +#NOTE: we must normalize specified target triple to a fully specified triple, +# including the vendor part. It is necessary to synchronize the runtime library +# installation path and operable target triple by Clang to get a correct runtime +# path through `-print-runtime-dir` Clang option. +function(norm_triple name triple abi) + string(REPLACE "-" ";" t_ "${name}") + list(LENGTH t_ tlen_) + if (tlen_ LESS 3) + message(FATAL_ERROR "invalid target triple ${name}") + endif() + # We suppose missed vendor's part. + if (tlen_ LESS 4) + list(INSERT t_ 1 "unknown") + endif() + list(GET t_ 3 abi_) + string(REPLACE ";" "-" t_ "${t_}") + + set(${triple} "${t_}" PARENT_SCOPE) + set(${abi} ${abi_} PARENT_SCOPE) +endfunction() + +message(STATUS "Toolchain target triples: ${TOOLCHAIN_TARGET_TRIPLE}") + +# Build the shared libraries for libc++/libc++abi/libunwind. +if (NOT DEFINED TOOLCHAIN_SHARED_LIBS) + set(TOOLCHAIN_SHARED_LIBS OFF) +endif() + +# Enable usage of the static libunwind and libc++abi libraries. +if (NOT DEFINED TOOLCHAIN_USE_STATIC_LIBS) + set(TOOLCHAIN_USE_STATIC_LIBS ON) +endif() + +if (NOT DEFINED CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE "Release" CACHE STRING "") +endif() + +if (NOT DEFINED CMAKE_MSVC_RUNTIME_LIBRARY AND WIN32) + #Note: Always specify MT DLL for the LLDB build configurations on Windows host. + if (CMAKE_BUILD_TYPE STREQUAL "Debug") + set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreadedDebugDLL" CACHE STRING "") + else() + set(CMAKE_MSVC_RUNTIME_LIBRARY "MultiThreadedDLL" CACHE STRING "") + endif() + # Grab all ucrt/vcruntime related DLLs into the binary installation folder. + set(CMAKE_INSTALL_UCRT_LIBRARIES ON CACHE BOOL "") +endif() + +# Set up RPATH for the target runtime/builtin libraries. +# See some details here: https://reviews.llvm.org/D91099 +if (NOT DEFINED RUNTIMES_INSTALL_RPATH) + set(RUNTIMES_INSTALL_RPATH "\$ORIGIN/../lib;${CMAKE_INSTALL_PREFIX}/lib") +endif() + +set(CMAKE_CL_SHOWINCLUDES_PREFIX "Note: including file: " CACHE STRING "") + +# Set the first target in the list as the default target. +# (Allow custom default targets) +if (NOT DEFINED LLVM_DEFAULT_TARGET_TRIPLE) + list(GET TOOLCHAIN_TARGET_TRIPLE 0 LLVM_DEFAULT_TARGET_TRIPLE) + set(LLVM_DEFAULT_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}" CACHE STRING "") +endif() +string(REPLACE "-" ";" t_ "${LLVM_DEFAULT_TARGET_TRIPLE}") +list(GET t_ 0 LLVM_TARGET_ARCH) + +# Clang configuration. +set(CLANG_DEFAULT_CXX_STDLIB "libc++" CACHE STRING "") +set(CLANG_DEFAULT_LINKER "lld" CACHE STRING "") +set(CLANG_DEFAULT_OBJCOPY "llvm-objcopy" CACHE STRING "") +set(CLANG_DEFAULT_RTLIB "compiler-rt" CACHE STRING "") +set(CLANG_DEFAULT_UNWINDLIB "libunwind" CACHE STRING "") + +# +# Configure the builtin targets. +# +set(LLVM_BUILTIN_TARGETS "${TOOLCHAIN_TARGET_TRIPLE}" CACHE STRING "") + +foreach (target ${LLVM_BUILTIN_TARGETS}) + set(BUILTINS_${target}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") + set(BUILTINS_${target}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") + set(BUILTINS_${target}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") + set(BUILTINS_${target}_LLVM_CMAKE_DIR "${LLVM_PROJECT_DIR}/llvm/cmake/modules" CACHE PATH "") + + if (DEFINED TOOLCHAIN_TARGET_COMPILER_FLAGS) + foreach(lang C;CXX;ASM) + set(BUILTINS_${target}_CMAKE_${lang}_FLAGS "${TOOLCHAIN_TARGET_COMPILER_FLAGS}" CACHE STRING "") + endforeach() + endif() + foreach(type SHARED;MODULE;EXE) + set(BUILTINS_${target}_CMAKE_${type}_LINKER_FLAGS "-fuse-ld=lld" CACHE STRING "") + endforeach() +endforeach() + +# +# Configure all runtime targets. +# +set(LLVM_RUNTIME_TARGETS "${TOOLCHAIN_TARGET_TRIPLE}" CACHE STRING "") +set(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR ON CACHE BOOL "") + +foreach(target ${LLVM_RUNTIME_TARGETS}) + norm_triple(${target} triple_ abi_) + + if (DEFINED "TOOLCHAIN_TARGET_SYSROOTFS-${target}") + set(sysroot_ "${TOOLCHAIN_TARGET_SYSROOTFS-${target}}") + elseif (DEFINED TOOLCHAIN_TARGET_SYSROOTFS) + set(sysroot_ ${TOOLCHAIN_TARGET_SYSROOTFS}) + endif() + + file(REMOVE "${CMAKE_BINARY_DIR}/bin/${triple_}.cfg") + + if (DEFINED sysroot_) + message(STATUS "Toolchain target sysroot: ${target}: ${sysroot_}") + # Store the --sysroot argument for the compiler-rt test flags. + set(sysroot_flags --sysroot='${sysroot_}') + # Generate the clang configuration file for the specified target triple and store --sysroot in there. + #Note: we use normalized target triple for the configuration file name. + file(APPEND "${CMAKE_BINARY_DIR}/bin/${triple_}.cfg" ${sysroot_flags} "\n") + endif() + + # Pass a list of enabled runtimes to the runtime. + set(RUNTIMES_${target}_LLVM_ENABLE_RUNTIMES "${LLVM_ENABLE_RUNTIMES}" CACHE STRING "") + + set(RUNTIMES_${target}_CMAKE_SYSTEM_NAME "Linux" CACHE STRING "") + set(RUNTIMES_${target}_CMAKE_INSTALL_RPATH "${RUNTIMES_INSTALL_RPATH}" CACHE STRING "") + set(RUNTIMES_${target}_CMAKE_BUILD_WITH_INSTALL_RPATH ON CACHE BOOL "") + + if (DEFINED TOOLCHAIN_TARGET_COMPILER_FLAGS OR DEFINED TOOLCHAIN_TARGET_COMPILER_FLAGS-${target}) + message(STATUS "Toolchain target compiler flags: ${target}: ${TOOLCHAIN_TARGET_COMPILER_FLAGS-${target}}") + foreach(lang C;CXX;ASM) + set(RUNTIMES_${target}_CMAKE_${lang}_FLAGS "${TOOLCHAIN_TARGET_COMPILER_FLAGS} ${TOOLCHAIN_TARGET_COMPILER_FLAGS-${target}}" CACHE STRING "") + endforeach() + # Update the target clang cofiguration file with these flags. + file(APPEND "${CMAKE_BINARY_DIR}/bin/${triple_}.cfg" ${TOOLCHAIN_TARGET_COMPILER_FLAGS} "\n") + file(APPEND "${CMAKE_BINARY_DIR}/bin/${triple_}.cfg" ${TOOLCHAIN_TARGET_COMPILER_FLAGS-${target}} "\n") + endif() + if (DEFINED TOOLCHAIN_TARGET_LINKER_FLAGS OR DEFINED TOOLCHAIN_TARGET_LINKER_FLAGS-${target}) + message(STATUS "Toolchain target linker flags: ${target}: ${TOOLCHAIN_TARGET_LINKER_FLAGS-${target}}") + foreach(type SHARED;MODULE;EXE) + set(RUNTIMES_${target}_CMAKE_${type}_LINKER_FLAGS "-fuse-ld=lld ${TOOLCHAIN_TARGET_LINKER_FLAGS} ${TOOLCHAIN_TARGET_LINKER_FLAGS-${target}}" CACHE STRING "") + endforeach() + endif() + + if (abi_ MATCHES "(musl|pauthtest)") + set(RUNTIMES_${target}_LIBCXX_HAS_MUSL_LIBC ON CACHE BOOL "") + set(RUNTIMES_${target}_COMPILER_RT_BUILD_BUILTINS OFF CACHE BOOL "") + else() + set(RUNTIMES_${target}_COMPILER_RT_BUILD_BUILTINS ON CACHE BOOL "") + endif() + + set(RUNTIMES_${target}_COMPILER_RT_USE_BUILTINS_LIBRARY ON CACHE BOOL "") + set(RUNTIMES_${target}_COMPILER_RT_BUILD_CRT ON CACHE BOOL "") + + #Note: COMPILER_RT_DEFAULT_TARGET_ONLY must be off for COMPILER_RT_DEFAULT_TARGET_TRIPLE. + set(RUNTIMES_${target}_COMPILER_RT_DEFAULT_TARGET_ONLY ON CACHE BOOL "") + + # Required if COMPILER_RT_DEFAULT_TARGET_ONLY is ON + if (RUNTIMES_${target}_COMPILER_RT_DEFAULT_TARGET_ONLY) + set(RUNTIMES_${target}_CMAKE_C_COMPILER_TARGET "${target}" CACHE STRING "") + set(RUNTIMES_${target}_CMAKE_CXX_COMPILER_TARGET "${target}" CACHE STRING "") + endif() + + set(RUNTIMES_${target}_COMPILER_RT_CXX_LIBRARY libcxx CACHE STRING "") + + set(RUNTIMES_${target}_COMPILER_RT_BUILD_SANITIZERS OFF CACHE BOOL "") + set(RUNTIMES_${target}_COMPILER_RT_BUILD_XRAY OFF CACHE BOOL "") + set(RUNTIMES_${target}_COMPILER_RT_BUILD_LIBFUZZER OFF CACHE BOOL "") + set(RUNTIMES_${target}_COMPILER_RT_BUILD_PROFILE OFF CACHE BOOL "") + set(RUNTIMES_${target}_COMPILER_RT_BUILD_MEMPROF OFF CACHE BOOL "") + set(RUNTIMES_${target}_COMPILER_RT_BUILD_ORC OFF CACHE BOOL "") + + set(RUNTIMES_${target}_COMPILER_RT_INCLUDE_TESTS ON CACHE BOOL "") + set(RUNTIMES_${target}_COMPILER_RT_CAN_EXECUTE_TESTS ON CACHE BOOL "") + # The compiler-rt tests disable the clang configuration files during the execution by setting CLANG_NO_DEFAULT_CONFIG=1 + # and drops out the --sysroot from there. Provide it explicity via the test flags here if target sysroot has been specified. + set(RUNTIMES_${target}_COMPILER_RT_TEST_COMPILER_CFLAGS "--stdlib=libc++ ${sysroot_flags}" CACHE STRING "") + + set(RUNTIMES_${target}_LIBUNWIND_USE_COMPILER_RT ON CACHE BOOL "") + + set(RUNTIMES_${target}_LIBCXXABI_USE_LLVM_UNWINDER ON CACHE BOOL "") + set(RUNTIMES_${target}_LIBCXXABI_USE_COMPILER_RT ON CACHE BOOL "") + set(RUNTIMES_${target}_LIBCXXABI_ENABLE_NEW_DELETE_DEFINITIONS OFF CACHE BOOL "") + + set(RUNTIMES_${target}_LIBCXX_USE_COMPILER_RT ON CACHE BOOL "") + set(RUNTIMES_${target}_LIBCXX_CXX_ABI "libcxxabi" CACHE STRING "") #!!! + set(RUNTIMES_${target}_LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS ON CACHE BOOL "") + + + if (DEFINED TOOLCHAIN_SHARED_LIBS) + set(RUNTIMES_${target}_LIBUNWIND_ENABLE_SHARED ${TOOLCHAIN_SHARED_LIBS} CACHE BOOL "") + set(RUNTIMES_${target}_LIBCXXABI_ENABLE_SHARED ${TOOLCHAIN_SHARED_LIBS} CACHE BOOL "") + set(RUNTIMES_${target}_LIBCXX_ENABLE_SHARED ${TOOLCHAIN_SHARED_LIBS} CACHE BOOL "") + endif() + if (DEFINED TOOLCHAIN_STATIC_LIBS) + set(RUNTIMES_${target}_LIBUNWIND_ENABLE_STATIC ${TOOLCHAIN_STATIC_LIBS} CACHE BOOL "") + set(RUNTIMES_${target}_LIBCXXABI_ENABLE_STATIC ${TOOLCHAIN_STATIC_LIBS} CACHE BOOL "") + set(RUNTIMES_${target}_LIBCXX_ENABLE_STATIC ${TOOLCHAIN_STATIC_LIBS} CACHE BOOL "") + endif() + + if (DEFINED TOOLCHAIN_USE_STATIC_LIBS) + set(RUNTIMES_${target}_LIBCXXABI_ENABLE_STATIC_UNWINDER ${TOOLCHAIN_USE_STATIC_LIBS} CACHE BOOL "") + # Merge libc++ and libc++abi libraries into the single libc++ library file. + set(RUNTIMES_${target}_LIBCXX_ENABLE_STATIC_ABI_LIBRARY ${TOOLCHAIN_USE_STATIC_LIBS} CACHE BOOL "") + endif() + + # Forcely disable the libc++ benchmarks on Windows build hosts + # (current benchmark test configuration does not support the cross builds there). + if (WIN32) + set(RUNTIMES_${target}_LIBCXX_INCLUDE_BENCHMARKS OFF CACHE BOOL "") + endif(WIN32) + + set(RUNTIMES_${target}_Python3_EXECUTABLE ${Python3_EXECUTABLE} CACHE PATH "") + + set(RUNTIMES_${target}_LIBUNWIND_TEST_PARAMS_default "${RUNTIMES_${target}_TEST_PARAMS}") + set(RUNTIMES_${target}_LIBCXXABI_TEST_PARAMS_default "${RUNTIMES_${target}_TEST_PARAMS}") + set(RUNTIMES_${target}_LIBCXX_TEST_PARAMS_default "${RUNTIMES_${target}_TEST_PARAMS}") + + # Remote test configuration. + if(DEFINED REMOTE_TEST_HOST) + set(RUNTIMES_${target}_COMPILER_RT_EMULATOR + "\\\"${Python3_EXECUTABLE}\\\" \\\"${LLVM_PROJECT_DIR}/llvm/utils/remote-exec.py\\\" --host=${REMOTE_TEST_USER}@${REMOTE_TEST_HOST}" + CACHE STRING "") + + list(APPEND RUNTIMES_${target}_LIBUNWIND_TEST_PARAMS_default "executor=${DEFAULT_TEST_EXECUTOR}") + list(APPEND RUNTIMES_${target}_LIBCXXABI_TEST_PARAMS_default "executor=${DEFAULT_TEST_EXECUTOR}") + list(APPEND RUNTIMES_${target}_LIBCXX_TEST_PARAMS_default "executor=${DEFAULT_TEST_EXECUTOR}") + endif() + + set(RUNTIMES_${target}_LIBUNWIND_TEST_PARAMS "${RUNTIMES_${target}_LIBUNWIND_TEST_PARAMS_default}" CACHE INTERNAL "") + set(RUNTIMES_${target}_LIBCXXABI_TEST_PARAMS "${RUNTIMES_${target}_LIBCXXABI_TEST_PARAMS_default}" CACHE INTERNAL "") + set(RUNTIMES_${target}_LIBCXX_TEST_PARAMS "${RUNTIMES_${target}_LIBCXX_TEST_PARAMS_default}" CACHE INTERNAL "") + + # Apply all passed LIBCXX|LIBCXXABI|LIBUNWIND|COMPILER_RT parameters to each runtime targets. + # Override the existing variable values by using FORCE. + # Because we don't know a type of the passed vars, use INTERNAL keyword for that. + foreach(v_ ${vars_}) + if(v_ MATCHES "^(LIBCXX|LIBCXXABI|LIBUNWIND|COMPILER_RT)_") + set(RUNTIMES_${target}_${v_} ${${v_}} CACHE INTERNAL "" FORCE) + endif() + endforeach() + unset(sysroot_) + unset(sysroot_flags) +endforeach() + +set(LLVM_INSTALL_TOOLCHAIN_ONLY ON CACHE BOOL "") +set(LLVM_TOOLCHAIN_TOOLS + llvm-ar + llvm-cov + llvm-cxxfilt + llvm-dwarfdump + llvm-lib + llvm-nm + llvm-objdump + llvm-pdbutil + llvm-profdata + llvm-ranlib + llvm-readobj + llvm-size + llvm-symbolizer + CACHE STRING "") + +set(LLVM_DISTRIBUTION_COMPONENTS + clang + lld + LTO + clang-format + builtins + runtimes + ${LLVM_TOOLCHAIN_TOOLS} + CACHE STRING "") diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst index 5ba117c231ad5..378a0c591d747 100644 --- a/clang/docs/ClangFormatStyleOptions.rst +++ b/clang/docs/ClangFormatStyleOptions.rst @@ -5015,7 +5015,8 @@ the configuration (without a prefix: ``Auto``). Keep the form feed character if it's immediately preceded and followed by a newline. Multiple form feeds and newlines within a whitespace range are replaced with a single newline and form feed followed by the remaining - newlines. + newlines. (See + www.gnu.org/prep/standards/html_node/Formatting.html#:~:text=formfeed.) .. _LambdaBodyIndentation: diff --git a/clang/docs/ClangIRCleanupAndEHDesign.md b/clang/docs/ClangIRCleanupAndEHDesign.md new file mode 100644 index 0000000000000..324cf51aa526b --- /dev/null +++ b/clang/docs/ClangIRCleanupAndEHDesign.md @@ -0,0 +1,1427 @@ +# ClangIR Cleanup and Exception Handling Design + +::: {.contents local=""} +::: + +## Overview + +This document describes the design for C++ cleanups and exception +handling representation and lowering in the CIR dialect. The initial CIR +generation will follow the general structure of the cleanup and +exception handling code in Clang's LLVM IR generation. In particular, +we will continue to use the `EHScopeStack` with pushing and popping of +`EHScopeStack::Cleanup` objects to drive the creation of cleanup scopes +within CIR. + +However, the LLVM IR generated by Clang is fundamentally unstructured +and therefore isn't well suited to the goals of CIR. Therefore, we are +proposing a high-level representation that follows MLIR's structured +control flow model. + +The `cir::LowerCFG` pass will lower this high-level representation to a +different form where control flow is block-based and explicit. This form +will more closely resemble the LLVM IR used when Clang is generating +LLVM IR directly. However, this form will still be ABI-agnostic. + +An additional pass will be introduced to lower the flattened form to an +ABI-specific representation. This ABI-specific form will have a direct +correspondence to the LLVM IR exception handling representation for a +given target. + +## High-level CIR representation + +### Normal and EH cleanups + +Scopes that require normal or EH cleanup will be represented using a new +operation, `cir.cleanup.scope`. + +``` +cir.cleanup.scope { + // body region +} cleanup [normal|eh|all] { + // cleanup instructions +} +``` + +Execution begins with the first operation in the body region and +continues according to normal control flow semantics until a terminating +operation (`cir.yield`, `cir.break`, `cir.return`, `cir.continue`) is +encountered or an exception is thrown. + +If the cleanup region is marked as `eh_only`, normal control flow exits +from the body region skip the cleanup region and continue to their +normal destination according to the semantics of the operation. If the +cleanup region is not marked as `eh_only`, normal control flow exits +from the body region must execute the cleanup region before control is +transferred to the destination implied by the operation. + +If a `cir.goto` operation occurs within a cleanup scope, the behavior +depends on the target of the operation. If the target is within the +same cleanup scope, control is transferred to the target block directly. +If the target is not within the cleanup scope, control is transferred to +the cleanup region according to the rules described above for normal +exits before branching to the destination of the goto operation. + +While we do not expect to encounter `cir.br` or `cir.brcond` operations +that exit a cleanup scope, if such a thing did happen, it would follow +the rules described above for `cir.goto` operations. + +The `cir.indirect_br` operation is not permitted within a cleanup scope. + +When an exception is thrown from within a cleanup scope and not caught +within the scope, the cleanup region must be executed before handling of +the exception continues. If the cleanup scope is nested within another +cleanup scope, the cleanup region of the inner scope is executed, +followed by the cleanup region of the outer scope, and handling +continues according to these rules. If the cleanup scope is nested +within a try operation, the cleanup region is executed before control is +transferred to the catch handlers. If an exception is thrown from within +a cleanup region that is not nested within either another cleanup region +or a try operation, the cleanup region is executed and then exception +unwinding continues as if a `cir.resume` operation had been executed. + +If a `cir.resume` operation occurs within a cleanup scope, for example, +if the scope contains a try operation with uncaught exception types, the +`cir.resume` operation will unwind to the cleanup region of the enclosing +cleanup scope. + +Note that this design eliminates the need for synthetic try operations, +such as were used to represent calls within a cleanup scope in the +ClangIR incubator project. + +#### Implementation notes + +The `cir.cleanup.scope` must be created when we call `pushCleanup`. We +will need to set the insertion point at that time. When each cleanup +block is popped, we will need to set the insertion point to immediately +following the cleanup scope operation. If `forceCleanups()` is called, +it will pop cleanup blocks, which is good. + +#### Example: Automatic storage object cleanup + +**C++** + +``` c++ +void someFunc() { + SomeClass c; + c.doSomething(); +} +``` + +**CIR** + +``` +cir.func @someFunc() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.call @_ZN9SomeClassC1Ev(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @_ZN9SomeClass11doSomethingEv(%0) : (!cir.ptr) -> () + cir.yield + } cleanup normal { + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} +``` + +In this example, we create an instance of `SomeClass` which has a +constructor and a destructor. If an exception occurs within the +constructor call, it unwinds without any handling in this function. The +cleanup scope is not entered in that case. Once the object has been +constructed, we enter a cleanup scope which continues until the object +goes out of scope, in this case for the remainder of the function. + +If an exception is thrown from within the `doSomething()` function, we +execute the cleanup region, calling the `SomeClass` destructor before +continuing to unwind the exception. If the call to `doSomething()` +completes successfully, the object goes out of scope and we execute the +cleanup region, calling the destructor, before continuing to the return +operation. + +#### Example: Multiple automatic objects + +**C++** + +``` c++ +void someFunc() { + SomeClass c; + SomeClass c2; + c.doSomething(); + SomeClass c3; + c3.doSomething(); +} +``` + +**CIR** + +``` +cir.func @someFunc() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + %1 = cir.alloca !rec_SomeClass, !cir.ptr, ["c2", init] + %2 = cir.alloca !rec_SomeClass, !cir.ptr, ["c3", init] + cir.call @_ZN9SomeClassC1Ev(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @_ZN9SomeClassC1Ev(%1) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @_ZN9SomeClass11doSomethingEv(%0) : (!cir.ptr) -> () + cir.call @_ZN9SomeClassC1Ev(%2) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @_ZN9SomeClass11doSomethingEv(%2) : (!cir.ptr) -> () + cir.yield + } cleanup normal { + cir.call @_ZN9SomeClassD1Ev(%2) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } cleanup normal { + cir.call @_ZN9SomeClassD1Ev(%1) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } cleanup normal { + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} +``` + +In this example, we have three objects with automatic storage duration. +The destructor must be called for each object that has been constructed, +and the destructors must be called in reverse order of object creation. +We guarantee that by creating nested cleanup scopes as each object is +constructed. + +Normal execution control flows through the body region of each of the +nested cleanup scopes until the body of the innermost scope. Next, the +cleanup scopes are visited, calling the destructor once in each cleanup +scope, in reverse order of the object construction. + +#### Implementation notes + +Branch through cleanups will be handled during flattening. In the +structured CIR representation, an operation like `cir.break`, +`cir.return`, or `cir.continue` has well-defined behavior. We will need +to define the semantics such that they include visiting the cleanup +region before continuing to their currently defined destination. + +#### Example: Branch through cleanup + +**C++** + +``` c++ +int someFunc() { + int i = 0; + while (true) { + SomeClass c; + if (i == 3) + continue; + if (i == 7) + break; + i = c.get(); + } + return i; +} +``` + +**CIR** + +``` +cir.func @someFunc() -> !s32i { + %0 = cir.alloca !s32i, !cir.ptr, ["__retval"] + %1 = cir.alloca !s32i, !cir.ptr, ["i", init] + %2 = cir.const #cir.int<0> : !s32i + cir.store align(4) %2, %1 : !s32i, !cir.ptr + cir.scope { + cir.while { + %5 = cir.const #true + cir.condition(%5) + } do { + cir.scope { + %5 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.call @_ZN9SomeClassC1Ev(%5) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.scope { // This is a scope for the `if`, unrelated to cleanups + %7 = cir.load align(4) %1 : !cir.ptr, !s32i + %8 = cir.const #cir.int<3> : !s32i + %9 = cir.cmp(eq, %7, %8) : !s32i, !cir.bool + cir.if %9 { + cir.continue // This implicitly branches through the cleanup region + } + } + cir.scope { // This is a scope for the `if`, unrelated to cleanups + %7 = cir.load align(4) %1 : !cir.ptr, !s32i + %8 = cir.const #cir.int<7> : !s32i + %9 = cir.cmp(eq, %7, %8) : !s32i, !cir.bool + cir.if %9 { + cir.break // This implicitly branches through the cleanup region + } + } + %6 = cir.call @_ZN9SomeClass3getEv(%5) : (!cir.ptr) -> !s32i + cir.store align(4) %6, %1 : !s32i, !cir.ptr + cir.yield + } cleanup normal { + cir.call @_ZN9SomeClassD1Ev(%5) : (!cir.ptr) -> () + cir.yield + } + } + cir.yield + } + } + %3 = cir.load align(4) %1 : !cir.ptr, !s32i + cir.store %3, %0 : !s32i, !cir.ptr + %4 = cir.load %0 : !cir.ptr, !s32i + cir.return %4 : !s32i +} +``` + +In this example we have a cleanup scope inside the body of a +`while-loop`, and multiple instructions that may exit the loop body with +different destinations. When the `cir.continue` operation is executed, +it will transfer control to the cleanup region, which calls the object +destructor before transferring control to the while condition region +according to the semantics of the `cir.continue` operation. + +When the `cir.break` operation is executed, it will transfer control to +the cleanup region, which calls the object destructor before +transferring control to the operation following the while loop according +to the semantics of the `cir.break` operation. + +If neither the `cir.continue` or `cir.break` operations are executed +during an iteration of the loop, when the end of the cleanup scope's +body region is reached, control will be transferred to the cleanup +region, which calls the object destructor before transferring control to +the next operation following the cleanup scope, in this case falling +through to the `cir.yield` operation to complete the loop iteration. + +This control flow is implicit in the semantics of the CIR operations at +this point. When this CIR is flattened, explicit branches and a switch +on destination slots will be created, matching the LLVM IR control flow +for cleanup block sharing. + +#### Example: EH-only cleanup + +**C++** + +``` c++ +class Base { +public: + Base(); + ~Base(); +}; + +class Derived : public Base { +public: + Derived() : Base() { f(); } + ~Derived(); +}; +``` + +**CIR** + +``` +cir.func @_ZN7DerivedC2Ev(%arg0: !cir.ptr) { + %0 = cir.alloca !cir.ptr, !cir.ptr>, ["this", init] + cir.store %arg0, %0 : !cir.ptr, !cir.ptr> + %1 = cir.load %0 : !cir.ptr>, !cir.ptr + %2 = cir.base_class_addr %1 : !cir.ptr nonnull [0] -> !cir.ptr + cir.call @_ZN4BaseC2Ev(%2) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call exception @_Z1fv() : () -> () + cir.yield + } cleanup eh { + %3 = cir.base_class_addr %1 : !cir.ptr nonnull [0] -> !cir.ptr + cir.call @_ZN4BaseD2Ev(%3) : (!cir.ptr) -> () + cir.resume + } + cir.return +} +``` + +In this example, the `Derived` constructor calls the `Base` constructor +and then calls a function which may throw an exception. If an exception +is thrown, we must call the `Base` destructor before continuing to +unwind the exception. However, if no exception is thrown, we do not call +the destructor. Therefore, this cleanup handler is marked as eh_only. + +### Try Operations and Exception Handling + +Try-catch blocks will be represented, as they are in the ClangIR +incubator project, using a `cir.try` operation. + +``` +cir.try { + cir.call exception @function() : () -> () + cir.yield +} catch [type #cir.global_view<@_ZTIPf> : !cir.ptr] { + ... + cir.yield +} unwind { + cir.resume +} +``` + +The operation consists of a try region, which contains the operations to +be executed during normal execution, and one or more handler regions, +which represent catch handlers or the fallback unwind for uncaught +exceptions. + +#### Example: Simple try-catch + +**C++** + +``` c++ +void someFunc() { + try { + f(); + } catch (std::exception &e) { + // Do nothing + } +} +``` + +**CIR** + +``` +cir.func @someFunc(){ + cir.scope { + cir.try { + cir.call exception @_Z1fv() : () -> () + cir.yield + } catch [type #cir.global_view<@_ZTISt9exception> : !cir.ptr] { + cir.yield + } unwind { + cir.resume + } + } + cir.return +} +``` + +If the call to `f()` throws an exception that matches the handled type +(`std::exception&`), control will be transferred to the catch handler +for that type, which simply yields, continuing execution immediately +after the try operation. + +If the call to `f()` throws any other type of exception, control will be +transferred to the unwind region, which simply continues unwinding the +exception at the next level, in this case, the handlers (if any) for the +function that called `someFunc()`. + +#### Example: Try-catch with catch all + +**C++** + +``` c++ +void someFunc() { + try { + f(); + } catch (std::exception &e) { + // Do nothing + } catch (...) { + // Do nothing + } +} +``` + +**CIR** + +``` +cir.func @someFunc(){ + cir.scope { + cir.try { + cir.call exception @_Z1fv() : () -> () + cir.yield + } catch [type #cir.global_view<@_ZTISt9exception> : !cir.ptr] { + cir.yield + } catch all { + cir.yield + } + } + cir.return +} +``` + +In this case, if the call to `f()` throws an exception that matches the +handled type (`std::exception&`), everything works exactly as in the +previous example. Control will be transferred to the catch handler for +that type, which simply yields, continuing execution immediately after +the try operation. + +If the call to `f()` throws any other type of exception, control will be +transferred to the catch all region, which also yields, continuing +execution immediately after the try operation. + +#### Example: Try-catch with cleanup + +**C++** + +``` c++ +void someFunc() { + try { + SomeClass c; + c.doSomething(); + } catch (...) { + // Do nothing + } +} +``` + +**CIR** + +``` +cir.func @someFunc(){ + cir.scope { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.try { + cir.call @_ZN9SomeClassC1Ev(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @_ZN9SomeClass11doSomethingEv(%0) : (!cir.ptr) -> () + cir.yield + } cleanup all { + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.yield + } + } catch all { + cir.yield + } + } + cir.return +} +``` + +In this case, an object that requires cleanup is instantiated inside the +try block scope. If the call to `doSomething()` throws an exception, the +cleanup region will be executed before control is transferred to the +catch handler. + +#### Example: Try-catch within a cleanup region + +**C++** + +``` c++ +void someFunc() { + SomeClass c; + try { + c.doSomething(); + } catch (std::exception& e) { + // Do nothing + } +} +``` + +**CIR** + +``` +cir.func @someFunc(){ + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.call @_ZN9SomeClassC1Ev(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.scope { + cir.try { + cir.call @_ZN9SomeClass11doSomethingEv(%0) : (!cir.ptr) -> () + } catch [type #cir.global_view<@_ZTISt9exception> : !cir.ptr] { + cir.yield + } unwind { + cir.resume + } + } + cir.yield + } cleanup all { + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} +``` + +In this case, the object that requires cleanup is instantiated outside +the try block scope, and not all exception types have catch handlers. + +If the call to `doSomething()` throws an exception of type +`std::exception&`, control will be transferred to the catch handler, +which will simply continue execution at the point immediately following +the try operation, and the cleanup handler will be executed when the +cleanup scope is exited normally. + +If the call to `doSomething()` throws any other exception of type, +control will be transferred to the unwind region, which executes +`cir.resume` to continue unwinding the exception. However, the cleanup +region of the cleanup scope will be executed before exception unwinding +continues because we are exiting the scope via the `cir.resume` +operation. + +### Partial Array Cleanup + +Partial array cleanup is a special case because the details of array +construction and deletion are already encapsulated within high-level CIR +operations. When an array of objects is constructed, the constructor for +each object is called sequentially. If one of the constructors throws an +exception, we must call the destructor for each object that was +previously constructed in reverse order of their construction. In the +high-level CIR representation, we have a single operation, +`cir.array.ctor` to represent the array construction. Because the +cleanup needed is entirely within the scope of this operation, we can +represent the cleanup by adding a cleanup region to this operation. + +``` +cir.array.ctor(%0 : !cir.ptr>) { +^bb0(%arg0: !cir.ptr): + cir.call @_ZN9SomeClassC1Ev(%arg0) : (!cir.ptr) -> () + cir.yield +} cleanup { +^bb0(%arg0: !cir.ptr): + cir.call @_ZN9SomeClassD1Ev(%arg0) : (!cir.ptr) -> () + cir.yield +} +``` + +This representation shows how a single instance of the object is +initialized and cleaned up. When the operation is transformed to a +low-level form (during `cir::LoweringPrepare`), these two regions will +be expanded to a loop within a `cir.cleanup.scope` for the +initialization, and a loop within the cleanup scope's cleanup region to +perform the partial array cleanup, as follows + +``` +cir.scope { + %1 = cir.const #cir.int<16> : !u64i + %2 = cir.cast array_to_ptrdecay %0 : !cir.ptr> -> !cir.ptr + %3 = cir.ptr_stride %2, %1 : (!cir.ptr, !u64i) -> !cir.ptr + %4 = cir.alloca !cir.ptr, !cir.ptr>, ["__array_idx"] + cir.store %2, %4 : !cir.ptr, !cir.ptr> + cir.cleanup.scope { + cir.do { + %5 = cir.load %4 : !cir.ptr>, !cir.ptr + cir.call @_ZN9SomeClassC1Ev(%5) : (!cir.ptr) -> () + %6 = cir.const #cir.int<1> : !u64i + %7 = cir.ptr_stride %5, %6 : (!cir.ptr, !u64i) -> !cir.ptr + cir.store %7, %4 : !cir.ptr, !cir.ptr> + cir.yield + } while { + %5 = cir.load %4 : !cir.ptr>, !cir.ptr + %6 = cir.cmp(ne, %5, %3) : !cir.ptr, !cir.bool + cir.condition(%6) + } + } cleanup eh { + cir.while { + %5 = cir.load %4 : !cir.ptr>, !cir.ptr + %6 = cir.cmp(ne, %5, %2) : !cir.ptr, !cir.bool + cir.condition(%6) + } cir.do { + %5 = cir.load %4 : !cir.ptr>, !cir.ptr + %6 = cir.const #cir.int<-1> : !s64i + %7 = cir.ptr_stride %5, %6 : (!cir.ptr, !s64i) -> !cir.ptr + cir.call @_ZN9SomeClassD1Ev(%7) : (!cir.ptr) -> () + cir.store %7, %4 : !cir.ptr, !cir.ptr> + cir.yield + } + } +} +``` + +Here, both the construction and cleanup loops use the same temporary +pointer variable to track their location. If an exception is thrown by +one of the constructor, the `__array_idx` variable will point to the +object that was being constructed when the exception was thrown. If the +exception was thrown during construction of the first object, +`__array_idx` will point to the start of the array, and so no destructor +will be called. If an exception is thrown during the constructor call +for any other object, `__array_idx` will not point to the start of the +array, and so the cleanup region will decrement the pointer, call the +destructor for the previous object, and so on until we reach the +beginning of the array. This corresponds to the way that partial array +destruction is handled in Clang's LLVM IR codegen. + +## CFG Flattening + +Before CIR can be lowered to the LLVM dialect, the CFG must be +flattened. That is, functions must not contain nested regions, and all +blocks in the function must belong to the parent region. This state is +formed by the `cir::FlattenCFG` pass. This pass will need to transform +the high-level CIR representation described above to a flat form where +cleanups and exception handling are explicitly routed through blocks, +which are shared as needed. + +The CIR representation will remain ABI agnostic after the flattening +pass. The flattening pass will implement the semantics for branching +through cleanup regions using the same slot and dispatch mechanism used +in Clang's LLVM IR codegen. + +### Exception Handling + +Flattening the CIR for exception handling, including any cleanups that +must be performed during exception unwinding, requires some specialized +CIR operations. The operations that were used in the ClangIR incubator +project were closely matched to the Itanium exception handling ABI. In +order to achieve a representation that also works well for other ABIs, +the following new operations are being proposed: `cir.eh.initiate`, +`cir.eh.dispatch`, `cir.begin_cleanup`, `cir.end_cleanup`, +`cir.begin_catch`, and `cir.end_catch`. + +Any time a cir.call operation that may throw and exception appears +within the try region of a `cir.try` operation or within the body region +of a `cir.cleanup.scope` with a cleanup region marked as an exception +cleanup, the call will be converted to a `cir.try_call` operation, with +normal and unwind destinations. The first operation in the unwind +destination block must be a `cir.eh.initiate` operation. + + `%eh_token = cir.eh.initiate [cleanup]` + +If this destination includes cleanup code, the cleanup keyword will be +present, and the cleanup code will be executed before the exception is +dispatched to any handlers. The `cir.eh.initiate` operation returns a +value of type `!cir.eh_token`. This is an opaque value that will be used +during ABI-lowering. At this phase, it conceptually represents the +exception that was thrown and is passed as the argument to the +`cir.begin_cleanup`, `cir.begin_catch`, and `cir.eh.dispatch` +operations. + +``` +cir.eh.dispatch %eh_token : !cir.eh_token [ + catch (#cir.global_view<@_ZTIi> : !u32i) : ^bb6 + catch_all : ^bb7 +] + +cir.eh.dispatch %eh_token : !cir.eh_token [ + catch (#cir.global_view<@_ZTIi> : !u32i) : ^bb6 + unwind : ^bb7 +] +``` + +The `cir.eh.dispatch` operation behaves similarly to the LLVM IR switch +instruction. It takes as an argument a token that was returned by a +previous `cir.eh.initiate` operation. It then has a list of key-value +pairs, where the key is either a type identifier, the keyword catch_all, +or the keyword unwind and the value is a block to which execution should +be transferred if the key is matched. Although the example above shows +both the catch_all and unwind keyword, in practice only one or the other +will be present, but the operation is required to have one of these +values. + +When we are unwinding an exception with cleanups, the `cir.eh.initiate` +operation will be marked with the cleanup attribute and will be followed +by a branch to the cleanup block, passing the EH token as an operand to +the block. The cleanup block will begin with a call to +`cir.begin_cleanup` which returns a cleanup token. + +``` +^bb4 (%eh_token : !cir.eh_token): + %cleanup_token = cir.begin_cleanup %eh_token : !cir.eh_token -> !cir.cleanup_token +``` + +This is followed by the operations to perform the cleanup and then a +cir.end_cleanup operation. + + `cir.end_cleanup(%cleanup_token : !cir.cleanup_token)` + +Finally, the cleanup block either branches to a catch dispatch block or +executes a `cir.resume` operation to continue unwinding the exception. + +When an exception is caught, the catch block will receive the eh token +for the exception being caught as an argument, and the first operation +of the catch handling block must be a `cir.begin_catch` operation. + +``` +^bb6 (%token : !cir.eh_token): + %catch_token, %exn_ptr = cir.begin_catch %8 -> (!cir.catch_token, !cir.ptr) +``` + +The `cir.begin_catch` operation returns two values: a new token that +uniquely identify this catch handler, and a pointer to the exception +object. All paths through the catch handler must converge on a single +`cir.end_catch` operation, which marks the end of the handler. + + `cir.end_catch %catch_token` + +The argument to the `cir.end_catch` operation is the token returned by +the `cir.begin_catch` operation. + +#### Example: Try-catch with cleanup + +**C++** + +``` c++ +void someFunc() { + try { + SomeClass c; + c.doSomething(); + } catch (...) { + // Do nothing + } +} +``` + +**High-level CIR** + +``` +cir.func @someFunc(){ + cir.scope { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.try { + cir.call @_ZN9SomeClassC1Ev(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @_ZN9SomeClass11doSomethingEv(%0) : (!cir.ptr) -> () + cir.yield + } cleanup all { + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.yield + } + } catch all { + cir.yield + } + } + cir.return +} +``` + +**Flattened CIR** + +``` +cir.func @someFunc(){ + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.try_call @_ZN9SomeClassC1Ev(%0) ^bb1, ^bb3 : (!cir.ptr) -> () +^bb1 + cir.try_call @_ZN9SomeClass11doSomethingEv(%0) ^bb2, ^bb4 : (!cir.ptr) -> () +^bb2 // Normal cleanup + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.br ^bb8 +^bb3 // EH catch (from entry block) + %1 = cir.eh.initiate : !cir.eh_token + cir.br ^bb6(%1 : !cir.eh_token) +^bb4 // EH cleanup (from ^bb1) + %2 = cir.eh.initiate cleanup : !cir.eh_token + cir.br ^bb5(%2 : !cir.eh_token) +^bb5(%eh_token : !cir.eh_token) + %3 = cir.begin_cleanup(%eh_token : !cir.eh_token) : !cir.cleanup_token + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.end_cleanup(%3 : !cir.cleanup_token) + cir.br ^bb6(%eh_token : !cir.eh_token) +^bb6(%eh_token.1 : !cir.eh_token) // Catch dispatch (from ^bb3 or ^bb4) + cir.eh.dispatch %eh_token.1 : !cir.eh_token [ + catch_all : ^bb7 + ] +^bb7(%eh_token.2 : !cir.eh_token) + %catch.token = cir.begin_catch(%eh_token.2 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb8 +^bb8 // Normal continue (from ^bb2 or ^bb6) + cir.return +} +``` + +In this example, the normal cleanup is performed in a different block +than the EH cleanup. This follows the pattern established by Clang's +LLVM IR codegen. Only the EH cleanup requires `cir.begin_cleanup` and +`cir.end_cleanup` operations. + +If the `SomeClass` constructor throws an exception, it unwinds to an EH +catch block (`^bb3`), which has excecutes a `cir.eh.initiate` operation +before branching to a shared catch dispatch block (`^bb6`). + +If the `doSomething()` function throws an exception, it unwinds to an EH +block `^bb4` that performs cleanup before branching to the shared catch +dispatch block (`^bb5`). + +#### Example: Cleanup with unhandled exception + +**C++** + +``` c++ +void someFunc() { + SomeClass c; + c.doSomething(); +} +``` + +**High-level CIR** + +``` +cir.func @someFunc(){ + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.call @_ZN9SomeClassC1Ev(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @_ZN9SomeClass11doSomethingEv(%0) : (!cir.ptr) -> () + cir.yield + } cleanup all { + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} +``` + +**Flattened CIR** + +``` +cir.func @someFunc(){ + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.call @_ZN9SomeClassC1Ev(%0) : (!cir.ptr) -> () + cir.try_call @_ZN9SomeClass11doSomethingEv(%0) ^bb1, ^bb2 : (!cir.ptr) -> () +^bb1 // Normal cleanup + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.br ^bb4 +^bb2 // EH cleanup (from entry block) + %1 = cir.eh.initiate cleanup : !cir.eh_token + cir.br ^bb3(%1 : !cir.eh_token) +^bb3(%eh_token : !cir.eh_token) // Perform cleanup + %2 = cir.begin_cleanup(%eh_token : !cir.eh_token) : !cir.cleanup_token + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.end_cleanup(%2 : !cir.cleanup_token) + cir.resume // Unwind to caller +^bb4 // Normal continue (from ^bb1) + cir.return +} +``` + +In this example, if `doSomething()` throws an exception, it unwinds to +the EH cleanup block (`^bb2`), which branches to `^bb3` to perform the +cleanup, but because we have no catch handler, we execute `cir.resume` +after the cleanup to unwind to the function that called `someFunc()`. + +#### Example: Shared cleanups + +**C++** + +``` c++ +int someFunc() { + int i = 0; + while (true) { + SomeClass c; + if (i == 3) + continue; + if (i == 7) + break; + i = c.get(); + } + return i; +} +``` + +**CIR** + +``` +cir.func @someFunc() -> !s32i { + %0 = cir.alloca !s32i, !cir.ptr, ["__retval"] + %1 = cir.alloca !s32i, !cir.ptr, ["i", init] + %2 = cir.const #cir.int<0> : !s32i + cir.store align(4) %2, %1 : !s32i, !cir.ptr + cir.scope { + cir.while { + %5 = cir.const #true + cir.condition(%5) + } do { + cir.scope { + %5 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.call @_ZN9SomeClassC1Ev(%5) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.scope { + %7 = cir.load align(4) %1 : !cir.ptr, !s32i + %8 = cir.const #cir.int<3> : !s32i + %9 = cir.cmp(eq, %7, %8) : !s32i, !cir.bool + cir.if %9 { + cir.continue + } + } + cir.scope { + %7 = cir.load align(4) %1 : !cir.ptr, !s32i + %8 = cir.const #cir.int<7> : !s32i + %9 = cir.cmp(eq, %7, %8) : !s32i, !cir.bool + cir.if %9 { + cir.break + } + } + %6 = cir.call @_ZN9SomeClass3getEv(%5) : (!cir.ptr) -> !s32i + cir.store align(4) %6, %1 : !s32i, !cir.ptr + cir.yield + } cleanup all { + cir.call @_ZN9SomeClassD1Ev(%5) : (!cir.ptr) -> () + cir.yield + } + } + cir.yield + } + } + %3 = cir.load align(4) %1 : !cir.ptr, !s32i + cir.store %3, %0 : !s32i, !cir.ptr + %4 = cir.load %0 : !cir.ptr, !s32i + cir.return %4 : !s32i +} +``` + +**Flattened CIR** + +``` +cir.func @someFunc() -> !s32i { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + %1 = cir.alloca !s32i, !cir.ptr, ["__cleanup_dest_slot "] + %2 = cir.alloca !s32i, !cir.ptr, ["__retval"] + %3 = cir.alloca !s32i, !cir.ptr, ["i", init] + %4 = cir.const #cir.int<0> : !s32i + cir.store align(4) %4, %3 : !s32i, !cir.ptr + cir.br ^bb1 +^bb1: // 3 preds: ^bb0, ^bb9, ^bb11 + %5 = cir.const #true + cir.brcond %5 ^bb2, ^bb12 +^bb2: // pred: ^bb1 + cir.call @_ZN9SomeClassC1Ev(%0) : (!cir.ptr) -> () + cir.br ^bb3 +^bb3: // pred: ^bb2 + %6 = cir.load align(4) %3 : !cir.ptr, !s32i + %7 = cir.const #cir.int<3> : !s32i + %8 = cir.cmp(eq, %6, %7) : !s32i, !cir.bool + cir.brcond %8 ^bb4, ^bb5 +^bb4: // pred: ^bb3 + // Set the destination slot and branch through cleanup + %9 = cir.const #cir.int<0> : !s32i + cir.store %9, %1 : !s32i, !cir.ptr + cir.br ^bb9 +^bb5: // pred: ^bb3 + %10 = cir.load align(4) %3 : !cir.ptr, !s32i + %11 = cir.const #cir.int<7> : !s32i + %12 = cir.cmp(eq, %10, %11) : !s32i, !cir.bool + cir.brcond %12 ^bb6, ^bb7 +^bb6: // pred: ^bb5 + // Set the destination slot and branch through cleanup + %13 = cir.const #cir.int<1> : !s32i + cir.store %13, %1 : !s32i, !cir.ptr + cir.br ^bb9 +^bb7: // pred: ^bb5 + %14 = cir.call @_ZN9SomeClass3getEv(%0) : (!cir.ptr) -> !s32i + cir.store align(4) %14, %3 : !s32i, !cir.ptr + cir.br ^bb8 +^bb8: // pred: ^bb7 + // Set the destination slot and branch through cleanup + %15 = cir.const #cir.int<2> : !s32i + cir.store %15, %1 : !s32i, !cir.ptr + cir.br ^bb9 +^bb9: // pred + // Shared cleanup + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + %16 = cir.load align(4) %1 : !cir.ptr, !s32i + cir.switch.flat %16 : !s32i, ^bb10 [ + 0: ^bb1 // continue + 1: ^bb12 // break + 2: ^bb11 // end of loop + ] +^bb10: // preds: ^bb9 + cir.unreachable +^bb11: // pred: ^bb9 + cir.br ^bb1 +^bb12: // pred: ^bb1 + %17 = cir.load align(4) %3 : !cir.ptr, !s32i + cir.store align(4) %17, %2 : !s32i, !cir.ptr + %18 = cir.load align(4) %2 : !cir.ptr, !s32i + cir.return %18 : !s32i +} +``` + +In this example we have a cleanup scope inside the body of a while loop, +and multiple instructions that may exit the loop body with different +destinations. For simplicity, the example is shown without exception +handling. + +When any of the conditions that exit a loop iteration occur (continue, +break, or completion of an iteration), we set a cleanup destination slot +to a unique value and branch to a shared normal cleanup block. That +block performs the cleanup and then compares the cleanup destination +slot value to the set of expected constants and branches to the +corresponding destination. + +For example, when the continue instruction is reached, we set the +cleanup destination slot (`%1`) to zero, branch to the shared cleanup +block (`^bb9`), which calls the `SomeClass` destructor, then uses +`cir.switch.flat` to switch on the cleanup destination slot value and, +finding it to be zero, branches to the loop condition block (`^bb1`). + +If none of the expected values is matched, the `cir.switch.flat` +branches to a block with a `cir.unreachable` operation. This corresponds +to the behavior of Clang's LLVM IR codegen. + +## ABI Lowering + +A new pass will be introduced to lower the flattened representation to +lower the ABI-agnostic flattened CIR representation to an ABI-specific +form. This will be a separate pass from the main CXXABI lowering pass, +which runs before CFG flattening. The ABI lowering pass will introduce +personality functions and ABI-specific exception handling operations. + +This new pass will make use of the `cir::CXXABI` interface class and +ABI-specific subclasses, but it will introduce a new set of interface +methods for use with the exception handling ABI. + +For each supported exception handling ABI, the operations and function +calls used will have a direct correspondence to the LLVM IR instructions +and runtime library functions used for that ABI. The LLVM IR exception +handling model is described in detail here: [LLVM Exception +Handling](https://llvm.org/docs/ExceptionHandling.html). + +A personality function attribute will be added to functions that require +it during the ABI lowering phase. + +### Itanium ABI Lowering + +The Itanium exception handling ABI representation replaces the +`cir.eh.initiate` and `cir.eh.dispatch` operations with a +`cir.eh.landingpad` operation and a series of `cir.compare` and +`cir.brcond` operations to model the correct handling based on type IDs +for the catch handlers. The `cir.begin_cleanup` and `cir.end_cleanup` +operations are simply dropped. The `cir.begin_catch` operation becomes a +call to `__cxa_begin_catch`. The `cir.end_catch` operation becomes a +call to `__cxa_end_catch`. + +The only operation that is specific to Itanium exception handling is +`cir.eh.landingpad`. + + `%exn_ptr_0, %type_id = cir.eh.landingpad [@_ZTISt9exception] : !cir.ptr, !u32i` + +This operation corresponds directly to the LLVM IR landingpad +instruction. It may have a list of type IDs that the handler can catch +(or null for \"catch all\") or it may have the cleanup attribute if the +handler performs cleanup but does not catch any exceptions. + +#### Example: Try-catch with cleanup + +**Flattened CIR** + +``` +cir.func @someFunc(){ + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.try_call @_ZN9SomeClassC1Ev(%0) ^bb1, ^bb3 : (!cir.ptr) -> () +^bb1 + cir.try_call @_ZN9SomeClass11doSomethingEv(%0) ^bb2, ^bb4 : (!cir.ptr) -> () +^bb2 // Normal cleanup + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.br ^bb8 +^bb3 // EH catch (from entry block) + %1 = cir.eh.initiate : !cir.eh_token + cir.br ^bb6(%1 : !cir.eh_token) +^bb4 // EH cleanup (from ^bb1) + %2 = cir.eh.initiate cleanup : !cir.eh_token + cir.br ^bb5(%2 : !cir.eh_token) +^bb5(%eh_token : !cir.eh_token) + %3 = cir.begin_cleanup(%eh_token : !cir.eh_token) : !cir.cleanup_token + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.end_cleanup(%3 : !cir.cleanup_token) + cir.br ^bb6(%eh_token : !cir.eh_token) +^bb6(%eh_token.1 : !cir.eh_token) // Catch dispatch (from ^bb3 or ^bb4) + cir.eh.dispatch %eh_token.1 : !cir.eh_token [ + catch_all : ^bb7 + ] +^bb7(%eh_token.2 : !cir.eh_token) + %catch.token = cir.begin_catch(%eh_token.2 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb8 +^bb8 // Normal continue (from ^bb2 or ^bb6) + cir.return +} +``` + +**ABI-lowered CIR** + +``` +cir.func @someFunc() #personality_fn = @__gxx_personality_v0 { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.try_call @_ZN9SomeClassC1Ev(%0) ^bb1, ^bb3 : (!cir.ptr) -> () +^bb1 + cir.try_call @_ZN9SomeClass11doSomethingEv(%0) ^bb2, ^bb4 : (!cir.ptr) -> () +^bb2 // Normal cleanup + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.br ^bb8 +^bb3 // EH catch (from entry block) + %exn, %type_id = cir.eh.landingpad [null] : (!cir.ptr, !u32i) + cir.br ^bb6(%exn, &type_id : !cir.ptr, !u32i) +^bb4 // EH cleanup (from ^bb1) + %exn.1, %type_id.1 = cir.eh.landingpad cleanup [null] : (!cir.ptr, !u32i) + cir.br ^bb5(%exn, %type_id : !cir.ptr, !u32i) +^bb5(%1: !cir.ptr, %2: !u32i) + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.br ^bb6(%1, %2 : !cir.ptr, !u32i) +^bb6(%3: !cir.ptr, %4: !u32i) // Catch dispatch (from ^bb3 or ^bb4) + cir.br ^bb7(%3, %4 : !cir.ptr, !u32i) +^bb7(%5: !cir.ptr, %6: !u32i) // Catch all handler + %7 = cir.call @__cxa_begin_catch(%5 : !cir.ptr) + cir.call @__cxa_end_catch() + cir.br ^bb8 +^bb8 // Normal continue (from ^bb2 or ^bb6) + cir.return +} +``` + +In this example, if an exception is thrown by the `SomeClass` +constructor, it unwinds to a landing pad block (`^bb3`), which branches +to the shared catch dispatch block (`^bb6`), which branches to the catch +all handler block (`^bb7`). The catch all handler calls +`__cxa_begin_catch` and `__cxa_end_catch` and then continues to the +normal continuation block (`^bb8`). + +#### Example: Try-catch with multiple catch handlers + +**Flattened CIR** + +``` +cir.func @someFunc(){ + cir.try_call @f() ^bb1, ^bb2 +^bb1 + cir.br ^bb7 +^bb2 // EH catch (from entry block) + %1 = cir.eh.initiate : !cir.eh_token + cir.br ^bb3(%1 : !cir.eh_token) +^bb3(%eh_token : !cir.eh_token) // Catch dispatch (from ^bb2) + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch (#cir.global_view<@_ZTIi> : !u32i) : ^bb4 + catch (#cir.global_view<@_ZTIf> : !u32i) : ^bb5 + catch_all : ^bb6 + ] +^bb4(%eh_token.1 : !cir.eh_token) // Catch handler for int exception + %catch.token = cir.begin_catch(%eh_token.1 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb7 +^bb5(%eh_token.2 : !cir.eh_token) // Catch handler for float exception + %catch.token = cir.begin_catch(%eh_token.2 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb7 +^bb6(%eh_token.3 : !cir.eh_token) // Catch all handler + %catch.token = cir.begin_catch(%eh_token.3 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb7 +^bb7 // Normal continue (from ^bb1, ^bb4, ^bb5, or ^bb6) + cir.return +} +``` + +**ABI-lowered CIR** + +``` +cir.func @someFunc() #personality_fn = @__gxx_personality_v0 { + cir.try_call @f() ^bb1, ^bb2 +^bb1 + cir.br ^bb8 +^bb2 // EH catch (from entry block) + %exn, %type_id = cir.eh.landingpad [null] : (!cir.ptr, !u32i) + cir.br ^bb3(%exn, &type_id : !cir.ptr, !u32i) +^bb3(%0: !cir.ptr, %1: !u32i) // Catch compare for int exception + %2 = cir.eh.typeid @_ZTIi : !u32i + %3 = cir.cmp(eq, %1, %2) : !u32i, !cir.bool + cir.brcond %3 ^bb4(%0 : !cir.ptr), ^bb5(%0, %1 : !cir.ptr, !u32i) +^bb4(%4: !cir.ptr, %5: !u32i) // Catch all handler for int exception + %6 = cir.call @__cxa_begin_catch(%4 : !cir.ptr) + cir.call @__cxa_end_catch() + cir.br ^bb8 +^bb5(%7: !cir.ptr, %8: !u32i) // Catch compare for float exception + %9 = cir.eh.typeid @_ZTIf : !u32i + %10 = cir.cmp(eq, %8, %9) : !u32i, !cir.bool + cir.brcond %10 ^bb7(%7 : !cir.ptr), ^bb8(%7 : !cir.ptr) +^bb6(%11: !cir.ptr, %12: !u32i) // Catch all handler for float exception + %13 = cir.call @__cxa_begin_catch(%11 : !cir.ptr) + cir.call @__cxa_end_catch() + cir.br ^bb8 +^bb7(%14: !cir.ptr) // Catch all handler + %15 = cir.call @__cxa_begin_catch(%14 : !cir.ptr) + cir.call @__cxa_end_catch() + cir.br ^bb8 +^bb8 // Normal continue (from ^bb1, ^bb4, ^bb6, or ^bb7) + cir.return +} +``` + +In this example, if an exception is thrown by the `f()` call, it unwinds +to a landing pad block (`^bb2`), which uses the `cir.eh.landingpad` +operation to capture the exception pointer and its type id, then branches +to `^bb3` to begin searching for a catch handler that handles the type id +of the exception. Each catch handler simply consumes the exception by +calling `__cxa_begin_catch` and `__cxa_end_catch` and then continues to +the normal continuation block (`^bb8`). + +### Microsoft C++ ABI Lowering + +The Microsoft C++ exception handling ABI representation drops the +`cir.eh.initiate` operation and replaces the `cir.eh.dispatch` operation +with `cir.eh.catchswitch` operation. The `cir.begin_cleanup` and +`cir.end_cleanup` operations are replaced with `cir.cleanuppad` and +`cir.cleanupret` respectively, and the `cir.begin_catch` and +`cir.end_catch` operations are replaced with `cir.catchpad` and +`cir.catchret`. + +Each of these operations corresponds directly to a similarly named +instruction in LLVM IR and have the same semantics. The first operation +in the unwind destination of a `cir.try_call` must be either +`cir.eh.catchswitch` or `cir.cleanuppad`. + + `%4 = cir.eh.catchswitch within none [^bb2, ^bb3] unwind to caller` + +The `cir.eh.catchswitch` operation takes an operand which specifies the +parent token, which may either be none or the token returned by a +previous `cir.catchpad` operation. This is followed by a list of blocks +which contain catch handlers. Each block in this list must begin with a +`cir.catchpad` operation. Finally, the unwind destination is provided to +specify where excution continues if the exception is not caught by any +of the handlers, with unwind to caller indicating that the unwind is not +handled further in the current function. This operation returns a token +that is used as the operand for `cir.catchpad` operations associated +with this switch. + + `%5 = cir.cleanuppad within none []` + +The `cir.cleanuppad` operation takes an operand which specifies the +parent token, which may either be none or the token returned by a +previous `cir.catchpad` operation. This is followed by a arguments +required by the personality function. In the case of C++ exception +handlers, the personality function will be `__CxxFrameHandler3` and the +argument list will be empty. This operation returns a token that is used +as the operand for the associated `cir.cleanupret` operation. + + `cir.cleanupret from %5 unwind to ^bb7` + +The `cir.cleanupret` operation takes an operand which specifies the +`cir.cleanuppad` operation which is completed by this operation and a +block at which unwinding of the current exception continues (or unwind +to caller if there is no catch handling in the current function). + + `%8 = cir.catchpad within %4 [ptr @"??_R0H@8", i32 0, ptr %e]` + +The `cir.catchpad` operation takes an operand which specifies the parent +token, which must have been return by a previous `cir.catchswitch` +operation. This is followed by a list of arguments, beginning with the +typeid for the type of exception being caught (or null for catch all), +followed by a type info flag value, followed by a pointer to the +in-flight exception. This operation returns a token that is used as the +operand for the associated `cir.catchret` operation or as the parent for +any `cir.catchswitch` or `cir.cleanuppad` operations that are nested +within this catch handler. + + `cir.catchret from %8 to ^bb8` + +The `cir.catchret` operation takes an operand which specifies the +`cir.catchpad` operation which is completed by this operation and a +block at which excution should be resumed. + +#### Example: Try-catch with cleanup + +**Flattened CIR** + +``` +cir.func @someFunc() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.try_call @_ZN9SomeClassC1Ev(%0) ^bb1, ^bb3 : (!cir.ptr) -> () +^bb1 + cir.try_call @_ZN9SomeClass11doSomethingEv(%0) ^bb2, ^bb4 : (!cir.ptr) -> () +^bb2 // Normal cleanup + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.br ^bb8 +^bb3 // EH catch (from entry block) + %1 = cir.eh.initiate : !cir.eh_token + cir.br ^bb6(%1 : !cir.eh_token) +^bb4 // EH cleanup (from ^bb1) + %2 = cir.eh.initiate cleanup : !cir.eh_token + cir.br ^bb5(%2 : !cir.eh_token) +^bb5(%eh_token : !cir.eh_token) + %3 = cir.begin_cleanup(%eh_token : !cir.eh_token) : !cir.cleanup_token + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.end_cleanup(%3 : !cir.cleanup_token) + cir.br ^bb6(%eh_token : !cir.eh_token) +^bb6(%eh_token.1 : !cir.eh_token) // Catch dispatch (from ^bb3 or ^bb4) + cir.eh.dispatch %eh_token.1 : !cir.eh_token [ + catch_all : ^bb7 + ] +^bb7(%eh_token.2 : !cir.eh_token) + %catch.token = cir.begin_catch(%eh_token.2 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb8 +^bb8 // Normal continue (from ^bb2 or ^bb6) + cir.return +} +``` + +**ABI-lowered CIR** + +``` +cir.func @someFunc() #personality_fn = @ __CxxFrameHandler3 { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] + cir.try_call @_ZN9SomeClassC1Ev(%0) ^bb1, ^bb4 : (!cir.ptr) -> () +^bb1 + cir.try_call @_ZN9SomeClass11doSomethingEv(%0) ^bb2, ^bb3 : (!cir.ptr) -> () +^bb2 // Normal cleanup + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.br ^bb6 +^bb3 // EH cleanup (from ^bb1) + %1 = cir.cleanuppad within none : !cir.cleanup_token + cir.call @_ZN9SomeClassD1Ev(%0) : (!cir.ptr) -> () + cir.cleanupret from %1 unwind to ^bb4 +^bb4 // Catch dispatch (from ^bb3 or ^bb4) + %2 = cir.catchswitch within none [^bb5] unwind to caller +^bb5 + %catch.token = cir.catchpad within %2 [null : !cir.ptr] : !cir.catch_token + cir.catchret within %catch.token to ^bb6 +^bb6 // Normal continue (from ^bb2 or ^bb6) + cir.return +} +``` + +#### Example: Try-catch with multiple catch handlers + +**Flattened CIR** + +``` +cir.func @someFunc(){ + cir.try_call @f() ^bb1, ^bb2 +^bb1 + cir.br ^bb7 +^bb2 // EH catch (from entry block) + %1 = cir.eh.initiate : !cir.eh_token + cir.br ^bb3(%1 : !cir.eh_token) +^bb3(%eh_token : !cir.eh_token) // Catch dispatch (from ^bb2) + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch (#cir.global_view<@_ZTIi> : !u32i) : ^bb4 + catch (#cir.global_view<@_ZTIf> : !u32i) : ^bb5 + catch_all : ^bb6 + ] +^bb4(%eh_token.1 : !cir.eh_token) // Catch handler for int exception + %catch.token = cir.begin_catch(%eh_token.1 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb7 +^bb5(%eh_token.2 : !cir.eh_token) // Catch handler for float exception + %catch.token = cir.begin_catch(%eh_token.2 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb7 +^bb6(%eh_token.3 : !cir.eh_token) // Catch all handler + %catch.token = cir.begin_catch(%eh_token.3 : !cir.eh_token) : !cir.catch_token + cir.end_catch(%catch.token : !cir.catch_token) + cir.br ^bb7 +^bb7 // Normal continue (from ^bb1, ^bb4, ^bb5, or ^bb6) + cir.return +} +``` + +**ABI-lowered CIR** + +``` +cir.func @someFunc() #personality_fn = @__CxxFrameHandler3 { + cir.try_call @f() ^bb1, ^bb2 +^bb1 + cir.br ^bb6 +^bb2 // EH catch (from entry block) + %0 = cir.catchswitch within none [^bb3, ^bb4, ^bb5] unwind to caller +^bb3(%0: !cir.ptr) // Catch handler for int exception + %1 = cir.catchpad within %0 [eh.typeid @"??_R0H@8", 0, %0 : (!cir.ptr, !u32i, !cir.ptr)] : !cir.catch_token + cir.catchret from %1 to ^bb6 +^bb4(%2: !cir.ptr) // Catch compare for float exception + %2 = cir.catchpad within %0 [eh.typeid @"??_R0M@8", 0, %0 : (!cir.ptr, !u32i, !cir.ptr)] : !cir.catch_token + cir.catchret from %2 to ^bb6 +^bb5(%3: !cir.ptr) // Catch all handler + %4 = cir.catchpad within %0 [null, 64, null : (!cir.ptr, !u32i, !cir.ptr)] : !cir.catch_token + cir.catchret from %4 to ^bb6 +^bb6 // Normal continue (from ^bb1, ^bb3, ^bb4, or ^bb5) + cir.return +} +``` + +In this example, if an exception is thrown by the `f()` call, it unwinds +to a catch dispatch block (`^bb2`), which uses the `cir.catchswitch` +operation to dispatch to a catch handler (`^bb3`, `^bb4`, or `^bb5`) +based on the type id of the exception. The actual comparisons in this +case will be handled by the personality function, using tables that are +generated from the `cir.catchpad` operations. Each catch handler simply +continues to the normal continuation block (`^bb6`) using the +`cir.catchret` operation. diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 1b4c9ae3003b1..a1bb1bd2467b7 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -43,15 +43,30 @@ C/C++ Language Potentially Breaking Changes C++ Specific Potentially Breaking Changes ----------------------------------------- +- Clang now more aggressively optimizes away stores to objects after they are + dead. This behavior can be disabled with ``-fno-lifetime-dse``. + ABI Changes in This Version --------------------------- AST Dumping Potentially Breaking Changes ---------------------------------------- +- The JSON AST dump now includes all fields from ``AvailabilityAttr``: ``platform``, + ``introduced``, ``deprecated``, ``obsoleted``, ``unavailable``, ``message``, + ``strict``, ``replacement``, ``priority``, and ``environment``. Previously, these + fields were missing from the JSON output. + Clang Frontend Potentially Breaking Changes ------------------------------------------- +- HIPSPV toolchain: `--offload-targets=spirv{32,64}` option is + deprecated and will be removed when the new offload driver becomes + default. The replacement for the option is + `--offload-targets=spirv{32,64}-unknown-chipstar` when using the new + offload driver (`--offload-new-driver`). + + Clang Python Bindings Potentially Breaking Changes -------------------------------------------------- - Remove ``CompletionString.Availability``. No libclang interfaces returned instances of it. @@ -77,6 +92,10 @@ Clang Python Bindings Potentially Breaking Changes An alias is kept in the form of a ``SPELLING_CACHE`` variable, but it only supports ``__getitem__`` and ``__contains__``. It will be removed in a future release. Please migrate to using ``CompletionChunk.SPELLING_CACHE`` instead. +- ``SourceLocation`` and ``SourceRange`` now use ``NotImplemented`` to delegate + equality checks (``__eq__``) to the other object they are compared with when + they are of different classes. They previously returned ``False`` when compared + with objects of other classes. What's New in Clang |release|? ============================== @@ -204,6 +223,10 @@ Improvements to Clang's diagnostics - Improved ``-Wassign-enum`` performance by caching enum enumerator values. (#GH176454) +- Fixed a false negative in ``-Warray-bounds`` where the warning was suppressed + when accessing a member function on a past-the-end array element. + (#GH179128) + Improvements to Clang's time-trace ---------------------------------- @@ -216,6 +239,9 @@ Improvements to Coverage Mapping Bug Fixes in This Version ------------------------- + +- Fixed atomic boolean compound assignment; the conversion back to atomic bool would be miscompiled. (#GH33210) + - Fixed a failed assertion in the preprocessor when ``__has_embed`` parameters are missing parentheses. (#GH175088) - Fix lifetime extension of temporaries in for-range-initializers in templates. (#GH165182) @@ -239,9 +265,11 @@ Bug Fixes to C++ Support Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ +- Fixed a bug where explicit nullability property attributes were not stored in AST nodes in Objective-C. (#GH179703) Miscellaneous Bug Fixes ^^^^^^^^^^^^^^^^^^^^^^^ +- Fixed the arguments of the format attribute on ``__builtin_os_log_format``. Previously, they were off by 1. Miscellaneous Clang Crashes Fixed ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -267,6 +295,7 @@ NVPTX Support X86 Support ^^^^^^^^^^^ +- ``march=znver6`` is now supported. Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index c624efb26f67d..cec1e2a6a4677 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -129,7 +129,7 @@ Options to Control Error and Warning Messages .. This is in plain monospaced font because it generates the same label as .. -Werror, and Sphinx complains. -``-Werror=foo`` +.. option:: -Werror=foo Turn warning "foo" into an error. @@ -2321,6 +2321,31 @@ are listed below. additional function arity information (for supported targets). See :doc:`ControlFlowIntegrity` for more details. +.. option:: -fsanitize-trap-loop + + When a UBSan or CFI check fails in trapping mode, spin in an infinite + loop instead of executing a trap instruction. Conditional branching + in an infinite loop has been experimentally determined to be executed + more efficiently (when the branch is not taken) than a conditional + branch to a trap instruction on AMD and older Intel microarchitectures, + and is also more code size efficient by avoiding the need to emit a + trap instruction and possibly a long branch instruction. + + This behavior may be used as-is, but it is also designed to be + used in combination with an interrupt handler that detects that the + program is stuck in such an infinite loop and terminates the program, + effectively emulating the behavior without this option. To facilitate + this, the following guarantees about the infinite loop generated by + this option are provided: + + - On i386 and x86_64, the loop is guaranteed to consist of a single + short conditional branch instruction that branches to + itself. Specifically, the first byte of the instruction will be + between 0x70 and 0x7F, and the second byte will be 0xFE. + + - There are currently no guarantees about instructions used by other + targets. + .. option:: -fstrict-vtable-pointers Enable optimizations based on the strict rules for overwriting polymorphic diff --git a/clang/docs/index.rst b/clang/docs/index.rst index c4464c4dbf0a2..5cdbd52a2398d 100644 --- a/clang/docs/index.rst +++ b/clang/docs/index.rst @@ -124,6 +124,7 @@ Design Documents ConstantInterpreter LLVMExceptionHandlingCodeGen ClangIRCodeDuplication + ClangIRCleanupAndEHDesign Indices and tables ================== diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h index 68205dd1c1fd9..6b819de2fb36d 100644 --- a/clang/include/clang/AST/ASTContext.h +++ b/clang/include/clang/AST/ASTContext.h @@ -2698,7 +2698,8 @@ class ASTContext : public RefCountedBase { CharUnits getTypeSizeInChars(const Type *T) const; std::optional getTypeSizeInCharsIfKnown(QualType Ty) const { - if (Ty->isIncompleteType() || Ty->isDependentType()) + if (Ty->isIncompleteType() || Ty->isDependentType() || + Ty->isUndeducedType() || Ty->isSizelessType()) return std::nullopt; return getTypeSizeInChars(Ty); } @@ -2883,6 +2884,8 @@ class ASTContext : public RefCountedBase { /// (from the AuxTargetInfo) is a an itanium target. MangleContext *createDeviceMangleContext(const TargetInfo &T); + MangleContext *cudaNVInitDeviceMC(); + void DeepCollectObjCIvars(const ObjCInterfaceDecl *OI, bool leafClass, SmallVectorImpl &Ivars) const; diff --git a/clang/include/clang/AST/ComputeDependence.h b/clang/include/clang/AST/ComputeDependence.h index 895105640b931..3a3c86842501a 100644 --- a/clang/include/clang/AST/ComputeDependence.h +++ b/clang/include/clang/AST/ComputeDependence.h @@ -45,6 +45,7 @@ class ArrayInitLoopExpr; class ImplicitValueInitExpr; class InitListExpr; class ExtVectorElementExpr; +class MatrixElementExpr; class BlockExpr; class AsTypeExpr; class DeclRefExpr; @@ -135,6 +136,7 @@ ExprDependence computeDependence(ArrayInitLoopExpr *E); ExprDependence computeDependence(ImplicitValueInitExpr *E); ExprDependence computeDependence(InitListExpr *E); ExprDependence computeDependence(ExtVectorElementExpr *E); +ExprDependence computeDependence(MatrixElementExpr *E); ExprDependence computeDependence(BlockExpr *E, bool ContainsUnexpandedParameterPack); ExprDependence computeDependence(AsTypeExpr *E); diff --git a/clang/include/clang/AST/DeclObjCCommon.h b/clang/include/clang/AST/DeclObjCCommon.h index 42c97204a6130..ddb373cf01bf5 100644 --- a/clang/include/clang/AST/DeclObjCCommon.h +++ b/clang/include/clang/AST/DeclObjCCommon.h @@ -43,7 +43,7 @@ enum Kind { // Also, don't forget to update the Clang C API at CXObjCPropertyAttrKind and // clang_Cursor_getObjCPropertyAttributes. }; -} // namespace ObjCPropertyAttribute::Kind +} // namespace ObjCPropertyAttribute enum { /// Number of bits fitting all the property attributes. diff --git a/clang/include/clang/AST/Expr.h b/clang/include/clang/AST/Expr.h index 3e30a8b420f19..873ddb38e832a 100644 --- a/clang/include/clang/AST/Expr.h +++ b/clang/include/clang/AST/Expr.h @@ -291,6 +291,7 @@ class Expr : public ValueStmt { LV_NotObjectType, LV_IncompleteVoidType, LV_DuplicateVectorComponents, + LV_DuplicateMatrixComponents, LV_InvalidExpression, LV_InvalidMessageExpression, LV_MemberFunction, @@ -306,8 +307,9 @@ class Expr : public ValueStmt { MLV_NotObjectType, MLV_IncompleteVoidType, MLV_DuplicateVectorComponents, + MLV_DuplicateMatrixComponents, MLV_InvalidExpression, - MLV_LValueCast, // Specialized form of MLV_InvalidExpression. + MLV_LValueCast, // Specialized form of MLV_InvalidExpression. MLV_IncompleteType, MLV_ConstQualified, MLV_ConstQualifiedField, @@ -340,16 +342,17 @@ class Expr : public ValueStmt { enum Kinds { CL_LValue, CL_XValue, - CL_Function, // Functions cannot be lvalues in C. - CL_Void, // Void cannot be an lvalue in C. + CL_Function, // Functions cannot be lvalues in C. + CL_Void, // Void cannot be an lvalue in C. CL_AddressableVoid, // Void expression whose address can be taken in C. CL_DuplicateVectorComponents, // A vector shuffle with dupes. + CL_DuplicateMatrixComponents, // A matrix shuffle with dupes. CL_MemberFunction, // An expression referring to a member function CL_SubObjCPropertySetting, - CL_ClassTemporary, // A temporary of class type, or subobject thereof. - CL_ArrayTemporary, // A temporary of array type. + CL_ClassTemporary, // A temporary of class type, or subobject thereof. + CL_ArrayTemporary, // A temporary of array type. CL_ObjCMessageRValue, // ObjC message is an rvalue - CL_PRValue // A prvalue for any other reason, of any other type + CL_PRValue // A prvalue for any other reason, of any other type }; /// The results of modification testing. enum ModifiableType { @@ -774,14 +777,14 @@ class Expr : public ValueStmt { /// /// \param Type - How to evaluate the size of the Expr, as defined by the /// "type" parameter of __builtin_object_size - bool tryEvaluateObjectSize(uint64_t &Result, ASTContext &Ctx, - unsigned Type) const; + std::optional tryEvaluateObjectSize(const ASTContext &Ctx, + unsigned Type) const; /// If the current Expr is a pointer, this will try to statically /// determine the strlen of the string pointed to. /// Returns true if all of the above holds and we were able to figure out the /// strlen, false otherwise. - bool tryEvaluateStrLen(uint64_t &Result, ASTContext &Ctx) const; + std::optional tryEvaluateStrLen(const ASTContext &Ctx) const; bool EvaluateCharRangeAsString(std::string &Result, const Expr *SizeExpression, @@ -6554,30 +6557,24 @@ class GenericSelectionExpr final // Clang Extensions //===----------------------------------------------------------------------===// -/// ExtVectorElementExpr - This represents access to specific elements of a -/// vector, and may occur on the left hand side or right hand side. For example -/// the following is legal: "V.xy = V.zw" if V is a 4 element extended vector. -/// -/// Note that the base may have either vector or pointer to vector type, just -/// like a struct field reference. -/// -class ExtVectorElementExpr : public Expr { +template class ElementAccessExprBase : public Expr { +protected: Stmt *Base; IdentifierInfo *Accessor; SourceLocation AccessorLoc; -public: - ExtVectorElementExpr(QualType ty, ExprValueKind VK, Expr *base, - IdentifierInfo &accessor, SourceLocation loc) - : Expr(ExtVectorElementExprClass, ty, VK, - (VK == VK_PRValue ? OK_Ordinary : OK_VectorComponent)), - Base(base), Accessor(&accessor), AccessorLoc(loc) { - setDependence(computeDependence(this)); + + ElementAccessExprBase(StmtClass SC, QualType Ty, ExprValueKind VK, Expr *Base, + IdentifierInfo &Accessor, SourceLocation Loc, + ExprObjectKind OK) + : Expr(SC, Ty, VK, OK), Base(Base), Accessor(&Accessor), + AccessorLoc(Loc) { + setDependence(computeDependence(static_cast(this))); } - /// Build an empty vector element expression. - explicit ExtVectorElementExpr(EmptyShell Empty) - : Expr(ExtVectorElementExprClass, Empty) { } + explicit ElementAccessExprBase(StmtClass SC, EmptyShell Empty) + : Expr(SC, Empty) {} +public: const Expr *getBase() const { return cast(Base); } Expr *getBase() { return cast(Base); } void setBase(Expr *E) { Base = E; } @@ -6588,6 +6585,37 @@ class ExtVectorElementExpr : public Expr { SourceLocation getAccessorLoc() const { return AccessorLoc; } void setAccessorLoc(SourceLocation L) { AccessorLoc = L; } + SourceLocation getBeginLoc() const LLVM_READONLY { + return getBase()->getBeginLoc(); + } + SourceLocation getEndLoc() const LLVM_READONLY { return AccessorLoc; } + + child_range children() { return child_range(&Base, &Base + 1); } + const_child_range children() const { + return const_child_range(&Base, &Base + 1); + } +}; + +/// ExtVectorElementExpr - This represents access to specific elements of a +/// vector, and may occur on the left hand side or right hand side. For example +/// the following is legal: "V.xy = V.zw" if V is a 4 element extended vector. +/// +/// Note that the base may have either vector or pointer to vector type, just +/// like a struct field reference. +/// +class ExtVectorElementExpr + : public ElementAccessExprBase { +public: + ExtVectorElementExpr(QualType Ty, ExprValueKind VK, Expr *Base, + IdentifierInfo &Accessor, SourceLocation Loc) + : ElementAccessExprBase( + ExtVectorElementExprClass, Ty, VK, Base, Accessor, Loc, + (VK == VK_PRValue ? OK_Ordinary : OK_VectorComponent)) {} + + /// Build an empty vector element expression. + explicit ExtVectorElementExpr(EmptyShell Empty) + : ElementAccessExprBase(ExtVectorElementExprClass, Empty) {} + /// getNumElements - Get the number of components being selected. unsigned getNumElements() const; @@ -6599,11 +6627,6 @@ class ExtVectorElementExpr : public Expr { /// aggregate Constant of ConstantInt(s). void getEncodedElementAccess(SmallVectorImpl &Elts) const; - SourceLocation getBeginLoc() const LLVM_READONLY { - return getBase()->getBeginLoc(); - } - SourceLocation getEndLoc() const LLVM_READONLY { return AccessorLoc; } - /// isArrow - Return true if the base expression is a pointer to vector, /// return false if the base expression is a vector. bool isArrow() const; @@ -6611,11 +6634,33 @@ class ExtVectorElementExpr : public Expr { static bool classof(const Stmt *T) { return T->getStmtClass() == ExtVectorElementExprClass; } +}; - // Iterators - child_range children() { return child_range(&Base, &Base+1); } - const_child_range children() const { - return const_child_range(&Base, &Base + 1); +class MatrixElementExpr : public ElementAccessExprBase { +public: + MatrixElementExpr(QualType Ty, ExprValueKind VK, Expr *Base, + IdentifierInfo &Accessor, SourceLocation Loc) + : ElementAccessExprBase( + MatrixElementExprClass, Ty, VK, Base, Accessor, Loc, + OK_Ordinary /*TODO: Should we add a new OK_MatrixComponent?*/) {} + + /// Build an empty matrix element expression. + explicit MatrixElementExpr(EmptyShell Empty) + : ElementAccessExprBase(MatrixElementExprClass, Empty) {} + + /// getNumElements - Get the number of components being selected. + unsigned getNumElements() const; + + /// containsDuplicateElements - Return true if any element access is + /// repeated. + bool containsDuplicateElements() const; + + /// getEncodedElementAccess - Encode the elements accessed into an llvm + /// aggregate Constant of ConstantInt(s). + void getEncodedElementAccess(SmallVectorImpl &Elts) const; + + static bool classof(const Stmt *T) { + return T->getStmtClass() == MatrixElementExprClass; } }; diff --git a/clang/include/clang/AST/ExprCXX.h b/clang/include/clang/AST/ExprCXX.h index 9435ab069a520..c40cd929b7408 100644 --- a/clang/include/clang/AST/ExprCXX.h +++ b/clang/include/clang/AST/ExprCXX.h @@ -44,6 +44,7 @@ #include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringRef.h" +#include "llvm/ADT/TypeSwitch.h" #include "llvm/ADT/iterator_range.h" #include "llvm/Support/Casting.h" #include "llvm/Support/Compiler.h" @@ -5499,6 +5500,60 @@ class BuiltinBitCastExpr final } }; +/// Represents a C++26 reflect expression [expr.reflect]. The operand of the +/// expression is either: +/// - :: (global namespace), +/// - a reflection-name, +/// - a type-id, or +/// - an id-expression. +class CXXReflectExpr : public Expr { + + // TODO(Reflection): add support for TemplateReference, NamespaceReference and + // DeclRefExpr + using operand_type = llvm::PointerUnion; + + SourceLocation CaretCaretLoc; + operand_type Operand; + + CXXReflectExpr(SourceLocation CaretCaretLoc, const TypeSourceInfo *TSI); + CXXReflectExpr(EmptyShell Empty); + +public: + static CXXReflectExpr *Create(ASTContext &C, SourceLocation OperatorLoc, + TypeSourceInfo *TL); + + static CXXReflectExpr *CreateEmpty(ASTContext &C); + + SourceLocation getBeginLoc() const LLVM_READONLY { + return llvm::TypeSwitch(Operand) + .Case( + [](auto *Ptr) { return Ptr->getTypeLoc().getBeginLoc(); }); + } + + SourceLocation getEndLoc() const LLVM_READONLY { + return llvm::TypeSwitch(Operand) + .Case( + [](auto *Ptr) { return Ptr->getTypeLoc().getEndLoc(); }); + } + + /// Returns location of the '^^'-operator. + SourceLocation getOperatorLoc() const { return CaretCaretLoc; } + + child_range children() { + // TODO(Reflection) + return child_range(child_iterator(), child_iterator()); + } + + const_child_range children() const { + // TODO(Reflection) + return const_child_range(const_child_iterator(), const_child_iterator()); + } + + static bool classof(const Stmt *T) { + return T->getStmtClass() == CXXReflectExprClass; + } +}; + } // namespace clang #endif // LLVM_CLANG_AST_EXPRCXX_H diff --git a/clang/include/clang/AST/HLSLResource.h b/clang/include/clang/AST/HLSLResource.h index 071e59d72d983..131aebf5f14f2 100644 --- a/clang/include/clang/AST/HLSLResource.h +++ b/clang/include/clang/AST/HLSLResource.h @@ -16,7 +16,6 @@ #include "clang/AST/ASTContext.h" #include "clang/AST/Attr.h" -#include "clang/AST/Attrs.inc" #include "clang/AST/DeclBase.h" #include "clang/Basic/TargetInfo.h" #include "clang/Support/Compiler.h" @@ -106,6 +105,7 @@ inline uint32_t getResourceDimensions(llvm::dxil::ResourceDimension Dim) { llvm_unreachable( "We cannot get the dimension of a resource with unknown dimension."); } + llvm_unreachable("Unhandled llvm::dxil::ResourceDimension enum."); } } // namespace hlsl diff --git a/clang/include/clang/AST/JSONNodeDumper.h b/clang/include/clang/AST/JSONNodeDumper.h index b786147728058..69dbdbbdb3ecd 100644 --- a/clang/include/clang/AST/JSONNodeDumper.h +++ b/clang/include/clang/AST/JSONNodeDumper.h @@ -219,6 +219,7 @@ class JSONNodeDumper void VisitSectionAttr(const SectionAttr *SA); void VisitVisibilityAttr(const VisibilityAttr *VA); void VisitTLSModelAttr(const TLSModelAttr *TA); + void VisitAvailabilityAttr(const AvailabilityAttr *AA); void VisitTypedefType(const TypedefType *TT); void VisitUsingType(const UsingType *TT); diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h index 9e18752145aef..cfee62a362b1e 100644 --- a/clang/include/clang/AST/RecursiveASTVisitor.h +++ b/clang/include/clang/AST/RecursiveASTVisitor.h @@ -2884,6 +2884,8 @@ DEF_TRAVERSE_STMT(CXXUnresolvedConstructExpr, { TRY_TO(TraverseTypeLoc(S->getTypeSourceInfo()->getTypeLoc())); }) +DEF_TRAVERSE_STMT(CXXReflectExpr, {/*TODO*/}) + // These expressions all might take explicit template arguments. // We traverse those if so. FIXME: implement these. DEF_TRAVERSE_STMT(CXXConstructExpr, {}) @@ -2942,6 +2944,7 @@ DEF_TRAVERSE_STMT(UserDefinedLiteral, {}) DEF_TRAVERSE_STMT(DesignatedInitExpr, {}) DEF_TRAVERSE_STMT(DesignatedInitUpdateExpr, {}) DEF_TRAVERSE_STMT(ExtVectorElementExpr, {}) +DEF_TRAVERSE_STMT(MatrixElementExpr, {}) DEF_TRAVERSE_STMT(GNUNullExpr, {}) DEF_TRAVERSE_STMT(ImplicitValueInitExpr, {}) DEF_TRAVERSE_STMT(NoInitExpr, {}) diff --git a/clang/include/clang/AST/TextNodeDumper.h b/clang/include/clang/AST/TextNodeDumper.h index 88ecd526e3d7e..ab828be124b0b 100644 --- a/clang/include/clang/AST/TextNodeDumper.h +++ b/clang/include/clang/AST/TextNodeDumper.h @@ -286,6 +286,7 @@ class TextNodeDumper void VisitUnaryExprOrTypeTraitExpr(const UnaryExprOrTypeTraitExpr *Node); void VisitMemberExpr(const MemberExpr *Node); void VisitExtVectorElementExpr(const ExtVectorElementExpr *Node); + void VisitMatrixElementExpr(const MatrixElementExpr *Node); void VisitBinaryOperator(const BinaryOperator *Node); void VisitCompoundAssignOperator(const CompoundAssignOperator *Node); void VisitAddrLabelExpr(const AddrLabelExpr *Node); diff --git a/clang/include/clang/AST/TypeBase.h b/clang/include/clang/AST/TypeBase.h index f648232c2949d..2bec5131dc0d2 100644 --- a/clang/include/clang/AST/TypeBase.h +++ b/clang/include/clang/AST/TypeBase.h @@ -6754,6 +6754,8 @@ class HLSLAttributedResourceType : public Type, public llvm::FoldingSetNode { QualType getContainedType() const { return ContainedType; } bool hasContainedType() const { return !ContainedType.isNull(); } const Attributes &getAttrs() const { return Attrs; } + bool isRaw() const { return Attrs.RawBuffer; } + bool isStructured() const { return !ContainedType->isChar8Type(); } bool isSugared() const { return false; } QualType desugar() const { return QualType(this, 0); } diff --git a/clang/include/clang/Analysis/Analyses/LifetimeSafety/Checker.h b/clang/include/clang/Analysis/Analyses/LifetimeSafety/Checker.h index 5c631c92c0167..1ad3f9da61f60 100644 --- a/clang/include/clang/Analysis/Analyses/LifetimeSafety/Checker.h +++ b/clang/include/clang/Analysis/Analyses/LifetimeSafety/Checker.h @@ -26,8 +26,9 @@ namespace clang::lifetimes::internal { /// examining loan expiration points and checking if any live origins hold /// the expired loan. void runLifetimeChecker(const LoanPropagationAnalysis &LoanPropagation, + const MovedLoansAnalysis &MovedLoans, const LiveOriginsAnalysis &LiveOrigins, - const FactManager &FactMgr, AnalysisDeclContext &ADC, + FactManager &FactMgr, AnalysisDeclContext &ADC, LifetimeSafetySemaHelper *SemaHelper); } // namespace clang::lifetimes::internal diff --git a/clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h b/clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h index d948965af34d5..f9d55991f2e09 100644 --- a/clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h +++ b/clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h @@ -19,6 +19,7 @@ #include "clang/Analysis/Analyses/LifetimeSafety/Utils.h" #include "clang/Analysis/AnalysisDeclContext.h" #include "clang/Analysis/CFG.h" +#include "llvm/ADT/STLFunctionalExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Debug.h" #include @@ -44,10 +45,14 @@ class Fact { OriginFlow, /// An origin is used (eg. appears as l-value expression like DeclRefExpr). Use, + /// An origin that is moved (e.g., passed to an rvalue reference parameter). + MovedOrigin, /// A marker for a specific point in the code, for testing. TestPoint, /// An origin that escapes the function scope (e.g., via return). OriginEscapes, + /// An origin is invalidated (e.g. vector resized). + InvalidateOrigin, }; private: @@ -219,6 +224,50 @@ class UseFact : public Fact { const OriginManager &OM) const override; }; +/// Represents that an origin's storage has been invalidated by a container +/// operation (e.g., vector::push_back may reallocate, invalidating iterators). +/// Created when a container method that may invalidate references/iterators +/// is called on the container. +class InvalidateOriginFact : public Fact { + OriginID OID; + const Expr *InvalidationExpr; + +public: + static bool classof(const Fact *F) { + return F->getKind() == Kind::InvalidateOrigin; + } + + InvalidateOriginFact(OriginID OID, const Expr *InvalidationExpr) + : Fact(Kind::InvalidateOrigin), OID(OID), + InvalidationExpr(InvalidationExpr) {} + + OriginID getInvalidatedOrigin() const { return OID; } + const Expr *getInvalidationExpr() const { return InvalidationExpr; } + void dump(llvm::raw_ostream &OS, const LoanManager &, + const OriginManager &OM) const override; +}; + +/// Top-level origin of the expression which was found to be moved, e.g, when +/// being used as an argument to an r-value reference parameter. +class MovedOriginFact : public Fact { + const OriginID MovedOrigin; + const Expr *MoveExpr; + +public: + static bool classof(const Fact *F) { + return F->getKind() == Kind::MovedOrigin; + } + + MovedOriginFact(const Expr *MoveExpr, OriginID MovedOrigin) + : Fact(Kind::MovedOrigin), MovedOrigin(MovedOrigin), MoveExpr(MoveExpr) {} + + OriginID getMovedOrigin() const { return MovedOrigin; } + const Expr *getMoveExpr() const { return MoveExpr; } + + void dump(llvm::raw_ostream &OS, const LoanManager &, + const OriginManager &OM) const override; +}; + /// A dummy-fact used to mark a specific point in the code for testing. /// It is generated by recognizing a `void("__lifetime_test_point_...")` cast. class TestPointFact : public Fact { diff --git a/clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h b/clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h index 8b45337bee218..fb7d5ad91db79 100644 --- a/clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h +++ b/clang/include/clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h @@ -67,6 +67,14 @@ class FactsGenerator : public ConstStmtVisitor { void handleGSLPointerConstruction(const CXXConstructExpr *CCE); + /// Detects arguments passed to rvalue reference parameters and creates + /// MovedOriginFact for them. The MovedLoansAnalysis then uses these facts + /// to track in a flow-sensitive manner which loans have been moved at each + /// program point, allowing warnings to distinguish potentially moved storage + /// from other use-after-free errors. + void handleMovedArgsInCall(const FunctionDecl *FD, + ArrayRef Args); + /// Checks if a call-like expression creates a borrow by passing a value to a /// reference parameter, creating an IssueFact if it does. /// \param IsGslConstruction True if this is a GSL construction where all @@ -75,6 +83,11 @@ class FactsGenerator : public ConstStmtVisitor { ArrayRef Args, bool IsGslConstruction = false); + // Detect container methods that invalidate iterators/references. + // For instance methods, Args[0] is the implicit 'this' pointer. + void handleInvalidatingCall(const Expr *Call, const FunctionDecl *FD, + ArrayRef Args); + template void flowOrigin(const Destination &D, const Source &S) { flow(getOriginsList(D), getOriginsList(S), /*Kill=*/false); @@ -110,15 +123,6 @@ class FactsGenerator : public ConstStmtVisitor { // corresponding to the left-hand side is updated to be a "write", thereby // exempting it from the check. llvm::DenseMap UseFacts; - - // This is a flow-insensitive approximation: once a declaration is moved - // anywhere in the function, it's treated as moved everywhere. This can lead - // to false negatives on control flow paths where the value is not actually - // moved, but these are considered lower priority than the false positives - // this tracking prevents. - // TODO: The ideal solution would be flow-sensitive ownership tracking that - // records where values are moved from and to, but this is more complex. - llvm::DenseSet MovedDecls; }; } // namespace clang::lifetimes::internal diff --git a/clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h b/clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h index 3ca7a79d32ee1..984e9f87fef57 100644 --- a/clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h +++ b/clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h @@ -66,6 +66,15 @@ bool isGslPointerType(QualType QT); // Tells whether the type is annotated with [[gsl::Owner]]. bool isGslOwnerType(QualType QT); +// Returns true if the given method is std::unique_ptr::release(). +// This is treated as a move in lifetime analysis to avoid false-positives +// when ownership is manually transferred. +bool isUniquePtrRelease(const CXXMethodDecl &MD); + +// Returns true if the given method invalidates iterators or references to +// container elements (e.g. vector::push_back). +bool isContainerInvalidationMethod(const CXXMethodDecl &MD); + } // namespace clang::lifetimes #endif // LLVM_CLANG_ANALYSIS_ANALYSES_LIFETIMEANNOTATIONS_H diff --git a/clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h b/clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h index 9f22db20e79b1..6148f86091110 100644 --- a/clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h +++ b/clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeSafety.h @@ -20,12 +20,15 @@ #ifndef LLVM_CLANG_ANALYSIS_ANALYSES_LIFETIMESAFETY_H #define LLVM_CLANG_ANALYSIS_ANALYSES_LIFETIMESAFETY_H +#include "clang/AST/Decl.h" #include "clang/Analysis/Analyses/LifetimeSafety/Facts.h" #include "clang/Analysis/Analyses/LifetimeSafety/LifetimeStats.h" #include "clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h" #include "clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h" +#include "clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h" #include "clang/Analysis/Analyses/LifetimeSafety/Origins.h" #include "clang/Analysis/AnalysisDeclContext.h" +#include namespace clang::lifetimes { @@ -58,18 +61,29 @@ class LifetimeSafetySemaHelper { virtual ~LifetimeSafetySemaHelper() = default; virtual void reportUseAfterFree(const Expr *IssueExpr, const Expr *UseExpr, - SourceLocation FreeLoc, + const Expr *MovedExpr, SourceLocation FreeLoc, Confidence Confidence) {} virtual void reportUseAfterReturn(const Expr *IssueExpr, const Expr *ReturnExpr, + const Expr *MovedExpr, SourceLocation ExpiryLoc, Confidence Confidence) {} virtual void reportDanglingField(const Expr *IssueExpr, const FieldDecl *Field, + const Expr *MovedExpr, SourceLocation ExpiryLoc) {} + // Reports when a reference/iterator is used after the container operation + // that invalidated it. + virtual void reportUseAfterInvalidation(const Expr *IssueExpr, + const Expr *UseExpr, + const Expr *InvalidationExpr) {} + virtual void reportUseAfterInvalidation(const ParmVarDecl *PVD, + const Expr *UseExpr, + const Expr *InvalidationExpr) {} + // Suggests lifetime bound annotations for function paramters. virtual void suggestLifetimeboundToParmVar(SuggestionScope Scope, const ParmVarDecl *ParmToAnnotate, @@ -107,6 +121,7 @@ void collectLifetimeStats(AnalysisDeclContext &AC, OriginManager &OM, struct LifetimeFactory { OriginLoanMap::Factory OriginMapFactory{/*canonicalize=*/false}; LoanSet::Factory LoanSetFactory{/*canonicalize=*/false}; + MovedLoansMap::Factory MovedLoansMapFactory{/*canonicalize=*/false}; LivenessMap::Factory LivenessMapFactory{/*canonicalize=*/false}; }; @@ -133,6 +148,7 @@ class LifetimeSafetyAnalysis { std::unique_ptr FactMgr; std::unique_ptr LiveOrigins; std::unique_ptr LoanPropagation; + std::unique_ptr MovedLoans; }; } // namespace internal } // namespace clang::lifetimes diff --git a/clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h b/clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h index a366e3e811cbf..9aaf4627ce5ad 100644 --- a/clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h +++ b/clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h @@ -30,8 +30,7 @@ inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, LoanID ID) { /// Represents the storage location being borrowed, e.g., a specific stack /// variable. /// TODO: Model access paths of other types, e.g., s.field, heap and globals. -struct AccessPath { -private: +class AccessPath { // An access path can be: // - ValueDecl * , to represent the storage location corresponding to the // variable declared in ValueDecl. @@ -52,6 +51,8 @@ struct AccessPath { const clang::MaterializeTemporaryExpr *getAsMaterializeTemporaryExpr() const { return P.dyn_cast(); } + + bool operator==(const AccessPath &RHS) const { return P == RHS.P; } }; /// An abstract base class for a single "Loan" which represents lending a diff --git a/clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h b/clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h new file mode 100644 index 0000000000000..a83f40c8855b6 --- /dev/null +++ b/clang/include/clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h @@ -0,0 +1,46 @@ +//===- MovedLoans.h - Moved Loans Analysis -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the MovedLoansAnalysis, a forward dataflow analysis that +// tracks which loans have been moved out of their original storage location +// at each program point. +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_CLANG_ANALYSIS_ANALYSES_LIFETIMESAFETY_MOVED_LOANS_H +#define LLVM_CLANG_ANALYSIS_ANALYSES_LIFETIMESAFETY_MOVED_LOANS_H + +#include "clang/Analysis/Analyses/LifetimeSafety/Facts.h" +#include "clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h" +#include "clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h" +#include "clang/Analysis/AnalysisDeclContext.h" +#include "clang/Analysis/CFG.h" + +namespace clang::lifetimes::internal { + +// Map from a loan to an expression responsible for moving the borrowed storage. +using MovedLoansMap = llvm::ImmutableMap; + +class MovedLoansAnalysis { +public: + MovedLoansAnalysis(const CFG &C, AnalysisDeclContext &AC, FactManager &F, + const LoanPropagationAnalysis &LoanPropagation, + const LiveOriginsAnalysis &LiveOrigins, + const LoanManager &LoanMgr, + MovedLoansMap::Factory &MovedLoansMapFactory); + ~MovedLoansAnalysis(); + + MovedLoansMap getMovedLoans(ProgramPoint P) const; + +private: + class Impl; + std::unique_ptr PImpl; +}; + +} // namespace clang::lifetimes::internal + +#endif // LLVM_CLANG_ANALYSIS_ANALYSES_LIFETIMESAFETY_MOVED_LOANS_H diff --git a/clang/include/clang/Analysis/Analyses/ThreadSafetyCommon.h b/clang/include/clang/Analysis/Analyses/ThreadSafetyCommon.h index 388d7e83ef5cf..36eed484e9fd1 100644 --- a/clang/include/clang/Analysis/Analyses/ThreadSafetyCommon.h +++ b/clang/include/clang/Analysis/Analyses/ThreadSafetyCommon.h @@ -35,8 +35,8 @@ #include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Casting.h" +#include "llvm/Support/raw_ostream.h" #include -#include #include #include #include @@ -91,9 +91,10 @@ inline bool partiallyMatches(const til::SExpr *E1, const til::SExpr *E2) { } inline std::string toString(const til::SExpr *E) { - std::stringstream ss; + std::string s; + llvm::raw_string_ostream ss(s); til::StdPrinter::print(E, ss); - return ss.str(); + return s; } } // namespace sx diff --git a/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h b/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h index 14c5b679428a3..ff2d32ee5f688 100644 --- a/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h +++ b/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h @@ -148,129 +148,54 @@ StringRef getBinaryOpcodeString(TIL_BinaryOpcode Op); /// All variables and expressions must have a value type. /// Pointer types are further subdivided into the various heap-allocated /// types, such as functions, records, etc. -/// Structured types that are passed by value (e.g. complex numbers) -/// require special handling; they use BT_ValueRef, and size ST_0. struct ValueType { enum BaseType : unsigned char { - BT_Void = 0, BT_Bool, - BT_Int, - BT_Float, - BT_String, // String literals - BT_Pointer, - BT_ValueRef + BT_Char, + BT_SInt, + BT_UInt, + BT_String, // String literals + BT_NullPointer, }; - enum SizeType : unsigned char { - ST_0 = 0, - ST_1, - ST_8, - ST_16, - ST_32, - ST_64, - ST_128 - }; - - ValueType(BaseType B, SizeType Sz, bool S, unsigned char VS) - : Base(B), Size(Sz), Signed(S), VectSize(VS) {} - - inline static SizeType getSizeType(unsigned nbytes); + ValueType(BaseType B) : Base(B) {} template inline static ValueType getValueType(); BaseType Base; - SizeType Size; - bool Signed; - - // 0 for scalar, otherwise num elements in vector - unsigned char VectSize; }; -inline ValueType::SizeType ValueType::getSizeType(unsigned nbytes) { - switch (nbytes) { - case 1: return ST_8; - case 2: return ST_16; - case 4: return ST_32; - case 8: return ST_64; - case 16: return ST_128; - default: return ST_0; - } -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Void, ST_0, false, 0); +inline bool operator==(const ValueType &a, const ValueType &b) { + return a.Base == b.Base; } template<> inline ValueType ValueType::getValueType() { - return ValueType(BT_Bool, ST_1, false, 0); + return ValueType(BT_Bool); } -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Int, ST_8, true, 0); -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Int, ST_8, false, 0); -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Int, ST_16, true, 0); -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Int, ST_16, false, 0); -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Int, ST_32, true, 0); -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Int, ST_32, false, 0); +template <> inline ValueType ValueType::getValueType() { + return ValueType(BT_Char); } template<> inline ValueType ValueType::getValueType() { - return ValueType(BT_Int, ST_64, true, 0); + return ValueType(BT_SInt); } template<> inline ValueType ValueType::getValueType() { - return ValueType(BT_Int, ST_64, false, 0); -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Float, ST_32, true, 0); -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Float, ST_64, true, 0); -} - -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Float, ST_128, true, 0); + return ValueType(BT_UInt); } template<> inline ValueType ValueType::getValueType() { - return ValueType(BT_String, getSizeType(sizeof(StringRef)), false, 0); + return ValueType(BT_String); } -template<> -inline ValueType ValueType::getValueType() { - return ValueType(BT_Pointer, getSizeType(sizeof(void*)), false, 0); +template <> inline ValueType ValueType::getValueType() { + return ValueType(BT_NullPointer); } /// Base class for AST nodes in the typed intermediate language. @@ -532,37 +457,29 @@ template class LiteralT; // Base class for literal values. class Literal : public SExpr { -public: - Literal(const Expr *C) - : SExpr(COP_Literal), ValType(ValueType::getValueType()), Cexpr(C) {} +protected: Literal(ValueType VT) : SExpr(COP_Literal), ValType(VT) {} - Literal(const Literal &) = default; +public: static bool classof(const SExpr *E) { return E->opcode() == COP_Literal; } - // The clang expression for this literal. - const Expr *clangExpr() const { return Cexpr; } - ValueType valueType() const { return ValType; } template const LiteralT& as() const { + assert(ValType == ValueType::getValueType()); return *static_cast*>(this); } template LiteralT& as() { + assert(ValType == ValueType::getValueType()); return *static_cast*>(this); } template typename V::R_SExpr traverse(V &Vs, typename V::R_Ctx Ctx); - template - typename C::CType compare(const Literal* E, C& Cmp) const { - // TODO: defer actual comparison to LiteralT - return Cmp.trueResult(); - } + template typename C::CType compare(const Literal *E, C &Cmp) const; private: const ValueType ValType; - const Expr *Cexpr = nullptr; }; // Derived class for literal values, which stores the actual value. @@ -583,60 +500,50 @@ class LiteralT : public Literal { T Val; }; +template LiteralT(T) -> LiteralT; + template typename V::R_SExpr Literal::traverse(V &Vs, typename V::R_Ctx Ctx) { - if (Cexpr) - return Vs.reduceLiteral(*this); - switch (ValType.Base) { - case ValueType::BT_Void: - break; case ValueType::BT_Bool: return Vs.reduceLiteralT(as()); - case ValueType::BT_Int: { - switch (ValType.Size) { - case ValueType::ST_8: - if (ValType.Signed) - return Vs.reduceLiteralT(as()); - else - return Vs.reduceLiteralT(as()); - case ValueType::ST_16: - if (ValType.Signed) - return Vs.reduceLiteralT(as()); - else - return Vs.reduceLiteralT(as()); - case ValueType::ST_32: - if (ValType.Signed) - return Vs.reduceLiteralT(as()); - else - return Vs.reduceLiteralT(as()); - case ValueType::ST_64: - if (ValType.Signed) - return Vs.reduceLiteralT(as()); - else - return Vs.reduceLiteralT(as()); - default: - break; - } - } - case ValueType::BT_Float: { - switch (ValType.Size) { - case ValueType::ST_32: - return Vs.reduceLiteralT(as()); - case ValueType::ST_64: - return Vs.reduceLiteralT(as()); - default: - break; - } - } + case ValueType::BT_Char: + return Vs.reduceLiteralT(as()); + case ValueType::BT_SInt: + return Vs.reduceLiteralT(as()); + case ValueType::BT_UInt: + return Vs.reduceLiteralT(as()); case ValueType::BT_String: return Vs.reduceLiteralT(as()); - case ValueType::BT_Pointer: - return Vs.reduceLiteralT(as()); - case ValueType::BT_ValueRef: - break; + case ValueType::BT_NullPointer: + return Vs.reduceLiteralT(as()); + } + llvm_unreachable("Invalid BaseType"); +} + +template +typename C::CType Literal::compare(const Literal *E, C &Cmp) const { + typename C::CType Ct = Cmp.compareIntegers(ValType.Base, E->ValType.Base); + if (Cmp.notTrue(Ct)) + return Ct; + switch (ValType.Base) { + case ValueType::BT_Bool: + return Cmp.compareIntegers(as().value(), E->as().value()); + case ValueType::BT_Char: + return Cmp.compareIntegers(as().value(), + E->as().value()); + case ValueType::BT_SInt: + return Cmp.compareIntegers(as().value(), E->as().value()); + case ValueType::BT_UInt: + return Cmp.compareIntegers(as().value(), + E->as().value()); + case ValueType::BT_String: + return Cmp.compareStrings(as().value(), + E->as().value()); + case ValueType::BT_NullPointer: + return Cmp.trueResult(); } - return Vs.reduceLiteral(*this); + llvm_unreachable("Invalid BaseType"); } /// A Literal pointer to an object allocated in memory. diff --git a/clang/include/clang/Analysis/Analyses/ThreadSafetyTraverse.h b/clang/include/clang/Analysis/Analyses/ThreadSafetyTraverse.h index acab8bcdc1dab..177d2baa3e4a7 100644 --- a/clang/include/clang/Analysis/Analyses/ThreadSafetyTraverse.h +++ b/clang/include/clang/Analysis/Analyses/ThreadSafetyTraverse.h @@ -17,6 +17,7 @@ #define LLVM_CLANG_ANALYSIS_ANALYSES_THREADSAFETYTRAVERSE_H #include "clang/AST/Decl.h" +#include "clang/AST/Expr.h" #include "clang/Analysis/Analyses/ThreadSafetyTIL.h" #include "clang/Analysis/Analyses/ThreadSafetyUtil.h" #include "clang/Basic/LLVM.h" @@ -192,7 +193,6 @@ class VisitReducer : public Traversal, R_SExpr reduceUndefined(Undefined &Orig) { return true; } R_SExpr reduceWildcard(Wildcard &Orig) { return true; } - R_SExpr reduceLiteral(Literal &Orig) { return true; } template R_SExpr reduceLiteralT(LiteralT &Orig) { return true; } R_SExpr reduceLiteralPtr(Literal &Orig) { return true; } @@ -336,7 +336,7 @@ class EqualsComparator : public Comparator { CType trueResult() { return true; } bool notTrue(CType ct) { return !ct; } - bool compareIntegers(unsigned i, unsigned j) { return i == j; } + bool compareIntegers(uint64_t i, uint64_t j) { return i == j; } bool compareStrings (StringRef s, StringRef r) { return s == r; } bool comparePointers(const void* P, const void* Q) { return P == Q; } @@ -364,7 +364,7 @@ class MatchComparator : public Comparator { CType trueResult() { return true; } bool notTrue(CType ct) { return !ct; } - bool compareIntegers(unsigned i, unsigned j) { return i == j; } + bool compareIntegers(uint64_t i, uint64_t j) { return i == j; } bool compareStrings (StringRef s, StringRef r) { return s == r; } bool comparePointers(const void *P, const void *Q) { return P == Q; } @@ -532,88 +532,34 @@ class PrettyPrinter { SS << "*"; } - template - void printLiteralT(const LiteralT *E, StreamType &SS) { - SS << E->value(); - } - - void printLiteralT(const LiteralT *E, StreamType &SS) { - SS << "'" << E->value() << "'"; - } - void printLiteral(const Literal *E, StreamType &SS) { - if (E->clangExpr()) { - SS << getSourceLiteralString(E->clangExpr()); + ValueType VT = E->valueType(); + switch (VT.Base) { + case ValueType::BT_Bool: + if (E->as().value()) + SS << "true"; + else + SS << "false"; + return; + case ValueType::BT_Char: + CharacterLiteral::print(E->as().value(), + CharacterLiteralKind::UTF32, SS); + return; + case ValueType::BT_SInt: + SS << E->as().value(); + return; + case ValueType::BT_UInt: + SS << E->as().value(); + return; + case ValueType::BT_String: + SS << '\"' << E->as().value() << '\"'; + return; + case ValueType::BT_NullPointer: + assert(E->as().value() == nullptr); + SS << "nullptr"; return; } - else { - ValueType VT = E->valueType(); - switch (VT.Base) { - case ValueType::BT_Void: - SS << "void"; - return; - case ValueType::BT_Bool: - if (E->as().value()) - SS << "true"; - else - SS << "false"; - return; - case ValueType::BT_Int: - switch (VT.Size) { - case ValueType::ST_8: - if (VT.Signed) - printLiteralT(&E->as(), SS); - else - printLiteralT(&E->as(), SS); - return; - case ValueType::ST_16: - if (VT.Signed) - printLiteralT(&E->as(), SS); - else - printLiteralT(&E->as(), SS); - return; - case ValueType::ST_32: - if (VT.Signed) - printLiteralT(&E->as(), SS); - else - printLiteralT(&E->as(), SS); - return; - case ValueType::ST_64: - if (VT.Signed) - printLiteralT(&E->as(), SS); - else - printLiteralT(&E->as(), SS); - return; - default: - break; - } - break; - case ValueType::BT_Float: - switch (VT.Size) { - case ValueType::ST_32: - printLiteralT(&E->as(), SS); - return; - case ValueType::ST_64: - printLiteralT(&E->as(), SS); - return; - default: - break; - } - break; - case ValueType::BT_String: - SS << "\""; - printLiteralT(&E->as(), SS); - SS << "\""; - return; - case ValueType::BT_Pointer: - SS << "#ptr"; - return; - case ValueType::BT_ValueRef: - SS << "#vref"; - return; - } - } - SS << "#lit"; + llvm_unreachable("Invalid BaseType"); } void printLiteralPtr(const LiteralPtr *E, StreamType &SS) { @@ -919,7 +865,7 @@ class PrettyPrinter { } }; -class StdPrinter : public PrettyPrinter {}; +class StdPrinter : public PrettyPrinter {}; } // namespace til } // namespace threadSafety diff --git a/clang/include/clang/Analysis/CFGBackEdges.h b/clang/include/clang/Analysis/CFGBackEdges.h new file mode 100644 index 0000000000000..d7cbe5818fc6a --- /dev/null +++ b/clang/include/clang/Analysis/CFGBackEdges.h @@ -0,0 +1,54 @@ +//===- CFGBackEdges.h - Finds back edges in Clang CFGs -*- C++ ----------*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_ANALYSIS_CFG_BACKEDGES_H +#define LLVM_CLANG_ANALYSIS_CFG_BACKEDGES_H + +#include "clang/Analysis/CFG.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" + +namespace clang { + +/// Finds and returns back edges in Clang CFGs. The CFG already has some +/// backedge information for structured loops (\c CFGBlock::getLoopTarget). +/// However, unstructured back edges from \c goto statements are not included. +/// This helps find back edges, whether the CFG is reducible or not. +/// This includes CFGBlock::getLoopTarget nodes, but one can filter those out +/// e.g., with \c findNonStructuredLoopBackedgeNodes. +llvm::DenseMap +findCFGBackEdges(const CFG &CFG); + +/// Returns a set of CFG blocks that is the source of a backedge and is not +/// tracked as part of a structured loop (with `CFGBlock::getLoopTarget`). +llvm::SmallDenseSet +findNonStructuredLoopBackedgeNodes(const CFG &CFG); + +/// Given a backedge from B1 to B2, B1 is a "backedge node" in a CFG. +/// It can be: +/// - A block introduced in the CFG exclusively to indicate a structured loop's +/// backedge. They are exactly identified by the presence of a non-null +/// pointer to the entry block of the loop condition. Note that this is not +/// necessarily the block with the loop statement as terminator, because +/// short-circuit operators will result in multiple blocks encoding the loop +/// condition, only one of which will contain the loop statement as +/// terminator. +/// - A block that is part of a backedge in a CFG with unstructured loops +/// (e.g., a CFG with a `goto` statement). Note that this is not necessarily +/// the block with the goto statement as terminator. The choice depends on how +/// blocks and edges are ordered. +/// +/// \param NonStructLoopBackedgeNodes is the set of nodes from +/// \c findNonStructuredLoopBackedgeNodes. +bool isBackedgeCFGNode( + const CFGBlock &B, + const llvm::SmallDenseSet &NonStructLoopBackedgeNodes); + +} // namespace clang + +#endif // LLVM_CLANG_ANALYSIS_CFG_BACKEDGES_H diff --git a/clang/include/clang/Analysis/Scalable/Serialization/SerializationFormat.h b/clang/include/clang/Analysis/Scalable/Serialization/SerializationFormat.h index a53a315f461df..d648ba60fc160 100644 --- a/clang/include/clang/Analysis/Scalable/Serialization/SerializationFormat.h +++ b/clang/include/clang/Analysis/Scalable/Serialization/SerializationFormat.h @@ -15,8 +15,11 @@ #define CLANG_ANALYSIS_SCALABLE_SERIALIZATION_SERIALIZATION_FORMAT_H #include "clang/Analysis/Scalable/Model/BuildNamespace.h" +#include "clang/Analysis/Scalable/Model/SummaryName.h" +#include "clang/Analysis/Scalable/TUSummary/TUSummary.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringRef.h" +#include "llvm/Support/VirtualFileSystem.h" #include namespace clang::ssaf { @@ -24,8 +27,7 @@ namespace clang::ssaf { class EntityId; class EntityIdTable; class EntityName; -class TUSummary; -class TUSummaryData; +class EntitySummary; /// Abstract base class for serialization formats. class SerializationFormat { @@ -46,14 +48,32 @@ class SerializationFormat { static const llvm::SmallString<16> &getEntityNameSuffix(const EntityName &EN); static const NestedBuildNamespace & getEntityNameNamespace(const EntityName &EN); + static decltype(TUSummary::Data) &getData(TUSummary &S); + static const decltype(TUSummary::Data) &getData(const TUSummary &S); public: + explicit SerializationFormat( + llvm::IntrusiveRefCntPtr FS); virtual ~SerializationFormat() = default; virtual TUSummary readTUSummary(llvm::StringRef Path) = 0; virtual void writeTUSummary(const TUSummary &Summary, llvm::StringRef OutputDir) = 0; + +protected: + llvm::IntrusiveRefCntPtr FS; +}; + +template struct FormatInfoEntry { + FormatInfoEntry(SummaryName ForSummary, SerializerFn Serialize, + DeserializerFn Deserialize) + : ForSummary(ForSummary), Serialize(Serialize), Deserialize(Deserialize) { + } + + SummaryName ForSummary; + SerializerFn Serialize; + DeserializerFn Deserialize; }; } // namespace clang::ssaf diff --git a/clang/include/clang/Analysis/Scalable/Serialization/SerializationFormatRegistry.h b/clang/include/clang/Analysis/Scalable/Serialization/SerializationFormatRegistry.h new file mode 100644 index 0000000000000..40281d549b402 --- /dev/null +++ b/clang/include/clang/Analysis/Scalable/Serialization/SerializationFormatRegistry.h @@ -0,0 +1,71 @@ +//===- SerializationFormatRegistry.h ----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Registry for SerializationFormats, and some helper functions. +// To register some custom serialization format, insert this code: +// +// static SerializationFormatRegistry::Add +// RegisterFormat("MyFormat", "My awesome serialization format"); +// +// Then implement the formatter for the specific analysis and register the +// format info for it: +// +// namespace { +// using FormatInfo = MyFormat::FormatInfo; +// struct MyAnalysisFormatInfo : FormatInfo { +// MyAnalysisFormatInfo() : FormatInfo{ +// SummaryName("MyAnalysis"), +// serializeMyAnalysis, +// deserializeMyAnalysis, +// } {} +// }; +// } // namespace +// +// static llvm::Registry::Add +// RegisterFormatInfo( +// "MyAnalysisFormatInfo", +// "The MyFormat format info implementation for MyAnalysis" +// ); +// +//===----------------------------------------------------------------------===// + +#ifndef CLANG_ANALYSIS_SCALABLE_SERIALIZATION_SERIALIZATION_FORMAT_REGISTRY_H +#define CLANG_ANALYSIS_SCALABLE_SERIALIZATION_SERIALIZATION_FORMAT_REGISTRY_H + +#include "clang/Analysis/Scalable/Serialization/SerializationFormat.h" +#include "clang/Support/Compiler.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/Registry.h" + +namespace clang::ssaf { + +/// Check if a SerializationFormat was registered with a given name. +bool isFormatRegistered(llvm::StringRef FormatName); + +/// Try to instantiate a SerializationFormat with a given name. +/// This might return null if the construction of the desired +/// SerializationFormat failed. +/// It's a fatal error if there is no format registered with the name. +std::unique_ptr +makeFormat(llvm::IntrusiveRefCntPtr FS, + llvm::StringRef FormatName); + +// Registry for adding new SerializationFormat implementations. +using SerializationFormatRegistry = + llvm::Registry>; + +} // namespace clang::ssaf + +namespace llvm { +extern template class CLANG_TEMPLATE_ABI + Registry>; +} // namespace llvm + +#endif // CLANG_ANALYSIS_SCALABLE_SERIALIZATION_SERIALIZATION_FORMAT_REGISTRY_H diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 2bf27839c750e..ea3f9df6d8342 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -476,7 +476,7 @@ def TargetMips32 : TargetArch<["mips", "mipsel"]>; def TargetAnyMips : TargetArch<["mips", "mipsel", "mips64", "mips64el"]>; def TargetMSP430 : TargetArch<["msp430"]>; def TargetM68k : TargetArch<["m68k"]>; -def TargetRISCV : TargetArch<["riscv32", "riscv64"]>; +def TargetRISCV : TargetArch<["riscv32", "riscv64", "riscv32be", "riscv64be"]>; def TargetX86 : TargetArch<["x86"]>; def TargetX86_64 : TargetArch<["x86_64"]>; def TargetAnyX86 : TargetArch<["x86", "x86_64"]>; diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index b3dcd4410de95..cad45501df6d2 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -6698,6 +6698,13 @@ Not all targets support this attribute: with an indirect call. The function pointer is initialized by a constructor that calls the resolver. - Baremetal target supports it on AVR. +- AIX/XCOFF supports it via a compiler-only solution. An ifunc appears as a + regular function (has an entry point ``.foo[PR]`` and a function descriptor + ``foo[DS]``). The entry point is a stub that branches to the function address + in the descriptor, and the descriptor is initialized via a constructor + function (``__init_ifuncs``) that is linked into every shared object and + executable. ``__init_ifuncs`` calls the resolver of each ifunc and stores the + result in the corresponding descriptor. - Other targets currently do not support this attribute. }]; } diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td index a410a138836eb..05e3af4a0e96f 100644 --- a/clang/include/clang/Basic/Builtins.td +++ b/clang/include/clang/Basic/Builtins.td @@ -4776,6 +4776,12 @@ def PtrauthAuthAndResign : Builtin { let Prototype = "void*(void*,int,void*,int,void*)"; } +def PtrauthAuthLoadRelativeAndSign : Builtin { + let Spellings = ["__builtin_ptrauth_auth_load_relative_and_sign"]; + let Attributes = [CustomTypeChecking, NoThrow]; + let Prototype = "void*(void*,int,void*,int,void*,ptrdiff_t)"; +} + def PtrauthAuth : Builtin { let Spellings = ["__builtin_ptrauth_auth"]; let Attributes = [CustomTypeChecking, NoThrow]; @@ -4970,8 +4976,7 @@ def OSLogFormatBufferSize : Builtin { def OSLogFormat : Builtin { let Spellings = ["__builtin_os_log_format"]; - // FIXME: The printf attribute looks suspiciously like it should be argument #1. - let Attributes = [PrintfFormat<0>, NoThrow, CustomTypeChecking]; + let Attributes = [PrintfFormat<1>, NoThrow, CustomTypeChecking]; let Prototype = "void*(void*, char const*, ...)"; } @@ -4995,12 +5000,24 @@ def HLSLResourceGetPointer : LangBuiltin<"HLSL_LANG"> { let Prototype = "void(...)"; } +def HLSLResourceGetPointerTyped : Builtin { + let Spellings = ["__builtin_hlsl_resource_getpointer_typed"]; + let Attributes = [NoThrow]; + let Prototype = "void(...)"; +} + def HLSLResourceLoadWithStatus : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_resource_load_with_status"]; let Attributes = [NoThrow]; let Prototype = "void(...)"; } +def HLSLResourceLoadWithStatusTyped : LangBuiltin<"HLSL_LANG"> { + let Spellings = ["__builtin_hlsl_resource_load_with_status_typed"]; + let Attributes = [NoThrow]; + let Prototype = "void(...)"; +} + def HLSLResourceSample : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_resource_sample"]; let Attributes = [NoThrow]; @@ -5151,6 +5168,12 @@ def HLSLWaveGetLaneCount : LangBuiltin<"HLSL_LANG"> { let Prototype = "unsigned int()"; } +def HLSLWavePrefixSum : LangBuiltin<"HLSL_LANG"> { + let Spellings = ["__builtin_hlsl_wave_prefix_sum"]; + let Attributes = [NoThrow, Const]; + let Prototype = "void(...)"; +} + def HLSLClamp : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_elementwise_clamp"]; let Attributes = [NoThrow, Const, CustomTypeChecking]; diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.td b/clang/include/clang/Basic/BuiltinsAMDGPU.td index 1950757097fc6..b7839b2febcd3 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.td +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.td @@ -270,7 +270,7 @@ def __builtin_amdgcn_fmed3h : AMDGPUBuiltin<"__fp16(__fp16, __fp16, __fp16)", [C def __builtin_amdgcn_global_atomic_fadd_f64 : AMDGPUBuiltin<"double(double address_space<1> *, double)", [], "gfx90a-insts">; def __builtin_amdgcn_global_atomic_fadd_f32 : AMDGPUBuiltin<"float(float address_space<1> *, float)", [], "atomic-fadd-rtn-insts">; -def __builtin_amdgcn_global_atomic_fadd_v2f16 : AMDGPUBuiltin<"_ExtVector<2, _Float16>(_ExtVector<2, _Float16 address_space<1> *>, _ExtVector<2, _Float16>)", [CustomTypeChecking], "atomic-buffer-global-pk-add-f16-insts">; +def __builtin_amdgcn_global_atomic_fadd_v2f16 : AMDGPUBuiltin<"_ExtVector<2, _Float16>(_ExtVector<2, _Float16> address_space<1> *, _ExtVector<2, _Float16>)", [CustomTypeChecking], "atomic-buffer-global-pk-add-f16-insts">; def __builtin_amdgcn_global_atomic_fmin_f64 : AMDGPUBuiltin<"double(double address_space<1> *, double)", [], "gfx90a-insts">; def __builtin_amdgcn_global_atomic_fmax_f64 : AMDGPUBuiltin<"double(double address_space<1> *, double)", [], "gfx90a-insts">; @@ -282,11 +282,11 @@ def __builtin_amdgcn_ds_atomic_fadd_f64 : AMDGPUBuiltin<"double(double address_s def __builtin_amdgcn_ds_atomic_fadd_f32 : AMDGPUBuiltin<"float(float address_space<3> *, float)", [], "gfx8-insts">; def __builtin_amdgcn_flat_atomic_fadd_f32 : AMDGPUBuiltin<"float(float address_space<0> *, float)", [], "gfx940-insts">; -def __builtin_amdgcn_flat_atomic_fadd_v2f16 : AMDGPUBuiltin<"_ExtVector<2, _Float16>(_ExtVector<2, _Float16 address_space<0> *>, _ExtVector<2, _Float16>)", [CustomTypeChecking], "atomic-flat-pk-add-16-insts">; -def __builtin_amdgcn_flat_atomic_fadd_v2bf16 : AMDGPUBuiltin<"_ExtVector<2, short>(_ExtVector<2, short address_space<0> *>, _ExtVector<2, short>)", [CustomTypeChecking], "atomic-flat-pk-add-16-insts">; -def __builtin_amdgcn_global_atomic_fadd_v2bf16 : AMDGPUBuiltin<"_ExtVector<2, short>(_ExtVector<2, short address_space<1> *>, _ExtVector<2, short>)", [CustomTypeChecking], "atomic-global-pk-add-bf16-inst">; -def __builtin_amdgcn_ds_atomic_fadd_v2bf16 : AMDGPUBuiltin<"_ExtVector<2, short>(_ExtVector<2, short address_space<3> *>, _ExtVector<2, short>)", [CustomTypeChecking], "atomic-ds-pk-add-16-insts">; -def __builtin_amdgcn_ds_atomic_fadd_v2f16 : AMDGPUBuiltin<"_ExtVector<2, _Float16>(_ExtVector<2, _Float16 address_space<3> *>, _ExtVector<2, _Float16>)", [CustomTypeChecking], "atomic-ds-pk-add-16-insts">; +def __builtin_amdgcn_flat_atomic_fadd_v2f16 : AMDGPUBuiltin<"_ExtVector<2, _Float16>(_ExtVector<2, _Float16> address_space<0> *, _ExtVector<2, _Float16>)", [CustomTypeChecking], "atomic-flat-pk-add-16-insts">; +def __builtin_amdgcn_flat_atomic_fadd_v2bf16 : AMDGPUBuiltin<"_ExtVector<2, short>(_ExtVector<2, short> address_space<0> *, _ExtVector<2, short>)", [CustomTypeChecking], "atomic-flat-pk-add-16-insts">; +def __builtin_amdgcn_global_atomic_fadd_v2bf16 : AMDGPUBuiltin<"_ExtVector<2, short>(_ExtVector<2, short> address_space<1> *, _ExtVector<2, short>)", [CustomTypeChecking], "atomic-global-pk-add-bf16-inst">; +def __builtin_amdgcn_ds_atomic_fadd_v2bf16 : AMDGPUBuiltin<"_ExtVector<2, short>(_ExtVector<2, short> address_space<3> *, _ExtVector<2, short>)", [CustomTypeChecking], "atomic-ds-pk-add-16-insts">; +def __builtin_amdgcn_ds_atomic_fadd_v2f16 : AMDGPUBuiltin<"_ExtVector<2, _Float16>(_ExtVector<2, _Float16> address_space<3> *, _ExtVector<2, _Float16>)", [CustomTypeChecking], "atomic-ds-pk-add-16-insts">; def __builtin_amdgcn_load_to_lds : AMDGPUBuiltin<"void(void *, void address_space<3> *, _Constant unsigned int, _Constant int, _Constant unsigned int)", [], "vmem-to-lds-load-insts">; def __builtin_amdgcn_global_load_lds : AMDGPUBuiltin<"void(void address_space<1> *, void address_space<3> *, _Constant unsigned int, _Constant int, _Constant unsigned int)", [], "vmem-to-lds-load-insts">; @@ -339,6 +339,7 @@ def __builtin_amdgcn_image_bvh_intersect_ray_lh : AMDGPUBuiltin<"_ExtVector<4, u // TODO: This is a no-op in wave32. Should the builtin require wavefrontsize64? def __builtin_amdgcn_permlane64 : AMDGPUBuiltin<"unsigned int(unsigned int)", [Const], "gfx11-insts">; def __builtin_amdgcn_s_wait_event_export_ready : AMDGPUBuiltin<"void()", [], "gfx11-insts">; +def __builtin_amdgcn_s_wait_event : AMDGPUBuiltin<"void(_Constant short)", [], "gfx11-insts">; //===----------------------------------------------------------------------===// // WMMA builtins. @@ -531,12 +532,12 @@ def __builtin_amdgcn_smfmac_f32_32x32x64_fp8_fp8 : AMDGPUBuiltin<"_ExtVector<16, def __builtin_amdgcn_permlane16_swap : AMDGPUBuiltin<"_ExtVector<2, unsigned int>(unsigned int, unsigned int, _Constant bool, _Constant bool)", [Const], "permlane16-swap">; def __builtin_amdgcn_permlane32_swap : AMDGPUBuiltin<"_ExtVector<2, unsigned int>(unsigned int, unsigned int, _Constant bool, _Constant bool)", [Const], "permlane32-swap">; -def __builtin_amdgcn_ds_read_tr4_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<3> *>)", [Const], "gfx950-insts">; -def __builtin_amdgcn_ds_read_tr6_b96_v3i32 : AMDGPUBuiltin<"_ExtVector<3, int>(_ExtVector<3, int address_space<3> *>)", [Const], "gfx950-insts">; -def __builtin_amdgcn_ds_read_tr8_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<3> *>)", [Const], "gfx950-insts">; -def __builtin_amdgcn_ds_read_tr16_b64_v4i16 : AMDGPUBuiltin<"_ExtVector<4, short>(_ExtVector<4, short address_space<3> *>)", [Const], "gfx950-insts">; -def __builtin_amdgcn_ds_read_tr16_b64_v4f16 : AMDGPUBuiltin<"_ExtVector<4, __fp16>(_ExtVector<4, __fp16 address_space<3> *>)", [Const], "gfx950-insts">; -def __builtin_amdgcn_ds_read_tr16_b64_v4bf16 : AMDGPUBuiltin<"_ExtVector<4, __bf16>(_ExtVector<4, __bf16 address_space<3> *>)", [Const], "gfx950-insts">; +def __builtin_amdgcn_ds_read_tr4_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<3> *)", [Const], "gfx950-insts">; +def __builtin_amdgcn_ds_read_tr6_b96_v3i32 : AMDGPUBuiltin<"_ExtVector<3, int>(_ExtVector<3, int> address_space<3> *)", [Const], "gfx950-insts">; +def __builtin_amdgcn_ds_read_tr8_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<3> *)", [Const], "gfx950-insts">; +def __builtin_amdgcn_ds_read_tr16_b64_v4i16 : AMDGPUBuiltin<"_ExtVector<4, short>(_ExtVector<4, short> address_space<3> *)", [Const], "gfx950-insts">; +def __builtin_amdgcn_ds_read_tr16_b64_v4f16 : AMDGPUBuiltin<"_ExtVector<4, __fp16>(_ExtVector<4, __fp16> address_space<3> *)", [Const], "gfx950-insts">; +def __builtin_amdgcn_ds_read_tr16_b64_v4bf16 : AMDGPUBuiltin<"_ExtVector<4, __bf16>(_ExtVector<4, __bf16> address_space<3> *)", [Const], "gfx950-insts">; def __builtin_amdgcn_ashr_pk_i8_i32 : AMDGPUBuiltin<"unsigned short(unsigned int, unsigned int, unsigned int)", [Const], "ashr-pk-insts">; def __builtin_amdgcn_ashr_pk_u8_i32 : AMDGPUBuiltin<"unsigned short(unsigned int, unsigned int, unsigned int)", [Const], "ashr-pk-insts">; @@ -563,21 +564,21 @@ def __builtin_amdgcn_s_get_named_barrier_state : AMDGPUBuiltin<"unsigned int(voi def __builtin_amdgcn_s_prefetch_data : AMDGPUBuiltin<"void(void const *, unsigned int)", [Const], "gfx12-insts">; def __builtin_amdgcn_s_buffer_prefetch_data : AMDGPUBuiltin<"void(__amdgpu_buffer_rsrc_t, _Constant int, unsigned int)", [Const], "gfx12-insts">; -def __builtin_amdgcn_global_load_tr_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<1> *>)", [Const], "gfx12-insts,wavefrontsize32">; -def __builtin_amdgcn_global_load_tr_b128_v8i16 : AMDGPUBuiltin<"_ExtVector<8, short>(_ExtVector<8, short address_space<1> *>)", [Const], "gfx12-insts,wavefrontsize32">; -def __builtin_amdgcn_global_load_tr_b128_v8f16 : AMDGPUBuiltin<"_ExtVector<8, __fp16>(_ExtVector<8, __fp16 address_space<1> *>)", [Const], "gfx12-insts,wavefrontsize32">; -def __builtin_amdgcn_global_load_tr_b128_v8bf16 : AMDGPUBuiltin<"_ExtVector<8, __bf16>(_ExtVector<8, __bf16 address_space<1> *>)", [Const], "gfx12-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<1> *)", [Const], "gfx12-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr_b128_v8i16 : AMDGPUBuiltin<"_ExtVector<8, short>(_ExtVector<8, short> address_space<1> *)", [Const], "gfx12-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr_b128_v8f16 : AMDGPUBuiltin<"_ExtVector<8, __fp16>(_ExtVector<8, __fp16> address_space<1> *)", [Const], "gfx12-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr_b128_v8bf16 : AMDGPUBuiltin<"_ExtVector<8, __bf16>(_ExtVector<8, __bf16> address_space<1> *)", [Const], "gfx12-insts,wavefrontsize32">; def __builtin_amdgcn_global_load_tr_b64_i32 : AMDGPUBuiltin<"int(int address_space<1> *)", [Const], "gfx12-insts,wavefrontsize64">; -def __builtin_amdgcn_global_load_tr_b128_v4i16 : AMDGPUBuiltin<"_ExtVector<4, short>(_ExtVector<4, short address_space<1> *>)", [Const], "gfx12-insts,wavefrontsize64">; -def __builtin_amdgcn_global_load_tr_b128_v4f16 : AMDGPUBuiltin<"_ExtVector<4, __fp16>(_ExtVector<4, __fp16 address_space<1> *>)", [Const], "gfx12-insts,wavefrontsize64">; -def __builtin_amdgcn_global_load_tr_b128_v4bf16 : AMDGPUBuiltin<"_ExtVector<4, __bf16>(_ExtVector<4, __bf16 address_space<1> *>)", [Const], "gfx12-insts,wavefrontsize64">; +def __builtin_amdgcn_global_load_tr_b128_v4i16 : AMDGPUBuiltin<"_ExtVector<4, short>(_ExtVector<4, short> address_space<1> *)", [Const], "gfx12-insts,wavefrontsize64">; +def __builtin_amdgcn_global_load_tr_b128_v4f16 : AMDGPUBuiltin<"_ExtVector<4, __fp16>(_ExtVector<4, __fp16> address_space<1> *)", [Const], "gfx12-insts,wavefrontsize64">; +def __builtin_amdgcn_global_load_tr_b128_v4bf16 : AMDGPUBuiltin<"_ExtVector<4, __bf16>(_ExtVector<4, __bf16> address_space<1> *)", [Const], "gfx12-insts,wavefrontsize64">; def __builtin_amdgcn_ds_bpermute_fi_b32 : AMDGPUBuiltin<"int(int, int)", [Const], "gfx12-insts">; // For the following two builtins, the second and third return values of the // intrinsics are returned through the last two pointer-type function arguments. -def __builtin_amdgcn_image_bvh8_intersect_ray : AMDGPUBuiltin<"_ExtVector<10, unsigned int>(uint64_t, float, unsigned char, _ExtVector<3, float>, _ExtVector<3, float>, unsigned int, _ExtVector<4, unsigned int>, _ExtVector<3, float *>, _ExtVector<3, float *>)", [Const], "gfx12-insts">; -def __builtin_amdgcn_image_bvh_dual_intersect_ray : AMDGPUBuiltin<"_ExtVector<10, unsigned int>(uint64_t, float, unsigned char, _ExtVector<3, float>, _ExtVector<3, float>, _ExtVector<2, unsigned int>, _ExtVector<4, unsigned int>, _ExtVector<3, float *>, _ExtVector<3, float *>)", [Const], "gfx12-insts">; +def __builtin_amdgcn_image_bvh8_intersect_ray : AMDGPUBuiltin<"_ExtVector<10, unsigned int>(uint64_t, float, unsigned char, _ExtVector<3, float>, _ExtVector<3, float>, unsigned int, _ExtVector<4, unsigned int>, _ExtVector<3, float> *, _ExtVector<3, float> *)", [Const], "gfx12-insts">; +def __builtin_amdgcn_image_bvh_dual_intersect_ray : AMDGPUBuiltin<"_ExtVector<10, unsigned int>(uint64_t, float, unsigned char, _ExtVector<3, float>, _ExtVector<3, float>, _ExtVector<2, unsigned int>, _ExtVector<4, unsigned int>, _ExtVector<3, float> *, _ExtVector<3, float> *)", [Const], "gfx12-insts">; def __builtin_amdgcn_ds_bvh_stack_push4_pop1_rtn : AMDGPUBuiltin<"_ExtVector<2, unsigned int>(unsigned int, unsigned int, _ExtVector<4, unsigned int>, _Constant int)", [], "gfx11-insts">; def __builtin_amdgcn_ds_bvh_stack_push8_pop1_rtn : AMDGPUBuiltin<"_ExtVector<2, unsigned int>(unsigned int, unsigned int, _ExtVector<8, unsigned int>, _Constant int)", [], "gfx12-insts">; @@ -711,27 +712,27 @@ def __builtin_amdgcn_s_cluster_barrier : AMDGPUBuiltin<"void()", [], "gfx1250-in def __builtin_amdgcn_flat_prefetch : AMDGPUBuiltin<"void(void const address_space<0> *, _Constant int)", [Const], "vmem-pref-insts">; def __builtin_amdgcn_global_prefetch : AMDGPUBuiltin<"void(void const address_space<1> *, _Constant int)", [Const], "vmem-pref-insts">; -def __builtin_amdgcn_global_load_monitor_b32 : AMDGPUBuiltin<"int(int address_space<1> *, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_global_load_monitor_b64 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<1> *>, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_global_load_monitor_b128 : AMDGPUBuiltin<"_ExtVector<4, int>(_ExtVector<4, int address_space<1> *>, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_flat_load_monitor_b32 : AMDGPUBuiltin<"int(int address_space<0> *, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_flat_load_monitor_b64 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<0> *>, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_flat_load_monitor_b128 : AMDGPUBuiltin<"_ExtVector<4, int>(_ExtVector<4, int address_space<0> *>, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_global_load_monitor_b32 : AMDGPUBuiltin<"int(int address_space<1> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_global_load_monitor_b64 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<1> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_global_load_monitor_b128 : AMDGPUBuiltin<"_ExtVector<4, int>(_ExtVector<4, int> address_space<1> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_flat_load_monitor_b32 : AMDGPUBuiltin<"int(int address_space<0> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_flat_load_monitor_b64 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<0> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_flat_load_monitor_b128 : AMDGPUBuiltin<"_ExtVector<4, int>(_ExtVector<4, int> address_space<0> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; def __builtin_amdgcn_cluster_load_b32 : AMDGPUBuiltin<"int(int address_space<1> *, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; -def __builtin_amdgcn_cluster_load_b64 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<1> *>, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; -def __builtin_amdgcn_cluster_load_b128 : AMDGPUBuiltin<"_ExtVector<4, int>(_ExtVector<4, int address_space<1> *>, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; +def __builtin_amdgcn_cluster_load_b64 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<1> *, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; +def __builtin_amdgcn_cluster_load_b128 : AMDGPUBuiltin<"_ExtVector<4, int>(_ExtVector<4, int> address_space<1> *, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; def __builtin_amdgcn_cluster_load_async_to_lds_b8 : AMDGPUBuiltin<"void(char address_space<1> *, char address_space<3> *, _Constant int, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; def __builtin_amdgcn_cluster_load_async_to_lds_b32 : AMDGPUBuiltin<"void(int address_space<1> *, int address_space<3> *, _Constant int, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; -def __builtin_amdgcn_cluster_load_async_to_lds_b64 : AMDGPUBuiltin<"void(_ExtVector<2, int address_space<1> *>, _ExtVector<2, int address_space<3> *>, _Constant int, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; -def __builtin_amdgcn_cluster_load_async_to_lds_b128 : AMDGPUBuiltin<"void(_ExtVector<4, int address_space<1> *>, _ExtVector<4, int address_space<3> *>, _Constant int, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; +def __builtin_amdgcn_cluster_load_async_to_lds_b64 : AMDGPUBuiltin<"void(_ExtVector<2, int> address_space<1> *, _ExtVector<2, int> address_space<3> *, _Constant int, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; +def __builtin_amdgcn_cluster_load_async_to_lds_b128 : AMDGPUBuiltin<"void(_ExtVector<4, int> address_space<1> *, _ExtVector<4, int> address_space<3> *, _Constant int, _Constant int, int)", [Const], "mcast-load-insts,wavefrontsize32">; def __builtin_amdgcn_global_load_async_to_lds_b8 : AMDGPUBuiltin<"void(char address_space<1> *, char address_space<3> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; def __builtin_amdgcn_global_load_async_to_lds_b32 : AMDGPUBuiltin<"void(int address_space<1> *, int address_space<3> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_global_load_async_to_lds_b64 : AMDGPUBuiltin<"void(_ExtVector<2, int address_space<1> *>, _ExtVector<2, int address_space<3> *>, _Constant int, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_global_load_async_to_lds_b128 : AMDGPUBuiltin<"void(_ExtVector<4, int address_space<1> *>, _ExtVector<4, int address_space<3> *>, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_global_load_async_to_lds_b64 : AMDGPUBuiltin<"void(_ExtVector<2, int> address_space<1> *, _ExtVector<2, int> address_space<3> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_global_load_async_to_lds_b128 : AMDGPUBuiltin<"void(_ExtVector<4, int> address_space<1> *, _ExtVector<4, int> address_space<3> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; def __builtin_amdgcn_global_store_async_from_lds_b8 : AMDGPUBuiltin<"void(char address_space<1> *, char address_space<3> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; def __builtin_amdgcn_global_store_async_from_lds_b32 : AMDGPUBuiltin<"void(int address_space<1> *, int address_space<3> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_global_store_async_from_lds_b64 : AMDGPUBuiltin<"void(_ExtVector<2, int address_space<1> *>, _ExtVector<2, int address_space<3> *>, _Constant int, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_global_store_async_from_lds_b128 : AMDGPUBuiltin<"void(_ExtVector<4, int address_space<1> *>, _ExtVector<4, int address_space<3> *>, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_global_store_async_from_lds_b64 : AMDGPUBuiltin<"void(_ExtVector<2, int> address_space<1> *, _ExtVector<2, int> address_space<3> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; +def __builtin_amdgcn_global_store_async_from_lds_b128 : AMDGPUBuiltin<"void(_ExtVector<4, int> address_space<1> *, _ExtVector<4, int> address_space<3> *, _Constant int, _Constant int)", [Const], "gfx1250-insts">; def __builtin_amdgcn_ds_atomic_async_barrier_arrive_b64 : AMDGPUBuiltin<"void(long int address_space<3> *)", [Const], "gfx1250-insts">; def __builtin_amdgcn_ds_atomic_barrier_arrive_rtn_b64 : AMDGPUBuiltin<"long int(long int address_space<3> *, long int)", [Const], "gfx1250-insts">; @@ -740,18 +741,18 @@ def __builtin_amdgcn_tensor_load_to_lds_d2 : AMDGPUBuiltin<"void(_ExtVector<4, i def __builtin_amdgcn_tensor_store_from_lds : AMDGPUBuiltin<"void(_ExtVector<4, int>, _ExtVector<8, int>, _ExtVector<4, int>, _ExtVector<4, int>, _Constant int)", [Const], "gfx1250-insts">; def __builtin_amdgcn_tensor_store_from_lds_d2 : AMDGPUBuiltin<"void(_ExtVector<4, int>, _ExtVector<8, int>, _Constant int)", [Const], "gfx1250-insts">; -def __builtin_amdgcn_global_load_tr4_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<1> *>)", [Const], "transpose-load-f4f6-insts,wavefrontsize32">; -def __builtin_amdgcn_global_load_tr8_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<1> *>)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_global_load_tr6_b96_v3i32 : AMDGPUBuiltin<"_ExtVector<3, int>(_ExtVector<3, int address_space<1> *>)", [Const], "transpose-load-f4f6-insts,wavefrontsize32">; -def __builtin_amdgcn_global_load_tr16_b128_v8i16 : AMDGPUBuiltin<"_ExtVector<8, short>(_ExtVector<8, short address_space<1> *>)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_global_load_tr16_b128_v8f16 : AMDGPUBuiltin<"_ExtVector<8, __fp16>(_ExtVector<8, __fp16 address_space<1> *>)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_global_load_tr16_b128_v8bf16 : AMDGPUBuiltin<"_ExtVector<8, __bf16>(_ExtVector<8, __bf16 address_space<1> *>)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_ds_load_tr4_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<3> *>)", [Const], "transpose-load-f4f6-insts,wavefrontsize32">; -def __builtin_amdgcn_ds_load_tr8_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int address_space<3> *>)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_ds_load_tr6_b96_v3i32 : AMDGPUBuiltin<"_ExtVector<3, int>(_ExtVector<3, int address_space<3> *>)", [Const], "transpose-load-f4f6-insts,wavefrontsize32">; -def __builtin_amdgcn_ds_load_tr16_b128_v8i16 : AMDGPUBuiltin<"_ExtVector<8, short>(_ExtVector<8, short address_space<3> *>)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_ds_load_tr16_b128_v8f16 : AMDGPUBuiltin<"_ExtVector<8, __fp16>(_ExtVector<8, __fp16 address_space<3> *>)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_ds_load_tr16_b128_v8bf16 : AMDGPUBuiltin<"_ExtVector<8, __bf16>(_ExtVector<8, __bf16 address_space<3> *>)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr4_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<1> *)", [Const], "transpose-load-f4f6-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr8_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<1> *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr6_b96_v3i32 : AMDGPUBuiltin<"_ExtVector<3, int>(_ExtVector<3, int> address_space<1> *)", [Const], "transpose-load-f4f6-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr16_b128_v8i16 : AMDGPUBuiltin<"_ExtVector<8, short>(_ExtVector<8, short> address_space<1> *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr16_b128_v8f16 : AMDGPUBuiltin<"_ExtVector<8, __fp16>(_ExtVector<8, __fp16> address_space<1> *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_global_load_tr16_b128_v8bf16 : AMDGPUBuiltin<"_ExtVector<8, __bf16>(_ExtVector<8, __bf16> address_space<1> *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_ds_load_tr4_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<3> *)", [Const], "transpose-load-f4f6-insts,wavefrontsize32">; +def __builtin_amdgcn_ds_load_tr8_b64_v2i32 : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> address_space<3> *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_ds_load_tr6_b96_v3i32 : AMDGPUBuiltin<"_ExtVector<3, int>(_ExtVector<3, int> address_space<3> *)", [Const], "transpose-load-f4f6-insts,wavefrontsize32">; +def __builtin_amdgcn_ds_load_tr16_b128_v8i16 : AMDGPUBuiltin<"_ExtVector<8, short>(_ExtVector<8, short> address_space<3> *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_ds_load_tr16_b128_v8f16 : AMDGPUBuiltin<"_ExtVector<8, __fp16>(_ExtVector<8, __fp16> address_space<3> *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_ds_load_tr16_b128_v8bf16 : AMDGPUBuiltin<"_ExtVector<8, __bf16>(_ExtVector<8, __bf16> address_space<3> *)", [Const], "gfx1250-insts,wavefrontsize32">; def __builtin_amdgcn_s_setprio_inc_wg : AMDGPUBuiltin<"void(_Constant short)", [], "setprio-inc-wg-inst">; def __builtin_amdgcn_s_monitor_sleep : AMDGPUBuiltin<"void(_Constant short)", [], "gfx1250-insts">; @@ -899,11 +900,11 @@ def __builtin_amdgcn_swmmac_f16_16x16x64_f16 : AMDGPUBuiltin<"_ExtVector<8, __fp def __builtin_amdgcn_cooperative_atomic_load_32x4B : AMDGPUBuiltin<"int(int *, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; def __builtin_amdgcn_cooperative_atomic_store_32x4B : AMDGPUBuiltin<"void(int *, int, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_cooperative_atomic_load_16x8B : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int *>, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_cooperative_atomic_store_16x8B : AMDGPUBuiltin<"void(_ExtVector<2, int *>, _ExtVector<2, int>, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_cooperative_atomic_load_16x8B : AMDGPUBuiltin<"_ExtVector<2, int>(_ExtVector<2, int> *, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_cooperative_atomic_store_16x8B : AMDGPUBuiltin<"void(_ExtVector<2, int> *, _ExtVector<2, int>, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_cooperative_atomic_load_8x16B : AMDGPUBuiltin<"_ExtVector<4, int>(_ExtVector<4, int *>, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; -def __builtin_amdgcn_cooperative_atomic_store_8x16B : AMDGPUBuiltin<"void(_ExtVector<4, int *>, _ExtVector<4, int>, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_cooperative_atomic_load_8x16B : AMDGPUBuiltin<"_ExtVector<4, int>(_ExtVector<4, int> *, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; +def __builtin_amdgcn_cooperative_atomic_store_8x16B : AMDGPUBuiltin<"void(_ExtVector<4, int> *, _ExtVector<4, int>, _Constant int, char const *)", [Const], "gfx1250-insts,wavefrontsize32">; //===----------------------------------------------------------------------===// // Image builtins diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index baf8b093c10e6..8c056bb690690 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -191,6 +191,8 @@ CODEGENOPT(EnableSegmentedStacks , 1, 0, Benign) ///< Set when -fsplit-stack is CODEGENOPT(StackClashProtector, 1, 0, Benign) ///< Set when -fstack-clash-protection is enabled. CODEGENOPT(NoImplicitFloat , 1, 0, Benign) ///< Set when -mno-implicit-float is enabled. CODEGENOPT(NullPointerIsValid , 1, 0, Benign) ///< Assume Null pointer deference is defined. +CODEGENOPT(StrictLifetimes , 1, 0, Benign) ///< Assume an object is dead + ///< after its destructor returns. CODEGENOPT(OpenCLCorrectlyRoundedDivSqrt, 1, 0, Benign) ///< -cl-fp32-correctly-rounded-divide-sqrt CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1, Benign) ///< -fno-hip-fp32-correctly-rounded-divide-sqrt CODEGENOPT(DisableBlockSignatureString, 1, 0, Benign) ///< Set when -fdisable-block-signature-string is enabled. @@ -277,6 +279,8 @@ CODEGENOPT(SanitizeMinimalRuntime, 1, 0, Benign) ///< Use "_minimal" sanitizer r ///< diagnostics. CODEGENOPT(SanitizeHandlerPreserveAllRegs, 1, 0, Benign) ///< Use "_preserve" sanitizer runtime for ///< diagnostics. +CODEGENOPT(SanitizeTrapLoop, 1, 0, Benign) ///< In trapping mode, use an infinite loop to halt the + ///< program in case of check failure. CODEGENOPT(SanitizeCfiICallGeneralizePointers, 1, 0, Benign) ///< Generalize pointer types in ///< CFI icall function signatures CODEGENOPT(SanitizeCfiICallNormalizeIntegers, 1, 0, Benign) ///< Normalize integer types in diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td b/clang/include/clang/Basic/DiagnosticCommonKinds.td index 4aa5855bb0b94..cb267e3ee05c1 100644 --- a/clang/include/clang/Basic/DiagnosticCommonKinds.td +++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td @@ -286,6 +286,8 @@ def err_seh___except_filter : Error< "%0 only allowed in __except filter expression">; def err_seh___finally_block : Error< "%0 only allowed in __finally block">; +def err_seh_object_unwinding : Error< + "'__try' is not permitted in functions that require object unwinding">; // Sema && AST def note_invalid_subexpr_in_const_expr : Note< diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 6798801c51142..90a92b1602231 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -446,6 +446,9 @@ def warn_ignored_clang_option : Warning<"the flag '%0' has been deprecated and w def warn_drv_unsupported_opt_for_target : Warning< "optimization flag '%0' is not supported for target '%1'">, InGroup; +def warn_drv_riscv_be_experimental : Warning< + "big-endian RISC-V target support is experimental">, + InGroup; def warn_drv_unsupported_debug_info_opt_for_target : Warning< "debug information option '%0' is not supported for target '%1'">, InGroup; @@ -916,4 +919,7 @@ def warn_drv_gcc_install_dir_libstdcxx : Warning< "future releases of the clang compiler will prefer GCC installations " "containing libstdc++ include directories; '%0' would be chosen over '%1'">, InGroup>; + +def err_drv_reflection_requires_cxx26 : Error< + "option '%0' is only supported when compiling in C++26 mode">; } diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td index d36ee57fe7651..0372cf062ec67 100644 --- a/clang/include/clang/Basic/DiagnosticGroups.td +++ b/clang/include/clang/Basic/DiagnosticGroups.td @@ -148,6 +148,7 @@ def UnsupportedFPOpt : DiagGroup<"unsupported-floating-point-opt">; def UnsupportedCB : DiagGroup<"unsupported-cb">; def UnsupportedGPOpt : DiagGroup<"unsupported-gpopt">; def UnsupportedTargetOpt : DiagGroup<"unsupported-target-opt">; +def RISCVBEExperimental : DiagGroup<"riscv-be-experimental">; def NonLiteralNullConversion : DiagGroup<"non-literal-null-conversion">; def NullConversion : DiagGroup<"null-conversion">; def ImplicitConversionFloatingPointToBool : @@ -539,9 +540,25 @@ def LifetimeSafetyDanglingField : DiagGroup<"lifetime-safety-dangling-field"> { }]; } +def LifetimeSafetyDanglingFieldStrict : DiagGroup<"lifetime-safety-dangling-field-strict"> { + code Documentation = [{ + Warning to detect dangling field references. + This may contain false-positives, e.g. when the borrowed storage is potentially moved and is not destroyed at function exit. + }]; +} + + +def LifetimeSafetyInvalidation : DiagGroup<"lifetime-safety-invalidation"> { + code Documentation = [{ + Warning to detect invalidation of references. + }]; +} + def LifetimeSafetyPermissive : DiagGroup<"lifetime-safety-permissive", [LifetimeSafetyDanglingField]>; -def LifetimeSafetyStrict : DiagGroup<"lifetime-safety-strict">; +def LifetimeSafetyStrict : DiagGroup<"lifetime-safety-strict", + [LifetimeSafetyDanglingFieldStrict, + LifetimeSafetyInvalidation]>; def LifetimeSafety : DiagGroup<"lifetime-safety", [LifetimeSafetyPermissive, LifetimeSafetyStrict]> { diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index 457d3644de35a..de10dbe5d0628 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -1847,6 +1847,11 @@ def err_placeholder_expected_auto_or_decltype_auto : Error< "expected 'auto' or 'decltype(auto)' after concept name">; } +let CategoryName = "Reflection Diagnostics" in { +def err_cannot_reflect_operand : Error< + "unknown or unimplemented reflectable entity">; +} + def warn_max_tokens : Warning< "the number of preprocessor source tokens (%0) exceeds this token limit (%1)">, InGroup, DefaultIgnore; diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 807440c107897..f12677ac11600 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -6558,6 +6558,9 @@ def err_vm_func_decl : Error< def err_array_too_large : Error< "array is too large (%0 elements)">; +def err_type_too_large_for_address_space : Error< + "%0 is too large for the address space (maximum allowed size of %1 bytes)">; + def err_typecheck_negative_array_size : Error<"array size is negative">; def warn_typecheck_function_qualifiers_ignored : Warning< "'%0' qualifier on function type %1 has no effect">, @@ -9367,6 +9370,8 @@ def err_typecheck_lvalue_casts_not_supported : Error< def err_typecheck_duplicate_vector_components_not_mlvalue : Error< "vector is not assignable (contains duplicate components)">; +def err_typecheck_duplicate_matrix_components_not_mlvalue + : Error<"matrix is not assignable (contains duplicate components)">; def err_block_decl_ref_not_modifiable_lvalue : Error< "variable is not assignable (missing __block type specifier)">; def err_lambda_decl_ref_not_modifiable_lvalue : Error< @@ -10816,24 +10821,43 @@ def warn_lifetime_safety_loan_expires_permissive : Warning< def warn_lifetime_safety_loan_expires_strict : Warning< "object whose reference is captured may not live long enough">, InGroup, DefaultIgnore; +def warn_lifetime_safety_loan_expires_moved_strict : Warning< + "object whose reference is captured may not live long enough. " + "This could be false positive as the storage may have been moved later">, + InGroup, DefaultIgnore; def warn_lifetime_safety_return_stack_addr_permissive : Warning<"address of stack memory is returned later">, InGroup, DefaultIgnore; -def warn_lifetime_safety_return_stack_addr_strict - : Warning<"address of stack memory may be returned later">, +def warn_lifetime_safety_return_stack_addr_moved_strict + : Warning<"address of stack memory may be returned later. " + "This could be false positive as the storage may have been moved. " + "Consider moving first and then aliasing later to resolve the issue">, InGroup, DefaultIgnore; +def warn_lifetime_safety_invalidation + : Warning<"%select{object whose reference is captured|parameter}0 is later invalidated">, + InGroup, + DefaultIgnore; + def warn_lifetime_safety_dangling_field : Warning<"address of stack memory escapes to a field">, InGroup, DefaultIgnore; +def warn_lifetime_safety_dangling_field_moved + : Warning<"address of stack memory escapes to a field. " + "This could be a false positive as the storage may have been moved. " + "Consider moving first and then aliasing later to resolve the issue">, + InGroup, + DefaultIgnore; def note_lifetime_safety_used_here : Note<"later used here">; +def note_lifetime_safety_invalidated_here : Note<"invalidated here">; def note_lifetime_safety_destroyed_here : Note<"destroyed here">; def note_lifetime_safety_returned_here : Note<"returned here">; +def note_lifetime_safety_moved_here : Note<"potentially moved here">; def note_lifetime_safety_dangling_field_here: Note<"this field dangles">; def note_lifetime_safety_escapes_to_field_here: Note<"escapes to this field">; @@ -11317,6 +11341,8 @@ def err_builtin_requires_language : Error<"'%0' is only available in %1">; def err_constant_integer_arg_type : Error< "argument to %0 must be a constant integer">; +def err_constant_integer_last_arg_type + : Error<"last argument to %0 must be a constant integer">; def ext_mixed_decls_code : Extension< "mixing declarations and code is a C99 extension">, @@ -13142,6 +13168,8 @@ def err_builtin_matrix_stride_too_small: Error< "stride must be greater or equal to the number of rows">; def err_builtin_matrix_invalid_dimension: Error< "%0 dimension is outside the allowed range [1, %1]">; +def err_builtin_matrix_invalid_member + : Error<"invalid matrix member '%0' expected %1">; def warn_mismatched_import : Warning< "import %select{module|name}0 (%1) does not match the import %select{module|name}0 (%2) of the " @@ -13413,6 +13441,17 @@ def err_hlsl_builtin_scalar_vector_mismatch "%select{all|second and third}0 arguments to %1 must be of scalar or " "vector type with matching scalar element type%diff{: $ vs $|}2,3">; +def err_hlsl_matrix_element_not_in_bounds + : Error<"matrix %select{row|column}0 element accessor is out of bounds of " + "%select{zero|one}1 based indexing">; + +def err_hlsl_matrix_index_out_of_bounds + : Error<"matrix %select{row|column}0 index %1 is out of bounds of " + "%select{rows|columns}0 size %2">; + +def err_hlsl_matrix_swizzle_invalid_length + : Error<"matrix swizzle length must be between 1 and 4 but is %0">; + def warn_hlsl_impcast_vector_truncation : Warning< "implicit conversion truncates vector: %0 to %1">, InGroup; @@ -13892,6 +13931,13 @@ def note_amdgcn_load_lds_size_valid_value : Note<"size must be %select{1, 2, or def err_amdgcn_coop_atomic_invalid_as : Error<"cooperative atomic requires a global or generic pointer">; +def warn_amdgpu_s_wait_event_mask_no_effect_target : + Warning<"event mask has no effect for target">, + InGroup>; + +def note_amdgpu_s_wait_event_suggested_value : + Note<"value of 2 valid for export_ready for gfx11 and gfx12+">; + def warn_comparison_in_enum_initializer : Warning< "comparison operator '%0' is potentially a typo for a shift operator '%1'">, InGroup>; diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index ba12e522f331f..45e2777def4fa 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -510,6 +510,7 @@ LANGOPT(EnableLifetimeSafetyInference, 1, 0, NotCompatible, "Lifetime safety inf LANGOPT(EnableLifetimeSafetyTUAnalysis, 1, 0, NotCompatible, "Lifetime safety at translation-unit end, analyzing functions in call graph post-order for C++") LANGOPT(PreserveVec3Type, 1, 0, NotCompatible, "Preserve 3-component vector type") +LANGOPT(Reflection , 1, 0, NotCompatible, "C++26 Reflection") #undef LANGOPT #undef ENUM_LANGOPT diff --git a/clang/include/clang/Basic/ObjCRuntime.h b/clang/include/clang/Basic/ObjCRuntime.h index df42b43898611..efb7c6692bfcf 100644 --- a/clang/include/clang/Basic/ObjCRuntime.h +++ b/clang/include/clang/Basic/ObjCRuntime.h @@ -110,6 +110,7 @@ class ObjCRuntime { case llvm::Triple::mips64: return !(getVersion() >= VersionTuple(1, 9)); case llvm::Triple::riscv64: + case llvm::Triple::riscv64be: return !(getVersion() >= VersionTuple(2, 2)); default: return true; diff --git a/clang/include/clang/Basic/OffloadArch.h b/clang/include/clang/Basic/OffloadArch.h index 31a56b47cbb29..558cd32a13cb8 100644 --- a/clang/include/clang/Basic/OffloadArch.h +++ b/clang/include/clang/Basic/OffloadArch.h @@ -102,6 +102,7 @@ enum class OffloadArch { GFX1151, GFX1152, GFX1153, + GFX1170, GFX12_GENERIC, GFX1200, GFX1201, diff --git a/clang/include/clang/Basic/StmtNodes.td b/clang/include/clang/Basic/StmtNodes.td index b08b9fe3b9271..cb869cc210627 100644 --- a/clang/include/clang/Basic/StmtNodes.td +++ b/clang/include/clang/Basic/StmtNodes.td @@ -93,6 +93,7 @@ def CStyleCastExpr : StmtNode; def OMPArrayShapingExpr : StmtNode; def CompoundLiteralExpr : StmtNode; def ExtVectorElementExpr : StmtNode; +def MatrixElementExpr : StmtNode; def InitListExpr : StmtNode; def DesignatedInitExpr : StmtNode; def DesignatedInitUpdateExpr : StmtNode; @@ -179,6 +180,9 @@ def CoyieldExpr : StmtNode; def ConceptSpecializationExpr : StmtNode; def RequiresExpr : StmtNode; +// c++ 26 reflection +def CXXReflectExpr : StmtNode; + // Obj-C Expressions. def ObjCStringLiteral : StmtNode; def ObjCBoxedExpr : StmtNode; diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 8803a3be7654d..ec6cd2be7c3c5 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -1578,6 +1578,9 @@ class TargetInfo : public TransferrableTargetInfo, return true; if (getTriple().getArch() == llvm::Triple::ArchType::avr) return true; + if (getTriple().isOSAIX()) + return getTriple().getOSMajorVersion() == 0 || + getTriple().getOSVersion() >= VersionTuple(7, 2); return getTriple().isOSBinFormatELF() && ((getTriple().isOSLinux() && !getTriple().isMusl()) || getTriple().isOSFreeBSD()); diff --git a/clang/include/clang/Basic/TargetOSMacros.def b/clang/include/clang/Basic/TargetOSMacros.def index f4f3276ad1c25..45999b926fdc5 100644 --- a/clang/include/clang/Basic/TargetOSMacros.def +++ b/clang/include/clang/Basic/TargetOSMacros.def @@ -56,4 +56,7 @@ TARGET_OS(TARGET_OS_UIKITFORMAC, Triple.isMacCatalystEnvironment()) // UEFI target. TARGET_OS(TARGET_OS_UEFI, Triple.isUEFI()) +// General targets. +TARGET_OS(TARGET_OS_FIRMWARE, Triple.isOSFirmware()) + #undef TARGET_OS diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def index 4ee4aa8b31f65..84339c8b64db9 100644 --- a/clang/include/clang/Basic/TokenKinds.def +++ b/clang/include/clang/Basic/TokenKinds.def @@ -238,6 +238,7 @@ PUNCTUATOR(greatergreater, ">>") PUNCTUATOR(greaterequal, ">=") PUNCTUATOR(greatergreaterequal, ">>=") PUNCTUATOR(caret, "^") +PUNCTUATOR(caretcaret, "^^") PUNCTUATOR(caretequal, "^=") PUNCTUATOR(pipe, "|") PUNCTUATOR(pipepipe, "||") diff --git a/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h b/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h index 229bf1e205994..eb80b6099a4f3 100644 --- a/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h +++ b/clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h @@ -576,7 +576,7 @@ class CIRBaseBuilderTy : public mlir::OpBuilder { } mlir::Value createSub(mlir::Location loc, mlir::Value lhs, mlir::Value rhs, - OverflowBehavior ob = OverflowBehavior::Saturated) { + OverflowBehavior ob = OverflowBehavior::None) { auto op = cir::BinOp::create(*this, loc, lhs.getType(), cir::BinOpKind::Sub, lhs, rhs); op.setNoUnsignedWrap( diff --git a/clang/include/clang/CIR/Dialect/IR/CIRDialect.td b/clang/include/clang/CIR/Dialect/IR/CIRDialect.td index 079b4cd87d019..3e134d952b8b5 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIRDialect.td +++ b/clang/include/clang/CIR/Dialect/IR/CIRDialect.td @@ -53,6 +53,9 @@ def CIR_Dialect : Dialect { static llvm::StringRef getOperandSegmentSizesAttrName() { return "operandSegmentSizes"; } static llvm::StringRef getNoCallerSavedRegsAttrName() { return "no_caller_saved_registers"; } static llvm::StringRef getNoCallbackAttrName() { return "nocallback"; } + static llvm::StringRef getAllocSizeAttrName() { return "allocsize"; } + static llvm::StringRef getOptimizeForSizeAttrName() { return "optsize"; } + static llvm::StringRef getMinSizeAttrName() { return "minsize"; } // Note: we have to name this with the underscore instead of the dash like // traditional LLVM-IR does, because the LLVM-IR-Dialect doesn't have a way // of forming names with a dash instead of underscore in its auto-generated @@ -60,6 +63,15 @@ def CIR_Dialect : Dialect { // of a [a-zA-Z0-9_] character regex(numbers only if not first), so there is // no way to get an underscore into this, even with escaping. static llvm::StringRef getModularFormatAttrName() { return "modular_format"; } + // NoBuiltins means "don't put builtins into my body", whereas "nobuiltin" + // means "I'm not a builtin, so don't replace me". This is a subtle + // difference, but one that reflects Classic Codegen. + static llvm::StringRef getNoBuiltinsAttrName() { return "nobuiltins"; } + static llvm::StringRef getNoBuiltinAttrName() { return "nobuiltin"; } + static llvm::StringRef getTrapFuncNameAttrName() { return "trap_func_name"; } + static llvm::StringRef getZeroCallUsedRegsAttrName() { return "zero_call_used_regs"; } + static llvm::StringRef getSaveRegParamsAttrName() { return "save_reg_params"; } + static llvm::StringRef getDefaultFuncAttrsAttrName() { return "default_func_attrs"; } void registerAttributes(); void registerTypes(); diff --git a/clang/include/clang/CIR/Dialect/IR/CIROps.td b/clang/include/clang/CIR/Dialect/IR/CIROps.td index 6cebf6e62af6f..906bd247f60ef 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIROps.td +++ b/clang/include/clang/CIR/Dialect/IR/CIROps.td @@ -722,7 +722,7 @@ def CIR_StoreOp : CIR_Op<"store", [ //===----------------------------------------------------------------------===// defvar CIR_ReturnableScopes = [ - "FuncOp", "ScopeOp", "IfOp", "SwitchOp", "CaseOp", + "FuncOp", "ScopeOp", "IfOp", "SwitchOp", "CaseOp", "CleanupScopeOp", "DoWhileOp", "WhileOp", "ForOp", "TryOp" ]; @@ -869,8 +869,9 @@ def CIR_ConditionOp : CIR_Op<"condition", [ //===----------------------------------------------------------------------===// defvar CIR_YieldableScopes = [ - "ArrayCtor", "ArrayDtor", "AwaitOp", "CaseOp", "DoWhileOp", "ForOp", - "GlobalOp", "IfOp", "ScopeOp", "SwitchOp", "TernaryOp", "WhileOp", "TryOp" + "ArrayCtor", "ArrayDtor", "AwaitOp", "CaseOp", "CleanupScopeOp", "DoWhileOp", + "ForOp", "GlobalOp", "IfOp", "ScopeOp", "SwitchOp", "TernaryOp", "TryOp", + "WhileOp" ]; def CIR_YieldOp : CIR_Op<"yield", [ @@ -1087,6 +1088,112 @@ def CIR_ScopeOp : CIR_Op<"scope", [ let hasLLVMLowering = false; } +//===----------------------------------------------------------------------===// +// CleanupScopeOp +//===----------------------------------------------------------------------===// + +def CIR_CleanupKind : CIR_I32EnumAttr<"CleanupKind", "cleanup kind", [ + I32EnumAttrCase<"Normal", 1, "normal">, + I32EnumAttrCase<"EH", 2, "eh">, + I32EnumAttrCase<"All", 3, "all"> +]> { + let genSpecializedAttr = 0; +} + +def CIR_CleanupKindAttr : CIR_EnumAttr { + let summary = "Cleanup kind attribute"; + let description = [{ + Cleanup kind attributes. + }]; + + let cppClassName = "CleanupKindAttr"; + + let skipDefaultBuilders = 1; + let builders = [ + AttrBuilder<(ins CArg<"CleanupKind", + "cir::CleanupKind::All">:$value), [{ + return $_get($_ctxt, value); + }]> + ]; + + let assemblyFormat = [{ + $value + }]; + + let extraClassDeclaration = [{ + bool isNormal() const { + return getValue() == CleanupKind::Normal || + getValue() == CleanupKind::All; + }; + bool isEH() const { + return getValue() == CleanupKind::EH || getValue() == CleanupKind::All; + }; + bool isNormalAndEH() const { return getValue() == CleanupKind::All; }; + }]; +} + +def CIR_CleanupScopeOp : CIR_Op<"cleanup.scope", [ + DeclareOpInterfaceMethods, + RecursivelySpeculatable, AutomaticAllocationScope, NoRegionArguments, + RecursiveMemoryEffects +]> { + let summary = "Represents a scope with associated cleanup code"; + let description = [{ + `cir.cleanup.scope` contains a body region and a cleanup region. The body + region is executed first, and the cleanup region is executed when the body + region is exited, either normally or due to an exception. + + The cleanup kind attribute specifies when the cleanup region should be + executed: + - `none`: No cleanup (cleanup region is empty/unused) + - `normal`: Cleanup is executed only on normal exit + - `eh`: Cleanup is executed only on exception unwinding + - `all`: Cleanup is executed on both normal exit and exception unwinding + + Examples: + + ```mlir + // Cleanup that runs on both normal and exception paths + cir.cleanup.scope { + cir.call @mayThrow() : () -> () + cir.yield + } cleanup all { + cir.call @destructor() : () -> () + cir.yield + } + + // EH-only cleanup (destructor only called on exception) + cir.cleanup.scope { + cir.call @mayThrow() : () -> () + cir.yield + } cleanup eh { + cir.call @destructor() : () -> () + cir.yield + } + ``` + + Both regions must be terminated. If a region has only one block, the + terminator can be left out, and `cir.yield` will be inserted implicitly. + }]; + + let arguments = (ins CIR_CleanupKindAttr:$cleanupKind); + let regions = (region AnyRegion:$bodyRegion, AnyRegion:$cleanupRegion); + + let skipDefaultBuilders = 1; + + let assemblyFormat = [{ + $bodyRegion `cleanup` $cleanupKind $cleanupRegion attr-dict + }]; + + let builders = [ + OpBuilder<(ins "CleanupKind":$cleanupKind, + "llvm::function_ref":$bodyBuilder, + "llvm::function_ref":$cleanupBuilder)> + ]; + + let hasLLVMLowering = false; +} + //===----------------------------------------------------------------------===// // SwitchOp //===----------------------------------------------------------------------===// @@ -3540,6 +3647,39 @@ def CIR_MemCpyOp : CIR_MemOp<"libc.memcpy"> { // TODO: MemMoveOp +//===----------------------------------------------------------------------===// +// MemSetOp +//===----------------------------------------------------------------------===// + +def CIR_MemSetOp : CIR_Op<"libc.memset"> { + let summary = "Equivalent to libc's `memset`"; + let description = [{ + Given the CIR pointer, `dst`, `cir.libc.memset` will set the first `len` + bytes of the memory pointed by `dst` to the specified `val`. + + Examples: + + ```mlir + // Set 2 bytes in a record to 0: + %len = cir.const #cir.int<2> : !u32i + %zero = cir.const #cir.int<0> : !u8i + cir.libc.memset %len bytes at %record to %zero : !cir.ptr, + !s32i, !u64i + ``` + }]; + + let arguments = (ins + Arg:$dst, + CIR_UInt8:$val, + CIR_AnyFundamentalUIntType:$len + ); + + let assemblyFormat = [{ + $len `bytes` `at` $dst `to` $val attr-dict + `:` qualified(type($dst)) `,` type($val) `,` type($len) + }]; +} + //===----------------------------------------------------------------------===// // ReturnAddrOp and FrameAddrOp //===----------------------------------------------------------------------===// @@ -5933,6 +6073,262 @@ def CIR_EhTypeIdOp : CIR_Op<"eh.typeid", }]; } +//===----------------------------------------------------------------------===// +// Flattened EH Operations: EhInitiateOp +//===----------------------------------------------------------------------===// + +def CIR_EhInitiateOp : CIR_Op<"eh.initiate"> { + let summary = "Initiate exception handling in flattened CIR"; + let description = [{ + `cir.eh.initiate` is the first operation in the unwind destination of a + `cir.try_call` operation after CFG flattening. It returns an opaque + `!cir.eh_token` that represents the in-flight exception. + + The `cleanup` attribute indicates that cleanup code must be executed before + the exception is dispatched to any handlers. When present, the operation + will be followed by cleanup code before branching to a `cir.eh.dispatch` + operation. + + The returned token is passed to `cir.begin_cleanup`, `cir.begin_catch`, + or `cir.eh.dispatch` operations. + + Example: + + ```mlir + ^unwind: + %eh_token = cir.eh.initiate : !cir.eh_token + cir.br ^dispatch(%eh_token : !cir.eh_token) + + ^unwind_with_cleanup: + %eh_token = cir.eh.initiate cleanup : !cir.eh_token + cir.br ^cleanup(%eh_token : !cir.eh_token) + ``` + }]; + + let arguments = (ins UnitAttr:$cleanup); + let results = (outs CIR_EhTokenType:$eh_token); + let assemblyFormat = [{ + (`cleanup` $cleanup^)? `:` type($eh_token) attr-dict + }]; + + let hasLLVMLowering = false; +} + +//===----------------------------------------------------------------------===// +// Flattened EH Operations: EhDispatchOp +//===----------------------------------------------------------------------===// + +def CIR_EhDispatchOp : CIR_Op<"eh.dispatch", [ + Terminator +]> { + let summary = "Dispatch to exception handlers based on exception type"; + + let description = [{ + `cir.eh.dispatch` is a terminator operation that dispatches control flow + based on the type of the in-flight exception. It takes an `!cir.eh_token` + as input and branches to an eh handler block based on the exception type. + + The operation contains a list of handlers specified as type-block pairs, + plus either a `catch_all` handler or an `unwind` handler, which continues + unwinding if no catch handler matches. Exactly one of `catch_all` or + `unwind` must be present. + + When the type of the in-flight exception matches a type handler, control + is transfered to the corresponding block with the eh_token as an argument. + The `catch_all` handler, if present, catches any exception not matched by + another type handler. The `unwind` handler is used when no handler is + matched. + + Example: + + ```mlir + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch (#cir.global_view<@_ZTIi> : !cir.ptr) : ^catch_int, + catch (#cir.global_view<@_ZTIPKc> : !cir.ptr) : ^catch_str, + catch_all : ^catch_all + ] + + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch (#cir.global_view : !cir.ptr) : ^catch_int, + unwind : ^continue_unwind + ] + ``` + }]; + + let arguments = (ins + CIR_EhTokenType:$eh_token, + OptionalAttr:$catch_types, + UnitAttr:$default_is_catch_all + ); + + let successors = (successor + AnySuccessor:$default_destination, + VariadicSuccessor:$catch_destinations + ); + + let assemblyFormat = [{ + $eh_token `:` type($eh_token) + custom($catch_types, $catch_destinations, + $default_destination, $default_is_catch_all) + attr-dict + }]; + + let hasLLVMLowering = false; +} + +//===----------------------------------------------------------------------===// +// Flattened EH Operations: BeginCleanupOp +//===----------------------------------------------------------------------===// + +def CIR_BeginCleanupOp : CIR_Op<"begin_cleanup"> { + let summary = "Begin a cleanup block during exception unwinding"; + let description = [{ + `cir.begin_cleanup` marks the beginning of a cleanup handler during + exception unwinding. It takes a `!cir.eh_token` and returns a + `!cir.cleanup_token` that must be passed to the corresponding + `cir.end_cleanup` operation. + + The cleanup code between `cir.begin_cleanup` and `cir.end_cleanup` will be + executed during exception unwinding before control is transferred to + the exception dispatcher. + + Example: + + ```mlir + ^cleanup(%eh_token : !cir.eh_token): + %cleanup_token = cir.begin_cleanup %eh_token : !cir.eh_token + -> !cir.cleanup_token + cir.call @destructor() : () -> () + cir.end_cleanup %cleanup_token : !cir.cleanup_token + cir.br ^dispatch(%eh_token : !cir.eh_token) + ``` + }]; + + let arguments = (ins CIR_EhTokenType:$eh_token); + let results = (outs CIR_CleanupTokenType:$cleanup_token); + let assemblyFormat = [{ + $eh_token `:` type($eh_token) `->` type($cleanup_token) attr-dict + }]; + + let hasLLVMLowering = false; +} + +//===----------------------------------------------------------------------===// +// Flattened EH Operations: EndCleanupOp +//===----------------------------------------------------------------------===// + +def CIR_EndCleanupOp : CIR_Op<"end_cleanup"> { + let summary = "End a cleanup block during exception unwinding"; + let description = [{ + `cir.end_cleanup` marks the end of a cleanup block during exception + unwinding. It takes the `!cir.cleanup_token` returned by the corresponding + `cir.begin_cleanup` operation. + + After the cleanup is complete, control typically transfers to either a + catch dispatch block or continues unwinding via `cir.resume`. + + Example: + + ```mlir + ^cleanup(%eh_token : !cir.eh_token): + %cleanup_token = cir.begin_cleanup %eh_token : !cir.eh_token + -> !cir.cleanup_token + cir.call @destructor() : () -> () + cir.end_cleanup %cleanup_token : !cir.cleanup_token + cir.br ^dispatch(%eh_token : !cir.eh_token) + ``` + }]; + + let arguments = (ins CIR_CleanupTokenType:$cleanup_token); + let assemblyFormat = [{ + $cleanup_token `:` type($cleanup_token) attr-dict + }]; + + let hasLLVMLowering = false; +} + +//===----------------------------------------------------------------------===// +// Flattened EH Operations: BeginCatchOp +//===----------------------------------------------------------------------===// + +def CIR_BeginCatchOp : CIR_Op<"begin_catch"> { + let summary = "Begin a catch handler block"; + let description = [{ + `cir.begin_catch` marks the beginning of a catch handler. It takes a + `!cir.eh_token` and an optional exception type, and returns a + `!cir.catch_token` along with a pointer to the exception object. + + The catch token must be passed to the corresponding `cir.end_catch` + operation. The exception pointer points to the caught exception object + and can be used to access the exception value. + + For `catch(...)` (catch all), the exception type is omitted. + + Example: + + ```mlir + ^catch_int(%eh_token : !cir.eh_token): + %catch_token, %exn_ptr = cir.begin_catch %eh_token + : !cir.eh_token -> (!cir.catch_token, !cir.ptr) + // Handle exception... + cir.end_catch %catch_token : !cir.catch_token + cir.br ^continue + + ^catch_all(%eh_token : !cir.eh_token): + %catch_token, %exn_ptr = cir.begin_catch %eh_token + : !cir.eh_token -> (!cir.catch_token, !cir.ptr) + // Handle exception... + cir.end_catch %catch_token : !cir.catch_token + cir.br ^continue + ``` + }]; + + let arguments = (ins CIR_EhTokenType:$eh_token); + let results = (outs CIR_CatchTokenType:$catch_token, + CIR_PointerType:$exn_ptr); + + let assemblyFormat = [{ + $eh_token `:` type($eh_token) `->` `(` type($catch_token) `,` + qualified(type($exn_ptr)) `)` attr-dict + }]; + + let hasLLVMLowering = false; +} + +//===----------------------------------------------------------------------===// +// Flattened EH Operations: EndCatchOp +//===----------------------------------------------------------------------===// + +def CIR_EndCatchOp : CIR_Op<"end_catch"> { + let summary = "End a catch handler block"; + let description = [{ + `cir.end_catch` marks the end of a catch handler block. It takes the + `!cir.catch_token` returned by the corresponding `cir.begin_catch` + operation. + + All control flow paths through a catch handler must pass through a single + `cir.end_catch` operation before leaving the catch block. + + Example: + + ```mlir + ^catch_int(%eh_token : !cir.eh_token): + %catch_token, %exn_ptr = cir.begin_catch %eh_token + : !cir.eh_token -> (!cir.catch_token, !cir.ptr) + // Handle exception... + cir.end_catch %catch_token : !cir.catch_token + cir.br ^continue + ``` + }]; + + let arguments = (ins CIR_CatchTokenType:$catch_token); + let assemblyFormat = [{ + $catch_token `:` type($catch_token) attr-dict + }]; + + let hasLLVMLowering = false; +} + //===----------------------------------------------------------------------===// // Atomic operations //===----------------------------------------------------------------------===// @@ -6037,11 +6433,14 @@ def CIR_AtomicXchgOp : CIR_Op<"atomic.xchg", [ Arg:$ptr, CIR_AnyType:$val, Arg:$mem_order, + CIR_SyncScopeKind:$sync_scope, UnitAttr:$is_volatile ); let assemblyFormat = [{ - $mem_order (`volatile` $is_volatile^)? + $mem_order + `syncscope` `(` $sync_scope `)` + (`volatile` $is_volatile^)? $ptr `,` $val `:` functional-type(operands, results) attr-dict }]; diff --git a/clang/include/clang/CIR/Dialect/IR/CIRTypes.td b/clang/include/clang/CIR/Dialect/IR/CIRTypes.td index 5ba7726e9b1a6..ea2113432d5b5 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIRTypes.td +++ b/clang/include/clang/CIR/Dialect/IR/CIRTypes.td @@ -753,6 +753,46 @@ def CIR_RecordType : CIR_Type<"Record", "record", [ def CIRRecordType : Type< CPred<"::mlir::isa<::cir::RecordType>($_self)">, "CIR record type">; +//===----------------------------------------------------------------------===// +// Exception Handling Token Types +//===----------------------------------------------------------------------===// + +def CIR_EhTokenType : CIR_Type<"EhToken", "eh_token"> { + let summary = "CIR exception handling token type"; + let description = [{ + `!cir.eh_token` is an opaque type used to track exception handling state + in flattened CIR. It is returned by `cir.eh.initiate` and passed to + `cir.eh.dispatch`, `cir.begin_cleanup`, and `cir.begin_catch` operations. + + This token represents an in-flight exception and is used during ABI-lowering + to generate the appropriate exception handling code. + }]; +} + +def CIR_CleanupTokenType : CIR_Type<"CleanupToken", "cleanup_token"> { + let summary = "CIR cleanup token type"; + let description = [{ + `!cir.cleanup_token` is an opaque type used to track cleanup handling state + in flattened CIR. It is returned by `cir.begin_cleanup` and consumed by + `cir.end_cleanup`. + + This token ensures that cleanup regions are properly paired and allows + the ABI lowering pass to generate appropriate cleanup handling code. + }]; +} + +def CIR_CatchTokenType : CIR_Type<"CatchToken", "catch_token"> { + let summary = "CIR catch token type"; + let description = [{ + `!cir.catch_token` is an opaque type used to track catch handling state + in flattened CIR. It is returned by `cir.begin_catch` and consumed by + `cir.end_catch`. + + This token ensures that catch handlers are properly paired and allows + the ABI lowering pass to generate appropriate exception catching code. + }]; +} + //===----------------------------------------------------------------------===// // Global type constraints //===----------------------------------------------------------------------===// @@ -760,7 +800,8 @@ def CIRRecordType : Type< def CIR_AnyType : AnyTypeOf<[ CIR_VoidType, CIR_BoolType, CIR_ArrayType, CIR_VectorType, CIR_IntType, CIR_AnyFloatType, CIR_PointerType, CIR_FuncType, CIR_RecordType, - CIR_ComplexType, CIR_VPtrType, CIR_DataMemberType, CIR_MethodType + CIR_ComplexType, CIR_VPtrType, CIR_DataMemberType, CIR_MethodType, + CIR_EhTokenType, CIR_CleanupTokenType, CIR_CatchTokenType ]>; #endif // CLANG_CIR_DIALECT_IR_CIRTYPES_TD diff --git a/clang/include/clang/CIR/Dialect/Passes.h b/clang/include/clang/CIR/Dialect/Passes.h index 98eaf884347ed..161f365bb1402 100644 --- a/clang/include/clang/CIR/Dialect/Passes.h +++ b/clang/include/clang/CIR/Dialect/Passes.h @@ -18,12 +18,14 @@ namespace clang { class ASTContext; } + namespace mlir { std::unique_ptr createCIRCanonicalizePass(); std::unique_ptr createCIRFlattenCFGPass(); std::unique_ptr createCIRSimplifyPass(); std::unique_ptr createCXXABILoweringPass(); +std::unique_ptr createTargetLoweringPass(); std::unique_ptr createHoistAllocasPass(); std::unique_ptr createLoweringPreparePass(); std::unique_ptr createLoweringPreparePass(clang::ASTContext *astCtx); diff --git a/clang/include/clang/CIR/Dialect/Passes.td b/clang/include/clang/CIR/Dialect/Passes.td index 48c409fa83cee..ef5308ffffd19 100644 --- a/clang/include/clang/CIR/Dialect/Passes.td +++ b/clang/include/clang/CIR/Dialect/Passes.td @@ -83,15 +83,72 @@ def GotoSolver : Pass<"cir-goto-solver"> { } def CXXABILowering : Pass<"cir-cxxabi-lowering", "mlir::ModuleOp"> { - let summary = "Lower abstract C++ operations to target-specific ABI form"; + let summary = "Lower CIR according to C++ ABI requirements"; let description = [{ - This pass lowers high-level operations that represent C++ constructs in a - target-independent way to concrete, target specific operations. + This pass lowers CIR operations and types that represent high-level C/C++ + constructs to a more fundamental form according to the target ABI + requirements. + + See the description of the `TargetLowering` pass for the difference between + this pass and the `TargetLowering` pass. }]; let constructor = "mlir::createCXXABILoweringPass()"; let dependentDialects = ["cir::CIRDialect"]; } +def TargetLowering : Pass<"cir-target-lowering", "mlir::ModuleOp"> { + let summary = "Lower CIR to a target-specific form"; + let description = [{ + This pass lowers CIR operations from a target-agnostic form to a + target-specific form without considering ABI requirements. + + CIR has three passes in its lowering pipeline that transform input CIR + according to target-specific requirements, scheduled in the pipeline by the + following order: + + 1. The `TargetLowering` pass. + 2. The `CXXABILowering` pass. + 3. The `CallConvLowering` pass (not implemented yet). + + The `TargetLowering` pass acts more like a legalization pass. It ensures + every operation in CIR conforms to the target's constraints. An example + would be the handling of synchronization scopes of atomic operations. The + x86 family of targets only support a system-wide synchronization scope, thus + any atomic operations with a different synchronization scope would be + transformed to use the system-wide scope in this pass. + + The `CXXABILowering` pass and the (not yet implemented) `CallConvLowering` + pass transform the CIR according to the target's ABI requirements. The + former handles all ABI-related lowering except for calling convention + handling, which is handled specifically in the latter. Example + transformations that the `CXXABILowering` pass could make include: + + - Replace C/C++ types that have an ABI-defined layout with more + fundamental types corresponding to the ABI requirements. For example, + the layout of the pointer-to-data-member type in C++ is ABI-defined, + thus the `CXXABILowering` pass would replace all occurrences of this + type according to the ABI requirements. With a typical target ABI, it + will be replaced by the `ptrdiff_t` type since this is the type most + ABIs use for the layout of the pointer-to-data-member type. + - Replace CIR operations that have ABI-dependent implementations with more + fundamental operations. For example, the `dynamic_cast` operator in C++ + is implemented in an ABI-dependent way, typically by calling into a + library function provided by the implementation. The `CXXABILowering` + pass would thus replace all `cir.dyn_cast` operations with corresponding + library function calls. + + The `CallConvLowering` pass is dedicated to handle calling conventions. It + rewrites function signatures according to calling convention requirements, + and updates function body and call sites accordingly. For example, when + passing a large struct by value in C/C++, most ABIs require passing a + pointer to a copy of the struct instead. Thus, the `CallConvLowering` pass + would rewrite function signatures that take a value of a large struct type + to take a pointer to the struct type instead, and update the function body + and the call sites accordingly. + }]; + let constructor = "mlir::createTargetLoweringPass()"; + let dependentDialects = ["cir::CIRDialect"]; +} def LoweringPrepare : Pass<"cir-lowering-prepare"> { let summary = "Lower to more fine-grained CIR operations before lowering to " diff --git a/clang/include/clang/CIR/MissingFeatures.h b/clang/include/clang/CIR/MissingFeatures.h index cdd9fb950b8b2..5cb0991326a3c 100644 --- a/clang/include/clang/CIR/MissingFeatures.h +++ b/clang/include/clang/CIR/MissingFeatures.h @@ -238,6 +238,7 @@ struct MissingFeatures { static bool cleanupAfterErrorDiags() { return false; } static bool cleanupAppendInsts() { return false; } static bool cleanupBranchThrough() { return false; } + static bool cleanupDeactivationScope() { return false; } static bool cleanupIndexAndBIAdjustment() { return false; } static bool cleanupWithPreservedValues() { return false; } static bool cleanupsToDeactivate() { return false; } @@ -370,15 +371,9 @@ struct MissingFeatures { static bool stringTypeWithDifferentArraySize() { return false; } // Future CIR operations - static bool awaitOp() { return false; } static bool callOp() { return false; } - static bool ifOp() { return false; } - static bool labelOp() { return false; } - static bool ptrDiffOp() { return false; } static bool llvmLoweringPtrDiffConsidersPointee() { return false; } - static bool ptrStrideOp() { return false; } static bool switchOp() { return false; } - static bool throwOp() { return false; } static bool tryOp() { return false; } static bool vecTernaryOp() { return false; } static bool zextOp() { return false; } diff --git a/clang/include/clang/Driver/Driver.h b/clang/include/clang/Driver/Driver.h index b7bd1bc8aab49..f7c138027bdae 100644 --- a/clang/include/clang/Driver/Driver.h +++ b/clang/include/clang/Driver/Driver.h @@ -546,8 +546,7 @@ class Driver { /// issue a diagnostic and return false. /// If TypoCorrect is true and the file does not exist, see if it looks /// like a likely typo for a flag and if so print a "did you mean" blurb. - bool DiagnoseInputExistence(const llvm::opt::DerivedArgList &Args, - StringRef Value, types::ID Ty, + bool DiagnoseInputExistence(StringRef Value, types::ID Ty, bool TypoCorrect) const; /// BuildJobs - Bind actions to concrete tools and translate diff --git a/clang/include/clang/Driver/SanitizerArgs.h b/clang/include/clang/Driver/SanitizerArgs.h index aa8aa9be287c6..ed2eb6852b124 100644 --- a/clang/include/clang/Driver/SanitizerArgs.h +++ b/clang/include/clang/Driver/SanitizerArgs.h @@ -68,6 +68,7 @@ class SanitizerArgs { bool TsanFuncEntryExit = true; bool TsanAtomics = true; bool MinimalRuntime = false; + bool TrapLoop = false; bool TysanOutlineInstrumentation = true; bool HandlerPreserveAllRegs = false; // True if cross-dso CFI support if provided by the system (i.e. Android). @@ -110,6 +111,7 @@ class SanitizerArgs { bool needsUbsanRt() const; bool needsUbsanCXXRt() const; bool requiresMinimalRuntime() const { return MinimalRuntime; } + bool needsUbsanLoopDetectRt() const { return TrapLoop; } bool needsDfsanRt() const { return Sanitizers.has(SanitizerKind::DataFlow); } bool needsSafeStackRt() const { return SafeStackRuntime; } bool needsCfiCrossDsoRt() const; diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index 43bea4b80cb8a..57ae14304b969 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -3520,7 +3520,8 @@ struct FormatStyle { /// Keep the form feed character if it's immediately preceded and followed by /// a newline. Multiple form feeds and newlines within a whitespace range are /// replaced with a single newline and form feed followed by the remaining - /// newlines. + /// newlines. (See + /// www.gnu.org/prep/standards/html_node/Formatting.html#:~:text=formfeed.) /// \version 20 bool KeepFormFeed; diff --git a/clang/include/clang/Frontend/CompilerInstance.h b/clang/include/clang/Frontend/CompilerInstance.h index a3a4c7e55b72b..217efa3fe756e 100644 --- a/clang/include/clang/Frontend/CompilerInstance.h +++ b/clang/include/clang/Frontend/CompilerInstance.h @@ -872,20 +872,24 @@ class CompilerInstance : public ModuleLoader { class ThreadSafeCloneConfig { IntrusiveRefCntPtr VFS; DiagnosticConsumer &DiagConsumer; + std::shared_ptr ModCache; std::shared_ptr ModuleDepCollector; public: ThreadSafeCloneConfig( IntrusiveRefCntPtr VFS, - DiagnosticConsumer &DiagConsumer, + DiagnosticConsumer &DiagConsumer, std::shared_ptr ModCache, std::shared_ptr ModuleDepCollector = nullptr) : VFS(std::move(VFS)), DiagConsumer(DiagConsumer), + ModCache(std::move(ModCache)), ModuleDepCollector(std::move(ModuleDepCollector)) { assert(this->VFS && "Clone config requires non-null VFS"); + assert(this->ModCache && "Clone config requires non-null ModuleCache"); } IntrusiveRefCntPtr getVFS() const { return VFS; } DiagnosticConsumer &getDiagConsumer() const { return DiagConsumer; } + std::shared_ptr getModuleCache() const { return ModCache; } std::shared_ptr getModuleDepCollector() const { return ModuleDepCollector; } diff --git a/clang/include/clang/Options/Options.td b/clang/include/clang/Options/Options.td index 5ecb516c2cf68..155f19fb00bd8 100644 --- a/clang/include/clang/Options/Options.td +++ b/clang/include/clang/Options/Options.td @@ -2724,6 +2724,13 @@ defm sanitize_handler_preserve_all_regs NegFlag>, Group; +defm sanitize_trap_loop : BoolOption<"f", "sanitize-trap-loop", + CodeGenOpts<"SanitizeTrapLoop">, DefaultFalse, + PosFlag, + NegFlag>, + Group; def fsanitize_link_runtime : Flag<["-"], "fsanitize-link-runtime">, Group; def fno_sanitize_link_runtime : Flag<["-"], "fno-sanitize-link-runtime">, @@ -2965,6 +2972,20 @@ attribute as undefined behavior. (And, thus the optimizer may assume that any pointer used in such a way must not have been null and optimize away the branches accordingly.) On by default.}]>; +defm lifetime_dse + : BoolFOption<"lifetime-dse", CodeGenOpts<"StrictLifetimes">, DefaultTrue, + NegFlag, + PosFlag, + BothFlags<[], [ClangOption, CLOption]>>, + DocBrief< + [{When enabled, mark an object dead after its destructor returns which allows the +the optimizer to perform more aggressive optimizations in some cases, particularly dead +store elimination.}]>; + defm use_line_directives : BoolFOption<"use-line-directives", PreprocessorOutputOpts<"UseLineDirectives">, DefaultFalse, PosFlag, NegFlag>; +defm reflection : BoolFOption<"reflection", + LangOpts<"Reflection">, DefaultFalse, + PosFlag, + NegFlag>, ShouldParseIf; defm sized_deallocation : BoolFOption<"sized-deallocation", LangOpts<"SizedDeallocation">, Default, PosFlag, @@ -3986,9 +4012,13 @@ def fno_openmp_assume_threads_oversubscription : Flag<["-"], "fno-openmp-assume- def fopenmp_assume_no_thread_state : Flag<["-"], "fopenmp-assume-no-thread-state">, HelpText<"Assert no thread in a parallel region modifies an ICV">, MarshallingInfoFlag>; +def fno_openmp_assume_no_thread_state : Flag<["-"], "fno-openmp-assume-no-thread-state">, + HelpText<"Assert that a thread in a parallel region may modify an ICV">; def fopenmp_assume_no_nested_parallelism : Flag<["-"], "fopenmp-assume-no-nested-parallelism">, HelpText<"Assert no nested parallel regions in the GPU">, MarshallingInfoFlag>; +def fno_openmp_assume_no_nested_parallelism : Flag<["-"], "fno-openmp-assume-no-nested-parallelism">, + HelpText<"Assert that a nested parallel region may be used in the GPU">; } // let Group = f_Group } // let Visibility = [ClangOption, CC1Option, FC1Option] @@ -4012,6 +4042,13 @@ def fopenmp_target_new_runtime : Flag<["-"], "fopenmp-target-new-runtime">, Group, Flags<[HelpHidden]>, Visibility<[ClangOption, CC1Option]>; def fno_openmp_target_new_runtime : Flag<["-"], "fno-openmp-target-new-runtime">, Group, Flags<[HelpHidden]>, Visibility<[ClangOption, CC1Option]>; +def fopenmp_target_fast : Flag<["-"], "fopenmp-target-fast">, + Group, Flags<[NoArgumentUnused, HelpHidden]>, + Visibility<[ClangOption]>, + HelpText<"Assert common GPU usage patterns to enable OpenMP runtime optimizations">; +def fno_openmp_target_fast : Flag<["-"], "fno-openmp-target-fast">, + Group, Flags<[NoArgumentUnused, HelpHidden]>, + Visibility<[ClangOption]>; defm openmp_optimistic_collapse : BoolFOption<"openmp-optimistic-collapse", LangOpts<"OpenMPOptimisticCollapse">, DefaultFalse, PosFlag, diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h index 2b1dcabc9a194..5ae02e2b4e8ad 100644 --- a/clang/include/clang/Parse/Parser.h +++ b/clang/include/clang/Parse/Parser.h @@ -150,6 +150,7 @@ enum class TentativeCXXTypeIdContext { AsTemplateArgument, InTrailingReturnType, AsGenericSelectionArgument, + AsReflectionOperand }; /// The kind of attribute specifier we have found. @@ -5152,6 +5153,15 @@ class Parser : public CodeCompletionHandler { ///@} + //===--------------------------------------------------------------------===// + // Reflection parsing + + /// ParseCXXReflectExpression - parses the operand of reflection operator. + /// + /// \returns on success, an expression holding the constructed CXXReflectExpr; + /// on failure, an ExprError. + ExprResult ParseCXXReflectExpression(); + // // // ------------------------------------------------------------------------- diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 0ba3daab764b7..9ae2fa52a441a 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -14838,6 +14838,12 @@ class Sema final : public SemaBase { /// Implementations are in SemaConcept.cpp ///@{ +public: + ExprResult ActOnCXXReflectExpr(SourceLocation OpLoc, TypeSourceInfo *TSI); + + ExprResult BuildCXXReflectExpr(SourceLocation OperatorLoc, + TypeSourceInfo *TSI); + public: void PushSatisfactionStackEntry(const NamedDecl *D, const llvm::FoldingSetNodeID &ID) { @@ -15344,6 +15350,17 @@ class Sema final : public SemaBase { bool AllowArrayTypes, bool OverrideExisting); + /// Check whether the given variable declaration has a size that fits within + /// the address space it is declared in. This issues a diagnostic if not. + /// + /// \param VD The variable declaration to check the size of. + /// + /// \param AS The address space to check the size of \p VD against. + /// + /// \returns true if the variable's size fits within the address space, false + /// otherwise. + bool CheckVarDeclSizeAddressSpace(const VarDecl *VD, LangAS AS); + /// Get the type of expression E, triggering instantiation to complete the /// type if necessary -- that is, if the expression refers to a templated /// static data member of incomplete array type. diff --git a/clang/include/clang/Sema/SemaAMDGPU.h b/clang/include/clang/Sema/SemaAMDGPU.h index bac812a9d4fcf..e080ccd008863 100644 --- a/clang/include/clang/Sema/SemaAMDGPU.h +++ b/clang/include/clang/Sema/SemaAMDGPU.h @@ -26,7 +26,14 @@ class SemaAMDGPU : public SemaBase { bool CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall); + /// Emits a diagnostic if the \p E is not an atomic ordering encoded in the C + /// ABI format, or if the atomic ordering is not valid for the operation type + /// as defined by \p MayLoad and \p MayStore. \returns true if a diagnostic + /// was emitted. + bool checkAtomicOrderingCABIArg(Expr *E, bool MayLoad, bool MayStore); + bool checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore); + bool checkAtomicMonitorLoad(CallExpr *TheCall); bool checkMovDPPFunctionCall(CallExpr *TheCall, unsigned NumArgs, unsigned NumDataArgs); diff --git a/clang/include/clang/Sema/SemaHLSL.h b/clang/include/clang/Sema/SemaHLSL.h index 99d8ed137b0c2..020a4dc44ee7f 100644 --- a/clang/include/clang/Sema/SemaHLSL.h +++ b/clang/include/clang/Sema/SemaHLSL.h @@ -215,6 +215,10 @@ class SemaHLSL : public SemaBase { bool transformInitList(const InitializedEntity &Entity, InitListExpr *Init); bool handleInitialization(VarDecl *VDecl, Expr *&Init); void deduceAddressSpace(VarDecl *Decl); + QualType checkMatrixComponent(Sema &S, QualType baseType, ExprValueKind &VK, + SourceLocation OpLoc, + const IdentifierInfo *CompName, + SourceLocation CompLoc); private: // HLSL resource type attributes need to be processed all at once. diff --git a/clang/include/clang/Serialization/ASTBitCodes.h b/clang/include/clang/Serialization/ASTBitCodes.h index 5a86d540e5d0b..d72f1f9db86b2 100644 --- a/clang/include/clang/Serialization/ASTBitCodes.h +++ b/clang/include/clang/Serialization/ASTBitCodes.h @@ -1696,6 +1696,9 @@ enum StmtCode { /// An ExtVectorElementExpr record. EXPR_EXT_VECTOR_ELEMENT, + /// A MatrixElementExpr record. + EXPR_MATRIX_ELEMENT, + /// An InitListExpr record. EXPR_INIT_LIST, @@ -1928,6 +1931,9 @@ enum StmtCode { EXPR_CONCEPT_SPECIALIZATION, // ConceptSpecializationExpr EXPR_REQUIRES, // RequiresExpr + // Reflection + EXPR_REFLECT, + // CUDA EXPR_CUDA_KERNEL_CALL, // CUDAKernelCallExpr diff --git a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td index 3af694ceda1e3..58e785d5ca36f 100644 --- a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td +++ b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td @@ -347,6 +347,10 @@ def ErrnoModeling : Checker<"Errno">, HelpText<"Make the special value 'errno' available to other checkers.">, Documentation; +def OpaqueSTLFunctionsModeling : Checker<"OpaqueSTLFunctionsModeling">, + HelpText<"Model opaque, conservative evaluation of some STL functions">, + Documentation; + def TrustNonnullChecker : Checker<"TrustNonnull">, HelpText<"Trust that returns from framework methods annotated with _Nonnull " "are not null">, diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h index b2b4e8729af25..75a24827d3e03 100644 --- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h +++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h @@ -243,21 +243,12 @@ class NodeBuilder { protected: const NodeBuilderContext &C; - /// Specifies if the builder results have been finalized. For example, if it - /// is set to false, autotransitions are yet to be generated. - bool Finalized; - bool HasGeneratedNodes = false; /// The frontier set - a set of nodes which need to be propagated after /// the builder dies. ExplodedNodeSet &Frontier; - /// Checks if the results are ready. - virtual bool checkResults() { - return Finalized; - } - bool hasNoSinksInFrontier() { for (const auto I : Frontier) if (I->isSink()) @@ -265,9 +256,6 @@ class NodeBuilder { return true; } - /// Allow subclasses to finalize results before result_begin() is executed. - virtual void finalizeResults() {} - ExplodedNode *generateNodeImpl(const ProgramPoint &PP, ProgramStateRef State, ExplodedNode *Pred, @@ -275,14 +263,14 @@ class NodeBuilder { public: NodeBuilder(ExplodedNode *SrcNode, ExplodedNodeSet &DstSet, - const NodeBuilderContext &Ctx, bool F = true) - : C(Ctx), Finalized(F), Frontier(DstSet) { + const NodeBuilderContext &Ctx) + : C(Ctx), Frontier(DstSet) { Frontier.Add(SrcNode); } NodeBuilder(const ExplodedNodeSet &SrcSet, ExplodedNodeSet &DstSet, - const NodeBuilderContext &Ctx, bool F = true) - : C(Ctx), Finalized(F), Frontier(DstSet) { + const NodeBuilderContext &Ctx) + : C(Ctx), Frontier(DstSet) { Frontier.insert(SrcSet); assert(hasNoSinksInFrontier()); } @@ -309,25 +297,14 @@ class NodeBuilder { return generateNodeImpl(PP, State, Pred, true); } - const ExplodedNodeSet &getResults() { - finalizeResults(); - assert(checkResults()); - return Frontier; - } + const ExplodedNodeSet &getResults() { return Frontier; } using iterator = ExplodedNodeSet::iterator; /// Iterators through the results frontier. - iterator begin() { - finalizeResults(); - assert(checkResults()); - return Frontier.begin(); - } + iterator begin() { return Frontier.begin(); } - iterator end() { - finalizeResults(); - return Frontier.end(); - } + iterator end() { return Frontier.end(); } const NodeBuilderContext &getContext() { return C; } bool hasGeneratedNodes() { return HasGeneratedNodes; } @@ -342,41 +319,6 @@ class NodeBuilder { void addNodes(ExplodedNode *N) { Frontier.Add(N); } }; -/// \class NodeBuilderWithSinks -/// This node builder keeps track of the generated sink nodes. -class NodeBuilderWithSinks: public NodeBuilder { - void anchor() override; - -protected: - SmallVector sinksGenerated; - ProgramPoint &Location; - -public: - NodeBuilderWithSinks(ExplodedNode *Pred, ExplodedNodeSet &DstSet, - const NodeBuilderContext &Ctx, ProgramPoint &L) - : NodeBuilder(Pred, DstSet, Ctx), Location(L) {} - - ExplodedNode *generateNode(ProgramStateRef State, - ExplodedNode *Pred, - const ProgramPointTag *Tag = nullptr) { - const ProgramPoint &LocalLoc = (Tag ? Location.withTag(Tag) : Location); - return NodeBuilder::generateNode(LocalLoc, State, Pred); - } - - ExplodedNode *generateSink(ProgramStateRef State, ExplodedNode *Pred, - const ProgramPointTag *Tag = nullptr) { - const ProgramPoint &LocalLoc = (Tag ? Location.withTag(Tag) : Location); - ExplodedNode *N = NodeBuilder::generateSink(LocalLoc, State, Pred); - if (N && N->isSink()) - sinksGenerated.push_back(N); - return N; - } - - const SmallVectorImpl &getSinks() const { - return sinksGenerated; - } -}; - /// \class StmtNodeBuilder /// This builder class is useful for generating nodes that resulted from /// visiting a statement. The main difference from its parent NodeBuilder is @@ -401,8 +343,7 @@ class StmtNodeBuilder: public NodeBuilder { NodeBuilder *Enclosing = nullptr) : NodeBuilder(SrcSet, DstSet, Ctx), EnclosingBldr(Enclosing) { if (EnclosingBldr) - for (const auto I : SrcSet) - EnclosingBldr->takeNodes(I); + EnclosingBldr->takeNodes(SrcSet); } ~StmtNodeBuilder() override; @@ -461,48 +402,25 @@ class BranchNodeBuilder: public NodeBuilder { }; class IndirectGotoNodeBuilder { - CoreEngine& Eng; + const CoreEngine &Eng; const CFGBlock *Src; const CFGBlock &DispatchBlock; const Expr *E; ExplodedNode *Pred; public: - IndirectGotoNodeBuilder(ExplodedNode *pred, const CFGBlock *src, - const Expr *e, const CFGBlock *dispatch, CoreEngine* eng) - : Eng(*eng), Src(src), DispatchBlock(*dispatch), E(e), Pred(pred) {} + IndirectGotoNodeBuilder(ExplodedNode *Pred, const CFGBlock *Src, + const Expr *E, const CFGBlock *Dispatch, + const CoreEngine *Eng) + : Eng(*Eng), Src(Src), DispatchBlock(*Dispatch), E(E), Pred(Pred) {} - class iterator { - friend class IndirectGotoNodeBuilder; + using iterator = CFGBlock::const_succ_iterator; - CFGBlock::const_succ_iterator I; + iterator begin() { return DispatchBlock.succ_begin(); } + iterator end() { return DispatchBlock.succ_end(); } - iterator(CFGBlock::const_succ_iterator i) : I(i) {} - - public: - // This isn't really a conventional iterator. - // We just implement the deref as a no-op for now to make range-based for - // loops work. - const iterator &operator*() const { return *this; } - - iterator &operator++() { ++I; return *this; } - bool operator!=(const iterator &X) const { return I != X.I; } - - const LabelDecl *getLabel() const { - return cast((*I)->getLabel())->getDecl(); - } - - const CFGBlock *getBlock() const { - return *I; - } - }; - - iterator begin() { return iterator(DispatchBlock.succ_begin()); } - iterator end() { return iterator(DispatchBlock.succ_end()); } - - ExplodedNode *generateNode(const iterator &I, - ProgramStateRef State, - bool isSink = false); + ExplodedNode *generateNode(const CFGBlock *Block, ProgramStateRef State, + bool IsSink = false); const Expr *getTarget() const { return E; } @@ -514,57 +432,24 @@ class IndirectGotoNodeBuilder { }; class SwitchNodeBuilder { - CoreEngine& Eng; + const CoreEngine &Eng; const CFGBlock *Src; - const Expr *Condition; ExplodedNode *Pred; public: - SwitchNodeBuilder(ExplodedNode *pred, const CFGBlock *src, - const Expr *condition, CoreEngine* eng) - : Eng(*eng), Src(src), Condition(condition), Pred(pred) {} - - class iterator { - friend class SwitchNodeBuilder; - - CFGBlock::const_succ_reverse_iterator I; - - iterator(CFGBlock::const_succ_reverse_iterator i) : I(i) {} + SwitchNodeBuilder(ExplodedNode *P, const CFGBlock *S, CoreEngine &E) + : Eng(E), Src(S), Pred(P) {} - public: - iterator &operator++() { ++I; return *this; } - bool operator!=(const iterator &X) const { return I != X.I; } - bool operator==(const iterator &X) const { return I == X.I; } + using iterator = CFGBlock::const_succ_reverse_iterator; - const CaseStmt *getCase() const { - return cast((*I)->getLabel()); - } + iterator begin() { return Src->succ_rbegin() + 1; } + iterator end() { return Src->succ_rend(); } - const CFGBlock *getBlock() const { - return *I; - } - }; - - iterator begin() { return iterator(Src->succ_rbegin()+1); } - iterator end() { return iterator(Src->succ_rend()); } - - const SwitchStmt *getSwitch() const { - return cast(Src->getTerminator()); - } - - ExplodedNode *generateCaseStmtNode(const iterator &I, + ExplodedNode *generateCaseStmtNode(const CFGBlock *Block, ProgramStateRef State); ExplodedNode *generateDefaultCaseNode(ProgramStateRef State, - bool isSink = false); - - const Expr *getCondition() const { return Condition; } - - ProgramStateRef getState() const { return Pred->State; } - - const LocationContext *getLocationContext() const { - return Pred->getLocationContext(); - } + bool IsSink = false); }; } // namespace ento diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h index d184986cda15d..6705716932bbc 100644 --- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h +++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h @@ -86,7 +86,6 @@ class ExplodedNode; class IndirectGotoNodeBuilder; class MemRegion; class NodeBuilderContext; -class NodeBuilderWithSinks; class ProgramState; class ProgramStateManager; class RegionAndSymbolInvalidationTraits; @@ -320,9 +319,8 @@ class ExprEngine { ExplodedNode *Pred, ExplodedNodeSet &Dst); /// Called by CoreEngine when processing the entrance of a CFGBlock. - void processCFGBlockEntrance(const BlockEdge &L, - NodeBuilderWithSinks &nodeBuilder, - ExplodedNode *Pred); + void processCFGBlockEntrance(const BlockEdge &L, const BlockEntrance &BE, + NodeBuilder &Builder, ExplodedNode *Pred); void runCheckersForBlockEntrance(const NodeBuilderContext &BldCtx, const BlockEntrance &Entrance, @@ -361,7 +359,8 @@ class ExprEngine { /// ProcessSwitch - Called by CoreEngine. Used to generate successor /// nodes by processing the 'effects' of a switch statement. - void processSwitch(SwitchNodeBuilder& builder); + void processSwitch(const SwitchStmt *Switch, CoreEngine &CoreEng, + const CFGBlock *B, ExplodedNode *Pred); /// Called by CoreEngine. Used to notify checkers that processing a /// function has begun. Called for both inlined and top-level functions. diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index f52470a4d7458..3f63420cae91e 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -13224,6 +13224,18 @@ MangleContext *ASTContext::createDeviceMangleContext(const TargetInfo &T) { llvm_unreachable("Unsupported ABI"); } +MangleContext *ASTContext::cudaNVInitDeviceMC() { + // If the host and device have different C++ ABIs, mark it as the device + // mangle context so that the mangling needs to retrieve the additional + // device lambda mangling number instead of the regular host one. + if (getAuxTargetInfo() && getTargetInfo().getCXXABI().isMicrosoft() && + getAuxTargetInfo()->getCXXABI().isItaniumFamily()) { + return createDeviceMangleContext(*getAuxTargetInfo()); + } + + return createMangleContext(getAuxTargetInfo()); +} + CXXABI::~CXXABI() = default; size_t ASTContext::getSideTableAllocatedMemory() const { diff --git a/clang/lib/AST/ByteCode/Compiler.cpp b/clang/lib/AST/ByteCode/Compiler.cpp index af076f90733df..a0138c402e143 100644 --- a/clang/lib/AST/ByteCode/Compiler.cpp +++ b/clang/lib/AST/ByteCode/Compiler.cpp @@ -1082,24 +1082,27 @@ bool Compiler::VisitPointerArithBinOp(const BinaryOperator *E) { // Do the operation and optionally transform to // result pointer type. - if (Op == BO_Add) { + switch (Op) { + case BO_Add: if (!this->emitAddOffset(OffsetType, E)) return false; - - if (classifyPrim(E) != PT_Ptr) - return this->emitDecayPtr(PT_Ptr, classifyPrim(E), E); - return true; - } - if (Op == BO_Sub) { + break; + case BO_Sub: if (!this->emitSubOffset(OffsetType, E)) return false; + break; + default: + return false; + } - if (classifyPrim(E) != PT_Ptr) - return this->emitDecayPtr(PT_Ptr, classifyPrim(E), E); - return true; + if (classifyPrim(E) != PT_Ptr) { + if (!this->emitDecayPtr(PT_Ptr, classifyPrim(E), E)) + return false; } - return false; + if (DiscardResult) + return this->emitPop(classifyPrim(E), E); + return true; } template @@ -1780,6 +1783,9 @@ bool Compiler::VisitImplicitValueInitExpr( template bool Compiler::VisitArraySubscriptExpr(const ArraySubscriptExpr *E) { + if (E->getType()->isVoidType()) + return false; + const Expr *LHS = E->getLHS(); const Expr *RHS = E->getRHS(); const Expr *Index = E->getIdx(); @@ -3598,6 +3604,9 @@ bool Compiler::VisitCXXNewExpr(const CXXNewExpr *E) { const Expr *PlacementDest = nullptr; bool IsNoThrow = false; + if (E->containsErrors()) + return false; + if (PlacementArgs != 0) { // FIXME: There is no restriction on this, but it's not clear that any // other form makes any sense. We get here for cases such as: @@ -4501,6 +4510,8 @@ bool Compiler::visitZeroArrayInitializer(QualType T, const Expr *E) { } if (ElemType->isRecordType()) { const Record *R = getRecord(ElemType); + if (!R) + return false; for (size_t I = 0; I != NumElems; ++I) { if (!this->emitConstUint32(I, E)) @@ -5058,14 +5069,29 @@ bool Compiler::visitAPValueInitializer(const APValue &Val, } if (Val.isUnion()) { const FieldDecl *UnionField = Val.getUnionField(); - const Record *R = this->getRecord(UnionField->getParent()); + if (!UnionField) + return true; + const Record *R = this->getRecord(T); assert(R); const APValue &F = Val.getUnionValue(); const Record::Field *RF = R->getField(UnionField); - PrimType T = classifyPrim(RF->Decl->getType()); - if (!this->visitAPValue(F, T, E)) + QualType FieldType = RF->Decl->getType(); + + if (OptPrimType PT = classify(FieldType)) { + if (!this->visitAPValue(F, *PT, E)) + return false; + if (RF->isBitField()) + return this->emitInitBitFieldActivate(*PT, RF, E); + return this->emitInitFieldActivate(*PT, RF->Offset, E); + } + + if (!this->emitGetPtrField(RF->Offset, E)) + return false; + if (!this->emitActivate(E)) + return false; + if (!this->visitAPValueInitializer(F, E, FieldType)) return false; - return this->emitInitField(T, RF->Offset, E); + return this->emitPopPtr(E); } if (Val.isArray()) { const auto *ArrType = T->getAsArrayTypeUnsafe(); @@ -5164,6 +5190,15 @@ bool Compiler::VisitBuiltinCallExpr(const CallExpr *E, case Builtin::BI__builtin_assume: // Argument is not evaluated. break; + case Builtin::BI__atomic_is_lock_free: + case Builtin::BI__atomic_always_lock_free: { + assert(E->getNumArgs() == 2); + if (!this->visit(E->getArg(0))) + return false; + if (!this->visitAsLValue(E->getArg(1))) + return false; + } break; + default: if (!Context::isUnevaluatedBuiltin(BuiltinID)) { // Put arguments on the stack. @@ -7106,8 +7141,9 @@ bool Compiler::visitDeclRef(const ValueDecl *D, const Expr *E) { return false; return this->emitInitGlobal(*T, *Index, E); } - return this->visitAPValueInitializer(TPOD->getValue(), E, - TPOD->getType()); + if (!this->visitAPValueInitializer(TPOD->getValue(), E, TPOD->getType())) + return false; + return this->emitFinishInit(E); } return false; } @@ -7580,8 +7616,6 @@ bool Compiler::emitDummyPtr(const DeclTy &D, const Expr *E) { template bool Compiler::emitFloat(const APFloat &F, const Expr *E) { - assert(!DiscardResult && "Should've been checked before"); - if (Floating::singleWord(F.getSemantics())) return this->emitConstFloat(Floating(F), E); diff --git a/clang/lib/AST/ByteCode/Context.cpp b/clang/lib/AST/ByteCode/Context.cpp index d6fdf581baaec..b4b8939f3fe00 100644 --- a/clang/lib/AST/ByteCode/Context.cpp +++ b/clang/lib/AST/ByteCode/Context.cpp @@ -285,10 +285,11 @@ bool Context::evaluateString(State &Parent, const Expr *E, return true; } -bool Context::evaluateStrlen(State &Parent, const Expr *E, uint64_t &Result) { +std::optional Context::evaluateStrlen(State &Parent, const Expr *E) { assert(Stk.empty()); Compiler C(*this, *P, Parent, Stk); + std::optional Result; auto PtrRes = C.interpretAsPointer(E, [&](const Pointer &Ptr) { const Descriptor *FieldDesc = Ptr.getFieldDesc(); if (!FieldDesc->isPrimitiveArray()) @@ -312,7 +313,7 @@ bool Context::evaluateStrlen(State &Parent, const Expr *E, uint64_t &Result) { auto Elem = Ptr.elem(I); if (Elem.isZero()) return true; - ++Result; + ++(*Result); }); } // We didn't find a 0 byte. @@ -322,9 +323,42 @@ bool Context::evaluateStrlen(State &Parent, const Expr *E, uint64_t &Result) { if (PtrRes.isInvalid()) { C.cleanup(); Stk.clear(); + return std::nullopt; + } + return Result; +} + +std::optional +Context::tryEvaluateObjectSize(State &Parent, const Expr *E, unsigned Kind) { + assert(Stk.empty()); + Compiler C(*this, *P, Parent, Stk); + + std::optional Result; + + auto PtrRes = C.interpretAsPointer(E, [&](const Pointer &Ptr) { + const Descriptor *DeclDesc = Ptr.getDeclDesc(); + if (!DeclDesc) + return false; + + QualType T = DeclDesc->getType().getNonReferenceType(); + if (T->isIncompleteType() || T->isFunctionType() || + !T->isConstantSizeType()) + return false; + + Pointer P = Ptr; + if (auto ObjectSize = evaluateBuiltinObjectSize(getASTContext(), Kind, P)) { + Result = *ObjectSize; + return true; + } return false; + }); + + if (PtrRes.isInvalid()) { + C.cleanup(); + Stk.clear(); + return std::nullopt; } - return true; + return Result; } const LangOptions &Context::getLangOpts() const { return Ctx.getLangOpts(); } diff --git a/clang/lib/AST/ByteCode/Context.h b/clang/lib/AST/ByteCode/Context.h index a21bb3ed8fbe7..53afafdb49c0d 100644 --- a/clang/lib/AST/ByteCode/Context.h +++ b/clang/lib/AST/ByteCode/Context.h @@ -73,7 +73,20 @@ class Context final { /// Evalute \param E and if it can be evaluated to a string literal, /// run strlen() on it. - bool evaluateStrlen(State &Parent, const Expr *E, uint64_t &Result); + std::optional evaluateStrlen(State &Parent, const Expr *E); + + /// If \param E evaluates to a pointer the number of accessible bytes + /// past the pointer is estimated in \param Result as if evaluated by + /// the builtin function __builtin_object_size. This is a best effort + /// approximation, when Kind & 2 == 0 the object size is less + /// than or equal to the estimated size, when Kind & 2 == 1 the + /// true value is greater than or equal to the estimated size. + /// When Kind & 1 == 1 only bytes belonging to the same subobject + /// as the one referred to by E are considered, when Kind & 1 == 0 + /// bytes belonging to the same storage (stack, heap allocation, + /// global variable) are considered. + std::optional tryEvaluateObjectSize(State &Parent, const Expr *E, + unsigned Kind); /// Returns the AST context. ASTContext &getASTContext() const { return Ctx; } diff --git a/clang/lib/AST/ByteCode/Descriptor.h b/clang/lib/AST/ByteCode/Descriptor.h index 8338585a1741b..b052971733567 100644 --- a/clang/lib/AST/ByteCode/Descriptor.h +++ b/clang/lib/AST/ByteCode/Descriptor.h @@ -227,6 +227,10 @@ struct Descriptor final { return dyn_cast_if_present(asDecl()); } + template const T *getAs() const { + return dyn_cast_if_present(asDecl()); + } + /// Returns the size of the object without metadata. unsigned getSize() const { assert(!isUnknownSizeArray() && "Array of unknown size"); diff --git a/clang/lib/AST/ByteCode/EvalEmitter.cpp b/clang/lib/AST/ByteCode/EvalEmitter.cpp index 7d44c32d73555..7c120b9ecc17c 100644 --- a/clang/lib/AST/ByteCode/EvalEmitter.cpp +++ b/clang/lib/AST/ByteCode/EvalEmitter.cpp @@ -193,12 +193,6 @@ template <> bool EvalEmitter::emitRet(SourceInfo Info) { return true; const Pointer &Ptr = S.Stk.pop(); - - if (Ptr.isFunctionPointer()) { - EvalResult.takeValue(Ptr.toAPValue(Ctx.getASTContext())); - return true; - } - // If we're returning a raw pointer, call our callback. if (this->PtrCB) return (*this->PtrCB)(Ptr); @@ -208,6 +202,12 @@ template <> bool EvalEmitter::emitRet(SourceInfo Info) { if (CheckFullyInitialized && !EvalResult.checkFullyInitialized(S, Ptr)) return false; + // Function pointers are alway returned as lvalues. + if (Ptr.isFunctionPointer()) { + EvalResult.takeValue(Ptr.toAPValue(Ctx.getASTContext())); + return true; + } + // Implicitly convert lvalue to rvalue, if requested. if (ConvertResultToRValue) { if (!Ptr.isZero() && !Ptr.isDereferencable()) diff --git a/clang/lib/AST/ByteCode/Interp.cpp b/clang/lib/AST/ByteCode/Interp.cpp index d095e6f862fc5..f6e2f149165ff 100644 --- a/clang/lib/AST/ByteCode/Interp.cpp +++ b/clang/lib/AST/ByteCode/Interp.cpp @@ -38,21 +38,21 @@ static bool RetValue(InterpState &S, CodePtr &Pt) { static bool Jmp(InterpState &S, CodePtr &PC, int32_t Offset) { PC += Offset; - return true; + return S.noteStep(PC); } static bool Jt(InterpState &S, CodePtr &PC, int32_t Offset) { if (S.Stk.pop()) { PC += Offset; } - return true; + return S.noteStep(PC); } static bool Jf(InterpState &S, CodePtr &PC, int32_t Offset) { if (!S.Stk.pop()) { PC += Offset; } - return true; + return S.noteStep(PC); } // https://github.com/llvm/llvm-project/issues/102513 @@ -1549,6 +1549,8 @@ bool CheckDestructor(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { return false; if (!CheckRange(S, OpPC, Ptr, AK_Destroy)) return false; + if (!CheckLifetime(S, OpPC, Ptr.getLifetime(), AK_Destroy)) + return false; // Can't call a dtor on a global variable. if (Ptr.block()->isStatic()) { diff --git a/clang/lib/AST/ByteCode/Interp.h b/clang/lib/AST/ByteCode/Interp.h index d856cd7c0a2d9..ca5b1fd6bf072 100644 --- a/clang/lib/AST/ByteCode/Interp.h +++ b/clang/lib/AST/ByteCode/Interp.h @@ -1164,14 +1164,14 @@ inline bool CmpHelperEQ(InterpState &S, CodePtr OpPC, CompareFn Fn) { // Otherwise we need to do a bunch of extra checks before returning Unordered. if (LHS.isOnePastEnd() && !RHS.isOnePastEnd() && !RHS.isZero() && - RHS.getOffset() == 0) { + RHS.isBlockPointer() && RHS.getOffset() == 0) { const SourceInfo &Loc = S.Current->getSource(OpPC); S.FFDiag(Loc, diag::note_constexpr_pointer_comparison_past_end) << LHS.toDiagnosticString(S.getASTContext()); return false; } if (RHS.isOnePastEnd() && !LHS.isOnePastEnd() && !LHS.isZero() && - LHS.getOffset() == 0) { + LHS.isBlockPointer() && LHS.getOffset() == 0) { const SourceInfo &Loc = S.Current->getSource(OpPC); S.FFDiag(Loc, diag::note_constexpr_pointer_comparison_past_end) << RHS.toDiagnosticString(S.getASTContext()); @@ -1973,8 +1973,7 @@ bool Load(InterpState &S, CodePtr OpPC) { return false; if (!Ptr.isBlockPointer()) return false; - if (const Descriptor *D = Ptr.getFieldDesc(); - !(D->isPrimitive() || D->isPrimitiveArray()) || D->getPrimType() != Name) + if (!Ptr.canDeref(Name)) return false; S.Stk.push(Ptr.deref()); return true; @@ -1987,8 +1986,7 @@ bool LoadPop(InterpState &S, CodePtr OpPC) { return false; if (!Ptr.isBlockPointer()) return false; - if (const Descriptor *D = Ptr.getFieldDesc(); - !(D->isPrimitive() || D->isPrimitiveArray()) || D->getPrimType() != Name) + if (!Ptr.canDeref(Name)) return false; S.Stk.push(Ptr.deref()); return true; diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp b/clang/lib/AST/ByteCode/InterpBuiltin.cpp index 42ed44ff3c3ea..e47fc43ee8638 100644 --- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp +++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp @@ -1048,7 +1048,7 @@ static bool interp__builtin_bswap(InterpState &S, CodePtr OpPC, const InterpFrame *Frame, const CallExpr *Call) { const APSInt &Val = popToAPSInt(S, Call->getArg(0)); - if (Val.getBitWidth() == 8) + if (Val.getBitWidth() == 8 || Val.getBitWidth() == 1) pushInteger(S, Val, Call->getType()); else pushInteger(S, Val.byteSwap(), Call->getType()); @@ -1125,7 +1125,7 @@ static bool interp__builtin_atomic_lock_free(InterpState &S, CodePtr OpPC, if (BuiltinOp == Builtin::BI__atomic_always_lock_free) return returnBool(false); - return false; + return Invalid(S, OpPC); } /// bool __c11_atomic_is_lock_free(size_t) @@ -1402,7 +1402,7 @@ static bool interp__builtin_infer_alloc_token(InterpState &S, CodePtr OpPC, // We do not read any of the arguments; discard them. for (int I = Call->getNumArgs() - 1; I >= 0; --I) - discard(S.Stk, *S.getContext().classify(Call->getArg(I))); + discard(S.Stk, S.getContext().classify(Call->getArg(I)).value_or(PT_Ptr)); // Note: Type inference from a surrounding cast is not supported in // constexpr evaluation. @@ -2278,7 +2278,8 @@ static bool pointsToLastObject(const Pointer &Ptr) { } /// Does Ptr point to the last object AND to a flexible array member? -static bool isUserWritingOffTheEnd(const ASTContext &Ctx, const Pointer &Ptr) { +static bool isUserWritingOffTheEnd(const ASTContext &Ctx, const Pointer &Ptr, + bool InvalidBase) { auto isFlexibleArrayMember = [&](const Descriptor *FieldDesc) { using FAMKind = LangOptions::StrictFlexArraysLevelKind; FAMKind StrictFlexArraysLevel = @@ -2300,58 +2301,56 @@ static bool isUserWritingOffTheEnd(const ASTContext &Ctx, const Pointer &Ptr) { if (!FieldDesc->isArray()) return false; - return Ptr.isDummy() && pointsToLastObject(Ptr) && + return InvalidBase && pointsToLastObject(Ptr) && isFlexibleArrayMember(FieldDesc); } -static bool interp__builtin_object_size(InterpState &S, CodePtr OpPC, - const InterpFrame *Frame, - const CallExpr *Call) { - const ASTContext &ASTCtx = S.getASTContext(); - // From the GCC docs: - // Kind is an integer constant from 0 to 3. If the least significant bit is - // clear, objects are whole variables. If it is set, a closest surrounding - // subobject is considered the object a pointer points to. The second bit - // determines if maximum or minimum of remaining bytes is computed. - unsigned Kind = popToUInt64(S, Call->getArg(1)); - assert(Kind <= 3 && "unexpected kind"); - bool UseFieldDesc = (Kind & 1u); - bool ReportMinimum = (Kind & 2u); - Pointer Ptr = S.Stk.pop(); - - if (Call->getArg(0)->HasSideEffects(ASTCtx)) { - // "If there are any side effects in them, it returns (size_t) -1 - // for type 0 or 1 and (size_t) 0 for type 2 or 3." - pushInteger(S, Kind <= 1 ? -1 : 0, Call->getType()); - return true; - } - +UnsignedOrNone evaluateBuiltinObjectSize(const ASTContext &ASTCtx, + unsigned Kind, Pointer &Ptr) { if (Ptr.isZero() || !Ptr.isBlockPointer()) - return false; + return std::nullopt; - // We can't load through pointers. if (Ptr.isDummy() && Ptr.getType()->isPointerType()) - return false; + return std::nullopt; + + bool InvalidBase = false; + + if (Ptr.isDummy()) { + if (const VarDecl *VD = Ptr.getDeclDesc()->asVarDecl(); + VD && VD->getType()->isPointerType()) + InvalidBase = true; + } + + // According to the GCC documentation, we want the size of the subobject + // denoted by the pointer. But that's not quite right -- what we actually + // want is the size of the immediately-enclosing array, if there is one. + if (Ptr.isArrayElement()) + Ptr = Ptr.expand(); bool DetermineForCompleteObject = Ptr.getFieldDesc() == Ptr.getDeclDesc(); const Descriptor *DeclDesc = Ptr.getDeclDesc(); assert(DeclDesc); + bool UseFieldDesc = (Kind & 1u); + bool ReportMinimum = (Kind & 2u); if (!UseFieldDesc || DetermineForCompleteObject) { // Lower bound, so we can't fall back to this. - if (ReportMinimum && !DetermineForCompleteObject) - return false; + if (ReportMinimum && UseFieldDesc && !DetermineForCompleteObject) + return std::nullopt; // Can't read beyond the pointer decl desc. if (!UseFieldDesc && !ReportMinimum && DeclDesc->getType()->isPointerType()) - return false; + return std::nullopt; + + if (InvalidBase) + return std::nullopt; } else { - if (isUserWritingOffTheEnd(ASTCtx, Ptr.expand())) { + if (isUserWritingOffTheEnd(ASTCtx, Ptr, InvalidBase)) { // If we cannot determine the size of the initial allocation, then we // can't given an accurate upper-bound. However, we are still able to give // conservative lower-bounds for Type=3. if (Kind == 1) - return false; + return std::nullopt; } } @@ -2365,7 +2364,7 @@ static bool interp__builtin_object_size(InterpState &S, CodePtr OpPC, std::optional FullSize = computeFullDescSize(ASTCtx, Desc); if (!FullSize) - return false; + return std::nullopt; unsigned ByteOffset; if (UseFieldDesc) { @@ -2386,10 +2385,34 @@ static bool interp__builtin_object_size(InterpState &S, CodePtr OpPC, ByteOffset = computePointerOffset(ASTCtx, Ptr); assert(ByteOffset <= *FullSize); - unsigned Result = *FullSize - ByteOffset; + return *FullSize - ByteOffset; +} - pushInteger(S, Result, Call->getType()); - return true; +static bool interp__builtin_object_size(InterpState &S, CodePtr OpPC, + const InterpFrame *Frame, + const CallExpr *Call) { + const ASTContext &ASTCtx = S.getASTContext(); + // From the GCC docs: + // Kind is an integer constant from 0 to 3. If the least significant bit is + // clear, objects are whole variables. If it is set, a closest surrounding + // subobject is considered the object a pointer points to. The second bit + // determines if maximum or minimum of remaining bytes is computed. + unsigned Kind = popToUInt64(S, Call->getArg(1)); + assert(Kind <= 3 && "unexpected kind"); + Pointer Ptr = S.Stk.pop(); + + if (Call->getArg(0)->HasSideEffects(ASTCtx)) { + // "If there are any side effects in them, it returns (size_t) -1 + // for type 0 or 1 and (size_t) 0 for type 2 or 3." + pushInteger(S, Kind <= 1 ? -1 : 0, Call->getType()); + return true; + } + + if (auto Result = evaluateBuiltinObjectSize(ASTCtx, Kind, Ptr)) { + pushInteger(S, *Result, Call->getType()); + return true; + } + return false; } static bool interp__builtin_is_within_lifetime(InterpState &S, CodePtr OpPC, diff --git a/clang/lib/AST/ByteCode/InterpHelpers.h b/clang/lib/AST/ByteCode/InterpHelpers.h index 6bf89d318378c..905bf1b43bfab 100644 --- a/clang/lib/AST/ByteCode/InterpHelpers.h +++ b/clang/lib/AST/ByteCode/InterpHelpers.h @@ -66,6 +66,9 @@ bool CheckNewDeleteForms(InterpState &S, CodePtr OpPC, /// Copy the contents of Src into Dest. bool DoMemcpy(InterpState &S, CodePtr OpPC, const Pointer &Src, Pointer &Dest); +UnsignedOrNone evaluateBuiltinObjectSize(const ASTContext &ASTCtx, + unsigned Kind, Pointer &Ptr); + template static bool handleOverflow(InterpState &S, CodePtr OpPC, const T &SrcValue) { const Expr *E = S.Current->getExpr(OpPC); diff --git a/clang/lib/AST/ByteCode/InterpState.cpp b/clang/lib/AST/ByteCode/InterpState.cpp index 837d5fef91b8e..df507bd5507c3 100644 --- a/clang/lib/AST/ByteCode/InterpState.cpp +++ b/clang/lib/AST/ByteCode/InterpState.cpp @@ -20,7 +20,9 @@ using namespace clang::interp; InterpState::InterpState(const State &Parent, Program &P, InterpStack &Stk, Context &Ctx, SourceMapper *M) : State(Ctx.getASTContext(), Parent.getEvalStatus()), M(M), P(P), Stk(Stk), - Ctx(Ctx), BottomFrame(*this), Current(&BottomFrame) { + Ctx(Ctx), BottomFrame(*this), Current(&BottomFrame), + StepsLeft(Ctx.getLangOpts().ConstexprStepLimit), + InfiniteSteps(StepsLeft == 0) { InConstantContext = Parent.InConstantContext; CheckingPotentialConstantExpression = Parent.CheckingPotentialConstantExpression; @@ -33,7 +35,8 @@ InterpState::InterpState(const State &Parent, Program &P, InterpStack &Stk, : State(Ctx.getASTContext(), Parent.getEvalStatus()), M(nullptr), P(P), Stk(Stk), Ctx(Ctx), BottomFrame(*this, Func, nullptr, CodePtr(), Func->getArgSize()), - Current(&BottomFrame) { + Current(&BottomFrame), StepsLeft(Ctx.getLangOpts().ConstexprStepLimit), + InfiniteSteps(StepsLeft == 0) { InConstantContext = Parent.InConstantContext; CheckingPotentialConstantExpression = Parent.CheckingPotentialConstantExpression; @@ -154,3 +157,15 @@ StdAllocatorCaller InterpState::getStdAllocatorCaller(StringRef Name) const { return {}; } + +bool InterpState::noteStep(CodePtr OpPC) { + if (InfiniteSteps) + return true; + + --StepsLeft; + if (StepsLeft != 0) + return true; + + FFDiag(Current->getSource(OpPC), diag::note_constexpr_step_limit_exceeded); + return false; +} diff --git a/clang/lib/AST/ByteCode/InterpState.h b/clang/lib/AST/ByteCode/InterpState.h index 98dc5cfd3b3c4..83ef56e7f8452 100644 --- a/clang/lib/AST/ByteCode/InterpState.h +++ b/clang/lib/AST/ByteCode/InterpState.h @@ -119,6 +119,10 @@ class InterpState final : public State, public SourceMapper { return Floating(Mem, llvm::APFloatBase::SemanticsToEnum(Sem)); } + /// Note that a step has been executed. If there are no more steps remaining, + /// diagnoses and returns \c false. + bool noteStep(CodePtr OpPC); + private: friend class EvaluationResult; friend class InterpStateCCOverride; @@ -146,6 +150,12 @@ class InterpState final : public State, public SourceMapper { SourceLocation EvalLocation; /// Declaration we're initializing/evaluting, if any. const VarDecl *EvaluatingDecl = nullptr; + /// Steps left during evaluation. + unsigned StepsLeft = 1; + /// Whether infinite evaluation steps have been requested. If this is false, + /// we use the StepsLeft value above. + const bool InfiniteSteps = false; + /// Things needed to do speculative execution. SmallVectorImpl *PrevDiags = nullptr; unsigned SpeculationDepth = 0; diff --git a/clang/lib/AST/ByteCode/Pointer.cpp b/clang/lib/AST/ByteCode/Pointer.cpp index a1ab492e5cb37..fb9202c6d66c8 100644 --- a/clang/lib/AST/ByteCode/Pointer.cpp +++ b/clang/lib/AST/ByteCode/Pointer.cpp @@ -947,6 +947,8 @@ std::optional Pointer::toRValue(const Context &Ctx, // Just load primitive types. if (OptPrimType T = Ctx.classify(ResultType)) { + if (!canDeref(*T)) + return std::nullopt; TYPE_SWITCH(*T, return this->deref().toAPValue(ASTCtx)); } diff --git a/clang/lib/AST/ByteCode/Pointer.h b/clang/lib/AST/ByteCode/Pointer.h index 7ff1559cd0000..2515b2fe56ab9 100644 --- a/clang/lib/AST/ByteCode/Pointer.h +++ b/clang/lib/AST/ByteCode/Pointer.h @@ -666,6 +666,15 @@ class Pointer { return false; } + /// Checks whether the pointer can be dereferenced to the given PrimType. + bool canDeref(PrimType T) const { + if (const Descriptor *FieldDesc = getFieldDesc()) { + return (FieldDesc->isPrimitive() || FieldDesc->isPrimitiveArray()) && + FieldDesc->getPrimType() == T; + } + return false; + } + /// Dereferences the pointer, if it's live. template T &deref() const { assert(isLive() && "Invalid pointer"); diff --git a/clang/lib/AST/ComputeDependence.cpp b/clang/lib/AST/ComputeDependence.cpp index 8429f17d26be5..34167eee8d8f2 100644 --- a/clang/lib/AST/ComputeDependence.cpp +++ b/clang/lib/AST/ComputeDependence.cpp @@ -256,6 +256,10 @@ ExprDependence clang::computeDependence(ExtVectorElementExpr *E) { return E->getBase()->getDependence(); } +ExprDependence clang::computeDependence(MatrixElementExpr *E) { + return E->getBase()->getDependence(); +} + ExprDependence clang::computeDependence(BlockExpr *E, bool ContainsUnexpandedParameterPack) { auto D = toExprDependenceForImpliedType(E->getType()->getDependence()); diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp index 4bb979e51b75d..9632d88fae4e4 100644 --- a/clang/lib/AST/Expr.cpp +++ b/clang/lib/AST/Expr.cpp @@ -25,6 +25,7 @@ #include "clang/AST/IgnoreExpr.h" #include "clang/AST/Mangle.h" #include "clang/AST/RecordLayout.h" +#include "clang/AST/TypeBase.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/CharInfo.h" #include "clang/Basic/SourceManager.h" @@ -3734,6 +3735,7 @@ bool Expr::HasSideEffects(const ASTContext &Ctx, case PackIndexingExprClass: case HLSLOutArgExprClass: case OpenACCAsteriskSizeExprClass: + case CXXReflectExprClass: // These never have a side-effect. return false; @@ -3802,6 +3804,7 @@ bool Expr::HasSideEffects(const ASTContext &Ctx, case BinaryConditionalOperatorClass: case CompoundLiteralExprClass: case ExtVectorElementExprClass: + case MatrixElementExprClass: case DesignatedInitExprClass: case DesignatedInitUpdateExprClass: case ArrayInitLoopExprClass: @@ -4422,7 +4425,14 @@ unsigned ExtVectorElementExpr::getNumElements() const { return 1; } -/// containsDuplicateElements - Return true if any element access is repeated. +unsigned MatrixElementExpr::getNumElements() const { + if (const auto *MT = getType()->getAs()) + return MT->getNumElementsFlattened(); + return 1; +} + +/// containsDuplicateElements - Return true if any Vector element access is +/// repeated. bool ExtVectorElementExpr::containsDuplicateElements() const { // FIXME: Refactor this code to an accessor on the AST node which returns the // "type" of component access, and share with code below and in Sema. @@ -4443,6 +4453,78 @@ bool ExtVectorElementExpr::containsDuplicateElements() const { return false; } +namespace { +struct MatrixAccessorFormat { + bool IsZeroIndexed = false; + unsigned ChunkLen = 0; +}; + +static MatrixAccessorFormat GetHLSLMatrixAccessorFormat(StringRef Comp) { + assert(!Comp.empty() && Comp[0] == '_' && "invalid matrix accessor"); + + MatrixAccessorFormat F; + if (Comp.size() >= 2 && Comp[0] == '_' && Comp[1] == 'm') { + F.IsZeroIndexed = true; + F.ChunkLen = 4; // _mRC + } else { + F.IsZeroIndexed = false; + F.ChunkLen = 3; // _RC + } + + assert(F.ChunkLen != 0 && "unrecognized matrix swizzle format"); + assert(Comp.size() % F.ChunkLen == 0 && + "matrix swizzle accessor has invalid length"); + return F; +} + +template +static bool ForEachMatrixAccessorIndex(StringRef Comp, unsigned Rows, + unsigned Cols, Fn &&F) { + auto Format = GetHLSLMatrixAccessorFormat(Comp); + + for (unsigned I = 0, E = Comp.size(); I < E; I += Format.ChunkLen) { + unsigned Row = 0, Col = 0; + unsigned ZeroIndexOffset = static_cast(Format.IsZeroIndexed); + unsigned OneIndexOffset = static_cast(!Format.IsZeroIndexed); + Row = static_cast(Comp[I + ZeroIndexOffset + 1] - '0') - + OneIndexOffset; + Col = static_cast(Comp[I + ZeroIndexOffset + 2] - '0') - + OneIndexOffset; + + assert(Row < Rows && Col < Cols && "matrix swizzle index out of bounds"); + const unsigned Index = Row * Cols + Col; + // Callback returns true to continue, false to stop early. + if (!F(Index)) + return false; + } + return true; +} + +} // namespace + +/// containsDuplicateElements - Return true if any Matrix element access is +/// repeated. +bool MatrixElementExpr::containsDuplicateElements() const { + StringRef Comp = Accessor->getName(); + const auto *MT = getBase()->getType()->castAs(); + const unsigned Rows = MT->getNumRows(); + const unsigned Cols = MT->getNumColumns(); + const unsigned Max = Rows * Cols; + + llvm::BitVector Seen(Max, /*t=*/false); + bool HasDup = false; + ForEachMatrixAccessorIndex(Comp, Rows, Cols, [&](unsigned Index) -> bool { + if (Seen[Index]) { + HasDup = true; + return false; // exit early + } + Seen.set(Index); + return true; + }); + + return HasDup; +} + /// getEncodedElementAccess - We encode the fields as a llvm ConstantArray. void ExtVectorElementExpr::getEncodedElementAccess( SmallVectorImpl &Elts) const { @@ -4476,6 +4558,18 @@ void ExtVectorElementExpr::getEncodedElementAccess( } } +void MatrixElementExpr::getEncodedElementAccess( + SmallVectorImpl &Elts) const { + StringRef Comp = Accessor->getName(); + const auto *MT = getBase()->getType()->castAs(); + const unsigned Rows = MT->getNumRows(); + const unsigned Cols = MT->getNumColumns(); + ForEachMatrixAccessorIndex(Comp, Rows, Cols, [&](unsigned Index) -> bool { + Elts.push_back(Index); + return true; + }); +} + ShuffleVectorExpr::ShuffleVectorExpr(const ASTContext &C, ArrayRef args, QualType Type, SourceLocation BLoc, SourceLocation RP) diff --git a/clang/lib/AST/ExprCXX.cpp b/clang/lib/AST/ExprCXX.cpp index c7f0ff040194d..bcc481fc8399f 100644 --- a/clang/lib/AST/ExprCXX.cpp +++ b/clang/lib/AST/ExprCXX.cpp @@ -1939,6 +1939,24 @@ TypeTraitExpr *TypeTraitExpr::CreateDeserialized(const ASTContext &C, return new (Mem) TypeTraitExpr(EmptyShell(), IsStoredAsBool); } +CXXReflectExpr::CXXReflectExpr(EmptyShell Empty) + : Expr(CXXReflectExprClass, Empty) {} + +CXXReflectExpr::CXXReflectExpr(SourceLocation CaretCaretLoc, + const TypeSourceInfo *TSI) + : Expr(CXXReflectExprClass, TSI->getType(), VK_PRValue, OK_Ordinary), + CaretCaretLoc(CaretCaretLoc), Operand(TSI) {} + +CXXReflectExpr *CXXReflectExpr::Create(ASTContext &C, + SourceLocation CaretCaretLoc, + TypeSourceInfo *TSI) { + return new (C) CXXReflectExpr(CaretCaretLoc, TSI); +} + +CXXReflectExpr *CXXReflectExpr::CreateEmpty(ASTContext &C) { + return new (C) CXXReflectExpr(EmptyShell()); +} + CUDAKernelCallExpr::CUDAKernelCallExpr(Expr *Fn, CallExpr *Config, ArrayRef Args, QualType Ty, ExprValueKind VK, SourceLocation RP, diff --git a/clang/lib/AST/ExprClassification.cpp b/clang/lib/AST/ExprClassification.cpp index 9995d1b411c5b..a83c17074ea69 100644 --- a/clang/lib/AST/ExprClassification.cpp +++ b/clang/lib/AST/ExprClassification.cpp @@ -63,6 +63,7 @@ Cl Expr::ClassifyImpl(ASTContext &Ctx, SourceLocation *Loc) const { case Cl::CL_Void: case Cl::CL_AddressableVoid: case Cl::CL_DuplicateVectorComponents: + case Cl::CL_DuplicateMatrixComponents: case Cl::CL_MemberFunction: case Cl::CL_SubObjCPropertySetting: case Cl::CL_ClassTemporary: @@ -216,6 +217,7 @@ static Cl::Kinds ClassifyInternal(ASTContext &Ctx, const Expr *E) { case Expr::SourceLocExprClass: case Expr::ConceptSpecializationExprClass: case Expr::RequiresExprClass: + case Expr::CXXReflectExprClass: return Cl::CL_PRValue; case Expr::EmbedExprClass: @@ -372,6 +374,16 @@ static Cl::Kinds ClassifyInternal(ASTContext &Ctx, const Expr *E) { return Cl::CL_LValue; return ClassifyInternal(Ctx, cast(E)->getBase()); + // Matrix element access is an lvalue unless there are duplicates + // in the shuffle expression. + case Expr::MatrixElementExprClass: + if (cast(E)->containsDuplicateElements()) + return Cl::CL_DuplicateMatrixComponents; + // NOTE: MatrixElementExpr is currently only used by HLSL which does not + // have pointers so there is no isArrow() necessary or way to test + // Cl::CL_LValue + return ClassifyInternal(Ctx, cast(E)->getBase()); + // Simply look at the actual default argument. case Expr::CXXDefaultArgExprClass: return ClassifyInternal(Ctx, cast(E)->getExpr()); @@ -738,6 +750,8 @@ Expr::LValueClassification Expr::ClassifyLValue(ASTContext &Ctx) const { case Cl::CL_Void: return LV_InvalidExpression; case Cl::CL_AddressableVoid: return LV_IncompleteVoidType; case Cl::CL_DuplicateVectorComponents: return LV_DuplicateVectorComponents; + case Cl::CL_DuplicateMatrixComponents: + return LV_DuplicateMatrixComponents; case Cl::CL_MemberFunction: return LV_MemberFunction; case Cl::CL_SubObjCPropertySetting: return LV_SubObjCPropertySetting; case Cl::CL_ClassTemporary: return LV_ClassTemporary; @@ -759,6 +773,8 @@ Expr::isModifiableLvalue(ASTContext &Ctx, SourceLocation *Loc) const { case Cl::CL_Void: return MLV_InvalidExpression; case Cl::CL_AddressableVoid: return MLV_IncompleteVoidType; case Cl::CL_DuplicateVectorComponents: return MLV_DuplicateVectorComponents; + case Cl::CL_DuplicateMatrixComponents: + return MLV_DuplicateMatrixComponents; case Cl::CL_MemberFunction: return MLV_MemberFunction; case Cl::CL_SubObjCPropertySetting: return MLV_SubObjCPropertySetting; case Cl::CL_ClassTemporary: return MLV_ClassTemporary; diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index 48054c2fda2ad..44629b8bae194 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -1775,9 +1775,9 @@ static bool EvaluateComplex(const Expr *E, ComplexValue &Res, EvalInfo &Info); static bool EvaluateAtomic(const Expr *E, const LValue *This, APValue &Result, EvalInfo &Info); static bool EvaluateAsRValue(EvalInfo &Info, const Expr *E, APValue &Result); -static bool EvaluateBuiltinStrLen(const Expr *E, uint64_t &Result, - EvalInfo &Info, - std::string *StringResult = nullptr); +static std::optional +EvaluateBuiltinStrLen(const Expr *E, EvalInfo &Info, + std::string *StringResult = nullptr); /// Evaluate an integer or fixed point expression into an APResult. static bool EvaluateFixedPointOrInteger(const Expr *E, APFixedPoint &Result, @@ -15781,8 +15781,8 @@ static bool determineEndOffset(EvalInfo &Info, SourceLocation ExprLoc, /// /// If @p WasError is non-null, this will report whether the failure to evaluate /// is to be treated as an Error in IntExprEvaluator. -static bool tryEvaluateBuiltinObjectSize(const Expr *E, unsigned Type, - EvalInfo &Info, uint64_t &Size) { +static std::optional +tryEvaluateBuiltinObjectSize(const Expr *E, unsigned Type, EvalInfo &Info) { // Determine the denoted object. LValue LVal; { @@ -15797,31 +15797,27 @@ static bool tryEvaluateBuiltinObjectSize(const Expr *E, unsigned Type, // Expr::tryEvaluateObjectSize. APValue RVal; if (!EvaluateAsRValue(Info, E, RVal)) - return false; + return std::nullopt; LVal.setFrom(Info.Ctx, RVal); } else if (!EvaluatePointer(ignorePointerCastsAndParens(E), LVal, Info, /*InvalidBaseOK=*/true)) - return false; + return std::nullopt; } // If we point to before the start of the object, there are no accessible // bytes. - if (LVal.getLValueOffset().isNegative()) { - Size = 0; - return true; - } + if (LVal.getLValueOffset().isNegative()) + return 0; CharUnits EndOffset; if (!determineEndOffset(Info, E->getExprLoc(), Type, LVal, EndOffset)) - return false; + return std::nullopt; // If we've fallen outside of the end offset, just pretend there's nothing to // write to/read from. if (EndOffset <= LVal.getLValueOffset()) - Size = 0; - else - Size = (EndOffset - LVal.getLValueOffset()).getQuantity(); - return true; + return 0; + return (EndOffset - LVal.getLValueOffset()).getQuantity(); } bool IntExprEvaluator::VisitCallExpr(const CallExpr *E) { @@ -15952,9 +15948,9 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E, E->getArg(1)->EvaluateKnownConstInt(Info.Ctx).getZExtValue(); assert(Type <= 3 && "unexpected type"); - uint64_t Size; - if (tryEvaluateBuiltinObjectSize(E->getArg(0), Type, Info, Size)) - return Success(Size, E); + if (std::optional Size = + tryEvaluateBuiltinObjectSize(E->getArg(0), Type, Info)) + return Success(*Size, E); if (E->getArg(0)->HasSideEffects(Info.Ctx)) return Success((Type & 2) ? 0 : -1, E); @@ -16059,7 +16055,7 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E, APSInt Val; if (!EvaluateInteger(E->getArg(0), Val, Info)) return false; - if (Val.getBitWidth() == 8) + if (Val.getBitWidth() == 8 || Val.getBitWidth() == 1) return Success(Val, E); return Success(Val.byteSwap(), E); @@ -16552,9 +16548,9 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E, case Builtin::BI__builtin_wcslen: { // As an extension, we support __builtin_strlen() as a constant expression, // and support folding strlen() to a constant. - uint64_t StrLen; - if (EvaluateBuiltinStrLen(E->getArg(0), StrLen, Info)) - return Success(StrLen, E); + if (std::optional StrLen = + EvaluateBuiltinStrLen(E->getArg(0), Info)) + return Success(*StrLen, E); return false; } @@ -21000,6 +20996,7 @@ static ICEDiag CheckICE(const Expr* E, const ASTContext &Ctx) { case Expr::CompoundAssignOperatorClass: case Expr::CompoundLiteralExprClass: case Expr::ExtVectorElementExprClass: + case Expr::MatrixElementExprClass: case Expr::DesignatedInitExprClass: case Expr::ArrayInitLoopExprClass: case Expr::ArrayInitIndexExprClass: @@ -21117,6 +21114,7 @@ static ICEDiag CheckICE(const Expr* E, const ASTContext &Ctx) { case Expr::ArrayTypeTraitExprClass: case Expr::ExpressionTraitExprClass: case Expr::CXXNoexceptExprClass: + case Expr::CXXReflectExprClass: return NoDiag(); case Expr::CallExprClass: case Expr::CXXOperatorCallExprClass: { @@ -21659,25 +21657,28 @@ bool Expr::isPotentialConstantExprUnevaluated(Expr *E, return Diags.empty(); } -bool Expr::tryEvaluateObjectSize(uint64_t &Result, ASTContext &Ctx, - unsigned Type) const { +std::optional Expr::tryEvaluateObjectSize(const ASTContext &Ctx, + unsigned Type) const { if (!getType()->isPointerType()) - return false; + return std::nullopt; Expr::EvalStatus Status; EvalInfo Info(Ctx, Status, EvaluationMode::ConstantFold); - return tryEvaluateBuiltinObjectSize(this, Type, Info, Result); + if (Info.EnableNewConstInterp) + return Info.Ctx.getInterpContext().tryEvaluateObjectSize(Info, this, Type); + return tryEvaluateBuiltinObjectSize(this, Type, Info); } -static bool EvaluateBuiltinStrLen(const Expr *E, uint64_t &Result, - EvalInfo &Info, std::string *StringResult) { +static std::optional +EvaluateBuiltinStrLen(const Expr *E, EvalInfo &Info, + std::string *StringResult) { if (!E->getType()->hasPointerRepresentation() || !E->isPRValue()) - return false; + return std::nullopt; LValue String; if (!EvaluatePointer(E, String, Info)) - return false; + return std::nullopt; QualType CharTy = E->getType()->getPointeeType(); @@ -21696,10 +21697,9 @@ static bool EvaluateBuiltinStrLen(const Expr *E, uint64_t &Result, if (Pos != StringRef::npos) Str = Str.substr(0, Pos); - Result = Str.size(); if (StringResult) *StringResult = Str; - return true; + return Str.size(); } // Fall through to slow path. @@ -21710,21 +21710,19 @@ static bool EvaluateBuiltinStrLen(const Expr *E, uint64_t &Result, APValue Char; if (!handleLValueToRValueConversion(Info, E, CharTy, String, Char) || !Char.isInt()) - return false; - if (!Char.getInt()) { - Result = Strlen; - return true; - } else if (StringResult) + return std::nullopt; + if (!Char.getInt()) + return Strlen; + else if (StringResult) StringResult->push_back(Char.getInt().getExtValue()); if (!HandleLValueArrayAdjustment(Info, E, String, CharTy, 1)) - return false; + return std::nullopt; } } std::optional Expr::tryEvaluateString(ASTContext &Ctx) const { Expr::EvalStatus Status; EvalInfo Info(Ctx, Status, EvaluationMode::ConstantFold); - uint64_t Result; std::string StringResult; if (Info.EnableNewConstInterp) { @@ -21733,7 +21731,7 @@ std::optional Expr::tryEvaluateString(ASTContext &Ctx) const { return StringResult; } - if (EvaluateBuiltinStrLen(this, Result, Info, &StringResult)) + if (EvaluateBuiltinStrLen(this, Info, &StringResult)) return StringResult; return std::nullopt; } @@ -21810,14 +21808,13 @@ bool Expr::EvaluateCharRangeAsString(APValue &Result, PtrExpression, Ctx, Status); } -bool Expr::tryEvaluateStrLen(uint64_t &Result, ASTContext &Ctx) const { +std::optional Expr::tryEvaluateStrLen(const ASTContext &Ctx) const { Expr::EvalStatus Status; EvalInfo Info(Ctx, Status, EvaluationMode::ConstantFold); if (Info.EnableNewConstInterp) - return Info.Ctx.getInterpContext().evaluateStrlen(Info, this, Result); - - return EvaluateBuiltinStrLen(this, Result, Info); + return Info.Ctx.getInterpContext().evaluateStrlen(Info, this); + return EvaluateBuiltinStrLen(this, Info); } namespace { diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp index fa28c0d444cc4..70acc8a78ed52 100644 --- a/clang/lib/AST/ItaniumMangle.cpp +++ b/clang/lib/AST/ItaniumMangle.cpp @@ -4951,11 +4951,18 @@ void CXXNameMangler::mangleExpression(const Expr *E, unsigned Arity, E = cast(E)->getSubExpr(); goto recurse; + case Expr::CXXReflectExprClass: { + // TODO(Reflection): implement this after introducing std::meta::info + assert(false && "unimplemented"); + break; + } + // FIXME: invent manglings for all these. case Expr::BlockExprClass: case Expr::ChooseExprClass: case Expr::CompoundLiteralExprClass: case Expr::ExtVectorElementExprClass: + case Expr::MatrixElementExprClass: case Expr::GenericSelectionExprClass: case Expr::ObjCEncodeExprClass: case Expr::ObjCIsaExprClass: diff --git a/clang/lib/AST/JSONNodeDumper.cpp b/clang/lib/AST/JSONNodeDumper.cpp index 715e1e0989422..3138f95e6a83b 100644 --- a/clang/lib/AST/JSONNodeDumper.cpp +++ b/clang/lib/AST/JSONNodeDumper.cpp @@ -596,6 +596,27 @@ void JSONNodeDumper::VisitTLSModelAttr(const TLSModelAttr *TA) { JOS.attribute("tls_model", TA->getModel()); } +void JSONNodeDumper::VisitAvailabilityAttr(const AvailabilityAttr *AA) { + if (const IdentifierInfo *Platform = AA->getPlatform()) + JOS.attribute("platform", Platform->getName()); + if (!AA->getIntroduced().empty()) + JOS.attribute("introduced", AA->getIntroduced().getAsString()); + if (!AA->getDeprecated().empty()) + JOS.attribute("deprecated", AA->getDeprecated().getAsString()); + if (!AA->getObsoleted().empty()) + JOS.attribute("obsoleted", AA->getObsoleted().getAsString()); + attributeOnlyIfTrue("unavailable", AA->getUnavailable()); + if (!AA->getMessage().empty()) + JOS.attribute("message", AA->getMessage()); + attributeOnlyIfTrue("strict", AA->getStrict()); + if (!AA->getReplacement().empty()) + JOS.attribute("replacement", AA->getReplacement()); + if (AA->getPriority() != 0) + JOS.attribute("priority", AA->getPriority()); + if (const IdentifierInfo *Env = AA->getEnvironment()) + JOS.attribute("environment", Env->getName()); +} + void JSONNodeDumper::VisitTypedefType(const TypedefType *TT) { JOS.attribute("decl", createBareDeclRef(TT->getDecl())); if (!TT->typeMatchesDecl()) diff --git a/clang/lib/AST/OpenMPClause.cpp b/clang/lib/AST/OpenMPClause.cpp index 62d78660570de..9e7a8a48372c7 100644 --- a/clang/lib/AST/OpenMPClause.cpp +++ b/clang/lib/AST/OpenMPClause.cpp @@ -2057,7 +2057,10 @@ void OMPClausePrinter::VisitOMPThreadsetClause(OMPThreadsetClause *Node) { void OMPClausePrinter::VisitOMPTransparentClause(OMPTransparentClause *Node) { OS << "transparent("; - Node->getImpexType()->printPretty(OS, nullptr, Policy, 0); + if (Node->getImpexType()) + Node->getImpexType()->printPretty(OS, nullptr, Policy, 0); + else + OS << "omp_impex"; OS << ")"; } diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp index 4d1ad387b8e8d..f4ce4a7573aab 100644 --- a/clang/lib/AST/StmtPrinter.cpp +++ b/clang/lib/AST/StmtPrinter.cpp @@ -1826,6 +1826,12 @@ void StmtPrinter::VisitExtVectorElementExpr(ExtVectorElementExpr *Node) { OS << Node->getAccessor().getName(); } +void StmtPrinter::VisitMatrixElementExpr(MatrixElementExpr *Node) { + PrintExpr(Node->getBase()); + OS << "."; + OS << Node->getAccessor().getName(); +} + void StmtPrinter::VisitCStyleCastExpr(CStyleCastExpr *Node) { OS << '('; Node->getTypeAsWritten().print(OS, Policy); @@ -2579,6 +2585,11 @@ void StmtPrinter::VisitCXXUnresolvedConstructExpr( OS << ')'; } +void StmtPrinter::VisitCXXReflectExpr(CXXReflectExpr *S) { + // TODO(Reflection): Implement this. + assert(false && "not implemented yet"); +} + void StmtPrinter::VisitCXXDependentScopeMemberExpr( CXXDependentScopeMemberExpr *Node) { if (!Node->isImplicitAccess()) { diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp index efabe9809c361..623905188b2dd 100644 --- a/clang/lib/AST/StmtProfile.cpp +++ b/clang/lib/AST/StmtProfile.cpp @@ -1680,6 +1680,11 @@ void StmtProfiler::VisitExtVectorElementExpr(const ExtVectorElementExpr *S) { VisitName(&S->getAccessor()); } +void StmtProfiler::VisitMatrixElementExpr(const MatrixElementExpr *S) { + VisitExpr(S); + VisitName(&S->getAccessor()); +} + void StmtProfiler::VisitBlockExpr(const BlockExpr *S) { VisitExpr(S); VisitDecl(S->getBlockDecl()); @@ -2188,6 +2193,11 @@ StmtProfiler::VisitLambdaExpr(const LambdaExpr *S) { ID.AddInteger(Hasher.CalculateHash()); } +void StmtProfiler::VisitCXXReflectExpr(const CXXReflectExpr *E) { + // TODO(Reflection): Implement this. + assert(false && "not implemented yet"); +} + void StmtProfiler::VisitCXXScalarValueInitExpr(const CXXScalarValueInitExpr *S) { VisitExpr(S); diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index 7bc0404db1bee..aebfb9fa53fa1 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -1675,6 +1675,10 @@ void TextNodeDumper::VisitExtVectorElementExpr( OS << " " << Node->getAccessor().getNameStart(); } +void TextNodeDumper::VisitMatrixElementExpr(const MatrixElementExpr *Node) { + OS << " " << Node->getAccessor().getNameStart(); +} + void TextNodeDumper::VisitBinaryOperator(const BinaryOperator *Node) { OS << " '" << BinaryOperator::getOpcodeStr(Node->getOpcode()) << "'"; if (Node->hasStoredFPFeatures()) diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp index 53082bcf78f6a..dcdbb62f9d62b 100644 --- a/clang/lib/AST/Type.cpp +++ b/clang/lib/AST/Type.cpp @@ -2947,7 +2947,8 @@ bool QualType::isWebAssemblyExternrefType() const { bool QualType::isWebAssemblyFuncrefType() const { return getTypePtr()->isFunctionPointerType() && - getAddressSpace() == LangAS::wasm_funcref; + (getTypePtr()->getPointeeType().getAddressSpace() == + LangAS::wasm_funcref); } QualType::PrimitiveDefaultInitializeKind diff --git a/clang/lib/Analysis/CFGBackEdges.cpp b/clang/lib/Analysis/CFGBackEdges.cpp new file mode 100644 index 0000000000000..9018d1a594ed2 --- /dev/null +++ b/clang/lib/Analysis/CFGBackEdges.cpp @@ -0,0 +1,105 @@ +//===- CFGBackEdges.cpp - Finds back edges in Clang CFGs ------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include +#include + +#include "clang/Analysis/CFG.h" +#include "clang/Analysis/CFGBackEdges.h" +#include "llvm/ADT/DenseMap.h" + +namespace clang { + +namespace { +struct VisitClockTimes { + // Timestamp for when the node was visited / discovered. + int Pre = -1; + // Timestamp for when we finished visiting a node's successors. + int Post = -1; +}; +} // namespace + +// Returns true if the CFG contains any goto statements (direct or indirect). +static bool hasGotoInCFG(const CFG &CFG) { + for (const CFGBlock *Block : CFG) { + const Stmt *Term = Block->getTerminatorStmt(); + if (Term == nullptr) + continue; + if (isa(Term) || isa(Term)) + return true; + } + return false; +} + +llvm::DenseMap +findCFGBackEdges(const CFG &CFG) { + // Do a simple textbook DFS with pre and post numberings to find back edges. + llvm::DenseMap BackEdges; + + std::vector VisitState; + VisitState.resize(CFG.getNumBlockIDs()); + std::stack> + DFSStack; + int Clock = 0; + const CFGBlock &Entry = CFG.getEntry(); + VisitState[Entry.getBlockID()].Pre = Clock++; + DFSStack.push({&Entry, Entry.succ_begin()}); + + while (!DFSStack.empty()) { + auto &[Block, SuccIt] = DFSStack.top(); + if (SuccIt == Block->succ_end()) { + VisitState[Block->getBlockID()].Post = Clock++; + DFSStack.pop(); + continue; + } + + const CFGBlock::AdjacentBlock &AdjacentSucc = *SuccIt++; + const CFGBlock *Succ = AdjacentSucc.getReachableBlock(); + // Skip unreachable blocks. + if (Succ == nullptr) + continue; + + VisitClockTimes &SuccVisitState = VisitState[Succ->getBlockID()]; + if (SuccVisitState.Pre != -1) { + if (SuccVisitState.Post == -1) + BackEdges.insert({Block, Succ}); + } else { + SuccVisitState.Pre = Clock++; + DFSStack.push({Succ, Succ->succ_begin()}); + } + } + return BackEdges; +} + +// Returns a set of CFG blocks that is the source of a backedge and is not +// tracked as part of a structured loop (with `CFGBlock::getLoopTarget`). +llvm::SmallDenseSet +findNonStructuredLoopBackedgeNodes(const CFG &CFG) { + llvm::SmallDenseSet NonStructLoopBackedgeNodes; + // We should only need this if the function has gotos. + if (!hasGotoInCFG(CFG)) + return NonStructLoopBackedgeNodes; + + llvm::DenseMap Backedges = + findCFGBackEdges(CFG); + for (const auto &[From, To] : Backedges) { + if (From->getLoopTarget() == nullptr) + NonStructLoopBackedgeNodes.insert(From); + } + return NonStructLoopBackedgeNodes; +} + +bool isBackedgeCFGNode( + const CFGBlock &B, + const llvm::SmallDenseSet &NonStructLoopBackedgeNodes) { + return B.getLoopTarget() != nullptr || + NonStructLoopBackedgeNodes.contains(&B); +} + +} // namespace clang diff --git a/clang/lib/Analysis/CMakeLists.txt b/clang/lib/Analysis/CMakeLists.txt index 65f160e965d47..fef688424978d 100644 --- a/clang/lib/Analysis/CMakeLists.txt +++ b/clang/lib/Analysis/CMakeLists.txt @@ -9,6 +9,7 @@ add_clang_library(clangAnalysis BodyFarm.cpp CalledOnceCheck.cpp CFG.cpp + CFGBackEdges.cpp CFGReachabilityAnalysis.cpp CFGStmtMap.cpp CallGraph.cpp diff --git a/clang/lib/Analysis/CloneDetection.cpp b/clang/lib/Analysis/CloneDetection.cpp index 52dd88bba024a..451aabc78b3a8 100644 --- a/clang/lib/Analysis/CloneDetection.cpp +++ b/clang/lib/Analysis/CloneDetection.cpp @@ -403,8 +403,8 @@ void RecursiveCloneTypeIIHashConstraint::constrain( Result.push_back(NewGroup); } } - // Sequences is the output parameter, so we copy our result into it. - Sequences = Result; + // Sequences is the output parameter, so we move our result into it. + Sequences = std::move(Result); } void RecursiveCloneTypeIIVerifyConstraint::constrain( @@ -519,7 +519,7 @@ void CloneConstraint::splitCloneGroups( assert(llvm::all_of(Indexes, [](char c) { return c == 1; })); } - CloneGroups = Result; + CloneGroups = std::move(Result); } void VariablePattern::addVariableOccurence(const VarDecl *VarDecl, diff --git a/clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp b/clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp index 94aa05559c5db..7dc3f5872f4d8 100644 --- a/clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp +++ b/clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp @@ -238,32 +238,30 @@ static auto possiblyReferencedStatusOrType() { return anyOf(statusOrType(), referenceType(pointee(statusOrType()))); } -static auto isConstStatusOrAccessorMemberCall() { +static auto isConstAccessorMemberCall() { using namespace ::clang::ast_matchers; // NOLINT: Too many names - return cxxMemberCallExpr(callee( - cxxMethodDecl(parameterCountIs(0), isConst(), - returns(qualType(possiblyReferencedStatusOrType()))))); + return cxxMemberCallExpr(callee(cxxMethodDecl( + parameterCountIs(0), isConst(), + returns(hasCanonicalType(anyOf(referenceType(), recordType())))))); } -static auto isConstStatusOrAccessorMemberOperatorCall() { +static auto isConstAccessorMemberOperatorCall() { using namespace ::clang::ast_matchers; // NOLINT: Too many names - return cxxOperatorCallExpr( - callee(cxxMethodDecl(parameterCountIs(0), isConst(), - returns(possiblyReferencedStatusOrType())))); + return cxxOperatorCallExpr(callee(cxxMethodDecl( + parameterCountIs(0), isConst(), + returns(hasCanonicalType(anyOf(referenceType(), recordType())))))); } -static auto isConstStatusOrPointerAccessorMemberCall() { +static auto isConstPointerAccessorMemberCall() { using namespace ::clang::ast_matchers; // NOLINT: Too many names - return cxxMemberCallExpr(callee(cxxMethodDecl( - parameterCountIs(0), isConst(), - returns(pointerType(pointee(possiblyReferencedStatusOrType())))))); + return cxxMemberCallExpr(callee( + cxxMethodDecl(parameterCountIs(0), isConst(), returns(pointerType())))); } -static auto isConstStatusOrPointerAccessorMemberOperatorCall() { +static auto isConstPointerAccessorMemberOperatorCall() { using namespace ::clang::ast_matchers; // NOLINT: Too many names - return cxxOperatorCallExpr(callee(cxxMethodDecl( - parameterCountIs(0), isConst(), - returns(pointerType(pointee(possiblyReferencedStatusOrType())))))); + return cxxOperatorCallExpr(callee( + cxxMethodDecl(parameterCountIs(0), isConst(), returns(pointerType())))); } static auto isNonConstMemberCall() { @@ -874,10 +872,9 @@ static void transferStatusOrReturningCall(const CallExpr *Expr, initializeStatusOr(*StatusOrLoc, State.Env); } -static bool doHandleConstStatusOrAccessorMemberCall( +static bool doHandleConstAccessorMemberCall( const CallExpr *Expr, RecordStorageLocation *RecordLoc, const MatchFinder::MatchResult &Result, LatticeTransferState &State) { - assert(isStatusOrType(Expr->getType())); if (RecordLoc == nullptr) return false; const FunctionDecl *DirectCallee = Expr->getDirectCallee(); @@ -886,7 +883,8 @@ static bool doHandleConstStatusOrAccessorMemberCall( StorageLocation &Loc = State.Lattice.getOrCreateConstMethodReturnStorageLocation( *RecordLoc, DirectCallee, State.Env, [&](StorageLocation &Loc) { - initializeStatusOr(cast(Loc), State.Env); + if (isStatusOrType(Expr->getType())) + initializeStatusOr(cast(Loc), State.Env); }); if (Expr->isPRValue()) { auto &ResultLoc = State.Env.getResultObjectLocation(*Expr); @@ -897,13 +895,14 @@ static bool doHandleConstStatusOrAccessorMemberCall( return true; } -static void handleConstStatusOrAccessorMemberCall( +static void handleConstAccessorMemberCall( const CallExpr *Expr, RecordStorageLocation *RecordLoc, const MatchFinder::MatchResult &Result, LatticeTransferState &State) { - if (!doHandleConstStatusOrAccessorMemberCall(Expr, RecordLoc, Result, State)) + if (!doHandleConstAccessorMemberCall(Expr, RecordLoc, Result, State) && + isStatusOrType(Expr->getType())) transferStatusOrReturningCall(Expr, State); } -static void handleConstStatusOrPointerAccessorMemberCall( +static void handleConstPointerAccessorMemberCall( const CallExpr *Expr, RecordStorageLocation *RecordLoc, const MatchFinder::MatchResult &Result, LatticeTransferState &State) { if (RecordLoc == nullptr) @@ -914,34 +913,42 @@ static void handleConstStatusOrPointerAccessorMemberCall( } static void -transferConstStatusOrAccessorMemberCall(const CXXMemberCallExpr *Expr, - const MatchFinder::MatchResult &Result, - LatticeTransferState &State) { - handleConstStatusOrAccessorMemberCall( +transferConstAccessorMemberCall(const CXXMemberCallExpr *Expr, + const MatchFinder::MatchResult &Result, + LatticeTransferState &State) { + auto Type = Expr->getType(); + if (!Type->isRecordType() && !Type->isReferenceType()) + return; + handleConstAccessorMemberCall( Expr, getImplicitObjectLocation(*Expr, State.Env), Result, State); } -static void transferConstStatusOrAccessorMemberOperatorCall( - const CXXOperatorCallExpr *Expr, const MatchFinder::MatchResult &Result, - LatticeTransferState &State) { +static void +transferConstAccessorMemberOperatorCall(const CXXOperatorCallExpr *Expr, + const MatchFinder::MatchResult &Result, + LatticeTransferState &State) { + auto Type = Expr->getArg(0)->getType(); + if (!Type->isRecordType() && !Type->isReferenceType()) + return; auto *RecordLoc = cast_or_null( State.Env.getStorageLocation(*Expr->getArg(0))); - handleConstStatusOrAccessorMemberCall(Expr, RecordLoc, Result, State); + handleConstAccessorMemberCall(Expr, RecordLoc, Result, State); } -static void transferConstStatusOrPointerAccessorMemberCall( - const CXXMemberCallExpr *Expr, const MatchFinder::MatchResult &Result, - LatticeTransferState &State) { - handleConstStatusOrPointerAccessorMemberCall( +static void +transferConstPointerAccessorMemberCall(const CXXMemberCallExpr *Expr, + const MatchFinder::MatchResult &Result, + LatticeTransferState &State) { + handleConstPointerAccessorMemberCall( Expr, getImplicitObjectLocation(*Expr, State.Env), Result, State); } -static void transferConstStatusOrPointerAccessorMemberOperatorCall( +static void transferConstPointerAccessorMemberOperatorCall( const CXXOperatorCallExpr *Expr, const MatchFinder::MatchResult &Result, LatticeTransferState &State) { auto *RecordLoc = cast_or_null( State.Env.getStorageLocation(*Expr->getArg(0))); - handleConstStatusOrPointerAccessorMemberCall(Expr, RecordLoc, Result, State); + handleConstPointerAccessorMemberCall(Expr, RecordLoc, Result, State); } static void handleNonConstMemberCall(const CallExpr *Expr, @@ -1265,17 +1272,16 @@ buildTransferMatchSwitch(ASTContext &Ctx, [](StorageLocation &Loc) {}); }) // const accessor calls - .CaseOfCFGStmt(isConstStatusOrAccessorMemberCall(), - transferConstStatusOrAccessorMemberCall) + .CaseOfCFGStmt(isConstAccessorMemberCall(), + transferConstAccessorMemberCall) .CaseOfCFGStmt( - isConstStatusOrAccessorMemberOperatorCall(), - transferConstStatusOrAccessorMemberOperatorCall) - .CaseOfCFGStmt( - isConstStatusOrPointerAccessorMemberCall(), - transferConstStatusOrPointerAccessorMemberCall) + isConstAccessorMemberOperatorCall(), + transferConstAccessorMemberOperatorCall) + .CaseOfCFGStmt(isConstPointerAccessorMemberCall(), + transferConstPointerAccessorMemberCall) .CaseOfCFGStmt( - isConstStatusOrPointerAccessorMemberOperatorCall(), - transferConstStatusOrPointerAccessorMemberOperatorCall) + isConstPointerAccessorMemberOperatorCall(), + transferConstPointerAccessorMemberOperatorCall) // non-const member calls that may modify the state of an object. .CaseOfCFGStmt(isNonConstMemberCall(), transferNonConstMemberCall) diff --git a/clang/lib/Analysis/FlowSensitive/Transfer.cpp b/clang/lib/Analysis/FlowSensitive/Transfer.cpp index 51cc1f9bc26ab..445f39b43f683 100644 --- a/clang/lib/Analysis/FlowSensitive/Transfer.cpp +++ b/clang/lib/Analysis/FlowSensitive/Transfer.cpp @@ -169,8 +169,16 @@ class TransferVisitor : public ConstStmtVisitor { break; auto *RHSVal = Env.getValue(*RHS); - if (RHSVal == nullptr) + if (RHSVal == nullptr) { RHSVal = Env.createValue(LHS->getType()); + if (RHSVal == nullptr) { + // At least make sure the old value is gone. It's unlikely to be there + // in the first place given that we don't even know how to create + // a basic unknown value of that type. + Env.clearValue(*LHSLoc); + break; + } + } // Assign a value to the storage location of the left-hand side. Env.setValue(*LHSLoc, *RHSVal); @@ -328,7 +336,6 @@ class TransferVisitor : public ConstStmtVisitor { RecordStorageLocation *Loc = nullptr; if (S->getType()->isPointerType()) { auto *PV = Env.get(*SubExpr); - assert(PV != nullptr); if (PV == nullptr) break; Loc = cast(&PV->getPointeeLoc()); diff --git a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp index 1113bbe7f4d9c..02982274093cb 100644 --- a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp +++ b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp @@ -19,18 +19,23 @@ #include "clang/AST/ASTDumper.h" #include "clang/AST/DeclCXX.h" #include "clang/AST/OperationKinds.h" +#include "clang/AST/Stmt.h" #include "clang/AST/StmtCXX.h" #include "clang/AST/StmtVisitor.h" #include "clang/Analysis/Analyses/PostOrderCFGView.h" #include "clang/Analysis/CFG.h" +#include "clang/Analysis/CFGBackEdges.h" #include "clang/Analysis/FlowSensitive/DataflowEnvironment.h" #include "clang/Analysis/FlowSensitive/DataflowLattice.h" #include "clang/Analysis/FlowSensitive/DataflowWorklist.h" #include "clang/Analysis/FlowSensitive/Transfer.h" #include "clang/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.h" #include "clang/Analysis/FlowSensitive/Value.h" +#include "clang/Basic/LLVM.h" #include "clang/Support/Compiler.h" #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Error.h" @@ -64,16 +69,6 @@ static int blockIndexInPredecessor(const CFGBlock &Pred, return BlockPos - Pred.succ_begin(); } -// A "backedge" node is a block introduced in the CFG exclusively to indicate a -// loop backedge. They are exactly identified by the presence of a non-null -// pointer to the entry block of the loop condition. Note that this is not -// necessarily the block with the loop statement as terminator, because -// short-circuit operators will result in multiple blocks encoding the loop -// condition, only one of which will contain the loop statement as terminator. -static bool isBackedgeNode(const CFGBlock &B) { - return B.getLoopTarget() != nullptr; -} - namespace { /// Extracts the terminator's condition expression. @@ -503,6 +498,8 @@ runTypeErasedDataflowAnalysis( const clang::CFG &CFG = ACFG.getCFG(); PostOrderCFGView POV(&CFG); ForwardDataflowWorklist Worklist(CFG, &POV); + llvm::SmallDenseSet NonStructLoopBackedgeNodes = + findNonStructuredLoopBackedgeNodes(CFG); std::vector> BlockStates( CFG.size()); @@ -537,7 +534,7 @@ runTypeErasedDataflowAnalysis( llvm::errs() << "Old Env:\n"; OldBlockState->Env.dump(); }); - if (isBackedgeNode(*Block)) { + if (isBackedgeCFGNode(*Block, NonStructLoopBackedgeNodes)) { LatticeJoinEffect Effect1 = Analysis.widenTypeErased( NewBlockState.Lattice, OldBlockState->Lattice); LatticeJoinEffect Effect2 = diff --git a/clang/lib/Analysis/LifetimeSafety/CMakeLists.txt b/clang/lib/Analysis/LifetimeSafety/CMakeLists.txt index e5876e747610a..247377c7256d9 100644 --- a/clang/lib/Analysis/LifetimeSafety/CMakeLists.txt +++ b/clang/lib/Analysis/LifetimeSafety/CMakeLists.txt @@ -8,6 +8,7 @@ add_clang_library(clangAnalysisLifetimeSafety LifetimeStats.cpp Loans.cpp LoanPropagation.cpp + MovedLoans.cpp Origins.cpp LINK_LIBS diff --git a/clang/lib/Analysis/LifetimeSafety/Checker.cpp b/clang/lib/Analysis/LifetimeSafety/Checker.cpp index c954a9b14bcdf..78c2a6dba3eb6 100644 --- a/clang/lib/Analysis/LifetimeSafety/Checker.cpp +++ b/clang/lib/Analysis/LifetimeSafety/Checker.cpp @@ -24,6 +24,7 @@ #include "clang/Basic/SourceLocation.h" #include "clang/Basic/SourceManager.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TimeProfiler.h" @@ -47,6 +48,8 @@ namespace { struct PendingWarning { SourceLocation ExpiryLoc; // Where the loan expired. llvm::PointerUnion CausingFact; + const Expr *MovedExpr; + const Expr *InvalidatedByExpr; Confidence ConfidenceLevel; }; @@ -60,22 +63,27 @@ class LifetimeChecker { llvm::DenseMap AnnotationWarningsMap; llvm::DenseMap NoescapeWarningsMap; const LoanPropagationAnalysis &LoanPropagation; + const MovedLoansAnalysis &MovedLoans; const LiveOriginsAnalysis &LiveOrigins; - const FactManager &FactMgr; + FactManager &FactMgr; LifetimeSafetySemaHelper *SemaHelper; ASTContext &AST; public: LifetimeChecker(const LoanPropagationAnalysis &LoanPropagation, - const LiveOriginsAnalysis &LiveOrigins, const FactManager &FM, + const MovedLoansAnalysis &MovedLoans, + const LiveOriginsAnalysis &LiveOrigins, FactManager &FM, AnalysisDeclContext &ADC, LifetimeSafetySemaHelper *SemaHelper) - : LoanPropagation(LoanPropagation), LiveOrigins(LiveOrigins), FactMgr(FM), - SemaHelper(SemaHelper), AST(ADC.getASTContext()) { + : LoanPropagation(LoanPropagation), MovedLoans(MovedLoans), + LiveOrigins(LiveOrigins), FactMgr(FM), SemaHelper(SemaHelper), + AST(ADC.getASTContext()) { for (const CFGBlock *B : *ADC.getAnalysis()) for (const Fact *F : FactMgr.getFacts(B)) if (const auto *EF = F->getAs()) checkExpiry(EF); + else if (const auto *IOF = F->getAs()) + checkInvalidation(IOF); else if (const auto *OEF = F->getAs()) checkAnnotations(OEF); issuePendingWarnings(); @@ -140,6 +148,10 @@ class LifetimeChecker { /// propagation (e.g., a loan may only be held on some execution paths). void checkExpiry(const ExpireFact *EF) { LoanID ExpiredLoan = EF->getLoanID(); + const Expr *MovedExpr = nullptr; + if (auto *ME = MovedLoans.getMovedLoans(EF).lookup(ExpiredLoan)) + MovedExpr = *ME; + LivenessMap Origins = LiveOrigins.getLiveOriginsAt(EF); Confidence CurConfidence = Confidence::None; // The UseFact or OriginEscapesFact most indicative of a lifetime error, @@ -166,32 +178,98 @@ class LifetimeChecker { return; FinalWarningsMap[ExpiredLoan] = {/*ExpiryLoc=*/EF->getExpiryLoc(), /*BestCausingFact=*/BestCausingFact, + /*MovedExpr=*/MovedExpr, + /*InvalidatedByExpr=*/nullptr, /*ConfidenceLevel=*/CurConfidence}; } + /// Checks for use-after-invalidation errors when a container is modified. + /// + /// This method identifies origins that are live at the point of invalidation + /// and checks if they hold loans that are invalidated by the operation + /// (e.g., iterators into a vector that is being pushed to). + void checkInvalidation(const InvalidateOriginFact *IOF) { + OriginID InvalidatedOrigin = IOF->getInvalidatedOrigin(); + /// Get loans directly pointing to the invalidated container + LoanSet DirectlyInvalidatedLoans = + LoanPropagation.getLoans(InvalidatedOrigin, IOF); + auto IsInvalidated = [&](const Loan *L) { + auto *PathL = dyn_cast(L); + auto *PlaceholderL = dyn_cast(L); + for (LoanID InvalidID : DirectlyInvalidatedLoans) { + const Loan *L = FactMgr.getLoanMgr().getLoan(InvalidID); + auto *InvalidPathL = dyn_cast(L); + auto *InvalidPlaceholderL = dyn_cast(L); + if (PathL && InvalidPathL && + PathL->getAccessPath() == InvalidPathL->getAccessPath()) + return true; + if (PlaceholderL && InvalidPlaceholderL && + PlaceholderL->getParmVarDecl() == + InvalidPlaceholderL->getParmVarDecl()) + return true; + } + return false; + }; + // For each live origin, check if it holds an invalidated loan and report. + LivenessMap Origins = LiveOrigins.getLiveOriginsAt(IOF); + for (auto &[OID, LiveInfo] : Origins) { + LoanSet HeldLoans = LoanPropagation.getLoans(OID, IOF); + for (LoanID LiveLoanID : HeldLoans) + if (IsInvalidated(FactMgr.getLoanMgr().getLoan(LiveLoanID))) { + Confidence CurConfidence = livenessKindToConfidence(LiveInfo.Kind); + Confidence LastConf = + FinalWarningsMap.lookup(LiveLoanID).ConfidenceLevel; + if (LastConf < CurConfidence) { + FinalWarningsMap[LiveLoanID] = { + /*ExpiryLoc=*/{}, + /*CausingFact=*/LiveInfo.CausingFact, + /*MovedExpr=*/nullptr, + /*InvalidatedByExpr=*/IOF->getInvalidationExpr(), + /*ConfidenceLevel=*/CurConfidence}; + } + } + } + } + void issuePendingWarnings() { if (!SemaHelper) return; for (const auto &[LID, Warning] : FinalWarningsMap) { const Loan *L = FactMgr.getLoanMgr().getLoan(LID); - const auto *BL = cast(L); - const Expr *IssueExpr = BL->getIssueExpr(); + + const Expr *IssueExpr = nullptr; + if (const auto *BL = dyn_cast(L)) + IssueExpr = BL->getIssueExpr(); + const ParmVarDecl *InvalidatedPVD = nullptr; + if (const auto *PL = dyn_cast(L)) + InvalidatedPVD = PL->getParmVarDecl(); llvm::PointerUnion CausingFact = Warning.CausingFact; Confidence Confidence = Warning.ConfidenceLevel; + const Expr *MovedExpr = Warning.MovedExpr; SourceLocation ExpiryLoc = Warning.ExpiryLoc; - if (const auto *UF = CausingFact.dyn_cast()) - SemaHelper->reportUseAfterFree(IssueExpr, UF->getUseExpr(), ExpiryLoc, - Confidence); - else if (const auto *OEF = - CausingFact.dyn_cast()) { + if (const auto *UF = CausingFact.dyn_cast()) { + if (Warning.InvalidatedByExpr) { + if (IssueExpr) + SemaHelper->reportUseAfterInvalidation(IssueExpr, UF->getUseExpr(), + Warning.InvalidatedByExpr); + if (InvalidatedPVD) + SemaHelper->reportUseAfterInvalidation( + InvalidatedPVD, UF->getUseExpr(), Warning.InvalidatedByExpr); + + } else + SemaHelper->reportUseAfterFree(IssueExpr, UF->getUseExpr(), MovedExpr, + ExpiryLoc, Confidence); + } else if (const auto *OEF = + CausingFact.dyn_cast()) { if (const auto *RetEscape = dyn_cast(OEF)) - SemaHelper->reportUseAfterReturn( - IssueExpr, RetEscape->getReturnExpr(), ExpiryLoc, Confidence); + SemaHelper->reportUseAfterReturn(IssueExpr, + RetEscape->getReturnExpr(), + MovedExpr, ExpiryLoc, Confidence); else if (const auto *FieldEscape = dyn_cast(OEF)) SemaHelper->reportDanglingField( - IssueExpr, FieldEscape->getFieldDecl(), ExpiryLoc); + IssueExpr, FieldEscape->getFieldDecl(), MovedExpr, ExpiryLoc); else llvm_unreachable("Unhandled OriginEscapesFact type"); } else @@ -293,11 +371,12 @@ class LifetimeChecker { } // namespace void runLifetimeChecker(const LoanPropagationAnalysis &LP, - const LiveOriginsAnalysis &LO, - const FactManager &FactMgr, AnalysisDeclContext &ADC, + const MovedLoansAnalysis &MovedLoans, + const LiveOriginsAnalysis &LO, FactManager &FactMgr, + AnalysisDeclContext &ADC, LifetimeSafetySemaHelper *SemaHelper) { llvm::TimeTraceScope TimeProfile("LifetimeChecker"); - LifetimeChecker Checker(LP, LO, FactMgr, ADC, SemaHelper); + LifetimeChecker Checker(LP, MovedLoans, LO, FactMgr, ADC, SemaHelper); } } // namespace clang::lifetimes::internal diff --git a/clang/lib/Analysis/LifetimeSafety/Dataflow.h b/clang/lib/Analysis/LifetimeSafety/Dataflow.h index 05c20d6385368..0f64ac8a36ef7 100644 --- a/clang/lib/Analysis/LifetimeSafety/Dataflow.h +++ b/clang/lib/Analysis/LifetimeSafety/Dataflow.h @@ -170,12 +170,16 @@ class DataflowAnalysis { return D->transfer(In, *F->getAs()); case Fact::Kind::OriginFlow: return D->transfer(In, *F->getAs()); + case Fact::Kind::MovedOrigin: + return D->transfer(In, *F->getAs()); case Fact::Kind::OriginEscapes: return D->transfer(In, *F->getAs()); case Fact::Kind::Use: return D->transfer(In, *F->getAs()); case Fact::Kind::TestPoint: return D->transfer(In, *F->getAs()); + case Fact::Kind::InvalidateOrigin: + return D->transfer(In, *F->getAs()); } llvm_unreachable("Unknown fact kind"); } @@ -184,9 +188,11 @@ class DataflowAnalysis { Lattice transfer(Lattice In, const IssueFact &) { return In; } Lattice transfer(Lattice In, const ExpireFact &) { return In; } Lattice transfer(Lattice In, const OriginFlowFact &) { return In; } + Lattice transfer(Lattice In, const MovedOriginFact &) { return In; } Lattice transfer(Lattice In, const OriginEscapesFact &) { return In; } Lattice transfer(Lattice In, const UseFact &) { return In; } Lattice transfer(Lattice In, const TestPointFact &) { return In; } + Lattice transfer(Lattice In, const InvalidateOriginFact &) { return In; } }; } // namespace clang::lifetimes::internal #endif // LLVM_CLANG_ANALYSIS_ANALYSES_LIFETIMESAFETY_DATAFLOW_H diff --git a/clang/lib/Analysis/LifetimeSafety/Facts.cpp b/clang/lib/Analysis/LifetimeSafety/Facts.cpp index 1fc72aa0a4259..c963d9c45fa9d 100644 --- a/clang/lib/Analysis/LifetimeSafety/Facts.cpp +++ b/clang/lib/Analysis/LifetimeSafety/Facts.cpp @@ -9,6 +9,8 @@ #include "clang/Analysis/Analyses/LifetimeSafety/Facts.h" #include "clang/AST/Decl.h" #include "clang/Analysis/Analyses/PostOrderCFGView.h" +#include "clang/Analysis/FlowSensitive/DataflowWorklist.h" +#include "llvm/ADT/STLFunctionalExtras.h" namespace clang::lifetimes::internal { @@ -45,6 +47,13 @@ void OriginFlowFact::dump(llvm::raw_ostream &OS, const LoanManager &, OS << "\n"; } +void MovedOriginFact::dump(llvm::raw_ostream &OS, const LoanManager &, + const OriginManager &OM) const { + OS << "MovedOrigins ("; + OM.dump(getMovedOrigin(), OS); + OS << ")\n"; +} + void ReturnEscapeFact::dump(llvm::raw_ostream &OS, const LoanManager &, const OriginManager &OM) const { OS << "OriginEscapes ("; @@ -73,6 +82,13 @@ void UseFact::dump(llvm::raw_ostream &OS, const LoanManager &, OS << ", " << (isWritten() ? "Write" : "Read") << ")\n"; } +void InvalidateOriginFact::dump(llvm::raw_ostream &OS, const LoanManager &, + const OriginManager &OM) const { + OS << "InvalidateOrigin ("; + OM.dump(getInvalidatedOrigin(), OS); + OS << ")\n"; +} + void TestPointFact::dump(llvm::raw_ostream &OS, const LoanManager &, const OriginManager &) const { OS << "TestPoint (Annotation: \"" << getAnnotation() << "\")\n"; diff --git a/clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp b/clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp index fb859eeb856af..b69f69ddbae34 100644 --- a/clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp +++ b/clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp @@ -9,6 +9,9 @@ #include #include +#include "clang/AST/DeclCXX.h" +#include "clang/AST/Expr.h" +#include "clang/AST/ExprCXX.h" #include "clang/AST/OperationKinds.h" #include "clang/Analysis/Analyses/LifetimeSafety/Facts.h" #include "clang/Analysis/Analyses/LifetimeSafety/FactsGenerator.h" @@ -185,6 +188,9 @@ void FactsGenerator::VisitCXXConstructExpr(const CXXConstructExpr *CCE) { handleGSLPointerConstruction(CCE); return; } + handleFunctionCall(CCE, CCE->getConstructor(), + {CCE->getArgs(), CCE->getNumArgs()}, + /*IsGslConstruction=*/false); } void FactsGenerator::handleCXXCtorInitializer(const CXXCtorInitializer *CII) { @@ -233,23 +239,9 @@ void FactsGenerator::VisitMemberExpr(const MemberExpr *ME) { } } -static bool isStdMove(const FunctionDecl *FD) { - return FD && FD->isInStdNamespace() && FD->getIdentifier() && - FD->getName() == "move"; -} - void FactsGenerator::VisitCallExpr(const CallExpr *CE) { handleFunctionCall(CE, CE->getDirectCallee(), {CE->getArgs(), CE->getNumArgs()}); - // Track declarations that are moved via std::move. - // This is a flow-insensitive approximation: once a declaration is moved - // anywhere in the function, it's treated as moved everywhere. We do not - // generate expire facts for moved decls to avoid false alarms. - if (isStdMove(CE->getDirectCallee())) - if (CE->getNumArgs() == 1) - if (auto *DRE = - dyn_cast(CE->getArg(0)->IgnoreParenImpCasts())) - MovedDecls.insert(DRE->getDecl()); } void FactsGenerator::VisitCXXNullPtrLiteralExpr( @@ -453,11 +445,6 @@ void FactsGenerator::handleLifetimeEnds(const CFGLifetimeEnds &LifetimeEnds) { // Iterate through all loans to see if any expire. for (const auto *Loan : FactMgr.getLoanMgr().getLoans()) { if (const auto *BL = dyn_cast(Loan)) { - // Skip loans for declarations that have been moved. When a value is - // moved, the original owner no longer has ownership and its destruction - // should not cause the loan to expire, preventing false positives. - if (MovedDecls.contains(BL->getAccessPath().getAsValueDecl())) - continue; // Check if the loan is for a stack variable and if that variable // is the one being destructed. const AccessPath AP = BL->getAccessPath(); @@ -533,10 +520,59 @@ void FactsGenerator::handleGSLPointerConstruction(const CXXConstructExpr *CCE) { } } -/// Checks if a call-like expression creates a borrow by passing a value to a -/// reference parameter, creating an IssueFact if it does. -/// \param IsGslConstruction True if this is a GSL construction where all -/// argument origins should flow to the returned origin. +void FactsGenerator::handleMovedArgsInCall(const FunctionDecl *FD, + ArrayRef Args) { + unsigned IsInstance = 0; + if (const auto *Method = dyn_cast(FD); + Method && Method->isInstance() && !isa(FD)) + IsInstance = 1; + + // Skip 'this' arg as it cannot be moved. + for (unsigned I = IsInstance; + I < Args.size() && I < FD->getNumParams() + IsInstance; ++I) { + const ParmVarDecl *PVD = FD->getParamDecl(I - IsInstance); + if (!PVD->getType()->isRValueReferenceType()) + continue; + const Expr *Arg = Args[I]; + OriginList *MovedOrigins = getOriginsList(*Arg); + assert(MovedOrigins->getLength() >= 1 && + "unexpected length for r-value reference param"); + // Arg is being moved to this parameter. Mark the origin as moved. + CurrentBlockFacts.push_back(FactMgr.createFact( + Arg, MovedOrigins->getOuterOriginID())); + } +} + +void FactsGenerator::handleInvalidatingCall(const Expr *Call, + const FunctionDecl *FD, + ArrayRef Args) { + const auto *MD = dyn_cast(FD); + if (!MD || !MD->isInstance()) + return; + // std::unique_ptr::release() transfers ownership. + // Treat it as a move to prevent false-positive warnings when the unique_ptr + // destructor runs after ownership has been transferred. + if (isUniquePtrRelease(*MD)) { + const Expr *UniquePtrExpr = Args[0]; + OriginList *MovedOrigins = getOriginsList(*UniquePtrExpr); + if (MovedOrigins) + CurrentBlockFacts.push_back(FactMgr.createFact( + UniquePtrExpr, MovedOrigins->getOuterOriginID())); + } + + if (!isContainerInvalidationMethod(*MD)) + return; + // Heuristics to turn-down false positives. + auto *DRE = dyn_cast(Args[0]); + if (!DRE || DRE->getDecl()->getType()->isReferenceType()) + return; + + OriginList *ThisList = getOriginsList(*Args[0]); + if (ThisList) + CurrentBlockFacts.push_back(FactMgr.createFact( + ThisList->getOuterOriginID(), Call)); +} + void FactsGenerator::handleFunctionCall(const Expr *Call, const FunctionDecl *FD, ArrayRef Args, @@ -544,7 +580,12 @@ void FactsGenerator::handleFunctionCall(const Expr *Call, OriginList *CallList = getOriginsList(*Call); // Ignore functions returning values with no origin. FD = getDeclWithMergedLifetimeBoundAttrs(FD); - if (!FD || !CallList) + if (!FD) + return; + + handleInvalidatingCall(Call, FD, Args); + handleMovedArgsInCall(FD, Args); + if (!CallList) return; auto IsArgLifetimeBound = [FD](unsigned I) -> bool { const ParmVarDecl *PVD = nullptr; diff --git a/clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp b/clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp index be33caf327802..01666f4ac271c 100644 --- a/clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp +++ b/clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp @@ -174,13 +174,41 @@ bool shouldTrackImplicitObjectArg(const CXXMethodDecl *Callee, } bool shouldTrackFirstArgument(const FunctionDecl *FD) { - if (!FD->getIdentifier() || FD->getNumParams() != 1) + if (!FD->getIdentifier() || FD->getNumParams() < 1) return false; + if (!FD->isInStdNamespace()) + return false; + // Track std:: algorithm functions that return an iterator whose lifetime is + // bound to the first argument. + if (FD->getNumParams() >= 2 && FD->isInStdNamespace() && + isGslPointerType(FD->getReturnType())) { + if (llvm::StringSwitch(FD->getName()) + .Cases( + { + "find", + "find_if", + "find_if_not", + "find_first_of", + "adjacent_find", + "search", + "find_end", + "lower_bound", + "upper_bound", + "partition_point", + }, + true) + .Default(false)) + return true; + } const auto *RD = FD->getParamDecl(0)->getType()->getPointeeCXXRecordDecl(); - if (!FD->isInStdNamespace() || !RD || !RD->isInStdNamespace()) + if (!RD || !RD->isInStdNamespace()) return false; if (!RD->hasAttr() && !RD->hasAttr()) return false; + + if (FD->getNumParams() != 1) + return false; + if (FD->getReturnType()->isPointerType() || isGslPointerType(FD->getReturnType())) { return llvm::StringSwitch(FD->getName()) @@ -227,4 +255,82 @@ template static bool isRecordWithAttr(QualType Type) { bool isGslPointerType(QualType QT) { return isRecordWithAttr(QT); } bool isGslOwnerType(QualType QT) { return isRecordWithAttr(QT); } +static StringRef getName(const CXXRecordDecl &RD) { + if (const auto *CTSD = dyn_cast(&RD)) + return CTSD->getSpecializedTemplate()->getName(); + if (RD.getIdentifier()) + return RD.getName(); + return ""; +} + +static bool isStdUniquePtr(const CXXRecordDecl &RD) { + return RD.isInStdNamespace() && getName(RD) == "unique_ptr"; +} + +bool isUniquePtrRelease(const CXXMethodDecl &MD) { + return MD.getIdentifier() && MD.getName() == "release" && + MD.getNumParams() == 0 && isStdUniquePtr(*MD.getParent()); +} + +bool isContainerInvalidationMethod(const CXXMethodDecl &MD) { + const CXXRecordDecl *RD = MD.getParent(); + if (!isInStlNamespace(RD)) + return false; + + StringRef ContainerName = getName(*RD); + static const llvm::StringSet<> Containers = { + // Sequence + "vector", "basic_string", "deque", + // Adaptors + // FIXME: Add queue and stack and check for underlying container (e.g. no + // invalidation for std::list). + "priority_queue", + // Associative + "set", "multiset", "map", "multimap", + // Unordered Associative + "unordered_set", "unordered_multiset", "unordered_map", + "unordered_multimap", + // C++23 Flat + "flat_map", "flat_set", "flat_multimap", "flat_multiset"}; + + if (!Containers.contains(ContainerName)) + return false; + + // Handle Operators via OverloadedOperatorKind + OverloadedOperatorKind OO = MD.getOverloadedOperator(); + if (OO != OO_None) { + switch (OO) { + case OO_Equal: // operator= : Always invalidates (Assignment) + case OO_PlusEqual: // operator+= : Append (String/Vector) + return true; + case OO_Subscript: // operator[] : Invalidation only for Maps + // (Insert-or-access) + { + static const llvm::StringSet<> MapContainers = {"map", "unordered_map", + "flat_map"}; + return MapContainers.contains(ContainerName); + } + default: + return false; + } + } + + if (!MD.getIdentifier()) + return false; + static const llvm::StringSet<> InvalidatingMembers = { + // Basic Insertion/Emplacement + "push_front", "push_back", "emplace_front", "emplace_back", "insert", + "emplace", "push", + // Basic Removal/Clearing + "pop_front", "pop_back", "pop", "erase", "clear", + // Memory Management + "reserve", "resize", "shrink_to_fit", + // Assignment (Named) + "assign", "swap", + // String Specifics + "append", "replace", + // Modern C++ (C++17/23) + "extract", "try_emplace", "insert_range", "append_range", "assign_range"}; + return InvalidatingMembers.contains(MD.getName()); +} } // namespace clang::lifetimes diff --git a/clang/lib/Analysis/LifetimeSafety/LifetimeSafety.cpp b/clang/lib/Analysis/LifetimeSafety/LifetimeSafety.cpp index bf9a65254e8fa..a6bea74c50b49 100644 --- a/clang/lib/Analysis/LifetimeSafety/LifetimeSafety.cpp +++ b/clang/lib/Analysis/LifetimeSafety/LifetimeSafety.cpp @@ -56,21 +56,12 @@ void LifetimeSafetyAnalysis::run() { llvm::TimeTraceScope TimeProfile("LifetimeSafetyAnalysis"); const CFG &Cfg = *AC.getCFG(); - DEBUG_WITH_TYPE("PrintCFG", Cfg.dump(AC.getASTContext().getLangOpts(), - /*ShowColors=*/true)); FactMgr = std::make_unique(AC, Cfg); FactsGenerator FactGen(*FactMgr, AC); FactGen.run(); - DEBUG_WITH_TYPE("LifetimeFacts", FactMgr->dump(Cfg, AC)); - - // Debug print facts for a specific function using - // -debug-only=EnableFilterByFunctionName,YourFunctionNameFoo - DEBUG_WITH_TYPE("EnableFilterByFunctionName", - DebugOnlyFunction(AC, Cfg, *FactMgr)); - /// TODO(opt): Consider optimizing individual blocks before running the /// dataflow analysis. /// 1. Expression Origins: These are assigned once and read at most once, @@ -87,10 +78,25 @@ void LifetimeSafetyAnalysis::run() { LiveOrigins = std::make_unique( Cfg, AC, *FactMgr, Factory.LivenessMapFactory); + + MovedLoans = std::make_unique( + Cfg, AC, *FactMgr, *LoanPropagation, *LiveOrigins, FactMgr->getLoanMgr(), + Factory.MovedLoansMapFactory); + + runLifetimeChecker(*LoanPropagation, *MovedLoans, *LiveOrigins, *FactMgr, AC, + SemaHelper); + + DEBUG_WITH_TYPE("PrintCFG", Cfg.dump(AC.getASTContext().getLangOpts(), + /*ShowColors=*/true)); + + DEBUG_WITH_TYPE("LifetimeFacts", FactMgr->dump(Cfg, AC)); + + // Debug print facts for a specific function using + // -debug-only=EnableFilterByFunctionName,YourFunctionNameFoo + DEBUG_WITH_TYPE("EnableFilterByFunctionName", + DebugOnlyFunction(AC, Cfg, *FactMgr)); DEBUG_WITH_TYPE("LiveOrigins", LiveOrigins->dump(llvm::dbgs(), FactMgr->getTestPoints())); - - runLifetimeChecker(*LoanPropagation, *LiveOrigins, *FactMgr, AC, SemaHelper); } void collectLifetimeStats(AnalysisDeclContext &AC, OriginManager &OM, diff --git a/clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp b/clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp index 01a74d30408ea..8a020eb829be6 100644 --- a/clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp +++ b/clang/lib/Analysis/LifetimeSafety/LoanPropagation.cpp @@ -63,9 +63,11 @@ static llvm::BitVector computePersistentOrigins(const FactManager &FactMgr, Cur = Cur->peelOuterOrigin()) CheckOrigin(Cur->getOuterOriginID()); break; + case Fact::Kind::MovedOrigin: case Fact::Kind::OriginEscapes: case Fact::Kind::Expire: case Fact::Kind::TestPoint: + case Fact::Kind::InvalidateOrigin: break; } } diff --git a/clang/lib/Analysis/LifetimeSafety/MovedLoans.cpp b/clang/lib/Analysis/LifetimeSafety/MovedLoans.cpp new file mode 100644 index 0000000000000..95de08d4425b0 --- /dev/null +++ b/clang/lib/Analysis/LifetimeSafety/MovedLoans.cpp @@ -0,0 +1,133 @@ +//===- MovedLoans.cpp - Moved Loans Analysis --------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the MovedLoansAnalysis, a forward dataflow analysis that +// tracks which loans have been moved out of their original storage location +// at each program point. +// +//===----------------------------------------------------------------------===// + +#include "clang/Analysis/Analyses/LifetimeSafety/MovedLoans.h" +#include "Dataflow.h" +#include "clang/Analysis/Analyses/LifetimeSafety/Facts.h" +#include "clang/Analysis/Analyses/LifetimeSafety/LiveOrigins.h" +#include "clang/Analysis/Analyses/LifetimeSafety/LoanPropagation.h" +#include "clang/Analysis/Analyses/LifetimeSafety/Loans.h" +#include "clang/Analysis/Analyses/LifetimeSafety/Utils.h" + +namespace clang::lifetimes::internal { +namespace { +struct Lattice { + MovedLoansMap MovedLoans = MovedLoansMap(nullptr); + + explicit Lattice(MovedLoansMap MovedLoans) : MovedLoans(MovedLoans) {} + + Lattice() = default; + + bool operator==(const Lattice &Other) const { + return MovedLoans == Other.MovedLoans; + } + bool operator!=(const Lattice &Other) const { return !(*this == Other); } +}; + +class AnalysisImpl + : public DataflowAnalysis { +public: + AnalysisImpl(const CFG &C, AnalysisDeclContext &AC, FactManager &F, + const LoanPropagationAnalysis &LoanPropagation, + const LiveOriginsAnalysis &LiveOrigins, + const LoanManager &LoanMgr, + MovedLoansMap::Factory &MovedLoansMapFactory) + : DataflowAnalysis(C, AC, F), LoanPropagation(LoanPropagation), + LiveOrigins(LiveOrigins), LoanMgr(LoanMgr), + MovedLoansMapFactory(MovedLoansMapFactory) {} + + using Base::transfer; + + StringRef getAnalysisName() const { return "MovedLoans"; } + + Lattice getInitialState() { return Lattice{}; } + + /// Merges moved loan state from different control flow paths. When a loan + /// is moved on multiple paths, picks the lexically earliest move expression. + Lattice join(Lattice A, Lattice B) { + MovedLoansMap MovedLoans = utils::join( + A.MovedLoans, B.MovedLoans, MovedLoansMapFactory, + [](const Expr *const *MoveA, const Expr *const *MoveB) -> const Expr * { + assert(MoveA || MoveB); + if (!MoveA) + return *MoveB; + if (!MoveB) + return *MoveA; + return (*MoveA)->getExprLoc() < (*MoveB)->getExprLoc() ? *MoveA + : *MoveB; + }, + utils::JoinKind::Asymmetric); + return Lattice(MovedLoans); + } + + /// Marks all live loans sharing the same access path as the moved origin as + /// potentially moved. + Lattice transfer(Lattice In, const MovedOriginFact &F) { + MovedLoansMap MovedLoans = In.MovedLoans; + OriginID MovedOrigin = F.getMovedOrigin(); + LoanSet ImmediatelyMovedLoans = LoanPropagation.getLoans(MovedOrigin, &F); + auto IsInvalidated = [&](const AccessPath &Path) { + for (LoanID LID : ImmediatelyMovedLoans) { + const Loan *MovedLoan = LoanMgr.getLoan(LID); + auto *PL = dyn_cast(MovedLoan); + if (!PL) + continue; + if (PL->getAccessPath() == Path) + return true; + } + return false; + }; + for (auto [O, _] : LiveOrigins.getLiveOriginsAt(&F)) + for (LoanID LiveLoan : LoanPropagation.getLoans(O, &F)) { + const Loan *LiveLoanPtr = LoanMgr.getLoan(LiveLoan); + auto *PL = dyn_cast(LiveLoanPtr); + if (!PL) + continue; + if (IsInvalidated(PL->getAccessPath())) + MovedLoans = + MovedLoansMapFactory.add(MovedLoans, LiveLoan, F.getMoveExpr()); + } + return Lattice(MovedLoans); + } + + MovedLoansMap getMovedLoans(ProgramPoint P) { return getState(P).MovedLoans; } + +private: + const LoanPropagationAnalysis &LoanPropagation; + const LiveOriginsAnalysis &LiveOrigins; + const LoanManager &LoanMgr; + MovedLoansMap::Factory &MovedLoansMapFactory; +}; +} // namespace + +class MovedLoansAnalysis::Impl final : public AnalysisImpl { + using AnalysisImpl::AnalysisImpl; +}; + +MovedLoansAnalysis::MovedLoansAnalysis( + const CFG &C, AnalysisDeclContext &AC, FactManager &F, + const LoanPropagationAnalysis &LoanPropagation, + const LiveOriginsAnalysis &LiveOrigins, const LoanManager &LoanMgr, + MovedLoansMap::Factory &MovedLoansMapFactory) + : PImpl(std::make_unique(C, AC, F, LoanPropagation, LiveOrigins, + LoanMgr, MovedLoansMapFactory)) { + PImpl->run(); +} + +MovedLoansAnalysis::~MovedLoansAnalysis() = default; + +MovedLoansMap MovedLoansAnalysis::getMovedLoans(ProgramPoint P) const { + return PImpl->getMovedLoans(P); +} +} // namespace clang::lifetimes::internal diff --git a/clang/lib/Analysis/Scalable/CMakeLists.txt b/clang/lib/Analysis/Scalable/CMakeLists.txt index 36365b1fb87e1..c8f959e274c6d 100644 --- a/clang/lib/Analysis/Scalable/CMakeLists.txt +++ b/clang/lib/Analysis/Scalable/CMakeLists.txt @@ -8,6 +8,7 @@ add_clang_library(clangAnalysisScalable Model/EntityIdTable.cpp Model/EntityName.cpp Serialization/SerializationFormat.cpp + Serialization/SerializationFormatRegistry.cpp TUSummary/ExtractorRegistry.cpp LINK_LIBS diff --git a/clang/lib/Analysis/Scalable/Serialization/SerializationFormat.cpp b/clang/lib/Analysis/Scalable/Serialization/SerializationFormat.cpp index ee155d22afa9b..224ad0c40cc2d 100644 --- a/clang/lib/Analysis/Scalable/Serialization/SerializationFormat.cpp +++ b/clang/lib/Analysis/Scalable/Serialization/SerializationFormat.cpp @@ -14,6 +14,10 @@ using namespace clang::ssaf; +SerializationFormat::SerializationFormat( + llvm::IntrusiveRefCntPtr FS) + : FS(FS) {} + EntityIdTable &SerializationFormat::getIdTableForDeserialization(TUSummary &S) { return S.IdTable; } @@ -59,3 +63,12 @@ const NestedBuildNamespace & SerializationFormat::getEntityNameNamespace(const EntityName &EN) { return EN.Namespace; } + +const decltype(TUSummary::Data) & +SerializationFormat::getData(const TUSummary &S) { + return S.Data; +} + +decltype(TUSummary::Data) &SerializationFormat::getData(TUSummary &S) { + return S.Data; +} diff --git a/clang/lib/Analysis/Scalable/Serialization/SerializationFormatRegistry.cpp b/clang/lib/Analysis/Scalable/Serialization/SerializationFormatRegistry.cpp new file mode 100644 index 0000000000000..f31a154866238 --- /dev/null +++ b/clang/lib/Analysis/Scalable/Serialization/SerializationFormatRegistry.cpp @@ -0,0 +1,36 @@ +//===- SerializationFormatRegistry.cpp ------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "clang/Analysis/Scalable/Serialization/SerializationFormatRegistry.h" +#include + +using namespace clang; +using namespace ssaf; + +// FIXME: LLVM_INSTANTIATE_REGISTRY can't be used here because it drops extra +// type parameters. +template class CLANG_EXPORT_TEMPLATE + llvm::Registry>; + +bool ssaf::isFormatRegistered(llvm::StringRef FormatName) { + for (const auto &Entry : SerializationFormatRegistry::entries()) + if (Entry.getName() == FormatName) + return true; + return false; +} + +std::unique_ptr +ssaf::makeFormat(llvm::IntrusiveRefCntPtr FS, + llvm::StringRef FormatName) { + for (const auto &Entry : SerializationFormatRegistry::entries()) + if (Entry.getName() == FormatName) + return Entry.instantiate(std::move(FS)); + assert(false && "Unknown SerializationFormat name"); + return nullptr; +} diff --git a/clang/lib/Analysis/ThreadSafety.cpp b/clang/lib/Analysis/ThreadSafety.cpp index df4bae89f62df..4ed3ef1993eda 100644 --- a/clang/lib/Analysis/ThreadSafety.cpp +++ b/clang/lib/Analysis/ThreadSafety.cpp @@ -726,11 +726,12 @@ void VarMapBuilder::VisitCallExpr(const CallExpr *CE) { } } - if (VDec && Ctx.lookup(VDec)) { + if (VDec) Ctx = VMap->clearDefinition(VDec, Ctx); - VMap->saveContext(CE, Ctx); - } } + // Save the context after the call where escaped variables' definitions (if + // they exist) are cleared. + VMap->saveContext(CE, Ctx); } // Computes the intersection of two contexts. The intersection is the diff --git a/clang/lib/Analysis/ThreadSafetyCommon.cpp b/clang/lib/Analysis/ThreadSafetyCommon.cpp index 5bee86470ed7f..8180265cc5ed0 100644 --- a/clang/lib/Analysis/ThreadSafetyCommon.cpp +++ b/clang/lib/Analysis/ThreadSafetyCommon.cpp @@ -337,15 +337,29 @@ til::SExpr *SExprBuilder::translate(const Stmt *S, CallingContext *Ctx) { // Collect all literals case Stmt::CharacterLiteralClass: + return new (Arena) + til::LiteralT(cast(S)->getValue()); case Stmt::CXXNullPtrLiteralExprClass: case Stmt::GNUNullExprClass: + return new (Arena) til::LiteralT(nullptr); case Stmt::CXXBoolLiteralExprClass: - case Stmt::FloatingLiteralClass: - case Stmt::ImaginaryLiteralClass: - case Stmt::IntegerLiteralClass: + return new (Arena) til::LiteralT(cast(S)->getValue()); + case Stmt::IntegerLiteralClass: { + const auto *IL = cast(S); + const auto *BT = cast(IL->getType()); + const llvm::APInt &Value = IL->getValue(); + if (BT->isSignedInteger()) + return new (Arena) til::LiteralT(Value.getSExtValue()); + else if (BT->isUnsignedInteger()) + return new (Arena) til::LiteralT(Value.getZExtValue()); + else + llvm_unreachable("Invalid integer type"); + } case Stmt::StringLiteralClass: + return new (Arena) til::LiteralT(cast(S)->getString()); case Stmt::ObjCStringLiteralClass: - return new (Arena) til::Literal(cast(S)); + return new (Arena) + til::LiteralT(cast(S)->getString()->getString()); case Stmt::DeclStmtClass: return translateDeclStmt(cast(S), Ctx); diff --git a/clang/lib/Analysis/UnsafeBufferUsage.cpp b/clang/lib/Analysis/UnsafeBufferUsage.cpp index 761aedda7eacf..193851cc5f381 100644 --- a/clang/lib/Analysis/UnsafeBufferUsage.cpp +++ b/clang/lib/Analysis/UnsafeBufferUsage.cpp @@ -458,6 +458,46 @@ static bool areEqualIntegers(const Expr *E1, const Expr *E2, ASTContext &Ctx) { } } +// Given an expression like `&X` or `std::addressof(X)`, returns the `Expr` +// corresponding to `X` (after removing parens and implicit casts). +// Returns null if the input expression `E` is not an address-of expression. +static const Expr *getSubExprInAddressOfExpr(const Expr &E) { + if (!E.getType()->isPointerType()) + return nullptr; + const Expr *Ptr = E.IgnoreParenImpCasts(); + + // `&X` where `X` is an `Expr`. + if (const auto *UO = dyn_cast(Ptr)) { + if (UO->getOpcode() != UnaryOperator::Opcode::UO_AddrOf) + return nullptr; + return UO->getSubExpr()->IgnoreParenImpCasts(); + } + + // `std::addressof(X)` where `X` is an `Expr`. + if (const auto *CE = dyn_cast(Ptr)) { + const FunctionDecl *FnDecl = CE->getDirectCallee(); + if (!FnDecl || !FnDecl->isInStdNamespace() || + FnDecl->getNameAsString() != "addressof" || CE->getNumArgs() != 1) + return nullptr; + return CE->getArg(0)->IgnoreParenImpCasts(); + } + + return nullptr; +} + +// Given an expression like `sizeof(X)`, returns the `Expr` corresponding to `X` +// (after removing parens and implicit casts). Returns null if the expression +// `E` is not a `sizeof` expression or is `sizeof(T)` for a type `T`. +static const Expr *getSubExprInSizeOfExpr(const Expr &E) { + const auto *SizeOfExpr = + dyn_cast(E.IgnoreParenImpCasts()); + if (!SizeOfExpr || SizeOfExpr->getKind() != UETT_SizeOf) + return nullptr; + if (SizeOfExpr->isArgumentType()) + return nullptr; + return SizeOfExpr->getArgumentExpr()->IgnoreParenImpCasts(); +} + // Providing that `Ptr` is a pointer and `Size` is an unsigned-integral // expression, returns true iff they follow one of the following safe // patterns: @@ -530,21 +570,14 @@ static bool isPtrBufferSafe(const Expr *Ptr, const Expr *Size, } // Pattern 3: - if (ER.Val.getInt().isOne()) { - if (auto *UO = dyn_cast(Ptr->IgnoreParenImpCasts())) - return UO && UO->getOpcode() == UnaryOperator::Opcode::UO_AddrOf; - if (auto *CE = dyn_cast(Ptr->IgnoreParenImpCasts())) { - auto *FnDecl = CE->getDirectCallee(); - - return FnDecl && FnDecl->getNameAsString() == "addressof" && - FnDecl->isInStdNamespace(); - } - return false; - } + if (ER.Val.getInt().isOne() && getSubExprInAddressOfExpr(*Ptr) != nullptr) + return true; + // Pattern 4: if (ER.Val.getInt().isZero()) return true; } + return false; } @@ -800,54 +833,13 @@ static bool isNullTermPointer(const Expr *Ptr, ASTContext &Ctx) { return false; } -// Given an expression like `&X` or `std::addressof(X)`, returns the `Expr` -// corresponding to `X` (after removing parens and implicit casts). -// Returns null if the input expression `E` is not an address-of expression. -static const Expr *getSubExprInAddressOfExpr(const Expr *E) { - if (!E->getType()->isPointerType()) - return nullptr; - const Expr *Ptr = E->IgnoreParenImpCasts(); - - // `&X` where `X` is an `Expr`. - if (const auto *UO = dyn_cast(Ptr)) { - if (UO->getOpcode() != UnaryOperator::Opcode::UO_AddrOf) - return nullptr; - return UO->getSubExpr()->IgnoreParenImpCasts(); - } - - // `std::addressof(X)` where `X` is an `Expr`. - if (const auto *CE = dyn_cast(Ptr)) { - const FunctionDecl *FnDecl = CE->getDirectCallee(); - if (!FnDecl || !FnDecl->isInStdNamespace() || - FnDecl->getNameAsString() != "addressof" || CE->getNumArgs() != 1) - return nullptr; - return CE->getArg(0)->IgnoreParenImpCasts(); - } - - return nullptr; -} - -// Given an expression like `sizeof(X)`, returns the `Expr` corresponding to `X` -// (after removing parens and implicit casts). Returns null if the expression -// `E` is not a `sizeof` expression or is `sizeof(T)` for a type `T`. -static const Expr *getSubExprInSizeOfExpr(const Expr *E) { - const auto *SizeOfExpr = - dyn_cast(E->IgnoreParenImpCasts()); - if (!SizeOfExpr || SizeOfExpr->getKind() != UETT_SizeOf) - return nullptr; - if (SizeOfExpr->isArgumentType()) - return nullptr; - return SizeOfExpr->getArgumentExpr()->IgnoreParenImpCasts(); -} - -namespace libc_func_matchers { // Under `libc_func_matchers`, define a set of matchers that match unsafe // functions in libc and unsafe calls to them. - +namespace libc_func_matchers { // A tiny parser to strip off common prefix and suffix of libc function names // in real code. // -// Given a function name, `matchName` returns `CoreName` according to the +// Given a function name, `matchName()` returns `CoreName` according to the // following grammar: // // LibcName := CoreName | CoreName + "_s" @@ -855,35 +847,33 @@ namespace libc_func_matchers { // "__builtin___" + LibcName + "_chk" | // "__asan_" + LibcName // -struct LibcFunNamePrefixSuffixParser { - StringRef matchName(StringRef FunName, bool isBuiltin) { - // Try to match __builtin_: - if (isBuiltin && FunName.starts_with("__builtin_")) - // Then either it is __builtin_LibcName or __builtin___LibcName_chk or - // no match: - return matchLibcNameOrBuiltinChk( - FunName.drop_front(10 /* truncate "__builtin_" */)); - // Try to match __asan_: - if (FunName.starts_with("__asan_")) - return matchLibcName(FunName.drop_front(7 /* truncate of "__asan_" */)); - return matchLibcName(FunName); - } - - // Parameter `Name` is the substring after stripping off the prefix - // "__builtin_". - StringRef matchLibcNameOrBuiltinChk(StringRef Name) { - if (Name.starts_with("__") && Name.ends_with("_chk")) - return matchLibcName( - Name.drop_front(2).drop_back(4) /* truncate "__" and "_chk" */); - return matchLibcName(Name); - } - - StringRef matchLibcName(StringRef Name) { - if (Name.ends_with("_s")) - return Name.drop_back(2 /* truncate "_s" */); - return Name; - } -}; +static StringRef matchLibcName(StringRef Name) { + if (Name.ends_with("_s")) + return Name.drop_back(2 /* truncate "_s" */); + return Name; +} + +// Parameter `Name` is the substring after stripping off the prefix +// "__builtin_". +static StringRef matchLibcNameOrBuiltinChk(StringRef Name) { + if (Name.starts_with("__") && Name.ends_with("_chk")) + return matchLibcName( + Name.drop_front(2).drop_back(4) /* truncate "__" and "_chk" */); + return matchLibcName(Name); +} + +static StringRef matchName(StringRef FunName, bool isBuiltin) { + // Try to match __builtin_: + if (isBuiltin && FunName.starts_with("__builtin_")) + // Then either it is __builtin_LibcName or __builtin___LibcName_chk or no + // match: + return matchLibcNameOrBuiltinChk( + FunName.drop_front(10 /* truncate "__builtin_" */)); + // Try to match __asan_: + if (FunName.starts_with("__asan_")) + return matchLibcName(FunName.drop_front(7 /* truncate of "__asan_" */)); + return matchLibcName(FunName); +} // Return true iff at least one of following cases holds: // 1. Format string is a literal and there is an unsafe pointer argument @@ -1038,7 +1028,7 @@ hasUnsafeFormatOrSArg(ASTContext &Ctx, const CallExpr *Call, // 2. `CoreName` or `CoreName[str/wcs]` is one of the `PredefinedNames`, which // is a set of libc function names. // -// Note: For predefined prefix and suffix, see `LibcFunNamePrefixSuffixParser`. +// Note: For predefined prefix and suffix, see `matchName()`. // The notation `CoreName[str/wcs]` means a new name obtained from replace // string "wcs" with "str" in `CoreName`. static bool isPredefinedUnsafeLibcFunc(const FunctionDecl &Node) { @@ -1121,8 +1111,7 @@ static bool isPredefinedUnsafeLibcFunc(const FunctionDecl &Node) { if (!II) return false; - StringRef Name = LibcFunNamePrefixSuffixParser().matchName( - II->getName(), Node.getBuiltinID()); + StringRef Name = matchName(II->getName(), Node.getBuiltinID()); // Match predefined names: if (PredefinedNames->find(Name) != PredefinedNames->end()) @@ -1155,8 +1144,7 @@ static bool isUnsafeMemset(const CallExpr &Node, ASTContext &Ctx) { if (!II) return false; - StringRef Name = LibcFunNamePrefixSuffixParser().matchName( - II->getName(), FD->getBuiltinID()); + StringRef Name = matchName(II->getName(), FD->getBuiltinID()); if (Name != "memset") return false; @@ -1170,12 +1158,12 @@ static bool isUnsafeMemset(const CallExpr &Node, ASTContext &Ctx) { // Now we have a known version of `memset`, consider it unsafe unless it's in // the form `memset(&x, 0, sizeof(x))`. const auto *AddressOfVar = dyn_cast_if_present( - getSubExprInAddressOfExpr(Node.getArg(0))); + getSubExprInAddressOfExpr(*Node.getArg(0))); if (!AddressOfVar) return true; const auto *SizeOfVar = - dyn_cast_if_present(getSubExprInSizeOfExpr(Node.getArg(2))); + dyn_cast_if_present(getSubExprInSizeOfExpr(*Node.getArg(2))); if (!SizeOfVar) return true; @@ -1191,12 +1179,9 @@ static bool isUnsafeVaListPrintfFunc(const FunctionDecl &Node) { if (!II) return false; - StringRef Name = LibcFunNamePrefixSuffixParser().matchName( - II->getName(), Node.getBuiltinID()); + StringRef Name = matchName(II->getName(), Node.getBuiltinID()); - if (!Name.ends_with("printf")) - return false; // neither printf nor scanf - return Name.starts_with("v"); + return Name.starts_with("v") && Name.ends_with("printf"); } // Matches a call to one of the `sprintf` functions as they are always unsafe @@ -1207,19 +1192,9 @@ static bool isUnsafeSprintfFunc(const FunctionDecl &Node) { if (!II) return false; - StringRef Name = LibcFunNamePrefixSuffixParser().matchName( - II->getName(), Node.getBuiltinID()); - - if (!Name.ends_with("printf") || - // Let `isUnsafeVaListPrintfFunc` check for cases with va-list: - Name.starts_with("v")) - return false; + StringRef Name = matchName(II->getName(), Node.getBuiltinID()); - StringRef Prefix = Name.drop_back(6); - - if (Prefix.ends_with("w")) - Prefix = Prefix.drop_back(1); - return Prefix == "s"; + return Name == "sprintf" || Name == "swprintf"; } // Match function declarations of `printf`, `fprintf`, `snprintf` and their wide @@ -1231,10 +1206,9 @@ static bool isNormalPrintfFunc(const FunctionDecl &Node) { if (!II) return false; - StringRef Name = LibcFunNamePrefixSuffixParser().matchName( - II->getName(), Node.getBuiltinID()); + StringRef Name = matchName(II->getName(), Node.getBuiltinID()); - if (!Name.ends_with("printf") || Name.starts_with("v")) + if (!Name.ends_with("printf")) return false; StringRef Prefix = Name.drop_back(6); diff --git a/clang/lib/Basic/OffloadArch.cpp b/clang/lib/Basic/OffloadArch.cpp index e1f9641383ce1..7da3feea7b51c 100644 --- a/clang/lib/Basic/OffloadArch.cpp +++ b/clang/lib/Basic/OffloadArch.cpp @@ -90,6 +90,7 @@ static const OffloadArchToStringMap ArchNames[] = { GFX(1151), // gfx1151 GFX(1152), // gfx1152 GFX(1153), // gfx1153 + GFX(1170), // gfx1170 {OffloadArch::GFX12_GENERIC, "gfx12-generic", "compute_amdgcn"}, GFX(1200), // gfx1200 GFX(1201), // gfx1201 diff --git a/clang/lib/Basic/OperatorPrecedence.cpp b/clang/lib/Basic/OperatorPrecedence.cpp index c4e8fe96cdf4b..f328d1efa2f87 100644 --- a/clang/lib/Basic/OperatorPrecedence.cpp +++ b/clang/lib/Basic/OperatorPrecedence.cpp @@ -54,6 +54,10 @@ prec::Level getBinOpPrecedence(tok::TokenKind Kind, bool GreaterThanIsOperator, case tok::pipepipe: return prec::LogicalOr; case tok::ampamp: return prec::LogicalAnd; case tok::pipe: return prec::InclusiveOr; + // this is for the case when ^^ appears where a binary operator is needed, + // and the first ^ is the actual binary operator, + // and the second is for a block. + case tok::caretcaret: case tok::caret: return prec::ExclusiveOr; case tok::amp: return prec::And; case tok::exclaimequal: diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index 263253918d965..cd5b29db07a9f 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -432,6 +432,7 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, return std::make_unique(Triple, Opts); case llvm::Triple::riscv32: + case llvm::Triple::riscv32be: switch (os) { case llvm::Triple::NetBSD: return std::make_unique>(Triple, @@ -443,6 +444,7 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, } case llvm::Triple::riscv64: + case llvm::Triple::riscv64be: switch (os) { case llvm::Triple::FreeBSD: return std::make_unique>(Triple, @@ -680,13 +682,13 @@ std::unique_ptr AllocateTarget(const llvm::Triple &Triple, return std::make_unique(Triple, Opts); } case llvm::Triple::spirv32: { - if (os != llvm::Triple::UnknownOS || + if ((os != llvm::Triple::UnknownOS && os != llvm::Triple::ChipStar) || Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) return nullptr; return std::make_unique(Triple, Opts); } case llvm::Triple::spirv64: { - if (os != llvm::Triple::UnknownOS || + if ((os != llvm::Triple::UnknownOS && os != llvm::Triple::ChipStar) || Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) { if (os == llvm::Triple::OSType::AMDHSA) return std::make_unique(Triple, Opts); diff --git a/clang/lib/Basic/Targets/OSTargets.h b/clang/lib/Basic/Targets/OSTargets.h index 04608649a8634..24bc300f3774e 100644 --- a/clang/lib/Basic/Targets/OSTargets.h +++ b/clang/lib/Basic/Targets/OSTargets.h @@ -255,6 +255,7 @@ class LLVM_LIBRARY_VISIBILITY FreeBSDTargetInfo : public OSTargetInfo { break; case llvm::Triple::loongarch64: case llvm::Triple::riscv64: + case llvm::Triple::riscv64be: break; } } @@ -519,6 +520,7 @@ class LLVM_LIBRARY_VISIBILITY OpenBSDTargetInfo : public OSTargetInfo { break; case llvm::Triple::loongarch64: case llvm::Triple::riscv64: + case llvm::Triple::riscv64be: break; } } diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h index ea992b0e01dbe..eef9521c7434a 100644 --- a/clang/lib/Basic/Targets/SPIR.h +++ b/clang/lib/Basic/Targets/SPIR.h @@ -362,8 +362,9 @@ class LLVM_LIBRARY_VISIBILITY SPIRV32TargetInfo : public BaseSPIRVTargetInfo { : BaseSPIRVTargetInfo(Triple, Opts) { assert(Triple.getArch() == llvm::Triple::spirv32 && "Invalid architecture for 32-bit SPIR-V."); - assert(getTriple().getOS() == llvm::Triple::UnknownOS && - "32-bit SPIR-V target must use unknown OS"); + assert((getTriple().getOS() == llvm::Triple::UnknownOS || + getTriple().getOS() == llvm::Triple::ChipStar) && + "32-bit SPIR-V target must use unknown or chipstar OS"); assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && "32-bit SPIR-V target must use unknown environment type"); PointerWidth = PointerAlign = 32; @@ -385,8 +386,9 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public BaseSPIRVTargetInfo { : BaseSPIRVTargetInfo(Triple, Opts) { assert(Triple.getArch() == llvm::Triple::spirv64 && "Invalid architecture for 64-bit SPIR-V."); - assert(getTriple().getOS() == llvm::Triple::UnknownOS && - "64-bit SPIR-V target must use unknown OS"); + assert((getTriple().getOS() == llvm::Triple::UnknownOS || + getTriple().getOS() == llvm::Triple::ChipStar) && + "64-bit SPIR-V target must use unknown or chipstar OS"); assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && "64-bit SPIR-V target must use unknown environment type"); PointerWidth = PointerAlign = 64; diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 896a27a2c4458..6f88a428b1230 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -721,6 +721,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_ZNVER5: defineCPUMacros(Builder, "znver5"); break; + case CK_ZNVER6: + defineCPUMacros(Builder, "znver6"); + break; case CK_Geode: defineCPUMacros(Builder, "geode"); break; @@ -1647,6 +1650,7 @@ std::optional X86TargetInfo::getCPUCacheLineSize() const { case CK_ZNVER3: case CK_ZNVER4: case CK_ZNVER5: + case CK_ZNVER6: // Deprecated case CK_x86_64: case CK_x86_64_v2: diff --git a/clang/lib/CIR/CodeGen/CIRGenAtomic.cpp b/clang/lib/CIR/CodeGen/CIRGenAtomic.cpp index 963f99a3276a9..a78b15511dd82 100644 --- a/clang/lib/CIR/CodeGen/CIRGenAtomic.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenAtomic.cpp @@ -470,6 +470,8 @@ static void emitAtomicOp(CIRGenFunction &cgf, AtomicExpr *expr, Address dest, case AtomicExpr::AO__c11_atomic_exchange: case AtomicExpr::AO__atomic_exchange_n: case AtomicExpr::AO__atomic_exchange: + case AtomicExpr::AO__scoped_atomic_exchange_n: + case AtomicExpr::AO__scoped_atomic_exchange: opName = cir::AtomicXchgOp::getOperationName(); break; @@ -589,8 +591,6 @@ static void emitAtomicOp(CIRGenFunction &cgf, AtomicExpr *expr, Address dest, case AtomicExpr::AO__hip_atomic_exchange: case AtomicExpr::AO__opencl_atomic_exchange: - case AtomicExpr::AO__scoped_atomic_exchange_n: - case AtomicExpr::AO__scoped_atomic_exchange: case AtomicExpr::AO__scoped_atomic_add_fetch: @@ -657,6 +657,7 @@ static void emitAtomicOp(CIRGenFunction &cgf, AtomicExpr *expr, Address dest, if (fetchAttr) rmwOp->setAttr("binop", fetchAttr); rmwOp->setAttr("mem_order", orderAttr); + rmwOp->setAttr("sync_scope", scopeAttr); if (expr->isVolatile()) rmwOp->setAttr("is_volatile", builder.getUnitAttr()); if (fetchFirst && opName == cir::AtomicFetchOp::getOperationName()) @@ -885,6 +886,7 @@ RValue CIRGenFunction::emitAtomicExpr(AtomicExpr *e) { break; case AtomicExpr::AO__atomic_exchange: + case AtomicExpr::AO__scoped_atomic_exchange: val1 = emitPointerWithAlignment(e->getVal1()); dest = emitPointerWithAlignment(e->getVal2()); break; @@ -945,6 +947,7 @@ RValue CIRGenFunction::emitAtomicExpr(AtomicExpr *e) { case AtomicExpr::AO__c11_atomic_exchange: case AtomicExpr::AO__c11_atomic_store: case AtomicExpr::AO__scoped_atomic_store_n: + case AtomicExpr::AO__scoped_atomic_exchange_n: val1 = emitValToTemp(*this, e->getVal1()); break; } diff --git a/clang/lib/CIR/CodeGen/CIRGenBuilder.h b/clang/lib/CIR/CodeGen/CIRGenBuilder.h index dedb369bf3f67..99a8152e7d365 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuilder.h +++ b/clang/lib/CIR/CodeGen/CIRGenBuilder.h @@ -197,6 +197,12 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy { mlir::Value src, mlir::Value len) { return cir::MemCpyOp::create(*this, loc, dst, src, len); } + + cir::MemSetOp createMemSet(mlir::Location loc, mlir::Value dst, + mlir::Value val, mlir::Value len) { + assert(val.getType() == getUInt8Ty()); + return cir::MemSetOp::create(*this, loc, dst, val, len); + } // --------------------------- cir::DataMemberAttr getDataMemberAttr(cir::DataMemberType ty, diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp index 580ada8901cbb..5e6c9e8e2490e 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp @@ -1901,7 +1901,11 @@ emitTargetArchBuiltinExpr(CIRGenFunction *cgf, unsigned builtinID, case llvm::Triple::ppc64: case llvm::Triple::ppc64le: case llvm::Triple::r600: + // These are actually NYI, but that will be reported by emitBuiltinExpr. + // At this point, we don't even know that the builtin is target-specific. + return std::nullopt; case llvm::Triple::amdgcn: + return cgf->emitAMDGPUBuiltinExpr(builtinID, e); case llvm::Triple::systemz: case llvm::Triple::nvptx: case llvm::Triple::nvptx64: @@ -2033,8 +2037,9 @@ mlir::Value CIRGenFunction::emitBuiltinObjectSize(const Expr *e, unsigned type, mlir::Value CIRGenFunction::evaluateOrEmitBuiltinObjectSize( const Expr *e, unsigned type, cir::IntType resType, mlir::Value emittedE, bool isDynamic) { - uint64_t objectSize; - if (!e->tryEvaluateObjectSize(objectSize, getContext(), type)) - return emitBuiltinObjectSize(e, type, resType, emittedE, isDynamic); - return builder.getConstInt(getLoc(e->getSourceRange()), resType, objectSize); + if (std::optional objectSize = + e->tryEvaluateObjectSize(getContext(), type)) + return builder.getConstInt(getLoc(e->getSourceRange()), resType, + *objectSize); + return emitBuiltinObjectSize(e, type, resType, emittedE, isDynamic); } diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index a8ede132f4eca..f51673cd92f5e 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -115,6 +115,85 @@ bool CIRGenFunction::getAArch64SVEProcessedOperands( return true; } +static llvm::StringRef getLLVMIntrNameNoPrefix(llvm::Intrinsic::ID intrID) { + llvm::StringRef llvmIntrName = llvm::Intrinsic::getBaseName(intrID); + assert(llvmIntrName.starts_with("llvm.") && "Not an LLVM intrinsic!"); + return llvmIntrName.drop_front(/*strlen("llvm.")=*/5); +} + +// Reinterpret the input predicate so that it can be used to correctly isolate +// the elements of the specified datatype. +mlir::Value CIRGenFunction::emitSVEPredicateCast(mlir::Value pred, + unsigned minNumElts, + mlir::Location loc) { + + // TODO: Handle "aarch64.svcount" once we get round to supporting SME. + + auto retTy = cir::VectorType::get(builder.getUIntNTy(1), minNumElts, + /*is_scalable=*/true); + if (pred.getType() == retTy) + return pred; + + llvm::Intrinsic::ID intID; + switch (minNumElts) { + default: + llvm_unreachable("unsupported element count!"); + case 1: + case 2: + case 4: + case 8: + intID = Intrinsic::aarch64_sve_convert_from_svbool; + break; + case 16: + intID = Intrinsic::aarch64_sve_convert_to_svbool; + break; + } + + llvm::StringRef llvmIntrName = getLLVMIntrNameNoPrefix(intID); + auto call = builder.emitIntrinsicCallOp(loc, llvmIntrName, retTy, + mlir::ValueRange{pred}); + assert(call.getType() == retTy && "Unexpected return type!"); + return call; +} + +// Get the minimum number of elements in an SVE vector for the given element +// type. The actual number of elements in the vector would be an integer (power +// of two) multiple of this value. +static unsigned getSVEMinEltCount(clang::SVETypeFlags::EltType sveType) { + switch (sveType) { + default: + llvm_unreachable("Invalid SVETypeFlag!"); + + case SVETypeFlags::EltTyInt8: + return 16; + case SVETypeFlags::EltTyInt16: + return 8; + case SVETypeFlags::EltTyInt32: + return 4; + case SVETypeFlags::EltTyInt64: + return 2; + + case SVETypeFlags::EltTyMFloat8: + return 16; + case SVETypeFlags::EltTyFloat16: + case SVETypeFlags::EltTyBFloat16: + return 8; + case SVETypeFlags::EltTyFloat32: + return 4; + case SVETypeFlags::EltTyFloat64: + return 2; + + case SVETypeFlags::EltTyBool8: + return 16; + case SVETypeFlags::EltTyBool16: + return 8; + case SVETypeFlags::EltTyBool32: + return 4; + case SVETypeFlags::EltTyBool64: + return 2; + } +} + std::optional CIRGenFunction::emitAArch64SVEBuiltinExpr(unsigned builtinID, const CallExpr *expr) { @@ -160,10 +239,12 @@ CIRGenFunction::emitAArch64SVEBuiltinExpr(unsigned builtinID, std::string("unimplemented AArch64 builtin call: ") + getContext().BuiltinInfo.getName(builtinID)); - if (typeFlags.getMergeType() == SVETypeFlags::MergeZeroExp) - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented AArch64 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); + // Zero-ing predication + if (typeFlags.getMergeType() == SVETypeFlags::MergeZeroExp) { + auto null = builder.getNullValue(convertType(expr->getType()), + getLoc(expr->getExprLoc())); + ops.insert(ops.begin(), null); + } if (typeFlags.getMergeType() == SVETypeFlags::MergeAnyExp) cgm.errorNYI(expr->getSourceRange(), @@ -183,11 +264,11 @@ CIRGenFunction::emitAArch64SVEBuiltinExpr(unsigned builtinID, // Predicates must match the main datatype. for (mlir::Value &op : ops) - if (auto predTy = dyn_cast(op.getType())) - if (predTy.getElementType().isInteger(1)) - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented AArch64 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); + if (auto predTy = dyn_cast(op.getType())) + if (auto cirInt = dyn_cast(predTy.getElementType())) + if (cirInt.getWidth() == 1) + op = emitSVEPredicateCast( + op, getSVEMinEltCount(typeFlags.getEltType()), loc); // Splat scalar operand to vector (intrinsics with _n infix) if (typeFlags.hasSplatOperand()) { @@ -222,11 +303,8 @@ CIRGenFunction::emitAArch64SVEBuiltinExpr(unsigned builtinID, getContext().BuiltinInfo.getName(builtinID)); } - std::string llvmIntrName(Intrinsic::getBaseName( - (llvm::Intrinsic::ID)builtinIntrInfo->llvmIntrinsic)); - - llvmIntrName.erase(0, /*std::strlen(".llvm")=*/5); - + llvm::StringRef llvmIntrName = getLLVMIntrNameNoPrefix( + static_cast(builtinIntrInfo->llvmIntrinsic)); auto retTy = convertType(expr->getType()); auto call = builder.emitIntrinsicCallOp(loc, llvmIntrName, retTy, diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp new file mode 100644 index 0000000000000..b4b0c455904fc --- /dev/null +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp @@ -0,0 +1,828 @@ +//===---- CIRGenBuiltinAMDGPU.cpp - Emit CIR for AMDGPU builtins ----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This contains code to emit AMDGPU Builtin calls. +// +//===----------------------------------------------------------------------===// + +#include "CIRGenFunction.h" + +#include "mlir/IR/Value.h" +#include "clang/Basic/TargetBuiltins.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace clang; +using namespace clang::CIRGen; + +std::optional +CIRGenFunction::emitAMDGPUBuiltinExpr(unsigned builtinId, + const CallExpr *expr) { + switch (builtinId) { + case AMDGPU::BI__builtin_amdgcn_wave_reduce_add_u32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_sub_u32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_min_i32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_min_u32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_max_i32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_max_u32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_and_b32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_or_b32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_xor_b32: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_add_u64: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_sub_u64: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_min_i64: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_min_u64: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_max_i64: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_max_u64: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_and_b64: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_or_b64: + case AMDGPU::BI__builtin_amdgcn_wave_reduce_xor_b64: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_div_scale: + case AMDGPU::BI__builtin_amdgcn_div_scalef: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_div_fmas: + case AMDGPU::BI__builtin_amdgcn_div_fmasf: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_ds_swizzle: + case AMDGPU::BI__builtin_amdgcn_mov_dpp8: + case AMDGPU::BI__builtin_amdgcn_mov_dpp: + case AMDGPU::BI__builtin_amdgcn_update_dpp: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_permlane16: + case AMDGPU::BI__builtin_amdgcn_permlanex16: + case AMDGPU::BI__builtin_amdgcn_permlane64: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_readlane: + case AMDGPU::BI__builtin_amdgcn_readfirstlane: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_div_fixup: + case AMDGPU::BI__builtin_amdgcn_div_fixupf: + case AMDGPU::BI__builtin_amdgcn_div_fixuph: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_trig_preop: + case AMDGPU::BI__builtin_amdgcn_trig_preopf: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_rcp: + case AMDGPU::BI__builtin_amdgcn_rcpf: + case AMDGPU::BI__builtin_amdgcn_rcph: + case AMDGPU::BI__builtin_amdgcn_rcp_bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_sqrt: + case AMDGPU::BI__builtin_amdgcn_sqrtf: + case AMDGPU::BI__builtin_amdgcn_sqrth: + case AMDGPU::BI__builtin_amdgcn_sqrt_bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_rsq: + case AMDGPU::BI__builtin_amdgcn_rsqf: + case AMDGPU::BI__builtin_amdgcn_rsqh: + case AMDGPU::BI__builtin_amdgcn_rsq_bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_rsq_clamp: + case AMDGPU::BI__builtin_amdgcn_rsq_clampf: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_sinf: + case AMDGPU::BI__builtin_amdgcn_sinh: + case AMDGPU::BI__builtin_amdgcn_sin_bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_cosf: + case AMDGPU::BI__builtin_amdgcn_cosh: + case AMDGPU::BI__builtin_amdgcn_cos_bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_dispatch_ptr: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_logf: + case AMDGPU::BI__builtin_amdgcn_log_bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_exp2f: + case AMDGPU::BI__builtin_amdgcn_exp2_bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_log_clampf: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_ldexp: + case AMDGPU::BI__builtin_amdgcn_ldexpf: + case AMDGPU::BI__builtin_amdgcn_ldexph: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_frexp_mant: + case AMDGPU::BI__builtin_amdgcn_frexp_mantf: + case AMDGPU::BI__builtin_amdgcn_frexp_manth: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_frexp_exp: + case AMDGPU::BI__builtin_amdgcn_frexp_expf: + case AMDGPU::BI__builtin_amdgcn_frexp_exph: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_fract: + case AMDGPU::BI__builtin_amdgcn_fractf: + case AMDGPU::BI__builtin_amdgcn_fracth: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_lerp: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_ubfe: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_sbfe: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_ballot_w32: + case AMDGPU::BI__builtin_amdgcn_ballot_w64: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_inverse_ballot_w32: + case AMDGPU::BI__builtin_amdgcn_inverse_ballot_w64: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_tanhf: + case AMDGPU::BI__builtin_amdgcn_tanhh: + case AMDGPU::BI__builtin_amdgcn_tanh_bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_uicmp: + case AMDGPU::BI__builtin_amdgcn_uicmpl: + case AMDGPU::BI__builtin_amdgcn_sicmp: + case AMDGPU::BI__builtin_amdgcn_sicmpl: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_fcmp: + case AMDGPU::BI__builtin_amdgcn_fcmpf: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_class: + case AMDGPU::BI__builtin_amdgcn_classf: + case AMDGPU::BI__builtin_amdgcn_classh: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_fmed3f: + case AMDGPU::BI__builtin_amdgcn_fmed3h: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_ds_append: + case AMDGPU::BI__builtin_amdgcn_ds_consume: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b64_i32: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b64_v2i32: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b128_v4i16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b128_v4f16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b128_v4bf16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b128_v8i16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b128_v8f16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr_b128_v8bf16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr4_b64_v2i32: + case AMDGPU::BI__builtin_amdgcn_global_load_tr8_b64_v2i32: + case AMDGPU::BI__builtin_amdgcn_global_load_tr6_b96_v3i32: + case AMDGPU::BI__builtin_amdgcn_global_load_tr16_b128_v8i16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr16_b128_v8f16: + case AMDGPU::BI__builtin_amdgcn_global_load_tr16_b128_v8bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_ds_load_tr4_b64_v2i32: + case AMDGPU::BI__builtin_amdgcn_ds_load_tr8_b64_v2i32: + case AMDGPU::BI__builtin_amdgcn_ds_load_tr6_b96_v3i32: + case AMDGPU::BI__builtin_amdgcn_ds_load_tr16_b128_v8i16: + case AMDGPU::BI__builtin_amdgcn_ds_load_tr16_b128_v8f16: + case AMDGPU::BI__builtin_amdgcn_ds_load_tr16_b128_v8bf16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_ds_read_tr4_b64_v2i32: + case AMDGPU::BI__builtin_amdgcn_ds_read_tr8_b64_v2i32: + case AMDGPU::BI__builtin_amdgcn_ds_read_tr6_b96_v3i32: + case AMDGPU::BI__builtin_amdgcn_ds_read_tr16_b64_v4f16: + case AMDGPU::BI__builtin_amdgcn_ds_read_tr16_b64_v4bf16: + case AMDGPU::BI__builtin_amdgcn_ds_read_tr16_b64_v4i16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b32: + case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b64: + case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b128: + case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b32: + case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b64: + case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b128: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_cluster_load_b32: + case AMDGPU::BI__builtin_amdgcn_cluster_load_b64: + case AMDGPU::BI__builtin_amdgcn_cluster_load_b128: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_load_to_lds: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_load_32x4B: + case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_32x4B: + case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_load_16x8B: + case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_16x8B: + case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_load_8x16B: + case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_8x16B: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_get_fpenv: + case AMDGPU::BI__builtin_amdgcn_set_fpenv: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_read_exec: + case AMDGPU::BI__builtin_amdgcn_read_exec_lo: + case AMDGPU::BI__builtin_amdgcn_read_exec_hi: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_image_bvh_intersect_ray: + case AMDGPU::BI__builtin_amdgcn_image_bvh_intersect_ray_h: + case AMDGPU::BI__builtin_amdgcn_image_bvh_intersect_ray_l: + case AMDGPU::BI__builtin_amdgcn_image_bvh_intersect_ray_lh: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_image_bvh8_intersect_ray: + case AMDGPU::BI__builtin_amdgcn_image_bvh_dual_intersect_ray: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_rtn: + case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push4_pop1_rtn: + case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push8_pop1_rtn: + case AMDGPU::BI__builtin_amdgcn_ds_bvh_stack_push8_pop2_rtn: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_2d_f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_2d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_2d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_2darray_f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_2darray_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_2darray_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_3d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_3d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_cube_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_cube_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_1d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_1d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_2d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_2d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_2darray_f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_2darray_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_2darray_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_3d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_3d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_cube_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_load_mip_cube_v4f16_i32: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_image_store_1d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_1d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_1darray_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_1darray_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_2d_f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_2d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_2d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_2darray_f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_2darray_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_2darray_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_3d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_3d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_cube_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_cube_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_1d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_1d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_1darray_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_1darray_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_2d_f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_2d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_2d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_2darray_f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_2darray_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_2darray_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_3d_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_3d_v4f16_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_cube_v4f32_i32: + case AMDGPU::BI__builtin_amdgcn_image_store_mip_cube_v4f16_i32: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_image_sample_1d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_1d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_1darray_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_1darray_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_2d_f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_2d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_2d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_2darray_f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_2darray_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_2darray_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_3d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_3d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_cube_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_cube_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_1d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_1d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_1d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_1d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_1d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_1d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2d_f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_2d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_2d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_2d_f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_2d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_2d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_2d_f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_3d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_3d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_3d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_3d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_3d_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_3d_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_cube_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_cube_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_cube_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_cube_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_1darray_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_1darray_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_1darray_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_1darray_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_1darray_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_1darray_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2darray_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2darray_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_lz_2darray_f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_2darray_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_2darray_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_l_2darray_f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_2darray_v4f32_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_2darray_v4f16_f32: + case AMDGPU::BI__builtin_amdgcn_image_sample_d_2darray_f32_f32: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_image_gather4_lz_2d_v4f32_f32: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_mfma_scale_f32_16x16x128_f8f6f4: + case AMDGPU::BI__builtin_amdgcn_mfma_scale_f32_32x32x64_f8f6f4: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_wmma_bf16_16x16x16_bf16_w32: + case AMDGPU::BI__builtin_amdgcn_wmma_bf16_16x16x16_bf16_tied_w32: + case AMDGPU::BI__builtin_amdgcn_wmma_bf16_16x16x16_bf16_w64: + case AMDGPU::BI__builtin_amdgcn_wmma_bf16_16x16x16_bf16_tied_w64: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x16_f16_w32: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x16_f16_tied_w32: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x16_f16_w64: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x16_f16_tied_w64: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_bf16_w32: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_bf16_w64: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_f16_w32: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_f16_w64: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x16_iu4_w32: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x16_iu4_w64: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x16_iu8_w32: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x16_iu8_w64: + case AMDGPU::BI__builtin_amdgcn_wmma_bf16_16x16x16_bf16_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_bf16_16x16x16_bf16_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x16_f16_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x16_f16_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_bf16_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_bf16_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_f16_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_f16_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x16_iu4_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x16_iu4_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x16_iu8_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x16_iu8_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_fp8_fp8_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_fp8_fp8_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_fp8_bf8_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_fp8_bf8_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_bf8_fp8_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_bf8_fp8_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_bf8_bf8_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x16_bf8_bf8_w64_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x32_iu4_w32_gfx12: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x32_iu4_w64_gfx12: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_f16_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_f16_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_bf16_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_bf16_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_f16_16x16x32_f16_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_f16_16x16x32_f16_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_bf16_16x16x32_bf16_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_bf16_16x16x32_bf16_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x32_iu8_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x32_iu8_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x32_iu4_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x32_iu4_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x64_iu4_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x64_iu4_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_fp8_fp8_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_fp8_fp8_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_fp8_bf8_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_fp8_bf8_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_bf8_fp8_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_bf8_fp8_w64: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_bf8_bf8_w32: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x32_bf8_bf8_w64: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x4_f32: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x32_bf16: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x32_f16: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x32_f16: + case AMDGPU::BI__builtin_amdgcn_wmma_bf16_16x16x32_bf16: + case AMDGPU::BI__builtin_amdgcn_wmma_bf16f32_16x16x32_bf16: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x64_fp8_fp8: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x64_fp8_bf8: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x64_bf8_fp8: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x64_bf8_bf8: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x64_fp8_fp8: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x64_fp8_bf8: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x64_bf8_fp8: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x64_bf8_bf8: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x128_fp8_fp8: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x128_fp8_bf8: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x128_bf8_fp8: + case AMDGPU::BI__builtin_amdgcn_wmma_f16_16x16x128_bf8_bf8: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x128_fp8_fp8: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x128_fp8_bf8: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x128_bf8_fp8: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x128_bf8_bf8: + case AMDGPU::BI__builtin_amdgcn_wmma_i32_16x16x64_iu8: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_16x16x128_f8f6f4: + case AMDGPU::BI__builtin_amdgcn_wmma_f32_32x16x128_f4: + case AMDGPU::BI__builtin_amdgcn_wmma_scale_f32_16x16x128_f8f6f4: + case AMDGPU::BI__builtin_amdgcn_wmma_scale16_f32_16x16x128_f8f6f4: + case AMDGPU::BI__builtin_amdgcn_wmma_scale_f32_32x16x128_f4: + case AMDGPU::BI__builtin_amdgcn_wmma_scale16_f32_32x16x128_f4: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x64_f16: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x64_bf16: + case AMDGPU::BI__builtin_amdgcn_swmmac_f16_16x16x64_f16: + case AMDGPU::BI__builtin_amdgcn_swmmac_bf16_16x16x64_bf16: + case AMDGPU::BI__builtin_amdgcn_swmmac_bf16f32_16x16x64_bf16: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x128_fp8_fp8: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x128_fp8_bf8: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x128_bf8_fp8: + case AMDGPU::BI__builtin_amdgcn_swmmac_f32_16x16x128_bf8_bf8: + case AMDGPU::BI__builtin_amdgcn_swmmac_f16_16x16x128_fp8_fp8: + case AMDGPU::BI__builtin_amdgcn_swmmac_f16_16x16x128_fp8_bf8: + case AMDGPU::BI__builtin_amdgcn_swmmac_f16_16x16x128_bf8_fp8: + case AMDGPU::BI__builtin_amdgcn_swmmac_f16_16x16x128_bf8_bf8: + case AMDGPU::BI__builtin_amdgcn_swmmac_i32_16x16x128_iu8: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + // amdgcn workgroup size + case AMDGPU::BI__builtin_amdgcn_workgroup_size_x: + case AMDGPU::BI__builtin_amdgcn_workgroup_size_y: + case AMDGPU::BI__builtin_amdgcn_workgroup_size_z: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_grid_size_x: + case AMDGPU::BI__builtin_amdgcn_grid_size_y: + case AMDGPU::BI__builtin_amdgcn_grid_size_z: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_r600_recipsqrt_ieee: + case AMDGPU::BI__builtin_r600_recipsqrt_ieeef: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_alignbit: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_fence: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_atomic_inc32: + case AMDGPU::BI__builtin_amdgcn_atomic_inc64: + case AMDGPU::BI__builtin_amdgcn_atomic_dec32: + case AMDGPU::BI__builtin_amdgcn_atomic_dec64: + case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_f64: + case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_f32: + case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_v2f16: + case AMDGPU::BI__builtin_amdgcn_ds_atomic_fadd_v2bf16: + case AMDGPU::BI__builtin_amdgcn_ds_faddf: + case AMDGPU::BI__builtin_amdgcn_ds_fminf: + case AMDGPU::BI__builtin_amdgcn_ds_fmaxf: + case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f32: + case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_f64: + case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2f16: + case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2f16: + case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f32: + case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_f64: + case AMDGPU::BI__builtin_amdgcn_global_atomic_fadd_v2bf16: + case AMDGPU::BI__builtin_amdgcn_flat_atomic_fadd_v2bf16: + case AMDGPU::BI__builtin_amdgcn_global_atomic_fmin_f64: + case AMDGPU::BI__builtin_amdgcn_global_atomic_fmax_f64: + case AMDGPU::BI__builtin_amdgcn_flat_atomic_fmin_f64: + case AMDGPU::BI__builtin_amdgcn_flat_atomic_fmax_f64: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_s_sendmsg_rtn: + case AMDGPU::BI__builtin_amdgcn_s_sendmsg_rtnl: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_permlane16_swap: + case AMDGPU::BI__builtin_amdgcn_permlane32_swap: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_bitop3_b32: + case AMDGPU::BI__builtin_amdgcn_bitop3_b16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_make_buffer_rsrc: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b8: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b16: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b32: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b64: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b96: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_store_b128: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b8: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b16: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b32: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b64: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b96: + case AMDGPU::BI__builtin_amdgcn_raw_buffer_load_b128: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_add_i32: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fadd_f32: + case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fadd_v2f16: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmin_f32: + case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmin_f64: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f32: + case AMDGPU::BI__builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f64: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case AMDGPU::BI__builtin_amdgcn_s_prefetch_data: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case Builtin::BIlogbf: + case Builtin::BI__builtin_logbf: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + case Builtin::BIscalbnf: + case Builtin::BI__builtin_scalbnf: + case Builtin::BIscalbn: + case Builtin::BI__builtin_scalbn: { + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AMDGPU builtin call: ") + + getContext().BuiltinInfo.getName(builtinId)); + return mlir::Value{}; + } + default: + return std::nullopt; + } +} diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 80022998448ad..cad80317cb870 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -186,6 +186,32 @@ static mlir::Value emitX86CompressExpand(CIRGenBuilderTy &builder, mlir::ValueRange{source, mask, maskValue}); } +static mlir::Value +emitEncodeKey(mlir::MLIRContext *context, CIRGenBuilderTy &builder, + const mlir::Location &location, mlir::ValueRange inputOperands, + mlir::Value outputOperand, std::uint8_t vecOutputCount, + const std::string &intrinsicName, std::uint8_t numResults) { + cir::VectorType resVector = cir::VectorType::get(builder.getUInt64Ty(), 2); + llvm::SmallVector members{builder.getUInt32Ty()}; + llvm::append_range(members, + llvm::SmallVector(vecOutputCount, resVector)); + cir::RecordType resRecord = cir::RecordType::get( + context, members, false, false, cir::RecordType::RecordKind::Struct); + + mlir::Value outputPtr = + builder.createBitcast(outputOperand, cir::PointerType::get(resVector)); + mlir::Value call = builder.emitIntrinsicCallOp(location, intrinsicName, + resRecord, inputOperands); + for (std::uint8_t i = 0; i < numResults; ++i) { + mlir::Value vecValue = + cir::ExtractMemberOp::create(builder, location, call, i + 1); + mlir::Value index = builder.getSInt32(i, location); + mlir::Value ptr = builder.createPtrStride(location, outputPtr, index); + builder.createStore(location, vecValue, Address{ptr, CharUnits::One()}); + } + return cir::ExtractMemberOp::create(builder, location, call, 0); +} + static mlir::Value emitX86Select(CIRGenBuilderTy &builder, mlir::Location loc, mlir::Value mask, mlir::Value op0, mlir::Value op1) { @@ -2402,14 +2428,23 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { case X86::BI__readgsbyte: case X86::BI__readgsword: case X86::BI__readgsdword: - case X86::BI__readgsqword: - case X86::BI__builtin_ia32_encodekey128_u32: - case X86::BI__builtin_ia32_encodekey256_u32: { + case X86::BI__readgsqword: { cgm.errorNYI(expr->getSourceRange(), std::string("unimplemented X86 builtin call: ") + getContext().BuiltinInfo.getName(builtinID)); return mlir::Value{}; } + case X86::BI__builtin_ia32_encodekey128_u32: { + return emitEncodeKey(&getMLIRContext(), builder, getLoc(expr->getExprLoc()), + {ops[0], ops[1]}, ops[2], 6, "x86.encodekey128", 3); + } + case X86::BI__builtin_ia32_encodekey256_u32: { + + return emitEncodeKey(&getMLIRContext(), builder, getLoc(expr->getExprLoc()), + {ops[0], ops[1], ops[2]}, ops[3], 7, + "x86.encodekey256", 4); + } + case X86::BI__builtin_ia32_aesenc128kl_u8: case X86::BI__builtin_ia32_aesdec128kl_u8: case X86::BI__builtin_ia32_aesenc256kl_u8: diff --git a/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp b/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp new file mode 100644 index 0000000000000..ad5da0d11ff02 --- /dev/null +++ b/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp @@ -0,0 +1,341 @@ +//========- CIRGenCUDANV.cpp - Interface to NVIDIA CUDA Runtime -----=========// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This provides a class for CUDA code generation targeting the NVIDIA CUDA +// runtime library. +// +//===----------------------------------------------------------------------===// + +#include "CIRGenCUDARuntime.h" +#include "CIRGenFunction.h" +#include "CIRGenModule.h" +#include "mlir/IR/Operation.h" +#include "clang/AST/ASTContext.h" +#include "clang/AST/Decl.h" +#include "clang/AST/GlobalDecl.h" +#include "clang/Basic/AddressSpaces.h" +#include "clang/Basic/Cuda.h" +#include "clang/CIR/Dialect/IR/CIRDialect.h" +#include "clang/CIR/Dialect/IR/CIRTypes.h" +#include "llvm/Support/Casting.h" + +using namespace clang; +using namespace clang::CIRGen; + +namespace { + +class CIRGenNVCUDARuntime : public CIRGenCUDARuntime { +protected: + StringRef prefix; + + // Map a device stub function to a symbol for identifying kernel in host + // code. For CUDA, the symbol for identifying the kernel is the same as the + // device stub function. For HIP, they are different. + llvm::StringMap kernelHandles; + + // Map a kernel handle to the kernel stub. + llvm::DenseMap kernelStubs; + // Mangle context for device. + std::unique_ptr deviceMC; + +private: + void emitDeviceStubBodyNew(CIRGenFunction &cgf, cir::FuncOp fn, + FunctionArgList &args); + mlir::Value prepareKernelArgs(CIRGenFunction &cgf, mlir::Location loc, + FunctionArgList &args); + mlir::Operation *getKernelHandle(cir::FuncOp fn, GlobalDecl gd) override; + std::string addPrefixToName(StringRef funcName) const; + std::string addUnderscoredPrefixToName(StringRef funcName) const; + +public: + CIRGenNVCUDARuntime(CIRGenModule &cgm); + ~CIRGenNVCUDARuntime(); + + void emitDeviceStub(CIRGenFunction &cgf, cir::FuncOp fn, + FunctionArgList &args) override; +}; + +} // namespace + +std::string CIRGenNVCUDARuntime::addPrefixToName(StringRef funcName) const { + return (prefix + funcName).str(); +} + +std::string +CIRGenNVCUDARuntime::addUnderscoredPrefixToName(StringRef funcName) const { + return ("__" + prefix + funcName).str(); +} + +CIRGenNVCUDARuntime::CIRGenNVCUDARuntime(CIRGenModule &cgm) + : CIRGenCUDARuntime(cgm), + deviceMC(cgm.getASTContext().cudaNVInitDeviceMC()) { + if (cgm.getLangOpts().OffloadViaLLVM) + cgm.errorNYI("CIRGenNVCUDARuntime: Offload via LLVM"); + else if (cgm.getLangOpts().HIP) + prefix = "hip"; + else + prefix = "cuda"; +} + +mlir::Value CIRGenNVCUDARuntime::prepareKernelArgs(CIRGenFunction &cgf, + mlir::Location loc, + FunctionArgList &args) { + CIRGenBuilderTy &builder = cgm.getBuilder(); + + // Build void *args[] and populate with the addresses of kernel arguments. + auto voidPtrArrayTy = cir::ArrayType::get(cgm.voidPtrTy, args.size()); + mlir::Value kernelArgs = builder.createAlloca( + loc, cir::PointerType::get(voidPtrArrayTy), voidPtrArrayTy, "kernel_args", + CharUnits::fromQuantity(16)); + + mlir::Value kernelArgsDecayed = + builder.createCast(cir::CastKind::array_to_ptrdecay, kernelArgs, + cir::PointerType::get(cgm.voidPtrTy)); + + for (const auto &[i, arg] : llvm::enumerate(args)) { + mlir::Value index = + builder.getConstInt(loc, llvm::APInt(/*numBits=*/32, i)); + mlir::Value storePos = + builder.createPtrStride(loc, kernelArgsDecayed, index); + mlir::Value argAddr = cgf.getAddrOfLocalVar(arg).getPointer(); + mlir::Value argAsVoid = builder.createBitcast(argAddr, cgm.voidPtrTy); + + builder.CIRBaseBuilderTy::createStore(loc, argAsVoid, storePos); + } + + return kernelArgsDecayed; +} + +// CUDA 9.0+ uses new way to launch kernels. Parameters are packed in a local +// array and kernels are launched using cudaLaunchKernel(). +void CIRGenNVCUDARuntime::emitDeviceStubBodyNew(CIRGenFunction &cgf, + cir::FuncOp fn, + FunctionArgList &args) { + + // This requires arguments to be sent to kernels in a different way. + if (cgm.getLangOpts().OffloadViaLLVM) + cgm.errorNYI("CIRGenNVCUDARuntime: Offload via LLVM"); + + if (cgm.getLangOpts().HIP) + cgm.errorNYI("CIRGenNVCUDARuntime: HIP Support"); + + CIRGenBuilderTy &builder = cgm.getBuilder(); + mlir::Location loc = fn.getLoc(); + + // For [cuda|hip]LaunchKernel, we must add another layer of indirection + // to arguments. For example, for function `add(int a, float b)`, + // we need to pass it as `void *args[2] = { &a, &b }`. + mlir::Value kernelArgs = prepareKernelArgs(cgf, loc, args); + + // Lookup cudaLaunchKernel/hipLaunchKernel function. + // HIP kernel launching API name depends on -fgpu-default-stream option. For + // the default value 'legacy', it is hipLaunchKernel. For 'per-thread', + // it is hipLaunchKernel_spt. + // cudaError_t cudaLaunchKernel(const void *func, dim3 gridDim, dim3 blockDim, + // void **args, size_t sharedMem, + // cudaStream_t stream); + // hipError_t hipLaunchKernel[_spt](const void *func, dim3 gridDim, + // dim3 blockDim, void **args, + // size_t sharedMem, hipStream_t stream); + TranslationUnitDecl *tuDecl = cgm.getASTContext().getTranslationUnitDecl(); + DeclContext *dc = TranslationUnitDecl::castToDeclContext(tuDecl); + + // The default stream is usually stream 0 (the legacy default stream). + // For per-thread default stream, we need a different LaunchKernel function. + StringRef kernelLaunchAPI = "LaunchKernel"; + if (cgm.getLangOpts().GPUDefaultStream == + LangOptions::GPUDefaultStreamKind::PerThread) + cgm.errorNYI("CUDA/HIP Stream per thread"); + + std::string launchKernelName = addPrefixToName(kernelLaunchAPI); + const IdentifierInfo &launchII = + cgm.getASTContext().Idents.get(launchKernelName); + FunctionDecl *cudaLaunchKernelFD = nullptr; + for (NamedDecl *result : dc->lookup(&launchII)) { + if (FunctionDecl *fd = dyn_cast(result)) + cudaLaunchKernelFD = fd; + } + + if (cudaLaunchKernelFD == nullptr) { + cgm.error(cgf.curFuncDecl->getLocation(), + "Can't find declaration for " + launchKernelName); + return; + } + + // Use this function to retrieve arguments for cudaLaunchKernel: + // int __[cuda|hip]PopCallConfiguration(dim3 *gridDim, dim3 *blockDim, size_t + // *sharedMem, cudaStream_t *stream) + // + // Here [cuda|hip]Stream_t, while also being the 6th argument of + // [cuda|hip]LaunchKernel, is a pointer to some opaque struct. + + mlir::Type dim3Ty = cgf.getTypes().convertType( + cudaLaunchKernelFD->getParamDecl(1)->getType()); + mlir::Type streamTy = cgf.getTypes().convertType( + cudaLaunchKernelFD->getParamDecl(5)->getType()); + + mlir::Value gridDim = + builder.createAlloca(loc, cir::PointerType::get(dim3Ty), dim3Ty, + "grid_dim", CharUnits::fromQuantity(8)); + mlir::Value blockDim = + builder.createAlloca(loc, cir::PointerType::get(dim3Ty), dim3Ty, + "block_dim", CharUnits::fromQuantity(8)); + mlir::Value sharedMem = + builder.createAlloca(loc, cir::PointerType::get(cgm.sizeTy), cgm.sizeTy, + "shared_mem", cgm.getSizeAlign()); + mlir::Value stream = + builder.createAlloca(loc, cir::PointerType::get(streamTy), streamTy, + "stream", cgm.getPointerAlign()); + + cir::FuncOp popConfig = cgm.createRuntimeFunction( + cir::FuncType::get({gridDim.getType(), blockDim.getType(), + sharedMem.getType(), stream.getType()}, + cgm.sInt32Ty), + addUnderscoredPrefixToName("PopCallConfiguration")); + cgf.emitRuntimeCall(loc, popConfig, {gridDim, blockDim, sharedMem, stream}); + + // Now emit the call to cudaLaunchKernel + // [cuda|hip]Error_t [cuda|hip]LaunchKernel(const void *func, dim3 gridDim, + // dim3 blockDim, + // void **args, size_t sharedMem, + // [cuda|hip]Stream_t stream); + + // We now either pick the function or the stub global for cuda, hip + // respectively. + mlir::Value kernel = [&]() -> mlir::Value { + if (cir::GlobalOp globalOp = llvm::dyn_cast_or_null( + kernelHandles[fn.getSymName()])) { + cir::PointerType kernelTy = cir::PointerType::get(globalOp.getSymType()); + mlir::Value kernelVal = cir::GetGlobalOp::create(builder, loc, kernelTy, + globalOp.getSymName()); + return kernelVal; + } + if (cir::FuncOp funcOp = llvm::dyn_cast_or_null( + kernelHandles[fn.getSymName()])) { + cir::PointerType kernelTy = + cir::PointerType::get(funcOp.getFunctionType()); + mlir::Value kernelVal = + cir::GetGlobalOp::create(builder, loc, kernelTy, funcOp.getSymName()); + mlir::Value func = builder.createBitcast(kernelVal, cgm.voidPtrTy); + return func; + } + llvm_unreachable("Expected stub handle to be cir::GlobalOp or FuncOp"); + }(); + + CallArgList launchArgs; + launchArgs.add(RValue::get(kernel), + cudaLaunchKernelFD->getParamDecl(0)->getType()); + launchArgs.add( + RValue::getAggregate(Address(gridDim, CharUnits::fromQuantity(8))), + cudaLaunchKernelFD->getParamDecl(1)->getType()); + launchArgs.add( + RValue::getAggregate(Address(blockDim, CharUnits::fromQuantity(8))), + cudaLaunchKernelFD->getParamDecl(2)->getType()); + launchArgs.add(RValue::get(kernelArgs), + cudaLaunchKernelFD->getParamDecl(3)->getType()); + launchArgs.add( + RValue::get(builder.CIRBaseBuilderTy::createLoad(loc, sharedMem)), + cudaLaunchKernelFD->getParamDecl(4)->getType()); + launchArgs.add(RValue::get(builder.CIRBaseBuilderTy::createLoad(loc, stream)), + cudaLaunchKernelFD->getParamDecl(5)->getType()); + + mlir::Type launchTy = + cgm.getTypes().convertType(cudaLaunchKernelFD->getType()); + mlir::Operation *cudaKernelLauncherFn = cgm.createRuntimeFunction( + cast(launchTy), launchKernelName); + const CIRGenFunctionInfo &callInfo = + cgm.getTypes().arrangeFunctionDeclaration(cudaLaunchKernelFD); + cgf.emitCall(callInfo, CIRGenCallee::forDirect(cudaKernelLauncherFn), + ReturnValueSlot(), launchArgs); + + if (cgm.getASTContext().getTargetInfo().getCXXABI().isMicrosoft() && + !cgf.getLangOpts().HIP) + cgm.errorNYI("MSVC CUDA stub handling"); +} + +void CIRGenNVCUDARuntime::emitDeviceStub(CIRGenFunction &cgf, cir::FuncOp fn, + FunctionArgList &args) { + + if (auto globalOp = + llvm::dyn_cast(kernelHandles[fn.getSymName()])) { + CIRGenBuilderTy &builder = cgm.getBuilder(); + mlir::Type fnPtrTy = globalOp.getSymType(); + auto sym = mlir::FlatSymbolRefAttr::get(fn.getSymNameAttr()); + auto gv = cir::GlobalViewAttr::get(fnPtrTy, sym); + + globalOp->setAttr("initial_value", gv); + globalOp->removeAttr("sym_visibility"); + globalOp->setAttr("alignment", builder.getI64IntegerAttr( + cgm.getPointerAlign().getQuantity())); + } + + // CUDA 9.0 changed the way to launch kernels. + if (CudaFeatureEnabled(cgm.getTarget().getSDKVersion(), + CudaFeature::CUDA_USES_NEW_LAUNCH) || + (cgm.getLangOpts().HIP && cgm.getLangOpts().HIPUseNewLaunchAPI) || + cgm.getLangOpts().OffloadViaLLVM) + emitDeviceStubBodyNew(cgf, fn, args); + else + cgm.errorNYI("Emit Stub Body Legacy"); +} + +CIRGenCUDARuntime *clang::CIRGen::createNVCUDARuntime(CIRGenModule &cgm) { + return new CIRGenNVCUDARuntime(cgm); +} + +CIRGenNVCUDARuntime::~CIRGenNVCUDARuntime() {} + +mlir::Operation *CIRGenNVCUDARuntime::getKernelHandle(cir::FuncOp fn, + GlobalDecl gd) { + + // Check if we already have a kernel handle for this function + auto it = kernelHandles.find(fn.getSymName()); + if (it != kernelHandles.end()) { + mlir::Operation *oldHandle = it->second; + // Here we know that the fn did not change. Return it + if (kernelStubs[oldHandle] == fn) + return oldHandle; + + // We've found the function name, but F itself has changed, so we need to + // update the references. + if (cgm.getLangOpts().HIP) { + // For HIP compilation the handle itself does not change, so we only need + // to update the Stub value. + kernelStubs[oldHandle] = fn; + return oldHandle; + } + // For non-HIP compilation, erase the old Stub and fall-through to creating + // new entries. + kernelStubs.erase(oldHandle); + } + + // If not targeting HIP, store the function itself + if (!cgm.getLangOpts().HIP) { + kernelHandles[fn.getSymName()] = fn; + kernelStubs[fn] = fn; + return fn; + } + + // Create a new CIR global variable to represent the kernel handle + CIRGenBuilderTy &builder = cgm.getBuilder(); + StringRef globalName = cgm.getMangledName( + gd.getWithKernelReferenceKind(KernelReferenceKind::Kernel)); + const VarDecl *varDecl = llvm::dyn_cast_or_null(gd.getDecl()); + cir::GlobalOp globalOp = + cgm.getOrCreateCIRGlobal(globalName, fn.getFunctionType().getReturnType(), + LangAS::Default, varDecl, NotForDefinition); + + globalOp->setAttr("alignment", builder.getI64IntegerAttr( + cgm.getPointerAlign().getQuantity())); + + // Store references + kernelHandles[fn.getSymName()] = globalOp; + kernelStubs[globalOp] = fn; + + return globalOp; +} diff --git a/clang/lib/CIR/CodeGen/CIRGenCUDARuntime.cpp b/clang/lib/CIR/CodeGen/CIRGenCUDARuntime.cpp new file mode 100644 index 0000000000000..14189ad7a52f3 --- /dev/null +++ b/clang/lib/CIR/CodeGen/CIRGenCUDARuntime.cpp @@ -0,0 +1,20 @@ +//===----- CIRGenCUDARuntime.cpp - Interface to CUDA Runtimes -------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This provides an abstract class for CUDA code generation. Concrete +// subclasses of this implement code generation for specific CUDA +// runtime libraries. +// +//===----------------------------------------------------------------------===// + +#include "CIRGenCUDARuntime.h" + +using namespace clang; +using namespace CIRGen; + +CIRGenCUDARuntime::~CIRGenCUDARuntime() {} diff --git a/clang/lib/CIR/CodeGen/CIRGenCUDARuntime.h b/clang/lib/CIR/CodeGen/CIRGenCUDARuntime.h new file mode 100644 index 0000000000000..83eb0c02188ba --- /dev/null +++ b/clang/lib/CIR/CodeGen/CIRGenCUDARuntime.h @@ -0,0 +1,50 @@ +//===------ CIRGenCUDARuntime.h - Interface to CUDA Runtimes -----*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This provides an abstract class for CUDA code generation. Concrete +// subclasses of this implement code generation for specific CUDA +// runtime libraries. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_LIB_CIR_CIRGENCUDARUNTIME_H +#define LLVM_CLANG_LIB_CIR_CIRGENCUDARUNTIME_H + +#include "clang/CIR/Dialect/IR/CIRDialect.h" + +namespace clang { +class CUDAKernelCallExpr; +} + +namespace clang::CIRGen { + +class CIRGenFunction; +class CIRGenModule; +class FunctionArgList; +class RValue; +class ReturnValueSlot; + +class CIRGenCUDARuntime { +protected: + CIRGenModule &cgm; + +public: + CIRGenCUDARuntime(CIRGenModule &cgm) : cgm(cgm) {} + virtual ~CIRGenCUDARuntime(); + + virtual void emitDeviceStub(CIRGenFunction &cgf, cir::FuncOp fn, + FunctionArgList &args) = 0; + + virtual mlir::Operation *getKernelHandle(cir::FuncOp fn, GlobalDecl gd) = 0; +}; + +CIRGenCUDARuntime *createNVCUDARuntime(CIRGenModule &cgm); + +} // namespace clang::CIRGen + +#endif // LLVM_CLANG_LIB_CIR_CIRGENCUDARUNTIME_H diff --git a/clang/lib/CIR/CodeGen/CIRGenCall.cpp b/clang/lib/CIR/CodeGen/CIRGenCall.cpp index 809d775e77d55..cfbba27e12b93 100644 --- a/clang/lib/CIR/CodeGen/CIRGenCall.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenCall.cpp @@ -111,6 +111,203 @@ static void addAttributesFromFunctionProtoType(CIRGenBuilderTy &builder, mlir::UnitAttr::get(builder.getContext())); } +static void addNoBuiltinAttributes(mlir::MLIRContext &ctx, + mlir::NamedAttrList &attrs, + const LangOptions &langOpts, + const NoBuiltinAttr *nba = nullptr) { + // First, handle the language options passed through -fno-builtin. + // or, if there is a wildcard in the builtin names specified through the + // attribute, disable them all. + if (langOpts.NoBuiltin || + (nba && llvm::is_contained(nba->builtinNames(), "*"))) { + // -fno-builtin disables them all. + // Empty attribute means 'all'. + attrs.set(cir::CIRDialect::getNoBuiltinsAttrName(), + mlir::ArrayAttr::get(&ctx, {})); + return; + } + + llvm::SetVector nbFuncs; + auto addNoBuiltinAttr = [&ctx, &nbFuncs](StringRef builtinName) { + nbFuncs.insert(mlir::StringAttr::get(&ctx, builtinName)); + }; + + // Then, add attributes for builtins specified through -fno-builtin-. + llvm::for_each(langOpts.NoBuiltinFuncs, addNoBuiltinAttr); + + // Now, let's check the __attribute__((no_builtin("...")) attribute added to + // the source. + if (nba) + llvm::for_each(nba->builtinNames(), addNoBuiltinAttr); + + if (!nbFuncs.empty()) + attrs.set(cir::CIRDialect::getNoBuiltinsAttrName(), + mlir::ArrayAttr::get(&ctx, nbFuncs.getArrayRef())); +} + +/// Add denormal-fp-math and denormal-fp-math-f32 as appropriate for the +/// requested denormal behavior, accounting for the overriding behavior of the +/// -f32 case. +static void addDenormalModeAttrs(llvm::DenormalMode fpDenormalMode, + llvm::DenormalMode fp32DenormalMode, + mlir::NamedAttrList &attrs) { + // TODO(cir): Classic-codegen sets the denormal modes here. There are two + // values, both with a string, but it seems that perhaps we could combine + // these into a single attribute? It seems a little silly to have two so + // similar named attributes that do the same thing. +} + +/// Add default attributes to a function, which have merge semantics under +/// -mlink-builtin-bitcode and should not simply overwrite any existing +/// attributes in the linked library. +static void +addMergeableDefaultFunctionAttributes(const CodeGenOptions &codeGenOpts, + mlir::NamedAttrList &attrs) { + addDenormalModeAttrs(codeGenOpts.FPDenormalMode, codeGenOpts.FP32DenormalMode, + attrs); +} + +static llvm::StringLiteral +getZeroCallUsedRegsKindStr(llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind k) { + switch (k) { + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::Skip: + llvm_unreachable("No string value, shouldn't be able to get here"); + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::UsedGPRArg: + return "used-gpr-arg"; + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::UsedGPR: + return "used-gpr"; + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::UsedArg: + return "used-arg"; + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::Used: + return "used"; + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::AllGPRArg: + return "all-gpr-arg"; + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::AllGPR: + return "all-gpr"; + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::AllArg: + return "all-arg"; + case llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::All: + return "all"; + } + + llvm_unreachable("Unknown kind?"); +} + +/// Add default attributes to a function, which have merge semantics under +/// -mlink-builtin-bitcode and should not simply overwrite any existing +/// attributes in the linked library. +static void addTrivialDefaultFunctionAttributes( + mlir::MLIRContext *mlirCtx, StringRef name, bool hasOptNoneAttr, + const CodeGenOptions &codeGenOpts, const LangOptions &langOpts, + bool attrOnCallSite, mlir::NamedAttrList &attrs) { + // TODO(cir): Handle optimize attribute flag here. + // OptimizeNoneAttr takes precedence over -Os or -Oz. No warning needed. + if (!hasOptNoneAttr) { + if (codeGenOpts.OptimizeSize) + attrs.set(cir::CIRDialect::getOptimizeForSizeAttrName(), + mlir::UnitAttr::get(mlirCtx)); + if (codeGenOpts.OptimizeSize == 2) + attrs.set(cir::CIRDialect::getMinSizeAttrName(), + mlir::UnitAttr::get(mlirCtx)); + } + + // TODO(cir): Classic codegen adds 'DisableRedZone', 'indirect-tls-seg-refs' + // and 'NoImplicitFloat' here. + + if (attrOnCallSite) { + // Add the 'nobuiltin' tag, which is different from 'no-builtins'. + if (!codeGenOpts.SimplifyLibCalls || langOpts.isNoBuiltinFunc(name)) + attrs.set(cir::CIRDialect::getNoBuiltinAttrName(), + mlir::UnitAttr::get(mlirCtx)); + + if (!codeGenOpts.TrapFuncName.empty()) + attrs.set(cir::CIRDialect::getTrapFuncNameAttrName(), + mlir::StringAttr::get(mlirCtx, codeGenOpts.TrapFuncName)); + } else { + // TODO(cir): Set frame pointer attribute here. + // TODO(cir): a number of other attribute 1-offs based on codegen/lang opts + // should be done here: less-recise-fpmad null-pointer-is-valid + // no-trapping-math + // various inf/nan/nsz/etc work here. + // + // TODO(cir): set stack-protector buffer size attribute (sorted oddly in + // classic compiler inside of the above region, but should be done on its + // own). + // TODO(cir): other attributes here: + // reciprocal estimates, prefer-vector-width, stackrealign, backchain, + // split-stack, speculative-load-hardening. + + if (codeGenOpts.getZeroCallUsedRegs() == + llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind::Skip) + attrs.erase(cir::CIRDialect::getZeroCallUsedRegsAttrName()); + else + attrs.set(cir::CIRDialect::getZeroCallUsedRegsAttrName(), + mlir::StringAttr::get(mlirCtx, + getZeroCallUsedRegsKindStr( + codeGenOpts.getZeroCallUsedRegs()))); + } + + if (langOpts.assumeFunctionsAreConvergent()) { + // Conservatively, mark all functions and calls in CUDA and OpenCL as + // convergent (meaning, they may call an intrinsically convergent op, such + // as __syncthreads() / barrier(), and so can't have certain optimizations + // applied around them). LLVM will remove this attribute where it safely + // can. + attrs.set(cir::CIRDialect::getConvergentAttrName(), + mlir::UnitAttr::get(mlirCtx)); + } + + // TODO(cir): Classic codegen adds 'nounwind' here in a bunch of offload + // targets. + + if (codeGenOpts.SaveRegParams && !attrOnCallSite) + attrs.set(cir::CIRDialect::getSaveRegParamsAttrName(), + mlir::UnitAttr::get(mlirCtx)); + + // These come in the form of an optional equality sign, so make sure we pass + // these on correctly. These will eventually just be passed through to + // LLVM-IR, but we want to put them all in 1 array to simplify the + // LLVM-MLIR dialect. + SmallVector defaultFuncAttrs; + llvm::transform( + codeGenOpts.DefaultFunctionAttrs, std::back_inserter(defaultFuncAttrs), + [mlirCtx](llvm::StringRef arg) { + auto [var, value] = arg.split('='); + auto valueAttr = + value.empty() + ? cast(mlir::UnitAttr::get(mlirCtx)) + : cast(mlir::StringAttr::get(mlirCtx, value)); + return mlir::NamedAttribute(var, valueAttr); + }); + + if (!defaultFuncAttrs.empty()) + attrs.set(cir::CIRDialect::getDefaultFuncAttrsAttrName(), + mlir::DictionaryAttr::get(mlirCtx, defaultFuncAttrs)); + + // TODO(cir): Do branch protection attributes here. +} + +/// This function matches the behavior of 'getDefaultFunctionAttributes' from +/// classic codegen, despite the similarity of its name to +/// 'addDefaultFunctionDefinitionAttributes', which is a caller of this +/// function. +void CIRGenModule::addDefaultFunctionAttributes(StringRef name, + bool hasOptNoneAttr, + bool attrOnCallSite, + mlir::NamedAttrList &attrs) { + + addTrivialDefaultFunctionAttributes(&getMLIRContext(), name, hasOptNoneAttr, + codeGenOpts, langOpts, attrOnCallSite, + attrs); + + if (!attrOnCallSite) { + // TODO(cir): Classic codegen adds pointer-auth attributes here, by calling + // into TargetCodeGenInfo. At the moment, we've not looked into this as it + // is somewhat less used. + addMergeableDefaultFunctionAttributes(codeGenOpts, attrs); + } +} + /// Construct the CIR attribute list of a function or call. void CIRGenModule::constructAttributeList(llvm::StringRef name, const CIRGenFunctionInfo &info, @@ -137,6 +334,13 @@ void CIRGenModule::constructAttributeList(llvm::StringRef name, const Decl *targetDecl = calleeInfo.getCalleeDecl().getDecl(); + // TODO(cir): OMP Assume Attributes should be here. + + const NoBuiltinAttr *nba = nullptr; + + // TODO(cir): Some work for arg memory effects can be done here, as it is in + // classic codegen. + if (targetDecl) { if (targetDecl->hasAttr()) addUnitAttr(cir::CIRDialect::getNoThrowAttrName()); @@ -173,7 +377,7 @@ void CIRGenModule::constructAttributeList(llvm::StringRef name, if (!(attrOnCallSite && isVirtualCall)) { if (func->isNoReturn()) addUnitAttr(cir::CIRDialect::getNoReturnAttrName()); - // TODO(cir): Set NoBuiltinAttr here. + nba = func->getAttr(); } } @@ -203,13 +407,19 @@ void CIRGenModule::constructAttributeList(llvm::StringRef name, // TODO(cir): Implement 'BPFFastCall' attribute here. This requires C, and // the BPF target. - // TODO(cir): Detecting 'OptimizeNone' is done here in classic codegen, when - // we figure out when to do that, we should do it here. - // TODO(cir): AllocSize attr should be done here, but it has some additional - // work with forming the correct value for it. Typically this calls into - // LLVM to set it correctly, which flattens the elem size and num-elems into - // a single value. CIR should probably represent these as two values and - // handle the combination during lowering by calling into LLVM. + if (auto *allocSizeAttr = targetDecl->getAttr()) { + unsigned size = allocSizeAttr->getElemSizeParam().getLLVMIndex(); + + if (allocSizeAttr->getNumElemsParam().isValid()) { + unsigned numElts = allocSizeAttr->getNumElemsParam().getLLVMIndex(); + attrs.set(cir::CIRDialect::getAllocSizeAttrName(), + builder.getDenseI32ArrayAttr( + {static_cast(size), static_cast(numElts)})); + } else { + attrs.set(cir::CIRDialect::getAllocSizeAttrName(), + builder.getDenseI32ArrayAttr({static_cast(size)})); + } + } // TODO(cir): Quite a few CUDA and OpenCL attributes are added here, like // uniform-work-group-size. @@ -229,13 +439,48 @@ void CIRGenModule::constructAttributeList(llvm::StringRef name, attrs.set(cir::CIRDialect::getModularFormatAttrName(), builder.getStringAttr(llvm::join(args, ","))); } + } - // TODO(cir): We should set nobuiltin and default function attrs here. + addNoBuiltinAttributes(getMLIRContext(), attrs, getLangOpts(), nba); + bool hasOptNoneAttr = targetDecl && targetDecl->hasAttr(); + addDefaultFunctionAttributes(name, hasOptNoneAttr, attrOnCallSite, attrs); + if (targetDecl) { // TODO(cir): There is another region of `if (targetDecl)` that handles // removing some attributes that are necessary modifications of the - // default-function attrs. We should do that here. + // default-function attrs. Including: + // NoSpeculativeLoadHardening + // SpeculativeLoadHardening + // NoSplitStack + // Non-lazy-bind + // 'sample-profile-suffix-elision-policy'. + + if (targetDecl->hasAttr()) { + // A function "__attribute__((...))" overrides the command-line flag. + auto kind = + targetDecl->getAttr()->getZeroCallUsedRegs(); + attrs.set( + cir::CIRDialect::getZeroCallUsedRegsAttrName(), + mlir::StringAttr::get( + &getMLIRContext(), + ZeroCallUsedRegsAttr::ConvertZeroCallUsedRegsKindToStr(kind))); + } + + if (targetDecl->hasAttr()) + attrs.erase(cir::CIRDialect::getConvergentAttrName()); } + + // TODO(cir): A bunch of non-call-site function IR attributes from + // declaration-specific information, including tail calls, + // cmse_nonsecure_entry, additional/automatic 'returns-twice' functions, + // CPU-features/overrides, and hotpatch support. + + // TODO(cir): Add loader-replaceable attribute here. + + // TODO(cir): Ret attrs. + // + // TODO(cir): Arg attrs. + assert(!cir::MissingFeatures::opCallAttrs()); } diff --git a/clang/lib/CIR/CodeGen/CIRGenCleanup.cpp b/clang/lib/CIR/CodeGen/CIRGenCleanup.cpp index 8d9ea7c6c22eb..01fd9e1004bc3 100644 --- a/clang/lib/CIR/CodeGen/CIRGenCleanup.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenCleanup.cpp @@ -147,12 +147,24 @@ void *EHScopeStack::pushCleanup(CleanupKind kind, size_t size) { assert(!cir::MissingFeatures::innermostEHScope()); - EHCleanupScope *scope = new (buffer) EHCleanupScope( - size, branchFixups.size(), innermostNormalCleanup, innermostEHScope); + // Per C++ [except.terminate], it is implementation-defined whether none, + // some, or all cleanups are called before std::terminate. Thus, when + // terminate is the current EH scope, we may skip adding any EH cleanup + // scopes. + if (innermostEHScope != stable_end() && + find(innermostEHScope)->getKind() == EHScope::Terminate) + isEHCleanup = false; + + EHCleanupScope *scope = new (buffer) + EHCleanupScope(isNormalCleanup, isEHCleanup, size, branchFixups.size(), + innermostNormalCleanup, innermostEHScope); if (isNormalCleanup) innermostNormalCleanup = stable_begin(); + if (isEHCleanup) + innermostEHScope = stable_begin(); + if (isLifetimeMarker) cgf->cgm.errorNYI("push lifetime marker cleanup"); diff --git a/clang/lib/CIR/CodeGen/CIRGenCleanup.h b/clang/lib/CIR/CodeGen/CIRGenCleanup.h index 85dbde4058889..6ad90a9072968 100644 --- a/clang/lib/CIR/CodeGen/CIRGenCleanup.h +++ b/clang/lib/CIR/CodeGen/CIRGenCleanup.h @@ -211,15 +211,14 @@ class alignas(EHScopeStack::ScopeStackAlignment) EHCleanupScope return sizeof(EHCleanupScope) + cleanupBits.cleanupSize; } - EHCleanupScope(unsigned cleanupSize, unsigned fixupDepth, + EHCleanupScope(bool isNormal, bool isEH, unsigned cleanupSize, + unsigned fixupDepth, EHScopeStack::stable_iterator enclosingNormal, EHScopeStack::stable_iterator enclosingEH) : EHScope(EHScope::Cleanup, enclosingEH), enclosingNormal(enclosingNormal), fixupDepth(fixupDepth) { - // TODO(cir): When exception handling is upstreamed, isNormalCleanup and - // isEHCleanup will be arguments to the constructor. - cleanupBits.isNormalCleanup = true; - cleanupBits.isEHCleanup = false; + cleanupBits.isNormalCleanup = isNormal; + cleanupBits.isEHCleanup = isEH; cleanupBits.isActive = true; cleanupBits.isLifetimeMarker = false; cleanupBits.testFlagInNormalCleanup = false; diff --git a/clang/lib/CIR/CodeGen/CIRGenConstantEmitter.h b/clang/lib/CIR/CodeGen/CIRGenConstantEmitter.h index ccded3dacf031..1cd7b5bffb1dc 100644 --- a/clang/lib/CIR/CodeGen/CIRGenConstantEmitter.h +++ b/clang/lib/CIR/CodeGen/CIRGenConstantEmitter.h @@ -116,6 +116,8 @@ class ConstantEmitter { mlir::Attribute tryEmitPrivateForMemory(const APValue &value, QualType destTy); + mlir::Attribute tryEmitAbstract(const Expr *e, QualType destType); + private: #ifndef NDEBUG void initializeNonAbstract() { diff --git a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp index 8bdf075aab695..b2f80a0a7da79 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp @@ -1464,8 +1464,7 @@ LValue CIRGenFunction::emitCastLValue(const CastExpr *e) { "emitCastLValue: address space conversion from unknown address " "space"); - mlir::Value v = getTargetHooks().performAddrSpaceCast( - *this, lv.getPointer(), srcAS, convertType(destTy)); + mlir::Value v = performAddrSpaceCast(lv.getPointer(), convertType(destTy)); return makeAddrLValue(Address(v, convertTypeForMem(e->getType()), lv.getAddress().getAlignment()), @@ -2504,20 +2503,13 @@ Address CIRGenFunction::createTempAlloca(mlir::Type ty, CharUnits align, // in C++ the auto variables are in the default address space. Therefore // cast alloca to the default address space when necessary. - LangAS allocaAS = alloca.getAddressSpace() - ? clang::getLangASFromTargetAS( - alloca.getAddressSpace().getValue().getUInt()) - : clang::LangAS::Default; - LangAS dstTyAS = clang::LangAS::Default; - if (getCIRAllocaAddressSpace()) { - dstTyAS = clang::getLangASFromTargetAS( - getCIRAllocaAddressSpace().getValue().getUInt()); - } + cir::PointerType dstTy; + if (getCIRAllocaAddressSpace()) + dstTy = builder.getPointerTo(ty, getCIRAllocaAddressSpace()); + else + dstTy = builder.getPointerTo(ty, clang::LangAS::Default); + v = performAddrSpaceCast(v, dstTy); - if (dstTyAS != allocaAS) { - getTargetHooks().performAddrSpaceCast(*this, v, getCIRAllocaAddressSpace(), - builder.getPointerTo(ty, dstTyAS)); - } return Address(v, ty, align); } diff --git a/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp b/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp index 98cf75f0d69e0..5d28ac6097c80 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp @@ -14,8 +14,10 @@ #include "CIRGenConstantEmitter.h" #include "CIRGenFunction.h" +#include "clang/AST/CharUnits.h" #include "clang/AST/DeclCXX.h" #include "clang/AST/ExprCXX.h" +#include "clang/AST/ExprObjC.h" #include "clang/Basic/OperatorKinds.h" #include "clang/CIR/MissingFeatures.h" @@ -465,7 +467,7 @@ static mlir::Value emitCXXNewAllocSize(CIRGenFunction &cgf, const CXXNewExpr *e, const Expr *arraySize = *e->getArraySize(); mlir::Attribute constNumElements = ConstantEmitter(cgf.cgm, &cgf) - .emitAbstract(arraySize, arraySize->getType()); + .tryEmitAbstract(arraySize, arraySize->getType()); if (constNumElements) { // Get an APInt from the constant const llvm::APInt &count = @@ -520,9 +522,113 @@ static mlir::Value emitCXXNewAllocSize(CIRGenFunction &cgf, const CXXNewExpr *e, size = cgf.getBuilder().getConstInt(loc, allocationSize); } } else { - // TODO: Handle the variable size case - cgf.cgm.errorNYI(e->getSourceRange(), - "emitCXXNewAllocSize: variable array size"); + // Create a value for the variable number of elements + numElements = cgf.emitScalarExpr(*e->getArraySize()); + auto numElementsType = mlir::cast(numElements.getType()); + unsigned numElementsWidth = numElementsType.getWidth(); + + // We might need check for overflow. + + mlir::Value hasOverflow; + // Classic codegen checks for the size variable being signed, having a + // smaller width than size_t, and having a larger width than size_t. + // However, the AST implicitly casts the size variable to size_t so none of + // these conditions will ever be met. + assert( + !(*e->getArraySize())->getType()->isSignedIntegerOrEnumerationType() && + (numElementsWidth == sizeWidth) && + (numElements.getType() == cgf.sizeTy) && + "Expected array size to be implicitly cast to size_t!"); + + // There are up to three conditions we need to test for: + // 1) if minElements > 0, we need to check whether numElements is smaller + // than that. + // 2) we need to compute + // sizeWithoutCookie := numElements * typeSizeMultiplier + // and check whether it overflows; and + // 3) if we need a cookie, we need to compute + // size := sizeWithoutCookie + cookieSize + // and check whether it overflows. + + if (minElements) { + // Don't allow allocation of fewer elements than we have initializers. + if (!hasOverflow) { + // FIXME: Avoid creating this twice. It may happen above. + mlir::Value minElementsV = cgf.getBuilder().getConstInt( + loc, llvm::APInt(sizeWidth, minElements)); + hasOverflow = cgf.getBuilder().createCompare(loc, cir::CmpOpKind::lt, + numElements, minElementsV); + } + } + + size = numElements; + + // Multiply by the type size if necessary. This multiplier + // includes all the factors for nested arrays. + // + // This step also causes numElements to be scaled up by the + // nested-array factor if necessary. Overflow on this computation + // can be ignored because the result shouldn't be used if + // allocation fails. + if (typeSizeMultiplier != 1) { + mlir::Value tsmV = cgf.getBuilder().getConstInt(loc, typeSizeMultiplier); + auto mulOp = cir::BinOpOverflowOp::create( + cgf.getBuilder(), loc, mlir::cast(cgf.sizeTy), + cir::BinOpOverflowKind::Mul, size, tsmV); + + if (hasOverflow) + hasOverflow = + cgf.getBuilder().createOr(loc, hasOverflow, mulOp.getOverflow()); + else + hasOverflow = mulOp.getOverflow(); + + size = mulOp.getResult(); + + // Also scale up numElements by the array size multiplier. + if (arraySizeMultiplier != 1) { + // If the base element type size is 1, then we can re-use the + // multiply we just did. + if (typeSize.isOne()) { + assert(arraySizeMultiplier == typeSizeMultiplier); + numElements = size; + + // Otherwise we need a separate multiply. + } else { + mlir::Value asmV = + cgf.getBuilder().getConstInt(loc, arraySizeMultiplier); + numElements = cgf.getBuilder().createMul(loc, numElements, asmV); + } + } + } else { + // numElements doesn't need to be scaled. + assert(arraySizeMultiplier == 1); + } + + // Add in the cookie size if necessary. + if (cookieSize != 0) { + sizeWithoutCookie = size; + mlir::Value cookieSizeV = cgf.getBuilder().getConstInt(loc, cookieSize); + auto addOp = cir::BinOpOverflowOp::create( + cgf.getBuilder(), loc, mlir::cast(cgf.sizeTy), + cir::BinOpOverflowKind::Add, size, cookieSizeV); + + if (hasOverflow) + hasOverflow = + cgf.getBuilder().createOr(loc, hasOverflow, addOp.getOverflow()); + else + hasOverflow = addOp.getOverflow(); + + size = addOp.getResult(); + } + + // If we had any possibility of dynamic overflow, make a select to + // overwrite 'size' with an all-ones value, which should cause + // operator new to throw. + if (hasOverflow) { + mlir::Value allOnes = + cgf.getBuilder().getConstInt(loc, llvm::APInt::getAllOnes(sizeWidth)); + size = cgf.getBuilder().createSelect(loc, hasOverflow, allOnes, size); + } } if (cookieSize == 0) @@ -568,13 +674,132 @@ void CIRGenFunction::emitNewArrayInitializer( if (!e->hasInitializer()) return; + Address curPtr = beginPtr; + unsigned initListElements = 0; const Expr *init = e->getInitializer(); + Address endOfInit = Address::invalid(); + QualType::DestructionKind dtorKind = elementType.isDestructedType(); + assert(!cir::MissingFeatures::cleanupDeactivationScope()); + + // Attempt to perform zero-initialization using memset. + auto tryMemsetInitialization = [&]() -> bool { + mlir::Location loc = numElements.getLoc(); + + // FIXME: If the type is a pointer-to-data-member under the Itanium ABI, + // we can initialize with a memset to -1. + if (!cgm.getTypes().isZeroInitializable(elementType)) + return false; + + // Optimization: since zero initialization will just set the memory + // to all zeroes, generate a single memset to do it in one shot. + + // Subtract out the size of any elements we've already initialized. + auto remainingSize = allocSizeWithoutCookie; + if (initListElements) { + // We know this can't overflow; we check this when doing the allocation. + unsigned initializedSize = + getContext().getTypeSizeInChars(elementType).getQuantity() * + initListElements; + cir::ConstantOp initSizeOp = + builder.getConstInt(loc, remainingSize.getType(), initializedSize); + remainingSize = builder.createSub(loc, remainingSize, initSizeOp); + } + + // Create the memset. + mlir::Value castOp = + builder.createPtrBitcast(curPtr.getPointer(), cgm.voidTy); + builder.createMemSet(loc, castOp, builder.getConstInt(loc, cgm.uInt8Ty, 0), + remainingSize); + return true; + }; + const InitListExpr *ile = dyn_cast(init); - if (ile) { - cgm.errorNYI(ile->getSourceRange(), "emitNewArrayInitializer: init list"); - return; + const CXXParenListInitExpr *cplie = nullptr; + const StringLiteral *sl = nullptr; + const ObjCEncodeExpr *ocee = nullptr; + const Expr *ignoreParen = nullptr; + if (!ile) { + ignoreParen = init->IgnoreParenImpCasts(); + cplie = dyn_cast(ignoreParen); + sl = dyn_cast(ignoreParen); + ocee = dyn_cast(ignoreParen); + } + // If the initializer is an initializer list, first do the explicit elements. + if (ile || cplie || sl || ocee) { + // Initializing from a (braced) string literal is a special case; the init + // list element does not initialize a (single) array element. + if ((ile && ile->isStringLiteralInit()) || sl || ocee) { + cgm.errorNYI(ile->getSourceRange(), + "emitNewArrayInitializer: string literal init"); + return; + } + + ArrayRef initExprs = + ile ? ile->inits() : cplie->getInitExprs(); + initListElements = initExprs.size(); + + // If this is a multi-dimensional array new, we will initialize multiple + // elements with each init list element. + QualType allocType = e->getAllocatedType(); + if (const ConstantArrayType *cat = dyn_cast_or_null( + allocType->getAsArrayTypeUnsafe())) { + (void)cat; + cgm.errorNYI(ile->getSourceRange(), + "emitNewArrayInitializer: constant array init"); + return; + } + + // Enter a partial-destruction Cleanup if necessary. + if (dtorKind) { + cgm.errorNYI(ile->getSourceRange(), + "emitNewArrayInitializer: init requires dtor"); + return; + } + + CharUnits elementSize = getContext().getTypeSizeInChars(elementType); + CharUnits startAlign = curPtr.getAlignment(); + unsigned i = 0; + for (const Expr *ie : initExprs) { + // Tell the cleanup that it needs to destroy up to this + // element. TODO: some of these stores can be trivially + // observed to be unnecessary. + if (endOfInit.isValid()) { + cgm.errorNYI(ie->getSourceRange(), + "emitNewArrayInitializer: update dtor cleanup ptr"); + return; + } + // FIXME: If the last initializer is an incomplete initializer list for + // an array, and we have an array filler, we can fold together the two + // initialization loops. + storeAnyExprIntoOneUnit(*this, ie, ie->getType(), curPtr, + AggValueSlot::DoesNotOverlap); + mlir::Location loc = getLoc(ie->getExprLoc()); + mlir::Value castOp = builder.createPtrBitcast( + curPtr.getPointer(), convertTypeForMem(allocType)); + mlir::Value offsetOp = builder.getSignedInt(loc, 1, /*width=*/32); + mlir::Value dataPtr = builder.createPtrStride(loc, castOp, offsetOp); + curPtr = Address(dataPtr, curPtr.getElementType(), + startAlign.alignmentAtOffset((++i) * elementSize)); + } + + // The remaining elements are filled with the array filler expression. + init = ile ? ile->getArrayFiller() : cplie->getArrayFiller(); + + // Extract the initializer for the individual array elements by pulling + // out the array filler from all the nested initializer lists. This avoids + // generating a nested loop for the initialization. + while (init && init->getType()->isConstantArrayType()) { + auto *subIle = dyn_cast(init); + if (!subIle) + break; + assert(subIle->getNumInits() == 0 && "explicit inits in array filler?"); + init = subIle->getArrayFiller(); + } + + // Switch back to initializing one base element at a time. + curPtr = curPtr.withElementType(builder, beginPtr.getElementType()); } // If all elements have already been initialized, skip any further @@ -609,6 +834,15 @@ void CIRGenFunction::emitNewArrayInitializer( return; } + // If this is value-initialization, we can usually use memset. + if (isa(init)) { + if (tryMemsetInitialization()) + return; + cgm.errorNYI(init->getSourceRange(), + "emitNewArrayInitializer: implicit value init"); + return; + } + cgm.errorNYI(init->getSourceRange(), "emitNewArrayInitializer: unsupported initializer"); return; @@ -846,6 +1080,16 @@ mlir::Value CIRGenFunction::emitCXXNewExpr(const CXXNewExpr *e) { // If there is a brace-initializer, cannot allocate fewer elements than inits. unsigned minElements = 0; + if (e->isArray() && e->hasInitializer()) { + const InitListExpr *ile = dyn_cast(e->getInitializer()); + if (ile && ile->isStringLiteralInit()) + minElements = + cast(ile->getType()->getAsArrayTypeUnsafe()) + ->getSize() + .getZExtValue(); + else if (ile) + minElements = ile->getNumInits(); + } mlir::Value numElements = nullptr; mlir::Value allocSizeWithoutCookie = nullptr; diff --git a/clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp b/clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp index 0c756d8456682..3b88856f09842 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp @@ -1671,6 +1671,12 @@ mlir::Attribute ConstantEmitter::tryEmitPrivateForVarInit(const VarDecl &d) { return {}; } +mlir::Attribute ConstantEmitter::tryEmitAbstract(const Expr *e, + QualType destType) { + AbstractStateRAII state{*this, true}; + return tryEmitPrivate(e, destType); +} + mlir::Attribute ConstantEmitter::tryEmitConstantExpr(const ConstantExpr *ce) { if (!ce->hasAPValueResult()) return {}; diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp index 940a0cb616b27..5977f8c585e26 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp @@ -400,6 +400,11 @@ class ScalarExprEmitter : public StmtVisitor { mlir::Value VisitExtVectorElementExpr(Expr *e) { return emitLoadOfLValue(e); } + mlir::Value VisitMatrixElementExpr(Expr *e) { + cgf.cgm.errorNYI(e->getSourceRange(), "ScalarExprEmitter: matrix element"); + return {}; + } + mlir::Value VisitMemberExpr(MemberExpr *e); mlir::Value VisitCompoundLiteralExpr(CompoundLiteralExpr *e) { @@ -792,8 +797,13 @@ class ScalarExprEmitter : public StmtVisitor { else operand = Visit(e->getSubExpr()); - bool nsw = - kind == cir::UnaryOpKind::Minus && e->getType()->isSignedIntegerType(); + // TODO(cir): We might have to change this to support overflow trapping. + // Classic codegen routes unary minus through emitSub to ensure + // that the overflow behavior is handled correctly. + bool nsw = kind == cir::UnaryOpKind::Minus && + e->getType()->isSignedIntegerType() && + cgf.getLangOpts().getSignedOverflowBehavior() != + LangOptions::SOB_Defined; // NOTE: LLVM codegen will lower this directly to either a FNeg // or a Sub instruction. In CIR this will be handled later in LowerToLLVM. @@ -2137,22 +2147,7 @@ mlir::Value ScalarExprEmitter::VisitCastExpr(CastExpr *ce) { return cgf.cgm.emitNullConstant(destTy, cgf.getLoc(subExpr->getExprLoc())); } - - clang::QualType srcTy = subExpr->IgnoreImpCasts()->getType(); - if (srcTy->isPointerType() || srcTy->isReferenceType()) - srcTy = srcTy->getPointeeType(); - - clang::LangAS srcLangAS = srcTy.getAddressSpace(); - cir::TargetAddressSpaceAttr subExprAS; - if (clang::isTargetAddressSpace(srcLangAS)) - subExprAS = cir::toCIRTargetAddressSpace(cgf.getMLIRContext(), srcLangAS); - else - cgf.cgm.errorNYI(subExpr->getSourceRange(), - "non-target address space conversion"); - // Since target may map different address spaces in AST to the same address - // space, an address space conversion may end up as a bitcast. - return cgf.cgm.getTargetCIRGenInfo().performAddrSpaceCast( - cgf, Visit(subExpr), subExprAS, convertType(destTy)); + return cgf.performAddrSpaceCast(Visit(subExpr), convertType(destTy)); } case CK_AtomicToNonAtomic: { diff --git a/clang/lib/CIR/CodeGen/CIRGenFunction.cpp b/clang/lib/CIR/CodeGen/CIRGenFunction.cpp index f2d73720a9c2b..c900797e54c81 100644 --- a/clang/lib/CIR/CodeGen/CIRGenFunction.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenFunction.cpp @@ -748,7 +748,7 @@ cir::FuncOp CIRGenFunction::generateCode(clang::GlobalDecl gd, cir::FuncOp fn, emitConstructorBody(args); } else if (getLangOpts().CUDA && !getLangOpts().CUDAIsDevice && funcDecl->hasAttr()) { - getCIRGenModule().errorNYI(bodyRange, "CUDA kernel"); + cgm.getCUDARuntime().emitDeviceStub(*this, fn, args); } else if (isa(funcDecl) && cast(funcDecl)->isLambdaStaticInvoker()) { // The lambda static invoker function is special, because it forwards or diff --git a/clang/lib/CIR/CodeGen/CIRGenFunction.h b/clang/lib/CIR/CodeGen/CIRGenFunction.h index adcf4d56e3892..d25c6c941360f 100644 --- a/clang/lib/CIR/CodeGen/CIRGenFunction.h +++ b/clang/lib/CIR/CodeGen/CIRGenFunction.h @@ -1269,6 +1269,8 @@ class CIRGenFunction : public CIRGenTypeCache { bool getAArch64SVEProcessedOperands(unsigned builtinID, const CallExpr *expr, SmallVectorImpl &ops, clang::SVETypeFlags typeFlags); + mlir::Value emitSVEPredicateCast(mlir::Value pred, unsigned minNumElts, + mlir::Location loc); std::optional emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, ReturnValueSlot returnValue, @@ -1802,6 +1804,10 @@ class CIRGenFunction : public CIRGenTypeCache { LValue emitMemberExpr(const MemberExpr *e); + /// Emit a call to an AMDGPU builtin function. + std::optional emitAMDGPUBuiltinExpr(unsigned builtinID, + const CallExpr *expr); + LValue emitOpaqueValueLValue(const OpaqueValueExpr *e); LValue emitConditionalOperatorLValue(const AbstractConditionalOperator *expr); @@ -2065,6 +2071,12 @@ class CIRGenFunction : public CIRGenTypeCache { const Twine &name = "tmp", Address *alloca = nullptr, mlir::OpBuilder::InsertPoint ip = {}); + mlir::Value performAddrSpaceCast(mlir::Value v, mlir::Type destTy) const { + if (cir::GlobalOp globalOp = v.getDefiningOp()) + cgm.errorNYI("Global op addrspace cast"); + return builder.createAddrSpaceCast(v, destTy); + } + //===--------------------------------------------------------------------===// // OpenMP Emission //===--------------------------------------------------------------------===// diff --git a/clang/lib/CIR/CodeGen/CIRGenModule.cpp b/clang/lib/CIR/CodeGen/CIRGenModule.cpp index cf49f44f795b2..508e941517c3d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenModule.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenModule.cpp @@ -11,11 +11,13 @@ //===----------------------------------------------------------------------===// #include "CIRGenModule.h" +#include "CIRGenCUDARuntime.h" #include "CIRGenCXXABI.h" #include "CIRGenConstantEmitter.h" #include "CIRGenFunction.h" #include "clang/AST/ASTContext.h" +#include "clang/AST/ASTLambda.h" #include "clang/AST/DeclBase.h" #include "clang/AST/DeclOpenACC.h" #include "clang/AST/GlobalDecl.h" @@ -28,9 +30,11 @@ #include "clang/CIR/MissingFeatures.h" #include "CIRGenFunctionInfo.h" +#include "TargetInfo.h" #include "mlir/IR/BuiltinOps.h" #include "mlir/IR/Location.h" #include "mlir/IR/MLIRContext.h" +#include "mlir/IR/Operation.h" #include "mlir/IR/Verifier.h" #include @@ -126,6 +130,10 @@ CIRGenModule::CIRGenModule(mlir::MLIRContext &mlirContext, cir::OptInfoAttr::get(&mlirContext, cgo.OptimizationLevel, cgo.OptimizeSize)); + + if (langOpts.CUDA) + createCUDARuntime(); + // Set the module name to be the name of the main file. TranslationUnitDecl // often contains invalid source locations and isn't a reliable source for the // module location. @@ -143,6 +151,10 @@ CIRGenModule::CIRGenModule(mlir::MLIRContext &mlirContext, CIRGenModule::~CIRGenModule() = default; +void CIRGenModule::createCUDARuntime() { + cudaRuntime.reset(createNVCUDARuntime(*this)); +} + /// FIXME: this could likely be a common helper and not necessarily related /// with codegen. /// Return the best known alignment for an unknown pointer to a @@ -242,6 +254,10 @@ const TargetCIRGenInfo &CIRGenModule::getTargetCIRGenInfo() { return *theTargetCIRGenInfo; } } + case llvm::Triple::nvptx: + case llvm::Triple::nvptx64: + theTargetCIRGenInfo = createNVPTXTargetCIRGenInfo(genTypes); + return *theTargetCIRGenInfo; } } @@ -358,6 +374,28 @@ void CIRGenModule::emitDeferred() { } } +template static bool hasImplicitAttr(const ValueDecl *decl) { + if (!decl) + return false; + if (auto *attr = decl->getAttr()) + return attr->isImplicit(); + return decl->isImplicit(); +} + +// TODO(cir): This should be shared with OG Codegen. +bool CIRGenModule::shouldEmitCUDAGlobalVar(const VarDecl *global) const { + assert(langOpts.CUDA && "Should not be called by non-CUDA languages"); + // We need to emit host-side 'shadows' for all global + // device-side variables because the CUDA runtime needs their + // size and host-side address in order to provide access to + // their device-side incarnations. + return !langOpts.CUDAIsDevice || global->hasAttr() || + global->hasAttr() || + global->hasAttr() || + global->getType()->isCUDADeviceBuiltinSurfaceType() || + global->getType()->isCUDADeviceBuiltinTextureType(); +} + void CIRGenModule::emitGlobal(clang::GlobalDecl gd) { if (const auto *cd = dyn_cast(gd.getDecl())) { emitGlobalOpenACCDecl(cd); @@ -372,6 +410,36 @@ void CIRGenModule::emitGlobal(clang::GlobalDecl gd) { const auto *global = cast(gd.getDecl()); + // If this is CUDA, be selective about which declarations we emit. + // Non-constexpr non-lambda implicit host device functions are not emitted + // unless they are used on device side. + if (langOpts.CUDA) { + assert((isa(global) || isa(global)) && + "Expected Variable or Function"); + if (const auto *varDecl = dyn_cast(global)) { + if (!shouldEmitCUDAGlobalVar(varDecl)) + return; + // TODO(cir): This should be shared with OG Codegen. + } else if (langOpts.CUDAIsDevice) { + const auto *functionDecl = dyn_cast(global); + if ((!global->hasAttr() || + (langOpts.OffloadImplicitHostDeviceTemplates && + hasImplicitAttr(functionDecl) && + hasImplicitAttr(functionDecl) && + !functionDecl->isConstexpr() && + !isLambdaCallOperator(functionDecl) && + !getASTContext().CUDAImplicitHostDeviceFunUsedByDevice.count( + functionDecl))) && + !global->hasAttr() && + !(langOpts.HIPStdPar && isa(global) && + !global->hasAttr())) + return; + // Device-only functions are the only things we skip. + } else if (!global->hasAttr() && + global->hasAttr()) + return; + } + if (const auto *fd = dyn_cast(global)) { // Update deferred annotations with the latest declaration if the function // was already used or defined. @@ -1745,6 +1813,15 @@ cir::FuncOp CIRGenModule::getAddrOfFunction(clang::GlobalDecl gd, cir::FuncOp func = getOrCreateCIRFunction(mangledName, funcType, gd, forVTable, dontDefer, /*isThunk=*/false, isForDefinition); + // Returns kernel handle for HIP kernel stub function. + if (langOpts.CUDA && !langOpts.CUDAIsDevice && + cast(gd.getDecl())->hasAttr()) { + mlir::Operation *handle = getCUDARuntime().getKernelHandle(func, gd); + + if (isForDefinition) + return func; + return mlir::dyn_cast(*handle); + } return func; } @@ -1769,9 +1846,15 @@ static std::string getMangledNameImpl(CIRGenModule &cgm, GlobalDecl gd, cgm.errorNYI(nd->getSourceRange(), "getMangledName: X86RegCall"); } else if (fd && fd->hasAttr() && gd.getKernelReferenceKind() == KernelReferenceKind::Stub) { - cgm.errorNYI(nd->getSourceRange(), "getMangledName: CUDA device stub"); + out << "__device_stub__" << ii->getName(); + } else if (fd && + DeviceKernelAttr::isOpenCLSpelling( + fd->getAttr()) && + gd.getKernelReferenceKind() == KernelReferenceKind::Stub) { + cgm.errorNYI(nd->getSourceRange(), "getMangledName: OpenCL Stub"); + } else { + out << ii->getName(); } - out << ii->getName(); } // Check if the module name hash should be appended for internal linkage diff --git a/clang/lib/CIR/CodeGen/CIRGenModule.h b/clang/lib/CIR/CodeGen/CIRGenModule.h index 2f7020a54e607..4444092b58466 100644 --- a/clang/lib/CIR/CodeGen/CIRGenModule.h +++ b/clang/lib/CIR/CodeGen/CIRGenModule.h @@ -14,6 +14,7 @@ #define LLVM_CLANG_LIB_CIR_CODEGEN_CIRGENMODULE_H #include "CIRGenBuilder.h" +#include "CIRGenCUDARuntime.h" #include "CIRGenCall.h" #include "CIRGenTypeCache.h" #include "CIRGenTypes.h" @@ -90,12 +91,17 @@ class CIRGenModule : public CIRGenTypeCache { /// Holds information about C++ vtables. CIRGenVTables vtables; + /// Holds the CUDA runtime + std::unique_ptr cudaRuntime; + /// Per-function codegen information. Updated everytime emitCIR is called /// for FunctionDecls's. CIRGenFunction *curCGF = nullptr; llvm::SmallVector globalScopeAsm; + void createCUDARuntime(); + public: mlir::ModuleOp getModule() const { return theModule; } CIRGenBuilderTy &getBuilder() { return builder; } @@ -277,6 +283,12 @@ class CIRGenModule : public CIRGenTypeCache { cir::CallingConv &callingConv, cir::SideEffect &sideEffect, bool attrOnCallSite, bool isThunk); + /// Helper function for constructAttributeList/others. Builds a set of + /// function attributes to add to a function based on language opts, codegen + /// opts, and some small properties. + void addDefaultFunctionAttributes(StringRef name, bool hasOptNoneAttr, + bool attrOnCallSite, + mlir::NamedAttrList &attrs); /// Will return a global variable of the given type. If a variable with a /// different type already exists then a new variable with the right type @@ -561,6 +573,10 @@ class CIRGenModule : public CIRGenTypeCache { static void setInitializer(cir::GlobalOp &op, mlir::Attribute value); + // Whether a global variable should be emitted by CUDA/HIP host/device + // related attributes. + bool shouldEmitCUDAGlobalVar(const VarDecl *global) const; + void replaceUsesOfNonProtoTypeWithRealFunction(mlir::Operation *old, cir::FuncOp newFn); @@ -597,6 +613,11 @@ class CIRGenModule : public CIRGenTypeCache { /// Function* for "fabsf". cir::FuncOp getBuiltinLibFunction(const FunctionDecl *fd, unsigned builtinID); + CIRGenCUDARuntime &getCUDARuntime() { + assert(cudaRuntime != nullptr); + return *cudaRuntime; + } + mlir::IntegerAttr getSize(CharUnits size) { return builder.getSizeFromCharUnits(size); } diff --git a/clang/lib/CIR/CodeGen/CIRGenStmtOpenMP.cpp b/clang/lib/CIR/CodeGen/CIRGenStmtOpenMP.cpp index ee25f7caec619..0d3b44db98307 100644 --- a/clang/lib/CIR/CodeGen/CIRGenStmtOpenMP.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenStmtOpenMP.cpp @@ -14,7 +14,7 @@ #include "CIRGenFunction.h" #include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "clang/AST/StmtOpenMP.h" - +#include "llvm/Frontend/OpenMP/OMPConstants.h" using namespace clang; using namespace clang::CIRGen; @@ -53,9 +53,13 @@ CIRGenFunction::emitOMPParallelDirective(const OMPParallelDirective &s) { if (s.getTaskReductionRefExpr()) getCIRGenModule().errorNYI(s.getBeginLoc(), "OpenMP Parallel with Task Reduction"); - - res = emitStmt(s.getAssociatedStmt(), /*useCurrentScope=*/true); - + // Don't lower the captured statement directly since this will be + // special-cased depending on the kind of OpenMP directive that is the + // parent, also the non-OpenMP context captured statements lowering does + // not apply directly. + const CapturedStmt *cs = s.getCapturedStmt(llvm::omp::OMPD_parallel); + const Stmt *bodyStmt = cs->getCapturedStmt(); + res = emitStmt(bodyStmt, /*useCurrentScope=*/true); mlir::omp::TerminatorOp::create(builder, end); } return res; diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp index e6ce39cf9571f..c4f745b492102 100644 --- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp @@ -374,6 +374,10 @@ mlir::Type CIRGenTypes::convertType(QualType type) { resultType = cir::VectorType::get(builder.getDoubleTy(), 2, /*is_scalable=*/true); break; + case BuiltinType::SveBool: + resultType = cir::VectorType::get(builder.getUIntNTy(1), 16, + /*is_scalable=*/true); + break; // Unsigned integral types. case BuiltinType::Char8: diff --git a/clang/lib/CIR/CodeGen/CIRGenerator.cpp b/clang/lib/CIR/CodeGen/CIRGenerator.cpp index 8c5d81bd61505..6453f3565c33d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenerator.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenerator.cpp @@ -149,9 +149,22 @@ void CIRGenerator::HandleTagDeclDefinition(TagDecl *d) { // inline initializers as definitions. if (astContext->getTargetInfo().getCXXABI().isMicrosoft()) cgm->errorNYI(d->getSourceRange(), "HandleTagDeclDefinition: MSABI"); - // For OpenMP emit declare reduction functions, if required. - if (astContext->getLangOpts().OpenMP) - cgm->errorNYI(d->getSourceRange(), "HandleTagDeclDefinition: OpenMP"); + + // For OpenMP emit declare reduction functions or declare mapper, if + // required. + if (astContext->getLangOpts().OpenMP) { + for (Decl *member : d->decls()) { + if (auto *drd = dyn_cast(member)) { + if (astContext->DeclMustBeEmitted(drd)) + cgm->errorNYI(d->getSourceRange(), + "HandleTagDeclDefinition: OMPDeclareReductionDecl"); + } else if (auto *dmd = dyn_cast(member)) { + if (astContext->DeclMustBeEmitted(dmd)) + cgm->errorNYI(d->getSourceRange(), + "HandleTagDeclDefinition: OMPDeclareMapperDecl"); + } + } + } } void CIRGenerator::HandleTagDeclRequiredDefinition(const TagDecl *D) { diff --git a/clang/lib/CIR/CodeGen/CMakeLists.txt b/clang/lib/CIR/CodeGen/CMakeLists.txt index 8efa587f31aac..f982fcf5b1b8a 100644 --- a/clang/lib/CIR/CodeGen/CMakeLists.txt +++ b/clang/lib/CIR/CodeGen/CMakeLists.txt @@ -13,11 +13,14 @@ add_clang_library(clangCIR CIRGenBuilder.cpp CIRGenBuiltin.cpp CIRGenBuiltinAArch64.cpp + CIRGenBuiltinAMDGPU.cpp CIRGenBuiltinX86.cpp CIRGenCall.cpp CIRGenClass.cpp CIRGenCleanup.cpp CIRGenCoroutine.cpp + CIRGenCUDANV.cpp + CIRGenCUDARuntime.cpp CIRGenCXX.cpp CIRGenCXXABI.cpp CIRGenDecl.cpp diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp b/clang/lib/CIR/CodeGen/TargetInfo.cpp index 377c532e492d9..5a0c854db9125 100644 --- a/clang/lib/CIR/CodeGen/TargetInfo.cpp +++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp @@ -56,6 +56,25 @@ class X8664TargetCIRGenInfo : public TargetCIRGenInfo { } // namespace +namespace { + +class NVPTXABIInfo : public ABIInfo { +public: + NVPTXABIInfo(CIRGenTypes &cgt) : ABIInfo(cgt) {} +}; + +class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo { +public: + NVPTXTargetCIRGenInfo(CIRGenTypes &cgt) + : TargetCIRGenInfo(std::make_unique(cgt)) {} +}; +} // namespace + +std::unique_ptr +clang::CIRGen::createNVPTXTargetCIRGenInfo(CIRGenTypes &cgt) { + return std::make_unique(cgt); +} + std::unique_ptr clang::CIRGen::createX8664TargetCIRGenInfo(CIRGenTypes &cgt) { return std::make_unique(cgt); @@ -71,14 +90,3 @@ bool TargetCIRGenInfo::isNoProtoCallVariadic( // For everything else, we just prefer false unless we opt out. return false; } - -mlir::Value TargetCIRGenInfo::performAddrSpaceCast( - CIRGenFunction &cgf, mlir::Value v, cir::TargetAddressSpaceAttr srcAddr, - mlir::Type destTy, bool isNonNull) const { - // Since target may map different address spaces in AST to the same address - // space, an address space conversion may end up as a bitcast. - if (cir::GlobalOp globalOp = v.getDefiningOp()) - cgf.cgm.errorNYI("Global op addrspace cast"); - // Try to preserve the source's name to make IR more readable. - return cgf.getBuilder().createAddrSpaceCast(v, destTy); -} diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h b/clang/lib/CIR/CodeGen/TargetInfo.h index 9535ba94fb08b..79325c2d35c4d 100644 --- a/clang/lib/CIR/CodeGen/TargetInfo.h +++ b/clang/lib/CIR/CodeGen/TargetInfo.h @@ -51,15 +51,6 @@ class TargetCIRGenInfo { virtual cir::TargetAddressSpaceAttr getCIRAllocaAddressSpace() const { return {}; } - /// Perform address space cast of an expression of pointer type. - /// \param V is the value to be casted to another address space. - /// \param DestTy is the destination pointer type. - /// \param srcAS is theaddress space of \p V. - /// \param IsNonNull is the flag indicating \p V is known to be non null. - virtual mlir::Value performAddrSpaceCast(CIRGenFunction &cgf, mlir::Value v, - cir::TargetAddressSpaceAttr srcAddr, - mlir::Type destTy, - bool isNonNull = false) const; /// Determine whether a call to an unprototyped functions under /// the given calling convention should use the variadic @@ -124,6 +115,8 @@ class TargetCIRGenInfo { std::unique_ptr createX8664TargetCIRGenInfo(CIRGenTypes &cgt); +std::unique_ptr createNVPTXTargetCIRGenInfo(CIRGenTypes &cgt); + } // namespace clang::CIRGen #endif // LLVM_CLANG_LIB_CIR_TARGETINFO_H diff --git a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp index a5b3dbe3ecb91..9574851a0ae2c 100644 --- a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp +++ b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp @@ -302,7 +302,6 @@ void cir::AllocaOp::build(mlir::OpBuilder &odsBuilder, //===----------------------------------------------------------------------===// LogicalResult cir::BreakOp::verify() { - assert(!cir::MissingFeatures::switchOp()); if (!getOperation()->getParentOfType() && !getOperation()->getParentOfType()) return emitOpError("must be within a loop"); @@ -1306,6 +1305,49 @@ LogicalResult cir::ScopeOp::fold(FoldAdaptor /*adaptor*/, return success(); } +//===----------------------------------------------------------------------===// +// CleanupScopeOp +//===----------------------------------------------------------------------===// + +void cir::CleanupScopeOp::getSuccessorRegions( + mlir::RegionBranchPoint point, SmallVectorImpl ®ions) { + if (!point.isParent()) { + regions.push_back(RegionSuccessor::parent()); + return; + } + + // Execution always proceeds from the body region to the cleanup region. + regions.push_back(RegionSuccessor(&getBodyRegion())); + regions.push_back(RegionSuccessor(&getCleanupRegion())); +} + +mlir::ValueRange +cir::CleanupScopeOp::getSuccessorInputs(RegionSuccessor successor) { + return ValueRange(); +} + +void cir::CleanupScopeOp::build( + OpBuilder &builder, OperationState &result, CleanupKind cleanupKind, + function_ref bodyBuilder, + function_ref cleanupBuilder) { + result.addAttribute(getCleanupKindAttrName(result.name), + CleanupKindAttr::get(builder.getContext(), cleanupKind)); + + OpBuilder::InsertionGuard guard(builder); + + // Build body region. + Region *bodyRegion = result.addRegion(); + builder.createBlock(bodyRegion); + if (bodyBuilder) + bodyBuilder(builder, result.location); + + // Build cleanup region. + Region *cleanupRegion = result.addRegion(); + builder.createBlock(cleanupRegion); + if (cleanupBuilder) + cleanupBuilder(builder, result.location); +} + //===----------------------------------------------------------------------===// // BrOp //===----------------------------------------------------------------------===// @@ -3838,6 +3880,148 @@ cir::EhTypeIdOp::verifySymbolUses(SymbolTableCollection &symbolTable) { return success(); } +//===----------------------------------------------------------------------===// +// EhDispatchOp +//===----------------------------------------------------------------------===// + +static ParseResult +parseEhDispatchDestinations(OpAsmParser &parser, mlir::ArrayAttr &catchTypes, + SmallVectorImpl &catchDestinations, + Block *&defaultDestination, + mlir::UnitAttr &defaultIsCatchAll) { + // Parse: [ ... ] + if (parser.parseLSquare()) + return failure(); + + SmallVector handlerTypes; + bool hasCatchAll = false; + bool hasUnwind = false; + + // Parse handler list. + auto parseHandler = [&]() -> ParseResult { + // Check for 'catch_all' or 'unwind' keywords. + if (succeeded(parser.parseOptionalKeyword("catch_all"))) { + if (hasCatchAll) + return parser.emitError(parser.getCurrentLocation(), + "duplicate 'catch_all' handler"); + if (hasUnwind) + return parser.emitError(parser.getCurrentLocation(), + "cannot have both 'catch_all' and 'unwind'"); + hasCatchAll = true; + + if (parser.parseColon().failed()) + return failure(); + + if (parser.parseSuccessor(defaultDestination).failed()) + return failure(); + + return success(); + } + + if (succeeded(parser.parseOptionalKeyword("unwind"))) { + if (hasUnwind) + return parser.emitError(parser.getCurrentLocation(), + "duplicate 'unwind' handler"); + if (hasCatchAll) + return parser.emitError(parser.getCurrentLocation(), + "cannot have both 'catch_all' and 'unwind'"); + hasUnwind = true; + + if (parser.parseColon().failed()) + return failure(); + + if (parser.parseSuccessor(defaultDestination).failed()) + return failure(); + return success(); + } + + // Otherwise, expect 'catch( : ) : ^block'. + // The 'catch(...)' wrapper allows the attribute to include its type + // without conflicting with the ':' used for the block destination. + if (parser.parseKeyword("catch").failed()) + return failure(); + + if (parser.parseLParen().failed()) + return failure(); + + mlir::Attribute catchTypeAttr; + if (parser.parseAttribute(catchTypeAttr).failed()) + return failure(); + handlerTypes.push_back(catchTypeAttr); + + if (parser.parseRParen().failed()) + return failure(); + + if (parser.parseColon().failed()) + return failure(); + + Block *dest; + if (parser.parseSuccessor(dest).failed()) + return failure(); + catchDestinations.push_back(dest); + return success(); + }; + + if (parser.parseCommaSeparatedList(parseHandler).failed()) + return failure(); + + if (parser.parseRSquare().failed()) + return failure(); + + // Verify we have catch_all or unwind. + if (!hasCatchAll && !hasUnwind) + return parser.emitError(parser.getCurrentLocation(), + "must have either 'catch_all' or 'unwind' handler"); + + // Add attributes and successors. + if (!handlerTypes.empty()) + catchTypes = parser.getBuilder().getArrayAttr(handlerTypes); + + if (hasCatchAll) + defaultIsCatchAll = parser.getBuilder().getUnitAttr(); + + return success(); +} + +static void printEhDispatchDestinations(OpAsmPrinter &p, cir::EhDispatchOp op, + mlir::ArrayAttr catchTypes, + SuccessorRange catchDestinations, + Block *defaultDestination, + mlir::UnitAttr defaultIsCatchAll) { + p << " ["; + p.printNewline(); + + // If we have at least one catch type, print them. + if (catchTypes) { + // Print type handlers using 'catch() : ^block' syntax. + llvm::interleave( + llvm::zip(catchTypes, catchDestinations), + [&](auto i) { + p << " catch("; + p.printAttribute(std::get<0>(i)); + p << ") : "; + p.printSuccessor(std::get<1>(i)); + }, + [&] { + p << ','; + p.printNewline(); + }); + + p << ", "; + p.printNewline(); + } + + // Print catch_all or unwind handler. + if (defaultIsCatchAll) + p << " catch_all : "; + else + p << " unwind : "; + p.printSuccessor(defaultDestination); + p.printNewline(); + + p << "]"; +} + //===----------------------------------------------------------------------===// // TableGen'd op method definitions //===----------------------------------------------------------------------===// diff --git a/clang/lib/CIR/Dialect/Transforms/CMakeLists.txt b/clang/lib/CIR/Dialect/Transforms/CMakeLists.txt index 34d95a92c3bfe..1ace2d8634b40 100644 --- a/clang/lib/CIR/Dialect/Transforms/CMakeLists.txt +++ b/clang/lib/CIR/Dialect/Transforms/CMakeLists.txt @@ -4,6 +4,7 @@ add_clang_library(MLIRCIRTransforms CIRCanonicalize.cpp CIRSimplify.cpp CXXABILowering.cpp + TargetLowering.cpp FlattenCFG.cpp HoistAllocas.cpp LoweringPrepare.cpp diff --git a/clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp b/clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp index f0e473a6574c7..cc6a6544a529a 100644 --- a/clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp +++ b/clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp @@ -453,21 +453,18 @@ populateCXXABIConversionTarget(mlir::ConversionTarget &target, //===----------------------------------------------------------------------===// void CXXABILoweringPass::runOnOperation() { - auto module = mlir::cast(getOperation()); - mlir::MLIRContext *ctx = module.getContext(); - - // If the triple is not present, e.g. CIR modules parsed from text, we - // cannot init LowerModule properly. - assert(!cir::MissingFeatures::makeTripleAlwaysPresent()); - // If no target triple is available, skip the ABI lowering pass. - if (!module->hasAttr(cir::CIRDialect::getTripleAttrName())) + auto mod = mlir::cast(getOperation()); + mlir::MLIRContext *ctx = mod.getContext(); + + std::unique_ptr lowerModule = cir::createLowerModule(mod); + // If lower module is not available, skip the ABI lowering pass. + if (!lowerModule) { + mod.emitWarning("Cannot create a CIR lower module, skipping the ") + << getName() << " pass"; return; + } - mlir::PatternRewriter rewriter(ctx); - std::unique_ptr lowerModule = - cir::createLowerModule(module, rewriter); - - mlir::DataLayout dataLayout(module); + mlir::DataLayout dataLayout(mod); mlir::TypeConverter typeConverter; prepareCXXABITypeConverter(typeConverter, dataLayout, *lowerModule); @@ -483,7 +480,7 @@ void CXXABILoweringPass::runOnOperation() { mlir::ConversionTarget target(*ctx); populateCXXABIConversionTarget(target, typeConverter); - if (failed(mlir::applyPartialConversion(module, target, std::move(patterns)))) + if (failed(mlir::applyPartialConversion(mod, target, std::move(patterns)))) signalPassFailure(); } diff --git a/clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp b/clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp index 8c674065a3b35..62802ba146686 100644 --- a/clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp +++ b/clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp @@ -22,6 +22,7 @@ #include "clang/CIR/Dialect/IR/CIRDialect.h" #include "clang/CIR/Dialect/Passes.h" #include "clang/CIR/MissingFeatures.h" +#include "llvm/ADT/TypeSwitch.h" using namespace mlir; using namespace cir; @@ -176,6 +177,144 @@ class CIRScopeOpFlattening : public mlir::OpRewritePattern { } }; +// TODO(cir): Move CleanupExit and collectExits into +// CIRCleanupScopeOpFlattening after multi-exit handling is implemented. +// They're here for now so that we can use them to emit errors for the +// not-yet-implemented multi-exit case. + +struct CleanupExit { + // An operation that exits the cleanup scope (yield, break, continue, + // return, etc.) + mlir::Operation *exitOp; + + // A unique identifier for this exit's destination (used for switch dispatch + // when there are multiple exits). + int destinationId; + + CleanupExit(mlir::Operation *op, int id) : exitOp(op), destinationId(id) {} +}; + +// Collect all operations that exit a cleanup scope body. Return, goto, break, +// and continue can all require branches through the cleanup region. When a loop +// is encountered, only return and goto are collected because break and continue +// are handled by the loop and stay within the cleanup scope. When a switch is +// encountered, return, goto and continue are collected because they may all +// branch through the cleanup, but break is local to the switch. When a nested +// cleanup scope is encountered, we recursively collect exits since any return, +// goto, break, or continue from the nested cleanup will also branch through the +// outer cleanup. +// +// Note that goto statements may not necessarily exit the cleanup scope, but +// for now we conservatively assume that they do. We'll need more nuanced +// handling of that when multi-exit flattening is implemented. +// +// This function assigns unique destination IDs to each exit, which will be used +// when multi-exit flattening is implemented. +static void collectExits(mlir::Region &cleanupBodyRegion, + llvm::SmallVectorImpl &exits, + int &nextId) { + // Collect yield terminators from the body region. We do this separately + // because yields in nested operations, including those in nested cleanup + // scopes, won't branch through the outer cleanup region. + for (mlir::Block &block : cleanupBodyRegion) { + auto *terminator = block.getTerminator(); + if (isa(terminator)) + exits.emplace_back(terminator, nextId++); + } + + // Lambda to walk a loop and collect only returns and gotos. + // Break and continue inside loops are handled by the loop itself. + // Loops don't require special handling for nested switch or cleanup scopes + // because break and continue never branch out of the loop. + auto collectExitsInLoop = [&](mlir::Operation *loopOp) { + loopOp->walk([&](mlir::Operation *nestedOp) { + if (isa(nestedOp)) + exits.emplace_back(nestedOp, nextId++); + return mlir::WalkResult::advance(); + }); + }; + + // Forward declaration for mutual recursion. + std::function collectExitsInCleanup; + std::function collectExitsInSwitch; + + // Lambda to collect exits from a switch. Collects return/goto/continue but + // not break (handled by switch). For nested loops/cleanups, recurses. + collectExitsInSwitch = [&](mlir::Operation *switchOp) { + switchOp->walk([&](mlir::Operation *nestedOp) { + if (isa(nestedOp)) { + // Walk the nested cleanup, but ignore break statements because they + // will be handled by the switch we are currently walking. + collectExitsInCleanup( + cast(nestedOp).getBodyRegion(), + /*ignoreBreak=*/true); + return mlir::WalkResult::skip(); + } else if (isa(nestedOp)) { + collectExitsInLoop(nestedOp); + return mlir::WalkResult::skip(); + } else if (isa(nestedOp)) { + exits.emplace_back(nestedOp, nextId++); + } + return mlir::WalkResult::advance(); + }); + }; + + // Lambda to collect exits from a cleanup scope body region. This collects + // break (optionally), continue, return, and goto, handling nested loops, + // switches, and cleanups appropriately. + collectExitsInCleanup = [&](mlir::Region ®ion, bool ignoreBreak) { + region.walk([&](mlir::Operation *op) { + // We need special handling for break statements because if this cleanup + // scope was nested within a switch op, break will be handled by the + // switch operation and therefore won't exit the cleanup scope enclosing + // the switch. We're only collecting exits from the cleanup that started + // this walk. Exits from nested cleanups will be handled when we flatten + // the nested cleanup. + if (!ignoreBreak && isa(op)) { + exits.emplace_back(op, nextId++); + } else if (isa(op)) { + exits.emplace_back(op, nextId++); + } else if (isa(op)) { + // Recurse into nested cleanup's body region. + collectExitsInCleanup(cast(op).getBodyRegion(), + /*ignoreBreak=*/ignoreBreak); + return mlir::WalkResult::skip(); + } else if (isa(op)) { + // This kicks off a separate walk rather than continuing to dig deeper + // in the current walk because we need to handle break and continue + // differently inside loops. + collectExitsInLoop(op); + return mlir::WalkResult::skip(); + } else if (isa(op)) { + // This kicks off a separate walk rather than continuing to dig deeper + // in the current walk because we need to handle break differently + // inside switches. + collectExitsInSwitch(op); + return mlir::WalkResult::skip(); + } + return mlir::WalkResult::advance(); + }); + }; + + // Collect exits from the body region. + collectExitsInCleanup(cleanupBodyRegion, /*ignoreBreak=*/false); +} + +// Check if this operation is within a cleanup scope or contains a cleanup +// scope with multiple exits. Either of these are unimplemented conditions and +// should trigger an error for now. This is a temporary check that is only +// needed until multi-exit cleanup flattening is implemented. +static bool enclosedByCleanupScopeWithMultipleExits(mlir::Operation *op) { + int nextId = 0; + cir::CleanupScopeOp cleanupParent = + op->getParentOfType(); + if (!cleanupParent) + return false; + llvm::SmallVector exits; + collectExits(cleanupParent.getBodyRegion(), exits, nextId); + return exits.size() > 1; +} + class CIRSwitchOpFlattening : public mlir::OpRewritePattern { public: using OpRewritePattern::OpRewritePattern; @@ -226,6 +365,22 @@ class CIRSwitchOpFlattening : public mlir::OpRewritePattern { mlir::LogicalResult matchAndRewrite(cir::SwitchOp op, mlir::PatternRewriter &rewriter) const override { + // Cleanup scopes must be lowered before the enclosing switch so that + // break inside them is properly routed through cleanup. + // Fail the match so the pattern rewriter will process cleanup scopes first. + bool hasNestedCleanup = op->walk([&](cir::CleanupScopeOp) { + return mlir::WalkResult::interrupt(); + }).wasInterrupted(); + if (hasNestedCleanup) + return mlir::failure(); + + // Don't flatten switches that contain cleanup scopes with multiple exits + // (break/continue/return/goto). Those cleanup scopes need multi-exit + // handling (destination slot + switch dispatch) which is not yet + // implemented. + if (enclosedByCleanupScopeWithMultipleExits(op)) + return op->emitError("cannot lower switch: cleanup with multiple exits"); + llvm::SmallVector cases; op.collectCases(cases); @@ -421,6 +576,21 @@ class CIRLoopOpInterfaceFlattening mlir::LogicalResult matchAndRewrite(cir::LoopOpInterface op, mlir::PatternRewriter &rewriter) const final { + // Cleanup scopes must be lowered before the enclosing loop so that + // break/continue inside them are properly routed through cleanup. + // Fail the match so the pattern rewriter will process cleanup scopes first. + bool hasNestedCleanup = false; + op->walk([&](cir::CleanupScopeOp) { hasNestedCleanup = true; }); + if (hasNestedCleanup) + return mlir::failure(); + + // Don't flatten loops that contain cleanup scopes with multiple exits + // (break/continue/return/goto). Those cleanup scopes need multi-exit + // handling (destination slot + switch dispatch) which is not yet + // implemented. + if (enclosedByCleanupScopeWithMultipleExits(op)) + return op->emitError("cannot lower loop: cleanup with multiple exits"); + // Setup CFG blocks. mlir::Block *entry = rewriter.getInsertionBlock(); mlir::Block *exit = @@ -453,8 +623,7 @@ class CIRLoopOpInterfaceFlattening }); // Lower break statements. - assert(!cir::MissingFeatures::switchOp()); - walkRegionSkipping( + walkRegionSkipping( op.getBody(), [&](mlir::Operation *op) { if (!isa(op)) return mlir::WalkResult::advance(); @@ -556,6 +725,157 @@ class CIRTernaryOpFlattening : public mlir::OpRewritePattern { } }; +class CIRCleanupScopeOpFlattening + : public mlir::OpRewritePattern { +public: + using OpRewritePattern::OpRewritePattern; + + // Flatten a cleanup scope with a single exit destination. + // The body region's exit branches to the cleanup block, the cleanup block + // branches to a cleanup exit block whose contents depend on the type of + // operation that exited the body region. Yield becomes a branch to the + // block after the cleanup scope, break and continue are preserved + // for later lowering by enclosing switch or loop. Return is preserved as is. + mlir::LogicalResult + flattenSimpleCleanup(cir::CleanupScopeOp cleanupOp, mlir::Operation *exitOp, + mlir::PatternRewriter &rewriter) const { + mlir::Location loc = cleanupOp.getLoc(); + + // Get references to region blocks before inlining. + mlir::Block *bodyEntry = &cleanupOp.getBodyRegion().front(); + mlir::Block *cleanupEntry = &cleanupOp.getCleanupRegion().front(); + mlir::Block *cleanupExit = &cleanupOp.getCleanupRegion().back(); + + auto cleanupYield = dyn_cast(cleanupExit->getTerminator()); + if (!cleanupYield) { + return rewriter.notifyMatchFailure(cleanupOp, + "Not yet implemented: cleanup region " + "terminated with non-yield operation"); + } + + // Split the current block to create the insertion point. + mlir::Block *currentBlock = rewriter.getInsertionBlock(); + mlir::Block *continueBlock = + rewriter.splitBlock(currentBlock, rewriter.getInsertionPoint()); + + // Inline the body region. + rewriter.inlineRegionBefore(cleanupOp.getBodyRegion(), continueBlock); + + // Inline the cleanup region after the body. + rewriter.inlineRegionBefore(cleanupOp.getCleanupRegion(), continueBlock); + + // Branch from current block to body entry. + rewriter.setInsertionPointToEnd(currentBlock); + cir::BrOp::create(rewriter, loc, bodyEntry); + + // Create a block for the exit terminator (after cleanup, before continue). + mlir::Block *exitBlock = rewriter.createBlock(continueBlock); + + // Rewrite the cleanup region's yield to branch to exit block. + rewriter.setInsertionPoint(cleanupYield); + rewriter.replaceOpWithNewOp(cleanupYield, exitBlock); + + // Put the appropriate terminator in the exit block. + rewriter.setInsertionPointToEnd(exitBlock); + mlir::LogicalResult result = + llvm::TypeSwitch(exitOp) + .Case([&](auto) { + // Yield becomes a branch to continue block. + cir::BrOp::create(rewriter, loc, continueBlock); + return mlir::success(); + }) + .Case([&](auto) { + // Break is preserved for later lowering by enclosing switch/loop. + cir::BreakOp::create(rewriter, loc); + return mlir::success(); + }) + .Case([&](auto) { + // Continue is preserved for later lowering by enclosing loop. + cir::ContinueOp::create(rewriter, loc); + return mlir::success(); + }) + .Case([&](auto &returnOp) { + // Return from the cleanup exit. Note, if this is a return inside + // a nested cleanup scope, the flattening of the outer scope will + // handle branching through the outer cleanup. + if (returnOp.hasOperand()) + cir::ReturnOp::create(rewriter, loc, returnOp.getOperands()); + else + cir::ReturnOp::create(rewriter, loc); + return mlir::success(); + }) + .Case([&](auto &gotoOp) { + // Correct goto handling requires determining whether the goto + // branches out of the cleanup scope or stays within it. + // Although the goto necessarily exits the cleanup scope in the + // case where it is the only exit from the scope, it is left + // as unimplemented for now so that it can be generalized when + // multi-exit flattening is implemented. + cir::UnreachableOp::create(rewriter, loc); + return gotoOp.emitError( + "goto in cleanup scope is not yet implemented"); + }) + .Default([&](mlir::Operation *op) { + cir::UnreachableOp::create(rewriter, loc); + return op->emitError( + "unexpected terminator in cleanup scope body"); + }); + + // Replace body exit with branch to cleanup entry. + rewriter.setInsertionPoint(exitOp); + rewriter.replaceOpWithNewOp(exitOp, cleanupEntry); + + // Erase the original cleanup scope op. + rewriter.eraseOp(cleanupOp); + + return result; + } + + // Flatten a cleanup scope with multiple exit destinations. + // Uses a destination slot and switch dispatch after cleanup. + mlir::LogicalResult + flattenMultiExitCleanup(cir::CleanupScopeOp cleanupOp, + llvm::SmallVectorImpl &exits, + mlir::PatternRewriter &rewriter) const { + // This will implement the destination slot mechanism: + // 1. Allocate a destination slot at function entry + // 2. Each exit stores its destination ID to the slot + // 3. All exits branch to cleanup entry + // 4. Cleanup branches to a dispatch block + // 5. Dispatch block loads slot and switches to correct destination + // + // For now, we report this as a match failure and leave the cleanup scope + // unchanged. The cleanup scope must remain inside its enclosing loop so + // that break/continue ops remain valid. + return cleanupOp->emitError( + "cleanup scope with multiple exits is not yet implemented"); + } + + mlir::LogicalResult + matchAndRewrite(cir::CleanupScopeOp cleanupOp, + mlir::PatternRewriter &rewriter) const override { + mlir::OpBuilder::InsertionGuard guard(rewriter); + + // Only handle normal cleanups for now - EH and "all" cleanups are NYI. + cir::CleanupKind cleanupKind = cleanupOp.getCleanupKind(); + if (cleanupKind != cir::CleanupKind::Normal) + return cleanupOp->emitError( + "EH cleanup flattening is not yet implemented"); + + // Collect all exits from the body region. + llvm::SmallVector exits; + int nextId = 0; + collectExits(cleanupOp.getBodyRegion(), exits, nextId); + + if (exits.size() > 1) + return flattenMultiExitCleanup(cleanupOp, exits, rewriter); + + assert(!exits.empty() && "cleanup scope body has no exit"); + + return flattenSimpleCleanup(cleanupOp, exits[0].exitOp, rewriter); + } +}; + class CIRTryOpFlattening : public mlir::OpRewritePattern { public: using OpRewritePattern::OpRewritePattern; @@ -651,7 +971,8 @@ class CIRTryOpFlattening : public mlir::OpRewritePattern { void populateFlattenCFGPatterns(RewritePatternSet &patterns) { patterns .add( + CIRSwitchOpFlattening, CIRTernaryOpFlattening, + CIRCleanupScopeOpFlattening, CIRTryOpFlattening>( patterns.getContext()); } @@ -662,10 +983,8 @@ void CIRFlattenCFGPass::runOnOperation() { // Collect operations to apply patterns. llvm::SmallVector ops; getOperation()->walk([&](Operation *op) { - assert(!cir::MissingFeatures::ifOp()); - assert(!cir::MissingFeatures::switchOp()); - assert(!cir::MissingFeatures::tryOp()); - if (isa(op)) + if (isa(op)) ops.push_back(op); }); diff --git a/clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp b/clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp new file mode 100644 index 0000000000000..656f29dab4e92 --- /dev/null +++ b/clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp @@ -0,0 +1,68 @@ +//===- TargetLowering.cpp -------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the cir-target-lowering pass. +// +//===----------------------------------------------------------------------===// + +#include "TargetLowering/LowerModule.h" + +#include "mlir/Support/LLVM.h" +#include "clang/CIR/Dialect/Passes.h" +#include "llvm/ADT/TypeSwitch.h" + +using namespace mlir; +using namespace cir; + +namespace mlir { +#define GEN_PASS_DEF_TARGETLOWERING +#include "clang/CIR/Dialect/Passes.h.inc" +} // namespace mlir + +namespace { + +struct TargetLoweringPass + : public impl::TargetLoweringBase { + TargetLoweringPass() = default; + void runOnOperation() override; +}; + +} // namespace + +static void convertSyncScopeIfPresent(mlir::Operation *op, + cir::LowerModule &lowerModule) { + auto syncScopeAttr = + mlir::cast_if_present(op->getAttr("sync_scope")); + if (syncScopeAttr) { + cir::SyncScopeKind convertedSyncScope = + lowerModule.getTargetLoweringInfo().convertSyncScope( + syncScopeAttr.getValue()); + op->setAttr("sync_scope", cir::SyncScopeKindAttr::get(op->getContext(), + convertedSyncScope)); + } +} + +void TargetLoweringPass::runOnOperation() { + auto mod = mlir::cast(getOperation()); + std::unique_ptr lowerModule = cir::createLowerModule(mod); + // If lower module is not available, skip the target lowering pass. + if (!lowerModule) { + mod.emitWarning("Cannot create a CIR lower module, skipping the ") + << getName() << " pass"; + return; + } + + mod->walk([&](mlir::Operation *op) { + if (mlir::isa(op)) + convertSyncScopeIfPresent(op, *lowerModule); + }); +} + +std::unique_ptr mlir::createTargetLoweringPass() { + return std::make_unique(); +} diff --git a/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp b/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp index e39b764f6a838..f2398e3105578 100644 --- a/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp +++ b/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp @@ -14,7 +14,6 @@ #include "LowerModule.h" #include "CIRCXXABI.h" #include "mlir/IR/BuiltinAttributes.h" -#include "mlir/IR/PatternMatch.h" #include "clang/Basic/LangOptions.h" #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" @@ -53,10 +52,8 @@ createTargetLoweringInfo(LowerModule &lm) { LowerModule::LowerModule(clang::LangOptions langOpts, clang::CodeGenOptions codeGenOpts, mlir::ModuleOp &module, - std::unique_ptr target, - mlir::PatternRewriter &rewriter) - : module(module), target(std::move(target)), abi(createCXXABI(*this)), - rewriter(rewriter) {} + std::unique_ptr target) + : module(module), target(std::move(target)), abi(createCXXABI(*this)) {} const TargetLoweringInfo &LowerModule::getTargetLoweringInfo() { if (!targetLoweringInfo) @@ -65,8 +62,13 @@ const TargetLoweringInfo &LowerModule::getTargetLoweringInfo() { } // TODO: not to create it every time -std::unique_ptr -createLowerModule(mlir::ModuleOp module, mlir::PatternRewriter &rewriter) { +std::unique_ptr createLowerModule(mlir::ModuleOp module) { + // If the triple is not present, e.g. CIR modules parsed from text, we + // cannot init LowerModule properly. + assert(!cir::MissingFeatures::makeTripleAlwaysPresent()); + if (!module->hasAttr(cir::CIRDialect::getTripleAttrName())) + return nullptr; + // Fetch target information. llvm::Triple triple(mlir::cast( module->getAttr(cir::CIRDialect::getTripleAttrName())) @@ -94,7 +96,7 @@ createLowerModule(mlir::ModuleOp module, mlir::PatternRewriter &rewriter) { return std::make_unique(std::move(langOpts), std::move(codeGenOpts), module, - std::move(targetInfo), rewriter); + std::move(targetInfo)); } } // namespace cir diff --git a/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.h b/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.h index 560bf87c76c11..ab3a648683279 100644 --- a/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.h +++ b/clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.h @@ -31,12 +31,11 @@ class LowerModule { const std::unique_ptr target; std::unique_ptr targetLoweringInfo; std::unique_ptr abi; - [[maybe_unused]] mlir::PatternRewriter &rewriter; public: LowerModule(clang::LangOptions langOpts, clang::CodeGenOptions codeGenOpts, - mlir::ModuleOp &module, std::unique_ptr target, - mlir::PatternRewriter &rewriter); + mlir::ModuleOp &module, + std::unique_ptr target); ~LowerModule() = default; clang::TargetCXXABI::Kind getCXXABIKind() const { @@ -51,8 +50,7 @@ class LowerModule { const TargetLoweringInfo &getTargetLoweringInfo(); }; -std::unique_ptr createLowerModule(mlir::ModuleOp module, - mlir::PatternRewriter &rewriter); +std::unique_ptr createLowerModule(mlir::ModuleOp module); } // namespace cir diff --git a/clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.cpp b/clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.cpp index b9b756077da04..5ecdb8d587552 100644 --- a/clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.cpp +++ b/clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.cpp @@ -17,9 +17,10 @@ namespace cir { TargetLoweringInfo::~TargetLoweringInfo() = default; -std::string -TargetLoweringInfo::getLLVMSyncScope(cir::SyncScopeKind syncScope) const { - return ""; // default sync scope +cir::SyncScopeKind +TargetLoweringInfo::convertSyncScope(cir::SyncScopeKind syncScope) const { + // By default, targets don't deal with sync scopes other than system scope. + return cir::SyncScopeKind::System; } } // namespace cir diff --git a/clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h b/clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h index 91e7eb79ec83e..760c3b0b7cc5e 100644 --- a/clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h +++ b/clang/lib/CIR/Dialect/Transforms/TargetLowering/TargetLoweringInfo.h @@ -15,7 +15,6 @@ #define LLVM_CLANG_LIB_CIR_DIALECT_TRANSFORMS_TARGETLOWERING_TARGETLOWERINGINFO_H #include "clang/CIR/Dialect/IR/CIROpsEnums.h" -#include namespace cir { @@ -23,7 +22,8 @@ class TargetLoweringInfo { public: virtual ~TargetLoweringInfo(); - virtual std::string getLLVMSyncScope(cir::SyncScopeKind syncScope) const; + virtual cir::SyncScopeKind + convertSyncScope(cir::SyncScopeKind syncScope) const; }; } // namespace cir diff --git a/clang/lib/CIR/Lowering/CIRPasses.cpp b/clang/lib/CIR/Lowering/CIRPasses.cpp index 72348ff6287b4..589c2c524c305 100644 --- a/clang/lib/CIR/Lowering/CIRPasses.cpp +++ b/clang/lib/CIR/Lowering/CIRPasses.cpp @@ -31,6 +31,7 @@ mlir::LogicalResult runCIRToCIRPasses(mlir::ModuleOp theModule, if (enableCIRSimplify) pm.addPass(mlir::createCIRSimplifyPass()); + pm.addPass(mlir::createTargetLoweringPass()); pm.addPass(mlir::createCXXABILoweringPass()); pm.addPass(mlir::createLoweringPreparePass(&astContext)); diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt b/clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt index 2525e02ae8f85..c7467fe40ba30 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt +++ b/clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt @@ -21,6 +21,7 @@ add_clang_library(clangCIRLoweringDirectToLLVM MLIRCIRTargetLowering MLIRBuiltinToLLVMIRTranslation MLIRLLVMToLLVMIRTranslation + MLIROpenMPToLLVMIRTranslation MLIRIR ) diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp index 0e50d9c595564..6ac32cade4576 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp @@ -29,6 +29,7 @@ #include "mlir/Pass/PassManager.h" #include "mlir/Target/LLVMIR/Dialect/Builtin/BuiltinToLLVMIRTranslation.h" #include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h" +#include "mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h" #include "mlir/Target/LLVMIR/Export.h" #include "mlir/Transforms/DialectConversion.h" #include "clang/CIR/Dialect/IR/CIRAttrs.h" @@ -196,6 +197,15 @@ mlir::LogicalResult CIRToLLVMMemCpyOpLowering::matchAndRewrite( return mlir::success(); } +mlir::LogicalResult CIRToLLVMMemSetOpLowering::matchAndRewrite( + cir::MemSetOp op, OpAdaptor adaptor, + mlir::ConversionPatternRewriter &rewriter) const { + rewriter.replaceOpWithNewOp( + op, adaptor.getDst(), adaptor.getVal(), adaptor.getLen(), + /*isVolatile=*/false); + return mlir::success(); +} + mlir::LogicalResult CIRToLLVMSqrtOpLowering::matchAndRewrite( cir::SqrtOp op, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const { @@ -259,10 +269,8 @@ class CIRAttrToValue { public: CIRAttrToValue(mlir::Operation *parentOp, mlir::ConversionPatternRewriter &rewriter, - const mlir::TypeConverter *converter, - cir::LowerModule *lowerMod) - : parentOp(parentOp), rewriter(rewriter), converter(converter), - lowerMod(lowerMod) {} + const mlir::TypeConverter *converter) + : parentOp(parentOp), rewriter(rewriter), converter(converter) {} mlir::Value visit(mlir::Attribute attr) { return llvm::TypeSwitch(attr) @@ -291,16 +299,14 @@ class CIRAttrToValue { mlir::Operation *parentOp; mlir::ConversionPatternRewriter &rewriter; const mlir::TypeConverter *converter; - [[maybe_unused]] cir::LowerModule *lowerMod; }; /// Switches on the type of attribute and calls the appropriate conversion. mlir::Value lowerCirAttrAsValue(mlir::Operation *parentOp, const mlir::Attribute attr, mlir::ConversionPatternRewriter &rewriter, - const mlir::TypeConverter *converter, - cir::LowerModule *lowerMod) { - CIRAttrToValue valueConverter(parentOp, rewriter, converter, lowerMod); + const mlir::TypeConverter *converter) { + CIRAttrToValue valueConverter(parentOp, rewriter, converter); mlir::Value value = valueConverter.visit(attr); if (!value) llvm_unreachable("unhandled attribute type"); @@ -806,12 +812,14 @@ getLLVMMemOrder(std::optional memorder) { llvm_unreachable("unknown memory order"); } +static llvm::StringRef getLLVMSyncScope(cir::SyncScopeKind syncScope) { + return syncScope == cir::SyncScopeKind::SingleThread ? "singlethread" : ""; +} + static std::optional getLLVMSyncScope(std::optional syncScope) { if (syncScope.has_value()) - return syncScope.value() == cir::SyncScopeKind::SingleThread - ? "singlethread" - : ""; + return getLLVMSyncScope(*syncScope); return std::nullopt; } @@ -845,9 +853,10 @@ mlir::LogicalResult CIRToLLVMAtomicXchgOpLowering::matchAndRewrite( mlir::ConversionPatternRewriter &rewriter) const { assert(!cir::MissingFeatures::atomicSyncScopeID()); mlir::LLVM::AtomicOrdering llvmOrder = getLLVMMemOrder(adaptor.getMemOrder()); + llvm::StringRef llvmSyncScope = getLLVMSyncScope(adaptor.getSyncScope()); rewriter.replaceOpWithNewOp( op, mlir::LLVM::AtomicBinOp::xchg, adaptor.getPtr(), adaptor.getVal(), - llvmOrder); + llvmOrder, llvmSyncScope); return mlir::success(); } @@ -1777,10 +1786,8 @@ mlir::LogicalResult CIRToLLVMLoadOpLowering::matchAndRewrite( // TODO: nontemporal. assert(!cir::MissingFeatures::opLoadStoreNontemporal()); - std::optional llvmSyncScope; - if (std::optional syncScope = op.getSyncScope()) - llvmSyncScope = - lowerMod->getTargetLoweringInfo().getLLVMSyncScope(*syncScope); + std::optional llvmSyncScope = + getLLVMSyncScope(op.getSyncScope()); mlir::LLVM::LoadOp newLoad = mlir::LLVM::LoadOp::create( rewriter, op->getLoc(), llvmTy, adaptor.getAddr(), alignment, @@ -1815,10 +1822,8 @@ mlir::LogicalResult CIRToLLVMStoreOpLowering::matchAndRewrite( assert(!cir::MissingFeatures::opLoadStoreNontemporal()); assert(!cir::MissingFeatures::opLoadStoreTbaa()); - std::optional llvmSyncScope; - if (std::optional syncScope = op.getSyncScope()) - llvmSyncScope = - lowerMod->getTargetLoweringInfo().getLLVMSyncScope(*syncScope); + std::optional llvmSyncScope = + getLLVMSyncScope(op.getSyncScope()); mlir::LLVM::StoreOp storeOp = mlir::LLVM::StoreOp::create( rewriter, op->getLoc(), value, adaptor.getAddr(), alignment, @@ -1890,8 +1895,7 @@ mlir::LogicalResult CIRToLLVMConstantOpLowering::matchAndRewrite( } // Lower GlobalViewAttr to llvm.mlir.addressof if (auto gv = mlir::dyn_cast(op.getValue())) { - auto newOp = - lowerCirAttrAsValue(op, gv, rewriter, getTypeConverter(), lowerMod); + auto newOp = lowerCirAttrAsValue(op, gv, rewriter, getTypeConverter()); rewriter.replaceOp(op, newOp); return mlir::success(); } @@ -1903,33 +1907,32 @@ mlir::LogicalResult CIRToLLVMConstantOpLowering::matchAndRewrite( std::optional denseAttr; if (constArr && hasTrailingZeros(constArr)) { - const mlir::Value newOp = lowerCirAttrAsValue( - op, constArr, rewriter, getTypeConverter(), lowerMod); + const mlir::Value newOp = + lowerCirAttrAsValue(op, constArr, rewriter, getTypeConverter()); rewriter.replaceOp(op, newOp); return mlir::success(); } else if (constArr && (denseAttr = lowerConstArrayAttr(constArr, typeConverter))) { attr = denseAttr.value(); } else { - const mlir::Value initVal = lowerCirAttrAsValue( - op, op.getValue(), rewriter, typeConverter, lowerMod); + const mlir::Value initVal = + lowerCirAttrAsValue(op, op.getValue(), rewriter, typeConverter); rewriter.replaceOp(op, initVal); return mlir::success(); } } else if (const auto recordAttr = mlir::dyn_cast(op.getValue())) { - auto initVal = - lowerCirAttrAsValue(op, recordAttr, rewriter, typeConverter, lowerMod); + auto initVal = lowerCirAttrAsValue(op, recordAttr, rewriter, typeConverter); rewriter.replaceOp(op, initVal); return mlir::success(); } else if (const auto vecTy = mlir::dyn_cast(op.getType())) { rewriter.replaceOp(op, lowerCirAttrAsValue(op, op.getValue(), rewriter, - getTypeConverter(), lowerMod)); + getTypeConverter())); return mlir::success(); } else if (auto recTy = mlir::dyn_cast(op.getType())) { if (mlir::isa(attr)) { mlir::Value initVal = - lowerCirAttrAsValue(op, attr, rewriter, typeConverter, lowerMod); + lowerCirAttrAsValue(op, attr, rewriter, typeConverter); rewriter.replaceOp(op, initVal); return mlir::success(); } @@ -2287,7 +2290,7 @@ CIRToLLVMGlobalOpLowering::matchAndRewriteRegionInitializedGlobal( // to the appropriate value. const mlir::Location loc = op.getLoc(); setupRegionInitializedLLVMGlobalOp(op, rewriter); - CIRAttrToValue valueConverter(op, rewriter, typeConverter, lowerMod); + CIRAttrToValue valueConverter(op, rewriter, typeConverter); mlir::Value value = valueConverter.visit(init); mlir::LLVM::ReturnOp::create(rewriter, loc, value); return mlir::success(); @@ -3019,20 +3022,8 @@ mlir::LogicalResult CIRToLLVMSelectOpLowering::matchAndRewrite( return mlir::success(); } -std::unique_ptr prepareLowerModule(mlir::ModuleOp module) { - mlir::PatternRewriter rewriter{module->getContext()}; - // If the triple is not present, e.g. CIR modules parsed from text, we - // cannot init LowerModule properly. This happens in some lowering tests, - // but it should not happen in real compilation. - assert(!cir::MissingFeatures::makeTripleAlwaysPresent()); - if (!module->hasAttr(cir::CIRDialect::getTripleAttrName())) - return {}; - return cir::createLowerModule(module, rewriter); -} - static void prepareTypeConverter(mlir::LLVMTypeConverter &converter, - mlir::DataLayout &dataLayout, - cir::LowerModule *lowerModule) { + mlir::DataLayout &dataLayout) { converter.addConversion([&](cir::PointerType type) -> mlir::Type { unsigned addrSpace = type.getAddrSpace() ? type.getAddrSpace().getValue().getUInt() : 0; @@ -3330,8 +3321,7 @@ void ConvertCIRToLLVMPass::runOnOperation() { mlir::ModuleOp module = getOperation(); mlir::DataLayout dl(module); mlir::LLVMTypeConverter converter(&getContext()); - std::unique_ptr lowerModule = prepareLowerModule(module); - prepareTypeConverter(converter, dl, lowerModule.get()); + prepareTypeConverter(converter, dl); /// Tracks the state required to lower CIR `LabelOp` and `BlockAddressOp`. /// Maps labels to their corresponding `BlockTagOp` and keeps bookkeeping @@ -3340,13 +3330,13 @@ void ConvertCIRToLLVMPass::runOnOperation() { LLVMBlockAddressInfo blockInfoAddr; mlir::RewritePatternSet patterns(&getContext()); patterns.add( - converter, patterns.getContext(), lowerModule.get(), dl, blockInfoAddr); + converter, patterns.getContext(), dl, blockInfoAddr); patterns.add< #define GET_LLVM_LOWERING_PATTERNS_LIST #include "clang/CIR/Dialect/IR/CIRLowering.inc" #undef GET_LLVM_LOWERING_PATTERNS_LIST - >(converter, patterns.getContext(), lowerModule.get(), dl); + >(converter, patterns.getContext(), dl); processCIRAttrs(module); @@ -4615,6 +4605,7 @@ lowerDirectlyFromCIRToLLVMIR(mlir::ModuleOp mlirModule, LLVMContext &llvmCtx) { mlir::registerBuiltinDialectTranslation(*mlirCtx); mlir::registerLLVMDialectTranslation(*mlirCtx); + mlir::registerOpenMPDialectTranslation(*mlirCtx); mlir::registerCIRDialectTranslation(*mlirCtx); llvm::TimeTraceScope translateScope("translateModuleToLLVMIR"); diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h index 7235794c3f9b4..0b5872f963317 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h @@ -12,8 +12,6 @@ #ifndef CLANG_CIR_LOWERTOLLVM_H #define CLANG_CIR_LOWERTOLLVM_H -#include "LowerModule.h" - #include "mlir/Dialect/LLVMIR/LLVMAttrs.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" #include "mlir/Transforms/DialectConversion.h" diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index b286ff359ec40..94257fb96fc7f 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -414,7 +414,6 @@ static bool initTargetOptions(const CompilerInstance &CI, if (CodeGenOpts.hasWasmExceptions()) Options.ExceptionModel = llvm::ExceptionHandling::Wasm; - Options.NoInfsFPMath = LangOpts.NoHonorInfs; Options.NoNaNsFPMath = LangOpts.NoHonorNaNs; Options.NoZerosInBSS = CodeGenOpts.NoZeroInitializedInBSS; diff --git a/clang/lib/CodeGen/CGAtomic.cpp b/clang/lib/CodeGen/CGAtomic.cpp index 06ef2f5b8fb6c..fb3a5663834ed 100644 --- a/clang/lib/CodeGen/CGAtomic.cpp +++ b/clang/lib/CodeGen/CGAtomic.cpp @@ -1145,8 +1145,7 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) { auto DestAS = getContext().getTargetAddressSpace(LangAS::opencl_generic); auto *DestType = llvm::PointerType::get(getLLVMContext(), DestAS); - return getTargetHooks().performAddrSpaceCast(*this, V, AS, DestType, - false); + return performAddrSpaceCast(V, DestType); }; Args.add(RValue::get(CastToGenericAddrSpace(Ptr.emitRawPointer(*this), diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 339d6cff0a386..3db880f63a4fe 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -121,6 +121,8 @@ static Value *EmitTargetArchBuiltinExpr(CodeGenFunction *CGF, return CGF->EmitHexagonBuiltinExpr(BuiltinID, E); case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: return CGF->EmitRISCVBuiltinExpr(BuiltinID, E, ReturnValue); case llvm::Triple::spirv32: case llvm::Triple::spirv64: @@ -924,10 +926,10 @@ CodeGenFunction::evaluateOrEmitBuiltinObjectSize(const Expr *E, unsigned Type, llvm::IntegerType *ResType, llvm::Value *EmittedE, bool IsDynamic) { - uint64_t ObjectSize; - if (!E->tryEvaluateObjectSize(ObjectSize, getContext(), Type)) - return emitBuiltinObjectSize(E, Type, ResType, EmittedE, IsDynamic); - return ConstantInt::get(ResType, ObjectSize, /*isSigned=*/true); + if (std::optional ObjectSize = + E->tryEvaluateObjectSize(getContext(), Type)) + return ConstantInt::get(ResType, *ObjectSize, /*isSigned=*/true); + return emitBuiltinObjectSize(E, Type, ResType, EmittedE, IsDynamic); } namespace { @@ -4452,12 +4454,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, AI->setAlignment(SuitableAlignmentInBytes); if (BuiltinID != Builtin::BI__builtin_alloca_uninitialized) initializeAlloca(*this, AI, Size, SuitableAlignmentInBytes); - LangAS AAS = getASTAllocaAddressSpace(); - LangAS EAS = E->getType()->getPointeeType().getAddressSpace(); - if (AAS != EAS) { + if (AI->getAddressSpace() != + CGM.getContext().getTargetAddressSpace( + E->getType()->getPointeeType().getAddressSpace())) { llvm::Type *Ty = CGM.getTypes().ConvertType(E->getType()); - return RValue::get( - getTargetHooks().performAddrSpaceCast(*this, AI, AAS, Ty)); + return RValue::get(performAddrSpaceCast(AI, Ty)); } return RValue::get(AI); } @@ -4474,12 +4475,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, AI->setAlignment(AlignmentInBytes); if (BuiltinID != Builtin::BI__builtin_alloca_with_align_uninitialized) initializeAlloca(*this, AI, Size, AlignmentInBytes); - LangAS AAS = getASTAllocaAddressSpace(); - LangAS EAS = E->getType()->getPointeeType().getAddressSpace(); - if (AAS != EAS) { + if (AI->getAddressSpace() != + CGM.getContext().getTargetAddressSpace( + E->getType()->getPointeeType().getAddressSpace())) { llvm::Type *Ty = CGM.getTypes().ConvertType(E->getType()); - return RValue::get( - getTargetHooks().performAddrSpaceCast(*this, AI, AAS, Ty)); + return RValue::get(performAddrSpaceCast(AI, Ty)); } return RValue::get(AI); } @@ -5712,12 +5712,13 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, case Builtin::BI__builtin_ptrauth_auth: case Builtin::BI__builtin_ptrauth_auth_and_resign: + case Builtin::BI__builtin_ptrauth_auth_load_relative_and_sign: case Builtin::BI__builtin_ptrauth_blend_discriminator: case Builtin::BI__builtin_ptrauth_sign_generic_data: case Builtin::BI__builtin_ptrauth_sign_unauthenticated: case Builtin::BI__builtin_ptrauth_strip: { // Emit the arguments. - SmallVector Args; + SmallVector Args; for (auto argExpr : E->arguments()) Args.push_back(EmitScalarExpr(argExpr)); @@ -5728,6 +5729,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, switch (BuiltinID) { case Builtin::BI__builtin_ptrauth_auth_and_resign: + case Builtin::BI__builtin_ptrauth_auth_load_relative_and_sign: if (Args[4]->getType()->isPointerTy()) Args[4] = Builder.CreatePtrToInt(Args[4], IntPtrTy); [[fallthrough]]; @@ -5755,6 +5757,8 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, return Intrinsic::ptrauth_auth; case Builtin::BI__builtin_ptrauth_auth_and_resign: return Intrinsic::ptrauth_resign; + case Builtin::BI__builtin_ptrauth_auth_load_relative_and_sign: + return Intrinsic::ptrauth_resign_load_relative; case Builtin::BI__builtin_ptrauth_blend_discriminator: return Intrinsic::ptrauth_blend; case Builtin::BI__builtin_ptrauth_sign_generic_data: diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 04f44146e1269..224b2997b7db4 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -27,6 +27,7 @@ #include "clang/AST/Decl.h" #include "clang/AST/DeclCXX.h" #include "clang/AST/DeclObjC.h" +#include "clang/AST/RecordLayout.h" #include "clang/Basic/CodeGenOptions.h" #include "clang/Basic/TargetInfo.h" #include "clang/CodeGen/CGFunctionInfo.h" @@ -1942,11 +1943,9 @@ static bool HasStrictReturn(const CodeGenModule &Module, QualType RetTy, static void addDenormalModeAttrs(llvm::DenormalMode FPDenormalMode, llvm::DenormalMode FP32DenormalMode, llvm::AttrBuilder &FuncAttrs) { - if (FPDenormalMode != llvm::DenormalMode::getDefault()) - FuncAttrs.addAttribute("denormal-fp-math", FPDenormalMode.str()); - - if (FP32DenormalMode != FPDenormalMode && FP32DenormalMode.isValid()) - FuncAttrs.addAttribute("denormal-fp-math-f32", FP32DenormalMode.str()); + llvm::DenormalFPEnv FPEnv(FPDenormalMode, FP32DenormalMode); + if (FPEnv != llvm::DenormalFPEnv::getDefault()) + FuncAttrs.addDenormalFPEnvAttr(FPEnv); } /// Add default attributes to a function, which have merge semantics under @@ -2011,8 +2010,6 @@ static void getTrivialDefaultFunctionAttributes( // TODO: Are these all needed? // unsafe/inf/nan/nsz are handled by instruction-level FastMathFlags. - if (LangOpts.NoHonorInfs) - FuncAttrs.addAttribute("no-infs-fp-math", "true"); if (LangOpts.NoHonorNaNs) FuncAttrs.addAttribute("no-nans-fp-math", "true"); if (CodeGenOpts.SoftFloat) @@ -2168,35 +2165,19 @@ void CodeGen::mergeDefaultFunctionDefinitionAttributes( llvm::AttributeMask AttrsToRemove; - llvm::DenormalMode DenormModeToMerge = F.getDenormalModeRaw(); - llvm::DenormalMode DenormModeToMergeF32 = F.getDenormalModeF32Raw(); - llvm::DenormalMode Merged = - CodeGenOpts.FPDenormalMode.mergeCalleeMode(DenormModeToMerge); - llvm::DenormalMode MergedF32 = CodeGenOpts.FP32DenormalMode; - - if (DenormModeToMergeF32.isValid()) { - MergedF32 = - CodeGenOpts.FP32DenormalMode.mergeCalleeMode(DenormModeToMergeF32); - } + llvm::DenormalFPEnv OptsFPEnv(CodeGenOpts.FPDenormalMode, + CodeGenOpts.FP32DenormalMode); + llvm::DenormalFPEnv MergedFPEnv = + OptsFPEnv.mergeCalleeMode(F.getDenormalFPEnv()); - if (Merged == llvm::DenormalMode::getDefault()) { - AttrsToRemove.addAttribute("denormal-fp-math"); - } else if (Merged != DenormModeToMerge) { - // Overwrite existing attribute - FuncAttrs.addAttribute("denormal-fp-math", - CodeGenOpts.FPDenormalMode.str()); - } - - if (MergedF32 == llvm::DenormalMode::getDefault()) { - AttrsToRemove.addAttribute("denormal-fp-math-f32"); - } else if (MergedF32 != DenormModeToMergeF32) { + if (MergedFPEnv == llvm::DenormalFPEnv::getDefault()) { + AttrsToRemove.addAttribute(llvm::Attribute::DenormalFPEnv); + } else { // Overwrite existing attribute - FuncAttrs.addAttribute("denormal-fp-math-f32", - CodeGenOpts.FP32DenormalMode.str()); + FuncAttrs.addDenormalFPEnvAttr(MergedFPEnv); } F.removeFnAttrs(AttrsToRemove); - addDenormalModeAttrs(Merged, MergedF32, FuncAttrs); overrideFunctionFeaturesWithTargetFeatures(FuncAttrs, F, TargetOpts); @@ -2781,7 +2762,8 @@ void CodeGenModule::ConstructAttributeList(StringRef Name, } // Apply `nonnull`, `dereferenceable(N)` and `align N` to the `this` argument, - // unless this is a thunk function. + // unless this is a thunk function. Add dead_on_return to the `this` argument + // in base class destructors to aid in DSE. // FIXME: fix this properly, https://reviews.llvm.org/D100388 if (FI.isInstanceMethod() && !IRFunctionArgs.hasInallocaArg() && !FI.arg_begin()->type->isVoidPointerType() && !IsThunk) { @@ -2814,6 +2796,27 @@ void CodeGenModule::ConstructAttributeList(StringRef Name, .getAsAlign(); Attrs.addAlignmentAttr(Alignment); + const auto *DD = dyn_cast_if_present( + CalleeInfo.getCalleeDecl().getDecl()); + // Do not annotate vector deleting destructors with dead_on_return as the + // this pointer in that case points to an array which we cannot + // statically know the size of. + if (DD && + CalleeInfo.getCalleeDecl().getDtorType() != + CXXDtorType::Dtor_VectorDeleting && + CodeGenOpts.StrictLifetimes) { + const CXXRecordDecl *ClassDecl = + dyn_cast(DD->getDeclContext()); + // TODO(boomanaiden154): We are being intentionally conservative here + // as we gain experience with this optimization. We should remove the + // condition for non-virtual bases after more testing. We cannot add + // dead_on_return if we have virtual base classes because they will + // generally still be live after the base object destructor. + if (ClassDecl->getNumBases() == 0 && ClassDecl->getNumVBases() == 0) + Attrs.addDeadOnReturnAttr(llvm::DeadOnReturnInfo( + Context.getASTRecordLayout(ClassDecl).getDataSize().getQuantity())); + } + ArgAttrs[IRArgs.first] = llvm::AttributeSet::get(getLLVMContext(), Attrs); } @@ -5341,13 +5344,11 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, // here, symmetrically with the handling we have for normal pointer args. if (SRetPtr.getAddressSpace() != RetAI.getIndirectAddrSpace()) { llvm::Value *V = SRetPtr.getBasePointer(); - LangAS SAS = getLangASFromTargetAS(SRetPtr.getAddressSpace()); llvm::Type *Ty = llvm::PointerType::get(getLLVMContext(), RetAI.getIndirectAddrSpace()); - SRetPtr = SRetPtr.withPointer( - getTargetHooks().performAddrSpaceCast(*this, V, SAS, Ty, true), - SRetPtr.isKnownNonNull()); + SRetPtr = SRetPtr.withPointer(performAddrSpaceCast(V, Ty), + SRetPtr.isKnownNonNull()); } IRCallArgs[IRFunctionArgs.getSRetArgNo()] = getAsNaturalPointerTo(SRetPtr, RetTy); @@ -5490,8 +5491,7 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, // only the contextual values. If the address space mismatches, see if // we can look through a cast to a compatible address space value, // otherwise emit a copy. - llvm::Value *Val = getTargetHooks().performAddrSpaceCast( - *this, V, I->Ty.getAddressSpace(), T, true); + llvm::Value *Val = performAddrSpaceCast(V, T); if (ArgHasMaybeUndefAttr) Val = Builder.CreateFreeze(Val); IRCallArgs[FirstIRArg] = Val; @@ -5575,9 +5575,7 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, if (FirstIRArg < IRFuncTy->getNumParams() && V->getType() != IRFuncTy->getParamType(FirstIRArg)) { assert(V->getType()->isPointerTy() && "Only pointers can mismatch!"); - auto ActualAS = I->Ty.getAddressSpace(); - V = getTargetHooks().performAddrSpaceCast( - *this, V, ActualAS, IRFuncTy->getParamType(FirstIRArg)); + V = performAddrSpaceCast(V, IRFuncTy->getParamType(FirstIRArg)); } if (ArgHasMaybeUndefAttr) diff --git a/clang/lib/CodeGen/CGCall.h b/clang/lib/CodeGen/CGCall.h index 4a86d58895dd9..145992652934f 100644 --- a/clang/lib/CodeGen/CGCall.h +++ b/clang/lib/CodeGen/CGCall.h @@ -410,7 +410,7 @@ class ReturnValueSlot { /// This is useful for adding attrs to bitcode modules that you want to link /// with but don't control, such as CUDA's libdevice. When linking with such /// a bitcode library, you might want to set e.g. its functions' -/// "denormal-fp-math" attribute to match the attr of the functions you're +/// denormal_fp_math attribute to match the attr of the functions you're /// codegen'ing. Otherwise, LLVM will interpret the bitcode module's lack of /// denormal-fp-math attrs as tantamount to denormal-fp-math=ieee, and then LLVM /// will propagate denormal-fp-math=ieee up to every transitive caller of a diff --git a/clang/lib/CodeGen/CGClass.cpp b/clang/lib/CodeGen/CGClass.cpp index 02e8912bdbbf0..831f63084fd6c 100644 --- a/clang/lib/CodeGen/CGClass.cpp +++ b/clang/lib/CodeGen/CGClass.cpp @@ -2278,8 +2278,7 @@ void CodeGenFunction::EmitCXXConstructorCall( unsigned TargetThisAS = getContext().getTargetAddressSpace(ThisAS); llvm::Type *NewType = llvm::PointerType::get(getLLVMContext(), TargetThisAS); - ThisPtr = - getTargetHooks().performAddrSpaceCast(*this, ThisPtr, ThisAS, NewType); + ThisPtr = performAddrSpaceCast(ThisPtr, NewType); } // Push the this ptr. @@ -2495,7 +2494,7 @@ void CodeGenFunction::EmitInlinedInheritingCXXConstructorCall( // FIXME: This is dumb, we should ask the ABI not to try to set the return // value instead. if (!RetType->isVoidType()) - ReturnValue = CreateIRTemp(RetType, "retval.inhctor"); + ReturnValue = CreateIRTempWithoutCast(RetType, "retval.inhctor"); CGM.getCXXABI().EmitInstanceFunctionProlog(*this); CXXThisValue = CXXABIThisValue; diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index f39e282f3d055..c66112e0e5bfb 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -303,8 +303,8 @@ llvm::Constant *CodeGenModule::getOrCreateStaticVarDecl( LangAS ExpectedAS = Ty.getAddressSpace(); llvm::Constant *Addr = GV; if (AS != ExpectedAS) { - Addr = getTargetCodeGenInfo().performAddrSpaceCast( - *this, GV, AS, + Addr = performAddrSpaceCast( + GV, llvm::PointerType::get(getLLVMContext(), getContext().getTargetAddressSpace(ExpectedAS))); } @@ -2227,8 +2227,13 @@ void CodeGenFunction::EmitAutoVarCleanups(const AutoVarEmission &emission) { const VarDecl &D = *emission.Variable; // Check the type for a cleanup. - if (QualType::DestructionKind dtorKind = D.needsDestruction(getContext())) + if (QualType::DestructionKind dtorKind = D.needsDestruction(getContext())) { + // Check if we're in a SEH block, prevent it + if (currentFunctionUsesSEHTry()) + getContext().getDiagnostics().Report(D.getLocation(), + diag::err_seh_object_unwinding); emitAutoVarTypeCleanup(emission, dtorKind); + } // In GC mode, honor objc_precise_lifetime. if (getLangOpts().getGC() != LangOptions::NonGC && @@ -2732,9 +2737,8 @@ void CodeGenFunction::EmitParmDecl(const VarDecl &D, ParamValue Arg, CGM.getDataLayout().getAllocaAddrSpace()); auto DestAS = getContext().getTargetAddressSpace(DestLangAS); auto *T = llvm::PointerType::get(getLLVMContext(), DestAS); - DeclPtr = DeclPtr.withPointer( - getTargetHooks().performAddrSpaceCast(*this, V, SrcLangAS, T, true), - DeclPtr.isKnownNonNull()); + DeclPtr = DeclPtr.withPointer(performAddrSpaceCast(V, T), + DeclPtr.isKnownNonNull()); } // Push a destructor cleanup for this parameter if the ABI requires it. diff --git a/clang/lib/CodeGen/CGException.cpp b/clang/lib/CodeGen/CGException.cpp index e9d20672ce185..2f1df6e9a8a5c 100644 --- a/clang/lib/CodeGen/CGException.cpp +++ b/clang/lib/CodeGen/CGException.cpp @@ -1143,7 +1143,6 @@ static void emitCatchDispatchBlock(CodeGenFunction &CGF, llvm::Function *llvm_eh_typeid_for = CGF.CGM.getIntrinsic(llvm::Intrinsic::eh_typeid_for, {CGF.VoidPtrTy}); llvm::Type *argTy = llvm_eh_typeid_for->getArg(0)->getType(); - LangAS globAS = CGF.CGM.GetGlobalVarAddressSpace(nullptr); // Load the selector value. llvm::Value *selector = CGF.getSelectorFromSlot(); @@ -1159,8 +1158,7 @@ static void emitCatchDispatchBlock(CodeGenFunction &CGF, assert(typeValue && "fell into catch-all case!"); // With opaque ptrs, only the address space can be a mismatch. if (typeValue->getType() != argTy) - typeValue = CGF.getTargetHooks().performAddrSpaceCast(CGF, typeValue, - globAS, argTy); + typeValue = CGF.performAddrSpaceCast(typeValue, argTy); // Figure out the next block. bool nextIsEnd; diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 339314ecff9cd..091e9c87c8ad4 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -29,6 +29,7 @@ #include "clang/AST/ASTLambda.h" #include "clang/AST/Attr.h" #include "clang/AST/DeclObjC.h" +#include "clang/AST/Expr.h" #include "clang/AST/InferAlloc.h" #include "clang/AST/NSAPI.h" #include "clang/AST/ParentMapContext.h" @@ -129,9 +130,7 @@ RawAddress CodeGenFunction::MaybeCastStackAddressSpace(RawAddress Alloca, // builder. if (!ArraySize) Builder.SetInsertPoint(getPostAllocaInsertPoint()); - V = getTargetHooks().performAddrSpaceCast( - *this, V, getASTAllocaAddressSpace(), Builder.getPtrTy(DestAddrSpace), - /*IsNonNull=*/true); + V = performAddrSpaceCast(V, Builder.getPtrTy(DestAddrSpace)); } return RawAddress(V, Alloca.getElementType(), Alloca.getAlignment(), @@ -181,9 +180,10 @@ RawAddress CodeGenFunction::CreateDefaultAlignTempAlloca(llvm::Type *Ty, return CreateTempAlloca(Ty, Align, Name); } -RawAddress CodeGenFunction::CreateIRTemp(QualType Ty, const Twine &Name) { +RawAddress CodeGenFunction::CreateIRTempWithoutCast(QualType Ty, + const Twine &Name) { CharUnits Align = getContext().getTypeAlignInChars(Ty); - return CreateTempAlloca(ConvertType(Ty), Align, Name); + return CreateTempAllocaWithoutCast(ConvertType(Ty), Align, Name, nullptr); } RawAddress CodeGenFunction::CreateMemTemp(QualType Ty, const Twine &Name, @@ -200,8 +200,14 @@ RawAddress CodeGenFunction::CreateMemTemp(QualType Ty, CharUnits Align, if (Ty->isConstantMatrixType()) { auto *ArrayTy = cast(Result.getElementType()); - auto *VectorTy = llvm::FixedVectorType::get(ArrayTy->getElementType(), - ArrayTy->getNumElements()); + auto *ArrayElementTy = ArrayTy->getElementType(); + auto ArrayElements = ArrayTy->getNumElements(); + if (getContext().getLangOpts().HLSL) { + auto *VectorTy = cast(ArrayElementTy); + ArrayElementTy = VectorTy->getElementType(); + ArrayElements *= VectorTy->getNumElements(); + } + auto *VectorTy = llvm::FixedVectorType::get(ArrayElementTy, ArrayElements); Result = Address(Result.getPointer(), VectorTy, Result.getAlignment(), KnownNonNull); @@ -459,7 +465,6 @@ static RawAddress createReferenceTemporary(CodeGenFunction &CGF, const MaterializeTemporaryExpr *M, const Expr *Inner, RawAddress *Alloca = nullptr) { - auto &TCG = CGF.getTargetHooks(); switch (M->getStorageDuration()) { case SD_FullExpression: case SD_Automatic: { @@ -482,11 +487,10 @@ static RawAddress createReferenceTemporary(CodeGenFunction &CGF, GV->setAlignment(alignment.getAsAlign()); llvm::Constant *C = GV; if (AS != LangAS::Default) - C = TCG.performAddrSpaceCast( - CGF.CGM, GV, AS, - llvm::PointerType::get( - CGF.getLLVMContext(), - CGF.getContext().getTargetAddressSpace(LangAS::Default))); + C = CGF.CGM.performAddrSpaceCast( + GV, llvm::PointerType::get( + CGF.getLLVMContext(), + CGF.getContext().getTargetAddressSpace(LangAS::Default))); // FIXME: Should we put the new global into a COMDAT? return RawAddress(C, GV->getValueType(), alignment); } @@ -1828,6 +1832,8 @@ LValue CodeGenFunction::EmitLValueHelper(const Expr *E, return EmitArraySectionExpr(cast(E)); case Expr::ExtVectorElementExprClass: return EmitExtVectorElementExpr(cast(E)); + case Expr::MatrixElementExprClass: + return EmitMatrixElementExpr(cast(E)); case Expr::CXXThisExprClass: return MakeAddrLValue(LoadCXXThisAddress(), E->getType()); case Expr::MemberExprClass: @@ -2279,8 +2285,14 @@ static RawAddress MaybeConvertMatrixAddress(RawAddress Addr, bool IsVector = true) { auto *ArrayTy = dyn_cast(Addr.getElementType()); if (ArrayTy && IsVector) { - auto *VectorTy = llvm::FixedVectorType::get(ArrayTy->getElementType(), - ArrayTy->getNumElements()); + auto ArrayElements = ArrayTy->getNumElements(); + auto *ArrayElementTy = ArrayTy->getElementType(); + if (CGF.getContext().getLangOpts().HLSL) { + auto *VectorTy = cast(ArrayElementTy); + ArrayElementTy = VectorTy->getElementType(); + ArrayElements *= VectorTy->getNumElements(); + } + auto *VectorTy = llvm::FixedVectorType::get(ArrayElementTy, ArrayElements); return Addr.withElementType(VectorTy); } @@ -2296,6 +2308,49 @@ static RawAddress MaybeConvertMatrixAddress(RawAddress Addr, return Addr; } +LValue CodeGenFunction::EmitMatrixElementExpr(const MatrixElementExpr *E) { + LValue Base; + if (E->getBase()->isGLValue()) + Base = EmitLValue(E->getBase()); + else { + assert(E->getBase()->getType()->isConstantMatrixType() && + "Result must be a Constant Matrix"); + llvm::Value *Mat = EmitScalarExpr(E->getBase()); + Address MatMem = CreateMemTemp(E->getBase()->getType()); + QualType Ty = E->getBase()->getType(); + llvm::Type *LTy = convertTypeForLoadStore(Ty, Mat->getType()); + if (LTy->getScalarSizeInBits() > Mat->getType()->getScalarSizeInBits()) + Mat = Builder.CreateZExt(Mat, LTy); + Builder.CreateStore(Mat, MatMem); + Base = MakeAddrLValue(MatMem, Ty, AlignmentSource::Decl); + } + QualType ResultType = + E->getType().withCVRQualifiers(Base.getQuals().getCVRQualifiers()); + + // Encode the element access list into a vector of unsigned indices. + SmallVector Indices; + E->getEncodedElementAccess(Indices); + + if (Base.isSimple()) { + llvm::Constant *CV = + llvm::ConstantDataVector::get(getLLVMContext(), Indices); + return LValue::MakeExtVectorElt( + MaybeConvertMatrixAddress(Base.getAddress(), *this), CV, ResultType, + Base.getBaseInfo(), TBAAAccessInfo()); + } + assert(Base.isExtVectorElt() && "Can only subscript lvalue vec elts here!"); + + llvm::Constant *BaseElts = Base.getExtVectorElts(); + SmallVector CElts; + + for (unsigned Index : Indices) + CElts.push_back(BaseElts->getAggregateElement(Index)); + llvm::Constant *CV = llvm::ConstantVector::get(CElts); + return LValue::MakeExtVectorElt( + MaybeConvertMatrixAddress(Base.getExtVectorAddress(), *this), CV, + ResultType, Base.getBaseInfo(), TBAAAccessInfo()); +} + // Emit a store of a matrix LValue. This may require casting the original // pointer to memory address (ArrayType) to a pointer to the value type // (VectorType). @@ -3659,14 +3714,14 @@ LValue CodeGenFunction::EmitDeclRefLValue(const DeclRefExpr *E) { AlignmentSource::Decl); if (const auto *TPO = dyn_cast(ND)) { - auto ATPO = CGM.GetAddrOfTemplateParamObject(TPO); + ConstantAddress ATPO = CGM.GetAddrOfTemplateParamObject(TPO); auto AS = getLangASFromTargetAS(ATPO.getAddressSpace()); if (AS != T.getAddressSpace()) { auto TargetAS = getContext().getTargetAddressSpace(T.getAddressSpace()); - auto PtrTy = llvm::PointerType::get(CGM.getLLVMContext(), TargetAS); - auto ASC = getTargetHooks().performAddrSpaceCast(CGM, ATPO.getPointer(), - AS, PtrTy); + llvm::Type *PtrTy = + llvm::PointerType::get(CGM.getLLVMContext(), TargetAS); + llvm::Constant *ASC = CGM.performAddrSpaceCast(ATPO.getPointer(), PtrTy); ATPO = ConstantAddress(ASC, ATPO.getElementType(), ATPO.getAlignment()); } @@ -4393,6 +4448,12 @@ void CodeGenFunction::EmitUnreachable(SourceLocation Loc) { void CodeGenFunction::EmitTrapCheck(llvm::Value *Checked, SanitizerHandler CheckHandlerID, bool NoMerge, const TrapReason *TR) { + if (CGM.getCodeGenOpts().SanitizeTrapLoop) { + Builder.CreateCall(CGM.getIntrinsic(llvm::Intrinsic::cond_loop), + Builder.CreateNot(Checked)); + return; + } + llvm::BasicBlock *Cont = createBasicBlock("cont"); // If we're optimizing, collapse all calls to trap down to just one per @@ -6117,9 +6178,8 @@ LValue CodeGenFunction::EmitCastLValue(const CastExpr *E) { case CK_AddressSpaceConversion: { LValue LV = EmitLValue(E->getSubExpr()); QualType DestTy = getContext().getPointerType(E->getType()); - llvm::Value *V = getTargetHooks().performAddrSpaceCast( - *this, LV.getPointer(*this), - E->getSubExpr()->getType().getAddressSpace(), ConvertType(DestTy)); + llvm::Value *V = + performAddrSpaceCast(LV.getPointer(*this), ConvertType(DestTy)); return MakeAddrLValue(Address(V, ConvertTypeForMem(E->getType()), LV.getAddress().getAlignment()), E->getType(), LV.getBaseInfo(), LV.getTBAAInfo()); @@ -6156,7 +6216,7 @@ CodeGenFunction::EmitHLSLOutArgLValues(const HLSLOutArgExpr *E, QualType Ty) { OpaqueValueMappingData::bind(*this, E->getOpaqueArgLValue(), BaseLV); QualType ExprTy = E->getType(); - Address OutTemp = CreateIRTemp(ExprTy); + Address OutTemp = CreateIRTempWithoutCast(ExprTy); LValue TempLV = MakeAddrLValue(OutTemp, ExprTy); if (E->isInOut()) @@ -6979,14 +7039,15 @@ void CodeGenFunction::SetFPAccuracy(llvm::Value *Val, float Accuracy) { void CodeGenFunction::SetSqrtFPAccuracy(llvm::Value *Val) { llvm::Type *EltTy = Val->getType()->getScalarType(); - if (!EltTy->isFloatTy()) + if (!EltTy->isFloatTy() && !EltTy->isHalfTy()) return; if ((getLangOpts().OpenCL && !CGM.getCodeGenOpts().OpenCLCorrectlyRoundedDivSqrt) || (getLangOpts().HIP && getLangOpts().CUDAIsDevice && !CGM.getCodeGenOpts().HIPCorrectlyRoundedDivSqrt)) { - // OpenCL v1.1 s7.4: minimum accuracy of single precision / is 3ulp + // OpenCL v1.1 s7.4: minimum accuracy of single precision sqrt is 3 ulp. + // OpenCL v3.0 s7.4: minimum accuracy of half precision sqrt is 1.5 ulp. // // OpenCL v1.2 s5.6.4.2: The -cl-fp32-correctly-rounded-divide-sqrt // build option allows an application to specify that single precision @@ -6994,20 +7055,21 @@ void CodeGenFunction::SetSqrtFPAccuracy(llvm::Value *Val) { // source are correctly rounded. // // TODO: CUDA has a prec-sqrt flag - SetFPAccuracy(Val, 3.0f); + SetFPAccuracy(Val, EltTy->isFloatTy() ? 3.0f : 1.5f); } } void CodeGenFunction::SetDivFPAccuracy(llvm::Value *Val) { llvm::Type *EltTy = Val->getType()->getScalarType(); - if (!EltTy->isFloatTy()) + if (!EltTy->isFloatTy() && !EltTy->isHalfTy()) return; if ((getLangOpts().OpenCL && !CGM.getCodeGenOpts().OpenCLCorrectlyRoundedDivSqrt) || (getLangOpts().HIP && getLangOpts().CUDAIsDevice && !CGM.getCodeGenOpts().HIPCorrectlyRoundedDivSqrt)) { - // OpenCL v1.1 s7.4: minimum accuracy of single precision / is 2.5ulp + // OpenCL v1.1 s7.4: minimum accuracy of single precision / is 2.5 ulp. + // OpenCL v3.0 s7.4: minimum accuracy of half precision / is 1 ulp. // // OpenCL v1.2 s5.6.4.2: The -cl-fp32-correctly-rounded-divide-sqrt // build option allows an application to specify that single precision @@ -7015,7 +7077,7 @@ void CodeGenFunction::SetDivFPAccuracy(llvm::Value *Val) { // source are correctly rounded. // // TODO: CUDA has a prec-div flag - SetFPAccuracy(Val, 2.5f); + SetFPAccuracy(Val, EltTy->isFloatTy() ? 2.5f : 1.f); } } diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp index 78c10ec757bca..c8e1fe69da9c7 100644 --- a/clang/lib/CodeGen/CGExprCXX.cpp +++ b/clang/lib/CodeGen/CGExprCXX.cpp @@ -113,7 +113,7 @@ RValue CodeGenFunction::EmitCXXDestructorCall( if (SrcAS != DstAS) { QualType DstTy = DtorDecl->getThisType(); llvm::Type *NewType = CGM.getTypes().ConvertType(DstTy); - This = getTargetHooks().performAddrSpaceCast(*this, This, SrcAS, NewType); + This = performAddrSpaceCast(This, NewType); } CallArgList Args; @@ -2179,10 +2179,10 @@ llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) { llvm::Type *PtrTy = Int8PtrTy; LangAS GlobAS = CGM.GetGlobalVarAddressSpace(nullptr); - auto MaybeASCast = [=](auto &&TypeInfo) { + auto MaybeASCast = [=](llvm::Constant *TypeInfo) { if (GlobAS == LangAS::Default) return TypeInfo; - return getTargetHooks().performAddrSpaceCast(CGM, TypeInfo, GlobAS, PtrTy); + return CGM.performAddrSpaceCast(TypeInfo, PtrTy); }; if (E->isTypeOperand()) { diff --git a/clang/lib/CodeGen/CGExprConstant.cpp b/clang/lib/CodeGen/CGExprConstant.cpp index 0eec4dba4824a..c316642a87baf 100644 --- a/clang/lib/CodeGen/CGExprConstant.cpp +++ b/clang/lib/CodeGen/CGExprConstant.cpp @@ -1224,13 +1224,11 @@ class ConstExprEmitter } case CK_AddressSpaceConversion: { - auto C = Emitter.tryEmitPrivate(subExpr, subExpr->getType()); + llvm::Constant *C = Emitter.tryEmitPrivate(subExpr, subExpr->getType()); if (!C) return nullptr; - LangAS srcAS = subExpr->getType()->getPointeeType().getAddressSpace(); llvm::Type *destTy = ConvertType(E->getType()); - return CGM.getTargetCodeGenInfo().performAddrSpaceCast(CGM, C, srcAS, - destTy); + return CGM.performAddrSpaceCast(C, destTy); } case CK_LValueToRValue: { diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 1b1bc4a11741e..ed4691c8efabb 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -608,6 +608,7 @@ class ScalarExprEmitter Value *VisitConvertVectorExpr(ConvertVectorExpr *E); Value *VisitMemberExpr(MemberExpr *E); Value *VisitExtVectorElementExpr(Expr *E) { return EmitLoadOfLValue(E); } + Value *VisitMatrixElementExpr(Expr *E) { return EmitLoadOfLValue(E); } Value *VisitCompoundLiteralExpr(CompoundLiteralExpr *E) { // Strictly speaking, we shouldn't be calling EmitLoadOfLValue, which // transitively calls EmitCompoundLiteralLValue, here in C++ since compound @@ -2459,8 +2460,8 @@ static Value *EmitHLSLElementwiseCast(CodeGenFunction &CGF, LValue SrcVal, assert(LoadList.size() >= VecTy->getNumElements() && "Flattened type on RHS must have the same number or more elements " "than vector on LHS."); - llvm::Value *V = - CGF.Builder.CreateLoad(CGF.CreateIRTemp(DestTy, "flatcast.tmp")); + llvm::Value *V = CGF.Builder.CreateLoad( + CGF.CreateIRTempWithoutCast(DestTy, "flatcast.tmp")); // write to V. for (unsigned I = 0, E = VecTy->getNumElements(); I < E; I++) { RValue RVal = CGF.EmitLoadOfLValue(LoadList[I], Loc); @@ -2478,8 +2479,8 @@ static Value *EmitHLSLElementwiseCast(CodeGenFunction &CGF, LValue SrcVal, "Flattened type on RHS must have the same number or more elements " "than vector on LHS."); - llvm::Value *V = - CGF.Builder.CreateLoad(CGF.CreateIRTemp(DestTy, "flatcast.tmp")); + llvm::Value *V = CGF.Builder.CreateLoad( + CGF.CreateIRTempWithoutCast(DestTy, "flatcast.tmp")); // V is an allocated temporary to build the truncated matrix into. for (unsigned I = 0, E = MatTy->getNumElementsFlattened(); I < E; I++) { unsigned ColMajorIndex = @@ -2564,8 +2565,7 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { // detail, and doing an AS cast here still retains the semantics the user // expects. It is desirable to remove this iff a better solution is found. if (auto A = dyn_cast(Src); A && A->hasStructRetAttr()) - return CGF.CGM.getTargetCodeGenInfo().performAddrSpaceCast( - CGF, Src, E->getType().getAddressSpace(), DstTy); + return CGF.performAddrSpaceCast(Src, DstTy); assert( (!SrcTy->isPtrOrPtrVectorTy() || !DstTy->isPtrOrPtrVectorTy() || @@ -2709,9 +2709,7 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { } // Since target may map different address spaces in AST to the same address // space, an address space conversion may end up as a bitcast. - return CGF.CGM.getTargetCodeGenInfo().performAddrSpaceCast( - CGF, Visit(E), E->getType()->getPointeeType().getAddressSpace(), - ConvertType(DestTy)); + return CGF.performAddrSpaceCast(Visit(E), ConvertType(DestTy)); } case CK_AtomicToNonAtomic: case CK_NonAtomicToAtomic: @@ -4038,9 +4036,14 @@ LValue ScalarExprEmitter::EmitCompoundAssignLValue( if (LHSLV.isBitField()) { Previous = Result; Result = EmitScalarConversion(Result, PromotionTypeCR, LHSTy, Loc); - } else + } else if (const auto *atomicTy = LHSTy->getAs()) { + Result = + EmitScalarConversion(Result, PromotionTypeCR, atomicTy->getValueType(), + Loc, ScalarConversionOpts(CGF.SanOpts)); + } else { Result = EmitScalarConversion(Result, PromotionTypeCR, LHSTy, Loc, ScalarConversionOpts(CGF.SanOpts)); + } if (atomicPHI) { llvm::BasicBlock *curBlock = Builder.GetInsertBlock(); diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index b3c0c90faeb02..c72eef1982e9e 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -346,57 +346,36 @@ static Intrinsic::ID getWaveActiveSumIntrinsic(llvm::Triple::ArchType Arch, } } -// Return wave active max that corresponds to the QT scalar type -static Intrinsic::ID getWaveActiveMaxIntrinsic(llvm::Triple::ArchType Arch, - CGHLSLRuntime &RT, QualType QT) { +static Intrinsic::ID getPrefixCountBitsIntrinsic(llvm::Triple::ArchType Arch) { switch (Arch) { case llvm::Triple::spirv: - if (QT->isUnsignedIntegerType()) - return Intrinsic::spv_wave_reduce_umax; - return Intrinsic::spv_wave_reduce_max; + return Intrinsic::spv_subgroup_prefix_bit_count; case llvm::Triple::dxil: { - if (QT->isUnsignedIntegerType()) - return Intrinsic::dx_wave_reduce_umax; - return Intrinsic::dx_wave_reduce_max; + return Intrinsic::dx_wave_prefix_bit_count; } default: - llvm_unreachable("Intrinsic WaveActiveMax" - " not supported by target architecture"); + llvm_unreachable( + "WavePrefixOp instruction not supported by target architecture"); } } -// Return wave active min that corresponds to the QT scalar type -static Intrinsic::ID getWaveActiveMinIntrinsic(llvm::Triple::ArchType Arch, +// Return wave prefix sum that corresponds to the QT scalar type +static Intrinsic::ID getWavePrefixSumIntrinsic(llvm::Triple::ArchType Arch, CGHLSLRuntime &RT, QualType QT) { switch (Arch) { case llvm::Triple::spirv: - if (QT->isUnsignedIntegerType()) - return Intrinsic::spv_wave_reduce_umin; - return Intrinsic::spv_wave_reduce_min; + return Intrinsic::spv_wave_prefix_sum; case llvm::Triple::dxil: { if (QT->isUnsignedIntegerType()) - return Intrinsic::dx_wave_reduce_umin; - return Intrinsic::dx_wave_reduce_min; + return Intrinsic::dx_wave_prefix_usum; + return Intrinsic::dx_wave_prefix_sum; } default: - llvm_unreachable("Intrinsic WaveActiveMin" + llvm_unreachable("Intrinsic WavePrefixSum" " not supported by target architecture"); } } -static Intrinsic::ID getPrefixCountBitsIntrinsic(llvm::Triple::ArchType Arch) { - switch (Arch) { - case llvm::Triple::spirv: - return Intrinsic::spv_subgroup_prefix_bit_count; - case llvm::Triple::dxil: { - return Intrinsic::dx_wave_prefix_bit_count; - } - default: - llvm_unreachable( - "WavePrefixOp instruction not supported by target architecture"); - } -} - // Returns the mangled name for a builtin function that the SPIR-V backend // will expand into a spec Constant. static std::string getSpecConstantFunctionName(clang::QualType SpecConstantType, @@ -497,7 +476,8 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, "hlsl.AddUint64"); return Result; } - case Builtin::BI__builtin_hlsl_resource_getpointer: { + case Builtin::BI__builtin_hlsl_resource_getpointer: + case Builtin::BI__builtin_hlsl_resource_getpointer_typed: { Value *HandleOp = EmitScalarExpr(E->getArg(0)); Value *IndexOp = EmitScalarExpr(E->getArg(1)); @@ -545,7 +525,8 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, return Builder.CreateIntrinsic( RetTy, CGM.getHLSLRuntime().getSampleClampIntrinsic(), Args); } - case Builtin::BI__builtin_hlsl_resource_load_with_status: { + case Builtin::BI__builtin_hlsl_resource_load_with_status: + case Builtin::BI__builtin_hlsl_resource_load_with_status_typed: { Value *HandleOp = EmitScalarExpr(E->getArg(0)); Value *IndexOp = EmitScalarExpr(E->getArg(1)); @@ -571,8 +552,11 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, Args.push_back(HandleOp); Args.push_back(IndexOp); - if (RT->getAttrs().RawBuffer) { + if (RT->isRaw()) { Value *Offset = Builder.getInt32(0); + // The offset parameter needs to be poison for ByteAddressBuffer + if (!RT->isStructured()) + Offset = llvm::PoisonValue::get(Builder.getInt32Ty()); Args.push_back(Offset); } @@ -1013,9 +997,12 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, case Builtin::BI__builtin_hlsl_wave_active_max: { // Due to the use of variadic arguments, explicitly retreive argument Value *OpExpr = EmitScalarExpr(E->getArg(0)); - Intrinsic::ID IID = getWaveActiveMaxIntrinsic( - getTarget().getTriple().getArch(), CGM.getHLSLRuntime(), - E->getArg(0)->getType()); + QualType QT = E->getArg(0)->getType(); + Intrinsic::ID IID; + if (QT->isUnsignedIntegerType()) + IID = CGM.getHLSLRuntime().getWaveActiveUMaxIntrinsic(); + else + IID = CGM.getHLSLRuntime().getWaveActiveMaxIntrinsic(); return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration( &CGM.getModule(), IID, {OpExpr->getType()}), @@ -1024,9 +1011,12 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, case Builtin::BI__builtin_hlsl_wave_active_min: { // Due to the use of variadic arguments, explicitly retreive argument Value *OpExpr = EmitScalarExpr(E->getArg(0)); - Intrinsic::ID IID = getWaveActiveMinIntrinsic( - getTarget().getTriple().getArch(), CGM.getHLSLRuntime(), - E->getArg(0)->getType()); + QualType QT = E->getArg(0)->getType(); + Intrinsic::ID IID; + if (QT->isUnsignedIntegerType()) + IID = CGM.getHLSLRuntime().getWaveActiveUMinIntrinsic(); + else + IID = CGM.getHLSLRuntime().getWaveActiveMinIntrinsic(); return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration( &CGM.getModule(), IID, {OpExpr->getType()}), @@ -1070,6 +1060,15 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, {OpExpr->getType()}), ArrayRef{OpExpr, OpIndex}, "hlsl.wave.readlane"); } + case Builtin::BI__builtin_hlsl_wave_prefix_sum: { + Value *OpExpr = EmitScalarExpr(E->getArg(0)); + Intrinsic::ID IID = getWavePrefixSumIntrinsic( + getTarget().getTriple().getArch(), CGM.getHLSLRuntime(), + E->getArg(0)->getType()); + return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration( + &CGM.getModule(), IID, {OpExpr->getType()}), + ArrayRef{OpExpr}, "hlsl.wave.prefix.sum"); + } case Builtin::BI__builtin_hlsl_elementwise_sign: { auto *Arg0 = E->getArg(0); Value *Op0 = EmitScalarExpr(Arg0); diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp b/clang/lib/CodeGen/CGHLSLRuntime.cpp index cff2824d29dc5..7aa7ecbe211d5 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.cpp +++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp @@ -20,7 +20,7 @@ #include "HLSLBufferLayoutBuilder.h" #include "TargetInfo.h" #include "clang/AST/ASTContext.h" -#include "clang/AST/Attrs.inc" +#include "clang/AST/Attr.h" #include "clang/AST/Decl.h" #include "clang/AST/Expr.h" #include "clang/AST/HLSLResource.h" @@ -1556,10 +1556,7 @@ LValue CGHLSLRuntime::emitBufferMemberExpr(CodeGenFunction &CGF, auto *Field = dyn_cast(E->getMemberDecl()); assert(Field && "Unexpected access into HLSL buffer"); - // Get the field index for the struct. const RecordDecl *Rec = Field->getParent(); - unsigned FieldIdx = - CGM.getTypes().getCGRecordLayout(Rec).getLLVMFieldNo(Field); // Work out the buffer layout type to index into. QualType RecType = CGM.getContext().getCanonicalTagType(Rec); @@ -1571,6 +1568,22 @@ LValue CGHLSLRuntime::emitBufferMemberExpr(CodeGenFunction &CGF, llvm::StructType *LayoutTy = HLSLBufferLayoutBuilder(CGM).layOutStruct( RecType->getAsCanonical(), EmptyOffsets); + // Get the field index for the layout struct, accounting for padding. + unsigned FieldIdx = + CGM.getTypes().getCGRecordLayout(Rec).getLLVMFieldNo(Field); + assert(FieldIdx < LayoutTy->getNumElements() && + "Layout struct is smaller than member struct"); + unsigned Skipped = 0; + for (unsigned I = 0; I <= FieldIdx;) { + llvm::Type *ElementTy = LayoutTy->getElementType(I + Skipped); + if (CGF.CGM.getTargetCodeGenInfo().isHLSLPadding(ElementTy)) + ++Skipped; + else + ++I; + } + FieldIdx += Skipped; + assert(FieldIdx < LayoutTy->getNumElements() && "Access out of bounds"); + // Now index into the struct, making sure that the type we return is the // buffer layout type rather than the original type in the AST. QualType FieldType = Field->getType(); diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h index 03a64ed0fa6bb..c13f91afa6a39 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.h +++ b/clang/lib/CodeGen/CGHLSLRuntime.h @@ -146,6 +146,10 @@ class CGHLSLRuntime { GENERATE_HLSL_INTRINSIC_FUNCTION(Dot4AddU8Packed, dot4add_u8packed) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveAllTrue, wave_all) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveAnyTrue, wave_any) + GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveMax, wave_reduce_max) + GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveUMax, wave_reduce_umax) + GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveMin, wave_reduce_min) + GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveUMin, wave_reduce_umin) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveCountBits, wave_active_countbits) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveGetLaneCount, wave_get_lane_count) diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp index d6706dc77d63f..0d7714ecbcc76 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp @@ -2373,6 +2373,7 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(const OMPRequiresDecl *D) { case OffloadArch::GFX1151: case OffloadArch::GFX1152: case OffloadArch::GFX1153: + case OffloadArch::GFX1170: case OffloadArch::GFX12_GENERIC: case OffloadArch::GFX1200: case OffloadArch::GFX1201: diff --git a/clang/lib/CodeGen/CGVTables.cpp b/clang/lib/CodeGen/CGVTables.cpp index 46f00192c5735..3891697a986e4 100644 --- a/clang/lib/CodeGen/CGVTables.cpp +++ b/clang/lib/CodeGen/CGVTables.cpp @@ -140,19 +140,32 @@ static void resolveTopLevelMetadata(llvm::Function *Fn, // Find all llvm.dbg.declare intrinsics and resolve the DILocalVariable nodes // they are referencing. + // + // DIDerivedTypes referring to incomplete Clang types, or + // LLVM enumeration types representing complete enums with no definition + // may be still unresolved. As they can't be cloned, keep references + // to the types from the base subprogram. + // FIXME: As a result, variables of cloned subprogram may refer to local types + // from base subprogram. In such case, type locality information is damaged. + // Find a way to enable cloning of all local types. + auto PrepareVariableMapping = [&VMap](llvm::DILocalVariable *DILocal) { + if (DILocal->isResolved()) + return; + + if (llvm::DIType *Ty = DILocal->getType(); Ty && !Ty->isResolved()) + VMap.MD()[Ty].reset(Ty); + + DILocal->resolve(); + }; + for (auto &BB : *Fn) { for (auto &I : BB) { for (llvm::DbgVariableRecord &DVR : - llvm::filterDbgVars(I.getDbgRecordRange())) { - auto *DILocal = DVR.getVariable(); - if (!DILocal->isResolved()) - DILocal->resolve(); - } - if (auto *DII = dyn_cast(&I)) { - auto *DILocal = DII->getVariable(); - if (!DILocal->isResolved()) - DILocal->resolve(); - } + llvm::filterDbgVars(I.getDbgRecordRange())) + PrepareVariableMapping(DVR.getVariable()); + + if (auto *DII = dyn_cast(&I)) + PrepareVariableMapping(DII->getVariable()); } } } diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index 61128316963ac..2d3507447804a 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -178,7 +178,6 @@ void CodeGenFunction::CGFPOptionsRAII::ConstructorHelper(FPOptions FPFeatures) { if (OldValue != NewValue) CGF.CurFn->addFnAttr(Name, llvm::toStringRef(NewValue)); }; - mergeFnAttrValue("no-infs-fp-math", FPFeatures.getNoHonorInfs()); mergeFnAttrValue("no-nans-fp-math", FPFeatures.getNoHonorNaNs()); mergeFnAttrValue("no-signed-zeros-fp-math", FPFeatures.getNoSignedZero()); } @@ -1244,7 +1243,7 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy, ReturnValue = Address(Addr, ConvertType(RetTy), CGM.getNaturalTypeAlignment(RetTy), KnownNonNull); } else { - ReturnValue = CreateIRTemp(RetTy, "retval"); + ReturnValue = CreateIRTempWithoutCast(RetTy, "retval"); // Tell the epilog emitter to autorelease the result. We do this // now so that various specialized functions can suppress it @@ -3025,6 +3024,8 @@ void CodeGenFunction::EmitMultiVersionResolver( return; case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: EmitRISCVMultiVersionResolver(Resolver, Options); return; diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 226950ab599e3..f769fee227878 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -447,6 +447,12 @@ class CodeGenFunction : public CodeGenTypeCache { return PostAllocaInsertPt; } + // Try to preserve the source's name to make IR more readable. + llvm::Value *performAddrSpaceCast(llvm::Value *Src, llvm::Type *DestTy) { + return Builder.CreateAddrSpaceCast( + Src, DestTy, Src->hasName() ? Src->getName() + ".ascast" : ""); + } + /// API for captured statement code generation. class CGCapturedStmtInfo { public: @@ -2904,15 +2910,15 @@ class CodeGenFunction : public CodeGenTypeCache { RawAddress CreateDefaultAlignTempAlloca(llvm::Type *Ty, const Twine &Name = "tmp"); - /// CreateIRTemp - Create a temporary IR object of the given type, with - /// appropriate alignment. This routine should only be used when an temporary - /// value needs to be stored into an alloca (for example, to avoid explicit - /// PHI construction), but the type is the IR type, not the type appropriate - /// for storing in memory. + /// CreateIRTempWithoutCast - Create a temporary IR object of the given type, + /// with appropriate alignment. This routine should only be used when an + /// temporary value needs to be stored into an alloca (for example, to avoid + /// explicit PHI construction), but the type is the IR type, not the type + /// appropriate for storing in memory. /// /// That is, this is exactly equivalent to CreateMemTemp, but calling /// ConvertType instead of ConvertTypeForMem. - RawAddress CreateIRTemp(QualType T, const Twine &Name = "tmp"); + RawAddress CreateIRTempWithoutCast(QualType T, const Twine &Name = "tmp"); /// CreateMemTemp - Create a temporary memory object of the given type, with /// appropriate alignmen and cast it to the default address space. Returns @@ -4439,6 +4445,7 @@ class CodeGenFunction : public CodeGenTypeCache { LValue EmitArraySectionExpr(const ArraySectionExpr *E, bool IsLowerBound = true); LValue EmitExtVectorElementExpr(const ExtVectorElementExpr *E); + LValue EmitMatrixElementExpr(const MatrixElementExpr *E); LValue EmitMemberExpr(const MemberExpr *E); LValue EmitObjCIsaExpr(const ObjCIsaExpr *E); LValue EmitCompoundLiteralLValue(const CompoundLiteralExpr *E); diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index d50c9605a30b3..65f5468c4b998 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -61,6 +61,7 @@ #include "llvm/IR/ProfileSummary.h" #include "llvm/ProfileData/InstrProfReader.h" #include "llvm/ProfileData/SampleProf.h" +#include "llvm/Support/ARMBuildAttributes.h" #include "llvm/Support/CRC.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" @@ -224,7 +225,9 @@ createTargetCodeGenInfo(CodeGenModule &CGM) { return createMSP430TargetCodeGenInfo(CGM); case llvm::Triple::riscv32: - case llvm::Triple::riscv64: { + case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: { StringRef ABIStr = Target.getABI(); unsigned XLen = Target.getPointerWidth(LangAS::Default); unsigned ABIFLen = 0; @@ -1413,6 +1416,36 @@ void CodeGenModule::Release() { } } } + if ((T.isARM() || T.isThumb()) && getTriple().isTargetAEABI() && + getTriple().isOSBinFormatELF()) { + uint32_t TagVal = 0; + llvm::Module::ModFlagBehavior DenormalTagBehavior = llvm::Module::Max; + if (getCodeGenOpts().FPDenormalMode == + llvm::DenormalMode::getPositiveZero()) { + TagVal = llvm::ARMBuildAttrs::PositiveZero; + } else if (getCodeGenOpts().FPDenormalMode == + llvm::DenormalMode::getIEEE()) { + TagVal = llvm::ARMBuildAttrs::IEEEDenormals; + DenormalTagBehavior = llvm::Module::Override; + } else if (getCodeGenOpts().FPDenormalMode == + llvm::DenormalMode::getPreserveSign()) { + TagVal = llvm::ARMBuildAttrs::PreserveFPSign; + } + getModule().addModuleFlag(DenormalTagBehavior, "arm-eabi-fp-denormal", + TagVal); + + if (getLangOpts().getDefaultExceptionMode() != + LangOptions::FPExceptionModeKind::FPE_Ignore) + getModule().addModuleFlag(llvm::Module::Min, "arm-eabi-fp-exceptions", + llvm::ARMBuildAttrs::Allowed); + + if (getLangOpts().NoHonorNaNs && getLangOpts().NoHonorInfs) + TagVal = llvm::ARMBuildAttrs::AllowIEEENormal; + else + TagVal = llvm::ARMBuildAttrs::AllowIEEE754; + getModule().addModuleFlag(llvm::Module::Min, "arm-eabi-fp-number-model", + TagVal); + } if (CodeGenOpts.StackClashProtector) getModule().addModuleFlag( @@ -5688,11 +5721,9 @@ CodeGenModule::GetOrCreateLLVMGlobal(StringRef MangledName, llvm::Type *Ty, D ? D->getType().getAddressSpace() : (LangOpts.OpenCL ? LangAS::opencl_global : LangAS::Default); assert(getContext().getTargetAddressSpace(ExpectedAS) == TargetAS); - if (DAddrSpace != ExpectedAS) { - return getTargetCodeGenInfo().performAddrSpaceCast( - *this, GV, DAddrSpace, - llvm::PointerType::get(getLLVMContext(), TargetAS)); - } + if (DAddrSpace != ExpectedAS) + return performAddrSpaceCast( + GV, llvm::PointerType::get(getLLVMContext(), TargetAS)); return GV; } @@ -5924,11 +5955,10 @@ castStringLiteralToDefaultAddressSpace(CodeGenModule &CGM, if (!CGM.getLangOpts().OpenCL) { auto AS = CGM.GetGlobalConstantAddressSpace(); if (AS != LangAS::Default) - Cast = CGM.getTargetCodeGenInfo().performAddrSpaceCast( - CGM, GV, AS, - llvm::PointerType::get( - CGM.getLLVMContext(), - CGM.getContext().getTargetAddressSpace(LangAS::Default))); + Cast = CGM.performAddrSpaceCast( + GV, llvm::PointerType::get( + CGM.getLLVMContext(), + CGM.getContext().getTargetAddressSpace(LangAS::Default))); } return Cast; } @@ -7351,11 +7381,10 @@ ConstantAddress CodeGenModule::GetAddrOfGlobalTemporary( setTLSMode(GV, *VD); llvm::Constant *CV = GV; if (AddrSpace != LangAS::Default) - CV = getTargetCodeGenInfo().performAddrSpaceCast( - *this, GV, AddrSpace, - llvm::PointerType::get( - getLLVMContext(), - getContext().getTargetAddressSpace(LangAS::Default))); + CV = performAddrSpaceCast( + GV, llvm::PointerType::get( + getLLVMContext(), + getContext().getTargetAddressSpace(LangAS::Default))); // Update the map with the new temporary. If we created a placeholder above, // replace it with the new global now. diff --git a/clang/lib/CodeGen/CodeGenModule.h b/clang/lib/CodeGen/CodeGenModule.h index cc18e21d45759..3ed1dd7a57225 100644 --- a/clang/lib/CodeGen/CodeGenModule.h +++ b/clang/lib/CodeGen/CodeGenModule.h @@ -1872,6 +1872,13 @@ class CodeGenModule : public CodeGenTypeCache { return TrapReasonBuilder(&getDiags(), DiagID, TR); } + llvm::Constant *performAddrSpaceCast(llvm::Constant *Src, + llvm::Type *DestTy) { + // Since target may map different address spaces in AST to the same address + // space, an address space conversion may end up as a bitcast. + return llvm::ConstantExpr::getPointerCast(Src, DestTy); + } + std::optional StackProtectorAttribute(const Decl *D) const; diff --git a/clang/lib/CodeGen/CodeGenPGO.cpp b/clang/lib/CodeGen/CodeGenPGO.cpp index 4921eba7934a2..59faa3aef2460 100644 --- a/clang/lib/CodeGen/CodeGenPGO.cpp +++ b/clang/lib/CodeGen/CodeGenPGO.cpp @@ -1505,7 +1505,7 @@ void CodeGenFunction::maybeCreateMCDCCondBitmap() { // Note: This doesn't initialize Addrs in invalidated Decisions. for (auto *MCDCCondBitmapAddr : PGO->getMCDCCondBitmapAddrArray(Builder)) *MCDCCondBitmapAddr = - CreateIRTemp(getContext().UnsignedIntTy, "mcdc.addr"); + CreateIRTempWithoutCast(getContext().UnsignedIntTy, "mcdc.addr"); } } bool CodeGenFunction::isMCDCDecisionExpr(const Expr *E) const { diff --git a/clang/lib/CodeGen/CodeGenTypes.cpp b/clang/lib/CodeGen/CodeGenTypes.cpp index 0e1131d586433..fd7a8929a9be9 100644 --- a/clang/lib/CodeGen/CodeGenTypes.cpp +++ b/clang/lib/CodeGen/CodeGenTypes.cpp @@ -105,8 +105,13 @@ llvm::Type *CodeGenTypes::ConvertTypeForMem(QualType T) { const Type *Ty = Context.getCanonicalType(T).getTypePtr(); const ConstantMatrixType *MT = cast(Ty); llvm::Type *IRElemTy = ConvertType(MT->getElementType()); - if (Context.getLangOpts().HLSL && T->isConstantMatrixBoolType()) - IRElemTy = ConvertTypeForMem(Context.BoolTy); + if (Context.getLangOpts().HLSL) { + if (T->isConstantMatrixBoolType()) + IRElemTy = ConvertTypeForMem(Context.BoolTy); + llvm::Type *VecTy = + llvm::FixedVectorType::get(IRElemTy, MT->getNumColumns()); + return llvm::ArrayType::get(VecTy, MT->getNumRows()); + } return llvm::ArrayType::get(IRElemTy, MT->getNumElementsFlattened()); } diff --git a/clang/lib/CodeGen/ItaniumCXXABI.cpp b/clang/lib/CodeGen/ItaniumCXXABI.cpp index a6c80cd083bb8..e3e071d827b92 100644 --- a/clang/lib/CodeGen/ItaniumCXXABI.cpp +++ b/clang/lib/CodeGen/ItaniumCXXABI.cpp @@ -35,6 +35,7 @@ #include "llvm/IR/Instructions.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/Value.h" +#include "llvm/Support/ConvertEBCDIC.h" #include "llvm/Support/ScopedPrinter.h" #include @@ -3619,8 +3620,17 @@ llvm::GlobalVariable *ItaniumRTTIBuilder::GetAddrOfTypeName( // We know that the mangled name of the type starts at index 4 of the // mangled name of the typename, so we can just index into it in order to // get the mangled name of the type. - llvm::Constant *Init = llvm::ConstantDataArray::getString(VMContext, - Name.substr(4)); + llvm::Constant *Init; + if (CGM.getTriple().isOSzOS()) { + // On z/OS, typename is stored as 2 encodings: EBCDIC followed by ASCII. + SmallString<256> DualEncodedName; + llvm::ConverterEBCDIC::convertToEBCDIC(Name.substr(4), DualEncodedName); + DualEncodedName += '\0'; + DualEncodedName += Name.substr(4); + Init = llvm::ConstantDataArray::getString(VMContext, DualEncodedName); + } else + Init = llvm::ConstantDataArray::getString(VMContext, Name.substr(4)); + auto Align = CGM.getContext().getTypeAlignInChars(CGM.getContext().CharTy); llvm::GlobalVariable *GV = CGM.CreateOrReplaceCXXRuntimeVariable( diff --git a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp index a096ed27a788e..d3a2b08fb7a98 100644 --- a/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp @@ -12,6 +12,7 @@ #include "CGBuiltin.h" #include "CodeGenFunction.h" +#include "TargetInfo.h" #include "clang/Basic/DiagnosticFrontend.h" #include "clang/Basic/SyncScope.h" #include "clang/Basic/TargetBuiltins.h" @@ -21,6 +22,7 @@ #include "llvm/IR/IntrinsicsR600.h" #include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/Support/AMDGPUAddrSpace.h" +#include "llvm/Support/AtomicOrdering.h" using namespace clang; using namespace CodeGen; @@ -272,6 +274,25 @@ static inline StringRef mapScopeToSPIRV(StringRef AMDGCNScope) { return AMDGCNScope; } +static llvm::AtomicOrdering mapCABIAtomicOrdering(unsigned AO) { + // Map C11/C++11 memory ordering to LLVM memory ordering + assert(llvm::isValidAtomicOrderingCABI(AO)); + switch (static_cast(AO)) { + case llvm::AtomicOrderingCABI::acquire: + case llvm::AtomicOrderingCABI::consume: + return llvm::AtomicOrdering::Acquire; + case llvm::AtomicOrderingCABI::release: + return llvm::AtomicOrdering::Release; + case llvm::AtomicOrderingCABI::acq_rel: + return llvm::AtomicOrdering::AcquireRelease; + case llvm::AtomicOrderingCABI::seq_cst: + return llvm::AtomicOrdering::SequentiallyConsistent; + case llvm::AtomicOrderingCABI::relaxed: + return llvm::AtomicOrdering::Monotonic; + } + llvm_unreachable("Unknown AtomicOrderingCABI enum"); +} + // For processing memory ordering and memory scope arguments of various // amdgcn builtins. // \p Order takes a C++11 compatible memory-ordering specifier and converts @@ -284,25 +305,7 @@ void CodeGenFunction::ProcessOrderScopeAMDGCN(Value *Order, Value *Scope, int ord = cast(Order)->getZExtValue(); // Map C11/C++11 memory ordering to LLVM memory ordering - assert(llvm::isValidAtomicOrderingCABI(ord)); - switch (static_cast(ord)) { - case llvm::AtomicOrderingCABI::acquire: - case llvm::AtomicOrderingCABI::consume: - AO = llvm::AtomicOrdering::Acquire; - break; - case llvm::AtomicOrderingCABI::release: - AO = llvm::AtomicOrdering::Release; - break; - case llvm::AtomicOrderingCABI::acq_rel: - AO = llvm::AtomicOrdering::AcquireRelease; - break; - case llvm::AtomicOrderingCABI::seq_cst: - AO = llvm::AtomicOrdering::SequentiallyConsistent; - break; - case llvm::AtomicOrderingCABI::relaxed: - AO = llvm::AtomicOrdering::Monotonic; - break; - } + AO = mapCABIAtomicOrdering(ord); // Some of the atomic builtins take the scope as a string name. StringRef scp; @@ -818,11 +821,24 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, break; } + LLVMContext &Ctx = CGM.getLLVMContext(); llvm::Type *LoadTy = ConvertType(E->getType()); llvm::Value *Addr = EmitScalarExpr(E->getArg(0)); - llvm::Value *Val = EmitScalarExpr(E->getArg(1)); + + auto *AOExpr = cast(EmitScalarExpr(E->getArg(1))); + auto *ScopeExpr = cast(EmitScalarExpr(E->getArg(2))); + + auto Scope = static_cast(ScopeExpr->getZExtValue()); + llvm::AtomicOrdering AO = mapCABIAtomicOrdering(AOExpr->getZExtValue()); + + StringRef ScopeStr = CGM.getTargetCodeGenInfo().getLLVMSyncScopeStr( + CGM.getLangOpts(), Scope, AO); + + llvm::MDNode *MD = + llvm::MDNode::get(Ctx, {llvm::MDString::get(Ctx, ScopeStr)}); + llvm::Value *ScopeMD = llvm::MetadataAsValue::get(Ctx, MD); llvm::Function *F = CGM.getIntrinsic(IID, {LoadTy}); - return Builder.CreateCall(F, {Addr, Val}); + return Builder.CreateCall(F, {Addr, AOExpr, ScopeMD}); } case AMDGPU::BI__builtin_amdgcn_cluster_load_b32: case AMDGPU::BI__builtin_amdgcn_cluster_load_b64: diff --git a/clang/lib/CodeGen/TargetBuiltins/WebAssembly.cpp b/clang/lib/CodeGen/TargetBuiltins/WebAssembly.cpp index 1a1889a4139d3..edaba6e5998fc 100644 --- a/clang/lib/CodeGen/TargetBuiltins/WebAssembly.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/WebAssembly.cpp @@ -633,8 +633,8 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID, Function *Callee; if (E->getArg(1)->getType().isWebAssemblyExternrefType()) Callee = CGM.getIntrinsic(Intrinsic::wasm_table_grow_externref); - else if (E->getArg(2)->getType().isWebAssemblyFuncrefType()) - Callee = CGM.getIntrinsic(Intrinsic::wasm_table_fill_funcref); + else if (E->getArg(1)->getType().isWebAssemblyFuncrefType()) + Callee = CGM.getIntrinsic(Intrinsic::wasm_table_grow_funcref); else llvm_unreachable( "Unexpected reference type for __builtin_wasm_table_grow"); diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 342a3af0ac1ee..dc0b392fd37f7 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -148,25 +148,11 @@ LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM, return D ? D->getType().getAddressSpace() : LangAS::Default; } -llvm::Value *TargetCodeGenInfo::performAddrSpaceCast( - CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr, - llvm::Type *DestTy, bool isNonNull) const { - // Since target may map different address spaces in AST to the same address - // space, an address space conversion may end up as a bitcast. - if (auto *C = dyn_cast(Src)) - return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestTy); - // Try to preserve the source's name to make IR more readable. - return CGF.Builder.CreateAddrSpaceCast( - Src, DestTy, Src->hasName() ? Src->getName() + ".ascast" : ""); -} - -llvm::Constant * -TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src, - LangAS SrcAddr, - llvm::Type *DestTy) const { - // Since target may map different address spaces in AST to the same address - // space, an address space conversion may end up as a bitcast. - return llvm::ConstantExpr::getPointerCast(Src, DestTy); +StringRef +TargetCodeGenInfo::getLLVMSyncScopeStr(const LangOptions &LangOpts, + SyncScope Scope, + llvm::AtomicOrdering Ordering) const { + return ""; /* default sync scope */ } llvm::SyncScope::ID @@ -174,7 +160,8 @@ TargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts, SyncScope Scope, llvm::AtomicOrdering Ordering, llvm::LLVMContext &Ctx) const { - return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */ + return Ctx.getOrInsertSyncScopeID( + getLLVMSyncScopeStr(LangOpts, Scope, Ordering)); } void TargetCodeGenInfo::addStackProbeTargetAttributes( diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h index db06584d766bf..98ee894fe557f 100644 --- a/clang/lib/CodeGen/TargetInfo.h +++ b/clang/lib/CodeGen/TargetInfo.h @@ -321,41 +321,21 @@ class TargetCodeGenInfo { /// Get the AST address space for alloca. virtual LangAS getASTAllocaAddressSpace() const { return LangAS::Default; } - Address performAddrSpaceCast(CodeGen::CodeGenFunction &CGF, Address Addr, - LangAS SrcAddr, llvm::Type *DestTy, - bool IsNonNull = false) const; - - /// Perform address space cast of an expression of pointer type. - /// \param V is the LLVM value to be casted to another address space. - /// \param SrcAddr is the language address space of \p V. - /// \param DestAddr is the targeted language address space. - /// \param DestTy is the destination LLVM pointer type. - /// \param IsNonNull is the flag indicating \p V is known to be non null. - virtual llvm::Value *performAddrSpaceCast(CodeGen::CodeGenFunction &CGF, - llvm::Value *V, LangAS SrcAddr, - llvm::Type *DestTy, - bool IsNonNull = false) const; - - /// Perform address space cast of a constant expression of pointer type. - /// \param V is the LLVM constant to be casted to another address space. - /// \param SrcAddr is the language address space of \p V. - /// \param DestAddr is the targeted language address space. - /// \param DestTy is the destination LLVM pointer type. - virtual llvm::Constant *performAddrSpaceCast(CodeGenModule &CGM, - llvm::Constant *V, - LangAS SrcAddr, - llvm::Type *DestTy) const; - /// Get address space of pointer parameter for __cxa_atexit. virtual LangAS getAddrSpaceOfCxaAtexitPtrParam() const { return LangAS::Default; } - /// Get the syncscope used in LLVM IR. - virtual llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions &LangOpts, - SyncScope Scope, - llvm::AtomicOrdering Ordering, - llvm::LLVMContext &Ctx) const; + /// Get the syncscope used in LLVM IR as a string + virtual StringRef getLLVMSyncScopeStr(const LangOptions &LangOpts, + SyncScope Scope, + llvm::AtomicOrdering Ordering) const; + + /// Get the syncscope used in LLVM IR as a SyncScope ID. + llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions &LangOpts, + SyncScope Scope, + llvm::AtomicOrdering Ordering, + llvm::LLVMContext &Ctx) const; /// Allow the target to apply other metadata to an atomic instruction virtual void setTargetAtomicMetadata(CodeGenFunction &CGF, diff --git a/clang/lib/CodeGen/Targets/AMDGPU.cpp b/clang/lib/CodeGen/Targets/AMDGPU.cpp index 7ba32b92cfd55..4ac7f42289d6d 100644 --- a/clang/lib/CodeGen/Targets/AMDGPU.cpp +++ b/clang/lib/CodeGen/Targets/AMDGPU.cpp @@ -310,10 +310,8 @@ class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo { } LangAS getGlobalVarAddressSpace(CodeGenModule &CGM, const VarDecl *D) const override; - llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions &LangOpts, - SyncScope Scope, - llvm::AtomicOrdering Ordering, - llvm::LLVMContext &Ctx) const override; + StringRef getLLVMSyncScopeStr(const LangOptions &LangOpts, SyncScope Scope, + llvm::AtomicOrdering Ordering) const override; void setTargetAtomicMetadata(CodeGenFunction &CGF, llvm::Instruction &AtomicInst, const AtomicExpr *Expr = nullptr) const override; @@ -493,55 +491,41 @@ AMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM, return DefaultGlobalAS; } -llvm::SyncScope::ID -AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts, - SyncScope Scope, - llvm::AtomicOrdering Ordering, - llvm::LLVMContext &Ctx) const { - std::string Name; +StringRef AMDGPUTargetCodeGenInfo::getLLVMSyncScopeStr( + const LangOptions &LangOpts, SyncScope Scope, + llvm::AtomicOrdering Ordering) const { + + // OpenCL assumes by default that atomic scopes are per-address space for + // non-sequentially consistent operations. + bool IsOneAs = (Scope >= SyncScope::OpenCLWorkGroup && + Scope <= SyncScope::OpenCLSubGroup && + Ordering != llvm::AtomicOrdering::SequentiallyConsistent); + switch (Scope) { case SyncScope::HIPSingleThread: case SyncScope::SingleScope: - Name = "singlethread"; - break; + return IsOneAs ? "singlethread-one-as" : "singlethread"; case SyncScope::HIPWavefront: case SyncScope::OpenCLSubGroup: case SyncScope::WavefrontScope: - Name = "wavefront"; - break; + return IsOneAs ? "wavefront-one-as" : "wavefront"; case SyncScope::HIPCluster: case SyncScope::ClusterScope: - Name = "cluster"; - break; + return IsOneAs ? "cluster-one-as" : "cluster"; case SyncScope::HIPWorkgroup: case SyncScope::OpenCLWorkGroup: case SyncScope::WorkgroupScope: - Name = "workgroup"; - break; + return IsOneAs ? "workgroup-one-as" : "workgroup"; case SyncScope::HIPAgent: case SyncScope::OpenCLDevice: case SyncScope::DeviceScope: - Name = "agent"; - break; + return IsOneAs ? "agent-one-as" : "agent"; case SyncScope::SystemScope: case SyncScope::HIPSystem: case SyncScope::OpenCLAllSVMDevices: - Name = ""; - break; - } - - // OpenCL assumes by default that atomic scopes are per-address space for - // non-sequentially consistent operations. - if (Scope >= SyncScope::OpenCLWorkGroup && - Scope <= SyncScope::OpenCLSubGroup && - Ordering != llvm::AtomicOrdering::SequentiallyConsistent) { - if (!Name.empty()) - Name = Twine(Twine(Name) + Twine("-")).str(); - - Name = Twine(Twine(Name) + Twine("one-as")).str(); + return IsOneAs ? "one-as" : ""; } - - return Ctx.getOrInsertSyncScopeID(Name); + llvm_unreachable("Unknown SyncScope enum"); } void AMDGPUTargetCodeGenInfo::setTargetAtomicMetadata( diff --git a/clang/lib/CodeGen/Targets/SPIR.cpp b/clang/lib/CodeGen/Targets/SPIR.cpp index 32998bb5d60d5..52d019b855dbc 100644 --- a/clang/lib/CodeGen/Targets/SPIR.cpp +++ b/clang/lib/CodeGen/Targets/SPIR.cpp @@ -131,42 +131,13 @@ class SPIRVTargetCodeGenInfo : public CommonSPIRTargetCodeGenInfo { const VarDecl *D) const override; void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const override; - llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions &LangOpts, - SyncScope Scope, - llvm::AtomicOrdering Ordering, - llvm::LLVMContext &Ctx) const override; + StringRef getLLVMSyncScopeStr(const LangOptions &LangOpts, SyncScope Scope, + llvm::AtomicOrdering Ordering) const override; bool supportsLibCall() const override { return getABIInfo().getTarget().getTriple().getVendor() != llvm::Triple::AMD; } }; - -inline StringRef mapClangSyncScopeToLLVM(SyncScope Scope) { - switch (Scope) { - case SyncScope::HIPSingleThread: - case SyncScope::SingleScope: - return "singlethread"; - case SyncScope::HIPWavefront: - case SyncScope::OpenCLSubGroup: - case SyncScope::WavefrontScope: - return "subgroup"; - case SyncScope::HIPCluster: - case SyncScope::ClusterScope: - case SyncScope::HIPWorkgroup: - case SyncScope::OpenCLWorkGroup: - case SyncScope::WorkgroupScope: - return "workgroup"; - case SyncScope::HIPAgent: - case SyncScope::OpenCLDevice: - case SyncScope::DeviceScope: - return "device"; - case SyncScope::SystemScope: - case SyncScope::HIPSystem: - case SyncScope::OpenCLAllSVMDevices: - return ""; - } - return ""; -} } // End anonymous namespace. void CommonSPIRABIInfo::setCCs() { @@ -563,11 +534,32 @@ void SPIRVTargetCodeGenInfo::setTargetAttributes( llvm::MDNode::get(M.getLLVMContext(), AttrMDArgs)); } -llvm::SyncScope::ID -SPIRVTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &, SyncScope Scope, - llvm::AtomicOrdering, - llvm::LLVMContext &Ctx) const { - return Ctx.getOrInsertSyncScopeID(mapClangSyncScopeToLLVM(Scope)); +StringRef SPIRVTargetCodeGenInfo::getLLVMSyncScopeStr( + const LangOptions &, SyncScope Scope, llvm::AtomicOrdering) const { + switch (Scope) { + case SyncScope::HIPSingleThread: + case SyncScope::SingleScope: + return "singlethread"; + case SyncScope::HIPWavefront: + case SyncScope::OpenCLSubGroup: + case SyncScope::WavefrontScope: + return "subgroup"; + case SyncScope::HIPCluster: + case SyncScope::ClusterScope: + case SyncScope::HIPWorkgroup: + case SyncScope::OpenCLWorkGroup: + case SyncScope::WorkgroupScope: + return "workgroup"; + case SyncScope::HIPAgent: + case SyncScope::OpenCLDevice: + case SyncScope::DeviceScope: + return "device"; + case SyncScope::SystemScope: + case SyncScope::HIPSystem: + case SyncScope::OpenCLAllSVMDevices: + return ""; + } + return ""; } /// Construct a SPIR-V target extension type for the given OpenCL image type. diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index eb3f9cbea2845..a55c5033b57cf 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -801,14 +801,30 @@ static llvm::Triple computeTargetTriple(const Driver &D, ArchName, /*EnableExperimentalExtensions=*/true); if (!llvm::errorToBool(ISAInfo.takeError())) { unsigned XLen = (*ISAInfo)->getXLen(); - if (XLen == 32) - Target.setArch(llvm::Triple::riscv32); - else if (XLen == 64) - Target.setArch(llvm::Triple::riscv64); + if (XLen == 32) { + if (Target.isLittleEndian()) + Target.setArch(llvm::Triple::riscv32); + else + Target.setArch(llvm::Triple::riscv32be); + } else if (XLen == 64) { + if (Target.isLittleEndian()) + Target.setArch(llvm::Triple::riscv64); + else + Target.setArch(llvm::Triple::riscv64be); + } } } } + if (Target.getArch() == llvm::Triple::riscv32be || + Target.getArch() == llvm::Triple::riscv64be) { + static bool WarnedRISCVBE = false; + if (!WarnedRISCVBE) { + D.Diag(diag::warn_drv_riscv_be_experimental); + WarnedRISCVBE = true; + } + } + return Target; } @@ -2866,8 +2882,8 @@ void Driver::BuildUniversalActions(Compilation &C, const ToolChain &TC, } } -bool Driver::DiagnoseInputExistence(const DerivedArgList &Args, StringRef Value, - types::ID Ty, bool TypoCorrect) const { +bool Driver::DiagnoseInputExistence(StringRef Value, types::ID Ty, + bool TypoCorrect) const { if (!getCheckInputsExist()) return true; @@ -3106,12 +3122,12 @@ void Driver::BuildInputs(const ToolChain &TC, DerivedArgList &Args, Args.hasArgNoClaim(options::OPT_hipstdpar)) Ty = types::TY_HIP; - if (DiagnoseInputExistence(Args, Value, Ty, /*TypoCorrect=*/true)) + if (DiagnoseInputExistence(Value, Ty, /*TypoCorrect=*/true)) Inputs.push_back(std::make_pair(Ty, A)); } else if (A->getOption().matches(options::OPT__SLASH_Tc)) { StringRef Value = A->getValue(); - if (DiagnoseInputExistence(Args, Value, types::TY_C, + if (DiagnoseInputExistence(Value, types::TY_C, /*TypoCorrect=*/false)) { Arg *InputArg = MakeInputArg(Args, Opts, A->getValue()); Inputs.push_back(std::make_pair(types::TY_C, InputArg)); @@ -3119,7 +3135,7 @@ void Driver::BuildInputs(const ToolChain &TC, DerivedArgList &Args, A->claim(); } else if (A->getOption().matches(options::OPT__SLASH_Tp)) { StringRef Value = A->getValue(); - if (DiagnoseInputExistence(Args, Value, types::TY_CXX, + if (DiagnoseInputExistence(Value, types::TY_CXX, /*TypoCorrect=*/false)) { Arg *InputArg = MakeInputArg(Args, Opts, A->getValue()); Inputs.push_back(std::make_pair(types::TY_CXX, InputArg)); @@ -4938,21 +4954,26 @@ Action *Driver::BuildOffloadingActions(Compilation &C, // Compiling HIP in device-only non-RDC mode requires linking each action // individually. for (Action *&A : DeviceActions) { - bool IsAMDGCNSPIRV = A->getOffloadingToolChain() && - A->getOffloadingToolChain()->getTriple().getOS() == - llvm::Triple::OSType::AMDHSA && - A->getOffloadingToolChain()->getTriple().isSPIRV(); + auto *OffloadTriple = A->getOffloadingToolChain() + ? &A->getOffloadingToolChain()->getTriple() + : nullptr; + bool IsHIPSPV = + OffloadTriple && OffloadTriple->isSPIRV() && + (OffloadTriple->getOS() == llvm::Triple::OSType::AMDHSA || + OffloadTriple->getOS() == llvm::Triple::OSType::ChipStar); bool UseSPIRVBackend = Args.hasFlag(options::OPT_use_spirv_backend, options::OPT_no_use_spirv_backend, /*Default=*/false); - // Special handling for the HIP SPIR-V toolchain in device-only. + // Special handling for the HIP SPIR-V toolchains in device-only. // The translator path has a linking step, whereas the SPIR-V backend path // does not to avoid any external dependency such as spirv-link. The // linking step is skipped for the SPIR-V backend path. - bool IsAMDGCNSPIRVWithBackend = IsAMDGCNSPIRV && UseSPIRVBackend; + bool IsAMDGCNSPIRVWithBackend = + IsHIPSPV && OffloadTriple->getOS() == llvm::Triple::OSType::AMDHSA && + UseSPIRVBackend; - if ((A->getType() != types::TY_Object && !IsAMDGCNSPIRV && + if ((A->getType() != types::TY_Object && !IsHIPSPV && A->getType() != types::TY_LTO_BC) || HIPRelocatableObj || !HIPNoRDC || !offloadDeviceOnly() || (IsAMDGCNSPIRVWithBackend && offloadDeviceOnly())) @@ -6961,6 +6982,9 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, case llvm::Triple::ShaderModel: TC = std::make_unique(*this, Target, Args); break; + case llvm::Triple::ChipStar: + TC = std::make_unique(*this, Target, Args); + break; default: // Of these targets, Hexagon is the only one that might have // an OS of Linux, in which case it got handled above already. @@ -6993,6 +7017,8 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, break; case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: TC = std::make_unique(*this, Target, Args); break; case llvm::Triple::ve: @@ -7010,6 +7036,8 @@ const ToolChain &Driver::getToolChain(const ArgList &Args, TC = std::make_unique(*this, Target, Args); else if (Target.isOSBinFormatELF()) TC = std::make_unique(*this, Target, Args); + else if (Target.isAppleFirmware()) + TC = std::make_unique(*this, Target, Args); else if (Target.isAppleMachO()) TC = std::make_unique(*this, Target, Args); else if (Target.isOSBinFormatMachO()) diff --git a/clang/lib/Driver/SanitizerArgs.cpp b/clang/lib/Driver/SanitizerArgs.cpp index 7c51d66645198..294c9ad2705dc 100644 --- a/clang/lib/Driver/SanitizerArgs.cpp +++ b/clang/lib/Driver/SanitizerArgs.cpp @@ -431,6 +431,8 @@ SanitizerArgs::SanitizerArgs(const ToolChain &TC, options::OPT_fno_sanitize_handler_preserve_all_regs, HandlerPreserveAllRegs) && MinimalRuntime && (Triple.isAArch64() || Triple.isX86_64()); + TrapLoop = Args.hasFlag(options::OPT_fsanitize_trap_loop, + options::OPT_fno_sanitize_trap_loop, false); // The object size sanitizer should not be enabled at -O0. Arg *OptLevel = Args.getLastArg(options::OPT_O_Group); @@ -1494,6 +1496,9 @@ void SanitizerArgs::addArgs(const ToolChain &TC, const llvm::opt::ArgList &Args, if (MinimalRuntime) CmdArgs.push_back("-fsanitize-minimal-runtime"); + if (TrapLoop) + CmdArgs.push_back("-fsanitize-trap-loop"); + if (HandlerPreserveAllRegs) CmdArgs.push_back("-fsanitize-handler-preserve-all-regs"); diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 77a2c73f0d446..0eee7f917d2b8 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -370,6 +370,8 @@ ToolChain::getMultilibFlags(const llvm::opt::ArgList &Args) const { break; case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: getRISCVMultilibFlags(D, Triple, Args, Result); break; default: diff --git a/clang/lib/Driver/ToolChains/AIX.cpp b/clang/lib/Driver/ToolChains/AIX.cpp index a8acf9cfc44c9..6b037bff137d6 100644 --- a/clang/lib/Driver/ToolChains/AIX.cpp +++ b/clang/lib/Driver/ToolChains/AIX.cpp @@ -147,25 +147,10 @@ void aix::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-bforceimprw"); } - // PGO instrumentation generates symbols belonging to special sections, and - // the linker needs to place all symbols in a particular section together in - // memory; the AIX linker does that under an option. - if (Args.hasFlag(options::OPT_fprofile_arcs, options::OPT_fno_profile_arcs, - false) || - Args.hasFlag(options::OPT_fprofile_generate, - options::OPT_fno_profile_generate, false) || - Args.hasFlag(options::OPT_fprofile_generate_EQ, - options::OPT_fno_profile_generate, false) || - Args.hasFlag(options::OPT_fprofile_instr_generate, - options::OPT_fno_profile_instr_generate, false) || - Args.hasFlag(options::OPT_fprofile_instr_generate_EQ, - options::OPT_fno_profile_instr_generate, false) || - Args.hasFlag(options::OPT_fcs_profile_generate, - options::OPT_fno_profile_generate, false) || - Args.hasFlag(options::OPT_fcs_profile_generate_EQ, - options::OPT_fno_profile_generate, false) || - Args.hasArg(options::OPT_fcreate_profile) || - Args.hasArg(options::OPT_coverage)) + // PGO and ifunc support depends on the named sections linker feature that is + // available on AIX 7.2 TL5 SP5 onwards. + if (ToolChain.getTriple().getOSMajorVersion() == 0 || + ToolChain.getTriple().getOSVersion() >= VersionTuple(7, 2)) CmdArgs.push_back("-bdbg:namedsects:ss"); if (Arg *A = Args.getLastArg(options::OPT_mxcoff_build_id_EQ)) { diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp b/clang/lib/Driver/ToolChains/Arch/ARM.cpp index 55eb2dcf7ddf4..7d9c1f0bd3d40 100644 --- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp +++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp @@ -517,7 +517,8 @@ arm::FloatABI arm::getARMFloatABI(const Driver &D, const llvm::Triple &Triple, else ABI = FloatABI::Soft; - if (Triple.getOS() != llvm::Triple::UnknownOS || + if (((Triple.getOS() != llvm::Triple::UnknownOS) && + !Triple.isOSFirmware()) || !Triple.isOSBinFormatMachO()) D.Diag(diag::warn_drv_assuming_mfloat_abi_is) << "soft"; } diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp b/clang/lib/Driver/ToolChains/Arch/X86.cpp index 4fcb744db120d..61d512f9e093f 100644 --- a/clang/lib/Driver/ToolChains/Arch/X86.cpp +++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp @@ -254,30 +254,29 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple, if (IsNegative) Name = Name.substr(3); - if (A->getOption().matches(options::OPT_mapxf) || - A->getOption().matches(options::OPT_mno_apxf) || - A->getOption().matches(options::OPT_mapx_features_EQ) || - A->getOption().matches(options::OPT_mno_apx_features_EQ)) { - if (Name == "apxf") { - if (IsNegative) { - Features.insert(Features.end(), - {"-egpr", "-ndd", "-ccmp", "-nf", "-zu"}); - if (!Triple.isOSWindows()) - Features.insert(Features.end(), {"-push2pop2", "-ppx"}); - } else { - Features.insert(Features.end(), - {"+egpr", "+ndd", "+ccmp", "+nf", "+zu"}); - if (!Triple.isOSWindows()) - Features.insert(Features.end(), {"+push2pop2", "+ppx"}); - - if (Not64Bit) - D.Diag(diag::err_drv_unsupported_opt_for_target) - << StringRef("-mapxf") << Triple.getTriple(); - } - continue; + if (A->getOption().matches(options::OPT_mapxf) || + A->getOption().matches(options::OPT_mno_apxf)) { + if (IsNegative) { + Features.insert(Features.end(), + {"-egpr", "-ndd", "-ccmp", "-nf", "-zu"}); + if (!Triple.isOSWindows()) + Features.insert(Features.end(), {"-push2pop2", "-ppx"}); + } else { + Features.insert(Features.end(), + {"+egpr", "+ndd", "+ccmp", "+nf", "+zu"}); + if (!Triple.isOSWindows()) + Features.insert(Features.end(), {"+push2pop2", "+ppx"}); + + if (Not64Bit) + D.Diag(diag::err_drv_unsupported_opt_for_target) + << StringRef("-mapxf") << Triple.getTriple(); } + continue; + } + if (A->getOption().matches(options::OPT_mapx_features_EQ) || + A->getOption().matches(options::OPT_mno_apx_features_EQ)) { if (Not64Bit && !IsNegative) D.Diag(diag::err_drv_unsupported_opt_for_target) << StringRef("-mapx-features=") << Triple.getTriple(); diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp b/clang/lib/Driver/ToolChains/BareMetal.cpp index 6574651b72a3e..0602a8a19f943 100644 --- a/clang/lib/Driver/ToolChains/BareMetal.cpp +++ b/clang/lib/Driver/ToolChains/BareMetal.cpp @@ -733,7 +733,7 @@ SanitizerMask BareMetal::getSupportedSanitizers() const { const bool IsX86_64 = getTriple().getArch() == llvm::Triple::x86_64; const bool IsAArch64 = getTriple().getArch() == llvm::Triple::aarch64 || getTriple().getArch() == llvm::Triple::aarch64_be; - const bool IsRISCV64 = getTriple().getArch() == llvm::Triple::riscv64; + const bool IsRISCV64 = getTriple().isRISCV64(); SanitizerMask Res = ToolChain::getSupportedSanitizers(); Res |= SanitizerKind::Address; Res |= SanitizerKind::KernelAddress; diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 0293b04217673..87d4d73748940 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -1218,6 +1218,8 @@ static bool isSignedCharDefault(const llvm::Triple &Triple) { case llvm::Triple::ppc64le: case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: case llvm::Triple::systemz: case llvm::Triple::xcore: case llvm::Triple::xtensa: @@ -1564,6 +1566,8 @@ void Clang::RenderTargetOptions(const llvm::Triple &EffectiveTriple, case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: AddRISCVTargetArgs(Args, CmdArgs); break; @@ -4967,13 +4971,6 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back(Args.MakeArgString( Twine("-target-sdk-version=") + CudaVersionToString(CTC->CudaInstallation.version()))); - // Unsized function arguments used for variadics were introduced in - // CUDA-9.0. We still do not support generating code that actually uses - // variadic arguments yet, but we do need to allow parsing them as - // recent CUDA headers rely on that. - // https://github.com/llvm/llvm-project/issues/58410 - if (CTC->CudaInstallation.version() >= CudaVersion::CUDA_90) - CmdArgs.push_back("-fcuda-allow-variadic-functions"); } } CmdArgs.push_back("-aux-triple"); @@ -5666,8 +5663,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, << Name << Triple.getArchName(); } else if (Name == "SLEEF" || Name == "ArmPL") { if (Triple.getArch() != llvm::Triple::aarch64 && - Triple.getArch() != llvm::Triple::aarch64_be && - Triple.getArch() != llvm::Triple::riscv64) + Triple.getArch() != llvm::Triple::aarch64_be && !Triple.isRISCV64()) D.Diag(diag::err_drv_unsupported_opt_for_target) << Name << Triple.getArchName(); } @@ -5681,6 +5677,9 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptOutFlag(CmdArgs, options::OPT_fdelete_null_pointer_checks, options::OPT_fno_delete_null_pointer_checks); + Args.addOptOutFlag(CmdArgs, options::OPT_flifetime_dse, + options::OPT_fno_lifetime_dse); + // LLVM Code Generator Options. if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ_quadword_atomics)) { @@ -6675,6 +6674,11 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, options::OPT_fno_offload_via_llvm, false) && (JA.isDeviceOffloading(Action::OFK_None) || JA.isDeviceOffloading(Action::OFK_OpenMP))) { + + // Determine if target-fast optimizations should be enabled + bool TargetFastUsed = + Args.hasFlag(options::OPT_fopenmp_target_fast, + options::OPT_fno_openmp_target_fast, OFastEnabled); switch (D.getOpenMPRuntime(Args)) { case Driver::OMPRT_OMP: case Driver::OMPRT_IOMP5: @@ -6725,10 +6729,19 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, options::OPT_fno_openmp_assume_threads_oversubscription, /*Default=*/false)) CmdArgs.push_back("-fopenmp-assume-threads-oversubscription"); - if (Args.hasArg(options::OPT_fopenmp_assume_no_thread_state)) + + // Handle -fopenmp-assume-no-thread-state (implied by target-fast) + if (Args.hasFlag(options::OPT_fopenmp_assume_no_thread_state, + options::OPT_fno_openmp_assume_no_thread_state, + /*Default=*/TargetFastUsed)) CmdArgs.push_back("-fopenmp-assume-no-thread-state"); - if (Args.hasArg(options::OPT_fopenmp_assume_no_nested_parallelism)) + + // Handle -fopenmp-assume-no-nested-parallelism (implied by target-fast) + if (Args.hasFlag(options::OPT_fopenmp_assume_no_nested_parallelism, + options::OPT_fno_openmp_assume_no_nested_parallelism, + /*Default=*/TargetFastUsed)) CmdArgs.push_back("-fopenmp-assume-no-nested-parallelism"); + if (Args.hasArg(options::OPT_fopenmp_offload_mandatory)) CmdArgs.push_back("-fopenmp-offload-mandatory"); if (Args.hasArg(options::OPT_fopenmp_force_usm)) @@ -8864,6 +8877,8 @@ void ClangAs::ConstructJob(Compilation &C, const JobAction &JA, case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: AddRISCVTargetArgs(Args, CmdArgs); break; @@ -9210,6 +9225,7 @@ void LinkerWrapper::ConstructJob(Compilation &C, const JobAction &JA, OPT_v, OPT_cuda_path_EQ, OPT_rocm_path_EQ, + OPT_hip_path_EQ, OPT_O_Group, OPT_g_Group, OPT_g_flags_Group, diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 57d19a73c5d2b..aea4bd95fefeb 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -90,6 +90,8 @@ static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args, case llvm::Triple::ppc64le: case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: case llvm::Triple::sparc: case llvm::Triple::sparcel: case llvm::Triple::sparcv9: @@ -608,6 +610,10 @@ const char *tools::getLDMOption(const llvm::Triple &T, const ArgList &Args) { return "elf32lriscv"; case llvm::Triple::riscv64: return "elf64lriscv"; + case llvm::Triple::riscv32be: + return "elf32briscv"; + case llvm::Triple::riscv64be: + return "elf64briscv"; case llvm::Triple::sparc: case llvm::Triple::sparcel: return "elf32_sparc"; @@ -785,6 +791,8 @@ std::string tools::getCPUName(const Driver &D, const ArgList &Args, return "ck810"; case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: return riscv::getRISCVTargetCPU(Args, T); case llvm::Triple::bpfel: @@ -866,6 +874,8 @@ void tools::getTargetFeatures(const Driver &D, const llvm::Triple &Triple, break; case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: riscv::getRISCVTargetFeatures(D, Triple, Args, Features); break; case llvm::Triple::systemz: @@ -1718,6 +1728,8 @@ collectSanitizerRuntimes(const ToolChain &TC, const ArgList &Args, if (SanArgs.linkCXXRuntimes()) StaticRuntimes.push_back("scudo_standalone_cxx"); } + if (SanArgs.needsUbsanLoopDetectRt()) + NonWholeStaticRuntimes.push_back("ubsan_loop_detect"); } // Should be called before we add system libraries (C++ ABI, libstdc++/libc++, diff --git a/clang/lib/Driver/ToolChains/Cuda.cpp b/clang/lib/Driver/ToolChains/Cuda.cpp index 6cc73ff5fc1f6..840df0b0fd5fc 100644 --- a/clang/lib/Driver/ToolChains/Cuda.cpp +++ b/clang/lib/Driver/ToolChains/Cuda.cpp @@ -863,13 +863,6 @@ void CudaToolChain::addClangTargetOptions( "-enable-memcpyopt-without-libcalls", "-fno-threadsafe-statics"}); - // Unsized function arguments used for variadics were introduced in CUDA-9.0 - // We still do not support generating code that actually uses variadic - // arguments yet, but we do need to allow parsing them as recent CUDA - // headers rely on that. https://github.com/llvm/llvm-project/issues/58410 - if (CudaInstallation.version() >= CudaVersion::CUDA_90) - CC1Args.push_back("-fcuda-allow-variadic-functions"); - if (DriverArgs.hasFlag(options::OPT_fcuda_short_ptr, options::OPT_fno_cuda_short_ptr, false)) CC1Args.append({"-mllvm", "--nvptx-short-ptr"}); diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index e7b41830feb7e..073f23950160c 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -78,9 +78,13 @@ void darwin::setTripleTypeForMachOArchName(llvm::Triple &T, StringRef Str, if (Arch != llvm::Triple::UnknownArch) T.setArchName(Str); - if (ArchKind == llvm::ARM::ArchKind::ARMV6M || - ArchKind == llvm::ARM::ArchKind::ARMV7M || - ArchKind == llvm::ARM::ArchKind::ARMV7EM) { + // Standalone/bare metal compiles often unintentionally come out as + // armv6m-apple-ios (-target not specified, or set from Xcode). Change these + // cases to armv6m-apple-unknown-macho to better reflect intent. + if ((T.getOS() != llvm::Triple::Firmware) && + (ArchKind == llvm::ARM::ArchKind::ARMV6M || + ArchKind == llvm::ARM::ArchKind::ARMV7M || + ArchKind == llvm::ARM::ArchKind::ARMV7EM)) { // Don't reject these -version-min= if we have the appropriate triple. if (T.getOS() == llvm::Triple::IOS) for (Arg *A : Args.filtered(options::OPT_mios_version_min_EQ)) @@ -590,8 +594,9 @@ void darwin::Linker::ConstructJob(Compilation &C, const JobAction &JA, const char *Exec = Args.MakeArgString(getToolChain().GetLinkerPath(&LinkerIsLLD)); - // xrOS always uses -platform-version. - bool UsePlatformVersion = getToolChain().getTriple().isXROS(); + // Newer triples always use -platform-version. + llvm::Triple Triple = getToolChain().getTriple(); + bool UsePlatformVersion = Triple.isXROS() || Triple.isOSFirmware(); // I'm not sure why this particular decomposition exists in gcc, but // we follow suite for ease of comparison. @@ -660,6 +665,15 @@ void darwin::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back(Args.MakeArgString("-lto-stats-file=" + StatsFile.str())); } + // Set up stack usage file path. + if (Args.hasArg(options::OPT_fstack_usage)) { + SmallString<128> StackUsageFile(Output.getFilename()); + llvm::sys::path::replace_extension(StackUsageFile, "su"); + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back( + Args.MakeArgString("-stack-usage-file=" + StackUsageFile)); + } + // It seems that the 'e' option is completely ignored for dynamic executables // (the default), and with static executables, the last one wins, as expected. Args.addAllArgs(CmdArgs, {options::OPT_d_Flag, options::OPT_s, options::OPT_t, @@ -1000,6 +1014,8 @@ ObjCRuntime Darwin::getDefaultObjCRuntime(bool isNonFragile) const { bool Darwin::hasBlocksRuntime() const { if (isTargetWatchOSBased() || isTargetDriverKit() || isTargetXROS()) return true; + else if (isTargetFirmware()) + return false; else if (isTargetIOSBased()) return !isIPhoneOSVersionLT(3, 2); else { @@ -1172,6 +1188,8 @@ std::string Darwin::ComputeEffectiveClangTriple(const ArgList &Args, Str += "ios"; else if (isTargetXROS()) Str += llvm::Triple::getOSTypeName(llvm::Triple::XROS); + else if (isTargetFirmware()) + Str += llvm::Triple::getOSTypeName(llvm::Triple::Firmware); else Str += "macosx"; Str += getTripleTargetVersion().getAsString(); @@ -1401,6 +1419,10 @@ std::string MachO::getCompilerRT(const ArgList &Args, StringRef Component, std::string Darwin::getCompilerRT(const ArgList &Args, StringRef Component, FileType Type, bool IsFortran) const { + // Firmware uses the "bare metal" RT. + if (TargetPlatform == DarwinPlatformKind::Firmware) + return MachO::getCompilerRT(Args, Component, Type, IsFortran); + assert(Type != ToolChain::FT_Object && "it doesn't make sense to ask for the compiler-rt library name as an " "object file"); @@ -1450,6 +1472,9 @@ StringRef Darwin::getOSLibraryNameSuffix(bool IgnoreSim) const { : "xrossim"; case DarwinPlatformKind::DriverKit: return "driverkit"; + + case DarwinPlatformKind::Firmware: + break; } llvm_unreachable("Unsupported platform"); } @@ -1550,6 +1575,10 @@ ToolChain::RuntimeLibType DarwinClang::GetRuntimeLibType( void DarwinClang::AddLinkRuntimeLibArgs(const ArgList &Args, ArgStringList &CmdArgs, bool ForceLinkBuiltinRT) const { + // Firmware uses the "bare metal" runtime lib. + if (TargetPlatform == DarwinPlatformKind::Firmware) + return MachO::AddLinkRuntimeLibArgs(Args, CmdArgs, ForceLinkBuiltinRT); + // Call once to ensure diagnostic is printed if wrong value was specified GetRuntimeLibType(Args); @@ -1795,11 +1824,8 @@ struct DarwinPlatform { case DarwinPlatformKind::WatchOS: Opt = options::OPT_mwatchos_version_min_EQ; break; - case DarwinPlatformKind::XROS: - // xrOS always explicitly provides a version in the triple. - return; - case DarwinPlatformKind::DriverKit: - // DriverKit always explicitly provides a version in the triple. + default: + // New platforms always explicitly provide a version in the triple. return; } Arg = Args.MakeJoinedArg(nullptr, Opts.getOption(Opt), OSVersionStr); @@ -1858,7 +1884,7 @@ struct DarwinPlatform { auto TargetVariantVersion = TargetVariantTriple->getOSVersion(); if (TargetVariantVersion.getMajor()) { if (TargetVariantVersion < ZipperedOSVersion) - ZipperedOSVersion = TargetVariantVersion; + ZipperedOSVersion = std::move(TargetVariantVersion); } } break; @@ -1990,6 +2016,8 @@ struct DarwinPlatform { return DarwinPlatformKind::XROS; case llvm::Triple::DriverKit: return DarwinPlatformKind::DriverKit; + case llvm::Triple::Firmware: + return DarwinPlatformKind::Firmware; default: llvm_unreachable("Unable to infer Darwin variant"); } @@ -2009,6 +2037,8 @@ struct DarwinPlatform { return llvm::Triple::DriverKit; case DarwinPlatformKind::XROS: return llvm::Triple::XROS; + case DarwinPlatformKind::Firmware: + return llvm::Triple::Firmware; } llvm_unreachable("Unknown DarwinPlatformKind enum"); } @@ -2172,7 +2202,6 @@ getDeploymentTargetFromOSVersionArg(DerivedArgList &Args, std::optional getDeploymentTargetFromEnvironmentVariables(const Driver &TheDriver, const llvm::Triple &Triple) { - std::string Targets[Darwin::LastDarwinPlatform + 1]; const char *EnvVars[] = { "MACOSX_DEPLOYMENT_TARGET", "IPHONEOS_DEPLOYMENT_TARGET", @@ -2181,8 +2210,7 @@ getDeploymentTargetFromEnvironmentVariables(const Driver &TheDriver, "DRIVERKIT_DEPLOYMENT_TARGET", "XROS_DEPLOYMENT_TARGET" }; - static_assert(std::size(EnvVars) == Darwin::LastDarwinPlatform + 1, - "Missing platform"); + std::string Targets[std::size(EnvVars)]; for (const auto &I : llvm::enumerate(llvm::ArrayRef(EnvVars))) { if (char *Env = ::getenv(I.value())) Targets[I.index()] = Env; @@ -2301,16 +2329,13 @@ VersionTuple getInferredOSVersion(llvm::Triple::OSType OS, case llvm::Triple::WatchOS: OsVersion = Triple.getWatchOSVersion(); break; - case llvm::Triple::XROS: - OsVersion = Triple.getOSVersion(); - if (!OsVersion.getMajor()) - OsVersion = OsVersion.withMajorReplaced(1); - break; case llvm::Triple::DriverKit: OsVersion = Triple.getDriverKitVersion(); break; default: - llvm_unreachable("Unexpected OS type"); + OsVersion = Triple.getOSVersion(); + if (!OsVersion.getMajor()) + OsVersion = OsVersion.withMajorReplaced(1); break; } return OsVersion; @@ -2644,15 +2669,14 @@ void Darwin::AddDeploymentTarget(DerivedArgList &Args) const { Micro >= 100) getDriver().Diag(diag::err_drv_invalid_version_number) << PlatformAndVersion->getAsString(Args, Opts); - } else if (Platform == XROS) { + } else { if (!Driver::GetReleaseVersion(OSVersionStr, Major, Minor, Micro, HadExtra) || HadExtra || Major < 1 || Major >= MajorVersionLimit || Minor >= 100 || Micro >= 100) getDriver().Diag(diag::err_drv_invalid_version_number) << PlatformAndVersion->getAsString(Args, Opts); - } else - llvm_unreachable("unknown kind of Darwin platform"); + } DarwinEnvironmentKind Environment = PlatformAndVersion->getEnvironment(); // Recognize iOS targets with an x86 architecture as the iOS simulator. @@ -3181,9 +3205,7 @@ bool Darwin::isAlignedAllocationUnavailable() const { case WatchOS: // Earlier than 4.0. OS = llvm::Triple::WatchOS; break; - case XROS: // Always available. - return false; - case DriverKit: // Always available. + default: // Always available on newer platforms. return false; } @@ -3266,9 +3288,8 @@ bool Darwin::isSizedDeallocationUnavailable() const { case WatchOS: // Earlier than 3.0. OS = llvm::Triple::WatchOS; break; - case DriverKit: - case XROS: - // Always available. + default: + // Always available on newer platforms. return false; } @@ -3649,12 +3670,18 @@ static const char *getPlatformName(Darwin::DarwinPlatformKind Platform, return "xros"; case Darwin::DriverKit: return "driverkit"; + default: + break; } llvm_unreachable("invalid platform"); } void Darwin::addPlatformVersionArgs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const { + // Firmware doesn't use -platform_version. + if (TargetPlatform == DarwinPlatformKind::Firmware) + return MachO::addPlatformVersionArgs(Args, CmdArgs); + auto EmitPlatformVersionArg = [&](const VersionTuple &TV, Darwin::DarwinPlatformKind TargetPlatform, Darwin::DarwinEnvironmentKind TargetEnvironment, @@ -3821,6 +3848,10 @@ static void addDefaultCRTLinkArgs(const Darwin &D, const ArgList &Args, void Darwin::addStartObjectFileArgs(const ArgList &Args, ArgStringList &CmdArgs) const { + // Firmware uses the "bare metal" start object file args. + if (isTargetFirmware()) + return MachO::addStartObjectFileArgs(Args, CmdArgs); + // Derived from startfile spec. if (Args.hasArg(options::OPT_dynamiclib)) addDynamicLibLinkArgs(*this, Args, CmdArgs); diff --git a/clang/lib/Driver/ToolChains/Darwin.h b/clang/lib/Driver/ToolChains/Darwin.h index 05762596fefba..14a80c973485a 100644 --- a/clang/lib/Driver/ToolChains/Darwin.h +++ b/clang/lib/Driver/ToolChains/Darwin.h @@ -363,7 +363,7 @@ class LLVM_LIBRARY_VISIBILITY Darwin : public AppleMachO { WatchOS, DriverKit, XROS, - LastDarwinPlatform = XROS + Firmware, }; enum DarwinEnvironmentKind { NativeEnvironment, @@ -520,6 +520,8 @@ class LLVM_LIBRARY_VISIBILITY Darwin : public AppleMachO { return TargetPlatform == DriverKit; } + bool isTargetFirmware() const { return TargetPlatform == Firmware; } + bool isTargetMacCatalyst() const { return TargetPlatform == IPhoneOS && TargetEnvironment == MacCatalyst; } diff --git a/clang/lib/Driver/ToolChains/FreeBSD.cpp b/clang/lib/Driver/ToolChains/FreeBSD.cpp index 70e66a2f5c3e7..cf6ad385d949a 100644 --- a/clang/lib/Driver/ToolChains/FreeBSD.cpp +++ b/clang/lib/Driver/ToolChains/FreeBSD.cpp @@ -212,6 +212,14 @@ void freebsd::Linker::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-m"); CmdArgs.push_back("elf64lriscv"); break; + case llvm::Triple::riscv32be: + CmdArgs.push_back("-m"); + CmdArgs.push_back("elf32briscv"); + break; + case llvm::Triple::riscv64be: + CmdArgs.push_back("-m"); + CmdArgs.push_back("elf64briscv"); + break; case llvm::Triple::loongarch64: CmdArgs.push_back("-m"); CmdArgs.push_back("elf64loongarch"); diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index ac31a45b557f1..f99eb9b3bae03 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -672,7 +672,9 @@ void tools::gnutools::Assembler::ConstructJob(Compilation &C, break; } case llvm::Triple::riscv32: - case llvm::Triple::riscv64: { + case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: { StringRef ABIName = riscv::getRISCVABI(Args, getToolChain().getTriple()); CmdArgs.push_back("-mabi"); CmdArgs.push_back(ABIName.data()); @@ -1088,7 +1090,7 @@ static bool findMipsMuslMultilibs(const Driver &D, }); } if (MuslMipsMultilibs.select(D, Flags, Result.SelectedMultilibs)) { - Result.Multilibs = MuslMipsMultilibs; + Result.Multilibs = std::move(MuslMipsMultilibs); return true; } return false; @@ -1499,7 +1501,7 @@ static void findAndroidArmMultilibs(const Driver &D, addMultilibFlag(IsThumbMode, "-mthumb", Flags); if (AndroidArmMultilibs.select(D, Flags, Result.SelectedMultilibs)) - Result.Multilibs = AndroidArmMultilibs; + Result.Multilibs = std::move(AndroidArmMultilibs); } static bool findMSP430Multilibs(const Driver &D, @@ -1592,7 +1594,7 @@ static void findCSKYMultilibs(const Driver &D, const llvm::Triple &TargetTriple, .FilterOut(NonExistent); if (CSKYMultilibs.select(D, Flags, Result.SelectedMultilibs)) - Result.Multilibs = CSKYMultilibs; + Result.Multilibs = std::move(CSKYMultilibs); } /// Extend the multi-lib re-use selection mechanism for RISC-V. @@ -1737,16 +1739,20 @@ static void findRISCVBareMetalMultilibs(const Driver &D, .flag(Twine("-march=", Element.march).str()) .flag(Twine("-mabi=", Element.mabi).str())); } + + StringRef EndiannessSuffix = TargetTriple.isLittleEndian() ? "" : "be"; MultilibSet RISCVMultilibs = MultilibSetBuilder() .Either(Ms) .makeMultilibSet() .FilterOut(NonExistent) - .setFilePathsCallback([](const Multilib &M) { + .setFilePathsCallback([EndiannessSuffix](const Multilib &M) { return std::vector( {M.gccSuffix(), - "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix(), - "/../../../../riscv32-unknown-elf/lib" + M.gccSuffix()}); + "/../../../../riscv64" + EndiannessSuffix.str() + + "-unknown-elf/lib" + M.gccSuffix(), + "/../../../../riscv32" + EndiannessSuffix.str() + + "-unknown-elf/lib" + M.gccSuffix()}); }); Multilib::flags_list Flags; @@ -1765,7 +1771,7 @@ static void findRISCVBareMetalMultilibs(const Driver &D, if (selectRISCVMultilib(D, RISCVMultilibs, MArch, Flags, Result.SelectedMultilibs)) - Result.Multilibs = RISCVMultilibs; + Result.Multilibs = std::move(RISCVMultilibs); } static void findRISCVMultilibs(const Driver &D, @@ -1794,7 +1800,7 @@ static void findRISCVMultilibs(const Driver &D, .FilterOut(NonExistent); Multilib::flags_list Flags; - bool IsRV64 = TargetTriple.getArch() == llvm::Triple::riscv64; + bool IsRV64 = TargetTriple.isRISCV64(); StringRef ABIName = tools::riscv::getRISCVABI(Args, TargetTriple); addMultilibFlag(!IsRV64, "-m32", Flags); @@ -1807,7 +1813,7 @@ static void findRISCVMultilibs(const Driver &D, addMultilibFlag(ABIName == "lp64d", "-mabi=lp64d", Flags); if (RISCVMultilibs.select(D, Flags, Result.SelectedMultilibs)) - Result.Multilibs = RISCVMultilibs; + Result.Multilibs = std::move(RISCVMultilibs); } static bool findBiarchMultilibs(const Driver &D, @@ -2441,6 +2447,15 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu", "riscv64-unknown-elf"}; + static const char *const RISCV32beLibDirs[] = {"/lib32", "/lib"}; + static const char *const RISCV32beTriples[] = {"riscv32be-unknown-linux-gnu", + "riscv32be-linux-gnu", + "riscv32be-unknown-elf"}; + static const char *const RISCV64beLibDirs[] = {"/lib64", "/lib"}; + static const char *const RISCV64beTriples[] = {"riscv64be-unknown-linux-gnu", + "riscv64be-linux-gnu", + "riscv64be-unknown-elf"}; + static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"}; static const char *const SPARCv8Triples[] = {"sparc-linux-gnu", "sparcv8-linux-gnu"}; @@ -2736,6 +2751,18 @@ void Generic_GCC::GCCInstallationDetector::AddDefaultGCCPrefixes( BiarchLibDirs.append(begin(RISCV32LibDirs), end(RISCV32LibDirs)); BiarchTripleAliases.append(begin(RISCV32Triples), end(RISCV32Triples)); break; + case llvm::Triple::riscv32be: + LibDirs.append(begin(RISCV32beLibDirs), end(RISCV32beLibDirs)); + TripleAliases.append(begin(RISCV32beTriples), end(RISCV32beTriples)); + BiarchLibDirs.append(begin(RISCV64beLibDirs), end(RISCV64beLibDirs)); + BiarchTripleAliases.append(begin(RISCV64beTriples), end(RISCV64beTriples)); + break; + case llvm::Triple::riscv64be: + LibDirs.append(begin(RISCV64beLibDirs), end(RISCV64beLibDirs)); + TripleAliases.append(begin(RISCV64beTriples), end(RISCV64beTriples)); + BiarchLibDirs.append(begin(RISCV32beLibDirs), end(RISCV32beLibDirs)); + BiarchTripleAliases.append(begin(RISCV32beTriples), end(RISCV32beTriples)); + break; case llvm::Triple::sparc: case llvm::Triple::sparcel: LibDirs.append(begin(SPARCv8LibDirs), end(SPARCv8LibDirs)); @@ -3051,6 +3078,8 @@ Generic_GCC::getDefaultUnwindTableLevel(const ArgList &Args) const { case llvm::Triple::ppc64le: case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: case llvm::Triple::x86: case llvm::Triple::x86_64: return UnwindTableLevel::Asynchronous; diff --git a/clang/lib/Driver/ToolChains/HIPAMD.cpp b/clang/lib/Driver/ToolChains/HIPAMD.cpp index 617809285c165..61ae7b81d5025 100644 --- a/clang/lib/Driver/ToolChains/HIPAMD.cpp +++ b/clang/lib/Driver/ToolChains/HIPAMD.cpp @@ -259,8 +259,6 @@ void HIPAMDToolChain::addClangTargetOptions( CC1Args.push_back(DriverArgs.MakeArgStringRef(ArgStr)); } - CC1Args.push_back("-fcuda-allow-variadic-functions"); - // Default to "hidden" visibility, as object level linking will not be // supported for the foreseeable future. if (!DriverArgs.hasArg(options::OPT_fvisibility_EQ, diff --git a/clang/lib/Driver/ToolChains/HIPSPV.cpp b/clang/lib/Driver/ToolChains/HIPSPV.cpp index f797573a5725d..8bdb7ab042b2b 100644 --- a/clang/lib/Driver/ToolChains/HIPSPV.cpp +++ b/clang/lib/Driver/ToolChains/HIPSPV.cpp @@ -90,9 +90,27 @@ void HIPSPV::Linker::constructLinkAndEmitSpirvCommand( } // Emit SPIR-V binary. + llvm::opt::ArgStringList TrArgs; + auto T = getToolChain().getTriple(); + bool HasNoSubArch = T.getSubArch() == llvm::Triple::NoSubArch; + if (T.getOS() == llvm::Triple::ChipStar) { + // chipStar needs 1.2 for supporting warp-level primitivies via sub-group + // extensions. Strictly put we'd need 1.3 for the standard non-extension + // shuffle operations, but it's not supported by any backend driver of the + // chipStar. + if (HasNoSubArch) + TrArgs.push_back("--spirv-max-version=1.2"); + TrArgs.push_back("--spirv-ext=-all" + // Needed for experimental indirect call support. + ",+SPV_INTEL_function_pointers" + // Needed for shuffles below SPIR-V 1.3 + ",+SPV_INTEL_subgroups"); + } else { + if (HasNoSubArch) + TrArgs.push_back("--spirv-max-version=1.1"); + TrArgs.push_back("--spirv-ext=+all"); + } - llvm::opt::ArgStringList TrArgs{"--spirv-max-version=1.1", - "--spirv-ext=+all"}; InputInfo TrInput = InputInfo(types::TY_LLVM_BC, TempFile, ""); SPIRV::constructTranslateCommand(C, *this, JA, Output, TrInput, TrArgs); } @@ -116,7 +134,16 @@ void HIPSPV::Linker::ConstructJob(Compilation &C, const JobAction &JA, HIPSPVToolChain::HIPSPVToolChain(const Driver &D, const llvm::Triple &Triple, const ToolChain &HostTC, const ArgList &Args) - : ToolChain(D, Triple, Args), HostTC(HostTC) { + : ToolChain(D, Triple, Args), HostTC(&HostTC) { + // Lookup binaries into the driver directory, this is used to + // discover the clang-offload-bundler executable. + getProgramPaths().push_back(getDriver().Dir); +} + +// Non-offloading toolchain. Primaly used by clang-offload-linker. +HIPSPVToolChain::HIPSPVToolChain(const Driver &D, const llvm::Triple &Triple, + const ArgList &Args) + : ToolChain(D, Triple, Args), HostTC(nullptr) { // Lookup binaries into the driver directory, this is used to // discover the clang-offload-bundler executable. getProgramPaths().push_back(getDriver().Dir); @@ -125,13 +152,20 @@ HIPSPVToolChain::HIPSPVToolChain(const Driver &D, const llvm::Triple &Triple, void HIPSPVToolChain::addClangTargetOptions( const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, Action::OffloadKind DeviceOffloadingKind) const { - HostTC.addClangTargetOptions(DriverArgs, CC1Args, DeviceOffloadingKind); + + if (!HostTC) { + assert(DeviceOffloadingKind == Action::OFK_None && + "Need host toolchain for offloading!"); + return; + } + + HostTC->addClangTargetOptions(DriverArgs, CC1Args, DeviceOffloadingKind); assert(DeviceOffloadingKind == Action::OFK_HIP && "Only HIP offloading kinds are supported for GPUs."); CC1Args.append( - {"-fcuda-is-device", "-fcuda-allow-variadic-functions", + {"-fcuda-is-device", // A crude workaround for llvm-spirv which does not handle the // autovectorized code well (vector reductions, non-i{8,16,32,64} types). // TODO: Allow autovectorization when SPIR-V backend arrives. @@ -156,27 +190,37 @@ Tool *HIPSPVToolChain::buildLinker() const { } void HIPSPVToolChain::addClangWarningOptions(ArgStringList &CC1Args) const { - HostTC.addClangWarningOptions(CC1Args); + if (HostTC) + HostTC->addClangWarningOptions(CC1Args); + ToolChain::addClangWarningOptions(CC1Args); } ToolChain::CXXStdlibType HIPSPVToolChain::GetCXXStdlibType(const ArgList &Args) const { - return HostTC.GetCXXStdlibType(Args); + if (HostTC) + return HostTC->GetCXXStdlibType(Args); + return ToolChain::GetCXXStdlibType(Args); } void HIPSPVToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs, ArgStringList &CC1Args) const { - HostTC.AddClangSystemIncludeArgs(DriverArgs, CC1Args); + if (HostTC) + HostTC->AddClangSystemIncludeArgs(DriverArgs, CC1Args); + ToolChain::AddClangSystemIncludeArgs(DriverArgs, CC1Args); } void HIPSPVToolChain::AddClangCXXStdlibIncludeArgs( const ArgList &Args, ArgStringList &CC1Args) const { - HostTC.AddClangCXXStdlibIncludeArgs(Args, CC1Args); + if (HostTC) + HostTC->AddClangCXXStdlibIncludeArgs(Args, CC1Args); + ToolChain::AddClangCXXStdlibIncludeArgs(Args, CC1Args); } void HIPSPVToolChain::AddIAMCUIncludeArgs(const ArgList &Args, ArgStringList &CC1Args) const { - HostTC.AddIAMCUIncludeArgs(Args, CC1Args); + if (HostTC) + HostTC->AddIAMCUIncludeArgs(Args, CC1Args); + ToolChain::AddIAMCUIncludeArgs(Args, CC1Args); } void HIPSPVToolChain::AddHIPIncludeArgs(const ArgList &DriverArgs, @@ -270,12 +314,16 @@ SanitizerMask HIPSPVToolChain::getSupportedSanitizers() const { // This behavior is necessary because the host and device toolchains // invocations often share the command line, so the device toolchain must // tolerate flags meant only for the host toolchain. - return HostTC.getSupportedSanitizers(); + if (HostTC) + return HostTC->getSupportedSanitizers(); + return ToolChain::getSupportedSanitizers(); } VersionTuple HIPSPVToolChain::computeMSVCVersion(const Driver *D, const ArgList &Args) const { - return HostTC.computeMSVCVersion(D, Args); + if (HostTC) + return HostTC->computeMSVCVersion(D, Args); + return ToolChain::computeMSVCVersion(D, Args); } void HIPSPVToolChain::adjustDebugInfoKind( diff --git a/clang/lib/Driver/ToolChains/HIPSPV.h b/clang/lib/Driver/ToolChains/HIPSPV.h index caf6924151446..068040ee4f491 100644 --- a/clang/lib/Driver/ToolChains/HIPSPV.h +++ b/clang/lib/Driver/ToolChains/HIPSPV.h @@ -47,9 +47,12 @@ class LLVM_LIBRARY_VISIBILITY HIPSPVToolChain final : public ToolChain { public: HIPSPVToolChain(const Driver &D, const llvm::Triple &Triple, const ToolChain &HostTC, const llvm::opt::ArgList &Args); + HIPSPVToolChain(const Driver &D, const llvm::Triple &Triple, + const llvm::opt::ArgList &Args); const llvm::Triple *getAuxTriple() const override { - return &HostTC.getTriple(); + assert(HostTC); + return &HostTC->getTriple(); } void @@ -90,7 +93,7 @@ class LLVM_LIBRARY_VISIBILITY HIPSPVToolChain final : public ToolChain { bool isPICDefaultForced() const override { return false; } bool SupportsProfiling() const override { return false; } - const ToolChain &HostTC; + const ToolChain *HostTC = nullptr; protected: Tool *buildLinker() const override; diff --git a/clang/lib/Driver/ToolChains/Linux.cpp b/clang/lib/Driver/ToolChains/Linux.cpp index f5ff70a595b01..fb3f531e77ace 100644 --- a/clang/lib/Driver/ToolChains/Linux.cpp +++ b/clang/lib/Driver/ToolChains/Linux.cpp @@ -203,7 +203,7 @@ static StringRef getOSLibDir(const llvm::Triple &Triple, const ArgList &Args) { if (Triple.getArch() == llvm::Triple::x86_64 && Triple.isX32()) return "libx32"; - if (Triple.getArch() == llvm::Triple::riscv32) + if (Triple.isRISCV32()) return "lib32"; if (Triple.getArch() == llvm::Triple::loongarch32) { @@ -692,7 +692,9 @@ std::string Linux::getDynamicLinker(const ArgList &Args) const { (tools::ppc::hasPPCAbiArg(Args, "elfv1")) ? "ld64.so.1" : "ld64.so.2"; break; case llvm::Triple::riscv32: - case llvm::Triple::riscv64: { + case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: { StringRef ArchName = llvm::Triple::getArchTypeName(Arch); StringRef ABIName = tools::riscv::getRISCVABI(Args, Triple); LibDir = "lib"; @@ -934,7 +936,7 @@ SanitizerMask Linux::getSupportedSanitizers() const { getTriple().getArch() == llvm::Triple::armeb || getTriple().getArch() == llvm::Triple::thumbeb; const bool IsLoongArch64 = getTriple().getArch() == llvm::Triple::loongarch64; - const bool IsRISCV64 = getTriple().getArch() == llvm::Triple::riscv64; + const bool IsRISCV64 = getTriple().isRISCV64(); const bool IsSystemZ = getTriple().getArch() == llvm::Triple::systemz; const bool IsHexagon = getTriple().getArch() == llvm::Triple::hexagon; const bool IsAndroid = getTriple().isAndroid(); diff --git a/clang/lib/Driver/ToolChains/OHOS.cpp b/clang/lib/Driver/ToolChains/OHOS.cpp index 607eb714f85dc..2a83ef9db59cc 100644 --- a/clang/lib/Driver/ToolChains/OHOS.cpp +++ b/clang/lib/Driver/ToolChains/OHOS.cpp @@ -50,7 +50,7 @@ static bool findOHOSMuslMultilibs(const Driver &D, {"-mcpu=cortex-a7", "-mfloat-abi=hard", "-mfpu=neon-vfpv4"})); if (Multilibs.select(D, Flags, Result.SelectedMultilibs)) { - Result.Multilibs = Multilibs; + Result.Multilibs = std::move(Multilibs); return true; } return false; diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp index ae17e5467c712..39f812ed1b403 100644 --- a/clang/lib/Frontend/CompilerInstance.cpp +++ b/clang/lib/Frontend/CompilerInstance.cpp @@ -1167,12 +1167,16 @@ std::unique_ptr CompilerInstance::cloneForModuleCompileImpl( Invocation->computeContextHash() && "Module hash mismatch!"); - // Construct a compiler instance that will be used to actually create the - // module. Since we're sharing an in-memory module cache, - // CompilerInstance::CompilerInstance is responsible for finalizing the - // buffers to prevent use-after-frees. + std::shared_ptr ModCache; + if (ThreadSafeConfig) { + ModCache = ThreadSafeConfig->getModuleCache(); + } else { + ModCache = this->ModCache; + } + + // Construct a compiler instance that will be used to create the module. auto InstancePtr = std::make_unique( - std::move(Invocation), getPCHContainerOperations(), ModCache); + std::move(Invocation), getPCHContainerOperations(), std::move(ModCache)); auto &Instance = *InstancePtr; auto &Inv = Instance.getInvocation(); @@ -1984,6 +1988,23 @@ CompilerInstance::loadModule(SourceLocation ImportLoc, // * `Preprocessor::HandleHeaderIncludeOrImport` will never call this // function as the `#include` or `#import` is textual. + MM.cacheModuleLoad(*Path[0].getIdentifierInfo(), Module); + } else if (getPreprocessorOpts().SingleModuleParseMode) { + // This mimics how findOrCompileModuleAndReadAST() finds the module. + Module = getPreprocessor().getHeaderSearchInfo().lookupModule( + ModuleName, ImportLoc, true, !IsInclusionDirective); + if (Module) { + // Mark the module and its submodules as if they were loaded from a PCM. + // This prevents emission of the "missing submodule" diagnostic below. + std::vector Worklist{Module}; + while (!Worklist.empty()) { + auto *M = Worklist.back(); + Worklist.pop_back(); + M->IsFromModuleFile = true; + for (auto *SubM : M->submodules()) + Worklist.push_back(SubM); + } + } MM.cacheModuleLoad(*Path[0].getIdentifierInfo(), Module); } else { SourceLocation ModuleNameEndLoc = Path.back().getLoc().getLocWithOffset( diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 2af4a7f536623..6aa2afb6f5918 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -622,6 +622,11 @@ static bool FixupInvocation(CompilerInvocation &Invocation, LangOpts.RawStringLiterals = true; } + if (Args.hasArg(OPT_freflection) && !LangOpts.CPlusPlus26) { + Diags.Report(diag::err_drv_reflection_requires_cxx26) + << Args.getLastArg(options::OPT_freflection)->getAsString(Args); + } + LangOpts.NamedLoops = Args.hasFlag(OPT_fnamed_loops, OPT_fno_named_loops, LangOpts.C2y); diff --git a/clang/lib/Frontend/FrontendAction.cpp b/clang/lib/Frontend/FrontendAction.cpp index 7810f0999f7d6..79e862f01be14 100644 --- a/clang/lib/Frontend/FrontendAction.cpp +++ b/clang/lib/Frontend/FrontendAction.cpp @@ -1018,19 +1018,28 @@ bool FrontendAction::BeginSourceFile(CompilerInstance &CI, return true; } - // If the implicit PCH include is actually a directory, rather than - // a single file, search for a suitable PCH file in that directory. if (!CI.getPreprocessorOpts().ImplicitPCHInclude.empty()) { FileManager &FileMgr = CI.getFileManager(); PreprocessorOptions &PPOpts = CI.getPreprocessorOpts(); + + // Canonicalize ImplicitPCHInclude. This way, all the downstream code, + // including the ASTWriter, will receive the absolute path to the included + // PCH. + SmallString<128> PCHIncludePath(PPOpts.ImplicitPCHInclude); + FileMgr.makeAbsolutePath(PCHIncludePath); + llvm::sys::path::remove_dots(PCHIncludePath, true); + PPOpts.ImplicitPCHInclude = PCHIncludePath.str(); StringRef PCHInclude = PPOpts.ImplicitPCHInclude; - std::string SpecificModuleCachePath = CI.getSpecificModuleCachePath(); + + // If the implicit PCH include is actually a directory, rather than + // a single file, search for a suitable PCH file in that directory. if (auto PCHDir = FileMgr.getOptionalDirectoryRef(PCHInclude)) { std::error_code EC; SmallString<128> DirNative; llvm::sys::path::native(PCHDir->getName(), DirNative); bool Found = false; llvm::vfs::FileSystem &FS = FileMgr.getVirtualFileSystem(); + std::string SpecificModuleCachePath = CI.getSpecificModuleCachePath(); for (llvm::vfs::directory_iterator Dir = FS.dir_begin(DirNative, EC), DirEnd; Dir != DirEnd && !EC; Dir.increment(EC)) { diff --git a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h index eb51244467bec..aaad8f94e23af 100644 --- a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h +++ b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h @@ -2908,6 +2908,105 @@ __attribute__((convergent)) double3 WaveActiveSum(double3); _HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_sum) __attribute__((convergent)) double4 WaveActiveSum(double4); +//===----------------------------------------------------------------------===// +// WavePrefixSum builtins +//===----------------------------------------------------------------------===// + +_HLSL_16BIT_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) half WavePrefixSum(half); +_HLSL_16BIT_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) half2 WavePrefixSum(half2); +_HLSL_16BIT_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) half3 WavePrefixSum(half3); +_HLSL_16BIT_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) half4 WavePrefixSum(half4); + +#ifdef __HLSL_ENABLE_16_BIT +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int16_t WavePrefixSum(int16_t); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int16_t2 WavePrefixSum(int16_t2); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int16_t3 WavePrefixSum(int16_t3); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int16_t4 WavePrefixSum(int16_t4); + +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint16_t WavePrefixSum(uint16_t); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint16_t2 WavePrefixSum(uint16_t2); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint16_t3 WavePrefixSum(uint16_t3); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint16_t4 WavePrefixSum(uint16_t4); +#endif + +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int WavePrefixSum(int); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int2 WavePrefixSum(int2); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int3 WavePrefixSum(int3); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int4 WavePrefixSum(int4); + +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint WavePrefixSum(uint); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint2 WavePrefixSum(uint2); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint3 WavePrefixSum(uint3); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint4 WavePrefixSum(uint4); + +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int64_t WavePrefixSum(int64_t); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int64_t2 WavePrefixSum(int64_t2); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int64_t3 WavePrefixSum(int64_t3); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) int64_t4 WavePrefixSum(int64_t4); + +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint64_t WavePrefixSum(uint64_t); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint64_t2 WavePrefixSum(uint64_t2); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint64_t3 WavePrefixSum(uint64_t3); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) uint64_t4 WavePrefixSum(uint64_t4); + +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) float WavePrefixSum(float); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) float2 WavePrefixSum(float2); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) float3 WavePrefixSum(float3); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) float4 WavePrefixSum(float4); + +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) double WavePrefixSum(double); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) double2 WavePrefixSum(double2); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) double3 WavePrefixSum(double3); +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_prefix_sum) +__attribute__((convergent)) double4 WavePrefixSum(double4); + //===----------------------------------------------------------------------===// // sign builtins //===----------------------------------------------------------------------===// diff --git a/clang/lib/Headers/ptrauth.h b/clang/lib/Headers/ptrauth.h index ad28f06f0930c..4650fb4722a8c 100644 --- a/clang/lib/Headers/ptrauth.h +++ b/clang/lib/Headers/ptrauth.h @@ -178,6 +178,31 @@ typedef __UINTPTR_TYPE__ ptrauth_generic_signature_t; __builtin_ptrauth_auth_and_resign(__value, __old_key, __old_data, __new_key, \ __new_data) +/* Authenticate a pointer using one scheme, load 32bit value at offset addend + from the pointer, and add this value to the pointer, sign using specified + scheme. + + If the result is subsequently authenticated using the new scheme, that + authentication is guaranteed to fail if and only if the initial + authentication failed. + + The value must be an expression of pointer type. + The key must be a constant expression of type ptrauth_key. + The extra data must be an expression of pointer or integer type; + if an integer, it will be coerced to ptrauth_extra_data_t. + The addend must be an immediate ptrdiff_t value. + The result will have the same type as the original value. + + This operation is guaranteed to not leave the intermediate value + available for attack before it is re-signed. + + Do not pass a null pointer to this function. A null pointer + will not successfully authenticate. */ +#define ptrauth_auth_load_relative_and_sign(__value, __old_key, __old_data, \ + __new_key, __new_data, __offset) \ + __builtin_ptrauth_auth_load_relative_and_sign( \ + __value, __old_key, __old_data, __new_key, __new_data, __offset) + /* Authenticate a pointer using one scheme and resign it as a C function pointer. @@ -363,6 +388,17 @@ typedef __UINTPTR_TYPE__ ptrauth_generic_signature_t; __value; \ }) +#define ptrauth_auth_load_relative_and_sign(__value, __old_key, __old_data, \ + __new_key, __new_data, __offset) \ + ({ \ + (void)__old_key; \ + (void)__old_data; \ + (void)__new_key; \ + (void)__new_data; \ + const char *__value_tmp = (const char *)(__value); \ + (void *)(__value_tmp + *(const int *)(__value_tmp + (__offset))); \ + }) + #define ptrauth_auth_function(__value, __old_key, __old_data) \ ({ \ (void)__old_key; \ diff --git a/clang/lib/Lex/Lexer.cpp b/clang/lib/Lex/Lexer.cpp index 5e9d2743ba53f..1498657047bd6 100644 --- a/clang/lib/Lex/Lexer.cpp +++ b/clang/lib/Lex/Lexer.cpp @@ -4374,6 +4374,9 @@ bool Lexer::LexTokenInternal(Token &Result, bool TokAtPhysicalStartOfLine) { if (Char == '=') { CurPtr = ConsumeChar(CurPtr, SizeTmp, Result); Kind = tok::caretequal; + } else if (LangOpts.Reflection && Char == '^') { + CurPtr = ConsumeChar(CurPtr, SizeTmp, Result); + Kind = tok::caretcaret; } else { if (LangOpts.OpenCL && Char == '^') Diag(CurPtr, diag::err_opencl_logical_exclusive_or); diff --git a/clang/lib/Lex/PPDirectives.cpp b/clang/lib/Lex/PPDirectives.cpp index 8d4c9c49f756a..85edbabf09ed3 100644 --- a/clang/lib/Lex/PPDirectives.cpp +++ b/clang/lib/Lex/PPDirectives.cpp @@ -2494,15 +2494,10 @@ Preprocessor::ImportAction Preprocessor::HandleHeaderIncludeOrImport( (getLangOpts().CPlusPlusModules || getLangOpts().Modules) && ModuleToImport && !ModuleToImport->isHeaderUnit(); - if (MaybeTranslateInclude && (UsableHeaderUnit || UsableClangHeaderModule) && - PPOpts.SingleModuleParseMode) { - Action = IncludeLimitReached; - } // Determine whether we should try to import the module for this #include, if // there is one. Don't do so if precompiled module support is disabled or we // are processing this module textually (because we're building the module). - else if (MaybeTranslateInclude && - (UsableHeaderUnit || UsableClangHeaderModule)) { + if (MaybeTranslateInclude && (UsableHeaderUnit || UsableClangHeaderModule)) { // If this include corresponds to a module but that module is // unavailable, diagnose the situation and bail out. // FIXME: Remove this; loadModule does the same check (but produces diff --git a/clang/lib/Parse/CMakeLists.txt b/clang/lib/Parse/CMakeLists.txt index e6cbf3b868b7d..8dd120f529b13 100644 --- a/clang/lib/Parse/CMakeLists.txt +++ b/clang/lib/Parse/CMakeLists.txt @@ -26,6 +26,7 @@ add_clang_library(clangParse ParseTentative.cpp Parser.cpp ParseOpenACC.cpp + ParseReflect.cpp LINK_LIBS clangAST diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp index fd53e6573051c..9117a725843d9 100644 --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -1405,7 +1405,7 @@ TypeResult Parser::ParseBaseTypeSpecifier(SourceLocation &BaseLoc, DeclSpec DS(AttrFactory); DS.SetRangeStart(IdLoc); DS.SetRangeEnd(EndLocation); - DS.getTypeSpecScope() = SS; + DS.getTypeSpecScope() = std::move(SS); const char *PrevSpec = nullptr; unsigned DiagID; diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp index 3515343202de1..be6c7824cdbae 100644 --- a/clang/lib/Parse/ParseExpr.cpp +++ b/clang/lib/Parse/ParseExpr.cpp @@ -333,6 +333,27 @@ Parser::ParseRHSOfBinaryExpression(ExprResult LHS, prec::Level MinPrec) { Token OpToken = Tok; ConsumeToken(); + // The reflection operator is not valid here (i.e., in the place of the + // operator token in a binary expression), so if reflection and blocks are + // enabled, we split caretcaret into two carets: the first being the binary + // operator and the second being the introducer for the block. + if (OpToken.is(tok::caretcaret)) { + assert(getLangOpts().Reflection); + if (getLangOpts().Blocks) { + OpToken.setKind(tok::caret); + Token Caret; + { + Caret.startToken(); + Caret.setKind(tok::caret); + Caret.setLocation(OpToken.getLocation().getLocWithOffset(1)); + Caret.setLength(1); + } + UnconsumeToken(OpToken); + PP.EnterToken(Caret, /*IsReinject=*/true); + return ParseRHSOfBinaryExpression(LHS, MinPrec); + } + } + // If we're potentially in a template-id, we may now be able to determine // whether we're actually in one or not. if (OpToken.isOneOf(tok::comma, tok::greater, tok::greatergreater, @@ -1208,6 +1229,18 @@ Parser::ParseCastExpression(CastParseKind ParseKind, bool isAddressOfOperand, AllowSuffix = false; Res = ParseUnaryExprOrTypeTraitExpression(); break; + case tok::caretcaret: { + if (!getLangOpts().Reflection) { + NotCastExpr = true; + return ExprError(); + } + + if (NotPrimaryExpression) + *NotPrimaryExpression = true; + AllowSuffix = false; + Res = ParseCXXReflectExpression(); + break; + } case tok::ampamp: { // unary-expression: '&&' identifier if (NotPrimaryExpression) *NotPrimaryExpression = true; diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp index ec62df83a203e..b41803d23cb25 100644 --- a/clang/lib/Parse/ParseOpenMP.cpp +++ b/clang/lib/Parse/ParseOpenMP.cpp @@ -3214,6 +3214,13 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind, ErrorFound = true; } + if (CKind == OMPC_transparent && PP.LookAhead(0).isNot(tok::l_paren)) { + SourceLocation Loc = ConsumeToken(); + SourceLocation LLoc = Tok.getLocation(); + Clause = Actions.OpenMP().ActOnOpenMPTransparentClause(nullptr, LLoc, + LLoc, Loc); + break; + } if ((CKind == OMPC_ordered || CKind == OMPC_partial) && PP.LookAhead(/*N=*/0).isNot(tok::l_paren)) Clause = ParseOpenMPClause(CKind, WrongDirective); diff --git a/clang/lib/Parse/ParseReflect.cpp b/clang/lib/Parse/ParseReflect.cpp new file mode 100644 index 0000000000000..b3914a3701a6d --- /dev/null +++ b/clang/lib/Parse/ParseReflect.cpp @@ -0,0 +1,52 @@ +//===--- ParseReflect.cpp - C++26 Reflection Parsing ---------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements parsing for reflection facilities. +// +//===----------------------------------------------------------------------===// + +#include "clang/AST/LocInfoType.h" +#include "clang/Basic/DiagnosticParse.h" +#include "clang/Parse/Parser.h" +#include "clang/Sema/EnterExpressionEvaluationContext.h" +using namespace clang; + +ExprResult Parser::ParseCXXReflectExpression() { + // TODO(reflection) : support parsing for global namespace, + // reflection-name, id-expression and remaining supports for + // type-id (placeholder type, alias template, etc.) + EnterExpressionEvaluationContext Unevaluated( + Actions, Sema::ExpressionEvaluationContext::Unevaluated); + assert(Tok.is(tok::caretcaret)); + SourceLocation CaretCaretLoc = ConsumeToken(); + SourceLocation OperandLoc = Tok.getLocation(); + + if (isCXXTypeId(TentativeCXXTypeIdContext::AsReflectionOperand)) { + TypeResult TR = ParseTypeName(/*TypeOf=*/nullptr); + if (TR.isInvalid()) + return ExprError(); + + TypeSourceInfo *TSI = nullptr; + QualType QT = Actions.GetTypeFromParser(TR.get(), &TSI); + + if (QT.isNull()) + return ExprError(); + + if (!TSI) + TSI = Actions.getASTContext().getTrivialTypeSourceInfo(QT, OperandLoc); + + QT = QT.getCanonicalType().getUnqualifiedType(); + if (TSI && QT.getTypePtr()->isBuiltinType()) { + // Only supports builtin types for now + return Actions.ActOnCXXReflectExpr(CaretCaretLoc, TSI); + } + } + + Diag(OperandLoc, diag::err_cannot_reflect_operand); + return ExprError(); +} diff --git a/clang/lib/Parse/ParseTentative.cpp b/clang/lib/Parse/ParseTentative.cpp index 9622a00687ca5..34b86db793890 100644 --- a/clang/lib/Parse/ParseTentative.cpp +++ b/clang/lib/Parse/ParseTentative.cpp @@ -574,6 +574,9 @@ bool Parser::isCXXTypeId(TentativeCXXTypeIdContext Context, bool &isAmbiguous) { } else if (Context == TentativeCXXTypeIdContext::InTrailingReturnType) { TPR = TPResult::True; isAmbiguous = true; + } else if (Context == TentativeCXXTypeIdContext::AsReflectionOperand) { + TPR = TPResult::True; + isAmbiguous = true; } else TPR = TPResult::False; } diff --git a/clang/lib/Sema/AnalysisBasedWarnings.cpp b/clang/lib/Sema/AnalysisBasedWarnings.cpp index 0c96b0afef1a7..4f04bc3999a24 100644 --- a/clang/lib/Sema/AnalysisBasedWarnings.cpp +++ b/clang/lib/Sema/AnalysisBasedWarnings.cpp @@ -2880,37 +2880,73 @@ class LifetimeSafetySemaHelperImpl : public LifetimeSafetySemaHelper { LifetimeSafetySemaHelperImpl(Sema &S) : S(S) {} void reportUseAfterFree(const Expr *IssueExpr, const Expr *UseExpr, - SourceLocation FreeLoc, Confidence C) override { + const Expr *MovedExpr, SourceLocation FreeLoc, + Confidence C) override { S.Diag(IssueExpr->getExprLoc(), - C == Confidence::Definite + MovedExpr ? diag::warn_lifetime_safety_loan_expires_moved_strict + : C == Confidence::Definite ? diag::warn_lifetime_safety_loan_expires_permissive : diag::warn_lifetime_safety_loan_expires_strict) << IssueExpr->getSourceRange(); + if (MovedExpr) + S.Diag(MovedExpr->getExprLoc(), diag::note_lifetime_safety_moved_here) + << MovedExpr->getSourceRange(); S.Diag(FreeLoc, diag::note_lifetime_safety_destroyed_here); S.Diag(UseExpr->getExprLoc(), diag::note_lifetime_safety_used_here) << UseExpr->getSourceRange(); } void reportUseAfterReturn(const Expr *IssueExpr, const Expr *ReturnExpr, - SourceLocation ExpiryLoc, Confidence C) override { + const Expr *MovedExpr, SourceLocation ExpiryLoc, + Confidence C) override { S.Diag(IssueExpr->getExprLoc(), - C == Confidence::Definite - ? diag::warn_lifetime_safety_return_stack_addr_permissive - : diag::warn_lifetime_safety_return_stack_addr_strict) + MovedExpr ? diag::warn_lifetime_safety_return_stack_addr_moved_strict + : diag::warn_lifetime_safety_return_stack_addr_permissive) << IssueExpr->getSourceRange(); + if (MovedExpr) + S.Diag(MovedExpr->getExprLoc(), diag::note_lifetime_safety_moved_here) + << MovedExpr->getSourceRange(); S.Diag(ReturnExpr->getExprLoc(), diag::note_lifetime_safety_returned_here) << ReturnExpr->getSourceRange(); } void reportDanglingField(const Expr *IssueExpr, const FieldDecl *DanglingField, + const Expr *MovedExpr, SourceLocation ExpiryLoc) override { - S.Diag(IssueExpr->getExprLoc(), diag::warn_lifetime_safety_dangling_field) + S.Diag(IssueExpr->getExprLoc(), + MovedExpr ? diag::warn_lifetime_safety_dangling_field_moved + : diag::warn_lifetime_safety_dangling_field) << IssueExpr->getSourceRange(); + if (MovedExpr) + S.Diag(MovedExpr->getExprLoc(), diag::note_lifetime_safety_moved_here) + << MovedExpr->getSourceRange(); S.Diag(DanglingField->getLocation(), diag::note_lifetime_safety_dangling_field_here) << DanglingField->getEndLoc(); } + void reportUseAfterInvalidation(const Expr *IssueExpr, const Expr *UseExpr, + const Expr *InvalidationExpr) override { + S.Diag(IssueExpr->getExprLoc(), diag::warn_lifetime_safety_invalidation) + << false << IssueExpr->getSourceRange(); + S.Diag(InvalidationExpr->getExprLoc(), + diag::note_lifetime_safety_invalidated_here) + << InvalidationExpr->getSourceRange(); + S.Diag(UseExpr->getExprLoc(), diag::note_lifetime_safety_used_here) + << UseExpr->getSourceRange(); + } + void reportUseAfterInvalidation(const ParmVarDecl *PVD, const Expr *UseExpr, + const Expr *InvalidationExpr) override { + S.Diag(PVD->getSourceRange().getBegin(), + diag::warn_lifetime_safety_invalidation) + << true << PVD->getSourceRange(); + S.Diag(InvalidationExpr->getExprLoc(), + diag::note_lifetime_safety_invalidated_here) + << InvalidationExpr->getSourceRange(); + S.Diag(UseExpr->getExprLoc(), diag::note_lifetime_safety_used_here) + << UseExpr->getSourceRange(); + } + void suggestLifetimeboundToParmVar(SuggestionScope Scope, const ParmVarDecl *ParmToAnnotate, const Expr *EscapeExpr) override { @@ -3117,9 +3153,14 @@ void clang::sema::AnalysisBasedWarnings::IssueWarnings( D->getBeginLoc()) || !Diags.isIgnored(diag::warn_lifetime_safety_loan_expires_strict, D->getBeginLoc()) || + !Diags.isIgnored(diag::warn_lifetime_safety_loan_expires_moved_strict, + D->getBeginLoc()) || !Diags.isIgnored(diag::warn_lifetime_safety_return_stack_addr_permissive, D->getBeginLoc()) || - !Diags.isIgnored(diag::warn_lifetime_safety_return_stack_addr_strict, + !Diags.isIgnored( + diag::warn_lifetime_safety_return_stack_addr_moved_strict, + D->getBeginLoc()) || + !Diags.isIgnored(diag::warn_lifetime_safety_invalidation, D->getBeginLoc()) || !Diags.isIgnored(diag::warn_lifetime_safety_noescape_escapes, D->getBeginLoc()); diff --git a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp index e799594023dbc..1dd7fd6fac455 100644 --- a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp +++ b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp @@ -167,6 +167,8 @@ struct BuiltinTypeMethodBuilder { StorageClass SC; llvm::SmallVector Params; llvm::SmallVector StmtsList; + TemplateParameterList *TemplateParams; + llvm::SmallVector TemplateParamDecls; // Argument placeholders, inspired by std::placeholder. These are the indices // of arguments to forward to `callBuiltin` and other method builder methods. @@ -190,6 +192,8 @@ struct BuiltinTypeMethodBuilder { Expr *convertPlaceholder(PlaceHolder PH); Expr *convertPlaceholder(LocalVar &Var); Expr *convertPlaceholder(Expr *E) { return E; } + // Converts a QualType to an Expr that carries type information to builtins. + Expr *convertPlaceholder(QualType Ty); public: friend BuiltinTypeDeclBuilder; @@ -198,7 +202,7 @@ struct BuiltinTypeMethodBuilder { QualType ReturnTy, bool IsConst = false, bool IsCtor = false, StorageClass SC = SC_None) : DeclBuilder(DB), Name(Name), ReturnTy(ReturnTy), Method(nullptr), - IsConst(IsConst), IsCtor(IsCtor), SC(SC) {} + IsConst(IsConst), IsCtor(IsCtor), SC(SC), TemplateParams(nullptr) {} BuiltinTypeMethodBuilder(BuiltinTypeDeclBuilder &DB, StringRef NameStr, QualType ReturnTy, bool IsConst = false, @@ -213,6 +217,7 @@ struct BuiltinTypeMethodBuilder { BuiltinTypeMethodBuilder &addParam(StringRef Name, QualType Ty, HLSLParamModifierAttr::Spelling Modifier = HLSLParamModifierAttr::Keyword_in); + QualType addTemplateTypeParam(StringRef Name); BuiltinTypeMethodBuilder &declareLocalVar(LocalVar &Var); template BuiltinTypeMethodBuilder &callBuiltin(StringRef BuiltinName, @@ -437,6 +442,15 @@ Expr *BuiltinTypeMethodBuilder::convertPlaceholder(LocalVar &Var) { VD->getType(), VK_LValue); } +Expr *BuiltinTypeMethodBuilder::convertPlaceholder(QualType Ty) { + ASTContext &AST = DeclBuilder.SemaRef.getASTContext(); + QualType PtrTy = AST.getPointerType(Ty); + // Creates a value-initialized null pointer of type Ty*. + return new (AST) CXXScalarValueInitExpr( + PtrTy, AST.getTrivialTypeSourceInfo(PtrTy, SourceLocation()), + SourceLocation()); +} + BuiltinTypeMethodBuilder::BuiltinTypeMethodBuilder(BuiltinTypeDeclBuilder &DB, StringRef NameStr, QualType ReturnTy, @@ -468,6 +482,22 @@ BuiltinTypeMethodBuilder::addParam(StringRef Name, QualType Ty, Params.emplace_back(II, Ty, Modifier); return *this; } +QualType BuiltinTypeMethodBuilder::addTemplateTypeParam(StringRef Name) { + assert(Method == nullptr && + "Cannot add template param, method already created"); + ASTContext &AST = DeclBuilder.SemaRef.getASTContext(); + unsigned Position = static_cast(TemplateParamDecls.size()); + auto *Decl = TemplateTypeParmDecl::Create( + AST, DeclBuilder.Record, SourceLocation(), SourceLocation(), + /* TemplateDepth */ 0, Position, + &AST.Idents.get(Name, tok::TokenKind::identifier), + /* Typename */ true, + /* ParameterPack */ false, + /* HasTypeConstraint*/ false); + TemplateParamDecls.push_back(Decl); + + return QualType(Decl->getTypeForDecl(), 0); +} void BuiltinTypeMethodBuilder::createDecl() { assert(Method == nullptr && "Method or constructor is already created"); @@ -522,8 +552,7 @@ void BuiltinTypeMethodBuilder::createDecl() { for (int I = 0, E = Params.size(); I != E; I++) { Param &MP = Params[I]; ParmVarDecl *Parm = ParmVarDecl::Create( - AST, Method->getDeclContext(), SourceLocation(), SourceLocation(), - &MP.NameII, MP.Ty, + AST, Method, SourceLocation(), SourceLocation(), &MP.NameII, MP.Ty, AST.getTrivialTypeSourceInfo(MP.Ty, SourceLocation()), SC_None, nullptr); if (MP.Modifier != HLSLParamModifierAttr::Keyword_in) { @@ -640,7 +669,7 @@ BuiltinTypeMethodBuilder &BuiltinTypeMethodBuilder::dereference(T Ptr) { Expr *Deref = UnaryOperator::Create(DeclBuilder.SemaRef.getASTContext(), PtrExpr, UO_Deref, PtrExpr->getType()->getPointeeType(), - VK_PRValue, OK_Ordinary, SourceLocation(), + VK_LValue, OK_Ordinary, SourceLocation(), /*CanOverflow=*/false, FPOptionsOverride()); StmtsList.push_back(Deref); return *this; @@ -791,7 +820,22 @@ BuiltinTypeDeclBuilder &BuiltinTypeMethodBuilder::finalize() { Method->setAccess(AS_public); Method->addAttr(AlwaysInlineAttr::CreateImplicit( AST, SourceRange(), AlwaysInlineAttr::CXX11_clang_always_inline)); - DeclBuilder.Record->addDecl(Method); + if (!TemplateParamDecls.empty()) { + TemplateParams = TemplateParameterList::Create( + AST, SourceLocation(), SourceLocation(), TemplateParamDecls, + SourceLocation(), nullptr); + + auto *FuncTemplate = FunctionTemplateDecl::Create(AST, DeclBuilder.Record, + SourceLocation(), Name, + TemplateParams, Method); + FuncTemplate->setAccess(AS_public); + FuncTemplate->setLexicalDeclContext(DeclBuilder.Record); + FuncTemplate->setImplicit(true); + Method->setDescribedFunctionTemplate(FuncTemplate); + DeclBuilder.Record->addDecl(FuncTemplate); + } else { + DeclBuilder.Record->addDecl(Method); + } } return DeclBuilder; } @@ -1211,6 +1255,51 @@ BuiltinTypeDeclBuilder &BuiltinTypeDeclBuilder::addLoadMethods() { return *this; } +BuiltinTypeDeclBuilder & +BuiltinTypeDeclBuilder::addByteAddressBufferLoadMethods() { + assert(!Record->isCompleteDefinition() && "record is already complete"); + + ASTContext &AST = SemaRef.getASTContext(); + + auto AddLoads = [&](StringRef MethodName, QualType ReturnType) { + IdentifierInfo &II = AST.Idents.get(MethodName, tok::TokenKind::identifier); + DeclarationName Load(&II); + + addHandleAccessFunction(Load, /*IsConst=*/false, /*IsRef=*/false, + ReturnType); + addLoadWithStatusFunction(Load, /*IsConst=*/false, ReturnType); + }; + + AddLoads("Load", AST.UnsignedIntTy); + AddLoads("Load2", AST.getExtVectorType(AST.UnsignedIntTy, 2)); + AddLoads("Load3", AST.getExtVectorType(AST.UnsignedIntTy, 3)); + AddLoads("Load4", AST.getExtVectorType(AST.UnsignedIntTy, 4)); + AddLoads("Load", AST.DependentTy); // Templated version + return *this; +} + +BuiltinTypeDeclBuilder & +BuiltinTypeDeclBuilder::addByteAddressBufferStoreMethods() { + assert(!Record->isCompleteDefinition() && "record is already complete"); + + ASTContext &AST = SemaRef.getASTContext(); + + auto AddStore = [&](StringRef MethodName, QualType ValueType) { + IdentifierInfo &II = AST.Idents.get(MethodName, tok::TokenKind::identifier); + DeclarationName Store(&II); + + addStoreFunction(Store, /*IsConst=*/false, ValueType); + }; + + AddStore("Store", AST.UnsignedIntTy); + AddStore("Store2", AST.getExtVectorType(AST.UnsignedIntTy, 2)); + AddStore("Store3", AST.getExtVectorType(AST.UnsignedIntTy, 3)); + AddStore("Store4", AST.getExtVectorType(AST.UnsignedIntTy, 4)); + AddStore("Store", AST.DependentTy); // Templated version + + return *this; +} + BuiltinTypeDeclBuilder & BuiltinTypeDeclBuilder::addSampleMethods(ResourceDimension Dim) { assert(!Record->isCompleteDefinition() && "record is already complete"); @@ -1353,30 +1442,50 @@ BuiltinTypeDeclBuilder &BuiltinTypeDeclBuilder::addDecrementCounterMethod() { .finalize(); } -BuiltinTypeDeclBuilder & -BuiltinTypeDeclBuilder::addLoadWithStatusFunction(DeclarationName &Name, - bool IsConst) { +BuiltinTypeDeclBuilder &BuiltinTypeDeclBuilder::addLoadWithStatusFunction( + DeclarationName &Name, bool IsConst, QualType ReturnTy) { assert(!Record->isCompleteDefinition() && "record is already complete"); ASTContext &AST = SemaRef.getASTContext(); using PH = BuiltinTypeMethodBuilder::PlaceHolder; + bool NeedsTypedBuiltin = !ReturnTy.isNull(); - QualType ReturnTy = getHandleElementType(); - return BuiltinTypeMethodBuilder(*this, Name, ReturnTy, IsConst) - .addParam("Index", AST.UnsignedIntTy) - .addParam("Status", AST.UnsignedIntTy, HLSLParamModifierAttr::Keyword_out) - .callBuiltin("__builtin_hlsl_resource_load_with_status", ReturnTy, - PH::Handle, PH::_0, PH::_1) - .finalize(); + // The empty QualType is a placeholder. The actual return type is set below. + BuiltinTypeMethodBuilder MMB(*this, Name, QualType(), IsConst); + + if (!NeedsTypedBuiltin) + ReturnTy = getHandleElementType(); + if (ReturnTy == AST.DependentTy) + ReturnTy = MMB.addTemplateTypeParam("element_type"); + MMB.ReturnTy = ReturnTy; + + MMB.addParam("Index", AST.UnsignedIntTy) + .addParam("Status", AST.UnsignedIntTy, + HLSLParamModifierAttr::Keyword_out); + + if (NeedsTypedBuiltin) + MMB.callBuiltin("__builtin_hlsl_resource_load_with_status_typed", ReturnTy, + PH::Handle, PH::_0, PH::_1, ReturnTy); + else + MMB.callBuiltin("__builtin_hlsl_resource_load_with_status", ReturnTy, + PH::Handle, PH::_0, PH::_1); + + return MMB.finalize(); } -BuiltinTypeDeclBuilder & -BuiltinTypeDeclBuilder::addHandleAccessFunction(DeclarationName &Name, - bool IsConst, bool IsRef) { +BuiltinTypeDeclBuilder &BuiltinTypeDeclBuilder::addHandleAccessFunction( + DeclarationName &Name, bool IsConst, bool IsRef, QualType ElemTy) { assert(!Record->isCompleteDefinition() && "record is already complete"); ASTContext &AST = SemaRef.getASTContext(); using PH = BuiltinTypeMethodBuilder::PlaceHolder; + bool NeedsTypedBuiltin = !ElemTy.isNull(); - QualType ElemTy = getHandleElementType(); + // The empty QualType is a placeholder. The actual return type is set below. + BuiltinTypeMethodBuilder MMB(*this, Name, QualType(), IsConst); + + if (!NeedsTypedBuiltin) + ElemTy = getHandleElementType(); + if (ElemTy == AST.DependentTy) + ElemTy = MMB.addTemplateTypeParam("element_type"); QualType AddrSpaceElemTy = AST.getAddrSpaceQualType(ElemTy, LangAS::hlsl_device); QualType ElemPtrTy = AST.getPointerType(AddrSpaceElemTy); @@ -1392,12 +1501,41 @@ BuiltinTypeDeclBuilder::addHandleAccessFunction(DeclarationName &Name, if (IsConst) ReturnTy.addConst(); } + MMB.ReturnTy = ReturnTy; + + MMB.addParam("Index", AST.UnsignedIntTy); + + if (NeedsTypedBuiltin) + MMB.callBuiltin("__builtin_hlsl_resource_getpointer_typed", ElemPtrTy, + PH::Handle, PH::_0, ElemTy); + else + MMB.callBuiltin("__builtin_hlsl_resource_getpointer", ElemPtrTy, PH::Handle, + PH::_0); + + return MMB.dereference(PH::LastStmt).finalize(); +} + +BuiltinTypeDeclBuilder & +BuiltinTypeDeclBuilder::addStoreFunction(DeclarationName &Name, bool IsConst, + QualType ValueTy) { + assert(!Record->isCompleteDefinition() && "record is already complete"); + ASTContext &AST = SemaRef.getASTContext(); + using PH = BuiltinTypeMethodBuilder::PlaceHolder; + + BuiltinTypeMethodBuilder MMB(*this, Name, AST.VoidTy, IsConst); + + if (ValueTy == AST.DependentTy) + ValueTy = MMB.addTemplateTypeParam("element_type"); + QualType AddrSpaceElemTy = + AST.getAddrSpaceQualType(ValueTy, LangAS::hlsl_device); + QualType ElemPtrTy = AST.getPointerType(AddrSpaceElemTy); - return BuiltinTypeMethodBuilder(*this, Name, ReturnTy, IsConst) - .addParam("Index", AST.UnsignedIntTy) - .callBuiltin("__builtin_hlsl_resource_getpointer", ElemPtrTy, PH::Handle, - PH::_0) + return MMB.addParam("Index", AST.UnsignedIntTy) + .addParam("Value", ValueTy) + .callBuiltin("__builtin_hlsl_resource_getpointer_typed", ElemPtrTy, + PH::Handle, PH::_0, ValueTy) .dereference(PH::LastStmt) + .assign(PH::LastStmt, PH::_1) .finalize(); } diff --git a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h index a505e2fb466dd..aa6967e1eb725 100644 --- a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h +++ b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h @@ -92,13 +92,19 @@ class BuiltinTypeDeclBuilder { // Builtin types methods BuiltinTypeDeclBuilder &addLoadMethods(); + BuiltinTypeDeclBuilder &addByteAddressBufferLoadMethods(); + BuiltinTypeDeclBuilder &addByteAddressBufferStoreMethods(); BuiltinTypeDeclBuilder &addSampleMethods(ResourceDimension Dim); BuiltinTypeDeclBuilder &addIncrementCounterMethod(); BuiltinTypeDeclBuilder &addDecrementCounterMethod(); BuiltinTypeDeclBuilder &addHandleAccessFunction(DeclarationName &Name, - bool IsConst, bool IsRef); - BuiltinTypeDeclBuilder &addLoadWithStatusFunction(DeclarationName &Name, - bool IsConst); + bool IsConst, bool IsRef, + QualType ElemTy = QualType()); + BuiltinTypeDeclBuilder & + addLoadWithStatusFunction(DeclarationName &Name, bool IsConst, + QualType ReturnTy = QualType()); + BuiltinTypeDeclBuilder &addStoreFunction(DeclarationName &Name, bool IsConst, + QualType ValueType); BuiltinTypeDeclBuilder &addAppendMethod(); BuiltinTypeDeclBuilder &addConsumeMethod(); diff --git a/clang/lib/Sema/HLSLExternalSemaSource.cpp b/clang/lib/Sema/HLSLExternalSemaSource.cpp index 92a4247e8796a..f7862b3a3f594 100644 --- a/clang/lib/Sema/HLSLExternalSemaSource.cpp +++ b/clang/lib/Sema/HLSLExternalSemaSource.cpp @@ -503,6 +503,7 @@ void HLSLExternalSemaSource::defineHLSLTypesWithForwardDeclarations() { onCompletion(Decl, [this](CXXRecordDecl *Decl) { setupBufferType(Decl, *SemaPtr, ResourceClass::SRV, /*IsROV=*/false, /*RawBuffer=*/true, /*HasCounter=*/false) + .addByteAddressBufferLoadMethods() .addGetDimensionsMethodForBuffer() .completeDefinition(); }); @@ -511,6 +512,8 @@ void HLSLExternalSemaSource::defineHLSLTypesWithForwardDeclarations() { onCompletion(Decl, [this](CXXRecordDecl *Decl) { setupBufferType(Decl, *SemaPtr, ResourceClass::UAV, /*IsROV=*/false, /*RawBuffer=*/true, /*HasCounter=*/false) + .addByteAddressBufferLoadMethods() + .addByteAddressBufferStoreMethods() .addGetDimensionsMethodForBuffer() .completeDefinition(); }); @@ -567,4 +570,5 @@ void HLSLExternalSemaSource::CompleteType(TagDecl *Tag) { if (It == Completions.end()) return; It->second(Record); + Completions.erase(It); } diff --git a/clang/lib/Sema/SemaAMDGPU.cpp b/clang/lib/Sema/SemaAMDGPU.cpp index 4261e1849133f..2fa29ef966cfd 100644 --- a/clang/lib/Sema/SemaAMDGPU.cpp +++ b/clang/lib/Sema/SemaAMDGPU.cpp @@ -89,6 +89,30 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, case AMDGPU::BI__builtin_amdgcn_s_setreg: return SemaRef.BuiltinConstantArgRange(TheCall, /*ArgNum=*/0, /*Low=*/0, /*High=*/UINT16_MAX); + case AMDGPU::BI__builtin_amdgcn_s_wait_event: { + llvm::APSInt Result; + if (SemaRef.BuiltinConstantArg(TheCall, 0, Result)) + return true; + + bool IsGFX12Plus = Builtin::evaluateRequiredTargetFeatures( + "gfx12-insts", CallerFeatureMap); + + // gfx11 -> gfx12 changed the interpretation of the bitmask. gfx12 inverted + // the intepretation for export_ready, but shifted the used bit by 1. Thus + // waiting for the export_ready event can use a value of 2 universally. + if (((IsGFX12Plus && !Result[1]) || (!IsGFX12Plus && Result[0])) || + Result.getZExtValue() > 2) { + Expr *ArgExpr = TheCall->getArg(0); + SemaRef.targetDiag(ArgExpr->getExprLoc(), + diag::warn_amdgpu_s_wait_event_mask_no_effect_target) + << ArgExpr->getSourceRange(); + SemaRef.targetDiag(ArgExpr->getExprLoc(), + diag::note_amdgpu_s_wait_event_suggested_value) + << ArgExpr->getSourceRange(); + } + + return false; + } case AMDGPU::BI__builtin_amdgcn_mov_dpp: return checkMovDPPFunctionCall(TheCall, 5, 1); case AMDGPU::BI__builtin_amdgcn_mov_dpp8: @@ -119,6 +143,13 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_16x8B: case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_8x16B: return checkCoopAtomicFunctionCall(TheCall, /*IsStore=*/true); + case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b32: + case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b64: + case AMDGPU::BI__builtin_amdgcn_flat_load_monitor_b128: + case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b32: + case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b64: + case AMDGPU::BI__builtin_amdgcn_global_load_monitor_b128: + return checkAtomicMonitorLoad(TheCall); case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f32_i32: case AMDGPU::BI__builtin_amdgcn_image_load_1darray_v4f32_i32: case AMDGPU::BI__builtin_amdgcn_image_load_1d_v4f16_i32: @@ -341,6 +372,27 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID, return false; } +bool SemaAMDGPU::checkAtomicOrderingCABIArg(Expr *E, bool MayLoad, + bool MayStore) { + Expr::EvalResult AtomicOrdArgRes; + if (!E->EvaluateAsInt(AtomicOrdArgRes, getASTContext())) + llvm_unreachable("Intrinsic requires imm for atomic ordering argument!"); + auto Ord = + llvm::AtomicOrderingCABI(AtomicOrdArgRes.Val.getInt().getZExtValue()); + + // Atomic ordering cannot be acq_rel in any case, acquire for stores or + // release for loads. + if (!llvm::isValidAtomicOrderingCABI((unsigned)Ord) || + (!(MayLoad && MayStore) && (Ord == llvm::AtomicOrderingCABI::acq_rel)) || + (!MayLoad && Ord == llvm::AtomicOrderingCABI::acquire) || + (!MayStore && Ord == llvm::AtomicOrderingCABI::release)) { + return Diag(E->getBeginLoc(), diag::warn_atomic_op_has_invalid_memory_order) + << 0 << E->getSourceRange(); + } + + return false; +} + bool SemaAMDGPU::checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore) { bool Fail = false; @@ -355,31 +407,47 @@ bool SemaAMDGPU::checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore) { << PtrArg->getSourceRange(); } + Expr *AO = TheCall->getArg(IsStore ? 2 : 1); + Expr *Scope = TheCall->getArg(TheCall->getNumArgs() - 1); + + if (AO->isValueDependent() || Scope->isValueDependent()) + return false; + // Check atomic ordering - Expr *AtomicOrdArg = TheCall->getArg(IsStore ? 2 : 1); - Expr::EvalResult AtomicOrdArgRes; - if (!AtomicOrdArg->EvaluateAsInt(AtomicOrdArgRes, getASTContext())) - llvm_unreachable("Intrinsic requires imm for atomic ordering argument!"); - auto Ord = - llvm::AtomicOrderingCABI(AtomicOrdArgRes.Val.getInt().getZExtValue()); + Fail |= + checkAtomicOrderingCABIArg(TheCall->getArg(IsStore ? 2 : 1), + /*MayLoad=*/!IsStore, /*MayStore=*/IsStore); - // Atomic ordering cannot be acq_rel in any case, acquire for stores or - // release for loads. - if (!llvm::isValidAtomicOrderingCABI((unsigned)Ord) || - (Ord == llvm::AtomicOrderingCABI::acq_rel) || - Ord == (IsStore ? llvm::AtomicOrderingCABI::acquire - : llvm::AtomicOrderingCABI::release)) { - return Diag(AtomicOrdArg->getBeginLoc(), - diag::warn_atomic_op_has_invalid_memory_order) - << 0 << AtomicOrdArg->getSourceRange(); + // Last argument is the syncscope as a string literal. + if (!isa(Scope->IgnoreParenImpCasts())) { + Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal) + << Scope->getSourceRange(); + Fail = true; } - // Last argument is a string literal - Expr *Arg = TheCall->getArg(TheCall->getNumArgs() - 1); - if (!isa(Arg->IgnoreParenImpCasts())) { - Fail = true; - Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal) - << Arg->getSourceRange(); + return Fail; +} + +bool SemaAMDGPU::checkAtomicMonitorLoad(CallExpr *TheCall) { + bool Fail = false; + + Expr *AO = TheCall->getArg(1); + Expr *Scope = TheCall->getArg(TheCall->getNumArgs() - 1); + + if (AO->isValueDependent() || Scope->isValueDependent()) + return false; + + Fail |= checkAtomicOrderingCABIArg(TheCall->getArg(1), /*MayLoad=*/true, + /*MayStore=*/false); + + auto ScopeModel = AtomicScopeModel::create(AtomicScopeModelKind::Generic); + if (std::optional Result = + Scope->getIntegerConstantExpr(SemaRef.Context)) { + if (!ScopeModel->isValid(Result->getZExtValue())) { + Diag(Scope->getBeginLoc(), diag::err_atomic_op_has_invalid_sync_scope) + << Scope->getSourceRange(); + Fail = true; + } } return Fail; diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index e2e1b37572364..e82c82d881a8a 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -1217,12 +1217,12 @@ void Sema::checkFortifiedBuiltinMemoryFunction(FunctionDecl *FD, return std::nullopt; const Expr *ObjArg = TheCall->getArg(NewIndex); - uint64_t Result; - if (!ObjArg->tryEvaluateObjectSize(Result, getASTContext(), BOSType)) - return std::nullopt; - - // Get the object size in the target's size_t width. - return llvm::APSInt::getUnsigned(Result).extOrTrunc(SizeTypeWidth); + if (std::optional ObjSize = + ObjArg->tryEvaluateObjectSize(getASTContext(), BOSType)) { + // Get the object size in the target's size_t width. + return llvm::APSInt::getUnsigned(*ObjSize).extOrTrunc(SizeTypeWidth); + } + return std::nullopt; }; auto ComputeStrLenArgument = @@ -1233,11 +1233,13 @@ void Sema::checkFortifiedBuiltinMemoryFunction(FunctionDecl *FD, unsigned NewIndex = *IndexOptional; const Expr *ObjArg = TheCall->getArg(NewIndex); - uint64_t Result; - if (!ObjArg->tryEvaluateStrLen(Result, getASTContext())) - return std::nullopt; - // Add 1 for null byte. - return llvm::APSInt::getUnsigned(Result + 1).extOrTrunc(SizeTypeWidth); + + if (std::optional Result = + ObjArg->tryEvaluateStrLen(getASTContext())) { + // Add 1 for null byte. + return llvm::APSInt::getUnsigned(*Result + 1).extOrTrunc(SizeTypeWidth); + } + return std::nullopt; }; std::optional SourceSize; @@ -1839,6 +1841,32 @@ static ExprResult PointerAuthAuthAndResign(Sema &S, CallExpr *Call) { return Call; } +static ExprResult PointerAuthAuthLoadRelativeAndSign(Sema &S, CallExpr *Call) { + if (S.checkArgCount(Call, 6)) + return ExprError(); + if (checkPointerAuthEnabled(S, Call)) + return ExprError(); + const Expr *AddendExpr = Call->getArg(5); + bool AddendIsConstInt = AddendExpr->isIntegerConstantExpr(S.Context); + if (!AddendIsConstInt) { + const Expr *Arg = Call->getArg(5)->IgnoreParenImpCasts(); + DeclRefExpr *DRE = cast(Call->getCallee()->IgnoreParenCasts()); + FunctionDecl *FDecl = cast(DRE->getDecl()); + S.Diag(Arg->getBeginLoc(), diag::err_constant_integer_last_arg_type) + << FDecl->getDeclName() << Arg->getSourceRange(); + } + if (checkPointerAuthValue(S, Call->getArgs()[0], PAO_Auth) || + checkPointerAuthKey(S, Call->getArgs()[1]) || + checkPointerAuthValue(S, Call->getArgs()[2], PAO_Discriminator) || + checkPointerAuthKey(S, Call->getArgs()[3]) || + checkPointerAuthValue(S, Call->getArgs()[4], PAO_Discriminator) || + !AddendIsConstInt) + return ExprError(); + + Call->setType(Call->getArgs()[0]->getType()); + return Call; +} + static ExprResult PointerAuthStringDiscriminator(Sema &S, CallExpr *Call) { if (checkPointerAuthEnabled(S, Call)) return ExprError(); @@ -2117,6 +2145,8 @@ bool Sema::CheckTSBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, return AMDGPU().CheckAMDGCNBuiltinFunctionCall(BuiltinID, TheCall); case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: return RISCV().CheckBuiltinFunctionCall(TI, BuiltinID, TheCall); case llvm::Triple::loongarch32: case llvm::Triple::loongarch64: @@ -2249,7 +2279,8 @@ static bool BuiltinBswapg(Sema &S, CallExpr *TheCall) { return true; } if (const auto *BT = dyn_cast(ArgTy)) { - if (BT->getNumBits() % 16 != 0 && BT->getNumBits() != 8) { + if (BT->getNumBits() % 16 != 0 && BT->getNumBits() != 8 && + BT->getNumBits() != 1) { S.Diag(Arg->getBeginLoc(), diag::err_bswapg_invalid_bit_width) << ArgTy << BT->getNumBits(); return true; @@ -3284,6 +3315,8 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, return PointerAuthSignGenericData(*this, TheCall); case Builtin::BI__builtin_ptrauth_auth_and_resign: return PointerAuthAuthAndResign(*this, TheCall); + case Builtin::BI__builtin_ptrauth_auth_load_relative_and_sign: + return PointerAuthAuthLoadRelativeAndSign(*this, TheCall); case Builtin::BI__builtin_ptrauth_string_discriminator: return PointerAuthStringDiscriminator(*this, TheCall); @@ -15421,6 +15454,10 @@ void Sema::CheckArrayAccess(const Expr *expr) { expr = cast(expr)->getBase(); break; } + case Stmt::CXXMemberCallExprClass: { + expr = cast(expr)->getImplicitObjectArgument(); + break; + } case Stmt::ArraySectionExprClass: { const ArraySectionExpr *ASE = cast(expr); // FIXME: We should probably be checking all of the elements to the diff --git a/clang/lib/Sema/SemaCoroutine.cpp b/clang/lib/Sema/SemaCoroutine.cpp index c0aba832dba94..90af7340c4614 100644 --- a/clang/lib/Sema/SemaCoroutine.cpp +++ b/clang/lib/Sema/SemaCoroutine.cpp @@ -18,6 +18,7 @@ #include "clang/AST/Decl.h" #include "clang/AST/Expr.h" #include "clang/AST/ExprCXX.h" +#include "clang/AST/IgnoreExpr.h" #include "clang/AST/StmtCXX.h" #include "clang/Basic/Builtins.h" #include "clang/Lex/Preprocessor.h" @@ -841,7 +842,11 @@ static bool isAttributedCoroAwaitElidable(const QualType &QT) { } static void applySafeElideContext(Expr *Operand) { - auto *Call = dyn_cast(Operand->IgnoreImplicit()); + // Strip both implicit nodes and parentheses to find the underlying CallExpr. + // The AST may have these in either order, so we apply both transformations + // iteratively until reaching a fixed point. + auto *Call = dyn_cast(IgnoreExprNodes( + Operand, IgnoreImplicitSingleStep, IgnoreParensSingleStep)); if (!Call || !Call->isPRValue()) return; diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 3b2c93b9fe7b5..7af6ce62d08dd 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -9194,6 +9194,12 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) { RISCV().checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext), CallerFeatureMap); } + + if (T.hasAddressSpace() && + !CheckVarDeclSizeAddressSpace(NewVD, T.getAddressSpace())) { + NewVD->setInvalidDecl(); + return; + } } bool Sema::CheckVariableDeclaration(VarDecl *NewVD, LookupResult &Previous) { diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index bee42cce09aca..5dbff18fff7a9 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -5140,6 +5140,8 @@ static void handleConstantAttr(Sema &S, Decl *D, const ParsedAttr &AL) { S.Diag(AL.getLoc(), diag::err_cuda_nonstatic_constdev); return; } + if (!S.CheckVarDeclSizeAddressSpace(VD, LangAS::cuda_constant)) + return; // constexpr variable may already get an implicit constant attr, which should // be replaced by the explicit constant attr. if (auto *A = D->getAttr()) { @@ -5159,6 +5161,8 @@ static void handleSharedAttr(Sema &S, Decl *D, const ParsedAttr &AL) { S.Diag(AL.getLoc(), diag::err_cuda_extern_shared) << VD; return; } + if (!S.CheckVarDeclSizeAddressSpace(VD, LangAS::cuda_shared)) + return; if (S.getLangOpts().CUDA && VD->hasLocalStorage() && S.CUDA().DiagIfHostCode(AL.getLoc(), diag::err_cuda_host_shared) << S.CUDA().CurrentTarget()) @@ -5208,6 +5212,8 @@ static void handleDeviceAttr(Sema &S, Decl *D, const ParsedAttr &AL) { S.Diag(AL.getLoc(), diag::err_cuda_nonstatic_constdev); return; } + if (!S.CheckVarDeclSizeAddressSpace(VD, LangAS::cuda_device)) + return; } if (auto *A = D->getAttr()) { @@ -5224,6 +5230,8 @@ static void handleManagedAttr(Sema &S, Decl *D, const ParsedAttr &AL) { S.Diag(AL.getLoc(), diag::err_cuda_nonstatic_constdev); return; } + if (!S.CheckVarDeclSizeAddressSpace(VD, LangAS::cuda_device)) + return; } if (!D->hasAttr()) D->addAttr(::new (S.Context) HIPManagedAttr(S.Context, AL)); @@ -6387,6 +6395,8 @@ static void handleInterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) { break; case llvm::Triple::riscv32: case llvm::Triple::riscv64: + case llvm::Triple::riscv32be: + case llvm::Triple::riscv64be: S.RISCV().handleInterruptAttr(D, AL); break; default: diff --git a/clang/lib/Sema/SemaExceptionSpec.cpp b/clang/lib/Sema/SemaExceptionSpec.cpp index 6208d6679df73..8df01a8a616c3 100644 --- a/clang/lib/Sema/SemaExceptionSpec.cpp +++ b/clang/lib/Sema/SemaExceptionSpec.cpp @@ -1276,6 +1276,7 @@ CanThrowResult Sema::canThrow(const Stmt *S) { case Expr::DesignatedInitUpdateExprClass: case Expr::ExprWithCleanupsClass: case Expr::ExtVectorElementExprClass: + case Expr::MatrixElementExprClass: case Expr::InitListExprClass: case Expr::ArrayInitLoopExprClass: case Expr::MemberExprClass: @@ -1380,6 +1381,7 @@ CanThrowResult Sema::canThrow(const Stmt *S) { case Expr::CXXNoexceptExprClass: case Expr::CXXNullPtrLiteralExprClass: case Expr::CXXPseudoDestructorExprClass: + case Expr::CXXReflectExprClass: case Expr::CXXScalarValueInitExprClass: case Expr::CXXThisExprClass: case Expr::CXXUuidofExprClass: diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 5795a71b5cae8..29b6129344ca5 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -18,7 +18,7 @@ #include "clang/AST/ASTDiagnostic.h" #include "clang/AST/ASTLambda.h" #include "clang/AST/ASTMutationListener.h" -#include "clang/AST/Attrs.inc" +#include "clang/AST/Attr.h" #include "clang/AST/CXXInheritance.h" #include "clang/AST/Decl.h" #include "clang/AST/DeclObjC.h" @@ -6823,9 +6823,10 @@ ExprResult Sema::BuildCallExpr(Scope *Scope, Expr *Fn, SourceLocation LParenLoc, // First, ensure that the Arg is an RValue. if (ArgExprs[Idx]->isGLValue()) { - ArgExprs[Idx] = ImplicitCastExpr::Create( - Context, ArgExprs[Idx]->getType(), CK_NoOp, ArgExprs[Idx], - nullptr, VK_PRValue, FPOptionsOverride()); + ExprResult Res = DefaultLvalueConversion(ArgExprs[Idx]); + if (Res.isInvalid()) + return ExprError(); + ArgExprs[Idx] = Res.get(); } // Construct a new arg type with address space of Param @@ -14137,6 +14138,9 @@ static bool CheckForModifiableLvalue(Expr *E, SourceLocation Loc, Sema &S) { case Expr::MLV_DuplicateVectorComponents: DiagID = diag::err_typecheck_duplicate_vector_components_not_mlvalue; break; + case Expr::MLV_DuplicateMatrixComponents: + DiagID = diag::err_typecheck_duplicate_matrix_components_not_mlvalue; + break; case Expr::MLV_NoSetterProperty: llvm_unreachable("readonly properties should be processed differently"); case Expr::MLV_InvalidMessageExpression: @@ -17922,6 +17926,16 @@ void Sema::PushExpressionEvaluationContextForFunction( } } +ExprResult Sema::ActOnCXXReflectExpr(SourceLocation CaretCaretLoc, + TypeSourceInfo *TSI) { + return BuildCXXReflectExpr(CaretCaretLoc, TSI); +} + +ExprResult Sema::BuildCXXReflectExpr(SourceLocation CaretCaretLoc, + TypeSourceInfo *TSI) { + return CXXReflectExpr::Create(Context, CaretCaretLoc, TSI); +} + namespace { const DeclRefExpr *CheckPossibleDeref(Sema &S, const Expr *PossibleDeref) { diff --git a/clang/lib/Sema/SemaExprMember.cpp b/clang/lib/Sema/SemaExprMember.cpp index aedfc5e88b1c6..e2f26ef5aa2b2 100644 --- a/clang/lib/Sema/SemaExprMember.cpp +++ b/clang/lib/Sema/SemaExprMember.cpp @@ -14,11 +14,13 @@ #include "clang/AST/DeclTemplate.h" #include "clang/AST/ExprCXX.h" #include "clang/AST/ExprObjC.h" +#include "clang/AST/TypeBase.h" #include "clang/Lex/Preprocessor.h" #include "clang/Sema/Lookup.h" #include "clang/Sema/Overload.h" #include "clang/Sema/Scope.h" #include "clang/Sema/ScopeInfo.h" +#include "clang/Sema/SemaHLSL.h" #include "clang/Sema/SemaObjC.h" #include "clang/Sema/SemaOpenMP.h" @@ -1617,6 +1619,21 @@ static ExprResult LookupMemberExpr(Sema &S, LookupResult &R, ExtVectorElementExpr(ret, VK, BaseExpr.get(), *Member, MemberLoc); } + if (S.getLangOpts().HLSL && BaseType->isConstantMatrixType()) { + IdentifierInfo *Member = MemberName.getAsIdentifierInfo(); + ExprValueKind VK = BaseExpr.get()->getValueKind(); + QualType Ret = S.HLSL().checkMatrixComponent(S, BaseType, VK, OpLoc, Member, + MemberLoc); + if (Ret.isNull()) + return ExprError(); + Qualifiers BaseQ = + S.Context.getCanonicalType(BaseExpr.get()->getType()).getQualifiers(); + Ret = S.Context.getQualifiedType(Ret, BaseQ); + + return new (S.Context) + MatrixElementExpr(Ret, VK, BaseExpr.get(), *Member, MemberLoc); + } + // Adjust builtin-sel to the appropriate redefinition type if that's // not just a pointer to builtin-sel again. if (IsArrow && BaseType->isSpecificBuiltinType(BuiltinType::ObjCSel) && diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index a880cb2271270..813ab16fece73 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -12,7 +12,6 @@ #include "clang/AST/ASTConsumer.h" #include "clang/AST/ASTContext.h" #include "clang/AST/Attr.h" -#include "clang/AST/Attrs.inc" #include "clang/AST/Decl.h" #include "clang/AST/DeclBase.h" #include "clang/AST/DeclCXX.h" @@ -3189,10 +3188,13 @@ static bool CheckAnyScalarOrVector(Sema *S, CallExpr *TheCall, return false; } -static bool CheckWaveActive(Sema *S, CallExpr *TheCall) { +// Check that the argument is not a bool or vector +// Returns true on error +static bool CheckNotBoolScalarOrVector(Sema *S, CallExpr *TheCall, + unsigned ArgIndex) { QualType BoolType = S->getASTContext().BoolTy; - assert(TheCall->getNumArgs() >= 1); - QualType ArgType = TheCall->getArg(0)->getType(); + assert(ArgIndex < TheCall->getNumArgs()); + QualType ArgType = TheCall->getArg(ArgIndex)->getType(); auto *VTy = ArgType->getAs(); // is the bool or vector if (S->Context.hasSameUnqualifiedType(ArgType, BoolType) || @@ -3206,6 +3208,18 @@ static bool CheckWaveActive(Sema *S, CallExpr *TheCall) { return false; } +static bool CheckWaveActive(Sema *S, CallExpr *TheCall) { + if (CheckNotBoolScalarOrVector(S, TheCall, 0)) + return true; + return false; +} + +static bool CheckWavePrefix(Sema *S, CallExpr *TheCall) { + if (CheckNotBoolScalarOrVector(S, TheCall, 0)) + return true; + return false; +} + static bool CheckBoolSelect(Sema *S, CallExpr *TheCall) { assert(TheCall->getNumArgs() == 3); Expr *Arg1 = TheCall->getArg(1); @@ -3363,6 +3377,31 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { break; } + case Builtin::BI__builtin_hlsl_resource_getpointer_typed: { + if (SemaRef.checkArgCount(TheCall, 3) || + CheckResourceHandle(&SemaRef, TheCall, 0) || + CheckArgTypeMatches(&SemaRef, TheCall->getArg(1), + SemaRef.getASTContext().UnsignedIntTy)) + return true; + + QualType ElementTy = TheCall->getArg(2)->getType(); + assert(ElementTy->isPointerType() && + "expected pointer type for second argument"); + ElementTy = ElementTy->getPointeeType(); + + // Reject array types + if (ElementTy->isArrayType()) + return SemaRef.Diag( + cast(SemaRef.CurContext)->getPointOfInstantiation(), + diag::err_invalid_use_of_array_type); + + auto ReturnType = + SemaRef.Context.getAddrSpaceQualType(ElementTy, LangAS::hlsl_device); + ReturnType = SemaRef.Context.getPointerType(ReturnType); + TheCall->setType(ReturnType); + + break; + } case Builtin::BI__builtin_hlsl_resource_load_with_status: { if (SemaRef.checkArgCount(TheCall, 3) || CheckResourceHandle(&SemaRef, TheCall, 0) || @@ -3380,6 +3419,31 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { break; } + case Builtin::BI__builtin_hlsl_resource_load_with_status_typed: { + if (SemaRef.checkArgCount(TheCall, 4) || + CheckResourceHandle(&SemaRef, TheCall, 0) || + CheckArgTypeMatches(&SemaRef, TheCall->getArg(1), + SemaRef.getASTContext().UnsignedIntTy) || + CheckArgTypeMatches(&SemaRef, TheCall->getArg(2), + SemaRef.getASTContext().UnsignedIntTy) || + CheckModifiableLValue(&SemaRef, TheCall, 2)) + return true; + + QualType ReturnType = TheCall->getArg(3)->getType(); + assert(ReturnType->isPointerType() && + "expected pointer type for second argument"); + ReturnType = ReturnType->getPointeeType(); + + // Reject array types + if (ReturnType->isArrayType()) + return SemaRef.Diag( + cast(SemaRef.CurContext)->getPointOfInstantiation(), + diag::err_invalid_use_of_array_type); + + TheCall->setType(ReturnType); + + break; + } case Builtin::BI__builtin_hlsl_resource_sample: { if (SemaRef.checkArgCountRange(TheCall, 3, 5)) return true; @@ -3741,6 +3805,20 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; break; } + case Builtin::BI__builtin_hlsl_wave_prefix_sum: { + if (SemaRef.checkArgCount(TheCall, 1)) + return true; + + // Ensure input expr type is a scalar/vector and the same as the return type + if (CheckAnyScalarOrVector(&SemaRef, TheCall, 0)) + return true; + if (CheckWavePrefix(&SemaRef, TheCall)) + return true; + ExprResult Expr = TheCall->getArg(0); + QualType ArgTyExpr = Expr.get()->getType(); + TheCall->setType(ArgTyExpr); + break; + } case Builtin::BI__builtin_hlsl_elementwise_splitdouble: { if (SemaRef.checkArgCount(TheCall, 3)) return true; @@ -4972,6 +5050,187 @@ bool SemaHLSL::transformInitList(const InitializedEntity &Entity, return true; } +static QualType ReportMatrixInvalidMember(Sema &S, StringRef Name, + StringRef Expected, + SourceLocation OpLoc, + SourceLocation CompLoc) { + S.Diag(OpLoc, diag::err_builtin_matrix_invalid_member) + << Name << Expected << SourceRange(CompLoc); + return QualType(); +} + +QualType SemaHLSL::checkMatrixComponent(Sema &S, QualType baseType, + ExprValueKind &VK, SourceLocation OpLoc, + const IdentifierInfo *CompName, + SourceLocation CompLoc) { + const auto *MT = baseType->castAs(); + StringRef AccessorName = CompName->getName(); + assert(!AccessorName.empty() && "Matrix Accessor must have a name"); + + unsigned Rows = MT->getNumRows(); + unsigned Cols = MT->getNumColumns(); + bool IsZeroBasedAccessor = false; + unsigned ChunkLen = 0; + if (AccessorName.size() < 2) + return ReportMatrixInvalidMember(S, AccessorName, + "length 4 for zero based: \'_mRC\' or " + "length 3 for one-based: \'_RC\' accessor", + OpLoc, CompLoc); + + if (AccessorName[0] == '_') { + if (AccessorName[1] == 'm') { + IsZeroBasedAccessor = true; + ChunkLen = 4; // zero-based: "_mRC" + } else { + ChunkLen = 3; // one-based: "_RC" + } + } else + return ReportMatrixInvalidMember( + S, AccessorName, "zero based: \'_mRC\' or one-based: \'_RC\' accessor", + OpLoc, CompLoc); + + if (AccessorName.size() % ChunkLen != 0) { + const llvm::StringRef Expected = IsZeroBasedAccessor + ? "zero based: '_mRC' accessor" + : "one-based: '_RC' accessor"; + + return ReportMatrixInvalidMember(S, AccessorName, Expected, OpLoc, CompLoc); + } + + auto isDigit = [](char c) { return c >= '0' && c <= '9'; }; + auto isZeroBasedIndex = [](unsigned i) { return i <= 3; }; + auto isOneBasedIndex = [](unsigned i) { return i >= 1 && i <= 4; }; + + bool HasRepeated = false; + SmallVector Seen(Rows * Cols, false); + unsigned NumComponents = 0; + const char *Begin = AccessorName.data(); + + for (unsigned I = 0, E = AccessorName.size(); I < E; I += ChunkLen) { + const char *Chunk = Begin + I; + char RowChar = 0, ColChar = 0; + if (IsZeroBasedAccessor) { + // Zero-based: "_mRC" + if (Chunk[0] != '_' || Chunk[1] != 'm') { + char Bad = (Chunk[0] != '_') ? Chunk[0] : Chunk[1]; + return ReportMatrixInvalidMember( + S, StringRef(&Bad, 1), "\'_m\' prefix", + OpLoc.getLocWithOffset(I + (Bad == Chunk[0] ? 1 : 2)), CompLoc); + } + RowChar = Chunk[2]; + ColChar = Chunk[3]; + } else { + // One-based: "_RC" + if (Chunk[0] != '_') + return ReportMatrixInvalidMember( + S, StringRef(&Chunk[0], 1), "\'_\' prefix", + OpLoc.getLocWithOffset(I + 1), CompLoc); + RowChar = Chunk[1]; + ColChar = Chunk[2]; + } + + // Must be digits. + bool IsDigitsError = false; + if (!isDigit(RowChar)) { + unsigned BadPos = IsZeroBasedAccessor ? 2 : 1; + ReportMatrixInvalidMember(S, StringRef(&RowChar, 1), "row as integer", + OpLoc.getLocWithOffset(I + BadPos + 1), + CompLoc); + IsDigitsError = true; + } + + if (!isDigit(ColChar)) { + unsigned BadPos = IsZeroBasedAccessor ? 3 : 2; + ReportMatrixInvalidMember(S, StringRef(&ColChar, 1), "column as integer", + OpLoc.getLocWithOffset(I + BadPos + 1), + CompLoc); + IsDigitsError = true; + } + if (IsDigitsError) + return QualType(); + + unsigned Row = RowChar - '0'; + unsigned Col = ColChar - '0'; + + bool HasIndexingError = false; + if (IsZeroBasedAccessor) { + // 0-based [0..3] + if (!isZeroBasedIndex(Row)) { + S.Diag(OpLoc, diag::err_hlsl_matrix_element_not_in_bounds) + << /*row*/ 0 << /*zero-based*/ 0 << SourceRange(CompLoc); + HasIndexingError = true; + } + if (!isZeroBasedIndex(Col)) { + S.Diag(OpLoc, diag::err_hlsl_matrix_element_not_in_bounds) + << /*col*/ 1 << /*zero-based*/ 0 << SourceRange(CompLoc); + HasIndexingError = true; + } + } else { + // 1-based [1..4] + if (!isOneBasedIndex(Row)) { + S.Diag(OpLoc, diag::err_hlsl_matrix_element_not_in_bounds) + << /*row*/ 0 << /*one-based*/ 1 << SourceRange(CompLoc); + HasIndexingError = true; + } + if (!isOneBasedIndex(Col)) { + S.Diag(OpLoc, diag::err_hlsl_matrix_element_not_in_bounds) + << /*col*/ 1 << /*one-based*/ 1 << SourceRange(CompLoc); + HasIndexingError = true; + } + // Convert to 0-based after range checking. + --Row; + --Col; + } + + if (HasIndexingError) + return QualType(); + + // Note: matrix swizzle index is hard coded. That means Row and Col can + // potentially be larger than Rows and Cols if matrix size is less than + // the max index size. + bool HasBoundsError = false; + if (Row >= Rows) { + Diag(OpLoc, diag::err_hlsl_matrix_index_out_of_bounds) + << /*Row*/ 0 << Row << Rows << SourceRange(CompLoc); + HasBoundsError = true; + } + if (Col >= Cols) { + Diag(OpLoc, diag::err_hlsl_matrix_index_out_of_bounds) + << /*Col*/ 1 << Col << Cols << SourceRange(CompLoc); + HasBoundsError = true; + } + if (HasBoundsError) + return QualType(); + + unsigned FlatIndex = Row * Cols + Col; + if (Seen[FlatIndex]) + HasRepeated = true; + Seen[FlatIndex] = true; + ++NumComponents; + } + if (NumComponents == 0 || NumComponents > 4) { + S.Diag(OpLoc, diag::err_hlsl_matrix_swizzle_invalid_length) + << NumComponents << SourceRange(CompLoc); + return QualType(); + } + + QualType ElemTy = MT->getElementType(); + QualType VT = S.Context.getExtVectorType(ElemTy, NumComponents); + if (HasRepeated) + VK = VK_PRValue; + + for (Sema::ExtVectorDeclsType::iterator + I = S.ExtVectorDecls.begin(S.getExternalSource()), + E = S.ExtVectorDecls.end(); + I != E; ++I) { + if ((*I)->getUnderlyingType() == VT) + return S.Context.getTypedefType(ElaboratedTypeKeyword::None, + /*Qualifier=*/std::nullopt, *I); + } + + return VT; +} + bool SemaHLSL::handleInitialization(VarDecl *VDecl, Expr *&Init) { const HLSLVkConstantIdAttr *ConstIdAttr = VDecl->getAttr(); diff --git a/clang/lib/Sema/SemaObjCProperty.cpp b/clang/lib/Sema/SemaObjCProperty.cpp index 67c554c50a8ce..4d7efed23939e 100644 --- a/clang/lib/Sema/SemaObjCProperty.cpp +++ b/clang/lib/Sema/SemaObjCProperty.cpp @@ -269,41 +269,6 @@ Decl *SemaObjC::ActOnProperty(Scope *S, SourceLocation AtLoc, return Res; } -static ObjCPropertyAttribute::Kind -makePropertyAttributesAsWritten(unsigned Attributes) { - unsigned attributesAsWritten = 0; - if (Attributes & ObjCPropertyAttribute::kind_readonly) - attributesAsWritten |= ObjCPropertyAttribute::kind_readonly; - if (Attributes & ObjCPropertyAttribute::kind_readwrite) - attributesAsWritten |= ObjCPropertyAttribute::kind_readwrite; - if (Attributes & ObjCPropertyAttribute::kind_getter) - attributesAsWritten |= ObjCPropertyAttribute::kind_getter; - if (Attributes & ObjCPropertyAttribute::kind_setter) - attributesAsWritten |= ObjCPropertyAttribute::kind_setter; - if (Attributes & ObjCPropertyAttribute::kind_assign) - attributesAsWritten |= ObjCPropertyAttribute::kind_assign; - if (Attributes & ObjCPropertyAttribute::kind_retain) - attributesAsWritten |= ObjCPropertyAttribute::kind_retain; - if (Attributes & ObjCPropertyAttribute::kind_strong) - attributesAsWritten |= ObjCPropertyAttribute::kind_strong; - if (Attributes & ObjCPropertyAttribute::kind_weak) - attributesAsWritten |= ObjCPropertyAttribute::kind_weak; - if (Attributes & ObjCPropertyAttribute::kind_copy) - attributesAsWritten |= ObjCPropertyAttribute::kind_copy; - if (Attributes & ObjCPropertyAttribute::kind_unsafe_unretained) - attributesAsWritten |= ObjCPropertyAttribute::kind_unsafe_unretained; - if (Attributes & ObjCPropertyAttribute::kind_nonatomic) - attributesAsWritten |= ObjCPropertyAttribute::kind_nonatomic; - if (Attributes & ObjCPropertyAttribute::kind_atomic) - attributesAsWritten |= ObjCPropertyAttribute::kind_atomic; - if (Attributes & ObjCPropertyAttribute::kind_class) - attributesAsWritten |= ObjCPropertyAttribute::kind_class; - if (Attributes & ObjCPropertyAttribute::kind_direct) - attributesAsWritten |= ObjCPropertyAttribute::kind_direct; - - return (ObjCPropertyAttribute::Kind)attributesAsWritten; -} - static bool LocPropertyAttribute( ASTContext &Context, const char *attrName, SourceLocation LParenLoc, SourceLocation &Loc) { if (LParenLoc.isMacroID()) @@ -629,7 +594,7 @@ ObjCPropertyDecl *SemaObjC::CreatePropertyDecl( PDecl->setGetterName(GetterSel, GetterNameLoc); PDecl->setSetterName(SetterSel, SetterNameLoc); PDecl->setPropertyAttributesAsWritten( - makePropertyAttributesAsWritten(AttributesAsWritten)); + static_cast(AttributesAsWritten)); SemaRef.ProcessDeclAttributes(S, PDecl, FD.D); diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 456e94a009d2f..e90884a89bf6e 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -17476,6 +17476,10 @@ OMPClause *SemaOpenMP::ActOnOpenMPTransparentClause(Expr *ImpexTypeArg, SourceLocation StartLoc, SourceLocation LParenLoc, SourceLocation EndLoc) { + if (!ImpexTypeArg) { + return new (getASTContext()) + OMPTransparentClause(ImpexTypeArg, StartLoc, LParenLoc, EndLoc); + } QualType Ty = ImpexTypeArg->getType(); if (const auto *TT = Ty->getAs()) { diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index 49877d180ead0..d5512f216ddb3 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -13,7 +13,6 @@ #include "clang/Sema/SemaRISCV.h" #include "clang/AST/ASTContext.h" #include "clang/AST/Attr.h" -#include "clang/AST/Attrs.inc" #include "clang/AST/Decl.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/TargetBuiltins.h" diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index 255c6ace8f603..37309d057fbe7 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -1413,7 +1413,8 @@ namespace { } void RememberSubstitution(MultiLevelTemplateArgumentList Old) { - const_cast(this->TemplateArgs) = Old; + const_cast(this->TemplateArgs) = + std::move(Old); } TemplateArgument diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp index 28d1d63ff7acf..348823ab2e9ca 100644 --- a/clang/lib/Sema/SemaType.cpp +++ b/clang/lib/Sema/SemaType.cpp @@ -7424,6 +7424,24 @@ bool Sema::CheckImplicitNullabilityTypeSpecifier(QualType &Type, /*isContextSensitive*/ false, AllowArrayTypes, OverrideExisting); } +bool Sema::CheckVarDeclSizeAddressSpace(const VarDecl *VD, LangAS AS) { + QualType T = VD->getType(); + + // Check that the variable's type can fit in the specified address space. This + // is determined by how far a pointer in that address space can reach. + llvm::APInt MaxSizeForAddrSpace = + llvm::APInt::getMaxValue(Context.getTargetInfo().getPointerWidth(AS)); + std::optional TSizeInChars = Context.getTypeSizeInCharsIfKnown(T); + if (TSizeInChars && static_cast(TSizeInChars->getQuantity()) > + MaxSizeForAddrSpace.getZExtValue()) { + Diag(VD->getLocation(), diag::err_type_too_large_for_address_space) + << T << MaxSizeForAddrSpace; + return false; + } + + return true; +} + /// Check the application of the Objective-C '__kindof' qualifier to /// the given type. static bool checkObjCKindOfType(TypeProcessingState &state, QualType &type, diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index fb32b0e70e3c9..6a4d88b28c614 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -3098,14 +3098,15 @@ class TreeTransform { Init); } - /// Build a new extended vector element access expression. + /// Build a new extended vector or matrix element access expression. /// /// By default, performs semantic analysis to build the new expression. /// Subclasses may override this routine to provide different behavior. - ExprResult RebuildExtVectorElementExpr(Expr *Base, SourceLocation OpLoc, - bool IsArrow, - SourceLocation AccessorLoc, - IdentifierInfo &Accessor) { + ExprResult RebuildExtVectorOrMatrixElementExpr(Expr *Base, + SourceLocation OpLoc, + bool IsArrow, + SourceLocation AccessorLoc, + IdentifierInfo &Accessor) { CXXScopeSpec SS; DeclarationNameInfo NameInfo(&Accessor, AccessorLoc); @@ -13054,6 +13055,13 @@ ExprResult TreeTransform::TransformSYCLUniqueStableNameExpr( E->getLocation(), E->getLParenLocation(), E->getRParenLocation(), NewT); } +template +ExprResult TreeTransform::TransformCXXReflectExpr(CXXReflectExpr *E) { + // TODO(reflection): Implement its transform + assert(false && "not implemented yet"); + return ExprError(); +} + template ExprResult TreeTransform::TransformPredefinedExpr(PredefinedExpr *E) { @@ -13965,11 +13973,29 @@ TreeTransform::TransformExtVectorElementExpr(ExtVectorElementExpr *E) { // FIXME: Bad source location SourceLocation FakeOperatorLoc = SemaRef.getLocForEndOfToken(E->getBase()->getEndLoc()); - return getDerived().RebuildExtVectorElementExpr( + return getDerived().RebuildExtVectorOrMatrixElementExpr( Base.get(), FakeOperatorLoc, E->isArrow(), E->getAccessorLoc(), E->getAccessor()); } +template +ExprResult +TreeTransform::TransformMatrixElementExpr(MatrixElementExpr *E) { + ExprResult Base = getDerived().TransformExpr(E->getBase()); + if (Base.isInvalid()) + return ExprError(); + + if (!getDerived().AlwaysRebuild() && Base.get() == E->getBase()) + return E; + + // FIXME: Bad source location + SourceLocation FakeOperatorLoc = + SemaRef.getLocForEndOfToken(E->getBase()->getEndLoc()); + return getDerived().RebuildExtVectorOrMatrixElementExpr( + Base.get(), FakeOperatorLoc, /*isArrow*/ false, E->getAccessorLoc(), + E->getAccessor()); +} + template ExprResult TreeTransform::TransformInitListExpr(InitListExpr *E) { diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp index 5553139dfaa46..a18fccb6518d2 100644 --- a/clang/lib/Serialization/ASTReaderStmt.cpp +++ b/clang/lib/Serialization/ASTReaderStmt.cpp @@ -535,6 +535,11 @@ void ASTStmtReader::VisitCapturedStmt(CapturedStmt *S) { } } +void ASTStmtReader::VisitCXXReflectExpr(CXXReflectExpr *E) { + // TODO(Reflection): Implement this. + assert(false && "not implemented yet"); +} + void ASTStmtReader::VisitSYCLKernelCallStmt(SYCLKernelCallStmt *S) { VisitStmt(S); S->setOriginalStmt(cast(Record.readSubStmt())); @@ -1231,6 +1236,13 @@ void ASTStmtReader::VisitExtVectorElementExpr(ExtVectorElementExpr *E) { E->setAccessorLoc(readSourceLocation()); } +void ASTStmtReader::VisitMatrixElementExpr(MatrixElementExpr *E) { + VisitExpr(E); + E->setBase(Record.readSubExpr()); + E->setAccessor(Record.readIdentifier()); + E->setAccessorLoc(readSourceLocation()); +} + void ASTStmtReader::VisitInitListExpr(InitListExpr *E) { VisitExpr(E); if (auto *SyntForm = cast_or_null(Record.readSubStmt())) @@ -3377,6 +3389,10 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) { S = new (Context) ExtVectorElementExpr(Empty); break; + case EXPR_MATRIX_ELEMENT: + S = new (Context) MatrixElementExpr(Empty); + break; + case EXPR_INIT_LIST: S = new (Context) InitListExpr(Empty); break; @@ -4542,6 +4558,10 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) { case EXPR_HLSL_OUT_ARG: S = HLSLOutArgExpr::CreateEmpty(Context); break; + case EXPR_REFLECT: { + S = CXXReflectExpr::CreateEmpty(Context); + break; + } } // We hit a STMT_STOP, so we're done with this expression. diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index 3e10bbfedfe65..0368fc2d6e3cc 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -1526,10 +1526,12 @@ void ASTWriter::WriteControlBlock(Preprocessor &PP, StringRef isysroot) { // Write out all other paths relative to the base directory if possible. BaseDirectory.assign(BaseDir->begin(), BaseDir->end()); - } else if (!isysroot.empty()) { - // Write out paths relative to the sysroot if possible. - BaseDirectory = std::string(isysroot); } + } else if (!isysroot.empty()) { + // Write out paths relative to the sysroot if possible. + SmallString<128> CleanedSysroot(isysroot); + cleanPathForOutput(PP.getFileManager(), CleanedSysroot); + BaseDirectory.assign(CleanedSysroot.begin(), CleanedSysroot.end()); } // Module map file @@ -1752,6 +1754,11 @@ void ASTWriter::WriteControlBlock(Preprocessor &PP, StringRef isysroot) { Record.push_back(PPOpts.UsePredefines); // Detailed record is important since it is used for the module cache hash. Record.push_back(PPOpts.DetailedRecord); + + // FIXME: Using `AddString` to record `ImplicitPCHInclude` does not handle + // relocatable files. We probably should call + // `AddPath(PPOpts.ImplicitPCHInclude, Record)` to properly support chained + // relocatable PCHs. AddString(PPOpts.ImplicitPCHInclude, Record); Record.push_back(static_cast(PPOpts.ObjCXXARCStandardLibrary)); Stream.EmitRecord(PREPROCESSOR_OPTIONS, Record); @@ -6115,6 +6122,10 @@ ASTFileSignature ASTWriter::WriteASTCore(Sema *SemaPtr, StringRef isysroot, endian::Writer LE(Out, llvm::endianness::little); LE.write(static_cast(M.Kind)); + // FIXME: Storing a PCH's name (M.FileName) as a string does not handle + // relocatable files. We probably should call + // `PreparePathForOutput(M.FileName)` to properly support relocatable + // PCHs. StringRef Name = M.isModule() ? M.ModuleName : M.FileName; LE.write(Name.size()); Out.write(Name.data(), Name.size()); diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp index 8f22156f93487..4fcac4d0261ab 100644 --- a/clang/lib/Serialization/ASTWriterStmt.cpp +++ b/clang/lib/Serialization/ASTWriterStmt.cpp @@ -473,6 +473,11 @@ void ASTStmtWriter::VisitCoyieldExpr(CoyieldExpr *E) { Code = serialization::EXPR_COYIELD; } +void ASTStmtWriter::VisitCXXReflectExpr(CXXReflectExpr *E) { + // TODO(Reflection): Implement this. + assert(false && "not implemented yet"); +} + void ASTStmtWriter::VisitDependentCoawaitExpr(DependentCoawaitExpr *E) { VisitExpr(E); Record.AddSourceLocation(E->getKeywordLoc()); @@ -1200,6 +1205,14 @@ void ASTStmtWriter::VisitExtVectorElementExpr(ExtVectorElementExpr *E) { Code = serialization::EXPR_EXT_VECTOR_ELEMENT; } +void ASTStmtWriter::VisitMatrixElementExpr(MatrixElementExpr *E) { + VisitExpr(E); + Record.AddStmt(E->getBase()); + Record.AddIdentifierRef(&E->getAccessor()); + Record.AddSourceLocation(E->getAccessorLoc()); + Code = serialization::EXPR_MATRIX_ELEMENT; +} + void ASTStmtWriter::VisitInitListExpr(InitListExpr *E) { VisitExpr(E); // NOTE: only add the (possibly null) syntactic form. diff --git a/clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt b/clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt index 2df36d8e672ae..3edbd7ebdc1bf 100644 --- a/clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt +++ b/clang/lib/StaticAnalyzer/Checkers/CMakeLists.txt @@ -86,6 +86,7 @@ add_clang_library(clangStaticAnalyzerCheckers ObjCSelfInitChecker.cpp ObjCSuperDeallocChecker.cpp ObjCUnusedIVarsChecker.cpp + OpaqueSTLFunctionsModeling.cpp OSObjectCStyleCast.cpp PaddingChecker.cpp PointerArithChecker.cpp diff --git a/clang/lib/StaticAnalyzer/Checkers/OpaqueSTLFunctionsModeling.cpp b/clang/lib/StaticAnalyzer/Checkers/OpaqueSTLFunctionsModeling.cpp new file mode 100644 index 0000000000000..cf94773d5d199 --- /dev/null +++ b/clang/lib/StaticAnalyzer/Checkers/OpaqueSTLFunctionsModeling.cpp @@ -0,0 +1,54 @@ +//===--- OpaqueSTLFunctionsModeling.cpp -----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Models STL functions whose best accurate model is to invalidate their +// arguments. Only functions where this simple approach is sufficient and won't +// interfere with the modeling of other checkers should be put here. +// +//===----------------------------------------------------------------------===// + +#include "clang/StaticAnalyzer/Checkers/BuiltinCheckerRegistration.h" +#include "clang/StaticAnalyzer/Core/Checker.h" +#include "clang/StaticAnalyzer/Core/PathSensitive/CallDescription.h" +#include "clang/StaticAnalyzer/Core/PathSensitive/CallEvent.h" +#include "clang/StaticAnalyzer/Core/PathSensitive/CheckerContext.h" + +using namespace clang; +using namespace ento; + +namespace { +class OpaqueSTLFunctionsModeling : public Checker { +public: + bool evalCall(const CallEvent &Call, CheckerContext &C) const; + +private: + const CallDescriptionSet ModeledFunctions{ + {CDM::SimpleFunc, {"std", "sort"}}, + {CDM::SimpleFunc, {"std", "stable_sort"}}, + {CDM::SimpleFunc, {"std", "inplace_merge"}}}; +}; +} // namespace + +bool OpaqueSTLFunctionsModeling::evalCall(const CallEvent &Call, + CheckerContext &C) const { + if (!ModeledFunctions.contains(Call)) + return false; + + ProgramStateRef InvalidatedRegionsState = + Call.invalidateRegions(C.blockCount(), C.getState()); + C.addTransition(InvalidatedRegionsState); + return true; +} + +void ento::registerOpaqueSTLFunctionsModeling(CheckerManager &Mgr) { + Mgr.registerChecker(); +} + +bool ento::shouldRegisterOpaqueSTLFunctionsModeling(const CheckerManager &Mgr) { + return Mgr.getLangOpts().CPlusPlus; +} diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp index 15971168934b5..4a9a3be2b6614 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp @@ -337,8 +337,13 @@ bool isAllocInit(const Expr *E, const Expr **InnerExpr) { auto NameForFirstSlot = Selector.getNameForSlot(0); if (NameForFirstSlot.starts_with("alloc") || NameForFirstSlot.starts_with("copy") || - NameForFirstSlot.starts_with("mutableCopy")) + NameForFirstSlot.starts_with("mutableCopy")) { + if (auto *MD = ObjCMsgExpr->getMethodDecl()) { + if (MD->getReturnType()->isVoidType()) + return false; + } return true; + } if (!NameForFirstSlot.starts_with("init") && !NameForFirstSlot.starts_with("_init")) return false; diff --git a/clang/lib/StaticAnalyzer/Core/CoreEngine.cpp b/clang/lib/StaticAnalyzer/Core/CoreEngine.cpp index 95a843ee87571..bfaa874f1632a 100644 --- a/clang/lib/StaticAnalyzer/Core/CoreEngine.cpp +++ b/clang/lib/StaticAnalyzer/Core/CoreEngine.cpp @@ -320,12 +320,12 @@ void CoreEngine::HandleBlockEdge(const BlockEdge &L, ExplodedNode *Pred) { // Call into the ExprEngine to process entering the CFGBlock. BlockEntrance BE(L.getSrc(), L.getDst(), Pred->getLocationContext()); ExplodedNodeSet DstNodes; - NodeBuilderWithSinks NodeBuilder(Pred, DstNodes, BuilderCtx, BE); - ExprEng.processCFGBlockEntrance(L, NodeBuilder, Pred); + NodeBuilder Builder(Pred, DstNodes, BuilderCtx); + ExprEng.processCFGBlockEntrance(L, BE, Builder, Pred); // Auto-generate a node. - if (!NodeBuilder.hasGeneratedNodes()) { - NodeBuilder.generateNode(Pred->State, Pred); + if (!Builder.hasGeneratedNodes()) { + Builder.generateNode(BE, Pred->State, Pred); } ExplodedNodeSet CheckerNodes; @@ -449,10 +449,7 @@ void CoreEngine::HandleBlockExit(const CFGBlock * B, ExplodedNode *Pred) { return; case Stmt::SwitchStmtClass: { - SwitchNodeBuilder builder(Pred, B, cast(Term)->getCond(), - this); - - ExprEng.processSwitch(builder); + ExprEng.processSwitch(cast(Term), *this, B, Pred); return; } @@ -705,8 +702,6 @@ ExplodedNode* NodeBuilder::generateNodeImpl(const ProgramPoint &Loc, return N; } -void NodeBuilderWithSinks::anchor() {} - StmtNodeBuilder::~StmtNodeBuilder() { if (EnclosingBldr) for (const auto I : Frontier) @@ -729,14 +724,12 @@ ExplodedNode *BranchNodeBuilder::generateNode(ProgramStateRef State, return Succ; } -ExplodedNode* -IndirectGotoNodeBuilder::generateNode(const iterator &I, - ProgramStateRef St, - bool IsSink) { +ExplodedNode *IndirectGotoNodeBuilder::generateNode(const CFGBlock *Block, + ProgramStateRef St, + bool IsSink) { bool IsNew; - ExplodedNode *Succ = - Eng.G.getNode(BlockEdge(Src, I.getBlock(), Pred->getLocationContext()), - St, IsSink, &IsNew); + ExplodedNode *Succ = Eng.G.getNode( + BlockEdge(Src, Block, Pred->getLocationContext()), St, IsSink, &IsNew); Succ->addPredecessor(Pred, Eng.G); if (!IsNew) @@ -748,13 +741,11 @@ IndirectGotoNodeBuilder::generateNode(const iterator &I, return Succ; } -ExplodedNode* -SwitchNodeBuilder::generateCaseStmtNode(const iterator &I, - ProgramStateRef St) { +ExplodedNode *SwitchNodeBuilder::generateCaseStmtNode(const CFGBlock *Block, + ProgramStateRef St) { bool IsNew; - ExplodedNode *Succ = - Eng.G.getNode(BlockEdge(Src, I.getBlock(), Pred->getLocationContext()), - St, false, &IsNew); + ExplodedNode *Succ = Eng.G.getNode( + BlockEdge(Src, Block, Pred->getLocationContext()), St, false, &IsNew); Succ->addPredecessor(Pred, Eng.G); if (!IsNew) return nullptr; diff --git a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp index a6a96b594fe85..883c7b5d66c32 100644 --- a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp +++ b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp @@ -1726,6 +1726,7 @@ void ExprEngine::Visit(const Stmt *S, ExplodedNode *Pred, switch (S->getStmtClass()) { // C++, OpenMP and ARC stuff we don't support yet. case Stmt::CXXDependentScopeMemberExprClass: + case Stmt::CXXReflectExprClass: case Stmt::CXXTryStmtClass: case Stmt::CXXTypeidExprClass: case Stmt::CXXUuidofExprClass: @@ -1930,6 +1931,7 @@ void ExprEngine::Visit(const Stmt *S, ExplodedNode *Pred, case Stmt::DesignatedInitUpdateExprClass: case Stmt::ArrayInitIndexExprClass: case Stmt::ExtVectorElementExprClass: + case Stmt::MatrixElementExprClass: case Stmt::ImaginaryLiteralClass: case Stmt::ObjCAtCatchStmtClass: case Stmt::ObjCAtFinallyStmtClass: @@ -2557,19 +2559,23 @@ static const LocationContext *getInlinedLocationContext(ExplodedNode *Node, } /// Block entrance. (Update counters). +/// FIXME: `BlockEdge &L` is only used for debug statistics, consider removing +/// it and using `BlockEntrance &BE` (where `BlockEntrance` is a subtype of +/// `ProgramPoint`) for statistical purposes. void ExprEngine::processCFGBlockEntrance(const BlockEdge &L, - NodeBuilderWithSinks &nodeBuilder, + const BlockEntrance &BE, + NodeBuilder &Builder, ExplodedNode *Pred) { // If we reach a loop which has a known bound (and meets // other constraints) then consider completely unrolling it. if(AMgr.options.ShouldUnrollLoops) { unsigned maxBlockVisitOnPath = AMgr.options.maxBlockVisitOnPath; - const Stmt *Term = nodeBuilder.getContext().getBlock()->getTerminatorStmt(); + const Stmt *Term = Builder.getContext().getBlock()->getTerminatorStmt(); if (Term) { ProgramStateRef NewState = updateLoopStack(Term, AMgr.getASTContext(), Pred, maxBlockVisitOnPath); if (NewState != Pred->getState()) { - ExplodedNode *UpdatedNode = nodeBuilder.generateNode(NewState, Pred); + ExplodedNode *UpdatedNode = Builder.generateNode(BE, NewState, Pred); if (!UpdatedNode) return; Pred = UpdatedNode; @@ -2582,10 +2588,10 @@ void ExprEngine::processCFGBlockEntrance(const BlockEdge &L, // If this block is terminated by a loop and it has already been visited the // maximum number of times, widen the loop. - unsigned int BlockCount = nodeBuilder.getContext().blockCount(); + unsigned int BlockCount = Builder.getContext().blockCount(); if (BlockCount == AMgr.options.maxBlockVisitOnPath - 1 && AMgr.options.ShouldWidenLoops) { - const Stmt *Term = nodeBuilder.getContext().getBlock()->getTerminatorStmt(); + const Stmt *Term = Builder.getContext().getBlock()->getTerminatorStmt(); if (!isa_and_nonnull(Term)) return; @@ -2600,16 +2606,17 @@ void ExprEngine::processCFGBlockEntrance(const BlockEdge &L, // Here we just pass the the first CFG element in the block. ProgramStateRef WidenedState = getWidenedLoopState(Pred->getState(), LCtx, BlockCount, - *nodeBuilder.getContext().getBlock()->ref_begin()); - nodeBuilder.generateNode(WidenedState, Pred); + *Builder.getContext().getBlock()->ref_begin()); + Builder.generateNode(BE, WidenedState, Pred); return; } // FIXME: Refactor this into a checker. if (BlockCount >= AMgr.options.maxBlockVisitOnPath) { - static SimpleProgramPointTag tag(TagProviderName, "Block count exceeded"); + static SimpleProgramPointTag Tag(TagProviderName, "Block count exceeded"); + const ProgramPoint TaggedLoc = BE.withTag(&Tag); const ExplodedNode *Sink = - nodeBuilder.generateSink(Pred->getState(), Pred, &tag); + Builder.generateSink(TaggedLoc, Pred->getState(), Pred); if (const LocationContext *LC = getInlinedLocationContext(Pred, G)) { // FIXME: This will unconditionally prevent inlining this function (even @@ -2996,13 +3003,11 @@ void ExprEngine::processIndirectGoto(IndirectGotoNodeBuilder &builder) { // (3) We have no clue about the label. Dispatch to all targets. // - using iterator = IndirectGotoNodeBuilder::iterator; - if (std::optional LV = V.getAs()) { const LabelDecl *L = LV->getLabel(); - for (iterator Succ : builder) { - if (Succ.getLabel() == L) { + for (const CFGBlock *Succ : builder) { + if (cast(Succ->getLabel())->getDecl() == L) { builder.generateNode(Succ, state); return; } @@ -3022,7 +3027,7 @@ void ExprEngine::processIndirectGoto(IndirectGotoNodeBuilder &builder) { // This is really a catch-all. We don't support symbolics yet. // FIXME: Implement dispatch for symbolic pointers. - for (iterator Succ : builder) + for (const CFGBlock *Succ : builder) builder.generateNode(Succ, state); } @@ -3107,37 +3112,34 @@ void ExprEngine::processEndOfFunction(NodeBuilderContext& BC, /// ProcessSwitch - Called by CoreEngine. Used to generate successor /// nodes by processing the 'effects' of a switch statement. -void ExprEngine::processSwitch(SwitchNodeBuilder& builder) { - using iterator = SwitchNodeBuilder::iterator; +void ExprEngine::processSwitch(const SwitchStmt *Switch, CoreEngine &CoreEng, + const CFGBlock *B, ExplodedNode *Pred) { + const Expr *Condition = Switch->getCond(); - ProgramStateRef state = builder.getState(); - const Expr *CondE = builder.getCondition(); - SVal CondV_untested = state->getSVal(CondE, builder.getLocationContext()); + SwitchNodeBuilder Builder(Pred, B, CoreEng); - if (CondV_untested.isUndef()) { - //ExplodedNode* N = builder.generateDefaultCaseNode(state, true); - // FIXME: add checker - //UndefBranches.insert(N); + ProgramStateRef State = Pred->getState(); + SVal CondV = State->getSVal(Condition, Pred->getLocationContext()); + if (CondV.isUndef()) { + // ExplodedNode* N = builder.generateDefaultCaseNode(state, true); + // FIXME: add checker + // UndefBranches.insert(N); return; } - DefinedOrUnknownSVal CondV = CondV_untested.castAs(); - ProgramStateRef DefaultSt = state; + std::optional CondNL = CondV.getAs(); - iterator I = builder.begin(), EI = builder.end(); - bool defaultIsFeasible = I == EI; - - for ( ; I != EI; ++I) { + for (const CFGBlock *Block : Builder) { // Successor may be pruned out during CFG construction. - if (!I.getBlock()) + if (!Block) continue; - const CaseStmt *Case = I.getCase(); + const CaseStmt *Case = cast(Block->getLabel()); // Evaluate the LHS of the case value. llvm::APSInt V1 = Case->getLHS()->EvaluateKnownConstInt(getContext()); - assert(V1.getBitWidth() == getContext().getIntWidth(CondE->getType())); + assert(V1.getBitWidth() == getContext().getIntWidth(Condition->getType())); // Get the RHS of the case, if it exists. llvm::APSInt V2; @@ -3146,29 +3148,25 @@ void ExprEngine::processSwitch(SwitchNodeBuilder& builder) { else V2 = V1; - ProgramStateRef StateCase; - if (std::optional NL = CondV.getAs()) - std::tie(StateCase, DefaultSt) = - DefaultSt->assumeInclusiveRange(*NL, V1, V2); - else // UnknownVal - StateCase = DefaultSt; - - if (StateCase) - builder.generateCaseStmtNode(I, StateCase); - - // Now "assume" that the case doesn't match. Add this state - // to the default state (if it is feasible). - if (DefaultSt) - defaultIsFeasible = true; - else { - defaultIsFeasible = false; - break; + ProgramStateRef StateMatching; + if (CondNL) { + // Split the state: this "case:" matches / does not match. + std::tie(StateMatching, State) = + State->assumeInclusiveRange(*CondNL, V1, V2); + } else { + // The switch condition is UnknownVal, so we enter each "case:" without + // any state update. + StateMatching = State; } - } - if (!defaultIsFeasible) - return; + if (StateMatching) + Builder.generateCaseStmtNode(Block, StateMatching); + // If _not_ entering the current case is infeasible, we are done with + // processing this branch. + if (!State) + return; + } // If we have switch(enum value), the default branch is not // feasible if all of the enum constants not covered by 'case:' statements // are not feasible values for the switch condition. @@ -3176,14 +3174,12 @@ void ExprEngine::processSwitch(SwitchNodeBuilder& builder) { // Note that this isn't as accurate as it could be. Even if there isn't // a case for a particular enum value as long as that enum value isn't // feasible then it shouldn't be considered for making 'default:' reachable. - const SwitchStmt *SS = builder.getSwitch(); - const Expr *CondExpr = SS->getCond()->IgnoreParenImpCasts(); - if (CondExpr->getType()->isEnumeralType()) { - if (SS->isAllEnumCasesCovered()) + if (Condition->IgnoreParenImpCasts()->getType()->isEnumeralType()) { + if (Switch->isAllEnumCasesCovered()) return; } - builder.generateDefaultCaseNode(DefaultSt); + Builder.generateDefaultCaseNode(State); } //===----------------------------------------------------------------------===// diff --git a/clang/lib/StaticAnalyzer/Core/ProgramState.cpp b/clang/lib/StaticAnalyzer/Core/ProgramState.cpp index c4790b0284281..6932714bb6be7 100644 --- a/clang/lib/StaticAnalyzer/Core/ProgramState.cpp +++ b/clang/lib/StaticAnalyzer/Core/ProgramState.cpp @@ -308,7 +308,7 @@ ProgramStateRef ProgramState::BindExpr(const Stmt *S, return this; ProgramState NewSt = *this; - NewSt.Env = NewEnv; + NewSt.Env = std::move(NewEnv); return getStateManager().getPersistentState(NewSt); } diff --git a/clang/lib/StaticAnalyzer/Core/RegionStore.cpp b/clang/lib/StaticAnalyzer/Core/RegionStore.cpp index 4f4824a3616ce..6ec66298e8c45 100644 --- a/clang/lib/StaticAnalyzer/Core/RegionStore.cpp +++ b/clang/lib/StaticAnalyzer/Core/RegionStore.cpp @@ -2566,6 +2566,14 @@ RegionStoreManager::setImplicitDefaultValue(LimitedRegionBindingsConstRef B, if (B.hasExhaustedBindingLimit()) return B; + // Prefer to keep the previous default binding if we had one; that is likely a + // better choice than setting some arbitrary new default value. + // This isn't ideal (more of a hack), but better than dropping the more + // accurate default binding. + if (B.getDefaultBinding(R).has_value()) { + return B; + } + SVal V; if (Loc::isLocType(T)) @@ -2659,12 +2667,9 @@ RegionStoreManager::bindArray(LimitedRegionBindingsConstRef B, return bindAggregate(B, R, Init); } - if (isa(Init)) + if (isa(Init)) return bindAggregate(B, R, Init); - if (Init.isUnknown()) - return bindAggregate(B, R, UnknownVal()); - // Remaining case: explicit compound values. const nonloc::CompoundVal& CV = Init.castAs(); nonloc::CompoundVal::iterator VI = CV.begin(), VE = CV.end(); diff --git a/clang/lib/Tooling/DependencyScanningTool.cpp b/clang/lib/Tooling/DependencyScanningTool.cpp index 9f27cb59b9cc8..cc4c88fc42f5a 100644 --- a/clang/lib/Tooling/DependencyScanningTool.cpp +++ b/clang/lib/Tooling/DependencyScanningTool.cpp @@ -220,7 +220,7 @@ std::optional DependencyScanningTool::getP1689ModuleDependencyFile( Rule.Provides = Provided; if (Rule.Provides) Rule.Provides->SourcePath = Filename.str(); - Rule.Requires = Requires; + Rule.Requires = std::move(Requires); } StringRef getMakeFormatDependencyOutputPath() { diff --git a/clang/test/AST/ByteCode/builtin-functions.cpp b/clang/test/AST/ByteCode/builtin-functions.cpp index b2f0213cfea05..10f7ff294ae00 100644 --- a/clang/test/AST/ByteCode/builtin-functions.cpp +++ b/clang/test/AST/ByteCode/builtin-functions.cpp @@ -841,6 +841,7 @@ namespace bswap { int h7 = __builtin_bswapg(0x1234) == 0x3412 ? 1 : f(); int h8 = __builtin_bswapg(0x00001234) == 0x34120000 ? 1 : f(); int h9 = __builtin_bswapg(0x0000000000001234) == 0x3412000000000000 ? 1 : f(); + int h9a = __builtin_bswapg(true) == true ? 1 : f(); #ifndef __AVR__ int h10 = __builtin_bswapg((_BitInt(8))0x12) == (_BitInt(8))0x12 ? 1 : f(); int h11 = __builtin_bswapg((_BitInt(16))0x1234) == (_BitInt(16))0x3412 ? 1 : f(); diff --git a/clang/test/AST/ByteCode/builtin-object-size-codegen.c b/clang/test/AST/ByteCode/builtin-object-size-codegen.c new file mode 100644 index 0000000000000..6aa0485bd65ad --- /dev/null +++ b/clang/test/AST/ByteCode/builtin-object-size-codegen.c @@ -0,0 +1,41 @@ +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -triple x86_64-apple-darwin -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s | FileCheck %s + + +#define PS(N) __attribute__((pass_object_size(N))) + int ObjectSize0(void *const p PS(0)) { + return __builtin_object_size(p, 0); + } + + int ObjectSize1(void *const p PS(1)) { + return __builtin_object_size(p, 1); + } + + int ObjectSize2(void *const p PS(2)) { + return __builtin_object_size(p, 2); + } + + int ObjectSize3(void *const p PS(3)) { + return __builtin_object_size(p, 3); + } + + struct Foo { + int t[10]; + }; + + + int gi; + void test1(unsigned long sz) { + struct Foo t[10]; + + // CHECK: call i32 @ObjectSize0(ptr noundef %{{.*}}, i64 noundef 360) + gi = ObjectSize0(&t[1]); + // call i32 @ObjectSize1(ptr noundef %{{.*}}, i64 noundef 360) + // gi = ObjectSize2(&t[1]); + // gi = ObjectSize2(&t[1].t[1]); + } + +/// Used to crash due to the void-typed ArraySubscriptExpr. +void foo(void *p) { + int i = __builtin_object_size(&p[2], 3); +} diff --git a/clang/test/AST/ByteCode/builtin-object-size-codegen.cpp b/clang/test/AST/ByteCode/builtin-object-size-codegen.cpp index c466c815e230a..a8071764219c5 100644 --- a/clang/test/AST/ByteCode/builtin-object-size-codegen.cpp +++ b/clang/test/AST/ByteCode/builtin-object-size-codegen.cpp @@ -15,6 +15,10 @@ void foo() { gi = __builtin_object_size(&c->bs[0], 2); // CHECK: store i32 16 gi = __builtin_object_size(&c->bs[0], 3); + + C c2{}; + // CHECK: store i32 16 + gi = __builtin_object_size(&c2.bs[0], 1); } @@ -102,3 +106,19 @@ void test3() { gi = __builtin_object_size((B*)&c, 3); } + +struct A { char buf[16]; }; +struct B : A {}; +struct C { int i; B bs[1]; } *c; +void globalPointer() { + int gi; + // CHECK: call i64 @llvm.objectsize.i64.p0(ptr %{{.*}}, i1 true, i1 true, i1 false) + gi = __builtin_object_size(&c->bs[0], 2); +} + +void nonPtrParam(C c) { + int gi; + // CHECK: store i32 16 + gi = __builtin_object_size(&c.bs[0], 2); +} + diff --git a/clang/test/AST/ByteCode/builtins.c b/clang/test/AST/ByteCode/builtins.c index 684db52296fc2..5630a36e1c05b 100644 --- a/clang/test/AST/ByteCode/builtins.c +++ b/clang/test/AST/ByteCode/builtins.c @@ -1,8 +1,5 @@ -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter %s -verify -// RUN: %clang_cc1 %s -verify=ref - -// expected-no-diagnostics -// ref-no-diagnostics +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter %s -verify=expected,both +// RUN: %clang_cc1 %s -verify=ref,both extern __SIZE_TYPE__ strlen(const char *); @@ -19,3 +16,6 @@ int structStrlen(void) { void f() { __builtin_memcpy(f, f, 1); } void f2() { __builtin_memchr(f2, 0, 1); } + + +_Static_assert(__atomic_is_lock_free(4, (void*)2), ""); // both-error {{not an integral constant expression}} diff --git a/clang/test/AST/ByteCode/c.c b/clang/test/AST/ByteCode/c.c index 7b98aa84a482c..9496f8060884a 100644 --- a/clang/test/AST/ByteCode/c.c +++ b/clang/test/AST/ByteCode/c.c @@ -425,3 +425,11 @@ int complexMul[2 * (22222222222wb + 2i) == 2]; // all-warning {{'_BitInt' suffix int complexDiv[2 / (22222222222wb + 2i) == 2]; // all-warning {{'_BitInt' suffix for literals is a C23 extension}} \ // pedantic-warning {{imaginary constants are a C2y extension}} \ // all-warning {{variable length array folded to constant array as an extension}} + + + +int i = 0; +void intPtrCmp1(void) { &i + 1 == 2; } // all-warning {{comparison between pointer and integer}} \ + // all-warning {{equality comparison result unused}} +void intPtrCmp2(void) { 2 == &i + 1; } // all-warning {{comparison between pointer and integer}} \ + // all-warning {{equality comparison result unused}} diff --git a/clang/test/AST/ByteCode/complex.cpp b/clang/test/AST/ByteCode/complex.cpp index 9bf000d65466c..68a8e78d5b25b 100644 --- a/clang/test/AST/ByteCode/complex.cpp +++ b/clang/test/AST/ByteCode/complex.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify=both,expected -Wno-unused-value %s -// RUN: %clang_cc1 -verify=both,ref -Wno-unused-value %s +// RUN: %clang_cc1 -verify=both,ref -Wno-unused-value %s constexpr _Complex double z1 = {1.0, 2.0}; static_assert(__real(z1) == 1.0, ""); @@ -131,6 +131,11 @@ static_assert(ignored() == 0, ""); static_assert((int)I1 == 1, ""); static_assert((float)D == 1.0f, ""); + +void ignoredEmitFloat() { + (1.f / (2.f + 3i), 4.f); +} + static_assert(__real((_Complex unsigned)5) == 5); static_assert(__imag((_Complex unsigned)5) == 0); diff --git a/clang/test/AST/ByteCode/constexpr-steps.cpp b/clang/test/AST/ByteCode/constexpr-steps.cpp new file mode 100644 index 0000000000000..490425107a140 --- /dev/null +++ b/clang/test/AST/ByteCode/constexpr-steps.cpp @@ -0,0 +1,10 @@ +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify %s -fconstexpr-steps=100 + + +constexpr int foo() { // expected-error {{never produces a constant expression}} + while (1) {} // expected-note 2{{constexpr evaluation hit maximum step limit}} + return 0; +} +static_assert (foo() == 0, ""); // expected-error {{not an integral constant expression}} \ + // expected-note {{in call to}} + diff --git a/clang/test/AST/ByteCode/cxx20.cpp b/clang/test/AST/ByteCode/cxx20.cpp index 2abe8dd120e6f..139b6c873adce 100644 --- a/clang/test/AST/ByteCode/cxx20.cpp +++ b/clang/test/AST/ByteCode/cxx20.cpp @@ -785,6 +785,30 @@ namespace APValues { constexpr const A &w = get; } +namespace InitFromAPValues { + template struct S { + static constexpr auto &ref = a; + }; + + union U1 { int x, y; }; + static_assert(S::ref.x == 1); + static_assert(S::ref.y == 1); // both-error {{static assertion expression is not an integral constant expression}} \ + // both-note {{read of member 'y' of union with active member 'x' is not allowed in a constant expression}} + + union U2 { + bool x; + constexpr U2() {} + }; + static_assert(S::ref.x); // both-error {{static assertion expression is not an integral constant expression}} \ + // both-note {{read of member 'x' of union with no active member is not allowed in a constant expression}} + + union U3 { + struct S { int x; }; + S s; + }; + static_assert(S::ref.s.x == 2); +} + namespace self_referencing { struct S { S* ptr = nullptr; diff --git a/clang/test/AST/ByteCode/floats.cpp b/clang/test/AST/ByteCode/floats.cpp index 7da4bf884e3e3..db5e491ccdf2b 100644 --- a/clang/test/AST/ByteCode/floats.cpp +++ b/clang/test/AST/ByteCode/floats.cpp @@ -1,13 +1,12 @@ -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify %s -// RUN: %clang_cc1 -verify=ref %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify=expected,both %s +// RUN: %clang_cc1 -verify=ref,both %s constexpr void assert(bool C) { if (C) return; // Invalid in constexpr. - (void)(1 / 0); // expected-warning {{undefined}} \ - // ref-warning {{undefined}} + (void)(1 / 0); // both-warning {{undefined}} } constexpr int i = 2; @@ -31,17 +30,13 @@ static_assert(10.0f * false == 0, ""); constexpr float floats[] = {1.0f, 2.0f, 3.0f, 4.0f}; -constexpr float m = 5.0f / 0.0f; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{division by zero}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{division by zero}} +constexpr float m = 5.0f / 0.0f; // both-error {{must be initialized by a constant expression}} \ + // both-note {{division by zero}} -static_assert(~2.0f == 3, ""); // ref-error {{invalid argument type 'float' to unary expression}} \ - // expected-error {{invalid argument type 'float' to unary expression}} +static_assert(~2.0f == 3, ""); // both-error {{invalid argument type 'float' to unary expression}} -typedef int tdb[(long long)4e20]; //expected-error {{variable length}} \ - //ref-error {{variable length}} +typedef int tdb[(long long)4e20]; //both-error {{variable length}} /// Initialized by a double. constexpr float df = 0.0; @@ -63,10 +58,8 @@ constexpr float fa[] = {1.0f, 2.0, 1, false}; constexpr double da[] = {1.0f, 2.0, 1, false}; constexpr float fm = __FLT_MAX__; -constexpr int someInt = fm; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{is outside the range of representable values}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{is outside the range of representable values}} +constexpr int someInt = fm; // both-error {{must be initialized by a constant expression}} \ + // both-note {{is outside the range of representable values}} namespace compound { constexpr float f1() { @@ -99,8 +92,7 @@ namespace compound { // write to a[1]; a[i++] += ++i; #if __cplusplus <= 201402L - // expected-warning@-2 {{multiple unsequenced modifications}} \ - // ref-warning@-2 {{multiple unsequenced modifications}} + // both-warning@-2 {{multiple unsequenced modifications}} #endif return a[1]; @@ -214,28 +206,20 @@ namespace nan { constexpr double nan = __builtin_nan(""); static_assert(nan); - constexpr double D1 = 1 + nan; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{produces a NaN}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{produces a NaN}} + constexpr double D1 = 1 + nan; // both-error {{must be initialized by a constant expression}} \ + // both-note {{produces a NaN}} - constexpr double D2 = __builtin_inf() / __builtin_inf(); // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{produces a NaN}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{produces a NaN}} + constexpr double D2 = __builtin_inf() / __builtin_inf(); // both-error {{must be initialized by a constant expression}} \ + // both-note {{produces a NaN}} } #ifdef __SIZEOF_INT128__ namespace ConvertToIntOverflow { // should not crash - enum { E = (__uint128_t)-1. }; // ref-error {{expression is not an integral constant expression}} \ - // ref-note {{outside the range of representable values of type}} \ - // expected-error {{expression is not an integral constant expression}} \ - // expected-note {{outside the range of representable values of type}} - - enum { F = (__int128)(3.0e38) }; // ref-error {{expression is not an integral constant expression}} \ - // ref-note {{outside the range of representable values of type}} \ - // expected-error {{expression is not an integral constant expression}} \ - // expected-note {{outside the range of representable values of type}} + enum { E = (__uint128_t)-1. }; // both-error {{expression is not an integral constant expression}} \ + // both-note {{outside the range of representable values of type}} + + enum { F = (__int128)(3.0e38) }; // both-error {{expression is not an integral constant expression}} \ + // both-note {{outside the range of representable values of type}} } #endif diff --git a/clang/test/AST/ByteCode/gh176549.cpp b/clang/test/AST/ByteCode/gh176549.cpp new file mode 100644 index 0000000000000..42d055e9608c7 --- /dev/null +++ b/clang/test/AST/ByteCode/gh176549.cpp @@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify %s + +const char a[4] = "abc"; +void foo() { + int i = 0; + i = 1 > (a + 1, sizeof(a)); // expected-warning {{left operand of comma operator has no effect}} +} diff --git a/clang/test/AST/ByteCode/invalid.cpp b/clang/test/AST/ByteCode/invalid.cpp index bfb33d0cc6dce..c8298fa2c2b9b 100644 --- a/clang/test/AST/ByteCode/invalid.cpp +++ b/clang/test/AST/ByteCode/invalid.cpp @@ -57,6 +57,12 @@ namespace Casts { /// Just make sure this doesn't crash. float PR9558 = reinterpret_cast("asd"); + + /// Ensure we don't crash when trying to dereference a cast pointer where the + /// target type is larger than the source allocation (GH#179015). + void GH179015() { + *(int **)""; // both-warning {{expression result unused}} + } } @@ -137,3 +143,11 @@ namespace BitCastWithErrors { template int f(); // both-note {{candidate template ignored}} static union { char *x = f(); }; // both-error {{no matching function for call to 'f'}} } + +namespace NullRecord { + struct S1; // both-note {{forward declaration}} + struct S2 { + S1 s[2]; // both-error {{field has incomplete type 'S1'}} + }; + S2 s = S2(); +} diff --git a/clang/test/AST/ByteCode/object-size-flex-array.c b/clang/test/AST/ByteCode/object-size-flex-array.c new file mode 100644 index 0000000000000..4f2a476209985 --- /dev/null +++ b/clang/test/AST/ByteCode/object-size-flex-array.c @@ -0,0 +1,156 @@ +// RUN: %clang -fexperimental-new-constant-interpreter -target x86_64 -O2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefixes=CHECK,CHECK-NO-STRICT %s +// RUN: %clang -fexperimental-new-constant-interpreter -fstrict-flex-arrays=0 -target x86_64 -O2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefixes=CHECK,CHECK-STRICT-0 %s +// RUN: %clang -fexperimental-new-constant-interpreter -fstrict-flex-arrays=1 -target x86_64 -O2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefixes=CHECK,CHECK-STRICT-1 %s +// RUN: %clang -fexperimental-new-constant-interpreter -fstrict-flex-arrays=2 -target x86_64 -O2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefixes=CHECK,CHECK-STRICT-2 %s +// RUN: %clang -fexperimental-new-constant-interpreter -fstrict-flex-arrays=3 -target x86_64 -O2 -S -emit-llvm %s -o - 2>&1 | FileCheck --check-prefixes=CHECK,CHECK-STRICT-3 %s + +#define OBJECT_SIZE_BUILTIN __builtin_object_size + +typedef struct { + float f; + double c[]; +} foo_t; + +typedef struct { + float f; + double c[0]; +} foo0_t; + +typedef struct { + float f; + double c[1]; +} foo1_t; + +typedef struct { + float f; + double c[2]; +} foo2_t; + +// CHECK-LABEL: @bar( +unsigned bar(foo_t *f) { + // CHECK-NO-STRICT: ret i32 -1 + // CHECK-STRICT-0: ret i32 -1 + // CHECK-STRICT-1: ret i32 -1 + // CHECK-STRICT-2: ret i32 -1 + // CHECK-STRICT-3: ret i32 -1 + return OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// CHECK-LABEL: @bar0( +unsigned bar0(foo0_t *f) { + // CHECK-NO-STRICT: ret i32 -1 + // CHECK-STRICT-0: ret i32 -1 + // CHECK-STRICT-1: ret i32 -1 + // CHECK-STRICT-2: ret i32 -1 + // CHECK-STRICT-3: ret i32 0 + return OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// CHECK-LABEL: @bar1( +unsigned bar1(foo1_t *f) { + // CHECK-NO-STRICT: ret i32 -1 + // CHECK-STRICT-0: ret i32 -1 + // CHECK-STRICT-1: ret i32 -1 + // CHECK-STRICT-2: ret i32 8 + // CHECK-STRICT-3: ret i32 8 + return OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// CHECK-LABEL: @bar2( +unsigned bar2(foo2_t *f) { + // CHECK-NO-STRICT: ret i32 -1 + // CHECK-STRICT-0: ret i32 -1 + // CHECK-STRICT-1: ret i32 16 + // CHECK-STRICT-2: ret i32 16 + // CHECK-STRICT-3: ret i32 16 + return OBJECT_SIZE_BUILTIN(f->c, 1); +} + +#define DYNAMIC_OBJECT_SIZE_BUILTIN __builtin_dynamic_object_size + +// CHECK-LABEL: @dyn_bar( +unsigned dyn_bar(foo_t *f) { + // CHECK-NO-STRICT: ret i32 -1 + // CHECK-STRICT-0: ret i32 -1 + // CHECK-STRICT-1: ret i32 -1 + // CHECK-STRICT-2: ret i32 -1 + // CHECK-STRICT-3: ret i32 -1 + return DYNAMIC_OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// CHECK-LABEL: @dyn_bar0( +unsigned dyn_bar0(foo0_t *f) { + // CHECK-NO-STRICT: ret i32 -1 + // CHECK-STRICT-0: ret i32 -1 + // CHECK-STRICT-1: ret i32 -1 + // CHECK-STRICT-2: ret i32 -1 + // CHECK-STRICT-3: ret i32 0 + return DYNAMIC_OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// CHECK-LABEL: @dyn_bar1( +unsigned dyn_bar1(foo1_t *f) { + // CHECK-NO-STRICT: ret i32 -1 + // CHECK-STRICT-0: ret i32 -1 + // CHECK-STRICT-1: ret i32 -1 + // CHECK-STRICT-2: ret i32 8 + // CHECK-STRICT-3: ret i32 8 + return DYNAMIC_OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// CHECK-LABEL: @dyn_bar2( +unsigned dyn_bar2(foo2_t *f) { + // CHECK-NO-STRICT: ret i32 -1 + // CHECK-STRICT-0: ret i32 -1 + // CHECK-STRICT-1: ret i32 16 + // CHECK-STRICT-2: ret i32 16 + // CHECK-STRICT-3: ret i32 16 + return DYNAMIC_OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// Also checks for non-trailing flex-array like members + +typedef struct { + double c[0]; + float f; +} foofoo0_t; + +typedef struct { + double c[1]; + float f; +} foofoo1_t; + +typedef struct { + double c[2]; + float f; +} foofoo2_t; + +// CHECK-LABEL: @babar0( +unsigned babar0(foofoo0_t *f) { + // CHECK-NO-STRICT: ret i32 0 + // CHECK-STRICT-0: ret i32 0 + // CHECK-STRICT-1: ret i32 0 + // CHECK-STRICT-2: ret i32 0 + // CHECK-STRICT-3: ret i32 0 + return OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// CHECK-LABEL: @babar1( +unsigned babar1(foofoo1_t *f) { + // CHECK-NO-STRICT: ret i32 8 + // CHECK-STRICT-0: ret i32 8 + // CHECK-STRICT-1: ret i32 8 + // CHECK-STRICT-2: ret i32 8 + // CHECK-STRICT-3: ret i32 8 + return OBJECT_SIZE_BUILTIN(f->c, 1); +} + +// CHECK-LABEL: @babar2( +unsigned babar2(foofoo2_t *f) { + // CHECK-NO-STRICT: ret i32 16 + // CHECK-STRICT-0: ret i32 16 + // CHECK-STRICT-1: ret i32 16 + // CHECK-STRICT-2: ret i32 16 + // CHECK-STRICT-3: ret i32 16 + return OBJECT_SIZE_BUILTIN(f->c, 1); +} diff --git a/clang/test/AST/ByteCode/pass-object-size.c b/clang/test/AST/ByteCode/pass-object-size.c new file mode 100644 index 0000000000000..d8ea5e9d3160c --- /dev/null +++ b/clang/test/AST/ByteCode/pass-object-size.c @@ -0,0 +1,103 @@ +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -triple x86_64-apple-darwin -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - %s | FileCheck %s + +/// This is the part of test/CodeGen/pass-object-size.c we can evaluate. + +typedef unsigned long size_t; + +struct Foo { + int t[10]; +}; + +#define PS(N) __attribute__((pass_object_size(N))) +#define PDS(N) __attribute__((pass_dynamic_object_size(N))) + +int gi = 0; + +// CHECK-LABEL: define{{.*}} i32 @ObjectSize0(ptr noundef %{{.*}}, i64 noundef %0) +int ObjectSize0(void *const p PS(0)) { + // CHECK-NOT: @llvm.objectsize + return __builtin_object_size(p, 0); +} + +// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize0(ptr noundef %{{.*}}, i64 noundef %0) +int DynamicObjectSize0(void *const p PDS(0)) { + // CHECK-NOT: @llvm.objectsize + return __builtin_dynamic_object_size(p, 0); +} + +// CHECK-LABEL: define{{.*}} i32 @ObjectSize1(ptr noundef %{{.*}}, i64 noundef %0) +int ObjectSize1(void *const p PS(1)) { + // CHECK-NOT: @llvm.objectsize + return __builtin_object_size(p, 1); +} + +// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize1(ptr noundef %{{.*}}, i64 noundef %0) +int DynamicObjectSize1(void *const p PDS(1)) { + // CHECK-NOT: @llvm.objectsize + return __builtin_dynamic_object_size(p, 1); +} + +// CHECK-LABEL: define{{.*}} i32 @ObjectSize2(ptr noundef %{{.*}}, i64 noundef %0) +int ObjectSize2(void *const p PS(2)) { + // CHECK-NOT: @llvm.objectsize + return __builtin_object_size(p, 2); +} + +// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize2(ptr noundef %{{.*}}, i64 noundef %0) +int DynamicObjectSize2(void *const p PDS(2)) { + // CHECK-NOT: @llvm.objectsize + return __builtin_object_size(p, 2); +} + +// CHECK-LABEL: define{{.*}} i32 @ObjectSize3(ptr noundef %{{.*}}, i64 noundef %0) +int ObjectSize3(void *const p PS(3)) { + // CHECK-NOT: @llvm.objectsize + return __builtin_object_size(p, 3); +} + +// CHECK-LABEL: define{{.*}} i32 @DynamicObjectSize3(ptr noundef %{{.*}}, i64 noundef %0) +int DynamicObjectSize3(void *const p PDS(3)) { + // CHECK-NOT: @llvm.objectsize + return __builtin_object_size(p, 3); +} + +void *malloc(unsigned long) __attribute__((alloc_size(1))); + +// CHECK-LABEL: define{{.*}} void @test1 +void test1(unsigned long sz) { + struct Foo t[10]; + + // CHECK: call i32 @ObjectSize0(ptr noundef %{{.*}}, i64 noundef 360) + gi = ObjectSize0(&t[1]); + // CHECK: call i32 @ObjectSize1(ptr noundef %{{.*}}, i64 noundef 360) + gi = ObjectSize1(&t[1]); + // CHECK: call i32 @ObjectSize2(ptr noundef %{{.*}}, i64 noundef 360) + gi = ObjectSize2(&t[1]); + // CHECK: call i32 @ObjectSize3(ptr noundef %{{.*}}, i64 noundef 360) + gi = ObjectSize3(&t[1]); + + // CHECK: call i32 @ObjectSize0(ptr noundef %{{.*}}, i64 noundef 356) + gi = ObjectSize0(&t[1].t[1]); + // CHECK: call i32 @ObjectSize1(ptr noundef %{{.*}}, i64 noundef 36) + gi = ObjectSize1(&t[1].t[1]); + // CHECK: call i32 @ObjectSize2(ptr noundef %{{.*}}, i64 noundef 356) + gi = ObjectSize2(&t[1].t[1]); + // CHECK: call i32 @ObjectSize3(ptr noundef %{{.*}}, i64 noundef 36) + gi = ObjectSize3(&t[1].t[1]); + + char *ptr = (char *)malloc(sz); + + // CHECK: [[REG:%.*]] = call i64 @llvm.objectsize.i64.p0({{.*}}, i1 false, i1 true, i1 true) + // CHECK: call i32 @DynamicObjectSize0(ptr noundef %{{.*}}, i64 noundef [[REG]]) + gi = DynamicObjectSize0(ptr); + + // CHECK: [[WITH_OFFSET:%.*]] = getelementptr + // CHECK: [[REG:%.*]] = call i64 @llvm.objectsize.i64.p0(ptr [[WITH_OFFSET]], i1 false, i1 true, i1 true) + // CHECK: call i32 @DynamicObjectSize0(ptr noundef {{.*}}, i64 noundef [[REG]]) + gi = DynamicObjectSize0(ptr+10); + + // CHECK: [[REG:%.*]] = call i64 @llvm.objectsize.i64.p0({{.*}}, i1 true, i1 true, i1 true) + // CHECK: call i32 @DynamicObjectSize2(ptr noundef {{.*}}, i64 noundef [[REG]]) + gi = DynamicObjectSize2(ptr); +} diff --git a/clang/test/AST/ByteCode/placement-new.cpp b/clang/test/AST/ByteCode/placement-new.cpp index f458ea17b6cc6..503e456565f5d 100644 --- a/clang/test/AST/ByteCode/placement-new.cpp +++ b/clang/test/AST/ByteCode/placement-new.cpp @@ -522,3 +522,5 @@ constexpr int intDestArray() { static_assert(intDestArray() == 0); // both-error {{not an integral constant expression}} \ // both-note {{in call to}} +constexpr void invalidDest() { new (undefinedfunction()) int; } // both-error {{use of undeclared identifier 'undefinedfunction'}} +static_assert((invalidDest(), true)); // both-error {{not an integral constant expression}} diff --git a/clang/test/AST/ByteCode/records.cpp b/clang/test/AST/ByteCode/records.cpp index 4799ebe25dde1..804b4c6ea466a 100644 --- a/clang/test/AST/ByteCode/records.cpp +++ b/clang/test/AST/ByteCode/records.cpp @@ -602,6 +602,15 @@ namespace Destructors { } static_assert(testS() == 1); // both-error {{not an integral constant expression}} \ // both-note {{in call to 'testS()'}} + + struct A { int n; }; + constexpr void double_destroy() { + A a; + a.~A(); + a.~A(); // both-note {{destruction of object outside its lifetime}} + } + static_assert((double_destroy(), true)); // both-error {{not an integral constant expression}} \ + // both-note {{in call to}} } namespace BaseToDerived { diff --git a/clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl b/clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl index 619b12a278b10..e9e7cd76167a5 100644 --- a/clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl +++ b/clang/test/AST/HLSL/ByteAddressBuffers-AST.hlsl @@ -4,7 +4,7 @@ // // RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-library -x hlsl -ast-dump \ // RUN: -DRESOURCE=ByteAddressBuffer %s | FileCheck -DRESOURCE=ByteAddressBuffer \ -// RUN: -check-prefixes=CHECK,CHECK-SRV,CHECK-NOSUBSCRIPT %s +// RUN: -check-prefixes=CHECK,CHECK-SRV,CHECK-NOSUBSCRIPT,CHECK-LOAD %s // // RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-library -x hlsl -ast-dump -DEMPTY \ // RUN: -DRESOURCE=RWByteAddressBuffer %s | FileCheck -DRESOURCE=RWByteAddressBuffer \ @@ -12,7 +12,7 @@ // // RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-library -x hlsl -ast-dump \ // RUN: -DRESOURCE=RWByteAddressBuffer %s | FileCheck -DRESOURCE=RWByteAddressBuffer \ -// RUN: -check-prefixes=CHECK,CHECK-UAV,CHECK-NOSUBSCRIPT %s +// RUN: -check-prefixes=CHECK,CHECK-UAV,CHECK-NOSUBSCRIPT,CHECK-LOAD,CHECK-STORE %s // // RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-library -x hlsl -ast-dump -DEMPTY \ // RUN: -DRESOURCE=RasterizerOrderedByteAddressBuffer %s | FileCheck -DRESOURCE=RasterizerOrderedByteAddressBuffer \ @@ -152,9 +152,270 @@ RESOURCE Buffer; // CHECK-NEXT: DeclRefExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue Var {{.*}} 'tmp' 'hlsl::[[RESOURCE]]' // CHECK-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline +// Load methods + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load 'unsigned int (unsigned int)' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: UnaryOperator {{.*}} 'hlsl_device unsigned int' lvalue prefix '*' cannot overflow +// CHECK-LOAD-NEXT: CallExpr {{.*}} 'hlsl_device unsigned int *' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'unsigned int *' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load 'unsigned int (unsigned int, out unsigned int) +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Status 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: HLSLParamModifierAttr {{.*}} out +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: CallExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_load_with_status_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Status' 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'unsigned int *' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load2 'vector' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: UnaryOperator {{.*}} 'vector' lvalue prefix '*' cannot overflow +// CHECK-LOAD-NEXT: CallExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load2 'vector' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Status 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: HLSLParamModifierAttr {{.*}} out +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: CallExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_load_with_status_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Status' 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load3 'vector' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: UnaryOperator {{.*}} 'vector' lvalue prefix '*' cannot overflow +// CHECK-LOAD-NEXT: CallExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load3 'vector' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Status 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: HLSLParamModifierAttr {{.*}} out +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: CallExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_load_with_status_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Status' 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load4 'vector' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: UnaryOperator {{.*}} 'vector' lvalue prefix '*' cannot overflow +// CHECK-LOAD-NEXT: CallExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load4 'vector' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Status 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: HLSLParamModifierAttr {{.*}} out +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: CallExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_load_with_status_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Status' 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load 'element_type (unsigned int)' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow +// CHECK-LOAD-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' +// CHECK-LOAD-NEXT: CallExpr {{.*}} '' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'element_type *' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-LOAD: CXXMethodDecl {{.*}} Load 'element_type (unsigned int, out unsigned int) +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Status 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: HLSLParamModifierAttr {{.*}} out +// CHECK-LOAD-NEXT: CompoundStmt +// CHECK-LOAD-NEXT: ReturnStmt +// CHECK-LOAD-NEXT: CStyleCastExpr {{.*}} 'element_type' +// CHECK-LOAD-NEXT: CallExpr {{.*}} '' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_load_with_status_typed' 'void (...) noexcept' +// CHECK-LOAD-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-LOAD-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-LOAD-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Status' 'unsigned int &__restrict' +// CHECK-LOAD-NEXT: CXXScalarValueInitExpr {{.*}} 'element_type *' +// CHECK-LOAD-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// Store method +// CHECK-STORE: CXXMethodDecl {{.*}} Store 'void (unsigned int, unsigned int)' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Value 'unsigned int' +// CHECK-STORE-NEXT: CompoundStmt +// CHECK-STORE-NEXT: BinaryOperator {{.*}} 'hlsl_device unsigned int' '=' +// CHECK-STORE-NEXT: UnaryOperator {{.*}} 'hlsl_device unsigned int' lvalue prefix '*' cannot overflow +// CHECK-STORE-NEXT: CallExpr {{.*}} 'hlsl_device unsigned int *' +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-STORE-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-STORE-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-STORE-NEXT: CXXScalarValueInitExpr {{.*}} 'unsigned int *' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Value' 'unsigned int' +// CHECK-STORE-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-STORE: CXXMethodDecl {{.*}} Store2 'void (unsigned int, vector)' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Value 'vector' +// CHECK-STORE-NEXT: CompoundStmt +// CHECK-STORE-NEXT: BinaryOperator {{.*}} 'vector' '=' +// CHECK-STORE-NEXT: UnaryOperator {{.*}} 'vector' lvalue prefix '*' cannot overflow +// CHECK-STORE-NEXT: CallExpr {{.*}} 'vector' +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-STORE-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-STORE-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-STORE-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'vector' lvalue ParmVar {{.*}} 'Value' 'vector' +// CHECK-STORE-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-STORE: CXXMethodDecl {{.*}} Store3 'void (unsigned int, vector)' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Value 'vector' +// CHECK-STORE-NEXT: CompoundStmt +// CHECK-STORE-NEXT: BinaryOperator {{.*}} 'vector' '=' +// CHECK-STORE-NEXT: UnaryOperator {{.*}} 'vector' lvalue prefix '*' cannot overflow +// CHECK-STORE-NEXT: CallExpr {{.*}} 'vector' +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-STORE-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-STORE-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-STORE-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'vector' lvalue ParmVar {{.*}} 'Value' 'vector' +// CHECK-STORE-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-STORE: CXXMethodDecl {{.*}} Store4 'void (unsigned int, vector)' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Value 'vector' +// CHECK-STORE-NEXT: CompoundStmt +// CHECK-STORE-NEXT: BinaryOperator {{.*}} 'vector' '=' +// CHECK-STORE-NEXT: UnaryOperator {{.*}} 'vector' lvalue prefix '*' cannot overflow +// CHECK-STORE-NEXT: CallExpr {{.*}} 'vector' +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} 'void (*)(...) noexcept' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} '__hlsl_resource_t {{.*}}' +// CHECK-STORE-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-STORE-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-STORE-NEXT: ImplicitCastExpr {{.*}} 'unsigned int' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-STORE-NEXT: CXXScalarValueInitExpr {{.*}} 'vector' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'vector' lvalue ParmVar {{.*}} 'Value' 'vector' +// CHECK-STORE-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + +// CHECK-STORE: CXXMethodDecl {{.*}} Store 'void (unsigned int, element_type)' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' +// CHECK-STORE-NEXT: ParmVarDecl {{.*}} Value 'element_type' +// CHECK-STORE-NEXT: CompoundStmt +// CHECK-STORE-NEXT: BinaryOperator {{.*}} 'hlsl_device element_type' '=' +// CHECK-STORE-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow +// CHECK-STORE-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' +// CHECK-STORE-NEXT: CallExpr {{.*}} '' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer_typed' 'void (...) noexcept' +// CHECK-STORE-NEXT: MemberExpr {{.*}} '__hlsl_resource_t {{.*}}' lvalue .__handle +// CHECK-STORE-NEXT: CXXThisExpr {{.*}} 'hlsl::[[RESOURCE]]' lvalue implicit this +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'unsigned int' lvalue ParmVar {{.*}} 'Index' 'unsigned int' +// CHECK-STORE-NEXT: CXXScalarValueInitExpr {{.*}} 'element_type *' +// CHECK-STORE-NEXT: DeclRefExpr {{.*}} 'element_type' lvalue ParmVar {{.*}} 'Value' 'element_type' +// CHECK-STORE-NEXT: AlwaysInlineAttr {{.*}} Implicit always_inline + // GetDimensions method -// CHECK-NEXT: CXXMethodDecl {{.*}} GetDimensions 'void (out unsigned int)' +// CHECK: CXXMethodDecl {{.*}} GetDimensions 'void (out unsigned int)' // CHECK-NEXT: ParmVarDecl {{.*}} dim 'unsigned int &__restrict' // CHECK-NEXT: HLSLParamModifierAttr {{.*}} out // CHECK-NEXT: CompoundStmt diff --git a/clang/test/AST/HLSL/StructuredBuffers-AST.hlsl b/clang/test/AST/HLSL/StructuredBuffers-AST.hlsl index 2bcca4854b136..c6411ccf77075 100644 --- a/clang/test/AST/HLSL/StructuredBuffers-AST.hlsl +++ b/clang/test/AST/HLSL/StructuredBuffers-AST.hlsl @@ -275,7 +275,7 @@ RESOURCE Buffer; // CHECK-SUBSCRIPT-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' // CHECK-SUBSCRIPT-NEXT: CompoundStmt // CHECK-SUBSCRIPT-NEXT: ReturnStmt -// CHECK-SUBSCRIPT-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' prefix '*' cannot overflow +// CHECK-SUBSCRIPT-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow // CHECK-SUBSCRIPT-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' // CHECK-SUBSCRIPT-NEXT: CallExpr // CHECK-SUBSCRIPT-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer' 'void (...) noexcept' @@ -292,7 +292,7 @@ RESOURCE Buffer; // CHECK-SUBSCRIPT-UAV-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' // CHECK-SUBSCRIPT-UAV-NEXT: CompoundStmt // CHECK-SUBSCRIPT-UAV-NEXT: ReturnStmt -// CHECK-SUBSCRIPT-UAV-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' prefix '*' cannot overflow +// CHECK-SUBSCRIPT-UAV-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow // CHECK-SUBSCRIPT-UAV-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' // CHECK-SUBSCRIPT-UAV-NEXT: CallExpr // CHECK-SUBSCRIPT-UAV-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer' 'void (...) noexcept' @@ -314,7 +314,7 @@ RESOURCE Buffer; // CHECK-LOAD-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' // CHECK-LOAD-NEXT: CompoundStmt // CHECK-LOAD-NEXT: ReturnStmt -// CHECK-LOAD-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' prefix '*' cannot overflow +// CHECK-LOAD-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow // CHECK-LOAD-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' // CHECK-LOAD-NEXT: CallExpr // CHECK-LOAD-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer' 'void (...) noexcept' @@ -384,7 +384,7 @@ RESOURCE Buffer; // CHECK-APPEND-NEXT: ParmVarDecl {{.*}} value 'element_type' // CHECK-APPEND-NEXT: CompoundStmt // CHECK-APPEND-NEXT: BinaryOperator {{.*}} 'hlsl_device element_type' '=' -// CHECK-APPEND-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' prefix '*' cannot overflow +// CHECK-APPEND-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow // CHECK-APPEND-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' // CHECK-APPEND-NEXT: CallExpr // CHECK-APPEND-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer' 'void (...) noexcept' @@ -409,7 +409,7 @@ RESOURCE Buffer; // CHECK-CONSUME: CXXMethodDecl {{.*}} Consume 'element_type ()' // CHECK-CONSUME-NEXT: CompoundStmt // CHECK-CONSUME-NEXT: ReturnStmt -// CHECK-CONSUME-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' prefix '*' cannot overflow +// CHECK-CONSUME-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow // CHECK-CONSUME-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' // CHECK-CONSUME-NEXT: CallExpr // CHECK-CONSUME-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer' 'void (...) noexcept' diff --git a/clang/test/AST/HLSL/TypedBuffers-AST.hlsl b/clang/test/AST/HLSL/TypedBuffers-AST.hlsl index eb53ad5e9fd0e..c2144d230887b 100644 --- a/clang/test/AST/HLSL/TypedBuffers-AST.hlsl +++ b/clang/test/AST/HLSL/TypedBuffers-AST.hlsl @@ -166,7 +166,7 @@ RESOURCE Buffer; // CHECK-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' // CHECK-NEXT: CompoundStmt // CHECK-NEXT: ReturnStmt -// CHECK-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' prefix '*' cannot overflow +// CHECK-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow // CHECK-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' // CHECK-NEXT: CallExpr // CHECK-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer' 'void (...) noexcept' @@ -183,7 +183,7 @@ RESOURCE Buffer; // CHECK-UAV-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' // CHECK-UAV-NEXT: CompoundStmt // CHECK-UAV-NEXT: ReturnStmt -// CHECK-UAV-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' prefix '*' cannot overflow +// CHECK-UAV-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow // CHECK-UAV-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' // CHECK-UAV-NEXT: CallExpr // CHECK-UAV-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer' 'void (...) noexcept' @@ -201,7 +201,7 @@ RESOURCE Buffer; // CHECK-NEXT: ParmVarDecl {{.*}} Index 'unsigned int' // CHECK-NEXT: CompoundStmt // CHECK-NEXT: ReturnStmt -// CHECK-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' prefix '*' cannot overflow +// CHECK-NEXT: UnaryOperator {{.*}} 'hlsl_device element_type' lvalue prefix '*' cannot overflow // CHECK-NEXT: CStyleCastExpr {{.*}} 'hlsl_device element_type *' // CHECK-NEXT: CallExpr // CHECK-NEXT: DeclRefExpr {{.*}} '' Function {{.*}} '__builtin_hlsl_resource_getpointer' 'void (...) noexcept' diff --git a/clang/test/AST/HLSL/ast-dump-availability-attr.hlsl b/clang/test/AST/HLSL/ast-dump-availability-attr.hlsl new file mode 100644 index 0000000000000..2addc84722099 --- /dev/null +++ b/clang/test/AST/HLSL/ast-dump-availability-attr.hlsl @@ -0,0 +1,16 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -ast-dump=json %s | FileCheck %s + +// Test AvailabilityAttr fields in JSON AST dump + +__attribute__((availability(shadermodel, introduced=6.0, deprecated=6.3, obsoleted=6.5, replacement="new_func", environment=compute))) +void availability_all(void); + +// CHECK: "kind": "FunctionDecl", +// CHECK: "name": "availability_all", +// CHECK: "kind": "AvailabilityAttr", +// CHECK: "platform": "shadermodel", +// CHECK: "introduced": "6.0", +// CHECK: "deprecated": "6.3", +// CHECK: "obsoleted": "6.5", +// CHECK: "replacement": "new_func", +// CHECK: "environment": "compute" diff --git a/clang/test/AST/HLSL/matrix-elementexpr-tree-transform.hlsl b/clang/test/AST/HLSL/matrix-elementexpr-tree-transform.hlsl new file mode 100644 index 0000000000000..137c6395fbde1 --- /dev/null +++ b/clang/test/AST/HLSL/matrix-elementexpr-tree-transform.hlsl @@ -0,0 +1,17 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl -std=hlsl202x \ +// RUN: -finclude-default-header -ast-dump -ast-dump-filter=get00 %s | FileCheck %s + +template +T get00(matrix m) { + return m._m00; +} + +// Force instantiation for T=float. +float caller(matrix m) { + return get00(m); +} + +// CHECK-LABEL: FunctionTemplateDecl {{.*}} get00 +// CHECK: FunctionDecl {{.*}} get00 'T (matrix)' +// CHECK-LABEL: FunctionDecl {{.*}} get00 'float (matrix)' +// CHECK: MatrixElementExpr diff --git a/clang/test/AST/HLSL/matrix-member-access-scalar.hlsl b/clang/test/AST/HLSL/matrix-member-access-scalar.hlsl new file mode 100644 index 0000000000000..b403d27b29760 --- /dev/null +++ b/clang/test/AST/HLSL/matrix-member-access-scalar.hlsl @@ -0,0 +1,38 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl -ast-dump -o - %s | FileCheck %s + +typedef float float3x3 __attribute__((matrix_type(3,3))); + +[numthreads(1,1,1)] +void ok() { + float3x3 A; + + // CHECK: BinaryOperator {{.*}} 'vector' lvalue '=' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'vector' lvalue _m12 + // CHECK-NEXT: DeclRefExpr {{.*}} 'float3x3':'matrix' lvalue Var {{.*}} 'A' 'float3x3':'matrix' + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'vector' + // CHECK-NEXT: FloatingLiteral {{.*}} 'float' 3.140000e+00 + A._m12 = 3.14; + + // CHECK: VarDecl {{.*}} r 'float' cinit + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'float' + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'vector' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'vector' lvalue _m00 + // CHECK-NEXT: DeclRefExpr {{.*}} 'float3x3':'matrix' lvalue Var {{.*}} 'A' 'float3x3':'matrix' + float r = A._m00; + + // CHECK: VarDecl {{.*}} good1 'float' cinit + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'float' + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'vector' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'vector' lvalue _11 + // CHECK-NEXT: DeclRefExpr {{.*}} 'float3x3':'matrix' lvalue Var {{.*}} 'A' 'float3x3':'matrix' + float good1 = A._11; + + // CHECK: BinaryOperator {{.*}} 'vector' lvalue '=' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'vector' lvalue _33 + // CHECK-NEXT: DeclRefExpr {{.*}} 'float3x3':'matrix' lvalue Var {{.*}} 'A' 'float3x3':'matrix' + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'vector' + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'float' + // CHECK-NEXT: DeclRefExpr {{.*}} 'float' lvalue Var {{.*}} 'R' 'float' + float R; + A._33 = R; +} diff --git a/clang/test/AST/HLSL/matrix-member-access-swizzle-ast-dump-json.hlsl b/clang/test/AST/HLSL/matrix-member-access-swizzle-ast-dump-json.hlsl new file mode 100644 index 0000000000000..afb144624696a --- /dev/null +++ b/clang/test/AST/HLSL/matrix-member-access-swizzle-ast-dump-json.hlsl @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl \ +// RUN: -ast-dump=json -disable-llvm-passes -o - -hlsl-entry main %s \ +// RUN: | FileCheck %s + +typedef float float4x4 __attribute__((matrix_type(4,4))); +typedef float float2 __attribute__((ext_vector_type(2))); +typedef float float3 __attribute__((ext_vector_type(3))); + +float4x4 gMat; + +[numthreads(1, 1, 1)] +void main() { + float4x4 A = gMat; + + // one-based swizzle + float3 v1 = A._11_22_33; + + // zero-based swizzle + float2 v2 = A._m00_m11; +} + +// CHECK: "kind": "MatrixElementExpr" +// CHECK-NEXT: "range": { +// CHECK: "kind": "MatrixElementExpr" +// CHECK-NEXT: "range": { diff --git a/clang/test/AST/HLSL/matrix-member-access-swizzle-ast-print.hlsl b/clang/test/AST/HLSL/matrix-member-access-swizzle-ast-print.hlsl new file mode 100644 index 0000000000000..9d7c7ea5d9133 --- /dev/null +++ b/clang/test/AST/HLSL/matrix-member-access-swizzle-ast-print.hlsl @@ -0,0 +1,21 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl \ +// RUN: -ast-print -disable-llvm-passes -o - -hlsl-entry main %s \ +// RUN: | FileCheck %s + +typedef float float4x4 __attribute__((matrix_type(4,4))); +typedef float float2 __attribute__((ext_vector_type(2))); +typedef float float3 __attribute__((ext_vector_type(3))); + +float4x4 gMat; + +[numthreads(1, 1, 1)] +void main() { + float4x4 A = gMat; + float3 v1 = A._12_21_32; + float2 v2 = A._m01_m10; +} + +// CHECK: float4x4 gMat; +// CHECK: float4x4 A = gMat; +// CHECK: float3 v1 = A._12_21_32; +// CHECK: float2 v2 = A._m01_m10; diff --git a/clang/test/AST/HLSL/matrix-member-access-swizzle.hlsl b/clang/test/AST/HLSL/matrix-member-access-swizzle.hlsl new file mode 100644 index 0000000000000..2d0169e799802 --- /dev/null +++ b/clang/test/AST/HLSL/matrix-member-access-swizzle.hlsl @@ -0,0 +1,49 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl -ast-dump -o - %s | FileCheck %s + +typedef float float3x3 __attribute__((matrix_type(3,3))); +typedef float float4x4 __attribute__((matrix_type(4,4))); +typedef float float2 __attribute__((ext_vector_type(2))); +typedef float float3 __attribute__((ext_vector_type(3))); +typedef float float4 __attribute__((ext_vector_type(4))); + +[numthreads(1,1,1)] +void ok() { + float3x3 A; + + // CHECK: BinaryOperator {{.*}} 'float2':'vector' lvalue '=' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'float2':'vector' lvalue _m12_m21 + // CHECK-NEXT: DeclRefExpr {{.*}} 'float3x3':'matrix' lvalue Var {{.*}} 'A' 'float3x3':'matrix' + // CHECK-NEXT: ExtVectorElementExpr {{.*}} 'float2':'vector' xx + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'vector' + // CHECK-NEXT: FloatingLiteral {{.*}} 'float' 3.140000e+00 + A._m12_m21 = 3.14.xx; + + // CHECK: VarDecl {{.*}}r 'float2':'vector' cinit + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'float2':'vector' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'float2':'vector' lvalue _m00_m11 + // CHECK-NEXT: DeclRefExpr {{.*}} 'float3x3':'matrix' lvalue Var {{.*}} 'A' 'float3x3':'matrix' + float2 r = A._m00_m11; + + // CHECK: VarDecl {{.*}} good1 'float3':'vector' cinit + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'float3':'vector' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'float3':'vector' lvalue _11_22_33 + // CHECK-NEXT: DeclRefExpr {{.*}} 'float3x3':'matrix' lvalue Var {{.*}} 'A' 'float3x3':'matrix' + float3 good1 = A._11_22_33; + + // CHECK: BinaryOperator {{.*}} 'float4':'vector' lvalue '=' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'float4':'vector' lvalue _11_22_33_44 + // CHECK-NEXT: DeclRefExpr {{.*}} 'float4x4':'matrix' lvalue Var {{.*}} 'B' 'float4x4':'matrix' + // CHECK-NEXT: ImplicitCastExpr {{.*}} 'float4':'vector' + // CHECK-NEXT: DeclRefExpr {{.*}} 'float4':'vector' lvalue Var {{.*}} 'R' 'float4':'vector' + float4 R; + float4x4 B; + B._11_22_33_44 = R; + + // CHECK: BinaryOperator {{.*}} 'float3':'vector' lvalue '=' + // CHECK-NEXT: MatrixElementExpr {{.*}} 'float3':'vector' lvalue _11_22_33 + // CHECK-NEXT: DeclRefExpr{{.*}} 'float3x3':'matrix' lvalue Var {{.*}} 'A' 'float3x3':'matrix' + // CHECK-NEXT: ImplicitCastExpr {{.*}}'float3':'vector' + // CHECK-NEXT: ExtVectorElementExpr {{.*}} 'float3':'vector' lvalue vectorcomponent rgb + // CHECK-NEXT: DeclRefExpr {{.*}} 'float4':'vector' lvalue Var {{.*}} 'R' 'float4':'vector' + A._11_22_33 = R.rgb; +} diff --git a/clang/test/AST/HLSL/pch_with_matrix_element_accessor.hlsl b/clang/test/AST/HLSL/pch_with_matrix_element_accessor.hlsl new file mode 100644 index 0000000000000..46f340a4196d8 --- /dev/null +++ b/clang/test/AST/HLSL/pch_with_matrix_element_accessor.hlsl @@ -0,0 +1,26 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -finclude-default-header -emit-pch -o %t %S/Inputs/pch.hlsl +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -finclude-default-header -include-pch %t -ast-dump-all %s | FileCheck %s + +float4x4 gM; + +// CHECK: FunctionDecl {{.*}} getDiag 'float4 ()' +// CHECK-NEXT: CompoundStmt {{.*}} +// CHECK-NEXT: ReturnStmt {{.*}} +// CHECK-NEXT: ImplicitCastExpr {{.*}} 'vector' +// CHECK-NEXT: MatrixElementExpr {{.*}} 'vector' lvalue _11_22_33_44 +// CHECK-NEXT: DeclRefExpr {{.*}} 'hlsl_constant float4x4':'matrix' lvalue Var {{.*}} 'gM' 'hlsl_constant float4x4':'matrix' +float4 getDiag() { + return gM._11_22_33_44; +} + +// CHECK: FunctionDecl {{.*}} setRowZero 'void (float4)' +// CHECK-NEXT: ParmVarDecl {{.*}} used V 'float4':'vector' +// CHECK-NEXT: CompoundStmt {{.*}} +// CHECK-NEXT: BinaryOperator {{.*}} 'vector' lvalue '=' +// CHECK-NEXT: MatrixElementExpr {{.*}} 'vector' lvalue _m00_m01_m02_m03 +// CHECK-NEXT: DeclRefExpr {{.*}} 'hlsl_constant float4x4':'matrix' lvalue Var {{.*}} 'gM' 'hlsl_constant float4x4':'matrix' +// CHECK-NEXT: ImplicitCastExpr {{.*}} 'float4':'vector' +// CHECK-NEXT: DeclRefExpr {{.*}} 'float4':'vector' lvalue ParmVar {{.*}} 'V' 'float4':'vector' +void setRowZero(float4 V) { + gM._m00_m01_m02_m03 = V; +} diff --git a/clang/test/AST/ast-dump-attr-json.cpp b/clang/test/AST/ast-dump-attr-json.cpp index 883e584bfedf0..454d9665dcfe2 100644 --- a/clang/test/AST/ast-dump-attr-json.cpp +++ b/clang/test/AST/ast-dump-attr-json.cpp @@ -21,6 +21,13 @@ __attribute__ ((visibility ("hidden"))) int visibility_var; __thread __attribute__ ((tls_model ("local-exec"))) int tls_model_var; +__attribute__((availability(macos, introduced=10.15, deprecated=12.0, obsoleted=13.0, strict, replacement="new_func"))) int availability_var_all; +__attribute__((availability(macos, unavailable, message="use new API"))) int availability_var_unavailable; + +#pragma clang attribute push(__attribute__((availability(macos, introduced=11.0))), apply_to=variable) +int availability_var_pragma; +#pragma clang attribute pop + // NOTE: CHECK lines have been autogenerated by gen_ast_dump_json_test.py // using --filters=VarDecl @@ -529,3 +536,154 @@ __thread __attribute__ ((tls_model ("local-exec"))) int tls_model_var; // CHECK-NEXT: } // CHECK-NEXT: ] // CHECK-NEXT: } + + +// CHECK-NOT: {{^}}Dumping +// CHECK: "kind": "VarDecl", +// CHECK-NEXT: "loc": { +// CHECK-NEXT: "offset": 888, +// CHECK-NEXT: "line": 24, +// CHECK-NEXT: "col": 125, +// CHECK-NEXT: "tokLen": 20 +// CHECK-NEXT: }, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": { +// CHECK-NEXT: "offset": 764, +// CHECK-NEXT: "col": 1, +// CHECK-NEXT: "tokLen": 13 +// CHECK-NEXT: }, +// CHECK-NEXT: "end": { +// CHECK-NEXT: "offset": 888, +// CHECK-NEXT: "col": 125, +// CHECK-NEXT: "tokLen": 20 +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: "name": "availability_var_all", +// CHECK-NEXT: "mangledName": "availability_var_all", +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "int" +// CHECK-NEXT: }, +// CHECK-NEXT: "inner": [ +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "AvailabilityAttr", +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": { +// CHECK-NEXT: "offset": 779, +// CHECK-NEXT: "col": 16, +// CHECK-NEXT: "tokLen": 12 +// CHECK-NEXT: }, +// CHECK-NEXT: "end": { +// CHECK-NEXT: "offset": 880, +// CHECK-NEXT: "col": 117, +// CHECK-NEXT: "tokLen": 1 +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: "platform": "macos", +// CHECK-NEXT: "introduced": "10.15", +// CHECK-NEXT: "deprecated": "12.0", +// CHECK-NEXT: "obsoleted": "13.0", +// CHECK-NEXT: "strict": true, +// CHECK-NEXT: "replacement": "new_func" +// CHECK-NEXT: } +// CHECK-NEXT: ] +// CHECK-NEXT: } + + +// CHECK-NOT: {{^}}Dumping +// CHECK: "kind": "VarDecl", +// CHECK-NEXT: "loc": { +// CHECK-NEXT: "offset": 987, +// CHECK-NEXT: "line": 25, +// CHECK-NEXT: "col": 78, +// CHECK-NEXT: "tokLen": 28 +// CHECK-NEXT: }, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": { +// CHECK-NEXT: "offset": 910, +// CHECK-NEXT: "col": 1, +// CHECK-NEXT: "tokLen": 13 +// CHECK-NEXT: }, +// CHECK-NEXT: "end": { +// CHECK-NEXT: "offset": 987, +// CHECK-NEXT: "col": 78, +// CHECK-NEXT: "tokLen": 28 +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: "name": "availability_var_unavailable", +// CHECK-NEXT: "mangledName": "availability_var_unavailable", +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "int" +// CHECK-NEXT: }, +// CHECK-NEXT: "inner": [ +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "AvailabilityAttr", +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": { +// CHECK-NEXT: "offset": 925, +// CHECK-NEXT: "col": 16, +// CHECK-NEXT: "tokLen": 12 +// CHECK-NEXT: }, +// CHECK-NEXT: "end": { +// CHECK-NEXT: "offset": 979, +// CHECK-NEXT: "col": 70, +// CHECK-NEXT: "tokLen": 1 +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: "platform": "macos", +// CHECK-NEXT: "unavailable": true, +// CHECK-NEXT: "message": "use new API" +// CHECK-NEXT: } +// CHECK-NEXT: ] +// CHECK-NEXT: } + + +// CHECK-NOT: {{^}}Dumping +// CHECK: "kind": "VarDecl", +// CHECK-NEXT: "loc": { +// CHECK-NEXT: "offset": 1125, +// CHECK-NEXT: "line": 28, +// CHECK-NEXT: "col": 5, +// CHECK-NEXT: "tokLen": 23 +// CHECK-NEXT: }, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": { +// CHECK-NEXT: "offset": 1121, +// CHECK-NEXT: "col": 1, +// CHECK-NEXT: "tokLen": 3 +// CHECK-NEXT: }, +// CHECK-NEXT: "end": { +// CHECK-NEXT: "offset": 1125, +// CHECK-NEXT: "col": 5, +// CHECK-NEXT: "tokLen": 23 +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: "name": "availability_var_pragma", +// CHECK-NEXT: "mangledName": "availability_var_pragma", +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "int" +// CHECK-NEXT: }, +// CHECK-NEXT: "inner": [ +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "AvailabilityAttr", +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": { +// CHECK-NEXT: "offset": 1062, +// CHECK-NEXT: "line": 27, +// CHECK-NEXT: "col": 45, +// CHECK-NEXT: "tokLen": 12 +// CHECK-NEXT: }, +// CHECK-NEXT: "end": { +// CHECK-NEXT: "offset": 1097, +// CHECK-NEXT: "col": 80, +// CHECK-NEXT: "tokLen": 1 +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: "platform": "macos", +// CHECK-NEXT: "introduced": "11.0", +// CHECK-NEXT: "priority": 1 +// CHECK-NEXT: } +// CHECK-NEXT: ] +// CHECK-NEXT: } diff --git a/clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use-arc.mm b/clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use-arc.mm index 47203cbd27355..79ea95b088167 100644 --- a/clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use-arc.mm +++ b/clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use-arc.mm @@ -69,6 +69,9 @@ - (SomeObj *)copyWithValue:(int)value { return copy; } +- (void)copy:(id)sender { +} + - (void)doWork { _number = [[NSNumber alloc] initWithInt:5]; } @@ -99,6 +102,17 @@ - (void)setValue:(NSNumber *)value { @end; +@interface SubObj : SomeObj +@end + +@implementation SubObj + +- (void)copy:(id)sender { + [super copy:sender]; // no-warning: a void copy does not actually copy anything +} + +@end + RetainPtr cf_out_argument() { auto surface = adoptCF(IOSurfaceCreate(nullptr)); CVPixelBufferRef rawBuffer = nullptr; diff --git a/clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use.mm b/clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use.mm index 427affdbbd601..20f951b27a149 100644 --- a/clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use.mm +++ b/clang/test/Analysis/Checkers/WebKit/retain-ptr-ctor-adopt-use.mm @@ -76,6 +76,9 @@ - (SomeObj *)copyWithValue:(int)value { return copy; } +- (void)copy:(id)sender { +} + - (void)doWork { _number = [[NSNumber alloc] initWithInt:5]; } @@ -114,6 +117,17 @@ - (id)copyWithZone:(NSZone *)zone { @end; +@interface SubObj : SomeObj +@end + +@implementation SubObj + +- (void)copy:(id)sender { + [super copy:sender]; +} + +@end + RetainPtr cf_out_argument() { auto surface = adoptCF(IOSurfaceCreate(nullptr)); CVPixelBufferRef rawBuffer = nullptr; diff --git a/clang/test/Analysis/Inputs/system-header-simulator-cxx-std-suppression.h b/clang/test/Analysis/Inputs/system-header-simulator-cxx-std-suppression.h index dc53af269c9c2..3b3b316469094 100644 --- a/clang/test/Analysis/Inputs/system-header-simulator-cxx-std-suppression.h +++ b/clang/test/Analysis/Inputs/system-header-simulator-cxx-std-suppression.h @@ -10,6 +10,12 @@ typedef unsigned char uint8_t; typedef __typeof__(sizeof(int)) size_t; void *memmove(void *s1, const void *s2, size_t n); +#define TRIGGER_DIV_BY_ZERO \ +do { \ + int z = 0; \ + z = 5/z; \ +} while (0) + namespace std { template @@ -41,8 +47,7 @@ namespace std { // Fake use-after-free. // No warning is expected as we are suppressing warning coming // out of std::list. - int z = 0; - z = 5/z; + TRIGGER_DIV_BY_ZERO; } bool empty() const; }; @@ -69,8 +74,7 @@ namespace std { // Fake error trigger. // No warning is expected as we are suppressing warning coming // out of std::basic_string. - int z = 0; - z = 5/z; + TRIGGER_DIV_BY_ZERO; } _CharT *getBuffer() { @@ -108,8 +112,7 @@ __independent_bits_engine<_Engine, _UIntType> // Fake error trigger. // No warning is expected as we are suppressing warning coming // out of std::__independent_bits_engine. - int z = 0; - z = 5/z; + TRIGGER_DIV_BY_ZERO; } #if __has_feature(cxx_decltype) @@ -130,8 +133,7 @@ class shared_ptr // Fake error trigger. // No warning is expected as we are suppressing warning coming // out of std::shared_ptr. - int z = 0; - z = 5/z; + TRIGGER_DIV_BY_ZERO; } }; @@ -142,5 +144,28 @@ shared_ptr<_Tp>::shared_ptr(nullptr_t) { } #endif // __has_feature(cxx_decltype) + +template +void sort(_RandomAccessIterator __first, _RandomAccessIterator __last) { + // Fake error trigger + // std::sort is expected to be evaluated conservatively. + TRIGGER_DIV_BY_ZERO; +} + +template +void stable_sort(_RandomAccessIterator __first, _RandomAccessIterator __last) { + // Fake error trigger + // std::stable_sort is expected to be evaluated conservatively. + TRIGGER_DIV_BY_ZERO; +} + +template +void inplace_merge(_BidirectionalIterator __first, + _BidirectionalIterator __middle, + _BidirectionalIterator __last) { + // Fake error trigger + // std::inplace_merge is expected to be evaluated conservatively. + TRIGGER_DIV_BY_ZERO; } +} // namespace std diff --git a/clang/test/Analysis/diagnostics/opaque-stl-functions-modeling.cpp b/clang/test/Analysis/diagnostics/opaque-stl-functions-modeling.cpp new file mode 100644 index 0000000000000..283cf27c4f993 --- /dev/null +++ b/clang/test/Analysis/diagnostics/opaque-stl-functions-modeling.cpp @@ -0,0 +1,16 @@ +// RUN: %clang_analyze_cc1 -verify %s \ +// RUN: -analyzer-checker=core,apiModeling \ +// RUN: -analyzer-dump-egraph=%t.dot \ +// RUN: -analyze-function="test_opaque_handling()" +// RUN: grep 'apiModeling.OpaqueSTLFunctionsModeling' %t.dot | count 3 + +// expected-no-diagnostics + +#include "../Inputs/system-header-simulator-cxx-std-suppression.h" + +void test_opaque_handling() { + int arr[5] = {}; + std::sort(arr, arr + 5); // no-warning + std::stable_sort(arr, arr + 5); // no-warning + std::inplace_merge(arr, arr + 2, arr + 5); // no-warning +} diff --git a/clang/test/Analysis/store-union-aggregates.c b/clang/test/Analysis/store-union-aggregates.c new file mode 100644 index 0000000000000..4b084cc080929 --- /dev/null +++ b/clang/test/Analysis/store-union-aggregates.c @@ -0,0 +1,35 @@ +// RUN: %clang_analyze_cc1 -verify %s + +// expected-no-diagnostics + +struct SizedBufferPtr { + union { + int* buffer_ptr; + } /*anonymous*/; + int size; +}; + +extern int global_buf_size; +extern int global_buf[]; + +void analysis_entry_point_rdar167136849(void) { + // When binding the initial value for "buffers". + // We will first bind the first array element: buffers[0] <- cv{cv{&Elem{global_buf, 0}}} + // This is of type "struct SizedBufferPtr" so we dispatch this bind to bind by fields. + // So we bind: buffers[0].union anonymous <- cv{&Elem{global_buf, 0}} + // Because that is "isUnionType", its bound using "bindAggregate", thus add a default binding. + // After this we have in the Store: { default at 0: cv{&Elem{global_buf, 0}} } + // We then bind the second field: buffers[0].size <- reg{global_buf_size} + // After this we have in the Store: { default at 0: cv{&Elem{global_buf, 0}}, direct at 64: reg{global_buf_size} } + // We are done with the initializer expression, so we realize that + // the second element of "buffers" didn't have an explicit initializer, + // so we need to bind a suitable default value using "setImplicitDefaultValue". + // That happens to add a default binding 0 to "buffer", which overwrites the previous default binding that "bindAggregate" added. + // After this we falsely conclude that "buffers[0].buffer_ptr" is a nullptr. + + struct SizedBufferPtr buffers[2] = { + {.buffer_ptr = global_buf, .size = global_buf_size}, + // [1] is not explicitly initialized, so it will be defaulted to zero. + }; + *buffers[0].buffer_ptr = 2; // no-warning: writing indirectly to "global_buf" is fine +} diff --git a/clang/test/Analysis/uninit-vals.cpp b/clang/test/Analysis/uninit-vals.cpp index 6ba56f0c4e78b..7775e6a2125d3 100644 --- a/clang/test/Analysis/uninit-vals.cpp +++ b/clang/test/Analysis/uninit-vals.cpp @@ -33,3 +33,21 @@ void foo() { } } +namespace gh_178797 { +struct SpecialBuffer { + SpecialBuffer() : src(defaultBuffer), dst(defaultBuffer) {} + int* src; + int* dst; + int defaultBuffer[2]; +}; +// Not really a swap, but we need an assignment assigning UndefinedVal +// within a "swap" function to trigger this behavior. +void swap(int& lhs, int& rhs) { + lhs = rhs; // no-crash + // Not reporting copying uninitialized data because that is explicitly suppressed in the checker. +} +void entry_point() { + SpecialBuffer special; + swap(*special.dst, *++special.src); +} +} // namespace gh_178797 diff --git a/clang/test/CIR/CodeGen/alloc-size.c b/clang/test/CIR/CodeGen/alloc-size.c new file mode 100644 index 0000000000000..17b548c369217 --- /dev/null +++ b/clang/test/CIR/CodeGen/alloc-size.c @@ -0,0 +1,79 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM + +#define NULL ((void *)0) + +typedef unsigned long size_t; + +// CIR: cir.func{{.*}}@my_malloc(!s32i){{.*}} attributes {allocsize = array} +extern void *my_malloc(int) __attribute__((alloc_size(1))); +// CIR: cir.func{{.*}}@my_calloc(!s32i, !s32i){{.*}} attributes {allocsize = array} +extern void *my_calloc(int, int) __attribute__((alloc_size(1, 2))); + +// CIR-LABEL: @call_direct +// LLVM-LABEL: @call_direct +void call_direct(void) { + my_malloc(50); + // CIR: cir.call @my_malloc(%{{.*}}) {allocsize = array} + // LLVM: call ptr @my_malloc(i32{{.*}} 50) [[DIRECT_MALLOC_ATTR:#[0-9]+]] + my_calloc(1, 16); + // CIR: cir.call @my_calloc(%{{.*}}) {allocsize = array} + // LLVM: call ptr @my_calloc(i32{{.*}} 1, i32{{.*}} 16) [[DIRECT_CALLOC_ATTR:#[0-9]+]] +} + +extern void *(*malloc_function_pointer)(void *, int)__attribute__((alloc_size(2))); +extern void *(*calloc_function_pointer)(void *, int, int)__attribute__((alloc_size(2, 3))); + +// CIR-LABEL: @call_function_pointer +// LLVM-LABEL: @call_function_pointer +void call_function_pointer(void) { + malloc_function_pointer(NULL, 100); + // CIR: %[[MALLOC_FN_PTR_GLOBAL:.*]] = cir.get_global @malloc_function_pointer + // CIR: %[[MALLOC_FN_PTR:.+]] = cir.load{{.*}}%[[MALLOC_FN_PTR_GLOBAL]] + // CIR: cir.call %[[MALLOC_FN_PTR]]({{.*}}) {allocsize = array} + // + // LLVM: %[[MALLOC_FN_PTR:.+]] = load ptr, ptr @malloc_function_pointer, align 8 + // LLVM: call ptr %[[MALLOC_FN_PTR]](ptr{{.*}} null, i32{{.*}} 100) [[INDIRECT_MALLOC_ATTR:#[0-9]+]] + calloc_function_pointer(NULL, 2, 4); + // CIR: %[[CALLOC_FN_PTR_GLOBAL:.*]] = cir.get_global @calloc_function_pointer + // CIR: %[[CALLOC_FN_PTR:.+]] = cir.load{{.*}}%[[CALLOC_FN_PTR_GLOBAL]] + // CIR: cir.call %[[CALLOC_FN_PTR]]({{.*}}) {allocsize = array} + // + // LLVM: %[[CALLOC_FN_PTR:.+]] = load ptr, ptr @calloc_function_pointer, align 8 + // LLVM: call ptr %[[CALLOC_FN_PTR]](ptr{{.*}} null, i32{{.*}} 2, i32{{.*}} 4) [[INDIRECT_CALLOC_ATTR:#[0-9]+]] +} + +typedef void *(__attribute__((alloc_size(3))) * my_malloc_fn_pointer_type)(void *, void *, int); +typedef void *(__attribute__((alloc_size(3, 4))) * my_calloc_fn_pointer_type)(void *, void *, int, int); +extern my_malloc_fn_pointer_type malloc_function_pointer_with_typedef; +extern my_calloc_fn_pointer_type calloc_function_pointer_with_typedef; + +// CIR-LABEL: @call_function_pointer_typedef +// LLVM-LABEL: @call_function_pointer_typedef +void call_function_pointer_typedef(void) { + malloc_function_pointer_with_typedef(NULL, NULL, 200); + // CIR: %[[INDIRECT_TYPEDEF_MALLOC_FN_PTR_GLOBAL:.*]] = cir.get_global @malloc_function_pointer_with_typedef + // CIR: %[[INDIRECT_TYPEDEF_MALLOC_FN_PTR:.+]] = cir.load{{.*}}%[[INDIRECT_TYPEDEF_MALLOC_FN_PTR_GLOBAL]] + // CIR: cir.call %[[INDIRECT_TYPEDEF_MALLOC_FN_PTR]]({{.*}}) {allocsize = array} + // + // LLVM: %[[INDIRECT_TYPEDEF_MALLOC_FN_PTR:.+]] = load ptr, ptr @malloc_function_pointer_with_typedef, align 8 + // LLVM: call ptr %[[INDIRECT_TYPEDEF_MALLOC_FN_PTR]](ptr{{.*}} null, ptr{{.*}} null, i32{{.*}} 200) [[INDIRECT_TYPEDEF_MALLOC_ATTR:#[0-9]+]] + calloc_function_pointer_with_typedef(NULL, NULL, 8, 4); + // CIR: %[[INDIRECT_TYPEDEF_CALLOC_FN_PTR_GLOBAL:.*]] = cir.get_global @calloc_function_pointer_with_typedef + // CIR: %[[INDIRECT_TYPEDEF_CALLOC_FN_PTR:.+]] = cir.load{{.*}}%[[INDIRECT_TYPEDEF_CALLOC_FN_PTR_GLOBAL]] + // CIR: cir.call %[[INDIRECT_TYPEDEF_CALLOC_FN_PTR]]({{.*}}) {allocsize = array} + // + // LLVM: %[[INDIRECT_TYPEDEF_CALLOC_FN_PTR:.+]] = load ptr, ptr @calloc_function_pointer_with_typedef, align 8 + // LLVM: call ptr %[[INDIRECT_TYPEDEF_CALLOC_FN_PTR]](ptr{{.*}} null, ptr{{.*}} null, i32{{.*}} 8, i32{{.*}} 4) [[INDIRECT_TYPEDEF_CALLOC_ATTR:#[0-9]+]] +} + +// LLVM: attributes [[DIRECT_MALLOC_ATTR]] = { allocsize(0) } +// LLVM: attributes [[DIRECT_CALLOC_ATTR]] = { allocsize(0,1) } +// LLVM: attributes [[INDIRECT_MALLOC_ATTR]] = { allocsize(1) } +// LLVM: attributes [[INDIRECT_CALLOC_ATTR]] = { allocsize(1,2) } +// LLVM: attributes [[INDIRECT_TYPEDEF_MALLOC_ATTR]] = { allocsize(2) } +// LLVM: attributes [[INDIRECT_TYPEDEF_CALLOC_ATTR]] = { allocsize(2,3) } diff --git a/clang/test/CIR/CodeGen/atomic-scoped.c b/clang/test/CIR/CodeGen/atomic-scoped.c index 62d075c21a893..d34b95b9a305a 100644 --- a/clang/test/CIR/CodeGen/atomic-scoped.c +++ b/clang/test/CIR/CodeGen/atomic-scoped.c @@ -1,4 +1,5 @@ -// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir %s -o %t.cir +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-cir -mmlir --mlir-print-ir-before=cir-target-lowering %s -o %t.cir 2>%t-before-target-lowering.cir +// RUN: FileCheck --input-file=%t-before-target-lowering.cir %s --check-prefixes=CIR-BEFORE-TL // RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -Wno-unused-value -fclangir -emit-llvm %s -o %t-cir.ll // RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=LLVM @@ -6,17 +7,20 @@ // RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG void scoped_atomic_load(int *ptr) { + // CIR-BEFORE-TL-LABEL: @scoped_atomic_load // CIR-LABEL: @scoped_atomic_load // LLVM-LABEL: @scoped_atomic_load // OGCG-LABEL: @scoped_atomic_load int x; __scoped_atomic_load(ptr, &x, __ATOMIC_RELAXED, __MEMORY_SCOPE_SINGLE); - // CIR: %{{.+}} = cir.load align(4) syncscope(single_thread) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i + // CIR-BEFORE-TL: %{{.+}} = cir.load align(4) syncscope(single_thread) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i + // CIR: %{{.+}} = cir.load align(4) syncscope(system) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i // LLVM: %{{.+}} = load atomic i32, ptr %{{.+}} monotonic, align 4 // OGCG: %{{.+}} = load atomic i32, ptr %{{.+}} monotonic, align 4 __scoped_atomic_load(ptr, &x, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); + // CIR-BEFORE-TL: %{{.+}} = cir.load align(4) syncscope(system) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i // CIR: %{{.+}} = cir.load align(4) syncscope(system) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i // LLVM: %{{.+}} = load atomic i32, ptr %{{.+}} monotonic, align 4 // OGCG: %{{.+}} = load atomic i32, ptr %{{.+}} monotonic, align 4 @@ -29,11 +33,13 @@ void scoped_atomic_load_n(int *ptr) { int x; x = __scoped_atomic_load_n(ptr, __ATOMIC_RELAXED, __MEMORY_SCOPE_SINGLE); - // CIR: %{{.+}} = cir.load align(4) syncscope(single_thread) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i + // CIR-BEFORE-TL: %{{.+}} = cir.load align(4) syncscope(single_thread) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i + // CIR: %{{.+}} = cir.load align(4) syncscope(system) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i // LLVM: %{{.+}} = load atomic i32, ptr %{{.+}} monotonic, align 4 // OGCG: %{{.+}} = load atomic i32, ptr %{{.+}} monotonic, align 4 x = __scoped_atomic_load_n(ptr, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); + // CIR-BEFORE-TL: %{{.+}} = cir.load align(4) syncscope(system) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i // CIR: %{{.+}} = cir.load align(4) syncscope(system) atomic(relaxed) %{{.+}} : !cir.ptr, !s32i // LLVM: %{{.+}} = load atomic i32, ptr %{{.+}} monotonic, align 4 // OGCG: %{{.+}} = load atomic i32, ptr %{{.+}} monotonic, align 4 @@ -45,11 +51,13 @@ void scoped_atomic_store(int *ptr, int value) { // OGCG-LABEL: @scoped_atomic_store __scoped_atomic_store(ptr, &value, __ATOMIC_RELAXED, __MEMORY_SCOPE_SINGLE); - // CIR: cir.store align(4) syncscope(single_thread) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr + // CIR-BEFORE-TL: cir.store align(4) syncscope(single_thread) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr + // CIR: cir.store align(4) syncscope(system) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr // LLVM: store atomic i32 %{{.+}}, ptr %{{.+}} monotonic, align 4 // OGCG: store atomic i32 %{{.+}}, ptr %{{.+}} monotonic, align 4 __scoped_atomic_store(ptr, &value, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); + // CIR-BEFORE-TL: cir.store align(4) syncscope(system) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr // CIR: cir.store align(4) syncscope(system) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr // LLVM: store atomic i32 %{{.+}}, ptr %{{.+}} monotonic, align 4 // OGCG: store atomic i32 %{{.+}}, ptr %{{.+}} monotonic, align 4 @@ -61,12 +69,46 @@ void scoped_atomic_store_n(int *ptr, int value) { // OGCG-LABEL: @scoped_atomic_store_n __scoped_atomic_store_n(ptr, value, __ATOMIC_RELAXED, __MEMORY_SCOPE_SINGLE); - // CIR: cir.store align(4) syncscope(single_thread) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr + // CIR-BEFORE-TL: cir.store align(4) syncscope(single_thread) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr + // CIR: cir.store align(4) syncscope(system) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr // LLVM: store atomic i32 %{{.+}}, ptr %{{.+}} monotonic, align 4 // OGCG: store atomic i32 %{{.+}}, ptr %{{.+}} monotonic, align 4 __scoped_atomic_store_n(ptr, value, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); + // CIR-BEFORE-TL: cir.store align(4) syncscope(system) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr // CIR: cir.store align(4) syncscope(system) atomic(relaxed) %{{.+}}, %{{.+}} : !s32i, !cir.ptr // LLVM: store atomic i32 %{{.+}}, ptr %{{.+}} monotonic, align 4 // OGCG: store atomic i32 %{{.+}}, ptr %{{.+}} monotonic, align 4 } + +void scoped_atomic_exchange(int *ptr, int *value, int *old) { + // CIR-LABEL: @scoped_atomic_exchange + // LLVM-LABEL: @scoped_atomic_exchange + // OGCG-LABEL: @scoped_atomic_exchange + + __scoped_atomic_exchange(ptr, value, old, __ATOMIC_RELAXED, __MEMORY_SCOPE_SINGLE); + // CIR: %{{.+}} = cir.atomic.xchg relaxed syncscope(single_thread) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 + // OGCG: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 + + __scoped_atomic_exchange(ptr, value, old, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); + // CIR: %{{.+}} = cir.atomic.xchg relaxed syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 + // OGCG: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 +} + +void scoped_atomic_exchange_n(int *ptr, int value) { + // CIR-LABEL: @scoped_atomic_exchange_n + // LLVM-LABEL: @scoped_atomic_exchange_n + // OGCG-LABEL: @scoped_atomic_exchange_n + + __scoped_atomic_exchange_n(ptr, value, __ATOMIC_RELAXED, __MEMORY_SCOPE_SINGLE); + // CIR: %{{.+}} = cir.atomic.xchg relaxed syncscope(single_thread) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 + // OGCG: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 + + __scoped_atomic_exchange_n(ptr, value, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); + // CIR: %{{.+}} = cir.atomic.xchg relaxed syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 + // OGCG: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 +} diff --git a/clang/test/CIR/CodeGen/atomic.c b/clang/test/CIR/CodeGen/atomic.c index 6477c8b6e1b85..631ab6174c937 100644 --- a/clang/test/CIR/CodeGen/atomic.c +++ b/clang/test/CIR/CodeGen/atomic.c @@ -480,12 +480,12 @@ void c11_atomic_exchange(_Atomic(int) *ptr, int value) { __c11_atomic_exchange(ptr, value, __ATOMIC_RELEASE); __c11_atomic_exchange(ptr, value, __ATOMIC_ACQ_REL); __c11_atomic_exchange(ptr, value, __ATOMIC_SEQ_CST); - // CIR: %{{.+}} = cir.atomic.xchg relaxed %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acquire %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acquire %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg release %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acq_rel %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg seq_cst %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg relaxed syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acquire syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acquire syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg release syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acq_rel syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg seq_cst syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} acquire, align 4 @@ -513,12 +513,12 @@ void atomic_exchange(int *ptr, int *value, int *old) { __atomic_exchange(ptr, value, old, __ATOMIC_RELEASE); __atomic_exchange(ptr, value, old, __ATOMIC_ACQ_REL); __atomic_exchange(ptr, value, old, __ATOMIC_SEQ_CST); - // CIR: %{{.+}} = cir.atomic.xchg relaxed %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acquire %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acquire %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg release %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acq_rel %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg seq_cst %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg relaxed syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acquire syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acquire syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg release syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acq_rel syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg seq_cst syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} acquire, align 4 @@ -546,12 +546,12 @@ void atomic_exchange_n(int *ptr, int value) { __atomic_exchange_n(ptr, value, __ATOMIC_RELEASE); __atomic_exchange_n(ptr, value, __ATOMIC_ACQ_REL); __atomic_exchange_n(ptr, value, __ATOMIC_SEQ_CST); - // CIR: %{{.+}} = cir.atomic.xchg relaxed %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acquire %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acquire %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg release %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg acq_rel %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - // CIR: %{{.+}} = cir.atomic.xchg seq_cst %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg relaxed syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acquire syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acquire syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg release syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg acq_rel syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + // CIR: %{{.+}} = cir.atomic.xchg seq_cst syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} monotonic, align 4 // LLVM: %{{.+}} = atomicrmw xchg ptr %{{.+}}, i32 %{{.+}} acquire, align 4 @@ -2065,31 +2065,31 @@ int atomic_load_and_store_dynamic_order(int *ptr, int order) { // CIR: cir.switch(%[[ORDER]] : !s32i) { // CIR-NEXT: cir.case(default, []) { // CIR-NEXT: %[[LIT:.+]] = cir.load align(4) %{{.+}} : !cir.ptr, !s32i - // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg relaxed %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i + // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg relaxed syncscope(system) %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i // CIR-NEXT: cir.store align(4) %[[RES]], %[[RES_SLOT:.+]] : !s32i, !cir.ptr // CIR-NEXT: cir.break // CIR-NEXT: } // CIR-NEXT: cir.case(anyof, [#cir.int<1> : !s32i, #cir.int<2> : !s32i]) { // CIR-NEXT: %[[LIT:.+]] = cir.load align(4) %{{.+}} : !cir.ptr, !s32i - // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg acquire %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i + // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg acquire syncscope(system) %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i // CIR-NEXT: cir.store align(4) %[[RES]], %[[RES_SLOT]] : !s32i, !cir.ptr // CIR-NEXT: cir.break // CIR-NEXT: } // CIR-NEXT: cir.case(anyof, [#cir.int<3> : !s32i]) { // CIR-NEXT: %[[LIT:.+]] = cir.load align(4) %{{.+}} : !cir.ptr, !s32i - // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg release %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i + // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg release syncscope(system) %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i // CIR-NEXT: cir.store align(4) %[[RES]], %[[RES_SLOT]] : !s32i, !cir.ptr // CIR-NEXT: cir.break // CIR-NEXT: } // CIR-NEXT: cir.case(anyof, [#cir.int<4> : !s32i]) { // CIR-NEXT: %[[LIT:.+]] = cir.load align(4) %{{.+}} : !cir.ptr, !s32i - // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg acq_rel %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i + // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg acq_rel syncscope(system) %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i // CIR-NEXT: cir.store align(4) %[[RES]], %[[RES_SLOT]] : !s32i, !cir.ptr // CIR-NEXT: cir.break // CIR-NEXT: } // CIR-NEXT: cir.case(anyof, [#cir.int<5> : !s32i]) { // CIR-NEXT: %[[LIT:.+]] = cir.load align(4) %{{.+}} : !cir.ptr, !s32i - // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg seq_cst %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i + // CIR-NEXT: %[[RES:.+]] = cir.atomic.xchg seq_cst syncscope(system) %[[PTR]], %[[LIT]] : (!cir.ptr, !s32i) -> !s32i // CIR-NEXT: cir.store align(4) %[[RES]], %[[RES_SLOT]] : !s32i, !cir.ptr // CIR-NEXT: cir.break // CIR-NEXT: } diff --git a/clang/test/CIR/CodeGen/coro-task.cpp b/clang/test/CIR/CodeGen/coro-task.cpp index c7072daa051e5..0a2b49345e628 100644 --- a/clang/test/CIR/CodeGen/coro-task.cpp +++ b/clang/test/CIR/CodeGen/coro-task.cpp @@ -173,7 +173,7 @@ VoidTask silly_task() { // CIR: cir.store{{.*}} %[[NullPtr]], %[[SavedFrameAddr]] : !cir.ptr, !cir.ptr> // CIR: cir.if %[[ShouldAlloc]] { // CIR: %[[CoroSize:.*]] = cir.call @__builtin_coro_size() : () -> !u64i -// CIR: %[[AllocAddr:.*]] = cir.call @_Znwm(%[[CoroSize]]) : (!u64i) -> !cir.ptr +// CIR: %[[AllocAddr:.*]] = cir.call @_Znwm(%[[CoroSize]]) {allocsize = array} : (!u64i) -> !cir.ptr // CIR: cir.store{{.*}} %[[AllocAddr]], %[[SavedFrameAddr]] : !cir.ptr, !cir.ptr> // CIR: } // CIR: %[[Load0:.*]] = cir.load{{.*}} %[[SavedFrameAddr]] : !cir.ptr>, !cir.ptr diff --git a/clang/test/CIR/CodeGen/default-func-attrs-cmd-line.cpp b/clang/test/CIR/CodeGen/default-func-attrs-cmd-line.cpp new file mode 100644 index 0000000000000..df1e9fa7d9b18 --- /dev/null +++ b/clang/test/CIR/CodeGen/default-func-attrs-cmd-line.cpp @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -default-function-attr "key=value" -default-function-attr "just_key" -default-function-attr "key-2=1" -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -default-function-attr "key=value" -default-function-attr "just_key" -default-function-attr "key-2=1" -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -default-function-attr "key=value" -default-function-attr "just_key" -default-function-attr "key-2=1" -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM + +extern "C" { +// CIR: cir.func{{.*}}@func() attributes { +// CIR-SAME: default_func_attrs = {just_key, key = "value", "key-2" = "1"} +// LLVM: define{{.*}}@func() #[[FUNC_ATTRS:.*]] { +void func() {} + +void caller() { + func(); + // CIR: cir.call @func() + // CIR-SAME: default_func_attrs = {just_key, key = "value", "key-2" = "1"} + // LLVM: call void{{.*}}@func() #[[FUNC_CALL_ATTRS:.*]] +} +} + +// LLVM: attributes #[[FUNC_ATTRS]] = +// LLVM-SAME: "just_key" +// LLVM-SAME: "key"="value" +// LLVM-SAME: "key-2"="1" +// LLVM: attributes #[[FUNC_CALL_ATTRS]] = +// LLVM-SAME: "just_key" +// LLVM-SAME: "key"="value" +// LLVM-SAME: "key-2"="1" diff --git a/clang/test/CIR/CodeGen/integer-overflow.c b/clang/test/CIR/CodeGen/integer-overflow.c new file mode 100644 index 0000000000000..7054e086423ad --- /dev/null +++ b/clang/test/CIR/CodeGen/integer-overflow.c @@ -0,0 +1,124 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu %s -fclangir -emit-cir -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=DEFAULT-CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu %s -fclangir -emit-cir -o %t-wrapv.cir -fwrapv +// RUN: FileCheck --input-file=%t-wrapv.cir %s -check-prefix=WRAPV-CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu %s -fclangir -emit-llvm -o %t-cir.ll +// RUN: FileCheck --input-file=%t-cir.ll %s -check-prefix=DEFAULT-LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu %s -fclangir -emit-llvm -o %t-wrapv-cir.ll -fwrapv +// RUN: FileCheck --input-file=%t-wrapv-cir.ll %s -check-prefix=WRAPV-LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu %s -emit-llvm -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=DEFAULT-OGCG +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu %s -emit-llvm -o %t-wrapv.ll -fwrapv +// RUN: FileCheck --input-file=%t-wrapv.ll %s -check-prefix=WRAPV-OGCG + +// TODO(cir): These tests are copied from clang/test/CodeGen/integer-overflow.c. +// When support for sanitizers is implemented, it this test should be updated +// to add sanitizer checks. + +// Tests for signed integer overflow stuff. +void test1(void) { + extern volatile int f11G, a, b; + + // DEFAULT-CIR: cir.binop(add, {{.*}}, {{.*}}) nsw : !s32i + // DEFAULT-LLVM: add nsw i32 + // DEFAULT-OGCG: add nsw i32 + // WRAPV-CIR: cir.binop(add, {{.*}}, {{.*}}) : !s32i + // WRAPV-LLVM: add i32 + // WRAPV-OGCG: add i32 + f11G = a + b; + + // DEFAULT-CIR: cir.binop(sub, {{.*}}, {{.*}}) nsw : !s32i + // DEFAULT-LLVM: sub nsw i32 + // DEFAULT-OGCG: sub nsw i32 + // WRAPV-CIR: cir.binop(sub, {{.*}}, {{.*}}) : !s32i + // WRAPV-LLVM: sub i32 + // WRAPV-OGCG: sub i32 + f11G = a - b; + + // DEFAULT-CIR: cir.binop(mul, {{.*}}, {{.*}}) nsw : !s32i + // DEFAULT-LLVM: mul nsw i32 + // DEFAULT-OGCG: mul nsw i32 + // WRAPV-CIR: cir.binop(mul, {{.*}}, {{.*}}) : !s32i + // WRAPV-LLVM: mul i32 + // WRAPV-OGCG: mul i32 + f11G = a * b; + + // DEFAULT-CIR: cir.unary(minus, {{.*}}) nsw : !s32i + // DEFAULT-LLVM: sub nsw i32 0, + // DEFAULT-OGCG: sub nsw i32 0, + // WRAPV-CIR: cir.unary(minus, {{.*}}) : !s32i + // WRAPV-LLVM: sub i32 0, + // WRAPV-OGCG: sub i32 0, + f11G = -a; + + // PR7426 - Overflow checking for increments. + + // DEFAULT-CIR: cir.unary(inc, {{.*}}) nsw : !s32i + // DEFAULT-LLVM: add nsw i32 {{.*}}, 1 + // DEFAULT-OGCG: add nsw i32 {{.*}}, 1 + // WRAPV-CIR: cir.unary(inc, {{.*}}) : !s32i + // WRAPV-LLVM: add i32 {{.*}}, 1 + // WRAPV-OGCG: add i32 {{.*}}, 1 + ++a; + + // DEFAULT-CIR: cir.unary(dec, {{.*}}) nsw : !s32i + // DEFAULT-LLVM: sub nsw i32 {{.*}}, 1 + // DEFAULT-OGCG: add nsw i32 {{.*}}, -1 + // WRAPV-CIR: cir.unary(dec, {{.*}}) : !s32i + // WRAPV-LLVM: sub i32 {{.*}}, 1 + // WRAPV-OGCG: add i32 {{.*}}, -1 + --a; + + // -fwrapv does not affect inbounds for GEP's. + // This is controlled by -fwrapv-pointer instead. + extern int* P; + ++P; + // DEFAULT-CIR: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i + // DEFAULT-CIR: cir.ptr_stride {{.*}}, %[[ONE]] + // DEFAULT-LLVM: getelementptr i32, ptr %{{.*}}, i64 1 + // DEFAULT-OGCG: getelementptr inbounds nuw i32, ptr + // WRAPV-CIR: %[[ONE:.*]] = cir.const #cir.int<1> : !s32i + // WRAPV-CIR: cir.ptr_stride {{.*}}, %[[ONE]] + // WRAPV-LLVM: getelementptr i32, ptr %{{.*}}, i64 1 + // WRAPV-OGCG: getelementptr inbounds nuw i32, ptr + + // PR9350: char pre-increment never overflows. + extern volatile signed char PR9350_char_inc; + // DEFAULT-CIR: cir.unary(inc, {{.*}}) : !s8i + // DEFAULT-LLVM: add i8 {{.*}}, 1 + // DEFAULT-OGCG: add i8 {{.*}}, 1 + // WRAPV-CIR: cir.unary(inc, {{.*}}) : !s8i + // WRAPV-LLVM: add i8 {{.*}}, 1 + // WRAPV-OGCG: add i8 {{.*}}, 1 + ++PR9350_char_inc; + + // PR9350: char pre-decrement never overflows. + extern volatile signed char PR9350_char_dec; + // DEFAULT-CIR: cir.unary(dec, {{.*}}) : !s8i + // DEFAULT-LLVM: sub i8 {{.*}}, 1 + // DEFAULT-OGCG: add i8 {{.*}}, -1 + // WRAPV-CIR: cir.unary(dec, {{.*}}) : !s8i + // WRAPV-LLVM: sub i8 {{.*}}, 1 + // WRAPV-OGCG: add i8 {{.*}}, -1 + --PR9350_char_dec; + + // PR9350: short pre-increment never overflows. + extern volatile signed short PR9350_short_inc; + // DEFAULT-CIR: cir.unary(inc, {{.*}}) : !s16i + // DEFAULT-LLVM: add i16 {{.*}}, 1 + // DEFAULT-OGCG: add i16 {{.*}}, 1 + // WRAPV-CIR: cir.unary(inc, {{.*}}) : !s16i + // WRAPV-LLVM: add i16 {{.*}}, 1 + // WRAPV-OGCG: add i16 {{.*}}, 1 + ++PR9350_short_inc; + + // PR9350: short pre-decrement never overflows. + extern volatile signed short PR9350_short_dec; + // DEFAULT-CIR: cir.unary(dec, {{.*}}) : !s16i + // DEFAULT-LLVM: sub i16 {{.*}}, 1 + // DEFAULT-OGCG: add i16 {{.*}}, -1 + // WRAPV-CIR: cir.unary(dec, {{.*}}) : !s16i + // WRAPV-LLVM: sub i16 {{.*}}, 1 + // WRAPV-OGCG: add i16 {{.*}}, -1 + --PR9350_short_dec; +} diff --git a/clang/test/CIR/CodeGen/new.cpp b/clang/test/CIR/CodeGen/new.cpp index 80a4b476226af..dfdd4d25c5f87 100644 --- a/clang/test/CIR/CodeGen/new.cpp +++ b/clang/test/CIR/CodeGen/new.cpp @@ -5,6 +5,8 @@ // RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll // RUN: FileCheck --check-prefix=OGCG --input-file=%t.ll %s +typedef __typeof__(sizeof(int)) size_t; + struct S { int a; int b; @@ -160,7 +162,7 @@ void test_new_with_complex_type() { // CHECK: cir.func{{.*}} @_Z26test_new_with_complex_typev // CHECK: %[[A_ADDR:.*]] = cir.alloca !cir.ptr>, !cir.ptr>>, ["a", init] // CHECK: %[[COMPLEX_SIZE:.*]] = cir.const #cir.int<8> : !u64i -// CHECK: %[[NEW_COMPLEX:.*]] = cir.call @_Znwm(%[[COMPLEX_SIZE]]) : (!u64i) -> !cir.ptr +// CHECK: %[[NEW_COMPLEX:.*]] = cir.call @_Znwm(%[[COMPLEX_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr // CHECK: %[[COMPLEX_PTR:.*]] = cir.cast bitcast %[[NEW_COMPLEX]] : !cir.ptr -> !cir.ptr> // CHECK: %[[COMPLEX_VAL:.*]] = cir.const #cir.const_complex<#cir.fp<1.000000e+00> : !cir.float, #cir.fp<2.000000e+00> : !cir.float> : !cir.complex // CHECK: cir.store{{.*}} %[[COMPLEX_VAL]], %[[COMPLEX_PTR]] : !cir.complex, !cir.ptr> @@ -187,8 +189,8 @@ void t_new_constant_size() { // CHECK: cir.func{{.*}} @_Z19t_new_constant_sizev() // CHECK: %[[P_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["p", init] {alignment = 8 : i64} -// CHECK: %[[#ALLOCATION_SIZE:]] = cir.const #cir.int<128> : !u64i -// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[#ALLOCATION_SIZE]]) : (!u64i) -> !cir.ptr +// CHECK: %[[ALLOCATION_SIZE:.*]] = cir.const #cir.int<128> : !u64i +// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[ALLOCATION_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr // CHECK: %[[TYPED_PTR:.*]] = cir.cast bitcast %[[RAW_PTR]] : !cir.ptr -> !cir.ptr // CHECK: cir.store align(8) %[[TYPED_PTR]], %[[P_ADDR]] : !cir.ptr, !cir.ptr> // CHECK: cir.return @@ -215,14 +217,14 @@ void t_constant_size_nontrivial() { // CHECK: cir.func{{.*}} @_Z26t_constant_size_nontrivialv() // CHECK: %[[P_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["p", init] {alignment = 8 : i64} -// CHECK: %[[#NUM_ELEMENTS:]] = cir.const #cir.int<3> : !u64i -// CHECK: %[[#ALLOCATION_SIZE:]] = cir.const #cir.int<11> : !u64i -// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[#ALLOCATION_SIZE]]) : (!u64i) -> !cir.ptr +// CHECK: %[[NUM_ELEMENTS:.*]] = cir.const #cir.int<3> : !u64i +// CHECK: %[[ALLOCATION_SIZE:.*]] = cir.const #cir.int<11> : !u64i +// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[ALLOCATION_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr // CHECK: %[[COOKIE_PTR_BASE:.*]] = cir.cast bitcast %[[RAW_PTR]] : !cir.ptr -> !cir.ptr> // CHECK: %[[COOKIE_PTR:.*]] = cir.cast bitcast %[[COOKIE_PTR_BASE]] : !cir.ptr> -> !cir.ptr -// CHECK: cir.store align(8) %[[#NUM_ELEMENTS]], %[[COOKIE_PTR]] : !u64i, !cir.ptr -// CHECK: %[[#COOKIE_SIZE:]] = cir.const #cir.int<8> : !s32i -// CHECK: %[[DATA_PTR_RAW:.*]] = cir.ptr_stride %[[COOKIE_PTR_BASE]], %[[#COOKIE_SIZE]] : (!cir.ptr>, !s32i) -> !cir.ptr> +// CHECK: cir.store align(8) %[[NUM_ELEMENTS]], %[[COOKIE_PTR]] : !u64i, !cir.ptr +// CHECK: %[[COOKIE_SIZE:.*]] = cir.const #cir.int<8> : !s32i +// CHECK: %[[DATA_PTR_RAW:.*]] = cir.ptr_stride %[[COOKIE_PTR_BASE]], %[[COOKIE_SIZE]] : (!cir.ptr>, !s32i) -> !cir.ptr> // CHECK: %[[DATA_PTR_VOID:.*]] = cir.cast bitcast %[[DATA_PTR_RAW]] : !cir.ptr> -> !cir.ptr // CHECK: %[[DATA_PTR:.*]] = cir.cast bitcast %[[DATA_PTR_VOID]] : !cir.ptr -> !cir.ptr // CHECK: cir.store align(8) %[[DATA_PTR]], %[[P_ADDR]] : !cir.ptr, !cir.ptr> @@ -255,14 +257,14 @@ void t_constant_size_nontrivial2() { // CHECK: cir.func{{.*}} @_Z27t_constant_size_nontrivial2v() // CHECK: %[[P_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["p", init] {alignment = 8 : i64} -// CHECK: %[[#NUM_ELEMENTS:]] = cir.const #cir.int<3> : !u64i -// CHECK: %[[#ALLOCATION_SIZE:]] = cir.const #cir.int<20> : !u64i -// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[#ALLOCATION_SIZE]]) : (!u64i) -> !cir.ptr +// CHECK: %[[NUM_ELEMENTS:.*]] = cir.const #cir.int<3> : !u64i +// CHECK: %[[ALLOCATION_SIZE:.*]] = cir.const #cir.int<20> : !u64i +// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[ALLOCATION_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr // CHECK: %[[COOKIE_PTR_BASE:.*]] = cir.cast bitcast %[[RAW_PTR]] : !cir.ptr -> !cir.ptr> // CHECK: %[[COOKIE_PTR:.*]] = cir.cast bitcast %[[COOKIE_PTR_BASE]] : !cir.ptr> -> !cir.ptr -// CHECK: cir.store align(8) %[[#NUM_ELEMENTS]], %[[COOKIE_PTR]] : !u64i, !cir.ptr -// CHECK: %[[#COOKIE_SIZE:]] = cir.const #cir.int<8> : !s32i -// CHECK: %[[DATA_PTR_RAW:.*]] = cir.ptr_stride %[[COOKIE_PTR_BASE]], %[[#COOKIE_SIZE]] : (!cir.ptr>, !s32i) -> !cir.ptr> +// CHECK: cir.store align(8) %[[NUM_ELEMENTS]], %[[COOKIE_PTR]] : !u64i, !cir.ptr +// CHECK: %[[COOKIE_SIZE:.*]] = cir.const #cir.int<8> : !s32i +// CHECK: %[[DATA_PTR_RAW:.*]] = cir.ptr_stride %[[COOKIE_PTR_BASE]], %[[COOKIE_SIZE]] : (!cir.ptr>, !s32i) -> !cir.ptr> // CHECK: %[[DATA_PTR_VOID:.*]] = cir.cast bitcast %[[DATA_PTR_RAW]] : !cir.ptr> -> !cir.ptr // CHECK: %[[DATA_PTR:.*]] = cir.cast bitcast %[[DATA_PTR_VOID]] : !cir.ptr -> !cir.ptr // CHECK: cir.store align(8) %[[DATA_PTR]], %[[P_ADDR]] : !cir.ptr, !cir.ptr> @@ -287,16 +289,16 @@ void t_align16_nontrivial() { // CHECK: cir.func{{.*}} @_Z20t_align16_nontrivialv() // CHECK: %[[P_ADDR:.*]] = cir.alloca !cir.ptr, !cir.ptr>, ["p", init] {alignment = 8 : i64} -// CHECK: %[[#NUM_ELEMENTS:]] = cir.const #cir.int<2> : !u64i -// CHECK: %[[#ALLOCATION_SIZE:]] = cir.const #cir.int<48> : !u64i -// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[#ALLOCATION_SIZE]]) : (!u64i) -> !cir.ptr +// CHECK: %[[NUM_ELEMENTS:.*]] = cir.const #cir.int<2> : !u64i +// CHECK: %[[ALLOCATION_SIZE:.*]] = cir.const #cir.int<48> : !u64i +// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[ALLOCATION_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr // CHECK: %[[COOKIE_PTR_BASE:.*]] = cir.cast bitcast %[[RAW_PTR]] : !cir.ptr -> !cir.ptr> // CHECK: %[[COOKIE_OFFSET:.*]] = cir.const #cir.int<8> : !s32i // CHECK: %[[COOKIE_PTR_RAW:.*]] = cir.ptr_stride %[[COOKIE_PTR_BASE]], %[[COOKIE_OFFSET]] : (!cir.ptr>, !s32i) -> !cir.ptr> // CHECK: %[[COOKIE_PTR:.*]] = cir.cast bitcast %[[COOKIE_PTR_RAW]] : !cir.ptr> -> !cir.ptr -// CHECK: cir.store align(8) %[[#NUM_ELEMENTS]], %[[COOKIE_PTR]] : !u64i, !cir.ptr -// CHECK: %[[#COOKIE_SIZE:]] = cir.const #cir.int<16> : !s32i -// CHECK: %[[DATA_PTR_RAW:.*]] = cir.ptr_stride %[[COOKIE_PTR_BASE]], %[[#COOKIE_SIZE]] : (!cir.ptr>, !s32i) -> !cir.ptr> +// CHECK: cir.store align(8) %[[NUM_ELEMENTS]], %[[COOKIE_PTR]] : !u64i, !cir.ptr +// CHECK: %[[COOKIE_SIZE:.*]] = cir.const #cir.int<16> : !s32i +// CHECK: %[[DATA_PTR_RAW:.*]] = cir.ptr_stride %[[COOKIE_PTR_BASE]], %[[COOKIE_SIZE]] : (!cir.ptr>, !s32i) -> !cir.ptr> // CHECK: %[[DATA_PTR_VOID:.*]] = cir.cast bitcast %[[DATA_PTR_RAW]] : !cir.ptr> -> !cir.ptr // CHECK: %[[DATA_PTR:.*]] = cir.cast bitcast %[[DATA_PTR_VOID]] : !cir.ptr -> !cir.ptr // CHECK: cir.store align(8) %[[DATA_PTR]], %[[P_ADDR]] : !cir.ptr, !cir.ptr> @@ -324,10 +326,10 @@ void t_new_multidim_constant_size() { auto p = new double[2][3][4]; } -// CHECK: cir.func{{.*}} @_Z28t_new_multidim_constant_sizev() +// CHECK: cir.func{{.*}} @_Z28t_new_multidim_constant_sizev() // CHECK: %[[P_ADDR:.*]] = cir.alloca !cir.ptr x 3>>, !cir.ptr x 3>>>, ["p", init] {alignment = 8 : i64} -// CHECK: %[[#ALLOCATION_SIZE:]] = cir.const #cir.int<192> : !u64i -// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[#ALLOCATION_SIZE]]) : (!u64i) -> !cir.ptr +// CHECK: %[[ALLOCATION_SIZE:.*]] = cir.const #cir.int<192> : !u64i +// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[ALLOCATION_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr // CHECK: %[[TYPED_PTR:.*]] = cir.cast bitcast %[[RAW_PTR]] : !cir.ptr -> !cir.ptr x 3>> // CHECK: cir.store align(8) %[[TYPED_PTR]], %[[P_ADDR]] : !cir.ptr x 3>>, !cir.ptr x 3>>> // CHECK: } @@ -341,3 +343,387 @@ void t_new_multidim_constant_size() { // OGCG: %[[P_ADDR:.*]] = alloca ptr, align 8 // OGCG: %[[CALL:.*]] = call noalias noundef nonnull ptr @_Znam(i64 noundef 192) // OGCG: store ptr %[[CALL]], ptr %[[P_ADDR]], align 8 + +void t_constant_size_memset_init() { + auto p = new int[16] {}; +} + +// CHECK: cir.func {{.*}} @_Z27t_constant_size_memset_initv() +// CHECK: %[[ALLOCATION_SIZE:.*]] = cir.const #cir.int<64> : !u64i +// CHECK: %[[ALLOC_PTR:.*]] = cir.call @_Znam(%[[ALLOCATION_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr +// CHECK: %[[ELEM_PTR:.*]] = cir.cast bitcast %[[ALLOC_PTR]] : !cir.ptr -> !cir.ptr +// CHECK: %[[VOID_PTR:.*]] = cir.cast bitcast %[[ELEM_PTR]] : !cir.ptr -> !cir.ptr +// CHECK: %[[ZERO:.*]] = cir.const #cir.int<0> : !u8i +// CHECK: cir.libc.memset %[[ALLOCATION_SIZE]] bytes at %[[VOID_PTR]] to %[[ZERO]] : !cir.ptr, !u8i, !u64i + +// LLVM: define {{.*}} void @_Z27t_constant_size_memset_initv() +// LLVM: %[[P:.*]] = call ptr @_Znam(i64 64) +// LLVM: call void @llvm.memset.p0.i64(ptr %[[P]], i8 0, i64 64, i1 false) + +// OGCG: define {{.*}} void @_Z27t_constant_size_memset_initv() +// OGCG: %[[P:.*]] = call{{.*}} ptr @_Znam(i64{{.*}} 64) +// OGCG: call void @llvm.memset.p0.i64(ptr{{.*}} %[[P]], i8 0, i64 64, i1 false) + +void t_constant_size_full_init() { + auto p = new int[4] { 1, 2, 3, 4 }; +} + +// CHECK: cir.func {{.*}} @_Z25t_constant_size_full_initv() +// CHECK: %[[ALLOCATION_SIZE:.*]] = cir.const #cir.int<16> : !u64i +// CHECK: %[[ALLOC_PTR:.*]] = cir.call @_Znam(%[[ALLOCATION_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr +// CHECK: %[[ELEM_0_PTR:.*]] = cir.cast bitcast %[[ALLOC_PTR]] : !cir.ptr -> !cir.ptr +// CHECK: %[[CONST_ONE:.*]] = cir.const #cir.int<1> : !s32i +// CHECK: cir.store{{.*}} %[[CONST_ONE]], %[[ELEM_0_PTR]] : !s32i, !cir.ptr +// CHECK: %[[OFFSET:.*]] = cir.const #cir.int<1> : !s32i +// CHECK: %[[ELEM_1_PTR:.*]] = cir.ptr_stride %[[ELEM_0_PTR]], %[[OFFSET]] : (!cir.ptr, !s32i) -> !cir.ptr +// CHECK: %[[CONST_TWO:.*]] = cir.const #cir.int<2> : !s32i +// CHECK: cir.store{{.*}} %[[CONST_TWO]], %[[ELEM_1_PTR]] : !s32i, !cir.ptr +// CHECK: %[[OFFSET1:.*]] = cir.const #cir.int<1> : !s32i +// CHECK: %[[ELEM_2_PTR:.*]] = cir.ptr_stride %[[ELEM_1_PTR]], %[[OFFSET1]] : (!cir.ptr, !s32i) -> !cir.ptr +// CHECK: %[[CONST_THREE:.*]] = cir.const #cir.int<3> : !s32i +// CHECK: cir.store{{.*}} %[[CONST_THREE]], %[[ELEM_2_PTR]] : !s32i, !cir.ptr +// CHECK: %[[OFFSET2:.*]] = cir.const #cir.int<1> : !s32i +// CHECK: %[[ELEM_3_PTR:.*]] = cir.ptr_stride %[[ELEM_2_PTR]], %[[OFFSET2]] : (!cir.ptr, !s32i) -> !cir.ptr +// CHECK: %[[CONST_FOUR:.*]] = cir.const #cir.int<4> : !s32i +// CHECK: cir.store{{.*}} %[[CONST_FOUR]], %[[ELEM_3_PTR]] : !s32i, !cir.ptr + +// LLVM: define {{.*}} void @_Z25t_constant_size_full_initv() +// LLVM: %[[P:.*]] = call ptr @_Znam(i64 16) +// LLVM: store i32 1, ptr %[[CALL]] +// LLVM: %[[ELEM_1:.*]] = getelementptr i32, ptr %[[P]], i64 1 +// LLVM: store i32 2, ptr %[[ELEM_1]] +// LLVM: %[[ELEM_2:.*]] = getelementptr i32, ptr %[[ELEM_1]], i64 1 +// LLVM: store i32 3, ptr %[[ELEM_2]] +// LLVM: %[[ELEM_3:.*]] = getelementptr i32, ptr %[[ELEM_2]], i64 1 +// LLVM: store i32 4, ptr %[[ELEM_3]] + +// OGCG: define {{.*}} void @_Z25t_constant_size_full_initv() +// OGCG: %[[P:.*]] = call{{.*}} ptr @_Znam(i64{{.*}} 16) +// OGCG: store i32 1, ptr %[[P]] +// OGCG: %[[ELEM_1:.*]] = getelementptr inbounds i32, ptr %[[P]], i64 1 +// OGCG: store i32 2, ptr %[[ELEM_1]] +// OGCG: %[[ELEM_2:.*]] = getelementptr inbounds i32, ptr %[[ELEM_1]], i64 1 +// OGCG: store i32 3, ptr %[[ELEM_2]] +// OGCG: %[[ELEM_3:.*]] = getelementptr inbounds i32, ptr %[[ELEM_2]], i64 1 +// OGCG: store i32 4, ptr %[[ELEM_3]] + +void t_constant_size_partial_init() { + auto p = new int[16] { 1, 2, 3 }; +} + +// CHECK: cir.func {{.*}} @_Z28t_constant_size_partial_initv() +// CHECK: %[[ALLOCATION_SIZE:.*]] = cir.const #cir.int<64> : !u64i +// CHECK: %[[ALLOC_PTR:.*]] = cir.call @_Znam(%[[ALLOCATION_SIZE]]) {allocsize = array} : (!u64i) -> !cir.ptr +// CHECK: %[[ELEM_0_PTR:.*]] = cir.cast bitcast %[[ALLOC_PTR]] : !cir.ptr -> !cir.ptr +// CHECK: %[[CONST_ONE:.*]] = cir.const #cir.int<1> : !s32i +// CHECK: cir.store{{.*}} %[[CONST_ONE]], %[[ELEM_0_PTR]] : !s32i, !cir.ptr +// CHECK: %[[OFFSET:.*]] = cir.const #cir.int<1> : !s32i +// CHECK: %[[ELEM_1_PTR:.*]] = cir.ptr_stride %[[ELEM_0_PTR]], %[[OFFSET]] : (!cir.ptr, !s32i) -> !cir.ptr +// CHECK: %[[CONST_TWO:.*]] = cir.const #cir.int<2> : !s32i +// CHECK: cir.store{{.*}} %[[CONST_TWO]], %[[ELEM_1_PTR]] : !s32i, !cir.ptr +// CHECK: %[[OFFSET1:.*]] = cir.const #cir.int<1> : !s32i +// CHECK: %[[ELEM_2_PTR:.*]] = cir.ptr_stride %[[ELEM_1_PTR]], %[[OFFSET1]] : (!cir.ptr, !s32i) -> !cir.ptr +// CHECK: %[[CONST_THREE:.*]] = cir.const #cir.int<3> : !s32i +// CHECK: cir.store{{.*}} %[[CONST_THREE]], %[[ELEM_2_PTR]] : !s32i, !cir.ptr +// CHECK: %[[OFFSET2:.*]] = cir.const #cir.int<1> : !s32i +// CHECK: %[[ELEM_3_PTR:.*]] = cir.ptr_stride %[[ELEM_2_PTR]], %[[OFFSET2]] : (!cir.ptr, !s32i) -> !cir.ptr +// CHECK: %[[INIT_SIZE:.*]] = cir.const #cir.int<12> : !u64i +// CHECK: %[[REMAINING_SIZE:.*]] = cir.binop(sub, %[[ALLOCATION_SIZE]], %[[INIT_SIZE]]) : !u64i +// CHECK: %[[VOID_PTR:.*]] = cir.cast bitcast %[[ELEM_3_PTR]] : !cir.ptr -> !cir.ptr +// CHECK: %[[ZERO:.*]] = cir.const #cir.int<0> : !u8i +// CHECK: cir.libc.memset %[[REMAINING_SIZE]] bytes at %[[VOID_PTR]] to %[[ZERO]] : !cir.ptr, !u8i, !u64i + +// LLVM: define {{.*}} void @_Z28t_constant_size_partial_initv() +// LLVM: %[[P:.*]] = call ptr @_Znam(i64 64) +// LLVM: store i32 1, ptr %[[P]] +// LLVM: %[[ELEM_1:.*]] = getelementptr i32, ptr %[[P]], i64 1 +// LLVM: store i32 2, ptr %[[ELEM_1]] +// LLVM: %[[ELEM_2:.*]] = getelementptr i32, ptr %[[ELEM_1]], i64 1 +// LLVM: store i32 3, ptr %[[ELEM_2]] +// LLVM: %[[ELEM_3:.*]] = getelementptr i32, ptr %[[ELEM_2]], i64 1 +// LLVM: call void @llvm.memset.p0.i64(ptr %[[ELEM_3]], i8 0, i64 52, i1 false) + +// OGCG: define {{.*}} void @_Z28t_constant_size_partial_initv() +// OGCG: %[[P:.*]] = call{{.*}} ptr @_Znam(i64{{.*}} 64) +// OGCG: store i32 1, ptr %[[P]] +// OGCG: %[[ELEM_1:.*]] = getelementptr inbounds i32, ptr %[[P]], i64 1 +// OGCG: store i32 2, ptr %[[ELEM_1]] +// OGCG: %[[ELEM_2:.*]] = getelementptr inbounds i32, ptr %[[ELEM_1]], i64 1 +// OGCG: store i32 3, ptr %[[ELEM_2]] +// OGCG: %[[ELEM_3:.*]] = getelementptr inbounds i32, ptr %[[ELEM_2]], i64 1 +// OGCG: call void @llvm.memset.p0.i64(ptr{{.*}} %[[ELEM_3]], i8 0, i64 52, i1 false) + +void t_new_var_size(size_t n) { + auto p = new char[n]; +} + +// CHECK: cir.func {{.*}} @_Z14t_new_var_sizem +// CHECK: %[[N:.*]] = cir.load{{.*}} %[[ARG_ALLOCA:.*]] +// CHECK: %[[PTR:.*]] = cir.call @_Znam(%[[N]]) {allocsize = array} : (!u64i) + +// LLVM: define{{.*}} void @_Z14t_new_var_sizem +// LLVM: %[[N:.*]] = load i64, ptr %{{.+}} +// LLVM: %[[PTR:.*]] = call ptr @_Znam(i64 %[[N]]) + +// OGCG: define{{.*}} void @_Z14t_new_var_sizem +// OGCG: %[[N:.*]] = load i64, ptr %{{.+}} +// OGCG: %[[PTR:.*]] = call {{.*}} ptr @_Znam(i64 {{.*}} %[[N]]) + +void t_new_var_size2(int n) { + auto p = new char[n]; +} + +// CHECK: cir.func {{.*}} @_Z15t_new_var_size2i +// CHECK: %[[N:.*]] = cir.load{{.*}} %[[ARG_ALLOCA:.*]] +// CHECK: %[[N_SIZE_T:.*]] = cir.cast integral %[[N]] : !s32i -> !u64i +// CHECK: %[[PTR:.*]] = cir.call @_Znam(%[[N_SIZE_T]]) {allocsize = array} : (!u64i) + +// LLVM: define{{.*}} void @_Z15t_new_var_size2i +// LLVM: %[[N:.*]] = load i32, ptr %{{.+}} +// LLVM: %[[N_SIZE_T:.*]] = sext i32 %[[N]] to i64 +// LLVM: %[[PTR:.*]] = call ptr @_Znam(i64 %[[N_SIZE_T]]) + +// OGCG: define{{.*}} void @_Z15t_new_var_size2i +// OGCG: %[[N:.*]] = load i32, ptr %{{.+}} +// OGCG: %[[N_SIZE_T:.*]] = sext i32 %[[N]] to i64 +// OGCG: %[[PTR:.*]] = call {{.*}} ptr @_Znam(i64 {{.*}} %[[N_SIZE_T]]) + +void t_new_var_size3(size_t n) { + auto p = new double[n]; +} + +// CHECK: cir.func {{.*}} @_Z15t_new_var_size3m +// CHECK: %[[N:.*]] = cir.load{{.*}} %[[ARG_ALLOCA:.*]] +// CHECK: %[[ELEMENT_SIZE:.*]] = cir.const #cir.int<8> : !u64i +// CHECK: %[[RESULT:.*]], %[[OVERFLOW:.*]] = cir.binop.overflow(mul, %[[N]], %[[ELEMENT_SIZE]]) : !u64i, (!u64i, !cir.bool) +// CHECK: %[[ALL_ONES:.*]] = cir.const #cir.int<18446744073709551615> : !u64i +// CHECK: %[[ALLOC_SIZE:.*]] = cir.select if %[[OVERFLOW]] then %[[ALL_ONES]] else %[[RESULT]] : (!cir.bool, !u64i, !u64i) +// CHECK: %[[PTR:.*]] = cir.call @_Znam(%[[ALLOC_SIZE]]) {allocsize = array} : (!u64i) + +// LLVM: define{{.*}} void @_Z15t_new_var_size3m +// LLVM: %[[N:.*]] = load i64, ptr %{{.+}} +// LLVM: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N]], i64 8) +// LLVM: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// LLVM: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// LLVM: %[[ALLOC_SIZE:.*]] = select i1 %[[OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// LLVM: %[[RESULT:.*]] = call ptr @_Znam(i64 %[[ALLOC_SIZE]]) + +// OGCG: define{{.*}} void @_Z15t_new_var_size3m +// OGCG: %[[N:.*]] = load i64, ptr %{{.+}} +// OGCG: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N]], i64 8) +// OGCG: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// OGCG: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// OGCG: %[[ALLOC_SIZE:.*]] = select i1 %[[OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// OGCG: %[[PTR:.*]] = call {{.*}} ptr @_Znam(i64 {{.*}} %[[ALLOC_SIZE]]) + +void t_new_var_size4(int n) { + auto p = new double[n]; +} + +// CHECK: cir.func {{.*}} @_Z15t_new_var_size4i +// CHECK: %[[N:.*]] = cir.load{{.*}} %[[ARG_ALLOCA:.*]] +// CHECK: %[[N_SIZE_T:.*]] = cir.cast integral %[[N]] : !s32i -> !u64i +// CHECK: %[[ELEMENT_SIZE:.*]] = cir.const #cir.int<8> : !u64i +// CHECK: %[[RESULT:.*]], %[[OVERFLOW:.*]] = cir.binop.overflow(mul, %[[N_SIZE_T]], %[[ELEMENT_SIZE]]) : !u64i, (!u64i, !cir.bool) +// CHECK: %[[ALL_ONES:.*]] = cir.const #cir.int<18446744073709551615> : !u64i +// CHECK: %[[ALLOC_SIZE:.*]] = cir.select if %[[OVERFLOW]] then %[[ALL_ONES]] else %[[RESULT]] : (!cir.bool, !u64i, !u64i) +// CHECK: %[[PTR:.*]] = cir.call @_Znam(%[[ALLOC_SIZE]]) {allocsize = array} : (!u64i) + +// LLVM: define{{.*}} void @_Z15t_new_var_size4i +// LLVM: %[[N:.*]] = load i32, ptr %{{.+}} +// LLVM: %[[N_SIZE_T:.*]] = sext i32 %[[N]] to i64 +// LLVM: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N_SIZE_T]], i64 8) +// LLVM: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// LLVM: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// LLVM: %[[ALLOC_SIZE:.*]] = select i1 %[[OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// LLVM: %[[PTR:.*]] = call ptr @_Znam(i64 %[[ALLOC_SIZE]]) + +// OGCG: define{{.*}} void @_Z15t_new_var_size4i +// OGCG: %[[N:.*]] = load i32, ptr %{{.+}} +// OGCG: %[[N_SIZE_T:.*]] = sext i32 %[[N]] to i64 +// OGCG: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N_SIZE_T]], i64 8) +// OGCG: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// OGCG: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// OGCG: %[[ALLOC_SIZE:.*]] = select i1 %[[OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// OGCG: %[[PTR:.*]] = call {{.*}} ptr @_Znam(i64 {{.*}} %[[ALLOC_SIZE]]) + +void t_new_var_size5(int n) { + auto p = new double[n][2][3]; +} + +// NUM_ELEMENTS isn't used in this case because there is no cookie. It isn't +// used in the allocation size because the allocation size is calculated with +// the element size and the fixed size dimensions already combined (6 * 8 = 48). +// We don't DCE NUM_ELEMENTS because it's not a constant, but later +// optimizations will eliminate it. + +// CHECK: cir.func {{.*}} @_Z15t_new_var_size5i +// CHECK: %[[N:.*]] = cir.load{{.*}} %[[ARG_ALLOCA:.*]] +// CHECK: %[[N_SIZE_T:.*]] = cir.cast integral %[[N]] : !s32i -> !u64i +// CHECK: %[[ELEMENT_SIZE:.*]] = cir.const #cir.int<48> : !u64i +// CHECK: %[[RESULT:.*]], %[[OVERFLOW:.*]] = cir.binop.overflow(mul, %[[N_SIZE_T]], %[[ELEMENT_SIZE]]) : !u64i, (!u64i, !cir.bool) +// CHECK: %[[NUM_ELEMENTS_MULTIPLIER:.*]] = cir.const #cir.int<6> +// CHECK: %[[NUM_ELEMENTS:.*]] = cir.binop(mul, %[[N_SIZE_T]], %[[NUM_ELEMENTS_MULTIPLIER]]) : !u64i +// CHECK: %[[ALL_ONES:.*]] = cir.const #cir.int<18446744073709551615> : !u64i +// CHECK: %[[ALLOC_SIZE:.*]] = cir.select if %[[OVERFLOW]] then %[[ALL_ONES]] else %[[RESULT]] : (!cir.bool, !u64i, !u64i) +// CHECK: %[[PTR:.*]] = cir.call @_Znam(%[[ALLOC_SIZE]]) {allocsize = array} : (!u64i) + +// LLVM: define{{.*}} void @_Z15t_new_var_size5i +// LLVM: %[[N:.*]] = load i32, ptr %{{.+}} +// LLVM: %[[N_SIZE_T:.*]] = sext i32 %[[N]] to i64 +// LLVM: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N_SIZE_T]], i64 48) +// LLVM: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// LLVM: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// LLVM: %[[ALLOC_SIZE:.*]] = select i1 %[[OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// LLVM: %[[PTR:.*]] = call ptr @_Znam(i64 %[[ALLOC_SIZE]]) + +// OGCG: define{{.*}} void @_Z15t_new_var_size5i +// OGCG: %[[N:.*]] = load i32, ptr %{{.+}} +// OGCG: %[[N_SIZE_T:.*]] = sext i32 %[[N]] to i64 +// OGCG: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N_SIZE_T]], i64 48) +// OGCG: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// OGCG: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// OGCG: %[[ALLOC_SIZE:.*]] = select i1 %[[OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// OGCG: %[[PTR:.*]] = call {{.*}} ptr @_Znam(i64 {{.*}} %[[ALLOC_SIZE]]) + +void t_new_var_size6(int n) { + auto p = new double[n] { 1.0, 2.0, 3.0 }; +} + +// CHECK: cir.func {{.*}} @_Z15t_new_var_size6i +// CHECK: %[[N:.*]] = cir.load{{.*}} %[[ARG_ALLOCA:.*]] +// CHECK: %[[N_SIZE_T:.*]] = cir.cast integral %[[N]] : !s32i -> !u64i +// CHECK: %[[MIN_SIZE:.*]] = cir.const #cir.int<3> : !u64i +// CHECK: %[[LT_MIN_SIZE:.*]] = cir.cmp(lt, %[[N_SIZE_T]], %[[MIN_SIZE]]) : !u64i, !cir.bool +// CHECK: %[[ELEMENT_SIZE:.*]] = cir.const #cir.int<8> : !u64i +// CHECK: %[[RESULT:.*]], %[[OVERFLOW:.*]] = cir.binop.overflow(mul, %[[N_SIZE_T]], %[[ELEMENT_SIZE]]) : !u64i, (!u64i, !cir.bool) +// CHECK: %[[ANY_OVERFLOW:.*]] = cir.binop(or, %[[LT_MIN_SIZE]], %[[OVERFLOW]]) : !cir.bool +// CHECK: %[[ALL_ONES:.*]] = cir.const #cir.int<18446744073709551615> : !u64i +// CHECK: %[[ALLOC_SIZE:.*]] = cir.select if %[[ANY_OVERFLOW]] then %[[ALL_ONES]] else %[[RESULT]] : (!cir.bool, !u64i, !u64i) +// CHECK: %[[PTR:.*]] = cir.call @_Znam(%[[ALLOC_SIZE]]) {allocsize = array} : (!u64i) +// CHECK: %[[PTR_DOUBLE:.*]] = cir.cast bitcast %[[PTR]] : !cir.ptr -> !cir.ptr +// CHECK: %[[ELEM_0:.*]] = cir.const #cir.fp<1.000000e+00> : !cir.double +// CHECK: cir.store{{.*}} %[[ELEM_0]], %[[PTR_DOUBLE]] +// CHECK: %[[ONE:.*]] = cir.const #cir.int<1> +// CHECK: %[[PTR_DOUBLE_1:.*]] = cir.ptr_stride %[[PTR_DOUBLE]], %[[ONE]] +// CHECK: %[[ELEM_1:.*]] = cir.const #cir.fp<2.000000e+00> : !cir.double +// CHECK: cir.store{{.*}} %[[ELEM_1]], %[[PTR_DOUBLE_1]] +// CHECK: %[[ONE:.*]] = cir.const #cir.int<1> +// CHECK: %[[PTR_DOUBLE_2:.*]] = cir.ptr_stride %[[PTR_DOUBLE_1]], %[[ONE]] +// CHECK: %[[ELEM_2:.*]] = cir.const #cir.fp<3.000000e+00> : !cir.double +// CHECK: cir.store{{.*}} %[[ELEM_2]], %[[PTR_DOUBLE_2]] +// CHECK: %[[ONE:.*]] = cir.const #cir.int<1> +// CHECK: %[[PTR_DOUBLE_3:.*]] = cir.ptr_stride %[[PTR_DOUBLE_2]], %[[ONE]] +// CHECK: %[[INIT_SIZE:.*]] = cir.const #cir.int<24> : !u64i +// CHECK: %[[REMAINING_SIZE:.*]] = cir.binop(sub, %[[ALLOC_SIZE]], %[[INIT_SIZE]]) : !u64i +// CHECK: %[[PTR_DOUBLE_3_VOID:.*]] = cir.cast bitcast %[[PTR_DOUBLE_3]] : !cir.ptr -> !cir.ptr +// CHECK: %[[ZERO:.*]] = cir.const #cir.int<0> : !u8i +// CHECK: cir.libc.memset{{.*}} bytes at %[[PTR_DOUBLE_3_VOID]] to %[[ZERO]] + +// LLVM: define{{.*}} void @_Z15t_new_var_size6i +// LLVM: %[[N:.*]] = load i32, ptr %{{.+}} +// LLVM: %[[N_SIZE_T:.*]] = sext i32 %[[N]] to i64 +// LLVM: %[[LT_MIN_SIZE:.*]] = icmp ult i64 %[[N_SIZE_T]], 3 +// LLVM: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N_SIZE_T]], i64 8) +// LLVM: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// LLVM: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// LLVM: %[[ANY_OVERFLOW:.*]] = or i1 %[[LT_MIN_SIZE]], %[[OVERFLOW]] +// LLVM: %[[ALLOC_SIZE:.*]] = select i1 %[[ANY_OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// LLVM: %[[PTR:.*]] = call ptr @_Znam(i64 %[[ALLOC_SIZE]]) +// LLVM: store double 1.000000e+00, ptr %[[PTR]], align 8 +// LLVM: %[[ELEM_1:.*]] = getelementptr double, ptr %[[PTR]], i64 1 +// LLVM: store double 2.000000e+00, ptr %[[ELEM_1]], align 8 +// LLVM: %[[ELEM_2:.*]] = getelementptr double, ptr %[[ELEM_1]], i64 1 +// LLVM: store double 3.000000e+00, ptr %[[ELEM_2]], align 8 +// LLVM: %[[ELEM_3:.*]] = getelementptr double, ptr %[[ELEM_2]], i64 1 +// LLVM: %[[REMAINING_SIZE:.*]] = sub i64 %[[ALLOC_SIZE]], 24 +// LLVM: call void @llvm.memset.p0.i64(ptr %[[ELEM_3]], i8 0, i64 %[[REMAINING_SIZE]], i1 false) + +// OGCG: define{{.*}} void @_Z15t_new_var_size6i +// OGCG: %[[N:.*]] = load i32, ptr %{{.+}} +// OGCG: %[[N_SIZE_T:.*]] = sext i32 %[[N]] to i64 +// OGCG: %[[LT_MIN_SIZE:.*]] = icmp ult i64 %[[N_SIZE_T]], 3 +// OGCG: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N_SIZE_T]], i64 8) +// OGCG: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// OGCG: %[[ANY_OVERFLOW:.*]] = or i1 %[[LT_MIN_SIZE]], %[[OVERFLOW]] +// OGCG: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// OGCG: %[[ALLOC_SIZE:.*]] = select i1 %[[ANY_OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// OGCG: %[[PTR:.*]] = call {{.*}} ptr @_Znam(i64 {{.*}} %[[ALLOC_SIZE]]) +// OGCG: store double 1.000000e+00, ptr %[[PTR]], align 8 +// OGCG: %[[ELEM_1:.*]] = getelementptr inbounds double, ptr %[[PTR]], i64 1 +// OGCG: store double 2.000000e+00, ptr %[[ELEM_1]], align 8 +// OGCG: %[[ELEM_2:.*]] = getelementptr inbounds double, ptr %[[ELEM_1]], i64 1 +// OGCG: store double 3.000000e+00, ptr %[[ELEM_2]], align 8 +// OGCG: %[[ELEM_3:.*]] = getelementptr inbounds double, ptr %[[ELEM_2]], i64 1 +// OGCG: %[[REMAINING_SIZE:.*]] = sub i64 %[[ALLOC_SIZE]], 24 +// OGCG: call void @llvm.memset.p0.i64(ptr{{.*}} %[[ELEM_3]], i8 0, i64 %[[REMAINING_SIZE]], i1 false) + +void t_new_var_size7(__int128 n) { + auto p = new double[n]; +} + +// CHECK: cir.func {{.*}} @_Z15t_new_var_size7n +// CHECK: %[[N:.*]] = cir.load{{.*}} %[[ARG_ALLOCA:.*]] +// CHECK: %[[N_SIZE_T:.*]] = cir.cast integral %[[N]] : !s128i -> !u64i +// CHECK: %[[ELEMENT_SIZE:.*]] = cir.const #cir.int<8> : !u64i +// CHECK: %[[RESULT:.*]], %[[OVERFLOW:.*]] = cir.binop.overflow(mul, %[[N_SIZE_T]], %[[ELEMENT_SIZE]]) : !u64i, (!u64i, !cir.bool) +// CHECK: %[[ALL_ONES:.*]] = cir.const #cir.int<18446744073709551615> : !u64i +// CHECK: %[[ALLOC_SIZE:.*]] = cir.select if %[[OVERFLOW]] then %[[ALL_ONES]] else %[[RESULT]] : (!cir.bool, !u64i, !u64i) +// CHECK: %[[PTR:.*]] = cir.call @_Znam(%[[ALLOC_SIZE]]) {allocsize = array} : (!u64i) + +// LLVM: define{{.*}} void @_Z15t_new_var_size7n +// LLVM: %[[N:.*]] = load i128, ptr %{{.+}} +// LLVM: %[[N_SIZE_T:.*]] = trunc i128 %[[N]] to i64 +// LLVM: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N_SIZE_T]], i64 8) +// LLVM: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// LLVM: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// LLVM: %[[ALLOC_SIZE:.*]] = select i1 %[[OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// LLVM: %[[PTR:.*]] = call ptr @_Znam(i64 %[[ALLOC_SIZE]]) + +// OGCG: define{{.*}} void @_Z15t_new_var_size7n +// OGCG: %[[N:.*]] = load i128, ptr %{{.+}} +// OGCG: %[[N_SIZE_T:.*]] = trunc i128 %[[N]] to i64 +// OGCG: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N_SIZE_T]], i64 8) +// OGCG: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// OGCG: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// OGCG: %[[ALLOC_SIZE:.*]] = select i1 %[[OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// OGCG: %[[PTR:.*]] = call {{.*}} ptr @_Znam(i64 {{.*}} %[[ALLOC_SIZE]]) + +void t_new_var_size_nontrivial(size_t n) { + auto p = new D[n]; +} + +// CHECK: cir.func {{.*}} @_Z25t_new_var_size_nontrivialm +// CHECK: %[[N:.*]] = cir.load{{.*}} %[[ARG_ALLOCA:.*]] +// CHECK: %[[ELEMENT_SIZE:.*]] = cir.const #cir.int<4> : !u64i +// CHECK: %[[SIZE_WITHOUT_COOKIE:.*]], %[[OVERFLOW:.*]] = cir.binop.overflow(mul, %[[N]], %[[ELEMENT_SIZE]]) : !u64i, (!u64i, !cir.bool) +// CHECK: %[[COOKIE_SIZE:.*]] = cir.const #cir.int<8> : !u64i +// CHECK: %[[SIZE:.*]], %[[OVERFLOW2:.*]] = cir.binop.overflow(add, %[[SIZE_WITHOUT_COOKIE]], %[[COOKIE_SIZE]]) : !u64i, (!u64i, !cir.bool) +// CHECK: %[[ANY_OVERFLOW:.*]] = cir.binop(or, %[[OVERFLOW]], %[[OVERFLOW2]]) : !cir.bool +// CHECK: %[[ALL_ONES:.*]] = cir.const #cir.int<18446744073709551615> : !u64i +// CHECK: %[[ALLOC_SIZE:.*]] = cir.select if %[[ANY_OVERFLOW]] then %[[ALL_ONES]] else %[[SIZE]] : (!cir.bool, !u64i, !u64i) +// CHECK: %[[PTR:.*]] = cir.call @_Znam(%[[ALLOC_SIZE]]) {allocsize = array} : (!u64i) + +// LLVM: define{{.*}} void @_Z25t_new_var_size_nontrivialm +// LLVM: %[[N:.*]] = load i64, ptr %{{.+}} +// LLVM: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N]], i64 4) +// LLVM: %[[MUL_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// LLVM: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// LLVM: %[[ADD_OVERFLOW:.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %[[MUL_SIZE]], i64 8) +// LLVM: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[ADD_OVERFLOW]], 0 +// LLVM: %[[OVERFLOW_ADD:.*]] = extractvalue { i64, i1 } %[[ADD_OVERFLOW]], 1 +// LLVM: %[[ANY_OVERFLOW:.*]] = or i1 %[[OVERFLOW]], %[[OVERFLOW_ADD]] +// LLVM: %[[ALLOC_SIZE:.*]] = select i1 %[[ANY_OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// LLVM: %[[PTR:.*]] = call ptr @_Znam(i64 %[[ALLOC_SIZE]]) + +// OGCG: define{{.*}} void @_Z25t_new_var_size_nontrivialm +// OGCG: %[[N:.*]] = load i64, ptr %{{.+}} +// OGCG: %[[MUL_OVERFLOW:.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %[[N]], i64 4) +// OGCG: %[[OVERFLOW:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 1 +// OGCG: %[[MUL_SIZE:.*]] = extractvalue { i64, i1 } %[[MUL_OVERFLOW]], 0 +// OGCG: %[[ADD_OVERFLOW:.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %[[MUL_SIZE]], i64 8) +// OGCG: %[[OVERFLOW_ADD:.*]] = extractvalue { i64, i1 } %[[ADD_OVERFLOW]], 1 +// OGCG: %[[ANY_OVERFLOW:.*]] = or i1 %[[OVERFLOW]], %[[OVERFLOW_ADD]] +// OGCG: %[[ELEMENT_SIZE:.*]] = extractvalue { i64, i1 } %[[ADD_OVERFLOW]], 0 +// OGCG: %[[ALLOC_SIZE:.*]] = select i1 %[[ANY_OVERFLOW]], i64 -1, i64 %[[ELEMENT_SIZE]] +// OGCG: %[[PTR:.*]] = call {{.*}} ptr @_Znam(i64 {{.*}} %[[ALLOC_SIZE]]) diff --git a/clang/test/CIR/CodeGen/no-builtin-attr-automatic.cpp b/clang/test/CIR/CodeGen/no-builtin-attr-automatic.cpp new file mode 100644 index 0000000000000..7cdda57b515cf --- /dev/null +++ b/clang/test/CIR/CodeGen/no-builtin-attr-automatic.cpp @@ -0,0 +1,83 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-memset -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefixes=CIR,CIR-STD +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-memset -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-STD +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-memset -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-STD +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-memset -fno-builtin -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefixes=CIR,CIR-NB +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-memset -fno-builtin -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-NB +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-builtin-memset -fno-builtin -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-NB + +extern "C" { +__attribute__((hot)) +__attribute__((no_builtin)) +void no_builtin() {} +// CIR: cir.func{{.*}}@no_builtin() +// CIR-SAME: nobuiltins = [] +// LLVM: define{{.*}}@no_builtin() #[[NO_BUILTIN_ATTRS:.*]] { + +__attribute__((cold)) +__attribute__((no_builtin("memcpy"))) +void no_memcpy() {} +// CIR: cir.func{{.*}}@no_memcpy() +// CIR-STD-SAME: nobuiltins = ["memset", "memcpy"] +// CIR-NB-SAME: nobuiltins = [] +// LLVM: define{{.*}}@no_memcpy() #[[NO_MEMCPY_ATTRS:.*]] { + +__attribute__((noduplicate)) +void memset() {} +// CIR: cir.func{{.*}}@memset() +// CIR-STD-SAME: nobuiltins = ["memset"] +// CIR-NB-SAME: nobuiltins = [] +// LLVM: define{{.*}}@memset() #[[MEMSET_ATTRS:.*]] { + +void caller() { + no_builtin(); + // CIR: cir.call @no_builtin() + // CIR-NB-SAME: nobuiltin + // CIR-SAME: nobuiltins = [] + // LLVM: call void @no_builtin() #[[NO_BUILTIN_CALL_ATTRS:.*]] + no_memcpy(); + // CIR: cir.call @no_memcpy() + // CIR-STD-SAME: nobuiltins = ["memset", "memcpy"] + // CIR-NB-SAME: nobuiltin + // CIR-NB-SAME: nobuiltins = [] + // LLVM: call void @no_memcpy() #[[NO_MEMCPY_CALL_ATTRS:.*]] + memset(); + // CIR: cir.call @memset() + // CIR-STD-SAME: nobuiltins = ["memset"] + // CIR-NB-SAME: nobuiltin + // CIR-NB-SAME: nobuiltins = [] + // LLVM: call void @memset() #[[MEMSET_CALL_ATTRS:.*]] +} +} + +// LLVM: attributes #[[NO_BUILTIN_ATTRS]] +// LLVM-SAME: no-builtins +// LLVM: attributes #[[NO_MEMCPY_ATTRS]] +// LLVM-STD-SAME: no-builtin-memcpy +// LLVM-STD-SAME: no-builtin-memset +// LLVM-NB-SAME: no-builtins +// LLVM: attributes #[[MEMSET_ATTRS]] +// LLVM-STD-SAME: no-builtin-memset +// LLVM-NB-SAME: no-builtins +// LLVM: attributes #[[NO_BUILTIN_CALL_ATTRS]] +// LLVM-NB-SAME: nobuiltin +// LLVM-SAME: no-builtins +// LLVM: attributes #[[NO_MEMCPY_CALL_ATTRS]] +// LLVM-STD-SAME: no-builtin-memcpy +// LLVM-STD-SAME: no-builtin-memset +// LLVM-NB-SAME: nobuiltin +// LLVM-NB-SAME: no-builtins +// LLVM: attributes #[[MEMSET_CALL_ATTRS]] +// LLVM-STD-SAME: no-builtin-memset +// LLVM-NB-SAME: nobuiltin +// LLVM-NB-SAME: no-builtins diff --git a/clang/test/CIR/CodeGen/no-builtin-attr.cpp b/clang/test/CIR/CodeGen/no-builtin-attr.cpp new file mode 100644 index 0000000000000..6abdb8835d5dd --- /dev/null +++ b/clang/test/CIR/CodeGen/no-builtin-attr.cpp @@ -0,0 +1,204 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefixes=CIR,CIR-DEF +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-DEF +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-DEF +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir -fno-builtin-memcmp %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefixes=CIR,CIR-SPC +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm -fno-builtin-memcmp %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-SPC +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -fno-builtin-memcmp %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-SPC +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir -fno-builtin-memcmp -fno-builtin-memset %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefixes=CIR,CIR-BTH +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm -fno-builtin-memcmp -fno-builtin-memset %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-BTH +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -fno-builtin-memcmp -fno-builtin-memset %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-BTH +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir -fno-builtin %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefixes=CIR,CIR-ALL +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm -fno-builtin %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-ALL +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -fno-builtin %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefixes=LLVM,LLVM-ALL + +extern "C" { +// CIR: cir.func{{.*}}@normal() attributes { +// CIR-DEF-NOT: nobuiltins +// CIR-SPC-SAME: nobuiltins = ["memcmp"] +// CIR-BTH-SAME: nobuiltins = ["memcmp", "memset"] +// CIR-ALL-SAME: nobuiltins = [] +// LLVM: define{{.*}}normal() #[[NORM_ATTR:.*]] { +__attribute__((cold)) // to force attributes on the call to be around. +void normal(){} + +// CIR: cir.func{{.*}}@no_builtins() attributes { +// CIR-DEF-SAME: nobuiltins = [] +// CIR-SPC-SAME: nobuiltins = [] +// CIR-BTH-SAME: nobuiltins = [] +// CIR-ALL-SAME: nobuiltins = [] +// LLVM: define{{.*}}no_builtins() #[[NB_ATTR:.*]] { +__attribute__((no_builtin)) +__attribute__((hot)) // force unique attributes +void no_builtins() {} + +// CIR: cir.func{{.*}}@no_memcpy() attributes { +// CIR-DEF-SAME: nobuiltins = ["memcpy"] +// CIR-SPC-SAME: nobuiltins = ["memcmp", "memcpy"] +// CIR-BTH-SAME: nobuiltins = ["memcmp", "memset", "memcpy"] +// CIR-ALL-SAME: nobuiltins = [] +// LLVM: define{{.*}}no_memcpy() #[[NO_MCPY_ATTR:.*]] { +__attribute__((no_builtin("memcpy"))) +__attribute__((leaf)) // force unique attributes +void no_memcpy() {} + +// CIR: cir.func{{.*}}@no_memcmp() attributes { +// CIR-DEF-SAME: nobuiltins = ["memcmp"] +// CIR-SPC-SAME: nobuiltins = ["memcmp"] +// CIR-BTH-SAME: nobuiltins = ["memcmp", "memset"] +// CIR-ALL-SAME: nobuiltins = [] +// LLVM: define{{.*}}no_memcmp() #[[NO_MCMP_ATTR:.*]] { +__attribute__((no_builtin("memcmp"))) +__attribute__((noduplicate)) // force unique attributes +void no_memcmp() {} + +// CIR: cir.func{{.*}}@no_both() attributes { +// CIR-DEF-SAME: nobuiltins = ["memcmp", "memcpy"] +// CIR-SPC-SAME: nobuiltins = ["memcmp", "memcpy"] +// CIR-BTH-SAME: nobuiltins = ["memcmp", "memset", "memcpy"] +// CIR-ALL-SAME: nobuiltins = [] +// LLVM: define{{.*}}no_both() #[[NO_BOTH_ATTR:.*]] { +__attribute__((no_builtin("memcpy"))) +__attribute__((no_builtin("memcmp"))) +__attribute__((convergent)) // force unique attributes +void no_both(){} +} + +void caller() { + // CIR: cir.call @normal() { + // CIR-DEF-NOT: nobuiltins + // CIR-SPC-SAME: nobuiltins = ["memcmp"] + // CIR-BTH-SAME: nobuiltins = ["memcmp", "memset"] + // CIR-ALL-SAME: nobuiltins = [] + // LLVM: call void @normal() #[[NORM_CALL_ATTR:.*]] + normal(); + // CIR: cir.call @no_builtins() { + // CIR-DEF-SAME: nobuiltins = [] + // CIR-SPC-SAME: nobuiltins = [] + // CIR-BTH-SAME: nobuiltins = [] + // CIR-ALL-SAME: nobuiltins = [] + // LLVM: call void @no_builtins() #[[NB_CALL_ATTR:.*]] + no_builtins(); + // CIR: cir.call @no_memcpy() { + // CIR-DEF-SAME: nobuiltins = ["memcpy"] + // CIR-SPC-SAME: nobuiltins = ["memcmp", "memcpy"] + // CIR-BTH-SAME: nobuiltins = ["memcmp", "memset", "memcpy"] + // CIR-ALL-SAME: nobuiltins = [] + // LLVM: call void @no_memcpy() #[[NO_MCPY_CALL_ATTR:.*]] + no_memcpy(); + // CIR: cir.call @no_memcmp() { + // CIR-DEF-SAME: nobuiltins = ["memcmp"] + // CIR-SPC-SAME: nobuiltins = ["memcmp"] + // CIR-BTH-SAME: nobuiltins = ["memcmp", "memset"] + // CIR-ALL-SAME: nobuiltins = [] + // LLVM: call void @no_memcmp() #[[NO_MCMP_CALL_ATTR:.*]] + no_memcmp(); + // CIR: cir.call @no_both() { + // CIR-DEF-SAME: nobuiltins = ["memcmp", "memcpy"] + // CIR-SPC-SAME: nobuiltins = ["memcmp", "memcpy"] + // CIR-BTH-SAME: nobuiltins = ["memcmp", "memset", "memcpy"] + // CIR-ALL-SAME: nobuiltins = [] + // LLVM: call void @no_both() #[[NO_BOTH_CALL_ATTR:.*]] + no_both(); +} + +// LLVM: attributes #[[NORM_ATTR]] = { +// LLVM-DEF-NOT: no-builtin +// LLVM-SPC-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memset" +// LLVM-ALL-SAME:"no-builtins" +// +// LLVM: attributes #[[NB_ATTR]] = { +// LLVM-DEF-SAME:"no-builtins" +// LLVM-SPC-SAME:"no-builtins" +// LLVM-BTH-SAME:"no-builtins" +// LLVM-ALL-SAME:"no-builtins" +// +// LLVM: attributes #[[NO_MCPY_ATTR]] = { +// LLVM-DEF-SAME: "no-builtin-memcpy" +// LLVM-SPC-SAME: "no-builtin-memcmp" +// LLVM-SPC-SAME: "no-builtin-memcpy" +// LLVM-BTH-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memcpy" +// LLVM-BTH-SAME: "no-builtin-memset" +// LLVM-ALL-SAME:"no-builtins" +// +// LLVM: attributes #[[NO_MCMP_ATTR]] = { +// LLVM-DEF-SAME: "no-builtin-memcmp" +// LLVM-SPC-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memset" +// LLVM-ALL-SAME:"no-builtins" +// +// LLVM: attributes #[[NO_BOTH_ATTR]] = { +// LLVM-DEF-SAME: "no-builtin-memcmp" +// LLVM-DEF-SAME: "no-builtin-memcpy" +// LLVM-SPC-SAME: "no-builtin-memcmp" +// LLVM-SPC-SAME: "no-builtin-memcpy" +// LLVM-BTH-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memcpy" +// LLVM-BTH-SAME: "no-builtin-memset" +// LLVM-ALL-SAME:"no-builtins" +// +// +// LLVM: attributes #[[NORM_CALL_ATTR]] = { +// LLVM-DEF-NOT: no-builtin +// LLVM-SPC-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memset" +// LLVM-ALL-SAME:"no-builtins" +// +// LLVM: attributes #[[NB_CALL_ATTR]] = { +// LLVM-DEF-SAME:"no-builtins" +// LLVM-SPC-SAME:"no-builtins" +// LLVM-BTH-SAME:"no-builtins" +// LLVM-ALL-SAME:"no-builtins" +// +// LLVM: attributes #[[NO_MCPY_CALL_ATTR]] = { +// LLVM-DEF-SAME: "no-builtin-memcpy" +// LLVM-SPC-SAME: "no-builtin-memcmp" +// LLVM-SPC-SAME: "no-builtin-memcpy" +// LLVM-BTH-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memcpy" +// LLVM-BTH-SAME: "no-builtin-memset" +// LLVM-ALL-SAME:"no-builtins" +// +// LLVM: attributes #[[NO_MCMP_CALL_ATTR]] = { +// LLVM-DEF-SAME: "no-builtin-memcmp" +// LLVM-SPC-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memset" +// LLVM-ALL-SAME:"no-builtins" +// +// LLVM: attributes #[[NO_BOTH_CALL_ATTR]] = { +// LLVM-DEF-SAME: "no-builtin-memcmp" +// LLVM-DEF-SAME: "no-builtin-memcpy" +// LLVM-SPC-SAME: "no-builtin-memcmp" +// LLVM-SPC-SAME: "no-builtin-memcpy" +// LLVM-BTH-SAME: "no-builtin-memcmp" +// LLVM-BTH-SAME: "no-builtin-memcpy" +// LLVM-BTH-SAME: "no-builtin-memset" +// LLVM-ALL-SAME:"no-builtins" diff --git a/clang/test/CIR/CodeGen/offload-convergent-attr.cu b/clang/test/CIR/CodeGen/offload-convergent-attr.cu new file mode 100644 index 0000000000000..1112ca3614326 --- /dev/null +++ b/clang/test/CIR/CodeGen/offload-convergent-attr.cu @@ -0,0 +1,45 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcuda-is-device -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcuda-is-device -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fcuda-is-device -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM + +extern "C" { +__attribute__((device)) +void normal() {} +// CIR: cir.func{{.*}}@normal() +// CIR-SAME: convergent +// LLVM: define {{.*}}@normal(){{.*}} #[[NORMAL_ATTR:.*]] { + +__attribute__((hot)) +__attribute__((device)) +__attribute__((noconvergent)) +void no_conv() {} +// CIR: cir.func{{.*}}@no_conv() +// CIR-NOT: convergent +// LLVM: define {{.*}}@no_conv(){{.*}} #[[NO_CONV_ATTR:.*]] { + +// CIR: cir.func{{.*}}@caller +__attribute__((device)) +void caller() { + normal(); + // CIR: cir.call{{.*}}@normal() + // CIR-SAME: convergent + // LLVM: call void{{.*}}@normal() #[[NORMAL_CALL_ATTR:.*]] + no_conv(); + // CIR: cir.call{{.*}}@no_conv() + // CIR-NOT: convergent + // CIR: cir.return + // LLVM: call void{{.*}}@no_conv() #[[NO_CONV_CALL_ATTR:.*]] +} +} + +// LLVM: attributes #[[NORMAL_ATTR]] +// LLVM-SAME: convergent +// LLVM: attributes #[[NO_CONV_ATTR]] +// LLVM-NOT: convergent +// LLVM: attributes #[[NORMAL_CALL_ATTR]] +// LLVM-SAME: convergent +// LLVM: attributes #[[NO_CONV_CALL_ATTR]] +// LLVM-NOT: convergent diff --git a/clang/test/CIR/CodeGen/optsize-func-attr.cpp b/clang/test/CIR/CodeGen/optsize-func-attr.cpp new file mode 100644 index 0000000000000..28441b8558584 --- /dev/null +++ b/clang/test/CIR/CodeGen/optsize-func-attr.cpp @@ -0,0 +1,74 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-llvm-passes -Os -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-llvm-passes -Os -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,BOTH +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-llvm-passes -Os -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG,BOTH +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-llvm-passes -Oz -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR,CIROZ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-llvm-passes -Oz -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,BOTH,BOTHOZ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -disable-llvm-passes -Oz -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=OGCG,OGCGOZ,BOTH,BOTHOZ + +extern "C" { + __attribute__((hot)) + void normal(){} + // CIR: cir.func{{.*}}@normal() + // CIROZ-SAME: minsize + // CIR-SAME: optsize + // BOTH: define{{.*}}@normal(){{.*}} #[[NORMAL_ATTR:.*]] { + + __attribute__((cold)) + __attribute__((optnone)) + void optnone(){} + // CIR: cir.func{{.*}}@optnone() + // CIR-NOT: optsize + // CIR-NOT: minsize + // BOTH: define{{.*}}@optnone(){{.*}} #[[OPTNONE_ATTR:.*]] { + + // CIR: cir.func{{.*}}@caller() + void caller() { + normal(); + // CIR: cir.call{{.*}}@normal() + // CIROZ-SAME: minsize + // CIR-SAME: optsize + // LLVM: call void @normal() #[[NORMAL_ATTR]] + // OGCG: call void @normal() #[[NORMAL_CALL_ATTR:.*]] + optnone(); + // CIR: cir.call{{.*}}@optnone() + // CIR-NOT: optsize + // CIR-NOT: minsize + // LLVM: call void @optnone() #[[OPTNONE_ATTR]] + // OGCG: call void @optnone() #[[OPTNONE_CALL_ATTR:.*]] + + // CIR: cir.return + } +} + +// BOTH: attributes #[[NORMAL_ATTR]] +// BOTHOZ-SAME: minsize +// BOTH-SAME: optsize +// +// BOTH: attributes #[[OPTNONE_ATTR]] +// BOTH-NOT: optsize +// BOTH-NOT: minsize +// +// attributes for caller, to block the 'NOT'. +// BOTH: attributes +// +// CIR doesn't have sufficiently different 'attributes' implemented for the +// caller and the callee to be different when doing -O settings (as 'optnone' +// is the only difference). So the below call attributes are only necessary +// for classic codegen. +// OGCG: attributes #[[NORMAL_CALL_ATTR]] +// OGCGOZ-SAME: minsize +// OGCG-SAME: optsize +// +// OGCG: attributes #[[OPTNONE_CALL_ATTR]] +// OGCG-NOT: optsize +// OGCG-NOT: minsize +// +// to block the 'NOT'. +// BOTH: llvm.module.flags diff --git a/clang/test/CIR/CodeGen/save-reg-params-func-attr.cpp b/clang/test/CIR/CodeGen/save-reg-params-func-attr.cpp new file mode 100644 index 0000000000000..61bf1bdf31287 --- /dev/null +++ b/clang/test/CIR/CodeGen/save-reg-params-func-attr.cpp @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -msave-reg-params -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -msave-reg-params -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -msave-reg-params -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM + +extern "C" { + + __attribute__((hot)) + void func(){} + // CIR: cir.func{{.*}}@func() + // CIR-SAME: save_reg_params + // LLVM: define{{.*}}@func() #[[FUNC_ATTRS:.*]] { + + void caller() { + func(); + // CIR: cir.call{{.*}}@func() + // CIR-NOT: save_reg_params + // CIR: cir.return + // LLVM: call void{{.*}}@func() #[[CALL_ATTRS:.*]] + + } +} + +// LLVM: attributes #[[FUNC_ATTRS]] +// LLVM-SAME: "save-reg-params" +// LLVM: attributes #[[CALL_ATTRS]] +// LLVM-NOT: "save-reg-params" diff --git a/clang/test/CIR/CodeGen/trap-func-name-attr.cpp b/clang/test/CIR/CodeGen/trap-func-name-attr.cpp new file mode 100644 index 0000000000000..38afc6b3b11d4 --- /dev/null +++ b/clang/test/CIR/CodeGen/trap-func-name-attr.cpp @@ -0,0 +1,33 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -ftrap-function=trap_func -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -ftrap-function=trap_func -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -ftrap-function=trap_func -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM + +extern "C" { + void normal() {} + // CIR: cir.func{{.*}}@normal() + // CIR-NOT: trap_func_name + // LLVM: define{{.*}}@normal() #[[FUNC_ATTR:.*]] { + void trap_func(){} + // CIR: cir.func{{.*}}@trap_func() + // CIR-NOT: trap_func_name + // LLVM: define{{.*}}@trap_func() #[[FUNC_ATTR]] { + + void caller() { + normal(); + // CIR: cir.call{{.*}}normal() + // CIR-SAME: trap_func_name = "trap_func" + // LLVM: call void{{.*}} @normal() #[[CALL_ATTR:.*]] + trap_func(); + // CIR: cir.call{{.*}}trap_func() + // CIR-SAME: trap_func_name = "trap_func" + // LLVM: call void{{.*}} @trap_func() #[[CALL_ATTR]] + } +} + +// LLVM: attributes #[[FUNC_ATTR]] +// LLVM-NOT: trap-func-name +// LLVM: attributes #[[CALL_ATTR]] +// LLVM-SAME: "trap-func-name"="trap_func" diff --git a/clang/test/CIR/CodeGen/zero-call-used-regs-func-attr.cpp b/clang/test/CIR/CodeGen/zero-call-used-regs-func-attr.cpp new file mode 100644 index 0000000000000..b5953fd63d581 --- /dev/null +++ b/clang/test/CIR/CodeGen/zero-call-used-regs-func-attr.cpp @@ -0,0 +1,102 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR,CIR_NONE +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,LLVM_NONE +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,LLVM_NONE + +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzero-call-used-regs=skip -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR,CIR_SKIP +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzero-call-used-regs=skip -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,LLVM_SKIP +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzero-call-used-regs=skip -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,LLVM_SKIP + +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzero-call-used-regs=all-gpr -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s -check-prefix=CIR,CIR_ALLGPR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzero-call-used-regs=all-gpr -fclangir -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,LLVM_ALLGPR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fzero-call-used-regs=all-gpr -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s -check-prefix=LLVM,LLVM_ALLGPR + +extern "C" { + __attribute__((hot)) + void normal(){} + // CIR: cir.func{{.*}}@normal() + // CIR_NONE-NOT: zero-call-used-regs + // CIR_SKIP-NOT: zero-call-used-regs + // CIR_ALLGPR-SAME: zero_call_used_regs = "all-gpr" + // LLVM: define{{.*}}@normal() #[[NORM_ATTR:.*]] { + + __attribute__((cold)) + __attribute__((zero_call_used_regs("skip"))) + void skip() { } + // CIR: cir.func{{.*}}@skip() + // CIR-SAME: zero_call_used_regs = "skip" + // LLVM: define{{.*}}@skip() #[[SKIP_ATTR:.*]] { + + __attribute__((zero_call_used_regs("all"))) + void all() { } + // CIR: cir.func{{.*}}@all() + // CIR-SAME: zero_call_used_regs = "all" + // LLVM: define{{.*}}@all() #[[ALL_ATTR:.*]] { + + __attribute__((zero_call_used_regs("used"))) + void used() { } + // CIR: cir.func{{.*}}@used() + // CIR-SAME: zero_call_used_regs = "used" + // LLVM: define{{.*}}@used() #[[USED_ATTR:.*]] { + + __attribute__((zero_call_used_regs("used-gpr-arg"))) + void used_gpr_arg() { } + // CIR: cir.func{{.*}}@used_gpr_arg() + // CIR-SAME: zero_call_used_regs = "used-gpr-arg" + // LLVM: define{{.*}}@used_gpr_arg() #[[USED_GPR_ATTR:.*]] { + + void caller() { + normal(); + // CIR: cir.call{{.*}}@normal() + // CIR-NOT: zero-call-used-regs + // LLVM: call void{{.*}}@normal() #[[NORM_CALL_ATTR:.*]] + skip(); + // CIR: cir.call{{.*}}@skip() + // CIR-SAME: zero_call_used_regs = "skip" + // LLVM: call void{{.*}}@skip() #[[SKIP_CALL_ATTR:.*]] + all(); + // CIR: cir.call{{.*}}@all() + // CIR-SAME: zero_call_used_regs = "all" + // LLVM: call void{{.*}}@all() #[[ALL_CALL_ATTR:.*]] + used(); + // CIR: cir.call{{.*}}@used() + // CIR-SAME: zero_call_used_regs = "used" + // LLVM: call void{{.*}}@used() #[[USED_CALL_ATTR:.*]] + used_gpr_arg(); + // CIR: cir.call{{.*}}@used_gpr_arg() + // CIR-SAME: zero_call_used_regs = "used-gpr-arg" + // LLVM: call void{{.*}}@used_gpr_arg() #[[USED_GPR_CALL_ATTR:.*]] + } +} + +// LLVM: attributes #[[NORM_ATTR]] +// LLVM_NONE-NOT: zero-call-used-regs +// LLVM_SKIP-NOT: zero-call-used-regs +// LLVM_ALLGPR-SAME: "zero-call-used-regs"="all-gpr" +// LLVM: attributes #[[SKIP_ATTR]] +// LLVM-SAME: "zero-call-used-regs"="skip" +// LLVM: attributes #[[ALL_ATTR]] +// LLVM-SAME: "zero-call-used-regs"="all" +// LLVM: attributes #[[USED_ATTR]] +// LLVM-SAME: "zero-call-used-regs"="used" +// LLVM: attributes #[[USED_GPR_ATTR]] +// LLVM-SAME: "zero-call-used-regs"="used-gpr-arg" +// +// LLVM: attributes #[[NORM_CALL_ATTR]] +// LLVM-NOT: zero-call-used-regs +// LLVM: attributes #[[SKIP_CALL_ATTR]] +// LLVM-SAME: "zero-call-used-regs"="skip" +// LLVM: attributes #[[ALL_CALL_ATTR]] +// LLVM-SAME: "zero-call-used-regs"="all" +// LLVM: attributes #[[USED_CALL_ATTR]] +// LLVM-SAME: "zero-call-used-regs"="used" +// LLVM: attributes #[[USED_GPR_CALL_ATTR]] +// LLVM-SAME: "zero-call-used-regs"="used-gpr-arg" diff --git a/clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c b/clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c index 3e0a892d6b368..60a2992ab14ad 100644 --- a/clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c +++ b/clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c @@ -1,13 +1,13 @@ // REQUIRES: aarch64-registered-target - +// // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -fclangir -emit-cir -o - %s | FileCheck %s --check-prefixes=ALL,CIR -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -fclangir -emit-llvm -o - %s | FileCheck %s --check-prefixes=ALL,LLVM_OGCG_CIR -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -fclangir -emit-llvm -o - %s | FileCheck %s --check-prefixes=ALL,LLVM_OGCG_CIR +// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -fclangir -emit-llvm -o - %s | FileCheck %s --check-prefixes=ALL,LLVM_OGCG_CIR,LLVM_VIA_CIR +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -fclangir -emit-llvm -o - %s | FileCheck %s --check-prefixes=ALL,LLVM_OGCG_CIR,LLVM_VIA_CIR -// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s --check-prefixes=ALL,LLVM_OGCG_CIR -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s --check-prefixes=ALL,LLVM_OGCG_CIR +// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s --check-prefixes=ALL,LLVM_OGCG_CIR,LLVM_DIRECT +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s --check-prefixes=ALL,LLVM_OGCG_CIR,LLVM_DIRECT #include #if defined __ARM_FEATURE_SME @@ -209,3 +209,470 @@ svfloat64_t test_svdup_n_f64(float64_t op) MODE_ATTR // LLVM_OGCG_CIR: [[RES:%.*]] = call @llvm.aarch64.sve.dup.x.nxv2f64(double [[OP_LOAD]]) return SVE_ACLE_FUNC(svdup,_n,_f64,)(op); } + +// ALL-LABEL: @test_svdup_n_s8_z +svint8_t test_svdup_n_s8_z(svbool_t pg, int8_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !s8i +// CIR-SAME: -> !cir.vector<[16] x !s8i> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !s8i +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[16] x !s8i> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(1) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[16] x !s8i> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[LOAD_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[16] x !s8i> +// CIR: cir.store %[[CONVERT_PG]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], i8 {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca i8,{{([[:space:]]?i64 1,)?}} align 1 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store i8 [[OP]], ptr [[OP_ADDR]], align 1 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load i8, ptr [[OP_ADDR]], align 1 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.dup.nxv16i8( zeroinitializer, [[TMP0]], i8 [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP2]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP2]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_s8_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_s16_z( +svint16_t test_svdup_n_s16_z(svbool_t pg, int16_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !s16i +// CIR-SAME: -> !cir.vector<[8] x !s16i> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !s16i +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[8] x !s16i> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(2) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[8] x !s16i> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[8] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[8] x !s16i> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], i16 {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca i16,{{([[:space:]]?i64 1,)?}} align 2 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store i16 [[OP]], ptr [[OP_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load i16, ptr [[OP_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv8i16( zeroinitializer, [[TMP2]], i16 [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_s16_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_s32_z( +svint32_t test_svdup_n_s32_z(svbool_t pg, int32_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !s32i +// CIR-SAME: -> !cir.vector<[4] x !s32i> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !s32i +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[4] x !s32i> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(4) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[4] x !s32i> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[4] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[4] x !s32i> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], i32 {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca i32,{{([[:space:]]?i64 1,)?}} align 4 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store i32 [[OP]], ptr [[OP_ADDR]], align 4 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load i32, ptr [[OP_ADDR]], align 4 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv4i32( zeroinitializer, [[TMP2]], i32 [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_s32_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_s64_z( +svint64_t test_svdup_n_s64_z(svbool_t pg, int64_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !s64i +// CIR-SAME: -> !cir.vector<[2] x !s64i> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !s64i +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[2] x !s64i> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(8) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[2] x !s64i> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[2] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[2] x !s64i> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], i64 {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca i64,{{([[:space:]]?i64 1,)?}} align 8 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store i64 [[OP]], ptr [[OP_ADDR]], align 8 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load i64, ptr [[OP_ADDR]], align 8 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv2i64( zeroinitializer, [[TMP2]], i64 [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_s64_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_u8_z( +svuint8_t test_svdup_n_u8_z(svbool_t pg, uint8_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !u8i +// CIR-SAME: -> !cir.vector<[16] x !u8i> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !u8i +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[16] x !u8i> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(1) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[16] x !u8i> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[LOAD_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[16] x !u8i> +// CIR: cir.store %[[CONVERT_PG]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], i8 {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca i8,{{([[:space:]]?i64 1,)?}} align 1 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store i8 [[OP]], ptr [[OP_ADDR]], align 1 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load i8, ptr [[OP_ADDR]], align 1 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.dup.nxv16i8( zeroinitializer, [[TMP0]], i8 [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP2]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP2]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_u8_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_u16_z( +svuint16_t test_svdup_n_u16_z(svbool_t pg, uint16_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !u16i +// CIR-SAME: -> !cir.vector<[8] x !u16i> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !u16i +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[8] x !u16i> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(2) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[8] x !u16i> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[8] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[8] x !u16i> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], i16 {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca i16,{{([[:space:]]?i64 1,)?}} align 2 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store i16 [[OP]], ptr [[OP_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load i16, ptr [[OP_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv8i16( zeroinitializer, [[TMP2]], i16 [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_u16_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_u32_z( +svuint32_t test_svdup_n_u32_z(svbool_t pg, uint32_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !u32i +// CIR-SAME: -> !cir.vector<[4] x !u32i> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !u32i +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[4] x !u32i> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(4) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[4] x !u32i> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[4] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[4] x !u32i> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], i32 {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca i32,{{([[:space:]]?i64 1,)?}} align 4 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store i32 [[OP]], ptr [[OP_ADDR]], align 4 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load i32, ptr [[OP_ADDR]], align 4 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv4i32( zeroinitializer, [[TMP2]], i32 [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_u32_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_u64_z( +svuint64_t test_svdup_n_u64_z(svbool_t pg, uint64_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !u64i +// CIR-SAME: -> !cir.vector<[2] x !u64i> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !u64i +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[2] x !u64i> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(8) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[2] x !u64i> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[2] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[2] x !u64i> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], i64 {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca i64,{{([[:space:]]?i64 1,)?}} align 8 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store i64 [[OP]], ptr [[OP_ADDR]], align 8 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load i64, ptr [[OP_ADDR]], align 8 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv2i64( zeroinitializer, [[TMP2]], i64 [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_u64_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_f16_z( +svfloat16_t test_svdup_n_f16_z(svbool_t pg, float16_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !cir.f16 +// CIR-SAME: -> !cir.vector<[8] x !cir.f16> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !cir.f16 +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[8] x !cir.f16> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(2) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[8] x !cir.f16> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[8] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[8] x !cir.f16> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], half {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca half,{{([[:space:]]?i64 1,)?}} align 2 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store half [[OP]], ptr [[OP_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load half, ptr [[OP_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv8f16( zeroinitializer, [[TMP2]], half [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_f16_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_f32_z( +svfloat32_t test_svdup_n_f32_z(svbool_t pg, float32_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !cir.float +// CIR-SAME: -> !cir.vector<[4] x !cir.float> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !cir.float +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[4] x !cir.float> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(4) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[4] x !cir.float> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[4] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[4] x !cir.float> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], float {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca float,{{([[:space:]]?i64 1,)?}} align 4 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store float [[OP]], ptr [[OP_ADDR]], align 4 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load float, ptr [[OP_ADDR]], align 4 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv4f32( zeroinitializer, [[TMP2]], float [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_f32_z,)(pg, op); +} + +// ALL-LABEL: @test_svdup_n_f64_z( +svfloat64_t test_svdup_n_f64_z(svbool_t pg, float64_t op) MODE_ATTR +{ +// CIR-SAME: %[[PG:.*]]: !cir.vector<[16] x !cir.int> +// CIR-SAME: %[[OP:.*]]: !cir.double +// CIR-SAME: -> !cir.vector<[2] x !cir.double> +// CIR: %[[ALLOCA_PG:.*]] = cir.alloca !cir.vector<[16] x !cir.int> +// CIR: %[[ALLOCA_OP:.*]] = cir.alloca !cir.double +// CIR: %[[ALLOCA_RES:.*]] = cir.alloca !cir.vector<[2] x !cir.double> +// CIR: cir.store %[[PG]], %[[ALLOCA_PG]] +// CIR: cir.store %[[OP]], %[[ALLOCA_OP]] +// CIR: %[[LOAD_PG:.*]] = cir.load align(2) %[[ALLOCA_PG]] +// CIR: %[[LOAD_OP:.*]] = cir.load align(8) %[[ALLOCA_OP]] +// CIR: %[[CONST_0:.*]] = cir.const #cir.zero : !cir.vector<[2] x !cir.double> +// CIR: %[[CONVERT_PG:.*]] = cir.call_llvm_intrinsic "aarch64.sve.convert.from.svbool" %[[LOAD_PG]] +// CIR-SAME: -> !cir.vector<[2] x !cir.int> +// CIR: %[[CALL_DUP:.*]] = cir.call_llvm_intrinsic "aarch64.sve.dup" %[[CONST_0]], %[[CONVERT_PG]], %[[LOAD_OP]] +// CIR-SAME: -> !cir.vector<[2] x !cir.double> +// CIR: cir.store %[[CALL_DUP]], %[[ALLOCA_RES]] +// CIR: %[[RES:.*]] = cir.load %[[ALLOCA_RES]] +// CIR: cir.return %[[RES]] + +// LLVM_OGCG_CIR-SAME: [[PG:%.*]], double {{(noundef)?[[:space:]]?}}[[OP:%.*]]) +// LLVM_OGCG_CIR: [[PG_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 2 +// LLVM_OGCG_CIR: [[OP_ADDR:%.*]] = alloca double,{{([[:space:]]?i64 1,)?}} align 8 +// +// LLVM_VIA_CIR: [[RES_ADDR:%.*]] = alloca ,{{([[:space:]]?i64 1,)?}} align 16 +// +// LLVM_OGCG_CIR: store [[PG]], ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: store double [[OP]], ptr [[OP_ADDR]], align 8 +// LLVM_OGCG_CIR: [[TMP0:%.*]] = load , ptr [[PG_ADDR]], align 2 +// LLVM_OGCG_CIR: [[TMP1:%.*]] = load double, ptr [[OP_ADDR]], align 8 +// LLVM_OGCG_CIR: [[TMP2:%.*]] = call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[TMP0]]) +// LLVM_OGCG_CIR: [[TMP3:%.*]] = call @llvm.aarch64.sve.dup.nxv2f64( zeroinitializer, [[TMP2]], double [[TMP1]]) +// +// LLVM_DIRECT: ret {{.*}} [[TMP3]] +// +// LLVM_VIA_CIR: store {{.*}} [[TMP3]], ptr [[RES_ADDR]] +// LLVM_VIA_CIR: [[RES:%.*]] = load {{.*}} [[RES_ADDR]] +// LLVM_VIA_CIR: ret {{.*}} [[RES]] + return SVE_ACLE_FUNC(svdup,_n,_f64_z,)(pg, op); +} diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512-reduceIntrin.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512-reduceIntrin.c index bc4249ffd25fc..c720dc031c3d1 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512-reduceIntrin.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512-reduceIntrin.c @@ -10,7 +10,7 @@ double test_mm512_reduce_add_pd(__m512d __W, double ExtraAddOp){ // CIR: cir.call_llvm_intrinsic "vector.reduce.fadd" %[[R:.*]], %[[V:.*]] : (!cir.double, !cir.vector<8 x !cir.double>) -> !cir.double // CIR-LABEL: test_mm512_reduce_add_pd - // CIR: cir.call @_mm512_reduce_add_pd(%[[VEC:.*]]) : (!cir.vector<8 x !cir.double>) -> !cir.double + // CIR: cir.call @_mm512_reduce_add_pd(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.double>) -> !cir.double // LLVM-LABEL: test_mm512_reduce_add_pd // LLVM: call double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> %{{.*}}) @@ -27,7 +27,7 @@ double test_mm512_reduce_mul_pd(__m512d __W, double ExtraMulOp){ // CIR: cir.call_llvm_intrinsic "vector.reduce.fmul" %[[R:.*]], %[[V:.*]] : (!cir.double, !cir.vector<8 x !cir.double>) -> !cir.double // CIR-LABEL: test_mm512_reduce_mul_pd - // CIR: cir.call @_mm512_reduce_mul_pd(%[[VEC:.*]]) : (!cir.vector<8 x !cir.double>) -> !cir.double + // CIR: cir.call @_mm512_reduce_mul_pd(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.double>) -> !cir.double // LLVM-LABEL: test_mm512_reduce_mul_pd // LLVM: call double @llvm.vector.reduce.fmul.v8f64(double 1.000000e+00, <8 x double> %{{.*}}) @@ -45,7 +45,7 @@ float test_mm512_reduce_add_ps(__m512 __W){ // CIR: cir.call_llvm_intrinsic "vector.reduce.fadd" %[[R:.*]], %[[V:.*]] : (!cir.float, !cir.vector<16 x !cir.float>) -> !cir.float // CIR-LABEL: test_mm512_reduce_add_ps - // CIR: cir.call @_mm512_reduce_add_ps(%[[VEC:.*]]) : (!cir.vector<16 x !cir.float>) -> !cir.float + // CIR: cir.call @_mm512_reduce_add_ps(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.float>) -> !cir.float // LLVM-LABEL: test_mm512_reduce_add_ps // LLVM: call float @llvm.vector.reduce.fadd.v16f32(float -0.000000e+00, <16 x float> %{{.*}}) @@ -60,7 +60,7 @@ float test_mm512_reduce_mul_ps(__m512 __W){ // CIR: cir.call_llvm_intrinsic "vector.reduce.fmul" %[[R:.*]], %[[V:.*]] : (!cir.float, !cir.vector<16 x !cir.float>) -> !cir.float // CIR-LABEL: test_mm512_reduce_mul_ps - // CIR: cir.call @_mm512_reduce_mul_ps(%[[VEC:.*]]) : (!cir.vector<16 x !cir.float>) -> !cir.float + // CIR: cir.call @_mm512_reduce_mul_ps(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.float>) -> !cir.float // LLVM-LABEL: test_mm512_reduce_mul_ps // LLVM: call float @llvm.vector.reduce.fmul.v16f32(float 1.000000e+00, <16 x float> %{{.*}}) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512-reduceMinMaxIntrin.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512-reduceMinMaxIntrin.c index 104e76fa6ad03..f61b55b6b27f8 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512-reduceMinMaxIntrin.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512-reduceMinMaxIntrin.c @@ -9,7 +9,7 @@ double test_mm512_reduce_max_pd(__m512d __W, double ExtraAddOp){ // CIR: cir.call_llvm_intrinsic "vector.reduce.fmax" %[[V:.*]] : (!cir.vector<8 x !cir.double>) -> !cir.double // CIR-LABEL: test_mm512_reduce_max_pd - // CIR: cir.call @_mm512_reduce_max_pd(%[[VEC:.*]]) : (!cir.vector<8 x !cir.double>) -> !cir.double + // CIR: cir.call @_mm512_reduce_max_pd(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.double>) -> !cir.double // LLVM-LABEL: test_mm512_reduce_max_pd // LLVM: call double @llvm.vector.reduce.fmax.v8f64(<8 x double> %{{.*}}) @@ -26,7 +26,7 @@ double test_mm512_reduce_min_pd(__m512d __W, double ExtraMulOp){ // CIR: cir.call_llvm_intrinsic "vector.reduce.fmin" %[[V:.*]] : (!cir.vector<8 x !cir.double>) -> !cir.double // CIR-LABEL: test_mm512_reduce_min_pd - // CIR: cir.call @_mm512_reduce_min_pd(%[[VEC:.*]]) : (!cir.vector<8 x !cir.double>) -> !cir.double + // CIR: cir.call @_mm512_reduce_min_pd(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.double>) -> !cir.double // LLVM-LABEL: test_mm512_reduce_min_pd // LLVM: call double @llvm.vector.reduce.fmin.v8f64(<8 x double> %{{.*}}) @@ -43,7 +43,7 @@ float test_mm512_reduce_max_ps(__m512 __W){ // CIR: cir.call_llvm_intrinsic "vector.reduce.fmax" %[[V:.*]] : (!cir.vector<16 x !cir.float>) -> !cir.float // CIR-LABEL: test_mm512_reduce_max_ps - // CIR: cir.call @_mm512_reduce_max_ps(%[[VEC:.*]]) : (!cir.vector<16 x !cir.float>) -> !cir.float + // CIR: cir.call @_mm512_reduce_max_ps(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.float>) -> !cir.float // LLVM-LABEL: test_mm512_reduce_max_ps // LLVM: call float @llvm.vector.reduce.fmax.v16f32(<16 x float> %{{.*}}) @@ -58,7 +58,7 @@ float test_mm512_reduce_min_ps(__m512 __W){ // CIR: cir.call_llvm_intrinsic "vector.reduce.fmin" %[[V:.*]] : (!cir.vector<16 x !cir.float>) -> !cir.float // CIR-LABEL: test_mm512_reduce_min_ps - // CIR: cir.call @_mm512_reduce_min_ps(%[[VEC:.*]]) : (!cir.vector<16 x !cir.float>) -> !cir.float + // CIR: cir.call @_mm512_reduce_min_ps(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.float>) -> !cir.float // LLVM-LABEL: test_mm512_reduce_min_ps // LLVM: call float @llvm.vector.reduce.fmin.v16f32(<16 x float> %{{.*}}) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c index 74e40c0d5a76e..cd6b87d65c90e 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c @@ -70,7 +70,7 @@ _Float16 test_mm512_reduce_add_ph(__m512h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fadd" %[[R:.*]], %[[V:.*]] : (!cir.f16, !cir.vector<32 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm512_reduce_add_ph - // CIR: cir.call @_mm512_reduce_add_ph(%[[VEC:.*]]) : (!cir.vector<32 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm512_reduce_add_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<32 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm512_reduce_add_ph // LLVM: call half @llvm.vector.reduce.fadd.v32f16(half 0xH8000, <32 x half> %{{.*}}) @@ -85,7 +85,7 @@ _Float16 test_mm512_reduce_mul_ph(__m512h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmul" %[[R:.*]], %[[V:.*]] : (!cir.f16, !cir.vector<32 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm512_reduce_mul_ph - // CIR: cir.call @_mm512_reduce_mul_ph(%[[VEC:.*]]) : (!cir.vector<32 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm512_reduce_mul_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<32 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm512_reduce_mul_ph // LLVM: call half @llvm.vector.reduce.fmul.v32f16(half 0xH3C00, <32 x half> %{{.*}}) @@ -100,7 +100,7 @@ _Float16 test_mm512_reduce_max_ph(__m512h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmax" %[[V:.*]] (!cir.vector<32 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm512_reduce_max_ph - // CIR: cir.call @_mm512_reduce_max_ph(%[[VEC:.*]]) : (!cir.vector<32 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm512_reduce_max_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<32 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm512_reduce_max_ph // LLVM: call half @llvm.vector.reduce.fmax.v32f16(<32 x half> %{{.*}}) @@ -115,7 +115,7 @@ _Float16 test_mm512_reduce_min_ph(__m512h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmin" %[[V:.*]] (!cir.vector<32 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm512_reduce_min_ph - // CIR: cir.call @_mm512_reduce_min_ph(%[[VEC:.*]]) : (!cir.vector<32 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm512_reduce_min_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<32 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm512_reduce_min_ph // LLVM: call half @llvm.vector.reduce.fmin.v32f16(<32 x half> %{{.*}}) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vlbf16-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512vlbf16-builtins.c index d1e9a030e637c..f85488aead8fb 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vlbf16-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vlbf16-builtins.c @@ -9,7 +9,7 @@ __m256bh test_mm512_mask_cvtneps_pbh(__m256bh src, __mmask16 k, __m512 a) { // CIR-LABEL: test_mm512_mask_cvtneps_pbh - // CIR: cir.call @_mm512_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<16 x !cir.bf16>, !u16i, !cir.vector<16 x !cir.float>) -> !cir.vector<16 x !cir.bf16> + // CIR: cir.call @_mm512_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.bf16>, !u16i, !cir.vector<16 x !cir.float>) -> !cir.vector<16 x !cir.bf16> // LLVM-LABEL: @test_mm512_mask_cvtneps_pbh // LLVM: call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512 @@ -21,7 +21,7 @@ __m256bh test_mm512_mask_cvtneps_pbh(__m256bh src, __mmask16 k, __m512 a) { __m256bh test_mm512_maskz_cvtneps_pbh(__mmask16 k, __m512 a) { // CIR-LABEL: test_mm512_maskz_cvtneps_pbh - // CIR: cir.call @_mm512_maskz_cvtneps_pbh({{.+}}, {{.+}}) : (!u16i, !cir.vector<16 x !cir.float>) -> !cir.vector<16 x !cir.bf16> + // CIR: cir.call @_mm512_maskz_cvtneps_pbh({{.+}}, {{.+}}) {nobuiltin, nobuiltins = [{{.*}}]} : (!u16i, !cir.vector<16 x !cir.float>) -> !cir.vector<16 x !cir.bf16> // LLVM-LABEL: @test_mm512_maskz_cvtneps_pbh // LLVM: call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> {{.+}}) @@ -34,7 +34,7 @@ __m256bh test_mm512_maskz_cvtneps_pbh(__mmask16 k, __m512 a) { __m128bh test_mm256_mask_cvtneps_pbh(__m128bh src, __mmask8 k, __m256 a) { // CIR-LABEL: test_mm256_mask_cvtneps_pbh - // CIR: cir.call @_mm256_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<8 x !cir.bf16>, !u8i, !cir.vector<8 x !cir.float>) -> !cir.vector<8 x !cir.bf16> + // CIR: cir.call @_mm256_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.bf16>, !u8i, !cir.vector<8 x !cir.float>) -> !cir.vector<8 x !cir.bf16> // LLVM-LABEL: @test_mm256_mask_cvtneps_pbh // LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> {{.+}}) @@ -46,7 +46,7 @@ __m128bh test_mm256_mask_cvtneps_pbh(__m128bh src, __mmask8 k, __m256 a) { __m128bh test_mm256_maskz_cvtneps_pbh(__mmask8 k, __m256 a) { // CIR-LABEL: test_mm256_maskz_cvtneps_pbh - // CIR: cir.call @_mm256_maskz_cvtneps_pbh({{.+}}, {{.+}}) : (!u8i, !cir.vector<8 x !cir.float>) -> !cir.vector<8 x !cir.bf16> + // CIR: cir.call @_mm256_maskz_cvtneps_pbh({{.+}}, {{.+}}) {nobuiltin, nobuiltins = [{{.*}}]} : (!u8i, !cir.vector<8 x !cir.float>) -> !cir.vector<8 x !cir.bf16> // LLVM-LABEL: @test_mm256_maskz_cvtneps_pbh // LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> {{.+}}) @@ -58,7 +58,7 @@ __m128bh test_mm256_maskz_cvtneps_pbh(__mmask8 k, __m256 a) { __m128bh test_mm_mask_cvtneps_pbh(__m128bh src, __mmask8 k, __m128 a) { // CIR-LABEL: test_mm_mask_cvtneps_pbh - // CIR: cir.call @_mm_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<8 x !cir.bf16>, !u8i, !cir.vector<4 x !cir.float>) -> !cir.vector<8 x !cir.bf16>{{.+}} + // CIR: cir.call @_mm_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.bf16>, !u8i, !cir.vector<4 x !cir.float>) -> !cir.vector<8 x !cir.bf16>{{.+}} // LLVM-LABEL: @test_mm_mask_cvtneps_pbh // LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.mask.cvtneps2bf16.128(<4 x float> {{.+}}, <8 x bfloat> {{.+}}, <4 x i1> {{.+}}) @@ -70,7 +70,7 @@ __m128bh test_mm_mask_cvtneps_pbh(__m128bh src, __mmask8 k, __m128 a) { __m128bh test_mm_maskz_cvtneps_pbh(__mmask8 k, __m128 a) { // CIR-LABEL: test_mm_maskz_cvtneps_pbh - // CIR: cir.call @_mm_maskz_cvtneps_pbh({{.+}}, {{.+}}) : (!u8i, !cir.vector<4 x !cir.float>) -> !cir.vector<8 x !cir.bf16> + // CIR: cir.call @_mm_maskz_cvtneps_pbh({{.+}}, {{.+}}) {nobuiltin, nobuiltins = [{{.*}}]} : (!u8i, !cir.vector<4 x !cir.float>) -> !cir.vector<8 x !cir.bf16> // LLVM-LABEL: @test_mm_maskz_cvtneps_pbh // LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.mask.cvtneps2bf16.128(<4 x float> {{.+}}, <8 x bfloat> {{.+}}, <4 x i1> {{.+}}) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vlfp16-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512vlfp16-builtins.c index 994fdfec23c2c..a9b5c74ba9afe 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vlfp16-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vlfp16-builtins.c @@ -12,7 +12,7 @@ _Float16 test_mm256_reduce_add_ph(__m256h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fadd" %[[R:.*]], %[[V:.*]] : (!cir.f16, !cir.vector<16 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm256_reduce_add_ph - // CIR: cir.call @_mm256_reduce_add_ph(%[[VEC:.*]]) : (!cir.vector<16 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm256_reduce_add_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm256_reduce_add_ph // LLVM: call half @llvm.vector.reduce.fadd.v16f16(half 0xH8000, <16 x half> %{{.*}}) @@ -27,7 +27,7 @@ _Float16 test_mm256_reduce_mul_ph(__m256h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmul" %[[R:.*]], %[[V:.*]] : (!cir.f16, !cir.vector<16 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm256_reduce_mul_ph - // CIR: cir.call @_mm256_reduce_mul_ph(%[[VEC:.*]]) : (!cir.vector<16 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm256_reduce_mul_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm256_reduce_mul_ph // LLVM: call half @llvm.vector.reduce.fmul.v16f16(half 0xH3C00, <16 x half> %{{.*}}) @@ -42,7 +42,7 @@ _Float16 test_mm256_reduce_max_ph(__m256h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmax" %[[V:.*]] (!cir.vector<16 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm256_reduce_max_ph - // CIR: cir.call @_mm256_reduce_max_ph(%[[VEC:.*]]) : (!cir.vector<16 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm256_reduce_max_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm256_reduce_max_ph // LLVM: call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %{{.*}}) @@ -57,7 +57,7 @@ _Float16 test_mm256_reduce_min_ph(__m256h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmin" %[[V:.*]] : (!cir.vector<16 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm256_reduce_min_ph - // CIR: cir.call @_mm256_reduce_min_ph(%[[VEC:.*]]) : (!cir.vector<16 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm256_reduce_min_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<16 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm256_reduce_min_ph // LLVM: call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %{{.*}}) @@ -72,7 +72,7 @@ _Float16 test_mm_reduce_add_ph(__m128h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fadd" %[[R:.*]], %[[V:.*]] : (!cir.f16, !cir.vector<8 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm_reduce_add_ph - // CIR: cir.call @_mm_reduce_add_ph(%[[VEC:.*]]) : (!cir.vector<8 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm_reduce_add_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm_reduce_add_ph // LLVM: call half @llvm.vector.reduce.fadd.v8f16(half 0xH8000, <8 x half> %{{.*}}) @@ -87,7 +87,7 @@ _Float16 test_mm_reduce_mul_ph(__m128h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmul" %[[R:.*]], %[[V:.*]] : (!cir.f16, !cir.vector<8 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm_reduce_mul_ph - // CIR: cir.call @_mm_reduce_mul_ph(%[[VEC:.*]]) : (!cir.vector<8 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm_reduce_mul_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm_reduce_mul_ph // LLVM: call half @llvm.vector.reduce.fmul.v8f16(half 0xH3C00, <8 x half> %{{.*}}) @@ -102,7 +102,7 @@ _Float16 test_mm_reduce_max_ph(__m128h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmax" %[[V:.*]] (!cir.vector<8 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm_reduce_max_ph - // CIR: cir.call @_mm_reduce_max_ph(%[[VEC:.*]]) : (!cir.vector<8 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm_reduce_max_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm_reduce_max_ph // LLVM: call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %{{.*}}) @@ -117,7 +117,7 @@ _Float16 test_mm_reduce_min_ph(__m128h __W) { // CIR: cir.call_llvm_intrinsic "vector.reduce.fmin" %[[V:.*]] : (!cir.vector<8 x !cir.f16>) -> !cir.f16 // CIR-LABEL: test_mm_reduce_min_ph - // CIR: cir.call @_mm_reduce_min_ph(%[[VEC:.*]]) : (!cir.vector<8 x !cir.f16>) -> !cir.f16 + // CIR: cir.call @_mm_reduce_min_ph(%[[VEC:.*]]) {nobuiltin, nobuiltins = [{{.*}}]} : (!cir.vector<8 x !cir.f16>) -> !cir.f16 // LLVM-LABEL: test_mm_reduce_min_ph // LLVM: call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %{{.*}}) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/keylocker.c b/clang/test/CIR/CodeGenBuiltins/X86/keylocker.c index a4995a108c8c8..6f4512c813820 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/keylocker.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/keylocker.c @@ -18,6 +18,8 @@ // CIR: !rec_anon_struct = !cir.record}> // CIR: !rec_anon_struct1 = !cir.record, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>}> +// CIR: !rec_anon_struct2 = !cir.record, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>}> +// CIR: !rec_anon_struct3 = !cir.record, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>, !cir.vector<2 x !u64i>}> unsigned char test_mm_aesenc256kl_u8(__m128i *odata, __m128i idata, const void *h) { // CIR-LABEL: _mm_aesenc256kl_u8 @@ -1174,3 +1176,152 @@ unsigned char test__mm_aesdecwide128kl_u8(__m128i odata[8], const __m128i idata[ // OGCG: ret i8 %[[RET]] return _mm_aesdecwide128kl_u8(odata, idata, h); } + +unsigned int test_encodekey128_u32(unsigned int htype, __m128i key, void *h) { + // CIR-LABEL: _mm_encodekey128_u32 + // CIR: %[[H:.*]] = cir.load {{.*}} : !cir.ptr>, !cir.ptr + // CIR: %[[OUT_PTR:.*]] = cir.cast bitcast %[[H]] : !cir.ptr -> !cir.ptr> + // CIR: %[[CALL:.*]] = cir.call_llvm_intrinsic "x86.encodekey128" {{.*}} : (!u32i, !cir.vector<2 x !s64i>) -> !rec_anon_struct2 + + // CIR: %[[X0:.*]] = cir.extract_member %[[CALL]][1] : !rec_anon_struct2 -> !cir.vector<2 x !u64i> + // CIR: %[[C0:.*]] = cir.const #cir.int<0> : !s32i + // CIR: %[[P0:.*]] = cir.ptr_stride %[[OUT_PTR]], %[[C0]] : (!cir.ptr>, !s32i) -> !cir.ptr> + // CIR: cir.store align(1) %[[X0]], %[[P0]] : !cir.vector<2 x !u64i>, !cir.ptr> + + // CIR: %[[X1:.*]] = cir.extract_member %[[CALL]][2] : !rec_anon_struct2 -> !cir.vector<2 x !u64i> + // CIR: %[[C1:.*]] = cir.const #cir.int<1> : !s32i + // CIR: %[[P1:.*]] = cir.ptr_stride %[[OUT_PTR]], %[[C1]] : (!cir.ptr>, !s32i) -> !cir.ptr> + // CIR: cir.store align(1) %[[X1]], %[[P1]] : !cir.vector<2 x !u64i>, !cir.ptr> + + // CIR: %[[X2:.*]] = cir.extract_member %[[CALL]][3] : !rec_anon_struct2 -> !cir.vector<2 x !u64i> + // CIR: %[[C2:.*]] = cir.const #cir.int<2> : !s32i + // CIR: %[[P2:.*]] = cir.ptr_stride %[[OUT_PTR]], %[[C2]] : (!cir.ptr>, !s32i) -> !cir.ptr> + // CIR: cir.store align(1) %[[X2]], %[[P2]] : !cir.vector<2 x !u64i>, !cir.ptr> + + // CIR: %[[RET_EXT:.*]] = cir.extract_member %[[CALL]][0] : !rec_anon_struct2 -> !u32i + // CIR: cir.store %[[RET_EXT]], %[[RET_PTR:.*]] : !u32i, !cir.ptr + // CIR: %[[RET:.*]] = cir.load %[[RET_PTR]] : !cir.ptr, !u32i + // CIR: cir.return %[[RET]] : !u32i + + // LLVM-LABEL: test_encodekey128_u32 + // LLVM: %[[CALL:.*]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 %{{.*}}, <2 x i64> %{{.*}}) + + // LLVM: %[[X0:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 1 + // LLVM: store <2 x i64> %[[X0]], ptr %[[OUT_PTR:.*]], align 1 + + // LLVM: %[[X1:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 2 + // LLVM: %[[P1:.*]] = getelementptr <2 x i64>, ptr %[[OUT_PTR]], i64 1 + // LLVM: store <2 x i64> %[[X1]], ptr %[[P1]], align 1 + + // LLVM: %[[X2:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 3 + // LLVM: %[[P2:.*]] = getelementptr <2 x i64>, ptr %[[OUT_PTR]], i64 2 + // LLVM: store <2 x i64> %[[X2]], ptr %[[P2]], align 1 + + // LLVM: %[[RET_EXT:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 0 + // LLVM: store i32 %[[RET_EXT]], ptr %[[RET_PTR1:.*]], align 4 + // LLVM: %[[RET1:.*]] = load i32, ptr %[[RET_PTR1:.*]], align 4 + // LLVM: store i32 %[[RET1]], ptr %[[RET_PTR:.*]], align 4 + // LLVM: %[[RET:.*]] = load i32, ptr %[[RET_PTR]], align 4 + // LLVM: ret i32 %[[RET]] + + // OGCG-LABEL: test_encodekey128_u32 + // OGCG: %[[OUT_PTR:.*]] = load ptr, ptr %__h.addr.i, align 8 + // OGCG: %[[CALL:.*]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 %{{.*}}, <2 x i64> %{{.*}}) + + // OGCG: %[[X0:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 1 + // OGCG: store <2 x i64> %[[X0]], ptr %[[OUT_PTR]], align 1 + + // OGCG: %[[X1:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 2 + // OGCG: %[[P1:.*]] = getelementptr i8, ptr %[[OUT_PTR]], i32 16 + // OGCG: store <2 x i64> %[[X1]], ptr %[[P1]], align 1 + + // OGCG: %[[X2:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 3 + // OGCG: %[[P2:.*]] = getelementptr i8, ptr %[[OUT_PTR]], i32 32 + // OGCG: store <2 x i64> %[[X2]], ptr %[[P2]], align 1 + + // OGCG: %[[RET:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 0 + // OGCG: ret i32 %[[RET]] + return _mm_encodekey128_u32(htype, key, h); +} + +unsigned int test_encodekey256_u32(unsigned int htype, __m128i key_lo, + __m128i key_hi, void *h) { + // CIR-LABEL: _mm_encodekey256_u32 + // CIR: %[[H:.*]] = cir.load {{.*}} : !cir.ptr>, !cir.ptr + // CIR: %[[OUT_PTR:.*]] = cir.cast bitcast %[[H]] : !cir.ptr -> !cir.ptr> + // CIR: %[[CALL:.*]] = cir.call_llvm_intrinsic "x86.encodekey256" {{.*}} : (!u32i, !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>) -> !rec_anon_struct3 + + // CIR: %[[X0:.*]] = cir.extract_member %[[CALL]][1] : !rec_anon_struct3 -> !cir.vector<2 x !u64i> + // CIR: %[[C0:.*]] = cir.const #cir.int<0> : !s32i + // CIR: %[[P0:.*]] = cir.ptr_stride %[[OUT_PTR]], %[[C0]] : (!cir.ptr>, !s32i) -> !cir.ptr> + // CIR: cir.store align(1) %[[X0]], %[[P0]] : !cir.vector<2 x !u64i>, !cir.ptr> + + // CIR: %[[X1:.*]] = cir.extract_member %[[CALL]][2] : !rec_anon_struct3 -> !cir.vector<2 x !u64i> + // CIR: %[[C1:.*]] = cir.const #cir.int<1> : !s32i + // CIR: %[[P1:.*]] = cir.ptr_stride %[[OUT_PTR]], %[[C1]] : (!cir.ptr>, !s32i) -> !cir.ptr> + // CIR: cir.store align(1) %[[X1]], %[[P1]] : !cir.vector<2 x !u64i>, !cir.ptr> + + // CIR: %[[X2:.*]] = cir.extract_member %[[CALL]][3] : !rec_anon_struct3 -> !cir.vector<2 x !u64i> + // CIR: %[[C2:.*]] = cir.const #cir.int<2> : !s32i + // CIR: %[[P2:.*]] = cir.ptr_stride %[[OUT_PTR]], %[[C2]] : (!cir.ptr>, !s32i) -> !cir.ptr> + // CIR: cir.store align(1) %[[X2]], %[[P2]] : !cir.vector<2 x !u64i>, !cir.ptr> + + // CIR: %[[X3:.*]] = cir.extract_member %[[CALL]][4] : !rec_anon_struct3 -> !cir.vector<2 x !u64i> + // CIR: %[[C3:.*]] = cir.const #cir.int<3> : !s32i + // CIR: %[[P3:.*]] = cir.ptr_stride %[[OUT_PTR]], %[[C3]] : (!cir.ptr>, !s32i) -> !cir.ptr> + // CIR: cir.store align(1) %[[X3]], %[[P3]] : !cir.vector<2 x !u64i>, !cir.ptr> + + // CIR: %[[RET_EXT:.*]] = cir.extract_member %[[CALL]][0] : !rec_anon_struct3 -> !u32i + // CIR: cir.store %[[RET_EXT]], %[[RET_PTR:.*]] : !u32i, !cir.ptr + // CIR: %[[RET:.*]] = cir.load %[[RET_PTR]] : !cir.ptr, !u32i + // CIR: cir.return %[[RET]] : !u32i + + // LLVM-LABEL: test_encodekey256_u32 + // LLVM: %[[CALL:.*]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey256(i32 %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + // LLVM: %[[X0:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 1 + // LLVM: store <2 x i64> %[[X0]], ptr %[[OUT_PTR:.*]], align 1 + + // LLVM: %[[X1:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 2 + // LLVM: %[[P1:.*]] = getelementptr <2 x i64>, ptr %[[OUT_PTR]], i64 1 + // LLVM: store <2 x i64> %[[X1]], ptr %[[P1]], align 1 + + // LLVM: %[[X2:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 3 + // LLVM: %[[P2:.*]] = getelementptr <2 x i64>, ptr %[[OUT_PTR]], i64 2 + // LLVM: store <2 x i64> %[[X2]], ptr %[[P2]], align 1 + + // LLVM: %[[X3:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 4 + // LLVM: %[[P3:.*]] = getelementptr <2 x i64>, ptr %[[OUT_PTR]], i64 3 + // LLVM: store <2 x i64> %[[X3]], ptr %[[P3]], align 1 + + // LLVM: %[[RET_EXT:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 0 + // LLVM: store i32 %[[RET_EXT]], ptr [[RET_PTR1:.*]], align 4 + // LLVM: %[[RET1:.*]] = load i32, ptr %[[RET_PTR1:.*]], align 4 + // LLVM: store i32 %[[RET1]], ptr %[[RET_PTR:.*]], align 4 + // LLVM: %[[RET:.*]] = load i32, ptr %[[RET_PTR]], align 4 + // LLVM: ret i32 %[[RET]] + + // OGCG-LABEL: test_encodekey256_u32 + // OGCG: %[[OUT_PTR:.*]] = load ptr, ptr %__h.addr.i, align 8 + // OGCG: %[[CALL:.*]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey256(i32 %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> %{{.*}}) + + // OGCG: %[[X0:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 1 + // OGCG: store <2 x i64> %[[X0]], ptr %[[OUT_PTR]], align 1 + + // OGCG: %[[X1:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 2 + // OGCG: %[[P1:.*]] = getelementptr i8, ptr %[[OUT_PTR]], i32 16 + // OGCG: store <2 x i64> %[[X1]], ptr %[[P1]], align 1 + + // OGCG: %[[X2:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 3 + // OGCG: %[[P2:.*]] = getelementptr i8, ptr %[[OUT_PTR]], i32 32 + // OGCG: store <2 x i64> %[[X2]], ptr %[[P2]], align 1 + + // OGCG: %[[X3:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 4 + // OGCG: %[[P3:.*]] = getelementptr i8, ptr %[[OUT_PTR]], i32 48 + // OGCG: store <2 x i64> %[[X3]], ptr %[[P3]], align 1 + + // OGCG: %[[RET_EXT:.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %[[CALL]], 0 + // OGCG: ret i32 %[[RET_EXT]] + + return _mm_encodekey256_u32(htype, key_lo, key_hi, h); +} diff --git a/clang/test/CIR/CodeGenBuiltins/builtin_new_delete.cpp b/clang/test/CIR/CodeGenBuiltins/builtin_new_delete.cpp index d540bfcf8a36d..52f1599a75e94 100644 --- a/clang/test/CIR/CodeGenBuiltins/builtin_new_delete.cpp +++ b/clang/test/CIR/CodeGenBuiltins/builtin_new_delete.cpp @@ -9,7 +9,7 @@ void test_builtins_basic() { __builtin_operator_delete(__builtin_operator_new(4)); // CIR-LABEL: test_builtins_basic - // CIR: [[P:%.*]] = cir.call @_Znwm({{%.*}}) : (!u64i) -> !cir.ptr + // CIR: [[P:%.*]] = cir.call @_Znwm({{%.*}}) {allocsize = array} : (!u64i) -> !cir.ptr // CIR: cir.call @_ZdlPv([[P]]) {{.*}}: (!cir.ptr) -> () // CIR: cir.return @@ -28,7 +28,7 @@ void test_sized_delete() { __builtin_operator_delete(__builtin_operator_new(4), 4); // CIR-LABEL: test_sized_delete - // CIR: [[P:%.*]] = cir.call @_Znwm({{%.*}}) : (!u64i) -> !cir.ptr + // CIR: [[P:%.*]] = cir.call @_Znwm({{%.*}}) {allocsize = array} : (!u64i) -> !cir.ptr // CIR: cir.call @_ZdlPvm([[P]], {{%.*}}) {{.*}}: (!cir.ptr, !u64i) -> () // CIR: cir.return diff --git a/clang/test/CIR/CodeGenCUDA/Inputs/cuda.h b/clang/test/CIR/CodeGenCUDA/Inputs/cuda.h new file mode 100644 index 0000000000000..225c7dfdcf0db --- /dev/null +++ b/clang/test/CIR/CodeGenCUDA/Inputs/cuda.h @@ -0,0 +1,80 @@ +/* Minimal declarations for CUDA support. Testing purposes only. */ +/* From test/CodeGenCUDA/Inputs/cuda.h. */ +#include + +#if __HIP__ || __CUDA__ +#define __constant__ __attribute__((constant)) +#define __device__ __attribute__((device)) +#define __global__ __attribute__((global)) +#define __host__ __attribute__((host)) +#define __shared__ __attribute__((shared)) +#if __HIP__ +#define __managed__ __attribute__((managed)) +#endif +#define __launch_bounds__(...) __attribute__((launch_bounds(__VA_ARGS__))) +#define __grid_constant__ __attribute__((grid_constant)) +#else +#define __constant__ +#define __device__ +#define __global__ +#define __host__ +#define __shared__ +#define __managed__ +#define __launch_bounds__(...) +#define __grid_constant__ +#endif + +struct dim3 { + unsigned x, y, z; + __host__ __device__ dim3(unsigned x, unsigned y = 1, unsigned z = 1) : x(x), y(y), z(z) {} +}; + +#if __HIP__ || HIP_PLATFORM +typedef struct hipStream *hipStream_t; +typedef enum hipError {} hipError_t; +int hipConfigureCall(dim3 gridSize, dim3 blockSize, size_t sharedSize = 0, + hipStream_t stream = 0); +extern "C" hipError_t __hipPushCallConfiguration(dim3 gridSize, dim3 blockSize, + size_t sharedSize = 0, + hipStream_t stream = 0); +extern "C" int __hipPopCallConfiguration(dim3 *gridSize, dim3 *blockSize, + size_t *sharedSize, + hipStream_t *stream); +#ifndef __HIP_API_PER_THREAD_DEFAULT_STREAM__ +extern "C" hipError_t hipLaunchKernel(const void *func, dim3 gridDim, + dim3 blockDim, void **args, + size_t sharedMem, + hipStream_t stream); +#else +extern "C" hipError_t hipLaunchKernel_spt(const void *func, dim3 gridDim, + dim3 blockDim, void **args, + size_t sharedMem, + hipStream_t stream); +#endif // __HIP_API_PER_THREAD_DEFAULT_STREAM__ +#elif __OFFLOAD_VIA_LLVM__ +extern "C" unsigned __llvmPushCallConfiguration(dim3 gridDim, dim3 blockDim, + size_t sharedMem = 0, void *stream = 0); +extern "C" unsigned llvmLaunchKernel(const void *func, dim3 gridDim, dim3 blockDim, + void **args, size_t sharedMem = 0, void *stream = 0); +#else +typedef struct cudaStream *cudaStream_t; +typedef enum cudaError {} cudaError_t; +extern "C" int cudaConfigureCall(dim3 gridSize, dim3 blockSize, + size_t sharedSize = 0, + cudaStream_t stream = 0); +extern "C" int __cudaPushCallConfiguration(dim3 gridSize, dim3 blockSize, + size_t sharedSize = 0, + cudaStream_t stream = 0); +extern "C" int __cudaPopCallConfiguration(dim3 *gridSize, dim3 *blockSize, + size_t *sharedSize, + cudaStream_t *stream); +extern "C" cudaError_t cudaLaunchKernel(const void *func, dim3 gridDim, + dim3 blockDim, void **args, + size_t sharedMem, cudaStream_t stream); +extern "C" cudaError_t cudaLaunchKernel_ptsz(const void *func, dim3 gridDim, + dim3 blockDim, void **args, + size_t sharedMem, cudaStream_t stream); + +#endif + +extern "C" __device__ int printf(const char*, ...); diff --git a/clang/test/CIR/CodeGenCUDA/filter-decl.cu b/clang/test/CIR/CodeGenCUDA/filter-decl.cu new file mode 100644 index 0000000000000..a2a7e9ba9a1b0 --- /dev/null +++ b/clang/test/CIR/CodeGenCUDA/filter-decl.cu @@ -0,0 +1,55 @@ +// Based on clang/test/CodeGenCUDA/filter-decl.cu tailored for CIR current capabilities. +// Tests that host/device functions are emitted only on the appropriate side. + +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-sdk-version=9.2 \ +// RUN: -x cuda -emit-cir %s -o %t.host.cir +// RUN: FileCheck --input-file=%t.host.cir %s --check-prefix=CIR-HOST + +// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -x cuda \ +// RUN: -fcuda-is-device -emit-cir %s -o %t.device.cir +// RUN: FileCheck --input-file=%t.device.cir %s --check-prefix=CIR-DEVICE + +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-sdk-version=9.2 \ +// RUN: -x cuda -emit-llvm %s -o %t.host.ll +// RUN: FileCheck --input-file=%t.host.ll %s --check-prefix=OGCG-HOST + +// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -x cuda \ +// RUN: -fcuda-is-device -emit-llvm %s -o %t.device.ll +// RUN: FileCheck --input-file=%t.device.ll %s --check-prefix=OGCG-DEVICE + +#include "Inputs/cuda.h" + +// Implicit host function (no attribute) — host only +// CIR-HOST: cir.func {{.*}} @_Z20implicithostonlyfuncv() +// CIR-DEVICE-NOT: @_Z20implicithostonlyfuncv +// OGCG-HOST: define{{.*}} void @_Z20implicithostonlyfuncv() +// OGCG-DEVICE-NOT: @_Z20implicithostonlyfuncv +void implicithostonlyfunc(void) {} + +// Explicit __host__ function — host only +// CIR-HOST: cir.func {{.*}} @_Z20explicithostonlyfuncv() +// CIR-DEVICE-NOT: @_Z20explicithostonlyfuncv +// OGCG-HOST: define{{.*}} void @_Z20explicithostonlyfuncv() +// OGCG-DEVICE-NOT: @_Z20explicithostonlyfuncv +__host__ void explicithostonlyfunc(void) {} + +// __device__ function — device only +// CIR-HOST-NOT: @_Z14deviceonlyfuncv +// CIR-DEVICE: cir.func {{.*}} @_Z14deviceonlyfuncv() +// OGCG-HOST-NOT: @_Z14deviceonlyfuncv +// OGCG-DEVICE: define{{.*}} void @_Z14deviceonlyfuncv() +__device__ void deviceonlyfunc(void) {} + +// __host__ __device__ function — both sides +// CIR-HOST: cir.func {{.*}} @_Z14hostdevicefuncv() +// CIR-DEVICE: cir.func {{.*}} @_Z14hostdevicefuncv() +// OGCG-HOST: define{{.*}} void @_Z14hostdevicefuncv() +// OGCG-DEVICE: define{{.*}} void @_Z14hostdevicefuncv() +__host__ __device__ void hostdevicefunc(void) {} + +// __global__ kernel — both sides (stub on host, kernel on device) +// CIR-HOST: cir.func {{.*}} @_Z25__device_stub__globalfuncv() +// CIR-DEVICE: cir.func {{.*}} @_Z10globalfuncv() +// OGCG-HOST: define{{.*}} void @_Z25__device_stub__globalfuncv() +// OGCG-DEVICE: define{{.*}} void @_Z10globalfuncv() +__global__ void globalfunc(void) {} diff --git a/clang/test/CIR/CodeGenCUDA/kernel-call.cu b/clang/test/CIR/CodeGenCUDA/kernel-call.cu new file mode 100644 index 0000000000000..3e0a788a96d98 --- /dev/null +++ b/clang/test/CIR/CodeGenCUDA/kernel-call.cu @@ -0,0 +1,50 @@ +// Based on clang/test/CodeGenCUDA/kernel-call.cu. +// Tests device stub body emission for CUDA kernels. + +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-sdk-version=9.2 \ +// RUN: -emit-cir %s -x cuda -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CUDA-NEW + + +#include "Inputs/cuda.h" + + +// TODO: Test CUDA legacy (< 9.0) when legacy stub body is implemented +// TODO: Test HIP when HIP stub body support is complete + +// Check that the stub function is generated with the correct name +// CUDA-NEW-LABEL: cir.func {{.*}} @_Z21__device_stub__kernelif +// +// Check kernel arguments are allocated as local variables +// CUDA-NEW-DAG: cir.alloca !s32i, {{.*}} ["x", init] +// CUDA-NEW-DAG: cir.alloca !cir.float, {{.*}} ["y", init] +// +// Check void *args[] array is created with correct size (2 args) +// CUDA-NEW: cir.alloca !cir.array x 2>, {{.*}} ["kernel_args"] +// CUDA-NEW: cir.cast array_to_ptrdecay +// +// Check arguments are stored in the args array via ptr_stride indexing +// CUDA-NEW: cir.const #cir.int<0> +// CUDA-NEW: cir.ptr_stride +// CUDA-NEW: cir.cast bitcast {{.*}} -> !cir.ptr +// CUDA-NEW: cir.store {{.*}} !cir.ptr, !cir.ptr> +// CUDA-NEW: cir.const #cir.int<1> +// CUDA-NEW: cir.ptr_stride +// CUDA-NEW: cir.cast bitcast {{.*}} -> !cir.ptr +// CUDA-NEW: cir.store {{.*}} !cir.ptr, !cir.ptr> +// +// Check dim3 grid_dim and block_dim allocas for launch configuration +// CUDA-NEW-DAG: cir.alloca !rec_dim3, {{.*}} ["grid_dim"] +// CUDA-NEW-DAG: cir.alloca !rec_dim3, {{.*}} ["block_dim"] +// +// Check shared_mem (size_t) and stream allocas +// CUDA-NEW-DAG: cir.alloca !u64i, {{.*}} ["shared_mem"] +// CUDA-NEW-DAG: cir.alloca !cir.ptr, {{.*}} ["stream"] +// +// Check __cudaPopCallConfiguration is called with correct argument types +// CUDA-NEW: cir.call @__cudaPopCallConfiguration({{.*}}) : (!cir.ptr, !cir.ptr, !cir.ptr, !cir.ptr>) -> !s32i +// +// Check cudaLaunchKernel is called with all 6 arguments: +// func ptr, gridDim, blockDim, args, sharedMem, stream +// CUDA-NEW: cir.call @cudaLaunchKernel({{.*}}) : (!cir.ptr, !rec_dim3, !rec_dim3, !cir.ptr>, !u64i, !cir.ptr) -> !u32i +__global__ void kernel(int x, float y) {} diff --git a/clang/test/CIR/CodeGenCUDA/kernel-stub-name.cu b/clang/test/CIR/CodeGenCUDA/kernel-stub-name.cu new file mode 100644 index 0000000000000..63c241a0e12e2 --- /dev/null +++ b/clang/test/CIR/CodeGenCUDA/kernel-stub-name.cu @@ -0,0 +1,22 @@ +// Based on clang/test/CodeGenCUDA/kernel-stub-name.cu. + +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -target-sdk-version=9.2 \ +// RUN: -emit-cir %s -x cuda -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s + +#include "Inputs/cuda.h" + +// CHECK: cir.func {{.*}} @[[CSTUB:__device_stub__ckernel]]() +// CHECK: cir.return +// CHECK-NEXT: } +extern "C" __global__ void ckernel() {} + +// CHECK: cir.func {{.*}} @_ZN2ns23__device_stub__nskernelEv() +namespace ns { +__global__ void nskernel() {} +} // namespace ns + +// CHECK: cir.func {{.*}} @_Z25__device_stub__kernelfuncIiEvv() +template +__global__ void kernelfunc() {} +template __global__ void kernelfunc(); diff --git a/clang/test/CIR/CodeGenCUDA/nvptx-basic.cu b/clang/test/CIR/CodeGenCUDA/nvptx-basic.cu new file mode 100644 index 0000000000000..99f0164a18506 --- /dev/null +++ b/clang/test/CIR/CodeGenCUDA/nvptx-basic.cu @@ -0,0 +1,30 @@ +// Based on clang/test/CodeGenCUDA/ptx-kernels.cu tailored for CIR current capabilities. +// Tests basic device-side compilation with NVPTX target. + +// RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -x cuda \ +// RUN: -fcuda-is-device -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s + +#include "Inputs/cuda.h" + +// CHECK: cir.func {{.*}} @device_function() +extern "C" +__device__ void device_function() {} + +// CHECK: cir.func {{.*}} @global_function() +// CHECK: cir.call @device_function() +extern "C" +__global__ void global_function() { + device_function(); +} + +// Template kernel with explicit instantiation +template __global__ void templated_kernel(T param) {} +template __global__ void templated_kernel(int); +// CHECK: cir.func {{.*}} @_Z16templated_kernelIiEvT_ + +// Anonymous namespace kernel +namespace { +__global__ void anonymous_ns_kernel() {} +// CHECK: cir.func {{.*}} @_ZN12_GLOBAL__N_119anonymous_ns_kernelEv +} diff --git a/clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl b/clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl new file mode 100644 index 0000000000000..279075a6dab60 --- /dev/null +++ b/clang/test/CIR/CodeGenHLSL/matrix-element-expr-load.hlsl @@ -0,0 +1,8 @@ +// RUN: not %clang_cc1 -x hlsl -finclude-default-header -triple spirv-unknown-vulkan-compute %s \ +// RUN: -fclangir -emit-cir -disable-llvm-passes 2>&1 | FileCheck %s + +// CHECK: ClangIR code gen Not Yet Implemented: processing of type: ConstantMatrix +float1 test_zero_indexed(float2x2 M) { + // CHECK: ClangIR code gen Not Yet Implemented: ScalarExprEmitter: matrix element + return M._m00; +} diff --git a/clang/test/CIR/CodeGenOpenMP/not-yet-implemented.c b/clang/test/CIR/CodeGenOpenMP/not-yet-implemented.c index 78a0bc8b2d416..6d59f45d6e5e4 100644 --- a/clang/test/CIR/CodeGenOpenMP/not-yet-implemented.c +++ b/clang/test/CIR/CodeGenOpenMP/not-yet-implemented.c @@ -12,8 +12,7 @@ void do_things() { int i; // TODO(OMP): We might consider overloading operator<< for OMPClauseKind in // the future if we want to improve this. - // expected-error@+2{{ClangIR code gen Not Yet Implemented: OpenMPClause : if}} - // expected-error@+2{{ClangIR code gen Not Yet Implemented: emitStmt: CapturedStmt}} + // expected-error@+1{{ClangIR code gen Not Yet Implemented: OpenMPClause : if}} #pragma omp parallel if(i) {} } diff --git a/clang/test/CIR/CodeGenOpenMP/omp-llvmir.c b/clang/test/CIR/CodeGenOpenMP/omp-llvmir.c new file mode 100644 index 0000000000000..d32753ae4475b --- /dev/null +++ b/clang/test/CIR/CodeGenOpenMP/omp-llvmir.c @@ -0,0 +1,169 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp -fclangir -emit-llvm %s -o %t-cir.ll +// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fopenmp -emit-llvm %s -o %t.ll +// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG + +// CIR-LABEL: cir.func no_inline no_proto dso_local @main() -> !s32i { +// CIR: [[RETVAL:%.*]] = cir.alloca !s32i, !cir.ptr, ["__retval"] {alignment = 4 : i64} +// CIR: [[J:%.*]] = cir.alloca !s32i, !cir.ptr, ["j"] {alignment = 4 : i64} +// CIR: omp.parallel { +// CIR: cir.scope { +// CIR: [[I:%.*]] = cir.alloca !s32i, !cir.ptr, ["i", init] {alignment = 4 : i64} +// CIR: [[ZERO1:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: cir.store align(4) [[ZERO1]], [[I]] : !s32i, !cir.ptr +// CIR: cir.for : cond { +// CIR: [[LOAD1:%.*]] = cir.load align(4) [[I]] : !cir.ptr, !s32i +// CIR: [[LIMIT:%.*]] = cir.const #cir.int<10000> : !s32i +// CIR: [[CMP:%.*]] = cir.cmp(lt, [[LOAD1]], [[LIMIT]]) : !s32i, !cir.bool +// CIR: cir.condition([[CMP]]) +// CIR: } body { +// CIR: [[ZERO2:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: cir.store align(4) [[ZERO2]], [[J]] : !s32i, !cir.ptr +// CIR: cir.yield +// CIR: } step { +// CIR: [[LOAD2:%.*]] = cir.load align(4) [[I]] : !cir.ptr, !s32i +// CIR: [[ONE:%.*]] = cir.const #cir.int<1> : !s32i +// CIR: [[ADD:%.*]] = cir.binop(add, [[LOAD2]], [[ONE]]) nsw : !s32i +// CIR: cir.store align(4) [[ADD]], [[I]] : !s32i, !cir.ptr +// CIR: cir.yield +// CIR: } +// CIR: } +// CIR: omp.terminator +// CIR: } +// CIR: [[ZERO3:%.*]] = cir.const #cir.int<0> : !s32i +// CIR: cir.store [[ZERO3]], [[RETVAL]] : !s32i, !cir.ptr +// CIR: [[RET:%.*]] = cir.load [[RETVAL]] : !cir.ptr, !s32i +// CIR: cir.return [[RET]] : !s32i +// CIR: } + +// LLVM-LABEL: define dso_local i32 @main() +// LLVM: %[[STRUCTARG:.*]] = alloca { ptr, ptr }, align 8 +// LLVM: %[[VAR1:.*]] = alloca i32, i64 1, align 4 +// LLVM: %[[VAR2:.*]] = alloca i32, i64 1, align 4 +// LLVM: %[[VAR3:.*]] = alloca i32, i64 1, align 4 +// LLVM: br label %[[ENTRY:.*]] + +// LLVM: [[ENTRY]]: +// LLVM: %[[THREAD_NUM:.*]] = call i32 @__kmpc_global_thread_num(ptr @1) +// LLVM: br label %[[OMP_PARALLEL:.*]] + +// LLVM: [[OMP_PARALLEL]]: +// LLVM: %[[GEP1:.*]] = getelementptr { ptr, ptr }, ptr %[[STRUCTARG]], i32 0, i32 0 +// LLVM: store ptr %[[VAR1]], ptr %[[GEP1]], align 8 +// LLVM: %[[GEP2:.*]] = getelementptr { ptr, ptr }, ptr %[[STRUCTARG]], i32 0, i32 1 +// LLVM: store ptr %[[VAR3]], ptr %[[GEP2]], align 8 +// LLVM: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @1, i32 1, ptr @main..omp_par, ptr %[[STRUCTARG]]) +// LLVM: br label %[[OMP_PAR_EXIT:.*]] + +// LLVM: [[OMP_PAR_EXIT]]: +// LLVM: store i32 0, ptr %[[VAR2]], align 4 +// LLVM: %[[LOAD:.*]] = load i32, ptr %[[VAR2]], align 4 +// LLVM: ret i32 %[[LOAD]] + +// LLVM-LABEL: define internal void @main..omp_par(ptr noalias %{{.*}}, ptr noalias %{{.*}}, ptr %{{.*}}) +// LLVM: [[PAR_ENTRY:.*]]: +// LLVM: %[[GEP_A:.*]] = getelementptr { ptr, ptr }, ptr %{{.*}}, i32 0, i32 0 +// LLVM: %[[LOAD_A:.*]] = load ptr, ptr %[[GEP_A]], align 8 +// LLVM: %[[GEP_B:.*]] = getelementptr { ptr, ptr }, ptr %{{.*}}, i32 0, i32 1 +// LLVM: %[[LOAD_B:.*]] = load ptr, ptr %[[GEP_B]], align 8 +// LLVM: %[[TID_LOCAL:.*]] = alloca i32, align 4 +// LLVM: %[[TID_VAL:.*]] = load i32, ptr %{{.*}}, align 4 +// LLVM: store i32 %[[TID_VAL]], ptr %[[TID_LOCAL]], align 4 +// LLVM: %{{.*}} = load i32, ptr %[[TID_LOCAL]], align 4 +// LLVM: br label %[[AFTER_ALLOCA:.*]] + +// LLVM: [[AFTER_ALLOCA]]: +// LLVM: br label %[[PAR_REGION:.*]] + +// LLVM: [[PAR_REGION]]: +// LLVM: br label %[[PAR_REGION1:.*]] + +// LLVM: [[PAR_REGION1]]: +// LLVM: br label %[[PAR_REGION2:.*]] + +// LLVM: [[PAR_REGION2]]: +// LLVM: store i32 0, ptr %[[LOAD_A]], align 4 +// LLVM: br label %[[PAR_REGION3:.*]] + +// LLVM: [[PAR_REGION3]]: +// LLVM: %[[I_LOAD:.*]] = load i32, ptr %[[LOAD_A]], align 4 +// LLVM: %[[CMP:.*]] = icmp slt i32 %[[I_LOAD]], 10000 +// LLVM: br i1 %[[CMP]], label %[[PAR_REGION4:.*]], label %[[PAR_REGION6:.*]] + +// LLVM: [[PAR_REGION6]]: +// LLVM: br label %[[PAR_REGION7:.*]] + +// LLVM: [[PAR_REGION7]]: +// LLVM: br label %[[REGION_CONT:.*]] + +// LLVM: [[REGION_CONT]]: +// LLVM: br label %[[PRE_FINALIZE:.*]] + +// LLVM: [[PRE_FINALIZE]]: +// LLVM: br label %[[FINI:.*]] + +// LLVM: [[FINI]]: +// LLVM: br label %[[EXIT_STUB:.*]] + +// LLVM: [[PAR_REGION4]]: +// LLVM: store i32 0, ptr %[[LOAD_B]], align 4 +// LLVM: br label %[[PAR_REGION5:.*]] + +// LLVM: [[PAR_REGION5]]: +// LLVM: %[[I_LOAD2:.*]] = load i32, ptr %[[LOAD_A]], align 4 +// LLVM: %[[ADD:.*]] = add nsw i32 %[[I_LOAD2]], 1 +// LLVM: store i32 %[[ADD]], ptr %[[LOAD_A]], align 4 +// LLVM: br label %[[PAR_REGION3]] + +// LLVM: [[EXIT_STUB]]: +// LLVM: ret void + +// OGCG-LABEL: define dso_local i32 @main() +// OGCG: [[ENTRY:.*]]: +// OGCG: %[[RETVAL:.*]] = alloca i32, align 4 +// OGCG: %[[J:.*]] = alloca i32, align 4 +// OGCG: store i32 0, ptr %[[RETVAL]], align 4 +// OGCG: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @1, i32 1, ptr @main.omp_outlined, ptr %[[J]]) +// OGCG: ret i32 0 + +// OGCG-LABEL: define internal void @main.omp_outlined(ptr noalias noundef %{{.*}}, ptr noalias noundef %{{.*}}, ptr noundef nonnull align 4 dereferenceable(4) %{{.*}}) +// OGCG: [[OUTLINED_ENTRY:.*]]: +// OGCG: %[[GLOBAL_TID_ADDR:.*]] = alloca ptr, align 8 +// OGCG: %[[BOUND_TID_ADDR:.*]] = alloca ptr, align 8 +// OGCG: %[[J_ADDR:.*]] = alloca ptr, align 8 +// OGCG: %[[I:.*]] = alloca i32, align 4 +// OGCG: store ptr %{{.*}}, ptr %[[GLOBAL_TID_ADDR]], align 8 +// OGCG: store ptr %{{.*}}, ptr %[[BOUND_TID_ADDR]], align 8 +// OGCG: store ptr %{{.*}}, ptr %[[J_ADDR]], align 8 +// OGCG: %[[J_LOAD:.*]] = load ptr, ptr %[[J_ADDR]], align 8 +// OGCG: store i32 0, ptr %[[I]], align 4 +// OGCG: br label %[[FOR_COND:.*]] + +// OGCG: [[FOR_COND]]: +// OGCG: %[[I_LOAD:.*]] = load i32, ptr %[[I]], align 4 +// OGCG: %[[CMP:.*]] = icmp slt i32 %[[I_LOAD]], 10000 +// OGCG: br i1 %[[CMP]], label %[[FOR_BODY:.*]], label %[[FOR_END:.*]] + +// OGCG: [[FOR_BODY]]: +// OGCG: store i32 0, ptr %[[J_LOAD]], align 4 +// OGCG: br label %[[FOR_INC:.*]] + +// OGCG: [[FOR_INC]]: +// OGCG: %[[I_LOAD2:.*]] = load i32, ptr %[[I]], align 4 +// OGCG: %[[ADD:.*]] = add nsw i32 %[[I_LOAD2]], 1 +// OGCG: store i32 %[[ADD]], ptr %[[I]], align 4 +// OGCG: br label %[[FOR_COND]] + +// OGCG: [[FOR_END]]: +// OGCG: ret void + +int main() { + int j; +#pragma omp parallel + for (int i = 0; i < 10000; i=i+1) + j = 0; + + return 0; +} diff --git a/clang/test/CIR/CodeGenOpenMP/parallel.c b/clang/test/CIR/CodeGenOpenMP/parallel.c index a2bfc8f4ce82e..fcf3683cfb6c4 100644 --- a/clang/test/CIR/CodeGenOpenMP/parallel.c +++ b/clang/test/CIR/CodeGenOpenMP/parallel.c @@ -18,11 +18,11 @@ void emit_simple_parallel() { // CHECK-NEXT: } #pragma omp parallel { - // TODO(OMP): We don't yet emit captured stmt, so the body of this is lost,x - // thus we don't emit the 'during' call. during(i); } // CHECK-NEXT: omp.parallel { + // CHECK-NEXT: {{.*}} = cir.load align(4) %{{.*}} : !cir.ptr, !s32i + // CHECK-NEXT: cir.call @during(%{{.*}}) : (!s32i) -> () // CHECK-NEXT: omp.terminator // CHECK-NEXT: } @@ -41,10 +41,18 @@ void parallel_with_operations() { // lines will need updating. #pragma omp parallel shared(a) firstprivate(b) { - ++a; - ++b; + a = a + 1; + b = b + 1; } // CHECK-NEXT: omp.parallel { + // CHECK-NEXT: cir.load align(4) %{{.*}} + // CHECK-NEXT: cir.const #cir.int<1> : !s32i + // CHECK-NEXT: cir.binop(add, %{{.*}}, %{{.*}}) nsw : !s32i + // CHECK-NEXT: cir.store align(4) %{{.*}}, %{{.*}} : !s32i, !cir.ptr + // CHECK-NEXT: cir.load align(4) %{{.*}} + // CHECK-NEXT: cir.const #cir.int<1> : !s32i + // CHECK-NEXT: cir.binop(add, %{{.*}}, %{{.*}}) nsw : !s32i + // CHECK-NEXT: cir.store align(4) %{{.*}}, %{{.*}} : !s32i, !cir.ptr // CHECK-NEXT: omp.terminator // CHECK-NEXT: } } diff --git a/clang/test/CIR/IR/atomic.cir b/clang/test/CIR/IR/atomic.cir index 790297ff99f47..c58cf472bb5f0 100644 --- a/clang/test/CIR/IR/atomic.cir +++ b/clang/test/CIR/IR/atomic.cir @@ -5,18 +5,18 @@ cir.func @atomic_xchg(%ptr: !cir.ptr, %val: !s32i) { // CHECK-LABEL: @atomic_xchg - %0 = cir.atomic.xchg relaxed %ptr, %val : (!cir.ptr, !s32i) -> !s32i - // CHECK: cir.atomic.xchg relaxed %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - %1 = cir.atomic.xchg consume %ptr, %val : (!cir.ptr, !s32i) -> !s32i - // CHECK: cir.atomic.xchg consume %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - %2 = cir.atomic.xchg acquire %ptr, %val : (!cir.ptr, !s32i) -> !s32i - // CHECK: cir.atomic.xchg acquire %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - %3 = cir.atomic.xchg release %ptr, %val : (!cir.ptr, !s32i) -> !s32i - // CHECK: cir.atomic.xchg release %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - %4 = cir.atomic.xchg acq_rel %ptr, %val : (!cir.ptr, !s32i) -> !s32i - // CHECK: cir.atomic.xchg acq_rel %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i - %5 = cir.atomic.xchg seq_cst %ptr, %val : (!cir.ptr, !s32i) -> !s32i - // CHECK: cir.atomic.xchg seq_cst %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + %0 = cir.atomic.xchg relaxed syncscope(system) %ptr, %val : (!cir.ptr, !s32i) -> !s32i + // CHECK: cir.atomic.xchg relaxed syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + %1 = cir.atomic.xchg consume syncscope(system) %ptr, %val : (!cir.ptr, !s32i) -> !s32i + // CHECK: cir.atomic.xchg consume syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + %2 = cir.atomic.xchg acquire syncscope(system) %ptr, %val : (!cir.ptr, !s32i) -> !s32i + // CHECK: cir.atomic.xchg acquire syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + %3 = cir.atomic.xchg release syncscope(system) %ptr, %val : (!cir.ptr, !s32i) -> !s32i + // CHECK: cir.atomic.xchg release syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + %4 = cir.atomic.xchg acq_rel syncscope(system) %ptr, %val : (!cir.ptr, !s32i) -> !s32i + // CHECK: cir.atomic.xchg acq_rel syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i + %5 = cir.atomic.xchg seq_cst syncscope(system) %ptr, %val : (!cir.ptr, !s32i) -> !s32i + // CHECK: cir.atomic.xchg seq_cst syncscope(system) %{{.+}}, %{{.+}} : (!cir.ptr, !s32i) -> !s32i cir.return } diff --git a/clang/test/CIR/IR/cleanup-scope.cir b/clang/test/CIR/IR/cleanup-scope.cir new file mode 100644 index 0000000000000..614a753d5abd7 --- /dev/null +++ b/clang/test/CIR/IR/cleanup-scope.cir @@ -0,0 +1,136 @@ +// RUN: cir-opt %s --verify-roundtrip | FileCheck %s + +!s32i = !cir.int + +module { + +// Test basic cleanup.scope with all cleanup kind (normal + eh) +cir.func @cleanup_scope_all() { + cir.cleanup.scope { + cir.yield + } cleanup all { + cir.yield + } + cir.return +} + +// CHECK: cir.func @cleanup_scope_all() { +// CHECK: cir.cleanup.scope { +// CHECK: cir.yield +// CHECK: } cleanup all { +// CHECK: cir.yield +// CHECK: } +// CHECK: cir.return +// CHECK: } + +// Test cleanup.scope with normal-only cleanup +cir.func @cleanup_scope_normal() { + cir.cleanup.scope { + cir.yield + } cleanup normal { + cir.yield + } + cir.return +} + +// CHECK: cir.func @cleanup_scope_normal() { +// CHECK: cir.cleanup.scope { +// CHECK: cir.yield +// CHECK: } cleanup normal { +// CHECK: cir.yield +// CHECK: } +// CHECK: cir.return +// CHECK: } + +// Test cleanup.scope with EH-only cleanup +cir.func @cleanup_scope_eh() { + cir.cleanup.scope { + cir.yield + } cleanup eh { + cir.yield + } + cir.return +} + +// CHECK: cir.func @cleanup_scope_eh() { +// CHECK: cir.cleanup.scope { +// CHECK: cir.yield +// CHECK: } cleanup eh { +// CHECK: cir.yield +// CHECK: } +// CHECK: cir.return +// CHECK: } + +// Test nested cleanup.scope operations +cir.func @nested_cleanup_scopes() { + cir.cleanup.scope { + cir.cleanup.scope { + cir.yield + } cleanup all { + cir.yield + } + cir.yield + } cleanup all { + cir.yield + } + cir.return +} + +// CHECK: cir.func @nested_cleanup_scopes() { +// CHECK: cir.cleanup.scope { +// CHECK: cir.cleanup.scope { +// CHECK: cir.yield +// CHECK: } cleanup all { +// CHECK: cir.yield +// CHECK: } +// CHECK: cir.yield +// CHECK: } cleanup all { +// CHECK: cir.yield +// CHECK: } +// CHECK: cir.return +// CHECK: } + +// Test cleanup.scope inside cir.scope +cir.func @cleanup_in_scope() { + cir.scope { + cir.cleanup.scope { + cir.yield + } cleanup all { + cir.yield + } + } + cir.return +} + +// CHECK: cir.func @cleanup_in_scope() { +// CHECK: cir.scope { +// CHECK: cir.cleanup.scope { +// CHECK: cir.yield +// CHECK: } cleanup all { +// CHECK: cir.yield +// CHECK: } +// CHECK: } +// CHECK: cir.return +// CHECK: } + + +// Test basic cleanup.scope with all cleanup kind (normal + eh) +cir.func @return_within_cleanup() { + cir.cleanup.scope { + cir.return + } cleanup all { + cir.yield + } + cir.return +} + +// CHECK: cir.func @return_within_cleanup() { +// CHECK: cir.cleanup.scope { +// CHECK: cir.return +// CHECK: } cleanup all { +// CHECK: cir.yield +// CHECK: } +// CHECK: cir.return +// CHECK: } + +} diff --git a/clang/test/CIR/IR/eh-flat.cir b/clang/test/CIR/IR/eh-flat.cir new file mode 100644 index 0000000000000..c6799dcda766c --- /dev/null +++ b/clang/test/CIR/IR/eh-flat.cir @@ -0,0 +1,225 @@ +// RUN: cir-opt %s --verify-roundtrip | FileCheck %s + +!u8i = !cir.int +!s32i = !cir.int +!void = !cir.void + +module { + +cir.global "private" constant external @_ZTIi : !cir.ptr +cir.global "private" constant external @_ZTIPKc : !cir.ptr + +// Test cir.eh.initiate without cleanup +cir.func @eh_initiate_basic(%arg0: !cir.ptr) { + cir.br ^bb1 +^bb1: + %eh_token = cir.eh.initiate : !cir.eh_token + cir.br ^bb2(%eh_token : !cir.eh_token) +^bb2(%tok: !cir.eh_token): + cir.return +} + +// CHECK: cir.func @eh_initiate_basic(%arg0: !cir.ptr) { +// CHECK: cir.br ^bb1 +// CHECK: ^bb1: +// CHECK: %[[TOKEN:.*]] = cir.eh.initiate : !cir.eh_token +// CHECK: cir.br ^bb2(%[[TOKEN]] : !cir.eh_token) +// CHECK: ^bb2(%{{.*}}: !cir.eh_token): +// CHECK: cir.return +// CHECK: } + +// Test cir.eh.initiate with cleanup +cir.func @eh_initiate_cleanup(%arg0: !cir.ptr) { + cir.br ^bb1 +^bb1: + %eh_token = cir.eh.initiate cleanup : !cir.eh_token + cir.br ^bb2(%eh_token : !cir.eh_token) +^bb2(%tok: !cir.eh_token): + cir.return +} + +// CHECK: cir.func @eh_initiate_cleanup(%arg0: !cir.ptr) { +// CHECK: cir.br ^bb1 +// CHECK: ^bb1: +// CHECK: %[[TOKEN:.*]] = cir.eh.initiate cleanup : !cir.eh_token +// CHECK: cir.br ^bb2(%[[TOKEN]] : !cir.eh_token) +// CHECK: ^bb2(%{{.*}}: !cir.eh_token): +// CHECK: cir.return +// CHECK: } + +// Test cir.eh.dispatch with catch_all +cir.func @eh_dispatch_catch_all(%eh_token: !cir.eh_token) { + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch_all : ^bb1 + ] +^bb1: + cir.return +} + +// CHECK: cir.func @eh_dispatch_catch_all(%arg0: !cir.eh_token) { +// CHECK: cir.eh.dispatch %arg0 : !cir.eh_token [ +// CHECK: catch_all : ^bb1 +// CHECK: ] +// CHECK: ^bb1: +// CHECK: cir.return +// CHECK: } + +// Test cir.eh.dispatch with unwind +cir.func @eh_dispatch_unwind(%eh_token: !cir.eh_token) { + cir.eh.dispatch %eh_token : !cir.eh_token [ + unwind : ^bb1 + ] +^bb1: + cir.return +} + +// CHECK: cir.func @eh_dispatch_unwind(%arg0: !cir.eh_token) { +// CHECK: cir.eh.dispatch %arg0 : !cir.eh_token [ +// CHECK: unwind : ^bb1 +// CHECK: ] +// CHECK: ^bb1: +// CHECK: cir.return +// CHECK: } + +// Test cir.eh.dispatch with type handlers and catch_all +cir.func @eh_dispatch_types_catch_all(%eh_token: !cir.eh_token) { + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb1, + catch(#cir.global_view<@_ZTIPKc> : !cir.ptr) : ^bb2, + catch_all : ^bb3 + ] +^bb1: + cir.return +^bb2: + cir.return +^bb3: + cir.return +} + +// CHECK: cir.func @eh_dispatch_types_catch_all(%arg0: !cir.eh_token) { +// CHECK: cir.eh.dispatch %arg0 : !cir.eh_token [ +// CHECK: catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb1, +// CHECK: catch(#cir.global_view<@_ZTIPKc> : !cir.ptr) : ^bb2, +// CHECK: catch_all : ^bb3 +// CHECK: ] +// CHECK: ^bb1: +// CHECK: cir.return +// CHECK: ^bb2: +// CHECK: cir.return +// CHECK: ^bb3: +// CHECK: cir.return +// CHECK: } + +// Test cir.eh.dispatch with type handlers and unwind +cir.func @eh_dispatch_types_unwind(%eh_token: !cir.eh_token) { + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^catch_int, + unwind : ^unwind + ] +^catch_int: + cir.return +^unwind: + cir.return +} + +// CHECK: cir.func @eh_dispatch_types_unwind(%arg0: !cir.eh_token) { +// CHECK: cir.eh.dispatch %arg0 : !cir.eh_token [ +// CHECK: catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb1, +// CHECK: unwind : ^bb2 +// CHECK: ] +// CHECK: ^bb1: +// CHECK: cir.return +// CHECK: ^bb2: +// CHECK: cir.return +// CHECK: } + +// Test cir.begin_cleanup and cir.end_cleanup +cir.func @cleanup_ops(%eh_token: !cir.eh_token) { + %cleanup_token = cir.begin_cleanup %eh_token : !cir.eh_token -> !cir.cleanup_token + cir.end_cleanup %cleanup_token : !cir.cleanup_token + cir.return +} + +// CHECK: cir.func @cleanup_ops(%arg0: !cir.eh_token) { +// CHECK: %[[CLEANUP:.*]] = cir.begin_cleanup %arg0 : !cir.eh_token -> !cir.cleanup_token +// CHECK: cir.end_cleanup %[[CLEANUP]] : !cir.cleanup_token +// CHECK: cir.return +// CHECK: } + +// Test cir.begin_catch and cir.end_catch +cir.func @catch_ops(%eh_token: !cir.eh_token) { + %catch_token, %exn_ptr = cir.begin_catch %eh_token : !cir.eh_token -> (!cir.catch_token, !cir.ptr) + cir.end_catch %catch_token : !cir.catch_token + cir.return +} + +// CHECK: cir.func @catch_ops(%arg0: !cir.eh_token) { +// CHECK: %[[CATCH:.*]], %[[EXN:.*]] = cir.begin_catch %arg0 : !cir.eh_token -> (!cir.catch_token, !cir.ptr) +// CHECK: cir.end_catch %[[CATCH]] : !cir.catch_token +// CHECK: cir.return +// CHECK: } + +// Test cir.begin_catch with void pointer (catch all) +cir.func @catch_all_ops(%eh_token: !cir.eh_token) { + %catch_token, %exn_ptr = cir.begin_catch %eh_token : !cir.eh_token -> (!cir.catch_token, !cir.ptr) + cir.end_catch %catch_token : !cir.catch_token + cir.return +} + +// CHECK: cir.func @catch_all_ops(%arg0: !cir.eh_token) { +// CHECK: %[[CATCH:.*]], %[[EXN:.*]] = cir.begin_catch %arg0 : !cir.eh_token -> (!cir.catch_token, !cir.ptr) +// CHECK: cir.end_catch %[[CATCH]] : !cir.catch_token +// CHECK: cir.return +// CHECK: } + +// Test complete example with try_call, eh.initiate, cleanup, and dispatch +cir.func private @mayThrow() -> () +cir.func private @destructor() -> () + +cir.func @complete_example() { + cir.try_call @mayThrow() ^bb1, ^bb2 : () -> () +^bb1: // Normal return + cir.return +^bb2: // Exception path + %eh_token = cir.eh.initiate cleanup : !cir.eh_token + %cleanup_token = cir.begin_cleanup %eh_token : !cir.eh_token -> !cir.cleanup_token + cir.call @destructor() : () -> () + cir.end_cleanup %cleanup_token : !cir.cleanup_token + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^catch_int, + catch_all : ^catch_all + ] +^catch_int: + %catch_token, %exn_ptr = cir.begin_catch %eh_token : !cir.eh_token -> (!cir.catch_token, !cir.ptr) + cir.end_catch %catch_token : !cir.catch_token + cir.return +^catch_all: + %catch_token2, %exn_ptr2 = cir.begin_catch %eh_token : !cir.eh_token -> (!cir.catch_token, !cir.ptr) + cir.end_catch %catch_token2 : !cir.catch_token + cir.return +} + +// CHECK: cir.func @complete_example() +// CHECK: cir.try_call @mayThrow() ^bb1, ^bb2 : () -> () +// CHECK: ^bb1: +// CHECK: cir.return +// CHECK: ^bb2: +// CHECK: %[[EH:.*]] = cir.eh.initiate cleanup : !cir.eh_token +// CHECK: %[[CLEANUP:.*]] = cir.begin_cleanup %[[EH]] : !cir.eh_token -> !cir.cleanup_token +// CHECK: cir.call @destructor() : () -> () +// CHECK: cir.end_cleanup %[[CLEANUP]] : !cir.cleanup_token +// CHECK: cir.eh.dispatch %[[EH]] : !cir.eh_token [ +// CHECK: catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb3, +// CHECK: catch_all : ^bb4 +// CHECK: ] +// CHECK: ^bb3: +// CHECK: %[[CATCH1:.*]], %{{.*}} = cir.begin_catch %[[EH]] : !cir.eh_token -> (!cir.catch_token, !cir.ptr) +// CHECK: cir.end_catch %[[CATCH1]] : !cir.catch_token +// CHECK: cir.return +// CHECK: ^bb4: +// CHECK: %[[CATCH2:.*]], %{{.*}} = cir.begin_catch %[[EH]] : !cir.eh_token -> (!cir.catch_token, !cir.ptr) +// CHECK: cir.end_catch %[[CATCH2]] : !cir.catch_token +// CHECK: cir.return +// CHECK: } + +} diff --git a/clang/test/CIR/IR/invalid-eh-flat.cir b/clang/test/CIR/IR/invalid-eh-flat.cir new file mode 100644 index 0000000000000..9ae02af66646a --- /dev/null +++ b/clang/test/CIR/IR/invalid-eh-flat.cir @@ -0,0 +1,148 @@ +// RUN: cir-opt %s -verify-diagnostics -split-input-file + +!u8i = !cir.int +!s32i = !cir.int +!void = !cir.void + +module { + +cir.global "private" constant external @_ZTIi : !cir.ptr +cir.global "private" constant external @_ZTIPKc : !cir.ptr + +cir.func @eh_dispatch_no_default(%eh_token: !cir.eh_token) { + // expected-error @+5 {{must have either 'catch_all' or 'unwind' handler}} + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb1, + catch(#cir.global_view<@_ZTIPKc> : !cir.ptr) : ^bb2 + ] +^bb1: + cir.return +^bb2: + cir.return +} + +} + +// ----- + +!u8i = !cir.int +!s32i = !cir.int +!void = !cir.void + +module { + +cir.global "private" constant external @_ZTIi : !cir.ptr +cir.global "private" constant external @_ZTIPKc : !cir.ptr + +cir.func @eh_dispatch_catch_all_and_unwind(%eh_token: !cir.eh_token) { + // expected-error @+5 {{cannot have both 'catch_all' and 'unwind'}} + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb1, + catch(#cir.global_view<@_ZTIPKc> : !cir.ptr) : ^bb2, + catch_all : ^bb3, + unwind : ^bb4 + ] +^bb1: + cir.return +^bb2: + cir.return +^bb3: + cir.return +^bb4: + cir.resume +} + +} + +// ----- + +!u8i = !cir.int +!s32i = !cir.int +!void = !cir.void + +module { + +cir.global "private" constant external @_ZTIi : !cir.ptr +cir.global "private" constant external @_ZTIPKc : !cir.ptr + +cir.func @eh_dispatch_unwind_and_catch_all(%eh_token: !cir.eh_token) { + // expected-error @+5 {{cannot have both 'catch_all' and 'unwind'}} + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb1, + catch(#cir.global_view<@_ZTIPKc> : !cir.ptr) : ^bb2, + unwind : ^bb3, + catch_all : ^bb4 + ] +^bb1: + cir.return +^bb2: + cir.return +^bb3: + cir.resume +^bb4: + cir.return +} + +} + +// ----- + +!u8i = !cir.int +!s32i = !cir.int +!void = !cir.void + +module { + +cir.global "private" constant external @_ZTIi : !cir.ptr +cir.global "private" constant external @_ZTIPKc : !cir.ptr + +cir.func @eh_dispatch_duplicate_unwind(%eh_token: !cir.eh_token) { + // expected-error @+5 {{duplicate 'unwind' handler}} + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb1, + catch(#cir.global_view<@_ZTIPKc> : !cir.ptr) : ^bb2, + unwind : ^bb3, + unwind : ^bb4 + ] +^bb1: + cir.return +^bb2: + cir.return +^bb3: + cir.resume +^bb4: + cir.resume +} + +} + +// ----- + +!u8i = !cir.int +!s32i = !cir.int +!void = !cir.void + +module { + +cir.global "private" constant external @_ZTIi : !cir.ptr +cir.global "private" constant external @_ZTIPKc : !cir.ptr + +cir.func @eh_dispatch_duplicate_catch_all(%eh_token: !cir.eh_token) { + // expected-error @+5 {{duplicate 'catch_all' handler}} + cir.eh.dispatch %eh_token : !cir.eh_token [ + catch(#cir.global_view<@_ZTIi> : !cir.ptr) : ^bb1, + catch(#cir.global_view<@_ZTIPKc> : !cir.ptr) : ^bb2, + catch_all : ^bb3, + catch_all : ^bb4 + ] +^bb1: + cir.return +^bb2: + cir.return +^bb3: + cir.return +^bb4: + cir.return +} + +} diff --git a/clang/test/CIR/Transforms/flatten-cleanup-scope-multi-exit.cir b/clang/test/CIR/Transforms/flatten-cleanup-scope-multi-exit.cir new file mode 100644 index 0000000000000..036df852590d4 --- /dev/null +++ b/clang/test/CIR/Transforms/flatten-cleanup-scope-multi-exit.cir @@ -0,0 +1,413 @@ +// RUN: cir-opt %s -cir-flatten-cfg -verify-diagnostics -split-input-file -o - + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that we detect multiple exits in a loop with a break that branches +// through a cleanup region. +cir.func @test_multi_exit_with_break() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.while { + %true = cir.const #cir.bool : !cir.bool + cir.condition(%true) + } do { + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %cond = cir.call @shouldBreak() : () -> !cir.bool + cir.brcond %cond ^bb_break, ^bb_normal + ^bb_break: + cir.break // Break through cleanup - exits loop + ^bb_normal: + cir.yield // Normal exit through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @shouldBreak() -> !cir.bool + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that we detect multiple exits in a loop with a continue that branches +// through a cleanup region. +cir.func @test_multi_exit_with_continue() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.while { + %true = cir.const #cir.bool : !cir.bool + cir.condition(%true) + } do { + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %cond = cir.call @shouldContinue() : () -> !cir.bool + cir.brcond %cond ^bb_continue, ^bb_normal + ^bb_continue: + cir.continue // Continue through cleanup - exits the region + ^bb_normal: + cir.yield // Normal exit through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @shouldContinue() -> !cir.bool + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that we detect multiple exits in a switch statement nested within a +// loop with a continue statement inside the switch that branches through a +// cleanup region. +cir.func @test_continue_in_switch() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.while { + %true = cir.const #cir.bool : !cir.bool + cir.condition(%true) + } do { + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %x = cir.const #cir.int<1> : !s32i + // expected-error @below {{cannot lower switch: cleanup with multiple exits}} + cir.switch (%x : !s32i) { + cir.case (equal, [#cir.int<1> : !s32i]) { + cir.break // Break from switch -- no cleanup exit + } + cir.case (equal, [#cir.int<2> : !s32i]) { + cir.continue // Continue to outer loop - exits through cleanup! + } + cir.yield + } + cir.yield // Normal exit through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that we detect return inside a loop inside a switch inside a cleanup +// scope. The return must be found even though it's nested inside the loop. +cir.func @test_return_in_loop_in_switch() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.while { + %true = cir.const #cir.bool : !cir.bool + cir.condition(%true) + } do { + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %x = cir.const #cir.int<1> : !s32i + // expected-error @below {{cannot lower switch: cleanup with multiple exits}} + cir.switch (%x : !s32i) { + cir.case (equal, [#cir.int<1> : !s32i]) { + // Nested loop inside switch + // expected-error @below {{cannot lower loop: cleanup with multiple exits}} + cir.while { + %cond = cir.call @shouldContinue() : () -> !cir.bool + cir.condition(%cond) + } do { + %ret = cir.call @shouldReturn() : () -> !cir.bool + cir.brcond %ret ^bb_return, ^bb_continue + ^bb_return: + cir.return // Return inside loop inside switch - exits through cleanup! + ^bb_continue: + cir.yield + } + cir.break // Break from switch - handled by switch + } + cir.yield + } + cir.yield // Normal exit through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @shouldContinue() -> !cir.bool +cir.func private @shouldReturn() -> !cir.bool + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that a return inside nested cleanup scopes causes both to be detected +// as having multiple exits. The return must go through both cleanup regions. +cir.func @test_return_in_nested_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c1", init] {alignment = 4 : i64} + %1 = cir.alloca !rec_SomeClass, !cir.ptr, ["c2", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + cir.call @ctor(%1) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %cond = cir.call @shouldReturn() : () -> !cir.bool + cir.brcond %cond ^bb_return, ^bb_normal + ^bb_return: + cir.return // Return exits through BOTH cleanup scopes + ^bb_normal: + cir.yield + } cleanup normal { + cir.call @dtor(%1) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @shouldReturn() -> !cir.bool + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that a goto inside nested cleanup scopes causes both to be detected +// as having multiple exits. The goto must go through both cleanup regions. +cir.func @test_goto_in_nested_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c1", init] {alignment = 4 : i64} + %1 = cir.alloca !rec_SomeClass, !cir.ptr, ["c2", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + cir.call @ctor(%1) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %cond = cir.call @shouldGoto() : () -> !cir.bool + cir.brcond %cond ^bb_goto, ^bb_normal + ^bb_goto: + cir.goto "target" // Goto exits through BOTH cleanup scopes + ^bb_normal: + cir.yield + } cleanup normal { + cir.call @dtor(%1) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.br ^bb_end +^bb_goto_target: + cir.label "target" + cir.br ^bb_end +^bb_end: + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @shouldGoto() -> !cir.bool + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that a break inside nested cleanup scopes (within a loop) causes both +// to be detected as having multiple exits. The break exits through both cleanups. +cir.func @test_break_in_nested_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c1", init] {alignment = 4 : i64} + %1 = cir.alloca !rec_SomeClass, !cir.ptr, ["c2", init] {alignment = 4 : i64} + cir.while { + %true = cir.const #cir.bool : !cir.bool + cir.condition(%true) + } do { + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + cir.call @ctor(%1) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %cond = cir.call @shouldBreak() : () -> !cir.bool + cir.brcond %cond ^bb_break, ^bb_normal + ^bb_break: + cir.break // Break exits through BOTH cleanup scopes, then exits loop + ^bb_normal: + cir.yield + } cleanup normal { + cir.call @dtor(%1) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @shouldBreak() -> !cir.bool + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that a continue inside nested cleanup scopes (within a loop) causes both +// to be detected as having multiple exits. The continue exits through both cleanups. +cir.func @test_continue_in_nested_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c1", init] {alignment = 4 : i64} + %1 = cir.alloca !rec_SomeClass, !cir.ptr, ["c2", init] {alignment = 4 : i64} + cir.while { + %true = cir.const #cir.bool : !cir.bool + cir.condition(%true) + } do { + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + cir.call @ctor(%1) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %cond = cir.call @shouldContinue() : () -> !cir.bool + cir.brcond %cond ^bb_continue, ^bb_normal + ^bb_continue: + cir.continue // Continue exits through BOTH cleanup scopes, then continues loop + ^bb_normal: + cir.yield + } cleanup normal { + cir.call @dtor(%1) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @shouldContinue() -> !cir.bool + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test a cleanup scope containing a switch which contains a nested cleanup +// scope with a continue. The continue must branch through both cleanup scopes. +cir.func @test_continue_in_nested_cleanup_in_switch() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c1", init] {alignment = 4 : i64} + %1 = cir.alloca !rec_SomeClass, !cir.ptr, ["c2", init] {alignment = 4 : i64} + %2 = cir.alloca !s32i, !cir.ptr, ["x", init] {alignment = 4 : i64} + cir.while { + %true = cir.const #cir.bool : !cir.bool + cir.condition(%true) + } do { + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + %x = cir.load %2 : !cir.ptr, !s32i + // expected-error @below {{cannot lower switch: cleanup with multiple exits}} + cir.switch (%x : !s32i) { + cir.case (equal, [#cir.int<1> : !s32i]) { + cir.call @ctor(%1) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.continue // Branches through both cleanups + } cleanup normal { + cir.call @dtor(%1) : (!cir.ptr) -> () + cir.yield + } + cir.break + } + cir.yield + } + cir.yield + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) + +// ----- + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test a cleanup scope containing a loop with a conditional return. +// The return must branch through the cleanup scope. +cir.func @test_return_in_loop_in_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{cleanup scope with multiple exits is not yet implemented}} + cir.cleanup.scope { + // expected-error @below {{cannot lower loop: cleanup with multiple exits}} + cir.while { + %true = cir.const #cir.bool : !cir.bool + cir.condition(%true) + } do { + %cond = cir.call @shouldReturn() : () -> !cir.bool + cir.brcond %cond ^bb_return, ^bb_continue + ^bb_return: + cir.return // Return branches through cleanup + ^bb_continue: + cir.yield + } + cir.yield + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @shouldReturn() -> !cir.bool diff --git a/clang/test/CIR/Transforms/flatten-cleanup-scope-nyi.cir b/clang/test/CIR/Transforms/flatten-cleanup-scope-nyi.cir new file mode 100644 index 0000000000000..729914fce608d --- /dev/null +++ b/clang/test/CIR/Transforms/flatten-cleanup-scope-nyi.cir @@ -0,0 +1,59 @@ +// RUN: cir-opt %s -cir-flatten-cfg -verify-diagnostics -o - + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test that we issue a diagnostic for EH-only cleanup scopes. +cir.func @test_eh_only_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{EH cleanup flattening is not yet implemented}} + cir.cleanup.scope { + cir.call @doSomething(%0) : (!cir.ptr) -> () + cir.yield + } cleanup eh { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// Test that we issue a diagnostic for Normal+EH cleanup scopes. +cir.func @test_all_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + // expected-error @below {{EH cleanup flattening is not yet implemented}} + cir.cleanup.scope { + cir.call @doSomething(%0) : (!cir.ptr) -> () + cir.yield + } cleanup all { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// Test that we issue a diagnostic for a single goto out of a cleanup scope. +// Strictly speaking, we could handle this case, but it's left unimplemented +// because when we handle multiple exits we'll need to do something to determine +// whether gotos branch out of the cleanup scope or stay within it. +cir.func @test_goto_out_of_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @doSomething(%0) : (!cir.ptr) -> () + // expected-error @below {{goto in cleanup scope is not yet implemented}} + cir.goto "exit" + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.br ^bb1 +^bb1: + cir.label "exit" + cir.return +} + +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @doSomething(!cir.ptr) diff --git a/clang/test/CIR/Transforms/flatten-cleanup-scope-simple.cir b/clang/test/CIR/Transforms/flatten-cleanup-scope-simple.cir new file mode 100644 index 0000000000000..e268704ddf485 --- /dev/null +++ b/clang/test/CIR/Transforms/flatten-cleanup-scope-simple.cir @@ -0,0 +1,540 @@ +// RUN: cir-opt %s -cir-flatten-cfg -o %t.cir +// RUN: FileCheck --input-file=%t.cir %s + +!s32i = !cir.int +!rec_SomeClass = !cir.record + +// Test basic cleanup scope flattening with normal cleanup. +// The body yields to cleanup, cleanup yields to continue. +cir.func @test_normal_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @doSomething(%0) : (!cir.ptr) -> () + cir.yield + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_normal_cleanup() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[BODY:bb[0-9]+]] +// CHECK: ^[[BODY]]: +// CHECK: cir.call @doSomething(%[[ALLOCA]]) +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[CONTINUE:bb[0-9]+]] +// CHECK: ^[[CONTINUE]]: +// CHECK: cir.return + +// Test that a single return from the cleanup body branches through the cleanup. +cir.func @test_return_from_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @doSomething(%0) : (!cir.ptr) -> () + cir.return // Should branch through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_return_from_cleanup() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[BODY:bb[0-9]+]] +// CHECK: ^[[BODY]]: +// CHECK: cir.call @doSomething(%[[ALLOCA]]) +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[CLEANUP_EXIT:bb[0-9]+]] +// CHECK: ^[[CLEANUP_EXIT]]: +// CHECK: cir.return +// CHECK: ^[[UNREACHABLE_NORMAL_RETURN:bb[0-9]+]] +// CHECK: cir.return + +// Test that a single return from the cleanup body branches through the cleanup. +cir.func @test_return_from_cleanup_with_operand() -> !s32i { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @doSomething(%0) : (!cir.ptr) -> () + %1 = cir.const #cir.int<-1> : !s32i + cir.return %1 : !s32i // Should branch through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + %2 = cir.const #cir.int<0> : !s32i + cir.return %2 : !s32i +} + +// CHECK-LABEL: cir.func @test_return_from_cleanup_with_operand() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[BODY:bb[0-9]+]] +// CHECK: ^[[BODY]]: +// CHECK: cir.call @doSomething(%[[ALLOCA]]) +// CHECK: %[[MINUS_ONE:.*]] = cir.const #cir.int<-1> : !s32i +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[CLEANUP_EXIT:bb[0-9]+]] +// CHECK: ^[[CLEANUP_EXIT]]: +// CHECK: cir.return %[[MINUS_ONE]] : !s32i +// CHECK: ^[[UNREACHABLE_NORMAL_RETURN:bb[0-9]+]] +// CHECK: %[[ZERO:.*]] = cir.const #cir.int<0> : !s32i +// CHECK: cir.return %[[ZERO]] : !s32i + +// Test that a continue statement in a cleanup scope branches through the +// cleanup block before continuing the loop. +cir.func @test_continue_in_cleanup_in_loop() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.while { + %cond = cir.call @shouldContinue() : () -> !cir.bool + cir.condition(%cond) + } do { + %cont = cir.call @shouldContinue() : () -> !cir.bool + cir.brcond %cont ^bb_continue, ^bb_normal + ^bb_continue: + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.continue // Branches through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.br ^bb_normal + ^bb_normal: + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_continue_in_cleanup_in_loop() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.br ^[[LOOP_COND:bb[0-9]+]] +// CHECK: ^[[LOOP_COND]]: +// CHECK: %[[COND1:.*]] = cir.call @shouldContinue() : () -> !cir.bool +// CHECK: cir.brcond %[[COND1]] ^[[LOOP_BODY:bb[0-9]+]], ^[[LOOP_EXIT:bb[0-9]+]] +// CHECK: ^[[LOOP_BODY]]: +// CHECK: %[[COND2:.*]] = cir.call @shouldContinue() : () -> !cir.bool +// CHECK: cir.brcond %[[COND2]] ^[[CONTINUE_PATH:bb[0-9]+]], ^[[NORMAL_PATH:bb[0-9]+]] +// CHECK: ^[[CONTINUE_PATH]]: +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[CLEANUP_BODY:bb[0-9]+]] +// CHECK: ^[[CLEANUP_BODY]]: +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[CLEANUP_EXIT:bb[0-9]+]] +// CHECK: ^[[CLEANUP_EXIT]]: +// CHECK: cir.br ^[[LOOP_COND]] +// CHECK: ^[[NORMAL_PATH]]: +// CHECK: cir.br ^[[LOOP_COND]] +// CHECK: ^[[LOOP_EXIT]]: +// CHECK: cir.return + +// Test that a break statement in a cleanup scope branches through the +// cleanup block before breaking out of the loop. +cir.func @test_break_in_cleanup_in_loop() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.while { + %cond = cir.call @shouldContinue() : () -> !cir.bool + cir.condition(%cond) + } do { + %cont = cir.call @shouldContinue() : () -> !cir.bool + cir.brcond %cont ^bb_continue, ^bb_normal + ^bb_continue: + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.break // Branches through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.br ^bb_normal + ^bb_normal: + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_break_in_cleanup_in_loop() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.br ^[[LOOP_COND:bb[0-9]+]] +// CHECK: ^[[LOOP_COND]]: +// CHECK: %[[COND1:.*]] = cir.call @shouldContinue() : () -> !cir.bool +// CHECK: cir.brcond %[[COND1]] ^[[LOOP_BODY:bb[0-9]+]], ^[[LOOP_EXIT:bb[0-9]+]] +// CHECK: ^[[LOOP_BODY]]: +// CHECK: %[[COND2:.*]] = cir.call @shouldContinue() : () -> !cir.bool +// CHECK: cir.brcond %[[COND2]] ^[[CONTINUE_PATH:bb[0-9]+]], ^[[NORMAL_PATH:bb[0-9]+]] +// CHECK: ^[[CONTINUE_PATH]]: +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[CLEANUP_BODY:bb[0-9]+]] +// CHECK: ^[[CLEANUP_BODY]]: +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[CLEANUP_EXIT:bb[0-9]+]] +// CHECK: ^[[CLEANUP_EXIT]]: +// CHECK: cir.br ^[[LOOP_EXIT]] +// CHECK: ^[[NORMAL_PATH]]: +// CHECK: cir.br ^[[LOOP_COND]] +// CHECK: ^[[LOOP_EXIT]]: +// CHECK: cir.return + +// Test nested cleanup scopes. +cir.func @test_nested_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c1", init] {alignment = 4 : i64} + %1 = cir.alloca !rec_SomeClass, !cir.ptr, ["c2", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @ctor(%1) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @doSomething(%0) : (!cir.ptr) -> () + cir.yield + } cleanup normal { + cir.call @dtor(%1) : (!cir.ptr) -> () + cir.yield + } + cir.yield + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_nested_cleanup() +// CHECK: %[[ALLOCA1:.*]] = cir.alloca !rec_SomeClass +// CHECK: %[[ALLOCA2:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA1]]) +// CHECK: cir.br ^[[OUTER_BODY:bb[0-9]+]] +// CHECK: ^[[OUTER_BODY]]: +// CHECK: cir.call @ctor(%[[ALLOCA2]]) +// CHECK: cir.br ^[[INNER_BODY:bb[0-9]+]] +// CHECK: ^[[INNER_BODY]]: +// CHECK: cir.call @doSomething(%[[ALLOCA1]]) +// CHECK: cir.br ^[[INNER_CLEANUP:bb[0-9]+]] +// CHECK: ^[[INNER_CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA2]]) +// CHECK: cir.br ^[[AFTER_INNER:bb[0-9]+]] +// CHECK: ^[[AFTER_INNER]]: +// CHECK: cir.br ^[[OUTER_CLEANUP:bb[0-9]+]] +// CHECK: ^[[OUTER_CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA1]]) +// CHECK: cir.br ^[[CONTINUE:bb[0-9]+]] +// CHECK: ^[[CONTINUE]]: +// CHECK: cir.return + +// Test a switch within a cleanup scope where the switch does not branch +// through the cleanup. +cir.func @test_normal_cleanup_with_switch() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + %1 = cir.call @get() : () -> !s32i + cir.switch (%1 : !s32i) { + cir.case (equal, [#cir.int<1> : !s32i]) { + cir.break // Break from switch -- no cleanup exit + } + cir.case (equal, [#cir.int<2> : !s32i]) { + cir.call @doSomething(%0) : (!cir.ptr) -> () + cir.break // Break from switch -- no cleanup exit + } + cir.yield // Yield from switch -- no cleanup exit + } + cir.yield // Normal exit through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_normal_cleanup_with_switch() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[BODY:bb[0-9]+]] +// CHECK: ^[[BODY]]: +// CHECK: %[[X:.*]] = cir.call @get() : () -> !s32i +// CHECK: cir.br ^[[SWITCH:bb[0-9]+]] +// CHECK: ^[[SWITCH]]: +// CHECK: cir.switch.flat %[[X]] : !s32i, ^bb6 [ +// CHECK: 1: ^[[BREAK:bb[0-9]+]], +// CHECK: 2: ^[[CALL:bb[0-9]+]] +// CHECK: ] +// CHECK: ^[[FALLTHROUGH:bb[0-9]+]]: +// CHECK: cir.br ^[[BREAK]] +// CHECK: ^[[BREAK]]: +// CHECK: cir.br ^[[SWITCH_END:bb[0-9]+]] +// CHECK: ^[[CALL]]: +// CHECK: cir.call @doSomething(%[[ALLOCA]]) +// CHECK: cir.br ^[[SWITCH_END]] +// CHECK: ^[[SWITCH_END]]: +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[DONE:bb[0-9]+]] +// CHECK: ^[[DONE]]: +// CHECK: cir.return + +// Test a loop within a cleanup scope where the loop's break and continue are +// handled by the loop itself, so only the yield after the loop exits through +// the cleanup. +cir.func @test_loop_in_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.while { + %cond = cir.call @shouldContinue() : () -> !cir.bool + cir.condition(%cond) + } do { + %brk = cir.call @shouldBreak() : () -> !cir.bool + cir.brcond %brk ^bb_break, ^bb_continue + ^bb_break: + cir.break // Break from loop - handled by loop, no cleanup exit + ^bb_continue: + cir.continue // Continue loop - handled by loop, no cleanup exit + } + cir.yield // Normal exit through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_loop_in_cleanup() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[LOOP_BEGIN:bb[0-9]+]] +// CHECK: ^[[LOOP_BEGIN]]: +// CHECK: cir.br ^[[COND:bb[0-9]+]] +// CHECK: ^[[COND]]: +// CHECK: %[[SHOULDCONT:.*]] = cir.call @shouldContinue +// CHECK: cir.brcond %[[SHOULDCONT]] ^[[LOOP_BODY:bb[0-9]+]], ^[[LOOP_EXIT:bb[0-9]+]] +// CHECK: ^[[LOOP_BODY]]: +// CHECK: %[[SHOULDBRK:.*]] = cir.call @shouldBreak +// CHECK: cir.brcond %[[SHOULDBRK]] ^[[BREAK:bb[0-9]+]], ^[[CONT:bb[0-9]+]] +// CHECK: ^[[BREAK]]: +// CHECK: cir.br ^[[LOOP_EXIT]] +// CHECK: ^[[CONT]]: +// CHECK: cir.br ^[[COND]] +// CHECK: ^[[LOOP_EXIT]]: +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[DONE:bb[0-9]+]] +// CHECK: ^[[DONE]]: +// CHECK: cir.return + +// Test a switch within a loop within a cleanup scope. The switch's break is +// handled by the switch, the loop's break/continue are handled by the loop, +// so only the yield exits through cleanup. +cir.func @test_switch_in_loop_in_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.while { + %cond = cir.call @shouldContinue() : () -> !cir.bool + cir.condition(%cond) + } do { + %x = cir.call @get() : () -> !s32i + cir.switch (%x : !s32i) { + cir.case (equal, [#cir.int<1> : !s32i]) { + cir.break // Break from switch - handled by switch + } + cir.case (equal, [#cir.int<2> : !s32i]) { + cir.continue // Continue outer loop - handled by loop + } + cir.yield + } + cir.yield // Yield from loop body + } + cir.yield // Normal exit through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_switch_in_loop_in_cleanup() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[LOOP_BEGIN:bb[0-9]+]] +// CHECK: ^[[LOOP_BEGIN]]: +// CHECK: cir.br ^[[COND:bb[0-9]+]] +// CHECK: ^[[COND]]: +// CHECK: %[[SHOULDCONT:.*]] = cir.call @shouldContinue +// CHECK: cir.brcond %[[SHOULDCONT]] ^[[LOOP_BODY:bb[0-9]+]], ^[[LOOP_EXIT:bb[0-9]+]] +// CHECK: ^[[LOOP_BODY]]: +// CHECK: %[[X:.*]] = cir.call @get() : () -> !s32i +// CHECK: cir.br ^[[SWITCH_BEGIN:bb[0-9]+]] +// CHECK: ^[[SWITCH_BEGIN]]: +// CHECK: cir.switch.flat %[[X]] : !s32i, ^[[FALLTHROUGH:bb[0-9]+]] [ +// CHECK: 1: ^[[SWITCH_BREAK:bb[0-9]+]], +// CHECK: 2: ^[[SWITCH_CONTINUE:bb[0-9]+]] +// CHECK: ] +// CHECK: ^[[SWITCH_BREAK]]: +// CHECK: cir.br ^[[FALLTHROUGH]] +// CHECK: ^[[SWITCH_CONTINUE]]: +// CHECK: cir.br ^[[COND]] +// CHECK: ^[[FALLTHROUGH]]: +// CHECK: cir.br ^[[COND]] +// CHECK: ^[[LOOP_EXIT]]: +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[DONE:bb[0-9]+]] +// CHECK: ^[[DONE]]: +// CHECK: cir.return + +// Test a loop within a switch within a cleanup scope. The loop's break/continue +// are handled by the loop, the switch's break exits the switch, so only the +// yield exits through cleanup. +cir.func @test_loop_in_switch_in_cleanup() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + %x = cir.call @get() : () -> !s32i + cir.switch (%x : !s32i) { + cir.case (equal, [#cir.int<1> : !s32i]) { + cir.while { + %cond = cir.call @shouldContinue() : () -> !cir.bool + cir.condition(%cond) + } do { + %brk = cir.call @shouldBreak() : () -> !cir.bool + cir.brcond %brk ^bb_break, ^bb_continue + ^bb_break: + cir.break // Break from loop - handled by loop + ^bb_continue: + cir.continue // Continue loop - handled by loop + } + cir.break // Break from switch - handled by switch + } + cir.yield + } + cir.yield // Normal exit through cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_loop_in_switch_in_cleanup() +// CHECK: %[[ALLOCA:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA]]) +// CHECK: cir.br ^[[BODY:bb[0-9]+]] +// CHECK: ^[[BODY]]: +// CHECK: %[[X:.*]] = cir.call @get() : () -> !s32i +// CHECK: cir.br ^[[SWITCH_BEGIN:bb[0-9]+]] +// CHECK: ^[[SWITCH_BEGIN]]: +// CHECK: cir.switch.flat %[[X]] : !s32i, ^[[SWITCH_END:bb[0-9]+]] [ +// CHECK: 1: ^[[CASE1:bb[0-9]+]] +// CHECK: ] +// CHECK: ^[[FALLTHROUGH:bb[0-9]+]]: +// CHECK: cir.br ^[[CASE1]] +// CHECK: ^[[CASE1]]: +// CHECK: cir.br ^[[LOOP_COND:bb[0-9]+]] +// CHECK: ^[[LOOP_COND]]: +// CHECK: %[[SHOULDCONT:.*]] = cir.call @shouldContinue() : () -> !cir.bool +// CHECK: cir.brcond %[[SHOULDCONT]] ^[[LOOP_BODY:bb[0-9]+]], ^[[LOOP_EXIT:bb[0-9]+]] +// CHECK: ^[[LOOP_BODY]]: +// CHECK: %[[SHOULDBRK:.*]] = cir.call @shouldBreak() : () -> !cir.bool +// CHECK: cir.brcond %[[SHOULDBRK]] ^[[BREAK:bb[0-9]+]], ^[[CONT:bb[0-9]+]] +// CHECK: ^[[BREAK]]: +// CHECK: cir.br ^[[LOOP_EXIT]] +// CHECK: ^[[CONT]]: +// CHECK: cir.br ^[[LOOP_COND]] +// CHECK: ^[[LOOP_EXIT]]: +// CHECK: cir.br ^[[SWITCH_END]] +// CHECK: ^[[SWITCH_END]]: +// CHECK: cir.br ^[[CLEANUP:bb[0-9]+]] +// CHECK: ^[[CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA]]) +// CHECK: cir.br ^[[DONE:bb[0-9]+]] +// CHECK: ^[[DONE]]: +// CHECK: cir.return + +// Test a cleanup scope containing a switch which contains a nested cleanup +// scope with a break. The break is handled by the switch, so the outer cleanup +// has only one exit (yield) and should flatten successfully. +cir.func @test_nested_cleanup_break_in_switch() { + %0 = cir.alloca !rec_SomeClass, !cir.ptr, ["c1", init] {alignment = 4 : i64} + %1 = cir.alloca !rec_SomeClass, !cir.ptr, ["c2", init] {alignment = 4 : i64} + cir.call @ctor(%0) : (!cir.ptr) -> () + cir.cleanup.scope { + %x = cir.call @get() : () -> !s32i + cir.switch (%x : !s32i) { + cir.case (equal, [#cir.int<1> : !s32i]) { + cir.call @ctor(%1) : (!cir.ptr) -> () + cir.cleanup.scope { + cir.call @doSomething(%1) : (!cir.ptr) -> () + cir.break // Branch through inner cleanup, but not outer cleanup + } cleanup normal { + cir.call @dtor(%1) : (!cir.ptr) -> () + cir.yield + } + cir.break + } + cir.yield + } + cir.yield // Only exit from outer cleanup + } cleanup normal { + cir.call @dtor(%0) : (!cir.ptr) -> () + cir.yield + } + cir.return +} + +// CHECK-LABEL: cir.func @test_nested_cleanup_break_in_switch() +// CHECK: %[[ALLOCA1:.*]] = cir.alloca !rec_SomeClass +// CHECK: %[[ALLOCA2:.*]] = cir.alloca !rec_SomeClass +// CHECK: cir.call @ctor(%[[ALLOCA1]]) +// CHECK: cir.br ^[[BODY:bb[0-9]+]] +// CHECK: ^[[BODY]]: +// CHECK: %[[X:.*]] = cir.call @get() : () -> !s32i +// CHECK: cir.br ^[[SWITCH_BEGIN:bb[0-9]+]] +// CHECK: ^[[SWITCH_BEGIN]]: +// CHECK: cir.switch.flat %[[X]] : !s32i, ^[[SWITCH_END:bb[0-9]+]] [ +// CHECK: 1: ^[[CASE1:bb[0-9]+]] +// CHECK: ] +// CHECK: ^[[CASE1]]: +// CHECK: cir.call @ctor(%[[ALLOCA2]]) +// CHECK: cir.br ^[[INNER_BODY:bb[0-9]+]] +// CHECK: ^[[INNER_BODY]]: +// CHECK: cir.call @doSomething(%[[ALLOCA2]]) +// CHECK: cir.br ^[[INNER_CLEANUP:bb[0-9]+]] +// CHECK: ^[[INNER_CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA2]]) +// CHECK: cir.br ^[[EXIT_CLEANUP:bb[0-9]+]] +// CHECK: ^[[EXIT_CLEANUP]]: +// CHECK: cir.br ^[[SWITCH_END]] +// CHECK: ^[[SWITCH_END]]: +// CHECK: cir.br ^[[OUTER_CLEANUP:bb[0-9]+]] +// CHECK: ^[[OUTER_CLEANUP]]: +// CHECK: cir.call @dtor(%[[ALLOCA1]]) +// CHECK: cir.br ^[[OUTER_CLEANUP_DONE:bb[0-9]+]] +// CHECK: ^[[OUTER_CLEANUP_DONE]]: +// CHECK: cir.br ^[[DONE:bb[0-9]+]] +// CHECK: ^[[DONE]]: +// CHECK: cir.return + +cir.func private @get() -> !s32i +cir.func private @ctor(!cir.ptr) +cir.func private @dtor(!cir.ptr) +cir.func private @doSomething(!cir.ptr) +cir.func private @shouldBreak() -> !cir.bool +cir.func private @shouldContinue() -> !cir.bool diff --git a/clang/test/CXX/drs/cwg0xx.cpp b/clang/test/CXX/drs/cwg0xx.cpp index 10a4f1d6add3a..6d3a3238d4f38 100644 --- a/clang/test/CXX/drs/cwg0xx.cpp +++ b/clang/test/CXX/drs/cwg0xx.cpp @@ -335,14 +335,14 @@ namespace cwg25 { // cwg25: 4 // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} void (A::*g)() throw () = f; // cxx98-14-error@-1 {{target exception specification is not superset of source}} - // since-cxx17-error@-2 {{different exception specifications}} + // since-cxx17-error@-2 {{cannot initialize a variable of type 'void (A::*)() throw()' with an lvalue of type 'void (A::*)() throw(int)': different exception specifications}} void (A::*g2)() throw () = 0; void (A::*h)() throw (int, char) = f; // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} // since-cxx17-note@-2 {{use 'noexcept(false)' instead}} void (A::*i)() throw () = &A::f; // cxx98-14-error@-1 {{target exception specification is not superset of source}} - // since-cxx17-error@-2 {{different exception specifications}} + // since-cxx17-error@-2 {{cannot initialize a variable of type 'void (A::*)() throw()' with an rvalue of type 'void (A::*)() throw(int)': different exception specifications}} void (A::*i2)() throw () = 0; void (A::*j)() throw (int, char) = &A::f; // since-cxx17-error@-1 {{ISO C++17 does not allow dynamic exception specifications}} @@ -350,11 +350,11 @@ namespace cwg25 { // cwg25: 4 void x() { g2 = f; // cxx98-14-error@-1 {{target exception specification is not superset of source}} - // since-cxx17-error@-2 {{different exception specifications}} + // since-cxx17-error@-2 {{assigning to 'void (A::*)() throw()' from incompatible type 'void (A::*)() throw(int)': different exception specifications}} h = f; i2 = &A::f; // cxx98-14-error@-1 {{target exception specification is not superset of source}} - // since-cxx17-error@-2 {{different exception specifications}} + // since-cxx17-error@-2 {{assigning to 'void (A::*)() throw()' from incompatible type 'void (A::*)() throw(int)': different exception specifications}} j = &A::f; } } // namespace cwg25 @@ -708,7 +708,7 @@ namespace cwg39 { // cwg39: no struct cwg39::PR5916::D -> C -> A}} */ // expected-note@#cwg39-A-n {{member found by ambiguous name lookup}} - // expected-error@#cwg39-sizeof {{unknown type name}} + // expected-error@#cwg39-sizeof {{unknown type name 'n'}} #if __cplusplus >= 201103L decltype(D::n) n; /* since-cxx11-error@-1 @@ -1058,19 +1058,19 @@ namespace cwg62 { // cwg62: 2.9 void f() { struct NoLinkage {}; X a; - // cxx98-error@-1 {{template argument uses local type }} + // cxx98-error@-1 {{template argument uses local type 'NoLinkage'}} X b; - // cxx98-error@-1 {{template argument uses local type }} + // cxx98-error@-1 {{template argument uses local type 'NoLinkage'}} get(); - // cxx98-error@-1 {{template argument uses local type }} - // cxx98-note@-2 {{while substituting explicitly-specified template arguments}} + // cxx98-error@-1 {{template argument uses local type 'NoLinkage'}} + // cxx98-note@-2 {{while substituting explicitly-specified template arguments into function template 'get'}} get(); - // cxx98-error@-1 {{template argument uses local type }} - // cxx98-note@-2 {{while substituting explicitly-specified template arguments}} + // cxx98-error@-1 {{template argument uses local type 'NoLinkage'}} + // cxx98-note@-2 {{while substituting explicitly-specified template arguments into function template 'get'}} X c; - // cxx98-error@-1 {{template argument uses local type }} + // cxx98-error@-1 {{template argument uses local type 'NoLinkage'}} X d; - // cxx98-error@-1 {{template argument uses local type }} + // cxx98-error@-1 {{template argument uses local type 'NoLinkage'}} } } // namespace cwg62 diff --git a/clang/test/CXX/drs/cwg11xx.cpp b/clang/test/CXX/drs/cwg11xx.cpp index 03612b6d87645..fc24deaf7cbcc 100644 --- a/clang/test/CXX/drs/cwg11xx.cpp +++ b/clang/test/CXX/drs/cwg11xx.cpp @@ -81,7 +81,7 @@ struct B : A { } b; void foo() { b.A::operator T(); // FIXME: qualified lookup should find T in A. - // expected-error@-1 {{unknown type name 'T'}} + // expected-error@-1 {{unknown type name 'T'; did you mean 'A::T'?}} // expected-note@#cwg1111-A-T {{'A::T' declared here}} } } // namespace example4 @@ -107,7 +107,7 @@ namespace cwg1113 { // cwg1113: partial namespace named { extern int a; // #cwg1113-a static int a; - // expected-error@-1 {{static declaration of 'a' follows non-static}} + // expected-error@-1 {{static declaration of 'a' follows non-static declaration}} // expected-note@#cwg1113-a {{previous declaration is here}} } namespace { diff --git a/clang/test/CXX/drs/cwg13xx.cpp b/clang/test/CXX/drs/cwg13xx.cpp index ad6ee01483b4a..0f97c484becdb 100644 --- a/clang/test/CXX/drs/cwg13xx.cpp +++ b/clang/test/CXX/drs/cwg13xx.cpp @@ -528,11 +528,11 @@ namespace cwg1359 { // cwg1359: 3.5 union B { constexpr B() = default; int a; }; // #cwg1359-B // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr before C++23}} union C { constexpr C() = default; int a, b; }; // #cwg1359-C - // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr}} + // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr before C++23}} struct X { constexpr X() = default; union {}; }; // since-cxx11-error@-1 {{declaration does not declare anything}} struct Y { constexpr Y() = default; union { int a; }; }; // #cwg1359-Y - // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr}} + // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr before C++23}} constexpr A a = A(); constexpr B b = B(); diff --git a/clang/test/CXX/drs/cwg14xx.cpp b/clang/test/CXX/drs/cwg14xx.cpp index 047df171afffa..dba1850ce8df9 100644 --- a/clang/test/CXX/drs/cwg14xx.cpp +++ b/clang/test/CXX/drs/cwg14xx.cpp @@ -31,20 +31,20 @@ namespace cwg1413 { // cwg1413: 12 // ok, variable declaration Check::type *var2; // #cwg1413-var2 Check::type *var3; - // expected-error@-1 {{use of undeclared identifier 'var3'}} + // expected-error@-1 {{use of undeclared identifier 'var3'; did you mean 'var2'?}} // expected-note@#cwg1413-var2 {{'var2' declared here}} Check::type *var4; - // expected-error@-1 {{use of undeclared identifier 'var4'}} + // expected-error@-1 {{use of undeclared identifier 'var4'; did you mean 'var2'?}} // expected-note@#cwg1413-var2 {{'var2' declared here}} // value-dependent because of the implied type-dependent 'this->', not because of 'd' Check::type *var5; - // expected-error@-1 {{use of undeclared identifier 'var5'}} + // expected-error@-1 {{use of undeclared identifier 'var5'; did you mean 'var2'?}} // expected-note@#cwg1413-var2 {{'var2' declared here}} // value-dependent because of the value-dependent '&' operator, not because of 'A::d' Check::type *var5; - // expected-error@-1 {{use of undeclared identifier 'var5'}} + // expected-error@-1 {{use of undeclared identifier 'var5'; did you mean 'var2'?}} // expected-note@#cwg1413-var2 {{'var2' declared here}} } }; @@ -116,7 +116,7 @@ void f() { // since-cxx11-error@-1 {{cannot initialize a variable of type 'const int' with an rvalue of type 'A *'}} constexpr A *p2 = &*a; // since-cxx11-error@-1 {{constexpr variable 'p2' must be initialized by a constant expression}} - // since-cxx11-note@-2 {{dereferencing a null pointer}} + // since-cxx11-note@-2 {{dereferencing a null pointer is not allowed in a constant expression}} } struct A { @@ -192,16 +192,16 @@ namespace cwg1460 { // cwg1460: 3.5 namespace Defaulted { union A { constexpr A() = default; }; union B { int n; constexpr B() = default; }; - // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr}} + // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr before C++23}} union C { int n = 0; constexpr C() = default; }; struct D { union {}; constexpr D() = default; }; // since-cxx11-error@-1 {{declaration does not declare anything}} struct E { union { int n; }; constexpr E() = default; }; - // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr}} + // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr before C++23}} struct F { union { int n = 0; }; constexpr F() = default; }; struct G { union { int n = 0; }; union { int m; }; constexpr G() = default; }; - // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr}} + // cxx11-17-error@-1 {{defaulted definition of default constructor cannot be marked constexpr before C++23}} struct H { union { int n = 0; diff --git a/clang/test/CXX/drs/cwg16xx.cpp b/clang/test/CXX/drs/cwg16xx.cpp index bd2c484344ddf..1a36aba859e50 100644 --- a/clang/test/CXX/drs/cwg16xx.cpp +++ b/clang/test/CXX/drs/cwg16xx.cpp @@ -162,10 +162,10 @@ namespace cwg1653 { // cwg1653: 4 c++17 void f(bool b) { ++b; // cxx98-14-warning@-1 {{incrementing expression of type bool is deprecated and incompatible with C++17}} - // since-cxx17-error@-2 {{SO C++17 does not allow incrementing expression of type bool}} + // since-cxx17-error@-2 {{ISO C++17 does not allow incrementing expression of type bool}} b++; // cxx98-14-warning@-1 {{incrementing expression of type bool is deprecated and incompatible with C++17}} - // since-cxx17-error@-2 {{SO C++17 does not allow incrementing expression of type bool}} + // since-cxx17-error@-2 {{ISO C++17 does not allow incrementing expression of type bool}} --b; // expected-error@-1 {{cannot decrement expression of type bool}} b--; @@ -453,7 +453,7 @@ namespace cwg1696 { // cwg1696: 7 struct A1 { A1() : v(42) {} // since-cxx14-error@-1 {{reference member 'v' binds to a temporary object whose lifetime would be shorter than the lifetime of the constructed object}} - // since-cxx14-note@#cwg1696-A1 {{reference member declared here}} + // since-cxx14-note@#cwg1696-A1 {{reference member declared here}} const int &v; // #cwg1696-A1 }; @@ -551,7 +551,7 @@ namespace cwg1696 { // cwg1696: 7 std::initializer_list il = {1, 2, 3}; // #cwg1696-il-5 haslist5() {} // since-cxx11-error@-1 {{backing array for 'std::initializer_list' member 'il' is a temporary object whose lifetime would be shorter than the lifetime of the constructed object}} - // since-cxx11-note@#cwg1696-il-5 {{nitializing field 'il' with default member initializer}} + // since-cxx11-note@#cwg1696-il-5 {{initializing field 'il' with default member initializer}} }; #endif } // namespace cwg1696 diff --git a/clang/test/CXX/drs/cwg18xx.cpp b/clang/test/CXX/drs/cwg18xx.cpp index 9948075852135..c0363fa467ea1 100644 --- a/clang/test/CXX/drs/cwg18xx.cpp +++ b/clang/test/CXX/drs/cwg18xx.cpp @@ -568,7 +568,7 @@ struct Bar { int a = 0; }; static_assert(__is_constructible(Baz), ""); - // since-cxx11-error@-1 {{static assertion failed due to requirement '__is_constructible(cwg1890::ex2::Bar::Baz)'}} + // since-cxx11-error@-1 {{static assertion failed due to requirement '__is_constructible(cwg1890::ex2::Bar::Baz)':}} // since-cxx11-note@#cwg1890-Baz {{'Baz' defined here}} }; #endif diff --git a/clang/test/CXX/drs/cwg19xx.cpp b/clang/test/CXX/drs/cwg19xx.cpp index 15ad3921cb1be..8bec8db734d78 100644 --- a/clang/test/CXX/drs/cwg19xx.cpp +++ b/clang/test/CXX/drs/cwg19xx.cpp @@ -123,7 +123,7 @@ namespace cwg1940 { // cwg1940: 3.5 static union { static_assert(true, ""); // ok static_assert(false, ""); - // since-cxx11-error@-1 {{static assertion failed}} + // since-cxx11-error@-1 {{static assertion failed:}} int not_empty; }; #endif diff --git a/clang/test/CXX/drs/cwg1xx.cpp b/clang/test/CXX/drs/cwg1xx.cpp index c9dce77b772dc..066a429ea1c59 100644 --- a/clang/test/CXX/drs/cwg1xx.cpp +++ b/clang/test/CXX/drs/cwg1xx.cpp @@ -910,7 +910,7 @@ namespace cwg152 { // cwg152: 2.7 namespace cwg154 { // cwg154: 2.7 union { int a; }; - // expected-error@-1 {{nonymous unions at namespace or global scope must be declared 'static'}} + // expected-error@-1 {{anonymous unions at namespace or global scope must be declared 'static'}} namespace { union { int b; }; } @@ -960,7 +960,7 @@ namespace cwg161 { // cwg161: 3.1 f(); sf(); c.f(); - // expected-error@-1 {{protected}} + // expected-error@-1 {{'f' is a protected member of 'cwg161::A'}} // expected-note@#cwg161-f {{declared protected here}} c.sf(); A::f(); diff --git a/clang/test/CXX/drs/cwg20xx.cpp b/clang/test/CXX/drs/cwg20xx.cpp index bd233bb09522f..339d4d83c47e9 100644 --- a/clang/test/CXX/drs/cwg20xx.cpp +++ b/clang/test/CXX/drs/cwg20xx.cpp @@ -160,16 +160,16 @@ namespace cwg2076 { // cwg2076: 13 foo({arg}); foo({{arg}}); foo({{{arg}}}); - // since-cxx11-error@-1 {{no matching function}} - // since-cxx11-note@#cwg2076-foo {{cannot convert initializer list}} + // since-cxx11-error@-1 {{no matching function for call to 'foo'}} + // since-cxx11-note@#cwg2076-foo {{candidate function not viable: cannot convert initializer list argument to 'const string'}} bar(arg); bar({arg}); bar({{arg}}); - // since-cxx11-error@-1 {{no matching function}} - // since-cxx11-note@#cwg2076-bar {{cannot convert initializer list}} + // since-cxx11-error@-1 {{no matching function for call to 'bar'}} + // since-cxx11-note@#cwg2076-bar {{candidate function not viable: cannot convert initializer list argument to 'string_view'}} bar({{{arg}}}); - // since-cxx11-error@-1 {{no matching function}} - // since-cxx11-note@#cwg2076-bar {{cannot convert initializer list}} + // since-cxx11-error@-1 {{no matching function for call to 'bar'}} + // since-cxx11-note@#cwg2076-bar {{candidate function not viable: cannot convert initializer list argument to 'string_view'}} } #endif } // namespace cwg2076 diff --git a/clang/test/CXX/drs/cwg22xx.cpp b/clang/test/CXX/drs/cwg22xx.cpp index 34119a162623e..5585602a2894e 100644 --- a/clang/test/CXX/drs/cwg22xx.cpp +++ b/clang/test/CXX/drs/cwg22xx.cpp @@ -108,7 +108,7 @@ namespace MultilevelSpecialization { template<> template void B::f(int i, int (&arr1)[a], int (&arr2)[b]) {} // since-cxx11-error@-1 {{out-of-line definition of 'f' does not match any declaration in 'cwg2233::MultilevelSpecialization::B'}} - // since-cxx11-note@#cwg2233-B {{defined here}} + // since-cxx11-note@#cwg2233-B {{B defined here}} template<> template<> void B::f<1, 1>(int i, int (&arr1a)[1], int (&arr2a)[1]) {} } diff --git a/clang/test/CXX/drs/cwg23xx.cpp b/clang/test/CXX/drs/cwg23xx.cpp index 72cf249f8b53d..ae52df2e9b8ea 100644 --- a/clang/test/CXX/drs/cwg23xx.cpp +++ b/clang/test/CXX/drs/cwg23xx.cpp @@ -270,7 +270,7 @@ namespace cwg2352 { // cwg2352: 10 // lvalue of type 'const int *const * const'? const int * const * r; void *y = &(true ? p : r); - // expected-error@-1 {{rvalue of type 'const int *const *'}} + // expected-error@-1 {{cannot take the address of an rvalue of type 'const int *const *'}} // FIXME: We order these as a speculative defect resolution. void f(const int * const * const &r); diff --git a/clang/test/CXX/drs/cwg26xx.cpp b/clang/test/CXX/drs/cwg26xx.cpp index aa87f5a1857c6..bfa785d75f06b 100644 --- a/clang/test/CXX/drs/cwg26xx.cpp +++ b/clang/test/CXX/drs/cwg26xx.cpp @@ -142,8 +142,8 @@ struct foo { void f() { foo fooable; // #cwg2628-fooable - // since-cxx20-error@#cwg2628-fooable {{call to deleted}} - // since-cxx20-note@#cwg2628-ctor {{marked deleted here}} + // since-cxx20-error@#cwg2628-fooable {{call to deleted constructor of 'foo<>' (aka 'cwg2628::foo<>')}} + // since-cxx20-note@#cwg2628-ctor {{'foo' has been explicitly marked deleted here}} } #endif } // namespace cwg2628 @@ -244,7 +244,7 @@ class X { }; int i0 = f(0); // since-cxx23-error@-1 {{no matching function for call to 'f'}} -// since-cxx23-note@#cwg2650-f {{type 'X' of non-type template parameter is not a structural type}} +// since-cxx23-note@#cwg2650-f {{candidate template ignored: substitution failure [with T = X]: type 'X' of non-type template parameter is not a structural type}} #endif } // namespace cwg2650 @@ -290,7 +290,7 @@ static_assert(__is_same(decltype(h), H)); // Not H static_assert(__is_same(decltype(i), I)); J j = { "ghi" }; -// since-cxx20-error@-1 {{no viable constructor or deduction guide}} +// since-cxx20-error@-1 {{no viable constructor or deduction guide for deduction of template arguments of 'J'}} // since-cxx20-note@#cwg2681-J {{candidate template ignored: could not match 'cwg2681::J' against 'const char *'}} // since-cxx20-note@#cwg2681-J {{implicit deduction guide declared as 'template J(cwg2681::J) -> cwg2681::J'}} // since-cxx20-note@#cwg2681-J {{candidate template ignored: could not match 'const unsigned char' against 'const char'}} @@ -370,8 +370,8 @@ void A::test() { (&A::g)(A()); // since-cxx23-error@-1 {{call to 'g' is ambiguous}} - // since-cxx23-note@#cwg2692-3 {{candidate function}} - // since-cxx23-note@#cwg2692-4 {{candidate function}} + // since-cxx23-note@#cwg2692-3 {{candidate function [with T = cwg2692::A]}} + // since-cxx23-note@#cwg2692-4 {{candidate function [with T = cwg2692::A]}} (&A::g)(); // since-cxx23-error@-1 {{no matching function for call to 'g'}} // since-cxx23-note@#cwg2692-3 {{candidate function template not viable: requires 1 argument, but 0 were provided}} diff --git a/clang/test/CXX/drs/cwg27xx.cpp b/clang/test/CXX/drs/cwg27xx.cpp index 7caf36a9f23b2..934646ae837e6 100644 --- a/clang/test/CXX/drs/cwg27xx.cpp +++ b/clang/test/CXX/drs/cwg27xx.cpp @@ -46,13 +46,13 @@ A(T...) -> A requires (sizeof...(T) == 2); // #cwg2707-guide- A a = {1, 2}; A b = {3, 4, 5}; -// since-cxx20-error@-1 {{no viable constructor or deduction guide}} -// since-cxx20-note@#cwg2707-A {{candidate function template not viable}} -// since-cxx20-note@#cwg2707-A {{implicit deduction guide}} -// since-cxx20-note@#cwg2707-guide-A {{constraints not satisfied}} +// since-cxx20-error@-1 {{no viable constructor or deduction guide for deduction of template arguments of 'A'}} +// since-cxx20-note@#cwg2707-A {{candidate function template not viable: requires 1 argument, but 3 were provided}} +// since-cxx20-note@#cwg2707-A {{implicit deduction guide declared as 'template A(cwg2707::A) -> cwg2707::A'}} +// since-cxx20-note@#cwg2707-guide-A {{candidate template ignored: constraints not satisfied [with T = ]}} // since-cxx20-note@#cwg2707-guide-A {{because 'sizeof...(T) == 2' (3 == 2) evaluated to false}} -// since-cxx20-note@#cwg2707-A {{candidate function template not viable}} -// since-cxx20-note@#cwg2707-A {{implicit deduction guide}} +// since-cxx20-note@#cwg2707-A {{candidate function template not viable: requires 0 arguments, but 3 were provided}} +// since-cxx20-note@#cwg2707-A {{implicit deduction guide declared as 'template A() -> cwg2707::A'}} #endif diff --git a/clang/test/CXX/drs/cwg29xx.cpp b/clang/test/CXX/drs/cwg29xx.cpp index f9c2e9ecf4618..7b0cc878f5bc8 100644 --- a/clang/test/CXX/drs/cwg29xx.cpp +++ b/clang/test/CXX/drs/cwg29xx.cpp @@ -74,8 +74,10 @@ template struct X { }; void test() { - &X::f; // since-cxx20-error {{reference to overloaded function could not be resolved}} - &X::g; // since-cxx20-error {{reference to overloaded function could not be resolved}} + &X::f; + // since-cxx20-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} + &X::g; + // since-cxx20-error@-1 {{reference to overloaded function could not be resolved; did you mean to call it?}} } } // namespace Example1 diff --git a/clang/test/CXX/drs/cwg30xx.cpp b/clang/test/CXX/drs/cwg30xx.cpp index 648ba9e78cd66..664e620672bcb 100644 --- a/clang/test/CXX/drs/cwg30xx.cpp +++ b/clang/test/CXX/drs/cwg30xx.cpp @@ -13,11 +13,11 @@ void f( int _, // #cwg3005-first-param int _) // expected-error@-1 {{redefinition of parameter '_'}} - // expected-note@#cwg3005-first-param {{previous definition is here}} + // expected-note@#cwg3005-first-param {{previous declaration is here}} { int _; // expected-error@-1 {{redefinition of '_'}} - // expected-note@#cwg3005-first-param {{previous declaration is here}} + // expected-note@#cwg3005-first-param {{previous definition is here}} } } // namespace cwg3005 diff --git a/clang/test/CXX/drs/cwg3xx.cpp b/clang/test/CXX/drs/cwg3xx.cpp index bbd87c060801a..754eb23157287 100644 --- a/clang/test/CXX/drs/cwg3xx.cpp +++ b/clang/test/CXX/drs/cwg3xx.cpp @@ -198,8 +198,8 @@ namespace cwg306 { // cwg306: dup 39 Z::X zx; Z::X zcx; // expected-error@-1 {{member 'X' found in multiple base classes of different types}} - // expected-note@#cwg306-X {{member type 'cwg306::X' found}} - // expected-note@#cwg306-typedef-X {{member type 'const cwg306::X' found}} + // expected-note@#cwg306-X {{member type 'cwg306::X' found by ambiguous name lookup}} + // expected-note@#cwg306-typedef-X {{member type 'const cwg306::X' found by ambiguous name lookup}} } // namespace cwg306 // cwg307: na @@ -601,7 +601,7 @@ namespace cwg336 { // cwg336: 2.7 template<> template class A::B {}; // #cwg336-B template<> template<> template void A::B::mf1(T t) {} // expected-error@-1 {{out-of-line definition of 'mf1' does not match any declaration in 'cwg336::Pre::A::B'}} - // expected-note@#cwg336-B {{defined here}} + // expected-note@#cwg336-B {{B defined here}} template template<> void A::B::mf2() {} // expected-error@-1 {{nested name specifier 'A::B' for declaration does not refer into a class, class template or class template partial specialization}} } @@ -652,8 +652,8 @@ namespace cwg339 { // cwg339: 2.8 A<1> a = f(0); A<2> b = f(0.0f); A<3> c = f("foo"); - // expected-error@-1 {{no matching function}} - // expected-note@#cwg339-f {{candidate}} + // expected-error@-1 {{no matching function for call to 'f'}} + // expected-note@#cwg339-f {{candidate template ignored: substitution failure [with T = const char *]: no matching function for call to 'xxx'}} } @@ -770,10 +770,10 @@ namespace cwg347 { // cwg347: 2.7 // expected-error@-1 {{no member named 'n' in 'cwg347::derived'}} void derived::f() {} // expected-error@-1 {{out-of-line definition of 'f' does not match any declaration in 'cwg347::derived'}} - // expected-note@#cwg347-derived {{defined here}} + // expected-note@#cwg347-derived {{derived defined here}} void derived::g() {} // expected-error@-1 {{out-of-line definition of 'g' does not match any declaration in 'cwg347::derived'}} - // expected-note@#cwg347-derived {{defined here}} + // expected-note@#cwg347-derived {{derived defined here}} } // namespace cwg347 // cwg348: na @@ -1028,7 +1028,7 @@ namespace cwg357 { // cwg357: 2.7 }; template void A::f() {} // expected-error@-1 {{out-of-line definition of 'f' does not match any declaration in 'cwg357::A'}} - // expected-note@#cwg357-A {{defined here}} + // expected-note@#cwg357-A {{A defined here}} // expected-note@#cwg357-f {{member declaration does not match because it is const qualified}} struct B { // #cwg357-B @@ -1036,7 +1036,7 @@ namespace cwg357 { // cwg357: 2.7 }; template void B::f() const {} // expected-error@-1 {{out-of-line definition of 'f' does not match any declaration in 'cwg357::B'}} - // expected-note@#cwg357-B {{defined here}} + // expected-note@#cwg357-B {{B defined here}} } // namespace cwg357 namespace cwg358 { // cwg358: 2.7 @@ -1128,10 +1128,10 @@ namespace cwg366 { // cwg366: 2.7 namespace cwg367 { // cwg367: 2.7 static_assert(__enable_constant_folding(true ? throw 0 : 4), ""); - // expected-error@-1 {{expression is not an integral constant expression}} + // expected-error@-1 {{static assertion expression is not an integral constant expression}} static_assert(__enable_constant_folding(true ? 4 : throw 0), ""); static_assert(__enable_constant_folding(true ? *new int : 4), ""); - // expected-error@-1 {{expression is not an integral constant expression}} + // expected-error@-1 {{static assertion expression is not an integral constant expression}} // expected-note@-2 {{read of uninitialized object is not allowed in a constant expression}} static_assert(__enable_constant_folding(true ? 4 : *new int), ""); } // namespace cwg367 @@ -1781,7 +1781,7 @@ namespace cwg398 { // cwg398: 2.7 // expected-note@#cwg398-f {{candidate template ignored: substitution failure [with T = B]: typename specifier refers to non-type member 'Y' in 'cwg398::example2::B'}} g(0); // expected-error@-1 {{no matching function for call to 'g'}} - // expected-note@#cwg398-g {{candidate template ignored: substitution failure [with T = C]: missing 'typename' prior to dependent type name 'C::N'}} + // expected-note@#cwg398-g {{candidate template ignored: substitution failure [with T = C]: missing 'typename' prior to dependent type name 'C::N' (aka 'int')}} h(0); // expected-error@-1 {{no matching function for call to 'h'}} // expected-note@#cwg398-h {{candidate template ignored: substitution failure [with T = D]: 'TT' following the 'template' keyword does not refer to a template}} diff --git a/clang/test/CXX/drs/cwg4xx.cpp b/clang/test/CXX/drs/cwg4xx.cpp index 8497f974b2ece..eccfbea014921 100644 --- a/clang/test/CXX/drs/cwg4xx.cpp +++ b/clang/test/CXX/drs/cwg4xx.cpp @@ -196,7 +196,7 @@ namespace cwg407 { // cwg407: 3.8 using namespace A; using namespace B; struct S s; - // expected-error@-1 {{ambiguous}} + // expected-error@-1 {{reference to 'S' is ambiguous}} // expected-note@#cwg407-A-S {{candidate found by name lookup is 'cwg407::UsingDir::A::S'}} // expected-note@#cwg407-B-S {{candidate found by name lookup is 'cwg407::UsingDir::B::S'}} } @@ -595,7 +595,7 @@ namespace cwg429 { // cwg429: 2.8 c++11 static void operator delete(void*, size_t); // #cwg429-delete } *a = new (0) A; // since-cxx11-error@-1 {{'new' expression with placement arguments refers to non-placement 'operator delete'}} - // since-cxx11-note@#cwg429-delete {{here}} + // since-cxx11-note@#cwg429-delete {{'operator delete' declared here}} struct B { static void *operator new(size_t, size_t); static void operator delete(void*); @@ -857,7 +857,7 @@ namespace cwg451 { // cwg451: 2.7 const int b = 1 / 0; // #cwg451-b // expected-warning@-1 {{division by zero is undefined}} static_assert(b, ""); - // expected-error@-1 {{expression is not an integral constant expression}} + // expected-error@-1 {{static assertion expression is not an integral constant expression}} // expected-note@-2 {{initializer of 'b' is not a constant expression}} // expected-note@#cwg451-b {{declared here}} } // namespace cwg451 @@ -882,7 +882,7 @@ namespace cwg456 { // cwg456: 3.4 const bool f = false; void *q = f; - // cxx98-warning@-1 {{initialization of pointer of type 'void *' to null from a constant boolean}} + // cxx98-warning@-1 {{initialization of pointer of type 'void *' to null from a constant boolean expression}} // since-cxx11-error@-2 {{cannot initialize a variable of type 'void *' with an lvalue of type 'const bool'}} } // namespace cwg456 @@ -891,7 +891,7 @@ namespace cwg457 { // cwg457: 2.7 const volatile int b = 1; static_assert(a, ""); static_assert(b, ""); - // expected-error@-1 {{expression is not an integral constant expression}} + // expected-error@-1 {{static assertion expression is not an integral constant expression}} // expected-note@-2 {{read of volatile-qualified type 'const volatile int' is not allowed in a constant expression}} enum E { @@ -1119,9 +1119,9 @@ namespace cwg477 { // cwg477: 3.5 // expected-error@-1 {{'virtual' is invalid in friend declarations}} }; explicit A::A() {} - // expected-error@-1 {{can only be specified inside the class definition}} + // expected-error@-1 {{'explicit' can only be specified inside the class definition}} virtual void A::f() {} - // expected-error@-1 {{can only be specified inside the class definition}} + // expected-error@-1 {{'virtual' can only be specified inside the class definition}} } // namespace cwg477 namespace cwg478 { // cwg478: 2.7 @@ -1379,7 +1379,7 @@ namespace cwg487 { // cwg487: 2.7 enum E { e }; int operator+(int, E); // #cwg487-operator-plus static_assert(4 + e, ""); - // expected-error@-1 {{expression is not an integral constant expression}} + // expected-error@-1 {{static assertion expression is not an integral constant expression}} // since-cxx11-note@-2 {{non-constexpr function 'operator+' cannot be used in a constant expression}} // since-cxx11-note@#cwg487-operator-plus {{declared here}} } // namespace cwg487 @@ -1395,7 +1395,7 @@ namespace cwg488 { // cwg488: 2.9 c++11 enum E { e }; f(e); // cxx98-error@-1 {{template argument uses local type 'E'}} - // cxx98-note@-2 {{while substituting deduced template arguments}} + // cxx98-note@-2 {{while substituting deduced template arguments into function template 'f' [with T = E]}} } } // namespace cwg488 diff --git a/clang/test/CXX/drs/cwg5xx.cpp b/clang/test/CXX/drs/cwg5xx.cpp index 1d505adecfb27..f29c1e8131019 100644 --- a/clang/test/CXX/drs/cwg5xx.cpp +++ b/clang/test/CXX/drs/cwg5xx.cpp @@ -184,7 +184,7 @@ namespace cwg522 { // cwg522: 2.7 b2(am); b2a(am); // expected-error@-1 {{no matching function for call to 'b2a'}} - // expected-note@#cwg522-b2a {{candidate template ignored: deduced type 'volatile int *S::*const *' of 1st parameter does not match adjusted type 'int *S::**' of argument}} + // expected-note@#cwg522-b2a {{candidate template ignored: deduced type 'volatile int *S::*const *' of 1st parameter does not match adjusted type 'int *S::**' of argument [with T = int]}} b3(d); b3(cd); } @@ -348,11 +348,11 @@ namespace cwg531 { // cwg531: partial void A::f(int) {} // expected-error@-1 {{template specialization requires 'template<>'}} template void A::g(int, U) {} - // expected-error@-1 {{template parameter list matching the non-templated nested type 'cwg531::bad::A' should be empty}} + // expected-error@-1 {{template parameter list matching the non-templated nested type 'cwg531::bad::A' should be empty ('template<>')}} struct A::B {}; // expected-error@-1 {{template specialization requires 'template<>'}} template struct A::C {}; - // expected-error@-1 {{template parameter list matching the non-templated nested type 'cwg531::bad::A' should be empty}} + // expected-error@-1 {{template parameter list matching the non-templated nested type 'cwg531::bad::A' should be empty ('template<>')}} // expected-error@-2 {{redefinition of 'C' as different kind of symbol}} // expected-note@#cwg531-C {{previous definition is here}} int A::n = 0; @@ -880,7 +880,7 @@ namespace cwg569 { // cwg569: 2.7 c++11 // FIXME: This is a DR issue against C++98, so should probably apply there // too. ;;;;; - // cxx98-error@-1 {{C++11 extension}} + // cxx98-error@-1 {{extra ';' outside of a function is a C++11 extension}} } // namespace cwg569 namespace cwg570 { // cwg570: dup 633 @@ -957,7 +957,7 @@ namespace cwg574 { // cwg574: 3.0 #elif __cplusplus >= 201103L // FIXME: We shouldn't produce the 'cannot overload' diagnostics here. friend C &C::operator=(const C&); // #cwg574-test-C - // since-cxx11-error@#cwg574-test-C {{cannot overload}} + // since-cxx11-error@#cwg574-test-C {{cannot overload a member function without a ref-qualifier with a member function with ref-qualifier '&'}} // since-cxx11-note@#cwg574-C-copy-assign {{previous declaration is here}} // since-cxx11-error@#cwg574-test-C {{friend declaration of 'operator=' does not match any declaration in 'cwg574::C'}} // since-cxx11-note@#cwg574-C-copy-assign {{candidate function}} @@ -1238,7 +1238,7 @@ namespace cwg591 { // cwg591: 20 template struct A::B::D : A { M m; - // expected-error@-1 {{field has incomplete type 'M' (aka 'void'}} + // expected-error@-1 {{field has incomplete type 'M' (aka 'void')}} }; template @@ -1246,7 +1246,7 @@ namespace cwg591 { // cwg591: 20 template struct H::B::C::P : B { M m; - // expected-error@-1 {{field has incomplete type 'M' (aka 'void'}} + // expected-error@-1 {{field has incomplete type 'M' (aka 'void')}} }; } // namespace cwg591 diff --git a/clang/test/CXX/drs/cwg6xx.cpp b/clang/test/CXX/drs/cwg6xx.cpp index 8eac049211193..3937a80d4f3c9 100644 --- a/clang/test/CXX/drs/cwg6xx.cpp +++ b/clang/test/CXX/drs/cwg6xx.cpp @@ -618,8 +618,8 @@ namespace cwg647 { // cwg647: 3.1 : n(0), d(0.0f) {} // #cwg647-int-d constexpr E(float f) - // cxx11-20-error@-1 {{never produces a constant expression}} - // cxx11-20-note@#cwg647-float-d {{non-constexpr constructor}} + // cxx11-20-error@-1 {{constexpr constructor never produces a constant expression}} + // cxx11-20-note@#cwg647-float-d {{non-constexpr constructor 'D' cannot be used in a constant expression}} // cxx11-20-note@#cwg647-D-float-ctor {{declared here}} : n(get()), d(D(0) + f) {} // #cwg647-float-d @@ -895,12 +895,12 @@ namespace cwg666 { // cwg666: 2.8 template int f(); template int f() { T::type *p = 0; - // expected-error@-1 {{missing 'typename' prior to dependent type name 'cwg666::Y::type'}} + // expected-error@-1 {{missing 'typename' prior to dependent type name 'cwg666::Y::type' (aka 'int')}} // expected-note@#cwg666-f-Y {{in instantiation of function template specialization 'cwg666::f' requested here}} int a(T::type); - // expected-error@-1 {{missing 'typename' prior to dependent type name 'cwg666::Y::type'}} + // expected-error@-1 {{missing 'typename' prior to dependent type name 'cwg666::Y::type' (aka 'int')}} return f(); - // expected-error@-1 {{missing 'typename' prior to dependent type name 'cwg666::Y::type'}} + // expected-error@-1 {{missing 'typename' prior to dependent type name 'cwg666::Y::type' (aka 'int')}} } struct X { static const int type = 0; }; struct Y { typedef int type; }; @@ -1159,7 +1159,7 @@ namespace cwg684 { // cwg684: sup 1454 constexpr int *p = &a; // since-cxx11-error@-1 {{constexpr variable 'p' must be initialized by a constant expression}} // since-cxx11-note@-2 {{pointer to 'a' is not a constant expression}} - // since-cxx11-note@#cwg684-a {{here}} + // since-cxx11-note@#cwg684-a {{declared here}} } #endif } // namespace cwg684 @@ -1308,7 +1308,7 @@ namespace cwg692 { // cwg692: 16 // expected-note@#cwg692-f-deleted {{candidate function [with T = int, U = int] has been explicitly deleted}} // expected-note@#cwg692-f {{candidate function [with U = int]}} g(42); - // expected-error@-1 {{ambiguous}} + // expected-error@-1 {{call to 'g' is ambiguous}} // expected-note@#cwg692-g {{candidate function [with T = int]}} // expected-note@#cwg692-g-variadic {{candidate function [with T = int, U = <>]}} } diff --git a/clang/test/CXX/drs/cwg7xx.cpp b/clang/test/CXX/drs/cwg7xx.cpp index 9ff01f316e3d1..84bcc07bf0a3e 100644 --- a/clang/test/CXX/drs/cwg7xx.cpp +++ b/clang/test/CXX/drs/cwg7xx.cpp @@ -21,7 +21,7 @@ namespace cwg705 { // cwg705: 2.7 N::S s; f(s); // ok (f)(s); - // expected-error@-1 {{use of undeclared identifier 'f'}} + // expected-error@-1 {{use of undeclared identifier 'f'; did you mean 'N::f'?}} // expected-note@#cwg705-f {{'N::f' declared here}} } } // namespace cwg705 @@ -273,7 +273,7 @@ namespace cwg727 { // cwg727: partial static_assert(B<1>().v<0> == 2, ""); static_assert(B<0>().v<1> == 3, ""); static_assert(B<0>().v<0> == 4, ""); - // cxx14-error@-1 {{static assertion failed due to requirement 'cwg727::mixed_inner_outer_specialization::B<0>().v<0> == 4'}} + // cxx14-error@-1 {{static assertion failed due to requirement 'cwg727::mixed_inner_outer_specialization::B<0>().v<0> == 4':}} // cxx14-note@-2 {{expression evaluates to '2 == 4'}} static_assert(B<1>().w<1> == 1, ""); diff --git a/clang/test/ClangScanDeps/prune-scanning-modules.m b/clang/test/ClangScanDeps/prune-scanning-modules.m index 8ceac9fd0ae38..0afcbd1313d65 100644 --- a/clang/test/ClangScanDeps/prune-scanning-modules.m +++ b/clang/test/ClangScanDeps/prune-scanning-modules.m @@ -8,14 +8,14 @@ // Check no pruning happens because pcms are new enough. // RUN: touch -m -a -t 201101010000 %t/modules.timestamp -// RUN: clang-scan-deps -j 1 -format experimental-full -o info.json -- %clang -fmodules -F %t/Frameworks \ +// RUN: clang-scan-deps -j 1 -format experimental-full -o /dev/null -- %clang -fmodules -F %t/Frameworks \ // RUN: -fmodules-cache-path=%t/cache %t/prune.m -fmodules -fmodules-prune-interval=172800 -fmodules-prune-after=345600 // RUN: ls -R %t | grep ^Module.*pcm // RUN: ls -R %t | grep DependsOnModule.*pcm // Check no pruning happens because modules.timestamp is new enough. // RUN: find %t/cache -name DependsOnModule*.pcm | sed -e 's/\\/\//g' | xargs touch -a -t 201101010000 -// RUN: clang-scan-deps -j 1 -format experimental-full -o info.json -- %clang -fmodules -F %t/Frameworks \ +// RUN: clang-scan-deps -j 1 -format experimental-full -o /dev/null -- %clang -fmodules -F %t/Frameworks \ // RUN: -fmodules-cache-path=%t/cache %t/prune.m -fmodules -fmodules-prune-interval=172800 -fmodules-prune-after=345600 // RUN: ls -R %t/cache | grep ^Module.*pcm // RUN: ls -R %t/cache | grep DependsOnModule.*pcm @@ -24,7 +24,7 @@ // RUN: touch -m -a -t 201101010000 %t/cache/modules.timestamp // RUN: find %t/cache -name DependsOnModule*.pcm | sed -e 's/\\/\//g' | xargs touch -a -t 201101010000 // RUN: find %t/cache -name Module*.pcm | sed -e 's/\\/\//g' | xargs touch -a -t 201101010000 -// RUN: clang-scan-deps -j 1 -format experimental-full -o info.json -- %clang -fmodules -F %t/Frameworks -DSKIP_MODULE \ +// RUN: clang-scan-deps -j 1 -format experimental-full -o /dev/null -- %clang -fmodules -F %t/Frameworks -DSKIP_MODULE \ // RUN: -fmodules-cache-path=%t/cache %t/prune.m -fmodules -fmodules-prune-interval=172800 -fmodules-prune-after=345600 // RUN: ls -R %t/cache | not grep ^Module.*pcm // RUN: ls -R %t/cache | not grep DependsOnModule.*pcm diff --git a/clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c b/clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c index d74470304c69e..1b77ead54d2b2 100644 --- a/clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c +++ b/clang/test/CodeGen/AMDGPU/amdgpu-atomic-float.c @@ -5,16 +5,12 @@ // SAFE-LABEL: define dso_local float @test_float_post_inc( // SAFE-SAME: ) #[[ATTR0:[0-9]+]] { // SAFE-NEXT: [[ENTRY:.*:]] -// SAFE-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) -// SAFE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // SAFE-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test_float_post_inc.n to ptr), float 1.000000e+00 seq_cst, align 4, !amdgpu.no.fine.grained.memory [[META3:![0-9]+]], !amdgpu.no.remote.memory [[META3]] // SAFE-NEXT: ret float [[TMP0]] // // UNSAFE-LABEL: define dso_local float @test_float_post_inc( // UNSAFE-SAME: ) #[[ATTR0:[0-9]+]] { // UNSAFE-NEXT: [[ENTRY:.*:]] -// UNSAFE-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) -// UNSAFE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // UNSAFE-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test_float_post_inc.n to ptr), float 1.000000e+00 seq_cst, align 4, !amdgpu.no.fine.grained.memory [[META3:![0-9]+]], !amdgpu.no.remote.memory [[META3]], !amdgpu.ignore.denormal.mode [[META3]] // UNSAFE-NEXT: ret float [[TMP0]] // @@ -27,8 +23,6 @@ float test_float_post_inc() // CHECK-LABEL: define dso_local float @test_float_post_dc( // CHECK-SAME: ) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test_float_post_dc.n to ptr), float 1.000000e+00 seq_cst, align 4, !amdgpu.no.fine.grained.memory [[META3:![0-9]+]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: ret float [[TMP0]] // @@ -41,8 +35,6 @@ float test_float_post_dc() // CHECK-LABEL: define dso_local float @test_float_pre_dc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test_float_pre_dc.n to ptr), float 1.000000e+00 seq_cst, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: [[TMP1:%.*]] = fsub float [[TMP0]], 1.000000e+00 // CHECK-NEXT: ret float [[TMP1]] @@ -56,8 +48,6 @@ float test_float_pre_dc() // SAFE-LABEL: define dso_local float @test_float_pre_inc( // SAFE-SAME: ) #[[ATTR0]] { // SAFE-NEXT: [[ENTRY:.*:]] -// SAFE-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) -// SAFE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // SAFE-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test_float_pre_inc.n to ptr), float 1.000000e+00 seq_cst, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // SAFE-NEXT: [[TMP1:%.*]] = fadd float [[TMP0]], 1.000000e+00 // SAFE-NEXT: ret float [[TMP1]] @@ -65,8 +55,6 @@ float test_float_pre_dc() // UNSAFE-LABEL: define dso_local float @test_float_pre_inc( // UNSAFE-SAME: ) #[[ATTR0]] { // UNSAFE-NEXT: [[ENTRY:.*:]] -// UNSAFE-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) -// UNSAFE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // UNSAFE-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test_float_pre_inc.n to ptr), float 1.000000e+00 seq_cst, align 4, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]], !amdgpu.ignore.denormal.mode [[META3]] // UNSAFE-NEXT: [[TMP1:%.*]] = fadd float [[TMP0]], 1.000000e+00 // UNSAFE-NEXT: ret float [[TMP1]] @@ -80,8 +68,6 @@ float test_float_pre_inc() // CHECK-LABEL: define dso_local double @test_double_post_inc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test_double_post_inc.n to ptr), double 1.000000e+00 seq_cst, align 8, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: ret double [[TMP0]] // @@ -94,8 +80,6 @@ double test_double_post_inc() // CHECK-LABEL: define dso_local double @test_double_post_dc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test_double_post_dc.n to ptr), double 1.000000e+00 seq_cst, align 8, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: ret double [[TMP0]] // @@ -108,8 +92,6 @@ double test_double_post_dc() // CHECK-LABEL: define dso_local double @test_double_pre_dc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test_double_pre_dc.n to ptr), double 1.000000e+00 seq_cst, align 8, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: [[TMP1:%.*]] = fsub double [[TMP0]], 1.000000e+00 // CHECK-NEXT: ret double [[TMP1]] @@ -123,8 +105,6 @@ double test_double_pre_dc() // CHECK-LABEL: define dso_local double @test_double_pre_inc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test_double_pre_inc.n to ptr), double 1.000000e+00 seq_cst, align 8, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: [[TMP1:%.*]] = fadd double [[TMP0]], 1.000000e+00 // CHECK-NEXT: ret double [[TMP1]] @@ -138,8 +118,6 @@ double test_double_pre_inc() // CHECK-LABEL: define dso_local half @test__Float16_post_inc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca half, align 2, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test__Float16_post_inc.n to ptr), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: ret half [[TMP0]] // @@ -152,8 +130,6 @@ _Float16 test__Float16_post_inc() // CHECK-LABEL: define dso_local half @test__Float16_post_dc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca half, align 2, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test__Float16_post_dc.n to ptr), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: ret half [[TMP0]] // @@ -166,8 +142,6 @@ _Float16 test__Float16_post_dc() // CHECK-LABEL: define dso_local half @test__Float16_pre_dc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca half, align 2, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fsub ptr addrspacecast (ptr addrspace(1) @test__Float16_pre_dc.n to ptr), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: [[TMP1:%.*]] = fsub half [[TMP0]], 0xH3C00 // CHECK-NEXT: ret half [[TMP1]] @@ -181,8 +155,6 @@ _Float16 test__Float16_pre_dc() // CHECK-LABEL: define dso_local half @test__Float16_pre_inc( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca half, align 2, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = atomicrmw fadd ptr addrspacecast (ptr addrspace(1) @test__Float16_pre_inc.n to ptr), half 0xH3C00 seq_cst, align 2, !amdgpu.no.fine.grained.memory [[META3]], !amdgpu.no.remote.memory [[META3]] // CHECK-NEXT: [[TMP1:%.*]] = fadd half [[TMP0]], 0xH3C00 // CHECK-NEXT: ret half [[TMP1]] diff --git a/clang/test/CodeGen/AMDGPU/full-bf16.c b/clang/test/CodeGen/AMDGPU/full-bf16.c index d2ec34561cd8e..3ce1027b95805 100644 --- a/clang/test/CodeGen/AMDGPU/full-bf16.c +++ b/clang/test/CodeGen/AMDGPU/full-bf16.c @@ -10,10 +10,8 @@ // CHECK-LABEL: define dso_local bfloat @div( // CHECK-SAME: bfloat noundef [[A:%.*]], bfloat noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca bfloat, align 2, addrspace(5) // CHECK-NEXT: [[A_ADDR:%.*]] = alloca bfloat, align 2, addrspace(5) // CHECK-NEXT: [[B_ADDR:%.*]] = alloca bfloat, align 2, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr // CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr // CHECK-NEXT: store bfloat [[A]], ptr [[A_ADDR_ASCAST]], align 2 diff --git a/clang/test/CodeGen/ARM/build-attributes.c b/clang/test/CodeGen/ARM/build-attributes.c new file mode 100644 index 0000000000000..2018b9ccaa5ca --- /dev/null +++ b/clang/test/CodeGen/ARM/build-attributes.c @@ -0,0 +1,24 @@ +// RUN: %clang_cc1 -triple arm-none-eabi -fdenormal-fp-math=positive-zero -emit-llvm -o - | FileCheck %s --check-prefix=DM-PZ +// RUN: %clang_cc1 -triple arm-none-eabi -fdenormal-fp-math=ieee -emit-llvm -o - | FileCheck %s --check-prefix=DM-IEEE +// RUN: %clang_cc1 -triple arm-none-eabi -fdenormal-fp-math=preserve-sign -emit-llvm -o - | FileCheck %s --check-prefix=DM-PS + +// RUN: %clang_cc1 -triple arm-none-eabi -menable-no-infs -menable-no-nans -emit-llvm -o - | FileCheck %s --check-prefix=NM-FIN +// RUN: %clang_cc1 -triple arm-none-eabi -emit-llvm -o - | FileCheck %s --check-prefix=NM-IEEE + +// RUN: %clang -target arm-none-eabi -S %s -emit-llvm -o - | FileCheck %s --check-prefix=FP-EXCEPT-IGNORE +// RUN: %clang -target arm-none-eabi -S %s -ffp-model=precise -emit-llvm -o - | FileCheck %s --check-prefix=FP-EXCEPT-IGNORE +// RUN: %clang -target arm-none-eabi -S %s -ffp-model=fast -emit-llvm -o - | FileCheck %s --check-prefix=FP-EXCEPT-IGNORE +// RUN: %clang -target arm-none-eabi -S %s -ffp-model=aggressive -emit-llvm -o - | FileCheck %s --check-prefix=FP-EXCEPT-IGNORE +// XUN: %clang -target arm-none-eabi -S %s -ffp-model=strict -emit-llvm -o - | FileCheck %s --check-prefix=FP-EXCEPT-CHECK + +// DM-PZ: !{i32 7, !"arm-eabi-fp-denormal", i32 0} +// DM-IEEE: !{i32 4, !"arm-eabi-fp-denormal", i32 1} +// DM-PS: !{i32 7, !"arm-eabi-fp-denormal", i32 2} + +// NM-FIN: !{i32 8, !"arm-eabi-fp-number-model", i32 1} +// NM-IEEE: !{i32 8, !"arm-eabi-fp-number-model", i32 3} + +// FP-EXCEPT-IGNORE-NOT: !{i32 2, !"arm-eabi-fp-exceptions", i32 1} +// FP-EXCEPT-CHECK: !{i32 2, !"arm-eabi-fp-exceptions", i32 1} + +void foo() {} diff --git a/clang/test/CodeGen/WebAssembly/builtins-table.c b/clang/test/CodeGen/WebAssembly/builtins-table-externref.c similarity index 100% rename from clang/test/CodeGen/WebAssembly/builtins-table.c rename to clang/test/CodeGen/WebAssembly/builtins-table-externref.c diff --git a/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c b/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c new file mode 100644 index 0000000000000..b4f729669a795 --- /dev/null +++ b/clang/test/CodeGen/WebAssembly/builtins-table-funcref.c @@ -0,0 +1,69 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature +// RUN: %clang_cc1 -triple wasm32 -target-feature +reference-types -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s +// REQUIRES: webassembly-registered-target + +typedef void (*__funcref funcref_t)(); +static funcref_t table[0]; + +// CHECK-LABEL: define {{[^@]+}}@test_builtin_wasm_table_get +// CHECK-SAME: (i32 noundef [[INDEX:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call ptr addrspace(20) @llvm.wasm.table.get.funcref(ptr addrspace(1) @table, i32 [[INDEX]]) +// CHECK-NEXT: ret ptr addrspace(20) [[TMP0]] +// +funcref_t test_builtin_wasm_table_get(int index) { + return __builtin_wasm_table_get(table, index); +} + +// CHECK-LABEL: define {{[^@]+}}@test_builtin_wasm_table_set +// CHECK-SAME: (i32 noundef [[INDEX:%.*]], ptr addrspace(20) noundef [[REF:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @llvm.wasm.table.set.funcref(ptr addrspace(1) @table, i32 [[INDEX]], ptr addrspace(20) [[REF]]) +// CHECK-NEXT: ret void +// +void test_builtin_wasm_table_set(int index, funcref_t ref) { + return __builtin_wasm_table_set(table, index, ref); +} + +// CHECK-LABEL: define {{[^@]+}}@test_builtin_wasm_table_size +// CHECK-SAME: () #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.wasm.table.size(ptr addrspace(1) @table) +// CHECK-NEXT: ret i32 [[TMP0]] +// +int test_builtin_wasm_table_size() { + return __builtin_wasm_table_size(table); +} + + +// CHECK-LABEL: define {{[^@]+}}@test_builtin_wasm_table_grow +// CHECK-SAME: (ptr addrspace(20) noundef [[REF:%.*]], i32 noundef [[NELEM:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.wasm.table.grow.funcref(ptr addrspace(1) @table, ptr addrspace(20) [[REF]], i32 [[NELEM]]) +// CHECK-NEXT: ret i32 [[TMP0]] +// +int test_builtin_wasm_table_grow(funcref_t ref, int nelem) { + return __builtin_wasm_table_grow(table, ref, nelem); +} + +// CHECK-LABEL: define {{[^@]+}}@test_builtin_wasm_table_fill +// CHECK-SAME: (i32 noundef [[INDEX:%.*]], ptr addrspace(20) noundef [[REF:%.*]], i32 noundef [[NELEM:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @llvm.wasm.table.fill.funcref(ptr addrspace(1) @table, i32 [[INDEX]], ptr addrspace(20) [[REF]], i32 [[NELEM]]) +// CHECK-NEXT: ret void +// +void test_builtin_wasm_table_fill(int index, funcref_t ref, int nelem) { + __builtin_wasm_table_fill(table, index, ref, nelem); +} + +static funcref_t other_table[0]; + +// CHECK-LABEL: define {{[^@]+}}@test_table_copy +// CHECK-SAME: (i32 noundef [[DST_IDX:%.*]], i32 noundef [[SRC_IDX:%.*]], i32 noundef [[NELEM:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @llvm.wasm.table.copy(ptr addrspace(1) @table, ptr addrspace(1) @other_table, i32 [[SRC_IDX]], i32 [[DST_IDX]], i32 [[NELEM]]) +// CHECK-NEXT: ret void +// +void test_table_copy(int dst_idx, int src_idx, int nelem) { + __builtin_wasm_table_copy(table, other_table, dst_idx, src_idx, nelem); +} diff --git a/clang/test/CodeGen/amdgpu-abi-version.c b/clang/test/CodeGen/amdgpu-abi-version.c index b9c1de0521b95..cc6223da76554 100644 --- a/clang/test/CodeGen/amdgpu-abi-version.c +++ b/clang/test/CodeGen/amdgpu-abi-version.c @@ -7,8 +7,6 @@ // CHECK-LABEL: define dso_local i32 @foo( // CHECK-SAME: ) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) @__oclc_ABI_version, align 4 // CHECK-NEXT: [[TMP1:%.*]] = icmp sge i32 [[TMP0]], 500 // CHECK-NEXT: [[TMP2:%.*]] = call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() diff --git a/clang/test/CodeGen/attr-ifunc.c b/clang/test/CodeGen/attr-ifunc.c index c9e70b17a8302..55d1866c17a69 100644 --- a/clang/test/CodeGen/attr-ifunc.c +++ b/clang/test/CodeGen/attr-ifunc.c @@ -4,6 +4,8 @@ // RUN: %clang_cc1 -triple x86_64-apple-macosx -verify -emit-llvm-only %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -verify -emit-llvm-only %s // RUN: %clang_cc1 -triple aarch64-pc-windows-msvcu -verify -emit-llvm-only %s +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify -emit-llvm-only %s +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify -emit-llvm-only -DCHECK_ALIASES %s #if defined(_WIN32) && !defined(__aarch64__) void foo(void) {} diff --git a/clang/test/CodeGen/attr-ifunc.cpp b/clang/test/CodeGen/attr-ifunc.cpp index 9e6cd7312122d..601fad94530bd 100644 --- a/clang/test/CodeGen/attr-ifunc.cpp +++ b/clang/test/CodeGen/attr-ifunc.cpp @@ -1,9 +1,11 @@ // RUN: %clang_cc1 -triple x86_64-linux -verify -emit-llvm-only %s // RUN: %clang_cc1 -triple x86_64-apple-macosx -verify -emit-llvm-only %s // RUN: %clang_cc1 -triple arm64-apple-macosx -verify -emit-llvm-only %s +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -verify -emit-llvm-only %s // RUN: not %clang_cc1 -triple x86_64-linux -emit-llvm-only -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s // RUN: not %clang_cc1 -triple x86_64-apple-macosx -emit-llvm-only -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s // RUN: not %clang_cc1 -triple arm64-apple-macosx -emit-llvm-only -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s +// RUN: not %clang_cc1 -triple powerpc64-ibm-aix-xcoff -emit-llvm-only -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s void *f1_ifunc(void) { return nullptr; } void f1(void) __attribute__((ifunc("f1_ifunc"))); diff --git a/clang/test/CodeGen/builtins-extended-image.c b/clang/test/CodeGen/builtins-extended-image.c index 0dbf81dabd77b..491bbcf7d5412 100644 --- a/clang/test/CodeGen/builtins-extended-image.c +++ b/clang/test/CodeGen/builtins-extended-image.c @@ -8,13 +8,11 @@ typedef _Float16 half4 __attribute__((ext_vector_type(4))); // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_gather4_lz_2d_v4f32_f32_r( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -41,13 +39,11 @@ float4 test_amdgcn_image_gather4_lz_2d_v4f32_f32_r(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_gather4_lz_2d_v4f32_f32_g( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -74,13 +70,11 @@ float4 test_amdgcn_image_gather4_lz_2d_v4f32_f32_g(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_gather4_lz_2d_v4f32_f32_b( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -107,13 +101,11 @@ float4 test_amdgcn_image_gather4_lz_2d_v4f32_f32_b(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_gather4_lz_2d_v4f32_f32_a( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -140,13 +132,11 @@ float4 test_amdgcn_image_gather4_lz_2d_v4f32_f32_a(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_lz_1d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -172,13 +162,11 @@ float4 test_amdgcn_image_sample_lz_1d_v4f32_f32(float4 v4f32, float f32, int i32 // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_l_1d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -205,13 +193,11 @@ float4 test_amdgcn_image_sample_l_1d_v4f32_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_d_1d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -239,13 +225,11 @@ float4 test_amdgcn_image_sample_d_1d_v4f32_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_lz_2d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -272,13 +256,11 @@ float4 test_amdgcn_image_sample_lz_2d_v4f32_f32(float4 v4f32, float f32, int i32 // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_l_2d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -306,13 +288,11 @@ float4 test_amdgcn_image_sample_l_2d_v4f32_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_d_2d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -342,13 +322,11 @@ float4 test_amdgcn_image_sample_d_2d_v4f32_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_lz_3d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -376,13 +354,11 @@ float4 test_amdgcn_image_sample_lz_3d_v4f32_f32(float4 v4f32, float f32, int i32 // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_l_3d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -411,13 +387,11 @@ float4 test_amdgcn_image_sample_l_3d_v4f32_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_d_3d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -451,13 +425,11 @@ float4 test_amdgcn_image_sample_d_3d_v4f32_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_lz_cube_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -485,13 +457,11 @@ float4 test_amdgcn_image_sample_lz_cube_v4f32_f32(float4 v4f32, float f32, int i // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_l_cube_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -520,13 +490,11 @@ float4 test_amdgcn_image_sample_l_cube_v4f32_f32(float4 v4f32, float f32, int i3 // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_lz_1darray_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -553,13 +521,11 @@ float4 test_amdgcn_image_sample_lz_1darray_v4f32_f32(float4 v4f32, float f32, in // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_l_1darray_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -587,13 +553,11 @@ float4 test_amdgcn_image_sample_l_1darray_v4f32_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_d_1darray_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -622,13 +586,11 @@ float4 test_amdgcn_image_sample_d_1darray_v4f32_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_lz_2darray_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -656,13 +618,11 @@ float4 test_amdgcn_image_sample_lz_2darray_v4f32_f32(float4 v4f32, float f32, in // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_l_2darray_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -691,13 +651,11 @@ float4 test_amdgcn_image_sample_l_2darray_v4f32_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x float> @test_amdgcn_image_sample_d_2darray_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -729,13 +687,11 @@ float4 test_amdgcn_image_sample_d_2darray_v4f32_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_lz_1d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -761,13 +717,11 @@ half4 test_amdgcn_image_sample_lz_1d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_l_1d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -794,13 +748,11 @@ half4 test_amdgcn_image_sample_l_1d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_d_1d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -828,13 +780,11 @@ half4 test_amdgcn_image_sample_d_1d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_lz_2d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -861,13 +811,11 @@ half4 test_amdgcn_image_sample_lz_2d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_l_2d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -895,13 +843,11 @@ half4 test_amdgcn_image_sample_l_2d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_d_2d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -932,13 +878,11 @@ half4 test_amdgcn_image_sample_d_2d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_lz_3d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -966,13 +910,11 @@ half4 test_amdgcn_image_sample_lz_3d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_l_3d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1001,13 +943,11 @@ half4 test_amdgcn_image_sample_l_3d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_d_3d_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1041,13 +981,11 @@ half4 test_amdgcn_image_sample_d_3d_v4f16_f32(float4 v4f32, float f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_lz_cube_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1075,13 +1013,11 @@ half4 test_amdgcn_image_sample_lz_cube_v4f16_f32(float4 v4f32, float f32, int i3 // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_l_cube_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1110,13 +1046,11 @@ half4 test_amdgcn_image_sample_l_cube_v4f16_f32(float4 v4f32, float f32, int i32 // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_lz_1darray_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1143,13 +1077,11 @@ half4 test_amdgcn_image_sample_lz_1darray_v4f16_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_l_1darray_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1177,13 +1109,11 @@ half4 test_amdgcn_image_sample_l_1darray_v4f16_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_d_1darray_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1212,13 +1142,11 @@ half4 test_amdgcn_image_sample_d_1darray_v4f16_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_lz_2darray_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1246,13 +1174,11 @@ half4 test_amdgcn_image_sample_lz_2darray_v4f16_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_l_2darray_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1281,13 +1207,11 @@ half4 test_amdgcn_image_sample_l_2darray_v4f16_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local <4 x half> @test_amdgcn_image_sample_d_2darray_v4f16_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1319,13 +1243,11 @@ half4 test_amdgcn_image_sample_d_2darray_v4f16_f32(float4 v4f32, float f32, int // CHECK-LABEL: define dso_local float @test_amdgcn_image_sample_lz_2d_f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1352,13 +1274,11 @@ float test_amdgcn_image_sample_lz_2d_f32_f32(float4 v4f32, float f32, int i32, _ // CHECK-LABEL: define dso_local float @test_amdgcn_image_sample_l_2d_f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1386,13 +1306,11 @@ float test_amdgcn_image_sample_l_2d_f32_f32(float4 v4f32, float f32, int i32, __ // CHECK-LABEL: define dso_local float @test_amdgcn_image_sample_d_2d_f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1423,13 +1341,11 @@ float test_amdgcn_image_sample_d_2d_f32_f32(float4 v4f32, float f32, int i32, __ // CHECK-LABEL: define dso_local float @test_amdgcn_image_sample_lz_2darray_f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1457,13 +1373,11 @@ float test_amdgcn_image_sample_lz_2darray_f32_f32(float4 v4f32, float f32, int i // CHECK-LABEL: define dso_local float @test_amdgcn_image_sample_l_2darray_f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr @@ -1492,13 +1406,11 @@ float test_amdgcn_image_sample_l_2darray_f32_f32(float4 v4f32, float f32, int i3 // CHECK-LABEL: define dso_local float @test_amdgcn_image_sample_d_2darray_f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr diff --git a/clang/test/CodeGen/builtins-image-load.c b/clang/test/CodeGen/builtins-image-load.c index 8442124416338..d2337eab7dbc8 100644 --- a/clang/test/CodeGen/builtins-image-load.c +++ b/clang/test/CodeGen/builtins-image-load.c @@ -9,11 +9,9 @@ typedef half half4 __attribute__((ext_vector_type(4))); // CHECK-LABEL: define dso_local float @test_builtin_image_load_2d( // CHECK-SAME: float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -35,11 +33,9 @@ float test_builtin_image_load_2d(float f32, int i32, __amdgpu_texture_t tex) { // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_2d_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -61,11 +57,9 @@ float4 test_builtin_image_load_2d_1(float4 v4f32, int i32, __amdgpu_texture_t te // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_2d_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -87,11 +81,9 @@ half4 test_builtin_image_load_2d_2(half4 v4f16, int i32, __amdgpu_texture_t tex) // CHECK-LABEL: define dso_local float @test_builtin_image_load_2darray( // CHECK-SAME: float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -114,11 +106,9 @@ float test_builtin_image_load_2darray(float f32, int i32, __amdgpu_texture_t tex // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_2darray_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -141,11 +131,9 @@ float4 test_builtin_image_load_2darray_1(float4 v4f32, int i32, __amdgpu_texture // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_2darray_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -168,11 +156,9 @@ half4 test_builtin_image_load_2darray_2(half4 v4f16, int i32, __amdgpu_texture_t // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_1d_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -193,11 +179,9 @@ float4 test_builtin_image_load_1d_1(float4 v4f32, int i32, __amdgpu_texture_t te // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_1d_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -218,11 +202,9 @@ half4 test_builtin_image_load_1d_2(half4 v4f16, int i32, __amdgpu_texture_t tex) // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_1darray_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -244,11 +226,9 @@ float4 test_builtin_image_load_1darray_1(float4 v4f32, int i32, __amdgpu_texture // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_1darray_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -270,11 +250,9 @@ half4 test_builtin_image_load_1darray_2(half4 v4f16, int i32, __amdgpu_texture_t // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_3d_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -297,11 +275,9 @@ float4 test_builtin_image_load_3d_1(float4 v4f32, int i32, __amdgpu_texture_t te // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_3d_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -324,11 +300,9 @@ half4 test_builtin_image_load_3d_2(half4 v4f16, int i32, __amdgpu_texture_t tex) // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_cube_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -351,11 +325,9 @@ float4 test_builtin_image_load_cube_1(float4 v4f32, int i32, __amdgpu_texture_t // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_cube_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -378,11 +350,9 @@ half4 test_builtin_image_load_cube_2(half4 v4f16, int i32, __amdgpu_texture_t te // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_mip_1d_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -404,11 +374,9 @@ float4 test_builtin_image_load_mip_1d_1(float4 v4f32, int i32, __amdgpu_texture_ // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_mip_1d_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -430,11 +398,9 @@ half4 test_builtin_image_load_mip_1d_2(half4 v4f16, int i32, __amdgpu_texture_t // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_mip_1darray_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -457,11 +423,9 @@ float4 test_builtin_image_load_mip_1darray_1(float4 v4f32, int i32, __amdgpu_tex // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_mip_1darray_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -484,11 +448,9 @@ half4 test_builtin_image_load_mip_1darray_2(half4 v4f16, int i32, __amdgpu_textu // CHECK-LABEL: define dso_local float @test_builtin_image_load_mip_2d( // CHECK-SAME: float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -511,11 +473,9 @@ float test_builtin_image_load_mip_2d(float f32, int i32, __amdgpu_texture_t tex) // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_mip_2d_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -538,11 +498,9 @@ float4 test_builtin_image_load_mip_2d_1(float4 v4f32, int i32, __amdgpu_texture_ // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_mip_2d_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -565,11 +523,9 @@ half4 test_builtin_image_load_mip_2d_2(half4 v4f16, int i32, __amdgpu_texture_t // CHECK-LABEL: define dso_local float @test_builtin_image_load_mip_2darray( // CHECK-SAME: float noundef [[F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -593,11 +549,9 @@ float test_builtin_image_load_mip_2darray(float f32, int i32, __amdgpu_texture_t // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_mip_2darray_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -621,11 +575,9 @@ float4 test_builtin_image_load_mip_2darray_1(float4 v4f32, int i32, __amdgpu_tex // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_mip_2darray_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -649,11 +601,9 @@ half4 test_builtin_image_load_mip_2darray_2(half4 v4f16, int i32, __amdgpu_textu // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_mip_3d_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -677,11 +627,9 @@ float4 test_builtin_image_load_mip_3d_1(float4 v4f32, int i32, __amdgpu_texture_ // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_mip_3d_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -705,11 +653,9 @@ half4 test_builtin_image_load_mip_3d_2(half4 v4f16, int i32, __amdgpu_texture_t // CHECK-LABEL: define dso_local <4 x float> @test_builtin_image_load_mip_cube_1( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -733,11 +679,9 @@ float4 test_builtin_image_load_mip_cube_1(float4 v4f32, int i32, __amdgpu_textur // CHECK-LABEL: define dso_local <4 x half> @test_builtin_image_load_mip_cube_2( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], ptr [[TEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -761,13 +705,11 @@ half4 test_builtin_image_load_mip_cube_2(half4 v4f16, int i32, __amdgpu_texture_ // CHECK-LABEL: define dso_local <4 x float> @test_builtin_amdgcn_image_sample_1d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -792,13 +734,11 @@ float4 test_builtin_amdgcn_image_sample_1d_v4f32_f32(float4 v4f32, int i32, floa // CHECK-LABEL: define dso_local <4 x half> @test_builtin_amdgcn_image_sample_1d_v4f16_f32( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -823,12 +763,10 @@ half4 test_builtin_amdgcn_image_sample_1d_v4f16_f32(half4 v4f16, int i32, float // CHECK-LABEL: define dso_local <4 x float> @test_builtin_amdgcn_image_sample_1darray_v4f32_f32( // CHECK-SAME: i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -852,13 +790,11 @@ float4 test_builtin_amdgcn_image_sample_1darray_v4f32_f32(int i32, float f32, __ // CHECK-LABEL: define dso_local <4 x half> @test_builtin_amdgcn_image_sample_1darray_v4f16_f32( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -884,12 +820,10 @@ half4 test_builtin_amdgcn_image_sample_1darray_v4f16_f32(half4 v4f16, int i32, f // CHECK-LABEL: define dso_local float @test_builtin_amdgcn_image_sample_2d_f32_f32( // CHECK-SAME: i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -913,13 +847,11 @@ float test_builtin_amdgcn_image_sample_2d_f32_f32(int i32, float f32, __amdgpu_t // CHECK-LABEL: define dso_local <4 x float> @test_builtin_amdgcn_image_sample_2d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -945,13 +877,11 @@ float4 test_builtin_amdgcn_image_sample_2d_v4f32_f32(float4 v4f32, int i32, floa // CHECK-LABEL: define dso_local <4 x half> @test_builtin_amdgcn_image_sample_2d_v4f16_f32( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -977,12 +907,10 @@ half4 test_builtin_amdgcn_image_sample_2d_v4f16_f32(half4 v4f16, int i32, float // CHECK-LABEL: define dso_local float @test_builtin_amdgcn_image_sample_2darray_f32_f32( // CHECK-SAME: i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr // CHECK-NEXT: [[TEX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TEX_ADDR]] to ptr @@ -1007,13 +935,11 @@ float test_builtin_amdgcn_image_sample_2darray_f32_f32(int i32, float f32, __amd // CHECK-LABEL: define dso_local <4 x float> @test_builtin_amdgcn_image_sample_2darray_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -1040,13 +966,11 @@ float4 test_builtin_amdgcn_image_sample_2darray_v4f32_f32(float4 v4f32, int i32, // CHECK-LABEL: define dso_local <4 x half> @test_builtin_amdgcn_image_sample_2darray_v4f16_f32( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -1073,13 +997,11 @@ half4 test_builtin_amdgcn_image_sample_2darray_v4f16_f32(half4 v4f16, int i32, f // CHECK-LABEL: define dso_local <4 x float> @test_builtin_amdgcn_image_sample_3d_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -1106,13 +1028,11 @@ float4 test_builtin_amdgcn_image_sample_3d_v4f32_f32(float4 v4f32, int i32, floa // CHECK-LABEL: define dso_local <4 x half> @test_builtin_amdgcn_image_sample_3d_v4f16_f32( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -1139,13 +1059,11 @@ half4 test_builtin_amdgcn_image_sample_3d_v4f16_f32(half4 v4f16, int i32, float // CHECK-LABEL: define dso_local <4 x float> @test_builtin_amdgcn_image_sample_cube_v4f32_f32( // CHECK-SAME: <4 x float> noundef [[V4F32:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[V4F32_ADDR:%.*]] = alloca <4 x float>, align 16, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F32_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr @@ -1172,13 +1090,11 @@ float4 test_builtin_amdgcn_image_sample_cube_v4f32_f32(float4 v4f32, int i32, fl // CHECK-LABEL: define dso_local <4 x half> @test_builtin_amdgcn_image_sample_cube_v4f16_f32( // CHECK-SAME: <4 x half> noundef [[V4F16:%.*]], i32 noundef [[I32:%.*]], float noundef [[F32:%.*]], ptr [[TEX:%.*]], <4 x i32> noundef [[VEC4I32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[V4F16_ADDR:%.*]] = alloca <4 x half>, align 8, addrspace(5) // CHECK-NEXT: [[I32_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[F32_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[TEX_ADDR:%.*]] = alloca ptr, align 32, addrspace(5) // CHECK-NEXT: [[VEC4I32_ADDR:%.*]] = alloca <4 x i32>, align 16, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[V4F16_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V4F16_ADDR]] to ptr // CHECK-NEXT: [[I32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I32_ADDR]] to ptr // CHECK-NEXT: [[F32_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F32_ADDR]] to ptr diff --git a/clang/test/CodeGen/builtins.c b/clang/test/CodeGen/builtins.c index 3545588aec654..0d0104515235c 100644 --- a/clang/test/CodeGen/builtins.c +++ b/clang/test/CodeGen/builtins.c @@ -135,6 +135,7 @@ int main(void) { P(object_size, (s0, 3)); // Whatever + P(bswapg, ((_Bool)N)); P(bswapg, ((char)N)); P(bswapg, ((short)N)); P(bswapg, ((int)N)); diff --git a/clang/test/CodeGen/compound-assign-atomic-bool.c b/clang/test/CodeGen/compound-assign-atomic-bool.c new file mode 100644 index 0000000000000..fd99f09d640ad --- /dev/null +++ b/clang/test/CodeGen/compound-assign-atomic-bool.c @@ -0,0 +1,31 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple riscv64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s + +// When performing compound assignment on atomic_bool, ensure that we +// correctly handle the conversion from integer to boolean, by comparing +// with zero rather than truncating. + +// CHECK-LABEL: @compund_assign_add +int compund_assign_add(void) { + _Atomic _Bool b; + + b += 2; + // CHECK: add + // CHECK: icmp ne + // CHECK-NOT: trunc + // CHECK: {{cmpxchg|call.*__atomic_compare_exchange}} + return b; +} + +// CHECK-LABEL: @compund_assign_minus +int compund_assign_minus(void) { + _Atomic _Bool b; + + b -= 2; + // CHECK: sub + // CHECK: icmp ne + // CHECK-NOT: trunc + // CHECK: {{cmpxchg|call.*__atomic_compare_exchange}} + return b; +} \ No newline at end of file diff --git a/clang/test/CodeGen/denormalfpmode-f32.c b/clang/test/CodeGen/denormalfpmode-f32.c index 312d1c9277722..f80e5539369cd 100644 --- a/clang/test/CodeGen/denormalfpmode-f32.c +++ b/clang/test/CodeGen/denormalfpmode-f32.c @@ -1,48 +1,54 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-NONE -// RUN: %clang_cc1 -fdenormal-fp-math=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-NONE -// RUN: %clang_cc1 -fdenormal-fp-math=preserve-sign %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PS,CHECK-F32-NONE -// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ,CHECK-F32-NONE -// RUN: %clang_cc1 -fdenormal-fp-math=dynamic %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-DYNAMIC,CHECK-F32-NONE +// RUN: %clang_cc1 %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE +// RUN: %clang_cc1 -fdenormal-fp-math=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE +// RUN: %clang_cc1 -fdenormal-fp-math=preserve-sign %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PS +// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ +// RUN: %clang_cc1 -fdenormal-fp-math=dynamic %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-DYNAMIC -// RUN: %clang_cc1 -fdenormal-fp-math-f32=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-NONE -// RUN: %clang_cc1 -fdenormal-fp-math=ieee -fdenormal-fp-math-f32=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-NONE -// RUN: %clang_cc1 -fdenormal-fp-math=preserve-sign -fdenormal-fp-math-f32=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PS,CHECK-F32-IEEE -// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero -fdenormal-fp-math-f32=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ,CHECK-F32-IEEE -// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero -fdenormal-fp-math-f32=dynamic %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ,CHECK-F32-DYNAMIC +// RUN: %clang_cc1 -fdenormal-fp-math-f32=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE +// RUN: %clang_cc1 -fdenormal-fp-math=ieee -fdenormal-fp-math-f32=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE +// RUN: %clang_cc1 -fdenormal-fp-math=preserve-sign -fdenormal-fp-math-f32=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PS-F32-IEEE +// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero -fdenormal-fp-math-f32=ieee %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ-F32-IEEE +// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero -fdenormal-fp-math-f32=dynamic %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ-F32-DYNAMIC // RUN: %clang_cc1 -fdenormal-fp-math-f32=preserve-sign %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-PS // RUN: %clang_cc1 -fdenormal-fp-math=ieee -fdenormal-fp-math-f32=preserve-sign %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-PS -// RUN: %clang_cc1 -fdenormal-fp-math=preserve-sign -fdenormal-fp-math-f32=preserve-sign %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PS,CHECK-F32-NONE -// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero -fdenormal-fp-math-f32=preserve-sign %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ,CHECK-F32-PS +// RUN: %clang_cc1 -fdenormal-fp-math=preserve-sign -fdenormal-fp-math-f32=preserve-sign %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PS +// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero -fdenormal-fp-math-f32=preserve-sign %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ-F32-PS // RUN: %clang_cc1 -fdenormal-fp-math=ieee -fdenormal-fp-math-f32=dynamic %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-DYNAMIC // RUN: %clang_cc1 -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-PZ // RUN: %clang_cc1 -fdenormal-fp-math-f32=dynamic %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-DYNAMIC -// RUN: %clang_cc1 -fdenormal-fp-math=ieee -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-NONE,CHECK-F32-PZ -// RUN: %clang_cc1 -fdenormal-fp-math=dynamic -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-DYNAMIC,CHECK-F32-PZ -// RUN: %clang_cc1 -fdenormal-fp-math=preserve-sign -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PS,CHECK-F32-PZ -// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ,CHECK-F32-NONE -// RUN: %clang_cc1 -fdenormal-fp-math=dynamic -fdenormal-fp-math-f32=dynamic %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-DYNAMIC,CHECK-F32-NONE +// RUN: %clang_cc1 -fdenormal-fp-math=ieee -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-F32-PZ +// RUN: %clang_cc1 -fdenormal-fp-math=dynamic -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-DYNAMIC-F32-PZ +// RUN: %clang_cc1 -fdenormal-fp-math=preserve-sign -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PS-F32-PZ +// RUN: %clang_cc1 -fdenormal-fp-math=positive-zero -fdenormal-fp-math-f32=positive-zero %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-PZ +// RUN: %clang_cc1 -fdenormal-fp-math=dynamic -fdenormal-fp-math-f32=dynamic %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK-ATTR,CHECK-DYNAMIC // CHECK-LABEL: main // CHECK-ATTR: attributes #0 = -// CHECK-NONE-NOT:"denormal-fp-math" -// CHECK-IEEE: "denormal-fp-math"="ieee,ieee" -// CHECK-PS: "denormal-fp-math"="preserve-sign,preserve-sign" -// CHECK-PZ: "denormal-fp-math"="positive-zero,positive-zero" -// CHECK-DYNAMIC: "denormal-fp-math"="dynamic,dynamic" +// CHECK-NONE-NOT: denormal_fpenv -// CHECK-F32-NONE-NOT:"denormal-fp-math-f32" -// CHECK-F32-IEEE: "denormal-fp-math-f32"="ieee,ieee" -// CHECK-F32-PS: "denormal-fp-math-f32"="preserve-sign,preserve-sign" -// CHECK-F32-PZ: "denormal-fp-math-f32"="positive-zero,positive-zero" +// CHECK-IEEE: denormal_fpenv(ieee) +// CHECK-PS: denormal_fpenv(preservesign) +// CHECK-PZ: denormal_fpenv(positivezero) +// CHECK-DYNAMIC: denormal_fpenv(dynamic) -// CHECK-F32-DYNAMIC: "denormal-fp-math-f32"="dynamic,dynamic" +// CHECK-PS-F32-IEEE: denormal_fpenv(preservesign, float: ieee) +// CHECK-PZ-F32-IEEE: denormal_fpenv(positivezero, float: ieee) +// CHECK-PZ-F32-DYNAMIC: denormal_fpenv(positivezero, float: dynamic) +// CHECK-PZ-F32-PS: denormal_fpenv(positivezero, float: preservesign) +// CHECK-DYNAMIC-F32-PZ: denormal_fpenv(dynamic, float: positivezero) +// CHECK: CHECK-PS-F32-PZ: denormal_fpenv(preservesign, float: positivezero) + +// CHECK-F32-IEEE: denormal_fpenv(float: ieee) +// CHECK-F32-PS: denormal_fpenv(float: preservesign) +// CHECK-F32-PZ: denormal_fpenv(float: positivezero) +// CHECK-F32-DYNAMIC: denormal_fpenv(float: dynamic) int main(void) { return 0; diff --git a/clang/test/CodeGen/denormalfpmode.c b/clang/test/CodeGen/denormalfpmode.c index cffff90d6fbe7..f475a1186392b 100644 --- a/clang/test/CodeGen/denormalfpmode.c +++ b/clang/test/CodeGen/denormalfpmode.c @@ -6,10 +6,10 @@ // CHECK-LABEL: main // The ieee,ieee is the default, so omit the attribute -// CHECK-IEEE-NOT:"denormal-fp-math" -// CHECK-PS: attributes #0 = {{.*}}"denormal-fp-math"="preserve-sign,preserve-sign"{{.*}} -// CHECK-PZ: attributes #0 = {{.*}}"denormal-fp-math"="positive-zero,positive-zero"{{.*}} -// CHECK-DYNAMIC: attributes #0 = {{.*}}"denormal-fp-math"="dynamic,dynamic"{{.*}} +// CHECK-IEEE-NOT:denormal_fpenv +// CHECK-PS: attributes #0 = {{.*}}denormal_fpenv(preservesign){{.*}} +// CHECK-PZ: attributes #0 = {{.*}}denormal_fpenv(positivezero){{.*}} +// CHECK-DYNAMIC: attributes #0 = {{.*}}denormal_fpenv(dynamic){{.*}} int main(void) { return 0; diff --git a/clang/test/CodeGen/fp-function-attrs.cpp b/clang/test/CodeGen/fp-function-attrs.cpp index 3775bd5452d78..dc1ca7ef00ea9 100644 --- a/clang/test/CodeGen/fp-function-attrs.cpp +++ b/clang/test/CodeGen/fp-function-attrs.cpp @@ -53,5 +53,5 @@ float test_contract_on_pragma(float a, float b, float c) { // CHECK: fmul fast float {{%.+}}, {{%.+}} // CHECK: fadd reassoc nnan ninf nsz arcp afn float {{%.+}}, {{%.+}} -// CHECK: attributes [[FAST_ATTRS]] = { {{.*}}"no-infs-fp-math"="true" {{.*}}"no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true"{{.*}} } -// CHECK: attributes [[PRECISE_ATTRS]] = { {{.*}}"no-infs-fp-math"="false" {{.*}}"no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false"{{.*}} } +// CHECK: attributes [[FAST_ATTRS]] = { {{.*}}"no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true"{{.*}} } +// CHECK: attributes [[PRECISE_ATTRS]] = { {{.*}}"no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false"{{.*}} } diff --git a/clang/test/CodeGen/ifunc.c b/clang/test/CodeGen/ifunc.c index 7d21f742e8676..c346f81947cde 100644 --- a/clang/test/CodeGen/ifunc.c +++ b/clang/test/CodeGen/ifunc.c @@ -16,6 +16,8 @@ // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -O2 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -fsanitize=thread -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=SAN // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -fsanitize=address -O2 -emit-llvm -o - %s | FileCheck %s --check-prefix=SAN +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -O2 -emit-llvm -o - %s | FileCheck %s /// The ifunc is emitted before its resolver. @@ -65,7 +67,7 @@ extern void hoo(int) __attribute__ ((ifunc("hoo_ifunc"))); // AVR: @goo = ifunc void (), ptr addrspace(1) @goo_ifunc // AVR: @hoo = ifunc void (i16), ptr addrspace(1) @hoo_ifunc -// CHECK: call i32 @foo(i32 +// CHECK: call {{(signext )?}}i32 @foo(i32 // CHECK: call void @goo() // SAN: define {{(dso_local )?}}noalias {{(noundef )?}}ptr @goo_ifunc() #[[#GOO_IFUNC:]] { diff --git a/clang/test/CodeGen/paren-list-agg-init.cpp b/clang/test/CodeGen/paren-list-agg-init.cpp index e30777ecc07d6..772e472057ed6 100644 --- a/clang/test/CodeGen/paren-list-agg-init.cpp +++ b/clang/test/CodeGen/paren-list-agg-init.cpp @@ -394,7 +394,7 @@ namespace gh61145 { // a.k.a. Vec::Vec(Vec&&) // CHECK-NEXT: call void @_ZN7gh611453VecC1EOS0_(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP_ENSURED]], ptr noundef nonnull align 1 dereferenceable(1) [[V]]) // a.k.a. S1::~S1() - // CHECK-NEXT: call void @_ZN7gh611452S1D1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[AGG_TMP_ENSURED]]) + // CHECK-NEXT: call void @_ZN7gh611452S1D1Ev(ptr noundef nonnull align 1 dead_on_return(1) dereferenceable(1) [[AGG_TMP_ENSURED]]) // a.k.a.Vec::~Vec() // CHECK-NEXT: call void @_ZN7gh611453VecD1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[V]]) // CHECK-NEXT: ret void @@ -416,7 +416,7 @@ namespace gh61145 { // CHECK-NEXT: [[C:%.*c.*]] = getelementptr inbounds nuw [[STRUCT_S2]], ptr [[AGG_TMP_ENSURED]], i32 0, i32 // CHECK-NEXT: store i8 0, ptr [[C]], align 1 // a.k.a. S2::~S2() - // CHECK-NEXT: call void @_ZN7gh611452S2D1Ev(ptr noundef nonnull align 1 dereferenceable(2) [[AGG_TMP_ENSURED]]) + // CHECK-NEXT: call void @_ZN7gh611452S2D1Ev(ptr noundef nonnull align 1 dead_on_return(2) dereferenceable(2) [[AGG_TMP_ENSURED]]) // a.k.a. Vec::~Vec() // CHECK-NEXT: call void @_ZN7gh611453VecD1Ev(ptr noundef nonnull align 1 dereferenceable(1) [[V]]) // CHECK-NEXT: ret void diff --git a/clang/test/CodeGen/ptrauth-intrinsics.c b/clang/test/CodeGen/ptrauth-intrinsics.c index 50bf1898e4b37..bd348f9b3551a 100644 --- a/clang/test/CodeGen/ptrauth-intrinsics.c +++ b/clang/test/CodeGen/ptrauth-intrinsics.c @@ -55,6 +55,18 @@ void test_auth_and_resign() { fnptr = __builtin_ptrauth_auth_and_resign(fnptr, 0, ptr_discriminator, 3, 15); } +// CHECK-LABEL: define {{.*}}void @test_auth_load_relative_and_sign() +void test_auth_load_relative_and_sign() { + // CHECK: [[PTR:%.*]] = load ptr, ptr @fnptr, + // CHECK-NEXT: [[DISC0:%.*]] = load ptr, ptr @ptr_discriminator, + // CHECK-NEXT: [[T0:%.*]] = ptrtoint ptr [[PTR]] to i64 + // CHECK-NEXT: [[DISC:%.*]] = ptrtoint ptr [[DISC0]] to i64 + // CHECK-NEXT: [[T1:%.*]] = call i64 @llvm.ptrauth.resign.load.relative(i64 [[T0]], i32 0, i64 [[DISC]], i32 3, i64 15, i64 16) + // CHECK-NEXT: [[RESULT:%.*]] = inttoptr i64 [[T1]] to ptr + // CHECK-NEXT: store ptr [[RESULT]], ptr @fnptr, + fnptr = __builtin_ptrauth_auth_load_relative_and_sign(fnptr, 0, ptr_discriminator, 3, 15, 16L); +} + // CHECK-LABEL: define {{.*}}void @test_blend_discriminator() void test_blend_discriminator() { // CHECK: [[PTR:%.*]] = load ptr, ptr @fnptr, diff --git a/clang/test/CodeGen/riscv-be-data-layout.c b/clang/test/CodeGen/riscv-be-data-layout.c new file mode 100644 index 0000000000000..9f88464da7587 --- /dev/null +++ b/clang/test/CodeGen/riscv-be-data-layout.c @@ -0,0 +1,12 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64be-unknown-elf -emit-llvm %s -o - \ +// RUN: | FileCheck %s --check-prefix=RV64 +// RUN: %clang_cc1 -triple riscv32be-unknown-elf -emit-llvm %s -o - \ +// RUN: | FileCheck %s --check-prefix=RV32 + +// RV64: target datalayout = "E-m:e-p:64:64-i64:64-i128:128-n32:64-S128" +// RV32: target datalayout = "E-m:e-p:32:32-i64:64-n32-S128" + +int foo(void) { + return 0; +} diff --git a/clang/test/CodeGen/scoped-atomic-ops.c b/clang/test/CodeGen/scoped-atomic-ops.c index 1385081578d2e..3fbaf75cf98e6 100644 --- a/clang/test/CodeGen/scoped-atomic-ops.c +++ b/clang/test/CodeGen/scoped-atomic-ops.c @@ -9,10 +9,8 @@ // AMDGCN_CL_DEF-LABEL: define hidden i32 @fi1a( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0:[0-9]+]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[V:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[V_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[V]] to ptr // AMDGCN_CL_DEF-NEXT: store ptr [[I]], ptr [[I_ADDR_ASCAST]], align 8 @@ -40,10 +38,8 @@ // AMDGCN_CL_20-LABEL: define hidden i32 @fi1a( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0:[0-9]+]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[V:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[I]], ptr [[I_ADDR_ASCAST]], align 8 // AMDGCN_CL_20-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR_ASCAST]], align 8 @@ -108,7 +104,6 @@ int fi1a(int *i) { // AMDGCN-LABEL: define hidden i32 @fi1b( // AMDGCN-SAME: ptr noundef [[I:%.*]]) #[[ATTR0:[0-9]+]] { // AMDGCN-NEXT: [[ENTRY:.*:]] -// AMDGCN-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca i32, align 4, addrspace(5) @@ -116,7 +111,6 @@ int fi1a(int *i) { // AMDGCN-NEXT: [[ATOMIC_TEMP3:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN-NEXT: [[ATOMIC_TEMP4:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN-NEXT: [[ATOMIC_TEMP5:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr // AMDGCN-NEXT: [[ATOMIC_TEMP1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP1]] to ptr @@ -2591,12 +2585,10 @@ void fi3e(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi4a( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DESIRED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DESIRED]] to ptr @@ -2624,12 +2616,10 @@ void fi3e(int *a, int *b, int *c, int *d, int *e, int *f, int *g, int *h) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi4a( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[I]], ptr [[I_ADDR_ASCAST]], align 8 @@ -2691,12 +2681,10 @@ _Bool fi4a(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi4b( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DESIRED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DESIRED]] to ptr @@ -2724,12 +2712,10 @@ _Bool fi4a(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi4b( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[I]], ptr [[I_ADDR_ASCAST]], align 8 @@ -2791,12 +2777,10 @@ _Bool fi4b(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi4c( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DESIRED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DESIRED]] to ptr @@ -2824,12 +2808,10 @@ _Bool fi4b(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi4c( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[I]], ptr [[I_ADDR_ASCAST]], align 8 @@ -2891,12 +2873,10 @@ _Bool fi4c(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi4_clustr( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DESIRED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DESIRED]] to ptr @@ -2924,12 +2904,10 @@ _Bool fi4c(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi4_clustr( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[I]], ptr [[I_ADDR_ASCAST]], align 8 @@ -2991,12 +2969,10 @@ _Bool fi4_clustr(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi4d( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DESIRED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DESIRED]] to ptr @@ -3024,12 +3000,10 @@ _Bool fi4_clustr(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi4d( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[I]], ptr [[I_ADDR_ASCAST]], align 8 @@ -3091,12 +3065,10 @@ _Bool fi4d(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi4e( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DESIRED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DESIRED]] to ptr @@ -3124,12 +3096,10 @@ _Bool fi4d(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi4e( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DESIRED:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[I]], ptr [[I_ADDR_ASCAST]], align 8 @@ -3191,12 +3161,10 @@ _Bool fi4e(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi5a( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr @@ -3224,12 +3192,10 @@ _Bool fi4e(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi5a( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr @@ -3290,12 +3256,10 @@ _Bool fi5a(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi5b( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr @@ -3323,12 +3287,10 @@ _Bool fi5a(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi5b( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr @@ -3389,12 +3351,10 @@ _Bool fi5b(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi5c( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr @@ -3422,12 +3382,10 @@ _Bool fi5b(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi5c( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr @@ -3487,12 +3445,10 @@ _Bool fi5c(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi5_clustr( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr @@ -3520,12 +3476,10 @@ _Bool fi5c(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi5_clustr( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr @@ -3585,12 +3539,10 @@ _Bool fi5_clustr(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi5d( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr @@ -3618,12 +3570,10 @@ _Bool fi5_clustr(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi5d( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr @@ -3683,12 +3633,10 @@ _Bool fi5d(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi5e( // AMDGCN_CL_DEF-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[CMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr @@ -3716,12 +3664,10 @@ _Bool fi5d(int *i) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi5e( // AMDGCN_CL_20-SAME: ptr noundef [[I:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[I_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[I_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[CMPXCHG_BOOL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CMPXCHG_BOOL]] to ptr @@ -3781,11 +3727,9 @@ _Bool fi5e(int *i) { // AMDGCN_CL_DEF-LABEL: define hidden i32 @fi6a( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[RET_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RET]] to ptr @@ -3802,11 +3746,9 @@ _Bool fi5e(int *i) { // AMDGCN_CL_20-LABEL: define hidden i32 @fi6a( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 @@ -3845,11 +3787,9 @@ int fi6a(int *c, int *d) { // AMDGCN_CL_DEF-LABEL: define hidden i32 @fi6b( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[RET_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RET]] to ptr @@ -3866,11 +3806,9 @@ int fi6a(int *c, int *d) { // AMDGCN_CL_20-LABEL: define hidden i32 @fi6b( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 @@ -3909,11 +3847,9 @@ int fi6b(int *c, int *d) { // AMDGCN_CL_DEF-LABEL: define hidden i32 @fi6c( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[RET_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RET]] to ptr @@ -3930,11 +3866,9 @@ int fi6b(int *c, int *d) { // AMDGCN_CL_20-LABEL: define hidden i32 @fi6c( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 @@ -3973,11 +3907,9 @@ int fi6c(int *c, int *d) { // AMDGCN_CL_DEF-LABEL: define hidden i32 @fi6_clustr( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[RET_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RET]] to ptr @@ -3994,11 +3926,9 @@ int fi6c(int *c, int *d) { // AMDGCN_CL_20-LABEL: define hidden i32 @fi6_clustr( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 @@ -4037,11 +3967,9 @@ int fi6_clustr(int *c, int *d) { // AMDGCN_CL_DEF-LABEL: define hidden i32 @fi6d( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[RET_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RET]] to ptr @@ -4058,11 +3986,9 @@ int fi6_clustr(int *c, int *d) { // AMDGCN_CL_20-LABEL: define hidden i32 @fi6d( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 @@ -4101,11 +4027,9 @@ int fi6d(int *c, int *d) { // AMDGCN_CL_DEF-LABEL: define hidden i32 @fi6e( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[RET_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RET]] to ptr @@ -4122,11 +4046,9 @@ int fi6d(int *c, int *d) { // AMDGCN_CL_20-LABEL: define hidden i32 @fi6e( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[RET:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[D_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[D_ADDR]] to ptr // AMDGCN_CL_20-NEXT: store ptr [[C]], ptr [[C_ADDR_ASCAST]], align 8 @@ -4165,11 +4087,9 @@ int fi6e(int *c, int *d) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi7a( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4186,11 +4106,9 @@ int fi6e(int *c, int *d) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi7a( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4228,11 +4146,9 @@ _Bool fi7a(_Bool *c) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi7b( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4249,11 +4165,9 @@ _Bool fi7a(_Bool *c) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi7b( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4291,11 +4205,9 @@ _Bool fi7b(_Bool *c) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi7c( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4312,11 +4224,9 @@ _Bool fi7b(_Bool *c) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi7c( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4354,11 +4264,9 @@ _Bool fi7c(_Bool *c) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi7_clustr( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4375,11 +4283,9 @@ _Bool fi7c(_Bool *c) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi7_clustr( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4417,11 +4323,9 @@ _Bool fi7_clustr(_Bool *c) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi7d( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4438,11 +4342,9 @@ _Bool fi7_clustr(_Bool *c) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi7d( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4480,11 +4382,9 @@ _Bool fi7d(_Bool *c) { // AMDGCN_CL_DEF-LABEL: define hidden zeroext i1 @fi7e( // AMDGCN_CL_DEF-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_DEF-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_DEF-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_DEF-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_DEF-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_DEF-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_DEF-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr @@ -4501,11 +4401,9 @@ _Bool fi7d(_Bool *c) { // AMDGCN_CL_20-LABEL: define hidden zeroext i1 @fi7e( // AMDGCN_CL_20-SAME: ptr noundef [[C:%.*]]) #[[ATTR0]] { // AMDGCN_CL_20-NEXT: [[ENTRY:.*:]] -// AMDGCN_CL_20-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP:%.*]] = alloca i8, align 1, addrspace(5) // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGCN_CL_20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN_CL_20-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr // AMDGCN_CL_20-NEXT: [[DOTATOMICTMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTATOMICTMP]] to ptr // AMDGCN_CL_20-NEXT: [[ATOMIC_TEMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ATOMIC_TEMP]] to ptr diff --git a/clang/test/CodeGen/target-addrspace.cpp b/clang/test/CodeGen/target-addrspace.cpp index 9adf53611bc24..c8e65bd9e6796 100644 --- a/clang/test/CodeGen/target-addrspace.cpp +++ b/clang/test/CodeGen/target-addrspace.cpp @@ -53,9 +53,7 @@ void p1(void [[clang::address_space(0)]] * p) { f(p); } // AMDGPU-LABEL: define hidden noundef ptr @_Z2p2PU3AS3v( // AMDGPU-SAME: ptr addrspace(3) noundef [[P:%.*]]) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGPU-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(3), align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr // AMDGPU-NEXT: store ptr addrspace(3) [[P]], ptr [[P_ADDR_ASCAST]], align 4 // AMDGPU-NEXT: [[TMP0:%.*]] = load ptr addrspace(3), ptr [[P_ADDR_ASCAST]], align 4 @@ -75,9 +73,7 @@ void *p2(void [[clang::address_space(3)]] * p) { return p; } // AMDGPU-LABEL: define hidden noundef ptr @_Z2p3PU3AS3v( // AMDGPU-SAME: ptr addrspace(3) noundef [[P:%.*]]) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5) // AMDGPU-NEXT: [[P_ADDR:%.*]] = alloca ptr addrspace(3), align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr // AMDGPU-NEXT: store ptr addrspace(3) [[P]], ptr [[P_ADDR_ASCAST]], align 4 // AMDGPU-NEXT: [[TMP0:%.*]] = load ptr addrspace(3), ptr [[P_ADDR_ASCAST]], align 4 diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c index 47d5ae51d643a..a65a07d81b8c0 100644 --- a/clang/test/CodeGen/target-builtin-noerror.c +++ b/clang/test/CodeGen/target-builtin-noerror.c @@ -209,5 +209,6 @@ void verifycpustrings(void) { (void)__builtin_cpu_is("znver3"); (void)__builtin_cpu_is("znver4"); (void)__builtin_cpu_is("znver5"); + (void)__builtin_cpu_is("znver6"); (void)__builtin_cpu_is("diamondrapids"); } diff --git a/clang/test/CodeGen/ubsan-function-sugared.cpp b/clang/test/CodeGen/ubsan-function-sugared.cpp index fb2487c024ba9..7eb37ca50c366 100644 --- a/clang/test/CodeGen/ubsan-function-sugared.cpp +++ b/clang/test/CodeGen/ubsan-function-sugared.cpp @@ -10,9 +10,9 @@ auto fun() {} // GNU-LABEL: define{{.*}} void @_Z6callerv() // MSVC-LABEL: define{{.*}} void @"?caller@@YAXXZ"() -// ARM: ptrtoint ptr {{.*}} to i32, !nosanitize !4 -// ARM: and i32 {{.*}}, -2, !nosanitize !4 -// ARM: inttoptr i32 {{.*}} to ptr, !nosanitize !4 +// ARM: ptrtoint ptr {{.*}} to i32, !nosanitize !6 +// ARM: and i32 {{.*}}, -2, !nosanitize !6 +// ARM: inttoptr i32 {{.*}} to ptr, !nosanitize !6 // CHECK: getelementptr <{ i32, i32 }>, ptr {{.*}}, i32 -1, i32 0, !nosanitize // CHECK: load i32, ptr {{.*}}, align {{.*}}, !nosanitize // CHECK: icmp eq i32 {{.*}}, -1056584962, !nosanitize diff --git a/clang/test/CodeGen/ubsan-function.cpp b/clang/test/CodeGen/ubsan-function.cpp index bc43942635a7b..59f8d84d8c877 100644 --- a/clang/test/CodeGen/ubsan-function.cpp +++ b/clang/test/CodeGen/ubsan-function.cpp @@ -13,9 +13,9 @@ void fun() {} // GNU-LABEL: define{{.*}} void @_Z6callerPFvvE(ptr noundef %f) // MSVC-LABEL: define{{.*}} void @"?caller@@YAXP6AXXZ@Z"(ptr noundef %f) -// ARM: ptrtoint ptr {{.*}} to i32, !nosanitize !5 -// ARM: and i32 {{.*}}, -2, !nosanitize !5 -// ARM: inttoptr i32 {{.*}} to ptr, !nosanitize !5 +// ARM: ptrtoint ptr {{.*}} to i32, !nosanitize !7 +// ARM: and i32 {{.*}}, -2, !nosanitize !7 +// ARM: inttoptr i32 {{.*}} to ptr, !nosanitize !7 // AUTH: %[[STRIPPED:.*]] = ptrtoint ptr {{.*}} to i64, !nosanitize // AUTH: call i64 @llvm.ptrauth.auth(i64 %[[STRIPPED]], i32 0, i64 0), !nosanitize // CHECK: getelementptr <{ i32, i32 }>, ptr {{.*}}, i32 -1, i32 0, !nosanitize diff --git a/clang/test/CodeGenCUDA/amdgpu-bf16.cu b/clang/test/CodeGenCUDA/amdgpu-bf16.cu index f9b067d3fe0d3..d146eb6dd9516 100644 --- a/clang/test/CodeGenCUDA/amdgpu-bf16.cu +++ b/clang/test/CodeGenCUDA/amdgpu-bf16.cu @@ -54,9 +54,7 @@ __device__ void test_load(__bf16 *out, __bf16 *in) { // CHECK-LABEL: @_Z8test_retDF16b( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca bfloat, align 2, addrspace(5) // CHECK-NEXT: [[IN_ADDR:%.*]] = alloca bfloat, align 2, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[IN_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[IN_ADDR]] to ptr // CHECK-NEXT: store bfloat [[IN:%.*]], ptr [[IN_ADDR_ASCAST]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load bfloat, ptr [[IN_ADDR_ASCAST]], align 2 @@ -68,9 +66,7 @@ __device__ __bf16 test_ret( __bf16 in) { // CHECK-LABEL: @_Z9test_callDF16b( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca bfloat, align 2, addrspace(5) // CHECK-NEXT: [[IN_ADDR:%.*]] = alloca bfloat, align 2, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[IN_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[IN_ADDR]] to ptr // CHECK-NEXT: store bfloat [[IN:%.*]], ptr [[IN_ADDR_ASCAST]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load bfloat, ptr [[IN_ADDR_ASCAST]], align 2 diff --git a/clang/test/CodeGenCUDA/flush-denormals.cu b/clang/test/CodeGenCUDA/flush-denormals.cu index b5abc29dea14b..c6a4046fdc965 100644 --- a/clang/test/CodeGenCUDA/flush-denormals.cu +++ b/clang/test/CodeGenCUDA/flush-denormals.cu @@ -24,7 +24,7 @@ #include "Inputs/cuda.h" -// Checks that device function calls get emitted with the "denormal-fp-math-f32" +// Checks that device function calls get emitted with the denormal_fpenv // attribute set when we compile CUDA device code with // -fdenormal-fp-math-f32. Further, check that we reflect the presence or // absence of -fgpu-flush-denormals-to-zero in a module flag. @@ -41,8 +41,8 @@ // CHECK-LABEL: define void @foo() #0 extern "C" __device__ void foo() {} -// FTZ: attributes #0 = {{.*}} "denormal-fp-math-f32"="preserve-sign,preserve-sign" -// NOFTZ-NOT: "denormal-fp-math-f32" +// FTZ: attributes #0 = {{.*}} denormal_fpenv(float: preservesign) +// NOFTZ-NOT: denormal_fpenv // PTXFTZ:!llvm.module.flags = !{{{.*}}[[MODFLAG:![0-9]+]]} // PTXFTZ:[[MODFLAG]] = !{i32 4, !"nvvm-reflect-ftz", i32 1} diff --git a/clang/test/CodeGenCUDA/link-builtin-bitcode-denormal-fp-mode.cu b/clang/test/CodeGenCUDA/link-builtin-bitcode-denormal-fp-mode.cu index ef02668c3697b..df72d3a1a3b9b 100644 --- a/clang/test/CodeGenCUDA/link-builtin-bitcode-denormal-fp-mode.cu +++ b/clang/test/CodeGenCUDA/link-builtin-bitcode-denormal-fp-mode.cu @@ -127,39 +127,39 @@ __global__ void kernel_f64(double* out, double* a, double* b, double* c) { // We should not be littering call sites with the attribute // Everything should use the default ieee with no explicit attribute -// FIXME: Should check-not "denormal-fp-math" within the denormal-fp-math-f32 +// FIXME: Should check-not denormal_fpenv within the denormal-fp-math-f32 // lines. // Default mode relies on the implicit check-not for the denormal-fp-math. -// PSZ: #[[$KERNELATTR]] = { {{.*}} "denormal-fp-math"="preserve-sign,preserve-sign" +// PSZ: #[[$KERNELATTR]] = { {{.*}} denormal_fpenv(preservesign) // PSZ-SAME: "target-cpu"="gfx803" -// PSZ: #[[$FUNCATTR]] = { {{.*}} "denormal-fp-math-f32"="preserve-sign,preserve-sign" +// PSZ: #[[$FUNCATTR]] = { {{.*}} denormal_fpenv(float: preservesign) // PSZ-SAME: "target-cpu"="gfx803" -// PSZ: #[[$WEAK_FUNCATTR]] = { {{.*}} "denormal-fp-math-f32"="preserve-sign,preserve-sign" +// PSZ: #[[$WEAK_FUNCATTR]] = { {{.*}} denormal_fpenv(float: preservesign) // PSZ-SAME: "target-cpu"="gfx803" -// FIXME: Should check-not "denormal-fp-math" within the line -// IEEEF64-PSZF32: #[[$KERNELATTR]] = { {{.*}} "denormal-fp-math-f32"="preserve-sign,preserve-sign" +// FIXME: Should check-not denormal_fpenv within the line +// IEEEF64-PSZF32: #[[$KERNELATTR]] = { {{.*}} denormal_fpenv(float: preservesign) // IEEEF64-PSZF32-SAME: "target-cpu"="gfx803" -// IEEEF64-PSZF32: #[[$FUNCATTR]] = { {{.*}} "denormal-fp-math-f32"="preserve-sign,preserve-sign" +// IEEEF64-PSZF32: #[[$FUNCATTR]] = { {{.*}} denormal_fpenv(float: preservesign) // IEEEF64-PSZF32-SAME: "target-cpu"="gfx803" -// IEEEF64-PSZF32: #[[$WEAK_FUNCATTR]] = { {{.*}} "denormal-fp-math-f32"="preserve-sign,preserve-sign" +// IEEEF64-PSZF32: #[[$WEAK_FUNCATTR]] = { {{.*}} denormal_fpenv(float: preservesign) // IEEEF64-PSZF32-SAME: "target-cpu"="gfx803" -// IEEEF32-PSZF64-DYNF32: #[[$KERNELATTR]] = { {{.*}} "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" {{.*}} "target-cpu"="gfx803" {{.*}} } -// implicit check-not +// IEEEF32-PSZF64-DYNF32: #[[$KERNELATTR]] = { {{.*}} denormal_fpenv(preservesign, float: ieee) {{.*}} "target-cpu"="gfx803" {{.*}} } +// implicit-not // implicit check-not -// IEEEF32-PSZF64-DYNFULL: #[[$KERNELATTR]] = { {{.*}} "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" +// IEEEF32-PSZF64-DYNFULL: #[[$KERNELATTR]] = { {{.*}} denormal_fpenv(preservesign, float: ieee) // IEEEF32-PSZF64-DYNFULL-SAME: "target-cpu"="gfx803" -// IEEEF32-PSZF64-DYNFULL: #[[$FUNCATTR]] = { {{.*}} "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" +// IEEEF32-PSZF64-DYNFULL: #[[$FUNCATTR]] = { {{.*}} denormal_fpenv(preservesign, float: ieee) // IEEEF32-PSZF64-DYNFULL-SAME: "target-cpu"="gfx803" -// IEEEF32-PSZF64-DYNFULL: #[[$WEAK_FUNCATTR]] = { {{.*}} "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" +// IEEEF32-PSZF64-DYNFULL: #[[$WEAK_FUNCATTR]] = { {{.*}} denormal_fpenv(preservesign, float: ieee) // IEEEF32-PSZF64-DYNFULL-SAME: "target-cpu"="gfx803" // -mlink-bitcode-file doesn't internalize or propagate attributes. -// NOINTERNALIZE-IEEEF32-PSZF64-DYNFULL: #[[$KERNELATTR]] = { {{.*}} "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" {{.*}} "target-cpu"="gfx803" {{.*}} } -// NOINTERNALIZE-IEEEF32-PSZF64-DYNFULL: #[[$FUNCATTR]] = { {{.*}} "denormal-fp-math"="dynamic,dynamic" {{.*}} } -// NOINTERNALIZE-IEEEF32-PSZF64-DYNFULL: #[[$WEAK_FUNCATTR]] = { {{.*}} "denormal-fp-math"="dynamic,dynamic" {{.*}} } +// NOINTERNALIZE-IEEEF32-PSZF64-DYNFULL: #[[$KERNELATTR]] = { {{.*}} denormal_fpenv(preservesign, float: ieee) {{.*}} "target-cpu"="gfx803" {{.*}} } +// NOINTERNALIZE-IEEEF32-PSZF64-DYNFULL: #[[$FUNCATTR]] = { {{.*}} denormal_fpenv(dynamic) {{.*}} } +// NOINTERNALIZE-IEEEF32-PSZF64-DYNFULL: #[[$WEAK_FUNCATTR]] = { {{.*}} denormal_fpenv(dynamic) {{.*}} } diff --git a/clang/test/CodeGenCUDA/propagate-attributes.cu b/clang/test/CodeGenCUDA/propagate-attributes.cu index a7e6b09ff97db..2d5a250974fb8 100644 --- a/clang/test/CodeGenCUDA/propagate-attributes.cu +++ b/clang/test/CodeGenCUDA/propagate-attributes.cu @@ -53,14 +53,14 @@ __global__ void kernel() { lib_fn(); } // line. // Check the attribute list for kernel. +// NOFTZ-NOT: denormal_fpenv + // CHECK: attributes [[kattr]] = { // CHECK-SAME: convergent // CHECK-SAME: norecurse -// FTZ-NOT: "denormal-fp-math" -// FTZ-SAME: "denormal-fp-math-f32"="preserve-sign,preserve-sign" -// NOFTZ-NOT: "denormal-fp-math-f32" +// FTZ-SAME: denormal_fpenv(float: preservesign) // CHECK-SAME: "no-trapping-math"="true" @@ -70,10 +70,4 @@ __global__ void kernel() { lib_fn(); } // CHECK-SAME: convergent // CHECK-NOT: norecurse -// FTZ-NOT: "denormal-fp-math" -// NOFTZ-NOT: "denormal-fp-math" - -// FTZ-SAME: "denormal-fp-math-f32"="preserve-sign,preserve-sign" -// NOFTZ-NOT: "denormal-fp-math-f32" - // CHECK-SAME: "no-trapping-math"="true" diff --git a/clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu b/clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu index 2a0f84d1daa75..caa5ed1783494 100644 --- a/clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu +++ b/clang/test/CodeGenCUDA/spirv-amdgcn-bf16.cu @@ -54,9 +54,7 @@ __device__ void test_load(__bf16 *out, __bf16 *in) { // CHECK-LABEL: @_Z8test_retDF16b( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca bfloat, align 2 // CHECK-NEXT: [[IN_ADDR:%.*]] = alloca bfloat, align 2 -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) // CHECK-NEXT: [[IN_ADDR_ASCAST:%.*]] = addrspacecast ptr [[IN_ADDR]] to ptr addrspace(4) // CHECK-NEXT: store bfloat [[IN:%.*]], ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load bfloat, ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 @@ -68,9 +66,7 @@ __device__ __bf16 test_ret( __bf16 in) { // CHECK-LABEL: @_Z9test_callDF16b( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca bfloat, align 2 // CHECK-NEXT: [[IN_ADDR:%.*]] = alloca bfloat, align 2 -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) // CHECK-NEXT: [[IN_ADDR_ASCAST:%.*]] = addrspacecast ptr [[IN_ADDR]] to ptr addrspace(4) // CHECK-NEXT: store bfloat [[IN:%.*]], ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load bfloat, ptr addrspace(4) [[IN_ADDR_ASCAST]], align 2 diff --git a/clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp b/clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp index 3c2a624bd4f95..9236c7d8137ab 100644 --- a/clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp +++ b/clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp @@ -75,7 +75,7 @@ int x; // CHECK-NEXT: [[A:%.*]] = alloca [[CLASS_A:%.*]], align 4, addrspace(5) // CHECK-NEXT: [[A_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A]] to ptr // CHECK-NEXT: call void @_ZN1AC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[A_ASCAST]]) -// CHECK-NEXT: call void @_ZN1AD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[A_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[A_ASCAST]]) // CHECK-NEXT: ret void // void func3() { diff --git a/clang/test/CodeGenCXX/amdgcn-func-arg.cpp b/clang/test/CodeGenCXX/amdgcn-func-arg.cpp index a5f83dc91b038..3cc5dd7828464 100644 --- a/clang/test/CodeGenCXX/amdgcn-func-arg.cpp +++ b/clang/test/CodeGenCXX/amdgcn-func-arg.cpp @@ -43,9 +43,9 @@ void func_with_indirect_arg(A a) { // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[AGG_TMP_ASCAST]], ptr align 4 [[A_ASCAST]], i64 4, i1 false) // CHECK-NEXT: [[AGG_TMP_ASCAST_ASCAST:%.*]] = addrspacecast ptr [[AGG_TMP_ASCAST]] to ptr addrspace(5) // CHECK-NEXT: call void @_Z22func_with_indirect_arg1A(ptr addrspace(5) noundef [[AGG_TMP_ASCAST_ASCAST]]) -// CHECK-NEXT: call void @_ZN1AD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[AGG_TMP_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[AGG_TMP_ASCAST]]) // CHECK-NEXT: call void @_Z17func_with_ref_argR1A(ptr noundef nonnull align 4 dereferenceable(4) [[A_ASCAST]]) -// CHECK-NEXT: call void @_ZN1AD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[A_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[A_ASCAST]]) // CHECK-NEXT: ret void // void test_indirect_arg_auto() { @@ -61,7 +61,7 @@ void test_indirect_arg_auto() { // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[AGG_TMP_ASCAST]], ptr align 4 addrspacecast (ptr addrspace(1) @g_a to ptr), i64 4, i1 false) // CHECK-NEXT: [[AGG_TMP_ASCAST_ASCAST:%.*]] = addrspacecast ptr [[AGG_TMP_ASCAST]] to ptr addrspace(5) // CHECK-NEXT: call void @_Z22func_with_indirect_arg1A(ptr addrspace(5) noundef [[AGG_TMP_ASCAST_ASCAST]]) -// CHECK-NEXT: call void @_ZN1AD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[AGG_TMP_ASCAST]]) +// CHECK-NEXT: call void @_ZN1AD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[AGG_TMP_ASCAST]]) // CHECK-NEXT: call void @_Z17func_with_ref_argR1A(ptr noundef nonnull align 4 dereferenceable(4) addrspacecast (ptr addrspace(1) @g_a to ptr)) // CHECK-NEXT: ret void // diff --git a/clang/test/CodeGenCXX/builtins.cpp b/clang/test/CodeGenCXX/builtins.cpp index ef30a25a17922..ad0d06cdb2637 100644 --- a/clang/test/CodeGenCXX/builtins.cpp +++ b/clang/test/CodeGenCXX/builtins.cpp @@ -120,17 +120,28 @@ void test_char_reference(char& a) { // CHECK-NOT: call i8 @llvm.bswap.i8 // CHECK: ret void +void test_bool_reference(bool& a) { + __builtin_bswapg(a); +} +// CHECK-LABEL: @_Z19test_bool_referenceRb +// CHECK: store ptr %a, ptr +// CHECK: load ptr, ptr +// CHECK-NOT: call i8 @llvm.bswap.i8 +// CHECK: ret void + void test_bitint() { - _BitInt(8) a = 0x12; + bool a = true; __builtin_bswapg(a); - _BitInt(16) b = 0x1234; + _BitInt(8) b = 0x12; __builtin_bswapg(b); - _BitInt(32) c = 0x00001234; + _BitInt(16) c = 0x1234; __builtin_bswapg(c); - _BitInt(64) d = 0x0000000000001234; + _BitInt(32) d = 0x00001234; __builtin_bswapg(d); - _BitInt(128) e = ~(_BitInt(128))0; + _BitInt(64) e = 0x0000000000001234; __builtin_bswapg(e); + _BitInt(128) f = ~(_BitInt(128))0; + __builtin_bswapg(f); } // CHECK-LABEL: @_Z11test_bitintv // CHECK-NOT: call i8 @llvm.bswap.i8 diff --git a/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp b/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp index 4eafa720e0cb4..9d1c9cc0a2ab6 100644 --- a/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp +++ b/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp @@ -217,7 +217,7 @@ void ArrayInit() { // CHECK: [[ARRAY_DESTROY_BODY2]]: // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %1, %cleanup ], [ %arraydestroy.element, %[[ARRAY_DESTROY_BODY2]] ] // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 - // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %arraydestroy.element) // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, %arr // CHECK-NEXT: br i1 %arraydestroy.done, label %[[ARRAY_DESTROY_DONE2]], label %[[ARRAY_DESTROY_BODY2]] @@ -265,7 +265,7 @@ void ArraySubobjects() { // CHECK: [[ARRAY_DESTROY_BODY]]: // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %0, %if.then ], [ %arraydestroy.element, %[[ARRAY_DESTROY_BODY]] ] // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 - // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %arraydestroy.element) // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, %arr2 // CHECK-NEXT: br i1 %arraydestroy.done, label %[[ARRAY_DESTROY_DONE]], label %[[ARRAY_DESTROY_BODY]] @@ -277,7 +277,7 @@ void ArraySubobjects() { // CHECK: [[ARRAY_DESTROY_BODY2]]: // CHECK-NEXT: %arraydestroy.elementPast4 = phi ptr [ %1, %[[ARRAY_DESTROY_DONE]] ], [ %arraydestroy.element5, %[[ARRAY_DESTROY_BODY2]] ] // CHECK-NEXT: %arraydestroy.element5 = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast4, i64 -1 - // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element5) + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %arraydestroy.element5) // CHECK-NEXT: %arraydestroy.done6 = icmp eq ptr %arraydestroy.element5, [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 %arraydestroy.done6, label %[[ARRAY_DESTROY_DONE2:.+]], label %[[ARRAY_DESTROY_BODY2]] @@ -384,7 +384,7 @@ void NewArrayInit() { // CHECK: arraydestroy.body: // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %{{.*}}, %if.then ], [ %arraydestroy.element, %arraydestroy.body ] // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 - // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %arraydestroy.element) // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, %0 // CHECK-NEXT: br i1 %arraydestroy.done, label %arraydestroy.done{{.*}}, label %arraydestroy.body diff --git a/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp b/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp index 24b1a4dd42977..c83cb32251462 100644 --- a/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp +++ b/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp @@ -41,11 +41,11 @@ void glob_delete_A(A *a) { ::delete a; } // CHECK: icmp eq ptr %[[a]], null // CHECK: br i1 -// CHECK-ITANIUM: call void @_ZN1AD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %[[a]]) +// CHECK-ITANIUM: call void @_ZN1AD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %[[a]]) // CHECK-ITANIUM-NEXT: call void @_ZdlPvm(ptr noundef %[[a]], i64 noundef 8) -// CHECK-MSABI64: call void @"??1A@@QEAA@XZ"(ptr noundef nonnull align 8 dereferenceable(8) %[[a]]) +// CHECK-MSABI64: call void @"??1A@@QEAA@XZ"(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %[[a]]) // CHECK-MSABI64-NEXT: call void @"??3@YAXPEAX_K@Z"(ptr noundef %[[a]], i64 noundef 8) -// CHECK-MSABI32: call x86_thiscallcc void @"??1A@@QAE@XZ"(ptr noundef nonnull align 4 dereferenceable(4) %[[a]]) +// CHECK-MSABI32: call x86_thiscallcc void @"??1A@@QAE@XZ"(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %[[a]]) // CHECK-MSABI32-NEXT: call void @"??3@YAXPAXI@Z"(ptr noundef %[[a]], i32 noundef 4) struct B { diff --git a/clang/test/CodeGenCXX/destructor-dead-on-return.cpp b/clang/test/CodeGenCXX/destructor-dead-on-return.cpp new file mode 100644 index 0000000000000..351d3b0de4d53 --- /dev/null +++ b/clang/test/CodeGenCXX/destructor-dead-on-return.cpp @@ -0,0 +1,86 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --filter "define" --version 6 +// Check that we appropriately annotate destructors with a dead_on_return +// attribute. +// +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fno-lifetime-dse -emit-llvm %s -o - | FileCheck %s --check-prefix NO-LIFETIME-DSE + +void opaque(); +void opaque(char*); + +class Foo { +public: + ~Foo(); + +private: + char FooVar[4]; +}; + +// CHECK-LABEL: define dso_local void @_ZN3FooD1Ev( +// CHECK-SAME: ptr noundef nonnull align 1 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +// NO-LIFETIME-DSE-LABEL: define dso_local void @_ZN3FooD1Ev( +// NO-LIFETIME-DSE-SAME: ptr noundef nonnull align 1 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +Foo::~Foo() { + opaque(FooVar); +} + +class Bar { +public: + ~Bar(); + +private: + char BarVar[8]; +}; + +// CHECK-LABEL: define dso_local void @_ZN3BarD1Ev( +// CHECK-SAME: ptr noundef nonnull align 1 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +// NO-LIFETIME-DSE-LABEL: define dso_local void @_ZN3BarD1Ev( +// NO-LIFETIME-DSE-SAME: ptr noundef nonnull align 1 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +Bar::~Bar() { + opaque(BarVar); +} + +class BarInheritsFoo : public Foo { +public: + ~BarInheritsFoo(); + +private: + char BarVar[12]; +}; + +// CHECK-LABEL: define dso_local void @_ZN14BarInheritsFooD1Ev( +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +// NO-LIFETIME-DSE-LABEL: define dso_local void @_ZN14BarInheritsFooD1Ev( +// NO-LIFETIME-DSE-SAME: ptr noundef nonnull align 1 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +BarInheritsFoo::~BarInheritsFoo() { + opaque(BarVar); +} + +class BarVirtualInheritsFoo : public virtual Foo { +public: + ~BarVirtualInheritsFoo(); + +private: + char BarVar[16]; +}; + +// CHECK-LABEL: define dso_local void @_ZN21BarVirtualInheritsFooD1Ev( +// CHECK-SAME: ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +// NO-LIFETIME-DSE-LABEL: define dso_local void @_ZN21BarVirtualInheritsFooD1Ev( +// NO-LIFETIME-DSE-SAME: ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +BarVirtualInheritsFoo::~BarVirtualInheritsFoo() { + opaque(BarVar); +} + +class Empty { +public: + ~Empty(); +}; + +// CHECK-LABEL: define dso_local void @_ZN5EmptyD1Ev( +// CHECK-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +// NO-LIFETIME-DSE-LABEL: define dso_local void @_ZN5EmptyD1Ev( +// NO-LIFETIME-DSE-SAME: ptr noundef nonnull align 1 dereferenceable(1) [[THIS:%.*]]) unnamed_addr #[[ATTR0:[0-9]+]] align 2 { +Empty::~Empty() { + opaque(); +} diff --git a/clang/test/CodeGenCXX/dynamic-cast-address-space.cpp b/clang/test/CodeGenCXX/dynamic-cast-address-space.cpp index 691a74f000adb..f81fc84691bf6 100644 --- a/clang/test/CodeGenCXX/dynamic-cast-address-space.cpp +++ b/clang/test/CodeGenCXX/dynamic-cast-address-space.cpp @@ -24,11 +24,9 @@ B fail; // CHECK-LABEL: define dso_local noundef nonnull align 8 dereferenceable(8) ptr @_Z1fP1A( // CHECK-SAME: ptr noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr // CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 @@ -61,11 +59,9 @@ B fail; // WITH-NONZERO-DEFAULT-AS-LABEL: define spir_func noundef align 8 dereferenceable(8) ptr addrspace(4) @_Z1fP1A( // WITH-NONZERO-DEFAULT-AS-SAME: ptr addrspace(4) noundef [[A:%.*]]) addrspace(4) #[[ATTR0:[0-9]+]] personality ptr addrspace(4) @__gxx_personality_v0 { // WITH-NONZERO-DEFAULT-AS-NEXT: entry: -// WITH-NONZERO-DEFAULT-AS-NEXT: [[RETVAL:%.*]] = alloca ptr addrspace(4), align 8 // WITH-NONZERO-DEFAULT-AS-NEXT: [[A_ADDR:%.*]] = alloca ptr addrspace(4), align 8 // WITH-NONZERO-DEFAULT-AS-NEXT: [[EXN_SLOT:%.*]] = alloca ptr addrspace(4), align 8 // WITH-NONZERO-DEFAULT-AS-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// WITH-NONZERO-DEFAULT-AS-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) // WITH-NONZERO-DEFAULT-AS-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr [[A_ADDR]] to ptr addrspace(4) // WITH-NONZERO-DEFAULT-AS-NEXT: store ptr addrspace(4) [[A]], ptr addrspace(4) [[A_ADDR_ASCAST]], align 8 // WITH-NONZERO-DEFAULT-AS-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[A_ADDR_ASCAST]], align 8 diff --git a/clang/test/CodeGenCXX/exceptions-seh.cpp b/clang/test/CodeGenCXX/exceptions-seh.cpp index bb374dd1f5bd5..7ccd17fa73bbd 100644 --- a/clang/test/CodeGenCXX/exceptions-seh.cpp +++ b/clang/test/CodeGenCXX/exceptions-seh.cpp @@ -4,6 +4,12 @@ // RUN: %clang_cc1 -std=c++11 -fblocks -fms-extensions %s -triple=x86_64-windows-msvc -emit-llvm \ // RUN: -o - -mconstructor-aliases -O1 -disable-llvm-passes | \ // RUN: FileCheck %s --check-prefix=CHECK --check-prefix=NOCXX +// RUN: %clang_cc1 -triple x86_64-windows -fasync-exceptions -fcxx-exceptions -fexceptions \ +// RUN: -fms-extensions -x c++ -emit-llvm-only -verify %s -DERR1 +// RUN: %clang_cc1 -triple x86_64-windows -fasync-exceptions -fcxx-exceptions -fexceptions \ +// RUN: -fms-extensions -x c++ -emit-llvm-only -verify %s -DERR2 +// RUN: %clang_cc1 -triple x86_64-windows -fasync-exceptions -fcxx-exceptions -fexceptions \ +// RUN: -fms-extensions -x c++ -emit-llvm-only -verify %s -DERR3 extern "C" unsigned long _exception_code(); extern "C" void might_throw(); @@ -175,3 +181,26 @@ void use_inline() { // CHECK: attributes #[[NOINLINE]] = { {{.*noinline.*}} } void seh_in_noexcept() noexcept { __try {} __finally {} } + +#if defined(ERR1) +void seh_unwinding() { + __try { + HasCleanup x; // expected-error{{'__try' is not permitted in functions that require object unwinding}} + } __except (1) { + } +} +#elif defined(ERR2) +void seh_unwinding() { + __try { + } __except (1) { + HasCleanup x; // expected-error{{'__try' is not permitted in functions that require object unwinding}} + } +} +#elif defined(ERR3) +void seh_unwinding() { + HasCleanup x; // expected-error{{'__try' is not permitted in functions that require object unwinding}} + __try { + } __except (1) { + } +} +#endif diff --git a/clang/test/CodeGenCXX/externc-ifunc-resolver.cpp b/clang/test/CodeGenCXX/externc-ifunc-resolver.cpp index be4453ae7eb08..1328781734e96 100644 --- a/clang/test/CodeGenCXX/externc-ifunc-resolver.cpp +++ b/clang/test/CodeGenCXX/externc-ifunc-resolver.cpp @@ -1,6 +1,7 @@ // RUN: %clang_cc1 -triple x86_64-linux-gnu -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple x86_64-apple-macosx -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple arm64-apple-macosx -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -emit-llvm -o - %s | FileCheck %s extern "C" { __attribute__((used)) static void *resolve_foo() { return 0; } diff --git a/clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp b/clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp index cbce869fb21b6..459c1b6593fa1 100644 --- a/clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp +++ b/clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp @@ -133,7 +133,7 @@ void bar() { // CLANG21: arraydestroy.body: // CLANG21-NEXT: %arraydestroy.elementPast = phi ptr [ %delete.end, %delete.notnull ], [ %arraydestroy.element, %arraydestroy.body ] // CLANG21-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Bird, ptr %arraydestroy.elementPast, i64 -1 -// CLANG21-NEXT: call void @"??1Bird@@UEAA@XZ"(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) +// CLANG21-NEXT: call void @"??1Bird@@UEAA@XZ"(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %arraydestroy.element) // CLANG21-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, %0 // CLANG21-NEXT: br i1 %arraydestroy.done, label %arraydestroy.done1, label %arraydestroy.body // CLANG21: arraydestroy.done1: diff --git a/clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp b/clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp index b16cb30d7133f..6412bf5b1dc3b 100644 --- a/clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp +++ b/clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp @@ -81,8 +81,8 @@ void TesttheTest() { // CHECK-NEXT: call void @llvm.trap() // CHECK-NEXT: unreachable // CHECK: dtor.scalar: -// X64-NEXT: call void @"??1Test@@UEAA@XZ"(ptr noundef nonnull align 8 dereferenceable(8) %this1) -// X86-NEXT: call x86_thiscallcc void @"??1Test@@UAE@XZ"(ptr noundef nonnull align 4 dereferenceable(4) %this1) +// X64-NEXT: call void @"??1Test@@UEAA@XZ"(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %this1) +// X86-NEXT: call x86_thiscallcc void @"??1Test@@UAE@XZ"(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) %this1) // CHECK-NEXT: %6 = and i32 %should_call_delete2, 1 // CHECK-NEXT: %7 = icmp eq i32 %6, 0 // CHECK-NEXT: br i1 %7, label %dtor.continue, label %dtor.call_delete diff --git a/clang/test/CodeGenCXX/ptrauth-apple-kext-indirect-virtual-dtor-call.cpp b/clang/test/CodeGenCXX/ptrauth-apple-kext-indirect-virtual-dtor-call.cpp index 7bcf1fbfdb9de..47d8ffa452733 100644 --- a/clang/test/CodeGenCXX/ptrauth-apple-kext-indirect-virtual-dtor-call.cpp +++ b/clang/test/CodeGenCXX/ptrauth-apple-kext-indirect-virtual-dtor-call.cpp @@ -14,11 +14,11 @@ void DELETE(B1 *pb1) { // CHECK-LABEL: define void @_ZN2B1D0Ev // CHECK: [[T1:%.*]] = load ptr, ptr getelementptr inbounds (ptr, ptr @_ZTV2B1, i64 2) // CHECK-NEXT: [[B1:%.*]] = call i64 @llvm.ptrauth.blend(i64 ptrtoint (ptr getelementptr inbounds (ptr, ptr @_ZTV2B1, i64 2) to i64), i64 14635) -// CHECK-NEXT: call noundef ptr [[T1]](ptr noundef nonnull align 8 dereferenceable(8) [[T2:%.*]]) [ "ptrauth"(i32 0, i64 [[B1]]) ] +// CHECK-NEXT: call noundef ptr [[T1]](ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[T2:%.*]]) [ "ptrauth"(i32 0, i64 [[B1]]) ] // CHECK-LABEL: define void @_Z6DELETEP2B1 // CHECK: [[T3:%.*]] = load ptr, ptr getelementptr inbounds (ptr, ptr @_ZTV2B1, i64 2) // CHECK-NEXT: [[B3:%.*]] = call i64 @llvm.ptrauth.blend(i64 ptrtoint (ptr getelementptr inbounds (ptr, ptr @_ZTV2B1, i64 2) to i64), i64 14635) -// CHECK-NEXT: call noundef ptr [[T3]](ptr noundef nonnull align 8 dereferenceable(8) [[T4:%.*]]) [ "ptrauth"(i32 0, i64 [[B3]]) +// CHECK-NEXT: call noundef ptr [[T3]](ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[T4:%.*]]) [ "ptrauth"(i32 0, i64 [[B3]]) template struct Templ { @@ -45,6 +45,6 @@ void f(SubTempl* t) { } // CHECK: getelementptr inbounds (ptr, ptr @_ZTV5TemplIiE, i64 2) -// CHECK: declare void @_ZN5TemplIiED0Ev(ptr noundef nonnull align 8 dereferenceable(8)) +// CHECK: declare void @_ZN5TemplIiED0Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8)) // CHECK: define internal void @_ZN5TemplIiE1fEv(ptr noundef nonnull align 8 dereferenceable(8) %this) // CHECK: define internal void @_ZN5TemplIiE1gEv(ptr noundef nonnull align 8 dereferenceable(8) %this) diff --git a/clang/test/CodeGenCXX/reflection-mangle-itanium.cpp b/clang/test/CodeGenCXX/reflection-mangle-itanium.cpp new file mode 100644 index 0000000000000..a6266165e77f8 --- /dev/null +++ b/clang/test/CodeGenCXX/reflection-mangle-itanium.cpp @@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -std=c++26 -freflection -triple x86_64-unknown-linux-gnu \ +// RUN: -emit-llvm -o - %s -verify + +int main() { + (void)(^^int); // expected-error {{cannot compile this scalar expression yet}} + return 0; +} diff --git a/clang/test/CodeGenCXX/reflection-mangle-ms.cpp b/clang/test/CodeGenCXX/reflection-mangle-ms.cpp new file mode 100644 index 0000000000000..327bc0111bae8 --- /dev/null +++ b/clang/test/CodeGenCXX/reflection-mangle-ms.cpp @@ -0,0 +1,7 @@ +// RUN: %clang_cc1 -std=c++26 -freflection -triple x86_64-pc-windows-msvc \ +// RUN: -emit-llvm -o - %s -verify + +int main() { + (void)(^^int); // expected-error {{cannot compile this scalar expression yet}} + return 0; +} diff --git a/clang/test/CodeGenCXX/sanitize-trap-loop.cpp b/clang/test/CodeGenCXX/sanitize-trap-loop.cpp new file mode 100644 index 0000000000000..ee083c52f5c30 --- /dev/null +++ b/clang/test/CodeGenCXX/sanitize-trap-loop.cpp @@ -0,0 +1,20 @@ +// RUN: %clang_cc1 -flto -flto-unit -triple x86_64-unknown-linux -fvisibility=hidden -fsanitize=cfi-vcall,signed-integer-overflow -fsanitize-trap=cfi-vcall,signed-integer-overflow -fsanitize-trap-loop -emit-llvm -o - %s | FileCheck %s + +struct A { + virtual void f(); +}; + +void vcall(A *a) { + // CHECK: [[TEST:%.*]] = call i1 @llvm.type.test + // CHECK-NEXT: [[NOT:%.*]] = xor i1 [[TEST]], true + // CHECK-NEXT: call void @llvm.cond.loop(i1 [[NOT]]) + a->f(); +} + +int overflow(int a, int b) { + // CHECK: [[OVERFLOW:%.*]] = extractvalue { i32, i1 } %2, 1, !nosanitize + // CHECK-NEXT: [[NOTOVERFLOW:%.*]] = xor i1 [[OVERFLOW]], true, !nosanitize + // CHECK-NEXT: [[NOTNOTOVERFLOW:%.*]] = xor i1 [[NOTOVERFLOW]], true, !nosanitize + // CHECK-NEXT: call void @llvm.cond.loop(i1 [[NOTNOTOVERFLOW]]) + return a + b; +} diff --git a/clang/test/CodeGenCXX/tmp-md-nodes3.cpp b/clang/test/CodeGenCXX/tmp-md-nodes3.cpp new file mode 100644 index 0000000000000..4656f6462e932 --- /dev/null +++ b/clang/test/CodeGenCXX/tmp-md-nodes3.cpp @@ -0,0 +1,53 @@ +// REQUIRES: asserts, riscv-registered-target +// Should trigger GenerateVarArgsThunk. +// RUN: %clang_cc1 -O0 -triple riscv64-linux-gnu -debug-info-kind=limited -emit-llvm %s -o - | \ +// RUN: FileCheck %s + +// RUN: %clang_cc1 -O0 -triple riscv64-linux-gnu -debug-info-kind=limited -emit-obj %s -o - | \ +// RUN: llvm-dwarfdump --verify - + +// This test checks that clang doesn't crash when creating a varargs thunk +// by cloning a function which DILocalVariable types are unresolved at cloning +// time. +// In such case, as a workaround, instead of cloning unresolved types for +// the thunk, clang produces thunk DILocalVariables that refer to local +// types from the original DISubprogram. + +typedef signed char __int8_t; +typedef int BOOL; +class CMsgAgent; + +class CFs { +public: + typedef enum {} CACHE_HINT; + virtual BOOL ReqCacheHint( CMsgAgent* p_ma, CACHE_HINT hint, ... ) ; +}; + +typedef struct {} _Lldiv_t; + +class CBdVfs { +public: + virtual ~CBdVfs( ) {} +}; + +class CBdVfsImpl : public CBdVfs, public CFs { + BOOL ReqCacheHint( CMsgAgent* p_ma, CACHE_HINT hint, ... ); +}; + +BOOL CBdVfsImpl::ReqCacheHint( CMsgAgent* p_ma, CACHE_HINT hint, ... ) { + // Complete enum with no defintion. Clang allows to declare variables of + // such type. + enum class E : int; + E enum_var; + // Structure has forward declaration. DIDerivedType which is a pointer + // to it is unresolved during debug info generation for the function. + struct LocalStruct; + LocalStruct *struct_var; + + struct GlobalStruct {}; + + return true; +} + +// Check that thunk is emitted. +// CHECK: define {{.*}} @_ZThn{{[48]}}_N10CBdVfsImpl12ReqCacheHintEP9CMsgAgentN3CFs10CACHE_HINTEz( diff --git a/clang/test/CodeGenCXX/zos-typename.cpp b/clang/test/CodeGenCXX/zos-typename.cpp new file mode 100644 index 0000000000000..dabb9cc25ae60 --- /dev/null +++ b/clang/test/CodeGenCXX/zos-typename.cpp @@ -0,0 +1,14 @@ +// RUN: %clang -S -emit-llvm -target s390x-none-zos -I%S -fexec-charset=UTF-8 %s -o - | FileCheck %s +// RUN: %clang -S -emit-llvm -target s390x-none-zos -I%S %s -o - | FileCheck %s +// RUN: %clang -S -emit-llvm -target s390x-none-zos -I%S -m32 %s -o - | FileCheck %s + +#include + +class TestClass {}; +struct TestStruct {}; + +const char *A = typeid(TestClass).name(); +const char *B = typeid(TestStruct).name(); + +// CHECK: @_ZTS9TestClass = {{.*}} c"\F9\E3\85\A2\A3\C3\93\81\A2\A2\009TestClass\00" +// CHECK: @_ZTS10TestStruct = {{.*}} c"\F1\F0\E3\85\A2\A3\E2\A3\99\A4\83\A3\0010TestStruct\00" diff --git a/clang/test/CodeGenCoroutines/coro-await-elidable.cpp b/clang/test/CodeGenCoroutines/coro-await-elidable.cpp index deb19b4a50043..71c56f310b344 100644 --- a/clang/test/CodeGenCoroutines/coro-await-elidable.cpp +++ b/clang/test/CodeGenCoroutines/coro-await-elidable.cpp @@ -124,4 +124,54 @@ Task elidableWithPackRecursive() { co_return co_await sumAll(addTasks(returnSame(1), returnSame(2)), returnSame(3)); } +// Test that parenthesized expressions don't break HALO +// CHECK-LABEL: define{{.*}} @_Z14withParenthesev{{.*}} { +Task withParenthese() { + // CHECK: call void @_Z6calleev(ptr {{.*}}) #[[ELIDE_SAFE]] + co_return co_await (callee()); +} + +// Test nested parentheses +// CHECK-LABEL: define{{.*}} @_Z20withNestedParenthesev{{.*}} { +Task withNestedParenthese() { + // CHECK: call void @_Z6calleev(ptr {{.*}}) #[[ELIDE_SAFE]] + co_return co_await ((callee())); +} + +// Test parentheses with elidable argument +// CHECK-LABEL: define{{.*}} @_Z21withParenArgsElidablev{{.*}} { +Task withParenArgsElidable() { + // CHECK: call void @_Z10returnSamei(ptr {{.*}}, i32 noundef 2) #[[ELIDE_SAFE]] + // CHECK: call void @_Z10returnSamei(ptr {{.*}}, i32 noundef 3){{$}} + co_return co_await (addTasks(returnSame(2), returnSame(3))); +} + +// Test parentheses around elidable argument expressions +// CHECK-LABEL: define{{.*}} @_Z24withParenInsideArgsFirstv{{.*}} { +Task withParenInsideArgsFirst() { + // Argument wrapped in parens should still be elidable + // CHECK: call void @_Z10returnSamei(ptr {{.*}}, i32 noundef 4) #[[ELIDE_SAFE]] + // CHECK: call void @_Z10returnSamei(ptr {{.*}}, i32 noundef 5){{$}} + co_return co_await addTasks((returnSame(4)), returnSame(5)); +} + +// CHECK-LABEL: define{{.*}} @_Z25withParenInsideArgsSecondv{{.*}} { +Task withParenInsideArgsSecond() { + // Both arguments wrapped in parens, first should still be elidable + // CHECK: call void @_Z10returnSamei(ptr {{.*}}, i32 noundef 6) #[[ELIDE_SAFE]] + // CHECK: call void @_Z10returnSamei(ptr {{.*}}, i32 noundef 7){{$}} + co_return co_await addTasks((returnSame(6)), (returnSame(7))); +} + +// Test operator overloading scenario (like the `operator|` case) +Task operator|(int, [[clang::coro_await_elidable_argument]] Task &&t) { + co_return co_await t; +} + +// CHECK-LABEL: define{{.*}} @_Z15withOperatorOldv{{.*}} { +Task withOperatorOld() { + // CHECK: call void @_Z10returnSamei(ptr {{.*}}, i32 noundef 8) #[[ELIDE_SAFE]] + co_return co_await (0 | returnSame(8)); +} + // CHECK: attributes #[[ELIDE_SAFE]] = { coro_elide_safe } diff --git a/clang/test/CodeGenHIP/amdgpu-barrier-type.hip b/clang/test/CodeGenHIP/amdgpu-barrier-type.hip index 229e8b3c737c6..383fba9c2493f 100644 --- a/clang/test/CodeGenHIP/amdgpu-barrier-type.hip +++ b/clang/test/CodeGenHIP/amdgpu-barrier-type.hip @@ -17,9 +17,7 @@ void useBar(__amdgpu_named_workgroup_barrier_t *); // CHECK-LABEL: define {{[^@]+}}@_Z7testSemPu34__amdgpu_named_workgroup_barrier_t // CHECK-SAME: (ptr noundef [[P:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr // CHECK-NEXT: store ptr [[P]], ptr [[P_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR_ASCAST]], align 8 diff --git a/clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip b/clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip new file mode 100644 index 0000000000000..68d3ed674a15a --- /dev/null +++ b/clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip @@ -0,0 +1,91 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 5 + +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1250 -fcuda-is-device -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1251 -fcuda-is-device -emit-llvm -o - %s | FileCheck %s + +#define __device__ __attribute__((device)) + +typedef int v2i __attribute__((ext_vector_type(2))); +typedef int v4i __attribute__((ext_vector_type(4))); + +template +__device__ void template_cooperative_atomic_store_32x4B(int* gaddr, int val) { + __builtin_amdgcn_cooperative_atomic_store_32x4B(gaddr, val, AO, "agent"); +} + +__device__ void test_amdgcn_cooperative_atomic_store_32x4B(int* gaddr, int val) +{ + template_cooperative_atomic_store_32x4B<__ATOMIC_SEQ_CST>(gaddr, val); +} + +template +__device__ int template_cooperative_atomic_load_32x4B(int* gaddr) { + return __builtin_amdgcn_cooperative_atomic_load_32x4B(gaddr, AO, ""); +} + +__device__ void test_amdgcn_cooperative_atomic_load_32x4B(int* addr, int *out) +{ + *out = template_cooperative_atomic_load_32x4B<__ATOMIC_SEQ_CST>(addr); +} + +// CHECK-LABEL: define dso_local void @_Z42test_amdgcn_cooperative_atomic_store_32x4BPii( +// CHECK-SAME: ptr noundef [[GADDR:%.*]], i32 noundef [[VAL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[GADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[GADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GADDR_ADDR]] to ptr +// CHECK-NEXT: [[VAL_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VAL_ADDR]] to ptr +// CHECK-NEXT: store ptr [[GADDR]], ptr [[GADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[VAL_ADDR_ASCAST]], align 4 +// CHECK-NEXT: call void @_Z39template_cooperative_atomic_store_32x4BILj5EEvPii(ptr noundef [[TMP0]], i32 noundef [[TMP1]]) #[[ATTR3:[0-9]+]] +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define linkonce_odr void @_Z39template_cooperative_atomic_store_32x4BILj5EEvPii( +// CHECK-SAME: ptr noundef [[GADDR:%.*]], i32 noundef [[VAL:%.*]]) #[[ATTR0]] comdat { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[GADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[GADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GADDR_ADDR]] to ptr +// CHECK-NEXT: [[VAL_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VAL_ADDR]] to ptr +// CHECK-NEXT: store ptr [[GADDR]], ptr [[GADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR_ASCAST]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[VAL_ADDR_ASCAST]], align 4 +// CHECK-NEXT: call void @llvm.amdgcn.cooperative.atomic.store.32x4B.p0(ptr [[TMP0]], i32 [[TMP1]], i32 5, metadata [[META4:![0-9]+]]) +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define dso_local void @_Z41test_amdgcn_cooperative_atomic_load_32x4BPiS_( +// CHECK-SAME: ptr noundef [[ADDR:%.*]], ptr noundef [[OUT:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z38template_cooperative_atomic_load_32x4BILj5EEiPi(ptr noundef [[TMP0]]) #[[ATTR3]] +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store i32 [[CALL]], ptr [[TMP1]], align 4 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define linkonce_odr noundef i32 @_Z38template_cooperative_atomic_load_32x4BILj5EEiPi( +// CHECK-SAME: ptr noundef [[GADDR:%.*]]) #[[ATTR0]] comdat { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[GADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[GADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[GADDR_ADDR]] to ptr +// CHECK-NEXT: store ptr [[GADDR]], ptr [[GADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[GADDR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.cooperative.atomic.load.32x4B.p0(ptr [[TMP0]], i32 5, metadata [[META5:![0-9]+]]) +// CHECK-NEXT: ret i32 [[TMP1]] +// +//. +// CHECK: [[META4]] = !{!"agent"} +// CHECK: [[META5]] = !{!""} +//. diff --git a/clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip b/clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip new file mode 100644 index 0000000000000..bc7a0878c9e57 --- /dev/null +++ b/clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip @@ -0,0 +1,48 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 5 +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1250 -emit-llvm -fcuda-is-device -o - %s | FileCheck %s + +#define __device__ __attribute__((device)) + +typedef int v4i __attribute__((ext_vector_type(4))); + +template +__device__ v4i templated_amdgcn_flat_load_monitor_b128(v4i* inptr) +{ + return __builtin_amdgcn_flat_load_monitor_b128(inptr, AO, Scope); +} + +__device__ void test_amdgcn_flat_load_monitor_b128_from_template(v4i* inptr, v4i *out) +{ + *out = templated_amdgcn_flat_load_monitor_b128<__ATOMIC_SEQ_CST, __MEMORY_SCOPE_SYSTEM>(inptr); +} + +// CHECK-LABEL: define dso_local void @_Z48test_amdgcn_flat_load_monitor_b128_from_templatePDv4_iS0_( +// CHECK-SAME: ptr noundef [[INPTR:%.*]], ptr noundef [[OUT:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[INPTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[INPTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[INPTR_ADDR]] to ptr +// CHECK-NEXT: [[OUT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[OUT_ADDR]] to ptr +// CHECK-NEXT: store ptr [[INPTR]], ptr [[INPTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store ptr [[OUT]], ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[INPTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[CALL:%.*]] = call noundef <4 x i32> @_Z39templated_amdgcn_flat_load_monitor_b128ILj5ELj0EEDv4_iPS0_(ptr noundef [[TMP0]]) #[[ATTR2:[0-9]+]] +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OUT_ADDR_ASCAST]], align 8 +// CHECK-NEXT: store <4 x i32> [[CALL]], ptr [[TMP1]], align 16 +// CHECK-NEXT: ret void +// +// +// CHECK-LABEL: define linkonce_odr noundef <4 x i32> @_Z39templated_amdgcn_flat_load_monitor_b128ILj5ELj0EEDv4_iPS0_( +// CHECK-SAME: ptr noundef [[INPTR:%.*]]) #[[ATTR0]] comdat { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[INPTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[INPTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[INPTR_ADDR]] to ptr +// CHECK-NEXT: store ptr [[INPTR]], ptr [[INPTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[INPTR_ADDR_ASCAST]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr [[TMP0]], i32 5, metadata [[META4:![0-9]+]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +//. +// CHECK: [[META4]] = !{!""} +//. diff --git a/clang/test/CodeGenHIP/builtins-make-buffer-rsrc.hip b/clang/test/CodeGenHIP/builtins-make-buffer-rsrc.hip index e92105091712c..83d5f44b3aeb8 100644 --- a/clang/test/CodeGenHIP/builtins-make-buffer-rsrc.hip +++ b/clang/test/CodeGenHIP/builtins-make-buffer-rsrc.hip @@ -7,12 +7,10 @@ // CHECK-LABEL: define dso_local ptr addrspace(8) @_Z31test_amdgcn_make_buffer_rsrc_p0Pvsii( // CHECK-SAME: ptr noundef [[P:%.*]], i16 noundef signext [[STRIDE:%.*]], i32 noundef [[NUM:%.*]], i32 noundef [[FLAGS:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca ptr addrspace(8), align 16, addrspace(5) // CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[STRIDE_ADDR:%.*]] = alloca i16, align 2, addrspace(5) // CHECK-NEXT: [[NUM_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[FLAGS_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr // CHECK-NEXT: [[STRIDE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[STRIDE_ADDR]] to ptr // CHECK-NEXT: [[NUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[NUM_ADDR]] to ptr @@ -36,11 +34,9 @@ __device__ __amdgpu_buffer_rsrc_t test_amdgcn_make_buffer_rsrc_p0(void *p, short // CHECK-LABEL: define dso_local ptr addrspace(8) @_Z47test_amdgcn_make_buffer_rsrc_p0_stride_constantPvii( // CHECK-SAME: ptr noundef [[P:%.*]], i32 noundef [[NUM:%.*]], i32 noundef [[FLAGS:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca ptr addrspace(8), align 16, addrspace(5) // CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[NUM_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[FLAGS_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr // CHECK-NEXT: [[NUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[NUM_ADDR]] to ptr // CHECK-NEXT: [[FLAGS_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[FLAGS_ADDR]] to ptr @@ -61,11 +57,9 @@ __device__ __amdgpu_buffer_rsrc_t test_amdgcn_make_buffer_rsrc_p0_stride_constan // CHECK-LABEL: define dso_local ptr addrspace(8) @_Z44test_amdgcn_make_buffer_rsrc_p0_num_constantPvsi( // CHECK-SAME: ptr noundef [[P:%.*]], i16 noundef signext [[STRIDE:%.*]], i32 noundef [[FLAGS:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca ptr addrspace(8), align 16, addrspace(5) // CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[STRIDE_ADDR:%.*]] = alloca i16, align 2, addrspace(5) // CHECK-NEXT: [[FLAGS_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr // CHECK-NEXT: [[STRIDE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[STRIDE_ADDR]] to ptr // CHECK-NEXT: [[FLAGS_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[FLAGS_ADDR]] to ptr @@ -85,11 +79,9 @@ __device__ __amdgpu_buffer_rsrc_t test_amdgcn_make_buffer_rsrc_p0_num_constant(v // CHECK-LABEL: define dso_local ptr addrspace(8) @_Z46test_amdgcn_make_buffer_rsrc_p0_flags_constantPvsi( // CHECK-SAME: ptr noundef [[P:%.*]], i16 noundef signext [[STRIDE:%.*]], i32 noundef [[NUM:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca ptr addrspace(8), align 16, addrspace(5) // CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[STRIDE_ADDR:%.*]] = alloca i16, align 2, addrspace(5) // CHECK-NEXT: [[NUM_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr // CHECK-NEXT: [[STRIDE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[STRIDE_ADDR]] to ptr // CHECK-NEXT: [[NUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[NUM_ADDR]] to ptr diff --git a/clang/test/CodeGenHIP/hip_weak_alias.cpp b/clang/test/CodeGenHIP/hip_weak_alias.cpp index 3cc9a2bd09fc0..3484d7f550056 100644 --- a/clang/test/CodeGenHIP/hip_weak_alias.cpp +++ b/clang/test/CodeGenHIP/hip_weak_alias.cpp @@ -9,6 +9,9 @@ extern "C" { //. +// HOST: @__HostVar = global i32 1, align 4 +// HOST: @__hip_cuid_ = global i8 0 +// HOST: @llvm.compiler.used = appending global [1 x ptr] [ptr @__hip_cuid_], section "llvm.metadata" // HOST: @HostFunc = weak alias i32 (), ptr @__HostFunc // HOST: @HostFunc_ = alias i32 (), ptr @__HostFunc // HOST: @HostVar = weak alias i32, ptr @__HostVar @@ -20,6 +23,8 @@ extern "C" { // HOST: @_Z4Fourv = weak alias i32 (), ptr @_Z6__Fourv // HOST: @_Z4Fourf = weak alias float (float), ptr @_Z6__Fourf //. +// DEVICE: @__hip_cuid_ = addrspace(1) global i8 0 +// DEVICE: @llvm.compiler.used = appending addrspace(1) global [1 x ptr] [ptr addrspacecast (ptr addrspace(1) @__hip_cuid_ to ptr)], section "llvm.metadata" // DEVICE: @One = weak alias i32 (), ptr @__One // DEVICE: @One_ = alias i32 (), ptr @__One // DEVICE: @Two = weak alias i32 (), ptr @__Two @@ -44,8 +49,6 @@ extern int __attribute__((alias("__HostVar"))) HostVar_; // DEVICE-LABEL: define dso_local i32 @__One( // DEVICE-SAME: ) #[[ATTR0:[0-9]+]] { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: ret i32 1 // __device__ int __One(void) { return 1; } @@ -60,8 +63,6 @@ __device__ int One_(void) __attribute__((alias("__One"))); // DEVICE-LABEL: define dso_local i32 @__Two( // DEVICE-SAME: ) #[[ATTR0]] { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: ret i32 2 // __host__ __device__ int __Two(void) { return 2; } @@ -77,8 +78,6 @@ __host__ __device__ int Two_(void) __attribute__((alias("__Two"))); // DEVICE-LABEL: define linkonce_odr noundef i32 @_Z7__Threev( // DEVICE-SAME: ) #[[ATTR0]] comdat { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: ret i32 5 // __host__ __device__ constexpr int __Three(void) { return 5; } @@ -94,8 +93,6 @@ __host__ __device__ int Three_(void) __attribute__((alias("_Z7__Threev"))); // DEVICE-LABEL: define dso_local noundef i32 @_Z6__Fourv( // DEVICE-SAME: ) #[[ATTR0]] { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: ret i32 2 // __host__ __device__ int __Four(void) { return 2; } @@ -111,9 +108,7 @@ __host__ __device__ int __Four(void) { return 2; } // DEVICE-LABEL: define dso_local noundef float @_Z6__Fourf( // DEVICE-SAME: float noundef [[F:%.*]]) #[[ATTR0]] { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // DEVICE-NEXT: [[F_ADDR:%.*]] = alloca float, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: [[F_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F_ADDR]] to ptr // DEVICE-NEXT: store float [[F]], ptr [[F_ADDR_ASCAST]], align 4 // DEVICE-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR_ASCAST]], align 4 @@ -123,3 +118,16 @@ __host__ __device__ int __Four(void) { return 2; } __host__ __device__ float __Four(float f) { return 2.0f * f; } __host__ __device__ int Four(void) __attribute__((weak, alias("_Z6__Fourv"))); __host__ __device__ float Four(float f) __attribute__((weak, alias("_Z6__Fourf"))); +//. +// HOST: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } +//. +// DEVICE: attributes #[[ATTR0]] = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +//. +// HOST: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// HOST: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. +// DEVICE: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// DEVICE: [[META1:![0-9]+]] = !{i32 1, !"amdgpu_printf_kind", !"hostcall"} +// DEVICE: [[META2:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// DEVICE: [[META3:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/CodeGenHIP/printf.cpp b/clang/test/CodeGenHIP/printf.cpp index 2d814d6fdc704..2dc08aa1e5dd9 100644 --- a/clang/test/CodeGenHIP/printf.cpp +++ b/clang/test/CodeGenHIP/printf.cpp @@ -12,9 +12,7 @@ extern "C" __device__ int printf(const char *format, ...); // AMDGCN-LABEL: define dso_local noundef i32 @_Z4foo1v( // AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] { // AMDGCN-NEXT: [[ENTRY:.*]]: -// AMDGCN-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGCN-NEXT: [[S:%.*]] = alloca ptr, align 8, addrspace(5) -// AMDGCN-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN-NEXT: [[S_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S]] to ptr // AMDGCN-NEXT: store ptr addrspacecast (ptr addrspace(4) @.str to ptr), ptr [[S_ASCAST]], align 8 // AMDGCN-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ASCAST]], align 8 @@ -65,9 +63,7 @@ extern "C" __device__ int printf(const char *format, ...); // AMDGCNSPIRV-LABEL: define spir_func noundef i32 @_Z4foo1v( // AMDGCNSPIRV-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: -// AMDGCNSPIRV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // AMDGCNSPIRV-NEXT: [[S:%.*]] = alloca ptr addrspace(4), align 8 -// AMDGCNSPIRV-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) // AMDGCNSPIRV-NEXT: [[S_ASCAST:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(4) // AMDGCNSPIRV-NEXT: store ptr addrspace(4) addrspacecast (ptr addrspace(1) @.str to ptr addrspace(4)), ptr addrspace(4) [[S_ASCAST]], align 8 // AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[S_ASCAST]], align 8 @@ -125,8 +121,6 @@ __device__ char *dstr; // AMDGCN-LABEL: define dso_local noundef i32 @_Z4foo2v( // AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] { // AMDGCN-NEXT: [[ENTRY:.*]]: -// AMDGCN-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGCN-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN-NEXT: [[TMP0:%.*]] = load ptr, ptr addrspacecast (ptr addrspace(1) @dstr to ptr), align 8 // AMDGCN-NEXT: [[TMP1:%.*]] = load ptr, ptr addrspacecast (ptr addrspace(1) @dstr to ptr), align 8 // AMDGCN-NEXT: [[TMP2:%.*]] = call i64 @__ockl_printf_begin(i64 0) @@ -171,8 +165,6 @@ __device__ char *dstr; // AMDGCNSPIRV-LABEL: define spir_func noundef i32 @_Z4foo2v( // AMDGCNSPIRV-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] { // AMDGCNSPIRV-NEXT: [[ENTRY:.*]]: -// AMDGCNSPIRV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// AMDGCNSPIRV-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) // AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr addrspace(4) addrspacecast (ptr addrspace(1) @dstr to ptr addrspace(4)), align 8 // AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = load ptr addrspace(4), ptr addrspace(4) addrspacecast (ptr addrspace(1) @dstr to ptr addrspace(4)), align 8 // AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = call addrspace(4) i64 @__ockl_printf_begin(i64 0) diff --git a/clang/test/CodeGenHIP/printf_nonhostcall.cpp b/clang/test/CodeGenHIP/printf_nonhostcall.cpp index 1982eb864e2a4..a05b8166eda8a 100644 --- a/clang/test/CodeGenHIP/printf_nonhostcall.cpp +++ b/clang/test/CodeGenHIP/printf_nonhostcall.cpp @@ -13,9 +13,7 @@ extern "C" __device__ int printf(const char *format, ...); // CHECK-LABEL: define dso_local noundef i32 @_Z4foo1v // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[S:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[S_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S]] to ptr // CHECK-NEXT: store ptr addrspacecast (ptr addrspace(4) @.str to ptr), ptr [[S_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ASCAST]], align 8 @@ -70,9 +68,7 @@ extern "C" __device__ int printf(const char *format, ...); // // CHECK_CONSTRAINED-LABEL: define dso_local noundef i32 @_Z4foo1v // CHECK_CONSTRAINED-NEXT: entry: -// CHECK_CONSTRAINED-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK_CONSTRAINED-NEXT: [[S:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK_CONSTRAINED-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK_CONSTRAINED-NEXT: [[S_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S]] to ptr // CHECK_CONSTRAINED-NEXT: store ptr addrspacecast (ptr addrspace(4) @.str to ptr), ptr [[S_ASCAST]], align 8 // CHECK_CONSTRAINED-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ASCAST]], align 8 @@ -134,9 +130,7 @@ __device__ char *dstr; __device__ const // CHECK-LABEL: define dso_local noundef i32 @_Z4foo2v // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[LCVAL:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[LCVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[LCVAL]] to ptr // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr addrspacecast (ptr addrspace(1) @dstr to ptr), align 8 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr addrspacecast (ptr addrspace(1) @dstr to ptr), align 8 @@ -186,9 +180,7 @@ __device__ const // // CHECK_CONSTRAINED-LABEL: define dso_local noundef i32 @_Z4foo2v // CHECK_CONSTRAINED-NEXT: entry: -// CHECK_CONSTRAINED-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK_CONSTRAINED-NEXT: [[LCVAL:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK_CONSTRAINED-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK_CONSTRAINED-NEXT: [[LCVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[LCVAL]] to ptr // CHECK_CONSTRAINED-NEXT: [[TMP0:%.*]] = load ptr, ptr addrspacecast (ptr addrspace(1) @dstr to ptr), align 8 // CHECK_CONSTRAINED-NEXT: [[TMP1:%.*]] = load ptr, ptr addrspacecast (ptr addrspace(1) @dstr to ptr), align 8 @@ -255,8 +247,6 @@ __device__ _BitInt(128) Int128 = 45637; // CHECK-LABEL: define dso_local noundef i32 @_Z4foo3v // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: store i32 25, ptr addrspacecast (ptr addrspace(3) @_ZZ4foo3vE1s to ptr), align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspacecast (ptr addrspace(3) @_ZZ4foo3vE1s to ptr), align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr addrspacecast (ptr addrspace(1) @g to ptr), align 2 @@ -316,8 +306,6 @@ __device__ _BitInt(128) Int128 = 45637; // // CHECK_CONSTRAINED-LABEL: define dso_local noundef i32 @_Z4foo3v // CHECK_CONSTRAINED-NEXT: entry: -// CHECK_CONSTRAINED-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK_CONSTRAINED-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK_CONSTRAINED-NEXT: store i32 25, ptr addrspacecast (ptr addrspace(3) @_ZZ4foo3vE1s to ptr), align 4 // CHECK_CONSTRAINED-NEXT: [[TMP0:%.*]] = load i32, ptr addrspacecast (ptr addrspace(3) @_ZZ4foo3vE1s to ptr), align 4 // CHECK_CONSTRAINED-NEXT: [[TMP1:%.*]] = load i16, ptr addrspacecast (ptr addrspace(1) @g to ptr), align 2 @@ -384,9 +372,7 @@ __device__ int foo3() { //A non trivial case, // CHECK-LABEL: define dso_local noundef i32 @_Z4foo4v // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[S:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[S_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S]] to ptr // CHECK-NEXT: store ptr addrspacecast (ptr addrspace(4) @.str.4 to ptr), ptr [[S_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ASCAST]], align 8 @@ -429,9 +415,7 @@ __device__ int foo3() { // // CHECK_CONSTRAINED-LABEL: define dso_local noundef i32 @_Z4foo4v // CHECK_CONSTRAINED-NEXT: entry: -// CHECK_CONSTRAINED-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK_CONSTRAINED-NEXT: [[S:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK_CONSTRAINED-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK_CONSTRAINED-NEXT: [[S_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S]] to ptr // CHECK_CONSTRAINED-NEXT: store ptr addrspacecast (ptr addrspace(4) @.str.4 to ptr), ptr [[S_ASCAST]], align 8 // CHECK_CONSTRAINED-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ASCAST]], align 8 diff --git a/clang/test/CodeGenHIP/sanitize-undefined-null.hip b/clang/test/CodeGenHIP/sanitize-undefined-null.hip index 9418b125f9955..229507129d0ff 100644 --- a/clang/test/CodeGenHIP/sanitize-undefined-null.hip +++ b/clang/test/CodeGenHIP/sanitize-undefined-null.hip @@ -14,9 +14,7 @@ //. // CHECK-LABEL: @_Z3fooPc( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[P_ADDR]] to ptr // CHECK-NEXT: store ptr [[P:%.*]], ptr [[P_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[P_ADDR_ASCAST]], align 8 diff --git a/clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp b/clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp index 8226a109d8b8d..a1a351b578fc0 100644 --- a/clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp +++ b/clang/test/CodeGenHIP/spirv-amdgcn-ballot.cpp @@ -12,9 +12,7 @@ // CHECK-LABEL: define spir_func noundef i64 @_Z3fooi( // CHECK-SAME: i32 noundef [[P:%.*]]) addrspace(4) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i64, align 8 // CHECK-NEXT: [[P_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) // CHECK-NEXT: [[P_ADDR_ASCAST:%.*]] = addrspacecast ptr [[P_ADDR]] to ptr addrspace(4) // CHECK-NEXT: store i32 [[P]], ptr addrspace(4) [[P_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(4) [[P_ADDR_ASCAST]], align 4 diff --git a/clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl index 3bd7636212862..f48edc19b86f7 100644 --- a/clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl +++ b/clang/test/CodeGenHLSL/BasicFeatures/MatrixElementTypeCast.hlsl @@ -5,8 +5,8 @@ // CHECK-LABEL: define hidden noundef <6 x i32> @_Z22elementwise_type_cast0u11matrix_typeILm3ELm2EfE( // CHECK-SAME: <6 x float> noundef nofpclass(nan inf) [[F32:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[F32_ADDR:%.*]] = alloca [6 x float], align 4 -// CHECK-NEXT: [[I32:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[F32_ADDR:%.*]] = alloca [3 x <2 x float>], align 4 +// CHECK-NEXT: [[I32:%.*]] = alloca [3 x <2 x i32>], align 4 // CHECK-NEXT: store <6 x float> [[F32]], ptr [[F32_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <6 x float>, ptr [[F32_ADDR]], align 4 // CHECK-NEXT: [[CONV:%.*]] = fptosi <6 x float> [[TMP0]] to <6 x i32> @@ -22,8 +22,8 @@ int3x2 elementwise_type_cast0(float3x2 f32) { // CHECK-LABEL: define hidden noundef <6 x i32> @_Z22elementwise_type_cast1u11matrix_typeILm3ELm2EsE( // CHECK-SAME: <6 x i16> noundef [[I16_32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I16_32_ADDR:%.*]] = alloca [6 x i16], align 2 -// CHECK-NEXT: [[I32:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[I16_32_ADDR:%.*]] = alloca [3 x <2 x i16>], align 2 +// CHECK-NEXT: [[I32:%.*]] = alloca [3 x <2 x i32>], align 4 // CHECK-NEXT: store <6 x i16> [[I16_32]], ptr [[I16_32_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load <6 x i16>, ptr [[I16_32_ADDR]], align 2 // CHECK-NEXT: [[CONV:%.*]] = sext <6 x i16> [[TMP0]] to <6 x i32> @@ -39,8 +39,8 @@ int3x2 elementwise_type_cast1(int16_t3x2 i16_32) { // CHECK-LABEL: define hidden noundef <6 x i32> @_Z22elementwise_type_cast2u11matrix_typeILm3ELm2ElE( // CHECK-SAME: <6 x i64> noundef [[I64_32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I64_32_ADDR:%.*]] = alloca [6 x i64], align 8 -// CHECK-NEXT: [[I32:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[I64_32_ADDR:%.*]] = alloca [3 x <2 x i64>], align 8 +// CHECK-NEXT: [[I32:%.*]] = alloca [3 x <2 x i32>], align 4 // CHECK-NEXT: store <6 x i64> [[I64_32]], ptr [[I64_32_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load <6 x i64>, ptr [[I64_32_ADDR]], align 8 // CHECK-NEXT: [[CONV:%.*]] = trunc <6 x i64> [[TMP0]] to <6 x i32> @@ -56,8 +56,8 @@ int3x2 elementwise_type_cast2(int64_t3x2 i64_32) { // CHECK-LABEL: define hidden noundef <6 x i16> @_Z22elementwise_type_cast3u11matrix_typeILm2ELm3EDhE( // CHECK-SAME: <6 x half> noundef nofpclass(nan inf) [[H23:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[H23_ADDR:%.*]] = alloca [6 x half], align 2 -// CHECK-NEXT: [[I23:%.*]] = alloca [6 x i16], align 2 +// CHECK-NEXT: [[H23_ADDR:%.*]] = alloca [2 x <3 x half>], align 2 +// CHECK-NEXT: [[I23:%.*]] = alloca [2 x <3 x i16>], align 2 // CHECK-NEXT: store <6 x half> [[H23]], ptr [[H23_ADDR]], align 2 // CHECK-NEXT: [[TMP0:%.*]] = load <6 x half>, ptr [[H23_ADDR]], align 2 // CHECK-NEXT: [[CONV:%.*]] = fptosi <6 x half> [[TMP0]] to <6 x i16> @@ -73,8 +73,8 @@ int16_t2x3 elementwise_type_cast3(half2x3 h23) { // CHECK-LABEL: define hidden noundef <6 x i32> @_Z22elementwise_type_cast4u11matrix_typeILm3ELm2EdE( // CHECK-SAME: <6 x double> noundef nofpclass(nan inf) [[D32:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[D32_ADDR:%.*]] = alloca [6 x double], align 8 -// CHECK-NEXT: [[I32:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[D32_ADDR:%.*]] = alloca [3 x <2 x double>], align 8 +// CHECK-NEXT: [[I32:%.*]] = alloca [3 x <2 x i32>], align 4 // CHECK-NEXT: store <6 x double> [[D32]], ptr [[D32_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load <6 x double>, ptr [[D32_ADDR]], align 8 // CHECK-NEXT: [[CONV:%.*]] = fptosi <6 x double> [[TMP0]] to <6 x i32> @@ -91,7 +91,7 @@ int3x2 elementwise_type_cast4(double3x2 d32) { // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[A:%.*]] = alloca [2 x [1 x i32]], align 4 -// CHECK-NEXT: [[B:%.*]] = alloca [2 x i32], align 4 +// CHECK-NEXT: [[B:%.*]] = alloca [2 x <1 x i32>], align 4 // CHECK-NEXT: [[AGG_TEMP:%.*]] = alloca [2 x [1 x i32]], align 4 // CHECK-NEXT: [[FLATCAST_TMP:%.*]] = alloca <2 x i32>, align 4 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[A]], ptr align 4 @__const._Z5call2v.A, i32 8, i1 false) @@ -120,7 +120,7 @@ struct S { // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 1 -// CHECK-NEXT: [[A:%.*]] = alloca [2 x i32], align 4 +// CHECK-NEXT: [[A:%.*]] = alloca [2 x <1 x i32>], align 4 // CHECK-NEXT: [[AGG_TEMP:%.*]] = alloca [[STRUCT_S]], align 1 // CHECK-NEXT: [[FLATCAST_TMP:%.*]] = alloca <2 x i32>, align 4 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[S]], ptr align 1 @__const._Z5call3v.s, i32 8, i1 false) @@ -155,7 +155,7 @@ struct Derived : BFields { // CHECK-LABEL: define hidden void @_Z5call47Derived( // CHECK-SAME: ptr noundef byval([[STRUCT_DERIVED:%.*]]) align 1 [[D:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[A:%.*]] = alloca [4 x i32], align 4 +// CHECK-NEXT: [[A:%.*]] = alloca [2 x <2 x i32>], align 4 // CHECK-NEXT: [[AGG_TEMP:%.*]] = alloca [[STRUCT_DERIVED]], align 1 // CHECK-NEXT: [[FLATCAST_TMP:%.*]] = alloca <4 x i32>, align 4 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[AGG_TEMP]], ptr align 1 [[D]], i32 19, i1 false) @@ -189,7 +189,7 @@ void call4(Derived D) { // CHECK-SAME: <4 x float> noundef nofpclass(nan inf) [[V:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x float>, align 16 -// CHECK-NEXT: [[M:%.*]] = alloca [4 x float], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [2 x <2 x float>], align 4 // CHECK-NEXT: [[HLSL_EWCAST_SRC:%.*]] = alloca <4 x float>, align 16 // CHECK-NEXT: [[FLATCAST_TMP:%.*]] = alloca <4 x float>, align 4 // CHECK-NEXT: store <4 x float> [[V]], ptr [[V_ADDR]], align 16 diff --git a/clang/test/CodeGenHLSL/BasicFeatures/MatrixExplicitTruncation.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/MatrixExplicitTruncation.hlsl index f3c4bc496d5a4..56f816806d63f 100644 --- a/clang/test/CodeGenHLSL/BasicFeatures/MatrixExplicitTruncation.hlsl +++ b/clang/test/CodeGenHLSL/BasicFeatures/MatrixExplicitTruncation.hlsl @@ -4,8 +4,8 @@ // CHECK-LABEL: define hidden noundef <12 x i32> @_Z10trunc_castu11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I34:%.*]] = alloca [12 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I34:%.*]] = alloca [3 x <4 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <12 x i32> @@ -21,8 +21,8 @@ // CHECK-LABEL: define hidden noundef <12 x i32> @_Z11trunc_cast0u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I43:%.*]] = alloca [12 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I43:%.*]] = alloca [4 x <3 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <12 x i32> @@ -38,8 +38,8 @@ // CHECK-LABEL: define hidden noundef <9 x i32> @_Z11trunc_cast1u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I33:%.*]] = alloca [9 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I33:%.*]] = alloca [3 x <3 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <9 x i32> @@ -55,8 +55,8 @@ // CHECK-LABEL: define hidden noundef <6 x i32> @_Z11trunc_cast2u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I32:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I32:%.*]] = alloca [3 x <2 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <6 x i32> @@ -72,8 +72,8 @@ // CHECK-LABEL: define hidden noundef <6 x i32> @_Z11trunc_cast3u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I23:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I23:%.*]] = alloca [2 x <3 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <6 x i32> @@ -89,8 +89,8 @@ // CHECK-LABEL: define hidden noundef <4 x i32> @_Z11trunc_cast4u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I22:%.*]] = alloca [4 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I22:%.*]] = alloca [2 x <2 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> @@ -106,8 +106,8 @@ // CHECK-LABEL: define hidden noundef <2 x i32> @_Z11trunc_cast5u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I21:%.*]] = alloca [2 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I21:%.*]] = alloca [2 x <1 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <2 x i32> @@ -123,7 +123,7 @@ // CHECK-LABEL: define hidden noundef i32 @_Z11trunc_cast6u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: [[I1:%.*]] = alloca i32, align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 @@ -140,7 +140,7 @@ // CHECK-LABEL: define hidden noundef i32 @_Z16trunc_multi_castu11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: [[I1:%.*]] = alloca i32, align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 diff --git a/clang/test/CodeGenHLSL/BasicFeatures/MatrixImplicitTruncation.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/MatrixImplicitTruncation.hlsl index e621f68623bd1..b58f567eb51d3 100644 --- a/clang/test/CodeGenHLSL/BasicFeatures/MatrixImplicitTruncation.hlsl +++ b/clang/test/CodeGenHLSL/BasicFeatures/MatrixImplicitTruncation.hlsl @@ -4,8 +4,8 @@ // CHECK-LABEL: define hidden noundef <12 x i32> @_Z10trunc_castu11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I34:%.*]] = alloca [12 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I34:%.*]] = alloca [3 x <4 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <12 x i32> @@ -21,8 +21,8 @@ // CHECK-LABEL: define hidden noundef <12 x i32> @_Z11trunc_cast0u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I43:%.*]] = alloca [12 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I43:%.*]] = alloca [4 x <3 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <12 x i32> @@ -38,8 +38,8 @@ // CHECK-LABEL: define hidden noundef <9 x i32> @_Z11trunc_cast1u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I33:%.*]] = alloca [9 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I33:%.*]] = alloca [3 x <3 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <9 x i32> @@ -55,8 +55,8 @@ // CHECK-LABEL: define hidden noundef <6 x i32> @_Z11trunc_cast2u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I32:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I32:%.*]] = alloca [3 x <2 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <6 x i32> @@ -72,8 +72,8 @@ // CHECK-LABEL: define hidden noundef <6 x i32> @_Z11trunc_cast3u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I23:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I23:%.*]] = alloca [2 x <3 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <6 x i32> @@ -89,8 +89,8 @@ // CHECK-LABEL: define hidden noundef <4 x i32> @_Z11trunc_cast4u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I22:%.*]] = alloca [4 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I22:%.*]] = alloca [2 x <2 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> @@ -106,8 +106,8 @@ // CHECK-LABEL: define hidden noundef <2 x i32> @_Z11trunc_cast5u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 -// CHECK-NEXT: [[I21:%.*]] = alloca [2 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: [[I21:%.*]] = alloca [2 x <1 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <2 x i32> @@ -123,7 +123,7 @@ // CHECK-LABEL: define hidden noundef i32 @_Z11trunc_cast6u11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: [[I1:%.*]] = alloca i32, align 4 // CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 diff --git a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptConstSwizzle.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptConstSwizzle.hlsl index 02885d153697a..2b950d8a51a38 100644 --- a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptConstSwizzle.hlsl +++ b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptConstSwizzle.hlsl @@ -108,7 +108,7 @@ void setVectorOnMatrixSwizzle(out int2x3 M, int3 V) { // CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(24) [[M:%.*]], <6 x i32> noundef [[N:%.*]], i32 noundef [[MINDEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 4 -// CHECK-NEXT: [[N_ADDR:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca [2 x <3 x i32>], align 4 // CHECK-NEXT: [[MINDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store <6 x i32> [[N]], ptr [[N_ADDR]], align 4 @@ -139,7 +139,7 @@ void setMatrixFromMatrix(out int2x3 M, int2x3 N, int MIndex) { // CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(24) [[M:%.*]], <6 x i32> noundef [[N:%.*]], i32 noundef [[NINDEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 4 -// CHECK-NEXT: [[N_ADDR:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca [2 x <3 x i32>], align 4 // CHECK-NEXT: [[NINDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store <6 x i32> [[N]], ptr [[N_ADDR]], align 4 diff --git a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptDynamicSwizzle.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptDynamicSwizzle.hlsl index 97ce63f545cff..7190b6e1148a5 100644 --- a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptDynamicSwizzle.hlsl +++ b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptDynamicSwizzle.hlsl @@ -38,7 +38,7 @@ void setMatrix(out float4x4 M, int index, float4 V) { // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <3 x float> @_Z9getMatrixu11matrix_typeILm4ELm4EfEi( // CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[M:%.*]], i32 noundef [[INDEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [16 x float], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 // CHECK-NEXT: [[INDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store <16 x float> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store i32 [[INDEX]], ptr [[INDEX_ADDR]], align 4 @@ -62,7 +62,7 @@ float3 getMatrix(float4x4 M, int index) { // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> @_Z9getMatrixu11matrix_typeILm3ELm3EfEi( // CHECK-SAME: <9 x float> noundef nofpclass(nan inf) [[M:%.*]], i32 noundef [[INDEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [9 x float], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [3 x <3 x float>], align 4 // CHECK-NEXT: [[INDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store <9 x float> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store i32 [[INDEX]], ptr [[INDEX_ADDR]], align 4 @@ -115,7 +115,7 @@ int3 getMatrixSwizzle2x3(out int2x3 M, int index) { // CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(24) [[M:%.*]], <6 x i32> noundef [[N:%.*]], i32 noundef [[INDEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 4 -// CHECK-NEXT: [[N_ADDR:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca [2 x <3 x i32>], align 4 // CHECK-NEXT: [[INDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store <6 x i32> [[N]], ptr [[N_ADDR]], align 4 diff --git a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptGetter.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptGetter.hlsl index df724d217fe6b..efa9381b515af 100644 --- a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptGetter.hlsl +++ b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptGetter.hlsl @@ -4,7 +4,7 @@ // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> @_Z24getFloatVecMatrixDynamicu11matrix_typeILm4ELm4EfEi( // CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[M:%.*]], i32 noundef [[INDEX:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [16 x float], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 // CHECK-NEXT: [[INDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store <16 x float> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store i32 [[INDEX]], ptr [[INDEX_ADDR]], align 4 @@ -31,7 +31,7 @@ float4 getFloatVecMatrixDynamic(float4x4 M, int index) { // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z27getFloatScalarMatrixDynamicu11matrix_typeILm2ELm1EfEi( // CHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[M:%.*]], i32 noundef [[INDEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [2 x float], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [2 x <1 x float>], align 4 // CHECK-NEXT: [[INDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store <2 x float> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store i32 [[INDEX]], ptr [[INDEX_ADDR]], align 4 @@ -50,7 +50,7 @@ float getFloatScalarMatrixDynamic(float2x1 M, int index) { // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z28getFloatScalarMatrixConstantu11matrix_typeILm2ELm1EfE( // CHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[M:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [2 x float], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [2 x <1 x float>], align 4 // CHECK-NEXT: store <2 x float> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[MATRIX_ELEM:%.*]] = extractelement <2 x float> [[TMP0]], i32 0 @@ -65,7 +65,7 @@ float getFloatScalarMatrixConstant(float2x1 M) { // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z29getFloatScalarMatrixConstant2u11matrix_typeILm2ELm1EfE( // CHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[M:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [2 x float], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [2 x <1 x float>], align 4 // CHECK-NEXT: store <2 x float> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[MATRIX_ELEM:%.*]] = extractelement <2 x float> [[TMP0]], i32 1 @@ -80,7 +80,7 @@ float getFloatScalarMatrixConstant2(float2x1 M) { // CHECK-LABEL: define hidden noundef <4 x i32> @_Z19getIntMatrixDynamicu11matrix_typeILm4ELm4EiEi( // CHECK-SAME: <16 x i32> noundef [[M:%.*]], i32 noundef [[INDEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: [[INDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: store <16 x i32> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store i32 [[INDEX]], ptr [[INDEX_ADDR]], align 4 @@ -107,7 +107,7 @@ int4 getIntMatrixDynamic(int4x4 M, int index) { // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> @_Z22AddFloatMatrixConstantu11matrix_typeILm4ELm4EfE( // CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[M:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [16 x float], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 // CHECK-NEXT: store <16 x float> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[MATRIX_ELEM:%.*]] = extractelement <16 x float> [[TMP0]], i32 0 @@ -157,7 +157,7 @@ float4 AddFloatMatrixConstant(float4x4 M) { // CHECK-LABEL: define hidden noundef <4 x i32> @_Z20AddIntMatrixConstantu11matrix_typeILm4ELm4EiE( // CHECK-SAME: <16 x i32> noundef [[M:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: store <16 x i32> [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[MATRIX_ELEM:%.*]] = extractelement <16 x i32> [[TMP0]], i32 0 @@ -207,7 +207,7 @@ int4 AddIntMatrixConstant(int4x4 M) { // CHECK-LABEL: define hidden noundef <3 x i1> @_Z23getBoolVecMatrixDynamicu11matrix_typeILm2ELm3EbEi( // CHECK-SAME: <6 x i1> noundef [[M:%.*]], i32 noundef [[INDEX:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [2 x <3 x i32>], align 4 // CHECK-NEXT: [[INDEX_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[TMP0:%.*]] = zext <6 x i1> [[M]] to <6 x i32> // CHECK-NEXT: store <6 x i32> [[TMP0]], ptr [[M_ADDR]], align 4 @@ -233,7 +233,7 @@ bool3 getBoolVecMatrixDynamic(bool2x3 M, int index) { // CHECK-LABEL: define hidden noundef <4 x i1> @_Z24getBoolVecMatrixConstantu11matrix_typeILm4ELm4EbE( // CHECK-SAME: <16 x i1> noundef [[M:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: [[TMP0:%.*]] = zext <16 x i1> [[M]] to <16 x i32> // CHECK-NEXT: store <16 x i32> [[TMP0]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[M_ADDR]], align 4 @@ -255,7 +255,7 @@ bool4 getBoolVecMatrixConstant(bool4x4 M) { // CHECK-LABEL: define hidden noundef i1 @_Z27getBoolScalarMatrixConstantu11matrix_typeILm3ELm1EbE( // CHECK-SAME: <3 x i1> noundef [[M:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [3 x i32], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [3 x <1 x i32>], align 4 // CHECK-NEXT: [[TMP0:%.*]] = zext <3 x i1> [[M]] to <3 x i32> // CHECK-NEXT: store <3 x i32> [[TMP0]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr [[M_ADDR]], align 4 diff --git a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptSetter.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptSetter.hlsl index 15861b3211606..ec362aa269986 100644 --- a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptSetter.hlsl +++ b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSingleSubscriptSetter.hlsl @@ -127,7 +127,7 @@ void setBoolMatrixScalar(out bool2x1 M, int index, bool S) { // CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[M:%.*]], <16 x i32> noundef [[N:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 4 -// CHECK-NEXT: [[N_ADDR:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[N_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: store <16 x i32> [[N]], ptr [[N_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[N_ADDR]], align 4 diff --git a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSplat.hlsl b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSplat.hlsl index 9b9538e0afdd1..768c1b8e02bea 100644 --- a/clang/test/CodeGenHLSL/BasicFeatures/MatrixSplat.hlsl +++ b/clang/test/CodeGenHLSL/BasicFeatures/MatrixSplat.hlsl @@ -4,7 +4,7 @@ // CHECK-LABEL: define hidden void @_Z13ConstantSplatv( // CHECK-SAME: ) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: store <16 x i32> splat (i32 1), ptr [[M]], align 4 // CHECK-NEXT: ret void // @@ -15,7 +15,7 @@ void ConstantSplat() { // CHECK-LABEL: define hidden void @_Z18ConstantFloatSplatv( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M:%.*]] = alloca [4 x float], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [2 x <2 x float>], align 4 // CHECK-NEXT: store <4 x float> splat (float 3.250000e+00), ptr [[M]], align 4 // CHECK-NEXT: ret void // @@ -26,7 +26,7 @@ void ConstantFloatSplat() { // CHECK-LABEL: define hidden void @_Z21ConstantTrueBoolSplatv( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M:%.*]] = alloca [9 x i32], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [3 x <3 x i32>], align 4 // CHECK-NEXT: store <9 x i32> splat (i32 1), ptr [[M]], align 4 // CHECK-NEXT: ret void // @@ -37,7 +37,7 @@ void ConstantTrueBoolSplat() { // CHECK-LABEL: define hidden void @_Z22ConstantFalseBoolSplatv( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M:%.*]] = alloca [9 x i32], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [3 x <3 x i32>], align 4 // CHECK-NEXT: store <9 x i32> zeroinitializer, ptr [[M]], align 4 // CHECK-NEXT: ret void // @@ -49,7 +49,7 @@ void ConstantFalseBoolSplat() { // CHECK-SAME: float noundef nofpclass(nan inf) [[VALUE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca float, align 4 -// CHECK-NEXT: [[M:%.*]] = alloca [9 x float], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [3 x <3 x float>], align 4 // CHECK-NEXT: store float [[VALUE]], ptr [[VALUE_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[VALUE_ADDR]], align 4 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <9 x float> poison, float [[TMP0]], i64 0 @@ -65,7 +65,7 @@ void DynamicSplat(float Value) { // CHECK-SAME: i1 noundef [[VALUE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[M:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[VALUE]] to i32 // CHECK-NEXT: store i32 [[STOREDV]], ptr [[VALUE_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VALUE_ADDR]], align 4 @@ -84,7 +84,7 @@ void DynamicBoolSplat(bool Value) { // CHECK-SAME: <4 x float> noundef nofpclass(nan inf) [[VALUE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca <4 x float>, align 16 -// CHECK-NEXT: [[M:%.*]] = alloca [9 x float], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [3 x <3 x float>], align 4 // CHECK-NEXT: store <4 x float> [[VALUE]], ptr [[VALUE_ADDR]], align 16 // CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, ptr [[VALUE_ADDR]], align 16 // CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <4 x float> [[TMP0]], i32 0 @@ -101,7 +101,7 @@ void CastThenSplat(float4 Value) { // CHECK-SAME: <3 x i32> noundef [[VALUE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca <3 x i32>, align 16 -// CHECK-NEXT: [[M:%.*]] = alloca [4 x i32], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [2 x <2 x i32>], align 4 // CHECK-NEXT: store <3 x i32> [[VALUE]], ptr [[VALUE_ADDR]], align 16 // CHECK-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr [[VALUE_ADDR]], align 16 // CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne <3 x i32> [[TMP0]], zeroinitializer @@ -120,7 +120,7 @@ void ExplicitIntToBoolCastThenSplat(int3 Value) { // CHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[VALUE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca <2 x float>, align 8 -// CHECK-NEXT: [[M:%.*]] = alloca [6 x i32], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [2 x <3 x i32>], align 4 // CHECK-NEXT: store <2 x float> [[VALUE]], ptr [[VALUE_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load <2 x float>, ptr [[VALUE_ADDR]], align 8 // CHECK-NEXT: [[TOBOOL:%.*]] = fcmp reassoc nnan ninf nsz arcp afn une <2 x float> [[TMP0]], zeroinitializer @@ -139,7 +139,7 @@ void ExplicitFloatToBoolCastThenSplat(float2 Value) { // CHECK-SAME: i1 noundef [[VALUE:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[M:%.*]] = alloca [6 x float], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [3 x <2 x float>], align 4 // CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[VALUE]] to i32 // CHECK-NEXT: store i32 [[STOREDV]], ptr [[VALUE_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VALUE_ADDR]], align 4 diff --git a/clang/test/CodeGenHLSL/BoolMatrix.hlsl b/clang/test/CodeGenHLSL/BoolMatrix.hlsl index 824b9656e6848..d6ac50c978405 100644 --- a/clang/test/CodeGenHLSL/BoolMatrix.hlsl +++ b/clang/test/CodeGenHLSL/BoolMatrix.hlsl @@ -11,7 +11,7 @@ struct S { // CHECK-SAME: ) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[RETVAL:%.*]] = alloca i1, align 4 -// CHECK-NEXT: [[B:%.*]] = alloca [4 x i32], align 4 +// CHECK-NEXT: [[B:%.*]] = alloca [2 x <2 x i32>], align 4 // CHECK-NEXT: store <4 x i32> splat (i32 1), ptr [[B]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[B]], align 4 // CHECK-NEXT: [[MATRIXEXT:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0 @@ -29,7 +29,7 @@ bool fn1() { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[RETVAL:%.*]] = alloca <4 x i1>, align 4 // CHECK-NEXT: [[V_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A:%.*]] = alloca [4 x i32], align 4 +// CHECK-NEXT: [[A:%.*]] = alloca [2 x <2 x i32>], align 4 // CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[V]] to i32 // CHECK-NEXT: store i32 [[STOREDV]], ptr [[V_ADDR]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 4 @@ -77,11 +77,11 @@ bool fn3() { // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[RETVAL:%.*]] = alloca i1, align 4 -// CHECK-NEXT: [[ARR:%.*]] = alloca [2 x [4 x i32]], align 4 +// CHECK-NEXT: [[ARR:%.*]] = alloca [2 x [2 x <2 x i32>]], align 4 // CHECK-NEXT: store <4 x i32> splat (i32 1), ptr [[ARR]], align 4 -// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i32 1 +// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [2 x <2 x i32>], ptr [[ARR]], i32 1 // CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[ARRAYINIT_ELEMENT]], align 4 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [4 x i32]], ptr [[ARR]], i32 0, i32 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [2 x <2 x i32>]], ptr [[ARR]], i32 0, i32 0 // CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: [[MATRIXEXT:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1 // CHECK-NEXT: store i32 [[MATRIXEXT]], ptr [[RETVAL]], align 4 @@ -96,7 +96,7 @@ bool fn4() { // CHECK-LABEL: define hidden void @_Z3fn5v( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[M:%.*]] = alloca [4 x i32], align 4 +// CHECK-NEXT: [[M:%.*]] = alloca [2 x <2 x i32>], align 4 // CHECK-NEXT: store <4 x i32> splat (i32 1), ptr [[M]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = getelementptr <4 x i32>, ptr [[M]], i32 0, i32 3 // CHECK-NEXT: store i32 0, ptr [[TMP0]], align 4 @@ -134,11 +134,11 @@ void fn6() { // CHECK-LABEL: define hidden void @_Z3fn7v( // CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ARR:%.*]] = alloca [2 x [4 x i32]], align 4 +// CHECK-NEXT: [[ARR:%.*]] = alloca [2 x [2 x <2 x i32>]], align 4 // CHECK-NEXT: store <4 x i32> splat (i32 1), ptr [[ARR]], align 4 -// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i32 1 +// CHECK-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [2 x <2 x i32>], ptr [[ARR]], i32 1 // CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[ARRAYINIT_ELEMENT]], align 4 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [4 x i32]], ptr [[ARR]], i32 0, i32 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [2 x <2 x i32>]], ptr [[ARR]], i32 0, i32 0 // CHECK-NEXT: [[TMP0:%.*]] = getelementptr <4 x i32>, ptr [[ARRAYIDX]], i32 0, i32 1 // CHECK-NEXT: store i32 0, ptr [[TMP0]], align 4 // CHECK-NEXT: ret void @@ -152,7 +152,7 @@ void fn7() { // CHECK-SAME: <16 x i1> noundef [[M:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[RETVAL:%.*]] = alloca <16 x i1>, align 4 -// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [16 x i32], align 4 +// CHECK-NEXT: [[M_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 // CHECK-NEXT: [[TMP0:%.*]] = zext <16 x i1> [[M]] to <16 x i32> // CHECK-NEXT: store <16 x i32> [[TMP0]], ptr [[M_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr [[M_ADDR]], align 4 diff --git a/clang/test/CodeGenHLSL/basic_types.hlsl b/clang/test/CodeGenHLSL/basic_types.hlsl index 677a9a8f5d1de..0aaf7a1b77797 100644 --- a/clang/test/CodeGenHLSL/basic_types.hlsl +++ b/clang/test/CodeGenHLSL/basic_types.hlsl @@ -38,22 +38,22 @@ // CHECK: @double2_Val = external hidden addrspace(2) global <2 x double>, align 16 // CHECK: @double3_Val = external hidden addrspace(2) global <3 x double>, align 32 // CHECK: @double4_Val = external hidden addrspace(2) global <4 x double>, align 32 -// CHECK: @bool1x1_Val = external hidden addrspace(2) global [1 x i32], align 4 -// CHECK: @bool1x2_Val = external hidden addrspace(2) global [2 x i32], align 4 -// CHECK: @bool1x3_Val = external hidden addrspace(2) global [3 x i32], align 4 -// CHECK: @bool1x4_Val = external hidden addrspace(2) global [4 x i32], align 4 -// CHECK: @bool2x1_Val = external hidden addrspace(2) global [2 x i32], align 4 -// CHECK: @bool2x2_Val = external hidden addrspace(2) global [4 x i32], align 4 -// CHECK: @bool2x3_Val = external hidden addrspace(2) global [6 x i32], align 4 -// CHECK: @bool2x4_Val = external hidden addrspace(2) global [8 x i32], align 4 -// CHECK: @bool3x1_Val = external hidden addrspace(2) global [3 x i32], align 4 -// CHECK: @bool3x2_Val = external hidden addrspace(2) global [6 x i32], align 4 -// CHECK: @bool3x3_Val = external hidden addrspace(2) global [9 x i32], align 4 -// CHECK: @bool3x4_Val = external hidden addrspace(2) global [12 x i32], align 4 -// CHECK: @bool4x1_Val = external hidden addrspace(2) global [4 x i32], align 4 -// CHECK: @bool4x2_Val = external hidden addrspace(2) global [8 x i32], align 4 -// CHECK: @bool4x3_Val = external hidden addrspace(2) global [12 x i32], align 4 -// CHECK: @bool4x4_Val = external hidden addrspace(2) global [16 x i32], align 4 +// CHECK: @bool1x1_Val = external hidden addrspace(2) global [1 x <1 x i32>], align 4 +// CHECK: @bool1x2_Val = external hidden addrspace(2) global [1 x <2 x i32>], align 4 +// CHECK: @bool1x3_Val = external hidden addrspace(2) global [1 x <3 x i32>], align 4 +// CHECK: @bool1x4_Val = external hidden addrspace(2) global [1 x <4 x i32>], align 4 +// CHECK: @bool2x1_Val = external hidden addrspace(2) global [2 x <1 x i32>], align 4 +// CHECK: @bool2x2_Val = external hidden addrspace(2) global [2 x <2 x i32>], align 4 +// CHECK: @bool2x3_Val = external hidden addrspace(2) global [2 x <3 x i32>], align 4 +// CHECK: @bool2x4_Val = external hidden addrspace(2) global [2 x <4 x i32>], align 4 +// CHECK: @bool3x1_Val = external hidden addrspace(2) global [3 x <1 x i32>], align 4 +// CHECK: @bool3x2_Val = external hidden addrspace(2) global [3 x <2 x i32>], align 4 +// CHECK: @bool3x3_Val = external hidden addrspace(2) global [3 x <3 x i32>], align 4 +// CHECK: @bool3x4_Val = external hidden addrspace(2) global [3 x <4 x i32>], align 4 +// CHECK: @bool4x1_Val = external hidden addrspace(2) global [4 x <1 x i32>], align 4 +// CHECK: @bool4x2_Val = external hidden addrspace(2) global [4 x <2 x i32>], align 4 +// CHECK: @bool4x3_Val = external hidden addrspace(2) global [4 x <3 x i32>], align 4 +// CHECK: @bool4x4_Val = external hidden addrspace(2) global [4 x <4 x i32>], align 4 #ifdef NAMESPACED #define TYPE_DECL(T) hlsl::T T##_Val diff --git a/clang/test/CodeGenHLSL/builtins/WavePrefixSum.hlsl b/clang/test/CodeGenHLSL/builtins/WavePrefixSum.hlsl new file mode 100644 index 0000000000000..f22aa69ba45d5 --- /dev/null +++ b/clang/test/CodeGenHLSL/builtins/WavePrefixSum.hlsl @@ -0,0 +1,46 @@ +// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ +// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \ +// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL +// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ +// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \ +// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV + +// Test basic lowering to runtime function call. + +// CHECK-LABEL: test_int +int test_int(int expr) { + // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.prefix.sum.i32([[TY]] %[[#]]) + // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.prefix.sum.i32([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WavePrefixSum(expr); +} + +// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.prefix.sum.i32([[TY]]) #[[#attr:]] +// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.prefix.sum.i32([[TY]]) #[[#attr:]] + +// CHECK-LABEL: test_uint64_t +uint64_t test_uint64_t(uint64_t expr) { + // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.prefix.sum.i64([[TY]] %[[#]]) + // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.prefix.usum.i64([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WavePrefixSum(expr); +} + +// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.prefix.usum.i64([[TY]]) #[[#attr:]] +// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.prefix.sum.i64([[TY]]) #[[#attr:]] + +// Test basic lowering to runtime function call with array and float value. + +// CHECK-LABEL: test_floatv4 +float4 test_floatv4(float4 expr) { + // CHECK-SPIRV: %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn spir_func [[TY1:.*]] @llvm.spv.wave.prefix.sum.v4f32([[TY1]] %[[#]] + // CHECK-DXIL: %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn [[TY1:.*]] @llvm.dx.wave.prefix.sum.v4f32([[TY1]] %[[#]]) + // CHECK: ret [[TY1]] %[[RET1]] + return WavePrefixSum(expr); +} + +// CHECK-DXIL: declare [[TY1]] @llvm.dx.wave.prefix.sum.v4f32([[TY1]]) #[[#attr]] +// CHECK-SPIRV: declare [[TY1]] @llvm.spv.wave.prefix.sum.v4f32([[TY1]]) #[[#attr]] + +// CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}} + diff --git a/clang/test/CodeGenHLSL/builtins/distance.hlsl b/clang/test/CodeGenHLSL/builtins/distance.hlsl index bf015415a7d2f..efe546bfdc5cf 100644 --- a/clang/test/CodeGenHLSL/builtins/distance.hlsl +++ b/clang/test/CodeGenHLSL/builtins/distance.hlsl @@ -10,14 +10,14 @@ // CHECK-SAME: half noundef nofpclass(nan inf) [[X:%.*]], half noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half [[X]], [[Y]] -// CHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.fabs.f16(half nofpclass(nan inf) [[SUB_I]]) +// CHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.fabs.f16(half nofpclass(nan inf) [[SUB_I]]) // CHECK-NEXT: ret half [[ELT_ABS_I]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z18test_distance_halfDhDh( // SPVCHECK-SAME: half noundef nofpclass(nan inf) [[X:%.*]], half noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] // SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn half [[X]], [[Y]] -// SPVCHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.fabs.f16(half nofpclass(nan inf) [[SUB_I]]) +// SPVCHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.fabs.f16(half nofpclass(nan inf) [[SUB_I]]) // SPVCHECK-NEXT: ret half [[ELT_ABS_I]] // half test_distance_half(half X, half Y) { return distance(X, Y); } @@ -27,14 +27,14 @@ half test_distance_half(half X, half Y) { return distance(X, Y); } // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> [[X]], [[Y]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v2f16(<2 x half> nofpclass(nan inf) [[SUB_I]], <2 x half> nofpclass(nan inf) [[SUB_I]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) // CHECK-NEXT: ret half [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z19test_distance_half2Dv2_DhS_( // SPVCHECK-SAME: <2 x half> noundef nofpclass(nan inf) [[X:%.*]], <2 x half> noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] // SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x half> [[X]], [[Y]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.spv.length.v2f16(<2 x half> nofpclass(nan inf) [[SUB_I]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.spv.length.v2f16(<2 x half> nofpclass(nan inf) [[SUB_I]]) // SPVCHECK-NEXT: ret half [[SPV_LENGTH_I]] // half test_distance_half2(half2 X, half2 Y) { return distance(X, Y); } @@ -44,14 +44,14 @@ half test_distance_half2(half2 X, half2 Y) { return distance(X, Y); } // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> [[X]], [[Y]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v3f16(<3 x half> nofpclass(nan inf) [[SUB_I]], <3 x half> nofpclass(nan inf) [[SUB_I]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) // CHECK-NEXT: ret half [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z19test_distance_half3Dv3_DhS_( // SPVCHECK-SAME: <3 x half> noundef nofpclass(nan inf) [[X:%.*]], <3 x half> noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] // SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x half> [[X]], [[Y]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.spv.length.v3f16(<3 x half> nofpclass(nan inf) [[SUB_I]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.spv.length.v3f16(<3 x half> nofpclass(nan inf) [[SUB_I]]) // SPVCHECK-NEXT: ret half [[SPV_LENGTH_I]] // half test_distance_half3(half3 X, half3 Y) { return distance(X, Y); } @@ -61,14 +61,14 @@ half test_distance_half3(half3 X, half3 Y) { return distance(X, Y); } // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> [[X]], [[Y]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v4f16(<4 x half> nofpclass(nan inf) [[SUB_I]], <4 x half> nofpclass(nan inf) [[SUB_I]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) // CHECK-NEXT: ret half [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z19test_distance_half4Dv4_DhS_( // SPVCHECK-SAME: <4 x half> noundef nofpclass(nan inf) [[X:%.*]], <4 x half> noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] // SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x half> [[X]], [[Y]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.spv.length.v4f16(<4 x half> nofpclass(nan inf) [[SUB_I]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.spv.length.v4f16(<4 x half> nofpclass(nan inf) [[SUB_I]]) // SPVCHECK-NEXT: ret half [[SPV_LENGTH_I]] // half test_distance_half4(half4 X, half4 Y) { return distance(X, Y); } @@ -77,14 +77,14 @@ half test_distance_half4(half4 X, half4 Y) { return distance(X, Y); } // CHECK-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn float [[X]], [[Y]] -// CHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.fabs.f32(float nofpclass(nan inf) [[SUB_I]]) +// CHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.fabs.f32(float nofpclass(nan inf) [[SUB_I]]) // CHECK-NEXT: ret float [[ELT_ABS_I]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z19test_distance_floatff( // SPVCHECK-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] // SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn float [[X]], [[Y]] -// SPVCHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.fabs.f32(float nofpclass(nan inf) [[SUB_I]]) +// SPVCHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.fabs.f32(float nofpclass(nan inf) [[SUB_I]]) // SPVCHECK-NEXT: ret float [[ELT_ABS_I]] // float test_distance_float(float X, float Y) { return distance(X, Y); } @@ -94,14 +94,14 @@ float test_distance_float(float X, float Y) { return distance(X, Y); } // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x float> [[X]], [[Y]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn float @llvm.dx.fdot.v2f32(<2 x float> nofpclass(nan inf) [[SUB_I]], <2 x float> nofpclass(nan inf) [[SUB_I]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) // CHECK-NEXT: ret float [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z20test_distance_float2Dv2_fS_( // SPVCHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[X:%.*]], <2 x float> noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] // SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <2 x float> [[X]], [[Y]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.spv.length.v2f32(<2 x float> nofpclass(nan inf) [[SUB_I]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.spv.length.v2f32(<2 x float> nofpclass(nan inf) [[SUB_I]]) // SPVCHECK-NEXT: ret float [[SPV_LENGTH_I]] // float test_distance_float2(float2 X, float2 Y) { return distance(X, Y); } @@ -111,14 +111,14 @@ float test_distance_float2(float2 X, float2 Y) { return distance(X, Y); } // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x float> [[X]], [[Y]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn float @llvm.dx.fdot.v3f32(<3 x float> nofpclass(nan inf) [[SUB_I]], <3 x float> nofpclass(nan inf) [[SUB_I]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) // CHECK-NEXT: ret float [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z20test_distance_float3Dv3_fS_( // SPVCHECK-SAME: <3 x float> noundef nofpclass(nan inf) [[X:%.*]], <3 x float> noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] // SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <3 x float> [[X]], [[Y]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.spv.length.v3f32(<3 x float> nofpclass(nan inf) [[SUB_I]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.spv.length.v3f32(<3 x float> nofpclass(nan inf) [[SUB_I]]) // SPVCHECK-NEXT: ret float [[SPV_LENGTH_I]] // float test_distance_float3(float3 X, float3 Y) { return distance(X, Y); } @@ -128,14 +128,14 @@ float test_distance_float3(float3 X, float3 Y) { return distance(X, Y); } // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x float> [[X]], [[Y]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn float @llvm.dx.fdot.v4f32(<4 x float> nofpclass(nan inf) [[SUB_I]], <4 x float> nofpclass(nan inf) [[SUB_I]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) // CHECK-NEXT: ret float [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z20test_distance_float4Dv4_fS_( // SPVCHECK-SAME: <4 x float> noundef nofpclass(nan inf) [[X:%.*]], <4 x float> noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] // SPVCHECK-NEXT: [[SUB_I:%.*]] = fsub reassoc nnan ninf nsz arcp afn <4 x float> [[X]], [[Y]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.spv.length.v4f32(<4 x float> nofpclass(nan inf) [[SUB_I]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.spv.length.v4f32(<4 x float> nofpclass(nan inf) [[SUB_I]]) // SPVCHECK-NEXT: ret float [[SPV_LENGTH_I]] // float test_distance_float4(float4 X, float4 Y) { return distance(X, Y); } diff --git a/clang/test/CodeGenHLSL/builtins/length.hlsl b/clang/test/CodeGenHLSL/builtins/length.hlsl index 95edb20dacdac..05f3fa4233ff5 100644 --- a/clang/test/CodeGenHLSL/builtins/length.hlsl +++ b/clang/test/CodeGenHLSL/builtins/length.hlsl @@ -11,13 +11,13 @@ // CHECK-LABEL: define hidden noundef nofpclass(nan inf) half @_Z16test_length_halfDh( // CHECK-SAME: half noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.fabs.f16(half nofpclass(nan inf) [[P0]]) +// CHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.fabs.f16(half nofpclass(nan inf) [[P0]]) // CHECK-NEXT: ret half [[ELT_ABS_I]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z16test_length_halfDh( // SPVCHECK-SAME: half noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.fabs.f16(half nofpclass(nan inf) [[P0]]) +// SPVCHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.fabs.f16(half nofpclass(nan inf) [[P0]]) // SPVCHECK-NEXT: ret half [[ELT_ABS_I]] // half test_length_half(half p0) @@ -29,13 +29,13 @@ half test_length_half(half p0) // CHECK-SAME: <2 x half> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v2f16(<2 x half> nofpclass(nan inf) [[P0]], <2 x half> nofpclass(nan inf) [[P0]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) // CHECK-NEXT: ret half [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z17test_length_half2Dv2_Dh( // SPVCHECK-SAME: <2 x half> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.spv.length.v2f16(<2 x half> nofpclass(nan inf) [[P0]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.spv.length.v2f16(<2 x half> nofpclass(nan inf) [[P0]]) // SPVCHECK-NEXT: ret half [[SPV_LENGTH_I]] // half test_length_half2(half2 p0) @@ -47,13 +47,13 @@ half test_length_half2(half2 p0) // CHECK-SAME: <3 x half> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v3f16(<3 x half> nofpclass(nan inf) [[P0]], <3 x half> nofpclass(nan inf) [[P0]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) // CHECK-NEXT: ret half [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z17test_length_half3Dv3_Dh( // SPVCHECK-SAME: <3 x half> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.spv.length.v3f16(<3 x half> nofpclass(nan inf) [[P0]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.spv.length.v3f16(<3 x half> nofpclass(nan inf) [[P0]]) // SPVCHECK-NEXT: ret half [[SPV_LENGTH_I]] // half test_length_half3(half3 p0) @@ -65,13 +65,13 @@ half test_length_half3(half3 p0) // CHECK-SAME: <4 x half> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn half @llvm.dx.fdot.v4f16(<4 x half> nofpclass(nan inf) [[P0]], <4 x half> nofpclass(nan inf) [[P0]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.sqrt.f16(half [[HLSL_DOT_I]]) // CHECK-NEXT: ret half [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z17test_length_half4Dv4_Dh( // SPVCHECK-SAME: <4 x half> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.spv.length.v4f16(<4 x half> nofpclass(nan inf) [[P0]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.spv.length.v4f16(<4 x half> nofpclass(nan inf) [[P0]]) // SPVCHECK-NEXT: ret half [[SPV_LENGTH_I]] // half test_length_half4(half4 p0) @@ -82,13 +82,13 @@ half test_length_half4(half4 p0) // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z17test_length_floatf( // CHECK-SAME: float noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.fabs.f32(float nofpclass(nan inf) [[P0]]) +// CHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.fabs.f32(float nofpclass(nan inf) [[P0]]) // CHECK-NEXT: ret float [[ELT_ABS_I]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z17test_length_floatf( // SPVCHECK-SAME: float noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.fabs.f32(float nofpclass(nan inf) [[P0]]) +// SPVCHECK-NEXT: [[ELT_ABS_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.fabs.f32(float nofpclass(nan inf) [[P0]]) // SPVCHECK-NEXT: ret float [[ELT_ABS_I]] // float test_length_float(float p0) @@ -100,13 +100,13 @@ float test_length_float(float p0) // CHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn float @llvm.dx.fdot.v2f32(<2 x float> nofpclass(nan inf) [[P0]], <2 x float> nofpclass(nan inf) [[P0]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) // CHECK-NEXT: ret float [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z18test_length_float2Dv2_f( // SPVCHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.spv.length.v2f32(<2 x float> nofpclass(nan inf) [[P0]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.spv.length.v2f32(<2 x float> nofpclass(nan inf) [[P0]]) // SPVCHECK-NEXT: ret float [[SPV_LENGTH_I]] // float test_length_float2(float2 p0) @@ -118,13 +118,13 @@ float test_length_float2(float2 p0) // CHECK-SAME: <3 x float> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn float @llvm.dx.fdot.v3f32(<3 x float> nofpclass(nan inf) [[P0]], <3 x float> nofpclass(nan inf) [[P0]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) // CHECK-NEXT: ret float [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z18test_length_float3Dv3_f( // SPVCHECK-SAME: <3 x float> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.spv.length.v3f32(<3 x float> nofpclass(nan inf) [[P0]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.spv.length.v3f32(<3 x float> nofpclass(nan inf) [[P0]]) // SPVCHECK-NEXT: ret float [[SPV_LENGTH_I]] // float test_length_float3(float3 p0) @@ -136,13 +136,13 @@ float test_length_float3(float3 p0) // CHECK-SAME: <4 x float> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[HLSL_DOT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn float @llvm.dx.fdot.v4f32(<4 x float> nofpclass(nan inf) [[P0]], <4 x float> nofpclass(nan inf) [[P0]]) -// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.sqrt.f32(float [[HLSL_DOT_I]]) // CHECK-NEXT: ret float [[TMP0]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z18test_length_float4Dv4_f( // SPVCHECK-SAME: <4 x float> noundef nofpclass(nan inf) [[P0:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.spv.length.v4f32(<4 x float> nofpclass(nan inf) [[P0]]) +// SPVCHECK-NEXT: [[SPV_LENGTH_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.spv.length.v4f32(<4 x float> nofpclass(nan inf) [[P0]]) // SPVCHECK-NEXT: ret float [[SPV_LENGTH_I]] // float test_length_float4(float4 p0) diff --git a/clang/test/CodeGenHLSL/builtins/max-overloads.hlsl b/clang/test/CodeGenHLSL/builtins/max-overloads.hlsl index a5ef87a822dd5..da5cd8ff37510 100644 --- a/clang/test/CodeGenHLSL/builtins/max-overloads.hlsl +++ b/clang/test/CodeGenHLSL/builtins/max-overloads.hlsl @@ -50,32 +50,32 @@ uint64_t4 test_max_ulong4_mismatch(uint64_t4 p0, uint64_t p1) { return max(p0, p // NATIVE_HALF-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> {{.*}}test_max_half4_mismatch // NATIVE_HALF: [[CONV0:%.*]] = insertelement <4 x half> poison, half %{{.*}}, i64 0 // NATIVE_HALF: [[CONV1:%.*]] = shufflevector <4 x half> [[CONV0]], <4 x half> poison, <4 x i32> zeroinitializer -// NATIVE_HALF: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x half> @llvm.maxnum.v4f16(<4 x half> %{{.*}}, <4 x half> [[CONV1]]) +// NATIVE_HALF: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x half> @llvm.maxnum.v4f16(<4 x half> %{{.*}}, <4 x half> [[CONV1]]) // NATIVE_HALF: ret <4 x half> [[MAX]] // NO_HALF-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_max_half4_mismatch // NO_HALF: [[CONV0:%.*]] = insertelement <4 x float> poison, float %{{.*}}, i64 0 // NO_HALF: [[CONV1:%.*]] = shufflevector <4 x float> [[CONV0]], <4 x float> poison, <4 x i32> zeroinitializer -// NO_HALF: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x float> @llvm.maxnum.v4f32(<4 x float> %{{.*}}, <4 x float> [[CONV1]]) +// NO_HALF: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x float> @llvm.maxnum.v4f32(<4 x float> %{{.*}}, <4 x float> [[CONV1]]) // NO_HALF: ret <4 x float> [[MAX]] half4 test_max_half4_mismatch(half4 p0, half p1) { return max(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_max_float4_mismatch // CHECK: [[CONV0:%.*]] = insertelement <4 x float> poison, float %{{.*}}, i64 0 // CHECK: [[CONV1:%.*]] = shufflevector <4 x float> [[CONV0]], <4 x float> poison, <4 x i32> zeroinitializer -// CHECK: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x float> @llvm.maxnum.v4f32(<4 x float> %{{.*}}, <4 x float> [[CONV1]]) +// CHECK: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x float> @llvm.maxnum.v4f32(<4 x float> %{{.*}}, <4 x float> [[CONV1]]) // CHECK: ret <4 x float> [[MAX]] float4 test_max_float4_mismatch(float4 p0, float p1) { return max(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x double> {{.*}}test_max_double4_mismatch // CHECK: [[CONV0:%.*]] = insertelement <4 x double> poison, double %{{.*}}, i64 0 // CHECK: [[CONV1:%.*]] = shufflevector <4 x double> [[CONV0]], <4 x double> poison, <4 x i32> zeroinitializer -// CHECK: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x double> @llvm.maxnum.v4f64(<4 x double> %{{.*}}, <4 x double> [[CONV1]]) +// CHECK: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x double> @llvm.maxnum.v4f64(<4 x double> %{{.*}}, <4 x double> [[CONV1]]) // CHECK: ret <4 x double> [[MAX]] double4 test_max_double4_mismatch(double4 p0, double p1) { return max(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x double> {{.*}}test_max_double4_mismatch2 // CHECK: [[CONV0:%.*]] = insertelement <4 x double> poison, double %{{.*}}, i64 0 // CHECK: [[CONV1:%.*]] = shufflevector <4 x double> [[CONV0]], <4 x double> poison, <4 x i32> zeroinitializer -// CHECK: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x double> @llvm.maxnum.v4f64(<4 x double> [[CONV1]], <4 x double> %{{.*}}) +// CHECK: [[MAX:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x double> @llvm.maxnum.v4f64(<4 x double> [[CONV1]], <4 x double> %{{.*}}) // CHECK: ret <4 x double> [[MAX]] double4 test_max_double4_mismatch2(double4 p0, double p1) { return max(p1, p0); } diff --git a/clang/test/CodeGenHLSL/builtins/min-overloads.hlsl b/clang/test/CodeGenHLSL/builtins/min-overloads.hlsl index c0e06b0d204b3..ee3455a07c8e1 100644 --- a/clang/test/CodeGenHLSL/builtins/min-overloads.hlsl +++ b/clang/test/CodeGenHLSL/builtins/min-overloads.hlsl @@ -50,32 +50,32 @@ uint64_t4 test_min_ulong4_mismatch(uint64_t4 p0, uint64_t p1) { return min(p0, p // NATIVE_HALF-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> {{.*}}test_min_half4_mismatch // NATIVE_HALF: [[CONV0:%.*]] = insertelement <4 x half> poison, half %{{.*}}, i64 0 // NATIVE_HALF: [[CONV1:%.*]] = shufflevector <4 x half> [[CONV0]], <4 x half> poison, <4 x i32> zeroinitializer -// NATIVE_HALF: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x half> @llvm.minnum.v4f16(<4 x half> %{{.*}}, <4 x half> [[CONV1]]) +// NATIVE_HALF: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x half> @llvm.minnum.v4f16(<4 x half> %{{.*}}, <4 x half> [[CONV1]]) // NATIVE_HALF: ret <4 x half> [[MIN]] // NO_HALF-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_min_half4_mismatch // NO_HALF: [[CONV0:%.*]] = insertelement <4 x float> poison, float %{{.*}}, i64 0 // NO_HALF: [[CONV1:%.*]] = shufflevector <4 x float> [[CONV0]], <4 x float> poison, <4 x i32> zeroinitializer -// NO_HALF: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x float> @llvm.minnum.v4f32(<4 x float> %{{.*}}, <4 x float> [[CONV1]]) +// NO_HALF: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x float> @llvm.minnum.v4f32(<4 x float> %{{.*}}, <4 x float> [[CONV1]]) // NO_HALF: ret <4 x float> [[MIN]] half4 test_min_half4_mismatch(half4 p0, half p1) { return min(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_min_float4_mismatch // CHECK: [[CONV0:%.*]] = insertelement <4 x float> poison, float %{{.*}}, i64 0 // CHECK: [[CONV1:%.*]] = shufflevector <4 x float> [[CONV0]], <4 x float> poison, <4 x i32> zeroinitializer -// CHECK: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x float> @llvm.minnum.v4f32(<4 x float> %{{.*}}, <4 x float> [[CONV1]]) +// CHECK: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x float> @llvm.minnum.v4f32(<4 x float> %{{.*}}, <4 x float> [[CONV1]]) // CHECK: ret <4 x float> [[MIN]] float4 test_min_float4_mismatch(float4 p0, float p1) { return min(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x double> {{.*}}test_min_double4_mismatch // CHECK: [[CONV0:%.*]] = insertelement <4 x double> poison, double %{{.*}}, i64 0 // CHECK: [[CONV1:%.*]] = shufflevector <4 x double> [[CONV0]], <4 x double> poison, <4 x i32> zeroinitializer -// CHECK: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x double> @llvm.minnum.v4f64(<4 x double> %{{.*}}, <4 x double> [[CONV1]]) +// CHECK: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x double> @llvm.minnum.v4f64(<4 x double> %{{.*}}, <4 x double> [[CONV1]]) // CHECK: ret <4 x double> [[MIN]] double4 test_min_double4_mismatch(double4 p0, double p1) { return min(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x double> {{.*}}test_min_double4_mismatch2 // CHECK: [[CONV0:%.*]] = insertelement <4 x double> poison, double %{{.*}}, i64 0 // CHECK: [[CONV1:%.*]] = shufflevector <4 x double> [[CONV0]], <4 x double> poison, <4 x i32> zeroinitializer -// CHECK: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x double> @llvm.minnum.v4f64(<4 x double> [[CONV1]], <4 x double> %{{.*}}) +// CHECK: [[MIN:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x double> @llvm.minnum.v4f64(<4 x double> [[CONV1]], <4 x double> %{{.*}}) // CHECK: ret <4 x double> [[MIN]] double4 test_min_double4_mismatch2(double4 p0, double p1) { return min(p1, p0); } diff --git a/clang/test/CodeGenHLSL/builtins/pow-overloads.hlsl b/clang/test/CodeGenHLSL/builtins/pow-overloads.hlsl index 0d1f3d3546a33..6a52051aefc62 100644 --- a/clang/test/CodeGenHLSL/builtins/pow-overloads.hlsl +++ b/clang/test/CodeGenHLSL/builtins/pow-overloads.hlsl @@ -5,124 +5,124 @@ // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float {{.*}}test_pow_double // CHECK: [[CONV0:%.*]] = fptrunc [[FLOATATTRS]] double %{{.*}} to float // CHECK: [[CONV1:%.*]] = fptrunc [[FLOATATTRS]] double %{{.*}} to float -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) // CHECK: ret float [[POW]] float test_pow_double(double p0, double p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <2 x float> {{.*}}test_pow_double2 // CHECK: [[CONV0:%.*]] = fptrunc [[FLOATATTRS]] <2 x double> %{{.*}} to <2 x float> // CHECK: [[CONV1:%.*]] = fptrunc [[FLOATATTRS]] <2 x double> %{{.*}} to <2 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) // CHECK: ret <2 x float> [[POW]] float2 test_pow_double2(double2 p0, double2 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <3 x float> {{.*}}test_pow_double3 // CHECK: [[CONV0:%.*]] = fptrunc [[FLOATATTRS]] <3 x double> %{{.*}} to <3 x float> // CHECK: [[CONV1:%.*]] = fptrunc [[FLOATATTRS]] <3 x double> %{{.*}} to <3 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) // CHECK: ret <3 x float> [[POW]] float3 test_pow_double3(double3 p0, double3 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_pow_double4 // CHECK: [[CONV0:%.*]] = fptrunc [[FLOATATTRS]] <4 x double> %{{.*}} to <4 x float> // CHECK: [[CONV1:%.*]] = fptrunc [[FLOATATTRS]] <4 x double> %{{.*}} to <4 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) // CHECK: ret <4 x float> [[POW]] float4 test_pow_double4(double4 p0, double4 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float {{.*}}test_pow_int // CHECK: [[CONV0:%.*]] = sitofp i32 %{{.*}} to float // CHECK: [[CONV1:%.*]] = sitofp i32 %{{.*}} to float -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) // CHECK: ret float [[POW]] float test_pow_int(int p0, int p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <2 x float> {{.*}}test_pow_int2 // CHECK: [[CONV0:%.*]] = sitofp <2 x i32> %{{.*}} to <2 x float> // CHECK: [[CONV1:%.*]] = sitofp <2 x i32> %{{.*}} to <2 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) // CHECK: ret <2 x float> [[POW]] float2 test_pow_int2(int2 p0, int2 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <3 x float> {{.*}}test_pow_int3 // CHECK: [[CONV0:%.*]] = sitofp <3 x i32> %{{.*}} to <3 x float> // CHECK: [[CONV1:%.*]] = sitofp <3 x i32> %{{.*}} to <3 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) // CHECK: ret <3 x float> [[POW]] float3 test_pow_int3(int3 p0, int3 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_pow_int4 // CHECK: [[CONV0:%.*]] = sitofp <4 x i32> %{{.*}} to <4 x float> // CHECK: [[CONV1:%.*]] = sitofp <4 x i32> %{{.*}} to <4 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) // CHECK: ret <4 x float> [[POW]] float4 test_pow_int4(int4 p0, int4 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float {{.*}}test_pow_uint // CHECK: [[CONV0:%.*]] = uitofp i32 %{{.*}} to float // CHECK: [[CONV1:%.*]] = uitofp i32 %{{.*}} to float -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) // CHECK: ret float [[POW]] float test_pow_uint(uint p0, uint p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <2 x float> {{.*}}test_pow_uint2 // CHECK: [[CONV0:%.*]] = uitofp <2 x i32> %{{.*}} to <2 x float> // CHECK: [[CONV1:%.*]] = uitofp <2 x i32> %{{.*}} to <2 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) // CHECK: ret <2 x float> [[POW]] float2 test_pow_uint2(uint2 p0, uint2 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <3 x float> {{.*}}test_pow_uint3 // CHECK: [[CONV0:%.*]] = uitofp <3 x i32> %{{.*}} to <3 x float> // CHECK: [[CONV1:%.*]] = uitofp <3 x i32> %{{.*}} to <3 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) // CHECK: ret <3 x float> [[POW]] float3 test_pow_uint3(uint3 p0, uint3 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_pow_uint4 // CHECK: [[CONV0:%.*]] = uitofp <4 x i32> %{{.*}} to <4 x float> // CHECK: [[CONV1:%.*]] = uitofp <4 x i32> %{{.*}} to <4 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) // CHECK: ret <4 x float> [[POW]] float4 test_pow_uint4(uint4 p0, uint4 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float {{.*}}test_pow_int64_t // CHECK: [[CONV0:%.*]] = sitofp i64 %{{.*}} to float // CHECK: [[CONV1:%.*]] = sitofp i64 %{{.*}} to float -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) // CHECK: ret float [[POW]] float test_pow_int64_t(int64_t p0, int64_t p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <2 x float> {{.*}}test_pow_int64_t2 // CHECK: [[CONV0:%.*]] = sitofp <2 x i64> %{{.*}} to <2 x float> // CHECK: [[CONV1:%.*]] = sitofp <2 x i64> %{{.*}} to <2 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) // CHECK: ret <2 x float> [[POW]] float2 test_pow_int64_t2(int64_t2 p0, int64_t2 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <3 x float> {{.*}}test_pow_int64_t3 // CHECK: [[CONV0:%.*]] = sitofp <3 x i64> %{{.*}} to <3 x float> // CHECK: [[CONV1:%.*]] = sitofp <3 x i64> %{{.*}} to <3 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) // CHECK: ret <3 x float> [[POW]] float3 test_pow_int64_t3(int64_t3 p0, int64_t3 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_pow_int64_t4 // CHECK: [[CONV0:%.*]] = sitofp <4 x i64> %{{.*}} to <4 x float> // CHECK: [[CONV1:%.*]] = sitofp <4 x i64> %{{.*}} to <4 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) // CHECK: ret <4 x float> [[POW]] float4 test_pow_int64_t4(int64_t4 p0, int64_t4 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) float {{.*}}test_pow_uint64_t // CHECK: [[CONV0:%.*]] = uitofp i64 %{{.*}} to float // CHECK: [[CONV1:%.*]] = uitofp i64 %{{.*}} to float -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) float @llvm.pow.f32(float [[CONV0]], float [[CONV1]]) // CHECK: ret float [[POW]] float test_pow_uint64_t(uint64_t p0, uint64_t p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <2 x float> {{.*}}test_pow_uint64_t2 // CHECK: [[CONV0:%.*]] = uitofp <2 x i64> %{{.*}} to <2 x float> // CHECK: [[CONV1:%.*]] = uitofp <2 x i64> %{{.*}} to <2 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <2 x float> @llvm.pow.v2f32(<2 x float> [[CONV0]], <2 x float> [[CONV1]]) // CHECK: ret <2 x float> [[POW]] float2 test_pow_uint64_t2(uint64_t2 p0, uint64_t2 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <3 x float> {{.*}}test_pow_uint64_t3 // CHECK: [[CONV0:%.*]] = uitofp <3 x i64> %{{.*}} to <3 x float> // CHECK: [[CONV1:%.*]] = uitofp <3 x i64> %{{.*}} to <3 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <3 x float> @llvm.pow.v3f32(<3 x float> [[CONV0]], <3 x float> [[CONV1]]) // CHECK: ret <3 x float> [[POW]] float3 test_pow_uint64_t3(uint64_t3 p0, uint64_t3 p1) { return pow(p0, p1); } // CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x float> {{.*}}test_pow_uint64_t4 // CHECK: [[CONV0:%.*]] = uitofp <4 x i64> %{{.*}} to <4 x float> // CHECK: [[CONV1:%.*]] = uitofp <4 x i64> %{{.*}} to <4 x float> -// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) +// CHECK: [[POW:%.*]] = call [[FLOATATTRS]] noundef nofpclass(nan inf) <4 x float> @llvm.pow.v4f32(<4 x float> [[CONV0]], <4 x float> [[CONV1]]) // CHECK: ret <4 x float> [[POW]] float4 test_pow_uint64_t4(uint64_t4 p0, uint64_t4 p1) { return pow(p0, p1); } diff --git a/clang/test/CodeGenHLSL/builtins/reflect.hlsl b/clang/test/CodeGenHLSL/builtins/reflect.hlsl index feb5a5b2ea78f..259490afb1c78 100644 --- a/clang/test/CodeGenHLSL/builtins/reflect.hlsl +++ b/clang/test/CodeGenHLSL/builtins/reflect.hlsl @@ -42,7 +42,7 @@ half test_reflect_half(half I, half N) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <2 x half> @_Z18test_reflect_half2Dv2_DhS_( // SPVCHECK-SAME: <2 x half> noundef nofpclass(nan inf) [[I:%.*]], <2 x half> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <2 x half> @llvm.spv.reflect.v2f16(<2 x half> nofpclass(nan inf) [[I]], <2 x half> nofpclass(nan inf) [[N]]) +// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <2 x half> @llvm.spv.reflect.v2f16(<2 x half> nofpclass(nan inf) [[I]], <2 x half> nofpclass(nan inf) [[N]]) // SPVCHECK-NEXT: ret <2 x half> [[SPV_REFLECT_I]] // half2 test_reflect_half2(half2 I, half2 N) { @@ -63,7 +63,7 @@ half2 test_reflect_half2(half2 I, half2 N) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <3 x half> @_Z18test_reflect_half3Dv3_DhS_( // SPVCHECK-SAME: <3 x half> noundef nofpclass(nan inf) [[I:%.*]], <3 x half> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <3 x half> @llvm.spv.reflect.v3f16(<3 x half> nofpclass(nan inf) [[I]], <3 x half> nofpclass(nan inf) [[N]]) +// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <3 x half> @llvm.spv.reflect.v3f16(<3 x half> nofpclass(nan inf) [[I]], <3 x half> nofpclass(nan inf) [[N]]) // SPVCHECK-NEXT: ret <3 x half> [[SPV_REFLECT_I]] // half3 test_reflect_half3(half3 I, half3 N) { @@ -84,7 +84,7 @@ half3 test_reflect_half3(half3 I, half3 N) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <4 x half> @_Z18test_reflect_half4Dv4_DhS_( // SPVCHECK-SAME: <4 x half> noundef nofpclass(nan inf) [[I:%.*]], <4 x half> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <4 x half> @llvm.spv.reflect.v4f16(<4 x half> nofpclass(nan inf) [[I]], <4 x half> nofpclass(nan inf) [[N]]) +// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x half> @llvm.spv.reflect.v4f16(<4 x half> nofpclass(nan inf) [[I]], <4 x half> nofpclass(nan inf) [[N]]) // SPVCHECK-NEXT: ret <4 x half> [[SPV_REFLECT_I]] // half4 test_reflect_half4(half4 I, half4 N) { @@ -127,7 +127,7 @@ float test_reflect_float(float I, float N) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <2 x float> @_Z19test_reflect_float2Dv2_fS_( // SPVCHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[I:%.*]], <2 x float> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <2 x float> @llvm.spv.reflect.v2f32(<2 x float> nofpclass(nan inf) [[I]], <2 x float> nofpclass(nan inf) [[N]]) +// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <2 x float> @llvm.spv.reflect.v2f32(<2 x float> nofpclass(nan inf) [[I]], <2 x float> nofpclass(nan inf) [[N]]) // SPVCHECK-NEXT: ret <2 x float> [[SPV_REFLECT_I]] // float2 test_reflect_float2(float2 I, float2 N) { @@ -148,7 +148,7 @@ float2 test_reflect_float2(float2 I, float2 N) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <3 x float> @_Z19test_reflect_float3Dv3_fS_( // SPVCHECK-SAME: <3 x float> noundef nofpclass(nan inf) [[I:%.*]], <3 x float> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <3 x float> @llvm.spv.reflect.v3f32(<3 x float> nofpclass(nan inf) [[I]], <3 x float> nofpclass(nan inf) [[N]]) +// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <3 x float> @llvm.spv.reflect.v3f32(<3 x float> nofpclass(nan inf) [[I]], <3 x float> nofpclass(nan inf) [[N]]) // SPVCHECK-NEXT: ret <3 x float> [[SPV_REFLECT_I]] // float3 test_reflect_float3(float3 I, float3 N) { @@ -169,7 +169,7 @@ float3 test_reflect_float3(float3 I, float3 N) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <4 x float> @_Z19test_reflect_float4Dv4_fS_( // SPVCHECK-SAME: <4 x float> noundef nofpclass(nan inf) [[I:%.*]], <4 x float> noundef nofpclass(nan inf) [[N:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <4 x float> @llvm.spv.reflect.v4f32(<4 x float> nofpclass(nan inf) [[I]], <4 x float> nofpclass(nan inf) [[N]]) +// SPVCHECK-NEXT: [[SPV_REFLECT_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x float> @llvm.spv.reflect.v4f32(<4 x float> nofpclass(nan inf) [[I]], <4 x float> nofpclass(nan inf) [[N]]) // SPVCHECK-NEXT: ret <4 x float> [[SPV_REFLECT_I]] // float4 test_reflect_float4(float4 I, float4 N) { diff --git a/clang/test/CodeGenHLSL/builtins/refract.hlsl b/clang/test/CodeGenHLSL/builtins/refract.hlsl index ffeb2a78b2517..ecc36d5c7aadf 100644 --- a/clang/test/CodeGenHLSL/builtins/refract.hlsl +++ b/clang/test/CodeGenHLSL/builtins/refract.hlsl @@ -25,9 +25,9 @@ // CHECK: ret half [[HLSL_SELECT_I]] // // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z17test_refract_halfDhDhDh( -// SPVCHECK-SAME: half noundef nofpclass(nan inf) [[I:%.*]], half noundef nofpclass(nan inf) [[N:%.*]], half noundef nofpclass(nan inf) [[ETA:%.*]]) #[[ATTR0:[0-9]+]] +// SPVCHECK-SAME: half noundef nofpclass(nan inf) [[I:%.*]], half noundef nofpclass(nan inf) [[N:%.*]], half noundef nofpclass(nan inf) [[ETA:%.*]]) #[[ATTR0:[0-9]+]] // SPVCHECK: [[ENTRY:.*:]] -// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef half @llvm.spv.refract.f16.f16(half %{{.*}}, half %{{.*}}, half %{{.*}}) +// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.spv.refract.f16.f16(half %{{.*}}, half %{{.*}}, half %{{.*}}) // SPVCHECK: ret half [[SPV_REFRACT_I]] // half test_refract_half(half I, half N, half ETA) { @@ -57,7 +57,7 @@ half test_refract_half(half I, half N, half ETA) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <2 x half> @_Z18test_refract_half2Dv2_DhS_Dh( // SPVCHECK-SAME: <2 x half> noundef nofpclass(nan inf) [[I:%.*]], <2 x half> noundef nofpclass(nan inf) [[N:%.*]], half noundef nofpclass(nan inf) [[ETA:%.*]]) #[[ATTR0:[0-9]+]] { // SPVCHECK: [[ENTRY:.*:]] -// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <2 x half> @llvm.spv.refract.v2f16.f16(<2 x half> %{{.*}}, <2 x half> %{{.*}}, half %{{.*}}) +// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <2 x half> @llvm.spv.refract.v2f16.f16(<2 x half> %{{.*}}, <2 x half> %{{.*}}, half %{{.*}}) // SPVCHECK: ret <2 x half> [[SPV_REFRACT_I]] // half2 test_refract_half2(half2 I, half2 N, half ETA) { @@ -87,7 +87,7 @@ half2 test_refract_half2(half2 I, half2 N, half ETA) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <3 x half> @_Z18test_refract_half3Dv3_DhS_Dh( // SPVCHECK-SAME: <3 x half> noundef nofpclass(nan inf) [[I:%.*]], <3 x half> noundef nofpclass(nan inf) [[N:%.*]], half noundef nofpclass(nan inf) [[ETA:%.*]]) #[[ATTR0:[0-9]+]] { // SPVCHECK: [[ENTRY:.*:]] -// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <3 x half> @llvm.spv.refract.v3f16.f16(<3 x half> %{{.*}}, <3 x half> %{{.*}}, half %{{.*}}) +// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <3 x half> @llvm.spv.refract.v3f16.f16(<3 x half> %{{.*}}, <3 x half> %{{.*}}, half %{{.*}}) // SPVCHECK: ret <3 x half> [[SPV_REFRACT_I]] // half3 test_refract_half3(half3 I, half3 N, half ETA) { @@ -117,7 +117,7 @@ half3 test_refract_half3(half3 I, half3 N, half ETA) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <4 x half> @_Z18test_refract_half4Dv4_DhS_Dh( // SPVCHECK-SAME: <4 x half> noundef nofpclass(nan inf) [[I:%.*]], <4 x half> noundef nofpclass(nan inf) [[N:%.*]], half noundef nofpclass(nan inf) [[ETA:%.*]]) #[[ATTR0:[0-9]+]] { // SPVCHECK: [[ENTRY:.*:]] -// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x half> @llvm.spv.refract.v4f16.f16(<4 x half> %{{.*}}, <4 x half> %{{.*}}, half %{{.*}}) +// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x half> @llvm.spv.refract.v4f16.f16(<4 x half> %{{.*}}, <4 x half> %{{.*}}, half %{{.*}}) // SPVCHECK: ret <4 x half> [[SPV_REFRACT_I]] // half4 test_refract_half4(half4 I, half4 N, half ETA) { @@ -146,7 +146,7 @@ half4 test_refract_half4(half4 I, half4 N, half ETA) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z18test_refract_floatfff( // SPVCHECK-SAME: float noundef nofpclass(nan inf) [[I:%.*]], float noundef nofpclass(nan inf) [[N:%.*]], float noundef nofpclass(nan inf) [[ETA:%.*]]) #[[ATTR0:[0-9]+]] { // SPVCHECK: [[ENTRY:.*:]] -// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef float @llvm.spv.refract.f32.f32(float %{{.*}}, float %{{.*}}, float %{{.*}}) +// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.spv.refract.f32.f32(float %{{.*}}, float %{{.*}}, float %{{.*}}) // SPVCHECK: ret float [[SPV_REFRACT_I]] // float test_refract_float(float I, float N, float ETA) { @@ -176,7 +176,7 @@ float test_refract_float(float I, float N, float ETA) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <2 x float> @_Z19test_refract_float2Dv2_fS_f( // SPVCHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[I:%.*]], <2 x float> noundef nofpclass(nan inf) [[N:%.*]], float noundef nofpclass(nan inf) [[ETA:%.*]]) #[[ATTR0:[0-9]+]] { // SPVCHECK: [[ENTRY:.*:]] -// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <2 x float> @llvm.spv.refract.v2f32.f32(<2 x float> %{{.*}}, <2 x float> %{{.*}}, float %{{.*}}) +// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <2 x float> @llvm.spv.refract.v2f32.f32(<2 x float> %{{.*}}, <2 x float> %{{.*}}, float %{{.*}}) // SPVCHECK: ret <2 x float> [[SPV_REFRACT_I]] // float2 test_refract_float2(float2 I, float2 N, float ETA) { @@ -206,7 +206,7 @@ float2 test_refract_float2(float2 I, float2 N, float ETA) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <3 x float> @_Z19test_refract_float3Dv3_fS_f( // SPVCHECK-SAME: <3 x float> noundef nofpclass(nan inf) [[I:%.*]], <3 x float> noundef nofpclass(nan inf) [[N:%.*]], float noundef nofpclass(nan inf) [[ETA:%.*]]) #[[ATTR0:[0-9]+]] { // SPVCHECK: [[ENTRY:.*:]] -// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <3 x float> @llvm.spv.refract.v3f32.f32(<3 x float> %{{.*}}, <3 x float> %{{.*}}, float %{{.*}}) +// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <3 x float> @llvm.spv.refract.v3f32.f32(<3 x float> %{{.*}}, <3 x float> %{{.*}}, float %{{.*}}) // SPVCHECK: ret <3 x float> [[SPV_REFRACT_I]] // float3 test_refract_float3(float3 I, float3 N, float ETA) { @@ -236,7 +236,7 @@ float3 test_refract_float3(float3 I, float3 N, float ETA) { // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <4 x float> @_Z19test_refract_float4Dv4_fS_f( // SPVCHECK-SAME: <4 x float> noundef nofpclass(nan inf) %{{.*}}, <4 x float> noundef nofpclass(nan inf) %{{.*}}, float noundef nofpclass(nan inf) %{{.*}}) #[[ATTR0:[0-9]+]] { // SPVCHECK: [[ENTRY:.*:]] -// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef <4 x float> @llvm.spv.refract.v4f32.f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, float %{{.*}}) +// SPVCHECK: [[SPV_REFRACT_I:%.*]] = call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x float> @llvm.spv.refract.v4f32.f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, float %{{.*}}) // SPVCHECK: ret <4 x float> [[SPV_REFRACT_I]] // float4 test_refract_float4(float4 I, float4 N, float ETA) { diff --git a/clang/test/CodeGenHLSL/builtins/smoothstep.hlsl b/clang/test/CodeGenHLSL/builtins/smoothstep.hlsl index dcf9013045c07..c39261cfb7915 100644 --- a/clang/test/CodeGenHLSL/builtins/smoothstep.hlsl +++ b/clang/test/CodeGenHLSL/builtins/smoothstep.hlsl @@ -22,7 +22,7 @@ // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) half @_Z20test_smoothstep_halfDhDhDh( // SPVCHECK-SAME: half noundef nofpclass(nan inf) [[MIN:%.*]], half noundef nofpclass(nan inf) [[MAX:%.*]], half noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef half @llvm.spv.smoothstep.f16(half nofpclass(nan inf) [[MIN]], half nofpclass(nan inf) [[MAX]], half nofpclass(nan inf) [[X]]) +// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) half @llvm.spv.smoothstep.f16(half nofpclass(nan inf) [[MIN]], half nofpclass(nan inf) [[MAX]], half nofpclass(nan inf) [[X]]) // SPVCHECK-NEXT: ret half [[SPV_SMOOTHSTEP_I]] // half test_smoothstep_half(half Min, half Max, half X) { return smoothstep(Min, Max, X); } @@ -43,7 +43,7 @@ half test_smoothstep_half(half Min, half Max, half X) { return smoothstep(Min, M // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <2 x half> @_Z21test_smoothstep_half2Dv2_DhS_S_( // SPVCHECK-SAME: <2 x half> noundef nofpclass(nan inf) [[MIN:%.*]], <2 x half> noundef nofpclass(nan inf) [[MAX:%.*]], <2 x half> noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <2 x half> @llvm.spv.smoothstep.v2f16(<2 x half> nofpclass(nan inf) [[MIN]], <2 x half> nofpclass(nan inf) [[MAX]], <2 x half> nofpclass(nan inf) [[X]]) +// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <2 x half> @llvm.spv.smoothstep.v2f16(<2 x half> nofpclass(nan inf) [[MIN]], <2 x half> nofpclass(nan inf) [[MAX]], <2 x half> nofpclass(nan inf) [[X]]) // SPVCHECK-NEXT: ret <2 x half> [[SPV_SMOOTHSTEP_I]] // half2 test_smoothstep_half2(half2 Min, half2 Max, half2 X) { return smoothstep(Min, Max, X); } @@ -64,7 +64,7 @@ half2 test_smoothstep_half2(half2 Min, half2 Max, half2 X) { return smoothstep(M // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <3 x half> @_Z21test_smoothstep_half3Dv3_DhS_S_( // SPVCHECK-SAME: <3 x half> noundef nofpclass(nan inf) [[MIN:%.*]], <3 x half> noundef nofpclass(nan inf) [[MAX:%.*]], <3 x half> noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <3 x half> @llvm.spv.smoothstep.v3f16(<3 x half> nofpclass(nan inf) [[MIN]], <3 x half> nofpclass(nan inf) [[MAX]], <3 x half> nofpclass(nan inf) [[X]]) +// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <3 x half> @llvm.spv.smoothstep.v3f16(<3 x half> nofpclass(nan inf) [[MIN]], <3 x half> nofpclass(nan inf) [[MAX]], <3 x half> nofpclass(nan inf) [[X]]) // SPVCHECK-NEXT: ret <3 x half> [[SPV_SMOOTHSTEP_I]] // half3 test_smoothstep_half3(half3 Min, half3 Max, half3 X) { return smoothstep(Min, Max, X); } @@ -85,7 +85,7 @@ half3 test_smoothstep_half3(half3 Min, half3 Max, half3 X) { return smoothstep(M // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <4 x half> @_Z21test_smoothstep_half4Dv4_DhS_S_( // SPVCHECK-SAME: <4 x half> noundef nofpclass(nan inf) [[MIN:%.*]], <4 x half> noundef nofpclass(nan inf) [[MAX:%.*]], <4 x half> noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <4 x half> @llvm.spv.smoothstep.v4f16(<4 x half> nofpclass(nan inf) [[MIN]], <4 x half> nofpclass(nan inf) [[MAX]], <4 x half> nofpclass(nan inf) [[X]]) +// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x half> @llvm.spv.smoothstep.v4f16(<4 x half> nofpclass(nan inf) [[MIN]], <4 x half> nofpclass(nan inf) [[MAX]], <4 x half> nofpclass(nan inf) [[X]]) // SPVCHECK-NEXT: ret <4 x half> [[SPV_SMOOTHSTEP_I]] // half4 test_smoothstep_half4(half4 Min, half4 Max, half4 X) { return smoothstep(Min, Max, X); } @@ -106,7 +106,7 @@ half4 test_smoothstep_half4(half4 Min, half4 Max, half4 X) { return smoothstep(M // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) float @_Z21test_smoothstep_floatfff( // SPVCHECK-SAME: float noundef nofpclass(nan inf) [[MIN:%.*]], float noundef nofpclass(nan inf) [[MAX:%.*]], float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef float @llvm.spv.smoothstep.f32(float nofpclass(nan inf) [[MIN]], float nofpclass(nan inf) [[MAX]], float nofpclass(nan inf) [[X]]) +// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) float @llvm.spv.smoothstep.f32(float nofpclass(nan inf) [[MIN]], float nofpclass(nan inf) [[MAX]], float nofpclass(nan inf) [[X]]) // SPVCHECK-NEXT: ret float [[SPV_SMOOTHSTEP_I]] // float test_smoothstep_float(float Min, float Max, float X) { return smoothstep(Min, Max, X); } @@ -127,7 +127,7 @@ float test_smoothstep_float(float Min, float Max, float X) { return smoothstep(M // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <2 x float> @_Z22test_smoothstep_float2Dv2_fS_S_( // SPVCHECK-SAME: <2 x float> noundef nofpclass(nan inf) [[MIN:%.*]], <2 x float> noundef nofpclass(nan inf) [[MAX:%.*]], <2 x float> noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <2 x float> @llvm.spv.smoothstep.v2f32(<2 x float> nofpclass(nan inf) [[MIN]], <2 x float> nofpclass(nan inf) [[MAX]], <2 x float> nofpclass(nan inf) [[X]]) +// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <2 x float> @llvm.spv.smoothstep.v2f32(<2 x float> nofpclass(nan inf) [[MIN]], <2 x float> nofpclass(nan inf) [[MAX]], <2 x float> nofpclass(nan inf) [[X]]) // SPVCHECK-NEXT: ret <2 x float> [[SPV_SMOOTHSTEP_I]] // float2 test_smoothstep_float2(float2 Min, float2 Max, float2 X) { return smoothstep(Min, Max, X); } @@ -148,7 +148,7 @@ float2 test_smoothstep_float2(float2 Min, float2 Max, float2 X) { return smooths // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <3 x float> @_Z22test_smoothstep_float3Dv3_fS_S_( // SPVCHECK-SAME: <3 x float> noundef nofpclass(nan inf) [[MIN:%.*]], <3 x float> noundef nofpclass(nan inf) [[MAX:%.*]], <3 x float> noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <3 x float> @llvm.spv.smoothstep.v3f32(<3 x float> nofpclass(nan inf) [[MIN]], <3 x float> nofpclass(nan inf) [[MAX]], <3 x float> nofpclass(nan inf) [[X]]) +// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <3 x float> @llvm.spv.smoothstep.v3f32(<3 x float> nofpclass(nan inf) [[MIN]], <3 x float> nofpclass(nan inf) [[MAX]], <3 x float> nofpclass(nan inf) [[X]]) // SPVCHECK-NEXT: ret <3 x float> [[SPV_SMOOTHSTEP_I]] // float3 test_smoothstep_float3(float3 Min, float3 Max, float3 X) { return smoothstep(Min, Max, X); } @@ -169,7 +169,7 @@ float3 test_smoothstep_float3(float3 Min, float3 Max, float3 X) { return smooths // SPVCHECK-LABEL: define hidden spir_func noundef nofpclass(nan inf) <4 x float> @_Z22test_smoothstep_float4Dv4_fS_S_( // SPVCHECK-SAME: <4 x float> noundef nofpclass(nan inf) [[MIN:%.*]], <4 x float> noundef nofpclass(nan inf) [[MAX:%.*]], <4 x float> noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR0]] { // SPVCHECK-NEXT: [[ENTRY:.*:]] -// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef <4 x float> @llvm.spv.smoothstep.v4f32(<4 x float> nofpclass(nan inf) [[MIN]], <4 x float> nofpclass(nan inf) [[MAX]], <4 x float> nofpclass(nan inf) [[X]]) +// SPVCHECK-NEXT: [[SPV_SMOOTHSTEP_I:%.*]] = tail call reassoc nnan ninf nsz arcp afn noundef nofpclass(nan inf) <4 x float> @llvm.spv.smoothstep.v4f32(<4 x float> nofpclass(nan inf) [[MIN]], <4 x float> nofpclass(nan inf) [[MAX]], <4 x float> nofpclass(nan inf) [[X]]) // SPVCHECK-NEXT: ret <4 x float> [[SPV_SMOOTHSTEP_I]] // float4 test_smoothstep_float4(float4 Min, float4 Max, float4 X) { return smoothstep(Min, Max, X); } diff --git a/clang/test/CodeGenHLSL/matrix-member-one-based-accessor-scalar-load.hlsl b/clang/test/CodeGenHLSL/matrix-member-one-based-accessor-scalar-load.hlsl new file mode 100644 index 0000000000000..bedb9fdbe11c8 --- /dev/null +++ b/clang/test/CodeGenHLSL/matrix-member-one-based-accessor-scalar-load.hlsl @@ -0,0 +1,230 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 + +// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return11u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return11(int4x4 A) { + return A._11; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return12u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return12(int4x4 A) { + return A._12; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return13u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return13(int4x4 A) { + return A._13; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return14u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return14(int4x4 A) { + return A._14; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return21u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return21(int4x4 A) { + return A._21; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return22u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return22(int4x4 A) { + return A._22; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return23u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return23(int4x4 A) { + return A._23; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return24u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return24(int4x4 A) { + return A._24; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return31u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return31(int4x4 A) { + return A._31; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return32u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return32(int4x4 A) { + return A._32; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return33u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return33(int4x4 A) { + return A._33; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return34u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return34(int4x4 A) { + return A._34; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return41u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return41(int4x4 A) { + return A._41; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return42u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return42(int4x4 A) { + return A._42; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return43u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return43(int4x4 A) { + return A._43; +} + +// CHECK-LABEL: define hidden noundef i32 @_Z8Return44u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: ret i32 [[CAST_VTRUNC]] +// +int Return44(int4x4 A) { + return A._44; +} + diff --git a/clang/test/CodeGenHLSL/matrix-member-one-based-accessor-scalar-store.hlsl b/clang/test/CodeGenHLSL/matrix-member-one-based-accessor-scalar-store.hlsl new file mode 100644 index 0000000000000..3098a09f67100 --- /dev/null +++ b/clang/test/CodeGenHLSL/matrix-member-one-based-accessor-scalar-store.hlsl @@ -0,0 +1,329 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 + +// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat11Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat11(out int4x4 A, int I) { + A._11 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat12Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 1 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat12(out int4x4 A, int I) { + A._12 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat13Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 2 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat13(out int4x4 A, int I) { + A._13 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat14Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 3 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat14(out int4x4 A, int I) { + A._14 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat21Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 4 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat21(out int4x4 A, int I) { + A._21 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat22Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 5 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat22(out int4x4 A, int I) { + A._22 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat23Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 6 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat23(out int4x4 A, int I) { + A._23 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat24Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 7 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat24(out int4x4 A, int I) { + A._24 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat31Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 8 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat31(out int4x4 A, int I) { + A._31 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat32Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 9 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat32(out int4x4 A, int I) { + A._32 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat33Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 10 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat33(out int4x4 A, int I) { + A._33 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat34Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 11 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat34(out int4x4 A, int I) { + A._34 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat41Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 12 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat41(out int4x4 A, int I) { + A._41 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat42Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 13 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat42(out int4x4 A, int I) { + A._42 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat43Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 14 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat43(out int4x4 A, int I) { + A._43 = I; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat44Ru11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x i32> [[SPLAT_SPLATINSERT]], <1 x i32> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x i32> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 15 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat44(out int4x4 A, int I) { + A._44 = I; +} + +//. +// CHECK: [[META4]] = !{} +// CHECK: [[META5]] = !{i64 4} +//. diff --git a/clang/test/CodeGenHLSL/matrix-member-one-based-swizzle-load.hlsl b/clang/test/CodeGenHLSL/matrix-member-one-based-swizzle-load.hlsl new file mode 100644 index 0000000000000..47737aaab0390 --- /dev/null +++ b/clang/test/CodeGenHLSL/matrix-member-one-based-swizzle-load.hlsl @@ -0,0 +1,108 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s + +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z17ReturnOnesSwizzleu11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int4 ReturnOnesSwizzle(int4x4 A) { + return A._11_12_13_14; +} + +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z18ReturnOnesSwizzle2u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int4 ReturnOnesSwizzle2(int4x4 A) { + return A._11_21_31_41; +} + +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z17ReturnTwosSwizzleu11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int4 ReturnTwosSwizzle(int4x4 A) { + return A._21_22_23_24; +} + +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z18ReturnTwosSwizzle2u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int4 ReturnTwosSwizzle2(int4x4 A) { + return A._12_22_32_42; +} + +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z19ReturnThreesSwizzleu11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int4 ReturnThreesSwizzle(int4x4 A) { + return A._31_32_33_34; +} + +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z20ReturnThreesSwizzle2u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int4 ReturnThreesSwizzle2(int4x4 A) { + return A._13_23_33_43; +} + +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z18ReturnFoursSwizzleu11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int4 ReturnFoursSwizzle(int4x4 A) { + return A._41_42_43_44; +} + +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z19ReturnFoursSwizzle2u11matrix_typeILm4ELm4EiE( +// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x i32>], align 4 +// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int4 ReturnFoursSwizzle2(int4x4 A) { + return A._14_24_34_44; +} diff --git a/clang/test/CodeGenHLSL/matrix-member-one-based-swizzle-store.hlsl b/clang/test/CodeGenHLSL/matrix-member-one-based-swizzle-store.hlsl new file mode 100644 index 0000000000000..ff7fab662a012 --- /dev/null +++ b/clang/test/CodeGenHLSL/matrix-member-one-based-swizzle-store.hlsl @@ -0,0 +1,230 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s + +// CHECK-LABEL: define hidden void @_Z19OnesSwizzleToScalarRu11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[CAST_SPLAT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <1 x i32> [[CAST_SPLAT]], <1 x i32> poison, <4 x i32> zeroinitializer +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]] +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP2]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 1 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP5]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 2 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP7]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 3 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[TMP9]], align 4 +// CHECK-NEXT: ret void +// +void OnesSwizzleToScalar(out int4x4 A, int I) { + A._11_12_13_14 = I.xxxx; +} + +// CHECK-LABEL: define hidden void @_Z19OnesSwizzleToVectorRu11matrix_typeILm4ELm4EiEDv4_i( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], <4 x i32> noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x i32>, align 16 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store <4 x i32> [[V]], ptr [[V_ADDR]], align 16 +// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[V_ADDR]], align 16 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 4 +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 8 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP6]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 12 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP8]], align 4 +// CHECK-NEXT: ret void +// +void OnesSwizzleToVector(out int4x4 A, int4 V) { + A._11_21_31_41 = V; +} + +// CHECK-LABEL: define hidden void @_Z19TwosSwizzleToScalarRu11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[CAST_SPLAT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <1 x i32> [[CAST_SPLAT]], <1 x i32> poison, <4 x i32> zeroinitializer +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 4 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 5 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP6]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 6 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP8]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 7 +// CHECK-NEXT: store i32 [[TMP9]], ptr [[TMP10]], align 4 +// CHECK-NEXT: ret void +// +void TwosSwizzleToScalar(out int4x4 A, int I) { + A._21_22_23_24 = I.xxxx; +} + +// CHECK-LABEL: define hidden void @_Z19TwosSwizzleToVectorRu11matrix_typeILm4ELm4EiEDv4_i( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], <4 x i32> noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x i32>, align 16 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store <4 x i32> [[V]], ptr [[V_ADDR]], align 16 +// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[V_ADDR]], align 16 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 1 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 5 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP5]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 9 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP7]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 13 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[TMP9]], align 4 +// CHECK-NEXT: ret void +// +void TwosSwizzleToVector(out int4x4 A, int4 V) { + A._12_22_32_42 = V; +} + +// CHECK-LABEL: define hidden void @_Z21ThreesSwizzleToScalarRu11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[CAST_SPLAT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <1 x i32> [[CAST_SPLAT]], <1 x i32> poison, <4 x i32> zeroinitializer +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 8 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 9 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP6]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 10 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP8]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 11 +// CHECK-NEXT: store i32 [[TMP9]], ptr [[TMP10]], align 4 +// CHECK-NEXT: ret void +// +void ThreesSwizzleToScalar(out int4x4 A, int I) { + A._31_32_33_34 = I.xxxx; +} + +// CHECK-LABEL: define hidden void @_Z21ThreesSwizzleToVectorRu11matrix_typeILm4ELm4EiEDv4_i( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], <4 x i32> noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x i32>, align 16 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store <4 x i32> [[V]], ptr [[V_ADDR]], align 16 +// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[V_ADDR]], align 16 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 2 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 6 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP5]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 10 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP7]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 14 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[TMP9]], align 4 +// CHECK-NEXT: ret void +// +void ThreesSwizzleToVector(out int4x4 A, int4 V) { + A._13_23_33_43 = V; +} + +// CHECK-LABEL: define hidden void @_Z20FoursSwizzleToScalarRu11matrix_typeILm4ELm4EiEi( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], i32 noundef [[I:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store i32 [[I]], ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 +// CHECK-NEXT: [[CAST_SPLAT:%.*]] = insertelement <1 x i32> poison, i32 [[TMP0]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <1 x i32> [[CAST_SPLAT]], <1 x i32> poison, <4 x i32> zeroinitializer +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 12 +// CHECK-NEXT: store i32 [[TMP3]], ptr [[TMP4]], align 4 +// CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 13 +// CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP6]], align 4 +// CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 14 +// CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP8]], align 4 +// CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr <16 x i32>, ptr [[TMP2]], i32 0, i32 15 +// CHECK-NEXT: store i32 [[TMP9]], ptr [[TMP10]], align 4 +// CHECK-NEXT: ret void +// +void FoursSwizzleToScalar(out int4x4 A, int I) { + A._41_42_43_44 = I.xxxx; +} + +// CHECK-LABEL: define hidden void @_Z20FoursSwizzleToVectorRu11matrix_typeILm4ELm4EiEDv4_i( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], <4 x i32> noundef [[V:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x i32>, align 16 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store <4 x i32> [[V]], ptr [[V_ADDR]], align 16 +// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr [[V_ADDR]], align 16 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 12 +// CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 13 +// CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP5]], align 4 +// CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 14 +// CHECK-NEXT: store i32 [[TMP6]], ptr [[TMP7]], align 4 +// CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr <16 x i32>, ptr [[TMP1]], i32 0, i32 15 +// CHECK-NEXT: store i32 [[TMP8]], ptr [[TMP9]], align 4 +// CHECK-NEXT: ret void +// +void FoursSwizzleToVector(out int4x4 A, int4 V) { + A._41_42_43_44 = V; +} +//. +// CHECK: [[META4]] = !{} +// CHECK: [[META5]] = !{i64 4} +//. diff --git a/clang/test/CodeGenHLSL/matrix-member-zero-based-accessor-scalar-load.hlsl b/clang/test/CodeGenHLSL/matrix-member-zero-based-accessor-scalar-load.hlsl new file mode 100644 index 0000000000000..8626e2d0d68b5 --- /dev/null +++ b/clang/test/CodeGenHLSL/matrix-member-zero-based-accessor-scalar-load.hlsl @@ -0,0 +1,230 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 + +// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return00u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return00(float4x4 A) { + return A._m00; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return01u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return01(float4x4 A) { + return A._m01; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return02u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return02(float4x4 A) { + return A._m02; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return03u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return03(float4x4 A) { + return A._m03; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return10u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return10(float4x4 A) { + return A._m10; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return11u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return11(float4x4 A) { + return A._m11; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return12u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return12(float4x4 A) { + return A._m12; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return13u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return13(float4x4 A) { + return A._m13; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return20u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return20(float4x4 A) { + return A._m20; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return21u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return21(float4x4 A) { + return A._m21; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return22u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return22(float4x4 A) { + return A._m22; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return23u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return23(float4x4 A) { + return A._m23; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return30u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return30(float4x4 A) { + return A._m30; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return31u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return31(float4x4 A) { + return A._m31; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return32u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return32(float4x4 A) { + return A._m32; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) float @_Z8Return33u11matrix_typeILm4ELm4EfE( +// CHECK-SAME: <16 x float> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x float>], align 4 +// CHECK-NEXT: store <16 x float> [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x float>, ptr [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x float> [[TMP0]], <16 x float> poison, <1 x i32> +// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x float> [[TMP1]], i32 0 +// CHECK-NEXT: ret float [[CAST_VTRUNC]] +// +float Return33(float4x4 A) { + return A._m33; +} + diff --git a/clang/test/CodeGenHLSL/matrix-member-zero-based-accessor-scalar-store.hlsl b/clang/test/CodeGenHLSL/matrix-member-zero-based-accessor-scalar-store.hlsl new file mode 100644 index 0000000000000..fb4fa267174b9 --- /dev/null +++ b/clang/test/CodeGenHLSL/matrix-member-zero-based-accessor-scalar-store.hlsl @@ -0,0 +1,329 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 + +// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat00Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP1]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat00(out float4x4 A, float F) { + A._m00 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat01Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 1 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat01(out float4x4 A, float F) { + A._m01 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat02Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 2 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat02(out float4x4 A, float F) { + A._m02 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat03Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 3 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat03(out float4x4 A, float F) { + A._m03 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat10Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 4 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat10(out float4x4 A, float F) { + A._m10 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat11Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 5 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat11(out float4x4 A, float F) { + A._m11 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat12Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 6 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat12(out float4x4 A, float F) { + A._m12 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat13Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 7 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat13(out float4x4 A, float F) { + A._m13 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat20Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 8 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat20(out float4x4 A, float F) { + A._m20 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat21Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 9 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat21(out float4x4 A, float F) { + A._m21 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat22Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 10 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat22(out float4x4 A, float F) { + A._m22 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat23Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 11 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat23(out float4x4 A, float F) { + A._m23 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat30Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 12 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat30(out float4x4 A, float F) { + A._m30 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat31Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 13 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat31(out float4x4 A, float F) { + A._m31 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat32Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 14 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat32(out float4x4 A, float F) { + A._m32 = F; +} + +// CHECK-LABEL: define hidden void @_Z18StoreScalarAtMat33Ru11matrix_typeILm4ELm4EfEf( +// CHECK-SAME: ptr noalias noundef nonnull align 4 dereferenceable(64) [[A:%.*]], float noundef nofpclass(nan inf) [[F:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[F_ADDR:%.*]] = alloca float, align 4 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store float [[F]], ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4 +// CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x float> poison, float [[TMP0]], i64 0 +// CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <1 x float> [[SPLAT_SPLATINSERT]], <1 x float> poison, <1 x i32> zeroinitializer +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <1 x float> [[SPLAT_SPLAT]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x float>, ptr [[TMP1]], i32 0, i32 15 +// CHECK-NEXT: store float [[TMP2]], ptr [[TMP3]], align 4 +// CHECK-NEXT: ret void +// +void StoreScalarAtMat33(out float4x4 A, float F) { + A._m33 = F; +} + +//. +// CHECK: [[META4]] = !{} +// CHECK: [[META5]] = !{i64 4} +//. diff --git a/clang/test/CodeGenHLSL/matrix-member-zero-based-swizzle-load.hlsl b/clang/test/CodeGenHLSL/matrix-member-zero-based-swizzle-load.hlsl new file mode 100644 index 0000000000000..dca2e6132de60 --- /dev/null +++ b/clang/test/CodeGenHLSL/matrix-member-zero-based-swizzle-load.hlsl @@ -0,0 +1,108 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> @_Z18ReturnZerosSwizzleu11matrix_typeILm4ELm4EDhE( +// CHECK-SAME: <16 x half> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x half>], align 2 +// CHECK-NEXT: store <16 x half> [[A]], ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x half> [[TMP0]], <16 x half> poison, <4 x i32> +// CHECK-NEXT: ret <4 x half> [[TMP1]] +// +half4 ReturnZerosSwizzle(half4x4 A) { + return A._m00_m01_m02_m03; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> @_Z19ReturnZerosSwizzle2u11matrix_typeILm4ELm4EDhE( +// CHECK-SAME: <16 x half> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x half>], align 2 +// CHECK-NEXT: store <16 x half> [[A]], ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x half> [[TMP0]], <16 x half> poison, <4 x i32> +// CHECK-NEXT: ret <4 x half> [[TMP1]] +// +half4 ReturnZerosSwizzle2(half4x4 A) { + return A._m00_m10_m20_m30; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> @_Z17ReturnOnesSwizzleu11matrix_typeILm4ELm4EDhE( +// CHECK-SAME: <16 x half> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x half>], align 2 +// CHECK-NEXT: store <16 x half> [[A]], ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x half> [[TMP0]], <16 x half> poison, <4 x i32> +// CHECK-NEXT: ret <4 x half> [[TMP1]] +// +half4 ReturnOnesSwizzle(half4x4 A) { + return A._m10_m11_m12_m13; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> @_Z18ReturnOnesSwizzle2u11matrix_typeILm4ELm4EDhE( +// CHECK-SAME: <16 x half> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x half>], align 2 +// CHECK-NEXT: store <16 x half> [[A]], ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x half> [[TMP0]], <16 x half> poison, <4 x i32> +// CHECK-NEXT: ret <4 x half> [[TMP1]] +// +half4 ReturnOnesSwizzle2(half4x4 A) { + return A._m01_m11_m21_m31; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> @_Z17ReturnTwosSwizzleu11matrix_typeILm4ELm4EDhE( +// CHECK-SAME: <16 x half> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x half>], align 2 +// CHECK-NEXT: store <16 x half> [[A]], ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x half> [[TMP0]], <16 x half> poison, <4 x i32> +// CHECK-NEXT: ret <4 x half> [[TMP1]] +// +half4 ReturnTwosSwizzle(half4x4 A) { + return A._m20_m21_m22_m23; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> @_Z18ReturnTwosSwizzle2u11matrix_typeILm4ELm4EDhE( +// CHECK-SAME: <16 x half> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x half>], align 2 +// CHECK-NEXT: store <16 x half> [[A]], ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x half> [[TMP0]], <16 x half> poison, <4 x i32> +// CHECK-NEXT: ret <4 x half> [[TMP1]] +// +half4 ReturnTwosSwizzle2(half4x4 A) { + return A._m02_m12_m22_m32; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> @_Z19ReturnThreesSwizzleu11matrix_typeILm4ELm4EDhE( +// CHECK-SAME: <16 x half> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x half>], align 2 +// CHECK-NEXT: store <16 x half> [[A]], ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x half> [[TMP0]], <16 x half> poison, <4 x i32> +// CHECK-NEXT: ret <4 x half> [[TMP1]] +// +half4 ReturnThreesSwizzle(half4x4 A) { + return A._m30_m31_m32_m33; +} + +// CHECK-LABEL: define hidden noundef nofpclass(nan inf) <4 x half> @_Z20ReturnThreesSwizzle2u11matrix_typeILm4ELm4EDhE( +// CHECK-SAME: <16 x half> noundef nofpclass(nan inf) [[A:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [4 x <4 x half>], align 2 +// CHECK-NEXT: store <16 x half> [[A]], ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x half>, ptr [[A_ADDR]], align 2 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x half> [[TMP0]], <16 x half> poison, <4 x i32> +// CHECK-NEXT: ret <4 x half> [[TMP1]] +// +half4 ReturnThreesSwizzle2(half4x4 A) { + return A._m03_m13_m23_m33; +} diff --git a/clang/test/CodeGenHLSL/matrix-member-zero-based-swizzle-store.hlsl b/clang/test/CodeGenHLSL/matrix-member-zero-based-swizzle-store.hlsl new file mode 100644 index 0000000000000..72fbc015d5934 --- /dev/null +++ b/clang/test/CodeGenHLSL/matrix-member-zero-based-swizzle-store.hlsl @@ -0,0 +1,230 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 +// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s + +// CHECK-LABEL: define hidden void @_Z20ZerosSwizzleToScalarRu11matrix_typeILm4ELm4EdEd( +// CHECK-SAME: ptr noalias noundef nonnull align 8 dereferenceable(128) [[A:%.*]], double noundef nofpclass(nan inf) [[D:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store double [[D]], ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[CAST_SPLAT:%.*]] = insertelement <1 x double> poison, double [[TMP0]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <1 x double> [[CAST_SPLAT]], <1 x double> poison, <4 x i32> zeroinitializer +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]] +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 0 +// CHECK-NEXT: store double [[TMP3]], ptr [[TMP2]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 1 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 1 +// CHECK-NEXT: store double [[TMP4]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP1]], i32 2 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 2 +// CHECK-NEXT: store double [[TMP6]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x double> [[TMP1]], i32 3 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 3 +// CHECK-NEXT: store double [[TMP8]], ptr [[TMP9]], align 8 +// CHECK-NEXT: ret void +// +void ZerosSwizzleToScalar(out double4x4 A, double D) { + A._m00_m01_m02_m03 = D.xxxx; +} + +// CHECK-LABEL: define hidden void @_Z20ZerosSwizzleToVectorRu11matrix_typeILm4ELm4EdEDv4_d( +// CHECK-SAME: ptr noalias noundef nonnull align 8 dereferenceable(128) [[A:%.*]], <4 x double> noundef nofpclass(nan inf) [[V:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x double>, align 32 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store <4 x double> [[V]], ptr [[V_ADDR]], align 32 +// CHECK-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr [[V_ADDR]], align 32 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x double> [[TMP0]], i32 0 +// CHECK-NEXT: store double [[TMP2]], ptr [[TMP1]], align 8 +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x double> [[TMP0]], i32 1 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 4 +// CHECK-NEXT: store double [[TMP3]], ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP0]], i32 2 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 8 +// CHECK-NEXT: store double [[TMP5]], ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP0]], i32 3 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 12 +// CHECK-NEXT: store double [[TMP7]], ptr [[TMP8]], align 8 +// CHECK-NEXT: ret void +// +void ZerosSwizzleToVector(out double4x4 A, double4 V) { + A._m00_m10_m20_m30 = V; +} + +// CHECK-LABEL: define hidden void @_Z19OnesSwizzleToScalarRu11matrix_typeILm4ELm4EdEd( +// CHECK-SAME: ptr noalias noundef nonnull align 8 dereferenceable(128) [[A:%.*]], double noundef nofpclass(nan inf) [[D:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store double [[D]], ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[CAST_SPLAT:%.*]] = insertelement <1 x double> poison, double [[TMP0]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <1 x double> [[CAST_SPLAT]], <1 x double> poison, <4 x i32> zeroinitializer +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 0 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 4 +// CHECK-NEXT: store double [[TMP3]], ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 1 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 5 +// CHECK-NEXT: store double [[TMP5]], ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP1]], i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 6 +// CHECK-NEXT: store double [[TMP7]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x double> [[TMP1]], i32 3 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 7 +// CHECK-NEXT: store double [[TMP9]], ptr [[TMP10]], align 8 +// CHECK-NEXT: ret void +// +void OnesSwizzleToScalar(out double4x4 A, double D) { + A._m10_m11_m12_m13 = D.xxxx; +} + +// CHECK-LABEL: define hidden void @_Z19OnesSwizzleToVectorRu11matrix_typeILm4ELm4EdEDv4_d( +// CHECK-SAME: ptr noalias noundef nonnull align 8 dereferenceable(128) [[A:%.*]], <4 x double> noundef nofpclass(nan inf) [[V:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x double>, align 32 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store <4 x double> [[V]], ptr [[V_ADDR]], align 32 +// CHECK-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr [[V_ADDR]], align 32 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x double> [[TMP0]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 1 +// CHECK-NEXT: store double [[TMP2]], ptr [[TMP3]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP0]], i32 1 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 5 +// CHECK-NEXT: store double [[TMP4]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP0]], i32 2 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 9 +// CHECK-NEXT: store double [[TMP6]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x double> [[TMP0]], i32 3 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 13 +// CHECK-NEXT: store double [[TMP8]], ptr [[TMP9]], align 8 +// CHECK-NEXT: ret void +// +void OnesSwizzleToVector(out double4x4 A, double4 V) { + A._m01_m11_m21_m31 = V; +} + +// CHECK-LABEL: define hidden void @_Z19TwosSwizzleToScalarRu11matrix_typeILm4ELm4EdEd( +// CHECK-SAME: ptr noalias noundef nonnull align 8 dereferenceable(128) [[A:%.*]], double noundef nofpclass(nan inf) [[D:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store double [[D]], ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[CAST_SPLAT:%.*]] = insertelement <1 x double> poison, double [[TMP0]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <1 x double> [[CAST_SPLAT]], <1 x double> poison, <4 x i32> zeroinitializer +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 0 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 8 +// CHECK-NEXT: store double [[TMP3]], ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 1 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 9 +// CHECK-NEXT: store double [[TMP5]], ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP1]], i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 10 +// CHECK-NEXT: store double [[TMP7]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x double> [[TMP1]], i32 3 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 11 +// CHECK-NEXT: store double [[TMP9]], ptr [[TMP10]], align 8 +// CHECK-NEXT: ret void +// +void TwosSwizzleToScalar(out double4x4 A, double D) { + A._m20_m21_m22_m23 = D.xxxx; +} + +// CHECK-LABEL: define hidden void @_Z19TwosSwizzleToVectorRu11matrix_typeILm4ELm4EdEDv4_d( +// CHECK-SAME: ptr noalias noundef nonnull align 8 dereferenceable(128) [[A:%.*]], <4 x double> noundef nofpclass(nan inf) [[V:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x double>, align 32 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store <4 x double> [[V]], ptr [[V_ADDR]], align 32 +// CHECK-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr [[V_ADDR]], align 32 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x double> [[TMP0]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 2 +// CHECK-NEXT: store double [[TMP2]], ptr [[TMP3]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP0]], i32 1 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 6 +// CHECK-NEXT: store double [[TMP4]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP0]], i32 2 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 10 +// CHECK-NEXT: store double [[TMP6]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x double> [[TMP0]], i32 3 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 14 +// CHECK-NEXT: store double [[TMP8]], ptr [[TMP9]], align 8 +// CHECK-NEXT: ret void +// +void TwosSwizzleToVector(out double4x4 A, double4 V) { + A._m02_m12_m22_m32 = V; +} + +// CHECK-LABEL: define hidden void @_Z21ThreesSwizzleToScalarRu11matrix_typeILm4ELm4EdEd( +// CHECK-SAME: ptr noalias noundef nonnull align 8 dereferenceable(128) [[A:%.*]], double noundef nofpclass(nan inf) [[D:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store double [[D]], ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8 +// CHECK-NEXT: [[CAST_SPLAT:%.*]] = insertelement <1 x double> poison, double [[TMP0]], i64 0 +// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <1 x double> [[CAST_SPLAT]], <1 x double> poison, <4 x i32> zeroinitializer +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 0 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 12 +// CHECK-NEXT: store double [[TMP3]], ptr [[TMP4]], align 8 +// CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 1 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 13 +// CHECK-NEXT: store double [[TMP5]], ptr [[TMP6]], align 8 +// CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP1]], i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 14 +// CHECK-NEXT: store double [[TMP7]], ptr [[TMP8]], align 8 +// CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x double> [[TMP1]], i32 3 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr <16 x double>, ptr [[TMP2]], i32 0, i32 15 +// CHECK-NEXT: store double [[TMP9]], ptr [[TMP10]], align 8 +// CHECK-NEXT: ret void +// +void ThreesSwizzleToScalar(out double4x4 A, double D) { + A._m30_m31_m32_m33 = D.xxxx; +} + +// CHECK-LABEL: define hidden void @_Z21ThreesSwizzleToVectorRu11matrix_typeILm4ELm4EdEDv4_d( +// CHECK-SAME: ptr noalias noundef nonnull align 8 dereferenceable(128) [[A:%.*]], <4 x double> noundef nofpclass(nan inf) [[V:%.*]]) #[[ATTR0]] { +// CHECK-NEXT: [[ENTRY:.*:]] +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK-NEXT: [[V_ADDR:%.*]] = alloca <4 x double>, align 32 +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK-NEXT: store <4 x double> [[V]], ptr [[V_ADDR]], align 32 +// CHECK-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr [[V_ADDR]], align 32 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] +// CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x double> [[TMP0]], i32 0 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 3 +// CHECK-NEXT: store double [[TMP2]], ptr [[TMP3]], align 8 +// CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP0]], i32 1 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 7 +// CHECK-NEXT: store double [[TMP4]], ptr [[TMP5]], align 8 +// CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP0]], i32 2 +// CHECK-NEXT: [[TMP7:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 11 +// CHECK-NEXT: store double [[TMP6]], ptr [[TMP7]], align 8 +// CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x double> [[TMP0]], i32 3 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr <16 x double>, ptr [[TMP1]], i32 0, i32 15 +// CHECK-NEXT: store double [[TMP8]], ptr [[TMP9]], align 8 +// CHECK-NEXT: ret void +// +void ThreesSwizzleToVector(out double4x4 A, double4 V) { + A._m03_m13_m23_m33 = V; +} +//. +// CHECK: [[META4]] = !{} +// CHECK: [[META5]] = !{i64 8} +//. diff --git a/clang/test/CodeGenHLSL/resources-declared-only-once.hlsl b/clang/test/CodeGenHLSL/resources-declared-only-once.hlsl new file mode 100644 index 0000000000000..0f726af70e552 --- /dev/null +++ b/clang/test/CodeGenHLSL/resources-declared-only-once.hlsl @@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -triple dxilv1.7-unknown-shadermodel6.7-library -finclude-default-header -verify -emit-llvm -o - -x hlsl %s + +// expected-warning@+1{{declaration does not declare anything}} +RWStructuredBuffer; +RWStructuredBuffer a; +RWStructuredBuffer b; diff --git a/clang/test/CodeGenHLSL/resources/ByteAddressBuffers-methods.hlsl b/clang/test/CodeGenHLSL/resources/ByteAddressBuffers-methods.hlsl index 9dd02287620e7..af0fc75df6e89 100644 --- a/clang/test/CodeGenHLSL/resources/ByteAddressBuffers-methods.hlsl +++ b/clang/test/CodeGenHLSL/resources/ByteAddressBuffers-methods.hlsl @@ -12,6 +12,166 @@ RWByteAddressBuffer RWBuf : register(u0); // DXIL: @Buf = internal global %"class.hlsl::ByteAddressBuffer" poison // DXIL: @RWBuf = internal global %"class.hlsl::RWByteAddressBuffer" poison +export float TestLoad() { + return Buf.Load(0) + RWBuf.Load4(4).w + Buf.Load(20) + RWBuf.Load(24).w; +} + +// CHECK: define {{.*}} float @TestLoad()() +// CHECK: call {{.*}} i32 @hlsl::ByteAddressBuffer::Load(unsigned int)(ptr {{.*}} @Buf, i32 noundef 0) +// CHECK: call {{.*}} <4 x i32> @hlsl::RWByteAddressBuffer::Load4(unsigned int)(ptr {{.*}} @RWBuf, i32 noundef 4) +// CHECK: call {{.*}} float @float hlsl::ByteAddressBuffer::Load(unsigned int)(ptr {{.*}} @Buf, i32 noundef 20) +// CHECK: call {{.*}} <4 x float> @float vector[4] hlsl::RWByteAddressBuffer::Load(unsigned int)(ptr {{.*}} @RWBuf, i32 noundef 24) +// CHECK: add +// CHECK: ret float + +// CHECK: define {{.*}} i32 @hlsl::ByteAddressBuffer::Load(unsigned int)(ptr {{.*}} %this, i32 noundef %Index) +// CHECK: %__handle = getelementptr inbounds nuw %"class.hlsl::ByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 0, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// DXIL-NEXT: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_0_0t(target("dx.RawBuffer", i8, 0, 0) %[[HANDLE]], i32 %[[INDEX]]) +// CHECK-NEXT: %[[VAL:.*]] = load i32, ptr %[[PTR]] +// CHECK-NEXT: ret i32 %[[VAL]] + +// CHECK: define {{.*}} <4 x i32> @hlsl::RWByteAddressBuffer::Load4(unsigned int)(ptr {{.*}} %this, i32 noundef %Index) +// CHECK: %__handle = getelementptr inbounds nuw %"class.hlsl::RWByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// DXIL-NEXT: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_1_0t(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %[[INDEX]]) +// CHECK-NEXT: %[[VEC:.*]] = load <4 x i32>, ptr %[[PTR]] +// CHECK-NEXT: ret <4 x i32> %[[VEC]] + +// CHECK: define {{.*}} float @float hlsl::ByteAddressBuffer::Load(unsigned int)(ptr {{.*}} %this, i32 noundef %Index) +// CHECK: %__handle = getelementptr inbounds nuw %"class.hlsl::ByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 0, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// DXIL-NEXT: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_0_0t(target("dx.RawBuffer", i8, 0, 0) %[[HANDLE]], i32 %[[INDEX]]) +// CHECK-NEXT: %[[VAL:.*]] = load float, ptr %[[PTR]] +// CHECK-NEXT: ret float %[[VAL]] + +// CHECK: define {{.*}} <4 x float> @float vector[4] hlsl::RWByteAddressBuffer::Load(unsigned int)(ptr {{.*}} %this, i32 noundef %Index) +// CHECK: %__handle = getelementptr inbounds nuw %"class.hlsl::RWByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// DXIL-NEXT: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_1_0t(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %[[INDEX]]) +// CHECK-NEXT: %[[VEC:.*]] = load <4 x float>, ptr %[[PTR]] +// CHECK-NEXT: ret <4 x float> %[[VEC]] + +export float TestLoadWithStatus() { + uint s1, s2, s3, s4; + float ret = Buf.Load(0, s1) + RWBuf.Load4(4, s2).w + Buf.Load(20, s3) + RWBuf.Load(24, s4).w; + ret += float(s1 + s2 + s3 + s4); + return ret; +} + +// CHECK: define {{.*}} float @TestLoadWithStatus()() +// CHECK: call {{.*}} i32 @hlsl::ByteAddressBuffer::Load(unsigned int, unsigned int&)(ptr {{.*}} @Buf, i32 noundef 0, ptr {{.*}} %tmp) +// CHECK: call {{.*}} <4 x i32> @hlsl::RWByteAddressBuffer::Load4(unsigned int, unsigned int&)(ptr {{.*}} @RWBuf, i32 noundef 4, ptr {{.*}} %tmp1) +// CHECK: call {{.*}} float @float hlsl::ByteAddressBuffer::Load(unsigned int, unsigned int&)(ptr {{.*}} @Buf, i32 noundef 20, ptr {{.*}} %tmp4) +// CHECK: call {{.*}} <4 x float> @float vector[4] hlsl::RWByteAddressBuffer::Load(unsigned int, unsigned int&)(ptr {{.*}} @RWBuf, i32 noundef 24, ptr {{.*}} %tmp7) +// CHECK: add +// CHECK: ret float + +// CHECK: define {{.*}} i32 @hlsl::ByteAddressBuffer::Load(unsigned int, unsigned int&)(ptr {{.*}} %this, i32 noundef %Index, ptr {{.*}} %Status) +// CHECK: %__handle = getelementptr inbounds nuw %"class.hlsl::ByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 0, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// CHECK-NEXT: %[[LOADED_STATUS_ADDR:.*]] = load ptr, ptr %Status.addr +// DXIL-NEXT: %[[STRUCT:.*]] = call { i32, i1 } @llvm.dx.resource.load.rawbuffer.i32.tdx.RawBuffer_i8_0_0t(target("dx.RawBuffer", i8, 0, 0) %[[HANDLE]], i32 %[[INDEX]], i32 poison) +// CHECK-NEXT: %[[VALUE:.*]] = extractvalue { i32, i1 } %[[STRUCT]], 0 +// CHECK-NEXT: %[[STATUS_TEMP:.*]] = extractvalue { i32, i1 } %[[STRUCT]], 1 +// CHECK-NEXT: %[[STATUS_EXT:.*]] = zext i1 %[[STATUS_TEMP]] to i32 +// CHECK-NEXT: store i32 %[[STATUS_EXT]], ptr %[[LOADED_STATUS_ADDR]], align 4 +// CHECK-NEXT: ret i32 %[[VALUE]] + +// CHECK: define {{.*}} <4 x i32> @hlsl::RWByteAddressBuffer::Load4(unsigned int, unsigned int&)(ptr {{.*}} %this, i32 noundef %Index, ptr {{.*}} %Status) +// CHECK: %__handle = getelementptr inbounds nuw %"class.hlsl::RWByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// CHECK-NEXT: %[[LOADED_STATUS_ADDR:.*]] = load ptr, ptr %Status.addr +// DXIL-NEXT: %[[STRUCT:.*]] = call { <4 x i32>, i1 } @llvm.dx.resource.load.rawbuffer.v4i32.tdx.RawBuffer_i8_1_0t(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %[[INDEX]], i32 poison) +// CHECK-NEXT: %[[VALUE:.*]] = extractvalue { <4 x i32>, i1 } %[[STRUCT]], 0 +// CHECK-NEXT: %[[STATUS_TEMP:.*]] = extractvalue { <4 x i32>, i1 } %[[STRUCT]], 1 +// CHECK-NEXT: %[[STATUS_EXT:.*]] = zext i1 %[[STATUS_TEMP]] to i32 +// CHECK-NEXT: store i32 %[[STATUS_EXT]], ptr %[[LOADED_STATUS_ADDR]], align 4 +// CHECK-NEXT: ret <4 x i32> %[[VALUE]] + +// CHECK: define {{.*}} float @float hlsl::ByteAddressBuffer::Load(unsigned int, unsigned int&)(ptr {{.*}} %this, i32 noundef %Index, ptr {{.*}} %Status) +// CHECK: %__handle = getelementptr inbounds nuw %"class.hlsl::ByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 0, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// CHECK-NEXT: %[[LOADED_STATUS_ADDR:.*]] = load ptr, ptr %Status.addr +// DXIL-NEXT: %[[STRUCT:.*]] = call { float, i1 } @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_i8_0_0t(target("dx.RawBuffer", i8, 0, 0) %[[HANDLE]], i32 %[[INDEX]], i32 poison) +// CHECK-NEXT: %[[VALUE:.*]] = extractvalue { float, i1 } %[[STRUCT]], 0 +// CHECK-NEXT: %[[STATUS_TEMP:.*]] = extractvalue { float, i1 } %[[STRUCT]], 1 +// CHECK-NEXT: %[[STATUS_EXT:.*]] = zext i1 %[[STATUS_TEMP]] to i32 +// CHECK-NEXT: store i32 %[[STATUS_EXT]], ptr %[[LOADED_STATUS_ADDR]], align 4 +// CHECK-NEXT: ret float %[[VALUE]] + +// CHECK: define {{.*}} <4 x float> @float vector[4] hlsl::RWByteAddressBuffer::Load(unsigned int, unsigned int&)(ptr {{.*}} %this, i32 noundef %Index, ptr {{.*}} %Status) +// CHECK: %__handle = getelementptr inbounds nuw %"class.hlsl::RWByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// CHECK-NEXT: %[[LOADED_STATUS_ADDR:.*]] = load ptr, ptr %Status.addr +// DXIL-NEXT: %[[STRUCT:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.rawbuffer.v4f32.tdx.RawBuffer_i8_1_0t(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %[[INDEX]], i32 poison) +// CHECK-NEXT: %[[VALUE:.*]] = extractvalue { <4 x float>, i1 } %[[STRUCT]], 0 +// CHECK-NEXT: %[[STATUS_TEMP:.*]] = extractvalue { <4 x float>, i1 } %[[STRUCT]], 1 +// CHECK-NEXT: %[[STATUS_EXT:.*]] = zext i1 %[[STATUS_TEMP]] to i32 +// CHECK-NEXT: store i32 %[[STATUS_EXT]], ptr %[[LOADED_STATUS_ADDR]], align 4 +// CHECK-NEXT: ret <4 x float> %[[VALUE]] + +export void TestStore() { + uint4 a; + float4 b; + RWBuf.Store(0, a.x); + RWBuf.Store4(4, a); + RWBuf.Store(20, b.x); + RWBuf.Store(24, b); + return; +} + +// CHECK: define void @TestStore()() +// CHECK: call void @hlsl::RWByteAddressBuffer::Store(unsigned int, unsigned int)(ptr {{.*}} @RWBuf, i32 noundef 0, i32 noundef %{{.*}}) +// CHECK: call void @hlsl::RWByteAddressBuffer::Store4(unsigned int, unsigned int vector[4])(ptr {{.*}} @RWBuf, i32 noundef 4, <4 x i32> noundef %{{.*}}) +// CHECK: call void @void hlsl::RWByteAddressBuffer::Store(unsigned int, float)(ptr {{.*}} @RWBuf, i32 noundef 20, float noundef {{.*}}) +// CHECK: call void @void hlsl::RWByteAddressBuffer::Store(unsigned int, float vector[4])(ptr {{.*}} @RWBuf, i32 noundef 24, <4 x float> noundef {{.*}}) +// CHECK: ret void + +// CHECK: define {{.*}} void @hlsl::RWByteAddressBuffer::Store(unsigned int, unsigned int)(ptr {{.*}} %this, i32 noundef %Index, i32 noundef %Value) +// CHECK: %[[VALUE:.*]] = load i32, ptr %Value.addr +// CHECK-NEXT: %__handle = getelementptr inbounds nuw %"class.hlsl::RWByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// DXIL-NEXT: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_1_0t(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %[[INDEX]]) +// CHECK-NEXT: store i32 %[[VALUE]], ptr %[[PTR]] +// CHECK-NEXT: ret void + +// CHECK: define {{.*}} void @hlsl::RWByteAddressBuffer::Store4(unsigned int, unsigned int vector[4])(ptr {{.*}} %this, i32 noundef %Index, <4 x i32> noundef %Value) +// CHECK: %[[VALUE:.*]] = load <4 x i32>, ptr %Value.addr +// CHECK-NEXT: %__handle = getelementptr inbounds nuw %"class.hlsl::RWByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// DXIL-NEXT: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_1_0t(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %[[INDEX]]) +// CHECK-NEXT: store <4 x i32> %[[VALUE]], ptr %[[PTR]] +// CHECK-NEXT: ret void + +// CHECK: define {{.*}} void @void hlsl::RWByteAddressBuffer::Store(unsigned int, float)(ptr {{.*}} %this, i32 noundef %Index, float noundef {{.*}} %Value) +// CHECK: %[[VALUE:.*]] = load float, ptr %Value.addr +// CHECK-NEXT: %__handle = getelementptr inbounds nuw %"class.hlsl::RWByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// DXIL-NEXT: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_1_0t(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %[[INDEX]]) +// CHECK-NEXT: store float %[[VALUE]], ptr %[[PTR]] +// CHECK-NEXT: ret void + +// CHECK: define {{.*}} void @void hlsl::RWByteAddressBuffer::Store(unsigned int, float vector[4])(ptr {{.*}} %this, i32 noundef %Index, <4 x float> noundef {{.*}} %Value) +// CHECK: %[[VALUE:.*]] = load <4 x float>, ptr %Value.addr +// CHECK-NEXT: %__handle = getelementptr inbounds nuw %"class.hlsl::RWByteAddressBuffer", ptr %{{.*}}, i32 0, i32 0 +// DXIL-NEXT: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr %__handle +// CHECK-NEXT: %[[INDEX:.*]] = load i32, ptr %Index.addr +// DXIL-NEXT: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_1_0t(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %[[INDEX]]) +// CHECK-NEXT: store <4 x float> %[[VALUE]], ptr %[[PTR]] +// CHECK-NEXT: ret void + export uint TestGetDimensions() { uint dim1, dim2; Buf.GetDimensions(dim1); diff --git a/clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl b/clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl index 7a0b45875faf9..657694aa90fd7 100644 --- a/clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl +++ b/clang/test/CodeGenHLSL/resources/cbuffer_geps.hlsl @@ -73,7 +73,7 @@ void cbstructs() { use(s1.a1); // CHECK: load <3 x i16>, ptr addrspace(2) getelementptr inbounds nuw (%B, ptr addrspace(2) @s2, i32 0, i32 1), align 2 use(s2.b1); - // CHECK: load <2 x float>, ptr addrspace(2) getelementptr inbounds nuw (%C, ptr addrspace(2) @s3, i32 0, i32 1), align 8 + // CHECK: load <2 x float>, ptr addrspace(2) getelementptr inbounds nuw (%C, ptr addrspace(2) @s3, i32 0, i32 2), align 8 use(s3.c2.a1); // CHECK: load <2 x float>, ptr addrspace(2) getelementptr (<{ %A, target("dx.Padding", 8) }>, ptr addrspace(2) @s4, i32 2, i32 0), align 8 use(s4[2].a1); @@ -108,9 +108,9 @@ void cbmix() { use(m3.y); // CHECK: load <2 x float>, ptr addrspace(2) getelementptr (<{ <2 x float>, target("dx.Padding", 8) }>, ptr addrspace(2) getelementptr (<{ <{ [3 x <{ <2 x float>, target("dx.Padding", 8) }>], <2 x float> }>, target("dx.Padding", 8) }>, ptr addrspace(2) @m4, i32 2, i32 0), i32 3, i32 0), align 16 use(m4[2][3]); - // CHECK: load <4 x i32>, ptr addrspace(2) getelementptr inbounds nuw ([[ANON_1]], ptr addrspace(2) @m5, i32 0, i32 1), align 16 + // CHECK: load <4 x i32>, ptr addrspace(2) getelementptr inbounds nuw ([[ANON_1]], ptr addrspace(2) @m5, i32 0, i32 2), align 16 use(m5.d); - // CHECK: load <4 x i32>, ptr addrspace(2) getelementptr inbounds ([5 x <4 x i32>], ptr addrspace(2) getelementptr (<{ %ArrayAndScalar, target("dx.Padding", 12) }>, ptr addrspace(2) getelementptr inbounds nuw ([[ANON_2]], ptr addrspace(2) @m6, i32 0, i32 1), i32 2, i32 0), i32 0, i32 2), align 16 + // CHECK: load <4 x i32>, ptr addrspace(2) getelementptr inbounds ([5 x <4 x i32>], ptr addrspace(2) getelementptr (<{ %ArrayAndScalar, target("dx.Padding", 12) }>, ptr addrspace(2) getelementptr inbounds nuw ([[ANON_2]], ptr addrspace(2) @m6, i32 0, i32 2), i32 2, i32 0), i32 0, i32 2), align 16 use(m6.j[2].x[2]); // CHECK: load <1 x double>, ptr addrspace(2) @m7, align 8 use(m7); diff --git a/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm b/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm index 3c24e22fafd10..d92f51a361df5 100644 --- a/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm +++ b/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm @@ -226,7 +226,7 @@ void testCallContainsNonTrivial(ContainsNonTrivial *a) { // CHECK: call void @objc_msgSend({{.*}}, i64 %[[COERCE_VAL_PI]]) // CHECK: br -// CHECK: %[[CALL1:.*]] = call noundef ptr @_ZN6StrongD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %[[AGG_TMP]]) +// CHECK: %[[CALL1:.*]] = call noundef ptr @_ZN6StrongD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %[[AGG_TMP]]) // CHECK: br void test0(C *c) { @@ -240,7 +240,7 @@ void test0(C *c) { // CHECK: call void @objc_msgSend({{.*}}, ptr noundef dead_on_return %[[AGG_TMP]]) // CHECK: br -// CHECK: %[[CALL1:.*]] = call noundef ptr @_ZN10StrongWeakD1Ev(ptr noundef nonnull align 8 dereferenceable(16) %[[AGG_TMP]]) +// CHECK: %[[CALL1:.*]] = call noundef ptr @_ZN10StrongWeakD1Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) %[[AGG_TMP]]) // CHECK: br void test1(C *c) { @@ -252,7 +252,7 @@ void test1(C *c) { // CHECK-LABEL: define{{.*}} void @_ZN16testNullReceiver5test2EP1C( // CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_NONTRIVIAL]], align 8 // CHECK: call void @objc_msgSend({{.*}}, ptr noundef %[[AGG_TMP]]) -// CHECK-NEXT: call noundef ptr @_ZN10NonTrivialD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %[[AGG_TMP]]) +// CHECK-NEXT: call noundef ptr @_ZN10NonTrivialD1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) %[[AGG_TMP]]) void test2(C *c) { [c passNonTrivial:NonTrivial()]; diff --git a/clang/test/CodeGenObjCXX/ptrauth-struct-cxx-abi.mm b/clang/test/CodeGenObjCXX/ptrauth-struct-cxx-abi.mm index 0f8ac7329081a..751300d0bd1e6 100644 --- a/clang/test/CodeGenObjCXX/ptrauth-struct-cxx-abi.mm +++ b/clang/test/CodeGenObjCXX/ptrauth-struct-cxx-abi.mm @@ -16,7 +16,7 @@ // Check that AddrDiscStrong0 is destructed in the callee. // CHECK: define void @_Z24testParamAddrDiscStrong015AddrDiscStrong0(ptr noundef dead_on_return %[[A:.*]]) -// CHECK: call noundef ptr @_ZN15AddrDiscStrong0D1Ev(ptr noundef nonnull align {{[0-9]+}} dereferenceable(16) %[[A]]) +// CHECK: call noundef ptr @_ZN15AddrDiscStrong0D1Ev(ptr noundef nonnull align {{[0-9]+}} dead_on_return(16) dereferenceable(16) %[[A]]) // CHECK: ret void // CHECK: define linkonce_odr noundef ptr @_ZN15AddrDiscStrong0D1Ev( diff --git a/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl b/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl index 85157bdcf43f9..758b8a0d4a946 100644 --- a/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl +++ b/clang/test/CodeGenOpenCL/addr-space-struct-arg.cl @@ -645,12 +645,10 @@ kernel void KernelLargeTwoMember(struct LargeStructTwoMember u) { // AMDGCN20-NEXT: [[ENTRY:.*:]] // AMDGCN20-NEXT: [[RETVAL:%.*]] = alloca [[STRUCT_MAT4X4:%.*]], align 4, addrspace(5) // AMDGCN20-NEXT: [[IN:%.*]] = alloca [[STRUCT_MAT3X3:%.*]], align 4, addrspace(5) -// AMDGCN20-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN20-NEXT: [[IN1:%.*]] = addrspacecast ptr addrspace(5) [[IN]] to ptr -// AMDGCN20-NEXT: [[RETVAL_ASCAST_ASCAST:%.*]] = addrspacecast ptr [[RETVAL_ASCAST]] to ptr addrspace(5) // AMDGCN20-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_MAT3X3]], ptr [[IN1]], i32 0, i32 0 // AMDGCN20-NEXT: store [9 x i32] [[IN_COERCE]], ptr [[COERCE_DIVE]], align 4 -// AMDGCN20-NEXT: [[TMP0:%.*]] = load [[STRUCT_MAT4X4]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGCN20-NEXT: [[TMP0:%.*]] = load [[STRUCT_MAT4X4]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGCN20-NEXT: ret [[STRUCT_MAT4X4]] [[TMP0]] // // @@ -1590,6 +1588,15 @@ kernel void KernelLargeTwoMember(struct LargeStructTwoMember u) { // AMDGCN30-NEXT: ret void // // +// AMDGCN30-LABEL: define dso_local void @test_indirect_arg_globl( +// AMDGCN30-SAME: ) #[[ATTR0]] { +// AMDGCN30-NEXT: [[ENTRY:.*:]] +// AMDGCN30-NEXT: [[BYVAL_TEMP:%.*]] = alloca [[STRUCT_LARGESTRUCTONEMEMBER:%.*]], align 8, addrspace(5) +// AMDGCN30-NEXT: call void @llvm.memcpy.p5.p1.i64(ptr addrspace(5) align 8 [[BYVAL_TEMP]], ptr addrspace(1) align 8 @g_s, i64 800, i1 false) +// AMDGCN30-NEXT: call void @FuncOneLargeMember(ptr addrspace(5) noundef byref([[STRUCT_LARGESTRUCTONEMEMBER]]) align 8 [[BYVAL_TEMP]]) #[[ATTR4]] +// AMDGCN30-NEXT: ret void +// +// // AMDGCN30-LABEL: define dso_local amdgpu_kernel void @test_indirect_arg_local( // AMDGCN30-SAME: ) #[[ATTR1]] !kernel_arg_addr_space [[META9:![0-9]+]] !kernel_arg_access_qual [[META9]] !kernel_arg_type [[META9]] !kernel_arg_base_type [[META9]] !kernel_arg_type_qual [[META9]] { // AMDGCN30-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl index bc65788c17352..1cf1fcf1c9f9f 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl @@ -119,12 +119,10 @@ kernel void KernelLargeTwoMember(struct LargeStructTwoMember u) { // AMDGCN-NEXT: [[ENTRY:.*:]] // AMDGCN-NEXT: [[RETVAL:%.*]] = alloca [[STRUCT_MAT4X4:%.*]], align 4, addrspace(5) // AMDGCN-NEXT: [[IN:%.*]] = alloca [[STRUCT_MAT3X3:%.*]], align 4, addrspace(5) -// AMDGCN-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGCN-NEXT: [[IN1:%.*]] = addrspacecast ptr addrspace(5) [[IN]] to ptr -// AMDGCN-NEXT: [[RETVAL_ASCAST_ASCAST:%.*]] = addrspacecast ptr [[RETVAL_ASCAST]] to ptr addrspace(5) // AMDGCN-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_MAT3X3]], ptr [[IN1]], i32 0, i32 0 // AMDGCN-NEXT: store [9 x i32] [[IN_COERCE]], ptr [[COERCE_DIVE]], align 4 -// AMDGCN-NEXT: [[TMP0:%.*]] = load [[STRUCT_MAT4X4]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGCN-NEXT: [[TMP0:%.*]] = load [[STRUCT_MAT4X4]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGCN-NEXT: ret [[STRUCT_MAT4X4]] [[TMP0]] // // diff --git a/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl b/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl index c2d7616a33754..002c19ede0e56 100644 --- a/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl +++ b/clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl @@ -69,7 +69,7 @@ kernel void test_target_features_kernel(global int *i) { // CHECK: @__test_target_features_kernel_block_invoke_kernel.runtime.handle = internal addrspace(1) externally_initialized constant %block.runtime.handle.t.3 zeroinitializer, section ".amdgpu.kernel.runtime.handle" // CHECK: @llvm.used = appending addrspace(1) global [10 x ptr] [ptr @__test_block_invoke_kernel, ptr addrspacecast (ptr addrspace(1) @__test_block_invoke_kernel.runtime.handle to ptr), ptr @__test_block_invoke_2_kernel, ptr addrspacecast (ptr addrspace(1) @__test_block_invoke_2_kernel.runtime.handle to ptr), ptr @__test_block_invoke_3_kernel, ptr addrspacecast (ptr addrspace(1) @__test_block_invoke_3_kernel.runtime.handle to ptr), ptr @__test_block_invoke_4_kernel, ptr addrspacecast (ptr addrspace(1) @__test_block_invoke_4_kernel.runtime.handle to ptr), ptr @__test_target_features_kernel_block_invoke_kernel, ptr addrspacecast (ptr addrspace(1) @__test_target_features_kernel_block_invoke_kernel.runtime.handle to ptr)], section "llvm.metadata" //. -// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone +// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define dso_local void @callee( // NOCPU-SAME: i64 noundef [[ID:%.*]], ptr addrspace(1) noundef [[OUT:%.*]]) #[[ATTR1:[0-9]+]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -87,7 +87,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone +// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define dso_local amdgpu_kernel void @test( // NOCPU-SAME: ptr addrspace(1) noundef align 1 [[A:%.*]], i8 noundef [[B:%.*]], ptr addrspace(1) noundef align 8 [[C:%.*]], i64 noundef [[D:%.*]]) #[[ATTR2:[0-9]+]] !kernel_arg_addr_space [[META3:![0-9]+]] !kernel_arg_access_qual [[META4:![0-9]+]] !kernel_arg_type [[META5:![0-9]+]] !kernel_arg_base_type [[META5]] !kernel_arg_type_qual [[META6:![0-9]+]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -111,7 +111,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone +// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define dso_local void @__clang_ocl_kern_imp_test( // NOCPU-SAME: ptr addrspace(1) noundef align 1 [[A:%.*]], i8 noundef signext [[B:%.*]], ptr addrspace(1) noundef align 8 [[C:%.*]], i64 noundef [[D:%.*]]) #[[ATTR3:[0-9]+]] !kernel_arg_addr_space [[META3]] !kernel_arg_access_qual [[META4]] !kernel_arg_type [[META5]] !kernel_arg_base_type [[META5]] !kernel_arg_type_qual [[META6]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -233,7 +233,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone +// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define dso_local amdgpu_kernel void @test_target_features_kernel( // NOCPU-SAME: ptr addrspace(1) noundef align 4 [[I:%.*]]) #[[ATTR4:[0-9]+]] !kernel_arg_addr_space [[META7:![0-9]+]] !kernel_arg_access_qual [[META8:![0-9]+]] !kernel_arg_type [[META9:![0-9]+]] !kernel_arg_base_type [[META9]] !kernel_arg_type_qual [[META10:![0-9]+]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -245,7 +245,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone +// NOCPU: Function Attrs: convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define dso_local void @__clang_ocl_kern_imp_test_target_features_kernel( // NOCPU-SAME: ptr addrspace(1) noundef align 4 [[I:%.*]]) #[[ATTR5:[0-9]+]] !kernel_arg_addr_space [[META7]] !kernel_arg_access_qual [[META8]] !kernel_arg_type [[META9]] !kernel_arg_base_type [[META9]] !kernel_arg_type_qual [[META10]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -266,7 +266,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline nounwind optnone +// NOCPU: Function Attrs: convergent noinline nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal void @__test_block_invoke( // NOCPU-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR7:[0-9]+]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -285,7 +285,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent nounwind +// NOCPU: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal amdgpu_kernel void @__test_block_invoke_kernel( // NOCPU-SAME: <{ i32, i32, ptr, ptr addrspace(1), i8 }> [[TMP0:%.*]]) #[[ATTR8:[0-9]+]] !associated [[META11:![0-9]+]] !kernel_arg_addr_space [[META12:![0-9]+]] !kernel_arg_access_qual [[META8]] !kernel_arg_type [[META13:![0-9]+]] !kernel_arg_base_type [[META13]] !kernel_arg_type_qual [[META10]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -296,7 +296,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline nounwind optnone +// NOCPU: Function Attrs: convergent noinline nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal void @__test_block_invoke_2( // NOCPU-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR7]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -321,7 +321,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent nounwind +// NOCPU: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal amdgpu_kernel void @__test_block_invoke_2_kernel( // NOCPU-SAME: <{ i32, i32, ptr, ptr addrspace(1), ptr addrspace(1), i64, i8 }> [[TMP0:%.*]]) #[[ATTR8]] !associated [[META14:![0-9]+]] !kernel_arg_addr_space [[META12]] !kernel_arg_access_qual [[META8]] !kernel_arg_type [[META13]] !kernel_arg_base_type [[META13]] !kernel_arg_type_qual [[META10]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -332,7 +332,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline nounwind optnone +// NOCPU: Function Attrs: convergent noinline nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal void @__test_block_invoke_3( // NOCPU-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]], ptr addrspace(3) noundef [[LP:%.*]]) #[[ATTR7]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -363,7 +363,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent nounwind +// NOCPU: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal amdgpu_kernel void @__test_block_invoke_3_kernel( // NOCPU-SAME: <{ i32, i32, ptr, ptr addrspace(1), ptr addrspace(1), i64, i8 }> [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) #[[ATTR8]] !associated [[META15:![0-9]+]] !kernel_arg_addr_space [[META16:![0-9]+]] !kernel_arg_access_qual [[META17:![0-9]+]] !kernel_arg_type [[META18:![0-9]+]] !kernel_arg_base_type [[META18]] !kernel_arg_type_qual [[META19:![0-9]+]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -374,7 +374,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline nounwind optnone +// NOCPU: Function Attrs: convergent noinline nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal void @__test_block_invoke_4( // NOCPU-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR7]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -392,7 +392,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent nounwind +// NOCPU: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal amdgpu_kernel void @__test_block_invoke_4_kernel( // NOCPU-SAME: <{ i32, i32, ptr, i64, ptr addrspace(1) }> [[TMP0:%.*]]) #[[ATTR8]] !associated [[META20:![0-9]+]] !kernel_arg_addr_space [[META12]] !kernel_arg_access_qual [[META8]] !kernel_arg_type [[META13]] !kernel_arg_base_type [[META13]] !kernel_arg_type_qual [[META10]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -403,7 +403,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent noinline nounwind optnone +// NOCPU: Function Attrs: convergent noinline nounwind optnone denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal void @__test_target_features_kernel_block_invoke( // NOCPU-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR7]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -417,7 +417,7 @@ kernel void test_target_features_kernel(global int *i) { // NOCPU-NEXT: ret void // // -// NOCPU: Function Attrs: convergent nounwind +// NOCPU: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // NOCPU-LABEL: define internal amdgpu_kernel void @__test_target_features_kernel_block_invoke_kernel( // NOCPU-SAME: { i32, i32, ptr } [[TMP0:%.*]]) #[[ATTR8]] !associated [[META21:![0-9]+]] !kernel_arg_addr_space [[META12]] !kernel_arg_access_qual [[META8]] !kernel_arg_type [[META13]] !kernel_arg_base_type [[META13]] !kernel_arg_type_qual [[META10]] { // NOCPU-NEXT: [[ENTRY:.*:]] @@ -443,7 +443,7 @@ kernel void test_target_features_kernel(global int *i) { // // // -// GFX900: Function Attrs: convergent norecurse nounwind +// GFX900: Function Attrs: convergent norecurse nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define dso_local void @callee( // GFX900-SAME: i64 noundef [[ID:%.*]], ptr addrspace(1) noundef [[OUT:%.*]]) #[[ATTR1:[0-9]+]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -461,7 +461,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent norecurse nounwind +// GFX900: Function Attrs: convergent norecurse nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define dso_local amdgpu_kernel void @test( // GFX900-SAME: ptr addrspace(1) noundef align 1 [[A:%.*]], i8 noundef [[B:%.*]], ptr addrspace(1) noundef align 8 [[C:%.*]], i64 noundef [[D:%.*]]) #[[ATTR2:[0-9]+]] !kernel_arg_addr_space [[META12:![0-9]+]] !kernel_arg_access_qual [[META13:![0-9]+]] !kernel_arg_type [[META14:![0-9]+]] !kernel_arg_base_type [[META14]] !kernel_arg_type_qual [[META15:![0-9]+]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -485,7 +485,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: alwaysinline convergent norecurse nounwind +// GFX900: Function Attrs: alwaysinline convergent norecurse nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define dso_local void @__clang_ocl_kern_imp_test( // GFX900-SAME: ptr addrspace(1) noundef align 1 [[A:%.*]], i8 noundef signext [[B:%.*]], ptr addrspace(1) noundef align 8 [[C:%.*]], i64 noundef [[D:%.*]]) #[[ATTR3:[0-9]+]] !kernel_arg_addr_space [[META12]] !kernel_arg_access_qual [[META13]] !kernel_arg_type [[META14]] !kernel_arg_base_type [[META14]] !kernel_arg_type_qual [[META15]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -617,7 +617,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent norecurse nounwind +// GFX900: Function Attrs: convergent norecurse nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define dso_local amdgpu_kernel void @test_target_features_kernel( // GFX900-SAME: ptr addrspace(1) noundef align 4 [[I:%.*]]) #[[ATTR2]] !kernel_arg_addr_space [[META22:![0-9]+]] !kernel_arg_access_qual [[META23:![0-9]+]] !kernel_arg_type [[META24:![0-9]+]] !kernel_arg_base_type [[META24]] !kernel_arg_type_qual [[META25:![0-9]+]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -629,7 +629,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: alwaysinline convergent norecurse nounwind +// GFX900: Function Attrs: alwaysinline convergent norecurse nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define dso_local void @__clang_ocl_kern_imp_test_target_features_kernel( // GFX900-SAME: ptr addrspace(1) noundef align 4 [[I:%.*]]) #[[ATTR3]] !kernel_arg_addr_space [[META22]] !kernel_arg_access_qual [[META23]] !kernel_arg_type [[META24]] !kernel_arg_base_type [[META24]] !kernel_arg_type_qual [[META25]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -656,7 +656,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal void @__test_block_invoke( // GFX900-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR6:[0-9]+]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -672,7 +672,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal amdgpu_kernel void @__test_block_invoke_kernel( // GFX900-SAME: <{ i32, i32, ptr, ptr addrspace(1), i8 }> [[TMP0:%.*]]) #[[ATTR6]] !associated [[META28:![0-9]+]] !kernel_arg_addr_space [[META29:![0-9]+]] !kernel_arg_access_qual [[META23]] !kernel_arg_type [[META30:![0-9]+]] !kernel_arg_base_type [[META30]] !kernel_arg_type_qual [[META25]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -683,7 +683,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal void @__test_block_invoke_2( // GFX900-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR6]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -705,7 +705,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal amdgpu_kernel void @__test_block_invoke_2_kernel( // GFX900-SAME: <{ i32, i32, ptr, ptr addrspace(1), ptr addrspace(1), i64, i8 }> [[TMP0:%.*]]) #[[ATTR6]] !associated [[META31:![0-9]+]] !kernel_arg_addr_space [[META29]] !kernel_arg_access_qual [[META23]] !kernel_arg_type [[META30]] !kernel_arg_base_type [[META30]] !kernel_arg_type_qual [[META25]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -716,7 +716,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal void @__test_block_invoke_3( // GFX900-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]], ptr addrspace(3) noundef [[LP:%.*]]) #[[ATTR6]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -744,7 +744,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal amdgpu_kernel void @__test_block_invoke_3_kernel( // GFX900-SAME: <{ i32, i32, ptr, ptr addrspace(1), ptr addrspace(1), i64, i8 }> [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) #[[ATTR6]] !associated [[META33:![0-9]+]] !kernel_arg_addr_space [[META34:![0-9]+]] !kernel_arg_access_qual [[META35:![0-9]+]] !kernel_arg_type [[META36:![0-9]+]] !kernel_arg_base_type [[META36]] !kernel_arg_type_qual [[META37:![0-9]+]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -755,7 +755,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal void @__test_block_invoke_4( // GFX900-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR6]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -770,7 +770,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal amdgpu_kernel void @__test_block_invoke_4_kernel( // GFX900-SAME: <{ i32, i32, ptr, i64, ptr addrspace(1) }> [[TMP0:%.*]]) #[[ATTR6]] !associated [[META38:![0-9]+]] !kernel_arg_addr_space [[META29]] !kernel_arg_access_qual [[META23]] !kernel_arg_type [[META30]] !kernel_arg_base_type [[META30]] !kernel_arg_type_qual [[META25]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -781,7 +781,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal void @__test_target_features_kernel_block_invoke( // GFX900-SAME: ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR6]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -792,7 +792,7 @@ kernel void test_target_features_kernel(global int *i) { // GFX900-NEXT: ret void // // -// GFX900: Function Attrs: convergent nounwind +// GFX900: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // GFX900-LABEL: define internal amdgpu_kernel void @__test_target_features_kernel_block_invoke_kernel( // GFX900-SAME: { i32, i32, ptr } [[TMP0:%.*]]) #[[ATTR6]] !associated [[META39:![0-9]+]] !kernel_arg_addr_space [[META29]] !kernel_arg_access_qual [[META23]] !kernel_arg_type [[META30]] !kernel_arg_base_type [[META30]] !kernel_arg_type_qual [[META25]] { // GFX900-NEXT: [[ENTRY:.*:]] @@ -804,24 +804,24 @@ kernel void test_target_features_kernel(global int *i) { // //. // NOCPU: attributes #[[ATTR0:[0-9]+]] = { "objc_arc_inert" } -// NOCPU: attributes #[[ATTR1]] = { convergent noinline norecurse nounwind optnone "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -// NOCPU: attributes #[[ATTR2]] = { convergent noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,256" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" } -// NOCPU: attributes #[[ATTR3]] = { convergent noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,256" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -// NOCPU: attributes #[[ATTR4]] = { convergent noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,256" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+s-memtime-inst" "uniform-work-group-size"="false" } -// NOCPU: attributes #[[ATTR5]] = { convergent noinline norecurse nounwind optnone "amdgpu-flat-work-group-size"="1,256" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+s-memtime-inst" } +// NOCPU: attributes #[[ATTR1]] = { convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +// NOCPU: attributes #[[ATTR2]] = { convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) "amdgpu-flat-work-group-size"="1,256" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" } +// NOCPU: attributes #[[ATTR3]] = { convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) "amdgpu-flat-work-group-size"="1,256" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +// NOCPU: attributes #[[ATTR4]] = { convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) "amdgpu-flat-work-group-size"="1,256" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+s-memtime-inst" "uniform-work-group-size"="false" } +// NOCPU: attributes #[[ATTR5]] = { convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) "amdgpu-flat-work-group-size"="1,256" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+s-memtime-inst" } // NOCPU: attributes #[[ATTR6:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) } -// NOCPU: attributes #[[ATTR7]] = { convergent noinline nounwind optnone "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -// NOCPU: attributes #[[ATTR8]] = { convergent nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +// NOCPU: attributes #[[ATTR7]] = { convergent noinline nounwind optnone denormal_fpenv(float: preservesign) "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +// NOCPU: attributes #[[ATTR8]] = { convergent nounwind denormal_fpenv(float: preservesign) "no-trapping-math"="true" "stack-protector-buffer-size"="8" } // NOCPU: attributes #[[ATTR9:[0-9]+]] = { nocallback nofree nosync nounwind willreturn } // NOCPU: attributes #[[ATTR10]] = { convergent nounwind } //. // GFX900: attributes #[[ATTR0:[0-9]+]] = { "objc_arc_inert" } -// GFX900: attributes #[[ATTR1]] = { convergent norecurse nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="-sram-ecc" } -// GFX900: attributes #[[ATTR2]] = { convergent norecurse nounwind "amdgpu-flat-work-group-size"="1,256" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="-sram-ecc" "uniform-work-group-size"="false" } -// GFX900: attributes #[[ATTR3]] = { alwaysinline convergent norecurse nounwind "amdgpu-flat-work-group-size"="1,256" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="-sram-ecc" } +// GFX900: attributes #[[ATTR1]] = { convergent norecurse nounwind denormal_fpenv(float: preservesign) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="-sram-ecc" } +// GFX900: attributes #[[ATTR2]] = { convergent norecurse nounwind denormal_fpenv(float: preservesign) "amdgpu-flat-work-group-size"="1,256" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="-sram-ecc" "uniform-work-group-size"="false" } +// GFX900: attributes #[[ATTR3]] = { alwaysinline convergent norecurse nounwind denormal_fpenv(float: preservesign) "amdgpu-flat-work-group-size"="1,256" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="-sram-ecc" } // GFX900: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } // GFX900: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) } -// GFX900: attributes #[[ATTR6]] = { convergent nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="-sram-ecc" } +// GFX900: attributes #[[ATTR6]] = { convergent nounwind denormal_fpenv(float: preservesign) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="gfx900" "target-features"="-sram-ecc" } // GFX900: attributes #[[ATTR7:[0-9]+]] = { nocallback nofree nosync nounwind willreturn } // GFX900: attributes #[[ATTR8]] = { convergent nounwind } // GFX900: attributes #[[ATTR9]] = { nounwind } diff --git a/clang/test/CodeGenOpenCL/atomic-ops.cl b/clang/test/CodeGenOpenCL/atomic-ops.cl index 214b3a4314222..f54880f88eb9a 100644 --- a/clang/test/CodeGenOpenCL/atomic-ops.cl +++ b/clang/test/CodeGenOpenCL/atomic-ops.cl @@ -344,7 +344,6 @@ int test_volatile(volatile atomic_int *i) { // CHECK-LABEL: @test_volatile // CHECK: %[[i_addr:.*]] = alloca ptr // CHECK-NEXT: %[[atomicdst:.*]] = alloca i32 - // CHECK-NEXT: %[[retval_ascast:.*]] = addrspacecast ptr addrspace(5) {{.*}} to ptr // CHECK-NEXT: %[[i_addr_ascast:.*]] = addrspacecast ptr addrspace(5) %[[i_addr]] to ptr // CHECK-NEXT: %[[atomicdst_ascast:.*]] = addrspacecast ptr addrspace(5) %[[atomicdst]] to ptr // CHECK-NEXT: store ptr %i, ptr %[[i_addr_ascast]] diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl index cdfe9fcd89091..83a44be930ae0 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl @@ -1,5 +1,6 @@ // REQUIRES: amdgpu-registered-target // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx942 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1170 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1250 -emit-llvm -o - %s | FileCheck %s diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl index 7cd3f1417844c..d7f97488376d7 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl @@ -7,6 +7,7 @@ // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1151 -emit-llvm -o - %s | FileCheck --check-prefixes=CHECK,GCN %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1152 -emit-llvm -o - %s | FileCheck --check-prefixes=CHECK,GCN %s // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1153 -emit-llvm -o - %s | FileCheck --check-prefixes=CHECK,GCN %s +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1170 -emit-llvm -o - %s | FileCheck --check-prefixes=CHECK,GCN %s // RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck --check-prefixes=CHECK,AMDGCNSPIRV %s typedef unsigned int uint; diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl index 8c02616780182..14d7e7a365989 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl @@ -185,10 +185,8 @@ void test_s_barrier_leave() // CHECK-LABEL: @test_s_get_barrier_state( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[STATE:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr // CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR_ASCAST]], align 4 @@ -205,10 +203,8 @@ unsigned test_s_get_barrier_state(int a) // CHECK-LABEL: @test_s_get_named_barrier_state( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[BAR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[STATE:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[BAR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[BAR_ADDR]] to ptr // CHECK-NEXT: store ptr [[BAR:%.*]], ptr [[BAR_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BAR_ADDR_ASCAST]], align 8 diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl index f2552d40fa273..8ecd6ba61a03e 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl @@ -7,60 +7,60 @@ typedef int v4i __attribute__((ext_vector_type(4))); // CHECK-GFX1250-LABEL: @test_amdgcn_global_load_monitor_b32( // CHECK-GFX1250-NEXT: entry: -// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) [[INPTR:%.*]], i32 1) +// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) [[INPTR:%.*]], i32 0, metadata [[META8:![0-9]+]]) // CHECK-GFX1250-NEXT: ret i32 [[TMP0]] // int test_amdgcn_global_load_monitor_b32(global int* inptr) { - return __builtin_amdgcn_global_load_monitor_b32(inptr, 1); + return __builtin_amdgcn_global_load_monitor_b32(inptr, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); } // CHECK-GFX1250-LABEL: @test_amdgcn_global_load_monitor_b64( // CHECK-GFX1250-NEXT: entry: -// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) [[INPTR:%.*]], i32 10) +// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) [[INPTR:%.*]], i32 2, metadata [[META9:![0-9]+]]) // CHECK-GFX1250-NEXT: ret <2 x i32> [[TMP0]] // v2i test_amdgcn_global_load_monitor_b64(global v2i* inptr) { - return __builtin_amdgcn_global_load_monitor_b64(inptr, 10); + return __builtin_amdgcn_global_load_monitor_b64(inptr, __ATOMIC_ACQUIRE, __MEMORY_SCOPE_DEVICE); } // CHECK-GFX1250-LABEL: @test_amdgcn_global_load_monitor_b128( // CHECK-GFX1250-NEXT: entry: -// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1) [[INPTR:%.*]], i32 22) +// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1) [[INPTR:%.*]], i32 2, metadata [[META10:![0-9]+]]) // CHECK-GFX1250-NEXT: ret <4 x i32> [[TMP0]] // v4i test_amdgcn_global_load_monitor_b128(global v4i* inptr) { - return __builtin_amdgcn_global_load_monitor_b128(inptr, 22); + return __builtin_amdgcn_global_load_monitor_b128(inptr, __ATOMIC_ACQUIRE, __MEMORY_SCOPE_WRKGRP); } // CHECK-GFX1250-LABEL: @test_amdgcn_flat_load_monitor_b32( // CHECK-GFX1250-NEXT: entry: -// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.amdgcn.flat.load.monitor.b32.i32(ptr [[INPTR:%.*]], i32 27) +// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.amdgcn.flat.load.monitor.b32.i32(ptr [[INPTR:%.*]], i32 0, metadata [[META8]]) // CHECK-GFX1250-NEXT: ret i32 [[TMP0]] // int test_amdgcn_flat_load_monitor_b32(int* inptr) { - return __builtin_amdgcn_flat_load_monitor_b32(inptr, 27); + return __builtin_amdgcn_flat_load_monitor_b32(inptr, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); } // CHECK-GFX1250-LABEL: @test_amdgcn_flat_load_monitor_b64( // CHECK-GFX1250-NEXT: entry: -// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call <2 x i32> @llvm.amdgcn.flat.load.monitor.b64.v2i32(ptr [[INPTR:%.*]], i32 1) +// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call <2 x i32> @llvm.amdgcn.flat.load.monitor.b64.v2i32(ptr [[INPTR:%.*]], i32 5, metadata [[META11:![0-9]+]]) // CHECK-GFX1250-NEXT: ret <2 x i32> [[TMP0]] // v2i test_amdgcn_flat_load_monitor_b64(v2i* inptr) { - return __builtin_amdgcn_flat_load_monitor_b64(inptr, 1); + return __builtin_amdgcn_flat_load_monitor_b64(inptr, __ATOMIC_SEQ_CST, __MEMORY_SCOPE_CLUSTR); } // CHECK-GFX1250-LABEL: @test_amdgcn_flat_load_monitor_b128( // CHECK-GFX1250-NEXT: entry: -// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr [[INPTR:%.*]], i32 0) +// CHECK-GFX1250-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr [[INPTR:%.*]], i32 0, metadata [[META8]]) // CHECK-GFX1250-NEXT: ret <4 x i32> [[TMP0]] // v4i test_amdgcn_flat_load_monitor_b128(v4i* inptr) { - return __builtin_amdgcn_flat_load_monitor_b128(inptr, 0); + return __builtin_amdgcn_flat_load_monitor_b128(inptr, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM); } diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl index b32bcdd408512..0b4cdd0c2c28f 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl @@ -1506,10 +1506,8 @@ void test_s_wakeup_barrier(void *bar) // CHECK-LABEL: @test_global_add_f32( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr // CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr // CHECK-NEXT: store ptr addrspace(1) [[ADDR:%.*]], ptr [[ADDR_ADDR_ASCAST]], align 8 @@ -1525,10 +1523,8 @@ float test_global_add_f32(global float *addr, float x) { // CHECK-LABEL: @test_global_add_half2( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <2 x half>, align 4, addrspace(5) // CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca <2 x half>, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr // CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr // CHECK-NEXT: store ptr addrspace(1) [[ADDR:%.*]], ptr [[ADDR_ADDR_ASCAST]], align 8 @@ -1544,10 +1540,8 @@ half2 test_global_add_half2(global half2 *addr, half2 x) { // CHECK-LABEL: @test_flat_add_2f16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <2 x half>, align 4, addrspace(5) // CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca <2 x half>, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr // CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr // CHECK-NEXT: store ptr [[ADDR:%.*]], ptr [[ADDR_ADDR_ASCAST]], align 8 @@ -1563,10 +1557,8 @@ half2 test_flat_add_2f16(generic half2 *addr, half2 x) { // CHECK-LABEL: @test_flat_add_2bf16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <2 x i16>, align 4, addrspace(5) // CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca <2 x i16>, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr // CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr // CHECK-NEXT: store ptr [[ADDR:%.*]], ptr [[ADDR_ADDR_ASCAST]], align 8 @@ -1584,10 +1576,8 @@ short2 test_flat_add_2bf16(generic short2 *addr, short2 x) { // CHECK-LABEL: @test_global_add_2bf16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <2 x i16>, align 4, addrspace(5) // CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca <2 x i16>, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr // CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr // CHECK-NEXT: store ptr addrspace(1) [[ADDR:%.*]], ptr [[ADDR_ADDR_ASCAST]], align 8 @@ -1605,10 +1595,8 @@ short2 test_global_add_2bf16(global short2 *addr, short2 x) { // CHECK-LABEL: @test_local_add_2f16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <2 x i16>, align 4, addrspace(5) // CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr addrspace(3), align 4, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca <2 x i16>, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr // CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr // CHECK-NEXT: store ptr addrspace(3) [[ADDR:%.*]], ptr [[ADDR_ADDR_ASCAST]], align 4 @@ -1626,10 +1614,8 @@ short2 test_local_add_2f16(local short2 *addr, short2 x) { // CHECK-LABEL: @test_local_add_2bf16( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <2 x half>, align 4, addrspace(5) // CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr addrspace(3), align 4, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca <2 x half>, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr // CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr // CHECK-NEXT: store ptr addrspace(3) [[ADDR:%.*]], ptr [[ADDR_ADDR_ASCAST]], align 4 diff --git a/clang/test/CodeGenOpenCL/check-atomic-alignment.cl b/clang/test/CodeGenOpenCL/check-atomic-alignment.cl index 89771d20ad090..1f7e4ce78ea55 100644 --- a/clang/test/CodeGenOpenCL/check-atomic-alignment.cl +++ b/clang/test/CodeGenOpenCL/check-atomic-alignment.cl @@ -24,10 +24,8 @@ struct __half2 { // CHECK-LABEL: define dso_local <2 x half> @test_flat_add_2f16( // CHECK-SAME: ptr noundef [[ADDR:%.*]], <2 x half> noundef [[VAL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[RETVAL:%.*]] = alloca <2 x half>, align 4, addrspace(5) // CHECK-NEXT: [[ADDR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca <2 x half>, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[ADDR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ADDR_ADDR]] to ptr // CHECK-NEXT: [[VAL_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VAL_ADDR]] to ptr // CHECK-NEXT: store ptr [[ADDR]], ptr [[ADDR_ADDR_ASCAST]], align 8 diff --git a/clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl b/clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl index 5cbf6452d4c85..0149d1618e2b0 100644 --- a/clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl +++ b/clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl @@ -20,7 +20,7 @@ kernel void device_side_enqueue(global float *a, global float *b, int i) { a[i] = 4.0f * b[i] + 1.0f; }); } -// SPIR32: Function Attrs: convergent noinline norecurse nounwind optnone +// SPIR32: Function Attrs: convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) // SPIR32-LABEL: define dso_local spir_kernel void @device_side_enqueue( // SPIR32-SAME: ptr addrspace(1) align 4 [[A:%.*]], ptr addrspace(1) align 4 [[B:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] !kernel_arg_addr_space [[META2:![0-9]+]] !kernel_arg_access_qual [[META3:![0-9]+]] !kernel_arg_type [[META4:![0-9]+]] !kernel_arg_base_type [[META4]] !kernel_arg_type_qual [[META5:![0-9]+]] { // SPIR32-NEXT: [[ENTRY:.*:]] @@ -37,7 +37,7 @@ kernel void device_side_enqueue(global float *a, global float *b, int i) { // SPIR32-NEXT: ret void // // -// SPIR32: Function Attrs: convergent noinline norecurse nounwind optnone +// SPIR32: Function Attrs: convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) // SPIR32-LABEL: define dso_local spir_func void @__clang_ocl_kern_imp_device_side_enqueue( // SPIR32-SAME: ptr addrspace(1) align 4 [[A:%.*]], ptr addrspace(1) align 4 [[B:%.*]], i32 [[I:%.*]]) #[[ATTR0]] !kernel_arg_addr_space [[META2]] !kernel_arg_access_qual [[META3]] !kernel_arg_type [[META4]] !kernel_arg_base_type [[META4]] !kernel_arg_type_qual [[META5]] { // SPIR32-NEXT: [[ENTRY:.*:]] @@ -76,7 +76,7 @@ kernel void device_side_enqueue(global float *a, global float *b, int i) { // SPIR32-NEXT: ret void // // -// SPIR32: Function Attrs: convergent noinline nounwind optnone +// SPIR32: Function Attrs: convergent noinline nounwind optnone denormal_fpenv(float: preservesign) // SPIR32-LABEL: define internal spir_func void @__device_side_enqueue_block_invoke( // SPIR32-SAME: ptr addrspace(4) [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { // SPIR32-NEXT: [[ENTRY:.*:]] @@ -100,7 +100,7 @@ kernel void device_side_enqueue(global float *a, global float *b, int i) { // SPIR32-NEXT: ret void // // -// SPIR32: Function Attrs: convergent nounwind +// SPIR32: Function Attrs: convergent nounwind denormal_fpenv(float: preservesign) // SPIR32-LABEL: define spir_kernel void @__device_side_enqueue_block_invoke_kernel( // SPIR32-SAME: ptr addrspace(4) [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] { // SPIR32-NEXT: [[ENTRY:.*:]] @@ -196,11 +196,11 @@ kernel void device_side_enqueue(global float *a, global float *b, int i) { // STRICTFP-NEXT: ret void // //. -// SPIR32: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind optnone "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" } +// SPIR32: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind optnone denormal_fpenv(float: preservesign) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" } // SPIR32: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) } -// SPIR32: attributes #[[ATTR2]] = { convergent noinline nounwind optnone "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +// SPIR32: attributes #[[ATTR2]] = { convergent noinline nounwind optnone denormal_fpenv(float: preservesign) "no-trapping-math"="true" "stack-protector-buffer-size"="8" } // SPIR32: attributes #[[ATTR3:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } -// SPIR32: attributes #[[ATTR4]] = { convergent nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +// SPIR32: attributes #[[ATTR4]] = { convergent nounwind denormal_fpenv(float: preservesign) "no-trapping-math"="true" "stack-protector-buffer-size"="8" } // SPIR32: attributes #[[ATTR5]] = { convergent nounwind "uniform-work-group-size"="true" } //. // STRICTFP: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind optnone strictfp "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" } diff --git a/clang/test/CodeGenOpenCL/fpmath.cl b/clang/test/CodeGenOpenCL/fpmath.cl index f3649d52e0091..5915496b3963d 100644 --- a/clang/test/CodeGenOpenCL/fpmath.cl +++ b/clang/test/CodeGenOpenCL/fpmath.cl @@ -1,8 +1,44 @@ // RUN: %clang_cc1 %s -emit-llvm -o - -triple spir-unknown-unknown | FileCheck --check-prefix=CHECK --check-prefix=NODIVOPT %s // RUN: %clang_cc1 %s -emit-llvm -o - -triple spir-unknown-unknown -cl-fp32-correctly-rounded-divide-sqrt | FileCheck --check-prefix=CHECK --check-prefix=DIVOPT %s -// RUN: %clang_cc1 %s -emit-llvm -o - -DNOFP64 -cl-std=CL1.2 -triple r600-unknown-unknown -target-cpu r600 -pedantic | FileCheck --check-prefix=CHECK-FLT %s +// RUN: %clang_cc1 %s -emit-llvm -o - -DNOFP16 -DNOFP64 -cl-std=CL1.2 -triple r600-unknown-unknown -target-cpu r600 -pedantic | FileCheck --check-prefix=CHECK-FLT %s // RUN: %clang_cc1 %s -emit-llvm -o - -DFP64 -cl-std=CL1.2 -triple spir-unknown-unknown -pedantic | FileCheck --check-prefix=CHECK-DBL %s +#ifndef NOFP16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +typedef __attribute__(( ext_vector_type(4) )) half half4; + +half hpscalardiv(half a, half b) { + // CHECK: @hpscalardiv + // CHECK: fdiv{{.*}}, + // NODIVOPT: !fpmath ![[MD_HFDIV:[0-9]+]] + // DIVOPT-NOT: !fpmath !{{[0-9]+}} + return a / b; +} + +half4 hpvectordiv(half4 a, half4 b) { + // CHECK: @hpvectordiv + // CHECK: fdiv{{.*}}, + // NODIVOPT: !fpmath ![[MD_HFDIV]] + // DIVOPT-NOT: !fpmath !{{[0-9]+}} + return a / b; +} + +half elementwise_sqrt_f16(half a) { + // CHECK-LABEL: @elementwise_sqrt_f16 + // NODIVOPT: call half @llvm.sqrt.f16(half %{{.+}}), !fpmath ![[MD_HSQRT:[0-9]+]] + // DIVOPT: call half @llvm.sqrt.f16(half %{{.+}}){{$}} + return __builtin_elementwise_sqrt(a); +} + +half4 elementwise_sqrt_v4f16(half4 a) { + // CHECK-LABEL: @elementwise_sqrt_v4f16 + // NODIVOPT: call <4 x half> @llvm.sqrt.v4f16(<4 x half> %{{.+}}), !fpmath ![[MD_HSQRT]] + // DIVOPT: call <4 x half> @llvm.sqrt.v4f16(<4 x half> %{{.+}}){{$}} + return __builtin_elementwise_sqrt(a); +} + +#endif // NOFP16 + typedef __attribute__(( ext_vector_type(4) )) float float4; float spscalardiv(float a, float b) { @@ -30,14 +66,14 @@ float spscalarsqrt(float a) { float elementwise_sqrt_f32(float a) { // CHECK-LABEL: @elementwise_sqrt_f32 - // NODIVOPT: call float @llvm.sqrt.f32(float %{{.+}}), !fpmath ![[MD_SQRT:[0-9]+]] + // NODIVOPT: call float @llvm.sqrt.f32(float %{{.+}}), !fpmath ![[MD_SQRT]] // DIVOPT: call float @llvm.sqrt.f32(float %{{.+}}){{$}} return __builtin_elementwise_sqrt(a); } float4 elementwise_sqrt_v4f32(float4 a) { // CHECK-LABEL: @elementwise_sqrt_v4f32 - // NODIVOPT: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{.+}}), !fpmath ![[MD_SQRT:[0-9]+]] + // NODIVOPT: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{.+}}), !fpmath ![[MD_SQRT]] // DIVOPT: call <4 x float> @llvm.sqrt.v4f32(<4 x float> %{{.+}}){{$}} return __builtin_elementwise_sqrt(a); } @@ -90,5 +126,7 @@ double4 elementwise_sqrt_v4f64(double4 a) { #endif +// NODIVOPT: ![[MD_HFDIV]] = !{float 1.000000e+00} +// NODIVOPT: ![[MD_HSQRT]] = !{float 1.500000e+00} // NODIVOPT: ![[MD_FDIV]] = !{float 2.500000e+00} // NODIVOPT: ![[MD_SQRT]] = !{float 3.000000e+00} diff --git a/clang/test/CodeGenOpenCL/relaxed-fpmath.cl b/clang/test/CodeGenOpenCL/relaxed-fpmath.cl index c113d23c3028d..126947ba8fd7f 100644 --- a/clang/test/CodeGenOpenCL/relaxed-fpmath.cl +++ b/clang/test/CodeGenOpenCL/relaxed-fpmath.cl @@ -30,32 +30,26 @@ float spscalardiv(float a, float b) { // CHECK: attributes // NORMAL-NOT: "less-precise-fpmad" -// NORMAL-NOT: "no-infs-fp-math" // NORMAL-NOT: "no-nans-fp-math" // NORMAL-NOT: "no-signed-zeros-fp-math" // FAST: "less-precise-fpmad"="true" -// FAST: "no-infs-fp-math"="true" // FAST: "no-nans-fp-math"="true" // FAST: "no-signed-zeros-fp-math"="true" // FINITE-NOT: "less-precise-fpmad" -// FINITE: "no-infs-fp-math"="true" // FINITE: "no-nans-fp-math"="true" // FINITE-NOT: "no-signed-zeros-fp-math" // UNSAFE: "less-precise-fpmad"="true" -// UNSAFE-NOT: "no-infs-fp-math" // UNSAFE-NOT: "no-nans-fp-math" // UNSAFE: "no-signed-zeros-fp-math"="true" // MAD: "less-precise-fpmad"="true" -// MAD-NOT: "no-infs-fp-math" // MAD-NOT: "no-nans-fp-math" // MAD-NOT: "no-signed-zeros-fp-math" // NOSIGNED-NOT: "less-precise-fpmad" -// NOSIGNED-NOT: "no-infs-fp-math" // NOSIGNED-NOT: "no-nans-fp-math" // NOSIGNED: "no-signed-zeros-fp-math"="true" diff --git a/clang/test/CodeGenOpenCL/sqrt-fpmath.cl b/clang/test/CodeGenOpenCL/sqrt-fpmath.cl index d0637283a7ec1..6f4adf56930ff 100644 --- a/clang/test/CodeGenOpenCL/sqrt-fpmath.cl +++ b/clang/test/CodeGenOpenCL/sqrt-fpmath.cl @@ -134,46 +134,52 @@ double16 call_sqrt_v16f64(double16 x) { } -// Not for f16 // CHECK-LABEL: define {{.*}} half @call_sqrt_f16( -// CHECK: call {{.*}} half @_Z4sqrtDh(half noundef %{{.+}}) #{{[0-9]+$}}{{$}} +// DEFAULT: call {{.*}} half @_Z4sqrtDh(half noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[HFPMATH:\![0-9]+]]{{$}} +// CORRECTLYROUNDED: call {{.*}} half @_Z4sqrtDh(half noundef %{{.+}}) #{{[0-9]+$}}{{$}} half call_sqrt_f16(half x) { return sqrt(x); } // CHECK-LABEL: define {{.*}} <2 x half> @call_sqrt_v2f16( -// CHECK: call {{.*}} <2 x half> @_Z4sqrtDv2_Dh(<2 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} +// DEFAULT: call {{.*}} <2 x half> @_Z4sqrtDv2_Dh(<2 x half> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[HFPMATH]]{{$}} +// CORRECTLYROUNDED: call {{.*}} <2 x half> @_Z4sqrtDv2_Dh(<2 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half2 call_sqrt_v2f16(half2 x) { return sqrt(x); } // CHECK-LABEL: define {{.*}} <3 x half> @call_sqrt_v3f16( -// CHECK: call {{.*}} <3 x half> @_Z4sqrtDv3_Dh(<3 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} +// DEFAULT: call {{.*}} <3 x half> @_Z4sqrtDv3_Dh(<3 x half> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[HFPMATH]]{{$}} +// CORRECTLYROUNDED: call {{.*}} <3 x half> @_Z4sqrtDv3_Dh(<3 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half3 call_sqrt_v3f16(half3 x) { return sqrt(x); } // CHECK-LABEL: define {{.*}} <4 x half> @call_sqrt_v4f16( -// CHECK: call {{.*}} <4 x half> @_Z4sqrtDv4_Dh(<4 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} +// DEFAULT: call {{.*}} <4 x half> @_Z4sqrtDv4_Dh(<4 x half> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[HFPMATH]]{{$}} +// CORRECTLYROUNDED: call {{.*}} <4 x half> @_Z4sqrtDv4_Dh(<4 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half4 call_sqrt_v4f16(half4 x) { return sqrt(x); } // CHECK-LABEL: define {{.*}} <8 x half> @call_sqrt_v8f16( -// CHECK: call {{.*}} <8 x half> @_Z4sqrtDv8_Dh(<8 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} +// DEFAULT: call {{.*}} <8 x half> @_Z4sqrtDv8_Dh(<8 x half> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[HFPMATH]]{{$}} +// CORRECTLYROUNDED: call {{.*}} <8 x half> @_Z4sqrtDv8_Dh(<8 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half8 call_sqrt_v8f16(half8 x) { return sqrt(x); } // CHECK-LABEL: define {{.*}} <16 x half> @call_sqrt_v16f16( -// CHECK: call {{.*}} <16 x half> @_Z4sqrtDv16_Dh(<16 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} +// DEFAULT: call {{.*}} <16 x half> @_Z4sqrtDv16_Dh(<16 x half> noundef %{{.+}}) #{{[0-9]+}}, !fpmath [[HFPMATH]]{{$}} +// CORRECTLYROUNDED: call {{.*}} <16 x half> @_Z4sqrtDv16_Dh(<16 x half> noundef %{{.+}}) #{{[0-9]+$}}{{$}} half16 call_sqrt_v16f16(half16 x) { return sqrt(x); } // DEFAULT: [[FPMATH]] = !{float 3.000000e+00} +// DEFAULT: [[HFPMATH]] = !{float 1.500000e+00} diff --git a/clang/test/CodeGenSYCL/function-attrs.cpp b/clang/test/CodeGenSYCL/function-attrs.cpp index 81f893644bc7c..5f3de41aa6584 100644 --- a/clang/test/CodeGenSYCL/function-attrs.cpp +++ b/clang/test/CodeGenSYCL/function-attrs.cpp @@ -5,11 +5,11 @@ int foo(); // CHECK-LABEL: define dso_local spir_func void @_Z3barv( -// CHECK-SAME: ) #[[ATTR2:[0-9]+]] { +// CHECK-SAME: ) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[A_ASCAST:%.*]] = addrspacecast ptr [[A]] to ptr addrspace(4) -// CHECK-NEXT: [[CALL:%.*]] = call spir_func noundef i32 @_Z3foov() #[[ATTR3:[0-9]+]] +// CHECK-NEXT: [[CALL:%.*]] = call spir_func noundef i32 @_Z3foov() #[[ATTR1:[0-9]+]] // CHECK-NEXT: store i32 [[CALL]], ptr addrspace(4) [[A_ASCAST]], align 4 // CHECK-NEXT: ret void // @@ -18,10 +18,8 @@ void bar() { } // CHECK-LABEL: define dso_local spir_func noundef i32 @_Z3foov( -// CHECK-SAME: ) #[[ATTR2]] { +// CHECK-SAME: ) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) // CHECK-NEXT: ret i32 1 // int foo() { @@ -38,8 +36,8 @@ int main() { return 0; } //. -// CHECK: attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -// CHECK: attributes #1 = { convergent nounwind } +// CHECK: attributes #[[ATTR0]] = { convergent mustprogress noinline norecurse nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +// CHECK: attributes #[[ATTR1]] = { convergent nounwind } //. -// CHECK: !{{[0-9]+}} = !{i32 1, !"wchar_size", i32 4} +// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} //. diff --git a/clang/test/DebugInfo/CXX/anon-union-vars.cpp b/clang/test/DebugInfo/CXX/anon-union-vars.cpp index 3aca4e199ab8d..547d31ce947e3 100644 --- a/clang/test/DebugInfo/CXX/anon-union-vars.cpp +++ b/clang/test/DebugInfo/CXX/anon-union-vars.cpp @@ -51,13 +51,13 @@ void instantiate(int x) { // CHECK: !DIGlobalVariable(name: "b",{{.*}} file: [[FILE]], line: 6,{{.*}} isLocal: true, isDefinition: true // CHECK: !DIGlobalVariable(name: "result", {{.*}} isLocal: false, isDefinition: true // CHECK: !DIGlobalVariable(name: "value", {{.*}} isLocal: false, isDefinition: true -// CHECK: !DILocalVariable(name: "i", {{.*}}, flags: DIFlagArtificial -// CHECK: !DILocalVariable(name: "c", {{.*}}, flags: DIFlagArtificial -// CHECK: !DILocalVariable( -// CHECK-NOT: name: -// CHECK: type: ![[UNION:[0-9]+]] -// CHECK: ![[UNION]] = distinct !DICompositeType(tag: DW_TAG_union_type, +// CHECK: ![[UNION:[0-9]+]] = distinct !DICompositeType(tag: DW_TAG_union_type, // CHECK-NOT: name: // CHECK: elements // CHECK: !DIDerivedType(tag: DW_TAG_member, name: "i", scope: ![[UNION]], // CHECK: !DIDerivedType(tag: DW_TAG_member, name: "c", scope: ![[UNION]], +// CHECK: !DILocalVariable(name: "i", {{.*}}, flags: DIFlagArtificial +// CHECK: !DILocalVariable(name: "c", {{.*}}, flags: DIFlagArtificial +// CHECK: !DILocalVariable( +// CHECK-NOT: name: +// CHECK-SAME: type: ![[UNION]] diff --git a/clang/test/DebugInfo/CXX/bpf-structors.cpp b/clang/test/DebugInfo/CXX/bpf-structors.cpp index c4c98486a776a..2291712b0c678 100644 --- a/clang/test/DebugInfo/CXX/bpf-structors.cpp +++ b/clang/test/DebugInfo/CXX/bpf-structors.cpp @@ -11,4 +11,4 @@ class Bar : public Foo { ~Bar() noexcept override; }; -// CHECK: declare !dbg !{{[0-9]+}} void @_ZN3FooD2Ev(ptr noundef nonnull align 8 dereferenceable(8)) +// CHECK: declare !dbg !{{[0-9]+}} void @_ZN3FooD2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8)) diff --git a/clang/test/DebugInfo/CXX/codeview-unnamed.cpp b/clang/test/DebugInfo/CXX/codeview-unnamed.cpp index 30815bda020ea..b625a80313c38 100644 --- a/clang/test/DebugInfo/CXX/codeview-unnamed.cpp +++ b/clang/test/DebugInfo/CXX/codeview-unnamed.cpp @@ -4,6 +4,60 @@ int main(int argc, char* argv[], char* arge[]) { // + // LINUX: [[TYPE_OF_ONE:![0-9]+]] = distinct !DICompositeType( + // LINUX-SAME: tag: DW_TAG_structure_type + // LINUX-NOT: name: + // LINUX-NOT: identifier: + // LINUX-SAME: ) + // + // MSVC: [[TYPE_OF_ONE:![0-9]+]] = distinct !DICompositeType + // MSVC-SAME: tag: DW_TAG_structure_type + // MSVC-SAME: name: "" + // MSVC-SAME: identifier: ".?AU@?1??main@@9@" + // MSVC-SAME: ) + + + // + // LINUX: [[TYPE_OF_TWO:![0-9]+]] = distinct !DICompositeType( + // LINUX-SAME: tag: DW_TAG_structure_type + // LINUX-NOT: name: + // LINUX-NOT: identifier: + // LINUX-SAME: ) + // + // MSVC: [[TYPE_OF_TWO:![0-9]+]] = distinct !DICompositeType + // MSVC-SAME: tag: DW_TAG_structure_type + // MSVC-SAME: name: "" + // MSVC-SAME: identifier: ".?AU@?2??main@@9@" + // MSVC-SAME: ) + + + // + // LINUX: [[TYPE_OF_THREE:![0-9]+]] = distinct !DICompositeType( + // LINUX-SAME: tag: DW_TAG_structure_type + // LINUX-SAME: name: "named" + // LINUX-NOT: identifier: + // LINUX-SAME: ) + // + // MSVC: [[TYPE_OF_THREE:![0-9]+]] = distinct !DICompositeType + // MSVC-SAME: tag: DW_TAG_structure_type + // MSVC-SAME: name: "named" + // MSVC-SAME: identifier: ".?AUnamed@?1??main@@9@" + // MSVC-SAME: ) + + // + // LINUX: [[TYPE_OF_FOUR:![0-9]+]] = distinct !DICompositeType( + // LINUX-SAME: tag: DW_TAG_class_type + // LINUX-NOT: name: + // LINUX-NOT: identifier: + // LINUX-SAME: ) + // + // MSVC: [[TYPE_OF_FOUR:![0-9]+]] = distinct !DICompositeType + // MSVC-SAME: tag: DW_TAG_class_type + // MSVC-SAME: name: "" + // MSVC-SAME: identifier: ".?AV@?0??main@@9@" + // MSVC-SAME: ) + + // In CodeView, the LF_MFUNCTION entry for "bar()" refers to the forward // reference of the unnamed struct. Visual Studio requires a unique // identifier to match the LF_STRUCTURE forward reference to the definition. @@ -11,21 +65,11 @@ int main(int argc, char* argv[], char* arge[]) { struct { void bar() {} } one; // // LINUX: !{{[0-9]+}} = !DILocalVariable(name: "one" - // LINUX-SAME: type: [[TYPE_OF_ONE:![0-9]+]] - // LINUX-SAME: ) - // LINUX: [[TYPE_OF_ONE]] = distinct !DICompositeType( - // LINUX-SAME: tag: DW_TAG_structure_type - // LINUX-NOT: name: - // LINUX-NOT: identifier: + // LINUX-SAME: type: [[TYPE_OF_ONE]] // LINUX-SAME: ) // // MSVC: !{{[0-9]+}} = !DILocalVariable(name: "one" - // MSVC-SAME: type: [[TYPE_OF_ONE:![0-9]+]] - // MSVC-SAME: ) - // MSVC: [[TYPE_OF_ONE]] = distinct !DICompositeType - // MSVC-SAME: tag: DW_TAG_structure_type - // MSVC-SAME: name: "" - // MSVC-SAME: identifier: ".?AU@?1??main@@9@" + // MSVC-SAME: type: [[TYPE_OF_ONE]] // MSVC-SAME: ) @@ -37,21 +81,11 @@ int main(int argc, char* argv[], char* arge[]) { int decltype(two)::*ptr2unnamed = &decltype(two)::bar; // // LINUX: !{{[0-9]+}} = !DILocalVariable(name: "two" - // LINUX-SAME: type: [[TYPE_OF_TWO:![0-9]+]] - // LINUX-SAME: ) - // LINUX: [[TYPE_OF_TWO]] = distinct !DICompositeType( - // LINUX-SAME: tag: DW_TAG_structure_type - // LINUX-NOT: name: - // LINUX-NOT: identifier: + // LINUX-SAME: type: [[TYPE_OF_TWO]] // LINUX-SAME: ) // // MSVC: !{{[0-9]+}} = !DILocalVariable(name: "two" - // MSVC-SAME: type: [[TYPE_OF_TWO:![0-9]+]] - // MSVC-SAME: ) - // MSVC: [[TYPE_OF_TWO]] = distinct !DICompositeType - // MSVC-SAME: tag: DW_TAG_structure_type - // MSVC-SAME: name: "" - // MSVC-SAME: identifier: ".?AU@?2??main@@9@" + // MSVC-SAME: type: [[TYPE_OF_TWO]] // MSVC-SAME: ) @@ -62,21 +96,11 @@ int main(int argc, char* argv[], char* arge[]) { struct named { int bar; int named::* p2mem; } three = { 42, &named::bar }; // // LINUX: !{{[0-9]+}} = !DILocalVariable(name: "three" - // LINUX-SAME: type: [[TYPE_OF_THREE:![0-9]+]] - // LINUX-SAME: ) - // LINUX: [[TYPE_OF_THREE]] = distinct !DICompositeType( - // LINUX-SAME: tag: DW_TAG_structure_type - // LINUX-SAME: name: "named" - // LINUX-NOT: identifier: + // LINUX-SAME: type: [[TYPE_OF_THREE]] // LINUX-SAME: ) // // MSVC: !{{[0-9]+}} = !DILocalVariable(name: "three" - // MSVC-SAME: type: [[TYPE_OF_THREE:![0-9]+]] - // MSVC-SAME: ) - // MSVC: [[TYPE_OF_THREE]] = distinct !DICompositeType - // MSVC-SAME: tag: DW_TAG_structure_type - // MSVC-SAME: name: "named" - // MSVC-SAME: identifier: ".?AUnamed@?1??main@@9@" + // MSVC-SAME: type: [[TYPE_OF_THREE]] // MSVC-SAME: ) @@ -88,21 +112,11 @@ int main(int argc, char* argv[], char* arge[]) { auto four = [argc](int i) -> int { return argc == i ? 1 : 0; }; // // LINUX: !{{[0-9]+}} = !DILocalVariable(name: "four" - // LINUX-SAME: type: [[TYPE_OF_FOUR:![0-9]+]] - // LINUX-SAME: ) - // LINUX: [[TYPE_OF_FOUR]] = distinct !DICompositeType( - // LINUX-SAME: tag: DW_TAG_class_type - // LINUX-NOT: name: - // LINUX-NOT: identifier: + // LINUX-SAME: type: [[TYPE_OF_FOUR]] // LINUX-SAME: ) // // MSVC: !{{[0-9]+}} = !DILocalVariable(name: "four" - // MSVC-SAME: type: [[TYPE_OF_FOUR:![0-9]+]] - // MSVC-SAME: ) - // MSVC: [[TYPE_OF_FOUR]] = distinct !DICompositeType - // MSVC-SAME: tag: DW_TAG_class_type - // MSVC-SAME: name: "" - // MSVC-SAME: identifier: ".?AV@?0??main@@9@" + // MSVC-SAME: type: [[TYPE_OF_FOUR]] // MSVC-SAME: ) return 0; diff --git a/clang/test/DebugInfo/CXX/gline-tables-only-codeview.cpp b/clang/test/DebugInfo/CXX/gline-tables-only-codeview.cpp index 6b9c9a243decd..122e4aa62ea7d 100644 --- a/clang/test/DebugInfo/CXX/gline-tables-only-codeview.cpp +++ b/clang/test/DebugInfo/CXX/gline-tables-only-codeview.cpp @@ -51,9 +51,9 @@ void test() { // CHECK-SAME: name: "", c.lambda_params(); - // CHECK: !DISubprogram(name: "operator()", scope: ![[LAMBDA1:[0-9]+]], - // CHECK: ![[LAMBDA1]] = !DICompositeType(tag: DW_TAG_class_type, + // CHECK: ![[LAMBDA1:[0-9]+]] = !DICompositeType(tag: DW_TAG_class_type, // CHECK-SAME: name: "", // CHECK-SAME: flags: DIFlagFwdDecl + // CHECK: !DISubprogram(name: "operator()", scope: ![[LAMBDA1]], c.lambda2(); } diff --git a/clang/test/DebugInfo/CXX/lambda-capture-packs.cpp b/clang/test/DebugInfo/CXX/lambda-capture-packs.cpp index 021b85d4ce3a4..609a71c6ec015 100644 --- a/clang/test/DebugInfo/CXX/lambda-capture-packs.cpp +++ b/clang/test/DebugInfo/CXX/lambda-capture-packs.cpp @@ -2,14 +2,6 @@ // RUN: -debug-info-kind=standalone -std=c++26 %s -o - | FileCheck %s -// CHECK: ![[PACK1:[0-9]+]] = distinct !DISubprogram(name: "capture_pack" -// CHECK: ![[PACK2:[0-9]+]] = distinct !DISubprogram(name: "capture_pack" -// CHECK: ![[PACK3:[0-9]+]] = distinct !DISubprogram(name: "capture_pack_and_locals" -// CHECK: ![[PACK4:[0-9]+]] = distinct !DISubprogram(name: "capture_pack_and_locals" -// CHECK: ![[PACK5:[0-9]+]] = distinct !DISubprogram(name: "capture_pack_and_this" -// CHECK: ![[PACK6:[0-9]+]] = distinct !DISubprogram(name: "capture_pack_and_this" -// CHECK: ![[PACK7:[0-9]+]] = distinct !DISubprogram(name: "capture_binding_and_param_pack" - template auto capture_pack(Args... args) { return [args..., ...params = args] { @@ -17,6 +9,7 @@ auto capture_pack(Args... args) { }(); } +// CHECK: ![[PACK1:[0-9]+]] = distinct !DISubprogram(name: "capture_pack" // CHECK: distinct !DICompositeType(tag: DW_TAG_class_type, scope: ![[PACK1]] // CHECK-SAME: elements: ![[PACK1_ELEMS:[0-9]+]] // CHECK-DAG: ![[PACK1_ELEMS]] = !{![[PACK1_ARGS:[0-9]+]], ![[PACK1_PARAMS:[0-9]+]]} @@ -24,6 +17,7 @@ auto capture_pack(Args... args) { // CHECK-DAG: ![[PACK1_PARAMS]] = !DIDerivedType(tag: DW_TAG_member, name: "params" // CHECK-NOT: DW_TAG_member +// CHECK: ![[PACK2:[0-9]+]] = distinct !DISubprogram(name: "capture_pack" // CHECK: distinct !DICompositeType(tag: DW_TAG_class_type, scope: ![[PACK2]] // CHECK-SAME: elements: ![[PACK2_ELEMS:[0-9]+]] // CHECK: ![[PACK2_ELEMS]] = !{![[PACK2_ARGS:[0-9]+]] @@ -42,6 +36,7 @@ auto capture_pack_and_locals(int x, Args... args) { }(); } +// CHECK: ![[PACK3:[0-9]+]] = distinct !DISubprogram(name: "capture_pack_and_locals" // CHECK: distinct !DICompositeType(tag: DW_TAG_class_type, scope: ![[PACK3]] // CHECK-SAME: elements: ![[PACK3_ELEMS:[0-9]+]] // CHECK: ![[PACK3_ELEMS]] = !{![[PACK3_ARGS:[0-9]+]] @@ -55,6 +50,7 @@ auto capture_pack_and_locals(int x, Args... args) { // CHECK-DAG: ![[PACK3_W]] = !DIDerivedType(tag: DW_TAG_member, name: "w" // CHECK-NOT: DW_TAG_member +// CHECK: ![[PACK4:[0-9]+]] = distinct !DISubprogram(name: "capture_pack_and_locals" // CHECK: distinct !DICompositeType(tag: DW_TAG_class_type, scope: ![[PACK4]] // CHECK-SAME: elements: ![[PACK4_ELEMS:[0-9]+]] // CHECK: ![[PACK4_ELEMS]] = !{![[PACK4_ARGS:[0-9]+]] @@ -90,6 +86,7 @@ struct Foo { int w = 10; } f; +// CHECK: ![[PACK5:[0-9]+]] = distinct !DISubprogram(name: "capture_pack_and_this" // CHECK: distinct !DICompositeType(tag: DW_TAG_class_type, scope: ![[PACK5]] // CHECK-SAME: elements: ![[PACK5a_ELEMS:[0-9]+]] // CHECK: ![[PACK5a_ELEMS]] = !{![[PACK5a_THIS:[0-9]+]] @@ -120,6 +117,7 @@ struct Foo { // CHECK-DAG: ![[PACK5c_THIS]] = !DIDerivedType(tag: DW_TAG_member, name: "this" // CHECK-NOT: DW_TAG_member +// CHECK: ![[PACK6:[0-9]+]] = distinct !DISubprogram(name: "capture_pack_and_this" // CHECK: distinct !DICompositeType(tag: DW_TAG_class_type, scope: ![[PACK6]] // CHECK-SAME: elements: ![[PACK6a_ELEMS:[0-9]+]] // CHECK: ![[PACK6a_ELEMS]] = !{![[PACK6a_THIS:[0-9]+]] @@ -168,6 +166,7 @@ auto capture_binding_and_param_pack(Args... args) { }(); } +// CHECK: ![[PACK7:[0-9]+]] = distinct !DISubprogram(name: "capture_binding_and_param_pack" // CHECK: distinct !DICompositeType(tag: DW_TAG_structure_type, name: "C" // CHECK: distinct !DICompositeType(tag: DW_TAG_class_type, scope: ![[PACK7]] // CHECK-SAME: elements: ![[PACK7_ELEMS:[0-9]+]] diff --git a/clang/test/DebugInfo/CXX/lambda-this.cpp b/clang/test/DebugInfo/CXX/lambda-this.cpp index 019d09c48f858..1df210953ac2e 100644 --- a/clang/test/DebugInfo/CXX/lambda-this.cpp +++ b/clang/test/DebugInfo/CXX/lambda-this.cpp @@ -13,10 +13,10 @@ void D::d(int x) { } // CHECK: ![[D:[0-9]+]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "D", -// CHECK: ![[POINTER:.*]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: ![[D]], size: 64) // CHECK: !DIDerivedType(tag: DW_TAG_member, name: "this", // CHECK-SAME: line: 11 -// CHECK-SAME: baseType: ![[POINTER]] +// CHECK-SAME: baseType: ![[POINTER:[0-9]+]] // CHECK-SAME: size: 64 // CHECK-NOT: offset: 0 // CHECK-SAME: ){{$}} +// CHECK: ![[POINTER]] = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: ![[D]], size: 64) diff --git a/clang/test/DebugInfo/CXX/trivial_abi.cpp b/clang/test/DebugInfo/CXX/trivial_abi.cpp index 3e486140b8acd..17173688e27d4 100644 --- a/clang/test/DebugInfo/CXX/trivial_abi.cpp +++ b/clang/test/DebugInfo/CXX/trivial_abi.cpp @@ -20,7 +20,7 @@ struct __attribute__((trivial_abi)) Trivial { // CHECK-NEXT: [[NRVO_VAL:%.*]] = load i1, ptr [[NRVO]], align 1, !dbg [[DBG22:![0-9]+]] // CHECK-NEXT: br i1 [[NRVO_VAL]], label [[NRVO_SKIPDTOR:%.*]], label [[NRVO_UNUSED:%.*]], !dbg [[DBG22]] // CHECK: nrvo.unused: -// CHECK-NEXT: call void @_ZN7TrivialD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[RETVAL]]) #[[ATTR1]], !dbg [[DBG22]] +// CHECK-NEXT: call void @_ZN7TrivialD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[RETVAL]]) #[[ATTR1]], !dbg [[DBG22]] // CHECK-NEXT: br label [[NRVO_SKIPDTOR]], !dbg [[DBG22]] // CHECK: nrvo.skipdtor: // CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_TRIVIAL]], ptr [[RETVAL]], i32 0, i32 0, !dbg [[DBG22]] diff --git a/clang/test/DebugInfo/Generic/codeview-unnamed.c b/clang/test/DebugInfo/Generic/codeview-unnamed.c index 0df6e1a0419bb..7b88f53a92e42 100644 --- a/clang/test/DebugInfo/Generic/codeview-unnamed.c +++ b/clang/test/DebugInfo/Generic/codeview-unnamed.c @@ -8,23 +8,23 @@ int main(int argc, char* argv[], char* arge[]) { // struct { int bar; } one = {42}; // - // LINUX: !{{[0-9]+}} = !DILocalVariable(name: "one" - // LINUX-SAME: type: [[TYPE_OF_ONE:![0-9]+]] - // LINUX-SAME: ) - // LINUX: [[TYPE_OF_ONE]] = distinct !DICompositeType( + // LINUX: [[TYPE_OF_ONE:![0-9]+]] = distinct !DICompositeType( // LINUX-SAME: tag: DW_TAG_structure_type // LINUX-NOT: name: // LINUX-NOT: identifier: // LINUX-SAME: ) + // LINUX: !{{[0-9]+}} = !DILocalVariable(name: "one" + // LINUX-SAME: type: [[TYPE_OF_ONE]] + // LINUX-SAME: ) // - // MSVC: !{{[0-9]+}} = !DILocalVariable(name: "one" - // MSVC-SAME: type: [[TYPE_OF_ONE:![0-9]+]] - // MSVC-SAME: ) - // MSVC: [[TYPE_OF_ONE]] = distinct !DICompositeType + // MSVC: [[TYPE_OF_ONE:![0-9]+]] = distinct !DICompositeType // MSVC-SAME: tag: DW_TAG_structure_type // MSVC-NOT: name: // MSVC-NOT: identifier: // MSVC-SAME: ) + // MSVC: !{{[0-9]+}} = !DILocalVariable(name: "one" + // MSVC-SAME: type: [[TYPE_OF_ONE]] + // MSVC-SAME: ) return 0; } diff --git a/clang/test/DebugInfo/Generic/unused-types.c b/clang/test/DebugInfo/Generic/unused-types.c index 3e9f7b07658e3..31d608d92a06b 100644 --- a/clang/test/DebugInfo/Generic/unused-types.c +++ b/clang/test/DebugInfo/Generic/unused-types.c @@ -18,13 +18,15 @@ void quux(void) { // CHECK: !DICompileUnit{{.+}}retainedTypes: [[RETTYPES:![0-9]+]] // CHECK: [[TYPE0:![0-9]+]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "bar" // CHECK: [[TYPE1:![0-9]+]] = !DIEnumerator(name: "BAR" -// CHECK: [[TYPE2:![0-9]+]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "z" -// CHECK: [[TYPE3:![0-9]+]] = !DIEnumerator(name: "Z" -// CHECK: [[RETTYPES]] = !{[[TYPE4:![0-9]+]], [[TYPE5:![0-9]+]], [[TYPE0]], [[TYPE6:![0-9]+]], {{![0-9]+}}, [[TYPE7:![0-9]+]], [[TYPE2]], [[TYPE8:![0-9]+]]} -// CHECK: [[TYPE4]] = !DIDerivedType(tag: DW_TAG_typedef, name: "my_int" -// CHECK: [[TYPE5]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo" -// CHECK: [[TYPE6]] = distinct !DICompositeType(tag: DW_TAG_union_type, name: "baz" -// CHECK: [[TYPE7]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "y" +// CHECK: [[RETTYPES]] = !{[[TYPE2:![0-9]+]], [[TYPE3:![0-9]+]], [[TYPE0]], [[TYPE4:![0-9]+]], {{![0-9]+}}} +// CHECK: [[TYPE2]] = !DIDerivedType(tag: DW_TAG_typedef, name: "my_int" +// CHECK: [[TYPE3]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "foo" +// CHECK: [[TYPE4]] = distinct !DICompositeType(tag: DW_TAG_union_type, name: "baz" +// CHECK: [[SP:![0-9]+]] = distinct !DISubprogram(name: "quux", {{.*}}, retainedNodes: [[SPRETNODES:![0-9]+]] +// CHECK: [[SPRETNODES]] = !{[[TYPE5:![0-9]+]], [[TYPE6:![0-9]+]], [[TYPE8:![0-9]+]]} +// CHECK: [[TYPE5]] = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "y" +// CHECK: [[TYPE6]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "z" +// CHECK: [[TYPE7:![0-9]+]] = !DIEnumerator(name: "Z" // CHECK: [[TYPE8]] = distinct !DICompositeType(tag: DW_TAG_union_type, name: "w" // Check that debug info is not emitted for the typedef, struct, enum, and diff --git a/clang/test/DebugInfo/Generic/unused-types.cpp b/clang/test/DebugInfo/Generic/unused-types.cpp index 023cac159faa4..5b01c6dbb3941 100644 --- a/clang/test/DebugInfo/Generic/unused-types.cpp +++ b/clang/test/DebugInfo/Generic/unused-types.cpp @@ -13,12 +13,14 @@ void quux() { // CHECK: !DICompileUnit{{.+}}retainedTypes: [[RETTYPES:![0-9]+]] // CHECK: [[TYPE0:![0-9]+]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "baz" // CHECK: [[TYPE1:![0-9]+]] = !DIEnumerator(name: "BAZ" -// CHECK: [[TYPE2:![0-9]+]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "z" -// CHECK: [[TYPE3:![0-9]+]] = !DIEnumerator(name: "Z" -// CHECK: [[RETTYPES]] = !{[[TYPE4:![0-9]+]], [[TYPE5:![0-9]+]], [[TYPE0]], {{![0-9]+}}, [[TYPE6:![0-9]+]], [[TYPE2]]} -// CHECK: [[TYPE4]] = !DIDerivedType(tag: DW_TAG_typedef, name: "foo" -// CHECK: [[TYPE5]] = distinct !DICompositeType(tag: DW_TAG_class_type, name: "bar" -// CHECK: [[TYPE6]] = distinct !DICompositeType(tag: DW_TAG_class_type, name: "y" +// CHECK: [[RETTYPES]] = !{[[TYPE2:![0-9]+]], [[TYPE3:![0-9]+]], [[TYPE0]], {{![0-9]+}}} +// CHECK: [[TYPE2]] = !DIDerivedType(tag: DW_TAG_typedef, name: "foo" +// CHECK: [[TYPE3]] = distinct !DICompositeType(tag: DW_TAG_class_type, name: "bar" +// CHECK: [[SP:![0-9]+]] = distinct !DISubprogram(name: "quux", {{.*}}, retainedNodes: [[SPRETNODES:![0-9]+]] +// CHECK: [[SPRETNODES]] = !{[[TYPE4:![0-9]+]], [[TYPE5:![0-9]+]]} +// CHECK: [[TYPE4]] = distinct !DICompositeType(tag: DW_TAG_class_type, name: "y", scope: [[SP]] +// CHECK: [[TYPE5]] = !DICompositeType(tag: DW_TAG_enumeration_type, name: "z", scope: [[SP]] +// CHECK: [[TYPE6:![0-9]+]] = !DIEnumerator(name: "Z" // NODBG-NOT: !DI{{CompositeType|Enumerator|DerivedType}} diff --git a/clang/test/Driver/Inputs/hipspv/lib/hip-device-lib/hipspv-spirv64-unknown-chipstar.bc b/clang/test/Driver/Inputs/hipspv/lib/hip-device-lib/hipspv-spirv64-unknown-chipstar.bc new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/crtbegin.o new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib32/ilp32/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib32/ilp32/crtbegin.o new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib32/ilp32d/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib32/ilp32d/crtbegin.o new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib64/lp64/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib64/lp64/crtbegin.o new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib64/lp64d/crtbegin.o b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib64/lp64d/crtbegin.o new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/riscv64be-unknown-linux-gnu/bin/ld b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/riscv64be-unknown-linux-gnu/bin/ld new file mode 100755 index 0000000000000..25b914c0f79f3 --- /dev/null +++ b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/riscv64be-unknown-linux-gnu/bin/ld @@ -0,0 +1 @@ +#\!/bin/true diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib32/ilp32/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib32/ilp32/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib32/ilp32d/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib32/ilp32d/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib64/lp64/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib64/lp64/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib64/lp64d/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib64/lp64d/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib32/ilp32/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib32/ilp32/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib32/ilp32d/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib32/ilp32d/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib64/lp64/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib64/lp64/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib64/lp64d/.keep b/clang/test/Driver/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib64/lp64d/.keep new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/clang/test/Driver/amdgpu-macros.cl b/clang/test/Driver/amdgpu-macros.cl index 6105fd0d8d3e0..67eb97e1be845 100644 --- a/clang/test/Driver/amdgpu-macros.cl +++ b/clang/test/Driver/amdgpu-macros.cl @@ -128,6 +128,7 @@ // RUN: %clang -E -dM -target amdgcn -mcpu=gfx1151 %s 2>&1 | FileCheck --check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx1151 -DFAMILY=GFX11 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx1152 %s 2>&1 | FileCheck --check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx1152 -DFAMILY=GFX11 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx1153 %s 2>&1 | FileCheck --check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx1153 -DFAMILY=GFX11 +// RUN: %clang -E -dM -target amdgcn -mcpu=gfx1170 %s 2>&1 | FileCheck --check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx1170 -DFAMILY=GFX11 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck --check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx1200 -DFAMILY=GFX12 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx1201 %s 2>&1 | FileCheck --check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx1201 -DFAMILY=GFX12 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx1250 %s 2>&1 | FileCheck --check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx1250 -DFAMILY=GFX12 diff --git a/clang/test/Driver/amdgpu-mcpu.cl b/clang/test/Driver/amdgpu-mcpu.cl index 12f4bed5120be..2a6ccf96a2cdc 100644 --- a/clang/test/Driver/amdgpu-mcpu.cl +++ b/clang/test/Driver/amdgpu-mcpu.cl @@ -113,6 +113,7 @@ // RUN: %clang -### -target amdgcn -mcpu=gfx1151 %s 2>&1 | FileCheck --check-prefix=GFX1151 %s // RUN: %clang -### -target amdgcn -mcpu=gfx1152 %s 2>&1 | FileCheck --check-prefix=GFX1152 %s // RUN: %clang -### -target amdgcn -mcpu=gfx1153 %s 2>&1 | FileCheck --check-prefix=GFX1153 %s +// RUN: %clang -### -target amdgcn -mcpu=gfx1170 %s 2>&1 | FileCheck --check-prefix=GFX1170 %s // RUN: %clang -### -target amdgcn -mcpu=gfx1200 %s 2>&1 | FileCheck --check-prefix=GFX1200 %s // RUN: %clang -### -target amdgcn -mcpu=gfx1201 %s 2>&1 | FileCheck --check-prefix=GFX1201 %s // RUN: %clang -### -target amdgcn -mcpu=gfx1250 %s 2>&1 | FileCheck --check-prefix=GFX1250 %s @@ -170,6 +171,7 @@ // GFX1151: "-target-cpu" "gfx1151" // GFX1152: "-target-cpu" "gfx1152" // GFX1153: "-target-cpu" "gfx1153" +// GFX1170: "-target-cpu" "gfx1170" // GFX1200: "-target-cpu" "gfx1200" // GFX1201: "-target-cpu" "gfx1201" // GFX1250: "-target-cpu" "gfx1250" diff --git a/clang/test/Driver/clang-sycl-linker-test.cpp b/clang/test/Driver/clang-sycl-linker-test.cpp index 8d26dc074b5e3..55f56bd2958f7 100644 --- a/clang/test/Driver/clang-sycl-linker-test.cpp +++ b/clang/test/Driver/clang-sycl-linker-test.cpp @@ -8,7 +8,7 @@ // RUN: clang-sycl-linker --dry-run -v -triple=spirv64 %t_1.bc %t_2.bc -o a.spv 2>&1 \ // RUN: | FileCheck %s --check-prefix=SIMPLE-FO // SIMPLE-FO: sycl-device-link: inputs: {{.*}}.bc, {{.*}}.bc libfiles: output: [[LLVMLINKOUT:.*]].bc -// SIMPLE-FO-NEXT: SPIR-V Backend: input: [[LLVMLINKOUT]].bc, output: a_0.spv +// SIMPLE-FO-NEXT: LLVM backend: input: [[LLVMLINKOUT]].bc, output: a_0.spv // // Test the dry run of a simple case with device library files specified. // RUN: mkdir -p %t.dir @@ -17,7 +17,7 @@ // RUN: clang-sycl-linker --dry-run -v -triple=spirv64 %t_1.bc %t_2.bc --library-path=%t.dir --device-libs=lib1.bc,lib2.bc -o a.spv 2>&1 \ // RUN: | FileCheck %s --check-prefix=DEVLIBS // DEVLIBS: sycl-device-link: inputs: {{.*}}.bc libfiles: {{.*}}lib1.bc, {{.*}}lib2.bc output: [[LLVMLINKOUT:.*]].bc -// DEVLIBS-NEXT: SPIR-V Backend: input: [[LLVMLINKOUT]].bc, output: a_0.spv +// DEVLIBS-NEXT: LLVM backend: input: [[LLVMLINKOUT]].bc, output: a_0.spv // // Test a simple case with a random file (not bitcode) as input. // RUN: touch %t.o @@ -38,7 +38,7 @@ // RUN: --ocloc-options="-a -b" \ // RUN: | FileCheck %s --check-prefix=AOT-INTEL-GPU // AOT-INTEL-GPU: sycl-device-link: inputs: {{.*}}.bc, {{.*}}.bc libfiles: output: [[LLVMLINKOUT:.*]].bc -// AOT-INTEL-GPU-NEXT: SPIR-V Backend: input: [[LLVMLINKOUT]].bc, output: [[SPIRVTRANSLATIONOUT:.*]]_0.spv +// AOT-INTEL-GPU-NEXT: LLVM backend: input: [[LLVMLINKOUT]].bc, output: [[SPIRVTRANSLATIONOUT:.*]]_0.spv // AOT-INTEL-GPU-NEXT: "{{.*}}ocloc{{.*}}" {{.*}}-device bmg_g21 -a -b {{.*}}-output a_0.out -file [[SPIRVTRANSLATIONOUT]]_0.spv // // Test AOT compilation for an Intel CPU. @@ -46,7 +46,7 @@ // RUN: --opencl-aot-options="-a -b" \ // RUN: | FileCheck %s --check-prefix=AOT-INTEL-CPU // AOT-INTEL-CPU: sycl-device-link: inputs: {{.*}}.bc, {{.*}}.bc libfiles: output: [[LLVMLINKOUT:.*]].bc -// AOT-INTEL-CPU-NEXT: SPIR-V Backend: input: [[LLVMLINKOUT]].bc, output: [[SPIRVTRANSLATIONOUT:.*]]_0.spv +// AOT-INTEL-CPU-NEXT: LLVM backend: input: [[LLVMLINKOUT]].bc, output: [[SPIRVTRANSLATIONOUT:.*]]_0.spv // AOT-INTEL-CPU-NEXT: "{{.*}}opencl-aot{{.*}}" {{.*}}--device=cpu -a -b {{.*}}-o a_0.out [[SPIRVTRANSLATIONOUT]]_0.spv // // Check that the output file must be specified. diff --git a/clang/test/Driver/darwin-fapple-link-rtlib.c b/clang/test/Driver/darwin-fapple-link-rtlib.c index 394f583331d74..4861304b3fc99 100644 --- a/clang/test/Driver/darwin-fapple-link-rtlib.c +++ b/clang/test/Driver/darwin-fapple-link-rtlib.c @@ -1,6 +1,9 @@ // RUN: %clang -target arm64-apple-ios12.0 %s -nostdlib -fapple-link-rtlib -resource-dir=%S/Inputs/resource_dir -### 2>&1 | FileCheck %s // RUN: %clang -target arm64-apple-ios12.0 %s -static -fapple-link-rtlib -resource-dir=%S/Inputs/resource_dir -### 2>&1 | FileCheck %s // RUN: %clang -target arm64-apple-ios12.0 %s -fapple-link-rtlib -resource-dir=%S/Inputs/resource_dir -### 2>&1 | FileCheck %s --check-prefix=DEFAULT +// RUN: %clang -target arm64-apple-firmware %s -static -fapple-link-rtlib -resource-dir=%S/Inputs/resource_dir -### 2>&1 | FileCheck %s --check-prefix=FIRMWARE // CHECK-NOT: "-lSystem" // DEFAULT: "-lSystem" // CHECK: libclang_rt.ios.a +// FIRMWARE-NOT: "-lSystem" +// FIRMWARE: libclang_rt.soft_static.a diff --git a/clang/test/Driver/darwin-ld-lto.c b/clang/test/Driver/darwin-ld-lto.c index b96d5ab30b496..6473248dfabdd 100644 --- a/clang/test/Driver/darwin-ld-lto.c +++ b/clang/test/Driver/darwin-ld-lto.c @@ -46,3 +46,8 @@ // RUN: FileCheck --check-prefix=KEXT %s // KEXT: {{ld(.exe)?"}} // KEXT: "-mllvm" "-disable-atexit-based-global-dtor-lowering" + +// Check that we select a filename for -fstack-usage. +// RUN: %clang --target=arm64-apple-darwin %s -flto -fstack-usage -o foo \ +// RUN: -### 2>&1 | FileCheck --check-prefix=STACKUSAGE %s +// STACKUSAGE: "-mllvm" "-stack-usage-file=foo.su" diff --git a/clang/test/Driver/darwin-ld.c b/clang/test/Driver/darwin-ld.c index 9a8d98cdb9c2c..cf89bdd4dac00 100644 --- a/clang/test/Driver/darwin-ld.c +++ b/clang/test/Driver/darwin-ld.c @@ -198,6 +198,16 @@ // LINK_DRIVERKIT-NOT: lSystem // LINK_DRIVERKIT: libclang_rt.driverkit.a +// RUN: %clang -target arm64-apple-firmware1.0 -fuse-ld= -mlinker-version=400 -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log +// RUN: FileCheck -check-prefix=LINK_FIRMWARE %s < %t.log +// RUN: %clang -target arm64-apple-firmware1.0 -static -fuse-ld= -mlinker-version=400 -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log +// RUN: FileCheck -check-prefix=LINK_FIRMWARE %s < %t.log +// LINK_FIRMWARE: {{ld(.exe)?"}} +// LINK_FIRMWARE-NOT: crt +// LINK_FIRMWARE-NOT: lgcc_s.1 +// LINK_FIRMWARE-NOT: lSystem +// LINK_FIRMWARE: libclang_rt.soft_static.a + // RUN: %clang -target armv7k-apple-watchos2.0 -fuse-ld= -mlinker-version=400 -mwatchos-version-min=2.0 -resource-dir=%S/Inputs/resource_dir -### %t.o 2> %t.log // RUN: FileCheck -check-prefix=LINK_WATCHOS_ARM %s < %t.log // LINK_WATCHOS_ARM: {{ld(.exe)?"}} diff --git a/clang/test/Driver/fdefine-target-os-macros.c b/clang/test/Driver/fdefine-target-os-macros.c index a4de51e8e7244..07755d01f9a52 100644 --- a/clang/test/Driver/fdefine-target-os-macros.c +++ b/clang/test/Driver/fdefine-target-os-macros.c @@ -19,7 +19,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-ios %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -35,7 +36,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-ios-macabi %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -51,7 +53,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-ios-simulator %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -67,7 +70,8 @@ // RUN: -DSIMULATOR=1 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-tvos %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -83,7 +87,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-tvos-simulator %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -99,7 +104,8 @@ // RUN: -DSIMULATOR=1 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-watchos %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -115,7 +121,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-watchos-simulator %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -131,7 +138,8 @@ // RUN: -DSIMULATOR=1 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-xros %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -147,7 +155,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-xros-simulator %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -163,7 +172,8 @@ // RUN: -DSIMULATOR=1 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=arm64-apple-driverkit %s 2>&1 \ // RUN: | FileCheck %s -DMAC=1 \ @@ -179,7 +189,25 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 + +// RUN: %clang -dM -E --target=arm64-apple-firmware %s 2>&1 \ +// RUN: | FileCheck %s -DMAC=1 \ +// RUN: -DOSX=0 \ +// RUN: -DIPHONE=0 \ +// RUN: -DIOS=0 \ +// RUN: -DTV=0 \ +// RUN: -DWATCH=0 \ +// RUN: -DVISION=0 \ +// RUN: -DDRIVERKIT=0 \ +// RUN: -DMACCATALYST=0 \ +// RUN: -DEMBEDDED=0 \ +// RUN: -DSIMULATOR=0 \ +// RUN: -DWINDOWS=0 \ +// RUN: -DLINUX=0 \ +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=1 // RUN: %clang -dM -E --target=x86_64-pc-linux-gnu \ // RUN: -fdefine-target-os-macros %s 2>&1 \ @@ -196,7 +224,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=1 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=x86_64-pc-win32 \ // RUN: -fdefine-target-os-macros %s 2>&1 \ @@ -213,7 +242,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=1 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=x86_64-pc-windows-gnu \ // RUN: -fdefine-target-os-macros %s 2>&1 \ @@ -230,7 +260,8 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=1 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=0 +// RUN: -DUNIX=0 \ +// RUN: -DFIRMWARE=0 // RUN: %clang -dM -E --target=sparc-none-solaris \ // RUN: -fdefine-target-os-macros %s 2>&1 \ @@ -247,7 +278,11 @@ // RUN: -DSIMULATOR=0 \ // RUN: -DWINDOWS=0 \ // RUN: -DLINUX=0 \ -// RUN: -DUNIX=1 +// RUN: -DUNIX=1 \ +// RUN: -DFIRMWARE=0 + +// If the firmware OS was valid for a non-Apple vendor, +// it would be TARGET_OS_MAC=0, TARGET_OS_FIRMWARE=1. // RUN: %clang -dM -E --target=arm64-apple-macos \ // RUN: -fno-define-target-os-macros %s 2>&1 \ @@ -285,3 +320,4 @@ // CHECK-DAG: #define TARGET_OS_WINDOWS [[WINDOWS]] // CHECK-DAG: #define TARGET_OS_LINUX [[LINUX]] // CHECK-DAG: #define TARGET_OS_UNIX [[UNIX]] +// CHECK-DAG: #define TARGET_OS_FIRMWARE [[FIRMWARE]] diff --git a/clang/test/Driver/hip-rdc-device-only.hip b/clang/test/Driver/hip-rdc-device-only.hip index f5d83d013c86a..d74de571e3a32 100644 --- a/clang/test/Driver/hip-rdc-device-only.hip +++ b/clang/test/Driver/hip-rdc-device-only.hip @@ -66,7 +66,7 @@ // EMITBC-SAME: "-emit-llvm-bc" // EMITLL-SAME: "-emit-llvm" // COMMON-SAME: {{.*}} "-main-file-name" "a.cu" -// COMMON-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// COMMON-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fvisibility=hidden" // COMMON-SAME: "-fapply-global-visibility-to-externs" // COMMON-SAME: "-target-cpu" "gfx803" // COMMON-SAME: "-fgpu-rdc" @@ -79,7 +79,7 @@ // EMITBC-SAME: "-emit-llvm-bc" // EMITLL-SAME: "-emit-llvm" // COMMON-SAME: {{.*}} "-main-file-name" "a.cu" -// COMMON-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// COMMON-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fvisibility=hidden" // COMMON-SAME: "-fapply-global-visibility-to-externs" // COMMON-SAME: "-target-cpu" "gfx900" // COMMON-SAME: "-fgpu-rdc" @@ -96,7 +96,7 @@ // EMITBC-SAME: "-emit-llvm-bc" // EMITLL-SAME: "-emit-llvm" // COMMON-SAME: {{.*}} "-main-file-name" "b.hip" -// COMMON-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// COMMON-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fvisibility=hidden" // COMMON-SAME: "-fapply-global-visibility-to-externs" // COMMON-SAME: "-target-cpu" "gfx803" // COMMON-SAME: "-fgpu-rdc" @@ -109,7 +109,7 @@ // EMITBC-SAME: "-emit-llvm-bc" // EMITLL-SAME: "-emit-llvm" // COMMON-SAME: {{.*}} "-main-file-name" "b.hip" -// COMMON-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// COMMON-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fvisibility=hidden" // COMMON-SAME: "-fapply-global-visibility-to-externs" // COMMON-SAME: "-target-cpu" "gfx900" // COMMON-SAME: "-fgpu-rdc" diff --git a/clang/test/Driver/hip-toolchain-no-rdc.hip b/clang/test/Driver/hip-toolchain-no-rdc.hip index bc560330d5696..fb4e7ef9a3f12 100644 --- a/clang/test/Driver/hip-toolchain-no-rdc.hip +++ b/clang/test/Driver/hip-toolchain-no-rdc.hip @@ -51,7 +51,7 @@ // NEW-SAME: "-emit-llvm-bc" // CHECK-SAME: {{.*}} "-main-file-name" "a.cu" // CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-mllvm" "-amdgpu-internalize-symbols" -// CHECK-SAME: "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// CHECK-SAME: "-fvisibility=hidden" // CHECK-SAME: "-fapply-global-visibility-to-externs" // CHECK-SAME: "{{.*}}lib1.bc" "{{.*}}lib2.bc" // CHECK-SAME: "-target-cpu" "gfx803" @@ -74,7 +74,7 @@ // CHECK-SAME: "-emit-{{(obj|llvm-bc)}}" // CHECK-SAME: {{.*}} "-main-file-name" "a.cu" // CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-mllvm" "-amdgpu-internalize-symbols" -// CHECK-SAME: "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// CHECK-SAME: "-fvisibility=hidden" // CHECK-SAME: "-fapply-global-visibility-to-externs" // CHECK-SAME: "{{.*}}lib1.bc" "{{.*}}lib2.bc" // CHECK-SAME: "-target-cpu" "gfx900" @@ -123,7 +123,7 @@ // CHECK-SAME: "-emit-{{(obj|llvm-bc)}}" // CHECK-SAME: {{.*}} "-main-file-name" "b.hip" // CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-mllvm" "-amdgpu-internalize-symbols" -// CHECK-SAME: "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// CHECK-SAME: "-fvisibility=hidden" // CHECK-SAME: "-fapply-global-visibility-to-externs" // CHECK-SAME: "{{.*}}lib1.bc" "{{.*}}lib2.bc" // CHECK-SAME: "-target-cpu" "gfx803" @@ -146,7 +146,7 @@ // CHECK-SAME: "-emit-{{(obj|llvm-bc)}}" // CHECK-SAME: {{.*}} "-main-file-name" "b.hip" // CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-mllvm" "-amdgpu-internalize-symbols" -// CHECK-SAME: "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// CHECK-SAME: "-fvisibility=hidden" // CHECK-SAME: "-fapply-global-visibility-to-externs" // CHECK-SAME: "{{.*}}lib1.bc" "{{.*}}lib2.bc" // CHECK-SAME: "-target-cpu" "gfx900" diff --git a/clang/test/Driver/hip-toolchain-rdc-separate.hip b/clang/test/Driver/hip-toolchain-rdc-separate.hip index d3c7d2d5be55b..574a23db36a79 100644 --- a/clang/test/Driver/hip-toolchain-rdc-separate.hip +++ b/clang/test/Driver/hip-toolchain-rdc-separate.hip @@ -13,7 +13,7 @@ // CHECK-SAME: "-aux-triple" "x86_64-unknown-linux-gnu" // CHECK-SAME: "-emit-llvm-bc" // CHECK-SAME: {{.*}} "-main-file-name" "a.cu" -// CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fvisibility=hidden" // CHECK-SAME: "-fapply-global-visibility-to-externs" // CHECK-SAME: "{{.*}}lib1.bc" "{{.*}}lib2.bc" // CHECK-SAME: "-target-cpu" "gfx803" @@ -48,7 +48,7 @@ // CHECK-SAME: "-aux-triple" "x86_64-unknown-linux-gnu" // CHECK-SAME: "-emit-llvm-bc" // CHECK-SAME: {{.*}} "-main-file-name" "b.hip" -// CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fvisibility=hidden" // CHECK-SAME: "-fapply-global-visibility-to-externs" // CHECK-SAME: "{{.*}}lib1.bc" "{{.*}}lib2.bc" // CHECK-SAME: "-target-cpu" "gfx803" diff --git a/clang/test/Driver/hip-toolchain-rdc.hip b/clang/test/Driver/hip-toolchain-rdc.hip index 204400aeaa15d..75d8f889a35a9 100644 --- a/clang/test/Driver/hip-toolchain-rdc.hip +++ b/clang/test/Driver/hip-toolchain-rdc.hip @@ -93,7 +93,7 @@ // CHECK-SAME: "-aux-triple" [[HOST:"x86_64-[^"]+"]] // CHECK-SAME: "-emit-llvm-bc" // CHECK-SAME: {{.*}} "-main-file-name" "a.cu" -// CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fvisibility=hidden" // CHECK-SAME: "-fapply-global-visibility-to-externs" // CHECK-SAME: "{{.*}}lib1.bc" "{{.*}}lib2.bc" // CHECK-SAME: "-target-cpu" "gfx803" @@ -105,7 +105,7 @@ // CHECK-SAME: "-aux-triple" [[HOST]] // CHECK-SAME: "-emit-llvm-bc" // CHECK-SAME: {{.*}} "-main-file-name" "b.hip" -// CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fcuda-allow-variadic-functions" "-fvisibility=hidden" +// CHECK-SAME: "-fcuda-is-device" "-fno-threadsafe-statics" "-fvisibility=hidden" // CHECK-SAME: "-fapply-global-visibility-to-externs" // CHECK-SAME: "{{.*}}lib1.bc" "{{.*}}lib2.bc" // CHECK-SAME: "-target-cpu" "gfx803" diff --git a/clang/test/Driver/hipspv-device-libs.hip b/clang/test/Driver/hipspv-device-libs.hip index 9d6af54b10255..71bf0897e39dd 100644 --- a/clang/test/Driver/hipspv-device-libs.hip +++ b/clang/test/Driver/hipspv-device-libs.hip @@ -6,7 +6,7 @@ // Test --hip-device-lib-path // RUN: %clang -### -target x86_64-linux-gnu --offload=spirv64 \ -// RUN: --hip-path=%S/Inputs/hipspv \ +// RUN: --hip-path=%S/Inputs/hipspv \ // RUN: --hip-device-lib-path=%S/Inputs/hipspv-dev-lib %s \ // RUN: 2>&1 | FileCheck --check-prefixes=ALL,HIP-DEV-LIB-PATH %s diff --git a/clang/test/Driver/hipspv-link-static-library.hip b/clang/test/Driver/hipspv-link-static-library.hip index cf16236738c12..eb114ada49020 100644 --- a/clang/test/Driver/hipspv-link-static-library.hip +++ b/clang/test/Driver/hipspv-link-static-library.hip @@ -1,28 +1,57 @@ // Test HIPSPV static device library linking // REQUIRES: system-linux +// REQUIRES: x86-registered-target +// REQUIRES: spirv-registered-target // UNSUPPORTED: system-windows // Create a dummy archive to test SDL linking // RUN: rm -rf %t && mkdir %t -// RUN: touch %t/dummy.bc +// RUN: touch %t/dummy.bc // RUN: llvm-ar cr %t/libSDL.a %t/dummy.bc // Test that -l options are passed to llvm-link for --offload=spirv64 // RUN: %clang -### --target=x86_64-linux-gnu --offload=spirv64 \ // RUN: --hip-path=%S/Inputs/hipspv -nohipwrapperinc %s \ -// RUN: -L%t -lSDL \ -// RUN: 2>&1 | FileCheck -check-prefix=SDL-LINK %s +// RUN: --no-offload-new-driver -L%t -lSDL \ +// RUN: 2>&1 | FileCheck -check-prefixes=SDL %s -// Test that .a files are properly unbundled and passed to llvm-link +// Test that .a files are properly unbundled and passed to llvm-link // RUN: %clang -### --target=x86_64-linux-gnu --offload=spirv64 \ // RUN: --hip-path=%S/Inputs/hipspv -nohipwrapperinc %s \ -// RUN: %t/libSDL.a \ -// RUN: 2>&1 | FileCheck -check-prefix=SDL-ARCHIVE %s +// RUN: --no-offload-new-driver %t/libSDL.a \ +// RUN: 2>&1 | FileCheck -check-prefixes=SDL %s + +// RUN: %clang -cc1 %s -triple spirv64-unknown-chipstar -emit-llvm-bc -o %t/dev.bc +// RUN: llvm-offload-binary -o %t/dev.out \ +// RUN: --image=file=%t/dev.bc,kind=hip,triple=spirv64-unknown-chipstar,arch=generic +// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t/tu0.o \ +// RUN: -fembed-offload-object=%t/dev.out +// RUN: cp %t/tu0.o %t/tu1.o +// RUN: llvm-ar cr %t/libSDL2.a %t/tu1.o + +// RUN: %clang -### --target=x86_64-linux-gnu --offload-new-driver -fgpu-rdc \ +// RUN: -Xoffload-compiler-spirv64-unknown-chipstar \ +// RUN: --hip-path=%S/Inputs/hipspv -no-hip-rt %t/tu0.o %t/libSDL2.a \ +// RUN: 2>&1 | FileCheck -check-prefixes=SDL-NEW %s -DHIP_PATH=%S/Inputs/hipspv + +// RUN: clang-linker-wrapper --dry-run --host-triple=x86_64-unknown-linux-gnu \ +// RUN: --device-compiler=spirv64-unknown-chipstar=--hip-path=%S/Inputs/hipspv \ +// RUN: --linker-path=/usr/bin/ld -o a.out %t/tu0.o %t/libSDL2.a \ +// RUN: 2>&1 | FileCheck -check-prefixes=SDL-NEW-WRAPPER %s -DHIP_PATH=%S/Inputs/hipspv // Verify that the input files are added before the SDL files in llvm-link command // This tests the ordering fix to match HIPAMD behavior -// SDL-LINK: "{{.*}}clang-offload-bundler" "-unbundle" "-type=a" "-input={{.*}}libSDL.a" "-targets=hip-spirv64-unknown-unknown-unknown-generic" "-output=[[SDL_A:.*\.a]]" "-allow-missing-bundles" -// SDL-LINK: "{{.*}}llvm-link" "-o" "{{.*}}.bc" "{{.*}}.bc" "[[SDL_A]]" +// SDL: "{{.*}}clang-offload-bundler" "-unbundle" "-type=a" "-input={{.*}}libSDL.a" "-targets=hip-spirv64-unknown-unknown-unknown-generic" "-output=[[SDL_A:.*\.a]]" "-allow-missing-bundles" +// SDL: "{{.*}}llvm-link" "-o" "{{.*}}.bc" "{{.*}}.bc" "[[SDL_A]]" +// SDL-NEW: "{{.*}}clang-linker-wrapper" +// SDL-NEW-SAME: "--device-compiler=spirv64-unknown-chipstar=--hip-path=[[HIP_PATH]]" +// SDL-NEW-SAME: "{{.*}}/tu0.o" "{{.*}}/libSDL2.a" +// DELETE-SDL-NEW: "{{.*}}llvm-link" "-o" "{{.*}}.bc" "{{.*}}.o" "{{.*}}.o" + +// SDL-NEW-WRAPPER: clang{{.*}}" --no-default-config -o {{[^ ]*.img}} +// SDL-NEW-WRAPPER-SAME: {{[^ ]*.o}} {{[^ ]*.o}} +// SDL-NEW-WRAPPER-SAME: --hip-path=[[HIP_PATH]] -// SDL-ARCHIVE: "{{.*}}clang-offload-bundler" "-unbundle" "-type=a" "-input={{.*}}libSDL.a" "-targets=hip-spirv64-unknown-unknown-unknown-generic" "-output=[[SDL_A:.*\.a]]" "-allow-missing-bundles" -// SDL-ARCHIVE: "{{.*}}llvm-link" "-o" "{{.*}}.bc" "{{.*}}.bc" "[[SDL_A]]" +// SDL: "{{.*}}opt" +// SDL-SAME: "-load-pass-plugin" {{".*/hipspv/lib/libLLVMHipSpvPasses.so"}} +// SDL-SAME: "-passes=hip-post-link-passes" diff --git a/clang/test/Driver/hipspv-pass-plugin.hip b/clang/test/Driver/hipspv-pass-plugin.hip index fc3c64b057352..3a0979ad6df01 100644 --- a/clang/test/Driver/hipspv-pass-plugin.hip +++ b/clang/test/Driver/hipspv-pass-plugin.hip @@ -1,20 +1,38 @@ // UNSUPPORTED: system-windows // RUN: %clang -### -target x86_64-linux-gnu --offload=spirv64 \ -// RUN: --hip-path=%S/Inputs/hipspv -nogpuinc %s \ -// RUN: 2>&1 | FileCheck --check-prefixes=FROM-HIP-PATH %s +// RUN: --no-offload-new-driver --hip-path=%S/Inputs/hipspv -nogpuinc %s \ +// RUN: 2>&1 | FileCheck --check-prefixes=ALL,FROM-HIP-PATH %s // RUN: %clang -### -target x86_64-linux-gnu --offload=spirv64 \ -// RUN: -nogpuinc -nogpulib --hipspv-pass-plugin=%S/Inputs/pass-plugin.so %s \ -// RUN: 2>&1 | FileCheck --check-prefixes=FROM-OPTION %s +// RUN: --no-offload-new-driver -nogpuinc -nogpulib --hipspv-pass-plugin=%S/Inputs/pass-plugin.so %s \ +// RUN: 2>&1 | FileCheck --check-prefixes=ALL,FROM-OPTION %s // RUN: not %clang -### --target=x86_64-linux-gnu --offload=spirv64 \ -// RUN: -nogpuinc -nogpulib --hipspv-pass-plugin=foo.so %s \ -// RUN: 2>&1 | FileCheck --check-prefixes=FROM-OPTION-INVALID %s +// RUN: --no-offload-new-driver -nogpuinc -nogpulib --hipspv-pass-plugin=foo.so %s \ +// RUN: 2>&1 | FileCheck --check-prefixes=ALL,FROM-OPTION-INVALID %s // RUN: %clang -### -target x86_64-linux-gnu --offload=spirv64 \ -// RUN: -nogpuinc -nogpulib %s \ -// RUN: 2>&1 | FileCheck --check-prefixes=NO-PLUGIN %s +// RUN: --no-offload-new-driver -nogpuinc -nogpulib %s \ +// RUN: 2>&1 | FileCheck --check-prefixes=ALL,NO-PLUGIN %s + +// Run commands for the new offload driver: + +// RUN: touch %t.dummy.o +// RUN: %clang -### --no-default-config -o /dev/null --target=spirv64-unknown-chipstar \ +// RUN: %t.dummy.o --hip-path=%S/Inputs/hipspv \ +// RUN: 2>&1 | FileCheck %s --check-prefixes=ALL,FROM-HIP-PATH + +// RUN: %clang -### --no-default-config -o /dev/null --target=spirv64-unknown-chipstar \ +// RUN: %t.dummy.o --hipspv-pass-plugin=%S/Inputs/pass-plugin.so \ +// RUN: 2>&1 | FileCheck %s --check-prefixes=ALL,FROM-OPTION + +// RUN: not %clang -### --no-default-config -o /dev/null --target=spirv64-unknown-chipstar \ +// RUN: %t.dummy.o --hipspv-pass-plugin=foo.so \ +// RUN: 2>&1 | FileCheck %s --check-prefixes=ALL,FROM-OPTION-INVALID + +// RUN: %clang -### --no-default-config -o /dev/null --target=spirv64-unknown-chipstar \ +// RUN: %t.dummy.o 2>&1 | FileCheck %s --check-prefixes=ALL,NO-PLUGIN // FROM-HIP-PATH: {{".*opt"}} {{".*.bc"}} "-load-pass-plugin" // FROM-HIP-PATH-SAME: {{".*/Inputs/hipspv/lib/libLLVMHipSpvPasses.so"}} @@ -23,3 +41,4 @@ // FROM-OPTION-INVALID: error: no such file or directory: 'foo.so' // NO-PLUGIN-NOT: {{".*opt"}} {{".*.bc"}} "-load-pass-plugin" // NO-PLUGIN-NOT: {{".*/Inputs/hipspv/lib/libLLVMHipSpvPasses.so"}} +// ALL: {{".*llvm-spirv[^ ]*"}} diff --git a/clang/test/Driver/hipspv-toolchain-rdc-separate.hip b/clang/test/Driver/hipspv-toolchain-rdc-separate.hip new file mode 100644 index 0000000000000..6e597d69223a4 --- /dev/null +++ b/clang/test/Driver/hipspv-toolchain-rdc-separate.hip @@ -0,0 +1,66 @@ +// UNSUPPORTED: system-windows + +// RUN: %clang -### -x hip -target x86_64-linux-gnu \ +// RUN: --offload=spirv64-unknown-chipstar --offload-new-driver -fgpu-rdc -c \ +// RUN: --hip-path=%S/Inputs/hipspv -nohipwrapperinc \ +// RUN: %S/Inputs/hip_multiple_inputs/a.cu \ +// RUN: %S/Inputs/hip_multiple_inputs/b.hip \ +// RUN: 2>&1 | FileCheck \ +// RUN: -DHIP_PATH=%S/Inputs/hipspv %s + +// CHECK: [[CLANG:".*clang[^ ]*"]] "-cc1" "-triple" "spirv64-unknown-chipstar" +// CHECK-SAME: "-aux-triple" "[[HOST_TRIPLE:[^ ]*]]" +// CHECK-SAME: "-emit-llvm-bc" +// CHECK-SAME: "-fcuda-is-device" +// CHECK-SAME: "-fvisibility=hidden" "-fapply-global-visibility-to-externs" +// CHECK-SAME: "-mlink-builtin-bitcode" "[[HIP_PATH]]/lib/hip-device-lib/hipspv-spirv64-unknown-chipstar.bc" +// CHECK-SAME: "-fgpu-rdc" +// CHECK-SAME: "-o" "[[A_DEV_BC:.*bc]]" "-x" "hip" +// CHECK-SAME: "[[A_SRC:.*a.cu]]" + +// CHECK: "{{.*llvm-offload-binary[^ ]*}}" "-o" "[[A_BIN_PACKAGE:.*.out]]" +// CHECK-SAME: "--image=file=[[A_DEV_BC]],triple=spirv64-unknown-chipstar,arch=generic,kind=hip" + +// CHECK: [[CLANG]] "-cc1" "-triple" "[[HOST_TRIPLE]]" +// CHECK-SAME: "-aux-triple" "spirv64-unknown-chipstar" +// CHECK-SAME: "-emit-obj" +// CHECK-SAME: "-fgpu-rdc" +// CHECK-SAME: "-fembed-offload-object=[[A_BIN_PACKAGE]]" +// CHECK-SAME: "-o" "[[A_HOST_OBJ:.*o]]" "-x" "hip" "[[A_SRC]]" + +// CHECK: [[CLANG]] "-cc1" "-triple" "spirv64-unknown-chipstar" +// CHECK-SAME: "-aux-triple" "[[HOST_TRIPLE]]" +// CHECK-SAME: "-emit-llvm-bc" +// CHECK-SAME: "-fcuda-is-device" +// CHECK-SAME: "-fvisibility=hidden" "-fapply-global-visibility-to-externs" +// CHECK-SAME: "-mlink-builtin-bitcode" "[[HIP_PATH]]/lib/hip-device-lib/hipspv-spirv64-unknown-chipstar.bc" +// CHECK-SAME: "-fgpu-rdc" +// CHECK-SAME: "-o" "[[B_DEV_BC:.*bc]]" "-x" "hip" +// CHECK-SAME: "[[B_SRC:.*b.hip]]" + +// CHECK: "{{.*llvm-offload-binary[^ ]*}}" "-o" "[[B_BIN_PACKAGE:.*.out]]" +// CHECK-SAME: "--image=file=[[B_DEV_BC]],triple=spirv64-unknown-chipstar,arch=generic,kind=hip" + +// CHECK: [[CLANG]] "-cc1" "-triple" "[[HOST_TRIPLE]]" +// CHECK-SAME: "-aux-triple" "spirv64-unknown-chipstar" +// CHECK-SAME: "-emit-obj" +// CHECK-SAME: "-fgpu-rdc" +// CHECK-SAME: "-fembed-offload-object=[[B_BIN_PACKAGE]]" +// CHECK-SAME: "-o" "[[B_HOST_OBJ:.*o]]" "-x" "hip" +// CHECK-SAME: "[[B_SRC]]" + +// RUN: rm -rf %t && mkdir %t +// RUN: touch %t/a.o %t/b.o +// RUN: %clang -### -target x86_64-linux-gnu --offload-new-driver -fgpu-rdc \ +// RUN: -Xoffload-compiler-spirv64-unknown-chipstar \ +// RUN: --hip-path=%S/Inputs/hipspv \ +// RUN: -no-hip-rt %t/a.o %t/b.o \ +// RUN: 2>&1 | FileCheck -check-prefixes=LINK \ +// RUN: -DHIP_PATH=%S/Inputs/hipspv %s + +// LINK: "{{.*clang-linker-wrapper[^ ]*}}" +// LINK-SAME: "--host-triple=x86_64-unknown-linux-gnu" +// LINK-SAME: "--device-compiler=spirv64-unknown-chipstar=--hip-path=[[HIP_PATH]]" +// LINK-SAME: "-o" "a.out" +// LINK-SAME: "{{.*a[.]o}}" "{{.*b[.]o}}" +// LINK-NOT: -lamdhip64 diff --git a/clang/test/Driver/hipspv-toolchain-rdc.hip b/clang/test/Driver/hipspv-toolchain-rdc.hip index 05d9079f8dc18..5a3f59a6287b2 100644 --- a/clang/test/Driver/hipspv-toolchain-rdc.hip +++ b/clang/test/Driver/hipspv-toolchain-rdc.hip @@ -4,57 +4,113 @@ // RUN: --no-offload-new-driver -fgpu-rdc --hip-path=%S/Inputs/hipspv -nohipwrapperinc \ // RUN: %S/Inputs/hip_multiple_inputs/a.cu \ // RUN: %S/Inputs/hip_multiple_inputs/b.hip \ -// RUN: 2>&1 | FileCheck %s +// RUN: 2>&1 | FileCheck --check-prefix=OLD %s + +// RUN: %clang -### -x hip -target x86_64-linux-gnu \ +// RUN: --offload=spirv64-unknown-chipstar --offload-new-driver -fgpu-rdc \ +// RUN: --hip-path=%S/Inputs/hipspv -nohipwrapperinc -no-hip-rt \ +// RUN: %S/Inputs/hip_multiple_inputs/a.cu \ +// RUN: %S/Inputs/hip_multiple_inputs/b.hip \ +// RUN: 2>&1 | FileCheck --check-prefix=NEW \ +// RUN: -DOFFLOAD_TRIPLE=spirv64-unknown-chipstar -DHIP_PATH=%S/Inputs/hipspv %s // Emit objects for host side path -// CHECK: [[CLANG:".*clang.*"]] "-cc1" "-triple" "x86_64-unknown-linux-gnu" -// CHECK-SAME: "-aux-triple" "spirv64" -// CHECK-SAME: "-emit-obj" -// CHECK-SAME: "-fgpu-rdc" -// CHECK-SAME: {{.*}} "-o" [[A_OBJ_HOST:".*o"]] "-x" "hip" -// CHECK-SAME: {{.*}} [[A_SRC:".*a.cu"]] - -// CHECK: [[CLANG]] "-cc1" "-triple" "x86_64-unknown-linux-gnu" -// CHECK-SAME: "-aux-triple" "spirv64" -// CHECK-SAME: "-emit-obj" -// CHECK-SAME: "-fgpu-rdc" -// CHECK-SAME: {{.*}} "-o" [[B_OBJ_HOST:".*o"]] "-x" "hip" -// CHECK-SAME: {{.*}} [[B_SRC:".*b.hip"]] +// OLD: [[CLANG:".*clang.*"]] "-cc1" "-triple" "x86_64-unknown-linux-gnu" +// OLD-SAME: "-aux-triple" "spirv64" +// OLD-SAME: "-emit-obj" +// OLD-SAME: "-fgpu-rdc" +// OLD-SAME: {{.*}} "-o" [[A_OBJ_HOST:".*o"]] "-x" "hip" +// OLD-SAME: {{.*}} [[A_SRC:".*a.cu"]] + +// OLD: [[CLANG]] "-cc1" "-triple" "x86_64-unknown-linux-gnu" +// OLD-SAME: "-aux-triple" "spirv64" +// OLD-SAME: "-emit-obj" +// OLD-SAME: "-fgpu-rdc" +// OLD-SAME: {{.*}} "-o" [[B_OBJ_HOST:".*o"]] "-x" "hip" +// OLD-SAME: {{.*}} [[B_SRC:".*b.hip"]] // Emit code (LLVM BC) for device side path. -// CHECK: [[CLANG]] "-cc1" "-triple" "spirv64" -// CHECK-SAME: "-aux-triple" "x86_64-unknown-linux-gnu" -// CHECK-SAME: "-emit-llvm-bc" -// CHECK-SAME: "-fcuda-is-device" "-fcuda-allow-variadic-functions" -// CHECK-SAME: "-fvisibility=hidden" "-fapply-global-visibility-to-externs" -// CHECK-SAME: "-fgpu-rdc" -// CHECK-SAME: {{.*}} "-o" [[A_BC1:".*bc"]] "-x" "hip" -// CHECK-SAME: {{.*}} [[A_SRC]] - -// CHECK: [[CLANG]] "-cc1" "-triple" "spirv64" -// CHECK-SAME: "-aux-triple" "x86_64-unknown-linux-gnu" -// CHECK-SAME: "-emit-llvm-bc" -// CHECK-SAME: "-fcuda-is-device" "-fcuda-allow-variadic-functions" -// CHECK-SAME: "-fvisibility=hidden" "-fapply-global-visibility-to-externs" -// CHECK-SAME: "-fgpu-rdc" -// CHECK-SAME: {{.*}} "-o" [[B_BC1:".*bc"]] "-x" "hip" -// CHECK-SAME: {{.*}} [[B_SRC]] +// OLD: [[CLANG]] "-cc1" "-triple" "spirv64" +// OLD-SAME: "-aux-triple" "x86_64-unknown-linux-gnu" +// OLD-SAME: "-emit-llvm-bc" +// OLD-SAME: "-fcuda-is-device" +// OLD-SAME: "-fvisibility=hidden" "-fapply-global-visibility-to-externs" +// OLD-SAME: "-fgpu-rdc" +// OLD-SAME: {{.*}} "-o" [[A_BC1:".*bc"]] "-x" "hip" +// OLD-SAME: {{.*}} [[A_SRC]] + +// OLD: [[CLANG]] "-cc1" "-triple" "spirv64" +// OLD-SAME: "-aux-triple" "x86_64-unknown-linux-gnu" +// OLD-SAME: "-emit-llvm-bc" +// OLD-SAME: "-fcuda-is-device" +// OLD-SAME: "-fvisibility=hidden" "-fapply-global-visibility-to-externs" +// OLD-SAME: "-fgpu-rdc" +// OLD-SAME: {{.*}} "-o" [[B_BC1:".*bc"]] "-x" "hip" +// OLD-SAME: {{.*}} [[B_SRC]] // Link device code, lower it with HIPSPV passes and emit SPIR-V binary. -// CHECK: {{".*llvm-link.*"}} "-o" [[AB_LINK:".*bc"]] [[A_BC1]] [[B_BC1]] -// CHECK: {{".*opt.*"}} [[AB_LINK]] "-load-pass-plugin" -// CHECK-SAME: "{{.*}}/Inputs/hipspv/lib/libLLVMHipSpvPasses.so" -// CHECK-SAME: "-o" [[AB_LOWER:".*bc"]] -// CHECK: {{".*llvm-spirv"}} "--spirv-max-version=1.1" "--spirv-ext=+all" -// CHECK-SAME: [[AB_LOWER]] "-o" "[[AB_SPIRV:.*out]]" +// OLD: {{".*llvm-link.*"}} "-o" [[AB_LINK:".*bc"]] [[A_BC1]] [[B_BC1]] +// OLD: {{".*opt.*"}} [[AB_LINK]] "-load-pass-plugin" +// OLD-SAME: "{{.*}}/Inputs/hipspv/lib/libLLVMHipSpvPasses.so" +// OLD-SAME: "-o" [[AB_LOWER:".*bc"]] +// OLD: {{".*llvm-spirv"}} "--spirv-max-version=1.1" "--spirv-ext=+all" +// OLD-SAME: [[AB_LOWER]] "-o" "[[AB_SPIRV:.*out]]" // Construct fat binary object. -// CHECK: [[BUNDLER:".*clang-offload-bundler"]] "-type=o" "-bundle-align=4096" -// CHECK-SAME: "-targets={{.*}},hip-spirv64----generic" -// CHECK-SAME: "-input=/dev/null" "-input=[[AB_SPIRV]]" -// CHECK-SAME: "-output=[[AB_FATBIN:.*hipfb]]" -// CHECK: {{".*clang.*"}} "-o" [[OBJBUNDLE:".*o"]] "{{.*}}.mcin" +// OLD: [[BUNDLER:".*clang-offload-bundler"]] "-type=o" "-bundle-align=4096" +// OLD-SAME: "-targets={{.*}},hip-spirv64----generic" +// OLD-SAME: "-input=/dev/null" "-input=[[AB_SPIRV]]" +// OLD-SAME: "-output=[[AB_FATBIN:.*hipfb]]" +// OLD: {{".*clang.*"}} "-o" [[OBJBUNDLE:".*o"]] "{{.*}}.mcin" // Output the executable -// CHECK: {{".*ld.*"}} {{.*}}"-o" "a.out" {{.*}} [[A_OBJ_HOST]] [[B_OBJ_HOST]] -// CHECK-SAME: [[OBJBUNDLE]] +// OLD: {{".*ld.*"}} {{.*}}"-o" "a.out" {{.*}} [[A_OBJ_HOST]] [[B_OBJ_HOST]] +// OLD-SAME: [[OBJBUNDLE]] + +// NEW: [[CLANG:".*clang[^ ]*"]] "-cc1" "-triple" "[[OFFLOAD_TRIPLE]]" +// NEW-SAME: "-aux-triple" "[[HOST_TRIPLE:[^ ]*]]" +// NEW-SAME: "-emit-llvm-bc" +// NEW-SAME: "-fcuda-is-device" +// NEW-SAME: "-fvisibility=hidden" "-fapply-global-visibility-to-externs" +// NEW-SAME: "-mlink-builtin-bitcode" "[[HIP_PATH]]/lib/hip-device-lib/hipspv-spirv64-unknown-chipstar.bc" +// NEW-SAME: "-fgpu-rdc" +// NEW-SAME: "-o" "[[A_DEV_BC:.*bc]]" "-x" "hip" +// NEW-SAME: "[[A_SRC:.*a.cu]]" + +// NEW: "{{.*llvm-offload-binary[^ ]*}}" "-o" "[[A_BIN_PACKAGE:.*.out]]" +// NEW-SAME: "--image=file=[[A_DEV_BC]],triple=[[OFFLOAD_TRIPLE]],arch=generic,kind=hip" + +// NEW: [[CLANG]] "-cc1" "-triple" "[[HOST_TRIPLE]]" +// NEW-SAME: "-aux-triple" "[[OFFLOAD_TRIPLE]]" +// NEW-SAME: "-emit-obj" +// NEW-SAME: "-fgpu-rdc" +// NEW-SAME: "-fembed-offload-object=[[A_BIN_PACKAGE]]" +// NEW-SAME: "-o" "[[A_HOST_OBJ:.*o]]" "-x" "hip" "[[A_SRC]]" + +// NEW: [[CLANG]] "-cc1" "-triple" "[[OFFLOAD_TRIPLE]]" +// NEW-SAME: "-aux-triple" "[[HOST_TRIPLE]]" +// NEW-SAME: "-emit-llvm-bc" +// NEW-SAME: "-fcuda-is-device" +// NEW-SAME: "-fvisibility=hidden" "-fapply-global-visibility-to-externs" +// NEW-SAME: "-mlink-builtin-bitcode" "[[HIP_PATH]]/lib/hip-device-lib/hipspv-spirv64-unknown-chipstar.bc" +// NEW-SAME: "-fgpu-rdc" +// NEW-SAME: "-o" "[[B_DEV_BC:.*bc]]" "-x" "hip" +// NEW-SAME: "[[B_SRC:.*b.hip]]" + +// NEW: "{{.*llvm-offload-binary[^ ]*}}" "-o" "[[B_BIN_PACKAGE:.*.out]]" +// NEW-SAME: "--image=file=[[B_DEV_BC]],triple=[[OFFLOAD_TRIPLE]],arch=generic,kind=hip" + +// NEW: [[CLANG]] "-cc1" "-triple" "[[HOST_TRIPLE]]" +// NEW-SAME: "-aux-triple" "[[OFFLOAD_TRIPLE]]" +// NEW-SAME: "-emit-obj" +// NEW-SAME: "-fgpu-rdc" +// NEW-SAME: "-fembed-offload-object=[[B_BIN_PACKAGE]]" +// NEW-SAME: "-o" "[[B_HOST_OBJ:.*o]]" "-x" "hip" +// NEW-SAME: "[[B_SRC]]" + +// NEW: "{{.*clang-linker-wrapper[^ ]*}}" +// NEW-SAME: "--device-compiler=[[OFFLOAD_TRIPLE]]=--hip-path=[[HIP_PATH]]" +// NEW-SAME: "--host-triple=[[HOST_TRIPLE]]" +// NEW-SAME: "-o" "a.out" +// NEW-SAME: "[[A_HOST_OBJ]]" "[[B_HOST_OBJ]]" +// NEW-NOT: -lamdhip64 diff --git a/clang/test/Driver/hipspv-toolchain.hip b/clang/test/Driver/hipspv-toolchain.hip index 85c4333e877f2..ae8d65313abfb 100644 --- a/clang/test/Driver/hipspv-toolchain.hip +++ b/clang/test/Driver/hipspv-toolchain.hip @@ -1,38 +1,108 @@ +// REQUIRES: spirv-registered-target // UNSUPPORTED: system-windows, system-cygwin // RUN: %clang -### -target x86_64-linux-gnu --offload=spirv64 \ // RUN: --no-offload-new-driver --hip-path=%S/Inputs/hipspv -nohipwrapperinc %s \ -// RUN: 2>&1 | FileCheck %s +// RUN: 2>&1 | FileCheck --check-prefixes=CHECK,OLD \ +// RUN: -DTRIPLE=spirv64 %s -// CHECK: [[CLANG:".*clang.*"]] "-cc1" "-triple" "spirv64" +// RUN: %clang -### -target x86_64-linux-gnu \ +// RUN: --offload=spirv64-unknown-chipstar \ +// RUN: --offload-new-driver --hip-path=%S/Inputs/hipspv -nohipwrapperinc %s \ +// RUN: 2>&1 | FileCheck --check-prefixes=CHECK,NEW \ +// RUN: -DTRIPLE=spirv64-unknown-chipstar -DHIP_PATH=%S/Inputs/hipspv %s + +// CHECK: [[CLANG:".*clang.*"]] "-cc1" "-triple" "[[TRIPLE]]" // CHECK-SAME: "-aux-triple" "{{.*}}" "-emit-llvm-bc" // CHECK-SAME: "-fcuda-is-device" -// CHECK-SAME: "-fcuda-allow-variadic-functions" -// CHECK-SAME: "-mlink-builtin-bitcode" {{".*/hipspv/lib/hip-device-lib/hipspv-spirv64.bc"}} +// CHECK-SAME: "-mlink-builtin-bitcode" {{".*/hipspv/lib/hip-device-lib/hipspv-}}[[TRIPLE]].bc" // CHECK-SAME: "-isystem" {{".*/hipspv/include"}} // CHECK-SAME: "-fhip-new-launch-api" -// CHECK-SAME: "-o" [[DEV_BC:".*bc"]] +// CHECK-SAME: "-o" "[[OBJ_DEV:.*(o|bc)]]" // CHECK-SAME: "-x" "hip" -// CHECK: {{".*llvm-link"}} "-o" [[LINK_BC:".*bc"]] [[DEV_BC]] +// OLD: {{".*llvm-link"}} "-o" [[LINK_BC:".*bc"]] "[[OBJ_DEV]]" + +// OLD: {{".*opt"}} [[LINK_BC]] "-load-pass-plugin" +// OLD-SAME: {{".*/hipspv/lib/libLLVMHipSpvPasses.so"}} +// OLD-SAME: "-passes=hip-post-link-passes" "-o" [[LOWER_BC:".*bc"]] + +// OLD: {{".*llvm-spirv"}} "--spirv-max-version=1.1" "--spirv-ext=+all" +// OLD-SAME: [[LOWER_BC]] "-o" "[[SPIRV_OUT:.*out]]" -// CHECK: {{".*opt"}} [[LINK_BC]] "-load-pass-plugin" -// CHECK-SAME: {{".*/hipspv/lib/libLLVMHipSpvPasses.so"}} -// CHECK-SAME: "-passes=hip-post-link-passes" "-o" [[LOWER_BC:".*bc"]] +// OLD: {{".*clang-offload-bundler"}} "-type=o" "-bundle-align=4096" +// OLD-SAME: "-targets=host-x86_64-unknown-linux-gnu,hip-spirv64----generic" +// OLD-SAME: "-input={{.*}}" "-input=[[SPIRV_OUT]]" "-output=[[BUNDLE:.*hipfb]]" -// CHECK: {{".*llvm-spirv"}} "--spirv-max-version=1.1" "--spirv-ext=+all" -// CHECK-SAME: [[LOWER_BC]] "-o" "[[SPIRV_OUT:.*out]]" +// NEW: {{".*llvm-offload-binary"}} "-o" "[[PACKAGE:.*.out]]" +// NEW-SAME: "--image=file=[[OBJ_DEV]],triple=[[TRIPLE]],arch=generic,kind=hip" -// CHECK: {{".*clang-offload-bundler"}} "-type=o" "-bundle-align=4096" -// CHECK-SAME: "-targets=host-x86_64-unknown-linux-gnu,hip-spirv64----generic" -// CHECK-SAME: "-input={{.*}}" "-input=[[SPIRV_OUT]]" "-output=[[BUNDLE:.*hipfb]]" +// NEW: {{".*clang-linker-wrapper"}} "--device-compiler=[[TRIPLE]]=--hip-path=[[HIP_PATH]]" +// NEW-SAME: "--emit-fatbin-only" "-o" "[[BUNDLE:.*hipfb]]" -// CHECK: [[CLANG]] "-cc1" "-triple" {{".*"}} "-aux-triple" "spirv64" +// CHECK: [[CLANG]] "-cc1" "-triple" {{".*"}} "-aux-triple" "[[TRIPLE]]" // CHECK-SAME: "-emit-obj" // CHECK-SAME: "-fcuda-include-gpubinary" "[[BUNDLE]]" // CHECK-SAME: "-o" [[OBJ_HOST:".*o"]] "-x" "hip" -// CHECK: {{".*ld.*"}} {{.*}}[[OBJ_HOST]] +// OLD: {{".*ld.*"}} {{.*}}[[OBJ_HOST]] + +// NEW: {{".*clang-linker-wrapper"}} +// NEW-SAME: "--linker-path={{.*ld.*}}" "-o" "a.out" +// NEW-SAME: [[OBJ_HOST]] + +//------------------------------------------------------------------------------ +// Check the clang command, invoked by the linker wrapper, selects the HIPSPV +// toolchain for the new offload driver. + +// RUN: %clang -cc1 %s -triple spirv64-unknown-chipstar -emit-llvm-bc -o %t.dev.bc +// RUN: llvm-offload-binary -o %t.dev.out \ +// RUN: --image=file=%t.dev.bc,kind=hip,triple=spirv64-unknown-chipstar,arch=generic + +// RUN: clang-linker-wrapper --dry-run \ +// RUN: --device-compiler=spirv64-unknown-chipstar=--hip-path="%S/Inputs/hipspv" \ +// RUN: --host-triple=spirv64-unknown-chipstar \ +// RUN: --linker-path=clang-offload-bundler \ +// RUN: --emit-fatbin-only -o /dev/null %t.dev.out \ +// RUN: 2>&1 | FileCheck %s --check-prefix=WRAPPER -DHIP_PATH=%S/Inputs/hipspv + +// WRAPPER: clang{{.*}}" --no-default-config -o {{[^ ]*.img}} +// WRAPPER-SAME: --target=spirv64-unknown-chipstar +// WRAPPER-SAME: {{[^ ]*.o}} +// WRAPPER-SAME: --hip-path=[[HIP_PATH]] + +// RUN: touch %t.dummy.o +// RUN: %clang -### --no-default-config -o %t.dummy.img \ +// RUN: --target=spirv64-unknown-chipstar %t.dummy.o \ +// RUN: --hip-path="%S/Inputs/hipspv" \ +// RUN: 2>&1 | FileCheck %s --check-prefix=CHIPSTAR -DHIP_PATH=%S/Inputs/hipspv + +// CHIPSTAR: {{".*llvm-link"}} +// CHIPSTAR-SAME: "-o" [[LINK_BC:".*bc"]] "{{[^ ]*.o}}" + +// CHIPSTAR: {{".*opt"}} [[LINK_BC]] "-load-pass-plugin" +// CHIPSTAR-SAME: "[[HIP_PATH]]/lib/libLLVMHipSpvPasses.so" +// CHIPSTAR-SAME: "-passes=hip-post-link-passes" "-o" [[LOWER_BC:".*bc"]] + +// CHIPSTAR: {{".*llvm-spirv"}} "--spirv-max-version=1.2" +// CHIPSTAR-SAME: "--spirv-ext=-all,+SPV_INTEL_function_pointers,+SPV_INTEL_subgroups" +// CHIPSTAR-SAME: [[LOWER_BC]] "-o" "[[SPIRV_OUT:.*img]]" + +// RUN: %clang -### --no-default-config -o %t.dummy.img \ +// RUN: --target=spirv64v1.3-unknown-chipstar \ +// RUN: %t.dummy.o --hip-path="%S/Inputs/hipspv" \ +// RUN: 2>&1 | FileCheck %s --check-prefix=CHIPSTAR-SUBARCH -DHIP_PATH=%S/Inputs/hipspv + +// CHIPSTAR-SUBARCH: {{".*llvm-link"}} +// CHIPSTAR-SUBARCH-SAME: "-o" [[LINK_BC:".*bc"]] "{{[^ ]*.o}}" + +// CHIPSTAR-SUBARCH: {{".*opt"}} [[LINK_BC]] "-load-pass-plugin" +// CHIPSTAR-SUBARCH-SAME: "[[HIP_PATH]]/lib/libLLVMHipSpvPasses.so" +// CHIPSTAR-SUBARCH-SAME: "-passes=hip-post-link-passes" "-o" [[LOWER_BC:".*bc"]] + +// CHIPSTAR-SUBARCH: {{".*llvm-spirv"}} +// CHIPSTAR-SUBARCH-SAME: "--spirv-ext=-all,+SPV_INTEL_function_pointers,+SPV_INTEL_subgroups" +// CHIPSTAR-SUBARCH-SAME: [[LOWER_BC]] "-o" "[[SPIRV_OUT:.*img]]" //----------------------------------------------------------------------------- // Check llvm-spirv- is used if it is found in PATH. @@ -41,8 +111,13 @@ // RUN: && chmod +x %t/versioned/llvm-spirv-%llvm-version-major // RUN: env "PATH=%t/versioned" %clang -### -target x86_64-linux-gnu \ // RUN: --offload=spirv64 --hip-path=%S/Inputs/hipspv -nohipwrapperinc \ -// RUN: %s 2>&1 \ +// RUN: --no-offload-new-driver %s 2>&1 \ // RUN: | FileCheck -DVERSION=%llvm-version-major \ // RUN: --check-prefix=VERSIONED %s +// RUN: env "PATH=%t/versioned" %clang -### --no-default-config \ +// RUN: -o %t.dummy.img --target=spirv64-unknown-chipstar %t.dummy.o \ +// RUN: --hip-path="%S/Inputs/hipspv" -o /dev/null 2>&1 \ +// RUN: | FileCheck -DVERSION=%llvm-version-major --check-prefix=VERSIONED %s + // VERSIONED: {{.*}}llvm-spirv-[[VERSION]] diff --git a/clang/test/Driver/linker-wrapper-image.c b/clang/test/Driver/linker-wrapper-image.c index b9327121edcf9..2c0df8c6be925 100644 --- a/clang/test/Driver/linker-wrapper-image.c +++ b/clang/test/Driver/linker-wrapper-image.c @@ -25,7 +25,7 @@ // OPENMP-REL: @.omp_offloading.device_image = internal unnamed_addr constant [[[SIZE:[0-9]+]] x i8] c"\10\FF\10\AD{{.*}}", section ".llvm.offloading.relocatable", align 8 // OPENMP: @.omp_offloading.device_image = internal unnamed_addr constant [[[SIZE:[0-9]+]] x i8] c"\10\FF\10\AD{{.*}}", section ".llvm.offloading", align 8 -// OPENMP-NEXT: @.omp_offloading.device_images = internal unnamed_addr constant [1 x %__tgt_device_image] [%__tgt_device_image { ptr getelementptr ([[[BEGIN:[0-9]+]] x i8], ptr @.omp_offloading.device_image, i64 0, i64 144), ptr getelementptr ([[[END:[0-9]+]] x i8], ptr @.omp_offloading.device_image, i64 0, i64 144), ptr @__start_llvm_offload_entries, ptr @__stop_llvm_offload_entries }] +// OPENMP-NEXT: @.omp_offloading.device_images = internal unnamed_addr constant [1 x %__tgt_device_image] [%__tgt_device_image { ptr getelementptr ([[[IMG_OFF:[0-9]+]] x i8], ptr @.omp_offloading.device_image, i64 0, i64 [[IMG_OFF]]), ptr getelementptr ([[[IMG_OFF]] x i8], ptr @.omp_offloading.device_image, i64 0, i64 [[IMG_OFF]]), ptr @__start_llvm_offload_entries, ptr @__stop_llvm_offload_entries }] // OPENMP-NEXT: @.omp_offloading.descriptor = internal constant %__tgt_bin_desc { i32 1, ptr @.omp_offloading.device_images, ptr @__start_llvm_offload_entries, ptr @__stop_llvm_offload_entries } // OPENMP-NEXT: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 101, ptr @.omp_offloading.descriptor_reg, ptr null }] diff --git a/clang/test/Driver/openmp-target-fast-flag.c b/clang/test/Driver/openmp-target-fast-flag.c new file mode 100644 index 0000000000000..0390790b3f533 --- /dev/null +++ b/clang/test/Driver/openmp-target-fast-flag.c @@ -0,0 +1,35 @@ +// REQUIRES: x86-registered-target, amdgpu-registered-target + +// RUN: %clang -### -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -nogpulib %s -O0 2>&1 \ +// RUN: | FileCheck -check-prefixes=DefaultTFast,DefaultTState,DefaultNoNestParallel %s + +// RUN: %clang -### -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -nogpulib -O0 -fopenmp-target-fast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=TState,NestParallel %s + +// RUN: %clang -### -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -nogpulib -O3 %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=O3,DefaultTFast,DefaultTState,DefaultNoNestParallel %s + +// RUN: %clang -### -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -nogpulib -O3 -fno-openmp-target-fast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=O3,DefaultTState,DefaultNoNestParallel %s + +// RUN: %clang -### -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -nogpulib -Ofast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=OFast,TState,NestParallel %s + +// RUN: %clang -### -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -nogpulib -Ofast -fno-openmp-target-fast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=OFast,DefaultTState,DefaultNoNestParallel %s + +// RUN: %clang -### -fopenmp=libomp -fopenmp-targets=amdgcn-amd-amdhsa -Xopenmp-target=amdgcn-amd-amdhsa -march=gfx90a -nogpulib -O0 -fno-openmp-target-fast -fopenmp-target-fast %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=TState,NestParallel %s + +// O3: -O3 +// OFast: -Ofast + +// DefaultTFast-NOT: {{"-f(no-)?openmp-target-fast"}} + +// TState: "-fopenmp-assume-no-thread-state" +// TState-NOT: "-fno-openmp-assume-no-thread-state" +// DefaultTState-NOT: {{"-f(no-)?openmp-assume-no-thread-state"}} + +// NestParallel: "-fopenmp-assume-no-nested-parallelism" +// NestParallel-NOT: "-fno-openmp-assume-no-nested-parallelism" +// DefaultNoNestParallel-NOT: {{"-f(-no-)?openmp-assume-no-nested-parallelism"}} diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 8337d9f12fabd..3abafb6deafb2 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -245,6 +245,7 @@ // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) +// CHECK-NEXT: zvabd 0.7 'Zvabd' (Vector Absolute Difference) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) // CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts) diff --git a/clang/test/Driver/reflection-requires-cxx26.cpp b/clang/test/Driver/reflection-requires-cxx26.cpp new file mode 100644 index 0000000000000..276b3c478c9ac --- /dev/null +++ b/clang/test/Driver/reflection-requires-cxx26.cpp @@ -0,0 +1,3 @@ +// RUN: not %clangxx -fsyntax-only -std=c++23 -Xclang -freflection %s 2>&1 | FileCheck %s +// +// CHECK: error: option '-freflection' is only supported when compiling in C++26 mode diff --git a/clang/test/Driver/riscv-be.c b/clang/test/Driver/riscv-be.c new file mode 100644 index 0000000000000..d3f71a454debe --- /dev/null +++ b/clang/test/Driver/riscv-be.c @@ -0,0 +1,95 @@ +// UNSUPPORTED: system-windows +// REQUIRES: riscv-registered-target +// RUN: %clang -target riscv64be-unknown-elf -### %s 2>&1 \ +// RUN: | FileCheck %s +// RUN: %clang -target riscv64be-unknown-elf -Wno-riscv-be-experimental -### %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=NOWARN + +// CHECK: warning: big-endian RISC-V target support is experimental +// CHECK: "-triple" "riscv64be-unknown-unknown-elf" +// NOWARN-NOT: warning: big-endian RISC-V target support is experimental +// NOWARN: "-triple" "riscv64be-unknown-unknown-elf" + +/// Test dynamic linker for big-endian RISC-V Linux targets +// RUN: %clang -### %s --target=riscv64be-unknown-linux-gnu \ +// RUN: -Wno-riscv-be-experimental --rtlib=platform --unwindlib=platform -mabi=lp64d 2>&1 \ +// RUN: | FileCheck -check-prefix=RV64BE-LINUX-LP64D %s +// RV64BE-LINUX-LP64D: "-dynamic-linker" "/lib/ld-linux-riscv64be-lp64d.so.1" + +// RUN: %clang -### %s --target=riscv64be-unknown-linux-gnu \ +// RUN: -Wno-riscv-be-experimental --rtlib=platform --unwindlib=platform -mabi=lp64 2>&1 \ +// RUN: | FileCheck -check-prefix=RV64BE-LINUX-LP64 %s +// RV64BE-LINUX-LP64: "-dynamic-linker" "/lib/ld-linux-riscv64be-lp64.so.1" + +// RUN: %clang -### %s --target=riscv32be-unknown-linux-gnu \ +// RUN: -Wno-riscv-be-experimental --rtlib=platform --unwindlib=platform -mabi=ilp32d 2>&1 \ +// RUN: | FileCheck -check-prefix=RV32BE-LINUX-ILP32D %s +// RV32BE-LINUX-ILP32D: "-dynamic-linker" "/lib/ld-linux-riscv32be-ilp32d.so.1" + +// RUN: %clang -### %s --target=riscv32be-unknown-linux-gnu \ +// RUN: -Wno-riscv-be-experimental --rtlib=platform --unwindlib=platform -mabi=ilp32 2>&1 \ +// RUN: | FileCheck -check-prefix=RV32BE-LINUX-ILP32 %s +// RV32BE-LINUX-ILP32: "-dynamic-linker" "/lib/ld-linux-riscv32be-ilp32.so.1" + +/// Test big-endian RISC-V GCC multilib directory layout +// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \ +// RUN: --target=riscv64be-unknown-linux-gnu --rtlib=platform --unwindlib=platform -mabi=lp64 \ +// RUN: -Wno-riscv-be-experimental \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk_be \ +// RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk_be/sysroot 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV64BE-LINUX-MULTI-LP64 %s + +// C-RV64BE-LINUX-MULTI-LP64: "{{.*}}/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/../../../../riscv64be-unknown-linux-gnu/bin/ld" +// C-RV64BE-LINUX-MULTI-LP64: "--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot" +// C-RV64BE-LINUX-MULTI-LP64: "-m" "elf64briscv" "-X" +// C-RV64BE-LINUX-MULTI-LP64: "-dynamic-linker" "/lib/ld-linux-riscv64be-lp64.so.1" +// C-RV64BE-LINUX-MULTI-LP64: "{{.*}}/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib64/lp64/crtbegin.o" +// C-RV64BE-LINUX-MULTI-LP64: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib64/lp64" +// C-RV64BE-LINUX-MULTI-LP64: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib64/lp64" +// C-RV64BE-LINUX-MULTI-LP64: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib64/lp64" + +// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \ +// RUN: --target=riscv64be-unknown-linux-gnu --rtlib=platform --unwindlib=platform -march=rv64imafd \ +// RUN: -Wno-riscv-be-experimental \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk_be \ +// RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk_be/sysroot 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV64BE-LINUX-MULTI-LP64D %s + +// C-RV64BE-LINUX-MULTI-LP64D: "{{.*}}/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/../../../../riscv64be-unknown-linux-gnu/bin/ld" +// C-RV64BE-LINUX-MULTI-LP64D: "--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot" +// C-RV64BE-LINUX-MULTI-LP64D: "-m" "elf64briscv" +// C-RV64BE-LINUX-MULTI-LP64D: "-dynamic-linker" "/lib/ld-linux-riscv64be-lp64d.so.1" +// C-RV64BE-LINUX-MULTI-LP64D: "{{.*}}/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib64/lp64d/crtbegin.o" +// C-RV64BE-LINUX-MULTI-LP64D: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/lib/gcc/riscv64be-unknown-linux-gnu/7.2.0/lib64/lp64d" +// C-RV64BE-LINUX-MULTI-LP64D: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib64/lp64d" +// C-RV64BE-LINUX-MULTI-LP64D: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib64/lp64d" + +// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \ +// RUN: --target=riscv32be-unknown-linux-gnu --rtlib=platform --unwindlib=platform -mabi=ilp32 \ +// RUN: -Wno-riscv-be-experimental \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk_be \ +// RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk_be/sysroot 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32BE-LINUX-MULTI-ILP32 %s + +// C-RV32BE-LINUX-MULTI-ILP32: "--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot" +// C-RV32BE-LINUX-MULTI-ILP32: "-m" "elf32briscv" "-X" +// C-RV32BE-LINUX-MULTI-ILP32: "-dynamic-linker" "/lib/ld-linux-riscv32be-ilp32.so.1" +// C-RV32BE-LINUX-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib32/ilp32" +// C-RV32BE-LINUX-MULTI-ILP32: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib32/ilp32" + +// RUN: env "PATH=" %clang -### %s -fuse-ld= -no-pie \ +// RUN: --target=riscv32be-unknown-linux-gnu --rtlib=platform --unwindlib=platform -march=rv32imafd \ +// RUN: -Wno-riscv-be-experimental \ +// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk_be \ +// RUN: --sysroot=%S/Inputs/multilib_riscv_linux_sdk_be/sysroot 2>&1 \ +// RUN: | FileCheck -check-prefix=C-RV32BE-LINUX-MULTI-ILP32D %s + +// C-RV32BE-LINUX-MULTI-ILP32D: "--sysroot={{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot" +// C-RV32BE-LINUX-MULTI-ILP32D: "-m" "elf32briscv" +// C-RV32BE-LINUX-MULTI-ILP32D: "-dynamic-linker" "/lib/ld-linux-riscv32be-ilp32d.so.1" +// C-RV32BE-LINUX-MULTI-ILP32D: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot/lib32/ilp32d" +// C-RV32BE-LINUX-MULTI-ILP32D: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk_be/sysroot/usr/lib32/ilp32d" + +int foo(void) { + return 0; +} diff --git a/clang/test/Driver/sanitize-trap-loop.c b/clang/test/Driver/sanitize-trap-loop.c new file mode 100644 index 0000000000000..afb7b0d5906b9 --- /dev/null +++ b/clang/test/Driver/sanitize-trap-loop.c @@ -0,0 +1,3 @@ +// RUN: %clang --target=x86_64-linux-gnu -fsanitize=undefined -fsanitize-trap-loop %s -### 2>&1 | FileCheck %s +// CHECK: "-fsanitize-trap-loop" + diff --git a/clang/test/Driver/unsupported-target-vendor.c b/clang/test/Driver/unsupported-target-vendor.c new file mode 100644 index 0000000000000..9b5f423f27660 --- /dev/null +++ b/clang/test/Driver/unsupported-target-vendor.c @@ -0,0 +1,60 @@ +// Tests that clang does not crash with invalid vendors in target triples. +// +// RUN: %clang --target=arm-apple-firmware -### %s 2>&1 | FileCheck -check-prefix CHECK_APPLE %s +// RUN: %clang_cl --target=arm-apple-firmware -### %s 2>&1 | FileCheck -check-prefix CHECK_APPLE %s + +// CHECK_APPLE-NOT: LLVM ERROR: the firmware target os is only supported for the apple vendor + + +// RUN: not %clang --target=arm-none-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-none-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-unknown-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-unknown-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-pc-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-pc-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-scei-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-scei-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-sie-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-sie-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-fsl-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-fsl-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-ibm-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-ibm-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-img-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-img-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-mti-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-mti-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-nvidia-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-nvidia-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-csr-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-csr-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-amd-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-amd-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-mesa-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-mesa-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-suse-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-suse-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-oe-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-oe-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-intel-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-intel-firmware -### %s 2>&1 | FileCheck %s + +// RUN: not %clang --target=arm-meta-firmware -### %s 2>&1 | FileCheck %s +// RUN: not %clang_cl --target=arm-meta-firmware -### %s 2>&1 | FileCheck %s + +// CHECK: LLVM ERROR: the firmware target os is only supported for the apple vendor diff --git a/clang/test/Driver/x86-march.c b/clang/test/Driver/x86-march.c index 15f82547892c2..6a3ef5be67d8a 100644 --- a/clang/test/Driver/x86-march.c +++ b/clang/test/Driver/x86-march.c @@ -258,6 +258,10 @@ // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver5 2>&1 \ // RUN: | FileCheck %s -check-prefix=znver5 // znver5: "-target-cpu" "znver5" +// +// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver6 2>&1 \ +// RUN: | FileCheck %s -check-prefix=znver6 +// znver6: "-target-cpu" "znver6" // RUN: %clang -target x86_64 -c -### %s -march=x86-64 2>&1 | FileCheck %s --check-prefix=x86-64 // x86-64: "-target-cpu" "x86-64" diff --git a/clang/test/ExtractAPI/objc_property.m b/clang/test/ExtractAPI/objc_property.m index 68869295f8c04..9e6b40f77370c 100644 --- a/clang/test/ExtractAPI/objc_property.m +++ b/clang/test/ExtractAPI/objc_property.m @@ -1,6 +1,7 @@ // RUN: rm -rf %t // RUN: %clang_cc1 -extract-api --pretty-sgf --emit-sgf-symbol-labels-for-testing \ -// RUN: -triple arm64-apple-macosx -x objective-c-header %s -o - -verify | FileCheck %s +// RUN: -triple arm64-apple-macosx -x objective-c-header %s -o %t/output.symbols.json -verify +// RUN: FileCheck %s --input-file %t/output.symbols.json @protocol Protocol @property(class) int myProtocolTypeProp; @@ -14,6 +15,30 @@ @interface Interface // CHECK-DAG: "!testRelLabel": "memberOf $ c:objc(cs)Interface(cpy)myInterfaceTypeProp $ c:objc(cs)Interface" @property int myInterfaceInstanceProp; // CHECK-DAG: "!testRelLabel": "memberOf $ c:objc(cs)Interface(py)myInterfaceInstanceProp $ c:objc(cs)Interface" + +// RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix NULLABLE +@property(nullable, strong) id myNullableProp; +// CHECK-DAG: "!testRelLabel": "memberOf $ c:objc(cs)Interface(py)myNullableProp $ c:objc(cs)Interface" +// NULLABLE: "!testLabel": "c:objc(cs)Interface(py)myNullableProp" +// NULLABLE: "declarationFragments": [ +// NULLABLE: "kind": "keyword", +// NULLABLE-NEXT: "spelling": "@property" +// NULLABLE: "kind": "keyword", +// NULLABLE-NEXT: "spelling": "strong" +// NULLABLE: "kind": "keyword", +// NULLABLE-NEXT: "spelling": "nullable" + +// RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix NULLRESETTABLE +@property(null_resettable, strong) id myNullResettableProp; +// CHECK-DAG: "!testRelLabel": "memberOf $ c:objc(cs)Interface(py)myNullResettableProp $ c:objc(cs)Interface" +// NULLRESETTABLE: "!testLabel": "c:objc(cs)Interface(py)myNullResettableProp" +// NULLABLE: "declarationFragments": [ +// NULLABLE: "kind": "keyword", +// NULLABLE-NEXT: "spelling": "@property" +// NULLABLE: "kind": "keyword", +// NULLABLE-NEXT: "spelling": "strong" +// NULLABLE: "kind": "keyword", +// NULLABLE-NEXT: "spelling": "null_resettable" @end @interface Interface (Category) diff --git a/clang/test/Frontend/x86-target-cpu.c b/clang/test/Frontend/x86-target-cpu.c index f2885a040c370..7dc7f5474687e 100644 --- a/clang/test/Frontend/x86-target-cpu.c +++ b/clang/test/Frontend/x86-target-cpu.c @@ -39,5 +39,6 @@ // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver3 -verify %s // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s // RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver5 -verify %s +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver6 -verify %s // // expected-no-diagnostics diff --git a/clang/test/Headers/__clang_hip_cmath.hip b/clang/test/Headers/__clang_hip_cmath.hip index 2e0b776c4bfe5..5bcd5857b3919 100644 --- a/clang/test/Headers/__clang_hip_cmath.hip +++ b/clang/test/Headers/__clang_hip_cmath.hip @@ -33,7 +33,7 @@ // // FINITEONLY-LABEL: @test_fma_f16( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef half @llvm.fma.f16(half nofpclass(nan inf) [[X:%.*]], half nofpclass(nan inf) [[Y:%.*]], half nofpclass(nan inf) [[Z:%.*]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) half @llvm.fma.f16(half nofpclass(nan inf) [[X:%.*]], half nofpclass(nan inf) [[Y:%.*]], half nofpclass(nan inf) [[Z:%.*]]) // FINITEONLY-NEXT: ret half [[TMP0]] // extern "C" __device__ _Float16 test_fma_f16(_Float16 x, _Float16 y, @@ -62,7 +62,7 @@ extern "C" __device__ _Float16 test_pow_f16(_Float16 x, int y) { // // FINITEONLY-LABEL: @test_fabs_f32( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.fabs.f32(float nofpclass(nan inf) [[X:%.*]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.fabs.f32(float nofpclass(nan inf) [[X:%.*]]) // FINITEONLY-NEXT: ret float [[TMP0]] // extern "C" __device__ float test_fabs_f32(float x) { @@ -159,12 +159,12 @@ namespace user_namespace { // // FINITEONLY-LABEL: @test_sqrt_f32( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.sqrt.f32(float nofpclass(nan inf) [[X:%.*]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.sqrt.f32(float nofpclass(nan inf) [[X:%.*]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // NO-CORRECT-DIV-SQRT-LABEL: @test_sqrt_f32( // NO-CORRECT-DIV-SQRT-NEXT: entry: -// NO-CORRECT-DIV-SQRT-NEXT: [[TMP0:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[X:%.*]]), !fpmath [[META4:![0-9]+]] +// NO-CORRECT-DIV-SQRT-NEXT: [[TMP0:%.*]] = tail call contract noundef float @llvm.sqrt.f32(float [[X:%.*]]), !fpmath [[META8:![0-9]+]] // NO-CORRECT-DIV-SQRT-NEXT: ret float [[TMP0]] // extern "C" __device__ float test_sqrt_f32(float x) { @@ -178,7 +178,7 @@ extern "C" __device__ float test_sqrt_f32(float x) { // // FINITEONLY-LABEL: @test_sqrt_f64( // FINITEONLY-NEXT: entry: -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.sqrt.f64(double nofpclass(nan inf) [[X:%.*]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.sqrt.f64(double nofpclass(nan inf) [[X:%.*]]) // FINITEONLY-NEXT: ret double [[TMP0]] // extern "C" __device__ double test_sqrt_f64(double x) { diff --git a/clang/test/Headers/__clang_hip_libdevice_declares.cpp b/clang/test/Headers/__clang_hip_libdevice_declares.cpp index 2b96f9499eb9a..87453797ab127 100644 --- a/clang/test/Headers/__clang_hip_libdevice_declares.cpp +++ b/clang/test/Headers/__clang_hip_libdevice_declares.cpp @@ -71,9 +71,7 @@ void attribute_check_hack(void) { // CHECK-LABEL: define internal float @_ZL18test_ockl_acos_f32f // CHECK-SAME: (float [[SRC:%.*]]) #[[ATTR2:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[SRC_ADDR:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[SRC_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SRC_ADDR]] to ptr // CHECK-NEXT: store float [[SRC]], ptr [[SRC_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[SRC_ADDR_ASCAST]], align 4 @@ -87,7 +85,6 @@ TEST_FUNC_ATTRS float test_ockl_acos_f32(float src) { // CHECK-LABEL: define internal float @_ZL15test_ockl_fdot2Dv2_DF16_S_fbi // CHECK-SAME: (<2 x half> [[A:%.*]], <2 x half> [[B:%.*]], float [[C:%.*]], i1 zeroext [[S:%.*]], i32 [[S_INT:%.*]]) #[[ATTR2]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x half>, align 4, addrspace(5) // CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x half>, align 4, addrspace(5) // CHECK-NEXT: [[C_ADDR:%.*]] = alloca float, align 4, addrspace(5) @@ -95,7 +92,6 @@ TEST_FUNC_ATTRS float test_ockl_acos_f32(float src) { // CHECK-NEXT: [[S_INT_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[X:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[Y:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr // CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr // CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr @@ -106,23 +102,23 @@ TEST_FUNC_ATTRS float test_ockl_acos_f32(float src) { // CHECK-NEXT: store <2 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 4 // CHECK-NEXT: store <2 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 4 // CHECK-NEXT: store float [[C]], ptr [[C_ADDR_ASCAST]], align 4 -// CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[S]] to i8 -// CHECK-NEXT: store i8 [[FROMBOOL]], ptr [[S_ADDR_ASCAST]], align 1 +// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[S]] to i8 +// CHECK-NEXT: store i8 [[STOREDV]], ptr [[S_ADDR_ASCAST]], align 1 // CHECK-NEXT: store i32 [[S_INT]], ptr [[S_INT_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr [[A_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[B_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[C_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[S_ADDR_ASCAST]], align 1 -// CHECK-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK-NEXT: [[CALL:%.*]] = call float @__ockl_fdot2(<2 x half> [[TMP0]], <2 x half> [[TMP1]], float [[TMP2]], i1 zeroext [[TOBOOL]]) #[[ATTR4]] +// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK-NEXT: [[CALL:%.*]] = call float @__ockl_fdot2(<2 x half> [[TMP0]], <2 x half> [[TMP1]], float [[TMP2]], i1 zeroext [[LOADEDV]]) #[[ATTR4]] // CHECK-NEXT: store float [[CALL]], ptr [[X_ASCAST]], align 4 // CHECK-NEXT: [[TMP4:%.*]] = load <2 x half>, ptr [[A_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP5:%.*]] = load <2 x half>, ptr [[B_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[C_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[S_INT_ADDR_ASCAST]], align 4 -// CHECK-NEXT: [[TOBOOL1:%.*]] = icmp ne i32 [[TMP7]], 0 -// CHECK-NEXT: [[CALL2:%.*]] = call float @__ockl_fdot2(<2 x half> [[TMP4]], <2 x half> [[TMP5]], float [[TMP6]], i1 zeroext [[TOBOOL1]]) #[[ATTR4]] -// CHECK-NEXT: store float [[CALL2]], ptr [[Y_ASCAST]], align 4 +// CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0 +// CHECK-NEXT: [[CALL1:%.*]] = call float @__ockl_fdot2(<2 x half> [[TMP4]], <2 x half> [[TMP5]], float [[TMP6]], i1 zeroext [[TOBOOL]]) #[[ATTR4]] +// CHECK-NEXT: store float [[CALL1]], ptr [[Y_ASCAST]], align 4 // CHECK-NEXT: [[TMP8:%.*]] = load float, ptr [[X_ASCAST]], align 4 // CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[Y_ASCAST]], align 4 // CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP8]], [[TMP9]] diff --git a/clang/test/Headers/__clang_hip_math.hip b/clang/test/Headers/__clang_hip_math.hip index e91f5723a8460..0270fb4cf74dd 100644 --- a/clang/test/Headers/__clang_hip_math.hip +++ b/clang/test/Headers/__clang_hip_math.hip @@ -1000,7 +1000,7 @@ extern "C" __device__ double test_cbrt(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_ceilf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.ceil.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.ceil.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_ceilf( @@ -1034,7 +1034,7 @@ extern "C" __device__ float test_ceilf(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_ceil( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.ceil.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.ceil.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_ceil( @@ -1068,7 +1068,7 @@ extern "C" __device__ double test_ceil(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_copysignf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.copysign.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.copysign.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_copysignf( @@ -1102,7 +1102,7 @@ extern "C" __device__ float test_copysignf(float x, float y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_copysign( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], double noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.copysign.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.copysign.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_copysign( @@ -1612,7 +1612,7 @@ extern "C" __device__ double test_erfinv(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_exp10f( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.exp10.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.exp10.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_exp10f( @@ -1680,7 +1680,7 @@ extern "C" __device__ double test_exp10(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_exp2f( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.exp2.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.exp2.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_exp2f( @@ -1748,7 +1748,7 @@ extern "C" __device__ double test_exp2(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_expf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.exp.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.exp.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_expf( @@ -1884,7 +1884,7 @@ extern "C" __device__ double test_expm1(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_fabsf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.fabs.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.fabs.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_fabsf( @@ -1918,7 +1918,7 @@ extern "C" __device__ float test_fabsf(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_fabs( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.fabs.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.fabs.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_fabs( @@ -2054,7 +2054,7 @@ extern "C" __device__ float test_fdividef(float x, float y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_floorf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.floor.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.floor.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_floorf( @@ -2088,7 +2088,7 @@ extern "C" __device__ float test_floorf(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_floor( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.floor.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.floor.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_floor( @@ -2122,7 +2122,7 @@ extern "C" __device__ double test_floor(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_fmaf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]], float noundef nofpclass(nan inf) [[Z:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.fma.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]], float nofpclass(nan inf) [[Z]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.fma.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]], float nofpclass(nan inf) [[Z]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_fmaf( @@ -2156,7 +2156,7 @@ extern "C" __device__ float test_fmaf(float x, float y, float z) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_fma( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], double noundef nofpclass(nan inf) [[Y:%.*]], double noundef nofpclass(nan inf) [[Z:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.fma.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]], double nofpclass(nan inf) [[Z]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.fma.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]], double nofpclass(nan inf) [[Z]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_fma( @@ -2190,7 +2190,7 @@ extern "C" __device__ double test_fma(double x, double y, double z) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_fma_rn( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], double noundef nofpclass(nan inf) [[Y:%.*]], double noundef nofpclass(nan inf) [[Z:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.fma.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]], double nofpclass(nan inf) [[Z]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.fma.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]], double nofpclass(nan inf) [[Z]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_fma_rn( @@ -2224,7 +2224,7 @@ extern "C" __device__ double test_fma_rn(double x, double y, double z) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_fmaxf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.maxnum.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.maxnum.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_fmaxf( @@ -2258,7 +2258,7 @@ extern "C" __device__ float test_fmaxf(float x, float y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_fmax( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], double noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.maxnum.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.maxnum.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_fmax( @@ -2292,7 +2292,7 @@ extern "C" __device__ double test_fmax(double x, double y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_fminf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.minnum.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.minnum.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_fminf( @@ -2326,7 +2326,7 @@ extern "C" __device__ float test_fminf(float x, float y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_fmin( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], double noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.minnum.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.minnum.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_fmin( @@ -3384,7 +3384,7 @@ extern "C" __device__ double test_jn(int x, double y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_ldexpf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], i32 noundef [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.ldexp.f32.i32(float nofpclass(nan inf) [[X]], i32 [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.ldexp.f32.i32(float nofpclass(nan inf) [[X]], i32 [[Y]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_ldexpf( @@ -3418,7 +3418,7 @@ extern "C" __device__ float test_ldexpf(float x, int y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_ldexp( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], i32 noundef [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.ldexp.f64.i32(double nofpclass(nan inf) [[X]], i32 [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.ldexp.f64.i32(double nofpclass(nan inf) [[X]], i32 [[Y]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_ldexp( @@ -3676,7 +3676,7 @@ extern "C" __device__ long long int test_llround(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_log10f( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.log10.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.log10.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_log10f( @@ -3812,7 +3812,7 @@ extern "C" __device__ double test_log1p(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_log2f( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.log2.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.log2.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_log2f( @@ -4018,7 +4018,7 @@ extern "C" __device__ double test_logb(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_logf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.log.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.log.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_logf( @@ -5148,7 +5148,7 @@ extern "C" __device__ double test_nan_fill() { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_nearbyintf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.nearbyint.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.nearbyint.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_nearbyintf( @@ -5182,7 +5182,7 @@ extern "C" __device__ float test_nearbyintf(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_nearbyint( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.nearbyint.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.nearbyint.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_nearbyint( @@ -5587,7 +5587,7 @@ extern "C" __device__ double test_normcdfinv(double x) { // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP20:![0-9]+]] // FINITEONLY: [[_ZL5NORMFIPKF_EXIT_LOOPEXIT]]: -// FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract float @llvm.sqrt.f32(float [[ADD_I]]) +// FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract nofpclass(nan inf) float @llvm.sqrt.f32(float [[ADD_I]]) // FINITEONLY-NEXT: br label %[[_ZL5NORMFIPKF_EXIT]] // FINITEONLY: [[_ZL5NORMFIPKF_EXIT]]: // FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL5NORMFIPKF_EXIT_LOOPEXIT]] ] @@ -5706,7 +5706,7 @@ extern "C" __device__ float test_normf(int x, const float *y) { // FINITEONLY-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq i32 [[DEC_I]], 0 // FINITEONLY-NEXT: br i1 [[TOBOOL_NOT_I]], label %[[_ZL4NORMIPKD_EXIT_LOOPEXIT:.*]], label %[[WHILE_BODY_I]], !llvm.loop [[LOOP21:![0-9]+]] // FINITEONLY: [[_ZL4NORMIPKD_EXIT_LOOPEXIT]]: -// FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract double @llvm.sqrt.f64(double [[ADD_I]]) +// FINITEONLY-NEXT: [[TMP1:%.*]] = tail call nnan ninf contract nofpclass(nan inf) double @llvm.sqrt.f64(double [[ADD_I]]) // FINITEONLY-NEXT: br label %[[_ZL4NORMIPKD_EXIT]] // FINITEONLY: [[_ZL4NORMIPKD_EXIT]]: // FINITEONLY-NEXT: [[__R_0_I_LCSSA:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[TMP1]], %[[_ZL4NORMIPKD_EXIT_LOOPEXIT]] ] @@ -6254,7 +6254,7 @@ extern "C" __device__ double test_rhypot(double x, double y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_rintf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.rint.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.rint.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_rintf( @@ -6288,7 +6288,7 @@ extern "C" __device__ float test_rintf(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_rint( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.rint.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.rint.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_rint( @@ -6676,7 +6676,7 @@ extern "C" __device__ double test_rnorm4d(double x, double y, double z, double w // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_roundf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.round.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.round.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_roundf( @@ -6710,7 +6710,7 @@ extern "C" __device__ float test_roundf(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_round( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.round.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.round.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_round( @@ -6816,7 +6816,7 @@ extern "C" __device__ double test_rsqrt(double x) { // FINITEONLY-NEXT: [[ENTRY:.*:]] // FINITEONLY-NEXT: [[SPEC_STORE_SELECT_I:%.*]] = tail call i64 @llvm.smax.i64(i64 [[Y]], i64 -2147483648) // FINITEONLY-NEXT: [[CONV_I:%.*]] = trunc i64 [[SPEC_STORE_SELECT_I]] to i32 -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.ldexp.f32.i32(float nofpclass(nan inf) [[X]], i32 [[CONV_I]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.ldexp.f32.i32(float nofpclass(nan inf) [[X]], i32 [[CONV_I]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_scalblnf( @@ -6860,7 +6860,7 @@ extern "C" __device__ float test_scalblnf(float x, long int y) { // FINITEONLY-NEXT: [[ENTRY:.*:]] // FINITEONLY-NEXT: [[SPEC_STORE_SELECT_I:%.*]] = tail call i64 @llvm.smax.i64(i64 [[Y]], i64 -2147483648) // FINITEONLY-NEXT: [[CONV_I:%.*]] = trunc i64 [[SPEC_STORE_SELECT_I]] to i32 -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.ldexp.f64.i32(double nofpclass(nan inf) [[X]], i32 [[CONV_I]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.ldexp.f64.i32(double nofpclass(nan inf) [[X]], i32 [[CONV_I]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_scalbln( @@ -6900,7 +6900,7 @@ extern "C" __device__ double test_scalbln(double x, long int y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_scalbnf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], i32 noundef [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.ldexp.f32.i32(float nofpclass(nan inf) [[X]], i32 [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.ldexp.f32.i32(float nofpclass(nan inf) [[X]], i32 [[Y]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_scalbnf( @@ -6934,7 +6934,7 @@ extern "C" __device__ float test_scalbnf(float x, int y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_scalbn( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], i32 noundef [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.ldexp.f64.i32(double nofpclass(nan inf) [[X]], i32 [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.ldexp.f64.i32(double nofpclass(nan inf) [[X]], i32 [[Y]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_scalbn( @@ -7447,7 +7447,7 @@ extern "C" __device__ double test_sinpi(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_sqrtf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.sqrt.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.sqrt.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_sqrtf( @@ -7481,7 +7481,7 @@ extern "C" __device__ float test_sqrtf(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_sqrt( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.sqrt.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.sqrt.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_sqrt( @@ -7719,7 +7719,7 @@ extern "C" __device__ double test_tgamma(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_truncf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.trunc.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.trunc.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_truncf( @@ -7753,7 +7753,7 @@ extern "C" __device__ float test_truncf(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_trunc( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.trunc.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.trunc.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_trunc( @@ -8307,7 +8307,7 @@ extern "C" __device__ float test___cosf(float x) { // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[X]], 0x400A934F00000000 -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.amdgcn.exp2.f32(float [[MUL_I]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test___exp10f( @@ -8346,7 +8346,7 @@ extern "C" __device__ float test___exp10f(float x) { // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] // FINITEONLY-NEXT: [[MUL_I:%.*]] = fmul nnan ninf contract float [[X]], 0x3FF7154760000000 -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.amdgcn.exp2.f32(float [[MUL_I]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.amdgcn.exp2.f32(float [[MUL_I]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test___expf( @@ -8451,7 +8451,7 @@ extern "C" __device__ float test___fdividef(float x, float y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test__fmaf_rn( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]], float noundef nofpclass(nan inf) [[Z:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.fma.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]], float nofpclass(nan inf) [[Z]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.fma.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]], float nofpclass(nan inf) [[Z]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test__fmaf_rn( @@ -8553,7 +8553,7 @@ extern "C" __device__ float test___frcp_rn(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test___frsqrt_rn( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.amdgcn.rsq.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.amdgcn.rsq.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test___frsqrt_rn( @@ -8655,7 +8655,7 @@ extern "C" __device__ float test___fsub_rn(float x, float y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test___log10f( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.log10.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.log10.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test___log10f( @@ -8689,7 +8689,7 @@ extern "C" __device__ float test___log10f(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test___log2f( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.amdgcn.log.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.amdgcn.log.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test___log2f( @@ -8723,7 +8723,7 @@ extern "C" __device__ float test___log2f(float x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test___logf( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.log.f32(float nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.log.f32(float nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test___logf( @@ -9108,7 +9108,7 @@ extern "C" __device__ double test___drcp_rn(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test___dsqrt_rn( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.sqrt.f64(double nofpclass(nan inf) [[X]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.sqrt.f64(double nofpclass(nan inf) [[X]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test___dsqrt_rn( @@ -9142,7 +9142,7 @@ extern "C" __device__ double test___dsqrt_rn(double x) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test__fma_rn( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], double noundef nofpclass(nan inf) [[Y:%.*]], double noundef nofpclass(nan inf) [[Z:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.fma.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]], double nofpclass(nan inf) [[Z]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.fma.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]], double nofpclass(nan inf) [[Z]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test__fma_rn( @@ -9176,7 +9176,7 @@ extern "C" __device__ double test__fma_rn(double x, double y, double z) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_float_min( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.minnum.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.minnum.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_float_min( @@ -9210,7 +9210,7 @@ extern "C" __device__ float test_float_min(float x, float y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) float @test_float_max( // FINITEONLY-SAME: float noundef nofpclass(nan inf) [[X:%.*]], float noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef float @llvm.maxnum.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) float @llvm.maxnum.f32(float nofpclass(nan inf) [[X]], float nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret float [[TMP0]] // // APPROX-LABEL: define dso_local noundef float @test_float_max( @@ -9244,7 +9244,7 @@ extern "C" __device__ float test_float_max(float x, float y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_double_min( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], double noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.minnum.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.minnum.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_double_min( @@ -9278,7 +9278,7 @@ extern "C" __device__ double test_double_min(double x, double y) { // FINITEONLY-LABEL: define dso_local noundef nofpclass(nan inf) double @test_double_max( // FINITEONLY-SAME: double noundef nofpclass(nan inf) [[X:%.*]], double noundef nofpclass(nan inf) [[Y:%.*]]) local_unnamed_addr #[[ATTR3]] { // FINITEONLY-NEXT: [[ENTRY:.*:]] -// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef double @llvm.maxnum.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) +// FINITEONLY-NEXT: [[TMP0:%.*]] = tail call nnan ninf contract noundef nofpclass(nan inf) double @llvm.maxnum.f64(double nofpclass(nan inf) [[X]], double nofpclass(nan inf) [[Y]]) // FINITEONLY-NEXT: ret double [[TMP0]] // // APPROX-LABEL: define dso_local noundef double @test_double_max( diff --git a/clang/test/Headers/amdgcn_openmp_device_math.c b/clang/test/Headers/amdgcn_openmp_device_math.c index 243d241628b2a..a1ea836cb87ad 100644 --- a/clang/test/Headers/amdgcn_openmp_device_math.c +++ b/clang/test/Headers/amdgcn_openmp_device_math.c @@ -14,15 +14,11 @@ // CHECK-C-LABEL: @test_math_f64( // CHECK-C-NEXT: entry: -// CHECK-C-NEXT: [[RETVAL_I13:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I14:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I9:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[__Y_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[__Z_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I9:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I10:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I4:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I5:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I7:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I4:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[__X_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[X_ADDR:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[Y_ADDR:%.*]] = alloca double, align 8, addrspace(5) @@ -42,37 +38,33 @@ // CHECK-C-NEXT: store double [[Y:%.*]], ptr [[Y_ADDR_ASCAST]], align 8 // CHECK-C-NEXT: store double [[Z:%.*]], ptr [[Z_ADDR_ASCAST]], align 8 // CHECK-C-NEXT: [[TMP0:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 -// CHECK-C-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-C-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-C-NEXT: store double [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: [[TMP1:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: [[CALL_I:%.*]] = call double @__ocml_sin_f64(double noundef [[TMP1]]) #[[ATTR3:[0-9]+]] // CHECK-C-NEXT: store double [[CALL_I]], ptr [[L1_ASCAST]], align 8 // CHECK-C-NEXT: [[TMP2:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 -// CHECK-C-NEXT: [[RETVAL_ASCAST_I6:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I4]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I7:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I5]] to ptr -// CHECK-C-NEXT: store double [[TMP2]], ptr [[__X_ADDR_ASCAST_I7]], align 8 -// CHECK-C-NEXT: [[TMP3:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I7]], align 8 -// CHECK-C-NEXT: [[CALL_I8:%.*]] = call double @__ocml_cos_f64(double noundef [[TMP3]]) #[[ATTR3]] -// CHECK-C-NEXT: store double [[CALL_I8]], ptr [[L2_ASCAST]], align 8 +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I5:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I4]] to ptr +// CHECK-C-NEXT: store double [[TMP2]], ptr [[__X_ADDR_ASCAST_I5]], align 8 +// CHECK-C-NEXT: [[TMP3:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I5]], align 8 +// CHECK-C-NEXT: [[CALL_I6:%.*]] = call double @__ocml_cos_f64(double noundef [[TMP3]]) #[[ATTR3]] +// CHECK-C-NEXT: store double [[CALL_I6]], ptr [[L2_ASCAST]], align 8 // CHECK-C-NEXT: [[TMP4:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 -// CHECK-C-NEXT: [[RETVAL_ASCAST_I11:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I9]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I12:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I10]] to ptr -// CHECK-C-NEXT: store double [[TMP4]], ptr [[__X_ADDR_ASCAST_I12]], align 8 -// CHECK-C-NEXT: [[TMP5:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I12]], align 8 +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I8:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I7]] to ptr +// CHECK-C-NEXT: store double [[TMP4]], ptr [[__X_ADDR_ASCAST_I8]], align 8 +// CHECK-C-NEXT: [[TMP5:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I8]], align 8 // CHECK-C-NEXT: [[TMP6:%.*]] = call double @llvm.fabs.f64(double [[TMP5]]) // CHECK-C-NEXT: store double [[TMP6]], ptr [[L3_ASCAST]], align 8 // CHECK-C-NEXT: [[TMP7:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 // CHECK-C-NEXT: [[TMP8:%.*]] = load double, ptr [[Y_ADDR_ASCAST]], align 8 // CHECK-C-NEXT: [[TMP9:%.*]] = load double, ptr [[Z_ADDR_ASCAST]], align 8 -// CHECK-C-NEXT: [[RETVAL_ASCAST_I15:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I13]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I16:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I14]] to ptr +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I10:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I9]] to ptr // CHECK-C-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-C-NEXT: [[__Z_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I]] to ptr -// CHECK-C-NEXT: store double [[TMP7]], ptr [[__X_ADDR_ASCAST_I16]], align 8 +// CHECK-C-NEXT: store double [[TMP7]], ptr [[__X_ADDR_ASCAST_I10]], align 8 // CHECK-C-NEXT: store double [[TMP8]], ptr [[__Y_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: store double [[TMP9]], ptr [[__Z_ADDR_ASCAST_I]], align 8 -// CHECK-C-NEXT: [[TMP10:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I16]], align 8 +// CHECK-C-NEXT: [[TMP10:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I10]], align 8 // CHECK-C-NEXT: [[TMP11:%.*]] = load double, ptr [[__Y_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: [[TMP12:%.*]] = load double, ptr [[__Z_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: [[TMP13:%.*]] = call double @llvm.fma.f64(double [[TMP10]], double [[TMP11]], double [[TMP12]]) @@ -81,15 +73,11 @@ // // CHECK-CPP-LABEL: @_Z13test_math_f64ddd( // CHECK-CPP-NEXT: entry: -// CHECK-CPP-NEXT: [[RETVAL_I13:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I14:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I9:%.*]] = alloca double, align 8, addrspace(5) // CHECK-CPP-NEXT: [[__Y_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) // CHECK-CPP-NEXT: [[__Z_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I9:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I10:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I4:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I5:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I7:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I4:%.*]] = alloca double, align 8, addrspace(5) // CHECK-CPP-NEXT: [[__X_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) // CHECK-CPP-NEXT: [[X_ADDR:%.*]] = alloca double, align 8, addrspace(5) // CHECK-CPP-NEXT: [[Y_ADDR:%.*]] = alloca double, align 8, addrspace(5) @@ -109,37 +97,33 @@ // CHECK-CPP-NEXT: store double [[Y:%.*]], ptr [[Y_ADDR_ASCAST]], align 8 // CHECK-CPP-NEXT: store double [[Z:%.*]], ptr [[Z_ADDR_ASCAST]], align 8 // CHECK-CPP-NEXT: [[TMP0:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-CPP-NEXT: store double [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 8 // CHECK-CPP-NEXT: [[TMP1:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I]], align 8 // CHECK-CPP-NEXT: [[CALL_I:%.*]] = call noundef double @__ocml_sin_f64(double noundef [[TMP1]]) #[[ATTR3:[0-9]+]] // CHECK-CPP-NEXT: store double [[CALL_I]], ptr [[L1_ASCAST]], align 8 // CHECK-CPP-NEXT: [[TMP2:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I6:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I4]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I7:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I5]] to ptr -// CHECK-CPP-NEXT: store double [[TMP2]], ptr [[__X_ADDR_ASCAST_I7]], align 8 -// CHECK-CPP-NEXT: [[TMP3:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I7]], align 8 -// CHECK-CPP-NEXT: [[CALL_I8:%.*]] = call noundef double @__ocml_cos_f64(double noundef [[TMP3]]) #[[ATTR3]] -// CHECK-CPP-NEXT: store double [[CALL_I8]], ptr [[L2_ASCAST]], align 8 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I5:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I4]] to ptr +// CHECK-CPP-NEXT: store double [[TMP2]], ptr [[__X_ADDR_ASCAST_I5]], align 8 +// CHECK-CPP-NEXT: [[TMP3:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I5]], align 8 +// CHECK-CPP-NEXT: [[CALL_I6:%.*]] = call noundef double @__ocml_cos_f64(double noundef [[TMP3]]) #[[ATTR3]] +// CHECK-CPP-NEXT: store double [[CALL_I6]], ptr [[L2_ASCAST]], align 8 // CHECK-CPP-NEXT: [[TMP4:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I11:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I9]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I12:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I10]] to ptr -// CHECK-CPP-NEXT: store double [[TMP4]], ptr [[__X_ADDR_ASCAST_I12]], align 8 -// CHECK-CPP-NEXT: [[TMP5:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I12]], align 8 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I8:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I7]] to ptr +// CHECK-CPP-NEXT: store double [[TMP4]], ptr [[__X_ADDR_ASCAST_I8]], align 8 +// CHECK-CPP-NEXT: [[TMP5:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I8]], align 8 // CHECK-CPP-NEXT: [[TMP6:%.*]] = call noundef double @llvm.fabs.f64(double [[TMP5]]) // CHECK-CPP-NEXT: store double [[TMP6]], ptr [[L3_ASCAST]], align 8 // CHECK-CPP-NEXT: [[TMP7:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 // CHECK-CPP-NEXT: [[TMP8:%.*]] = load double, ptr [[Y_ADDR_ASCAST]], align 8 // CHECK-CPP-NEXT: [[TMP9:%.*]] = load double, ptr [[Z_ADDR_ASCAST]], align 8 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I15:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I13]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I16:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I14]] to ptr +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I10:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I9]] to ptr // CHECK-CPP-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-CPP-NEXT: [[__Z_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I]] to ptr -// CHECK-CPP-NEXT: store double [[TMP7]], ptr [[__X_ADDR_ASCAST_I16]], align 8 +// CHECK-CPP-NEXT: store double [[TMP7]], ptr [[__X_ADDR_ASCAST_I10]], align 8 // CHECK-CPP-NEXT: store double [[TMP8]], ptr [[__Y_ADDR_ASCAST_I]], align 8 // CHECK-CPP-NEXT: store double [[TMP9]], ptr [[__Z_ADDR_ASCAST_I]], align 8 -// CHECK-CPP-NEXT: [[TMP10:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I16]], align 8 +// CHECK-CPP-NEXT: [[TMP10:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I10]], align 8 // CHECK-CPP-NEXT: [[TMP11:%.*]] = load double, ptr [[__Y_ADDR_ASCAST_I]], align 8 // CHECK-CPP-NEXT: [[TMP12:%.*]] = load double, ptr [[__Z_ADDR_ASCAST_I]], align 8 // CHECK-CPP-NEXT: [[TMP13:%.*]] = call noundef double @llvm.fma.f64(double [[TMP10]], double [[TMP11]], double [[TMP12]]) @@ -155,15 +139,11 @@ void test_math_f64(double x, double y, double z) { // CHECK-C-LABEL: @test_math_f32( // CHECK-C-NEXT: entry: -// CHECK-C-NEXT: [[RETVAL_I22:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I23:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I18:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[__Y_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[__Z_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I18:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I19:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I13:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I14:%.*]] = alloca double, align 8, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I16:%.*]] = alloca double, align 8, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I13:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[__X_ADDR_I:%.*]] = alloca double, align 8, addrspace(5) // CHECK-C-NEXT: [[X_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-C-NEXT: [[Y_ADDR:%.*]] = alloca float, align 4, addrspace(5) @@ -184,7 +164,6 @@ void test_math_f64(double x, double y, double z) { // CHECK-C-NEXT: store float [[Z:%.*]], ptr [[Z_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: [[CONV:%.*]] = fpext float [[TMP0]] to double -// CHECK-C-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-C-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-C-NEXT: store double [[CONV]], ptr [[__X_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: [[TMP1:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I]], align 8 @@ -193,19 +172,17 @@ void test_math_f64(double x, double y, double z) { // CHECK-C-NEXT: store float [[CONV1]], ptr [[L1_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP2:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: [[CONV2:%.*]] = fpext float [[TMP2]] to double -// CHECK-C-NEXT: [[RETVAL_ASCAST_I15:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I13]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I16:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I14]] to ptr -// CHECK-C-NEXT: store double [[CONV2]], ptr [[__X_ADDR_ASCAST_I16]], align 8 -// CHECK-C-NEXT: [[TMP3:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I16]], align 8 -// CHECK-C-NEXT: [[CALL_I17:%.*]] = call double @__ocml_cos_f64(double noundef [[TMP3]]) #[[ATTR3]] -// CHECK-C-NEXT: [[CONV4:%.*]] = fptrunc double [[CALL_I17]] to float +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I14:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I13]] to ptr +// CHECK-C-NEXT: store double [[CONV2]], ptr [[__X_ADDR_ASCAST_I14]], align 8 +// CHECK-C-NEXT: [[TMP3:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I14]], align 8 +// CHECK-C-NEXT: [[CALL_I15:%.*]] = call double @__ocml_cos_f64(double noundef [[TMP3]]) #[[ATTR3]] +// CHECK-C-NEXT: [[CONV4:%.*]] = fptrunc double [[CALL_I15]] to float // CHECK-C-NEXT: store float [[CONV4]], ptr [[L2_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP4:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: [[CONV5:%.*]] = fpext float [[TMP4]] to double -// CHECK-C-NEXT: [[RETVAL_ASCAST_I20:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I18]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I21:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I19]] to ptr -// CHECK-C-NEXT: store double [[CONV5]], ptr [[__X_ADDR_ASCAST_I21]], align 8 -// CHECK-C-NEXT: [[TMP5:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I21]], align 8 +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I17:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I16]] to ptr +// CHECK-C-NEXT: store double [[CONV5]], ptr [[__X_ADDR_ASCAST_I17]], align 8 +// CHECK-C-NEXT: [[TMP5:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I17]], align 8 // CHECK-C-NEXT: [[TMP6:%.*]] = call double @llvm.fabs.f64(double [[TMP5]]) // CHECK-C-NEXT: [[CONV7:%.*]] = fptrunc double [[TMP6]] to float // CHECK-C-NEXT: store float [[CONV7]], ptr [[L3_ASCAST]], align 4 @@ -215,14 +192,13 @@ void test_math_f64(double x, double y, double z) { // CHECK-C-NEXT: [[CONV9:%.*]] = fpext float [[TMP8]] to double // CHECK-C-NEXT: [[TMP9:%.*]] = load float, ptr [[Z_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: [[CONV10:%.*]] = fpext float [[TMP9]] to double -// CHECK-C-NEXT: [[RETVAL_ASCAST_I24:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I22]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I25:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I23]] to ptr +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I19:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I18]] to ptr // CHECK-C-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-C-NEXT: [[__Z_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I]] to ptr -// CHECK-C-NEXT: store double [[CONV8]], ptr [[__X_ADDR_ASCAST_I25]], align 8 +// CHECK-C-NEXT: store double [[CONV8]], ptr [[__X_ADDR_ASCAST_I19]], align 8 // CHECK-C-NEXT: store double [[CONV9]], ptr [[__Y_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: store double [[CONV10]], ptr [[__Z_ADDR_ASCAST_I]], align 8 -// CHECK-C-NEXT: [[TMP10:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I25]], align 8 +// CHECK-C-NEXT: [[TMP10:%.*]] = load double, ptr [[__X_ADDR_ASCAST_I19]], align 8 // CHECK-C-NEXT: [[TMP11:%.*]] = load double, ptr [[__Y_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: [[TMP12:%.*]] = load double, ptr [[__Z_ADDR_ASCAST_I]], align 8 // CHECK-C-NEXT: [[TMP13:%.*]] = call double @llvm.fma.f64(double [[TMP10]], double [[TMP11]], double [[TMP12]]) @@ -232,25 +208,17 @@ void test_math_f64(double x, double y, double z) { // // CHECK-CPP-LABEL: @_Z13test_math_f32fff( // CHECK-CPP-NEXT: entry: -// CHECK-CPP-NEXT: [[RETVAL_I32:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I33:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__Y_ADDR_I34:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__Z_ADDR_I35:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I28:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I29:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I24:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I25:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I19:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[__X_ADDR_I20:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I14:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I15:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__Y_ADDR_I21:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__Z_ADDR_I22:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I18:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I16:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I13:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I10:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[__Z_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I9:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I10:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I4:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I5:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I7:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I4:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[X_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[Y_ADDR:%.*]] = alloca float, align 4, addrspace(5) @@ -270,61 +238,53 @@ void test_math_f64(double x, double y, double z) { // CHECK-CPP-NEXT: store float [[Y:%.*]], ptr [[Y_ADDR_ASCAST]], align 4 // CHECK-CPP-NEXT: store float [[Z:%.*]], ptr [[Z_ADDR_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-CPP-NEXT: store float [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-CPP-NEXT: [[TMP1:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I21:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I19]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I22:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I20]] to ptr -// CHECK-CPP-NEXT: store float [[TMP1]], ptr [[__X_ADDR_ASCAST_I22]], align 4 -// CHECK-CPP-NEXT: [[TMP2:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I22]], align 4 -// CHECK-CPP-NEXT: [[CALL_I23:%.*]] = call noundef float @__ocml_sin_f32(float noundef [[TMP2]]) #[[ATTR3]] -// CHECK-CPP-NEXT: store float [[CALL_I23]], ptr [[L1_ASCAST]], align 4 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I14:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I13]] to ptr +// CHECK-CPP-NEXT: store float [[TMP1]], ptr [[__X_ADDR_ASCAST_I14]], align 4 +// CHECK-CPP-NEXT: [[TMP2:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I14]], align 4 +// CHECK-CPP-NEXT: [[CALL_I15:%.*]] = call noundef float @__ocml_sin_f32(float noundef [[TMP2]]) #[[ATTR3]] +// CHECK-CPP-NEXT: store float [[CALL_I15]], ptr [[L1_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP3:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I6:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I4]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I7:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I5]] to ptr -// CHECK-CPP-NEXT: store float [[TMP3]], ptr [[__X_ADDR_ASCAST_I7]], align 4 -// CHECK-CPP-NEXT: [[TMP4:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I7]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I26:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I24]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I27:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I25]] to ptr -// CHECK-CPP-NEXT: store float [[TMP4]], ptr [[__X_ADDR_ASCAST_I27]], align 4 -// CHECK-CPP-NEXT: [[TMP5:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I27]], align 4 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I5:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I4]] to ptr +// CHECK-CPP-NEXT: store float [[TMP3]], ptr [[__X_ADDR_ASCAST_I5]], align 4 +// CHECK-CPP-NEXT: [[TMP4:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I5]], align 4 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I17:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I16]] to ptr +// CHECK-CPP-NEXT: store float [[TMP4]], ptr [[__X_ADDR_ASCAST_I17]], align 4 +// CHECK-CPP-NEXT: [[TMP5:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I17]], align 4 // CHECK-CPP-NEXT: [[CALL_I:%.*]] = call noundef float @__ocml_cos_f32(float noundef [[TMP5]]) #[[ATTR3]] // CHECK-CPP-NEXT: store float [[CALL_I]], ptr [[L2_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP6:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I11:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I9]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I12:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I10]] to ptr -// CHECK-CPP-NEXT: store float [[TMP6]], ptr [[__X_ADDR_ASCAST_I12]], align 4 -// CHECK-CPP-NEXT: [[TMP7:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I12]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I30:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I28]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I31:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I29]] to ptr -// CHECK-CPP-NEXT: store float [[TMP7]], ptr [[__X_ADDR_ASCAST_I31]], align 4 -// CHECK-CPP-NEXT: [[TMP8:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I31]], align 4 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I8:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I7]] to ptr +// CHECK-CPP-NEXT: store float [[TMP6]], ptr [[__X_ADDR_ASCAST_I8]], align 4 +// CHECK-CPP-NEXT: [[TMP7:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I8]], align 4 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I19:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I18]] to ptr +// CHECK-CPP-NEXT: store float [[TMP7]], ptr [[__X_ADDR_ASCAST_I19]], align 4 +// CHECK-CPP-NEXT: [[TMP8:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I19]], align 4 // CHECK-CPP-NEXT: [[TMP9:%.*]] = call noundef float @llvm.fabs.f32(float [[TMP8]]) // CHECK-CPP-NEXT: store float [[TMP9]], ptr [[L3_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP10:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP11:%.*]] = load float, ptr [[Y_ADDR_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP12:%.*]] = load float, ptr [[Z_ADDR_ASCAST]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I16:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I14]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I17:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I15]] to ptr +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I11:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I10]] to ptr // CHECK-CPP-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-CPP-NEXT: [[__Z_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I]] to ptr -// CHECK-CPP-NEXT: store float [[TMP10]], ptr [[__X_ADDR_ASCAST_I17]], align 4 +// CHECK-CPP-NEXT: store float [[TMP10]], ptr [[__X_ADDR_ASCAST_I11]], align 4 // CHECK-CPP-NEXT: store float [[TMP11]], ptr [[__Y_ADDR_ASCAST_I]], align 4 // CHECK-CPP-NEXT: store float [[TMP12]], ptr [[__Z_ADDR_ASCAST_I]], align 4 -// CHECK-CPP-NEXT: [[TMP13:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I17]], align 4 +// CHECK-CPP-NEXT: [[TMP13:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I11]], align 4 // CHECK-CPP-NEXT: [[TMP14:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I]], align 4 // CHECK-CPP-NEXT: [[TMP15:%.*]] = load float, ptr [[__Z_ADDR_ASCAST_I]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I36:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I32]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I37:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I33]] to ptr -// CHECK-CPP-NEXT: [[__Y_ADDR_ASCAST_I38:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I34]] to ptr -// CHECK-CPP-NEXT: [[__Z_ADDR_ASCAST_I39:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I35]] to ptr -// CHECK-CPP-NEXT: store float [[TMP13]], ptr [[__X_ADDR_ASCAST_I37]], align 4 -// CHECK-CPP-NEXT: store float [[TMP14]], ptr [[__Y_ADDR_ASCAST_I38]], align 4 -// CHECK-CPP-NEXT: store float [[TMP15]], ptr [[__Z_ADDR_ASCAST_I39]], align 4 -// CHECK-CPP-NEXT: [[TMP16:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I37]], align 4 -// CHECK-CPP-NEXT: [[TMP17:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I38]], align 4 -// CHECK-CPP-NEXT: [[TMP18:%.*]] = load float, ptr [[__Z_ADDR_ASCAST_I39]], align 4 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I23:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I20]] to ptr +// CHECK-CPP-NEXT: [[__Y_ADDR_ASCAST_I24:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I21]] to ptr +// CHECK-CPP-NEXT: [[__Z_ADDR_ASCAST_I25:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I22]] to ptr +// CHECK-CPP-NEXT: store float [[TMP13]], ptr [[__X_ADDR_ASCAST_I23]], align 4 +// CHECK-CPP-NEXT: store float [[TMP14]], ptr [[__Y_ADDR_ASCAST_I24]], align 4 +// CHECK-CPP-NEXT: store float [[TMP15]], ptr [[__Z_ADDR_ASCAST_I25]], align 4 +// CHECK-CPP-NEXT: [[TMP16:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I23]], align 4 +// CHECK-CPP-NEXT: [[TMP17:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I24]], align 4 +// CHECK-CPP-NEXT: [[TMP18:%.*]] = load float, ptr [[__Z_ADDR_ASCAST_I25]], align 4 // CHECK-CPP-NEXT: [[TMP19:%.*]] = call noundef float @llvm.fma.f32(float [[TMP16]], float [[TMP17]], float [[TMP18]]) // CHECK-CPP-NEXT: store float [[TMP19]], ptr [[L4_ASCAST]], align 4 // CHECK-CPP-NEXT: ret void @@ -338,15 +298,11 @@ void test_math_f32(float x, float y, float z) { // CHECK-C-LABEL: @test_math_f32_suffix( // CHECK-C-NEXT: entry: -// CHECK-C-NEXT: [[RETVAL_I13:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I14:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I9:%.*]] = alloca float, align 4, addrspace(5) // CHECK-C-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-C-NEXT: [[__Z_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I9:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I10:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I4:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-C-NEXT: [[__X_ADDR_I5:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I7:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-C-NEXT: [[__X_ADDR_I4:%.*]] = alloca float, align 4, addrspace(5) // CHECK-C-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-C-NEXT: [[X_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-C-NEXT: [[Y_ADDR:%.*]] = alloca float, align 4, addrspace(5) @@ -366,37 +322,33 @@ void test_math_f32(float x, float y, float z) { // CHECK-C-NEXT: store float [[Y:%.*]], ptr [[Y_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: store float [[Z:%.*]], ptr [[Z_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-C-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-C-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-C-NEXT: store float [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-C-NEXT: [[TMP1:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-C-NEXT: [[CALL_I:%.*]] = call float @__ocml_sin_f32(float noundef [[TMP1]]) #[[ATTR3]] // CHECK-C-NEXT: store float [[CALL_I]], ptr [[L1_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP2:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-C-NEXT: [[RETVAL_ASCAST_I6:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I4]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I7:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I5]] to ptr -// CHECK-C-NEXT: store float [[TMP2]], ptr [[__X_ADDR_ASCAST_I7]], align 4 -// CHECK-C-NEXT: [[TMP3:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I7]], align 4 -// CHECK-C-NEXT: [[CALL_I8:%.*]] = call float @__ocml_cos_f32(float noundef [[TMP3]]) #[[ATTR3]] -// CHECK-C-NEXT: store float [[CALL_I8]], ptr [[L2_ASCAST]], align 4 +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I5:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I4]] to ptr +// CHECK-C-NEXT: store float [[TMP2]], ptr [[__X_ADDR_ASCAST_I5]], align 4 +// CHECK-C-NEXT: [[TMP3:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I5]], align 4 +// CHECK-C-NEXT: [[CALL_I6:%.*]] = call float @__ocml_cos_f32(float noundef [[TMP3]]) #[[ATTR3]] +// CHECK-C-NEXT: store float [[CALL_I6]], ptr [[L2_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP4:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-C-NEXT: [[RETVAL_ASCAST_I11:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I9]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I12:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I10]] to ptr -// CHECK-C-NEXT: store float [[TMP4]], ptr [[__X_ADDR_ASCAST_I12]], align 4 -// CHECK-C-NEXT: [[TMP5:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I12]], align 4 +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I8:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I7]] to ptr +// CHECK-C-NEXT: store float [[TMP4]], ptr [[__X_ADDR_ASCAST_I8]], align 4 +// CHECK-C-NEXT: [[TMP5:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I8]], align 4 // CHECK-C-NEXT: [[TMP6:%.*]] = call float @llvm.fabs.f32(float [[TMP5]]) // CHECK-C-NEXT: store float [[TMP6]], ptr [[L3_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP7:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP8:%.*]] = load float, ptr [[Y_ADDR_ASCAST]], align 4 // CHECK-C-NEXT: [[TMP9:%.*]] = load float, ptr [[Z_ADDR_ASCAST]], align 4 -// CHECK-C-NEXT: [[RETVAL_ASCAST_I15:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I13]] to ptr -// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I16:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I14]] to ptr +// CHECK-C-NEXT: [[__X_ADDR_ASCAST_I10:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I9]] to ptr // CHECK-C-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-C-NEXT: [[__Z_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I]] to ptr -// CHECK-C-NEXT: store float [[TMP7]], ptr [[__X_ADDR_ASCAST_I16]], align 4 +// CHECK-C-NEXT: store float [[TMP7]], ptr [[__X_ADDR_ASCAST_I10]], align 4 // CHECK-C-NEXT: store float [[TMP8]], ptr [[__Y_ADDR_ASCAST_I]], align 4 // CHECK-C-NEXT: store float [[TMP9]], ptr [[__Z_ADDR_ASCAST_I]], align 4 -// CHECK-C-NEXT: [[TMP10:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I16]], align 4 +// CHECK-C-NEXT: [[TMP10:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I10]], align 4 // CHECK-C-NEXT: [[TMP11:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I]], align 4 // CHECK-C-NEXT: [[TMP12:%.*]] = load float, ptr [[__Z_ADDR_ASCAST_I]], align 4 // CHECK-C-NEXT: [[TMP13:%.*]] = call float @llvm.fma.f32(float [[TMP10]], float [[TMP11]], float [[TMP12]]) @@ -405,15 +357,11 @@ void test_math_f32(float x, float y, float z) { // // CHECK-CPP-LABEL: @_Z20test_math_f32_suffixfff( // CHECK-CPP-NEXT: entry: -// CHECK-CPP-NEXT: [[RETVAL_I13:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I14:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I9:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[__Z_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I9:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I10:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I4:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[__X_ADDR_I5:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-CPP-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I7:%.*]] = alloca float, align 4, addrspace(5) +// CHECK-CPP-NEXT: [[__X_ADDR_I4:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[X_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-CPP-NEXT: [[Y_ADDR:%.*]] = alloca float, align 4, addrspace(5) @@ -433,37 +381,33 @@ void test_math_f32(float x, float y, float z) { // CHECK-CPP-NEXT: store float [[Y:%.*]], ptr [[Y_ADDR_ASCAST]], align 4 // CHECK-CPP-NEXT: store float [[Z:%.*]], ptr [[Z_ADDR_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP0:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-CPP-NEXT: store float [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-CPP-NEXT: [[TMP1:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-CPP-NEXT: [[CALL_I:%.*]] = call noundef float @__ocml_sin_f32(float noundef [[TMP1]]) #[[ATTR3]] // CHECK-CPP-NEXT: store float [[CALL_I]], ptr [[L1_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP2:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I6:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I4]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I7:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I5]] to ptr -// CHECK-CPP-NEXT: store float [[TMP2]], ptr [[__X_ADDR_ASCAST_I7]], align 4 -// CHECK-CPP-NEXT: [[TMP3:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I7]], align 4 -// CHECK-CPP-NEXT: [[CALL_I8:%.*]] = call noundef float @__ocml_cos_f32(float noundef [[TMP3]]) #[[ATTR3]] -// CHECK-CPP-NEXT: store float [[CALL_I8]], ptr [[L2_ASCAST]], align 4 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I5:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I4]] to ptr +// CHECK-CPP-NEXT: store float [[TMP2]], ptr [[__X_ADDR_ASCAST_I5]], align 4 +// CHECK-CPP-NEXT: [[TMP3:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I5]], align 4 +// CHECK-CPP-NEXT: [[CALL_I6:%.*]] = call noundef float @__ocml_cos_f32(float noundef [[TMP3]]) #[[ATTR3]] +// CHECK-CPP-NEXT: store float [[CALL_I6]], ptr [[L2_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP4:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I11:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I9]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I12:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I10]] to ptr -// CHECK-CPP-NEXT: store float [[TMP4]], ptr [[__X_ADDR_ASCAST_I12]], align 4 -// CHECK-CPP-NEXT: [[TMP5:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I12]], align 4 +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I8:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I7]] to ptr +// CHECK-CPP-NEXT: store float [[TMP4]], ptr [[__X_ADDR_ASCAST_I8]], align 4 +// CHECK-CPP-NEXT: [[TMP5:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I8]], align 4 // CHECK-CPP-NEXT: [[TMP6:%.*]] = call noundef float @llvm.fabs.f32(float [[TMP5]]) // CHECK-CPP-NEXT: store float [[TMP6]], ptr [[L3_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP7:%.*]] = load float, ptr [[X_ADDR_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP8:%.*]] = load float, ptr [[Y_ADDR_ASCAST]], align 4 // CHECK-CPP-NEXT: [[TMP9:%.*]] = load float, ptr [[Z_ADDR_ASCAST]], align 4 -// CHECK-CPP-NEXT: [[RETVAL_ASCAST_I15:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I13]] to ptr -// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I16:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I14]] to ptr +// CHECK-CPP-NEXT: [[__X_ADDR_ASCAST_I10:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I9]] to ptr // CHECK-CPP-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-CPP-NEXT: [[__Z_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I]] to ptr -// CHECK-CPP-NEXT: store float [[TMP7]], ptr [[__X_ADDR_ASCAST_I16]], align 4 +// CHECK-CPP-NEXT: store float [[TMP7]], ptr [[__X_ADDR_ASCAST_I10]], align 4 // CHECK-CPP-NEXT: store float [[TMP8]], ptr [[__Y_ADDR_ASCAST_I]], align 4 // CHECK-CPP-NEXT: store float [[TMP9]], ptr [[__Z_ADDR_ASCAST_I]], align 4 -// CHECK-CPP-NEXT: [[TMP10:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I16]], align 4 +// CHECK-CPP-NEXT: [[TMP10:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I10]], align 4 // CHECK-CPP-NEXT: [[TMP11:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I]], align 4 // CHECK-CPP-NEXT: [[TMP12:%.*]] = load float, ptr [[__Z_ADDR_ASCAST_I]], align 4 // CHECK-CPP-NEXT: [[TMP13:%.*]] = call noundef float @llvm.fma.f32(float [[TMP10]], float [[TMP11]], float [[TMP12]]) diff --git a/clang/test/Headers/amdgcn_openmp_device_math_c.c b/clang/test/Headers/amdgcn_openmp_device_math_c.c index 0eb5edeb5ba6c..5699e50d824db 100644 --- a/clang/test/Headers/amdgcn_openmp_device_math_c.c +++ b/clang/test/Headers/amdgcn_openmp_device_math_c.c @@ -8,7 +8,6 @@ // CHECK-LABEL: @test_math_int( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[__SGN_I:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4, addrspace(5) @@ -17,7 +16,6 @@ // CHECK-NEXT: [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr // CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR_ASCAST]], align 4 -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr // CHECK-NEXT: store i32 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 4 @@ -38,7 +36,6 @@ void test_math_int(int x) { // CHECK-LABEL: @test_math_long( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[__SGN_I:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8, addrspace(5) @@ -47,7 +44,6 @@ void test_math_int(int x) { // CHECK-NEXT: [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr // CHECK-NEXT: store i64 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[X_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr // CHECK-NEXT: store i64 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 8 @@ -68,7 +64,6 @@ void test_math_long(long x) { // CHECK-LABEL: @test_math_long_long( // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[__SGN_I:%.*]] = alloca i64, align 8, addrspace(5) // CHECK-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8, addrspace(5) @@ -77,7 +72,6 @@ void test_math_long(long x) { // CHECK-NEXT: [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr // CHECK-NEXT: store i64 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[X_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr // CHECK-NEXT: store i64 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 8 diff --git a/clang/test/Headers/amdgcn_openmp_device_math_constexpr.cpp b/clang/test/Headers/amdgcn_openmp_device_math_constexpr.cpp index 0fdc02edc1508..d2235f94f93cb 100644 --- a/clang/test/Headers/amdgcn_openmp_device_math_constexpr.cpp +++ b/clang/test/Headers/amdgcn_openmp_device_math_constexpr.cpp @@ -38,9 +38,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK-SAME: () #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 @@ -52,15 +50,11 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[RETVAL_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I_I]] to ptr // CHECK-NEXT: store float [[TMP0]], ptr [[__X_ADDR_ASCAST_I_I]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I_I]], align 4 @@ -72,9 +66,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 @@ -86,15 +78,11 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[RETVAL_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I_I]] to ptr // CHECK-NEXT: store float [[TMP0]], ptr [[__X_ADDR_ASCAST_I_I]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I_I]], align 4 @@ -106,9 +94,7 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 @@ -120,15 +106,11 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.5 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: store float -2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[RETVAL_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I_I]] to ptr // CHECK-NEXT: store float [[TMP0]], ptr [[__X_ADDR_ASCAST_I_I]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I_I]], align 4 @@ -140,11 +122,9 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.6 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Z_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-NEXT: [[__Z_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I]] to ptr @@ -162,15 +142,12 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.7 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Y_ADDR_I_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Z_ADDR_I_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Z_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-NEXT: [[__Z_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I]] to ptr @@ -180,7 +157,6 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[__X_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__Y_ADDR_ASCAST_I]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[__Z_ADDR_ASCAST_I]], align 4 -// CHECK-NEXT: [[RETVAL_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I_I]] to ptr // CHECK-NEXT: [[__Y_ADDR_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I_I]] to ptr // CHECK-NEXT: [[__Z_ADDR_ASCAST_I_I:%.*]] = addrspacecast ptr addrspace(5) [[__Z_ADDR_I_I]] to ptr @@ -198,10 +174,8 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.8 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-NEXT: store float 2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 @@ -216,10 +190,8 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.9 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-NEXT: store float 2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 @@ -250,10 +222,8 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.12 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-NEXT: store float 2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 @@ -268,10 +238,8 @@ const float constexpr_fmaxf_f32 = fmaxf(2.0f, -4.0f); // CHECK-LABEL: define {{[^@]+}}@__cxx_global_var_init.13 // CHECK-SAME: () #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[__Y_ADDR_I:%.*]] = alloca float, align 4, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr // CHECK-NEXT: [[__Y_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__Y_ADDR_I]] to ptr // CHECK-NEXT: store float 2.000000e+00, ptr [[__X_ADDR_ASCAST_I]], align 4 diff --git a/clang/test/Headers/gpu_disabled_math.cpp b/clang/test/Headers/gpu_disabled_math.cpp index 6e697f52120ae..8d0667eae6f97 100644 --- a/clang/test/Headers/gpu_disabled_math.cpp +++ b/clang/test/Headers/gpu_disabled_math.cpp @@ -18,9 +18,7 @@ extern "C" double sin(double x); // AMDGPU-LABEL: define dso_local noundef double @_Z3food( // AMDGPU-SAME: double noundef [[X:%.*]]) #[[ATTR0:[0-9]+]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca double, align 8, addrspace(5) // AMDGPU-NEXT: [[X_ADDR:%.*]] = alloca double, align 8, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr // AMDGPU-NEXT: store double [[X]], ptr [[X_ADDR_ASCAST]], align 8 // AMDGPU-NEXT: [[TMP0:%.*]] = load double, ptr [[X_ADDR_ASCAST]], align 8 diff --git a/clang/test/Headers/gpuintrin.c b/clang/test/Headers/gpuintrin.c index 891a5abf7a72a..a9b9889b280ae 100644 --- a/clang/test/Headers/gpuintrin.c +++ b/clang/test/Headers/gpuintrin.c @@ -82,8 +82,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_num_blocks_x( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() // AMDGPU-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP0]], i32 12 // AMDGPU-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG3:![0-9]+]], !invariant.load [[META4:![0-9]+]] @@ -98,8 +96,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_num_blocks_y( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() // AMDGPU-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP0]], i32 16 // AMDGPU-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG3]], !invariant.load [[META4]] @@ -114,8 +110,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_num_blocks_z( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() // AMDGPU-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP0]], i32 20 // AMDGPU-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[TMP1]], align 4, !range [[RNG3]], !invariant.load [[META4]] @@ -132,7 +126,6 @@ __gpu_kernel void foo() { // AMDGPU-NEXT: [[ENTRY:.*:]] // AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__DIM_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__DIM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__DIM_ADDR]] to ptr // AMDGPU-NEXT: store i32 [[__DIM]], ptr [[__DIM_ADDR_ASCAST]], align 4 // AMDGPU-NEXT: [[TMP0:%.*]] = load i32, ptr [[__DIM_ADDR_ASCAST]], align 4 @@ -143,29 +136,27 @@ __gpu_kernel void foo() { // AMDGPU-NEXT: ] // AMDGPU: [[SW_BB]]: // AMDGPU-NEXT: [[CALL:%.*]] = call i32 @__gpu_num_blocks_x() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN:.*]] // AMDGPU: [[SW_BB1]]: // AMDGPU-NEXT: [[CALL2:%.*]] = call i32 @__gpu_num_blocks_y() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL2]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL2]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[SW_BB3]]: // AMDGPU-NEXT: [[CALL4:%.*]] = call i32 @__gpu_num_blocks_z() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL4]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL4]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[SW_DEFAULT]]: -// AMDGPU-NEXT: store i32 1, ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 1, ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[RETURN]]: -// AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: ret i32 [[TMP1]] // // // AMDGPU-LABEL: define internal i32 @__gpu_block_id_x( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.x() // AMDGPU-NEXT: ret i32 [[TMP0]] // @@ -173,8 +164,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_block_id_y( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.y() // AMDGPU-NEXT: ret i32 [[TMP0]] // @@ -182,8 +171,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_block_id_z( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workgroup.id.z() // AMDGPU-NEXT: ret i32 [[TMP0]] // @@ -193,7 +180,6 @@ __gpu_kernel void foo() { // AMDGPU-NEXT: [[ENTRY:.*:]] // AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__DIM_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__DIM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__DIM_ADDR]] to ptr // AMDGPU-NEXT: store i32 [[__DIM]], ptr [[__DIM_ADDR_ASCAST]], align 4 // AMDGPU-NEXT: [[TMP0:%.*]] = load i32, ptr [[__DIM_ADDR_ASCAST]], align 4 @@ -204,29 +190,27 @@ __gpu_kernel void foo() { // AMDGPU-NEXT: ] // AMDGPU: [[SW_BB]]: // AMDGPU-NEXT: [[CALL:%.*]] = call i32 @__gpu_block_id_x() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN:.*]] // AMDGPU: [[SW_BB1]]: // AMDGPU-NEXT: [[CALL2:%.*]] = call i32 @__gpu_block_id_y() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL2]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL2]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[SW_BB3]]: // AMDGPU-NEXT: [[CALL4:%.*]] = call i32 @__gpu_block_id_z() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL4]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL4]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[SW_DEFAULT]]: -// AMDGPU-NEXT: store i32 0, ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 0, ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[RETURN]]: -// AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: ret i32 [[TMP1]] // // // AMDGPU-LABEL: define internal i32 @__gpu_num_threads_x( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() // AMDGPU-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP0]], i32 12 // AMDGPU-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2, !range [[RNG5]], !invariant.load [[META4]], !noundef [[META4]] @@ -237,8 +221,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_num_threads_y( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() // AMDGPU-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP0]], i32 14 // AMDGPU-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2, !range [[RNG5]], !invariant.load [[META4]], !noundef [[META4]] @@ -249,8 +231,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_num_threads_z( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call align 8 dereferenceable(256) ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() // AMDGPU-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP0]], i32 16 // AMDGPU-NEXT: [[TMP2:%.*]] = load i16, ptr addrspace(4) [[TMP1]], align 2, !range [[RNG5]], !invariant.load [[META4]], !noundef [[META4]] @@ -263,7 +243,6 @@ __gpu_kernel void foo() { // AMDGPU-NEXT: [[ENTRY:.*:]] // AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__DIM_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__DIM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__DIM_ADDR]] to ptr // AMDGPU-NEXT: store i32 [[__DIM]], ptr [[__DIM_ADDR_ASCAST]], align 4 // AMDGPU-NEXT: [[TMP0:%.*]] = load i32, ptr [[__DIM_ADDR_ASCAST]], align 4 @@ -274,29 +253,27 @@ __gpu_kernel void foo() { // AMDGPU-NEXT: ] // AMDGPU: [[SW_BB]]: // AMDGPU-NEXT: [[CALL:%.*]] = call i32 @__gpu_num_threads_x() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN:.*]] // AMDGPU: [[SW_BB1]]: // AMDGPU-NEXT: [[CALL2:%.*]] = call i32 @__gpu_num_threads_y() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL2]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL2]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[SW_BB3]]: // AMDGPU-NEXT: [[CALL4:%.*]] = call i32 @__gpu_num_threads_z() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL4]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL4]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[SW_DEFAULT]]: -// AMDGPU-NEXT: store i32 1, ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 1, ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[RETURN]]: -// AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: ret i32 [[TMP1]] // // // AMDGPU-LABEL: define internal i32 @__gpu_thread_id_x( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() // AMDGPU-NEXT: ret i32 [[TMP0]] // @@ -304,8 +281,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_thread_id_y( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.y() // AMDGPU-NEXT: ret i32 [[TMP0]] // @@ -313,8 +288,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_thread_id_z( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.z() // AMDGPU-NEXT: ret i32 [[TMP0]] // @@ -324,7 +297,6 @@ __gpu_kernel void foo() { // AMDGPU-NEXT: [[ENTRY:.*:]] // AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__DIM_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__DIM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__DIM_ADDR]] to ptr // AMDGPU-NEXT: store i32 [[__DIM]], ptr [[__DIM_ADDR_ASCAST]], align 4 // AMDGPU-NEXT: [[TMP0:%.*]] = load i32, ptr [[__DIM_ADDR_ASCAST]], align 4 @@ -335,29 +307,27 @@ __gpu_kernel void foo() { // AMDGPU-NEXT: ] // AMDGPU: [[SW_BB]]: // AMDGPU-NEXT: [[CALL:%.*]] = call i32 @__gpu_thread_id_x() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN:.*]] // AMDGPU: [[SW_BB1]]: // AMDGPU-NEXT: [[CALL2:%.*]] = call i32 @__gpu_thread_id_y() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL2]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL2]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[SW_BB3]]: // AMDGPU-NEXT: [[CALL4:%.*]] = call i32 @__gpu_thread_id_z() #[[ATTR8]] -// AMDGPU-NEXT: store i32 [[CALL4]], ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 [[CALL4]], ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[SW_DEFAULT]]: -// AMDGPU-NEXT: store i32 0, ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: store i32 0, ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: br label %[[RETURN]] // AMDGPU: [[RETURN]]: -// AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL_ASCAST]], align 4 +// AMDGPU-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[RETVAL]], align 4 // AMDGPU-NEXT: ret i32 [[TMP1]] // // // AMDGPU-LABEL: define internal i32 @__gpu_num_lanes( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.wavefrontsize() // AMDGPU-NEXT: ret i32 [[TMP0]] // @@ -365,8 +335,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_lane_id( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) // AMDGPU-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[TMP0]]) // AMDGPU-NEXT: ret i32 [[TMP1]] @@ -375,8 +343,6 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i64 @__gpu_lane_mask( // AMDGPU-SAME: ) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i64, align 8, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) // AMDGPU-NEXT: ret i64 [[TMP0]] // @@ -384,10 +350,8 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_read_first_lane_u32( // AMDGPU-SAME: i64 noundef [[__LANE_MASK:%.*]], i32 noundef [[__X:%.*]]) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__LANE_MASK_ADDR:%.*]] = alloca i64, align 8, addrspace(5) // AMDGPU-NEXT: [[__X_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__LANE_MASK_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__LANE_MASK_ADDR]] to ptr // AMDGPU-NEXT: [[__X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR]] to ptr // AMDGPU-NEXT: store i64 [[__LANE_MASK]], ptr [[__LANE_MASK_ADDR_ASCAST]], align 8 @@ -400,12 +364,10 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i64 @__gpu_read_first_lane_u64( // AMDGPU-SAME: i64 noundef [[__LANE_MASK:%.*]], i64 noundef [[__X:%.*]]) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i64, align 8, addrspace(5) // AMDGPU-NEXT: [[__LANE_MASK_ADDR:%.*]] = alloca i64, align 8, addrspace(5) // AMDGPU-NEXT: [[__X_ADDR:%.*]] = alloca i64, align 8, addrspace(5) // AMDGPU-NEXT: [[__HI:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__LO:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__LANE_MASK_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__LANE_MASK_ADDR]] to ptr // AMDGPU-NEXT: [[__X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR]] to ptr // AMDGPU-NEXT: [[__HI_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__HI]] to ptr @@ -437,10 +399,8 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i64 @__gpu_ballot( // AMDGPU-SAME: i64 noundef [[__LANE_MASK:%.*]], i1 noundef zeroext [[__X:%.*]]) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i64, align 8, addrspace(5) // AMDGPU-NEXT: [[__LANE_MASK_ADDR:%.*]] = alloca i64, align 8, addrspace(5) // AMDGPU-NEXT: [[__X_ADDR:%.*]] = alloca i8, align 1, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__LANE_MASK_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__LANE_MASK_ADDR]] to ptr // AMDGPU-NEXT: [[__X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR]] to ptr // AMDGPU-NEXT: store i64 [[__LANE_MASK]], ptr [[__LANE_MASK_ADDR_ASCAST]], align 8 @@ -475,13 +435,11 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i32 @__gpu_shuffle_idx_u32( // AMDGPU-SAME: i64 noundef [[__LANE_MASK:%.*]], i32 noundef [[__IDX:%.*]], i32 noundef [[__X:%.*]], i32 noundef [[__WIDTH:%.*]]) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__LANE_MASK_ADDR:%.*]] = alloca i64, align 8, addrspace(5) // AMDGPU-NEXT: [[__IDX_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__X_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__WIDTH_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // AMDGPU-NEXT: [[__LANE:%.*]] = alloca i32, align 4, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__LANE_MASK_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__LANE_MASK_ADDR]] to ptr // AMDGPU-NEXT: [[__IDX_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__IDX_ADDR]] to ptr // AMDGPU-NEXT: [[__X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR]] to ptr @@ -509,9 +467,7 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal i64 @__gpu_first_lane_id( // AMDGPU-SAME: i64 noundef [[__LANE_MASK:%.*]]) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i64, align 8, addrspace(5) // AMDGPU-NEXT: [[__LANE_MASK_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__LANE_MASK_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__LANE_MASK_ADDR]] to ptr // AMDGPU-NEXT: store i64 [[__LANE_MASK]], ptr [[__LANE_MASK_ADDR_ASCAST]], align 8 // AMDGPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[__LANE_MASK_ADDR_ASCAST]], align 8 @@ -528,9 +484,7 @@ __gpu_kernel void foo() { // AMDGPU-LABEL: define internal zeroext i1 @__gpu_is_first_in_lane( // AMDGPU-SAME: i64 noundef [[__LANE_MASK:%.*]]) #[[ATTR0]] { // AMDGPU-NEXT: [[ENTRY:.*:]] -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca i1, align 1, addrspace(5) // AMDGPU-NEXT: [[__LANE_MASK_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[__LANE_MASK_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__LANE_MASK_ADDR]] to ptr // AMDGPU-NEXT: store i64 [[__LANE_MASK]], ptr [[__LANE_MASK_ADDR_ASCAST]], align 8 // AMDGPU-NEXT: [[CALL:%.*]] = call i32 @__gpu_lane_id() #[[ATTR8]] @@ -1422,3 +1376,9 @@ __gpu_kernel void foo() { // SPIRV-NEXT: [[ENTRY:.*:]] // SPIRV-NEXT: call void @llvm.trap() // SPIRV-NEXT: ret void +// +//. +// AMDGPU: [[RNG3]] = !{i32 1, i32 0} +// AMDGPU: [[META4]] = !{} +// AMDGPU: [[RNG5]] = !{i16 1, i16 1025} +//. diff --git a/clang/test/Headers/gpuintrin_lang.c b/clang/test/Headers/gpuintrin_lang.c index e3db72d5ff928..433d24b18d654 100644 --- a/clang/test/Headers/gpuintrin_lang.c +++ b/clang/test/Headers/gpuintrin_lang.c @@ -49,10 +49,6 @@ extern "C" [[clang::sycl_external]] int foo() { return __gpu_thread_id_x(); } // HIP-LABEL: define dso_local i32 @foo( // HIP-SAME: ) #[[ATTR0:[0-9]+]] { // HIP-NEXT: [[ENTRY:.*:]] -// HIP-NEXT: [[RETVAL_I:%.*]] = alloca i32, align 4, addrspace(5) -// HIP-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// HIP-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr -// HIP-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // HIP-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() // HIP-NEXT: ret i32 [[TMP0]] // @@ -71,10 +67,6 @@ extern "C" [[clang::sycl_external]] int foo() { return __gpu_thread_id_x(); } // SYCL-LABEL: define spir_func i32 @foo( // SYCL-SAME: ) #[[ATTR0:[0-9]+]] { // SYCL-NEXT: [[ENTRY:.*:]] -// SYCL-NEXT: [[RETVAL_I:%.*]] = alloca i32, align 4 -// SYCL-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 -// SYCL-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4) -// SYCL-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr [[RETVAL_I]] to ptr addrspace(4) // SYCL-NEXT: [[SPV_THREAD_ID_IN_GROUP_I:%.*]] = call i64 @llvm.spv.thread.id.in.group.i64(i32 0) // SYCL-NEXT: [[CONV_I:%.*]] = trunc i64 [[SPV_THREAD_ID_IN_GROUP_I]] to i32 // SYCL-NEXT: ret i32 [[CONV_I]] @@ -82,10 +74,6 @@ extern "C" [[clang::sycl_external]] int foo() { return __gpu_thread_id_x(); } // C89-LABEL: define dso_local i32 @foo( // C89-SAME: ) #[[ATTR0:[0-9]+]] { // C89-NEXT: [[ENTRY:.*:]] -// C89-NEXT: [[RETVAL_I:%.*]] = alloca i32, align 4, addrspace(5) -// C89-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// C89-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr -// C89-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr // C89-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() // C89-NEXT: ret i32 [[TMP0]] // diff --git a/clang/test/Headers/openmp-device-functions-bool.c b/clang/test/Headers/openmp-device-functions-bool.c index bb01096027849..3d5ea9009c1d9 100644 --- a/clang/test/Headers/openmp-device-functions-bool.c +++ b/clang/test/Headers/openmp-device-functions-bool.c @@ -18,12 +18,10 @@ typedef _Bool ockl_bool; // CHECK-LABEL: define hidden float @test_fdot2 // CHECK-SAME: (<2 x half> noundef [[A:%.*]], <2 x half> noundef [[B:%.*]], float noundef [[C:%.*]], i1 noundef zeroext [[S:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[A_ADDR:%.*]] = alloca <2 x half>, align 4, addrspace(5) // CHECK-NEXT: [[B_ADDR:%.*]] = alloca <2 x half>, align 4, addrspace(5) // CHECK-NEXT: [[C_ADDR:%.*]] = alloca float, align 4, addrspace(5) // CHECK-NEXT: [[S_ADDR:%.*]] = alloca i8, align 1, addrspace(5) -// CHECK-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr // CHECK-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr // CHECK-NEXT: [[C_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[C_ADDR]] to ptr @@ -31,14 +29,14 @@ typedef _Bool ockl_bool; // CHECK-NEXT: store <2 x half> [[A]], ptr [[A_ADDR_ASCAST]], align 4 // CHECK-NEXT: store <2 x half> [[B]], ptr [[B_ADDR_ASCAST]], align 4 // CHECK-NEXT: store float [[C]], ptr [[C_ADDR_ASCAST]], align 4 -// CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[S]] to i8 -// CHECK-NEXT: store i8 [[FROMBOOL]], ptr [[S_ADDR_ASCAST]], align 1 +// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[S]] to i8 +// CHECK-NEXT: store i8 [[STOREDV]], ptr [[S_ADDR_ASCAST]], align 1 // CHECK-NEXT: [[TMP0:%.*]] = load <2 x half>, ptr [[A_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[B_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[C_ADDR_ASCAST]], align 4 // CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[S_ADDR_ASCAST]], align 1 -// CHECK-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 -// CHECK-NEXT: [[CALL:%.*]] = call float @__ockl_fdot2(<2 x half> noundef [[TMP0]], <2 x half> noundef [[TMP1]], float noundef [[TMP2]], i1 noundef zeroext [[TOBOOL]]) #[[ATTR2:[0-9]+]] +// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK-NEXT: [[CALL:%.*]] = call float @__ockl_fdot2(<2 x half> noundef [[TMP0]], <2 x half> noundef [[TMP1]], float noundef [[TMP2]], i1 noundef zeroext [[LOADEDV]]) #[[ATTR2:[0-9]+]] // CHECK-NEXT: ret float [[CALL]] // EXTERN_C float test_fdot2(__2f16 a, __2f16 b, float c, ockl_bool s) { @@ -56,11 +54,9 @@ enum my_bool { // CHECK-C-LABEL: define hidden i32 @use_my_bool // CHECK-C-SAME: (i32 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-C-NEXT: entry: -// CHECK-C-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-C-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-C-NEXT: [[T:%.*]] = alloca i32, align 4, addrspace(5) // CHECK-C-NEXT: [[F:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-C-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // CHECK-C-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr // CHECK-C-NEXT: [[T_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[T]] to ptr // CHECK-C-NEXT: [[F_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F]] to ptr diff --git a/clang/test/Headers/openmp_new_nothrow.cpp b/clang/test/Headers/openmp_new_nothrow.cpp index 1208387013547..d46ba46f327d8 100644 --- a/clang/test/Headers/openmp_new_nothrow.cpp +++ b/clang/test/Headers/openmp_new_nothrow.cpp @@ -22,8 +22,6 @@ extern const std::nothrow_t nothrow; // AMDGPU-LABEL: define hidden noundef ptr @_Z17new_stuff_nothrowv // AMDGPU-SAME: () #[[ATTR0:[0-9]+]] { // AMDGPU-NEXT: entry: -// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5) -// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnwmRKSt9nothrow_t(i64 noundef 4, ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR4:[0-9]+]] // AMDGPU-NEXT: ret ptr [[CALL]] // @@ -52,16 +50,12 @@ int* new_stuff_nothrow() { // AMDGPU-CXX03-LABEL: define hidden noundef ptr @_Z23new_array_stuff_nothrowv // AMDGPU-CXX03-SAME: () #[[ATTR0]] { // AMDGPU-CXX03-NEXT: entry: -// AMDGPU-CXX03-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5) -// AMDGPU-CXX03-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-CXX03-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnamRKSt9nothrow_t(i64 noundef 136, ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR4]] // AMDGPU-CXX03-NEXT: ret ptr [[CALL]] // // AMDGPU-CXX11-LABEL: define hidden noundef ptr @_Z23new_array_stuff_nothrowv // AMDGPU-CXX11-SAME: () #[[ATTR0]] { // AMDGPU-CXX11-NEXT: entry: -// AMDGPU-CXX11-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5) -// AMDGPU-CXX11-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // AMDGPU-CXX11-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnamRKSt9nothrow_t(i64 noundef 136, ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR7:[0-9]+]] // AMDGPU-CXX11-NEXT: ret ptr [[CALL]] // diff --git a/clang/test/Misc/target-invalid-cpu-note/amdgcn.c b/clang/test/Misc/target-invalid-cpu-note/amdgcn.c index c554dad4171e4..a82258c6be1dc 100644 --- a/clang/test/Misc/target-invalid-cpu-note/amdgcn.c +++ b/clang/test/Misc/target-invalid-cpu-note/amdgcn.c @@ -66,6 +66,7 @@ // CHECK-SAME: {{^}}, gfx1151 // CHECK-SAME: {{^}}, gfx1152 // CHECK-SAME: {{^}}, gfx1153 +// CHECK-SAME: {{^}}, gfx1170 // CHECK-SAME: {{^}}, gfx1200 // CHECK-SAME: {{^}}, gfx1201 // CHECK-SAME: {{^}}, gfx1250 diff --git a/clang/test/Misc/target-invalid-cpu-note/nvptx.c b/clang/test/Misc/target-invalid-cpu-note/nvptx.c index 8dd485a1fdbca..acd6d812e3f84 100644 --- a/clang/test/Misc/target-invalid-cpu-note/nvptx.c +++ b/clang/test/Misc/target-invalid-cpu-note/nvptx.c @@ -87,6 +87,7 @@ // CHECK-SAME: {{^}}, gfx1151 // CHECK-SAME: {{^}}, gfx1152 // CHECK-SAME: {{^}}, gfx1153 +// CHECK-SAME: {{^}}, gfx1170 // CHECK-SAME: {{^}}, gfx12-generic // CHECK-SAME: {{^}}, gfx1200 // CHECK-SAME: {{^}}, gfx1201 diff --git a/clang/test/Misc/target-invalid-cpu-note/x86.c b/clang/test/Misc/target-invalid-cpu-note/x86.c index 4a70e9bff3fef..766bd679796f5 100644 --- a/clang/test/Misc/target-invalid-cpu-note/x86.c +++ b/clang/test/Misc/target-invalid-cpu-note/x86.c @@ -103,6 +103,7 @@ // X86-SAME: {{^}}, znver3 // X86-SAME: {{^}}, znver4 // X86-SAME: {{^}}, znver5 +// X86-SAME: {{^}}, znver6 // X86-SAME: {{^}}, x86-64 // X86-SAME: {{^}}, x86-64-v2 // X86-SAME: {{^}}, x86-64-v3 @@ -183,6 +184,7 @@ // X86_64-SAME: {{^}}, znver3 // X86_64-SAME: {{^}}, znver4 // X86_64-SAME: {{^}}, znver5 +// X86_64-SAME: {{^}}, znver6 // X86_64-SAME: {{^}}, x86-64 // X86_64-SAME: {{^}}, x86-64-v2 // X86_64-SAME: {{^}}, x86-64-v3 @@ -290,6 +292,7 @@ // TUNE_X86-SAME: {{^}}, znver3 // TUNE_X86-SAME: {{^}}, znver4 // TUNE_X86-SAME: {{^}}, znver5 +// TUNE_X86-SAME: {{^}}, znver6 // TUNE_X86-SAME: {{^}}, x86-64 // TUNE_X86-SAME: {{^}}, geode // TUNE_X86-SAME: {{$}} @@ -395,6 +398,7 @@ // TUNE_X86_64-SAME: {{^}}, znver3 // TUNE_X86_64-SAME: {{^}}, znver4 // TUNE_X86_64-SAME: {{^}}, znver5 +// TUNE_X86_64-SAME: {{^}}, znver6 // TUNE_X86_64-SAME: {{^}}, x86-64 // TUNE_X86_64-SAME: {{^}}, geode // TUNE_X86_64-SAME: {{$}} diff --git a/clang/test/Modules/single-module-parse-mode-compiles.m b/clang/test/Modules/single-module-parse-mode-compiles.m new file mode 100644 index 0000000000000..8e9b92c86fe61 --- /dev/null +++ b/clang/test/Modules/single-module-parse-mode-compiles.m @@ -0,0 +1,36 @@ +// This test checks that with -fmodules-single-module-parse-mode, no modules get +// compiled into PCM files from any of the import syntax Clang supports. + +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: mkdir %t/cache + +// With -fmodules-single-module-parse-mode, no modules get compiled. +// RUN: %clang_cc1 -x objective-c -fmodules -fmodules-cache-path=%t/cache \ +// RUN: -emit-module %t/module.modulemap -fmodule-name=Mod -o %t/Mod.pcm \ +// RUN: -fmodules-single-module-parse-mode +// RUN: find %t/cache -name "*.pcm" | count 0 + +// Without -fmodules-single-module-parse-mode, loaded modules get compiled. +// RUN: %clang_cc1 -x objective-c -fmodules -fmodules-cache-path=%t/cache \ +// RUN: -emit-module %t/module.modulemap -fmodule-name=Mod -o %t/Mod.pcm +// RUN: find %t/cache -name "*.pcm" | count 5 + +//--- module.modulemap +module Mod { header "Mod.h" } +module Load1 { header "Load1.h" } +module Load2 { header "Load2.h" } +module Load3 { header "Load3.h" } +module Load4 { header "Load4.h" } +module Load5 { header "Load5.h" } +//--- Mod.h +#include "Load1.h" +#import "Load2.h" +@import Load3; +#pragma clang module import Load4 +#pragma clang module load Load5 +//--- Load1.h +//--- Load2.h +//--- Load3.h +//--- Load4.h +//--- Load5.h diff --git a/clang/test/Modules/validate-file-content.m b/clang/test/Modules/validate-file-content.m index cff89884552b7..1eae7748165c1 100644 --- a/clang/test/Modules/validate-file-content.m +++ b/clang/test/Modules/validate-file-content.m @@ -24,7 +24,7 @@ // RUN: not %clang_cc1 -fsyntax-only -fmodules-cache-path=%t/cache -fmodules -fimplicit-module-maps -I %t -include-pch %t/a.pch %s -fvalidate-ast-input-files-content 2> %t/stderr // RUN: FileCheck %s < %t/stderr // -// CHECK: file '[[M_H:.*[/\\]m\.h]]' has been modified since the precompiled header '[[A_PCH:.*/a\.pch]]' was built: content changed +// CHECK: file '[[M_H:.*[/\\]m\.h]]' has been modified since the precompiled header '[[A_PCH:.*[/\\]a\.pch]]' was built: content changed // CHECK: '[[M_H]]' required by '[[M_PCM:.*[/\\]m.*\.pcm]]' // CHECK: '[[M_PCM]]' required by '[[A_PCH]]' // CHECK: please rebuild precompiled file '[[A_PCH]]' diff --git a/clang/test/OpenMP/amdgcn_target_global_constructor.cpp b/clang/test/OpenMP/amdgcn_target_global_constructor.cpp index bbfb0c4d9b11e..045f199653382 100644 --- a/clang/test/OpenMP/amdgcn_target_global_constructor.cpp +++ b/clang/test/OpenMP/amdgcn_target_global_constructor.cpp @@ -49,13 +49,13 @@ S A; // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[THIS_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[THIS_ADDR]] to ptr // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR_ASCAST]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR_ASCAST]], align 8 -// CHECK-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4:[0-9]+]] +// CHECK-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4:[0-9]+]] // CHECK-NEXT: ret void // // @@ -79,7 +79,7 @@ S A; // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) // CHECK-NEXT: [[THIS_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[THIS_ADDR]] to ptr diff --git a/clang/test/OpenMP/amdgcn_weak_alias.c b/clang/test/OpenMP/amdgcn_weak_alias.c index 33c7dc0041810..c647d7eb89f8c 100644 --- a/clang/test/OpenMP/amdgcn_weak_alias.c +++ b/clang/test/OpenMP/amdgcn_weak_alias.c @@ -26,6 +26,11 @@ // HOST: @Three_var = weak alias i32, ptr @__Three_var // HOST: @Three_var_ = alias i32, ptr @__Three_var //. +// DEVICE: @__omp_rtl_debug_kind = weak_odr hidden addrspace(1) constant i32 0 +// DEVICE: @__omp_rtl_assume_teams_oversubscription = weak_odr hidden addrspace(1) constant i32 0 +// DEVICE: @__omp_rtl_assume_threads_oversubscription = weak_odr hidden addrspace(1) constant i32 0 +// DEVICE: @__omp_rtl_assume_no_thread_state = weak_odr hidden addrspace(1) constant i32 0 +// DEVICE: @__omp_rtl_assume_no_nested_parallelism = weak_odr hidden addrspace(1) constant i32 0 // DEVICE: @__Two_var = addrspace(1) global i32 2, align 4 // DEVICE: @__Three_var = addrspace(1) global i32 3, align 4 // DEVICE: @Two = weak hidden alias i32 (), ptr @__Two @@ -61,8 +66,6 @@ extern int __attribute__((alias("__One_var"))) One_var_; // DEVICE-LABEL: define hidden i32 @__Two( // DEVICE-SAME: ) #[[ATTR0:[0-9]+]] { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: ret i32 2 // int __Two(void) { return 2; } @@ -83,8 +86,6 @@ extern int __attribute__((alias("__Two_var"))) Two_var_; // DEVICE-LABEL: define hidden i32 @__Three( // DEVICE-SAME: ) #[[ATTR0]] { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: ret i32 3 // int __Three(void) { return 3; } @@ -94,3 +95,24 @@ int Three(void) __attribute__ ((weak, alias("__Three"))); int Three_(void) __attribute__ ((alias("__Three"))); extern int __attribute__((weak, alias("__Three_var"))) Three_var; extern int __attribute__((alias("__Three_var"))) Three_var_; +//. +// HOST: attributes #[[ATTR0]] = { noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } +//. +// DEVICE: attributes #[[ATTR0]] = { convergent noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +//. +// HOST: [[META0:![0-9]+]] = !{i32 1, !"__Two_var", i32 0, i32 0} +// HOST: [[META1:![0-9]+]] = !{i32 1, !"__Three_var", i32 0, i32 1} +// HOST: [[META2:![0-9]+]] = !{ptr @.offloading.entry_name} +// HOST: [[META3:![0-9]+]] = !{ptr @.offloading.entry_name.1} +// HOST: [[META4:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// HOST: [[META5:![0-9]+]] = !{i32 7, !"openmp", i32 51} +// HOST: [[META6:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. +// DEVICE: [[META0:![0-9]+]] = !{i32 1, !"__Two_var", i32 0, i32 0} +// DEVICE: [[META1:![0-9]+]] = !{i32 1, !"__Three_var", i32 0, i32 1} +// DEVICE: [[META2:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// DEVICE: [[META3:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// DEVICE: [[META4:![0-9]+]] = !{i32 7, !"openmp", i32 51} +// DEVICE: [[META5:![0-9]+]] = !{i32 7, !"openmp-device", i32 51} +// DEVICE: [[META6:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/OpenMP/amdgcn_weak_alias.cpp b/clang/test/OpenMP/amdgcn_weak_alias.cpp index d1ffff4b1ca01..b8b3c5877c9e8 100644 --- a/clang/test/OpenMP/amdgcn_weak_alias.cpp +++ b/clang/test/OpenMP/amdgcn_weak_alias.cpp @@ -17,6 +17,11 @@ // HOST: @_Z4Fourv = weak alias i32 (), ptr @_Z6__Fourv // HOST: @_Z5Four_v = alias i32 (), ptr @_Z6__Fourv //. +// DEVICE: @__omp_rtl_debug_kind = weak_odr hidden addrspace(1) constant i32 0 +// DEVICE: @__omp_rtl_assume_teams_oversubscription = weak_odr hidden addrspace(1) constant i32 0 +// DEVICE: @__omp_rtl_assume_threads_oversubscription = weak_odr hidden addrspace(1) constant i32 0 +// DEVICE: @__omp_rtl_assume_no_thread_state = weak_odr hidden addrspace(1) constant i32 0 +// DEVICE: @__omp_rtl_assume_no_nested_parallelism = weak_odr hidden addrspace(1) constant i32 0 // DEVICE: @_Z3Twov = weak hidden alias i32 (), ptr @_Z5__Twov // DEVICE: @_Z3Twof = weak hidden alias float (float), ptr @_Z5__Twof // DEVICE: @_Z4Two_v = hidden alias i32 (), ptr @_Z5__Twov @@ -54,8 +59,6 @@ float One_(float f) __attribute__((alias("_Z5__Onef"))); // DEVICE-LABEL: define hidden noundef i32 @_Z5__Twov( // DEVICE-SAME: ) #[[ATTR0:[0-9]+]] { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: ret i32 2 // int __Two(void) { return 2; } @@ -71,9 +74,7 @@ int __Two(void) { return 2; } // DEVICE-LABEL: define hidden noundef float @_Z5__Twof( // DEVICE-SAME: float noundef [[F:%.*]]) #[[ATTR0]] { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca float, align 4, addrspace(5) // DEVICE-NEXT: [[F_ADDR:%.*]] = alloca float, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: [[F_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[F_ADDR]] to ptr // DEVICE-NEXT: store float [[F]], ptr [[F_ADDR_ASCAST]], align 4 // DEVICE-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR_ASCAST]], align 4 @@ -96,8 +97,6 @@ float Two_(float f) __attribute__((alias("_Z5__Twof"))); // DEVICE-LABEL: define linkonce_odr hidden noundef i32 @_Z7__Threev( // DEVICE-SAME: ) #[[ATTR0]] comdat { // DEVICE-NEXT: [[ENTRY:.*:]] -// DEVICE-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5) -// DEVICE-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr // DEVICE-NEXT: ret i32 3 // constexpr int __Three(void) { return 3; } @@ -113,3 +112,18 @@ int Three_(void) __attribute__((alias("_Z7__Threev"))); constexpr int __Four(void) { return 4; } int Four(void) __attribute__((weak, alias("_Z6__Fourv"))); int Four_(void) __attribute__((alias("_Z6__Fourv"))); +//. +// HOST: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+cx8,+mmx,+sse,+sse2,+x87" } +//. +// DEVICE: attributes #[[ATTR0]] = { convergent mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +//. +// HOST: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// HOST: [[META1:![0-9]+]] = !{i32 7, !"openmp", i32 51} +// HOST: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. +// DEVICE: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 600} +// DEVICE: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} +// DEVICE: [[META2:![0-9]+]] = !{i32 7, !"openmp", i32 51} +// DEVICE: [[META3:![0-9]+]] = !{i32 7, !"openmp-device", i32 51} +// DEVICE: [[META4:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} +//. diff --git a/clang/test/OpenMP/distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_firstprivate_codegen.cpp index 7697fcc6f4943..ffffeb61c8c87 100644 --- a/clang/test/OpenMP/distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_firstprivate_codegen.cpp @@ -162,7 +162,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 @@ -181,7 +181,7 @@ int main() { // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK1-NEXT: ret void // @@ -216,12 +216,12 @@ int main() { // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -229,7 +229,7 @@ int main() { // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load volatile double, ptr [[TMP0]], align 8 // CHECK1-NEXT: store double [[TMP5]], ptr [[G3]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP7:%.*]] = load volatile double, ptr [[TMP6]], align 8 // CHECK1-NEXT: store double [[TMP7]], ptr [[G14]], align 8 // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 @@ -267,7 +267,7 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load double, ptr [[G3]], align 8 // CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 // CHECK1-NEXT: store double [[ADD9]], ptr [[G3]], align 8 -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 8 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 // CHECK1-NEXT: store volatile double [[ADD10]], ptr [[TMP19]], align 8 @@ -282,7 +282,7 @@ int main() { // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G3]], ptr [[TMP23]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP26]], align 8 @@ -316,7 +316,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 @@ -337,16 +337,16 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4 // CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK3-NEXT: ret void // @@ -381,12 +381,12 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -394,7 +394,7 @@ int main() { // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load volatile double, ptr [[TMP0]], align 8 // CHECK3-NEXT: store double [[TMP5]], ptr [[G3]], align 8 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP7:%.*]] = load volatile double, ptr [[TMP6]], align 4 // CHECK3-NEXT: store double [[TMP7]], ptr [[G14]], align 8 // CHECK3-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 4 @@ -432,7 +432,7 @@ int main() { // CHECK3-NEXT: [[TMP18:%.*]] = load double, ptr [[G3]], align 8 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 // CHECK3-NEXT: store double [[ADD9]], ptr [[G3]], align 8 -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 4 // CHECK3-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 // CHECK3-NEXT: store volatile double [[ADD10]], ptr [[TMP19]], align 4 @@ -447,7 +447,7 @@ int main() { // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G3]], ptr [[TMP23]], align 4 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP5]], align 4 +// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 4 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR6]], ptr [[TMP26]], align 4 @@ -478,7 +478,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -497,17 +497,17 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -575,17 +575,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -627,11 +627,11 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK9-NEXT: ret void // @@ -656,8 +656,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -668,13 +668,13 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -683,7 +683,7 @@ int main() { // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -696,7 +696,7 @@ int main() { // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK9: omp.arraycpy.done6: -// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i64 4, i1 false) // CHECK9-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4 @@ -735,10 +735,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP20]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -754,14 +754,14 @@ int main() { // CHECK9-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP24]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -769,12 +769,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -785,7 +785,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -801,14 +801,14 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -869,17 +869,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -910,7 +910,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -953,11 +953,11 @@ int main() { // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK9-NEXT: ret void // @@ -981,8 +981,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -991,12 +991,12 @@ int main() { // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1005,7 +1005,7 @@ int main() { // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1018,7 +1018,7 @@ int main() { // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK9: omp.arraycpy.done6: -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i64 4, i1 false) // CHECK9-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1055,10 +1055,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1074,14 +1074,14 @@ int main() { // CHECK9-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1089,12 +1089,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1124,7 +1124,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1141,7 +1141,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1160,17 +1160,17 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1238,17 +1238,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1290,11 +1290,11 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK11-NEXT: ret void // @@ -1319,8 +1319,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1331,13 +1331,13 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1346,7 +1346,7 @@ int main() { // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK11-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1359,7 +1359,7 @@ int main() { // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK11: omp.arraycpy.done6: -// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i32 4, i1 false) // CHECK11-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4 @@ -1397,9 +1397,9 @@ int main() { // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP21]] +// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 [[TMP21]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP20]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1415,14 +1415,14 @@ int main() { // CHECK11-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP24]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -1430,12 +1430,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1446,7 +1446,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1462,14 +1462,14 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1530,17 +1530,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -1571,7 +1571,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1614,11 +1614,11 @@ int main() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK11-NEXT: ret void // @@ -1642,8 +1642,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1652,12 +1652,12 @@ int main() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1666,7 +1666,7 @@ int main() { // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1679,7 +1679,7 @@ int main() { // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK11: omp.arraycpy.done6: -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i32 4, i1 false) // CHECK11-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1715,9 +1715,9 @@ int main() { // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1733,14 +1733,14 @@ int main() { // CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -1748,12 +1748,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1783,7 +1783,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_lastprivate_codegen.cpp index 4790192de986b..46a7dc17bf9c3 100644 --- a/clang/test/OpenMP/distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_lastprivate_codegen.cpp @@ -152,7 +152,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 @@ -171,7 +171,7 @@ int main() { // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK1-NEXT: ret void // @@ -206,18 +206,18 @@ int main() { // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 @@ -247,14 +247,14 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G3]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP14]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR6]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G3]], ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP18]], align 8 @@ -303,7 +303,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 @@ -324,16 +324,16 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4 // CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK3-NEXT: ret void // @@ -368,18 +368,18 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 @@ -409,14 +409,14 @@ int main() { // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G3]], align 8 -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP14]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR6]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G3]], ptr [[TMP15]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP5]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR6]], ptr [[TMP18]], align 4 @@ -462,7 +462,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -482,17 +482,17 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -560,17 +560,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -612,11 +612,11 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK9-NEXT: ret void // @@ -641,8 +641,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -653,19 +653,19 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -675,7 +675,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -712,10 +712,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -738,7 +738,7 @@ int main() { // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP24]], ptr [[TMP0]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP25]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -757,14 +757,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP27]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -772,12 +772,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -788,7 +788,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -804,14 +804,14 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -872,17 +872,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -913,7 +913,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -956,11 +956,11 @@ int main() { // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK9-NEXT: ret void // @@ -984,8 +984,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -994,18 +994,18 @@ int main() { // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1015,7 +1015,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1052,10 +1052,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1078,7 +1078,7 @@ int main() { // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP23]], ptr [[TMP0]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP24]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1095,14 +1095,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1110,12 +1110,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1145,7 +1145,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1162,7 +1162,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1182,17 +1182,17 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1260,17 +1260,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1312,11 +1312,11 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK11-NEXT: ret void // @@ -1341,8 +1341,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1353,19 +1353,19 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1375,7 +1375,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1411,9 +1411,9 @@ int main() { // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1436,7 +1436,7 @@ int main() { // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: store i32 [[TMP24]], ptr [[TMP0]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP25]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1455,14 +1455,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP27]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done15: @@ -1470,12 +1470,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1486,7 +1486,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1502,14 +1502,14 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1570,17 +1570,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -1611,7 +1611,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1654,11 +1654,11 @@ int main() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK11-NEXT: ret void // @@ -1682,8 +1682,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1692,18 +1692,18 @@ int main() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1713,7 +1713,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1749,9 +1749,9 @@ int main() { // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP15]] // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1774,7 +1774,7 @@ int main() { // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: store i32 [[TMP23]], ptr [[TMP0]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1791,14 +1791,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -1806,12 +1806,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1841,7 +1841,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp index 583cad5ae18ce..f9015846bc046 100644 --- a/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp @@ -275,7 +275,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 @@ -294,7 +294,7 @@ int main() { // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK1-NEXT: ret void // @@ -332,12 +332,12 @@ int main() { // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -345,7 +345,7 @@ int main() { // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK1-NEXT: store double [[TMP5]], ptr [[G3]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8 // CHECK1-NEXT: store double [[TMP7]], ptr [[G14]], align 8 // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 @@ -383,7 +383,7 @@ int main() { // CHECK1-NEXT: [[TMP21:%.*]] = load double, ptr [[G3]], align 8 // CHECK1-NEXT: store double [[TMP21]], ptr [[G_CASTED]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[G_CASTED]], align 8 -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP24:%.*]] = load volatile double, ptr [[TMP23]], align 8 // CHECK1-NEXT: store double [[TMP24]], ptr [[G1_CASTED]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[G1_CASTED]], align 8 @@ -475,14 +475,14 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP10]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR_ADDR]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G_ADDR]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR_ADDR]], ptr [[TMP14]], align 8 @@ -516,7 +516,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 @@ -537,16 +537,16 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4 // CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK3-NEXT: ret void // @@ -583,12 +583,12 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -596,7 +596,7 @@ int main() { // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK3-NEXT: store double [[TMP5]], ptr [[G3]], align 8 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 4 // CHECK3-NEXT: store double [[TMP7]], ptr [[G14]], align 8 // CHECK3-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 4 @@ -629,7 +629,7 @@ int main() { // CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, ptr [[TMP19]], align 4 // CHECK3-NEXT: store double [[TMP20]], ptr [[G1_CASTED]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[G1_CASTED]], align 4 @@ -683,7 +683,7 @@ int main() { // CHECK3-NEXT: store i32 [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -723,14 +723,14 @@ int main() { // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP12]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP13]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR_ADDR]], ptr [[TMP16]], align 4 @@ -761,7 +761,7 @@ int main() { // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK8-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -780,17 +780,17 @@ int main() { // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 // CHECK8-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK8-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK8-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK8-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK8-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK8-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 // CHECK8-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -858,17 +858,17 @@ int main() { // CHECK8: omp_offload.cont: // CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK8-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP41]] // @@ -910,11 +910,11 @@ int main() { // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK8-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK8-NEXT: ret void // @@ -939,8 +939,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK8-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -953,13 +953,13 @@ int main() { // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK8-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -968,7 +968,7 @@ int main() { // CHECK8-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK8-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -981,7 +981,7 @@ int main() { // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK8: omp.arraycpy.done6: -// CHECK8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i64 4, i1 false) // CHECK8-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4 @@ -1018,7 +1018,7 @@ int main() { // CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK8-NEXT: store i32 [[TMP21]], ptr [[T_VAR_CASTED]], align 4 // CHECK8-NEXT: [[TMP22:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK8-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: [[TMP24:%.*]] = load i32, ptr [[SVAR9]], align 4 // CHECK8-NEXT: store i32 [[TMP24]], ptr [[SVAR_CASTED]], align 4 // CHECK8-NEXT: [[TMP25:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 @@ -1036,14 +1036,14 @@ int main() { // CHECK8-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK8-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP29]]) -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done12: @@ -1070,8 +1070,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK8-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1083,9 +1083,9 @@ int main() { // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK8-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1098,7 +1098,7 @@ int main() { // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1111,7 +1111,7 @@ int main() { // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] // CHECK8: omp.arraycpy.done5: -// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false) // CHECK8-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1148,10 +1148,10 @@ int main() { // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: @@ -1167,14 +1167,14 @@ int main() { // CHECK8-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done13: @@ -1182,12 +1182,12 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK8-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -1198,7 +1198,7 @@ int main() { // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK8-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1214,14 +1214,14 @@ int main() { // CHECK8-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK8-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) // CHECK8-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK8-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK8-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK8-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK8-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1282,17 +1282,17 @@ int main() { // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: omp_offload.cont: // CHECK8-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP36]] // @@ -1323,7 +1323,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK8-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1366,11 +1366,11 @@ int main() { // CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK8-NEXT: ret void // @@ -1394,8 +1394,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK8-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1405,12 +1405,12 @@ int main() { // CHECK8-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -1419,7 +1419,7 @@ int main() { // CHECK8-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK8-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1432,7 +1432,7 @@ int main() { // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK8: omp.arraycpy.done6: -// CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i64 4, i1 false) // CHECK8-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 8 // CHECK8-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1467,7 +1467,7 @@ int main() { // CHECK8-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK8-NEXT: store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 4 // CHECK8-NEXT: [[TMP20:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK8-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK8-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[VEC4]], i64 [[TMP20]], ptr [[S_ARR5]], ptr [[TMP21]]) // CHECK8-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK8: omp.inner.for.inc: @@ -1482,14 +1482,14 @@ int main() { // CHECK8-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK8-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP25]]) -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: @@ -1515,8 +1515,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK8-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1527,9 +1527,9 @@ int main() { // CHECK8-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK8-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK8-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK8-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK8-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1542,7 +1542,7 @@ int main() { // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1555,7 +1555,7 @@ int main() { // CHECK8-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]] // CHECK8: omp.arraycpy.done5: -// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK8-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR6]], ptr align 4 [[TMP6]], i64 4, i1 false) // CHECK8-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK8-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1592,10 +1592,10 @@ int main() { // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: @@ -1611,14 +1611,14 @@ int main() { // CHECK8-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK8-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK8-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done13: @@ -1626,12 +1626,12 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK8-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -1661,7 +1661,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK8-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1678,7 +1678,7 @@ int main() { // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK10-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1697,17 +1697,17 @@ int main() { // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK10-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK10-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK10-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1775,17 +1775,17 @@ int main() { // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP41]] // @@ -1827,11 +1827,11 @@ int main() { // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK10-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l139.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK10-NEXT: ret void // @@ -1856,8 +1856,8 @@ int main() { // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK10-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1870,13 +1870,13 @@ int main() { // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK10-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 4 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -1885,7 +1885,7 @@ int main() { // CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1898,7 +1898,7 @@ int main() { // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK10: omp.arraycpy.done6: -// CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP8]], i32 4, i1 false) // CHECK10-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 4 // CHECK10-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP4]], align 4 @@ -1933,7 +1933,7 @@ int main() { // CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK10-NEXT: store i32 [[TMP19]], ptr [[T_VAR_CASTED]], align 4 // CHECK10-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 4 +// CHECK10-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: [[TMP22:%.*]] = load i32, ptr [[SVAR9]], align 4 // CHECK10-NEXT: store i32 [[TMP22]], ptr [[SVAR_CASTED]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -1951,14 +1951,14 @@ int main() { // CHECK10-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK10-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done12: @@ -1985,8 +1985,8 @@ int main() { // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK10-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1998,9 +1998,9 @@ int main() { // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK10-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2011,7 +2011,7 @@ int main() { // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2024,7 +2024,7 @@ int main() { // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK10: omp.arraycpy.done4: -// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false) // CHECK10-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2060,9 +2060,9 @@ int main() { // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: @@ -2078,14 +2078,14 @@ int main() { // CHECK10-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -2093,12 +2093,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2109,7 +2109,7 @@ int main() { // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK10-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2125,14 +2125,14 @@ int main() { // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK10-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK10-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK10-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -2193,17 +2193,17 @@ int main() { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP36]] // @@ -2234,7 +2234,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2277,11 +2277,11 @@ int main() { // CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK10-NEXT: ret void // @@ -2305,8 +2305,8 @@ int main() { // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK10-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2316,12 +2316,12 @@ int main() { // CHECK10-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 -// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 @@ -2330,7 +2330,7 @@ int main() { // CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2343,7 +2343,7 @@ int main() { // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] // CHECK10: omp.arraycpy.done6: -// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR7]], ptr align 4 [[TMP7]], i32 4, i1 false) // CHECK10-NEXT: store ptr [[VAR7]], ptr [[_TMP8]], align 4 // CHECK10-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2376,7 +2376,7 @@ int main() { // CHECK10-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK10-NEXT: store i32 [[TMP17]], ptr [[T_VAR_CASTED]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK10-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 4 +// CHECK10-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l48.omp_outlined.omp_outlined, i32 [[TMP15]], i32 [[TMP16]], ptr [[VEC4]], i32 [[TMP18]], ptr [[S_ARR5]], ptr [[TMP19]]) // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK10: omp.inner.for.inc: @@ -2391,14 +2391,14 @@ int main() { // CHECK10-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK10-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -2424,8 +2424,8 @@ int main() { // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK10-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2436,9 +2436,9 @@ int main() { // CHECK10-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK10-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK10-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK10-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK10-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2449,7 +2449,7 @@ int main() { // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2462,7 +2462,7 @@ int main() { // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]] // CHECK10: omp.arraycpy.done4: -// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK10-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VAR5]], ptr align 4 [[TMP6]], i32 4, i1 false) // CHECK10-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK10-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2498,9 +2498,9 @@ int main() { // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: @@ -2516,14 +2516,14 @@ int main() { // CHECK10-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK10-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK10-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -2531,12 +2531,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2566,7 +2566,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp index a3b39f4e4c946..fe2bc59a7a97b 100644 --- a/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp @@ -216,7 +216,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 @@ -235,7 +235,7 @@ int main() { // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK1-NEXT: ret void // @@ -269,18 +269,18 @@ int main() { // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 @@ -309,7 +309,7 @@ int main() { // CHECK1-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], ptr [[G3]], ptr [[TMP17]], ptr [[SVAR6]], ptr [[SFVAR7]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: @@ -373,10 +373,10 @@ int main() { // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -388,7 +388,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -418,14 +418,14 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G3]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP15]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR6]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G3]], ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP18]], ptr [[TMP17]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP19]], align 8 @@ -474,7 +474,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 @@ -495,16 +495,16 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, ptr [[TMP3]], align 4 // CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK3-NEXT: ret void // @@ -538,18 +538,18 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 @@ -576,7 +576,7 @@ int main() { // CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP5]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP5]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i32 [[TMP13]], i32 [[TMP14]], ptr [[G3]], ptr [[TMP15]], ptr [[SVAR6]], ptr [[SFVAR7]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: @@ -640,10 +640,10 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -653,7 +653,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -683,14 +683,14 @@ int main() { // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP15]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR5]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP16]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP18]], ptr [[TMP17]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR5]], ptr [[TMP19]], align 4 @@ -736,7 +736,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -756,17 +756,17 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -834,17 +834,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -886,11 +886,11 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK9-NEXT: ret void // @@ -915,8 +915,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -927,19 +927,19 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -949,7 +949,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -981,7 +981,7 @@ int main() { // CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.omp_outlined.omp_outlined, i64 [[TMP15]], i64 [[TMP17]], ptr [[VEC4]], ptr [[T_VAR3]], ptr [[S_ARR5]], ptr [[TMP18]], ptr [[SVAR8]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: @@ -1003,7 +1003,7 @@ int main() { // CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP25]], ptr [[TMP0]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP26]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1022,14 +1022,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP28]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done13: @@ -1057,8 +1057,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1071,11 +1071,11 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1087,7 +1087,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1097,7 +1097,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1134,10 +1134,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1160,7 +1160,7 @@ int main() { // CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP25]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP26]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1179,14 +1179,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP28]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1194,12 +1194,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1210,7 +1210,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1226,14 +1226,14 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1294,17 +1294,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -1335,7 +1335,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1378,11 +1378,11 @@ int main() { // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK9-NEXT: ret void // @@ -1406,8 +1406,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1416,18 +1416,18 @@ int main() { // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1437,7 +1437,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1469,7 +1469,7 @@ int main() { // CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], ptr [[VEC4]], ptr [[T_VAR3]], ptr [[S_ARR5]], ptr [[TMP17]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: @@ -1491,7 +1491,7 @@ int main() { // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP24]], ptr [[TMP0]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP25]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1508,14 +1508,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP26]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done12: @@ -1542,8 +1542,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1554,10 +1554,10 @@ int main() { // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1569,7 +1569,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1579,7 +1579,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1616,10 +1616,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1642,7 +1642,7 @@ int main() { // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP24]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP25]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1659,14 +1659,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP6]], ptr align 4 [[TMP26]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1674,12 +1674,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1709,7 +1709,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1726,7 +1726,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1746,17 +1746,17 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1824,17 +1824,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1876,11 +1876,11 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK11-NEXT: ret void // @@ -1905,8 +1905,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1917,19 +1917,19 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1939,7 +1939,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1969,7 +1969,7 @@ int main() { // CHECK11: omp.inner.for.body: // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l123.omp_outlined.omp_outlined, i32 [[TMP14]], i32 [[TMP15]], ptr [[VEC4]], ptr [[T_VAR3]], ptr [[S_ARR5]], ptr [[TMP16]], ptr [[SVAR8]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: @@ -1991,7 +1991,7 @@ int main() { // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: store i32 [[TMP23]], ptr [[TMP0]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP24]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2010,14 +2010,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP26]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2045,8 +2045,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2059,11 +2059,11 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2073,7 +2073,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2083,7 +2083,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2119,9 +2119,9 @@ int main() { // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP18]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2144,7 +2144,7 @@ int main() { // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP25]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP26]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2163,14 +2163,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP28]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2178,12 +2178,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2194,7 +2194,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2210,14 +2210,14 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -2278,17 +2278,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -2319,7 +2319,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2362,11 +2362,11 @@ int main() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[T_VAR_ADDR]], ptr [[TMP0]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK11-NEXT: ret void // @@ -2390,8 +2390,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2400,18 +2400,18 @@ int main() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2421,7 +2421,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK11-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2451,7 +2451,7 @@ int main() { // CHECK11: omp.inner.for.body: // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined.omp_outlined, i32 [[TMP13]], i32 [[TMP14]], ptr [[VEC4]], ptr [[T_VAR3]], ptr [[S_ARR5]], ptr [[TMP15]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: @@ -2473,7 +2473,7 @@ int main() { // CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: store i32 [[TMP22]], ptr [[TMP0]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP23]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2490,14 +2490,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP24]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -2524,8 +2524,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2536,10 +2536,10 @@ int main() { // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2549,7 +2549,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2559,7 +2559,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2595,9 +2595,9 @@ int main() { // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2620,7 +2620,7 @@ int main() { // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP24]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP25]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2637,14 +2637,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP6]], ptr align 4 [[TMP26]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2652,12 +2652,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2687,7 +2687,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp index bf979d79fc61b..77e321783222b 100644 --- a/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp @@ -2550,7 +2550,7 @@ int main() { // CHECK1-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK1-NEXT: br label [[EH_RESUME:%.*]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -2608,7 +2608,7 @@ int main() { // CHECK1: invoke.cont7: // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP41]] // CHECK1: eh.resume: @@ -3106,12 +3106,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -3130,7 +3130,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3636,7 +3636,7 @@ int main() { // CHECK1: invoke.cont2: // CHECK1-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -3802,7 +3802,7 @@ int main() { // CHECK5-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK5-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK5-NEXT: br label [[EH_RESUME:%.*]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -3860,7 +3860,7 @@ int main() { // CHECK5: invoke.cont7: // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK5-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP41]] // CHECK5: eh.resume: @@ -4358,12 +4358,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK5-NEXT: ret void // // @@ -4879,7 +4879,7 @@ int main() { // CHECK5: invoke.cont2: // CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR3]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -4985,7 +4985,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -5054,7 +5054,7 @@ int main() { // CHECK9-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK9-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK9-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK9-NEXT: br label [[EH_RESUME:%.*]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -5112,7 +5112,7 @@ int main() { // CHECK9: invoke.cont7: // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK9-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9: eh.resume: @@ -5610,12 +5610,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK9-NEXT: ret void // // @@ -5634,7 +5634,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -6140,7 +6140,7 @@ int main() { // CHECK9: invoke.cont2: // CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR3]] // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -6306,7 +6306,7 @@ int main() { // CHECK13-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK13-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK13-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK13-NEXT: br label [[EH_RESUME:%.*]] // CHECK13: omp_offload.cont: // CHECK13-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -6364,7 +6364,7 @@ int main() { // CHECK13: invoke.cont7: // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK13-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP41]] // CHECK13: eh.resume: @@ -6862,12 +6862,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -7383,7 +7383,7 @@ int main() { // CHECK13: invoke.cont2: // CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 // CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]) -// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -7489,7 +7489,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp index b4bc232f3a9b4..81455c273c5e0 100644 --- a/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp @@ -288,14 +288,14 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP10]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[TMP14]], align 8 @@ -466,14 +466,14 @@ int main() { // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G]], align 8 -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP10]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP11]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[TMP14]], align 4 @@ -504,7 +504,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -554,17 +554,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP16]] // @@ -613,8 +613,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -625,7 +625,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -680,14 +680,14 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -710,8 +710,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -730,7 +730,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -776,10 +776,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -795,14 +795,14 @@ int main() { // CHECK9-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done9: @@ -810,12 +810,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -826,7 +826,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -873,17 +873,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP16]] // @@ -914,7 +914,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -966,8 +966,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -977,7 +977,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1032,14 +1032,14 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -1062,8 +1062,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1081,7 +1081,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1127,10 +1127,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1146,14 +1146,14 @@ int main() { // CHECK9-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done9: @@ -1161,12 +1161,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1196,7 +1196,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1213,7 +1213,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1263,17 +1263,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP16]] // @@ -1322,8 +1322,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1334,7 +1334,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1387,14 +1387,14 @@ int main() { // CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: @@ -1417,8 +1417,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1435,7 +1435,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1480,9 +1480,9 @@ int main() { // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1498,14 +1498,14 @@ int main() { // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1513,12 +1513,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1529,7 +1529,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1576,17 +1576,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP16]] // @@ -1617,7 +1617,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1669,8 +1669,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1680,7 +1680,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1733,14 +1733,14 @@ int main() { // CHECK11-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: @@ -1763,8 +1763,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1780,7 +1780,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1825,9 +1825,9 @@ int main() { // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1843,14 +1843,14 @@ int main() { // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1858,12 +1858,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1893,7 +1893,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp index 04f9a3713a44f..7833262bcec20 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -824,7 +824,7 @@ int main() { // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK8-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -921,17 +921,17 @@ int main() { // CHECK8: omp_offload.cont: // CHECK8-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK8-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP41]] // @@ -1002,8 +1002,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK8-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1031,7 +1031,7 @@ int main() { // CHECK8-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK8-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1106,14 +1106,14 @@ int main() { // CHECK8-NEXT: store i32 2, ptr [[I]], align 4 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK8: .omp.final.done: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP32]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done12: @@ -1140,8 +1140,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK8-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1168,7 +1168,7 @@ int main() { // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1221,7 +1221,7 @@ int main() { // CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP13]] // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: @@ -1244,14 +1244,14 @@ int main() { // CHECK8-NEXT: store i32 2, ptr [[I]], align 4 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK8: .omp.final.done: -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done13: @@ -1259,12 +1259,12 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK8-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -1275,7 +1275,7 @@ int main() { // CHECK8-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK8-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK8-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK8-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1359,17 +1359,17 @@ int main() { // CHECK8-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK8: omp_offload.cont: // CHECK8-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK8-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done2: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK8-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK8-NEXT: ret i32 [[TMP36]] // @@ -1400,7 +1400,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK8-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1471,8 +1471,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK8-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK8-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1496,7 +1496,7 @@ int main() { // CHECK8-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK8-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1566,14 +1566,14 @@ int main() { // CHECK8-NEXT: store i32 2, ptr [[I]], align 4 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK8: .omp.final.done: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK8-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done11: @@ -1599,8 +1599,8 @@ int main() { // CHECK8-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK8-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK8-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK8-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK8-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK8-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1626,7 +1626,7 @@ int main() { // CHECK8-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK8-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK8-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK8-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1679,7 +1679,7 @@ int main() { // CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP21]] // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: @@ -1702,14 +1702,14 @@ int main() { // CHECK8-NEXT: store i32 2, ptr [[I]], align 4 // CHECK8-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK8: .omp.final.done: -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK8-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK8-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK8-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK8: arraydestroy.body: // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK8-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK8-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK8-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK8: arraydestroy.done13: @@ -1717,12 +1717,12 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK8-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK8-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK8-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK8-NEXT: ret void // // @@ -1752,7 +1752,7 @@ int main() { // // // CHECK8-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK8-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK8-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK8-NEXT: entry: // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK8-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1769,7 +1769,7 @@ int main() { // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK10-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1866,17 +1866,17 @@ int main() { // CHECK10: omp_offload.cont: // CHECK10-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK10-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP41]] // @@ -1947,8 +1947,8 @@ int main() { // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK10-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1976,7 +1976,7 @@ int main() { // CHECK10-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK10-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2049,14 +2049,14 @@ int main() { // CHECK10-NEXT: store i32 2, ptr [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done12: @@ -2083,8 +2083,8 @@ int main() { // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK10-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2109,7 +2109,7 @@ int main() { // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2160,7 +2160,7 @@ int main() { // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP14]] // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: @@ -2183,14 +2183,14 @@ int main() { // CHECK10-NEXT: store i32 2, ptr [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -2198,12 +2198,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2214,7 +2214,7 @@ int main() { // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK10-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2298,17 +2298,17 @@ int main() { // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK10: omp_offload.cont: // CHECK10-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done2: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK10-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK10-NEXT: ret i32 [[TMP36]] // @@ -2339,7 +2339,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2410,8 +2410,8 @@ int main() { // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK10-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2435,7 +2435,7 @@ int main() { // CHECK10-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK10-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2503,14 +2503,14 @@ int main() { // CHECK10-NEXT: store i32 2, ptr [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -2536,8 +2536,8 @@ int main() { // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK10-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK10-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK10-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK10-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK10-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2561,7 +2561,7 @@ int main() { // CHECK10-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK10-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2612,7 +2612,7 @@ int main() { // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP22]] // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP22]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: @@ -2635,14 +2635,14 @@ int main() { // CHECK10-NEXT: store i32 2, ptr [[I]], align 4 // CHECK10-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK10: .omp.final.done: -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK10-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK10: arraydestroy.body: // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK10: arraydestroy.done11: @@ -2650,12 +2650,12 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK10-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK10-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK10-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK10-NEXT: ret void // // @@ -2685,7 +2685,7 @@ int main() { // // // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK10-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK10-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK10-NEXT: entry: // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK10-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2702,7 +2702,7 @@ int main() { // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK12-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2751,7 +2751,7 @@ int main() { // CHECK12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]] // CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK12-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK12-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: @@ -2765,17 +2765,17 @@ int main() { // CHECK12-NEXT: store i32 2, ptr [[I]], align 4 // CHECK12-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK12-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: -// CHECK12-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK12-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK12-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP14]] // @@ -2810,7 +2810,7 @@ int main() { // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK12-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2857,7 +2857,7 @@ int main() { // CHECK12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]] // CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK12-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK12-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: @@ -2870,28 +2870,28 @@ int main() { // CHECK12: omp.inner.for.end: // CHECK12-NEXT: store i32 2, ptr [[I]], align 4 // CHECK12-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK12: arraydestroy.body: // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK12: arraydestroy.done7: -// CHECK12-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK12-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK12-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK12-NEXT: ret i32 [[TMP14]] // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK12-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK12-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK12-NEXT: ret void // // @@ -2907,7 +2907,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK12-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2953,12 +2953,12 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK12-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK12-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK12-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK12-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK12-NEXT: ret void // // @@ -2988,7 +2988,7 @@ int main() { // // // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK12-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK12-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK12-NEXT: entry: // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK12-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3005,7 +3005,7 @@ int main() { // CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK14-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK14-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -3052,7 +3052,7 @@ int main() { // CHECK14-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK14-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]] // CHECK14-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK14-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: @@ -3066,17 +3066,17 @@ int main() { // CHECK14-NEXT: store i32 2, ptr [[I]], align 4 // CHECK14-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK14-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done6: -// CHECK14-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK14-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK14-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP14]] // @@ -3111,7 +3111,7 @@ int main() { // CHECK14-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK14-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK14-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK14-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK14-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK14-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK14-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -3156,7 +3156,7 @@ int main() { // CHECK14-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK14-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]] // CHECK14-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK14-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: @@ -3169,28 +3169,28 @@ int main() { // CHECK14: omp.inner.for.end: // CHECK14-NEXT: store i32 2, ptr [[I]], align 4 // CHECK14-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK14-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK14-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK14-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK14: arraydestroy.body: // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK14-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK14-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK14-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK14: arraydestroy.done6: -// CHECK14-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK14-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK14-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK14-NEXT: ret i32 [[TMP14]] // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK14-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK14-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK14-NEXT: ret void // // @@ -3206,7 +3206,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK14-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3252,12 +3252,12 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK14-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK14-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK14-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK14-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK14-NEXT: ret void // // @@ -3287,7 +3287,7 @@ int main() { // // // CHECK14-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK14-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK14-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK14-NEXT: entry: // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK14-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp index f9f979b5785c3..a993071844609 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -803,7 +803,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -901,17 +901,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -982,8 +982,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1006,7 +1006,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1077,7 +1077,7 @@ int main() { // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP27]], ptr [[TMP0]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP28]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1096,14 +1096,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP30]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done13: @@ -1131,8 +1131,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1161,7 +1161,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1211,7 +1211,7 @@ int main() { // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1241,7 +1241,7 @@ int main() { // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP27]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP28]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1260,14 +1260,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP30]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1275,12 +1275,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1291,7 +1291,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1375,17 +1375,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -1416,7 +1416,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1487,8 +1487,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1508,7 +1508,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1579,7 +1579,7 @@ int main() { // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP26]], ptr [[TMP0]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP27]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1596,14 +1596,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP28]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done12: @@ -1630,8 +1630,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1657,7 +1657,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1707,7 +1707,7 @@ int main() { // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1737,7 +1737,7 @@ int main() { // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP26]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP27]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1754,14 +1754,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP6]], ptr align 4 [[TMP28]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1769,12 +1769,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1804,7 +1804,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1821,7 +1821,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1919,17 +1919,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -2000,8 +2000,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2024,7 +2024,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2093,7 +2093,7 @@ int main() { // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: store i32 [[TMP25]], ptr [[TMP0]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP26]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2112,14 +2112,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP28]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2147,8 +2147,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2175,7 +2175,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2223,7 +2223,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2253,7 +2253,7 @@ int main() { // CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP27]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP28]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2272,14 +2272,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP30]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2287,12 +2287,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2303,7 +2303,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2387,17 +2387,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -2428,7 +2428,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2499,8 +2499,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2520,7 +2520,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2589,7 +2589,7 @@ int main() { // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: store i32 [[TMP24]], ptr [[TMP0]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP25]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2606,14 +2606,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP26]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -2640,8 +2640,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2665,7 +2665,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2713,7 +2713,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2743,7 +2743,7 @@ int main() { // CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP26]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP27]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2760,14 +2760,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP6]], ptr align 4 [[TMP28]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2775,12 +2775,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2810,7 +2810,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2827,7 +2827,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2839,7 +2839,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2864,7 +2864,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2898,7 +2898,7 @@ int main() { // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] +// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2913,7 +2913,7 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP15]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2930,30 +2930,30 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN17]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] // CHECK13: arraydestroy.body18: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] // CHECK13: arraydestroy.done22: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP20]] // @@ -2982,12 +2982,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2998,7 +2998,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -3010,7 +3010,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -3031,7 +3031,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -3065,7 +3065,7 @@ int main() { // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] +// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3080,7 +3080,7 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP15]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3095,29 +3095,29 @@ int main() { // CHECK13: omp.arraycpy.done13: // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP8]], align 8 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN16]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] // CHECK13: arraydestroy.body17: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13: arraydestroy.done21: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP19]] // @@ -3134,7 +3134,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3180,12 +3180,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -3215,7 +3215,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3232,7 +3232,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -3244,7 +3244,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -3269,7 +3269,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3301,7 +3301,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3316,7 +3316,7 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP15]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3333,30 +3333,30 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done14: // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN16]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] // CHECK15: arraydestroy.body17: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK15: arraydestroy.done21: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP20]] // @@ -3385,12 +3385,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -3401,7 +3401,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -3413,7 +3413,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -3434,7 +3434,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3466,7 +3466,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3481,7 +3481,7 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP15]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3496,29 +3496,29 @@ int main() { // CHECK15: omp.arraycpy.done12: // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP8]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done14: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN15]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] // CHECK15: arraydestroy.body16: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK15: arraydestroy.done20: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP19]] // @@ -3535,7 +3535,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3581,12 +3581,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -3616,7 +3616,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp index 0d4b9b245743d..d6a3f1b8c4e3e 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp @@ -154,7 +154,7 @@ int main() { // CHECK1-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK1-NEXT: br label [[EH_RESUME:%.*]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -212,7 +212,7 @@ int main() { // CHECK1: invoke.cont7: // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP41]] // CHECK1: eh.resume: @@ -292,24 +292,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -370,26 +370,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP19]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -406,7 +406,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: unreachable // // @@ -442,7 +442,7 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META24:![0-9]+]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -465,26 +465,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP0]], align 1, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP0]], align 1, !llvm.access.group [[ACC_GRP25]] // CHECK1-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group [[ACC_GRP18]] -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group [[ACC_GRP25]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -545,26 +545,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP28]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -581,7 +581,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP28]] // CHECK1-NEXT: unreachable // // @@ -738,12 +738,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK1-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -762,7 +762,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK1-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -813,24 +813,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP24]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP31]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -891,26 +891,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP34]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -927,7 +927,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP34]] // CHECK1-NEXT: unreachable // // @@ -974,24 +974,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP30]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP37]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP37]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1052,26 +1052,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP40]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1088,7 +1088,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP40]] // CHECK1-NEXT: unreachable // // @@ -1135,24 +1135,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP36]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP43]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP43]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1213,26 +1213,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP46]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1249,7 +1249,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP46]] // CHECK1-NEXT: unreachable // // @@ -1297,32 +1297,32 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: // CHECK1-NEXT: invoke void @_ZN1SC1El(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP49]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP49]] // CHECK1: invoke.cont2: // CHECK1-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3]], !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group [[ACC_GRP49]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR3]], !llvm.access.group [[ACC_GRP49]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group [[ACC_GRP49]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1339,7 +1339,7 @@ int main() { // CHECK1-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP49]] // CHECK1-NEXT: unreachable // // @@ -1389,26 +1389,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP52]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1425,7 +1425,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP52]] // CHECK1-NEXT: unreachable // // @@ -1486,7 +1486,7 @@ int main() { // CHECK3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR5:[0-9]+]] // CHECK3-NEXT: br label [[EH_RESUME:%.*]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 @@ -1529,7 +1529,7 @@ int main() { // CHECK3: invoke.cont21: // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK3-NEXT: store i32 [[ADD23]], ptr [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR5]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP14]] // CHECK3: eh.resume: @@ -1736,12 +1736,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK3-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR5]] // CHECK3-NEXT: ret void // // @@ -1760,7 +1760,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK3-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1829,7 +1829,7 @@ int main() { // CHECK5-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK5-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK5-NEXT: br label [[EH_RESUME:%.*]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -1887,7 +1887,7 @@ int main() { // CHECK5: invoke.cont7: // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK5-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP41]] // CHECK5: eh.resume: @@ -1967,24 +1967,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP9]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP15]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2045,26 +2045,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP19]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2081,7 +2081,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: unreachable // // @@ -2117,7 +2117,7 @@ int main() { // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META24:![0-9]+]] // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -2140,26 +2140,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP0]], align 1, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP0]], align 1, !llvm.access.group [[ACC_GRP25]] // CHECK5-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group [[ACC_GRP18]] -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group [[ACC_GRP25]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK5-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group [[ACC_GRP25]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2220,26 +2220,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP28]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2256,7 +2256,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP28]] // CHECK5-NEXT: unreachable // // @@ -2413,12 +2413,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK5-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK5-NEXT: ret void // // @@ -2479,24 +2479,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP24]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP31]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP31]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2557,26 +2557,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP34]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2593,7 +2593,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP34]] // CHECK5-NEXT: unreachable // // @@ -2640,24 +2640,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP30]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP37]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP37]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2718,26 +2718,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP40]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2754,7 +2754,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP40]] // CHECK5-NEXT: unreachable // // @@ -2801,24 +2801,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP36]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP43]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2879,26 +2879,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP46]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2915,7 +2915,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP46]] // CHECK5-NEXT: unreachable // // @@ -2963,32 +2963,32 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: // CHECK5-NEXT: invoke void @_ZN1SC1El(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP49]] // CHECK5: invoke.cont: // CHECK5-NEXT: [[CALL:%.*]] = invoke signext i8 @_ZN1ScvcEv(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP49]] // CHECK5: invoke.cont2: // CHECK5-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group [[ACC_GRP42]] -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3]], !llvm.access.group [[ACC_GRP42]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group [[ACC_GRP49]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR3]], !llvm.access.group [[ACC_GRP49]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK5-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK5-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group [[ACC_GRP49]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3005,7 +3005,7 @@ int main() { // CHECK5-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP49]] // CHECK5-NEXT: unreachable // // @@ -3055,26 +3055,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP52]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3091,12 +3091,12 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP52]] // CHECK5-NEXT: unreachable // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { +// CHECK5-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3165,7 +3165,7 @@ int main() { // CHECK9-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK9-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK9-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK9-NEXT: br label [[EH_RESUME:%.*]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -3223,7 +3223,7 @@ int main() { // CHECK9: invoke.cont7: // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK9-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // CHECK9: eh.resume: @@ -3303,24 +3303,24 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP9]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP9]] +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3381,26 +3381,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP19]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3417,7 +3417,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK9-NEXT: catch ptr null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP13]] +// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP19]] // CHECK9-NEXT: unreachable // // @@ -3453,7 +3453,7 @@ int main() { // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META24:![0-9]+]] // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -3476,26 +3476,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP0]], align 1, !llvm.access.group [[ACC_GRP18]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP0]], align 1, !llvm.access.group [[ACC_GRP25]] // CHECK9-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group [[ACC_GRP18]] -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group [[ACC_GRP25]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group [[ACC_GRP18]] +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group [[ACC_GRP25]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3556,26 +3556,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP28]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3592,7 +3592,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK9-NEXT: catch ptr null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP21]] +// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP28]] // CHECK9-NEXT: unreachable // // @@ -3749,12 +3749,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { +// CHECK9-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK9-NEXT: ret void // // @@ -3773,7 +3773,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK9-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { +// CHECK9-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3824,24 +3824,24 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP24]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP31]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP24]] +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP31]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3902,26 +3902,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP34]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -3938,7 +3938,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK9-NEXT: catch ptr null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] +// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP34]] // CHECK9-NEXT: unreachable // // @@ -3985,24 +3985,24 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP30]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP37]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP37]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4063,26 +4063,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP40]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4099,7 +4099,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK9-NEXT: catch ptr null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] +// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP40]] // CHECK9-NEXT: unreachable // // @@ -4146,24 +4146,24 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43:![0-9]+]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP36]] -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP43]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP43]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4224,26 +4224,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46:![0-9]+]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP46]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4260,7 +4260,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK9-NEXT: catch ptr null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] +// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP46]] // CHECK9-NEXT: unreachable // // @@ -4308,32 +4308,32 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]] +// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: // CHECK9-NEXT: invoke void @_ZN1SC1El(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP42]] +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP49]] // CHECK9: invoke.cont: // CHECK9-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK9-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP42]] +// CHECK9-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP49]] // CHECK9: invoke.cont2: // CHECK9-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group [[ACC_GRP42]] -// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3]], !llvm.access.group [[ACC_GRP42]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK9-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group [[ACC_GRP49]] +// CHECK9-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR3]], !llvm.access.group [[ACC_GRP49]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group [[ACC_GRP42]] +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group [[ACC_GRP49]] // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4350,7 +4350,7 @@ int main() { // CHECK9-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 } // CHECK9-NEXT: catch ptr null // CHECK9-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP42]] +// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP49]] // CHECK9-NEXT: unreachable // // @@ -4400,26 +4400,26 @@ int main() { // CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK9: omp.inner.for.cond: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52:![0-9]+]] +// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK9-NEXT: invoke void @_Z3foov() -// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] +// CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP52]] // CHECK9: invoke.cont: // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK9-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: @@ -4436,7 +4436,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK9-NEXT: catch ptr null // CHECK9-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] +// CHECK9-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP52]] // CHECK9-NEXT: unreachable // // @@ -4497,7 +4497,7 @@ int main() { // CHECK11-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 // CHECK11-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // CHECK11-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK11-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5:[0-9]+]] +// CHECK11-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR5:[0-9]+]] // CHECK11-NEXT: br label [[EH_RESUME:%.*]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: store i32 100, ptr [[I]], align 4 @@ -4540,7 +4540,7 @@ int main() { // CHECK11: invoke.cont21: // CHECK11-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK11-NEXT: store i32 [[ADD23]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR5]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP14]] // CHECK11: eh.resume: @@ -4747,12 +4747,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat { +// CHECK11-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] +// CHECK11-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR5]] // CHECK11-NEXT: ret void // // @@ -4771,7 +4771,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK11-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat { +// CHECK11-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4840,7 +4840,7 @@ int main() { // CHECK13-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK13-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK13-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK13-NEXT: br label [[EH_RESUME:%.*]] // CHECK13: omp_offload.cont: // CHECK13-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -4898,7 +4898,7 @@ int main() { // CHECK13: invoke.cont7: // CHECK13-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK13-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP41]] // CHECK13: eh.resume: @@ -4978,24 +4978,24 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP9]] -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP15]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5056,26 +5056,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP19]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5092,7 +5092,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK13-NEXT: catch ptr null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP13]] +// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP19]] // CHECK13-NEXT: unreachable // // @@ -5128,7 +5128,7 @@ int main() { // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK13-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK13-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META24:![0-9]+]] // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK13-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -5151,26 +5151,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP0]], align 1, !llvm.access.group [[ACC_GRP18]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP0]], align 1, !llvm.access.group [[ACC_GRP25]] // CHECK13-NEXT: [[TMP9:%.*]] = sext i8 [[TMP8]] to i32 -// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group [[ACC_GRP18]] -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP2]], i32 [[TMP9]]), !llvm.access.group [[ACC_GRP25]] +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK13-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group [[ACC_GRP18]] +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]]), !llvm.access.group [[ACC_GRP25]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5231,26 +5231,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP28]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5267,7 +5267,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK13-NEXT: catch ptr null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP21]] +// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP28]] // CHECK13-NEXT: unreachable // // @@ -5424,12 +5424,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { +// CHECK13-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -5490,24 +5490,24 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]] +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP24]] -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP31]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP24]] +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP31]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5568,26 +5568,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP34]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5604,7 +5604,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK13-NEXT: catch ptr null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] +// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP34]] // CHECK13-NEXT: unreachable // // @@ -5651,24 +5651,24 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]] +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP30]] -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP37]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP37]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5729,26 +5729,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP40]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5765,7 +5765,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK13-NEXT: catch ptr null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] +// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP40]] // CHECK13-NEXT: unreachable // // @@ -5812,24 +5812,24 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43:![0-9]+]] +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP36]] -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP43]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l52.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP43]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP43]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP43]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP44:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5890,26 +5890,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46:![0-9]+]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP46]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP46]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP47:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -5926,7 +5926,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK13-NEXT: catch ptr null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] +// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP46]] // CHECK13-NEXT: unreachable // // @@ -5974,32 +5974,32 @@ int main() { // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49:![0-9]+]] +// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK13-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: // CHECK13-NEXT: invoke void @_ZN1SC1El(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]], i64 23) -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP42]] +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP49]] // CHECK13: invoke.cont: // CHECK13-NEXT: [[CALL:%.*]] = invoke i8 @_ZN1ScvcEv(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK13-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP42]] +// CHECK13-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]], !llvm.access.group [[ACC_GRP49]] // CHECK13: invoke.cont2: // CHECK13-NEXT: [[TMP7:%.*]] = sext i8 [[CALL]] to i32 -// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group [[ACC_GRP42]] -// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3]], !llvm.access.group [[ACC_GRP42]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK13-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP7]]), !llvm.access.group [[ACC_GRP49]] +// CHECK13-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR3]], !llvm.access.group [[ACC_GRP49]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group [[ACC_GRP42]] +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l57.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]]), !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP49]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP50:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -6016,7 +6016,7 @@ int main() { // CHECK13-NEXT: [[TMP16:%.*]] = landingpad { ptr, i32 } // CHECK13-NEXT: catch ptr null // CHECK13-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP16]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP42]] +// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP17]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: unreachable // // @@ -6066,26 +6066,26 @@ int main() { // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52:![0-9]+]] +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK13-NEXT: invoke void @_Z3foov() -// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] +// CHECK13-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP52]] // CHECK13: invoke.cont: // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] // CHECK13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK13-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP52]] +// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP53:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: @@ -6102,12 +6102,12 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK13-NEXT: catch ptr null // CHECK13-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] +// CHECK13-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP52]] // CHECK13-NEXT: unreachable // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK13-SAME: (ptr nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { +// CHECK13-SAME: (ptr nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR6]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp index 59c00caa5587e..770ff125c8aa8 100644 --- a/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp @@ -558,7 +558,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -608,17 +608,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP16]] // @@ -667,8 +667,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -679,7 +679,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -741,14 +741,14 @@ int main() { // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -771,8 +771,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -791,7 +791,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -840,7 +840,7 @@ int main() { // CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META12:![0-9]+]], !align [[META13:![0-9]+]], !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -863,14 +863,14 @@ int main() { // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done9: @@ -878,12 +878,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -894,7 +894,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -941,17 +941,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP16]] // @@ -982,7 +982,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1034,8 +1034,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1045,7 +1045,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1107,14 +1107,14 @@ int main() { // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -1137,8 +1137,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1156,7 +1156,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1205,7 +1205,7 @@ int main() { // CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META12]], !align [[META13]], !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1228,14 +1228,14 @@ int main() { // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done9: @@ -1243,12 +1243,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1278,7 +1278,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1295,7 +1295,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1345,17 +1345,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP16]] // @@ -1404,8 +1404,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1416,7 +1416,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1476,14 +1476,14 @@ int main() { // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: @@ -1506,8 +1506,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1524,7 +1524,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1571,7 +1571,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META13:![0-9]+]], !align [[META14:![0-9]+]], !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1594,14 +1594,14 @@ int main() { // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1609,12 +1609,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1625,7 +1625,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1672,17 +1672,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP16]] // @@ -1713,7 +1713,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1765,8 +1765,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1776,7 +1776,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1836,14 +1836,14 @@ int main() { // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: @@ -1866,8 +1866,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1883,7 +1883,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1930,7 +1930,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META13]], !align [[META14]], !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1953,14 +1953,14 @@ int main() { // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1968,12 +1968,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2003,7 +2003,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2020,7 +2020,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2029,7 +2029,7 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2048,7 +2048,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2081,7 +2081,7 @@ int main() { // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]], !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2093,30 +2093,30 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP11]] // @@ -2145,12 +2145,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2161,7 +2161,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2170,7 +2170,7 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2186,7 +2186,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2219,7 +2219,7 @@ int main() { // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2231,29 +2231,29 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP11]] // @@ -2270,7 +2270,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2316,12 +2316,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2351,7 +2351,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2368,7 +2368,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2377,7 +2377,7 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2396,7 +2396,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2427,7 +2427,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]], !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2439,30 +2439,30 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP11]] // @@ -2491,12 +2491,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2507,7 +2507,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2516,7 +2516,7 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2532,7 +2532,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2563,7 +2563,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META4]], !align [[META5]], !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2575,29 +2575,29 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP11]] // @@ -2614,7 +2614,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2660,12 +2660,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2695,7 +2695,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_private_codegen.cpp b/clang/test/OpenMP/distribute_private_codegen.cpp index a65c51ebdb607..5a388c7ae2fbb 100644 --- a/clang/test/OpenMP/distribute_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_private_codegen.cpp @@ -189,14 +189,14 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP8]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[TMP12]], align 8 @@ -293,14 +293,14 @@ int main() { // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G]], align 8 -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP8]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP9]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[TMP12]], align 4 @@ -331,7 +331,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -417,17 +417,17 @@ int main() { // CHECK9: omp_offload.cont5: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done6: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP31]] // @@ -476,8 +476,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -488,7 +488,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -534,10 +534,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -553,14 +553,14 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -568,12 +568,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -652,7 +652,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -699,17 +699,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP16]] // @@ -740,7 +740,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -792,8 +792,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -803,7 +803,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -849,10 +849,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META9]], !align [[META10]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -868,14 +868,14 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -883,12 +883,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -918,7 +918,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -935,7 +935,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1021,17 +1021,17 @@ int main() { // CHECK11: omp_offload.cont5: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done6: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP31]] // @@ -1080,8 +1080,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1092,7 +1092,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1137,9 +1137,9 @@ int main() { // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1155,14 +1155,14 @@ int main() { // CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1170,12 +1170,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1254,7 +1254,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1301,17 +1301,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP16]] // @@ -1342,7 +1342,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1394,8 +1394,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1405,7 +1405,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1450,9 +1450,9 @@ int main() { // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10]], !align [[META11]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1468,14 +1468,14 @@ int main() { // CHECK11-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1483,12 +1483,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1518,7 +1518,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp index 96b06eb596dd6..e77597d19aeaf 100644 --- a/clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp @@ -531,7 +531,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -628,17 +628,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -709,8 +709,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -736,7 +736,7 @@ int main() { // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -791,7 +791,7 @@ int main() { // CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -814,14 +814,14 @@ int main() { // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -829,12 +829,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -845,7 +845,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -929,17 +929,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -970,7 +970,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1041,8 +1041,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1065,7 +1065,7 @@ int main() { // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1118,7 +1118,7 @@ int main() { // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1141,14 +1141,14 @@ int main() { // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1156,12 +1156,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1191,7 +1191,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1208,7 +1208,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1305,17 +1305,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1386,8 +1386,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1413,7 +1413,7 @@ int main() { // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK11-NEXT: store i32 [[TMP6]], ptr [[T_VAR3]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1466,7 +1466,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP21]] +// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 [[TMP21]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1489,14 +1489,14 @@ int main() { // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -1504,12 +1504,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1520,7 +1520,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1604,17 +1604,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -1645,7 +1645,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1716,8 +1716,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1740,7 +1740,7 @@ int main() { // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1791,7 +1791,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1814,14 +1814,14 @@ int main() { // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -1829,12 +1829,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1864,7 +1864,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1881,7 +1881,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1930,7 +1930,7 @@ int main() { // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1944,17 +1944,17 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done7: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP14]] // @@ -1989,7 +1989,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2036,7 +2036,7 @@ int main() { // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2049,28 +2049,28 @@ int main() { // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done7: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP14]] // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2086,7 +2086,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2132,12 +2132,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2167,7 +2167,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2184,7 +2184,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2231,7 +2231,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2245,17 +2245,17 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP14]] // @@ -2290,7 +2290,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2335,7 +2335,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2348,28 +2348,28 @@ int main() { // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP14]] // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2385,7 +2385,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2431,12 +2431,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2466,7 +2466,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp index 0aabe1ad41cf1..2fc07f5504a34 100644 --- a/clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp @@ -517,7 +517,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -615,17 +615,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -696,8 +696,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -720,7 +720,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -770,7 +770,7 @@ int main() { // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -800,7 +800,7 @@ int main() { // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP26]], ptr [[TMP0]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP27]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -819,14 +819,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP29]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -834,12 +834,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -850,7 +850,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -934,17 +934,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -975,7 +975,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1046,8 +1046,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1067,7 +1067,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1117,7 +1117,7 @@ int main() { // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1147,7 +1147,7 @@ int main() { // CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP25]], ptr [[TMP0]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP26]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1164,14 +1164,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1179,12 +1179,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1214,7 +1214,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1231,7 +1231,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1329,17 +1329,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1410,8 +1410,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1434,7 +1434,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1482,7 +1482,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1512,7 +1512,7 @@ int main() { // CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: store i32 [[TMP26]], ptr [[TMP0]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP27]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1531,14 +1531,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP29]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done15: @@ -1546,12 +1546,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1562,7 +1562,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1646,17 +1646,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -1687,7 +1687,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1758,8 +1758,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1779,7 +1779,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1827,7 +1827,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1857,7 +1857,7 @@ int main() { // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: store i32 [[TMP25]], ptr [[TMP0]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP1]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP26]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1874,14 +1874,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -1889,12 +1889,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1924,7 +1924,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1941,7 +1941,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1953,7 +1953,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -1978,7 +1978,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2012,7 +2012,7 @@ int main() { // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] +// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2027,7 +2027,7 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP15]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2044,30 +2044,30 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN17:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN17]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY18:%.*]] // CHECK13: arraydestroy.body18: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST19:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT20:%.*]], [[ARRAYDESTROY_BODY18]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT20]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST19]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT20]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE21:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT20]], [[ARRAY_BEGIN17]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY18]] // CHECK13: arraydestroy.done22: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP20]] // @@ -2096,12 +2096,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2112,7 +2112,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2124,7 +2124,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR6:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2145,7 +2145,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2179,7 +2179,7 @@ int main() { // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] +// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2194,7 +2194,7 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP15]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2209,29 +2209,29 @@ int main() { // CHECK13: omp.arraycpy.done13: // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP8]], align 8 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done15: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN16]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] // CHECK13: arraydestroy.body17: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE15]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13: arraydestroy.done21: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP19]] // @@ -2248,7 +2248,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2294,12 +2294,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2329,7 +2329,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2346,7 +2346,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2358,7 +2358,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2383,7 +2383,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2415,7 +2415,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2430,7 +2430,7 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP15]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2447,30 +2447,30 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done14: // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN16]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] // CHECK15: arraydestroy.body17: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK15: arraydestroy.done21: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP20]] // @@ -2499,12 +2499,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2515,7 +2515,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2527,7 +2527,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR4:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC5:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR6:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP8:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2548,7 +2548,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2580,7 +2580,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2595,7 +2595,7 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR4]], align 4 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC5]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP15]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2610,29 +2610,29 @@ int main() { // CHECK15: omp.arraycpy.done12: // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP8]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR6]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done14: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN15]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] // CHECK15: arraydestroy.body16: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK15: arraydestroy.done20: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP19]] // @@ -2649,7 +2649,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2695,12 +2695,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2730,7 +2730,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/distribute_simd_private_codegen.cpp b/clang/test/OpenMP/distribute_simd_private_codegen.cpp index a2d5e0dc711e6..b7029a2633d19 100644 --- a/clang/test/OpenMP/distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/distribute_simd_private_codegen.cpp @@ -372,7 +372,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -473,17 +473,17 @@ int main() { // CHECK9: omp_offload.cont5: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP37]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done6: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP38]] // @@ -532,8 +532,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -544,7 +544,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -593,7 +593,7 @@ int main() { // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]], !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -616,14 +616,14 @@ int main() { // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -631,12 +631,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -726,7 +726,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -773,17 +773,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP16]] // @@ -814,7 +814,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -866,8 +866,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -877,7 +877,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -926,7 +926,7 @@ int main() { // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META10]], !align [[META11]], !llvm.access.group [[ACC_GRP20]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP20]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -949,14 +949,14 @@ int main() { // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK9: .omp.final.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -964,12 +964,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -999,7 +999,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1016,7 +1016,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1117,17 +1117,17 @@ int main() { // CHECK11: omp_offload.cont5: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP37]], [[OMP_OFFLOAD_CONT5]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done6: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP38:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP38]] // @@ -1176,8 +1176,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1188,7 +1188,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1235,7 +1235,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META11:![0-9]+]], !align [[META12:![0-9]+]], !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1258,14 +1258,14 @@ int main() { // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1273,12 +1273,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1368,7 +1368,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1415,17 +1415,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP16]] // @@ -1456,7 +1456,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1508,8 +1508,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1519,7 +1519,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1566,7 +1566,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META11]], !align [[META12]], !llvm.access.group [[ACC_GRP21]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1589,14 +1589,14 @@ int main() { // CHECK11-NEXT: store i32 2, ptr [[I]], align 4 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK11: .omp.final.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done7: @@ -1604,12 +1604,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1639,7 +1639,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1656,7 +1656,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1665,7 +1665,7 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -1690,7 +1690,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -1723,7 +1723,7 @@ int main() { // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]], !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1735,14 +1735,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: @@ -1773,17 +1773,17 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I12]], align 4 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN27:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN27:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN27]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY28:%.*]] // CHECK13: arraydestroy.body28: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST29:%.*]] = phi ptr [ [[TMP15]], [[OMP_INNER_FOR_END26]] ], [ [[ARRAYDESTROY_ELEMENT30:%.*]], [[ARRAYDESTROY_BODY28]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT30]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST29]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT30]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT30]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE31:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT30]], [[ARRAY_BEGIN27]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE31]], label [[ARRAYDESTROY_DONE32:%.*]], label [[ARRAYDESTROY_BODY28]] // CHECK13: arraydestroy.done32: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP16]] // @@ -1812,12 +1812,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -1828,7 +1828,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1837,7 +1837,7 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1853,7 +1853,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -1886,7 +1886,7 @@ int main() { // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP11]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1898,29 +1898,29 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done11: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK13: arraydestroy.body13: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK13: arraydestroy.done17: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP11]] // @@ -1937,7 +1937,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1983,12 +1983,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2018,7 +2018,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2035,7 +2035,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2044,7 +2044,7 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2069,7 +2069,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2100,7 +2100,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]], !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2112,14 +2112,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -2150,17 +2150,17 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I11]], align 4 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN26:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN26:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN26]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY27:%.*]] // CHECK15: arraydestroy.body27: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST28:%.*]] = phi ptr [ [[TMP15]], [[OMP_INNER_FOR_END25]] ], [ [[ARRAYDESTROY_ELEMENT29:%.*]], [[ARRAYDESTROY_BODY27]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT29]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST28]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT29]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT29]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE30:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT29]], [[ARRAY_BEGIN26]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE30]], label [[ARRAYDESTROY_DONE31:%.*]], label [[ARRAYDESTROY_BODY27]] // CHECK15: arraydestroy.done31: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP16]] // @@ -2189,12 +2189,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2205,7 +2205,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2214,7 +2214,7 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2230,7 +2230,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2261,7 +2261,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META4]], !align [[META5]], !llvm.access.group [[ACC_GRP12]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2273,29 +2273,29 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] // CHECK15: arraydestroy.body12: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK15: arraydestroy.done16: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP11]] // @@ -2312,7 +2312,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2358,12 +2358,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2393,7 +2393,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/for_firstprivate_codegen.cpp b/clang/test/OpenMP/for_firstprivate_codegen.cpp index 83b5939799642..57070861b5fd5 100644 --- a/clang/test/OpenMP/for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/for_firstprivate_codegen.cpp @@ -167,12 +167,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -190,7 +190,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -229,7 +229,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -273,9 +273,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -288,7 +288,7 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @t_var, align 4 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -297,7 +297,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] @@ -305,7 +305,7 @@ int main() { // CHECK1: omp.arraycpy.done1: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], ptr noundef nonnull align 4 dereferenceable(4) @var, ptr noundef [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[SIVAR]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -342,7 +342,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -360,14 +360,14 @@ int main() { // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -402,12 +402,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -418,7 +418,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -430,17 +430,17 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP0]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // @@ -481,7 +481,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -531,9 +531,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP8:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP9:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -557,7 +557,7 @@ int main() { // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[T_VAR3]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC4]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -566,7 +566,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] @@ -575,7 +575,7 @@ int main() { // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP7]], ptr noundef [[AGG_TMP8]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP8]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR7]], ptr [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 @@ -614,7 +614,7 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -630,14 +630,14 @@ int main() { // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR7]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done15: @@ -663,12 +663,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -722,7 +722,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -758,12 +758,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -781,7 +781,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -820,7 +820,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -892,12 +892,12 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // @@ -915,7 +915,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -954,7 +954,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: diff --git a/clang/test/OpenMP/for_lastprivate_codegen.cpp b/clang/test/OpenMP/for_lastprivate_codegen.cpp index dce927d1832e1..46de6fdf77273 100644 --- a/clang/test/OpenMP/for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/for_lastprivate_codegen.cpp @@ -367,7 +367,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(24) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) @@ -384,18 +384,18 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @main.omp_outlined.3) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -454,8 +454,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR5:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -465,16 +465,16 @@ int main() { // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -521,7 +521,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX8]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR5]], align 4 @@ -548,7 +548,7 @@ int main() { // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: store i32 [[TMP23]], ptr [[TMP0]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC2]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -566,14 +566,14 @@ int main() { // CHECK1-NEXT: store i32 [[TMP25]], ptr [[TMP4]], align 4 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1: .omp.lastprivate.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done16: @@ -584,12 +584,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -841,7 +841,7 @@ int main() { // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 128 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[SST]]) @@ -851,20 +851,20 @@ int main() { // CHECK1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 128 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 128 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 128, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP0]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP2]] // @@ -895,7 +895,7 @@ int main() { // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK1-NEXT: store ptr [[TMP]], ptr [[_TMP2]], align 8 @@ -928,9 +928,9 @@ int main() { // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP8]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP9]], align 4 @@ -950,7 +950,7 @@ int main() { // CHECK1-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 // CHECK1-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 // CHECK1-NEXT: [[C11:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[C11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[C11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP13]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP12]], align 4 @@ -1006,29 +1006,29 @@ int main() { // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A2]], ptr [[A]], align 8 // CHECK1-NEXT: [[C3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C3]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP4]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[E]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META3]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP5]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[E7]], ptr align 1 [[TMP5]], i64 4, i1 false) // CHECK1-NEXT: store ptr [[E7]], ptr [[_TMP8]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP7]]) -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[A9]], ptr [[_TMP10]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[C12]], ptr [[_TMP13]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]] // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 @@ -1054,14 +1054,14 @@ int main() { // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP18]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP17]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[B11]], align 4 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP19]], -1 // CHECK1-NEXT: store i32 [[DEC]], ptr [[B11]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP13]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP21]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP20]], align 4 @@ -1118,7 +1118,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1192,8 +1192,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR3:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 128 -// CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK1-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 +// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1202,18 +1202,18 @@ int main() { // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -1223,7 +1223,7 @@ int main() { // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK1-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1260,10 +1260,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX10]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1286,7 +1286,7 @@ int main() { // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 128 // CHECK1-NEXT: store i32 [[TMP23]], ptr [[TMP0]], align 128 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP1]], ptr align 128 [[VEC4]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP24]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1303,14 +1303,14 @@ int main() { // CHECK1-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP25]]) // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1: .omp.lastprivate.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN16]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN16]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done17: @@ -1321,12 +1321,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -1390,9 +1390,9 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP8]], align 4 @@ -1435,13 +1435,13 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A1]], ptr [[A]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[A3]], ptr [[_TMP4]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 @@ -1470,7 +1470,7 @@ int main() { // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP11]], align 4 @@ -1514,7 +1514,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1576,7 +1576,7 @@ int main() { // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK3-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK3-NEXT: store ptr [[TMP]], ptr [[_TMP2]], align 8 @@ -1609,12 +1609,12 @@ int main() { // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP8]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP9]], align 8 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE0_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1670,29 +1670,29 @@ int main() { // CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[A2]], ptr [[A]], align 8 // CHECK3-NEXT: [[C3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C3]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP3]], ptr [[_TMP4]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[E]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META3]] // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP5]], align 8 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[E7]], ptr align 1 [[TMP5]], i64 4, i1 false) // CHECK3-NEXT: store ptr [[E7]], ptr [[_TMP8]], align 8 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP7]]) -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[A9]], ptr [[_TMP10]], align 8 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[C12]], ptr [[_TMP13]], align 8 -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]] // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 @@ -1721,12 +1721,12 @@ int main() { // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP10]], align 8 +// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP10]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[B11]], ptr [[TMP20]], align 8 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[_TMP13]], align 8 +// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[_TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1779,26 +1779,26 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP12]], ptr [[TMP14]], ptr [[TMP16]]) // CHECK3-NEXT: ret void // @@ -1812,7 +1812,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP4]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP3]], align 4 @@ -1832,12 +1832,12 @@ int main() { // CHECK3-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 // CHECK3-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 2 // CHECK3-NEXT: store i32 [[MUL]], ptr [[TMP6]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @_ZZN2SSC1ERiENKUlvE0_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP9]]) // CHECK3-NEXT: ret void // @@ -1874,22 +1874,22 @@ int main() { // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP5]], ptr [[_TMP3]], align 8 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[A5]], ptr [[_TMP6]], align 8 -// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[C8]], ptr [[_TMP9]], align 8 // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 @@ -1918,14 +1918,14 @@ int main() { // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP17]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP16]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[B7]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP18]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[B7]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP9]], align 8 +// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP20]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP19]], align 4 @@ -1982,9 +1982,9 @@ int main() { // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2017,7 +2017,7 @@ int main() { // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[B3]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP11]], align 4 @@ -2025,7 +2025,7 @@ int main() { // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP13]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[B3]], align 4 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP15]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP14]], align 4 @@ -2135,14 +2135,14 @@ int main() { // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr @g1, align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr @g1, align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr @g1, align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr @g1, align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 @@ -2172,11 +2172,11 @@ int main() { // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK4-NEXT: store i32 1, ptr [[G]], align 128 -// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store volatile i32 1, ptr [[TMP11]], align 4 // CHECK4-NEXT: store i32 2, ptr [[SIVAR3]], align 4 // CHECK4-NEXT: store i32 1, ptr [[G]], align 128 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store volatile i32 1, ptr [[TMP12]], align 4 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, [84 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 128 @@ -2192,7 +2192,7 @@ int main() { // CHECK4-NEXT: [[TMP13:%.*]] = load volatile i32, ptr [[G]], align 128 // CHECK4-NEXT: store volatile i32 [[TMP13]], ptr [[BLOCK_CAPTURED]], align 128 // CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, [84 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 5 -// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP14]], ptr [[BLOCK_CAPTURED5]], align 32 // CHECK4-NEXT: [[BLOCK_CAPTURED6:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, [84 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 6 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR3]], align 4 @@ -2239,7 +2239,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, [84 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 // CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 128 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, [84 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 32 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 32, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store i32 1, ptr [[TMP0]], align 4 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32, [84 x i8], i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 // CHECK4-NEXT: store i32 4, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 @@ -2273,7 +2273,7 @@ int main() { // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK4-NEXT: store ptr [[TMP]], ptr [[_TMP2]], align 8 @@ -2306,7 +2306,7 @@ int main() { // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP8]], align 4 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 0 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 @@ -2321,7 +2321,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 5 // CHECK4-NEXT: store ptr [[THIS1]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr }>, ptr [[BLOCK]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP9]], ptr [[BLOCK_CAPTURED]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 // CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 @@ -2379,29 +2379,29 @@ int main() { // CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[A2]], ptr [[A]], align 8 // CHECK4-NEXT: [[C3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C3]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP4]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[E]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META3]] // CHECK4-NEXT: store ptr [[TMP4]], ptr [[_TMP5]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]] // CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[E7]], ptr align 1 [[TMP5]], i64 4, i1 false) // CHECK4-NEXT: store ptr [[E7]], ptr [[_TMP8]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP7]]) -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[A9]], ptr [[_TMP10]], align 8 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[C12]], ptr [[_TMP13]], align 8 -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]] // CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 @@ -2440,13 +2440,13 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8 +// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP17]], ptr [[BLOCK_CAPTURED]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED15:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 8 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[B11]], align 4 // CHECK4-NEXT: store i32 [[TMP18]], ptr [[BLOCK_CAPTURED15]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED16:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP13]], align 8 +// CHECK4-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP19]], ptr [[BLOCK_CAPTURED16]], align 8 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 // CHECK4-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8 @@ -2502,7 +2502,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 // CHECK4-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 @@ -2511,15 +2511,15 @@ int main() { // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @g1_block_invoke_2.omp_outlined, ptr [[THIS]], ptr [[TMP5]], ptr [[BLOCK_CAPTURE_ADDR4]], ptr [[TMP6]]) // CHECK4-NEXT: ret void // @@ -2556,22 +2556,22 @@ int main() { // CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP5]], ptr [[_TMP3]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[A5]], ptr [[_TMP6]], align 8 -// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[C8]], ptr [[_TMP9]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 @@ -2600,14 +2600,14 @@ int main() { // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP17]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP16]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[B7]], align 4 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP18]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[B7]], align 4 -// CHECK4-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP9]], align 8 +// CHECK4-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP20]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP19]], align 4 @@ -2651,7 +2651,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 // CHECK4-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 @@ -2671,12 +2671,12 @@ int main() { // CHECK4-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 // CHECK4-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @___ZN2SSC2ERi_block_invoke.omp_outlined, ptr [[THIS]], ptr [[TMP5]]) // CHECK4-NEXT: ret void // @@ -2704,9 +2704,9 @@ int main() { // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 // CHECK4-NEXT: store ptr [[_TMP2]], ptr [[_TMP3]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 @@ -2740,9 +2740,9 @@ int main() { // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP11]], align 4 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP12]], align 4 @@ -2761,7 +2761,7 @@ int main() { // CHECK4-NEXT: [[BF_RESULT_SHL:%.*]] = shl i8 [[BF_VALUE]], 4 // CHECK4-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 // CHECK4-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 -// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP16]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP15]], align 4 @@ -2789,7 +2789,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK5-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(24) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) @@ -2806,18 +2806,18 @@ int main() { // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @main.omp_outlined.3) // CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP1]] // @@ -2876,8 +2876,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[SIVAR5:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2887,16 +2887,16 @@ int main() { // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -2943,7 +2943,7 @@ int main() { // CHECK5-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX8]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR5]], align 4 @@ -2970,7 +2970,7 @@ int main() { // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[TMP0]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC2]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2988,14 +2988,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP25]], ptr [[TMP4]], align 4 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done16: @@ -3006,12 +3006,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -3281,7 +3281,7 @@ int main() { // CHECK5-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 128 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: call void @_ZN3SSTIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[SST]]) @@ -3291,20 +3291,20 @@ int main() { // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 128 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 128 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 128, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP0]]) // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP2]] // @@ -3335,7 +3335,7 @@ int main() { // CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8 // CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK5-NEXT: store ptr [[TMP]], ptr [[_TMP2]], align 8 @@ -3368,9 +3368,9 @@ int main() { // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP8]], align 4 -// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK5-NEXT: store i32 [[INC]], ptr [[TMP9]], align 4 @@ -3390,7 +3390,7 @@ int main() { // CHECK5-NEXT: [[BF_RESULT_ASHR:%.*]] = ashr i8 [[BF_RESULT_SHL]], 4 // CHECK5-NEXT: [[BF_RESULT_CAST:%.*]] = sext i8 [[BF_RESULT_ASHR]] to i32 // CHECK5-NEXT: [[C11:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 -// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[C11]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[C11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP13]], 1 // CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP12]], align 4 @@ -3446,29 +3446,29 @@ int main() { // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: store ptr [[A2]], ptr [[A]], align 8 // CHECK5-NEXT: [[C3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 3 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C3]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[TMP3]], ptr [[_TMP4]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[E]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META3]] // CHECK5-NEXT: store ptr [[TMP4]], ptr [[_TMP5]], align 8 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[E7]], ptr align 1 [[TMP5]], i64 4, i1 false) // CHECK5-NEXT: store ptr [[E7]], ptr [[_TMP8]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP7]]) -// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[A9]], ptr [[_TMP10]], align 8 -// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[C12]], ptr [[_TMP13]], align 8 -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]] // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 1 @@ -3494,14 +3494,14 @@ int main() { // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP18]], 1 // CHECK5-NEXT: store i32 [[INC]], ptr [[TMP17]], align 4 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[B11]], align 4 // CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP19]], -1 // CHECK5-NEXT: store i32 [[DEC]], ptr [[B11]], align 4 -// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP13]], align 8 +// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP21]], 1 // CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP20]], align 4 @@ -3572,7 +3572,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3632,8 +3632,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 128 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 128 -// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3642,18 +3642,18 @@ int main() { // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -3663,7 +3663,7 @@ int main() { // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK5-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3700,10 +3700,10 @@ int main() { // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX10]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3726,7 +3726,7 @@ int main() { // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 128 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[TMP0]], align 128 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP1]], ptr align 128 [[VEC4]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP24]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3743,14 +3743,14 @@ int main() { // CHECK5-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP25]]) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN16]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN16]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done17: @@ -3761,12 +3761,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -3830,9 +3830,9 @@ int main() { // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK5-NEXT: store i32 [[INC]], ptr [[TMP8]], align 4 @@ -3875,13 +3875,13 @@ int main() { // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: store ptr [[A1]], ptr [[A]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store ptr [[A3]], ptr [[_TMP4]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 @@ -3910,7 +3910,7 @@ int main() { // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK5-NEXT: store i32 [[INC]], ptr [[TMP11]], align 4 @@ -3954,7 +3954,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/for_linear_codegen.cpp b/clang/test/OpenMP/for_linear_codegen.cpp index 5a21fe8509fd3..55522c93d8df1 100644 --- a/clang/test/OpenMP/for_linear_codegen.cpp +++ b/clang/test/OpenMP/for_linear_codegen.cpp @@ -201,7 +201,7 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 2, ptr @main.omp_outlined, ptr [[PVAR]], ptr [[LVAR]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP0]] // @@ -250,8 +250,8 @@ int main() { // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[PVAR]], ptr [[PVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[LVAR]], ptr [[LVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTLINEAR_START]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP1]], align 8 @@ -349,19 +349,19 @@ int main() { // CHECK1-NEXT: store ptr [[F]], ptr [[PVAR]], align 8 // CHECK1-NEXT: [[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TEST]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[F1]], ptr [[LVAR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LVAR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[LVAR]], align 8, !nonnull [[META3]], !align [[META7:![0-9]+]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[PVAR]], ptr [[TMP0]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -381,7 +381,7 @@ int main() { // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK1-NEXT: ret void @@ -422,18 +422,18 @@ int main() { // CHECK1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A1]], ptr [[A]], align 8 // CHECK1-NEXT: [[C2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C2]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C2]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP3]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTLINEAR_START]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTLINEAR_START5]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTLINEAR_START6]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 @@ -485,14 +485,14 @@ int main() { // CHECK1-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP22]], 1 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP21]], [[MUL17]] // CHECK1-NEXT: store i32 [[ADD18]], ptr [[C10]], align 4 -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP24]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP23]], align 4 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[B9]], align 4 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP25]], -1 // CHECK1-NEXT: store i32 [[DEC]], ptr [[B9]], align 4 -// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[_TMP11]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[_TMP11]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP27]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP26]], align 4 @@ -512,17 +512,17 @@ int main() { // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK1-NEXT: br i1 [[TMP30]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK1: .omp.linear.pu: -// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP31]], ptr [[_TMP20]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[A7]], align 4 -// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[_TMP20]], align 8 +// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[_TMP20]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store i32 [[TMP32]], ptr [[TMP33]], align 4 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[B9]], align 4 // CHECK1-NEXT: store i32 [[TMP34]], ptr [[B]], align 4 -// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP35]], ptr [[_TMP21]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[C10]], align 4 -// CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[_TMP21]], align 8 +// CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[_TMP21]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store i32 [[TMP36]], ptr [[TMP37]], align 4 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[B22:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 1 @@ -595,14 +595,14 @@ int main() { // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[PVAR]], ptr [[PVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[LVAR]], ptr [[LVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTLINEAR_START]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTLINEAR_START3]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 @@ -652,7 +652,7 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[PVAR4]], align 8 // CHECK1-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP18]], i32 1 // CHECK1-NEXT: store ptr [[INCDEC_PTR]], ptr [[PVAR4]], align 8 -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP19]], align 4 @@ -674,10 +674,10 @@ int main() { // CHECK1: .omp.linear.pu: // CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[PVAR4]], align 8 // CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP0]], align 8 -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP25]], ptr [[_TMP12]], align 8 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[LVAR5]], align 4 -// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[_TMP12]], align 8 +// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[_TMP12]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store i32 [[TMP26]], ptr [[TMP27]], align 4 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK1: .omp.linear.pu.done: @@ -686,12 +686,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -743,9 +743,9 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A1]], ptr [[A]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[DOTLINEAR_START]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 @@ -786,7 +786,7 @@ int main() { // CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP13]], 1 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[MUL6]] // CHECK1-NEXT: store i32 [[ADD7]], ptr [[A3]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP14]], align 4 @@ -806,10 +806,10 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 // CHECK1-NEXT: br i1 [[TMP18]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK1: .omp.linear.pu: -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP19]], ptr [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A3]], align 4 -// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP9]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP9]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store i32 [[TMP20]], ptr [[TMP21]], align 4 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK1: .omp.linear.pu.done: @@ -818,7 +818,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -827,7 +827,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -876,7 +876,7 @@ int main() { // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK3-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK3-NEXT: ret void @@ -918,18 +918,18 @@ int main() { // CHECK3-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[A1]], ptr [[A]], align 8 // CHECK3-NEXT: [[C2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C2]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP3]], ptr [[_TMP3]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTLINEAR_START]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTLINEAR_START5]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTLINEAR_START6]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 @@ -984,12 +984,12 @@ int main() { // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP23]], align 8 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[B9]], ptr [[TMP26]], align 8 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP11]], align 8 +// CHECK3-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 8 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1008,17 +1008,17 @@ int main() { // CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0 // CHECK3-NEXT: br i1 [[TMP31]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK3: .omp.linear.pu: -// CHECK3-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP32]], ptr [[_TMP20]], align 8 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[A7]], align 4 -// CHECK3-NEXT: [[TMP34:%.*]] = load ptr, ptr [[_TMP20]], align 8 +// CHECK3-NEXT: [[TMP34:%.*]] = load ptr, ptr [[_TMP20]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store i32 [[TMP33]], ptr [[TMP34]], align 4 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[B9]], align 4 // CHECK3-NEXT: store i32 [[TMP35]], ptr [[B]], align 4 -// CHECK3-NEXT: [[TMP36:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK3-NEXT: [[TMP36:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP36]], ptr [[_TMP21]], align 8 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[C10]], align 4 -// CHECK3-NEXT: [[TMP38:%.*]] = load ptr, ptr [[_TMP21]], align 8 +// CHECK3-NEXT: [[TMP38:%.*]] = load ptr, ptr [[_TMP21]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store i32 [[TMP37]], ptr [[TMP38]], align 4 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[B22:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 1 @@ -1043,26 +1043,26 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP12]], ptr [[TMP14]], ptr [[TMP16]]) // CHECK3-NEXT: ret void // @@ -1104,21 +1104,21 @@ int main() { // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP5]], ptr [[_TMP3]], align 8 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTLINEAR_START]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTLINEAR_START5]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTLINEAR_START6]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 @@ -1170,14 +1170,14 @@ int main() { // CHECK3-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP24]], 1 // CHECK3-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], [[MUL17]] // CHECK3-NEXT: store i32 [[ADD18]], ptr [[C10]], align 4 -// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP26]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP25]], align 4 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[B9]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP27]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[B9]], align 4 -// CHECK3-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP11]], align 8 +// CHECK3-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP29]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP28]], align 4 @@ -1197,17 +1197,17 @@ int main() { // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK3-NEXT: br i1 [[TMP32]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK3: .omp.linear.pu: -// CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP33]], ptr [[_TMP20]], align 8 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[A7]], align 4 -// CHECK3-NEXT: [[TMP35:%.*]] = load ptr, ptr [[_TMP20]], align 8 +// CHECK3-NEXT: [[TMP35:%.*]] = load ptr, ptr [[_TMP20]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store i32 [[TMP34]], ptr [[TMP35]], align 4 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[B9]], align 4 // CHECK3-NEXT: store i32 [[TMP36]], ptr [[TMP2]], align 4 -// CHECK3-NEXT: [[TMP37:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK3-NEXT: [[TMP37:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP37]], ptr [[_TMP21]], align 8 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[C10]], align 4 -// CHECK3-NEXT: [[TMP39:%.*]] = load ptr, ptr [[_TMP21]], align 8 +// CHECK3-NEXT: [[TMP39:%.*]] = load ptr, ptr [[_TMP21]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store i32 [[TMP38]], ptr [[TMP39]], align 4 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK3: .omp.linear.pu.done: @@ -1273,7 +1273,7 @@ int main() { // CHECK4-NEXT: [[_TMP13:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr @g1, align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr @g1, align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr @g, align 4 // CHECK4-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START]], align 4 @@ -1325,12 +1325,12 @@ int main() { // CHECK4-NEXT: [[TMP15:%.*]] = load i32, ptr [[G]], align 4 // CHECK4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP15]], 5 // CHECK4-NEXT: store i32 [[ADD9]], ptr [[G]], align 4 -// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP17:%.*]] = load volatile i32, ptr [[TMP16]], align 4 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], 5 // CHECK4-NEXT: store volatile i32 [[ADD10]], ptr [[TMP16]], align 4 // CHECK4-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store volatile i32 5, ptr [[TMP18]], align 4 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 @@ -1346,7 +1346,7 @@ int main() { // CHECK4-NEXT: [[TMP19:%.*]] = load volatile i32, ptr [[G]], align 4 // CHECK4-NEXT: store volatile i32 [[TMP19]], ptr [[BLOCK_CAPTURED]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED11:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 -// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP20]], ptr [[BLOCK_CAPTURED11]], align 8 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 // CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 @@ -1369,10 +1369,10 @@ int main() { // CHECK4: .omp.linear.pu: // CHECK4-NEXT: [[TMP26:%.*]] = load i32, ptr [[G]], align 4 // CHECK4-NEXT: store i32 [[TMP26]], ptr @g, align 4 -// CHECK4-NEXT: [[TMP27:%.*]] = load ptr, ptr @g1, align 8 +// CHECK4-NEXT: [[TMP27:%.*]] = load ptr, ptr @g1, align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP27]], ptr [[_TMP13]], align 8 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, ptr [[G1]], align 4 -// CHECK4-NEXT: [[TMP29:%.*]] = load ptr, ptr [[_TMP13]], align 8 +// CHECK4-NEXT: [[TMP29:%.*]] = load ptr, ptr [[_TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store volatile i32 [[TMP28]], ptr [[TMP29]], align 4 // CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK4: .omp.linear.pu.done: @@ -1390,7 +1390,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 // CHECK4-NEXT: store i32 2, ptr [[BLOCK_CAPTURE_ADDR]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store i32 2, ptr [[TMP0]], align 4 // CHECK4-NEXT: ret void // @@ -1411,7 +1411,7 @@ int main() { // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK4-NEXT: ret void @@ -1453,18 +1453,18 @@ int main() { // CHECK4-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[A1]], ptr [[A]], align 8 // CHECK4-NEXT: [[C2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C2]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP3]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK4-NEXT: store i32 [[TMP5]], ptr [[DOTLINEAR_START]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[B]], align 4 // CHECK4-NEXT: store i32 [[TMP6]], ptr [[DOTLINEAR_START5]], align 4 -// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK4-NEXT: store i32 [[TMP8]], ptr [[DOTLINEAR_START6]], align 4 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 @@ -1529,13 +1529,13 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK4-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP23]], ptr [[BLOCK_CAPTURED]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED19:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 8 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, ptr [[B9]], align 4 // CHECK4-NEXT: store i32 [[TMP24]], ptr [[BLOCK_CAPTURED19]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED20:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP11]], align 8 +// CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP25]], ptr [[BLOCK_CAPTURED20]], align 8 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 // CHECK4-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP26]], align 8 @@ -1556,17 +1556,17 @@ int main() { // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK4-NEXT: br i1 [[TMP30]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK4: .omp.linear.pu: -// CHECK4-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP31]], ptr [[_TMP22]], align 8 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, ptr [[A7]], align 4 -// CHECK4-NEXT: [[TMP33:%.*]] = load ptr, ptr [[_TMP22]], align 8 +// CHECK4-NEXT: [[TMP33:%.*]] = load ptr, ptr [[_TMP22]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store i32 [[TMP32]], ptr [[TMP33]], align 4 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, ptr [[B9]], align 4 // CHECK4-NEXT: store i32 [[TMP34]], ptr [[B]], align 4 -// CHECK4-NEXT: [[TMP35:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP35:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP35]], ptr [[_TMP23]], align 8 // CHECK4-NEXT: [[TMP36:%.*]] = load i32, ptr [[C10]], align 4 -// CHECK4-NEXT: [[TMP37:%.*]] = load ptr, ptr [[_TMP23]], align 8 +// CHECK4-NEXT: [[TMP37:%.*]] = load ptr, ptr [[_TMP23]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store i32 [[TMP36]], ptr [[TMP37]], align 4 // CHECK4-NEXT: [[TMP38:%.*]] = load i32, ptr [[B]], align 4 // CHECK4-NEXT: [[B24:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 1 @@ -1592,7 +1592,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 // CHECK4-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 @@ -1601,15 +1601,15 @@ int main() { // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @g1_block_invoke_2.omp_outlined, ptr [[THIS]], ptr [[TMP5]], ptr [[BLOCK_CAPTURE_ADDR4]], ptr [[TMP6]]) // CHECK4-NEXT: ret void // @@ -1651,21 +1651,21 @@ int main() { // CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP4]], ptr [[_TMP2]], align 8 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP5]], ptr [[_TMP3]], align 8 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK4-NEXT: store i32 [[TMP7]], ptr [[DOTLINEAR_START]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK4-NEXT: store i32 [[TMP8]], ptr [[DOTLINEAR_START5]], align 4 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-NEXT: store i32 [[TMP10]], ptr [[DOTLINEAR_START6]], align 4 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 @@ -1717,14 +1717,14 @@ int main() { // CHECK4-NEXT: [[MUL17:%.*]] = mul nsw i32 [[TMP24]], 1 // CHECK4-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP23]], [[MUL17]] // CHECK4-NEXT: store i32 [[ADD18]], ptr [[C10]], align 4 -// CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP8]], align 8 +// CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP26]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP25]], align 4 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, ptr [[B9]], align 4 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP27]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[B9]], align 4 -// CHECK4-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP11]], align 8 +// CHECK4-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP29]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP28]], align 4 @@ -1744,18 +1744,18 @@ int main() { // CHECK4-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 // CHECK4-NEXT: br i1 [[TMP32]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] // CHECK4: .omp.linear.pu: -// CHECK4-NEXT: [[TMP33:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP33:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP33]], ptr [[_TMP20]], align 8 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, ptr [[A7]], align 4 -// CHECK4-NEXT: [[TMP35:%.*]] = load ptr, ptr [[_TMP20]], align 8 +// CHECK4-NEXT: [[TMP35:%.*]] = load ptr, ptr [[_TMP20]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store i32 [[TMP34]], ptr [[TMP35]], align 4 // CHECK4-NEXT: [[TMP36:%.*]] = load i32, ptr [[B9]], align 4 // CHECK4-NEXT: store i32 [[TMP36]], ptr [[TMP2]], align 4 -// CHECK4-NEXT: [[TMP37:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP37:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP37]], ptr [[_TMP21]], align 8 // CHECK4-NEXT: [[TMP38:%.*]] = load i32, ptr [[C10]], align 4 // CHECK4-NEXT: [[C22:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP39:%.*]] = load ptr, ptr [[C22]], align 8 +// CHECK4-NEXT: [[TMP39:%.*]] = load ptr, ptr [[C22]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store i32 [[TMP38]], ptr [[TMP39]], align 4 // CHECK4-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] // CHECK4: .omp.linear.pu.done: diff --git a/clang/test/OpenMP/for_private_codegen.cpp b/clang/test/OpenMP/for_private_codegen.cpp index e3bac41b8df3a..45148d75e6ab6 100644 --- a/clang/test/OpenMP/for_private_codegen.cpp +++ b/clang/test/OpenMP/for_private_codegen.cpp @@ -114,7 +114,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -129,17 +129,17 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @main.omp_outlined.1) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -181,8 +181,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -193,7 +193,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -239,10 +239,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -258,14 +258,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -276,12 +276,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -354,7 +354,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -365,17 +365,17 @@ int main() { // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -406,7 +406,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -451,8 +451,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -462,7 +462,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -508,10 +508,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -527,14 +527,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -545,12 +545,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -580,7 +580,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -674,7 +674,7 @@ int main() { // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK4-NEXT: store double 1.000000e+00, ptr [[G]], align 8 -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK4-NEXT: store volatile double 1.000000e+00, ptr [[TMP8]], align 8 // CHECK4-NEXT: store i32 2, ptr [[SVAR]], align 4 // CHECK4-NEXT: store float 3.000000e+00, ptr [[SFVAR]], align 4 @@ -692,7 +692,7 @@ int main() { // CHECK4-NEXT: [[TMP9:%.*]] = load volatile double, ptr [[G]], align 8 // CHECK4-NEXT: store volatile double [[TMP9]], ptr [[BLOCK_CAPTURED]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP10]], ptr [[BLOCK_CAPTURED4]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[BLOCK]], i32 0, i32 7 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[SVAR]], align 4 @@ -729,7 +729,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 // CHECK4-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store double 2.000000e+00, ptr [[TMP0]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr, i32, float }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 // CHECK4-NEXT: store i32 4, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 diff --git a/clang/test/OpenMP/for_reduction_codegen.cpp b/clang/test/OpenMP/for_reduction_codegen.cpp index cb4bcc99c3ff3..314d78592316a 100644 --- a/clang/test/OpenMP/for_reduction_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_codegen.cpp @@ -536,6 +536,8 @@ int main() { #endif + + //. // CHECK1: @.gomp_critical_user_.reduction.var = common global [8 x i32] zeroinitializer, align 8 // CHECK1: @.gomp_critical_user_.atomic_reduction.var = common global [8 x i32] zeroinitializer, align 8 @@ -544,40 +546,138 @@ int main() { //. // CHECK4: @.gomp_critical_user_.reduction.var = common global [8 x i32] zeroinitializer, align 8 //. - -// CHECK1-LABEL: define {{.*}}reductionArrayElement{{.*}}.omp_outlined{{.*}} +// CHECK1-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv +// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK1-NEXT: entry: +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 0, ptr @_Z21reductionArrayElementv.omp_outlined) +// CHECK1-NEXT: ret void +// +// +// CHECK1-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv.omp_outlined +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1: [[G_ARR:%.*]] = alloca i32, align 4 -// CHECK1: [[TMP0:%.*]] = sdiv exact i64 sub (i64 ptrtoint (ptr @g_arr to i64){{.*}} -// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[G_ARR:%.*]], i64 [[TMP0]] +// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[G_ARR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK1-NEXT: store i32 0, ptr [[G_ARR]], align 4 +// CHECK1-NEXT: [[TMP0:%.*]] = sdiv exact i64 sub (i64 ptrtoint (ptr @g_arr to i64), i64 ptrtoint (ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1) to i64)), ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) +// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[G_ARR]], i64 [[TMP0]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK1: cond.true: +// CHECK1-NEXT: br label [[COND_END:%.*]] +// CHECK1: cond.false: +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: br label [[COND_END]] +// CHECK1: cond.end: +// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK1: omp.inner.for.cond: +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 1 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 1 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]],{{.+}} +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] // CHECK1-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 +// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK1: omp.body.continue: +// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK1: omp.inner.for.inc: +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK1: omp.inner.for.end: +// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void {{.*}}__kmpc_for_static_fini{{.+}} -// CHECK1: {{.*}}call i32 {{.*}}__kmpc_reduce{{.+}} -// CHECK1: omp.reduction.default: -// CHECK1-NEXT: call void @__kmpc_barrier{{.+}} +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[G_ARR]], ptr [[TMP13]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z21reductionArrayElementv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP14]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK1-NEXT: ] +// CHECK1: .omp.reduction.case1: +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[G_ARR]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP3]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK1: .omp.reduction.case2: +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[G_ARR]], align 4 +// CHECK1-NEXT: [[TMP18:%.*]] = atomicrmw add ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), i32 [[TMP17]] monotonic, align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP3]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK1: .omp.reduction.default: +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) // CHECK1-NEXT: ret void // - +// +// CHECK1-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv.omp_outlined.omp.reduction.reduction_func +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK1-NEXT: entry: +// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 +// CHECK1-NEXT: ret void +// +// // CHECK1-LABEL: define {{[^@]+}}@main -// CHECK1-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: () #[[ATTR5:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [4 x %struct.S], align 16 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [4 x [[STRUCT_S]]], align 16 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 -// CHECK1-NEXT: [[ARRS:%.*]] = alloca [10 x [4 x %struct.S]], align 16 +// CHECK1-NEXT: [[ARRS:%.*]] = alloca [10 x [4 x [[STRUCT_S]]]], align 16 // CHECK1-NEXT: [[VAR2:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[VVAR2:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK1-NEXT: [[VVAR2:%.*]] = alloca [5 x [[STRUCT_S]]], align 16 // CHECK1-NEXT: [[VAR3:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 @@ -594,7 +694,7 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT2]], float noundef 4.000000e+00) // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], ptr [[ARRS]], i32 0, i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x [[STRUCT_S]]]], ptr [[ARRS]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 40 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -606,7 +706,7 @@ int main() { // CHECK1: arrayctor.cont: // CHECK1-NEXT: [[CALL:%.*]] = call noundef ptr @_Z3foov() // CHECK1-NEXT: store ptr [[CALL]], ptr [[VAR2]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[VVAR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[VVAR2]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END4:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN3]], i64 5 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP5:%.*]] // CHECK1: arrayctor.loop5: @@ -617,8 +717,8 @@ int main() { // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE8]], label [[ARRAYCTOR_CONT9:%.*]], label [[ARRAYCTOR_LOOP5]] // CHECK1: arrayctor.cont9: // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[VAR3]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 @@ -627,65 +727,65 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 10, [[TMP2]] // CHECK1-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP4]], align 16 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @main.omp_outlined.1, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[VEC]], ptr [[ARRS]]) -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @main.omp_outlined.2, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[ARRS]]) -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @main.omp_outlined.3, i64 10, i64 [[TMP2]], ptr [[VLA]]) -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.4, ptr [[VAR2]]) -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.5, ptr [[VAR2]]) -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.6, ptr [[VAR2]]) -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.7, ptr [[VAR2]]) -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.8, ptr [[VVAR2]]) -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VAR3]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.9, ptr [[TMP5]]) -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[VAR3]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.10, ptr [[TMP6]]) -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VAR3]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.11, ptr [[TMP7]]) -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[VAR3]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 1, ptr @main.omp_outlined.12, ptr [[TMP8]]) -// CHECK1-NEXT: call void {{.*}}reductionArrayElement{{.*}} +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @main.omp_outlined.1, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[VEC]], ptr [[ARRS]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 4, ptr @main.omp_outlined.2, i64 10, i64 [[TMP2]], ptr [[VLA]], ptr [[ARRS]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @main.omp_outlined.3, i64 10, i64 [[TMP2]], ptr [[VLA]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.4, ptr [[VAR2]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.5, ptr [[VAR2]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.6, ptr [[VAR2]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.7, ptr [[VAR2]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.8, ptr [[VVAR2]]) +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[VAR3]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.9, ptr [[TMP5]]) +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[VAR3]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.10, ptr [[TMP6]]) +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[VAR3]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.11, ptr [[TMP7]]) +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[VAR3]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 1, ptr @main.omp_outlined.12, ptr [[TMP8]]) +// CHECK1-NEXT: call void @_Z21reductionArrayElementv() // CHECK1-NEXT: [[CALL10:%.*]] = call noundef i32 @_Z5tmainIiLi42EET_v() // CHECK1-NEXT: store i32 [[CALL10]], ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP9]]) -// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[VVAR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[VVAR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[ARRAYCTOR_CONT9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: -// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], ptr [[ARRS]], i32 0, i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [10 x [4 x [[STRUCT_S]]]], ptr [[ARRS]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 40 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY14:%.*]] // CHECK1: arraydestroy.body14: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi ptr [ [[TMP11]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST15]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK1: arraydestroy.done18: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] -// CHECK1-NEXT: [[ARRAY_BEGIN19:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR1]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN19:%.*]] = getelementptr inbounds [4 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN19]], i64 4 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY20:%.*]] // CHECK1: arraydestroy.body20: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST21:%.*]] = phi ptr [ [[TMP12]], [[ARRAYDESTROY_DONE18]] ], [ [[ARRAYDESTROY_ELEMENT22:%.*]], [[ARRAYDESTROY_BODY20]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT22]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST21]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT22]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE23:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT22]], [[ARRAY_BEGIN19]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE23]], label [[ARRAYDESTROY_DONE24:%.*]], label [[ARRAYDESTROY_BODY20]] // CHECK1: arraydestroy.done24: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP13]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -695,7 +795,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -708,7 +808,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[S_ARR:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[S_ARR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -745,28 +845,28 @@ int main() { // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store float 0.000000e+00, ptr [[T_VAR3]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: store ptr [[VAR4]], ptr [[_TMP5]], align 8 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR16]]) // CHECK1-NEXT: store float 0x47EFFFFFE0000000, ptr [[T_VAR17]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 1 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -799,10 +899,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP5]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [4 x [[STRUCT_S]]], ptr [[TMP5]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -824,7 +924,7 @@ int main() { // CHECK1-NEXT: store ptr [[VAR16]], ptr [[TMP23]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 3 // CHECK1-NEXT: store ptr [[T_VAR17]], ptr [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 4, i64 32, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @main.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP9]], i32 4, i64 32, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @main.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: switch i32 [[TMP25]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] @@ -848,7 +948,7 @@ int main() { // CHECK1-NEXT: [[CONV16:%.*]] = uitofp i1 [[TMP28]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV16]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP29:%.*]] = load float, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[TMP30:%.*]] = load float, ptr [[T_VAR17]], align 4 // CHECK1-NEXT: [[CMP17:%.*]] = fcmp olt float [[TMP29]], [[TMP30]] @@ -867,11 +967,11 @@ int main() { // CHECK1: .omp.reduction.case2: // CHECK1-NEXT: [[TMP33:%.*]] = load float, ptr [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP34:%.*]] = atomicrmw fadd ptr [[TMP0]], float [[TMP33]] monotonic, align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL22:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP7]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP7]], ptr align 4 [[CALL22]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL24:%.*]] = call noundef float @_ZN1SIfEcvfEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL25:%.*]] = fcmp une float [[CALL24]], 0.000000e+00 // CHECK1-NEXT: br i1 [[TOBOOL25]], label [[LAND_RHS26:%.*]], label [[LAND_END29:%.*]] @@ -884,8 +984,8 @@ int main() { // CHECK1-NEXT: [[CONV30:%.*]] = uitofp i1 [[TMP35]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP23]], float noundef [[CONV30]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP23]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP23]]) #[[ATTR5]] -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP23]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP36:%.*]] = load float, ptr [[T_VAR17]], align 4 // CHECK1-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, ptr [[TMP3]] monotonic, align 4 // CHECK1-NEXT: br label [[ATOMIC_CONT:%.*]] @@ -915,14 +1015,14 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP9]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR16]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP9]]) +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR16]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP9]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -965,7 +1065,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP22]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP15]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP23:%.*]] = load float, ptr [[TMP19]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP17]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP23]], [[TMP24]] @@ -983,7 +1083,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEanERKS0_ -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 @@ -994,7 +1094,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEcvfEv -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1003,17 +1103,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1042,9 +1142,9 @@ int main() { // CHECK1-NEXT: store ptr [[ARRS]], ptr [[ARRS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRS_ADDR]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRS_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -1084,15 +1184,15 @@ int main() { // CHECK1-NEXT: [[TMP19:%.*]] = sub i64 [[TMP17]], [[TMP18]] // CHECK1-NEXT: [[TMP20:%.*]] = sdiv exact i64 [[TMP19]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[VLA7]], i64 [[TMP20]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw [10 x [4 x %struct.S]], ptr [[TMP4]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[ARRAYIDX8]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[ARRAYDECAY]], i64 1 +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds nuw [10 x [4 x [[STRUCT_S:%.*]]]], ptr [[TMP4]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x [[STRUCT_S]]], ptr [[ARRAYIDX8]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[ARRAYDECAY]], i64 1 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], i64 0, i64 1 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = sext i32 [[TMP22]] to i64 // CHECK1-NEXT: [[LB_ADD_LEN11:%.*]] = add nsw i64 0, [[TMP23]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds nuw [10 x [4 x %struct.S]], ptr [[TMP4]], i64 0, i64 [[LB_ADD_LEN11]] -// CHECK1-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[ARRAYIDX12]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds nuw [10 x [4 x [[STRUCT_S]]]], ptr [[TMP4]], i64 0, i64 [[LB_ADD_LEN11]] +// CHECK1-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [4 x [[STRUCT_S]]], ptr [[ARRAYIDX12]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[ARRAYDECAY13]], i64 2 // CHECK1-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 // CHECK1-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[ARRAYIDX9]] to i64 @@ -1238,10 +1338,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST50:%.*]] = phi ptr [ [[ARRAYIDX9]], [[OMP_ARRAYCPY_DONE46]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT52:%.*]], [[OMP_ARRAYCPY_BODY48]] ] // CHECK1-NEXT: [[TMP67:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP68:%.*]] = load i32, ptr [[TMP67]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP68]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP68]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL51:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST50]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST49]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST50]], ptr align 4 [[CALL51]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP68]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP68]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT52]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST50]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT53]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST49]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE54:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT52]], [[TMP66]] @@ -1255,7 +1355,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP69]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA15]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE56]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done56: @@ -1265,7 +1365,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.1.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -1319,7 +1419,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.2 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(160) [[ARRS:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1335,7 +1435,7 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[ARRS4:%.*]] = alloca [10 x [4 x %struct.S]], align 16 +// CHECK1-NEXT: [[ARRS4:%.*]] = alloca [10 x [4 x [[STRUCT_S:%.*]]]], align 16 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [3 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1346,8 +1446,8 @@ int main() { // CHECK1-NEXT: store ptr [[ARRS]], ptr [[ARRS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRS_ADDR]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[ARRS_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -1369,8 +1469,8 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] // CHECK1: omp.arrayinit.done: -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], ptr [[ARRS4]], i32 0, i32 0, i32 0 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 40 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [4 x [[STRUCT_S]]]], ptr [[ARRS4]], i32 0, i32 0, i32 0 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 40 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY5:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP9]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY5]], label [[OMP_ARRAYINIT_DONE10:%.*]], label [[OMP_ARRAYINIT_BODY6:%.*]] // CHECK1: omp.arrayinit.body6: @@ -1498,10 +1598,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST38:%.*]] = phi ptr [ [[TMP3]], [[OMP_ARRAYCPY_DONE34]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT40:%.*]], [[OMP_ARRAYCPY_BODY36]] ] // CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP40]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP40]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL39:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST38]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST37]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST38]], ptr align 4 [[CALL39]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP40]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP40]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT40]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST38]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT41]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST37]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE42:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT40]], [[TMP38]] @@ -1510,13 +1610,13 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP29]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: [[ARRAY_BEGIN44:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], ptr [[ARRS4]], i32 0, i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN44:%.*]] = getelementptr inbounds [10 x [4 x [[STRUCT_S]]]], ptr [[ARRS4]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN44]], i64 40 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN44]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE45:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done45: @@ -1524,12 +1624,12 @@ int main() { // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP42]]) // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP44]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP44]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.2.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -1580,7 +1680,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.3 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[ARR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1603,7 +1703,7 @@ int main() { // CHECK1-NEXT: store ptr [[ARR]], ptr [[ARR_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -1725,12 +1825,12 @@ int main() { // CHECK1: .omp.reduction.default: // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP36]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP36]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.3.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -1761,7 +1861,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.4 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1781,7 +1881,7 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR2]], ptr [[VAR2_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR2_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR2_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -1903,10 +2003,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST15:%.*]] = phi ptr [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT17:%.*]], [[OMP_ARRAYCPY_BODY13]] ] // CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP40]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP40]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST15]], ptr align 4 [[CALL16]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP40]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP40]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT17]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT18]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST14]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE19:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP38]] @@ -1921,7 +2021,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP41]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done21: @@ -1929,12 +2029,12 @@ int main() { // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP42]]) // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP44]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP44]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.4.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -1966,7 +2066,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.5 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1977,7 +2077,7 @@ int main() { // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VAR24:%.*]] = alloca [1 x [6 x %struct.S]], align 16 +// CHECK1-NEXT: [[VAR24:%.*]] = alloca [1 x [6 x [[STRUCT_S:%.*]]]], align 16 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1985,7 +2085,7 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR2]], ptr [[VAR2_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR2_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR2_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -1993,12 +2093,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[TMP1]], i64 1 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[TMP2]], i64 1 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP2]], i64 1 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds ptr, ptr [[TMP3]], i64 1 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP4]], i64 6 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [1 x [6 x %struct.S]], ptr [[VAR24]], i32 0, i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [1 x [6 x [[STRUCT_S]]]], ptr [[VAR24]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 6 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] @@ -2095,10 +2195,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST16:%.*]] = phi ptr [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT18:%.*]], [[OMP_ARRAYCPY_BODY14]] ] // CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP31]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP31]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL17:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST16]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST16]], ptr align 4 [[CALL17]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP31]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP31]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST16]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST15]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP29]] @@ -2107,24 +2207,24 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP26]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: [[ARRAY_BEGIN22:%.*]] = getelementptr inbounds [1 x [6 x %struct.S]], ptr [[VAR24]], i32 0, i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN22:%.*]] = getelementptr inbounds [1 x [6 x [[STRUCT_S]]]], ptr [[VAR24]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN22]], i64 6 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP32]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN22]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE23:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done23: // CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP34]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP34]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.5.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -2153,7 +2253,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.6 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2164,7 +2264,7 @@ int main() { // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VAR24:%.*]] = alloca [1 x [6 x %struct.S]], align 16 +// CHECK1-NEXT: [[VAR24:%.*]] = alloca [1 x [6 x [[STRUCT_S:%.*]]]], align 16 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2172,7 +2272,7 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR2]], ptr [[VAR2_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR2_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR2_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -2180,12 +2280,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw ptr, ptr [[TMP1]], i64 1 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[TMP2]], i64 1 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP2]], i64 1 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw ptr, ptr [[TMP3]], i64 1 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX2]], align 8 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP4]], i64 6 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [1 x [6 x %struct.S]], ptr [[VAR24]], i32 0, i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [1 x [6 x [[STRUCT_S]]]], ptr [[VAR24]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 6 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] @@ -2282,10 +2382,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST16:%.*]] = phi ptr [ [[ARRAYIDX1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT18:%.*]], [[OMP_ARRAYCPY_BODY14]] ] // CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP31]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP31]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL17:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST16]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST15]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST16]], ptr align 4 [[CALL17]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP31]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP31]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT18]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST16]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT19]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST15]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE20:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT18]], [[TMP29]] @@ -2294,24 +2394,24 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP26]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: [[ARRAY_BEGIN22:%.*]] = getelementptr inbounds [1 x [6 x %struct.S]], ptr [[VAR24]], i32 0, i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN22:%.*]] = getelementptr inbounds [1 x [6 x [[STRUCT_S]]]], ptr [[VAR24]], i32 0, i32 0, i32 0 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN22]], i64 6 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP32]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN22]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE23:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done23: // CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP34]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP34]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.6.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -2340,7 +2440,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.7 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[VAR2:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2359,7 +2459,7 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR2]], ptr [[VAR2_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR2_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR2_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -2436,20 +2536,20 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP13]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP13]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP13]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL9:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX1]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR24]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[CALL9]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP13]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP13]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP13]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR24]]) #[[ATTR5]] -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP13]]) +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR24]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP13]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.7.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -2467,7 +2567,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.8 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(20) [[VVAR2:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(20) [[VVAR2:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2478,21 +2578,21 @@ int main() { // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VVAR22:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK1-NEXT: [[VVAR22:%.*]] = alloca [5 x [[STRUCT_S:%.*]]], align 16 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VVAR2]], ptr [[VVAR2_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VVAR2_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VVAR2_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [5 x %struct.S], ptr [[TMP0]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [5 x %struct.S], ptr [[TMP0]], i64 0, i64 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[VVAR22]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [5 x [[STRUCT_S]]], ptr [[TMP0]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [5 x [[STRUCT_S]]], ptr [[TMP0]], i64 0, i64 4 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[VVAR22]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP1]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -2584,10 +2684,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST12:%.*]] = phi ptr [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT14:%.*]], [[OMP_ARRAYCPY_BODY10]] ] // CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP25]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP25]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST12]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST11]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST12]], ptr align 4 [[CALL13]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP25]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP25]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT14]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST12]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT15]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST11]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE16:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT14]], [[TMP23]] @@ -2596,24 +2696,24 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP20]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: [[ARRAY_BEGIN18:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[VVAR22]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN18:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[VVAR22]], i32 0, i32 0 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN18]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN18]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done19: // CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP28]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP28]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.8.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -2642,7 +2742,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.9 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2655,27 +2755,27 @@ int main() { // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VAR34:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[VAR34:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR3]], ptr [[VAR3_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR3_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR3_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x %struct.S], ptr [[TMP2]], i64 0, i64 1 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [4 x %struct.S], ptr [[TMP3]], i64 0, i64 2 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[VAR34]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x [[STRUCT_S]]], ptr [[TMP2]], i64 0, i64 1 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [4 x [[STRUCT_S]]], ptr [[TMP3]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[VAR34]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -2685,7 +2785,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] // CHECK1: omp.arrayinit.done: -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = sub i64 [[TMP6]], [[TMP7]] @@ -2769,10 +2869,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST15:%.*]] = phi ptr [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT17:%.*]], [[OMP_ARRAYCPY_BODY13]] ] // CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP29]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP29]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST15]], ptr align 4 [[CALL16]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP29]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP29]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT17]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT18]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST14]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE19:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP27]] @@ -2781,24 +2881,24 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: [[ARRAY_BEGIN21:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[VAR34]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN21:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[VAR34]], i32 0, i32 0 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN21]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN21]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done22: // CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP32]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP32]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.9.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -2827,7 +2927,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.10 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -2840,27 +2940,27 @@ int main() { // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VAR34:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[VAR34:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR3]], ptr [[VAR3_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR3_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR3_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x %struct.S], ptr [[TMP2]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [4 x %struct.S], ptr [[TMP3]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[VAR34]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x [[STRUCT_S]]], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [4 x [[STRUCT_S]]], ptr [[TMP3]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[VAR34]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -2870,7 +2970,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] // CHECK1: omp.arrayinit.done: -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP5]] to i64 // CHECK1-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK1-NEXT: [[TMP8:%.*]] = sub i64 [[TMP6]], [[TMP7]] @@ -2954,10 +3054,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST15:%.*]] = phi ptr [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT17:%.*]], [[OMP_ARRAYCPY_BODY13]] ] // CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP29]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP29]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL16:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST15]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST14]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST15]], ptr align 4 [[CALL16]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP29]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP29]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT17]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT18]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST14]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE19:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP27]] @@ -2966,24 +3066,24 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: [[ARRAY_BEGIN21:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[VAR34]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN21:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[VAR34]], i32 0, i32 0 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN21]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN21]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE22:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done22: // CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP32]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP32]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.10.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -3012,7 +3112,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.11 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3033,22 +3133,22 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR3]], ptr [[VAR3_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR3_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR3_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x %struct.S], ptr [[TMP2]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [4 x %struct.S], ptr [[TMP3]], i64 0, i64 3 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4 x [[STRUCT_S:%.*]]], ptr [[TMP2]], i64 0, i64 2 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [4 x [[STRUCT_S]]], ptr [[TMP3]], i64 0, i64 3 // CHECK1-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK1-NEXT: [[TMP6:%.*]] = sub i64 [[TMP4]], [[TMP5]] -// CHECK1-NEXT: [[TMP7:%.*]] = sdiv exact i64 [[TMP6]], ptrtoint (ptr getelementptr ([[STRUCT_S:%.*]], ptr null, i32 1) to i64) +// CHECK1-NEXT: [[TMP7:%.*]] = sdiv exact i64 [[TMP6]], ptrtoint (ptr getelementptr ([[STRUCT_S]], ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP8:%.*]] = add nuw i64 [[TMP7]], 1 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], ptrtoint (ptr getelementptr ([[STRUCT_S]], ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP10:%.*]] = call ptr @llvm.stacksave.p0() @@ -3065,7 +3165,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] // CHECK1: omp.arrayinit.done: -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i64 // CHECK1-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK1-NEXT: [[TMP15:%.*]] = sub i64 [[TMP13]], [[TMP14]] @@ -3152,10 +3252,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST14:%.*]] = phi ptr [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT16:%.*]], [[OMP_ARRAYCPY_BODY12]] ] // CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP37]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP38]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP38]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST14]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST14]], ptr align 4 [[CALL15]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP38]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP38]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT16]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT17]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST13]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE18:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT16]], [[TMP36]] @@ -3170,7 +3270,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP39]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[VLA]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done20: @@ -3178,12 +3278,12 @@ int main() { // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP40]]) // CHECK1-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP42]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP42]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.11.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -3215,7 +3315,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.12 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[VAR3:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3228,24 +3328,24 @@ int main() { // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VAR33:%.*]] = alloca [4 x %struct.S], align 16 +// CHECK1-NEXT: [[VAR33:%.*]] = alloca [4 x [[STRUCT_S:%.*]]], align 16 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR3]], ptr [[VAR3_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR3_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR3_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[VAR33]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 4 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [4 x [[STRUCT_S]]], ptr [[VAR33]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 4 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -3333,10 +3433,10 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST14:%.*]] = phi ptr [ [[TMP2]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT16:%.*]], [[OMP_ARRAYCPY_BODY12]] ] // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP22]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP22]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL15:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST14]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST13]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST14]], ptr align 4 [[CALL15]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP22]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP22]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT16]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT17]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST13]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE18:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT16]], [[TMP20]] @@ -3345,24 +3445,24 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP17]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: [[ARRAY_BEGIN20:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[VAR33]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN20:%.*]] = getelementptr inbounds [4 x [[STRUCT_S]]], ptr [[VAR33]], i32 0, i32 0 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN20]], i64 4 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN20]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done21: // CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP25]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP25]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.12.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -3391,7 +3491,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v -// CHECK1-SAME: () #[[ATTR1]] { +// CHECK1-SAME: () #[[ATTR0]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T:%.*]] = alloca i32, align 4 @@ -3399,10 +3499,10 @@ int main() { // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 -// CHECK1-NEXT: [[ARR:%.*]] = alloca [42 x %struct.S.0], align 16 +// CHECK1-NEXT: [[ARR:%.*]] = alloca [42 x [[STRUCT_S_0]]], align 16 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiLi42EET_v.vec, i64 8, i1 false) @@ -3411,7 +3511,7 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK1-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x %struct.S.0], ptr [[ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [42 x [[STRUCT_S_0]]], ptr [[ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 42 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -3421,41 +3521,41 @@ int main() { // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @_Z5tmainIiLi42EET_v.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @_Z5tmainIiLi42EET_v.omp_outlined.13, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP1]]) -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @_Z5tmainIiLi42EET_v.omp_outlined.14, ptr [[ARR]], ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[TMP2]]) +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 6, ptr @_Z5tmainIiLi42EET_v.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 4, ptr @_Z5tmainIiLi42EET_v.omp_outlined.13, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP1]]) +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 5, ptr @_Z5tmainIiLi42EET_v.omp_outlined.14, ptr [[ARR]], ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[TMP2]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN1:%.*]] = getelementptr inbounds [42 x %struct.S.0], ptr [[ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN1:%.*]] = getelementptr inbounds [42 x [[STRUCT_S_0]]], ptr [[ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN1]], i64 42 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] -// CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR1]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN3]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY4:%.*]] // CHECK1: arraydestroy.body4: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST5:%.*]] = phi ptr [ [[TMP4]], [[ARRAYDESTROY_DONE2]] ], [ [[ARRAYDESTROY_ELEMENT6:%.*]], [[ARRAYDESTROY_BODY4]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT6]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST5]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT6]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE7:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT6]], [[ARRAY_BEGIN3]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE7]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY4]] // CHECK1: arraydestroy.done8: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP5]] // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3468,7 +3568,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 @@ -3486,7 +3586,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3495,7 +3595,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3505,7 +3605,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -3518,7 +3618,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR1:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3553,21 +3653,21 @@ int main() { // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: store i32 0, ptr [[T_VAR3]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: store ptr [[VAR4]], ptr [[_TMP5]], align 8 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR16]]) @@ -3606,10 +3706,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP5]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP5]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -3655,7 +3755,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP28]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[T_VAR17]], align 4 // CHECK1-NEXT: [[CMP16:%.*]] = icmp slt i32 [[TMP29]], [[TMP30]] @@ -3674,11 +3774,11 @@ int main() { // CHECK1: .omp.reduction.case2: // CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP34:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP33]] monotonic, align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL21:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEanERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP7]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP7]], ptr align 4 [[CALL21]], i64 4, i1 false) -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL23:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]]) // CHECK1-NEXT: [[TOBOOL24:%.*]] = icmp ne i32 [[CALL23]], 0 // CHECK1-NEXT: br i1 [[TOBOOL24]], label [[LAND_RHS25:%.*]], label [[LAND_END28:%.*]] @@ -3691,19 +3791,19 @@ int main() { // CHECK1-NEXT: [[CONV29:%.*]] = zext i1 [[TMP35]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP22]], i32 noundef [[CONV29]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP22]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP22]]) #[[ATTR5]] -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP22]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP9]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[T_VAR17]], align 4 // CHECK1-NEXT: [[TMP37:%.*]] = atomicrmw min ptr [[TMP3]], i32 [[TMP36]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR16]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR16]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v.omp_outlined.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -3746,7 +3846,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP22]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP15]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] @@ -3764,7 +3864,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEanERKS0_ -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 @@ -3775,7 +3875,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEcviEv -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3784,17 +3884,17 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v.omp_outlined.13 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3821,12 +3921,12 @@ int main() { // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -3865,10 +3965,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP2]], i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -3931,12 +4031,12 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP6]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP6]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP6]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v.omp_outlined.13.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -3963,7 +4063,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v.omp_outlined.14 -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(168) [[ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(168) [[ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3980,10 +4080,10 @@ int main() { // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[ARR4:%.*]] = alloca [40 x %struct.S.0], align 16 +// CHECK1-NEXT: [[ARR4:%.*]] = alloca [40 x [[STRUCT_S_0:%.*]]], align 16 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[REF_TMP20:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -3992,21 +4092,21 @@ int main() { // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP5]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [42 x %struct.S.0], ptr [[TMP0]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [42 x %struct.S.0], ptr [[TMP0]], i64 0, i64 40 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [40 x %struct.S.0], ptr [[ARR4]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [42 x [[STRUCT_S_0]]], ptr [[TMP0]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds nuw [42 x [[STRUCT_S_0]]], ptr [[TMP0]], i64 0, i64 40 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [40 x [[STRUCT_S_0]]], ptr [[ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 40 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] @@ -4056,10 +4156,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP20]], ptr [[ARRAYIDX6]], align 4 -// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP3]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP3]], i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP22]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -4096,7 +4196,7 @@ int main() { // CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CALL]], [[CALL11]] // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[ADD12]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST10]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT13]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST10]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE14:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT13]], [[TMP31]] @@ -4113,14 +4213,14 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST19:%.*]] = phi ptr [ [[ARRAYIDX]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT24:%.*]], [[OMP_ARRAYCPY_BODY17]] ] // CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4 -// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB3]], i32 [[TMP34]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB4]], i32 [[TMP34]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[CALL21:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST19]]) // CHECK1-NEXT: [[CALL22:%.*]] = call noundef i32 @_ZN1SIiEcviEv(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST18]]) // CHECK1-NEXT: [[ADD23:%.*]] = add nsw i32 [[CALL21]], [[CALL22]] // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP20]], i32 noundef [[ADD23]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST19]], ptr align 4 [[REF_TMP20]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP20]]) #[[ATTR5]] -// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP34]], ptr @.gomp_critical_user_.atomic_reduction.var) +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP20]]) #[[ATTR2]] +// CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB4]], i32 [[TMP34]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT24]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST19]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT25]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST18]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE26:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT24]], [[TMP32]] @@ -4129,24 +4229,24 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP29]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: [[ARRAY_BEGIN28:%.*]] = getelementptr inbounds [40 x %struct.S.0], ptr [[ARR4]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN28:%.*]] = getelementptr inbounds [40 x [[STRUCT_S_0]]], ptr [[ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN28]], i64 40 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[DOTOMP_REDUCTION_DEFAULT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN28]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE29:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done29: // CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 -// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP37]]) +// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP37]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiLi42EET_v.omp_outlined.14.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR6]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -4170,7 +4270,7 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL2]] // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[ADD]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] @@ -4180,7 +4280,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4193,7 +4293,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 @@ -4211,7 +4311,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4219,9 +4319,127 @@ int main() { // CHECK1-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@main +// CHECK3-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { // CHECK3-NEXT: entry: +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 0, ptr @_Z21reductionArrayElementv.omp_outlined) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv.omp_outlined +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[G_ARR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 +// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK3-NEXT: store i32 0, ptr [[G_ARR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = sdiv exact i64 sub (i64 ptrtoint (ptr @g_arr to i64), i64 ptrtoint (ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1) to i64)), ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) +// CHECK3-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[G_ARR]], i64 [[TMP0]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK3: cond.true: +// CHECK3-NEXT: br label [[COND_END:%.*]] +// CHECK3: cond.false: +// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: br label [[COND_END]] +// CHECK3: cond.end: +// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK3: omp.inner.for.cond: +// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK3: omp.inner.for.body: +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 1 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] +// CHECK3-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK3: omp.body.continue: +// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK3: omp.inner.for.inc: +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK3: omp.inner.for.end: +// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK3: omp.loop.exit: +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) +// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK3-NEXT: store ptr [[G_ARR]], ptr [[TMP13]], align 8 +// CHECK3-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z21reductionArrayElementv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP14]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK3-NEXT: ] +// CHECK3: .omp.reduction.case1: +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[G_ARR]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK3-NEXT: store i32 [[ADD4]], ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP3]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK3: .omp.reduction.case2: +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[G_ARR]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = atomicrmw add ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), i32 [[TMP17]] monotonic, align 4 +// CHECK3-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP3]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK3: .omp.reduction.default: +// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv.omp_outlined.omp.reduction.reduction_func +// CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK3-NEXT: entry: +// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] +// CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 +// CHECK3-NEXT: ret void +// +// +// CHECK3-LABEL: define {{[^@]+}}@main +// CHECK3-SAME: () #[[ATTR5:[0-9]+]] { +// CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -4229,9 +4447,127 @@ int main() { // CHECK3-NEXT: ret i32 0 // // -// CHECK4-LABEL: define {{[^@]+}}@main +// CHECK4-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv // CHECK4-SAME: () #[[ATTR1:[0-9]+]] { // CHECK4-NEXT: entry: +// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 0, ptr @_Z21reductionArrayElementv.omp_outlined) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv.omp_outlined +// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[G_ARR:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 +// CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// CHECK4-NEXT: store i32 0, ptr [[G_ARR]], align 4 +// CHECK4-NEXT: [[TMP0:%.*]] = sdiv exact i64 sub (i64 ptrtoint (ptr @g_arr to i64), i64 ptrtoint (ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1) to i64)), ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) +// CHECK4-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[G_ARR]], i64 [[TMP0]] +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9 +// CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK4: cond.true: +// CHECK4-NEXT: br label [[COND_END:%.*]] +// CHECK4: cond.false: +// CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: br label [[COND_END]] +// CHECK4: cond.end: +// CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] +// CHECK4-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// CHECK4-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// CHECK4: omp.inner.for.cond: +// CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] +// CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK4: omp.inner.for.body: +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 1 +// CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP10]] +// CHECK4-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4 +// CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK4: omp.body.continue: +// CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// CHECK4: omp.inner.for.inc: +// CHECK4-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK4-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] +// CHECK4: omp.inner.for.end: +// CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// CHECK4: omp.loop.exit: +// CHECK4-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]]) +// CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK4-NEXT: store ptr [[G_ARR]], ptr [[TMP13]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z21reductionArrayElementv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK4-NEXT: switch i32 [[TMP14]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] +// CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] +// CHECK4-NEXT: ] +// CHECK4: .omp.reduction.case1: +// CHECK4-NEXT: [[TMP15:%.*]] = load i32, ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), align 4 +// CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[G_ARR]], align 4 +// CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK4-NEXT: store i32 [[ADD4]], ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), align 4 +// CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP3]], ptr @.gomp_critical_user_.reduction.var) +// CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK4: .omp.reduction.case2: +// CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[G_ARR]], align 4 +// CHECK4-NEXT: [[TMP18:%.*]] = atomicrmw add ptr getelementptr inbounds ([10 x i32], ptr @g_arr, i64 0, i64 1), i32 [[TMP17]] monotonic, align 4 +// CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP3]], ptr @.gomp_critical_user_.reduction.var) +// CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] +// CHECK4: .omp.reduction.default: +// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@_Z21reductionArrayElementv.omp_outlined.omp.reduction.reduction_func +// CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK4-NEXT: entry: +// CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK4-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 +// CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 +// CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] +// CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 +// CHECK4-NEXT: ret void +// +// +// CHECK4-LABEL: define {{[^@]+}}@main +// CHECK4-SAME: () #[[ATTR6:[0-9]+]] { +// CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds nuw ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8 @@ -4240,18 +4576,18 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke -// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] { +// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR7:[0-9]+]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8 // CHECK4-NEXT: store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8 -// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined) +// CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 0, ptr @__main_block_invoke.omp_outlined) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined -// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -4270,19 +4606,19 @@ int main() { // CHECK4-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [2 x ptr], align 8 // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr @g1, align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr @g1, align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK4-NEXT: store double 0.000000e+00, ptr [[G]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr @g1, align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr @g1, align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store double 0.000000e+00, ptr [[G1]], align 8 // CHECK4-NEXT: store ptr [[G1]], ptr [[_TMP2]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK4-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] @@ -4308,7 +4644,7 @@ int main() { // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK4-NEXT: store double 1.000000e+00, ptr [[G]], align 8 -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store volatile double 1.000000e+00, ptr [[TMP10]], align 8 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr }>, ptr [[BLOCK]], i32 0, i32 0 // CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_ISA]], align 8 @@ -4324,7 +4660,7 @@ int main() { // CHECK4-NEXT: [[TMP11:%.*]] = load volatile double, ptr [[G]], align 8 // CHECK4-NEXT: store volatile double [[TMP11]], ptr [[BLOCK_CAPTURED]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr }>, ptr [[BLOCK]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP12]], ptr [[BLOCK_CAPTURED4]], align 8 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 // CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 @@ -4345,7 +4681,7 @@ int main() { // CHECK4-NEXT: store ptr [[G]], ptr [[TMP16]], align 8 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 1 // CHECK4-NEXT: store ptr [[G1]], ptr [[TMP17]], align 8 -// CHECK4-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 2, i64 16, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @__main_block_invoke.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK4-NEXT: [[TMP18:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB2]], i32 [[TMP3]], i32 2, i64 16, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @__main_block_invoke.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) // CHECK4-NEXT: switch i32 [[TMP18]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK4-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK4-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] @@ -4369,12 +4705,12 @@ int main() { // CHECK4-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP3]], ptr @.gomp_critical_user_.reduction.var) // CHECK4-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK4: .omp.reduction.default: -// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]]) +// CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]]) // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@g1_block_invoke -// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] { +// CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR7]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: [[BLOCK_ADDR:%.*]] = alloca ptr, align 8 @@ -4383,13 +4719,13 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 // CHECK4-NEXT: store double 2.000000e+00, ptr [[BLOCK_CAPTURE_ADDR]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR1:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, ptr }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store double 2.000000e+00, ptr [[TMP0]], align 8 // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined.omp.reduction.reduction_func -// CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { +// CHECK4-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4]] { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp index 7d467293d0c8f..7b7dff4b92d9e 100644 --- a/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp @@ -48,19 +48,19 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK1-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [[STRUCT_S:%.*]]], align 16 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x %struct.kmp_taskred_input_t], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x [[STRUCT_KMP_TASKRED_INPUT_T:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x %struct.kmp_taskred_input_t.0], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_6:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -76,8 +76,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP5]], align 8 @@ -91,7 +91,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb., ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 1 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 1 @@ -106,7 +106,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..2, ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP17]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 2 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 2 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP18]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 1 @@ -124,8 +124,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP25:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 3, ptr [[DOTRD_INPUT_]]) // CHECK1-NEXT: store ptr [[TMP25]], ptr [[DOTTASK_RED_]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP26]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP27]], align 8 @@ -139,7 +139,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..6, ptr [[TMP31]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 1 @@ -164,13 +164,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP43]]) -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -280,8 +280,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP2]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -300,13 +300,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP1]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -314,12 +314,12 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -341,7 +341,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] @@ -359,7 +359,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[AGG_RESULT]], ptr [[RESULT_PTR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK1-NEXT: call void @_ZN1SC1ERKS_(ptr nonnull align 4 dereferenceable(4) [[AGG_RESULT]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // @@ -451,11 +451,11 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_1]], ptr [[DOTTASK_RED__ADDR2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8, !nonnull [[META3]], !align [[META6:![0-9]+]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8, !nonnull [[META3]], !align [[META6]] // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP6]]) @@ -560,55 +560,55 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META18:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: call void [[TMP22]](ptr [[TMP23]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]] -// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP28]], ptr [[TMP27]], ptr [[TMP26]]) // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8 +// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP32:%.*]] = mul nuw i64 [[TMP21]], 2 // CHECK1-NEXT: [[TMP33:%.*]] = udiv exact i64 [[TMP32]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP34:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP28]], ptr @{{reduction_size[.].+[.]}}) // CHECK1-NEXT: store i64 [[TMP33]], ptr [[TMP34]], align 8 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP25]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP28]], ptr [[TMP35]], ptr [[TMP31]]) -// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP37]] to i32 -// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK1: omp.inner.for.cond.i: -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP38]] to i64 -// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP39]] // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: omp.inner.for.body.i: -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] +// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP29]], align 4 // CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP41]] to i64 // CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i16, ptr [[TMP36]], i64 [[IDXPROM_I]] @@ -617,9 +617,9 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP29]], align 4 // CHECK1-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], [[CONV3_I]] // CHECK1-NEXT: store i32 [[ADD4_I]], ptr [[TMP29]], align 4 -// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[ADD5_I:%.*]] = add nsw i32 [[TMP44]], 1 -// CHECK1-NEXT: store i32 [[ADD5_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[ADD5_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK1: .omp_outlined..exit: // CHECK1-NEXT: ret i32 0 @@ -637,7 +637,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp b/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp index b0d00c5f539b1..5fb788dd45e32 100644 --- a/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp @@ -48,19 +48,19 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK1-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [[STRUCT_S:%.*]]], align 16 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x %struct.kmp_taskred_input_t], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x [[STRUCT_KMP_TASKRED_INPUT_T:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x %struct.kmp_taskred_input_t.0], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_6:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -76,8 +76,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP5]], align 8 @@ -91,7 +91,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb., ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 1 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 1 @@ -106,7 +106,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..2, ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP17]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 2 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 2 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP18]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 1 @@ -124,8 +124,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP25:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 3, ptr [[DOTRD_INPUT_]]) // CHECK1-NEXT: store ptr [[TMP25]], ptr [[DOTTASK_RED_]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP26]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP27]], align 8 @@ -139,7 +139,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..6, ptr [[TMP31]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 1 @@ -164,13 +164,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP43]]) -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -280,8 +280,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP2]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -300,13 +300,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP1]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -314,12 +314,12 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -341,7 +341,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] @@ -359,7 +359,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[AGG_RESULT]], ptr [[RESULT_PTR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK1-NEXT: call void @_ZN1SC1ERKS_(ptr nonnull align 4 dereferenceable(4) [[AGG_RESULT]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // @@ -451,11 +451,11 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_1]], ptr [[DOTTASK_RED__ADDR2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8, !nonnull [[META3]], !align [[META6:![0-9]+]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8, !nonnull [[META3]], !align [[META6]] // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP6]]) @@ -560,67 +560,67 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META18:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: call void [[TMP22]](ptr [[TMP23]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]] -// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP28]], ptr [[TMP27]], ptr [[TMP26]]) // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8 +// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP32:%.*]] = mul nuw i64 [[TMP21]], 2 // CHECK1-NEXT: [[TMP33:%.*]] = udiv exact i64 [[TMP32]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP34:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP28]], ptr @{{reduction_size[.].+[.]}}) // CHECK1-NEXT: store i64 [[TMP33]], ptr [[TMP34]], align 8 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP25]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP28]], ptr [[TMP35]], ptr [[TMP31]]) -// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP37]] to i32 -// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK1: omp.inner.for.cond.i: -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19:![0-9]+]] // CHECK1-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP38]] to i64 -// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP39]] // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: omp.inner.for.body.i: -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP41]] to i64 // CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i16, ptr [[TMP36]], i64 [[IDXPROM_I]] -// CHECK1-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX_I]], align 2, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX_I]], align 2, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[CONV3_I:%.*]] = sext i16 [[TMP42]] to i32 -// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], [[CONV3_I]] -// CHECK1-NEXT: store i32 [[ADD4_I]], ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store i32 [[ADD4_I]], ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[ADD5_I:%.*]] = add nsw i32 [[TMP44]], 1 -// CHECK1-NEXT: store i32 [[ADD5_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK1: .omp_outlined..exit: // CHECK1-NEXT: ret i32 0 // @@ -637,7 +637,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -677,7 +677,7 @@ int main(int argc, char **argv) { // CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK3-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [[STRUCT_S:%.*]]], align 16 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTTASK_RED_:%.*]] = alloca ptr, align 8 @@ -690,8 +690,8 @@ int main(int argc, char **argv) { // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK3-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -744,13 +744,13 @@ int main(int argc, char **argv) { // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]]) -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 5 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -769,12 +769,12 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK3-NEXT: ret void // // @@ -790,7 +790,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/parallel_copyin_codegen.cpp b/clang/test/OpenMP/parallel_copyin_codegen.cpp index 74e57bf53ed87..fa89a42fe4b79 100644 --- a/clang/test/OpenMP/parallel_copyin_codegen.cpp +++ b/clang/test/OpenMP/parallel_copyin_codegen.cpp @@ -219,7 +219,7 @@ void foo() { // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR2:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE5s_arr acquire, align 8 // CHECK1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] @@ -255,7 +255,7 @@ void foo() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @main.omp_outlined.3) // CHECK1-NEXT: [[CALL6:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL6]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP8]] // @@ -282,12 +282,12 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -328,7 +328,7 @@ void foo() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -344,7 +344,7 @@ void foo() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @_ZZ4mainE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ4mainE5s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -368,7 +368,7 @@ void foo() { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -391,8 +391,8 @@ void foo() { // CHECK1-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3vec, i64 8, ptr @_ZZ4mainE3vec.cache.) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP6]], ptr align 4 @_ZZ4mainE3vec, i64 8, i1 false) // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5s_arr, i64 8, ptr @_ZZ4mainE5s_arr.cache.) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP7]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP7]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK1: omp.arraycpy.body: @@ -416,7 +416,7 @@ void foo() { // CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3var, i64 4, ptr @_ZZ4mainE3var.cache.) // CHECK1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5s_arr, i64 8, ptr @_ZZ4mainE5s_arr.cache.) -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP14]], i64 0, i64 0 // CHECK1-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) // CHECK1-NEXT: ret void // @@ -455,7 +455,7 @@ void foo() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ5tmainIiET_vE5s_arr acquire, align 8 // CHECK1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]] @@ -489,7 +489,7 @@ void foo() { // CHECK1: init.end5: // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined.9) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: ret i32 0 // // @@ -509,7 +509,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -558,12 +558,12 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -604,7 +604,7 @@ void foo() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -620,7 +620,7 @@ void foo() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S_0:%.*]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ5tmainIiET_vE5s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -644,7 +644,7 @@ void foo() { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -667,8 +667,8 @@ void foo() { // CHECK1-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3vec, i64 8, ptr @_ZZ5tmainIiET_vE3vec.cache.) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP6]], ptr align 128 @_ZZ5tmainIiET_vE3vec, i64 8, i1 false) // CHECK1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 8, ptr @_ZZ5tmainIiET_vE5s_arr.cache.) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP7]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP7]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP8]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK1: omp.arraycpy.body: @@ -692,7 +692,7 @@ void foo() { // CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 128 // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3var, i64 4, ptr @_ZZ5tmainIiET_vE3var.cache.) // CHECK1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 8, ptr @_ZZ5tmainIiET_vE5s_arr.cache.) -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP14]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP14]], i64 0, i64 0 // CHECK1-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) // CHECK1-NEXT: ret void // @@ -734,7 +734,7 @@ void foo() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -865,8 +865,8 @@ void foo() { // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_ST:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -900,7 +900,7 @@ void foo() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] +// CHECK5-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -908,12 +908,12 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]] +// CHECK5-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR1]] // CHECK5-NEXT: ret void // // @@ -926,7 +926,7 @@ void foo() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_ST:%.*]], ptr @_ZZ10array_funcvE1s, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] +// CHECK5-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ10array_funcvE1s // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -949,8 +949,8 @@ void foo() { // CHECK5: copyin.not.master: // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 @_ZZ10array_funcvE1a, i64 8, i1 false) // CHECK5-NEXT: [[TMP5:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ10array_funcvE1s, i64 16, ptr @_ZZ10array_funcvE1s.cache.) -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP5]], i32 0, i32 0 -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_ST:%.*]]], ptr [[TMP5]], i32 0, i32 0 +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK5: omp.arraycpy.body: @@ -993,7 +993,7 @@ void foo() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1011,7 +1011,7 @@ void foo() { // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE5s_arr, align 1 // CHECK11-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]] @@ -1040,7 +1040,7 @@ void foo() { // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @main.omp_outlined.1, ptr [[TMP8]]) // CHECK11-NEXT: [[CALL4:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL4]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP9]] // @@ -1067,12 +1067,12 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK11-NEXT: ret void // // @@ -1098,7 +1098,7 @@ void foo() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @_ZZ4mainE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ4mainE5s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -1120,10 +1120,10 @@ void foo() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK11-NEXT: [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var) // CHECK11-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK11-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP4]] to i64 @@ -1135,8 +1135,8 @@ void foo() { // CHECK11-NEXT: [[TMP9:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3vec) // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP9]], ptr align 4 [[TMP1]], i64 8, i1 false) // CHECK11-NEXT: [[TMP10:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP10]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP10]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP11]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK11: omp.arraycpy.body: @@ -1162,7 +1162,7 @@ void foo() { // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3var) // CHECK11-NEXT: [[TMP19:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr) -// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP19]], i64 0, i64 0 +// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP19]], i64 0, i64 0 // CHECK11-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]]) // CHECK11-NEXT: ret void // @@ -1176,7 +1176,7 @@ void foo() { // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK11-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var) // CHECK11-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK11-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64 @@ -1205,7 +1205,7 @@ void foo() { // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK11-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ5tmainIiET_vE5s_arr, align 8 // CHECK11-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 // CHECK11-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]] @@ -1232,7 +1232,7 @@ void foo() { // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]]) // CHECK11-NEXT: [[TMP8:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var) // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.3, ptr [[TMP8]]) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK11-NEXT: ret i32 0 // // @@ -1251,7 +1251,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1299,12 +1299,12 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK11-NEXT: ret void // // @@ -1330,7 +1330,7 @@ void foo() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S_0:%.*]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ5tmainIiET_vE5s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -1352,10 +1352,10 @@ void foo() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK11-NEXT: [[TMP4:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var) // CHECK11-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK11-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[TMP4]] to i64 @@ -1367,8 +1367,8 @@ void foo() { // CHECK11-NEXT: [[TMP9:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3vec) // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP9]], ptr align 128 [[TMP1]], i64 8, i1 false) // CHECK11-NEXT: [[TMP10:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP10]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP10]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP11]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK11: omp.arraycpy.body: @@ -1394,7 +1394,7 @@ void foo() { // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 128 // CHECK11-NEXT: [[TMP18:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3var) // CHECK11-NEXT: [[TMP19:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr) -// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP19]], i64 0, i64 0 +// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP19]], i64 0, i64 0 // CHECK11-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]]) // CHECK11-NEXT: ret void // @@ -1408,7 +1408,7 @@ void foo() { // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK11-NEXT: [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var) // CHECK11-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK11-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64 @@ -1439,7 +1439,7 @@ void foo() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1517,7 +1517,7 @@ void foo() { // CHECK14-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK14-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK14-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 -// CHECK14-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 +// CHECK14-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK14-NEXT: [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g) // CHECK14-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK14-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64 @@ -1600,7 +1600,7 @@ void foo() { // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_ST:%.*]], ptr @_ZZ10array_funcvE1s, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ10array_funcvE1s // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done1: @@ -1608,12 +1608,12 @@ void foo() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK15-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK15-NEXT: ret void // // @@ -1628,8 +1628,8 @@ void foo() { // CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK15-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK15-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 -// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK15-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]] +// CHECK15-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META4]], !align [[META5]] // CHECK15-NEXT: [[TMP2:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ10array_funcvE1a) // CHECK15-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK15-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP2]] to i64 @@ -1638,8 +1638,8 @@ void foo() { // CHECK15: copyin.not.master: // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[TMP0]], i64 8, i1 false) // CHECK15-NEXT: [[TMP6:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @_ZZ10array_funcvE1s) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP6]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_ST:%.*]]], ptr [[TMP6]], i32 0, i32 0 +// CHECK15-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK15: omp.arraycpy.body: @@ -1684,7 +1684,7 @@ void foo() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1729,7 +1729,7 @@ void foo() { // CHECK16-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK16-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK16-NEXT: store ptr [[T]], ptr [[T_ADDR]], align 8 -// CHECK16-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8 +// CHECK16-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK16-NEXT: [[TMP1:%.*]] = call ptr @_ZTW1t() // CHECK16-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK16-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64 @@ -1762,7 +1762,7 @@ void foo() { // CHECK16-NEXT: entry: // CHECK16-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1 // CHECK16-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK16-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF5:![0-9]+]] +// CHECK16-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF7:![0-9]+]] // CHECK16: init: // CHECK16-NEXT: store i8 1, ptr @__tls_guard, align 1 // CHECK16-NEXT: call void @__cxx_global_var_init() diff --git a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp index 441e809dc59e5..4b95f8764dd91 100644 --- a/clang/test/OpenMP/parallel_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_firstprivate_codegen.cpp @@ -247,7 +247,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 @@ -276,18 +276,18 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i32 [[TMP5]]) // CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP7]] // @@ -339,9 +339,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 @@ -354,7 +354,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -363,7 +363,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -371,21 +371,21 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK1-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -418,22 +418,22 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -464,7 +464,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i32, align 4 @@ -485,18 +485,18 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_CASTED1]], align 4 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.2, i32 [[TMP3]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP5]] // @@ -668,7 +668,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -677,7 +677,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -728,9 +728,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 @@ -742,7 +742,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META4]], !align [[META5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i32 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -751,7 +751,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -759,20 +759,20 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -795,12 +795,12 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -907,7 +907,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1427,7 +1427,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 @@ -1456,18 +1456,18 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @main.omp_outlined.1, i64 [[TMP5]]) // CHECK9-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP7]] // @@ -1519,9 +1519,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -1534,7 +1534,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1543,7 +1543,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1551,21 +1551,21 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9: omp.arraycpy.done3: // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false) // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -1598,22 +1598,22 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1644,7 +1644,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[T_VAR_CASTED1:%.*]] = alloca i64, align 8 @@ -1665,18 +1665,18 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[T_VAR_CASTED1]], align 8 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.2, i64 [[TMP3]]) // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP5]] // @@ -1848,7 +1848,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1857,7 +1857,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1908,9 +1908,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -1922,7 +1922,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1931,7 +1931,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1939,20 +1939,20 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9: omp.arraycpy.done3: // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -1975,12 +1975,12 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -2087,7 +2087,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/parallel_for_linear_codegen.cpp b/clang/test/OpenMP/parallel_for_linear_codegen.cpp index 15eb0dfa42af5..6b1ec7896f3b8 100644 --- a/clang/test/OpenMP/parallel_for_linear_codegen.cpp +++ b/clang/test/OpenMP/parallel_for_linear_codegen.cpp @@ -101,7 +101,7 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 2, ptr @main.omp_outlined, ptr [[PVAR]], ptr [[LVAR]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP0]] // @@ -138,8 +138,8 @@ int main() { // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[PVAR]], ptr [[PVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[LVAR]], ptr [[LVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTLINEAR_START]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP1]], align 8 @@ -230,17 +230,17 @@ int main() { // CHECK1-NEXT: store ptr [[F]], ptr [[PVAR]], align 8 // CHECK1-NEXT: store i32 0, ptr [[LVAR]], align 4 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[PVAR]], ptr [[LVAR]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -287,8 +287,8 @@ int main() { // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[PVAR]], ptr [[PVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[LVAR]], ptr [[LVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[LVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META7:![0-9]+]] // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTLINEAR_START]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 4 @@ -368,12 +368,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -389,7 +389,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -398,7 +398,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -456,7 +456,7 @@ int main() { // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START]], align 4 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 diff --git a/clang/test/OpenMP/parallel_master_codegen.cpp b/clang/test/OpenMP/parallel_master_codegen.cpp index c2fc00661a6fb..65bc0d9156e0e 100644 --- a/clang/test/OpenMP/parallel_master_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_codegen.cpp @@ -382,7 +382,7 @@ void parallel_master_allocate() { // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP2]]) @@ -448,7 +448,7 @@ void parallel_master_allocate() { // CHECK17-NEXT: store i32 [[TMP2]], ptr [[Y_CASTED1]], align 4 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[Y_CASTED1]], align 8 // CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 3, ptr @_Z36parallel_master_default_firstprivatev.omp_outlined, ptr [[A]], i64 [[TMP1]], i64 [[TMP3]]) -// CHECK17-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] +// CHECK17-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[A]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: ret void // // @@ -476,7 +476,7 @@ void parallel_master_allocate() { // CHECK17-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK17-NEXT: store i64 [[Y]], ptr [[Y_ADDR]], align 8 // CHECK17-NEXT: store i64 [[Y1]], ptr [[Y_ADDR2]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[A3]], ptr align 4 [[TMP0]], i64 8, i1 false) // CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 @@ -501,17 +501,17 @@ void parallel_master_allocate() { // CHECK17-NEXT: call void @__kmpc_end_master(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK17-NEXT: br label [[OMP_IF_END]] // CHECK17: omp_if.end: -// CHECK17-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[A3]]) #[[ATTR3]] +// CHECK17-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[A3]]) #[[ATTR3]] // CHECK17-NEXT: ret void // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { +// CHECK17-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK17-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK17-NEXT: ret void // // @@ -529,7 +529,7 @@ void parallel_master_allocate() { // // // CHECK17-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK17-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { +// CHECK17-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -630,7 +630,7 @@ void parallel_master_allocate() { // CHECK29-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK29-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK29-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK29-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK29-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK29-NEXT: [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @a) // CHECK29-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK29-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64 diff --git a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp index dc34ec28fb37b..e7f2afbc6f587 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp @@ -198,7 +198,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -216,19 +216,19 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done1: -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP3]] // @@ -289,9 +289,9 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) @@ -310,8 +310,8 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP9]], i32 0, i32 1 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP13]], i32 0, i32 0 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i32 0, i32 0 -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP14]], i32 0, i32 0 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP15]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: @@ -428,51 +428,51 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META17:![0-9]+]] +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] +// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] // CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] // CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32 -// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK: omp.inner.for.cond.i: -// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] // CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP29]] // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK: omp.inner.for.body.i: -// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] -// CHECK-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] +// CHECK-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META17]] // CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP23]], align 4 // CHECK-NEXT: store i32 [[TMP31]], ptr [[TMP25]], align 4 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP24]], ptr align 8 [[TMP22]], i64 8, i1 false) // CHECK-NEXT: store i32 33, ptr [[TMP26]], align 4 -// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK: .omp_outlined..exit: // CHECK-NEXT: ret i32 0 @@ -495,9 +495,9 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP8]], i32 0, i32 0 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8, !nonnull [[META3]], !align [[META5]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: @@ -511,7 +511,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK: omp.arraycpy.done3: // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP8]], i32 0, i32 1 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP7]], i32 0, i32 1 -// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TMP13]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP15]], double noundef 0.000000e+00) // CHECK-NEXT: ret void // @@ -528,14 +528,14 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TMP5]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done2: @@ -544,12 +544,12 @@ void array_func(int n, float a[n], St s[2]) { // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // @@ -561,7 +561,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) @@ -577,19 +577,19 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done1: -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP3]] // @@ -616,7 +616,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 // CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 @@ -640,7 +640,7 @@ void array_func(int n, float a[n], St s[2]) { // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -704,9 +704,9 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) @@ -719,19 +719,19 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8 // CHECK-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, ptr @.omp_task_entry..3) -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP9]], i32 0, i32 0 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP10]], i32 0, i32 0 // CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 128 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) -// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP9]], i32 0, i32 2 -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP13]], i32 0, i32 0 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP9]], i32 0, i32 2 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP13]], i32 0, i32 0 // CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 128 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP13]], i32 0, i32 1 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP16]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 2 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP17]], i32 0, i32 0 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP13]], i32 0, i32 2 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP17]], i32 0, i32 0 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP18]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: @@ -743,7 +743,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done1: -// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 3 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP13]], i32 0, i32 3 // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP19]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0) // CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 3 // CHECK-NEXT: store ptr @.omp_task_destructor..5, ptr [[TMP20]], align 8 @@ -778,16 +778,16 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 // CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP5]], i32 0, i32 0 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 1 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 1 // CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 2 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 2 // CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 3 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 3 // CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 // CHECK-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 // CHECK-NEXT: ret void @@ -819,11 +819,11 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 2 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 // CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 @@ -834,49 +834,49 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 64 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) -// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META28:![0-9]+]] -// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META28]] -// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META28]] +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]] +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]] +// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]] // CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META28]] -// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META28]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META31]] +// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]] // CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32 -// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] +// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK: omp.inner.for.cond.i: -// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] // CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META28]] +// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]] // CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP28]] // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] // CHECK: omp.inner.for.body.i: -// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] -// CHECK-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META28]] +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] +// CHECK-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META31]] // CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP22]], align 128 // CHECK-NEXT: store i32 [[TMP30]], ptr [[TMP23]], align 4 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP24]], ptr align 4 [[TMP25]], i64 4, i1 false) -// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] // CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] +// CHECK-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK: .omp_outlined..1.exit: // CHECK-NEXT: ret i32 0 @@ -893,15 +893,15 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 0 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP8]], i32 0, i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP8]], i32 0, i32 2 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP9]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: @@ -913,9 +913,9 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done3: -// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP8]], i32 0, i32 3 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP8]], i32 0, i32 3 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP7]], i32 0, i32 1 -// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]], i32 noundef 0) // CHECK-NEXT: ret void // @@ -929,17 +929,17 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP2]], i32 0, i32 2 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP3]], i32 0, i32 3 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP2]], i32 0, i32 2 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP3]], i32 0, i32 3 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP5]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done2: @@ -948,12 +948,12 @@ void array_func(int n, float a[n], St s[2]) { // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // @@ -979,7 +979,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 @@ -1003,7 +1003,7 @@ void array_func(int n, float a[n], St s[2]) { // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1080,50 +1080,50 @@ void array_func(int n, float a[n], St s[2]) { // LAMBDA-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // LAMBDA-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // LAMBDA-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) -// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// LAMBDA-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// LAMBDA-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// LAMBDA-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// LAMBDA-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META17:![0-9]+]] +// LAMBDA-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] +// LAMBDA-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] // LAMBDA-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]] -// LAMBDA-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// LAMBDA-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] // LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32 -// LAMBDA-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// LAMBDA-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // LAMBDA: omp.inner.for.cond.i: -// LAMBDA-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// LAMBDA-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP25]] to i64 -// LAMBDA-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// LAMBDA-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] // LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP26]] // LAMBDA-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // LAMBDA: omp.inner.for.body.i: -// LAMBDA-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] -// LAMBDA-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias [[META14]] +// LAMBDA-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] +// LAMBDA-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias [[META17]] // LAMBDA-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8 // LAMBDA-NEXT: store i32 11, ptr [[TMP23]], align 4 -// LAMBDA-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 8, !noalias [[META14]] +// LAMBDA-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 8, !noalias [[META17]] // LAMBDA-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1 -// LAMBDA-NEXT: store ptr [[TMP23]], ptr [[TMP28]], align 8, !noalias [[META14]] +// LAMBDA-NEXT: store ptr [[TMP23]], ptr [[TMP28]], align 8, !noalias [[META17]] // LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) -// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP29]], 1 -// LAMBDA-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// LAMBDA-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I]] // LAMBDA: .omp_outlined..exit: // LAMBDA-NEXT: ret i32 0 @@ -1509,7 +1509,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1531,7 +1531,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX1]], ptr align 8 [[VAR]], i64 8, i1 false) // SIMD-ONLY0-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4 // SIMD-ONLY0-NEXT: br label [[FOR_INC:%.*]] @@ -1543,19 +1543,19 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0: for.end: // SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // SIMD-ONLY0-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]] -// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]] +// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY0: arraydestroy.body: // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY0: arraydestroy.done2: -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR3]] -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: ret i32 [[TMP4]] // @@ -1607,7 +1607,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) @@ -1628,7 +1628,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 128 // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 0 // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // SIMD-ONLY0-NEXT: br label [[FOR_INC:%.*]] // SIMD-ONLY0: for.inc: @@ -1638,30 +1638,30 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // SIMD-ONLY0: for.end: // SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR3]] -// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY0: arraydestroy.body: // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY0: arraydestroy.done2: -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: ret i32 [[TMP4]] // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: ret void // // @@ -1677,7 +1677,7 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1696,7 +1696,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 @@ -1759,12 +1759,12 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: ret void // // @@ -1790,7 +1790,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] // SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 @@ -1814,7 +1814,7 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1830,7 +1830,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1852,7 +1852,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // SIMD-ONLY1-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX1]], ptr align 8 [[VAR]], i64 8, i1 false) // SIMD-ONLY1-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4 // SIMD-ONLY1-NEXT: br label [[FOR_INC:%.*]] @@ -1864,19 +1864,19 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1: for.end: // SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // SIMD-ONLY1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]] -// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]] +// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY1: arraydestroy.body: // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY1: arraydestroy.done2: -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR3]] -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY1-NEXT: ret i32 [[TMP4]] // @@ -1928,7 +1928,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY1-NEXT: [[I:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) @@ -1949,7 +1949,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 128 // SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // SIMD-ONLY1-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 0 // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // SIMD-ONLY1-NEXT: br label [[FOR_INC:%.*]] // SIMD-ONLY1: for.inc: @@ -1959,30 +1959,30 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // SIMD-ONLY1: for.end: // SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR3]] -// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY1: arraydestroy.body: // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY1: arraydestroy.done2: -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY1-NEXT: ret i32 [[TMP4]] // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: ret void // // @@ -1998,7 +1998,7 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2017,7 +2017,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 @@ -2080,12 +2080,12 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: ret void // // @@ -2111,7 +2111,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] // SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 @@ -2135,7 +2135,7 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp index 8f7ffb571e06a..bd1f83dcf6597 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp @@ -205,7 +205,7 @@ void loop() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) @@ -219,19 +219,19 @@ void loop() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -276,10 +276,10 @@ void loop() { // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP5]]) @@ -304,8 +304,8 @@ void loop() { // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 40, i1 false) // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP13]], i32 0, i32 1 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP17]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP18]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP18]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -411,67 +411,67 @@ void loop() { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META17:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] // CHECK1-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]], ptr [[DOTLASTPRIV_PTR_ADDR2_I]], ptr [[DOTLASTPRIV_PTR_ADDR3_I]], ptr [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP26]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP26]], align 8, !nonnull [[META3]], !align [[META5]] +// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8 +// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8 +// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 4 -// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 -// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP40]] to i32 -// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK1: omp.inner.for.cond.i: -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK1-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP41]] to i64 -// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP42]] // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK1: omp.inner.for.body.i: -// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP43]], ptr [[I_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] +// CHECK1-NEXT: store i32 [[TMP43]], ptr [[I_I]], align 4, !noalias [[META17]] // CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP36]], align 4 // CHECK1-NEXT: store i32 [[TMP44]], ptr [[TMP38]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP37]], ptr align 8 [[TMP35]], i64 8, i1 false) // CHECK1-NEXT: store i32 33, ptr [[TMP39]], align 4 -// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP45]], 1 -// CHECK1-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK1: omp.inner.for.end.i: -// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] // CHECK1-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 // CHECK1-NEXT: br i1 [[TMP47]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: .omp.lastprivate.then.i: @@ -513,8 +513,8 @@ void loop() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP8]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP8]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -540,14 +540,14 @@ void loop() { // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: @@ -556,12 +556,12 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -573,7 +573,7 @@ void loop() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -585,19 +585,19 @@ void loop() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -628,7 +628,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -676,10 +676,10 @@ void loop() { // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP5]]) @@ -696,14 +696,14 @@ void loop() { // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP11]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP5]]) // CHECK1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP5]], i32 9, i64 256, i64 32, ptr @.omp_task_entry..3) -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP12]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP12]], i32 0, i32 0 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP13]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 128 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP15]], ptr align 8 [[AGG_CAPTURED]], i64 32, i1 false) -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP12]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP16]], i32 0, i32 2 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP17]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP12]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP16]], i32 0, i32 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP17]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -712,7 +712,7 @@ void loop() { // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP16]], i32 0, i32 3 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP16]], i32 0, i32 3 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]]) // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 3 // CHECK1-NEXT: store ptr @.omp_task_destructor..5, ptr [[TMP19]], align 8 @@ -747,16 +747,16 @@ void loop() { // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 1 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 1 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 2 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 3 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 3 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 // CHECK1-NEXT: ret void @@ -788,11 +788,11 @@ void loop() { // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 2 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 @@ -803,63 +803,63 @@ void loop() { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 64 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META28:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META28]] -// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META31:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META31]] // CHECK1-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]], ptr [[DOTLASTPRIV_PTR_ADDR2_I]], ptr [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP19]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8 -// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8 +// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8 +// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8 -// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META28]] -// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META31]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META31]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP37]] to i32 -// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK1: omp.inner.for.cond.i: -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] // CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP38]] to i64 -// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META31]] // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP39]] // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK1: omp.inner.for.body.i: -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] -// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META28]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] +// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META31]] // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP33]], align 128 // CHECK1-NEXT: store i32 [[TMP41]], ptr [[TMP34]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[TMP36]], i64 4, i1 false) -// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] +// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] // CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP42]], 1 -// CHECK1-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META28]] +// CHECK1-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META31]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK1: omp.inner.for.end.i: -// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META28]] +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META31]] // CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 // CHECK1-NEXT: br i1 [[TMP44]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] // CHECK1: .omp.lastprivate.then.i: @@ -893,14 +893,14 @@ void loop() { // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 64 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP7]], i32 0, i32 2 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP8]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP7]], i32 0, i32 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP8]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -909,7 +909,7 @@ void loop() { // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP7]], i32 0, i32 3 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP7]], i32 0, i32 3 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]]) // CHECK1-NEXT: ret void // @@ -923,17 +923,17 @@ void loop() { // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP2]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP3]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP3]], i32 0, i32 3 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP4]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP2]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP3]], i32 0, i32 3 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: @@ -942,12 +942,12 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -977,7 +977,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1054,56 +1054,56 @@ void loop() { // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK3-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META17:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] +// CHECK3-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] // CHECK3-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]] -// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 -// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] // CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32 -// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK3: omp.inner.for.cond.i: -// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK3-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK3-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK3-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] // CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP29]] // CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK3: omp.inner.for.body.i: -// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] -// CHECK3-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]] +// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] +// CHECK3-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META17]] // CHECK3-NEXT: store double 1.000000e+00, ptr [[TMP25]], align 8 // CHECK3-NEXT: store i32 11, ptr [[TMP26]], align 4 -// CHECK3-NEXT: store ptr [[TMP25]], ptr [[REF_TMP_I]], align 8, !noalias [[META14]] +// CHECK3-NEXT: store ptr [[TMP25]], ptr [[REF_TMP_I]], align 8, !noalias [[META17]] // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1 -// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8, !noalias [[META14]] +// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8, !noalias [[META17]] // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]) -// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK3-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK3-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK3: omp.inner.for.end.i: -// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] // CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 // CHECK3-NEXT: br i1 [[TMP34]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK3: .omp.lastprivate.then.i: @@ -1291,9 +1291,9 @@ void loop() { // CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] // CHECK4-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] // CHECK4-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]] -// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META15:![0-9]+]], !align [[META16:![0-9]+]] // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 +// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !nonnull [[META15]], !align [[META17:![0-9]+]] // CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] // CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] // CHECK4-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] @@ -1396,8 +1396,8 @@ void loop() { // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) @@ -1492,52 +1492,52 @@ void loop() { // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]]) // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK5-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META16:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META16]] +// CHECK5-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] // CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[TMP19]], align 8 -// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] // CHECK5-NEXT: call void [[TMP21]](ptr [[TMP22]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 -// CHECK5-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META16]] // CHECK5-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32 -// CHECK5-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK5-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK5: omp.inner.for.cond.i: -// CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK5-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK5-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK5-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META16]] // CHECK5-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP31]] // CHECK5-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK5: omp.inner.for.body.i: -// CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] -// CHECK5-NEXT: store i32 [[TMP32]], ptr [[I_I]], align 4, !noalias [[META14]] -// CHECK5-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] +// CHECK5-NEXT: store i32 [[TMP32]], ptr [[I_I]], align 4, !noalias [[META16]] +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK5-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP33]], 1 -// CHECK5-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK5-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK5: omp.inner.for.end.i: -// CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META16]] // CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK5-NEXT: br i1 [[TMP35]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK5: .omp.lastprivate.then.i: @@ -1587,7 +1587,7 @@ void loop() { // CHECK6-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK6-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK6-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP2]]) @@ -1672,52 +1672,52 @@ void loop() { // CHECK6-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK6-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK6-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]]) // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK6-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META16:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META16]] +// CHECK6-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] // CHECK6-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]]) #[[ATTR2:[0-9]+]] -// CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8 -// CHECK6-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK6-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META16]] // CHECK6-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32 -// CHECK6-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK6: omp.inner.for.cond.i: -// CHECK6-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: [[CONV1_I:%.*]] = sext i32 [[TMP25]] to i64 -// CHECK6-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META16]] // CHECK6-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV1_I]], [[TMP26]] // CHECK6-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK6: omp.inner.for.body.i: -// CHECK6-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] -// CHECK6-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias [[META14]] -// CHECK6-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] +// CHECK6-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias [[META16]] +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: [[ADD2_I:%.*]] = add nsw i32 [[TMP28]], 1 -// CHECK6-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: store i32 [[ADD2_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK6: omp.inner.for.end.i: -// CHECK6-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 // CHECK6-NEXT: br i1 [[TMP30]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK6: .omp.lastprivate.then.i: -// CHECK6-NEXT: store i32 10, ptr [[I_I]], align 4, !noalias [[META14]] -// CHECK6-NEXT: [[TMP31:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: store i32 10, ptr [[I_I]], align 4, !noalias [[META16]] +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: store i32 [[TMP31]], ptr [[TMP22]], align 4 // CHECK6-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK6: .omp_outlined..exit: diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp index d81e575b93b46..9287944db21f2 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp @@ -198,7 +198,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -216,19 +216,19 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done1: -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP3]] // @@ -289,9 +289,9 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) @@ -310,8 +310,8 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP9]], i32 0, i32 1 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP13]], i32 0, i32 0 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i32 0, i32 0 -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP14]], i32 0, i32 0 +// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP15]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: @@ -428,52 +428,52 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META17:![0-9]+]] +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] +// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] // CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META14]] -// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META17]] +// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] // CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32 -// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK: omp.inner.for.cond.i: -// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18:![0-9]+]] // CHECK-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP29]] // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK: omp.inner.for.body.i: -// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: store i32 [[TMP31]], ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP24]], ptr align 8 [[TMP22]], i64 8, i1 false), !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: store i32 33, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK-NEXT: store i32 [[TMP31]], ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP24]], ptr align 8 [[TMP22]], i64 8, i1 false), !llvm.access.group [[ACC_GRP18]] +// CHECK-NEXT: store i32 33, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // CHECK-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK: .omp_outlined..exit: // CHECK-NEXT: ret i32 0 // @@ -495,9 +495,9 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP8]], i32 0, i32 0 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8, !nonnull [[META3]], !align [[META5]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: @@ -511,7 +511,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK: omp.arraycpy.done3: // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP8]], i32 0, i32 1 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP7]], i32 0, i32 1 -// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK-NEXT: call void @_ZN1SIdEC1ERKS0_d(ptr noundef nonnull align 8 dereferenceable(8) [[TMP13]], ptr noundef nonnull align 8 dereferenceable(8) [[TMP15]], double noundef 0.000000e+00) // CHECK-NEXT: ret void // @@ -528,14 +528,14 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 // CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TMP5]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done2: @@ -544,12 +544,12 @@ void array_func(int n, float a[n], St s[2]) { // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // @@ -561,7 +561,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) @@ -577,19 +577,19 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 // CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], i64 [[TMP1]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done1: -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP3]] // @@ -616,7 +616,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 // CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 @@ -640,7 +640,7 @@ void array_func(int n, float a[n], St s[2]) { // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -704,9 +704,9 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) @@ -719,19 +719,19 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store ptr [[TMP2]], ptr [[TMP8]], align 8 // CHECK-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP4]]) // CHECK-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP4]], i32 9, i64 256, i64 16, ptr @.omp_task_entry..3) -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP9]], i32 0, i32 0 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP10]], i32 0, i32 0 // CHECK-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 128 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP12]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) -// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP9]], i32 0, i32 2 -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP13]], i32 0, i32 0 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP9]], i32 0, i32 2 +// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP13]], i32 0, i32 0 // CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP14]], align 128 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 1 +// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP13]], i32 0, i32 1 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP16]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 2 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP17]], i32 0, i32 0 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP13]], i32 0, i32 2 +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP17]], i32 0, i32 0 +// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP18]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: @@ -743,7 +743,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP18]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done1: -// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP13]], i32 0, i32 3 +// CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP13]], i32 0, i32 3 // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP19]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], i32 noundef 0) // CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP10]], i32 0, i32 3 // CHECK-NEXT: store ptr @.omp_task_destructor..5, ptr [[TMP20]], align 8 @@ -778,16 +778,16 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 // CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP5]], i32 0, i32 0 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 1 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 1 // CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 2 +// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 2 // CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 3 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 3 // CHECK-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 // CHECK-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 // CHECK-NEXT: ret void @@ -819,11 +819,11 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 2 // CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 // CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 @@ -834,50 +834,50 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 64 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) // CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) -// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META32]] -// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]]) +// CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) +// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META35:![0-9]+]] +// CHECK-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META35]] +// CHECK-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META35]] // CHECK-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] -// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META32]] -// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META32]] +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META35]] +// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META35]] // CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP26]] to i32 -// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]] +// CHECK-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]] // CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK: omp.inner.for.cond.i: -// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36:![0-9]+]] // CHECK-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP27]] to i64 -// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] // CHECK-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP28]] // CHECK-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] // CHECK: omp.inner.for.body.i: -// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP22]], align 128, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: store i32 [[TMP30]], ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP24]], ptr align 4 [[TMP25]], i64 4, i1 false), !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] +// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: store i32 [[TMP29]], ptr [[I_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP22]], align 128, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: store i32 [[TMP30]], ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP24]], ptr align 4 [[TMP25]], i64 4, i1 false), !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] // CHECK-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] +// CHECK-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK: .omp_outlined..1.exit: // CHECK-NEXT: ret i32 0 // @@ -893,15 +893,15 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 // CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 // CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP5]], i32 0, i32 0 // CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP8]], i32 0, i32 2 +// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP8]], i32 0, i32 2 // CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP9]], i32 0, i32 0 -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP9]], i32 0, i32 0 +// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // CHECK: omp.arraycpy.body: @@ -913,9 +913,9 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]] // CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]] // CHECK: omp.arraycpy.done3: -// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP8]], i32 0, i32 3 +// CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP8]], i32 0, i32 3 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP7]], i32 0, i32 1 -// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 +// CHECK-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK-NEXT: call void @_ZN1SIiEC1ERKS0_i(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]], i32 noundef 0) // CHECK-NEXT: ret void // @@ -929,17 +929,17 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 // CHECK-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP2]], i32 0, i32 2 -// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP3]], i32 0, i32 2 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP3]], i32 0, i32 3 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP2]], i32 0, i32 2 +// CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP3]], i32 0, i32 3 +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP5]]) #[[ATTR4]] +// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK: arraydestroy.body: // CHECK-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK: arraydestroy.done2: @@ -948,12 +948,12 @@ void array_func(int n, float a[n], St s[2]) { // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK-NEXT: ret void // // @@ -979,7 +979,7 @@ void array_func(int n, float a[n], St s[2]) { // CHECK-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 @@ -1003,7 +1003,7 @@ void array_func(int n, float a[n], St s[2]) { // // // CHECK-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK-NEXT: entry: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1080,51 +1080,51 @@ void array_func(int n, float a[n], St s[2]) { // LAMBDA-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // LAMBDA-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // LAMBDA-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) -// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// LAMBDA-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// LAMBDA-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// LAMBDA-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// LAMBDA-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// LAMBDA-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META17:![0-9]+]] +// LAMBDA-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] +// LAMBDA-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] // LAMBDA-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]] -// LAMBDA-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// LAMBDA-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// LAMBDA-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META17]] +// LAMBDA-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] // LAMBDA-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP24]] to i32 -// LAMBDA-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// LAMBDA-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // LAMBDA: omp.inner.for.cond.i: -// LAMBDA-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// LAMBDA-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18:![0-9]+]] // LAMBDA-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP25]] to i64 -// LAMBDA-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // LAMBDA-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP26]] // LAMBDA-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // LAMBDA: omp.inner.for.body.i: -// LAMBDA-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: store i32 11, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// LAMBDA-NEXT: store i32 [[TMP27]], ptr [[I_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// LAMBDA-NEXT: store double 1.000000e+00, ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP18]] +// LAMBDA-NEXT: store i32 11, ptr [[TMP23]], align 4, !llvm.access.group [[ACC_GRP18]] +// LAMBDA-NEXT: store ptr [[TMP22]], ptr [[REF_TMP_I]], align 8, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // LAMBDA-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1 -// LAMBDA-NEXT: store ptr [[TMP23]], ptr [[TMP28]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// LAMBDA-NEXT: store ptr [[TMP23]], ptr [[TMP28]], align 8, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// LAMBDA-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP18]] +// LAMBDA-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // LAMBDA-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP29]], 1 -// LAMBDA-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// LAMBDA-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// LAMBDA-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP19:![0-9]+]] // LAMBDA: .omp_outlined..exit: // LAMBDA-NEXT: ret i32 0 // @@ -1509,7 +1509,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY0-NEXT: [[TMP:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 @@ -1545,7 +1545,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX2]], ptr align 8 [[VAR]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY0-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY0-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1560,19 +1560,19 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: store i32 10, ptr [[I]], align 4 // SIMD-ONLY0-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // SIMD-ONLY0-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]] -// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]] +// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY0: arraydestroy.body: // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY0: arraydestroy.done4: -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR3]] -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: ret i32 [[TMP7]] // @@ -1624,7 +1624,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY0-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // SIMD-ONLY0-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// SIMD-ONLY0-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // SIMD-ONLY0-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY0-NEXT: [[TMP:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 @@ -1659,7 +1659,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 0 // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY0-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // SIMD-ONLY0: omp.body.continue: @@ -1672,30 +1672,30 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0: omp.inner.for.end: // SIMD-ONLY0-NEXT: store i32 10, ptr [[I]], align 4 // SIMD-ONLY0-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR3]] -// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY0-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY0: arraydestroy.body: // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY0-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY0: arraydestroy.done4: -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY0-NEXT: ret i32 [[TMP7]] // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: ret void // // @@ -1711,7 +1711,7 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1730,7 +1730,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 @@ -1793,12 +1793,12 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// SIMD-ONLY0-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // SIMD-ONLY0-NEXT: ret void // // @@ -1824,7 +1824,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY0-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 // SIMD-ONLY0-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY0-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META9]], !align [[META11:![0-9]+]] // SIMD-ONLY0-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 @@ -1848,7 +1848,7 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY0-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY0-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1864,7 +1864,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // SIMD-ONLY1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 @@ -1900,7 +1900,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // SIMD-ONLY1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX2]], ptr align 8 [[VAR]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY1-NEXT: store i32 33, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1915,19 +1915,19 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: store i32 10, ptr [[I]], align 4 // SIMD-ONLY1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // SIMD-ONLY1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]] -// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR3:[0-9]+]] +// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY1: arraydestroy.body: // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY1: arraydestroy.done4: -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR3]] -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY1-NEXT: ret i32 [[TMP7]] // @@ -1979,7 +1979,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // SIMD-ONLY1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// SIMD-ONLY1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // SIMD-ONLY1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // SIMD-ONLY1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // SIMD-ONLY1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 @@ -2014,7 +2014,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // SIMD-ONLY1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 0 // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // SIMD-ONLY1: omp.body.continue: @@ -2027,30 +2027,30 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1: omp.inner.for.end: // SIMD-ONLY1-NEXT: store i32 10, ptr [[I]], align 4 // SIMD-ONLY1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR3]] -// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // SIMD-ONLY1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // SIMD-ONLY1: arraydestroy.body: // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // SIMD-ONLY1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD-ONLY1: arraydestroy.done4: -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // SIMD-ONLY1-NEXT: ret i32 [[TMP7]] // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: ret void // // @@ -2066,7 +2066,7 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2085,7 +2085,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: store double [[T]], ptr [[T_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load double, ptr [[F2]], align 8 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load double, ptr [[T_ADDR]], align 8 @@ -2148,12 +2148,12 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// SIMD-ONLY1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // SIMD-ONLY1-NEXT: ret void // // @@ -2179,7 +2179,7 @@ void array_func(int n, float a[n], St s[2]) { // SIMD-ONLY1-NEXT: store i32 [[T]], ptr [[T_ADDR]], align 4 // SIMD-ONLY1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // SIMD-ONLY1-NEXT: [[F:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0 -// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META9]], !align [[META11:![0-9]+]] // SIMD-ONLY1-NEXT: [[F2:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_ADDR]], align 4 @@ -2203,7 +2203,7 @@ void array_func(int n, float a[n], St s[2]) { // // // SIMD-ONLY1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// SIMD-ONLY1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // SIMD-ONLY1-NEXT: entry: // SIMD-ONLY1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp index b5d2053e54cc2..5a01e737d8a92 100644 --- a/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp @@ -205,7 +205,7 @@ void loop() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) @@ -219,19 +219,19 @@ void loop() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -276,10 +276,10 @@ void loop() { // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP5]]) @@ -304,8 +304,8 @@ void loop() { // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP16]], ptr align 8 [[AGG_CAPTURED]], i64 40, i1 false) // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP13]], i32 0, i32 1 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP17]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP18]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP18]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -411,67 +411,67 @@ void loop() { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META17:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] // CHECK1-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]], ptr [[DOTLASTPRIV_PTR_ADDR2_I]], ptr [[DOTLASTPRIV_PTR_ADDR3_I]], ptr [[DOTLASTPRIV_PTR_ADDR4_I]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8 +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[TMP24]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP26]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP26]], align 8, !nonnull [[META3]], !align [[META5]] +// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8 +// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8 +// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 4 -// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8 -// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR4_I]], align 8, !noalias [[META17]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP40]] to i32 -// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK1: omp.inner.for.cond.i: -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18:![0-9]+]] // CHECK1-NEXT: [[CONV5_I:%.*]] = sext i32 [[TMP41]] to i64 -// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV5_I]], [[TMP42]] // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK1: omp.inner.for.body.i: -// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: store i32 [[TMP43]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP36]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: store i32 [[TMP44]], ptr [[TMP38]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP37]], ptr align 8 [[TMP35]], i64 8, i1 false), !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: store i32 33, ptr [[TMP39]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: store i32 [[TMP43]], ptr [[I_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP36]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: store i32 [[TMP44]], ptr [[TMP38]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP37]], ptr align 8 [[TMP35]], i64 8, i1 false), !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: store i32 33, ptr [[TMP39]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // CHECK1-NEXT: [[ADD7_I:%.*]] = add nsw i32 [[TMP45]], 1 -// CHECK1-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD7_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK1: omp.inner.for.end.i: -// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] // CHECK1-NEXT: [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0 // CHECK1-NEXT: br i1 [[TMP47]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: .omp.lastprivate.then.i: @@ -513,8 +513,8 @@ void loop() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP7]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP8]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP8]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -540,14 +540,14 @@ void loop() { // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TMP5]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: @@ -556,12 +556,12 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -573,7 +573,7 @@ void loop() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -585,19 +585,19 @@ void loop() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -628,7 +628,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -676,10 +676,10 @@ void loop() { // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP5]]) @@ -696,14 +696,14 @@ void loop() { // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP11]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP5]]) // CHECK1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP5]], i32 9, i64 256, i64 32, ptr @.omp_task_entry..3) -// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP12]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP12]], i32 0, i32 0 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP13]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 128 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP15]], ptr align 8 [[AGG_CAPTURED]], i64 32, i1 false) -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP12]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP16]], i32 0, i32 2 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP17]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP12]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP16]], i32 0, i32 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP17]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -712,7 +712,7 @@ void loop() { // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP16]], i32 0, i32 3 +// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP16]], i32 0, i32 3 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]]) // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP13]], i32 0, i32 3 // CHECK1-NEXT: store ptr @.omp_task_destructor..5, ptr [[TMP19]], align 8 @@ -747,16 +747,16 @@ void loop() { // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP5]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 1 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 1 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 2 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP5]], i32 0, i32 3 +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP5]], i32 0, i32 3 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR4]], align 8 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8 // CHECK1-NEXT: ret void @@ -788,11 +788,11 @@ void loop() { // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 2 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 5 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 6 @@ -803,63 +803,63 @@ void loop() { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 64 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META32]] -// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META27:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META29:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META31:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META35:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map..2, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META35]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META35]] // CHECK1-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]], ptr [[DOTLASTPRIV_PTR_ADDR2_I]], ptr [[DOTLASTPRIV_PTR_ADDR3_I]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1:%.*]], ptr [[TMP19]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8 -// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 +// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8 +// CHECK1-NEXT: [[TMP28:%.*]] = load ptr, ptr [[TMP27]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8 +// CHECK1-NEXT: [[TMP30:%.*]] = load ptr, ptr [[TMP29]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_1]], ptr [[TMP19]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8 -// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META32]] +// CHECK1-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR2_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR3_I]], align 8, !noalias [[META35]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META35]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP37]] to i32 -// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]] +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK1: omp.inner.for.cond.i: -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36:![0-9]+]] // CHECK1-NEXT: [[CONV4_I:%.*]] = sext i32 [[TMP38]] to i64 -// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV4_I]], [[TMP39]] // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK1: omp.inner.for.body.i: -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] -// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP33]], align 128, !llvm.access.group [[ACC_GRP33]] -// CHECK1-NEXT: store i32 [[TMP41]], ptr [[TMP34]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[TMP36]], i64 4, i1 false), !llvm.access.group [[ACC_GRP33]] -// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP33]], align 128, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: store i32 [[TMP41]], ptr [[TMP34]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[TMP36]], i64 4, i1 false), !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] // CHECK1-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP42]], 1 -// CHECK1-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META32]], !llvm.access.group [[ACC_GRP33]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META35]], !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK1: omp.inner.for.end.i: -// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META32]] +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META35]] // CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 // CHECK1-NEXT: br i1 [[TMP44]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] // CHECK1: .omp.lastprivate.then.i: @@ -893,14 +893,14 @@ void loop() { // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTADDR2]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTADDR2]], align 4 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 64 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2]], ptr [[TMP3]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP7]], i32 0, i32 2 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP8]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3]], ptr [[TMP3]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP7]], i32 0, i32 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP8]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -909,7 +909,7 @@ void loop() { // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP7]], i32 0, i32 3 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP7]], i32 0, i32 3 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]]) // CHECK1-NEXT: ret void // @@ -923,17 +923,17 @@ void loop() { // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_2:%.*]], ptr [[TMP2]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3:%.*]], ptr [[TMP3]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_3]], ptr [[TMP3]], i32 0, i32 3 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP4]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP2]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2:%.*]], ptr [[TMP3]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_2]], ptr [[TMP3]], i32 0, i32 3 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP5]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: @@ -942,12 +942,12 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -977,7 +977,7 @@ void loop() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1054,56 +1054,56 @@ void loop() { // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK3-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META9:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META17:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] +// CHECK3-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META17]] // CHECK3-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR3:[0-9]+]] -// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 -// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK3-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META17]] +// CHECK3-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META17]] // CHECK3-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP27]] to i32 -// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK3-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]] // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK3: omp.inner.for.cond.i: -// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18:![0-9]+]] // CHECK3-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK3-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK3-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP29]] // CHECK3-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK3: omp.inner.for.body.i: -// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: store double 1.000000e+00, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: store i32 11, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: store ptr [[TMP25]], ptr [[REF_TMP_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: store double 1.000000e+00, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: store i32 11, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: store ptr [[TMP25]], ptr [[REF_TMP_I]], align 8, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP_I]], i32 0, i32 1 -// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP_I]]), !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK3-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK3-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META17]], !llvm.access.group [[ACC_GRP18]] +// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK3: omp.inner.for.end.i: -// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META17]] // CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 // CHECK3-NEXT: br i1 [[TMP34]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK3: .omp.lastprivate.then.i: @@ -1291,9 +1291,9 @@ void loop() { // CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] // CHECK4-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] // CHECK4-NEXT: call void [[TMP20]](ptr [[TMP21]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR4:[0-9]+]] -// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META15:![0-9]+]], !align [[META16:![0-9]+]] // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 +// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !nonnull [[META15]], !align [[META17:![0-9]+]] // CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] // CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] // CHECK4-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] @@ -1301,38 +1301,38 @@ void loop() { // CHECK4-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK4: omp.inner.for.cond.i: -// CHECK4-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK4-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP18:![0-9]+]] // CHECK4-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK4-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP29]] // CHECK4-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK4: omp.inner.for.body.i: -// CHECK4-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: store double 1.000000e+00, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: store i32 11, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: store i32 [[TMP30]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: store double 1.000000e+00, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: store i32 11, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: store ptr @_NSConcreteStackBlock, ptr [[BLOCK_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[BLOCK_FLAGS_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 1 -// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: store i32 1073741824, ptr [[BLOCK_FLAGS_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[BLOCK_RESERVED_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 2 -// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: store i32 0, ptr [[BLOCK_RESERVED_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[BLOCK_INVOKE_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 3 -// CHECK4-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: store ptr @_block_invoke, ptr [[BLOCK_INVOKE_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[BLOCK_DESCRIPTOR_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 4 -// CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: store ptr @__block_descriptor_tmp.1, ptr [[BLOCK_DESCRIPTOR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[BLOCK_CAPTURED_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 5 -// CHECK4-NEXT: [[TMP31:%.*]] = load volatile double, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: store volatile double [[TMP31]], ptr [[BLOCK_CAPTURED_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: [[TMP31:%.*]] = load volatile double, ptr [[TMP25]], align 8, !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: store volatile double [[TMP31]], ptr [[BLOCK_CAPTURED_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[BLOCK_CAPTURED3_I:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, double, i32 }>, ptr [[BLOCK_I]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: store i32 [[TMP32]], ptr [[BLOCK_CAPTURED3_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP26]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: store i32 [[TMP32]], ptr [[BLOCK_CAPTURED3_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK_I]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: call void [[TMP34]](ptr noundef [[BLOCK_I]]) #[[ATTR4]], !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK4-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: call void [[TMP34]](ptr noundef [[BLOCK_I]]) #[[ATTR4]], !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] // CHECK4-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP35]], 1 -// CHECK4-NEXT: store i32 [[ADD4_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK4-NEXT: store i32 [[ADD4_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP18]] +// CHECK4-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP19:![0-9]+]] // CHECK4: omp.inner.for.end.i: // CHECK4-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] // CHECK4-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 @@ -1396,8 +1396,8 @@ void loop() { // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store ptr [[S]], ptr [[S_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ADDR]], align 8 +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP4]]) @@ -1492,52 +1492,52 @@ void loop() { // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]]) // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK5-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK5-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META16:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META16]] +// CHECK5-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] // CHECK5-NEXT: [[TMP20:%.*]] = load i64, ptr [[TMP19]], align 8 -// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK5-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] // CHECK5-NEXT: call void [[TMP21]](ptr [[TMP22]], ptr [[DOTLASTPRIV_PTR_ADDR_I]], ptr [[DOTLASTPRIV_PTR_ADDR1_I]]) #[[ATTR2:[0-9]+]] // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 +// CHECK5-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 -// CHECK5-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK5-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTLASTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META16]] +// CHECK5-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META16]] // CHECK5-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP29]] to i32 -// CHECK5-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK5-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK5: omp.inner.for.cond.i: -// CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17:![0-9]+]] // CHECK5-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK5-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK5-NEXT: [[TMP31:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] // CHECK5-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP31]] // CHECK5-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK5: omp.inner.for.body.i: -// CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK5-NEXT: store i32 [[TMP32]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK5-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK5-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK5-NEXT: store i32 [[TMP32]], ptr [[I_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK5-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] // CHECK5-NEXT: [[ADD3_I:%.*]] = add nsw i32 [[TMP33]], 1 -// CHECK5-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK5: omp.inner.for.end.i: -// CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META16]] // CHECK5-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 // CHECK5-NEXT: br i1 [[TMP35]], label [[DOTOMP_LASTPRIVATE_THEN_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK5: .omp.lastprivate.then.i: @@ -1590,8 +1590,8 @@ void loop() { // CHECK6-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK6-NEXT: store ptr [[I]], ptr [[I_ADDR]], align 8 // CHECK6-NEXT: store ptr [[J]], ptr [[J_ADDR]], align 8 -// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 -// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[J_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK6-NEXT: [[TMP1:%.*]] = load ptr, ptr [[J_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK6-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB1]], i32 [[TMP3]]) @@ -1664,64 +1664,64 @@ void loop() { // CHECK6-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8 // CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META5:![0-9]+]]) // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK6-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK6-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META16:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store i64 [[TMP9]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store i64 [[TMP11]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store i64 [[TMP13]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store i32 [[TMP15]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META16]] +// CHECK6-NEXT: store ptr [[TMP17]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: [[TMP18:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] +// CHECK6-NEXT: [[TMP19:%.*]] = load ptr, ptr [[TMP18]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK6-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 -// CHECK6-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: store i32 [[TMP20]], ptr [[DOTLINEAR_START_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP18]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK6-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -// CHECK6-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START1_I]], align 4, !noalias [[META14]] -// CHECK6-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP18]], align 8 -// CHECK6-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK6-NEXT: store i32 [[TMP23]], ptr [[DOTLINEAR_START1_I]], align 4, !noalias [[META16]] +// CHECK6-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP18]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK6-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META16]] // CHECK6-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP25]] to i32 -// CHECK6-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK6: omp.inner.for.cond.i: -// CHECK6-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK6-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17:![0-9]+]] // CHECK6-NEXT: [[CONV3_I:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK6-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK6-NEXT: [[TMP27:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] // CHECK6-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV3_I]], [[TMP27]] // CHECK6-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[OMP_INNER_FOR_END_I:%.*]] // CHECK6: omp.inner.for.body.i: -// CHECK6-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK6-NEXT: store i32 [[TMP28]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK6-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTLINEAR_START1_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK6-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK6-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK6-NEXT: store i32 [[TMP28]], ptr [[I_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK6-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTLINEAR_START1_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK6-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] // CHECK6-NEXT: [[ADD5_I:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK6-NEXT: store i32 [[ADD5_I]], ptr [[J_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK6-NEXT: [[TMP31:%.*]] = load i32, ptr [[J_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK6-NEXT: store i32 [[ADD5_I]], ptr [[J_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK6-NEXT: [[TMP31:%.*]] = load i32, ptr [[J_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] // CHECK6-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP31]], 1 -// CHECK6-NEXT: store i32 [[INC_I]], ptr [[J_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK6-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK6-NEXT: store i32 [[INC_I]], ptr [[J_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK6-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] // CHECK6-NEXT: [[ADD6_I:%.*]] = add nsw i32 [[TMP32]], 1 -// CHECK6-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK6-NEXT: store i32 [[ADD6_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META16]], !llvm.access.group [[ACC_GRP17]] +// CHECK6-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP18:![0-9]+]] // CHECK6: omp.inner.for.end.i: -// CHECK6-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 // CHECK6-NEXT: br i1 [[TMP34]], label [[DOTOMP_LINEAR_PU_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK6: .omp.linear.pu.i: -// CHECK6-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP18]], align 8 +// CHECK6-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP18]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK6-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP18]], i32 0, i32 1 -// CHECK6-NEXT: [[TMP37:%.*]] = load ptr, ptr [[TMP36]], align 8 -// CHECK6-NEXT: [[TMP38:%.*]] = load i32, ptr [[J_I]], align 4, !noalias [[META14]] +// CHECK6-NEXT: [[TMP37:%.*]] = load ptr, ptr [[TMP36]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK6-NEXT: [[TMP38:%.*]] = load i32, ptr [[J_I]], align 4, !noalias [[META16]] // CHECK6-NEXT: store i32 [[TMP38]], ptr [[TMP37]], align 4 // CHECK6-NEXT: br label [[DOTOMP_OUTLINED__EXIT]] // CHECK6: .omp_outlined..exit: @@ -1736,7 +1736,7 @@ void loop() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 16 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 @@ -1745,7 +1745,7 @@ void loop() { // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 8 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 16 +// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S]]], align 16 // CHECK7-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1763,7 +1763,7 @@ void loop() { // CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK7-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 // CHECK7-NEXT: call void @_ZN1SIdEC1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR1]]) -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -1790,7 +1790,7 @@ void loop() { // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 0 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 0 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX6]], ptr align 8 [[VAR1]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: store i32 33, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1806,7 +1806,7 @@ void loop() { // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[VAR]], ptr align 8 [[VAR1]], i64 8, i1 false) // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[T_VAR]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP7]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1822,32 +1822,32 @@ void loop() { // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i64 8, i1 false) // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4 // CHECK7-NEXT: store i32 [[TMP8]], ptr @_ZZ4mainE5sivar, align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_ARRAYCPY_DONE9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR1]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR1]]) #[[ATTR3]] // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK7-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[VAR]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[VAR]]) #[[ATTR3]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK7: arraydestroy.body13: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK7: arraydestroy.done17: -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TEST]]) #[[ATTR3]] -// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dereferenceable(8) [[TTT]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TEST]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIdED1Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[TTT]]) #[[ATTR3]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP11]] // @@ -1876,12 +1876,12 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIdED2Ev(ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK7-NEXT: ret void // // @@ -1893,7 +1893,7 @@ void loop() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 @@ -1902,7 +1902,7 @@ void loop() { // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 // CHECK7-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -1917,7 +1917,7 @@ void loop() { // CHECK7-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK7-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK7-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -1945,7 +1945,7 @@ void loop() { // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR1]], align 128, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 0 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1960,7 +1960,7 @@ void loop() { // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR1]], align 128 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[T_VAR]], align 128 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC2]], i64 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP7]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1974,31 +1974,31 @@ void loop() { // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]] // CHECK7: omp.arraycpy.done9: // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VAR]], ptr align 4 [[VAR4]], i64 4, i1 false) -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR3]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP8]], [[OMP_ARRAYCPY_DONE9]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR3]] -// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR3]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK7: arraydestroy.body13: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP9]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK7: arraydestroy.done17: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TTT]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TTT]]) #[[ATTR3]] // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP10]] // @@ -2015,7 +2015,7 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIdED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 8 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2061,12 +2061,12 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK7-NEXT: ret void // // @@ -2096,7 +2096,7 @@ void loop() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/parallel_private_codegen.cpp b/clang/test/OpenMP/parallel_private_codegen.cpp index 39cc893ab7f09..a84322512aa7e 100644 --- a/clang/test/OpenMP/parallel_private_codegen.cpp +++ b/clang/test/OpenMP/parallel_private_codegen.cpp @@ -175,7 +175,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: call void @_ZN2SSC1ERi(ptr noundef nonnull align 8 dereferenceable(16) [[SS]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5sivar) @@ -189,18 +189,18 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @main.omp_outlined) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -248,12 +248,12 @@ int main() { // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -267,17 +267,17 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 3, ptr [[SIVAR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -285,12 +285,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -302,7 +302,7 @@ int main() { // CHECK1-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: call void @_ZN3SSTIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[SST]]) @@ -314,18 +314,18 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -346,7 +346,7 @@ int main() { // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK1-NEXT: ret void @@ -369,14 +369,14 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP]], align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 // CHECK1-NEXT: store i32 [[DEC]], ptr [[B]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 @@ -409,7 +409,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -457,11 +457,11 @@ int main() { // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -475,16 +475,16 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 128 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX1]], ptr align 128 [[VAR]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -492,12 +492,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -539,7 +539,7 @@ int main() { // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK1-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP2]], i64 4, ptr inttoptr (i64 2 to ptr)) // CHECK1-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 @@ -562,7 +562,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -611,7 +611,7 @@ int main() { // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK3-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK3-NEXT: ret void @@ -638,12 +638,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP4]], align 8 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: ret void @@ -658,17 +658,17 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 @@ -693,14 +693,14 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP]], align 8 // CHECK3-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[B]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 @@ -807,7 +807,7 @@ int main() { // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK4-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]]) // CHECK4-NEXT: ret void @@ -844,13 +844,13 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[BLOCK_CAPTURED]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[B]], align 4 // CHECK4-NEXT: store i32 [[TMP2]], ptr [[BLOCK_CAPTURED2]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP3]], ptr [[BLOCK_CAPTURED3]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 // CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 @@ -868,7 +868,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 // CHECK4-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 @@ -877,7 +877,7 @@ int main() { // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4 @@ -902,14 +902,14 @@ int main() { // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: store ptr [[A]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[B]], align 4 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 diff --git a/clang/test/OpenMP/parallel_reduction_codegen.cpp b/clang/test/OpenMP/parallel_reduction_codegen.cpp index ce76429b871fe..2869fca650ae9 100644 --- a/clang/test/OpenMP/parallel_reduction_codegen.cpp +++ b/clang/test/OpenMP/parallel_reduction_codegen.cpp @@ -502,7 +502,7 @@ int main() { // CHECK1-NEXT: [[T_VAR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[CF:%.*]] = alloca { float, float }, align 4 @@ -527,19 +527,19 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @main.omp_outlined.2, ptr [[CF]]) // CHECK1-NEXT: [[CALL1:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL1]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5:[0-9]+]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR1]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[IF_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -608,12 +608,12 @@ int main() { // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR1]], ptr [[VAR1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store float 0.000000e+00, ptr [[T_VAR2]], align 4 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) @@ -622,7 +622,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP7]], align 8 @@ -658,7 +658,7 @@ int main() { // CHECK1-NEXT: [[CONV10:%.*]] = uitofp i1 [[TMP16]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV10]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP5]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load float, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP17]], [[TMP18]] @@ -694,7 +694,7 @@ int main() { // CHECK1-NEXT: [[CONV19:%.*]] = uitofp i1 [[TMP23]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP12]], float noundef [[CONV19]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[REF_TMP12]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP12]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP12]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB2]], i32 [[TMP12]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP24:%.*]] = load float, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, ptr [[TMP5]] monotonic, align 4 @@ -724,8 +724,8 @@ int main() { // CHECK1: atomic_exit: // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR14]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR3]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // @@ -773,7 +773,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP22]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP15]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP23:%.*]] = load float, ptr [[TMP19]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP17]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP23]], [[TMP24]] @@ -811,12 +811,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // @@ -843,12 +843,12 @@ int main() { // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR1]], ptr [[VAR1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store float 0.000000e+00, ptr [[T_VAR2]], align 4 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) @@ -861,9 +861,9 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR3]], i64 4, i1 false) -// CHECK1-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// CHECK1-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP7:![0-9]+]] // // // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.2 @@ -880,7 +880,7 @@ int main() { // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[CF]], ptr [[CF_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[CF_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[CF_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[CF1_REALP:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[CF1]], i32 0, i32 0 // CHECK1-NEXT: [[CF1_IMAGP:%.*]] = getelementptr inbounds nuw { float, float }, ptr [[CF1]], i32 0, i32 1 // CHECK1-NEXT: store float 0.000000e+00, ptr [[CF1_REALP]], align 4 @@ -989,7 +989,7 @@ int main() { // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 128 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -1003,19 +1003,19 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 6, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[VEC]], ptr [[T_VAR]], ptr [[S_ARR]], ptr [[VAR]], ptr [[VAR1]], ptr [[T_VAR1]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -1039,15 +1039,15 @@ int main() { // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A3]], ptr [[A2]], align 8 // CHECK1-NEXT: [[C6:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C6]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C6]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[C5]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C5]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], ptr [[TMP2]], ptr [[B4]], ptr [[TMP3]]) // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B4]], align 4 // CHECK1-NEXT: [[B7:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 @@ -1084,26 +1084,26 @@ int main() { // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store i32 0, ptr [[A2]], align 4 // CHECK1-NEXT: store ptr [[A2]], ptr [[_TMP3]], align 8 // CHECK1-NEXT: store i32 0, ptr [[B4]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store i32 0, ptr [[C5]], align 4 // CHECK1-NEXT: store ptr [[C5]], ptr [[_TMP6]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP6]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[B4]], align 4 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 // CHECK1-NEXT: store i32 [[DEC]], ptr [[B4]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 @@ -1214,7 +1214,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1281,12 +1281,12 @@ int main() { // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR1]], ptr [[VAR1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 128 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) @@ -1294,7 +1294,7 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR2]], align 128 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 128 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP7]], align 8 @@ -1330,7 +1330,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP16]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP4]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 128 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR15]], align 128 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP17]], [[TMP18]] @@ -1366,14 +1366,14 @@ int main() { // CHECK1-NEXT: [[CONV18:%.*]] = zext i1 [[TMP23]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP11]], i32 noundef [[CONV18]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP4]], ptr align 4 [[REF_TMP11]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP11]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP11]]) #[[ATTR5]] // CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB2]], i32 [[TMP12]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR15]], align 128 // CHECK1-NEXT: [[TMP25:%.*]] = atomicrmw min ptr [[TMP5]], i32 [[TMP24]] monotonic, align 128 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR5]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR14]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR3]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // @@ -1421,7 +1421,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP22]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP15]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP19]], align 128 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP17]], align 128 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] @@ -1459,12 +1459,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // @@ -1491,7 +1491,7 @@ int main() { // CHECK1-NEXT: store i32 0, ptr [[A]], align 4 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A3]], ptr [[A2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @_ZN3SSTIiEC2Ev.omp_outlined, ptr [[THIS1]], ptr [[TMP0]]) // CHECK1-NEXT: ret void // @@ -1514,12 +1514,12 @@ int main() { // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store i32 1, ptr [[A1]], align 4 // CHECK1-NEXT: store ptr [[A1]], ptr [[_TMP2]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 @@ -1598,7 +1598,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1815,15 +1815,15 @@ int main() { // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK3-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[A3]], ptr [[A2]], align 8 // CHECK3-NEXT: [[C6:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C6]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C6]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[C5]], align 8 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C5]], align 8 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], ptr [[TMP2]], ptr [[B4]], ptr [[TMP3]]) // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B4]], align 4 // CHECK3-NEXT: [[B7:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 @@ -1861,27 +1861,27 @@ int main() { // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store i32 0, ptr [[A2]], align 4 // CHECK3-NEXT: store ptr [[A2]], ptr [[_TMP3]], align 8 // CHECK3-NEXT: store i32 0, ptr [[B4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store i32 0, ptr [[C5]], align 4 // CHECK3-NEXT: store ptr [[C5]], ptr [[_TMP6]], align 8 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[B4]], ptr [[TMP9]], align 8 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 @@ -1933,26 +1933,26 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP12]], ptr [[TMP14]], ptr [[TMP16]]) // CHECK3-NEXT: ret void // @@ -2017,26 +2017,26 @@ int main() { // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store i32 -1, ptr [[A2]], align 4 // CHECK3-NEXT: store ptr [[A2]], ptr [[_TMP3]], align 8 // CHECK3-NEXT: store i32 -1, ptr [[B4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: store i32 -1, ptr [[C5]], align 4 // CHECK3-NEXT: store ptr [[C5]], ptr [[_TMP6]], align 8 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP6]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[B4]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[B4]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 @@ -2329,7 +2329,7 @@ int main() { // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK4-NEXT: store i32 0, ptr [[G1]], align 128 // CHECK4-NEXT: store i32 1, ptr [[G1]], align 128 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, [96 x i8], i32 }>, ptr [[BLOCK]], i32 0, i32 0 @@ -2423,15 +2423,15 @@ int main() { // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[A3]], ptr [[A2]], align 8 // CHECK4-NEXT: [[C6:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C6]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C6]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[C5]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C5]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], ptr [[TMP2]], ptr [[B4]], ptr [[TMP3]]) // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[B4]], align 4 // CHECK4-NEXT: [[B7:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1 @@ -2469,16 +2469,16 @@ int main() { // CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store i32 0, ptr [[A2]], align 4 // CHECK4-NEXT: store ptr [[A2]], ptr [[_TMP3]], align 8 // CHECK4-NEXT: store i32 0, ptr [[B4]], align 4 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store i32 0, ptr [[C5]], align 4 // CHECK4-NEXT: store ptr [[C5]], ptr [[_TMP6]], align 8 // CHECK4-NEXT: [[BLOCK_ISA:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 0 @@ -2494,13 +2494,13 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 5 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[BLOCK_CAPTURED_THIS_ADDR]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP6]], ptr [[BLOCK_CAPTURED]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED7:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 8 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[B4]], align 4 // CHECK4-NEXT: store i32 [[TMP7]], ptr [[BLOCK_CAPTURED7]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURED8:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[BLOCK]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP8]], ptr [[BLOCK_CAPTURED8]], align 8 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr [[BLOCK]], i32 0, i32 3 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 @@ -2555,7 +2555,7 @@ int main() { // CHECK4-NEXT: [[BLOCK_CAPTURED_THIS:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 5 // CHECK4-NEXT: [[THIS:%.*]] = load ptr, ptr [[BLOCK_CAPTURED_THIS]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP0]], align 4 @@ -2564,15 +2564,15 @@ int main() { // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP2]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[BLOCK_CAPTURE_ADDR1]], align 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR2:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP4]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP3]], align 4 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR3:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR4:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 8 // CHECK4-NEXT: [[BLOCK_CAPTURE_ADDR5:%.*]] = getelementptr inbounds nuw <{ ptr, i32, i32, ptr, ptr, ptr, ptr, ptr, i32 }>, ptr [[DOTBLOCK_DESCRIPTOR]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[BLOCK_CAPTURE_ADDR5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @g_block_invoke_2.omp_outlined, ptr [[THIS]], ptr [[TMP5]], ptr [[BLOCK_CAPTURE_ADDR4]], ptr [[TMP6]]) // CHECK4-NEXT: ret void // @@ -2601,26 +2601,26 @@ int main() { // CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store i32 0, ptr [[A2]], align 4 // CHECK4-NEXT: store ptr [[A2]], ptr [[_TMP3]], align 8 // CHECK4-NEXT: store i32 0, ptr [[B4]], align 4 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store i32 0, ptr [[C5]], align 4 // CHECK4-NEXT: store ptr [[C5]], ptr [[_TMP6]], align 8 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP7]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP6]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[B4]], align 4 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[B4]], align 4 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 diff --git a/clang/test/OpenMP/scope_codegen.cpp b/clang/test/OpenMP/scope_codegen.cpp index ef69b8302fa2d..ebf2d3e7a6769 100644 --- a/clang/test/OpenMP/scope_codegen.cpp +++ b/clang/test/OpenMP/scope_codegen.cpp @@ -147,12 +147,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -168,7 +168,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -205,7 +205,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -227,7 +227,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -255,7 +255,7 @@ int main() { // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 4 // CHECK1-NEXT: [[A24:%.*]] = alloca [2 x i8], align 1 -// CHECK1-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 4 +// CHECK1-NEXT: [[TC2:%.*]] = alloca [2 x [[CLASS_TESTCLASS]]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store ptr @tc, ptr [[C]], align 8 @@ -273,7 +273,7 @@ int main() { // CHECK1-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc) // CHECK1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK1: invoke.cont3: -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS]]], ptr [[TC2]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -288,18 +288,18 @@ int main() { // CHECK1-NEXT: invoke void @_Z3foov() // CHECK1-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK1: invoke.cont6: -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS]]], ptr [[TC2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]] -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TC]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[C2]]) #[[ATTR3]] // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK1-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1 // CHECK1-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 @@ -384,7 +384,7 @@ int main() { // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META7:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 // CHECK1-NEXT: store ptr [[A2]], ptr [[TMP]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8 @@ -393,12 +393,12 @@ int main() { // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 // CHECK1-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] @@ -424,30 +424,30 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 // CHECK1-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP14]]) // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]]) // CHECK1-NEXT: ret void // @@ -482,41 +482,41 @@ int main() { // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[E2]], ptr [[E]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4 // CHECK1-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4 // CHECK1-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store i32 0, ptr [[E11]], align 4 // CHECK1-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4 @@ -575,7 +575,7 @@ int main() { // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 @@ -645,12 +645,12 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK4-NEXT: ret void // // @@ -666,7 +666,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -703,7 +703,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -725,7 +725,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -753,7 +753,7 @@ int main() { // CHECK4-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 4 // CHECK4-NEXT: [[A24:%.*]] = alloca [2 x i8], align 1 -// CHECK4-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 4 +// CHECK4-NEXT: [[TC2:%.*]] = alloca [2 x [[CLASS_TESTCLASS]]], align 4 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK4-NEXT: store ptr @tc, ptr [[C]], align 8 @@ -771,7 +771,7 @@ int main() { // CHECK4-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc) // CHECK4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK4: invoke.cont3: -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0 +// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS]]], ptr [[TC2]], i32 0, i32 0 // CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: @@ -786,18 +786,18 @@ int main() { // CHECK4-NEXT: invoke void @_Z3foov() // CHECK4-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK4: invoke.cont6: -// CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0 +// CHECK4-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS]]], ptr [[TC2]], i32 0, i32 0 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done8: -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]] -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TC]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[C2]]) #[[ATTR3]] // CHECK4-NEXT: call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK4-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1 // CHECK4-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32 @@ -943,7 +943,7 @@ int main() { // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[A1]], ptr [[A]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK4-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP1]], align 8 // CHECK4-NEXT: store double [[TMP2]], ptr [[A_CASTED]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8 @@ -985,21 +985,21 @@ int main() { // CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 // CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[A1]], ptr [[_TMP2]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP10]], align 8 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP13]], align 8 @@ -1047,43 +1047,43 @@ int main() { // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP6]], align 8 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8 +// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP10]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP11]], ptr [[TMP9]], align 8 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 4 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 4 -// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP14]], ptr [[TMP12]], align 8 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 5 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 5 -// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 +// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP17]], ptr [[TMP15]], align 8 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 6 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP20]], ptr [[TMP18]], align 8 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 7 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8 +// CHECK4-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP22]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP23]], ptr [[TMP21]], align 8 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 8 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 8 -// CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 +// CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP26]], ptr [[TMP24]], align 8 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 9 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 9 -// CHECK4-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP28]], align 8 +// CHECK4-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP28]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP29]], ptr [[TMP27]], align 8 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 10 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 10 -// CHECK4-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8 +// CHECK4-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP31]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[TMP32]], ptr [[TMP30]], align 8 // CHECK4-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(88) [[REF_TMP]]) // CHECK4-NEXT: ret void @@ -1100,33 +1100,33 @@ int main() { // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 // CHECK4-NEXT: store double [[INC]], ptr [[TMP3]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP8]], align 8 // CHECK4-NEXT: store double [[TMP9]], ptr [[A_CASTED]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 4 -// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP13]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 5 -// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 6 -// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 7 -// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 8 -// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8 +// CHECK4-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP21]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 9 -// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8 +// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[TMP23]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 10 -// CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8 +// CHECK4-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP25]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 11, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP6]], i64 [[TMP10]], ptr [[TMP12]], ptr [[TMP14]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]], ptr [[TMP22]], ptr [[TMP24]], ptr [[TMP26]]) // CHECK4-NEXT: ret void // @@ -1163,22 +1163,22 @@ int main() { // CHECK4-NEXT: store ptr [[OMP_PTEAM_MEM_ALLOC]], ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 // CHECK4-NEXT: store ptr [[OMP_THREAD_MEM_ALLOC]], ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[OMP_NULL_ALLOCATOR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[OMP_DEFAULT_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[OMP_LARGE_CAP_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[OMP_CONST_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[OMP_HIGH_BW_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[OMP_LOW_LAT_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[OMP_PTEAM_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[OMP_THREAD_MEM_ALLOC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8 // CHECK4-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP11]], i64 8, ptr [[TMP12]]) // CHECK4-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[_TMP1]], align 8 -// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK4-NEXT: [[TMP14:%.*]] = load double, ptr [[TMP13]], align 8 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 // CHECK4-NEXT: store double [[INC]], ptr [[TMP13]], align 8 @@ -1210,7 +1210,7 @@ int main() { // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META7:![0-9]+]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[C]], align 8 // CHECK4-NEXT: store ptr [[A2]], ptr [[TMP]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8 @@ -1219,12 +1219,12 @@ int main() { // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK4-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 // CHECK4-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] @@ -1250,30 +1250,30 @@ int main() { // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8 +// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK4-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP14]]) // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 +// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]]) // CHECK4-NEXT: ret void // @@ -1308,41 +1308,41 @@ int main() { // CHECK4-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8 // CHECK4-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[E2]], ptr [[E]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8 -// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK4-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4 // CHECK4-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK4-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4 -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK4-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4 // CHECK4-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: store i32 0, ptr [[E11]], align 4 // CHECK4-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8 -// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4 -// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8 +// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK4-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4 -// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8 +// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4 @@ -1401,7 +1401,7 @@ int main() { // CHECK4-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4 // CHECK4-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 @@ -1464,12 +1464,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG16:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG16:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG17:![0-9]+]] +// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG17:![0-9]+]] // CHECK5-NEXT: ret void, !dbg [[DBG18:![0-9]+]] // // @@ -1485,7 +1485,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG22:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG22:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1522,7 +1522,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG25]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG25]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG25]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG25]] // CHECK5: arraydestroy.done1: @@ -1544,7 +1544,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG30]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG30]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG30]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG30]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG30]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG30]] // CHECK5: arraydestroy.done1: @@ -1572,7 +1572,7 @@ int main() { // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TC:%.*]] = alloca [[CLASS_TESTCLASS]], align 4 // CHECK5-NEXT: [[A24:%.*]] = alloca [2 x i8], align 1 -// CHECK5-NEXT: [[TC2:%.*]] = alloca [2 x %class.TestClass], align 4 +// CHECK5-NEXT: [[TC2:%.*]] = alloca [2 x [[CLASS_TESTCLASS]]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]), !dbg [[DBG35:![0-9]+]] // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK5-NEXT: store ptr @tc, ptr [[C]], align 8, !dbg [[DBG36:![0-9]+]] @@ -1590,7 +1590,7 @@ int main() { // CHECK5-NEXT: invoke void @_ZN9TestClassC1ERKS_(ptr noundef nonnull align 4 dereferenceable(4) [[TC]], ptr noundef nonnull align 4 dereferenceable(4) @tc) // CHECK5-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG45:![0-9]+]] // CHECK5: invoke.cont3: -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0, !dbg [[DBG46:![0-9]+]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS]]], ptr [[TC2]], i32 0, i32 0, !dbg [[DBG46:![0-9]+]] // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2, !dbg [[DBG46]] // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG46]] // CHECK5: arrayctor.loop: @@ -1605,18 +1605,18 @@ int main() { // CHECK5-NEXT: invoke void @_Z3foov() // CHECK5-NEXT: to label [[INVOKE_CONT6:%.*]] unwind label [[TERMINATE_LPAD]], !dbg [[DBG47:![0-9]+]] // CHECK5: invoke.cont6: -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TC2]], i32 0, i32 0, !dbg [[DBG47]] +// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS]]], ptr [[TC2]], i32 0, i32 0, !dbg [[DBG47]] // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN7]], i64 2, !dbg [[DBG47]] // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG47]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[INVOKE_CONT6]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG47]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG47]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG47]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG47]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]], !dbg [[DBG47]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG47]] // CHECK5: arraydestroy.done8: -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TC]]) #[[ATTR3]], !dbg [[DBG47]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[C2]]) #[[ATTR3]], !dbg [[DBG47]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TC]]) #[[ATTR3]], !dbg [[DBG47]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[C2]]) #[[ATTR3]], !dbg [[DBG47]] // CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP0]]), !dbg [[DBG48:![0-9]+]] // CHECK5-NEXT: [[TMP3:%.*]] = load i8, ptr [[A]], align 1, !dbg [[DBG49:![0-9]+]] // CHECK5-NEXT: [[CONV:%.*]] = sext i8 [[TMP3]] to i32, !dbg [[DBG49]] @@ -1714,16 +1714,16 @@ int main() { // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG68:![0-9]+]] // CHECK5-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_SST:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG69:![0-9]+]] // CHECK5-NEXT: store ptr [[A1]], ptr [[A]], align 8, !dbg [[DBG69]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8, !dbg [[DBG69]] -// CHECK5-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP1]], align 8, !dbg [[DBG70:![0-9]+]] -// CHECK5-NEXT: store double [[TMP2]], ptr [[A_CASTED]], align 8, !dbg [[DBG70]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG70]] -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB8:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined, ptr [[TMP0]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], i64 [[TMP3]]), !dbg [[DBG70]] -// CHECK5-NEXT: ret void, !dbg [[DBG71:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A]], align 8, !dbg [[DBG69]], !nonnull [[META8:![0-9]+]], !align [[META70:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP1]], align 8, !dbg [[DBG71:![0-9]+]] +// CHECK5-NEXT: store double [[TMP2]], ptr [[A_CASTED]], align 8, !dbg [[DBG71]] +// CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG71]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB8:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined, ptr [[TMP0]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], i64 [[TMP3]]), !dbg [[DBG71]] +// CHECK5-NEXT: ret void, !dbg [[DBG72:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN3SSTIdEC1Ev_l70.omp_outlined.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 !dbg [[DBG72:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 !dbg [[DBG73:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1739,34 +1739,34 @@ int main() { // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG73:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG73]] -// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG73]] -// CHECK5-NEXT: store ptr [[A1]], ptr [[_TMP2]], align 8, !dbg [[DBG74:![0-9]+]] -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG75:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8, !dbg [[DBG75]] -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG75]] -// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG76:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 8, !dbg [[DBG75]] -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG75]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP5]], align 8, !dbg [[DBG75]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG74:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG74]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG74]] +// CHECK5-NEXT: store ptr [[A1]], ptr [[_TMP2]], align 8, !dbg [[DBG75:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG76:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP2]], align 8, !dbg [[DBG76]] +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG76]] +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG77:![0-9]+]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 8, !dbg [[DBG76]] +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG76]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP5]], align 8, !dbg [[DBG76]] // CHECK5-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG75]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG76]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG77:![0-9]+]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4, !dbg [[DBG77]] -// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB6:[0-9]+]], i32 [[TMP7]]), !dbg [[DBG77]] -// CHECK5-NEXT: ret void, !dbg [[DBG77]] +// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG78:![0-9]+]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4, !dbg [[DBG78]] +// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB6:[0-9]+]], i32 [[TMP7]]), !dbg [[DBG78]] +// CHECK5-NEXT: ret void, !dbg [[DBG78]] // CHECK5: terminate.lpad: // CHECK5-NEXT: [[TMP8:%.*]] = landingpad { ptr, i32 } -// CHECK5-NEXT: catch ptr null, !dbg [[DBG75]] -// CHECK5-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP8]], 0, !dbg [[DBG75]] -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP9]]) #[[ATTR10]], !dbg [[DBG75]] -// CHECK5-NEXT: unreachable, !dbg [[DBG75]] +// CHECK5-NEXT: catch ptr null, !dbg [[DBG76]] +// CHECK5-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP8]], 0, !dbg [[DBG76]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP9]]) #[[ATTR10]], !dbg [[DBG76]] +// CHECK5-NEXT: unreachable, !dbg [[DBG76]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] align 2 !dbg [[DBG78:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR1]] align 2 !dbg [[DBG79:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 @@ -1774,22 +1774,22 @@ int main() { // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG79:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8, !dbg [[DBG79]] -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG79]] -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG80:![0-9]+]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG80]] -// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8, !dbg [[DBG79]] -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG79]] -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG80]] -// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !dbg [[DBG80]] -// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP6]], align 8, !dbg [[DBG79]] -// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !dbg [[DBG79]] -// CHECK5-NEXT: ret void, !dbg [[DBG81:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG80:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8, !dbg [[DBG80]] +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG80]] +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG81:![0-9]+]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG81]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8, !dbg [[DBG80]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG80]] +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG81]] +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !dbg [[DBG81]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP6]], align 8, !dbg [[DBG80]] +// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !dbg [[DBG80]] +// CHECK5-NEXT: ret void, !dbg [[DBG82:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG84:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG85:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[C:%.*]] = alloca i32, align 4 @@ -1798,24 +1798,24 @@ int main() { // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG85:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG85]] -// CHECK5-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8, !dbg [[DBG86:![0-9]+]] -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG86]] -// CHECK5-NEXT: store double [[INC]], ptr [[TMP3]], align 8, !dbg [[DBG86]] -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG87:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG87]] -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG88:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !dbg [[DBG88]] -// CHECK5-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP8]], align 8, !dbg [[DBG89:![0-9]+]] -// CHECK5-NEXT: store double [[TMP9]], ptr [[A_CASTED]], align 8, !dbg [[DBG89]] -// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG89]] -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB14:[0-9]+]], i32 3, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP6]], i64 [[TMP10]]), !dbg [[DBG89]] -// CHECK5-NEXT: ret void, !dbg [[DBG90:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG86:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG86]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8, !dbg [[DBG87:![0-9]+]] +// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG87]] +// CHECK5-NEXT: store double [[INC]], ptr [[TMP3]], align 8, !dbg [[DBG87]] +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG88:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG88]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG89:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !dbg [[DBG89]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: [[TMP9:%.*]] = load double, ptr [[TMP8]], align 8, !dbg [[DBG90:![0-9]+]] +// CHECK5-NEXT: store double [[TMP9]], ptr [[A_CASTED]], align 8, !dbg [[DBG90]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG90]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB14:[0-9]+]], i32 3, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], ptr [[TMP6]], i64 [[TMP10]]), !dbg [[DBG90]] +// CHECK5-NEXT: ret void, !dbg [[DBG91:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] !dbg [[DBG91:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[OMP_CGROUP_MEM_ALLOC:%.*]], i64 noundef [[A:%.*]]) #[[ATTR8]] !dbg [[DBG92:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1829,26 +1829,26 @@ int main() { // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[OMP_CGROUP_MEM_ALLOC]], ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG92:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG92]] -// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG92]] -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG93]] -// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG94:![0-9]+]] -// CHECK5-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP3]], i64 8, ptr [[TMP4]]), !dbg [[DBG93]] -// CHECK5-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG93]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG95:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load double, ptr [[TMP5]], align 8, !dbg [[DBG96:![0-9]+]] -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00, !dbg [[DBG96]] -// CHECK5-NEXT: store double [[INC]], ptr [[TMP5]], align 8, !dbg [[DBG96]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG94]] -// CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP3]], ptr [[DOTA__VOID_ADDR]], ptr [[TMP7]]), !dbg [[DBG96]] -// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB12:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG97:![0-9]+]] -// CHECK5-NEXT: ret void, !dbg [[DBG97]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG93:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[OMP_CGROUP_MEM_ALLOC_ADDR]], align 8, !dbg [[DBG93]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG93]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG94:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG94]] +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG95:![0-9]+]] +// CHECK5-NEXT: [[DOTA__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP3]], i64 8, ptr [[TMP4]]), !dbg [[DBG94]] +// CHECK5-NEXT: store ptr [[DOTA__VOID_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG94]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG96:![0-9]+]], !nonnull [[META8]], !align [[META70]] +// CHECK5-NEXT: [[TMP6:%.*]] = load double, ptr [[TMP5]], align 8, !dbg [[DBG97:![0-9]+]] +// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00, !dbg [[DBG97]] +// CHECK5-NEXT: store double [[INC]], ptr [[TMP5]], align 8, !dbg [[DBG97]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG95]] +// CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP3]], ptr [[DOTA__VOID_ADDR]], ptr [[TMP7]]), !dbg [[DBG97]] +// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB12:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG98:![0-9]+]] +// CHECK5-NEXT: ret void, !dbg [[DBG98]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 personality ptr @__gxx_personality_v0 !dbg [[DBG98:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 personality ptr @__gxx_personality_v0 !dbg [[DBG99:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 @@ -1857,88 +1857,88 @@ int main() { // CHECK5-NEXT: [[C3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_1:%.*]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB16:[0-9]+]]), !dbg [[DBG99:![0-9]+]] +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB16:[0-9]+]]), !dbg [[DBG100:![0-9]+]] // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG100:![0-9]+]] -// CHECK5-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG100]] -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG101:![0-9]+]] -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 8, !dbg [[DBG101]] -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG101]] -// CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0, !dbg [[DBG101]] -// CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8, !dbg [[DBG101]] -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG102:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG103:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[C]], align 8, !dbg [[DBG102]] -// CHECK5-NEXT: store ptr [[A2]], ptr [[TMP]], align 8, !dbg [[DBG104:![0-9]+]] -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8, !dbg [[DBG105:![0-9]+]] -// CHECK5-NEXT: [[DOTB__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP2]]), !dbg [[DBG104]] -// CHECK5-NEXT: store ptr [[C3]], ptr [[_TMP4]], align 8, !dbg [[DBG104]] -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG106:![0-9]+]] -// CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8, !dbg [[DBG106]] -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG106]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG107:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8, !dbg [[DBG106]] -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG106]] -// CHECK5-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8, !dbg [[DBG106]] -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3, !dbg [[DBG106]] -// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !dbg [[DBG107]] -// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8, !dbg [[DBG106]] +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG101:![0-9]+]] +// CHECK5-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG101]] +// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG102:![0-9]+]] +// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 8, !dbg [[DBG102]] +// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG102]] +// CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0, !dbg [[DBG102]] +// CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 8, !dbg [[DBG102]] +// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG103:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG104:![0-9]+]], !nonnull [[META8]], !align [[META105:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[C]], align 8, !dbg [[DBG103]] +// CHECK5-NEXT: store ptr [[A2]], ptr [[TMP]], align 8, !dbg [[DBG106:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8, !dbg [[DBG107:![0-9]+]] +// CHECK5-NEXT: [[DOTB__VOID_ADDR:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP0]], i64 4, ptr [[TMP2]]), !dbg [[DBG106]] +// CHECK5-NEXT: store ptr [[C3]], ptr [[_TMP4]], align 8, !dbg [[DBG106]] +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG108:![0-9]+]] +// CHECK5-NEXT: store ptr [[THIS1]], ptr [[TMP3]], align 8, !dbg [[DBG108]] +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG108]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG109:![0-9]+]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8, !dbg [[DBG108]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG108]] +// CHECK5-NEXT: store ptr [[DOTB__VOID_ADDR]], ptr [[TMP6]], align 8, !dbg [[DBG108]] +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3, !dbg [[DBG108]] +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8, !dbg [[DBG109]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8, !dbg [[DBG108]] // CHECK5-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG106]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG108]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8, !dbg [[DBG105]] -// CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTB__VOID_ADDR]], ptr [[TMP9]]), !dbg [[DBG106]] -// CHECK5-NEXT: ret void, !dbg [[DBG108:![0-9]+]] +// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr @omp_default_mem_alloc, align 8, !dbg [[DBG107]] +// CHECK5-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTB__VOID_ADDR]], ptr [[TMP9]]), !dbg [[DBG108]] +// CHECK5-NEXT: ret void, !dbg [[DBG110:![0-9]+]] // CHECK5: terminate.lpad: // CHECK5-NEXT: [[TMP10:%.*]] = landingpad { ptr, i32 } -// CHECK5-NEXT: catch ptr null, !dbg [[DBG106]] -// CHECK5-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0, !dbg [[DBG106]] -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR10]], !dbg [[DBG106]] -// CHECK5-NEXT: unreachable, !dbg [[DBG106]] +// CHECK5-NEXT: catch ptr null, !dbg [[DBG108]] +// CHECK5-NEXT: [[TMP11:%.*]] = extractvalue { ptr, i32 } [[TMP10]], 0, !dbg [[DBG108]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP11]]) #[[ATTR10]], !dbg [[DBG108]] +// CHECK5-NEXT: unreachable, !dbg [[DBG108]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG109:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG111:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB22:[0-9]+]]), !dbg [[DBG110:![0-9]+]] +// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB22:[0-9]+]]), !dbg [[DBG112:![0-9]+]] // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG111:![0-9]+]] -// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG111]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG112:![0-9]+]] -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1, !dbg [[DBG112]] -// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4, !dbg [[DBG112]] -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG113:![0-9]+]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG113]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG114:![0-9]+]] -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1, !dbg [[DBG114]] -// CHECK5-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4, !dbg [[DBG114]] -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG115:![0-9]+]] -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG115]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG116:![0-9]+]] -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG116]] -// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4, !dbg [[DBG116]] -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG117:![0-9]+]] -// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8, !dbg [[DBG117]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG117]] -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB22]], i32 [[TMP0]], i32 [[TMP14]]), !dbg [[DBG118:![0-9]+]] -// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG119:![0-9]+]] -// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG119]] -// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG120:![0-9]+]] -// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !dbg [[DBG120]] -// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG121:![0-9]+]] -// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG121]] -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB24:[0-9]+]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]]), !dbg [[DBG118]] -// CHECK5-NEXT: ret void, !dbg [[DBG122:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG113:![0-9]+]] +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG113]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG114:![0-9]+]] +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP5]], 1, !dbg [[DBG114]] +// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP4]], align 4, !dbg [[DBG114]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG115:![0-9]+]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG115]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG116:![0-9]+]] +// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP8]], -1, !dbg [[DBG116]] +// CHECK5-NEXT: store i32 [[DEC]], ptr [[TMP7]], align 4, !dbg [[DBG116]] +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG117:![0-9]+]] +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG117]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG118:![0-9]+]] +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG118]] +// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4, !dbg [[DBG118]] +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG119:![0-9]+]] +// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[TMP12]], align 8, !dbg [[DBG119]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG119]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB22]], i32 [[TMP0]], i32 [[TMP14]]), !dbg [[DBG120:![0-9]+]] +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG121:![0-9]+]] +// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG121]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG122:![0-9]+]] +// CHECK5-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8, !dbg [[DBG122]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG123:![0-9]+]] +// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG123]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB24:[0-9]+]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP2]], ptr [[TMP16]], ptr [[TMP18]], ptr [[TMP20]]), !dbg [[DBG120]] +// CHECK5-NEXT: ret void, !dbg [[DBG124:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR8]] !dbg [[DBG123:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) #[[ATTR8]] !dbg [[DBG125:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -1966,141 +1966,141 @@ int main() { // CHECK5-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG124:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG124]] -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG124]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG124]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG124]] -// CHECK5-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG124]] -// CHECK5-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG125:![0-9]+]] -// CHECK5-NEXT: store ptr [[E2]], ptr [[E]], align 8, !dbg [[DBG125]] -// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG126:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8, !dbg [[DBG127:![0-9]+]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8, !dbg [[DBG128:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8, !dbg [[DBG127]] -// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG129:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8, !dbg [[DBG127]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG130:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG130]] -// CHECK5-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4, !dbg [[DBG130]] -// CHECK5-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8, !dbg [[DBG127]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG131:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4, !dbg [[DBG131]] -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !dbg [[DBG132:![0-9]+]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG132]] -// CHECK5-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4, !dbg [[DBG132]] -// CHECK5-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8, !dbg [[DBG127]] -// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !dbg [[DBG125]] -// CHECK5-NEXT: store i32 0, ptr [[E11]], align 4, !dbg [[DBG125]] -// CHECK5-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8, !dbg [[DBG127]] -// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8, !dbg [[DBG126]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG133:![0-9]+]] -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1, !dbg [[DBG133]] -// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4, !dbg [[DBG133]] -// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8, !dbg [[DBG128]] -// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4, !dbg [[DBG134:![0-9]+]] -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1, !dbg [[DBG134]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4, !dbg [[DBG134]] -// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !dbg [[DBG129]] -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG135:![0-9]+]] -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1, !dbg [[DBG135]] -// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4, !dbg [[DBG135]] -// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0, !dbg [[DBG133]] -// CHECK5-NEXT: store ptr [[E11]], ptr [[TMP19]], align 8, !dbg [[DBG133]] -// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG133]] -// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG133]] -// CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB18:[0-9]+]], i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG126:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG126]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG126]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG126]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8, !dbg [[DBG126]] +// CHECK5-NEXT: store ptr [[TMP3]], ptr [[_TMP1]], align 8, !dbg [[DBG126]] +// CHECK5-NEXT: [[E2:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG127:![0-9]+]] +// CHECK5-NEXT: store ptr [[E2]], ptr [[E]], align 8, !dbg [[DBG127]] +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG128:![0-9]+]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: store ptr [[TMP4]], ptr [[_TMP3]], align 8, !dbg [[DBG129:![0-9]+]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[E]], align 8, !dbg [[DBG130:![0-9]+]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: store ptr [[TMP5]], ptr [[_TMP4]], align 8, !dbg [[DBG129]] +// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG131:![0-9]+]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: store ptr [[TMP6]], ptr [[_TMP5]], align 8, !dbg [[DBG129]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG132:![0-9]+]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG132]] +// CHECK5-NEXT: store i32 [[TMP8]], ptr [[A6]], align 4, !dbg [[DBG132]] +// CHECK5-NEXT: store ptr [[A6]], ptr [[_TMP7]], align 8, !dbg [[DBG129]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG133:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP9]], ptr [[B8]], align 4, !dbg [[DBG133]] +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP5]], align 8, !dbg [[DBG134:![0-9]+]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG134]] +// CHECK5-NEXT: store i32 [[TMP11]], ptr [[C9]], align 4, !dbg [[DBG134]] +// CHECK5-NEXT: store ptr [[C9]], ptr [[_TMP10]], align 8, !dbg [[DBG129]] +// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !dbg [[DBG127]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: store i32 0, ptr [[E11]], align 4, !dbg [[DBG127]] +// CHECK5-NEXT: store ptr [[E11]], ptr [[_TMP12]], align 8, !dbg [[DBG129]] +// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP7]], align 8, !dbg [[DBG128]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG135:![0-9]+]] +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP14]], 1, !dbg [[DBG135]] +// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP13]], align 4, !dbg [[DBG135]] +// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP12]], align 8, !dbg [[DBG130]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4, !dbg [[DBG136:![0-9]+]] +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1, !dbg [[DBG136]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP15]], align 4, !dbg [[DBG136]] +// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP10]], align 8, !dbg [[DBG131]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG137:![0-9]+]] +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP18]], 1, !dbg [[DBG137]] +// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP17]], align 4, !dbg [[DBG137]] +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0, !dbg [[DBG135]] +// CHECK5-NEXT: store ptr [[E11]], ptr [[TMP19]], align 8, !dbg [[DBG135]] +// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG135]] +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG135]] +// CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB18:[0-9]+]], i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG135]] // CHECK5-NEXT: switch i32 [[TMP22]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK5-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK5-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK5-NEXT: ], !dbg [[DBG133]] +// CHECK5-NEXT: ], !dbg [[DBG135]] // CHECK5: .omp.reduction.case1: -// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG125]] -// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[E11]], align 4, !dbg [[DBG125]] -// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]], !dbg [[DBG136:![0-9]+]] -// CHECK5-NEXT: store i32 [[ADD13]], ptr [[TMP12]], align 4, !dbg [[DBG136]] -// CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB18]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]] -// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]], !dbg [[DBG133]] +// CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG127]] +// CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[E11]], align 4, !dbg [[DBG127]] +// CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP23]], [[TMP24]], !dbg [[DBG138:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD13]], ptr [[TMP12]], align 4, !dbg [[DBG138]] +// CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB18]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG135]] +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]], !dbg [[DBG135]] // CHECK5: .omp.reduction.case2: -// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[E11]], align 4, !dbg [[DBG125]] -// CHECK5-NEXT: [[TMP26:%.*]] = atomicrmw add ptr [[TMP12]], i32 [[TMP25]] monotonic, align 4, !dbg [[DBG133]] -// CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB18]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG133]] -// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]], !dbg [[DBG133]] +// CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[E11]], align 4, !dbg [[DBG127]] +// CHECK5-NEXT: [[TMP26:%.*]] = atomicrmw add ptr [[TMP12]], i32 [[TMP25]] monotonic, align 4, !dbg [[DBG135]] +// CHECK5-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB18]], i32 [[TMP21]], ptr @.gomp_critical_user_.reduction.var), !dbg [[DBG135]] +// CHECK5-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]], !dbg [[DBG135]] // CHECK5: .omp.reduction.default: -// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB20:[0-9]+]], i32 [[TMP21]]), !dbg [[DBG137:![0-9]+]] -// CHECK5-NEXT: ret void, !dbg [[DBG137]] +// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB20:[0-9]+]], i32 [[TMP21]]), !dbg [[DBG139:![0-9]+]] +// CHECK5-NEXT: ret void, !dbg [[DBG139]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined.omp.reduction.reduction_func -// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] !dbg [[DBG138:![0-9]+]] { +// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] !dbg [[DBG140:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG139:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG139]] -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG139]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG139]] -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG139]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG139]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG140:![0-9]+]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG140]] -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]], !dbg [[DBG141:![0-9]+]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4, !dbg [[DBG141]] -// CHECK5-NEXT: ret void, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG141:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG141]] +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG141]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG141]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG141]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG141]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG142:![0-9]+]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG142]] +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]], !dbg [[DBG143:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4, !dbg [[DBG143]] +// CHECK5-NEXT: ret void, !dbg [[DBG142]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassC2ERKS_ -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG142:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[C:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG144:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG143:![0-9]+]] -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG144:![0-9]+]] -// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG145:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4, !dbg [[DBG145]] -// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A]], align 4, !dbg [[DBG143]] -// CHECK5-NEXT: ret void, !dbg [[DBG146:![0-9]+]] +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG145:![0-9]+]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG146:![0-9]+]], !nonnull [[META8]], !align [[META105]] +// CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[CLASS_TESTCLASS]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG147:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[A2]], align 4, !dbg [[DBG147]] +// CHECK5-NEXT: store i32 [[TMP1]], ptr [[A]], align 4, !dbg [[DBG145]] +// CHECK5-NEXT: ret void, !dbg [[DBG148:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev -// CHECK5-SAME: () #[[ATTR2]] !dbg [[DBG147:![0-9]+]] { +// CHECK5-SAME: () #[[ATTR2]] !dbg [[DBG149:![0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB28:[0-9]+]], i32 0, ptr @_Z15parallel_singlev.omp_outlined), !dbg [[DBG148:![0-9]+]] -// CHECK5-NEXT: ret void, !dbg [[DBG149:![0-9]+]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB28:[0-9]+]], i32 0, ptr @_Z15parallel_singlev.omp_outlined), !dbg [[DBG150:![0-9]+]] +// CHECK5-NEXT: ret void, !dbg [[DBG151:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 !dbg [[DBG150:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR8]] personality ptr @__gxx_personality_v0 !dbg [[DBG152:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG151:![0-9]+]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG153:![0-9]+]] // CHECK5: invoke.cont: -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG152:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG152]] -// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB26:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG152]] -// CHECK5-NEXT: ret void, !dbg [[DBG152]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG154:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG154]] +// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB26:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG154]] +// CHECK5-NEXT: ret void, !dbg [[DBG154]] // CHECK5: terminate.lpad: // CHECK5-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } -// CHECK5-NEXT: catch ptr null, !dbg [[DBG151]] -// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG151]] -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR10]], !dbg [[DBG151]] -// CHECK5-NEXT: unreachable, !dbg [[DBG151]] +// CHECK5-NEXT: catch ptr null, !dbg [[DBG153]] +// CHECK5-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG153]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP3]]) #[[ATTR10]], !dbg [[DBG153]] +// CHECK5-NEXT: unreachable, !dbg [[DBG153]] // // // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_scope_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG153:![0-9]+]] { +// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG155:![0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG154:![0-9]+]] -// CHECK5-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG154]] +// CHECK5-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG156:![0-9]+]] +// CHECK5-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG156]] // CHECK5-NEXT: ret void // // @@ -2193,10 +2193,10 @@ int main() { // CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 // CHECK6-NEXT: [[A:%.*]] = alloca [10 x i32], align 16 -// CHECK6-NEXT: [[S:%.*]] = alloca [2 x %struct.St], align 16 +// CHECK6-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_ST:%.*]]], align 16 // CHECK6-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_ST]]], ptr [[S]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK6: arrayctor.loop: // CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -2207,16 +2207,16 @@ int main() { // CHECK6: arrayctor.cont: // CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4 // CHECK6-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 0 -// CHECK6-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i64 0, i64 0 +// CHECK6-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [2 x [[STRUCT_ST]]], ptr [[S]], i64 0, i64 0 // CHECK6-NEXT: call void @_Z10array_funciPiP2St(i32 noundef [[TMP0]], ptr noundef [[ARRAYDECAY]], ptr noundef [[ARRAYDECAY1]]) // CHECK6-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK6-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[S]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_ST]]], ptr [[S]], i32 0, i32 0 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK6: arraydestroy.body: // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK6-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1:[0-9]+]] +// CHECK6-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1:[0-9]+]] // CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK6: arraydestroy.done3: @@ -2235,12 +2235,12 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK6-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK6-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]] +// CHECK6-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR1]] // CHECK6-NEXT: ret void // // @@ -2258,7 +2258,7 @@ int main() { // // // CHECK6-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK6-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK6-NEXT: entry: // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/sections_firstprivate_codegen.cpp b/clang/test/OpenMP/sections_firstprivate_codegen.cpp index 32c5826e6f75d..11ff44af810ab 100644 --- a/clang/test/OpenMP/sections_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/sections_firstprivate_codegen.cpp @@ -166,12 +166,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -189,7 +189,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -228,7 +228,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -271,9 +271,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]]) @@ -285,7 +285,7 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr @t_var, align 4 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[T_VAR]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP2]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -294,7 +294,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP2]] @@ -302,7 +302,7 @@ int main() { // CHECK1: omp.arraycpy.done1: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], ptr noundef nonnull align 4 dereferenceable(4) @var, ptr noundef [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[SIVAR]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -327,7 +327,7 @@ int main() { // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 31, ptr [[SIVAR]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] @@ -340,14 +340,14 @@ int main() { // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -381,12 +381,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -397,7 +397,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -408,18 +408,18 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -460,7 +460,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -507,9 +507,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -528,7 +528,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[T_VAR1]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -537,7 +537,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -545,7 +545,7 @@ int main() { // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_SECTIONS_IL_]], ptr [[DOTOMP_SECTIONS_LB_]], ptr [[DOTOMP_SECTIONS_UB_]], ptr [[DOTOMP_SECTIONS_ST_]], i32 1, i32 1) @@ -573,7 +573,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case7: -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: @@ -587,14 +587,14 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP18]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done10: @@ -620,12 +620,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -679,7 +679,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -715,12 +715,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -738,7 +738,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -777,7 +777,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -849,12 +849,12 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // @@ -872,7 +872,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -911,7 +911,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: diff --git a/clang/test/OpenMP/sections_lastprivate_codegen.cpp b/clang/test/OpenMP/sections_lastprivate_codegen.cpp index 64fd8fa85cac6..1249d31daa18b 100644 --- a/clang/test/OpenMP/sections_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/sections_lastprivate_codegen.cpp @@ -195,7 +195,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -209,18 +209,18 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @main.omp_outlined.1) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -265,8 +265,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR5:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -275,16 +275,16 @@ int main() { // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -319,7 +319,7 @@ int main() { // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 0 // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: store i32 31, ptr [[SIVAR5]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] @@ -341,7 +341,7 @@ int main() { // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: store i32 [[TMP20]], ptr [[TMP0]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC2]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN7]], [[TMP21]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -359,14 +359,14 @@ int main() { // CHECK1-NEXT: store i32 [[TMP22]], ptr [[TMP4]], align 4 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1: .omp.lastprivate.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -377,12 +377,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -459,7 +459,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -470,18 +470,18 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -498,7 +498,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -559,23 +559,23 @@ int main() { // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -613,7 +613,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case5: -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 0 // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: @@ -634,7 +634,7 @@ int main() { // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: store i32 [[TMP19]], ptr [[TMP0]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC2]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN7]], [[TMP20]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -650,14 +650,14 @@ int main() { // CHECK1-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK1: .omp.lastprivate.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -668,12 +668,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -703,7 +703,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -776,7 +776,7 @@ int main() { // CHECK4-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK4-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK4-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 @@ -871,7 +871,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -885,18 +885,18 @@ int main() { // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @main.omp_outlined.1) // CHECK5-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP1]] // @@ -941,8 +941,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[SIVAR5:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -951,16 +951,16 @@ int main() { // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -995,7 +995,7 @@ int main() { // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 0 // CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: store i32 31, ptr [[SIVAR5]], align 4 // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] @@ -1017,7 +1017,7 @@ int main() { // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK5-NEXT: store i32 [[TMP20]], ptr [[TMP0]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC2]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN7]], [[TMP21]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1035,14 +1035,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP22]], ptr [[TMP4]], align 4 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done12: @@ -1053,12 +1053,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -1153,7 +1153,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -1164,18 +1164,18 @@ int main() { // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP1]] // @@ -1206,7 +1206,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1253,23 +1253,23 @@ int main() { // CHECK5-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK5-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1307,7 +1307,7 @@ int main() { // CHECK5-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK5: .omp.sections.case5: -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 0 // CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK5: .omp.sections.exit: @@ -1328,7 +1328,7 @@ int main() { // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK5-NEXT: store i32 [[TMP19]], ptr [[TMP0]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP1]], ptr align 4 [[VEC2]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN7]], [[TMP20]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1344,14 +1344,14 @@ int main() { // CHECK5-NEXT: [[CALL10:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done12: @@ -1362,12 +1362,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -1397,7 +1397,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/sections_private_codegen.cpp b/clang/test/OpenMP/sections_private_codegen.cpp index 98c38424c134a..8cde412a07564 100644 --- a/clang/test/OpenMP/sections_private_codegen.cpp +++ b/clang/test/OpenMP/sections_private_codegen.cpp @@ -111,7 +111,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -124,18 +124,18 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @main.omp_outlined) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -175,8 +175,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -184,7 +184,7 @@ int main() { // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -219,7 +219,7 @@ int main() { // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] @@ -234,14 +234,14 @@ int main() { // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -252,12 +252,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -268,7 +268,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -279,18 +279,18 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -321,7 +321,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -364,15 +364,15 @@ int main() { // CHECK1-NEXT: [[DOTOMP_SECTIONS_IV_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_IL_]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -410,7 +410,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case1: -// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: @@ -424,14 +424,14 @@ int main() { // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN3]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN3]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done4: @@ -442,12 +442,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -477,7 +477,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/sections_reduction_codegen.cpp b/clang/test/OpenMP/sections_reduction_codegen.cpp index 4f9e77416d6f2..3c28f951da02e 100644 --- a/clang/test/OpenMP/sections_reduction_codegen.cpp +++ b/clang/test/OpenMP/sections_reduction_codegen.cpp @@ -189,7 +189,7 @@ int main() { // CHECK1-NEXT: [[T_VAR:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca float, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -204,19 +204,19 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[VAR]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR1]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -277,12 +277,12 @@ int main() { // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 @@ -316,13 +316,13 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP15]] to i32 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP5]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[CONV7:%.*]] = fptosi float [[TMP16]] to i32 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 1 // CHECK1-NEXT: store i32 [[CONV7]], ptr [[ARRAYIDX8]], align 4 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP5]], i64 0, i64 1 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR14]], i64 4, i1 false) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: @@ -366,7 +366,7 @@ int main() { // CHECK1-NEXT: [[CONV13:%.*]] = uitofp i1 [[TMP25]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV13]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP26:%.*]] = load float, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[TMP27:%.*]] = load float, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[CMP14:%.*]] = fcmp olt float [[TMP26]], [[TMP27]] @@ -402,7 +402,7 @@ int main() { // CHECK1-NEXT: [[CONV23:%.*]] = uitofp i1 [[TMP32]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP16]], float noundef [[CONV23]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP16]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP16]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP16]]) #[[ATTR4]] // CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP33:%.*]] = load float, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[ATOMIC_LOAD:%.*]] = load atomic i32, ptr [[TMP3]] monotonic, align 4 @@ -433,8 +433,8 @@ int main() { // CHECK1-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB2]], i32 [[TMP7]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR14]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR3]]) #[[ATTR4]] // CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP7]]) // CHECK1-NEXT: ret void // @@ -483,7 +483,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = uitofp i1 [[TMP22]] to float // CHECK1-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], float noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP15]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP23:%.*]] = load float, ptr [[TMP19]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP17]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt float [[TMP23]], [[TMP24]] @@ -521,12 +521,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -539,7 +539,7 @@ int main() { // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[VAR1:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -552,19 +552,19 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VAR]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR1]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -601,7 +601,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -663,12 +663,12 @@ int main() { // CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[T_VAR1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR1_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[T_VAR1_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_SECTIONS_LB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_UB_]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_SECTIONS_ST_]], align 4 @@ -704,7 +704,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case6: -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP5]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP5]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: @@ -748,7 +748,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP24]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP25]], [[TMP26]] @@ -784,14 +784,14 @@ int main() { // CHECK1-NEXT: [[CONV20:%.*]] = zext i1 [[TMP31]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP13]], i32 noundef [[CONV20]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[REF_TMP13]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP13]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP13]]) #[[ATTR4]] // CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB3]], i32 [[TMP7]], ptr @.gomp_critical_user_.atomic_reduction.var) // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[TMP33:%.*]] = atomicrmw min ptr [[TMP3]], i32 [[TMP32]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) #[[ATTR4]] -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR3]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR14]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR3]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -839,7 +839,7 @@ int main() { // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TMP22]] to i32 // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]], i32 noundef [[CONV]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP15]], ptr align 4 [[REF_TMP]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP17]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]] @@ -877,12 +877,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -918,7 +918,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/simd_private_taskloop_codegen.cpp b/clang/test/OpenMP/simd_private_taskloop_codegen.cpp index e9971115de1b4..7ee8f96fd8014 100644 --- a/clang/test/OpenMP/simd_private_taskloop_codegen.cpp +++ b/clang/test/OpenMP/simd_private_taskloop_codegen.cpp @@ -456,7 +456,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -482,7 +482,7 @@ int main() { // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 3 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -521,17 +521,17 @@ int main() { // CHECK9-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP20]] // @@ -685,7 +685,7 @@ int main() { // CHECK9-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP_I]], align 8, !noalias [[META14]], !nonnull [[META16:![0-9]+]], !align [[META17:![0-9]+]], !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM8_I:%.*]] = sext i32 [[TMP34]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP24]], i64 0, i64 [[IDXPROM8_I]] +// CHECK9-NEXT: [[ARRAYIDX9_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP24]], i64 0, i64 [[IDXPROM8_I]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9_I]], ptr align 4 [[TMP33]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[ADD10_I:%.*]] = add nsw i32 [[TMP35]], 1 @@ -709,8 +709,8 @@ int main() { // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP4]], i32 0, i32 3 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP6]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP6]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -734,28 +734,28 @@ int main() { // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 3 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP4]]) #[[ATTR3]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP7]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK9-NEXT: ret void // // @@ -840,7 +840,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_2:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.2], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_2]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 1 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -861,7 +861,7 @@ int main() { // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]]) // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4]], ptr [[TMP3]], i32 0, i32 3 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2]]], ptr [[TMP5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -885,17 +885,17 @@ int main() { // CHECK9-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 0, i64 0, ptr @.omp_task_dup..6) // CHECK9-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP13]] // @@ -926,7 +926,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1076,7 +1076,7 @@ int main() { // CHECK9-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP_I]], align 8, !noalias [[META47]], !nonnull [[META16]], !align [[META17]], !llvm.access.group [[ACC_GRP48]] // CHECK9-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]] // CHECK9-NEXT: [[IDXPROM7_I:%.*]] = sext i32 [[TMP33]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8_I:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP24]], i64 0, i64 [[IDXPROM7_I]] +// CHECK9-NEXT: [[ARRAYIDX8_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2:%.*]]], ptr [[TMP24]], i64 0, i64 [[IDXPROM7_I]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8_I]], ptr align 4 [[TMP32]], i64 4, i1 false), !llvm.access.group [[ACC_GRP48]] // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META47]], !llvm.access.group [[ACC_GRP48]] // CHECK9-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP34]], 1 @@ -1100,8 +1100,8 @@ int main() { // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4]], ptr [[TMP4]], i32 0, i32 3 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP6]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2:%.*]]], ptr [[TMP6]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: // CHECK9-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -1125,28 +1125,28 @@ int main() { // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP2]], i32 0, i32 1 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4]], ptr [[TMP3]], i32 0, i32 3 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP5]], i32 0, i32 0 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2:%.*]]], ptr [[TMP5]], i32 0, i32 0 +// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP4]]) #[[ATTR3]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP7]] // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK9-NEXT: ret void // // @@ -1176,7 +1176,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1193,7 +1193,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1217,7 +1217,7 @@ int main() { // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP1]], i32 0, i32 1 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 2 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1258,17 +1258,17 @@ int main() { // CHECK11-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done5: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP20]] // @@ -1420,7 +1420,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP31]], ptr [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP_I]], align 4, !noalias [[META15]], !nonnull [[META17:![0-9]+]], !align [[META18:![0-9]+]], !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX8_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP24]], i32 0, i32 [[TMP34]] +// CHECK11-NEXT: [[ARRAYIDX8_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP24]], i32 0, i32 [[TMP34]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8_I]], ptr align 4 [[TMP33]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META15]], !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[ADD9_I:%.*]] = add nsw i32 [[TMP35]], 1 @@ -1442,8 +1442,8 @@ int main() { // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 1 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP4]], i32 0, i32 2 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -1469,14 +1469,14 @@ int main() { // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP2]], i32 0, i32 1 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP3]], i32 0, i32 2 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP3]], i32 0, i32 3 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR3]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP5]]) #[[ATTR3]] +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: @@ -1485,12 +1485,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK11-NEXT: ret void // // @@ -1575,7 +1575,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_2:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.2], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_2]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 1 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 @@ -1594,7 +1594,7 @@ int main() { // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5]], ptr [[TMP1]], i32 0, i32 1 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4:%.*]], ptr [[TMP3]], i32 0, i32 2 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2]]], ptr [[TMP4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1620,17 +1620,17 @@ int main() { // CHECK11-NEXT: call void @__kmpc_taskloop(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]], i32 1, ptr [[TMP7]], ptr [[TMP8]], i64 [[TMP11]], i32 1, i32 0, i64 0, ptr @.omp_task_dup..6) // CHECK11-NEXT: call void @__kmpc_end_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done3: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP13]] // @@ -1661,7 +1661,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1809,7 +1809,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP30]], ptr [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK11-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP_I]], align 4, !noalias [[META48]], !nonnull [[META17]], !align [[META18]], !llvm.access.group [[ACC_GRP49]] // CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[I_I]], align 4, !noalias [[META48]], !llvm.access.group [[ACC_GRP49]] -// CHECK11-NEXT: [[ARRAYIDX7_I:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP24]], i32 0, i32 [[TMP33]] +// CHECK11-NEXT: [[ARRAYIDX7_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2:%.*]]], ptr [[TMP24]], i32 0, i32 [[TMP33]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7_I]], ptr align 4 [[TMP32]], i32 4, i1 false), !llvm.access.group [[ACC_GRP49]] // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META48]], !llvm.access.group [[ACC_GRP49]] // CHECK11-NEXT: [[ADD8_I:%.*]] = add nsw i32 [[TMP34]], 1 @@ -1831,8 +1831,8 @@ int main() { // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP3]], i32 0, i32 1 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4:%.*]], ptr [[TMP4]], i32 0, i32 2 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP5]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2:%.*]]], ptr [[TMP5]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: // CHECK11-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -1858,14 +1858,14 @@ int main() { // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP2]], i32 0, i32 1 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4:%.*]], ptr [[TMP3]], i32 0, i32 2 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_4]], ptr [[TMP3]], i32 0, i32 3 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP5]]) #[[ATTR3]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.2], ptr [[TMP4]], i32 0, i32 0 -// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_2:%.*]], ptr [[ARRAY_BEGIN]], i32 2 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP5]]) #[[ATTR3]] +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_2:%.*]]], ptr [[TMP4]], i32 0, i32 0 +// CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_2]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: @@ -1874,12 +1874,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK11-NEXT: ret void // // @@ -1909,7 +1909,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1926,7 +1926,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1935,7 +1935,7 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -1961,7 +1961,7 @@ int main() { // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -1995,7 +1995,7 @@ int main() { // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]], !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2007,14 +2007,14 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done12: @@ -2047,17 +2047,17 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I13]], align 4 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN30:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN30:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN30]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY31:%.*]] // CHECK13: arraydestroy.body31: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST32:%.*]] = phi ptr [ [[TMP15]], [[OMP_INNER_FOR_END29]] ], [ [[ARRAYDESTROY_ELEMENT33:%.*]], [[ARRAYDESTROY_BODY31]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT33]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST32]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT33]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT33]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE34:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT33]], [[ARRAY_BEGIN30]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE34]], label [[ARRAYDESTROY_DONE35:%.*]], label [[ARRAYDESTROY_BODY31]] // CHECK13: arraydestroy.done35: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP16]] // @@ -2086,12 +2086,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2102,7 +2102,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2111,7 +2111,7 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2128,7 +2128,7 @@ int main() { // CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2162,7 +2162,7 @@ int main() { // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP11]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2174,29 +2174,29 @@ int main() { // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done12: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY14:%.*]] // CHECK13: arraydestroy.body14: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST15]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK13: arraydestroy.done18: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP11]] // @@ -2213,7 +2213,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2259,12 +2259,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2294,7 +2294,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2311,7 +2311,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2320,7 +2320,7 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2346,7 +2346,7 @@ int main() { // CHECK15-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK15-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK15-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2378,7 +2378,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META4:![0-9]+]], !align [[META5:![0-9]+]], !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2390,14 +2390,14 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done11: @@ -2430,17 +2430,17 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I12]], align 4 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN29:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN29:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN29]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY30:%.*]] // CHECK15: arraydestroy.body30: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST31:%.*]] = phi ptr [ [[TMP15]], [[OMP_INNER_FOR_END28]] ], [ [[ARRAYDESTROY_ELEMENT32:%.*]], [[ARRAYDESTROY_BODY30]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT32]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST31]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT32]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT32]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE33:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT32]], [[ARRAY_BEGIN29]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE33]], label [[ARRAYDESTROY_DONE34:%.*]], label [[ARRAYDESTROY_BODY30]] // CHECK15: arraydestroy.done34: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP16]] // @@ -2469,12 +2469,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2485,7 +2485,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2494,7 +2494,7 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2511,7 +2511,7 @@ int main() { // CHECK15-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 // CHECK15-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 // CHECK15-NEXT: store i32 [[CONV]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2543,7 +2543,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META4]], !align [[META5]], !llvm.access.group [[ACC_GRP12]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2555,29 +2555,29 @@ int main() { // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done11: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK15: arraydestroy.body13: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK15: arraydestroy.done17: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP11]] // @@ -2594,7 +2594,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2640,12 +2640,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2675,7 +2675,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/single_codegen.cpp b/clang/test/OpenMP/single_codegen.cpp index a4c9b015b615f..c1a0f6f0c0aa4 100644 --- a/clang/test/OpenMP/single_codegen.cpp +++ b/clang/test/OpenMP/single_codegen.cpp @@ -134,17 +134,17 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -164,8 +164,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TMP1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] @@ -190,7 +190,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -214,7 +214,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -266,7 +266,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -288,7 +288,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -307,7 +307,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -494,7 +494,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: store double 0.000000e+00, ptr [[A]], align 8 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A3]], ptr [[A2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK1-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK1-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 @@ -520,7 +520,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -532,7 +532,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 // CHECK1-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] @@ -542,7 +542,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP11]]) @@ -568,7 +568,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8 // CHECK1-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret void @@ -602,12 +602,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 // CHECK1-NEXT: store double [[INC]], ptr [[TMP3]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8 // CHECK1-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 @@ -632,7 +632,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -641,7 +641,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK1-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 // CHECK1-NEXT: store double [[INC]], ptr [[TMP6]], align 8 @@ -650,7 +650,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP10]]) @@ -697,7 +697,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META7:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A3]], ptr [[A2]], align 8 @@ -708,16 +708,16 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 // CHECK1-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 // CHECK1-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8 @@ -750,9 +750,9 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 // CHECK1-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -764,12 +764,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8 // CHECK1-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] @@ -779,12 +779,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1 // CHECK1-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP18]]) @@ -809,32 +809,32 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK1-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK1-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8 @@ -896,9 +896,9 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 // CHECK1-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -907,14 +907,14 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK1-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1 // CHECK1-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4 @@ -923,12 +923,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1 // CHECK1-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META3]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK1-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.8, i32 [[TMP17]]) @@ -1030,12 +1030,12 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1068,7 +1068,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1090,7 +1090,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1114,7 +1114,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1134,8 +1134,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TMP1]], i32 0, i32 0 -// CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] @@ -1160,7 +1160,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1184,7 +1184,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1414,7 +1414,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1444,7 +1444,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK2-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK2-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK2-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK2-NEXT: store ptr [[A3]], ptr [[A2]], align 8 @@ -1455,16 +1455,16 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 // CHECK2-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 // CHECK2-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8 -// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 // CHECK2-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8 +// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK2-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8 @@ -1497,9 +1497,9 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 // CHECK2-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 -// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1511,12 +1511,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK2-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8 // CHECK2-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] @@ -1526,12 +1526,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1 // CHECK2-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2 -// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP18]]) @@ -1556,32 +1556,32 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK2-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3 -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK2-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 // CHECK2-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK2-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3 -// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK2-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8 @@ -1643,9 +1643,9 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 // CHECK2-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 -// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1654,14 +1654,14 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2: omp_if.then: -// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK2-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK2-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1 // CHECK2-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 -// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK2-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4 @@ -1670,12 +1670,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1 // CHECK2-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2 -// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK2-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP17]]) @@ -1724,7 +1724,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: store double 0.000000e+00, ptr [[A]], align 8 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0 // CHECK2-NEXT: store ptr [[A3]], ptr [[A2]], align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] // CHECK2-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK2-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 @@ -1750,7 +1750,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1762,7 +1762,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 // CHECK2-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] @@ -1772,7 +1772,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP11]]) @@ -1798,7 +1798,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8 // CHECK2-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK2-NEXT: ret void @@ -1832,12 +1832,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 // CHECK2-NEXT: store double [[INC]], ptr [[TMP3]], align 8 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8 // CHECK2-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 @@ -1862,7 +1862,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 -// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1871,7 +1871,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK2-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK2: omp_if.then: -// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 // CHECK2-NEXT: store double [[INC]], ptr [[TMP6]], align 8 @@ -1880,7 +1880,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK2-NEXT: br label [[OMP_IF_END]] // CHECK2: omp_if.end: // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK2-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.8, i32 [[TMP10]]) @@ -1952,17 +1952,17 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3]] // CHECK4-NEXT: ret void // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK4-NEXT: ret void // // @@ -1997,7 +1997,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2018,8 +2018,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TMP1]], i32 0, i32 0 -// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ] @@ -2044,7 +2044,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2068,7 +2068,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2084,7 +2084,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK4-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2 // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: @@ -2306,7 +2306,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2336,7 +2336,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK4-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK4-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK4-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[A3]], ptr [[A2]], align 8 @@ -2347,16 +2347,16 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32 // CHECK4-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4 // CHECK4-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK4-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4 // CHECK4-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8 -// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK4-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8 @@ -2389,9 +2389,9 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2403,12 +2403,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK4-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8 // CHECK4-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] @@ -2418,12 +2418,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1 // CHECK4-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2 -// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.4, i32 [[TMP18]]) @@ -2448,32 +2448,32 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4 // CHECK4-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK4-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 3 -// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK4-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK4-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4 // CHECK4-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8 @@ -2535,9 +2535,9 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 // CHECK4-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8 -// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2546,14 +2546,14 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0 // CHECK4-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK4: omp_if.then: -// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 // CHECK4-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK4-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4 // CHECK4-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1 // CHECK4-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4 -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1 // CHECK4-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4 @@ -2562,12 +2562,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1 // CHECK4-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2 -// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK4-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK4-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP17]]) @@ -2616,7 +2616,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: store double 0.000000e+00, ptr [[A]], align 8 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[A3]], ptr [[A2]], align 8 -// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8 +// CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] // CHECK4-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK4-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8 @@ -2642,7 +2642,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2654,7 +2654,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK4-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8 // CHECK4-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] @@ -2664,7 +2664,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP11]]) @@ -2690,7 +2690,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 +// CHECK4-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8 // CHECK4-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK4-NEXT: ret void @@ -2724,12 +2724,12 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00 // CHECK4-NEXT: store double [[INC]], ptr [[TMP3]], align 8 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8 // CHECK4-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8 @@ -2754,7 +2754,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK4-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8 -// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK4-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8 // CHECK4-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2763,7 +2763,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 // CHECK4-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK4: omp_if.then: -// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00 // CHECK4-NEXT: store double [[INC]], ptr [[TMP6]], align 8 @@ -2772,7 +2772,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK4-NEXT: br label [[OMP_IF_END]] // CHECK4: omp_if.end: // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0 -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK4-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4 // CHECK4-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB1]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP10]]) @@ -2832,17 +2832,17 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG16:![0-9]+]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]], !dbg [[DBG16]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]], !dbg [[DBG16]] // CHECK5-NEXT: ret void, !dbg [[DBG17:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG18:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 !dbg [[DBG18:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG19:![0-9]+]] +// CHECK5-NEXT: call void @_ZN9TestClassD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG19:![0-9]+]] // CHECK5-NEXT: ret void, !dbg [[DBG20:![0-9]+]] // // @@ -2862,8 +2862,8 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG24:![0-9]+]] -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %class.TestClass], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG25:![0-9]+]] -// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS:%.*]], ptr [[ARRAY_BEGIN]], i64 2, !dbg [[DBG25]] +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[CLASS_TESTCLASS:%.*]]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG25:![0-9]+]] +// CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAY_BEGIN]], i64 2, !dbg [[DBG25]] // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]], !dbg [[DBG25]] // CHECK5: arrayctor.loop: // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[INVOKE_CONT:%.*]] ], !dbg [[DBG25]] @@ -2888,7 +2888,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG25]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG25]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG25]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]], !dbg [[DBG25]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG25]] // CHECK5: arraydestroy.done1: @@ -2912,7 +2912,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG28]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG28]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG28]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG28]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG28]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG28]] // CHECK5: arraydestroy.done1: @@ -2964,7 +2964,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[ARRAYCTOR_CUR]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG37]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG37]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG37]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG37]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG37]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG37]] // CHECK5: arraydestroy.done1: @@ -2986,7 +2986,7 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[CLASS_TESTCLASS:%.*]], ptr @tc2, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG42]] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[CLASS_TESTCLASS]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG42]] -// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG42]] +// CHECK5-NEXT: call void @_ZN9TestClassD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG42]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @tc2, !dbg [[DBG42]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG42]] // CHECK5: arraydestroy.done1: @@ -3005,7 +3005,7 @@ void array_func(int n, int a[n], St s[2]) { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN9TestClassD2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG46:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG46:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3192,16 +3192,16 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: store double 0.000000e+00, ptr [[A]], align 8, !dbg [[DBG83]] // CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SST]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG84:![0-9]+]] // CHECK5-NEXT: store ptr [[A3]], ptr [[A2]], align 8, !dbg [[DBG84]] -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !dbg [[DBG85:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8, !dbg [[DBG86:![0-9]+]] -// CHECK5-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8, !dbg [[DBG86]] -// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG86]] -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB18:[0-9]+]], i32 2, ptr @_ZN3SSTIdEC2Ev.omp_outlined, ptr [[THIS1]], i64 [[TMP2]]), !dbg [[DBG86]] -// CHECK5-NEXT: ret void, !dbg [[DBG87:![0-9]+]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A2]], align 8, !dbg [[DBG85:![0-9]+]], !nonnull [[META9:![0-9]+]], !align [[META86:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP0]], align 8, !dbg [[DBG87:![0-9]+]] +// CHECK5-NEXT: store double [[TMP1]], ptr [[A_CASTED]], align 8, !dbg [[DBG87]] +// CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG87]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB18:[0-9]+]], i32 2, ptr @_ZN3SSTIdEC2Ev.omp_outlined, ptr [[THIS1]], i64 [[TMP2]]), !dbg [[DBG87]] +// CHECK5-NEXT: ret void, !dbg [[DBG88:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN3SSTIdEC2Ev.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR10:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG88:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR10:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG89:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3216,45 +3216,45 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG89:![0-9]+]] -// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG89]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG90:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8, !dbg [[DBG91:![0-9]+]] -// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG91]] -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG91]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG91]] -// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB16:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG91]] -// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0, !dbg [[DBG91]] -// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG91]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG90:![0-9]+]] +// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG90]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG91:![0-9]+]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8, !dbg [[DBG92:![0-9]+]] +// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG92]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG92]] +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG92]] +// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB16:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG92]] +// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0, !dbg [[DBG92]] +// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG92]] // CHECK5: omp_if.then: -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG92:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8, !dbg [[DBG92]] -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG92]] -// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG93:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8, !dbg [[DBG92]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG93:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP6]], align 8, !dbg [[DBG93]] +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG93]] +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG94:![0-9]+]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8, !dbg [[DBG93]] // CHECK5-NEXT: invoke void @_ZZN3SSTIdEC1EvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG92]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG93]] // CHECK5: invoke.cont: -// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB16]], i32 [[TMP3]]), !dbg [[DBG92]] -// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG92]] -// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG92]] +// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB16]], i32 [[TMP3]]), !dbg [[DBG93]] +// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG93]] +// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG93]] // CHECK5: omp_if.end: -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG92]] -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG94:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8, !dbg [[DBG92]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG92]] -// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB16]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP11]]), !dbg [[DBG92]] -// CHECK5-NEXT: ret void, !dbg [[DBG95:![0-9]+]] +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG93]] +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG95:![0-9]+]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 8, !dbg [[DBG93]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG93]] +// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB16]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.5, i32 [[TMP11]]), !dbg [[DBG93]] +// CHECK5-NEXT: ret void, !dbg [[DBG96:![0-9]+]] // CHECK5: terminate.lpad: // CHECK5-NEXT: [[TMP12:%.*]] = landingpad { ptr, i32 } -// CHECK5-NEXT: catch ptr null, !dbg [[DBG92]] -// CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP12]], 0, !dbg [[DBG92]] -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP13]]) #[[ATTR11]], !dbg [[DBG92]] -// CHECK5-NEXT: unreachable, !dbg [[DBG92]] +// CHECK5-NEXT: catch ptr null, !dbg [[DBG93]] +// CHECK5-NEXT: [[TMP13:%.*]] = extractvalue { ptr, i32 } [[TMP12]], 0, !dbg [[DBG93]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP13]]) #[[ATTR11]], !dbg [[DBG93]] +// CHECK5-NEXT: unreachable, !dbg [[DBG93]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN3SSTIdEC1EvENKUlvE_clEv -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] align 2 !dbg [[DBG96:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR1]] align 2 !dbg [[DBG97:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 @@ -3262,36 +3262,36 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG97:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8, !dbg [[DBG97]] -// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG97]] -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG98:![0-9]+]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG98]] -// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8, !dbg [[DBG97]] -// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]), !dbg [[DBG97]] -// CHECK5-NEXT: ret void, !dbg [[DBG99:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG98:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[TMP2]], align 8, !dbg [[DBG98]] +// CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG98]] +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG99:![0-9]+]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG99]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: store ptr [[TMP5]], ptr [[TMP3]], align 8, !dbg [[DBG98]] +// CHECK5-NEXT: call void @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]), !dbg [[DBG98]] +// CHECK5-NEXT: ret void, !dbg [[DBG100:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.5 -// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG100:![0-9]+]] { +// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG101:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG101:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG101]] -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG101]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG101]] -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG101]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG101]] -// CHECK5-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8, !dbg [[DBG102:![0-9]+]] -// CHECK5-NEXT: store double [[TMP8]], ptr [[TMP5]], align 8, !dbg [[DBG102]] -// CHECK5-NEXT: ret void, !dbg [[DBG102]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG102:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG102]] +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG102]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG102]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG102]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG102]] +// CHECK5-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8, !dbg [[DBG103:![0-9]+]] +// CHECK5-NEXT: store double [[TMP8]], ptr [[TMP5]], align 8, !dbg [[DBG103]] +// CHECK5-NEXT: ret void, !dbg [[DBG103]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG105:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG106:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -3299,22 +3299,22 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG106:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG106]] -// CHECK5-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8, !dbg [[DBG107:![0-9]+]] -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG107]] -// CHECK5-NEXT: store double [[INC]], ptr [[TMP3]], align 8, !dbg [[DBG107]] -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG108:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG108]] -// CHECK5-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8, !dbg [[DBG109:![0-9]+]] -// CHECK5-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8, !dbg [[DBG109]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG109]] -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB22:[0-9]+]], i32 2, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP8]]), !dbg [[DBG109]] -// CHECK5-NEXT: ret void, !dbg [[DBG110:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG107:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG107]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 8, !dbg [[DBG108:![0-9]+]] +// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP4]], 1.000000e+00, !dbg [[DBG108]] +// CHECK5-NEXT: store double [[INC]], ptr [[TMP3]], align 8, !dbg [[DBG108]] +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG109:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG109]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8, !dbg [[DBG110:![0-9]+]] +// CHECK5-NEXT: store double [[TMP7]], ptr [[A_CASTED]], align 8, !dbg [[DBG110]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG110]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB22:[0-9]+]], i32 2, ptr @_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP8]]), !dbg [[DBG110]] +// CHECK5-NEXT: ret void, !dbg [[DBG111:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZZN3SSTIdEC1EvENKUlvE_clEvENKUlvE_clEv.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR10]] !dbg [[DBG111:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]]) #[[ATTR10]] !dbg [[DBG112:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3328,53 +3328,53 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG112:![0-9]+]] -// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG112]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG113:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8, !dbg [[DBG114:![0-9]+]] -// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG114]] -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG114]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG114]] -// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB20:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG114]] -// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0, !dbg [[DBG114]] -// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG114]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG113:![0-9]+]] +// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG113]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG114:![0-9]+]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP1]], align 8, !dbg [[DBG115:![0-9]+]] +// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG115]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG115]] +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG115]] +// CHECK5-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB20:[0-9]+]], i32 [[TMP3]]), !dbg [[DBG115]] +// CHECK5-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0, !dbg [[DBG115]] +// CHECK5-NEXT: br i1 [[TMP5]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG115]] // CHECK5: omp_if.then: -// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG113]] -// CHECK5-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8, !dbg [[DBG115:![0-9]+]] -// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00, !dbg [[DBG115]] -// CHECK5-NEXT: store double [[INC]], ptr [[TMP6]], align 8, !dbg [[DBG115]] -// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB20]], i32 [[TMP3]]), !dbg [[DBG115]] -// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG115]] -// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG115]] +// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG114]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: [[TMP7:%.*]] = load double, ptr [[TMP6]], align 8, !dbg [[DBG116:![0-9]+]] +// CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP7]], 1.000000e+00, !dbg [[DBG116]] +// CHECK5-NEXT: store double [[INC]], ptr [[TMP6]], align 8, !dbg [[DBG116]] +// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB20]], i32 [[TMP3]]), !dbg [[DBG116]] +// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG116]] +// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG116]] // CHECK5: omp_if.end: -// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG115]] -// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG116:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8, !dbg [[DBG115]] -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG115]] -// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB20]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP10]]), !dbg [[DBG115]] -// CHECK5-NEXT: ret void, !dbg [[DBG117:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG116]] +// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG117:![0-9]+]], !nonnull [[META9]], !align [[META86]] +// CHECK5-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8, !dbg [[DBG116]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG116]] +// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB20]], i32 [[TMP3]], i64 8, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.6, i32 [[TMP10]]), !dbg [[DBG116]] +// CHECK5-NEXT: ret void, !dbg [[DBG118:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.6 -// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG118:![0-9]+]] { +// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG119:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG119:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG119]] -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG119]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG119]] -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG119]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG119]] -// CHECK5-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8, !dbg [[DBG120:![0-9]+]] -// CHECK5-NEXT: store double [[TMP8]], ptr [[TMP5]], align 8, !dbg [[DBG120]] -// CHECK5-NEXT: ret void, !dbg [[DBG120]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG120:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG120]] +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG120]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG120]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG120]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG120]] +// CHECK5-NEXT: [[TMP8:%.*]] = load double, ptr [[TMP7]], align 8, !dbg [[DBG121:![0-9]+]] +// CHECK5-NEXT: store double [[TMP8]], ptr [[TMP5]], align 8, !dbg [[DBG121]] +// CHECK5-NEXT: ret void, !dbg [[DBG121]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG121:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[D:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG122:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8 @@ -3387,44 +3387,44 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG122:![0-9]+]] -// CHECK5-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG122]] -// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG123:![0-9]+]] -// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4, !dbg [[DBG123]] -// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG123]] -// CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0, !dbg [[DBG123]] -// CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4, !dbg [[DBG123]] -// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG124:![0-9]+]] -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG125:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP0]], ptr [[C]], align 8, !dbg [[DBG124]] -// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG126:![0-9]+]] -// CHECK5-NEXT: store ptr [[A3]], ptr [[A2]], align 8, !dbg [[DBG126]] -// CHECK5-NEXT: [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG127:![0-9]+]] -// CHECK5-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4, !dbg [[DBG127]] -// CHECK5-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4, !dbg [[DBG127]] -// CHECK5-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4, !dbg [[DBG127]] -// CHECK5-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32, !dbg [[DBG127]] -// CHECK5-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4, !dbg [[DBG127]] -// CHECK5-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG128:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !dbg [[DBG128]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8, !dbg [[DBG128]] -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !dbg [[DBG129:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG130:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4, !dbg [[DBG130]] -// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG130]] -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4, !dbg [[DBG130]] -// CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4, !dbg [[DBG130]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8, !dbg [[DBG130]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !dbg [[DBG131:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG130]] -// CHECK5-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4, !dbg [[DBG130]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8, !dbg [[DBG130]] -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB26:[0-9]+]], i32 4, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]]), !dbg [[DBG130]] -// CHECK5-NEXT: ret void, !dbg [[DBG132:![0-9]+]] +// CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG123:![0-9]+]] +// CHECK5-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG123]] +// CHECK5-NEXT: [[B:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG124:![0-9]+]] +// CHECK5-NEXT: [[BF_LOAD:%.*]] = load i8, ptr [[B]], align 4, !dbg [[DBG124]] +// CHECK5-NEXT: [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -16, !dbg [[DBG124]] +// CHECK5-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0, !dbg [[DBG124]] +// CHECK5-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4, !dbg [[DBG124]] +// CHECK5-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG125:![0-9]+]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG126:![0-9]+]], !nonnull [[META9]], !align [[META127:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP0]], ptr [[C]], align 8, !dbg [[DBG125]] +// CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG128:![0-9]+]] +// CHECK5-NEXT: store ptr [[A3]], ptr [[A2]], align 8, !dbg [[DBG128]] +// CHECK5-NEXT: [[B5:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG129:![0-9]+]] +// CHECK5-NEXT: [[BF_LOAD6:%.*]] = load i8, ptr [[B5]], align 4, !dbg [[DBG129]] +// CHECK5-NEXT: [[BF_SHL:%.*]] = shl i8 [[BF_LOAD6]], 4, !dbg [[DBG129]] +// CHECK5-NEXT: [[BF_ASHR:%.*]] = ashr i8 [[BF_SHL]], 4, !dbg [[DBG129]] +// CHECK5-NEXT: [[BF_CAST:%.*]] = sext i8 [[BF_ASHR]] to i32, !dbg [[DBG129]] +// CHECK5-NEXT: store i32 [[BF_CAST]], ptr [[B4]], align 4, !dbg [[DBG129]] +// CHECK5-NEXT: [[C8:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG130:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[C8]], align 8, !dbg [[DBG130]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[C7]], align 8, !dbg [[DBG130]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A2]], align 8, !dbg [[DBG131:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG132:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4, !dbg [[DBG132]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG132]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[B4]], align 4, !dbg [[DBG132]] +// CHECK5-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4, !dbg [[DBG132]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8, !dbg [[DBG132]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[C7]], align 8, !dbg [[DBG133:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG132]] +// CHECK5-NEXT: store i32 [[TMP8]], ptr [[C_CASTED]], align 4, !dbg [[DBG132]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8, !dbg [[DBG132]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB26:[0-9]+]], i32 4, ptr @_ZN2SSC2ERi.omp_outlined, ptr [[THIS1]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP9]]), !dbg [[DBG132]] +// CHECK5-NEXT: ret void, !dbg [[DBG134:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSC2ERi.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR10]] personality ptr @__gxx_personality_v0 !dbg [[DBG133:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR10]] personality ptr @__gxx_personality_v0 !dbg [[DBG135:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3445,58 +3445,58 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 // CHECK5-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG134:![0-9]+]] -// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG134]] -// CHECK5-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG134]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG135:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8, !dbg [[DBG136:![0-9]+]] -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG137:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8, !dbg [[DBG136]] -// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG136]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG136]] -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG136]] -// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB24:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG136]] -// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG136]] -// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG136]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG136:![0-9]+]] +// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG136]] +// CHECK5-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG136]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG137:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8, !dbg [[DBG138:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG139:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8, !dbg [[DBG138]] +// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG138]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG138]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG138]] +// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB24:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG138]] +// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG138]] +// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG138]] // CHECK5: omp_if.then: -// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG138:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG139:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG138]] -// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG139]] -// CHECK5-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !dbg [[DBG138]] +// CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 0, !dbg [[DBG140:![0-9]+]] +// CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 8, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 1, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG141:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 2, !dbg [[DBG140]] +// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP10]], align 8, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[REF_TMP]], i32 0, i32 3, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG141]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !dbg [[DBG140]] // CHECK5-NEXT: invoke void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG138]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG140]] // CHECK5: invoke.cont: -// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB24]], i32 [[TMP4]]), !dbg [[DBG138]] -// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG138]] -// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG138]] +// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB24]], i32 [[TMP4]]), !dbg [[DBG140]] +// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG140]] +// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG140]] // CHECK5: omp_if.end: -// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG140:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG138]] -// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG141:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG138]] -// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB24]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP18]]), !dbg [[DBG138]] -// CHECK5-NEXT: ret void, !dbg [[DBG142:![0-9]+]] +// CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG142:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG140]] +// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP15]], align 8, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG143:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG140]] +// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB24]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.7, i32 [[TMP18]]), !dbg [[DBG140]] +// CHECK5-NEXT: ret void, !dbg [[DBG144:![0-9]+]] // CHECK5: terminate.lpad: // CHECK5-NEXT: [[TMP19:%.*]] = landingpad { ptr, i32 } -// CHECK5-NEXT: catch ptr null, !dbg [[DBG138]] -// CHECK5-NEXT: [[TMP20:%.*]] = extractvalue { ptr, i32 } [[TMP19]], 0, !dbg [[DBG138]] -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP20]]) #[[ATTR11]], !dbg [[DBG138]] -// CHECK5-NEXT: unreachable, !dbg [[DBG138]] +// CHECK5-NEXT: catch ptr null, !dbg [[DBG140]] +// CHECK5-NEXT: [[TMP20:%.*]] = extractvalue { ptr, i32 } [[TMP19]], 0, !dbg [[DBG140]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP20]]) #[[ATTR11]], !dbg [[DBG140]] +// CHECK5-NEXT: unreachable, !dbg [[DBG140]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG143:![0-9]+]] { +// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(32) [[THIS:%.*]]) #[[ATTR2]] align 2 !dbg [[DBG145:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 @@ -3506,72 +3506,72 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG144:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG144]] -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG145:![0-9]+]] -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG145]] -// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4, !dbg [[DBG145]] -// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG146:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG146]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4, !dbg [[DBG147:![0-9]+]] -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1, !dbg [[DBG147]] -// CHECK5-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4, !dbg [[DBG147]] -// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG148:![0-9]+]] -// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !dbg [[DBG148]] -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG149:![0-9]+]] -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1, !dbg [[DBG149]] -// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4, !dbg [[DBG149]] -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG150:![0-9]+]] -// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG150]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG151:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4, !dbg [[DBG151]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG151]] -// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG152:![0-9]+]] -// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG152]] -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4, !dbg [[DBG151]] -// CHECK5-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4, !dbg [[DBG151]] -// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8, !dbg [[DBG151]] -// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG153:![0-9]+]] -// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG153]] -// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG151]] -// CHECK5-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4, !dbg [[DBG151]] -// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8, !dbg [[DBG151]] -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB30:[0-9]+]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]]), !dbg [[DBG151]] -// CHECK5-NEXT: ret void, !dbg [[DBG154:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG146:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG146]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG147:![0-9]+]] +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1, !dbg [[DBG147]] +// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4, !dbg [[DBG147]] +// CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG148:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !dbg [[DBG148]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4, !dbg [[DBG149:![0-9]+]] +// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1, !dbg [[DBG149]] +// CHECK5-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4, !dbg [[DBG149]] +// CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG150:![0-9]+]] +// CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !dbg [[DBG150]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4, !dbg [[DBG151:![0-9]+]] +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1, !dbg [[DBG151]] +// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4, !dbg [[DBG151]] +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 1, !dbg [[DBG152:![0-9]+]] +// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG152]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG153:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP13]], ptr [[A_CASTED]], align 4, !dbg [[DBG153]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i64, ptr [[A_CASTED]], align 8, !dbg [[DBG153]] +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 2, !dbg [[DBG154:![0-9]+]] +// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP15]], align 8, !dbg [[DBG154]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4, !dbg [[DBG153]] +// CHECK5-NEXT: store i32 [[TMP17]], ptr [[B_CASTED]], align 4, !dbg [[DBG153]] +// CHECK5-NEXT: [[TMP18:%.*]] = load i64, ptr [[B_CASTED]], align 8, !dbg [[DBG153]] +// CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_1]], ptr [[THIS1]], i32 0, i32 3, !dbg [[DBG155:![0-9]+]] +// CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP19]], align 8, !dbg [[DBG155]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG153]] +// CHECK5-NEXT: store i32 [[TMP21]], ptr [[C_CASTED]], align 4, !dbg [[DBG153]] +// CHECK5-NEXT: [[TMP22:%.*]] = load i64, ptr [[C_CASTED]], align 8, !dbg [[DBG153]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB30:[0-9]+]], i32 4, ptr @_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined, ptr [[TMP1]], i64 [[TMP14]], i64 [[TMP18]], i64 [[TMP22]]), !dbg [[DBG153]] +// CHECK5-NEXT: ret void, !dbg [[DBG156:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.7 -// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG155:![0-9]+]] { +// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG157:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG156:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG157:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP8]], ptr [[TMP5]], align 4, !dbg [[DBG157]] -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG158:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP13]], ptr [[TMP10]], align 4, !dbg [[DBG158]] -// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !dbg [[DBG156]] -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG159:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4, !dbg [[DBG159]] -// CHECK5-NEXT: ret void, !dbg [[DBG159]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG158:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG159:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP8]], ptr [[TMP5]], align 4, !dbg [[DBG159]] +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG160:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP13]], ptr [[TMP10]], align 4, !dbg [[DBG160]] +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !dbg [[DBG158]] +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG161:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4, !dbg [[DBG161]] +// CHECK5-NEXT: ret void, !dbg [[DBG161]] // // // CHECK5-LABEL: define {{[^@]+}}@_ZZN2SSC1ERiENKUlvE_clEv.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR10]] !dbg [[DBG160:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[A:%.*]], i64 noundef [[B:%.*]], i64 noundef [[C:%.*]]) #[[ATTR10]] !dbg [[DBG162:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 @@ -3591,121 +3591,121 @@ void array_func(int n, int a[n], St s[2]) { // CHECK5-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8 // CHECK5-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8 // CHECK5-NEXT: store i64 [[C]], ptr [[C_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG161:![0-9]+]] -// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG161]] -// CHECK5-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG161]] -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG162:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8, !dbg [[DBG163:![0-9]+]] -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG164:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8, !dbg [[DBG163]] -// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG163]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG163]] -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG163]] -// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB28:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG163]] -// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG163]] -// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG163]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8, !dbg [[DBG163:![0-9]+]] +// CHECK5-NEXT: store ptr [[A_ADDR]], ptr [[TMP]], align 8, !dbg [[DBG163]] +// CHECK5-NEXT: store ptr [[C_ADDR]], ptr [[_TMP1]], align 8, !dbg [[DBG163]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !dbg [[DBG164:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP1]], ptr [[_TMP2]], align 8, !dbg [[DBG165:![0-9]+]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8, !dbg [[DBG166:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP2]], ptr [[_TMP3]], align 8, !dbg [[DBG165]] +// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG165]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG165]] +// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG165]] +// CHECK5-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB28:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG165]] +// CHECK5-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG165]] +// CHECK5-NEXT: br i1 [[TMP6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG165]] // CHECK5: omp_if.then: -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG162]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG165:![0-9]+]] -// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1, !dbg [[DBG165]] -// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4, !dbg [[DBG165]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4, !dbg [[DBG166:![0-9]+]] -// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1, !dbg [[DBG166]] -// CHECK5-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4, !dbg [[DBG166]] -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG164]] -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG167:![0-9]+]] -// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG167]] -// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4, !dbg [[DBG167]] -// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB28]], i32 [[TMP4]]), !dbg [[DBG165]] -// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG165]] -// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG165]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG164]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG167:![0-9]+]] +// CHECK5-NEXT: [[INC:%.*]] = add nsw i32 [[TMP8]], 1, !dbg [[DBG167]] +// CHECK5-NEXT: store i32 [[INC]], ptr [[TMP7]], align 4, !dbg [[DBG167]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4, !dbg [[DBG168:![0-9]+]] +// CHECK5-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP9]], -1, !dbg [[DBG168]] +// CHECK5-NEXT: store i32 [[DEC]], ptr [[B_ADDR]], align 4, !dbg [[DBG168]] +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG166]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG169:![0-9]+]] +// CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 1, !dbg [[DBG169]] +// CHECK5-NEXT: store i32 [[DIV]], ptr [[TMP10]], align 4, !dbg [[DBG169]] +// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB28]], i32 [[TMP4]]), !dbg [[DBG167]] +// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG167]] +// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG167]] // CHECK5: omp_if.end: -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG165]] -// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG168:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !dbg [[DBG165]] -// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG165]] -// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8, !dbg [[DBG165]] -// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG165]] -// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG169:![0-9]+]] -// CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8, !dbg [[DBG165]] -// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG165]] -// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB28]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.8, i32 [[TMP17]]), !dbg [[DBG165]] -// CHECK5-NEXT: ret void, !dbg [[DBG170:![0-9]+]] +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 0, !dbg [[DBG167]] +// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG170:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !dbg [[DBG167]] +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 1, !dbg [[DBG167]] +// CHECK5-NEXT: store ptr [[B_ADDR]], ptr [[TMP14]], align 8, !dbg [[DBG167]] +// CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], i64 0, i64 2, !dbg [[DBG167]] +// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG171:![0-9]+]], !nonnull [[META9]], !align [[META127]] +// CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8, !dbg [[DBG167]] +// CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COPYPRIVATE_DID_IT]], align 4, !dbg [[DBG167]] +// CHECK5-NEXT: call void @__kmpc_copyprivate(ptr @[[GLOB28]], i32 [[TMP4]], i64 24, ptr [[DOTOMP_COPYPRIVATE_CPR_LIST]], ptr @.omp.copyprivate.copy_func.8, i32 [[TMP17]]), !dbg [[DBG167]] +// CHECK5-NEXT: ret void, !dbg [[DBG172:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@.omp.copyprivate.copy_func.8 -// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG171:![0-9]+]] { +// CHECK5-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR8]] !dbg [[DBG173:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK5-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG172:![0-9]+]] -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG173:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP8]], ptr [[TMP5]], align 4, !dbg [[DBG173]] -// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG174:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP13]], ptr [[TMP10]], align 4, !dbg [[DBG174]] -// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !dbg [[DBG172]] -// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG175:![0-9]+]] -// CHECK5-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4, !dbg [[DBG175]] -// CHECK5-NEXT: ret void, !dbg [[DBG175]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG174:![0-9]+]] +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 0, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG175:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP8]], ptr [[TMP5]], align 4, !dbg [[DBG175]] +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 1, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4, !dbg [[DBG176:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP13]], ptr [[TMP10]], align 4, !dbg [[DBG176]] +// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP2]], i64 0, i64 2, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[TMP3]], i64 0, i64 2, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8, !dbg [[DBG174]] +// CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4, !dbg [[DBG177:![0-9]+]] +// CHECK5-NEXT: store i32 [[TMP18]], ptr [[TMP15]], align 4, !dbg [[DBG177]] +// CHECK5-NEXT: ret void, !dbg [[DBG177]] // // // CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev -// CHECK5-SAME: () #[[ATTR2]] !dbg [[DBG176:![0-9]+]] { +// CHECK5-SAME: () #[[ATTR2]] !dbg [[DBG178:![0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB35:[0-9]+]], i32 0, ptr @_Z15parallel_singlev.omp_outlined), !dbg [[DBG177:![0-9]+]] -// CHECK5-NEXT: ret void, !dbg [[DBG178:![0-9]+]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB35:[0-9]+]], i32 0, ptr @_Z15parallel_singlev.omp_outlined), !dbg [[DBG179:![0-9]+]] +// CHECK5-NEXT: ret void, !dbg [[DBG180:![0-9]+]] // // // CHECK5-LABEL: define {{[^@]+}}@_Z15parallel_singlev.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR10]] personality ptr @__gxx_personality_v0 !dbg [[DBG179:![0-9]+]] { +// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR10]] personality ptr @__gxx_personality_v0 !dbg [[DBG181:![0-9]+]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG180:![0-9]+]] -// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG180]] -// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB32:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG180]] -// CHECK5-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG180]] -// CHECK5-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG180]] +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG182:![0-9]+]] +// CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG182]] +// CHECK5-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB32:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG182]] +// CHECK5-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG182]] +// CHECK5-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]], !dbg [[DBG182]] // CHECK5: omp_if.then: // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG181:![0-9]+]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG183:![0-9]+]] // CHECK5: invoke.cont: -// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB32]], i32 [[TMP1]]), !dbg [[DBG181]] -// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG181]] +// CHECK5-NEXT: call void @__kmpc_end_single(ptr @[[GLOB32]], i32 [[TMP1]]), !dbg [[DBG183]] +// CHECK5-NEXT: br label [[OMP_IF_END]], !dbg [[DBG183]] // CHECK5: omp_if.end: -// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB33:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG182:![0-9]+]] -// CHECK5-NEXT: ret void, !dbg [[DBG182]] +// CHECK5-NEXT: call void @__kmpc_barrier(ptr @[[GLOB33:[0-9]+]], i32 [[TMP1]]), !dbg [[DBG184:![0-9]+]] +// CHECK5-NEXT: ret void, !dbg [[DBG184]] // CHECK5: terminate.lpad: // CHECK5-NEXT: [[TMP4:%.*]] = landingpad { ptr, i32 } -// CHECK5-NEXT: catch ptr null, !dbg [[DBG181]] -// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG181]] -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR11]], !dbg [[DBG181]] -// CHECK5-NEXT: unreachable, !dbg [[DBG181]] +// CHECK5-NEXT: catch ptr null, !dbg [[DBG183]] +// CHECK5-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP4]], 0, !dbg [[DBG183]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP5]]) #[[ATTR11]], !dbg [[DBG183]] +// CHECK5-NEXT: unreachable, !dbg [[DBG183]] // // // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_single_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG183:![0-9]+]] { +// CHECK5-SAME: () #[[ATTR0]] section "__TEXT,__StaticInit,regular,pure_instructions" !dbg [[DBG185:![0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG184:![0-9]+]] -// CHECK5-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG184]] -// CHECK5-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG184]] -// CHECK5-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG184]] +// CHECK5-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG186:![0-9]+]] +// CHECK5-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG186]] +// CHECK5-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG186]] +// CHECK5-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG186]] // CHECK5-NEXT: ret void // // diff --git a/clang/test/OpenMP/single_firstprivate_codegen.cpp b/clang/test/OpenMP/single_firstprivate_codegen.cpp index 31ea1ca4952fc..5cc7ef1706afb 100644 --- a/clang/test/OpenMP/single_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/single_firstprivate_codegen.cpp @@ -152,12 +152,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -175,7 +175,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -214,7 +214,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -252,9 +252,9 @@ int main() { // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP2:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) @@ -266,7 +266,7 @@ int main() { // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr @t_var, align 4 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[T_VAR]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @vec, i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -275,7 +275,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] @@ -283,23 +283,23 @@ int main() { // CHECK1: omp.arraycpy.done1: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR]], ptr nonnull align 4 dereferenceable(4) @var, ptr [[AGG_TMP2]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP2]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 41, ptr [[SIVAR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[OMP_ARRAYCPY_DONE1]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -336,12 +336,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -352,7 +352,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -363,18 +363,18 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr nonnull align 4 dereferenceable(4) [[VAR]], i32 3) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[T_VAR]], ptr [[VEC]], ptr [[S_ARR]], ptr [[VAR]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -415,7 +415,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -457,9 +457,9 @@ int main() { // CHECK1-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -480,7 +480,7 @@ int main() { // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[T_VAR1]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP1]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP9]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -489,7 +489,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[OMP_IF_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] @@ -497,20 +497,20 @@ int main() { // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR5]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP11]], [[OMP_ARRAYCPY_DONE4]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -537,12 +537,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -596,7 +596,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -632,12 +632,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -655,7 +655,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -694,7 +694,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -766,12 +766,12 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK4-NEXT: ret void // // @@ -789,7 +789,7 @@ int main() { // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK4-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -828,7 +828,7 @@ int main() { // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK4-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done1: diff --git a/clang/test/OpenMP/single_private_codegen.cpp b/clang/test/OpenMP/single_private_codegen.cpp index 9ae000f142abe..bc83b4638e18e 100644 --- a/clang/test/OpenMP/single_private_codegen.cpp +++ b/clang/test/OpenMP/single_private_codegen.cpp @@ -98,7 +98,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -111,18 +111,18 @@ int main() { // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @main.omp_outlined) // CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK1-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -157,8 +157,8 @@ int main() { // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -168,7 +168,7 @@ int main() { // CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -182,17 +182,17 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 303, ptr [[SIVAR]], align 4 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -204,12 +204,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // @@ -220,7 +220,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) // CHECK1-NEXT: store i32 0, ptr [[T_VAR]], align 4 @@ -231,18 +231,18 @@ int main() { // CHECK1-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]], i32 noundef 3) // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP0]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR5]] // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP1]] // @@ -273,7 +273,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -311,8 +311,8 @@ int main() { // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -321,7 +321,7 @@ int main() { // CHECK1-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0 // CHECK1-NEXT: br i1 [[TMP3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -335,16 +335,16 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -356,12 +356,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR5]] // CHECK1-NEXT: ret void // // @@ -391,7 +391,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/target_has_device_addr_codegen.cpp b/clang/test/OpenMP/target_has_device_addr_codegen.cpp index 39eaedb0e48d1..cbd44fa131d68 100644 --- a/clang/test/OpenMP/target_has_device_addr_codegen.cpp +++ b/clang/test/OpenMP/target_has_device_addr_codegen.cpp @@ -275,7 +275,7 @@ void use_template() { // CHECK-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DA:%.*]] = alloca [5 x i32], align 4 -// CHECK-NEXT: [[H:%.*]] = alloca [10 x %struct.S6], align 4 +// CHECK-NEXT: [[H:%.*]] = alloca [10 x [[STRUCT_S6:%.*]]], align 4 // CHECK-NEXT: [[RH:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[J:%.*]] = alloca ptr, align 8 @@ -315,7 +315,7 @@ void use_template() { // CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[DA]], i8 0, i64 20, i1 false) // CHECK-NEXT: store ptr [[H]], ptr [[RH]], align 8 // CHECK-NEXT: store ptr [[I]], ptr [[J]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8, !nonnull [[META33:![0-9]+]], !align [[META34:![0-9]+]] // CHECK-NEXT: store ptr [[TMP0]], ptr [[K]], align 8 // CHECK-NEXT: store ptr [[K]], ptr [[Z]], align 8 // CHECK-NEXT: store ptr [[AA]], ptr [[RAA]], align 8 @@ -360,9 +360,9 @@ void use_template() { // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l145(ptr [[K]]) #[[ATTR5:[0-9]+]] // CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK: omp_offload.cont: -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[Z]], align 8 +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META33]], !align [[META35:![0-9]+]] // CHECK-NEXT: store ptr [[TMP21]], ptr [[TMP]], align 8 -// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 // CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP23]], align 8 // CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 @@ -445,9 +445,9 @@ void use_template() { // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l149(ptr [[AA]]) #[[ATTR5]] // CHECK-NEXT: br label [[OMP_OFFLOAD_CONT12]] // CHECK: omp_offload.cont12: -// CHECK-NEXT: [[TMP63:%.*]] = load ptr, ptr [[RAA]], align 8 +// CHECK-NEXT: [[TMP63:%.*]] = load ptr, ptr [[RAA]], align 8, !nonnull [[META33]], !align [[META34]] // CHECK-NEXT: store ptr [[TMP63]], ptr [[_TMP13]], align 8 -// CHECK-NEXT: [[TMP64:%.*]] = load ptr, ptr [[_TMP13]], align 8 +// CHECK-NEXT: [[TMP64:%.*]] = load ptr, ptr [[_TMP13]], align 8, !nonnull [[META33]], !align [[META34]] // CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 // CHECK-NEXT: store ptr [[TMP64]], ptr [[TMP65]], align 8 // CHECK-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 @@ -584,7 +584,7 @@ void use_template() { // CHECK-NEXT: entry: // CHECK-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP1]], i32 1 // CHECK-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8 @@ -597,9 +597,9 @@ void use_template() { // CHECK-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Z_ADDR]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 // CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP2]], i32 1 // CHECK-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 8 @@ -611,7 +611,7 @@ void use_template() { // CHECK-NEXT: entry: // CHECK-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META33]], !align [[META34]] // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 0 // CHECK-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: ret void @@ -624,9 +624,9 @@ void use_template() { // CHECK-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[RAA]], ptr [[RAA_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RAA_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RAA_ADDR]], align 8, !nonnull [[META33]], !align [[META34]] // CHECK-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META33]], !align [[META34]] // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 0 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 @@ -639,9 +639,9 @@ void use_template() { // CHECK-NEXT: [[H_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[H]], ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], i64 0, i64 1 -// CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S6:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8, !nonnull [[META33]], !align [[META34]] +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [[STRUCT_S6:%.*]]], ptr [[TMP0]], i64 0, i64 1 +// CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S6]], ptr [[ARRAYIDX]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A1]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 // CHECK-NEXT: ret void @@ -653,7 +653,7 @@ void use_template() { // CHECK-NEXT: [[DA_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[DA]], ptr [[DA_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DA_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DA_ADDR]], align 8, !nonnull [[META33]], !align [[META34]] // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x i32], ptr [[TMP0]], i64 0, i64 1 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 @@ -665,7 +665,7 @@ void use_template() { // CHECK-NEXT: entry: // CHECK-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[DA:%.*]] = alloca [5 x i32], align 4 -// CHECK-NEXT: [[H:%.*]] = alloca [10 x %struct.S6], align 4 +// CHECK-NEXT: [[H:%.*]] = alloca [10 x [[STRUCT_S6:%.*]]], align 4 // CHECK-NEXT: [[RH:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK-NEXT: [[J:%.*]] = alloca ptr, align 8 @@ -693,7 +693,7 @@ void use_template() { // CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[DA]], i8 0, i64 20, i1 false) // CHECK-NEXT: store ptr [[H]], ptr [[RH]], align 8 // CHECK-NEXT: store ptr [[I]], ptr [[J]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8, !nonnull [[META33]], !align [[META34]] // CHECK-NEXT: store ptr [[TMP0]], ptr [[K]], align 8 // CHECK-NEXT: store ptr [[K]], ptr [[Z]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 @@ -737,9 +737,9 @@ void use_template() { // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_S0__l123(ptr [[K]]) #[[ATTR5]] // CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK: omp_offload.cont: -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[Z]], align 8 +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: store ptr [[TMP21]], ptr [[TMP]], align 8 -// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 // CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP23]], align 8 // CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 @@ -871,7 +871,7 @@ void use_template() { // CHECK-NEXT: entry: // CHECK-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[DA:%.*]] = alloca [5 x ptr], align 8 -// CHECK-NEXT: [[H:%.*]] = alloca [10 x %struct.S6], align 4 +// CHECK-NEXT: [[H:%.*]] = alloca [10 x [[STRUCT_S6:%.*]]], align 4 // CHECK-NEXT: [[RH:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[I:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[J:%.*]] = alloca ptr, align 8 @@ -899,7 +899,7 @@ void use_template() { // CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[DA]], i8 0, i64 40, i1 false) // CHECK-NEXT: store ptr [[H]], ptr [[RH]], align 8 // CHECK-NEXT: store ptr [[I]], ptr [[J]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: store ptr [[TMP0]], ptr [[K]], align 8 // CHECK-NEXT: store ptr [[K]], ptr [[Z]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 @@ -943,9 +943,9 @@ void use_template() { // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIPiET_S1__l123(ptr [[K]]) #[[ATTR5]] // CHECK-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK: omp_offload.cont: -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[Z]], align 8 +// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: store ptr [[TMP21]], ptr [[TMP]], align 8 -// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK-NEXT: [[TMP22:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS1]], i32 0, i32 0 // CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP23]], align 8 // CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS2]], i32 0, i32 0 @@ -1077,7 +1077,7 @@ void use_template() { // CHECK-NEXT: entry: // CHECK-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP1]], i32 1 // CHECK-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8 @@ -1090,9 +1090,9 @@ void use_template() { // CHECK-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Z_ADDR]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 // CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP2]], i32 1 // CHECK-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 8 @@ -1105,7 +1105,7 @@ void use_template() { // CHECK-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META33]], !align [[META34]] // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 @@ -1118,9 +1118,9 @@ void use_template() { // CHECK-NEXT: [[H_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[H]], ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], i64 0, i64 0 -// CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S6:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8, !nonnull [[META33]], !align [[META34]] +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [[STRUCT_S6:%.*]]], ptr [[TMP0]], i64 0, i64 0 +// CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S6]], ptr [[ARRAYIDX]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A1]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 // CHECK-NEXT: ret void @@ -1131,7 +1131,7 @@ void use_template() { // CHECK-NEXT: entry: // CHECK-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw ptr, ptr [[TMP1]], i32 1 // CHECK-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP0]], align 8 @@ -1144,9 +1144,9 @@ void use_template() { // CHECK-NEXT: [[Z_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[Z]], ptr [[Z_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Z_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[Z_ADDR]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP1]], align 8 // CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw ptr, ptr [[TMP2]], i32 1 // CHECK-NEXT: store ptr [[INCDEC_PTR]], ptr [[TMP1]], align 8 @@ -1159,7 +1159,7 @@ void use_template() { // CHECK-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8, !nonnull [[META33]], !align [[META35]] // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[TMP0]], i64 0, i64 0 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 // CHECK-NEXT: store ptr [[TMP1]], ptr [[A]], align 8 @@ -1172,9 +1172,9 @@ void use_template() { // CHECK-NEXT: [[H_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[H]], ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], i64 0, i64 0 -// CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S6:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8, !nonnull [[META33]], !align [[META34]] +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [[STRUCT_S6:%.*]]], ptr [[TMP0]], i64 0, i64 0 +// CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S6]], ptr [[ARRAYIDX]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A1]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 // CHECK-NEXT: ret void @@ -1186,7 +1186,7 @@ void use_template() { // CHECK-NEXT: [[AKERN:%.*]] = alloca [[STRUCT_SOMEKERNEL:%.*]], align 4 // CHECK-NEXT: call void @_ZN10SomeKernelC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) // CHECK-NEXT: call void @_ZN10SomeKernel5applyILj32EEEvv(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) -// CHECK-NEXT: call void @_ZN10SomeKernelD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) #[[ATTR5]] +// CHECK-NEXT: call void @_ZN10SomeKernelD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AKERN]]) #[[ATTR5]] // CHECK-NEXT: ret void // // @@ -1306,7 +1306,7 @@ void use_template() { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1 // CHECK-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0 -// CHECK-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF18:![0-9]+]] +// CHECK-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF36:![0-9]+]] // CHECK: init: // CHECK-NEXT: store i8 1, ptr @__tls_guard, align 1 // CHECK-NEXT: call void @__cxx_global_var_init.4() @@ -1398,7 +1398,7 @@ void use_template() { // SIMD-ONLY0-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[DA:%.*]] = alloca [5 x i32], align 4 -// SIMD-ONLY0-NEXT: [[H:%.*]] = alloca [10 x %struct.S6], align 4 +// SIMD-ONLY0-NEXT: [[H:%.*]] = alloca [10 x [[STRUCT_S6:%.*]]], align 4 // SIMD-ONLY0-NEXT: [[RH:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[J:%.*]] = alloca ptr, align 8 @@ -1417,31 +1417,31 @@ void use_template() { // SIMD-ONLY0-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[DA]], i8 0, i64 20, i1 false) // SIMD-ONLY0-NEXT: store ptr [[H]], ptr [[RH]], align 8 // SIMD-ONLY0-NEXT: store ptr [[I]], ptr [[J]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8, !nonnull [[META2:![0-9]+]], !align [[META3:![0-9]+]] // SIMD-ONLY0-NEXT: store ptr [[TMP0]], ptr [[K]], align 8 // SIMD-ONLY0-NEXT: store ptr [[K]], ptr [[Z]], align 8 // SIMD-ONLY0-NEXT: store ptr [[AA]], ptr [[RAA]], align 8 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load ptr, ptr [[K]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP1]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR]], ptr [[K]], align 8 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[Z]], align 8 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META2]], !align [[META4:![0-9]+]] // SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[Z]], align 8 -// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META2]], !align [[META4]] +// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META4]] // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[AA]], i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[RAA]], align 8 +// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[RAA]], align 8, !nonnull [[META2]], !align [[META3]] // SIMD-ONLY0-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8 -// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load ptr, ptr [[RAA]], align 8 -// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load ptr, ptr [[RAA]], align 8, !nonnull [[META2]], !align [[META3]] +// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META2]], !align [[META3]] // SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP8]], i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX3]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP9]], ptr [[A]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], i64 0, i64 1 -// SIMD-ONLY0-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S6:%.*]], ptr [[ARRAYIDX5]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x [[STRUCT_S6]]], ptr [[H]], i64 0, i64 1 +// SIMD-ONLY0-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S6]], ptr [[ARRAYIDX5]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[A6]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP10]], ptr [[A4]], align 4 // SIMD-ONLY0-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x i32], ptr [[DA]], i64 0, i64 1 @@ -1460,7 +1460,7 @@ void use_template() { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[DA:%.*]] = alloca [5 x i32], align 4 -// SIMD-ONLY0-NEXT: [[H:%.*]] = alloca [10 x %struct.S6], align 4 +// SIMD-ONLY0-NEXT: [[H:%.*]] = alloca [10 x [[STRUCT_S6:%.*]]], align 4 // SIMD-ONLY0-NEXT: [[RH:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca i32, align 4 // SIMD-ONLY0-NEXT: [[J:%.*]] = alloca ptr, align 8 @@ -1474,24 +1474,24 @@ void use_template() { // SIMD-ONLY0-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[DA]], i8 0, i64 20, i1 false) // SIMD-ONLY0-NEXT: store ptr [[H]], ptr [[RH]], align 8 // SIMD-ONLY0-NEXT: store ptr [[I]], ptr [[J]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8, !nonnull [[META2]], !align [[META3]] // SIMD-ONLY0-NEXT: store ptr [[TMP0]], ptr [[K]], align 8 // SIMD-ONLY0-NEXT: store ptr [[K]], ptr [[Z]], align 8 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load ptr, ptr [[K]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP1]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR]], ptr [[K]], align 8 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[Z]], align 8 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META2]], !align [[META4]] // SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[Z]], align 8 -// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META2]], !align [[META4]] +// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META4]] // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds nuw i32, ptr [[TMP5]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[AA]], i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP6]], ptr [[A]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S6:%.*]], ptr [[ARRAYIDX3]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [[STRUCT_S6]]], ptr [[H]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S6]], ptr [[ARRAYIDX3]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[A4]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP7]], ptr [[A2]], align 4 // SIMD-ONLY0-NEXT: ret i32 0 @@ -1502,7 +1502,7 @@ void use_template() { // SIMD-ONLY0-NEXT: entry: // SIMD-ONLY0-NEXT: [[ARGC_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[DA:%.*]] = alloca [5 x ptr], align 8 -// SIMD-ONLY0-NEXT: [[H:%.*]] = alloca [10 x %struct.S6], align 4 +// SIMD-ONLY0-NEXT: [[H:%.*]] = alloca [10 x [[STRUCT_S6:%.*]]], align 4 // SIMD-ONLY0-NEXT: [[RH:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[I:%.*]] = alloca ptr, align 8 // SIMD-ONLY0-NEXT: [[J:%.*]] = alloca ptr, align 8 @@ -1516,24 +1516,24 @@ void use_template() { // SIMD-ONLY0-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[DA]], i8 0, i64 40, i1 false) // SIMD-ONLY0-NEXT: store ptr [[H]], ptr [[RH]], align 8 // SIMD-ONLY0-NEXT: store ptr [[I]], ptr [[J]], align 8 -// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8 +// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J]], align 8, !nonnull [[META2]], !align [[META4]] // SIMD-ONLY0-NEXT: store ptr [[TMP0]], ptr [[K]], align 8 // SIMD-ONLY0-NEXT: store ptr [[K]], ptr [[Z]], align 8 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load ptr, ptr [[K]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds nuw ptr, ptr [[TMP1]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR]], ptr [[K]], align 8 -// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[Z]], align 8 +// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META2]], !align [[META4]] // SIMD-ONLY0-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[Z]], align 8 -// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load ptr, ptr [[Z]], align 8, !nonnull [[META2]], !align [[META4]] +// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META2]], !align [[META4]] // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds nuw ptr, ptr [[TMP5]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[AA]], i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 // SIMD-ONLY0-NEXT: store ptr [[TMP6]], ptr [[A]], align 8 -// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], i64 0, i64 0 -// SIMD-ONLY0-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S6:%.*]], ptr [[ARRAYIDX3]], i32 0, i32 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [[STRUCT_S6]]], ptr [[H]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[A4:%.*]] = getelementptr inbounds nuw [[STRUCT_S6]], ptr [[ARRAYIDX3]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[A4]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP7]], ptr [[A2]], align 4 // SIMD-ONLY0-NEXT: ret ptr null @@ -1545,7 +1545,7 @@ void use_template() { // SIMD-ONLY0-NEXT: [[AKERN:%.*]] = alloca [[STRUCT_SOMEKERNEL:%.*]], align 4 // SIMD-ONLY0-NEXT: call void @_ZN10SomeKernelC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) // SIMD-ONLY0-NEXT: call void @_ZN10SomeKernel5applyILj32EEEvv(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) -// SIMD-ONLY0-NEXT: call void @_ZN10SomeKernelD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AKERN]]) #[[ATTR6:[0-9]+]] +// SIMD-ONLY0-NEXT: call void @_ZN10SomeKernelD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AKERN]]) #[[ATTR6:[0-9]+]] // SIMD-ONLY0-NEXT: ret void // // diff --git a/clang/test/OpenMP/target_in_reduction_codegen.cpp b/clang/test/OpenMP/target_in_reduction_codegen.cpp index 4748d5d7d2102..5550634a50928 100644 --- a/clang/test/OpenMP/target_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/target_in_reduction_codegen.cpp @@ -164,7 +164,7 @@ int main(int argc, char **argv) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP60]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -300,7 +300,7 @@ int main(int argc, char **argv) { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #3 +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #3 // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -308,12 +308,12 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #3 +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #3 // CHECK1-NEXT: ret void // // @@ -335,7 +335,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP3]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #3 +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #3 // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]] @@ -589,7 +589,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/target_parallel_generic_loop_codegen-1.cpp b/clang/test/OpenMP/target_parallel_generic_loop_codegen-1.cpp index caafd8b9cf2f9..61f722b10a74f 100644 --- a/clang/test/OpenMP/target_parallel_generic_loop_codegen-1.cpp +++ b/clang/test/OpenMP/target_parallel_generic_loop_codegen-1.cpp @@ -1461,12 +1461,12 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SAD1Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-NEXT: call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-NEXT: call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-NEXT: ret void // // @@ -1490,7 +1490,7 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SAD2Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1535,12 +1535,12 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SBD1Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-NEXT: call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-NEXT: call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-NEXT: ret void // // @@ -1564,7 +1564,7 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SBD2Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1609,12 +1609,12 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SCD1Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-NEXT: call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-NEXT: call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-NEXT: ret void // // @@ -1718,7 +1718,7 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SCD2Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1755,12 +1755,12 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SDD1Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-NEXT: call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-NEXT: call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-NEXT: ret void // // @@ -1784,7 +1784,7 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SDD2Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -1901,12 +1901,12 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SED1Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-NEXT: call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-NEXT: call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-NEXT: ret void // // @@ -2010,7 +2010,7 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2SED2Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2127,12 +2127,12 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi100EED1Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-NEXT: call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-NEXT: call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-NEXT: ret void // // @@ -2236,7 +2236,7 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi100EED2Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2353,12 +2353,12 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi1000EED1Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-NEXT: call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-NEXT: call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-NEXT: ret void // // @@ -2462,7 +2462,7 @@ int bar(int a){ // // // CHECK-NTARGET-LABEL: define {{[^@]+}}@_ZN2STILi1000EED2Ev -// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { +// CHECK-NTARGET-SAME: (ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] comdat { // CHECK-NTARGET-NEXT: entry: // CHECK-NTARGET-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -2918,12 +2918,12 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SAD1Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY2-NEXT: call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]]) #[[ATTR2]] +// SIMD-ONLY2-NEXT: call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR2]] // SIMD-ONLY2-NEXT: ret void // // @@ -2954,12 +2954,12 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SBD1Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY2-NEXT: call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]]) #[[ATTR2]] +// SIMD-ONLY2-NEXT: call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS1]]) #[[ATTR2]] // SIMD-ONLY2-NEXT: ret void // // @@ -2990,12 +2990,12 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SCD1Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY2-NEXT: call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]]) #[[ATTR2]] +// SIMD-ONLY2-NEXT: call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS1]]) #[[ATTR2]] // SIMD-ONLY2-NEXT: ret void // // @@ -3018,12 +3018,12 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SDD1Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY2-NEXT: call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]]) #[[ATTR2]] +// SIMD-ONLY2-NEXT: call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS1]]) #[[ATTR2]] // SIMD-ONLY2-NEXT: ret void // // @@ -3046,12 +3046,12 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SED1Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY2-NEXT: call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]]) #[[ATTR2]] +// SIMD-ONLY2-NEXT: call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS1]]) #[[ATTR2]] // SIMD-ONLY2-NEXT: ret void // // @@ -3074,12 +3074,12 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi100EED1Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY2-NEXT: call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]]) #[[ATTR2]] +// SIMD-ONLY2-NEXT: call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS1]]) #[[ATTR2]] // SIMD-ONLY2-NEXT: ret void // // @@ -3102,12 +3102,12 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi1000EED1Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD-ONLY2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD-ONLY2-NEXT: call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]]) #[[ATTR2]] +// SIMD-ONLY2-NEXT: call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS1]]) #[[ATTR2]] // SIMD-ONLY2-NEXT: ret void // // @@ -3366,7 +3366,7 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SAD2Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3404,7 +3404,7 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SBD2Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3457,7 +3457,7 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SCD2Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3495,7 +3495,7 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SDD2Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3563,7 +3563,7 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2SED2Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3631,7 +3631,7 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi100EED2Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -3699,7 +3699,7 @@ int bar(int a){ // // // SIMD-ONLY2-LABEL: define {{[^@]+}}@_ZN2STILi1000EED2Ev -// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// SIMD-ONLY2-SAME: (ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // SIMD-ONLY2-NEXT: entry: // SIMD-ONLY2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD-ONLY2-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4001,12 +4001,12 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SAD1Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // OMP-DEfAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// OMP-DEfAULT-NEXT: call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]]) #[[ATTR2]] +// OMP-DEfAULT-NEXT: call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR2]] // OMP-DEfAULT-NEXT: ret void // // @@ -4030,7 +4030,7 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SAD2Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4075,12 +4075,12 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SBD1Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // OMP-DEfAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// OMP-DEfAULT-NEXT: call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]]) #[[ATTR2]] +// OMP-DEfAULT-NEXT: call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS1]]) #[[ATTR2]] // OMP-DEfAULT-NEXT: ret void // // @@ -4104,7 +4104,7 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SBD2Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4149,12 +4149,12 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SCD1Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // OMP-DEfAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// OMP-DEfAULT-NEXT: call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]]) #[[ATTR2]] +// OMP-DEfAULT-NEXT: call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS1]]) #[[ATTR2]] // OMP-DEfAULT-NEXT: ret void // // @@ -4302,7 +4302,7 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SCD2Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4339,12 +4339,12 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SDD1Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // OMP-DEfAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// OMP-DEfAULT-NEXT: call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]]) #[[ATTR2]] +// OMP-DEfAULT-NEXT: call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS1]]) #[[ATTR2]] // OMP-DEfAULT-NEXT: ret void // // @@ -4368,7 +4368,7 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SDD2Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4529,12 +4529,12 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SED1Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // OMP-DEfAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// OMP-DEfAULT-NEXT: call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]]) #[[ATTR2]] +// OMP-DEfAULT-NEXT: call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS1]]) #[[ATTR2]] // OMP-DEfAULT-NEXT: ret void // // @@ -4682,7 +4682,7 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2SED2Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -4843,12 +4843,12 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EED1Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // OMP-DEfAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// OMP-DEfAULT-NEXT: call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]]) #[[ATTR2]] +// OMP-DEfAULT-NEXT: call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS1]]) #[[ATTR2]] // OMP-DEfAULT-NEXT: ret void // // @@ -4996,7 +4996,7 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EED2Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -5157,12 +5157,12 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EED1Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // OMP-DEfAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// OMP-DEfAULT-NEXT: call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]]) #[[ATTR2]] +// OMP-DEfAULT-NEXT: call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS1]]) #[[ATTR2]] // OMP-DEfAULT-NEXT: ret void // // @@ -5310,7 +5310,7 @@ int bar(int a){ // // // OMP-DEfAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EED2Ev -// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// OMP-DEfAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // OMP-DEfAULT-NEXT: entry: // OMP-DEfAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // OMP-DEfAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6680,12 +6680,12 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SAD1Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dereferenceable(16) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SAD2Ev(ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-OMP-DEFAULT-NEXT: ret void // // @@ -6709,7 +6709,7 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SAD2Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6754,12 +6754,12 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SBD1Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dereferenceable(32) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SBD2Ev(ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-OMP-DEFAULT-NEXT: ret void // // @@ -6783,7 +6783,7 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SBD2Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(32) dereferenceable(32) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6828,12 +6828,12 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SCD1Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dereferenceable(64) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SCD2Ev(ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-OMP-DEFAULT-NEXT: ret void // // @@ -6937,7 +6937,7 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SCD2Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(64) dereferenceable(64) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -6974,12 +6974,12 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SDD1Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dereferenceable(128) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SDD2Ev(ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-OMP-DEFAULT-NEXT: ret void // // @@ -7003,7 +7003,7 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SDD2Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(128) dereferenceable(128) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7120,12 +7120,12 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SED1Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dereferenceable(256) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2SED2Ev(ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-OMP-DEFAULT-NEXT: ret void // // @@ -7229,7 +7229,7 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2SED2Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(256) dereferenceable(256) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7346,12 +7346,12 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EED1Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dereferenceable(912) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2STILi100EED2Ev(ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-OMP-DEFAULT-NEXT: ret void // // @@ -7455,7 +7455,7 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi100EED2Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(912) dereferenceable(912) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -7572,12 +7572,12 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EED1Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dereferenceable(4512) [[THIS1]]) #[[ATTR2]] +// CHECK-NTARGET-OMP-DEFAULT-NEXT: call void @_ZN2STILi1000EED2Ev(ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS1]]) #[[ATTR2]] // CHECK-NTARGET-OMP-DEFAULT-NEXT: ret void // // @@ -7681,7 +7681,7 @@ int bar(int a){ // // // CHECK-NTARGET-OMP-DEFAULT-LABEL: define {{[^@]+}}@_ZN2STILi1000EED2Ev -// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK-NTARGET-OMP-DEFAULT-SAME: (ptr noundef nonnull align 4 dead_on_return(4512) dereferenceable(4512) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK-NTARGET-OMP-DEFAULT-NEXT: entry: // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NTARGET-OMP-DEFAULT-NEXT: [[A:%.*]] = alloca i32, align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp index a171827a18646..ac6e16933828e 100644 --- a/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp @@ -158,12 +158,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -181,7 +181,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -220,7 +220,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -384,9 +384,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -404,7 +404,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -413,7 +413,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -421,7 +421,7 @@ int main() { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -458,7 +458,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false) // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -478,14 +478,14 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -518,12 +518,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -534,7 +534,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -616,17 +616,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP34]] // @@ -667,7 +667,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -740,9 +740,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -761,7 +761,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -770,7 +770,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -779,7 +779,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -818,7 +818,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -834,14 +834,14 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -864,12 +864,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -923,7 +923,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -959,12 +959,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -982,7 +982,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1021,7 +1021,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1185,9 +1185,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1205,7 +1205,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1214,7 +1214,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1222,7 +1222,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1257,7 +1257,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -1277,14 +1277,14 @@ int main() { // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -1317,12 +1317,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1333,7 +1333,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1415,17 +1415,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP34]] // @@ -1466,7 +1466,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1539,9 +1539,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1560,7 +1560,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1569,7 +1569,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1578,7 +1578,7 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -1615,7 +1615,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1631,14 +1631,14 @@ int main() { // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -1661,12 +1661,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1720,7 +1720,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1756,12 +1756,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -1779,7 +1779,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1818,7 +1818,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: diff --git a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp index 85380d9418970..4c71955394187 100644 --- a/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp @@ -146,7 +146,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 @@ -172,7 +172,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = load double, ptr [[G_ADDR]], align 8 // CHECK1-NEXT: store double [[TMP0]], ptr [[G_CASTED]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP3:%.*]] = load volatile double, ptr [[TMP2]], align 8 // CHECK1-NEXT: store double [[TMP3]], ptr [[G1_CASTED]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8 @@ -220,7 +220,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 @@ -250,14 +250,14 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G2]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP9]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR5]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G2]], ptr [[TMP10]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR5]], ptr [[TMP13]], align 8 @@ -306,7 +306,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 @@ -326,10 +326,10 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[SVAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -369,14 +369,14 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 @@ -406,14 +406,14 @@ int main() { // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP11]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR5]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP12]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR5]], ptr [[TMP15]], align 4 @@ -459,7 +459,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -479,12 +479,12 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 @@ -555,17 +555,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // @@ -609,14 +609,14 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 @@ -643,8 +643,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -655,15 +655,15 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -673,7 +673,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -710,10 +710,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP14]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -736,7 +736,7 @@ int main() { // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP21]], ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP22]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -755,14 +755,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP24]], ptr [[SVAR_ADDR]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -770,12 +770,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -786,7 +786,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -802,12 +802,12 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -868,17 +868,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP34]] // @@ -909,7 +909,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -953,14 +953,14 @@ int main() { // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) // CHECK9-NEXT: ret void // @@ -983,8 +983,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -993,15 +993,15 @@ int main() { // CHECK9-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1011,7 +1011,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1048,10 +1048,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP14]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1074,7 +1074,7 @@ int main() { // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP21]], ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP22]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1091,14 +1091,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP23]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1106,12 +1106,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1141,7 +1141,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1158,7 +1158,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1178,12 +1178,12 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -1254,17 +1254,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // @@ -1308,14 +1308,14 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -1342,8 +1342,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1354,15 +1354,15 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1372,7 +1372,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1408,9 +1408,9 @@ int main() { // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP13]] // CHECK11-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP14]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1433,7 +1433,7 @@ int main() { // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP21]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP22]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1452,14 +1452,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP24]], ptr [[SVAR_ADDR]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -1467,12 +1467,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1483,7 +1483,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1499,12 +1499,12 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1565,17 +1565,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP34]] // @@ -1606,7 +1606,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1650,14 +1650,14 @@ int main() { // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) // CHECK11-NEXT: ret void // @@ -1680,8 +1680,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1690,15 +1690,15 @@ int main() { // CHECK11-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1708,7 +1708,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1744,9 +1744,9 @@ int main() { // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP13]] // CHECK11-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP14]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1769,7 +1769,7 @@ int main() { // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP21]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP22]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1786,14 +1786,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP23]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -1801,12 +1801,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1836,7 +1836,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp index 678770520f677..1382aef84da68 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -219,12 +219,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -242,7 +242,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -281,7 +281,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -445,9 +445,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -467,7 +467,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -476,7 +476,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -484,7 +484,7 @@ int main() { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -534,14 +534,14 @@ int main() { // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -574,12 +574,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -602,9 +602,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -630,7 +630,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -639,7 +639,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -647,7 +647,7 @@ int main() { // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -684,7 +684,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -704,14 +704,14 @@ int main() { // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -725,7 +725,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -807,17 +807,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP34]] // @@ -858,7 +858,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -931,9 +931,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -953,7 +953,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -962,7 +962,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -971,7 +971,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -1020,14 +1020,14 @@ int main() { // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done10: @@ -1068,9 +1068,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1097,7 +1097,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1106,7 +1106,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -1115,7 +1115,7 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -1154,7 +1154,7 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1170,14 +1170,14 @@ int main() { // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done14: @@ -1185,12 +1185,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -1244,7 +1244,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1280,12 +1280,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1303,7 +1303,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1342,7 +1342,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1506,9 +1506,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1528,7 +1528,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1537,7 +1537,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1545,7 +1545,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1593,14 +1593,14 @@ int main() { // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done8: @@ -1633,12 +1633,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1661,9 +1661,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1687,7 +1687,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1696,7 +1696,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -1704,7 +1704,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1739,7 +1739,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -1759,14 +1759,14 @@ int main() { // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -1780,7 +1780,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1862,17 +1862,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP34]] // @@ -1913,7 +1913,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1986,9 +1986,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2008,7 +2008,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2017,7 +2017,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -2026,7 +2026,7 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -2073,14 +2073,14 @@ int main() { // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done10: @@ -2121,9 +2121,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2148,7 +2148,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2157,7 +2157,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -2166,7 +2166,7 @@ int main() { // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -2203,7 +2203,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2219,14 +2219,14 @@ int main() { // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -2234,12 +2234,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -2293,7 +2293,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2329,12 +2329,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -2352,7 +2352,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2391,7 +2391,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -2689,9 +2689,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -2711,7 +2711,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2720,7 +2720,7 @@ int main() { // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -2728,7 +2728,7 @@ int main() { // CHECK13: omp.arraycpy.done3: // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2778,14 +2778,14 @@ int main() { // CHECK13-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -2818,12 +2818,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2846,9 +2846,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2874,7 +2874,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2883,7 +2883,7 @@ int main() { // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -2891,7 +2891,7 @@ int main() { // CHECK13: omp.arraycpy.done4: // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -2928,7 +2928,7 @@ int main() { // CHECK13-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -2948,14 +2948,14 @@ int main() { // CHECK13-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: @@ -2963,12 +2963,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -3016,9 +3016,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3038,7 +3038,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3047,7 +3047,7 @@ int main() { // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -3056,7 +3056,7 @@ int main() { // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META8]], !align [[META9]] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] // CHECK13-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -3105,14 +3105,14 @@ int main() { // CHECK13-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done10: @@ -3153,9 +3153,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3182,7 +3182,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3191,7 +3191,7 @@ int main() { // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -3200,7 +3200,7 @@ int main() { // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META8]], !align [[META9]] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP7]]) #[[ATTR3]] // CHECK13-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -3239,7 +3239,7 @@ int main() { // CHECK13-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META8]], !align [[META9]] // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3255,14 +3255,14 @@ int main() { // CHECK13-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: @@ -3270,12 +3270,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -3293,7 +3293,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3302,7 +3302,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3333,7 +3333,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3409,9 +3409,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -3431,7 +3431,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3440,7 +3440,7 @@ int main() { // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -3448,7 +3448,7 @@ int main() { // CHECK15: omp.arraycpy.done3: // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3496,14 +3496,14 @@ int main() { // CHECK15-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done8: @@ -3536,12 +3536,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -3564,9 +3564,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -3590,7 +3590,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3599,7 +3599,7 @@ int main() { // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -3607,7 +3607,7 @@ int main() { // CHECK15: omp.arraycpy.done3: // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3642,7 +3642,7 @@ int main() { // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] // CHECK15-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -3662,14 +3662,14 @@ int main() { // CHECK15-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done11: @@ -3677,12 +3677,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -3730,9 +3730,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3752,7 +3752,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3761,7 +3761,7 @@ int main() { // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -3770,7 +3770,7 @@ int main() { // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META9]], !align [[META10]] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -3817,14 +3817,14 @@ int main() { // CHECK15-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -3865,9 +3865,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3892,7 +3892,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3901,7 +3901,7 @@ int main() { // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -3910,7 +3910,7 @@ int main() { // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META9]], !align [[META10]] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -3947,7 +3947,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META9]], !align [[META10]] // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3963,14 +3963,14 @@ int main() { // CHECK15-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: @@ -3978,12 +3978,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -4001,7 +4001,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -4010,7 +4010,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -4041,7 +4041,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp index d25d3d30aae28..560eea6231a94 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -181,7 +181,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 @@ -204,7 +204,7 @@ int main() { // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, ptr [[TMP0]], align 8 // CHECK1-NEXT: store double [[TMP1]], ptr [[G1_CASTED]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[G1_CASTED]], align 8 @@ -258,7 +258,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 @@ -287,7 +287,7 @@ int main() { // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: [[TMP13:%.*]] = load volatile double, ptr [[TMP12]], align 8 // CHECK1-NEXT: store double [[TMP13]], ptr [[G1_CASTED]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[G1_CASTED]], align 8 @@ -374,7 +374,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 @@ -403,14 +403,14 @@ int main() { // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP11]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR6]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G3]], ptr [[TMP12]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP15]], align 8 @@ -459,7 +459,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 @@ -479,10 +479,10 @@ int main() { // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[SVAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -523,14 +523,14 @@ int main() { // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 @@ -557,7 +557,7 @@ int main() { // CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[SVAR5]], align 4 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[SVAR_CASTED]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -627,8 +627,8 @@ int main() { // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -638,7 +638,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -667,14 +667,14 @@ int main() { // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP13]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR5]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP14]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR5]], ptr [[TMP17]], align 4 @@ -720,7 +720,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -740,12 +740,12 @@ int main() { // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 @@ -816,17 +816,17 @@ int main() { // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP39]] // @@ -870,14 +870,14 @@ int main() { // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 @@ -904,8 +904,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -918,15 +918,15 @@ int main() { // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -936,7 +936,7 @@ int main() { // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -971,7 +971,7 @@ int main() { // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK5-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[SVAR7]], align 4 // CHECK5-NEXT: store i32 [[TMP18]], ptr [[SVAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 @@ -996,7 +996,7 @@ int main() { // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK5-NEXT: store i32 [[TMP26]], ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP27]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1015,14 +1015,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP29]], ptr [[SVAR_ADDR]], align 4 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done12: @@ -1050,8 +1050,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1064,9 +1064,9 @@ int main() { // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1078,7 +1078,7 @@ int main() { // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1088,7 +1088,7 @@ int main() { // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK5-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1125,10 +1125,10 @@ int main() { // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1151,7 +1151,7 @@ int main() { // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP24]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1170,14 +1170,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done16: @@ -1185,12 +1185,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -1201,7 +1201,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1217,12 +1217,12 @@ int main() { // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1283,17 +1283,17 @@ int main() { // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP34]] // @@ -1324,7 +1324,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1368,14 +1368,14 @@ int main() { // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) // CHECK5-NEXT: ret void // @@ -1398,8 +1398,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1409,15 +1409,15 @@ int main() { // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1427,7 +1427,7 @@ int main() { // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1462,7 +1462,7 @@ int main() { // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK5-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC3]], i64 [[TMP16]], ptr [[S_ARR4]], ptr [[TMP17]]) // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: @@ -1484,7 +1484,7 @@ int main() { // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK5-NEXT: store i32 [[TMP24]], ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP25]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1501,14 +1501,14 @@ int main() { // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP26]], i64 4, i1 false) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done11: @@ -1535,8 +1535,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1547,9 +1547,9 @@ int main() { // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1561,7 +1561,7 @@ int main() { // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1571,7 +1571,7 @@ int main() { // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK5: arrayctor.cont: -// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK5-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1608,10 +1608,10 @@ int main() { // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1634,7 +1634,7 @@ int main() { // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP24]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1651,14 +1651,14 @@ int main() { // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i64 4, i1 false) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done15: @@ -1666,12 +1666,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -1701,7 +1701,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1718,7 +1718,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1738,12 +1738,12 @@ int main() { // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -1814,17 +1814,17 @@ int main() { // CHECK7: omp_offload.cont: // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK7-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP39]] // @@ -1868,14 +1868,14 @@ int main() { // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -1902,8 +1902,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1916,15 +1916,15 @@ int main() { // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -1934,7 +1934,7 @@ int main() { // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1967,7 +1967,7 @@ int main() { // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[SVAR7]], align 4 // CHECK7-NEXT: store i32 [[TMP16]], ptr [[SVAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 @@ -1992,7 +1992,7 @@ int main() { // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP24]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP25]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2011,14 +2011,14 @@ int main() { // CHECK7-NEXT: store i32 [[TMP27]], ptr [[SVAR_ADDR]], align 4 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done12: @@ -2046,8 +2046,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2060,9 +2060,9 @@ int main() { // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2072,7 +2072,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2082,7 +2082,7 @@ int main() { // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2118,9 +2118,9 @@ int main() { // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2143,7 +2143,7 @@ int main() { // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2162,14 +2162,14 @@ int main() { // CHECK7-NEXT: store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done14: @@ -2177,12 +2177,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -2193,7 +2193,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2209,12 +2209,12 @@ int main() { // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -2275,17 +2275,17 @@ int main() { // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP34]] // @@ -2316,7 +2316,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2360,14 +2360,14 @@ int main() { // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]]) // CHECK7-NEXT: ret void // @@ -2390,8 +2390,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2401,15 +2401,15 @@ int main() { // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2419,7 +2419,7 @@ int main() { // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2452,7 +2452,7 @@ int main() { // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC3]], i32 [[TMP14]], ptr [[S_ARR4]], ptr [[TMP15]]) // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK7: omp.inner.for.inc: @@ -2474,7 +2474,7 @@ int main() { // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP22]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP23]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2491,14 +2491,14 @@ int main() { // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP24]], i32 4, i1 false) // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: @@ -2525,8 +2525,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2537,9 +2537,9 @@ int main() { // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2549,7 +2549,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2559,7 +2559,7 @@ int main() { // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK7: arrayctor.cont: -// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2595,9 +2595,9 @@ int main() { // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2620,7 +2620,7 @@ int main() { // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP24]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2637,14 +2637,14 @@ int main() { // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i32 4, i1 false) // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done13: @@ -2652,12 +2652,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -2687,7 +2687,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp index c0260af74c74b..3f855824ab4c9 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp @@ -199,12 +199,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -222,7 +222,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -261,7 +261,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -357,8 +357,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -367,7 +367,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -421,14 +421,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -450,8 +450,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -468,7 +468,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -515,7 +515,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -535,14 +535,14 @@ int main() { // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -556,7 +556,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -603,17 +603,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -662,8 +662,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -673,7 +673,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -728,14 +728,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -758,8 +758,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -777,7 +777,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -823,10 +823,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -842,14 +842,14 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -857,12 +857,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -895,7 +895,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -931,12 +931,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -954,7 +954,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -993,7 +993,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1089,8 +1089,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1099,7 +1099,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1151,14 +1151,14 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done3: @@ -1180,8 +1180,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1196,7 +1196,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1241,7 +1241,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -1261,14 +1261,14 @@ int main() { // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1282,7 +1282,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1329,17 +1329,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1388,8 +1388,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1399,7 +1399,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1452,14 +1452,14 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done5: @@ -1482,8 +1482,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1499,7 +1499,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1544,9 +1544,9 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1562,14 +1562,14 @@ int main() { // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1577,12 +1577,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1615,7 +1615,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1651,12 +1651,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1674,7 +1674,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1713,7 +1713,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1893,13 +1893,13 @@ int main() { // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK5-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK5-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 // CHECK5-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK5-NEXT: store ptr [[G]], ptr [[TMP11]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8 @@ -1950,8 +1950,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1960,7 +1960,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2014,14 +2014,14 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done3: @@ -2053,8 +2053,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2071,7 +2071,7 @@ int main() { // CHECK13-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2118,7 +2118,7 @@ int main() { // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -2138,14 +2138,14 @@ int main() { // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -2153,12 +2153,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK13-NEXT: ret void // // @@ -2185,8 +2185,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2196,7 +2196,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2251,14 +2251,14 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done5: @@ -2291,8 +2291,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2310,7 +2310,7 @@ int main() { // CHECK13-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2356,10 +2356,10 @@ int main() { // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2375,14 +2375,14 @@ int main() { // CHECK13-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done9: @@ -2390,12 +2390,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK13-NEXT: ret void // // @@ -2413,7 +2413,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2434,7 +2434,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2464,8 +2464,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2474,7 +2474,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2526,14 +2526,14 @@ int main() { // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done3: @@ -2565,8 +2565,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2581,7 +2581,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2626,7 +2626,7 @@ int main() { // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -2646,14 +2646,14 @@ int main() { // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: @@ -2661,12 +2661,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK15-NEXT: ret void // // @@ -2693,8 +2693,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2704,7 +2704,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2757,14 +2757,14 @@ int main() { // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done5: @@ -2797,8 +2797,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2814,7 +2814,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2859,9 +2859,9 @@ int main() { // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META11:![0-9]+]], !align [[META12:![0-9]+]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2877,14 +2877,14 @@ int main() { // CHECK15-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done7: @@ -2892,12 +2892,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK15-NEXT: ret void // // @@ -2915,7 +2915,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2936,7 +2936,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3084,13 +3084,13 @@ int main() { // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK17-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 // CHECK17-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK17-NEXT: store ptr [[G]], ptr [[TMP11]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META6]], !align [[META7]] // CHECK17-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp index cac4dd3eb2a79..5c4b2fc1f9ed3 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -217,12 +217,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -240,7 +240,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -279,7 +279,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -443,9 +443,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -465,7 +465,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -474,7 +474,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -482,7 +482,7 @@ int main() { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -539,14 +539,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -579,12 +579,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -607,9 +607,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -635,7 +635,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -644,7 +644,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -652,7 +652,7 @@ int main() { // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -689,7 +689,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]] @@ -716,14 +716,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -737,7 +737,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -819,17 +819,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP34]] // @@ -870,7 +870,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -943,9 +943,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -965,7 +965,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -974,7 +974,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -983,7 +983,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -1039,14 +1039,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done10: @@ -1087,9 +1087,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1116,7 +1116,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1125,7 +1125,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -1134,7 +1134,7 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -1173,7 +1173,7 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP21]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1196,14 +1196,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done14: @@ -1211,12 +1211,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -1270,7 +1270,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1306,12 +1306,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1329,7 +1329,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1368,7 +1368,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1532,9 +1532,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1554,7 +1554,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1563,7 +1563,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1571,7 +1571,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1626,14 +1626,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done8: @@ -1666,12 +1666,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1694,9 +1694,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1720,7 +1720,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1729,7 +1729,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -1737,7 +1737,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1772,7 +1772,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]] @@ -1799,14 +1799,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -1820,7 +1820,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1902,17 +1902,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP34]] // @@ -1953,7 +1953,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2026,9 +2026,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2048,7 +2048,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2057,7 +2057,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -2066,7 +2066,7 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -2120,14 +2120,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done10: @@ -2168,9 +2168,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2195,7 +2195,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2204,7 +2204,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -2213,7 +2213,7 @@ int main() { // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -2250,7 +2250,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP22]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP22]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2273,14 +2273,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -2288,12 +2288,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -2347,7 +2347,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2383,12 +2383,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -2406,7 +2406,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2445,7 +2445,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -2729,12 +2729,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2769,7 +2769,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -2816,7 +2816,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] +// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr @s_arr, i64 0, i64 [[IDXPROM1]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] @@ -2843,7 +2843,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -2886,7 +2886,7 @@ int main() { // CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK7-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2899,17 +2899,17 @@ int main() { // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP14]] // @@ -2928,7 +2928,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2977,12 +2977,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -3015,7 +3015,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3051,12 +3051,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -3091,7 +3091,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -3136,7 +3136,7 @@ int main() { // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr @s_arr, i32 0, i32 [[TMP6]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] @@ -3163,7 +3163,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -3204,7 +3204,7 @@ int main() { // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3217,17 +3217,17 @@ int main() { // CHECK9: omp.inner.for.end: // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done4: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP14]] // @@ -3246,7 +3246,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3295,12 +3295,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -3333,7 +3333,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3369,12 +3369,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // @@ -3409,7 +3409,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -3448,7 +3448,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3529,9 +3529,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -3551,7 +3551,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3560,7 +3560,7 @@ int main() { // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -3568,7 +3568,7 @@ int main() { // CHECK13: omp.arraycpy.done3: // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3625,14 +3625,14 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -3665,12 +3665,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -3693,9 +3693,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3721,7 +3721,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3730,7 +3730,7 @@ int main() { // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -3738,7 +3738,7 @@ int main() { // CHECK13: omp.arraycpy.done4: // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK13-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -3775,7 +3775,7 @@ int main() { // CHECK13-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]] @@ -3802,14 +3802,14 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: @@ -3817,12 +3817,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -3870,9 +3870,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -3892,7 +3892,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3901,7 +3901,7 @@ int main() { // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -3910,7 +3910,7 @@ int main() { // CHECK13-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META8]], !align [[META9]] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] // CHECK13-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK13-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -3966,14 +3966,14 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK13-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done10: @@ -4014,9 +4014,9 @@ int main() { // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK13-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK13-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -4043,7 +4043,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -4052,7 +4052,7 @@ int main() { // CHECK13-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK13-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK13-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -4061,7 +4061,7 @@ int main() { // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META8]], !align [[META9]] // CHECK13-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) // CHECK13-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) -// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP7]]) #[[ATTR3]] // CHECK13-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 // CHECK13-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -4100,7 +4100,7 @@ int main() { // CHECK13-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP22]] // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP22]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -4123,14 +4123,14 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: @@ -4138,12 +4138,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -4161,7 +4161,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4170,7 +4170,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4201,7 +4201,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4277,9 +4277,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -4299,7 +4299,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -4308,7 +4308,7 @@ int main() { // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3:[0-9]+]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -4316,7 +4316,7 @@ int main() { // CHECK15: omp.arraycpy.done3: // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4371,14 +4371,14 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done8: @@ -4411,12 +4411,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -4439,9 +4439,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -4465,7 +4465,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -4474,7 +4474,7 @@ int main() { // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -4482,7 +4482,7 @@ int main() { // CHECK15: omp.arraycpy.done3: // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK15-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -4517,7 +4517,7 @@ int main() { // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] // CHECK15-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP15]] @@ -4544,14 +4544,14 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done11: @@ -4559,12 +4559,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -4612,9 +4612,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -4634,7 +4634,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -4643,7 +4643,7 @@ int main() { // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -4652,7 +4652,7 @@ int main() { // CHECK15-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META9]], !align [[META10]] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -4706,14 +4706,14 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done10: @@ -4754,9 +4754,9 @@ int main() { // CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK15-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -4781,7 +4781,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -4790,7 +4790,7 @@ int main() { // CHECK15-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR3]] // CHECK15-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK15-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -4799,7 +4799,7 @@ int main() { // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META9]], !align [[META10]] // CHECK15-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK15-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) -// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR3]] // CHECK15-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -4836,7 +4836,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK15-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META9]], !align [[META10]], !llvm.access.group [[ACC_GRP23]] // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP23]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -4859,14 +4859,14 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK15-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: @@ -4874,12 +4874,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -4897,7 +4897,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -4906,7 +4906,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -4937,7 +4937,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp index bd43b4798f6f0..98e18ff847477 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -748,7 +748,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -844,17 +844,17 @@ int main() { // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK5-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP39]] // @@ -932,8 +932,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -954,7 +954,7 @@ int main() { // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1031,7 +1031,7 @@ int main() { // CHECK5-NEXT: [[TMP28:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK5-NEXT: store i32 [[TMP28]], ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP29]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1050,14 +1050,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP31]], ptr [[SVAR_ADDR]], align 4 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP32]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done12: @@ -1085,8 +1085,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1113,7 +1113,7 @@ int main() { // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1163,7 +1163,7 @@ int main() { // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1193,7 +1193,7 @@ int main() { // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK5-NEXT: store i32 [[TMP25]], ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP26]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1212,14 +1212,14 @@ int main() { // CHECK5-NEXT: store i32 [[TMP28]], ptr [[SVAR_ADDR]], align 4 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done16: @@ -1227,12 +1227,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -1243,7 +1243,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1325,17 +1325,17 @@ int main() { // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done2: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP34]] // @@ -1366,7 +1366,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1440,8 +1440,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1459,7 +1459,7 @@ int main() { // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1533,7 +1533,7 @@ int main() { // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK5-NEXT: store i32 [[TMP26]], ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP27]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1550,14 +1550,14 @@ int main() { // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP28]], i64 4, i1 false) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done11: @@ -1584,8 +1584,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1610,7 +1610,7 @@ int main() { // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1660,7 +1660,7 @@ int main() { // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1690,7 +1690,7 @@ int main() { // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK5-NEXT: store i32 [[TMP25]], ptr [[T_VAR_ADDR]], align 4 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP26]] // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1707,14 +1707,14 @@ int main() { // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i64 4, i1 false) // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK5: .omp.lastprivate.done: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done15: @@ -1722,12 +1722,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -1757,7 +1757,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1774,7 +1774,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1870,17 +1870,17 @@ int main() { // CHECK7: omp_offload.cont: // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK7-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP39]] // @@ -1958,8 +1958,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1980,7 +1980,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2055,7 +2055,7 @@ int main() { // CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP26]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP27]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2074,14 +2074,14 @@ int main() { // CHECK7-NEXT: store i32 [[TMP29]], ptr [[SVAR_ADDR]], align 4 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done12: @@ -2109,8 +2109,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2135,7 +2135,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2183,7 +2183,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP14]] // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2213,7 +2213,7 @@ int main() { // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP25]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP26]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2232,14 +2232,14 @@ int main() { // CHECK7-NEXT: store i32 [[TMP28]], ptr [[SVAR_ADDR]], align 4 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done14: @@ -2247,12 +2247,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -2263,7 +2263,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2345,17 +2345,17 @@ int main() { // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK7: omp_offload.cont: // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done2: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK7-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP34]] // @@ -2386,7 +2386,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2460,8 +2460,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2479,7 +2479,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2551,7 +2551,7 @@ int main() { // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP24]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP25]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2568,14 +2568,14 @@ int main() { // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP26]], i32 4, i1 false) // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: @@ -2602,8 +2602,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2626,7 +2626,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2674,7 +2674,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP22]] // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP22]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2704,7 +2704,7 @@ int main() { // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: store i32 [[TMP25]], ptr [[T_VAR_ADDR]], align 4 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP26]] // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2721,14 +2721,14 @@ int main() { // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP27]], i32 4, i1 false) // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK7: .omp.lastprivate.done: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done13: @@ -2736,12 +2736,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK7-NEXT: ret void // // @@ -2771,7 +2771,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2824,7 +2824,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -2834,7 +2834,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2857,7 +2857,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2891,7 +2891,7 @@ int main() { // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2906,7 +2906,7 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP15]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2923,30 +2923,30 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] // CHECK13: arraydestroy.body16: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13: arraydestroy.done20: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP20]] // @@ -2975,12 +2975,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2991,7 +2991,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -3001,7 +3001,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -3020,7 +3020,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -3054,7 +3054,7 @@ int main() { // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3069,7 +3069,7 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP15]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3084,29 +3084,29 @@ int main() { // CHECK13: omp.arraycpy.done11: // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY15:%.*]] // CHECK13: arraydestroy.body15: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK13: arraydestroy.done19: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP19]] // @@ -3123,7 +3123,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3169,12 +3169,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -3204,7 +3204,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3221,7 +3221,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -3231,7 +3231,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -3254,7 +3254,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3286,7 +3286,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3301,7 +3301,7 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP15]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3318,30 +3318,30 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY15:%.*]] // CHECK15: arraydestroy.body15: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK15: arraydestroy.done19: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP20]] // @@ -3370,12 +3370,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -3386,7 +3386,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -3396,7 +3396,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -3415,7 +3415,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3447,7 +3447,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3462,7 +3462,7 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP15]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3477,29 +3477,29 @@ int main() { // CHECK15: omp.arraycpy.done10: // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY14:%.*]] // CHECK15: arraydestroy.body14: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST15]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK15: arraydestroy.done18: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP19]] // @@ -3516,7 +3516,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3562,12 +3562,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -3597,7 +3597,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp index 1b54926e48976..611011a59f66a 100644 --- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp @@ -199,12 +199,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -222,7 +222,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -261,7 +261,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -357,8 +357,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -367,7 +367,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -428,14 +428,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -457,8 +457,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -475,7 +475,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -522,7 +522,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP11]] @@ -549,14 +549,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -570,7 +570,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -617,17 +617,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -676,8 +676,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -687,7 +687,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -749,14 +749,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -779,8 +779,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -798,7 +798,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -847,7 +847,7 @@ int main() { // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]], !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -870,14 +870,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -885,12 +885,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -923,7 +923,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -959,12 +959,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -982,7 +982,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1021,7 +1021,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1117,8 +1117,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1127,7 +1127,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1186,14 +1186,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done3: @@ -1215,8 +1215,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1231,7 +1231,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1276,7 +1276,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -1303,14 +1303,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1324,7 +1324,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1371,17 +1371,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1430,8 +1430,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1441,7 +1441,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1501,14 +1501,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done5: @@ -1531,8 +1531,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1548,7 +1548,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1595,7 +1595,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META21:![0-9]+]], !align [[META22:![0-9]+]], !llvm.access.group [[ACC_GRP20]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP20]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1618,14 +1618,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1633,12 +1633,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1671,7 +1671,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1707,12 +1707,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1730,7 +1730,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1769,7 +1769,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -2017,12 +2017,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2057,7 +2057,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -2082,8 +2082,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -2091,7 +2091,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2122,7 +2122,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] +// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] @@ -2138,14 +2138,14 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK7-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done6: @@ -2160,7 +2160,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2169,7 +2169,7 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2185,7 +2185,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2218,7 +2218,7 @@ int main() { // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]], !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2230,29 +2230,29 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done11: // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK7: arraydestroy.body13: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK7: arraydestroy.done17: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP11]] // @@ -2271,7 +2271,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2320,12 +2320,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2358,7 +2358,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2394,12 +2394,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -2434,7 +2434,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2459,8 +2459,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -2468,7 +2468,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -2497,7 +2497,7 @@ int main() { // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP6]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] @@ -2513,14 +2513,14 @@ int main() { // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK9-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done5: @@ -2535,7 +2535,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2544,7 +2544,7 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2560,7 +2560,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -2591,7 +2591,7 @@ int main() { // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]], !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2603,29 +2603,29 @@ int main() { // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done10: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] // CHECK9: arraydestroy.body12: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK9: arraydestroy.done16: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP11]] // @@ -2644,7 +2644,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2693,12 +2693,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -2731,7 +2731,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2767,12 +2767,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // @@ -2807,7 +2807,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -2846,7 +2846,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2902,8 +2902,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -2912,7 +2912,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2973,14 +2973,14 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done3: @@ -3012,8 +3012,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3030,7 +3030,7 @@ int main() { // CHECK13-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -3077,7 +3077,7 @@ int main() { // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -3104,14 +3104,14 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -3119,12 +3119,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK13-NEXT: ret void // // @@ -3151,8 +3151,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3162,7 +3162,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -3224,14 +3224,14 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done5: @@ -3264,8 +3264,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -3283,7 +3283,7 @@ int main() { // CHECK13-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -3332,7 +3332,7 @@ int main() { // CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META21:![0-9]+]], !align [[META22:![0-9]+]], !llvm.access.group [[ACC_GRP20]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP20]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3355,14 +3355,14 @@ int main() { // CHECK13-NEXT: store i32 2, ptr [[I]], align 4 // CHECK13-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK13: .omp.final.done: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done9: @@ -3370,12 +3370,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK13-NEXT: ret void // // @@ -3393,7 +3393,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3414,7 +3414,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3444,8 +3444,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -3454,7 +3454,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3513,14 +3513,14 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done3: @@ -3552,8 +3552,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -3568,7 +3568,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3613,7 +3613,7 @@ int main() { // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP13]] @@ -3640,14 +3640,14 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: @@ -3655,12 +3655,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK15-NEXT: ret void // // @@ -3687,8 +3687,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -3698,7 +3698,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3758,14 +3758,14 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done5: @@ -3798,8 +3798,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -3815,7 +3815,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3862,7 +3862,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META22:![0-9]+]], !align [[META23:![0-9]+]], !llvm.access.group [[ACC_GRP21]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3885,14 +3885,14 @@ int main() { // CHECK15-NEXT: store i32 2, ptr [[I]], align 4 // CHECK15-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK15: .omp.final.done: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done7: @@ -3900,12 +3900,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK15-NEXT: ret void // // @@ -3923,7 +3923,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3944,7 +3944,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp index b80a2c269867a..5143dbb198c4b 100644 --- a/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_private_codegen.cpp @@ -138,12 +138,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -161,7 +161,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -200,7 +200,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -296,8 +296,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -306,7 +306,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -353,7 +353,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -373,14 +373,14 @@ int main() { // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -394,7 +394,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -441,17 +441,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -500,8 +500,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -511,7 +511,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -557,10 +557,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -576,14 +576,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -591,12 +591,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -629,7 +629,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -665,12 +665,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -688,7 +688,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -727,7 +727,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -823,8 +823,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -833,7 +833,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -878,7 +878,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -898,14 +898,14 @@ int main() { // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -919,7 +919,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -966,17 +966,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1025,8 +1025,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1036,7 +1036,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1081,9 +1081,9 @@ int main() { // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1099,14 +1099,14 @@ int main() { // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1114,12 +1114,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1152,7 +1152,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1188,12 +1188,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -1211,7 +1211,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1250,7 +1250,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -1353,13 +1353,13 @@ int main() { // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp index c3d0fd52d812d..7efa532103e5a 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp @@ -158,12 +158,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -181,7 +181,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -220,7 +220,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -384,9 +384,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -404,7 +404,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -413,7 +413,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -421,7 +421,7 @@ int main() { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -458,7 +458,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] @@ -485,14 +485,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -525,12 +525,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -541,7 +541,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -623,17 +623,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP34]] // @@ -674,7 +674,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -747,9 +747,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -768,7 +768,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -777,7 +777,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -786,7 +786,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -825,7 +825,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -848,14 +848,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -878,12 +878,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -937,7 +937,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -973,12 +973,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -996,7 +996,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1035,7 +1035,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1199,9 +1199,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1219,7 +1219,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1228,7 +1228,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1236,7 +1236,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1271,7 +1271,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] @@ -1298,14 +1298,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -1338,12 +1338,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1354,7 +1354,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1436,17 +1436,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP34]] // @@ -1487,7 +1487,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1560,9 +1560,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1581,7 +1581,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1590,7 +1590,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1599,7 +1599,7 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -1636,7 +1636,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1659,14 +1659,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -1689,12 +1689,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1748,7 +1748,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1784,12 +1784,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1824,7 +1824,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1871,7 +1871,7 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr @s_arr, i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] @@ -1898,7 +1898,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -1940,7 +1940,7 @@ int main() { // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP9]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1953,17 +1953,17 @@ int main() { // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done5: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP13]] // @@ -1982,7 +1982,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2031,12 +2031,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -2069,7 +2069,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2105,12 +2105,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2145,7 +2145,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -2190,7 +2190,7 @@ int main() { // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr @s_arr, i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] @@ -2217,7 +2217,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -2257,7 +2257,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[TMP9]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2270,17 +2270,17 @@ int main() { // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done4: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP13]] // @@ -2299,7 +2299,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2348,12 +2348,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2386,7 +2386,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2422,12 +2422,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -2445,7 +2445,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2484,7 +2484,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2670,12 +2670,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // @@ -2710,7 +2710,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -2749,7 +2749,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp index e8d271bc8edea..e9e9e2b74b3af 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp @@ -509,7 +509,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -605,17 +605,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP39]] // @@ -693,8 +693,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -713,7 +713,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -763,7 +763,7 @@ int main() { // CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -793,7 +793,7 @@ int main() { // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP24]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -812,14 +812,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -827,12 +827,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -843,7 +843,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -925,17 +925,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP34]] // @@ -966,7 +966,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1040,8 +1040,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1058,7 +1058,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1108,7 +1108,7 @@ int main() { // CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1138,7 +1138,7 @@ int main() { // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1155,14 +1155,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP25]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1170,12 +1170,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1205,7 +1205,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1222,7 +1222,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1318,17 +1318,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP39]] // @@ -1406,8 +1406,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1426,7 +1426,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1474,7 +1474,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1504,7 +1504,7 @@ int main() { // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1523,14 +1523,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -1538,12 +1538,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1554,7 +1554,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1636,17 +1636,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP34]] // @@ -1677,7 +1677,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1751,8 +1751,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1769,7 +1769,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1817,7 +1817,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1847,7 +1847,7 @@ int main() { // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP24]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1864,14 +1864,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP25]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -1879,12 +1879,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1914,7 +1914,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1931,7 +1931,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -1941,7 +1941,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -1963,7 +1963,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -1997,7 +1997,7 @@ int main() { // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2012,7 +2012,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK13-NEXT: store i32 [[TMP13]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP14]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2029,30 +2029,30 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP16]], ptr @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] // CHECK13: arraydestroy.body16: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13: arraydestroy.done20: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP19]] // @@ -2081,12 +2081,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2097,7 +2097,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -2107,7 +2107,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2125,7 +2125,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2159,7 +2159,7 @@ int main() { // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2174,7 +2174,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK13-NEXT: store i32 [[TMP13]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP14]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2189,29 +2189,29 @@ int main() { // CHECK13: omp.arraycpy.done11: // CHECK13-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 8 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[TMP15]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done13: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY15:%.*]] // CHECK13: arraydestroy.body15: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP17]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK13: arraydestroy.done19: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP18]] // @@ -2228,7 +2228,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2274,12 +2274,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2309,7 +2309,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2326,7 +2326,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -2336,7 +2336,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2358,7 +2358,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2390,7 +2390,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2405,7 +2405,7 @@ int main() { // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK15-NEXT: store i32 [[TMP13]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP14]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2422,30 +2422,30 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP4]], ptr align 4 [[TMP15]], i32 4, i1 false) // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP16]], ptr @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY15:%.*]] // CHECK15: arraydestroy.body15: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK15: arraydestroy.done19: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP19]] // @@ -2474,12 +2474,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2490,7 +2490,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 @@ -2500,7 +2500,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2518,7 +2518,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2550,7 +2550,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2565,7 +2565,7 @@ int main() { // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK15-NEXT: store i32 [[TMP13]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP14]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2580,29 +2580,29 @@ int main() { // CHECK15: omp.arraycpy.done10: // CHECK15-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP4]], ptr align 4 [[TMP15]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_ARRAYCPY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done12: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY14:%.*]] // CHECK15: arraydestroy.body14: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST15:%.*]] = phi ptr [ [[TMP17]], [[ARRAYDESTROY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT16:%.*]], [[ARRAYDESTROY_BODY14]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT16]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST15]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT16]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE17:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT16]], [[ARRAY_BEGIN13]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE17]], label [[ARRAYDESTROY_DONE18:%.*]], label [[ARRAYDESTROY_BODY14]] // CHECK15: arraydestroy.done18: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP18]] // @@ -2619,7 +2619,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2665,12 +2665,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2700,7 +2700,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp b/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp index ab2b3eee259f1..42bc30120dd55 100644 --- a/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp @@ -138,12 +138,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -161,7 +161,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -200,7 +200,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -296,8 +296,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -306,7 +306,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -353,7 +353,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP7]] @@ -380,14 +380,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -401,7 +401,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -448,17 +448,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -507,8 +507,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -518,7 +518,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -567,7 +567,7 @@ int main() { // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META14:![0-9]+]], !align [[META15:![0-9]+]], !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -590,14 +590,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -605,12 +605,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -643,7 +643,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -679,12 +679,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -702,7 +702,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -741,7 +741,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -837,8 +837,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -847,7 +847,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -892,7 +892,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP8]] @@ -919,14 +919,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -940,7 +940,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -987,17 +987,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1046,8 +1046,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1057,7 +1057,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1104,7 +1104,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META15:![0-9]+]], !align [[META16:![0-9]+]], !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1127,14 +1127,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1142,12 +1142,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1180,7 +1180,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1216,12 +1216,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1256,7 +1256,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1281,8 +1281,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1290,7 +1290,7 @@ int main() { // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1321,7 +1321,7 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] @@ -1337,14 +1337,14 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: @@ -1359,7 +1359,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1368,7 +1368,7 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1384,7 +1384,7 @@ int main() { // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1417,7 +1417,7 @@ int main() { // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]], !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1429,29 +1429,29 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done11: // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK5: arraydestroy.body13: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5: arraydestroy.done17: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP11]] // @@ -1470,7 +1470,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1519,12 +1519,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1557,7 +1557,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1593,12 +1593,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -1633,7 +1633,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -1658,8 +1658,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1667,7 +1667,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -1696,7 +1696,7 @@ int main() { // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] @@ -1712,14 +1712,14 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: @@ -1734,7 +1734,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1743,7 +1743,7 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1759,7 +1759,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -1790,7 +1790,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]], !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1802,29 +1802,29 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done10: // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] // CHECK7: arraydestroy.body12: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK7: arraydestroy.done16: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP11]] // @@ -1843,7 +1843,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1892,12 +1892,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -1930,7 +1930,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1966,12 +1966,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -1989,7 +1989,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2028,7 +2028,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2192,12 +2192,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // @@ -2232,7 +2232,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -2271,7 +2271,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp index 6b4e4d42ab9c9..bcead6ed92c62 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp @@ -199,12 +199,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -222,7 +222,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -261,7 +261,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -357,8 +357,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -367,7 +367,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -414,7 +414,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -434,14 +434,14 @@ int main() { // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -455,7 +455,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -502,17 +502,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -561,8 +561,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -572,7 +572,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -618,10 +618,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -637,14 +637,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -652,12 +652,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -690,7 +690,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -726,12 +726,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -749,7 +749,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -788,7 +788,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -884,8 +884,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -894,7 +894,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -939,7 +939,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -959,14 +959,14 @@ int main() { // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -980,7 +980,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1027,17 +1027,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1086,8 +1086,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1097,7 +1097,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1142,9 +1142,9 @@ int main() { // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1160,14 +1160,14 @@ int main() { // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1175,12 +1175,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1213,7 +1213,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1249,12 +1249,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1272,7 +1272,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1311,7 +1311,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1414,13 +1414,13 @@ int main() { // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK5-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK5-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 // CHECK5-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK5-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK5-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK5-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 @@ -1471,8 +1471,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1481,7 +1481,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -1528,7 +1528,7 @@ int main() { // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -1548,14 +1548,14 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done7: @@ -1573,12 +1573,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK13-NEXT: ret void // // @@ -1605,8 +1605,8 @@ int main() { // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1616,7 +1616,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -1662,10 +1662,10 @@ int main() { // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1681,14 +1681,14 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done8: @@ -1706,12 +1706,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK13-NEXT: ret void // // @@ -1729,7 +1729,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1750,7 +1750,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1780,8 +1780,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1790,7 +1790,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -1835,7 +1835,7 @@ int main() { // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -1855,14 +1855,14 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done6: @@ -1880,12 +1880,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK15-NEXT: ret void // // @@ -1912,8 +1912,8 @@ int main() { // CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1923,7 +1923,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -1968,9 +1968,9 @@ int main() { // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META11:![0-9]+]], !align [[META12:![0-9]+]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -1986,14 +1986,14 @@ int main() { // CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done7: @@ -2011,12 +2011,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK15-NEXT: ret void // // @@ -2034,7 +2034,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2055,7 +2055,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2126,13 +2126,13 @@ int main() { // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK17-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 // CHECK17-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK17-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META6]], !align [[META7]] // CHECK17-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK17-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 diff --git a/clang/test/OpenMP/task_ast_print.cpp b/clang/test/OpenMP/task_ast_print.cpp index 4c59a7c7fafa1..5ed43d802b5a1 100644 --- a/clang/test/OpenMP/task_ast_print.cpp +++ b/clang/test/OpenMP/task_ast_print.cpp @@ -16,12 +16,6 @@ typedef void *omp_depend_t; typedef unsigned long omp_event_handle_t; -typedef void **omp_impex_t; -extern const omp_impex_t omp_not_impex; -extern const omp_impex_t omp_import; -extern const omp_impex_t omp_export; -extern const omp_impex_t omp_impex; - void foo() {} struct S1 { @@ -250,6 +244,9 @@ int main(int argc, char **argv) { #pragma omp task threadset(omp_team) foo(); +#pragma omp task transparent shared(x) +#pragma omp task transparent(omp_export) shared(x) +#pragma omp task transparent #pragma omp task transparent(omp_not_impex) #pragma omp task transparent(omp_import) #pragma omp task transparent(omp_export) @@ -273,9 +270,13 @@ int main(int argc, char **argv) { // CHECK60: #pragma omp task transparent(omp_import) // CHECK60: #pragma omp taskloop transparent(omp_impex) // CHECK60: #pragma omp task transparent(omp_import) + // CHECK60: #pragma omp taskloop transparent(omp_impex) // CHECK60: #pragma omp task threadset(omp_pool) // CHECK60: #pragma omp task threadset(omp_team) // CHECK60-NEXT: foo(); + // CHECK60: #pragma omp task transparent(omp_impex) shared(x) + // CHECK60: #pragma omp task transparent(omp_export) shared(x) + // CHECK60: #pragma omp task transparent(omp_impex) // CHECK60: #pragma omp task transparent(omp_not_impex) // CHECK60-NEXT: #pragma omp task transparent(omp_import) // CHECK60-NEXT: #pragma omp task transparent(omp_export) diff --git a/clang/test/OpenMP/task_codegen.cpp b/clang/test/OpenMP/task_codegen.cpp index faa9c3dfbcf61..f428265aec0e5 100644 --- a/clang/test/OpenMP/task_codegen.cpp +++ b/clang/test/OpenMP/task_codegen.cpp @@ -240,6 +240,13 @@ void test_threadset() void test_transparent() { + int x; +#pragma omp task transparent shared(x) + {} +#pragma omp task transparent(omp_not_impex) shared(x) + {} +#pragma omp task transparent + {} #pragma omp task transparent(omp_not_impex) {} #pragma omp task transparent(omp_import) @@ -259,27 +266,31 @@ void test_transparent() #endif // OMP60 #endif + + + + // CHECK1-LABEL: define {{[^@]+}}@main // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK1-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK1-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 -// CHECK1-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x %struct.kmp_depend_info], align 8 +// CHECK1-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK1-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 // CHECK1-NEXT: [[AGG_CAPTURED4:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK1-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK1-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-NEXT: [[DEP_COUNTER_ADDR11:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AGG_CAPTURED12:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK1-NEXT: [[DOTDEP_ARR_ADDR13:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK1-NEXT: [[DOTDEP_ARR_ADDR13:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-NEXT: [[DEP_COUNTER_ADDR19:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AGG_CAPTURED20:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK1-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK1-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[AGG_CAPTURED28:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 // CHECK1-NEXT: [[FLAG:%.*]] = alloca i8, align 1 @@ -289,8 +300,8 @@ void test_transparent() // CHECK1-NEXT: [[AGG_CAPTURED31:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -327,8 +338,8 @@ void test_transparent() // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP16]], i32 0, i32 0 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP18]], ptr align 8 [[AGG_CAPTURED1]], i64 8, i1 false) -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP19]], i64 0 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i64 0 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP20]], i32 0, i32 0 // CHECK1-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP21]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP20]], i32 0, i32 1 @@ -376,8 +387,8 @@ void test_transparent() // CHECK1-NEXT: [[TMP49:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP46]]) // CHECK1-NEXT: [[TMP50:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP50]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK1-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP52]], i64 0 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i32 0, i32 0 @@ -414,8 +425,8 @@ void test_transparent() // CHECK1-NEXT: [[TMP74:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP50]], i32 2, ptr [[TMP52]], i32 0, ptr null) // CHECK1-NEXT: [[TMP75:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP75]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK1-NEXT: [[TMP78:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP77]], i64 0 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP79]], i32 0, i32 0 @@ -452,7 +463,7 @@ void test_transparent() // CHECK1-NEXT: [[TMP99:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP75]], i32 2, ptr [[TMP77]], i32 0, ptr null) // CHECK1-NEXT: [[TMP100:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP100]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 0 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 0 // CHECK1-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP104]], align 8 @@ -460,7 +471,7 @@ void test_transparent() // CHECK1-NEXT: store i64 4, ptr [[TMP105]], align 8 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 2 // CHECK1-NEXT: store i8 3, ptr [[TMP106]], align 8 -// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK1-NEXT: [[TMP107:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 1 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP108]], i32 0, i32 0 @@ -515,9 +526,9 @@ void test_transparent() // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP141]], ptr align 8 [[AGG_CAPTURED30]], i64 8, i1 false) // CHECK1-NEXT: [[TMP142:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP138]]) // CHECK1-NEXT: [[TMP143:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..21) -// CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP143]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP143]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP145]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP143]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP143]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP145]], i32 0, i32 0 // CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[C]], align 128 // CHECK1-NEXT: store i32 [[TMP147]], ptr [[TMP146]], align 128 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP144]], i32 0, i32 2 @@ -527,13 +538,13 @@ void test_transparent() // CHECK1-NEXT: store i32 [[TMP150]], ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP151:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP151]]) -// CHECK1-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 // CHECK1-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN32]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP152]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE33:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done33: @@ -584,10 +595,10 @@ void test_transparent() // CHECK1-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] // CHECK1-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] // CHECK1-NEXT: store i32 10, ptr [[TMP12]], align 4 // CHECK1-NEXT: ret i32 0 // @@ -611,20 +622,20 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-NEXT: store i32 15, ptr @a, align 4, !noalias [[META22]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 // CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK1-NEXT: ret i32 0 // @@ -649,42 +660,42 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK1-NEXT: ] // CHECK1: .untied.done..i: -// CHECK1-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK1-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK1-NEXT: br label [[CLEANUP_I:%.*]] // CHECK1: .untied.jmp..i: -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32]] -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34]] +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] // CHECK1-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] // CHECK1: .untied.jmp.1.i: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34]] // CHECK1-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[TMP15]], ptr @.gomp_critical_user_.var) -// CHECK1-NEXT: store i32 1, ptr @a, align 4, !noalias [[META32]] +// CHECK1-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] // CHECK1-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[TMP15]], ptr @.gomp_critical_user_.var) -// CHECK1-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK1-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK1-NEXT: br label [[CLEANUP_I]] // CHECK1: cleanup.i: -// CHECK1-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK1-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] // CHECK1: .omp_outlined..3.exit: // CHECK1-NEXT: ret i32 0 @@ -710,39 +721,39 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK1-NEXT: ] // CHECK1: .untied.done..i: -// CHECK1-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK1-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK1-NEXT: br label [[CLEANUP_I:%.*]] // CHECK1: .untied.jmp..i: -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42]] -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44]] +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] // CHECK1-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] // CHECK1: .untied.jmp.1.i: -// CHECK1-NEXT: store i32 1, ptr @a, align 4, !noalias [[META42]] -// CHECK1-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK1-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK1-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK1-NEXT: br label [[CLEANUP_I]] // CHECK1: cleanup.i: -// CHECK1-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK1-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] // CHECK1: .omp_outlined..5.exit: // CHECK1-NEXT: ret i32 0 @@ -768,39 +779,39 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK1-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK1-NEXT: ] // CHECK1: .untied.done..i: -// CHECK1-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK1-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK1-NEXT: br label [[CLEANUP_I:%.*]] // CHECK1: .untied.jmp..i: -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK1-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52]] -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54]] +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] // CHECK1-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] // CHECK1: .untied.jmp.1.i: -// CHECK1-NEXT: store i32 1, ptr @a, align 4, !noalias [[META52]] -// CHECK1-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK1-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK1-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK1-NEXT: br label [[CLEANUP_I]] // CHECK1: cleanup.i: -// CHECK1-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK1-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] // CHECK1: .omp_outlined..7.exit: // CHECK1-NEXT: ret i32 0 @@ -825,18 +836,18 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-NEXT: store i32 2, ptr @a, align 4, !noalias [[META62]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] // CHECK1-NEXT: ret i32 0 // // @@ -859,18 +870,18 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META72:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-NEXT: store i32 2, ptr @a, align 4, !noalias [[META72]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] // CHECK1-NEXT: ret i32 0 // // @@ -893,18 +904,18 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META82:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-NEXT: store i32 3, ptr @a, align 4, !noalias [[META82]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-NEXT: store i32 3, ptr @a, align 4, !noalias [[META84]] // CHECK1-NEXT: ret i32 0 // // @@ -927,19 +938,19 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META92:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-NEXT: store i32 4, ptr @a, align 4, !noalias [[META92]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-NEXT: store i32 4, ptr @a, align 4, !noalias [[META94]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK1-NEXT: store i32 5, ptr [[TMP9]], align 128 // CHECK1-NEXT: ret i32 0 // @@ -979,33 +990,33 @@ void test_transparent() // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], ptr [[TMP3]], i32 0, i32 2 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META102:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] // CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META102]] +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META104]] // CHECK1-NEXT: store i32 4, ptr [[TMP12]], align 128 -// CHECK1-NEXT: store i32 4, ptr @a, align 4, !noalias [[META102]] +// CHECK1-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] // CHECK1-NEXT: ret i32 0 // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -1021,13 +1032,13 @@ void test_transparent() // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 2 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 3 +// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 3 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK1-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 // CHECK1-NEXT: ret void @@ -1053,30 +1064,30 @@ void test_transparent() // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP3]], i32 0, i32 2 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]]) +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK1-NEXT: switch i32 [[TMP17]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK1-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] @@ -1087,73 +1098,73 @@ void test_transparent() // CHECK1-NEXT: i32 5, label [[DOTUNTIED_JMP_10_I:%.*]] // CHECK1-NEXT: ] // CHECK1: .untied.done..i: -// CHECK1-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: br label [[CLEANUP_I:%.*]] // CHECK1: .untied.jmp..i: -// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: store i32 1, ptr [[TMP18]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP19]], ptr [[TMP20]]) // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK1: .untied.jmp.2.i: // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: [[DOTS2__VOID_ADDR_I:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP22]], i64 4, ptr inttoptr (i64 7 to ptr)) // CHECK1-NEXT: store ptr [[DOTS2__VOID_ADDR_I]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: store i32 2, ptr [[TMP23]], align 4 -// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP24]], ptr [[TMP25]]) // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK1: .untied.jmp.3.i: // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]]) // CHECK1-NEXT: store i32 0, ptr [[TMP15]], align 4 -// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: [[TMP28:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP27]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..19) // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.*]], ptr [[TMP28]], i32 0, i32 2 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP12]], align 128 // CHECK1-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 128 -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: [[TMP32:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP31]], ptr [[TMP28]]) -// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: store i32 3, ptr [[TMP33]], align 4 -// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: [[TMP36:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP34]], ptr [[TMP35]]) // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK1: .untied.jmp.5.i: -// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[TMP37]], i32 0) -// CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: store i32 4, ptr [[TMP39]], align 4 -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK1-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK1-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP40]], ptr [[TMP41]]) // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK1: .untied.jmp.7.i: // CHECK1-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP13]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK1-NEXT: store i32 10, ptr [[TMP15]], align 4 -// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: [[TMP44:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP43]]) -// CHECK1-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: store i32 5, ptr [[TMP45]], align 4 -// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP46]], ptr [[TMP47]]) // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK1: .untied.jmp.10.i: -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]]) #[[ATTR4]] -// CHECK1-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP15]]) #[[ATTR4]] +// CHECK1-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: call void @__kmpc_free(i32 [[TMP49]], ptr [[TMP15]], ptr inttoptr (i64 7 to ptr)) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) #[[ATTR4]] -// CHECK1-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP13]]) #[[ATTR4]] +// CHECK1-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: br label [[CLEANUP_I]] // CHECK1: cleanup.i: -// CHECK1-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK1-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK1: .omp_outlined..17.exit: // CHECK1-NEXT: ret i32 0 @@ -1171,7 +1182,7 @@ void test_transparent() // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1244,17 +1255,17 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK1-NEXT: store i32 0, ptr [[TMP9]], align 4 // CHECK1-NEXT: ret i32 0 @@ -1286,7 +1297,7 @@ void test_transparent() // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP2]]) @@ -1296,12 +1307,12 @@ void test_transparent() // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_23]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i64 48, i64 8, ptr @.omp_task_entry..26) -// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_25:%.*]], ptr [[TMP6]], i32 0, i32 0 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP7]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP9]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) -// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24]], ptr [[TMP6]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_25:%.*]], ptr [[TMP10]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_25]], ptr [[TMP6]], i32 0, i32 1 +// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_24:%.*]], ptr [[TMP10]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load double, ptr [[B]], align 8 // CHECK1-NEXT: store double [[TMP12]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP2]], ptr [[TMP6]]) @@ -1320,7 +1331,7 @@ void test_transparent() // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_25:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_24:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK1-NEXT: ret void @@ -1342,28 +1353,28 @@ void test_transparent() // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_25:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META123:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META126:![0-9]+]]) +// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_25]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META125:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META128:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META130:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META132:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map..25, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META132]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META132:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META134:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map..25, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META134]] // CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META132]] +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META134]] // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[TMP12]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP14]], align 4 // CHECK1-NEXT: [[CONV_I:%.*]] = fpext float [[TMP15]] to double // CHECK1-NEXT: [[ADD_I:%.*]] = fadd double [[CONV_I]], [[TMP13]] @@ -1384,25 +1395,25 @@ void test_transparent() // CHECK1-51-NEXT: entry: // CHECK1-51-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK1-51-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK1-51-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-51-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-51-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-51-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 // CHECK1-51-NEXT: [[AGG_CAPTURED4:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR11:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED12:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR13:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR13:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR19:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED20:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED28:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR29:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR29:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR37:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED38:%.*]] = alloca [[STRUCT_ANON_12:%.*]], align 1 // CHECK1-51-NEXT: [[FLAG:%.*]] = alloca i8, align 1 @@ -1412,8 +1423,8 @@ void test_transparent() // CHECK1-51-NEXT: [[AGG_CAPTURED41:%.*]] = alloca [[STRUCT_ANON_18:%.*]], align 1 // CHECK1-51-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-51-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-51-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 -// CHECK1-51-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK1-51-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK1-51-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-51-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1-51: arrayctor.loop: // CHECK1-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -1450,8 +1461,8 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP16]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // CHECK1-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP18]], ptr align 8 [[AGG_CAPTURED1]], i64 8, i1 false) -// CHECK1-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK1-51-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP19]], i64 0 +// CHECK1-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i64 0 // CHECK1-51-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP20]], i32 0, i32 0 // CHECK1-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP21]], align 8 // CHECK1-51-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP20]], i32 0, i32 1 @@ -1499,8 +1510,8 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP49:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP46]]) // CHECK1-51-NEXT: [[TMP50:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK1-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP50]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 -// CHECK1-51-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 +// CHECK1-51-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK1-51-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK1-51-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP52]], i64 0 // CHECK1-51-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i32 0, i32 0 @@ -1537,8 +1548,8 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP74:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP50]], i32 2, ptr [[TMP52]], i32 0, ptr null) // CHECK1-51-NEXT: [[TMP75:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK1-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP75]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 -// CHECK1-51-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 +// CHECK1-51-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK1-51-NEXT: [[TMP78:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 // CHECK1-51-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP77]], i64 0 // CHECK1-51-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP79]], i32 0, i32 0 @@ -1575,7 +1586,7 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP99:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP75]], i32 2, ptr [[TMP77]], i32 0, ptr null) // CHECK1-51-NEXT: [[TMP100:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) // CHECK1-51-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP100]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP102:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP102:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 // CHECK1-51-NEXT: [[TMP103:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 0 // CHECK1-51-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 0 // CHECK1-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP104]], align 8 @@ -1583,7 +1594,7 @@ void test_transparent() // CHECK1-51-NEXT: store i64 4, ptr [[TMP105]], align 8 // CHECK1-51-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 2 // CHECK1-51-NEXT: store i8 3, ptr [[TMP106]], align 8 -// CHECK1-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK1-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK1-51-NEXT: [[TMP107:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK1-51-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 1 // CHECK1-51-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP108]], i32 0, i32 0 @@ -1620,7 +1631,7 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP127:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP100]], i32 3, ptr [[TMP102]], i32 0, ptr null) // CHECK1-51-NEXT: [[TMP128:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry..12) // CHECK1-51-NEXT: [[TMP129:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], ptr [[TMP128]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP130:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR29]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP130:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR29]], i64 0, i64 0 // CHECK1-51-NEXT: [[TMP131:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP130]], i64 0 // CHECK1-51-NEXT: [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP131]], i32 0, i32 0 // CHECK1-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP132]], align 8 @@ -1628,7 +1639,7 @@ void test_transparent() // CHECK1-51-NEXT: store i64 4, ptr [[TMP133]], align 8 // CHECK1-51-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP131]], i32 0, i32 2 // CHECK1-51-NEXT: store i8 8, ptr [[TMP134]], align 8 -// CHECK1-51-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK1-51-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK1-51-NEXT: [[TMP135:%.*]] = ptrtoint ptr [[ARRAYIDX30]] to i64 // CHECK1-51-NEXT: [[TMP136:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP130]], i64 1 // CHECK1-51-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP136]], i32 0, i32 0 @@ -1683,9 +1694,9 @@ void test_transparent() // CHECK1-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP169]], ptr align 8 [[AGG_CAPTURED40]], i64 8, i1 false) // CHECK1-51-NEXT: [[TMP170:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP166]]) // CHECK1-51-NEXT: [[TMP171:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..23) -// CHECK1-51-NEXT: [[TMP172:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21:%.*]], ptr [[TMP171]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21]], ptr [[TMP171]], i32 0, i32 2 -// CHECK1-51-NEXT: [[TMP174:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22:%.*]], ptr [[TMP173]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP172:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.*]], ptr [[TMP171]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22]], ptr [[TMP171]], i32 0, i32 2 +// CHECK1-51-NEXT: [[TMP174:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21:%.*]], ptr [[TMP173]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP175:%.*]] = load i32, ptr [[C]], align 128 // CHECK1-51-NEXT: store i32 [[TMP175]], ptr [[TMP174]], align 128 // CHECK1-51-NEXT: [[TMP176:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP172]], i32 0, i32 2 @@ -1695,13 +1706,13 @@ void test_transparent() // CHECK1-51-NEXT: store i32 [[TMP178]], ptr [[RETVAL]], align 4 // CHECK1-51-NEXT: [[TMP179:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-51-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP179]]) -// CHECK1-51-NEXT: [[ARRAY_BEGIN42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 +// CHECK1-51-NEXT: [[ARRAY_BEGIN42:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP180:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN42]], i64 2 // CHECK1-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1-51: arraydestroy.body: // CHECK1-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP180]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK1-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN42]] // CHECK1-51-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE43:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1-51: arraydestroy.done43: @@ -1752,10 +1763,10 @@ void test_transparent() // CHECK1-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] // CHECK1-51-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] // CHECK1-51-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] // CHECK1-51-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 // CHECK1-51-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] // CHECK1-51-NEXT: store i32 10, ptr [[TMP12]], align 4 // CHECK1-51-NEXT: ret i32 0 // @@ -1779,20 +1790,20 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK1-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META22]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK1-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK1-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK1-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 // CHECK1-51-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK1-51-NEXT: ret i32 0 // @@ -1817,42 +1828,42 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK1-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK1-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK1-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK1-51-NEXT: ] // CHECK1-51: .untied.done..i: -// CHECK1-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK1-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK1-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK1-51: .untied.jmp..i: -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK1-51-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK1-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32]] -// CHECK1-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34]] +// CHECK1-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] // CHECK1-51-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] // CHECK1-51: .untied.jmp.1.i: -// CHECK1-51-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32]] +// CHECK1-51-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34]] // CHECK1-51-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[TMP15]], ptr @.gomp_critical_user_.var) -// CHECK1-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META32]] +// CHECK1-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] // CHECK1-51-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[TMP15]], ptr @.gomp_critical_user_.var) -// CHECK1-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK1-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK1-51-NEXT: br label [[CLEANUP_I]] // CHECK1-51: cleanup.i: -// CHECK1-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK1-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] // CHECK1-51: .omp_outlined..3.exit: // CHECK1-51-NEXT: ret i32 0 @@ -1878,39 +1889,39 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK1-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK1-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK1-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK1-51-NEXT: ] // CHECK1-51: .untied.done..i: -// CHECK1-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK1-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK1-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK1-51: .untied.jmp..i: -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK1-51-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK1-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42]] -// CHECK1-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44]] +// CHECK1-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] // CHECK1-51-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] // CHECK1-51: .untied.jmp.1.i: -// CHECK1-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META42]] -// CHECK1-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK1-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK1-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK1-51-NEXT: br label [[CLEANUP_I]] // CHECK1-51: cleanup.i: -// CHECK1-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK1-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] // CHECK1-51: .omp_outlined..5.exit: // CHECK1-51-NEXT: ret i32 0 @@ -1936,39 +1947,39 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK1-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK1-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK1-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK1-51-NEXT: ] // CHECK1-51: .untied.done..i: -// CHECK1-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK1-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK1-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK1-51: .untied.jmp..i: -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK1-51-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK1-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52]] -// CHECK1-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54]] +// CHECK1-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] // CHECK1-51-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] // CHECK1-51: .untied.jmp.1.i: -// CHECK1-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META52]] -// CHECK1-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK1-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK1-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK1-51-NEXT: br label [[CLEANUP_I]] // CHECK1-51: cleanup.i: -// CHECK1-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK1-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] // CHECK1-51: .omp_outlined..7.exit: // CHECK1-51-NEXT: ret i32 0 @@ -1993,18 +2004,18 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK1-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META62]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK1-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] // CHECK1-51-NEXT: ret i32 0 // // @@ -2027,18 +2038,18 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META72:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK1-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META72]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK1-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] // CHECK1-51-NEXT: ret i32 0 // // @@ -2061,18 +2072,18 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META82:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK1-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META82]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK1-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META84]] // CHECK1-51-NEXT: ret i32 0 // // @@ -2095,18 +2106,18 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META92:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK1-51-NEXT: store i32 3, ptr @a, align 4, !noalias [[META92]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK1-51-NEXT: store i32 3, ptr @a, align 4, !noalias [[META94]] // CHECK1-51-NEXT: ret i32 0 // // @@ -2129,19 +2140,19 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META102:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK1-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META102]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK1-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK1-51-NEXT: store i32 5, ptr [[TMP9]], align 128 // CHECK1-51-NEXT: ret i32 0 // @@ -2181,33 +2192,33 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 // CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-51-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-51-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] // CHECK1-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META112]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] // CHECK1-51-NEXT: store i32 4, ptr [[TMP12]], align 128 -// CHECK1-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META112]] +// CHECK1-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META114]] // CHECK1-51-NEXT: ret i32 0 // // // CHECK1-51-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-51-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-51-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-51-NEXT: entry: // CHECK1-51-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-51-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-51-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-51-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK1-51-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK1-51-NEXT: ret void // // @@ -2223,13 +2234,13 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 // CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK1-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22]], ptr [[TMP4]], i32 0, i32 2 +// CHECK1-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 -// CHECK1-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22]], ptr [[TMP4]], i32 0, i32 3 +// CHECK1-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21]], ptr [[TMP4]], i32 0, i32 3 // CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK1-51-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 // CHECK1-51-NEXT: ret void @@ -2255,30 +2266,30 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21]], ptr [[TMP3]], i32 0, i32 2 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]]) +// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22]], ptr [[TMP3]], i32 0, i32 2 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..22, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..22, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 -// CHECK1-51-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK1-51-NEXT: switch i32 [[TMP17]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK1-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] @@ -2289,73 +2300,73 @@ void test_transparent() // CHECK1-51-NEXT: i32 5, label [[DOTUNTIED_JMP_10_I:%.*]] // CHECK1-51-NEXT: ] // CHECK1-51: .untied.done..i: -// CHECK1-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK1-51: .untied.jmp..i: -// CHECK1-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: store i32 1, ptr [[TMP18]], align 4 -// CHECK1-51-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP19]], ptr [[TMP20]]) // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT:%.*]] // CHECK1-51: .untied.jmp.2.i: // CHECK1-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) -// CHECK1-51-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: [[DOTS2__VOID_ADDR_I:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP22]], i64 4, ptr inttoptr (i64 7 to ptr)) // CHECK1-51-NEXT: store ptr [[DOTS2__VOID_ADDR_I]], ptr [[TMP14]], align 8 -// CHECK1-51-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: store i32 2, ptr [[TMP23]], align 4 -// CHECK1-51-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP24]], ptr [[TMP25]]) // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK1-51: .untied.jmp.3.i: // CHECK1-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]]) // CHECK1-51-NEXT: store i32 0, ptr [[TMP15]], align 4 -// CHECK1-51-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP28:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP27]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..21) // CHECK1-51-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP28]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP12]], align 128 // CHECK1-51-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 128 -// CHECK1-51-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP32:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP31]], ptr [[TMP28]]) -// CHECK1-51-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: store i32 3, ptr [[TMP33]], align 4 -// CHECK1-51-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP36:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP34]], ptr [[TMP35]]) // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK1-51: .untied.jmp.5.i: -// CHECK1-51-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP38:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[TMP37]], i32 0) -// CHECK1-51-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: store i32 4, ptr [[TMP39]], align 4 -// CHECK1-51-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP40]], ptr [[TMP41]]) // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK1-51: .untied.jmp.7.i: // CHECK1-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) // CHECK1-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP13]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false) -// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK1-51-NEXT: store i32 10, ptr [[TMP15]], align 4 -// CHECK1-51-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP44:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP43]]) -// CHECK1-51-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: store i32 5, ptr [[TMP45]], align 4 -// CHECK1-51-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK1-51-NEXT: [[TMP47:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK1-51-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK1-51-NEXT: [[TMP47:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK1-51-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP46]], ptr [[TMP47]]) // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK1-51: .untied.jmp.10.i: -// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP15]]) #[[ATTR4]] +// CHECK1-51-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: call void @__kmpc_free(i32 [[TMP49]], ptr [[TMP15]], ptr inttoptr (i64 7 to ptr)) -// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) #[[ATTR4]] -// CHECK1-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP13]]) #[[ATTR4]] +// CHECK1-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: br label [[CLEANUP_I]] // CHECK1-51: cleanup.i: -// CHECK1-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK1-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK1-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK1-51: .omp_outlined..19.exit: // CHECK1-51-NEXT: ret i32 0 @@ -2373,7 +2384,7 @@ void test_transparent() // // // CHECK1-51-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-51-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-51-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-51-NEXT: entry: // CHECK1-51-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-51-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2446,17 +2457,17 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META123:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META126:![0-9]+]]) +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META125:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META128:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META130:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META132:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] -// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META132:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META134:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK1-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] // CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK1-51-NEXT: store i32 0, ptr [[TMP9]], align 4 // CHECK1-51-NEXT: ret i32 0 @@ -2488,7 +2499,7 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-51-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-51-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-51-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-51-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK1-51-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK1-51-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP2]]) @@ -2498,12 +2509,12 @@ void test_transparent() // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_25]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-51-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 // CHECK1-51-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i64 48, i64 8, ptr @.omp_task_entry..28) -// CHECK1-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27:%.*]], ptr [[TMP6]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP7]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK1-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP9]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) -// CHECK1-51-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26]], ptr [[TMP6]], i32 0, i32 1 -// CHECK1-51-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_27:%.*]], ptr [[TMP10]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27]], ptr [[TMP6]], i32 0, i32 1 +// CHECK1-51-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_26:%.*]], ptr [[TMP10]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP12:%.*]] = load double, ptr [[B]], align 8 // CHECK1-51-NEXT: store double [[TMP12]], ptr [[TMP11]], align 8 // CHECK1-51-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP2]], ptr [[TMP6]]) @@ -2522,7 +2533,7 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_27:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_26:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK1-51-NEXT: ret void @@ -2544,28 +2555,28 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META133:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META136:![0-9]+]]) +// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META135:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META138:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META140:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META142:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META142]] -// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META142]] -// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..27, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META142]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META142]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META142]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META142]] -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META142]] -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META142]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META142:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META144:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META144]] +// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META144]] +// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..27, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META144]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META144]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META144]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META144]] +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META144]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META144]] // CHECK1-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META142]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META144]] // CHECK1-51-NEXT: [[TMP13:%.*]] = load double, ptr [[TMP12]], align 8 -// CHECK1-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK1-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK1-51-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP14]], align 4 // CHECK1-51-NEXT: [[CONV_I:%.*]] = fpext float [[TMP15]] to double // CHECK1-51-NEXT: [[ADD_I:%.*]] = fadd double [[CONV_I]], [[TMP13]] @@ -2583,29 +2594,29 @@ void test_transparent() // CHECK1-51-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK1-51-NEXT: [[E:%.*]] = alloca i32, align 4 // CHECK1-51-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_28:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_31:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR2:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR2:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR3:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED4:%.*]] = alloca [[STRUCT_ANON_34:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR6:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED7:%.*]] = alloca [[STRUCT_ANON_37:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR8:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR8:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR9:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[AGG_CAPTURED10:%.*]] = alloca [[STRUCT_ANON_40:%.*]], align 1 -// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK1-51-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [1 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK1-51-NEXT: [[DEP_COUNTER_ADDR12:%.*]] = alloca i64, align 8 // CHECK1-51-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK1-51-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..31) -// CHECK1-51-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29:%.*]], ptr [[TMP1]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29]], ptr [[TMP1]], i32 0, i32 1 -// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_30:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30]], ptr [[TMP1]], i32 0, i32 1 +// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_29:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-51-NEXT: store i32 [[TMP5]], ptr [[TMP4]], align 8 -// CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK1-51-NEXT: [[TMP7:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP6]], i64 0 +// CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP7:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP6]], i64 0 // CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP7]], i32 0, i32 0 // CHECK1-51-NEXT: store i64 0, ptr [[TMP8]], align 8 // CHECK1-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP7]], i32 0, i32 1 @@ -2623,12 +2634,12 @@ void test_transparent() // CHECK1-51-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR]], align 8 // CHECK1-51-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]], i32 2, ptr [[TMP6]], i32 0, ptr null) // CHECK1-51-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..34) -// CHECK1-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32:%.*]], ptr [[TMP17]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32]], ptr [[TMP17]], i32 0, i32 1 -// CHECK1-51-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_33:%.*]], ptr [[TMP19]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33:%.*]], ptr [[TMP17]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33]], ptr [[TMP17]], i32 0, i32 1 +// CHECK1-51-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_32:%.*]], ptr [[TMP19]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-51-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 8 -// CHECK1-51-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR2]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR2]], i64 0, i64 0 // CHECK1-51-NEXT: [[TMP23:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP22]], i64 0 // CHECK1-51-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP23]], i32 0, i32 0 // CHECK1-51-NEXT: store i64 0, ptr [[TMP24]], align 8 @@ -2647,12 +2658,12 @@ void test_transparent() // CHECK1-51-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR3]], align 8 // CHECK1-51-NEXT: [[TMP32:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP17]], i32 2, ptr [[TMP22]], i32 0, ptr null) // CHECK1-51-NEXT: [[TMP33:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..37) -// CHECK1-51-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35:%.*]], ptr [[TMP33]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35]], ptr [[TMP33]], i32 0, i32 1 -// CHECK1-51-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_36:%.*]], ptr [[TMP35]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36:%.*]], ptr [[TMP33]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36]], ptr [[TMP33]], i32 0, i32 1 +// CHECK1-51-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_35:%.*]], ptr [[TMP35]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP37:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-51-NEXT: store i32 [[TMP37]], ptr [[TMP36]], align 8 -// CHECK1-51-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 // CHECK1-51-NEXT: [[TMP39:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP38]], i64 0 // CHECK1-51-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP39]], i32 0, i32 0 // CHECK1-51-NEXT: store i64 0, ptr [[TMP40]], align 8 @@ -2671,12 +2682,12 @@ void test_transparent() // CHECK1-51-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR6]], align 8 // CHECK1-51-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP33]], i32 2, ptr [[TMP38]], i32 0, ptr null) // CHECK1-51-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..40) -// CHECK1-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38:%.*]], ptr [[TMP49]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38]], ptr [[TMP49]], i32 0, i32 1 -// CHECK1-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_39:%.*]], ptr [[TMP51]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39:%.*]], ptr [[TMP49]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39]], ptr [[TMP49]], i32 0, i32 1 +// CHECK1-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_38:%.*]], ptr [[TMP51]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP53:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-51-NEXT: store i32 [[TMP53]], ptr [[TMP52]], align 8 -// CHECK1-51-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR8]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR8]], i64 0, i64 0 // CHECK1-51-NEXT: [[TMP55:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i64 0 // CHECK1-51-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP55]], i32 0, i32 0 // CHECK1-51-NEXT: store i64 0, ptr [[TMP56]], align 8 @@ -2695,12 +2706,12 @@ void test_transparent() // CHECK1-51-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR9]], align 8 // CHECK1-51-NEXT: [[TMP64:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP49]], i32 2, ptr [[TMP54]], i32 0, ptr null) // CHECK1-51-NEXT: [[TMP65:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..43) -// CHECK1-51-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_41:%.*]], ptr [[TMP65]], i32 0, i32 0 -// CHECK1-51-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_41]], ptr [[TMP65]], i32 0, i32 1 -// CHECK1-51-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_42:%.*]], ptr [[TMP67]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42:%.*]], ptr [[TMP65]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42]], ptr [[TMP65]], i32 0, i32 1 +// CHECK1-51-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_41:%.*]], ptr [[TMP67]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP69:%.*]] = load i32, ptr [[A]], align 4 // CHECK1-51-NEXT: store i32 [[TMP69]], ptr [[TMP68]], align 8 -// CHECK1-51-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 +// CHECK1-51-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 // CHECK1-51-NEXT: [[TMP71:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP70]], i64 0 // CHECK1-51-NEXT: [[TMP72:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP71]], i32 0, i32 0 // CHECK1-51-NEXT: store i64 0, ptr [[TMP72]], align 8 @@ -2721,7 +2732,7 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_30:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_29:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK1-51-NEXT: ret void @@ -2743,26 +2754,26 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META145:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META148:![0-9]+]]) +// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META147:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META150:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META152:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META154:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META154]] -// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META154]] -// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..30, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META154]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META154]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META154]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META154]] -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META154]] -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META154]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META154:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META156:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META156]] +// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META156]] +// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..30, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META156]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META156]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META156]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META156]] +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META156]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META156]] // CHECK1-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META154]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META156]] // CHECK1-51-NEXT: store i32 13, ptr [[TMP12]], align 4 // CHECK1-51-NEXT: ret i32 0 // @@ -2775,7 +2786,7 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_33:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_32:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK1-51-NEXT: ret void @@ -2797,26 +2808,26 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META155:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META158:![0-9]+]]) +// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META157:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META160:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META162:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META164:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META164]] -// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META164]] -// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..33, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META164]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META164]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META164]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META164]] -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META164]] -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META164]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META164:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META166:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META166]] +// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META166]] +// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..33, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META166]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META166]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META166]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META166]] +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META166]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META166]] // CHECK1-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META164]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META166]] // CHECK1-51-NEXT: store i32 14, ptr [[TMP12]], align 4 // CHECK1-51-NEXT: ret i32 0 // @@ -2829,7 +2840,7 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_36:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_35:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK1-51-NEXT: ret void @@ -2851,26 +2862,26 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META165:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META168:![0-9]+]]) +// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META167:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META170:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META172:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META174:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META174]] -// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META174]] -// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..36, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META174]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META174]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META174]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META174]] -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META174]] -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META174]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META174:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META176:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META176]] +// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META176]] +// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..36, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META176]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META176]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META176]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META176]] +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META176]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META176]] // CHECK1-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META174]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META176]] // CHECK1-51-NEXT: store i32 15, ptr [[TMP12]], align 4 // CHECK1-51-NEXT: ret i32 0 // @@ -2883,7 +2894,7 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_39:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_38:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK1-51-NEXT: ret void @@ -2905,26 +2916,26 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META175:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META178:![0-9]+]]) +// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META177:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META180:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META182:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META184:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META184]] -// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META184]] -// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..39, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META184]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META184]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META184]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META184]] -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META184]] -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META184]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META184:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META186:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META186]] +// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META186]] +// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..39, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META186]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META186]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META186]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META186]] +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META186]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META186]] // CHECK1-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META184]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META186]] // CHECK1-51-NEXT: store i32 16, ptr [[TMP12]], align 4 // CHECK1-51-NEXT: ret i32 0 // @@ -2937,7 +2948,7 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_42:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_41:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK1-51-NEXT: ret void @@ -2959,26 +2970,26 @@ void test_transparent() // CHECK1-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK1-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_41:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK1-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_41]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META185:![0-9]+]]) -// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META188:![0-9]+]]) +// CHECK1-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42]], ptr [[TMP3]], i32 0, i32 1 +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META187:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META190:![0-9]+]]) // CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META192:![0-9]+]]) -// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META194:![0-9]+]] -// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META194]] -// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META194]] -// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..42, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META194]] -// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META194]] -// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META194]] -// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META194]] -// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META194]] -// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META194]] +// CHECK1-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META194:![0-9]+]]) +// CHECK1-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META196:![0-9]+]] +// CHECK1-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META196]] +// CHECK1-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META196]] +// CHECK1-51-NEXT: store ptr @.omp_task_privates_map..42, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META196]] +// CHECK1-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META196]] +// CHECK1-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META196]] +// CHECK1-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META196]] +// CHECK1-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META196]] +// CHECK1-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META196]] // CHECK1-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META194]] +// CHECK1-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META196]] // CHECK1-51-NEXT: store i32 17, ptr [[TMP12]], align 4 // CHECK1-51-NEXT: ret i32 0 // @@ -2995,22 +3006,22 @@ void test_transparent() // CHECK2-NEXT: entry: // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK2-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK2-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK2-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 -// CHECK2-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x %struct.kmp_depend_info], align 8 +// CHECK2-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK2-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 // CHECK2-NEXT: [[AGG_CAPTURED4:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK2-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK2-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-NEXT: [[DEP_COUNTER_ADDR11:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AGG_CAPTURED12:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK2-NEXT: [[DOTDEP_ARR_ADDR13:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK2-NEXT: [[DOTDEP_ARR_ADDR13:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-NEXT: [[DEP_COUNTER_ADDR19:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AGG_CAPTURED20:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK2-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK2-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[AGG_CAPTURED28:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 // CHECK2-NEXT: [[FLAG:%.*]] = alloca i8, align 1 @@ -3020,8 +3031,8 @@ void test_transparent() // CHECK2-NEXT: [[AGG_CAPTURED31:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK2-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 -// CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK2-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK2-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2: arrayctor.loop: // CHECK2-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -3058,8 +3069,8 @@ void test_transparent() // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP16]], i32 0, i32 0 // CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP18]], ptr align 8 [[AGG_CAPTURED1]], i64 8, i1 false) -// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP19]], i64 0 +// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i64 0 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP20]], i32 0, i32 0 // CHECK2-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP21]], align 8 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP20]], i32 0, i32 1 @@ -3107,8 +3118,8 @@ void test_transparent() // CHECK2-NEXT: [[TMP49:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP46]]) // CHECK2-NEXT: [[TMP50:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP50]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 -// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 +// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK2-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP52]], i64 0 // CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i32 0, i32 0 @@ -3145,8 +3156,8 @@ void test_transparent() // CHECK2-NEXT: [[TMP74:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP50]], i32 2, ptr [[TMP52]], i32 0, ptr null) // CHECK2-NEXT: [[TMP75:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP75]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 -// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 +// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK2-NEXT: [[TMP78:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 // CHECK2-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP77]], i64 0 // CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP79]], i32 0, i32 0 @@ -3183,7 +3194,7 @@ void test_transparent() // CHECK2-NEXT: [[TMP99:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP75]], i32 2, ptr [[TMP77]], i32 0, ptr null) // CHECK2-NEXT: [[TMP100:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) // CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP100]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 // CHECK2-NEXT: [[TMP103:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 0 // CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 0 // CHECK2-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP104]], align 8 @@ -3191,7 +3202,7 @@ void test_transparent() // CHECK2-NEXT: store i64 4, ptr [[TMP105]], align 8 // CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 2 // CHECK2-NEXT: store i8 3, ptr [[TMP106]], align 8 -// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK2-NEXT: [[TMP107:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK2-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 1 // CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP108]], i32 0, i32 0 @@ -3246,9 +3257,9 @@ void test_transparent() // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP141]], ptr align 8 [[AGG_CAPTURED30]], i64 8, i1 false) // CHECK2-NEXT: [[TMP142:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP138]]) // CHECK2-NEXT: [[TMP143:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..21) -// CHECK2-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP143]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP143]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP145]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP143]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP143]], i32 0, i32 2 +// CHECK2-NEXT: [[TMP146:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP145]], i32 0, i32 0 // CHECK2-NEXT: [[TMP147:%.*]] = load i32, ptr [[C]], align 128 // CHECK2-NEXT: store i32 [[TMP147]], ptr [[TMP146]], align 128 // CHECK2-NEXT: [[TMP148:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP144]], i32 0, i32 2 @@ -3258,13 +3269,13 @@ void test_transparent() // CHECK2-NEXT: store i32 [[TMP150]], ptr [[RETVAL]], align 4 // CHECK2-NEXT: [[TMP151:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK2-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP151]]) -// CHECK2-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 +// CHECK2-NEXT: [[ARRAY_BEGIN32:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 // CHECK2-NEXT: [[TMP152:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN32]], i64 2 // CHECK2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP152]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN32]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE33:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done33: @@ -3315,10 +3326,10 @@ void test_transparent() // CHECK2-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] // CHECK2-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 -// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] // CHECK2-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] // CHECK2-NEXT: store i32 10, ptr [[TMP12]], align 4 // CHECK2-NEXT: ret i32 0 // @@ -3342,20 +3353,20 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-NEXT: store i32 15, ptr @a, align 4, !noalias [[META22]] -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK2-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK2-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 // CHECK2-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK2-NEXT: ret i32 0 // @@ -3380,42 +3391,42 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK2-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK2-NEXT: ] // CHECK2: .untied.done..i: -// CHECK2-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK2-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK2-NEXT: br label [[CLEANUP_I:%.*]] // CHECK2: .untied.jmp..i: -// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK2-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32]] -// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34]] +// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] // CHECK2-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] // CHECK2: .untied.jmp.1.i: -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32]] +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34]] // CHECK2-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[TMP15]], ptr @.gomp_critical_user_.var) -// CHECK2-NEXT: store i32 1, ptr @a, align 4, !noalias [[META32]] +// CHECK2-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] // CHECK2-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[TMP15]], ptr @.gomp_critical_user_.var) -// CHECK2-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK2-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK2-NEXT: br label [[CLEANUP_I]] // CHECK2: cleanup.i: -// CHECK2-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK2-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] // CHECK2: .omp_outlined..3.exit: // CHECK2-NEXT: ret i32 0 @@ -3441,39 +3452,39 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK2-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK2-NEXT: ] // CHECK2: .untied.done..i: -// CHECK2-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK2-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK2-NEXT: br label [[CLEANUP_I:%.*]] // CHECK2: .untied.jmp..i: -// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK2-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42]] -// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44]] +// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] // CHECK2-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] // CHECK2: .untied.jmp.1.i: -// CHECK2-NEXT: store i32 1, ptr @a, align 4, !noalias [[META42]] -// CHECK2-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK2-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK2-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK2-NEXT: br label [[CLEANUP_I]] // CHECK2: cleanup.i: -// CHECK2-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK2-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] // CHECK2: .omp_outlined..5.exit: // CHECK2-NEXT: ret i32 0 @@ -3499,39 +3510,39 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK2-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK2-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK2-NEXT: ] // CHECK2: .untied.done..i: -// CHECK2-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK2-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK2-NEXT: br label [[CLEANUP_I:%.*]] // CHECK2: .untied.jmp..i: -// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK2-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52]] -// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] +// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54]] +// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] // CHECK2-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] // CHECK2: .untied.jmp.1.i: -// CHECK2-NEXT: store i32 1, ptr @a, align 4, !noalias [[META52]] -// CHECK2-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK2-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK2-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK2-NEXT: br label [[CLEANUP_I]] // CHECK2: cleanup.i: -// CHECK2-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK2-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] // CHECK2: .omp_outlined..7.exit: // CHECK2-NEXT: ret i32 0 @@ -3556,18 +3567,18 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-NEXT: store i32 2, ptr @a, align 4, !noalias [[META62]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] // CHECK2-NEXT: ret i32 0 // // @@ -3590,18 +3601,18 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META72:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-NEXT: store i32 2, ptr @a, align 4, !noalias [[META72]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] // CHECK2-NEXT: ret i32 0 // // @@ -3624,18 +3635,18 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META82:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-NEXT: store i32 3, ptr @a, align 4, !noalias [[META82]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-NEXT: store i32 3, ptr @a, align 4, !noalias [[META84]] // CHECK2-NEXT: ret i32 0 // // @@ -3658,19 +3669,19 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META92:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-NEXT: store i32 4, ptr @a, align 4, !noalias [[META92]] -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-NEXT: store i32 4, ptr @a, align 4, !noalias [[META94]] +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK2-NEXT: store i32 5, ptr [[TMP9]], align 128 // CHECK2-NEXT: ret i32 0 // @@ -3710,33 +3721,33 @@ void test_transparent() // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], ptr [[TMP3]], i32 0, i32 2 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META102:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] // CHECK2-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META102]] +// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META104]] // CHECK2-NEXT: store i32 4, ptr [[TMP12]], align 128 -// CHECK2-NEXT: store i32 4, ptr @a, align 4, !noalias [[META102]] +// CHECK2-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] // CHECK2-NEXT: ret i32 0 // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-NEXT: ret void // // @@ -3752,13 +3763,13 @@ void test_transparent() // CHECK2-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 // CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 -// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 2 +// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK2-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 -// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 3 +// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 3 // CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK2-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 // CHECK2-NEXT: ret void @@ -3784,30 +3795,30 @@ void test_transparent() // CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP3]], i32 0, i32 2 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]]) +// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] -// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 -// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK2-NEXT: switch i32 [[TMP17]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK2-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] @@ -3818,73 +3829,73 @@ void test_transparent() // CHECK2-NEXT: i32 5, label [[DOTUNTIED_JMP_10_I:%.*]] // CHECK2-NEXT: ] // CHECK2: .untied.done..i: -// CHECK2-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: br label [[CLEANUP_I:%.*]] // CHECK2: .untied.jmp..i: -// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: store i32 1, ptr [[TMP18]], align 4 -// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP19]], ptr [[TMP20]]) // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK2: .untied.jmp.2.i: // CHECK2-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) -// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: [[DOTS2__VOID_ADDR_I:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP22]], i64 4, ptr inttoptr (i64 7 to ptr)) // CHECK2-NEXT: store ptr [[DOTS2__VOID_ADDR_I]], ptr [[TMP14]], align 8 -// CHECK2-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: store i32 2, ptr [[TMP23]], align 4 -// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK2-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK2-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP24]], ptr [[TMP25]]) // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK2: .untied.jmp.3.i: // CHECK2-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]]) // CHECK2-NEXT: store i32 0, ptr [[TMP15]], align 4 -// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: [[TMP28:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP27]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..19) // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.*]], ptr [[TMP28]], i32 0, i32 2 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP12]], align 128 // CHECK2-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 128 -// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: [[TMP32:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP31]], ptr [[TMP28]]) -// CHECK2-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: store i32 3, ptr [[TMP33]], align 4 -// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK2-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK2-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: [[TMP36:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP34]], ptr [[TMP35]]) // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK2: .untied.jmp.5.i: -// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: [[TMP38:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[TMP37]], i32 0) -// CHECK2-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: store i32 4, ptr [[TMP39]], align 4 -// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK2-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK2-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP40]], ptr [[TMP41]]) // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK2: .untied.jmp.7.i: // CHECK2-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP13]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false) -// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK2-NEXT: store i32 10, ptr [[TMP15]], align 4 -// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: [[TMP44:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP43]]) -// CHECK2-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: store i32 5, ptr [[TMP45]], align 4 -// CHECK2-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] -// CHECK2-NEXT: [[TMP47:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] +// CHECK2-NEXT: [[TMP47:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP46]], ptr [[TMP47]]) // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK2: .untied.jmp.10.i: -// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]]) #[[ATTR4]] -// CHECK2-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP15]]) #[[ATTR4]] +// CHECK2-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: call void @__kmpc_free(i32 [[TMP49]], ptr [[TMP15]], ptr inttoptr (i64 7 to ptr)) -// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) #[[ATTR4]] -// CHECK2-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP13]]) #[[ATTR4]] +// CHECK2-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: br label [[CLEANUP_I]] // CHECK2: cleanup.i: -// CHECK2-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK2-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK2: .omp_outlined..17.exit: // CHECK2-NEXT: ret i32 0 @@ -3902,7 +3913,7 @@ void test_transparent() // // // CHECK2-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3975,17 +3986,17 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]]) +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] // CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK2-NEXT: store i32 0, ptr [[TMP9]], align 4 // CHECK2-NEXT: ret i32 0 @@ -4017,7 +4028,7 @@ void test_transparent() // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP2]]) @@ -4027,12 +4038,12 @@ void test_transparent() // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_23]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 // CHECK2-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i64 48, i64 8, ptr @.omp_task_entry..26) -// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_25:%.*]], ptr [[TMP6]], i32 0, i32 0 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP7]], i32 0, i32 0 // CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK2-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP9]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) -// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24]], ptr [[TMP6]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_25:%.*]], ptr [[TMP10]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_25]], ptr [[TMP6]], i32 0, i32 1 +// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_24:%.*]], ptr [[TMP10]], i32 0, i32 0 // CHECK2-NEXT: [[TMP12:%.*]] = load double, ptr [[B]], align 8 // CHECK2-NEXT: store double [[TMP12]], ptr [[TMP11]], align 8 // CHECK2-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP2]], ptr [[TMP6]]) @@ -4051,7 +4062,7 @@ void test_transparent() // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_25:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_24:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK2-NEXT: ret void @@ -4073,28 +4084,28 @@ void test_transparent() // CHECK2-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_25:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24]], ptr [[TMP3]], i32 0, i32 1 -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META123:![0-9]+]]) -// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META126:![0-9]+]]) +// CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_25]], ptr [[TMP3]], i32 0, i32 1 +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META125:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META128:![0-9]+]]) // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META130:![0-9]+]]) -// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META132:![0-9]+]] -// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-NEXT: store ptr @.omp_task_privates_map..25, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META132]] +// CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META132:![0-9]+]]) +// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META134:![0-9]+]] +// CHECK2-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-NEXT: store ptr @.omp_task_privates_map..25, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META134]] // CHECK2-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META132]] +// CHECK2-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META134]] // CHECK2-NEXT: [[TMP13:%.*]] = load double, ptr [[TMP12]], align 8 -// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK2-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK2-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP14]], align 4 // CHECK2-NEXT: [[CONV_I:%.*]] = fpext float [[TMP15]] to double // CHECK2-NEXT: [[ADD_I:%.*]] = fadd double [[CONV_I]], [[TMP13]] @@ -4115,25 +4126,25 @@ void test_transparent() // CHECK2-51-NEXT: entry: // CHECK2-51-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK2-51-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK2-51-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK2-51-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK2-51-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK2-51-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED3:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 // CHECK2-51-NEXT: [[AGG_CAPTURED4:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR11:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED12:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR13:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR13:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR19:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED20:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED28:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR29:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR29:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR37:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED38:%.*]] = alloca [[STRUCT_ANON_12:%.*]], align 1 // CHECK2-51-NEXT: [[FLAG:%.*]] = alloca i8, align 1 @@ -4143,8 +4154,8 @@ void test_transparent() // CHECK2-51-NEXT: [[AGG_CAPTURED41:%.*]] = alloca [[STRUCT_ANON_18:%.*]], align 1 // CHECK2-51-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK2-51-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK2-51-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 -// CHECK2-51-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK2-51-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK2-51-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK2-51-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK2-51: arrayctor.loop: // CHECK2-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -4181,8 +4192,8 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP16]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 // CHECK2-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP18]], ptr align 8 [[AGG_CAPTURED1]], i64 8, i1 false) -// CHECK2-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK2-51-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP19]], i64 0 +// CHECK2-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP20:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i64 0 // CHECK2-51-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP20]], i32 0, i32 0 // CHECK2-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP21]], align 8 // CHECK2-51-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP20]], i32 0, i32 1 @@ -4230,8 +4241,8 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP49:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP46]]) // CHECK2-51-NEXT: [[TMP50:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK2-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP50]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 -// CHECK2-51-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 +// CHECK2-51-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK2-51-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK2-51-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP52]], i64 0 // CHECK2-51-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i32 0, i32 0 @@ -4268,8 +4279,8 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP74:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP50]], i32 2, ptr [[TMP52]], i32 0, ptr null) // CHECK2-51-NEXT: [[TMP75:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK2-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP75]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 -// CHECK2-51-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 +// CHECK2-51-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK2-51-NEXT: [[TMP78:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 // CHECK2-51-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP77]], i64 0 // CHECK2-51-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP79]], i32 0, i32 0 @@ -4306,7 +4317,7 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP99:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP75]], i32 2, ptr [[TMP77]], i32 0, ptr null) // CHECK2-51-NEXT: [[TMP100:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) // CHECK2-51-NEXT: [[TMP101:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP100]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP102:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP102:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 // CHECK2-51-NEXT: [[TMP103:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 0 // CHECK2-51-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 0 // CHECK2-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP104]], align 8 @@ -4314,7 +4325,7 @@ void test_transparent() // CHECK2-51-NEXT: store i64 4, ptr [[TMP105]], align 8 // CHECK2-51-NEXT: [[TMP106:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 2 // CHECK2-51-NEXT: store i8 3, ptr [[TMP106]], align 8 -// CHECK2-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK2-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK2-51-NEXT: [[TMP107:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK2-51-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 1 // CHECK2-51-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP108]], i32 0, i32 0 @@ -4351,7 +4362,7 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP127:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP100]], i32 3, ptr [[TMP102]], i32 0, ptr null) // CHECK2-51-NEXT: [[TMP128:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry..12) // CHECK2-51-NEXT: [[TMP129:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], ptr [[TMP128]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP130:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR29]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP130:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR29]], i64 0, i64 0 // CHECK2-51-NEXT: [[TMP131:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP130]], i64 0 // CHECK2-51-NEXT: [[TMP132:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP131]], i32 0, i32 0 // CHECK2-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP132]], align 8 @@ -4359,7 +4370,7 @@ void test_transparent() // CHECK2-51-NEXT: store i64 4, ptr [[TMP133]], align 8 // CHECK2-51-NEXT: [[TMP134:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP131]], i32 0, i32 2 // CHECK2-51-NEXT: store i8 8, ptr [[TMP134]], align 8 -// CHECK2-51-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK2-51-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK2-51-NEXT: [[TMP135:%.*]] = ptrtoint ptr [[ARRAYIDX30]] to i64 // CHECK2-51-NEXT: [[TMP136:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP130]], i64 1 // CHECK2-51-NEXT: [[TMP137:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP136]], i32 0, i32 0 @@ -4414,9 +4425,9 @@ void test_transparent() // CHECK2-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP169]], ptr align 8 [[AGG_CAPTURED40]], i64 8, i1 false) // CHECK2-51-NEXT: [[TMP170:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP166]]) // CHECK2-51-NEXT: [[TMP171:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..23) -// CHECK2-51-NEXT: [[TMP172:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21:%.*]], ptr [[TMP171]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21]], ptr [[TMP171]], i32 0, i32 2 -// CHECK2-51-NEXT: [[TMP174:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22:%.*]], ptr [[TMP173]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP172:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.*]], ptr [[TMP171]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22]], ptr [[TMP171]], i32 0, i32 2 +// CHECK2-51-NEXT: [[TMP174:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21:%.*]], ptr [[TMP173]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP175:%.*]] = load i32, ptr [[C]], align 128 // CHECK2-51-NEXT: store i32 [[TMP175]], ptr [[TMP174]], align 128 // CHECK2-51-NEXT: [[TMP176:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP172]], i32 0, i32 2 @@ -4426,13 +4437,13 @@ void test_transparent() // CHECK2-51-NEXT: store i32 [[TMP178]], ptr [[RETVAL]], align 4 // CHECK2-51-NEXT: [[TMP179:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK2-51-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP179]]) -// CHECK2-51-NEXT: [[ARRAY_BEGIN42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 +// CHECK2-51-NEXT: [[ARRAY_BEGIN42:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP180:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN42]], i64 2 // CHECK2-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK2-51: arraydestroy.body: // CHECK2-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP180]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK2-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN42]] // CHECK2-51-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE43:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2-51: arraydestroy.done43: @@ -4483,10 +4494,10 @@ void test_transparent() // CHECK2-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] // CHECK2-51-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] // CHECK2-51-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] // CHECK2-51-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 // CHECK2-51-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] // CHECK2-51-NEXT: store i32 10, ptr [[TMP12]], align 4 // CHECK2-51-NEXT: ret i32 0 // @@ -4510,20 +4521,20 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK2-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META22]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK2-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK2-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK2-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 // CHECK2-51-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK2-51-NEXT: ret i32 0 // @@ -4548,42 +4559,42 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK2-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK2-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK2-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK2-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK2-51-NEXT: ] // CHECK2-51: .untied.done..i: -// CHECK2-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK2-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK2-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK2-51: .untied.jmp..i: -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK2-51-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK2-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32]] -// CHECK2-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34]] +// CHECK2-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] // CHECK2-51-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] // CHECK2-51: .untied.jmp.1.i: -// CHECK2-51-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32]] +// CHECK2-51-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34]] // CHECK2-51-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[TMP15]], ptr @.gomp_critical_user_.var) -// CHECK2-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META32]] +// CHECK2-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] // CHECK2-51-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[TMP15]], ptr @.gomp_critical_user_.var) -// CHECK2-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK2-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK2-51-NEXT: br label [[CLEANUP_I]] // CHECK2-51: cleanup.i: -// CHECK2-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK2-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] // CHECK2-51: .omp_outlined..3.exit: // CHECK2-51-NEXT: ret i32 0 @@ -4609,39 +4620,39 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK2-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK2-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK2-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK2-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK2-51-NEXT: ] // CHECK2-51: .untied.done..i: -// CHECK2-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK2-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK2-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK2-51: .untied.jmp..i: -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK2-51-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK2-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42]] -// CHECK2-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44]] +// CHECK2-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] // CHECK2-51-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] // CHECK2-51: .untied.jmp.1.i: -// CHECK2-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META42]] -// CHECK2-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK2-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK2-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK2-51-NEXT: br label [[CLEANUP_I]] // CHECK2-51: cleanup.i: -// CHECK2-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK2-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] // CHECK2-51: .omp_outlined..5.exit: // CHECK2-51-NEXT: ret i32 0 @@ -4667,39 +4678,39 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK2-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK2-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK2-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK2-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK2-51-NEXT: ] // CHECK2-51: .untied.done..i: -// CHECK2-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK2-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK2-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK2-51: .untied.jmp..i: -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK2-51-NEXT: store i32 1, ptr [[TMP11]], align 4 -// CHECK2-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52]] -// CHECK2-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54]] +// CHECK2-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] // CHECK2-51-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP12]], ptr [[TMP13]]) // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] // CHECK2-51: .untied.jmp.1.i: -// CHECK2-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META52]] -// CHECK2-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK2-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK2-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK2-51-NEXT: br label [[CLEANUP_I]] // CHECK2-51: cleanup.i: -// CHECK2-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK2-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] // CHECK2-51: .omp_outlined..7.exit: // CHECK2-51-NEXT: ret i32 0 @@ -4724,18 +4735,18 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK2-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META62]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK2-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] // CHECK2-51-NEXT: ret i32 0 // // @@ -4758,18 +4769,18 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META72:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK2-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META72]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK2-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] // CHECK2-51-NEXT: ret i32 0 // // @@ -4792,18 +4803,18 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META82:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK2-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META82]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK2-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META84]] // CHECK2-51-NEXT: ret i32 0 // // @@ -4826,18 +4837,18 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META92:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK2-51-NEXT: store i32 3, ptr @a, align 4, !noalias [[META92]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK2-51-NEXT: store i32 3, ptr @a, align 4, !noalias [[META94]] // CHECK2-51-NEXT: ret i32 0 // // @@ -4860,19 +4871,19 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META102:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK2-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META102]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK2-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK2-51-NEXT: store i32 5, ptr [[TMP9]], align 128 // CHECK2-51-NEXT: ret i32 0 // @@ -4912,33 +4923,33 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 // CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-51-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-51-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] // CHECK2-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META112]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] // CHECK2-51-NEXT: store i32 4, ptr [[TMP12]], align 128 -// CHECK2-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META112]] +// CHECK2-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META114]] // CHECK2-51-NEXT: ret i32 0 // // // CHECK2-51-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK2-51-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-51-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-51-NEXT: entry: // CHECK2-51-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-51-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK2-51-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK2-51-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK2-51-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK2-51-NEXT: ret void // // @@ -4954,13 +4965,13 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 // CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK2-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22]], ptr [[TMP4]], i32 0, i32 2 +// CHECK2-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 -// CHECK2-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22]], ptr [[TMP4]], i32 0, i32 3 +// CHECK2-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21]], ptr [[TMP4]], i32 0, i32 3 // CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK2-51-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 // CHECK2-51-NEXT: ret void @@ -4986,30 +4997,30 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21]], ptr [[TMP3]], i32 0, i32 2 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]]) +// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22]], ptr [[TMP3]], i32 0, i32 2 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..22, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..22, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP15:%.*]] = load ptr, ptr [[TMP14]], align 8 -// CHECK2-51-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK2-51-NEXT: switch i32 [[TMP17]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK2-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] @@ -5020,73 +5031,73 @@ void test_transparent() // CHECK2-51-NEXT: i32 5, label [[DOTUNTIED_JMP_10_I:%.*]] // CHECK2-51-NEXT: ] // CHECK2-51: .untied.done..i: -// CHECK2-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK2-51: .untied.jmp..i: -// CHECK2-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: store i32 1, ptr [[TMP18]], align 4 -// CHECK2-51-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP19]], ptr [[TMP20]]) // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT:%.*]] // CHECK2-51: .untied.jmp.2.i: // CHECK2-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) -// CHECK2-51-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: [[DOTS2__VOID_ADDR_I:%.*]] = call ptr @__kmpc_alloc(i32 [[TMP22]], i64 4, ptr inttoptr (i64 7 to ptr)) // CHECK2-51-NEXT: store ptr [[DOTS2__VOID_ADDR_I]], ptr [[TMP14]], align 8 -// CHECK2-51-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: store i32 2, ptr [[TMP23]], align 4 -// CHECK2-51-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP24]], ptr [[TMP25]]) // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK2-51: .untied.jmp.3.i: // CHECK2-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]]) // CHECK2-51-NEXT: store i32 0, ptr [[TMP15]], align 4 -// CHECK2-51-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP28:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP27]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..21) // CHECK2-51-NEXT: [[TMP29:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP28]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP12]], align 128 // CHECK2-51-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 128 -// CHECK2-51-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP32:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP31]], ptr [[TMP28]]) -// CHECK2-51-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: store i32 3, ptr [[TMP33]], align 4 -// CHECK2-51-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP36:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP34]], ptr [[TMP35]]) // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK2-51: .untied.jmp.5.i: -// CHECK2-51-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP38:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[TMP37]], i32 0) -// CHECK2-51-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: store i32 4, ptr [[TMP39]], align 4 -// CHECK2-51-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP40]], ptr [[TMP41]]) // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK2-51: .untied.jmp.7.i: // CHECK2-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) // CHECK2-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP13]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false) -// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] // CHECK2-51-NEXT: store i32 10, ptr [[TMP15]], align 4 -// CHECK2-51-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP44:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[TMP43]]) -// CHECK2-51-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP45:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: store i32 5, ptr [[TMP45]], align 4 -// CHECK2-51-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] -// CHECK2-51-NEXT: [[TMP47:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK2-51-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] +// CHECK2-51-NEXT: [[TMP47:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK2-51-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP46]], ptr [[TMP47]]) // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK2-51: .untied.jmp.10.i: -// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP15]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP15]]) #[[ATTR4]] +// CHECK2-51-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: call void @__kmpc_free(i32 [[TMP49]], ptr [[TMP15]], ptr inttoptr (i64 7 to ptr)) -// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) #[[ATTR4]] -// CHECK2-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP13]]) #[[ATTR4]] +// CHECK2-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: br label [[CLEANUP_I]] // CHECK2-51: cleanup.i: -// CHECK2-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK2-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK2-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK2-51: .omp_outlined..19.exit: // CHECK2-51-NEXT: ret i32 0 @@ -5104,7 +5115,7 @@ void test_transparent() // // // CHECK2-51-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK2-51-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK2-51-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK2-51-NEXT: entry: // CHECK2-51-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-51-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -5177,17 +5188,17 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META123:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META126:![0-9]+]]) +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META125:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META128:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META130:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META132:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] -// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META132:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META134:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] // CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK2-51-NEXT: store i32 0, ptr [[TMP9]], align 4 // CHECK2-51-NEXT: ret i32 0 @@ -5219,7 +5230,7 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-51-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-51-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK2-51-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK2-51-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK2-51-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK2-51-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB1]], i32 [[TMP2]]) @@ -5229,12 +5240,12 @@ void test_transparent() // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_25]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK2-51-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 // CHECK2-51-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i64 48, i64 8, ptr @.omp_task_entry..28) -// CHECK2-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27:%.*]], ptr [[TMP6]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP7]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK2-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP9]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) -// CHECK2-51-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26]], ptr [[TMP6]], i32 0, i32 1 -// CHECK2-51-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_27:%.*]], ptr [[TMP10]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27]], ptr [[TMP6]], i32 0, i32 1 +// CHECK2-51-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_26:%.*]], ptr [[TMP10]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP12:%.*]] = load double, ptr [[B]], align 8 // CHECK2-51-NEXT: store double [[TMP12]], ptr [[TMP11]], align 8 // CHECK2-51-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP2]], ptr [[TMP6]]) @@ -5253,7 +5264,7 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_27:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_26:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK2-51-NEXT: ret void @@ -5275,28 +5286,28 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26]], ptr [[TMP3]], i32 0, i32 1 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META133:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META136:![0-9]+]]) +// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27]], ptr [[TMP3]], i32 0, i32 1 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META135:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META138:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META140:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META142:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META142]] -// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META142]] -// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..27, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META142]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META142]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META142]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META142]] -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META142]] -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META142]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META142:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META144:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META144]] +// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META144]] +// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..27, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META144]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META144]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META144]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META144]] +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META144]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META144]] // CHECK2-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META142]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META144]] // CHECK2-51-NEXT: [[TMP13:%.*]] = load double, ptr [[TMP12]], align 8 -// CHECK2-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK2-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK2-51-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP14]], align 4 // CHECK2-51-NEXT: [[CONV_I:%.*]] = fpext float [[TMP15]] to double // CHECK2-51-NEXT: [[ADD_I:%.*]] = fadd double [[CONV_I]], [[TMP13]] @@ -5314,29 +5325,29 @@ void test_transparent() // CHECK2-51-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK2-51-NEXT: [[E:%.*]] = alloca i32, align 4 // CHECK2-51-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_28:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED1:%.*]] = alloca [[STRUCT_ANON_31:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR2:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR2:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR3:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED4:%.*]] = alloca [[STRUCT_ANON_34:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR5:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR6:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED7:%.*]] = alloca [[STRUCT_ANON_37:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR8:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR8:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR9:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[AGG_CAPTURED10:%.*]] = alloca [[STRUCT_ANON_40:%.*]], align 1 -// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK2-51-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [1 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK2-51-NEXT: [[DEP_COUNTER_ADDR12:%.*]] = alloca i64, align 8 // CHECK2-51-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK2-51-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..31) -// CHECK2-51-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29:%.*]], ptr [[TMP1]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29]], ptr [[TMP1]], i32 0, i32 1 -// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_30:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30]], ptr [[TMP1]], i32 0, i32 1 +// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_29:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-51-NEXT: store i32 [[TMP5]], ptr [[TMP4]], align 8 -// CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK2-51-NEXT: [[TMP7:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP6]], i64 0 +// CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP7:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP6]], i64 0 // CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP7]], i32 0, i32 0 // CHECK2-51-NEXT: store i64 0, ptr [[TMP8]], align 8 // CHECK2-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP7]], i32 0, i32 1 @@ -5354,12 +5365,12 @@ void test_transparent() // CHECK2-51-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR]], align 8 // CHECK2-51-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP1]], i32 2, ptr [[TMP6]], i32 0, ptr null) // CHECK2-51-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..34) -// CHECK2-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32:%.*]], ptr [[TMP17]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32]], ptr [[TMP17]], i32 0, i32 1 -// CHECK2-51-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_33:%.*]], ptr [[TMP19]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33:%.*]], ptr [[TMP17]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33]], ptr [[TMP17]], i32 0, i32 1 +// CHECK2-51-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_32:%.*]], ptr [[TMP19]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP21:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-51-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 8 -// CHECK2-51-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR2]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR2]], i64 0, i64 0 // CHECK2-51-NEXT: [[TMP23:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP22]], i64 0 // CHECK2-51-NEXT: [[TMP24:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP23]], i32 0, i32 0 // CHECK2-51-NEXT: store i64 0, ptr [[TMP24]], align 8 @@ -5378,12 +5389,12 @@ void test_transparent() // CHECK2-51-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR3]], align 8 // CHECK2-51-NEXT: [[TMP32:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP17]], i32 2, ptr [[TMP22]], i32 0, ptr null) // CHECK2-51-NEXT: [[TMP33:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..37) -// CHECK2-51-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35:%.*]], ptr [[TMP33]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35]], ptr [[TMP33]], i32 0, i32 1 -// CHECK2-51-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_36:%.*]], ptr [[TMP35]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36:%.*]], ptr [[TMP33]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36]], ptr [[TMP33]], i32 0, i32 1 +// CHECK2-51-NEXT: [[TMP36:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_35:%.*]], ptr [[TMP35]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP37:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-51-NEXT: store i32 [[TMP37]], ptr [[TMP36]], align 8 -// CHECK2-51-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 // CHECK2-51-NEXT: [[TMP39:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP38]], i64 0 // CHECK2-51-NEXT: [[TMP40:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP39]], i32 0, i32 0 // CHECK2-51-NEXT: store i64 0, ptr [[TMP40]], align 8 @@ -5402,12 +5413,12 @@ void test_transparent() // CHECK2-51-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR6]], align 8 // CHECK2-51-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP33]], i32 2, ptr [[TMP38]], i32 0, ptr null) // CHECK2-51-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..40) -// CHECK2-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38:%.*]], ptr [[TMP49]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38]], ptr [[TMP49]], i32 0, i32 1 -// CHECK2-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_39:%.*]], ptr [[TMP51]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39:%.*]], ptr [[TMP49]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39]], ptr [[TMP49]], i32 0, i32 1 +// CHECK2-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_38:%.*]], ptr [[TMP51]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP53:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-51-NEXT: store i32 [[TMP53]], ptr [[TMP52]], align 8 -// CHECK2-51-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR8]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR8]], i64 0, i64 0 // CHECK2-51-NEXT: [[TMP55:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i64 0 // CHECK2-51-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP55]], i32 0, i32 0 // CHECK2-51-NEXT: store i64 0, ptr [[TMP56]], align 8 @@ -5426,12 +5437,12 @@ void test_transparent() // CHECK2-51-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR9]], align 8 // CHECK2-51-NEXT: [[TMP64:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP49]], i32 2, ptr [[TMP54]], i32 0, ptr null) // CHECK2-51-NEXT: [[TMP65:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..43) -// CHECK2-51-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_41:%.*]], ptr [[TMP65]], i32 0, i32 0 -// CHECK2-51-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_41]], ptr [[TMP65]], i32 0, i32 1 -// CHECK2-51-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_42:%.*]], ptr [[TMP67]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42:%.*]], ptr [[TMP65]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42]], ptr [[TMP65]], i32 0, i32 1 +// CHECK2-51-NEXT: [[TMP68:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_41:%.*]], ptr [[TMP67]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP69:%.*]] = load i32, ptr [[A]], align 4 // CHECK2-51-NEXT: store i32 [[TMP69]], ptr [[TMP68]], align 8 -// CHECK2-51-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 +// CHECK2-51-NEXT: [[TMP70:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 // CHECK2-51-NEXT: [[TMP71:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP70]], i64 0 // CHECK2-51-NEXT: [[TMP72:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP71]], i32 0, i32 0 // CHECK2-51-NEXT: store i64 0, ptr [[TMP72]], align 8 @@ -5452,7 +5463,7 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_30:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_29:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK2-51-NEXT: ret void @@ -5474,26 +5485,26 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29]], ptr [[TMP3]], i32 0, i32 1 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META145:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META148:![0-9]+]]) +// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30]], ptr [[TMP3]], i32 0, i32 1 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META147:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META150:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META152:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META154:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META154]] -// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META154]] -// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..30, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META154]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META154]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META154]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META154]] -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META154]] -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META154]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META154:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META156:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META156]] +// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META156]] +// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..30, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META156]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META156]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META156]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META156]] +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META156]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META156]] // CHECK2-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META154]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META156]] // CHECK2-51-NEXT: store i32 13, ptr [[TMP12]], align 4 // CHECK2-51-NEXT: ret i32 0 // @@ -5506,7 +5517,7 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_33:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_32:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK2-51-NEXT: ret void @@ -5528,26 +5539,26 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32]], ptr [[TMP3]], i32 0, i32 1 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META155:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META158:![0-9]+]]) +// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33]], ptr [[TMP3]], i32 0, i32 1 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META157:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META160:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META162:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META164:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META164]] -// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META164]] -// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..33, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META164]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META164]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META164]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META164]] -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META164]] -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META164]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META164:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META166:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META166]] +// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META166]] +// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..33, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META166]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META166]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META166]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META166]] +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META166]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META166]] // CHECK2-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META164]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META166]] // CHECK2-51-NEXT: store i32 14, ptr [[TMP12]], align 4 // CHECK2-51-NEXT: ret i32 0 // @@ -5560,7 +5571,7 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_36:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_35:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK2-51-NEXT: ret void @@ -5582,26 +5593,26 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35]], ptr [[TMP3]], i32 0, i32 1 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META165:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META168:![0-9]+]]) +// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36]], ptr [[TMP3]], i32 0, i32 1 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META167:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META170:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META172:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META174:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META174]] -// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META174]] -// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..36, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META174]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META174]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META174]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META174]] -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META174]] -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META174]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META174:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META176:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META176]] +// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META176]] +// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..36, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META176]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META176]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META176]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META176]] +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META176]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META176]] // CHECK2-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META174]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META176]] // CHECK2-51-NEXT: store i32 15, ptr [[TMP12]], align 4 // CHECK2-51-NEXT: ret i32 0 // @@ -5614,7 +5625,7 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_39:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_38:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK2-51-NEXT: ret void @@ -5636,26 +5647,26 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38]], ptr [[TMP3]], i32 0, i32 1 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META175:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META178:![0-9]+]]) +// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39]], ptr [[TMP3]], i32 0, i32 1 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META177:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META180:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META182:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META184:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META184]] -// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META184]] -// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..39, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META184]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META184]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META184]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META184]] -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META184]] -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META184]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META184:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META186:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META186]] +// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META186]] +// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..39, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META186]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META186]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META186]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META186]] +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META186]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META186]] // CHECK2-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META184]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META186]] // CHECK2-51-NEXT: store i32 16, ptr [[TMP12]], align 4 // CHECK2-51-NEXT: ret i32 0 // @@ -5668,7 +5679,7 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_42:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_41:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK2-51-NEXT: ret void @@ -5690,26 +5701,26 @@ void test_transparent() // CHECK2-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK2-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK2-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_41:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK2-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK2-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_41]], ptr [[TMP3]], i32 0, i32 1 -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META185:![0-9]+]]) -// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META188:![0-9]+]]) +// CHECK2-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42]], ptr [[TMP3]], i32 0, i32 1 +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META187:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META190:![0-9]+]]) // CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META192:![0-9]+]]) -// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META194:![0-9]+]] -// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META194]] -// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META194]] -// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..42, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META194]] -// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META194]] -// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META194]] -// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META194]] -// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META194]] -// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META194]] +// CHECK2-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META194:![0-9]+]]) +// CHECK2-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META196:![0-9]+]] +// CHECK2-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META196]] +// CHECK2-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META196]] +// CHECK2-51-NEXT: store ptr @.omp_task_privates_map..42, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META196]] +// CHECK2-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META196]] +// CHECK2-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META196]] +// CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META196]] +// CHECK2-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META196]] +// CHECK2-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META196]] // CHECK2-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META194]] +// CHECK2-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META196]] // CHECK2-51-NEXT: store i32 17, ptr [[TMP12]], align 4 // CHECK2-51-NEXT: ret i32 0 // @@ -5726,22 +5737,22 @@ void test_transparent() // CHECK3-NEXT: entry: // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK3-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK3-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 -// CHECK3-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x %struct.kmp_depend_info], align 8 +// CHECK3-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK3-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[AGG_CAPTURED6:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 // CHECK3-NEXT: [[AGG_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK3-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK3-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[AGG_CAPTURED19:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK3-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK3-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[AGG_CAPTURED29:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK3-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK3-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-NEXT: [[DEP_COUNTER_ADDR37:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[AGG_CAPTURED39:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 // CHECK3-NEXT: [[FLAG:%.*]] = alloca i8, align 1 @@ -5750,8 +5761,8 @@ void test_transparent() // CHECK3-NEXT: [[AGG_CAPTURED45:%.*]] = alloca [[STRUCT_ANON_14:%.*]], align 8 // CHECK3-NEXT: [[AGG_CAPTURED48:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -5791,8 +5802,8 @@ void test_transparent() // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP15]], i32 0, i32 0 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP17]], ptr align 8 [[AGG_CAPTURED2]], i64 8, i1 false) -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP18]], i64 0 +// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP18]], i64 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 0 // CHECK3-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP20]], align 8 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 1 @@ -5844,8 +5855,8 @@ void test_transparent() // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) // CHECK3-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 -// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 +// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK3-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 @@ -5884,8 +5895,8 @@ void test_transparent() // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11:[0-9]+]]) // CHECK3-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 -// CHECK3-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK3-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK3-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 // CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 @@ -5924,7 +5935,7 @@ void test_transparent() // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]) // CHECK3-NEXT: [[TMP99:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP99]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 +// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 0 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 0 // CHECK3-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP103]], align 8 @@ -5932,7 +5943,7 @@ void test_transparent() // CHECK3-NEXT: store i64 4, ptr [[TMP104]], align 8 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 // CHECK3-NEXT: store i8 3, ptr [[TMP105]], align 8 -// CHECK3-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK3-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK3-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 @@ -5995,9 +6006,9 @@ void test_transparent() // CHECK3-NEXT: [[TMP141:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM47]], ptr [[TMP137]]) // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21:[0-9]+]]) // CHECK3-NEXT: [[TMP142:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM49]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..21) -// CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP142]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP142]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP144]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP142]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP142]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP144]], i32 0, i32 0 // CHECK3-NEXT: [[TMP146:%.*]] = load i32, ptr [[C]], align 128 // CHECK3-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) @@ -6008,13 +6019,13 @@ void test_transparent() // CHECK3-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP150]]) -// CHECK3-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 // CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done52: @@ -6065,10 +6076,10 @@ void test_transparent() // CHECK3-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] // CHECK3-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] // CHECK3-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] // CHECK3-NEXT: store i32 10, ptr [[TMP12]], align 4 // CHECK3-NEXT: ret i32 0 // @@ -6092,20 +6103,20 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-NEXT: store i32 15, ptr @a, align 4, !noalias [[META22]] -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK3-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK3-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 // CHECK3-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK3-NEXT: ret i32 0 // @@ -6130,42 +6141,42 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK3-NEXT: ] // CHECK3: .untied.done..i: -// CHECK3-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK3-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK3-NEXT: br label [[CLEANUP_I:%.*]] // CHECK3: .untied.jmp..i: -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK3-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]]) -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] // CHECK3: .untied.jmp.1.i: // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK3-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) -// CHECK3-NEXT: store i32 1, ptr @a, align 4, !noalias [[META32]] +// CHECK3-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] // CHECK3-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) -// CHECK3-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK3-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK3-NEXT: br label [[CLEANUP_I]] // CHECK3: cleanup.i: -// CHECK3-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK3-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] // CHECK3: .omp_outlined..3.exit: // CHECK3-NEXT: ret i32 0 @@ -6191,39 +6202,39 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK3-NEXT: ] // CHECK3: .untied.done..i: -// CHECK3-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK3-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK3-NEXT: br label [[CLEANUP_I:%.*]] // CHECK3: .untied.jmp..i: -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK3-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9]]) -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] // CHECK3: .untied.jmp.1.i: -// CHECK3-NEXT: store i32 1, ptr @a, align 4, !noalias [[META42]] -// CHECK3-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK3-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK3-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK3-NEXT: br label [[CLEANUP_I]] // CHECK3: cleanup.i: -// CHECK3-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK3-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] // CHECK3: .omp_outlined..5.exit: // CHECK3-NEXT: ret i32 0 @@ -6249,39 +6260,39 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK3-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK3-NEXT: ] // CHECK3: .untied.done..i: -// CHECK3-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK3-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK3-NEXT: br label [[CLEANUP_I:%.*]] // CHECK3: .untied.jmp..i: -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK3-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11]]) -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] // CHECK3: .untied.jmp.1.i: -// CHECK3-NEXT: store i32 1, ptr @a, align 4, !noalias [[META52]] -// CHECK3-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK3-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK3-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK3-NEXT: br label [[CLEANUP_I]] // CHECK3: cleanup.i: -// CHECK3-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK3-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] // CHECK3: .omp_outlined..7.exit: // CHECK3-NEXT: ret i32 0 @@ -6306,18 +6317,18 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-NEXT: store i32 2, ptr @a, align 4, !noalias [[META62]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] // CHECK3-NEXT: ret i32 0 // // @@ -6340,18 +6351,18 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META72:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-NEXT: store i32 2, ptr @a, align 4, !noalias [[META72]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] // CHECK3-NEXT: ret i32 0 // // @@ -6374,18 +6385,18 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META82:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-NEXT: store i32 3, ptr @a, align 4, !noalias [[META82]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-NEXT: store i32 3, ptr @a, align 4, !noalias [[META84]] // CHECK3-NEXT: ret i32 0 // // @@ -6408,19 +6419,19 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META92:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-NEXT: store i32 4, ptr @a, align 4, !noalias [[META92]] -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-NEXT: store i32 4, ptr @a, align 4, !noalias [[META94]] +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK3-NEXT: store i32 5, ptr [[TMP9]], align 128 // CHECK3-NEXT: ret i32 0 // @@ -6460,33 +6471,33 @@ void test_transparent() // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], ptr [[TMP3]], i32 0, i32 2 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META102:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] // CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META102]] +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META104]] // CHECK3-NEXT: store i32 4, ptr [[TMP12]], align 128 -// CHECK3-NEXT: store i32 4, ptr @a, align 4, !noalias [[META102]] +// CHECK3-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] // CHECK3-NEXT: ret i32 0 // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK3-NEXT: ret void // // @@ -6502,13 +6513,13 @@ void test_transparent() // CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 -// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 1 +// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 1 // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 -// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 2 +// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 // CHECK3-NEXT: ret void @@ -6536,29 +6547,29 @@ void test_transparent() // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP3]], i32 0, i32 2 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]]) +// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META112]] -// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META114]] +// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK3-NEXT: switch i32 [[TMP16]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK3-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] @@ -6568,19 +6579,19 @@ void test_transparent() // CHECK3-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]] // CHECK3-NEXT: ] // CHECK3: .untied.done..i: -// CHECK3-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK3-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK3-NEXT: br label [[CLEANUP_I:%.*]] // CHECK3: .untied.jmp..i: -// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: store i32 1, ptr [[TMP17]], align 4 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP18]]) // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK3: .untied.jmp.2.i: // CHECK3-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) // CHECK3-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) -// CHECK3-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META112]] +// CHECK3-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META114]] // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23:[0-9]+]]) // CHECK3-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..19) // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.*]], ptr [[TMP20]], i32 0, i32 2 @@ -6588,41 +6599,41 @@ void test_transparent() // CHECK3-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 128 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) // CHECK3-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], ptr [[TMP20]]) -// CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: store i32 2, ptr [[TMP24]], align 4 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], ptr [[TMP25]]) // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK3: .untied.jmp.6.i: // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) -// CHECK3-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: store i32 3, ptr [[TMP28]], align 4 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK3-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], ptr [[TMP29]]) // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK3: .untied.jmp.10.i: // CHECK3-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) -// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META112]] -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] -// CHECK3-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META112]] +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META114]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK3-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META114]] // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) -// CHECK3-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: store i32 4, ptr [[TMP32]], align 4 // CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], ptr [[TMP33]]) // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK3: .untied.jmp.15.i: -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]] -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]] -// CHECK3-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S2_I]]) #[[ATTR4]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S1_I]]) #[[ATTR4]] +// CHECK3-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK3-NEXT: br label [[CLEANUP_I]] // CHECK3: cleanup.i: -// CHECK3-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK3-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK3: .omp_outlined..17.exit: // CHECK3-NEXT: ret i32 0 @@ -6640,7 +6651,7 @@ void test_transparent() // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -6714,17 +6725,17 @@ void test_transparent() // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]]) -// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]]) +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122:![0-9]+]] -// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK3-NEXT: store i32 0, ptr [[TMP9]], align 4 // CHECK3-NEXT: ret i32 0 @@ -6742,22 +6753,22 @@ void test_transparent() // CHECK4-NEXT: entry: // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK4-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK4-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK4-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 -// CHECK4-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x %struct.kmp_depend_info], align 8 +// CHECK4-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK4-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[AGG_CAPTURED6:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 // CHECK4-NEXT: [[AGG_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK4-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK4-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK4-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[AGG_CAPTURED19:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK4-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK4-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK4-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[AGG_CAPTURED29:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK4-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK4-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK4-NEXT: [[DEP_COUNTER_ADDR37:%.*]] = alloca i64, align 8 // CHECK4-NEXT: [[AGG_CAPTURED39:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 // CHECK4-NEXT: [[FLAG:%.*]] = alloca i8, align 1 @@ -6766,8 +6777,8 @@ void test_transparent() // CHECK4-NEXT: [[AGG_CAPTURED45:%.*]] = alloca [[STRUCT_ANON_14:%.*]], align 8 // CHECK4-NEXT: [[AGG_CAPTURED48:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 // CHECK4-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 -// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK4-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK4-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK4-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4: arrayctor.loop: // CHECK4-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -6807,8 +6818,8 @@ void test_transparent() // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP15]], i32 0, i32 0 // CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 // CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP17]], ptr align 8 [[AGG_CAPTURED2]], i64 8, i1 false) -// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP18]], i64 0 +// CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP18]], i64 0 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 0 // CHECK4-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP20]], align 8 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 1 @@ -6860,8 +6871,8 @@ void test_transparent() // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) // CHECK4-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK4-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 -// CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 +// CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK4-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 // CHECK4-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 @@ -6900,8 +6911,8 @@ void test_transparent() // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11:[0-9]+]]) // CHECK4-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 -// CHECK4-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK4-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK4-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK4-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 // CHECK4-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 @@ -6940,7 +6951,7 @@ void test_transparent() // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]) // CHECK4-NEXT: [[TMP99:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) // CHECK4-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP99]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 +// CHECK4-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 // CHECK4-NEXT: [[TMP102:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 0 // CHECK4-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 0 // CHECK4-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP103]], align 8 @@ -6948,7 +6959,7 @@ void test_transparent() // CHECK4-NEXT: store i64 4, ptr [[TMP104]], align 8 // CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 // CHECK4-NEXT: store i8 3, ptr [[TMP105]], align 8 -// CHECK4-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK4-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK4-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 // CHECK4-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 // CHECK4-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 @@ -7011,9 +7022,9 @@ void test_transparent() // CHECK4-NEXT: [[TMP141:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM47]], ptr [[TMP137]]) // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21:[0-9]+]]) // CHECK4-NEXT: [[TMP142:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM49]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..21) -// CHECK4-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP142]], i32 0, i32 0 -// CHECK4-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP142]], i32 0, i32 2 -// CHECK4-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP144]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP142]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP142]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP144]], i32 0, i32 0 // CHECK4-NEXT: [[TMP146:%.*]] = load i32, ptr [[C]], align 128 // CHECK4-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) @@ -7024,13 +7035,13 @@ void test_transparent() // CHECK4-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4 // CHECK4-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK4-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP150]]) -// CHECK4-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 +// CHECK4-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 // CHECK4-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2 // CHECK4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4: arraydestroy.body: // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4: arraydestroy.done52: @@ -7081,10 +7092,10 @@ void test_transparent() // CHECK4-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] // CHECK4-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] // CHECK4-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] // CHECK4-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] // CHECK4-NEXT: store i32 10, ptr [[TMP12]], align 4 // CHECK4-NEXT: ret i32 0 // @@ -7108,20 +7119,20 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-NEXT: store i32 15, ptr @a, align 4, !noalias [[META22]] -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK4-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK4-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 // CHECK4-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK4-NEXT: ret i32 0 // @@ -7146,42 +7157,42 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK4-NEXT: ] // CHECK4: .untied.done..i: -// CHECK4-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK4-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK4-NEXT: br label [[CLEANUP_I:%.*]] // CHECK4: .untied.jmp..i: -// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK4-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]]) -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] // CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] // CHECK4: .untied.jmp.1.i: // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK4-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) -// CHECK4-NEXT: store i32 1, ptr @a, align 4, !noalias [[META32]] +// CHECK4-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] // CHECK4-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) -// CHECK4-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK4-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK4-NEXT: br label [[CLEANUP_I]] // CHECK4: cleanup.i: -// CHECK4-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK4-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] // CHECK4: .omp_outlined..3.exit: // CHECK4-NEXT: ret i32 0 @@ -7207,39 +7218,39 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK4-NEXT: ] // CHECK4: .untied.done..i: -// CHECK4-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK4-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK4-NEXT: br label [[CLEANUP_I:%.*]] // CHECK4: .untied.jmp..i: -// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK4-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9]]) -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] // CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] // CHECK4: .untied.jmp.1.i: -// CHECK4-NEXT: store i32 1, ptr @a, align 4, !noalias [[META42]] -// CHECK4-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK4-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK4-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK4-NEXT: br label [[CLEANUP_I]] // CHECK4: cleanup.i: -// CHECK4-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK4-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] // CHECK4: .omp_outlined..5.exit: // CHECK4-NEXT: ret i32 0 @@ -7265,39 +7276,39 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK4-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK4-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK4-NEXT: ] // CHECK4: .untied.done..i: -// CHECK4-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK4-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK4-NEXT: br label [[CLEANUP_I:%.*]] // CHECK4: .untied.jmp..i: -// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK4-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11]]) -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] // CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] // CHECK4: .untied.jmp.1.i: -// CHECK4-NEXT: store i32 1, ptr @a, align 4, !noalias [[META52]] -// CHECK4-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK4-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK4-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK4-NEXT: br label [[CLEANUP_I]] // CHECK4: cleanup.i: -// CHECK4-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK4-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] // CHECK4: .omp_outlined..7.exit: // CHECK4-NEXT: ret i32 0 @@ -7322,18 +7333,18 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-NEXT: store i32 2, ptr @a, align 4, !noalias [[META62]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] // CHECK4-NEXT: ret i32 0 // // @@ -7356,18 +7367,18 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META72:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-NEXT: store i32 2, ptr @a, align 4, !noalias [[META72]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] // CHECK4-NEXT: ret i32 0 // // @@ -7390,18 +7401,18 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META82:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-NEXT: store i32 3, ptr @a, align 4, !noalias [[META82]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-NEXT: store i32 3, ptr @a, align 4, !noalias [[META84]] // CHECK4-NEXT: ret i32 0 // // @@ -7424,19 +7435,19 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META92:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-NEXT: store i32 4, ptr @a, align 4, !noalias [[META92]] -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-NEXT: store i32 4, ptr @a, align 4, !noalias [[META94]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK4-NEXT: store i32 5, ptr [[TMP9]], align 128 // CHECK4-NEXT: ret i32 0 // @@ -7476,33 +7487,33 @@ void test_transparent() // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], ptr [[TMP3]], i32 0, i32 2 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META102:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] // CHECK4-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META102]] +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META104]] // CHECK4-NEXT: store i32 4, ptr [[TMP12]], align 128 -// CHECK4-NEXT: store i32 4, ptr @a, align 4, !noalias [[META102]] +// CHECK4-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] // CHECK4-NEXT: ret i32 0 // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK4-NEXT: ret void // // @@ -7518,13 +7529,13 @@ void test_transparent() // CHECK4-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 // CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK4-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 -// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 1 +// CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 1 // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK4-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 -// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 2 +// CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK4-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 // CHECK4-NEXT: ret void @@ -7552,29 +7563,29 @@ void test_transparent() // CHECK4-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK4-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP3]], i32 0, i32 2 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]]) +// CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] -// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META112]] -// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META114]] +// CHECK4-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK4-NEXT: switch i32 [[TMP16]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK4-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] @@ -7584,19 +7595,19 @@ void test_transparent() // CHECK4-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]] // CHECK4-NEXT: ] // CHECK4: .untied.done..i: -// CHECK4-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK4-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK4-NEXT: br label [[CLEANUP_I:%.*]] // CHECK4: .untied.jmp..i: -// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: store i32 1, ptr [[TMP17]], align 4 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP18]]) // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK4: .untied.jmp.2.i: // CHECK4-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) // CHECK4-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) -// CHECK4-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META112]] +// CHECK4-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META114]] // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23:[0-9]+]]) // CHECK4-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..19) // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.*]], ptr [[TMP20]], i32 0, i32 2 @@ -7604,41 +7615,41 @@ void test_transparent() // CHECK4-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 128 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) // CHECK4-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], ptr [[TMP20]]) -// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: store i32 2, ptr [[TMP24]], align 4 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], ptr [[TMP25]]) // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4: .untied.jmp.6.i: // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK4-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) -// CHECK4-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: store i32 3, ptr [[TMP28]], align 4 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK4-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], ptr [[TMP29]]) // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4: .untied.jmp.10.i: // CHECK4-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) -// CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META112]] -// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] -// CHECK4-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META112]] +// CHECK4-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META114]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK4-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META114]] // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK4-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) -// CHECK4-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: store i32 4, ptr [[TMP32]], align 4 // CHECK4-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK4-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-NEXT: [[TMP34:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], ptr [[TMP33]]) // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4: .untied.jmp.15.i: -// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]] -// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]] -// CHECK4-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S2_I]]) #[[ATTR4]] +// CHECK4-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S1_I]]) #[[ATTR4]] +// CHECK4-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK4-NEXT: br label [[CLEANUP_I]] // CHECK4: cleanup.i: -// CHECK4-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK4-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4: .omp_outlined..17.exit: // CHECK4-NEXT: ret i32 0 @@ -7656,7 +7667,7 @@ void test_transparent() // // // CHECK4-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-NEXT: entry: // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -7730,17 +7741,17 @@ void test_transparent() // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]]) -// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]]) +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) -// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122:![0-9]+]] -// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] +// CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK4-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK4-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] // CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK4-NEXT: store i32 0, ptr [[TMP9]], align 4 // CHECK4-NEXT: ret i32 0 @@ -7758,25 +7769,25 @@ void test_transparent() // CHECK3-51-NEXT: entry: // CHECK3-51-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK3-51-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK3-51-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-51-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-51-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK3-51-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED6:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 // CHECK3-51-NEXT: [[AGG_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED19:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED29:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR37:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED39:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR41:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR41:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR49:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED51:%.*]] = alloca [[STRUCT_ANON_12:%.*]], align 1 // CHECK3-51-NEXT: [[FLAG:%.*]] = alloca i8, align 1 @@ -7785,8 +7796,8 @@ void test_transparent() // CHECK3-51-NEXT: [[AGG_CAPTURED57:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED60:%.*]] = alloca [[STRUCT_ANON_18:%.*]], align 1 // CHECK3-51-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-51-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 -// CHECK3-51-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK3-51-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK3-51-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK3-51-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3-51: arrayctor.loop: // CHECK3-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -7826,8 +7837,8 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP15]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 // CHECK3-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP17]], ptr align 8 [[AGG_CAPTURED2]], i64 8, i1 false) -// CHECK3-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK3-51-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP18]], i64 0 +// CHECK3-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP18]], i64 0 // CHECK3-51-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 0 // CHECK3-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP20]], align 8 // CHECK3-51-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 1 @@ -7879,8 +7890,8 @@ void test_transparent() // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) // CHECK3-51-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK3-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 -// CHECK3-51-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 +// CHECK3-51-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK3-51-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 // CHECK3-51-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 // CHECK3-51-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 @@ -7919,8 +7930,8 @@ void test_transparent() // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11:[0-9]+]]) // CHECK3-51-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK3-51-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 -// CHECK3-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK3-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK3-51-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK3-51-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 // CHECK3-51-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 @@ -7959,7 +7970,7 @@ void test_transparent() // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]) // CHECK3-51-NEXT: [[TMP99:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) // CHECK3-51-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP99]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 // CHECK3-51-NEXT: [[TMP102:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 0 // CHECK3-51-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 0 // CHECK3-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP103]], align 8 @@ -7967,7 +7978,7 @@ void test_transparent() // CHECK3-51-NEXT: store i64 4, ptr [[TMP104]], align 8 // CHECK3-51-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 // CHECK3-51-NEXT: store i8 3, ptr [[TMP105]], align 8 -// CHECK3-51-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK3-51-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK3-51-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 // CHECK3-51-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 // CHECK3-51-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 @@ -8006,7 +8017,7 @@ void test_transparent() // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM40:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB15:[0-9]+]]) // CHECK3-51-NEXT: [[TMP127:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM40]], i32 1, i64 40, i64 1, ptr @.omp_task_entry..12) // CHECK3-51-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], ptr [[TMP127]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP129:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR41]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP129:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR41]], i64 0, i64 0 // CHECK3-51-NEXT: [[TMP130:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP129]], i64 0 // CHECK3-51-NEXT: [[TMP131:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP130]], i32 0, i32 0 // CHECK3-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP131]], align 8 @@ -8014,7 +8025,7 @@ void test_transparent() // CHECK3-51-NEXT: store i64 4, ptr [[TMP132]], align 8 // CHECK3-51-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP130]], i32 0, i32 2 // CHECK3-51-NEXT: store i8 8, ptr [[TMP133]], align 8 -// CHECK3-51-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK3-51-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK3-51-NEXT: [[TMP134:%.*]] = ptrtoint ptr [[ARRAYIDX42]] to i64 // CHECK3-51-NEXT: [[TMP135:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP129]], i64 1 // CHECK3-51-NEXT: [[TMP136:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP135]], i32 0, i32 0 @@ -8077,9 +8088,9 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP169:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM59]], ptr [[TMP165]]) // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM61:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23:[0-9]+]]) // CHECK3-51-NEXT: [[TMP170:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM61]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..23) -// CHECK3-51-NEXT: [[TMP171:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21:%.*]], ptr [[TMP170]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP172:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21]], ptr [[TMP170]], i32 0, i32 2 -// CHECK3-51-NEXT: [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22:%.*]], ptr [[TMP172]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP171:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.*]], ptr [[TMP170]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP172:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22]], ptr [[TMP170]], i32 0, i32 2 +// CHECK3-51-NEXT: [[TMP173:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21:%.*]], ptr [[TMP172]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP174:%.*]] = load i32, ptr [[C]], align 128 // CHECK3-51-NEXT: store i32 [[TMP174]], ptr [[TMP173]], align 128 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM62:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) @@ -8090,13 +8101,13 @@ void test_transparent() // CHECK3-51-NEXT: store i32 [[TMP177]], ptr [[RETVAL]], align 4 // CHECK3-51-NEXT: [[TMP178:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-51-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP178]]) -// CHECK3-51-NEXT: [[ARRAY_BEGIN63:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 +// CHECK3-51-NEXT: [[ARRAY_BEGIN63:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP179:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN63]], i64 2 // CHECK3-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3-51: arraydestroy.body: // CHECK3-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP179]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK3-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN63]] // CHECK3-51-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE64:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3-51: arraydestroy.done64: @@ -8147,10 +8158,10 @@ void test_transparent() // CHECK3-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] // CHECK3-51-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] // CHECK3-51-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 -// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] // CHECK3-51-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 // CHECK3-51-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] // CHECK3-51-NEXT: store i32 10, ptr [[TMP12]], align 4 // CHECK3-51-NEXT: ret i32 0 // @@ -8174,20 +8185,20 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK3-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META22]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK3-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK3-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK3-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 // CHECK3-51-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK3-51-NEXT: ret i32 0 // @@ -8212,42 +8223,42 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK3-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK3-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK3-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK3-51-NEXT: ] // CHECK3-51: .untied.done..i: -// CHECK3-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK3-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK3-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK3-51: .untied.jmp..i: -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK3-51-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]]) -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] // CHECK3-51-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] // CHECK3-51: .untied.jmp.1.i: // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK3-51-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) -// CHECK3-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META32]] +// CHECK3-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] // CHECK3-51-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) -// CHECK3-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK3-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK3-51-NEXT: br label [[CLEANUP_I]] // CHECK3-51: cleanup.i: -// CHECK3-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK3-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] // CHECK3-51: .omp_outlined..3.exit: // CHECK3-51-NEXT: ret i32 0 @@ -8273,39 +8284,39 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK3-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK3-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK3-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK3-51-NEXT: ] // CHECK3-51: .untied.done..i: -// CHECK3-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK3-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK3-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK3-51: .untied.jmp..i: -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK3-51-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9]]) -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] // CHECK3-51-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] // CHECK3-51: .untied.jmp.1.i: -// CHECK3-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META42]] -// CHECK3-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK3-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK3-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK3-51-NEXT: br label [[CLEANUP_I]] // CHECK3-51: cleanup.i: -// CHECK3-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK3-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] // CHECK3-51: .omp_outlined..5.exit: // CHECK3-51-NEXT: ret i32 0 @@ -8331,39 +8342,39 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK3-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK3-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK3-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK3-51-NEXT: ] // CHECK3-51: .untied.done..i: -// CHECK3-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK3-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK3-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK3-51: .untied.jmp..i: -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK3-51-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11]]) -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] // CHECK3-51-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] // CHECK3-51: .untied.jmp.1.i: -// CHECK3-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META52]] -// CHECK3-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK3-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK3-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK3-51-NEXT: br label [[CLEANUP_I]] // CHECK3-51: cleanup.i: -// CHECK3-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK3-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] // CHECK3-51: .omp_outlined..7.exit: // CHECK3-51-NEXT: ret i32 0 @@ -8388,18 +8399,18 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK3-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META62]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK3-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] // CHECK3-51-NEXT: ret i32 0 // // @@ -8422,18 +8433,18 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META72:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK3-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META72]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK3-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] // CHECK3-51-NEXT: ret i32 0 // // @@ -8456,18 +8467,18 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META82:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK3-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META82]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK3-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META84]] // CHECK3-51-NEXT: ret i32 0 // // @@ -8490,18 +8501,18 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META92:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK3-51-NEXT: store i32 3, ptr @a, align 4, !noalias [[META92]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK3-51-NEXT: store i32 3, ptr @a, align 4, !noalias [[META94]] // CHECK3-51-NEXT: ret i32 0 // // @@ -8524,19 +8535,19 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META102:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK3-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META102]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK3-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK3-51-NEXT: store i32 5, ptr [[TMP9]], align 128 // CHECK3-51-NEXT: ret i32 0 // @@ -8576,33 +8587,33 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 // CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-51-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-51-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] // CHECK3-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META112]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] // CHECK3-51-NEXT: store i32 4, ptr [[TMP12]], align 128 -// CHECK3-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META112]] +// CHECK3-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META114]] // CHECK3-51-NEXT: ret i32 0 // // // CHECK3-51-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-51-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-51-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-51-NEXT: entry: // CHECK3-51-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-51-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-51-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-51-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK3-51-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK3-51-NEXT: ret void // // @@ -8618,13 +8629,13 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 // CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK3-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22]], ptr [[TMP4]], i32 0, i32 1 +// CHECK3-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21]], ptr [[TMP4]], i32 0, i32 1 // CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 -// CHECK3-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_22]], ptr [[TMP4]], i32 0, i32 2 +// CHECK3-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_21]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK3-51-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 // CHECK3-51-NEXT: ret void @@ -8652,29 +8663,29 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK3-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_21]], ptr [[TMP3]], i32 0, i32 2 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]]) +// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22]], ptr [[TMP3]], i32 0, i32 2 +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..22, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..22, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META122]] -// CHECK3-51-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META124]] +// CHECK3-51-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK3-51-NEXT: switch i32 [[TMP16]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK3-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] @@ -8684,19 +8695,19 @@ void test_transparent() // CHECK3-51-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]] // CHECK3-51-NEXT: ] // CHECK3-51: .untied.done..i: -// CHECK3-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK3-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK3-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK3-51: .untied.jmp..i: -// CHECK3-51-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: store i32 1, ptr [[TMP17]], align 4 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) -// CHECK3-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP18]]) // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT:%.*]] // CHECK3-51: .untied.jmp.2.i: // CHECK3-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) // CHECK3-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) -// CHECK3-51-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META122]] +// CHECK3-51-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META124]] // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB25:[0-9]+]]) // CHECK3-51-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..21) // CHECK3-51-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP20]], i32 0, i32 2 @@ -8704,41 +8715,41 @@ void test_transparent() // CHECK3-51-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 128 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB25]]) // CHECK3-51-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], ptr [[TMP20]]) -// CHECK3-51-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: store i32 2, ptr [[TMP24]], align 4 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) -// CHECK3-51-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], ptr [[TMP25]]) // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK3-51: .untied.jmp.6.i: // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK3-51-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) -// CHECK3-51-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: store i32 3, ptr [[TMP28]], align 4 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) -// CHECK3-51-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], ptr [[TMP29]]) // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK3-51: .untied.jmp.10.i: // CHECK3-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) -// CHECK3-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META122]] -// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META122]] +// CHECK3-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META124]] +// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK3-51-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META124]] // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK3-51-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) -// CHECK3-51-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: store i32 4, ptr [[TMP32]], align 4 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) -// CHECK3-51-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] +// CHECK3-51-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] // CHECK3-51-NEXT: [[TMP34:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], ptr [[TMP33]]) // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK3-51: .untied.jmp.15.i: -// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S2_I]]) #[[ATTR4]] +// CHECK3-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S1_I]]) #[[ATTR4]] +// CHECK3-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK3-51-NEXT: br label [[CLEANUP_I]] // CHECK3-51: cleanup.i: -// CHECK3-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META122]] +// CHECK3-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META124]] // CHECK3-51-NEXT: br label [[DOTOMP_OUTLINED__19_EXIT]] // CHECK3-51: .omp_outlined..19.exit: // CHECK3-51-NEXT: ret i32 0 @@ -8756,7 +8767,7 @@ void test_transparent() // // // CHECK3-51-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-51-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-51-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-51-NEXT: entry: // CHECK3-51-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-51-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -8830,17 +8841,17 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META123:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META126:![0-9]+]]) +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META125:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META128:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META130:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META132:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META132]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META132]] -// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META132]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META132]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] -// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META132]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META132:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META134:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META134]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META134]] +// CHECK3-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META134]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META134]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] // CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK3-51-NEXT: store i32 0, ptr [[TMP9]], align 4 // CHECK3-51-NEXT: ret i32 0 @@ -8855,29 +8866,29 @@ void test_transparent() // CHECK3-51-NEXT: [[D:%.*]] = alloca i32, align 4 // CHECK3-51-NEXT: [[E:%.*]] = alloca i32, align 4 // CHECK3-51-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_25:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_28:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR4:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR4:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR5:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED7:%.*]] = alloca [[STRUCT_ANON_31:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR9:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR9:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR10:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED12:%.*]] = alloca [[STRUCT_ANON_34:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR14:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR14:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR15:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[AGG_CAPTURED17:%.*]] = alloca [[STRUCT_ANON_37:%.*]], align 1 -// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR19:%.*]] = alloca [1 x %struct.kmp_depend_info], align 8 +// CHECK3-51-NEXT: [[DOTDEP_ARR_ADDR19:%.*]] = alloca [1 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK3-51-NEXT: [[DEP_COUNTER_ADDR20:%.*]] = alloca i64, align 8 // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB29:[0-9]+]]) // CHECK3-51-NEXT: [[TMP0:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..28) -// CHECK3-51-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26]], ptr [[TMP0]], i32 0, i32 1 -// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_27:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27]], ptr [[TMP0]], i32 0, i32 1 +// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_26:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-51-NEXT: store i32 [[TMP4]], ptr [[TMP3]], align 8 -// CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP5]], i64 0 +// CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP5]], i64 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP6]], i32 0, i32 0 // CHECK3-51-NEXT: store i64 0, ptr [[TMP7]], align 8 // CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP6]], i32 0, i32 1 @@ -8897,12 +8908,12 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[TMP0]], i32 2, ptr [[TMP5]], i32 0, ptr null) // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB31:[0-9]+]]) // CHECK3-51-NEXT: [[TMP16:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..31) -// CHECK3-51-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29:%.*]], ptr [[TMP16]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29]], ptr [[TMP16]], i32 0, i32 1 -// CHECK3-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_30:%.*]], ptr [[TMP18]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30:%.*]], ptr [[TMP16]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30]], ptr [[TMP16]], i32 0, i32 1 +// CHECK3-51-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_29:%.*]], ptr [[TMP18]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP20:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-51-NEXT: store i32 [[TMP20]], ptr [[TMP19]], align 8 -// CHECK3-51-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR4]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP21:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR4]], i64 0, i64 0 // CHECK3-51-NEXT: [[TMP22:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP21]], i64 0 // CHECK3-51-NEXT: [[TMP23:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP22]], i32 0, i32 0 // CHECK3-51-NEXT: store i64 0, ptr [[TMP23]], align 8 @@ -8923,12 +8934,12 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM6]], ptr [[TMP16]], i32 2, ptr [[TMP21]], i32 0, ptr null) // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB33:[0-9]+]]) // CHECK3-51-NEXT: [[TMP32:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..34) -// CHECK3-51-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32:%.*]], ptr [[TMP32]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32]], ptr [[TMP32]], i32 0, i32 1 -// CHECK3-51-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_33:%.*]], ptr [[TMP34]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33:%.*]], ptr [[TMP32]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33]], ptr [[TMP32]], i32 0, i32 1 +// CHECK3-51-NEXT: [[TMP35:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_32:%.*]], ptr [[TMP34]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-51-NEXT: store i32 [[TMP36]], ptr [[TMP35]], align 8 -// CHECK3-51-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR9]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR9]], i64 0, i64 0 // CHECK3-51-NEXT: [[TMP38:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP37]], i64 0 // CHECK3-51-NEXT: [[TMP39:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP38]], i32 0, i32 0 // CHECK3-51-NEXT: store i64 0, ptr [[TMP39]], align 8 @@ -8949,12 +8960,12 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP47:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]], ptr [[TMP32]], i32 2, ptr [[TMP37]], i32 0, ptr null) // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB35:[0-9]+]]) // CHECK3-51-NEXT: [[TMP48:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..37) -// CHECK3-51-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35:%.*]], ptr [[TMP48]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35]], ptr [[TMP48]], i32 0, i32 1 -// CHECK3-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_36:%.*]], ptr [[TMP50]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP49:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36:%.*]], ptr [[TMP48]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36]], ptr [[TMP48]], i32 0, i32 1 +// CHECK3-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_35:%.*]], ptr [[TMP50]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP52:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-51-NEXT: store i32 [[TMP52]], ptr [[TMP51]], align 8 -// CHECK3-51-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR14]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP53:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR14]], i64 0, i64 0 // CHECK3-51-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i64 0 // CHECK3-51-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i32 0, i32 0 // CHECK3-51-NEXT: store i64 0, ptr [[TMP55]], align 8 @@ -8975,12 +8986,12 @@ void test_transparent() // CHECK3-51-NEXT: [[TMP63:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM16]], ptr [[TMP48]], i32 2, ptr [[TMP53]], i32 0, ptr null) // CHECK3-51-NEXT: [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB37:[0-9]+]]) // CHECK3-51-NEXT: [[TMP64:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]], i32 1, i64 48, i64 1, ptr @.omp_task_entry..40) -// CHECK3-51-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38:%.*]], ptr [[TMP64]], i32 0, i32 0 -// CHECK3-51-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38]], ptr [[TMP64]], i32 0, i32 1 -// CHECK3-51-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_39:%.*]], ptr [[TMP66]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP65:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39:%.*]], ptr [[TMP64]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP66:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39]], ptr [[TMP64]], i32 0, i32 1 +// CHECK3-51-NEXT: [[TMP67:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_38:%.*]], ptr [[TMP66]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP68:%.*]] = load i32, ptr [[A]], align 4 // CHECK3-51-NEXT: store i32 [[TMP68]], ptr [[TMP67]], align 8 -// CHECK3-51-NEXT: [[TMP69:%.*]] = getelementptr inbounds [1 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR19]], i64 0, i64 0 +// CHECK3-51-NEXT: [[TMP69:%.*]] = getelementptr inbounds [1 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR19]], i64 0, i64 0 // CHECK3-51-NEXT: [[TMP70:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP69]], i64 0 // CHECK3-51-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP70]], i32 0, i32 0 // CHECK3-51-NEXT: store i64 0, ptr [[TMP71]], align 8 @@ -9002,7 +9013,7 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_27:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_26:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK3-51-NEXT: ret void @@ -9024,26 +9035,26 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK3-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META133:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META136:![0-9]+]]) +// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_27]], ptr [[TMP3]], i32 0, i32 1 +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META135:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META138:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META140:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META142:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META142]] -// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META142]] -// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..27, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META142]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META142]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META142]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META142]] -// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META142]] -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META142]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META142:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META144:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META144]] +// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META144]] +// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..27, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META144]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META144]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META144]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META144]] +// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META144]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META144]] // CHECK3-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META142]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META144]] // CHECK3-51-NEXT: store i32 13, ptr [[TMP12]], align 4 // CHECK3-51-NEXT: ret i32 0 // @@ -9056,7 +9067,7 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_30:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_29:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK3-51-NEXT: ret void @@ -9078,26 +9089,26 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK3-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_29]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META143:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META146:![0-9]+]]) +// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30]], ptr [[TMP3]], i32 0, i32 1 +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META145:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META148:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META150:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META152:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META152]] -// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META152]] -// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..30, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META152]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META152]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META152]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META152]] -// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META152]] -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META152]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META152:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META154:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META154]] +// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META154]] +// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..30, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META154]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META154]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META154]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META154]] +// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META154]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META154]] // CHECK3-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META152]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META154]] // CHECK3-51-NEXT: store i32 14, ptr [[TMP12]], align 4 // CHECK3-51-NEXT: ret i32 0 // @@ -9110,7 +9121,7 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_33:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_32:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK3-51-NEXT: ret void @@ -9132,26 +9143,26 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK3-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META153:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META156:![0-9]+]]) +// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_33]], ptr [[TMP3]], i32 0, i32 1 +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META155:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META158:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META160:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META162:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META162]] -// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META162]] -// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..33, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META162]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META162]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META162]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META162]] -// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META162]] -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META162]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META162:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META164:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META164]] +// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META164]] +// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..33, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META164]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META164]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META164]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META164]] +// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META164]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META164]] // CHECK3-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META162]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META164]] // CHECK3-51-NEXT: store i32 15, ptr [[TMP12]], align 4 // CHECK3-51-NEXT: ret i32 0 // @@ -9164,7 +9175,7 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_36:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_35:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK3-51-NEXT: ret void @@ -9186,26 +9197,26 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK3-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_35]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META163:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META166:![0-9]+]]) +// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36]], ptr [[TMP3]], i32 0, i32 1 +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META165:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META168:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META170:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META172:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META172]] -// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META172]] -// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..36, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META172]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META172]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META172]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META172]] -// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META172]] -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META172]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META172:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META174:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META174]] +// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META174]] +// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..36, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META174]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META174]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META174]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META174]] +// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META174]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META174]] // CHECK3-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META172]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META174]] // CHECK3-51-NEXT: store i32 16, ptr [[TMP12]], align 4 // CHECK3-51-NEXT: ret i32 0 // @@ -9218,7 +9229,7 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_39:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_38:%.*]], ptr [[TMP2]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 // CHECK3-51-NEXT: ret void @@ -9240,26 +9251,26 @@ void test_transparent() // CHECK3-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK3-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK3-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK3-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK3-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META173:![0-9]+]]) -// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META176:![0-9]+]]) +// CHECK3-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_39]], ptr [[TMP3]], i32 0, i32 1 +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META175:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META178:![0-9]+]]) // CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META180:![0-9]+]]) -// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META182:![0-9]+]] -// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META182]] -// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META182]] -// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..39, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META182]] -// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META182]] -// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META182]] -// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META182]] -// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META182]] -// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META182]] +// CHECK3-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META182:![0-9]+]]) +// CHECK3-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META184:![0-9]+]] +// CHECK3-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META184]] +// CHECK3-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META184]] +// CHECK3-51-NEXT: store ptr @.omp_task_privates_map..39, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META184]] +// CHECK3-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META184]] +// CHECK3-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META184]] +// CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META184]] +// CHECK3-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META184]] +// CHECK3-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META184]] // CHECK3-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META182]] +// CHECK3-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META184]] // CHECK3-51-NEXT: store i32 17, ptr [[TMP12]], align 4 // CHECK3-51-NEXT: ret i32 0 // @@ -9276,22 +9287,22 @@ void test_transparent() // CHECK4-51-NEXT: entry: // CHECK4-51-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK4-51-NEXT: [[B:%.*]] = alloca i8, align 1 -// CHECK4-51-NEXT: [[S:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK4-51-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK4-51-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK4-51-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK4-51-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 // CHECK4-51-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 -// CHECK4-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x %struct.kmp_depend_info], align 8 +// CHECK4-51-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 // CHECK4-51-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 // CHECK4-51-NEXT: [[AGG_CAPTURED6:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 // CHECK4-51-NEXT: [[AGG_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 -// CHECK4-51-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK4-51-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK4-51-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 // CHECK4-51-NEXT: [[AGG_CAPTURED19:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 -// CHECK4-51-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x %struct.kmp_depend_info], align 8 +// CHECK4-51-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK4-51-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 // CHECK4-51-NEXT: [[AGG_CAPTURED29:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 -// CHECK4-51-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x %struct.kmp_depend_info], align 8 +// CHECK4-51-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 // CHECK4-51-NEXT: [[DEP_COUNTER_ADDR37:%.*]] = alloca i64, align 8 // CHECK4-51-NEXT: [[AGG_CAPTURED39:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 // CHECK4-51-NEXT: [[FLAG:%.*]] = alloca i8, align 1 @@ -9300,8 +9311,8 @@ void test_transparent() // CHECK4-51-NEXT: [[AGG_CAPTURED45:%.*]] = alloca [[STRUCT_ANON_14:%.*]], align 8 // CHECK4-51-NEXT: [[AGG_CAPTURED48:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 // CHECK4-51-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK4-51-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 -// CHECK4-51-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK4-51-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK4-51-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK4-51-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK4-51: arrayctor.loop: // CHECK4-51-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -9341,8 +9352,8 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP15]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 // CHECK4-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP17]], ptr align 8 [[AGG_CAPTURED2]], i64 8, i1 false) -// CHECK4-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 -// CHECK4-51-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO:%.*]], ptr [[TMP18]], i64 0 +// CHECK4-51-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK4-51-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP18]], i64 0 // CHECK4-51-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 0 // CHECK4-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP20]], align 8 // CHECK4-51-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 1 @@ -9394,8 +9405,8 @@ void test_transparent() // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) // CHECK4-51-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK4-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 -// CHECK4-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 -// CHECK4-51-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK4-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 +// CHECK4-51-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK4-51-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 // CHECK4-51-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 // CHECK4-51-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 @@ -9434,8 +9445,8 @@ void test_transparent() // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11:[0-9]+]]) // CHECK4-51-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK4-51-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 -// CHECK4-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 -// CHECK4-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK4-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK4-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 // CHECK4-51-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK4-51-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 // CHECK4-51-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 @@ -9474,7 +9485,7 @@ void test_transparent() // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]) // CHECK4-51-NEXT: [[TMP99:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) // CHECK4-51-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP99]], i32 0, i32 0 -// CHECK4-51-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 +// CHECK4-51-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 // CHECK4-51-NEXT: [[TMP102:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 0 // CHECK4-51-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 0 // CHECK4-51-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP103]], align 8 @@ -9482,7 +9493,7 @@ void test_transparent() // CHECK4-51-NEXT: store i64 4, ptr [[TMP104]], align 8 // CHECK4-51-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 // CHECK4-51-NEXT: store i8 3, ptr [[TMP105]], align 8 -// CHECK4-51-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK4-51-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 // CHECK4-51-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 // CHECK4-51-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 // CHECK4-51-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 @@ -9545,9 +9556,9 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP141:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM47]], ptr [[TMP137]]) // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21:[0-9]+]]) // CHECK4-51-NEXT: [[TMP142:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM49]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..21) -// CHECK4-51-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP142]], i32 0, i32 0 -// CHECK4-51-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP142]], i32 0, i32 2 -// CHECK4-51-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP144]], i32 0, i32 0 +// CHECK4-51-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP142]], i32 0, i32 0 +// CHECK4-51-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP142]], i32 0, i32 2 +// CHECK4-51-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP144]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP146:%.*]] = load i32, ptr [[C]], align 128 // CHECK4-51-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) @@ -9558,13 +9569,13 @@ void test_transparent() // CHECK4-51-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4 // CHECK4-51-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK4-51-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP150]]) -// CHECK4-51-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i32 0, i32 0 +// CHECK4-51-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2 // CHECK4-51-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK4-51: arraydestroy.body: // CHECK4-51-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK4-51-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] // CHECK4-51-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] // CHECK4-51-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK4-51: arraydestroy.done52: @@ -9615,10 +9626,10 @@ void test_transparent() // CHECK4-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] // CHECK4-51-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] // CHECK4-51-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 -// CHECK4-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK4-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] // CHECK4-51-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 // CHECK4-51-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 -// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8 +// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] // CHECK4-51-NEXT: store i32 10, ptr [[TMP12]], align 4 // CHECK4-51-NEXT: ret i32 0 // @@ -9642,20 +9653,20 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META22:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META22]] -// CHECK4-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META22]] -// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK4-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK4-51-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK4-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 // CHECK4-51-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK4-51-NEXT: ret i32 0 // @@ -9680,42 +9691,42 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META32:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META32]] -// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK4-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK4-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK4-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK4-51-NEXT: ] // CHECK4-51: .untied.done..i: -// CHECK4-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK4-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK4-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK4-51: .untied.jmp..i: -// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META32]] +// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] // CHECK4-51-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]]) -// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META32]] +// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] // CHECK4-51-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] // CHECK4-51: .untied.jmp.1.i: // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK4-51-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) -// CHECK4-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META32]] +// CHECK4-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] // CHECK4-51-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) -// CHECK4-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK4-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK4-51-NEXT: br label [[CLEANUP_I]] // CHECK4-51: cleanup.i: -// CHECK4-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META32]] +// CHECK4-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] // CHECK4-51: .omp_outlined..3.exit: // CHECK4-51-NEXT: ret i32 0 @@ -9741,39 +9752,39 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META33:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META36:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META42:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META42]] -// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK4-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK4-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK4-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK4-51-NEXT: ] // CHECK4-51: .untied.done..i: -// CHECK4-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK4-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK4-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK4-51: .untied.jmp..i: -// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META42]] +// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] // CHECK4-51-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9]]) -// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META42]] +// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] // CHECK4-51-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] // CHECK4-51: .untied.jmp.1.i: -// CHECK4-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META42]] -// CHECK4-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK4-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK4-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK4-51-NEXT: br label [[CLEANUP_I]] // CHECK4-51: cleanup.i: -// CHECK4-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META42]] +// CHECK4-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] // CHECK4-51: .omp_outlined..5.exit: // CHECK4-51-NEXT: ret i32 0 @@ -9799,39 +9810,39 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META43:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META46:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META52:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META52]] -// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK4-51-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK4-51-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK4-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] // CHECK4-51-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] // CHECK4-51-NEXT: ] // CHECK4-51: .untied.done..i: -// CHECK4-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK4-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK4-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK4-51: .untied.jmp..i: -// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META52]] +// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] // CHECK4-51-NEXT: store i32 1, ptr [[TMP11]], align 4 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11]]) -// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META52]] +// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] // CHECK4-51-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] // CHECK4-51: .untied.jmp.1.i: -// CHECK4-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META52]] -// CHECK4-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK4-51-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK4-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK4-51-NEXT: br label [[CLEANUP_I]] // CHECK4-51: cleanup.i: -// CHECK4-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META52]] +// CHECK4-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] // CHECK4-51: .omp_outlined..7.exit: // CHECK4-51-NEXT: ret i32 0 @@ -9856,18 +9867,18 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META53:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META56:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META62:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META62]] -// CHECK4-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META62]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK4-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] // CHECK4-51-NEXT: ret i32 0 // // @@ -9890,18 +9901,18 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META63:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META66:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META72:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META72]] -// CHECK4-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META72]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK4-51-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] // CHECK4-51-NEXT: ret i32 0 // // @@ -9924,18 +9935,18 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META73:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META76:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META82:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META82]] -// CHECK4-51-NEXT: store i32 3, ptr @a, align 4, !noalias [[META82]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK4-51-NEXT: store i32 3, ptr @a, align 4, !noalias [[META84]] // CHECK4-51-NEXT: ret i32 0 // // @@ -9958,19 +9969,19 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META83:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META86:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META92:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META92]] -// CHECK4-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META92]] -// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK4-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META94]] +// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK4-51-NEXT: store i32 5, ptr [[TMP9]], align 128 // CHECK4-51-NEXT: ret i32 0 // @@ -10010,33 +10021,33 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 // CHECK4-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], ptr [[TMP3]], i32 0, i32 2 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META93:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META96:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META102:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-51-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META102]] -// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META102]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-51-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] // CHECK4-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] -// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META102]] +// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META104]] // CHECK4-51-NEXT: store i32 4, ptr [[TMP12]], align 128 -// CHECK4-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META102]] +// CHECK4-51-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] // CHECK4-51-NEXT: ret i32 0 // // // CHECK4-51-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK4-51-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-51-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-51-NEXT: entry: // CHECK4-51-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-51-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK4-51-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK4-51-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK4-51-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK4-51-NEXT: ret void // // @@ -10052,13 +10063,13 @@ void test_transparent() // CHECK4-51-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 // CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 // CHECK4-51-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 // CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 1 +// CHECK4-51-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 1 // CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 // CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 -// CHECK4-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_20]], ptr [[TMP4]], i32 0, i32 2 +// CHECK4-51-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 // CHECK4-51-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 // CHECK4-51-NEXT: ret void @@ -10086,29 +10097,29 @@ void test_transparent() // CHECK4-51-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK4-51-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 // CHECK4-51-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK4-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK4-51-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP3]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 -// CHECK4-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_19]], ptr [[TMP3]], i32 0, i32 2 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META103:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META106:![0-9]+]]) +// CHECK4-51-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META112:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] -// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META112]] -// CHECK4-51-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META114]] +// CHECK4-51-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK4-51-NEXT: switch i32 [[TMP16]], label [[DOTUNTIED_DONE__I:%.*]] [ // CHECK4-51-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] @@ -10118,19 +10129,19 @@ void test_transparent() // CHECK4-51-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]] // CHECK4-51-NEXT: ] // CHECK4-51: .untied.done..i: -// CHECK4-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK4-51-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK4-51-NEXT: br label [[CLEANUP_I:%.*]] // CHECK4-51: .untied.jmp..i: -// CHECK4-51-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: store i32 1, ptr [[TMP17]], align 4 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK4-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP18]]) // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] // CHECK4-51: .untied.jmp.2.i: // CHECK4-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) // CHECK4-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) -// CHECK4-51-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META112]] +// CHECK4-51-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META114]] // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23:[0-9]+]]) // CHECK4-51-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..19) // CHECK4-51-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.*]], ptr [[TMP20]], i32 0, i32 2 @@ -10138,41 +10149,41 @@ void test_transparent() // CHECK4-51-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 128 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) // CHECK4-51-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], ptr [[TMP20]]) -// CHECK4-51-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: store i32 2, ptr [[TMP24]], align 4 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK4-51-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], ptr [[TMP25]]) // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4-51: .untied.jmp.6.i: // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK4-51-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) -// CHECK4-51-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: store i32 3, ptr [[TMP28]], align 4 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK4-51-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], ptr [[TMP29]]) // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4-51: .untied.jmp.10.i: // CHECK4-51-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) -// CHECK4-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META112]] -// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] -// CHECK4-51-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META112]] +// CHECK4-51-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META114]] +// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK4-51-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META114]] // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK4-51-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) -// CHECK4-51-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: store i32 4, ptr [[TMP32]], align 4 // CHECK4-51-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) -// CHECK4-51-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META112]] +// CHECK4-51-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] // CHECK4-51-NEXT: [[TMP34:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], ptr [[TMP33]]) // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4-51: .untied.jmp.15.i: -// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) #[[ATTR4]] -// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) #[[ATTR4]] -// CHECK4-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S2_I]]) #[[ATTR4]] +// CHECK4-51-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S1_I]]) #[[ATTR4]] +// CHECK4-51-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK4-51-NEXT: br label [[CLEANUP_I]] // CHECK4-51: cleanup.i: -// CHECK4-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META112]] +// CHECK4-51-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] // CHECK4-51-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] // CHECK4-51: .omp_outlined..17.exit: // CHECK4-51-NEXT: ret i32 0 @@ -10190,7 +10201,7 @@ void test_transparent() // // // CHECK4-51-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK4-51-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK4-51-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK4-51-NEXT: entry: // CHECK4-51-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK4-51-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -10264,17 +10275,17 @@ void test_transparent() // CHECK4-51-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK4-51-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META113:![0-9]+]]) -// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META116:![0-9]+]]) +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) // CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) -// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META122:![0-9]+]] -// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] -// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META122]] +// CHECK4-51-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK4-51-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK4-51-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-51-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-51-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-51-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] // CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 // CHECK4-51-NEXT: store i32 0, ptr [[TMP9]], align 4 // CHECK4-51-NEXT: ret i32 0 @@ -10286,67 +10297,1501 @@ void test_transparent() // CHECK4-51-NEXT: call void @__cxx_global_var_init() // CHECK4-51-NEXT: ret void // -// CHECK6-LABEL: define void @_Z14test_threadsetv() +// +// CHECK6-LABEL: define {{[^@]+}}@main +// CHECK6-SAME: () #[[ATTR0:[0-9]+]] { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_23:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_25:%.*]], align 1 -// CHECK6-NEXT: call i32 @__kmpc_global_thread_num(ptr @[[GLOB_PTR:[0-9]+]]) -// CHECK6-NEXT: [[TMP0:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 %omp_global_thread_num, i32 1, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY1:[0-9]+]]) -// CHECK6-NEXT: getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr %0, i32 0, i32 0 -// CHECK6-NEXT: call i32 @__kmpc_global_thread_num(ptr @[[GLOB_PTR:[0-9]+]]) -// CHECK6-NEXT: call i32 @__kmpc_omp_task(ptr @1, i32 %omp_global_thread_num1, ptr %0) -// CHECK6-NEXT: call i32 @__kmpc_global_thread_num(ptr @[[GLOB_PTR2:[0-9]+]]) -// CHECK6-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 %omp_global_thread_num3, i32 129, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY2:[0-9]+]]) -// CHECK6-NEXT: getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr %3, i32 0, i32 0 -// CHECK6-NEXT: call i32 @__kmpc_global_thread_num(ptr @[[GLOB_PTR2:[0-9]+]]) -// CHECK6-NEXT: call i32 @__kmpc_omp_task(ptr @1, i32 %omp_global_thread_num4, ptr %3) -// CHECK6-NEXT: ret void - -// CHECK6-LABEL: define void @_Z16test_transparentv() #1 { +// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[B:%.*]] = alloca i8, align 1 +// CHECK6-NEXT: [[S:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 +// CHECK6-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 +// CHECK6-NEXT: [[DOTDEP_ARR_ADDR:%.*]] = alloca [4 x [[STRUCT_KMP_DEPEND_INFO:%.*]]], align 8 +// CHECK6-NEXT: [[DEP_COUNTER_ADDR:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AGG_CAPTURED6:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 1 +// CHECK6-NEXT: [[DOTDEP_ARR_ADDR11:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 +// CHECK6-NEXT: [[DEP_COUNTER_ADDR17:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AGG_CAPTURED19:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 1 +// CHECK6-NEXT: [[DOTDEP_ARR_ADDR21:%.*]] = alloca [2 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 +// CHECK6-NEXT: [[DEP_COUNTER_ADDR27:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AGG_CAPTURED29:%.*]] = alloca [[STRUCT_ANON_8:%.*]], align 1 +// CHECK6-NEXT: [[DOTDEP_ARR_ADDR31:%.*]] = alloca [3 x [[STRUCT_KMP_DEPEND_INFO]]], align 8 +// CHECK6-NEXT: [[DEP_COUNTER_ADDR37:%.*]] = alloca i64, align 8 +// CHECK6-NEXT: [[AGG_CAPTURED39:%.*]] = alloca [[STRUCT_ANON_10:%.*]], align 1 +// CHECK6-NEXT: [[FLAG:%.*]] = alloca i8, align 1 +// CHECK6-NEXT: [[AGG_CAPTURED42:%.*]] = alloca [[STRUCT_ANON_12:%.*]], align 1 +// CHECK6-NEXT: [[C:%.*]] = alloca i32, align 128 +// CHECK6-NEXT: [[AGG_CAPTURED45:%.*]] = alloca [[STRUCT_ANON_14:%.*]], align 8 +// CHECK6-NEXT: [[AGG_CAPTURED48:%.*]] = alloca [[STRUCT_ANON_16:%.*]], align 1 +// CHECK6-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// CHECK6-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 +// CHECK6-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] +// CHECK6: arrayctor.loop: +// CHECK6-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] +// CHECK6-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) +// CHECK6-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 +// CHECK6-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] +// CHECK6-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] +// CHECK6: arrayctor.cont: +// CHECK6-NEXT: [[TMP0:%.*]] = load i32, ptr @a, align 4 +// CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// CHECK6-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() +// CHECK6-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = mul nuw i64 10, [[TMP1]] +// CHECK6-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP3]], align 16 +// CHECK6-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK6-NEXT: store ptr [[B]], ptr [[TMP4]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 +// CHECK6-NEXT: store ptr [[S]], ptr [[TMP5]], align 8 +// CHECK6-NEXT: [[TMP6:%.*]] = load i8, ptr [[B]], align 1 +// CHECK6-NEXT: [[CONV:%.*]] = sext i8 [[TMP6]] to i32 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) +// CHECK6-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 33, i64 40, i64 16, ptr @.omp_task_entry.) +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP8]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK6-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP10]], ptr align 8 [[AGG_CAPTURED]], i64 16, i1 false) +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP8]], i32 0, i32 4 +// CHECK6-NEXT: store i32 [[CONV]], ptr [[TMP11]], align 8 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) +// CHECK6-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[TMP7]]) +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_0]], ptr [[AGG_CAPTURED2]], i32 0, i32 0 +// CHECK6-NEXT: store ptr [[S]], ptr [[TMP13]], align 8 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]) +// CHECK6-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 1, i64 40, i64 8, ptr @.omp_task_entry..2) +// CHECK6-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP14]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP15]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 +// CHECK6-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP17]], ptr align 8 [[AGG_CAPTURED2]], i64 8, i1 false) +// CHECK6-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP18]], i64 0 +// CHECK6-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 0 +// CHECK6-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP20]], align 8 +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, ptr [[TMP21]], align 8 +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP19]], i32 0, i32 2 +// CHECK6-NEXT: store i8 1, ptr [[TMP22]], align 8 +// CHECK6-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[B]] to i64 +// CHECK6-NEXT: [[TMP24:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP18]], i64 1 +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP24]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP23]], ptr [[TMP25]], align 8 +// CHECK6-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP24]], i32 0, i32 1 +// CHECK6-NEXT: store i64 1, ptr [[TMP26]], align 8 +// CHECK6-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP24]], i32 0, i32 2 +// CHECK6-NEXT: store i8 1, ptr [[TMP27]], align 8 +// CHECK6-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[S]] to i64 +// CHECK6-NEXT: [[TMP29:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP18]], i64 2 +// CHECK6-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP29]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP28]], ptr [[TMP30]], align 8 +// CHECK6-NEXT: [[TMP31:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP29]], i32 0, i32 1 +// CHECK6-NEXT: store i64 8, ptr [[TMP31]], align 8 +// CHECK6-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP29]], i32 0, i32 2 +// CHECK6-NEXT: store i8 1, ptr [[TMP32]], align 8 +// CHECK6-NEXT: [[TMP33:%.*]] = mul nsw i64 0, [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 [[TMP33]] +// CHECK6-NEXT: [[TMP34:%.*]] = mul nsw i64 9, [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 [[TMP34]] +// CHECK6-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[ARRAYIDX4]], i32 1 +// CHECK6-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 +// CHECK6-NEXT: [[TMP37:%.*]] = ptrtoint ptr [[TMP35]] to i64 +// CHECK6-NEXT: [[TMP38:%.*]] = sub nuw i64 [[TMP37]], [[TMP36]] +// CHECK6-NEXT: [[TMP39:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 +// CHECK6-NEXT: [[TMP40:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP18]], i64 3 +// CHECK6-NEXT: [[TMP41:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP40]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP39]], ptr [[TMP41]], align 8 +// CHECK6-NEXT: [[TMP42:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP40]], i32 0, i32 1 +// CHECK6-NEXT: store i64 [[TMP38]], ptr [[TMP42]], align 8 +// CHECK6-NEXT: [[TMP43:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP40]], i32 0, i32 2 +// CHECK6-NEXT: store i8 1, ptr [[TMP43]], align 8 +// CHECK6-NEXT: store i64 4, ptr [[DEP_COUNTER_ADDR]], align 8 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM5:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5]]) +// CHECK6-NEXT: [[TMP44:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5]], ptr [[TMP14]], i32 4, ptr [[TMP18]], i32 0, ptr null) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]) +// CHECK6-NEXT: [[TMP45:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM7]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..4) +// CHECK6-NEXT: [[TMP46:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP45]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]]) +// CHECK6-NEXT: [[TMP47:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP46]], i32 0, i32 2 +// CHECK6-NEXT: store i32 0, ptr [[TMP47]], align 8 +// CHECK6-NEXT: [[TMP48:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]], ptr [[TMP45]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) +// CHECK6-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) +// CHECK6-NEXT: [[TMP50:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 +// CHECK6-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 +// CHECK6-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 +// CHECK6-NEXT: [[TMP54:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP52]], ptr [[TMP54]], align 8 +// CHECK6-NEXT: [[TMP55:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, ptr [[TMP55]], align 8 +// CHECK6-NEXT: [[TMP56:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 2 +// CHECK6-NEXT: store i8 3, ptr [[TMP56]], align 8 +// CHECK6-NEXT: [[TMP57:%.*]] = load i8, ptr [[B]], align 1 +// CHECK6-NEXT: [[TMP58:%.*]] = sext i8 [[TMP57]] to i64 +// CHECK6-NEXT: [[TMP59:%.*]] = mul nsw i64 4, [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 [[TMP59]] +// CHECK6-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds nuw i32, ptr [[ARRAYIDX13]], i64 [[TMP58]] +// CHECK6-NEXT: [[TMP60:%.*]] = load i8, ptr [[B]], align 1 +// CHECK6-NEXT: [[TMP61:%.*]] = sext i8 [[TMP60]] to i64 +// CHECK6-NEXT: [[TMP62:%.*]] = mul nsw i64 9, [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 [[TMP62]] +// CHECK6-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds nuw i32, ptr [[ARRAYIDX15]], i64 [[TMP61]] +// CHECK6-NEXT: [[TMP63:%.*]] = getelementptr i32, ptr [[ARRAYIDX16]], i32 1 +// CHECK6-NEXT: [[TMP64:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 +// CHECK6-NEXT: [[TMP65:%.*]] = ptrtoint ptr [[TMP63]] to i64 +// CHECK6-NEXT: [[TMP66:%.*]] = sub nuw i64 [[TMP65]], [[TMP64]] +// CHECK6-NEXT: [[TMP67:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 +// CHECK6-NEXT: [[TMP68:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 1 +// CHECK6-NEXT: [[TMP69:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP68]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP67]], ptr [[TMP69]], align 8 +// CHECK6-NEXT: [[TMP70:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP68]], i32 0, i32 1 +// CHECK6-NEXT: store i64 [[TMP66]], ptr [[TMP70]], align 8 +// CHECK6-NEXT: [[TMP71:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP68]], i32 0, i32 2 +// CHECK6-NEXT: store i8 3, ptr [[TMP71]], align 8 +// CHECK6-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR17]], align 8 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9]]) +// CHECK6-NEXT: [[TMP72:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP50]], i32 0, i32 2 +// CHECK6-NEXT: store i32 0, ptr [[TMP72]], align 8 +// CHECK6-NEXT: [[TMP73:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]], ptr [[TMP49]], i32 2, ptr [[TMP51]], i32 0, ptr null) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM20:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11:[0-9]+]]) +// CHECK6-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) +// CHECK6-NEXT: [[TMP75:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 +// CHECK6-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 +// CHECK6-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 +// CHECK6-NEXT: [[TMP79:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP77]], ptr [[TMP79]], align 8 +// CHECK6-NEXT: [[TMP80:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, ptr [[TMP80]], align 8 +// CHECK6-NEXT: [[TMP81:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 2 +// CHECK6-NEXT: store i8 4, ptr [[TMP81]], align 8 +// CHECK6-NEXT: [[TMP82:%.*]] = load i8, ptr [[B]], align 1 +// CHECK6-NEXT: [[TMP83:%.*]] = sext i8 [[TMP82]] to i64 +// CHECK6-NEXT: [[TMP84:%.*]] = mul nsw i64 4, [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 [[TMP84]] +// CHECK6-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds nuw i32, ptr [[ARRAYIDX23]], i64 [[TMP83]] +// CHECK6-NEXT: [[TMP85:%.*]] = load i8, ptr [[B]], align 1 +// CHECK6-NEXT: [[TMP86:%.*]] = sext i8 [[TMP85]] to i64 +// CHECK6-NEXT: [[TMP87:%.*]] = mul nsw i64 9, [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 [[TMP87]] +// CHECK6-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds nuw i32, ptr [[ARRAYIDX25]], i64 [[TMP86]] +// CHECK6-NEXT: [[TMP88:%.*]] = getelementptr i32, ptr [[ARRAYIDX26]], i32 1 +// CHECK6-NEXT: [[TMP89:%.*]] = ptrtoint ptr [[ARRAYIDX24]] to i64 +// CHECK6-NEXT: [[TMP90:%.*]] = ptrtoint ptr [[TMP88]] to i64 +// CHECK6-NEXT: [[TMP91:%.*]] = sub nuw i64 [[TMP90]], [[TMP89]] +// CHECK6-NEXT: [[TMP92:%.*]] = ptrtoint ptr [[ARRAYIDX24]] to i64 +// CHECK6-NEXT: [[TMP93:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 1 +// CHECK6-NEXT: [[TMP94:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP93]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP92]], ptr [[TMP94]], align 8 +// CHECK6-NEXT: [[TMP95:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP93]], i32 0, i32 1 +// CHECK6-NEXT: store i64 [[TMP91]], ptr [[TMP95]], align 8 +// CHECK6-NEXT: [[TMP96:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP93]], i32 0, i32 2 +// CHECK6-NEXT: store i8 4, ptr [[TMP96]], align 8 +// CHECK6-NEXT: store i64 2, ptr [[DEP_COUNTER_ADDR27]], align 8 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM28:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11]]) +// CHECK6-NEXT: [[TMP97:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP75]], i32 0, i32 2 +// CHECK6-NEXT: store i32 0, ptr [[TMP97]], align 8 +// CHECK6-NEXT: [[TMP98:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM28]], ptr [[TMP74]], i32 2, ptr [[TMP76]], i32 0, ptr null) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM30:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13:[0-9]+]]) +// CHECK6-NEXT: [[TMP99:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM30]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..10) +// CHECK6-NEXT: [[TMP100:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP99]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP101:%.*]] = getelementptr inbounds [3 x [[STRUCT_KMP_DEPEND_INFO]]], ptr [[DOTDEP_ARR_ADDR31]], i64 0, i64 0 +// CHECK6-NEXT: [[TMP102:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 0 +// CHECK6-NEXT: [[TMP103:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 0 +// CHECK6-NEXT: store i64 ptrtoint (ptr @a to i64), ptr [[TMP103]], align 8 +// CHECK6-NEXT: [[TMP104:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, ptr [[TMP104]], align 8 +// CHECK6-NEXT: [[TMP105:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 +// CHECK6-NEXT: store i8 3, ptr [[TMP105]], align 8 +// CHECK6-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i64 0, i64 1 +// CHECK6-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 +// CHECK6-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 +// CHECK6-NEXT: [[TMP108:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP106]], ptr [[TMP108]], align 8 +// CHECK6-NEXT: [[TMP109:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 1 +// CHECK6-NEXT: store i64 4, ptr [[TMP109]], align 8 +// CHECK6-NEXT: [[TMP110:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 2 +// CHECK6-NEXT: store i8 3, ptr [[TMP110]], align 8 +// CHECK6-NEXT: [[TMP111:%.*]] = mul nsw i64 0, [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 [[TMP111]] +// CHECK6-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds nuw i32, ptr [[ARRAYIDX33]], i64 3 +// CHECK6-NEXT: [[TMP112:%.*]] = load i32, ptr @a, align 4 +// CHECK6-NEXT: [[TMP113:%.*]] = sext i32 [[TMP112]] to i64 +// CHECK6-NEXT: [[LEN_SUB_1:%.*]] = sub nsw i64 [[TMP113]], 1 +// CHECK6-NEXT: [[TMP114:%.*]] = load i32, ptr @a, align 4 +// CHECK6-NEXT: [[TMP115:%.*]] = sext i32 [[TMP114]] to i64 +// CHECK6-NEXT: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, [[TMP115]] +// CHECK6-NEXT: [[TMP116:%.*]] = mul nsw i64 [[LB_ADD_LEN]], [[TMP1]] +// CHECK6-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds nuw i32, ptr [[VLA]], i64 [[TMP116]] +// CHECK6-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds nuw i32, ptr [[ARRAYIDX35]], i64 [[LEN_SUB_1]] +// CHECK6-NEXT: [[TMP117:%.*]] = getelementptr i32, ptr [[ARRAYIDX36]], i32 1 +// CHECK6-NEXT: [[TMP118:%.*]] = ptrtoint ptr [[ARRAYIDX34]] to i64 +// CHECK6-NEXT: [[TMP119:%.*]] = ptrtoint ptr [[TMP117]] to i64 +// CHECK6-NEXT: [[TMP120:%.*]] = sub nuw i64 [[TMP119]], [[TMP118]] +// CHECK6-NEXT: [[TMP121:%.*]] = ptrtoint ptr [[ARRAYIDX34]] to i64 +// CHECK6-NEXT: [[TMP122:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 2 +// CHECK6-NEXT: [[TMP123:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP122]], i32 0, i32 0 +// CHECK6-NEXT: store i64 [[TMP121]], ptr [[TMP123]], align 8 +// CHECK6-NEXT: [[TMP124:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP122]], i32 0, i32 1 +// CHECK6-NEXT: store i64 [[TMP120]], ptr [[TMP124]], align 8 +// CHECK6-NEXT: [[TMP125:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP122]], i32 0, i32 2 +// CHECK6-NEXT: store i8 3, ptr [[TMP125]], align 8 +// CHECK6-NEXT: store i64 3, ptr [[DEP_COUNTER_ADDR37]], align 8 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM38:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB13]]) +// CHECK6-NEXT: [[TMP126:%.*]] = call i32 @__kmpc_omp_task_with_deps(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM38]], ptr [[TMP99]], i32 3, ptr [[TMP101]], i32 0, ptr null) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM40:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB15:[0-9]+]]) +// CHECK6-NEXT: [[TMP127:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM40]], i32 3, i64 40, i64 1, ptr @.omp_task_entry..12) +// CHECK6-NEXT: [[TMP128:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], ptr [[TMP127]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB15]]) +// CHECK6-NEXT: [[TMP129:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]], ptr [[TMP127]]) +// CHECK6-NEXT: store i8 0, ptr [[FLAG]], align 1 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM43:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB17:[0-9]+]]) +// CHECK6-NEXT: [[TMP130:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM43]], i32 1, i64 40, i64 1, ptr @.omp_task_entry..14) +// CHECK6-NEXT: [[TMP131:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], ptr [[TMP130]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM44:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB17]]) +// CHECK6-NEXT: [[TMP132:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM44]], ptr [[TMP130]]) +// CHECK6-NEXT: [[TMP133:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_14]], ptr [[AGG_CAPTURED45]], i32 0, i32 0 +// CHECK6-NEXT: store ptr [[C]], ptr [[TMP133]], align 8 +// CHECK6-NEXT: [[TMP134:%.*]] = load i8, ptr [[B]], align 1 +// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i8 [[TMP134]], 0 +// CHECK6-NEXT: [[TMP135:%.*]] = select i1 [[TOBOOL]], i32 2, i32 0 +// CHECK6-NEXT: [[TMP136:%.*]] = or i32 [[TMP135]], 1 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM46:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB19:[0-9]+]]) +// CHECK6-NEXT: [[TMP137:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM46]], i32 [[TMP136]], i64 40, i64 8, ptr @.omp_task_entry..16) +// CHECK6-NEXT: [[TMP138:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], ptr [[TMP137]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP139:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP138]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP140:%.*]] = load ptr, ptr [[TMP139]], align 8 +// CHECK6-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP140]], ptr align 8 [[AGG_CAPTURED45]], i64 8, i1 false) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM47:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB19]]) +// CHECK6-NEXT: [[TMP141:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM47]], ptr [[TMP137]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21:[0-9]+]]) +// CHECK6-NEXT: [[TMP142:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM49]], i32 0, i64 256, i64 1, ptr @.omp_task_entry..21) +// CHECK6-NEXT: [[TMP143:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP142]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP144:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP142]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP145:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP144]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP146:%.*]] = load i32, ptr [[C]], align 128 +// CHECK6-NEXT: store i32 [[TMP146]], ptr [[TMP145]], align 128 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM50:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) +// CHECK6-NEXT: [[TMP147:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP143]], i32 0, i32 2 +// CHECK6-NEXT: store i32 0, ptr [[TMP147]], align 16 +// CHECK6-NEXT: [[TMP148:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM50]], ptr [[TMP142]]) +// CHECK6-NEXT: [[TMP149:%.*]] = load i32, ptr @a, align 4 +// CHECK6-NEXT: store i32 [[TMP149]], ptr [[RETVAL]], align 4 +// CHECK6-NEXT: [[TMP150:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// CHECK6-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP150]]) +// CHECK6-NEXT: [[ARRAY_BEGIN51:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN51]], i64 2 +// CHECK6-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] +// CHECK6: arraydestroy.body: +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP151]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK6-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 +// CHECK6-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4:[0-9]+]] +// CHECK6-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN51]] +// CHECK6-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE52:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK6: arraydestroy.done52: +// CHECK6-NEXT: [[TMP152:%.*]] = load i32, ptr [[RETVAL]], align 4 +// CHECK6-NEXT: ret i32 [[TMP152]] +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC1Ev +// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] align 2 { // CHECK6-NEXT: entry: -// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_27:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_29:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED5:%.*]] = alloca [[STRUCT_ANON_31:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_33:%.*]], align 1 -// CHECK6-NEXT: [[V:%.*]] = alloca ptr, align 8 -// CHECK6-NEXT: [[AGG_CAPTURED11:%.*]] = alloca [[STRUCT_ANON_35:%.*]], align 1 -//CHECK6-NEXT: [[AGG_CAPTURED14:%.*]] = alloca [[STRUCT_ANON_37:%.*]], align 1 -// CHECK6-NEXT: [[AGG_CAPTURED17:%.*]] = alloca [[STRUCT_ANON_39:%.*]], align 1 -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @31) -// CHECK6-NEXT: [[TMP0:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY1:[0-9]+]]) -// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP0]], i32 0, i32 0 -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @31) -// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_omp_task(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[TMP0]]) -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @33) -// CHECK6-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY2:[0-9]+]]) -// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP3]], i32 0, i32 0 -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @33) -// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_omp_task(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM4]], ptr [[TMP3]]) -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @35) -// CHECK6-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM6]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY3:[0-9]+]]) -// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP6]], i32 0, i32 0 -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(ptr @35) -// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM7]], ptr [[TMP6]]) -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM9:%.*]] = call i32 @__kmpc_global_thread_num(ptr @37) -// CHECK6-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM9]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY4:[0-9]+]]) -// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP9]], i32 0, i32 0 -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @37) -// CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_omp_task(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM10]], ptr [[TMP9]]) -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @39) -// CHECK6-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM12]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY37:[0-9]+]]) -// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP12]], i32 0, i32 0 -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @39) -// CHECK6-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM13]], ptr [[TMP12]]) - -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM15:%.*]] = call i32 @__kmpc_global_thread_num(ptr @41) -// CHECK6-NEXT: [[TMP15:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM15]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY39:[0-9]+]]) -// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP15]], i32 0, i32 0 -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM16:%.*]] = call i32 @__kmpc_global_thread_num(ptr @41) -// CHECK6-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_omp_task(ptr @1, i32 %omp_global_thread_num16, ptr [[TMP15]]) -// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @43) - // CHECK6-NEXT: [[TMP18:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM18]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..[[ENTRY41:[0-9]+]]) - // CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP18]], i32 0, i32 0 - // CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @43) - // CHECK6-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_omp_task(ptr @1, i32 [[OMP_GLOBAL_THREAD_NUM19]], ptr [[TMP18]]) -// CHECK6-NEXT: ret void -// CHECK6-NEXT:} +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry. +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META12:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META12]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META12]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META12]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META12]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META12]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META12]] +// CHECK6-NEXT: store i32 15, ptr @a, align 4, !noalias [[META12]] +// CHECK6-NEXT: [[TMP9:%.*]] = load i32, ptr @a, align 4, !noalias [[META12]] +// CHECK6-NEXT: [[CONV_I:%.*]] = trunc i32 [[TMP9]] to i8 +// CHECK6-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13:![0-9]+]] +// CHECK6-NEXT: store i8 [[CONV_I]], ptr [[TMP10]], align 1 +// CHECK6-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP8]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP12:%.*]] = load ptr, ptr [[TMP11]], align 8, !nonnull [[META13]], !align [[META14:![0-9]+]] +// CHECK6-NEXT: store i32 10, ptr [[TMP12]], align 4 +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..2 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_1:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] +// CHECK6-NEXT: store i32 15, ptr @a, align 4, !noalias [[META24]] +// CHECK6-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK6-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr [[TMP9]], i64 0, i64 1 +// CHECK6-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..4 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[CLEANUP_DEST_SLOT_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_3:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META28:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META30:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META32:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META34:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK6-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ +// CHECK6-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] +// CHECK6-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .untied.done..i: +// CHECK6-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] +// CHECK6-NEXT: br label [[CLEANUP_I:%.*]] +// CHECK6: .untied.jmp..i: +// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: store i32 1, ptr [[TMP11]], align 4 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]]) +// CHECK6-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META34]] +// CHECK6-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT:%.*]] +// CHECK6: .untied.jmp.1.i: +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM2_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK6-NEXT: call void @__kmpc_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) +// CHECK6-NEXT: store i32 1, ptr @a, align 4, !noalias [[META34]] +// CHECK6-NEXT: call void @__kmpc_end_critical(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2_I]], ptr @.gomp_critical_user_.var) +// CHECK6-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] +// CHECK6-NEXT: br label [[CLEANUP_I]] +// CHECK6: cleanup.i: +// CHECK6-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META34]] +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]] +// CHECK6: .omp_outlined..3.exit: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..6 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[CLEANUP_DEST_SLOT_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META35:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META38:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META40:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META42:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META44:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK6-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ +// CHECK6-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] +// CHECK6-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .untied.done..i: +// CHECK6-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] +// CHECK6-NEXT: br label [[CLEANUP_I:%.*]] +// CHECK6: .untied.jmp..i: +// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: store i32 1, ptr [[TMP11]], align 4 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9]]) +// CHECK6-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META44]] +// CHECK6-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT:%.*]] +// CHECK6: .untied.jmp.1.i: +// CHECK6-NEXT: store i32 1, ptr @a, align 4, !noalias [[META44]] +// CHECK6-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] +// CHECK6-NEXT: br label [[CLEANUP_I]] +// CHECK6: cleanup.i: +// CHECK6-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META44]] +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__5_EXIT]] +// CHECK6: .omp_outlined..5.exit: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..8 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[CLEANUP_DEST_SLOT_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META45:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META48:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META50:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META52:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META54:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 +// CHECK6-NEXT: switch i32 [[TMP10]], label [[DOTUNTIED_DONE__I:%.*]] [ +// CHECK6-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] +// CHECK6-NEXT: i32 1, label [[DOTUNTIED_JMP_1_I:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .untied.done..i: +// CHECK6-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] +// CHECK6-NEXT: br label [[CLEANUP_I:%.*]] +// CHECK6: .untied.jmp..i: +// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: store i32 1, ptr [[TMP11]], align 4 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB11]]) +// CHECK6-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META54]] +// CHECK6-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP12]]) +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT:%.*]] +// CHECK6: .untied.jmp.1.i: +// CHECK6-NEXT: store i32 1, ptr @a, align 4, !noalias [[META54]] +// CHECK6-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] +// CHECK6-NEXT: br label [[CLEANUP_I]] +// CHECK6: cleanup.i: +// CHECK6-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META54]] +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__7_EXIT]] +// CHECK6: .omp_outlined..7.exit: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..10 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_9:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META55:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META58:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META60:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META62:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META64:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META64]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META64]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META64]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META64]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META64]] +// CHECK6-NEXT: store i32 2, ptr @a, align 4, !noalias [[META64]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..12 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_11:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META65:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META68:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META70:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META72:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META74:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META74]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META74]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META74]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META74]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META74]] +// CHECK6-NEXT: store i32 2, ptr @a, align 4, !noalias [[META74]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..14 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_13:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META75:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META78:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META80:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META82:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META84:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META84]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META84]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META84]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META84]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META84]] +// CHECK6-NEXT: store i32 3, ptr @a, align 4, !noalias [[META84]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..16 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_15:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META85:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META88:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META90:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META92:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META94:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META94]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META94]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META94]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META94]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META94]] +// CHECK6-NEXT: store i32 4, ptr @a, align 4, !noalias [[META94]] +// CHECK6-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META13]], !align [[META14]] +// CHECK6-NEXT: store i32 5, ptr [[TMP9]], align 128 +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_privates_map. +// CHECK6-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[TMP4]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..19 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18]], ptr [[TMP3]], i32 0, i32 2 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META95:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META98:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META100:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META102:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META104:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META104]] +// CHECK6-NEXT: store i32 4, ptr [[TMP12]], align 128 +// CHECK6-NEXT: store i32 4, ptr @a, align 4, !noalias [[META104]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD1Ev +// CHECK6-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_privates_map..20 +// CHECK6-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]]) #[[ATTR7]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8 +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR]], align 8 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19:%.*]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[TMP6]], align 8 +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 1 +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTADDR2]], align 8 +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[TMP8]], align 8 +// CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[STRUCT__KMP_PRIVATES_T_19]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTADDR3]], align 8 +// CHECK6-NEXT: store ptr [[TMP9]], ptr [[TMP10]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..21 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTLOCAL_PTR_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTLOCAL_PTR_ADDR1_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[CLEANUP_DEST_SLOT_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[S1_I:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK6-NEXT: [[S2_I:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK6-NEXT: [[REF_TMP_I:%.*]] = alloca [[STRUCT_S]], align 4 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 128 +// CHECK6-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_20]], ptr [[TMP3]], i32 0, i32 2 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META105:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META108:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META110:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META112:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META114:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: store ptr @.omp_task_privates_map..20, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR_I]], ptr [[DOTLOCAL_PTR_ADDR1_I]]) #[[ATTR4]] +// CHECK6-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTLOCAL_PTR_ADDR1_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 +// CHECK6-NEXT: switch i32 [[TMP16]], label [[DOTUNTIED_DONE__I:%.*]] [ +// CHECK6-NEXT: i32 0, label [[DOTUNTIED_JMP__I:%.*]] +// CHECK6-NEXT: i32 1, label [[DOTUNTIED_JMP_2_I:%.*]] +// CHECK6-NEXT: i32 2, label [[DOTUNTIED_JMP_6_I:%.*]] +// CHECK6-NEXT: i32 3, label [[DOTUNTIED_JMP_10_I:%.*]] +// CHECK6-NEXT: i32 4, label [[DOTUNTIED_JMP_15_I:%.*]] +// CHECK6-NEXT: ] +// CHECK6: .untied.done..i: +// CHECK6-NEXT: store i32 1, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] +// CHECK6-NEXT: br label [[CLEANUP_I:%.*]] +// CHECK6: .untied.jmp..i: +// CHECK6-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: store i32 1, ptr [[TMP17]], align 4 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) +// CHECK6-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP19:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM_I]], ptr [[TMP18]]) +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT:%.*]] +// CHECK6: .untied.jmp.2.i: +// CHECK6-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S1_I]]) +// CHECK6-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[S2_I]]) +// CHECK6-NEXT: store i32 0, ptr [[S2_I]], align 4, !noalias [[META114]] +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM3_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23:[0-9]+]]) +// CHECK6-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3_I]], i32 1, i64 256, i64 1, ptr @.omp_task_entry..19) +// CHECK6-NEXT: [[TMP21:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_18:%.*]], ptr [[TMP20]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP12]], align 128 +// CHECK6-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 128 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM4_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB23]]) +// CHECK6-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4_I]], ptr [[TMP20]]) +// CHECK6-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: store i32 2, ptr [[TMP24]], align 4 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM5_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) +// CHECK6-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM5_I]], ptr [[TMP25]]) +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] +// CHECK6: .untied.jmp.6.i: +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM8_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK6-NEXT: [[TMP27:%.*]] = call i32 @__kmpc_omp_taskyield(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8_I]], i32 0) +// CHECK6-NEXT: [[TMP28:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: store i32 3, ptr [[TMP28]], align 4 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM9_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) +// CHECK6-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP30:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9_I]], ptr [[TMP29]]) +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] +// CHECK6: .untied.jmp.10.i: +// CHECK6-NEXT: call void @_ZN1SC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP_I]]) +// CHECK6-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[S1_I]], ptr align 4 [[REF_TMP_I]], i64 4, i1 false), !noalias [[META114]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP_I]]) #[[ATTR4]] +// CHECK6-NEXT: store i32 10, ptr [[S2_I]], align 4, !noalias [[META114]] +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM13_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK6-NEXT: [[TMP31:%.*]] = call i32 @__kmpc_omp_taskwait(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13_I]]) +// CHECK6-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: store i32 4, ptr [[TMP32]], align 4 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM14_I:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB21]]) +// CHECK6-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META114]] +// CHECK6-NEXT: [[TMP34:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM14_I]], ptr [[TMP33]]) +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] +// CHECK6: .untied.jmp.15.i: +// CHECK6-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S2_I]]) #[[ATTR4]] +// CHECK6-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[S1_I]]) #[[ATTR4]] +// CHECK6-NEXT: store i32 0, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] +// CHECK6-NEXT: br label [[CLEANUP_I]] +// CHECK6: cleanup.i: +// CHECK6-NEXT: [[CLEANUP_DEST_I:%.*]] = load i32, ptr [[CLEANUP_DEST_SLOT_I]], align 4, !noalias [[META114]] +// CHECK6-NEXT: br label [[DOTOMP_OUTLINED__17_EXIT]] +// CHECK6: .omp_outlined..17.exit: +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SC2Ev +// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0 +// CHECK6-NEXT: store i32 0, ptr [[A]], align 4 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN1SD2Ev +// CHECK6-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@__cxx_global_var_init +// CHECK6-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @_ZN2S1C1Ev(ptr noundef nonnull align 4 dereferenceable(4) @s1) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2S1C1Ev +// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN2S1C2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2S1C2Ev +// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: call void @_ZN2S18taskinitEv(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@_ZN2S18taskinitEv +// CHECK6-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) #[[ATTR1]] align 2 { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_21:%.*]], align 8 +// CHECK6-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 +// CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON_21]], ptr [[AGG_CAPTURED]], i32 0, i32 0 +// CHECK6-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 8 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB25:[0-9]+]]) +// CHECK6-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1, i64 40, i64 8, ptr @.omp_task_entry..23) +// CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.*]], ptr [[TMP1]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP2]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP3]], align 8 +// CHECK6-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP4]], ptr align 8 [[AGG_CAPTURED]], i64 8, i1 false) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB25]]) +// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]], ptr [[TMP1]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..23 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_22:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META115:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META118:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META120:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META122:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META124:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META124]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META124]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META124]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META124]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META124]] +// CHECK6-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK6-NEXT: store i32 0, ptr [[TMP9]], align 4 +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z14test_threadsetv +// CHECK6-SAME: () #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_23:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_25:%.*]], align 1 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]) +// CHECK6-NEXT: [[TMP0:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1, i64 40, i64 1, ptr @.omp_task_entry..25) +// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27]]) +// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[TMP0]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB29:[0-9]+]]) +// CHECK6-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 129, i64 40, i64 1, ptr @.omp_task_entry..27) +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB29]]) +// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4]], ptr [[TMP3]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..25 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_24:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META125:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META128:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META130:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META132:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META134:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META134]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META134]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META134]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META134]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META134]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..27 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_26:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META135:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META138:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META140:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META142:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META144:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META144]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META144]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META144]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META144]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META144]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META144]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@_Z16test_transparentv +// CHECK6-SAME: () #[[ATTR1]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_27:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED2:%.*]] = alloca [[STRUCT_ANON_29:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED5:%.*]] = alloca [[STRUCT_ANON_31:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED8:%.*]] = alloca [[STRUCT_ANON_33:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED11:%.*]] = alloca [[STRUCT_ANON_35:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED14:%.*]] = alloca [[STRUCT_ANON_37:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED17:%.*]] = alloca [[STRUCT_ANON_39:%.*]], align 1 +// CHECK6-NEXT: [[V:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[AGG_CAPTURED20:%.*]] = alloca [[STRUCT_ANON_41:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED23:%.*]] = alloca [[STRUCT_ANON_43:%.*]], align 1 +// CHECK6-NEXT: [[AGG_CAPTURED26:%.*]] = alloca [[STRUCT_ANON_45:%.*]], align 1 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB31:[0-9]+]]) +// CHECK6-NEXT: [[TMP0:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..29) +// CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_28:%.*]], ptr [[TMP0]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB31]]) +// CHECK6-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[TMP0]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB33:[0-9]+]]) +// CHECK6-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..31) +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB33]]) +// CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM4]], ptr [[TMP3]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB35:[0-9]+]]) +// CHECK6-NEXT: [[TMP6:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM6]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..33) +// CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32:%.*]], ptr [[TMP6]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB35]]) +// CHECK6-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM7]], ptr [[TMP6]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM9:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB37:[0-9]+]]) +// CHECK6-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM9]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..35) +// CHECK6-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_34:%.*]], ptr [[TMP9]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB37]]) +// CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], ptr [[TMP9]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB39:[0-9]+]]) +// CHECK6-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM12]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..37) +// CHECK6-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36:%.*]], ptr [[TMP12]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM13:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB39]]) +// CHECK6-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM13]], ptr [[TMP12]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM15:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]) +// CHECK6-NEXT: [[TMP15:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM15]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..39) +// CHECK6-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38:%.*]], ptr [[TMP15]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM16:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41]]) +// CHECK6-NEXT: [[TMP17:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM16]], ptr [[TMP15]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB43:[0-9]+]]) +// CHECK6-NEXT: [[TMP18:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..41) +// CHECK6-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_40:%.*]], ptr [[TMP18]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB43]]) +// CHECK6-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM19]], ptr [[TMP18]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM21:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB45:[0-9]+]]) +// CHECK6-NEXT: [[TMP21:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM21]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..43) +// CHECK6-NEXT: [[TMP22:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42:%.*]], ptr [[TMP21]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM22:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB45]]) +// CHECK6-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM22]], ptr [[TMP21]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM24:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB47:[0-9]+]]) +// CHECK6-NEXT: [[TMP24:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM24]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..45) +// CHECK6-NEXT: [[TMP25:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_44:%.*]], ptr [[TMP24]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM25:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB47]]) +// CHECK6-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM25]], ptr [[TMP24]]) +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM27:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB49:[0-9]+]]) +// CHECK6-NEXT: [[TMP27:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM27]], i32 257, i64 40, i64 1, ptr @.omp_task_entry..47) +// CHECK6-NEXT: [[TMP28:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_46:%.*]], ptr [[TMP27]], i32 0, i32 0 +// CHECK6-NEXT: [[OMP_GLOBAL_THREAD_NUM28:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB49]]) +// CHECK6-NEXT: [[TMP29:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM28]], ptr [[TMP27]]) +// CHECK6-NEXT: ret void +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..29 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_28:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META145:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META148:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META150:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META152:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META154:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META154]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META154]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META154]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META154]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META154]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META154]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..31 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_30:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META155:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META158:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META160:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META162:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META164:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META164]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META164]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META164]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META164]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META164]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META164]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..33 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_32:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META165:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META168:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META170:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META172:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META174:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META174]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META174]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META174]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META174]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META174]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META174]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..35 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_34:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META175:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META178:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META180:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META182:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META184:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META184]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META184]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META184]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META184]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META184]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META184]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..37 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_36:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META185:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META188:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META190:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META192:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META194:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META194]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META194]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META194]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META194]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META194]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META194]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..39 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_38:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META195:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META198:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META200:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META202:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META204:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META204]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META204]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META204]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META204]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META204]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META204]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..41 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_40:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META205:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META208:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META210:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META212:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META214:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META214]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META214]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META214]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META214]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META214]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META214]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..43 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_42:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META215:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META218:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META220:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META222:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META224:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META224]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META224]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META224]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META224]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META224]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META224]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..45 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_44:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META225:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META228:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META230:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META232:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META234:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META234]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META234]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META234]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META234]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META234]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META234]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@.omp_task_entry..47 +// CHECK6-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 +// CHECK6-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 +// CHECK6-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4 +// CHECK6-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 +// CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES_46:%.*]], ptr [[TMP3]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 +// CHECK6-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 +// CHECK6-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META235:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META238:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META240:![0-9]+]]) +// CHECK6-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META242:![0-9]+]]) +// CHECK6-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META244:![0-9]+]] +// CHECK6-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META244]] +// CHECK6-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META244]] +// CHECK6-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META244]] +// CHECK6-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META244]] +// CHECK6-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META244]] +// CHECK6-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META244]] +// CHECK6-NEXT: ret i32 0 +// +// +// CHECK6-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_task_codegen.cpp +// CHECK6-SAME: () #[[ATTR7]] section "__TEXT,__StaticInit,regular,pure_instructions" { +// CHECK6-NEXT: entry: +// CHECK6-NEXT: call void @__cxx_global_var_init() +// CHECK6-NEXT: ret void +// diff --git a/clang/test/OpenMP/task_in_reduction_codegen.cpp b/clang/test/OpenMP/task_in_reduction_codegen.cpp index 29dc12978d7d9..cd6ed42218f38 100644 --- a/clang/test/OpenMP/task_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/task_in_reduction_codegen.cpp @@ -61,20 +61,20 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK1-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [[STRUCT_S:%.*]]], align 16 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x %struct.kmp_taskred_input_t], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x [[STRUCT_KMP_TASKRED_INPUT_T:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x %struct.kmp_taskred_input_t.0], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_6:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -90,8 +90,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP5]], align 8 @@ -105,7 +105,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb., ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 1 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 1 @@ -120,7 +120,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..2, ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP17]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 2 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 2 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP18]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 1 @@ -138,8 +138,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP25:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 3, ptr [[DOTRD_INPUT_]]) // CHECK1-NEXT: store ptr [[TMP25]], ptr [[DOTTASK_RED_]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP26]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP27]], align 8 @@ -153,7 +153,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..6, ptr [[TMP31]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 1 @@ -186,13 +186,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP49:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP49]]) -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP50]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -302,8 +302,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP2]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -322,13 +322,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP1]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -336,12 +336,12 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -363,7 +363,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] @@ -381,7 +381,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[AGG_RESULT]], ptr [[RESULT_PTR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK1-NEXT: call void @_ZN1SC1ERKS_(ptr nonnull align 4 dereferenceable(4) [[AGG_RESULT]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // @@ -472,11 +472,11 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_1]], ptr [[DOTTASK_RED__ADDR2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8, !nonnull [[META3]], !align [[META6:![0-9]+]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8, !nonnull [[META3]], !align [[META6]] // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 @@ -546,30 +546,30 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META12:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META12]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META12]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META12]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META12]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META12]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META12]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META16:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META16]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META16]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META16]] // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 8 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META12]] -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META12]] +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META16]] +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META16]] // CHECK1-NEXT: call void [[TMP12]](ptr [[TMP13]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]] -// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META12]] -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META12]] -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP9]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META16]] +// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META16]] +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[TMP9]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META12]] +// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META16]] // CHECK1-NEXT: [[TMP19:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP18]], ptr [[TMP17]], ptr [[TMP16]]) // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[TMP20]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP22:%.*]] = mul nuw i64 [[TMP11]], 2 // CHECK1-NEXT: [[TMP23:%.*]] = udiv exact i64 [[TMP22]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP24:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP18]], ptr @{{reduction_size[.].+[.]}}) @@ -606,19 +606,19 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META24]] -// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META24]] -// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META24]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META24]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META24]] -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META24]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META26:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META28:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META28]] +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META3]], !align [[META4]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META28]] // CHECK1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP10]], ptr null, ptr [[TMP9]]) // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK1-NEXT: [[INC_I:%.*]] = add nsw i32 [[TMP12]], 1 @@ -638,7 +638,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/taskloop_ast_print.cpp b/clang/test/OpenMP/taskloop_ast_print.cpp index 9bca586937347..ff39f525435d4 100644 --- a/clang/test/OpenMP/taskloop_ast_print.cpp +++ b/clang/test/OpenMP/taskloop_ast_print.cpp @@ -104,14 +104,20 @@ int main(int argc, char **argv) { } } -#pragma omp taskloop transparent(omp_not_impex) +#pragma omp taskloop transparent priority(10) for (int i = 0; i < 10; ++i) { -#pragma omp task transparent(omp_import) +#pragma omp taskloop transparent for (int i = 0; i < 10; ++i) { -#pragma omp task transparent(omp_export) +#pragma omp taskloop transparent(omp_not_impex) for (int i = 0; i < 10; ++i) { +#pragma omp task transparent(omp_import) + for (int i = 0; i < 10; ++i) { +#pragma omp task transparent(omp_export) + for (int i = 0; i < 10; ++i) { #pragma omp task transparent(omp_impex) - foo(); + foo(); + } + } } } } @@ -122,14 +128,16 @@ int main(int argc, char **argv) { // CHECK60-NEXT: for (int j = 0; j < 10; ++j) { // CHECK60-NEXT: foo(); -// CHECK60: #pragma omp taskloop transparent(omp_not_impex) -// CHECK60-NEXT: for (int i = 0; i < 10; ++i) { -// CHECK60-NEXT: #pragma omp task transparent(omp_import) -// CHECK60-NEXT: for (int i = 0; i < 10; ++i) { -// CHECK60-NEXT: #pragma omp task transparent(omp_export) -// CHECK60-NEXT: for (int i = 0; i < 10; ++i) { -// CHECK60-NEXT: #pragma omp task transparent(omp_impex) -// CHECK60-NEXT: foo(); + // CHECK60: #pragma omp taskloop transparent(omp_impex) priority(10) + // CHECK60: #pragma omp taskloop transparent(omp_impex) + // CHECK60: #pragma omp taskloop transparent(omp_not_impex) + // CHECK60-NEXT: for (int i = 0; i < 10; ++i) { + // CHECK60-NEXT: #pragma omp task transparent(omp_import) + // CHECK60-NEXT: for (int i = 0; i < 10; ++i) { + // CHECK60-NEXT: #pragma omp task transparent(omp_export) + // CHECK60-NEXT: for (int i = 0; i < 10; ++i) { + // CHECK60-NEXT: #pragma omp task transparent(omp_impex) + // CHECK60-NEXT: foo(); return (tmain(argc) + tmain(argv[0][0])); } diff --git a/clang/test/OpenMP/taskloop_codegen.cpp b/clang/test/OpenMP/taskloop_codegen.cpp index 9073a2376f5b4..b5bbf6e259c35 100644 --- a/clang/test/OpenMP/taskloop_codegen.cpp +++ b/clang/test/OpenMP/taskloop_codegen.cpp @@ -265,6 +265,12 @@ void test_threadset() void test_transparent() { +#pragma omp taskloop transparent priority(10) + for (int i = 0; i < 10; ++i) { + } +#pragma omp taskloop transparent + for (int i = 0; i < 10; ++i) { + } #pragma omp taskloop transparent(omp_not_impex) for (int i = 0; i < 10; ++i) { } @@ -327,62 +333,95 @@ void test_transparent() // CHECK6: [[TMP4:%.*]] = alloca i32, align 4 // CHECK6: [[AGG_CAPTURED5:%.*]] = alloca [[STRUCT_ANON_24:%.*]], align 1 // CHECK6: [[TMP6:%.*]] = alloca i32, align 4 +// CHECK6: [[AGGD_CAPTURED9:%.*]] = alloca [[STRUCT_ANON_28:%.*]], align 1 +// CHECK6: [[TMP10:%.*]] = alloca i32, align 4 // CHECK6: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @1) // CHECK6: call void @__kmpc_taskgroup(ptr @1, i32 [[TMP0]]) -// CHECK6: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..[[ENTRY1:[0-9]+]]) +// CHECK6: [[TMP1:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 289, i64 80, i64 1, ptr @.omp_task_entry..[[ENTRY1:[0-9]+]]) // CHECK6: [[TMP2:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP1]], i32 0, i32 0 -// CHECK6: [[TMP3:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP2]], i32 0, i32 5 -// CHECK6: store i64 0, ptr [[TMP3]], align 8 -// CHECK6: [[TMP4:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP2]], i32 0, i32 6 -// CHECK6: store i64 9, ptr [[TMP4]], align 8 -// CHECK6: [[TMP5:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP2]], i32 0, i32 7 -// CHECK6: store i64 1, ptr [[TMP5]], align 8 -// CHECK6: [[TMP6:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP2]], i32 0, i32 9 -// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP6]], i8 0, i64 8, i1 false) -// CHECK6: [[TMP7:%.*]] = load i64, ptr [[TMP5]], align 8 -// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP1]], i32 1, ptr [[TMP3]], ptr [[TMP4]], i64 [[TMP7]], i32 1, i32 0, i64 0, ptr null) +// CHECK6: [[TMP3:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP2]], i32 0, i32 4 +// CHECK6: store i32 10, ptr [[TMP3]], align 8 +// CHECK6: [[TMP4:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP2]], i32 0, i32 5 +// CHECK6: store i64 0, ptr [[TMP4]], align 8 +// CHECK6: [[TMP5:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP2]], i32 0, i32 6 +// CHECK6: store i64 9, ptr [[TMP5]], align 8 +// CHECK6: [[TMP6:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP2]], i32 0, i32 7 +// CHECK6: store i64 1, ptr [[TMP6]], align 8 +// CHECK6: [[TMP7:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP2]], i32 0, i32 9 +// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP7]], i8 0, i64 8, i1 false) +// CHECK6: [[TMP8:%.*]] = load i64, ptr [[TMP6]], align 8 +// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP1]], i32 1, ptr [[TMP4]], ptr [[TMP5]], i64 [[TMP8]], i32 1, i32 0, i64 0, ptr null) // CHECK6: call void @__kmpc_end_taskgroup(ptr @1, i32 [[TMP0]]) // CHECK6: call void @__kmpc_taskgroup(ptr @1, i32 [[TMP0]]) -// CHECK6: [[TMP8:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..[[ENTRY2:[0-9]+]]) -// CHECK6: [[TMP9:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP8]], i32 0, i32 0 -// CHECK6: [[TMP10:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP9]], i32 0, i32 5 -// CHECK6: store i64 0, ptr [[TMP10]], align 8 -// CHECK6: [[TMP11:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP9]], i32 0, i32 6 -// CHECK6: store i64 9, ptr [[TMP11]], align 8 -// CHECK6: [[TMP12:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP9]], i32 0, i32 7 -// CHECK6: store i64 1, ptr [[TMP12]], align 8 -// CHECK6: [[TMP13:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP9]], i32 0, i32 9 -// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP13]], i8 0, i64 8, i1 false) -// CHECK6: [[TMP14:%.*]] = load i64, ptr [[TMP12]], align 8 -// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP8]], i32 1, ptr [[TMP10]], ptr [[TMP11]], i64 [[TMP14]], i32 1, i32 0, i64 0, ptr null) +// CHECK6: [[TMP9:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..[[ENTRY2:[0-9]+]]) +// CHECK6: [[TMP10:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP9]], i32 0, i32 0 +// CHECK6: [[TMP11:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP10]], i32 0, i32 5 +// CHECK6: store i64 0, ptr [[TMP11]], align 8 +// CHECK6: [[TMP12:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP10]], i32 0, i32 6 +// CHECK6: store i64 9, ptr [[TMP12]], align 8 +// CHECK6: [[TMP13:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP10]], i32 0, i32 7 +// CHECK6: store i64 1, ptr [[TMP13]], align 8 +// CHECK6: [[TMP14:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP10]], i32 0, i32 9 +// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP14]], i8 0, i64 8, i1 false) +// CHECK6: [[TMP15:%.*]] = load i64, ptr [[TMP13]], align 8 +// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP9]], i32 1, ptr [[TMP11]], ptr [[TMP12]], i64 [[TMP15]], i32 1, i32 0, i64 0, ptr null) // CHECK6: call void @__kmpc_end_taskgroup(ptr @1, i32 [[TMP0]]) // CHECK6: call void @__kmpc_taskgroup(ptr @1, i32 [[TMP0]]) -// CHECK6: [[TMP15:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..22) -// CHECK6: [[TMP16:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP15]], i32 0, i32 0 -// CHECK6: [[TMP17:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP16]], i32 0, i32 5 -// CHECK6: store i64 0, ptr [[TMP17]], align 8 -// CHECK6: [[TMP18:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP16]], i32 0, i32 6 -// CHECK6: store i64 9, ptr [[TMP18]], align 8 -// CHECK6: [[TMP19:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP16]], i32 0, i32 7 -// CHECK6: store i64 1, ptr [[TMP19]], align 8 -// CHECK6: [[TMP20:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP16]], i32 0, i32 9 -// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP20]], i8 0, i64 8, i1 false) -// CHECK6: [[TMP21:%.*]] = load i64, ptr [[TMP19]], align 8 -// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP15]], i32 1, ptr [[TMP17]], ptr [[TMP18]], i64 [[TMP21]], i32 1, i32 0, i64 0, ptr null) +// CHECK6: [[TMP16:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..22) +// CHECK6: [[TMP17:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP16]], i32 0, i32 0 +// CHECK6: [[TMP18:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP17]], i32 0, i32 5 +// CHECK6: store i64 0, ptr [[TMP18]], align 8 +// CHECK6: [[TMP19:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP17]], i32 0, i32 6 +// CHECK6: store i64 9, ptr [[TMP19]], align 8 +// CHECK6: [[TMP20:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP17]], i32 0, i32 7 +// CHECK6: store i64 1, ptr [[TMP20]], align 8 +// CHECK6: [[TMP21:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP17]], i32 0, i32 9 +// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP21]], i8 0, i64 8, i1 false) +// CHECK6: [[TMP22:%.*]] = load i64, ptr [[TMP20]], align 8 +// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP16]], i32 1, ptr [[TMP18]], ptr [[TMP19]], i64 [[TMP22]], i32 1, i32 0, i64 0, ptr null) +// CHECK6: call void @__kmpc_end_taskgroup(ptr @1, i32 [[TMP0]]) +// CHECK6: call void @__kmpc_taskgroup(ptr @1, i32 [[TMP0]]) +// CHECK6: [[TMP23:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..24) +// CHECK6: [[TMP24:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP23]], i32 0, i32 0 +// CHECK6: [[TMP25:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP24]], i32 0, i32 5 +// CHECK6: store i64 0, ptr [[TMP25]], align 8 +// CHECK6: [[TMP26:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP24]], i32 0, i32 6 +// CHECK6: store i64 9, ptr [[TMP26]], align 8 +// CHECK6: [[TMP27:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP24]], i32 0, i32 7 +// CHECK6: store i64 1, ptr [[TMP27]], align 8 +// CHECK6: [[TMP28:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP24]], i32 0, i32 9 +// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP28]], i8 0, i64 8, i1 false) +// CHECK6: [[TMP29:%.*]] = load i64, ptr [[TMP27]], align 8 +// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP23]], i32 1, ptr [[TMP25]], ptr [[TMP26]], i64 [[TMP29]], i32 1, i32 0, i64 0, ptr null) +// CHECK6: call void @__kmpc_end_taskgroup(ptr @1, i32 [[TMP0]]) + +// CHECK6: call void @__kmpc_taskgroup(ptr @1, i32 [[TMP0]]) +// CHECK6: [[TMP30:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..[[ENTRY26:[0-9]+]]) +// CHECK6: [[TMP31:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates.27, ptr [[TMP30]], i32 0, i32 0 +// CHECK6: [[TMP32:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP31]], i32 0, i32 5 +// CHECK6: store i64 0, ptr [[TMP32]], align 8 +// CHECK6: [[TMP33:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP31]], i32 0, i32 6 +// CHECK6: store i64 9, ptr [[TMP33]], align 8 +// CHECK6: [[TMP34:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP31]], i32 0, i32 7 +// CHECK6: store i64 1, ptr [[TMP34]], align 8 +// CHECK6: [[TMP35:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP31]], i32 0, i32 9 +// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP35]], i8 0, i64 8, i1 false) +// CHECK6: [[TMP36:%.*]] = load i64, ptr [[TMP34]], align 8 +// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP30]], i32 1, ptr [[TMP32]], ptr [[TMP33]], i64 [[TMP36]], i32 1, i32 0, i64 0, ptr null) // CHECK6: call void @__kmpc_end_taskgroup(ptr @1, i32 [[TMP0]]) // CHECK6: call void @__kmpc_taskgroup(ptr @1, i32 [[TMP0]]) -// CHECK6: [[TMP22:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..24) -// CHECK6: [[TMP23:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates{{.*}}, ptr [[TMP22]], i32 0, i32 0 -// CHECK6: [[TMP24:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP23]], i32 0, i32 5 -// CHECK6: store i64 0, ptr [[TMP24]], align 8 -// CHECK6: [[TMP25:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP23]], i32 0, i32 6 -// CHECK6: store i64 9, ptr [[TMP25]], align 8 -// CHECK6: [[TMP26:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP23]], i32 0, i32 7 -// CHECK6: store i64 1, ptr [[TMP26]], align 8 -// CHECK6: [[TMP27:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t{{.*}}, ptr [[TMP23]], i32 0, i32 9 -// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP27]], i8 0, i64 8, i1 false) -// CHECK6: [[TMP28:%.*]] = load i64, ptr [[TMP26]], align 8 -// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP22]], i32 1, ptr [[TMP24]], ptr [[TMP25]], i64 [[TMP28]], i32 1, i32 0, i64 0, ptr null) +// CHECK6: [[TMP37:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @1, i32 [[TMP0]], i32 257, i64 80, i64 1, ptr @.omp_task_entry..[[ENTRY28:[0-9]+]]) +// CHECK6: [[TMP38:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t_with_privates.29, ptr [[TMP37]], i32 0, i32 0 +// CHECK6: [[TMP39:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP38]], i32 0, i32 5 +// CHECK6: store i64 0, ptr [[TMP39]], align 8 +// CHECK6: [[TMP40:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP38]], i32 0, i32 6 +// CHECK6: store i64 9, ptr [[TMP40]], align 8 +// CHECK6: [[TMP41:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP38]], i32 0, i32 7 +// CHECK6: store i64 1, ptr [[TMP41]], align 8 +// CHECK6: [[TMP42:%.*]] = getelementptr inbounds nuw %struct.kmp_task_t.2, ptr [[TMP38]], i32 0, i32 9 +// CHECK6: call void @llvm.memset.p0.i64(ptr align 8 [[TMP42]], i8 0, i64 8, i1 false) +// CHECK6: [[TMP43:%.*]] = load i64, ptr [[TMP41]], align 8 +// CHECK6: call void @__kmpc_taskloop(ptr @1, i32 [[TMP0]], ptr [[TMP37]], i32 1, ptr [[TMP39]], ptr [[TMP40]], i64 [[TMP43]], i32 1, i32 0, i64 0, ptr null) // CHECK6: call void @__kmpc_end_taskgroup(ptr @1, i32 [[TMP0]]) // CHECK6: ret void // CHECK6:} diff --git a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp index 87b4cd2caf18a..1ea8c597f3608 100644 --- a/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_in_reduction_codegen.cpp @@ -48,19 +48,19 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK1-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [[STRUCT_S:%.*]]], align 16 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x %struct.kmp_taskred_input_t], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x [[STRUCT_KMP_TASKRED_INPUT_T:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x %struct.kmp_taskred_input_t.0], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_6:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -76,8 +76,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP5]], align 8 @@ -91,7 +91,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb., ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 1 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 1 @@ -106,7 +106,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..2, ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP17]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 2 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 2 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP18]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 1 @@ -124,8 +124,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP25:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 3, ptr [[DOTRD_INPUT_]]) // CHECK1-NEXT: store ptr [[TMP25]], ptr [[DOTTASK_RED_]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP26]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP27]], align 8 @@ -139,7 +139,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..6, ptr [[TMP31]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 1 @@ -164,13 +164,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP43]]) -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -280,8 +280,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP2]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -300,13 +300,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP1]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -314,12 +314,12 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -341,7 +341,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] @@ -359,7 +359,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[AGG_RESULT]], ptr [[RESULT_PTR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK1-NEXT: call void @_ZN1SC1ERKS_(ptr nonnull align 4 dereferenceable(4) [[AGG_RESULT]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // @@ -451,11 +451,11 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_1]], ptr [[DOTTASK_RED__ADDR2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8, !nonnull [[META3]], !align [[META6:![0-9]+]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8, !nonnull [[META3]], !align [[META6]] // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 @@ -553,55 +553,55 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META18:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: call void [[TMP22]](ptr [[TMP23]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]] -// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP28]], ptr [[TMP27]], ptr [[TMP26]]) // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8 +// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP32:%.*]] = mul nuw i64 [[TMP21]], 2 // CHECK1-NEXT: [[TMP33:%.*]] = udiv exact i64 [[TMP32]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP34:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP28]], ptr @{{reduction_size[.].+[.]}}) // CHECK1-NEXT: store i64 [[TMP33]], ptr [[TMP34]], align 8 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP25]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP28]], ptr [[TMP35]], ptr [[TMP31]]) -// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP37]] to i32 -// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK1: omp.inner.for.cond.i: -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP38]] to i64 -// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP39]] // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: omp.inner.for.body.i: -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] +// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP29]], align 4 // CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP41]] to i64 // CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i16, ptr [[TMP36]], i64 [[IDXPROM_I]] @@ -610,9 +610,9 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP29]], align 4 // CHECK1-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], [[CONV3_I]] // CHECK1-NEXT: store i32 [[ADD4_I]], ptr [[TMP29]], align 4 -// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[ADD5_I:%.*]] = add nsw i32 [[TMP44]], 1 -// CHECK1-NEXT: store i32 [[ADD5_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[ADD5_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]] // CHECK1: .omp_outlined..exit: // CHECK1-NEXT: ret i32 0 @@ -630,7 +630,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp b/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp index 9e4e51a442742..b3d32f9a11d3e 100644 --- a/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp +++ b/clang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp @@ -48,19 +48,19 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK1-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [[STRUCT_S:%.*]]], align 16 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x %struct.kmp_taskred_input_t], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_:%.*]] = alloca [3 x [[STRUCT_KMP_TASKRED_INPUT_T:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x %struct.kmp_taskred_input_t.0], align 8 +// CHECK1-NEXT: [[DOTRD_INPUT_3:%.*]] = alloca [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]]], align 8 // CHECK1-NEXT: [[DOTTASK_RED_6:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: // CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -76,8 +76,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP2]], align 16 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP5]], align 8 @@ -91,7 +91,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb., ptr [[TMP9]], align 8 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP10]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_1:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 1 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 1 @@ -106,7 +106,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..2, ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_1]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP17]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 2 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_2:%.*]] = getelementptr inbounds nuw [3 x [[STRUCT_KMP_TASKRED_INPUT_T]]], ptr [[DOTRD_INPUT_]], i64 0, i64 2 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[ARGC_ADDR]], ptr [[TMP18]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T]], ptr [[DOTRD_INPUT_GEP_2]], i32 0, i32 1 @@ -124,8 +124,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP25:%.*]] = call ptr @__kmpc_taskred_init(i32 [[TMP0]], i32 3, ptr [[DOTRD_INPUT_]]) // CHECK1-NEXT: store ptr [[TMP25]], ptr [[DOTTASK_RED_]], align 8 // CHECK1-NEXT: call void @__kmpc_taskgroup(ptr @[[GLOB1]], i32 [[TMP0]]) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0:%.*]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_4:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 0 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP26]], align 8 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 1 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP27]], align 8 @@ -139,7 +139,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr @.red_comb..6, ptr [[TMP31]], align 8 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_4]], i32 0, i32 6 // CHECK1-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP32]], i8 0, i64 4, i1 false) -// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x %struct.kmp_taskred_input_t.0], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 +// CHECK1-NEXT: [[DOTRD_INPUT_GEP_5:%.*]] = getelementptr inbounds nuw [2 x [[STRUCT_KMP_TASKRED_INPUT_T_0]]], ptr [[DOTRD_INPUT_3]], i64 0, i64 1 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP33]], align 8 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASKRED_INPUT_T_0]], ptr [[DOTRD_INPUT_GEP_5]], i32 0, i32 1 @@ -164,13 +164,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK1-NEXT: [[TMP43:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP43]]) -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP44]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -280,8 +280,8 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP2]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP2]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP3:%.*]] = getelementptr [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] // CHECK1: omp.arrayinit.body: @@ -300,13 +300,13 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP1]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S:%.*]]], ptr [[TMP1]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -314,12 +314,12 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -341,7 +341,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZplRK1SS1_(ptr dead_on_unwind writable sret([[STRUCT_S]]) align 4 [[REF_TMP]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]]) // CHECK1-NEXT: [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) ptr @_ZN1SaSERKS_(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[REF_TMP]]) #[[ATTR3]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] @@ -359,7 +359,7 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[AGG_RESULT]], ptr [[RESULT_PTR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3:![0-9]+]], !align [[META4:![0-9]+]] // CHECK1-NEXT: call void @_ZN1SC1ERKS_(ptr nonnull align 4 dereferenceable(4) [[AGG_RESULT]], ptr nonnull align 4 dereferenceable(4) [[TMP0]]) // CHECK1-NEXT: ret void // @@ -451,11 +451,11 @@ int main(int argc, char **argv) { // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_]], ptr [[DOTTASK_RED__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTTASK_RED_1]], ptr [[DOTTASK_RED__ADDR2]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META3]], !align [[META5:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR]], align 8, !nonnull [[META3]], !align [[META6:![0-9]+]] +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTTASK_RED__ADDR2]], align 8, !nonnull [[META3]], !align [[META6]] // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP5]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1 @@ -553,67 +553,67 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 9 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[TMP17]], align 8 -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META3:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META6:![0-9]+]]) -// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META8:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META7:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META10:![0-9]+]]) // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14:![0-9]+]] -// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]]) +// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) +// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META18:![0-9]+]] +// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP10]], ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i64 [[TMP14]], ptr [[DOTST__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store i32 [[TMP16]], ptr [[DOTLITER__ADDR_I]], align 4, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP18]], ptr [[DOTREDUCTIONS__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON:%.*]], ptr [[TMP19]], i32 0, i32 1 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: call void [[TMP22]](ptr [[TMP23]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]]) #[[ATTR3]] -// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META14]] -// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias [[META18]] +// CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP19]], align 8, !nonnull [[META3]], !align [[META4]] // CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP28]], ptr [[TMP27]], ptr [[TMP26]]) // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds nuw [[STRUCT_ANON]], ptr [[TMP19]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8 +// CHECK1-NEXT: [[TMP31:%.*]] = load ptr, ptr [[TMP30]], align 8, !nonnull [[META3]], !align [[META5]] // CHECK1-NEXT: [[TMP32:%.*]] = mul nuw i64 [[TMP21]], 2 // CHECK1-NEXT: [[TMP33:%.*]] = udiv exact i64 [[TMP32]], ptrtoint (ptr getelementptr (i16, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP34:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP28]], ptr @{{reduction_size[.].+[.]}}) // CHECK1-NEXT: store i64 [[TMP33]], ptr [[TMP34]], align 8 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP25]], align 8 // CHECK1-NEXT: [[TMP36:%.*]] = call ptr @__kmpc_task_reduction_get_th_data(i32 [[TMP28]], ptr [[TMP35]], ptr [[TMP31]]) -// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META14]] +// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[DOTLB__ADDR_I]], align 8, !noalias [[META18]] // CHECK1-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP37]] to i32 -// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]] +// CHECK1-NEXT: store i32 [[CONV_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I:%.*]] // CHECK1: omp.inner.for.cond.i: -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19:![0-9]+]] // CHECK1-NEXT: [[CONV2_I:%.*]] = sext i32 [[TMP38]] to i64 -// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTUB__ADDR_I]], align 8, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[CMP_I:%.*]] = icmp ule i64 [[CONV2_I]], [[TMP39]] // CHECK1-NEXT: br i1 [[CMP_I]], label [[OMP_INNER_FOR_BODY_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]] // CHECK1: omp.inner.for.body.i: -// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: store i32 [[TMP40]], ptr [[I_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[IDXPROM_I:%.*]] = sext i32 [[TMP41]] to i64 // CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i16, ptr [[TMP36]], i64 [[IDXPROM_I]] -// CHECK1-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX_I]], align 2, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP42:%.*]] = load i16, ptr [[ARRAYIDX_I]], align 2, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[CONV3_I:%.*]] = sext i16 [[TMP42]] to i32 -// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[ADD4_I:%.*]] = add nsw i32 [[TMP43]], [[CONV3_I]] -// CHECK1-NEXT: store i32 [[ADD4_I]], ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: store i32 [[ADD4_I]], ptr [[TMP29]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[ADD5_I:%.*]] = add nsw i32 [[TMP44]], 1 -// CHECK1-NEXT: store i32 [[ADD5_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META14]], !llvm.access.group [[ACC_GRP15]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP16:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD5_I]], ptr [[DOTOMP_IV_I]], align 4, !noalias [[META18]], !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND_I]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK1: .omp_outlined..exit: // CHECK1-NEXT: ret i32 0 // @@ -630,7 +630,7 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK1-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -670,7 +670,7 @@ int main(int argc, char **argv) { // CHECK3-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[B:%.*]] = alloca float, align 4 -// CHECK3-NEXT: [[C:%.*]] = alloca [5 x %struct.S], align 16 +// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [[STRUCT_S:%.*]]], align 16 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 // CHECK3-NEXT: [[DOTTASK_RED_:%.*]] = alloca ptr, align 8 @@ -683,8 +683,8 @@ int main(int argc, char **argv) { // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK3-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: // CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] @@ -737,13 +737,13 @@ int main(int argc, char **argv) { // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP11]]) -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[C]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [5 x [[STRUCT_S]]], ptr [[C]], i32 0, i32 0 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 5 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3:[0-9]+]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -762,12 +762,12 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK3-NEXT: ret void // // @@ -783,7 +783,7 @@ int main(int argc, char **argv) { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { +// CHECK3-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp index f3c9565a17656..a19541690be19 100644 --- a/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp @@ -161,12 +161,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -184,7 +184,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -223,7 +223,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -387,9 +387,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -407,7 +407,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -416,7 +416,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -424,7 +424,7 @@ int main() { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -461,7 +461,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false) // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -481,14 +481,14 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -521,12 +521,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -537,7 +537,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -621,17 +621,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP36]] // @@ -672,7 +672,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -745,9 +745,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -766,7 +766,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -775,7 +775,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -784,7 +784,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -823,7 +823,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -839,14 +839,14 @@ int main() { // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -869,12 +869,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -928,7 +928,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -964,12 +964,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -987,7 +987,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1026,7 +1026,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1190,9 +1190,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1210,7 +1210,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1219,7 +1219,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1227,7 +1227,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1262,7 +1262,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -1282,14 +1282,14 @@ int main() { // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -1322,12 +1322,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1338,7 +1338,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1422,17 +1422,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP36]] // @@ -1473,7 +1473,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1546,9 +1546,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1567,7 +1567,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1576,7 +1576,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1585,7 +1585,7 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -1622,7 +1622,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1638,14 +1638,14 @@ int main() { // CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -1668,12 +1668,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1727,7 +1727,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1763,12 +1763,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -1786,7 +1786,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1825,7 +1825,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: diff --git a/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp index 2e83429cc4c8a..66042fd4c77cd 100644 --- a/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp @@ -149,7 +149,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 @@ -168,7 +168,7 @@ int main() { // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK1-NEXT: ret void // @@ -202,16 +202,16 @@ int main() { // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -241,14 +241,14 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G2]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP13]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR5]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G2]], ptr [[TMP14]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR5]], ptr [[TMP17]], align 8 @@ -297,7 +297,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 @@ -318,16 +318,16 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 4 // CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK3-NEXT: ret void // @@ -361,16 +361,16 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -400,14 +400,14 @@ int main() { // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP13]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR5]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP14]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR5]], ptr [[TMP17]], align 4 @@ -453,7 +453,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -473,17 +473,17 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -551,17 +551,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -603,11 +603,11 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined, ptr [[TMP0]], ptr [[T_VAR_ADDR]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK9-NEXT: ret void // @@ -631,8 +631,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -643,17 +643,17 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -663,7 +663,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -700,10 +700,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -726,7 +726,7 @@ int main() { // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP23]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP24]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -745,14 +745,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP26]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -760,12 +760,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -776,7 +776,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -792,14 +792,14 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -860,17 +860,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -901,7 +901,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -944,11 +944,11 @@ int main() { // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[TMP0]], ptr [[T_VAR_ADDR]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK9-NEXT: ret void // @@ -971,8 +971,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -981,16 +981,16 @@ int main() { // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1000,7 +1000,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1037,10 +1037,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK9-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1063,7 +1063,7 @@ int main() { // CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP22]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP23]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1080,14 +1080,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[TMP24]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1095,12 +1095,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1130,7 +1130,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1147,7 +1147,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1167,17 +1167,17 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1245,17 +1245,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1297,11 +1297,11 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined, ptr [[TMP0]], ptr [[T_VAR_ADDR]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK11-NEXT: ret void // @@ -1325,8 +1325,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1337,17 +1337,17 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1357,7 +1357,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1393,9 +1393,9 @@ int main() { // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1418,7 +1418,7 @@ int main() { // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP23]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1437,14 +1437,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP26]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -1452,12 +1452,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1468,7 +1468,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1484,14 +1484,14 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1552,17 +1552,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -1593,7 +1593,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1636,11 +1636,11 @@ int main() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[TMP0]], ptr [[T_VAR_ADDR]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK11-NEXT: ret void // @@ -1663,8 +1663,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1673,16 +1673,16 @@ int main() { // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1692,7 +1692,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1728,9 +1728,9 @@ int main() { // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP14]] // CHECK11-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP16]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP15]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1753,7 +1753,7 @@ int main() { // CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP22]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP23]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1770,14 +1770,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP4]], ptr align 4 [[TMP24]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -1785,12 +1785,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1820,7 +1820,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp index 037aa12d57226..0657ed797181f 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -195,12 +195,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -218,7 +218,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -257,7 +257,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -421,9 +421,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -443,7 +443,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -452,7 +452,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -460,7 +460,7 @@ int main() { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -510,14 +510,14 @@ int main() { // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -550,12 +550,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -578,9 +578,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -606,7 +606,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -615,7 +615,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -623,7 +623,7 @@ int main() { // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -660,7 +660,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -680,14 +680,14 @@ int main() { // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -701,7 +701,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -785,17 +785,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP36]] // @@ -836,7 +836,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -909,9 +909,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -931,7 +931,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -940,7 +940,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -949,7 +949,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -998,14 +998,14 @@ int main() { // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done10: @@ -1046,9 +1046,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1075,7 +1075,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1084,7 +1084,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -1093,7 +1093,7 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -1132,7 +1132,7 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1148,14 +1148,14 @@ int main() { // CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done14: @@ -1163,12 +1163,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -1222,7 +1222,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1258,12 +1258,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1281,7 +1281,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1320,7 +1320,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1484,9 +1484,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1506,7 +1506,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1515,7 +1515,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1523,7 +1523,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1571,14 +1571,14 @@ int main() { // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done8: @@ -1611,12 +1611,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1639,9 +1639,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1665,7 +1665,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1674,7 +1674,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -1682,7 +1682,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1717,7 +1717,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -1737,14 +1737,14 @@ int main() { // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -1758,7 +1758,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1842,17 +1842,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP36]] // @@ -1893,7 +1893,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1966,9 +1966,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1988,7 +1988,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1997,7 +1997,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -2006,7 +2006,7 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -2053,14 +2053,14 @@ int main() { // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP21]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done10: @@ -2101,9 +2101,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2128,7 +2128,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2137,7 +2137,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -2146,7 +2146,7 @@ int main() { // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -2183,7 +2183,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2199,14 +2199,14 @@ int main() { // CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -2214,12 +2214,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -2273,7 +2273,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2309,12 +2309,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -2332,7 +2332,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2371,7 +2371,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp index f82a6da51728b..3b5d45f98cbd3 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -187,7 +187,7 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8 +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]]) // CHECK1-NEXT: ret i32 0 @@ -206,7 +206,7 @@ int main() { // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G_ADDR]], ptr [[TMP0]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK1-NEXT: ret void // @@ -239,16 +239,16 @@ int main() { // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7:![0-9]+]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -277,7 +277,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 8 +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[G2]], ptr [[TMP16]], ptr [[SVAR5]], ptr [[SFVAR6]]) // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: @@ -341,10 +341,10 @@ int main() { // CHECK1-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 8, !nonnull [[META5]], !align [[META6]] +// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 8, !nonnull [[META5]], !align [[META7]] // CHECK1-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -356,7 +356,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -386,14 +386,14 @@ int main() { // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: store double 1.000000e+00, ptr [[G3]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP15]], align 8 // CHECK1-NEXT: store i32 3, ptr [[SVAR6]], align 4 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[G3]], ptr [[TMP16]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK1-NEXT: store ptr [[TMP18]], ptr [[TMP17]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP19]], align 8 @@ -442,7 +442,7 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4 +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4, !nonnull [[META6:![0-9]+]], !align [[META7:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]]) // CHECK3-NEXT: ret i32 0 @@ -463,16 +463,16 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load double, ptr [[TMP0]], align 8 // CHECK3-NEXT: store double [[TMP2]], ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: [[TMP4:%.*]] = load double, ptr [[TMP3]], align 4 // CHECK3-NEXT: store double [[TMP4]], ptr [[G13]], align 8 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[G2]], ptr [[TMP5]], ptr [[SVAR_ADDR]], ptr [[SFVAR_ADDR]]) // CHECK3-NEXT: ret void // @@ -505,16 +505,16 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -541,7 +541,7 @@ int main() { // CHECK3: omp.inner.for.body: // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[G2]], ptr [[TMP14]], ptr [[SVAR5]], ptr [[SFVAR6]]) // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: @@ -605,10 +605,10 @@ int main() { // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[SFVAR]], ptr [[SFVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G1_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[SFVAR_ADDR]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP1]], ptr [[TMP]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -618,7 +618,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -648,14 +648,14 @@ int main() { // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: store double 1.000000e+00, ptr [[G2]], align 8 -// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP15]], align 4 // CHECK3-NEXT: store i32 3, ptr [[SVAR5]], align 4 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP16]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP4]], align 4 +// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP4]], align 4, !nonnull [[META6]], !align [[META7]] // CHECK3-NEXT: store ptr [[TMP18]], ptr [[TMP17]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[SVAR5]], ptr [[TMP19]], align 4 @@ -701,7 +701,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -721,17 +721,17 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -799,17 +799,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -851,11 +851,11 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined, ptr [[TMP0]], ptr [[T_VAR_ADDR]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK9-NEXT: ret void // @@ -879,8 +879,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -891,17 +891,17 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -911,7 +911,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -943,7 +943,7 @@ int main() { // CHECK9-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined, i64 [[TMP14]], i64 [[TMP16]], ptr [[VEC3]], ptr [[T_VAR2]], ptr [[S_ARR4]], ptr [[TMP17]], ptr [[SVAR7]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: @@ -965,7 +965,7 @@ int main() { // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP24]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP25]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -984,14 +984,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP27]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done12: @@ -1019,8 +1019,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1033,11 +1033,11 @@ int main() { // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1049,7 +1049,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1059,7 +1059,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1096,10 +1096,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1122,7 +1122,7 @@ int main() { // CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP25]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP26]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1141,14 +1141,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP28]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1156,12 +1156,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1172,7 +1172,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1188,14 +1188,14 @@ int main() { // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i64 1 // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2) // CHECK9-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store i64 [[TMP2]], ptr [[TMP6]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1256,17 +1256,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -1297,7 +1297,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1340,11 +1340,11 @@ int main() { // CHECK9-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[TMP0]], ptr [[T_VAR_ADDR]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK9-NEXT: ret void // @@ -1367,8 +1367,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1377,16 +1377,16 @@ int main() { // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1396,7 +1396,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK9-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1428,7 +1428,7 @@ int main() { // CHECK9-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8 +// CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[VEC3]], ptr [[T_VAR2]], ptr [[S_ARR4]], ptr [[TMP16]]) // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: @@ -1450,7 +1450,7 @@ int main() { // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP23]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP24]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1467,14 +1467,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[TMP25]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done11: @@ -1501,8 +1501,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1513,10 +1513,10 @@ int main() { // CHECK9-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8 // CHECK9-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] +// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 8 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -1528,7 +1528,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1538,7 +1538,7 @@ int main() { // CHECK9-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK9-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK9: arrayctor.cont: -// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) // CHECK9-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1575,10 +1575,10 @@ int main() { // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 +// CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1601,7 +1601,7 @@ int main() { // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP24]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP25]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1618,14 +1618,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP6]], ptr align 4 [[TMP26]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1633,12 +1633,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1668,7 +1668,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1685,7 +1685,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1705,17 +1705,17 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -1783,17 +1783,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1835,11 +1835,11 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined, ptr [[TMP0]], ptr [[T_VAR_ADDR]], ptr [[TMP1]], ptr [[TMP3]], ptr [[SVAR_ADDR]]) // CHECK11-NEXT: ret void // @@ -1863,8 +1863,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1875,17 +1875,17 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1895,7 +1895,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1925,7 +1925,7 @@ int main() { // CHECK11: omp.inner.for.body: // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined, i32 [[TMP13]], i32 [[TMP14]], ptr [[VEC3]], ptr [[T_VAR2]], ptr [[S_ARR4]], ptr [[TMP15]], ptr [[SVAR7]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: @@ -1947,7 +1947,7 @@ int main() { // CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP22]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP23]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1966,14 +1966,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP25]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -2001,8 +2001,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2015,11 +2015,11 @@ int main() { // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[SVAR]], ptr [[SVAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[SVAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2029,7 +2029,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2039,7 +2039,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2075,9 +2075,9 @@ int main() { // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP18]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2100,7 +2100,7 @@ int main() { // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP25]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP26]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2119,14 +2119,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP28]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2134,12 +2134,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2150,7 +2150,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2166,14 +2166,14 @@ int main() { // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[S_ARR]], i32 1 // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) // CHECK11-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -2234,17 +2234,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -2275,7 +2275,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2318,11 +2318,11 @@ int main() { // CHECK11-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined, ptr [[TMP0]], ptr [[T_VAR_ADDR]], ptr [[TMP1]], ptr [[TMP3]]) // CHECK11-NEXT: ret void // @@ -2345,8 +2345,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2355,16 +2355,16 @@ int main() { // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2374,7 +2374,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2404,7 +2404,7 @@ int main() { // CHECK11: omp.inner.for.body: // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[VEC3]], ptr [[T_VAR2]], ptr [[S_ARR4]], ptr [[TMP14]]) // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: @@ -2426,7 +2426,7 @@ int main() { // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP21]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP22]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2443,14 +2443,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP4]], ptr align 4 [[TMP23]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -2477,8 +2477,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2489,10 +2489,10 @@ int main() { // CHECK11-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4 // CHECK11-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] +// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 @@ -2502,7 +2502,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2512,7 +2512,7 @@ int main() { // CHECK11-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK11-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK11: arrayctor.cont: -// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) // CHECK11-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2548,9 +2548,9 @@ int main() { // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 +// CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2573,7 +2573,7 @@ int main() { // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP24]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP25]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2590,14 +2590,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP6]], ptr align 4 [[TMP26]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2605,12 +2605,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2640,7 +2640,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp index d097631f7d0e5..b738321e45902 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp @@ -135,7 +135,7 @@ int main() { // CHECK1-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR4]] // CHECK1-NEXT: br label [[EH_RESUME:%.*]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -198,7 +198,7 @@ int main() { // CHECK1: invoke.cont7: // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP45]] // CHECK1: eh.resume: @@ -670,7 +670,7 @@ int main() { // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 @@ -718,12 +718,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -742,7 +742,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1201,7 +1201,7 @@ int main() { // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 @@ -1422,7 +1422,7 @@ int main() { // CHECK5-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK5-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR4]] // CHECK5-NEXT: br label [[EH_RESUME:%.*]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -1485,7 +1485,7 @@ int main() { // CHECK5: invoke.cont7: // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP45]] // CHECK5: eh.resume: @@ -1957,7 +1957,7 @@ int main() { // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 @@ -2005,12 +2005,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -2479,7 +2479,7 @@ int main() { // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 @@ -2639,7 +2639,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp index a6abc906ecd2d..be1523ec5ef5e 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp @@ -161,12 +161,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -184,7 +184,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -223,7 +223,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -319,8 +319,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -329,7 +329,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -383,14 +383,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -412,8 +412,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -430,7 +430,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -477,7 +477,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -497,14 +497,14 @@ int main() { // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -518,7 +518,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -565,17 +565,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -624,8 +624,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -635,7 +635,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -690,14 +690,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -720,8 +720,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -739,7 +739,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -785,10 +785,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -804,14 +804,14 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -819,12 +819,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -857,7 +857,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -893,12 +893,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -916,7 +916,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -955,7 +955,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1051,8 +1051,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1061,7 +1061,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1113,14 +1113,14 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done3: @@ -1142,8 +1142,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1158,7 +1158,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1203,7 +1203,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -1223,14 +1223,14 @@ int main() { // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1244,7 +1244,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1291,17 +1291,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1350,8 +1350,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1361,7 +1361,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1414,14 +1414,14 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done5: @@ -1444,8 +1444,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1461,7 +1461,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1506,9 +1506,9 @@ int main() { // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1524,14 +1524,14 @@ int main() { // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1539,12 +1539,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1577,7 +1577,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1613,12 +1613,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -1636,7 +1636,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1675,7 +1675,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -1859,13 +1859,13 @@ int main() { // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK9-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP11]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8 +// CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK9-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp index 532aa50e7415b..79949697d410b 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -198,12 +198,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -221,7 +221,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -260,7 +260,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -424,9 +424,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -446,7 +446,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -455,7 +455,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -463,7 +463,7 @@ int main() { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -520,14 +520,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -560,12 +560,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -588,9 +588,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -616,7 +616,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -625,7 +625,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -633,7 +633,7 @@ int main() { // CHECK1: omp.arraycpy.done4: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -670,7 +670,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]] @@ -697,14 +697,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -718,7 +718,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -802,17 +802,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP36]] // @@ -853,7 +853,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -926,9 +926,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -948,7 +948,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -957,7 +957,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -966,7 +966,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -1022,14 +1022,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done10: @@ -1070,9 +1070,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP8:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1099,7 +1099,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1108,7 +1108,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -1117,7 +1117,7 @@ int main() { // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR6]], ptr [[_TMP8]], align 8 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -1156,7 +1156,7 @@ int main() { // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP21]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1179,14 +1179,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done14: @@ -1194,12 +1194,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -1253,7 +1253,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1289,12 +1289,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1312,7 +1312,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1351,7 +1351,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1515,9 +1515,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1537,7 +1537,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1546,7 +1546,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1554,7 +1554,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1609,14 +1609,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done8: @@ -1649,12 +1649,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1677,9 +1677,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1703,7 +1703,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1712,7 +1712,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -1720,7 +1720,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1755,7 +1755,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]] @@ -1782,14 +1782,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -1803,7 +1803,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1887,17 +1887,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP36]] // @@ -1938,7 +1938,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2011,9 +2011,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2033,7 +2033,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2042,7 +2042,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -2051,7 +2051,7 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -2105,14 +2105,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done10: @@ -2153,9 +2153,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2180,7 +2180,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2189,7 +2189,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]] @@ -2198,7 +2198,7 @@ int main() { // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 @@ -2235,7 +2235,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP22]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP22]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2258,14 +2258,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -2273,12 +2273,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -2332,7 +2332,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2368,12 +2368,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -2408,7 +2408,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -2455,7 +2455,7 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr @s_arr, i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] @@ -2482,7 +2482,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2527,7 +2527,7 @@ int main() { // CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2540,17 +2540,17 @@ int main() { // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP14]] // @@ -2569,7 +2569,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2618,12 +2618,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -2656,7 +2656,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2692,12 +2692,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2732,7 +2732,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -2777,7 +2777,7 @@ int main() { // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr @s_arr, i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] @@ -2804,7 +2804,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2847,7 +2847,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2860,17 +2860,17 @@ int main() { // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP14]] // @@ -2889,7 +2889,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2938,12 +2938,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2976,7 +2976,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3012,12 +3012,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -3035,7 +3035,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3074,7 +3074,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -3358,12 +3358,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // @@ -3398,7 +3398,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -3437,7 +3437,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp index 25020d5f51362..b62ed708a5838 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -774,7 +774,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -872,17 +872,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -952,8 +952,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -974,7 +974,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1045,7 +1045,7 @@ int main() { // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP26]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP27]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1064,14 +1064,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP29]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done12: @@ -1099,8 +1099,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR8:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1129,7 +1129,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1179,7 +1179,7 @@ int main() { // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1209,7 +1209,7 @@ int main() { // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP27]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP28]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1228,14 +1228,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP30]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done16: @@ -1243,12 +1243,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1259,7 +1259,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -1343,17 +1343,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -1384,7 +1384,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1454,8 +1454,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1473,7 +1473,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1544,7 +1544,7 @@ int main() { // CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP25]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP26]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1561,14 +1561,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[TMP27]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done11: @@ -1595,8 +1595,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1622,7 +1622,7 @@ int main() { // CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1672,7 +1672,7 @@ int main() { // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1702,7 +1702,7 @@ int main() { // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: store i32 [[TMP26]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP27]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1719,14 +1719,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP6]], ptr align 4 [[TMP28]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -1734,12 +1734,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1769,7 +1769,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1786,7 +1786,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1884,17 +1884,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1964,8 +1964,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1986,7 +1986,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2055,7 +2055,7 @@ int main() { // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP24]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP25]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2074,14 +2074,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP27]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done12: @@ -2109,8 +2109,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2137,7 +2137,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2185,7 +2185,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2215,7 +2215,7 @@ int main() { // CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP27]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP28]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2234,14 +2234,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP30]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP31]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -2249,12 +2249,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2265,7 +2265,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -2349,17 +2349,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -2390,7 +2390,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2460,8 +2460,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2479,7 +2479,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2548,7 +2548,7 @@ int main() { // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP23]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP24]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2565,14 +2565,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP4]], ptr align 4 [[TMP25]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done11: @@ -2599,8 +2599,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -2624,7 +2624,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -2672,7 +2672,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2702,7 +2702,7 @@ int main() { // CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP26]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP27]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2719,14 +2719,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP6]], ptr align 4 [[TMP28]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -2734,12 +2734,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -2769,7 +2769,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2786,7 +2786,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2797,7 +2797,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2821,7 +2821,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2855,7 +2855,7 @@ int main() { // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2870,7 +2870,7 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP15]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2887,30 +2887,30 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN16]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] // CHECK13: arraydestroy.body17: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13: arraydestroy.done21: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP20]] // @@ -2939,12 +2939,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2955,7 +2955,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2966,7 +2966,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2986,7 +2986,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -3020,7 +3020,7 @@ int main() { // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3035,7 +3035,7 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK13-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP15]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3050,29 +3050,29 @@ int main() { // CHECK13: omp.arraycpy.done12: // CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] // CHECK13: arraydestroy.body16: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13: arraydestroy.done20: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP19]] // @@ -3089,7 +3089,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3135,12 +3135,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -3170,7 +3170,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3187,7 +3187,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -3198,7 +3198,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -3222,7 +3222,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3254,7 +3254,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3269,7 +3269,7 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP15]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3286,30 +3286,30 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP17]], ptr @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done13: // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] // CHECK15: arraydestroy.body16: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP19]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK15: arraydestroy.done20: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP20]] // @@ -3338,12 +3338,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -3354,7 +3354,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -3365,7 +3365,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -3385,7 +3385,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -3417,7 +3417,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3432,7 +3432,7 @@ int main() { // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK15-NEXT: store i32 [[TMP14]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP15]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -3447,29 +3447,29 @@ int main() { // CHECK15: omp.arraycpy.done11: // CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP16]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done13: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY15:%.*]] // CHECK15: arraydestroy.body15: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK15: arraydestroy.done19: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP19]] // @@ -3486,7 +3486,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -3532,12 +3532,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -3567,7 +3567,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp index d5f3af343fced..8dbf1ca9f20f9 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp @@ -137,7 +137,7 @@ int main() { // CHECK1-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK1-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR4]] // CHECK1-NEXT: br label [[EH_RESUME:%.*]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -200,7 +200,7 @@ int main() { // CHECK1: invoke.cont7: // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK1-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP45]] // CHECK1: eh.resume: @@ -279,24 +279,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -357,26 +357,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP19]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -393,7 +393,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP13]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: unreachable // // @@ -458,26 +458,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP18]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -538,26 +538,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -574,7 +574,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP21]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] // CHECK1-NEXT: unreachable // // @@ -700,7 +700,7 @@ int main() { // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 @@ -748,12 +748,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR4]] // CHECK1-NEXT: ret void // // @@ -772,7 +772,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -823,24 +823,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP24]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -901,26 +901,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -937,7 +937,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] // CHECK1-NEXT: unreachable // // @@ -984,24 +984,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP30]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1062,26 +1062,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1098,7 +1098,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] // CHECK1-NEXT: unreachable // // @@ -1145,24 +1145,24 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP36]] -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP42]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1223,26 +1223,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1259,7 +1259,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] // CHECK1-NEXT: unreachable // // @@ -1273,7 +1273,7 @@ int main() { // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK1: invoke.cont: // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] +// CHECK1-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] // CHECK1-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK1-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 @@ -1326,26 +1326,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48:![0-9]+]] +// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP48]] // CHECK1-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK1-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP48]] // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1406,26 +1406,26 @@ int main() { // CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51:![0-9]+]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP51]] // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP51]] // CHECK1-NEXT: invoke void @_Z3foov() -// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP51]] // CHECK1: invoke.cont: // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: @@ -1442,7 +1442,7 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK1-NEXT: catch ptr null // CHECK1-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] +// CHECK1-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP51]] // CHECK1-NEXT: unreachable // // @@ -1504,7 +1504,7 @@ int main() { // CHECK3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8 // CHECK3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5:[0-9]+]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR5:[0-9]+]] // CHECK3-NEXT: br label [[EH_RESUME:%.*]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: store i32 100, ptr [[I]], align 4 @@ -1549,7 +1549,7 @@ int main() { // CHECK3: invoke.cont21: // CHECK3-NEXT: [[ADD23:%.*]] = add nsw i32 [[ADD20]], [[CALL22]] // CHECK3-NEXT: store i32 [[ADD23]], ptr [[RETVAL]], align 4 -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR5]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR5]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP15]] // CHECK3: eh.resume: @@ -1723,7 +1723,7 @@ int main() { // CHECK3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[TERMINATE_LPAD]] // CHECK3: invoke.cont2: // CHECK3-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] +// CHECK3-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR5]] // CHECK3-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB4]], align 4 // CHECK3-NEXT: store i32 99, ptr [[DOTOMP_UB5]], align 4 @@ -1763,12 +1763,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK3-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]] +// CHECK3-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR5]] // CHECK3-NEXT: ret void // // @@ -1787,7 +1787,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK3-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1857,7 +1857,7 @@ int main() { // CHECK5-NEXT: store ptr [[TMP16]], ptr [[EXN_SLOT]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = extractvalue { ptr, i32 } [[TMP15]], 1 // CHECK5-NEXT: store i32 [[TMP17]], ptr [[EHSELECTOR_SLOT]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR4]] // CHECK5-NEXT: br label [[EH_RESUME:%.*]] // CHECK5: omp_offload.cont: // CHECK5-NEXT: [[TMP18:%.*]] = load i8, ptr [[A]], align 1 @@ -1920,7 +1920,7 @@ int main() { // CHECK5: invoke.cont7: // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[ADD]], [[CALL8]] // CHECK5-NEXT: store i32 [[ADD9]], ptr [[RETVAL]], align 4 -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[S]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[S]]) #[[ATTR4]] // CHECK5-NEXT: [[TMP45:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP45]] // CHECK5: eh.resume: @@ -1999,24 +1999,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP9]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 2), !llvm.access.group [[ACC_GRP15]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l50.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP9]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2077,26 +2077,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP19]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2113,7 +2113,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP13]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7:[0-9]+]], !llvm.access.group [[ACC_GRP19]] // CHECK5-NEXT: unreachable // // @@ -2178,26 +2178,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP24]] // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP18]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP24]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP18]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2258,26 +2258,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2294,7 +2294,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP21]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] // CHECK5-NEXT: unreachable // // @@ -2420,7 +2420,7 @@ int main() { // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP15:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP16:%.*]] = zext i8 [[TMP15]] to i32 @@ -2468,12 +2468,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD1Ev -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR4]] // CHECK5-NEXT: ret void // // @@ -2534,24 +2534,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP24]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 5), !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP24]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2612,26 +2612,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2648,7 +2648,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP27]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: unreachable // // @@ -2695,24 +2695,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP30]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 23), !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIcLi5EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP30]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2773,26 +2773,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2809,7 +2809,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP33]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: unreachable // // @@ -2856,24 +2856,24 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP36]] -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 1), !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l36.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP42]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP36]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2934,26 +2934,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -2970,7 +2970,7 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP39]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] // CHECK5-NEXT: unreachable // // @@ -2984,7 +2984,7 @@ int main() { // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] // CHECK5: invoke.cont: // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i8 @_ZN1ScvcEv(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] +// CHECK5-NEXT: call void @_ZN1SD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[REF_TMP]]) #[[ATTR4]] // CHECK5-NEXT: store i8 [[CALL]], ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 // CHECK5-NEXT: store i8 [[TMP0]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 @@ -3037,26 +3037,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]] -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48:![0-9]+]] +// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP48]] // CHECK5-NEXT: [[TMP8:%.*]] = sext i8 [[TMP7]] to i32 -// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP42]] -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: call void @__kmpc_push_num_threads(ptr @[[GLOB3]], i32 [[TMP1]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP48]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainI1SLi1EEiv_l40.omp_outlined.omp_outlined, i64 [[TMP10]], i64 [[TMP12]]), !llvm.access.group [[ACC_GRP48]] // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP42]] +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3117,26 +3117,26 @@ int main() { // CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]] -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51:![0-9]+]] +// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP51]] // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP51]] // CHECK5-NEXT: invoke void @_Z3foov() -// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !llvm.access.group [[ACC_GRP51]] // CHECK5: invoke.cont: // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]] -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] +// CHECK5-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP51]] +// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP52:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK5: omp.loop.exit: @@ -3153,12 +3153,12 @@ int main() { // CHECK5-NEXT: [[TMP13:%.*]] = landingpad { ptr, i32 } // CHECK5-NEXT: catch ptr null // CHECK5-NEXT: [[TMP14:%.*]] = extractvalue { ptr, i32 } [[TMP13]], 0 -// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP45]] +// CHECK5-NEXT: call void @__clang_call_terminate(ptr [[TMP14]]) #[[ATTR7]], !llvm.access.group [[ACC_GRP51]] // CHECK5-NEXT: unreachable // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SD2Ev -// CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp index 934dd9542b223..47743eeabd39d 100644 --- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp @@ -163,12 +163,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -186,7 +186,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -225,7 +225,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -321,8 +321,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -331,7 +331,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -392,14 +392,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done3: @@ -421,8 +421,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -439,7 +439,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -486,7 +486,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP11]] @@ -513,14 +513,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -534,7 +534,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -581,17 +581,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -640,8 +640,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -651,7 +651,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -713,14 +713,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -743,8 +743,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -762,7 +762,7 @@ int main() { // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -811,7 +811,7 @@ int main() { // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !nonnull [[META20:![0-9]+]], !align [[META21:![0-9]+]], !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP19]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -834,14 +834,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done9: @@ -849,12 +849,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -887,7 +887,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -923,12 +923,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -946,7 +946,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -985,7 +985,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1081,8 +1081,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1091,7 +1091,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1150,14 +1150,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done3: @@ -1179,8 +1179,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1195,7 +1195,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1240,7 +1240,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP12]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -1267,14 +1267,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -1288,7 +1288,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1335,17 +1335,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1394,8 +1394,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1405,7 +1405,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1465,14 +1465,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done5: @@ -1495,8 +1495,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1512,7 +1512,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1559,7 +1559,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META21:![0-9]+]], !align [[META22:![0-9]+]], !llvm.access.group [[ACC_GRP20]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP20]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1582,14 +1582,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1597,12 +1597,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1635,7 +1635,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1671,12 +1671,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1711,7 +1711,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1736,8 +1736,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1745,7 +1745,7 @@ int main() { // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1776,7 +1776,7 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] @@ -1792,14 +1792,14 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: @@ -1814,7 +1814,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1823,7 +1823,7 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1839,7 +1839,7 @@ int main() { // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1872,7 +1872,7 @@ int main() { // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]], !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1884,29 +1884,29 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done11: // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK5: arraydestroy.body13: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5: arraydestroy.done17: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP11]] // @@ -1925,7 +1925,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1974,12 +1974,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -2012,7 +2012,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2048,12 +2048,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2088,7 +2088,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -2113,8 +2113,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -2122,7 +2122,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2151,7 +2151,7 @@ int main() { // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] @@ -2167,14 +2167,14 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: @@ -2189,7 +2189,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2198,7 +2198,7 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -2214,7 +2214,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -2245,7 +2245,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]], !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2257,29 +2257,29 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done10: // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] // CHECK7: arraydestroy.body12: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK7: arraydestroy.done16: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP11]] // @@ -2298,7 +2298,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2347,12 +2347,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2385,7 +2385,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2421,12 +2421,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -2444,7 +2444,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2483,7 +2483,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2735,12 +2735,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // @@ -2775,7 +2775,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -2814,7 +2814,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_private_codegen.cpp index 9d35ca12353ee..6fb23e3cd0250 100644 --- a/clang/test/OpenMP/teams_distribute_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_private_codegen.cpp @@ -141,12 +141,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -164,7 +164,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -203,7 +203,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -299,8 +299,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -309,7 +309,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -356,7 +356,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -376,14 +376,14 @@ int main() { // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -397,7 +397,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -444,17 +444,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -503,8 +503,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -514,7 +514,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -560,10 +560,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -579,14 +579,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -594,12 +594,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -632,7 +632,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -668,12 +668,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -691,7 +691,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -730,7 +730,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -826,8 +826,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -836,7 +836,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -881,7 +881,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -901,14 +901,14 @@ int main() { // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -922,7 +922,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -969,17 +969,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1028,8 +1028,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1039,7 +1039,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1084,9 +1084,9 @@ int main() { // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1102,14 +1102,14 @@ int main() { // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1117,12 +1117,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1155,7 +1155,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1191,12 +1191,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -1214,7 +1214,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1253,7 +1253,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -1360,13 +1360,13 @@ int main() { // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp index c06f90342dc46..1d22ee28de0b8 100644 --- a/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp @@ -161,12 +161,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -184,7 +184,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -223,7 +223,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -387,9 +387,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK1-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -407,7 +407,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -416,7 +416,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -424,7 +424,7 @@ int main() { // CHECK1: omp.arraycpy.done3: // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -461,7 +461,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] @@ -488,14 +488,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done12: @@ -528,12 +528,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -544,7 +544,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -628,17 +628,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP36]] // @@ -679,7 +679,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -752,9 +752,9 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK1-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK1-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -773,7 +773,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK1-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -782,7 +782,7 @@ int main() { // CHECK1-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK1-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK1-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -791,7 +791,7 @@ int main() { // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -830,7 +830,7 @@ int main() { // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -853,14 +853,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done13: @@ -883,12 +883,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -942,7 +942,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -978,12 +978,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1001,7 +1001,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1040,7 +1040,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -1204,9 +1204,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK3-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1224,7 +1224,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1233,7 +1233,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1241,7 +1241,7 @@ int main() { // CHECK3: omp.arraycpy.done3: // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK3-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) @@ -1276,7 +1276,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] @@ -1303,14 +1303,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done11: @@ -1343,12 +1343,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1359,7 +1359,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1443,17 +1443,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP36]] // @@ -1494,7 +1494,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1567,9 +1567,9 @@ int main() { // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC2:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR3:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 // CHECK3-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK3-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1588,7 +1588,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK3-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1597,7 +1597,7 @@ int main() { // CHECK3-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]] // CHECK3-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK3-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1606,7 +1606,7 @@ int main() { // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) // CHECK3-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]]) -// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK3-NEXT: store ptr [[VAR5]], ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 @@ -1643,7 +1643,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1666,14 +1666,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR3]], i32 0, i32 0 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP22]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done12: @@ -1696,12 +1696,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1755,7 +1755,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1791,12 +1791,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1831,7 +1831,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1878,7 +1878,7 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr @s_arr, i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] @@ -1905,7 +1905,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1949,7 +1949,7 @@ int main() { // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META6]], !align [[META7]], !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP9]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1962,17 +1962,17 @@ int main() { // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP13]] // @@ -1991,7 +1991,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2040,12 +2040,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -2078,7 +2078,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2114,12 +2114,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2154,7 +2154,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -2199,7 +2199,7 @@ int main() { // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S:%.*]]], ptr @s_arr, i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] @@ -2226,7 +2226,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2268,7 +2268,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP9]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2281,17 +2281,17 @@ int main() { // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP12]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP13]] // @@ -2310,7 +2310,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2359,12 +2359,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -2397,7 +2397,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2433,12 +2433,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -2456,7 +2456,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2495,7 +2495,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2681,12 +2681,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // @@ -2721,7 +2721,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -2760,7 +2760,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp index 57bb81c916ab9..3bb8a24b32981 100644 --- a/clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp @@ -503,7 +503,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -601,17 +601,17 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP41]] // @@ -681,8 +681,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -703,7 +703,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -753,7 +753,7 @@ int main() { // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -783,7 +783,7 @@ int main() { // CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP25]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP26]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -802,14 +802,14 @@ int main() { // CHECK9-NEXT: store i32 [[TMP28]], ptr [[TMP4]], align 4 // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN14]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done15: @@ -817,12 +817,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -833,7 +833,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 @@ -917,17 +917,17 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done2: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP36]] // @@ -958,7 +958,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1028,8 +1028,8 @@ int main() { // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK9-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK9-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -1047,7 +1047,7 @@ int main() { // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -1097,7 +1097,7 @@ int main() { // CHECK9-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7]], !align [[META8]], !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1127,7 +1127,7 @@ int main() { // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: store i32 [[TMP24]], ptr [[TMP1]], align 4 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP25]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1144,14 +1144,14 @@ int main() { // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[TMP26]], i64 4, i1 false) // CHECK9-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK9: .omp.lastprivate.done: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done14: @@ -1159,12 +1159,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1194,7 +1194,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1211,7 +1211,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1309,17 +1309,17 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP40]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP41:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP41]] // @@ -1389,8 +1389,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SVAR7:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1411,7 +1411,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1459,7 +1459,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1489,7 +1489,7 @@ int main() { // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP25]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP26]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1508,14 +1508,14 @@ int main() { // CHECK11-NEXT: store i32 [[TMP28]], ptr [[TMP4]], align 4 // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP29]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done14: @@ -1523,12 +1523,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1539,7 +1539,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 @@ -1623,17 +1623,17 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done2: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP36]] // @@ -1664,7 +1664,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1734,8 +1734,8 @@ int main() { // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK11-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK11-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1753,7 +1753,7 @@ int main() { // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1801,7 +1801,7 @@ int main() { // CHECK11-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8]], !align [[META9]], !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP16]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1831,7 +1831,7 @@ int main() { // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: store i32 [[TMP24]], ptr [[TMP1]], align 4 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[TMP2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP25]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1848,14 +1848,14 @@ int main() { // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP4]], ptr align 4 [[TMP26]], i32 4, i1 false) // CHECK11-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // CHECK11: .omp.lastprivate.done: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done13: @@ -1863,12 +1863,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1898,7 +1898,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1915,7 +1915,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1926,7 +1926,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -1949,7 +1949,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -1983,7 +1983,7 @@ int main() { // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP4]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1998,7 +1998,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK13-NEXT: store i32 [[TMP13]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP14]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2015,30 +2015,30 @@ int main() { // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK13-NEXT: store i32 [[TMP16]], ptr @_ZZ4mainE4svar, align 4 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3:[0-9]+]] +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN16:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN16]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY17:%.*]] // CHECK13: arraydestroy.body17: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAY_BEGIN16]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17]] // CHECK13: arraydestroy.done21: -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP19]] // @@ -2067,12 +2067,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2083,7 +2083,7 @@ int main() { // CHECK13-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -2094,7 +2094,7 @@ int main() { // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK13-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK13-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK13-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK13-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2113,7 +2113,7 @@ int main() { // CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK13-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK13: arrayctor.loop: @@ -2147,7 +2147,7 @@ int main() { // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP7]], align 8, !nonnull [[META2]], !align [[META3]], !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2162,7 +2162,7 @@ int main() { // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK13-NEXT: store i32 [[TMP13]], ptr [[T_VAR]], align 4 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i64 8, i1 false) -// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i64 2 // CHECK13-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP14]] // CHECK13-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2177,29 +2177,29 @@ int main() { // CHECK13: omp.arraycpy.done12: // CHECK13-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP4]], ptr align 4 [[TMP15]], i64 4, i1 false) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3]] -// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3]] +// CHECK13-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_ARRAYCPY_DONE12]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK13: arraydestroy.done14: // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN15]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] // CHECK13: arraydestroy.body16: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP17]], [[ARRAYDESTROY_DONE14]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] // CHECK13-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK13: arraydestroy.done20: -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK13-NEXT: ret i32 [[TMP18]] // @@ -2216,7 +2216,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2262,12 +2262,12 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK13-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK13-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK13-NEXT: ret void // // @@ -2297,7 +2297,7 @@ int main() { // // // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK13-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2314,7 +2314,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2325,7 +2325,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK15-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[SVAR:%.*]] = alloca i32, align 4 @@ -2348,7 +2348,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2380,7 +2380,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2395,7 +2395,7 @@ int main() { // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK15-NEXT: store i32 [[TMP13]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP14]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2412,30 +2412,30 @@ int main() { // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP4]], ptr align 4 [[TMP15]], i32 4, i1 false) // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[SVAR]], align 4 // CHECK15-NEXT: store i32 [[TMP16]], ptr @_ZZ4mainE4svar, align 4 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3:[0-9]+]] +// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done13: // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY16:%.*]] // CHECK15: arraydestroy.body16: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST17:%.*]] = phi ptr [ [[TMP18]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT18:%.*]], [[ARRAYDESTROY_BODY16]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT18]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST17]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT18]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE19:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT18]], [[ARRAY_BEGIN15]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_DONE20:%.*]], label [[ARRAYDESTROY_BODY16]] // CHECK15: arraydestroy.done20: -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP19]] // @@ -2464,12 +2464,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2480,7 +2480,7 @@ int main() { // CHECK15-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[TMP:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -2491,7 +2491,7 @@ int main() { // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 // CHECK15-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK15-NEXT: [[S_ARR5:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK15-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK15-NEXT: [[_TMP7:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -2510,7 +2510,7 @@ int main() { // CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK15-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK15: arrayctor.loop: @@ -2542,7 +2542,7 @@ int main() { // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP7]], align 4, !nonnull [[META3]], !align [[META4]], !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2557,7 +2557,7 @@ int main() { // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK15-NEXT: store i32 [[TMP13]], ptr [[T_VAR]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 [[VEC4]], i32 8, i1 false) -// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2 // CHECK15-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP14]] // CHECK15-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -2572,29 +2572,29 @@ int main() { // CHECK15: omp.arraycpy.done11: // CHECK15-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP4]], ptr align 4 [[TMP15]], i32 4, i1 false) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR3]] -// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0 +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR6]]) #[[ATTR3]] +// CHECK15-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR5]], i32 0, i32 0 // CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_ARRAYCPY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK15: arraydestroy.done13: // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK15-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY15:%.*]] // CHECK15: arraydestroy.body15: // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP17]], [[ARRAYDESTROY_DONE13]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAY_BEGIN14]] // CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15]] // CHECK15: arraydestroy.done19: -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR3]] // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK15-NEXT: ret i32 [[TMP18]] // @@ -2611,7 +2611,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -2657,12 +2657,12 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK15-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK15-NEXT: ret void // // @@ -2692,7 +2692,7 @@ int main() { // // // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp b/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp index f9f5926e25462..902e1adff26d0 100644 --- a/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp +++ b/clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp @@ -142,12 +142,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -165,7 +165,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -204,7 +204,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -300,8 +300,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -310,7 +310,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -357,7 +357,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP7]] @@ -384,14 +384,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -405,7 +405,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -452,17 +452,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -511,8 +511,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -522,7 +522,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -571,7 +571,7 @@ int main() { // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META14:![0-9]+]], !align [[META15:![0-9]+]], !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -594,14 +594,14 @@ int main() { // CHECK1-NEXT: store i32 2, ptr [[I]], align 4 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK1: .omp.final.done: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -609,12 +609,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -647,7 +647,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -683,12 +683,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -706,7 +706,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -745,7 +745,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -841,8 +841,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -851,7 +851,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -896,7 +896,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP8]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP8]] @@ -923,14 +923,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -944,7 +944,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -991,17 +991,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1050,8 +1050,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1061,7 +1061,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1108,7 +1108,7 @@ int main() { // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META15:![0-9]+]], !align [[META16:![0-9]+]], !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1131,14 +1131,14 @@ int main() { // CHECK3-NEXT: store i32 2, ptr [[I]], align 4 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] // CHECK3: .omp.final.done: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1146,12 +1146,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1184,7 +1184,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1220,12 +1220,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1260,7 +1260,7 @@ int main() { // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done1: @@ -1285,8 +1285,8 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK5-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1294,7 +1294,7 @@ int main() { // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1325,7 +1325,7 @@ int main() { // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] @@ -1341,14 +1341,14 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK5-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done6: @@ -1363,7 +1363,7 @@ int main() { // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -1372,7 +1372,7 @@ int main() { // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1388,7 +1388,7 @@ int main() { // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK5: arrayctor.loop: @@ -1421,7 +1421,7 @@ int main() { // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]], !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1433,29 +1433,29 @@ int main() { // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK5: arraydestroy.body: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK5: arraydestroy.done11: // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY13:%.*]] // CHECK5: arraydestroy.body13: // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ] // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1 -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]] // CHECK5-NEXT: [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]] // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]] // CHECK5: arraydestroy.done17: -// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK5-NEXT: ret i32 [[TMP11]] // @@ -1474,7 +1474,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1523,12 +1523,12 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK5-NEXT: ret void // // @@ -1561,7 +1561,7 @@ int main() { // // // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK5-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK5-NEXT: entry: // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1597,12 +1597,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -1637,7 +1637,7 @@ int main() { // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done1: @@ -1662,8 +1662,8 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK7-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK7-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1671,7 +1671,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -1700,7 +1700,7 @@ int main() { // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] @@ -1716,14 +1716,14 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK7-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done5: @@ -1738,7 +1738,7 @@ int main() { // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -1747,7 +1747,7 @@ int main() { // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4 -// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 @@ -1763,7 +1763,7 @@ int main() { // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK7: arrayctor.loop: @@ -1794,7 +1794,7 @@ int main() { // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]], !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1806,29 +1806,29 @@ int main() { // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] // CHECK7: omp.inner.for.end: // CHECK7-NEXT: store i32 2, ptr [[I]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] -// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0 +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR5]]) #[[ATTR2]] +// CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR4]], i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK7: arraydestroy.body: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK7: arraydestroy.done10: // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY12:%.*]] // CHECK7: arraydestroy.body12: // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ] // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1 -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]] // CHECK7-NEXT: [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]] // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]] // CHECK7: arraydestroy.done16: -// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK7-NEXT: ret i32 [[TMP11]] // @@ -1847,7 +1847,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1896,12 +1896,12 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK7-NEXT: ret void // // @@ -1934,7 +1934,7 @@ int main() { // // // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK7-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK7-NEXT: entry: // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1970,12 +1970,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -1993,7 +1993,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2032,7 +2032,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -2200,12 +2200,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK11-NEXT: ret void // // @@ -2240,7 +2240,7 @@ int main() { // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: @@ -2279,7 +2279,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 diff --git a/clang/test/OpenMP/teams_firstprivate_codegen.cpp b/clang/test/OpenMP/teams_firstprivate_codegen.cpp index fec8fcb78f91e..70face99374cc 100644 --- a/clang/test/OpenMP/teams_firstprivate_codegen.cpp +++ b/clang/test/OpenMP/teams_firstprivate_codegen.cpp @@ -266,7 +266,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[SIVAR_CASTED:%.*]] = alloca i64, align 8 @@ -404,18 +404,18 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9: omp_offload.cont7: // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP58]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP59:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP59]] // @@ -482,9 +482,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -497,7 +497,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META11]], !align [[META12]] // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META11]], !align [[META12]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -506,7 +506,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -514,21 +514,21 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9: omp.arraycpy.done3: // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false) // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -561,22 +561,22 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -612,7 +612,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8 @@ -738,18 +738,18 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK9: omp_offload.cont7: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP53]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP54:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP54]] // @@ -820,7 +820,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -829,7 +829,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -892,9 +892,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK9-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 // CHECK9-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK9-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK9-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -906,7 +906,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8, !nonnull [[META11]], !align [[META12]] // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8, !nonnull [[META11]], !align [[META12]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i64 8, i1 false) -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -915,7 +915,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -923,20 +923,20 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK9: omp.arraycpy.done3: // CHECK9-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) -// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done8: @@ -959,12 +959,12 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1043,7 +1043,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1058,7 +1058,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[SIVAR_CASTED:%.*]] = alloca i32, align 4 @@ -1196,18 +1196,18 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11: omp_offload.cont7: // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP58]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done8: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP59:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP59]] // @@ -1274,9 +1274,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 @@ -1289,7 +1289,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META12]], !align [[META13]] // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META12]], !align [[META13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1298,7 +1298,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1306,21 +1306,21 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11: omp.arraycpy.done3: // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) -// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK11-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done8: @@ -1353,22 +1353,22 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD1Ev -// CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN2StD2Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1404,7 +1404,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4 @@ -1530,18 +1530,18 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT7]] // CHECK11: omp_offload.cont7: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP53]], [[OMP_OFFLOAD_CONT7]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done8: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP54:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP54]] // @@ -1612,7 +1612,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN2StD2Ev -// CHECK11-SAME: (ptr nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1621,7 +1621,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1684,9 +1684,9 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[VEC1:%.*]] = alloca [2 x i32], align 128 -// CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK11-NEXT: [[S_ARR2:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 // CHECK11-NEXT: [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4 -// CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK11-NEXT: [[VAR4:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK11-NEXT: [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 @@ -1698,7 +1698,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4, !nonnull [[META12]], !align [[META13]] // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4, !nonnull [[META12]], !align [[META13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[VEC1]], ptr align 128 [[TMP0]], i32 8, i1 false) -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] @@ -1707,7 +1707,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr [[AGG_TMP]]) -// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP]]) #[[ATTR4]] // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] @@ -1715,20 +1715,20 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // CHECK11: omp.arraycpy.done3: // CHECK11-NEXT: call void @_ZN2StC1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) -// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dead_on_return(8) dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR4]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR2]], i32 0, i32 0 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[OMP_ARRAYCPY_DONE3]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done8: @@ -1751,12 +1751,12 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1835,7 +1835,7 @@ void array_func(float a[3], St s[2], int n, long double vla1[n]) { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp index f892dad0f69ba..4166122f62e8a 100644 --- a/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp @@ -161,12 +161,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -184,7 +184,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -223,7 +223,7 @@ int main() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -319,8 +319,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -329,7 +329,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -376,7 +376,7 @@ int main() { // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -396,14 +396,14 @@ int main() { // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done7: @@ -417,7 +417,7 @@ int main() { // CHECK1-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK1-NEXT: [[VAR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 @@ -464,17 +464,17 @@ int main() { // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done2: -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK1-NEXT: ret i32 [[TMP16]] // @@ -523,8 +523,8 @@ int main() { // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 @@ -534,7 +534,7 @@ int main() { // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK1: arrayctor.loop: @@ -580,10 +580,10 @@ int main() { // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META9:![0-9]+]], !align [[META10:![0-9]+]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -599,14 +599,14 @@ int main() { // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done8: @@ -614,12 +614,12 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK1-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK1-NEXT: ret void // // @@ -652,7 +652,7 @@ int main() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -688,12 +688,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -711,7 +711,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -750,7 +750,7 @@ int main() { // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done1: @@ -846,8 +846,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -856,7 +856,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -901,7 +901,7 @@ int main() { // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -921,14 +921,14 @@ int main() { // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done6: @@ -942,7 +942,7 @@ int main() { // CHECK3-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 4 // CHECK3-NEXT: [[VAR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 @@ -989,17 +989,17 @@ int main() { // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done2: -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR2]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK3-NEXT: ret i32 [[TMP16]] // @@ -1048,8 +1048,8 @@ int main() { // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 +// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 4 +// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 4 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 @@ -1059,7 +1059,7 @@ int main() { // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK3: arrayctor.loop: @@ -1104,9 +1104,9 @@ int main() { // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !nonnull [[META10:![0-9]+]], !align [[META11:![0-9]+]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1122,14 +1122,14 @@ int main() { // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR2]] +// CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] // CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK3: arraydestroy.done7: @@ -1137,12 +1137,12 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK3-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK3-NEXT: ret void // // @@ -1175,7 +1175,7 @@ int main() { // // // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1211,12 +1211,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2]] // CHECK9-NEXT: ret void // // @@ -1234,7 +1234,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1273,7 +1273,7 @@ int main() { // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: @@ -1380,13 +1380,13 @@ int main() { // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5:![0-9]+]], !align [[META6:![0-9]+]] // CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !nonnull [[META5]], !align [[META6]] // CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 diff --git a/clang/test/OpenMP/teams_private_codegen.cpp b/clang/test/OpenMP/teams_private_codegen.cpp index d801e22ddb2ad..2453b0d8bd660 100644 --- a/clang/test/OpenMP/teams_private_codegen.cpp +++ b/clang/test/OpenMP/teams_private_codegen.cpp @@ -208,7 +208,7 @@ int main() { // CHECK1-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK1-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK1-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META7:![0-9]+]], !align [[META8:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP1]], align 8 @@ -285,12 +285,12 @@ int main() { // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 8 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP4]], align 8 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8 // CHECK1-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]]) // CHECK1-NEXT: ret void @@ -305,17 +305,17 @@ int main() { // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8 +// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8 +// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK1-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK1-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 +// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8, !nonnull [[META7]], !align [[META8]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 @@ -394,7 +394,7 @@ int main() { // CHECK3-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK3-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK3-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4 +// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META8:![0-9]+]], !align [[META9:![0-9]+]] // CHECK3-NEXT: store ptr [[TMP0]], ptr [[C]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP1]], align 4 @@ -471,12 +471,12 @@ int main() { // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP1]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP4]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 4 // CHECK3-NEXT: call void @_ZZN2SSC1ERiENKUlvE_clEv(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]]) // CHECK3-NEXT: ret void @@ -491,17 +491,17 @@ int main() { // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP0]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 1 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4 +// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP2]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 // CHECK3-NEXT: [[INC:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: store i32 [[INC]], ptr [[TMP3]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 2 -// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4 +// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[TMP5]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4 // CHECK3-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP7]], -1 // CHECK3-NEXT: store i32 [[DEC]], ptr [[TMP6]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw [[CLASS_ANON_0]], ptr [[THIS1]], i32 0, i32 3 -// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 4, !nonnull [[META8]], !align [[META9]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 1 // CHECK3-NEXT: store i32 [[DIV]], ptr [[TMP9]], align 4 @@ -543,7 +543,7 @@ int main() { // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -590,18 +590,18 @@ int main() { // CHECK9: omp_offload.cont: // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v() // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP16]] // @@ -656,12 +656,12 @@ int main() { // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -675,17 +675,17 @@ int main() { // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK9-NEXT: store i32 3, ptr [[SIVAR]], align 4 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: @@ -693,12 +693,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -710,7 +710,7 @@ int main() { // CHECK9-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -755,18 +755,18 @@ int main() { // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK9: omp_offload.cont: // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done1: -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK9-NEXT: ret i32 [[TMP16]] // @@ -791,7 +791,7 @@ int main() { // CHECK9-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK9-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK9-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8 +// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !nonnull [[META13:![0-9]+]], !align [[META14:![0-9]+]] // CHECK9-NEXT: store ptr [[TMP0]], ptr [[C]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK9-NEXT: store ptr [[THIS1]], ptr [[TMP1]], align 8 @@ -864,14 +864,14 @@ int main() { // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[A]], ptr [[TMP]], align 8 // CHECK9-NEXT: store ptr [[C]], ptr [[_TMP1]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK9-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 // CHECK9-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 // CHECK9-NEXT: store i32 [[DEC]], ptr [[B]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8 +// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 // CHECK9-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 @@ -904,7 +904,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -959,11 +959,11 @@ int main() { // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 +// CHECK9-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK9-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK9: arrayctor.loop: @@ -977,16 +977,16 @@ int main() { // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX1]], ptr align 128 [[VAR]], i64 4, i1 false) -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN2]], i64 2 // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK9: arraydestroy.body: // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK9: arraydestroy.done3: @@ -994,12 +994,12 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK9-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK9-NEXT: ret void // // @@ -1093,7 +1093,7 @@ int main() { // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 // CHECK9-NEXT: store ptr [[A]], ptr [[TMP]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 +// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8, !nonnull [[META13]], !align [[META14]] // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK9-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 @@ -1115,7 +1115,7 @@ int main() { // // // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { +// CHECK9-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1131,7 +1131,7 @@ int main() { // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S]]], align 4 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 @@ -1178,18 +1178,18 @@ int main() { // CHECK11: omp_offload.cont: // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v() // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP16]] // @@ -1244,12 +1244,12 @@ int main() { // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S:%.*]]], align 4 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S]], align 4 // CHECK11-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1263,17 +1263,17 @@ int main() { // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK11-NEXT: store i32 3, ptr [[SIVAR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done3: @@ -1281,12 +1281,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1298,7 +1298,7 @@ int main() { // CHECK11-NEXT: [[SST:%.*]] = alloca [[STRUCT_SST:%.*]], align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0]]], align 128 // CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) @@ -1343,18 +1343,18 @@ int main() { // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK11: omp_offload.cont: // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done1: -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TEST]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK11-NEXT: ret i32 [[TMP16]] // @@ -1379,7 +1379,7 @@ int main() { // CHECK11-NEXT: [[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 0 // CHECK11-NEXT: store i8 [[BF_SET]], ptr [[B]], align 4 // CHECK11-NEXT: [[C:%.*]] = getelementptr inbounds nuw [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 2 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4 +// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4, !nonnull [[META14:![0-9]+]], !align [[META15:![0-9]+]] // CHECK11-NEXT: store ptr [[TMP0]], ptr [[C]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK11-NEXT: store ptr [[THIS1]], ptr [[TMP1]], align 4 @@ -1452,14 +1452,14 @@ int main() { // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: store ptr [[A]], ptr [[TMP]], align 4 // CHECK11-NEXT: store ptr [[C]], ptr [[_TMP1]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META14]], !align [[META15]] // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK11-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[B]], align 4 // CHECK11-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP3]], -1 // CHECK11-NEXT: store i32 [[DEC]], ptr [[B]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 4 +// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[_TMP1]], align 4, !nonnull [[META14]], !align [[META15]] // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP5]], 1 // CHECK11-NEXT: store i32 [[DIV]], ptr [[TMP4]], align 4 @@ -1492,7 +1492,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 @@ -1547,11 +1547,11 @@ int main() { // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 128 // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 128 -// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 128 -// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 128 +// CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x [[STRUCT_S_0:%.*]]], align 128 +// CHECK11-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0]], align 128 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 // CHECK11-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] // CHECK11: arrayctor.loop: @@ -1565,16 +1565,16 @@ int main() { // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 128 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX1]], ptr align 128 [[VAR]], i32 4, i1 false) -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[VAR]]) #[[ATTR4]] +// CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x [[STRUCT_S_0]]], ptr [[S_ARR]], i32 0, i32 0 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN2]], i32 2 // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK11: arraydestroy.body: // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ARRAYCTOR_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK11: arraydestroy.done3: @@ -1582,12 +1582,12 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK11-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK11-NEXT: ret void // // @@ -1681,7 +1681,7 @@ int main() { // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 // CHECK11-NEXT: store ptr [[A]], ptr [[TMP]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4 +// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 4, !nonnull [[META14]], !align [[META15]] // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK11-NEXT: [[INC:%.*]] = add nsw i32 [[TMP2]], 1 // CHECK11-NEXT: store i32 [[INC]], ptr [[TMP1]], align 4 @@ -1703,7 +1703,7 @@ int main() { // // // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev -// CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK11-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK11-NEXT: entry: // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 diff --git a/clang/test/OpenMP/threadprivate_codegen.cpp b/clang/test/OpenMP/threadprivate_codegen.cpp index 154c5f45642a4..91e5bff3fd55f 100644 --- a/clang/test/OpenMP/threadprivate_codegen.cpp +++ b/clang/test/OpenMP/threadprivate_codegen.cpp @@ -1001,17 +1001,17 @@ int foobar() { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -1049,7 +1049,7 @@ int foobar() { // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT3]], i32 noundef 3) // CHECK1-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont4: -// CHECK1-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 1 +// CHECK1-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP1]], i64 1 // CHECK1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8 // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT6]], i32 noundef 4) @@ -1080,7 +1080,7 @@ int foobar() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done5: @@ -1098,21 +1098,21 @@ int foobar() { // CHECK1: arraydestroy.body15: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]] // CHECK1: arraydestroy.done19: // CHECK1-NEXT: br label [[EHCLEANUP]] // CHECK1: ehcleanup: // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK1-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 0, i64 0 -// CHECK1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0 +// CHECK1-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP1]], i64 0, i64 0 +// CHECK1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP11]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]] // CHECK1: arraydestroy.body21: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]] // CHECK1: arraydestroy.done25: @@ -1136,7 +1136,7 @@ int foobar() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -1174,7 +1174,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1206,12 +1206,12 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -1230,7 +1230,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1261,17 +1261,17 @@ int foobar() { // CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) // CHECK1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK1: invoke.cont3: -// CHECK1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) +// CHECK1-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 +// CHECK1-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) // CHECK1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // CHECK1: invoke.cont7: -// CHECK1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// CHECK1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) // CHECK1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // CHECK1: invoke.cont8: -// CHECK1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// CHECK1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) // CHECK1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // CHECK1: invoke.cont9: // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] @@ -1289,7 +1289,7 @@ int foobar() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done4: @@ -1302,25 +1302,25 @@ int foobar() { // CHECK1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] +// CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] // CHECK1: arraydestroy.body11: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// CHECK1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1) // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // CHECK1: arraydestroy.done15: // CHECK1-NEXT: br label [[EHCLEANUP]] // CHECK1: ehcleanup: // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 +// CHECK1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] // CHECK1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] // CHECK1: arraydestroy.body17: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK1: arraydestroy.done21: @@ -1342,7 +1342,7 @@ int foobar() { // CHECK1: arraydestroy.body: // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK1: arraydestroy.done1: @@ -1405,8 +1405,8 @@ int foobar() { // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] // CHECK1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP20]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1 // CHECK1-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 @@ -1482,17 +1482,17 @@ int foobar() { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[TMP1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -1511,7 +1511,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1547,8 +1547,8 @@ int foobar() { // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] // CHECK1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP11]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1 // CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4 @@ -1622,17 +1622,17 @@ int foobar() { // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[TMP1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK1-NEXT: ret void // // @@ -1651,7 +1651,7 @@ int foobar() { // // // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -1694,12 +1694,12 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1720,7 +1720,7 @@ int foobar() { // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1754,12 +1754,12 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -1784,17 +1784,17 @@ int foobar() { // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) // CHECK2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont3: -// CHECK2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) +// CHECK2-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 +// CHECK2-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) // CHECK2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // CHECK2: invoke.cont7: -// CHECK2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// CHECK2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) // CHECK2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // CHECK2: invoke.cont8: -// CHECK2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// CHECK2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) // CHECK2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // CHECK2: invoke.cont9: // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] @@ -1812,7 +1812,7 @@ int foobar() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done4: @@ -1825,25 +1825,25 @@ int foobar() { // CHECK2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // CHECK2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 // CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] +// CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] // CHECK2: arraydestroy.body11: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] -// CHECK2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// CHECK2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1) // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // CHECK2: arraydestroy.done15: // CHECK2-NEXT: br label [[EHCLEANUP]] // CHECK2: ehcleanup: // CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 +// CHECK2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0 // CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] // CHECK2: arraydestroy.body17: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK2: arraydestroy.done21: @@ -1865,7 +1865,7 @@ int foobar() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -1898,7 +1898,7 @@ int foobar() { // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT3]], i32 noundef 3) // CHECK2-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]] // CHECK2: invoke.cont4: -// CHECK2-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 1 +// CHECK2-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP1]], i64 1 // CHECK2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8 // CHECK2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8 // CHECK2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT6]], i32 noundef 4) @@ -1929,7 +1929,7 @@ int foobar() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done5: @@ -1947,21 +1947,21 @@ int foobar() { // CHECK2: arraydestroy.body15: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]] // CHECK2: arraydestroy.done19: // CHECK2-NEXT: br label [[EHCLEANUP]] // CHECK2: ehcleanup: // CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK2-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 0, i64 0 -// CHECK2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0 +// CHECK2-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP1]], i64 0, i64 0 +// CHECK2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP11]], i64 0, i64 0 // CHECK2-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]] // CHECK2: arraydestroy.body21: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]] // CHECK2: arraydestroy.done25: @@ -1985,7 +1985,7 @@ int foobar() { // CHECK2: arraydestroy.body: // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]] // CHECK2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK2: arraydestroy.done1: @@ -2056,8 +2056,8 @@ int foobar() { // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] // CHECK2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1 -// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP20]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1 // CHECK2-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 @@ -2133,17 +2133,17 @@ int foobar() { // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[TMP1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -2173,8 +2173,8 @@ int foobar() { // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] // CHECK2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1 -// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP11]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1 // CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4 @@ -2248,17 +2248,17 @@ int foobar() { // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[TMP1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK2-NEXT: ret void // // @@ -2277,7 +2277,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2302,7 +2302,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2327,7 +2327,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2352,7 +2352,7 @@ int foobar() { // // // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK2-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2395,12 +2395,12 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// SIMD1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // SIMD1-NEXT: ret void // // @@ -2426,12 +2426,12 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]] // SIMD1-NEXT: ret void // // @@ -2456,17 +2456,17 @@ int foobar() { // SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) // SIMD1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // SIMD1: invoke.cont3: -// SIMD1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// SIMD1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) +// SIMD1-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 +// SIMD1-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) // SIMD1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // SIMD1: invoke.cont7: -// SIMD1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// SIMD1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) // SIMD1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // SIMD1: invoke.cont8: -// SIMD1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// SIMD1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// SIMD1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) // SIMD1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // SIMD1: invoke.cont9: // SIMD1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] @@ -2484,7 +2484,7 @@ int foobar() { // SIMD1: arraydestroy.body: // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // SIMD1: arraydestroy.done4: @@ -2497,25 +2497,25 @@ int foobar() { // SIMD1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // SIMD1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 // SIMD1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] +// SIMD1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]] // SIMD1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] // SIMD1: arraydestroy.body11: // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] -// SIMD1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) +// SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// SIMD1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1) // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // SIMD1: arraydestroy.done15: // SIMD1-NEXT: br label [[EHCLEANUP]] // SIMD1: ehcleanup: // SIMD1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// SIMD1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 +// SIMD1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0 // SIMD1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] // SIMD1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] // SIMD1: arraydestroy.body17: // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // SIMD1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // SIMD1: arraydestroy.done21: @@ -2537,7 +2537,7 @@ int foobar() { // SIMD1: arraydestroy.body: // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // SIMD1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD1: arraydestroy.done1: @@ -2586,7 +2586,7 @@ int foobar() { // SIMD1-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 // SIMD1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] // SIMD1-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4 -// SIMD1-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 +// SIMD1-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x [[STRUCT_S1:%.*]]], ptr getelementptr inbounds ([2 x [3 x [[STRUCT_S1]]]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 // SIMD1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4 // SIMD1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] // SIMD1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 @@ -2636,12 +2636,12 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // SIMD1-NEXT: ret void // // @@ -2663,7 +2663,7 @@ int foobar() { // SIMD1-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4 // SIMD1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] // SIMD1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 -// SIMD1-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 +// SIMD1-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x [[STRUCT_S1:%.*]]], ptr getelementptr inbounds ([2 x [3 x [[STRUCT_S1]]]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 // SIMD1-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4 // SIMD1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] // SIMD1-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4 @@ -2713,12 +2713,12 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// SIMD1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // SIMD1-NEXT: ret void // // @@ -2737,7 +2737,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2762,7 +2762,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2787,7 +2787,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2812,7 +2812,7 @@ int foobar() { // // // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD1-NEXT: entry: // SIMD1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -2845,168 +2845,168 @@ int foobar() { // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META123:![0-9]+]], !DIExpression(), [[META125:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META124:![0-9]+]], !DIExpression(), [[META126:![0-9]+]]) // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META126:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META127:![0-9]+]], !DIExpression(), [[META128:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG128]] -// SIMD2-NEXT: ret void, !dbg [[DBG129:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] +// SIMD2-NEXT: ret void, !dbg [[DBG130:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META132:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META133:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG133:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG134:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG135:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG135:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG136:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG136:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG139:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG137:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG139:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG140:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG140:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG141:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META141:![0-9]+]], !DIExpression(), [[META143:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META142:![0-9]+]], !DIExpression(), [[META144:![0-9]+]]) // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META145:![0-9]+]], !DIExpression(), [[META146:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG146]] -// SIMD2-NEXT: ret void, !dbg [[DBG147:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG147]] +// SIMD2-NEXT: ret void, !dbg [[DBG148:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG148:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG149:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META149:![0-9]+]], !DIExpression(), [[META150:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META150:![0-9]+]], !DIExpression(), [[META151:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG152:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG152:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG153:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// SIMD2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG153:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG154:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154:![0-9]+]] -// SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156:![0-9]+]] +// SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155:![0-9]+]] +// SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157:![0-9]+]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG157:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG158:![0-9]+]] // SIMD2: invoke.cont: -// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// SIMD2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG158:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] // SIMD2: invoke.cont2: -// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// SIMD2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG160:![0-9]+]] // SIMD2: invoke.cont3: -// SIMD2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160:![0-9]+]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// SIMD2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG161:![0-9]+]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161:![0-9]+]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) +// SIMD2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG162:![0-9]+]] // SIMD2: invoke.cont7: -// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// SIMD2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG162:![0-9]+]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// SIMD2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] // SIMD2: invoke.cont8: -// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// SIMD2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// SIMD2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG164:![0-9]+]] // SIMD2: invoke.cont9: -// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG164]] +// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG165:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG165]] // SIMD2: lpad: // SIMD2-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG165:![0-9]+]] -// SIMD2-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG165]] -// SIMD2-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG165]] -// SIMD2-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG156]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] +// SIMD2-NEXT: cleanup, !dbg [[DBG166:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG166]] +// SIMD2-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG166]] +// SIMD2-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG157]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]] // SIMD2: arraydestroy.body: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG156]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG157]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]] // SIMD2: arraydestroy.done4: -// SIMD2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG156]] +// SIMD2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG157]] // SIMD2: lpad6: // SIMD2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG165]] -// SIMD2-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG165]] -// SIMD2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG160]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG160]] +// SIMD2-NEXT: cleanup, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG166]] +// SIMD2-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG166]] +// SIMD2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG161]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG161]] // SIMD2: arraydestroy.body11: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG160]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG160]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG160]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG161]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), !dbg [[DBG161]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG161]] // SIMD2: arraydestroy.done15: -// SIMD2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG160]] +// SIMD2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG161]] // SIMD2: ehcleanup: -// SIMD2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG154]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG154]] +// SIMD2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG155]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG155]] // SIMD2: arraydestroy.body17: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG154]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG154]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG154]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG155]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG155]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG155]] // SIMD2: arraydestroy.done21: -// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG154]] +// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG155]] // SIMD2: eh.resume: -// SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG154]] -// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG154]] -// SIMD2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG154]] -// SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG154]] +// SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG155]] +// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG155]] +// SIMD2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG155]] +// SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG155]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// SIMD2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] { +// SIMD2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG167:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META170:![0-9]+]], !DIExpression(), [[META171:![0-9]+]]) -// SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META171]] +// SIMD2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META171:![0-9]+]], !DIExpression(), [[META172:![0-9]+]]) +// SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META172]] // SIMD2: arraydestroy.body: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META171]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META171]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META171]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META171]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META171]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META172]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META172]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META172]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META172]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META172]] // SIMD2: arraydestroy.done1: -// SIMD2-NEXT: ret void, !dbg [[META171]] +// SIMD2-NEXT: ret void, !dbg [[META172]] // // // SIMD2-LABEL: define {{[^@]+}}@main @@ -3017,302 +3017,302 @@ int foobar() { // SIMD2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[RES]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]]) -// SIMD2-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG174:![0-9]+]] -// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG174]], !prof [[PROF175:![0-9]+]] +// SIMD2-NEXT: #dbg_declare(ptr [[RES]], [[META173:![0-9]+]], !DIExpression(), [[META174:![0-9]+]]) +// SIMD2-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG175:![0-9]+]] +// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG175]], !prof [[PROF176:![0-9]+]] // SIMD2: init.check: -// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG174]] +// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG175]] // SIMD2: init: -// SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG176:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG177:![0-9]+]] // SIMD2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) -// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG177:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG178:![0-9]+]] // SIMD2: invoke.cont: -// SIMD2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG174]] +// SIMD2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG175]] // SIMD2: init.end: -// SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG178:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG179:![0-9]+]] -// SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG180:![0-9]+]] -// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG181:![0-9]+]] -// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG181]] -// SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG181]] -// SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG182:![0-9]+]] -// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG183:![0-9]+]] -// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG183]] -// SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG183]] -// SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG184:![0-9]+]] -// SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]] -// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG185]] -// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG185]] -// SIMD2-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG186:![0-9]+]] -// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]] -// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]] -// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG187]] -// SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG188:![0-9]+]] -// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG189:![0-9]+]] -// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]] -// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG189]] -// SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG190:![0-9]+]] -// SIMD2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG191:![0-9]+]] -// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG191]] -// SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG191]] -// SIMD2-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG192:![0-9]+]] -// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG192]] -// SIMD2-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG193:![0-9]+]] -// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG193]] -// SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG193]] -// SIMD2-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG194:![0-9]+]] -// SIMD2-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG195:![0-9]+]] -// SIMD2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG195]] -// SIMD2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG195]] -// SIMD2-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] -// SIMD2-NEXT: ret i32 [[TMP21]], !dbg [[DBG197:![0-9]+]] +// SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG179:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]] +// SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG181:![0-9]+]] +// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]] +// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG182]] +// SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG182]] +// SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG183:![0-9]+]] +// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG184:![0-9]+]] +// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG184]] +// SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG184]] +// SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG185:![0-9]+]] +// SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]] +// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG186]] +// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG186]] +// SIMD2-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG187:![0-9]+]] +// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG188:![0-9]+]] +// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG188]] +// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG188]] +// SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x [[STRUCT_S1:%.*]]], ptr getelementptr inbounds ([2 x [3 x [[STRUCT_S1]]]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG189:![0-9]+]] +// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG190:![0-9]+]] +// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG190]] +// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG190]] +// SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG191:![0-9]+]] +// SIMD2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG192:![0-9]+]] +// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG192]] +// SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG192]] +// SIMD2-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG193:![0-9]+]] +// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG193]] +// SIMD2-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG194:![0-9]+]] +// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG194]] +// SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG194]] +// SIMD2-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG195:![0-9]+]] +// SIMD2-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] +// SIMD2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG196]] +// SIMD2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG196]] +// SIMD2-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG197:![0-9]+]] +// SIMD2-NEXT: ret i32 [[TMP21]], !dbg [[DBG198:![0-9]+]] // SIMD2: lpad: // SIMD2-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG198:![0-9]+]] -// SIMD2-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG198]] -// SIMD2-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG198]] -// SIMD2-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG198]] -// SIMD2-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG198]] -// SIMD2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG174]] +// SIMD2-NEXT: cleanup, !dbg [[DBG199:![0-9]+]] +// SIMD2-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG199]] +// SIMD2-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG199]] +// SIMD2-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG199]] +// SIMD2-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG199]] +// SIMD2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG175]] // SIMD2: eh.resume: -// SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG174]] -// SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG174]] -// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG174]] -// SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG174]] +// SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG175]] +// SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG175]] +// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG175]] +// SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG175]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG199:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG200:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META200:![0-9]+]], !DIExpression(), [[META202:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META201:![0-9]+]], !DIExpression(), [[META203:![0-9]+]]) // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META203:![0-9]+]], !DIExpression(), [[META204:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] -// SIMD2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG205]] -// SIMD2-NEXT: ret void, !dbg [[DBG206:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]] +// SIMD2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG206]] +// SIMD2-NEXT: ret void, !dbg [[DBG207:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG207:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG208:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META208:![0-9]+]], !DIExpression(), [[META209:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META209:![0-9]+]], !DIExpression(), [[META210:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG210:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG211:![0-9]+]] +// SIMD2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG211:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG212:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_Z6foobarv -// SIMD2-SAME: () #[[ATTR2]] !dbg [[DBG212:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR2]] !dbg [[DBG213:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[RES:%.*]] = alloca i32, align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[RES]], [[META213:![0-9]+]], !DIExpression(), [[META214:![0-9]+]]) -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG215:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] -// SIMD2-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG217:![0-9]+]] -// SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] -// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG218]] -// SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG218]] -// SIMD2-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] -// SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG220]] -// SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG220]] -// SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG221:![0-9]+]] -// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG222:![0-9]+]] -// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]] -// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG222]] -// SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG223:![0-9]+]] -// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] -// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]] -// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG224]] -// SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG225:![0-9]+]] -// SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] -// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG226]] -// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG226]] -// SIMD2-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG227:![0-9]+]] -// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG227]] -// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] -// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG228]] -// SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG228]] -// SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG229:![0-9]+]] -// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG230]] -// SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG230]] -// SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] -// SIMD2-NEXT: ret i32 [[TMP15]], !dbg [[DBG232:![0-9]+]] +// SIMD2-NEXT: #dbg_declare(ptr [[RES]], [[META214:![0-9]+]], !DIExpression(), [[META215:![0-9]+]]) +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG216:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]] +// SIMD2-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG218:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]] +// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG219]] +// SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG219]] +// SIMD2-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]] +// SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG221]] +// SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG221]] +// SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG222:![0-9]+]] +// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] +// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG223]] +// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG223]] +// SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x [[STRUCT_S1:%.*]]], ptr getelementptr inbounds ([2 x [3 x [[STRUCT_S1]]]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG224:![0-9]+]] +// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]] +// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG225]] +// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG225]] +// SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG226:![0-9]+]] +// SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] +// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG227]] +// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG227]] +// SIMD2-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG228:![0-9]+]] +// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG228]] +// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]] +// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG229]] +// SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG229]] +// SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG230:![0-9]+]] +// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG231]] +// SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG231]] +// SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]] +// SIMD2-NEXT: ret i32 [[TMP15]], !dbg [[DBG233:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// SIMD2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG233:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG234:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234:![0-9]+]] -// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG234]] -// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG234]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235:![0-9]+]] +// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG235]] +// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG235]] // SIMD2: init.check: -// SIMD2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234]] -// SIMD2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG235:![0-9]+]] -// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG234]] -// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG234]] +// SIMD2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235]] +// SIMD2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG236:![0-9]+]] +// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG235]] +// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG235]] // SIMD2: init.end: -// SIMD2-NEXT: ret void, !dbg [[DBG237:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG238:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG238:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG239:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META239:![0-9]+]], !DIExpression(), [[META241:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META240:![0-9]+]], !DIExpression(), [[META242:![0-9]+]]) // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META243:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META243:![0-9]+]], !DIExpression(), [[META244:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG244:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG244]] -// SIMD2-NEXT: ret void, !dbg [[DBG245:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG245:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG245]] +// SIMD2-NEXT: ret void, !dbg [[DBG246:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG246:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG247:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META247:![0-9]+]], !DIExpression(), [[META248:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META248:![0-9]+]], !DIExpression(), [[META249:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG249:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG250:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG250:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG251:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG251:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG252:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META252:![0-9]+]], !DIExpression(), [[META253:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META253:![0-9]+]], !DIExpression(), [[META254:![0-9]+]]) // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META254:![0-9]+]], !DIExpression(), [[META255:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META255:![0-9]+]], !DIExpression(), [[META256:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG257:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG256]] -// SIMD2-NEXT: ret void, !dbg [[DBG258:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG258:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG257]] +// SIMD2-NEXT: ret void, !dbg [[DBG259:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG259:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG260:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META260:![0-9]+]], !DIExpression(), [[META261:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META261:![0-9]+]], !DIExpression(), [[META262:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] -// SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG264:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG265:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] +// SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG265:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG266:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG266:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG267:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META267:![0-9]+]], !DIExpression(), [[META268:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META268:![0-9]+]], !DIExpression(), [[META269:![0-9]+]]) // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META269:![0-9]+]], !DIExpression(), [[META270:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META270:![0-9]+]], !DIExpression(), [[META271:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG272:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG271]] -// SIMD2-NEXT: ret void, !dbg [[DBG273:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG273:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG272]] +// SIMD2-NEXT: ret void, !dbg [[DBG274:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG274:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG275:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META275:![0-9]+]], !DIExpression(), [[META276:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META276:![0-9]+]], !DIExpression(), [[META277:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] -// SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG279:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG280:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG278:![0-9]+]] +// SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG280:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG281:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG281:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG282:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META282:![0-9]+]], !DIExpression(), [[META283:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META283:![0-9]+]], !DIExpression(), [[META284:![0-9]+]]) // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META284:![0-9]+]], !DIExpression(), [[META285:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META285:![0-9]+]], !DIExpression(), [[META286:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG287:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG286]] -// SIMD2-NEXT: ret void, !dbg [[DBG288:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG288:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG287]] +// SIMD2-NEXT: ret void, !dbg [[DBG289:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG289:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG290:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META290:![0-9]+]], !DIExpression(), [[META291:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META291:![0-9]+]], !DIExpression(), [[META292:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG292:![0-9]+]] -// SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG294:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG295:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG293:![0-9]+]] +// SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG295:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG296:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG297:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META297:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META298:![0-9]+]], !DIExpression(), [[META299:![0-9]+]]) // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META300:![0-9]+]], !DIExpression(), [[META301:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG301:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG301]] -// SIMD2-NEXT: ret void, !dbg [[DBG303:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG302:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG303:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG302]] +// SIMD2-NEXT: ret void, !dbg [[DBG304:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG305:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META305:![0-9]+]], !DIExpression(), [[META306:![0-9]+]]) +// SIMD2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META306:![0-9]+]], !DIExpression(), [[META307:![0-9]+]]) // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG307:![0-9]+]] -// SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG309:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG308:![0-9]+]] +// SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG310:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG311:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG311:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG312:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG313:![0-9]+]] -// SIMD2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG313]] -// SIMD2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG313]] +// SIMD2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG314:![0-9]+]] +// SIMD2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG314]] +// SIMD2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG314]] // SIMD2-NEXT: ret void // // @@ -3338,12 +3338,12 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // @@ -3362,7 +3362,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3394,12 +3394,12 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // @@ -3418,7 +3418,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3449,17 +3449,17 @@ int foobar() { // CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK-TLS1: invoke.cont3: -// CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) +// CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 +// CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // CHECK-TLS1: invoke.cont7: -// CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // CHECK-TLS1: invoke.cont8: -// CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// CHECK-TLS1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK-TLS1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) // CHECK-TLS1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // CHECK-TLS1: invoke.cont9: // CHECK-TLS1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] @@ -3477,7 +3477,7 @@ int foobar() { // CHECK-TLS1: arraydestroy.body: // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // CHECK-TLS1: arraydestroy.done4: @@ -3490,25 +3490,25 @@ int foobar() { // CHECK-TLS1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // CHECK-TLS1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 // CHECK-TLS1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] +// CHECK-TLS1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]] // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] // CHECK-TLS1: arraydestroy.body11: // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] -// CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) +// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1) // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // CHECK-TLS1: arraydestroy.done15: // CHECK-TLS1-NEXT: br label [[EHCLEANUP]] // CHECK-TLS1: ehcleanup: // CHECK-TLS1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK-TLS1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 +// CHECK-TLS1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0 // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] // CHECK-TLS1: arraydestroy.body17: // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK-TLS1: arraydestroy.done21: @@ -3530,7 +3530,7 @@ int foobar() { // CHECK-TLS1: arraydestroy.body: // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // CHECK-TLS1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // CHECK-TLS1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK-TLS1: arraydestroy.done1: @@ -3582,8 +3582,8 @@ int foobar() { // CHECK-TLS1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] // CHECK-TLS1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 // CHECK-TLS1-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x() -// CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1 -// CHECK-TLS1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP17]], i64 0, i64 1 +// CHECK-TLS1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1 // CHECK-TLS1-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 // CHECK-TLS1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4 // CHECK-TLS1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 @@ -3631,12 +3631,12 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // @@ -3693,7 +3693,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3728,8 +3728,8 @@ int foobar() { // CHECK-TLS1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] // CHECK-TLS1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 // CHECK-TLS1-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x() -// CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1 -// CHECK-TLS1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP10]], i64 0, i64 1 +// CHECK-TLS1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1 // CHECK-TLS1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 // CHECK-TLS1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4 // CHECK-TLS1-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 @@ -3785,12 +3785,12 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-TLS1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// CHECK-TLS1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // CHECK-TLS1-NEXT: ret void // // @@ -3809,7 +3809,7 @@ int foobar() { // // // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // CHECK-TLS1-NEXT: entry: // CHECK-TLS1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -3886,8 +3886,8 @@ int foobar() { // CHECK-TLS2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] // CHECK-TLS2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 // CHECK-TLS2-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x() -// CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1 -// CHECK-TLS2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP17]], i64 0, i64 1 +// CHECK-TLS2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1 // CHECK-TLS2-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 // CHECK-TLS2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4 // CHECK-TLS2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 @@ -3935,12 +3935,12 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { +// CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // @@ -4019,8 +4019,8 @@ int foobar() { // CHECK-TLS2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] // CHECK-TLS2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 // CHECK-TLS2-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x() -// CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1 -// CHECK-TLS2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP10]], i64 0, i64 1 +// CHECK-TLS2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1 // CHECK-TLS2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 // CHECK-TLS2-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4 // CHECK-TLS2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 @@ -4069,12 +4069,12 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // @@ -4093,7 +4093,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4125,12 +4125,12 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // @@ -4149,7 +4149,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4180,17 +4180,17 @@ int foobar() { // CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // CHECK-TLS2: invoke.cont3: -// CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) +// CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 +// CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // CHECK-TLS2: invoke.cont7: -// CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // CHECK-TLS2: invoke.cont8: -// CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// CHECK-TLS2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// CHECK-TLS2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) // CHECK-TLS2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // CHECK-TLS2: invoke.cont9: // CHECK-TLS2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]] @@ -4208,7 +4208,7 @@ int foobar() { // CHECK-TLS2: arraydestroy.body: // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // CHECK-TLS2: arraydestroy.done4: @@ -4221,25 +4221,25 @@ int foobar() { // CHECK-TLS2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // CHECK-TLS2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 // CHECK-TLS2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// CHECK-TLS2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] +// CHECK-TLS2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]] // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] // CHECK-TLS2: arraydestroy.body11: // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]] -// CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) +// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1) // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // CHECK-TLS2: arraydestroy.done15: // CHECK-TLS2-NEXT: br label [[EHCLEANUP]] // CHECK-TLS2: ehcleanup: // CHECK-TLS2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// CHECK-TLS2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 +// CHECK-TLS2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0 // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] // CHECK-TLS2: arraydestroy.body17: // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // CHECK-TLS2: arraydestroy.done21: @@ -4261,7 +4261,7 @@ int foobar() { // CHECK-TLS2: arraydestroy.body: // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] // CHECK-TLS2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // CHECK-TLS2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // CHECK-TLS2: arraydestroy.done1: @@ -4283,7 +4283,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { +// CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4322,12 +4322,12 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-TLS2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]] +// CHECK-TLS2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]] // CHECK-TLS2-NEXT: ret void // // @@ -4346,7 +4346,7 @@ int foobar() { // // // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { +// CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 { // CHECK-TLS2-NEXT: entry: // CHECK-TLS2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -4392,224 +4392,224 @@ int foobar() { // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META124:![0-9]+]], !DIExpression(), [[META126:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META125:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META127:![0-9]+]], !DIExpression(), [[META128:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META128:![0-9]+]], !DIExpression(), [[META129:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG130:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG130:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG130]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG131:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG132:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META133:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META133:![0-9]+]], !DIExpression(), [[META134:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG135:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG135:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG136:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG136:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG137:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META137:![0-9]+]], !DIExpression(), [[META138:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META138:![0-9]+]], !DIExpression(), [[META139:![0-9]+]]) // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META139:![0-9]+]], !DIExpression(), [[META140:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META140:![0-9]+]], !DIExpression(), [[META141:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG141:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG142:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG141]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG143:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG142:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG143:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG142]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG144:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG144:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG145:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META145:![0-9]+]], !DIExpression(), [[META146:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META146:![0-9]+]], !DIExpression(), [[META147:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG147:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG149:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG150:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG148:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG150:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG151:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG152:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG152:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG154:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG155:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG153:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG155:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG156:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG156:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG157:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META157:![0-9]+]], !DIExpression(), [[META159:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META158:![0-9]+]], !DIExpression(), [[META160:![0-9]+]]) // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META160:![0-9]+]], !DIExpression(), [[META161:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META161:![0-9]+]], !DIExpression(), [[META162:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG162:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG162]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG163:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG163:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG163]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG164:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG164:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG165:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META165:![0-9]+]], !DIExpression(), [[META166:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META166:![0-9]+]], !DIExpression(), [[META167:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG167:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG168:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG168:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG169:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG169:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG170:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META170:![0-9]+]], !DIExpression(), [[META171:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META171:![0-9]+]], !DIExpression(), [[META172:![0-9]+]]) // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META173:![0-9]+]], !DIExpression(), [[META174:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG175:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG174]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG176:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG175:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG176:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG175]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG177:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG177:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG178:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META178:![0-9]+]], !DIExpression(), [[META179:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META179:![0-9]+]], !DIExpression(), [[META180:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG180:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG182:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG183:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG181:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG183:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG184:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK-TLS3-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG184:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG185:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185:![0-9]+]] -// CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187:![0-9]+]] +// CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186:![0-9]+]] +// CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188:![0-9]+]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG188:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG189:![0-9]+]] // CHECK-TLS3: invoke.cont: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG189:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG190:![0-9]+]] // CHECK-TLS3: invoke.cont2: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG190:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG191:![0-9]+]] // CHECK-TLS3: invoke.cont3: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191:![0-9]+]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG192:![0-9]+]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192:![0-9]+]] +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG193:![0-9]+]] // CHECK-TLS3: invoke.cont7: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG193:![0-9]+]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]] +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG194:![0-9]+]] // CHECK-TLS3: invoke.cont8: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG194:![0-9]+]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]] +// CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG195:![0-9]+]] // CHECK-TLS3: invoke.cont9: -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG195:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG195]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG196:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG196]] // CHECK-TLS3: lpad: // CHECK-TLS3-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// CHECK-TLS3-NEXT: cleanup, !dbg [[DBG196:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG187]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG187]] +// CHECK-TLS3-NEXT: cleanup, !dbg [[DBG197:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG188]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG188]] // CHECK-TLS3: arraydestroy.body: -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG187]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG187]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG187]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG188]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG188]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG188]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG188]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG188]] // CHECK-TLS3: arraydestroy.done4: -// CHECK-TLS3-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG187]] +// CHECK-TLS3-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG188]] // CHECK-TLS3: lpad6: // CHECK-TLS3-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// CHECK-TLS3-NEXT: cleanup, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG191]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG191]] +// CHECK-TLS3-NEXT: cleanup, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG192]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG192]] // CHECK-TLS3: arraydestroy.body11: -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG191]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG191]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG191]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG191]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG192]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG192]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG192]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), !dbg [[DBG192]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG192]] // CHECK-TLS3: arraydestroy.done15: -// CHECK-TLS3-NEXT: br label [[EHCLEANUP]], !dbg [[DBG191]] +// CHECK-TLS3-NEXT: br label [[EHCLEANUP]], !dbg [[DBG192]] // CHECK-TLS3: ehcleanup: -// CHECK-TLS3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG185]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG186]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG186]] // CHECK-TLS3: arraydestroy.body17: -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG186]] // CHECK-TLS3: arraydestroy.done21: -// CHECK-TLS3-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG186]] // CHECK-TLS3: eh.resume: -// CHECK-TLS3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG186]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK-TLS3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG197:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG198:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META201:![0-9]+]], !DIExpression(), [[META202:![0-9]+]]) -// CHECK-TLS3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META202]] +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META202:![0-9]+]], !DIExpression(), [[META203:![0-9]+]]) +// CHECK-TLS3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META203]] // CHECK-TLS3: arraydestroy.body: -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META202]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META202]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META202]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META202]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META202]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META203]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META203]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META203]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META203]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META203]] // CHECK-TLS3: arraydestroy.done1: -// CHECK-TLS3-NEXT: ret void, !dbg [[META202]] +// CHECK-TLS3-NEXT: ret void, !dbg [[META203]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@main @@ -4618,72 +4618,72 @@ int foobar() { // CHECK-TLS3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: [[RES:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[RES]], [[META203:![0-9]+]], !DIExpression(), [[META204:![0-9]+]]) -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG205:![0-9]+]] -// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG205]] -// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG205]], !prof [[PROF206:![0-9]+]] +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[RES]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]]) +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG206:![0-9]+]] +// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG206]] +// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG206]], !prof [[PROF207:![0-9]+]] // CHECK-TLS3: init.check: -// CHECK-TLS3-NEXT: [[TMP1:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG207:![0-9]+]] -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG208:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG208]] -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG209:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG205]] -// CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG205]] -// CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG205]] +// CHECK-TLS3-NEXT: [[TMP1:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG208:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG209:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG209]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG210:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG206]] +// CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG206]] +// CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG206]] // CHECK-TLS3: init.end: -// CHECK-TLS3-NEXT: [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG210:![0-9]+]] -// CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG211:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG211]] -// CHECK-TLS3-NEXT: store i32 [[TMP5]], ptr [[RES]], align 4, !dbg [[DBG212:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm), !dbg [[DBG213:![0-9]+]] -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG214]] -// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG215:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG215]] -// CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG215]] -// CHECK-TLS3-NEXT: [[TMP9:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG216:![0-9]+]] -// CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG217:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP10:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG217]] -// CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG218]] -// CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG218]] -// CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG220]] -// CHECK-TLS3-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG220]] -// CHECK-TLS3-NEXT: [[TMP14:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG221:![0-9]+]] -// CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0, !dbg [[DBG222:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG222]] -// CHECK-TLS3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG223]] -// CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG223]] -// CHECK-TLS3-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG224:![0-9]+]] -// CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG224]] -// CHECK-TLS3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG224]] -// CHECK-TLS3-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG225:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG225]] -// CHECK-TLS3-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG226]] -// CHECK-TLS3-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG226]] -// CHECK-TLS3-NEXT: [[TMP20:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG227:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG227]] -// CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG228]] -// CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG228]] -// CHECK-TLS3-NEXT: [[TMP23:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG229:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4, !dbg [[DBG229]] -// CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP24]] to i32, !dbg [[DBG229]] -// CHECK-TLS3-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]], !dbg [[DBG230]] -// CHECK-TLS3-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG230]] -// CHECK-TLS3-NEXT: [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG231:![0-9]+]] -// CHECK-TLS3-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0, !dbg [[DBG232:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG232]] -// CHECK-TLS3-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG233:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]], !dbg [[DBG233]] -// CHECK-TLS3-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG233]] -// CHECK-TLS3-NEXT: [[TMP29:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG234:![0-9]+]] -// CHECK-TLS3-NEXT: ret i32 [[TMP29]], !dbg [[DBG235:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG211:![0-9]+]] +// CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG212]] +// CHECK-TLS3-NEXT: store i32 [[TMP5]], ptr [[RES]], align 4, !dbg [[DBG213:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm), !dbg [[DBG214:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG215:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG215]] +// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG216]] +// CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG216]] +// CHECK-TLS3-NEXT: [[TMP9:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG217:![0-9]+]] +// CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG218:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP10:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG218]] +// CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG219]] +// CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG219]] +// CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG221]] +// CHECK-TLS3-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG221]] +// CHECK-TLS3-NEXT: [[TMP14:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG222:![0-9]+]] +// CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0, !dbg [[DBG223:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG223]] +// CHECK-TLS3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG224]] +// CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG224]] +// CHECK-TLS3-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG225:![0-9]+]] +// CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG225]] +// CHECK-TLS3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG225]] +// CHECK-TLS3-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG226:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG226]] +// CHECK-TLS3-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG227]] +// CHECK-TLS3-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG227]] +// CHECK-TLS3-NEXT: [[TMP20:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG228:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG228]] +// CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG229]] +// CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG229]] +// CHECK-TLS3-NEXT: [[TMP23:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG230:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4, !dbg [[DBG230]] +// CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP24]] to i32, !dbg [[DBG230]] +// CHECK-TLS3-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]], !dbg [[DBG231]] +// CHECK-TLS3-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG231]] +// CHECK-TLS3-NEXT: [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG232:![0-9]+]] +// CHECK-TLS3-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0, !dbg [[DBG233:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG233]] +// CHECK-TLS3-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG234:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]], !dbg [[DBG234]] +// CHECK-TLS3-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG234]] +// CHECK-TLS3-NEXT: [[TMP29:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG235:![0-9]+]] +// CHECK-TLS3-NEXT: ret i32 [[TMP29]], !dbg [[DBG236:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWL3gs1 @@ -4694,29 +4694,29 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG236:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG237:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META237:![0-9]+]], !DIExpression(), [[META239:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META238:![0-9]+]], !DIExpression(), [[META240:![0-9]+]]) // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META240:![0-9]+]], !DIExpression(), [[META241:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META241:![0-9]+]], !DIExpression(), [[META242:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG242:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG242]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG243:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG243:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG243]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG244:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG244:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG245:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META245:![0-9]+]], !DIExpression(), [[META246:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META246:![0-9]+]], !DIExpression(), [[META247:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG247:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG248:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG248:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG249:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWN6Static1sE @@ -4758,174 +4758,174 @@ int foobar() { // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG249:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG250:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META250:![0-9]+]], !DIExpression(), [[META251:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META251:![0-9]+]], !DIExpression(), [[META252:![0-9]+]]) // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META252:![0-9]+]], !DIExpression(), [[META253:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META253:![0-9]+]], !DIExpression(), [[META254:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG254:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG255:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG254]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG256:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG255:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG256:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG255]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG257:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG257:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG258:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META258:![0-9]+]], !DIExpression(), [[META259:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META259:![0-9]+]], !DIExpression(), [[META260:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG260:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG262:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG263:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG261:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG263:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG264:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_Z6foobarv -// CHECK-TLS3-SAME: () #[[ATTR1]] !dbg [[DBG264:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR1]] !dbg [[DBG265:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[RES:%.*]] = alloca i32, align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[RES]], [[META265:![0-9]+]], !DIExpression(), [[META266:![0-9]+]]) -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG267:![0-9]+]] -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG268:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG268]] -// CHECK-TLS3-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG269:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG270:![0-9]+]] -// CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG271]] -// CHECK-TLS3-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG272:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG272]] -// CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG272]] -// CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG273:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG274:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG274]] -// CHECK-TLS3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG274]] -// CHECK-TLS3-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG275:![0-9]+]] -// CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG276:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG276]] -// CHECK-TLS3-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG277:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG277]] -// CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG277]] -// CHECK-TLS3-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG278:![0-9]+]] -// CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG278]] -// CHECK-TLS3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG278]] -// CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG279:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG279]] -// CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG280:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG280]] -// CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG280]] -// CHECK-TLS3-NEXT: [[TMP13:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG281:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG281]] -// CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG282]] -// CHECK-TLS3-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG282]] -// CHECK-TLS3-NEXT: [[TMP16:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG283:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG283]] -// CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG283]] -// CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG284:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG284]] -// CHECK-TLS3-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG284]] -// CHECK-TLS3-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG285:![0-9]+]] -// CHECK-TLS3-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG286]] -// CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG287:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG287]] -// CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG287]] -// CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG288:![0-9]+]] -// CHECK-TLS3-NEXT: ret i32 [[TMP22]], !dbg [[DBG289:![0-9]+]] +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[RES]], [[META266:![0-9]+]], !DIExpression(), [[META267:![0-9]+]]) +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG268:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG269:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG269]] +// CHECK-TLS3-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG270:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG271:![0-9]+]] +// CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG272]] +// CHECK-TLS3-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG273:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG273]] +// CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG273]] +// CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG274:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG275:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG275]] +// CHECK-TLS3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG275]] +// CHECK-TLS3-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG276:![0-9]+]] +// CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG277]] +// CHECK-TLS3-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG278:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG278]] +// CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG278]] +// CHECK-TLS3-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG279:![0-9]+]] +// CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG279]] +// CHECK-TLS3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG279]] +// CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG280]] +// CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG281:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG281]] +// CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG281]] +// CHECK-TLS3-NEXT: [[TMP13:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG282:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG282]] +// CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG283:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG283]] +// CHECK-TLS3-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG283]] +// CHECK-TLS3-NEXT: [[TMP16:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG284:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG284]] +// CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG284]] +// CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG285:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG285]] +// CHECK-TLS3-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG285]] +// CHECK-TLS3-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG286:![0-9]+]] +// CHECK-TLS3-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG287]] +// CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG288:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG288]] +// CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG288]] +// CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG289:![0-9]+]] +// CHECK-TLS3-NEXT: ret i32 [[TMP22]], !dbg [[DBG290:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG290:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG291:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291:![0-9]+]] -// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG291]] -// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG291]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292:![0-9]+]] +// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG292]] +// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG292]] // CHECK-TLS3: init.check: -// CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291]] -// CHECK-TLS3-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG292:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG291]] -// CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG291]] +// CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292]] +// CHECK-TLS3-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG293:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG292]] +// CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG292]] // CHECK-TLS3: init.end: -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG294:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG295:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG295:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG296:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META296:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META297:![0-9]+]], !DIExpression(), [[META299:![0-9]+]]) // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META300:![0-9]+]], !DIExpression(), [[META301:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG302:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG302]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG303:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG303:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META304:![0-9]+]], !DIExpression(), [[META305:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META305:![0-9]+]], !DIExpression(), [[META306:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG306:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG307:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG307:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG308:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG308:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG309:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META309:![0-9]+]], !DIExpression(), [[META310:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META310:![0-9]+]], !DIExpression(), [[META311:![0-9]+]]) // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META311:![0-9]+]], !DIExpression(), [[META312:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META312:![0-9]+]], !DIExpression(), [[META313:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG313:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG314:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG313]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG315:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG315:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG314]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG316:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG316:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG317:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META317:![0-9]+]], !DIExpression(), [[META318:![0-9]+]]) +// CHECK-TLS3-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META318:![0-9]+]], !DIExpression(), [[META319:![0-9]+]]) // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG321:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG322:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG322:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG323:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG323:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG324:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG325:![0-9]+]] +// CHECK-TLS3-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG326:![0-9]+]] // CHECK-TLS3-NEXT: ret void // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__tls_init -// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG326:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG327:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG327:![0-9]+]] -// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG327]] -// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG327]], !prof [[PROF206]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG328:![0-9]+]] +// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG328]] +// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG328]], !prof [[PROF207]] // CHECK-TLS3: init: -// CHECK-TLS3-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG327]] -// CHECK-TLS3-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG327]] -// CHECK-TLS3-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG327]] -// CHECK-TLS3-NEXT: br label [[EXIT]], !dbg [[DBG327]] +// CHECK-TLS3-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG328]] +// CHECK-TLS3-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG328]] +// CHECK-TLS3-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG328]] +// CHECK-TLS3-NEXT: br label [[EXIT]], !dbg [[DBG328]] // CHECK-TLS3: exit: // CHECK-TLS3-NEXT: ret void // @@ -4976,8 +4976,8 @@ int foobar() { // CHECK-TLS4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG136]] // CHECK-TLS4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG136]] // CHECK-TLS4-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG137:![0-9]+]] -// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG137]] -// CHECK-TLS4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG137]] +// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG137]] +// CHECK-TLS4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG137]] // CHECK-TLS4-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG138:![0-9]+]] // CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG138]] // CHECK-TLS4-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG139:![0-9]+]] @@ -5017,24 +5017,24 @@ int foobar() { // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META150:![0-9]+]], !DIExpression(), [[META152:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META151:![0-9]+]], !DIExpression(), [[META153:![0-9]+]]) // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META153:![0-9]+]], !DIExpression(), [[META154:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META154:![0-9]+]], !DIExpression(), [[META155:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG155:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG155]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG156:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG156:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG156]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG157:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 !dbg [[DBG157:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 !dbg [[DBG158:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META158:![0-9]+]], !DIExpression(), [[META159:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META159:![0-9]+]], !DIExpression(), [[META160:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG160:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG161:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG161:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG162:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN6Static1sE @@ -5088,408 +5088,408 @@ int foobar() { // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_Z6foobarv -// CHECK-TLS4-SAME: () #[[ATTR2]] !dbg [[DBG162:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR2]] !dbg [[DBG163:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[RES:%.*]] = alloca i32, align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[RES]], [[META163:![0-9]+]], !DIExpression(), [[META164:![0-9]+]]) -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG165:![0-9]+]] -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG166:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG166]] -// CHECK-TLS4-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG167:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG168:![0-9]+]] -// CHECK-TLS4-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG169:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG169]] -// CHECK-TLS4-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG170:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG170]] -// CHECK-TLS4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG170]] -// CHECK-TLS4-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG171:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG172:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG172]] -// CHECK-TLS4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG172]] -// CHECK-TLS4-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG173:![0-9]+]] -// CHECK-TLS4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG174]] -// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG175:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG175]] -// CHECK-TLS4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG175]] -// CHECK-TLS4-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG176:![0-9]+]] -// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG176]] -// CHECK-TLS4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG176]] -// CHECK-TLS4-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG177:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG177]] -// CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG178:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG178]] -// CHECK-TLS4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG178]] -// CHECK-TLS4-NEXT: [[TMP13:%.*]] = call ptr @_ZTWN2STIiE2stE(), !dbg [[DBG179:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG179]] -// CHECK-TLS4-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG180]] -// CHECK-TLS4-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG180]] -// CHECK-TLS4-NEXT: [[TMP16:%.*]] = call ptr @_ZTWN2STIfE2stE(), !dbg [[DBG181:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG181]] -// CHECK-TLS4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG181]] -// CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG182]] -// CHECK-TLS4-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG182]] -// CHECK-TLS4-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG183:![0-9]+]] -// CHECK-TLS4-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG184:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG184]] -// CHECK-TLS4-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]] -// CHECK-TLS4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG185]] -// CHECK-TLS4-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG185]] -// CHECK-TLS4-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]] -// CHECK-TLS4-NEXT: ret i32 [[TMP22]], !dbg [[DBG187:![0-9]+]] +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[RES]], [[META164:![0-9]+]], !DIExpression(), [[META165:![0-9]+]]) +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG166:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG167:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG167]] +// CHECK-TLS4-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG168:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG169:![0-9]+]] +// CHECK-TLS4-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG170:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG170]] +// CHECK-TLS4-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG171:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG171]] +// CHECK-TLS4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG171]] +// CHECK-TLS4-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG172:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG173:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG173]] +// CHECK-TLS4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG173]] +// CHECK-TLS4-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG174:![0-9]+]] +// CHECK-TLS4-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG175:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG175]] +// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG176:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG176]] +// CHECK-TLS4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG176]] +// CHECK-TLS4-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG177:![0-9]+]] +// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG177]] +// CHECK-TLS4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG177]] +// CHECK-TLS4-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG178:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG178]] +// CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG179:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG179]] +// CHECK-TLS4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG179]] +// CHECK-TLS4-NEXT: [[TMP13:%.*]] = call ptr @_ZTWN2STIiE2stE(), !dbg [[DBG180:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG180]] +// CHECK-TLS4-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG181:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG181]] +// CHECK-TLS4-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG181]] +// CHECK-TLS4-NEXT: [[TMP16:%.*]] = call ptr @_ZTWN2STIfE2stE(), !dbg [[DBG182:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG182]] +// CHECK-TLS4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG182]] +// CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG183:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG183]] +// CHECK-TLS4-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG183]] +// CHECK-TLS4-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG184:![0-9]+]] +// CHECK-TLS4-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG185:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG185]] +// CHECK-TLS4-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]] +// CHECK-TLS4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG186]] +// CHECK-TLS4-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG186]] +// CHECK-TLS4-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]] +// CHECK-TLS4-NEXT: ret i32 [[TMP22]], !dbg [[DBG188:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init -// CHECK-TLS4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG188:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG189:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG191:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG193:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG194:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG192:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG194:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG195:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG195:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG196:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META196:![0-9]+]], !DIExpression(), [[META198:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META197:![0-9]+]], !DIExpression(), [[META199:![0-9]+]]) // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META199:![0-9]+]], !DIExpression(), [[META200:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META200:![0-9]+]], !DIExpression(), [[META201:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG201:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG201]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG202:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG202:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG202]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG203:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG203:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG204:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META205:![0-9]+]], !DIExpression(), [[META206:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG206:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG207:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG207:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG208:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG208:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG209:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META209:![0-9]+]], !DIExpression(), [[META210:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META210:![0-9]+]], !DIExpression(), [[META211:![0-9]+]]) // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META211:![0-9]+]], !DIExpression(), [[META212:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META212:![0-9]+]], !DIExpression(), [[META213:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG213:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG214:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG213]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG215:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG215:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG214]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG216:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG216:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG217:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META217:![0-9]+]], !DIExpression(), [[META218:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META218:![0-9]+]], !DIExpression(), [[META219:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG219:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG221:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG222:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG220:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG222:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG223:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG223:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG224:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG224:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG226:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG227:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG225:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG227:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG228:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG228:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG229:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META229:![0-9]+]], !DIExpression(), [[META231:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META230:![0-9]+]], !DIExpression(), [[META232:![0-9]+]]) // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META232:![0-9]+]], !DIExpression(), [[META233:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META233:![0-9]+]], !DIExpression(), [[META234:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG234:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG234]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG235:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG235:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG235]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG236:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG236:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG237:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META237:![0-9]+]], !DIExpression(), [[META238:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META238:![0-9]+]], !DIExpression(), [[META239:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG239:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG240:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG240:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG241:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG241:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG242:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META243:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META243:![0-9]+]], !DIExpression(), [[META244:![0-9]+]]) // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META244:![0-9]+]], !DIExpression(), [[META245:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META245:![0-9]+]], !DIExpression(), [[META246:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG246:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG247:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG246]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG248:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG247:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG248:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG247]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG249:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG249:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG250:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META250:![0-9]+]], !DIExpression(), [[META251:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META251:![0-9]+]], !DIExpression(), [[META252:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG252:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG254:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG255:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG253:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG255:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG256:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK-TLS4-SAME: () #[[ATTR6]] personality ptr @__gxx_personality_v0 !dbg [[DBG256:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR6]] personality ptr @__gxx_personality_v0 !dbg [[DBG257:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257:![0-9]+]] -// CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259:![0-9]+]] +// CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258:![0-9]+]] +// CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260:![0-9]+]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG260:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG261:![0-9]+]] // CHECK-TLS4: invoke.cont: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG261:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG262:![0-9]+]] // CHECK-TLS4: invoke.cont2: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG262:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG263:![0-9]+]] // CHECK-TLS4: invoke.cont3: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263:![0-9]+]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG264:![0-9]+]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264:![0-9]+]] +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG265:![0-9]+]] // CHECK-TLS4: invoke.cont7: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG265:![0-9]+]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]] +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG266:![0-9]+]] // CHECK-TLS4: invoke.cont8: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] -// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG266:![0-9]+]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]] +// CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG267:![0-9]+]] // CHECK-TLS4: invoke.cont9: -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG267:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG267]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG268:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG268]] // CHECK-TLS4: lpad: // CHECK-TLS4-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// CHECK-TLS4-NEXT: cleanup, !dbg [[DBG268:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG259]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG259]] +// CHECK-TLS4-NEXT: cleanup, !dbg [[DBG269:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG260]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG260]] // CHECK-TLS4: arraydestroy.body: -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG259]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG259]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG259]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG259]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG259]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG260]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG260]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG260]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG260]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG260]] // CHECK-TLS4: arraydestroy.done4: -// CHECK-TLS4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG259]] +// CHECK-TLS4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG260]] // CHECK-TLS4: lpad6: // CHECK-TLS4-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// CHECK-TLS4-NEXT: cleanup, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG263]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG263]] +// CHECK-TLS4-NEXT: cleanup, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG264]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG264]] // CHECK-TLS4: arraydestroy.body11: -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG263]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG263]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG263]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG263]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG263]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG264]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG264]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG264]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), !dbg [[DBG264]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG264]] // CHECK-TLS4: arraydestroy.done15: -// CHECK-TLS4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG263]] +// CHECK-TLS4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG264]] // CHECK-TLS4: ehcleanup: -// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG257]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG257]] +// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG258]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG258]] // CHECK-TLS4: arraydestroy.body17: -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG257]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG258]] // CHECK-TLS4: arraydestroy.done21: -// CHECK-TLS4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG257]] +// CHECK-TLS4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG258]] // CHECK-TLS4: eh.resume: -// CHECK-TLS4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG257]] +// CHECK-TLS4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG258]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK-TLS4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6]] !dbg [[DBG269:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6]] !dbg [[DBG270:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META273:![0-9]+]], !DIExpression(), [[META274:![0-9]+]]) -// CHECK-TLS4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META274]] +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META274:![0-9]+]], !DIExpression(), [[META275:![0-9]+]]) +// CHECK-TLS4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META275]] // CHECK-TLS4: arraydestroy.body: -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META274]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META274]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[META274]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META274]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META274]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META275]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META275]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[META275]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META275]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META275]] // CHECK-TLS4: arraydestroy.done1: -// CHECK-TLS4-NEXT: ret void, !dbg [[META274]] +// CHECK-TLS4-NEXT: ret void, !dbg [[META275]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG275:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG276:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META276:![0-9]+]], !DIExpression(), [[META277:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META277:![0-9]+]], !DIExpression(), [[META278:![0-9]+]]) // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META278:![0-9]+]], !DIExpression(), [[META279:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META279:![0-9]+]], !DIExpression(), [[META280:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG281:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG280]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG282:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG281:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG282:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG281]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG283:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG283:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG284:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META284:![0-9]+]], !DIExpression(), [[META285:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META285:![0-9]+]], !DIExpression(), [[META286:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG288:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG289:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG289:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG290:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG290:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG291:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291:![0-9]+]] -// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG291]] -// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG291]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292:![0-9]+]] +// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG292]] +// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG292]] // CHECK-TLS4: init.check: -// CHECK-TLS4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291]] -// CHECK-TLS4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG292:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG291]] -// CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG291]] +// CHECK-TLS4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292]] +// CHECK-TLS4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG293:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG292]] +// CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG292]] // CHECK-TLS4: init.end: -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG294:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG295:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG295:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META296:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META297:![0-9]+]], !DIExpression(), [[META299:![0-9]+]]) // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META300:![0-9]+]], !DIExpression(), [[META301:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG302:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG302]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG303:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG303:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG304:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META304:![0-9]+]], !DIExpression(), [[META305:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META305:![0-9]+]], !DIExpression(), [[META306:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG306:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG307:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG307:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG308:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG308:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG309:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META309:![0-9]+]], !DIExpression(), [[META310:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META310:![0-9]+]], !DIExpression(), [[META311:![0-9]+]]) // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META311:![0-9]+]], !DIExpression(), [[META312:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META312:![0-9]+]], !DIExpression(), [[META313:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG313:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG314:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG313]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG315:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG315:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG314]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG316:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG316:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG317:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META317:![0-9]+]], !DIExpression(), [[META318:![0-9]+]]) +// CHECK-TLS4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META318:![0-9]+]], !DIExpression(), [[META319:![0-9]+]]) // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG321:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG322:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG322:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG323:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG323:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG324:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG325:![0-9]+]] +// CHECK-TLS4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG326:![0-9]+]] // CHECK-TLS4-NEXT: ret void // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__tls_init -// CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG326:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR6]] !dbg [[DBG327:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG327:![0-9]+]] -// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG327]] -// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG327]], !prof [[PROF119]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG328:![0-9]+]] +// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG328]] +// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG328]], !prof [[PROF119]] // CHECK-TLS4: init: -// CHECK-TLS4-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG327]] -// CHECK-TLS4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG327]] -// CHECK-TLS4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG327]] -// CHECK-TLS4-NEXT: br label [[EXIT]], !dbg [[DBG327]] +// CHECK-TLS4-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG328]] +// CHECK-TLS4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG328]] +// CHECK-TLS4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG328]] +// CHECK-TLS4-NEXT: br label [[EXIT]], !dbg [[DBG328]] // CHECK-TLS4: exit: // CHECK-TLS4-NEXT: ret void // @@ -5516,12 +5516,12 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { +// SIMD3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD3-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]] // SIMD3-NEXT: ret void // // @@ -5547,12 +5547,12 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD3-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]] // SIMD3-NEXT: ret void // // @@ -5577,17 +5577,17 @@ int foobar() { // SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) // SIMD3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]] // SIMD3: invoke.cont3: -// SIMD3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// SIMD3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) +// SIMD3-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8 +// SIMD3-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) // SIMD3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]] // SIMD3: invoke.cont7: -// SIMD3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// SIMD3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) // SIMD3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]] // SIMD3: invoke.cont8: -// SIMD3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// SIMD3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8 +// SIMD3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) // SIMD3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]] // SIMD3: invoke.cont9: // SIMD3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]] @@ -5605,7 +5605,7 @@ int foobar() { // SIMD3: arraydestroy.body: // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]] // SIMD3: arraydestroy.done4: @@ -5618,25 +5618,25 @@ int foobar() { // SIMD3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1 // SIMD3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4 // SIMD3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8 -// SIMD3-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]] +// SIMD3-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]] // SIMD3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]] // SIMD3: arraydestroy.body11: // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ] // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1 -// SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] -// SIMD3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1) +// SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]] +// SIMD3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1) // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]] // SIMD3: arraydestroy.done15: // SIMD3-NEXT: br label [[EHCLEANUP]] // SIMD3: ehcleanup: // SIMD3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8 -// SIMD3-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0 +// SIMD3-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0 // SIMD3-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]] // SIMD3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]] // SIMD3: arraydestroy.body17: // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ] // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1 -// SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]] // SIMD3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]] // SIMD3: arraydestroy.done21: @@ -5658,7 +5658,7 @@ int foobar() { // SIMD3: arraydestroy.body: // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // SIMD3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]] // SIMD3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x // SIMD3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]] // SIMD3: arraydestroy.done1: @@ -5707,7 +5707,7 @@ int foobar() { // SIMD3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 // SIMD3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] // SIMD3-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4 -// SIMD3-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 +// SIMD3-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x [[STRUCT_S1:%.*]]], ptr getelementptr inbounds ([2 x [3 x [[STRUCT_S1]]]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 // SIMD3-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4 // SIMD3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] // SIMD3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 @@ -5757,12 +5757,12 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD3-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]] // SIMD3-NEXT: ret void // // @@ -5784,7 +5784,7 @@ int foobar() { // SIMD3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4 // SIMD3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]] // SIMD3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4 -// SIMD3-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 +// SIMD3-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x [[STRUCT_S1:%.*]]], ptr getelementptr inbounds ([2 x [3 x [[STRUCT_S1]]]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4 // SIMD3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4 // SIMD3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]] // SIMD3-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4 @@ -5834,12 +5834,12 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // SIMD3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD3-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]] +// SIMD3-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]] // SIMD3-NEXT: ret void // // @@ -5858,7 +5858,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -5883,7 +5883,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -5908,7 +5908,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { +// SIMD3-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -5933,7 +5933,7 @@ int foobar() { // // // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { +// SIMD3-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 { // SIMD3-NEXT: entry: // SIMD3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -5966,168 +5966,168 @@ int foobar() { // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META123:![0-9]+]], !DIExpression(), [[META125:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META124:![0-9]+]], !DIExpression(), [[META126:![0-9]+]]) // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META126:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META127:![0-9]+]], !DIExpression(), [[META128:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG128]] -// SIMD4-NEXT: ret void, !dbg [[DBG129:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] +// SIMD4-NEXT: ret void, !dbg [[DBG130:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META132:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META133:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG133:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG134:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG135:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG135:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG136:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG136:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG139:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG137:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG139:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG140:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG140:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG141:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META141:![0-9]+]], !DIExpression(), [[META143:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META142:![0-9]+]], !DIExpression(), [[META144:![0-9]+]]) // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META145:![0-9]+]], !DIExpression(), [[META146:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG146]] -// SIMD4-NEXT: ret void, !dbg [[DBG147:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG147]] +// SIMD4-NEXT: ret void, !dbg [[DBG148:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG148:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG149:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META149:![0-9]+]], !DIExpression(), [[META150:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META150:![0-9]+]], !DIExpression(), [[META151:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG152:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG152:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG153:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// SIMD4-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG153:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG154:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154:![0-9]+]] -// SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156:![0-9]+]] +// SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155:![0-9]+]] +// SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157:![0-9]+]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG157:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG158:![0-9]+]] // SIMD4: invoke.cont: -// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// SIMD4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG158:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] // SIMD4: invoke.cont2: -// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// SIMD4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG160:![0-9]+]] // SIMD4: invoke.cont3: -// SIMD4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160:![0-9]+]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// SIMD4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG161:![0-9]+]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161:![0-9]+]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) +// SIMD4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG162:![0-9]+]] // SIMD4: invoke.cont7: -// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// SIMD4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG162:![0-9]+]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// SIMD4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] // SIMD4: invoke.cont8: -// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// SIMD4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// SIMD4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG164:![0-9]+]] // SIMD4: invoke.cont9: -// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG164]] +// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG165:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG165]] // SIMD4: lpad: // SIMD4-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG165:![0-9]+]] -// SIMD4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG165]] -// SIMD4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG165]] -// SIMD4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG156]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] +// SIMD4-NEXT: cleanup, !dbg [[DBG166:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG166]] +// SIMD4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG166]] +// SIMD4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG157]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]] // SIMD4: arraydestroy.body: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG156]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG157]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]] // SIMD4: arraydestroy.done4: -// SIMD4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG156]] +// SIMD4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG157]] // SIMD4: lpad6: // SIMD4-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG165]] -// SIMD4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG165]] -// SIMD4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG160]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG160]] +// SIMD4-NEXT: cleanup, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG166]] +// SIMD4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG166]] +// SIMD4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG161]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG161]] // SIMD4: arraydestroy.body11: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG160]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG160]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG160]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG161]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), !dbg [[DBG161]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG161]] // SIMD4: arraydestroy.done15: -// SIMD4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG160]] +// SIMD4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG161]] // SIMD4: ehcleanup: -// SIMD4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG154]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG154]] +// SIMD4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG155]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG155]] // SIMD4: arraydestroy.body17: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG154]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG154]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG154]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG155]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG155]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG155]] // SIMD4: arraydestroy.done21: -// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG154]] +// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG155]] // SIMD4: eh.resume: -// SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG154]] -// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG154]] -// SIMD4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG154]] -// SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG154]] +// SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG155]] +// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG155]] +// SIMD4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG155]] +// SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG155]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// SIMD4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] { +// SIMD4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG167:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META170:![0-9]+]], !DIExpression(), [[META171:![0-9]+]]) -// SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META171]] +// SIMD4-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META171:![0-9]+]], !DIExpression(), [[META172:![0-9]+]]) +// SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META172]] // SIMD4: arraydestroy.body: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META171]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META171]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META171]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META171]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META171]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META172]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META172]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META172]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META172]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META172]] // SIMD4: arraydestroy.done1: -// SIMD4-NEXT: ret void, !dbg [[META171]] +// SIMD4-NEXT: ret void, !dbg [[META172]] // // // SIMD4-LABEL: define {{[^@]+}}@main @@ -6138,302 +6138,302 @@ int foobar() { // SIMD4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[RES]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]]) -// SIMD4-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG174:![0-9]+]] -// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG174]], !prof [[PROF175:![0-9]+]] +// SIMD4-NEXT: #dbg_declare(ptr [[RES]], [[META173:![0-9]+]], !DIExpression(), [[META174:![0-9]+]]) +// SIMD4-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG175:![0-9]+]] +// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG175]], !prof [[PROF176:![0-9]+]] // SIMD4: init.check: -// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG174]] +// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG175]] // SIMD4: init: -// SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG176:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG177:![0-9]+]] // SIMD4-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) -// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG177:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG178:![0-9]+]] // SIMD4: invoke.cont: -// SIMD4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG174]] +// SIMD4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG175]] // SIMD4: init.end: -// SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG178:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG179:![0-9]+]] -// SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG180:![0-9]+]] -// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG181:![0-9]+]] -// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG181]] -// SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG181]] -// SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG182:![0-9]+]] -// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG183:![0-9]+]] -// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG183]] -// SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG183]] -// SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG184:![0-9]+]] -// SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]] -// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG185]] -// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG185]] -// SIMD4-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG186:![0-9]+]] -// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]] -// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]] -// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG187]] -// SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG188:![0-9]+]] -// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG189:![0-9]+]] -// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]] -// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG189]] -// SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG190:![0-9]+]] -// SIMD4-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG191:![0-9]+]] -// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG191]] -// SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG191]] -// SIMD4-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG192:![0-9]+]] -// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG192]] -// SIMD4-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG193:![0-9]+]] -// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG193]] -// SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG193]] -// SIMD4-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG194:![0-9]+]] -// SIMD4-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG195:![0-9]+]] -// SIMD4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG195]] -// SIMD4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG195]] -// SIMD4-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] -// SIMD4-NEXT: ret i32 [[TMP21]], !dbg [[DBG197:![0-9]+]] +// SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG179:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]] +// SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG181:![0-9]+]] +// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]] +// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG182]] +// SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG182]] +// SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG183:![0-9]+]] +// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG184:![0-9]+]] +// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG184]] +// SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG184]] +// SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG185:![0-9]+]] +// SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]] +// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG186]] +// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG186]] +// SIMD4-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG187:![0-9]+]] +// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG188:![0-9]+]] +// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG188]] +// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG188]] +// SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([3 x [[STRUCT_S1:%.*]]], ptr getelementptr inbounds ([2 x [3 x [[STRUCT_S1]]]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG189:![0-9]+]] +// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG190:![0-9]+]] +// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG190]] +// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG190]] +// SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG191:![0-9]+]] +// SIMD4-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG192:![0-9]+]] +// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG192]] +// SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG192]] +// SIMD4-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG193:![0-9]+]] +// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG193]] +// SIMD4-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG194:![0-9]+]] +// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG194]] +// SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG194]] +// SIMD4-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG195:![0-9]+]] +// SIMD4-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] +// SIMD4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG196]] +// SIMD4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG196]] +// SIMD4-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG197:![0-9]+]] +// SIMD4-NEXT: ret i32 [[TMP21]], !dbg [[DBG198:![0-9]+]] // SIMD4: lpad: // SIMD4-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG198:![0-9]+]] -// SIMD4-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG198]] -// SIMD4-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG198]] -// SIMD4-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG198]] -// SIMD4-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG198]] -// SIMD4-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG174]] +// SIMD4-NEXT: cleanup, !dbg [[DBG199:![0-9]+]] +// SIMD4-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG199]] +// SIMD4-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG199]] +// SIMD4-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG199]] +// SIMD4-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG199]] +// SIMD4-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG175]] // SIMD4: eh.resume: -// SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG174]] -// SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG174]] -// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG174]] -// SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG174]] +// SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG175]] +// SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG175]] +// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG175]] +// SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG175]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG199:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG200:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META200:![0-9]+]], !DIExpression(), [[META202:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META201:![0-9]+]], !DIExpression(), [[META203:![0-9]+]]) // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META203:![0-9]+]], !DIExpression(), [[META204:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] -// SIMD4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG205]] -// SIMD4-NEXT: ret void, !dbg [[DBG206:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]] +// SIMD4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG206]] +// SIMD4-NEXT: ret void, !dbg [[DBG207:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG207:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG208:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META208:![0-9]+]], !DIExpression(), [[META209:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META209:![0-9]+]], !DIExpression(), [[META210:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG210:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG211:![0-9]+]] +// SIMD4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG211:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG212:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_Z6foobarv -// SIMD4-SAME: () #[[ATTR2]] !dbg [[DBG212:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR2]] !dbg [[DBG213:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[RES:%.*]] = alloca i32, align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[RES]], [[META213:![0-9]+]], !DIExpression(), [[META214:![0-9]+]]) -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG215:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] -// SIMD4-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG217:![0-9]+]] -// SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] -// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG218]] -// SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG218]] -// SIMD4-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] -// SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG220]] -// SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG220]] -// SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG221:![0-9]+]] -// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG222:![0-9]+]] -// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]] -// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG222]] -// SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x %struct.S1], ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG223:![0-9]+]] -// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] -// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]] -// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG224]] -// SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG225:![0-9]+]] -// SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] -// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG226]] -// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG226]] -// SIMD4-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG227:![0-9]+]] -// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG227]] -// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] -// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG228]] -// SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG228]] -// SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG229:![0-9]+]] -// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG230]] -// SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG230]] -// SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] -// SIMD4-NEXT: ret i32 [[TMP15]], !dbg [[DBG232:![0-9]+]] +// SIMD4-NEXT: #dbg_declare(ptr [[RES]], [[META214:![0-9]+]], !DIExpression(), [[META215:![0-9]+]]) +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG216:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]] +// SIMD4-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG218:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]] +// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG219]] +// SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG219]] +// SIMD4-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]] +// SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG221]] +// SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG221]] +// SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG222:![0-9]+]] +// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] +// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG223]] +// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG223]] +// SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([3 x [[STRUCT_S1:%.*]]], ptr getelementptr inbounds ([2 x [3 x [[STRUCT_S1]]]], ptr @arr_x, i64 0, i64 1), i64 0, i64 1), align 4, !dbg [[DBG224:![0-9]+]] +// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]] +// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG225]] +// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG225]] +// SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG226:![0-9]+]] +// SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] +// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG227]] +// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG227]] +// SIMD4-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG228:![0-9]+]] +// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG228]] +// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]] +// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG229]] +// SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG229]] +// SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG230:![0-9]+]] +// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG231]] +// SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG231]] +// SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]] +// SIMD4-NEXT: ret i32 [[TMP15]], !dbg [[DBG233:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// SIMD4-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG233:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG234:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234:![0-9]+]] -// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG234]] -// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG234]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235:![0-9]+]] +// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG235]] +// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG235]] // SIMD4: init.check: -// SIMD4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234]] -// SIMD4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG235:![0-9]+]] -// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG234]] -// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG234]] +// SIMD4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235]] +// SIMD4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG236:![0-9]+]] +// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG235]] +// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG235]] // SIMD4: init.end: -// SIMD4-NEXT: ret void, !dbg [[DBG237:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG238:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG238:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG239:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META239:![0-9]+]], !DIExpression(), [[META241:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META240:![0-9]+]], !DIExpression(), [[META242:![0-9]+]]) // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META243:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META243:![0-9]+]], !DIExpression(), [[META244:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG244:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG244]] -// SIMD4-NEXT: ret void, !dbg [[DBG245:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG245:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG245]] +// SIMD4-NEXT: ret void, !dbg [[DBG246:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG246:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG247:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META247:![0-9]+]], !DIExpression(), [[META248:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META248:![0-9]+]], !DIExpression(), [[META249:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG249:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG250:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG250:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG251:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG251:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG252:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META252:![0-9]+]], !DIExpression(), [[META253:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META253:![0-9]+]], !DIExpression(), [[META254:![0-9]+]]) // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META254:![0-9]+]], !DIExpression(), [[META255:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META255:![0-9]+]], !DIExpression(), [[META256:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG257:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG256]] -// SIMD4-NEXT: ret void, !dbg [[DBG258:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG258:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG257]] +// SIMD4-NEXT: ret void, !dbg [[DBG259:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG259:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG260:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META260:![0-9]+]], !DIExpression(), [[META261:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META261:![0-9]+]], !DIExpression(), [[META262:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] -// SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG264:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG265:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] +// SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG265:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG266:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG266:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG267:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META267:![0-9]+]], !DIExpression(), [[META268:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META268:![0-9]+]], !DIExpression(), [[META269:![0-9]+]]) // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META269:![0-9]+]], !DIExpression(), [[META270:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META270:![0-9]+]], !DIExpression(), [[META271:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG272:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG271]] -// SIMD4-NEXT: ret void, !dbg [[DBG273:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG273:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG272]] +// SIMD4-NEXT: ret void, !dbg [[DBG274:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG274:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG275:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META275:![0-9]+]], !DIExpression(), [[META276:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META276:![0-9]+]], !DIExpression(), [[META277:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] -// SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG279:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG280:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG278:![0-9]+]] +// SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG280:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG281:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG281:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG282:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META282:![0-9]+]], !DIExpression(), [[META283:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META283:![0-9]+]], !DIExpression(), [[META284:![0-9]+]]) // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META284:![0-9]+]], !DIExpression(), [[META285:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META285:![0-9]+]], !DIExpression(), [[META286:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG287:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG286]] -// SIMD4-NEXT: ret void, !dbg [[DBG288:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG288:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG287]] +// SIMD4-NEXT: ret void, !dbg [[DBG289:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG289:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG290:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META290:![0-9]+]], !DIExpression(), [[META291:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META291:![0-9]+]], !DIExpression(), [[META292:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG292:![0-9]+]] -// SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG294:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG295:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG293:![0-9]+]] +// SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG295:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG296:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG297:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META297:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META298:![0-9]+]], !DIExpression(), [[META299:![0-9]+]]) // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META300:![0-9]+]], !DIExpression(), [[META301:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG301:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG301]] -// SIMD4-NEXT: ret void, !dbg [[DBG303:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG302:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG303:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG302]] +// SIMD4-NEXT: ret void, !dbg [[DBG304:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG305:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META305:![0-9]+]], !DIExpression(), [[META306:![0-9]+]]) +// SIMD4-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META306:![0-9]+]], !DIExpression(), [[META307:![0-9]+]]) // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG307:![0-9]+]] -// SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG309:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG308:![0-9]+]] +// SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG310:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG311:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG311:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG312:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG313:![0-9]+]] -// SIMD4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG313]] -// SIMD4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG313]] +// SIMD4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG314:![0-9]+]] +// SIMD4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG314]] +// SIMD4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG314]] // SIMD4-NEXT: ret void // // @@ -6442,60 +6442,60 @@ int foobar() { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META118:![0-9]+]], !DIExpression(), [[META120:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG121:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG122:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG121]] -// DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG121]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META119:![0-9]+]], !DIExpression(), [[META121:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG122:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG123:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG122]] +// DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG122]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG124:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META124:![0-9]+]], !DIExpression(), [[META126:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META125:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META127:![0-9]+]], !DIExpression(), [[META128:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META128:![0-9]+]], !DIExpression(), [[META129:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] -// DEBUG1-NEXT: ret void, !dbg [[DBG130:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG130:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG130]] +// DEBUG1-NEXT: ret void, !dbg [[DBG131:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG131:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG132:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META132:![0-9]+]], !DIExpression(), [[META133:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META133]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]], !dbg [[META133]] -// DEBUG1-NEXT: ret void, !dbg [[DBG134:![0-9]+]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META133:![0-9]+]], !DIExpression(), [[META134:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META134]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]], !dbg [[META134]] +// DEBUG1-NEXT: ret void, !dbg [[DBG135:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG135:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG136:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META136:![0-9]+]], !DIExpression(), [[META137:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META137:![0-9]+]], !DIExpression(), [[META138:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG139:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG139:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG140:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_. -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG140:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG141:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG141:![0-9]+]] -// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG141]] -// DEBUG1-NEXT: ret void, !dbg [[DBG141]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG142:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG142]] +// DEBUG1-NEXT: ret void, !dbg [[DBG142]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG142:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG143:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 @@ -6504,332 +6504,332 @@ int foobar() { // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT7:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META143:![0-9]+]], !DIExpression(), [[META144:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG145:![0-9]+]] -// DEBUG1-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146:![0-9]+]] -// DEBUG1-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG147:![0-9]+]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG146:![0-9]+]] +// DEBUG1-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG147:![0-9]+]] +// DEBUG1-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG148:![0-9]+]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 1) -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG148:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG149:![0-9]+]] // DEBUG1: invoke.cont: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 1, !dbg [[DBG147]] -// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG147]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 1, !dbg [[DBG148]] +// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG148]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG149:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG150:![0-9]+]] // DEBUG1: invoke.cont2: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP1]], i64 2, !dbg [[DBG147]] -// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT3]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG147]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP1]], i64 2, !dbg [[DBG148]] +// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT3]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG148]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT3]], i32 noundef 3) -// DEBUG1-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]], !dbg [[DBG150:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]], !dbg [[DBG151:![0-9]+]] // DEBUG1: invoke.cont4: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 1, !dbg [[DBG146]] -// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]] -// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG151:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP1]], i64 1, !dbg [[DBG147]] +// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG147]] +// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG152:![0-9]+]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT6]], i32 noundef 4) -// DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD8:%.*]], !dbg [[DBG152:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD8:%.*]], !dbg [[DBG153:![0-9]+]] // DEBUG1: invoke.cont9: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT10:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 1, !dbg [[DBG151]] -// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT10]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG151]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT10:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 1, !dbg [[DBG152]] +// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT10]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG152]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT10]], i32 noundef 5) -// DEBUG1-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD8]], !dbg [[DBG153:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD8]], !dbg [[DBG154:![0-9]+]] // DEBUG1: invoke.cont11: -// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 2, !dbg [[DBG151]] -// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG151]] +// DEBUG1-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 2, !dbg [[DBG152]] +// DEBUG1-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG152]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 6) -// DEBUG1-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD8]], !dbg [[DBG154:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD8]], !dbg [[DBG155:![0-9]+]] // DEBUG1: invoke.cont13: -// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG145]] -// DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG145]] +// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG146]] +// DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG146]] // DEBUG1: lpad: // DEBUG1-NEXT: [[TMP3:%.*]] = landingpad { ptr, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[META144]] -// DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[META144]] -// DEBUG1-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[META144]] -// DEBUG1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[META144]] -// DEBUG1-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META144]] -// DEBUG1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG147]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP6]], !dbg [[DBG147]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG147]] +// DEBUG1-NEXT: cleanup, !dbg [[META145]] +// DEBUG1-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[META145]] +// DEBUG1-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[META145]] +// DEBUG1-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[META145]] +// DEBUG1-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META145]] +// DEBUG1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG148]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP6]], !dbg [[DBG148]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG148]] // DEBUG1: arraydestroy.body: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG147]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG147]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG147]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG147]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG147]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG148]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG148]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG148]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG148]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG148]] // DEBUG1: arraydestroy.done5: -// DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG147]] +// DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG148]] // DEBUG1: lpad8: // DEBUG1-NEXT: [[TMP7:%.*]] = landingpad { ptr, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[META144]] -// DEBUG1-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[META144]] -// DEBUG1-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[META144]] -// DEBUG1-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[META144]] -// DEBUG1-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META144]] -// DEBUG1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG151]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY14:%.*]] = icmp eq ptr [[ARRAYINIT_ELEMENT6]], [[TMP10]], !dbg [[DBG151]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY14]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15:%.*]], !dbg [[DBG151]] +// DEBUG1-NEXT: cleanup, !dbg [[META145]] +// DEBUG1-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[META145]] +// DEBUG1-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[META145]] +// DEBUG1-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[META145]] +// DEBUG1-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META145]] +// DEBUG1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG152]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY14:%.*]] = icmp eq ptr [[ARRAYINIT_ELEMENT6]], [[TMP10]], !dbg [[DBG152]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY14]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15:%.*]], !dbg [[DBG152]] // DEBUG1: arraydestroy.body15: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ], !dbg [[DBG151]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1, !dbg [[DBG151]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]], !dbg [[DBG151]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]], !dbg [[DBG151]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]], !dbg [[DBG151]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ], !dbg [[DBG152]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1, !dbg [[DBG152]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]], !dbg [[DBG152]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]], !dbg [[DBG152]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]], !dbg [[DBG152]] // DEBUG1: arraydestroy.done19: -// DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG151]] +// DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG152]] // DEBUG1: ehcleanup: -// DEBUG1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]] -// DEBUG1-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG146]] -// DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG146]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG146]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]], !dbg [[DBG146]] +// DEBUG1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG147]] +// DEBUG1-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG147]] +// DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG147]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG147]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]], !dbg [[DBG147]] // DEBUG1: arraydestroy.body21: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ], !dbg [[DBG146]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1, !dbg [[DBG146]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]], !dbg [[DBG146]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]], !dbg [[DBG146]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]], !dbg [[DBG146]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ], !dbg [[DBG147]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1, !dbg [[DBG147]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]], !dbg [[DBG147]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]], !dbg [[DBG147]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]], !dbg [[DBG147]] // DEBUG1: arraydestroy.done25: -// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG146]] +// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG147]] // DEBUG1: eh.resume: -// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG146]] -// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG146]] -// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG146]] -// DEBUG1-NEXT: [[LPAD_VAL26:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG146]] -// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL26]], !dbg [[DBG146]] +// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG147]] +// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG147]] +// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG147]] +// DEBUG1-NEXT: [[LPAD_VAL26:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG147]] +// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL26]], !dbg [[DBG147]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG155:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG156:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META156:![0-9]+]], !DIExpression(), [[META157:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META157]] -// DEBUG1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[META157]] -// DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META157]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META157:![0-9]+]], !DIExpression(), [[META158:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META158]] +// DEBUG1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[META158]] +// DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META158]] // DEBUG1: arraydestroy.body: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META157]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META157]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META157]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[META157]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META157]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META158]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META158]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META158]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[META158]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META158]] // DEBUG1: arraydestroy.done1: -// DEBUG1-NEXT: ret void, !dbg [[DBG158:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG159:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..3 -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG159:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG160:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG160:![0-9]+]] -// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2), !dbg [[DBG160]] -// DEBUG1-NEXT: ret void, !dbg [[DBG160]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG161:![0-9]+]] +// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2), !dbg [[DBG161]] +// DEBUG1-NEXT: ret void, !dbg [[DBG161]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG161:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG162:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG164:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG166:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG167:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG165:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG167:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG168:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG168:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG169:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META169:![0-9]+]], !DIExpression(), [[META170:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META170:![0-9]+]], !DIExpression(), [[META171:![0-9]+]]) // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META171:![0-9]+]], !DIExpression(), [[META172:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META172:![0-9]+]], !DIExpression(), [[META173:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG173:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG174:![0-9]+]] -// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG173]] -// DEBUG1-NEXT: ret void, !dbg [[DBG175:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG175:![0-9]+]] +// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG174]] +// DEBUG1-NEXT: ret void, !dbg [[DBG176:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG176:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG177:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META177:![0-9]+]], !DIExpression(), [[META178:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META178:![0-9]+]], !DIExpression(), [[META179:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG179:![0-9]+]] -// DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG181:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG182:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG180:![0-9]+]] +// DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG182:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG183:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG184:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG184:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG186:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG187:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG185:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG187:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG188:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG188:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG189:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META189:![0-9]+]], !DIExpression(), [[META191:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META190:![0-9]+]], !DIExpression(), [[META192:![0-9]+]]) // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META192:![0-9]+]], !DIExpression(), [[META193:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META193:![0-9]+]], !DIExpression(), [[META194:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG194]] -// DEBUG1-NEXT: ret void, !dbg [[DBG195:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG195:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG195]] +// DEBUG1-NEXT: ret void, !dbg [[DBG196:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG196:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG197:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META197:![0-9]+]], !DIExpression(), [[META198:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META198:![0-9]+]], !DIExpression(), [[META199:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG199:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG200:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG200:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG201:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG201:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG202:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META202:![0-9]+]], !DIExpression(), [[META203:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META203:![0-9]+]], !DIExpression(), [[META204:![0-9]+]]) // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META204:![0-9]+]], !DIExpression(), [[META205:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META205:![0-9]+]], !DIExpression(), [[META206:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG206:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG207:![0-9]+]] -// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG206]] -// DEBUG1-NEXT: ret void, !dbg [[DBG208:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG207:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG208:![0-9]+]] +// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG207]] +// DEBUG1-NEXT: ret void, !dbg [[DBG209:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG209:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG210:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META210:![0-9]+]], !DIExpression(), [[META211:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META211:![0-9]+]], !DIExpression(), [[META212:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]] -// DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG214:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG215:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG213:![0-9]+]] +// DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG215:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG216:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.5 -// DEBUG1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG216:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG217:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217:![0-9]+]] -// DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219:![0-9]+]] +// DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218:![0-9]+]] +// DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220:![0-9]+]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG220:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG221:![0-9]+]] // DEBUG1: invoke.cont: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG221:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG222:![0-9]+]] // DEBUG1: invoke.cont2: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// DEBUG1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG222:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG223:![0-9]+]] // DEBUG1: invoke.cont3: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217]] -// DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223:![0-9]+]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// DEBUG1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG224:![0-9]+]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224:![0-9]+]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) +// DEBUG1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG225:![0-9]+]] // DEBUG1: invoke.cont7: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// DEBUG1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG225:![0-9]+]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// DEBUG1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG226:![0-9]+]] // DEBUG1: invoke.cont8: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] -// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG226:![0-9]+]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]] +// DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG227:![0-9]+]] // DEBUG1: invoke.cont9: -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG227:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG227]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG228:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG228]] // DEBUG1: lpad: // DEBUG1-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[DBG228:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG228]] -// DEBUG1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG228]] -// DEBUG1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG219]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG219]] +// DEBUG1-NEXT: cleanup, !dbg [[DBG229:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG229]] +// DEBUG1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG229]] +// DEBUG1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG220]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG220]] // DEBUG1: arraydestroy.body: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG219]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG219]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG219]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG219]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG219]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG220]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG220]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG220]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG220]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG220]] // DEBUG1: arraydestroy.done4: -// DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG219]] +// DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG220]] // DEBUG1: lpad6: // DEBUG1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG228]] -// DEBUG1-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG228]] -// DEBUG1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG223]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG223]] +// DEBUG1-NEXT: cleanup, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG229]] +// DEBUG1-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG229]] +// DEBUG1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG224]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG224]] // DEBUG1: arraydestroy.body11: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG223]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG223]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG223]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG223]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG223]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG224]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG224]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG224]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), !dbg [[DBG224]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG224]] // DEBUG1: arraydestroy.done15: -// DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG223]] +// DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG224]] // DEBUG1: ehcleanup: -// DEBUG1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217]] -// DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG217]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG217]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG217]] +// DEBUG1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218]] +// DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG218]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG218]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG218]] // DEBUG1: arraydestroy.body17: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG217]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG217]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG217]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG217]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG217]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG218]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG218]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG218]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG218]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG218]] // DEBUG1: arraydestroy.done21: -// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG217]] +// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG218]] // DEBUG1: eh.resume: -// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG217]] -// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG217]] -// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG217]] -// DEBUG1-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG217]] -// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG217]] +// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG218]] +// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG218]] +// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG218]] +// DEBUG1-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG218]] +// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG218]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG229:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG230:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META232:![0-9]+]], !DIExpression(), [[META233:![0-9]+]]) -// DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META233]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META233:![0-9]+]], !DIExpression(), [[META234:![0-9]+]]) +// DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META234]] // DEBUG1: arraydestroy.body: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META233]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META233]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META233]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META233]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META233]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META234]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META234]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META234]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META234]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META234]] // DEBUG1: arraydestroy.done1: -// DEBUG1-NEXT: ret void, !dbg [[META233]] +// DEBUG1-NEXT: ret void, !dbg [[META234]] // // // DEBUG1-LABEL: define {{[^@]+}}@main @@ -6839,337 +6839,337 @@ int foobar() { // DEBUG1-NEXT: [[RES:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]), !dbg [[DBG234:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]), !dbg [[DBG235:![0-9]+]] // DEBUG1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[RES]], [[META235:![0-9]+]], !DIExpression(), [[META236:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG237:![0-9]+]] -// DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG237]] -// DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG237]], !prof [[PROF238:![0-9]+]] +// DEBUG1-NEXT: #dbg_declare(ptr [[RES]], [[META236:![0-9]+]], !DIExpression(), [[META237:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG238:![0-9]+]] +// DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG238]] +// DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG238]], !prof [[PROF239:![0-9]+]] // DEBUG1: init.check: -// DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG237]] -// DEBUG1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG237]] -// DEBUG1-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG237]] +// DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG238]] +// DEBUG1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG238]] +// DEBUG1-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG238]] // DEBUG1: init: -// DEBUG1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG237]] -// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7), !dbg [[DBG237]] -// DEBUG1-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG234]] -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG239:![0-9]+]] -// DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG239]] +// DEBUG1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG238]] +// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7), !dbg [[DBG238]] +// DEBUG1-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG235]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG240:![0-9]+]] +// DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG240]] // DEBUG1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]]) -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG240:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG241:![0-9]+]] // DEBUG1: invoke.cont: -// DEBUG1-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG237]] -// DEBUG1-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG237]] -// DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG237]] +// DEBUG1-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG238]] +// DEBUG1-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG238]] +// DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG238]] // DEBUG1: init.end: -// DEBUG1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG241:![0-9]+]] -// DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG242:![0-9]+]] -// DEBUG1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG242]] -// DEBUG1-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG243:![0-9]+]] -// DEBUG1-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG244:![0-9]+]] -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG245:![0-9]+]] -// DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG245]] -// DEBUG1-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG246:![0-9]+]] -// DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG246]] -// DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG246]] -// DEBUG1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG247:![0-9]+]] -// DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG248:![0-9]+]] -// DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG248]] -// DEBUG1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG249:![0-9]+]] -// DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG249]] -// DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG249]] -// DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG250:![0-9]+]] -// DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG251:![0-9]+]] -// DEBUG1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG251]] -// DEBUG1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG251]] -// DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG252:![0-9]+]] -// DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG253:![0-9]+]] -// DEBUG1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG253]] -// DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG254:![0-9]+]] -// DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG254]] -// DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG254]] -// DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG255:![0-9]+]] -// DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG255]] -// DEBUG1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG255]] -// DEBUG1-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] -// DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG256]] -// DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG257:![0-9]+]] -// DEBUG1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG257]] -// DEBUG1-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG257]] -// DEBUG1-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG258:![0-9]+]] -// DEBUG1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG258]] -// DEBUG1-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG259:![0-9]+]] -// DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG259]] -// DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG259]] -// DEBUG1-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG260:![0-9]+]] -// DEBUG1-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG260]] -// DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG260]] -// DEBUG1-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG261:![0-9]+]] -// DEBUG1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG261]] -// DEBUG1-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG261]] -// DEBUG1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG262:![0-9]+]] -// DEBUG1-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] -// DEBUG1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG263]] -// DEBUG1-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG264:![0-9]+]] -// DEBUG1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG264]] -// DEBUG1-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG264]] -// DEBUG1-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG265:![0-9]+]] -// DEBUG1-NEXT: ret i32 [[TMP32]], !dbg [[DBG266:![0-9]+]] +// DEBUG1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG242:![0-9]+]] +// DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG243:![0-9]+]] +// DEBUG1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG243]] +// DEBUG1-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG244:![0-9]+]] +// DEBUG1-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG245:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG246:![0-9]+]] +// DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG246]] +// DEBUG1-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG247:![0-9]+]] +// DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG247]] +// DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG247]] +// DEBUG1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG248:![0-9]+]] +// DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG249:![0-9]+]] +// DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG249]] +// DEBUG1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG250:![0-9]+]] +// DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG250]] +// DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG250]] +// DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG251:![0-9]+]] +// DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG252:![0-9]+]] +// DEBUG1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG252]] +// DEBUG1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG252]] +// DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG253:![0-9]+]] +// DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG254:![0-9]+]] +// DEBUG1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG254]] +// DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG255:![0-9]+]] +// DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG255]] +// DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG255]] +// DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG256:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG256]] +// DEBUG1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG256]] +// DEBUG1-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]] +// DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG257]] +// DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG258:![0-9]+]] +// DEBUG1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG258]] +// DEBUG1-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG258]] +// DEBUG1-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG259:![0-9]+]] +// DEBUG1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG259]] +// DEBUG1-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG260:![0-9]+]] +// DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG260]] +// DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG260]] +// DEBUG1-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG261:![0-9]+]] +// DEBUG1-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG261]] +// DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG261]] +// DEBUG1-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG262:![0-9]+]] +// DEBUG1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG262]] +// DEBUG1-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG262]] +// DEBUG1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG263:![0-9]+]] +// DEBUG1-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG264:![0-9]+]] +// DEBUG1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG264]] +// DEBUG1-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG265:![0-9]+]] +// DEBUG1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG265]] +// DEBUG1-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG265]] +// DEBUG1-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG266:![0-9]+]] +// DEBUG1-NEXT: ret i32 [[TMP32]], !dbg [[DBG267:![0-9]+]] // DEBUG1: lpad: // DEBUG1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[DBG267:![0-9]+]] -// DEBUG1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG267]] -// DEBUG1-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG267]] -// DEBUG1-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG267]] -// DEBUG1-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG267]] -// DEBUG1-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG237]] -// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG237]] +// DEBUG1-NEXT: cleanup, !dbg [[DBG268:![0-9]+]] +// DEBUG1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG268]] +// DEBUG1-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]] +// DEBUG1-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG268]] +// DEBUG1-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]] +// DEBUG1-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG238]] +// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG238]] // DEBUG1: eh.resume: -// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG237]] -// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG237]] -// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG237]] -// DEBUG1-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG237]] -// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG237]] +// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG238]] +// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG238]] +// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG238]] +// DEBUG1-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG238]] +// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG238]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG268:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG269:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG269:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG270:![0-9]+]] // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META270:![0-9]+]], !DIExpression(), [[META271:![0-9]+]]) -// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG272:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG269]] -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG273:![0-9]+]] -// DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG273]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG274:![0-9]+]] -// DEBUG1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG272]] -// DEBUG1-NEXT: ret ptr [[TMP5]], !dbg [[DBG272]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META271:![0-9]+]], !DIExpression(), [[META272:![0-9]+]]) +// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG273:![0-9]+]] +// DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG270]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG274:![0-9]+]] +// DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG274]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG275:![0-9]+]] +// DEBUG1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG273]] +// DEBUG1-NEXT: ret ptr [[TMP5]], !dbg [[DBG273]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG275:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG276:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META276:![0-9]+]], !DIExpression(), [[META278:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META277:![0-9]+]], !DIExpression(), [[META279:![0-9]+]]) // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META279:![0-9]+]], !DIExpression(), [[META280:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META280:![0-9]+]], !DIExpression(), [[META281:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG281:![0-9]+]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG281]] -// DEBUG1-NEXT: ret void, !dbg [[DBG282:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG282:![0-9]+]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG282]] +// DEBUG1-NEXT: ret void, !dbg [[DBG283:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG283:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG284:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META284:![0-9]+]], !DIExpression(), [[META285:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META285]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]], !dbg [[META285]] -// DEBUG1-NEXT: ret void, !dbg [[DBG286:![0-9]+]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META285:![0-9]+]], !DIExpression(), [[META286:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META286]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[TMP1]]) #[[ATTR3]], !dbg [[META286]] +// DEBUG1-NEXT: ret void, !dbg [[DBG287:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG287:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG288:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META288:![0-9]+]], !DIExpression(), [[META289:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META289:![0-9]+]], !DIExpression(), [[META290:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG290:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG291:![0-9]+]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG291:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG292:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG292:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG293:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META293:![0-9]+]], !DIExpression(), [[META294:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META294:![0-9]+]], !DIExpression(), [[META295:![0-9]+]]) // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META295:![0-9]+]], !DIExpression(), [[META296:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META296:![0-9]+]], !DIExpression(), [[META297:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG297:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG298:![0-9]+]] -// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG297]] -// DEBUG1-NEXT: ret void, !dbg [[DBG299:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG298:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG299:![0-9]+]] +// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG298]] +// DEBUG1-NEXT: ret void, !dbg [[DBG300:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG300:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG301:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META301:![0-9]+]], !DIExpression(), [[META302:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META302:![0-9]+]], !DIExpression(), [[META303:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG303:![0-9]+]] -// DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG305:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG306:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG304:![0-9]+]] +// DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG306:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG307:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_Z6foobarv -// DEBUG1-SAME: () #[[ATTR2]] !dbg [[DBG307:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR2]] !dbg [[DBG308:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[RES:%.*]] = alloca i32, align 4 -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]), !dbg [[DBG308:![0-9]+]] -// DEBUG1-NEXT: #dbg_declare(ptr [[RES]], [[META309:![0-9]+]], !DIExpression(), [[META310:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG308]] -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG311:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG311]] -// DEBUG1-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG312:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG313:![0-9]+]] -// DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]] -// DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG314]] -// DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG315:![0-9]+]] -// DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG315]] -// DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG315]] -// DEBUG1-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG316:![0-9]+]] -// DEBUG1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG317:![0-9]+]] -// DEBUG1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG317]] -// DEBUG1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG317]] -// DEBUG1-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG318:![0-9]+]] -// DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] -// DEBUG1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG319]] -// DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG320:![0-9]+]] -// DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG320]] -// DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG320]] -// DEBUG1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG321:![0-9]+]] -// DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG321]] -// DEBUG1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG321]] -// DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG322:![0-9]+]] -// DEBUG1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG322]] -// DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG323:![0-9]+]] -// DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG323]] -// DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG323]] -// DEBUG1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG324:![0-9]+]] -// DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG324]] -// DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG325:![0-9]+]] -// DEBUG1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG325]] -// DEBUG1-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG325]] -// DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG326:![0-9]+]] -// DEBUG1-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG326]] -// DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG326]] -// DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG327:![0-9]+]] -// DEBUG1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG327]] -// DEBUG1-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG327]] -// DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG328:![0-9]+]] -// DEBUG1-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG329:![0-9]+]] -// DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG329]] -// DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG330:![0-9]+]] -// DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG330]] -// DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG330]] -// DEBUG1-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG331:![0-9]+]] -// DEBUG1-NEXT: ret i32 [[TMP23]], !dbg [[DBG332:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]), !dbg [[DBG309:![0-9]+]] +// DEBUG1-NEXT: #dbg_declare(ptr [[RES]], [[META310:![0-9]+]], !DIExpression(), [[META311:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG309]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG312:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG312]] +// DEBUG1-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG313:![0-9]+]] +// DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG314:![0-9]+]] +// DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG315:![0-9]+]] +// DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG315]] +// DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG316:![0-9]+]] +// DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG316]] +// DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG316]] +// DEBUG1-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG317:![0-9]+]] +// DEBUG1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG318:![0-9]+]] +// DEBUG1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG318]] +// DEBUG1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG318]] +// DEBUG1-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG319:![0-9]+]] +// DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]] +// DEBUG1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG320]] +// DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG321:![0-9]+]] +// DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG321]] +// DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG321]] +// DEBUG1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG322:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG322]] +// DEBUG1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG322]] +// DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG323:![0-9]+]] +// DEBUG1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG323]] +// DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG324:![0-9]+]] +// DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG324]] +// DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG324]] +// DEBUG1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG325:![0-9]+]] +// DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG325]] +// DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG326:![0-9]+]] +// DEBUG1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG326]] +// DEBUG1-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG326]] +// DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG327:![0-9]+]] +// DEBUG1-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG327]] +// DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG327]] +// DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG328:![0-9]+]] +// DEBUG1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG328]] +// DEBUG1-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG328]] +// DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG329:![0-9]+]] +// DEBUG1-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG330:![0-9]+]] +// DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG330]] +// DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG331:![0-9]+]] +// DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG331]] +// DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG331]] +// DEBUG1-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG332:![0-9]+]] +// DEBUG1-NEXT: ret i32 [[TMP23]], !dbg [[DBG333:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.8 -// DEBUG1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG333:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG334:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG334:![0-9]+]] -// DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG334]] -// DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG334]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG335:![0-9]+]] +// DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG335]] +// DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG335]] // DEBUG1: init.check: -// DEBUG1-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG334]] -// DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG334]] -// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10), !dbg [[DBG334]] -// DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG335:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG334]] -// DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG334]] +// DEBUG1-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG335]] +// DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG335]] +// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10), !dbg [[DBG335]] +// DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG336:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG335]] +// DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG335]] // DEBUG1: init.end: -// DEBUG1-NEXT: ret void, !dbg [[DBG337:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG338:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG338:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG339:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META339:![0-9]+]], !DIExpression(), [[META340:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG341:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG342:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG341]] -// DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG341]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META340:![0-9]+]], !DIExpression(), [[META341:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG342:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG343:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG342]] +// DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG342]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG343:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG344:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META344:![0-9]+]], !DIExpression(), [[META346:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META345:![0-9]+]], !DIExpression(), [[META347:![0-9]+]]) // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META347:![0-9]+]], !DIExpression(), [[META348:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META348:![0-9]+]], !DIExpression(), [[META349:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG349:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG349]] -// DEBUG1-NEXT: ret void, !dbg [[DBG350:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG350:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG350]] +// DEBUG1-NEXT: ret void, !dbg [[DBG351:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG351:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG352:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META352:![0-9]+]], !DIExpression(), [[META353:![0-9]+]]) -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META353]] -// DEBUG1-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]], !dbg [[META353]] -// DEBUG1-NEXT: ret void, !dbg [[DBG354:![0-9]+]] +// DEBUG1-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META353:![0-9]+]], !DIExpression(), [[META354:![0-9]+]]) +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META354]] +// DEBUG1-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[TMP1]]) #[[ATTR3]], !dbg [[META354]] +// DEBUG1-NEXT: ret void, !dbg [[DBG355:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG355:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG356:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META356:![0-9]+]], !DIExpression(), [[META357:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META357:![0-9]+]], !DIExpression(), [[META358:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG358:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG359:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG359:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG360:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG360:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG361:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META361:![0-9]+]], !DIExpression(), [[META362:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META362:![0-9]+]], !DIExpression(), [[META363:![0-9]+]]) // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META363:![0-9]+]], !DIExpression(), [[META364:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META364:![0-9]+]], !DIExpression(), [[META365:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG365:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG366:![0-9]+]] -// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG365]] -// DEBUG1-NEXT: ret void, !dbg [[DBG367:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG366:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG367:![0-9]+]] +// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG366]] +// DEBUG1-NEXT: ret void, !dbg [[DBG368:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG368:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG369:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META369:![0-9]+]], !DIExpression(), [[META370:![0-9]+]]) +// DEBUG1-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META370:![0-9]+]], !DIExpression(), [[META371:![0-9]+]]) // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG371:![0-9]+]] -// DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG373:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG374:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG372:![0-9]+]] +// DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG374:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG375:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG375:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG376:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG376:![0-9]+]] -// DEBUG1-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG376]] -// DEBUG1-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG376]] -// DEBUG1-NEXT: call void @__cxx_global_var_init.5(), !dbg [[DBG376]] -// DEBUG1-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG376]] +// DEBUG1-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG377:![0-9]+]] +// DEBUG1-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG377]] +// DEBUG1-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG377]] +// DEBUG1-NEXT: call void @__cxx_global_var_init.5(), !dbg [[DBG377]] +// DEBUG1-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG377]] // DEBUG1-NEXT: ret void // // @@ -7188,181 +7188,181 @@ int foobar() { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META125:![0-9]+]], !DIExpression(), [[META127:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG128:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG129:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG128]] -// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG128]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META126:![0-9]+]], !DIExpression(), [[META128:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG129:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG130:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG129]] +// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG129]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META131:![0-9]+]], !DIExpression(), [[META133:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META132:![0-9]+]], !DIExpression(), [[META134:![0-9]+]]) // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META134:![0-9]+]], !DIExpression(), [[META135:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META135:![0-9]+]], !DIExpression(), [[META136:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG136:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG136]] -// DEBUG2-NEXT: ret void, !dbg [[DBG137:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG137:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG137]] +// DEBUG2-NEXT: ret void, !dbg [[DBG138:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG138:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG139:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META139:![0-9]+]], !DIExpression(), [[META140:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META140]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]], !dbg [[META140]] -// DEBUG2-NEXT: ret void, !dbg [[DBG141:![0-9]+]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META140:![0-9]+]], !DIExpression(), [[META141:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META141]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[TMP1]]) #[[ATTR3]], !dbg [[META141]] +// DEBUG2-NEXT: ret void, !dbg [[DBG142:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG142:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG143:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META143:![0-9]+]], !DIExpression(), [[META144:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META144:![0-9]+]], !DIExpression(), [[META145:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG145:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG146:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG146:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG147:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG147:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG148:![0-9]+]] { // DEBUG2-NEXT: entry: -// DEBUG2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG148:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG150:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG151:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG149:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG152:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG152:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG153:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META153:![0-9]+]], !DIExpression(), [[META155:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META154:![0-9]+]], !DIExpression(), [[META156:![0-9]+]]) // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META156:![0-9]+]], !DIExpression(), [[META157:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META157:![0-9]+]], !DIExpression(), [[META158:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG158:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG158]] -// DEBUG2-NEXT: ret void, !dbg [[DBG159:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG159:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG159]] +// DEBUG2-NEXT: ret void, !dbg [[DBG160:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG160:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG161:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META161:![0-9]+]], !DIExpression(), [[META162:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META162:![0-9]+]], !DIExpression(), [[META163:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG163:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG164:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG165:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// DEBUG2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG165:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG166:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG166:![0-9]+]] -// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..3, ptr null, ptr @.__kmpc_global_dtor_..4), !dbg [[DBG166]] -// DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167:![0-9]+]] -// DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG167:![0-9]+]] +// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..3, ptr null, ptr @.__kmpc_global_dtor_..4), !dbg [[DBG167]] +// DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168:![0-9]+]] +// DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170:![0-9]+]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG170:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG171:![0-9]+]] // DEBUG2: invoke.cont: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG171:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG172:![0-9]+]] // DEBUG2: invoke.cont2: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG172:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG173:![0-9]+]] // DEBUG2: invoke.cont3: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167]] -// DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173:![0-9]+]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// DEBUG2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG174:![0-9]+]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174:![0-9]+]] +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i32 noundef 4) +// DEBUG2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG175:![0-9]+]] // DEBUG2: invoke.cont7: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// DEBUG2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG175:![0-9]+]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]] +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 1), i32 noundef 5) +// DEBUG2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG176:![0-9]+]] // DEBUG2: invoke.cont8: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] -// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG176:![0-9]+]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]] +// DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), i64 2), i32 noundef 6) +// DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG177:![0-9]+]] // DEBUG2: invoke.cont9: -// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG166]] -// DEBUG2-NEXT: ret void, !dbg [[DBG166]] +// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG167]] +// DEBUG2-NEXT: ret void, !dbg [[DBG167]] // DEBUG2: lpad: // DEBUG2-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[DBG177:![0-9]+]] -// DEBUG2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG177]] -// DEBUG2-NEXT: store ptr [[TMP3]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 1, !dbg [[DBG177]] -// DEBUG2-NEXT: store i32 [[TMP4]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP5]], !dbg [[DBG169]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG169]] +// DEBUG2-NEXT: cleanup, !dbg [[DBG178:![0-9]+]] +// DEBUG2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG178]] +// DEBUG2-NEXT: store ptr [[TMP3]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 1, !dbg [[DBG178]] +// DEBUG2-NEXT: store i32 [[TMP4]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP5]], !dbg [[DBG170]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG170]] // DEBUG2: arraydestroy.body: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG169]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG169]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG169]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG169]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG169]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG170]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG170]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG170]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG170]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG170]] // DEBUG2: arraydestroy.done4: -// DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG169]] +// DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG170]] // DEBUG2: lpad6: // DEBUG2-NEXT: [[TMP6:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 0, !dbg [[DBG177]] -// DEBUG2-NEXT: store ptr [[TMP7]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 1, !dbg [[DBG177]] -// DEBUG2-NEXT: store i32 [[TMP8]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP9]], !dbg [[DBG173]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG173]] +// DEBUG2-NEXT: cleanup, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 0, !dbg [[DBG178]] +// DEBUG2-NEXT: store ptr [[TMP7]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 1, !dbg [[DBG178]] +// DEBUG2-NEXT: store i32 [[TMP8]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), [[TMP9]], !dbg [[DBG174]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG174]] // DEBUG2: arraydestroy.body11: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP9]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG173]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG173]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG173]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG173]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG173]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP9]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG174]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG174]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG174]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x [[STRUCT_S1]]], ptr @arr_x, i64 1), !dbg [[DBG174]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG174]] // DEBUG2: arraydestroy.done15: -// DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG173]] +// DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG174]] // DEBUG2: ehcleanup: -// DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167]] -// DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP10]], i64 0, i64 0, !dbg [[DBG167]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG167]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG167]] +// DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168]] +// DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP10]], i64 0, i64 0, !dbg [[DBG168]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG168]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG168]] // DEBUG2: arraydestroy.body17: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG167]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG167]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG167]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG167]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG167]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG168]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG168]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG168]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG168]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG168]] // DEBUG2: arraydestroy.done21: -// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG167]] +// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG168]] // DEBUG2: eh.resume: -// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG167]] -// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG167]] -// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG167]] -// DEBUG2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG167]] -// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG167]] +// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG168]] +// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG168]] +// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG168]] +// DEBUG2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG168]] +// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG168]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..3 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG178:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG179:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 @@ -7371,133 +7371,133 @@ int foobar() { // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT7:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META179:![0-9]+]], !DIExpression(), [[META180:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG181:![0-9]+]] -// DEBUG2-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182:![0-9]+]] -// DEBUG2-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG183:![0-9]+]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META180:![0-9]+]], !DIExpression(), [[META181:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG182:![0-9]+]] +// DEBUG2-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183:![0-9]+]] +// DEBUG2-NEXT: store ptr [[TMP1]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG184:![0-9]+]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 1) -// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG184:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG185:![0-9]+]] // DEBUG2: invoke.cont: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 1, !dbg [[DBG183]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 1, !dbg [[DBG184]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG184]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG185:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG186:![0-9]+]] // DEBUG2: invoke.cont2: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP1]], i64 2, !dbg [[DBG183]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT3]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP1]], i64 2, !dbg [[DBG184]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT3]], ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG184]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT3]], i32 noundef 3) -// DEBUG2-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]], !dbg [[DBG186:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT4:%.*]] unwind label [[LPAD]], !dbg [[DBG187:![0-9]+]] // DEBUG2: invoke.cont4: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 1, !dbg [[DBG182]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG187:![0-9]+]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT6:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP1]], i64 1, !dbg [[DBG183]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT6]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG188:![0-9]+]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT6]], i32 noundef 4) -// DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD8:%.*]], !dbg [[DBG188:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD8:%.*]], !dbg [[DBG189:![0-9]+]] // DEBUG2: invoke.cont9: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT10:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 1, !dbg [[DBG187]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT10]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG187]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT10:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 1, !dbg [[DBG188]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT10]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG188]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT10]], i32 noundef 5) -// DEBUG2-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD8]], !dbg [[DBG189:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD8]], !dbg [[DBG190:![0-9]+]] // DEBUG2: invoke.cont11: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 2, !dbg [[DBG187]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG187]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT6]], i64 2, !dbg [[DBG188]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG188]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 6) -// DEBUG2-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD8]], !dbg [[DBG190:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD8]], !dbg [[DBG191:![0-9]+]] // DEBUG2: invoke.cont13: -// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG181]] -// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG181]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG182]] +// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG182]] // DEBUG2: lpad: // DEBUG2-NEXT: [[TMP3:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[META180]] -// DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[META180]] -// DEBUG2-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[META180]] -// DEBUG2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[META180]] -// DEBUG2-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META180]] -// DEBUG2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG183]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP6]], !dbg [[DBG183]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG183]] +// DEBUG2-NEXT: cleanup, !dbg [[META181]] +// DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[META181]] +// DEBUG2-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[META181]] +// DEBUG2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[META181]] +// DEBUG2-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META181]] +// DEBUG2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG184]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP6]], !dbg [[DBG184]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG184]] // DEBUG2: arraydestroy.body: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG183]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG183]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG183]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG183]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG184]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG184]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG184]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG184]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG184]] // DEBUG2: arraydestroy.done5: -// DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG183]] +// DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG184]] // DEBUG2: lpad8: // DEBUG2-NEXT: [[TMP7:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[META180]] -// DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[META180]] -// DEBUG2-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[META180]] -// DEBUG2-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[META180]] -// DEBUG2-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META180]] -// DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG187]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY14:%.*]] = icmp eq ptr [[ARRAYINIT_ELEMENT6]], [[TMP10]], !dbg [[DBG187]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY14]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15:%.*]], !dbg [[DBG187]] +// DEBUG2-NEXT: cleanup, !dbg [[META181]] +// DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[META181]] +// DEBUG2-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[META181]] +// DEBUG2-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[META181]] +// DEBUG2-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[META181]] +// DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT7]], align 8, !dbg [[DBG188]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY14:%.*]] = icmp eq ptr [[ARRAYINIT_ELEMENT6]], [[TMP10]], !dbg [[DBG188]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY14]], label [[ARRAYDESTROY_DONE19:%.*]], label [[ARRAYDESTROY_BODY15:%.*]], !dbg [[DBG188]] // DEBUG2: arraydestroy.body15: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ], !dbg [[DBG187]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1, !dbg [[DBG187]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]], !dbg [[DBG187]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]], !dbg [[DBG187]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]], !dbg [[DBG187]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST16:%.*]] = phi ptr [ [[TMP10]], [[LPAD8]] ], [ [[ARRAYDESTROY_ELEMENT17:%.*]], [[ARRAYDESTROY_BODY15]] ], !dbg [[DBG188]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT17]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST16]], i64 -1, !dbg [[DBG188]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT17]]) #[[ATTR3]], !dbg [[DBG188]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE18:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT17]], [[ARRAYINIT_ELEMENT6]], !dbg [[DBG188]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE18]], label [[ARRAYDESTROY_DONE19]], label [[ARRAYDESTROY_BODY15]], !dbg [[DBG188]] // DEBUG2: arraydestroy.done19: -// DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG187]] +// DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG188]] // DEBUG2: ehcleanup: -// DEBUG2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] -// DEBUG2-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG182]] -// DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG182]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG182]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]], !dbg [[DBG182]] +// DEBUG2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG183]] +// DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY20:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG183]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY20]], label [[ARRAYDESTROY_DONE25:%.*]], label [[ARRAYDESTROY_BODY21:%.*]], !dbg [[DBG183]] // DEBUG2: arraydestroy.body21: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ], !dbg [[DBG182]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1, !dbg [[DBG182]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]], !dbg [[DBG182]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]], !dbg [[DBG182]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]], !dbg [[DBG182]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST22:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT23:%.*]], [[ARRAYDESTROY_BODY21]] ], !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT23]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST22]], i64 -1, !dbg [[DBG183]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT23]]) #[[ATTR3]], !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE24:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT23]], [[PAD_ARRAYBEGIN]], !dbg [[DBG183]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE24]], label [[ARRAYDESTROY_DONE25]], label [[ARRAYDESTROY_BODY21]], !dbg [[DBG183]] // DEBUG2: arraydestroy.done25: -// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG182]] +// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG183]] // DEBUG2: eh.resume: -// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG182]] -// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG182]] -// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG182]] -// DEBUG2-NEXT: [[LPAD_VAL26:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG182]] -// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL26]], !dbg [[DBG182]] +// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG183]] +// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG183]] +// DEBUG2-NEXT: [[LPAD_VAL26:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG183]] +// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL26]], !dbg [[DBG183]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..4 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG191:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG192:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META192:![0-9]+]], !DIExpression(), [[META193:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META193]] -// DEBUG2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[META193]] -// DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META193]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META193:![0-9]+]], !DIExpression(), [[META194:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META194]] +// DEBUG2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[META194]] +// DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META194]] // DEBUG2: arraydestroy.body: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META193]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META193]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META193]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[META193]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META193]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META194]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META194]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META194]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[META194]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META194]] // DEBUG2: arraydestroy.done1: -// DEBUG2-NEXT: ret void, !dbg [[DBG194:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG195:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG195:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG196:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META198:![0-9]+]], !DIExpression(), [[META199:![0-9]+]]) -// DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META199]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META199:![0-9]+]], !DIExpression(), [[META200:![0-9]+]]) +// DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[META200]] // DEBUG2: arraydestroy.body: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META199]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META199]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META199]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META199]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META199]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[META200]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[META200]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[META200]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[META200]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[META200]] // DEBUG2: arraydestroy.done1: -// DEBUG2-NEXT: ret void, !dbg [[META199]] +// DEBUG2-NEXT: ret void, !dbg [[META200]] // // // DEBUG2-LABEL: define {{[^@]+}}@main @@ -7507,390 +7507,390 @@ int foobar() { // DEBUG2-NEXT: [[RES:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 -// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]), !dbg [[DBG200:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]), !dbg [[DBG201:![0-9]+]] // DEBUG2-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[RES]], [[META201:![0-9]+]], !DIExpression(), [[META202:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG203:![0-9]+]] -// DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG203]] -// DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG203]], !prof [[PROF204:![0-9]+]] +// DEBUG2-NEXT: #dbg_declare(ptr [[RES]], [[META202:![0-9]+]], !DIExpression(), [[META203:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG204:![0-9]+]] +// DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG204]] +// DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG204]], !prof [[PROF205:![0-9]+]] // DEBUG2: init.check: -// DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG203]] -// DEBUG2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG203]] -// DEBUG2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG203]] +// DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG204]] +// DEBUG2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG204]] +// DEBUG2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG204]] // DEBUG2: init: -// DEBUG2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG203]] -// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..5, ptr null, ptr @.__kmpc_global_dtor_..6), !dbg [[DBG203]] -// DEBUG2-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG200]] -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG205:![0-9]+]] -// DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG205]] +// DEBUG2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG204]] +// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..5, ptr null, ptr @.__kmpc_global_dtor_..6), !dbg [[DBG204]] +// DEBUG2-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG201]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG206:![0-9]+]] +// DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG206]] // DEBUG2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]]) -// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG206:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG207:![0-9]+]] // DEBUG2: invoke.cont: -// DEBUG2-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG203]] -// DEBUG2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG203]] -// DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG203]] +// DEBUG2-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG204]] +// DEBUG2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG204]] +// DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG204]] // DEBUG2: init.end: -// DEBUG2-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG207:![0-9]+]] -// DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG208:![0-9]+]] -// DEBUG2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG208]] -// DEBUG2-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG209:![0-9]+]] -// DEBUG2-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG210:![0-9]+]] -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG211:![0-9]+]] -// DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG211]] -// DEBUG2-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG212:![0-9]+]] -// DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG212]] -// DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG212]] -// DEBUG2-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG213:![0-9]+]] -// DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]] -// DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG214]] -// DEBUG2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG215:![0-9]+]] -// DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG215]] -// DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG215]] -// DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG216:![0-9]+]] -// DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]] -// DEBUG2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG217]] -// DEBUG2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG217]] -// DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG218:![0-9]+]] -// DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG219:![0-9]+]] -// DEBUG2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG219]] -// DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG220]] -// DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG220]] -// DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG221:![0-9]+]] -// DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG221]] -// DEBUG2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG221]] -// DEBUG2-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG222:![0-9]+]] -// DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG222]] -// DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] -// DEBUG2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG223]] -// DEBUG2-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG223]] -// DEBUG2-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG224:![0-9]+]] -// DEBUG2-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG224]] -// DEBUG2-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]] -// DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG225]] -// DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG225]] -// DEBUG2-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG226:![0-9]+]] -// DEBUG2-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG226]] -// DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG226]] -// DEBUG2-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] -// DEBUG2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG227]] -// DEBUG2-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG227]] -// DEBUG2-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG228:![0-9]+]] -// DEBUG2-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG229:![0-9]+]] -// DEBUG2-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG229]] -// DEBUG2-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// DEBUG2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG230]] -// DEBUG2-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG230]] -// DEBUG2-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] -// DEBUG2-NEXT: ret i32 [[TMP32]], !dbg [[DBG232:![0-9]+]] +// DEBUG2-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG208:![0-9]+]] +// DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG209:![0-9]+]] +// DEBUG2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG209]] +// DEBUG2-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG210:![0-9]+]] +// DEBUG2-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG211:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]] +// DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG212]] +// DEBUG2-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG213:![0-9]+]] +// DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG213]] +// DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG213]] +// DEBUG2-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG214:![0-9]+]] +// DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG215:![0-9]+]] +// DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG215]] +// DEBUG2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] +// DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG216]] +// DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG216]] +// DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG217:![0-9]+]] +// DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] +// DEBUG2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG218]] +// DEBUG2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG218]] +// DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG219:![0-9]+]] +// DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG220:![0-9]+]] +// DEBUG2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG220]] +// DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG221]] +// DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG221]] +// DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG222:![0-9]+]] +// DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG222]] +// DEBUG2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG222]] +// DEBUG2-NEXT: [[A9:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG223:![0-9]+]] +// DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG223]] +// DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] +// DEBUG2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG224]] +// DEBUG2-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG224]] +// DEBUG2-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG225:![0-9]+]] +// DEBUG2-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG225]] +// DEBUG2-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] +// DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG226]] +// DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG226]] +// DEBUG2-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG227:![0-9]+]] +// DEBUG2-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG227]] +// DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG227]] +// DEBUG2-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] +// DEBUG2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG228]] +// DEBUG2-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG228]] +// DEBUG2-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG229:![0-9]+]] +// DEBUG2-NEXT: [[A13:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG230:![0-9]+]] +// DEBUG2-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG230]] +// DEBUG2-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// DEBUG2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG231]] +// DEBUG2-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG231]] +// DEBUG2-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]] +// DEBUG2-NEXT: ret i32 [[TMP32]], !dbg [[DBG233:![0-9]+]] // DEBUG2: lpad: // DEBUG2-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[DBG233:![0-9]+]] -// DEBUG2-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG233]] -// DEBUG2-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG233]] -// DEBUG2-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG233]] -// DEBUG2-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG233]] -// DEBUG2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG203]] -// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG203]] +// DEBUG2-NEXT: cleanup, !dbg [[DBG234:![0-9]+]] +// DEBUG2-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG234]] +// DEBUG2-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG234]] +// DEBUG2-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG234]] +// DEBUG2-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG234]] +// DEBUG2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG204]] +// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG204]] // DEBUG2: eh.resume: -// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG203]] -// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG203]] -// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG203]] -// DEBUG2-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG203]] -// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG203]] +// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG204]] +// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG204]] +// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG204]] +// DEBUG2-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG204]] +// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG204]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..5 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG234:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG235:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG235:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG236:![0-9]+]] // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META236:![0-9]+]], !DIExpression(), [[META237:![0-9]+]]) -// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG238:![0-9]+]] -// DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG235]] -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG239:![0-9]+]] -// DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG239]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG240:![0-9]+]] -// DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG238]] -// DEBUG2-NEXT: ret ptr [[TMP5]], !dbg [[DBG238]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META237:![0-9]+]], !DIExpression(), [[META238:![0-9]+]]) +// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG239:![0-9]+]] +// DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG236]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG240:![0-9]+]] +// DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG240]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG241:![0-9]+]] +// DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG239]] +// DEBUG2-NEXT: ret ptr [[TMP5]], !dbg [[DBG239]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG241:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG242:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META242:![0-9]+]], !DIExpression(), [[META244:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META243:![0-9]+]], !DIExpression(), [[META245:![0-9]+]]) // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META245:![0-9]+]], !DIExpression(), [[META246:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META246:![0-9]+]], !DIExpression(), [[META247:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG247:![0-9]+]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG247]] -// DEBUG2-NEXT: ret void, !dbg [[DBG248:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG248:![0-9]+]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG248]] +// DEBUG2-NEXT: ret void, !dbg [[DBG249:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..6 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG249:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG250:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META250:![0-9]+]], !DIExpression(), [[META251:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META251]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]], !dbg [[META251]] -// DEBUG2-NEXT: ret void, !dbg [[DBG252:![0-9]+]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META251:![0-9]+]], !DIExpression(), [[META252:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META252]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[TMP1]]) #[[ATTR3]], !dbg [[META252]] +// DEBUG2-NEXT: ret void, !dbg [[DBG253:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG253:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG254:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META254:![0-9]+]], !DIExpression(), [[META255:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META255:![0-9]+]], !DIExpression(), [[META256:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG256:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG257:![0-9]+]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG257:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG258:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_Z6foobarv -// DEBUG2-SAME: () #[[ATTR2]] !dbg [[DBG258:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR2]] !dbg [[DBG259:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[RES:%.*]] = alloca i32, align 4 -// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]), !dbg [[DBG259:![0-9]+]] -// DEBUG2-NEXT: #dbg_declare(ptr [[RES]], [[META260:![0-9]+]], !DIExpression(), [[META261:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG259]] -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG262]] -// DEBUG2-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG263:![0-9]+]] -// DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG264:![0-9]+]] -// DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG265:![0-9]+]] -// DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG265]] -// DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG266:![0-9]+]] -// DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG266]] -// DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG266]] -// DEBUG2-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG267:![0-9]+]] -// DEBUG2-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG268:![0-9]+]] -// DEBUG2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG268]] -// DEBUG2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG268]] -// DEBUG2-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG269:![0-9]+]] -// DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG270:![0-9]+]] -// DEBUG2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG270]] -// DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG271:![0-9]+]] -// DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG271]] -// DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG271]] -// DEBUG2-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG272:![0-9]+]] -// DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG272]] -// DEBUG2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG272]] -// DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG273:![0-9]+]] -// DEBUG2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG273]] -// DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG274:![0-9]+]] -// DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG274]] -// DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG274]] -// DEBUG2-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG275:![0-9]+]] -// DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG275]] -// DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG276:![0-9]+]] -// DEBUG2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG276]] -// DEBUG2-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG276]] -// DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG277:![0-9]+]] -// DEBUG2-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG277]] -// DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG277]] -// DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG278:![0-9]+]] -// DEBUG2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG278]] -// DEBUG2-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG278]] -// DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG279:![0-9]+]] -// DEBUG2-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]] -// DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG280]] -// DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG281:![0-9]+]] -// DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG281]] -// DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG281]] -// DEBUG2-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]] -// DEBUG2-NEXT: ret i32 [[TMP23]], !dbg [[DBG283:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]), !dbg [[DBG260:![0-9]+]] +// DEBUG2-NEXT: #dbg_declare(ptr [[RES]], [[META261:![0-9]+]], !DIExpression(), [[META262:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG260]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG263]] +// DEBUG2-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG264:![0-9]+]] +// DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG265:![0-9]+]] +// DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG266:![0-9]+]] +// DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG266]] +// DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG267:![0-9]+]] +// DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG267]] +// DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG267]] +// DEBUG2-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG268:![0-9]+]] +// DEBUG2-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG269:![0-9]+]] +// DEBUG2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG269]] +// DEBUG2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG269]] +// DEBUG2-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG270:![0-9]+]] +// DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds nuw [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] +// DEBUG2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG271]] +// DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG272:![0-9]+]] +// DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG272]] +// DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG272]] +// DEBUG2-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG273:![0-9]+]] +// DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x [[STRUCT_S1]]]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG273]] +// DEBUG2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x [[STRUCT_S1]]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG273]] +// DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds nuw [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG274:![0-9]+]] +// DEBUG2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG274]] +// DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG275:![0-9]+]] +// DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG275]] +// DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG275]] +// DEBUG2-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG276:![0-9]+]] +// DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG276]] +// DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG277:![0-9]+]] +// DEBUG2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG277]] +// DEBUG2-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG277]] +// DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG278:![0-9]+]] +// DEBUG2-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG278]] +// DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG278]] +// DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG279:![0-9]+]] +// DEBUG2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG279]] +// DEBUG2-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG279]] +// DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG280:![0-9]+]] +// DEBUG2-NEXT: [[A10:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG281:![0-9]+]] +// DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG281]] +// DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]] +// DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG282]] +// DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG282]] +// DEBUG2-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG283:![0-9]+]] +// DEBUG2-NEXT: ret i32 [[TMP23]], !dbg [[DBG284:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.7 -// DEBUG2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG284:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG285:![0-9]+]] { // DEBUG2-NEXT: entry: -// DEBUG2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG285:![0-9]+]] -// DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG285]] -// DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG285]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG286:![0-9]+]] +// DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG286]] +// DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG286]] // DEBUG2: init.check: -// DEBUG2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG285]] -// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG285]] -// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..8, ptr null, ptr @.__kmpc_global_dtor_..9), !dbg [[DBG285]] -// DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG286:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG285]] -// DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG285]] +// DEBUG2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG286]] +// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG286]] +// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..8, ptr null, ptr @.__kmpc_global_dtor_..9), !dbg [[DBG286]] +// DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG287:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG286]] +// DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG286]] // DEBUG2: init.end: -// DEBUG2-NEXT: ret void, !dbg [[DBG288:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG289:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..8 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG289:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG290:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META290:![0-9]+]], !DIExpression(), [[META291:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG292:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG293:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG292]] -// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG292]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META291:![0-9]+]], !DIExpression(), [[META292:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG293:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG294:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG293]] +// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG293]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG294:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG295:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META295:![0-9]+]], !DIExpression(), [[META297:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META296:![0-9]+]], !DIExpression(), [[META298:![0-9]+]]) // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META298:![0-9]+]], !DIExpression(), [[META299:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META299:![0-9]+]], !DIExpression(), [[META300:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG300:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG300]] -// DEBUG2-NEXT: ret void, !dbg [[DBG301:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]] +// DEBUG2-NEXT: ret void, !dbg [[DBG302:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..9 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG302:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG303:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META303:![0-9]+]], !DIExpression(), [[META304:![0-9]+]]) -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META304]] -// DEBUG2-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]], !dbg [[META304]] -// DEBUG2-NEXT: ret void, !dbg [[DBG305:![0-9]+]] +// DEBUG2-NEXT: #dbg_declare(ptr [[DOTADDR]], [[META304:![0-9]+]], !DIExpression(), [[META305:![0-9]+]]) +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[META305]] +// DEBUG2-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[TMP1]]) #[[ATTR3]], !dbg [[META305]] +// DEBUG2-NEXT: ret void, !dbg [[DBG306:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG306:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG307:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META307:![0-9]+]], !DIExpression(), [[META308:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META308:![0-9]+]], !DIExpression(), [[META309:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG309:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG310:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG311:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG311:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG312:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META312:![0-9]+]], !DIExpression(), [[META313:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META313:![0-9]+]], !DIExpression(), [[META314:![0-9]+]]) // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META314:![0-9]+]], !DIExpression(), [[META315:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META315:![0-9]+]], !DIExpression(), [[META316:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG316:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG317:![0-9]+]] -// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG316]] -// DEBUG2-NEXT: ret void, !dbg [[DBG318:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG317:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG318:![0-9]+]] +// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG317]] +// DEBUG2-NEXT: ret void, !dbg [[DBG319:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG319:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG320:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META320:![0-9]+]], !DIExpression(), [[META321:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META321:![0-9]+]], !DIExpression(), [[META322:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG322:![0-9]+]] -// DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG324:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG325:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG323:![0-9]+]] +// DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG325:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG326:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG326:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG327:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META327:![0-9]+]], !DIExpression(), [[META328:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META328:![0-9]+]], !DIExpression(), [[META329:![0-9]+]]) // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META329:![0-9]+]], !DIExpression(), [[META330:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META330:![0-9]+]], !DIExpression(), [[META331:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG331:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG332:![0-9]+]] -// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG331]] -// DEBUG2-NEXT: ret void, !dbg [[DBG333:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG332:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG333:![0-9]+]] +// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG332]] +// DEBUG2-NEXT: ret void, !dbg [[DBG334:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG334:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dead_on_return(16) dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG335:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META335:![0-9]+]], !DIExpression(), [[META336:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META336:![0-9]+]], !DIExpression(), [[META337:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG337:![0-9]+]] -// DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG339:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG340:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG338:![0-9]+]] +// DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG340:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG341:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG341:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG342:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META342:![0-9]+]], !DIExpression(), [[META343:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META343:![0-9]+]], !DIExpression(), [[META344:![0-9]+]]) // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META344:![0-9]+]], !DIExpression(), [[META345:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META345:![0-9]+]], !DIExpression(), [[META346:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG346:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG347:![0-9]+]] -// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG346]] -// DEBUG2-NEXT: ret void, !dbg [[DBG348:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG347:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG348:![0-9]+]] +// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG347]] +// DEBUG2-NEXT: ret void, !dbg [[DBG349:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG349:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dead_on_return(24) dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG350:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META350:![0-9]+]], !DIExpression(), [[META351:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META351:![0-9]+]], !DIExpression(), [[META352:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG352:![0-9]+]] -// DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG354:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG355:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG353:![0-9]+]] +// DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG355:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG356:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG356:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG357:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META357:![0-9]+]], !DIExpression(), [[META358:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META358:![0-9]+]], !DIExpression(), [[META359:![0-9]+]]) // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META359:![0-9]+]], !DIExpression(), [[META360:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[A_ADDR]], [[META360:![0-9]+]], !DIExpression(), [[META361:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG361:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG362:![0-9]+]] -// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG361]] -// DEBUG2-NEXT: ret void, !dbg [[DBG363:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG362:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG363:![0-9]+]] +// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG362]] +// DEBUG2-NEXT: ret void, !dbg [[DBG364:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG364:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dead_on_return(8) dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG365:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META365:![0-9]+]], !DIExpression(), [[META366:![0-9]+]]) +// DEBUG2-NEXT: #dbg_declare(ptr [[THIS_ADDR]], [[META366:![0-9]+]], !DIExpression(), [[META367:![0-9]+]]) // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG367:![0-9]+]] -// DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG369:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG370:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds nuw [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG368:![0-9]+]] +// DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG370:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG371:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG371:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG372:![0-9]+]] { // DEBUG2-NEXT: entry: -// DEBUG2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG372:![0-9]+]] -// DEBUG2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG372]] -// DEBUG2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG372]] +// DEBUG2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG373:![0-9]+]] +// DEBUG2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG373]] +// DEBUG2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG373]] // DEBUG2-NEXT: ret void // diff --git a/clang/test/PCH/debug-info-pch-path.c b/clang/test/PCH/debug-info-pch-path.c index 22b367f344204..0a4e9d8146f00 100644 --- a/clang/test/PCH/debug-info-pch-path.c +++ b/clang/test/PCH/debug-info-pch-path.c @@ -17,6 +17,7 @@ // RUN: %clang_cc1 -debug-info-kind=standalone \ // RUN: -dwarf-ext-refs -fmodule-format=obj \ // RUN: -triple %itanium_abi_triple \ +// RUN: -fdebug-compilation-dir=%t \ // RUN: -include-pch prefix.pch %s -emit-llvm -o %t.nodir.ll %s // RUN: cat %t.nodir.ll | FileCheck %s --check-prefix=CHECK-REL-NODIR // @@ -42,6 +43,7 @@ // RUN: %clang_cc1 -debug-info-kind=standalone \ // RUN: -dwarf-ext-refs -fmodule-format=obj \ // RUN: -triple %itanium_abi_triple \ +// RUN: -fdebug-compilation-dir=%t \ // RUN: -include-pch pchdir/prefix.pch %s -emit-llvm -o %t.rel.ll %s // RUN: cat %t.rel.ll | FileCheck %s --check-prefix=CHECK-REL diff --git a/clang/test/PCH/modified-module-dependency.m b/clang/test/PCH/modified-module-dependency.m index a4710dea51169..bf93b53e2c152 100644 --- a/clang/test/PCH/modified-module-dependency.m +++ b/clang/test/PCH/modified-module-dependency.m @@ -14,7 +14,7 @@ // RUN: not %clang_cc1 -x objective-c -I %t-dir -include-pch %t-dir/prefix.pch -fmodules -fimplicit-module-maps -fmodules-cache-path=%t-dir/cache -fdisable-module-hash -fsyntax-only %s 2> %t-dir/log // RUN: FileCheck %s < %t-dir/log -// CHECK: file '[[TEST_H:.*[/\\]test\.h]]' has been modified since the precompiled header '[[PREFIX_PCH:.*/prefix\.pch]]' was built +// CHECK: file '[[TEST_H:.*[/\\]test\.h]]' has been modified since the precompiled header '[[PREFIX_PCH:.*[/\\]prefix\.pch]]' was built // CHECK: '[[TEST_H]]' required by '[[TEST_PCM:.*[/\\]test\.pcm]]' // CHECK: '[[TEST_PCM]]' required by '[[PREFIX_PCH]]' // CHECK: please rebuild precompiled file '[[PREFIX_PCH]]' diff --git a/clang/test/PCH/pch-input-path-independent.c b/clang/test/PCH/pch-input-path-independent.c new file mode 100644 index 0000000000000..44d01e4c4040c --- /dev/null +++ b/clang/test/PCH/pch-input-path-independent.c @@ -0,0 +1,29 @@ +// Testing `-include-pch` canonicalization. +// When PCHs are chained, the dependent PCHs produced are identical +// whether the included PCH is specified through a relative path or an absolute +// path (bridging1.h.pch vs bridging2.h.pch). +// The dependent PCHs are also identical regardless of the working +// directory where clang is invoked (bridging1.h.pch vs bridging3.h.pch). + +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: cd %t +// RUN: %clang_cc1 -triple x86_64-apple-macos11 -emit-pch h1.h -o %t/h1.h.pch +// RUN: %clang_cc1 -triple x86_64-apple-macos11 -emit-pch %t/bridging.h \ +// RUN: -o %t/bridging1.h.pch -include-pch %t/h1.h.pch +// RUN: %clang_cc1 -triple x86_64-apple-macos11 -emit-pch %t/bridging.h \ +// RUN: -o %t/bridging2.h.pch -include-pch ./h1.h.pch +// RUN: mkdir %t/wd/ +// RUN: cd %t/wd/ +// RUN: %clang_cc1 -triple x86_64-apple-macos11 -emit-pch %t/bridging.h \ +// RUN: -o %t/bridging3.h.pch -include-pch ../h1.h.pch + +// RUN: diff %t/bridging1.h.pch %t/bridging2.h.pch +// RUN: diff %t/bridging1.h.pch %t/bridging3.h.pch + +//--- h1.h +int bar1() { return 42; } + +//--- bridging.h +int bar() { return bar1(); } + diff --git a/clang/test/PCH/reloc.c b/clang/test/PCH/reloc.c index 435fde2e19234..019e3c495218b 100644 --- a/clang/test/PCH/reloc.c +++ b/clang/test/PCH/reloc.c @@ -3,6 +3,11 @@ // RUN: %clang -target x86_64-apple-darwin11 -fsyntax-only \ // RUN: -include-pch %t -isysroot %S/Inputs/libroot %s -Xclang -verify // RUN: not %clang -target x86_64-apple-darwin11 -include-pch %t %s +// RUN: llvm-bcanalyzer --dump --disable-histogram %t \ +// RUN: | FileCheck %s +// CHECK: blob data = 'usr{{[/\\]}}include{{[/\\]}}reloc.h' +// CHECK: blob data = 'usr{{[/\\]}}include{{[/\\]}}reloc.h' +// CHECK: blob data = 'usr{{[/\\]}}include{{[/\\]}}reloc2.h' // REQUIRES: x86-registered-target #include diff --git a/clang/test/PCH/validate-file-content.m b/clang/test/PCH/validate-file-content.m index 8863b7abea3af..289dbff1a8c20 100644 --- a/clang/test/PCH/validate-file-content.m +++ b/clang/test/PCH/validate-file-content.m @@ -22,6 +22,6 @@ // RUN: not %clang_cc1 -fsyntax-only -I %t -include-pch %t/a.pch %s -fvalidate-ast-input-files-content 2> %t/stderr // RUN: FileCheck %s < %t/stderr // -// CHECK: file '[[M_H:.*[/\\]m\.h]]' has been modified since the precompiled header '[[A_PCH:.*/a\.pch]]' was built: content changed +// CHECK: file '[[M_H:.*[/\\]m\.h]]' has been modified since the precompiled header '[[A_PCH:.*[/\\]a\.pch]]' was built: content changed // CHECK: please rebuild precompiled file '[[A_PCH]]' // expected-no-diagnostics diff --git a/clang/test/Parser/parsing-reflection-with-blocks.cpp b/clang/test/Parser/parsing-reflection-with-blocks.cpp new file mode 100644 index 0000000000000..6db7fff1dc030 --- /dev/null +++ b/clang/test/Parser/parsing-reflection-with-blocks.cpp @@ -0,0 +1,20 @@ +// RUN: %clang_cc1 %s -std=c++26 -freflection -fblocks -fsyntax-only + +struct A { + int operator^(int (^block)(int x)) const { + return block(0); + } +}; + + +consteval void test() +{ + (void)(A{}^^(int y){ return y + 1; }); + (void)(1^^(){ return 1; }()); + (void)(1^^{ return 1; }()); + + { + (void)(^^int); + (void)(A{}^^(int y){ return y + 1; }); + } +} diff --git a/clang/test/Parser/parsing-reflection.cpp b/clang/test/Parser/parsing-reflection.cpp new file mode 100644 index 0000000000000..4eabe7d8683fe --- /dev/null +++ b/clang/test/Parser/parsing-reflection.cpp @@ -0,0 +1,32 @@ +// RUN: %clang_cc1 %s -std=c++26 -freflection -fsyntax-only -verify + +struct A{}; +namespace B{}; +void f(){}; + +consteval void test() +{ + (void)(^^void); + (void)(^^bool); + (void)(^^char); + (void)(^^signed char); + (void)(^^unsigned char); + (void)(^^short); + (void)(^^unsigned short); + (void)(^^int); + (void)(^^unsigned int); + (void)(^^long); + (void)(^^unsigned long); + (void)(^^long long); + (void)(^^float); + (void)(^^double); + (void)(^^const void); + (void)(^^decltype(nullptr)); + + (void)(^^::); // expected-error {{unknown or unimplemented reflectable entity}} + constexpr auto x = 1; + (void)(^^x); // expected-error {{unknown or unimplemented reflectable entity}} + (void)(^^A); // expected-error {{unknown or unimplemented reflectable entity}} + (void)(^^B); // expected-error {{unknown or unimplemented reflectable entity}} + (void)(^^f); // expected-error {{unknown or unimplemented reflectable entity}} +} diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c index 1e38b4d3ba350..be94eb064cf91 100644 --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -4133,6 +4133,157 @@ // CHECK_ZNVER5_M64: #define __znver5 1 // CHECK_ZNVER5_M64: #define __znver5__ 1 +// RUN: %clang -march=znver6 -m32 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER6_M32 +// CHECK_ZNVER6_M32-NOT: #define __3dNOW_A__ 1 +// CHECK_ZNVER6_M32-NOT: #define __3dNOW__ 1 +// CHECK_ZNVER6_M32: #define __ADX__ 1 +// CHECK_ZNVER6_M32: #define __AES__ 1 +// CHECK_ZNVER6_M32: #define __AVX2__ 1 +// CHECK_ZNVER6_M32: #define __AVX512BF16__ 1 +// CHECK_ZNVER6_M32: #define __AVX512BITALG__ 1 +// CHECK_ZNVER6_M32: #define __AVX512BW__ 1 +// CHECK_ZNVER6_M32: #define __AVX512CD__ 1 +// CHECK_ZNVER6_M32: #define __AVX512DQ__ 1 +// CHECK_ZNVER6_M32: #define __AVX512FP16__ 1 +// CHECK_ZNVER6_M32: #define __AVX512F__ 1 +// CHECK_ZNVER6_M32: #define __AVX512IFMA__ 1 +// CHECK_ZNVER6_M32: #define __AVX512VBMI2__ 1 +// CHECK_ZNVER6_M32: #define __AVX512VBMI__ 1 +// CHECK_ZNVER6_M32: #define __AVX512VL__ 1 +// CHECK_ZNVER6_M32: #define __AVX512VNNI__ 1 +// CHECK_ZNVER6_M32: #define __AVX512VP2INTERSECT__ 1 +// CHECK_ZNVER6_M32: #define __AVX512VPOPCNTDQ__ 1 +// CHECK_ZNVER6_M32: #define __AVXIFMA__ 1 +// CHECK_ZNVER6_M32: #define __AVXNECONVERT__ 1 +// CHECK_ZNVER6_M32: #define __AVXVNNIINT8__ 1 +// CHECK_ZNVER6_M32: #define __AVXVNNI__ 1 +// CHECK_ZNVER6_M32: #define __AVX__ 1 +// CHECK_ZNVER6_M32: #define __BMI2__ 1 +// CHECK_ZNVER6_M32: #define __BMI__ 1 +// CHECK_ZNVER6_M32: #define __CLFLUSHOPT__ 1 +// CHECK_ZNVER6_M32: #define __CLWB__ 1 +// CHECK_ZNVER6_M32: #define __CLZERO__ 1 +// CHECK_ZNVER6_M32: #define __F16C__ 1 +// CHECK_ZNVER6_M32-NOT: #define __FMA4__ 1 +// CHECK_ZNVER6_M32: #define __FMA__ 1 +// CHECK_ZNVER6_M32: #define __FSGSBASE__ 1 +// CHECK_ZNVER6_M32: #define __GFNI__ 1 +// CHECK_ZNVER6_M32: #define __LZCNT__ 1 +// CHECK_ZNVER6_M32: #define __MMX__ 1 +// CHECK_ZNVER6_M32: #define __MOVDIR64B__ 1 +// CHECK_ZNVER6_M32: #define __MOVDIRI__ 1 +// CHECK_ZNVER6_M32: #define __PCLMUL__ 1 +// CHECK_ZNVER6_M32: #define __PKU__ 1 +// CHECK_ZNVER6_M32: #define __POPCNT__ 1 +// CHECK_ZNVER6_M32: #define __PREFETCHI__ 1 +// CHECK_ZNVER6_M32: #define __PRFCHW__ 1 +// CHECK_ZNVER6_M32: #define __RDPID__ 1 +// CHECK_ZNVER6_M32: #define __RDPRU__ 1 +// CHECK_ZNVER6_M32: #define __RDRND__ 1 +// CHECK_ZNVER6_M32: #define __RDSEED__ 1 +// CHECK_ZNVER6_M32: #define __SHA__ 1 +// CHECK_ZNVER6_M32: #define __SSE2_MATH__ 1 +// CHECK_ZNVER6_M32: #define __SSE2__ 1 +// CHECK_ZNVER6_M32: #define __SSE3__ 1 +// CHECK_ZNVER6_M32: #define __SSE4A__ 1 +// CHECK_ZNVER6_M32: #define __SSE4_1__ 1 +// CHECK_ZNVER6_M32: #define __SSE4_2__ 1 +// CHECK_ZNVER6_M32: #define __SSE_MATH__ 1 +// CHECK_ZNVER6_M32: #define __SSE__ 1 +// CHECK_ZNVER6_M32: #define __SSSE3__ 1 +// CHECK_ZNVER6_M32-NOT: #define __TBM__ 1 +// CHECK_ZNVER6_M32: #define __WBNOINVD__ 1 +// CHECK_ZNVER6_M32-NOT: #define __XOP__ 1 +// CHECK_ZNVER6_M32: #define __XSAVEC__ 1 +// CHECK_ZNVER6_M32: #define __XSAVEOPT__ 1 +// CHECK_ZNVER6_M32: #define __XSAVES__ 1 +// CHECK_ZNVER6_M32: #define __XSAVE__ 1 +// CHECK_ZNVER6_M32: #define __i386 1 +// CHECK_ZNVER6_M32: #define __i386__ 1 +// CHECK_ZNVER6_M32: #define __tune_znver6__ 1 +// CHECK_ZNVER6_M32: #define __znver6 1 +// CHECK_ZNVER6_M32: #define __znver6__ 1 + +// RUN: %clang -march=znver6 -m64 -E -dM %s -o - 2>&1 \ +// RUN: -target i386-unknown-linux \ +// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER6_M64 +// CHECK_ZNVER6_M64-NOT: #define __3dNOW_A__ 1 +// CHECK_ZNVER6_M64-NOT: #define __3dNOW__ 1 +// CHECK_ZNVER6_M64: #define __ADX__ 1 +// CHECK_ZNVER6_M64: #define __AES__ 1 +// CHECK_ZNVER6_M64: #define __AVX2__ 1 +// CHECK_ZNVER6_M64: #define __AVX512BF16__ 1 +// CHECK_ZNVER6_M64: #define __AVX512BITALG__ 1 +// CHECK_ZNVER6_M64: #define __AVX512BW__ 1 +// CHECK_ZNVER6_M64: #define __AVX512CD__ 1 +// CHECK_ZNVER6_M64: #define __AVX512DQ__ 1 +// CHECK_ZNVER6_M64: #define __AVX512FP16__ 1 +// CHECK_ZNVER6_M64: #define __AVX512F__ 1 +// CHECK_ZNVER6_M64: #define __AVX512IFMA__ 1 +// CHECK_ZNVER6_M64: #define __AVX512VBMI2__ 1 +// CHECK_ZNVER6_M64: #define __AVX512VBMI__ 1 +// CHECK_ZNVER6_M64: #define __AVX512VL__ 1 +// CHECK_ZNVER6_M64: #define __AVX512VNNI__ 1 +// CHECK_ZNVER6_M64: #define __AVX512VP2INTERSECT__ 1 +// CHECK_ZNVER6_M64: #define __AVX512VPOPCNTDQ__ 1 +// CHECK_ZNVER6_M64: #define __AVXIFMA__ 1 +// CHECK_ZNVER6_M64: #define __AVXNECONVERT__ 1 +// CHECK_ZNVER6_M64: #define __AVXVNNIINT8__ 1 +// CHECK_ZNVER6_M64: #define __AVXVNNI__ 1 +// CHECK_ZNVER6_M64: #define __AVX__ 1 +// CHECK_ZNVER6_M64: #define __BMI2__ 1 +// CHECK_ZNVER6_M64: #define __BMI__ 1 +// CHECK_ZNVER6_M64: #define __CLFLUSHOPT__ 1 +// CHECK_ZNVER6_M64: #define __CLWB__ 1 +// CHECK_ZNVER6_M64: #define __CLZERO__ 1 +// CHECK_ZNVER6_M64: #define __F16C__ 1 +// CHECK_ZNVER6_M64-NOT: #define __FMA4__ 1 +// CHECK_ZNVER6_M64: #define __FMA__ 1 +// CHECK_ZNVER6_M64: #define __FSGSBASE__ 1 +// CHECK_ZNVER6_M64: #define __GFNI__ 1 +// CHECK_ZNVER6_M64: #define __LZCNT__ 1 +// CHECK_ZNVER6_M64: #define __MMX__ 1 +// CHECK_ZNVER6_M64: #define __MOVDIR64B__ 1 +// CHECK_ZNVER6_M64: #define __MOVDIRI__ 1 +// CHECK_ZNVER6_M64: #define __PCLMUL__ 1 +// CHECK_ZNVER6_M64: #define __PKU__ 1 +// CHECK_ZNVER6_M64: #define __POPCNT__ 1 +// CHECK_ZNVER6_M64: #define __PREFETCHI__ 1 +// CHECK_ZNVER6_M64: #define __PRFCHW__ 1 +// CHECK_ZNVER6_M64: #define __RDPID__ 1 +// CHECK_ZNVER6_M64: #define __RDPRU__ 1 +// CHECK_ZNVER6_M64: #define __RDRND__ 1 +// CHECK_ZNVER6_M64: #define __RDSEED__ 1 +// CHECK_ZNVER6_M64: #define __SHA__ 1 +// CHECK_ZNVER6_M64: #define __SSE2_MATH__ 1 +// CHECK_ZNVER6_M64: #define __SSE2__ 1 +// CHECK_ZNVER6_M64: #define __SSE3__ 1 +// CHECK_ZNVER6_M64: #define __SSE4A__ 1 +// CHECK_ZNVER6_M64: #define __SSE4_1__ 1 +// CHECK_ZNVER6_M64: #define __SSE4_2__ 1 +// CHECK_ZNVER6_M64: #define __SSE_MATH__ 1 +// CHECK_ZNVER6_M64: #define __SSE__ 1 +// CHECK_ZNVER6_M64: #define __SSSE3__ 1 +// CHECK_ZNVER6_M64-NOT: #define __TBM__ 1 +// CHECK_ZNVER6_M64: #define __VAES__ 1 +// CHECK_ZNVER6_M64: #define __VPCLMULQDQ__ 1 +// CHECK_ZNVER6_M64: #define __WBNOINVD__ 1 +// CHECK_ZNVER6_M64-NOT: #define __XOP__ 1 +// CHECK_ZNVER6_M64: #define __XSAVEC__ 1 +// CHECK_ZNVER6_M64: #define __XSAVEOPT__ 1 +// CHECK_ZNVER6_M64: #define __XSAVES__ 1 +// CHECK_ZNVER6_M64: #define __XSAVE__ 1 +// CHECK_ZNVER6_M64: #define __amd64 1 +// CHECK_ZNVER6_M64: #define __amd64__ 1 +// CHECK_ZNVER6_M64: #define __tune_znver6__ 1 +// CHECK_ZNVER6_M64: #define __x86_64 1 +// CHECK_ZNVER6_M64: #define __x86_64__ 1 +// CHECK_ZNVER6_M64: #define __znver6 1 +// CHECK_ZNVER6_M64: #define __znver6__ 1 + + // End X86/GCC/Linux tests ------------------ // Begin PPC/GCC/Linux tests ---------------- diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index e315f75b15614..833a64d23c4e0 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -140,6 +140,7 @@ // CHECK-NOT: __riscv_zkt {{.*$}} // CHECK-NOT: __riscv_zmmul {{.*$}} // CHECK-NOT: __riscv_ztso {{.*$}} +// CHECK-NOT: __riscv_zvabd {{.*$}} // CHECK-NOT: __riscv_zvbb {{.*$}} // CHECK-NOT: __riscv_zvbc {{.*$}} // CHECK-NOT: __riscv_zve32f {{.*$}} @@ -1382,6 +1383,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s // CHECK-ZFA-EXT: __riscv_zfa 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvabd0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVABD-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvabd0p7 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVABD-EXT %s +// CHECK-ZVABD-EXT: __riscv_zvabd 7000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_zve64x_zvbb1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s diff --git a/clang/test/Sema/Inputs/lifetime-analysis.h b/clang/test/Sema/Inputs/lifetime-analysis.h index 4f881d463ebcc..f30db1a29b149 100644 --- a/clang/test/Sema/Inputs/lifetime-analysis.h +++ b/clang/test/Sema/Inputs/lifetime-analysis.h @@ -7,6 +7,8 @@ struct basic_iterator { T* operator->() const; }; +template +bool operator==(basic_iterator, basic_iterator); template bool operator!=(basic_iterator, basic_iterator); } @@ -16,6 +18,13 @@ template struct remove_reference { typedef T type; }; template struct remove_reference { typedef T type; }; template struct remove_reference { typedef T type; }; +template< class InputIt, class T > +InputIt find( InputIt first, InputIt last, const T& value ); + +template< class ForwardIt1, class ForwardIt2 > +ForwardIt1 search( ForwardIt1 first, ForwardIt1 last, + ForwardIt2 s_first, ForwardIt2 s_last ); + template typename remove_reference::type &&move(T &&t) noexcept; @@ -24,6 +33,8 @@ auto data(const C &c) -> decltype(c.data()); template auto begin(C &c) -> decltype(c.begin()); +template +auto end(C &c) -> decltype(c.end()); template T *begin(T (&array)[N]); @@ -49,15 +60,29 @@ struct vector { template vector(InputIterator first, InputIterator __last); + T& operator[](unsigned); + T & at(int n) &; T && at(int n) &&; void push_back(const T&); void push_back(T&&); const T& back() const; - void insert(iterator, T&&); + void pop_back(); + iterator insert(iterator, T&&); + void resize(size_t); + void erase(iterator); + void clear(); +}; + +template +struct unordered_map { + T& operator[](const Key& key); }; +template +void swap( T& a, T& b ); + template struct pair { A first; @@ -85,8 +110,13 @@ template struct iter { template struct basic_string { basic_string(); + basic_string(const basic_string &); + basic_string(basic_string &&); basic_string(const T *); ~basic_string(); + basic_string& operator=(const basic_string&); + basic_string& operator+=(const basic_string&); + basic_string& operator+=(const T*); const T *c_str() const; operator basic_string_view () const; using const_iterator = iter; @@ -96,7 +126,10 @@ using string = basic_string; template struct unique_ptr { + unique_ptr(); + unique_ptr(unique_ptr&&); ~unique_ptr(); + T* release(); T &operator*(); T *get() const; }; diff --git a/clang/test/Sema/constant-builtins-2.c b/clang/test/Sema/constant-builtins-2.c index 9579052b1f76b..e875863e7fa91 100644 --- a/clang/test/Sema/constant-builtins-2.c +++ b/clang/test/Sema/constant-builtins-2.c @@ -479,6 +479,7 @@ int h0 = __builtin_types_compatible_p(int, float); int h3 = __builtin_bswap16(0x1234) == 0x3412 ? 1 : f(); int h4 = __builtin_bswap32(0x1234) == 0x34120000 ? 1 : f(); int h5 = __builtin_bswap64(0x1234) == 0x3412000000000000 ? 1 : f(); +int h5a = __builtin_bswapg((_Bool)(0x0)) == (_Bool)(0x0) ? 1 : f(); int h6 = __builtin_bswapg((char)(0x12)) == (char)(0x12) ? 1 : f(); int h7 = __builtin_bswapg((short)(0x1234)) == (short)(0x3412) ? 1 : f(); int h8 = __builtin_bswapg(0x00001234) == 0x34120000 ? 1 : f(); diff --git a/clang/test/Sema/constant-builtins.c b/clang/test/Sema/constant-builtins.c index 6c13fe96b6b4a..565547a16dde5 100644 --- a/clang/test/Sema/constant-builtins.c +++ b/clang/test/Sema/constant-builtins.c @@ -25,6 +25,7 @@ int h0 = __builtin_types_compatible_p(int,float); int h3 = __builtin_bswap16(0x1234) == 0x3412 ? 1 : f(); int h4 = __builtin_bswap32(0x1234) == 0x34120000 ? 1 : f(); int h5 = __builtin_bswap64(0x1234) == 0x3412000000000000 ? 1 : f(); +int h5a = __builtin_bswapg((_Bool)1) == (_Bool)1 ? 1 : f(); int h6 = __builtin_bswapg((char)0x12) == (char)0x12 ? 1 : f(); int h7 = __builtin_bswapg((short)(0x1234)) == (short)(0x3412) ? 1 : f(); int h8 = __builtin_bswapg(0x00001234) == 0x34120000 ? 1 : f(); diff --git a/clang/test/Sema/format-strings-nonnull.c b/clang/test/Sema/format-strings-nonnull.c index b9eeb5954ffb6..1204bf1cde305 100644 --- a/clang/test/Sema/format-strings-nonnull.c +++ b/clang/test/Sema/format-strings-nonnull.c @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -fsyntax-only --std=c23 -verify -Wnonnull -Wno-format-security %s +// RUN: %clang_cc1 -fsyntax-only --std=c23 -verify -Wnonnull -Wno-format-security -fexperimental-new-constant-interpreter %s #define NULL (void*)0 diff --git a/clang/test/Sema/ptrauth.c b/clang/test/Sema/ptrauth.c index 6c4b92b0104df..59c18a3ef5e40 100644 --- a/clang/test/Sema/ptrauth.c +++ b/clang/test/Sema/ptrauth.c @@ -121,6 +121,29 @@ void test_auth_and_resign(int *dp, int (*fp)(int)) { float *mismatch = __builtin_ptrauth_auth_and_resign(dp, VALID_DATA_KEY, 0, VALID_DATA_KEY, dp); // expected-error {{incompatible pointer types initializing 'float *' with an expression of type 'int *'}} } +void test_auth_load_relative_and_sign(int *dp, int (*fp)(int)) { + __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, 0, VALID_DATA_KEY, 0); // expected-error {{too few arguments}} + __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, dp, VALID_DATA_KEY, dp, 0, 0); // expected-error {{too many arguments}} + int n = *dp; + __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, dp, VALID_DATA_KEY, dp,n); // expected-error {{last argument to '__builtin_ptrauth_auth_load_relative_and_sign' must be a constant integer}} + __builtin_ptrauth_auth_load_relative_and_sign(mismatched_type, VALID_DATA_KEY, 0, VALID_DATA_KEY, dp, 0); // expected-error {{signed value must have pointer type; type here is 'struct A'}} + __builtin_ptrauth_auth_load_relative_and_sign(dp, mismatched_type, 0, VALID_DATA_KEY, dp, 0); // expected-error {{passing 'struct A' to parameter of incompatible type 'int'}} + __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, mismatched_type, VALID_DATA_KEY, dp, 0); // expected-error {{extra discriminator must have pointer or integer type; type here is 'struct A'}} + __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, 0, mismatched_type, dp, 0); // expected-error {{passing 'struct A' to parameter of incompatible type 'int'}} + __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, 0, VALID_DATA_KEY, mismatched_type, 0); // expected-error {{extra discriminator must have pointer or integer type; type here is 'struct A'}} + + (void) __builtin_ptrauth_auth_and_resign(NULL, VALID_DATA_KEY, 0, VALID_DATA_KEY, dp); // expected-warning {{authenticating a null pointer will almost certainly trap}} + + int *dr = __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, 0, VALID_DATA_KEY, dp, 10); + dr = __builtin_ptrauth_auth_load_relative_and_sign(dp, INVALID_KEY, 0, VALID_DATA_KEY, dp, 10); // expected-error {{does not identify a valid pointer authentication key for the current target}} + dr = __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, 0, INVALID_KEY, dp, 10); // expected-error {{does not identify a valid pointer authentication key for the current target}} + + int (*fr)(int) = __builtin_ptrauth_auth_load_relative_and_sign(fp, VALID_CODE_KEY, 0, VALID_CODE_KEY, dp, 10); + fr = __builtin_ptrauth_auth_load_relative_and_sign(fp, INVALID_KEY, 0, VALID_CODE_KEY, dp, 10); // expected-error {{does not identify a valid pointer authentication key for the current target}} + fr = __builtin_ptrauth_auth_load_relative_and_sign(fp, VALID_CODE_KEY, 0, INVALID_KEY, dp, 10); // expected-error {{does not identify a valid pointer authentication key for the current target}} + + float *mismatch = __builtin_ptrauth_auth_load_relative_and_sign(dp, VALID_DATA_KEY, 0, VALID_DATA_KEY, dp,0); // expected-error {{incompatible pointer types initializing 'float *' with an expression of type 'int *'}} +} void test_sign_generic_data(int *dp) { __builtin_ptrauth_sign_generic_data(dp); // expected-error {{too few arguments}} diff --git a/clang/test/Sema/sizeless-1.c b/clang/test/Sema/sizeless-1.c index b6b92e7a68c19..7c8eed994a6a1 100644 --- a/clang/test/Sema/sizeless-1.c +++ b/clang/test/Sema/sizeless-1.c @@ -2,6 +2,10 @@ // RUN: %clang_cc1 -fsyntax-only -verify -Wall -W -Wno-strict-prototypes -triple arm64-linux-gnu -target-feature +sve -std=c11 %s // RUN: %clang_cc1 -fsyntax-only -verify -Wall -W -Wno-strict-prototypes -triple arm64-linux-gnu -target-feature +sve -std=gnu11 %s +// RUN: %clang_cc1 -fsyntax-only -verify -Wall -W -Wno-comment -Wno-strict-prototypes -triple arm64-linux-gnu -target-feature +sve -std=c90 %s -fexperimental-new-constant-interpreter +// RUN: %clang_cc1 -fsyntax-only -verify -Wall -W -Wno-strict-prototypes -triple arm64-linux-gnu -target-feature +sve -std=c11 %s -fexperimental-new-constant-interpreter +// RUN: %clang_cc1 -fsyntax-only -verify -Wall -W -Wno-strict-prototypes -triple arm64-linux-gnu -target-feature +sve -std=gnu11 %s -fexperimental-new-constant-interpreter + typedef __SVInt8_t svint8_t; typedef __SVInt16_t svint16_t; diff --git a/clang/test/Sema/warn-lifetime-analysis-nocfg.cpp b/clang/test/Sema/warn-lifetime-analysis-nocfg.cpp index c82cf41b07361..c40c6a671e3ab 100644 --- a/clang/test/Sema/warn-lifetime-analysis-nocfg.cpp +++ b/clang/test/Sema/warn-lifetime-analysis-nocfg.cpp @@ -349,9 +349,11 @@ const char *trackThroughMultiplePointer() { struct X { X(std::unique_ptr up) : - pointee(*up), pointee2(up.get()), pointer(std::move(up)) {} - int &pointee; - int *pointee2; + pointee(*up), // cfg-field-warning {{may have been moved.}} + pointee2(up.get()), // cfg-field-warning {{may have been moved.}} + pointer(std::move(up)) {} // cfg-field-note 2 {{potentially moved here}} + int &pointee; // cfg-field-note {{this field dangles}} + int *pointee2; // cfg-field-note {{this field dangles}} std::unique_ptr pointer; }; @@ -360,11 +362,11 @@ struct [[gsl::Owner]] XOwner { }; struct X2 { // A common usage that moves the passing owner to the class. - // verify no warning on this case. + // verify a strict warning on this case. X2(XOwner owner) : - pointee(owner.get()), - owner(std::move(owner)) {} - int* pointee; + pointee(owner.get()), // cfg-field-warning {{may have been moved.}} + owner(std::move(owner)) {} // cfg-field-note {{potentially moved here}} + int* pointee; // cfg-field-note {{this field dangles}} XOwner owner; }; @@ -429,6 +431,29 @@ int *returnPtrToLocalArray() { return std::begin(a); // TODO } +namespace lifetimebound_stl_algorithms { + +std::vector GetTemporaryString(); +std::vector GetTemporaryView(); + +std::string_view test_str_local() { + std::vector v; + return *std::find(v.begin(), // cfg-warning {{address of stack memory is returned later}} cfg-note {{returned here}} + v.end(), "42"); +} +std::string_view test_str_temporary() { + return *std::find(GetTemporaryString().begin(), // cfg-warning {{address of stack memory is returned later}} cfg-note {{returned here}} + GetTemporaryString().end(), "42"); +} +std::string_view test_view() { + std::vector v; + return *std::find(v.begin(), v.end(), "42"); +} +std::string_view test_view_local() { + return *std::find(GetTemporaryView().begin(), GetTemporaryView().end(), "42"); +} +} // namespace lifetimebound_stl_algorithms + struct ptr_wrapper { std::vector::iterator member; }; @@ -1108,9 +1133,8 @@ struct Foo2 { }; struct Test { - Test(Foo2 foo) : bar(foo.bar.get()), // OK \ - // FIXME: cfg-field-warning {{address of stack memory escapes to a field}} - storage(std::move(foo.bar)) {}; + Test(Foo2 foo) : bar(foo.bar.get()), // cfg-field-warning-re {{address of stack memory escapes to a field. {{.*}} may have been moved}} + storage(std::move(foo.bar)) {}; // cfg-field-note {{potentially moved here}} Bar* bar; // cfg-field-note {{this field dangles}} std::unique_ptr storage; diff --git a/clang/test/Sema/warn-lifetime-safety-dangling-field.cpp b/clang/test/Sema/warn-lifetime-safety-dangling-field.cpp index dfc43e49906f2..fa45458371012 100644 --- a/clang/test/Sema/warn-lifetime-safety-dangling-field.cpp +++ b/clang/test/Sema/warn-lifetime-safety-dangling-field.cpp @@ -24,15 +24,26 @@ struct CtorInitLifetimeBound { }; struct CtorInitButMoved { - std::string_view view; - CtorInitButMoved(std::string s) : view(s) { takeString(std::move(s)); } + std::string_view view; // expected-note {{this field dangles}} + CtorInitButMoved(std::string s) + : view(s) { // expected-warning-re {{address of stack memory escapes to a field. {{.*}} may have been moved}} + takeString(std::move(s)); // expected-note {{potentially moved here}} + } }; struct CtorInitButMovedOwned { + std::string_view view; // expected-note {{this field dangles}} + std::string owned; + CtorInitButMovedOwned(std::string s) + : view(s), // expected-warning-re {{address of stack memory escapes to a field. {{.*}} may have been moved}} + owned(std::move(s)) {} // expected-note {{potentially moved here}} +}; + +struct CtorInitButMovedOwnedOrderedCorrectly { std::string owned; std::string_view view; - CtorInitButMovedOwned(std::string s) : view(s), owned(std::move(s)) {} - CtorInitButMovedOwned(Dummy<1>, std::string s) : owned(std::move(s)), view(owned) {} + CtorInitButMovedOwnedOrderedCorrectly(std::string s) + :owned(std::move(s)), view(owned) {} }; struct CtorInitMultipleViews { @@ -65,8 +76,8 @@ struct CtorPointerField { }; struct MemberSetters { - std::string_view view; // expected-note 5 {{this field dangles}} - const char* p; // expected-note 5 {{this field dangles}} + std::string_view view; // expected-note 6 {{this field dangles}} + const char* p; // expected-note 6 {{this field dangles}} void setWithParam(std::string s) { view = s; // expected-warning {{address of stack memory escapes to a field}} @@ -98,9 +109,9 @@ struct MemberSetters { void setWithLocalButMoved() { std::string s; - view = s; - p = s.data(); - takeString(std::move(s)); + view = s; // expected-warning-re {{address of stack memory escapes to a field. {{.*}} may have been moved}} + p = s.data(); // expected-warning-re {{address of stack memory escapes to a field. {{.*}} may have been moved}} + takeString(std::move(s)); // expected-note 2 {{potentially moved here}} } void setWithGlobal() { diff --git a/clang/test/Sema/warn-lifetime-safety-fixits.cpp b/clang/test/Sema/warn-lifetime-safety-fixits.cpp new file mode 100644 index 0000000000000..82b36caf8d141 --- /dev/null +++ b/clang/test/Sema/warn-lifetime-safety-fixits.cpp @@ -0,0 +1,140 @@ +// RUN: %clang_cc1 -fsyntax-only -std=c++17 -flifetime-safety-inference \ +// RUN: -fexperimental-lifetime-safety-tu-analysis \ +// RUN: -Wlifetime-safety-suggestions -Wno-dangling \ +// RUN: -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s + +struct View; + +struct [[gsl::Owner]] MyObj { + int id; + MyObj(int i) : id(i) {} + MyObj() {} + ~MyObj() {} + MyObj operator+(MyObj); + View getView() const [[clang::lifetimebound]]; +}; + +struct [[gsl::Pointer()]] View { + View(const MyObj &); + View(); + void use() const; +}; + +View return_view(View a) { + // CHECK: :[[@LINE-1]]:18: warning: parameter in intra-TU function should be marked {{\[\[}}clang::lifetimebound]] [-Wlifetime-safety-intra-tu-suggestions] + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:24-[[@LINE-2]]:24}:" {{\[\[}}clang::lifetimebound]]" + return a; +} + +MyObj &return_multi(MyObj &a, bool c, MyObj &b) { + // CHECK-DAG: :[[@LINE-1]]:21: warning: parameter in intra-TU function should be marked + // CHECK-DAG: fix-it:"{{.*}}":{[[@LINE-2]]:29-[[@LINE-2]]:29}:" {{\[\[}}clang::lifetimebound]]" + // CHECK-DAG: :[[@LINE-3]]:39: warning: parameter in intra-TU function should be marked + // CHECK-DAG: fix-it:"{{.*}}":{[[@LINE-4]]:47-[[@LINE-4]]:47}:" {{\[\[}}clang::lifetimebound]]" + if (c) + return a; + return b; +} + +View return_partial(View a [[clang::lifetimebound]], bool c, View b) { + // CHECK: :[[@LINE-1]]:62: warning: parameter in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:68-[[@LINE-2]]:68}:" {{\[\[}}clang::lifetimebound]]" + if (c) + return a; + return b; +} + +View param_with_attr(View a [[maybe_unused]]) { + // CHECK: :[[@LINE-1]]:22: warning: parameter in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:28-[[@LINE-2]]:28}:" {{\[\[}}clang::lifetimebound]]" + return a; +} + +View param_default(View a = View()) { + // CHECK: :[[@LINE-1]]:20: warning: parameter in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:35-[[@LINE-2]]:35}:" {{\[\[}}clang::lifetimebound]]" + return a; +} + +// FIXME: Iterate over redecls and add [[clang::lifetimebound]] +View multi_decl(View a); +View multi_decl(View a); +View multi_decl(View a) { + // CHECK: :[[@LINE-1]]:17: warning: parameter in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:23-[[@LINE-2]]:23}:" {{\[\[}}clang::lifetimebound]]" + return a; +} + +template +T *template_identity(T *a) { + // CHECK: :[[@LINE-1]]:22: warning: parameter in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:26-[[@LINE-2]]:26}:" {{\[\[}}clang::lifetimebound]]" + return a; +} + +MyObj *instantiate_template() { + MyObj local; + return template_identity(&local); +} + +struct ViewMember { + ViewMember(int d) : data(d) {} + ~ViewMember() {} + MyObj data; + + View get_view() { + // CHECK: :[[@LINE-1]]:18: warning: implicit this in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:18-[[@LINE-2]]:18}:" {{\[\[}}clang::lifetimebound]]" + return data; + } + + View get_view_const() const { + // CHECK: :[[@LINE-1]]:30: warning: implicit this in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:30-[[@LINE-2]]:30}:" {{\[\[}}clang::lifetimebound]]" + return data; + } + + const View get_view_const_noexcept() const noexcept { + // CHECK: :[[@LINE-1]]:54: warning: implicit this in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:54-[[@LINE-2]]:54}:" {{\[\[}}clang::lifetimebound]]" + return data; + } +}; + +struct Base { + Base() {} + virtual ~Base() {} + MyObj data; + virtual const MyObj &get_virtual() const { + // CHECK: :[[@LINE-1]]:43: warning: implicit this in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:43-[[@LINE-2]]:43}:" {{\[\[}}clang::lifetimebound]]" + return data; + } +}; + +struct Derived : Base { + const MyObj &get_virtual() const override { + // CHECK: :[[@LINE-1]]:35: warning: implicit this in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:35-[[@LINE-2]]:35}:" {{\[\[}}clang::lifetimebound]]" + return data; + } +}; + +struct DerivedFinal : Base { + const MyObj &get_virtual() const final { + // CHECK: :[[@LINE-1]]:35: warning: implicit this in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:35-[[@LINE-2]]:35}:" {{\[\[}}clang::lifetimebound]]" + return data; + } +}; + +struct OutOfLine { + OutOfLine() {} + ~OutOfLine() {} + const OutOfLine &get() const; +}; +const OutOfLine &OutOfLine::get() const { + // CHECK: :[[@LINE-1]]:40: warning: implicit this in intra-TU function should be marked + // CHECK: fix-it:"{{.*}}":{[[@LINE-2]]:40-[[@LINE-2]]:40}:" {{\[\[}}clang::lifetimebound]]" + return *this; +} diff --git a/clang/test/Sema/warn-lifetime-safety-invalidations.cpp b/clang/test/Sema/warn-lifetime-safety-invalidations.cpp new file mode 100644 index 0000000000000..c9ce0c35c53d2 --- /dev/null +++ b/clang/test/Sema/warn-lifetime-safety-invalidations.cpp @@ -0,0 +1,344 @@ +// RUN: %clang_cc1 -fsyntax-only -Wlifetime-safety -Wno-dangling -verify %s + +#include "Inputs/lifetime-analysis.h" + +bool Bool(); + +namespace SimpleResize { +void IteratorInvalidAfterResize(int new_size) { + std::vector v; + auto it = std::begin(v); // expected-warning {{object whose reference is captured is later invalidated}} + v.resize(new_size); // expected-note {{invalidated here}} + *it; // expected-note {{later used here}} +} + +void IteratorValidAfterResize(int new_size) { + std::vector v; + auto it = std::begin(v); + v.resize(new_size); + it = std::begin(v); + if (it != std::end(v)) { + *it; // ok + } +} +} // namespace SimpleResize + +namespace CheckModel { +void IteratorValidAfterCheck() { + std::vector v; + auto it = v.begin(); + *it; // ok +} +} // namespace CheckModel + +namespace PointerToContainer { +std::vector* GetContainerPointer(); +void PointerToContainerTest() { + // FIXME: Use opaque loans. + std::vector* v = GetContainerPointer(); + auto it = v->begin(); + *it = 0; // not-ok +} +void PointerToContainerTest(std::vector* v) { + // FIXME: Handle placeholder loans. + auto it = v->begin(); + *it = 0; // not-ok +} +} // namespace PointerToContainer + +namespace InvalidateBeforeSwap { +void InvalidateBeforeSwapIterators(std::vector v1, std::vector v2) { + auto it1 = std::begin(v1); // expected-warning {{object whose reference is captured is later invalidated}} + auto it2 = std::begin(v2); + if (it1 == std::end(v1) || it2 == std::end(v2)) return; + *it1 = 0; // ok + *it2 = 0; // ok + v1.clear(); // expected-note {{invalidated here}} + *it1 = 0; // expected-note {{later used here}} + // FIXME: Handle invalidating functions like std::swap. + std::swap(it1, it2); + *it1 = 0; // ok + *it2 = 0; // not-ok +} + +void InvalidateBeforeSwapContainers(std::vector v1, std::vector v2) { + auto it1 = std::begin(v1); // expected-warning {{object whose reference is captured is later invalidated}} + auto it2 = std::begin(v2); + if (it1 == std::end(v1) || it2 == std::end(v2)) return; + *it1 = 0; // ok + *it2 = 0; // ok + v1.clear(); // expected-note {{invalidated here}} + *it1 = 0; // expected-note {{later used here}} +} +} // namespace InvalidateBeforeSwap + +namespace MergeConditionBasic { +bool A(); +bool B(); +void SameConditionInvalidatesThenValidatesIterator() { + std::vector container; + auto it = container.begin(); // expected-warning {{object whose reference is captured is later invalidated}} + if (it == container.end()) return; + const bool a = A(); + if (a) { + container.clear(); // expected-note {{invalidated here}} + } + if (a) { + it = container.begin(); + if (it == std::end(container)) return; + } + *it = 10; // expected-note {{later used here}} +} +} // namespace MergeConditionBasic + +namespace IteratorWithMultipleContainers { +void MergeWithDifferentContainerValuesIteratorNotInvalidated() { + std::vector v1, v2, v3; + auto it = std::find(v1.begin(), v1.end(), 10); + if (Bool()) { + it = std::find(v2.begin(), v2.end(), 10); + } else { + it = std::find(v3.begin(), v3.end(), 10); + } + v1.clear(); + *it = 20; +} + +void MergeWithDifferentContainerValuesInvalidated() { + std::vector v1, v2, v3; + auto it = std::find(v1.begin(), v1.end(), 10); + if (Bool()) { + it = std::find(v2.begin(), v2.end(), 10); // expected-warning {{object whose reference is captured is later invalidated}} + } else { + it = std::find(v3.begin(), v3.end(), 10); + } + v2.clear(); // expected-note {{invalidated here}} + *it = 20; // expected-note {{later used here}} +} +} // namespace IteratorWithMultipleContainers + +namespace InvalidationInLoops { +void IteratorInvalidationInAForLoop(std::vector v) { + for (auto it = std::begin(v); // expected-warning {{object whose reference is captured is later invalidated}} + it != std::end(v); + ++it) { // expected-note {{later used here}} + if (Bool()) { + v.erase(it); // expected-note {{invalidated here}} + } + } +} + +void IteratorInvalidationInAWhileLoop(std::vector v) { + auto it = std::begin(v); // expected-warning {{object whose reference is captured is later invalidated}} + while (it != std::end(v)) { + if (Bool()) { + v.erase(it); // expected-note {{invalidated here}} + } + ++it; // expected-note {{later used here}} + } +} + +void IteratorInvalidationInAForeachLoop(std::vector v) { + for (int& x : v) { // expected-warning {{object whose reference is captured is later invalidated}} \ + // expected-note {{later used here}} + if (x % 2 == 0) { + v.erase(std::find(v.begin(), v.end(), 1)); // expected-note {{invalidated here}} + } + } +} +} // namespace InvalidationInLoops + +namespace StdVectorPopBack { +void StdVectorPopBackInvalid(std::vector v) { + auto it = v.begin(); // expected-warning {{object whose reference is captured is later invalidated}} + if (it == v.end()) return; + *it; // ok + v.pop_back(); // expected-note {{invalidated here}} + *it; // expected-note {{later used here}} +} +} // namespace StdVectorPopBack + + +namespace SimpleStdFind { +void IteratorCheckedAfterFind(std::vector v) { + auto it = std::find(std::begin(v), std::end(v), 3); + if (it != std::end(v)) { + *it; // ok + } +} + +void IteratorCheckedAfterFindThenErased(std::vector v) { + auto it = std::find(std::begin(v), std::end(v), 3); // expected-warning {{object whose reference is captured is later invalidated}} + if (it != std::end(v)) { + v.erase(it); // expected-note {{invalidated here}} + } + *it; // expected-note {{later used here}} +} +} // namespace SimpleStdFind + +namespace SimpleInsert { +void UseReturnedIteratorAfterInsert(std::vector v) { + auto it = std::begin(v); + it = v.insert(it, 10); + if (it != std::end(v)) { + *it; // ok + } +} + +void UseInvalidIteratorAfterInsert(std::vector v) { + auto it = std::begin(v); // expected-warning {{object whose reference is captured is later invalidated}} + v.insert(it, 10); // expected-note {{invalidated here}} + if (it != std::end(v)) { // expected-note {{later used here}} + *it; + } +} +} // namespace SimpleInsert + +namespace SimpleStdInsert { +void IteratorValidAfterInsert(std::vector v) { + auto it = std::begin(v); + v.insert(it, 0); + it = std::begin(v); + if (it != std::end(v)) { + *it; // ok + } +} + +void IteratorInvalidAfterInsert(std::vector v, int value) { + auto it = std::begin(v); // expected-warning {{object whose reference is captured is later invalidated}} + v.insert(it, 0); // expected-note {{invalidated here}} + *it; // expected-note {{later used here}} +} +} // namespace SimpleStdInsert + +namespace SimpleInvalidIterators { +void IteratorUsedAfterErase(std::vector v) { + auto it = std::begin(v); // expected-warning {{object whose reference is captured is later invalidated}} + for (; it != std::end(v); ++it) { // expected-note {{later used here}} + if (*it > 3) { + v.erase(it); // expected-note {{invalidated here}} + } + } +} + +// FIXME: Detect this. We currently skip invalidation through ref/pointers to containers. +void IteratorUsedAfterPushBackParam(std::vector& v) { + auto it = std::begin(v); + if (it != std::end(v) && *it == 3) { + v.push_back(4); + } + ++it; +} + +void IteratorUsedAfterPushBack(std::vector v) { + auto it = std::begin(v); // expected-warning {{object whose reference is captured is later invalidated}} + if (it != std::end(v) && *it == 3) { + v.push_back(4); // expected-note {{invalidated here}} + } + ++it; // expected-note {{later used here}} +} +} // namespace SimpleInvalidIterators + +namespace ElementReferences { +// Testing raw pointers and references to elements, not just iterators. + +void ReferenceToVectorElement() { + std::vector v = {1, 2, 3}; + int& ref = v[0]; + v.push_back(4); + // FIXME: Detect this as a use of 'ref'. + // https://github.com/llvm/llvm-project/issues/180187 + ref = 10; + (void)ref; +} + +void PointerToVectorElement() { + std::vector v = {1, 2, 3}; + int* ptr = &v[0]; // expected-warning {{object whose reference is captured is later invalidated}} + v.resize(100); // expected-note {{invalidated here}} + *ptr = 10; // expected-note {{later used here}} +} + +void SelfInvalidatingMap() { + std::unordered_map mp; + mp[1] = 1; + mp[2] = mp[1]; // FIXME: Detect this. We are mising a UseFact for the assignment params. +} +} // namespace ElementReferences + +namespace Strings { + +void append(std::string str) { + std::string_view view = str; // expected-warning {{object whose reference is captured is later invalidated}} + str += "456"; // expected-note {{invalidated here}} + (void)view; // expected-note {{later used here}} +} +void reassign(std::string str, std::string str2) { + std::string_view view = str; // expected-warning {{object whose reference is captured is later invalidated}} + str = str2; // expected-note {{invalidated here}} + (void)view; // expected-note {{later used here}} +} +} // namespace Strings + +// FIXME: This should be diagnosed as use-after-invalidation but with potential move. +void ReassigningAfterMove(std::string str, std::string str2) { + std::string_view view = str; // expected-warning {{object whose reference is captured is later invalidated}} + std::vector someStorage; + someStorage.push_back(std::move(str)); + str = str2; // expected-note {{invalidated here}} + (void)view; // expected-note {{later used here}} +} + +namespace ContainersAsFields { +struct S { + std::vector strings1; + std::vector strings2; +}; +// FIXME: Make Paths more precise to reason at field granularity. +// Currently we only detect invalidations to direct declarations and not members. +void Invalidate1Use1IsInvalid() { + // FIXME: Detect this. + S s; + auto it = s.strings1.begin(); + s.strings1.push_back("1"); + *it; +} +void Invalidate1Use2IsOk() { + S s; + auto it = s.strings1.begin(); + s.strings2.push_back("1"); + *it; +}void Invalidate1Use2ViaRefIsOk() { + S s; + auto it = s.strings2.begin(); + auto& strings2 = s.strings2; + strings2.push_back("1"); + *it; +} +void Invalidate1UseSIsOk() { + S s; + S* p = &s; + s.strings2.push_back("1"); + (void)*p; +} +void PointerToContainerIsOk() { + std::vector s; + std::vector* p = &s; + p->push_back("1"); + (void)*p; +} +void IteratorFromPointerToContainerIsInvalidated() { + // FIXME: Detect this. + std::vector s; + std::vector* p = &s; + auto it = p->begin(); + p->push_back("1"); + *it; +} +void ChangingRegionOwnedByContainerIsOk() { + std::vector subdirs; + for (std::string& path : subdirs) + path = std::string(); +} + +} // namespace ContainersAsFields diff --git a/clang/test/Sema/warn-lifetime-safety.cpp b/clang/test/Sema/warn-lifetime-safety.cpp index 2976c809e389c..8f52ff27bc6fd 100644 --- a/clang/test/Sema/warn-lifetime-safety.cpp +++ b/clang/test/Sema/warn-lifetime-safety.cpp @@ -10,6 +10,8 @@ struct [[gsl::Owner]] MyObj { MyObj(); MyObj(int); MyObj(const MyObj&); + MyObj(MyObj&&); + MyObj& operator=(MyObj&&); ~MyObj() {} // Non-trivial destructor MyObj operator+(MyObj); @@ -1404,39 +1406,69 @@ void add(int c, MyObj* node) { } } // namespace CppCoverage -namespace do_not_warn_on_std_move { -void silenced() { +namespace strict_warn_on_move { +void strict_warn_on_move() { MyObj b; View v; { MyObj a; - v = a; - b = std::move(a); // No warning for 'a' being moved. - } - (void)v; + v = a; // expected-warning-re {{object whose reference {{.*}} may have been moved}} + b = std::move(a); // expected-note {{potentially moved here}} + } // expected-note {{destroyed here}} + (void)v; // expected-note {{later used here}} } -void silenced_flow_insensitive(bool c) { - MyObj a; - View v = a; - if (c) { - MyObj b = std::move(a); - } - (void)v; +void flow_sensitive(bool c) { + View v; + { + MyObj a; + if (c) { + MyObj b = std::move(a); + return; + } + v = a; // expected-warning {{object whose reference}} + } // expected-note {{destroyed here}} + (void)v; // expected-note {{later used here}} } -// FIXME: Silence when move arg is not a declref. void take(MyObj&&); -void not_silenced_via_conditional(bool cond) { +void detect_conditional(bool cond) { View v; { MyObj a, b; - v = cond ? a : b; // expected-warning 2 {{object whose reference }} - take(std::move(cond ? a : b)); + v = cond ? a : b; // expected-warning-re 2 {{object whose reference {{.*}} may have been moved}} + take(std::move(cond ? a : b)); // expected-note 2 {{potentially moved here}} } // expected-note 2 {{destroyed here}} (void)v; // expected-note 2 {{later used here}} } -} // namespace do_not_warn_on_std_move + +void wrong_use_of_move_is_permissive() { + View v; + { + MyObj a; + v = std::move(a); // expected-warning {{object whose reference is captured does not live long enough}} + } // expected-note {{destroyed here}} + (void)v; // expected-note {{later used here}} + const int* p; + { + MyObj a; + p = std::move(a).getData(); // expected-warning {{object whose reference is captured does not live long enough}} + } // expected-note {{destroyed here}} + (void)p; // expected-note {{later used here}} +} + +void take(int*); +void test_release_no_uaf() { + int* r; + // Calling release() marks p as moved from, so its destruction doesn't invalidate r. + { + std::unique_ptr p; + r = p.get(); // expected-warning-re {{object whose reference {{.*}} may have been moved}} + take(p.release()); // expected-note {{potentially moved here}} + } // expected-note {{destroyed here}} + (void)*r; // expected-note {{later used here}} +} +} // namespace strict_warn_on_move // Implicit this annotations with redecls. namespace GH172013 { diff --git a/clang/test/Sema/wasm-funcref-table.c b/clang/test/Sema/wasm-funcref-table.c new file mode 100644 index 0000000000000..9b4d53b8bbf08 --- /dev/null +++ b/clang/test/Sema/wasm-funcref-table.c @@ -0,0 +1,18 @@ +// RUN: %clang_cc1 -triple wasm32 -target-feature +reference-types -fsyntax-only -verify %s + +typedef void (*__funcref fn_funcref)(void); + +// Valid funcref table declaration (zero-length, static) +static fn_funcref valid_table[0]; // no error expected + +// Invalid: non-zero length +static fn_funcref bad_table[1]; // expected-error {{only zero-length WebAssembly tables are currently supported}} + +// Array subscript on funcref table should be rejected +void test_subscript(void) { + (void)valid_table[0]; // expected-error {{cannot subscript a WebAssembly table}} +} + +// Original reproducer from https://github.com/llvm/llvm-project/issues/140933 +// The declaration should be rejected (not static, non-zero length) +extern fn_funcref issue_table[1]; // expected-error {{WebAssembly table must be static}} diff --git a/clang/test/SemaCUDA/vararg.cu b/clang/test/SemaCUDA/vararg.cu index 62693e1d4a0af..91318fc6601c7 100644 --- a/clang/test/SemaCUDA/vararg.cu +++ b/clang/test/SemaCUDA/vararg.cu @@ -3,7 +3,7 @@ // RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-is-device -fsyntax-only \ // RUN: -verify -DEXPECT_VA_ARG_ERR %s // RUN: %clang_cc1 -triple nvptx64-nvidia-cuda -fcuda-is-device -fsyntax-only \ -// RUN: -fcuda-allow-variadic-functions -verify -DEXPECT_VA_ARG_ERR %s +// RUN: -verify -DEXPECT_VA_ARG_ERR %s #include #include "Inputs/cuda.h" diff --git a/clang/test/SemaCXX/alloc-token.cpp b/clang/test/SemaCXX/alloc-token.cpp index 2a11e3366d5fb..aae25720d4329 100644 --- a/clang/test/SemaCXX/alloc-token.cpp +++ b/clang/test/SemaCXX/alloc-token.cpp @@ -79,4 +79,9 @@ void negative_tests() { negative_template_test(); // expected-note {{in instantiation of function template specialization 'negative_template_test' requested here}} constexpr auto inference_fail = __builtin_infer_alloc_token(123); // expected-error {{must be initialized by a constant expression}} \ // expected-note {{could not infer allocation type for __builtin_infer_alloc_token}} + + // PR178892: Ensure struct arguments don't crash the bytecode interpreter. + struct S {}; + constexpr auto struct_arg = __builtin_infer_alloc_token(S()); // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{could not infer allocation type for __builtin_infer_alloc_token}} } diff --git a/clang/test/SemaCXX/builtin-bswapg.cpp b/clang/test/SemaCXX/builtin-bswapg.cpp index 539390fa9b606..815cc0085f89e 100644 --- a/clang/test/SemaCXX/builtin-bswapg.cpp +++ b/clang/test/SemaCXX/builtin-bswapg.cpp @@ -2,6 +2,7 @@ // RUN: %clang_cc1 -fsyntax-only -verify -fexperimental-new-constant-interpreter %s void test_basic_type_checks() { + static_assert(__is_same(bool, decltype(__builtin_bswapg((bool)0))), ""); static_assert(__is_same(char, decltype(__builtin_bswapg((char)0))), ""); static_assert(__is_same(unsigned char, decltype(__builtin_bswapg((unsigned char)0))), ""); static_assert(__is_same(short, decltype(__builtin_bswapg((short)0))), ""); diff --git a/clang/test/SemaCXX/constant-expression-cxx2a.cpp b/clang/test/SemaCXX/constant-expression-cxx2a.cpp index 4fcd243b4442c..fb60b5300c362 100644 --- a/clang/test/SemaCXX/constant-expression-cxx2a.cpp +++ b/clang/test/SemaCXX/constant-expression-cxx2a.cpp @@ -1241,8 +1241,9 @@ namespace dtor_call { } constexpr void destroy_past_end_array() { // expected-error {{never produces a constant expression}} - A a[2]; - a[2].~A(); // expected-note {{destruction of dereferenced one-past-the-end pointer}} + A a[2]; // expected-note {{array 'a' declared here}} + a[2].~A(); // expected-note {{destruction of dereferenced one-past-the-end pointer}} \ + // expected-warning {{array index 2 is past the end of the array}} } union As { diff --git a/clang/test/SemaCXX/ifunc-has-attribute.cpp b/clang/test/SemaCXX/ifunc-has-attribute.cpp index 242f3b621745f..913bc40ffee44 100644 --- a/clang/test/SemaCXX/ifunc-has-attribute.cpp +++ b/clang/test/SemaCXX/ifunc-has-attribute.cpp @@ -2,6 +2,7 @@ // RUN: %clang_cc1 -emit-llvm-only -triple x86_64-apple-macosx -verify %s -DSUPPORTED=1 // RUN: %clang_cc1 -emit-llvm-only -triple arm64-apple-macosx -verify %s -DSUPPORTED=1 // RUN: %clang_cc1 -emit-llvm-only -triple x86_64-pc-win32 -verify %s -DNOT_SUPPORTED=1 +// RUN: %clang_cc1 -emit-llvm-only -triple powerpc64-ibm-aix-xcoff -verify %s -DSUPPORTED=1 // expected-no-diagnostics diff --git a/clang/test/SemaCXX/warn-thread-safety-analysis.cpp b/clang/test/SemaCXX/warn-thread-safety-analysis.cpp index 466135a1d9cef..e57299e93aa48 100644 --- a/clang/test/SemaCXX/warn-thread-safety-analysis.cpp +++ b/clang/test/SemaCXX/warn-thread-safety-analysis.cpp @@ -2532,6 +2532,10 @@ class Bar { Foo& getFoo() { return *f; } Foo& getFoo2(int c) { return *f; } Foo& getFoo3(int c, int d) { return *f; } + Foo& getFoo4(bool) { return *f; } + Foo& getFoo5(char) { return *f; } + Foo& getFoo6(char16_t) { return *f; } + Foo& getFoo7(const char*) { return *f; } Foo& getFooey() { return *f; } }; @@ -2563,6 +2567,22 @@ void test() { bar.getFoo3(a, b).a = 0; bar.getFoo3(a, b).mu_.Unlock(); + bar.getFoo4(true).mu_.Lock(); + bar.getFoo4(true).a = 0; + bar.getFoo4(true).mu_.Unlock(); + + bar.getFoo5('a').mu_.Lock(); + bar.getFoo5('a').a = 0; + bar.getFoo5('a').mu_.Unlock(); + + bar.getFoo6(u'\u1234').mu_.Lock(); + bar.getFoo6(u'\u1234').a = 0; + bar.getFoo6(u'\u1234').mu_.Unlock(); + + bar.getFoo7("foo").mu_.Lock(); + bar.getFoo7("foo").a = 0; + bar.getFoo7("foo").mu_.Unlock(); + getBarFoo(bar, a).mu_.Lock(); getBarFoo(bar, a).a = 0; getBarFoo(bar, a).mu_.Unlock(); @@ -2604,12 +2624,42 @@ void test2() { // expected-note {{found near match 'bar.getFoo2(a).mu_'}} bar.getFoo2(a).mu_.Unlock(); + bar.getFoo2(0).mu_.Lock(); + bar.getFoo2(1).a = 0; // \ + // expected-warning {{writing variable 'a' requires holding mutex 'bar.getFoo2(1).mu_' exclusively}} \ + // expected-note {{found near match 'bar.getFoo2(0).mu_'}} + bar.getFoo2(0).mu_.Unlock(); + bar.getFoo3(a, b).mu_.Lock(); bar.getFoo3(a, c).a = 0; // \ // expected-warning {{writing variable 'a' requires holding mutex 'bar.getFoo3(a, c).mu_' exclusively}} \ // expected-note {{found near match 'bar.getFoo3(a, b).mu_'}} bar.getFoo3(a, b).mu_.Unlock(); + bar.getFoo4(true).mu_.Lock(); + bar.getFoo4(false).a = 0; // \ + // expected-warning {{writing variable 'a' requires holding mutex 'bar.getFoo4(false).mu_' exclusively}} \ + // expected-note {{found near match 'bar.getFoo4(true).mu_'}} + bar.getFoo4(true).mu_.Unlock(); + + bar.getFoo5('x').mu_.Lock(); + bar.getFoo5('y').a = 0; // \ + // expected-warning {{writing variable 'a' requires holding mutex 'bar.getFoo5(U'y').mu_' exclusively}} \ + // expected-note {{found near match 'bar.getFoo5(U'x').mu_'}} + bar.getFoo5('x').mu_.Unlock(); + + bar.getFoo6(u'\u1234').mu_.Lock(); + bar.getFoo6(u'\u4321').a = 0; // \ + // expected-warning {{writing variable 'a' requires holding mutex 'bar.getFoo6(U'\u4321').mu_' exclusively}} \ + // expected-note {{found near match 'bar.getFoo6(U'\u1234').mu_'}} + bar.getFoo6(u'\u1234').mu_.Unlock(); + + bar.getFoo7("foo").mu_.Lock(); + bar.getFoo7("bar").a = 0; // \ + // expected-warning {{writing variable 'a' requires holding mutex 'bar.getFoo7("bar").mu_' exclusively}} \ + // expected-note {{found near match 'bar.getFoo7("foo").mu_'}} + bar.getFoo7("foo").mu_.Unlock(); + getBarFoo(bar, a).mu_.Lock(); getBarFoo(bar, b).a = 0; // \ // expected-warning {{writing variable 'a' requires holding mutex 'getBarFoo(bar, b).mu_' exclusively}} \ @@ -7434,6 +7484,16 @@ void testPointerAliasEscapeAndReset(Foo *f) { ptr->mu.Unlock(); } +// A function that may do anything to the objects referred to by the inputs. +void escapeAliasMultiple(void *, void *, void *); +void testPointerAliasEscapeMultiple(Foo *F) { + Foo *L; + F->mu.Lock(); // expected-note{{mutex acquired here}} + Foo *Fp = F; + escapeAliasMultiple(&L, &L, &Fp); + Fp->mu.Unlock(); // expected-warning{{releasing mutex 'Fp->mu' that was not held}} +} // expected-warning{{mutex 'F->mu' is still held at the end of function}} + void testPointerAliasTryLock1() { Foo *ptr = returnsFoo(); if (ptr->mu.TryLock()) { @@ -7536,6 +7596,19 @@ void testNestedAcquire(Container *c) EXCLUSIVE_LOCK_FUNCTION(&c->foo.mu) { buf->mu.Lock(); } +void testArrayOfContainers() { + Container array[10]; + + Foo *ptr1 = &array[0].foo; + Foo *ptr2 = &array[1].foo; + ptr1->mu.Lock(); + ptr2->mu.Lock(); + array[0].foo.data = 0; + array[1].foo.data = 1; + ptr2->mu.Unlock(); + ptr1->mu.Unlock(); +} + struct ContainerOfPtr { Foo *foo_ptr; ContainerOfPtr *next; diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-format-attr-builtins.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-format-attr-builtins.cpp new file mode 100644 index 0000000000000..71426aa9ef992 --- /dev/null +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-format-attr-builtins.cpp @@ -0,0 +1,31 @@ +// RUN: %clang_cc1 -Wformat -verify=expected-format %s +// RUN: %clang_cc1 -Wunsafe-buffer-usage -Wunsafe-buffer-usage-in-format-attr-call -verify=expected,expected-format %s + +namespace std { + template + struct basic_string { + T* p; + T *c_str(); + T *data(); + unsigned size_bytes(); + unsigned size(); + }; + + typedef basic_string string; +} // namespace std + +// PR#178320 corrects the format attribute arguments for +// '__builtin_os_log_format' so that +// '-Wunsafe-buffer-usage-in-format-attr-call' behaves correctly on +// them. For '-Wformat', the check for '__builtin_os_log_format' is +// hand-craft without using the attribute. So they are still fine. + +void test_format_attr(char * Str, std::string StdStr) { + __builtin_os_log_format(nullptr, "hello", Str); // expected-format-warning{{data argument not used by format string}} + __builtin_os_log_format(nullptr, "hello %s", StdStr.c_str()); + __builtin_os_log_format(nullptr, "hello %s", Str); // expected-warning{{formatting function '__builtin_os_log_format' is unsafe}} \ + expected-note{{string argument is not guaranteed to be null-terminated}} + + __builtin_os_log_format(nullptr, "hello %"); // expected-format-warning{{incomplete format specifier}} + __builtin_os_log_format(nullptr, "hello %d", .42); // expected-format-warning{{format specifies type 'int' but the argument has type 'double'}} +} diff --git a/clang/test/SemaHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip b/clang/test/SemaHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip new file mode 100644 index 0000000000000..b57d059d7767e --- /dev/null +++ b/clang/test/SemaHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip @@ -0,0 +1,32 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1250 -fsyntax-only -fcuda-is-device -verify %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1251 -fsyntax-only -fcuda-is-device -verify %s + +#define __device__ __attribute__((device)) + +typedef int v2i __attribute__((ext_vector_type(2))); +typedef int v4i __attribute__((ext_vector_type(4))); + +template +__device__ void template_cooperative_atomic_store_32x4B(int* gaddr, int val) { + // expected-warning@+1 {{memory order argument to atomic operation is invalid}} + __builtin_amdgcn_cooperative_atomic_store_32x4B(gaddr, val, AO, "agent"); +} + +__device__ void test_amdgcn_cooperative_atomic_store_32x4B_invalid_ao(int* gaddr, int val) +{ + // expected-note@+1 {{in instantiation of function template specialization 'template_cooperative_atomic_store_32x4B<42U>' requested here}} + template_cooperative_atomic_store_32x4B<42>(gaddr, val); +} + +template +__device__ int template_cooperative_atomic_load_32x4B(int* gaddr) { + // expected-warning@+1 {{memory order argument to atomic operation is invalid}} + return __builtin_amdgcn_cooperative_atomic_load_32x4B(gaddr, AO, ""); +} + +__device__ void test_amdgcn_cooperative_atomic_load_32x4B_invalid_ao(int* addr, int *out) +{ + // expected-note@+1 {{in instantiation of function template specialization 'template_cooperative_atomic_load_32x4B<42U>' requested here}} + *out = template_cooperative_atomic_load_32x4B<42>(addr); +} diff --git a/clang/test/SemaHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip b/clang/test/SemaHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip new file mode 100644 index 0000000000000..a47e9a7ef2822 --- /dev/null +++ b/clang/test/SemaHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip @@ -0,0 +1,26 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx1250 -fsyntax-only -fcuda-is-device -verify %s + +#define __device__ __attribute__((device)) + +typedef int v4i __attribute__((ext_vector_type(4))); + +template +__device__ v4i templated_amdgcn_flat_load_monitor_b128(v4i* inptr) +{ + // expected-error@+2 {{synchronization scope argument to atomic operation is invalid}} + // expected-warning@+1 {{memory order argument to atomic operation is invalid}} + return __builtin_amdgcn_flat_load_monitor_b128(inptr, AO, Scope); +} + +__device__ void test_amdgcn_flat_load_monitor_b128_invalid_ao_from_template(v4i* inptr, v4i *out) +{ + // expected-note@+1 {{in instantiation of function template specialization 'templated_amdgcn_flat_load_monitor_b128<42U, 0U>' requested here}} + *out = templated_amdgcn_flat_load_monitor_b128<42, __MEMORY_SCOPE_SYSTEM>(inptr); +} + +__device__ void test_amdgcn_flat_load_monitor_b128_invalid_sc_from_template(v4i* inptr, v4i *out) +{ + // expected-note@+1 {{in instantiation of function template specialization 'templated_amdgcn_flat_load_monitor_b128<5U, 42U>' requested here}} + *out = templated_amdgcn_flat_load_monitor_b128<__ATOMIC_SEQ_CST, 42>(inptr); +} diff --git a/clang/test/SemaHIP/hip-builtin-lvalue-to-rvalue.hip b/clang/test/SemaHIP/hip-builtin-lvalue-to-rvalue.hip new file mode 100644 index 0000000000000..b3238d7b29d3e --- /dev/null +++ b/clang/test/SemaHIP/hip-builtin-lvalue-to-rvalue.hip @@ -0,0 +1,19 @@ +// REQUIRES: amdgpu-registered-target +// RUN: %clang_cc1 -std=c++20 -triple amdgcn -target-cpu gfx1200 -fsyntax-only -fcuda-is-device -ast-dump %s 2>&1 | FileCheck %s + +// expected-no-diagnostics + +// Test that HIP builtins correctly perform lvalue-to-rvalue conversion on pointer arg. + +#define __device__ __attribute__((device)) + +typedef __attribute__((__vector_size__(8 * sizeof(__fp16)))) __fp16 fp16x8_t; + +// CHECK: ImplicitCastExpr {{.*}} +// CHECK-NEXT: ImplicitCastExpr {{.*}} +// CHECK-NEXT: DeclRefExpr {{.*}} lvalue Var {{.*}} 'glb_ptr' +__device__ fp16x8_t test_global_load_transpose(const _Float16 *in_ptr) { + fp16x8_t *glb_ptr = reinterpret_cast( + reinterpret_cast<__UINTPTR_TYPE__>(in_ptr)); + return __builtin_amdgcn_global_load_tr_b128_v8f16(glb_ptr); +} diff --git a/clang/test/SemaHIP/shared-variable-too-large.hip b/clang/test/SemaHIP/shared-variable-too-large.hip new file mode 100644 index 0000000000000..eff5f8f6a7900 --- /dev/null +++ b/clang/test/SemaHIP/shared-variable-too-large.hip @@ -0,0 +1,23 @@ +// RUN: %clang_cc1 -fsyntax-only -triple amdgcn -target-cpu gfx90a -verify %s -fcuda-is-device + +#define __global__ __attribute__((global)) +#define __device__ __attribute__((device)) +#define __shared__ __attribute__((shared)) + +__shared__ short max_size_global_arr1[2147483647]; +[[clang::loader_uninitialized]] short [[clang::address_space(3)]] max_size_global_arr2[2147483647]; +__shared__ short too_large_global_arr1[2147483648]; // expected-error {{'short[2147483648]' is too large for the address space (maximum allowed size of 4'294'967'295 bytes)}} +[[clang::loader_uninitialized]] short [[clang::address_space(3)]] too_large_global_arr2[2147483648]; // expected-error {{'__attribute__((address_space(3))) short[2147483648]' is too large for the address space (maximum allowed size of 4'294'967'295 bytes)}} + +__device__ void func() { + __shared__ int max_size_arr[1073741823]; + __shared__ int too_large_arr[1073741824]; // expected-error {{'int[1073741824]' is too large for the address space (maximum allowed size of 4'294'967'295 bytes)}} +} + +__global__ void kernel() { + __shared__ char max_size_arr[4294967295]; + __shared__ char too_large_arr[4294967296]; // expected-error {{'char[4294967296]' is too large for the address space (maximum allowed size of 4'294'967'295 bytes)}} +} + +// TODO: The implementation of the __shared__ attribute doesn't check the +// instantiation of dependent variables. diff --git a/clang/test/SemaHLSL/BuiltIns/ByteAddressBuffers.hlsl b/clang/test/SemaHLSL/BuiltIns/ByteAddressBuffers.hlsl new file mode 100644 index 0000000000000..bd5759ddc0f04 --- /dev/null +++ b/clang/test/SemaHLSL/BuiltIns/ByteAddressBuffers.hlsl @@ -0,0 +1,44 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library -x hlsl -fsyntax-only -verify %s + +ByteAddressBuffer Buf : register(t0); +RWByteAddressBuffer RWBuf : register(u0); + +uint test_load_uint_array()[4] { + return Buf.Load(0); + // expected-error@-1 {{an array type is not allowed here}} + // expected-note@-2 {{in instantiation of function template specialization 'hlsl::ByteAddressBuffer::Load' requested here}} +} + +float test_load_float_array()[2] { + return RWBuf.Load(0); + // expected-error@-1 {{an array type is not allowed here}} + // expected-note@-2 {{in instantiation of function template specialization 'hlsl::RWByteAddressBuffer::Load' requested here}} +} + +uint test_load_uint_array_with_status()[4] { + uint s1; + return RWBuf.Load(0, s1); + // expected-error@-1 {{an array type is not allowed here}} + // expected-note@-2 {{in instantiation of function template specialization 'hlsl::RWByteAddressBuffer::Load' requested here}} +} + +float test_load_float_array_with_status()[2] { + uint s1; + return Buf.Load(0, s1); + // expected-error@-1 {{an array type is not allowed here}} + // expected-note@-2 {{in instantiation of function template specialization 'hlsl::ByteAddressBuffer::Load' requested here}} +} + +void test_store_uint_array() { + uint UIntArray[4]; + RWBuf.Store(0, UIntArray); + // expected-error@-1 {{an array type is not allowed here}} + // expected-note@-2 {{in instantiation of function template specialization 'hlsl::RWByteAddressBuffer::Store' requested here}} +} + +void test_store_float_array() { + float FloatArray[2]; + RWBuf.Store(0, FloatArray); + // expected-error@-1 {{an array type is not allowed here}} + // expected-note@-2 {{in instantiation of function template specialization 'hlsl::RWByteAddressBuffer::Store' requested here}} +} diff --git a/clang/test/SemaHLSL/BuiltIns/WavePrefixSum-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/WavePrefixSum-errors.hlsl new file mode 100644 index 0000000000000..1e575c94e67a5 --- /dev/null +++ b/clang/test/SemaHLSL/BuiltIns/WavePrefixSum-errors.hlsl @@ -0,0 +1,28 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify + +int test_too_few_arg() { + return __builtin_hlsl_wave_prefix_sum(); + // expected-error@-1 {{too few arguments to function call, expected 1, have 0}} +} + +float2 test_too_many_arg(float2 p0) { + return __builtin_hlsl_wave_prefix_sum(p0, p0); + // expected-error@-1 {{too many arguments to function call, expected 1, have 2}} +} + +bool test_expr_bool_type_check(bool p0) { + return __builtin_hlsl_wave_prefix_sum(p0); + // expected-error@-1 {{invalid operand of type 'bool'}} +} + +bool2 test_expr_bool_vec_type_check(bool2 p0) { + return __builtin_hlsl_wave_prefix_sum(p0); + // expected-error@-1 {{invalid operand of type 'bool2' (aka 'vector')}} +} + +struct S { float f; }; + +S test_expr_struct_type_check(S p0) { + return __builtin_hlsl_wave_prefix_sum(p0); + // expected-error@-1 {{invalid operand of type 'S' where a scalar or vector is required}} +} diff --git a/clang/test/SemaHLSL/matrix-member-access-errors.hlsl b/clang/test/SemaHLSL/matrix-member-access-errors.hlsl new file mode 100644 index 0000000000000..bba038651f210 --- /dev/null +++ b/clang/test/SemaHLSL/matrix-member-access-errors.hlsl @@ -0,0 +1,39 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -finclude-default-header -verify %s + +typedef vector float5; + +void foo() { + float3x3 A; + float r = A._m00; // read is ok + float good1 = A._11; + float good2 = A._33; + + float bad0 = A._m44; // expected-error {{matrix row element accessor is out of bounds of zero based indexing}} expected-error {{matrix column element accessor is out of bounds of zero based indexing}} + float bad1 = A._m33; // expected-error {{matrix row index 3 is out of bounds of rows size 3}} expected-error {{matrix column index 3 is out of bounds of columns size 3}} + float bad2 = A._mA2; // expected-error {{invalid matrix member 'A' expected row as integer}} + float bad3 = A._m2F; // expected-error {{invalid matrix member 'F' expected column as integer}} + + float bad4 = A._00; // expected-error {{matrix row element accessor is out of bounds of one based indexing}} expected-error {{matrix column element accessor is out of bounds of one based indexing}} + float bad5 = A._44; // expected-error {{matrix row index 3 is out of bounds of rows size 3}} expected-error {{matrix column index 3 is out of bounds of columns size 3}} + float bad6 = A._55; // expected-error {{matrix row element accessor is out of bounds of one based indexing}} expected-error {{matrix column element accessor is out of bounds of one based indexing}} + float bad7 = A.foo; // expected-error {{invalid matrix member 'foo' expected zero based: '_mRC' or one-based: '_RC' accessor}} + float2 bad8 = A._m00_33; // expected-error {{invalid matrix member '_m00_33' expected zero based: '_mRC' accessor}} + float2 bad9 = A._11_m33; // expected-error {{invalid matrix member '_11_m33' expected one-based: '_RC' accessor}} + float bad10 = A._m0000; // expected-error {{invalid matrix member '_m0000' expected zero based: '_mRC' accessor}} + float bad11 = A._m1; // expected-error {{invalid matrix member '_m1' expected zero based: '_mRC' accessor}} + float bad12 = A._m; // expected-error {{invalid matrix member '_m' expected zero based: '_mRC' accessor}} + float bad13 = A._1; // expected-error {{invalid matrix member '_1' expected one-based: '_RC' accessor}} + float bad14 = A.m; // expected-error {{invalid matrix member 'm' expected length 4 for zero based: '_mRC' or length 3 for one-based: '_RC' accessor}} + float bad15 = A._; // expected-error {{invalid matrix member '_' expected length 4 for zero based: '_mRC' or length 3 for one-based: '_RC' accessor}} + float bad16 = A._m00_m; // expected-error {{invalid matrix member '_m00_m' expected zero based: '_mRC' accessor}} + float bad17 = A._m11_m2; // expected-error {{invalid matrix member '_m11_m2' expected zero based: '_mRC' accessor}} + float bad18 = A._m11_mAF; // expected-error {{invalid matrix member 'A' expected row as integer}} // expected-error {{invalid matrix member 'F' expected column as integer}} + + A._m12 = 3.14; // write is OK + A._m00_m00 = 1.xx; // expected-error {{matrix is not assignable (contains duplicate components)}} + + float4x4 B; + float5 vec5; + B._m00_m01_m02_m03_m10 = vec5; // expected-error {{matrix swizzle length must be between 1 and 4 but is 5}} + float5 badVec5 = B._m00_m01_m02_m03_m10; // expected-error {{matrix swizzle length must be between 1 and 4 but is 5}} +} diff --git a/clang/test/SemaOpenCL/amdgpu-variables-too-large-for-address-space.cl b/clang/test/SemaOpenCL/amdgpu-variables-too-large-for-address-space.cl new file mode 100644 index 0000000000000..a0c2b8838761b --- /dev/null +++ b/clang/test/SemaOpenCL/amdgpu-variables-too-large-for-address-space.cl @@ -0,0 +1,13 @@ +// RUN: %clang_cc1 -triple amdgcn-- -verify -fsyntax-only %s + +void func() { + __private char max_size_private_arr[4294967295]; + __private char too_large_private_arr[4294967296]; // expected-error {{'__private char[4294967296]' is too large for the address space (maximum allowed size of 4'294'967'295 bytes)}} +} + +void kernel kernel_func() { + __private int max_size_private_arr[1073741823]; + __local long max_size_local_arr[536870911]; + __private int too_large_private_arr[1073741824]; // expected-error {{'__private int[1073741824]' is too large for the address space (maximum allowed size of 4'294'967'295 bytes)}} + __local long too_large_local_arr[536870912]; // expected-error {{'__local long[536870912]' is too large for the address space (maximum allowed size of 4'294'967'295 bytes)}} +} diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl index da6a03bc93eeb..8ab4f43d70c40 100644 --- a/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl +++ b/clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl @@ -94,15 +94,48 @@ void test_cvt_scale_pk(global half8 *outh8, global bfloat8 *outy8, uint2 src2, *outf16 = __builtin_amdgcn_cvt_scale_pk16_f32_bf6(src3, scale, 16); // expected-error {{argument value 16 is outside the valid range [0, 15]}} } -void test_amdgcn_load_monitor(global int* b32gaddr, global v2i* b64gaddr, global v4i* b128gaddr, int *b32faddr, v2i* b64faddr, v4i *b128faddr, - global int* b32out, global v2i* b64out, global v4i* b128out, int cpol) +void test_amdgcn_load_monitor_ao_constant(global int* b32gaddr, global v2i* b64gaddr, global v4i* b128gaddr, int *b32faddr, v2i* b64faddr, v4i *b128faddr, + global int* b32out, global v2i* b64out, global v4i* b128out, int ao) { - *b32out = __builtin_amdgcn_global_load_monitor_b32(b32gaddr, cpol); // expected-error {{'__builtin_amdgcn_global_load_monitor_b32' must be a constant integer}} - *b64out = __builtin_amdgcn_global_load_monitor_b64(b64gaddr, cpol); // expected-error {{'__builtin_amdgcn_global_load_monitor_b64' must be a constant integer}} - *b128out = __builtin_amdgcn_global_load_monitor_b128(b128gaddr, cpol); // expected-error {{'__builtin_amdgcn_global_load_monitor_b128' must be a constant integer}} - *b32out = __builtin_amdgcn_flat_load_monitor_b32(b32faddr, cpol); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b32' must be a constant integer}} - *b64out = __builtin_amdgcn_flat_load_monitor_b64(b64faddr, cpol); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b64' must be a constant integer}} - *b128out = __builtin_amdgcn_flat_load_monitor_b128(b128faddr, cpol); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b128' must be a constant integer}} + *b32out = __builtin_amdgcn_global_load_monitor_b32(b32gaddr, ao, __MEMORY_SCOPE_SYSTEM); // expected-error {{'__builtin_amdgcn_global_load_monitor_b32' must be a constant integer}} + *b64out = __builtin_amdgcn_global_load_monitor_b64(b64gaddr, ao, __MEMORY_SCOPE_SYSTEM); // expected-error {{'__builtin_amdgcn_global_load_monitor_b64' must be a constant integer}} + *b128out = __builtin_amdgcn_global_load_monitor_b128(b128gaddr, ao, __MEMORY_SCOPE_SYSTEM); // expected-error {{'__builtin_amdgcn_global_load_monitor_b128' must be a constant integer}} + *b32out = __builtin_amdgcn_flat_load_monitor_b32(b32faddr, ao, __MEMORY_SCOPE_SYSTEM); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b32' must be a constant integer}} + *b64out = __builtin_amdgcn_flat_load_monitor_b64(b64faddr, ao, __MEMORY_SCOPE_SYSTEM); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b64' must be a constant integer}} + *b128out = __builtin_amdgcn_flat_load_monitor_b128(b128faddr, ao, __MEMORY_SCOPE_SYSTEM); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b128' must be a constant integer}} +} + +void test_amdgcn_load_monitor_ao_valid(global int* b32gaddr, global v2i* b64gaddr, global v4i* b128gaddr, int *b32faddr, v2i* b64faddr, v4i *b128faddr, + global int* b32out, global v2i* b64out, global v4i* b128out) +{ + *b32out = __builtin_amdgcn_global_load_monitor_b32(b32gaddr, __ATOMIC_RELEASE, __MEMORY_SCOPE_SYSTEM); // expected-warning {{memory order argument to atomic operation is invalid}} + *b64out = __builtin_amdgcn_global_load_monitor_b64(b64gaddr, __ATOMIC_ACQ_REL, __MEMORY_SCOPE_SYSTEM); // expected-warning {{memory order argument to atomic operation is invalid}} + *b128out = __builtin_amdgcn_global_load_monitor_b128(b128gaddr, __ATOMIC_ACQ_REL, __MEMORY_SCOPE_SYSTEM); // expected-warning {{memory order argument to atomic operation is invalid}} + *b32out = __builtin_amdgcn_flat_load_monitor_b32(b32faddr, __ATOMIC_RELEASE, __MEMORY_SCOPE_SYSTEM); // expected-warning {{memory order argument to atomic operation is invalid}} + *b64out = __builtin_amdgcn_flat_load_monitor_b64(b64faddr, __ATOMIC_ACQ_REL, __MEMORY_SCOPE_SYSTEM); // expected-warning {{memory order argument to atomic operation is invalid}} + *b128out = __builtin_amdgcn_flat_load_monitor_b128(b128faddr, __ATOMIC_RELEASE, __MEMORY_SCOPE_SYSTEM); // expected-warning {{memory order argument to atomic operation is invalid}} +} + +void test_amdgcn_load_monitor_scope_constant(global int* b32gaddr, global v2i* b64gaddr, global v4i* b128gaddr, int *b32faddr, v2i* b64faddr, v4i *b128faddr, + global int* b32out, global v2i* b64out, global v4i* b128out, int sc) +{ + *b32out = __builtin_amdgcn_global_load_monitor_b32(b32gaddr, __ATOMIC_RELAXED, sc); // expected-error {{'__builtin_amdgcn_global_load_monitor_b32' must be a constant integer}} + *b64out = __builtin_amdgcn_global_load_monitor_b64(b64gaddr, __ATOMIC_RELAXED, sc); // expected-error {{'__builtin_amdgcn_global_load_monitor_b64' must be a constant integer}} + *b128out = __builtin_amdgcn_global_load_monitor_b128(b128gaddr, __ATOMIC_RELAXED, sc); // expected-error {{'__builtin_amdgcn_global_load_monitor_b128' must be a constant integer}} + *b32out = __builtin_amdgcn_flat_load_monitor_b32(b32faddr, __ATOMIC_RELAXED, sc); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b32' must be a constant integer}} + *b64out = __builtin_amdgcn_flat_load_monitor_b64(b64faddr, __ATOMIC_RELAXED, sc); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b64' must be a constant integer}} + *b128out = __builtin_amdgcn_flat_load_monitor_b128(b128faddr, __ATOMIC_RELAXED, sc); // expected-error {{'__builtin_amdgcn_flat_load_monitor_b128' must be a constant integer}} +} + +void test_amdgcn_load_monitor_scope_valid(global int* b32gaddr, global v2i* b64gaddr, global v4i* b128gaddr, int *b32faddr, v2i* b64faddr, v4i *b128faddr, + global int* b32out, global v2i* b64out, global v4i* b128out) +{ + *b32out = __builtin_amdgcn_global_load_monitor_b32(b32gaddr, __ATOMIC_RELAXED, 42); // expected-error {{synchronization scope argument to atomic operation is invalid}} + *b64out = __builtin_amdgcn_global_load_monitor_b64(b64gaddr, __ATOMIC_RELAXED, 42); // expected-error {{synchronization scope argument to atomic operation is invalid}} + *b128out = __builtin_amdgcn_global_load_monitor_b128(b128gaddr, __ATOMIC_RELAXED, 42); // expected-error {{synchronization scope argument to atomic operation is invalid}} + *b32out = __builtin_amdgcn_flat_load_monitor_b32(b32faddr, __ATOMIC_RELAXED, 42); // expected-error {{synchronization scope argument to atomic operation is invalid}} + *b64out = __builtin_amdgcn_flat_load_monitor_b64(b64faddr, __ATOMIC_RELAXED, 42); // expected-error {{synchronization scope argument to atomic operation is invalid}} + *b128out = __builtin_amdgcn_flat_load_monitor_b128(b128faddr, __ATOMIC_RELAXED, 42); // expected-error {{synchronization scope argument to atomic operation is invalid}} } void test_amdgcn_cluster_load(global int* addr32, global v2i* addr64, global v4i* addr128, global int* b32out, global v2i* b64out, global v4i* b128out, int cpol, int mask) diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-s-wait-event.cl b/clang/test/SemaOpenCL/builtins-amdgcn-s-wait-event.cl new file mode 100644 index 0000000000000..1a9d40cf90cbe --- /dev/null +++ b/clang/test/SemaOpenCL/builtins-amdgcn-s-wait-event.cl @@ -0,0 +1,27 @@ +// xUN: %clang_cc1 -fsyntax-only -triple amdgcn-- -target-cpu gfx1100 -verify=ALL,GFX11 %s +// RUN: %clang_cc1 -fsyntax-only -triple amdgcn-- -target-cpu gfx1200 -verify=ALL,GFX12 %s + +void test(int x) { + // ALL-error@+1 {{argument to '__builtin_amdgcn_s_wait_event' must be a constant integer}} + __builtin_amdgcn_s_wait_event(x); + + // GFX11-expected-no-diagnostics + // GFX12-warning@+2 {{event mask has no effect for target}} + // GFX12-note@+1 {{value of 2 valid for export_ready for gfx11 and gfx12+}} + __builtin_amdgcn_s_wait_event(0); // 0 does nothing on gfx12 + + // GFX11-expected-no-diagnostics + // GFX12-warning@+2 {{event mask has no effect for target}} + // GFX12-note@+1 {{value of 2 valid for export_ready for gfx11 and gfx12+}} + __builtin_amdgcn_s_wait_event(1); // 1 does nothing on gfx11 + + __builtin_amdgcn_s_wait_event(2); // expected-no-diagnostics + + // ALL-warning@+2 {{event mask has no effect for target}} + // ALL-note@+1 {{value of 2 valid for export_ready for gfx11 and gfx12+}} + __builtin_amdgcn_s_wait_event(3); + + // ALL-warning@+2 {{event mask has no effect for target}} + // ALL-note@+1 {{value of 2 valid for export_ready for gfx11 and gfx12+}} + __builtin_amdgcn_s_wait_event(-1); +} diff --git a/clang/test/TableGen/target-builtins-prototype-parser.td b/clang/test/TableGen/target-builtins-prototype-parser.td index 1cd40444e35a0..ea22b8ed626eb 100644 --- a/clang/test/TableGen/target-builtins-prototype-parser.td +++ b/clang/test/TableGen/target-builtins-prototype-parser.td @@ -69,6 +69,12 @@ def : Builtin { let Spellings = ["__builtin_10"]; } +def : Builtin { +// CHECK: Builtin::Info{{.*}} __builtin_11 {{.*}} /* V2i*0 */ + let Prototype = "_Vector<2, int> address_space<0> *()"; + let Spellings = ["__builtin_11"]; +} + #ifdef ERROR_EXPECTED_LANES def : Builtin { // ERROR_EXPECTED_LANES: :[[# @LINE + 1]]:7: error: Expected number of lanes after '_ExtVector<' diff --git a/clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected b/clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected index 96370b4bec2d9..cf38dfb21a7c6 100644 --- a/clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected +++ b/clang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected @@ -58,7 +58,7 @@ int main() { // // // CHECK-LABEL: define dso_local void @_ZN3FooD2Ev( -// CHECK-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK-SAME: ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -67,12 +67,12 @@ int main() { // // // CHECK-LABEL: define dso_local void @_ZN3FooD1Ev( -// CHECK-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// CHECK-SAME: ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3FooD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2:[0-9]+]] +// CHECK-NEXT: call void @_ZN3FooD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2:[0-9]+]] // CHECK-NEXT: ret void // // @@ -87,7 +87,7 @@ int main() { // CHECK-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZNK3Foo28function_defined_out_of_lineEi(ptr noundef nonnull align 4 dereferenceable(4) [[F]], i32 noundef 3) // CHECK-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZL18static_noinline_fni(i32 noundef 0) // CHECK-NEXT: store i32 [[CALL2]], ptr [[RETVAL]], align 4 -// CHECK-NEXT: call void @_ZN3FooD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) #[[ATTR2]] +// CHECK-NEXT: call void @_ZN3FooD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[F]]) #[[ATTR2]] // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 4 // CHECK-NEXT: ret i32 [[TMP0]] // @@ -159,7 +159,7 @@ int main() { // // // MACHO-LABEL: define void @_ZN3FooD2Ev( -// MACHO-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// MACHO-SAME: ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // MACHO-NEXT: [[ENTRY:.*:]] // MACHO-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // MACHO-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -168,12 +168,12 @@ int main() { // // // MACHO-LABEL: define void @_ZN3FooD1Ev( -// MACHO-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// MACHO-SAME: ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // MACHO-NEXT: [[ENTRY:.*:]] // MACHO-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // MACHO-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // MACHO-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// MACHO-NEXT: call void @_ZN3FooD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2:[0-9]+]] +// MACHO-NEXT: call void @_ZN3FooD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2:[0-9]+]] // MACHO-NEXT: ret void // // @@ -188,7 +188,7 @@ int main() { // MACHO-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZNK3Foo28function_defined_out_of_lineEi(ptr noundef nonnull align 4 dereferenceable(4) [[F]], i32 noundef 3) // MACHO-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZL18static_noinline_fni(i32 noundef 0) // MACHO-NEXT: store i32 [[CALL2]], ptr [[RETVAL]], align 4 -// MACHO-NEXT: call void @_ZN3FooD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) #[[ATTR2]] +// MACHO-NEXT: call void @_ZN3FooD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[F]]) #[[ATTR2]] // MACHO-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 4 // MACHO-NEXT: ret i32 [[TMP0]] // @@ -243,7 +243,7 @@ int main() { // MSVC-NEXT: [[CALL2:%.*]] = call noundef i32 @"?function_defined_out_of_line@Foo@@QEBAHH@Z"(ptr noundef nonnull align 4 dereferenceable(4) [[F]], i32 noundef 3) // MSVC-NEXT: [[CALL3:%.*]] = call noundef i32 @"?static_noinline_fn@@YAHH@Z"(i32 noundef 0) // MSVC-NEXT: store i32 [[CALL3]], ptr [[RETVAL]], align 4 -// MSVC-NEXT: call void @"??1Foo@@QEAA@XZ"(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) #[[ATTR2:[0-9]+]] +// MSVC-NEXT: call void @"??1Foo@@QEAA@XZ"(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[F]]) #[[ATTR2:[0-9]+]] // MSVC-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 4 // MSVC-NEXT: ret i32 [[TMP0]] // @@ -276,7 +276,7 @@ int main() { // // // MINGW-LABEL: define dso_local void @_ZN3FooD2Ev( -// MINGW-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// MINGW-SAME: ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // MINGW-NEXT: [[ENTRY:.*:]] // MINGW-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // MINGW-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 @@ -285,12 +285,12 @@ int main() { // // // MINGW-LABEL: define dso_local void @_ZN3FooD1Ev( -// MINGW-SAME: ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { +// MINGW-SAME: ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR0]] align 2 { // MINGW-NEXT: [[ENTRY:.*:]] // MINGW-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // MINGW-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // MINGW-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// MINGW-NEXT: call void @_ZN3FooD2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2:[0-9]+]] +// MINGW-NEXT: call void @_ZN3FooD2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR2:[0-9]+]] // MINGW-NEXT: ret void // // @@ -305,7 +305,7 @@ int main() { // MINGW-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZNK3Foo28function_defined_out_of_lineEi(ptr noundef nonnull align 4 dereferenceable(4) [[F]], i32 noundef 3) // MINGW-NEXT: [[CALL2:%.*]] = call noundef i32 @_ZL18static_noinline_fni(i32 noundef 0) // MINGW-NEXT: store i32 [[CALL2]], ptr [[RETVAL]], align 4 -// MINGW-NEXT: call void @_ZN3FooD1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[F]]) #[[ATTR2]] +// MINGW-NEXT: call void @_ZN3FooD1Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[F]]) #[[ATTR2]] // MINGW-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 4 // MINGW-NEXT: ret i32 [[TMP0]] // diff --git a/clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected b/clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected index 2ed8693d181d7..ce9ea6b84fdf3 100644 --- a/clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected +++ b/clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected @@ -52,7 +52,7 @@ public: // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3FooIcED2Ev(ptr noundef nonnull align 1 dereferenceable(1) [[THIS1]]) #[[ATTR1:[0-9]+]] +// CHECK-NEXT: call void @_ZN3FooIcED2Ev(ptr noundef nonnull align 1 dead_on_return(1) dereferenceable(1) [[THIS1]]) #[[ATTR1:[0-9]+]] // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3FooIcE3getEv( @@ -94,7 +94,7 @@ template struct Foo; // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3FooIsED2Ev(ptr noundef nonnull align 2 dereferenceable(2) [[THIS1]]) #[[ATTR1]] +// CHECK-NEXT: call void @_ZN3FooIsED2Ev(ptr noundef nonnull align 2 dead_on_return(2) dereferenceable(2) [[THIS1]]) #[[ATTR1]] // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3FooIsE3getEv( @@ -139,7 +139,7 @@ template struct Foo; // CHECK-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[THIS:%.*]], ptr [[THIS_ADDR]], align 8 // CHECK-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-NEXT: call void @_ZN3BarIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR1]] +// CHECK-NEXT: call void @_ZN3BarIiED2Ev(ptr noundef nonnull align 4 dead_on_return(4) dereferenceable(4) [[THIS1]]) #[[ATTR1]] // CHECK-NEXT: ret void // // CHECK-LABEL: @_ZN3BarIiE3getEv( diff --git a/clang/tools/cir-opt/cir-opt.cpp b/clang/tools/cir-opt/cir-opt.cpp index ee42015bb38e9..edadfeec09a2a 100644 --- a/clang/tools/cir-opt/cir-opt.cpp +++ b/clang/tools/cir-opt/cir-opt.cpp @@ -17,6 +17,7 @@ #include "mlir/Dialect/Func/IR/FuncOps.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" #include "mlir/Dialect/MemRef/IR/MemRef.h" +#include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "mlir/IR/BuiltinDialect.h" #include "mlir/Pass/PassManager.h" #include "mlir/Pass/PassOptions.h" @@ -35,7 +36,7 @@ int main(int argc, char **argv) { mlir::DialectRegistry registry; registry.insert(); + mlir::DLTIDialect, mlir::omp::OpenMPDialect>(); ::mlir::registerPass([]() -> std::unique_ptr<::mlir::Pass> { return mlir::createCIRCanonicalizePass(); diff --git a/clang/tools/cir-translate/cir-translate.cpp b/clang/tools/cir-translate/cir-translate.cpp index 29a310a89de09..2b00d1bd62e4a 100644 --- a/clang/tools/cir-translate/cir-translate.cpp +++ b/clang/tools/cir-translate/cir-translate.cpp @@ -13,6 +13,7 @@ #include "mlir/Dialect/DLTI/DLTI.h" #include "mlir/Dialect/Func/IR/FuncOps.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "mlir/IR/BuiltinOps.h" #include "mlir/IR/MLIRContext.h" #include "mlir/InitAllTranslations.h" @@ -105,7 +106,8 @@ llvm::LogicalResult prepareCIRModuleDataLayout(mlir::ModuleOp mod, std::string layoutString = targetInfo->getDataLayoutString(); // Registered dialects may not be loaded yet, ensure they are. - context->loadDialect(); + context->loadDialect(); mlir::DataLayoutSpecInterface dlSpec = mlir::translateDataLayout(llvm::DataLayout(layoutString), context); diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index 48a3c5f97e375..619e539857fc6 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -409,8 +409,19 @@ fatbinary(ArrayRef> InputFiles, } // namespace nvptx namespace amdgcn { + +// Constructs a triple string for clang offload bundler. +// NOTE: copied from HIPUtility.cpp. +static std::string normalizeForBundler(const llvm::Triple &T, + bool HasTargetID) { + return HasTargetID ? (T.getArchName() + "-" + T.getVendorName() + "-" + + T.getOSName() + "-" + T.getEnvironmentName()) + .str() + : T.normalize(llvm::Triple::CanonicalForm::FOUR_IDENT); +} + Expected -fatbinary(ArrayRef> InputFiles, +fatbinary(ArrayRef> InputFiles, const ArgList &Args) { llvm::TimeTraceScope TimeScope("AMDGPU Fatbinary"); @@ -441,10 +452,10 @@ fatbinary(ArrayRef> InputFiles, Args.MakeArgString(Twine("-compression-level=") + Arg->getValue())); SmallVector Targets = {"-targets=host-x86_64-unknown-linux-gnu"}; - for (const auto &[File, Arch] : InputFiles) { - Targets.push_back(Saver.save(Arch == "amdgcnspirv" - ? "hip-spirv64-amd-amdhsa--" + Arch - : "hip-amdgcn-amd-amdhsa--" + Arch)); + for (const auto &[File, TripleRef, Arch] : InputFiles) { + std::string NormalizedTriple = + normalizeForBundler(Triple(TripleRef), !Arch.empty()); + Targets.push_back(Saver.save("hip-" + NormalizedTriple + "-" + Arch)); } CmdArgs.push_back(Saver.save(llvm::join(Targets, ","))); @@ -453,7 +464,7 @@ fatbinary(ArrayRef> InputFiles, #else CmdArgs.push_back("-input=/dev/null"); #endif - for (const auto &[File, Arch] : InputFiles) + for (const auto &[File, Triple, Arch] : InputFiles) CmdArgs.push_back(Saver.save("-input=" + File)); CmdArgs.push_back(Saver.save("-output=" + *TempFileOrErr)); @@ -816,10 +827,11 @@ bundleCuda(ArrayRef Images, const ArgList &Args) { Expected>> bundleHIP(ArrayRef Images, const ArgList &Args) { - SmallVector, 4> InputFiles; + SmallVector, 4> InputFiles; for (const OffloadingImage &Image : Images) - InputFiles.emplace_back(std::make_pair(Image.Image->getBufferIdentifier(), - Image.StringData.lookup("arch"))); + InputFiles.emplace_back(std::make_tuple(Image.Image->getBufferIdentifier(), + Image.StringData.lookup("triple"), + Image.StringData.lookup("arch"))); auto FileOrErr = amdgcn::fatbinary(InputFiles, Args); if (!FileOrErr) diff --git a/clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp b/clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp index de20e74360fbc..6c400e39405f6 100644 --- a/clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp +++ b/clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp @@ -12,6 +12,7 @@ // with the fully linked source bitcode file(s), running several SYCL specific // post-link steps on the fully linked bitcode file(s), and finally generating // target-specific device code. +// //===---------------------------------------------------------------------===// #include "clang/Basic/OffloadArch.h" @@ -54,7 +55,7 @@ using namespace clang; /// Save intermediary results. static bool SaveTemps = false; -/// Print arguments without executing. +/// Print commands/steps with arguments without executing. static bool DryRun = false; /// Print verbose output. @@ -312,13 +313,15 @@ Expected linkDeviceCode(ArrayRef InputFiles, return *BitcodeOutput; } -/// Run LLVM to SPIR-V translation. -/// Converts 'File' from LLVM bitcode to SPIR-V format using SPIR-V backend. -/// 'Args' encompasses all arguments required for linking device code and will -/// be parsed to generate options required to be passed into the backend. -static Error runSPIRVCodeGen(StringRef File, const ArgList &Args, - StringRef OutputFile, LLVMContext &C) { - llvm::TimeTraceScope TimeScope("SPIR-V code generation"); +/// Run Code Generation using LLVM backend. +/// \param 'File' The input LLVM IR bitcode file. +/// \param 'Args' encompasses all arguments required for linking device code and +/// will be parsed to generate options required to be passed into the backend. +/// \param 'OutputFile' The output file name. +/// \param 'C' The LLVM context. +static Error runCodeGen(StringRef File, const ArgList &Args, + StringRef OutputFile, LLVMContext &C) { + llvm::TimeTraceScope TimeScope("Code generation"); // Parse input module. SMDiagnostic Err; @@ -332,13 +335,13 @@ static Error runSPIRVCodeGen(StringRef File, const ArgList &Args, Triple TargetTriple(Args.getLastArgValue(OPT_triple_EQ)); M->setTargetTriple(TargetTriple); - // Get a handle to SPIR-V target backend. + // Get a handle to a target backend. std::string Msg; const Target *T = TargetRegistry::lookupTarget(M->getTargetTriple(), Msg); if (!T) return createStringError(Msg + ": " + M->getTargetTriple().str()); - // Allocate SPIR-V target machine. + // Allocate target machine. TargetOptions Options; std::optional RM; std::optional CM; @@ -358,17 +361,16 @@ static Error runSPIRVCodeGen(StringRef File, const ArgList &Args, return errorCodeToError(EC); auto OS = std::make_unique(FD, true); - // Run SPIR-V codegen passes to generate SPIR-V file. legacy::PassManager CodeGenPasses; TargetLibraryInfoImpl TLII(M->getTargetTriple()); CodeGenPasses.add(new TargetLibraryInfoWrapperPass(TLII)); if (TM->addPassesToEmitFile(CodeGenPasses, *OS, nullptr, CodeGenFileType::ObjectFile)) - return createStringError("Failed to execute SPIR-V Backend"); + return createStringError("Failed to execute LLVM backend"); CodeGenPasses.run(*M); if (Verbose) - errs() << formatv("SPIR-V Backend: input: {0}, output: {1}\n", File, + errs() << formatv("LLVM backend: input: {0}, output: {1}\n", File, OutputFile); return Error::success(); @@ -507,11 +509,11 @@ Error runSYCLLink(ArrayRef Files, const ArgList &Args) { bool IsAOTCompileNeeded = IsIntelOffloadArch( StringToOffloadArch(Args.getLastArgValue(OPT_arch_EQ))); - // SPIR-V code generation step. + // Code generation step. for (size_t I = 0, E = SplitModules.size(); I != E; ++I) { StringRef Stem = OutputFile.rsplit('.').first; std::string SPVFile = (Stem + "_" + Twine(I) + ".spv").str(); - if (Error Err = runSPIRVCodeGen(SplitModules[I], Args, SPVFile, C)) + if (Error Err = runCodeGen(SplitModules[I], Args, SPVFile, C)) return Err; if (!IsAOTCompileNeeded) { SplitModules[I] = SPVFile; diff --git a/clang/tools/libclang/CXCursor.cpp b/clang/tools/libclang/CXCursor.cpp index 08ea73dcded08..17f485e5c78a5 100644 --- a/clang/tools/libclang/CXCursor.cpp +++ b/clang/tools/libclang/CXCursor.cpp @@ -310,6 +310,7 @@ CXCursor cxcursor::MakeCXCursor(const Stmt *S, const Decl *Parent, case Stmt::CXXDefaultArgExprClass: case Stmt::CXXDefaultInitExprClass: case Stmt::CXXFoldExprClass: + case Stmt::CXXReflectExprClass: case Stmt::CXXRewrittenBinaryOperatorClass: case Stmt::CXXStdInitializerListExprClass: case Stmt::CXXScalarValueInitExprClass: @@ -322,6 +323,7 @@ CXCursor cxcursor::MakeCXCursor(const Stmt *S, const Decl *Parent, case Stmt::ExprWithCleanupsClass: case Stmt::ExpressionTraitExprClass: case Stmt::ExtVectorElementExprClass: + case Stmt::MatrixElementExprClass: case Stmt::ImplicitCastExprClass: case Stmt::ImplicitValueInitExprClass: case Stmt::NoInitExprClass: diff --git a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp index c0a03deb5b543..a3281f948fdb7 100644 --- a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp +++ b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "ASTMatchersTest.h" -#include "clang/AST/Attrs.inc" +#include "clang/AST/Attr.h" #include "clang/AST/DeclCXX.h" #include "clang/AST/PrettyPrinter.h" #include "clang/ASTMatchers/ASTMatchFinder.h" diff --git a/clang/unittests/Analysis/CFGBackEdgesTest.cpp b/clang/unittests/Analysis/CFGBackEdgesTest.cpp new file mode 100644 index 0000000000000..1bf699c65ec81 --- /dev/null +++ b/clang/unittests/Analysis/CFGBackEdgesTest.cpp @@ -0,0 +1,312 @@ +//===- unittests/Analysis/CFGBackEdgesTest.cpp - CFG backedges tests ------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "clang/Analysis/CFGBackEdges.h" +#include "CFGBuildResult.h" +#include "clang/AST/Stmt.h" +#include "clang/Analysis/CFG.h" +#include "clang/Basic/LLVM.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" + +namespace clang { +namespace analysis { +namespace { + +using ::testing::IsNull; +using ::testing::NotNull; +using ::testing::SizeIs; + +TEST(CFGBackEdgesTest, NoBackedgesLinear) { + const char *Code = R"cc( + int f(int x) { + l1: + x++; + l2: + x++; + return x; + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_TRUE(BackEdges.empty()); +} + +TEST(CFGBackEdgesTest, NoBackedgesOnlyCrossEdge) { + const char *Code = R"cc( + int f(int x) { + if (x > 0) + x++; + else + x--; + return x; + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_TRUE(BackEdges.empty()); +} + +TEST(CFGBackEdgesTest, NoBackedgesWithUnreachableSuccessorForSwitch) { + const char *Code = R"cc( + enum class Kind { A, B }; + + void f(Kind kind) { + switch(kind) { + case Kind::A: return 0; + case Kind::B: break; + } + return 1; + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_TRUE(BackEdges.empty()); +} + +TEST(CFGBackEdgesTest, ForLoop) { + const char *Code = R"cc( + void f(int n) { + for (int i = 0; i < n; ++i) {} + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + // Finds one backedge, which is the one looping back to the loop header + // (has a loop target). + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_THAT(BackEdges, SizeIs(1)); + EXPECT_THAT(BackEdges.begin()->first->getLoopTarget(), NotNull()); +} + +TEST(CFGBackEdgesTest, WhileLoop) { + const char *Code = R"cc( + void f(int n) { + int i = 0; + while (i < n) { ++i; } + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_THAT(BackEdges, SizeIs(1)); + EXPECT_THAT(BackEdges.begin()->first->getLoopTarget(), NotNull()); +} + +TEST(CFGBackEdgesTest, DoWhileLoop) { + const char *Code = R"cc( + void f(int n) { + int i = 0; + do { ++i; } while (i < n); + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_THAT(BackEdges, SizeIs(1)); + EXPECT_THAT(BackEdges.begin()->first->getLoopTarget(), NotNull()); +} + +TEST(CFGBackEdgesTest, GotoLoop) { + const char *Code = R"cc( + void f(int n) { + int i = 0; + loop: + if (i < n) { + ++i; + goto loop; + } + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + // Finds one backedge, but since it's an unstructured loop, the loop target is + // null. Instead, the node has a goto terminator. + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_THAT(BackEdges, SizeIs(1)); + EXPECT_THAT(BackEdges.begin()->first->getLoopTarget(), IsNull()); + EXPECT_TRUE(isa(BackEdges.begin()->first->getTerminatorStmt())); +} + +TEST(CFGBackEdgesTest, WhileWithContinueLoop) { + const char *Code = R"cc( + void f(int n) { + int i = 0; + while (i < n) { + ++i; + if (i == 5) continue; + if (i == 10) break; + i *= 2; + } + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_THAT(BackEdges, SizeIs(testing::Gt(0))); + for (const auto &[From, To] : BackEdges) + EXPECT_THAT(From->getLoopTarget(), NotNull()); +} + +TEST(CFGBackEdgesTest, NestedForLoop) { + const char *Code = R"cc( + void f(int n) { + for (int i = 0; i < n; ++i) { + for (int j = i; j < n; ++j) {} + } + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_THAT(BackEdges, SizeIs(2)); + auto It = BackEdges.begin(); + auto *FirstLoopTarget = It->first->getLoopTarget(); + EXPECT_THAT(FirstLoopTarget, NotNull()); + ++It; + auto *SecondLoopTarget = It->first->getLoopTarget(); + EXPECT_THAT(SecondLoopTarget, NotNull()); + EXPECT_NE(FirstLoopTarget, SecondLoopTarget); +} + +TEST(CFGBackEdgesTest, IrreducibleCFG) { + const char *Code = R"cc( + void f(int cond) { + if (cond) goto L1; + L0: + goto L1; + L1: + goto L0; + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdges = findCFGBackEdges(*Cfg); + // In an irreducible CFG, we still expect to find a back edge. + EXPECT_THAT(BackEdges, SizeIs(1)); + EXPECT_TRUE(isa(BackEdges.begin()->first->getTerminatorStmt())); +} + +TEST(CFGBackEdgesTest, FirstBackedgeIsNotGoto) { + const char *Code = R"cc( + void f(int x, int y) { + if (x > y) { + } else { + L1: + --x; + if (x == 0) return; + } + goto L1; + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + + auto BackEdges = findCFGBackEdges(*Cfg); + EXPECT_THAT(BackEdges, SizeIs(1)); + // We might find a backedge where the source block doesn't terminate with + // a `goto`, due to the DFS search order. For example: + // + // B_entry: `if (x > y)` + // \--then--> B1: `` + // --> B2: `goto L1` + // --> B3: `--x; if (x == 0)` + // \--then--> B4 `return` --> B_exit. + // \--else--> B2: ... (the `if`'s else is a backedge from B3 to B2!) + // \--else--> B3: ... + EXPECT_FALSE(isa(BackEdges.begin()->first->getTerminatorStmt())); +} + +TEST(CFGBackEdgesTest, FindNonStructuredLoopBackedgeNodes) { + const char *Code = R"cc( + void f(int n) { + for (int i = 0; i < n; ++i) { + int j = 0; + inner_loop: + if (j < n) { + ++j; + goto inner_loop; + } + } + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + // Finds just the goto backedge, and not the for-loop backedge. + auto BackEdgeNodes = findNonStructuredLoopBackedgeNodes(*Cfg); + EXPECT_THAT(BackEdgeNodes, SizeIs(1)); + const CFGBlock *Node = *BackEdgeNodes.begin(); + EXPECT_EQ(Node->getLoopTarget(), nullptr); + EXPECT_TRUE(isa(Node->getTerminatorStmt())); +} + +TEST(CFGBackEdgesTest, IsBackedgeCFGNode) { + const char *Code = R"cc( + void f(int n) { + for (int i = 0; i < n; ++i) { + int j = 0; + inner_loop: + if (j < n) { + ++j; + goto inner_loop; + } + } + })cc"; + BuildResult Result = BuildCFG(Code); + EXPECT_EQ(BuildResult::BuiltCFG, Result.getStatus()); + CFG *Cfg = Result.getCFG(); + ASSERT_THAT(Cfg, NotNull()); + + auto BackEdgeNodes = findNonStructuredLoopBackedgeNodes(*Cfg); + + // `isBackedgeCFGNode` should be true for both the for-loop backedge node and + // goto backedge nodes. + const CFGBlock *ForLoopBackedgeNode = nullptr; + const CFGBlock *GotoBackedgeNode = nullptr; + for (const CFGBlock *Block : *Cfg) { + if (Block->getLoopTarget() != nullptr) { + ForLoopBackedgeNode = Block; + } else if (Block->getTerminatorStmt() != nullptr && + isa(Block->getTerminatorStmt())) { + GotoBackedgeNode = Block; + } + } + ASSERT_THAT(ForLoopBackedgeNode, NotNull()); + ASSERT_THAT(GotoBackedgeNode, NotNull()); + EXPECT_TRUE(isBackedgeCFGNode(*ForLoopBackedgeNode, BackEdgeNodes)); + EXPECT_TRUE(isBackedgeCFGNode(*GotoBackedgeNode, BackEdgeNodes)); +} + +} // namespace +} // namespace analysis +} // namespace clang diff --git a/clang/unittests/Analysis/CMakeLists.txt b/clang/unittests/Analysis/CMakeLists.txt index 97e768b11db69..7cefa2caf3c91 100644 --- a/clang/unittests/Analysis/CMakeLists.txt +++ b/clang/unittests/Analysis/CMakeLists.txt @@ -1,4 +1,5 @@ add_clang_unittest(ClangAnalysisTests + CFGBackEdgesTest.cpp CFGDominatorTree.cpp CFGTest.cpp CloneDetectionTest.cpp diff --git a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp index e528ca2221ad1..3c79c367415aa 100644 --- a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp @@ -1011,6 +1011,54 @@ TEST(TransferTest, BinaryOperatorAssignUnknown) { }); } +TEST(TransferTest, BinaryOperatorAssignFloat) { + using ast_matchers::binaryOperator; + using ast_matchers::hasOperatorName; + using ast_matchers::match; + using ast_matchers::selectFirst; + + // This was crashing. + std::string Code = R"( + void target() { + double Foo = 0.0f; + double FooAtA = Foo; + Foo = 1.0f; + double FooAtB = Foo; + bool check = (FooAtA == FooAtB); + // [[p]] + } + )"; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + ASSERT_THAT(Results.keys(), UnorderedElementsAre("p")); + + const Environment &EnvP = getEnvironmentAtAnnotation(Results, "p"); + + const ValueDecl *FooAtADecl = findValueDecl(ASTCtx, "FooAtA"); + ASSERT_THAT(FooAtADecl, NotNull()); + const Value *FooAtAVal = EnvP.getValue(*FooAtADecl); + // FIXME: Should be non-null. Floats aren't modeled at all. + EXPECT_THAT(FooAtAVal, IsNull()); + + const ValueDecl *FooAtBDecl = findValueDecl(ASTCtx, "FooAtB"); + ASSERT_THAT(FooAtBDecl, NotNull()); + const Value *FooAtBVal = EnvP.getValue(*FooAtBDecl); + // FIXME: Should be non-null. Floats aren't modeled at all. + EXPECT_THAT(FooAtBVal, IsNull()); + + // See if the storage location is correctly propagated. + auto MatchResult = + match(binaryOperator(hasOperatorName("=")).bind("bo"), ASTCtx); + const auto *BO = selectFirst("bo", MatchResult); + ASSERT_THAT(BO, NotNull()); + const StorageLocation *BOLoc = EnvP.getStorageLocation(*BO); + // FIXME: Should be non-null. + EXPECT_THAT(BOLoc, IsNull()); + }); +} + TEST(TransferTest, VarDeclInitAssign) { std::string Code = R"( void target() { @@ -3786,6 +3834,34 @@ TEST(TransferTest, StaticCastBaseToDerived) { }); } +TEST(TransferTest, StaticCastBaseToDerivedUnknown) { + // This code used to crash. + std::string Code = R"( + struct Base {}; + struct Derived: Base {}; + + Base *unknown(); + void target() { + Derived *DPtr = static_cast(unknown()); + // [[p]] + } + )"; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + ASSERT_THAT(Results.keys(), UnorderedElementsAre("p")); + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + + const ValueDecl *DPtrDecl = findValueDecl(ASTCtx, "DPtr"); + ASSERT_THAT(DPtrDecl, NotNull()); + + const auto *DPtrVal = + dyn_cast_or_null(Env.getValue(*DPtrDecl)); + EXPECT_THAT(DPtrVal, NotNull()); + }); +} + TEST(TransferTest, MultipleConstructionsFromStaticCastsBaseToDerived) { std::string Code = R"cc( struct Base {}; diff --git a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp index d1dd4ff3ea33e..3a64bbdf52702 100644 --- a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp @@ -1145,6 +1145,34 @@ TEST_F(WideningTest, DistinctValuesWithDifferentPropertiesWidenedToTop) { }); } +TEST_F(WideningTest, + DistinctValuesWithDifferentPropertiesWidenedToTopGotoInsteadOfWhile) { + std::string Code = R"cc( + void target(bool Cond) { + int *Foo; + int i = 0; + Foo = nullptr; + start: + if (Cond) { + Foo = &i; + goto start; + } + (void)0; + /*[[p]]*/ + } + )cc"; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + const auto &FooVal = getValueForDecl(ASTCtx, Env, "Foo"); + ASSERT_THAT(FooVal.getProperty("is_null"), NotNull()); + EXPECT_TRUE(areEquivalentValues(*FooVal.getProperty("is_null"), + Env.makeTopBoolValue())); + }); +} + class FlowConditionTest : public Test { protected: template @@ -1253,18 +1281,47 @@ TEST_F(FlowConditionTest, WhileStmt) { } TEST_F(FlowConditionTest, WhileStmtWithAssignmentInCondition) { - std::string Code = R"( + std::string Code = R"cc( + bool getBool(); + void target(bool Foo) { // This test checks whether the analysis preserves the connection between // the value of `Foo` and the assignment expression, despite widening. - // The equality operator generates a fresh boolean variable on each - // interpretation, which forces use of widening. - while ((Foo = (3 == 4))) { + // The return value of getBool() should have a fresh boolean variable on + // each interpretation, which forces use of widening. + while (Foo = getBool()) { (void)0; /*[[p]]*/ } } - )"; + )cc"; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + auto &FooVal = getValueForDecl(ASTCtx, Env, "Foo").formula(); + EXPECT_TRUE(Env.proves(FooVal)); + }); +} + +TEST_F(FlowConditionTest, GotoLoopWithAssignmentInCondition) { + std::string Code = R"cc( + bool getBool(); + + void target(bool Foo) { + // This test checks whether the analysis preserves the connection between + // the value of `Foo` and the assignment expression, despite widening. + // The return value of getBool() should have a fresh boolean variable on + // each interpretation, which forces use of widening. + start: + if (Foo = getBool()) { + (void)0; + /*[[p]]*/ + goto start; + } + } + )cc"; runDataflow( Code, [](const llvm::StringMap> &Results, diff --git a/clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp b/clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp index 5be4e38133744..f842abe9e454a 100644 --- a/clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp +++ b/clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp @@ -1129,6 +1129,102 @@ TEST_P(UncheckedStatusOrAccessModelTest, BuiltinExpect) { )cc"); } +TEST_P(UncheckedStatusOrAccessModelTest, CopyConstructor) { + ExpectDiagnosticsFor( + R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_INT sor1 = Make(); + auto sor2 = sor1; + auto sor3 = sor2; + if (sor1.ok()) { + sor1.value(); + + sor2.value(); + + sor3.value(); + } else { + sor1.value(); // [[unsafe]] + + sor2.value(); // [[unsafe]] + + sor3.value(); // [[unsafe]] + } + } + )cc"); + ExpectDiagnosticsFor( + R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_INT sor1 = Make(); + auto sor2 = sor1; + auto sor3 = sor2; + + STATUS s = sor1.status(); + if (s.ok()) { + sor1.value(); + + sor2.value(); + + sor3.value(); + } else { + sor1.value(); // [[unsafe]] + + sor2.value(); // [[unsafe]] + + sor3.value(); // [[unsafe]] + } + } + )cc"); + ExpectDiagnosticsFor( + R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_INT x = Make(); + if (!x.ok()) return; + + STATUSOR_INT y = x; + y.value(); + } + )cc"); + ExpectDiagnosticsFor( + R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_INT x = Make(); + if (x.ok()) { + STATUSOR_INT y = x; + y.value(); + } + } + )cc"); +} + +TEST_P(UncheckedStatusOrAccessModelTest, MoveConstructor) { + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_INT sor1(42); + STATUSOR_INT sor2(std::move(sor1)); + sor2.value(); + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_INT sor1 = Make(); + STATUSOR_INT sor2(std::move(sor1)); + sor2.value(); // [[unsafe]] + } + )cc"); +} + TEST_P(UncheckedStatusOrAccessModelTest, CopyAssignment) { ExpectDiagnosticsFor(R"cc( #include "unchecked_statusor_access_test_defs.h" @@ -1201,6 +1297,29 @@ TEST_P(UncheckedStatusOrAccessModelTest, CopyAssignment) { )cc"); } +TEST_P(UncheckedStatusOrAccessModelTest, MoveAssignment) { + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_INT sor1(42); + STATUSOR_INT sor2; + sor2 = std::move(sor1); + sor2.value(); + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_INT sor1 = Make(); + STATUSOR_INT sor2; + sor2 = std::move(sor1); + sor2.value(); // [[unsafe]] + } + )cc"); +} + TEST_P(UncheckedStatusOrAccessModelTest, ShortCircuitingBinaryOperators) { ExpectDiagnosticsFor(R"cc( #include "unchecked_statusor_access_test_defs.h" @@ -1831,6 +1950,119 @@ TEST_P(UncheckedStatusOrAccessModelTest, QcheckNeMacro) { )cc"); } +TEST_P(UncheckedStatusOrAccessModelTest, Member) { + // The following examples are not sound as there could be member calls between + // the ok() and the value() calls that change the StatusOr value. + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + struct Foo { + STATUSOR_INT bar; + }; + + void target() { + Foo foo; + if (foo.bar.ok()) foo.bar.value(); + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + struct Foo { + STATUSOR_INT sor; + }; + + void target(Foo foo) { + foo.sor.value(); // [[unsafe]] + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + struct Foo { + STATUSOR_INT sor; + }; + + void target(Foo foo) { + if (foo.sor.ok()) + foo.sor.value(); + else + foo.sor.value(); // [[unsafe]] + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + struct Foo { + STATUSOR_INT sor; + }; + + void target(Foo foo) { + if (foo.sor.status().ok()) + foo.sor.value(); + else + foo.sor.value(); // [[unsafe]] + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + struct Foo { + STATUSOR_INT sor; + + void target() { + if (sor.ok()) + sor.value(); + else + sor.value(); // [[unsafe]] + } + }; + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + struct Foo { + STATUSOR_INT sor; + + void target(bool b) { + if (b) { + if (!sor.ok()) return; + } else { + if (!sor.ok()) return; + } + sor.value(); + } + }; + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + struct Foo { + struct Bar { + STATUSOR_INT sor; + + void target() { + if (sor.ok()) + sor.value(); + else + sor.value(); // [[unsafe]] + } + }; + }; + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + struct Foo { + STATUSOR_INT sor; + }; + + void target() { + Foo().sor.value(); // [[unsafe]] + } + )cc"); +} + TEST_P(UncheckedStatusOrAccessModelTest, GlobalVars) { // The following examples are not sound as there could be opaque calls between // the ok() and the value() calls that change the StatusOr value. @@ -2111,6 +2343,26 @@ TEST_P(UncheckedStatusOrAccessModelTest, Status) { )cc"); } +TEST_P(UncheckedStatusOrAccessModelTest, StatusBranches) { + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target() { + STATUSOR_VOIDPTR sor; + STATUS s; + if (Make()) { + s = absl::InvalidArgumentError("foo"); + } else { + sor = Make(); + if (!sor.ok()) { + s = sor.status(); + } + } + if (s.ok()) *sor; + } + )cc"); +} + TEST_P(UncheckedStatusOrAccessModelTest, ExpectThatMacro) { ExpectDiagnosticsFor(R"cc( #include "unchecked_statusor_access_test_defs.h" @@ -2355,6 +2607,63 @@ TEST_P(UncheckedStatusOrAccessModelTest, AssertTrueMacro) { )cc"); } +TEST_P(UncheckedStatusOrAccessModelTest, ExpectTrueMacro) { + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUSOR_INT sor) { + EXPECT_TRUE(sor.ok()); + + sor.value(); // [[unsafe]] + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUSOR_INT sor) { + EXPECT_TRUE(sor.status().ok()); + + sor.value(); // [[unsafe]] + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUSOR_INT sor) { + EXPECT_TRUE(!sor.ok()); + + sor.value(); // [[unsafe]] + } + )cc"); +} + +TEST_P(UncheckedStatusOrAccessModelTest, AssertFalseMacro) { + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUSOR_INT sor) { + ASSERT_FALSE(!sor.ok()); + sor.value(); + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUSOR_INT sor) { + ASSERT_FALSE(!sor.status().ok()); + sor.value(); + } + )cc"); + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUSOR_INT sor) { + ASSERT_FALSE(sor.ok()); + sor.value(); // [[unsafe]] + } + )cc"); +} + TEST_P(UncheckedStatusOrAccessModelTest, AssertOkMacro) { ExpectDiagnosticsFor(R"cc( #include "unchecked_statusor_access_test_defs.h" @@ -3960,6 +4269,38 @@ TEST_P(UncheckedStatusOrAccessModelTest, StatusPtrReference) { )cc"); } +TEST_P(UncheckedStatusOrAccessModelTest, PairIterator) { + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + class iterator { + public: + const std::pair>* operator->() const; + }; + void target() { + if (auto it = Make(); it->second.ok()) { + it->second.value(); + } + } +)cc"); +} + +TEST_P(UncheckedStatusOrAccessModelTest, PairIteratorRef) { + ExpectDiagnosticsFor(R"cc( +#include "unchecked_statusor_access_test_defs.h" + + class iterator { + public: + const std::pair>& operator*() const; + }; + void target() { + if (auto it = Make(); (*it).second.ok()) { + (*it).second.value(); + } + } +)cc"); +} + } // namespace std::string diff --git a/clang/unittests/Analysis/Scalable/CMakeLists.txt b/clang/unittests/Analysis/Scalable/CMakeLists.txt index a21002e313ead..601845b4ab77a 100644 --- a/clang/unittests/Analysis/Scalable/CMakeLists.txt +++ b/clang/unittests/Analysis/Scalable/CMakeLists.txt @@ -4,8 +4,11 @@ add_distinct_clang_unittest(ClangScalableAnalysisTests EntityIdTest.cpp EntityIdTableTest.cpp EntityNameTest.cpp + Registries/FancyAnalysisData.cpp + Registries/MockSerializationFormat.cpp Registries/MockSummaryExtractor1.cpp Registries/MockSummaryExtractor2.cpp + Registries/SerializationFormatRegistryTest.cpp Registries/SummaryExtractorRegistryTest.cpp SummaryNameTest.cpp diff --git a/clang/unittests/Analysis/Scalable/Registries/FancyAnalysisData.cpp b/clang/unittests/Analysis/Scalable/Registries/FancyAnalysisData.cpp new file mode 100644 index 0000000000000..0f06ed7e159b5 --- /dev/null +++ b/clang/unittests/Analysis/Scalable/Registries/FancyAnalysisData.cpp @@ -0,0 +1,57 @@ +//===- FancyAnalysisData.cpp ----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Registries/MockSerializationFormat.h" +#include "clang/Analysis/Scalable/TUSummary/EntitySummary.h" +#include "llvm/Support/Registry.h" + +using namespace clang; +using namespace ssaf; + +using SpecialFileRepresentation = + MockSerializationFormat::SpecialFileRepresentation; + +namespace { +struct FancyAnalysisData : EntitySummary { + FancyAnalysisData() : EntitySummary(SummaryName("FancyAnalysis")) {} + + std::string Text; +}; +} // namespace + +static SpecialFileRepresentation +serializeFancyAnalysis(const EntitySummary &Data, + MockSerializationFormat &Format) { + const auto &FancyAnalysis = static_cast(Data); + return SpecialFileRepresentation{/*MockRepresentation=*/FancyAnalysis.Text}; +} + +static std::unique_ptr +deserializeFancyAnalysis(const SpecialFileRepresentation &File, + EntityIdTable &) { + auto Result = std::make_unique(); + Result->Text = File.MockRepresentation; + return std::move(Result); +} + +namespace { +using FormatInfo = MockSerializationFormat::FormatInfo; +struct FancyAnalysisFormatInfo : FormatInfo { + FancyAnalysisFormatInfo() + : FormatInfo{ + SummaryName("FancyAnalysis"), + serializeFancyAnalysis, + deserializeFancyAnalysis, + } {} +}; +} // namespace + +static llvm::Registry::Add + RegisterFormatInfo("FancyAnalysisData", + "Format info for FancyAnalysisData for the " + "MockSerializationFormat format"); diff --git a/clang/unittests/Analysis/Scalable/Registries/MockSerializationFormat.cpp b/clang/unittests/Analysis/Scalable/Registries/MockSerializationFormat.cpp new file mode 100644 index 0000000000000..44904d53d2412 --- /dev/null +++ b/clang/unittests/Analysis/Scalable/Registries/MockSerializationFormat.cpp @@ -0,0 +1,139 @@ +//===- MockSerializationFormat.cpp ----------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Registries/MockSerializationFormat.h" +#include "clang/Analysis/Scalable/Model/BuildNamespace.h" +#include "clang/Analysis/Scalable/Model/EntityName.h" +#include "clang/Analysis/Scalable/Model/SummaryName.h" +#include "clang/Analysis/Scalable/Serialization/SerializationFormat.h" +#include "clang/Analysis/Scalable/Serialization/SerializationFormatRegistry.h" +#include "clang/Analysis/Scalable/TUSummary/TUSummary.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include +#include + +using namespace clang; +using namespace ssaf; + +MockSerializationFormat::MockSerializationFormat( + llvm::IntrusiveRefCntPtr FS) + : SerializationFormat(FS) { + for (const auto &FormatInfoEntry : llvm::Registry::entries()) { + std::unique_ptr Info = FormatInfoEntry.instantiate(); + bool Inserted = FormatInfos.try_emplace(Info->ForSummary, *Info).second; + if (!Inserted) { + llvm::report_fatal_error( + "Format info was already registered for summary name: " + + Info->ForSummary.str()); + } + } +} + +TUSummary MockSerializationFormat::readTUSummary(llvm::StringRef Path) { + BuildNamespace NS(BuildNamespaceKind::CompilationUnit, "Mock.cpp"); + TUSummary Summary(NS); + + auto ManifestFile = FS->getBufferForFile(Path + "/analyses.txt"); + assert(ManifestFile); // TODO Handle error. + llvm::StringRef ManifestFileContent = (*ManifestFile)->getBuffer(); + + llvm::SmallVector Analyses; + ManifestFileContent.split(Analyses, /*Separator=*/"\n", /*MaxSplit=*/-1, + /*KeepEmpty=*/false); + + for (llvm::StringRef Analysis : Analyses) { + SummaryName Name(Analysis.str()); + auto InputFile = FS->getBufferForFile(Path + "/" + Name.str() + ".special"); + assert(InputFile); + auto InfoIt = FormatInfos.find(Name); + if (InfoIt == FormatInfos.end()) { + llvm::report_fatal_error( + "No FormatInfo was registered for summary name: " + Name.str()); + } + const auto &InfoEntry = InfoIt->second; + assert(InfoEntry.ForSummary == Name); + + SpecialFileRepresentation Repr{(*InputFile)->getBuffer().str()}; + auto &Table = getIdTableForDeserialization(Summary); + + std::unique_ptr Result = InfoEntry.Deserialize(Repr, Table); + if (!Result) // TODO: Handle error. + continue; + + EntityId FooId = Table.getId(EntityName{"c:@F@foo", "", /*Namespace=*/{}}); + auto &IdMappings = getData(Summary).try_emplace(Name).first->second; + [[maybe_unused]] bool Inserted = + IdMappings.try_emplace(FooId, std::move(Result)).second; + assert(Inserted); + } + + return Summary; +} + +void MockSerializationFormat::writeTUSummary(const TUSummary &Summary, + llvm::StringRef OutputDir) { + std::error_code EC; + + // Check if output directory exists, create if needed + if (!llvm::sys::fs::exists(OutputDir)) { + EC = llvm::sys::fs::create_directories(OutputDir); + if (EC) { + llvm::report_fatal_error("Failed to create output directory '" + + OutputDir + "': " + EC.message()); + } + } + + std::set Analyses; + for (const auto &[SummaryName, EntityMappings] : getData(Summary)) { + [[maybe_unused]] bool Inserted = Analyses.insert(SummaryName).second; + assert(Inserted); + for (const auto &Data : llvm::make_second_range(EntityMappings)) { + auto InfoIt = FormatInfos.find(SummaryName); + if (InfoIt == FormatInfos.end()) { + llvm::report_fatal_error( + "There was no FormatInfo registered for summary name '" + + SummaryName.str() + "'"); + } + const auto &InfoEntry = InfoIt->second; + assert(InfoEntry.ForSummary == SummaryName); + + auto Output = InfoEntry.Serialize(*Data, *this); + + std::string AnalysisFilePath = + (OutputDir + "/" + SummaryName.str() + ".special").str(); + llvm::raw_fd_ostream AnalysisOutputFile(AnalysisFilePath, EC); + if (EC) { + llvm::report_fatal_error("Failed to create file '" + AnalysisFilePath + + "': " + llvm::StringRef(EC.message())); + } + AnalysisOutputFile << Output.MockRepresentation; + } + } + + std::string ManifestFilePath = (OutputDir + "/analyses.txt").str(); + llvm::raw_fd_ostream ManifestFile(ManifestFilePath, EC); + if (EC) { + llvm::report_fatal_error("Failed to create manifest file '" + + ManifestFilePath + + "': " + llvm::StringRef(EC.message())); + } + + interleave(map_range(Analyses, std::mem_fn(&SummaryName::str)), ManifestFile, + "\n"); + ManifestFile << "\n"; +} + +static SerializationFormatRegistry::Add + RegisterFormat("MockSerializationFormat", + "A serialization format for testing"); diff --git a/clang/unittests/Analysis/Scalable/Registries/MockSerializationFormat.h b/clang/unittests/Analysis/Scalable/Registries/MockSerializationFormat.h new file mode 100644 index 0000000000000..a106e53fc20ac --- /dev/null +++ b/clang/unittests/Analysis/Scalable/Registries/MockSerializationFormat.h @@ -0,0 +1,44 @@ +//===- MockSerializationFormat.h --------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_UNITTESTS_ANALYSIS_SCALABLE_REGISTRIES_MOCKSERIALIZATIONFORMAT_H +#define LLVM_CLANG_UNITTESTS_ANALYSIS_SCALABLE_REGISTRIES_MOCKSERIALIZATIONFORMAT_H + +#include "clang/Analysis/Scalable/Model/SummaryName.h" +#include "clang/Analysis/Scalable/Serialization/SerializationFormat.h" +#include "llvm/ADT/STLFunctionalExtras.h" +#include + +namespace clang::ssaf { + +class MockSerializationFormat final : public SerializationFormat { +public: + explicit MockSerializationFormat( + llvm::IntrusiveRefCntPtr FS); + + TUSummary readTUSummary(llvm::StringRef Path) override; + + void writeTUSummary(const TUSummary &Summary, + llvm::StringRef OutputDir) override; + + struct SpecialFileRepresentation { + std::string MockRepresentation; + }; + + using SerializerFn = llvm::function_ref; + using DeserializerFn = llvm::function_ref( + const SpecialFileRepresentation &, EntityIdTable &)>; + + using FormatInfo = FormatInfoEntry; + std::map FormatInfos; +}; + +} // namespace clang::ssaf + +#endif // LLVM_CLANG_UNITTESTS_ANALYSIS_SCALABLE_REGISTRIES_MOCKSERIALIZATIONFORMAT_H diff --git a/clang/unittests/Analysis/Scalable/Registries/SerializationFormatRegistryTest.cpp b/clang/unittests/Analysis/Scalable/Registries/SerializationFormatRegistryTest.cpp new file mode 100644 index 0000000000000..484c38309e3d8 --- /dev/null +++ b/clang/unittests/Analysis/Scalable/Registries/SerializationFormatRegistryTest.cpp @@ -0,0 +1,89 @@ +//===- SummaryExtractorRegistryTest.cpp -----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "clang/Analysis/Scalable/Serialization/SerializationFormatRegistry.h" +#include "clang/Analysis/Scalable/TUSummary/TUSummary.h" +#include "llvm/ADT/ScopeExit.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/VirtualFileSystem.h" +#include "gtest/gtest.h" +#include + +using namespace llvm; +using namespace clang; +using namespace ssaf; + +// Returns the file name and content in a map. +static std::map readFilesFromDir(StringRef DirPath) { + std::map Result; + std::error_code EC; + + for (sys::fs::directory_iterator It(DirPath, EC), End; It != End && !EC; + It.increment(EC)) { + StringRef FilePath = It->path(); + + if (sys::fs::is_directory(FilePath)) + continue; + + auto BufferOrErr = MemoryBuffer::getFile(FilePath); + if (!BufferOrErr) + continue; + + // Store only the filename (relative to DirPath). + StringRef FileName = sys::path::filename(FilePath); + Result[FileName.str()] = BufferOrErr.get()->getBuffer().str(); + } + + return Result; +} +namespace { + +TEST(SerializationFormatRegistryTest, isFormatRegistered) { + EXPECT_FALSE(isFormatRegistered("Non-existent-format")); + EXPECT_TRUE(isFormatRegistered("MockSerializationFormat")); +} + +TEST(SerializationFormatRegistryTest, EnumeratingRegistryEntries) { + auto Formats = SerializationFormatRegistry::entries(); + ASSERT_EQ(std::distance(Formats.begin(), Formats.end()), 1U); + EXPECT_EQ(Formats.begin()->getName(), "MockSerializationFormat"); +} + +TEST(SerializationFormatRegistryTest, Roundtrip) { + auto Inputs = makeIntrusiveRefCnt(); + Inputs->addFile("input/analyses.txt", /*ModificationTime=*/{}, + MemoryBuffer::getMemBufferCopy("FancyAnalysis\n")); + Inputs->addFile("input/FancyAnalysis.special", /*ModificationTime=*/{}, + MemoryBuffer::getMemBufferCopy("Some FancyAnalysisData...")); + + std::unique_ptr Format = + makeFormat(Inputs, "MockSerializationFormat"); + ASSERT_TRUE(Format); + + TUSummary LoadedSummary = Format->readTUSummary("input"); + + // Create a temporary output directory + SmallString<128> OutputDir; + std::error_code EC = sys::fs::createUniqueDirectory("ssaf-test", OutputDir); + ASSERT_FALSE(EC) << "Failed to create temporary directory: " << EC.message(); + llvm::scope_exit CleanupOnExit( + [&] { sys::fs::remove_directories(OutputDir); }); + + Format->writeTUSummary(LoadedSummary, OutputDir); + + EXPECT_EQ(readFilesFromDir(OutputDir), + (std::map{ + {"analyses.txt", "FancyAnalysis\n"}, + {"FancyAnalysis.special", "Some FancyAnalysisData..."}, + })); +} + +} // namespace diff --git a/clang/utils/TableGen/CIRLoweringEmitter.cpp b/clang/utils/TableGen/CIRLoweringEmitter.cpp index d50373bb8b5dc..21c3caca7c66d 100644 --- a/clang/utils/TableGen/CIRLoweringEmitter.cpp +++ b/clang/utils/TableGen/CIRLoweringEmitter.cpp @@ -140,7 +140,6 @@ void GenerateLLVMLoweringPattern(llvm::StringRef OpName, Code << "class " << PatternName << " : public mlir::OpConversionPattern {\n"; - Code << " [[maybe_unused]] cir::LowerModule *lowerMod;\n"; Code << " [[maybe_unused]] mlir::DataLayout const &dataLayout;\n"; if (CustomCtor) { @@ -156,10 +155,8 @@ void GenerateLLVMLoweringPattern(llvm::StringRef OpName, // Constructor Code << " " << PatternName - << "(mlir::TypeConverter const " - "&typeConverter, mlir::MLIRContext *context, " - "cir::LowerModule *lowerMod, mlir::DataLayout const " - "&dataLayout"; + << "(const mlir::TypeConverter &typeConverter, " + "mlir::MLIRContext *context, const mlir::DataLayout &dataLayout"; if (CustomCtor) emitCustomParamList(Code, CustomCtor->Params); @@ -167,8 +164,7 @@ void GenerateLLVMLoweringPattern(llvm::StringRef OpName, Code << ")\n"; Code << " : OpConversionPattern(typeConverter, context), lowerMod(lowerMod), " - "dataLayout(dataLayout)"; + << ">(typeConverter, context), dataLayout(dataLayout)"; if (CustomCtor) emitCustomInitList(Code, CustomCtor->Params); diff --git a/clang/utils/TableGen/ClangBuiltinsEmitter.cpp b/clang/utils/TableGen/ClangBuiltinsEmitter.cpp index fb089a811ef92..d61226a5c5f5c 100644 --- a/clang/utils/TableGen/ClangBuiltinsEmitter.cpp +++ b/clang/utils/TableGen/ClangBuiltinsEmitter.cpp @@ -265,7 +265,9 @@ class PrototypeParser { if (T.consume_back("*")) { // Pointers may have an address space qualifier immediately before them. std::optional AS = ConsumeAddrSpace(); - ParseType(T); + // Pointers can apply to already parsed types, like vectors. + if (!T.empty()) + ParseType(T); Type += "*"; if (AS) Type += std::to_string(*AS); diff --git a/compiler-rt/include/sanitizer/ubsan_interface.h b/compiler-rt/include/sanitizer/ubsan_interface.h index 30a7fd875043d..b53d6013c71cd 100644 --- a/compiler-rt/include/sanitizer/ubsan_interface.h +++ b/compiler-rt/include/sanitizer/ubsan_interface.h @@ -27,6 +27,28 @@ extern "C" { /// \returns Default options string. const char *SANITIZER_CDECL __ubsan_default_options(void); +/// Set up an interval timer and install a SIGPROF signal handler that crashes +/// the program if it is stuck in a trap loop generated by -fsanitize-trap-loop. +/// +/// This function is only intended to be called by single-threaded programs. +/// Because interval timers are delivered to an arbitrary thread in the process, +/// it is possible that a thread in a trap loop will never have the signal +/// delivered to it. For multi-threaded programs, it is recommended to call +/// OS-specific APIs such as timer_create(CLOCK_THREAD_CPUTIME_ID) on Linux to +/// install a timer on each thread. +/// +/// Programs with their own signal handlers can call __ubsan_is_trap_loop from +/// the signal handler to implement trap loop handling. +/// +/// This function is currently only supported on Linux/x86. +void __ubsan_install_trap_loop_detection(void); + +/// Returns whether uc (actually a pointer to ucontext_t) indicates that the +/// thread is stuck in a trap loop generated by -fsanitize-trap-loop. +/// +/// This function is currently only supported on Linux/x86. +int __ubsan_is_trap_loop(void *uc); + #ifdef __cplusplus } // extern "C" #endif diff --git a/compiler-rt/lib/asan/asan_flags.cpp b/compiler-rt/lib/asan/asan_flags.cpp index 190a89345dd18..e4bf87f463857 100644 --- a/compiler-rt/lib/asan/asan_flags.cpp +++ b/compiler-rt/lib/asan/asan_flags.cpp @@ -160,7 +160,12 @@ static void ProcessFlags() { // Make "strict_init_order" imply "check_initialization_order". // TODO(samsonov): Use a single runtime flag for an init-order checker. if (f->strict_init_order) { +#if SANITIZER_AIX + Report("WARNING: strict_init_order is not supported on AIX.\n"); + f->strict_init_order = false; +#else f->check_initialization_order = true; +#endif } CHECK_LE((uptr)common_flags()->malloc_context_size, kStackTraceMax); CHECK_LE(f->min_uar_stack_size_log, f->max_uar_stack_size_log); diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt index 6e454f23c3da2..f43ef4743ff97 100644 --- a/compiler-rt/lib/builtins/CMakeLists.txt +++ b/compiler-rt/lib/builtins/CMakeLists.txt @@ -516,6 +516,10 @@ set(arm_EABI_RT_SOURCES arm/aeabi_ldivmod.S arm/aeabi_uidivmod.S arm/aeabi_uldivmod.S + arm/aeabi_uread4.S + arm/aeabi_uread8.S + arm/aeabi_uwrite4.S + arm/aeabi_uwrite8.S ) set(arm_EABI_CLIB_SOURCES @@ -839,6 +843,16 @@ if (NOT OS_NAME MATCHES "AIX") ${powerpc64_SOURCES} ) endif() +if (OS_NAME MATCHES "AIX") + set(powerpc_SOURCES + ppc/init_ifuncs.c + ${powerpc_SOURCES} + ) + set(powerpc64_SOURCES + ppc/init_ifuncs.c + ${powerpc64_SOURCES} + ) +endif() set(powerpc64le_SOURCES ${powerpc64_SOURCES}) set(riscv_SOURCES diff --git a/compiler-rt/lib/builtins/arm/aeabi_uread4.S b/compiler-rt/lib/builtins/arm/aeabi_uread4.S new file mode 100644 index 0000000000000..4a54890fdf830 --- /dev/null +++ b/compiler-rt/lib/builtins/arm/aeabi_uread4.S @@ -0,0 +1,63 @@ +//===-- aeabi_uread4.S - ARM EABI Helper — Unaligned 4-Byte Memory Read ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Implements __aeabi_uread4 for unaligned memory accesses. +// Reference: Arm RTABI32 Specification. +// https://github.com/ARM-software/abi-aa/blob/main/rtabi32/rtabi32.rst#unaligned-memory-access +//===-------------------------------------------------------------------------------------===// + +#include "../assembly.h" + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_uread4) +#if defined(__thumb__) && !defined(__thumb2__) +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + ldrb r1, [r0] + ldrb r2, [r0, #1] + lsls r2, r2, #8 + adds r1, r2, r1 + ldrb r2, [r0, #2] + lsls r2, r2, #16 + ldrb r0, [r0, #3] + lsls r0, r0, #24 + adds r0, r0, r2 + adds r0, r0, r1 +#else + ldrb r1, [r0, #3] + ldrb r2, [r0, #2] + lsls r2, r2, #8 + adds r1, r2, r1 + ldrb r2, [r0, #1] + lsls r2, r2, #16 + ldrb r0, [r0] + lsls r0, r0, #24 + adds r0, r0, r2 + adds r0, r0, r1 +#endif + bx lr +#else +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + ldrb r1, [r0] + ldrb r2, [r0, #1] + ldrb r3, [r0, #2] + ldrb r0, [r0, #3] + orr r0, r3, r0, lsl #8 + orr r1, r1, r2, lsl #8 + orr r0, r1, r0, lsl #16 +#else + ldrb r1, [r0] + ldrb r2, [r0, #1] + ldrb r3, [r0, #2] + ldrb r0, [r0, #3] + orr r1, r2, r1, lsl #8 + orr r0, r0, r3, lsl #8 + orr r0, r0, r1, lsl #16 +#endif + bx lr +#endif +END_COMPILERRT_FUNCTION(__aeabi_uread4) + diff --git a/compiler-rt/lib/builtins/arm/aeabi_uread8.S b/compiler-rt/lib/builtins/arm/aeabi_uread8.S new file mode 100644 index 0000000000000..32844b8b3c7e1 --- /dev/null +++ b/compiler-rt/lib/builtins/arm/aeabi_uread8.S @@ -0,0 +1,100 @@ +//===-- aeabi_uread8.S - ARM EABI Helper — Unaligned 8-Byte Memory Read----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Implements __aeabi_uread8 for unaligned memory accesses. +// Reference: Arm RTABI32 Specification. +// https://github.com/ARM-software/abi-aa/blob/main/rtabi32/rtabi32.rst#unaligned-memory-access +//===-------------------------------------------------------------------------------------===// + +#include "../assembly.h" + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_uread8) +#if defined(__thumb__) && !defined(__thumb2__) +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + ldrb r1, [r0] + ldrb r2, [r0, #1] + lsls r2, r2, #8 + adds r1, r2, r1 + ldrb r2, [r0, #2] + lsls r2, r2, #16 + ldrb r3, [r0, #3] + lsls r3, r3, #24 + adds r2, r3, r2 + adds r2, r2, r1 + ldrb r1, [r0, #4] + ldrb r3, [r0, #5] + lsls r3, r3, #8 + adds r1, r3, r1 + ldrb r3, [r0, #6] + lsls r3, r3, #16 + ldrb r0, [r0, #7] + lsls r0, r0, #24 + adds r0, r0, r3 + adds r1, r0, r1 +#else + ldrb r1, [r0, #3] + ldrb r2, [r0, #2] + lsls r2, r2, #8 + adds r1, r2, r1 + ldrb r2, [r0, #1] + lsls r2, r2, #16 + ldrb r3, [r0] + lsls r3, r3, #24 + adds r2, r3, r2 + adds r2, r2, r1 + ldrb r1, [r0, #7] + ldrb r3, [r0, #6] + lsls r3, r3, #8 + adds r1, r3, r1 + ldrb r3, [r0, #5] + lsls r3, r3, #16 + ldrb r0, [r0, #4] + lsls r0, r0, #24 + adds r0, r0, r3 + adds r1, r0, r1 +#endif + mov r0, r2 + bx lr +#else +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + ldrb r12, [r0] + ldrb r2, [r0, #1] + ldrb r3, [r0, #2] + ldrb r1, [r0, #3] + orr r1, r3, r1, lsl #8 + orr r2, r12, r2, lsl #8 + orr r2, r2, r1, lsl #16 + ldrb r1, [r0, #5] + ldrb r3, [r0, #4]! + orr r1, r3, r1, lsl #8 + ldrb r3, [r0, #2] + ldrb r0, [r0, #3] + orr r0, r3, r0, lsl #8 + orr r1, r1, r0, lsl #16 +#else + ldrb r12, [r0] + ldrb r2, [r0, #1] + ldrb r3, [r0, #2] + ldrb r1, [r0, #3] + orr r2, r2, r12, lsl #8 + orr r1, r1, r3, lsl #8 + orr r2, r1, r2, lsl #16 + mov r1, r0 + ldrb r0, [r0, #5] + ldrb r3, [r1, #4]! + orr r0, r0, r3, lsl #8 + ldrb r3, [r1, #2] + ldrb r1, [r1, #3] + orr r1, r1, r3, lsl #8 + orr r1, r1, r0, lsl #16 +#endif + mov r0, r2 + bx lr +#endif + +END_COMPILERRT_FUNCTION(__aeabi_uread8) diff --git a/compiler-rt/lib/builtins/arm/aeabi_uwrite4.S b/compiler-rt/lib/builtins/arm/aeabi_uwrite4.S new file mode 100644 index 0000000000000..9f749695910be --- /dev/null +++ b/compiler-rt/lib/builtins/arm/aeabi_uwrite4.S @@ -0,0 +1,35 @@ +//===-- aeabi_uwrite4.S - ARM EABI Helper — Unaligned 4-Byte Memory Write--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Implements __aeabi_uwrite4 for unaligned memory accesses. +// Reference: Arm RTABI32 Specification. +// https://github.com/ARM-software/abi-aa/blob/main/rtabi32/rtabi32.rst#unaligned-memory-access +//===-------------------------------------------------------------------------------------===// + +#include "../assembly.h" + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_uwrite4) +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + lsrs r2, r0, #24 + strb r0, [r1] + strb r2, [r1, #3] + lsrs r2, r0, #16 + strb r2, [r1, #2] + lsrs r2, r0, #8 + strb r2, [r1, #1] +#else + lsrs r2, r0, #8 + strb r0, [r1, #3] + strb r2, [r1, #2] + lsrs r2, r0, #16 + strb r2, [r1, #1] + lsrs r2, r0, #24 + strb r2, [r1] +#endif + bx lr +END_COMPILERRT_FUNCTION(__aeabi_uwrite4) diff --git a/compiler-rt/lib/builtins/arm/aeabi_uwrite8.S b/compiler-rt/lib/builtins/arm/aeabi_uwrite8.S new file mode 100644 index 0000000000000..8188032fc3bd1 --- /dev/null +++ b/compiler-rt/lib/builtins/arm/aeabi_uwrite8.S @@ -0,0 +1,51 @@ +//===-- aeabi_uwrite8.S - ARM EABI Helper — Unaligned 8-Byte Memory Write--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Implements __aeabi_uwrite8 for unaligned memory accesses. +// Reference: Arm RTABI32 Specification. +// https://github.com/ARM-software/abi-aa/blob/main/rtabi32/rtabi32.rst#unaligned-memory-access +//===-------------------------------------------------------------------------------------===// + +#include "../assembly.h" + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_uwrite8) +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + strb r0, [r2, #0] + lsrs r3, r0, #8 + strb r3, [r2, #1] + lsrs r3, r0, #16 + strb r3, [r2, #2] + lsrs r3, r0, #24 + strb r3, [r2, #3] + + strb r1, [r2, #4] + lsrs r3, r1, #8 + strb r3, [r2, #5] + lsrs r3, r1, #16 + strb r3, [r2, #6] + lsrs r3, r1, #24 + strb r3, [r2, #7] +#else + lsrs r3, r0, #24 + strb r3, [r2, #0] + lsrs r3, r0, #16 + strb r3, [r2, #1] + lsrs r3, r0, #8 + strb r3, [r2, #2] + strb r0, [r2, #3] + + lsrs r3, r1, #24 + strb r3, [r2, #4] + lsrs r3, r1, #16 + strb r3, [r2, #5] + lsrs r3, r1, #8 + strb r3, [r2, #6] + strb r1, [r2, #7] +#endif + bx lr +END_COMPILERRT_FUNCTION(__aeabi_uwrite8) diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c index 55eb2b0958450..a71078e9064d5 100644 --- a/compiler-rt/lib/builtins/cpu_model/x86.c +++ b/compiler-rt/lib/builtins/cpu_model/x86.c @@ -105,6 +105,7 @@ enum ProcessorSubtypes { INTEL_COREI7_ARROWLAKE_S, INTEL_COREI7_PANTHERLAKE, AMDFAM1AH_ZNVER5, + AMDFAM1AH_ZNVER6, INTEL_COREI7_DIAMONDRAPIDS, INTEL_COREI7_NOVALAKE, CPU_SUBTYPE_MAX @@ -837,20 +838,27 @@ getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, case 26: CPU = "znver5"; Type = AMDFAM1AH; - if (Model <= 0x77) { + if (Model <= 0x4f || (Model >= 0x60 && Model <= 0x77) || + (Model >= 0xd0 && Model <= 0xd7)) { // Models 00h-0Fh (Breithorn). // Models 10h-1Fh (Breithorn-Dense). // Models 20h-2Fh (Strix 1). // Models 30h-37h (Strix 2). // Models 38h-3Fh (Strix 3). // Models 40h-4Fh (Granite Ridge). - // Models 50h-5Fh (Weisshorn). // Models 60h-6Fh (Krackan1). // Models 70h-77h (Sarlak). + // Models D0h-D7h (Annapurna). CPU = "znver5"; Subtype = AMDFAM1AH_ZNVER5; break; // "znver5" } + if ((Model >= 0x50 && Model <= 0x5f) || (Model >= 0x80 && Model <= 0xcf) || + (Model >= 0xd8 && Model <= 0xe7)) { + CPU = "znver6"; + Subtype = AMDFAM1AH_ZNVER6; + break; // "znver6" + } break; default: break; // Unknown AMD CPU. diff --git a/compiler-rt/lib/builtins/ppc/init_ifuncs.c b/compiler-rt/lib/builtins/ppc/init_ifuncs.c new file mode 100644 index 0000000000000..e95a5496d4c57 --- /dev/null +++ b/compiler-rt/lib/builtins/ppc/init_ifuncs.c @@ -0,0 +1,38 @@ +typedef void *Ptr; +typedef struct { + Ptr addr, toc, env; +} Descr; +typedef struct { + Descr *desc; + Ptr (*resolver)(); +} IFUNCPair; + +#define CONC2(A, B) A##B +#define CONC(A, B) CONC2(A, B) + +#define IFUNC_SEC __ifunc_sec +#define IFUNC_SEC_STR "__ifunc_sec" +#define START_SEC CONC(__start_, IFUNC_SEC) +#define STOP_SEC CONC(__stop_, IFUNC_SEC) + +// A zero-length entry in section "__ifunc_sec" to satisfy the START_SEC and +// STOP_SEC references in this file, when no user code has any ifuncs. +__attribute__((section(IFUNC_SEC_STR))) static int dummy_ifunc_sec[0]; + +extern IFUNCPair START_SEC, STOP_SEC; + +__attribute__((constructor)) void __init_ifuncs() { + void *volatile ref = &dummy_ifunc_sec; // hack to keep dummy_ifunc_sec alive + + // hack to prevent compiler from assuming START_SEC and STOP_SEC + // occupy different addresses. + IFUNCPair *volatile volatile_end = &STOP_SEC; + for (IFUNCPair *pair = &START_SEC, *end = volatile_end; pair != end; pair++) { + // Call the resolver and copy the entire descriptor because: + // - the resolved function might be in another DSO, so copy the TOC address + // - we might be linking with objects from a language that uses the + // enviroment pointer, so copy it too. + Descr *result = (Descr *)pair->resolver(); + *(pair->desc) = *result; + } +} diff --git a/compiler-rt/lib/scudo/standalone/primary64.h b/compiler-rt/lib/scudo/standalone/primary64.h index 40b4d56998189..11dfc8492ed03 100644 --- a/compiler-rt/lib/scudo/standalone/primary64.h +++ b/compiler-rt/lib/scudo/standalone/primary64.h @@ -1167,9 +1167,14 @@ void SizeClassAllocator64::getStats(ScopedString *Str, uptr ClassId, const u64 LastReleaseSecAgo = DiffSinceLastReleaseNs / 1000000000; const u64 LastReleaseMsAgo = (DiffSinceLastReleaseNs % 1000000000) / 1000000; - Str->append(" Latest release: %" PRIu64 ":%" PRIu64 " seconds ago", + Str->append(" Latest release: %6" PRIu64 ":%" PRIu64 " seconds ago", LastReleaseSecAgo, LastReleaseMsAgo); } +#if SCUDO_LINUX + const uptr MapBase = Region->MemMapInfo.MemMap.getBase(); + Str->append(" Resident Pages: %6" PRIu64, + getResidentPages(MapBase, RegionSize)); +#endif Str->append("\n"); } diff --git a/compiler-rt/lib/ubsan/CMakeLists.txt b/compiler-rt/lib/ubsan/CMakeLists.txt index a6c98c40ec772..f48db7c455bb8 100644 --- a/compiler-rt/lib/ubsan/CMakeLists.txt +++ b/compiler-rt/lib/ubsan/CMakeLists.txt @@ -9,6 +9,10 @@ set(UBSAN_SOURCES ubsan_value.cpp ) +set(UBSAN_LOOP_DETECT_SOURCES + ubsan_loop_detect.cpp + ) + set(UBSAN_STANDALONE_SOURCES ubsan_diag_standalone.cpp ubsan_init_standalone.cpp @@ -39,6 +43,7 @@ set(UBSAN_HEADERS ) include_directories(..) +include_directories(../../include) set(UBSAN_CFLAGS ${SANITIZER_COMMON_CFLAGS}) append_list_if(MSVC /Zl UBSAN_CFLAGS) @@ -155,6 +160,13 @@ else() ADDITIONAL_HEADERS ${UBSAN_HEADERS} CFLAGS ${UBSAN_CXXFLAGS}) + add_compiler_rt_object_libraries(RTUbsan_loop_detect + ARCHS ${UBSAN_COMMON_SUPPORTED_ARCH} + SOURCES ${UBSAN_LOOP_DETECT_SOURCES} + ADDITIONAL_HEADERS ${UBSAN_HEADERS} + CFLAGS ${UBSAN_CXXFLAGS} + DEPS compiler-rt-headers) + if (WIN32) set(RUNTIME_THUNK_CFLAGS -DSANITIZER_DYNAMIC_RUNTIME_THUNK -DSANITIZER_STATIC_RUNTIME_THUNK) add_compiler_rt_object_libraries(UbsanRuntimeThunk @@ -198,6 +210,13 @@ else() CFLAGS ${UBSAN_CXXFLAGS} PARENT_TARGET ubsan) + add_compiler_rt_runtime(clang_rt.ubsan_loop_detect + STATIC + ARCHS ${UBSAN_SUPPORTED_ARCH} + OBJECT_LIBS RTUbsan_loop_detect + CFLAGS ${UBSAN_CXXFLAGS} + PARENT_TARGET ubsan) + if (COMPILER_RT_HAS_VERSION_SCRIPT) file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/dummy.cpp "") add_compiler_rt_object_libraries(RTUbsan_dynamic_version_script_dummy @@ -251,6 +270,9 @@ else() ARCHS ${ARCHS_FOR_SYMBOLS} PARENT_TARGET ubsan EXTRA ubsan.syms.extra) + add_sanitizer_rt_symbols(clang_rt.ubsan_loop_detect + ARCHS ${ARCHS_FOR_SYMBOLS} + PARENT_TARGET ubsan) endif() endif() endif() diff --git a/compiler-rt/lib/ubsan/ubsan_loop_detect.cpp b/compiler-rt/lib/ubsan/ubsan_loop_detect.cpp new file mode 100644 index 0000000000000..75e9724a06f35 --- /dev/null +++ b/compiler-rt/lib/ubsan/ubsan_loop_detect.cpp @@ -0,0 +1,100 @@ +//===-- ubsan_loop_detect.cpp ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Runtime support for -fsanitize-trap-loop. +// +//===----------------------------------------------------------------------===// + +#include + +#if defined(__linux__) && (defined(__i386__) || defined(__x86_64__)) + +#include +#include +#include +#include +#include + +int __ubsan_is_trap_loop(void *c) { + auto *uc = reinterpret_cast(c); +#if defined(__x86_64__) + auto *ip = reinterpret_cast(uc->uc_mcontext.gregs[REG_RIP]); +#else + auto *ip = reinterpret_cast(uc->uc_mcontext.gregs[REG_EIP]); +#endif + // Test whether IP is at a conditional branch to self instruction. + if ((ip[0] & 0xf0) != 0x70 || ip[1] != 0xfe) + return false; + + // If so, test whether the condition is satisfied, in case we happened to + // receive the signal at a not-taken branch to self. + uint64_t eflags = uc->uc_mcontext.gregs[REG_EFL]; + switch (ip[0]) { + case 0x70: // JO + return eflags & X86_EFLAGS_OF; + case 0x71: // JNO + return !(eflags & X86_EFLAGS_OF); + case 0x72: // JB + return eflags & X86_EFLAGS_CF; + case 0x73: // JAE + return !(eflags & X86_EFLAGS_CF); + case 0x74: // JE + return eflags & X86_EFLAGS_ZF; + case 0x75: // JNE + return !(eflags & X86_EFLAGS_ZF); + case 0x76: // JBE + return (eflags & X86_EFLAGS_CF) || (eflags & X86_EFLAGS_ZF); + case 0x77: // JA + return !(eflags & X86_EFLAGS_CF) && !(eflags & X86_EFLAGS_ZF); + case 0x78: // JS + return eflags & X86_EFLAGS_SF; + case 0x79: // JNS + return !(eflags & X86_EFLAGS_SF); + case 0x7A: // JP + return eflags & X86_EFLAGS_PF; + case 0x7B: // JNP + return !(eflags & X86_EFLAGS_PF); + case 0x7C: // JL + return !!(eflags & X86_EFLAGS_SF) != !!(eflags & X86_EFLAGS_OF); + case 0x7D: // JGE + return !!(eflags & X86_EFLAGS_SF) == !!(eflags & X86_EFLAGS_OF); + case 0x7E: // JLE + return (eflags & X86_EFLAGS_ZF) || + !!(eflags & X86_EFLAGS_SF) != !!(eflags & X86_EFLAGS_OF); + case 0x7F: // JG + return !(eflags & X86_EFLAGS_ZF) && + !!(eflags & X86_EFLAGS_SF) == !!(eflags & X86_EFLAGS_OF); + default: + return false; + } +} + +static void SigprofHandler(int signo, siginfo_t *si, void *c) { + if (__ubsan_is_trap_loop(c)) { + __builtin_trap(); + } +} + +void __ubsan_install_trap_loop_detection(void) { + struct sigaction sa; + sa.sa_sigaction = SigprofHandler; + sigaction(SIGPROF, &sa, nullptr); + + struct itimerval timer; + timer.it_value.tv_sec = 0; + timer.it_value.tv_usec = 100000; + timer.it_interval = timer.it_value; + setitimer(ITIMER_PROF, &timer, NULL); +} + +#else + +int __ubsan_is_trap_loop(void *c) { return false; } +void __ubsan_install_trap_loop_detection(void) {} + +#endif diff --git a/compiler-rt/test/asan/TestCases/AIX/lit.local.cfg.py b/compiler-rt/test/asan/TestCases/AIX/lit.local.cfg.py new file mode 100644 index 0000000000000..3337c692bd0d7 --- /dev/null +++ b/compiler-rt/test/asan/TestCases/AIX/lit.local.cfg.py @@ -0,0 +1,10 @@ +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + + +root = getRoot(config) + +if root.target_os not in ["AIX"]: + config.unsupported = True diff --git a/compiler-rt/test/asan/TestCases/AIX/strict-init-order-warning.cpp b/compiler-rt/test/asan/TestCases/AIX/strict-init-order-warning.cpp new file mode 100644 index 0000000000000..14e8fefcc8b44 --- /dev/null +++ b/compiler-rt/test/asan/TestCases/AIX/strict-init-order-warning.cpp @@ -0,0 +1,6 @@ +// RUN: %clangxx_asan %s -o %t +// RUN: %env_asan_opts=strict_init_order=true %run %t 2>&1 | FileCheck %s + +// CHECK: WARNING: strict_init_order is not supported on AIX. + +int main() { return 0; } diff --git a/compiler-rt/test/asan/TestCases/initialization-bug-no-global.cpp b/compiler-rt/test/asan/TestCases/initialization-bug-no-global.cpp index 26dc0f0d29a6d..1d4fd5040ecd3 100644 --- a/compiler-rt/test/asan/TestCases/initialization-bug-no-global.cpp +++ b/compiler-rt/test/asan/TestCases/initialization-bug-no-global.cpp @@ -9,6 +9,9 @@ // Fails on some Darwin bots, probably iOS. // XFAIL: ios +// Strict init order checking is not supported on AIX +// UNSUPPORTED: target={{.*aix.*}} + #include extern int y; diff --git a/compiler-rt/test/builtins/Unit/arm/aeabi_unaligned_access_test.c b/compiler-rt/test/builtins/Unit/arm/aeabi_unaligned_access_test.c new file mode 100644 index 0000000000000..a947e097b9c03 --- /dev/null +++ b/compiler-rt/test/builtins/Unit/arm/aeabi_unaligned_access_test.c @@ -0,0 +1,86 @@ +// REQUIRES: arm-target-arch || armv6m-target-arch +// RUN: %clang_builtins %s %librt -o %t && %run %t + +#include +#include +#include + +extern int __aeabi_uread4(void *); +extern int __aeabi_uwrite4(int, void *); +extern long long __aeabi_uread8(void *); +extern long long __aeabi_uwrite8(long long, void *); + +int test_unaligned(void) { + long long target8; + int target4; + const char source[] = "abcdefghijklmno"; + static char dest1[_Countof(source)], dest2[_Countof(source)]; + int i, j; + + for (i = 0; i < 7; i++) { + memcpy(&target8, source + i, 8); + if (__aeabi_uread8(source + i) != target8) { + printf("error in __aeabi_uread8 => output = %llx, expected %llx\n", + __aeabi_uread8(source + i), target8); + return 1; + } + + memcpy(dest1, source, _Countof(source)); + memcpy(dest2, source, _Countof(source)); + target8 = 0x4142434445464748ULL; + if (__aeabi_uwrite8(target8, dest1 + i) != target8) { + printf("error in __aeabi_uwrite8 => output = %llx, expected %llx\n", + __aeabi_uwrite8(target8, dest1 + i), target8); + return 1; + } + memcpy(dest2 + i, &target8, 8); + if (memcmp(dest1, dest2, _Countof(source)) != 0) { + int pos = -1; + printf("error in __aeabi_uwrite8: memcmp failed: buffers differ!\n"); + for (int j = 0; j < 8; ++j) { + if (dest1[j] != dest2[j]) { + pos = j; + break; + } + } + printf("error: 8-byte write mismatch at offset %d\n", pos); + return 1; + } + + memcpy(&target4, source + i, 4); + if (__aeabi_uread4(source + i) != target4) { + printf("error in __aeabi_uread4 => output = %x, expected %x\n", + __aeabi_uread4(source + i), target4); + return 1; + } + + memcpy(dest1, source, _Countof(source)); + memcpy(dest2, source, _Countof(source)); + target4 = 0x414243444; + if (__aeabi_uwrite4(target4, dest1 + i) != target4) { + printf("error in __aeabi_uwrite4 => output = %x, expected %x\n", + __aeabi_uwrite4(target4, dest1 + i), target4); + return 1; + } + memcpy(dest2 + i, &target4, 4); + if (memcmp(dest1, dest2, _Countof(source)) != 0) { + int pos = -1; + printf("error in __aeabi_uwrite4: memcmp failed: buffers differ!\n"); + for (int j = 0; j < 4; ++j) { + if (dest1[j] != dest2[j]) { + pos = j; + break; + } + } + printf("error: 4-byte write mismatch at offset %d\n", pos); + return 1; + } + } + return 0; +} + +int main() { + if (test_unaligned()) + return 1; + return 0; +} diff --git a/compiler-rt/test/builtins/Unit/ppc/aix_ifunc.c b/compiler-rt/test/builtins/Unit/ppc/aix_ifunc.c new file mode 100644 index 0000000000000..ec8fd79679ffa --- /dev/null +++ b/compiler-rt/test/builtins/Unit/ppc/aix_ifunc.c @@ -0,0 +1,23 @@ +// We created a constructor function in compiler-rt/lib/builtins/ppc/init_ifuncs.c +// that reads an array contained in a certain named section of the object file. +// The compiler generates extra globals (one per ifunc) in that section. +// This test is to make sure the section name in the builtins library and the +// compiler match by checking the distance between the start and end of the +// section is "2*sizeof(void*)" because there's one ifunc in the entire program. +// +// REQUIRES: target={{.*aix.*}} +// RUN: %clang_builtins %s %librt -fno-integrated-as -o a.out +// RUN: llvm-nm -Xany --numeric-sort a.out | \ +// RUN: FileCheck %s %if target-is-powerpc64 %{ --check-prefix=CHECK64 %} \ +// RUN: %else %{ --check-prefix=CHECK %} + +// CHECK: [[#%x,ADDR:]] W __start___ifunc_sec +// CHECK: [[#ADDR+8]] W __stop___ifunc_sec +// CHECK64: [[#%x,ADDR:]] W __start___ifunc_sec +// CHECK64: [[#ADDR+16]] W __stop___ifunc_sec + +static int my_foo() { return 5; } +static void *foo_resolver() { return &my_foo; }; + +__attribute__((ifunc("foo_resolver"))) int foo(); +int main() { return foo(); } diff --git a/compiler-rt/test/cfi/CMakeLists.txt b/compiler-rt/test/cfi/CMakeLists.txt index a02573dfeb1ea..5e1c9253a1d17 100644 --- a/compiler-rt/test/cfi/CMakeLists.txt +++ b/compiler-rt/test/cfi/CMakeLists.txt @@ -1,6 +1,6 @@ set(CFI_TESTSUITES) -macro (add_cfi_test_suites lld thinlto) +macro (add_cfi_test_suites lld thinlto traploop) set(suffix) if (${lld}) set(suffix ${suffix}-lld) @@ -8,10 +8,14 @@ macro (add_cfi_test_suites lld thinlto) if (${thinlto}) set(suffix ${suffix}-thinlto) endif() + if (${traploop}) + set(suffix ${suffix}-traploop) + endif() set(suffix ${suffix}-${CFI_TEST_TARGET_ARCH}) set(CFI_TEST_USE_LLD ${lld}) set(CFI_TEST_USE_THINLTO ${thinlto}) + set(CFI_TEST_USE_TRAP_LOOP ${traploop}) set(CFI_LIT_TEST_MODE Standalone) set(CFI_TEST_CONFIG_SUFFIX -standalone${suffix}) @@ -42,14 +46,18 @@ foreach(arch ${CFI_TEST_ARCH}) # FIXME: enable ThinLTO tests after fixing http://llvm.org/pr32741 add_cfi_test_suites(False False False) elseif(WIN32) - add_cfi_test_suites(True False) - add_cfi_test_suites(True True) + add_cfi_test_suites(True False False) + add_cfi_test_suites(True True False) else() - add_cfi_test_suites(False False) - add_cfi_test_suites(False True) + add_cfi_test_suites(False False False) + add_cfi_test_suites(False True False) if (COMPILER_RT_HAS_LLD) - add_cfi_test_suites(True False) - add_cfi_test_suites(True True) + add_cfi_test_suites(True False False) + add_cfi_test_suites(True True False) + if (LINUX AND ${arch} MATCHES "x86_64|i386") + add_cfi_test_suites(True False True) + add_cfi_test_suites(True True True) + endif() endif() endif() endforeach() diff --git a/compiler-rt/test/cfi/lit.cfg.py b/compiler-rt/test/cfi/lit.cfg.py index f9afc6bc0234f..c879d7f46e6be 100644 --- a/compiler-rt/test/cfi/lit.cfg.py +++ b/compiler-rt/test/cfi/lit.cfg.py @@ -37,8 +37,18 @@ def build_invocation(compile_flags): dso = "-fsanitize-cfi-cross-dso -fvisibility=default " if config.android: dso += "-include " + config.test_source_root + "/cross-dso/util/cfi_stubs.h " - config.substitutions.append((r"%clang_cfi ", clang_cfi + non_dso)) - config.substitutions.append((r"%clangxx_cfi ", clang_cfi + cxx + non_dso)) + maybe_trap_loop = "" + if config.use_trap_loop: + maybe_trap_loop = ( + "-fsanitize-trap-loop " + + "-include " + + config.test_source_root + + "/trap_loop_signal_handler.inc " + ) + config.substitutions.append((r"%clang_cfi ", clang_cfi + non_dso + maybe_trap_loop)) + config.substitutions.append( + (r"%clangxx_cfi ", clang_cfi + cxx + non_dso + maybe_trap_loop) + ) config.substitutions.append((r"%clang_cfi_diag ", clang_cfi + non_dso + diag)) config.substitutions.append( (r"%clangxx_cfi_diag ", clang_cfi + cxx + non_dso + diag) diff --git a/compiler-rt/test/cfi/lit.site.cfg.py.in b/compiler-rt/test/cfi/lit.site.cfg.py.in index 9218a578b07e7..8179d0f0cc32e 100644 --- a/compiler-rt/test/cfi/lit.site.cfg.py.in +++ b/compiler-rt/test/cfi/lit.site.cfg.py.in @@ -7,6 +7,7 @@ config.target_cflags = "@CFI_TEST_TARGET_CFLAGS@" config.use_lld = @CFI_TEST_USE_LLD@ config.use_lto = True # CFI *requires* LTO. config.use_thinlto = @CFI_TEST_USE_THINLTO@ +config.use_trap_loop = @CFI_TEST_USE_TRAP_LOOP@ lit_config.load_config(config, "@COMPILER_RT_BINARY_DIR@/test/lit.common.configured") lit_config.load_config(config, "@CMAKE_CURRENT_SOURCE_DIR@/lit.cfg.py") diff --git a/compiler-rt/test/cfi/trap_loop_signal_handler.inc b/compiler-rt/test/cfi/trap_loop_signal_handler.inc new file mode 100644 index 0000000000000..fd50d3d3bbd49 --- /dev/null +++ b/compiler-rt/test/cfi/trap_loop_signal_handler.inc @@ -0,0 +1,5 @@ +#include + +static __attribute__((constructor)) void install_trap_loop_detection() { + __ubsan_install_trap_loop_detection(); +} diff --git a/compiler-rt/test/profile/AIX/ifunc.c b/compiler-rt/test/profile/AIX/ifunc.c new file mode 100644 index 0000000000000..8f1cf7f98988d --- /dev/null +++ b/compiler-rt/test/profile/AIX/ifunc.c @@ -0,0 +1,15 @@ +// RUN: %clang_pgogen %s -fno-integrated-as -o %t.out && %t.out + +// candidates +__attribute__((visibility("hidden"))) int my_foo() { return 4; } +static int my_foo2() { return 5; } + +// resolver +extern int x; +static void *foo_resolver() { return x ? &my_foo : &my_foo2; }; + +// ifunc +__attribute__((ifunc("foo_resolver"))) int foo(); + +int x = 1; +int main() { return foo() - 4; } diff --git a/compiler-rt/test/ubsan/TestCases/Misc/Posix/static-link.cpp b/compiler-rt/test/ubsan/TestCases/Misc/Posix/static-link.cpp index 081eec049e3fc..daa76b7322669 100644 --- a/compiler-rt/test/ubsan/TestCases/Misc/Posix/static-link.cpp +++ b/compiler-rt/test/ubsan/TestCases/Misc/Posix/static-link.cpp @@ -6,7 +6,7 @@ // UNSUPPORTED: i386-target-arch, internal_symbolizer // Does not link. -// UNSUPPORTED: darwin +// UNSUPPORTED: darwin,target={{.*solaris.*}} #include #include diff --git a/flang-rt/CMakeLists.txt b/flang-rt/CMakeLists.txt index 174974884fd41..eac795e4e3894 100644 --- a/flang-rt/CMakeLists.txt +++ b/flang-rt/CMakeLists.txt @@ -202,7 +202,7 @@ elseif (FLANG_RT_EXPERIMENTAL_OFFLOAD_SUPPORT STREQUAL "OpenMP") "gfx908;gfx90a;gfx90c;gfx940;gfx1010;gfx1030" "gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036" "gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151" - "gfx1152;gfx1153") + "gfx1152;gfx1153;gfx1170") set(all_nvptx_architectures "sm_35;sm_37;sm_50;sm_52;sm_53;sm_60;sm_61;sm_62" "sm_70;sm_72;sm_75;sm_80;sm_86;sm_89;sm_90") diff --git a/flang-rt/lib/runtime/descriptor-io.cpp b/flang-rt/lib/runtime/descriptor-io.cpp index e599e624fe02e..6e5752ec22f30 100644 --- a/flang-rt/lib/runtime/descriptor-io.cpp +++ b/flang-rt/lib/runtime/descriptor-io.cpp @@ -165,9 +165,9 @@ static RT_API_ATTRS common::optional DefinedFormattedIo( external->PopChildIo(child); if (!actualExternal) { // Close unit created for internal I/O above. - auto *closing{external->LookUpForClose(external->unitNumber())}; + auto *closing{external->LookUpForClose(external->unitNumber(), handler)}; RUNTIME_CHECK(handler, external == closing); - external->DestroyClosed(); + external->DestroyClosed(handler); } if (startPos) { io.GotChar(io.InquirePos() - *startPos); diff --git a/flang-rt/lib/runtime/extensions.cpp b/flang-rt/lib/runtime/extensions.cpp index 978cc526d707a..b06b9eabe2c60 100644 --- a/flang-rt/lib/runtime/extensions.cpp +++ b/flang-rt/lib/runtime/extensions.cpp @@ -478,8 +478,9 @@ void RTNAME(ShowDescriptor)(const Fortran::runtime::Descriptor *descr) { namespace io { std::int32_t RTNAME(Fseek)(int unitNumber, std::int64_t zeroBasedPos, int whence, const char *sourceFileName, int lineNumber) { - if (ExternalFileUnit * unit{ExternalFileUnit::LookUp(unitNumber)}) { - Terminator terminator{sourceFileName, lineNumber}; + Terminator terminator{sourceFileName, lineNumber}; + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUp(unitNumber, terminator)}) { IoErrorHandler handler{terminator}; if (unit->Fseek( zeroBasedPos, static_cast(whence), handler)) { @@ -493,7 +494,9 @@ std::int32_t RTNAME(Fseek)(int unitNumber, std::int64_t zeroBasedPos, } std::int64_t RTNAME(Ftell)(int unitNumber) { - if (ExternalFileUnit * unit{ExternalFileUnit::LookUp(unitNumber)}) { + Terminator terminator{__FILE__, __LINE__}; + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUp(unitNumber, terminator)}) { return unit->InquirePos() - 1; // zero-based result } else { return -1; @@ -501,7 +504,9 @@ std::int64_t RTNAME(Ftell)(int unitNumber) { } std::int32_t FORTRAN_PROCEDURE_NAME(fnum)(const int &unitNumber) { - if (ExternalFileUnit * unit{ExternalFileUnit::LookUp(unitNumber)}) { + Terminator terminator{__FILE__, __LINE__}; + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUp(unitNumber, terminator)}) { return unit->fd(); } else { return -1; @@ -509,7 +514,5 @@ std::int32_t FORTRAN_PROCEDURE_NAME(fnum)(const int &unitNumber) { } } // namespace io - } // extern "C" - } // namespace Fortran::runtime diff --git a/flang-rt/lib/runtime/external-unit.cpp b/flang-rt/lib/runtime/external-unit.cpp index 6a609a22d093a..0c08691673823 100644 --- a/flang-rt/lib/runtime/external-unit.cpp +++ b/flang-rt/lib/runtime/external-unit.cpp @@ -47,13 +47,13 @@ void FlushOutputOnCrash(const Terminator &terminator) { } } -ExternalFileUnit *ExternalFileUnit::LookUp(int unit) { - return GetUnitMap().LookUp(unit); +ExternalFileUnit *ExternalFileUnit::LookUp(int unit, Terminator &terminator) { + return GetUnitMap(terminator).LookUp(unit); } ExternalFileUnit *ExternalFileUnit::LookUpOrCreate( int unit, const Terminator &terminator, bool &wasExtant) { - return GetUnitMap().LookUpOrCreate(unit, terminator, wasExtant); + return GetUnitMap(terminator).LookUpOrCreate(unit, terminator, wasExtant); } ExternalFileUnit *ExternalFileUnit::LookUpOrCreateAnonymous(int unit, @@ -63,7 +63,8 @@ ExternalFileUnit *ExternalFileUnit::LookUpOrCreateAnonymous(int unit, // not just created in the unitMap. CriticalSection critical{createOpenLock}; bool exists{false}; - ExternalFileUnit *result{GetUnitMap().LookUpOrCreate(unit, handler, exists)}; + ExternalFileUnit *result{ + GetUnitMap(handler).LookUpOrCreate(unit, handler, exists)}; if (result && !exists) { common::optional action; if (dir == Direction::Output) { @@ -73,8 +74,9 @@ ExternalFileUnit *ExternalFileUnit::LookUpOrCreateAnonymous(int unit, dir == Direction::Input ? OpenStatus::Unknown : OpenStatus::Replace, action, Position::Rewind, Convert::Unknown, handler)) { // fort.N isn't a writable file - if (ExternalFileUnit * closed{LookUpForClose(result->unitNumber())}) { - closed->DestroyClosed(); + if (ExternalFileUnit * + closed{LookUpForClose(result->unitNumber(), handler)}) { + closed->DestroyClosed(handler); } result = nullptr; } else { @@ -85,26 +87,27 @@ ExternalFileUnit *ExternalFileUnit::LookUpOrCreateAnonymous(int unit, } ExternalFileUnit *ExternalFileUnit::LookUp( - const char *path, std::size_t pathLen) { - return GetUnitMap().LookUp(path, pathLen); + const char *path, std::size_t pathLen, Terminator &terminator) { + return GetUnitMap(terminator).LookUp(path, pathLen); } ExternalFileUnit &ExternalFileUnit::CreateNew( int unit, const Terminator &terminator) { bool wasExtant{false}; ExternalFileUnit *result{ - GetUnitMap().LookUpOrCreate(unit, terminator, wasExtant)}; + GetUnitMap(terminator).LookUpOrCreate(unit, terminator, wasExtant)}; RUNTIME_CHECK(terminator, result && !wasExtant); return *result; } -ExternalFileUnit *ExternalFileUnit::LookUpForClose(int unit) { - return GetUnitMap().LookUpForClose(unit); +ExternalFileUnit *ExternalFileUnit::LookUpForClose( + int unit, Terminator &terminator) { + return GetUnitMap(terminator).LookUpForClose(unit); } ExternalFileUnit &ExternalFileUnit::NewUnit( const Terminator &terminator, bool forChildIo) { - ExternalFileUnit &unit{GetUnitMap().NewUnit(terminator)}; + ExternalFileUnit &unit{GetUnitMap(terminator).NewUnit(terminator)}; unit.createdForInternalChildIo_ = forChildIo; return unit; } @@ -143,7 +146,7 @@ bool ExternalFileUnit::OpenUnit(common::optional status, } if (newPath.get() && newPathLength > 0) { if (const auto *already{ - GetUnitMap().LookUp(newPath.get(), newPathLength)}) { + GetUnitMap(handler).LookUp(newPath.get(), newPathLength)}) { handler.SignalError(IostatOpenAlreadyConnected, "OPEN(UNIT=%d,FILE='%.*s'): file is already connected to unit %d", unitNumber_, static_cast(newPathLength), newPath.get(), @@ -213,8 +216,8 @@ void ExternalFileUnit::CloseUnit(CloseStatus status, IoErrorHandler &handler) { Close(status, handler); } -void ExternalFileUnit::DestroyClosed() { - GetUnitMap().DestroyClosed(*this); // destroys *this +void ExternalFileUnit::DestroyClosed(Terminator &terminator) { + GetUnitMap(terminator).DestroyClosed(*this); // destroys *this } Iostat ExternalFileUnit::SetDirection(Direction direction) { @@ -242,8 +245,7 @@ Iostat ExternalFileUnit::SetDirection(Direction direction) { } } -UnitMap &ExternalFileUnit::CreateUnitMap() { - Terminator terminator{__FILE__, __LINE__}; +UnitMap &ExternalFileUnit::CreateUnitMap(const Terminator &terminator) { IoErrorHandler handler{terminator}; UnitMap &newUnitMap{*New{terminator}().release()}; @@ -285,7 +287,7 @@ static void CloseAllExternalUnits() { ExternalFileUnit::CloseAll(handler); } -UnitMap &ExternalFileUnit::GetUnitMap() { +UnitMap &ExternalFileUnit::GetUnitMap(const Terminator &terminator) { if (unitMap) { return *unitMap; } @@ -294,7 +296,7 @@ UnitMap &ExternalFileUnit::GetUnitMap() { if (unitMap) { return *unitMap; } - unitMap = &CreateUnitMap(); + unitMap = &CreateUnitMap(terminator); } std::atexit(CloseAllExternalUnits); return *unitMap; diff --git a/flang-rt/lib/runtime/io-api.cpp b/flang-rt/lib/runtime/io-api.cpp index da324f392e008..b7ff74dd0e383 100644 --- a/flang-rt/lib/runtime/io-api.cpp +++ b/flang-rt/lib/runtime/io-api.cpp @@ -308,7 +308,8 @@ Cookie IODEF(BeginOpenNewUnit)( // OPEN(NEWUNIT=j) Cookie IODEF(BeginWait)(ExternalUnit unitNumber, AsynchronousId id, const char *sourceFile, int sourceLine) { Terminator terminator{sourceFile, sourceLine}; - if (ExternalFileUnit * unit{ExternalFileUnit::LookUp(unitNumber)}) { + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUp(unitNumber, terminator)}) { if (unit->Wait(id)) { return &unit->BeginIoStatement(terminator, *unit, ExternalMiscIoStatementState::Wait, sourceFile, sourceLine); @@ -329,14 +330,16 @@ Cookie IODEF(BeginWaitAll)( Cookie IODEF(BeginClose)( ExternalUnit unitNumber, const char *sourceFile, int sourceLine) { Terminator terminator{sourceFile, sourceLine}; - if (ExternalFileUnit * unit{ExternalFileUnit::LookUp(unitNumber)}) { + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUp(unitNumber, terminator)}) { if (ChildIo * child{unit->GetChildIo()}) { return &child->BeginIoStatement( IostatBadOpOnChildUnit, nullptr /* no unit */, sourceFile, sourceLine); } } - if (ExternalFileUnit * unit{ExternalFileUnit::LookUpForClose(unitNumber)}) { + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUpForClose(unitNumber, terminator)}) { return &unit->BeginIoStatement( terminator, *unit, sourceFile, sourceLine); } else { @@ -348,7 +351,8 @@ Cookie IODEF(BeginClose)( Cookie IODEF(BeginFlush)( ExternalUnit unitNumber, const char *sourceFile, int sourceLine) { Terminator terminator{sourceFile, sourceLine}; - if (ExternalFileUnit * unit{ExternalFileUnit::LookUp(unitNumber)}) { + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUp(unitNumber, terminator)}) { if (ChildIo * child{unit->GetChildIo()}) { return &child->BeginIoStatement( *unit, ExternalMiscIoStatementState::Flush, sourceFile, sourceLine); @@ -366,7 +370,8 @@ Cookie IODEF(BeginFlush)( Cookie IODEF(BeginBackspace)( ExternalUnit unitNumber, const char *sourceFile, int sourceLine) { Terminator terminator{sourceFile, sourceLine}; - if (ExternalFileUnit * unit{ExternalFileUnit::LookUp(unitNumber)}) { + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUp(unitNumber, terminator)}) { if (ChildIo * child{unit->GetChildIo()}) { return &child->BeginIoStatement( IostatBadOpOnChildUnit, nullptr /* no unit */, sourceFile, @@ -424,7 +429,8 @@ Cookie IODEF(BeginRewind)( Cookie IODEF(BeginInquireUnit)( ExternalUnit unitNumber, const char *sourceFile, int sourceLine) { Terminator terminator{sourceFile, sourceLine}; - if (ExternalFileUnit * unit{ExternalFileUnit::LookUp(unitNumber)}) { + if (ExternalFileUnit * + unit{ExternalFileUnit::LookUp(unitNumber, terminator)}) { if (ChildIo * child{unit->GetChildIo()}) { return &child->BeginIoStatement( *unit, sourceFile, sourceLine); @@ -447,8 +453,8 @@ Cookie IODEF(BeginInquireFile)(const char *path, std::size_t pathLength, auto trimmed{SaveDefaultCharacter( path, TrimTrailingSpaces(path, pathLength), terminator)}; if (ExternalFileUnit * - unit{ExternalFileUnit::LookUp( - trimmed.get(), Fortran::runtime::strlen(trimmed.get()))}) { + unit{ExternalFileUnit::LookUp(trimmed.get(), + Fortran::runtime::strlen(trimmed.get()), terminator)}) { // INQUIRE(FILE=) to a connected unit if (ChildIo * child{unit->GetChildIo()}) { return &child->BeginIoStatement( diff --git a/flang-rt/lib/runtime/io-stmt.cpp b/flang-rt/lib/runtime/io-stmt.cpp index 97ee59da12a57..6d3b01af6c792 100644 --- a/flang-rt/lib/runtime/io-stmt.cpp +++ b/flang-rt/lib/runtime/io-stmt.cpp @@ -264,9 +264,9 @@ int ExternalIoStatementBase::EndIoStatement() { unit_.EndIoStatement(); // annihilates *this in unit_.u_ if (destroy_) { if (ExternalFileUnit * - toClose{ExternalFileUnit::LookUpForClose(unitNumber)}) { + toClose{ExternalFileUnit::LookUpForClose(unitNumber, *this)}) { toClose->Close(CloseStatus::Delete, *this); - toClose->DestroyClosed(); + toClose->DestroyClosed(*this); } } #else @@ -377,7 +377,7 @@ int CloseStatementState::EndIoStatement() { CompleteOperation(); int result{ExternalIoStatementBase::EndIoStatement()}; unit().CloseUnit(status_, *this); - unit().DestroyClosed(); + unit().DestroyClosed(*this); return result; } diff --git a/flang-rt/lib/runtime/pseudo-unit.cpp b/flang-rt/lib/runtime/pseudo-unit.cpp index 3c9a9ae261332..4242f685134ed 100644 --- a/flang-rt/lib/runtime/pseudo-unit.cpp +++ b/flang-rt/lib/runtime/pseudo-unit.cpp @@ -25,13 +25,13 @@ namespace Fortran::runtime::io { void FlushOutputOnCrash(const Terminator &) {} -ExternalFileUnit *ExternalFileUnit::LookUp(int) { - Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); +ExternalFileUnit *ExternalFileUnit::LookUp(int, Terminator &terminator) { + terminator.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } ExternalFileUnit *ExternalFileUnit::LookUpOrCreate( - int, const Terminator &, bool &) { - Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); + int, const Terminator &terminator, bool &) { + terminator.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } ExternalFileUnit *ExternalFileUnit::LookUpOrCreateAnonymous(int unit, @@ -44,20 +44,24 @@ ExternalFileUnit *ExternalFileUnit::LookUpOrCreateAnonymous(int unit, return New{handler}(unit).release(); } -ExternalFileUnit *ExternalFileUnit::LookUp(const char *, std::size_t) { - Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); +ExternalFileUnit *ExternalFileUnit::LookUp( + const char *, std::size_t, Terminator &terminator) { + terminator.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -ExternalFileUnit &ExternalFileUnit::CreateNew(int, const Terminator &) { - Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); +ExternalFileUnit &ExternalFileUnit::CreateNew( + int, const Terminator &terminator) { + terminator.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -ExternalFileUnit *ExternalFileUnit::LookUpForClose(int) { - Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); +ExternalFileUnit *ExternalFileUnit::LookUpForClose( + int, Terminator &terminator) { + terminator.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -ExternalFileUnit &ExternalFileUnit::NewUnit(const Terminator &, bool) { - Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); +ExternalFileUnit &ExternalFileUnit::NewUnit( + const Terminator &terminator, bool) { + terminator.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } bool ExternalFileUnit::OpenUnit(common::optional status, @@ -76,8 +80,8 @@ void ExternalFileUnit::CloseUnit(CloseStatus, IoErrorHandler &handler) { handler.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -void ExternalFileUnit::DestroyClosed() { - Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); +void ExternalFileUnit::DestroyClosed(Terminator &terminator) { + terminator.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } Iostat ExternalFileUnit::SetDirection(Direction direction) { diff --git a/flang-rt/lib/runtime/unit.h b/flang-rt/lib/runtime/unit.h index bd4fc81c2f306..dc3296371e0e8 100644 --- a/flang-rt/lib/runtime/unit.h +++ b/flang-rt/lib/runtime/unit.h @@ -128,15 +128,15 @@ class ExternalFileUnit : public ConnectionState, return createdForInternalChildIo_; } - static RT_API_ATTRS ExternalFileUnit *LookUp(int unit); + static RT_API_ATTRS ExternalFileUnit *LookUp(int unit, Terminator &); static RT_API_ATTRS ExternalFileUnit *LookUpOrCreate( int unit, const Terminator &, bool &wasExtant); static RT_API_ATTRS ExternalFileUnit *LookUpOrCreateAnonymous(int unit, Direction, common::optional isUnformatted, IoErrorHandler &); static RT_API_ATTRS ExternalFileUnit *LookUp( - const char *path, std::size_t pathLen); + const char *path, std::size_t pathLen, Terminator &); static RT_API_ATTRS ExternalFileUnit &CreateNew(int unit, const Terminator &); - static RT_API_ATTRS ExternalFileUnit *LookUpForClose(int unit); + static RT_API_ATTRS ExternalFileUnit *LookUpForClose(int unit, Terminator &); static RT_API_ATTRS ExternalFileUnit &NewUnit( const Terminator &, bool forChildIo); static RT_API_ATTRS void CloseAll(IoErrorHandler &); @@ -149,7 +149,7 @@ class ExternalFileUnit : public ConnectionState, RT_API_ATTRS bool OpenAnonymousUnit(common::optional, common::optional, Position, Convert, IoErrorHandler &); RT_API_ATTRS void CloseUnit(CloseStatus, IoErrorHandler &); - RT_API_ATTRS void DestroyClosed(); + RT_API_ATTRS void DestroyClosed(Terminator &); RT_API_ATTRS Iostat SetDirection(Direction); @@ -207,8 +207,8 @@ class ExternalFileUnit : public ConnectionState, } private: - static RT_API_ATTRS UnitMap &CreateUnitMap(); - static RT_API_ATTRS UnitMap &GetUnitMap(); + static RT_API_ATTRS UnitMap &CreateUnitMap(const Terminator &); + static RT_API_ATTRS UnitMap &GetUnitMap(const Terminator &); RT_API_ATTRS const char *FrameNextInput(IoErrorHandler &, std::size_t); RT_API_ATTRS void SetPosition(std::int64_t zeroBasedPos); RT_API_ATTRS void Sought(std::int64_t zeroBasedPos); diff --git a/flang/docs/Extensions.md b/flang/docs/Extensions.md index 493bb10af6f85..79e6213f7f3c9 100644 --- a/flang/docs/Extensions.md +++ b/flang/docs/Extensions.md @@ -481,6 +481,8 @@ end * A data object can be initialized multiple times by `DATA` statements and default component initialization, but only when all initializations are to the same value. Distinct initializations remain errors. +* A pointer component that has no default initialization or explicit value + in a structure constructor is defaulted to `NULL()`. ### Extensions supported when enabled by options diff --git a/flang/include/flang/Evaluate/check-expression.h b/flang/include/flang/Evaluate/check-expression.h index 41a98a4bea6a2..c837a7d72e8b1 100644 --- a/flang/include/flang/Evaluate/check-expression.h +++ b/flang/include/flang/Evaluate/check-expression.h @@ -180,5 +180,14 @@ std::optional CheckStatementFunction( std::optional ActualArgNeedsCopy(const ActualArgument *, const characteristics::DummyArgument *, FoldingContext &, bool forCopyOut); +// Scan expressions and note uses of values of symbols. +semantics::UnorderedSymbolSet CollectUsedSymbolValues( + semantics::SemanticsContext &, const Expr &, + bool isDefinition = false); +semantics::UnorderedSymbolSet CollectUsedSymbolValues( + semantics::SemanticsContext &, const ProcedureRef &); +semantics::UnorderedSymbolSet CollectUsedSymbolValues( + semantics::SemanticsContext &, const Assignment &); + } // namespace Fortran::evaluate #endif diff --git a/flang/include/flang/Evaluate/tools.h b/flang/include/flang/Evaluate/tools.h index 6a424f2cbb04e..0776a0afb4d92 100644 --- a/flang/include/flang/Evaluate/tools.h +++ b/flang/include/flang/Evaluate/tools.h @@ -1638,6 +1638,9 @@ std::optional GetDummyArgumentNumber(const Symbol *); const Symbol *FindAncestorModuleProcedure(const Symbol *symInSubmodule); +// Given a Cray pointee symbol, returns the related Cray pointer symbol. +const Symbol &GetCrayPointer(const Symbol &crayPointee); + } // namespace Fortran::semantics #endif // FORTRAN_EVALUATE_TOOLS_H_ diff --git a/flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h b/flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h new file mode 100644 index 0000000000000..0a9ff13e30525 --- /dev/null +++ b/flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h @@ -0,0 +1,119 @@ +//===- ArraySectionAnalyzer.h - Analyze array sections --------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_OPTIMIZER_ANALYSIS_ARRAYSECTIONANALYZER_H +#define FORTRAN_OPTIMIZER_ANALYSIS_ARRAYSECTIONANALYZER_H + +#include "mlir/IR/Operation.h" +#include "mlir/IR/Value.h" + +namespace mlir { +class Operation; +class Value; +} // namespace mlir + +namespace hlfir { +class ElementalOpInterface; +class DesignateOp; +} // namespace hlfir + +namespace fir { +class ArraySectionAnalyzer { +public: + // The result of the analyzis is one of the values below. + enum class SlicesOverlapKind { + // Slices overlap is unknown. + Unknown, + // Slices are definitely identical. + DefinitelyIdentical, + // Slices are definitely disjoint. + DefinitelyDisjoint, + // Slices may be either disjoint or identical, + // i.e. there is definitely no partial overlap. + EitherIdenticalOrDisjoint + }; + + // Analyzes two hlfir.designate results and returns the overlap kind. + // The callers may use this method when the alias analysis reports + // an alias of some kind, so that we can run Fortran specific analysis + // on the array slices to see if they are identical or disjoint. + // Note that the alias analysis are not able to give such an answer + // about the references. + static SlicesOverlapKind analyze(mlir::Value ref1, mlir::Value ref2); + + static bool isDesignatingArrayInOrder(hlfir::DesignateOp designate, + hlfir::ElementalOpInterface elemental); + +private: + struct SectionDesc { + // An array section is described by tuple. + // If the designator's subscript is not a triple, then + // the section descriptor is constructed as . + mlir::Value lb, ub, stride; + + SectionDesc(mlir::Value lb, mlir::Value ub, mlir::Value stride); + + // Normalize the section descriptor: + // 1. If UB is nullptr, then it is set to LB. + // 2. If LB==UB, then stride does not matter, + // so it is reset to nullptr. + // 3. If STRIDE==1, then it is reset to nullptr. + void normalize(); + + bool operator==(const SectionDesc &other) const; + }; + + // Given an operand_iterator over the indices operands, + // read the subscript values and return them as SectionDesc + // updating the iterator. If isTriplet is true, + // the subscript is a triplet, and the result is . + // Otherwise, the subscript is a scalar index, and the result + // is . + static SectionDesc readSectionDesc(mlir::Operation::operand_iterator &it, + bool isTriplet); + + // Return the ordered lower and upper bounds of the section. + // If stride is known to be non-negative, then the ordered + // bounds match the of the descriptor. + // If stride is known to be negative, then the ordered + // bounds are of the descriptor. + // If stride is unknown, we cannot deduce any order, + // so the result is + static std::pair + getOrderedBounds(const SectionDesc &desc); + + // Given two array sections and + // , return true only if the sections + // are known to be disjoint. + // + // For example, for any positive constant C: + // X:Y does not overlap with (Y+C):Z + // X:Y does not overlap with Z:(X-C) + static bool areDisjointSections(const SectionDesc &desc1, + const SectionDesc &desc2); + + // Given two array sections and + // , return true only if the sections + // are known to be identical. + // + // For example: + // + // + // + // These sections are identical, from the point of which array + // elements are being addresses, even though the shape + // of the array slices might be different. + static bool areIdenticalSections(const SectionDesc &desc1, + const SectionDesc &desc2); + + // Return true, if v1 is known to be less than v2. + static bool isLess(mlir::Value v1, mlir::Value v2); +}; +} // namespace fir + +#endif // FORTRAN_OPTIMIZER_ANALYSIS_ARRAYSECTIONANALYZER_H diff --git a/flang/include/flang/Optimizer/Dialect/FIROps.td b/flang/include/flang/Optimizer/Dialect/FIROps.td index 30f5dcc37b0f3..02a204c9a6e26 100644 --- a/flang/include/flang/Optimizer/Dialect/FIROps.td +++ b/flang/include/flang/Optimizer/Dialect/FIROps.td @@ -1902,7 +1902,7 @@ def fir_ArrayCoorOp } def fir_CoordinateOp - : fir_Op<"coordinate_of", [NoMemoryEffect, + : fir_Op<"coordinate_of", [NoMemoryEffect, ConditionallySpeculatable, fir_FortranObjectViewOpInterface]> { let summary = "Finds the coordinate (location) of a value in memory"; @@ -1959,6 +1959,9 @@ def fir_CoordinateOp // FortranObjectViewOpInterface methods: mlir::Value getViewSource(mlir::OpResult) { return getRef(); } std::optional getViewOffset(mlir::OpResult); + + // Interface method for ConditionallySpeculatable. + mlir::Speculation::Speculatability getSpeculatability(); }]; } @@ -1992,7 +1995,7 @@ def fir_ExtractValueOp : fir_OneResultOp<"extract_value", [NoMemoryEffect]> { }]; } -def fir_FieldIndexOp : fir_OneResultOp<"field_index", [NoMemoryEffect]> { +def fir_FieldIndexOp : fir_OneResultOp<"field_index", [Pure]> { let summary = "create a field index value from a field identifier"; let description = [{ diff --git a/flang/include/flang/Optimizer/Passes/Pipelines.h b/flang/include/flang/Optimizer/Passes/Pipelines.h index 70b9341347244..1a7ff4ff3dfa2 100644 --- a/flang/include/flang/Optimizer/Passes/Pipelines.h +++ b/flang/include/flang/Optimizer/Passes/Pipelines.h @@ -105,6 +105,10 @@ void addDebugInfoPass(mlir::PassManager &pm, llvm::OptimizationLevel optLevel, llvm::StringRef inputFilename, int32_t dwarfVersion); +/// Create FIRToLLVMPassOptions from pipeline configuration. +FIRToLLVMPassOptions +getFIRToLLVMPassOptions(const MLIRToLLVMPassPipelineConfig &config); + void addFIRToLLVMPass(mlir::PassManager &pm, const MLIRToLLVMPassPipelineConfig &config); diff --git a/flang/include/flang/Optimizer/Transforms/Passes.td b/flang/include/flang/Optimizer/Transforms/Passes.td index c2d6526b558d2..090a1ce24fd8b 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.td +++ b/flang/include/flang/Optimizer/Transforms/Passes.td @@ -437,7 +437,7 @@ def FunctionAttr : Pass<"function-attr", "mlir::func::FuncOp"> { "Sets the name of the profiling function called during function " "exit">, Option<"noInfsFPMath", "no-infs-fp-math", "bool", /*default=*/"false", - "Set the no-infs-fp-math attribute on functions in the module.">, + "Set the ninf flag on instructions in the module.">, Option<"noNaNsFPMath", "no-nans-fp-math", "bool", /*default=*/"false", "Set the no-nans-fp-math attribute on functions in the module.">, Option<"approxFuncFPMath", "approx-func-fp-math", "bool", diff --git a/flang/include/flang/Semantics/expression.h b/flang/include/flang/Semantics/expression.h index 50f75b2304d95..4de20f5ea46a5 100644 --- a/flang/include/flang/Semantics/expression.h +++ b/flang/include/flang/Semantics/expression.h @@ -465,12 +465,8 @@ evaluate::Expr AnalyzeKindSelector( SemanticsContext &, common::TypeCategory, const std::optional &); -void NoteUsedSymbols(SemanticsContext &, const SomeExpr &); -void NoteUsedSymbols(SemanticsContext &, const evaluate::ProcedureRef &); -void NoteUsedSymbols(SemanticsContext &, const evaluate::Assignment &); -void NoteUsedSymbols(SemanticsContext &, const parser::TypedExpr &); -void NoteUsedSymbols(SemanticsContext &, const parser::TypedCall &); -void NoteUsedSymbols(SemanticsContext &, const parser::TypedAssignment &); +void NoteUsedSymbols( + SemanticsContext &, const SomeExpr &, bool isDefinition = false); // Semantic analysis of all expressions in a parse tree, which becomes // decorated with typed representations for top-level expressions. @@ -499,11 +495,11 @@ class ExprChecker { return false; } bool Pre(const parser::AllocateObject &x) { - AnalyzeAndNoteUses(x); + AnalyzeAndNoteUses(x, /*isDefinition=*/true); return false; } bool Pre(const parser::PointerObject &x) { - AnalyzeAndNoteUses(x); + AnalyzeAndNoteUses(x, /*isDefinition=*/true); return false; } bool Pre(const parser::DataStmtObject &); @@ -583,14 +579,23 @@ class ExprChecker { } private: - template void AnalyzeAndNoteUses(const A &x) { + template + void AnalyzeAndNoteUses(const A &x, bool isDefinition = false) { exprAnalyzer_.Analyze(x); if constexpr (parser::HasTypedExpr::value) { - NoteUsedSymbols(context_, x.typedExpr); + if (x.typedExpr && x.typedExpr->v) { + NoteUsedSymbols(context_, *x.typedExpr->v, isDefinition); + } } else if constexpr (parser::HasTypedCall::value) { - NoteUsedSymbols(context_, x.typedCall); + if (x.typedCall) { + context_.NoteUsedSymbols( + evaluate::CollectUsedSymbolValues(context_, *x.typedCall)); + } } else if constexpr (parser::HasTypedAssignment::value) { - NoteUsedSymbols(context_, x.typedAssignment); + if (x.typedAssignment && x.typedAssignment->v) { + context_.NoteUsedSymbols( + evaluate::CollectUsedSymbolValues(context_, *x.typedAssignment->v)); + } } } bool InWhereBody() const { return whereDepth_ > 0; } diff --git a/flang/include/flang/Semantics/semantics.h b/flang/include/flang/Semantics/semantics.h index 88bc23380b22d..f7a8e76879b77 100644 --- a/flang/include/flang/Semantics/semantics.h +++ b/flang/include/flang/Semantics/semantics.h @@ -332,6 +332,7 @@ class SemanticsContext { void NoteDefinedSymbol(const Symbol &); bool IsSymbolDefined(const Symbol &) const; void NoteUsedSymbol(const Symbol &); + void NoteUsedSymbols(const UnorderedSymbolSet &); bool IsSymbolUsed(const Symbol &) const; void DumpSymbols(llvm::raw_ostream &); diff --git a/flang/include/flang/Semantics/tools.h b/flang/include/flang/Semantics/tools.h index 1c3477013b559..5773e93801ed4 100644 --- a/flang/include/flang/Semantics/tools.h +++ b/flang/include/flang/Semantics/tools.h @@ -334,9 +334,6 @@ const Symbol *FindExternallyVisibleObject( // specific procedure of the same name, return it instead. const Symbol &BypassGeneric(const Symbol &); -// Given a cray pointee symbol, returns the related cray pointer symbol. -const Symbol &GetCrayPointer(const Symbol &crayPointee); - using SomeExpr = evaluate::Expr; bool ExprHasTypeCategory( diff --git a/flang/include/flang/Support/Fortran-features.h b/flang/include/flang/Support/Fortran-features.h index c705e031eff9d..fa300da48ffe1 100644 --- a/flang/include/flang/Support/Fortran-features.h +++ b/flang/include/flang/Support/Fortran-features.h @@ -56,7 +56,8 @@ ENUM_CLASS(LanguageFeature, BackslashEscapes, OldDebugLines, IgnoreIrrelevantAttributes, Unsigned, ContiguousOkForSeqAssociation, ForwardRefExplicitTypeDummy, InaccessibleDeferredOverride, CudaWarpMatchFunction, DoConcurrentOffload, TransferBOZ, Coarray, - PointerPassObject, MultipleIdenticalDATA) + PointerPassObject, MultipleIdenticalDATA, + DefaultStructConstructorNullPointer) // Portability and suspicious usage warnings ENUM_CLASS(UsageWarning, Portability, PointerToUndefinable, diff --git a/flang/include/flang/Tools/CrossToolHelpers.h b/flang/include/flang/Tools/CrossToolHelpers.h index e964882ef6dac..44fb252d2b366 100644 --- a/flang/include/flang/Tools/CrossToolHelpers.h +++ b/flang/include/flang/Tools/CrossToolHelpers.h @@ -123,7 +123,7 @@ struct MLIRToLLVMPassPipelineConfig : public FlangEPCallBacks { llvm::FramePointerKind::None; ///< Add frame pointer to functions. unsigned VScaleMin = 0; ///< SVE vector range minimum. unsigned VScaleMax = 0; ///< SVE vector range maximum. - bool NoInfsFPMath = false; ///< Set no-infs-fp-math attribute for functions. + bool NoInfsFPMath = false; ///< Set ninf flag for instructions. bool NoNaNsFPMath = false; ///< Set no-nans-fp-math attribute for functions. bool ApproxFuncFPMath = false; ///< Set afn flag for instructions. bool NoSignedZerosFPMath = diff --git a/flang/lib/Evaluate/check-expression.cpp b/flang/lib/Evaluate/check-expression.cpp index 9e63f216693a2..f18953c1b9849 100644 --- a/flang/lib/Evaluate/check-expression.cpp +++ b/flang/lib/Evaluate/check-expression.cpp @@ -1665,4 +1665,121 @@ std::optional ActualArgNeedsCopy(const ActualArgument *actual, return std::nullopt; } +// CollectUsedSymbolValues() + +class CollectUsedSymbolValuesHelper + : public SetTraverse { +public: + using Result = semantics::UnorderedSymbolSet; + using Base = SetTraverse; + explicit CollectUsedSymbolValuesHelper( + semantics::SemanticsContext &c, bool isDefinition = false) + : Base{*this}, context_{c}, isDefinition_{isDefinition} {} + using Base::operator(); + + Result operator()(const semantics::Symbol &symbol) const { + Result result; + if (!isDefinition_) { + const Symbol &root{semantics::GetAssociationRoot(symbol)}; + switch (root.owner().kind()) { + case semantics::Scope::Kind::Subprogram: + case semantics::Scope::Kind::MainProgram: + case semantics::Scope::Kind::BlockConstruct: + if ((root.has() || + IsProcedurePointer(root))) { + result.insert(root); + if (root.test(semantics::Symbol::Flag::CrayPointee)) { + result.insert(semantics::GetCrayPointer(root)); + } + } + break; + default: + break; + } + } + return result; + } + + Result operator()(const Subscript &subscript) { + auto restorer{common::ScopedSet(isDefinition_, false)}; + return (*this)(subscript.u); + } + + template Result operator()(const FunctionRef &fRef) { + return (*this)(static_cast(fRef)); + } + Result operator()(const ProcedureRef &call) { + auto restorer{common::ScopedSet(isDefinition_, false)}; + Result result{(*this)(call.proc())}; + int skipLeading{0}; + if (const auto *intrinsic{call.proc().GetSpecificIntrinsic()}) { + if (context_.intrinsics().GetIntrinsicClass(intrinsic->name) == + IntrinsicClass::inquiryFunction) { + skipLeading = 1; // first argument to inquiry doesn't count as a use + } + } + for (const auto &maybeArg : call.arguments()) { + if (skipLeading) { + --skipLeading; + } else if (maybeArg) { + if (const auto *expr{maybeArg->UnwrapExpr()}) { + if (IsBindingUsedAsProcedure(*expr)) { + // Ignore procedure bindings being used as actual procedures + // (a local extension). + } else { + result = Combine(std::move(result), (*this)(*expr)); + } + } + } + } + return result; + } + + Result operator()(const Assignment &assignment) { + auto restorer{common::ScopedSet(isDefinition_, true)}; + Result result{(*this)(assignment.lhs)}; + if (IsBindingUsedAsProcedure(assignment.rhs)) { + // Don't look at the RHS, we're just using its binding (extension). + } else { + auto restorer{common::ScopedSet(isDefinition_, false)}; + result = Combine(std::move(result), (*this)(assignment.rhs)); + } + return result; + } + + Result operator()(const TypeParamInquiry &) const { + return {}; // doesn't count as a use + } + Result operator()(const DescriptorInquiry &) const { + return {}; // doesn't count as a use + } + +private: + static bool IsBindingUsedAsProcedure(const Expr &expr) { + if (const auto *pd{std::get_if(&expr.u)}) { + if (const Symbol *symbol{pd->GetSymbol()}) { + return symbol->has(); + } + } + return false; + } + + semantics::SemanticsContext &context_; + bool isDefinition_{false}; +}; + +semantics::UnorderedSymbolSet CollectUsedSymbolValues( + semantics::SemanticsContext &context, const Expr &expr, + bool isDefinition) { + return CollectUsedSymbolValuesHelper{context, isDefinition}(expr); +} +semantics::UnorderedSymbolSet CollectUsedSymbolValues( + semantics::SemanticsContext &context, const ProcedureRef &call) { + return CollectUsedSymbolValuesHelper{context}(call); +} +semantics::UnorderedSymbolSet CollectUsedSymbolValues( + semantics::SemanticsContext &context, const Assignment &assignment) { + return CollectUsedSymbolValuesHelper{context}(assignment); +} } // namespace Fortran::evaluate diff --git a/flang/lib/Evaluate/tools.cpp b/flang/lib/Evaluate/tools.cpp index 37f718c98ebb5..9b7d4c758769e 100644 --- a/flang/lib/Evaluate/tools.cpp +++ b/flang/lib/Evaluate/tools.cpp @@ -2645,4 +2645,16 @@ const Symbol *FindAncestorModuleProcedure(const Symbol *symInSubmodule) { return nullptr; } +const Symbol &GetCrayPointer(const Symbol &crayPointee) { + const Symbol *found{nullptr}; + const Symbol &ultimate{crayPointee.GetUltimate()}; + for (const auto &[pointee, pointer] : ultimate.owner().crayPointers()) { + if (pointee == ultimate.name()) { + found = &pointer.get(); + break; + } + } + return DEREF(found); +} + } // namespace Fortran::semantics diff --git a/flang/lib/Lower/ConvertCall.cpp b/flang/lib/Lower/ConvertCall.cpp index 179626624822d..d72f74b440c53 100644 --- a/flang/lib/Lower/ConvertCall.cpp +++ b/flang/lib/Lower/ConvertCall.cpp @@ -342,6 +342,22 @@ getTypeWithIgnoreTkrC(mlir::FunctionType funcType, return std::nullopt; } +static bool mustDestroyOrFinalizeFunctionResult( + mlir::FunctionType callSiteType, + std::optional retTy) { + if (callSiteType.getNumResults() == 0 || !retTy.has_value()) + return false; + if (fir::isPointerType(callSiteType.getResult(0))) + return false; + if (retTy->IsPolymorphic() || retTy->IsUnlimitedPolymorphic()) + return true; + if (retTy->category() != Fortran::common::TypeCategory::Derived) + return false; + return Fortran::semantics::MayRequireFinalization( + retTy->GetDerivedTypeSpec()) || + hlfir::mayHaveAllocatableComponent(callSiteType.getResult(0)); +} + std::tuple Fortran::lower::genCallOpAndResult( mlir::Location loc, Fortran::lower::AbstractConverter &converter, @@ -803,10 +819,7 @@ Fortran::lower::genCallOpAndResult( // the resulting array result will be finalized/destroyed // as needed by hlfir.destroy. const bool mustFinalizeResult = - !isElemental && callSiteType.getNumResults() > 0 && - !fir::isPointerType(callSiteType.getResult(0)) && retTy.has_value() && - (retTy->category() == Fortran::common::TypeCategory::Derived || - retTy->IsPolymorphic() || retTy->IsUnlimitedPolymorphic()); + !isElemental && mustDestroyOrFinalizeFunctionResult(callSiteType, retTy); if (caller.mustSaveResult()) { assert(allocatedResult.has_value()); @@ -828,7 +841,13 @@ Fortran::lower::genCallOpAndResult( mustFinalizeResult, callOp}; } - if (allocatedResult) { + // Insert clean-up for the result. + // In HLFIR, this is skipped when the result does not need to be finalized + // because the result is moved to an expression that will deal with the + // finalization. + if (allocatedResult && + (mustFinalizeResult || + !converter.getLoweringOptions().getLowerToHighLevelFIR())) { // The result must be optionally destroyed (if it is of a derived type // that may need finalization or deallocation of the components). // For an allocatable result we have to free the memory allocated @@ -853,40 +872,23 @@ Fortran::lower::genCallOpAndResult( [](const auto &) {}); // 7.5.6.3 point 5. Derived-type finalization for nonpointer function. - bool resultIsFinalized = false; - // Check if the derived-type is finalizable if it is a monomorphic - // derived-type. - // For polymorphic and unlimited polymorphic enities call the runtime - // in any cases. + // Note that this is also done for derived type with no final routines + // that have allocatable components to ensure the allocatable + // components are deallocated. if (mustFinalizeResult) { - if (retTy->IsPolymorphic() || retTy->IsUnlimitedPolymorphic()) { - auto *bldr = &converter.getFirOpBuilder(); - stmtCtx.attachCleanup([bldr, loc, allocatedResult]() { - fir::runtime::genDerivedTypeDestroy(*bldr, loc, - fir::getBase(*allocatedResult)); - }); - resultIsFinalized = true; - } else { - const Fortran::semantics::DerivedTypeSpec &typeSpec = - retTy->GetDerivedTypeSpec(); - // If the result type may require finalization - // or have allocatable components, we need to make sure - // everything is properly finalized/deallocated. - if (Fortran::semantics::MayRequireFinalization(typeSpec) || - // We can use DerivedTypeDestroy even if finalization is not needed. - hlfir::mayHaveAllocatableComponent(funcType.getResults()[0])) { - auto *bldr = &converter.getFirOpBuilder(); - stmtCtx.attachCleanup([bldr, loc, allocatedResult]() { - mlir::Value box = bldr->createBox(loc, *allocatedResult); - fir::runtime::genDerivedTypeDestroy(*bldr, loc, box); - }); - resultIsFinalized = true; - } - } + auto *bldr = &converter.getFirOpBuilder(); + stmtCtx.attachCleanup([bldr, loc, allocatedResult]() { + mlir::Value box = bldr->createBox(loc, *allocatedResult); + fir::runtime::genDerivedTypeDestroy(*bldr, loc, box); + }); } - return {LoweredResult{*allocatedResult}, resultIsFinalized, callOp}; + return {LoweredResult{*allocatedResult}, mustFinalizeResult, callOp}; } + if (allocatedResult) + return {LoweredResult{*allocatedResult}, /*resultIsFinalized=*/false, + callOp}; + // subroutine call if (!resultType) return {LoweredResult{fir::ExtendedValue{mlir::Value{}}}, @@ -1928,14 +1930,14 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, prepareUserCallArguments(loweredActuals, caller, callSiteType, callContext, callCleanUps); + const bool isElemental = callContext.isElementalProcWithArrayArgs(); // Prepare lowered arguments according to the interface // and map the lowered values to the dummy // arguments. auto [loweredResult, resultIsFinalized, callOp] = Fortran::lower::genCallOpAndResult( loc, callContext.converter, callContext.symMap, callContext.stmtCtx, - caller, callSiteType, callContext.resultType, - callContext.isElementalProcWithArrayArgs()); + caller, callSiteType, callContext.resultType, isElemental); // Clean-up associations and copy-in. // The association clean-ups are postponed to the end of the statement @@ -1973,17 +1975,28 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, if (!resultIsFinalized) { hlfir::Entity resultEntity = extendedValueToHlfirEntity( loc, builder, result, tempResultName, /*insertBefore=*/callOp); + // Allocatable result must be freed, other results are stack allocated. + const auto *allocatable = result.getBoxOf(); + const bool mustFree = allocatable != nullptr; resultEntity = loadTrivialScalar(loc, builder, resultEntity); if (resultEntity.isVariable()) { // If the result has no finalization, it can be moved into an expression. - // In such case, the expression should not be freed after its use since - // the result is stack allocated or deallocation (for allocatable results) - // was already inserted in genCallOpAndResult. - auto asExpr = - hlfir::AsExprOp::create(builder, loc, resultEntity, - /*mustFree=*/builder.createBool(loc, false)); - return hlfir::EntityWithAttributes{asExpr.getResult()}; + mlir::Value asExpr = hlfir::AsExprOp::create( + builder, loc, resultEntity, builder.createBool(loc, mustFree)); + if (!isElemental) { + // Insert clean-up for the expression, except for elemental call where + // the cleaned-up is inserted at the array level. + callContext.stmtCtx.attachCleanup([bldr = &builder, loc, asExpr]() { + hlfir::DestroyOp::create(*bldr, loc, asExpr, /*finalize=*/false); + }); + } + return hlfir::EntityWithAttributes{asExpr}; } + if (allocatable) + callContext.stmtCtx.attachCleanup( + [bldr = &builder, loc, box = *allocatable]() { + fir::factory::genFreememIfAllocated(*bldr, loc, box); + }); return hlfir::EntityWithAttributes{resultEntity}; } // If the result has finalization, it cannot be moved because use of its diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp index 183f9e717532a..45420a1b720c9 100644 --- a/flang/lib/Lower/OpenACC.cpp +++ b/flang/lib/Lower/OpenACC.cpp @@ -775,16 +775,9 @@ genDataOperandOperations(const Fortran::parser::AccObjectList &objectList, if (auto *defOp = op.getVar().getDefiningOp()) addDeclareAttr(builder, defOp, dataClause); - // TODO: no_create remapping could currently cause segfaults because of the - // fir.box_addr that may be inserted in the remapping in the region. - // This is an issue if the variable is not mapped (which is OK if its - // accesses are not reached inside the construct). - bool isNoCreateWithBounds = - std::is_same_v && !bounds.empty(); - // Track the symbol and its corresponding mlir::Value if requested so that // accesses inside regions can be remapped. - if (dataMap && !isNoCreateWithBounds) { + if (dataMap) { if (componentRef) dataMap->emplaceComponent(op.getAccVar(), std::move(*componentRef), baseAddr); @@ -4304,20 +4297,26 @@ genACC(Fortran::lower::AbstractConverter &converter, fir::substBase(hostExv, cacheOp.getAccVar()); converter.bindSymbol(symbol, cacheExv); } else { - // Must be a derived type component reference. + // Derived type component reference. assert(designator && "expected designator for non-symbol cache operand"); std::optional componentRef = extractComponentFromDesignator(designator); assert(componentRef && "expected component reference for derived type cache operand"); - // Component references are lowered to designate operations. - auto designate = base.getDefiningOp(); - assert(designate && "expected designate op for component reference"); + // When component is mapped via a data clause, base may be a declare op + // instead of a designate op. + auto varIface = base.getDefiningOp(); + assert(varIface && + "expected FortranVariableOpInterface for component reference"); + fir::FortranVariableFlagsAttr attrs; + if (auto fortranAttrs = varIface.getFortranAttrs()) + attrs = fir::FortranVariableFlagsAttr::get(builder.getContext(), + *fortranAttrs); auto declareOp = hlfir::DeclareOp::create( builder, operandLocation, cacheOp.getAccVar(), asFortran.str(), - designate.getShape(), designate.getTypeparams(), + varIface.getShape(), varIface.getExplicitTypeParams(), /*dummyScope=*/nullptr, /*storage=*/nullptr, - /*storageOffset=*/0, designate.getFortranAttrsAttr()); + /*storageOffset=*/0, attrs); converter.getSymbolMap().addComponentOverride(*componentRef, declareOp); } } diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 8094c6264b492..b1973a3b8bf06 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -710,6 +710,23 @@ static llvm::StringMap getTargetFeatures(mlir::ModuleOp module) { return featuresMap; } +bool ClauseProcessor::processAffinity( + mlir::omp::AffinityClauseOps &result) const { + return findRepeatableClause( + [&](const omp::clause::Affinity &clause, const parser::CharBlock &) { + if (std::get>(clause.t)) { + TODO(converter.getCurrentLocation(), + "Support for iterator modifiers is not implemented yet"); + } + + const auto &objects = std::get(clause.t); + if (!objects.empty()) + genObjectList(objects, converter, result.affinityVars); + + return true; + }); +} + static void addAlignedClause(lower::AbstractConverter &converter, const omp::clause::Aligned &clause, diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.h b/flang/lib/Lower/OpenMP/ClauseProcessor.h index ba1764ce46821..ca9b28dfdd061 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.h +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.h @@ -119,6 +119,7 @@ class ClauseProcessor { bool processDetach(mlir::omp::DetachClauseOps &result) const; // 'Repeatable' clauses: They can appear multiple times in the clause list. + bool processAffinity(mlir::omp::AffinityClauseOps &result) const; bool processAligned(mlir::omp::AlignedClauseOps &result) const; bool processAllocate(mlir::omp::AllocateClauseOps &result) const; bool processCopyin() const; diff --git a/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp b/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp index 83c2eda0a2dc7..a958ec9ba503c 100644 --- a/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp +++ b/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp @@ -479,8 +479,7 @@ void DataSharingProcessor::collectSymbols( for (const semantics::Scope &child : scope->children()) collectScopes(&child); }; - parser::CharBlock source = - clauses.empty() ? getSource(semaCtx, eval) : clauses.front().source; + parser::CharBlock source = getSource(semaCtx, eval); const semantics::Scope *curScope = nullptr; if (!source.empty()) { curScope = &semaCtx.FindScope(source); diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index 43c6128d46647..df89cbe46a5c8 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -1801,6 +1801,7 @@ static void genTaskClauses( mlir::omp::TaskOperands &clauseOps, llvm::SmallVectorImpl &inReductionSyms) { ClauseProcessor cp(converter, semaCtx, clauses); + cp.processAffinity(clauseOps); cp.processAllocate(clauseOps); cp.processDepend(symTable, stmtCtx, clauseOps); cp.processFinal(stmtCtx, clauseOps); @@ -1810,8 +1811,6 @@ static void genTaskClauses( cp.processPriority(stmtCtx, clauseOps); cp.processUntied(clauseOps); cp.processDetach(clauseOps); - - cp.processTODO(loc, llvm::omp::Directive::OMPD_task); } static void genTaskgroupClauses( @@ -3884,31 +3883,29 @@ static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, const auto &specifier = DEREF(parser::omp::GetFirstArgument( construct.v)); - if (std::get(specifier.t).v.size() > 1) - TODO(converter.getCurrentLocation(), - "multiple types in declare reduction is not yet supported"); - - mlir::Type reductionType = getReductionType(converter, specifier); + const auto &typeNameList = std::get(specifier.t); List clauses = makeClauses(construct.v.Clauses(), semaCtx); const clause::Combiner &combiner = appendCombiner(construct, clauses, semaCtx); - - ReductionProcessor::GenCombinerCBTy genCombinerCB = - processReductionCombiner(converter, symTable, semaCtx, combiner); - - ReductionProcessor::GenInitValueCBTy genInitValueCB; - ClauseProcessor cp(converter, semaCtx, clauses); - cp.processInitializer(symTable, genInitValueCB); - const auto &identifier = std::get(specifier.t); const auto &designator = std::get(identifier.u); const auto &reductionName = std::get(designator.u); - bool isByRef = ReductionProcessor::doReductionByRef(reductionType); - ReductionProcessor::createDeclareReductionHelper< - mlir::omp::DeclareReductionOp>( - converter, reductionName.ToString(), reductionType, - converter.getCurrentLocation(), isByRef, genCombinerCB, genInitValueCB); + + for (const auto &typeSpec : typeNameList.v) { + (void)typeSpec; // Currently unused + mlir::Type reductionType = getReductionType(converter, specifier); + ReductionProcessor::GenCombinerCBTy genCombinerCB = + processReductionCombiner(converter, symTable, semaCtx, combiner); + ReductionProcessor::GenInitValueCBTy genInitValueCB; + ClauseProcessor cp(converter, semaCtx, clauses); + cp.processInitializer(symTable, genInitValueCB); + bool isByRef = ReductionProcessor::doReductionByRef(reductionType); + ReductionProcessor::createDeclareReductionHelper< + mlir::omp::DeclareReductionOp>( + converter, reductionName.ToString(), reductionType, + converter.getCurrentLocation(), isByRef, genCombinerCB, genInitValueCB); + } } static void diff --git a/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp b/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp index 2901ee00e1fbc..0eb00e2f0c549 100644 --- a/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp +++ b/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp @@ -227,6 +227,34 @@ bool AliasAnalysis::Source::mayBeActualArgWithPtr( return false; } +// Return true if the two locations cannot alias based +// on the access data type, e.g. an address of a descriptor +// cannot alias with an address of data (unless the data +// may contain a descriptor). +static bool noAliasBasedOnType(mlir::Value lhs, mlir::Value rhs) { + mlir::Type lhsType = lhs.getType(); + mlir::Type rhsType = rhs.getType(); + if (!fir::isa_ref_type(lhsType) || !fir::isa_ref_type(rhsType)) + return false; + mlir::Type lhsElemType = fir::unwrapRefType(lhsType); + mlir::Type rhsElemType = fir::unwrapRefType(rhsType); + if (mlir::isa(lhsElemType) != + mlir::isa(rhsElemType)) { + // One of the types is fir.box and another is not. + mlir::Type nonBoxType; + if (mlir::isa(lhsElemType)) + nonBoxType = rhsElemType; + else + nonBoxType = lhsElemType; + + if (!fir::isRecordWithDescriptorMember(nonBoxType)) { + LLVM_DEBUG(llvm::dbgs() << " no alias based on the access types\n"); + return true; + } + } + return false; +} + AliasResult AliasAnalysis::alias(mlir::Value lhs, mlir::Value rhs) { // A wrapper around alias(Source lhsSrc, Source rhsSrc, mlir::Value lhs, // mlir::Value rhs) This allows a user to provide Source that may be obtained @@ -248,6 +276,10 @@ AliasResult AliasAnalysis::alias(Source lhsSrc, Source rhsSrc, mlir::Value lhs, llvm::dbgs() << " rhs: " << rhs << "\n"; llvm::dbgs() << " rhsSrc: " << rhsSrc << "\n";); + // Disambiguate data and descriptors addresses. + if (noAliasBasedOnType(lhs, rhs)) + return AliasResult::NoAlias; + // Indirect case currently not handled. Conservatively assume // it aliases with everything if (lhsSrc.kind >= SourceKind::Indirect || diff --git a/flang/lib/Optimizer/Analysis/ArraySectionAnalyzer.cpp b/flang/lib/Optimizer/Analysis/ArraySectionAnalyzer.cpp new file mode 100644 index 0000000000000..f5ee298f0948c --- /dev/null +++ b/flang/lib/Optimizer/Analysis/ArraySectionAnalyzer.cpp @@ -0,0 +1,300 @@ +//===- ArraySectionAnalyzer.cpp - Analyze array sections ------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "flang/Optimizer/Analysis/ArraySectionAnalyzer.h" +#include "flang/Optimizer/Dialect/FIROps.h" +#include "flang/Optimizer/Dialect/FIROpsSupport.h" +#include "flang/Optimizer/HLFIR/HLFIROps.h" +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "array-section-analyzer" + +using namespace fir; + +ArraySectionAnalyzer::SectionDesc::SectionDesc(mlir::Value lb, mlir::Value ub, + mlir::Value stride) + : lb(lb), ub(ub), stride(stride) { + assert(lb && "lower bound or index must be specified"); + normalize(); +} + +void ArraySectionAnalyzer::SectionDesc::normalize() { + if (!ub) + ub = lb; + if (lb == ub) + stride = nullptr; + if (stride) + if (auto val = fir::getIntIfConstant(stride)) + if (*val == 1) + stride = nullptr; +} + +bool ArraySectionAnalyzer::SectionDesc::operator==( + const SectionDesc &other) const { + return lb == other.lb && ub == other.ub && stride == other.stride; +} + +ArraySectionAnalyzer::SectionDesc +ArraySectionAnalyzer::readSectionDesc(mlir::Operation::operand_iterator &it, + bool isTriplet) { + if (isTriplet) + return {*it++, *it++, *it++}; + return {*it++, nullptr, nullptr}; +} + +std::pair +ArraySectionAnalyzer::getOrderedBounds(const SectionDesc &desc) { + mlir::Value stride = desc.stride; + // Null stride means stride=1. + if (!stride) + return {desc.lb, desc.ub}; + // Reverse the bounds, if stride is negative. + if (auto val = fir::getIntIfConstant(stride)) { + if (*val >= 0) + return {desc.lb, desc.ub}; + else + return {desc.ub, desc.lb}; + } + + return {nullptr, nullptr}; +} + +bool ArraySectionAnalyzer::areDisjointSections(const SectionDesc &desc1, + const SectionDesc &desc2) { + auto [lb1, ub1] = getOrderedBounds(desc1); + auto [lb2, ub2] = getOrderedBounds(desc2); + if (!lb1 || !lb2) + return false; + // Note that this comparison must be made on the ordered bounds, + // otherwise 'a(x:y:1) = a(z:x-1:-1) + 1' may be incorrectly treated + // as not overlapping (x=2, y=10, z=9). + if (isLess(ub1, lb2) || isLess(ub2, lb1)) + return true; + return false; +} + +bool ArraySectionAnalyzer::areIdenticalSections(const SectionDesc &desc1, + const SectionDesc &desc2) { + if (desc1 == desc2) + return true; + return false; +} + +ArraySectionAnalyzer::SlicesOverlapKind +ArraySectionAnalyzer::analyze(mlir::Value ref1, mlir::Value ref2) { + if (ref1 == ref2) + return SlicesOverlapKind::DefinitelyIdentical; + + auto des1 = ref1.getDefiningOp(); + auto des2 = ref2.getDefiningOp(); + // We only support a pair of designators right now. + if (!des1 || !des2) + return SlicesOverlapKind::Unknown; + + if (des1.getMemref() != des2.getMemref()) { + // If the bases are different, then there is unknown overlap. + LLVM_DEBUG(llvm::dbgs() << "No identical base for:\n" + << des1 << "and:\n" + << des2 << "\n"); + return SlicesOverlapKind::Unknown; + } + + // Require all components of the designators to be the same. + // It might be too strict, e.g. we may probably allow for + // different type parameters. + if (des1.getComponent() != des2.getComponent() || + des1.getComponentShape() != des2.getComponentShape() || + des1.getSubstring() != des2.getSubstring() || + des1.getComplexPart() != des2.getComplexPart() || + des1.getTypeparams() != des2.getTypeparams()) { + LLVM_DEBUG(llvm::dbgs() << "Different designator specs for:\n" + << des1 << "and:\n" + << des2 << "\n"); + return SlicesOverlapKind::Unknown; + } + + // Analyze the subscripts. + auto des1It = des1.getIndices().begin(); + auto des2It = des2.getIndices().begin(); + bool identicalTriplets = true; + bool identicalIndices = true; + for (auto [isTriplet1, isTriplet2] : + llvm::zip(des1.getIsTriplet(), des2.getIsTriplet())) { + SectionDesc desc1 = readSectionDesc(des1It, isTriplet1); + SectionDesc desc2 = readSectionDesc(des2It, isTriplet2); + + // See if we can prove that any of the sections do not overlap. + // This is mostly a Polyhedron/nf performance hack that looks for + // particular relations between the lower and upper bounds + // of the array sections, e.g. for any positive constant C: + // X:Y does not overlap with (Y+C):Z + // X:Y does not overlap with Z:(X-C) + if (areDisjointSections(desc1, desc2)) + return SlicesOverlapKind::DefinitelyDisjoint; + + if (!areIdenticalSections(desc1, desc2)) { + if (isTriplet1 || isTriplet2) { + // For example: + // hlfir.designate %6#0 (%c2:%c7999:%c1, %c1:%c120:%c1, %0) + // hlfir.designate %6#0 (%c2:%c7999:%c1, %c1:%c120:%c1, %1) + // + // If all the triplets (section speficiers) are the same, then + // we do not care if %0 is equal to %1 - the slices are either + // identical or completely disjoint. + // + // Also, treat these as identical sections: + // hlfir.designate %6#0 (%c2:%c2:%c1) + // hlfir.designate %6#0 (%c2) + identicalTriplets = false; + LLVM_DEBUG(llvm::dbgs() << "Triplet mismatch for:\n" + << des1 << "and:\n" + << des2 << "\n"); + } else { + identicalIndices = false; + LLVM_DEBUG(llvm::dbgs() << "Indices mismatch for:\n" + << des1 << "and:\n" + << des2 << "\n"); + } + } + } + + if (identicalTriplets) { + if (identicalIndices) + return SlicesOverlapKind::DefinitelyIdentical; + else + return SlicesOverlapKind::EitherIdenticalOrDisjoint; + } + + LLVM_DEBUG(llvm::dbgs() << "Different sections for:\n" + << des1 << "and:\n" + << des2 << "\n"); + return SlicesOverlapKind::Unknown; +} + +bool ArraySectionAnalyzer::isLess(mlir::Value v1, mlir::Value v2) { + auto removeConvert = [](mlir::Value v) -> mlir::Operation * { + auto *op = v.getDefiningOp(); + while (auto conv = mlir::dyn_cast_or_null(op)) + op = conv.getValue().getDefiningOp(); + return op; + }; + + auto isPositiveConstant = [](mlir::Value v) -> bool { + if (auto val = fir::getIntIfConstant(v)) + return *val > 0; + return false; + }; + + auto *op1 = removeConvert(v1); + auto *op2 = removeConvert(v2); + if (!op1 || !op2) + return false; + + // Check if they are both constants. + if (auto val1 = fir::getIntIfConstant(op1->getResult(0))) + if (auto val2 = fir::getIntIfConstant(op2->getResult(0))) + return *val1 < *val2; + + // Handle some variable cases (C > 0): + // v2 = v1 + C + // v2 = C + v1 + // v1 = v2 - C + if (auto addi = mlir::dyn_cast(op2)) + if ((addi.getLhs().getDefiningOp() == op1 && + isPositiveConstant(addi.getRhs())) || + (addi.getRhs().getDefiningOp() == op1 && + isPositiveConstant(addi.getLhs()))) + return true; + if (auto subi = mlir::dyn_cast(op1)) + if (subi.getLhs().getDefiningOp() == op2 && + isPositiveConstant(subi.getRhs())) + return true; + return false; +} + +/// Returns the array indices for the given hlfir.designate. +/// It recognizes the computations used to transform the one-based indices +/// into the array's lb-based indices, and returns the one-based indices +/// in these cases. +static llvm::SmallVector +getDesignatorIndices(hlfir::DesignateOp designate) { + mlir::Value memref = designate.getMemref(); + + // If the object is a box, then the indices may be adjusted + // according to the box's lower bound(s). Scan through + // the computations to try to find the one-based indices. + if (mlir::isa(memref.getType())) { + // Look for the following pattern: + // %13 = fir.load %12 : !fir.ref + // %14:3 = fir.box_dims %13, %c0 : (!fir.box<...>, index) -> ... + // %17 = arith.subi %14#0, %c1 : index + // %18 = arith.addi %arg2, %17 : index + // %19 = hlfir.designate %13 (%18) : (!fir.box<...>, index) -> ... + // + // %arg2 is a one-based index. + + auto isNormalizedLb = [memref](mlir::Value v, unsigned dim) { + // Return true, if v and dim are such that: + // %14:3 = fir.box_dims %13, %dim : (!fir.box<...>, index) -> ... + // %17 = arith.subi %14#0, %c1 : index + // %19 = hlfir.designate %13 (...) : (!fir.box<...>, index) -> ... + if (auto subOp = + mlir::dyn_cast_or_null(v.getDefiningOp())) { + auto cst = fir::getIntIfConstant(subOp.getRhs()); + if (!cst || *cst != 1) + return false; + if (auto dimsOp = mlir::dyn_cast_or_null( + subOp.getLhs().getDefiningOp())) { + if (memref != dimsOp.getVal() || + dimsOp.getResult(0) != subOp.getLhs()) + return false; + auto dimsOpDim = fir::getIntIfConstant(dimsOp.getDim()); + return dimsOpDim && dimsOpDim == dim; + } + } + return false; + }; + + llvm::SmallVector newIndices; + for (auto index : llvm::enumerate(designate.getIndices())) { + if (auto addOp = mlir::dyn_cast_or_null( + index.value().getDefiningOp())) { + for (unsigned opNum = 0; opNum < 2; ++opNum) + if (isNormalizedLb(addOp->getOperand(opNum), index.index())) { + newIndices.push_back(addOp->getOperand((opNum + 1) % 2)); + break; + } + + // If new one-based index was not added, exit early. + if (newIndices.size() <= index.index()) + break; + } + } + + // If any of the indices is not adjusted to the array's lb, + // then return the original designator indices. + if (newIndices.size() != designate.getIndices().size()) + return designate.getIndices(); + + return newIndices; + } + + return designate.getIndices(); +} + +bool fir::ArraySectionAnalyzer::isDesignatingArrayInOrder( + hlfir::DesignateOp designate, hlfir::ElementalOpInterface elemental) { + + auto indices = getDesignatorIndices(designate); + auto elementalIndices = elemental.getIndices(); + if (indices.size() == elementalIndices.size()) + return std::equal(indices.begin(), indices.end(), elementalIndices.begin(), + elementalIndices.end()); + return false; +} diff --git a/flang/lib/Optimizer/Analysis/CMakeLists.txt b/flang/lib/Optimizer/Analysis/CMakeLists.txt index c890b969bae34..398a6d3b88427 100644 --- a/flang/lib/Optimizer/Analysis/CMakeLists.txt +++ b/flang/lib/Optimizer/Analysis/CMakeLists.txt @@ -1,5 +1,6 @@ add_flang_library(FIRAnalysis AliasAnalysis.cpp + ArraySectionAnalyzer.cpp TBAAForest.cpp DEPENDS @@ -10,7 +11,6 @@ add_flang_library(FIRAnalysis LINK_LIBS CUFDialect - FIRBuilder FIRDialect FIRSupport HLFIRDialect diff --git a/flang/lib/Optimizer/Dialect/FIROps.cpp b/flang/lib/Optimizer/Dialect/FIROps.cpp index 339ba3ac7449e..9c22b614d0cf9 100644 --- a/flang/lib/Optimizer/Dialect/FIROps.cpp +++ b/flang/lib/Optimizer/Dialect/FIROps.cpp @@ -1922,6 +1922,15 @@ std::optional fir::CoordinateOp::getViewOffset(mlir::OpResult) { return std::nullopt; } +mlir::Speculation::Speculatability fir::CoordinateOp::getSpeculatability() { + const mlir::Type refTy = getRef().getType(); + if (fir::isa_ref_type(refTy)) + return mlir::Speculation::Speculatable; + + return mayBeAbsentBox(getRef()) ? mlir::Speculation::NotSpeculatable + : mlir::Speculation::Speculatable; +} + //===----------------------------------------------------------------------===// // DispatchOp //===----------------------------------------------------------------------===// diff --git a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp index 5351a9a50954f..58891227965f4 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "flang/Optimizer/Analysis/AliasAnalysis.h" +#include "flang/Optimizer/Analysis/ArraySectionAnalyzer.h" #include "flang/Optimizer/Builder/FIRBuilder.h" #include "flang/Optimizer/Builder/HLFIRTools.h" #include "flang/Optimizer/Dialect/FIROps.h" @@ -88,13 +89,6 @@ class ElementalAssignBufferization /// determines if the transformation can be applied to this elemental static std::optional findMatch(hlfir::ElementalOp elemental); - /// Returns the array indices for the given hlfir.designate. - /// It recognizes the computations used to transform the one-based indices - /// into the array's lb-based indices, and returns the one-based indices - /// in these cases. - static llvm::SmallVector - getDesignatorIndices(hlfir::DesignateOp designate); - public: using mlir::OpRewritePattern::OpRewritePattern; @@ -167,344 +161,6 @@ containsReadOrWriteEffectOn(const mlir::MemoryEffects::EffectInstance &effect, return mlir::AliasResult::NoAlias; } -// Helper class for analyzing two array slices represented -// by two hlfir.designate operations. -class ArraySectionAnalyzer { -public: - // The result of the analyzis is one of the values below. - enum class SlicesOverlapKind { - // Slices overlap is unknown. - Unknown, - // Slices are definitely identical. - DefinitelyIdentical, - // Slices are definitely disjoint. - DefinitelyDisjoint, - // Slices may be either disjoint or identical, - // i.e. there is definitely no partial overlap. - EitherIdenticalOrDisjoint - }; - - // Analyzes two hlfir.designate results and returns the overlap kind. - // The callers may use this method when the alias analysis reports - // an alias of some kind, so that we can run Fortran specific analysis - // on the array slices to see if they are identical or disjoint. - // Note that the alias analysis are not able to give such an answer - // about the references. - static SlicesOverlapKind analyze(mlir::Value ref1, mlir::Value ref2); - -private: - struct SectionDesc { - // An array section is described by tuple. - // If the designator's subscript is not a triple, then - // the section descriptor is constructed as . - mlir::Value lb, ub, stride; - - SectionDesc(mlir::Value lb, mlir::Value ub, mlir::Value stride) - : lb(lb), ub(ub), stride(stride) { - assert(lb && "lower bound or index must be specified"); - normalize(); - } - - // Normalize the section descriptor: - // 1. If UB is nullptr, then it is set to LB. - // 2. If LB==UB, then stride does not matter, - // so it is reset to nullptr. - // 3. If STRIDE==1, then it is reset to nullptr. - void normalize() { - if (!ub) - ub = lb; - if (lb == ub) - stride = nullptr; - if (stride) - if (auto val = fir::getIntIfConstant(stride)) - if (*val == 1) - stride = nullptr; - } - - bool operator==(const SectionDesc &other) const { - return lb == other.lb && ub == other.ub && stride == other.stride; - } - }; - - // Given an operand_iterator over the indices operands, - // read the subscript values and return them as SectionDesc - // updating the iterator. If isTriplet is true, - // the subscript is a triplet, and the result is . - // Otherwise, the subscript is a scalar index, and the result - // is . - static SectionDesc readSectionDesc(mlir::Operation::operand_iterator &it, - bool isTriplet) { - if (isTriplet) - return {*it++, *it++, *it++}; - return {*it++, nullptr, nullptr}; - } - - // Return the ordered lower and upper bounds of the section. - // If stride is known to be non-negative, then the ordered - // bounds match the of the descriptor. - // If stride is known to be negative, then the ordered - // bounds are of the descriptor. - // If stride is unknown, we cannot deduce any order, - // so the result is - static std::pair - getOrderedBounds(const SectionDesc &desc) { - mlir::Value stride = desc.stride; - // Null stride means stride=1. - if (!stride) - return {desc.lb, desc.ub}; - // Reverse the bounds, if stride is negative. - if (auto val = fir::getIntIfConstant(stride)) { - if (*val >= 0) - return {desc.lb, desc.ub}; - else - return {desc.ub, desc.lb}; - } - - return {nullptr, nullptr}; - } - - // Given two array sections and - // , return true only if the sections - // are known to be disjoint. - // - // For example, for any positive constant C: - // X:Y does not overlap with (Y+C):Z - // X:Y does not overlap with Z:(X-C) - static bool areDisjointSections(const SectionDesc &desc1, - const SectionDesc &desc2) { - auto [lb1, ub1] = getOrderedBounds(desc1); - auto [lb2, ub2] = getOrderedBounds(desc2); - if (!lb1 || !lb2) - return false; - // Note that this comparison must be made on the ordered bounds, - // otherwise 'a(x:y:1) = a(z:x-1:-1) + 1' may be incorrectly treated - // as not overlapping (x=2, y=10, z=9). - if (isLess(ub1, lb2) || isLess(ub2, lb1)) - return true; - return false; - } - - // Given two array sections and - // , return true only if the sections - // are known to be identical. - // - // For example: - // - // - // - // These sections are identical, from the point of which array - // elements are being addresses, even though the shape - // of the array slices might be different. - static bool areIdenticalSections(const SectionDesc &desc1, - const SectionDesc &desc2) { - if (desc1 == desc2) - return true; - return false; - } - - // Return true, if v1 is known to be less than v2. - static bool isLess(mlir::Value v1, mlir::Value v2); -}; - -ArraySectionAnalyzer::SlicesOverlapKind -ArraySectionAnalyzer::analyze(mlir::Value ref1, mlir::Value ref2) { - if (ref1 == ref2) - return SlicesOverlapKind::DefinitelyIdentical; - - auto des1 = ref1.getDefiningOp(); - auto des2 = ref2.getDefiningOp(); - // We only support a pair of designators right now. - if (!des1 || !des2) - return SlicesOverlapKind::Unknown; - - if (des1.getMemref() != des2.getMemref()) { - // If the bases are different, then there is unknown overlap. - LLVM_DEBUG(llvm::dbgs() << "No identical base for:\n" - << des1 << "and:\n" - << des2 << "\n"); - return SlicesOverlapKind::Unknown; - } - - // Require all components of the designators to be the same. - // It might be too strict, e.g. we may probably allow for - // different type parameters. - if (des1.getComponent() != des2.getComponent() || - des1.getComponentShape() != des2.getComponentShape() || - des1.getSubstring() != des2.getSubstring() || - des1.getComplexPart() != des2.getComplexPart() || - des1.getTypeparams() != des2.getTypeparams()) { - LLVM_DEBUG(llvm::dbgs() << "Different designator specs for:\n" - << des1 << "and:\n" - << des2 << "\n"); - return SlicesOverlapKind::Unknown; - } - - // Analyze the subscripts. - auto des1It = des1.getIndices().begin(); - auto des2It = des2.getIndices().begin(); - bool identicalTriplets = true; - bool identicalIndices = true; - for (auto [isTriplet1, isTriplet2] : - llvm::zip(des1.getIsTriplet(), des2.getIsTriplet())) { - SectionDesc desc1 = readSectionDesc(des1It, isTriplet1); - SectionDesc desc2 = readSectionDesc(des2It, isTriplet2); - - // See if we can prove that any of the sections do not overlap. - // This is mostly a Polyhedron/nf performance hack that looks for - // particular relations between the lower and upper bounds - // of the array sections, e.g. for any positive constant C: - // X:Y does not overlap with (Y+C):Z - // X:Y does not overlap with Z:(X-C) - if (areDisjointSections(desc1, desc2)) - return SlicesOverlapKind::DefinitelyDisjoint; - - if (!areIdenticalSections(desc1, desc2)) { - if (isTriplet1 || isTriplet2) { - // For example: - // hlfir.designate %6#0 (%c2:%c7999:%c1, %c1:%c120:%c1, %0) - // hlfir.designate %6#0 (%c2:%c7999:%c1, %c1:%c120:%c1, %1) - // - // If all the triplets (section speficiers) are the same, then - // we do not care if %0 is equal to %1 - the slices are either - // identical or completely disjoint. - // - // Also, treat these as identical sections: - // hlfir.designate %6#0 (%c2:%c2:%c1) - // hlfir.designate %6#0 (%c2) - identicalTriplets = false; - LLVM_DEBUG(llvm::dbgs() << "Triplet mismatch for:\n" - << des1 << "and:\n" - << des2 << "\n"); - } else { - identicalIndices = false; - LLVM_DEBUG(llvm::dbgs() << "Indices mismatch for:\n" - << des1 << "and:\n" - << des2 << "\n"); - } - } - } - - if (identicalTriplets) { - if (identicalIndices) - return SlicesOverlapKind::DefinitelyIdentical; - else - return SlicesOverlapKind::EitherIdenticalOrDisjoint; - } - - LLVM_DEBUG(llvm::dbgs() << "Different sections for:\n" - << des1 << "and:\n" - << des2 << "\n"); - return SlicesOverlapKind::Unknown; -} - -bool ArraySectionAnalyzer::isLess(mlir::Value v1, mlir::Value v2) { - auto removeConvert = [](mlir::Value v) -> mlir::Operation * { - auto *op = v.getDefiningOp(); - while (auto conv = mlir::dyn_cast_or_null(op)) - op = conv.getValue().getDefiningOp(); - return op; - }; - - auto isPositiveConstant = [](mlir::Value v) -> bool { - if (auto val = fir::getIntIfConstant(v)) - return *val > 0; - return false; - }; - - auto *op1 = removeConvert(v1); - auto *op2 = removeConvert(v2); - if (!op1 || !op2) - return false; - - // Check if they are both constants. - if (auto val1 = fir::getIntIfConstant(op1->getResult(0))) - if (auto val2 = fir::getIntIfConstant(op2->getResult(0))) - return *val1 < *val2; - - // Handle some variable cases (C > 0): - // v2 = v1 + C - // v2 = C + v1 - // v1 = v2 - C - if (auto addi = mlir::dyn_cast(op2)) - if ((addi.getLhs().getDefiningOp() == op1 && - isPositiveConstant(addi.getRhs())) || - (addi.getRhs().getDefiningOp() == op1 && - isPositiveConstant(addi.getLhs()))) - return true; - if (auto subi = mlir::dyn_cast(op1)) - if (subi.getLhs().getDefiningOp() == op2 && - isPositiveConstant(subi.getRhs())) - return true; - return false; -} - -llvm::SmallVector -ElementalAssignBufferization::getDesignatorIndices( - hlfir::DesignateOp designate) { - mlir::Value memref = designate.getMemref(); - - // If the object is a box, then the indices may be adjusted - // according to the box's lower bound(s). Scan through - // the computations to try to find the one-based indices. - if (mlir::isa(memref.getType())) { - // Look for the following pattern: - // %13 = fir.load %12 : !fir.ref - // %14:3 = fir.box_dims %13, %c0 : (!fir.box<...>, index) -> ... - // %17 = arith.subi %14#0, %c1 : index - // %18 = arith.addi %arg2, %17 : index - // %19 = hlfir.designate %13 (%18) : (!fir.box<...>, index) -> ... - // - // %arg2 is a one-based index. - - auto isNormalizedLb = [memref](mlir::Value v, unsigned dim) { - // Return true, if v and dim are such that: - // %14:3 = fir.box_dims %13, %dim : (!fir.box<...>, index) -> ... - // %17 = arith.subi %14#0, %c1 : index - // %19 = hlfir.designate %13 (...) : (!fir.box<...>, index) -> ... - if (auto subOp = - mlir::dyn_cast_or_null(v.getDefiningOp())) { - auto cst = fir::getIntIfConstant(subOp.getRhs()); - if (!cst || *cst != 1) - return false; - if (auto dimsOp = mlir::dyn_cast_or_null( - subOp.getLhs().getDefiningOp())) { - if (memref != dimsOp.getVal() || - dimsOp.getResult(0) != subOp.getLhs()) - return false; - auto dimsOpDim = fir::getIntIfConstant(dimsOp.getDim()); - return dimsOpDim && dimsOpDim == dim; - } - } - return false; - }; - - llvm::SmallVector newIndices; - for (auto index : llvm::enumerate(designate.getIndices())) { - if (auto addOp = mlir::dyn_cast_or_null( - index.value().getDefiningOp())) { - for (unsigned opNum = 0; opNum < 2; ++opNum) - if (isNormalizedLb(addOp->getOperand(opNum), index.index())) { - newIndices.push_back(addOp->getOperand((opNum + 1) % 2)); - break; - } - - // If new one-based index was not added, exit early. - if (newIndices.size() <= index.index()) - break; - } - } - - // If any of the indices is not adjusted to the array's lb, - // then return the original designator indices. - if (newIndices.size() != designate.getIndices().size()) - return designate.getIndices(); - - return newIndices; - } - - return designate.getIndices(); -} - std::optional ElementalAssignBufferization::findMatch(hlfir::ElementalOp elemental) { mlir::Operation::user_range users = elemental->getUsers(); @@ -627,22 +283,20 @@ ElementalAssignBufferization::findMatch(hlfir::ElementalOp elemental) { if (!res.isPartial()) { if (auto designate = effect.getValue().getDefiningOp()) { - ArraySectionAnalyzer::SlicesOverlapKind overlap = - ArraySectionAnalyzer::analyze(match.array, designate.getMemref()); + fir::ArraySectionAnalyzer::SlicesOverlapKind overlap = + fir::ArraySectionAnalyzer::analyze(match.array, + designate.getMemref()); if (overlap == - ArraySectionAnalyzer::SlicesOverlapKind::DefinitelyDisjoint) + fir::ArraySectionAnalyzer::SlicesOverlapKind::DefinitelyDisjoint) continue; - if (overlap == ArraySectionAnalyzer::SlicesOverlapKind::Unknown) { + if (overlap == fir::ArraySectionAnalyzer::SlicesOverlapKind::Unknown) { LLVM_DEBUG(llvm::dbgs() << "possible read conflict: " << designate << " at " << elemental.getLoc() << "\n"); return std::nullopt; } - auto indices = getDesignatorIndices(designate); - auto elementalIndices = elemental.getIndices(); - if (indices.size() == elementalIndices.size() && - std::equal(indices.begin(), indices.end(), elementalIndices.begin(), - elementalIndices.end())) + if (fir::ArraySectionAnalyzer::isDesignatingArrayInOrder(designate, + elemental)) continue; LLVM_DEBUG(llvm::dbgs() << "possible read conflict: " << designate diff --git a/flang/lib/Optimizer/Passes/Pipelines.cpp b/flang/lib/Optimizer/Passes/Pipelines.cpp index 6054675643c64..6812347a8d39b 100644 --- a/flang/lib/Optimizer/Passes/Pipelines.cpp +++ b/flang/lib/Optimizer/Passes/Pipelines.cpp @@ -108,8 +108,8 @@ void addDebugInfoPass(mlir::PassManager &pm, [&]() { return fir::createAddDebugInfoPass(options); }); } -void addFIRToLLVMPass(mlir::PassManager &pm, - const MLIRToLLVMPassPipelineConfig &config) { +fir::FIRToLLVMPassOptions +getFIRToLLVMPassOptions(const MLIRToLLVMPassPipelineConfig &config) { fir::FIRToLLVMPassOptions options; options.ignoreMissingTypeDescriptors = ignoreMissingTypeDescriptors; options.skipExternalRttiDefinition = skipExternalRttiDefinition; @@ -118,6 +118,12 @@ void addFIRToLLVMPass(mlir::PassManager &pm, options.typeDescriptorsRenamedForAssembly = !disableCompilerGeneratedNamesConversion; options.ComplexRange = config.ComplexRange; + return options; +} + +void addFIRToLLVMPass(mlir::PassManager &pm, + const MLIRToLLVMPassPipelineConfig &config) { + fir::FIRToLLVMPassOptions options = getFIRToLLVMPassOptions(config); addPassConditionally(pm, disableFirToLlvmIr, [&]() { return fir::createFIRToLLVMPass(options); }); // The dialect conversion framework may leave dead unrealized_conversion_cast diff --git a/flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp b/flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp index 4be174fe7a4ea..4532af98d8390 100644 --- a/flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp +++ b/flang/lib/Optimizer/Transforms/CUDA/CUFDeviceFuncTransform.cpp @@ -223,6 +223,8 @@ class CUFDeviceFuncTransform clonedFuncOp->setAttr(gpu::GPUDialect::getKernelFuncAttrName(), builder.getUnitAttr()); clonedFuncOp->removeAttr(cuf::getProcAttrName()); + if (auto funcOp = mlir::dyn_cast(clonedFuncOp)) + funcOp.setNested(); } gpuModSymTab.insert(clonedFuncOp); } else { diff --git a/flang/lib/Optimizer/Transforms/FunctionAttr.cpp b/flang/lib/Optimizer/Transforms/FunctionAttr.cpp index fea511cc63a37..3879a807fda2f 100644 --- a/flang/lib/Optimizer/Transforms/FunctionAttr.cpp +++ b/flang/lib/Optimizer/Transforms/FunctionAttr.cpp @@ -87,10 +87,6 @@ void FunctionAttrPass::runOnOperation() { func->setAttr(mlir::LLVM::LLVMFuncOp::getInstrumentFunctionExitAttrName( llvmFuncOpName), mlir::StringAttr::get(context, instrumentFunctionExit)); - if (noInfsFPMath) - func->setAttr( - mlir::LLVM::LLVMFuncOp::getNoInfsFpMathAttrName(llvmFuncOpName), - mlir::BoolAttr::get(context, true)); if (noNaNsFPMath) func->setAttr( mlir::LLVM::LLVMFuncOp::getNoNansFpMathAttrName(llvmFuncOpName), diff --git a/flang/lib/Semantics/check-call.cpp b/flang/lib/Semantics/check-call.cpp index d4f406d1ee27c..f0837e1f2ec61 100644 --- a/flang/lib/Semantics/check-call.cpp +++ b/flang/lib/Semantics/check-call.cpp @@ -986,6 +986,12 @@ static void CheckExplicitDataArg(const characteristics::DummyDataObject &dummy, messages.Say( "If a POINTER or ALLOCATABLE dummy or actual argument is polymorphic, both must be so"_err_en_US); } + } else if ((dummy.ignoreTKR.test(common::IgnoreTKR::Type) || + dummy.ignoreTKR.test(common::IgnoreTKR::Kind)) && + dummy.ignoreTKR.test(common::IgnoreTKR::Contiguous)) { + // Descriptor based dummy args passed with ignore_tkr(tc) or + // ignore_tkr(kc) are allowed to have type and kind differences + checkTypeCompatibility = false; } if (checkTypeCompatibility && !actualIsUnlimited) { if (!actualType.type().IsTkCompatibleWith(dummy.type.type())) { @@ -1058,9 +1064,9 @@ static void CheckExplicitDataArg(const characteristics::DummyDataObject &dummy, // Warn about dubious actual argument association with a TARGET dummy // argument + bool actualIsVariable{evaluate::IsVariable(actual)}; if (dummy.attrs.test(characteristics::DummyDataObject::Attr::Target) && context.ShouldWarn(common::UsageWarning::NonTargetPassedToTarget)) { - bool actualIsVariable{evaluate::IsVariable(actual)}; bool actualIsTemp{ !actualIsVariable || HasVectorSubscript(actual) || actualCoarrayRef}; if (actualIsTemp) { @@ -1084,10 +1090,15 @@ static void CheckExplicitDataArg(const characteristics::DummyDataObject &dummy, !dummy.attrs.test(characteristics::DummyDataObject::Attr::Value) && !FindOpenACCConstructContaining(scope)) { std::optional actualDataAttr, dummyDataAttr; - if (const auto *actualObject{actualLastSymbol - ? actualLastSymbol->detailsIf() - : nullptr}) { - actualDataAttr = actualObject->cudaDataAttr(); + // For a%b%c, the last symbol with a CUDA data attribute wins + if (actualIsVariable) { + for (const Symbol &s : evaluate::GetSymbolVector(actual)) { + if (const auto *object{s.detailsIf()}) { + if (auto cudaAttr{object->cudaDataAttr()}) { + actualDataAttr = *cudaAttr; + } + } + } } dummyDataAttr = dummy.cudaDataAttr; // Treat MANAGED like DEVICE for nonallocatable nonpointer arguments to @@ -1107,9 +1118,10 @@ static void CheckExplicitDataArg(const characteristics::DummyDataObject &dummy, actualDataAttr = common::CUDADataAttr::Device; } // For device procedures, treat actual arguments with VALUE attribute as - // device data; also constant actual arguments. + // device data; also constant actual arguments and the function result. if (!actualDataAttr && - (!actualLastSymbol || IsValue(*actualLastSymbol)) && + (!actualFirstSymbol || IsValue(*actualFirstSymbol) || + IsFunctionResult(*actualFirstSymbol)) && (*procedure.cudaSubprogramAttrs == common::CUDASubprogramAttrs::Device)) { actualDataAttr = common::CUDADataAttr::Device; diff --git a/flang/lib/Semantics/check-coarray.cpp b/flang/lib/Semantics/check-coarray.cpp index 74e2d4e25c7ec..00b97162ff0d4 100644 --- a/flang/lib/Semantics/check-coarray.cpp +++ b/flang/lib/Semantics/check-coarray.cpp @@ -9,6 +9,7 @@ #include "check-coarray.h" #include "definable.h" #include "flang/Common/indirection.h" +#include "flang/Evaluate/check-expression.h" #include "flang/Evaluate/expression.h" #include "flang/Parser/message.h" #include "flang/Parser/parse-tree.h" diff --git a/flang/lib/Semantics/check-declarations.cpp b/flang/lib/Semantics/check-declarations.cpp index b50b71f28f790..b9c807a63638b 100644 --- a/flang/lib/Semantics/check-declarations.cpp +++ b/flang/lib/Semantics/check-declarations.cpp @@ -961,7 +961,10 @@ void CheckHelper::CheckObjectEntity( messages_.Say( "!DIR$ IGNORE_TKR(R) may not apply in an ELEMENTAL procedure"_err_en_US); } - if (IsPassedViaDescriptor(symbol)) { + // Descriptor based dummy args passed with ignore_tkr(c) are allowed + // to have type/kind/rank differences + if (IsPassedViaDescriptor(symbol) && + !ignoreTKR.test(common::IgnoreTKR::Contiguous)) { if (IsAllocatableOrObjectPointer(&symbol) && !ignoreTKR.test(common::IgnoreTKR::Pointer)) { if (inExplicitExternalInterface) { diff --git a/flang/lib/Semantics/expression.cpp b/flang/lib/Semantics/expression.cpp index fef6b4f0470dd..b0235469c9de6 100644 --- a/flang/lib/Semantics/expression.cpp +++ b/flang/lib/Semantics/expression.cpp @@ -2431,6 +2431,14 @@ MaybeExpr ExpressionAnalyzer::CheckStructureConstructor( result.Add(symbol, Expr{ProcedureDesignator{**proc->init()}}); } else if (IsAllocatableOrPointer(symbol)) { result.Add(symbol, Expr{NullPointer{}}); + if (IsPointer(symbol)) { + AttachDeclaration( + Warn(common::LanguageFeature::DefaultStructConstructorNullPointer, + typeName, + "Structure constructor lacks a value for pointer component '%s', NULL() assumed"_warn_en_US, + symbol.name()), + symbol); + } } else { AttachDeclaration( Say(typeName, @@ -5321,94 +5329,10 @@ evaluate::Expr AnalyzeKindSelector( return analyzer.AnalyzeKindSelector(category, selector); } -// NoteUsedSymbols() - -static void NoteUsedSymbol(SemanticsContext &context, const Symbol &symbol) { - const Symbol &root{GetAssociationRoot(symbol)}; - switch (root.owner().kind()) { - case semantics::Scope::Kind::Subprogram: - case semantics::Scope::Kind::MainProgram: - case semantics::Scope::Kind::BlockConstruct: - if ((root.has() || - IsProcedurePointer(root))) { - context.NoteUsedSymbol(root); - if (root.test(Symbol::Flag::CrayPointee)) { - context.NoteUsedSymbol(GetCrayPointer(root)); - } - } - break; - default: - break; - } -} - -template -void NoteUsedSymbolsHelper(SemanticsContext &context, const A &x) { - if (context.ShouldWarn(common::UsageWarning::UnusedVariable)) { - for (const Symbol &symbol : CollectSymbols(x)) { - NoteUsedSymbol(context, symbol); - } - } -} - -void NoteUsedSymbols(SemanticsContext &context, const SomeExpr &expr) { - NoteUsedSymbolsHelper(context, expr); -} - -static bool IsBindingUsedAsProcedure(const SomeExpr &expr) { - if (const auto *pd{std::get_if(&expr.u)}) { - if (const Symbol *symbol{pd->GetSymbol()}) { - return symbol->has(); - } - } - return false; -} - -void NoteUsedSymbols( - SemanticsContext &context, const evaluate::ProcedureRef &call) { - NoteUsedSymbolsHelper(context, call.proc()); - for (const auto &maybeArg : call.arguments()) { - if (maybeArg) { - if (const auto *expr{maybeArg->UnwrapExpr()}) { - if (!IsBindingUsedAsProcedure(*expr)) { - // Ignore procedure bindings being used as actual procedures - // (a local extension). - NoteUsedSymbolsHelper(context, *expr); - } - } - } - } -} - -void NoteUsedSymbols( - SemanticsContext &context, const evaluate::Assignment &assignment) { - if (IsBindingUsedAsProcedure(assignment.rhs)) { - // Don't look at the RHS, we're just using its binding (extension). - NoteUsedSymbolsHelper(context, assignment.lhs); - } else { - NoteUsedSymbolsHelper(context, assignment); - } -} - -void NoteUsedSymbols( - SemanticsContext &context, const parser::TypedExpr &typedExpr) { - if (typedExpr && typedExpr->v) { - NoteUsedSymbols(context, *typedExpr->v); - } -} - void NoteUsedSymbols( - SemanticsContext &context, const parser::TypedCall &typedCall) { - if (typedCall) { - NoteUsedSymbols(context, *typedCall); - } -} - -void NoteUsedSymbols( - SemanticsContext &context, const parser::TypedAssignment &typedAssignment) { - if (typedAssignment && typedAssignment->v) { - NoteUsedSymbols(context, *typedAssignment->v); - } + SemanticsContext &context, const SomeExpr &expr, bool isDefinition) { + context.NoteUsedSymbols( + evaluate::CollectUsedSymbolValues(context, expr, isDefinition)); } ExprChecker::ExprChecker(SemanticsContext &context) : context_{context} {} diff --git a/flang/lib/Semantics/pointer-assignment.cpp b/flang/lib/Semantics/pointer-assignment.cpp index c1c0b28789cab..97179b4030147 100644 --- a/flang/lib/Semantics/pointer-assignment.cpp +++ b/flang/lib/Semantics/pointer-assignment.cpp @@ -60,6 +60,7 @@ class PointerAssignmentChecker { PointerAssignmentChecker &set_isAssumedRank(bool); PointerAssignmentChecker &set_pointerComponentLHS(const Symbol *); PointerAssignmentChecker &set_isRHSPointerActualArgument(bool); + PointerAssignmentChecker &set_ignoreTKR(common::IgnoreTKRSet); bool CheckLeftHandSide(const SomeExpr &); bool Check(const SomeExpr &); @@ -96,6 +97,7 @@ class PointerAssignmentChecker { bool isBoundsRemapping_{false}; bool isAssumedRank_{false}; bool isRHSPointerActualArgument_{false}; + common::IgnoreTKRSet ignoreTKR_; const Symbol *pointerComponentLHS_{nullptr}; }; @@ -141,6 +143,12 @@ PointerAssignmentChecker::set_isRHSPointerActualArgument(bool isPointerActual) { return *this; } +PointerAssignmentChecker &PointerAssignmentChecker::set_ignoreTKR( + common::IgnoreTKRSet ignoreTKR) { + ignoreTKR_ = ignoreTKR; + return *this; +} + bool PointerAssignmentChecker::CharacterizeProcedure() { if (!characterizedProcedure_) { characterizedProcedure_ = true; @@ -354,6 +362,9 @@ bool PointerAssignmentChecker::Check(const evaluate::Designator &d) { msg = "Pointer type must be unlimited polymorphic or non-extensible" " derived type when target is unlimited polymorphic"_err_en_US; } + } else if (ignoreTKR_.test(common::IgnoreTKR::Type) && + ignoreTKR_.test(common::IgnoreTKR::Contiguous)) { + // Don't check for target type mismatch error if we have ignore_tkr(tc) } else if (!lhsType_->type().IsTkLenCompatibleWith(rhsType->type())) { msg = MessageFormattedText{ "Target type %s is not compatible with pointer type %s"_err_en_US, @@ -467,7 +478,10 @@ std::optional PointerAssignmentChecker::CheckRanks( !lhsType_->attrs().test(TypeAndShape::Attr::AssumedRank)) { int lhsRank{lhsType_->Rank()}; int rhsRank{rhs.Rank()}; - if (lhsRank != rhsRank) { + // Turn off rank mismatch error if we have ignore_tkr(rc) + if (lhsRank != rhsRank && + !(ignoreTKR_.test(common::IgnoreTKR::Rank) && + ignoreTKR_.test(common::IgnoreTKR::Contiguous))) { return MessageFormattedText{ "Pointer has rank %d but target has rank %d"_err_en_US, lhsRank, rhsRank}; @@ -609,6 +623,7 @@ bool CheckPointerAssignment(SemanticsContext &context, parser::CharBlock source, .set_isVolatile(lhs.attrs.test(DummyDataObject::Attr::Volatile)) .set_isAssumedRank(isAssumedRank) .set_isRHSPointerActualArgument(isPointerActualArgument) + .set_ignoreTKR(lhs.ignoreTKR) .Check(rhs); } diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp index 13cce518aae94..401d4d825b57e 100644 --- a/flang/lib/Semantics/resolve-directives.cpp +++ b/flang/lib/Semantics/resolve-directives.cpp @@ -409,6 +409,29 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor { explicit OmpAttributeVisitor(SemanticsContext &context) : DirectiveAttributeVisitor(context) {} + static bool HasStaticStorageDuration(const Symbol &symbol) { + auto &ultSym = symbol.GetUltimate(); + // Module-scope variable + return ultSym.owner().kind() == Scope::Kind::Module || + // Data statement variable + ultSym.flags().test(Symbol::Flag::InDataStmt) || + // Save attribute variable + ultSym.attrs().test(Attr::SAVE) || + // Referenced in a common block + ultSym.flags().test(Symbol::Flag::InCommonBlock); + } + + // Recognize symbols that are not created as a part of the OpenMP data- + // sharing processing, and that are declared inside of the construct. + // These symbols are predetermined private, but they shouldn't be marked + // in any special way, because there is nothing to be done for them. + // They are not symbols for which private copies need to be created, + // they are already themselves private. + static bool IsLocalInsideScope(const Symbol &symbol, const Scope &scope) { + return symbol.owner() != scope && scope.Contains(symbol.owner()) && + !HasStaticStorageDuration(symbol); + } + template void Walk(const A &x) { parser::Walk(x, *this); } template bool Pre(const A &) { return true; } template void Post(const A &) {} @@ -704,20 +727,6 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor { } void Post(const parser::OmpDeclareVariantDirective &) { PopContext(); }; - void Post(const parser::OmpObjectList &x) { - // The objects from OMP clauses should have already been resolved, - // except common blocks (the ResolveNamesVisitor does not visit - // parser::Name, those are dealt with as members of other structures). - // Iterate over elements of x, and resolve any common blocks that - // are still unresolved. - for (const parser::OmpObject &obj : x.v) { - auto *name{std::get_if(&obj.u)}; - if (name && !name->symbol) { - Resolve(*name, currScope().MakeCommonBlock(name->source, name->source)); - } - } - } - // 2.15.3 Data-Sharing Attribute Clauses bool Pre(const parser::OmpClause::Inclusive &x) { ResolveOmpObjectList(x.v, Symbol::Flag::OmpInclusiveScan); @@ -2107,6 +2116,9 @@ void OmpAttributeVisitor::ResolveSeqLoopIndexInParallelOrTaskConstruct( break; } } + if (IsLocalInsideScope(*iv.symbol, targetIt->scope)) { + return; + } // If this symbol already has a data-sharing attribute then there is nothing // to do here. if (const Symbol * symbol{iv.symbol}) { @@ -2431,14 +2443,14 @@ void OmpAttributeVisitor::PrivatizeAssociatedLoopIndexAndCheckLoopLevel( } } // go through all the nested do-loops and resolve index variables - const parser::Name *iv{GetLoopIndex(*loop)}; - if (iv) { - if (auto *symbol{ResolveOmp(*iv, ivDSA, currScope())}) { - SetSymbolDSA(*symbol, {Symbol::Flag::OmpPreDetermined, ivDSA}); - iv->symbol = symbol; // adjust the symbol within region - AddToContextObjectWithDSA(*symbol, ivDSA); + if (const parser::Name *iv{GetLoopIndex(*loop)}) { + if (!iv->symbol || !IsLocalInsideScope(*iv->symbol, currScope())) { + if (auto *symbol{ResolveOmp(*iv, ivDSA, currScope())}) { + SetSymbolDSA(*symbol, {Symbol::Flag::OmpPreDetermined, ivDSA}); + iv->symbol = symbol; // adjust the symbol within region + AddToContextObjectWithDSA(*symbol, ivDSA); + } } - const auto &block{std::get(loop->t)}; const auto it{block.begin()}; loop = it != block.end() ? GetDoConstructIf(*it) : nullptr; @@ -2682,20 +2694,6 @@ static bool IsPrivatizable(const Symbol *sym) { misc->kind() != MiscDetails::Kind::ConstructName)); } -static bool IsSymbolStaticStorageDuration(const Symbol &symbol) { - LLVM_DEBUG(llvm::dbgs() << "IsSymbolStaticStorageDuration(" << symbol.name() - << "):\n"); - auto ultSym = symbol.GetUltimate(); - // Module-scope variable - return (ultSym.owner().kind() == Scope::Kind::Module) || - // Data statement variable - (ultSym.flags().test(Symbol::Flag::InDataStmt)) || - // Save attribute variable - (ultSym.attrs().test(Attr::SAVE)) || - // Referenced in a common block - (ultSym.flags().test(Symbol::Flag::InCommonBlock)); -} - static bool IsTargetCaptureImplicitlyFirstprivatizeable(const Symbol &symbol, const Symbol::Flags &dsa, const Symbol::Flags &dataSharingAttributeFlags, const Symbol::Flags &dataMappingAttributeFlags, @@ -2854,7 +2852,9 @@ void OmpAttributeVisitor::CreateImplicitSymbols(const Symbol *symbol) { bool targetDir = llvm::omp::allTargetSet.test(dirContext.directive); bool parallelDir = llvm::omp::topParallelSet.test(dirContext.directive); bool teamsDir = llvm::omp::allTeamsSet.test(dirContext.directive); - bool isStaticStorageDuration = IsSymbolStaticStorageDuration(*symbol); + bool isStaticStorageDuration = HasStaticStorageDuration(*symbol); + LLVM_DEBUG(llvm::dbgs() + << "HasStaticStorageDuration(" << symbol->name() << "):\n"); if (dsa.any()) { if (parallelDir || taskGenDir || teamsDir) { @@ -3008,7 +3008,8 @@ void OmpAttributeVisitor::Post(const parser::Name &name) { auto *symbol{name.symbol}; if (symbol && WithinConstruct()) { - if (IsPrivatizable(symbol) && !IsObjectWithDSA(*symbol)) { + if (IsPrivatizable(symbol) && !IsObjectWithDSA(*symbol) && + !IsLocalInsideScope(*symbol, currScope())) { // TODO: create a separate function to go through the rules for // predetermined, explicitly determined, and implicitly // determined data-sharing attributes (2.15.1.1). @@ -3077,7 +3078,17 @@ void OmpAttributeVisitor::Post(const parser::Name &name) { return; } - CreateImplicitSymbols(symbol); + // We should only create any additional symbols, if the one mentioned + // in the source code was declared outside of the construct. This was + // always the case before Fortran 2008. F2008 introduced the BLOCK + // construct, and allowed local variable declarations. + // In OpenMP local (non-static) variables are always private in a given + // construct, if they are declared inside the construct. In those cases + // we don't need to do anything here (i.e. no flags are needed or + // anything else). + if (!IsLocalInsideScope(*symbol, currScope())) { + CreateImplicitSymbols(symbol); + } } // within OpenMP construct } diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 16b76b72880c9..164a9bedcc393 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -1569,6 +1569,8 @@ void AccVisitor::Post(const parser::OpenACCCombinedConstruct &x) { PopScope(); } class OmpVisitor : public virtual DeclarationVisitor { public: void AddOmpSourceRange(const parser::CharBlock &); + void PushScopeWithSource( + Scope::Kind kind, parser::CharBlock source, Symbol *symbol = nullptr); static bool NeedsScope(const parser::OmpBlockConstruct &); static bool NeedsScope(const parser::OmpClause &); @@ -1592,8 +1594,8 @@ class OmpVisitor : public virtual DeclarationVisitor { Post(static_cast(x)); } - bool Pre(const parser::OpenMPLoopConstruct &) { - PushScope(Scope::Kind::OtherConstruct, nullptr); + bool Pre(const parser::OpenMPLoopConstruct &x) { + PushScopeWithSource(Scope::Kind::OtherConstruct, x.source); return true; } void Post(const parser::OpenMPLoopConstruct &) { PopScope(); } @@ -1616,6 +1618,20 @@ class OmpVisitor : public virtual DeclarationVisitor { bool Pre(const parser::OmpStylizedInstance &); void Post(const parser::OmpStylizedInstance &); + void Post(const parser::OmpObjectList &x) { + // The objects from OMP clauses should have already been resolved, + // except common blocks (the ResolveNamesVisitor does not visit + // parser::Name, those are dealt with as members of other structures). + // Iterate over elements of x, and resolve any common blocks that + // are still unresolved. + for (const parser::OmpObject &obj : x.v) { + auto *name{std::get_if(&obj.u)}; + if (name && !name->symbol) { + Resolve(*name, currScope().MakeCommonBlock(name->source, name->source)); + } + } + } + bool Pre(const parser::OpenMPDeclareMapperConstruct &x) { AddOmpSourceRange(x.source); return true; @@ -1637,8 +1653,8 @@ class OmpVisitor : public virtual DeclarationVisitor { } bool Pre(const parser::OmpMapClause &); - bool Pre(const parser::OpenMPSectionsConstruct &) { - PushScope(Scope::Kind::OtherConstruct, nullptr); + bool Pre(const parser::OpenMPSectionsConstruct &x) { + PushScopeWithSource(Scope::Kind::OtherConstruct, x.source); return true; } void Post(const parser::OpenMPSectionsConstruct &) { PopScope(); } @@ -1744,7 +1760,7 @@ class OmpVisitor : public virtual DeclarationVisitor { } bool Pre(const parser::OmpClause &x) { if (NeedsScope(x)) { - PushScope(Scope::Kind::OtherClause, nullptr); + PushScopeWithSource(Scope::Kind::OtherClause, x.source); } return true; } @@ -1813,9 +1829,15 @@ void OmpVisitor::AddOmpSourceRange(const parser::CharBlock &source) { currScope().AddSourceRange(source); } +void OmpVisitor::PushScopeWithSource( + Scope::Kind kind, parser::CharBlock source, Symbol *symbol) { + PushScope(kind, symbol); + currScope().AddSourceRange(source); +} + bool OmpVisitor::Pre(const parser::OmpBlockConstruct &x) { if (NeedsScope(x)) { - PushScope(Scope::Kind::OtherConstruct, nullptr); + PushScopeWithSource(Scope::Kind::OtherConstruct, x.source); } return true; } diff --git a/flang/lib/Semantics/semantics.cpp b/flang/lib/Semantics/semantics.cpp index 1f23a6c29bbe7..72b36416adda2 100644 --- a/flang/lib/Semantics/semantics.cpp +++ b/flang/lib/Semantics/semantics.cpp @@ -819,6 +819,11 @@ bool SemanticsContext::IsSymbolDefined(const Symbol &symbol) const { void SemanticsContext::NoteUsedSymbol(const Symbol &symbol) { isUsed_.insert(symbol); } +void SemanticsContext::NoteUsedSymbols(const UnorderedSymbolSet &set) { + for (const Symbol &symbol : set) { + NoteUsedSymbol(symbol); + } +} bool SemanticsContext::IsSymbolUsed(const Symbol &symbol) const { return isUsed_.find(symbol) != isUsed_.end(); diff --git a/flang/lib/Semantics/tools.cpp b/flang/lib/Semantics/tools.cpp index baa8e6d7f59a3..7fe44317a198f 100644 --- a/flang/lib/Semantics/tools.cpp +++ b/flang/lib/Semantics/tools.cpp @@ -346,18 +346,6 @@ const Symbol &BypassGeneric(const Symbol &symbol) { return symbol; } -const Symbol &GetCrayPointer(const Symbol &crayPointee) { - const Symbol *found{nullptr}; - const Symbol &ultimate{crayPointee.GetUltimate()}; - for (const auto &[pointee, pointer] : ultimate.owner().crayPointers()) { - if (pointee == ultimate.name()) { - found = &pointer.get(); - break; - } - } - return DEREF(found); -} - bool ExprHasTypeCategory( const SomeExpr &expr, const common::TypeCategory &type) { auto dynamicType{expr.GetType()}; diff --git a/flang/test/Analysis/AliasAnalysis/alias-analysis-cray-pointers.fir b/flang/test/Analysis/AliasAnalysis/alias-analysis-cray-pointers.fir index ef3b12d9c449c..853a2c5ba850d 100644 --- a/flang/test/Analysis/AliasAnalysis/alias-analysis-cray-pointers.fir +++ b/flang/test/Analysis/AliasAnalysis/alias-analysis-cray-pointers.fir @@ -5,40 +5,164 @@ // Fortran source: // subroutine test() -// real :: a, b +// real :: a, b, c // pointer(p, a) // p = loc(b) +// p = loc(c) +// a = 1.0 // end subroutine // CHECK-LABEL: Testing : "_QPtest" +// Legend: +// * 'a' is the descriptor address. +// * 'a.data" is the address of the 'a's data. +// * 'b' is the address of the 'b's data. +// * 'c' is the address of the 'c's data. +// * 'p' is the address of memory holding the raw address +// of the 'b's data (or any other pointee's data) +// * 'raw_ptr_b' is the address of the 'b's data. +// * 'raw_ptr_c' is the address of the 'c's data. + +// TODO: we should report NoAlias here, because +// 'p' is the address of location of the cray pointer value. +// It cannot alias with anything but itself. // CHECK-DAG: p#0 <-> b#0: MayAlias // CHECK-DAG: p#1 <-> b#0: MayAlias // CHECK-DAG: p#0 <-> b#1: MayAlias // CHECK-DAG: p#1 <-> b#1: MayAlias -// CHECK-DAG: p#0 <-> a#0: MayAlias -// CHECK-DAG: p#1 <-> a#0: MayAlias -// CHECK-DAG: b#0 <-> a#0: MayAlias -// CHECK-DAG: b#1 <-> a#0: MayAlias -// CHECK-DAG: p#0 <-> a#1: MayAlias -// CHECK-DAG: p#1 <-> a#1: MayAlias -// CHECK-DAG: b#0 <-> a#1: MayAlias -// CHECK-DAG: b#1 <-> a#1: MayAlias +// CHECK-DAG: p#0 <-> c#0: MayAlias +// CHECK-DAG: p#1 <-> c#0: MayAlias +// CHECK-DAG: p#0 <-> c#1: MayAlias +// CHECK-DAG: p#1 <-> c#1: MayAlias +// CHECK-DAG: p#0 <-> raw_ptr_b#0: MayAlias +// CHECK-DAG: p#1 <-> raw_ptr_b#0: MayAlias +// CHECK-DAG: p#0 <-> raw_ptr_c#0: MayAlias +// CHECK-DAG: p#1 <-> raw_ptr_c#0: MayAlias +// CHECK-DAG: p#0 <-> a.data#0: MayAlias +// CHECK-DAG: p#1 <-> a.data#0: MayAlias + +// The descriptor address does not alias 'p'. +// CHECK-DAG: p#0 <-> a#0: NoAlias +// CHECK-DAG: p#1 <-> a#0: NoAlias +// CHECK-DAG: p#0 <-> a#1: NoAlias +// CHECK-DAG: p#1 <-> a#1: NoAlias + +// 'b's data address and 'c's data address cannot alias. +// CHECK-DAG: b#0 <-> c#0: NoAlias +// CHECK-DAG: b#1 <-> c#0: NoAlias +// CHECK-DAG: b#0 <-> c#1: NoAlias +// CHECK-DAG: b#1 <-> c#1: NoAlias + +// 'b's and 'c's data addresses cannot alias with +// the address of 'a' descriptor. +// CHECK-DAG: b#0 <-> a#0: NoAlias +// CHECK-DAG: b#1 <-> a#0: NoAlias +// CHECK-DAG: c#0 <-> a#0: NoAlias +// CHECK-DAG: c#1 <-> a#0: NoAlias +// CHECK-DAG: b#0 <-> a#1: NoAlias +// CHECK-DAG: b#1 <-> a#1: NoAlias +// CHECK-DAG: c#0 <-> a#1: NoAlias +// CHECK-DAG: c#1 <-> a#1: NoAlias + +// 'b' == 'raw_ptr_b' and 'c' == 'raw_ptr_c' +// CHECK-DAG: b#0 <-> raw_ptr_b#0: MustAlias +// CHECK-DAG: b#1 <-> raw_ptr_b#0: MustAlias +// CHECK-DAG: c#0 <-> raw_ptr_c#0: MustAlias +// CHECK-DAG: c#1 <-> raw_ptr_c#0: MustAlias + +// CHECK-DAG: c#0 <-> raw_ptr_b#0: NoAlias +// CHECK-DAG: c#1 <-> raw_ptr_b#0: NoAlias +// CHECK-DAG: a#0 <-> raw_ptr_b#0: NoAlias +// CHECK-DAG: a#1 <-> raw_ptr_b#0: NoAlias +// CHECK-DAG: b#0 <-> raw_ptr_c#0: NoAlias +// CHECK-DAG: b#1 <-> raw_ptr_c#0: NoAlias +// CHECK-DAG: a#0 <-> raw_ptr_c#0: NoAlias +// CHECK-DAG: a#1 <-> raw_ptr_c#0: NoAlias +// CHECK-DAG: raw_ptr_b#0 <-> raw_ptr_c#0: NoAlias + +// 'a.data' may point to either 'b' or 'c'. +// CHECK-DAG: b#0 <-> a.data#0: MayAlias +// CHECK-DAG: b#1 <-> a.data#0: MayAlias +// CHECK-DAG: c#0 <-> a.data#0: MayAlias +// CHECK-DAG: c#1 <-> a.data#0: MayAlias +// CHECK-DAG: raw_ptr_b#0 <-> a.data#0: MayAlias +// CHECK-DAG: raw_ptr_c#0 <-> a.data#0: MayAlias + +// The descriptor address 'a' does not alias the 'a's data. +// CHECK-DAG: a#0 <-> a.data#0: NoAlias +// CHECK-DAG: a#1 <-> a.data#0: NoAlias // By default, alias analysis assumes that cray pointers do not alias with // non-target data. See flang/docs/Aliasing.md. // DEFAULT-LABEL: Testing : "_QPtest" +// NoAlias is always correct, though we report MayAlias +// under -unsafe-cray-pointers. // DEFAULT-DAG: p#0 <-> b#0: NoAlias // DEFAULT-DAG: p#1 <-> b#0: NoAlias // DEFAULT-DAG: p#0 <-> b#1: NoAlias // DEFAULT-DAG: p#1 <-> b#1: NoAlias +// DEFAULT-DAG: p#0 <-> c#0: NoAlias +// DEFAULT-DAG: p#1 <-> c#0: NoAlias +// DEFAULT-DAG: p#0 <-> c#1: NoAlias +// DEFAULT-DAG: p#1 <-> c#1: NoAlias +// DEFAULT-DAG: p#0 <-> raw_ptr_b#0: NoAlias +// DEFAULT-DAG: p#1 <-> raw_ptr_b#0: NoAlias +// DEFAULT-DAG: p#0 <-> raw_ptr_c#0: NoAlias +// DEFAULT-DAG: p#1 <-> raw_ptr_c#0: NoAlias +// DEFAULT-DAG: p#0 <-> a.data#0: NoAlias +// DEFAULT-DAG: p#1 <-> a.data#0: NoAlias + +// Same as with -unsafe-cray-pointers. // DEFAULT-DAG: p#0 <-> a#0: NoAlias // DEFAULT-DAG: p#1 <-> a#0: NoAlias -// DEFAULT-DAG: b#0 <-> a#0: NoAlias -// DEFAULT-DAG: b#1 <-> a#0: NoAlias // DEFAULT-DAG: p#0 <-> a#1: NoAlias // DEFAULT-DAG: p#1 <-> a#1: NoAlias + +// Same as with -unsafe-cray-pointers. +// DEFAULT-DAG: b#0 <-> c#0: NoAlias +// DEFAULT-DAG: b#1 <-> c#0: NoAlias +// DEFAULT-DAG: b#0 <-> c#1: NoAlias +// DEFAULT-DAG: b#1 <-> c#1: NoAlias + +// Same as with -unsafe-cray-pointers. +// DEFAULT-DAG: b#0 <-> a#0: NoAlias +// DEFAULT-DAG: b#1 <-> a#0: NoAlias +// DEFAULT-DAG: c#0 <-> a#0: NoAlias +// DEFAULT-DAG: c#1 <-> a#0: NoAlias // DEFAULT-DAG: b#0 <-> a#1: NoAlias // DEFAULT-DAG: b#1 <-> a#1: NoAlias +// DEFAULT-DAG: c#0 <-> a#1: NoAlias +// DEFAULT-DAG: c#1 <-> a#1: NoAlias + +// Same as with -unsafe-cray-pointers. +// DEFAULT-DAG: b#0 <-> raw_ptr_b#0: MustAlias +// DEFAULT-DAG: b#1 <-> raw_ptr_b#0: MustAlias +// DEFAULT-DAG: c#0 <-> raw_ptr_c#0: MustAlias +// DEFAULT-DAG: c#1 <-> raw_ptr_c#0: MustAlias + +// Same as with -unsafe-cray-pointers. +// DEFAULT-DAG: c#0 <-> raw_ptr_b#0: NoAlias +// DEFAULT-DAG: c#1 <-> raw_ptr_b#0: NoAlias +// DEFAULT-DAG: a#0 <-> raw_ptr_b#0: NoAlias +// DEFAULT-DAG: a#1 <-> raw_ptr_b#0: NoAlias +// DEFAULT-DAG: b#0 <-> raw_ptr_c#0: NoAlias +// DEFAULT-DAG: b#1 <-> raw_ptr_c#0: NoAlias +// DEFAULT-DAG: a#0 <-> raw_ptr_c#0: NoAlias +// DEFAULT-DAG: a#1 <-> raw_ptr_c#0: NoAlias +// DEFAULT-DAG: raw_ptr_b#0 <-> raw_ptr_c#0: NoAlias + +// This is the functional difference with -unsafe-cray-pointers. +// The safe assumption is MayAlias. +// DEFAULT-DAG: b#0 <-> a.data#0: NoAlias +// DEFAULT-DAG: b#1 <-> a.data#0: NoAlias +// DEFAULT-DAG: c#0 <-> a.data#0: NoAlias +// DEFAULT-DAG: c#1 <-> a.data#0: NoAlias +// DEFAULT-DAG: raw_ptr_b#0 <-> a.data#0: NoAlias +// DEFAULT-DAG: raw_ptr_c#0 <-> a.data#0: NoAlias + +// Same as with -unsafe-cray-pointers. +// DEFAULT-DAG: a#0 <-> a.data#0: NoAlias +// DEFAULT-DAG: a#1 <-> a.data#0: NoAlias func.func @_QPtest() { %0 = fir.alloca !fir.box> @@ -47,14 +171,26 @@ func.func @_QPtest() { %3:2 = hlfir.declare %2 {test.ptr = "p", fortran_attrs = #fir.var_attrs, uniq_name = "_QFtestEp"} : (!fir.ref) -> (!fir.ref, !fir.ref) %4 = fir.alloca f32 {bindc_name = "b", uniq_name = "_QFtestEb"} %5:2 = hlfir.declare %4 {test.ptr = "b", uniq_name = "_QFtestEb"} : (!fir.ref) -> (!fir.ref, !fir.ref) - %6:2 = hlfir.declare %0 {test.ptr = "a", fortran_attrs = #fir.var_attrs, uniq_name = "_QFtestEa"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) - %7 = fir.zero_bits !fir.ptr - %8 = fir.embox %7 : (!fir.ptr) -> !fir.box> - fir.store %8 to %6#0 : !fir.ref>> - %9 = fir.embox %5#0 : (!fir.ref) -> !fir.box - %10 = fir.box_addr %9 : (!fir.box) -> !fir.ref - %11 = fir.convert %10 : (!fir.ref) -> i64 - hlfir.assign %11 to %3#0 : i64, !fir.ref + %6 = fir.alloca f32 {bindc_name = "c", uniq_name = "_QFtestEc"} + %7:2 = hlfir.declare %6 {test.ptr = "c", uniq_name = "_QFtestEc"} : (!fir.ref) -> (!fir.ref, !fir.ref) + %8:2 = hlfir.declare %0 {test.ptr = "a", fortran_attrs = #fir.var_attrs, uniq_name = "_QFtestEa"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) + %9 = fir.zero_bits !fir.ptr + %10 = fir.embox %9 : (!fir.ptr) -> !fir.box> + fir.store %10 to %8#0 : !fir.ref>> + %11 = fir.embox %5#0 : (!fir.ref) -> !fir.box + %12 = fir.box_addr %11 {test.ptr = "raw_ptr_b"} : (!fir.box) -> !fir.ref + %13 = fir.convert %12 : (!fir.ref) -> i64 + hlfir.assign %13 to %3#0 : i64, !fir.ref + %14 = fir.embox %7#0 : (!fir.ref) -> !fir.box + %15 = fir.box_addr %14 {test.ptr = "raw_ptr_c"} : (!fir.box) -> !fir.ref + %16 = fir.convert %15 : (!fir.ref) -> i64 + hlfir.assign %16 to %3#0 : i64, !fir.ref + %cst = arith.constant 1.000000e+00 : f32 + // There should be _FortranAPointerAssociateScalar call here, but + // we skip it for the test. + %21 = fir.load %8#0 : !fir.ref>> + %22 = fir.box_addr %21 {test.ptr = "a.data"} : (!fir.box>) -> !fir.ptr + hlfir.assign %cst to %22 : f32, !fir.ptr return } diff --git a/flang/test/Analysis/AliasAnalysis/load-ptr-designate.fir b/flang/test/Analysis/AliasAnalysis/load-ptr-designate.fir index 6b9ff25f590f3..634f6f4dbcee5 100644 --- a/flang/test/Analysis/AliasAnalysis/load-ptr-designate.fir +++ b/flang/test/Analysis/AliasAnalysis/load-ptr-designate.fir @@ -236,12 +236,10 @@ func.func @_QPtest.fir() { // CHECK-DAG: obj%p0.tgt.fir#0 <-> t_obj%alloc.tgt.fir#0: MayAlias // The address in an allocatable cannot alias the address of that allocatable. -// TODO: Thus, we expect all cases below to be NoAlias. However, target dummy -// args are currently indiscrimnately analyzed as MayAlias. // CHECK-DAG: obj%alloc#0 <-> obj%alloc.tgt#0: NoAlias -// CHECK-DAG: t_obj%alloc#0 <-> t_obj%alloc.tgt#0: MayAlias +// CHECK-DAG: t_obj%alloc#0 <-> t_obj%alloc.tgt#0: NoAlias // CHECK-DAG: obj%alloc.fir#0 <-> obj%alloc.tgt.fir#0: NoAlias -// CHECK-DAG: t_obj%alloc.fir#0 <-> t_obj%alloc.tgt.fir#0: MayAlias +// CHECK-DAG: t_obj%alloc.fir#0 <-> t_obj%alloc.tgt.fir#0: NoAlias // The address of a composite aliases the address of any component but not the // address in a pointer or allocatable component. diff --git a/flang/test/Analysis/AliasAnalysis/ptr-component.fir b/flang/test/Analysis/AliasAnalysis/ptr-component.fir index 83cc4d36a7395..455efb5c2a0ba 100644 --- a/flang/test/Analysis/AliasAnalysis/ptr-component.fir +++ b/flang/test/Analysis/AliasAnalysis/ptr-component.fir @@ -478,13 +478,14 @@ func.func @_QMmPtest.fir(%arg0: !fir.ref>> {fir.bindc_nam // CHECK-DAG: argp.fir#0 <-> arg%p.fir#0: MayAlias // CHECK-DAG: argp.fir#0 <-> arg%i.fir#0: NoAlias // -// TODO: Shouldn't these be NoAlias? However, argp.tgt is currently handled as -// Indirect. +// TODO: Shouldn't these all be NoAlias? +// However, argp.tgt is currently handled as Indirect, and we only +// can disambiguate descriptor and data addresses. // CHECK-DAG: argp.tgt#0 <-> arg#0: MayAlias -// CHECK-DAG: argp.tgt#0 <-> arg%p#0: MayAlias +// CHECK-DAG: argp.tgt#0 <-> arg%p#0: NoAlias // CHECK-DAG: argp.tgt#0 <-> arg%i#0: MayAlias // CHECK-DAG: argp.tgt.fir#0 <-> arg.fir#0: MayAlias -// CHECK-DAG: argp.tgt.fir#0 <-> arg%p.fir#0: MayAlias +// CHECK-DAG: argp.tgt.fir#0 <-> arg%p.fir#0: NoAlias // CHECK-DAG: argp.tgt.fir#0 <-> arg%i.fir#0: MayAlias // // CHECK-DAG: arga#0 <-> arg#0: NoAlias @@ -501,13 +502,14 @@ func.func @_QMmPtest.fir(%arg0: !fir.ref>> {fir.bindc_nam // CHECK-DAG: argp.fir#0 <-> glob%p.fir#0: MayAlias // CHECK-DAG: argp.fir#0 <-> glob%i.fir#0: NoAlias // -// TODO: Shouldn't these be NoAlias? However, argp.tgt is currently handled as -// Indirect. +// TODO: Shouldn't these all be NoAlias? +// However, argp.tgt is currently handled as Indirect, and we only +// can disambiguate descriptor and data addresses. // CHECK-DAG: argp.tgt#0 <-> glob#0: MayAlias -// CHECK-DAG: argp.tgt#0 <-> glob%p#0: MayAlias +// CHECK-DAG: argp.tgt#0 <-> glob%p#0: NoAlias // CHECK-DAG: argp.tgt#0 <-> glob%i#0: MayAlias // CHECK-DAG: argp.tgt.fir#0 <-> glob.fir#0: MayAlias -// CHECK-DAG: argp.tgt.fir#0 <-> glob%p.fir#0: MayAlias +// CHECK-DAG: argp.tgt.fir#0 <-> glob%p.fir#0: NoAlias // CHECK-DAG: argp.tgt.fir#0 <-> glob%i.fir#0: MayAlias // // CHECK-DAG: arga#0 <-> glob#0: NoAlias @@ -524,13 +526,14 @@ func.func @_QMmPtest.fir(%arg0: !fir.ref>> {fir.bindc_nam // CHECK-DAG: argp.fir#0 <-> loc%p.fir#0: NoAlias // CHECK-DAG: argp.fir#0 <-> loc%i.fir#0: NoAlias // -// TODO: Shouldn't these be NoAlias? However, argp.tgt is currently handled as -// Indirect. +// TODO: Shouldn't these all be NoAlias? +// However, argp.tgt is currently handled as Indirect, and we only +// can disambiguate descriptor and data addresses. // CHECK-DAG: argp.tgt#0 <-> loc#0: MayAlias -// CHECK-DAG: argp.tgt#0 <-> loc%p#0: MayAlias +// CHECK-DAG: argp.tgt#0 <-> loc%p#0: NoAlias // CHECK-DAG: argp.tgt#0 <-> loc%i#0: MayAlias // CHECK-DAG: argp.tgt.fir#0 <-> loc.fir#0: MayAlias -// CHECK-DAG: argp.tgt.fir#0 <-> loc%p.fir#0: MayAlias +// CHECK-DAG: argp.tgt.fir#0 <-> loc%p.fir#0: NoAlias // CHECK-DAG: argp.tgt.fir#0 <-> loc%i.fir#0: MayAlias // // CHECK-DAG: arga#0 <-> loc#0: NoAlias diff --git a/flang/test/Driver/asm-error-fix.s b/flang/test/Driver/asm-error-fix.s new file mode 100644 index 0000000000000..725366de84eda --- /dev/null +++ b/flang/test/Driver/asm-error-fix.s @@ -0,0 +1,9 @@ +! Test that flang rejects assembly files as input + +! RUN: not %flang -c %s 2>&1 | FileCheck %s + +! CHECK: error: flang does not support assembly files as input + +.globl foo +foo: + ret diff --git a/flang/test/Driver/func-attr-fast-math.f90 b/flang/test/Driver/func-attr-fast-math.f90 index 3af641ea2db26..b8f8a0e1c8a63 100644 --- a/flang/test/Driver/func-attr-fast-math.f90 +++ b/flang/test/Driver/func-attr-fast-math.f90 @@ -11,8 +11,8 @@ end subroutine func ! CHECK-OFAST-LABEL: define void @func_() local_unnamed_addr ! CHECK-OFAST-SAME: #[[ATTRS:[0-9]+]] -! CHECK-OFAST: attributes #[[ATTRS]] = { {{.*}}"no-infs-fp-math"="true" {{.*}}"no-nans-fp-math"="true" {{.*}}"no-signed-zeros-fp-math"="true"{{.*}} } +! CHECK-OFAST: attributes #[[ATTRS]] = { {{.*}}"no-nans-fp-math"="true" {{.*}}"no-signed-zeros-fp-math"="true"{{.*}} } ! CHECK-FFAST-MATH-LABEL: define void @func_() local_unnamed_addr ! CHECK-FFAST-MATH-SAME: #[[ATTRS:[0-9]+]] -! CHECK-FFAST-MATH: attributes #[[ATTRS]] = { {{.*}}"no-infs-fp-math"="true" {{.*}}"no-nans-fp-math"="true" {{.*}}"no-signed-zeros-fp-math"="true"{{.*}} } +! CHECK-FFAST-MATH: attributes #[[ATTRS]] = { {{.*}}"no-nans-fp-math"="true" {{.*}}"no-signed-zeros-fp-math"="true"{{.*}} } diff --git a/flang/test/Fir/CUDA/cuda-device-func-transform.mlir b/flang/test/Fir/CUDA/cuda-device-func-transform.mlir index 1ce21aeecffe5..cc183f0144e82 100644 --- a/flang/test/Fir/CUDA/cuda-device-func-transform.mlir +++ b/flang/test/Fir/CUDA/cuda-device-func-transform.mlir @@ -45,7 +45,7 @@ func.func private @_QMmod1Psub1(!fir.ref> {cuf.data_attr = #c // CHECK: gpu.func @_QPsub_host_device1() -// CHECK: func.func private @_QMmod1Psub1(!fir.ref> {cuf.data_attr = #cuf.cuda}) attributes {gpu.kernel} +// CHECK: func.func nested @_QMmod1Psub1(!fir.ref> {cuf.data_attr = #cuf.cuda}) attributes {gpu.kernel} // CHECK: func.func @_QPsub_global1() attributes {cuf.proc_attr = #cuf.cuda_proc} // CHECK-NEXT: return diff --git a/flang/test/Lower/HLFIR/function-return-as-expr.f90 b/flang/test/Lower/HLFIR/function-return-as-expr.f90 index 3b43b6e261db1..3fafc47833d6c 100644 --- a/flang/test/Lower/HLFIR/function-return-as-expr.f90 +++ b/flang/test/Lower/HLFIR/function-return-as-expr.f90 @@ -37,9 +37,10 @@ end subroutine test2 ! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref>>> ! CHECK: %[[VAL_11:.*]] = fir.box_elesize %[[VAL_10]] : (!fir.box>>) -> index ! CHECK: %[[VAL_12:.*]] = fir.emboxchar %[[VAL_9]], %[[VAL_11]] : (!fir.heap>, index) -> !fir.boxchar<1> -! CHECK: %[[VAL_13:.*]] = arith.constant false +! CHECK: %[[VAL_13:.*]] = arith.constant true ! CHECK: %[[VAL_14:.*]] = hlfir.as_expr %[[VAL_12]] move %[[VAL_13]] : (!fir.boxchar<1>, i1) -> !hlfir.expr> ! CHECK: hlfir.assign %[[VAL_14]] to %{{.*}}#0 realloc : !hlfir.expr>, !fir.ref>>> +! CHECK: hlfir.destroy %[[VAL_14]] subroutine test3 character(len=:), allocatable :: c @@ -53,9 +54,10 @@ end subroutine test3 ! CHECK: %[[VAL_13:.*]]:2 = hlfir.declare %{{.*}} typeparams %{{.*}} {uniq_name = ".tmp.func_result"} : (!fir.ref>>>, index) -> (!fir.ref>>>, !fir.ref>>>) ! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_13]]#0 : !fir.ref>>> ! CHECK: %[[VAL_15:.*]] = fir.box_addr %[[VAL_14]] : (!fir.box>>) -> !fir.heap> -! CHECK: %[[VAL_16:.*]] = arith.constant false +! CHECK: %[[VAL_16:.*]] = arith.constant true ! CHECK: %[[VAL_17:.*]] = hlfir.as_expr %[[VAL_15]] move %[[VAL_16]] : (!fir.heap>, i1) -> !hlfir.expr> ! CHECK: hlfir.assign %[[VAL_17]] to %{{.*}}#0 realloc : !hlfir.expr>, !fir.ref>>> +! CHECK: hlfir.destroy %[[VAL_17]] subroutine test4 class(*), allocatable :: p @@ -69,7 +71,8 @@ end subroutine test4 ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_0:.*]] : !fir.ref>> ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = ".tmp.func_result"} : (!fir.class>) -> (!fir.class, !fir.class) ! CHECK: hlfir.assign %[[VAL_7]]#0 to %{{.*}}#0 realloc : !fir.class, !fir.ref>> -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>>) -> !fir.box +! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_8]] : (!fir.class>) -> !fir.box ! CHECK: fir.call @_FortranADestroy(%[[VAL_10]]) fastmath : (!fir.box) -> () subroutine test4b @@ -84,7 +87,8 @@ end subroutine test4b ! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_0:.*]] : !fir.ref>>> ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = ".tmp.func_result"} : (!fir.class>>) -> (!fir.class>, !fir.class>) ! CHECK: hlfir.assign %[[VAL_7]]#0 to %{{.*}}#0 realloc : !fir.class>, !fir.ref>>> -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>>>) -> !fir.box +! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> +! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_8]] : (!fir.class>>) -> !fir.box ! CHECK: fir.call @_FortranADestroy(%[[VAL_10]]) fastmath : (!fir.box) -> () subroutine test5 diff --git a/flang/test/Lower/HLFIR/function-return-destroy.f90 b/flang/test/Lower/HLFIR/function-return-destroy.f90 index 5bd014981c128..ca65a6e1ec39c 100644 --- a/flang/test/Lower/HLFIR/function-return-destroy.f90 +++ b/flang/test/Lower/HLFIR/function-return-destroy.f90 @@ -59,9 +59,11 @@ end function ret_type_t1a end subroutine test1a ! CHECK-LABEL: func.func @_QPtest1a() { ! CHECK-NOT: fir.call{{.*}}Destroy -! CHECK: fir.if %{{.*}} { -! CHECK-NEXT: fir.freemem %{{.*}} : !fir.heap> +! CHECK-NOT: fir.freemem +! CHECK: hlfir.as_expr %{{.*}} move %true ! CHECK-NOT: fir.call{{.*}}Destroy +! CHECK-NOT: fir.freemem +! CHECK: hlfir.destroy ! CHECK: fir.if %{{.*}} { ! CHECK: fir.call @_FortranAAllocatableDeallocate({{.*}}) fastmath : (!fir.ref>, i1, !fir.box, !fir.ref, i32) -> i32 ! CHECK-NOT: fir.call{{.*}}Destroy diff --git a/flang/test/Lower/HLFIR/where.f90 b/flang/test/Lower/HLFIR/where.f90 index dea344214928a..0081d7751239b 100644 --- a/flang/test/Lower/HLFIR/where.f90 +++ b/flang/test/Lower/HLFIR/where.f90 @@ -80,10 +80,10 @@ subroutine where_cleanup() ! CHECK: %[[VAL_6:.*]] = fir.call @_QPreturn_temporary_mask() fastmath : () -> !fir.box>>> ! CHECK: fir.save_result %[[VAL_6]] to %[[VAL_7]]#0 : !fir.box>>>, !fir.ref>>>> ! CHECK: %[[deref:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref>>>> -! CHECK: %[[MustFree:.*]] = arith.constant false +! CHECK: %[[MustFree:.*]] = arith.constant true ! CHECK: %[[ResTemp:.*]] = hlfir.as_expr %[[deref]] move %[[MustFree]] : (!fir.box>>>, i1) -> !hlfir.expr> ! CHECK: hlfir.yield %[[ResTemp]] : !hlfir.expr> cleanup { -! CHECK: fir.freemem +! CHECK: hlfir.destroy %[[ResTemp]] ! CHECK: } ! CHECK: } do { ! CHECK: hlfir.region_assign { @@ -91,10 +91,10 @@ subroutine where_cleanup() ! CHECK: %[[VAL_14:.*]] = fir.call @_QPreturn_temporary_array() fastmath : () -> !fir.box>> ! CHECK: fir.save_result %[[VAL_14]] to %[[VAL_15]]#0 : !fir.box>>, !fir.ref>>> ! CHECK: %[[deref:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>>> -! CHECK: %[[MustFree:.*]] = arith.constant false +! CHECK: %[[MustFree:.*]] = arith.constant true ! CHECK: %[[ResTemp:.*]] = hlfir.as_expr %[[deref]] move %[[MustFree]] : (!fir.box>>, i1) -> !hlfir.expr ! CHECK: hlfir.yield %[[ResTemp]] : !hlfir.expr cleanup { -! CHECK: fir.freemem +! CHECK: hlfir.destroy %[[ResTemp]] ! CHECK: } ! CHECK: } to { ! CHECK: hlfir.yield %[[VAL_5]]#0 : !fir.ref> diff --git a/flang/test/Lower/OpenACC/acc-cache.f90 b/flang/test/Lower/OpenACC/acc-cache.f90 index 22dd0a84aee8a..36874d3c21cdb 100644 --- a/flang/test/Lower/OpenACC/acc-cache.f90 +++ b/flang/test/Lower/OpenACC/acc-cache.f90 @@ -638,6 +638,110 @@ subroutine test_cache_nested_derived_type() ! CHECK: acc.yield end subroutine +! Test cache with allocatable component in combined construct +! CHECK-LABEL: func.func @_QPtest_cache_combined_allocatable( +subroutine test_cache_combined_allocatable(data, C, M) + type :: dt + real, dimension(:), allocatable :: A + end type + + type(dt), intent(inout) :: data + real, dimension(:), intent(out) :: C + integer, intent(in) :: M + integer :: i + + !$acc parallel loop gang vector copyin(data, data%A(-3:M+4)) copyout(C(1:M)) + do i = 1, M + !$acc cache(data%A(i-4:i+4)) + C(i) = data%A(i) + end do + +! CHECK: acc.parallel {{.*}} { +! CHECK: acc.loop +! CHECK: acc.cache varPtr(%{{.*}}) bounds(%{{.*}}) -> !fir.ref>>> {name = "data%a(i-4_4:i+4_4)", structured = false} +! CHECK: hlfir.declare %{{.*}} {{{.*}}uniq_name = "data%a(i-4_4:i+4_4)"} +! CHECK: acc.yield +end subroutine + +! Test cache with copy of whole struct (not explicit component copyin) +! CHECK-LABEL: func.func @_QPtest_cache_parallel_copy_struct( +subroutine test_cache_parallel_copy_struct(data, M) + type :: dt + real, dimension(:), allocatable :: A + end type + + type(dt), intent(inout) :: data + integer, intent(in) :: M + real :: r + integer :: i + + !$acc parallel loop copy(data) + do i = 1, M + !$acc cache(data%A(i)) + r = data%A(i) + end do + +! CHECK: acc.parallel {{.*}} { +! CHECK: acc.loop +! CHECK: acc.cache varPtr(%{{.*}}) bounds(%{{.*}}) -> !fir.ref>>> {name = "data%a(i)", structured = false} +! CHECK: hlfir.declare %{{.*}} {{{.*}}uniq_name = "data%a(i)"} +! CHECK: acc.yield +end subroutine + +! Test cache with nested derived type in parallel loop with copyin +! CHECK-LABEL: func.func @_QPtest_cache_nested_parallel( +subroutine test_cache_nested_parallel(obj, N) + type :: inner + real, dimension(:), allocatable :: arr + end type + + type :: outer + type(inner) :: in + end type + + type(outer), intent(inout) :: obj + integer, intent(in) :: N + real :: r + integer :: i + + !$acc parallel loop copyin(obj%in%arr(1:N)) + do i = 1, N + !$acc cache(obj%in%arr(i)) + r = obj%in%arr(i) + end do + +! CHECK: acc.parallel {{.*}} { +! CHECK: acc.loop +! CHECK: acc.cache varPtr(%{{.*}}) bounds(%{{.*}}) -> !fir.ref>>> {name = "obj%in%arr(i)", structured = false} +! CHECK: hlfir.declare %{{.*}} {{{.*}}uniq_name = "obj%in%arr(i)"} +! CHECK: acc.yield +end subroutine + +! Test cache with explicit shape component in parallel loop with copyin +! CHECK-LABEL: func.func @_QPtest_cache_explicit_shape_comp( +subroutine test_cache_explicit_shape_comp(data, C, M) + type :: dt + real, dimension(10) :: A + end type + + type(dt), intent(inout) :: data + real, dimension(:), intent(out) :: C + integer, intent(in) :: M + integer :: i + + !$acc parallel loop gang vector copyin(data, data%A(1:M)) copyout(C(1:M)) + do i = 1, M + !$acc cache(data%A(i:i+4)) + C(i) = data%A(i) + end do + +! CHECK: acc.parallel {{.*}} { +! CHECK: acc.loop +! CHECK: acc.cache varPtr(%{{.*}}) bounds(%{{.*}}) -> !fir.ref> {name = "data%a(i:i+4_4)", structured = false} +! CHECK: hlfir.declare %{{.*}}(%{{.*}}) {uniq_name = "data%a(i:i+4_4)"} +! CHECK: acc.yield +end subroutine + ! Test cache with temporary in designator bounds - verifies local statement context ! doesn't cause issues with temporary cleanup ! CHECK-LABEL: func.func @_QPtest_cache_temp_in_designator( diff --git a/flang/test/Lower/OpenACC/acc-no-create-array-section.f90 b/flang/test/Lower/OpenACC/acc-no-create-array-section.f90 new file mode 100644 index 0000000000000..3097eccc8cbee --- /dev/null +++ b/flang/test/Lower/OpenACC/acc-no-create-array-section.f90 @@ -0,0 +1,21 @@ +! This test checks lowering of OpenACC no_create with an array section. + +! RUN: bbc -fopenacc -emit-hlfir %s -o - | FileCheck %s + +subroutine foo(n) + real :: a(n) + !$acc parallel no_create(a(11:20)) + call bar(a) + !$acc end parallel +end subroutine +! CHECK-LABEL: func.func @_QPfoo( +! CHECK: %[[SHAPE_0:.*]] = fir.shape +! CHECK: %[[BOUNDS_0:.*]] = acc.bounds +! CHECK: %[[NOCREATE_0:.*]] = acc.nocreate var(%{{.*}} : !fir.box>) bounds(%[[BOUNDS_0]]) -> !fir.box> {name = "a(11:20)"} +! CHECK: acc.parallel dataOperands(%[[NOCREATE_0]] : !fir.box>) { +! CHECK: %[[BOX_ADDR_0:.*]] = fir.box_addr %[[NOCREATE_0]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[DECLARE_2:.*]]:2 = hlfir.declare %[[BOX_ADDR_0]](%[[SHAPE_0]]) {uniq_name = "_QFfooEa"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: fir.call @_QPbar(%[[DECLARE_2]]#1) fastmath : (!fir.ref>) -> () +! CHECK: acc.yield +! CHECK: } +! CHECK: acc.delete accVar(%[[NOCREATE_0]] : !fir.box>) bounds(%[[BOUNDS_0]]) {dataClause = #acc, name = "a(11:20)"} diff --git a/flang/test/Lower/OpenMP/Todo/affinity-clause.f90 b/flang/test/Lower/OpenMP/Todo/affinity-clause.f90 index 3459dd219e425..6be477229286a 100644 --- a/flang/test/Lower/OpenMP/Todo/affinity-clause.f90 +++ b/flang/test/Lower/OpenMP/Todo/affinity-clause.f90 @@ -1,10 +1,10 @@ !RUN: %not_todo_cmd bbc -emit-hlfir -fopenmp -fopenmp-version=50 -o - %s 2>&1 | FileCheck %s !RUN: %not_todo_cmd %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=50 -o - %s 2>&1 | FileCheck %s -!CHECK: not yet implemented: Unhandled clause AFFINITY in TASK construct +!CHECK: Support for iterator modifiers is not implemented yet subroutine f00(x) integer :: x(10) -!$omp task affinity(x) +!$omp task affinity(iterator(i = 1:10) : x(i)) x = x + 1 !$omp end task end diff --git a/flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90 b/flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90 new file mode 100644 index 0000000000000..e4931018b07ec --- /dev/null +++ b/flang/test/Lower/OpenMP/Todo/multiple-types-declare_reduction.f90 @@ -0,0 +1,51 @@ +! Test OpenMP declare reduction with integer and real types. +! This test verifies correct lowering of user-defined reductions +! to HLFIR and their use in OpenMP parallel loops. + +! RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s + +program main + implicit none + integer :: i, isum + real :: rsum + + !$omp declare reduction(myred: integer, real : & + !$omp omp_out = omp_out + omp_in) initializer(omp_priv = 0) + + isum = 0 + rsum = 0.0 + + !$omp parallel do reduction(myred:isum) + do i = 1, 3 + isum = isum + i + end do + + !$omp parallel do reduction(myred:rsum) + do i = 1, 3 + rsum = rsum + real(i) + end do + + print *, isum, rsum +end program main + +! Verify declare reduction is created for integer +! CHECK-LABEL: omp.declare_reduction @myred : i32 +! CHECK: init { +! CHECK: arith.constant 0 : i32 +! CHECK: omp.yield + +! Verify integer combiner uses addi +! CHECK: combiner { +! CHECK: arith.addi +! CHECK: omp.yield + +! Verify reduction is used in first parallel loop (integer) +! CHECK: omp.parallel +! CHECK: omp.wsloop +! CHECK-SAME: reduction(@myred + +! Verify reduction is used in second parallel loop (real) +! CHECK: omp.parallel +! CHECK: omp.wsloop +! CHECK-SAME: reduction(@myred +! CHECK: arith.addf diff --git a/flang/test/Lower/OpenMP/task-affinity.f90 b/flang/test/Lower/OpenMP/task-affinity.f90 new file mode 100644 index 0000000000000..66254e48e9b8e --- /dev/null +++ b/flang/test/Lower/OpenMP/task-affinity.f90 @@ -0,0 +1,111 @@ +! RUN: %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=52 -o - %s | FileCheck %s + +! scalar element locator +subroutine omp_task_affinity_elem() + implicit none + integer, parameter :: n = 100 + integer :: a(n) + + !$omp parallel + !$omp single + !$omp task affinity(a(1)) + a(1) = 1 + !$omp end task + !$omp end single + !$omp end parallel +end subroutine omp_task_affinity_elem + +! CHECK-LABEL: func.func @_QPomp_task_affinity_elem() +! CHECK: %[[A1:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFomp_task_affinity_elemEa"} +! CHECK: omp.parallel { +! CHECK: omp.single { +! CHECK: omp.task affinity(%[[A1]]#0 : !fir.ref>) { +! CHECK: omp.terminator +! CHECK: } +! CHECK: omp.terminator +! CHECK: } +! CHECK: return + +! array section locator +subroutine omp_task_affinity_array_section() + implicit none + integer, parameter :: n = 100 + integer :: a(n) + integer :: i + + !$omp parallel + !$omp single + !$omp task affinity(a(2:50)) private(i) + do i = 2, 50 + a(i) = i + end do + !$omp end task + !$omp end single + !$omp end parallel +end subroutine omp_task_affinity_array_section + +! CHECK-LABEL: func.func @_QPomp_task_affinity_array_section() +! CHECK: %[[A2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFomp_task_affinity_array_sectionEa"} +! CHECK: %[[I2:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFomp_task_affinity_array_sectionEi"} +! CHECK: omp.parallel { +! CHECK: omp.single { +! CHECK: omp.task affinity(%[[A2]]#0 : !fir.ref>) private({{.*}} %[[I2]]#0 -> %{{.*}} : !fir.ref) { +! CHECK: omp.terminator +! CHECK: } +! CHECK: omp.terminator +! CHECK: } +! CHECK: return + +! scalar variable locator +subroutine omp_task_affinity_scalar() + implicit none + integer :: s + s = 7 + + !$omp parallel + !$omp single + !$omp task affinity(s) + s = s + 1 + !$omp end task + !$omp end single + !$omp end parallel +end subroutine omp_task_affinity_scalar + +! CHECK-LABEL: func.func @_QPomp_task_affinity_scalar() +! CHECK: %[[S3:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFomp_task_affinity_scalarEs"} +! CHECK: omp.parallel { +! CHECK: omp.single { +! CHECK: omp.task affinity(%[[S3]]#0 : !fir.ref) { +! CHECK: omp.terminator +! CHECK: } +! CHECK: omp.terminator +! CHECK: } +! CHECK: return + +! multiple locators +subroutine omp_task_affinity_multi() + implicit none + integer, parameter :: n = 100 + integer :: a(n), b(n) + + !$omp parallel + !$omp single + !$omp task affinity(a(1), b(1)) + a(2) = 2 + b(2) = 2 + !$omp end task + !$omp end single + !$omp end parallel +end subroutine omp_task_affinity_multi + +! CHECK-LABEL: func.func @_QPomp_task_affinity_multi() +! CHECK: %[[A4:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFomp_task_affinity_multiEa"} +! CHECK: %[[B4:.*]]:2 = hlfir.declare {{.*}} {uniq_name = "_QFomp_task_affinity_multiEb"} +! CHECK: omp.parallel { +! CHECK: omp.single { +! CHECK: omp.task affinity(%[[A4]]#0 : !fir.ref>, %[[B4]]#0 : !fir.ref>) { +! CHECK: omp.terminator +! CHECK: } +! CHECK: omp.terminator +! CHECK: } +! CHECK: return diff --git a/flang/test/Lower/dummy-argument-assumed-shape-optional.f90 b/flang/test/Lower/dummy-argument-assumed-shape-optional.f90 index 5e52459a24309..a1fcea20c3eaf 100644 --- a/flang/test/Lower/dummy-argument-assumed-shape-optional.f90 +++ b/flang/test/Lower/dummy-argument-assumed-shape-optional.f90 @@ -1,4 +1,4 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s module tests interface subroutine takes_contiguous(a) @@ -22,26 +22,11 @@ subroutine test_assumed_shape_to_contiguous(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_assumed_shape_to_contiguous( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.box>) -> !fir.box -! CHECK: %[[VAL_2:.*]] = fir.call @_FortranAIsContiguous(%[[VAL_1]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_3:.*]] = fir.if %[[VAL_2]] -> (!fir.heap>) { -! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_0]] : (!fir.box>) -> !fir.heap> -! CHECK: fir.result %[[VAL_4]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_7:.*]] = fir.allocmem !fir.array -! CHECK: fir.call @_FortranAAssign -! CHECK: fir.result %[[VAL_7]] : !fir.heap> -! CHECK: } -! CHECK: %[[VAL_20:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_21:.*]]:3 = fir.box_dims %[[VAL_0]], %[[VAL_20]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_22:.*]] = arith.constant false -! CHECK: %[[VAL_23:.*]] = arith.cmpi eq, %[[VAL_2]], %[[VAL_22]] : i1 -! CHECK: %[[VAL_24:.*]] = fir.shape %[[VAL_21]]#1 : (index) -> !fir.shape<1> -! CHECK: %[[VAL_25:.*]] = fir.embox %[[VAL_3]](%[[VAL_24]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> -! CHECK: fir.call @_QPtakes_contiguous(%[[VAL_25]]) {{.*}}: (!fir.box>) -> () -! CHECK: fir.if %[[VAL_23]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } +! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_assumed_shape_to_contiguousEx"{{.*}} +! CHECK: %[[VAL_3:.*]]:2 = hlfir.copy_in %[[VAL_2]]#0 to %[[VAL_1]] : (!fir.box>, !fir.ref>>>) -> (!fir.box>, i1) +! CHECK: fir.call @_QPtakes_contiguous(%[[VAL_3]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: hlfir.copy_out %[[VAL_1]], %[[VAL_3]]#1 to %[[VAL_2]]#0 : (!fir.ref>>>, i1, !fir.box>) -> () ! CHECK: return ! CHECK:} @@ -52,13 +37,12 @@ subroutine test_assumed_shape_contiguous_to_contiguous(x) ! CHECK-LABEL: func.func @_QMtestsPtest_assumed_shape_contiguous_to_contiguous( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}) { ! CHECK: %[[VAL_1:.*]] = fir.box_addr %[[VAL_0]] : (!fir.box>) -> !fir.ref> -! CHECK: %[[VAL_2:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_3:.*]]:3 = fir.box_dims %[[VAL_0]], %[[VAL_2]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_5:.*]] = fir.shape_shift %[[VAL_4]], %[[VAL_3]]#1 : (index, index) -> !fir.shapeshift<1> -! CHECK: %[[VAL_6:.*]] = fir.embox %[[VAL_1]](%[[VAL_5]]) : (!fir.ref>, !fir.shapeshift<1>) -> !fir.box> -! CHECK: fir.call @_QPtakes_contiguous(%[[VAL_6]]) {{.*}}: (!fir.box>) -> () -! CHECK-NEXT: return +! CHECK: %[[VAL_2:.*]]:3 = fir.box_dims %[[VAL_0]], %c0 : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[VAL_3:.*]] = fir.shape_shift %c1, %[[VAL_2]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_3]]) {{.*}}uniq_name = "_QMtestsFtest_assumed_shape_contiguous_to_contiguousEx"{{.*}} +! CHECK: fir.call @_QPtakes_contiguous(%[[VAL_4]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: return +! CHECK:} subroutine test_assumed_shape_opt_to_contiguous(x) real, optional :: x(:) @@ -66,26 +50,11 @@ subroutine test_assumed_shape_opt_to_contiguous(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_assumed_shape_opt_to_contiguous( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.box>) -> !fir.box -! CHECK: %[[VAL_2:.*]] = fir.call @_FortranAIsContiguous(%[[VAL_1]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_3:.*]] = fir.if %[[VAL_2]] -> (!fir.heap>) { -! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_0]] : (!fir.box>) -> !fir.heap> -! CHECK: fir.result %[[VAL_4]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_7:.*]] = fir.allocmem !fir.array -! CHECK: fir.call @_FortranAAssign -! CHECK: fir.result %[[VAL_7]] : !fir.heap> -! CHECK: } -! CHECK: %[[VAL_20:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_21:.*]]:3 = fir.box_dims %[[VAL_0]], %[[VAL_20]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_22:.*]] = arith.constant false -! CHECK: %[[VAL_23:.*]] = arith.cmpi eq, %[[VAL_2]], %[[VAL_22]] : i1 -! CHECK: %[[VAL_24:.*]] = fir.shape %[[VAL_21]]#1 : (index) -> !fir.shape<1> -! CHECK: %[[VAL_25:.*]] = fir.embox %[[VAL_3]](%[[VAL_24]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> -! CHECK: fir.call @_QPtakes_contiguous(%[[VAL_25]]) {{.*}}: (!fir.box>) -> () -! CHECK: fir.if %[[VAL_23]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } +! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_assumed_shape_opt_to_contiguousEx"{{.*}} +! CHECK: %[[VAL_3:.*]]:2 = hlfir.copy_in %[[VAL_2]]#0 to %[[VAL_1]] : (!fir.box>, !fir.ref>>>) -> (!fir.box>, i1) +! CHECK: fir.call @_QPtakes_contiguous(%[[VAL_3]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: hlfir.copy_out %[[VAL_1]], %[[VAL_3]]#1 to %[[VAL_2]]#0 : (!fir.ref>>>, i1, !fir.box>) -> () ! CHECK: return ! CHECK:} @@ -95,9 +64,10 @@ subroutine test_assumed_shape_contiguous_opt_to_contiguous(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_assumed_shape_contiguous_opt_to_contiguous( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous, fir.optional}) { -! CHECK: fir.call @_QPtakes_contiguous(%[[VAL_0]]) {{.*}}: (!fir.box>) -> () -! CHECK-NEXT: return - +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_assumed_shape_contiguous_opt_to_contiguousEx"{{.*}} +! CHECK: fir.call @_QPtakes_contiguous(%[[VAL_1]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: return +! CHECK:} ! ----------------------------------------------------------------------------- ! Test passing assumed shapes to contiguous optional assumed shapes @@ -111,26 +81,11 @@ subroutine test_assumed_shape_to_contiguous_opt(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_assumed_shape_to_contiguous_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.box>) -> !fir.box -! CHECK: %[[VAL_2:.*]] = fir.call @_FortranAIsContiguous(%[[VAL_1]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_3:.*]] = fir.if %[[VAL_2]] -> (!fir.heap>) { -! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_0]] : (!fir.box>) -> !fir.heap> -! CHECK: fir.result %[[VAL_4]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_7:.*]] = fir.allocmem !fir.array -! CHECK: fir.call @_FortranAAssign -! CHECK: fir.result %[[VAL_7]] : !fir.heap> -! CHECK: } -! CHECK: %[[VAL_20:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_21:.*]]:3 = fir.box_dims %[[VAL_0]], %[[VAL_20]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_22:.*]] = arith.constant false -! CHECK: %[[VAL_23:.*]] = arith.cmpi eq, %[[VAL_2]], %[[VAL_22]] : i1 -! CHECK: %[[VAL_24:.*]] = fir.shape %[[VAL_21]]#1 : (index) -> !fir.shape<1> -! CHECK: %[[VAL_25:.*]] = fir.embox %[[VAL_3]](%[[VAL_24]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> -! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_25]]) {{.*}}: (!fir.box>) -> () -! CHECK: fir.if %[[VAL_23]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } +! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_assumed_shape_to_contiguous_optEx"{{.*}} +! CHECK: %[[VAL_3:.*]]:2 = hlfir.copy_in %[[VAL_2]]#0 to %[[VAL_1]] : (!fir.box>, !fir.ref>>>) -> (!fir.box>, i1) +! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_3]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: hlfir.copy_out %[[VAL_1]], %[[VAL_3]]#1 to %[[VAL_2]]#0 : (!fir.ref>>>, i1, !fir.box>) -> () ! CHECK: return ! CHECK:} @@ -141,13 +96,12 @@ subroutine test_assumed_shape_contiguous_to_contiguous_opt(x) ! CHECK-LABEL: func.func @_QMtestsPtest_assumed_shape_contiguous_to_contiguous_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}) { ! CHECK: %[[VAL_1:.*]] = fir.box_addr %[[VAL_0]] : (!fir.box>) -> !fir.ref> -! CHECK: %[[VAL_2:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_3:.*]]:3 = fir.box_dims %[[VAL_0]], %[[VAL_2]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_5:.*]] = fir.shape_shift %[[VAL_4]], %[[VAL_3]]#1 : (index, index) -> !fir.shapeshift<1> -! CHECK: %[[VAL_6:.*]] = fir.embox %[[VAL_1]](%[[VAL_5]]) : (!fir.ref>, !fir.shapeshift<1>) -> !fir.box> -! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_6]]) {{.*}}: (!fir.box>) -> () -! CHECK-NEXT: return +! CHECK: %[[VAL_2:.*]]:3 = fir.box_dims %[[VAL_0]], %c0 : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[VAL_3:.*]] = fir.shape_shift %c1, %[[VAL_2]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_3]]) {{.*}}uniq_name = "_QMtestsFtest_assumed_shape_contiguous_to_contiguous_optEx"{{.*}} +! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_4]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: return +! CHECK:} subroutine test_assumed_shape_opt_to_contiguous_opt(x) real, optional :: x(:) @@ -155,41 +109,20 @@ subroutine test_assumed_shape_opt_to_contiguous_opt(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_assumed_shape_opt_to_contiguous_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]] : (!fir.box>) -> i1 -! CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ref> -! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = fir.embox %[[VAL_2]](%[[VAL_4]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -! CHECK: %[[VAL_6:.*]] = arith.select %[[VAL_1]], %[[VAL_0]], %[[VAL_5]] : !fir.box> -! CHECK: %[[VAL_7:.*]] = fir.convert %[[VAL_6]] : (!fir.box>) -> !fir.box -! CHECK: %[[VAL_8:.*]] = fir.call @_FortranAIsContiguous(%[[VAL_7]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_9:.*]] = fir.if %[[VAL_1]] -> (!fir.heap>) { -! CHECK: %[[VAL_10:.*]] = fir.if %[[VAL_8]] -> (!fir.heap>) { -! CHECK: %[[VAL_11:.*]] = fir.box_addr %[[VAL_6]] : (!fir.box>) -> !fir.heap> -! CHECK: fir.result %[[VAL_11]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_14:.*]] = fir.allocmem !fir.array -! CHECK: fir.call @_FortranAAssign -! CHECK: fir.result %[[VAL_14]] : !fir.heap> -! CHECK: } -! CHECK: fir.result %[[VAL_10]] : !fir.heap> +! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_assumed_shape_opt_to_contiguous_optEx"{{.*}} +! CHECK: %[[VAL_3:.*]] = fir.is_present %[[VAL_2]]#0 : (!fir.box>) -> i1 +! CHECK: %[[VAL_4:.*]]:3 = fir.if %[[VAL_3]] -> (!fir.box>, i1, !fir.box>) { +! CHECK: %[[VAL_5:.*]]:2 = hlfir.copy_in %[[VAL_2]]#0 to %[[VAL_1]] : (!fir.box>, !fir.ref>>>) -> (!fir.box>, i1) +! CHECK: fir.result %[[VAL_5]]#0, %[[VAL_5]]#1, %[[VAL_2]]#0 : !fir.box>, i1, !fir.box> ! CHECK: } else { -! CHECK: %[[VAL_28:.*]] = fir.zero_bits !fir.heap> -! CHECK: fir.result %[[VAL_28]] : !fir.heap> -! CHECK: } -! CHECK: %[[VAL_29:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_30:.*]]:3 = fir.box_dims %[[VAL_6]], %[[VAL_29]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_31:.*]] = arith.constant false -! CHECK: %[[VAL_32:.*]] = arith.cmpi eq, %[[VAL_8]], %[[VAL_31]] : i1 -! CHECK: %[[VAL_33:.*]] = arith.andi %[[VAL_1]], %[[VAL_32]] : i1 -! CHECK: %[[VAL_34:.*]] = fir.shape %[[VAL_30]]#1 : (index) -> !fir.shape<1> -! CHECK: %[[VAL_35:.*]] = fir.embox %[[VAL_9]](%[[VAL_34]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> -! CHECK: %[[VAL_37:.*]] = fir.absent !fir.box> -! CHECK: %[[VAL_38:.*]] = arith.select %[[VAL_1]], %[[VAL_35]], %[[VAL_37]] : !fir.box> -! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_38]]) {{.*}}: (!fir.box>) -> () -! CHECK: fir.if %[[VAL_33]] { -! CHECK: fir.call @_FortranACopyOutAssign +! CHECK: %[[VAL_6:.*]] = fir.absent !fir.box> +! CHECK: %[[VAL_7:.*]] = arith.constant false +! CHECK: %[[VAL_8:.*]] = fir.absent !fir.box> +! CHECK: fir.result %[[VAL_6]], %[[VAL_7]], %[[VAL_8]] : !fir.box>, i1, !fir.box> ! CHECK: } +! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_4]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: hlfir.copy_out %[[VAL_1]], %[[VAL_4]]#1 to %[[VAL_4]]#2 : (!fir.ref>>>, i1, !fir.box>) -> () ! CHECK: return ! CHECK:} @@ -199,8 +132,17 @@ subroutine test_assumed_shape_contiguous_opt_to_contiguous_opt(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_assumed_shape_contiguous_opt_to_contiguous_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous, fir.optional}) { -! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_0]]) {{.*}}: (!fir.box>) -> () -! CHECK-NEXT: return +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_assumed_shape_contiguous_opt_to_contiguous_optEx"{{.*}} +! CHECK: %[[VAL_2:.*]] = fir.is_present %[[VAL_1]]#0 : (!fir.box>) -> i1 +! CHECK: %[[VAL_3:.*]] = fir.if %[[VAL_2]] -> (!fir.box>) { +! CHECK: fir.result %[[VAL_1]]#0 : !fir.box> +! CHECK: } else { +! CHECK: %[[VAL_4:.*]] = fir.absent !fir.box> +! CHECK: fir.result %[[VAL_4]] : !fir.box> +! CHECK: } +! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_3]]) {{.*}} : (!fir.box>) -> () +! CHECK: return +! CHECK:} ! ----------------------------------------------------------------------------- ! Test passing pointers to contiguous optional assumed shapes @@ -215,43 +157,25 @@ subroutine test_pointer_to_contiguous_opt(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_pointer_to_contiguous_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ptr>) -> i64 -! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 -! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 -! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_7:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_8:.*]]:3 = fir.box_dims %[[VAL_6]], %[[VAL_7]] : (!fir.box>>, index) -> (index, index, index) -! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_6]] : (!fir.box>>) -> !fir.box -! CHECK: %[[VAL_10:.*]] = fir.call @_FortranAIsContiguous(%[[VAL_9]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_11:.*]] = fir.if %[[VAL_5]] -> (!fir.heap>) { -! CHECK: %[[VAL_12:.*]] = fir.if %[[VAL_10]] -> (!fir.heap>) { -! CHECK: %[[VAL_13:.*]] = fir.box_addr %[[VAL_6]] : (!fir.box>>) -> !fir.heap> -! CHECK: fir.result %[[VAL_13]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_16:.*]] = fir.allocmem !fir.array -! CHECK: fir.call @_FortranAAssign -! CHECK: fir.result %[[VAL_16]] : !fir.heap> -! CHECK: } -! CHECK: fir.result %[[VAL_12]] : !fir.heap> +! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_pointer_to_contiguous_optEx"{{.*}} +! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref>>> +! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_3]] : (!fir.box>>) -> !fir.ptr> +! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (!fir.ptr>) -> i64 +! CHECK: %[[VAL_6:.*]] = arith.cmpi ne, %[[VAL_5]], %c0_i64 : i64 +! CHECK: %[[VAL_7:.*]]:3 = fir.if %[[VAL_6]] -> (!fir.box>, i1, !fir.box>>) { +! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref>>> +! CHECK: %[[VAL_9:.*]]:2 = hlfir.copy_in %[[VAL_8]] to %[[VAL_1]] : (!fir.box>>, !fir.ref>>>) -> (!fir.box>>, i1) +! CHECK: %[[VAL_10:.*]] = fir.rebox %[[VAL_9]]#0 : (!fir.box>>) -> !fir.box> +! CHECK: fir.result %[[VAL_10]], %[[VAL_9]]#1, %[[VAL_8]] : !fir.box>, i1, !fir.box>> ! CHECK: } else { -! CHECK: %[[VAL_31:.*]] = fir.zero_bits !fir.heap> -! CHECK: fir.result %[[VAL_31]] : !fir.heap> -! CHECK: } -! CHECK: %[[VAL_32:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_33:.*]]:3 = fir.box_dims %[[VAL_6]], %[[VAL_32]] : (!fir.box>>, index) -> (index, index, index) -! CHECK: %[[VAL_34:.*]] = arith.constant false -! CHECK: %[[VAL_35:.*]] = arith.cmpi eq, %[[VAL_10]], %[[VAL_34]] : i1 -! CHECK: %[[VAL_36:.*]] = arith.andi %[[VAL_5]], %[[VAL_35]] : i1 -! CHECK: %[[VAL_37:.*]] = fir.shape_shift %[[VAL_8]]#0, %[[VAL_33]]#1 : (index, index) -> !fir.shapeshift<1> -! CHECK: %[[VAL_38:.*]] = fir.embox %[[VAL_11]](%[[VAL_37]]) : (!fir.heap>, !fir.shapeshift<1>) -> !fir.box> -! CHECK: %[[VAL_40:.*]] = fir.absent !fir.box> -! CHECK: %[[VAL_41:.*]] = arith.select %[[VAL_5]], %[[VAL_38]], %[[VAL_40]] : !fir.box> -! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_41]]) {{.*}}: (!fir.box>) -> () -! CHECK: fir.if %[[VAL_36]] { -! CHECK: fir.call @_FortranACopyOutAssign +! CHECK: %[[VAL_11:.*]] = fir.absent !fir.box> +! CHECK: %[[VAL_12:.*]] = arith.constant false +! CHECK: %[[VAL_13:.*]] = fir.absent !fir.box>> +! CHECK: fir.result %[[VAL_11]], %[[VAL_12]], %[[VAL_13]] : !fir.box>, i1, !fir.box>> ! CHECK: } +! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_7]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: hlfir.copy_out %[[VAL_1]], %[[VAL_7]]#1 to %[[VAL_7]]#2 : (!fir.ref>>>, i1, !fir.box>>) -> () ! CHECK: return ! CHECK:} @@ -261,21 +185,22 @@ subroutine test_pointer_contiguous_to_contiguous_opt(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_pointer_contiguous_to_contiguous_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x", fir.contiguous}) { -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ptr>) -> i64 -! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 -! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 -! CHECK: %[[VAL_6:.*]] = fir.absent !fir.box> -! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_8:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_9:.*]]:3 = fir.box_dims %[[VAL_7]], %[[VAL_8]] : (!fir.box>>, index) -> (index, index, index) -! CHECK: %[[VAL_10:.*]] = fir.box_addr %[[VAL_7]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_11:.*]] = fir.shape_shift %[[VAL_9]]#0, %[[VAL_9]]#1 : (index, index) -> !fir.shapeshift<1> -! CHECK: %[[VAL_12:.*]] = fir.embox %[[VAL_10]](%[[VAL_11]]) : (!fir.ptr>, !fir.shapeshift<1>) -> !fir.box> -! CHECK: %[[VAL_13:.*]] = arith.select %[[VAL_5]], %[[VAL_12]], %[[VAL_6]] : !fir.box> -! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_13]]) {{.*}}: (!fir.box>) -> () -! CHECK-NEXT: return +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_pointer_contiguous_to_contiguous_optEx"{{.*}} +! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> +! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]] : (!fir.box>>) -> !fir.ptr> +! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ptr>) -> i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_4]], %c0_i64 : i64 +! CHECK: %[[VAL_6:.*]] = fir.if %[[VAL_5]] -> (!fir.box>) { +! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> +! CHECK: %[[VAL_8:.*]] = fir.rebox %[[VAL_7]] : (!fir.box>>) -> !fir.box> +! CHECK: fir.result %[[VAL_8]] : !fir.box> +! CHECK: } else { +! CHECK: %[[VAL_9:.*]] = fir.absent !fir.box> +! CHECK: fir.result %[[VAL_9]] : !fir.box> +! CHECK: } +! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_6]]) {{.*}} : (!fir.box>) -> () +! CHECK: return +! CHECK:} subroutine test_pointer_opt_to_contiguous_opt(x) real, pointer, optional :: x(:) @@ -283,43 +208,25 @@ subroutine test_pointer_opt_to_contiguous_opt(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_pointer_opt_to_contiguous_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x", fir.optional}) { -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ptr>) -> i64 -! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 -! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 -! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_7:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_8:.*]]:3 = fir.box_dims %[[VAL_6]], %[[VAL_7]] : (!fir.box>>, index) -> (index, index, index) -! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_6]] : (!fir.box>>) -> !fir.box -! CHECK: %[[VAL_10:.*]] = fir.call @_FortranAIsContiguous(%[[VAL_9]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_11:.*]] = fir.if %[[VAL_5]] -> (!fir.heap>) { -! CHECK: %[[VAL_12:.*]] = fir.if %[[VAL_10]] -> (!fir.heap>) { -! CHECK: %[[VAL_13:.*]] = fir.box_addr %[[VAL_6]] : (!fir.box>>) -> !fir.heap> -! CHECK: fir.result %[[VAL_13]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_16:.*]] = fir.allocmem !fir.array -! CHECK: fir.call @_FortranAAssign -! CHECK: fir.result %[[VAL_16]] : !fir.heap> -! CHECK: } -! CHECK: fir.result %[[VAL_12]] : !fir.heap> +! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> +! CHECK: %[[VAL_2:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_pointer_opt_to_contiguous_optEx"{{.*}} +! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref>>> +! CHECK: %[[VAL_4:.*]] = fir.box_addr %[[VAL_3]] : (!fir.box>>) -> !fir.ptr> +! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (!fir.ptr>) -> i64 +! CHECK: %[[VAL_6:.*]] = arith.cmpi ne, %[[VAL_5]], %c0_i64 : i64 +! CHECK: %[[VAL_7:.*]]:3 = fir.if %[[VAL_6]] -> (!fir.box>, i1, !fir.box>>) { +! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_2]]#0 : !fir.ref>>> +! CHECK: %[[VAL_9:.*]]:2 = hlfir.copy_in %[[VAL_8]] to %[[VAL_1]] : (!fir.box>>, !fir.ref>>>) -> (!fir.box>>, i1) +! CHECK: %[[VAL_10:.*]] = fir.rebox %[[VAL_9]]#0 : (!fir.box>>) -> !fir.box> +! CHECK: fir.result %[[VAL_10]], %[[VAL_9]]#1, %[[VAL_8]] : !fir.box>, i1, !fir.box>> ! CHECK: } else { -! CHECK: %[[VAL_31:.*]] = fir.zero_bits !fir.heap> -! CHECK: fir.result %[[VAL_31]] : !fir.heap> -! CHECK: } -! CHECK: %[[VAL_32:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_33:.*]]:3 = fir.box_dims %[[VAL_6]], %[[VAL_32]] : (!fir.box>>, index) -> (index, index, index) -! CHECK: %[[VAL_34:.*]] = arith.constant false -! CHECK: %[[VAL_35:.*]] = arith.cmpi eq, %[[VAL_10]], %[[VAL_34]] : i1 -! CHECK: %[[VAL_36:.*]] = arith.andi %[[VAL_5]], %[[VAL_35]] : i1 -! CHECK: %[[VAL_37:.*]] = fir.shape_shift %[[VAL_8]]#0, %[[VAL_33]]#1 : (index, index) -> !fir.shapeshift<1> -! CHECK: %[[VAL_38:.*]] = fir.embox %[[VAL_11]](%[[VAL_37]]) : (!fir.heap>, !fir.shapeshift<1>) -> !fir.box> -! CHECK: %[[VAL_40:.*]] = fir.absent !fir.box> -! CHECK: %[[VAL_41:.*]] = arith.select %[[VAL_5]], %[[VAL_38]], %[[VAL_40]] : !fir.box> -! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_41]]) {{.*}}: (!fir.box>) -> () -! CHECK: fir.if %[[VAL_36]] { -! CHECK: fir.call @_FortranACopyOutAssign +! CHECK: %[[VAL_11:.*]] = fir.absent !fir.box> +! CHECK: %[[VAL_12:.*]] = arith.constant false +! CHECK: %[[VAL_13:.*]] = fir.absent !fir.box>> +! CHECK: fir.result %[[VAL_11]], %[[VAL_12]], %[[VAL_13]] : !fir.box>, i1, !fir.box>> ! CHECK: } +! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_7]]#0) {{.*}} : (!fir.box>) -> () +! CHECK: hlfir.copy_out %[[VAL_1]], %[[VAL_7]]#1 to %[[VAL_7]]#2 : (!fir.ref>>>, i1, !fir.box>>) -> () ! CHECK: return ! CHECK:} @@ -329,19 +236,20 @@ subroutine test_pointer_contiguous_opt_to_contiguous_opt(x) end subroutine ! CHECK-LABEL: func.func @_QMtestsPtest_pointer_contiguous_opt_to_contiguous_opt( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "x", fir.contiguous, fir.optional}) { -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ptr>) -> i64 -! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 -! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 -! CHECK: %[[VAL_6:.*]] = fir.absent !fir.box> -! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_8:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_9:.*]]:3 = fir.box_dims %[[VAL_7]], %[[VAL_8]] : (!fir.box>>, index) -> (index, index, index) -! CHECK: %[[VAL_10:.*]] = fir.box_addr %[[VAL_7]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_11:.*]] = fir.shape_shift %[[VAL_9]]#0, %[[VAL_9]]#1 : (index, index) -> !fir.shapeshift<1> -! CHECK: %[[VAL_12:.*]] = fir.embox %[[VAL_10]](%[[VAL_11]]) : (!fir.ptr>, !fir.shapeshift<1>) -> !fir.box> -! CHECK: %[[VAL_13:.*]] = arith.select %[[VAL_5]], %[[VAL_12]], %[[VAL_6]] : !fir.box> -! CHECK-NEXT: fir.call @_QPtakes_contiguous_optional(%[[VAL_13]]) {{.*}}: (!fir.box>) -> () +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMtestsFtest_pointer_contiguous_opt_to_contiguous_optEx"{{.*}} +! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> +! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]] : (!fir.box>>) -> !fir.ptr> +! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ptr>) -> i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_4]], %c0_i64 : i64 +! CHECK: %[[VAL_6:.*]] = fir.if %[[VAL_5]] -> (!fir.box>) { +! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref>>> +! CHECK: %[[VAL_8:.*]] = fir.rebox %[[VAL_7]] : (!fir.box>>) -> !fir.box> +! CHECK: fir.result %[[VAL_8]] : !fir.box> +! CHECK: } else { +! CHECK: %[[VAL_9:.*]] = fir.absent !fir.box> +! CHECK: fir.result %[[VAL_9]] : !fir.box> +! CHECK: } +! CHECK: fir.call @_QPtakes_contiguous_optional(%[[VAL_6]]) {{.*}} : (!fir.box>) -> () ! CHECK: return +! CHECK:} end module diff --git a/flang/test/Lower/dummy-argument-contiguous.f90 b/flang/test/Lower/dummy-argument-contiguous.f90 index 19bc3818ea0f5..2d6797a92bac8 100644 --- a/flang/test/Lower/dummy-argument-contiguous.f90 +++ b/flang/test/Lower/dummy-argument-contiguous.f90 @@ -1,5 +1,4 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: bbc -emit-fir -hlfir=false -gen-array-coor %s -o - | FileCheck %s --check-prefix=ArrayCoorCHECK +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s ! Test that non-contiguous assumed-shape memory layout is handled in lowering. ! In practice, test that input fir.box is propagated to fir operations @@ -8,126 +7,120 @@ ! attribute to the fir argument and that is takes the contiguity into account ! In practice, test that the input fir.box is not propagated to fir operations. -! CHECK-LABEL: func @_QPtest_element_ref(%arg0: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %arg1: !fir.box>{{.*}}) { -! ArrayCoorCHECK-LABEL: func @_QPtest_element_ref +! CHECK-LABEL: func @_QPtest_element_ref( +! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %[[ARG1:.*]]: !fir.box> {fir.bindc_name = "y"}) { subroutine test_element_ref(x, y) real, contiguous :: x(:) - ! CHECK-DAG: %[[xaddr:.*]] = fir.box_addr %arg0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_REF:.*]] = fir.box_addr %[[ARG0]] : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]]({{.*}}) {{.*}}uniq_name = "_QFtest_element_refEx"{{.*}} : (!fir.ref>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) real :: y(4:) - ! CHECK-DAG: %[[c4:.*]] = fir.convert %c4{{.*}} : (i64) -> index + ! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[ARG1]]({{.*}}) {{.*}}uniq_name = "_QFtest_element_refEy"{{.*}} : (!fir.box>, !fir.shift<1>, !fir.dscope) -> (!fir.box>, !fir.box>) call bar(x(100)) - ! CHECK: fir.coordinate_of %[[xaddr]], %{{.*}} : (!fir.ref>, i64) -> !fir.ref + ! CHECK: %[[X_ELT:.*]] = hlfir.designate %[[X_DECL]]#0 (%c100) : (!fir.box>, index) -> !fir.ref + ! CHECK: fir.call @_QPbar(%[[X_ELT]]) {{.*}} : (!fir.ref) -> () call bar(y(100)) - ! Test that for an entity that is not know to be contiguous, the fir.box is passed - ! to coordinate of and that the lower bounds is already applied by lowering. - ! CHECK: %[[c4_2:.*]] = fir.convert %[[c4]] : (index) -> i64 - ! CHECK: %[[index:.*]] = arith.subi %c100{{.*}}, %[[c4_2]] : i64 - ! CHECK: fir.coordinate_of %arg1, %{{.*}} : (!fir.box>, i64) -> !fir.ref - - - ! Repeat test when lowering is using fir.array_coor - ! ArrayCoorCHECK-DAG: %[[xaddr:.*]] = fir.box_addr %arg0 : (!fir.box>) -> !fir.ref> - ! ArrayCoorCHECK-DAG: %[[xshape:.*]] = fir.shape - ! ArrayCoorCHECK-DAG: %[[c100:.*]] = fir.convert %c100{{.*}} : (i64) -> index - ! ArrayCoorCHECK: fir.array_coor %[[xaddr]](%[[xshape]]) %[[c100]] : (!fir.ref>, !fir.shapeshift<1>, index) -> !fir.ref - - ! ArrayCoorCHECK-DAG: %[[c100_1:.*]] = fir.convert %c100{{.*}} : (i64) -> index - ! ArrayCoorCHECK-DAG: %[[shift:.*]] = fir.shift %{{.*}} : (index) -> !fir.shift<1> - ! ArrayCoorCHECK: fir.array_coor %arg1(%[[shift]]) %[[c100_1]] : (!fir.box>, !fir.shift<1>, index) -> !fir.ref + ! CHECK: %[[Y_ELT:.*]] = hlfir.designate %[[Y_DECL]]#0 (%c100_0) : (!fir.box>, index) -> !fir.ref + ! CHECK: fir.call @_QPbar(%[[Y_ELT]]) {{.*}} : (!fir.ref) -> () end subroutine -! CHECK-LABEL: func @_QPtest_element_assign(%arg0: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %arg1: !fir.box>{{.*}}) { -! ArrayCoorCHECK-LABEL: func @_QPtest_element_assign +! CHECK-LABEL: func @_QPtest_element_assign( +! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %[[ARG1:.*]]: !fir.box> {fir.bindc_name = "y"}) { subroutine test_element_assign(x, y) real, contiguous :: x(:) - ! CHECK-DAG: %[[xaddr:.*]] = fir.box_addr %arg0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_REF:.*]] = fir.box_addr %[[ARG0]] : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]]({{.*}}) {{.*}}uniq_name = "_QFtest_element_assignEx"{{.*}} : (!fir.ref>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) real :: y(4:) - ! CHECK-DAG: %[[c4:.*]] = fir.convert %c4{{.*}} : (i64) -> index + ! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[ARG1]]({{.*}}) {{.*}}uniq_name = "_QFtest_element_assignEy"{{.*}} : (!fir.box>, !fir.shift<1>, !fir.dscope) -> (!fir.box>, !fir.box>) x(100) = 42. - ! CHECK: fir.coordinate_of %[[xaddr]], %{{.*}} : (!fir.ref>, i64) -> !fir.ref + ! CHECK: %[[X_ELT:.*]] = hlfir.designate %[[X_DECL]]#0 (%c100) : (!fir.box>, index) -> !fir.ref + ! CHECK: hlfir.assign %cst to %[[X_ELT]] : f32, !fir.ref y(100) = 42. - ! CHECK: %[[c4_2:.*]] = fir.convert %[[c4]] : (index) -> i64 - ! CHECK: %[[index:.*]] = arith.subi %c100{{.*}}, %[[c4_2]] : i64 - ! CHECK: fir.coordinate_of %arg1, %{{.*}} : (!fir.box>, i64) -> !fir.ref - - ! ArrayCoorCHECK-DAG: %[[xaddr:.*]] = fir.box_addr %arg0 : (!fir.box>) -> !fir.ref> - ! ArrayCoorCHECK-DAG: %[[xshape:.*]] = fir.shape - ! ArrayCoorCHECK-DAG: %[[c100:.*]] = fir.convert %c100{{.*}} : (i64) -> index - ! ArrayCoorCHECK: fir.array_coor %[[xaddr]](%[[xshape]]) %[[c100]] : (!fir.ref>, !fir.shapeshift<1>, index) -> !fir.ref - - ! ArrayCoorCHECK-DAG: %[[c100_1:.*]] = fir.convert %c100{{.*}} : (i64) -> index - ! ArrayCoorCHECK-DAG: %[[shift:.*]] = fir.shift %{{.*}} : (index) -> !fir.shift<1> - ! ArrayCoorCHECK: fir.array_coor %arg1(%[[shift]]) %[[c100_1]] : (!fir.box>, !fir.shift<1>, index) -> !fir.ref + ! CHECK: %[[Y_ELT:.*]] = hlfir.designate %[[Y_DECL]]#0 (%c100_1) : (!fir.box>, index) -> !fir.ref + ! CHECK: hlfir.assign %cst_0 to %[[Y_ELT]] : f32, !fir.ref end subroutine -! CHECK-LABEL: func @_QPtest_ref_in_array_expr(%arg0: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %arg1: !fir.box>{{.*}}) { +! CHECK-LABEL: func @_QPtest_ref_in_array_expr( +! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %[[ARG1:.*]]: !fir.box> {fir.bindc_name = "y"}) { subroutine test_ref_in_array_expr(x, y) real, contiguous :: x(:) - ! CHECK: %[[xaddr:.*]] = fir.box_addr %arg0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_REF:.*]] = fir.box_addr %[[ARG0]] : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]]({{.*}}) {{.*}}uniq_name = "_QFtest_ref_in_array_exprEx"{{.*}} : (!fir.ref>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) real :: y(:) + ! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {{.*}}uniq_name = "_QFtest_ref_in_array_exprEy"{{.*}} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) call bar2(x+1.) - ! CHECK: fir.array_load %[[xaddr]](%{{.*}}) : (!fir.ref>, !fir.shapeshift<1>) -> !fir.array + ! CHECK: hlfir.elemental {{.*}} + ! CHECK: hlfir.designate %[[X_DECL]]#0 (%{{.*}}) : (!fir.box>, index) -> !fir.ref call bar2(y+1.) - ! CHECK: fir.array_load %arg1 : (!fir.box>) -> !fir.array + ! CHECK: hlfir.elemental {{.*}} + ! CHECK: hlfir.designate %[[Y_DECL]]#0 (%{{.*}}) : (!fir.box>, index) -> !fir.ref end subroutine -! CHECK-LABEL: func @_QPtest_assign_in_array_ref(%arg0: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %arg1: !fir.box>{{.*}}) { +! CHECK-LABEL: func @_QPtest_assign_in_array_ref( +! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %[[ARG1:.*]]: !fir.box> {fir.bindc_name = "y"}) { subroutine test_assign_in_array_ref(x, y) real, contiguous :: x(:) - ! CHECK: %[[xaddr:.*]] = fir.box_addr %arg0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_REF:.*]] = fir.box_addr %[[ARG0]] : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]]({{.*}}) {{.*}}uniq_name = "_QFtest_assign_in_array_refEx"{{.*}} : (!fir.ref>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) real :: y(:) + ! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {{.*}}uniq_name = "_QFtest_assign_in_array_refEy"{{.*}} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) x = 42. - ! CHECK: %[[xload:.*]] = fir.array_load %[[xaddr]]({{.*}}) : (!fir.ref>, !fir.shapeshift<1>) -> !fir.array - ! CHECK: %[[xloop:.*]] = fir.do_loop {{.*}} iter_args(%arg3 = %[[xload]]) -> (!fir.array) - ! CHECK: fir.array_merge_store %[[xload]], %[[xloop]] to %[[xaddr]] : !fir.array, !fir.array, !fir.ref> + ! CHECK: hlfir.assign %cst to %[[X_DECL]]#0 : f32, !fir.box> y = 42. - ! CHECK: %[[yload:.*]] = fir.array_load %arg1 : (!fir.box>) -> !fir.array - ! CHECK: %[[yloop:.*]] = fir.do_loop {{.*}} iter_args(%arg3 = %[[yload]]) -> (!fir.array) { - ! CHECK: fir.array_merge_store %[[yload]], %[[yloop]] to %arg1 : !fir.array, !fir.array, !fir.box> + ! CHECK: hlfir.assign %cst_0 to %[[Y_DECL]]#0 : f32, !fir.box> end subroutine -! CHECK-LABEL: func @_QPtest_slice_ref(%arg0: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %arg1: !fir.box> +! CHECK-LABEL: func @_QPtest_slice_ref( +! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %[[ARG1:.*]]: !fir.box> {fir.bindc_name = "y"}, subroutine test_slice_ref(x, y, z1, z2, i, j, k, n) real, contiguous :: x(:) - ! CHECK: %[[xaddr:.*]] = fir.box_addr %arg0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_REF:.*]] = fir.box_addr %[[ARG0]] : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]]({{.*}}) {{.*}}uniq_name = "_QFtest_slice_refEx"{{.*}} : (!fir.ref>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) real :: y(:) + ! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {{.*}}uniq_name = "_QFtest_slice_refEy"{{.*}} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) integer :: i, j, k, n real :: z1(n), z2(n) z2 = x(i:j:k) - ! CHECK: %[[xslice:.*]] = fir.slice - ! CHECK: fir.array_load %[[xaddr]]{{.*}}%[[xslice]]{{.*}}: (!fir.ref>, !fir.shapeshift<1>, !fir.slice<1>) -> !fir.array + ! CHECK: %[[X_SLICE:.*]] = hlfir.designate %[[X_DECL]]#0 {{.*}} : (!fir.box>, index, index, index, !fir.shape<1>) -> !fir.box> + ! CHECK: hlfir.assign %[[X_SLICE]] to %{{.*}} : !fir.box>, !fir.box> z1 = y(i:j:k) - ! CHECK: %[[yslice:.*]] = fir.slice - ! CHECK: fir.array_load %arg1 {{.*}}%[[yslice]]{{.*}} : (!fir.box>, !fir.slice<1>) -> !fir.array + ! CHECK: %[[Y_SLICE:.*]] = hlfir.designate %[[Y_DECL]]#0 {{.*}} : (!fir.box>, index, index, index, !fir.shape<1>) -> !fir.box> + ! CHECK: hlfir.assign %[[Y_SLICE]] to %{{.*}} : !fir.box>, !fir.box> end subroutine -! CHECK-LABEL: func @_QPtest_slice_assign(%arg0: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %arg1: !fir.box> +! CHECK-LABEL: func @_QPtest_slice_assign( +! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous}, %[[ARG1:.*]]: !fir.box> {fir.bindc_name = "y"}, subroutine test_slice_assign(x, y, i, j, k) real, contiguous :: x(:) - ! CHECK: %[[xaddr:.*]] = fir.box_addr %arg0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_REF:.*]] = fir.box_addr %[[ARG0]] : (!fir.box>) -> !fir.ref> + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]]({{.*}}) {{.*}}uniq_name = "_QFtest_slice_assignEx"{{.*}} : (!fir.ref>, !fir.shapeshift<1>, !fir.dscope) -> (!fir.box>, !fir.ref>) real :: y(:) + ! CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[ARG1]] {{.*}}uniq_name = "_QFtest_slice_assignEy"{{.*}} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) integer :: i, j, k x(i:j:k) = 42. - ! CHECK: %[[xslice:.*]] = fir.slice - ! CHECK: fir.array_load %[[xaddr]]{{.*}}%[[xslice]]{{.*}}: (!fir.ref>, !fir.shapeshift<1>, !fir.slice<1>) -> !fir.array + ! CHECK: %[[X_SLICE:.*]] = hlfir.designate %[[X_DECL]]#0 {{.*}} : (!fir.box>, index, index, index, !fir.shape<1>) -> !fir.box> + ! CHECK: hlfir.assign %cst to %[[X_SLICE]] : f32, !fir.box> y(i:j:k) = 42. - ! CHECK: %[[yslice:.*]] = fir.slice - ! CHECK: fir.array_load %arg1 {{.*}}%[[yslice]]{{.*}}: (!fir.box>, !fir.slice<1>) -> !fir.array + ! CHECK: %[[Y_SLICE:.*]] = hlfir.designate %[[Y_DECL]]#0 {{.*}} : (!fir.box>, index, index, index, !fir.shape<1>) -> !fir.box> + ! CHECK: hlfir.assign %cst_1 to %[[Y_SLICE]] : f32, !fir.box> end subroutine ! test that allocatable are considered contiguous. -! CHECK-LABEL: func @_QPfoo +! CHECK-LABEL: func @_QPfoo( +! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "x"}) { subroutine foo(x) real, allocatable :: x(:) + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {{.*}}uniq_name = "_QFfooEx"{{.*}} call bar(x(100)) - ! CHECK: fir.coordinate_of %{{.*}}, %{{.*}} (!fir.heap>, i64) -> !fir.ref + ! CHECK: %[[X_LOAD:.*]] = fir.load %[[X_DECL]]#0 : !fir.ref>>> + ! CHECK: %[[X_ELT:.*]] = hlfir.designate %[[X_LOAD]] (%c100) : (!fir.box>>, index) -> !fir.ref + ! CHECK: fir.call @_QPbar(%[[X_ELT]]) {{.*}} : (!fir.ref) -> () end subroutine ! Test that non-contiguous dummy are propagated with their memory layout (we ! mainly do not want to create a new box that would ignore the original layout). -! CHECK: func @_QPpropagate(%arg0: !fir.box> {fir.bindc_name = "x"}) +! CHECK: func @_QPpropagate(%[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x"}) subroutine propagate(x) interface subroutine bar3(x) @@ -135,6 +128,7 @@ subroutine bar3(x) end subroutine end interface real :: x(:) + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[ARG0]] {{.*}}uniq_name = "_QFpropagateEx"{{.*}} : (!fir.box>, !fir.dscope) -> (!fir.box>, !fir.box>) call bar3(x) - ! CHECK: fir.call @_QPbar3(%arg0) {{.*}}: (!fir.box>) -> () + ! CHECK: fir.call @_QPbar3(%[[X_DECL]]#0) {{.*}}: (!fir.box>) -> () end subroutine diff --git a/flang/test/Lower/dummy-argument-optional-2.f90 b/flang/test/Lower/dummy-argument-optional-2.f90 index cc026132bd081..da666708b203b 100644 --- a/flang/test/Lower/dummy-argument-optional-2.f90 +++ b/flang/test/Lower/dummy-argument-optional-2.f90 @@ -1,6 +1,6 @@ ! Test passing pointer, allocatables, and optional assumed shapes to optional ! explicit shapes (see F2018 15.5.2.12). -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s module optional_tests implicit none interface @@ -38,46 +38,92 @@ function returns_pointer() ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>{{.*}}) { subroutine pass_pointer_scalar(i) integer, pointer :: i + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_pointer_scalarEi"{{.*}} call takes_opt_scalar(i) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.ptr -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ptr) -> !fir.ref -! CHECK: fir.call @_QPtakes_opt_scalar(%[[VAL_3]]) {{.*}}: (!fir.ref) -> () + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>> + ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>) -> !fir.ptr + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.ptr) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.ref) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>> + ! CHECK: %[[ADDR2:.*]] = fir.box_addr %[[LOAD2]] : (!fir.box>) -> !fir.ptr + ! CHECK: %[[REF:.*]] = fir.convert %[[ADDR2]] : (!fir.ptr) -> !fir.ref + ! CHECK: fir.result %[[REF]] : !fir.ref + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref + ! CHECK: fir.result %[[ABSENT]] : !fir.ref + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_scalar(%[[ARG]]) {{.*}} : (!fir.ref) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_allocatable_scalar( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>{{.*}}) { subroutine pass_allocatable_scalar(i) integer, allocatable :: i + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_allocatable_scalarEi"{{.*}} call takes_opt_scalar(i) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.heap -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.heap) -> !fir.ref -! CHECK: fir.call @_QPtakes_opt_scalar(%[[VAL_3]]) {{.*}}: (!fir.ref) -> () + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>> + ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>) -> !fir.heap + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.heap) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.ref) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>> + ! CHECK: %[[ADDR2:.*]] = fir.box_addr %[[LOAD2]] : (!fir.box>) -> !fir.heap + ! CHECK: %[[REF:.*]] = fir.convert %[[ADDR2]] : (!fir.heap) -> !fir.ref + ! CHECK: fir.result %[[REF]] : !fir.ref + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref + ! CHECK: fir.result %[[ABSENT]] : !fir.ref + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_scalar(%[[ARG]]) {{.*}} : (!fir.ref) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_pointer_scalar_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>{{.*}}) { subroutine pass_pointer_scalar_char(c) character(:), pointer :: c + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_pointer_scalar_charEc"{{.*}} call takes_opt_scalar_char(c) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_elesize %[[VAL_1]] : (!fir.box>>) -> index -! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_5:.*]] = fir.emboxchar %[[VAL_3]], %[[VAL_2]] : (!fir.ptr>, index) -> !fir.boxchar<1> -! CHECK: fir.call @_QPtakes_opt_scalar_char(%[[VAL_5]]) {{.*}}: (!fir.boxchar<1>) -> () + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>) -> !fir.ptr> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.ptr>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.boxchar<1>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[ADDR2:.*]] = fir.box_addr %[[LOAD2]] : (!fir.box>>) -> !fir.ptr> + ! CHECK: %[[LOAD3:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[LEN:.*]] = fir.box_elesize %[[LOAD3]] : (!fir.box>>) -> index + ! CHECK: %[[EMBOX:.*]] = fir.emboxchar %[[ADDR2]], %[[LEN]] : (!fir.ptr>, index) -> !fir.boxchar<1> + ! CHECK: fir.result %[[EMBOX]] : !fir.boxchar<1> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxchar<1> + ! CHECK: fir.result %[[ABSENT]] : !fir.boxchar<1> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_scalar_char(%[[ARG]]) {{.*}} : (!fir.boxchar<1>) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_allocatable_scalar_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>{{.*}}) { subroutine pass_allocatable_scalar_char(c) character(:), allocatable :: c + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_allocatable_scalar_charEc"{{.*}} call takes_opt_scalar_char(c) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_elesize %[[VAL_1]] : (!fir.box>>) -> index -! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.heap> -! CHECK: %[[VAL_5:.*]] = fir.emboxchar %[[VAL_3]], %[[VAL_2]] : (!fir.heap>, index) -> !fir.boxchar<1> -! CHECK: fir.call @_QPtakes_opt_scalar_char(%[[VAL_5]]) {{.*}}: (!fir.boxchar<1>) -> () + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>) -> !fir.heap> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.heap>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.boxchar<1>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[ADDR2:.*]] = fir.box_addr %[[LOAD2]] : (!fir.box>>) -> !fir.heap> + ! CHECK: %[[LOAD3:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[LEN:.*]] = fir.box_elesize %[[LOAD3]] : (!fir.box>>) -> index + ! CHECK: %[[EMBOX:.*]] = fir.emboxchar %[[ADDR2]], %[[LEN]] : (!fir.heap>, index) -> !fir.boxchar<1> + ! CHECK: fir.result %[[EMBOX]] : !fir.boxchar<1> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxchar<1> + ! CHECK: fir.result %[[ABSENT]] : !fir.boxchar<1> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_scalar_char(%[[ARG]]) {{.*}} : (!fir.boxchar<1>) -> () end subroutine ! ----------------------------------------------------------------------------- @@ -91,74 +137,56 @@ subroutine pass_allocatable_scalar_char(c) ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>{{.*}}) { subroutine pass_pointer_array(i) real, pointer :: i(:) + ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.box>> + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_pointer_arrayEi"{{.*}} call takes_opt_explicit_shape(i) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ptr>) -> i64 -! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 -! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 -! CHECK: %[[box:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_7:.*]] = arith.constant 0 : index -! CHECK: %[[box_none:.*]] = fir.convert %[[box]] : (!fir.box>>) -> !fir.box -! CHECK: %[[is_contiguous:.*]] = fir.call @_FortranAIsContiguous(%[[box_none]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_9:.*]] = fir.if %[[VAL_5]] -> (!fir.heap>) { -! CHECK: %[[addr:.*]] = fir.if %[[is_contiguous]] -> (!fir.heap>) { -! CHECK: %[[box_addr:.*]] = fir.box_addr %[[box]] : (!fir.box>>) -> !fir.heap> -! CHECK: fir.result %[[box_addr]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_10:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_11:.*]]:3 = fir.box_dims %[[box]], %[[VAL_10]] : (!fir.box>>, index) -> (index, index, index) -! CHECK: %[[VAL_12:.*]] = fir.allocmem !fir.array, %[[VAL_11]]#1 {uniq_name = ".copyinout"} -! CHECK: fir.call @_FortranAAssignTemporary -! CHECK: fir.result %[[VAL_12]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_26:.*]] = fir.zero_bits !fir.heap> -! CHECK: fir.result %[[VAL_26]] : !fir.heap> -! CHECK: } -! CHECK: %[[not_contiguous:.*]] = arith.cmpi eq, %[[is_contiguous]], %false : i1 -! CHECK: %[[and:.*]] = arith.andi %[[VAL_5]], %[[not_contiguous]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_9]] : (!fir.heap>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[VAL_29]]) {{.*}}: (!fir.ref>) -> () -! CHECK: fir.if %[[and]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>) -> !fir.ptr> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.ptr>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]]:3 = fir.if %[[IS_PRESENT]] -> (!fir.ref>, i1, !fir.box>>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[COPY_IN:.*]]:2 = hlfir.copy_in %[[LOAD2]] to %[[ALLOCA]] : (!fir.box>>, !fir.ref>>>) -> (!fir.box>>, i1) + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[COPY_IN]]#0 : (!fir.box>>) -> !fir.ptr> + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ptr>) -> !fir.ref> + ! CHECK: fir.result %[[REF]], %[[COPY_IN]]#1, %[[LOAD2]] : !fir.ref>, i1, !fir.box>> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: %[[FALSE:.*]] = arith.constant false + ! CHECK: %[[ABSENT_BOX:.*]] = fir.absent !fir.box>> + ! CHECK: fir.result %[[ABSENT]], %[[FALSE]], %[[ABSENT_BOX]] : !fir.ref>, i1, !fir.box>> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[ARG]]#0) {{.*}} : (!fir.ref>) -> () + ! CHECK: hlfir.copy_out %[[ALLOCA]], %[[ARG]]#1 to %[[ARG]]#2 : (!fir.ref>>>, i1, !fir.box>>) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_pointer_array_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>>{{.*}}) { subroutine pass_pointer_array_char(c) character(:), pointer :: c(:) + ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.box>>> + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_pointer_array_charEc"{{.*}} call takes_opt_explicit_shape_char(c) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>>) -> !fir.ptr>> -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ptr>>) -> i64 -! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 -! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 -! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_0]] : !fir.ref>>>> -! CHECK: %[[box_none:.*]] = fir.convert %[[VAL_6]] : (!fir.box>>>) -> !fir.box -! CHECK: %[[is_contiguous:.*]] = fir.call @_FortranAIsContiguous(%[[box_none]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_9:.*]] = fir.if %[[VAL_5]] -> (!fir.heap>>) { -! CHECK: %[[VAL_10:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_11:.*]]:3 = fir.box_dims %[[VAL_6]], %[[VAL_10]] : (!fir.box>>>, index) -> (index, index, index) -! CHECK: %[[VAL_12:.*]] = fir.box_elesize %[[VAL_6]] : (!fir.box>>>) -> index -! CHECK: %[[VAL_13:.*]] = fir.allocmem !fir.array>(%[[VAL_12]] : index), %[[VAL_11]]#1 {uniq_name = ".copyinout"} -! CHECK: fir.call @_FortranAAssignTemporary -! CHECK: fir.result %[[VAL_13]] : !fir.heap>> -! CHECK: } else { -! CHECK: %[[VAL_46:.*]] = fir.zero_bits !fir.heap>> -! CHECK: fir.result %[[VAL_46]] : !fir.heap>> -! CHECK: } -! CHECK: %[[VAL_47:.*]] = fir.box_elesize %[[VAL_6]] : (!fir.box>>>) -> index -! CHECK: %[[not_contiguous:.*]] = arith.cmpi eq, %[[is_contiguous]], %false : i1 -! CHECK: %[[and:.*]] = arith.andi %[[VAL_5]], %[[not_contiguous]] : i1 -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_9]] : (!fir.heap>>) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.emboxchar %[[VAL_50]], %[[VAL_47]] : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[VAL_52]]) {{.*}}: (!fir.boxchar<1>) -> () -! CHECK: fir.if %[[and]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } -! CHECK: return -! CHECK: } + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>>> + ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>>) -> !fir.ptr>> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.ptr>>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]]:3 = fir.if %[[IS_PRESENT]] -> (!fir.boxchar<1>, i1, !fir.box>>>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>>> + ! CHECK: %[[COPY_IN:.*]]:2 = hlfir.copy_in %[[LOAD2]] to %[[ALLOCA]] : (!fir.box>>>, !fir.ref>>>>) -> (!fir.box>>>, i1) + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[COPY_IN]]#0 : (!fir.box>>>) -> !fir.ptr>> + ! CHECK: %[[ELE_SIZE:.*]] = fir.box_elesize %[[COPY_IN]]#0 : (!fir.box>>>) -> index + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ptr>>) -> !fir.ref> + ! CHECK: %[[EMBOX:.*]] = fir.emboxchar %[[REF]], %[[ELE_SIZE]] : (!fir.ref>, index) -> !fir.boxchar<1> + ! CHECK: fir.result %[[EMBOX]], %[[COPY_IN]]#1, %[[LOAD2]] : !fir.boxchar<1>, i1, !fir.box>>> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxchar<1> + ! CHECK: %[[FALSE:.*]] = arith.constant false + ! CHECK: %[[ABSENT_BOX:.*]] = fir.absent !fir.box>>> + ! CHECK: fir.result %[[ABSENT]], %[[FALSE]], %[[ABSENT_BOX]] : !fir.boxchar<1>, i1, !fir.box>>> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[ARG]]#0) {{.*}} : (!fir.boxchar<1>) -> () + ! CHECK: hlfir.copy_out %[[ALLOCA]], %[[ARG]]#1 to %[[ARG]]#2 : (!fir.ref>>>>, i1, !fir.box>>>) -> () end subroutine ! This case is bit special because the pointer is not a symbol but a function @@ -166,31 +194,30 @@ subroutine pass_pointer_array_char(c) ! CHECK-LABEL: func @_QMoptional_testsPforward_pointer_array() { subroutine forward_pointer_array() + ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.box>> + ! CHECK: %[[RES:.*]] = fir.alloca !fir.box>> {bindc_name = ".result"} call takes_opt_explicit_shape(returns_pointer()) -! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>> {bindc_name = ".result"} -! CHECK: %[[VAL_1:.*]] = fir.call @_QPreturns_pointer() {{.*}}: () -> !fir.box>> -! CHECK: fir.save_result %[[VAL_1]] to %[[VAL_0]] : !fir.box>>, !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_2]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ptr>) -> i64 -! CHECK: %[[VAL_5:.*]] = arith.constant 0 : i64 -! CHECK: %[[VAL_6:.*]] = arith.cmpi ne, %[[VAL_4]], %[[VAL_5]] : i64 -! CHECK: %[[is_contiguous:.*]] = fir.call @_FortranAIsContiguous(%{{.*}}) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_7:.*]] = fir.if %[[VAL_6]] -> (!fir.heap>) { -! CHECK: %[[VAL_10:.*]] = fir.allocmem !fir.array -! CHECK: fir.call @_FortranAAssignTemporary -! CHECK: fir.result %[[VAL_10]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_11:.*]] = fir.zero_bits !fir.heap> -! CHECK: fir.result %[[VAL_11]] : !fir.heap> -! CHECK: } -! CHECK: %[[not_contiguous:.*]] = arith.cmpi eq, %[[is_contiguous]], %false : i1 -! CHECK: %[[and:.*]] = arith.andi %[[VAL_6]], %[[not_contiguous]] : i1 -! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_7]] : (!fir.heap>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[VAL_14]]) {{.*}}: (!fir.ref>) -> () -! CHECK: fir.if %[[and]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } + ! CHECK: %[[RET:.*]] = fir.call @_QPreturns_pointer() {{.*}} : () -> !fir.box>> + ! CHECK: fir.save_result %[[RET]] to %[[RES]] : !fir.box>>, !fir.ref>>> + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[RES]] {uniq_name = ".tmp.func_result"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>) -> !fir.ptr> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.ptr>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]]:3 = fir.if %[[IS_PRESENT]] -> (!fir.ref>, i1, !fir.box>>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[COPY_IN:.*]]:2 = hlfir.copy_in %[[LOAD2]] to %[[ALLOCA]] : (!fir.box>>, !fir.ref>>>) -> (!fir.box>>, i1) + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[COPY_IN]]#0 : (!fir.box>>) -> !fir.ptr> + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ptr>) -> !fir.ref> + ! CHECK: fir.result %[[REF]], %[[COPY_IN]]#1, %[[LOAD2]] : !fir.ref>, i1, !fir.box>> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: %[[FALSE:.*]] = arith.constant false + ! CHECK: %[[ABSENT_BOX:.*]] = fir.absent !fir.box>> + ! CHECK: fir.result %[[ABSENT]], %[[FALSE]], %[[ABSENT_BOX]] : !fir.ref>, i1, !fir.box>> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[ARG]]#0) {{.*}} : (!fir.ref>) -> () + ! CHECK: hlfir.copy_out %[[ALLOCA]], %[[ARG]]#1 to %[[ARG]]#2 : (!fir.ref>>>, i1, !fir.box>>) -> () end subroutine ! ----------------------------------------------------------------------------- @@ -204,69 +231,48 @@ subroutine forward_pointer_array() ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { subroutine pass_opt_assumed_shape(x) real, optional :: x(:) + ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.box>> + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_opt_assumed_shapeEx"{{.*}} call takes_opt_explicit_shape(x) -! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]] : (!fir.box>) -> i1 -! CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ref> -! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = fir.embox %[[VAL_2]](%[[VAL_4]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -! CHECK: %[[VAL_6:.*]] = arith.select %[[VAL_1]], %[[VAL_0]], %[[VAL_5]] : !fir.box> -! CHECK: %[[is_contiguous:.*]] = fir.call @_FortranAIsContiguous(%{{.*}}) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_7:.*]] = fir.if %[[VAL_1]] -> (!fir.heap>) { -! CHECK: %[[VAL_8:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_9:.*]]:3 = fir.box_dims %[[VAL_6]], %[[VAL_8]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_10:.*]] = fir.allocmem !fir.array, %[[VAL_9]]#1 {uniq_name = ".copyinout"} -! CHECK: fir.call @_FortranAAssignTemporary -! CHECK: fir.result %[[VAL_10]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_23:.*]] = fir.zero_bits !fir.heap> -! CHECK: fir.result %[[VAL_23]] : !fir.heap> -! CHECK: } -! CHECK: %[[not_contiguous:.*]] = arith.cmpi eq, %[[is_contiguous]], %false : i1 -! CHECK: %[[and:.*]] = arith.andi %[[VAL_1]], %[[not_contiguous]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_27:.*]] : (!fir.heap>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[VAL_26]]) {{.*}}: (!fir.ref>) -> () -! CHECK: fir.if %[[and]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } + ! CHECK: %[[IS_PRESENT:.*]] = fir.is_present %[[DECL]]#0 : (!fir.box>) -> i1 + ! CHECK: %[[ARG:.*]]:3 = fir.if %[[IS_PRESENT]] -> (!fir.ref>, i1, !fir.box>) { + ! CHECK: %[[COPY_IN:.*]]:2 = hlfir.copy_in %[[DECL]]#0 to %[[ALLOCA]] : (!fir.box>, !fir.ref>>>) -> (!fir.box>, i1) + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[COPY_IN]]#0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ref>) -> !fir.ref> + ! CHECK: fir.result %[[REF]], %[[COPY_IN]]#1, %[[DECL]]#0 : !fir.ref>, i1, !fir.box> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: %[[FALSE:.*]] = arith.constant false + ! CHECK: %[[ABSENT_BOX:.*]] = fir.absent !fir.box> + ! CHECK: fir.result %[[ABSENT]], %[[FALSE]], %[[ABSENT_BOX]] : !fir.ref>, i1, !fir.box> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[ARG]]#0) {{.*}} : (!fir.ref>) -> () + ! CHECK: hlfir.copy_out %[[ALLOCA]], %[[ARG]]#1 to %[[ARG]]#2 : (!fir.ref>>>, i1, !fir.box>) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_opt_assumed_shape_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box>> {fir.bindc_name = "c", fir.optional}) { subroutine pass_opt_assumed_shape_char(c) character(*), optional :: c(:) + ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.box>>> + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_opt_assumed_shape_charEc"{{.*}} call takes_opt_explicit_shape_char(c) -! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]] : (!fir.box>>) -> i1 -! CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ref>> -! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_6:.*]] = fir.embox %[[VAL_2]](%[[VAL_4]]) typeparams %[[VAL_5]] : (!fir.ref>>, !fir.shape<1>, index) -> !fir.box>> -! CHECK: %[[VAL_7:.*]] = arith.select %[[VAL_1]], %[[VAL_0]], %[[VAL_6]] : !fir.box>> -! CHECK: %[[box_none:.*]] = fir.convert %[[VAL_7]] : (!fir.box>>) -> !fir.box -! CHECK: %[[is_contiguous:.*]] = fir.call @_FortranAIsContiguous(%[[box_none]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_8:.*]] = fir.if %[[VAL_1]] -> (!fir.heap>>) { -! CHECK: %[[addr:.*]] = fir.if %[[is_contiguous]] -> (!fir.heap>>) { -! CHECK: %[[res:.*]] = fir.box_addr %[[VAL_7]] : (!fir.box>>) -> !fir.heap>> -! CHECK: fir.result %[[res]] : !fir.heap>> -! CHECK: } else { -! CHECK: %[[box_elesize:.*]] = fir.box_elesize %[[VAL_7]] : (!fir.box>>) -> index -! CHECK: %[[temp:.*]] = fir.allocmem !fir.array>(%[[box_elesize]] : index), %{{.*}}#1 {uniq_name = ".copyinout"} -! CHECK: fir.call @_FortranAAssignTemporary -! CHECK: fir.result %[[VAL_12]] : !fir.heap>> -! CHECK: } else { -! CHECK: %[[VAL_44:.*]] = fir.zero_bits !fir.heap>> -! CHECK: fir.result %[[VAL_44]] : !fir.heap>> -! CHECK: } -! CHECK: %[[VAL_45:.*]] = fir.box_elesize %[[VAL_7]] : (!fir.box>>) -> index -! CHECK: %[[not_contiguous:.*]] = arith.cmpi eq, %[[is_contiguous]], %false : i1 -! CHECK: %[[and:.*]] = arith.andi %[[VAL_1]], %[[not_contiguous]] : i1 -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_49:.*]] : (!fir.heap>>) -> !fir.ref> -! CHECK: %[[VAL_50:.*]] = fir.emboxchar %[[VAL_48]], %[[VAL_45]] : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[VAL_50]]) {{.*}}: (!fir.boxchar<1>) -> () -! CHECK: fir.if %[[and]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } + ! CHECK: %[[IS_PRESENT:.*]] = fir.is_present %[[DECL]]#0 : (!fir.box>>) -> i1 + ! CHECK: %[[ARG:.*]]:3 = fir.if %[[IS_PRESENT]] -> (!fir.boxchar<1>, i1, !fir.box>>) { + ! CHECK: %[[COPY_IN:.*]]:2 = hlfir.copy_in %[[DECL]]#0 to %[[ALLOCA]] : (!fir.box>>, !fir.ref>>>>) -> (!fir.box>>, i1) + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[COPY_IN]]#0 : (!fir.box>>) -> !fir.ref>> + ! CHECK: %[[ELE_SIZE:.*]] = fir.box_elesize %[[COPY_IN]]#0 : (!fir.box>>) -> index + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ref>>) -> !fir.ref> + ! CHECK: %[[EMBOX:.*]] = fir.emboxchar %[[REF]], %[[ELE_SIZE]] : (!fir.ref>, index) -> !fir.boxchar<1> + ! CHECK: fir.result %[[EMBOX]], %[[COPY_IN]]#1, %[[DECL]]#0 : !fir.boxchar<1>, i1, !fir.box>> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxchar<1> + ! CHECK: %[[FALSE:.*]] = arith.constant false + ! CHECK: %[[ABSENT_BOX:.*]] = fir.absent !fir.box>> + ! CHECK: fir.result %[[ABSENT]], %[[FALSE]], %[[ABSENT_BOX]] : !fir.boxchar<1>, i1, !fir.box>> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[ARG]]#0) {{.*}} : (!fir.boxchar<1>) -> () + ! CHECK: hlfir.copy_out %[[ALLOCA]], %[[ARG]]#1 to %[[ARG]]#2 : (!fir.ref>>>>, i1, !fir.box>>) -> () end subroutine ! ----------------------------------------------------------------------------- @@ -279,35 +285,38 @@ subroutine pass_opt_assumed_shape_char(c) ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.contiguous, fir.optional}) { subroutine pass_opt_contiguous_assumed_shape(x) real, optional, contiguous :: x(:) + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_opt_contiguous_assumed_shapeEx"{{.*}} call takes_opt_explicit_shape(x) -! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]] : (!fir.box>) -> i1 -! CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ref> -! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = fir.embox %[[VAL_2]](%[[VAL_4]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -! CHECK: %[[VAL_6:.*]] = arith.select %[[VAL_1]], %[[VAL_0]], %[[VAL_5]] : !fir.box> -! CHECK: %[[VAL_7:.*]] = fir.box_addr %[[VAL_6]] : (!fir.box>) -> !fir.ref> -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.ref>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[VAL_8]]) {{.*}}: (!fir.ref>) -> () + ! CHECK: %[[IS_PRESENT:.*]] = fir.is_present %[[DECL]]#0 : (!fir.box>) -> i1 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.ref>) { + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[DECL]]#1 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ref>) -> !fir.ref> + ! CHECK: fir.result %[[REF]] : !fir.ref> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: fir.result %[[ABSENT]] : !fir.ref> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[ARG]]) {{.*}} : (!fir.ref>) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_opt_contiguous_assumed_shape_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box>> {fir.bindc_name = "c", fir.contiguous, fir.optional}) { subroutine pass_opt_contiguous_assumed_shape_char(c) character(*), optional, contiguous :: c(:) + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_opt_contiguous_assumed_shape_charEc"{{.*}} call takes_opt_explicit_shape_char(c) -! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]] : (!fir.box>>) -> i1 -! CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ref>> -! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_6:.*]] = fir.embox %[[VAL_2]](%[[VAL_4]]) typeparams %[[VAL_5]] : (!fir.ref>>, !fir.shape<1>, index) -> !fir.box>> -! CHECK: %[[VAL_7:.*]] = arith.select %[[VAL_1]], %[[VAL_0]], %[[VAL_6]] : !fir.box>> -! CHECK: %[[VAL_8:.*]] = fir.box_addr %[[VAL_7]] : (!fir.box>>) -> !fir.ref>> -! CHECK: %[[VAL_9:.*]] = fir.box_elesize %[[VAL_7]] : (!fir.box>>) -> index -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_8]] : (!fir.ref>>) -> !fir.ref> -! CHECK: %[[VAL_11:.*]] = fir.emboxchar %[[VAL_10]], %[[VAL_9]] : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[VAL_11]]) {{.*}}: (!fir.boxchar<1>) -> () + ! CHECK: %[[IS_PRESENT:.*]] = fir.is_present %[[DECL]]#0 : (!fir.box>>) -> i1 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.boxchar<1>) { + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[DECL]]#1 : (!fir.box>>) -> !fir.ref>> + ! CHECK: %[[ELE_SIZE:.*]] = fir.box_elesize %[[DECL]]#1 : (!fir.box>>) -> index + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ref>>) -> !fir.ref> + ! CHECK: %[[EMBOX:.*]] = fir.emboxchar %[[REF]], %[[ELE_SIZE]] : (!fir.ref>, index) -> !fir.boxchar<1> + ! CHECK: fir.result %[[EMBOX]] : !fir.boxchar<1> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxchar<1> + ! CHECK: fir.result %[[ABSENT]] : !fir.boxchar<1> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[ARG]]) {{.*}} : (!fir.boxchar<1>) -> () end subroutine ! ----------------------------------------------------------------------------- @@ -320,48 +329,92 @@ subroutine pass_opt_contiguous_assumed_shape_char(c) ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>{{.*}}) { subroutine pass_allocatable_array(i) real, allocatable :: i(:) + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_allocatable_arrayEi"{{.*}} call takes_opt_explicit_shape(i) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.heap> -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.heap>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[VAL_3]]) {{.*}}: (!fir.ref>) -> () + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>) -> !fir.heap> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.heap>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.ref>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[BOX_ADDR2:.*]] = fir.box_addr %[[LOAD2]] : (!fir.box>>) -> !fir.heap> + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR2]] : (!fir.heap>) -> !fir.ref> + ! CHECK: fir.result %[[REF]] : !fir.ref> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: fir.result %[[ABSENT]] : !fir.ref> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[ARG]]) {{.*}} : (!fir.ref>) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_allocatable_array_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>>{{.*}}) { subroutine pass_allocatable_array_char(c) character(:), allocatable :: c(:) + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_allocatable_array_charEc"{{.*}} call takes_opt_explicit_shape_char(c) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>>> -! CHECK: %[[VAL_2:.*]] = fir.box_elesize %[[VAL_1]] : (!fir.box>>>) -> index -! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>>) -> !fir.heap>> -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.heap>>) -> !fir.ref> -! CHECK: %[[VAL_5:.*]] = fir.emboxchar %[[VAL_4]], %[[VAL_2]] : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[VAL_5]]) {{.*}}: (!fir.boxchar<1>) -> () + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>>> + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>>) -> !fir.heap>> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.heap>>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.boxchar<1>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>>> + ! CHECK: %[[BOX_ADDR2:.*]] = fir.box_addr %[[LOAD2]] : (!fir.box>>>) -> !fir.heap>> + ! CHECK: %[[ELE_SIZE:.*]] = fir.box_elesize %[[LOAD2]] : (!fir.box>>>) -> index + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR2]] : (!fir.heap>>) -> !fir.ref> + ! CHECK: %[[EMBOX:.*]] = fir.emboxchar %[[REF]], %[[ELE_SIZE]] : (!fir.ref>, index) -> !fir.boxchar<1> + ! CHECK: fir.result %[[EMBOX]] : !fir.boxchar<1> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxchar<1> + ! CHECK: fir.result %[[ABSENT]] : !fir.boxchar<1> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[ARG]]) {{.*}} : (!fir.boxchar<1>) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_contiguous_pointer_array( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>> {fir.bindc_name = "i", fir.contiguous}) { subroutine pass_contiguous_pointer_array(i) real, pointer, contiguous :: i(:) + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_contiguous_pointer_arrayEi"{{.*}} call takes_opt_explicit_shape(i) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>> -! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>) -> !fir.ptr> -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ptr>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[VAL_3]]) {{.*}}: (!fir.ref>) -> () + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>) -> !fir.ptr> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ptr>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.ref>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[BOX_ADDR2:.*]] = fir.box_addr %[[LOAD2]] : (!fir.box>>) -> !fir.ptr> + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR2]] : (!fir.ptr>) -> !fir.ref> + ! CHECK: fir.result %[[REF]] : !fir.ref> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: fir.result %[[ABSENT]] : !fir.ref> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape(%[[ARG]]) {{.*}} : (!fir.ref>) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_contiguous_pointer_array_char( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>>>> {fir.bindc_name = "c", fir.contiguous}) { subroutine pass_contiguous_pointer_array_char(c) character(:), pointer, contiguous :: c(:) + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_contiguous_pointer_array_charEc"{{.*}} call takes_opt_explicit_shape_char(c) -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>>>> -! CHECK: %[[VAL_2:.*]] = fir.box_elesize %[[VAL_1]] : (!fir.box>>>) -> index -! CHECK: %[[VAL_3:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>>>) -> !fir.ptr>> -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ptr>>) -> !fir.ref> -! CHECK: %[[VAL_5:.*]] = fir.emboxchar %[[VAL_4]], %[[VAL_2]] : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[VAL_5]]) {{.*}}: (!fir.boxchar<1>) -> () + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>>> + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>>) -> !fir.ptr>> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ptr>>) -> i64 + ! CHECK: %[[IS_PRESENT:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0_i64 : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_PRESENT]] -> (!fir.boxchar<1>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>>> + ! CHECK: %[[BOX_ADDR2:.*]] = fir.box_addr %[[LOAD2]] : (!fir.box>>>) -> !fir.ptr>> + ! CHECK: %[[ELE_SIZE:.*]] = fir.box_elesize %[[LOAD2]] : (!fir.box>>>) -> index + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR2]] : (!fir.ptr>>) -> !fir.ref> + ! CHECK: %[[EMBOX:.*]] = fir.emboxchar %[[REF]], %[[ELE_SIZE]] : (!fir.ref>, index) -> !fir.boxchar<1> + ! CHECK: fir.result %[[EMBOX]] : !fir.boxchar<1> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxchar<1> + ! CHECK: fir.result %[[ABSENT]] : !fir.boxchar<1> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape_char(%[[ARG]]) {{.*}} : (!fir.boxchar<1>) -> () end subroutine ! ----------------------------------------------------------------------------- @@ -376,60 +429,44 @@ subroutine pass_contiguous_pointer_array_char(c) ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { subroutine pass_opt_assumed_shape_to_intentin(x) real, optional :: x(:) + ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.box>> + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_opt_assumed_shape_to_intentinEx"{{.*}} call takes_opt_explicit_shape_intentin(x) -! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]] : (!fir.box>) -> i1 -! CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ref> -! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = fir.embox %[[VAL_2]](%[[VAL_4]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -! CHECK: %[[VAL_6:.*]] = arith.select %[[VAL_1]], %[[VAL_0]], %[[VAL_5]] : !fir.box> -! CHECK: %[[box_none:.*]] = fir.convert %[[VAL_6]] : (!fir.box>) -> !fir.box -! CHECK: %[[is_contiguous:.*]] = fir.call @_FortranAIsContiguous(%[[box_none]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_7:.*]] = fir.if %[[VAL_1]] -> (!fir.heap>) { -! CHECK: %[[VAL_10:.*]] = fir.allocmem !fir.array -! CHECK: fir.call @_FortranAAssignTemporary -! CHECK: fir.result %[[VAL_10]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_23:.*]] = fir.zero_bits !fir.heap> -! CHECK: fir.result %[[VAL_23]] : !fir.heap> -! CHECK: } -! CHECK: %[[not_contiguous:.*]] = arith.cmpi eq, %[[is_contiguous]], %false : i1 -! CHECK: %[[and:.*]] = arith.andi %[[VAL_1]], %[[not_contiguous]] : i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_7]] : (!fir.heap>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_opt_explicit_shape_intentin(%[[VAL_24]]) {{.*}}: (!fir.ref>) -> () -! CHECK: fir.if %[[and]] { -! CHECK: fir.zero -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } + ! CHECK: %[[IS_PRESENT:.*]] = fir.is_present %[[DECL]]#0 : (!fir.box>) -> i1 + ! CHECK: %[[ARG:.*]]:2 = fir.if %[[IS_PRESENT]] -> (!fir.ref>, i1) { + ! CHECK: %[[COPY_IN:.*]]:2 = hlfir.copy_in %[[DECL]]#0 to %[[ALLOCA]] : (!fir.box>, !fir.ref>>>) -> (!fir.box>, i1) + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[COPY_IN]]#0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ref>) -> !fir.ref> + ! CHECK: fir.result %[[REF]], %[[COPY_IN]]#1 : !fir.ref>, i1 + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: %[[FALSE:.*]] = arith.constant false + ! CHECK: fir.result %[[ABSENT]], %[[FALSE]] : !fir.ref>, i1 + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape_intentin(%[[ARG]]#0) {{.*}} : (!fir.ref>) -> () + ! CHECK: hlfir.copy_out %[[ALLOCA]], %[[ARG]]#1 : (!fir.ref>>>, i1) -> () end subroutine ! CHECK-LABEL: func @_QMoptional_testsPpass_opt_assumed_shape_to_intentout( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { subroutine pass_opt_assumed_shape_to_intentout(x) real, optional :: x(:) + ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.box>> + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}}uniq_name = "_QMoptional_testsFpass_opt_assumed_shape_to_intentoutEx"{{.*}} call takes_opt_explicit_shape_intentout(x) -! CHECK: %[[VAL_1:.*]] = fir.is_present %[[VAL_0]] : (!fir.box>) -> i1 -! CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ref> -! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = fir.embox %[[VAL_2]](%[[VAL_4]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -! CHECK: %[[VAL_6:.*]] = arith.select %[[VAL_1]], %[[VAL_0]], %[[VAL_5]] : !fir.box> -! CHECK: %[[box_none:.*]] = fir.convert %[[VAL_6]] : (!fir.box>) -> !fir.box -! CHECK: %[[is_contiguous:.*]] = fir.call @_FortranAIsContiguous(%[[box_none]]) {{.*}}: (!fir.box) -> i1 -! CHECK: %[[VAL_7:.*]] = fir.if %[[VAL_1]] -> (!fir.heap>) { -! CHECK: %[[VAL_10:.*]] = fir.allocmem !fir.array -! CHECK-NOT: fir.call @_FortranAAssignTemporary -! CHECK: fir.result %[[VAL_10]] : !fir.heap> -! CHECK: } else { -! CHECK: %[[VAL_11:.*]] = fir.zero_bits !fir.heap> -! CHECK: fir.result %[[VAL_11]] : !fir.heap> -! CHECK: } -! CHECK: %[[not_contiguous:.*]] = arith.cmpi eq, %[[is_contiguous]], %false : i1 -! CHECK: %[[and:.*]] = arith.andi %[[VAL_1]], %[[not_contiguous]] : i1 -! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_7]] : (!fir.heap>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_opt_explicit_shape_intentout(%[[VAL_14]]) {{.*}}: (!fir.ref>) -> () -! CHECK: fir.if %[[and]] { -! CHECK: fir.call @_FortranACopyOutAssign -! CHECK: } + ! CHECK: %[[IS_PRESENT:.*]] = fir.is_present %[[DECL]]#0 : (!fir.box>) -> i1 + ! CHECK: %[[ARG:.*]]:3 = fir.if %[[IS_PRESENT]] -> (!fir.ref>, i1, !fir.box>) { + ! CHECK: %[[COPY_IN:.*]]:2 = hlfir.copy_in %[[DECL]]#0 to %[[ALLOCA]] : (!fir.box>, !fir.ref>>>) -> (!fir.box>, i1) + ! CHECK: %[[BOX_ADDR:.*]] = fir.box_addr %[[COPY_IN]]#0 : (!fir.box>) -> !fir.ref> + ! CHECK: %[[REF:.*]] = fir.convert %[[BOX_ADDR]] : (!fir.ref>) -> !fir.ref> + ! CHECK: fir.result %[[REF]], %[[COPY_IN]]#1, %[[DECL]]#0 : !fir.ref>, i1, !fir.box> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: %[[FALSE:.*]] = arith.constant false + ! CHECK: %[[ABSENT_BOX:.*]] = fir.absent !fir.box> + ! CHECK: fir.result %[[ABSENT]], %[[FALSE]], %[[ABSENT_BOX]] : !fir.ref>, i1, !fir.box> + ! CHECK: } + ! CHECK: fir.call @_QPtakes_opt_explicit_shape_intentout(%[[ARG]]#0) {{.*}} : (!fir.ref>) -> () + ! CHECK: hlfir.copy_out %[[ALLOCA]], %[[ARG]]#1 to %[[ARG]]#2 : (!fir.ref>>>, i1, !fir.box>) -> () end subroutine end module diff --git a/flang/test/Lower/dummy-argument-optional.f90 b/flang/test/Lower/dummy-argument-optional.f90 index a6749b6528e81..d0972f157fa11 100644 --- a/flang/test/Lower/dummy-argument-optional.f90 +++ b/flang/test/Lower/dummy-argument-optional.f90 @@ -1,5 +1,5 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: %flang_fc1 -fdefault-integer-8 -emit-fir -flang-deprecated-no-hlfir %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s +! RUN: %flang_fc1 -fdefault-integer-8 -emit-hlfir %s -o - | FileCheck %s ! Test OPTIONAL lowering on caller/callee and PRESENT intrinsic. module opt @@ -11,73 +11,79 @@ module opt ! Test simple scalar optional ! CHECK-LABEL: func @_QMoptPintrinsic_scalar( -! CHECK-SAME: %[[arg0:.*]]: !fir.ref {fir.bindc_name = "x", fir.optional}) { +! CHECK-SAME: %[[ARG0:.*]]: !fir.ref {fir.bindc_name = "x", fir.optional}) { subroutine intrinsic_scalar(x) real, optional :: x - ! CHECK: fir.is_present %[[arg0]] : (!fir.ref) -> i1 + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] {{.*}}uniq_name = "_QMoptFintrinsic_scalarEx"{{.*}} + ! CHECK: fir.is_present %[[DECL]]#0 : (!fir.ref) -> i1 print *, present(x) end subroutine ! CHECK-LABEL: @_QMoptPcall_intrinsic_scalar() subroutine call_intrinsic_scalar() - ! CHECK: %[[x:.*]] = fir.alloca f32 + ! CHECK: %[[X:.*]] = fir.alloca f32 + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] real :: x - ! CHECK: fir.call @_QMoptPintrinsic_scalar(%[[x]]) {{.*}}: (!fir.ref) -> () + ! CHECK: fir.call @_QMoptPintrinsic_scalar(%[[X_DECL]]#0) {{.*}}: (!fir.ref) -> () call intrinsic_scalar(x) - ! CHECK: %[[absent:.*]] = fir.absent !fir.ref - ! CHECK: fir.call @_QMoptPintrinsic_scalar(%[[absent]]) {{.*}}: (!fir.ref) -> () + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref + ! CHECK: fir.call @_QMoptPintrinsic_scalar(%[[ABSENT]]) {{.*}}: (!fir.ref) -> () call intrinsic_scalar() end subroutine ! Test explicit shape array optional ! CHECK-LABEL: func @_QMoptPintrinsic_f77_array( -! CHECK-SAME: %[[arg0:.*]]: !fir.ref> {fir.bindc_name = "x", fir.optional}) { +! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "x", fir.optional}) { subroutine intrinsic_f77_array(x) real, optional :: x(100) - ! CHECK: fir.is_present %[[arg0]] : (!fir.ref>) -> i1 + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]]{{.*}}uniq_name = "_QMoptFintrinsic_f77_arrayEx"{{.*}} + ! CHECK: fir.is_present %[[DECL]]#0 : (!fir.ref>) -> i1 print *, present(x) end subroutine ! CHECK-LABEL: func @_QMoptPcall_intrinsic_f77_array() subroutine call_intrinsic_f77_array() - ! CHECK: %[[x:.*]] = fir.alloca !fir.array<100xf32> + ! CHECK: %[[X:.*]] = fir.alloca !fir.array<100xf32> real :: x(100) - ! CHECK: fir.call @_QMoptPintrinsic_f77_array(%[[x]]) {{.*}}: (!fir.ref>) -> () + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] + ! CHECK: fir.call @_QMoptPintrinsic_f77_array(%[[X_DECL]]#0) {{.*}}: (!fir.ref>) -> () call intrinsic_f77_array(x) - ! CHECK: %[[absent:.*]] = fir.absent !fir.ref> - ! CHECK: fir.call @_QMoptPintrinsic_f77_array(%[[absent]]) {{.*}}: (!fir.ref>) -> () + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref> + ! CHECK: fir.call @_QMoptPintrinsic_f77_array(%[[ABSENT]]) {{.*}}: (!fir.ref>) -> () call intrinsic_f77_array() end subroutine ! Test optional character scalar ! CHECK-LABEL: func @_QMoptPcharacter_scalar( -! CHECK-SAME: %[[arg0:.*]]: !fir.boxchar<1> {fir.bindc_name = "x", fir.optional}) { +! CHECK-SAME: %[[ARG0:.*]]: !fir.boxchar<1> {fir.bindc_name = "x", fir.optional}) { subroutine character_scalar(x) - ! CHECK: %[[unboxed:.*]]:2 = fir.unboxchar %[[arg0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) - ! CHECK: %[[ref:.*]] = fir.convert %[[unboxed]]#0 : (!fir.ref>) -> !fir.ref> + ! CHECK: %[[UNBOX:.*]]:2 = fir.unboxchar %[[ARG0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) + ! CHECK: %[[REF:.*]] = fir.convert %[[UNBOX]]#0 : (!fir.ref>) -> !fir.ref> + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[REF]] typeparams %c10 dummy_scope %{{.*}} arg 1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QMoptFcharacter_scalarEx"} : (!fir.ref>, index, !fir.dscope) -> (!fir.ref>, !fir.ref>) character(10), optional :: x - ! CHECK: fir.is_present %[[ref]] : (!fir.ref>) -> i1 + ! CHECK: fir.is_present %[[DECL]]#0 : (!fir.ref>) -> i1 print *, present(x) end subroutine ! CHECK-LABEL: func @_QMoptPcall_character_scalar() subroutine call_character_scalar() - ! CHECK: %[[addr:.*]] = fir.alloca !fir.char<1,10> + ! CHECK: %[[X:.*]] = fir.alloca !fir.char<1,10> character(10) :: x - ! CHECK: %[[x:.*]] = fir.emboxchar %[[addr]], {{.*}} - ! CHECK: fir.call @_QMoptPcharacter_scalar(%[[x]]) {{.*}}: (!fir.boxchar<1>) -> () + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] + ! CHECK: %[[EMBOX:.*]] = fir.emboxchar %[[X_DECL]]#0, %c10 : (!fir.ref>, index) -> !fir.boxchar<1> + ! CHECK: fir.call @_QMoptPcharacter_scalar(%[[EMBOX]]) {{.*}}: (!fir.boxchar<1>) -> () call character_scalar(x) - ! CHECK: %[[absent:.*]] = fir.absent !fir.boxchar<1> - ! CHECK: fir.call @_QMoptPcharacter_scalar(%[[absent]]) {{.*}}: (!fir.boxchar<1>) -> () + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxchar<1> + ! CHECK: fir.call @_QMoptPcharacter_scalar(%[[ABSENT]]) {{.*}}: (!fir.boxchar<1>) -> () call character_scalar() end subroutine ! Test optional character function ! CHECK-LABEL: func @_QMoptPchar_proc( -! CHECK-SAME: %[[arg0:.*]]: !fir.ref>, +! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>, character(len=3) function char_proc(i) integer :: i char_proc = "XYZ" end function ! CHECK-LABEL: func @_QMoptPuse_char_proc( -! CHECK-SAME: %[[arg0:.*]]: tuple ()>, i64> {fir.char_proc}, +! CHECK-SAME: %[[ARG0:.*]]: tuple ()>, i64> {fir.char_proc}, subroutine use_char_proc(f, c) optional :: f interface @@ -86,9 +92,8 @@ character(len=3) function f(i) end function end interface character(len=3) :: c -! CHECK: %[[boxProc:.*]] = fir.extract_value %[[arg0]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> -! CHECK: %[[procAddr:.*]] = fir.box_addr %[[boxProc]] : (!fir.boxproc<() -> ()>) -> (() -> ()) -! CHECK: %{{.*}} = fir.is_present %[[procAddr]] : (() -> ()) -> i1 +! CHECK: %[[BOXPROC:.*]] = fir.extract_value %[[ARG0]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[IS_PRESENT:.*]] = fir.is_present %{{.*}} : (!fir.boxproc<() -> ()>) -> i1 if (present(f)) then c = f(0) else @@ -98,87 +103,97 @@ character(len=3) function f(i) ! CHECK-LABEL: func @_QMoptPcall_use_char_proc( subroutine call_use_char_proc() character(len=3) :: c -! CHECK: %[[boxProc:.*]] = fir.absent !fir.boxproc<() -> ()> -! CHECK: %[[undef:.*]] = fir.undefined index -! CHECK: %[[charLen:.*]] = fir.convert %[[undef]] : (index) -> i64 -! CHECK: %[[tuple:.*]] = fir.undefined tuple ()>, i64> -! CHECK: %[[tuple2:.*]] = fir.insert_value %[[tuple]], %[[boxProc]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> -! CHECK: %[[tuple3:.*]] = fir.insert_value %[[tuple2]], %[[charLen]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> -! CHECK: fir.call @_QMoptPuse_char_proc(%[[tuple3]], %{{.*}}){{.*}} : (tuple ()>, i64>, !fir.boxchar<1>) -> () +! CHECK: %[[ABSENT:.*]] = fir.absent !fir.boxproc<() -> ()> +! CHECK: %[[UNDEF:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[TUPLE:.*]] = fir.insert_value %[[UNDEF]], %[[ABSENT]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[TUPLE2:.*]] = fir.insert_value %[[TUPLE]], %{{.*}}, [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: fir.call @_QMoptPuse_char_proc(%[[TUPLE2]], %{{.*}}){{.*}} : (tuple ()>, i64>, !fir.boxchar<1>) -> () call use_char_proc(c=c) -! CHECK: %[[funcAddr:.*]] = fir.address_of(@_QMoptPchar_proc) : (!fir.ref>, index, {{.*}}) -> !fir.boxchar<1> -! CHECK: %[[c3:.*]] = arith.constant 3 : i64 -! CHECK: %[[boxProc2:.*]] = fir.emboxproc %[[funcAddr]] : ((!fir.ref>, index, {{.*}}) -> !fir.boxchar<1>) -> !fir.boxproc<() -> ()> -! CHECK: %[[tuple4:.*]] = fir.undefined tuple ()>, i64> -! CHECK: %[[tuple5:.*]] = fir.insert_value %[[tuple4]], %[[boxProc2]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> -! CHECK: %[[tuple6:.*]] = fir.insert_value %[[tuple5]], %[[c3]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> -! CHECK: fir.call @_QMoptPuse_char_proc(%[[tuple6]], {{.*}}){{.*}} : (tuple ()>, i64>, !fir.boxchar<1>) -> () +! CHECK: %[[ADDR:.*]] = fir.address_of(@_QMoptPchar_proc) : (!fir.ref>, index, {{.*}}) -> !fir.boxchar<1> +! CHECK: %[[BOXPROC:.*]] = fir.emboxproc %[[ADDR]] : ((!fir.ref>, index, {{.*}}) -> !fir.boxchar<1>) -> !fir.boxproc<() -> ()> +! CHECK: %[[UNDEF:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[TUPLE:.*]] = fir.insert_value %[[UNDEF]], %[[BOXPROC]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[TUPLE2:.*]] = fir.insert_value %[[TUPLE]], %{{.*}}, [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: fir.call @_QMoptPuse_char_proc(%[[TUPLE2]], {{.*}}){{.*}} : (tuple ()>, i64>, !fir.boxchar<1>) -> () call use_char_proc(char_proc, c) end subroutine ! Test optional assumed shape ! CHECK-LABEL: func @_QMoptPassumed_shape( -! CHECK-SAME: %[[arg0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { +! CHECK-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "x", fir.optional}) { subroutine assumed_shape(x) real, optional :: x(:) - ! CHECK: fir.is_present %[[arg0]] : (!fir.box>) -> i1 + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] {{.*}}uniq_name = "_QMoptFassumed_shapeEx"{{.*}} + ! CHECK: fir.is_present %[[DECL]]#1 : (!fir.box>) -> i1 print *, present(x) end subroutine ! CHECK: func @_QMoptPcall_assumed_shape() subroutine call_assumed_shape() - ! CHECK: %[[addr:.*]] = fir.alloca !fir.array<100xf32> + ! CHECK: %[[X:.*]] = fir.alloca !fir.array<100xf32> real :: x(100) - ! CHECK: %[[embox:.*]] = fir.embox %[[addr]] - ! CHECK: %[[x:.*]] = fir.convert %[[embox]] : (!fir.box>) -> !fir.box> - ! CHECK: fir.call @_QMoptPassumed_shape(%[[x]]) {{.*}}: (!fir.box>) -> () + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] + ! CHECK: %[[EMBOX:.*]] = fir.embox %[[X_DECL]]#0(%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> + ! CHECK: %[[BOX:.*]] = fir.convert %[[EMBOX]] : (!fir.box>) -> !fir.box> + ! CHECK: fir.call @_QMoptPassumed_shape(%[[BOX]]) {{.*}}: (!fir.box>) -> () call assumed_shape(x) - ! CHECK: %[[absent:.*]] = fir.absent !fir.box> - ! CHECK: fir.call @_QMoptPassumed_shape(%[[absent]]) {{.*}}: (!fir.box>) -> () + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.box> + ! CHECK: fir.call @_QMoptPassumed_shape(%[[ABSENT]]) {{.*}}: (!fir.box>) -> () call assumed_shape() end subroutine ! Test optional allocatable ! CHECK: func @_QMoptPallocatable_array( -! CHECK-SAME: %[[arg0:.*]]: !fir.ref>>> {fir.bindc_name = "x", fir.optional}) { +! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>> {fir.bindc_name = "x", fir.optional}) { subroutine allocatable_array(x) real, allocatable, optional :: x(:) - ! CHECK: fir.is_present %[[arg0]] : (!fir.ref>>>) -> i1 + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] {{.*}}uniq_name = "_QMoptFallocatable_arrayEx"{{.*}} + ! CHECK: fir.is_present %[[DECL]]#0 : (!fir.ref>>>) -> i1 print *, present(x) end subroutine ! CHECK: func @_QMoptPcall_allocatable_array() subroutine call_allocatable_array() - ! CHECK: %[[x:.*]] = fir.alloca !fir.box>> + ! CHECK: %[[X:.*]] = fir.alloca !fir.box>> real, allocatable :: x(:) - ! CHECK: fir.call @_QMoptPallocatable_array(%[[x]]) {{.*}}: (!fir.ref>>>) -> () + ! CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X]] + ! CHECK: fir.call @_QMoptPallocatable_array(%[[X_DECL]]#0) {{.*}}: (!fir.ref>>>) -> () call allocatable_array(x) - ! CHECK: %[[absent:.*]] = fir.absent !fir.ref>>> - ! CHECK: fir.call @_QMoptPallocatable_array(%[[absent]]) {{.*}}: (!fir.ref>>>) -> () + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.ref>>> + ! CHECK: fir.call @_QMoptPallocatable_array(%[[ABSENT]]) {{.*}}: (!fir.ref>>>) -> () call allocatable_array() end subroutine ! CHECK: func @_QMoptPallocatable_to_assumed_optional_array( -! CHECK-SAME: %[[arg0:.*]]: !fir.ref>>>{{.*}}) { +! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>>>{{.*}}) { subroutine allocatable_to_assumed_optional_array(x) real, allocatable :: x(:) - - ! CHECK: %[[xboxload:.*]] = fir.load %[[arg0]] : !fir.ref>>> - ! CHECK: %[[xptr:.*]] = fir.box_addr %[[xboxload]] : (!fir.box>>) -> !fir.heap> - ! CHECK: %[[xaddr:.*]] = fir.convert %[[xptr]] : (!fir.heap>) -> i64 - ! CHECK: %[[isAlloc:.*]] = arith.cmpi ne, %[[xaddr]], %c0{{.*}} : i64 - ! CHECK: %[[absent:.*]] = fir.absent !fir.box> - ! CHECK: %[[embox:.*]] = fir.embox %{{.*}} - ! CHECK: %[[actual:.*]] = arith.select %[[isAlloc]], %[[embox]], %[[absent]] : !fir.box> - ! CHECK: fir.call @_QMoptPassumed_shape(%[[actual]]) {{.*}}: (!fir.box>) -> () + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]] + ! CHECK: %[[LOAD:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[ADDR:.*]] = fir.box_addr %[[LOAD]] : (!fir.box>>) -> !fir.heap> + ! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.heap>) -> i64 + ! CHECK: %[[IS_ALLOC:.*]] = arith.cmpi ne, %[[ADDR_I64]], %c0{{.*}} : i64 + ! CHECK: %[[ARG:.*]] = fir.if %[[IS_ALLOC]] -> (!fir.box>) { + ! CHECK: %[[LOAD2:.*]] = fir.load %[[DECL]]#0 : !fir.ref>>> + ! CHECK: %[[REBOX:.*]] = fir.rebox %[[LOAD2]] : (!fir.box>>) -> !fir.box> + ! CHECK: fir.result %[[REBOX]] : !fir.box> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.box> + ! CHECK: fir.result %[[ABSENT]] : !fir.box> + ! CHECK: } + ! CHECK: fir.call @_QMoptPassumed_shape(%[[ARG]]) {{.*}}: (!fir.box>) -> () call assumed_shape(x) end subroutine ! CHECK-LABEL: func @_QMoptPalloc_component_to_optional_assumed_shape( subroutine alloc_component_to_optional_assumed_shape(x) type(t) :: x(100) - ! CHECK-DAG: %[[isAlloc:.*]] = arith.cmpi ne - ! CHECK-DAG: %[[absent:.*]] = fir.absent !fir.box> - ! CHECK: %[[select:.*]] = arith.select %[[isAlloc]], %{{.*}}, %[[absent]] : !fir.box> - ! CHECK: fir.call @_QMoptPassumed_shape(%[[select]]) + ! CHECK: %[[IS_ALLOC:.*]] = arith.cmpi ne + ! CHECK: %[[SELECT:.*]] = fir.if %[[IS_ALLOC]] -> (!fir.box>) { + ! CHECK: fir.result %{{.*}} : !fir.box> + ! CHECK: } else { + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.box> + ! CHECK: fir.result %[[ABSENT]] : !fir.box> + ! CHECK: } + ! CHECK: fir.call @_QMoptPassumed_shape(%[[SELECT]]) call assumed_shape(x(55)%p) end subroutine @@ -195,11 +210,8 @@ subroutine alloc_component_eval_only_once(x) ! CHECK-LABEL: func @_QMoptPnull_as_optional() { subroutine null_as_optional - ! CHECK: %[[null_ptr:.*]] = fir.alloca !fir.box> - ! CHECK: %[[null:.*]] = fir.zero_bits !fir.ptr - ! CHECK: %[[null_box:.*]] = fir.embox %[[null]] : (!fir.ptr) -> !fir.box> - ! CHECK: fir.store %[[null_box]] to %[[null_ptr]] : !fir.ref>> - ! CHECK: fir.call @_QMoptPassumed_shape(%{{.*}}) {{.*}}: (!fir.box>) -> () + ! CHECK: %[[ABSENT:.*]] = fir.absent !fir.box> + ! CHECK: fir.call @_QMoptPassumed_shape(%[[ABSENT]]) {{.*}}: (!fir.box>) -> () call assumed_shape(null()) end subroutine null_as_optional diff --git a/flang/test/Lower/dummy-arguments.f90 b/flang/test/Lower/dummy-arguments.f90 index 331e089a60fa0..dcd2ab057a022 100644 --- a/flang/test/Lower/dummy-arguments.f90 +++ b/flang/test/Lower/dummy-arguments.f90 @@ -1,11 +1,10 @@ -! RUN: bbc -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s ! CHECK-LABEL: _QQmain program test1 - ! CHECK-DAG: %[[TMP:.*]] = fir.alloca - ! CHECK-DAG: %[[TEN:.*]] = arith.constant - ! CHECK: fir.store %[[TEN]] to %[[TMP]] - ! CHECK-NEXT: fir.call @_QFPfoo + ! CHECK: %[[C10:.*]] = arith.constant 10 : i32 + ! CHECK: %[[ASSOC:.*]]:3 = hlfir.associate %[[C10]] {adapt.valuebyref} : (i32) -> (!fir.ref, !fir.ref, i1) + ! CHECK: fir.call @_QFPfoo(%[[ASSOC]]#0) {{.*}} : (!fir.ref) -> () call foo(10) contains @@ -24,8 +23,9 @@ end program test1 ! CHECK-LABEL: func @_QPsub2 function sub2(r) real :: r(20) - ! CHECK: %[[coor:.*]] = fir.coordinate_of %arg0 - ! CHECK: = fir.call @_QPf(%[[coor]]) {{.*}}: (!fir.ref) -> f32 + ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %arg0 + ! CHECK: %[[ELT:.*]] = hlfir.designate %[[DECL]]#0 (%c1) : (!fir.ref>, index) -> !fir.ref + ! CHECK: = fir.call @_QPf(%[[ELT]]) {{.*}}: (!fir.ref) -> f32 sub2 = f(r(1)) ! CHECK: return %{{.*}} : f32 end function sub2 diff --git a/flang/test/Lower/dummy-procedure-character.f90 b/flang/test/Lower/dummy-procedure-character.f90 index 7a6bb249d30d0..36654927df221 100644 --- a/flang/test/Lower/dummy-procedure-character.f90 +++ b/flang/test/Lower/dummy-procedure-character.f90 @@ -1,12 +1,12 @@ ! Test lowering of character function dummy procedure. The length must be ! passed along the function address. -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s ! ----------------------------------------------------------------------------- ! Test passing a character function as dummy procedure ! ----------------------------------------------------------------------------- -! CHECK-LABEL: func @_QPcst_len +! CHECK-LABEL: func.func @_QPcst_len() { subroutine cst_len() interface character(7) function bar1() @@ -22,7 +22,7 @@ character(7) function bar1() ! CHECK: fir.call @_QPfoo1(%[[VAL_5]]) {{.*}}: (tuple ()>, i64>) -> () end subroutine -! CHECK-LABEL: func @_QPcst_len_array +! CHECK-LABEL: func.func @_QPcst_len_array() { subroutine cst_len_array() interface function bar1_array() @@ -39,7 +39,7 @@ function bar1_array() call foo1b(bar1_array) end subroutine -! CHECK-LABEL: func @_QPcst_len_2 +! CHECK-LABEL: func.func @_QPcst_len_2() { subroutine cst_len_2() character(7) :: bar2 external :: bar2 @@ -53,14 +53,15 @@ subroutine cst_len_2() call foo2(bar2) end subroutine -! CHECK-LABEL: func @_QPdyn_len( +! CHECK-LABEL: func.func @_QPdyn_len( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref{{.*}}) { subroutine dyn_len(n) integer :: n character(n) :: bar3 external :: bar3 +! CHECK: %[[VAL_ARG:.*]]:2 = hlfir.declare %[[VAL_0]] {{.*}} ! CHECK: %[[VAL_1:.*]] = fir.address_of(@_QPbar3) : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref +! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_ARG]]#0 : !fir.ref ! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (i32) -> i64 ! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 ! CHECK: %[[VAL_5:.*]] = arith.cmpi sgt, %[[VAL_3]], %[[VAL_4]] : i64 @@ -73,7 +74,7 @@ subroutine dyn_len(n) call foo3(bar3) end subroutine -! CHECK-LABEL: func @_QPcannot_compute_len_yet +! CHECK-LABEL: func.func @_QPcannot_compute_len_yet() { subroutine cannot_compute_len_yet() interface function bar4(n) @@ -92,7 +93,7 @@ function bar4(n) call foo4(bar4) end subroutine -! CHECK-LABEL: func @_QPcannot_compute_len_yet_2 +! CHECK-LABEL: func.func @_QPcannot_compute_len_yet_2() { subroutine cannot_compute_len_yet_2() character(*) :: bar5 external :: bar5 @@ -107,7 +108,7 @@ subroutine cannot_compute_len_yet_2() call foo5(bar5) end subroutine -! CHECK-LABEL: func @_QPforward_incoming_length +! CHECK-LABEL: func.func @_QPforward_incoming_length( ! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> {fir.char_proc}) { subroutine forward_incoming_length(bar6) character(*) :: bar6 @@ -123,7 +124,7 @@ subroutine forward_incoming_length(bar6) call foo6(bar6) end subroutine -! CHECK-LABEL: func @_QPoverride_incoming_length +! CHECK-LABEL: func.func @_QPoverride_incoming_length( ! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> {fir.char_proc}) { subroutine override_incoming_length(bar7) character(7) :: bar7 @@ -143,40 +144,56 @@ subroutine override_incoming_length(bar7) ! Test calling character dummy function ! ----------------------------------------------------------------------------- -! CHECK-LABEL: func @_QPcall_assumed_length +! CHECK-LABEL: func.func @_QPcall_assumed_length( ! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> {fir.char_proc}) { subroutine call_assumed_length(bar8) character(*) :: bar8 external :: bar8 +! CHECK: %[[VAL_CONST:.*]] = arith.constant 42 : i32 +! CHECK: %[[VAL_ASSOC:.*]]:3 = hlfir.associate %[[VAL_CONST]] {{.*}} ! CHECK: %[[VAL_3:.*]] = fir.extract_value %[[VAL_0]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> ! CHECK: %[[WAL_2:.*]] = fir.box_addr %[[VAL_3]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: %[[VAL_4:.*]] = fir.extract_value %[[VAL_0]], [1 : index] : (tuple ()>, i64>) -> i64 -! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.char<1,?>(%[[VAL_4]] : i64) {bindc_name = ".result"} -! CHECK: %[[VAL_7:.*]] = fir.convert %[[WAL_2]] : (() -> ()) -> ((!fir.ref>, index, !fir.ref) -> !fir.boxchar<1>) -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_4]] : (i64) -> index -! CHECK: fir.call %[[VAL_7]](%[[VAL_6]], %[[VAL_8]], %{{.*}}) {{.*}}: (!fir.ref>, index, !fir.ref) -> !fir.boxchar<1> +! CHECK: %[[EMBOX:.*]] = fir.emboxproc %[[WAL_2]] : (() -> ()) -> !fir.boxproc<() -> ()> +! CHECK: %[[TUPLE:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[INS1:.*]] = fir.insert_value %[[TUPLE]], %[[EMBOX]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[INS2:.*]] = fir.insert_value %[[INS1]], %[[VAL_4]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: %[[VAL_EXT0:.*]] = fir.extract_value %[[INS2]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_EXT1:.*]] = fir.extract_value %[[INS2]], [1 : index] : (tuple ()>, i64>) -> i64 +! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.char<1,?>(%[[VAL_EXT1]] : i64) {bindc_name = ".result"} +! CHECK: %[[VAL_7:.*]] = fir.box_addr %[[VAL_EXT0]] : (!fir.boxproc<() -> ()>) -> ((!fir.ref>, index, !fir.ref) -> !fir.boxchar<1>) +! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_EXT1]] : (i64) -> index +! CHECK: fir.call %[[VAL_7]](%[[VAL_6]], %[[VAL_8]], %[[VAL_ASSOC]]#0) {{.*}}: (!fir.ref>, index, !fir.ref) -> !fir.boxchar<1> call test(bar8(42)) end subroutine -! CHECK-LABEL: func @_QPcall_explicit_length +! CHECK-LABEL: func.func @_QPcall_explicit_length( ! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> {fir.char_proc}) { subroutine call_explicit_length(bar9) character(7) :: bar9 external :: bar9 ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.char<1,7> {bindc_name = ".result"} +! CHECK: %[[VAL_CONST:.*]] = arith.constant 42 : i32 +! CHECK: %[[VAL_ASSOC:.*]]:3 = hlfir.associate %[[VAL_CONST]] {{.*}} ! CHECK: %[[VAL_4:.*]] = fir.extract_value %[[VAL_0]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> ! CHECK: %[[WAL_1:.*]] = fir.box_addr %[[VAL_4]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: %[[VAL_5:.*]] = arith.constant 7 : i64 -! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i64) -> index +! CHECK: %[[EMBOX:.*]] = fir.emboxproc %[[WAL_1]] : (() -> ()) -> !fir.boxproc<() -> ()> +! CHECK: %[[TUPLE:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[INS1:.*]] = fir.insert_value %[[TUPLE]], %[[EMBOX]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[INS2:.*]] = fir.insert_value %[[INS1]], %[[VAL_5]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: %[[VAL_EXT0:.*]] = fir.extract_value %[[INS2]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_5_NEW:.*]] = arith.constant 7 : i64 +! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5_NEW]] : (i64) -> index ! CHECK: %[[C0:.*]] = arith.constant 0 : index ! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_6]], %[[C0]] : index ! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_6]], %[[C0]] : index -! CHECK: %[[VAL_8:.*]] = fir.convert %[[WAL_1]] : (() -> ()) -> ((!fir.ref>, index, !fir.ref) -> !fir.boxchar<1>) -! CHECK: fir.call %[[VAL_8]](%[[VAL_1]], %[[SELECT]], %{{.*}}) {{.*}}: (!fir.ref>, index, !fir.ref) -> !fir.boxchar<1> +! CHECK: %[[VAL_7:.*]] = fir.box_addr %[[VAL_EXT0]] : (!fir.boxproc<() -> ()>) -> ((!fir.ref>, index, !fir.ref) -> !fir.boxchar<1>) +! CHECK: fir.call %[[VAL_7]](%[[VAL_1]], %[[SELECT]], %[[VAL_ASSOC]]#0) {{.*}}: (!fir.ref>, index, !fir.ref) -> !fir.boxchar<1> call test(bar9(42)) end subroutine -! CHECK-LABEL: func @_QPcall_explicit_length_with_iface +! CHECK-LABEL: func.func @_QPcall_explicit_length_with_iface( ! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> {fir.char_proc}) { subroutine call_explicit_length_with_iface(bar10) interface @@ -185,25 +202,33 @@ function bar10(n) character(n) :: bar10 end function end interface -! CHECK: %[[VAL_1:.*]] = fir.alloca i64 ! CHECK: %[[VAL_2:.*]] = arith.constant 42 : i64 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref +! CHECK: %[[VAL_ASSOC:.*]]:3 = hlfir.associate %[[VAL_2]] {{.*}} +! CHECK: %[[VAL_DECL:.*]]:2 = hlfir.declare %[[VAL_ASSOC]]#0 {{.*}} ! CHECK: %[[VAL_3:.*]] = fir.extract_value %[[VAL_0]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> ! CHECK: %[[WAL_1:.*]] = fir.box_addr %[[VAL_3]] : (!fir.boxproc<() -> ()>) -> (() -> ()) -! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i64) -> index -! CHECK: %[[C0:.*]] = arith.constant 0 : index -! CHECK: %[[COMPI:.*]] = arith.cmpi sgt, %[[VAL_5]], %[[C0]] : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_5]], %[[C0]] : index -! CHECK: %[[VAL_6:.*]] = llvm.intr.stacksave : !llvm.ptr -! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.char<1,?>(%[[SELECT]] : index) {bindc_name = ".result"} -! CHECK: %[[VAL_8:.*]] = fir.convert %[[WAL_1]] : (() -> ()) -> ((!fir.ref>, index, !fir.ref) -> !fir.boxchar<1>) -! CHECK: fir.call %[[VAL_8]](%[[VAL_7]], %[[SELECT]], %[[VAL_1]]) {{.*}}: (!fir.ref>, index, !fir.ref) -> !fir.boxchar<1> +! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_DECL]]#0 : !fir.ref +! CHECK: %[[C0:.*]] = arith.constant 0 : i64 +! CHECK: %[[COMPI:.*]] = arith.cmpi sgt, %[[VAL_4]], %[[C0]] : i64 +! CHECK: %[[SELECT:.*]] = arith.select %[[COMPI]], %[[VAL_4]], %[[C0]] : i64 +! CHECK: %[[EMBOX:.*]] = fir.emboxproc %[[WAL_1]] : (() -> ()) -> !fir.boxproc<() -> ()> +! CHECK: %[[TUPLE:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[INS1:.*]] = fir.insert_value %[[TUPLE]], %[[EMBOX]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[INS2:.*]] = fir.insert_value %[[INS1]], %[[SELECT]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: %[[VAL_EXT0:.*]] = fir.extract_value %[[INS2]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_DECL]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i64) -> index +! CHECK: %[[C0_IDX:.*]] = arith.constant 0 : index +! CHECK: %[[CMP_IDX:.*]] = arith.cmpi sgt, %[[VAL_14]], %[[C0_IDX]] : index +! CHECK: %[[SELECT_IDX:.*]] = arith.select %[[CMP_IDX]], %[[VAL_14]], %[[C0_IDX]] : index +! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.char<1,?>(%[[SELECT_IDX]] : index) {bindc_name = ".result"} +! CHECK: %[[VAL_8:.*]] = fir.box_addr %[[VAL_EXT0]] : (!fir.boxproc<() -> ()>) -> ((!fir.ref>, index, !fir.ref) -> !fir.boxchar<1>) +! CHECK: fir.call %[[VAL_8]](%[[VAL_7]], %[[SELECT_IDX]], %[[VAL_ASSOC]]#0) {{.*}}: (!fir.ref>, index, !fir.ref) -> !fir.boxchar<1> call test(bar10(42_8)) end subroutine -! CHECK-LABEL: func @_QPhost( +! CHECK-LABEL: func.func @_QPhost( ! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> subroutine host(f) character*(*) :: f @@ -213,7 +238,7 @@ subroutine host(f) ! CHECK: fir.call @_QFhostPintern(%[[VAL_1]]) call intern() contains -! CHECK-LABEL: func private @_QFhostPintern( +! CHECK-LABEL: func.func private @_QFhostPintern( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>, i64>>> {fir.host_assoc}) subroutine intern() ! CHECK: %[[VAL_1:.*]] = arith.constant 0 : i32 @@ -222,15 +247,22 @@ subroutine intern() ! CHECK: %[[VAL_4:.*]] = fir.extract_value %[[VAL_3]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> ! CHECK: %[[WAL_1:.*]] = fir.box_addr %[[VAL_4]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: %[[VAL_5:.*]] = fir.extract_value %[[VAL_3]], [1 : index] : (tuple ()>, i64>) -> i64 -! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.char<1,?>(%[[VAL_5]] : i64) {bindc_name = ".result"} -! CHECK: %[[VAL_8:.*]] = fir.convert %[[WAL_1]] : (() -> ()) -> ((!fir.ref>, index) -> !fir.boxchar<1>) -! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_5]] : (i64) -> index -! CHECK: fir.call %[[VAL_8]](%[[VAL_7]], %[[VAL_9]]) {{.*}}: (!fir.ref>, index) -> !fir.boxchar<1> +! CHECK: %[[VAL_6:.*]] = fir.emboxproc %[[WAL_1]] : (() -> ()) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_7:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[VAL_8:.*]] = fir.insert_value %[[VAL_7]], %[[VAL_6]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[VAL_9:.*]] = fir.insert_value %[[VAL_8]], %[[VAL_5]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: %[[VAL_10:.*]] = fir.extract_value %[[VAL_9]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_11:.*]] = fir.extract_value %[[VAL_9]], [1 : index] : (tuple ()>, i64>) -> i64 +! CHECK: %[[VAL_12:.*]] = llvm.intr.stacksave : !llvm.ptr +! CHECK: %[[VAL_13:.*]] = fir.alloca !fir.char<1,?>(%[[VAL_11]] : i64) {bindc_name = ".result"} +! CHECK: %[[VAL_14:.*]] = fir.box_addr %[[VAL_10]] : (!fir.boxproc<() -> ()>) -> ((!fir.ref>, index) -> !fir.boxchar<1>) +! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_11]] : (i64) -> index +! CHECK: fir.call %[[VAL_14]](%[[VAL_13]], %[[VAL_15]]) {{.*}}: (!fir.ref>, index) -> !fir.boxchar<1> call test(f()) end subroutine end subroutine -! CHECK-LABEL: func @_QPhost2( +! CHECK-LABEL: func.func @_QPhost2( ! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> {fir.char_proc}) subroutine host2(f) ! Test that dummy length is overridden by local length even when used @@ -242,7 +274,7 @@ subroutine host2(f) ! CHECK: fir.call @_QFhost2Pintern(%[[VAL_1]]) call intern() contains -! CHECK-LABEL: func private @_QFhost2Pintern( +! CHECK-LABEL: func.func private @_QFhost2Pintern( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>, i64>>> {fir.host_assoc}) subroutine intern() ! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.char<1,42> {bindc_name = ".result"} @@ -252,11 +284,17 @@ subroutine intern() ! CHECK: %[[VAL_5:.*]] = fir.extract_value %[[VAL_4]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> ! CHECK: %[[WAL_1:.*]] = fir.box_addr %[[VAL_5]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: %[[VAL_6:.*]] = arith.constant 42 : i64 - ! CHECK: %[[VAL_7:.*]] = fir.convert %[[VAL_6]] : (i64) -> index + ! CHECK: %[[VAL_NEW_EMBOX:.*]] = fir.emboxproc %[[WAL_1]] : (() -> ()) -> !fir.boxproc<() -> ()> + ! CHECK: %[[VAL_NEW_TUPLE:.*]] = fir.undefined tuple ()>, i64> + ! CHECK: %[[VAL_INS1:.*]] = fir.insert_value %[[VAL_NEW_TUPLE]], %[[VAL_NEW_EMBOX]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> + ! CHECK: %[[VAL_INS2:.*]] = fir.insert_value %[[VAL_INS1]], %[[VAL_6]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> + ! CHECK: %[[VAL_EXT1:.*]] = fir.extract_value %[[VAL_INS2]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> + ! CHECK: %[[VAL_CONST_42:.*]] = arith.constant 42 : i64 + ! CHECK: %[[VAL_7:.*]] = fir.convert %[[VAL_CONST_42]] : (i64) -> index ! CHECK: %[[C0:.*]] = arith.constant 0 : index ! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_7]], %[[C0]] : index ! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_7]], %[[C0]] : index - ! CHECK: %[[VAL_9:.*]] = fir.convert %[[WAL_1]] : (() -> ()) -> ((!fir.ref>, index) -> !fir.boxchar<1>) + ! CHECK: %[[VAL_9:.*]] = fir.box_addr %[[VAL_EXT1]] : (!fir.boxproc<() -> ()>) -> ((!fir.ref>, index) -> !fir.boxchar<1>) ! CHECK: fir.call %[[VAL_9]](%[[VAL_1]], %[[SELECT]]) {{.*}}: (!fir.ref>, index) -> !fir.boxchar<1> call test(f()) end subroutine diff --git a/flang/test/Lower/dummy-procedure-in-entry.f90 b/flang/test/Lower/dummy-procedure-in-entry.f90 index 6ba12e1afdaa1..ee85da35275d3 100644 --- a/flang/test/Lower/dummy-procedure-in-entry.f90 +++ b/flang/test/Lower/dummy-procedure-in-entry.f90 @@ -1,7 +1,7 @@ ! Test dummy procedures that are not an argument in every entry. ! This requires creating a mock value in the entries where it is ! not an argument. -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s subroutine dummy_with_iface() interface @@ -11,40 +11,38 @@ real function x() entry dummy_with_iface_entry(x) call takes_real(x()) end subroutine -! CHECK-LABEL: func @_QPdummy_with_iface() { -! CHECK: %[[VAL_0:.*]] = fir.alloca f32 {adapt.valuebyref} +! CHECK-LABEL: func.func @_QPdummy_with_iface() { ! CHECK: %[[VAL_1:.*]] = fir.undefined !fir.boxproc<() -> ()> -! CHECK: br ^bb1 +! CHECK: cf.br ^bb1 ! CHECK: ^bb1: ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.boxproc<() -> ()>) -> (() -> f32) ! CHECK: %[[VAL_3:.*]] = fir.call %[[VAL_2]]() {{.*}}: () -> f32 -! CHECK: fir.store %[[VAL_3]] to %[[VAL_0]] : !fir.ref -! CHECK: fir.call @_QPtakes_real(%[[VAL_0]]) {{.*}}: (!fir.ref) -> () +! CHECK: %[[VAL_4:.*]]:3 = hlfir.associate %[[VAL_3]] {adapt.valuebyref} : (f32) -> (!fir.ref, !fir.ref, i1) +! CHECK: fir.call @_QPtakes_real(%[[VAL_4]]#0) {{.*}}: (!fir.ref) -> () -! CHECK-LABEL: func @_QPdummy_with_iface_entry( +! CHECK-LABEL: func.func @_QPdummy_with_iface_entry( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.boxproc<() -> ()>) { -! CHECK: %[[VAL_1:.*]] = fir.alloca f32 {adapt.valuebyref} -! CHECK: br ^bb1 +! CHECK: cf.br ^bb1 ! CHECK: ^bb1: ! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_0]] : (!fir.boxproc<() -> ()>) -> (() -> f32) ! CHECK: %[[VAL_3:.*]] = fir.call %[[VAL_2]]() {{.*}}: () -> f32 -! CHECK: fir.store %[[VAL_3]] to %[[VAL_1]] : !fir.ref -! CHECK: fir.call @_QPtakes_real(%[[VAL_1]]) {{.*}}: (!fir.ref) -> () +! CHECK: %[[VAL_4:.*]]:3 = hlfir.associate %[[VAL_3]] {adapt.valuebyref} : (f32) -> (!fir.ref, !fir.ref, i1) +! CHECK: fir.call @_QPtakes_real(%[[VAL_4]]#0) {{.*}}: (!fir.ref) -> () subroutine subroutine_dummy() entry subroutine_dummy_entry(x) call x() end subroutine -! CHECK-LABEL: func @_QPsubroutine_dummy() { +! CHECK-LABEL: func.func @_QPsubroutine_dummy() { ! CHECK: %[[VAL_0:.*]] = fir.undefined !fir.boxproc<() -> ()> -! CHECK: br ^bb1 +! CHECK: cf.br ^bb1 ! CHECK: ^bb1: ! CHECK: %[[VAL_1:.*]] = fir.box_addr %[[VAL_0]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: fir.call %[[VAL_1]]() {{.*}}: () -> () -! CHECK-LABEL: func @_QPsubroutine_dummy_entry( +! CHECK-LABEL: func.func @_QPsubroutine_dummy_entry( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.boxproc<() -> ()>) { -! CHECK: br ^bb1 +! CHECK: cf.br ^bb1 ! CHECK: ^bb1: ! CHECK: %[[VAL_1:.*]] = fir.box_addr %[[VAL_0]] : (!fir.boxproc<() -> ()>) -> (() -> ()) ! CHECK: fir.call %[[VAL_1]]() {{.*}}: () -> () diff --git a/flang/test/Lower/dummy-procedure.f90 b/flang/test/Lower/dummy-procedure.f90 index a02aa21d2cc2e..0359897258d2f 100644 --- a/flang/test/Lower/dummy-procedure.f90 +++ b/flang/test/Lower/dummy-procedure.f90 @@ -1,21 +1,22 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s ! Test dummy procedures ! Test of dummy procedure call -! CHECK-LABEL: func @_QPfoo( +! CHECK-LABEL: func.func @_QPfoo( ! CHECK-SAME: %{{.*}}: !fir.boxproc<() -> ()>{{.*}}) -> f32 real function foo(bar) real :: bar, x ! CHECK: %[[x:.*]] = fir.alloca f32 {{{.*}}uniq_name = "{{.*}}Ex"} + ! CHECK: %[[x_decl:.*]]:2 = hlfir.declare %[[x]] x = 42. ! CHECK: %[[funccast:.*]] = fir.box_addr %arg0 : (!fir.boxproc<() -> ()>) -> ((!fir.ref) -> f32) - ! CHECK: fir.call %[[funccast]](%[[x]]) {{.*}}: (!fir.ref) -> f32 + ! CHECK: fir.call %[[funccast]](%[[x_decl]]#0) {{.*}}: (!fir.ref) -> f32 foo = bar(x) end function ! Test case where dummy procedure is only transiting. -! CHECK-LABEL: func @_QPprefoo( +! CHECK-LABEL: func.func @_QPprefoo( ! CHECK-SAME: %{{.*}}: !fir.boxproc<() -> ()>{{.*}}) -> f32 real function prefoo(bar) external :: bar @@ -24,7 +25,7 @@ real function prefoo(bar) end function ! Function that will be passed as dummy argument -! CHECK-LABEL: func @_QPfunc( +! CHECK-LABEL: func.func @_QPfunc( ! CHECK-SAME: %{{.*}}: !fir.ref{{.*}}) -> f32 real function func(x) real :: x @@ -32,7 +33,7 @@ real function func(x) end function ! Test passing functions as dummy procedure arguments -! CHECK-LABEL: func @_QPtest_func +! CHECK-LABEL: func.func @_QPtest_func real function test_func() real :: func, prefoo external :: func @@ -44,18 +45,19 @@ real function test_func() ! Repeat test with dummy subroutine -! CHECK-LABEL: func @_QPfoo_sub( +! CHECK-LABEL: func.func @_QPfoo_sub( ! CHECK-SAME: %{{.*}}: !fir.boxproc<() -> ()>{{.*}}) subroutine foo_sub(bar_sub) ! CHECK: %[[x:.*]] = fir.alloca f32 {{{.*}}uniq_name = "{{.*}}Ex"} + ! CHECK: %[[x_decl:.*]]:2 = hlfir.declare %[[x]] x = 42. ! CHECK: %[[funccast:.*]] = fir.box_addr %arg0 : (!fir.boxproc<() -> ()>) -> ((!fir.ref) -> ()) - ! CHECK: fir.call %[[funccast]](%[[x]]) {{.*}}: (!fir.ref) + ! CHECK: fir.call %[[funccast]](%[[x_decl]]#0) {{.*}}: (!fir.ref) call bar_sub(x) end subroutine ! Test case where dummy procedure is only transiting. -! CHECK-LABEL: func @_QPprefoo_sub( +! CHECK-LABEL: func.func @_QPprefoo_sub( ! CHECK-SAME: %{{.*}}: !fir.boxproc<() -> ()>{{.*}}) subroutine prefoo_sub(bar_sub) external :: bar_sub @@ -64,7 +66,7 @@ subroutine prefoo_sub(bar_sub) end subroutine ! Subroutine that will be passed as dummy argument -! CHECK-LABEL: func @_QPsub( +! CHECK-LABEL: func.func @_QPsub( ! CHECK-SAME: %{{.*}}: !fir.ref{{.*}}) subroutine sub(x) real :: x @@ -72,7 +74,7 @@ subroutine sub(x) end subroutine ! Test passing functions as dummy procedure arguments -! CHECK-LABEL: func @_QPtest_sub +! CHECK-LABEL: func.func @_QPtest_sub subroutine test_sub() external :: sub !CHECK: %[[f:.*]] = fir.address_of(@_QPsub) : (!fir.ref) -> () @@ -81,7 +83,7 @@ subroutine test_sub() call prefoo_sub(sub) end subroutine -! CHECK-LABEL: func @_QPpassing_not_defined_in_file() +! CHECK-LABEL: func.func @_QPpassing_not_defined_in_file() subroutine passing_not_defined_in_file() external proc_not_defined_in_file ! CHECK: %[[addr:.*]] = fir.address_of(@_QPproc_not_defined_in_file) : () -> () @@ -93,7 +95,7 @@ subroutine passing_not_defined_in_file() ! Test passing unrestricted intrinsics ! Intrinsic using runtime -! CHECK-LABEL: func @_QPtest_acos +! CHECK-LABEL: func.func @_QPtest_acos subroutine test_acos(x) intrinsic :: acos !CHECK: %[[f:.*]] = fir.address_of(@fir.acos.f32.ref_f32) : (!fir.ref) -> f32 @@ -102,7 +104,7 @@ subroutine test_acos(x) call foo_acos(acos) end subroutine -! CHECK-LABEL: func @_QPtest_atan2 +! CHECK-LABEL: func.func @_QPtest_atan2 subroutine test_atan2() intrinsic :: atan2 ! CHECK: %[[f:.*]] = fir.address_of(@fir.atan2.f32.ref_f32.ref_f32) : (!fir.ref, !fir.ref) -> f32 @@ -112,7 +114,7 @@ subroutine test_atan2() end subroutine ! Intrinsic implemented inlined -! CHECK-LABEL: func @_QPtest_aimag +! CHECK-LABEL: func.func @_QPtest_aimag subroutine test_aimag() intrinsic :: aimag !CHECK: %[[f:.*]] = fir.address_of(@fir.aimag.f32.ref_z32) : (!fir.ref>) -> f32 @@ -122,7 +124,7 @@ subroutine test_aimag() end subroutine ! Character Intrinsic implemented inlined -! CHECK-LABEL: func @_QPtest_len +! CHECK-LABEL: func.func @_QPtest_len subroutine test_len() intrinsic :: len ! CHECK: %[[f:.*]] = fir.address_of(@fir.len.i32.bc1) : (!fir.boxchar<1>) -> i32 @@ -132,7 +134,7 @@ subroutine test_len() end subroutine ! Intrinsic implemented inlined with specific name different from generic -! CHECK-LABEL: func @_QPtest_iabs +! CHECK-LABEL: func.func @_QPtest_iabs subroutine test_iabs() intrinsic :: iabs ! CHECK: %[[f:.*]] = fir.address_of(@fir.abs.i32.ref_i32) : (!fir.ref) -> i32 @@ -144,32 +146,32 @@ subroutine test_iabs() ! TODO: exhaustive test of unrestricted intrinsic table 16.2 ! TODO: improve dummy procedure types when interface is given. -! CHECK: func @_QPtodo3( +! CHECK: func.func @_QPtodo3( ! CHECK-SAME: %{{.*}}: !fir.boxproc<() -> ()>{{.*}}) -! SHOULD-CHECK: func @_QPtodo3(%arg0: (!fir.ref) -> f32) +! SHOULD-CHECK: func.func @_QPtodo3(%arg0: (!fir.ref) -> f32) subroutine todo3(dummy_proc) intrinsic :: acos procedure(acos) :: dummy_proc end subroutine -! CHECK-LABEL: func private @fir.acos.f32.ref_f32(%arg0: !fir.ref) -> f32 +! CHECK-LABEL: func.func private @fir.acos.f32.ref_f32(%arg0: !fir.ref) -> f32 !CHECK: %[[load:.*]] = fir.load %arg0 !CHECK: %[[res:.*]] = math.acos %[[load]] fastmath : f32 !CHECK: return %[[res]] : f32 -! CHECK-LABEL: func private @fir.atan2.f32.ref_f32.ref_f32( +! CHECK-LABEL: func.func private @fir.atan2.f32.ref_f32.ref_f32( ! CHECK-SAME: %[[x:.*]]: !fir.ref, %[[y:.*]]: !fir.ref) -> f32 ! CHECK-DAG: %[[xload:.*]] = fir.load %[[x]] : !fir.ref ! CHECK-DAG: %[[yload:.*]] = fir.load %[[y]] : !fir.ref ! CHECK: %[[atan2:.*]] = math.atan2 %[[xload]], %[[yload]] fastmath : f32 ! CHECK: return %[[atan2]] : f32 -!CHECK-LABEL: func private @fir.aimag.f32.ref_z32(%arg0: !fir.ref>) +!CHECK-LABEL: func.func private @fir.aimag.f32.ref_z32(%arg0: !fir.ref>) !CHECK: %[[load:.*]] = fir.load %arg0 !CHECK: %[[imag:.*]] = fir.extract_value %[[load]], [1 : index] : (complex) -> f32 !CHECK: return %[[imag]] : f32 -!CHECK-LABEL: func private @fir.len.i32.bc1(%arg0: !fir.boxchar<1>) +!CHECK-LABEL: func.func private @fir.len.i32.bc1(%arg0: !fir.boxchar<1>) !CHECK: %[[unboxed:.*]]:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref>, index) !CHECK: %[[len:.*]] = fir.convert %[[unboxed]]#1 : (index) -> i32 !CHECK: return %[[len]] : i32 diff --git a/flang/test/Lower/equivalence-1.f90 b/flang/test/Lower/equivalence-1.f90 index deb3a5b5614f4..b27cb55297d7d 100644 --- a/flang/test/Lower/equivalence-1.f90 +++ b/flang/test/Lower/equivalence-1.f90 @@ -1,38 +1,44 @@ -! RUN: bbc -hlfir=false -o - %s | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir -o - %s | FileCheck %s -! CHECK-LABEL: func @_QPs1 +! CHECK-LABEL: func.func @_QPs1() SUBROUTINE s1 INTEGER i REAL r - ! CHECK: = fir.alloca !fir.array<4xi8> {uniq_name = "_QFs1Ei"} + ! CHECK: %[[group:.*]] = fir.alloca !fir.array<4xi8> {uniq_name = "_QFs1Ei"} EQUIVALENCE (r,i) - ! CHECK: %[[coor:.*]] = fir.coordinate_of %{{.*}}, %{{.*}} : (!fir.ref>, index) -> !fir.ref + ! CHECK: %[[coor:.*]] = fir.coordinate_of %[[group]], %c0{{.*}} : (!fir.ref>, index) -> !fir.ref ! CHECK: %[[iloc:.*]] = fir.convert %[[coor]] : (!fir.ref) -> !fir.ptr - ! CHECK-DAG: fir.store %{{.*}} to %[[iloc]] : !fir.ptr + ! CHECK: %[[i_decl:.*]]:2 = hlfir.declare %[[iloc]] storage(%[[group]][0]) {uniq_name = "_QFs1Ei"} + ! CHECK: %[[coor2:.*]] = fir.coordinate_of %[[group]], %c0{{.*}} : (!fir.ref>, index) -> !fir.ref + ! CHECK: %[[rloc:.*]] = fir.convert %[[coor2]] : (!fir.ref) -> !fir.ptr + ! CHECK: %[[r_decl:.*]]:2 = hlfir.declare %[[rloc]] storage(%[[group]][0]) {uniq_name = "_QFs1Er"} i = 4 - ! CHECK-DAG: %[[floc:.*]] = fir.convert %[[coor]] : (!fir.ref) -> !fir.ptr - ! CHECK: %[[ld:.*]] = fir.load %[[floc]] : !fir.ptr + ! CHECK: hlfir.assign %c4{{.*}} to %[[i_decl]]#0 PRINT *, r + ! CHECK: fir.load %[[r_decl]]#0 END SUBROUTINE s1 -! CHECK-LABEL: func @_QPs2 +! CHECK-LABEL: func.func @_QPs2() SUBROUTINE s2 INTEGER i(10) REAL r(10) ! CHECK: %[[arr:.*]] = fir.alloca !fir.array<48xi8> EQUIVALENCE (r(3),i(5)) - ! CHECK: %[[iarr:.*]] = fir.convert %{{.*}} : (!fir.ref) -> !fir.ptr> - ! CHECK: %[[foff:.*]] = fir.coordinate_of %[[arr]], %{{.*}} : (!fir.ref>, index) -> !fir.ref - ! CHECK: %[[farr:.*]] = fir.convert %[[foff]] : (!fir.ref) -> !fir.ptr> - ! CHECK: %[[ia:.*]] = fir.coordinate_of %[[iarr]], %{{.*}} : (!fir.ptr>, i64) -> !fir.ref - ! CHECK: fir.store %{{.*}} to %[[ia]] : !fir.ref + ! CHECK: %[[coor:.*]] = fir.coordinate_of %[[arr]], %c0{{.*}} : (!fir.ref>, index) -> !fir.ref + ! CHECK: %[[iarr:.*]] = fir.convert %[[coor]] : (!fir.ref) -> !fir.ptr> + ! CHECK: %[[i_decl:.*]]:2 = hlfir.declare %[[iarr]](%{{.*}}) storage(%[[arr]][0]) {uniq_name = "_QFs2Ei"} + ! CHECK: %[[coor2:.*]] = fir.coordinate_of %[[arr]], %c8{{.*}} : (!fir.ref>, index) -> !fir.ref + ! CHECK: %[[rarr:.*]] = fir.convert %[[coor2]] : (!fir.ref) -> !fir.ptr> + ! CHECK: %[[r_decl:.*]]:2 = hlfir.declare %[[rarr]](%{{.*}}) storage(%[[arr]][8]) {uniq_name = "_QFs2Er"} i(5) = 18 - ! CHECK: %[[fld:.*]] = fir.coordinate_of %[[farr]], %{{.*}} : (!fir.ptr>, i64) -> !fir.ref - ! CHECK: = fir.load %[[fld]] : !fir.ref + ! CHECK: %[[ides:.*]] = hlfir.designate %[[i_decl]]#0 (%c5{{.*}}) + ! CHECK: hlfir.assign %c18{{.*}} to %[[ides]] PRINT *, r(3) + ! CHECK: %[[rdes:.*]] = hlfir.designate %[[r_decl]]#0 (%c3{{.*}}) + ! CHECK: fir.load %[[rdes]] END SUBROUTINE s2 -! CHECK-LABEL: func @_QPs3 +! CHECK-LABEL: func.func @_QPs3() SUBROUTINE s3 REAL r(10) TYPE t @@ -42,16 +48,14 @@ SUBROUTINE s3 TYPE(t) x ! CHECK: %[[group:.*]] = fir.alloca !fir.array<40xi8> EQUIVALENCE (r,x) - ! CHECK: %[[coor:.*]] = fir.coordinate_of %[[group]], %c0 : (!fir.ref>, index) -> !fir.ref - ! CHECK: %[[rloc:.*]] = fir.convert %[[coor]] : (!fir.ref) -> !fir.ptr> - ! CHECK: %[[xloc:.*]] = fir.convert %[[coor]] : (!fir.ref) -> !fir.ptr}>> - ! CHECK: %[[xrloc:.*]] = fir.coordinate_of %[[xloc]], r - ! CHECK: %[[v1loc:.*]] = fir.coordinate_of %[[xrloc]], %c8_i64 : (!fir.ref>, i64) -> !fir.ref - ! CHECK: fir.store %{{.*}} to %[[v1loc]] : !fir.ref + ! CHECK: %[[r_decl:.*]]:2 = hlfir.declare %{{.*}} storage(%[[group]][0]) {uniq_name = "_QFs3Er"} + ! CHECK: %[[x_decl:.*]]:2 = hlfir.declare %{{.*}} storage(%[[group]][0]) {uniq_name = "_QFs3Ex"} x%r(9) = 9.0 - ! CHECK: %[[v2loc:.*]] = fir.coordinate_of %[[rloc]], %c8_i64 : (!fir.ptr>, i64) -> !fir.ref - ! CHECK: %{{.*}} = fir.load %[[v2loc]] : !fir.ref + ! CHECK: %[[xdes:.*]] = hlfir.designate %[[x_decl]]#0{"r"} <%{{.*}}> (%c9{{.*}}) + ! CHECK: hlfir.assign %{{.*}} to %[[xdes]] PRINT *, r(9) + ! CHECK: %[[rdes:.*]] = hlfir.designate %[[r_decl]]#0 (%c9{{.*}}) + ! CHECK: fir.load %[[rdes]] END SUBROUTINE s3 ! test that equivalence in main program containing arrays are placed in global memory. diff --git a/flang/test/Lower/equivalence-2.f90 b/flang/test/Lower/equivalence-2.f90 index 1c4506054c76a..12e878f743711 100644 --- a/flang/test/Lower/equivalence-2.f90 +++ b/flang/test/Lower/equivalence-2.f90 @@ -1,26 +1,36 @@ -! RUN: bbc -emit-fir -hlfir=false -o - %s | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir -o - %s | FileCheck %s ! Check more advanced equivalence cases ! Several set of local and global equivalences in the same scope -! CHECK-LABEL: @_QPtest_eq_sets +! CHECK-LABEL: func.func @_QPtest_eq_sets subroutine test_eq_sets DIMENSION Al(4), Bl(4) EQUIVALENCE (Al(1), Bl(2)) ! CHECK-DAG: %[[albl:.*]] = fir.alloca !fir.array<20xi8> ! CHECK-DAG: %[[alAddr:.*]] = fir.coordinate_of %[[albl]], %c4{{.*}} : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[al:.*]] = fir.convert %[[alAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[al_decl:.*]]:2 = hlfir.declare %[[al]](%{{.*}}) storage(%[[albl]][4]) {uniq_name = "_QFtest_eq_setsEal"} ! CHECK-DAG: %[[blAddr:.*]] = fir.coordinate_of %[[albl]], %c0{{.*}} : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[bl:.*]] = fir.convert %[[blAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[bl_decl:.*]]:2 = hlfir.declare %[[bl]](%{{.*}}) storage(%[[albl]][0]) {uniq_name = "_QFtest_eq_setsEbl"} DIMENSION Il(2), Xl(2) EQUIVALENCE (Il(2), Xl(1)) ! CHECK-DAG: %[[ilxl:.*]] = fir.alloca !fir.array<12xi8> + ! CHECK-DAG: %[[igAddr:.*]] = fir.coordinate_of %{{.*}}, %c0{{.*}} : (!fir.ref>, index) -> !fir.ref + ! CHECK-DAG: %[[ig:.*]] = fir.convert %[[igAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[ig_decl:.*]]:2 = hlfir.declare %[[ig]](%{{.*}}) storage(%{{.*}}[0]) {uniq_name = "_QFtest_eq_setsEig"} ! CHECK-DAG: %[[ilAddr:.*]] = fir.coordinate_of %[[ilxl]], %c0{{.*}} : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[il:.*]] = fir.convert %[[ilAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[il_decl:.*]]:2 = hlfir.declare %[[il]](%{{.*}}) storage(%[[ilxl]][0]) {uniq_name = "_QFtest_eq_setsEil"} + ! CHECK-DAG: %[[xgAddr:.*]] = fir.coordinate_of %{{.*}}, %c0{{.*}} : (!fir.ref>, index) -> !fir.ref + ! CHECK-DAG: %[[xg:.*]] = fir.convert %[[xgAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[xg_decl:.*]]:2 = hlfir.declare %[[xg]](%{{.*}}) storage(%{{.*}}[0]) {uniq_name = "_QFtest_eq_setsExg"} ! CHECK-DAG: %[[xlAddr:.*]] = fir.coordinate_of %[[ilxl]], %c4{{.*}} : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[xl:.*]] = fir.convert %[[xlAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[xl_decl:.*]]:2 = hlfir.declare %[[xl]](%{{.*}}) storage(%[[ilxl]][4]) {uniq_name = "_QFtest_eq_setsExl"} DIMENSION Ag(2), Bg(2) SAVE Ag, Bg @@ -28,27 +38,24 @@ subroutine test_eq_sets ! CHECK-DAG: %[[agbg:.*]] = fir.address_of(@_QFtest_eq_setsEag) : !fir.ref> ! CHECK-DAG: %[[agAddr:.*]] = fir.coordinate_of %[[agbg]], %c4{{.*}} : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[ag:.*]] = fir.convert %[[agAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[ag_decl:.*]]:2 = hlfir.declare %[[ag]](%{{.*}}) storage(%[[agbg]][4]) {uniq_name = "_QFtest_eq_setsEag"} ! CHECK-DAG: %[[bgAddr:.*]] = fir.coordinate_of %[[agbg]], %c0{{.*}} : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[bg:.*]] = fir.convert %[[bgAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[bg_decl:.*]]:2 = hlfir.declare %[[bg]](%{{.*}}) storage(%[[agbg]][0]) {uniq_name = "_QFtest_eq_setsEbg"} DIMENSION Ig(2), Xg(2) SAVE Ig, Xg EQUIVALENCE (Ig(1), Xg(1)) ! CHECK-DAG: %[[igxg:.*]] = fir.address_of(@_QFtest_eq_setsEig) : !fir.ref> - ! CHECK-DAG: %[[igOffset:.*]] = arith.constant 0 : index - ! CHECK-DAG: %[[igAddr:.*]] = fir.coordinate_of %[[igxg]], %c0{{.*}} : (!fir.ref>, index) -> !fir.ref - ! CHECK-DAG: %[[ig:.*]] = fir.convert %[[igAddr]] : (!fir.ref) -> !fir.ptr> - ! CHECK-DAG: %[[xgAddr:.*]] = fir.coordinate_of %[[igxg]], %c0{{.*}} : (!fir.ref>, index) -> !fir.ref - ! CHECK-DAG: %[[xg:.*]] = fir.convert %[[xgAddr]] : (!fir.ref) -> !fir.ptr> - ! CHECK: %[[alCast:.*]] = fir.convert %[[al]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[blCast:.*]] = fir.convert %[[bl]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[ilCast:.*]] = fir.convert %[[il]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[xlCast:.*]] = fir.convert %[[xl]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[agCast:.*]] = fir.convert %[[ag]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[bgCast:.*]] = fir.convert %[[bg]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[xgCast:.*]] = fir.convert %[[xg]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[igCast:.*]] = fir.convert %[[ig]] : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[alCast:.*]] = fir.convert %[[al_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[blCast:.*]] = fir.convert %[[bl_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[ilCast:.*]] = fir.convert %[[il_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[xlCast:.*]] = fir.convert %[[xl_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[agCast:.*]] = fir.convert %[[ag_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[bgCast:.*]] = fir.convert %[[bg_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[xgCast:.*]] = fir.convert %[[xg_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[igCast:.*]] = fir.convert %[[ig_decl]]#0 : (!fir.ptr>) -> !fir.ref> call fooc(Al, Bl, Il, Xl, Ag, Bg, Xg, Ig) ! CHECK: fir.call @_QPfooc(%[[alCast]], %[[blCast]], %[[ilCast]], %[[xlCast]], %[[agCast]], %[[bgCast]], %[[xgCast]], %[[igCast]]) @@ -57,7 +64,7 @@ subroutine test_eq_sets ! Mixing global equivalence and entry -! CHECK-LABEL: @_QPeq_and_entry_foo() +! CHECK-LABEL: func.func @_QPeq_and_entry_foo() subroutine eq_and_entry_foo SAVE x, i DIMENSION :: x(2) @@ -68,40 +75,46 @@ subroutine eq_and_entry_foo ! CHECK-DAG: %[[iOffset:.*]] = arith.constant 4 : index ! CHECK-DAG: %[[iAddr:.*]] = fir.coordinate_of %[[xi]], %[[iOffset]] : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[i:.*]] = fir.convert %[[iAddr]] : (!fir.ref) -> !fir.ptr + ! CHECK-DAG: %[[i_decl:.*]]:2 = hlfir.declare %[[i]] storage(%[[xi]][4]) {uniq_name = "_QFeq_and_entry_fooEi"} ! CHECK-DAG: %[[xOffset:.*]] = arith.constant 0 : index ! CHECK-DAG: %[[xAddr:.*]] = fir.coordinate_of %[[xi]], %[[xOffset]] : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[x:.*]] = fir.convert %[[xAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[x_decl:.*]]:2 = hlfir.declare %[[x]](%{{.*}}) storage(%[[xi]][0]) {uniq_name = "_QFeq_and_entry_fooEx"} + call foo2(x, i) - ! CHECK: %[[xCast:.*]] = fir.convert %[[x]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[iCast:.*]] = fir.convert %[[i]] : (!fir.ptr) -> !fir.ref + ! CHECK: %[[xCast:.*]] = fir.convert %[[x_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[iCast:.*]] = fir.convert %[[i_decl]]#0 : (!fir.ptr) -> !fir.ref ! CHECK: fir.call @_QPfoo1(%[[xCast]], %[[iCast]]) {{.*}}: (!fir.ref>, !fir.ref) -> () entry eq_and_entry_bar call foo2(x, i) - ! CHECK: %[[xCast2:.*]] = fir.convert %[[x]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[iCast2:.*]] = fir.convert %[[i]] : (!fir.ptr) -> !fir.ref + ! CHECK: %[[xCast2:.*]] = fir.convert %[[x_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[iCast2:.*]] = fir.convert %[[i_decl]]#0 : (!fir.ptr) -> !fir.ref ! CHECK: fir.call @_QPfoo2(%[[xCast2]], %[[iCast2]]) {{.*}}: (!fir.ref>, !fir.ref) -> () end -! CHECK-LABEL: @_QPeq_and_entry_bar() +! CHECK-LABEL: func.func @_QPeq_and_entry_bar() ! CHECK: %[[xi:.*]] = fir.address_of(@_QFeq_and_entry_fooEi) : !fir.ref> ! CHECK-DAG: %[[iOffset:.*]] = arith.constant 4 : index ! CHECK-DAG: %[[iAddr:.*]] = fir.coordinate_of %[[xi]], %[[iOffset]] : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[i:.*]] = fir.convert %[[iAddr]] : (!fir.ref) -> !fir.ptr + ! CHECK-DAG: %[[i_decl:.*]]:2 = hlfir.declare %[[i]] storage(%[[xi]][4]) {uniq_name = "_QFeq_and_entry_fooEi"} ! CHECK-DAG: %[[xOffset:.*]] = arith.constant 0 : index ! CHECK-DAG: %[[xAddr:.*]] = fir.coordinate_of %[[xi]], %[[xOffset]] : (!fir.ref>, index) -> !fir.ref ! CHECK-DAG: %[[x:.*]] = fir.convert %[[xAddr]] : (!fir.ref) -> !fir.ptr> + ! CHECK-DAG: %[[x_decl:.*]]:2 = hlfir.declare %[[x]](%{{.*}}) storage(%[[xi]][0]) {uniq_name = "_QFeq_and_entry_fooEx"} + ! CHECK-NOT: fir.call @_QPfoo1 - ! CHECK: %[[xCast:.*]] = fir.convert %[[x]] : (!fir.ptr>) -> !fir.ref> - ! CHECK: %[[iCast:.*]] = fir.convert %[[i]] : (!fir.ptr) -> !fir.ref + ! CHECK: %[[xCast:.*]] = fir.convert %[[x_decl]]#0 : (!fir.ptr>) -> !fir.ref> + ! CHECK: %[[iCast:.*]] = fir.convert %[[i_decl]]#0 : (!fir.ptr) -> !fir.ref ! CHECK: fir.call @_QPfoo2(%[[xCast]], %[[iCast]]) {{.*}}: (!fir.ref>, !fir.ref) -> () ! Check that cases where equivalenced local variables and common blocks will ! share the same offset use the correct stores -! CHECK-LABEL: @_QPeq_and_comm_same_offset() +! CHECK-LABEL: func.func @_QPeq_and_comm_same_offset() subroutine eq_and_comm_same_offset real common_arr1(133),common_arr2(133) common /my_common_block/ common_arr1,common_arr2 @@ -115,15 +128,25 @@ subroutine eq_and_comm_same_offset ! CHECK: %[[c0:.*]] = arith.constant 0 : index ! CHECK: %[[mcbCoor:.*]] = fir.coordinate_of %[[mcbAddr]], %[[c0]] : (!fir.ref>, index) -> !fir.ref ! CHECK: %[[mcbCoorCast:.*]] = fir.convert %[[mcbCoor]] : (!fir.ref) -> !fir.ptr> + ! CHECK: %[[c133:.*]] = arith.constant 133 : index + ! CHECK: %[[shape1:.*]] = fir.shape %[[c133]] : (index) -> !fir.shape<1> + ! CHECK: %[[arr1_decl:.*]]:2 = hlfir.declare %[[mcbCoorCast]](%[[shape1]]) storage(%[[mcbAddr]][0]) {uniq_name = "_QFeq_and_comm_same_offsetEarr1"} + ! CHECK: %[[c1:.*]] = arith.constant 0 : index ! CHECK: %[[arr4Addr:.*]] = fir.coordinate_of %[[arr4Store]], %[[c1]] : (!fir.ref>, index) -> !fir.ref ! CHECK: %[[arr4Cast:.*]] = fir.convert %[[arr4Addr]] : (!fir.ref) -> !fir.ptr> + ! CHECK: %[[arr3_decl:.*]]:2 = hlfir.declare %[[arr4Cast]](%{{.*}}) storage(%[[arr4Store]][0]) {uniq_name = "_QFeq_and_comm_same_offsetEarr3"} + + ! CHECK: %[[c0_new:.*]] = arith.constant 0 : index + ! CHECK: %[[arr4Addr_new:.*]] = fir.coordinate_of %[[arr4Store]], %[[c0_new]] : (!fir.ref>, index) -> !fir.ref + ! CHECK: %[[arr4Cast_new:.*]] = fir.convert %[[arr4Addr_new]] : (!fir.ref) -> !fir.ptr> + ! CHECK: %[[arr4_decl:.*]]:2 = hlfir.declare %[[arr4Cast_new]](%{{.*}}) storage(%[[arr4Store]][0]) {uniq_name = "_QFeq_and_comm_same_offsetEarr4"} arr1(1) = 1 - ! CHECK:%[[mcbFinalAddr:.*]] = fir.coordinate_of %[[mcbCoorCast]], %{{.*}} : (!fir.ptr>, i64) -> !fir.ref - ! CHECK:fir.store %{{.*}} to %[[mcbFinalAddr]] : !fir.ref + ! CHECK:%[[mcbFinalAddr:.*]] = hlfir.designate %[[arr1_decl]]#0 (%c1{{.*}}) + ! CHECK:hlfir.assign %{{.*}} to %[[mcbFinalAddr]] arr4(1,1) = 2 - ! CHECK: %[[arr4FinalAddr:.*]] = fir.coordinate_of %[[arr4Cast]], %{{.*}}, %{{.*}} : (!fir.ptr>, i64, i64) -> !fir.ref - ! CHECK: fir.store %{{.*}} to %[[arr4FinalAddr]] : !fir.ref + ! CHECK: %[[arr4FinalAddr:.*]] = hlfir.designate %[[arr4_decl]]#0 (%c1{{.*}}, %c1{{.*}}) + ! CHECK: hlfir.assign %{{.*}} to %[[arr4FinalAddr]] end subroutine diff --git a/flang/test/Lower/equivalence-with-host-assoc.f90 b/flang/test/Lower/equivalence-with-host-assoc.f90 index 733531ab8a2c8..c3a7f743fcd87 100644 --- a/flang/test/Lower/equivalence-with-host-assoc.f90 +++ b/flang/test/Lower/equivalence-with-host-assoc.f90 @@ -1,5 +1,4 @@ -! RUN: bbc -emit-fir -hlfir=false -o - %s | FileCheck %s --check-prefixes=FIR -! RUN: bbc -emit-hlfir -o - %s | FileCheck %s --check-prefixes=HLFIR +! RUN: %flang_fc1 -emit-hlfir -o - %s | FileCheck %s --check-prefixes=HLFIR subroutine test1() integer :: i1 = 1 @@ -10,20 +9,6 @@ subroutine inner i1 = j1 end subroutine inner end subroutine test1 -! FIR-LABEL: func.func private @_QFtest1Pinner() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { -! FIR: %[[VAL_0:.*]] = fir.address_of(@_QFtest1Ei1) : !fir.ref> -! FIR: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> -! FIR: %[[VAL_2:.*]] = arith.constant 0 : index -! FIR: %[[VAL_3:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_2]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_5:.*]] = arith.constant 0 : index -! FIR: %[[VAL_6:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_5]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_7:.*]] = fir.convert %[[VAL_6]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_8:.*]] = fir.load %[[VAL_7]] : !fir.ptr -! FIR: fir.store %[[VAL_8]] to %[[VAL_4]] : !fir.ptr -! FIR: return -! FIR: } - ! HLFIR-LABEL: func.func private @_QFtest1Pinner() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { ! HLFIR: %[[VAL_0:.*]] = fir.address_of(@_QFtest1Ei1) : !fir.ref> ! HLFIR: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> @@ -54,20 +39,6 @@ subroutine inner end subroutine inner end subroutine host end module test2 -! FIR-LABEL: func.func private @_QMtest2FhostPinner() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { -! FIR: %[[VAL_0:.*]] = fir.address_of(@_QMtest2FhostEf1) : !fir.ref> -! FIR: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> -! FIR: %[[VAL_2:.*]] = arith.constant 0 : index -! FIR: %[[VAL_3:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_2]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_5:.*]] = arith.constant 0 : index -! FIR: %[[VAL_6:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_5]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_7:.*]] = fir.convert %[[VAL_6]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_8:.*]] = fir.load %[[VAL_7]] : !fir.ptr -! FIR: fir.store %[[VAL_8]] to %[[VAL_4]] : !fir.ptr -! FIR: return -! FIR: } - ! HLFIR-LABEL: func.func private @_QMtest2FhostPinner() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { ! HLFIR: %[[VAL_0:.*]] = fir.address_of(@_QMtest2FhostEf1) : !fir.ref> ! HLFIR: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> @@ -94,27 +65,6 @@ subroutine inner i1 = j1 + k1 end subroutine inner end subroutine test3 -! FIR-LABEL: func.func private @_QFtest3Pinner() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { -! FIR: %[[VAL_0:.*]] = fir.address_of(@blk_) : !fir.ref> -! FIR: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> -! FIR: %[[VAL_2:.*]] = arith.constant 0 : index -! FIR: %[[VAL_3:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_2]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_5:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> -! FIR: %[[VAL_6:.*]] = arith.constant 0 : index -! FIR: %[[VAL_7:.*]] = fir.coordinate_of %[[VAL_5]], %[[VAL_6]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_9:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> -! FIR: %[[VAL_10:.*]] = arith.constant 0 : index -! FIR: %[[VAL_11:.*]] = fir.coordinate_of %[[VAL_9]], %[[VAL_10]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_13:.*]] = fir.load %[[VAL_8]] : !fir.ptr -! FIR: %[[VAL_14:.*]] = fir.load %[[VAL_12]] : !fir.ptr -! FIR: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 -! FIR: fir.store %[[VAL_15]] to %[[VAL_4]] : !fir.ptr -! FIR: return -! FIR: } - ! HLFIR-LABEL: func.func private @_QFtest3Pinner() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { ! HLFIR: %[[VAL_0:.*]] = fir.address_of(@blk_) : !fir.ref> ! HLFIR: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> @@ -149,27 +99,6 @@ subroutine inner i1 = j1 + k1 end subroutine inner end subroutine test4 -! FIR-LABEL: func.func private @_QFtest4Pinner() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { -! FIR: %[[VAL_0:.*]] = fir.address_of(@blk_) : !fir.ref> -! FIR: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> -! FIR: %[[VAL_2:.*]] = arith.constant 0 : index -! FIR: %[[VAL_3:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_2]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_5:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> -! FIR: %[[VAL_6:.*]] = arith.constant 0 : index -! FIR: %[[VAL_7:.*]] = fir.coordinate_of %[[VAL_5]], %[[VAL_6]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_9:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> -! FIR: %[[VAL_10:.*]] = arith.constant 0 : index -! FIR: %[[VAL_11:.*]] = fir.coordinate_of %[[VAL_9]], %[[VAL_10]] : (!fir.ref>, index) -> !fir.ref -! FIR: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (!fir.ref) -> !fir.ptr -! FIR: %[[VAL_13:.*]] = fir.load %[[VAL_8]] : !fir.ptr -! FIR: %[[VAL_14:.*]] = fir.load %[[VAL_12]] : !fir.ptr -! FIR: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 -! FIR: fir.store %[[VAL_15]] to %[[VAL_4]] : !fir.ptr -! FIR: return -! FIR: } - ! HLFIR-LABEL: func.func private @_QFtest4Pinner() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { ! HLFIR: %[[VAL_0:.*]] = fir.address_of(@blk_) : !fir.ref> ! HLFIR: %[[VAL_1:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>) -> !fir.ref> diff --git a/flang/test/Lower/explicit-interface-results-2.f90 b/flang/test/Lower/explicit-interface-results-2.f90 index 42043579a53d0..f29ee99522b2e 100644 --- a/flang/test/Lower/explicit-interface-results-2.f90 +++ b/flang/test/Lower/explicit-interface-results-2.f90 @@ -1,7 +1,4 @@ -! Test lowering of internal procedures returning arrays or characters. -! This test allocation on the caller side of the results that may depend on -! host associated symbols. -! RUN: bbc -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s module some_module integer :: n_module @@ -9,17 +6,19 @@ module some_module ! Test host calling array internal procedure. ! Result depends on host variable. -! CHECK-LABEL: func @_QPhost1 +! CHECK-LABEL: func.func @_QPhost1 subroutine host1() implicit none integer :: n -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 call takes_array(return_array()) -! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_5]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_5]], %{{.*}} : index -! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_8:.*]] = hlfir.eval_in_mem shape %[[VAL_7:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost1Preturn_array(%{{.*}}) {{.*}}: (!fir.ref>>) -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_7]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_9:.*]]:3 = hlfir.associate %[[VAL_8]](%[[VAL_7]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_9]]#1) {{.*}}: (!fir.ref>) -> () contains function return_array() real :: return_array(n) @@ -28,16 +27,18 @@ function return_array() ! Test host calling array internal procedure. ! Result depends on module variable with the use statement inside the host. -! CHECK-LABEL: func @_QPhost2 +! CHECK-LABEL: func.func @_QPhost2 subroutine host2() use :: some_module call takes_array(return_array()) -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QMsome_moduleEn_module) : !fir.ref -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_2]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_2]], %{{.*}} : index -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_5:.*]] = hlfir.eval_in_mem shape %[[VAL_4:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost2Preturn_array() {{.*}}: () -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_4]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_6:.*]]:3 = hlfir.associate %[[VAL_5]](%[[VAL_4]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_6]]#1) {{.*}}: (!fir.ref>) -> () contains function return_array() real :: return_array(n_module) @@ -46,15 +47,17 @@ function return_array() ! Test host calling array internal procedure. ! Result depends on module variable with the use statement inside the internal procedure. -! CHECK-LABEL: func @_QPhost3 +! CHECK-LABEL: func.func @_QPhost3 subroutine host3() call takes_array(return_array()) -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QMsome_moduleEn_module) : !fir.ref -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_2]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_2]], %{{.*}} : index -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_5:.*]] = hlfir.eval_in_mem shape %[[VAL_4:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost3Preturn_array() {{.*}}: () -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_4]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_6:.*]]:3 = hlfir.associate %[[VAL_5]](%[[VAL_4]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_6]]#1) {{.*}}: (!fir.ref>) -> () contains function return_array() use :: some_module @@ -69,18 +72,18 @@ subroutine host4() integer :: n call internal_proc_a() contains -! CHECK-LABEL: func private @_QFhost4Pinternal_proc_a -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.host_assoc}) attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { +! CHECK-LABEL: func.func private @_QFhost4Pinternal_proc_a +! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.host_assoc}) subroutine internal_proc_a() call takes_array(return_array()) -! CHECK: %[[VAL_1:.*]] = arith.constant 0 : i32 -! CHECK: %[[VAL_2:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_1]] : (!fir.ref>>, i32) -> !fir.llvm_ptr> -! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]] : !fir.llvm_ptr> -! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_5]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_5]], %{{.*}} : index -! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_8:.*]] = hlfir.eval_in_mem shape %[[VAL_7:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost4Preturn_array(%[[VAL_0]]) {{.*}}: (!fir.ref>>) -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_7]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_9:.*]]:3 = hlfir.associate %[[VAL_8]](%[[VAL_7]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_9]]#1) {{.*}}: (!fir.ref>) -> () end subroutine function return_array() real :: return_array(n) @@ -94,15 +97,17 @@ subroutine host5() implicit none call internal_proc_a() contains -! CHECK-LABEL: func private @_QFhost5Pinternal_proc_a() attributes {fir.host_symbol = {{.*}}, llvm.linkage = #llvm.linkage} { +! CHECK-LABEL: func.func private @_QFhost5Pinternal_proc_a subroutine internal_proc_a() call takes_array(return_array()) -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QMsome_moduleEn_module) : !fir.ref -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_2]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_2]], %{{.*}} : index -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_5:.*]] = hlfir.eval_in_mem shape %[[VAL_4:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost5Preturn_array() {{.*}}: () -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_4]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_6:.*]]:3 = hlfir.associate %[[VAL_5]](%[[VAL_4]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_6]]#1) {{.*}}: (!fir.ref>) -> () end subroutine function return_array() real :: return_array(n_module) @@ -115,15 +120,17 @@ subroutine host6() implicit none call internal_proc_a() contains -! CHECK-LABEL: func private @_QFhost6Pinternal_proc_a +! CHECK-LABEL: func.func private @_QFhost6Pinternal_proc_a subroutine internal_proc_a() call takes_array(return_array()) -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QMsome_moduleEn_module) : !fir.ref -! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_2]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_2]], %{{.*}} : index -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_5:.*]] = hlfir.eval_in_mem shape %[[VAL_4:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost6Preturn_array() {{.*}}: () -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_4]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_6:.*]]:3 = hlfir.associate %[[VAL_5]](%[[VAL_4]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_6]]#1) {{.*}}: (!fir.ref>) -> () end subroutine function return_array() use :: some_module @@ -133,21 +140,20 @@ function return_array() ! Test host calling array internal procedure. ! Result depends on a common block variable declared in the host. -! CHECK-LABEL: func @_QPhost7 +! CHECK-LABEL: func.func @_QPhost7 subroutine host7() implicit none integer :: n_common common /mycom/ n_common call takes_array(return_array()) -! CHECK: %[[VAL_0:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_2:.*]] = fir.address_of(@mycom_) : !fir.ref> -! CHECK: %[[VAL_4:.*]] = fir.coordinate_of %[[VAL_2]], %[[VAL_0]] : (!fir.ref>, index) -> !fir.ref -! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (!fir.ref) -> !fir.ref -! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_9]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_9]], %{{.*}} : index -! CHECK: %[[VAL_10:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_12:.*]] = hlfir.eval_in_mem shape %[[VAL_11:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost7Preturn_array() {{.*}}: () -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_11]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_13:.*]]:3 = hlfir.associate %[[VAL_12]](%[[VAL_11]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_13]]#1) {{.*}}: (!fir.ref>) -> () contains function return_array() real :: return_array(n_common) @@ -156,19 +162,18 @@ function return_array() ! Test host calling array internal procedure. ! Result depends on a common block variable declared in the internal procedure. -! CHECK-LABEL: func @_QPhost8 +! CHECK-LABEL: func.func @_QPhost8 subroutine host8() implicit none call takes_array(return_array()) -! CHECK: %[[VAL_0:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_1:.*]] = fir.address_of(@mycom_) : !fir.ref> -! CHECK: %[[VAL_3:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_0]] : (!fir.ref>, index) -> !fir.ref -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref) -> !fir.ref -! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_4]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_6]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_6]], %{{.*}} : index -! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_9:.*]] = hlfir.eval_in_mem shape %[[VAL_8:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost8Preturn_array() {{.*}}: () -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_8]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_10:.*]]:3 = hlfir.associate %[[VAL_9]](%[[VAL_8]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_10]]#1) {{.*}}: (!fir.ref>) -> () contains function return_array() integer :: n_common @@ -185,18 +190,17 @@ subroutine host9() common /mycom/ n_common call internal_proc_a() contains -! CHECK-LABEL: func private @_QFhost9Pinternal_proc_a +! CHECK-LABEL: func.func private @_QFhost9Pinternal_proc_a subroutine internal_proc_a() -! CHECK: %[[VAL_0:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_1:.*]] = fir.address_of(@mycom_) : !fir.ref> -! CHECK: %[[VAL_3:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_0]] : (!fir.ref>, index) -> !fir.ref -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref) -> !fir.ref -! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_4]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i32) -> index -! CHECK: %[[VAL_7:.*]] = arith.cmpi sgt, %[[VAL_6]], %[[VAL_0]] : index -! CHECK: %[[VAL_8:.*]] = arith.select %[[VAL_7]], %[[VAL_6]], %[[VAL_0]] : index -! CHECK: %[[VAL_10:.*]] = fir.alloca !fir.array, %[[VAL_8]] {bindc_name = ".result"} call takes_array(return_array()) +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_11:.*]] = hlfir.eval_in_mem shape %[[VAL_10:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost9Preturn_array() {{.*}}: () -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_10]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_12:.*]]:3 = hlfir.associate %[[VAL_11]](%[[VAL_10]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_12]]#1) {{.*}}: (!fir.ref>) -> () end subroutine function return_array() use :: some_module @@ -210,18 +214,17 @@ subroutine host10() implicit none call internal_proc_a() contains -! CHECK-LABEL: func private @_QFhost10Pinternal_proc_a +! CHECK-LABEL: func.func private @_QFhost10Pinternal_proc_a subroutine internal_proc_a() call takes_array(return_array()) -! CHECK: %[[VAL_0:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_1:.*]] = fir.address_of(@mycom_) : !fir.ref> -! CHECK: %[[VAL_3:.*]] = fir.coordinate_of %[[VAL_1]], %[[VAL_0]] : (!fir.ref>, index) -> !fir.ref -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (!fir.ref) -> !fir.ref -! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_4]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i32) -> index -! CHECK: %[[CMPI:.*]] = arith.cmpi sgt, %[[VAL_6]], %{{.*}} : index -! CHECK: %[[SELECT:.*]] = arith.select %[[CMPI]], %[[VAL_6]], %{{.*}} : index -! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.array, %[[SELECT]] {bindc_name = ".result"} +! CHECK: fir.shape %[[SELECT:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_9:.*]] = hlfir.eval_in_mem shape %[[VAL_8:.*]] : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[RES:.*]] = fir.call @_QFhost10Preturn_array() {{.*}}: () -> !fir.array +! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_8]]) : !fir.array, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_10:.*]]:3 = hlfir.associate %[[VAL_9]](%[[VAL_8]]) {{.*}} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) +! CHECK: fir.call @_QPtakes_array(%[[VAL_10]]#1) {{.*}}: (!fir.ref>) -> () end subroutine function return_array() integer :: n_common @@ -240,18 +243,20 @@ function foo() foo = 42 end function end module -! CHECK-LABEL: func @_QPtest_call_to_used_interface( +! CHECK-LABEL: func.func @_QPtest_call_to_used_interface( ! CHECK-SAME: %[[VAL_0:.*]]: !fir.boxproc<() -> ()>) { subroutine test_call_to_used_interface(dummy_proc) use define_interface procedure(foo) :: dummy_proc call takes_array(dummy_proc()) -! CHECK: %[[VAL_1:.*]] = arith.constant 100 : index -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.array<100xf32> {bindc_name = ".result"} -! CHECK: %[[VAL_4:.*]] = fir.shape %[[VAL_1]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_5:.*]] = fir.box_addr %[[VAL_0]] : (!fir.boxproc<() -> ()>) -> (() -> !fir.array<100xf32>) -! CHECK: %[[VAL_6:.*]] = fir.call %[[VAL_5]]() {{.*}}: () -> !fir.array<100xf32> -! CHECK: fir.save_result %[[VAL_6]] to %[[VAL_2]](%[[VAL_4]]) : !fir.array<100xf32>, !fir.ref>, !fir.shape<1> -! CHECK: %[[VAL_7:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.ref> -! CHECK: fir.call @_QPtakes_array(%[[VAL_7]]) {{.*}}: (!fir.ref>) -> () +! CHECK: fir.shape %[[VAL_9:.*]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_11:.*]] = hlfir.eval_in_mem shape %[[VAL_10:.*]] : (!fir.shape<1>) -> !hlfir.expr<100xf32> { +! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): +! CHECK: %[[VAL_12:.*]] = fir.box_addr %[[VAL_0]] : (!fir.boxproc<() -> ()>) -> (() -> !fir.array<100xf32>) +! CHECK: %[[VAL_13:.*]] = fir.call %[[VAL_12]]() fastmath : () -> !fir.array<100xf32> +! CHECK: fir.save_result %[[VAL_13]] to %[[ARG]](%[[VAL_10]]) : !fir.array<100xf32>, !fir.ref>, !fir.shape<1> +! CHECK: } +! CHECK: %[[VAL_14:.*]]:3 = hlfir.associate %[[VAL_11]](%[[VAL_10]]) {adapt.valuebyref} : (!hlfir.expr<100xf32>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>, i1) +! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]]#0 : (!fir.ref>) -> !fir.ref> +! CHECK: fir.call @_QPtakes_array(%[[VAL_15]]) fastmath : (!fir.ref>) -> () end subroutine diff --git a/flang/test/Lower/explicit-interface-results.f90 b/flang/test/Lower/explicit-interface-results.f90 index 8d51786da14ca..dff009d5496f2 100644 --- a/flang/test/Lower/explicit-interface-results.f90 +++ b/flang/test/Lower/explicit-interface-results.f90 @@ -1,86 +1,86 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s module callee implicit none contains -! CHECK-LABEL: func @_QMcalleePreturn_cst_array() -> !fir.array<20x30xf32> +! CHECK-LABEL: func.func @_QMcalleePreturn_cst_array() -> !fir.array<20x30xf32> function return_cst_array() real :: return_cst_array(20, 30) end function -! CHECK-LABEL: func @_QMcalleePreturn_dyn_array( +! CHECK-LABEL: func.func @_QMcalleePreturn_dyn_array( ! CHECK-SAME: %{{.*}}: !fir.ref{{.*}}, %{{.*}}: !fir.ref{{.*}}) -> !fir.array function return_dyn_array(m, n) integer :: m, n real :: return_dyn_array(m, n) end function -! CHECK-LABEL: func @_QMcalleePreturn_cst_char_cst_array() -> !fir.array<20x30x!fir.char<1,10>> +! CHECK-LABEL: func.func @_QMcalleePreturn_cst_char_cst_array() -> !fir.array<20x30x!fir.char<1,10>> function return_cst_char_cst_array() character(10) :: return_cst_char_cst_array(20, 30) end function -! CHECK-LABEL: func @_QMcalleePreturn_dyn_char_cst_array( +! CHECK-LABEL: func.func @_QMcalleePreturn_dyn_char_cst_array( ! CHECK-SAME: %{{.*}}: !fir.ref{{.*}}) -> !fir.array<20x30x!fir.char<1,?>> function return_dyn_char_cst_array(l) integer :: l character(l) :: return_dyn_char_cst_array(20, 30) end function -! CHECK-LABEL: func @_QMcalleePreturn_cst_char_dyn_array( +! CHECK-LABEL: func.func @_QMcalleePreturn_cst_char_dyn_array( ! CHECK-SAME: %{{.*}}: !fir.ref{{.*}}, %{{.*}}: !fir.ref{{.*}}) -> !fir.array> function return_cst_char_dyn_array(m, n) integer :: m, n character(10) :: return_cst_char_dyn_array(m, n) end function -! CHECK-LABEL: func @_QMcalleePreturn_dyn_char_dyn_array( +! CHECK-LABEL: func.func @_QMcalleePreturn_dyn_char_dyn_array( ! CHECK-SAME: %{{.*}}: !fir.ref{{.*}}, %{{.*}}: !fir.ref{{.*}}, %{{.*}}: !fir.ref{{.*}}) -> !fir.array> function return_dyn_char_dyn_array(l, m, n) integer :: l, m, n character(l) :: return_dyn_char_dyn_array(m, n) end function -! CHECK-LABEL: func @_QMcalleePreturn_alloc() -> !fir.box>> +! CHECK-LABEL: func.func @_QMcalleePreturn_alloc() -> !fir.box>> function return_alloc() real, allocatable :: return_alloc(:) end function -! CHECK-LABEL: func @_QMcalleePreturn_cst_char_alloc() -> !fir.box>>> +! CHECK-LABEL: func.func @_QMcalleePreturn_cst_char_alloc() -> !fir.box>>> function return_cst_char_alloc() character(10), allocatable :: return_cst_char_alloc(:) end function -! CHECK-LABEL: func @_QMcalleePreturn_dyn_char_alloc( +! CHECK-LABEL: func.func @_QMcalleePreturn_dyn_char_alloc( ! CHECK-SAME: %{{.*}}: !fir.ref{{.*}}) -> !fir.box>>> function return_dyn_char_alloc(l) integer :: l character(l), allocatable :: return_dyn_char_alloc(:) end function -! CHECK-LABEL: func @_QMcalleePreturn_def_char_alloc() -> !fir.box>>> +! CHECK-LABEL: func.func @_QMcalleePreturn_def_char_alloc() -> !fir.box>>> function return_def_char_alloc() character(:), allocatable :: return_def_char_alloc(:) end function -! CHECK-LABEL: func @_QMcalleePreturn_pointer() -> !fir.box>> +! CHECK-LABEL: func.func @_QMcalleePreturn_pointer() -> !fir.box>> function return_pointer() real, pointer :: return_pointer(:) end function -! CHECK-LABEL: func @_QMcalleePreturn_cst_char_pointer() -> !fir.box>>> +! CHECK-LABEL: func.func @_QMcalleePreturn_cst_char_pointer() -> !fir.box>>> function return_cst_char_pointer() character(10), pointer :: return_cst_char_pointer(:) end function -! CHECK-LABEL: func @_QMcalleePreturn_dyn_char_pointer( +! CHECK-LABEL: func.func @_QMcalleePreturn_dyn_char_pointer( ! CHECK-SAME: %{{.*}}: !fir.ref{{.*}}) -> !fir.box>>> function return_dyn_char_pointer(l) integer :: l character(l), pointer :: return_dyn_char_pointer(:) end function -! CHECK-LABEL: func @_QMcalleePreturn_def_char_pointer() -> !fir.box>>> +! CHECK-LABEL: func.func @_QMcalleePreturn_def_char_pointer() -> !fir.box>>> function return_def_char_pointer() character(:), pointer :: return_def_char_pointer(:) end function @@ -90,212 +90,195 @@ module caller use callee contains -! CHECK-LABEL: func @_QMcallerPcst_array() +! CHECK-LABEL: func.func @_QMcallerPcst_array() subroutine cst_array() - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.array<20x30xf32> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[shape:.*]] = fir.shape %{{.*}}, {{.*}} : (index, index) -> !fir.shape<2> - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_cst_array() {{.*}}: () -> !fir.array<20x30xf32> - ! CHECK: fir.save_result %[[res]] to %[[alloc]](%[[shape]]) : !fir.array<20x30xf32>, !fir.ref>, !fir.shape<2> + ! CHECK: %[[VAL_14:.*]] = fir.shape %{{.*}}, %{{.*}} : (index, index) -> !fir.shape<2> + ! CHECK: %[[VAL_15:.*]] = hlfir.eval_in_mem shape %[[VAL_14]] : (!fir.shape<2>) -> !hlfir.expr<20x30xf32> { + ! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): + ! CHECK: %[[RES:.*]] = fir.call @_QMcalleePreturn_cst_array() {{.*}}: () -> !fir.array<20x30xf32> + ! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_14]]) : !fir.array<20x30xf32>, !fir.ref>, !fir.shape<2> + ! CHECK: } + ! CHECK: %[[VAL_16:.*]]:3 = hlfir.associate %[[VAL_15]](%[[VAL_14]]) print *, return_cst_array() end subroutine -! CHECK-LABEL: func @_QMcallerPcst_char_cst_array() +! CHECK-LABEL: func.func @_QMcallerPcst_char_cst_array() subroutine cst_char_cst_array() - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.array<20x30x!fir.char<1,10>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[shape:.*]] = fir.shape %{{.*}}, {{.*}} : (index, index) -> !fir.shape<2> - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_cst_char_cst_array() {{.*}}: () -> !fir.array<20x30x!fir.char<1,10>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]](%[[shape]]) typeparams %{{.*}} : !fir.array<20x30x!fir.char<1,10>>, !fir.ref>>, !fir.shape<2>, index + ! CHECK: %[[VAL_17:.*]] = fir.shape %{{.*}}, %{{.*}} : (index, index) -> !fir.shape<2> + ! CHECK: %[[VAL_18:.*]] = hlfir.eval_in_mem shape %[[VAL_17]] typeparams %{{.*}} : (!fir.shape<2>, index) -> !hlfir.expr<20x30x!fir.char<1,10>> { + ! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>>): + ! CHECK: %[[RES:.*]] = fir.call @_QMcalleePreturn_cst_char_cst_array() {{.*}}: () -> !fir.array<20x30x!fir.char<1,10>> + ! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_17]]) typeparams %{{.*}} : !fir.array<20x30x!fir.char<1,10>>, !fir.ref>>, !fir.shape<2>, index + ! CHECK: } + ! CHECK: %[[VAL_19:.*]]:3 = hlfir.associate %[[VAL_18]](%[[VAL_17]]) typeparams %{{.*}} print *, return_cst_char_cst_array() end subroutine -! CHECK-LABEL: func @_QMcallerPalloc() +! CHECK-LABEL: func.func @_QMcallerPalloc() subroutine alloc() - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.box>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_alloc() {{.*}}: () -> !fir.box>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]] : !fir.box>>, !fir.ref>>> + ! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>> {bindc_name = ".result"} + ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = ".tmp.func_result"} + ! CHECK: %[[VAL_6:.*]] = fir.call @_QMcalleePreturn_alloc() {{.*}}: () -> !fir.box>> + ! CHECK: fir.save_result %[[VAL_6]] to %[[VAL_5]]#0 : !fir.box>>, !fir.ref>>> print *, return_alloc() + ! CHECK: %[[load:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref>>> + ! CHECK: %[[as_expr:.*]] = hlfir.as_expr %[[load]] move %{{.*}} : (!fir.box>>, i1) -> !hlfir.expr + ! CHECK: %[[assoc:.*]]:3 = hlfir.associate %[[as_expr]]({{.*}}) {adapt.valuebyref} : (!hlfir.expr, !fir.shape<1>) -> (!fir.box>, !fir.ref>, i1) ! CHECK: _FortranAioOutputDescriptor - ! CHECK: %[[load:.*]] = fir.load %[[alloc]] : !fir.ref>>> - ! CHECK: %[[addr:.*]] = fir.box_addr %[[load]] : (!fir.box>>) -> !fir.heap> - ! CHECK: %[[cmpi:.*]] = arith.cmpi - ! CHECK: fir.if %[[cmpi]] - ! CHECK: fir.freemem %[[addr]] : !fir.heap> + ! CHECK: hlfir.end_associate %[[assoc]]#1, %[[assoc]]#2 : !fir.ref>, i1 + ! CHECK: hlfir.destroy %[[as_expr]] : !hlfir.expr end subroutine -! CHECK-LABEL: func @_QMcallerPcst_char_alloc() +! CHECK-LABEL: func.func @_QMcallerPcst_char_alloc() subroutine cst_char_alloc() - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.box>>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_cst_char_alloc() {{.*}}: () -> !fir.box>>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]] : !fir.box>>>, !fir.ref>>>> + ! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>>> {bindc_name = ".result"} + ! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %{{.*}} {uniq_name = ".tmp.func_result"} + ! CHECK: %[[VAL_10:.*]] = fir.call @_QMcalleePreturn_cst_char_alloc() {{.*}}: () -> !fir.box>>> + ! CHECK: fir.save_result %[[VAL_10]] to %[[VAL_9]]#0 : !fir.box>>>, !fir.ref>>>> print *, return_cst_char_alloc() + ! CHECK: %[[load:.*]] = fir.load %[[VAL_9]]#0 : !fir.ref>>>> + ! CHECK: %[[as_expr:.*]] = hlfir.as_expr %[[load]] move %{{.*}} : (!fir.box>>>, i1) -> !hlfir.expr> + ! CHECK: %[[assoc:.*]]:3 = hlfir.associate %[[as_expr]]({{.*}}) typeparams %{{.*}} {adapt.valuebyref} : (!hlfir.expr>, !fir.shape<1>, index) -> (!fir.box>>, !fir.ref>>, i1) ! CHECK: _FortranAioOutputDescriptor - ! CHECK: %[[load:.*]] = fir.load %[[alloc]] : !fir.ref>>>> - ! CHECK: %[[addr:.*]] = fir.box_addr %[[load]] : (!fir.box>>>) -> !fir.heap>> - ! CHECK: %[[cmpi:.*]] = arith.cmpi - ! CHECK: fir.if %[[cmpi]] - ! CHECK: fir.freemem %[[addr]] : !fir.heap>> + ! CHECK: hlfir.end_associate %[[assoc]]#1, %[[assoc]]#2 : !fir.ref>>, i1 + ! CHECK: hlfir.destroy %[[as_expr]] : !hlfir.expr> end subroutine -! CHECK-LABEL: func @_QMcallerPdef_char_alloc() +! CHECK-LABEL: func.func @_QMcallerPdef_char_alloc() subroutine def_char_alloc() - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.box>>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_def_char_alloc() {{.*}}: () -> !fir.box>>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]] : !fir.box>>>, !fir.ref>>>> + ! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>>> {bindc_name = ".result"} + ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_0]] {uniq_name = ".tmp.func_result"} + ! CHECK: %[[VAL_6:.*]] = fir.call @_QMcalleePreturn_def_char_alloc() {{.*}}: () -> !fir.box>>> + ! CHECK: fir.save_result %[[VAL_6]] to %[[VAL_5]]#0 : !fir.box>>>, !fir.ref>>>> print *, return_def_char_alloc() + ! CHECK: %[[load:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref>>>> + ! CHECK: %[[as_expr:.*]] = hlfir.as_expr %[[load]] move %{{.*}} : (!fir.box>>>, i1) -> !hlfir.expr> + ! CHECK: %[[assoc:.*]]:3 = hlfir.associate %[[as_expr]]({{.*}}) typeparams %{{.*}} {adapt.valuebyref} : (!hlfir.expr>, !fir.shape<1>, index) -> (!fir.box>>, !fir.ref>>, i1) ! CHECK: _FortranAioOutputDescriptor - ! CHECK: %[[load:.*]] = fir.load %[[alloc]] : !fir.ref>>>> - ! CHECK: %[[addr:.*]] = fir.box_addr %[[load]] : (!fir.box>>>) -> !fir.heap>> - ! CHECK: %[[cmpi:.*]] = arith.cmpi - ! CHECK: fir.if %[[cmpi]] - ! CHECK: fir.freemem %[[addr]] : !fir.heap>> + ! CHECK: hlfir.end_associate %[[assoc]]#1, %[[assoc]]#2 : !fir.ref>>, i1 + ! CHECK: hlfir.destroy %[[as_expr]] : !hlfir.expr> end subroutine -! CHECK-LABEL: func @_QMcallerPpointer_test() +! CHECK-LABEL: func.func @_QMcallerPpointer_test() subroutine pointer_test() - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.box>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_pointer() {{.*}}: () -> !fir.box>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]] : !fir.box>>, !fir.ref>>> + ! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>> {bindc_name = ".result"} + ! CHECK: %[[VAL_5:.*]] = fir.call @_QMcalleePreturn_pointer() {{.*}}: () -> !fir.box>> + ! CHECK: fir.save_result %[[VAL_5]] to %[[VAL_0]] : !fir.box>>, !fir.ref>>> print *, return_pointer() + ! CHECK: %[[load:.*]] = fir.load %{{.*}} : !fir.ref>>> + ! CHECK: _FortranAioOutputDescriptor ! CHECK-NOT: fir.freemem end subroutine -! CHECK-LABEL: func @_QMcallerPcst_char_pointer() +! CHECK-LABEL: func.func @_QMcallerPcst_char_pointer() subroutine cst_char_pointer() - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.box>>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_cst_char_pointer() {{.*}}: () -> !fir.box>>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]] : !fir.box>>>, !fir.ref>>>> + ! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>>> {bindc_name = ".result"} + ! CHECK: %[[VAL_9:.*]] = fir.call @_QMcalleePreturn_cst_char_pointer() {{.*}}: () -> !fir.box>>> + ! CHECK: fir.save_result %[[VAL_9]] to %[[VAL_0]] : !fir.box>>>, !fir.ref>>>> print *, return_cst_char_pointer() + ! CHECK: %[[load:.*]] = fir.load %{{.*}} : !fir.ref>>>> + ! CHECK: _FortranAioOutputDescriptor ! CHECK-NOT: fir.freemem end subroutine -! CHECK-LABEL: func @_QMcallerPdef_char_pointer() +! CHECK-LABEL: func.func @_QMcallerPdef_char_pointer() subroutine def_char_pointer() - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.box>>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_def_char_pointer() {{.*}}: () -> !fir.box>>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]] : !fir.box>>>, !fir.ref>>>> + ! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>>> {bindc_name = ".result"} + ! CHECK: %[[VAL_5:.*]] = fir.call @_QMcalleePreturn_def_char_pointer() {{.*}}: () -> !fir.box>>> + ! CHECK: fir.save_result %[[VAL_5]] to %[[VAL_0]] : !fir.box>>>, !fir.ref>>>> print *, return_def_char_pointer() + ! CHECK: %[[load:.*]] = fir.load %{{.*}} : !fir.ref>>>> + ! CHECK: _FortranAioOutputDescriptor ! CHECK-NOT: fir.freemem end subroutine -! CHECK-LABEL: func @_QMcallerPdyn_array( +! CHECK-LABEL: func.func @_QMcallerPdyn_array( ! CHECK-SAME: %[[m:.*]]: !fir.ref{{.*}}, %[[n:.*]]: !fir.ref{{.*}}) { subroutine dyn_array(m, n) integer :: m, n - ! CHECK-DAG: %[[mload:.*]] = fir.load %[[m]] : !fir.ref - ! CHECK-DAG: %[[mcast:.*]] = fir.convert %[[mload]] : (i32) -> i64 - ! CHECK-DAG: %[[msub:.*]] = arith.subi %[[mcast]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[madd:.*]] = arith.addi %[[msub]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[mcast2:.*]] = fir.convert %[[madd]] : (i64) -> index - ! CHECK-DAG: %[[mcmpi:.*]] = arith.cmpi sgt, %[[mcast2]], %{{.*}} : index - ! CHECK-DAG: %[[mselect:.*]] = arith.select %[[mcmpi]], %[[mcast2]], %{{.*}} : index - ! CHECK-DAG: %[[nload:.*]] = fir.load %[[n]] : !fir.ref - ! CHECK-DAG: %[[ncast:.*]] = fir.convert %[[nload]] : (i32) -> i64 - ! CHECK-DAG: %[[nsub:.*]] = arith.subi %[[ncast]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[nadd:.*]] = arith.addi %[[nsub]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[ncast2:.*]] = fir.convert %[[nadd]] : (i64) -> index - ! CHECK-DAG: %[[ncmpi:.*]] = arith.cmpi sgt, %[[ncast2]], %{{.*}} : index - ! CHECK-DAG: %[[nselect:.*]] = arith.select %[[ncmpi]], %[[ncast2]], %{{.*}} : index - ! CHECK: %[[shape:.*]] = fir.shape %[[mselect]], %[[nselect]] : (index, index) -> !fir.shape<2> - ! CHECK: %[[tmp:.*]] = fir.alloca !fir.array, %[[mselect]], %[[nselect]] - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_dyn_array(%[[m]], %[[n]]) {{.*}}: (!fir.ref, !fir.ref) -> !fir.array - ! CHECK: fir.save_result %[[res]] to %[[tmp]](%[[shape]]) : !fir.array, !fir.ref>, !fir.shape<2> + ! CHECK: %[[VAL_22:.*]] = fir.shape %{{.*}}, %{{.*}} : (index, index) -> !fir.shape<2> + ! CHECK: %[[VAL_23:.*]] = hlfir.eval_in_mem shape %[[VAL_22]] : (!fir.shape<2>) -> !hlfir.expr { + ! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>): + ! CHECK: %[[RES:.*]] = fir.call @_QMcalleePreturn_dyn_array(%{{.*}}, %{{.*}}) {{.*}}: (!fir.ref, !fir.ref) -> !fir.array + ! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_22]]) : !fir.array, !fir.ref>, !fir.shape<2> + ! CHECK: } + ! CHECK: %[[VAL_24:.*]]:3 = hlfir.associate %[[VAL_23]](%[[VAL_22]]) {adapt.valuebyref} print *, return_dyn_array(m, n) + ! CHECK: _FortranAioOutputDescriptor + ! CHECK: hlfir.end_associate %[[VAL_24]]#1, %[[VAL_24]]#2 : !fir.ref>, i1 + ! CHECK: hlfir.destroy %[[VAL_23]] : !hlfir.expr end subroutine -! CHECK-LABEL: func @_QMcallerPdyn_char_cst_array( +! CHECK-LABEL: func.func @_QMcallerPdyn_char_cst_array( ! CHECK-SAME: %[[l:.*]]: !fir.ref{{.*}}) { subroutine dyn_char_cst_array(l) integer :: l - ! CHECK: %[[lload:.*]] = fir.load %[[l]] : !fir.ref - ! CHECK: %[[lcast:.*]] = fir.convert %[[lload]] : (i32) -> i64 - ! CHECK: %[[lcast2:.*]] = fir.convert %[[lcast]] : (i64) -> index - ! CHECK: %[[cmpi:.*]] = arith.cmpi sgt, %[[lcast2]], %{{.*}} : index - ! CHECK: %[[select:.*]] = arith.select %[[cmpi]], %[[lcast2]], %{{.*}} : index - ! CHECK: %[[shape:.*]] = fir.shape %{{.*}}, %{{.*}} : (index, index) -> !fir.shape<2> - ! CHECK: %[[tmp:.*]] = fir.alloca !fir.array<20x30x!fir.char<1,?>>(%[[select]] : index) - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_dyn_char_cst_array(%[[l]]) {{.*}}: (!fir.ref) -> !fir.array<20x30x!fir.char<1,?>> - ! CHECK: fir.save_result %[[res]] to %[[tmp]](%[[shape]]) typeparams %[[select]] : !fir.array<20x30x!fir.char<1,?>>, !fir.ref>>, !fir.shape<2>, index + ! CHECK: %[[VAL_21:.*]] = fir.shape %{{.*}}, %{{.*}} : (index, index) -> !fir.shape<2> + ! CHECK: %[[VAL_22:.*]] = hlfir.eval_in_mem shape %[[VAL_21]] typeparams %[[VAL_20:.*]] : (!fir.shape<2>, index) -> !hlfir.expr<20x30x!fir.char<1,?>> { + ! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>>): + ! CHECK: %[[RES:.*]] = fir.call @_QMcalleePreturn_dyn_char_cst_array(%{{.*}}) {{.*}}: (!fir.ref) -> !fir.array<20x30x!fir.char<1,?>> + ! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_21]]) typeparams %[[VAL_20]] : !fir.array<20x30x!fir.char<1,?>>, !fir.ref>>, !fir.shape<2>, index + ! CHECK: } + ! CHECK: %[[VAL_23:.*]]:3 = hlfir.associate %[[VAL_22]](%[[VAL_21]]) typeparams %[[VAL_20]] {adapt.valuebyref} print *, return_dyn_char_cst_array(l) + ! CHECK: _FortranAioOutputDescriptor + ! CHECK: hlfir.end_associate %[[VAL_23]]#1, %[[VAL_23]]#2 : !fir.ref>>, i1 + ! CHECK: hlfir.destroy %[[VAL_22]] : !hlfir.expr<20x30x!fir.char<1,?>> end subroutine -! CHECK-LABEL: func @_QMcallerPcst_char_dyn_array( +! CHECK-LABEL: func.func @_QMcallerPcst_char_dyn_array( ! CHECK-SAME: %[[m:.*]]: !fir.ref{{.*}}, %[[n:.*]]: !fir.ref{{.*}}) { subroutine cst_char_dyn_array(m, n) integer :: m, n - ! CHECK-DAG: %[[mload:.*]] = fir.load %[[m]] : !fir.ref - ! CHECK-DAG: %[[mcast:.*]] = fir.convert %[[mload]] : (i32) -> i64 - ! CHECK-DAG: %[[msub:.*]] = arith.subi %[[mcast]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[madd:.*]] = arith.addi %[[msub]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[mcast2:.*]] = fir.convert %[[madd]] : (i64) -> index - ! CHECK-DAG: %[[mcmpi:.*]] = arith.cmpi sgt, %[[mcast2]], %{{.*}} : index - ! CHECK-DAG: %[[mselect:.*]] = arith.select %[[mcmpi]], %[[mcast2]], %{{.*}} : index - ! CHECK-DAG: %[[nload:.*]] = fir.load %[[n]] : !fir.ref - ! CHECK-DAG: %[[ncast:.*]] = fir.convert %[[nload]] : (i32) -> i64 - ! CHECK-DAG: %[[nsub:.*]] = arith.subi %[[ncast]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[nadd:.*]] = arith.addi %[[nsub]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[ncast2:.*]] = fir.convert %[[nadd]] : (i64) -> index - ! CHECK-DAG: %[[ncmpi:.*]] = arith.cmpi sgt, %[[ncast2]], %{{.*}} : index - ! CHECK-DAG: %[[nselect:.*]] = arith.select %[[ncmpi]], %[[ncast2]], %{{.*}} : index - ! CHECK: %[[shape:.*]] = fir.shape %[[mselect]], %[[nselect]] : (index, index) -> !fir.shape<2> - ! CHECK: %[[tmp:.*]] = fir.alloca !fir.array>, %[[mselect]], %[[nselect]] - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_cst_char_dyn_array(%[[m]], %[[n]]) {{.*}}: (!fir.ref, !fir.ref) -> !fir.array> - ! CHECK: fir.save_result %[[res]] to %[[tmp]](%[[shape]]) typeparams {{.*}} : !fir.array>, !fir.ref>>, !fir.shape<2>, index + ! CHECK: %[[VAL_25:.*]] = fir.shape %{{.*}}, %{{.*}} : (index, index) -> !fir.shape<2> + ! CHECK: %[[VAL_26:.*]] = hlfir.eval_in_mem shape %[[VAL_25]] typeparams %[[VAL_24:.*]] : (!fir.shape<2>, index) -> !hlfir.expr> { + ! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>>): + ! CHECK: %[[RES:.*]] = fir.call @_QMcalleePreturn_cst_char_dyn_array(%{{.*}}, %{{.*}}) {{.*}}: (!fir.ref, !fir.ref) -> !fir.array> + ! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_25]]) typeparams %[[VAL_24]] : !fir.array>, !fir.ref>>, !fir.shape<2>, index + ! CHECK: } + ! CHECK: %[[VAL_27:.*]]:3 = hlfir.associate %[[VAL_26]](%[[VAL_25]]) typeparams %[[VAL_24]] {adapt.valuebyref} print *, return_cst_char_dyn_array(m, n) + ! CHECK: _FortranAioOutputDescriptor + ! CHECK: hlfir.end_associate %[[VAL_27]]#1, %[[VAL_27]]#2 : !fir.ref>>, i1 + ! CHECK: hlfir.destroy %[[VAL_26]] : !hlfir.expr> end subroutine -! CHECK-LABEL: func @_QMcallerPdyn_char_dyn_array( +! CHECK-LABEL: func.func @_QMcallerPdyn_char_dyn_array( ! CHECK-SAME: %[[l:.*]]: !fir.ref{{.*}}, %[[m:.*]]: !fir.ref{{.*}}, %[[n:.*]]: !fir.ref{{.*}}) { subroutine dyn_char_dyn_array(l, m, n) - ! CHECK-DAG: %[[mload:.*]] = fir.load %[[m]] : !fir.ref - ! CHECK-DAG: %[[mcast:.*]] = fir.convert %[[mload]] : (i32) -> i64 - ! CHECK-DAG: %[[msub:.*]] = arith.subi %[[mcast]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[madd:.*]] = arith.addi %[[msub]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[mcast2:.*]] = fir.convert %[[madd]] : (i64) -> index - ! CHECK-DAG: %[[mcmpi:.*]] = arith.cmpi sgt, %[[mcast2]], %{{.*}} : index - ! CHECK-DAG: %[[mselect:.*]] = arith.select %[[mcmpi]], %[[mcast2]], %{{.*}} : index - - ! CHECK-DAG: %[[nload:.*]] = fir.load %[[n]] : !fir.ref - ! CHECK-DAG: %[[ncast:.*]] = fir.convert %[[nload]] : (i32) -> i64 - ! CHECK-DAG: %[[nsub:.*]] = arith.subi %[[ncast]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[nadd:.*]] = arith.addi %[[nsub]], %c1{{.*}} : i64 - ! CHECK-DAG: %[[ncast2:.*]] = fir.convert %[[nadd]] : (i64) -> index - ! CHECK-DAG: %[[ncmpi:.*]] = arith.cmpi sgt, %[[ncast2]], %{{.*}} : index - ! CHECK-DAG: %[[nselect:.*]] = arith.select %[[ncmpi]], %[[ncast2]], %{{.*}} : index - - ! CHECK-DAG: %[[lload:.*]] = fir.load %[[l]] : !fir.ref - ! CHECK-DAG: %[[lcast:.*]] = fir.convert %[[lload]] : (i32) -> i64 - ! CHECK-DAG: %[[lcast2:.*]] = fir.convert %[[lcast]] : (i64) -> index - ! CHECK-DAG: %[[lcmpi:.*]] = arith.cmpi sgt, %[[lcast2]], %{{.*}} : index - ! CHECK-DAG: %[[lselect:.*]] = arith.select %[[lcmpi]], %[[lcast2]], %{{.*}} : index - ! CHECK: %[[shape:.*]] = fir.shape %[[mselect]], %[[nselect]] : (index, index) -> !fir.shape<2> - ! CHECK: %[[tmp:.*]] = fir.alloca !fir.array>(%[[lselect]] : index), %[[mselect]], %[[nselect]] - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_dyn_char_dyn_array(%[[l]], %[[m]], %[[n]]) {{.*}}: (!fir.ref, !fir.ref, !fir.ref) -> !fir.array> - ! CHECK: fir.save_result %[[res]] to %[[tmp]](%[[shape]]) typeparams {{.*}} : !fir.array>, !fir.ref>>, !fir.shape<2>, index + ! CHECK: %[[VAL_29:.*]] = fir.shape %{{.*}}, %{{.*}} : (index, index) -> !fir.shape<2> + ! CHECK: %[[VAL_30:.*]] = hlfir.eval_in_mem shape %[[VAL_29]] typeparams %[[VAL_28:.*]] : (!fir.shape<2>, index) -> !hlfir.expr> { + ! CHECK: ^bb0(%[[ARG:.*]]: !fir.ref>>): + ! CHECK: %[[RES:.*]] = fir.call @_QMcalleePreturn_dyn_char_dyn_array(%{{.*}}, %{{.*}}, %{{.*}}) {{.*}}: (!fir.ref, !fir.ref, !fir.ref) -> !fir.array> + ! CHECK: fir.save_result %[[RES]] to %[[ARG]](%[[VAL_29]]) typeparams %[[VAL_28]] : !fir.array>, !fir.ref>>, !fir.shape<2>, index + ! CHECK: } + ! CHECK: %[[VAL_31:.*]]:3 = hlfir.associate %[[VAL_30]](%[[VAL_29]]) typeparams %[[VAL_28]] {adapt.valuebyref} integer :: l, m, n print *, return_dyn_char_dyn_array(l, m, n) + ! CHECK: _FortranAioOutputDescriptor + ! CHECK: hlfir.end_associate %[[VAL_31]]#1, %[[VAL_31]]#2 : !fir.ref>>, i1 + ! CHECK: hlfir.destroy %[[VAL_30]] : !hlfir.expr> end subroutine -! CHECK-LABEL: @_QMcallerPdyn_char_alloc +! CHECK-LABEL: func.func @_QMcallerPdyn_char_alloc subroutine dyn_char_alloc(l) integer :: l - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.box>>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_dyn_char_alloc({{.*}}) {{.*}}: (!fir.ref) -> !fir.box>>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]] : !fir.box>>>, !fir.ref>>>> + ! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>>> {bindc_name = ".result"} + ! CHECK: %[[VAL_13:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_11:.*]] {uniq_name = ".tmp.func_result"} + ! CHECK: %[[VAL_14:.*]] = fir.call @_QMcalleePreturn_dyn_char_alloc({{.*}}) {{.*}}: (!fir.ref) -> !fir.box>>> + ! CHECK: fir.save_result %[[VAL_14]] to %[[VAL_13]]#0 : !fir.box>>>, !fir.ref>>>> print *, return_dyn_char_alloc(l) ! CHECK: _FortranAioOutputDescriptor - ! CHECK: %[[load:.*]] = fir.load %[[alloc]] : !fir.ref>>>> - ! CHECK: %[[addr:.*]] = fir.box_addr %[[load]] : (!fir.box>>>) -> !fir.heap>> - ! CHECK: %[[cmpi:.*]] = arith.cmpi - ! CHECK: fir.if %[[cmpi]] - ! CHECK: fir.freemem %[[addr]] : !fir.heap>> + ! CHECK: hlfir.destroy %{{.*}} : !hlfir.expr> end subroutine -! CHECK-LABEL: @_QMcallerPdyn_char_pointer +! CHECK-LABEL: func.func @_QMcallerPdyn_char_pointer subroutine dyn_char_pointer(l) integer :: l - ! CHECK: %[[alloc:.*]] = fir.alloca !fir.box>>> {{{.*}}bindc_name = ".result"} - ! CHECK: %[[res:.*]] = fir.call @_QMcalleePreturn_dyn_char_pointer({{.*}}) {{.*}}: (!fir.ref) -> !fir.box>>> - ! CHECK: fir.save_result %[[res]] to %[[alloc]] : !fir.box>>>, !fir.ref>>>> + ! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box>>> {bindc_name = ".result"} + ! CHECK: %[[VAL_13:.*]] = fir.call @_QMcalleePreturn_dyn_char_pointer({{.*}}) {{.*}}: (!fir.ref) -> !fir.box>>> + ! CHECK: fir.save_result %[[VAL_13]] to %[[VAL_0]] : !fir.box>>>, !fir.ref>>>> + ! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_0]] typeparams %[[VAL_11:.*]] {uniq_name = ".tmp.func_result"} print *, return_dyn_char_pointer(l) ! CHECK-NOT: fir.freemem end subroutine @@ -316,13 +299,14 @@ function result_depends_on_equiv_sym() end function end module -! CHECK-LABEL: func @_QPtest_result_depends_on_equiv_sym +! CHECK-LABEL: func.func @_QPtest_result_depends_on_equiv_sym subroutine test_result_depends_on_equiv_sym() use m_with_equiv, only : result_depends_on_equiv_sym ! CHECK: %[[equiv:.*]] = fir.address_of(@_QMm_with_equivEarray) : !fir.ref> ! CHECK: %[[coor:.*]] = fir.coordinate_of %[[equiv]], %c{{.*}} : (!fir.ref>, index) -> !fir.ref ! CHECK: %[[l:.*]] = fir.convert %[[coor]] : (!fir.ref) -> !fir.ptr - ! CHECK: %[[load:.*]] = fir.load %[[l]] : !fir.ptr + ! CHECK: %[[l_decl:.*]]:2 = hlfir.declare %[[l]] storage(%[[equiv]][8]) {uniq_name = "_QMm_with_equivEl"} + ! CHECK: %[[load:.*]] = fir.load %[[l_decl]]#0 : !fir.ptr ! CHECK: %[[lcast:.*]] = fir.convert %[[load]] : (i64) -> index ! CHECK: %[[cmpi:.*]] = arith.cmpi sgt, %[[lcast]], %{{.*}} : index ! CHECK: %[[select:.*]] = arith.select %[[cmpi]], %[[lcast]], %{{.*}} : index @@ -330,7 +314,7 @@ subroutine test_result_depends_on_equiv_sym() print *, result_depends_on_equiv_sym() end subroutine -! CHECK-LABEL: func @_QPtest_depends_on_descriptor( +! CHECK-LABEL: func.func @_QPtest_depends_on_descriptor( ! CHECK-SAME: %[[x:.*]]: !fir.box>{{.*}}) { subroutine test_depends_on_descriptor(x) interface @@ -340,7 +324,7 @@ function depends_on_descriptor(x) end function end interface real :: x(:) - ! CHECK: %[[dims:.*]]:3 = fir.box_dims %arg0, %c0 : (!fir.box>, index) -> (index, index, index) + ! CHECK: %[[dims:.*]]:3 = fir.box_dims %{{.*}}, %c0 : (!fir.box>, index) -> (index, index, index) ! CHECK: %[[extentCast:.*]] = fir.convert %[[dims]]#1 : (index) -> i64 ! CHECK: %[[extent:.*]] = fir.convert %[[extentCast]] : (i64) -> index ! CHECK: %[[cmpi:.*]] = arith.cmpi sgt, %[[extent]], %{{.*}} : index @@ -349,7 +333,7 @@ function depends_on_descriptor(x) print *, depends_on_descriptor(x) end subroutine -! CHECK-LABEL: func @_QPtest_symbol_indirection( +! CHECK-LABEL: func.func @_QPtest_symbol_indirection( ! CHECK-SAME: %[[n:.*]]: !fir.ref{{.*}}) { subroutine test_symbol_indirection(n) interface @@ -362,7 +346,7 @@ function symbol_indirection(c, n) integer(8) :: n character(n) :: c ! CHECK: BeginExternalListOutput - ! CHECK: %[[nload:.*]] = fir.load %[[n]] : !fir.ref + ! CHECK: %[[nload:.*]] = fir.load %{{.*}} : !fir.ref ! CHECK: %[[n_is_positive:.*]] = arith.cmpi sgt, %[[nload]], %c0{{.*}} : i64 ! CHECK: %[[len:.*]] = arith.select %[[n_is_positive]], %[[nload]], %c0{{.*}} : i64 ! CHECK: %[[len_cast:.*]] = fir.convert %[[len]] : (i64) -> index @@ -372,7 +356,7 @@ function symbol_indirection(c, n) print *, symbol_indirection(c, n) end subroutine -! CHECK-LABEL: func @_QPtest_recursion( +! CHECK-LABEL: func.func @_QPtest_recursion( ! CHECK-SAME: %[[res:.*]]: !fir.ref>{{.*}}, %[[resLen:.*]]: index{{.*}}, %[[n:.*]]: !fir.ref{{.*}}) -> !fir.boxchar<1> { function test_recursion(n) result(res) integer(8) :: n @@ -393,42 +377,46 @@ function test_recursion(n) result(res) ! verify that the actual argument for symbol n ("n-1") is used to allocate ! the result, and not the local value of symbol n. - ! CHECK: %[[nLoad:.*]] = fir.load %[[n]] : !fir.ref + ! CHECK: %[[nLoad:.*]] = fir.load %[[n_decl:.*]]#0 : !fir.ref ! CHECK: %[[sub:.*]] = arith.subi %[[nLoad]], %c1{{.*}} : i64 - ! CHECK: fir.store %[[sub]] to %[[nInCall:.*]] : !fir.ref + ! CHECK: %[[nInCall_assoc:.*]]:3 = hlfir.associate %[[sub]] {adapt.valuebyref} : (i64) -> (!fir.ref, !fir.ref, i1) + ! CHECK: %[[nInCall_decl:.*]]:2 = hlfir.declare %[[nInCall_assoc]]#0 {uniq_name = "_QFtest_recursionEn"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK-NOT: fir.alloca !fir.array - ! CHECK: %[[nInCallLoad:.*]] = fir.load %[[nInCall]] : !fir.ref + ! CHECK: %[[nInCallLoad:.*]] = fir.load %[[nInCall_decl]]#0 : !fir.ref ! CHECK: %[[nInCallCast:.*]] = fir.convert %[[nInCallLoad]] : (i64) -> index ! CHECK: %[[cmpi:.*]] = arith.cmpi sgt, %[[nInCallCast]], %{{.*}} : index ! CHECK: %[[select:.*]] = arith.select %[[cmpi]], %[[nInCallCast]], %{{.*}} : index ! CHECK: %[[tmp:.*]] = fir.alloca !fir.char<1,?>(%[[select]] : index) ! CHECK-NOT: fir.alloca !fir.array - ! CHECK: fir.call @_QPtest_recursion(%[[tmp]], {{.*}} + ! CHECK: fir.call @_QPtest_recursion(%[[tmp]], %[[select]], %[[nInCall_assoc]]#0) {{.*}} res = char(some_local(1)) // test_recursion(n-1) + ! CHECK: hlfir.end_associate %[[nInCall_assoc]]#1, %[[nInCall_assoc]]#2 : !fir.ref, i1 ! Verify that symbol n was not remapped to the actual argument passed ! to n in the call (that the temporary mapping was cleaned-up). - ! CHECK: %[[nLoad2:.*]] = fir.load %[[n]] : !fir.ref + ! CHECK: %[[nLoad2:.*]] = fir.load %[[n_decl]]#0 : !fir.ref ! CHECK: OutputInteger64(%{{.*}}, %[[nLoad2]]) print *, n end if end function ! Test call to character function for which only the result type is explicit -! CHECK-LABEL:func @_QPtest_not_entirely_explicit_interface( +! CHECK-LABEL:func.func @_QPtest_not_entirely_explicit_interface( ! CHECK-SAME: %[[n_arg:.*]]: !fir.ref{{.*}}) { subroutine test_not_entirely_explicit_interface(n) integer(8) :: n character(n) :: return_dyn_char_2 print *, return_dyn_char_2(10) - ! CHECK: %[[n:.*]] = fir.load %[[n_arg]] : !fir.ref + ! CHECK: %[[assoc:.*]]:3 = hlfir.associate %c10_i32 {adapt.valuebyref} + ! CHECK: %[[n:.*]] = fir.load %[[n_decl:.*]]#0 : !fir.ref ! CHECK: %[[len:.*]] = fir.convert %[[n]] : (i64) -> index ! CHECK: %[[cmpi:.*]] = arith.cmpi sgt, %[[len]], %{{.*}} : index ! CHECK: %[[select:.*]] = arith.select %[[cmpi]], %[[len]], %{{.*}} : index ! CHECK: %[[result:.*]] = fir.alloca !fir.char<1,?>(%[[select]] : index) {bindc_name = ".result"} - ! CHECK: fir.call @_QPreturn_dyn_char_2(%[[result]], %[[select]], %{{.*}}) {{.*}}: (!fir.ref>, index, !fir.ref) -> !fir.boxchar<1> + ! CHECK: fir.call @_QPreturn_dyn_char_2(%[[result]], %[[select]], %[[assoc]]#0) {{.*}}: (!fir.ref>, index, !fir.ref) -> !fir.boxchar<1> + ! CHECK: hlfir.end_associate %[[assoc]]#1, %[[assoc]]#2 : !fir.ref, i1 end subroutine diff --git a/flang/test/Lower/ext-proc-as-actual-argument-1.f90 b/flang/test/Lower/ext-proc-as-actual-argument-1.f90 index 6ef8e00610086..50da368ab967f 100644 --- a/flang/test/Lower/ext-proc-as-actual-argument-1.f90 +++ b/flang/test/Lower/ext-proc-as-actual-argument-1.f90 @@ -1,19 +1,29 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s ! Test external procedure as actual argument with the implicit character type. -! CHECK-LABEL: func @_QQmain -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QPext_func) : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: %[[VAL_1:.*]] = fir.emboxproc %[[VAL_0]] : ((!fir.ref>, index) -> !fir.boxchar<1>) -> !fir.boxproc<() -> ()> -! CHECK: %[[VAL_2:.*]] = fir.undefined i64 -! CHECK: %[[VAL_3:.*]] = fir.undefined tuple ()>, i64> -! CHECK: %[[VAL_4:.*]] = fir.insert_value %[[VAL_3]], %[[VAL_1]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> -! CHECK: %[[VAL_5:.*]] = fir.insert_value %[[VAL_4]], %[[VAL_2]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> -! CHECK: fir.call @_QFPsub(%[[VAL_5]]) {{.*}}: (tuple ()>, i64>) -> () -! CHECK: return +! CHECK-LABEL: func.func @_QQmain() +! CHECK: %[[VAL_1:.*]] = fir.address_of(@_QPext_func) : (!fir.ref>, index) -> !fir.boxchar<1> +! CHECK: %[[VAL_2:.*]] = fir.emboxproc %[[VAL_1]] : ((!fir.ref>, index) -> !fir.boxchar<1>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_5:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[VAL_6:.*]] = fir.insert_value %[[VAL_5]], %[[VAL_2]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[VAL_7:.*]] = fir.insert_value %[[VAL_6]], %{{.*}}, [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: fir.call @_QFPsub(%[[VAL_7]]) {{.*}}: (tuple ()>, i64>) -> () -! CHECK-LABEL: func @_QPext_func( -! CHECK: %[[ARG_0:.*]]: !fir.ref>, %[[ARG_1:.*]]: index) -> !fir.boxchar<1> { +! CHECK-LABEL: func.func private @_QFPsub( +! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> {fir.char_proc} +! CHECK: %[[VAL_5:.*]] = fir.extract_value %[[VAL_0]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_6:.*]] = fir.box_addr %[[VAL_5]] : (!fir.boxproc<() -> ()>) -> (() -> ()) +! CHECK: %[[VAL_7:.*]] = fir.emboxproc %[[VAL_6]] : (() -> ()) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_8:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[VAL_9:.*]] = fir.insert_value %[[VAL_8]], %[[VAL_7]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[VAL_10:.*]] = fir.insert_value %[[VAL_9]], %{{.*}}, [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: %[[VAL_11:.*]] = fir.extract_value %[[VAL_10]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_16:.*]] = fir.box_addr %[[VAL_11]] : (!fir.boxproc<() -> ()>) -> ((!fir.ref>, index) -> !fir.boxchar<1>) +! CHECK: %[[VAL_18:.*]] = fir.call %[[VAL_16]](%{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, index) -> !fir.boxchar<1> + +! CHECK-LABEL: func.func @_QPext_func( +! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>{{.*}}, %[[VAL_1:.*]]: index{{.*}}) -> !fir.boxchar<1> program m external :: ext_func call sub(ext_func) diff --git a/flang/test/Lower/ext-proc-as-actual-argument-2.f90 b/flang/test/Lower/ext-proc-as-actual-argument-2.f90 index d0544271e0628..4f469791b592b 100644 --- a/flang/test/Lower/ext-proc-as-actual-argument-2.f90 +++ b/flang/test/Lower/ext-proc-as-actual-argument-2.f90 @@ -1,19 +1,27 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir %s -o - | FileCheck %s ! Test external procedure as actual argument with the implicit character type. -! CHECK-LABEL: func @_QQmain -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QPext_func) : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: %[[VAL_1:.*]] = fir.emboxproc %[[VAL_0]] : ((!fir.ref>, index) -> !fir.boxchar<1>) -> !fir.boxproc<() -> ()> -! CHECK: %[[VAL_2:.*]] = fir.undefined i64 -! CHECK: %[[VAL_3:.*]] = fir.undefined tuple ()>, i64> -! CHECK: %[[VAL_4:.*]] = fir.insert_value %[[VAL_3]], %[[VAL_1]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> -! CHECK: %[[VAL_5:.*]] = fir.insert_value %[[VAL_4]], %[[VAL_2]], [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> -! CHECK: fir.call @_QFPsub(%[[VAL_5]]) {{.*}}: (tuple ()>, i64>) -> () -! CHECK: return +! CHECK-LABEL: func.func @_QQmain() +! CHECK: %[[VAL_1:.*]] = fir.address_of(@_QPext_func) : (!fir.ref>, index) -> !fir.boxchar<1> +! CHECK: %[[VAL_2:.*]] = fir.emboxproc %[[VAL_1]] : ((!fir.ref>, index) -> !fir.boxchar<1>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_5:.*]] = fir.undefined tuple ()>, i64> +! CHECK: %[[VAL_6:.*]] = fir.insert_value %[[VAL_5]], %[[VAL_2]], [0 : index] : (tuple ()>, i64>, !fir.boxproc<() -> ()>) -> tuple ()>, i64> +! CHECK: %[[VAL_7:.*]] = fir.insert_value %[[VAL_6]], %{{.*}}, [1 : index] : (tuple ()>, i64>, i64) -> tuple ()>, i64> +! CHECK: fir.call @_QFPsub(%[[VAL_7]]) {{.*}}: (tuple ()>, i64>) -> () + +! CHECK-LABEL: func.func private @_QFPsub( +! CHECK-SAME: %[[VAL_0:.*]]: tuple ()>, i64> {fir.char_proc} +! CHECK: %[[VAL_5:.*]] = fir.extract_value %[[VAL_0]], [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_6:.*]] = fir.box_addr %[[VAL_5]] : (!fir.boxproc<() -> ()>) -> (() -> ()) +! CHECK: %[[VAL_7:.*]] = fir.emboxproc %[[VAL_6]] : (() -> ()) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_11:.*]] = fir.extract_value %{{.*}}, [0 : index] : (tuple ()>, i64>) -> !fir.boxproc<() -> ()> +! CHECK: %[[VAL_16:.*]] = fir.box_addr %[[VAL_11]] : (!fir.boxproc<() -> ()>) -> ((!fir.ref>, index) -> !fir.boxchar<1>) +! CHECK: %[[VAL_18:.*]] = fir.call %[[VAL_16]](%{{.*}}, %{{.*}}) {{.*}}: (!fir.ref>, index) -> !fir.boxchar<1> + +! CHECK-LABEL: func.func @_QPext_func( +! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>{{.*}}, %[[VAL_1:.*]]: index{{.*}}) -> !fir.boxchar<1> -! CHECK-LABEL: func @_QPext_func( -! CHECK: %[[ARG_0:.*]]: !fir.ref>, %[[ARG_1:.*]]: index) -> !fir.boxchar<1> { program m external :: ext_func call sub(ext_func) diff --git a/flang/test/Lower/io-statement-clean-ups.f90 b/flang/test/Lower/io-statement-clean-ups.f90 index 7e590e7236322..c8a48e8f7bcf0 100644 --- a/flang/test/Lower/io-statement-clean-ups.f90 +++ b/flang/test/Lower/io-statement-clean-ups.f90 @@ -13,34 +13,44 @@ function gen_temp_character() end interface integer :: status open (10, encoding=gen_temp_character(), file=gen_temp_character(), pad=gen_temp_character(), iostat=status) -! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.box>> -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.box>> -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.box>> -! CHECK: fir.call @_FortranAioBeginOpenUnit -! CHECK: %[[DECLARE3:.*]] = fir.declare %[[VAL_3]] -! CHECK: %[[VAL_15:.*]] = fir.call @_QPgen_temp_character() {{.*}}: () -> !fir.box>> -! CHECK: fir.save_result %[[VAL_15]] to %[[DECLARE3]] : !fir.box>>, !fir.ref>>> -! CHECK: %[[VAL_21:.*]] = fir.call @_FortranAioSetEncoding -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_3]] : !fir.ref>>> -! CHECK: %[[VAL_23:.*]] = fir.box_addr %[[VAL_22]] : (!fir.box>>) -> !fir.heap> -! CHECK: fir.freemem %[[VAL_23]] : !fir.heap> -! CHECK: fir.if %[[VAL_21]] { -! CHECK: %[[DECLARE2:.*]] = fir.declare %[[VAL_2]] -! CHECK: %[[VAL_27:.*]] = fir.call @_QPgen_temp_character() {{.*}}: () -> !fir.box>> -! CHECK: fir.save_result %[[VAL_27]] to %[[DECLARE2]] : !fir.box>>, !fir.ref>>> -! CHECK: %[[VAL_33:.*]] = fir.call @_FortranAioSetFile -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_2]] : !fir.ref>>> -! CHECK: %[[VAL_35:.*]] = fir.box_addr %[[VAL_34]] : (!fir.box>>) -> !fir.heap> -! CHECK: fir.freemem %[[VAL_35]] : !fir.heap> -! CHECK: fir.if %[[VAL_33]] { -! CHECK: %[[DECLARE1:.*]] = fir.declare %[[VAL_1]] -! CHECK: %[[VAL_39:.*]] = fir.call @_QPgen_temp_character() {{.*}}: () -> !fir.box>> -! CHECK: fir.save_result %[[VAL_39]] to %[[DECLARE1]] : !fir.box>>, !fir.ref>>> -! CHECK: fir.call @_FortranAioSetPad -! CHECK: %[[VAL_46:.*]] = fir.load %[[VAL_1]] : !fir.ref>>> -! CHECK: %[[VAL_47:.*]] = fir.box_addr %[[VAL_46]] : (!fir.box>>) -> !fir.heap> -! CHECK: fir.freemem %[[VAL_47]] : !fir.heap> -! CHECK: } -! CHECK: } -! CHECK: fir.call @_FortranAioEndIoStatement +! CHECK: %[[ALLOCA_0:.*]] = fir.alloca !fir.box>> {bindc_name = ".result"} +! CHECK: %[[ALLOCA_1:.*]] = fir.alloca !fir.box>> {bindc_name = ".result"} +! CHECK: %[[ALLOCA_2:.*]] = fir.alloca !fir.box>> {bindc_name = ".result"} +! CHECK: fir.call @_FortranAioBeginOpenUnit +! CHECK: %[[DECLARE_1:.*]] = fir.declare %[[ALLOCA_2]] {uniq_name = ".tmp.func_result"} : (!fir.ref>>>) -> !fir.ref>>> +! CHECK: %[[CALL_1:.*]] = fir.call @_QPgen_temp_character() {{.*}}: () -> !fir.box>> +! CHECK: fir.save_result %[[CALL_1]] to %[[DECLARE_1]] : !fir.box>>, !fir.ref>>> +! CHECK: %[[LOAD_0:.*]] = fir.load %[[DECLARE_1]] : !fir.ref>>> +! CHECK: %[[BOX_ADDR_0:.*]] = fir.box_addr %[[LOAD_0]] : (!fir.box>>) -> !fir.heap> +! CHECK: %[[EMBOXCHAR_0:.*]] = fir.emboxchar %[[BOX_ADDR_0]], %{{.*}} : (!fir.heap>, index) -> !fir.boxchar<1> +! CHECK: %[[BOX_ADDR_1:.*]] = fir.box_addr %[[EMBOXCHAR_0]] : (!fir.boxchar<1>) -> !fir.ref> +! CHECK: %[[CALL_2:.*]] = fir.call @_FortranAioSetEncoding +! CHECK: %[[CONVERT_3:.*]] = fir.convert %[[BOX_ADDR_1]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[CONVERT_3]] : !fir.heap> +! CHECK: fir.if %[[CALL_2]] { +! CHECK: %[[DECLARE_2:.*]] = fir.declare %[[ALLOCA_1]] {uniq_name = ".tmp.func_result"} : (!fir.ref>>>) -> !fir.ref>>> +! CHECK: %[[CALL_3:.*]] = fir.call @_QPgen_temp_character() {{.*}}: () -> !fir.box>> +! CHECK: fir.save_result %[[CALL_3]] to %[[DECLARE_2]] : !fir.box>>, !fir.ref>>> +! CHECK: %[[LOAD_1:.*]] = fir.load %[[DECLARE_2]] : !fir.ref>>> +! CHECK: %[[BOX_ADDR_2:.*]] = fir.box_addr %[[LOAD_1]] : (!fir.box>>) -> !fir.heap> +! CHECK: %[[EMBOXCHAR_1:.*]] = fir.emboxchar %[[BOX_ADDR_2]], %{{.*}} : (!fir.heap>, index) -> !fir.boxchar<1> +! CHECK: %[[BOX_ADDR_3:.*]] = fir.box_addr %[[EMBOXCHAR_1]] : (!fir.boxchar<1>) -> !fir.ref> +! CHECK: %[[CALL_4:.*]] = fir.call @_FortranAioSetFile +! CHECK: %[[CONVERT_6:.*]] = fir.convert %[[BOX_ADDR_3]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[CONVERT_6]] : !fir.heap> +! CHECK: fir.if %[[CALL_4]] { +! CHECK: %[[DECLARE_3:.*]] = fir.declare %[[ALLOCA_0]] {uniq_name = ".tmp.func_result"} : (!fir.ref>>>) -> !fir.ref>>> +! CHECK: %[[CALL_5:.*]] = fir.call @_QPgen_temp_character() {{.*}}: () -> !fir.box>> +! CHECK: fir.save_result %[[CALL_5]] to %[[DECLARE_3]] : !fir.box>>, !fir.ref>>> +! CHECK: %[[LOAD_2:.*]] = fir.load %[[DECLARE_3]] : !fir.ref>>> +! CHECK: %[[BOX_ADDR_4:.*]] = fir.box_addr %[[LOAD_2]] : (!fir.box>>) -> !fir.heap> +! CHECK: %[[EMBOXCHAR_2:.*]] = fir.emboxchar %[[BOX_ADDR_4]], %{{.*}} : (!fir.heap>, index) -> !fir.boxchar<1> +! CHECK: %[[BOX_ADDR_5:.*]] = fir.box_addr %[[EMBOXCHAR_2]] : (!fir.boxchar<1>) -> !fir.ref> +! CHECK: fir.call @_FortranAioSetPad +! CHECK: %[[CONVERT_9:.*]] = fir.convert %[[BOX_ADDR_5]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[CONVERT_9]] : !fir.heap> +! CHECK: } +! CHECK: } +! CHECK: fir.call @_FortranAioEndIoStatement + end subroutine diff --git a/flang/test/Semantics/OpenMP/local-variables.f90 b/flang/test/Semantics/OpenMP/local-variables.f90 new file mode 100644 index 0000000000000..8e7a220319605 --- /dev/null +++ b/flang/test/Semantics/OpenMP/local-variables.f90 @@ -0,0 +1,95 @@ +!RUN: %flang_fc1 -fdebug-unparse-with-symbols -fopenmp %s | FileCheck %s + +!Make sure that the local `bbb`s are their own entities. + +!CHECK-LABEL: !DEF: /f00 (Subroutine) Subprogram +!CHECK-NEXT: subroutine f00 +!CHECK-NEXT: !DEF: /f00/i ObjectEntity INTEGER(4) +!CHECK-NEXT: integer i +!CHECK-NEXT: !$omp parallel +!CHECK-NEXT: block +!CHECK-NEXT: block +!CHECK-NEXT: !DEF: /f00/OtherConstruct1/BlockConstruct1/BlockConstruct1/bbb ObjectEntity INTEGER(4) +!CHECK-NEXT: integer bbb +!CHECK-NEXT: !REF: /f00/OtherConstruct1/BlockConstruct1/BlockConstruct1/bbb +!CHECK-NEXT: bbb = 1 +!CHECK-NEXT: end block +!CHECK-NEXT: block +!CHECK-NEXT: !DEF: /f00/OtherConstruct1/BlockConstruct1/BlockConstruct2/bbb ObjectEntity INTEGER(4) +!CHECK-NEXT: integer bbb +!CHECK-NEXT: !REF: /f00/OtherConstruct1/BlockConstruct1/BlockConstruct2/bbb +!CHECK-NEXT: bbb = 2 +!CHECK-NEXT: end block +!CHECK-NEXT: end block +!CHECK-NEXT: !$omp end parallel +!CHECK-NEXT: end subroutine + +subroutine f00() + integer :: i + !$omp parallel + block + block + integer :: bbb + bbb = 1 + end block + block + integer :: bbb + bbb = 2 + end block + end block + !$omp end parallel +end subroutine + + +!CHECK-LABEL: !DEF: /f01 (Subroutine) Subprogram +!CHECK-NEXT: subroutine f01 +!CHECK-NEXT: !DEF: /f01/i ObjectEntity INTEGER(4) +!CHECK-NEXT: integer i +!CHECK-NEXT: !DEF: /f01/bbb ObjectEntity INTEGER(4) +!CHECK-NEXT: integer bbb +!CHECK-NEXT: !REF: /f01/bbb +!CHECK-NEXT: bbb = 0 +!CHECK-NEXT: !$omp parallel +!CHECK-NEXT: block +!CHECK-NEXT: !DEF: /f01/OtherConstruct1/bbb (OmpShared) HostAssoc INTEGER(4) +!CHECK-NEXT: bbb = 1234 +!CHECK-NEXT: block +!CHECK-NEXT: !DEF: /f01/OtherConstruct1/BlockConstruct1/BlockConstruct1/bbb ObjectEntity INTEGER(4) +!CHECK-NEXT: integer bbb +!CHECK-NEXT: !REF: /f01/OtherConstruct1/BlockConstruct1/BlockConstruct1/bbb +!CHECK-NEXT: bbb = 1 +!CHECK-NEXT: end block +!CHECK-NEXT: block +!CHECK-NEXT: !DEF: /f01/OtherConstruct1/BlockConstruct1/BlockConstruct2/bbb ObjectEntity INTEGER(4) +!CHECK-NEXT: integer bbb +!CHECK-NEXT: !REF: /f01/OtherConstruct1/BlockConstruct1/BlockConstruct2/bbb +!CHECK-NEXT: bbb = 2 +!CHECK-NEXT: end block +!CHECK-NEXT: end block +!CHECK-NEXT: !$omp end parallel +!CHECK-NEXT: !REF: /f01/bbb +!CHECK-NEXT: print *, bbb +!CHECK-NEXT: end subroutine + +subroutine f01() + integer :: i + integer :: bbb + + bbb = 0 + + !$omp parallel + block + bbb = 1234 + block + integer :: bbb + bbb = 1 + end block + block + integer :: bbb + bbb = 2 + end block + end block + !$omp end parallel + + print *, bbb +end subroutine diff --git a/flang/test/Semantics/bug1214.cuf b/flang/test/Semantics/bug1214.cuf index 114fad15ea500..71dc6b14f887a 100644 --- a/flang/test/Semantics/bug1214.cuf +++ b/flang/test/Semantics/bug1214.cuf @@ -14,13 +14,13 @@ module overrides real, intent(in) :: x real, intent(in), device :: y type(realResult) result - result%a = x * y + result%a = x * (y) end elemental function multDeviceHost(x, y) result(result) real, intent(in), device :: x real, intent(in) :: y type(realResult) result - result%a = x * y + result%a = (x) * y end elemental subroutine assignHostResult(lhs, rhs) real, intent(out) :: lhs diff --git a/flang/test/Semantics/bug179580.f90 b/flang/test/Semantics/bug179580.f90 new file mode 100644 index 0000000000000..88ca0c551d2b5 --- /dev/null +++ b/flang/test/Semantics/bug179580.f90 @@ -0,0 +1,9 @@ +!RUN: %python %S/test_errors.py %s %flang_fc1 -pedantic -Werror +type t + real v + integer, pointer :: p +end type +type(t), allocatable :: a +!WARNING: Structure constructor lacks a value for pointer component 'p', NULL() assumed [-Wdefault-struct-constructor-null-pointer] +allocate(a, source=t(v=3.3)) +end diff --git a/flang/test/Semantics/bug2131b.cuf b/flang/test/Semantics/bug2131b.cuf new file mode 100644 index 0000000000000..87886b7a02e90 --- /dev/null +++ b/flang/test/Semantics/bug2131b.cuf @@ -0,0 +1,33 @@ +!RUN: %flang_fc1 -fdebug-unparse %s | FileCheck %s +module rgbCUDA + type rgb + real v(3) + end type + interface assignment (=) + module procedure rgbEqR3 + end interface + interface operator(*) + module procedure rgbTimesR + end interface +contains + attributes(device) subroutine rgbEqR3(rgbout, rin) + type(rgb), intent(out) :: rgbout + real(4), intent(in) :: rin(3) + rgbout%v = rin + end + attributes(device) function rgbTimesR(rgbin, rin) result(res) + type(rgb), intent(in) :: rgbin + real(4), intent(in) :: rin + real(4) :: res(3) + res = rgbin%v * rin + end + attributes(device) function color() result(res) + type(rgb) :: res + real :: attenuation +!CHECK: CALL rgbeqr3(res,[REAL(4)::0._4,0._4,0._4]) + res = [0.0, 0.0, 0.0] + attenuation = 0.5 +!CHECK: CALL rgbeqr3(res,rgbtimesr(res,attenuation)) + res = res * attenuation + end +end diff --git a/flang/test/Semantics/bug2174.f90 b/flang/test/Semantics/bug2174.f90 new file mode 100644 index 0000000000000..fcea9761ccad2 --- /dev/null +++ b/flang/test/Semantics/bug2174.f90 @@ -0,0 +1,6 @@ +!RUN: %python %S/test_errors.py %s %flang_fc1 -pedantic -Werror +!WARNING: Value of local variable 'x' is never used [-Wunused-variable] +real, allocatable:: x(:) +allocate(x(1)) +print *, lbound(x) +end diff --git a/flang/test/Semantics/ignore_tkr05.f90 b/flang/test/Semantics/ignore_tkr05.f90 new file mode 100644 index 0000000000000..006e7a777f42d --- /dev/null +++ b/flang/test/Semantics/ignore_tkr05.f90 @@ -0,0 +1,97 @@ +! RUN: %python %S/test_errors.py %s %flang_fc1 -pedantic +! Tests for ignore_tkr(ac) (allocatable/all + contiguous) with pointers +! Should suppress warnings about applying to pointer/descriptor +! and suppress errors about rank/type mismatch. + +module m_ptr_tkr + interface + subroutine s1(p) + real, pointer :: p(:) + !dir$ ignore_tkr(ac) p + end subroutine + + subroutine s2(p) + real, allocatable :: p(:) + !dir$ ignore_tkr(ac) p + end subroutine + + subroutine s_ct(p) + real, pointer :: p(:) + !dir$ ignore_tkr(ct) p + end subroutine + + subroutine s_c(p) + integer, pointer :: p(:) + !dir$ ignore_tkr(c) p + end subroutine + + subroutine s_ck(p) + real, pointer :: p(:) + !dir$ ignore_tkr(ck) p + end subroutine + + subroutine s_cr(p) + real, pointer :: p(:) + !dir$ ignore_tkr(cr) p + end subroutine + + subroutine s_ckr(p) + real, pointer :: p(:) + !dir$ ignore_tkr(ckr) p + end subroutine + + subroutine s_ctr(p) + real, pointer :: p(:) + !dir$ ignore_tkr(ctr) p + end subroutine + + subroutine s_ctk(p) + real, pointer :: p(:) + !dir$ ignore_tkr(ctk) p + end subroutine + end interface + +contains + subroutine test_ptr_tkr() + real(8), pointer :: p3(:,:,:) + real(8), allocatable :: a3(:,:,:) + + ! Rank mismatch (1 vs 3), Type mismatch (real(4) vs real(8)) + ! Should be ignored due to ignore_tkr(ac) which implies TKR + C. + call s1(p3) + call s2(a3) + + ! ignore_tkr(c): still have type/kind/rank differences + !ERROR: Actual argument type 'REAL(8)' is not compatible with dummy argument type 'INTEGER(4)' + !ERROR: Pointer has rank 1 but target has rank 3 + call s_c(p3) + + ! ignore_tkr(ct): ignore type differences, still have kind/rank differences + !ERROR: Actual argument type 'REAL(8)' is not compatible with dummy argument type 'REAL(4)' + !ERROR: Pointer has rank 1 but target has rank 3 + call s_ct(p3) + + ! ignore_tkr(ck): ignore kind differences, still have type/rank differences + !ERROR: Rank of dummy argument is 1, but actual argument has rank 3 + !ERROR: Pointer has rank 1 but target has rank 3 + call s_ck(p3) + + ! ignore_tkr(cr): ignore rank differences, still have type/kind differences + !ERROR: Actual argument type 'REAL(8)' is not compatible with dummy argument type 'REAL(4)' + !ERROR: Target type REAL(8) is not compatible with pointer type REAL(4) + call s_cr(p3) + + ! ignore_tkr(ckr): ignore kind/rank differences, still have type differences + !ERROR: Target type REAL(8) is not compatible with pointer type REAL(4) + call s_ckr(p3) + + ! ignore_tkr(ctr): ignore type/rank differences, still have kind differences + !ERROR: Actual argument type 'REAL(8)' is not compatible with dummy argument type 'REAL(4)' + call s_ctr(p3) + + ! ignore_tkr(ctk): ignore type/kind differences, still have rank differences + !ERROR: Rank of dummy argument is 1, but actual argument has rank 3 + !ERROR: Pointer has rank 1 but target has rank 3 + call s_ctk(p3) + end subroutine +end module diff --git a/flang/test/Transforms/licm.fir b/flang/test/Transforms/licm.fir index 8a34249a36d97..b8a7ef64845f9 100644 --- a/flang/test/Transforms/licm.fir +++ b/flang/test/Transforms/licm.fir @@ -2012,3 +2012,51 @@ func.func @test_acc_loop_private2_hoisting() { } return } + +// ----- +// Test hoisting of fir.field_index and fir.coordinate_of. +// CHECK-LABEL: func.func @_QMmPtest( +// CHECK-SAME: %[[ARG0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: !fir.ref {fir.bindc_name = "n"}) { +// CHECK: %[[DUMMY_SCOPE_0:.*]] = fir.dummy_scope : !fir.dscope +// CHECK: %[[ADDRESS_OF_0:.*]] = fir.address_of(@_QMmEglob) : !fir.ref>>}>> +// CHECK: %[[DECLARE_0:.*]] = fir.declare %[[ADDRESS_OF_0]] {uniq_name = "_QMmEglob"} : (!fir.ref>>}>>) -> !fir.ref>>}>> +// CHECK: %[[FIELD_INDEX_0:.*]] = fir.field_index a, !fir.type<_QMmTt{a:!fir.box>>}> +// CHECK: %[[COORDINATE_OF_0:.*]] = fir.coordinate_of %[[DECLARE_0]], a : (!fir.ref>>}>>) -> !fir.ref>>> +// CHECK: %[[LOAD_1:.*]] = fir.load %[[COORDINATE_OF_0]] : !fir.ref>>> +// CHECK: %[[BOX_ADDR_0:.*]] = fir.box_addr %[[LOAD_1]] : (!fir.box>>) -> !fir.heap> +// CHECK: %[[CONSTANT_2:.*]] = arith.constant 0 : index +// CHECK: %[[BOX_DIMS_0:.*]]:3 = fir.box_dims %[[LOAD_1]], %[[CONSTANT_2]] : (!fir.box>>, index) -> (index, index, index) +// CHECK: %[[SHAPE_SHIFT_0:.*]] = fir.shape_shift %[[BOX_DIMS_0]]#0, %[[BOX_DIMS_0]]#1 : (index, index) -> !fir.shapeshift<1> +// CHECK: %[[DO_LOOP_0:.*]] = fir.do_loop +func.func @_QMmPtest(%arg0: !fir.ref {fir.bindc_name = "n"}) { + %cst = arith.constant 1.000000e+00 : f32 + %c1 = arith.constant 1 : index + %0 = fir.dummy_scope : !fir.dscope + %1 = fir.address_of(@_QMmEglob) : !fir.ref>>}>> + %2 = fir.declare %1 {uniq_name = "_QMmEglob"} : (!fir.ref>>}>>) -> !fir.ref>>}>> + %3 = fir.alloca i32 {bindc_name = "i", uniq_name = "_QMmFtestEi"} + %4 = fir.declare %3 {uniq_name = "_QMmFtestEi"} : (!fir.ref) -> !fir.ref + %5 = fir.declare %arg0 dummy_scope %0 arg 1 {uniq_name = "_QMmFtestEn"} : (!fir.ref, !fir.dscope) -> !fir.ref + %6 = fir.load %5 : !fir.ref + %7 = fir.convert %6 : (i32) -> index + %8 = fir.convert %c1 : (index) -> i32 + %9 = fir.do_loop %arg1 = %c1 to %7 step %c1 iter_args(%arg2 = %8) -> (i32) { + fir.store %arg2 to %4 : !fir.ref + %10 = fir.field_index a, !fir.type<_QMmTt{a:!fir.box>>}> + %11 = fir.coordinate_of %2, a : (!fir.ref>>}>>) -> !fir.ref>>> + %12 = fir.load %11 : !fir.ref>>> + %13 = fir.load %4 : !fir.ref + %14 = fir.convert %13 : (i32) -> i64 + %15 = fir.box_addr %12 : (!fir.box>>) -> !fir.heap> + %c0 = arith.constant 0 : index + %16:3 = fir.box_dims %12, %c0 : (!fir.box>>, index) -> (index, index, index) + %17 = fir.shape_shift %16#0, %16#1 : (index, index) -> !fir.shapeshift<1> + %18 = fir.array_coor %15(%17) %14 : (!fir.heap>, !fir.shapeshift<1>, i64) -> !fir.ref + fir.store %cst to %18 : !fir.ref + %19 = fir.load %4 : !fir.ref + %20 = arith.addi %19, %8 overflow : i32 + fir.result %20 : i32 + } + fir.store %9 to %4 : !fir.ref + return +} diff --git a/flang/test/lit.cfg.py b/flang/test/lit.cfg.py index 4221354df34a2..3a87f9ea06803 100644 --- a/flang/test/lit.cfg.py +++ b/flang/test/lit.cfg.py @@ -64,6 +64,7 @@ ".ll", ".fir", ".mlir", + ".s", ] config.substitutions.append(("%PATH%", config.environment["PATH"])) diff --git a/flang/tools/flang-driver/driver.cpp b/flang/tools/flang-driver/driver.cpp index 0840255a739f3..0e7d31a50e105 100644 --- a/flang/tools/flang-driver/driver.cpp +++ b/flang/tools/flang-driver/driver.cpp @@ -83,6 +83,28 @@ static void ExpandResponseFiles(llvm::StringSaver &saver, } } +static bool rejectAssemblyInputs(const llvm::opt::ArgList &args, + clang::DiagnosticsEngine &diags) { + for (const llvm::opt::Arg *arg : args) { + if (arg->getOption().getKind() == llvm::opt::Option::InputClass) { + llvm::StringRef filename(arg->getValue()); + llvm::StringRef ext = filename.rsplit('.').second; + clang::driver::types::ID type = + clang::driver::types::lookupTypeForExtension(ext); + + if (type == clang::driver::types::TY_Asm || + type == clang::driver::types::TY_PP_Asm) { + diags.Report(diags.getCustomDiagID( + clang::DiagnosticsEngine::Error, + "flang does not support assembly files as input: '%0'")) + << filename; + return true; + } + } + } + return false; +} + int main(int argc, const char **argv) { // Initialize variables to call the driver @@ -147,6 +169,11 @@ int main(int argc, const char **argv) { llvm::SmallVector, 4> failingCommands; + // Reject assembly files as flang does not support assembly inputs. + // TODO: Since clang supports this, flang should too. + if (rejectAssemblyInputs(c->getInputArgs(), diags)) + return 1; + // Set the environment variable, FLANG_COMPILER_OPTIONS_STRING, to contain all // the compiler options. This is intended for the frontend driver, // flang -fc1, to enable the implementation of the COMPILER_OPTIONS diff --git a/libc/cmake/modules/prepare_libc_gpu_build.cmake b/libc/cmake/modules/prepare_libc_gpu_build.cmake index 4d12a5917a56f..55cd0242eedeb 100644 --- a/libc/cmake/modules/prepare_libc_gpu_build.cmake +++ b/libc/cmake/modules/prepare_libc_gpu_build.cmake @@ -17,8 +17,8 @@ if(NOT LLVM_LIBC_FULL_BUILD) endif() # Set the required flags globally so standard CMake utilities can compile. -if(LIBC_TARGET_TRIPLE) - set(CMAKE_REQUIRED_FLAGS "--target=${LIBC_TARGET_TRIPLE}") +if(NOT CMAKE_CXX_COMPILER_TARGET) + set(CMAKE_REQUIRED_FLAGS "${LIBC_COMPILE_OPTIONS_DEFAULT}") endif() # Optionally set up a job pool to limit the number of GPU tests run in parallel. diff --git a/libc/config/baremetal/config.json b/libc/config/baremetal/config.json index 259bc9a7dff61..323d866d17a8b 100644 --- a/libc/config/baremetal/config.json +++ b/libc/config/baremetal/config.json @@ -48,5 +48,10 @@ "LIBC_ADD_NULL_CHECKS": { "value": false } + }, + "codegen": { + "LIBC_CONF_ENABLE_STRONG_STACK_PROTECTOR": { + "value": false + } } } diff --git a/libc/docs/dev/printf_behavior.rst b/libc/docs/dev/printf_behavior.rst index ba0578aee3fd8..a825da55367bb 100644 --- a/libc/docs/dev/printf_behavior.rst +++ b/libc/docs/dev/printf_behavior.rst @@ -78,9 +78,13 @@ conversions will be ignored. This reduces code size. This will be set by default on windows platforms as current printf implementation does not support UTF-16 wide characters. +.. _printf_no_nullptr_checks: + LIBC_COPT_PRINTF_NO_NULLPTR_CHECKS ---------------------------------- -When set, this flag disables the nullptr checks in %n and %s. +When set, this flag disables the nullptr checks in %n and %s; passing a null +pointer is undefined behavior. See :ref:`printf_conversion` for the behavior +when nullptr checks are enabled. LIBC_COPT_PRINTF_CONV_ATLAS --------------------------- @@ -188,6 +192,8 @@ If a number passed as a bit width is less than or equal to zero, the conversion is considered invalid. If the provided bit width is larger than the width of uintmax_t, it will be clamped to the width of uintmax_t. +.. _printf_conversion: + ---------- Conversion ---------- @@ -199,7 +205,7 @@ If a conversion specification ends in %, then it will be treated as if it is "%%", ignoring all options. If a null pointer is passed to a %s conversion specification and null pointer -checks are enabled, it will be treated as if the provided string is "null". +checks are enabled, it will be treated as if the provided string is "(null)". If a null pointer is passed to a %n conversion specification and null pointer checks are enabled, the conversion will fail and printf will return a negative diff --git a/libc/docs/dev/undefined_behavior.rst b/libc/docs/dev/undefined_behavior.rst index 4f8ac22919b0a..d0cd4c9c921a9 100644 --- a/libc/docs/dev/undefined_behavior.rst +++ b/libc/docs/dev/undefined_behavior.rst @@ -75,13 +75,11 @@ Path without Leading Slashs in shm_open ---------------------------------------- POSIX.1 leaves that when the name of a shared memory object does not begin with a slash, the behavior is implementation defined. In such cases, the shm_open in LLVM libc is implemented to behave as if the name began with a slash. -Handling of NULL arguments to the 's' format specifier ------------------------------------------------------- -The C standard does not specify behavior for ``printf("%s", NULL)``. We will -print the string literal ``(null)`` unless using the -``LIBC_COPT_PRINTF_NO_NULLPTR_CHECKS`` option described in :ref:`printf -behavior`. -TODO: Move this to printf_behavior. +Handling of NULL arguments to the 's' and 'n' format specifiers +--------------------------------------------------------------- +The C standard does not specify behavior for ``printf("%s", NULL)`` or +``printf("%n", NULL)``. For LLVM-libc, see +:ref:`LIBC_COPT_PRINTF_NO_NULLPTR_CHECKS ` for details. Unknown Math Rounding Direction ------------------------------- diff --git a/libc/docs/gpu/building.rst b/libc/docs/gpu/building.rst index 9f9528b30d9bf..a7791331423dc 100644 --- a/libc/docs/gpu/building.rst +++ b/libc/docs/gpu/building.rst @@ -100,12 +100,12 @@ targeting a GPU architecture. $> TARGET_C_COMPILER= $> TARGET_CXX_COMPILER= $> cmake ../runtimes \ # Point to the runtimes build - -G Ninja \ - -DLLVM_ENABLE_RUNTIMES=libc \ - -DCMAKE_C_COMPILER=$TARGET_C_COMPILER \ - -DCMAKE_CXX_COMPILER=$TARGET_CXX_COMPILER \ - -DLLVM_LIBC_FULL_BUILD=ON \ - -DLLVM_RUNTIMES_TARGET=$TARGET_TRIPLE \ + -G Ninja \ + -DLLVM_ENABLE_RUNTIMES=libc \ + -DCMAKE_C_COMPILER=$TARGET_C_COMPILER \ + -DCMAKE_CXX_COMPILER=$TARGET_CXX_COMPILER \ + -DLLVM_LIBC_FULL_BUILD=ON \ + -DLLVM_DEFAULT_TARGET_TRIPLE=$TARGET_TRIPLE \ -DCMAKE_BUILD_TYPE=Release $> ninja install @@ -113,34 +113,6 @@ The above steps will result in a build targeting one of the supported GPU architectures. Building for multiple targets requires separate CMake invocations. -Standalone cross build ----------------------- - -The GPU build can also be targeted directly as long as the compiler used is a -supported ``clang`` compiler. This method is generally not recommended as it can -only target a single GPU architecture. - -.. code-block:: sh - - $> cd llvm-project # The llvm-project checkout - $> mkdir build # A different build directory for the build tools - $> cd build - $> CLANG_C_COMPILER= # Must be a trunk build - $> CLANG_CXX_COMPILER= # Must be a trunk build - $> TARGET_TRIPLE= - $> cmake ../llvm \ # Point to the llvm directory - -G Ninja \ - -DLLVM_ENABLE_PROJECTS=libc \ - -DCMAKE_C_COMPILER=$CLANG_C_COMPILER \ - -DCMAKE_CXX_COMPILER=$CLANG_CXX_COMPILER \ - -DLLVM_LIBC_FULL_BUILD=ON \ - -DLIBC_TARGET_TRIPLE=$TARGET_TRIPLE \ - -DCMAKE_BUILD_TYPE=Release - $> ninja install - -This will build and install the GPU C library along with all the other LLVM -libraries. - Build overview ============== diff --git a/libc/shared/math.h b/libc/shared/math.h index b58d29d1ee480..66132326c2257 100644 --- a/libc/shared/math.h +++ b/libc/shared/math.h @@ -60,9 +60,12 @@ #include "math/expm1f.h" #include "math/expm1f16.h" #include "math/f16fma.h" +#include "math/f16fmaf.h" +#include "math/f16fmaf128.h" #include "math/f16fmal.h" #include "math/f16sqrt.h" #include "math/f16sqrtl.h" +#include "math/ffmal.h" #include "math/frexpf.h" #include "math/frexpf128.h" #include "math/frexpf16.h" @@ -102,6 +105,7 @@ #include "math/sinpif.h" #include "math/sqrt.h" #include "math/sqrtf.h" +#include "math/sqrtf128.h" #include "math/sqrtf16.h" #include "math/tan.h" #include "math/tanf.h" diff --git a/libc/shared/math/f16fmaf.h b/libc/shared/math/f16fmaf.h new file mode 100644 index 0000000000000..bafbb4b4803b6 --- /dev/null +++ b/libc/shared/math/f16fmaf.h @@ -0,0 +1,31 @@ +//===-- Shared f16fmaf function ---------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SHARED_MATH_F16FMAF_H +#define LLVM_LIBC_SHARED_MATH_F16FMAF_H + +#include "include/llvm-libc-macros/float16-macros.h" +#include "shared/libc_common.h" + +#ifdef LIBC_TYPES_HAS_FLOAT16 + +#include "src/__support/math/f16fmaf.h" + +namespace LIBC_NAMESPACE_DECL { + +namespace shared { + +using math::f16fmaf; + +} // namespace shared + +} // namespace LIBC_NAMESPACE_DECL + +#endif // LIBC_TYPES_HAS_FLOAT16 + +#endif // LLVM_LIBC_SHARED_MATH_F16FMAF_H diff --git a/libc/shared/math/f16fmaf128.h b/libc/shared/math/f16fmaf128.h new file mode 100644 index 0000000000000..56844676a392c --- /dev/null +++ b/libc/shared/math/f16fmaf128.h @@ -0,0 +1,32 @@ +//===-- Shared f16fmaf128 function ------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SHARED_MATH_F16FMAF128_H +#define LLVM_LIBC_SHARED_MATH_F16FMAF128_H + +#include "include/llvm-libc-macros/float16-macros.h" +#include "include/llvm-libc-types/float128.h" +#include "shared/libc_common.h" + +#ifdef LIBC_TYPES_HAS_FLOAT128 +#ifdef LIBC_TYPES_HAS_FLOAT16 + +#include "src/__support/math/f16fmaf128.h" + +namespace LIBC_NAMESPACE_DECL { +namespace shared { + +using math::f16fmaf128; + +} // namespace shared +} // namespace LIBC_NAMESPACE_DECL + +#endif // LIBC_TYPES_HAS_FLOAT16 +#endif // LIBC_TYPES_HAS_FLOAT128 + +#endif // LLVM_LIBC_SHARED_MATH_F16FMAF128_H diff --git a/libc/shared/math/ffmal.h b/libc/shared/math/ffmal.h new file mode 100644 index 0000000000000..51e20cbed70f5 --- /dev/null +++ b/libc/shared/math/ffmal.h @@ -0,0 +1,25 @@ +//===-- Shared ffmal function -----------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SHARED_MATH_FFMAL_H +#define LLVM_LIBC_SHARED_MATH_FFMAL_H + +#include "shared/libc_common.h" +#include "src/__support/math/ffmal.h" + +namespace LIBC_NAMESPACE_DECL { + +namespace shared { + +using math::ffmal; + +} // namespace shared + +} // namespace LIBC_NAMESPACE_DECL + +#endif // LLVM_LIBC_SHARED_MATH_FFMAL_H diff --git a/libc/shared/math/sqrtf128.h b/libc/shared/math/sqrtf128.h new file mode 100644 index 0000000000000..609b8921ab36b --- /dev/null +++ b/libc/shared/math/sqrtf128.h @@ -0,0 +1,29 @@ +//===-- Shared sqrtf128 function -------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SHARED_MATH_SQRTF128_H +#define LLVM_LIBC_SHARED_MATH_SQRTF128_H + +#include "include/llvm-libc-types/float128.h" + +#ifdef LIBC_TYPES_HAS_FLOAT128 + +#include "shared/libc_common.h" +#include "src/__support/math/sqrtf128.h" + +namespace LIBC_NAMESPACE_DECL { +namespace shared { + +using math::sqrtf128; + +} // namespace shared +} // namespace LIBC_NAMESPACE_DECL + +#endif // LIBC_TYPES_HAS_FLOAT128 + +#endif // LLVM_LIBC_SHARED_MATH_SQRTF128_H diff --git a/libc/src/__support/ctype_utils.h b/libc/src/__support/ctype_utils.h index d60562c02e81c..515eca18f9e4c 100644 --- a/libc/src/__support/ctype_utils.h +++ b/libc/src/__support/ctype_utils.h @@ -37,7 +37,7 @@ namespace internal { // EBCDIC. Technically we could use some smaller ranges, but that's even harder // to read. -LIBC_INLINE static constexpr bool islower(char ch) { +LIBC_INLINE constexpr bool islower(char ch) { switch (ch) { case 'a': case 'b': @@ -71,7 +71,7 @@ LIBC_INLINE static constexpr bool islower(char ch) { } } -LIBC_INLINE static constexpr bool isupper(char ch) { +LIBC_INLINE constexpr bool isupper(char ch) { switch (ch) { case 'A': case 'B': @@ -105,7 +105,7 @@ LIBC_INLINE static constexpr bool isupper(char ch) { } } -LIBC_INLINE static constexpr bool isdigit(char ch) { +LIBC_INLINE constexpr bool isdigit(char ch) { switch (ch) { case '0': case '1': @@ -123,7 +123,7 @@ LIBC_INLINE static constexpr bool isdigit(char ch) { } } -LIBC_INLINE static constexpr char tolower(char ch) { +LIBC_INLINE constexpr char tolower(char ch) { switch (ch) { case 'A': return 'a'; @@ -182,7 +182,7 @@ LIBC_INLINE static constexpr char tolower(char ch) { } } -LIBC_INLINE static constexpr char toupper(char ch) { +LIBC_INLINE constexpr char toupper(char ch) { switch (ch) { case 'a': return 'A'; @@ -241,7 +241,7 @@ LIBC_INLINE static constexpr char toupper(char ch) { } } -LIBC_INLINE static constexpr bool isalpha(char ch) { +LIBC_INLINE constexpr bool isalpha(char ch) { switch (ch) { case 'a': case 'b': @@ -301,7 +301,7 @@ LIBC_INLINE static constexpr bool isalpha(char ch) { } } -LIBC_INLINE static constexpr bool isalnum(char ch) { +LIBC_INLINE constexpr bool isalnum(char ch) { switch (ch) { case 'a': case 'b': @@ -371,7 +371,7 @@ LIBC_INLINE static constexpr bool isalnum(char ch) { } } -LIBC_INLINE static constexpr int b36_char_to_int(char ch) { +LIBC_INLINE constexpr int b36_char_to_int(char ch) { switch (ch) { case '0': return 0; @@ -476,7 +476,7 @@ LIBC_INLINE static constexpr int b36_char_to_int(char ch) { } } -LIBC_INLINE static constexpr char int_to_b36_char(int num) { +LIBC_INLINE constexpr char int_to_b36_char(int num) { // Can't actually use LIBC_ASSERT here because it depends on integer_to_string // which depends on this. @@ -559,7 +559,7 @@ LIBC_INLINE static constexpr char int_to_b36_char(int num) { } } -LIBC_INLINE static constexpr bool isspace(char ch) { +LIBC_INLINE constexpr bool isspace(char ch) { switch (ch) { case ' ': case '\t': @@ -574,14 +574,12 @@ LIBC_INLINE static constexpr bool isspace(char ch) { } // not yet encoding independent. -LIBC_INLINE static constexpr bool isgraph(char ch) { - return 0x20 < ch && ch < 0x7f; -} +LIBC_INLINE constexpr bool isgraph(char ch) { return 0x20 < ch && ch < 0x7f; } // An overload which provides a way to compare input with specific character // values, when input can be of a regular or a wide character type. -LIBC_INLINE static constexpr bool is_char_or_wchar(char ch, char c_value, - [[maybe_unused]] wchar_t) { +LIBC_INLINE constexpr bool is_char_or_wchar(char ch, char c_value, + [[maybe_unused]] wchar_t) { return (ch == c_value); } diff --git a/libc/src/__support/fixed_point/fx_bits.h b/libc/src/__support/fixed_point/fx_bits.h index 25221d9a33161..91814bda7dd7e 100644 --- a/libc/src/__support/fixed_point/fx_bits.h +++ b/libc/src/__support/fixed_point/fx_bits.h @@ -23,8 +23,6 @@ #include "fx_rep.h" -#include - #ifdef LIBC_COMPILER_HAS_FIXED_POINT namespace LIBC_NAMESPACE_DECL { diff --git a/libc/src/__support/math/CMakeLists.txt b/libc/src/__support/math/CMakeLists.txt index 58e4040911f8e..c0293c0969217 100644 --- a/libc/src/__support/math/CMakeLists.txt +++ b/libc/src/__support/math/CMakeLists.txt @@ -593,6 +593,16 @@ add_header_library( libc.src.__support.math.exp10_float16_constants ) +add_header_library( + ffmal + HDRS + ffmal.h + DEPENDS + libc.src.__support.common + libc.src.__support.FPUtil.fma + libc.src.__support.macros.config +) + add_header_library( f16sqrt HDRS @@ -675,6 +685,28 @@ add_header_library( libc.include.llvm-libc-macros.float16_macros ) +add_header_library( + f16fmaf + HDRS + f16fmaf.h + DEPENDS + libc.src.__support.macros.config + libc.src.__support.FPUtil.fma + libc.include.llvm-libc-macros.float16_macros +) + +add_header_library( + f16fmaf128 + HDRS + f16fmaf128.h + DEPENDS + libc.src.__support.FPUtil.fma + libc.src.__support.common + libc.src.__support.macros.config + libc.include.llvm-libc-types.float128 + libc.include.llvm-libc-macros.float16_macros +) + add_header_library( f16fmal HDRS @@ -1490,6 +1522,21 @@ add_header_library( libc.include.llvm-libc-types.float128 ) +add_header_library( + sqrtf128 + HDRS + sqrtf128.h + DEPENDS + libc.src.__support.CPP.bit + libc.src.__support.FPUtil.fenv_impl + libc.src.__support.FPUtil.fp_bits + libc.src.__support.FPUtil.rounding_mode + libc.src.__support.common + libc.src.__support.macros.optimization + libc.src.__support.uint128 + libc.include.llvm-libc-types.float128 +) + add_header_library( tan HDRS diff --git a/libc/src/__support/math/acos.h b/libc/src/__support/math/acos.h index 0e1e413870844..6b419449176fd 100644 --- a/libc/src/__support/math/acos.h +++ b/libc/src/__support/math/acos.h @@ -24,7 +24,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr double acos(double x) { +LIBC_INLINE constexpr double acos(double x) { using DoubleDouble = fputil::DoubleDouble; using namespace asin_internal; using FPBits = fputil::FPBits; diff --git a/libc/src/__support/math/acosf.h b/libc/src/__support/math/acosf.h index 7a0c0e535a8a1..4cdf8ef704f25 100644 --- a/libc/src/__support/math/acosf.h +++ b/libc/src/__support/math/acosf.h @@ -26,26 +26,27 @@ namespace acosf_internal { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS -static constexpr size_t N_EXCEPTS = 4; +LIBC_INLINE_VAR constexpr size_t N_EXCEPTS = 4; // Exceptional values when |x| <= 0.5 -static constexpr fputil::ExceptValues ACOSF_EXCEPTS = {{ - // (inputs, RZ output, RU offset, RD offset, RN offset) - // x = 0x1.110b46p-26, acosf(x) = 0x1.921fb4p0 (RZ) - {0x328885a3, 0x3fc90fda, 1, 0, 1}, - // x = -0x1.110b46p-26, acosf(x) = 0x1.921fb4p0 (RZ) - {0xb28885a3, 0x3fc90fda, 1, 0, 1}, - // x = 0x1.04c444p-12, acosf(x) = 0x1.920f68p0 (RZ) - {0x39826222, 0x3fc907b4, 1, 0, 1}, - // x = -0x1.04c444p-12, acosf(x) = 0x1.923p0 (RZ) - {0xb9826222, 0x3fc91800, 1, 0, 1}, -}}; +LIBC_INLINE_VAR constexpr fputil::ExceptValues ACOSF_EXCEPTS = + {{ + // (inputs, RZ output, RU offset, RD offset, RN offset) + // x = 0x1.110b46p-26, acosf(x) = 0x1.921fb4p0 (RZ) + {0x328885a3, 0x3fc90fda, 1, 0, 1}, + // x = -0x1.110b46p-26, acosf(x) = 0x1.921fb4p0 (RZ) + {0xb28885a3, 0x3fc90fda, 1, 0, 1}, + // x = 0x1.04c444p-12, acosf(x) = 0x1.920f68p0 (RZ) + {0x39826222, 0x3fc907b4, 1, 0, 1}, + // x = -0x1.04c444p-12, acosf(x) = 0x1.923p0 (RZ) + {0xb9826222, 0x3fc91800, 1, 0, 1}, + }}; #endif // !LIBC_MATH_HAS_SKIP_ACCURATE_PASS } // namespace acosf_internal -LIBC_INLINE static constexpr float acosf(float x) { +LIBC_INLINE constexpr float acosf(float x) { using namespace acosf_internal; using namespace inv_trigf_utils_internal; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/acosf16.h b/libc/src/__support/math/acosf16.h index 3f0e002a590e0..49cd203919aeb 100644 --- a/libc/src/__support/math/acosf16.h +++ b/libc/src/__support/math/acosf16.h @@ -26,7 +26,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 acosf16(float16 x) { +LIBC_INLINE constexpr float16 acosf16(float16 x) { // Generated by Sollya using the following command: // > round(pi/2, SG, RN); diff --git a/libc/src/__support/math/acosh_float_constants.h b/libc/src/__support/math/acosh_float_constants.h index 2eb245d8265e0..f27e126099c7c 100644 --- a/libc/src/__support/math/acosh_float_constants.h +++ b/libc/src/__support/math/acosh_float_constants.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_MATH_ACOSH_FLOAT_CONSTANTS_H #define LLVM_LIBC_SRC___SUPPORT_MATH_ACOSH_FLOAT_CONSTANTS_H +#include "src/__support/macros/attributes.h" #include "src/__support/macros/config.h" namespace LIBC_NAMESPACE_DECL { @@ -16,7 +17,7 @@ namespace LIBC_NAMESPACE_DECL { namespace acoshf_internal { // Lookup table for (1/f) where f = 1 + n*2^(-7), n = 0..127. -static constexpr double ONE_OVER_F[128] = { +LIBC_INLINE_VAR constexpr double ONE_OVER_F[128] = { 0x1.0000000000000p+0, 0x1.fc07f01fc07f0p-1, 0x1.f81f81f81f820p-1, 0x1.f44659e4a4271p-1, 0x1.f07c1f07c1f08p-1, 0x1.ecc07b301ecc0p-1, 0x1.e9131abf0b767p-1, 0x1.e573ac901e574p-1, 0x1.e1e1e1e1e1e1ep-1, @@ -62,7 +63,7 @@ static constexpr double ONE_OVER_F[128] = { 0x1.0204081020408p-1, 0x1.0101010101010p-1}; // Lookup table for log(f) = log(1 + n*2^(-7)) where n = 0..127. -static constexpr double LOG_F[128] = { +LIBC_INLINE_VAR constexpr double LOG_F[128] = { 0x0.0000000000000p+0, 0x1.fe02a6b106788p-8, 0x1.fc0a8b0fc03e3p-7, 0x1.7b91b07d5b11ap-6, 0x1.f829b0e783300p-6, 0x1.39e87b9febd5fp-5, 0x1.77458f632dcfcp-5, 0x1.b42dd711971bep-5, 0x1.f0a30c01162a6p-5, diff --git a/libc/src/__support/math/acoshf.h b/libc/src/__support/math/acoshf.h index 4e003110efafb..acc6fde1378de 100644 --- a/libc/src/__support/math/acoshf.h +++ b/libc/src/__support/math/acoshf.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float acoshf(float x) { +LIBC_INLINE constexpr float acoshf(float x) { using namespace acoshf_internal; using FPBits_t = typename fputil::FPBits; FPBits_t xbits(x); diff --git a/libc/src/__support/math/acoshf16.h b/libc/src/__support/math/acoshf16.h index e5be2a8dd915c..eeb9e9f7afa9d 100644 --- a/libc/src/__support/math/acoshf16.h +++ b/libc/src/__support/math/acoshf16.h @@ -28,7 +28,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 acoshf16(float16 x) { +LIBC_INLINE constexpr float16 acoshf16(float16 x) { using namespace acoshf_internal; constexpr size_t N_EXCEPTS = 2; diff --git a/libc/src/__support/math/acoshf_utils.h b/libc/src/__support/math/acoshf_utils.h index 808c3dd41cfe4..a0002f404a19f 100644 --- a/libc/src/__support/math/acoshf_utils.h +++ b/libc/src/__support/math/acoshf_utils.h @@ -19,7 +19,7 @@ namespace LIBC_NAMESPACE_DECL { namespace acoshf_internal { // x should be positive, normal finite value -LIBC_INLINE static double log_eval(double x) { +LIBC_INLINE double log_eval(double x) { // For x = 2^ex * (1 + mx) // log(x) = ex * log(2) + log(1 + mx) using FPB = fputil::FPBits; diff --git a/libc/src/__support/math/acospif16.h b/libc/src/__support/math/acospif16.h index cf29c7654abc2..4b5c28084f709 100644 --- a/libc/src/__support/math/acospif16.h +++ b/libc/src/__support/math/acospif16.h @@ -25,7 +25,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 acospif16(float16 x) { +LIBC_INLINE constexpr float16 acospif16(float16 x) { using FPBits = fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/asin.h b/libc/src/__support/math/asin.h index 396a5355b9b3b..98e77d0b97454 100644 --- a/libc/src/__support/math/asin.h +++ b/libc/src/__support/math/asin.h @@ -25,7 +25,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static double asin(double x) { +LIBC_INLINE double asin(double x) { using namespace asin_internal; using FPBits = fputil::FPBits; diff --git a/libc/src/__support/math/asin_utils.h b/libc/src/__support/math/asin_utils.h index efe779c8a81fd..2feb1485ec667 100644 --- a/libc/src/__support/math/asin_utils.h +++ b/libc/src/__support/math/asin_utils.h @@ -24,10 +24,11 @@ namespace asin_internal { using DoubleDouble = fputil::DoubleDouble; using Float128 = fputil::DyadicFloat<128>; -static constexpr DoubleDouble PI = {0x1.1a62633145c07p-53, 0x1.921fb54442d18p1}; +LIBC_INLINE_VAR constexpr DoubleDouble PI = {0x1.1a62633145c07p-53, + 0x1.921fb54442d18p1}; -static constexpr DoubleDouble PI_OVER_TWO = {0x1.1a62633145c07p-54, - 0x1.921fb54442d18p0}; +LIBC_INLINE_VAR constexpr DoubleDouble PI_OVER_TWO = {0x1.1a62633145c07p-54, + 0x1.921fb54442d18p0}; #ifdef LIBC_MATH_HAS_SKIP_ACCURATE_PASS @@ -38,7 +39,7 @@ static constexpr DoubleDouble PI_OVER_TWO = {0x1.1a62633145c07p-54, // > dirtyinfnorm(asin(x)/x - P, [0, 0.5]); // 0x1.1a71ef0a0f26a9fb7ed7e41dee788b13d1770db3dp-52 -static constexpr double ASIN_COEFFS[12] = { +LIBC_INLINE_VAR constexpr double ASIN_COEFFS[12] = { 0x1.0000000000000p0, 0x1.5555555556dcfp-3, 0x1.3333333082e11p-4, 0x1.6db6dd14099edp-5, 0x1.f1c69b35bf81fp-6, 0x1.6e97194225a67p-6, 0x1.1babddb82ce12p-6, 0x1.d55bd078600d6p-7, 0x1.33328959e63d6p-7, @@ -123,7 +124,7 @@ LIBC_INLINE double asin_eval(double u) { // > dirtyinfnorm(asin(x)/x - P, [-1/64, 1/64]); // 0x1.999075402cafp-83 -static constexpr double ASIN_COEFFS[9][12] = { +LIBC_INLINE_VAR constexpr double ASIN_COEFFS[9][12] = { {1.0, 0.0, 0x1.5555555555555p-3, 0x1.5555555555555p-57, 0x1.3333333333333p-4, 0x1.6db6db6db6db7p-5, 0x1.f1c71c71c71c7p-6, 0x1.6e8ba2e8ba2e9p-6, 0x1.1c4ec4ec4ec4fp-6, 0x1.c99999999999ap-7, @@ -163,8 +164,8 @@ static constexpr double ASIN_COEFFS[9][12] = { }; // We calculate the lower part of the approximation P(u). -LIBC_INLINE static DoubleDouble asin_eval(const DoubleDouble &u, unsigned &idx, - double &err) { +LIBC_INLINE DoubleDouble asin_eval(const DoubleDouble &u, unsigned &idx, + double &err) { using fputil::multiply_add; // k = round(u * 32). double k = fputil::nearest_integer(u.hi * 0x1.0p5); @@ -238,7 +239,7 @@ LIBC_INLINE static DoubleDouble asin_eval(const DoubleDouble &u, unsigned &idx, // + (676039 x^24)/104857600 + (1300075 x^26)/226492416 + // + (5014575 x^28)/973078528 + (9694845 x^30)/2080374784. -static constexpr Float128 ASIN_COEFFS_F128[17][16] = { +LIBC_INLINE_VAR constexpr Float128 ASIN_COEFFS_F128[17][16] = { { {Sign::POS, -127, 0x80000000'00000000'00000000'00000000_u128}, {Sign::POS, -130, 0xaaaaaaaa'aaaaaaaa'aaaaaaaa'aaaaaaab_u128}, @@ -547,14 +548,13 @@ static constexpr Float128 ASIN_COEFFS_F128[17][16] = { }, }; -static constexpr Float128 PI_OVER_TWO_F128 = { +LIBC_INLINE_VAR constexpr Float128 PI_OVER_TWO_F128 = { Sign::POS, -127, 0xc90fdaa2'2168c234'c4c6628b'80dc1cd1_u128}; -static constexpr Float128 PI_F128 = { +LIBC_INLINE_VAR constexpr Float128 PI_F128 = { Sign::POS, -126, 0xc90fdaa2'2168c234'c4c6628b'80dc1cd1_u128}; -LIBC_INLINE static constexpr Float128 asin_eval(const Float128 &u, - unsigned idx) { +LIBC_INLINE constexpr Float128 asin_eval(const Float128 &u, unsigned idx) { return fputil::polyeval(u, ASIN_COEFFS_F128[idx][0], ASIN_COEFFS_F128[idx][1], ASIN_COEFFS_F128[idx][2], ASIN_COEFFS_F128[idx][3], ASIN_COEFFS_F128[idx][4], ASIN_COEFFS_F128[idx][5], diff --git a/libc/src/__support/math/asinf.h b/libc/src/__support/math/asinf.h index bfa0dc31ecf4c..c00b764a41853 100644 --- a/libc/src/__support/math/asinf.h +++ b/libc/src/__support/math/asinf.h @@ -23,7 +23,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float asinf(float x) { +LIBC_INLINE constexpr float asinf(float x) { using namespace inv_trigf_utils_internal; #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS diff --git a/libc/src/__support/math/asinf16.h b/libc/src/__support/math/asinf16.h index 3d032a41a2bb3..e9c9c6fca9184 100644 --- a/libc/src/__support/math/asinf16.h +++ b/libc/src/__support/math/asinf16.h @@ -25,7 +25,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 asinf16(float16 x) { +LIBC_INLINE constexpr float16 asinf16(float16 x) { // Generated by Sollya using the following command: // > round(pi/2, D, RN); diff --git a/libc/src/__support/math/asinhf.h b/libc/src/__support/math/asinhf.h index 1c08a6e6651b7..b08d30b97b9f1 100644 --- a/libc/src/__support/math/asinhf.h +++ b/libc/src/__support/math/asinhf.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float asinhf(float x) { +LIBC_INLINE constexpr float asinhf(float x) { using namespace acoshf_internal; using FPBits_t = typename fputil::FPBits; FPBits_t xbits(x); diff --git a/libc/src/__support/math/asinhf16.h b/libc/src/__support/math/asinhf16.h index 3c5171e59c11f..39118d9357043 100644 --- a/libc/src/__support/math/asinhf16.h +++ b/libc/src/__support/math/asinhf16.h @@ -29,7 +29,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 asinhf16(float16 x) { +LIBC_INLINE constexpr float16 asinhf16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr size_t N_EXCEPTS = 8; diff --git a/libc/src/__support/math/atan.h b/libc/src/__support/math/atan.h index 62190b092429a..db60311bd746d 100644 --- a/libc/src/__support/math/atan.h +++ b/libc/src/__support/math/atan.h @@ -52,7 +52,7 @@ namespace math { // So we can return: // atan(x) = sign(x) * (pi/2 - epsilon) -LIBC_INLINE static constexpr double atan(double x) { +LIBC_INLINE constexpr double atan(double x) { using namespace atan_internal; using FPBits = fputil::FPBits; diff --git a/libc/src/__support/math/atan2.h b/libc/src/__support/math/atan2.h index 90ed926c8d75f..f59d92b6dc19c 100644 --- a/libc/src/__support/math/atan2.h +++ b/libc/src/__support/math/atan2.h @@ -75,7 +75,7 @@ namespace math { // and relative errors bounded by: // |(atan(u) - P(u)) / P(u)| < u^10 / 11 < 2^-73. -LIBC_INLINE static constexpr double atan2(double y, double x) { +LIBC_INLINE constexpr double atan2(double y, double x) { using namespace atan_internal; using FPBits = fputil::FPBits; diff --git a/libc/src/__support/math/atan2f.h b/libc/src/__support/math/atan2f.h index 0133d12c1e071..15d1fce2b707c 100644 --- a/libc/src/__support/math/atan2f.h +++ b/libc/src/__support/math/atan2f.h @@ -17,7 +17,7 @@ #include "src/__support/FPUtil/multiply_add.h" #include "src/__support/FPUtil/nearest_integer.h" #include "src/__support/macros/config.h" -#include "src/__support/macros/optimization.h" // LIBC_UNLIKELY +#include "src/__support/macros/optimization.h" // LIBC_UNLIKELY #include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA #if defined(LIBC_MATH_HAS_SKIP_ACCURATE_PASS) && \ @@ -45,7 +45,7 @@ namespace atan2f_internal { // b = round(atan(i/16) - a, D, RN); // print("{", b, ",", a, "},"); // }; -static constexpr fputil::DoubleDouble ATAN_I[17] = { +LIBC_INLINE_VAR constexpr fputil::DoubleDouble ATAN_I[17] = { {0.0, 0.0}, {-0x1.c934d86d23f1dp-60, 0x1.ff55bb72cfdeap-5}, {-0x1.cd37686760c17p-59, 0x1.fd5ba9aac2f6ep-4}, @@ -72,7 +72,7 @@ static constexpr fputil::DoubleDouble ATAN_I[17] = { // b = round(j - a, D, RN); // print("{", b, ",", a, "},"); // }; -static constexpr fputil::DoubleDouble COEFFS[9] = { +LIBC_INLINE_VAR constexpr fputil::DoubleDouble COEFFS[9] = { {0.0, 1.0}, // 1 {-0x1.5555555555555p-56, -0x1.5555555555555p-2}, // -1/3 {-0x1.999999999999ap-57, 0x1.999999999999ap-3}, // 1/5 @@ -98,8 +98,7 @@ static constexpr fputil::DoubleDouble COEFFS[9] = { // = 33. // Thus, the Veltkamp splitting constant is C = 2^33 + 1. // This is used when FMA instruction is not available. -[[maybe_unused]] LIBC_INLINE static constexpr fputil::DoubleDouble -split_d(double a) { +[[maybe_unused]] LIBC_INLINE constexpr fputil::DoubleDouble split_d(double a) { fputil::DoubleDouble r{0.0, 0.0}; constexpr double C = 0x1.0p33 + 1.0; double t1 = C * a; @@ -116,10 +115,9 @@ split_d(double a) { // idx, k_d = round( 2^4 * num_d / den_d ) // final_sign = sign of the final result // const_term = the constant term in the final expression. -LIBC_INLINE static float -atan2f_double_double(double num_d, double den_d, double q_d, int idx, - double k_d, double final_sign, - const fputil::DoubleDouble &const_term) { +LIBC_INLINE float atan2f_double_double(double num_d, double den_d, double q_d, + int idx, double k_d, double final_sign, + const fputil::DoubleDouble &const_term) { fputil::DoubleDouble q; double num_r = 0, den_r = 0; @@ -241,7 +239,7 @@ atan2f_double_double(double num_d, double den_d, double q_d, int idx, // 0x1.aec6f...p-100 // which is about rounding errors of double-double (2^-104). -LIBC_INLINE static constexpr float atan2f(float y, float x) { +LIBC_INLINE constexpr float atan2f(float y, float x) { using namespace atan2f_internal; using namespace inv_trigf_utils_internal; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/atan2f128.h b/libc/src/__support/math/atan2f128.h index 89efaf1fd72a0..b2891bdec4c76 100644 --- a/libc/src/__support/math/atan2f128.h +++ b/libc/src/__support/math/atan2f128.h @@ -81,7 +81,7 @@ namespace math { // and relative errors bounded by: // |(atan(u) - P(u)) / P(u)| < 2^-114. -LIBC_INLINE static constexpr float128 atan2f128(float128 y, float128 x) { +LIBC_INLINE constexpr float128 atan2f128(float128 y, float128 x) { using Float128 = fputil::DyadicFloat<128>; constexpr Float128 ZERO = {Sign::POS, 0, 0_u128}; diff --git a/libc/src/__support/math/atan2f_float.h b/libc/src/__support/math/atan2f_float.h index cc5ea77d5dd36..1f44b67749964 100644 --- a/libc/src/__support/math/atan2f_float.h +++ b/libc/src/__support/math/atan2f_float.h @@ -30,7 +30,7 @@ using FloatFloat = fputil::FloatFloat; // b = round(atan(i/16) - a, SG, RN); // print("{", b, ",", a, "},"); // }; -static constexpr FloatFloat ATAN_I[17] = { +LIBC_INLINE_VAR constexpr FloatFloat ATAN_I[17] = { {0.0f, 0.0f}, {-0x1.1a6042p-30f, 0x1.ff55bcp-5f}, {-0x1.54f424p-30f, 0x1.fd5baap-4f}, @@ -60,7 +60,7 @@ static constexpr FloatFloat ATAN_I[17] = { // For x = x_hi + x_lo, fully expand the polynomial and drop any terms less than // ulp(x_hi^3 / 3) gives us: // P(x) ~ x_hi - x_hi^3/3 + x_lo * (1 - x_hi^2) -LIBC_INLINE static constexpr FloatFloat atan_eval(const FloatFloat &x) { +LIBC_INLINE constexpr FloatFloat atan_eval(const FloatFloat &x) { FloatFloat p; p.hi = x.hi; float x_hi_sq = x.hi * x.hi; @@ -124,7 +124,7 @@ LIBC_INLINE static constexpr FloatFloat atan_eval(const FloatFloat &x) { // > dirtyinfnorm(atan(x) - P, [-2^-5, 2^-5]); // 0x1.995...p-28. -LIBC_INLINE static constexpr float atan2f(float y, float x) { +LIBC_INLINE constexpr float atan2f(float y, float x) { using namespace atan2f_internal; using FPBits = typename fputil::FPBits; constexpr float IS_NEG[2] = {1.0f, -1.0f}; diff --git a/libc/src/__support/math/atan_utils.h b/libc/src/__support/math/atan_utils.h index 9e8d7d6569c8f..e752af3568373 100644 --- a/libc/src/__support/math/atan_utils.h +++ b/libc/src/__support/math/atan_utils.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIBC_SRC_MATH_GENERIC_ATAN_UTILS_H -#define LLVM_LIBC_SRC_MATH_GENERIC_ATAN_UTILS_H +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_ATAN_UTILS_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_ATAN_UTILS_H #include "src/__support/FPUtil/PolyEval.h" #include "src/__support/FPUtil/double_double.h" @@ -29,7 +29,7 @@ using Float128 = fputil::DyadicFloat<128>; // b = round(atan(i/64) - a, D, RN); // print("{", b, ",", a, "},"); // }; -static constexpr DoubleDouble ATAN_I[65] = { +LIBC_INLINE_VAR constexpr DoubleDouble ATAN_I[65] = { {0.0, 0.0}, {-0x1.220c39d4dff5p-61, 0x1.fff555bbb729bp-7}, {-0x1.5ec431444912cp-60, 0x1.ffd55bba97625p-6}, @@ -110,8 +110,7 @@ static constexpr DoubleDouble ATAN_I[65] = { // + x_lo * (1 - x_hi^2 + x_hi^4) // Since p.lo is ~ x^3/3, the relative error from rounding is bounded by: // |(atan(x) - P(x))/atan(x)| < ulp(x^2) <= 2^(-14-52) = 2^-66. -[[maybe_unused]] LIBC_INLINE static DoubleDouble -atan_eval(const DoubleDouble &x) { +[[maybe_unused]] LIBC_INLINE DoubleDouble atan_eval(const DoubleDouble &x) { DoubleDouble p; p.hi = x.hi; double x_hi_sq = x.hi * x.hi; @@ -143,7 +142,7 @@ atan_eval(const DoubleDouble &x) { // b = 2^ll + a; // print("{Sign::POS, ", 2^(ll - 128), ",", b, "},"); // }; -static constexpr Float128 ATAN_I_F128[65] = { +LIBC_INLINE_VAR constexpr Float128 ATAN_I_F128[65] = { {Sign::POS, 0, 0_u128}, {Sign::POS, -134, 0xfffaaadd'db94d5bb'e78c5640'15f76048_u128}, {Sign::POS, -133, 0xffeaaddd'4bb12542'779d776d'da8c6214_u128}, @@ -216,7 +215,7 @@ static constexpr Float128 ATAN_I_F128[65] = { // [0, 2^-7]); // > dirtyinfnorm(atan(x) - P, [0, 2^-7]); // 0x1.26016ad97f323875760f869684c0898d7b7bb8bep-122 -static constexpr Float128 ATAN_POLY_F128[] = { +LIBC_INLINE_VAR constexpr Float128 ATAN_POLY_F128[] = { {Sign::NEG, -129, 0xaaaaaaaa'aaaaaaaa'aaaaaaa6'003c5d1d_u128}, {Sign::POS, -130, 0xcccccccc'cccccccc'cca00232'8776b063_u128}, {Sign::NEG, -130, 0x92492492'49249201'27f5268a'cb24aec0_u128}, @@ -226,8 +225,7 @@ static constexpr Float128 ATAN_POLY_F128[] = { }; // Approximate atan for |x| <= 2^-7. -[[maybe_unused]] LIBC_INLINE static constexpr Float128 -atan_eval(const Float128 &x) { +[[maybe_unused]] LIBC_INLINE constexpr Float128 atan_eval(const Float128 &x) { Float128 x_sq = fputil::quick_mul(x, x); Float128 x3 = fputil::quick_mul(x, x_sq); Float128 p = fputil::polyeval(x_sq, ATAN_POLY_F128[0], ATAN_POLY_F128[1], @@ -240,4 +238,4 @@ atan_eval(const Float128 &x) { } // namespace LIBC_NAMESPACE_DECL -#endif // LLVM_LIBC_SRC_MATH_GENERIC_ATAN_UTILS_H +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_ATAN_UTILS_H diff --git a/libc/src/__support/math/atanf.h b/libc/src/__support/math/atanf.h index a16e386d58106..633a95b02d5ff 100644 --- a/libc/src/__support/math/atanf.h +++ b/libc/src/__support/math/atanf.h @@ -30,7 +30,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float atanf(float x) { +LIBC_INLINE constexpr float atanf(float x) { using namespace inv_trigf_utils_internal; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/atanf16.h b/libc/src/__support/math/atanf16.h index f75d145f36852..01eb8770591eb 100644 --- a/libc/src/__support/math/atanf16.h +++ b/libc/src/__support/math/atanf16.h @@ -26,7 +26,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 atanf16(float16 x) { +LIBC_INLINE constexpr float16 atanf16(float16 x) { // Generated by Solly using the following command: // > round(pi/2, SG, RN); constexpr float PI_2 = 0x1.921fb6p0; diff --git a/libc/src/__support/math/atanf_float.h b/libc/src/__support/math/atanf_float.h index 8794cec54f7a5..56db2ad2955e6 100644 --- a/libc/src/__support/math/atanf_float.h +++ b/libc/src/__support/math/atanf_float.h @@ -30,7 +30,7 @@ using fputil::FloatFloat; // b = round(atan(i/16) - a, SG, RN); // print("{", b, ",", a, "},"); // }; -static constexpr FloatFloat ATAN_I[17] = { +LIBC_INLINE_VAR constexpr FloatFloat ATAN_I[17] = { {0.0f, 0.0f}, {-0x1.1a6042p-30f, 0x1.ff55bcp-5f}, {-0x1.54f424p-30f, 0x1.fd5baap-4f}, @@ -55,7 +55,7 @@ static constexpr FloatFloat ATAN_I[17] = { // a = round(1 / (1 + (i/16)^2), SG, RN); // print(a, ","); // }; -static constexpr float ATANF_REDUCED_ARG[17] = { +LIBC_INLINE_VAR constexpr float ATANF_REDUCED_ARG[17] = { 0x1.0p0f, 0x1.fe01fep-1f, 0x1.f81f82p-1f, 0x1.ee9c8p-1f, 0x1.e1e1e2p-1f, 0x1.d272cap-1f, 0x1.c0e07p-1f, 0x1.adbe88p-1f, 0x1.99999ap-1f, 0x1.84f00cp-1f, 0x1.702e06p-1f, 0x1.5babccp-1f, @@ -66,7 +66,7 @@ static constexpr float ATANF_REDUCED_ARG[17] = { // Approximating atan( u / (1 + u * k/16) ) // atan( u / (1 + u * k/16) ) / u ~ 1 - k/16 * u + (k^2/256 - 1/3) * u^2 + // + (k/16 - (k/16)^3) * u^3 + O(u^4) -LIBC_INLINE static float atanf_eval(float u, float k_over_16) { +LIBC_INLINE float atanf_eval(float u, float k_over_16) { // (k/16)^2 float c2 = k_over_16 * k_over_16; // -(k/16)^3 @@ -85,7 +85,7 @@ LIBC_INLINE static float atanf_eval(float u, float k_over_16) { // There are several range reduction steps we can take for atan2(y, x) as // follow: -LIBC_INLINE static float atanf(float x) { +LIBC_INLINE float atanf(float x) { using namespace atanf_internal; using FPBits = typename fputil::FPBits; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/atanhf.h b/libc/src/__support/math/atanhf.h index b3ee5bbb4d408..607bc51e73709 100644 --- a/libc/src/__support/math/atanhf.h +++ b/libc/src/__support/math/atanhf.h @@ -19,7 +19,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float atanhf(float x) { +LIBC_INLINE constexpr float atanhf(float x) { using namespace acoshf_internal; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/atanhf16.h b/libc/src/__support/math/atanhf16.h index 80929dd30fa34..0787e126b2691 100644 --- a/libc/src/__support/math/atanhf16.h +++ b/libc/src/__support/math/atanhf16.h @@ -33,7 +33,7 @@ namespace atanhf16_internal { // Generated by Sollya with the following commands: // display = hexadecimal; // for n from 0 to 127 do { print(single(1 / (1 + n / 128.0))); }; -static constexpr float ONE_OVER_F_FLOAT[128] = { +LIBC_INLINE_VAR constexpr float ONE_OVER_F_FLOAT[128] = { 0x1p0f, 0x1.fc07fp-1f, 0x1.f81f82p-1f, 0x1.f4465ap-1f, 0x1.f07c2p-1f, 0x1.ecc07cp-1f, 0x1.e9131ap-1f, 0x1.e573acp-1f, 0x1.e1e1e2p-1f, 0x1.de5d6ep-1f, 0x1.dae608p-1f, 0x1.d77b66p-1f, @@ -72,7 +72,7 @@ static constexpr float ONE_OVER_F_FLOAT[128] = { // Generated by Sollya with the following commands: // display = hexadecimal; // for n from 0 to 127 do { print(single(log(1 + n / 128.0))); }; -static constexpr float LOG_F_FLOAT[128] = { +LIBC_INLINE_VAR constexpr float LOG_F_FLOAT[128] = { 0.0f, 0x1.fe02a6p-8f, 0x1.fc0a8cp-7f, 0x1.7b91bp-6f, 0x1.f829bp-6f, 0x1.39e87cp-5f, 0x1.77459p-5f, 0x1.b42dd8p-5f, 0x1.f0a30cp-5f, 0x1.16536ep-4f, 0x1.341d7ap-4f, 0x1.51b074p-4f, @@ -109,7 +109,7 @@ static constexpr float LOG_F_FLOAT[128] = { // x should be positive, normal finite value // TODO: Simplify range reduction and polynomial degree for float16. // See issue #137190. -LIBC_INLINE static float log_eval_f(float x) { +LIBC_INLINE float log_eval_f(float x) { // For x = 2^ex * (1 + mx), logf(x) = ex * logf(2) + logf(1 + mx). using FPBits = fputil::FPBits; FPBits xbits(x); @@ -151,7 +151,7 @@ LIBC_INLINE static float log_eval_f(float x) { } // namespace atanhf16_internal -LIBC_INLINE static constexpr float16 atanhf16(float16 x) { +LIBC_INLINE constexpr float16 atanhf16(float16 x) { constexpr size_t N_EXCEPTS = 1; constexpr fputil::ExceptValues ATANHF16_EXCEPTS{{ // (input, RZ output, RU offset, RD offset, RN offset) diff --git a/libc/src/__support/math/cbrt.h b/libc/src/__support/math/cbrt.h index 38df9fbfd6579..a781ed36238b8 100644 --- a/libc/src/__support/math/cbrt.h +++ b/libc/src/__support/math/cbrt.h @@ -35,7 +35,7 @@ using namespace fputil; // > P = fpminimax(x^(-2/3), 7, [|D...|], [1, 2]); // > dirtyinfnorm(P/x^(-2/3) - 1, [1, 2]); // 0x1.28...p-21 -LIBC_INLINE static double initial_approximation(double x) { +LIBC_INLINE double initial_approximation(double x) { constexpr double COEFFS[8] = { 0x1.bc52aedead5c6p1, -0x1.b52bfebf110b3p2, 0x1.1d8d71d53d126p3, -0x1.de2db9e81cf87p2, 0x1.0154ca06153bdp2, -0x1.5973c66ee6da7p0, @@ -59,14 +59,14 @@ LIBC_INLINE static double initial_approximation(double x) { // Get the error term for Newton iteration: // h(x) = x^3 * a^2 - 1, #ifdef LIBC_TARGET_CPU_HAS_FMA_DOUBLE -LIBC_INLINE static double get_error(const DoubleDouble &x_3, - const DoubleDouble &a_sq) { +LIBC_INLINE double get_error(const DoubleDouble &x_3, + const DoubleDouble &a_sq) { return fputil::multiply_add(x_3.hi, a_sq.hi, -1.0) + fputil::multiply_add(x_3.lo, a_sq.hi, x_3.hi * a_sq.lo); } #else -LIBC_INLINE static constexpr double get_error(const DoubleDouble &x_3, - const DoubleDouble &a_sq) { +LIBC_INLINE constexpr double get_error(const DoubleDouble &x_3, + const DoubleDouble &a_sq) { DoubleDouble x_3_a_sq = fputil::quick_mult(a_sq, x_3); return (x_3_a_sq.hi - 1.0) + x_3_a_sq.lo; } @@ -144,7 +144,7 @@ LIBC_INLINE static constexpr double get_error(const DoubleDouble &x_3, // exceptional handling, similar to what was done in the CORE-MATH project: // https://gitlab.inria.fr/core-math/core-math/-/blob/master/src/binary64/cbrt/cbrt.c -LIBC_INLINE static constexpr double cbrt(double x) { +LIBC_INLINE constexpr double cbrt(double x) { using DoubleDouble = fputil::DoubleDouble; using namespace cbrt_internal; using FPBits = fputil::FPBits; diff --git a/libc/src/__support/math/cbrtf.h b/libc/src/__support/math/cbrtf.h index d7ff1cd61af1d..35e60562a39c0 100644 --- a/libc/src/__support/math/cbrtf.h +++ b/libc/src/__support/math/cbrtf.h @@ -19,7 +19,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float cbrtf(float x) { +LIBC_INLINE constexpr float cbrtf(float x) { // Look up table for 2^(i/3) for i = 0, 1, 2. constexpr double CBRT2[3] = {1.0, 0x1.428a2f98d728bp0, 0x1.965fea53d6e3dp0}; diff --git a/libc/src/__support/math/common_constants.h b/libc/src/__support/math/common_constants.h index 53abbfeef3412..4548cd506bb99 100644 --- a/libc/src/__support/math/common_constants.h +++ b/libc/src/__support/math/common_constants.h @@ -19,15 +19,15 @@ namespace common_constants_internal { // log(2) generated by Sollya with: // > a = 2^-43 * nearestint(2^43*log(2)); // LSB = 2^-43 is chosen so that e_x * LOG_2_HI is exact for -1075 < e_x < 1024. -static constexpr double LOG_2_HI = 0x1.62e42fefa38p-1; // LSB = 2^-43 +LIBC_INLINE_VAR constexpr double LOG_2_HI = 0x1.62e42fefa38p-1; // LSB = 2^-43 // > b = round(log10(2) - a, D, RN); -static constexpr double LOG_2_LO = 0x1.ef35793c7673p-45; // LSB = 2^-97 +LIBC_INLINE_VAR constexpr double LOG_2_LO = 0x1.ef35793c7673p-45; // LSB = 2^-97 // Minimax polynomial for (log(1 + x) - x)/x^2, generated by sollya with: // > P = fpminimax((log(1 + x) - x)/x^2, 5, [|D...|], [-2^-8, 2^-7]); -constexpr double LOG_COEFFS[6] = {-0x1.fffffffffffffp-2, 0x1.5555555554a9bp-2, - -0x1.0000000094567p-2, 0x1.99999dcc9823cp-3, - -0x1.55550ac2e537ap-3, 0x1.21a02c4e624d7p-3}; +LIBC_INLINE_VAR constexpr double LOG_COEFFS[6] = { + -0x1.fffffffffffffp-2, 0x1.5555555554a9bp-2, -0x1.0000000094567p-2, + 0x1.99999dcc9823cp-3, -0x1.55550ac2e537ap-3, 0x1.21a02c4e624d7p-3}; // Range reduction constants for logarithms. // r(0) = 1, r(127) = 0.5 @@ -36,7 +36,7 @@ constexpr double LOG_COEFFS[6] = {-0x1.fffffffffffffp-2, 0x1.5555555554a9bp-2, // precision, and -2^-8 <= v < 2^-7. // TODO(lntue): Add reference to how the constants are derived after the // resulting paper is ready. -alignas(8) static constexpr float R[128] = { +alignas(8) LIBC_INLINE_VAR constexpr float R[128] = { 0x1p0, 0x1.fcp-1, 0x1.f8p-1, 0x1.f4p-1, 0x1.fp-1, 0x1.ecp-1, 0x1.e8p-1, 0x1.e4p-1, 0x1.ep-1, 0x1.dep-1, 0x1.dap-1, 0x1.d6p-1, 0x1.d4p-1, 0x1.dp-1, 0x1.ccp-1, 0x1.cap-1, 0x1.c6p-1, 0x1.c4p-1, 0x1.cp-1, 0x1.bep-1, 0x1.bap-1, @@ -57,7 +57,7 @@ alignas(8) static constexpr float R[128] = { 0x1.0ap-1, 0x1.08p-1, 0x1.08p-1, 0x1.06p-1, 0x1.06p-1, 0x1.04p-1, 0x1.04p-1, 0x1.02p-1, 0x1.0p-1}; -static constexpr double RD[128] = { +LIBC_INLINE_VAR constexpr double RD[128] = { 0x1p0, 0x1.fcp-1, 0x1.f8p-1, 0x1.f4p-1, 0x1.fp-1, 0x1.ecp-1, 0x1.e8p-1, 0x1.e4p-1, 0x1.ep-1, 0x1.dep-1, 0x1.dap-1, 0x1.d6p-1, 0x1.d4p-1, 0x1.dp-1, 0x1.ccp-1, 0x1.cap-1, 0x1.c6p-1, 0x1.c4p-1, 0x1.cp-1, 0x1.bep-1, 0x1.bap-1, @@ -82,7 +82,7 @@ static constexpr double RD[128] = { // available. // Generated by Sollya with the formula: CD[i] = RD[i]*(1 + i*2^-7) - 1 // for RD[i] defined on the table above. -static constexpr double CD[128] = { +LIBC_INLINE_VAR constexpr double CD[128] = { 0.0, -0x1p-14, -0x1p-12, -0x1.2p-11, -0x1p-10, -0x1.9p-10, -0x1.2p-9, -0x1.88p-9, -0x1p-8, -0x1.9p-11, -0x1.fp-10, -0x1.9cp-9, -0x1p-12, -0x1.cp-10, -0x1.bp-9, -0x1.5p-11, -0x1.4p-9, 0x1p-14, @@ -107,7 +107,7 @@ static constexpr double CD[128] = { -0x1p-14, -0x1p-8, }; -static constexpr double LOG_R[128] = { +LIBC_INLINE_VAR constexpr double LOG_R[128] = { 0x0.0000000000000p0, 0x1.010157588de71p-7, 0x1.0205658935847p-6, 0x1.8492528c8cabfp-6, 0x1.0415d89e74444p-5, 0x1.466aed42de3eap-5, 0x1.894aa149fb343p-5, 0x1.ccb73cdddb2ccp-5, 0x1.08598b59e3a07p-4, @@ -152,7 +152,7 @@ static constexpr double LOG_R[128] = { 0x1.5707a26bb8c66p-1, 0x1.5af405c3649ep-1, 0x1.5af405c3649ep-1, 0x1.5ee82aa24192p-1, 0x0.000000000000p0}; -static constexpr double LOG2_R[128] = { +LIBC_INLINE_VAR constexpr double LOG2_R[128] = { 0x0.0000000000000p+0, 0x1.72c7ba20f7327p-7, 0x1.743ee861f3556p-6, 0x1.184b8e4c56af8p-5, 0x1.77394c9d958d5p-5, 0x1.d6ebd1f1febfep-5, 0x1.1bb32a600549dp-4, 0x1.4c560fe68af88p-4, 0x1.7d60496cfbb4cp-4, @@ -205,7 +205,7 @@ static constexpr double LOG2_R[128] = { // print("{", -c, ",", -b, "},"); // }; // We replace LOG_R[0] with log10(1.0) == 0.0 -alignas(16) static constexpr NumberPair LOG_R_DD[128] = { +alignas(16) LIBC_INLINE_VAR constexpr NumberPair LOG_R_DD[128] = { {0.0, 0.0}, {-0x1.0c76b999d2be8p-46, 0x1.010157589p-7}, {-0x1.3dc5b06e2f7d2p-45, 0x1.0205658938p-6}, @@ -341,7 +341,7 @@ alignas(16) static constexpr NumberPair LOG_R_DD[128] = { // Output range: // [-0x1.3ffcp-15, 0x1.3e3dp-15] // We store S2[i] = 2^16 (r(i - 2^6) - 1). -alignas(8) static constexpr int S2[193] = { +alignas(8) LIBC_INLINE_VAR constexpr int S2[193] = { 0x101, 0xfd, 0xf9, 0xf5, 0xf1, 0xed, 0xe9, 0xe5, 0xe1, 0xdd, 0xd9, 0xd5, 0xd1, 0xcd, 0xc9, 0xc5, 0xc1, 0xbd, 0xb9, 0xb4, 0xb0, 0xac, 0xa8, 0xa4, 0xa0, 0x9c, 0x98, @@ -365,7 +365,7 @@ alignas(8) static constexpr int S2[193] = { -0x1cd, -0x1d1, -0x1d5, -0x1d9, -0x1dd, -0x1e0, -0x1e4, -0x1e8, -0x1ec, -0x1f0, -0x1f4, -0x1f8, -0x1fc}; -static constexpr double R2[193] = { +LIBC_INLINE_VAR constexpr double R2[193] = { 0x1.0101p0, 0x1.00fdp0, 0x1.00f9p0, 0x1.00f5p0, 0x1.00f1p0, 0x1.00edp0, 0x1.00e9p0, 0x1.00e5p0, 0x1.00e1p0, 0x1.00ddp0, 0x1.00d9p0, 0x1.00d5p0, 0x1.00d1p0, 0x1.00cdp0, 0x1.00c9p0, @@ -412,7 +412,7 @@ static constexpr double R2[193] = { // Output range: // [-0x1.01928p-22 , 0x1p-22] // We store S[i] = 2^21 (r(i - 80) - 1). -alignas(8) static constexpr int S3[161] = { +alignas(8) LIBC_INLINE_VAR constexpr int S3[161] = { 0x50, 0x4f, 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, @@ -435,7 +435,7 @@ alignas(8) static constexpr int S3[161] = { // Output range: // [-0x1.0002143p-29 , 0x1p-29] // We store S[i] = 2^28 (r(i - 65) - 1). -alignas(8) static constexpr int S4[130] = { +alignas(8) LIBC_INLINE_VAR constexpr int S4[130] = { 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, @@ -456,7 +456,7 @@ alignas(8) static constexpr int S4[130] = { // Table is generated with Sollya as follow: // > display = hexadecimal; // > for i from -104 to 89 do { D(exp(i)); }; -static constexpr double EXP_M1[195] = { +LIBC_INLINE_VAR constexpr double EXP_M1[195] = { 0x1.f1e6b68529e33p-151, 0x1.525be4e4e601dp-149, 0x1.cbe0a45f75eb1p-148, 0x1.3884e838aea68p-146, 0x1.a8c1f14e2af5dp-145, 0x1.20a717e64a9bdp-143, 0x1.8851d84118908p-142, 0x1.0a9bdfb02d240p-140, 0x1.6a5bea046b42ep-139, @@ -528,7 +528,7 @@ static constexpr double EXP_M1[195] = { // Table is generated with Sollya as follow: // > display = hexadecimal; // > for i from 0 to 127 do { D(exp(i / 128)); }; -static constexpr double EXP_M2[128] = { +LIBC_INLINE_VAR constexpr double EXP_M2[128] = { 0x1.0000000000000p0, 0x1.0202015600446p0, 0x1.04080ab55de39p0, 0x1.06122436410ddp0, 0x1.08205601127edp0, 0x1.0a32a84e9c1f6p0, 0x1.0c49236829e8cp0, 0x1.0e63cfa7ab09dp0, 0x1.1082b577d34edp0, diff --git a/libc/src/__support/math/cos.h b/libc/src/__support/math/cos.h index cd4abc2864324..1a7833978304a 100644 --- a/libc/src/__support/math/cos.h +++ b/libc/src/__support/math/cos.h @@ -30,7 +30,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr double cos(double x) { +LIBC_INLINE constexpr double cos(double x) { using namespace range_reduction_double_internal; using DoubleDouble = fputil::DoubleDouble; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/cosf.h b/libc/src/__support/math/cosf.h index e635d30819719..4893a436e331e 100644 --- a/libc/src/__support/math/cosf.h +++ b/libc/src/__support/math/cosf.h @@ -26,7 +26,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float cosf(float x) { +LIBC_INLINE constexpr float cosf(float x) { return sincosf_float_eval::sincosf_eval(x); } @@ -41,7 +41,8 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float cosf(float x) { +LIBC_INLINE constexpr float cosf(float x) { + using namespace sincosf_utils_internal; #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS // Exceptional cases for cosf. diff --git a/libc/src/__support/math/cosf16.h b/libc/src/__support/math/cosf16.h index 50c9a8f765c2a..f7485a074ac63 100644 --- a/libc/src/__support/math/cosf16.h +++ b/libc/src/__support/math/cosf16.h @@ -25,7 +25,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 cosf16(float16 x) { +LIBC_INLINE constexpr float16 cosf16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr size_t N_EXCEPTS = 4; diff --git a/libc/src/__support/math/coshf.h b/libc/src/__support/math/coshf.h index 0f233b87c5e2c..aa0988f9711f1 100644 --- a/libc/src/__support/math/coshf.h +++ b/libc/src/__support/math/coshf.h @@ -20,7 +20,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float coshf(float x) { +LIBC_INLINE constexpr float coshf(float x) { using namespace sinhfcoshf_internal; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/coshf16.h b/libc/src/__support/math/coshf16.h index 4c96a78fa5254..dc39944d89f85 100644 --- a/libc/src/__support/math/coshf16.h +++ b/libc/src/__support/math/coshf16.h @@ -25,7 +25,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 coshf16(float16 x) { +LIBC_INLINE constexpr float16 coshf16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr fputil::ExceptValues COSHF16_EXCEPTS_POS = {{ diff --git a/libc/src/__support/math/cospif.h b/libc/src/__support/math/cospif.h index e921090459769..08c9f9e7b14b9 100644 --- a/libc/src/__support/math/cospif.h +++ b/libc/src/__support/math/cospif.h @@ -22,7 +22,8 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float cospif(float x) { +LIBC_INLINE constexpr float cospif(float x) { + using namespace sincosf_utils_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/cospif16.h b/libc/src/__support/math/cospif16.h index d07236cccac75..c763c27db102c 100644 --- a/libc/src/__support/math/cospif16.h +++ b/libc/src/__support/math/cospif16.h @@ -24,7 +24,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 cospif16(float16 x) { +LIBC_INLINE constexpr float16 cospif16(float16 x) { using namespace sincosf16_internal; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/dfmaf128.h b/libc/src/__support/math/dfmaf128.h index 0a266d4aacb98..54c8761af85f8 100644 --- a/libc/src/__support/math/dfmaf128.h +++ b/libc/src/__support/math/dfmaf128.h @@ -20,7 +20,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static double dfmaf128(float128 x, float128 y, float128 z) { +LIBC_INLINE double dfmaf128(float128 x, float128 y, float128 z) { return fputil::fma(x, y, z); } diff --git a/libc/src/__support/math/dfmal.h b/libc/src/__support/math/dfmal.h index ffe94bc4abcc6..0331d59a2c962 100644 --- a/libc/src/__support/math/dfmal.h +++ b/libc/src/__support/math/dfmal.h @@ -16,7 +16,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static double dfmal(long double x, long double y, long double z) { +LIBC_INLINE double dfmal(long double x, long double y, long double z) { return fputil::fma(x, y, z); } diff --git a/libc/src/__support/math/dsqrtl.h b/libc/src/__support/math/dsqrtl.h index e66b6502d27c4..14decf8c6ed77 100644 --- a/libc/src/__support/math/dsqrtl.h +++ b/libc/src/__support/math/dsqrtl.h @@ -15,7 +15,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr double dsqrtl(long double x) { +LIBC_INLINE constexpr double dsqrtl(long double x) { return fputil::sqrt(x); } diff --git a/libc/src/__support/math/erff.h b/libc/src/__support/math/erff.h index b81be30f7b8f9..a40b927c60a26 100644 --- a/libc/src/__support/math/erff.h +++ b/libc/src/__support/math/erff.h @@ -19,7 +19,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float erff(float x) { +LIBC_INLINE constexpr float erff(float x) { // Polynomials approximating erf(x)/x on ( k/8, (k + 1)/8 ) generated by // Sollya with: > P = fpminimax(erf(x)/x, [|0, 2, 4, 6, 8, 10, 12, 14|], diff --git a/libc/src/__support/math/exp.h b/libc/src/__support/math/exp.h index 83638e85c400a..8444a59bdf999 100644 --- a/libc/src/__support/math/exp.h +++ b/libc/src/__support/math/exp.h @@ -29,6 +29,10 @@ namespace LIBC_NAMESPACE_DECL { +namespace math { + +namespace exp_internal { + using fputil::DoubleDouble; using fputil::TripleDouble; using Float128 = typename fputil::DyadicFloat<128>; @@ -36,15 +40,15 @@ using Float128 = typename fputil::DyadicFloat<128>; using LIBC_NAMESPACE::operator""_u128; // log2(e) -static constexpr double LOG2_E = 0x1.71547652b82fep+0; +LIBC_INLINE_VAR constexpr double LOG2_E = 0x1.71547652b82fep+0; // Error bounds: // Errors when using double precision. -static constexpr double EXP_ERR_D = 0x1.8p-63; +LIBC_INLINE_VAR constexpr double EXP_ERR_D = 0x1.8p-63; #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS // Errors when using double-double precision. -static constexpr double EXP_ERR_DD = 0x1.0p-99; +LIBC_INLINE_VAR constexpr double EXP_ERR_DD = 0x1.0p-99; #endif // LIBC_MATH_HAS_SKIP_ACCURATE_PASS // -2^-12 * log(2) @@ -53,21 +57,19 @@ static constexpr double EXP_ERR_DD = 0x1.0p-99; // > c = round(a - b, 30, RN); // > d = round(a - b - c, D, RN); // Errors < 1.5 * 2^-133 -static constexpr double MLOG_2_EXP2_M12_HI = -0x1.62e42ffp-13; -static constexpr double MLOG_2_EXP2_M12_MID = 0x1.718432a1b0e26p-47; +LIBC_INLINE_VAR constexpr double MLOG_2_EXP2_M12_HI = -0x1.62e42ffp-13; +LIBC_INLINE_VAR constexpr double MLOG_2_EXP2_M12_MID = 0x1.718432a1b0e26p-47; #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS -static constexpr double MLOG_2_EXP2_M12_MID_30 = 0x1.718432ap-47; -static constexpr double MLOG_2_EXP2_M12_LO = 0x1.b0e2633fe0685p-79; +LIBC_INLINE_VAR constexpr double MLOG_2_EXP2_M12_MID_30 = 0x1.718432ap-47; +LIBC_INLINE_VAR constexpr double MLOG_2_EXP2_M12_LO = 0x1.b0e2633fe0685p-79; #endif // LIBC_MATH_HAS_SKIP_ACCURATE_PASS -namespace { - // Polynomial approximations with double precision: // Return expm1(dx) / x ~ 1 + dx / 2 + dx^2 / 6 + dx^3 / 24. // For |dx| < 2^-13 + 2^-30: // | output - expm1(dx) / dx | < 2^-51. -LIBC_INLINE static double poly_approx_d(double dx) { +LIBC_INLINE double poly_approx_d(double dx) { // dx^2 double dx2 = dx * dx; // c0 = 1 + dx / 2 @@ -85,7 +87,7 @@ LIBC_INLINE static double poly_approx_d(double dx) { // Return exp(dx) ~ 1 + dx + dx^2 / 2 + ... + dx^6 / 720 // For |dx| < 2^-13 + 2^-30: // | output - exp(dx) | < 2^-101 -LIBC_INLINE static DoubleDouble poly_approx_dd(const DoubleDouble &dx) { +LIBC_INLINE DoubleDouble poly_approx_dd(const DoubleDouble &dx) { // Taylor polynomial. constexpr DoubleDouble COEFFS[] = { {0, 0x1p0}, // 1 @@ -106,7 +108,7 @@ LIBC_INLINE static DoubleDouble poly_approx_dd(const DoubleDouble &dx) { // Return exp(dx) ~ 1 + dx + dx^2 / 2 + ... + dx^7 / 5040 // For |dx| < 2^-13 + 2^-30: // | output - exp(dx) | < 2^-126. -LIBC_INLINE static Float128 poly_approx_f128(const Float128 &dx) { +LIBC_INLINE Float128 poly_approx_f128(const Float128 &dx) { constexpr Float128 COEFFS_128[]{ {Sign::POS, -127, 0x80000000'00000000'00000000'00000000_u128}, // 1.0 {Sign::POS, -127, 0x80000000'00000000'00000000'00000000_u128}, // 1.0 @@ -127,7 +129,7 @@ LIBC_INLINE static Float128 poly_approx_f128(const Float128 &dx) { // Compute exp(x) using 128-bit precision. // TODO(lntue): investigate triple-double precision implementation for this // step. -LIBC_INLINE static Float128 exp_f128(double x, double kd, int idx1, int idx2) { +LIBC_INLINE Float128 exp_f128(double x, double kd, int idx1, int idx2) { // Recalculate dx: double t1 = fputil::multiply_add(kd, MLOG_2_EXP2_M12_HI, x); // exact @@ -160,8 +162,8 @@ LIBC_INLINE static Float128 exp_f128(double x, double kd, int idx1, int idx2) { } // Compute exp(x) with double-double precision. -LIBC_INLINE static DoubleDouble exp_double_double(double x, double kd, - const DoubleDouble &exp_mid) { +LIBC_INLINE DoubleDouble exp_double_double(double x, double kd, + const DoubleDouble &exp_mid) { // Recalculate dx: // dx = x - k * 2^-12 * log(2) double t1 = fputil::multiply_add(kd, MLOG_2_EXP2_M12_HI, x); // exact @@ -184,7 +186,7 @@ LIBC_INLINE static DoubleDouble exp_double_double(double x, double kd, // Check for exceptional cases when // |x| <= 2^-53 or x < log(2^-1075) or x >= 0x1.6232bdd7abcd3p+9 -LIBC_INLINE static double set_exceptional(double x) { +LIBC_INLINE double set_exceptional(double x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); @@ -230,11 +232,10 @@ LIBC_INLINE static double set_exceptional(double x) { return x + FPBits::inf().get_val(); } -} // namespace - -namespace math { +} // namespace exp_internal -LIBC_INLINE static double exp(double x) { +LIBC_INLINE double exp(double x) { + using namespace exp_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/exp10.h b/libc/src/__support/math/exp10.h index 12a09d7492457..4a761b01ae13e 100644 --- a/libc/src/__support/math/exp10.h +++ b/libc/src/__support/math/exp10.h @@ -36,7 +36,7 @@ using Float128 = typename fputil::DyadicFloat<128>; using LIBC_NAMESPACE::operator""_u128; // log2(10) -static constexpr double LOG2_10 = 0x1.a934f0979a371p+1; +LIBC_INLINE_VAR constexpr double LOG2_10 = 0x1.a934f0979a371p+1; // -2^-12 * log10(2) // > a = -2^-12 * log10(2); @@ -44,21 +44,21 @@ static constexpr double LOG2_10 = 0x1.a934f0979a371p+1; // > c = round(a - b, 32, RN); // > d = round(a - b - c, D, RN); // Errors < 1.5 * 2^-144 -static constexpr double MLOG10_2_EXP2_M12_HI = -0x1.3441350ap-14; -static constexpr double MLOG10_2_EXP2_M12_MID = 0x1.0c0219dc1da99p-51; +LIBC_INLINE_VAR constexpr double MLOG10_2_EXP2_M12_HI = -0x1.3441350ap-14; +LIBC_INLINE_VAR constexpr double MLOG10_2_EXP2_M12_MID = 0x1.0c0219dc1da99p-51; #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS -static constexpr double MLOG10_2_EXP2_M12_MID_32 = 0x1.0c0219dcp-51; -static constexpr double MLOG10_2_EXP2_M12_LO = 0x1.da994fd20dba2p-87; +LIBC_INLINE_VAR constexpr double MLOG10_2_EXP2_M12_MID_32 = 0x1.0c0219dcp-51; +LIBC_INLINE_VAR constexpr double MLOG10_2_EXP2_M12_LO = 0x1.da994fd20dba2p-87; #endif // LIBC_MATH_HAS_SKIP_ACCURATE_PASS // Error bounds: // Errors when using double precision. -constexpr double EXP10_ERR_D = 0x1.8p-63; +LIBC_INLINE_VAR constexpr double EXP10_ERR_D = 0x1.8p-63; #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS // Errors when using double-double precision. -static constexpr double EXP10_ERR_DD = 0x1.8p-99; +LIBC_INLINE_VAR constexpr double EXP10_ERR_DD = 0x1.8p-99; #endif // LIBC_MATH_HAS_SKIP_ACCURATE_PASS // Polynomial approximations with double precision. Generated by Sollya with: @@ -66,7 +66,7 @@ static constexpr double EXP10_ERR_DD = 0x1.8p-99; // > P; // Error bounds: // | output - (10^dx - 1) / dx | < 2^-52. -LIBC_INLINE static double exp10_poly_approx_d(double dx) { +LIBC_INLINE double exp10_poly_approx_d(double dx) { // dx^2 double dx2 = dx * dx; double c0 = @@ -83,7 +83,7 @@ LIBC_INLINE static double exp10_poly_approx_d(double dx) { // > P = fpminimax((10^x - 1)/x, 5, [|DD...|], [-2^-14, 2^-14]); // Error bounds: // | output - 10^(dx) | < 2^-101 -LIBC_INLINE static constexpr DoubleDouble +LIBC_INLINE constexpr DoubleDouble exp10_poly_approx_dd(const DoubleDouble &dx) { // Taylor polynomial. constexpr DoubleDouble COEFFS[] = { @@ -106,8 +106,7 @@ exp10_poly_approx_dd(const DoubleDouble &dx) { // Return exp(dx) ~ 1 + a0 * dx + a1 * dx^2 + ... + a6 * dx^7 // For |dx| < 2^-14: // | output - 10^dx | < 1.5 * 2^-124. -LIBC_INLINE static constexpr Float128 -exp10_poly_approx_f128(const Float128 &dx) { +LIBC_INLINE constexpr Float128 exp10_poly_approx_f128(const Float128 &dx) { constexpr Float128 COEFFS_128[]{ {Sign::POS, -127, 0x80000000'00000000'00000000'00000000_u128}, // 1.0 {Sign::POS, -126, 0x935d8ddd'aaa8ac16'ea56d62b'82d30a2d_u128}, @@ -128,8 +127,7 @@ exp10_poly_approx_f128(const Float128 &dx) { // Compute 10^(x) using 128-bit precision. // TODO(lntue): investigate triple-double precision implementation for this // step. -LIBC_INLINE static Float128 exp10_f128(double x, double kd, int idx1, - int idx2) { +LIBC_INLINE Float128 exp10_f128(double x, double kd, int idx1, int idx2) { double t1 = fputil::multiply_add(kd, MLOG10_2_EXP2_M12_HI, x); // exact double t2 = kd * MLOG10_2_EXP2_M12_MID_32; // exact double t3 = kd * MLOG10_2_EXP2_M12_LO; // Error < 2^-144 @@ -160,8 +158,8 @@ LIBC_INLINE static Float128 exp10_f128(double x, double kd, int idx1, } // Compute 10^x with double-double precision. -LIBC_INLINE static DoubleDouble -exp10_double_double(double x, double kd, const DoubleDouble &exp_mid) { +LIBC_INLINE DoubleDouble exp10_double_double(double x, double kd, + const DoubleDouble &exp_mid) { // Recalculate dx: // dx = x - k * 2^-12 * log10(2) double t1 = fputil::multiply_add(kd, MLOG10_2_EXP2_M12_HI, x); // exact @@ -183,7 +181,7 @@ exp10_double_double(double x, double kd, const DoubleDouble &exp_mid) { #endif // LIBC_MATH_HAS_SKIP_ACCURATE_PASS // When output is denormal. -LIBC_INLINE static double exp10_denorm(double x) { +LIBC_INLINE double exp10_denorm(double x) { // Range reduction. double tmp = fputil::multiply_add(x, LOG2_10, 0x1.8000'0000'4p21); int k = static_cast(cpp::bit_cast(tmp) >> 19); @@ -237,7 +235,7 @@ LIBC_INLINE static double exp10_denorm(double x) { // * x >= log10(2^1024) // * x <= log10(2^-1022) // * x is inf or nan -LIBC_INLINE static constexpr double exp10_set_exceptional(double x) { +LIBC_INLINE constexpr double exp10_set_exceptional(double x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); @@ -288,7 +286,7 @@ LIBC_INLINE static constexpr double exp10_set_exceptional(double x) { namespace math { -LIBC_INLINE static constexpr double exp10(double x) { +LIBC_INLINE constexpr double exp10(double x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/exp10_float16_constants.h b/libc/src/__support/math/exp10_float16_constants.h index ef501857e25e5..cf8bb7f25b41c 100644 --- a/libc/src/__support/math/exp10_float16_constants.h +++ b/libc/src/__support/math/exp10_float16_constants.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { // Generated by Sollya with the following commands: // > display = hexadecimal; // > for i from 0 to 7 do printsingle(round(2^(i * 2^-3), SG, RN)); -static constexpr cpp::array EXP2_MID_BITS = { +LIBC_INLINE_VAR constexpr cpp::array EXP2_MID_BITS = { 0x3f80'0000U, 0x3f8b'95c2U, 0x3f98'37f0U, 0x3fa5'fed7U, 0x3fb5'04f3U, 0x3fc5'672aU, 0x3fd7'44fdU, 0x3fea'c0c7U, }; @@ -29,12 +29,12 @@ static constexpr cpp::array EXP2_MID_BITS = { // Generated by Sollya with the following commands: // > display = hexadecimal; // > round(log2(10), SG, RN); -static constexpr float LOG2F_10 = 0x1.a934fp+1f; +LIBC_INLINE_VAR constexpr float LOG2F_10 = 0x1.a934fp+1f; // Generated by Sollya with the following commands: // > display = hexadecimal; // > round(log10(2), SG, RN); -static constexpr float LOG10F_2 = 0x1.344136p-2f; +LIBC_INLINE_VAR constexpr float LOG10F_2 = 0x1.344136p-2f; } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/__support/math/exp10f.h b/libc/src/__support/math/exp10f.h index 76ae197d7fd24..31d3492d56a5e 100644 --- a/libc/src/__support/math/exp10f.h +++ b/libc/src/__support/math/exp10f.h @@ -20,7 +20,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float exp10f(float x) { +LIBC_INLINE constexpr float exp10f(float x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/exp10f16.h b/libc/src/__support/math/exp10f16.h index 3eca867376bf9..935a301544edf 100644 --- a/libc/src/__support/math/exp10f16.h +++ b/libc/src/__support/math/exp10f16.h @@ -29,12 +29,12 @@ namespace math { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS #ifdef LIBC_TARGET_CPU_HAS_FMA_FLOAT -static constexpr size_t N_EXP10F16_EXCEPTS = 5; +LIBC_INLINE_VAR constexpr size_t N_EXP10F16_EXCEPTS = 5; #else -static constexpr size_t N_EXP10F16_EXCEPTS = 8; +LIBC_INLINE_VAR constexpr size_t N_EXP10F16_EXCEPTS = 8; #endif -static constexpr fputil::ExceptValues +LIBC_INLINE_VAR constexpr fputil::ExceptValues EXP10F16_EXCEPTS = {{ // x = 0x1.8f4p-2, exp10f16(x) = 0x1.3ap+1 (RZ) {0x363dU, 0x40e8U, 1U, 0U, 1U}, @@ -57,7 +57,7 @@ static constexpr fputil::ExceptValues }}; #endif // !LIBC_MATH_HAS_SKIP_ACCURATE_PASS -LIBC_INLINE static constexpr float16 exp10f16(float16 x) { +LIBC_INLINE constexpr float16 exp10f16(float16 x) { using FPBits = fputil::FPBits; FPBits x_bits(x); diff --git a/libc/src/__support/math/exp10f16_utils.h b/libc/src/__support/math/exp10f16_utils.h index 5952a4160511d..a0fca6399a78f 100644 --- a/libc/src/__support/math/exp10f16_utils.h +++ b/libc/src/__support/math/exp10f16_utils.h @@ -19,7 +19,7 @@ namespace LIBC_NAMESPACE_DECL { -LIBC_INLINE static ExpRangeReduction exp10_range_reduction(float16 x) { +LIBC_INLINE ExpRangeReduction exp10_range_reduction(float16 x) { // For -8 < x < 5, to compute 10^x, we perform the following range reduction: // find hi, mid, lo, such that: // x = (hi + mid) * log2(10) + lo, in which diff --git a/libc/src/__support/math/exp10f_utils.h b/libc/src/__support/math/exp10f_utils.h index 010a2f1445be5..6134f3e6a8ab1 100644 --- a/libc/src/__support/math/exp10f_utils.h +++ b/libc/src/__support/math/exp10f_utils.h @@ -132,7 +132,7 @@ struct exp_b_reduc_t { // Return: // { 2^(hi + mid), lo } template -LIBC_INLINE static constexpr exp_b_reduc_t exp_b_range_reduc(float x) { +LIBC_INLINE constexpr exp_b_reduc_t exp_b_range_reduc(float x) { double xd = static_cast(x); // kd = round((hi + mid) * log2(b) * 2^MID_BITS) double kd = fputil::nearest_integer(Base::LOG2_B * xd); diff --git a/libc/src/__support/math/exp10m1f.h b/libc/src/__support/math/exp10m1f.h index 9fe4ff774ec68..3b05c2479b32e 100644 --- a/libc/src/__support/math/exp10m1f.h +++ b/libc/src/__support/math/exp10m1f.h @@ -28,10 +28,10 @@ namespace math { namespace exp10m1f_internal { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS -static constexpr size_t N_EXCEPTS_LO = 11; +LIBC_INLINE_VAR constexpr size_t N_EXCEPTS_LO = 11; -static constexpr fputil::ExceptValues EXP10M1F_EXCEPTS_LO = - {{ +LIBC_INLINE_VAR constexpr fputil::ExceptValues + EXP10M1F_EXCEPTS_LO = {{ // x = 0x1.0fe54ep-11, exp10m1f(x) = 0x1.3937eep-10 (RZ) {0x3a07'f2a7U, 0x3a9c'9bf7U, 1U, 0U, 1U}, // x = 0x1.80e6eap-11, exp10m1f(x) = 0x1.bb8272p-10 (RZ) @@ -56,10 +56,10 @@ static constexpr fputil::ExceptValues EXP10M1F_EXCEPTS_LO = {0xbb65'b4a6U, 0xbc03'b272U, 0U, 1U, 0U}, }}; -static constexpr size_t N_EXCEPTS_HI = 19; +LIBC_INLINE_VAR constexpr size_t N_EXCEPTS_HI = 19; -static constexpr fputil::ExceptValues EXP10M1F_EXCEPTS_HI = - {{ +LIBC_INLINE_VAR constexpr fputil::ExceptValues + EXP10M1F_EXCEPTS_HI = {{ // (input, RZ output, RU offset, RD offset, RN offset) // x = 0x1.8d31eep-8, exp10m1f(x) = 0x1.cc7e4cp-7 (RZ) {0x3bc6'98f7U, 0x3c66'3f26U, 1U, 0U, 1U}, @@ -104,7 +104,7 @@ static constexpr fputil::ExceptValues EXP10M1F_EXCEPTS_HI = } // namespace exp10m1f_internal -LIBC_INLINE static constexpr float exp10m1f(float x) { +LIBC_INLINE constexpr float exp10m1f(float x) { using namespace exp10m1f_internal; using FPBits = fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/exp10m1f16.h b/libc/src/__support/math/exp10m1f16.h index 6367a857fa98a..7ee43a0092476 100644 --- a/libc/src/__support/math/exp10m1f16.h +++ b/libc/src/__support/math/exp10m1f16.h @@ -30,7 +30,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 exp10m1f16(float16 x) { +LIBC_INLINE constexpr float16 exp10m1f16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr fputil::ExceptValues EXP10M1F16_EXCEPTS_LO = {{ diff --git a/libc/src/__support/math/exp2.h b/libc/src/__support/math/exp2.h index 7eaa465f93841..90c91c109874d 100644 --- a/libc/src/__support/math/exp2.h +++ b/libc/src/__support/math/exp2.h @@ -45,14 +45,14 @@ using LIBC_NAMESPACE::operator""_u128; // Error bounds: // Errors when using double precision. #ifdef LIBC_TARGET_CPU_HAS_FMA_DOUBLE -constexpr double ERR_D = 0x1.0p-63; +LIBC_INLINE_VAR constexpr double ERR_D = 0x1.0p-63; #else -constexpr double ERR_D = 0x1.8p-63; +LIBC_INLINE_VAR constexpr double ERR_D = 0x1.8p-63; #endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS // Errors when using double-double precision. -constexpr double ERR_DD = 0x1.0p-100; +LIBC_INLINE_VAR constexpr double ERR_DD = 0x1.0p-100; #endif // LIBC_MATH_HAS_SKIP_ACCURATE_PASS // Polynomial approximations with double precision. Generated by Sollya with: @@ -60,7 +60,7 @@ constexpr double ERR_DD = 0x1.0p-100; // > P; // Error bounds: // | output - (2^dx - 1) / dx | < 1.5 * 2^-52. -LIBC_INLINE static double poly_approx_d(double dx) { +LIBC_INLINE double poly_approx_d(double dx) { // dx^2 double dx2 = dx * dx; double c0 = @@ -77,8 +77,7 @@ LIBC_INLINE static double poly_approx_d(double dx) { // > P = fpminimax((2^x - 1)/x, 5, [|DD...|], [-2^-13 - 2^-30, 2^-13 + 2^-30]); // Error bounds: // | output - 2^(dx) | < 2^-101 -LIBC_INLINE static constexpr DoubleDouble -poly_approx_dd(const DoubleDouble &dx) { +LIBC_INLINE constexpr DoubleDouble poly_approx_dd(const DoubleDouble &dx) { // Taylor polynomial. constexpr DoubleDouble COEFFS[] = { {0, 0x1p0}, @@ -99,7 +98,7 @@ poly_approx_dd(const DoubleDouble &dx) { // Return exp(dx) ~ 1 + a0 * dx + a1 * dx^2 + ... + a6 * dx^7 // For |dx| < 2^-13 + 2^-30: // | output - exp(dx) | < 2^-126. -LIBC_INLINE static constexpr Float128 poly_approx_f128(const Float128 &dx) { +LIBC_INLINE constexpr Float128 poly_approx_f128(const Float128 &dx) { constexpr Float128 COEFFS_128[]{ {Sign::POS, -127, 0x80000000'00000000'00000000'00000000_u128}, // 1.0 {Sign::POS, -128, 0xb17217f7'd1cf79ab'c9e3b398'03f2f6af_u128}, @@ -120,8 +119,7 @@ LIBC_INLINE static constexpr Float128 poly_approx_f128(const Float128 &dx) { // Compute 2^(x) using 128-bit precision. // TODO(lntue): investigate triple-double precision implementation for this // step. -LIBC_INLINE static constexpr Float128 exp2_f128(double x, int hi, int idx1, - int idx2) { +LIBC_INLINE constexpr Float128 exp2_f128(double x, int hi, int idx1, int idx2) { Float128 dx = Float128(x); // TODO: Skip recalculating exp_mid1 and exp_mid2. @@ -147,8 +145,8 @@ LIBC_INLINE static constexpr Float128 exp2_f128(double x, int hi, int idx1, } // Compute 2^x with double-double precision. -LIBC_INLINE static DoubleDouble -exp2_double_double(double x, const DoubleDouble &exp_mid) { +LIBC_INLINE DoubleDouble exp2_double_double(double x, + const DoubleDouble &exp_mid) { DoubleDouble dx({0, x}); // Degree-6 polynomial approximation in double-double precision. @@ -163,7 +161,7 @@ exp2_double_double(double x, const DoubleDouble &exp_mid) { #endif // LIBC_MATH_HAS_SKIP_ACCURATE_PASS // When output is denormal. -LIBC_INLINE static double exp2_denorm(double x) { +LIBC_INLINE double exp2_denorm(double x) { // Range reduction. int k = static_cast(cpp::bit_cast(x + 0x1.8000'0000'4p21) >> 19); @@ -215,7 +213,7 @@ LIBC_INLINE static double exp2_denorm(double x) { // * x >= 1024 // * x <= -1022 // * x is inf or nan -LIBC_INLINE static constexpr double set_exceptional(double x) { +LIBC_INLINE constexpr double set_exceptional(double x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); @@ -266,7 +264,7 @@ LIBC_INLINE static constexpr double set_exceptional(double x) { } // namespace exp2_internal -LIBC_INLINE static constexpr double exp2(double x) { +LIBC_INLINE constexpr double exp2(double x) { using namespace exp2_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/exp2f.h b/libc/src/__support/math/exp2f.h index ef2aad051b8a9..a231fcedda034 100644 --- a/libc/src/__support/math/exp2f.h +++ b/libc/src/__support/math/exp2f.h @@ -26,7 +26,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float exp2f(float x) { +LIBC_INLINE constexpr float exp2f(float x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/exp2f16.h b/libc/src/__support/math/exp2f16.h index 599ba0f5411bd..8ff918b665a6f 100644 --- a/libc/src/__support/math/exp2f16.h +++ b/libc/src/__support/math/exp2f16.h @@ -27,7 +27,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 exp2f16(float16 x) { +LIBC_INLINE constexpr float16 exp2f16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr fputil::ExceptValues EXP2F16_EXCEPTS = {{ diff --git a/libc/src/__support/math/exp2m1f.h b/libc/src/__support/math/exp2m1f.h index e95076c9eac22..f1acde27ac0e1 100644 --- a/libc/src/__support/math/exp2m1f.h +++ b/libc/src/__support/math/exp2m1f.h @@ -26,7 +26,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float exp2m1f(float x) { +LIBC_INLINE constexpr float exp2m1f(float x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr size_t N_EXCEPTS_LO = 8; diff --git a/libc/src/__support/math/exp2m1f16.h b/libc/src/__support/math/exp2m1f16.h index 0424af4aa953d..196fc52158cfc 100644 --- a/libc/src/__support/math/exp2m1f16.h +++ b/libc/src/__support/math/exp2m1f16.h @@ -29,7 +29,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 exp2m1f16(float16 x) { +LIBC_INLINE constexpr float16 exp2m1f16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr fputil::ExceptValues EXP2M1F16_EXCEPTS_LO = {{ // (input, RZ output, RU offset, RD offset, RN offset) diff --git a/libc/src/__support/math/exp_constants.h b/libc/src/__support/math/exp_constants.h index 1abb4479e0848..2a5d585efff1f 100644 --- a/libc/src/__support/math/exp_constants.h +++ b/libc/src/__support/math/exp_constants.h @@ -10,6 +10,7 @@ #define LLVM_LIBC_SRC___SUPPORT_MATH_EXP_CONSTANTS_H #include "src/__support/FPUtil/triple_double.h" +#include "src/__support/macros/attributes.h" namespace LIBC_NAMESPACE_DECL { @@ -24,7 +25,7 @@ namespace LIBC_NAMESPACE_DECL { // d = round(a - b - c, D, RN); // print("{", d, ",", c, ",", b, "},"); // }; -static constexpr fputil::TripleDouble EXP2_MID1[64] = { +LIBC_INLINE_VAR constexpr fputil::TripleDouble EXP2_MID1[64] = { {0, 0, 0x1p0}, {-0x1.9085b0a3d74d5p-110, -0x1.19083535b085dp-56, 0x1.02c9a3e778061p0}, {0x1.05ff94f8d257ep-110, 0x1.d73e2a475b465p-55, 0x1.059b0d3158574p0}, @@ -102,7 +103,7 @@ static constexpr fputil::TripleDouble EXP2_MID1[64] = { // d = round(a - b - c, D, RN); // print("{", d, ",", c, ",", b, "},"); // }; -static constexpr fputil::TripleDouble EXP2_MID2[64] = { +LIBC_INLINE_VAR constexpr fputil::TripleDouble EXP2_MID2[64] = { {0, 0, 0x1p0}, {0x1.39726694630e3p-108, 0x1.ae8e38c59c72ap-54, 0x1.000b175effdc7p0}, {0x1.e5e06ddd31156p-112, -0x1.7b5d0d58ea8f4p-58, 0x1.00162f3904052p0}, diff --git a/libc/src/__support/math/exp_float_constants.h b/libc/src/__support/math/exp_float_constants.h index cabb227a034b5..86cc0f5fbee35 100644 --- a/libc/src/__support/math/exp_float_constants.h +++ b/libc/src/__support/math/exp_float_constants.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_MATH_EXP_FLOAT_CONSTANTS_H #define LLVM_LIBC_SRC___SUPPORT_MATH_EXP_FLOAT_CONSTANTS_H +#include "src/__support/macros/attributes.h" #include "src/__support/macros/config.h" namespace LIBC_NAMESPACE_DECL { @@ -20,7 +21,7 @@ namespace math { // Table is generated with Sollya as follow: // > display = hexadecimal; // > for i from -104 to 89 do { D(exp(i)); }; -static constexpr double EXP_M1[195] = { +LIBC_INLINE_VAR constexpr double EXP_M1[195] = { 0x1.f1e6b68529e33p-151, 0x1.525be4e4e601dp-149, 0x1.cbe0a45f75eb1p-148, 0x1.3884e838aea68p-146, 0x1.a8c1f14e2af5dp-145, 0x1.20a717e64a9bdp-143, 0x1.8851d84118908p-142, 0x1.0a9bdfb02d240p-140, 0x1.6a5bea046b42ep-139, @@ -92,7 +93,7 @@ static constexpr double EXP_M1[195] = { // Table is generated with Sollya as follow: // > display = hexadecimal; // > for i from 0 to 127 do { D(exp(i / 128)); }; -static constexpr double EXP_M2[128] = { +LIBC_INLINE_VAR constexpr double EXP_M2[128] = { 0x1.0000000000000p0, 0x1.0202015600446p0, 0x1.04080ab55de39p0, 0x1.06122436410ddp0, 0x1.08205601127edp0, 0x1.0a32a84e9c1f6p0, 0x1.0c49236829e8cp0, 0x1.0e63cfa7ab09dp0, 0x1.1082b577d34edp0, diff --git a/libc/src/__support/math/exp_utils.h b/libc/src/__support/math/exp_utils.h index ef408edbc9931..abb97a74a9de8 100644 --- a/libc/src/__support/math/exp_utils.h +++ b/libc/src/__support/math/exp_utils.h @@ -22,7 +22,7 @@ namespace LIBC_NAMESPACE_DECL { // So if we scale x up by 2^1022, we can use // double(1.0 + 2^1022 * x) - 1.0 to test how x is rounded in denormal range. template -LIBC_INLINE static constexpr cpp::optional +LIBC_INLINE constexpr cpp::optional ziv_test_denorm(int hi, double mid, double lo, double err) { using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/expf.h b/libc/src/__support/math/expf.h index f7e11be81a7c9..5fcf0ffa97d5c 100644 --- a/libc/src/__support/math/expf.h +++ b/libc/src/__support/math/expf.h @@ -24,7 +24,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float expf(float x) { +LIBC_INLINE constexpr float expf(float x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/expf16.h b/libc/src/__support/math/expf16.h index 14302a7c4891e..2ca7c021e36b9 100644 --- a/libc/src/__support/math/expf16.h +++ b/libc/src/__support/math/expf16.h @@ -13,6 +13,7 @@ #ifdef LIBC_TYPES_HAS_FLOAT16 +#include "expf16_utils.h" #include "hdr/errno_macros.h" #include "hdr/fenv_macros.h" #include "src/__support/FPUtil/FEnvImpl.h" @@ -25,13 +26,11 @@ #include "src/__support/macros/config.h" #include "src/__support/macros/optimization.h" -#include "expf16_utils.h" - namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 expf16(float16 x) { +LIBC_INLINE constexpr float16 expf16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr fputil::ExceptValues EXPF16_EXCEPTS_LO = {{ // (input, RZ output, RU offset, RD offset, RN offset) diff --git a/libc/src/__support/math/expf16_utils.h b/libc/src/__support/math/expf16_utils.h index 4204dab72a0c3..de7add4ecf731 100644 --- a/libc/src/__support/math/expf16_utils.h +++ b/libc/src/__support/math/expf16_utils.h @@ -23,7 +23,7 @@ namespace LIBC_NAMESPACE_DECL { // Generated by Sollya with the following commands: // > display = hexadecimal; // > for i from -18 to 12 do print(round(exp(i), SG, RN)); -static constexpr cpp::array EXP_HI = { +LIBC_INLINE_VAR constexpr cpp::array EXP_HI = { 0x1.05a628p-26f, 0x1.639e32p-25f, 0x1.e355bcp-24f, 0x1.4875cap-22f, 0x1.be6c7p-21f, 0x1.2f6054p-19f, 0x1.9c54c4p-18f, 0x1.183542p-16f, 0x1.7cd79cp-15f, 0x1.02cf22p-13f, 0x1.5fc21p-12f, 0x1.de16bap-11f, @@ -37,7 +37,7 @@ static constexpr cpp::array EXP_HI = { // Generated by Sollya with the following commands: // > display = hexadecimal; // > for i from 0 to 7 do print(round(exp(i * 2^-3), SG, RN)); -static constexpr cpp::array EXP_MID = { +LIBC_INLINE_VAR constexpr cpp::array EXP_MID = { 0x1p+0f, 0x1.221604p+0f, 0x1.48b5e4p+0f, 0x1.747a52p+0f, 0x1.a61298p+0f, 0x1.de455ep+0f, 0x1.0ef9dcp+1f, 0x1.330e58p+1f, }; @@ -47,8 +47,7 @@ struct ExpRangeReduction { float exp_lo; }; -[[maybe_unused]] LIBC_INLINE static ExpRangeReduction -exp_range_reduction(float16 x) { +[[maybe_unused]] LIBC_INLINE ExpRangeReduction exp_range_reduction(float16 x) { // For -18 < x < 12, to compute exp(x), we perform the following range // reduction: find hi, mid, lo, such that: // x = hi + mid + lo, in which diff --git a/libc/src/__support/math/expm1.h b/libc/src/__support/math/expm1.h index 4bbb20ffbf7a1..7066997ebcc09 100644 --- a/libc/src/__support/math/expm1.h +++ b/libc/src/__support/math/expm1.h @@ -43,15 +43,15 @@ using Float128 = typename fputil::DyadicFloat<128>; using LIBC_NAMESPACE::operator""_u128; // log2(e) -static constexpr double LOG2_E = 0x1.71547652b82fep+0; +LIBC_INLINE_VAR constexpr double LOG2_E = 0x1.71547652b82fep+0; // Error bounds: // Errors when using double precision. // 0x1.8p-63; -static constexpr uint64_t ERR_D = 0x3c08000000000000; +LIBC_INLINE_VAR constexpr uint64_t ERR_D = 0x3c08000000000000; // Errors when using double-double precision. // 0x1.0p-99 -[[maybe_unused]] static constexpr uint64_t ERR_DD = 0x39c0000000000000; +[[maybe_unused]] LIBC_INLINE_VAR constexpr uint64_t ERR_DD = 0x39c0000000000000; // -2^-12 * log(2) // > a = -2^-12 * log(2); @@ -59,10 +59,10 @@ static constexpr uint64_t ERR_D = 0x3c08000000000000; // > c = round(a - b, 30, RN); // > d = round(a - b - c, D, RN); // Errors < 1.5 * 2^-133 -static constexpr double MLOG_2_EXP2_M12_HI = -0x1.62e42ffp-13; -static constexpr double MLOG_2_EXP2_M12_MID = 0x1.718432a1b0e26p-47; -static constexpr double MLOG_2_EXP2_M12_MID_30 = 0x1.718432ap-47; -static constexpr double MLOG_2_EXP2_M12_LO = 0x1.b0e2633fe0685p-79; +LIBC_INLINE_VAR constexpr double MLOG_2_EXP2_M12_HI = -0x1.62e42ffp-13; +LIBC_INLINE_VAR constexpr double MLOG_2_EXP2_M12_MID = 0x1.718432a1b0e26p-47; +LIBC_INLINE_VAR constexpr double MLOG_2_EXP2_M12_MID_30 = 0x1.718432ap-47; +LIBC_INLINE_VAR constexpr double MLOG_2_EXP2_M12_LO = 0x1.b0e2633fe0685p-79; using namespace common_constants_internal; @@ -70,7 +70,7 @@ using namespace common_constants_internal; // Return expm1(dx) / x ~ 1 + dx / 2 + dx^2 / 6 + dx^3 / 24. // For |dx| < 2^-13 + 2^-30: // | output - expm1(dx) / dx | < 2^-51. -LIBC_INLINE static double poly_approx_d(double dx) { +LIBC_INLINE double poly_approx_d(double dx) { // dx^2 double dx2 = dx * dx; // c0 = 1 + dx / 2 @@ -87,8 +87,7 @@ LIBC_INLINE static double poly_approx_d(double dx) { // Return expm1(dx) / dx ~ 1 + dx / 2 + dx^2 / 6 + ... + dx^6 / 5040 // For |dx| < 2^-13 + 2^-30: // | output - expm1(dx) | < 2^-101 -LIBC_INLINE static constexpr DoubleDouble -poly_approx_dd(const DoubleDouble &dx) { +LIBC_INLINE constexpr DoubleDouble poly_approx_dd(const DoubleDouble &dx) { // Taylor polynomial. constexpr DoubleDouble COEFFS[] = { {0, 0x1p0}, // 1 @@ -109,7 +108,7 @@ poly_approx_dd(const DoubleDouble &dx) { // Return (exp(dx) - 1)/dx ~ 1 + dx / 2 + dx^2 / 6 + ... + dx^6 / 5040 // For |dx| < 2^-13 + 2^-30: // | output - exp(dx) | < 2^-126. -[[maybe_unused]] LIBC_INLINE static constexpr Float128 +[[maybe_unused]] LIBC_INLINE constexpr Float128 poly_approx_f128(const Float128 &dx) { constexpr Float128 COEFFS_128[]{ {Sign::POS, -127, 0x80000000'00000000'00000000'00000000_u128}, // 1.0 @@ -144,8 +143,8 @@ std::ostream &operator<<(std::ostream &OS, const DoubleDouble &r) { // Compute exp(x) - 1 using 128-bit precision. // TODO(lntue): investigate triple-double precision implementation for this // step. -[[maybe_unused]] LIBC_INLINE static Float128 expm1_f128(double x, double kd, - int idx1, int idx2) { +[[maybe_unused]] LIBC_INLINE Float128 expm1_f128(double x, double kd, int idx1, + int idx2) { // Recalculate dx: double t1 = fputil::multiply_add(kd, MLOG_2_EXP2_M12_HI, x); // exact @@ -196,9 +195,9 @@ std::ostream &operator<<(std::ostream &OS, const DoubleDouble &r) { } // Compute exp(x) - 1 with double-double precision. -LIBC_INLINE static DoubleDouble exp_double_double(double x, double kd, - const DoubleDouble &exp_mid, - const DoubleDouble &hi_part) { +LIBC_INLINE DoubleDouble exp_double_double(double x, double kd, + const DoubleDouble &exp_mid, + const DoubleDouble &hi_part) { // Recalculate dx: // dx = x - k * 2^-12 * log(2) double t1 = fputil::multiply_add(kd, MLOG_2_EXP2_M12_HI, x); // exact @@ -226,7 +225,7 @@ LIBC_INLINE static DoubleDouble exp_double_double(double x, double kd, // Check for exceptional cases when // |x| <= 2^-53 or x < log(2^-54) or x >= 0x1.6232bdd7abcd3p+9 -LIBC_INLINE static constexpr double set_exceptional(double x) { +LIBC_INLINE constexpr double set_exceptional(double x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); @@ -280,7 +279,7 @@ LIBC_INLINE static constexpr double set_exceptional(double x) { } // namespace expm1_internal -LIBC_INLINE static constexpr double expm1(double x) { +LIBC_INLINE constexpr double expm1(double x) { using namespace expm1_internal; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/expm1f.h b/libc/src/__support/math/expm1f.h index 43e79ae3112dc..f581635f77c7b 100644 --- a/libc/src/__support/math/expm1f.h +++ b/libc/src/__support/math/expm1f.h @@ -27,7 +27,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float expm1f(float x) { +LIBC_INLINE constexpr float expm1f(float x) { using namespace common_constants_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/expm1f16.h b/libc/src/__support/math/expm1f16.h index 79547b62b0892..a14a6f051a834 100644 --- a/libc/src/__support/math/expm1f16.h +++ b/libc/src/__support/math/expm1f16.h @@ -29,7 +29,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 expm1f16(float16 x) { +LIBC_INLINE constexpr float16 expm1f16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr fputil::ExceptValues EXPM1F16_EXCEPTS_LO = {{ // (input, RZ output, RU offset, RD offset, RN offset) diff --git a/libc/src/__support/math/expxf16_utils.h b/libc/src/__support/math/expxf16_utils.h index 5d3bd3845a74f..0375eaf179b9f 100644 --- a/libc/src/__support/math/expxf16_utils.h +++ b/libc/src/__support/math/expxf16_utils.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIBC_SRC_MATH_GENERIC_EXPXF16_H -#define LLVM_LIBC_SRC_MATH_GENERIC_EXPXF16_H +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_EXPXF16_UTILS_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_EXPXF16_UTILS_H #include "hdr/stdint_proxy.h" #include "src/__support/FPUtil/FPBits.h" @@ -25,7 +25,7 @@ namespace math { namespace expxf16_internal { -LIBC_INLINE static ExpRangeReduction exp2_range_reduction(float16 x) { +LIBC_INLINE ExpRangeReduction exp2_range_reduction(float16 x) { // For -25 < x < 16, to compute 2^x, we perform the following range reduction: // find hi, mid, lo, such that: // x = hi + mid + lo, in which @@ -65,17 +65,17 @@ LIBC_INLINE static ExpRangeReduction exp2_range_reduction(float16 x) { // Generated by Sollya with the following commands: // > display = hexadecimal; // > round(log2(exp(1)), SG, RN); -static constexpr float LOG2F_E = 0x1.715476p+0f; +LIBC_INLINE_VAR constexpr float LOG2F_E = 0x1.715476p+0f; // Generated by Sollya with the following commands: // > display = hexadecimal; // > round(log(2), SG, RN); -static constexpr float LOGF_2 = 0x1.62e43p-1f; +LIBC_INLINE_VAR constexpr float LOGF_2 = 0x1.62e43p-1f; // Generated by Sollya with the following commands: // > display = hexadecimal; // > for i from 0 to 31 do printsingle(round(2^(i * 2^-5), SG, RN)); -static constexpr cpp::array EXP2_MID_5_BITS = { +LIBC_INLINE_VAR constexpr cpp::array EXP2_MID_5_BITS = { 0x3f80'0000U, 0x3f82'cd87U, 0x3f85'aac3U, 0x3f88'980fU, 0x3f8b'95c2U, 0x3f8e'a43aU, 0x3f91'c3d3U, 0x3f94'f4f0U, 0x3f98'37f0U, 0x3f9b'8d3aU, 0x3f9e'f532U, 0x3fa2'7043U, 0x3fa5'fed7U, 0x3fa9'a15bU, 0x3fad'583fU, @@ -122,7 +122,7 @@ static constexpr cpp::array EXP2_MID_5_BITS = { // the polynomials approximating lower parts of e^x and e^(-x) is shared and // only done once. template -LIBC_INLINE static constexpr float16 eval_sinh_or_cosh(float16 x) { +LIBC_INLINE constexpr float16 eval_sinh_or_cosh(float16 x) { float xf = x; float kf = fputil::nearest_integer(xf * (LOG2F_E * 0x1.0p+5f)); int x_hi_mid_p = static_cast(kf); @@ -179,7 +179,7 @@ LIBC_INLINE static constexpr float16 eval_sinh_or_cosh(float16 x) { // Generated by Sollya with the following commands: // > display = hexadecimal; // > for i from 0 to 31 do print(round(log(1 + i * 2^-5), SG, RN)); -static constexpr cpp::array LOGF_F = { +LIBC_INLINE_VAR constexpr cpp::array LOGF_F = { 0x0p+0f, 0x1.f829bp-6f, 0x1.f0a30cp-5f, 0x1.6f0d28p-4f, 0x1.e27076p-4f, 0x1.29553p-3f, 0x1.5ff308p-3f, 0x1.9525aap-3f, 0x1.c8ff7cp-3f, 0x1.fb9186p-3f, 0x1.1675cap-2f, 0x1.2e8e2cp-2f, @@ -193,7 +193,7 @@ static constexpr cpp::array LOGF_F = { // Generated by Sollya with the following commands: // > display = hexadecimal; // > for i from 0 to 31 do print(round(log2(1 + i * 2^-5), SG, RN)); -static constexpr cpp::array LOG2F_F = { +LIBC_INLINE_VAR constexpr cpp::array LOG2F_F = { 0x0p+0f, 0x1.6bad38p-5f, 0x1.663f7p-4f, 0x1.08c588p-3f, 0x1.5c01a4p-3f, 0x1.acf5e2p-3f, 0x1.fbc16cp-3f, 0x1.24407ap-2f, 0x1.49a784p-2f, 0x1.6e221cp-2f, 0x1.91bba8p-2f, 0x1.b47ecp-2f, @@ -207,7 +207,7 @@ static constexpr cpp::array LOG2F_F = { // Generated by Sollya with the following commands: // > display = hexadecimal; // > for i from 0 to 31 do print(round(log10(1 + i * 2^-5), SG, RN)); -static constexpr cpp::array LOG10F_F = { +LIBC_INLINE_VAR constexpr cpp::array LOG10F_F = { 0x0p+0f, 0x1.b5e908p-7f, 0x1.af5f92p-6f, 0x1.3ed11ap-5f, 0x1.a30a9ep-5f, 0x1.02428cp-4f, 0x1.31b306p-4f, 0x1.5fe804p-4f, 0x1.8cf184p-4f, 0x1.b8de4ep-4f, 0x1.e3bc1ap-4f, 0x1.06cbd6p-3f, @@ -221,7 +221,7 @@ static constexpr cpp::array LOG10F_F = { // Generated by Sollya with the following commands: // > display = hexadecimal; // > for i from 0 to 31 do print(round(1 / (1 + i * 2^-5), SG, RN)); -static constexpr cpp::array ONE_OVER_F_F = { +LIBC_INLINE_VAR constexpr cpp::array ONE_OVER_F_F = { 0x1p+0f, 0x1.f07c2p-1f, 0x1.e1e1e2p-1f, 0x1.d41d42p-1f, 0x1.c71c72p-1f, 0x1.bacf92p-1f, 0x1.af286cp-1f, 0x1.a41a42p-1f, 0x1.99999ap-1f, 0x1.8f9c18p-1f, 0x1.861862p-1f, 0x1.7d05f4p-1f, @@ -238,4 +238,4 @@ static constexpr cpp::array ONE_OVER_F_F = { } // namespace LIBC_NAMESPACE_DECL -#endif // LLVM_LIBC_SRC_MATH_GENERIC_EXPXF16_H +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_EXPXF16_UTILS_H diff --git a/libc/src/__support/math/f16fma.h b/libc/src/__support/math/f16fma.h index f7bb2fe33e963..2fc8e657b9efe 100644 --- a/libc/src/__support/math/f16fma.h +++ b/libc/src/__support/math/f16fma.h @@ -20,7 +20,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static float16 f16fma(double x, double y, double z) { +LIBC_INLINE float16 f16fma(double x, double y, double z) { return fputil::fma(x, y, z); } diff --git a/libc/src/__support/math/f16fmaf.h b/libc/src/__support/math/f16fmaf.h new file mode 100644 index 0000000000000..92f94a9721e7d --- /dev/null +++ b/libc/src/__support/math/f16fmaf.h @@ -0,0 +1,33 @@ +//===-- Implementation header for f16fmaf -----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_F16FMAF_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_F16FMAF_H + +#include "include/llvm-libc-macros/float16-macros.h" + +#ifdef LIBC_TYPES_HAS_FLOAT16 + +#include "src/__support/FPUtil/FMA.h" +#include "src/__support/macros/config.h" + +namespace LIBC_NAMESPACE_DECL { + +namespace math { + +LIBC_INLINE float16 f16fmaf(float x, float y, float z) { + return fputil::fma(x, y, z); +} + +} // namespace math + +} // namespace LIBC_NAMESPACE_DECL + +#endif // LIBC_TYPES_HAS_FLOAT16 + +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_F16FMAF_H diff --git a/libc/src/__support/math/f16fmaf128.h b/libc/src/__support/math/f16fmaf128.h new file mode 100644 index 0000000000000..a8ba4bce9eb30 --- /dev/null +++ b/libc/src/__support/math/f16fmaf128.h @@ -0,0 +1,37 @@ +//===-- Implementation header for f16fmaf128 --------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_F16FMAF128_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_F16FMAF128_H + +#include "include/llvm-libc-macros/float16-macros.h" +#include "include/llvm-libc-types/float128.h" + +#ifdef LIBC_TYPES_HAS_FLOAT128 +#ifdef LIBC_TYPES_HAS_FLOAT16 + +#include "src/__support/FPUtil/FMA.h" +#include "src/__support/common.h" +#include "src/__support/macros/config.h" + +namespace LIBC_NAMESPACE_DECL { + +namespace math { + +LIBC_INLINE float16 f16fmaf128(float128 x, float128 y, float128 z) { + return fputil::fma(x, y, z); +} + +} // namespace math + +} // namespace LIBC_NAMESPACE_DECL + +#endif // LIBC_TYPES_HAS_FLOAT16 +#endif // LIBC_TYPES_HAS_FLOAT128 + +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_F16FMAF128_H diff --git a/libc/src/__support/math/f16fmal.h b/libc/src/__support/math/f16fmal.h index 6e9c4b9af13f4..72fd6950fab49 100644 --- a/libc/src/__support/math/f16fmal.h +++ b/libc/src/__support/math/f16fmal.h @@ -20,8 +20,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static float16 f16fmal(long double x, long double y, - long double z) { +LIBC_INLINE float16 f16fmal(long double x, long double y, long double z) { return fputil::fma(x, y, z); } diff --git a/libc/src/__support/math/f16sqrt.h b/libc/src/__support/math/f16sqrt.h index 806aa9fd97372..656196cdb6281 100644 --- a/libc/src/__support/math/f16sqrt.h +++ b/libc/src/__support/math/f16sqrt.h @@ -20,7 +20,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 f16sqrt(double x) { +LIBC_INLINE constexpr float16 f16sqrt(double x) { return fputil::sqrt(x); } diff --git a/libc/src/__support/math/f16sqrtl.h b/libc/src/__support/math/f16sqrtl.h index 86f0e594408e1..f76642fa13fa1 100644 --- a/libc/src/__support/math/f16sqrtl.h +++ b/libc/src/__support/math/f16sqrtl.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 f16sqrtl(long double x) { +LIBC_INLINE constexpr float16 f16sqrtl(long double x) { return fputil::sqrt(x); } diff --git a/libc/src/__support/math/ffmal.h b/libc/src/__support/math/ffmal.h new file mode 100644 index 0000000000000..b03c45ea25cf2 --- /dev/null +++ b/libc/src/__support/math/ffmal.h @@ -0,0 +1,28 @@ +//===-- Implementation header for ffmal -------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_FFMAL_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_FFMAL_H + +#include "src/__support/FPUtil/FMA.h" +#include "src/__support/common.h" +#include "src/__support/macros/config.h" + +namespace LIBC_NAMESPACE_DECL { + +namespace math { + +LIBC_INLINE float ffmal(long double x, long double y, long double z) { + return fputil::fma(x, y, z); +} + +} // namespace math + +} // namespace LIBC_NAMESPACE_DECL + +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_FFMAL_H diff --git a/libc/src/__support/math/frexpf.h b/libc/src/__support/math/frexpf.h index 7834a12793d30..caaaaeaf58306 100644 --- a/libc/src/__support/math/frexpf.h +++ b/libc/src/__support/math/frexpf.h @@ -17,7 +17,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float frexpf(float x, int *exp) { +LIBC_INLINE constexpr float frexpf(float x, int *exp) { return fputil::frexp(x, *exp); } diff --git a/libc/src/__support/math/frexpf128.h b/libc/src/__support/math/frexpf128.h index 5218b26dd52c6..176a33f0d2407 100644 --- a/libc/src/__support/math/frexpf128.h +++ b/libc/src/__support/math/frexpf128.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float128 frexpf128(float128 x, int *exp) { +LIBC_INLINE constexpr float128 frexpf128(float128 x, int *exp) { return fputil::frexp(x, *exp); } diff --git a/libc/src/__support/math/frexpf16.h b/libc/src/__support/math/frexpf16.h index 530b61aea0aeb..0bfc323326add 100644 --- a/libc/src/__support/math/frexpf16.h +++ b/libc/src/__support/math/frexpf16.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 frexpf16(float16 x, int *exp) { +LIBC_INLINE constexpr float16 frexpf16(float16 x, int *exp) { return fputil::frexp(x, *exp); } diff --git a/libc/src/__support/math/fsqrt.h b/libc/src/__support/math/fsqrt.h index 8dd6afc7845f0..d35f25b9a8111 100644 --- a/libc/src/__support/math/fsqrt.h +++ b/libc/src/__support/math/fsqrt.h @@ -15,9 +15,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float fsqrt(double x) { - return fputil::sqrt(x); -} +LIBC_INLINE constexpr float fsqrt(double x) { return fputil::sqrt(x); } } // namespace math diff --git a/libc/src/__support/math/fsqrtf128.h b/libc/src/__support/math/fsqrtf128.h index 8ca274eff6888..955e19a818c57 100644 --- a/libc/src/__support/math/fsqrtf128.h +++ b/libc/src/__support/math/fsqrtf128.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float fsqrtf128(float128 x) { +LIBC_INLINE constexpr float fsqrtf128(float128 x) { return fputil::sqrt(x); } diff --git a/libc/src/__support/math/fsqrtl.h b/libc/src/__support/math/fsqrtl.h index 3033f0a5242f3..26c3b9e4c14c9 100644 --- a/libc/src/__support/math/fsqrtl.h +++ b/libc/src/__support/math/fsqrtl.h @@ -15,7 +15,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float fsqrtl(long double x) { +LIBC_INLINE constexpr float fsqrtl(long double x) { return fputil::sqrt(x); } diff --git a/libc/src/__support/math/hypotf.h b/libc/src/__support/math/hypotf.h index e712a07bda01a..081fc91ce4dfb 100644 --- a/libc/src/__support/math/hypotf.h +++ b/libc/src/__support/math/hypotf.h @@ -22,7 +22,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static float hypotf(float x, float y) { +LIBC_INLINE float hypotf(float x, float y) { using DoubleBits = fputil::FPBits; using FPBits = fputil::FPBits; diff --git a/libc/src/__support/math/ilogb.h b/libc/src/__support/math/ilogb.h index 021531489b43f..1172645f678c5 100644 --- a/libc/src/__support/math/ilogb.h +++ b/libc/src/__support/math/ilogb.h @@ -17,9 +17,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr int ilogb(double x) { - return fputil::intlogb(x); -} +LIBC_INLINE constexpr int ilogb(double x) { return fputil::intlogb(x); } } // namespace math } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/__support/math/ilogbf128.h b/libc/src/__support/math/ilogbf128.h index 47c3643c2326e..a2a4a3b194044 100644 --- a/libc/src/__support/math/ilogbf128.h +++ b/libc/src/__support/math/ilogbf128.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr int ilogbf128(float128 x) { +LIBC_INLINE constexpr int ilogbf128(float128 x) { return fputil::intlogb(x); } diff --git a/libc/src/__support/math/ilogbl.h b/libc/src/__support/math/ilogbl.h index 1d6a8b568fe06..71c5bb5ed4ba7 100644 --- a/libc/src/__support/math/ilogbl.h +++ b/libc/src/__support/math/ilogbl.h @@ -17,7 +17,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr int ilogbl(long double x) { +LIBC_INLINE constexpr int ilogbl(long double x) { return fputil::intlogb(x); } diff --git a/libc/src/__support/math/inv_trigf_utils.h b/libc/src/__support/math/inv_trigf_utils.h index 4a8fbeca93e49..6eab68d8bbe01 100644 --- a/libc/src/__support/math/inv_trigf_utils.h +++ b/libc/src/__support/math/inv_trigf_utils.h @@ -19,8 +19,8 @@ namespace LIBC_NAMESPACE_DECL { namespace inv_trigf_utils_internal { // PI and PI / 2 -static constexpr double M_MATH_PI = 0x1.921fb54442d18p+1; -static constexpr double M_MATH_PI_2 = 0x1.921fb54442d18p+0; +LIBC_INLINE_VAR constexpr double M_MATH_PI = 0x1.921fb54442d18p+1; +LIBC_INLINE_VAR constexpr double M_MATH_PI_2 = 0x1.921fb54442d18p+0; // Polynomial approximation for 0 <= x <= 1: // atan(x) ~ atan((i/16) + (x - (i/16)) * Q(x - i/16) @@ -40,7 +40,7 @@ static constexpr double M_MATH_PI_2 = 0x1.921fb54442d18p+0; // Notice that degree-7 is good enough for atanf, but degree-8 helps reduce the // error bounds for atan2f's fast pass 16 times, and it does not affect the // performance of atanf much. -static constexpr double ATAN_COEFFS[17][9] = { +LIBC_INLINE_VAR constexpr double ATAN_COEFFS[17][9] = { {0.0, 1.0, 0x1.3f8d76d26d61bp-47, -0x1.5555555574cd8p-2, 0x1.0dde5d06878eap-29, 0x1.99997738acc77p-3, 0x1.2c43eac9797cap-16, -0x1.25fb020007dbdp-3, 0x1.c1b6c31d7b0aep-7}, @@ -95,7 +95,7 @@ static constexpr double ATAN_COEFFS[17][9] = { }; // Look-up table for atan(k/16) with k = 0..16. -static constexpr double ATAN_K_OVER_16[17] = { +LIBC_INLINE_VAR constexpr double ATAN_K_OVER_16[17] = { 0.0, 0x1.ff55bb72cfdeap-5, 0x1.fd5ba9aac2f6ep-4, @@ -117,7 +117,7 @@ static constexpr double ATAN_K_OVER_16[17] = { // For |x| <= 1/32 and 0 <= i <= 16, return Q(x) such that: // Q(x) ~ (atan(x + i/16) - atan(i/16)) / x. -LIBC_INLINE static double atan_eval(double x, unsigned i) { +LIBC_INLINE double atan_eval(double x, unsigned i) { double x2 = x * x; double c0 = fputil::multiply_add(x, ATAN_COEFFS[i][2], ATAN_COEFFS[i][1]); @@ -138,8 +138,8 @@ LIBC_INLINE static double atan_eval(double x, unsigned i) { // So we let q = (n - d * k/16) / (d + n * k/16), // and approximate with Taylor polynomial: // atan(q) ~ q - q^3/3 + q^5/5 - q^7/7 + q^9/9 -LIBC_INLINE static double atan_eval_no_table(double num, double den, - double k_over_16) { +LIBC_INLINE double atan_eval_no_table(double num, double den, + double k_over_16) { double num_r = fputil::multiply_add(den, -k_over_16, num); double den_r = fputil::multiply_add(num, k_over_16, den); double q = num_r / den_r; @@ -161,14 +161,14 @@ LIBC_INLINE static double atan_eval_no_table(double num, double den, // > Q = fpminimax(asin(x)/x, [|0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20|], // [|1, D...|], [0, 0.5]); -static constexpr double ASIN_COEFFS[10] = { +LIBC_INLINE_VAR constexpr double ASIN_COEFFS[10] = { 0x1.5555555540fa1p-3, 0x1.333333512edc2p-4, 0x1.6db6cc1541b31p-5, 0x1.f1caff324770ep-6, 0x1.6e43899f5f4f4p-6, 0x1.1f847cf652577p-6, 0x1.9b60f47f87146p-7, 0x1.259e2634c494fp-6, -0x1.df946fa875ddp-8, 0x1.02311ecf99c28p-5}; // Evaluate P(x^2) - 1, where P(x^2) ~ asin(x)/x -LIBC_INLINE static double asin_eval(double xsq) { +LIBC_INLINE double asin_eval(double xsq) { double x4 = xsq * xsq; double r1 = fputil::polyeval(x4, ASIN_COEFFS[0], ASIN_COEFFS[2], ASIN_COEFFS[4], ASIN_COEFFS[6], ASIN_COEFFS[8]); diff --git a/libc/src/__support/math/ldexpf.h b/libc/src/__support/math/ldexpf.h index 9ef5d96d00e06..9d0030e3dd529 100644 --- a/libc/src/__support/math/ldexpf.h +++ b/libc/src/__support/math/ldexpf.h @@ -17,7 +17,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float ldexpf(float x, int exp) { +LIBC_INLINE constexpr float ldexpf(float x, int exp) { return fputil::ldexp(x, exp); } diff --git a/libc/src/__support/math/ldexpf128.h b/libc/src/__support/math/ldexpf128.h index 4fba20c3a2d92..571d2f951294d 100644 --- a/libc/src/__support/math/ldexpf128.h +++ b/libc/src/__support/math/ldexpf128.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float128 ldexpf128(float128 x, int exp) { +LIBC_INLINE constexpr float128 ldexpf128(float128 x, int exp) { return fputil::ldexp(x, exp); } diff --git a/libc/src/__support/math/ldexpf16.h b/libc/src/__support/math/ldexpf16.h index d978d222142b4..b9cf06d7ec8dd 100644 --- a/libc/src/__support/math/ldexpf16.h +++ b/libc/src/__support/math/ldexpf16.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 ldexpf16(float16 x, int exp) { +LIBC_INLINE constexpr float16 ldexpf16(float16 x, int exp) { return fputil::ldexp(x, exp); } diff --git a/libc/src/__support/math/llogb.h b/libc/src/__support/math/llogb.h index 0c6acf0db6f4a..f790cfb092087 100644 --- a/libc/src/__support/math/llogb.h +++ b/libc/src/__support/math/llogb.h @@ -16,9 +16,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr long llogb(double x) { - return fputil::intlogb(x); -} +LIBC_INLINE constexpr long llogb(double x) { return fputil::intlogb(x); } } // namespace math diff --git a/libc/src/__support/math/llogbf.h b/libc/src/__support/math/llogbf.h index 1dcdcd0f7311f..ed8648242d4eb 100644 --- a/libc/src/__support/math/llogbf.h +++ b/libc/src/__support/math/llogbf.h @@ -17,9 +17,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr long llogbf(float x) { - return fputil::intlogb(x); -} +LIBC_INLINE constexpr long llogbf(float x) { return fputil::intlogb(x); } } // namespace math diff --git a/libc/src/__support/math/llogbf128.h b/libc/src/__support/math/llogbf128.h index 5168647f49c02..483c464fd3a63 100644 --- a/libc/src/__support/math/llogbf128.h +++ b/libc/src/__support/math/llogbf128.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr long llogbf128(float128 x) { +LIBC_INLINE constexpr long llogbf128(float128 x) { return fputil::intlogb(x); } diff --git a/libc/src/__support/math/llogbf16.h b/libc/src/__support/math/llogbf16.h index 55ddd3b9e2569..275a149fdbfee 100644 --- a/libc/src/__support/math/llogbf16.h +++ b/libc/src/__support/math/llogbf16.h @@ -21,7 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr long llogbf16(float16 x) { +LIBC_INLINE constexpr long llogbf16(float16 x) { return fputil::intlogb(x); } diff --git a/libc/src/__support/math/log.h b/libc/src/__support/math/log.h index 7640e6a5707c1..f7b5767899ccc 100644 --- a/libc/src/__support/math/log.h +++ b/libc/src/__support/math/log.h @@ -721,7 +721,7 @@ LIBC_INLINE_VAR constexpr Float128 BIG_COEFFS[3]{ // Reuse the output of the fast pass range reduction. // -2^-8 <= m_x < 2^-7 #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS -LIBC_INLINE static double log_accurate(int e_x, int index, double m_x) { +LIBC_INLINE double log_accurate(int e_x, int index, double m_x) { Float128 e_x_f128(static_cast(e_x)); Float128 sum = fputil::quick_mul(LOG_2, e_x_f128); @@ -744,7 +744,7 @@ LIBC_INLINE static double log_accurate(int e_x, int index, double m_x) { } // namespace log_internal -LIBC_INLINE static double log(double x) { +LIBC_INLINE double log(double x) { using namespace log_internal; using FPBits_t = typename fputil::FPBits; diff --git a/libc/src/__support/math/log10.h b/libc/src/__support/math/log10.h index 8861c8934578d..e4e7313449633 100644 --- a/libc/src/__support/math/log10.h +++ b/libc/src/__support/math/log10.h @@ -722,7 +722,7 @@ LIBC_INLINE_VAR constexpr Float128 BIG_COEFFS[4]{ // Reuse the output of the fast pass range reduction. // -2^-8 <= m_x < 2^-7 -LIBC_INLINE static double log10_accurate(int e_x, int index, double m_x) { +LIBC_INLINE double log10_accurate(int e_x, int index, double m_x) { Float128 e_x_f128(static_cast(e_x)); Float128 sum = fputil::quick_mul(LOG10_2, e_x_f128); @@ -744,7 +744,7 @@ LIBC_INLINE static double log10_accurate(int e_x, int index, double m_x) { } // namespace log10_internal -LIBC_INLINE static double log10(double x) { +LIBC_INLINE double log10(double x) { using namespace log10_internal; using namespace common_constants_internal; using FPBits_t = typename fputil::FPBits; diff --git a/libc/src/__support/math/log1p.h b/libc/src/__support/math/log1p.h index 9950161b338cb..b0ab4514e895a 100644 --- a/libc/src/__support/math/log1p.h +++ b/libc/src/__support/math/log1p.h @@ -828,8 +828,8 @@ LIBC_INLINE_VAR constexpr Float128 BIG_COEFFS[4]{ {Sign::NEG, -128, 0x80000000'00000000'00000000'00000000_u128}, }; -[[maybe_unused]] LIBC_INLINE static double -log1p_accurate(int e_x, int index, fputil::DoubleDouble m_x) { +[[maybe_unused]] LIBC_INLINE double log1p_accurate(int e_x, int index, + fputil::DoubleDouble m_x) { Float128 e_x_f128(static_cast(e_x)); Float128 sum = fputil::quick_mul(LOG_2, e_x_f128); sum = fputil::quick_add(sum, LOG_R1[index]); @@ -884,7 +884,7 @@ log1p_accurate(int e_x, int index, fputil::DoubleDouble m_x) { } // namespace log1p_internal -LIBC_INLINE static double log1p(double x) { +LIBC_INLINE double log1p(double x) { using namespace log1p_internal; using FPBits_t = typename fputil::FPBits; diff --git a/libc/src/__support/math/log2.h b/libc/src/__support/math/log2.h index 79ec907783f69..3033bf332fe04 100644 --- a/libc/src/__support/math/log2.h +++ b/libc/src/__support/math/log2.h @@ -841,7 +841,7 @@ LIBC_INLINE_VAR constexpr Float128 BIG_COEFFS[4]{ // Reuse the output of the fast pass range reduction. // -2^-8 <= m_x < 2^-7 -LIBC_INLINE static double log2_accurate(int e_x, int index, double m_x) { +LIBC_INLINE double log2_accurate(int e_x, int index, double m_x) { Float128 sum(static_cast(e_x)); sum = fputil::quick_add(sum, LOG2_TABLE.step_1[index]); @@ -862,7 +862,7 @@ LIBC_INLINE static double log2_accurate(int e_x, int index, double m_x) { } // namespace log2_internal -LIBC_INLINE static double log2(double x) { +LIBC_INLINE double log2(double x) { using namespace log2_internal; using namespace common_constants_internal; using FPBits_t = typename fputil::FPBits; diff --git a/libc/src/__support/math/logbf.h b/libc/src/__support/math/logbf.h index 1b0daf92784ed..2580748e2891b 100644 --- a/libc/src/__support/math/logbf.h +++ b/libc/src/__support/math/logbf.h @@ -17,7 +17,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float logbf(float x) { return fputil::logb(x); } +LIBC_INLINE constexpr float logbf(float x) { return fputil::logb(x); } } // namespace math diff --git a/libc/src/__support/math/logbf128.h b/libc/src/__support/math/logbf128.h index d18efc5077ade..e7053fe8a4cbd 100644 --- a/libc/src/__support/math/logbf128.h +++ b/libc/src/__support/math/logbf128.h @@ -21,9 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float128 logbf128(float128 x) { - return fputil::logb(x); -} +LIBC_INLINE constexpr float128 logbf128(float128 x) { return fputil::logb(x); } } // namespace math diff --git a/libc/src/__support/math/logbf16.h b/libc/src/__support/math/logbf16.h index 239e57b0a2cd5..2c8fe94615958 100644 --- a/libc/src/__support/math/logbf16.h +++ b/libc/src/__support/math/logbf16.h @@ -21,9 +21,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 logbf16(float16 x) { - return fputil::logb(x); -} +LIBC_INLINE constexpr float16 logbf16(float16 x) { return fputil::logb(x); } } // namespace math diff --git a/libc/src/__support/math/logf.h b/libc/src/__support/math/logf.h index e96fe28fc020d..09baa283cb120 100644 --- a/libc/src/__support/math/logf.h +++ b/libc/src/__support/math/logf.h @@ -56,7 +56,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static float logf(float x) { +LIBC_INLINE float logf(float x) { using namespace common_constants_internal; constexpr double LOG_2 = 0x1.62e42fefa39efp-1; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/logf16.h b/libc/src/__support/math/logf16.h index c123eb09b9665..77682e6082e0b 100644 --- a/libc/src/__support/math/logf16.h +++ b/libc/src/__support/math/logf16.h @@ -78,7 +78,7 @@ LIBC_INLINE_VAR constexpr fputil::ExceptValues } // namespace logf16_internal -LIBC_INLINE static float16 logf16(float16 x) { +LIBC_INLINE float16 logf16(float16 x) { using namespace math::expxf16_internal; using namespace math::logf16_internal; using FPBits = fputil::FPBits; diff --git a/libc/src/__support/math/range_reduction.h b/libc/src/__support/math/range_reduction.h index b813b2ed42d06..93ec9846e5f1b 100644 --- a/libc/src/__support/math/range_reduction.h +++ b/libc/src/__support/math/range_reduction.h @@ -17,11 +17,13 @@ namespace LIBC_NAMESPACE_DECL { -namespace generic { +namespace math { -static constexpr uint32_t FAST_PASS_BOUND = 0x4a80'0000U; // 2^22 +namespace trigonometric_func_utils_internal { -static constexpr int N_ENTRIES = 8; +LIBC_INLINE_VAR constexpr uint32_t FAST_PASS_BOUND = 0x4a80'0000U; // 2^22 + +LIBC_INLINE_VAR constexpr int N_ENTRIES = 8; // We choose to split bits of 32/pi into 28-bit precision pieces, so that the // product of x * THIRTYTWO_OVER_PI_28[i] is exact. @@ -31,13 +33,13 @@ static constexpr int N_ENTRIES = 8; // > a3 = D(round(32/pi - a1 - a2, 28, RN)); a3; // > a4 = D(round(32/pi - a1 - a2 - a3, 28, RN)); a4; // ... -static constexpr double THIRTYTWO_OVER_PI_28[N_ENTRIES] = { +LIBC_INLINE_VAR constexpr double THIRTYTWO_OVER_PI_28[N_ENTRIES] = { 0x1.45f306ep+3, -0x1.b1bbeaep-28, 0x1.3f84ebp-57, -0x1.7056592p-87, 0x1.c0db62ap-116, -0x1.4cd8778p-145, -0x1.bef806cp-174, 0x1.63abdecp-204}; // Exponents of the least significant bits of the corresponding entries in // THIRTYTWO_OVER_PI_28. -static constexpr int THIRTYTWO_OVER_PI_28_LSB_EXP[N_ENTRIES] = { +LIBC_INLINE_VAR constexpr int THIRTYTWO_OVER_PI_28_LSB_EXP[N_ENTRIES] = { -24, -55, -81, -114, -143, -170, -200, -230}; // Return k and y, where @@ -83,7 +85,9 @@ LIBC_INLINE int64_t large_range_reduction(double x, int x_exp, double &y) { return static_cast(k_hi) + static_cast(k_lo); } -} // namespace generic +} // namespace trigonometric_func_utils_internal + +} // namespace math } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/__support/math/range_reduction_double_common.h b/libc/src/__support/math/range_reduction_double_common.h index a12c25da4fdd0..5888ca5f833ef 100644 --- a/libc/src/__support/math/range_reduction_double_common.h +++ b/libc/src/__support/math/range_reduction_double_common.h @@ -25,12 +25,12 @@ namespace math { namespace range_reduction_double_internal { #ifdef LIBC_TARGET_CPU_HAS_FMA_DOUBLE -static constexpr unsigned SPLIT = fputil::DefaultSplit::VALUE; +LIBC_INLINE_VAR constexpr unsigned SPLIT = fputil::DefaultSplit::VALUE; #else // When there is no-FMA instructions, in order to have exact product of 2 double // precision with directional roundings, we need to lower the precision of the // constants by at least 1 bit, and use a different splitting constant. -static constexpr unsigned SPLIT = 28; +LIBC_INLINE_VAR constexpr unsigned SPLIT = 28; #endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE using LIBC_NAMESPACE::fputil::DoubleDouble; @@ -44,7 +44,7 @@ using Float128 = LIBC_NAMESPACE::fputil::DyadicFloat<128>; // Error bound: // |(x - k * pi/128) - (u_hi + u_lo)| <= max(ulp(ulp(u_hi)), 2^-119) // <= 2^-111. -LIBC_INLINE static unsigned range_reduction_small(double x, DoubleDouble &u) { +LIBC_INLINE unsigned range_reduction_small(double x, DoubleDouble &u) { // Values of -pi/128 used for inputs with absolute value <= 2^16. // The first 3 parts are generated with (53 - 21 = 32)-bit precision, so that // the product k * MPI_OVER_128[i] is exact. @@ -97,7 +97,7 @@ LIBC_INLINE static unsigned range_reduction_small(double x, DoubleDouble &u) { // and one of those conditions guarantees that ulp(0.25 * x_reduced) >= 2, and // will safely be discarded. -static constexpr double ONE_TWENTY_EIGHT_OVER_PI[64][4] = { +LIBC_INLINE_VAR constexpr double ONE_TWENTY_EIGHT_OVER_PI[64][4] = { {0x1.0000000000014p5, 0x1.7cc1b727220a8p-49, 0x1.4fe13abe8fa9cp-101, -0x1.911f924eb5336p-153}, {0x1.0000000145f3p5, 0x1.b727220a94fep-49, 0x1.3abe8fa9a6eep-101, @@ -284,7 +284,7 @@ struct LargeRangeReduction { }; #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS -LIBC_INLINE static Float128 range_reduction_small_f128(double x) { +LIBC_INLINE Float128 range_reduction_small_f128(double x) { constexpr Float128 PI_OVER_128_F128 = { Sign::POS, -133, 0xc90f'daa2'2168'c234'c4c6'628b'80dc'1cd1_u128}; constexpr double ONE_TWENTY_EIGHT_OVER_PI_D = 0x1.45f306dc9c883p5; @@ -306,7 +306,7 @@ LIBC_INLINE static Float128 range_reduction_small_f128(double x) { return fputil::quick_mul(y, PI_OVER_128_F128); } -static constexpr Float128 SIN_K_PI_OVER_128_F128[65] = { +LIBC_INLINE_VAR constexpr Float128 SIN_K_PI_OVER_128_F128[65] = { {Sign::POS, 0, 0}, {Sign::POS, -133, 0xc90a'afbd'1b33'efc9'c539'edcb'fda0'cf2c_u128}, {Sign::POS, -132, 0xc8fb'2f88'6ec0'9f37'6a17'954b'2b7c'5171_u128}, diff --git a/libc/src/__support/math/range_reduction_double_fma.h b/libc/src/__support/math/range_reduction_double_fma.h index 7fa3e40522cf6..b03d7f08713a3 100644 --- a/libc/src/__support/math/range_reduction_double_fma.h +++ b/libc/src/__support/math/range_reduction_double_fma.h @@ -82,7 +82,7 @@ LIBC_INLINE unsigned LargeRangeReduction::fast(double x, DoubleDouble &u) { // b = D(sin(k * pi/128) - a); // print("{", b, ",", a, "},"); // }; -LIBC_INLINE constexpr DoubleDouble SIN_K_PI_OVER_128[] = { +LIBC_INLINE_VAR constexpr DoubleDouble SIN_K_PI_OVER_128[] = { {0, 0}, {-0x1.b1d63091a013p-64, 0x1.92155f7a3667ep-6}, {-0x1.912bd0d569a9p-61, 0x1.91f65f10dd814p-5}, diff --git a/libc/src/__support/math/range_reduction_double_nofma.h b/libc/src/__support/math/range_reduction_double_nofma.h index 3990b9bcbd3bb..d3ad74b6ffb7d 100644 --- a/libc/src/__support/math/range_reduction_double_nofma.h +++ b/libc/src/__support/math/range_reduction_double_nofma.h @@ -85,7 +85,7 @@ LIBC_INLINE unsigned LargeRangeReduction::fast(double x, DoubleDouble &u) { // b = round(sin(k * pi/128) - a, D, RN); // print("{", b, ",", a, "},"); // }; -LIBC_INLINE constexpr DoubleDouble SIN_K_PI_OVER_128[] = { +LIBC_INLINE_VAR constexpr DoubleDouble SIN_K_PI_OVER_128[] = { {0, 0}, {0x1.f938a73db97fbp-58, 0x1.92155f7a3667cp-6}, {-0x1.912bd0d569a9p-61, 0x1.91f65f10dd814p-5}, diff --git a/libc/src/__support/math/range_reduction_fma.h b/libc/src/__support/math/range_reduction_fma.h index d8676d0ad1c77..fe6d94946af7e 100644 --- a/libc/src/__support/math/range_reduction_fma.h +++ b/libc/src/__support/math/range_reduction_fma.h @@ -16,16 +16,18 @@ namespace LIBC_NAMESPACE_DECL { -namespace fma { +namespace math { -static constexpr uint32_t FAST_PASS_BOUND = 0x5600'0000U; // 2^45 +namespace trigonometric_fma_utils_internal { + +LIBC_INLINE_VAR constexpr uint32_t FAST_PASS_BOUND = 0x5600'0000U; // 2^45 // Digits of 32/pi, generated by Sollya with: // > a0 = D(32/pi); // > a1 = D(32/pi - a0); // > a2 = D(32/pi - a0 - a1); // > a3 = D(32/pi - a0 - a1 - a2); -static constexpr double THIRTYTWO_OVER_PI[5] = { +LIBC_INLINE_VAR constexpr double THIRTYTWO_OVER_PI[5] = { 0x1.45f306dc9c883p+3, -0x1.6b01ec5417056p-51, -0x1.6447e493ad4cep-105, 0x1.e21c820ff28b2p-159, -0x1.508510ea79237p-214}; @@ -85,7 +87,9 @@ LIBC_INLINE int64_t large_range_reduction(double x, int x_exp, double &y) { return static_cast(k_lo); } -} // namespace fma +} // namespace trigonometric_fma_utils_internal + +} // namespace math } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/__support/math/rsqrtf.h b/libc/src/__support/math/rsqrtf.h index 5da1e73109488..1e98a5dbb428f 100644 --- a/libc/src/__support/math/rsqrtf.h +++ b/libc/src/__support/math/rsqrtf.h @@ -20,7 +20,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float rsqrtf(float x) { +LIBC_INLINE constexpr float rsqrtf(float x) { using FPBits = fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/rsqrtf16.h b/libc/src/__support/math/rsqrtf16.h index 30ab58f8a5798..ab7529682950d 100644 --- a/libc/src/__support/math/rsqrtf16.h +++ b/libc/src/__support/math/rsqrtf16.h @@ -24,7 +24,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 rsqrtf16(float16 x) { +LIBC_INLINE constexpr float16 rsqrtf16(float16 x) { using FPBits = fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/sin.h b/libc/src/__support/math/sin.h index 3a67af08b2b80..124df61b1dc80 100644 --- a/libc/src/__support/math/sin.h +++ b/libc/src/__support/math/sin.h @@ -29,7 +29,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr double sin(double x) { +LIBC_INLINE constexpr double sin(double x) { using namespace math::range_reduction_double_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/sincos_eval.h b/libc/src/__support/math/sincos_eval.h index fc741af19551f..3c0bafc5cebf8 100644 --- a/libc/src/__support/math/sincos_eval.h +++ b/libc/src/__support/math/sincos_eval.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIBC_SRC_MATH_GENERIC_SINCOS_EVAL_H -#define LLVM_LIBC_SRC_MATH_GENERIC_SINCOS_EVAL_H +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_SINCOS_EVAL_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_SINCOS_EVAL_H #include "src/__support/FPUtil/PolyEval.h" #include "src/__support/FPUtil/double_double.h" @@ -139,4 +139,4 @@ LIBC_INLINE void sincos_eval(const Float128 &u, Float128 &sin_u, } // namespace LIBC_NAMESPACE_DECL -#endif // LLVM_LIBC_SRC_MATH_GENERIC_SINCOSF_EVAL_H +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_SINCOS_EVAL_H diff --git a/libc/src/__support/math/sincosf.h b/libc/src/__support/math/sincosf.h index b6b6ffeb7e6b0..a6b1cd8ae3010 100644 --- a/libc/src/__support/math/sincosf.h +++ b/libc/src/__support/math/sincosf.h @@ -60,6 +60,7 @@ LIBC_INLINE_VAR constexpr uint32_t EXCEPT_OUTPUTS_COS[N_EXCEPTS][4] = { LIBC_INLINE void sincosf(float x, float *sinp, float *cosp) { using namespace sincosf_internal; + using namespace sincosf_utils_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/sincosf16_utils.h b/libc/src/__support/math/sincosf16_utils.h index 74f21fd0a9dc4..cd91eaf711df2 100644 --- a/libc/src/__support/math/sincosf16_utils.h +++ b/libc/src/__support/math/sincosf16_utils.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIBC_SRC_MATH_GENERIC_SINCOSF16_UTILS_H -#define LLVM_LIBC_SRC_MATH_GENERIC_SINCOSF16_UTILS_H +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_SINCOSF16_UTILS_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_SINCOSF16_UTILS_H #include "src/__support/FPUtil/PolyEval.h" #include "src/__support/FPUtil/nearest_integer.h" @@ -16,13 +16,15 @@ namespace LIBC_NAMESPACE_DECL { +namespace math { + namespace sincosf16_internal { // Lookup table for sin(k * pi / 32) with k = 0, ..., 63. // Table is generated with Sollya as follows: // > display = hexadecimmal; // > for k from 0 to 63 do { round(sin(k * pi/32), SG, RN); }; -constexpr float SIN_K_PI_OVER_32[64] = { +LIBC_INLINE_VAR constexpr float SIN_K_PI_OVER_32[64] = { 0x0.0p0, 0x1.917a6cp-4, 0x1.8f8b84p-3, 0x1.294062p-2, 0x1.87de2ap-2, 0x1.e2b5d4p-2, 0x1.1c73b4p-1, 0x1.44cf32p-1, 0x1.6a09e6p-1, 0x1.8bc806p-1, 0x1.a9b662p-1, 0x1.c38b3p-1, @@ -68,9 +70,9 @@ LIBC_INLINE int32_t range_reduction_sincosf16(float x, float &y) { return static_cast(kd); } -LIBC_INLINE static void sincosf16_poly_eval(int32_t k, float y, float &sin_k, - float &cos_k, float &sin_y, - float &cosm1_y) { +LIBC_INLINE void sincosf16_poly_eval(int32_t k, float y, float &sin_k, + float &cos_k, float &sin_y, + float &cosm1_y) { sin_k = SIN_K_PI_OVER_32[k & 63]; cos_k = SIN_K_PI_OVER_32[(k + 16) & 63]; @@ -111,6 +113,8 @@ LIBC_INLINE void sincospif16_eval(float xf, float &sin_k, float &cos_k, } // namespace sincosf16_internal +} // namespace math + } // namespace LIBC_NAMESPACE_DECL -#endif // LLVM_LIBC_SRC_MATH_GENERIC_SINCOSF16_UTILS_H +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_SINCOSF16_UTILS_H diff --git a/libc/src/__support/math/sincosf_utils.h b/libc/src/__support/math/sincosf_utils.h index b13a39999866d..8fbc8384f9e32 100644 --- a/libc/src/__support/math/sincosf_utils.h +++ b/libc/src/__support/math/sincosf_utils.h @@ -16,21 +16,32 @@ #if defined(LIBC_TARGET_CPU_HAS_FMA_DOUBLE) #include "range_reduction_fma.h" -// using namespace LIBC_NAMESPACE::fma; -using LIBC_NAMESPACE::fma::FAST_PASS_BOUND; -using LIBC_NAMESPACE::fma::large_range_reduction; -using LIBC_NAMESPACE::fma::small_range_reduction; - #else #include "range_reduction.h" -// using namespace LIBC_NAMESPACE::generic; -using LIBC_NAMESPACE::generic::FAST_PASS_BOUND; -using LIBC_NAMESPACE::generic::large_range_reduction; -using LIBC_NAMESPACE::generic::small_range_reduction; #endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE namespace LIBC_NAMESPACE_DECL { +namespace math { + +namespace sincosf_utils_internal { + +#if defined(LIBC_TARGET_CPU_HAS_FMA_DOUBLE) + +// using namespace LIBC_NAMESPACE::fma; +using math::trigonometric_fma_utils_internal::FAST_PASS_BOUND; +using math::trigonometric_fma_utils_internal::large_range_reduction; +using math::trigonometric_fma_utils_internal::small_range_reduction; + +#else + +// using namespace LIBC_NAMESPACE::generic; +using math::trigonometric_func_utils_internal::FAST_PASS_BOUND; +using math::trigonometric_func_utils_internal::large_range_reduction; +using math::trigonometric_func_utils_internal::small_range_reduction; + +#endif // LIBC_TARGET_CPU_HAS_FMA_DOUBLE + // Lookup table for sin(k * pi / 32) with k = 0, ..., 63. // Table is generated with Sollya as follow: // > display = hexadecimal; @@ -120,6 +131,10 @@ LIBC_INLINE void sincospif_eval(double xd, double &sin_k, double &cos_k, sincosf_poly_eval(k, y, sin_k, cos_k, sin_y, cosm1_y); } +} // namespace sincosf_utils_internal + +} // namespace math + } // namespace LIBC_NAMESPACE_DECL #endif // LLVM_LIBC_SRC___SUPPORT_MATH_SINCOSF_UTILS_H diff --git a/libc/src/__support/math/sinf.h b/libc/src/__support/math/sinf.h index 9290444b43619..c61beed749900 100644 --- a/libc/src/__support/math/sinf.h +++ b/libc/src/__support/math/sinf.h @@ -29,7 +29,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static float sinf(float x) { +LIBC_INLINE float sinf(float x) { return math::sincosf_float_eval::sincosf_eval(x); } @@ -51,7 +51,8 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static float sinf(float x) { +LIBC_INLINE float sinf(float x) { + using namespace sincosf_utils_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/sinf16.h b/libc/src/__support/math/sinf16.h index e18d0cfbd262f..ec27c4ec61c53 100644 --- a/libc/src/__support/math/sinf16.h +++ b/libc/src/__support/math/sinf16.h @@ -44,7 +44,7 @@ LIBC_INLINE_VAR constexpr fputil::ExceptValues } // namespace sinf16_internal -LIBC_INLINE static float16 sinf16(float16 x) { +LIBC_INLINE float16 sinf16(float16 x) { using namespace sinf16_internal; using namespace sincosf16_internal; using FPBits = fputil::FPBits; diff --git a/libc/src/__support/math/sinhf.h b/libc/src/__support/math/sinhf.h index e8efc29aeac79..6af34412129fc 100644 --- a/libc/src/__support/math/sinhf.h +++ b/libc/src/__support/math/sinhf.h @@ -20,7 +20,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float sinhf(float x) { +LIBC_INLINE constexpr float sinhf(float x) { using FPBits = typename fputil::FPBits; FPBits xbits(x); uint32_t x_abs = xbits.abs().uintval(); diff --git a/libc/src/__support/math/sinhf16.h b/libc/src/__support/math/sinhf16.h index df9b82c967ae4..19ff5a3e12423 100644 --- a/libc/src/__support/math/sinhf16.h +++ b/libc/src/__support/math/sinhf16.h @@ -28,7 +28,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 sinhf16(float16 x) { +LIBC_INLINE constexpr float16 sinhf16(float16 x) { #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS constexpr fputil::ExceptValues SINHF16_EXCEPTS_POS = {{ diff --git a/libc/src/__support/math/sinpif.h b/libc/src/__support/math/sinpif.h index 8f1570399f6c4..926e17ba6203c 100644 --- a/libc/src/__support/math/sinpif.h +++ b/libc/src/__support/math/sinpif.h @@ -21,7 +21,8 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static float sinpif(float x) { +LIBC_INLINE float sinpif(float x) { + using namespace sincosf_utils_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/math/sqrt.h b/libc/src/__support/math/sqrt.h index 3faa62dea8eb1..baef03fca9587 100644 --- a/libc/src/__support/math/sqrt.h +++ b/libc/src/__support/math/sqrt.h @@ -15,7 +15,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static double sqrt(double x) { return fputil::sqrt(x); } +LIBC_INLINE double sqrt(double x) { return fputil::sqrt(x); } } // namespace math diff --git a/libc/src/__support/math/sqrtf.h b/libc/src/__support/math/sqrtf.h index 4818dfee50a74..aaa25d91ee820 100644 --- a/libc/src/__support/math/sqrtf.h +++ b/libc/src/__support/math/sqrtf.h @@ -15,7 +15,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static float sqrtf(float x) { return fputil::sqrt(x); } +LIBC_INLINE float sqrtf(float x) { return fputil::sqrt(x); } } // namespace math diff --git a/libc/src/__support/math/sqrtf128.h b/libc/src/__support/math/sqrtf128.h new file mode 100644 index 0000000000000..d5b54b724c259 --- /dev/null +++ b/libc/src/__support/math/sqrtf128.h @@ -0,0 +1,454 @@ +//===-- Implementation header of sqrtf128 ---------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC___SUPPORT_MATH_SQRTF128_H +#define LLVM_LIBC_SRC___SUPPORT_MATH_SQRTF128_H + +#include "include/llvm-libc-types/float128.h" + +#ifdef LIBC_TYPES_HAS_FLOAT128 + +#include "src/__support/CPP/bit.h" +#include "src/__support/FPUtil/FEnvImpl.h" +#include "src/__support/FPUtil/FPBits.h" +#include "src/__support/FPUtil/rounding_mode.h" +#include "src/__support/common.h" +#include "src/__support/macros/optimization.h" +#include "src/__support/uint128.h" + +// Compute sqrtf128 with correct rounding for all rounding modes using integer +// arithmetic by Alexei Sibidanov (sibid@uvic.ca): +// https://github.com/sibidanov/llvm-project/tree/as_sqrt_v2 +// https://github.com/sibidanov/llvm-project/tree/as_sqrt_v3 +// TODO: Update the reference once Alexei's implementation is in the CORE-MATH +// project. https://github.com/llvm/llvm-project/issues/126794 + +// Let the input be expressed as x = 2^e * m_x, +// - Step 1: Range reduction +// Let x_reduced = 2^(e % 2) * m_x, +// Then sqrt(x) = 2^(e / 2) * sqrt(x_reduced), with +// 1 <= x_reduced < 4. +// - Step 2: Polynomial approximation +// Approximate 1/sqrt(x_reduced) using polynomial approximation with the +// result errors bounded by: +// |r0 - 1/sqrt(x_reduced)| < 2^-32. +// The computations are done in uint64_t. +// - Step 3: First Newton iteration +// Let the scaled error defined by: +// h0 = r0^2 * x_reduced - 1. +// Then we compute the first Newton iteration: +// r1 = r0 - r0 * h0 / 2. +// The result is then bounded by: +// |r1 - 1 / sqrt(x_reduced)| < 2^-62. +// - Step 4: Second Newton iteration +// We calculate the scaled error from Step 3: +// h1 = r1^2 * x_reduced - 1. +// Then the second Newton iteration is computed by: +// r2 = x_reduced * (r1 - r1 * h0 / 2) +// ~ x_reduced * (1/sqrt(x_reduced)) = sqrt(x_reduced) +// - Step 5: Perform rounding test and correction if needed. +// Rounding correction is done by computing the exact rounding errors: +// x_reduced - r2^2. + +namespace LIBC_NAMESPACE_DECL { +namespace math { + +namespace sqrtf128_internal { + +using FPBits = fputil::FPBits; + +template LIBC_INLINE constexpr T prod_hi(T, U); + +// Get high part of integer multiplications. +// Use template to prevent implicit conversion. +template <> +LIBC_INLINE constexpr uint64_t prod_hi(uint64_t x, uint64_t y) { + return static_cast( + (static_cast(x) * static_cast(y)) >> 64); +} + +// Get high part of unsigned 128x64 bit multiplication. +template <> +LIBC_INLINE constexpr UInt128 prod_hi(UInt128 x, + uint64_t y) { + uint64_t x_lo = static_cast(x); + uint64_t x_hi = static_cast(x >> 64); + UInt128 xyl = static_cast(x_lo) * static_cast(y); + UInt128 xyh = static_cast(x_hi) * static_cast(y); + return xyh + (xyl >> 64); +} + +// Get high part of signed 64x64 bit multiplication. +template <> +LIBC_INLINE constexpr int64_t prod_hi(int64_t x, int64_t y) { + return static_cast( + (static_cast(x) * static_cast(y)) >> 64); +} + +// Get high 128-bit part of unsigned 128x128 bit multiplication. +template <> +LIBC_INLINE constexpr UInt128 prod_hi(UInt128 x, UInt128 y) { + uint64_t x_lo = static_cast(x); + uint64_t x_hi = static_cast(x >> 64); + uint64_t y_lo = static_cast(y); + uint64_t y_hi = static_cast(y >> 64); + + UInt128 xh_yh = static_cast(x_hi) * static_cast(y_hi); + UInt128 xh_yl = static_cast(x_hi) * static_cast(y_lo); + UInt128 xl_yh = static_cast(x_lo) * static_cast(y_hi); + + xh_yh += xh_yl >> 64; + + return xh_yh + (xl_yh >> 64); +} + +// Get high 128-bit part of mixed sign 128x128 bit multiplication. +template <> +LIBC_INLINE constexpr Int128 prod_hi(Int128 x, UInt128 y) { + UInt128 mask = static_cast(x >> 127); + UInt128 negative_part = y & mask; + UInt128 prod = prod_hi(static_cast(x), y); + return static_cast(prod - negative_part); +} + +// Newton-Raphson first order step to improve accuracy of the result. +// For the initial approximation r0 ~ 1/sqrt(x), let +// h = r0^2 * x - 1 +// be its scaled error. Then the first-order Newton-Raphson iteration is: +// r1 = r0 - r0 * h / 2 +// which has error bounded by: +// |r1 - 1/sqrt(x)| < h^2 / 2. +LIBC_INLINE constexpr uint64_t rsqrt_newton_raphson(uint64_t m, uint64_t r) { + uint64_t r2 = prod_hi(r, r); + // h = r0^2*x - 1. + int64_t h = static_cast(prod_hi(m, r2) + r2); + // hr = r * h / 2 + int64_t hr = prod_hi(h, static_cast(r >> 1)); + return r - hr; +} + +#ifdef LIBC_MATH_HAS_SMALL_TABLES +// Degree-12 minimax polynomials for 1/sqrt(x) on [1, 2]. +LIBC_INLINE_VAR constexpr uint32_t RSQRT_COEFFS[12] = { + 0xb5947a4a, 0x2d651e32, 0x9ad50532, 0x2d28d093, 0x0d8be653, 0x04239014, + 0x01492449, 0x0066ff7d, 0x001e74a1, 0x000984cc, 0x00049abc, 0x00018340, +}; + +LIBC_INLINE constexpr uint64_t rsqrt_approx(uint64_t m) { + int64_t x = static_cast(m) ^ (uint64_t(1) << 63); + int64_t x_26 = x >> 2; + int64_t z = x >> 31; + + if (LIBC_UNLIKELY(z <= -4294967296)) + return ~(m >> 1); + + uint64_t x2 = static_cast(z) * static_cast(z); + uint64_t x2_26 = x2 >> 5; + x2 >>= 32; + // Calculate the odd part of the polynomial using Horner's method. + uint64_t c0 = RSQRT_COEFFS[8] + ((x2 * RSQRT_COEFFS[10]) >> 32); + uint64_t c1 = RSQRT_COEFFS[6] + ((x2 * c0) >> 32); + uint64_t c2 = RSQRT_COEFFS[4] + ((x2 * c1) >> 32); + uint64_t c3 = RSQRT_COEFFS[2] + ((x2 * c2) >> 32); + uint64_t c4 = RSQRT_COEFFS[0] + ((x2 * c3) >> 32); + uint64_t odd = + static_cast((x >> 34) * static_cast(c4 >> 3)) + x_26; + // Calculate the even part of the polynomial using Horner's method. + uint64_t d0 = RSQRT_COEFFS[9] + ((x2 * RSQRT_COEFFS[11]) >> 32); + uint64_t d1 = RSQRT_COEFFS[7] + ((x2 * d0) >> 32); + uint64_t d2 = RSQRT_COEFFS[5] + ((x2 * d1) >> 32); + uint64_t d3 = RSQRT_COEFFS[3] + ((x2 * d2) >> 32); + uint64_t d4 = RSQRT_COEFFS[1] + ((x2 * d3) >> 32); + uint64_t even = 0xd105eb806655d608ul + ((x2 * d4) >> 6) + x2_26; + + uint64_t r = even - odd; // error < 1.5e-10 + // Newton-Raphson first order step to improve accuracy of the result to almost + // 64 bits. + return rsqrt_newton_raphson(m, r); +} + +#else +// Cubic minimax polynomials for 1/sqrt(x) on [1 + k/64, 1 + (k + 1)/64] +// for k = 0..63. +LIBC_INLINE_VAR constexpr uint32_t RSQRT_COEFFS[64][4] = { + {0xffffffff, 0xfffff780, 0xbff55815, 0x9bb5b6e7}, + {0xfc0bd889, 0xfa1d6e7d, 0xb8a95a89, 0x938bf8f0}, + {0xf82ec882, 0xf473bea9, 0xb1bf4705, 0x8bed0079}, + {0xf467f280, 0xeefff2a1, 0xab309d4a, 0x84cdb431}, + {0xf0b6848c, 0xe9bf46f4, 0xa4f76232, 0x7e24037b}, + {0xed19b75e, 0xe4af2628, 0x9f0e1340, 0x77e6ca62}, + {0xe990cdad, 0xdfcd2521, 0x996f9b96, 0x720db8df}, + {0xe61b138e, 0xdb16ffde, 0x94174a00, 0x6c913cff}, + {0xe2b7dddf, 0xd68a967b, 0x8f00c812, 0x676a6f92}, + {0xdf6689b7, 0xd225ea80, 0x8a281226, 0x62930308}, + {0xdc267bea, 0xcde71c63, 0x8589702c, 0x5e05343e}, + {0xd8f7208e, 0xc9cc6948, 0x81216f2e, 0x59bbbcf8}, + {0xd5d7ea91, 0xc5d428ee, 0x7cecdb76, 0x55b1c7d6}, + {0xd2c8534e, 0xc1fccbc9, 0x78e8bb45, 0x51e2e592}, + {0xcfc7da32, 0xbe44d94a, 0x75124a0a, 0x4e4b0369}, + {0xccd6045f, 0xbaaaee41, 0x7166f40f, 0x4ae66284}, + {0xc9f25c5c, 0xb72dbb69, 0x6de45288, 0x47b19045}, + {0xc71c71c7, 0xb3cc040f, 0x6a882804, 0x44a95f5f}, + {0xc453d90f, 0xb0849cd4, 0x67505d2a, 0x41cae1a0}, + {0xc1982b2e, 0xad566a85, 0x643afdc8, 0x3f13625c}, + {0xbee9056f, 0xaa406113, 0x6146361f, 0x3c806169}, + {0xbc46092e, 0xa7418293, 0x5e70506d, 0x3a0f8e8e}, + {0xb9aedba5, 0xa458de58, 0x5bb7b2b1, 0x37bec572}, + {0xb72325b7, 0xa1859022, 0x591adc9a, 0x358c09e2}, + {0xb4a293c2, 0x9ec6bf52, 0x569865a7, 0x33758476}, + {0xb22cd56d, 0x9c1b9e36, 0x542efb6a, 0x31797f8a}, + {0xafc19d86, 0x9983695c, 0x51dd5ffb, 0x2f96647a}, + {0xad60a1d1, 0x96fd66f7, 0x4fa2687c, 0x2dcab91f}, + {0xab099ae9, 0x9488e64b, 0x4d7cfbc9, 0x2c151d8a}, + {0xa8bc441a, 0x92253f20, 0x4b6c1139, 0x2a7449ef}, + {0xa6785b42, 0x8fd1d14a, 0x496eaf82, 0x28e70cc3}, + {0xa43da0ae, 0x8d8e042a, 0x4783eba7, 0x276c4900}, + {0xa20bd701, 0x8b594648, 0x45aae80a, 0x2602f493}, + {0x9fe2c315, 0x89330ce4, 0x43e2d382, 0x24aa16ec}, + {0x9dc22be4, 0x871ad399, 0x422ae88c, 0x2360c7af}, + {0x9ba9da6c, 0x85101c05, 0x40826c88, 0x22262d7b}, + {0x99999999, 0x83126d70, 0x3ee8af07, 0x20f97cd2}, + {0x97913630, 0x81215480, 0x3d5d0922, 0x1fd9f714}, + {0x95907eb8, 0x7f3c62ef, 0x3bdedce0, 0x1ec6e994}, + {0x93974369, 0x7d632f45, 0x3a6d94a9, 0x1dbfacbb}, + {0x91a55615, 0x7b955498, 0x3908a2be, 0x1cc3a33b}, + {0x8fba8a1c, 0x79d2724e, 0x37af80bf, 0x1bd23960}, + {0x8dd6b456, 0x781a2be4, 0x3661af39, 0x1aeae458}, + {0x8bf9ab07, 0x766c28ba, 0x351eb539, 0x1a0d21a2}, + {0x8a2345cc, 0x74c813dd, 0x33e61feb, 0x19387676}, + {0x88535d90, 0x732d9bdc, 0x32b7823a, 0x186c6f3e}, + {0x8689cc7e, 0x719c7297, 0x3192747d, 0x17a89f21}, + {0x84c66df1, 0x70144d19, 0x30769424, 0x16ec9f89}, + {0x83091e6a, 0x6e94e36c, 0x2f63836f, 0x16380fbf}, + {0x8151bb87, 0x6d1df079, 0x2e58e925, 0x158a9484}, + {0x7fa023f1, 0x6baf31de, 0x2d567053, 0x14e3d7ba}, + {0x7df43758, 0x6a4867d3, 0x2c5bc811, 0x1443880e}, + {0x7c4dd664, 0x68e95508, 0x2b68a346, 0x13a958ab}, + {0x7aace2b0, 0x6791be86, 0x2a7cb871, 0x131500ee}, + {0x79113ebc, 0x66416b95, 0x2997c17a, 0x12863c29}, + {0x777acde8, 0x64f825a1, 0x28b97b82, 0x11fcc95c}, + {0x75e9746a, 0x63b5b822, 0x27e1a6b4, 0x11786b03}, + {0x745d1746, 0x6279f081, 0x2710061d, 0x10f8e6da}, + {0x72d59c46, 0x61449e06, 0x26445f86, 0x107e05ac}, + {0x7152e9f4, 0x601591be, 0x257e7b4d, 0x10079327}, + {0x6fd4e793, 0x5eec9e6b, 0x24be2445, 0x0f955da9}, + {0x6e5b7d16, 0x5dc9986e, 0x24032795, 0x0f273620}, + {0x6ce6931d, 0x5cac55b7, 0x234d5496, 0x0ebcefdb}, + {0x6b7612ec, 0x5b94adb2, 0x229c7cbc, 0x0e56606e}, +}; + +// Approximate rsqrt with cubic polynomials. +// The range [1,2] is splitted into 64 equal sub-ranges and the reciprocal +// square root is approximated by a cubic polynomial by the minimax method in +// each subrange. The approximation accuracy fits into 32-33 bits and thus it is +// natural to round coefficients into 32 bit. The constant coefficient can be +// rounded to 33 bits since the most significant bit is always 1 and implicitly +// assumed in the table. +LIBC_INLINE constexpr uint64_t rsqrt_approx(uint64_t m) { + // ULP(m) = 2^-64. + // Use the top 6 bits as index for looking up polynomial coeffs. + uint64_t indx = m >> 58; + + uint64_t c0 = static_cast(RSQRT_COEFFS[indx][0]); + c0 <<= 31; // to 64 bit with the space for the implicit bit + c0 |= 1ull << 63; // add implicit bit + + uint64_t c1 = static_cast(RSQRT_COEFFS[indx][1]); + c1 <<= 25; // to 64 bit format + + uint64_t c2 = static_cast(RSQRT_COEFFS[indx][2]); + uint64_t c3 = static_cast(RSQRT_COEFFS[indx][3]); + + uint64_t d = (m << 6) >> 32; // local coordinate in the subrange [0, 2^32] + uint64_t d2 = (d * d) >> 32; // square of the local coordinate + uint64_t re = c0 + (d2 * c2 >> 13); // even part of the polynomial (positive) + uint64_t ro = d * ((c1 + ((d2 * c3) >> 19)) >> 26) >> + 6; // odd part of the polynomial (negative) + uint64_t r = re - ro; // maximal error < 1.55e-10 and it is less than 2^-32 + // Newton-Raphson first order step to improve accuracy of the result to almost + // 64 bits. + r = rsqrt_newton_raphson(m, r); + // Adjust in the unlucky case x~1; + if (LIBC_UNLIKELY(!r)) + --r; + return r; +} +#endif // LIBC_MATH_HAS_SMALL_TABLES + +} // namespace sqrtf128_internal + +LIBC_INLINE float128 sqrtf128(float128 x) { + using namespace sqrtf128_internal; + using FPBits = fputil::FPBits; + // Get rounding mode. + uint32_t rm = fputil::get_round(); + + FPBits xbits(x); + UInt128 x_u = xbits.uintval(); + // Bring leading bit of the mantissa to the highest bit. + // ulp(x_frac) = 2^-128. + UInt128 x_frac = xbits.get_mantissa() << (FPBits::EXP_LEN + 1); + + int sign_exp = static_cast(x_u >> FPBits::FRACTION_LEN); + + if (LIBC_UNLIKELY(sign_exp == 0 || sign_exp >= 0x7fff)) { + // Special cases: NAN, inf, negative numbers + if (sign_exp >= 0x7fff) { + // x = -0 or x = inf + if (xbits.is_zero() || xbits == xbits.inf()) + return x; + // x is nan + if (xbits.is_nan()) { + // pass through quiet nan + if (xbits.is_quiet_nan()) + return x; + // transform signaling nan to quiet and return + return xbits.quiet_nan().get_val(); + } + // x < 0 or x = -inf + fputil::set_errno_if_required(EDOM); + fputil::raise_except_if_required(FE_INVALID); + return xbits.quiet_nan().get_val(); + } + // Now x is subnormal or x = +0. + + // x is +0. + if (x_frac == 0) + return x; + + // Normalize subnormal inputs. + sign_exp = -cpp::countl_zero(x_frac); + int normal_shifts = 1 - sign_exp; + x_frac <<= normal_shifts; + } + + // For sign_exp = biased exponent of x = real_exponent + 16383, + // let f be the real exponent of the output: + // f = floor(real_exponent / 2) + // Then: + // floor((sign_exp + 1) / 2) = f + 8192 + // Hence, the biased exponent of the final result is: + // f + 16383 = floor((sign_exp + 1) / 2) + 8191. + // Since the output mantissa will include the hidden bit, we can define the + // output exponent part: + // e2 = floor((sign_exp + 1) / 2) + 8190 + unsigned i = static_cast(1 - (sign_exp & 1)); + uint32_t q2 = (sign_exp + 1) >> 1; + // Exponent of the final result + uint32_t e2 = q2 + 8190; + + constexpr uint64_t RSQRT_2[2] = {~0ull, + 0xb504f333f9de6484 /* 2^64/sqrt(2) */}; + + // Approximate 1/sqrt(1 + x_frac) + // Error: |r_1 - 1/sqrt(x)| < 2^-62. + uint64_t r1 = rsqrt_approx(static_cast(x_frac >> 64)); + // Adjust for the even/odd exponent. + uint64_t r2 = prod_hi(r1, RSQRT_2[i]); + unsigned shift = 2 - i; + + // Normalized input: + // 1 <= x_reduced < 4 + UInt128 x_reduced = (x_frac >> shift) | (UInt128(1) << (126 + i)); + // With r2 ~ 1/sqrt(x) up to 2^-63, we perform another round of Newton-Raphson + // iteration: + // r3 = r2 - r2 * h / 2, + // for h = r2^2 * x - 1. + // Then: + // sqrt(x) = x * (1 / sqrt(x)) + // ~ x * r3 + // = x * (r2 - r2 * h / 2) + // = (x * r2) - (x * r2) * h / 2 + UInt128 sx = prod_hi(x_reduced, r2); + UInt128 h = prod_hi(sx, r2) << 2; + UInt128 ds = static_cast(prod_hi(static_cast(h), sx)); + UInt128 v = (sx << 1) - ds; + + uint32_t nrst = rm == FE_TONEAREST; + // The result lies within (-2,5) of true square root so we now + // test that we can correctly round the result taking into account + // the rounding mode. + // Check the lowest 14 bits (by clearing and sign-extending the top + // 32 - 14 = 18 bits). + int dd = (static_cast(v) << 18) >> 18; + + if (LIBC_UNLIKELY(dd < 4 && dd >= -8)) { // can round correctly? + // m is almost the final result it can be only 1 ulp off so we + // just need to test both possibilities. We square it and + // compare with the initial argument. + UInt128 m = v >> 15; + UInt128 m2 = m * m; + // The difference of the squared result and the argument + Int128 t0 = static_cast(m2 - (x_reduced << 98)); + if (t0 == 0) { + // the square root is exact + v = m << 15; + } else { + // Add +-1 ulp to m depend on the sign of the difference. Here + // we do not need to square again since (m+1)^2 = m^2 + 2*m + + // 1 so just need to add shifted m and 1. + Int128 t1 = t0; + Int128 sgn = t0 >> 127; // sign of the difference + Int128 m_xor_sgn = static_cast(m << 1) ^ sgn; + t1 -= m_xor_sgn; + t1 += Int128(1) + sgn; + + Int128 sgn1 = t1 >> 127; + if (LIBC_UNLIKELY(sgn == sgn1)) { + t0 = t1; + v -= sgn << 15; + t1 -= m_xor_sgn; + t1 += Int128(1) + sgn; + } + + if (t1 == 0) { + // 1 ulp offset brings again an exact root + v = (m - static_cast((sgn << 1) + 1)) << 15; + } else { + t1 += t0; + Int128 side = t1 >> 127; // select what is closer m or m+-1 + v &= ~UInt128(0) << 15; // wipe the fractional bits + v -= ((sgn & side) | (~sgn & 1)) << (15 + static_cast(side)); + v |= 1; // add sticky bit since we cannot have an exact mid-point + // situation + } + } + } + + unsigned frac = static_cast(v) & 0x7fff; // fractional part + unsigned rnd = 0; // round bit + if (LIBC_LIKELY(nrst != 0)) { + rnd = frac >> 14; // round to nearest tie to even + } else if (rm == FE_UPWARD) { + rnd = !!frac; // round up + } else { + rnd = 0; // round down or round to zero + } + + v >>= 15; // position mantissa + v += rnd; // round + + // Set inexact flag only if square root is inexact + // TODO: We will have to raise FE_INEXACT most of the time, but this + // operation is very costly, especially in x86-64, since technically, it + // needs to synchronize both SSE and x87 flags. Need to investigate + // further to see how we can make this performant. + // https://github.com/llvm/llvm-project/issues/126753 + + // if(frac) fputil::raise_except_if_required(FE_INEXACT); + + v += static_cast(e2) << FPBits::FRACTION_LEN; // place exponent + return cpp::bit_cast(v); +} + +} // namespace math +} // namespace LIBC_NAMESPACE_DECL + +#endif // LIBC_TYPES_HAS_FLOAT128 + +#endif // LLVM_LIBC_SRC___SUPPORT_MATH_SQRTF128_H diff --git a/libc/src/__support/math/sqrtf16.h b/libc/src/__support/math/sqrtf16.h index 8c9e1e65177de..a1a11a7574ced 100644 --- a/libc/src/__support/math/sqrtf16.h +++ b/libc/src/__support/math/sqrtf16.h @@ -19,7 +19,7 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE static constexpr float16 sqrtf16(float16 x) { +LIBC_INLINE constexpr float16 sqrtf16(float16 x) { return fputil::sqrt(x); } diff --git a/libc/src/__support/math/tan.h b/libc/src/__support/math/tan.h index f7566bda360ea..27cd4b7a044ab 100644 --- a/libc/src/__support/math/tan.h +++ b/libc/src/__support/math/tan.h @@ -38,8 +38,7 @@ namespace tan_internal { using DoubleDouble = fputil::DoubleDouble; using Float128 = typename fputil::DyadicFloat<128>; -LIBC_INLINE static double tan_eval(const DoubleDouble &u, - DoubleDouble &result) { +LIBC_INLINE double tan_eval(const DoubleDouble &u, DoubleDouble &result) { // Evaluate tan(y) = tan(x - k * (pi/128)) // We use the degree-9 Taylor approximation: // tan(y) ~ P(y) = y + y^3/3 + 2*y^5/15 + 17*y^7/315 + 62*y^9/2835 @@ -77,7 +76,7 @@ LIBC_INLINE static double tan_eval(const DoubleDouble &u, #ifndef LIBC_MATH_HAS_SKIP_ACCURATE_PASS // Accurate evaluation of tan for small u. -[[maybe_unused]] LIBC_INLINE static Float128 tan_eval(const Float128 &u) { +[[maybe_unused]] LIBC_INLINE Float128 tan_eval(const Float128 &u) { Float128 u_sq = fputil::quick_mul(u, u); // tan(x) ~ x + x^3/3 + x^5 * 2/15 + x^7 * 17/315 + x^9 * 62/2835 + @@ -124,7 +123,7 @@ LIBC_INLINE static double tan_eval(const DoubleDouble &u, } // namespace tan_internal -LIBC_INLINE static double tan(double x) { +LIBC_INLINE double tan(double x) { using namespace tan_internal; using namespace math::range_reduction_double_internal; using FPBits = typename fputil::FPBits; diff --git a/libc/src/__support/math/tanf.h b/libc/src/__support/math/tanf.h index 139de3c593ad4..3a1d8e8bd53b6 100644 --- a/libc/src/__support/math/tanf.h +++ b/libc/src/__support/math/tanf.h @@ -49,7 +49,8 @@ LIBC_INLINE_VAR constexpr fputil::ExceptValues TANF_EXCEPTS{{ } // namespace tanf_internal -LIBC_INLINE static float tanf(float x) { +LIBC_INLINE float tanf(float x) { + using namespace sincosf_utils_internal; using namespace tanf_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/__support/wctype/CMakeLists.txt b/libc/src/__support/wctype/CMakeLists.txt index 48d9cd9d056c7..fcd4b777b2203 100644 --- a/libc/src/__support/wctype/CMakeLists.txt +++ b/libc/src/__support/wctype/CMakeLists.txt @@ -1,7 +1,9 @@ -add_header_library( +add_object_library( wctype_classification_utils HDRS wctype_classification_utils.h + SRCS + wctype_classification_utils.cpp DEPENDS libc.hdr.types.wchar_t libc.hdr.stdint_proxy diff --git a/libc/src/__support/wctype/wctype_classification_utils.cpp b/libc/src/__support/wctype/wctype_classification_utils.cpp new file mode 100644 index 0000000000000..d3d672a579e85 --- /dev/null +++ b/libc/src/__support/wctype/wctype_classification_utils.cpp @@ -0,0 +1,3681 @@ +//===-- Lookup tables for wctype classification functions -------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// DO NOT EDIT MANUALLY. +// This file is generated by libc/utils/wctype_utils scripts. + +#include "wctype_classification_utils.h" + +namespace LIBC_NAMESPACE_DECL { + +// Level 1 table: indexed by (codepoint >> 8), stores level2 block offsets +const uint16_t LEVEL1[LEVEL1_SIZE] = { + 0, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, + 2816, 3072, 3328, 3584, 3840, 4096, 4352, 4608, 4864, 5120, 4352, + 5376, 5632, 5888, 6144, 6400, 6656, 6912, 7168, 7424, 7680, 7936, + 8192, 8448, 8448, 8704, 8448, 8448, 8960, 8448, 8448, 8448, 9216, + 9472, 9728, 9984, 10240, 10496, 10752, 11008, 8448, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 11264, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 11520, + 4352, 11776, 12032, 12288, 12544, 12800, 13056, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, + 4352, 4352, 4352, 4352, 4352, 4352, 13312, 13568, 13568, 13568, 13568, + 13568, 13568, 13568, 13568, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 4352, 14080, 14336, 4352, + 14592, 14848, 15104, 15360, 15616, 15872, 16128, 16384, 16640, 4352, 16896, + 17152, 17408, 17664, 17920, 18176, 18432, 18688, 18944, 19200, 19456, 19712, + 19968, 20224, 20480, 20736, 20992, 21248, 21504, 21760, 22016, 22272, 22528, + 22784, 23040, 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13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, + 13824, 13824, 13824, 13824, 13824, 13824, 38912}; + +// Level 2 table: blocks of 256 property flags +const uint8_t LEVEL2[LEVEL2_SIZE] = { + 0x40, 0x40, 0x40, 0x40, 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a/libc/src/__support/wctype/wctype_classification_utils.h +++ b/libc/src/__support/wctype/wctype_classification_utils.h @@ -39,3673 +39,13 @@ LIBC_INLINE_VAR constexpr uint16_t LEVEL1_SIZE = 4352; LIBC_INLINE_VAR constexpr uint16_t LEVEL2_SIZE = 39168; // Level 1 table: indexed by (codepoint >> 8), stores level2 block offsets -LIBC_INLINE_VAR constexpr uint16_t level1[LEVEL1_SIZE] = { - 0, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, - 2816, 3072, 3328, 3584, 3840, 4096, 4352, 4608, 4864, 5120, 4352, - 5376, 5632, 5888, 6144, 6400, 6656, 6912, 7168, 7424, 7680, 7936, - 8192, 8448, 8448, 8704, 8448, 8448, 8960, 8448, 8448, 8448, 9216, - 9472, 9728, 9984, 10240, 10496, 10752, 11008, 8448, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 11264, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 11520, - 4352, 11776, 12032, 12288, 12544, 12800, 13056, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 13312, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13824, 13824, 13824, 13824, 13824, 13824, 13824, - 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, - 13824, 13824, 13824, 13824, 13824, 13824, 13824, 4352, 14080, 14336, 4352, - 14592, 14848, 15104, 15360, 15616, 15872, 16128, 16384, 16640, 4352, 16896, - 17152, 17408, 17664, 17920, 18176, 18432, 18688, 18944, 19200, 19456, 19712, - 19968, 20224, 20480, 20736, 20992, 21248, 21504, 21760, 22016, 22272, 22528, - 22784, 23040, 4352, 4352, 4352, 23296, 23552, 23808, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 24064, 4352, 4352, 4352, 4352, - 24320, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 24576, 4352, 4352, 24832, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 25088, 13568, 13568, 13568, 13568, 13568, 13568, 4352, 4352, 25344, - 25600, 13568, 25856, 26112, 26368, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 26624, 26880, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 27136, 4352, 27392, 27648, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 27904, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 28160, 8448, - 28416, 28672, 28928, 29184, 29440, 29696, 29952, 30208, 30464, 30720, 8448, - 8448, 30976, 13568, 13568, 13568, 13568, 31232, 31488, 31744, 32000, 13568, - 32256, 32512, 32768, 33024, 33280, 33536, 13568, 13568, 33792, 34048, 34304, - 13568, 34560, 34816, 35072, 8448, 8448, 8448, 35328, 35584, 35840, 8448, - 36096, 36352, 13568, 13568, 13568, 13568, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 36608, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 36864, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 37120, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 37376, - 4352, 4352, 37632, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 4352, 4352, 37888, 13568, 13568, 13568, 13568, 13568, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 38144, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, 4352, - 4352, 4352, 4352, 4352, 4352, 4352, 38400, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, 13568, - 13568, 13568, 13568, 13568, 13568, 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13824, - 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, 13824, - 13824, 13824, 13824, 13824, 13824, 13824, 38912}; +extern const uint16_t LEVEL1[LEVEL1_SIZE]; // Level 2 table: blocks of 256 property flags -LIBC_INLINE_VAR constexpr uint8_t level2[LEVEL2_SIZE] = { - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x68, 0x48, 0x48, - 0x48, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x38, 0x90, 0x90, 0x90, - 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x90, 0x90, - 0x90, 0x90, 0x90, 0x90, 0x90, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, - 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, - 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x90, 0x90, 0x90, 0x90, 0x90, - 0x90, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x90, 0x90, 0x90, 0x90, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, - 0x40, 0x40, 0x40, 0x40, 0x10, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, - 0x90, 0x90, 0x14, 0x90, 0x90, 0x00, 0x90, 0x90, 0x90, 0x90, 0x10, 0x10, - 0x90, 0x16, 0x90, 0x90, 0x90, 0x10, 0x14, 0x90, 0x10, 0x10, 0x10, 0x90, - 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, - 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x90, - 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x90, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, - 0x16, 0x15, 0x16, 0x15, 0x16, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x16, - 0x16, 0x15, 0x15, 0x16, 0x15, 0x16, 0x15, 0x15, 0x16, 0x15, 0x15, 0x15, - 0x16, 0x16, 0x15, 0x15, 0x15, 0x15, 0x16, 0x15, 0x15, 0x16, 0x15, 0x15, - 0x15, 0x16, 0x16, 0x16, 0x15, 0x15, 0x16, 0x15, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x15, 0x16, 0x15, 0x16, 0x16, 0x15, 0x16, 0x15, 0x15, - 0x16, 0x15, 0x15, 0x15, 0x16, 0x15, 0x16, 0x15, 0x15, 0x16, 0x16, 0x14, - 0x15, 0x16, 0x16, 0x16, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x16, 0x15, - 0x15, 0x16, 0x15, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, - 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x16, 0x15, 0x15, 0x16, 0x15, 0x16, 0x15, 0x15, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x15, 0x15, 0x16, 0x15, 0x15, 0x16, - 0x16, 0x15, 0x16, 0x15, 0x15, 0x15, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x14, 0x14, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, - 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x90, 0x90, - 0x90, 0x90, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, - 0x14, 0x14, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, - 0x90, 0x90, 0x90, 0x90, 0x14, 0x14, 0x14, 0x14, 0x14, 0x90, 0x90, 0x90, - 0x90, 0x90, 0x90, 0x90, 0x14, 0x90, 0x14, 0x90, 0x90, 0x90, 0x90, 0x90, - 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x15, 0x16, 0x15, 0x16, 0x14, 0x90, 0x15, 0x16, - 0x00, 0x00, 0x14, 0x16, 0x16, 0x16, 0x90, 0x15, 0x00, 0x00, 0x00, 0x00, - 0x90, 0x90, 0x15, 0x90, 0x15, 0x15, 0x15, 0x00, 0x15, 0x00, 0x15, 0x15, - 0x16, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, - 0x15, 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0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, - 0x16, 0x16, 0x16, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x90, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, - 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, 0x15, 0x16, - 0x15, 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0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00}; +extern const uint8_t LEVEL2[LEVEL2_SIZE]; // Returns the Unicode property flag for a given wide character. -LIBC_INLINE constexpr uint8_t lookup_properties(const wchar_t wc) { +LIBC_INLINE uint8_t lookup_properties(const wchar_t wc) { // Out of Unicode range if (static_cast(wc) > 0x10FFFF) { return 0; @@ -3714,11 +54,11 @@ LIBC_INLINE constexpr uint8_t lookup_properties(const wchar_t wc) { uint16_t l1_idx = static_cast(wc >> 8); LIBC_ASSERT(l1_idx < LEVEL1_SIZE); - uint16_t l2_offset = level1[l1_idx]; + uint16_t l2_offset = LEVEL1[l1_idx]; uint16_t l2_idx = l2_offset + (wc & 0xFF); LIBC_ASSERT(l2_idx < LEVEL2_SIZE); - return level2[l2_idx]; + return LEVEL2[l2_idx]; } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/CMakeLists.txt b/libc/src/math/generic/CMakeLists.txt index 1b18388ed60f8..96dc0e7ca4851 100644 --- a/libc/src/math/generic/CMakeLists.txt +++ b/libc/src/math/generic/CMakeLists.txt @@ -3014,13 +3014,7 @@ add_entrypoint_object( HDRS ../sqrtf128.h DEPENDS - libc.src.__support.CPP.bit - libc.src.__support.FPUtil.fenv_impl - libc.src.__support.FPUtil.fp_bits - libc.src.__support.FPUtil.rounding_mode - libc.src.__support.macros.optimization - libc.src.__support.macros.properties.types - libc.src.__support.FPUtil.sqrt + libc.src.__support.math.sqrtf128 ) add_entrypoint_object( @@ -3309,7 +3303,7 @@ add_entrypoint_object( HDRS ../ffmal.h DEPENDS - libc.src.__support.FPUtil.fma + libc.src.__support.math.ffmal ) add_entrypoint_object( @@ -5038,8 +5032,7 @@ add_entrypoint_object( HDRS ../f16fmaf.h DEPENDS - libc.src.__support.macros.properties.types - libc.src.__support.FPUtil.fma + libc.src.__support.math.f16fmaf ) add_entrypoint_object( @@ -5059,8 +5052,7 @@ add_entrypoint_object( HDRS ../f16fmaf128.h DEPENDS - libc.src.__support.macros.properties.types - libc.src.__support.FPUtil.fma + libc.src.__support.math.f16fmaf128 ) add_entrypoint_object( diff --git a/libc/src/math/generic/f16fmaf.cpp b/libc/src/math/generic/f16fmaf.cpp index bd0b56b1ab31b..1c2c6d80934c8 100644 --- a/libc/src/math/generic/f16fmaf.cpp +++ b/libc/src/math/generic/f16fmaf.cpp @@ -7,14 +7,12 @@ //===----------------------------------------------------------------------===// #include "src/math/f16fmaf.h" -#include "src/__support/FPUtil/FMA.h" -#include "src/__support/common.h" -#include "src/__support/macros/config.h" +#include "src/__support/math/f16fmaf.h" namespace LIBC_NAMESPACE_DECL { LLVM_LIBC_FUNCTION(float16, f16fmaf, (float x, float y, float z)) { - return fputil::fma(x, y, z); + return math::f16fmaf(x, y, z); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/f16fmaf128.cpp b/libc/src/math/generic/f16fmaf128.cpp index 5c4823c47e79f..f8bcdc3028972 100644 --- a/libc/src/math/generic/f16fmaf128.cpp +++ b/libc/src/math/generic/f16fmaf128.cpp @@ -7,14 +7,12 @@ //===----------------------------------------------------------------------===// #include "src/math/f16fmaf128.h" -#include "src/__support/FPUtil/FMA.h" -#include "src/__support/common.h" -#include "src/__support/macros/config.h" +#include "src/__support/math/f16fmaf128.h" namespace LIBC_NAMESPACE_DECL { LLVM_LIBC_FUNCTION(float16, f16fmaf128, (float128 x, float128 y, float128 z)) { - return fputil::fma(x, y, z); + return math::f16fmaf128(x, y, z); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/ffmal.cpp b/libc/src/math/generic/ffmal.cpp index d5cd4f763cbe5..c5d0d421c42a4 100644 --- a/libc/src/math/generic/ffmal.cpp +++ b/libc/src/math/generic/ffmal.cpp @@ -7,15 +7,13 @@ //===----------------------------------------------------------------------===// #include "src/math/ffmal.h" -#include "src/__support/FPUtil/FMA.h" -#include "src/__support/common.h" -#include "src/__support/macros/config.h" +#include "src/__support/math/ffmal.h" namespace LIBC_NAMESPACE_DECL { LLVM_LIBC_FUNCTION(float, ffmal, (long double x, long double y, long double z)) { - return fputil::fma(x, y, z); + return math::ffmal(x, y, z); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/sinpif16.cpp b/libc/src/math/generic/sinpif16.cpp index 311e6f989ebf1..94cbd33b76f9e 100644 --- a/libc/src/math/generic/sinpif16.cpp +++ b/libc/src/math/generic/sinpif16.cpp @@ -18,7 +18,7 @@ namespace LIBC_NAMESPACE_DECL { LLVM_LIBC_FUNCTION(float16, sinpif16, (float16 x)) { - using namespace sincosf16_internal; + using namespace math::sincosf16_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/math/generic/sqrtf128.cpp b/libc/src/math/generic/sqrtf128.cpp index 3aa7db8362734..47e4da97581ba 100644 --- a/libc/src/math/generic/sqrtf128.cpp +++ b/libc/src/math/generic/sqrtf128.cpp @@ -7,432 +7,12 @@ //===----------------------------------------------------------------------===// #include "src/math/sqrtf128.h" -#include "src/__support/CPP/bit.h" -#include "src/__support/FPUtil/FEnvImpl.h" -#include "src/__support/FPUtil/FPBits.h" -#include "src/__support/FPUtil/rounding_mode.h" -#include "src/__support/common.h" -#include "src/__support/macros/optimization.h" -#include "src/__support/uint128.h" - -// Compute sqrtf128 with correct rounding for all rounding modes using integer -// arithmetic by Alexei Sibidanov (sibid@uvic.ca): -// https://github.com/sibidanov/llvm-project/tree/as_sqrt_v2 -// https://github.com/sibidanov/llvm-project/tree/as_sqrt_v3 -// TODO: Update the reference once Alexei's implementation is in the CORE-MATH -// project. https://github.com/llvm/llvm-project/issues/126794 - -// Let the input be expressed as x = 2^e * m_x, -// - Step 1: Range reduction -// Let x_reduced = 2^(e % 2) * m_x, -// Then sqrt(x) = 2^(e / 2) * sqrt(x_reduced), with -// 1 <= x_reduced < 4. -// - Step 2: Polynomial approximation -// Approximate 1/sqrt(x_reduced) using polynomial approximation with the -// result errors bounded by: -// |r0 - 1/sqrt(x_reduced)| < 2^-32. -// The computations are done in uint64_t. -// - Step 3: First Newton iteration -// Let the scaled error defined by: -// h0 = r0^2 * x_reduced - 1. -// Then we compute the first Newton iteration: -// r1 = r0 - r0 * h0 / 2. -// The result is then bounded by: -// |r1 - 1 / sqrt(x_reduced)| < 2^-62. -// - Step 4: Second Newton iteration -// We calculate the scaled error from Step 3: -// h1 = r1^2 * x_reduced - 1. -// Then the second Newton iteration is computed by: -// r2 = x_reduced * (r1 - r1 * h0 / 2) -// ~ x_reduced * (1/sqrt(x_reduced)) = sqrt(x_reduced) -// - Step 5: Perform rounding test and correction if needed. -// Rounding correction is done by computing the exact rounding errors: -// x_reduced - r2^2. +#include "src/__support/math/sqrtf128.h" namespace LIBC_NAMESPACE_DECL { -using FPBits = fputil::FPBits; - -namespace { - -template static inline constexpr T prod_hi(T, U); - -// Get high part of integer multiplications. -// Use template to prevent implicit conversion. -template <> -inline constexpr uint64_t prod_hi(uint64_t x, uint64_t y) { - return static_cast( - (static_cast(x) * static_cast(y)) >> 64); -} - -// Get high part of unsigned 128x64 bit multiplication. -template <> -inline constexpr UInt128 prod_hi(UInt128 x, uint64_t y) { - uint64_t x_lo = static_cast(x); - uint64_t x_hi = static_cast(x >> 64); - UInt128 xyl = static_cast(x_lo) * static_cast(y); - UInt128 xyh = static_cast(x_hi) * static_cast(y); - return xyh + (xyl >> 64); -} - -// Get high part of signed 64x64 bit multiplication. -template <> inline constexpr int64_t prod_hi(int64_t x, int64_t y) { - return static_cast( - (static_cast(x) * static_cast(y)) >> 64); -} - -// Get high 128-bit part of unsigned 128x128 bit multiplication. -template <> inline constexpr UInt128 prod_hi(UInt128 x, UInt128 y) { - uint64_t x_lo = static_cast(x); - uint64_t x_hi = static_cast(x >> 64); - uint64_t y_lo = static_cast(y); - uint64_t y_hi = static_cast(y >> 64); - - UInt128 xh_yh = static_cast(x_hi) * static_cast(y_hi); - UInt128 xh_yl = static_cast(x_hi) * static_cast(y_lo); - UInt128 xl_yh = static_cast(x_lo) * static_cast(y_hi); - - xh_yh += xh_yl >> 64; - - return xh_yh + (xl_yh >> 64); -} - -// Get high 128-bit part of mixed sign 128x128 bit multiplication. -template <> -inline constexpr Int128 prod_hi(Int128 x, UInt128 y) { - UInt128 mask = static_cast(x >> 127); - UInt128 negative_part = y & mask; - UInt128 prod = prod_hi(static_cast(x), y); - return static_cast(prod - negative_part); -} - -// Newton-Raphson first order step to improve accuracy of the result. -// For the initial approximation r0 ~ 1/sqrt(x), let -// h = r0^2 * x - 1 -// be its scaled error. Then the first-order Newton-Raphson iteration is: -// r1 = r0 - r0 * h / 2 -// which has error bounded by: -// |r1 - 1/sqrt(x)| < h^2 / 2. -LIBC_INLINE uint64_t rsqrt_newton_raphson(uint64_t m, uint64_t r) { - uint64_t r2 = prod_hi(r, r); - // h = r0^2*x - 1. - int64_t h = static_cast(prod_hi(m, r2) + r2); - // hr = r * h / 2 - int64_t hr = prod_hi(h, static_cast(r >> 1)); - return r - hr; -} - -#ifdef LIBC_MATH_HAS_SMALL_TABLES -// Degree-12 minimax polynomials for 1/sqrt(x) on [1, 2]. -constexpr uint32_t RSQRT_COEFFS[12] = { - 0xb5947a4a, 0x2d651e32, 0x9ad50532, 0x2d28d093, 0x0d8be653, 0x04239014, - 0x01492449, 0x0066ff7d, 0x001e74a1, 0x000984cc, 0x00049abc, 0x00018340, -}; - -LIBC_INLINE uint64_t rsqrt_approx(uint64_t m) { - int64_t x = static_cast(m) ^ (uint64_t(1) << 63); - int64_t x_26 = x >> 2; - int64_t z = x >> 31; - - if (LIBC_UNLIKELY(z <= -4294967296)) - return ~(m >> 1); - - uint64_t x2 = static_cast(z) * static_cast(z); - uint64_t x2_26 = x2 >> 5; - x2 >>= 32; - // Calculate the odd part of the polynomial using Horner's method. - uint64_t c0 = RSQRT_COEFFS[8] + ((x2 * RSQRT_COEFFS[10]) >> 32); - uint64_t c1 = RSQRT_COEFFS[6] + ((x2 * c0) >> 32); - uint64_t c2 = RSQRT_COEFFS[4] + ((x2 * c1) >> 32); - uint64_t c3 = RSQRT_COEFFS[2] + ((x2 * c2) >> 32); - uint64_t c4 = RSQRT_COEFFS[0] + ((x2 * c3) >> 32); - uint64_t odd = - static_cast((x >> 34) * static_cast(c4 >> 3)) + x_26; - // Calculate the even part of the polynomial using Horner's method. - uint64_t d0 = RSQRT_COEFFS[9] + ((x2 * RSQRT_COEFFS[11]) >> 32); - uint64_t d1 = RSQRT_COEFFS[7] + ((x2 * d0) >> 32); - uint64_t d2 = RSQRT_COEFFS[5] + ((x2 * d1) >> 32); - uint64_t d3 = RSQRT_COEFFS[3] + ((x2 * d2) >> 32); - uint64_t d4 = RSQRT_COEFFS[1] + ((x2 * d3) >> 32); - uint64_t even = 0xd105eb806655d608ul + ((x2 * d4) >> 6) + x2_26; - - uint64_t r = even - odd; // error < 1.5e-10 - // Newton-Raphson first order step to improve accuracy of the result to almost - // 64 bits. - return rsqrt_newton_raphson(m, r); -} - -#else -// Cubic minimax polynomials for 1/sqrt(x) on [1 + k/64, 1 + (k + 1)/64] -// for k = 0..63. -constexpr uint32_t RSQRT_COEFFS[64][4] = { - {0xffffffff, 0xfffff780, 0xbff55815, 0x9bb5b6e7}, - {0xfc0bd889, 0xfa1d6e7d, 0xb8a95a89, 0x938bf8f0}, - {0xf82ec882, 0xf473bea9, 0xb1bf4705, 0x8bed0079}, - {0xf467f280, 0xeefff2a1, 0xab309d4a, 0x84cdb431}, - {0xf0b6848c, 0xe9bf46f4, 0xa4f76232, 0x7e24037b}, - {0xed19b75e, 0xe4af2628, 0x9f0e1340, 0x77e6ca62}, - {0xe990cdad, 0xdfcd2521, 0x996f9b96, 0x720db8df}, - {0xe61b138e, 0xdb16ffde, 0x94174a00, 0x6c913cff}, - {0xe2b7dddf, 0xd68a967b, 0x8f00c812, 0x676a6f92}, - {0xdf6689b7, 0xd225ea80, 0x8a281226, 0x62930308}, - {0xdc267bea, 0xcde71c63, 0x8589702c, 0x5e05343e}, - {0xd8f7208e, 0xc9cc6948, 0x81216f2e, 0x59bbbcf8}, - {0xd5d7ea91, 0xc5d428ee, 0x7cecdb76, 0x55b1c7d6}, - {0xd2c8534e, 0xc1fccbc9, 0x78e8bb45, 0x51e2e592}, - {0xcfc7da32, 0xbe44d94a, 0x75124a0a, 0x4e4b0369}, - {0xccd6045f, 0xbaaaee41, 0x7166f40f, 0x4ae66284}, - {0xc9f25c5c, 0xb72dbb69, 0x6de45288, 0x47b19045}, - {0xc71c71c7, 0xb3cc040f, 0x6a882804, 0x44a95f5f}, - {0xc453d90f, 0xb0849cd4, 0x67505d2a, 0x41cae1a0}, - {0xc1982b2e, 0xad566a85, 0x643afdc8, 0x3f13625c}, - {0xbee9056f, 0xaa406113, 0x6146361f, 0x3c806169}, - {0xbc46092e, 0xa7418293, 0x5e70506d, 0x3a0f8e8e}, - {0xb9aedba5, 0xa458de58, 0x5bb7b2b1, 0x37bec572}, - {0xb72325b7, 0xa1859022, 0x591adc9a, 0x358c09e2}, - {0xb4a293c2, 0x9ec6bf52, 0x569865a7, 0x33758476}, - {0xb22cd56d, 0x9c1b9e36, 0x542efb6a, 0x31797f8a}, - {0xafc19d86, 0x9983695c, 0x51dd5ffb, 0x2f96647a}, - {0xad60a1d1, 0x96fd66f7, 0x4fa2687c, 0x2dcab91f}, - {0xab099ae9, 0x9488e64b, 0x4d7cfbc9, 0x2c151d8a}, - {0xa8bc441a, 0x92253f20, 0x4b6c1139, 0x2a7449ef}, - {0xa6785b42, 0x8fd1d14a, 0x496eaf82, 0x28e70cc3}, - {0xa43da0ae, 0x8d8e042a, 0x4783eba7, 0x276c4900}, - {0xa20bd701, 0x8b594648, 0x45aae80a, 0x2602f493}, - {0x9fe2c315, 0x89330ce4, 0x43e2d382, 0x24aa16ec}, - {0x9dc22be4, 0x871ad399, 0x422ae88c, 0x2360c7af}, - {0x9ba9da6c, 0x85101c05, 0x40826c88, 0x22262d7b}, - {0x99999999, 0x83126d70, 0x3ee8af07, 0x20f97cd2}, - {0x97913630, 0x81215480, 0x3d5d0922, 0x1fd9f714}, - {0x95907eb8, 0x7f3c62ef, 0x3bdedce0, 0x1ec6e994}, - {0x93974369, 0x7d632f45, 0x3a6d94a9, 0x1dbfacbb}, - {0x91a55615, 0x7b955498, 0x3908a2be, 0x1cc3a33b}, - {0x8fba8a1c, 0x79d2724e, 0x37af80bf, 0x1bd23960}, - {0x8dd6b456, 0x781a2be4, 0x3661af39, 0x1aeae458}, - {0x8bf9ab07, 0x766c28ba, 0x351eb539, 0x1a0d21a2}, - {0x8a2345cc, 0x74c813dd, 0x33e61feb, 0x19387676}, - {0x88535d90, 0x732d9bdc, 0x32b7823a, 0x186c6f3e}, - {0x8689cc7e, 0x719c7297, 0x3192747d, 0x17a89f21}, - {0x84c66df1, 0x70144d19, 0x30769424, 0x16ec9f89}, - {0x83091e6a, 0x6e94e36c, 0x2f63836f, 0x16380fbf}, - {0x8151bb87, 0x6d1df079, 0x2e58e925, 0x158a9484}, - {0x7fa023f1, 0x6baf31de, 0x2d567053, 0x14e3d7ba}, - {0x7df43758, 0x6a4867d3, 0x2c5bc811, 0x1443880e}, - {0x7c4dd664, 0x68e95508, 0x2b68a346, 0x13a958ab}, - {0x7aace2b0, 0x6791be86, 0x2a7cb871, 0x131500ee}, - {0x79113ebc, 0x66416b95, 0x2997c17a, 0x12863c29}, - {0x777acde8, 0x64f825a1, 0x28b97b82, 0x11fcc95c}, - {0x75e9746a, 0x63b5b822, 0x27e1a6b4, 0x11786b03}, - {0x745d1746, 0x6279f081, 0x2710061d, 0x10f8e6da}, - {0x72d59c46, 0x61449e06, 0x26445f86, 0x107e05ac}, - {0x7152e9f4, 0x601591be, 0x257e7b4d, 0x10079327}, - {0x6fd4e793, 0x5eec9e6b, 0x24be2445, 0x0f955da9}, - {0x6e5b7d16, 0x5dc9986e, 0x24032795, 0x0f273620}, - {0x6ce6931d, 0x5cac55b7, 0x234d5496, 0x0ebcefdb}, - {0x6b7612ec, 0x5b94adb2, 0x229c7cbc, 0x0e56606e}, -}; - -// Approximate rsqrt with cubic polynomials. -// The range [1,2] is splitted into 64 equal sub-ranges and the reciprocal -// square root is approximated by a cubic polynomial by the minimax method in -// each subrange. The approximation accuracy fits into 32-33 bits and thus it is -// natural to round coefficients into 32 bit. The constant coefficient can be -// rounded to 33 bits since the most significant bit is always 1 and implicitly -// assumed in the table. -LIBC_INLINE uint64_t rsqrt_approx(uint64_t m) { - // ULP(m) = 2^-64. - // Use the top 6 bits as index for looking up polynomial coeffs. - uint64_t indx = m >> 58; - - uint64_t c0 = static_cast(RSQRT_COEFFS[indx][0]); - c0 <<= 31; // to 64 bit with the space for the implicit bit - c0 |= 1ull << 63; // add implicit bit - - uint64_t c1 = static_cast(RSQRT_COEFFS[indx][1]); - c1 <<= 25; // to 64 bit format - - uint64_t c2 = static_cast(RSQRT_COEFFS[indx][2]); - uint64_t c3 = static_cast(RSQRT_COEFFS[indx][3]); - - uint64_t d = (m << 6) >> 32; // local coordinate in the subrange [0, 2^32] - uint64_t d2 = (d * d) >> 32; // square of the local coordinate - uint64_t re = c0 + (d2 * c2 >> 13); // even part of the polynomial (positive) - uint64_t ro = d * ((c1 + ((d2 * c3) >> 19)) >> 26) >> - 6; // odd part of the polynomial (negative) - uint64_t r = re - ro; // maximal error < 1.55e-10 and it is less than 2^-32 - // Newton-Raphson first order step to improve accuracy of the result to almost - // 64 bits. - r = rsqrt_newton_raphson(m, r); - // Adjust in the unlucky case x~1; - if (LIBC_UNLIKELY(!r)) - --r; - return r; -} -#endif // LIBC_MATH_HAS_SMALL_TABLES - -} // anonymous namespace - LLVM_LIBC_FUNCTION(float128, sqrtf128, (float128 x)) { - using FPBits = fputil::FPBits; - // Get rounding mode. - uint32_t rm = fputil::get_round(); - - FPBits xbits(x); - UInt128 x_u = xbits.uintval(); - // Bring leading bit of the mantissa to the highest bit. - // ulp(x_frac) = 2^-128. - UInt128 x_frac = xbits.get_mantissa() << (FPBits::EXP_LEN + 1); - - int sign_exp = static_cast(x_u >> FPBits::FRACTION_LEN); - - if (LIBC_UNLIKELY(sign_exp == 0 || sign_exp >= 0x7fff)) { - // Special cases: NAN, inf, negative numbers - if (sign_exp >= 0x7fff) { - // x = -0 or x = inf - if (xbits.is_zero() || xbits == xbits.inf()) - return x; - // x is nan - if (xbits.is_nan()) { - // pass through quiet nan - if (xbits.is_quiet_nan()) - return x; - // transform signaling nan to quiet and return - return xbits.quiet_nan().get_val(); - } - // x < 0 or x = -inf - fputil::set_errno_if_required(EDOM); - fputil::raise_except_if_required(FE_INVALID); - return xbits.quiet_nan().get_val(); - } - // Now x is subnormal or x = +0. - - // x is +0. - if (x_frac == 0) - return x; - - // Normalize subnormal inputs. - sign_exp = -cpp::countl_zero(x_frac); - int normal_shifts = 1 - sign_exp; - x_frac <<= normal_shifts; - } - - // For sign_exp = biased exponent of x = real_exponent + 16383, - // let f be the real exponent of the output: - // f = floor(real_exponent / 2) - // Then: - // floor((sign_exp + 1) / 2) = f + 8192 - // Hence, the biased exponent of the final result is: - // f + 16383 = floor((sign_exp + 1) / 2) + 8191. - // Since the output mantissa will include the hidden bit, we can define the - // output exponent part: - // e2 = floor((sign_exp + 1) / 2) + 8190 - unsigned i = static_cast(1 - (sign_exp & 1)); - uint32_t q2 = (sign_exp + 1) >> 1; - // Exponent of the final result - uint32_t e2 = q2 + 8190; - - constexpr uint64_t RSQRT_2[2] = {~0ull, - 0xb504f333f9de6484 /* 2^64/sqrt(2) */}; - - // Approximate 1/sqrt(1 + x_frac) - // Error: |r_1 - 1/sqrt(x)| < 2^-62. - uint64_t r1 = rsqrt_approx(static_cast(x_frac >> 64)); - // Adjust for the even/odd exponent. - uint64_t r2 = prod_hi(r1, RSQRT_2[i]); - unsigned shift = 2 - i; - - // Normalized input: - // 1 <= x_reduced < 4 - UInt128 x_reduced = (x_frac >> shift) | (UInt128(1) << (126 + i)); - // With r2 ~ 1/sqrt(x) up to 2^-63, we perform another round of Newton-Raphson - // iteration: - // r3 = r2 - r2 * h / 2, - // for h = r2^2 * x - 1. - // Then: - // sqrt(x) = x * (1 / sqrt(x)) - // ~ x * r3 - // = x * (r2 - r2 * h / 2) - // = (x * r2) - (x * r2) * h / 2 - UInt128 sx = prod_hi(x_reduced, r2); - UInt128 h = prod_hi(sx, r2) << 2; - UInt128 ds = static_cast(prod_hi(static_cast(h), sx)); - UInt128 v = (sx << 1) - ds; - - uint32_t nrst = rm == FE_TONEAREST; - // The result lies within (-2,5) of true square root so we now - // test that we can correctly round the result taking into account - // the rounding mode. - // Check the lowest 14 bits (by clearing and sign-extending the top - // 32 - 14 = 18 bits). - int dd = (static_cast(v) << 18) >> 18; - - if (LIBC_UNLIKELY(dd < 4 && dd >= -8)) { // can round correctly? - // m is almost the final result it can be only 1 ulp off so we - // just need to test both possibilities. We square it and - // compare with the initial argument. - UInt128 m = v >> 15; - UInt128 m2 = m * m; - // The difference of the squared result and the argument - Int128 t0 = static_cast(m2 - (x_reduced << 98)); - if (t0 == 0) { - // the square root is exact - v = m << 15; - } else { - // Add +-1 ulp to m depend on the sign of the difference. Here - // we do not need to square again since (m+1)^2 = m^2 + 2*m + - // 1 so just need to add shifted m and 1. - Int128 t1 = t0; - Int128 sgn = t0 >> 127; // sign of the difference - Int128 m_xor_sgn = static_cast(m << 1) ^ sgn; - t1 -= m_xor_sgn; - t1 += Int128(1) + sgn; - - Int128 sgn1 = t1 >> 127; - if (LIBC_UNLIKELY(sgn == sgn1)) { - t0 = t1; - v -= sgn << 15; - t1 -= m_xor_sgn; - t1 += Int128(1) + sgn; - } - - if (t1 == 0) { - // 1 ulp offset brings again an exact root - v = (m - static_cast((sgn << 1) + 1)) << 15; - } else { - t1 += t0; - Int128 side = t1 >> 127; // select what is closer m or m+-1 - v &= ~UInt128(0) << 15; // wipe the fractional bits - v -= ((sgn & side) | (~sgn & 1)) << (15 + static_cast(side)); - v |= 1; // add sticky bit since we cannot have an exact mid-point - // situation - } - } - } - - unsigned frac = static_cast(v) & 0x7fff; // fractional part - unsigned rnd; // round bit - if (LIBC_LIKELY(nrst != 0)) { - rnd = frac >> 14; // round to nearest tie to even - } else if (rm == FE_UPWARD) { - rnd = !!frac; // round up - } else { - rnd = 0; // round down or round to zero - } - - v >>= 15; // position mantissa - v += rnd; // round - - // Set inexact flag only if square root is inexact - // TODO: We will have to raise FE_INEXACT most of the time, but this - // operation is very costly, especially in x86-64, since technically, it - // needs to synchronize both SSE and x87 flags. Need to investigate - // further to see how we can make this performant. - // https://github.com/llvm/llvm-project/issues/126753 - - // if(frac) fputil::raise_except_if_required(FE_INEXACT); - - v += static_cast(e2) << FPBits::FRACTION_LEN; // place exponent - return cpp::bit_cast(v); + return math::sqrtf128(x); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/tanf16.cpp b/libc/src/math/generic/tanf16.cpp index 20323a88f3527..880ba0101a96e 100644 --- a/libc/src/math/generic/tanf16.cpp +++ b/libc/src/math/generic/tanf16.cpp @@ -37,7 +37,7 @@ constexpr fputil::ExceptValues TANF16_EXCEPTS{{ #endif // !LIBC_MATH_HAS_SKIP_ACCURATE_PASS LLVM_LIBC_FUNCTION(float16, tanf16, (float16 x)) { - using namespace sincosf16_internal; + using namespace math::sincosf16_internal; using FPBits = fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/math/generic/tanpif.cpp b/libc/src/math/generic/tanpif.cpp index b49f3cea4911b..44df22b517a46 100644 --- a/libc/src/math/generic/tanpif.cpp +++ b/libc/src/math/generic/tanpif.cpp @@ -31,6 +31,7 @@ constexpr fputil::ExceptValues TANPIF_EXCEPTS{{ #endif // !LIBC_MATH_HAS_SKIP_ACCURATE_PASS LLVM_LIBC_FUNCTION(float, tanpif, (float x)) { + using namespace math::sincosf_utils_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/math/generic/tanpif16.cpp b/libc/src/math/generic/tanpif16.cpp index b137b09860f7c..c8dbe9eaf7d6f 100644 --- a/libc/src/math/generic/tanpif16.cpp +++ b/libc/src/math/generic/tanpif16.cpp @@ -39,7 +39,7 @@ constexpr fputil::ExceptValues TANPIF16_EXCEPTS{{ #endif // !LIBC_MATH_HAS_SKIP_ACCURATE_PASS LLVM_LIBC_FUNCTION(float16, tanpif16, (float16 x)) { - using namespace sincosf16_internal; + using namespace math::sincosf16_internal; using FPBits = typename fputil::FPBits; FPBits xbits(x); diff --git a/libc/src/string/memory_utils/aarch64/inline_memcpy.h b/libc/src/string/memory_utils/aarch64/inline_memcpy.h index 11cf022e12b1f..0c9224010784f 100644 --- a/libc/src/string/memory_utils/aarch64/inline_memcpy.h +++ b/libc/src/string/memory_utils/aarch64/inline_memcpy.h @@ -9,17 +9,40 @@ #define LLVM_LIBC_SRC_STRING_MEMORY_UTILS_AARCH64_INLINE_MEMCPY_H #include "src/__support/macros/attributes.h" // LIBC_INLINE +#include "src/__support/macros/properties/cpu_features.h" #include "src/string/memory_utils/op_builtin.h" #include "src/string/memory_utils/utils.h" #include // size_t +#if defined(LIBC_TARGET_CPU_HAS_SVE) +#include +#endif namespace LIBC_NAMESPACE_DECL { - [[maybe_unused]] LIBC_INLINE void inline_memcpy_aarch64(Ptr __restrict dst, CPtr __restrict src, size_t count) { + // Always avoid emit any memory operation if count == 0. if (count == 0) return; + // Use predicated load/store on SVE available targets to avoid branching in + // small cases. +#ifdef LIBC_TARGET_CPU_HAS_SVE + auto src_ptr = reinterpret_cast(src); + auto dst_ptr = reinterpret_cast(dst); + if (count <= 16) { + const svbool_t mask = svwhilelt_b8_u64(0, count); + svst1_u8(mask, dst_ptr, svld1_u8(mask, src_ptr)); + return; + } + if (count <= 32) { + const size_t vlen = svcntb(); + svbool_t m0 = svwhilelt_b8_u64(0, count); + svbool_t m1 = svwhilelt_b8_u64(vlen, count); + svst1_u8(m0, dst_ptr, svld1_u8(m0, src_ptr)); + svst1_u8(m1, dst_ptr + vlen, svld1_u8(m1, src_ptr + vlen)); + return; + } +#else if (count == 1) return builtin::Memcpy<1>::block(dst, src); if (count == 2) @@ -34,6 +57,7 @@ inline_memcpy_aarch64(Ptr __restrict dst, CPtr __restrict src, size_t count) { return builtin::Memcpy<8>::head_tail(dst, src, count); if (count < 32) return builtin::Memcpy<16>::head_tail(dst, src, count); +#endif if (count < 64) return builtin::Memcpy<32>::head_tail(dst, src, count); if (count < 128) diff --git a/libc/startup/gpu/CMakeLists.txt b/libc/startup/gpu/CMakeLists.txt index fa326ef46a9d1..63e2a6c5dee1a 100644 --- a/libc/startup/gpu/CMakeLists.txt +++ b/libc/startup/gpu/CMakeLists.txt @@ -34,6 +34,7 @@ function(add_startup_object name) RUNTIME_OUTPUT_DIRECTORY ${LIBC_LIBRARY_DIR} RUNTIME_OUTPUT_NAME ${name}.o) target_link_options(${fq_target_name}.exe PRIVATE + ${LIBC_COMPILE_OPTIONS_DEFAULT} "-r" "-nostdlib" "-flto" "-Wl,--lto-emit-llvm") endif() endfunction() diff --git a/libc/test/shared/CMakeLists.txt b/libc/test/shared/CMakeLists.txt index 07ccd0ca1bc4b..7d72ced3e057c 100644 --- a/libc/test/shared/CMakeLists.txt +++ b/libc/test/shared/CMakeLists.txt @@ -56,9 +56,12 @@ add_fp_unittest( libc.src.__support.math.expf libc.src.__support.math.expf16 libc.src.__support.math.f16fma + libc.src.__support.math.f16fmaf + libc.src.__support.math.f16fmaf128 libc.src.__support.math.f16fmal libc.src.__support.math.f16sqrt libc.src.__support.math.f16sqrtl + libc.src.__support.math.ffmal libc.src.__support.math.frexpf libc.src.__support.math.frexpf128 libc.src.__support.math.frexpf16 @@ -97,6 +100,7 @@ add_fp_unittest( libc.src.__support.math.sinf16 libc.src.__support.math.sinhf libc.src.__support.math.sinhf16 + libc.src.__support.math.sqrtf128 libc.src.__support.math.sinpif libc.src.__support.math.sqrt libc.src.__support.math.sqrtf diff --git a/libc/test/shared/shared_math_test.cpp b/libc/test/shared/shared_math_test.cpp index ec70025f0f4ea..9e024387efbfa 100644 --- a/libc/test/shared/shared_math_test.cpp +++ b/libc/test/shared/shared_math_test.cpp @@ -38,6 +38,16 @@ TEST(LlvmLibcSharedMathTest, AllFloat16) { EXPECT_FP_EQ(float16(10.0), LIBC_NAMESPACE::shared::f16fma(2.0, 3.0, 4.0)); + EXPECT_FP_EQ(float16(10.0), + LIBC_NAMESPACE::shared::f16fmaf(2.0f, 3.0f, 4.0f)); + +#ifdef LIBC_TYPES_HAS_FLOAT128 + + EXPECT_FP_EQ(10.0f16, LIBC_NAMESPACE::shared::f16fmaf128( + float128(2.0), float128(3.0), float128(4.0))); + +#endif + EXPECT_FP_EQ(0x0p+0f16, LIBC_NAMESPACE::shared::f16sqrt(0.0)); EXPECT_FP_EQ(float16(10.0), @@ -139,6 +149,7 @@ TEST(LlvmLibcSharedMathTest, AllLongDouble) { LIBC_NAMESPACE::shared::dfmal(0x0.p+0L, 0x0.p+0L, 0x0.p+0L)); EXPECT_FP_EQ(0x0p+0f, LIBC_NAMESPACE::shared::fsqrtl(0.0L)); EXPECT_EQ(0, LIBC_NAMESPACE::shared::ilogbl(0x1.p+0L)); + EXPECT_FP_EQ(10.0f, LIBC_NAMESPACE::shared::ffmal(2.0L, 3.0, 4.0L)); } #ifdef LIBC_TYPES_HAS_FLOAT128 @@ -161,6 +172,8 @@ TEST(LlvmLibcSharedMathTest, AllFloat128) { EXPECT_FP_EQ(float128(0.0), LIBC_NAMESPACE::shared::logbf128(float128(1.0))); EXPECT_FP_EQ(0.0, LIBC_NAMESPACE::shared::dfmaf128( float128(0.0), float128(0.0), float128(0.0))); + EXPECT_FP_EQ(float128(0x1p+0), + LIBC_NAMESPACE::shared::sqrtf128(float128(1.0))); EXPECT_EQ(0L, LIBC_NAMESPACE::shared::llogbf128(float128(1.0))); } diff --git a/libc/utils/wctype_utils/classification/gen_classification_data.py b/libc/utils/wctype_utils/classification/gen_classification_data.py index 1726c84fcf55a..6e5ccdf786613 100644 --- a/libc/utils/wctype_utils/classification/gen_classification_data.py +++ b/libc/utils/wctype_utils/classification/gen_classification_data.py @@ -206,7 +206,7 @@ def build_lookup_tables(properties: defaultdict[int, int]) -> StagedLookupTable: def generate_code(lookup_table: StagedLookupTable, llvm_project_root_path: str) -> None: - """Generates C++ header with lookup tables.""" + """Generates C++ header and source file with lookup tables.""" level1 = lookup_table.level1 level2 = lookup_table.level2 @@ -228,12 +228,12 @@ def generate_code(lookup_table: StagedLookupTable, llvm_project_root_path: str) #ifndef LLVM_LIBC_SRC___SUPPORT_WCTYPE_WCTYPE_CLASSIFICATION_UTILS_H #define LLVM_LIBC_SRC___SUPPORT_WCTYPE_WCTYPE_CLASSIFICATION_UTILS_H -#include "hdr/stdint_proxy.h" +#include "hdr/stdint_proxy.h" #include "hdr/types/wchar_t.h" +#include "src/__support/CPP/limits.h" +#include "src/__support/libc_assert.h" #include "src/__support/macros/attributes.h" #include "src/__support/macros/config.h" -#include "src/__support/libc_assert.h" -#include "src/__support/CPP/limits.h" namespace LIBC_NAMESPACE_DECL {{ @@ -256,35 +256,13 @@ def generate_code(lookup_table: StagedLookupTable, llvm_project_root_path: str) LIBC_INLINE_VAR constexpr uint16_t LEVEL2_SIZE = {len(level2)}; // Level 1 table: indexed by (codepoint >> 8), stores level2 block offsets -LIBC_INLINE_VAR constexpr uint16_t level1[LEVEL1_SIZE] = {{ -""" - ) - for i in range(0, len(level1), 11): - f.write(" ") - for j in range(i, min(i + 11, len(level1))): - f.write(f"{level1[j]:7d}") - if j + 1 < len(level1): - f.write(",") - f.write("\n") - f.write( - f"""}}; +extern const uint16_t LEVEL1[LEVEL1_SIZE]; // Level 2 table: blocks of 256 property flags -LIBC_INLINE_VAR constexpr uint8_t level2[LEVEL2_SIZE] = {{ -""" - ) - for i in range(0, len(level2), 11): - f.write(" ") - for j in range(i, min(i + 11, len(level2))): - f.write(f"0x{level2[j]:02x}") - if j + 1 < len(level2): - f.write(", ") - f.write("\n") - f.write( - f"""}}; +extern const uint8_t LEVEL2[LEVEL2_SIZE]; // Returns the Unicode property flag for a given wide character. -LIBC_INLINE constexpr uint8_t lookup_properties(const wchar_t wc) {{ +LIBC_INLINE uint8_t lookup_properties(const wchar_t wc) {{ // Out of Unicode range if (static_cast(wc) > 0x10FFFF) {{ return 0; @@ -293,16 +271,67 @@ def generate_code(lookup_table: StagedLookupTable, llvm_project_root_path: str) uint16_t l1_idx = static_cast(wc >> 8); LIBC_ASSERT(l1_idx < LEVEL1_SIZE); - uint16_t l2_offset = level1[l1_idx]; + uint16_t l2_offset = LEVEL1[l1_idx]; uint16_t l2_idx = l2_offset + (wc & 0xFF); LIBC_ASSERT(l2_idx < LEVEL2_SIZE); - return level2[l2_idx]; + return LEVEL2[l2_idx]; }} }} // namespace LIBC_NAMESPACE_DECL #endif // LLVM_LIBC_SRC___SUPPORT_WCTYPE_WCTYPE_CLASSIFICATION_UTILS_H +""" + ) + + with open( + f"{llvm_project_root_path}/libc/src/__support/wctype/wctype_classification_utils.cpp", + "w", + ) as f: + f.write( + """//===-- Lookup tables for wctype classification functions -------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// DO NOT EDIT MANUALLY. +// This file is generated by libc/utils/wctype_utils scripts. + +#include "wctype_classification_utils.h" + +namespace LIBC_NAMESPACE_DECL { + +// Level 1 table: indexed by (codepoint >> 8), stores level2 block offsets +const uint16_t LEVEL1[LEVEL1_SIZE] = { +""" + ) + for i in range(0, len(level1), 11): + f.write(" ") + for j in range(i, min(i + 11, len(level1))): + f.write(f"{level1[j]:7d}") + if j + 1 < len(level1): + f.write(",") + f.write("\n") + f.write( + """}; + +// Level 2 table: blocks of 256 property flags +const uint8_t LEVEL2[LEVEL2_SIZE] = { +""" + ) + for i in range(0, len(level2), 11): + f.write(" ") + for j in range(i, min(i + 11, len(level2))): + f.write(f"0x{level2[j]:02x}") + if j + 1 < len(level2): + f.write(", ") + f.write("\n") + f.write( + """}; + +} // namespace LIBC_NAMESPACE_DECL """ ) diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt index ec4c2538637a2..3ab587c79cd12 100644 --- a/libclc/CMakeLists.txt +++ b/libclc/CMakeLists.txt @@ -229,6 +229,7 @@ set( tahiti_aliases pitcairn verde oland hainan bonaire kabini kaveri hawaii gfx1030 gfx1031 gfx1032 gfx1033 gfx1034 gfx1035 gfx1036 gfx1100 gfx1101 gfx1102 gfx1103 gfx1150 gfx1151 gfx1152 gfx1153 + gfx1170 gfx1200 gfx1201 gfx1250 gfx1251 gfx1310 ) diff --git a/libclc/clc/include/clc/internal/math/clc_sw_fma.h b/libclc/clc/include/clc/internal/math/clc_sw_fma.h index 5d6c76879ceb9..4338fb01861c1 100644 --- a/libclc/clc/include/clc/internal/math/clc_sw_fma.h +++ b/libclc/clc/include/clc/internal/math/clc_sw_fma.h @@ -10,6 +10,7 @@ #define __CLC_INTERNAL_MATH_CLC_SW_FMA_H__ #define __CLC_FUNCTION __clc_sw_fma +#define __CLC_FLOAT_ONLY #define __CLC_BODY #include diff --git a/libclc/clc/include/clc/math/math.h b/libclc/clc/include/clc/math/math.h index c2647f66b4006..b909960b7f498 100644 --- a/libclc/clc/include/clc/math/math.h +++ b/libclc/clc/include/clc/math/math.h @@ -11,7 +11,6 @@ #include #include -#include #define SNAN 0x001 #define QNAN 0x002 @@ -24,11 +23,8 @@ #define PNOR 0x100 #define PINF 0x200 -#if (defined __AMDGCN__ || defined __R600__) && !defined __HAS_FMAF__ +#ifdef __R600__ #define __CLC_HAVE_HW_FMA32() (0) -#elif defined(CLC_SPIRV) -bool __attribute__((noinline)) __clc_runtime_has_hw_fma32(void); -#define __CLC_HAVE_HW_FMA32() __clc_runtime_has_hw_fma32() #else #define __CLC_HAVE_HW_FMA32() (1) #endif @@ -65,16 +61,6 @@ bool __attribute__((noinline)) __clc_runtime_has_hw_fma32(void); #define LOG_MAGIC_NUM_SP32 (1 + NUMEXPBITS_SP32 - EXPBIAS_SP32) -_CLC_OVERLOAD _CLC_INLINE float __clc_flush_denormal_if_not_supported(float x) { - int ix = __clc_as_int(x); - if (!__clc_fp32_subnormals_supported() && ((ix & EXPBITS_SP32) == 0) && - ((ix & MANTBITS_SP32) != 0)) { - ix &= SIGNBIT_SP32; - x = __clc_as_float(ix); - } - return x; -} - #ifdef cl_khr_fp64 #define SIGNBIT_DP64 0x8000000000000000L diff --git a/libclc/clc/lib/clspv/SOURCES b/libclc/clc/lib/clspv/SOURCES index b91b0e70a397d..2faea79cbc0bf 100644 --- a/libclc/clc/lib/clspv/SOURCES +++ b/libclc/clc/lib/clspv/SOURCES @@ -1,2 +1 @@ -math/clc_sw_fma.cl integer/clc_mul_hi.cl diff --git a/libclc/clc/lib/clspv/math/clc_sw_fma.cl b/libclc/clc/lib/clspv/math/clc_sw_fma.cl deleted file mode 100644 index c28b9441b05ff..0000000000000 --- a/libclc/clc/lib/clspv/math/clc_sw_fma.cl +++ /dev/null @@ -1,274 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// This version is derived from the generic fma software implementation -// (__clc_sw_fma), but avoids the use of ulong in favor of uint2. The logic has -// been updated as appropriate. - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct fp { - uint2 mantissa; - int exponent; - uint sign; -}; - -static uint2 u2_set(uint hi, uint lo) { - uint2 res; - res.lo = lo; - res.hi = hi; - return res; -} - -static uint2 u2_set_u(uint val) { return u2_set(0, val); } - -static uint2 u2_mul(uint a, uint b) { - uint2 res; - res.hi = __clc_mul_hi(a, b); - res.lo = a * b; - return res; -} - -static uint2 u2_sll(uint2 val, uint shift) { - if (shift == 0) - return val; - if (shift < 32) { - val.hi <<= shift; - val.hi |= val.lo >> (32 - shift); - val.lo <<= shift; - } else { - val.hi = val.lo << (shift - 32); - val.lo = 0; - } - return val; -} - -static uint2 u2_srl(uint2 val, uint shift) { - if (shift == 0) - return val; - if (shift < 32) { - val.lo >>= shift; - val.lo |= val.hi << (32 - shift); - val.hi >>= shift; - } else { - val.lo = val.hi >> (shift - 32); - val.hi = 0; - } - return val; -} - -static uint2 u2_or(uint2 a, uint b) { - a.lo |= b; - return a; -} - -static uint2 u2_and(uint2 a, uint2 b) { - a.lo &= b.lo; - a.hi &= b.hi; - return a; -} - -static uint2 u2_add(uint2 a, uint2 b) { - uint carry = (__clc_hadd(a.lo, b.lo) >> 31) & 0x1; - a.lo += b.lo; - a.hi += b.hi + carry; - return a; -} - -static uint2 u2_add_u(uint2 a, uint b) { return u2_add(a, u2_set_u(b)); } - -static uint2 u2_inv(uint2 a) { - a.lo = ~a.lo; - a.hi = ~a.hi; - return u2_add_u(a, 1); -} - -static uint u2_clz(uint2 a) { - uint leading_zeroes = __clc_clz(a.hi); - if (leading_zeroes == 32) { - leading_zeroes += __clc_clz(a.lo); - } - return leading_zeroes; -} - -static bool u2_eq(uint2 a, uint2 b) { return a.lo == b.lo && a.hi == b.hi; } - -static bool u2_zero(uint2 a) { return u2_eq(a, u2_set_u(0)); } - -static bool u2_gt(uint2 a, uint2 b) { - return a.hi > b.hi || (a.hi == b.hi && a.lo > b.lo); -} - -_CLC_DEF _CLC_OVERLOAD float __clc_sw_fma(float a, float b, float c) { - /* special cases */ - if (__clc_isnan(a) || __clc_isnan(b) || __clc_isnan(c) || __clc_isinf(a) || - __clc_isinf(b)) { - return __clc_mad(a, b, c); - } - - /* If only c is inf, and both a,b are regular numbers, the result is c*/ - if (__clc_isinf(c)) { - return c; - } - - a = __clc_flush_denormal_if_not_supported(a); - b = __clc_flush_denormal_if_not_supported(b); - c = __clc_flush_denormal_if_not_supported(c); - - if (a == 0.0f || b == 0.0f) { - return c; - } - - if (c == 0) { - return a * b; - } - - struct fp st_a, st_b, st_c; - - st_a.exponent = a == .0f ? 0 : ((__clc_as_uint(a) & 0x7f800000) >> 23) - 127; - st_b.exponent = b == .0f ? 0 : ((__clc_as_uint(b) & 0x7f800000) >> 23) - 127; - st_c.exponent = c == .0f ? 0 : ((__clc_as_uint(c) & 0x7f800000) >> 23) - 127; - - st_a.mantissa = - u2_set_u(a == .0f ? 0 : (__clc_as_uint(a) & 0x7fffff) | 0x800000); - st_b.mantissa = - u2_set_u(b == .0f ? 0 : (__clc_as_uint(b) & 0x7fffff) | 0x800000); - st_c.mantissa = - u2_set_u(c == .0f ? 0 : (__clc_as_uint(c) & 0x7fffff) | 0x800000); - - st_a.sign = __clc_as_uint(a) & 0x80000000; - st_b.sign = __clc_as_uint(b) & 0x80000000; - st_c.sign = __clc_as_uint(c) & 0x80000000; - - // Multiplication. - // Move the product to the highest bits to maximize precision - // mantissa is 24 bits => product is 48 bits, 2bits non-fraction. - // Add one bit for future addition overflow, - // add another bit to detect subtraction underflow - struct fp st_mul; - st_mul.sign = st_a.sign ^ st_b.sign; - st_mul.mantissa = u2_sll(u2_mul(st_a.mantissa.lo, st_b.mantissa.lo), 14); - st_mul.exponent = - !u2_zero(st_mul.mantissa) ? st_a.exponent + st_b.exponent : 0; - - // FIXME: Detecting a == 0 || b == 0 above crashed GCN isel - if (st_mul.exponent == 0 && u2_zero(st_mul.mantissa)) - return c; - -// Mantissa is 23 fractional bits, shift it the same way as product mantissa -#define C_ADJUST 37ul - - // both exponents are bias adjusted - int exp_diff = st_mul.exponent - st_c.exponent; - - st_c.mantissa = u2_sll(st_c.mantissa, C_ADJUST); - uint2 cutoff_bits = u2_set_u(0); - uint2 cutoff_mask = u2_add(u2_sll(u2_set_u(1), __clc_abs(exp_diff)), - u2_set(0xffffffff, 0xffffffff)); - if (exp_diff > 0) { - cutoff_bits = - exp_diff >= 64 ? st_c.mantissa : u2_and(st_c.mantissa, cutoff_mask); - st_c.mantissa = - exp_diff >= 64 ? u2_set_u(0) : u2_srl(st_c.mantissa, exp_diff); - } else { - cutoff_bits = -exp_diff >= 64 ? st_mul.mantissa - : u2_and(st_mul.mantissa, cutoff_mask); - st_mul.mantissa = - -exp_diff >= 64 ? u2_set_u(0) : u2_srl(st_mul.mantissa, -exp_diff); - } - - struct fp st_fma; - st_fma.sign = st_mul.sign; - st_fma.exponent = __clc_max(st_mul.exponent, st_c.exponent); - if (st_c.sign == st_mul.sign) { - st_fma.mantissa = u2_add(st_mul.mantissa, st_c.mantissa); - } else { - // cutoff bits borrow one - st_fma.mantissa = - u2_add(u2_add(st_mul.mantissa, u2_inv(st_c.mantissa)), - (!u2_zero(cutoff_bits) && (st_mul.exponent > st_c.exponent) - ? u2_set(0xffffffff, 0xffffffff) - : u2_set_u(0))); - } - - // underflow: st_c.sign != st_mul.sign, and magnitude switches the sign - if (u2_gt(st_fma.mantissa, u2_set(0x7fffffff, 0xffffffff))) { - st_fma.mantissa = u2_inv(st_fma.mantissa); - st_fma.sign = st_mul.sign ^ 0x80000000; - } - - // detect overflow/underflow - int overflow_bits = 3 - u2_clz(st_fma.mantissa); - - // adjust exponent - st_fma.exponent += overflow_bits; - - // handle underflow - if (overflow_bits < 0) { - st_fma.mantissa = u2_sll(st_fma.mantissa, -overflow_bits); - overflow_bits = 0; - } - - // rounding - uint2 trunc_mask = u2_add(u2_sll(u2_set_u(1), C_ADJUST + overflow_bits), - u2_set(0xffffffff, 0xffffffff)); - uint2 trunc_bits = - u2_or(u2_and(st_fma.mantissa, trunc_mask), !u2_zero(cutoff_bits)); - uint2 last_bit = - u2_and(st_fma.mantissa, u2_sll(u2_set_u(1), C_ADJUST + overflow_bits)); - uint2 grs_bits = u2_sll(u2_set_u(4), C_ADJUST - 3 + overflow_bits); - - // round to nearest even - if (u2_gt(trunc_bits, grs_bits) || - (u2_eq(trunc_bits, grs_bits) && !u2_zero(last_bit))) { - st_fma.mantissa = - u2_add(st_fma.mantissa, u2_sll(u2_set_u(1), C_ADJUST + overflow_bits)); - } - - // Shift mantissa back to bit 23 - st_fma.mantissa = u2_srl(st_fma.mantissa, C_ADJUST + overflow_bits); - - // Detect rounding overflow - if (u2_gt(st_fma.mantissa, u2_set_u(0xffffff))) { - ++st_fma.exponent; - st_fma.mantissa = u2_srl(st_fma.mantissa, 1); - } - - if (u2_zero(st_fma.mantissa)) { - return 0.0f; - } - - // Flating point range limit - if (st_fma.exponent > 127) { - return __clc_as_float(__clc_as_uint(INFINITY) | st_fma.sign); - } - - // Flush denormals - if (st_fma.exponent <= -127) { - return __clc_as_float(st_fma.sign); - } - - return __clc_as_float(st_fma.sign | ((st_fma.exponent + 127) << 23) | - ((uint)st_fma.mantissa.lo & 0x7fffff)); -} - -#define __CLC_FLOAT_ONLY -#define __CLC_FUNCTION __clc_sw_fma -#define __CLC_BODY -#include diff --git a/libclc/clc/lib/generic/SOURCES b/libclc/clc/lib/generic/SOURCES index d6db515c1d47f..ee080cd356629 100644 --- a/libclc/clc/lib/generic/SOURCES +++ b/libclc/clc/lib/generic/SOURCES @@ -143,7 +143,6 @@ math/clc_sincos_helpers.cl math/clc_sinh.cl math/clc_sinpi.cl math/clc_sqrt.cl -math/clc_sw_fma.cl math/clc_tables.cl math/clc_tan.cl math/clc_tanh.cl diff --git a/libclc/clc/lib/generic/math/clc_fma.cl b/libclc/clc/lib/generic/math/clc_fma.cl index e69ef614e780f..9527460cb2c69 100644 --- a/libclc/clc/lib/generic/math/clc_fma.cl +++ b/libclc/clc/lib/generic/math/clc_fma.cl @@ -7,8 +7,11 @@ //===----------------------------------------------------------------------===// #include -#include +#include #include -#define __CLC_BODY +#define __CLC_FUNCTION __clc_fma +#define __CLC_IMPL_FUNCTION(x) __builtin_elementwise_fma +#define __CLC_BODY + #include diff --git a/libclc/clc/lib/r600/SOURCES b/libclc/clc/lib/r600/SOURCES index 4bb95e4441120..c60ac1e2b043e 100644 --- a/libclc/clc/lib/r600/SOURCES +++ b/libclc/clc/lib/r600/SOURCES @@ -1,2 +1,4 @@ +math/clc_fma.cl math/clc_native_rsqrt.cl math/clc_rsqrt.cl +math/clc_sw_fma.cl diff --git a/libclc/opencl/lib/spirv/math/fma.cl b/libclc/clc/lib/r600/math/clc_fma.cl similarity index 75% rename from libclc/opencl/lib/spirv/math/fma.cl rename to libclc/clc/lib/r600/math/clc_fma.cl index 172ec32b8a3b3..e69ef614e780f 100644 --- a/libclc/opencl/lib/spirv/math/fma.cl +++ b/libclc/clc/lib/r600/math/clc_fma.cl @@ -6,11 +6,9 @@ // //===----------------------------------------------------------------------===// +#include #include +#include -#define __CLC_FLOAT_ONLY -#define __CLC_FUNCTION fma -#define __CLC_IMPL_FUNCTION(x) __clc_sw_fma -#define __CLC_BODY - +#define __CLC_BODY #include diff --git a/libclc/clc/lib/generic/math/clc_fma.inc b/libclc/clc/lib/r600/math/clc_fma.inc similarity index 90% rename from libclc/clc/lib/generic/math/clc_fma.inc rename to libclc/clc/lib/r600/math/clc_fma.inc index b23b6433d2922..dec1adb66cf89 100644 --- a/libclc/clc/lib/generic/math/clc_fma.inc +++ b/libclc/clc/lib/r600/math/clc_fma.inc @@ -9,8 +9,8 @@ _CLC_DEF _CLC_OVERLOAD __CLC_GENTYPE __clc_fma(__CLC_GENTYPE a, __CLC_GENTYPE b, __CLC_GENTYPE c) { #if __CLC_FPSIZE == 32 - if (!__CLC_HAVE_HW_FMA32()) - return __clc_sw_fma(a, b, c); -#endif + return __clc_sw_fma(a, b, c); +#else return __builtin_elementwise_fma(a, b, c); +#endif } diff --git a/libclc/clc/lib/generic/math/clc_sw_fma.cl b/libclc/clc/lib/r600/math/clc_sw_fma.cl similarity index 94% rename from libclc/clc/lib/generic/math/clc_sw_fma.cl rename to libclc/clc/lib/r600/math/clc_sw_fma.cl index 606e4df320a89..ab5418e569371 100644 --- a/libclc/clc/lib/generic/math/clc_sw_fma.cl +++ b/libclc/clc/lib/r600/math/clc_sw_fma.cl @@ -18,6 +18,15 @@ #include #include +static _CLC_INLINE float __clc_flush_denormal(float x) { + int ix = __clc_as_int(x); + if (((ix & EXPBITS_SP32) == 0) && ((ix & MANTBITS_SP32) != 0)) { + ix &= SIGNBIT_SP32; + x = __clc_as_float(ix); + } + return x; +} + struct fp { ulong mantissa; int exponent; @@ -36,9 +45,9 @@ _CLC_DEF _CLC_OVERLOAD float __clc_sw_fma(float a, float b, float c) { return c; } - a = __clc_flush_denormal_if_not_supported(a); - b = __clc_flush_denormal_if_not_supported(b); - c = __clc_flush_denormal_if_not_supported(c); + a = __clc_flush_denormal(a); + b = __clc_flush_denormal(b); + c = __clc_flush_denormal(c); if (c == 0) { return a * b; diff --git a/libclc/clc/lib/spirv/SOURCES b/libclc/clc/lib/spirv/SOURCES index 07bc7aaead8e8..ed63fe6b7c529 100644 --- a/libclc/clc/lib/spirv/SOURCES +++ b/libclc/clc/lib/spirv/SOURCES @@ -1,3 +1,2 @@ math/clc_fmax.cl math/clc_fmin.cl -math/clc_runtime_has_hw_fma32.cl diff --git a/libclc/cmake/modules/AddLibclc.cmake b/libclc/cmake/modules/AddLibclc.cmake index 7092457bd6229..abd913d613ff4 100644 --- a/libclc/cmake/modules/AddLibclc.cmake +++ b/libclc/cmake/modules/AddLibclc.cmake @@ -394,12 +394,15 @@ function(add_libclc_builtin_set) set( libclc_builtins_lib ${library_dir}/${LIBCLC_OUTPUT_FILENAME}.spv ) if ( LIBCLC_USE_SPIRV_BACKEND ) add_custom_command( OUTPUT ${libclc_builtins_lib} - COMMAND ${clang_exe} -c --target=${ARG_TRIPLE} -x ir -o ${libclc_builtins_lib} ${builtins_link_lib} + COMMAND ${clang_exe} -c --target=${ARG_TRIPLE} + -mllvm --spirv-ext=+SPV_KHR_fma + -x ir -o ${libclc_builtins_lib} ${builtins_link_lib} DEPENDS ${clang_target} ${builtins_link_lib} ${builtins_link_lib_tgt} ) else() add_custom_command( OUTPUT ${libclc_builtins_lib} - COMMAND ${llvm-spirv_exe} ${spvflags} -o ${libclc_builtins_lib} ${builtins_link_lib} + COMMAND ${llvm-spirv_exe} ${spvflags} --spirv-ext=+SPV_KHR_fma + -o ${libclc_builtins_lib} ${builtins_link_lib} DEPENDS ${llvm-spirv_target} ${builtins_link_lib} ${builtins_link_lib_tgt} ) endif() diff --git a/libclc/opencl/lib/clspv/SOURCES b/libclc/opencl/lib/clspv/SOURCES index 8537d7c2d6b42..2616c0fe7dafb 100644 --- a/libclc/opencl/lib/clspv/SOURCES +++ b/libclc/opencl/lib/clspv/SOURCES @@ -2,7 +2,6 @@ conversion/convert_float2float.cl conversion/convert_float2int.cl conversion/convert_int2float.cl conversion/convert_integer.cl -math/fma.cl shared/vstore_half.cl subnormal_config.cl ../generic/geometric/distance.cl diff --git a/libclc/opencl/lib/spirv/SOURCES b/libclc/opencl/lib/spirv/SOURCES index 0aa923978e9f1..6b7fa8261f6d9 100644 --- a/libclc/opencl/lib/spirv/SOURCES +++ b/libclc/opencl/lib/spirv/SOURCES @@ -38,7 +38,6 @@ subnormal_config.cl ../generic/math/expm1.cl ../generic/math/exp2.cl ../generic/math/exp10.cl -math/fma.cl ../generic/math/fmod.cl ../generic/math/fract.cl ../generic/math/frexp.cl diff --git a/libcxx/docs/ReleaseNotes/23.rst b/libcxx/docs/ReleaseNotes/23.rst index c19a731a006d7..a1d62a367f33c 100644 --- a/libcxx/docs/ReleaseNotes/23.rst +++ b/libcxx/docs/ReleaseNotes/23.rst @@ -43,6 +43,10 @@ Implemented Papers Improvements and New Features ----------------------------- +- The ``std::ranges::fold_left_with_iter`` algorithm has been optimized for + segmented iterators, resulting in a performance improvement of up to 1.38x + for ``std::deque`` iterators. + Deprecations and Removals ------------------------- diff --git a/libcxx/docs/Status/Cxx2cIssues.csv b/libcxx/docs/Status/Cxx2cIssues.csv index 101a708b7b2de..60b1bd6ff70da 100644 --- a/libcxx/docs/Status/Cxx2cIssues.csv +++ b/libcxx/docs/Status/Cxx2cIssues.csv @@ -46,7 +46,7 @@ "`LWG3975 `__","Specializations of ``basic_format_context`` should not be permitted","2024-03 (Tokyo)","|Nothing To Do|","","`#105317 `__","" "`LWG3984 `__","``ranges::to``'s recursion branch may be ill-formed","2024-03 (Tokyo)","|Complete|","19","`#105318 `__","" "`LWG4011 `__","""`Effects`: Equivalent to return"" in ``[span.elem]``","2024-03 (Tokyo)","|Nothing To Do|","","`#105319 `__","" -"`LWG4012 `__","``common_view::begin/end`` are missing the ``simple-view`` check","2024-03 (Tokyo)","","","`#105320 `__","" +"`LWG4012 `__","``common_view::begin/end`` are missing the ``simple-view`` check","2024-03 (Tokyo)","|Complete|","23","`#105320 `__","" "`LWG4013 `__","``lazy_split_view::outer-iterator::value_type`` should not provide default constructor","2024-03 (Tokyo)","","","`#105321 `__","" "`LWG4016 `__","container-insertable checks do not match what container-inserter does","2024-03 (Tokyo)","|Complete|","20","`#105322 `__","" "`LWG4023 `__","Preconditions of ``std::basic_streambuf::setg/setp``","2024-03 (Tokyo)","|Complete|","19","`#105323 `__","" diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt index 494c21bd30019..dc6c262fad17e 100644 --- a/libcxx/include/CMakeLists.txt +++ b/libcxx/include/CMakeLists.txt @@ -480,6 +480,7 @@ set(files __iterator/aliasing_iterator.h __iterator/back_insert_iterator.h __iterator/bounded_iter.h + __iterator/capacity_aware_iterator.h __iterator/common_iterator.h __iterator/concepts.h __iterator/counted_iterator.h diff --git a/libcxx/include/__algorithm/for_each.h b/libcxx/include/__algorithm/for_each.h index 85fedce3d936d..bb656a2db0188 100644 --- a/libcxx/include/__algorithm/for_each.h +++ b/libcxx/include/__algorithm/for_each.h @@ -26,7 +26,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _InputIterator -__for_each(_InputIterator __first, _Sent __last, _Func& __func, _Proj& __proj) { +__for_each(_InputIterator __first, _Sent __last, _Func&& __func, _Proj& __proj) { #ifndef _LIBCPP_CXX03_LANG if constexpr (using _SpecialAlg = __specialized_algorithm<_Algorithm::__for_each, __iterator_pair<_InputIterator, _Sent>>; diff --git a/libcxx/include/__algorithm/for_each_n.h b/libcxx/include/__algorithm/for_each_n.h index 72c7adb093f95..7ff3f9b157c02 100644 --- a/libcxx/include/__algorithm/for_each_n.h +++ b/libcxx/include/__algorithm/for_each_n.h @@ -18,6 +18,7 @@ #include <__iterator/segmented_iterator.h> #include <__type_traits/invoke.h> #include <__utility/convert_to_integral.h> +#include <__utility/forward.h> #include <__utility/move.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) @@ -31,7 +32,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _InputIterator -__for_each_n(_InputIterator __first, _Size __orig_n, _Func& __f, _Proj& __proj) { +__for_each_n(_InputIterator __first, _Size __orig_n, _Func&& __f, _Proj& __proj) { typedef decltype(std::__convert_to_integral(__orig_n)) _IntegralSize; _IntegralSize __n = __orig_n; @@ -43,7 +44,7 @@ __for_each_n(_InputIterator __first, _Size __orig_n, _Func& __f, _Proj& __proj) std::__for_each(__lfirst, __llast, __f, __proj); }); } else { - return std::__for_each(__first, __first + __n, __f, __proj); + return std::__for_each(__first, __first + __n, std::forward<_Func>(__f), __proj); } } else #endif diff --git a/libcxx/include/__algorithm/generate_n.h b/libcxx/include/__algorithm/generate_n.h index 23899e49e0b65..ba04eb62e3c3a 100644 --- a/libcxx/include/__algorithm/generate_n.h +++ b/libcxx/include/__algorithm/generate_n.h @@ -29,8 +29,11 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _OutputIterator __generate_n(_OutputIterator __first, _Size __orig_n, _Generator& __gen) { using __iter_ref = decltype(*__first); __identity __proj; - auto __f = [&](__iter_ref __element) { std::forward<__iter_ref>(__element) = __gen(); }; - return std::__for_each_n(std::move(__first), __orig_n, __f, __proj); + return std::__for_each_n( + std::move(__first), + __orig_n, + [&](__iter_ref __element) { std::forward<__iter_ref>(__element) = __gen(); }, + __proj); } template diff --git a/libcxx/include/__algorithm/ranges_fold.h b/libcxx/include/__algorithm/ranges_fold.h index d2c3921398504..c2d150a16d328 100644 --- a/libcxx/include/__algorithm/ranges_fold.h +++ b/libcxx/include/__algorithm/ranges_fold.h @@ -10,12 +10,14 @@ #ifndef _LIBCPP___ALGORITHM_RANGES_FOLD_H #define _LIBCPP___ALGORITHM_RANGES_FOLD_H +#include <__algorithm/for_each.h> #include <__concepts/assignable.h> #include <__concepts/constructible.h> #include <__concepts/convertible_to.h> #include <__concepts/invocable.h> #include <__concepts/movable.h> #include <__config> +#include <__functional/identity.h> #include <__functional/invoke.h> #include <__functional/reference_wrapper.h> #include <__iterator/concepts.h> @@ -87,11 +89,17 @@ struct __fold_left_with_iter { } _Up __result = std::invoke(__f, std::move(__init), *__first); - for (++__first; __first != __last; ++__first) { - __result = std::invoke(__f, std::move(__result), *__first); - } - - return fold_left_with_iter_result<_Ip, _Up>{std::move(__first), std::move(__result)}; + ++__first; + __identity __proj; + auto __end = std::__for_each( + std::move(__first), + std::move(__last), + [&](auto&& __element) { + __result = std::invoke(__f, std::move(__result), std::forward(__element)); + }, + __proj); + + return fold_left_with_iter_result<_Ip, _Up>{std::move(__end), std::move(__result)}; } template > _Fp> diff --git a/libcxx/include/__algorithm/ranges_reverse_copy.h b/libcxx/include/__algorithm/ranges_reverse_copy.h index e5ca5cf652dc4..9fedab5bd4362 100644 --- a/libcxx/include/__algorithm/ranges_reverse_copy.h +++ b/libcxx/include/__algorithm/ranges_reverse_copy.h @@ -18,6 +18,7 @@ #include <__ranges/access.h> #include <__ranges/concepts.h> #include <__ranges/dangling.h> +#include <__ranges/reverse_view.h> #include <__ranges/subrange.h> #include <__utility/move.h> @@ -49,7 +50,7 @@ struct __reverse_copy { requires indirectly_copyable, _OutIter> _LIBCPP_HIDE_FROM_ABI constexpr reverse_copy_result, _OutIter> operator()(_Range&& __range, _OutIter __result) const { - auto __ret = ranges::copy(std::__reverse_range(__range), std::move(__result)); + auto __ret = ranges::copy(__range | views::reverse, std::move(__result)); return {ranges::next(ranges::begin(__range), ranges::end(__range)), std::move(__ret.out)}; } }; diff --git a/libcxx/include/__algorithm/unwrap_range.h b/libcxx/include/__algorithm/unwrap_range.h index 2d4b9bb5545ad..c46094f1e6861 100644 --- a/libcxx/include/__algorithm/unwrap_range.h +++ b/libcxx/include/__algorithm/unwrap_range.h @@ -10,10 +10,9 @@ #define _LIBCPP___ALGORITHM_UNWRAP_RANGE_H #include <__algorithm/unwrap_iter.h> -#include <__concepts/constructible.h> #include <__config> #include <__iterator/concepts.h> -#include <__iterator/next.h> +#include <__type_traits/is_same.h> #include <__utility/declval.h> #include <__utility/move.h> #include <__utility/pair.h> @@ -33,52 +32,24 @@ _LIBCPP_BEGIN_NAMESPACE_STD #if _LIBCPP_STD_VER >= 20 template -struct __unwrap_range_impl { - _LIBCPP_HIDE_FROM_ABI static constexpr auto __unwrap(_Iter __first, _Sent __sent) - requires random_access_iterator<_Iter> && sized_sentinel_for<_Sent, _Iter> - { - auto __last = ranges::next(__first, __sent); +_LIBCPP_HIDE_FROM_ABI constexpr auto __unwrap_range(_Iter __first, _Sent __last) { + if constexpr (is_same_v<_Iter, _Sent>) return pair{std::__unwrap_iter(std::move(__first)), std::__unwrap_iter(std::move(__last))}; - } - - _LIBCPP_HIDE_FROM_ABI static constexpr auto __unwrap(_Iter __first, _Sent __last) { + else if constexpr (random_access_iterator<_Iter> && sized_sentinel_for<_Sent, _Iter>) { + auto __iter_last = __first + (__last - __first); + return pair{std::__unwrap_iter(std::move(__first)), std::__unwrap_iter(std::move(__iter_last))}; + } else return pair{std::move(__first), std::move(__last)}; - } - - _LIBCPP_HIDE_FROM_ABI static constexpr auto - __rewrap(_Iter __orig_iter, decltype(std::__unwrap_iter(std::move(__orig_iter))) __iter) - requires random_access_iterator<_Iter> && sized_sentinel_for<_Sent, _Iter> - { - return std::__rewrap_iter(std::move(__orig_iter), std::move(__iter)); - } - - _LIBCPP_HIDE_FROM_ABI static constexpr auto __rewrap(const _Iter&, _Iter __iter) - requires(!(random_access_iterator<_Iter> && sized_sentinel_for<_Sent, _Iter>)) - { - return __iter; - } -}; - -template -struct __unwrap_range_impl<_Iter, _Iter> { - _LIBCPP_HIDE_FROM_ABI static constexpr auto __unwrap(_Iter __first, _Iter __last) { - return pair{std::__unwrap_iter(std::move(__first)), std::__unwrap_iter(std::move(__last))}; - } - - _LIBCPP_HIDE_FROM_ABI static constexpr auto - __rewrap(_Iter __orig_iter, decltype(std::__unwrap_iter(__orig_iter)) __iter) { - return std::__rewrap_iter(std::move(__orig_iter), std::move(__iter)); - } -}; - -template -_LIBCPP_HIDE_FROM_ABI constexpr auto __unwrap_range(_Iter __first, _Sent __last) { - return __unwrap_range_impl<_Iter, _Sent>::__unwrap(std::move(__first), std::move(__last)); } template < class _Sent, class _Iter, class _Unwrapped> _LIBCPP_HIDE_FROM_ABI constexpr _Iter __rewrap_range(_Iter __orig_iter, _Unwrapped __iter) { - return __unwrap_range_impl<_Iter, _Sent>::__rewrap(std::move(__orig_iter), std::move(__iter)); + if constexpr (is_same_v<_Iter, _Sent>) + return std::__rewrap_iter(std::move(__orig_iter), std::move(__iter)); + else if constexpr (random_access_iterator<_Iter> && sized_sentinel_for<_Sent, _Iter>) + return std::__rewrap_iter(std::move(__orig_iter), std::move(__iter)); + else + return __iter; } #else // _LIBCPP_STD_VER >= 20 template ()))> diff --git a/libcxx/include/__chrono/duration.h b/libcxx/include/__chrono/duration.h index 9313fc797ecd5..b7762bd1203ad 100644 --- a/libcxx/include/__chrono/duration.h +++ b/libcxx/include/__chrono/duration.h @@ -291,13 +291,13 @@ typedef duration nanoseconds; typedef duration microseconds; typedef duration milliseconds; typedef duration seconds; -typedef duration< long, ratio< 60> > minutes; -typedef duration< long, ratio<3600> > hours; +typedef duration > minutes; +typedef duration > hours; #if _LIBCPP_STD_VER >= 20 -typedef duration< int, ratio_multiply, hours::period>> days; -typedef duration< int, ratio_multiply, days::period>> weeks; -typedef duration< int, ratio_multiply, days::period>> years; -typedef duration< int, ratio_divide>> months; +typedef duration> days; +typedef duration> weeks; +typedef duration(365.2425 * 60 * 60 * 24)>> years; +typedef duration(365.2425 * 60 * 60 * 24) / 12>> months; #endif // Duration == diff --git a/libcxx/include/__iterator/capacity_aware_iterator.h b/libcxx/include/__iterator/capacity_aware_iterator.h new file mode 100644 index 0000000000000..4fbe2a6028175 --- /dev/null +++ b/libcxx/include/__iterator/capacity_aware_iterator.h @@ -0,0 +1,186 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBCPP___CAPACITY_AWARE_ITERATOR_H +#define _LIBCPP___CAPACITY_AWARE_ITERATOR_H + +#include <__assert> +#include <__compare/ordering.h> +#include <__compare/three_way_comparable.h> +#include <__config> +#include <__cstddef/size_t.h> +#include <__iterator/concepts.h> +#include <__iterator/incrementable_traits.h> +#include <__iterator/iterator_traits.h> +#include <__memory/pointer_traits.h> +#include <__type_traits/is_constructible.h> +#include <__type_traits/is_convertible.h> +#include <__utility/move.h> + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +_LIBCPP_PUSH_MACROS +#include <__undef_macros> + +#if _LIBCPP_STD_VER >= 26 + +_LIBCPP_BEGIN_NAMESPACE_STD + +// __capacity_aware_iterator is an iterator that wraps a contiguous iterator and encodes the maximum number of +// elements that can appear in a range of such iterators. That maximum number of elements must be known at compile-time. +// As of writing, the only standard library containers which fulfill these requirements are inplace_vector and optional. +// +// It also embeds a tag type to prevent mixing iterators from e.g. different containers. This also allows for some +// algorithms to detect this iterator and perform optimizations based on the added semantic information. + +template +class __capacity_aware_iterator { +private: + _Iter __iter_; + + template + friend class __capacity_aware_iterator; + +public: + static_assert(contiguous_iterator<_Iter>, "__capacity_aware_iterator can only be used with contiguous iterators"); + + using iterator_category = iterator_traits<_Iter>::iterator_category; + using iterator_concept = contiguous_iterator_tag; + using difference_type = iter_difference_t<_Iter>; + using pointer = iterator_traits<_Iter>::pointer; + using reference = iter_reference_t<_Iter>; + using value_type = iter_value_t<_Iter>; + + _LIBCPP_HIDE_FROM_ABI constexpr __capacity_aware_iterator() + requires is_default_constructible_v<_Iter> + = default; + + template + requires is_convertible_v<_Iter2, _Iter> + _LIBCPP_HIDE_FROM_ABI constexpr __capacity_aware_iterator( + const __capacity_aware_iterator<_Iter2, _Tag, _RangeMaxElements>& __y) noexcept + : __iter_(__y.__iter_) {} + + template + _LIBCPP_HIDE_FROM_ABI friend constexpr auto __make_capacity_aware_iterator(_It __iter) noexcept; + +private: + _LIBCPP_HIDE_FROM_ABI constexpr explicit __capacity_aware_iterator(_Iter __iter) : __iter_(std::move(__iter)) {} + +public: + _LIBCPP_HIDE_FROM_ABI constexpr decltype(auto) operator*() const noexcept { return *__iter_; } + _LIBCPP_HIDE_FROM_ABI constexpr decltype(auto) operator->() const noexcept { return std::__to_address(__iter_); } + + _LIBCPP_HIDE_FROM_ABI constexpr __capacity_aware_iterator& operator++() noexcept { + ++__iter_; + return *this; + } + + _LIBCPP_HIDE_FROM_ABI constexpr __capacity_aware_iterator operator++(int) noexcept { + __capacity_aware_iterator __tmp(*this); + ++*this; + return __tmp; + } + + _LIBCPP_HIDE_FROM_ABI constexpr __capacity_aware_iterator& operator--() noexcept { + --__iter_; + return *this; + } + + _LIBCPP_HIDE_FROM_ABI constexpr __capacity_aware_iterator operator--(int) noexcept { + __capacity_aware_iterator __tmp(*this); + --*this; + return __tmp; + } + + _LIBCPP_HIDE_FROM_ABI constexpr __capacity_aware_iterator& operator+=(difference_type __n) noexcept { + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + static_cast(__n >= 0 ? __n : -__n) <= _RangeMaxElements, + "__capacity_aware_iterator::operator+=: Attempting to move iterator past its container's possible range"); + + __iter_ += __n; + return *this; + } + + _LIBCPP_HIDE_FROM_ABI constexpr __capacity_aware_iterator& operator-=(difference_type __n) noexcept { + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + static_cast(__n >= 0 ? __n : -__n) <= _RangeMaxElements, + "__capacity_aware_iterator::operator-=: Attempting to move iterator past its container's possible range"); + + __iter_ -= __n; + return *this; + } + + _LIBCPP_HIDE_FROM_ABI constexpr decltype(auto) operator[](difference_type __n) const noexcept { + _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS( + static_cast(__n >= 0 ? __n : -__n) < _RangeMaxElements, + "__capacity_aware_iterator::operator[]: Attempting to index iterator past its container's possible range"); + return *(*this + __n); + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr bool + operator==(const __capacity_aware_iterator& __x, const __capacity_aware_iterator& __y) noexcept { + return __x.__iter_ == __y.__iter_; + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr auto + operator<=>(const __capacity_aware_iterator& __x, const __capacity_aware_iterator& __y) noexcept { + if constexpr (three_way_comparable_with<_Iter, _Iter, strong_ordering>) { + return __x.__iter_ <=> __y.__iter_; + } else { + if (__x.__iter_ < __y.__iter_) { + return strong_ordering::less; + } else if (__x.__iter_ == __y.__iter_) { + return strong_ordering::equal; + } + return strong_ordering::greater; + } + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr __capacity_aware_iterator + operator+(const __capacity_aware_iterator& __i, difference_type __n) noexcept { + auto __tmp = __i; + __tmp += __n; + return __tmp; + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr __capacity_aware_iterator + operator+(difference_type __n, const __capacity_aware_iterator& __i) noexcept { + auto __tmp = __i; + __tmp += __n; + return __tmp; + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr __capacity_aware_iterator + operator-(const __capacity_aware_iterator& __i, difference_type __n) noexcept { + auto __tmp = __i; + __tmp -= __n; + return __tmp; + } + + _LIBCPP_HIDE_FROM_ABI friend constexpr difference_type + operator-(const __capacity_aware_iterator& __x, const __capacity_aware_iterator& __y) noexcept { + return difference_type(__x.__iter_ - __y.__iter_); + } +}; + +template +_LIBCPP_HIDE_FROM_ABI constexpr auto __make_capacity_aware_iterator(_It __iter) noexcept { + return __capacity_aware_iterator<_It, _Tag2, _RangeMaxElems2>(__iter); +} + +_LIBCPP_END_NAMESPACE_STD + +#endif // _LIBCPP_STD_VER >= 26 + +_LIBCPP_POP_MACROS + +#endif // _LIBCPP___CAPACITY_AWARE_ITERATOR_H diff --git a/libcxx/include/__iterator/reverse_iterator.h b/libcxx/include/__iterator/reverse_iterator.h index 834695dd16703..e2984f8e39652 100644 --- a/libcxx/include/__iterator/reverse_iterator.h +++ b/libcxx/include/__iterator/reverse_iterator.h @@ -15,21 +15,13 @@ #include <__compare/three_way_comparable.h> #include <__concepts/convertible_to.h> #include <__config> -#include <__iterator/advance.h> #include <__iterator/concepts.h> #include <__iterator/incrementable_traits.h> #include <__iterator/iter_move.h> #include <__iterator/iter_swap.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> -#include <__iterator/next.h> -#include <__iterator/prev.h> -#include <__iterator/readable_traits.h> -#include <__iterator/segmented_iterator.h> #include <__memory/addressof.h> -#include <__ranges/access.h> -#include <__ranges/concepts.h> -#include <__ranges/subrange.h> #include <__type_traits/conditional.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_assignable.h> @@ -38,7 +30,6 @@ #include <__type_traits/is_pointer.h> #include <__type_traits/is_same.h> #include <__utility/declval.h> -#include <__utility/move.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -312,16 +303,6 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX17 reverse_iterator<_Ite } #endif -#if _LIBCPP_STD_VER >= 20 -template -_LIBCPP_HIDE_FROM_ABI constexpr ranges::subrange>, - reverse_iterator>> -__reverse_range(_Range&& __range) { - auto __first = ranges::begin(__range); - return {std::make_reverse_iterator(ranges::next(__first, ranges::end(__range))), std::make_reverse_iterator(__first)}; -} -#endif - template struct __unwrap_iter_impl >, __b> { using _UnwrappedIter _LIBCPP_NODEBUG = decltype(__unwrap_iter_impl<_Iter>::__unwrap(std::declval<_Iter>())); diff --git a/libcxx/include/__memory/allocator_traits.h b/libcxx/include/__memory/allocator_traits.h index b38d7293a3fd3..7038885a8b24f 100644 --- a/libcxx/include/__memory/allocator_traits.h +++ b/libcxx/include/__memory/allocator_traits.h @@ -11,6 +11,7 @@ #define _LIBCPP___MEMORY_ALLOCATOR_TRAITS_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__cstddef/size_t.h> #include <__fwd/memory.h> #include <__memory/construct_at.h> @@ -223,8 +224,13 @@ _LIBCPP_CTAD_SUPPORTED_FOR_TYPE(allocation_result); #endif // _LIBCPP_STD_VER +template +struct allocator_traits; + +// We have a base class that can be specialized for different allocators, since the metaprogramming to get the aliases +// is quite expensive and the definition of these aliases is usually quite trivial in the end. template -struct allocator_traits { +struct __allocator_traits_base { using allocator_type = _Alloc; using value_type = typename allocator_type::value_type; using pointer = __pointer; @@ -253,6 +259,60 @@ struct allocator_traits { using other = allocator_traits::other>; }; #endif // _LIBCPP_CXX03_LANG +}; + +template +struct __allocator_traits_base > { + using allocator_type = allocator<_Tp>; + using value_type = _Tp; + using pointer = _Tp*; + using const_pointer = const _Tp*; + using void_pointer = void*; + using const_void_pointer = const void*; + using difference_type = ptrdiff_t; + using size_type = size_t; + using propagate_on_container_copy_assignment = false_type; + using propagate_on_container_move_assignment = true_type; + using propagate_on_container_swap = false_type; + using is_always_equal = true_type; + +#ifndef _LIBCPP_CXX03_LANG + template + using rebind_alloc = allocator<_Up>; + template + using rebind_traits = allocator_traits >; +#else + template + struct rebind_alloc { + using other = allocator<_Up>; + }; + template + struct rebind_traits { + using other = allocator_traits >; + }; +#endif +}; + +template +struct allocator_traits : __allocator_traits_base<_Alloc> { + using __base _LIBCPP_NODEBUG = __allocator_traits_base<_Alloc>; + + using allocator_type = typename __base::allocator_type; + using value_type = typename __base::value_type; + using pointer = typename __base::pointer; + using const_pointer = typename __base::const_pointer; + using void_pointer = typename __base::void_pointer; + using const_void_pointer = typename __base::const_void_pointer; + using difference_type = typename __base::difference_type; + using size_type = typename __base::size_type; + using propagate_on_container_copy_assignment = typename __base::propagate_on_container_copy_assignment; + using propagate_on_container_move_assignment = typename __base::propagate_on_container_move_assignment; + using is_always_equal = typename __base::is_always_equal; + + template + using rebind_alloc = typename __base::template rebind_alloc<_Tp>; + template + using rebind_traits = typename __base::template rebind_traits<_Tp>; [[__nodiscard__]] _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 static pointer allocate(allocator_type& __a, size_type __n) { diff --git a/libcxx/include/__vector/vector.h b/libcxx/include/__vector/vector.h index b5d49e20dc875..e28ceb7f69e96 100644 --- a/libcxx/include/__vector/vector.h +++ b/libcxx/include/__vector/vector.h @@ -85,8 +85,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD template */> class vector { - template - using __split_buffer _LIBCPP_NODEBUG = std::__split_buffer<_Up, _Alloc, __split_buffer_pointer_layout>; + using _SplitBuffer _LIBCPP_NODEBUG = std::__split_buffer<_Tp, _Allocator, __split_buffer_pointer_layout>; public: // @@ -487,7 +486,7 @@ class vector { if (__len < __cap_ - __end_) { __construct_at_end(ranges::begin(__range), ranges::end(__range), __len); } else { - __split_buffer __buffer(__recommend(size() + __len), size(), __alloc_); + _SplitBuffer __buffer(__recommend(size() + __len), size(), __alloc_); __buffer.__construct_at_end_with_size(ranges::begin(__range), __len); __swap_out_circular_buffer(__buffer); } @@ -698,10 +697,9 @@ class vector { #endif // _LIBCPP_ABI_BOUNDED_ITERATORS_IN_VECTOR } - _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void - __swap_out_circular_buffer(__split_buffer& __v); + _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __swap_out_circular_buffer(_SplitBuffer& __v); _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI pointer - __swap_out_circular_buffer(__split_buffer& __v, pointer __p); + __swap_out_circular_buffer(_SplitBuffer& __v, pointer __p); _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __move_range(pointer __from_s, pointer __from_e, pointer __to); _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __move_assign(vector& __c, true_type) @@ -808,7 +806,7 @@ class vector { _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __move_assign_alloc(vector&, false_type) _NOEXCEPT {} template ::value, int> = 0> - static _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI _LIBCPP_NO_CFI pointer + static _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI _LIBCPP_NO_CFI _Ptr __add_alignment_assumption(_Ptr __p) _NOEXCEPT { if (!__libcpp_is_constant_evaluated()) { return static_cast(__builtin_assume_aligned(__p, _LIBCPP_ALIGNOF(decltype(*__p)))); @@ -817,12 +815,12 @@ class vector { } template ::value, int> = 0> - static _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI _LIBCPP_NO_CFI pointer + static _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI _LIBCPP_NO_CFI _Ptr __add_alignment_assumption(_Ptr __p) _NOEXCEPT { return __p; } - _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __swap_layouts(__split_buffer<_Tp, allocator_type>& __sb) { + _LIBCPP_CONSTEXPR_SINCE_CXX20 _LIBCPP_HIDE_FROM_ABI void __swap_layouts(_SplitBuffer& __sb) { auto __vector_begin = __begin_; auto __vector_sentinel = __end_; auto __vector_cap = __cap_; @@ -866,8 +864,7 @@ vector(from_range_t, _Range&&, _Alloc = _Alloc()) -> vector -_LIBCPP_CONSTEXPR_SINCE_CXX20 void -vector<_Tp, _Allocator>::__swap_out_circular_buffer(__split_buffer& __v) { +_LIBCPP_CONSTEXPR_SINCE_CXX20 void vector<_Tp, _Allocator>::__swap_out_circular_buffer(_SplitBuffer& __v) { __annotate_delete(); auto __new_begin = __v.begin() - size(); std::__uninitialized_allocator_relocate( @@ -886,7 +883,7 @@ vector<_Tp, _Allocator>::__swap_out_circular_buffer(__split_buffer _LIBCPP_CONSTEXPR_SINCE_CXX20 typename vector<_Tp, _Allocator>::pointer -vector<_Tp, _Allocator>::__swap_out_circular_buffer(__split_buffer& __v, pointer __p) { +vector<_Tp, _Allocator>::__swap_out_circular_buffer(_SplitBuffer& __v, pointer __p) { __annotate_delete(); pointer __ret = __v.begin(); @@ -1086,7 +1083,7 @@ _LIBCPP_CONSTEXPR_SINCE_CXX20 void vector<_Tp, _Allocator>::reserve(size_type __ if (__n > capacity()) { if (__n > max_size()) this->__throw_length_error(); - __split_buffer __v(__n, size(), this->__alloc_); + _SplitBuffer __v(__n, size(), this->__alloc_); __swap_out_circular_buffer(__v); } } @@ -1097,7 +1094,7 @@ _LIBCPP_CONSTEXPR_SINCE_CXX20 void vector<_Tp, _Allocator>::shrink_to_fit() _NOE #if _LIBCPP_HAS_EXCEPTIONS try { #endif // _LIBCPP_HAS_EXCEPTIONS - __split_buffer __v(size(), size(), this->__alloc_); + _SplitBuffer __v(size(), size(), this->__alloc_); // The Standard mandates shrink_to_fit() does not increase the capacity. // With equal capacity keep the existing buffer. This avoids extra work // due to swapping the elements. @@ -1114,7 +1111,7 @@ template template _LIBCPP_CONSTEXPR_SINCE_CXX20 typename vector<_Tp, _Allocator>::pointer vector<_Tp, _Allocator>::__emplace_back_slow_path(_Args&&... __args) { - __split_buffer __v(__recommend(size() + 1), size(), this->__alloc_); + _SplitBuffer __v(__recommend(size() + 1), size(), this->__alloc_); // __v.emplace_back(std::forward<_Args>(__args)...); pointer __end = __v.end(); __alloc_traits::construct(this->__alloc_, std::__to_address(__end), std::forward<_Args>(__args)...); @@ -1217,7 +1214,7 @@ vector<_Tp, _Allocator>::insert(const_iterator __position, const_reference __x) *__p = *__xr; } } else { - __split_buffer __v(__recommend(size() + 1), __p - this->__begin_, this->__alloc_); + _SplitBuffer __v(__recommend(size() + 1), __p - this->__begin_, this->__alloc_); __v.emplace_back(__x); __p = __swap_out_circular_buffer(__v, __p); } @@ -1236,7 +1233,7 @@ vector<_Tp, _Allocator>::insert(const_iterator __position, value_type&& __x) { *__p = std::move(__x); } } else { - __split_buffer __v(__recommend(size() + 1), __p - this->__begin_, this->__alloc_); + _SplitBuffer __v(__recommend(size() + 1), __p - this->__begin_, this->__alloc_); __v.emplace_back(std::move(__x)); __p = __swap_out_circular_buffer(__v, __p); } @@ -1257,7 +1254,7 @@ vector<_Tp, _Allocator>::emplace(const_iterator __position, _Args&&... __args) { *__p = std::move(__tmp.get()); } } else { - __split_buffer __v(__recommend(size() + 1), __p - this->__begin_, this->__alloc_); + _SplitBuffer __v(__recommend(size() + 1), __p - this->__begin_, this->__alloc_); __v.emplace_back(std::forward<_Args>(__args)...); __p = __swap_out_circular_buffer(__v, __p); } @@ -1285,7 +1282,7 @@ vector<_Tp, _Allocator>::insert(const_iterator __position, size_type __n, const_ std::fill_n(__p, __n, *__xr); } } else { - __split_buffer __v(__recommend(size() + __n), __p - this->__begin_, this->__alloc_); + _SplitBuffer __v(__recommend(size() + __n), __p - this->__begin_, this->__alloc_); __v.__construct_at_end(__n, __x); __p = __swap_out_circular_buffer(__v, __p); } @@ -1306,11 +1303,11 @@ vector<_Tp, _Allocator>::__insert_with_sentinel(const_iterator __position, _Inpu if (__first == __last) (void)std::rotate(__p, __old_last, this->__end_); else { - __split_buffer __v(__alloc_); + _SplitBuffer __v(__alloc_); auto __guard = std::__make_exception_guard( _AllocatorDestroyRangeReverse(__alloc_, __old_last, this->__end_)); __v.__construct_at_end_with_sentinel(std::move(__first), std::move(__last)); - __split_buffer __merged( + _SplitBuffer __merged( __recommend(size() + __v.size()), __off, __alloc_); // has `__off` positions available at the front std::__uninitialized_allocator_relocate( __alloc_, std::__to_address(__old_last), std::__to_address(this->__end_), std::__to_address(__merged.end())); @@ -1356,7 +1353,7 @@ vector<_Tp, _Allocator>::__insert_with_size( __insert_assign_n_unchecked<_AlgPolicy>(std::move(__first), __n, __p); } } else { - __split_buffer __v(__recommend(size() + __n), __p - this->__begin_, this->__alloc_); + _SplitBuffer __v(__recommend(size() + __n), __p - this->__begin_, this->__alloc_); __v.__construct_at_end_with_size(std::move(__first), __n); __p = __swap_out_circular_buffer(__v, __p); } @@ -1371,7 +1368,7 @@ _LIBCPP_CONSTEXPR_SINCE_CXX20 void vector<_Tp, _Allocator>::resize(size_type __n if (__new_size <= capacity()) { __construct_at_end(__new_size - __current_size); } else { - __split_buffer __v(__recommend(__new_size), __current_size, __alloc_); + _SplitBuffer __v(__recommend(__new_size), __current_size, __alloc_); __v.__construct_at_end(__new_size - __current_size); __swap_out_circular_buffer(__v); } @@ -1387,7 +1384,7 @@ _LIBCPP_CONSTEXPR_SINCE_CXX20 void vector<_Tp, _Allocator>::resize(size_type __n if (__new_size <= capacity()) __construct_at_end(__new_size - __current_size, __x); else { - __split_buffer __v(__recommend(__new_size), __current_size, __alloc_); + _SplitBuffer __v(__recommend(__new_size), __current_size, __alloc_); __v.__construct_at_end(__new_size - __current_size, __x); __swap_out_circular_buffer(__v); } diff --git a/libcxx/include/any b/libcxx/include/any index 382a7c894b86b..d9368df75296e 100644 --- a/libcxx/include/any +++ b/libcxx/include/any @@ -89,6 +89,7 @@ namespace std { # include <__type_traits/add_cv_quals.h> # include <__type_traits/add_pointer.h> # include <__type_traits/conditional.h> +# include <__type_traits/conjunction.h> # include <__type_traits/decay.h> # include <__type_traits/enable_if.h> # include <__type_traits/is_constructible.h> @@ -97,6 +98,7 @@ namespace std { # include <__type_traits/is_reference.h> # include <__type_traits/is_same.h> # include <__type_traits/is_void.h> +# include <__type_traits/negation.h> # include <__type_traits/remove_cv.h> # include <__type_traits/remove_cvref.h> # include <__type_traits/remove_reference.h> @@ -201,10 +203,11 @@ public: __other.__call(_Action::_Move, this); } - template , - enable_if_t && !__is_inplace_type<_ValueType>::value && is_copy_constructible_v<_Tp>, - int> = 0> + template < + class _ValueType, + class _Tp = decay_t<_ValueType>, + enable_if_t<_And<_Not>, _Not<__is_inplace_type<_ValueType>>, is_copy_constructible<_Tp>>::value, + int> = 0> _LIBCPP_HIDE_FROM_ABI any(_ValueType&& __value) : __h_(nullptr) { __any_imp::_Handler<_Tp>::__create(*this, std::forward<_ValueType>(__value)); } diff --git a/libcxx/include/module.modulemap.in b/libcxx/include/module.modulemap.in index 58fc4941cb7d8..b622680a4920b 100644 --- a/libcxx/include/module.modulemap.in +++ b/libcxx/include/module.modulemap.in @@ -1549,6 +1549,7 @@ module std [system] { module sortable { header "__iterator/sortable.h" } module static_bounded_iter { header "__iterator/static_bounded_iter.h" } module unreachable_sentinel { header "__iterator/unreachable_sentinel.h" } + module capacity_aware_iterator { header "__iterator/capacity_aware_iterator.h" } module wrap_iter { header "__iterator/wrap_iter.h" } header "iterator" diff --git a/libcxx/include/optional b/libcxx/include/optional index 12fbcdfa5c5d6..b851a858ed26a 100644 --- a/libcxx/include/optional +++ b/libcxx/include/optional @@ -264,7 +264,6 @@ namespace std { # include <__compare/three_way_comparable.h> # include <__concepts/invocable.h> # include <__config> -# include <__cstddef/ptrdiff_t.h> # include <__exception/exception.h> # include <__format/range_format.h> # include <__functional/hash.h> @@ -272,6 +271,7 @@ namespace std { # include <__functional/unary_function.h> # include <__fwd/functional.h> # include <__iterator/bounded_iter.h> +# include <__iterator/capacity_aware_iterator.h> # include <__iterator/wrap_iter.h> # include <__memory/addressof.h> # include <__memory/construct_at.h> @@ -722,8 +722,8 @@ public: using iterator = __bounded_iter<__wrap_iter<__pointer>>; using const_iterator = __bounded_iter<__wrap_iter<__const_pointer>>; # else - using iterator = __wrap_iter<__pointer>; - using const_iterator = __wrap_iter<__const_pointer>; + using iterator = __capacity_aware_iterator<__pointer, optional<_Tp>, 1>; + using const_iterator = __capacity_aware_iterator<__const_pointer, optional<_Tp>, 1>; # endif // [optional.iterators], iterator support @@ -737,7 +737,7 @@ public: __wrap_iter<__pointer>(__ptr), __wrap_iter<__pointer>(__ptr) + (__derived_self.has_value() ? 1 : 0)); # else - return iterator(__ptr); + return std::__make_capacity_aware_iterator<__pointer, optional<_Tp>, 1>(__ptr); # endif } @@ -751,7 +751,7 @@ public: __wrap_iter<__const_pointer>(__ptr), __wrap_iter<__const_pointer>(__ptr) + (__derived_self.has_value() ? 1 : 0)); # else - return const_iterator(__ptr); + return std::__make_capacity_aware_iterator<__const_pointer, optional<_Tp>, 1>(__ptr); # endif } @@ -772,7 +772,7 @@ public: # ifdef _LIBCPP_ABI_BOUNDED_ITERATORS_IN_OPTIONAL using iterator = __bounded_iter<__wrap_iter<__pointer>>; # else - using iterator = __wrap_iter<__pointer>; + using iterator = __capacity_aware_iterator<__pointer, optional<_Tp&>, 1>; # endif // [optional.ref.iterators], iterator support @@ -787,7 +787,7 @@ public: __wrap_iter<__pointer>(__ptr), __wrap_iter<__pointer>(__ptr) + (__derived_self.has_value() ? 1 : 0)); # else - return iterator(__ptr); + return std::__make_capacity_aware_iterator<__pointer, optional<_Tp&>, 1>(__pointer(__ptr)); # endif } diff --git a/libcxx/test/benchmarks/algorithms/make_heap.bench.cpp b/libcxx/test/benchmarks/algorithms/make_heap.bench.cpp deleted file mode 100644 index 64d559620c512..0000000000000 --- a/libcxx/test/benchmarks/algorithms/make_heap.bench.cpp +++ /dev/null @@ -1,38 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// UNSUPPORTED: c++03, c++11, c++14, c++17 - -#include - -#include "common.h" - -namespace { -template -struct MakeHeap { - size_t Quantity; - - void run(benchmark::State& state) const { - runOpOnCopies(state, Quantity, Order(), BatchSize::CountElements, [](auto& Copy) { - std::make_heap(Copy.begin(), Copy.end()); - }); - } - - std::string name() const { - return "BM_MakeHeap" + ValueType::name() + Order::name() + "_" + std::to_string(Quantity); - }; -}; -} // namespace - -int main(int argc, char** argv) { - benchmark::Initialize(&argc, argv); - if (benchmark::ReportUnrecognizedArguments(argc, argv)) - return 1; - makeCartesianProductBenchmark(Quantities); - benchmark::RunSpecifiedBenchmarks(); -} diff --git a/libcxx/test/benchmarks/algorithms/ranges_make_heap.bench.cpp b/libcxx/test/benchmarks/algorithms/ranges_make_heap.bench.cpp deleted file mode 100644 index c04ea369fea0c..0000000000000 --- a/libcxx/test/benchmarks/algorithms/ranges_make_heap.bench.cpp +++ /dev/null @@ -1,38 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// UNSUPPORTED: c++03, c++11, c++14, c++17 - -#include - -#include "common.h" - -namespace { -template -struct RangesMakeHeap { - size_t Quantity; - - void run(benchmark::State& state) const { - runOpOnCopies(state, Quantity, Order(), BatchSize::CountElements, [](auto& Copy) { - std::ranges::make_heap(Copy); - }); - } - - std::string name() const { - return "BM_RangesMakeHeap" + ValueType::name() + Order::name() + "_" + std::to_string(Quantity); - }; -}; -} // namespace - -int main(int argc, char** argv) { - benchmark::Initialize(&argc, argv); - if (benchmark::ReportUnrecognizedArguments(argc, argv)) - return 1; - makeCartesianProductBenchmark(Quantities); - benchmark::RunSpecifiedBenchmarks(); -} diff --git a/libcxx/test/benchmarks/algorithms/ranges_pop_heap.bench.cpp b/libcxx/test/benchmarks/algorithms/ranges_pop_heap.bench.cpp deleted file mode 100644 index ab3ae6f7c30ae..0000000000000 --- a/libcxx/test/benchmarks/algorithms/ranges_pop_heap.bench.cpp +++ /dev/null @@ -1,38 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// UNSUPPORTED: c++03, c++11, c++14, c++17 - -#include - -#include "common.h" - -namespace { -template -struct RangesPopHeap { - size_t Quantity; - - void run(benchmark::State& state) const { - runOpOnCopies(state, Quantity, Order(), BatchSize::CountElements, [](auto& Copy) { - for (auto B = Copy.begin(), I = Copy.end(); I != B; --I) { - std::ranges::pop_heap(B, I); - } - }); - } - - std::string name() const { return "BM_RangesPopHeap" + ValueType::name() + "_" + std::to_string(Quantity); }; -}; -} // namespace - -int main(int argc, char** argv) { - benchmark::Initialize(&argc, argv); - if (benchmark::ReportUnrecognizedArguments(argc, argv)) - return 1; - makeCartesianProductBenchmark(Quantities); - benchmark::RunSpecifiedBenchmarks(); -} diff --git a/libcxx/test/benchmarks/algorithms/ranges_push_heap.bench.cpp b/libcxx/test/benchmarks/algorithms/ranges_push_heap.bench.cpp deleted file mode 100644 index 8139ba32cb974..0000000000000 --- a/libcxx/test/benchmarks/algorithms/ranges_push_heap.bench.cpp +++ /dev/null @@ -1,42 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// UNSUPPORTED: c++03, c++11, c++14, c++17 - -#include - -#include "common.h" - -namespace { -template -struct RangesPushHeap { - size_t Quantity; - - void run(benchmark::State& state) const { - runOpOnCopies(state, Quantity, Order(), BatchSize::CountElements, [](auto& Copy) { - for (auto I = Copy.begin(), E = Copy.end(); I != E; ++I) { - std::ranges::push_heap(Copy.begin(), I + 1); - } - }); - } - - bool skip() const { return Order() == ::Order::Heap; } - - std::string name() const { - return "BM_RangesPushHeap" + ValueType::name() + Order::name() + "_" + std::to_string(Quantity); - }; -}; -} // namespace - -int main(int argc, char** argv) { - benchmark::Initialize(&argc, argv); - if (benchmark::ReportUnrecognizedArguments(argc, argv)) - return 1; - makeCartesianProductBenchmark(Quantities); - benchmark::RunSpecifiedBenchmarks(); -} diff --git a/libcxx/test/benchmarks/algorithms/sorting/make_heap.bench.cpp b/libcxx/test/benchmarks/algorithms/sorting/make_heap.bench.cpp new file mode 100644 index 0000000000000..90bc8ee749eef --- /dev/null +++ b/libcxx/test/benchmarks/algorithms/sorting/make_heap.bench.cpp @@ -0,0 +1,84 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 + +#include +#include +#include +#include +#include +#include + +#include "benchmark/benchmark.h" +#include "common.h" + +int main(int argc, char** argv) { + // Benchmark std::make_heap on various types of data + // + // We perform this benchmark in a batch because we need to restore the + // state of the container after the operation. + { + auto bm = [](std::string name, auto generate_data, auto pred) { + benchmark::RegisterBenchmark( + name, + [generate_data, pred](auto& st) { + std::size_t const size = st.range(0); + constexpr std::size_t BatchSize = 32; + using ValueType = typename Container::value_type; + std::vector data = generate_data(size); + std::array c; + std::fill_n(c.begin(), BatchSize, Container(data.begin(), data.end())); + + while (st.KeepRunningBatch(BatchSize)) { + for (std::size_t i = 0; i != BatchSize; ++i) { + benchmark::DoNotOptimize(c[i]); + std::make_heap(c[i].begin(), c[i].end(), pred); + benchmark::DoNotOptimize(c[i]); + } + + st.PauseTiming(); + for (std::size_t i = 0; i != BatchSize; ++i) { + std::copy(data.begin(), data.end(), c[i].begin()); + } + st.ResumeTiming(); + } + }) + ->Arg(8) + ->Arg(1024) + ->Arg(8192); + }; + + auto register_bm = [&](auto generate, std::string variant) { + auto gen2 = [generate](auto size) { + std::vector data = generate(size); + return std::vector(data.begin(), data.end()); + }; + auto name = [variant](std::string op) { return op + " (" + variant + ")"; }; + bm.operator()>(name("std::make_heap(vector)"), generate, std::less{}); + bm.operator()>(name("std::make_heap(vector)"), gen2, std::less{}); + bm.operator()>(name("std::make_heap(deque)"), generate, std::less{}); + auto pred = [](auto lhs, auto rhs) { return lhs < rhs; }; + bm.operator()>(name("std::make_heap(vector, pred)"), generate, pred); + bm.operator()>(name("std::make_heap(vector, pred)"), gen2, pred); + bm.operator()>(name("std::make_heap(deque, pred)"), generate, pred); + }; + + register_bm(support::ascending_sorted_data, "ascending"); + register_bm(support::descending_sorted_data, "descending"); + register_bm(support::pipe_organ_data, "pipe-organ"); + register_bm(support::heap_data, "heap"); + register_bm(support::shuffled_data, "shuffled"); + register_bm(support::single_element_data, "repeated"); + } + + benchmark::Initialize(&argc, argv); + benchmark::RunSpecifiedBenchmarks(); + benchmark::Shutdown(); + return 0; +} diff --git a/libcxx/test/benchmarks/format/format_to.bench.cpp b/libcxx/test/benchmarks/format/format_to.bench.cpp index 5b06e826715e7..d1cbb49cad4e2 100644 --- a/libcxx/test/benchmarks/format/format_to.bench.cpp +++ b/libcxx/test/benchmarks/format/format_to.bench.cpp @@ -84,24 +84,24 @@ static void BM_format_to_string_pointer(benchmark::State& state) { /*** Main ***/ -BENCHMARK(BM_format_to_string_back_inserter)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_back_inserter>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_back_inserter>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_begin)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_begin>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_begin>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_span)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_pointer)->RangeMultiplier(2)->Range(1, 1 << 20); +BENCHMARK(BM_format_to_string_back_inserter)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_back_inserter>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_back_inserter>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_begin)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_begin>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_begin>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_span)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_pointer)->Arg(1)->Arg(16384)->Arg(1048576); #ifndef TEST_HAS_NO_WIDE_CHARACTERS -BENCHMARK(BM_format_to_string_back_inserter)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_back_inserter>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_back_inserter>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_begin)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_begin>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_begin>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_span)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_string_pointer)->RangeMultiplier(2)->Range(1, 1 << 20); +BENCHMARK(BM_format_to_string_back_inserter)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_back_inserter>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_back_inserter>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_begin)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_begin>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_begin>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_span)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_string_pointer)->Arg(1)->Arg(16384)->Arg(1048576); #endif BENCHMARK_MAIN(); diff --git a/libcxx/test/benchmarks/format/format_to_n.bench.cpp b/libcxx/test/benchmarks/format/format_to_n.bench.cpp index 30f6ce74f7c93..748c72f2c2866 100644 --- a/libcxx/test/benchmarks/format/format_to_n.bench.cpp +++ b/libcxx/test/benchmarks/format/format_to_n.bench.cpp @@ -84,24 +84,24 @@ static void BM_format_to_n_string_pointer(benchmark::State& state) { /*** Main ***/ -BENCHMARK(BM_format_to_n_string_back_inserter)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_back_inserter>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_back_inserter>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_begin)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_begin>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_begin>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_span)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_pointer)->RangeMultiplier(2)->Range(1, 1 << 20); +BENCHMARK(BM_format_to_n_string_back_inserter)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_back_inserter>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_back_inserter>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_begin)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_begin>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_begin>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_span)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_pointer)->Arg(1)->Arg(16384)->Arg(1048576); #ifndef TEST_HAS_NO_WIDE_CHARACTERS -BENCHMARK(BM_format_to_n_string_back_inserter)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_back_inserter>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_back_inserter>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_begin)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_begin>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_begin>)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_span)->RangeMultiplier(2)->Range(1, 1 << 20); -BENCHMARK(BM_format_to_n_string_pointer)->RangeMultiplier(2)->Range(1, 1 << 20); +BENCHMARK(BM_format_to_n_string_back_inserter)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_back_inserter>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_back_inserter>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_begin)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_begin>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_begin>)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_span)->Arg(1)->Arg(16384)->Arg(1048576); +BENCHMARK(BM_format_to_n_string_pointer)->Arg(1)->Arg(16384)->Arg(1048576); #endif BENCHMARK_MAIN(); diff --git a/libcxx/test/benchmarks/format/formatted_size.bench.cpp b/libcxx/test/benchmarks/format/formatted_size.bench.cpp index e244f0bbb8cb2..9c52f386a782a 100644 --- a/libcxx/test/benchmarks/format/formatted_size.bench.cpp +++ b/libcxx/test/benchmarks/format/formatted_size.bench.cpp @@ -28,9 +28,9 @@ static void BM_formatted_size_string(benchmark::State& state) { state.SetBytesProcessed(state.iterations() * size * sizeof(CharT)); } -BENCHMARK(BM_formatted_size_string)->RangeMultiplier(2)->Range(1, 1 << 20); +BENCHMARK(BM_formatted_size_string)->Arg(1)->Arg(16384)->Arg(1048576); #ifndef TEST_HAS_NO_WIDE_CHARACTERS -BENCHMARK(BM_formatted_size_string)->RangeMultiplier(2)->Range(1, 1 << 20); +BENCHMARK(BM_formatted_size_string)->Arg(1)->Arg(16384)->Arg(1048576); #endif BENCHMARK_MAIN(); diff --git a/libcxx/test/benchmarks/format/formatter_float.bench.cpp b/libcxx/test/benchmarks/format/formatter_float.bench.cpp index 77c067e7bc03e..f8c3284391580 100644 --- a/libcxx/test/benchmarks/format/formatter_float.bench.cpp +++ b/libcxx/test/benchmarks/format/formatter_float.bench.cpp @@ -17,245 +17,327 @@ #include #include -#include "../CartesianBenchmarks.h" #include "benchmark/benchmark.h" -// *** Localization *** -enum class LocalizationE { False, True }; -struct AllLocalizations : EnumValuesAsTuple { - static constexpr const char* Names[] = {"LocFalse", "LocTrue"}; -}; - -template -struct Localization {}; - -template <> -struct Localization { - static constexpr const char* fmt = ""; -}; - -template <> -struct Localization { - static constexpr const char* fmt = "L"; -}; - -// *** Types *** -enum class TypeE { Float, Double, LongDouble }; -// TODO FMT Set to 3 after to_chars has long double suport. -struct AllTypes : EnumValuesAsTuple { - static constexpr const char* Names[] = {"Float", "Double", "LongDouble"}; -}; - -template -struct Type {}; +template +inline constexpr std::string to_string = ""; template <> -struct Type { - using type = float; -}; +inline constexpr std::string to_string = "float"; template <> -struct Type { - using type = double; -}; +inline constexpr std::string to_string = "double"; -template <> -struct Type { - using type = long double; -}; - -// *** Values *** enum class ValueE { Inf, Random }; -struct AllValues : EnumValuesAsTuple { - static constexpr const char* Names[] = {"Inf", "Random"}; -}; - -template -struct Value {}; - -template <> -struct Value { - template - static std::array make_data() { - std::array result; - std::fill(result.begin(), result.end(), -std::numeric_limits::infinity()); - return result; - } -}; - -template <> -struct Value { - template - static std::array make_data() { - std::random_device seed; - std::mt19937 generator(seed()); - std::uniform_int_distribution> distribution; - - std::array result; - std::generate(result.begin(), result.end(), [&] { - while (true) { - auto val = std::bit_cast(distribution(generator)); - if (std::isfinite(val)) - return val; - } - }); - return result; - } -}; - -// *** Display Type *** -enum class DisplayTypeE { - Default, - Hex, - Scientific, - Fixed, - General, -}; -struct AllDisplayTypes : EnumValuesAsTuple { - static constexpr const char* Names[] = { - "DisplayDefault", "DisplayHex", "DisplayScientific", "DisplayFixed", "DisplayGeneral"}; -}; - -template -struct DisplayType {}; - -template <> -struct DisplayType { - static constexpr const char* fmt = ""; -}; - -template <> -struct DisplayType { - static constexpr const char* fmt = "a"; -}; - -template <> -struct DisplayType { - static constexpr const char* fmt = "e"; -}; - -template <> -struct DisplayType { - static constexpr const char* fmt = "f"; -}; - -template <> -struct DisplayType { - static constexpr const char* fmt = "g"; -}; - -// *** Alignment *** -enum class AlignmentE { None, Left, Center, Right, ZeroPadding }; -struct AllAlignments : EnumValuesAsTuple { - static constexpr const char* Names[] = { - "AlignNone", "AlignmentLeft", "AlignmentCenter", "AlignmentRight", "ZeroPadding"}; -}; - -template -struct Alignment {}; - -template <> -struct Alignment { - static constexpr const char* fmt = ""; -}; - -template <> -struct Alignment { - // Width > PrecisionE::Huge - static constexpr const char* fmt = "0<17500"; -}; - -template <> -struct Alignment { - // Width > PrecisionE::Huge - static constexpr const char* fmt = "0^17500"; -}; - -template <> -struct Alignment { - // Width > PrecisionE::Huge - static constexpr const char* fmt = "0>17500"; -}; - -template <> -struct Alignment { - // Width > PrecisionE::Huge - static constexpr const char* fmt = "017500"; -}; - -enum class PrecisionE { None, Zero, Small, Huge }; -struct AllPrecisions : EnumValuesAsTuple { - static constexpr const char* Names[] = {"PrecNone", "PrecZero", "PrecSmall", "PrecHuge"}; -}; - -template -struct Precision {}; - -template <> -struct Precision { - static constexpr const char* fmt = ""; -}; - -template <> -struct Precision { - static constexpr const char* fmt = ".0"; -}; - -template <> -struct Precision { - static constexpr const char* fmt = ".10"; -}; - -template <> -struct Precision { - // The maximum precision for a minimal sub normal long double is +/- 0x1p-16494. - // This value is always larger than that value forcing the trailing zero path - // to be executed. - static constexpr const char* fmt = ".17000"; -}; - -template -struct FloatingPoint { - using F = typename Type::type; - - void run(benchmark::State& state) const { - std::array data{Value::template make_data()}; - std::array output; - - while (state.KeepRunningBatch(1000)) - for (F value : data) - benchmark::DoNotOptimize(std::format_to(output.begin(), std::string_view{fmt.data(), fmt.size()}, value)); - } - - std::string name() const { - return "FloatingPoint" + L::name() + DT::name() + T::name() + V::name() + A::name() + P::name(); - } - - static constexpr std::string make_fmt() { - return std::string("{:") + Alignment::fmt + Precision::fmt + Localization::fmt + - DisplayType::fmt + "}"; - } - - static constexpr auto fmt = []() { - constexpr size_t s = make_fmt().size(); - std::array r; - std::ranges::copy(make_fmt(), r.begin()); - return r; - }(); -}; int main(int argc, char** argv) { - benchmark::Initialize(&argc, argv); - if (benchmark::ReportUnrecognizedArguments(argc, argv)) - return 1; - - makeCartesianProductBenchmark(); + auto bm = [](std::type_identity, ValueE v, std::string fmt) { + benchmark::RegisterBenchmark( + "std::format(" + to_string + ") (fmt: " + fmt + ")", [fmt, v](benchmark::State& state) { + std::array data = [&] { + std::array result; + if (v == ValueE::Inf) { + std::fill(result.begin(), result.end(), -std::numeric_limits::infinity()); + } else { + std::mt19937 generator(123456); + std::uniform_int_distribution< + std::conditional_t> + distribution; + + std::generate(result.begin(), result.end(), [&] { + while (true) { + auto val = std::bit_cast(distribution(generator)); + if (std::isfinite(val)) + return val; + } + }); + } + return result; + }(); + std::array output; + + while (state.KeepRunningBatch(1000)) + for (auto value : data) + benchmark::DoNotOptimize(std::vformat_to(output.begin(), fmt, std::make_format_args(value))); + }); + }; + + bm(std::type_identity(), ValueE::Inf, "{:.0}"); + bm(std::type_identity(), ValueE::Random, "{:.0}"); + bm(std::type_identity(), ValueE::Inf, "{:0<17500.0}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0}"); + bm(std::type_identity(), ValueE::Inf, "{:0^17500.0}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0}"); + bm(std::type_identity(), ValueE::Inf, "{:0>17500.0}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0}"); + bm(std::type_identity(), ValueE::Inf, "{:017500.0}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0}"); + + bm(std::type_identity(), ValueE::Random, "{:.10}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10}"); + + bm(std::type_identity(), ValueE::Random, "{:.17000}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.17000}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.17000}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.17000}"); + bm(std::type_identity(), ValueE::Random, "{:017500.17000}"); + + bm(std::type_identity(), ValueE::Random, "{:.0L}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0L}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0L}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0L}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0L}"); + + bm(std::type_identity(), ValueE::Random, "{:.10L}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10L}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10L}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10L}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10L}"); + + bm(std::type_identity(), ValueE::Random, "{:.17000L}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.17000L}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.17000L}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.17000L}"); + bm(std::type_identity(), ValueE::Random, "{:017500.17000L}"); + + bm(std::type_identity(), ValueE::Random, "{:.0a}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0a}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0a}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0a}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0a}"); + + bm(std::type_identity(), ValueE::Random, "{:.10a}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10a}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10a}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10a}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10a}"); + + bm(std::type_identity(), ValueE::Random, "{:.0La}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0La}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0La}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0La}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0La}"); + + bm(std::type_identity(), ValueE::Random, "{:.10La}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10La}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10La}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10La}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10La}"); + + bm(std::type_identity(), ValueE::Random, "{:.0e}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0e}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0e}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0e}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0e}"); + + bm(std::type_identity(), ValueE::Random, "{:.10e}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10e}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10e}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10e}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10e}"); + + bm(std::type_identity(), ValueE::Random, "{:.0Le}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0Le}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0Le}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0Le}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0Le}"); + + bm(std::type_identity(), ValueE::Random, "{:.10Le}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10Le}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10Le}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10Le}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10Le}"); + + bm(std::type_identity(), ValueE::Random, "{:.0f}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0f}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0f}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0f}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0f}"); + + bm(std::type_identity(), ValueE::Random, "{:.10f}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10f}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10f}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10f}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10f}"); + + bm(std::type_identity(), ValueE::Random, "{:.0Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0Lf}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0Lf}"); + + bm(std::type_identity(), ValueE::Random, "{:.10Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10Lf}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10Lf}"); + + bm(std::type_identity(), ValueE::Random, "{:.0g}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0g}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0g}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0g}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0g}"); + + bm(std::type_identity(), ValueE::Random, "{:.10g}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10g}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10g}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10g}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10g}"); + + bm(std::type_identity(), ValueE::Random, "{:.0Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0Lg}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0Lg}"); + + bm(std::type_identity(), ValueE::Random, "{:.10Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10Lg}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10Lg}"); + + bm(std::type_identity(), ValueE::Inf, "{:.0}"); + bm(std::type_identity(), ValueE::Random, "{:.0}"); + bm(std::type_identity(), ValueE::Inf, "{:0<17500.0}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0}"); + bm(std::type_identity(), ValueE::Inf, "{:0^17500.0}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0}"); + bm(std::type_identity(), ValueE::Inf, "{:0>17500.0}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0}"); + bm(std::type_identity(), ValueE::Inf, "{:017500.0}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0}"); + + bm(std::type_identity(), ValueE::Random, "{:.10}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10}"); + + bm(std::type_identity(), ValueE::Random, "{:.17000}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.17000}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.17000}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.17000}"); + bm(std::type_identity(), ValueE::Random, "{:017500.17000}"); + + bm(std::type_identity(), ValueE::Random, "{:.0L}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0L}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0L}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0L}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0L}"); + + bm(std::type_identity(), ValueE::Random, "{:.10L}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10L}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10L}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10L}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10L}"); + + bm(std::type_identity(), ValueE::Random, "{:.17000L}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.17000L}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.17000L}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.17000L}"); + bm(std::type_identity(), ValueE::Random, "{:017500.17000L}"); + + bm(std::type_identity(), ValueE::Random, "{:.0a}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0a}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0a}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0a}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0a}"); + + bm(std::type_identity(), ValueE::Random, "{:.10a}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10a}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10a}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10a}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10a}"); + + bm(std::type_identity(), ValueE::Random, "{:.0La}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0La}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0La}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0La}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0La}"); + + bm(std::type_identity(), ValueE::Random, "{:.10La}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10La}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10La}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10La}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10La}"); + + bm(std::type_identity(), ValueE::Random, "{:.0e}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0e}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0e}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0e}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0e}"); + + bm(std::type_identity(), ValueE::Random, "{:.10e}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10e}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10e}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10e}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10e}"); + + bm(std::type_identity(), ValueE::Random, "{:.0Le}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0Le}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0Le}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0Le}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0Le}"); + + bm(std::type_identity(), ValueE::Random, "{:.10Le}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10Le}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10Le}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10Le}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10Le}"); + + bm(std::type_identity(), ValueE::Random, "{:.0f}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0f}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0f}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0f}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0f}"); + + bm(std::type_identity(), ValueE::Random, "{:.10f}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10f}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10f}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10f}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10f}"); + + bm(std::type_identity(), ValueE::Random, "{:.0Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0Lf}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0Lf}"); + + bm(std::type_identity(), ValueE::Random, "{:.10Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10Lf}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10Lf}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10Lf}"); + + bm(std::type_identity(), ValueE::Random, "{:.0g}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0g}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0g}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0g}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0g}"); + + bm(std::type_identity(), ValueE::Random, "{:.10g}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10g}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10g}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10g}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10g}"); + + bm(std::type_identity(), ValueE::Random, "{:.0Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.0Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.0Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.0Lg}"); + bm(std::type_identity(), ValueE::Random, "{:017500.0Lg}"); + + bm(std::type_identity(), ValueE::Random, "{:.10Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0<17500.10Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0^17500.10Lg}"); + bm(std::type_identity(), ValueE::Random, "{:0>17500.10Lg}"); + bm(std::type_identity(), ValueE::Random, "{:017500.10Lg}"); + benchmark::Initialize(&argc, argv); benchmark::RunSpecifiedBenchmarks(); + benchmark::Shutdown(); + return 0; } diff --git a/libcxx/test/benchmarks/format/formatter_int.bench.cpp b/libcxx/test/benchmarks/format/formatter_int.bench.cpp index 6df0187667aa1..5e0667873279c 100644 --- a/libcxx/test/benchmarks/format/formatter_int.bench.cpp +++ b/libcxx/test/benchmarks/format/formatter_int.bench.cpp @@ -12,7 +12,6 @@ #include #include -#include "../CartesianBenchmarks.h" #include "benchmark/benchmark.h" #include "test_macros.h" @@ -60,154 +59,90 @@ BENCHMARK(BM_Basic<__uint128_t>); BENCHMARK(BM_Basic<__int128_t>); #endif -// *** Localization *** -enum class LocalizationE { False, True }; -struct AllLocalizations : EnumValuesAsTuple { - static constexpr const char* Names[] = {"LocFalse", "LocTrue"}; -}; - -template -struct Localization {}; - -template <> -struct Localization { - static constexpr const char* fmt = ""; -}; - -template <> -struct Localization { - static constexpr const char* fmt = "L"; -}; - -// *** Base *** -enum class BaseE { - Binary, - Octal, - Decimal, - Hex, - HexUpper, -}; -struct AllBases : EnumValuesAsTuple { - static constexpr const char* Names[] = {"BaseBin", "BaseOct", "BaseDec", "BaseHex", "BaseHexUpper"}; -}; - -template -struct Base {}; - -template <> -struct Base { - static constexpr const char* fmt = "b"; -}; - -template <> -struct Base { - static constexpr const char* fmt = "o"; -}; - -template <> -struct Base { - static constexpr const char* fmt = "d"; -}; - -template <> -struct Base { - static constexpr const char* fmt = "x"; -}; - -template <> -struct Base { - static constexpr const char* fmt = "X"; -}; - -// *** Types *** -enum class TypeE { Int64, Uint64 }; -struct AllTypes : EnumValuesAsTuple { - static constexpr const char* Names[] = {"Int64", "Uint64"}; -}; - -template -struct Type {}; +template +inline constexpr std::string to_string = ""; template <> -struct Type { - using type = int64_t; - - static std::array make_data() { return generate(); } -}; +inline constexpr std::string to_string = "int64_t"; template <> -struct Type { - using type = uint64_t; - - static std::array make_data() { return generate(); } -}; - -// *** Alignment *** -enum class AlignmentE { None, Left, Center, Right, ZeroPadding }; -struct AllAlignments : EnumValuesAsTuple { - static constexpr const char* Names[] = { - "AlignNone", "AlignmentLeft", "AlignmentCenter", "AlignmentRight", "ZeroPadding"}; -}; - -template -struct Alignment {}; - -template <> -struct Alignment { - static constexpr const char* fmt = ""; -}; - -template <> -struct Alignment { - static constexpr const char* fmt = "0<512"; -}; - -template <> -struct Alignment { - static constexpr const char* fmt = "0^512"; -}; - -template <> -struct Alignment { - static constexpr const char* fmt = "0>512"; -}; - -template <> -struct Alignment { - static constexpr const char* fmt = "0512"; -}; - -template -struct Integral { - void run(benchmark::State& state) const { - std::array data{Type::make_data()}; - std::array output; - - while (state.KeepRunningBatch(data.size())) - for (auto value : data) - benchmark::DoNotOptimize(std::format_to(output.begin(), std::string_view{fmt.data(), fmt.size()}, value)); - } - - std::string name() const { return "Integral" + L::name() + B::name() + A::name() + T::name(); } - - static constexpr std::string make_fmt() { - return std::string("{:") + Alignment::fmt + Localization::fmt + Base::fmt + "}"; - } - - static constexpr auto fmt = []() { - constexpr size_t s = make_fmt().size(); - std::array r; - std::ranges::copy(make_fmt(), r.begin()); - return r; - }(); -}; +inline constexpr std::string to_string = "uint64_t"; int main(int argc, char** argv) { - benchmark::Initialize(&argc, argv); - if (benchmark::ReportUnrecognizedArguments(argc, argv)) - return 1; - - makeCartesianProductBenchmark(); + auto bm = [](std::type_identity, std::string fmt) { + benchmark::RegisterBenchmark( + "std::format(" + to_string + ") (fmt: " + fmt + ")", [fmt](benchmark::State& state) { + std::array data = generate(); + std::array output; + + while (state.KeepRunningBatch(data.size())) + for (auto value : data) + benchmark::DoNotOptimize(std::vformat_to(output.begin(), fmt, std::make_format_args(value))); + }); + }; + + bm(std::type_identity(), "{:b}"); + bm(std::type_identity(), "{:0<512b}"); + bm(std::type_identity(), "{:0^512b}"); + bm(std::type_identity(), "{:0>512b}"); + bm(std::type_identity(), "{:0512b}"); + + bm(std::type_identity(), "{:Lb}"); + bm(std::type_identity(), "{:0<512Lb}"); + bm(std::type_identity(), "{:0^512Lb}"); + bm(std::type_identity(), "{:0>512Lb}"); + bm(std::type_identity(), "{:0512Lb}"); + + bm(std::type_identity(), "{:o}"); + bm(std::type_identity(), "{:0<512o}"); + bm(std::type_identity(), "{:0^512o}"); + bm(std::type_identity(), "{:0>512o}"); + bm(std::type_identity(), "{:0512o}"); + + bm(std::type_identity(), "{:Lo}"); + bm(std::type_identity(), "{:0<512Lo}"); + bm(std::type_identity(), "{:0^512Lo}"); + bm(std::type_identity(), "{:0>512Lo}"); + bm(std::type_identity(), "{:0512Lo}"); + + bm(std::type_identity(), "{:d}"); + bm(std::type_identity(), "{:0<512d}"); + bm(std::type_identity(), "{:0^512d}"); + bm(std::type_identity(), "{:0>512d}"); + bm(std::type_identity(), "{:0512d}"); + + bm(std::type_identity(), "{:Ld}"); + bm(std::type_identity(), "{:0<512Ld}"); + bm(std::type_identity(), "{:0^512Ld}"); + bm(std::type_identity(), "{:0>512Ld}"); + bm(std::type_identity(), "{:0512Ld}"); + + bm(std::type_identity(), "{:x}"); + bm(std::type_identity(), "{:0<512x}"); + bm(std::type_identity(), "{:0^512x}"); + bm(std::type_identity(), "{:0>512x}"); + bm(std::type_identity(), "{:0512x}"); + + bm(std::type_identity(), "{:Lx}"); + bm(std::type_identity(), "{:0<512Lx}"); + bm(std::type_identity(), "{:0^512Lx}"); + bm(std::type_identity(), "{:0>512Lx}"); + bm(std::type_identity(), "{:0512Lx}"); + + bm(std::type_identity(), "{:X}"); + bm(std::type_identity(), "{:0<512X}"); + bm(std::type_identity(), "{:0^512X}"); + bm(std::type_identity(), "{:0>512X}"); + bm(std::type_identity(), "{:0512X}"); + + bm(std::type_identity(), "{:LX}"); + bm(std::type_identity(), "{:0<512LX}"); + bm(std::type_identity(), "{:0^512LX}"); + bm(std::type_identity(), "{:0>512LX}"); + bm(std::type_identity(), "{:0512LX}"); + benchmark::Initialize(&argc, argv); benchmark::RunSpecifiedBenchmarks(); + benchmark::Shutdown(); + return 0; } diff --git a/libcxx/test/benchmarks/format/std_format_spec_string_unicode.bench.cpp b/libcxx/test/benchmarks/format/std_format_spec_string_unicode.bench.cpp index 1c859e1b2b833..eb3ffc37c882e 100644 --- a/libcxx/test/benchmarks/format/std_format_spec_string_unicode.bench.cpp +++ b/libcxx/test/benchmarks/format/std_format_spec_string_unicode.bench.cpp @@ -6,17 +6,17 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 -# include -# include -# include +// UNSUPPORTED: libcpp-has-no-unicode -# include "benchmark/benchmark.h" -# include "make_string.h" -# include "test_macros.h" +#include +#include +#include -# define SV(S) MAKE_STRING_VIEW(CharT, S) +#include "benchmark/benchmark.h" +#include "make_string.h" +#include "test_macros.h" -#if _LIBCPP_HAS_UNICODE +#define SV(S) MAKE_STRING_VIEW(CharT, S) // generated with https://generator.lorem-ipsum.info/_latin @@ -285,16 +285,12 @@ BENCHMARK(BM_cyrillic_text); BENCHMARK(BM_japanese_text); BENCHMARK(BM_emoji_text); -# ifndef TEST_HAS_NO_WIDE_CHARACTERS +#ifndef TEST_HAS_NO_WIDE_CHARACTERS BENCHMARK(BM_ascii_text); BENCHMARK(BM_unicode_text); BENCHMARK(BM_cyrillic_text); BENCHMARK(BM_japanese_text); BENCHMARK(BM_emoji_text); -# endif +#endif BENCHMARK_MAIN(); - -#else -int main(int, char**) { return 0; } -#endif diff --git a/libcxx/test/benchmarks/format/std_format_spec_string_unicode_escape.bench.cpp b/libcxx/test/benchmarks/format/std_format_spec_string_unicode_escape.bench.cpp index 4a1eb47a71ff0..aa91229798903 100644 --- a/libcxx/test/benchmarks/format/std_format_spec_string_unicode_escape.bench.cpp +++ b/libcxx/test/benchmarks/format/std_format_spec_string_unicode_escape.bench.cpp @@ -8,21 +8,20 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 +// UNSUPPORTED: libcpp-has-no-unicode + // This test formats a larger piece of text in "escaped" mode. It uses several // datasets to give an impression how the amount of multibyte UTF-8 sequences // and larger grapheme clusters affect the performance. -# include -# include -# include - -# include "benchmark/benchmark.h" -# include "make_string.h" -# include "test_macros.h" +#include +#include +#include -#if _LIBCPP_HAS_UNICODE +#include "benchmark/benchmark.h" +#include "make_string.h" -# define SV(S) MAKE_STRING_VIEW(CharT, S) +#define SV(S) MAKE_STRING_VIEW(CharT, S) // generated with https://generator.lorem-ipsum.info/_latin @@ -288,16 +287,12 @@ BENCHMARK(BM_cyrillic_escaped); BENCHMARK(BM_japanese_escaped); BENCHMARK(BM_emoji_escaped); -# ifndef TEST_HAS_NO_WIDE_CHARACTERS +#ifndef TEST_HAS_NO_WIDE_CHARACTERS BENCHMARK(BM_ascii_escaped); BENCHMARK(BM_unicode_escaped); BENCHMARK(BM_cyrillic_escaped); BENCHMARK(BM_japanese_escaped); BENCHMARK(BM_emoji_escaped); -# endif +#endif BENCHMARK_MAIN(); - -#else -int main(int, char**) { return 0; } -#endif diff --git a/libcxx/test/benchmarks/spec.gen.py b/libcxx/test/benchmarks/spec.gen.py index 640a29e5c24c5..09d3bce3f9b22 100644 --- a/libcxx/test/benchmarks/spec.gen.py +++ b/libcxx/test/benchmarks/spec.gen.py @@ -88,5 +88,5 @@ # If there were no errors, parse the SPEC results and the `time` output into LNT-compatible format and print them. print(f'RUN: %{{libcxx-dir}}/utils/parse-spec-results %{{temp}}/result/*.train.csv --output-format=lnt > %{{temp}}/results.lnt') - print(f'RUN: %{{libcxx-dir}}/utils/parse-time-output %{{temp}}/time.txt --benchmark {benchmark} --extract instructions max_rss cycles peak_memory >> %{{temp}}/results.lnt') + print(f'RUN: %{{libcxx-dir}}/utils/parse-time-output %{{temp}}/time.txt --benchmark {benchmark.replace(".", "_")} --extract instructions max_rss cycles peak_memory >> %{{temp}}/results.lnt') print(f'RUN: cat %{{temp}}/results.lnt') diff --git a/libcxx/test/benchmarks/stop_token.bench.cpp b/libcxx/test/benchmarks/stop_token.bench.cpp index a627f80697dd5..a386c30c6c15c 100644 --- a/libcxx/test/benchmarks/stop_token.bench.cpp +++ b/libcxx/test/benchmarks/stop_token.bench.cpp @@ -42,7 +42,7 @@ void BM_stop_token_single_thread_polling_stop_requested(benchmark::State& state) } } -BENCHMARK(BM_stop_token_single_thread_polling_stop_requested)->RangeMultiplier(2)->Range(1 << 10, 1 << 24); +BENCHMARK(BM_stop_token_single_thread_polling_stop_requested)->Arg(1024)->Arg(131072)->Arg(16777216); // We have multiple threads polling for stop_requested of the same stop_token. void BM_stop_token_multi_thread_polling_stop_requested(benchmark::State& state) { @@ -91,7 +91,7 @@ void BM_stop_token_multi_thread_polling_stop_requested(benchmark::State& state) ss.request_stop(); } -BENCHMARK(BM_stop_token_multi_thread_polling_stop_requested)->RangeMultiplier(2)->Range(1 << 10, 1 << 24); +BENCHMARK(BM_stop_token_multi_thread_polling_stop_requested)->Arg(1024)->Arg(131072)->Arg(16777216); // We have a single thread created by std::jthread consuming the stop_token: // registering/deregistering callbacks, one at a time. @@ -117,7 +117,7 @@ void BM_stop_token_single_thread_reg_unreg_callback(benchmark::State& state) { } } } -BENCHMARK(BM_stop_token_single_thread_reg_unreg_callback)->RangeMultiplier(2)->Range(1 << 10, 1 << 24); +BENCHMARK(BM_stop_token_single_thread_reg_unreg_callback)->Arg(1024)->Arg(131072)->Arg(16777216); // At startup, it creates a single stop_source which it will then pass an associated stop_token to every // request. @@ -182,6 +182,6 @@ void BM_stop_token_async_reg_unreg_callback(benchmark::State& state) { ss.request_stop(); } -BENCHMARK(BM_stop_token_async_reg_unreg_callback)->RangeMultiplier(2)->Range(1 << 10, 1 << 24); +BENCHMARK(BM_stop_token_async_reg_unreg_callback)->Arg(1024)->Arg(131072)->Arg(16777216); BENCHMARK_MAIN(); diff --git a/libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp b/libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp index f5a878582666b..638137f8d4c58 100644 --- a/libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp +++ b/libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp @@ -172,6 +172,19 @@ template class UncompressibleAllocator : public std::allocator { }; }; +// Helper function to check pretty printing of short strings returned by +// debugger-called functions. +std::string return_short_string() { + return "abc"; +} + +// Helper function to check pretty printing of long strings returned by +// debugger-called functions. +std::basic_string, UncompressibleAllocator> +return_long_string() { + return "this is a string that is too long to fit in the string object"; +} + void string_test() { std::string short_string("kdjflskdjf"); // The display_hint "string" adds quotes the printed result. @@ -181,7 +194,14 @@ void string_test() { long_string("mehmet bizim dostumuz agzi kirik testimiz"); ComparePrettyPrintToChars(long_string, "\"mehmet bizim dostumuz agzi kirik testimiz\""); -} + + // GDB handles strings that are returned from a debugger called function or + // when stepping out of a function differently from string variables. These + // two tests check that pretty printing works also for this case. + CompareExpressionPrettyPrintToChars("return_short_string()", "\"abc\""); + CompareExpressionPrettyPrintToChars("return_long_string()", + "\"this is a string that is too long to fit in the string object\""); + } namespace a_namespace { // To test name-lookup in the presence of using inside a namespace. Inside this @@ -211,6 +231,14 @@ void string_view_test() { } } +std::u16string return_short_u16string() { + return u"a"; +} + +std::u16string return_long_u16string() { + return u"this is a string that is too long to fit in the string object"; +} + void u16string_test() { std::u16string test0 = u"Hello World"; ComparePrettyPrintToChars(test0, "u\"Hello World\""); @@ -221,6 +249,20 @@ void u16string_test() { std::u16string test3 = u"mehmet bizim dostumuz agzi kirik testimiz"; ComparePrettyPrintToChars(test3, ("u\"mehmet bizim dostumuz agzi kirik testimiz\"")); + // GDB handles strings that are returned from a debugger called function or + // when stepping out of a function differently from string variables. These + // two tests check that pretty printing works also for this case. + CompareExpressionPrettyPrintToChars("return_short_u16string()", "u\"a\""); + CompareExpressionPrettyPrintToChars("return_long_u16string()", + "u\"this is a string that is too long to fit in the string object\""); +} + +std::u32string return_short_u32string() { + return U"a"; +} + +std::u32string return_long_u32string() { + return U"this is a string that is too long to fit in the string object"; } void u32string_test() { @@ -235,6 +277,12 @@ void u32string_test() { ComparePrettyPrintToChars(test2, ("U\"\U00004f60\U0000597d\"")); std::u32string test3 = U"mehmet bizim dostumuz agzi kirik testimiz"; ComparePrettyPrintToChars(test3, ("U\"mehmet bizim dostumuz agzi kirik testimiz\"")); + // GDB handles strings that are returned from a debugger called function or + // when stepping out of a function differently from string variables. These + // two tests check that pretty printing works also for this case. + CompareExpressionPrettyPrintToChars("return_short_u32string()", "U\"a\""); + CompareExpressionPrettyPrintToChars("return_long_u32string()", + "U\"this is a string that is too long to fit in the string object\""); } void tuple_test() { diff --git a/libcxx/test/libcxx/iterators/capacity_aware_iter/arithmetic.pass.cpp b/libcxx/test/libcxx/iterators/capacity_aware_iter/arithmetic.pass.cpp new file mode 100644 index 0000000000000..c8451141c9844 --- /dev/null +++ b/libcxx/test/libcxx/iterators/capacity_aware_iter/arithmetic.pass.cpp @@ -0,0 +1,165 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: std-at-least-c++26 + +// template +// struct __capacity_aware_iterator; + +// Arithmetic operators + +// operator++() +// operator++(int) +// operator--() +// operator--(int) +// operator+=(difference_type) +// operator+(__capacity_aware_iterator, difference_type) +// operator+(difference_type, __capacity_aware_iterator) +// operator-=(difference_type) +// operator-(__capacity_aware_iterator, difference_type) +// operator-(__capacity_aware_iterator, __capacity_aware_iterator) + +#include <__iterator/capacity_aware_iterator.h> +#include +#include +#include + +#include "test_iterators.h" +#include "test_macros.h" + +template +constexpr bool test() { + int arr[] = {1, 2, 3, 4, 5, 6}; + constexpr size_t sz = std::size(arr); + + using CapIter = std::__capacity_aware_iterator; + + int* i = arr + 0; + + // operator++() + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i)); + + std::same_as decltype(auto) res = ++iter; + + ASSERT_NOEXCEPT(++iter); + assert(&res == &iter); + assert(*iter == 2); + } + + // operator++(int) + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i)); + + std::same_as decltype(auto) res = iter++; + + ASSERT_NOEXCEPT(iter++); + assert(*res == 1); + assert(*iter == 2); + } + + // operator--() + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i + 1)); + + std::same_as decltype(auto) res = --iter; + + ASSERT_NOEXCEPT(--iter); + assert(&iter == &res); + assert(*iter == 1); + } + + // operator--(int) + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i + 1)); + + std::same_as decltype(auto) res = iter--; + + ASSERT_NOEXCEPT(iter--); + assert(*res == 2); + assert(*iter == 1); + } + + // operator+=(difference_type) + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i)); + + std::same_as decltype(auto) res = iter += 2; + + ASSERT_NOEXCEPT(iter += 2); + assert(&iter == &res); + assert(*iter == 3); + } + + // operator+(__capacity_aware_iterator, difference_type) + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i)); + + std::same_as decltype(auto) res = iter + 2; + + ASSERT_NOEXCEPT(iter + 2); + assert(*iter == 1); + assert(*res == 3); + } + + // operator+(difference_type, __capacity_aware_iterator) + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i)); + + std::same_as decltype(auto) res = 2 + iter; + + ASSERT_NOEXCEPT(2 + iter); + assert(*iter == 1); + assert(*res == 3); + } + + // operator-=(difference_type) + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i + 2)); + + std::same_as decltype(auto) res = iter -= 2; + + ASSERT_NOEXCEPT(iter -= 2); + assert(&iter == &res); + assert(*iter == 1); + } + + // operator-(__capacity_aware_iterator, difference_type) + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i + 2)); + + std::same_as decltype(auto) res = iter - 2; + + ASSERT_NOEXCEPT(iter - 2); + assert(*iter == 3); + assert(*res == 1); + } + + // operator-(__capacity_aware_iterator, __capacity_aware_iterator) + { + CapIter iter = std::__make_capacity_aware_iterator(Iter(i)); + CapIter iter2 = std::__make_capacity_aware_iterator(Iter(i + 2)); + CapIter iter3 = std::__make_capacity_aware_iterator(Iter(i + 6)); + + std::same_as decltype(auto) res = iter2 - iter; + std::same_as decltype(auto) res2 = iter3 - iter; + + ASSERT_NOEXCEPT(iter2 - iter); + assert(res == 2); + assert(res2 == 6); + } + + return true; +} + +int main(int, char**) { + test>(); + static_assert(test>()); + + return 0; +} diff --git a/libcxx/test/libcxx/iterators/capacity_aware_iter/assert.pass.cpp b/libcxx/test/libcxx/iterators/capacity_aware_iter/assert.pass.cpp new file mode 100644 index 0000000000000..ceac20d549c34 --- /dev/null +++ b/libcxx/test/libcxx/iterators/capacity_aware_iter/assert.pass.cpp @@ -0,0 +1,63 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: std-at-least-c++26 +// UNSUPPORTED: libcpp-hardening-mode=none + +// template +// struct __capacity_aware_iterator; + +// Check assert failure if advancing, rewinding or indexing iterator past its maximum range size + +#include <__iterator/capacity_aware_iterator.h> +#include + +#include "check_assertion.h" +#include "test_iterators.h" +#include "test_macros.h" + +template +void test() { + int arr[] = {1, 2, 3, 4}; + + constexpr long sz = std::size(arr); + + using CapIter = std::__capacity_aware_iterator; + + CapIter it = std::__make_capacity_aware_iterator(Iter(arr)); + + TEST_LIBCPP_ASSERT_FAILURE( + it += (sz + 1), + "__capacity_aware_iterator::operator+=: Attempting to move iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + it += -(sz + 1), + "__capacity_aware_iterator::operator+=: Attempting to move iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + it -= (sz + 1), + "__capacity_aware_iterator::operator-=: Attempting to move iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + it -= -(sz + 1), + "__capacity_aware_iterator::operator-=: Attempting to move iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + it[sz], + "__capacity_aware_iterator::operator[]: Attempting to index iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + it[-sz], + "__capacity_aware_iterator::operator[]: Attempting to index iterator past its container's possible range"); +} + +int main(int, char**) { + test>(); + + return 0; +} diff --git a/libcxx/test/libcxx/iterators/capacity_aware_iter/comparison.pass.cpp b/libcxx/test/libcxx/iterators/capacity_aware_iter/comparison.pass.cpp new file mode 100644 index 0000000000000..d1f396fb93777 --- /dev/null +++ b/libcxx/test/libcxx/iterators/capacity_aware_iter/comparison.pass.cpp @@ -0,0 +1,116 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: std-at-least-c++26 + +// template +// struct __capacity_aware_iterator; + +// Comparison operators + +// operator== +// operator!= +// operator< +// operator<= +// operator> +// operator>= +// operator<=> + +#include <__iterator/capacity_aware_iterator.h> +#include +#include +#include + +#include "test_iterators.h" +#include "test_macros.h" + +template +constexpr bool test() { + int arr[] = {1, 2, 3, 4}; + constexpr long sz = std::size(arr); + + using CapIter = std::__capacity_aware_iterator; + + CapIter iter1 = std::__make_capacity_aware_iterator(Iter(arr)); + CapIter iter2 = std::__make_capacity_aware_iterator(Iter(arr + 4)); + + // operator== + { + std::same_as decltype(auto) res = iter1 == iter1; + ASSERT_NOEXCEPT(iter1 == iter2); + assert(res); + assert(!(iter1 == iter2)); + } + + // operator!= + { + std::same_as decltype(auto) res = iter1 != iter2; + ASSERT_NOEXCEPT(iter1 != iter2); + assert(res); + assert(!(iter1 != iter1)); + } + + // operator< + { + std::same_as decltype(auto) res = iter1 < iter2; + ASSERT_NOEXCEPT(iter1 < iter2); + assert(res); + assert(!(iter1 < iter1)); + assert(!(iter2 < iter1)); + } + + // operator<= + { + std::same_as decltype(auto) res = iter1 <= iter2; + ASSERT_NOEXCEPT(iter1 <= iter2); + assert(res); + assert(iter1 <= iter1); + assert(!(iter2 <= iter1)); + } + + // operator> + { + std::same_as decltype(auto) res = iter1 > iter2; + ASSERT_NOEXCEPT(iter1 > iter2); + assert(iter2 > iter1); + assert(!res); + assert(!(iter1 > iter1)); + } + + // operator>= + { + std::same_as decltype(auto) res = iter1 >= iter2; + ASSERT_NOEXCEPT(iter1 >= iter2); + assert(iter2 >= iter1); + assert(iter1 >= iter1); + assert(!res); + } + + // operator <=> + { + ASSERT_NOEXCEPT(iter1 <=> iter2); + std::same_as decltype(auto) r1 = iter1 <=> iter2; + assert(r1 == std::strong_ordering::less); + + std::same_as decltype(auto) r2 = iter2 <=> iter1; + assert(r2 == std::strong_ordering::greater); + + std::same_as decltype(auto) r3 = iter1 <=> iter1; + assert(r3 == std::strong_ordering::equal); + assert(r3 == std::strong_ordering::equivalent); + } + + return true; +} + +int main(int, char**) { + test>(); + static_assert(test>()); + + return 0; +} diff --git a/libcxx/test/libcxx/iterators/capacity_aware_iter/contiguous.verify.cpp b/libcxx/test/libcxx/iterators/capacity_aware_iter/contiguous.verify.cpp new file mode 100644 index 0000000000000..0c49d2f1ac000 --- /dev/null +++ b/libcxx/test/libcxx/iterators/capacity_aware_iter/contiguous.verify.cpp @@ -0,0 +1,30 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: std-at-least-c++26 + +// __capacity_aware_iterator + +// Verify that only contiguous_iterators are accepted + +#include <__iterator/capacity_aware_iterator.h> + +#include "test_iterators.h" + +void test() { + std::__capacity_aware_iterator, int[], 0> + v1; // expected-error@*:* {{static assertion failed: __capacity_aware_iterator can only be used with contiguous iterators}} + std::__capacity_aware_iterator, int[], 0> + v2; // expected-error@*:* {{static assertion failed: __capacity_aware_iterator can only be used with contiguous iterators}} + std::__capacity_aware_iterator, int[], 0> + v3; // expected-error@*:* {{static assertion failed: __capacity_aware_iterator can only be used with contiguous iterators}} + std::__capacity_aware_iterator, int[], 0> + v4; // expected-error@*:* {{static assertion failed: __capacity_aware_iterator can only be used with contiguous iterators}} + std::__capacity_aware_iterator, int[], 0> + v5; // expected-error@*:* {{static assertion failed: __capacity_aware_iterator can only be used with contiguous iterators}} +} diff --git a/libcxx/test/libcxx/iterators/capacity_aware_iter/dereference.pass.cpp b/libcxx/test/libcxx/iterators/capacity_aware_iter/dereference.pass.cpp new file mode 100644 index 0000000000000..ff7d4b53b071a --- /dev/null +++ b/libcxx/test/libcxx/iterators/capacity_aware_iter/dereference.pass.cpp @@ -0,0 +1,80 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: std-at-least-c++26 + +// template +// struct __capacity_aware_iterator; + +// Dereference operators + +// operator[](difference_type) +// operator*(); +// operator->(); + +#include <__iterator/capacity_aware_iterator.h> +#include + +#include "test_iterators.h" +#include "test_macros.h" + +struct Foo { + int x; + constexpr bool operator==(Foo const& other) const { return x == other.x; } +}; + +template +constexpr bool test() { + Foo arr[] = {Foo{1}, Foo{2}, Foo{3}, Foo{4}}; + constexpr long sz = std::size(arr); + + using CapIter = std::__capacity_aware_iterator; + + CapIter it = std::__make_capacity_aware_iterator(Iter(arr)); + + // operator[] + { + std::same_as decltype(auto) res = it[0]; + ASSERT_NOEXCEPT(it[0]); + assert(res == arr[0]); + assert(&res == &arr[0]); + assert(it[1] == arr[1]); + assert(it[2] == arr[2]); + + CapIter it2 = it + 2; + + assert(it2[-1] == arr[1]); + assert(it2[-2] == arr[0]); + } + + // operator* + { + std::same_as decltype(auto) res = *it; + ASSERT_NOEXCEPT(*it); + assert(*it == arr[0]); + assert(&res == &arr[0]); + assert(&res == &(*it)); + } + + // operator-> + { + std::same_as decltype(auto) ptr = it.operator->(); + ASSERT_NOEXCEPT(it->x); + assert(ptr->x == 1); + assert(ptr == &arr[0]); + } + + return true; +} + +int main(int, char**) { + test>(); + static_assert(test>()); + + return 0; +} diff --git a/libcxx/test/libcxx/iterators/capacity_aware_iter/types.compile.pass.cpp b/libcxx/test/libcxx/iterators/capacity_aware_iter/types.compile.pass.cpp new file mode 100644 index 0000000000000..b3b72a0728ed7 --- /dev/null +++ b/libcxx/test/libcxx/iterators/capacity_aware_iter/types.compile.pass.cpp @@ -0,0 +1,31 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: std-at-least-c++26 + +// template +// struct __capacity_aware_iterator; + +// Nested types + +#include <__iterator/capacity_aware_iterator.h> +#include +#include + +#include "test_iterators.h" + +using It = contiguous_iterator; + +using CapIter = std::__capacity_aware_iterator; + +static_assert(std::is_same_v); +static_assert(std::is_same_v); +static_assert(std::is_same_v>); +static_assert(std::is_same_v>); +static_assert(std::is_same_v>); +static_assert(std::is_same_v>); diff --git a/libcxx/test/libcxx/utilities/optional/optional.iterator/assert.arithmetic.pass.cpp b/libcxx/test/libcxx/utilities/optional/optional.iterator/assert.arithmetic.pass.cpp new file mode 100644 index 0000000000000..cd73d67b39038 --- /dev/null +++ b/libcxx/test/libcxx/utilities/optional/optional.iterator/assert.arithmetic.pass.cpp @@ -0,0 +1,51 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// Add to iterator out of bounds. + +// REQUIRES: std-at-least-c++26 +// UNSUPPORTED: libcpp-hardening-mode=none, libcpp-has-abi-bounded-iterators-in-optional + +#include + +#include "check_assertion.h" + +int main(int, char**) { + { + std::optional opt(1); + auto i = opt.begin(); + + TEST_LIBCPP_ASSERT_FAILURE( + i += 2, + "__capacity_aware_iterator::operator+=: Attempting to move iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + i += -2, + "__capacity_aware_iterator::operator+=: Attempting to move iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + i -= 2, + "__capacity_aware_iterator::operator-=: Attempting to move iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + i -= -2, + "__capacity_aware_iterator::operator-=: Attempting to move iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + i[2], + "__capacity_aware_iterator::operator[]: Attempting to index iterator past its container's possible range"); + + TEST_LIBCPP_ASSERT_FAILURE( + i[-2], + "__capacity_aware_iterator::operator[]: Attempting to index iterator past its container's possible range"); + } + + return 0; +} diff --git a/libcxx/test/libcxx/utilities/optional/optional.iterator/iterator.compile.pass.cpp b/libcxx/test/libcxx/utilities/optional/optional.iterator/iterator.compile.pass.cpp new file mode 100644 index 0000000000000..265d39c97cb39 --- /dev/null +++ b/libcxx/test/libcxx/utilities/optional/optional.iterator/iterator.compile.pass.cpp @@ -0,0 +1,57 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: std-at-least-c++26 + +// + +// UNSUPPORTED: libcpp-has-abi-bounded-iterators-in-optional, libcpp-has-no-experimental-optional-iterator + +// Ensure that a std::optional::iterator can only be converted to a std::optional::iterator. + +// template class optional::iterator; +// template class optional::const_iterator; + +#include +#include +#include + +using Iter1 = std::optional::iterator; +using Iter2 = std::optional::iterator; +using Iter3 = std::optional::const_iterator; +using Iter4 = std::optional::const_iterator; +using VIter1 = std::vector::iterator; +using VIter2 = std::vector::const_iterator; + +static_assert(std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); + +static_assert(std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); + +static_assert(std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); + +static_assert(std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); +static_assert(!std::is_convertible_v); diff --git a/libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/left_folds.pass.cpp b/libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/left_folds.pass.cpp index 4987ca9cac4ae..107e09a63c96f 100644 --- a/libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/left_folds.pass.cpp +++ b/libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/left_folds.pass.cpp @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -322,6 +323,12 @@ void runtime_only_test_case() { // int(-15.5) + -6.6 = -15 + -6.6 = -21.6. check(data, 0.0, plus, expected); } + + { + auto const data = std::set{2, 4, 6, 8, 10, 12}; + auto const expected = triangular_sum(data); + check(data, 0, std::plus(), static_cast(expected)); + } } int main(int, char**) { diff --git a/libcxx/test/std/atomics/atomics.ref/address.pass.cpp b/libcxx/test/std/atomics/atomics.ref/address.pass.cpp index e0db6a93e2eda..27f0c198e89ef 100644 --- a/libcxx/test/std/atomics/atomics.ref/address.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/address.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -20,7 +21,7 @@ template struct TestAddress { void operator()() const { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); const std::atomic_ref a(x); std::same_as decltype(auto) p = a.address(); diff --git a/libcxx/test/std/atomics/atomics.ref/assign.pass.cpp b/libcxx/test/std/atomics/atomics.ref/assign.pass.cpp index 9b2f9042e9836..c643a313c2f23 100644 --- a/libcxx/test/std/atomics/atomics.ref/assign.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/assign.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -24,7 +25,7 @@ template struct TestAssign { void operator()() const { { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); std::same_as decltype(auto) y = (a = T(2)); diff --git a/libcxx/test/std/atomics/atomics.ref/bitwise_and_assign.pass.cpp b/libcxx/test/std/atomics/atomics.ref/bitwise_and_assign.pass.cpp index bfbd69f93845e..2a2502ce8cabe 100644 --- a/libcxx/test/std/atomics/atomics.ref/bitwise_and_assign.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/bitwise_and_assign.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -32,7 +33,7 @@ struct TestBitwiseAndAssign { void operator()() const { static_assert(std::is_integral_v); - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); std::same_as decltype(auto) y = (a &= T(1)); diff --git a/libcxx/test/std/atomics/atomics.ref/bitwise_or_assign.pass.cpp b/libcxx/test/std/atomics/atomics.ref/bitwise_or_assign.pass.cpp index e424da7167518..2cf0d300a3104 100644 --- a/libcxx/test/std/atomics/atomics.ref/bitwise_or_assign.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/bitwise_or_assign.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -32,7 +33,7 @@ struct TestBitwiseOrAssign { void operator()() const { static_assert(std::is_integral_v); - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); std::same_as decltype(auto) y = (a |= T(2)); diff --git a/libcxx/test/std/atomics/atomics.ref/bitwise_xor_assign.pass.cpp b/libcxx/test/std/atomics/atomics.ref/bitwise_xor_assign.pass.cpp index 8a90d241e88e1..266f350f81a30 100644 --- a/libcxx/test/std/atomics/atomics.ref/bitwise_xor_assign.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/bitwise_xor_assign.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -32,7 +33,7 @@ struct TestBitwiseXorAssign { void operator()() const { static_assert(std::is_integral_v); - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); std::same_as decltype(auto) y = (a ^= T(2)); diff --git a/libcxx/test/std/atomics/atomics.ref/compare_exchange_strong.pass.cpp b/libcxx/test/std/atomics/atomics.ref/compare_exchange_strong.pass.cpp index 90aa5ea5b6df4..aa0a7850bf325 100644 --- a/libcxx/test/std/atomics/atomics.ref/compare_exchange_strong.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/compare_exchange_strong.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -28,7 +29,7 @@ template struct TestCompareExchangeStrong { void operator()() const { { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); T t(T(1)); @@ -44,7 +45,7 @@ struct TestCompareExchangeStrong { ASSERT_NOEXCEPT(a.compare_exchange_strong(t, T(2))); } { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); T t(T(1)); @@ -60,7 +61,7 @@ struct TestCompareExchangeStrong { ASSERT_NOEXCEPT(a.compare_exchange_strong(t, T(2), std::memory_order_seq_cst)); } { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); T t(T(1)); diff --git a/libcxx/test/std/atomics/atomics.ref/compare_exchange_weak.pass.cpp b/libcxx/test/std/atomics/atomics.ref/compare_exchange_weak.pass.cpp index 99c1385a2fe0b..58cf2e0fe338b 100644 --- a/libcxx/test/std/atomics/atomics.ref/compare_exchange_weak.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/compare_exchange_weak.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -28,7 +29,7 @@ template struct TestCompareExchangeWeak { void operator()() const { { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); T t(T(1)); @@ -44,7 +45,7 @@ struct TestCompareExchangeWeak { ASSERT_NOEXCEPT(a.compare_exchange_weak(t, T(2))); } { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); T t(T(1)); diff --git a/libcxx/test/std/atomics/atomics.ref/convert.pass.cpp b/libcxx/test/std/atomics/atomics.ref/convert.pass.cpp index 2a58a5ea6ae2a..dd84c1bc256ad 100644 --- a/libcxx/test/std/atomics/atomics.ref/convert.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/convert.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -24,7 +25,7 @@ struct TestConvert { void operator()() const { T x(T(1)); - T copy = x; + alignas(std::atomic_ref::required_alignment) T copy = x; std::atomic_ref const a(copy); T converted = a; diff --git a/libcxx/test/std/atomics/atomics.ref/ctor.pass.cpp b/libcxx/test/std/atomics/atomics.ref/ctor.pass.cpp index d6c647406abf5..9fb06de357eb4 100644 --- a/libcxx/test/std/atomics/atomics.ref/ctor.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/ctor.pass.cpp @@ -25,7 +25,7 @@ struct TestCtor { static_assert(!std::is_convertible_v>); static_assert(std::is_constructible_v, T&>); - T x(T(0)); + alignas(std::atomic_ref::required_alignment) T x(T(0)); std::atomic_ref a(x); (void)a; } diff --git a/libcxx/test/std/atomics/atomics.ref/deduction.pass.cpp b/libcxx/test/std/atomics/atomics.ref/deduction.pass.cpp index 24a399ac4711e..9a559f9a23f4d 100644 --- a/libcxx/test/std/atomics/atomics.ref/deduction.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/deduction.pass.cpp @@ -21,7 +21,7 @@ template struct TestDeduction { void operator()() const { - T x(T(0)); + alignas(std::atomic_ref::required_alignment) T x(T(0)); std::atomic_ref a(x); ASSERT_SAME_TYPE(decltype(a), std::atomic_ref); } diff --git a/libcxx/test/std/atomics/atomics.ref/exchange.pass.cpp b/libcxx/test/std/atomics/atomics.ref/exchange.pass.cpp index c2afa6b8dfd07..4c70b445da6e6 100644 --- a/libcxx/test/std/atomics/atomics.ref/exchange.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/exchange.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -24,7 +25,7 @@ template struct TestExchange { void operator()() const { { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); { diff --git a/libcxx/test/std/atomics/atomics.ref/fetch_add.pass.cpp b/libcxx/test/std/atomics/atomics.ref/fetch_add.pass.cpp index 65a457a6129d5..bb42eb86a3e7f 100644 --- a/libcxx/test/std/atomics/atomics.ref/fetch_add.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/fetch_add.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -38,7 +39,7 @@ template struct TestFetchAdd { void operator()() const { if constexpr (std::is_arithmetic_v) { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); { @@ -57,7 +58,7 @@ struct TestFetchAdd { } else if constexpr (std::is_pointer_v) { using U = std::remove_pointer_t; U t[9] = {}; - T p{&t[1]}; + alignas(std::atomic_ref::required_alignment) T p{&t[1]}; std::atomic_ref const a(p); { diff --git a/libcxx/test/std/atomics/atomics.ref/fetch_and.pass.cpp b/libcxx/test/std/atomics/atomics.ref/fetch_and.pass.cpp index 9d1fa846a9e66..7ce48674aca7f 100644 --- a/libcxx/test/std/atomics/atomics.ref/fetch_and.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/fetch_and.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -35,7 +36,7 @@ struct TestFetchAnd { void operator()() const { static_assert(std::is_integral_v); - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); { diff --git a/libcxx/test/std/atomics/atomics.ref/fetch_or.pass.cpp b/libcxx/test/std/atomics/atomics.ref/fetch_or.pass.cpp index 51500e3a62bea..4219835f0f29b 100644 --- a/libcxx/test/std/atomics/atomics.ref/fetch_or.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/fetch_or.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -35,7 +36,7 @@ struct TestFetchOr { void operator()() const { static_assert(std::is_integral_v); - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); { diff --git a/libcxx/test/std/atomics/atomics.ref/fetch_sub.pass.cpp b/libcxx/test/std/atomics/atomics.ref/fetch_sub.pass.cpp index ab89ebdbde261..a9c2b8bf4ce54 100644 --- a/libcxx/test/std/atomics/atomics.ref/fetch_sub.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/fetch_sub.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -38,7 +39,7 @@ template struct TestFetchSub { void operator()() const { if constexpr (std::is_arithmetic_v) { - T x(T(7)); + alignas(std::atomic_ref::required_alignment) T x(T(7)); std::atomic_ref const a(x); { diff --git a/libcxx/test/std/atomics/atomics.ref/fetch_xor.pass.cpp b/libcxx/test/std/atomics/atomics.ref/fetch_xor.pass.cpp index 35437cbba3135..902f439fa2401 100644 --- a/libcxx/test/std/atomics/atomics.ref/fetch_xor.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/fetch_xor.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -35,7 +36,7 @@ struct TestFetchXor { void operator()() const { static_assert(std::is_integral_v); - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); { diff --git a/libcxx/test/std/atomics/atomics.ref/increment_decrement.pass.cpp b/libcxx/test/std/atomics/atomics.ref/increment_decrement.pass.cpp index 15bf0ecda5363..2adc8e49a2c68 100644 --- a/libcxx/test/std/atomics/atomics.ref/increment_decrement.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/increment_decrement.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -49,7 +50,7 @@ template struct TestIncrementDecrement { void operator()() const { if constexpr (std::is_integral_v) { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); { @@ -82,7 +83,7 @@ struct TestIncrementDecrement { } else if constexpr (std::is_pointer_v) { using U = std::remove_pointer_t; U t[9] = {}; - T p{&t[1]}; + alignas(std::atomic_ref::required_alignment) T p{&t[1]}; std::atomic_ref const a(p); { diff --git a/libcxx/test/std/atomics/atomics.ref/is_always_lock_free.pass.cpp b/libcxx/test/std/atomics/atomics.ref/is_always_lock_free.pass.cpp index 78e46c0397951..678085210efff 100644 --- a/libcxx/test/std/atomics/atomics.ref/is_always_lock_free.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/is_always_lock_free.pass.cpp @@ -60,16 +60,16 @@ void check_always_lock_free(std::atomic_ref const& a) { } while (0) void test() { - char c = 'x'; + alignas(std::atomic_ref::required_alignment) char c = 'x'; check_always_lock_free(std::atomic_ref(c)); - int i = 0; + alignas(std::atomic_ref::required_alignment) int i = 0; check_always_lock_free(std::atomic_ref(i)); - float f = 0.f; + alignas(std::atomic_ref::required_alignment) float f = 0.f; check_always_lock_free(std::atomic_ref(f)); - int* p = &i; + alignas(std::atomic_ref::required_alignment) int* p = &i; check_always_lock_free(std::atomic_ref(p)); CHECK_ALWAYS_LOCK_FREE(struct Empty{}); diff --git a/libcxx/test/std/atomics/atomics.ref/load.pass.cpp b/libcxx/test/std/atomics/atomics.ref/load.pass.cpp index feed0fbaed842..30d25ea36d01d 100644 --- a/libcxx/test/std/atomics/atomics.ref/load.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/load.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -23,7 +24,7 @@ template struct TestLoad { void operator()() const { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); { diff --git a/libcxx/test/std/atomics/atomics.ref/notify_all.pass.cpp b/libcxx/test/std/atomics/atomics.ref/notify_all.pass.cpp index 6b4702595e68a..df8e84285bc83 100644 --- a/libcxx/test/std/atomics/atomics.ref/notify_all.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/notify_all.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -25,7 +26,7 @@ template struct TestNotifyAll { void operator()() const { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); bool done = false; diff --git a/libcxx/test/std/atomics/atomics.ref/notify_one.pass.cpp b/libcxx/test/std/atomics/atomics.ref/notify_one.pass.cpp index 6ad9698b46e8f..8c76a63e5a951 100644 --- a/libcxx/test/std/atomics/atomics.ref/notify_one.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/notify_one.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -25,7 +26,7 @@ template struct TestNotifyOne { void operator()() const { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); std::thread t = support::make_test_thread([&]() { diff --git a/libcxx/test/std/atomics/atomics.ref/operator_minus_equals.pass.cpp b/libcxx/test/std/atomics/atomics.ref/operator_minus_equals.pass.cpp index 502eff772ab76..b89dd47c204af 100644 --- a/libcxx/test/std/atomics/atomics.ref/operator_minus_equals.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/operator_minus_equals.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -34,7 +35,7 @@ template struct TestOperatorMinusEquals { void operator()() const { if constexpr (std::is_arithmetic_v) { - T x(T(3)); + alignas(std::atomic_ref::required_alignment) T x(T(3)); std::atomic_ref const a(x); std::same_as decltype(auto) y = (a -= T(2)); @@ -44,7 +45,7 @@ struct TestOperatorMinusEquals { } else if constexpr (std::is_pointer_v) { using U = std::remove_pointer_t; U t[9] = {}; - T p{&t[3]}; + alignas(std::atomic_ref::required_alignment) T p{&t[3]}; std::atomic_ref const a(p); std::same_as decltype(auto) y = (a -= 2); diff --git a/libcxx/test/std/atomics/atomics.ref/operator_plus_equals.pass.cpp b/libcxx/test/std/atomics/atomics.ref/operator_plus_equals.pass.cpp index 1f287f6945bda..d80dd6e4e6191 100644 --- a/libcxx/test/std/atomics/atomics.ref/operator_plus_equals.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/operator_plus_equals.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -34,7 +35,7 @@ template struct TestOperatorPlusEquals { void operator()() const { if constexpr (std::is_arithmetic_v) { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); std::same_as decltype(auto) y = (a += T(2)); @@ -44,7 +45,7 @@ struct TestOperatorPlusEquals { } else if constexpr (std::is_pointer_v) { using U = std::remove_pointer_t; U t[9] = {}; - T p{&t[1]}; + alignas(std::atomic_ref::required_alignment) T p{&t[1]}; std::atomic_ref const a(p); std::same_as decltype(auto) y = (a += 2); diff --git a/libcxx/test/std/atomics/atomics.ref/required_alignment.pass.cpp b/libcxx/test/std/atomics/atomics.ref/required_alignment.pass.cpp index 4fc453fb0ff11..8928b7d862e12 100644 --- a/libcxx/test/std/atomics/atomics.ref/required_alignment.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/required_alignment.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/libcxx/test/std/atomics/atomics.ref/requires-trivially-copyable.verify.cpp b/libcxx/test/std/atomics/atomics.ref/requires-trivially-copyable.verify.cpp index 9a8b036ffd1f8..03397fc241b47 100644 --- a/libcxx/test/std/atomics/atomics.ref/requires-trivially-copyable.verify.cpp +++ b/libcxx/test/std/atomics/atomics.ref/requires-trivially-copyable.verify.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -20,7 +21,8 @@ void trivially_copyable() { struct X { X() = default; X(X const&) {} // -> not trivially copyable - } x; + }; + alignas(std::atomic_ref::required_alignment) X x; // expected-error-re@*:* {{static assertion failed {{.*}}atomic_ref requires that 'T' be a trivially copyable type}} std::atomic_ref r(x); } diff --git a/libcxx/test/std/atomics/atomics.ref/store.pass.cpp b/libcxx/test/std/atomics/atomics.ref/store.pass.cpp index ea01a3d02a34f..1495b649509a6 100644 --- a/libcxx/test/std/atomics/atomics.ref/store.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/store.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -22,7 +23,7 @@ template struct TestStore { void operator()() const { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); a.store(T(2)); diff --git a/libcxx/test/std/atomics/atomics.ref/test_helper.h b/libcxx/test/std/atomics/atomics.ref/test_helper.h index 225a70c5a16ca..9e2c1d5e24239 100644 --- a/libcxx/test/std/atomics/atomics.ref/test_helper.h +++ b/libcxx/test/std/atomics/atomics.ref/test_helper.h @@ -48,9 +48,9 @@ void test_seq_cst(StoreOp store_op, LoadOp load_op) { T old_value(make_value(0)); T new_value(make_value(1)); - T copy_x = old_value; + alignas(std::atomic_ref::required_alignment) T copy_x = old_value; std::atomic_ref const x(copy_x); - T copy_y = old_value; + alignas(std::atomic_ref::required_alignment) T copy_y = old_value; std::atomic_ref const y(copy_y); std::atomic_bool x_updated_first(false); @@ -101,7 +101,7 @@ void test_acquire_release(StoreOp store_op, LoadOp load_op) { T old_value(make_value(0)); T new_value(make_value(1)); - T copy = old_value; + alignas(std::atomic_ref::required_alignment) T copy = old_value; std::atomic_ref const at(copy); int non_atomic = 5; diff --git a/libcxx/test/std/atomics/atomics.ref/wait.pass.cpp b/libcxx/test/std/atomics/atomics.ref/wait.pass.cpp index fc8f6ef59ad2e..58328eb7ae4e6 100644 --- a/libcxx/test/std/atomics/atomics.ref/wait.pass.cpp +++ b/libcxx/test/std/atomics/atomics.ref/wait.pass.cpp @@ -1,3 +1,4 @@ +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -28,7 +29,7 @@ template struct TestWait { void operator()() const { { - T x(T(1)); + alignas(std::atomic_ref::required_alignment) T x(T(1)); std::atomic_ref const a(x); assert(a.load() == T(1)); diff --git a/libcxx/test/std/ranges/range.adaptors/range.common.view/begin.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.common.view/begin.pass.cpp index 96116dc37553a..b13b4b4e69e71 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.common.view/begin.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.common.view/begin.pass.cpp @@ -51,6 +51,12 @@ constexpr bool test() { assert(begin == std::ranges::begin(view)); } + { + NonSimpleNonCommonView view{buf, buf + 8}; + std::ranges::common_view common(view); + static_assert(!std::is_same_v); + } + return true; } diff --git a/libcxx/test/std/ranges/range.adaptors/range.common.view/end.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.common.view/end.pass.cpp index 0565ed02f2716..a80f85defaeb5 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.common.view/end.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.common.view/end.pass.cpp @@ -39,6 +39,12 @@ constexpr bool test() { assert(base(end) == buf + 8); } + { + NonSimpleNonCommonView view{buf, buf + 8}; + std::ranges::common_view common(view); + static_assert(!std::is_same_v); + } + return true; } diff --git a/libcxx/test/std/ranges/range.adaptors/range.common.view/types.h b/libcxx/test/std/ranges/range.adaptors/range.common.view/types.h index 18354483fd329..56f2f6ad5fcbf 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.common.view/types.h +++ b/libcxx/test/std/ranges/range.adaptors/range.common.view/types.h @@ -90,4 +90,37 @@ struct NonCommonView : std::ranges::view_base { static_assert( std::ranges::view); static_assert(!std::ranges::common_range); +template +concept HasConstBegin = requires(const T& ct) { ct.begin(); }; + +template +concept HasBegin = requires(T& t) { t.begin(); }; + +template +concept HasConstAndNonConstBegin = HasConstBegin && requires(T& t, const T& ct) { + requires !std::same_as; +}; + +template +concept HasOnlyNonConstBegin = HasBegin && !HasConstBegin; + +template +concept HasOnlyConstBegin = HasConstBegin && !HasConstAndNonConstBegin; + +struct NonSimpleNonCommonView : std::ranges::view_base { + int* begin_; + int* end_; + constexpr explicit NonSimpleNonCommonView(int* b, int* e) : begin_(b), end_(e) {} + constexpr auto begin() const { return static_cast(begin_); } + constexpr auto end() const { return sentinel_wrapper(end_); } + constexpr int* begin() { return begin_; } + constexpr auto end() { return sentinel_wrapper(end_); } +}; + +static_assert(!HasOnlyNonConstBegin>); +static_assert(!HasOnlyConstBegin>); +static_assert(HasConstAndNonConstBegin>); +static_assert(HasConstBegin>); +static_assert(HasOnlyConstBegin>); + #endif // TEST_STD_RANGES_RANGE_ADAPTORS_RANGE_COMMON_VIEW_TYPES_H diff --git a/libcxx/test/std/re/re.alg/re.alg.search/grep.pass.cpp b/libcxx/test/std/re/re.alg/re.alg.search/grep.pass.cpp index 3569ad53ee60b..a7a6e243c9838 100644 --- a/libcxx/test/std/re/re.alg/re.alg.search/grep.pass.cpp +++ b/libcxx/test/std/re/re.alg/re.alg.search/grep.pass.cpp @@ -16,6 +16,7 @@ // regex_constants::match_flag_type flags = regex_constants::match_default); #include +#include #include #include "test_macros.h" @@ -24,7 +25,7 @@ extern "C" void LLVMFuzzerTestOneInput(const char *data) { #ifndef TEST_HAS_NO_EXCEPTIONS - std::size_t size = strlen(data); + std::size_t size = std::strlen(data); if (size > 0) { try diff --git a/libcxx/test/std/thread/thread.semaphore/lost_wakeup.timed.pass.cpp b/libcxx/test/std/thread/thread.semaphore/lost_wakeup.timed.pass.cpp index aa18b8fc61a39..a6099a6800c7d 100644 --- a/libcxx/test/std/thread/thread.semaphore/lost_wakeup.timed.pass.cpp +++ b/libcxx/test/std/thread/thread.semaphore/lost_wakeup.timed.pass.cpp @@ -14,27 +14,25 @@ // Test that counting_semaphore::try_acquire_for does not suffer from lost wakeup // under stress testing. -#include #include +#include #include #include #include #include "make_test_thread.h" -static std::counting_semaphore<> s(0); constexpr auto num_acquirer = 100; constexpr auto num_iterations = 5000; -static std::barrier<> b(num_acquirer + 1); -void acquire() { +void acquire(std::counting_semaphore<>& s) { for (int i = 0; i < num_iterations; ++i) { while (!s.try_acquire_for(std::chrono::seconds(1))) { } } } -void release() { +void release(std::counting_semaphore<>& s) { for (int i = 0; i < num_iterations; ++i) { s.release(num_acquirer); } @@ -42,11 +40,11 @@ void release() { int main(int, char**) { std::vector threads; + std::counting_semaphore<> s(0); for (int i = 0; i < num_acquirer; ++i) - threads.push_back(support::make_test_thread(acquire)); - - threads.push_back(support::make_test_thread(release)); + threads.push_back(support::make_test_thread(acquire, std::ref(s))); + threads.push_back(support::make_test_thread(release, std::ref(s))); for (auto& thread : threads) thread.join(); diff --git a/libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp b/libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp index 120dfc22f3fbc..b78f72210f7da 100644 --- a/libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp +++ b/libcxx/test/std/utilities/any/any.class/any.cons/value.pass.cpp @@ -21,6 +21,7 @@ #include #include +#include #include "any_helpers.h" #include "count_new.h" @@ -140,6 +141,24 @@ void test_sfinae_constraints() { } } +// https://llvm.org/PR176877 +// Avoid constraint meta-recursion for a type both convertible from and to std::any. +template ::value> +void test_default_template_argument_is_copy_constructible(T) {} + +template > +void test_default_template_argument_is_copy_constructible_v(T) {} + +void test_no_constraint_recursion() { + struct ConvertibleFromAndToAny { + ConvertibleFromAndToAny(std::any) {} + }; + + ConvertibleFromAndToAny src = std::any{}; + test_default_template_argument_is_copy_constructible(src); + test_default_template_argument_is_copy_constructible_v(src); +} + int main(int, char**) { test_copy_move_value(); test_copy_move_value(); @@ -147,6 +166,7 @@ int main(int, char**) { test_copy_value_throws(); test_move_value_throws(); test_sfinae_constraints(); + test_no_constraint_recursion(); - return 0; + return 0; } diff --git a/libcxx/test/std/utilities/optional/optional.iterator/compare.pass.cpp b/libcxx/test/std/utilities/optional/optional.iterator/compare.pass.cpp new file mode 100644 index 0000000000000..4c48c54df3257 --- /dev/null +++ b/libcxx/test/std/utilities/optional/optional.iterator/compare.pass.cpp @@ -0,0 +1,100 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// REQUIRES: std-at-least-c++26 +// UNSUPPORTED: libcpp-has-no-experimental-optional-iterator + +// + +// template class optional::iterator::operator<=>; +// template class optional::const_iterator::operator<=>; + +#include +#include +#include +#include +#include +#include + +template +constexpr bool test() { + using Opt = std::optional; + + static_assert(std::three_way_comparable); + + if constexpr (std::is_object_v) { + static_assert(std::three_way_comparable); + } + + std::remove_reference_t t{}; + Opt opt{t}; + + // [container.reqmts] tests for comparison operators of optional::iterator and optional::const_iterator + auto it1 = opt.begin(); + + { + auto it2 = opt.begin(); + assert(it1 == it2); + assert(!(it1 != it2)); + + std::same_as decltype(auto) spaceship = it1 <=> it2; + assert(spaceship == std::strong_ordering::equal); + } + + { + auto it3 = opt.end(); + assert(it1 != it3); + assert(it1 <= it3); + assert(it1 < it3); + assert(it3 >= it1); + assert(it3 > it1); + + assert(it1 <=> it3 == std::strong_ordering::less); + assert(it3 <=> it1 == std::strong_ordering::greater); + } + + auto cit1 = std::as_const(opt).begin(); + + { + auto cit2 = std::as_const(opt).begin(); + assert(cit1 == cit2); + assert(!(cit1 != cit2)); + + std::same_as decltype(auto) spaceship = cit1 <=> cit2; + assert(spaceship == std::strong_ordering::equal); + } + + { + auto cit3 = std::as_const(opt).end(); + + assert(cit1 <= cit3); + assert(cit1 < cit3); + assert(cit3 >= cit1); + assert(cit3 > cit1); + + assert(cit1 <=> cit3 == std::strong_ordering::less); + assert(cit3 <=> cit1 == std::strong_ordering::greater); + } + + return true; +} + +constexpr bool test() { + test(); + test(); + test(); + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/optional/optional.iterator/iterator.pass.cpp b/libcxx/test/std/utilities/optional/optional.iterator/iterator.pass.cpp index 1581c640136c6..05b8b3572ef53 100644 --- a/libcxx/test/std/utilities/optional/optional.iterator/iterator.pass.cpp +++ b/libcxx/test/std/utilities/optional/optional.iterator/iterator.pass.cpp @@ -100,6 +100,30 @@ constexpr void test(std::decay_t v) { assert(val.begin() != val.end()); assert(*(val.begin()) == v); } + + // [container.reqmts] operator- + { + std::optional val(v); + auto it1 = val.begin(); + auto it2 = val.begin(); + auto it3 = val.end(); + + auto cit1 = std::as_const(val).begin(); + auto cit2 = std::as_const(val).begin(); + auto cit3 = std::as_const(val).end(); + + assert(it1 - it2 == 0); + assert(cit1 - cit2 == 0); + assert(it1 - cit1 == 0); + assert(it3 - it1 == 1); + assert(it1 - it3 == -1); + + assert(cit3 - cit1 == 1); + assert(cit1 - cit3 == -1); + assert(cit3 - cit3 == 0); + assert(cit3 - it1 == 1); + assert(it1 - cit3 == -1); + } } constexpr bool test() { diff --git a/libcxx/utils/ci/benchmark-for-lnt.py b/libcxx/utils/ci/benchmark-for-lnt.py index 3105010ebe881..a139c58bb366f 100755 --- a/libcxx/utils/ci/benchmark-for-lnt.py +++ b/libcxx/utils/ci/benchmark-for-lnt.py @@ -46,7 +46,7 @@ def main(argv): help='Print the output of all subcommands.') args = parser.parse_args(argv) - def run(command, *posargs, **kwargs): + def run(command, *posargs, enforce_success=True, **kwargs): command = [str(c) for c in command] if args.dry_run: print(f'$ {" ".join(command)}') @@ -61,7 +61,10 @@ def run(command, *posargs, **kwargs): kwargs.update({'stdout': subprocess.DEVNULL}) if 'stderr' not in kwargs: kwargs.update({'stderr': subprocess.DEVNULL}) - subprocess.check_call(command, *posargs, **kwargs) + if enforce_success: + subprocess.check_call(command, *posargs, **kwargs) + else: + subprocess.call(command, *posargs, **kwargs) with tempfile.TemporaryDirectory() as build_dir: build_dir = pathlib.Path(build_dir) @@ -86,7 +89,8 @@ def run(command, *posargs, **kwargs): '--param', 'std=c++17', '--param', f'spec_dir={args.spec_dir}', build_dir / 'spec/libcxx/test', - '--filter', 'benchmarks/spec.gen.py']) + '--filter', 'benchmarks/spec.gen.py'], + enforce_success=False) # TODO: For now, we run only a subset of the benchmarks because running the whole test suite is too slow. # Run the whole test suite once https://github.com/llvm/llvm-project/issues/173032 is resolved. @@ -101,7 +105,8 @@ def run(command, *posargs, **kwargs): '--param', 'optimization=speed', '--param', 'std=c++26', build_dir / 'micro/libcxx/test', - '--filter', 'benchmarks/(algorithms|containers|iterators|locale|memory|streams|numeric|utility)']) + '--filter', 'benchmarks/(algorithms|containers|iterators|locale|memory|streams|numeric|utility)'], + enforce_success=False) step('Installing LNT') run(['python', '-m', 'venv', build_dir / '.venv']) diff --git a/libcxx/utils/gdb/libcxx/printers.py b/libcxx/utils/gdb/libcxx/printers.py index 1c8ef6d7feb97..ccaa6e9a019e8 100644 --- a/libcxx/utils/gdb/libcxx/printers.py +++ b/libcxx/utils/gdb/libcxx/printers.py @@ -199,6 +199,8 @@ def to_string(self): size = long_field["__size_"] else: data = short_field["__data_"] + ptr_type = data.type.target().pointer() + data = data.cast(ptr_type) size = short_field["__size_"] return data.lazy_string(length=size) diff --git a/libcxx/utils/libcxx/test/features/libcxx_macros.py b/libcxx/utils/libcxx/test/features/libcxx_macros.py index f8395fc320bcc..02705bff1c09d 100644 --- a/libcxx/utils/libcxx/test/features/libcxx_macros.py +++ b/libcxx/utils/libcxx/test/features/libcxx_macros.py @@ -26,6 +26,7 @@ "_LIBCPP_ABI_BOUNDED_ITERATORS": "libcpp-has-abi-bounded-iterators", "_LIBCPP_ABI_BOUNDED_ITERATORS_IN_OPTIONAL": "libcpp-has-abi-bounded-iterators-in-optional", "_LIBCPP_ABI_BOUNDED_ITERATORS_IN_STRING": "libcpp-has-abi-bounded-iterators-in-string", + "_LIBCPP_ABI_BOUNDED_ITERATORS_IN_OPTIONAL": "libcpp-has-abi-bounded-iterators-in-optional", "_LIBCPP_ABI_BOUNDED_ITERATORS_IN_VECTOR": "libcpp-has-abi-bounded-iterators-in-vector", "_LIBCPP_ABI_BOUNDED_ITERATORS_IN_STD_ARRAY": "libcpp-has-abi-bounded-iterators-in-std-array", "_LIBCPP_ABI_BOUNDED_UNIQUE_PTR": "libcpp-has-abi-bounded-unique_ptr", diff --git a/libsycl/docs/index.rst b/libsycl/docs/index.rst index ce48743be3ae2..03e083227ace4 100644 --- a/libsycl/docs/index.rst +++ b/libsycl/docs/index.rst @@ -1,6 +1,6 @@ -===================== +=========================== SYCL runtime implementation -===================== +=========================== .. contents:: :local: @@ -8,7 +8,7 @@ SYCL runtime implementation .. _index: Current Status -======== +============== The implementation is in the very early stages of upstreaming. The first milestone is to get @@ -59,7 +59,7 @@ libsycl side: from the multi-architectural binaries Build steps -======== +=========== To build LLVM with libsycl runtime enabled the following script can be used. @@ -87,7 +87,22 @@ To build LLVM with libsycl runtime enabled the following script can be used. Limitations -======== +=========== Libsycl is not currently supported on Windows because it depends on liboffload which doesn't currently support Windows. + +TODO for added SYCL classes +=========================== + +* ``exception``: methods with context are not implemented, to add once context is ready +* ``platform``: deprecated info descriptor is not implemented (info::platform::extensions), to implement on RT level with ``device::get_info()`` +* ``device``: + + * ``get_info``: to find an efficient way to map descriptors to liboffload types, add other descriptors, add cache of info data + * ``has(aspect)``: same as get_info + * ``create_sub_devices``: partitioning is not supported by liboffload now, blocked + * ``has_extension``: deprecated API, to implement on RT level with ``device::has`` + +* device selection: to add compatibility with old SYCL 1.2.1 device selectors, still part of SYCL 2020 specification + diff --git a/libsycl/include/sycl/__impl/aspect.hpp b/libsycl/include/sycl/__impl/aspect.hpp new file mode 100644 index 0000000000000..0a73dd621df9a --- /dev/null +++ b/libsycl/include/sycl/__impl/aspect.hpp @@ -0,0 +1,43 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBSYCL___IMPL_ASPECT_HPP +#define _LIBSYCL___IMPL_ASPECT_HPP + +#include + +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL + +// SYCL 2020 4.6.4.5. Aspects. +enum class aspect : std::uint32_t { + cpu, + gpu, + accelerator, + custom, + emulated, + host_debuggable, + fp16, + fp64, + atomic64, + image, + online_compiler, + online_linker, + queue_profiling, + usm_device_allocations, + usm_host_allocations, + usm_atomic_host_allocations, + usm_shared_allocations, + usm_atomic_shared_allocations, + usm_system_allocations +}; + +_LIBSYCL_END_NAMESPACE_SYCL + +#endif // _LIBSYCL___IMPL_ASPECT_HPP diff --git a/libsycl/include/sycl/__impl/device.hpp b/libsycl/include/sycl/__impl/device.hpp new file mode 100644 index 0000000000000..55b624f8fcbd5 --- /dev/null +++ b/libsycl/include/sycl/__impl/device.hpp @@ -0,0 +1,183 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains the declaration of the SYCL 2020 device class, which +/// represents a single SYCL device on which kernels can be executed. +/// +//===----------------------------------------------------------------------===// + +#ifndef _LIBSYCL___IMPL_DEVICE_HPP +#define _LIBSYCL___IMPL_DEVICE_HPP + +#include +#include +#include +#include + +#include +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL + +class platform; + +namespace detail { +class DeviceImpl; +} // namespace detail + +// SYCL 2020 4.6.4. Device class. +class _LIBSYCL_EXPORT device { +public: + device(const device &rhs) = default; + + device(device &&rhs) = default; + + device &operator=(const device &rhs) = default; + + device &operator=(device &&rhs) = default; + + friend bool operator==(const device &lhs, const device &rhs) { + return lhs.impl == rhs.impl; + } + + friend bool operator!=(const device &lhs, const device &rhs) { + return !(lhs == rhs); + } + + /// Constructs a SYCL device instance using the default device (device chosen + /// by default device selector). + device(); + + /// Constructs a SYCL device instance using the device + /// identified by the provided device selector. + /// \param DeviceSelector is SYCL 2020 device selector, a simple callable that + /// takes a device and returns an int. + template < + typename DeviceSelector, + // `DeviceImpl` (used as a parameter in private ctor) is incomplete + // so would result in a error trying to instantiate + // `EnableIfDeviceSelectorIsInvocable` below. Filter it out + // before trying to do that. + typename = + std::enable_if_t>, + typename = detail::EnableIfDeviceSelectorIsInvocable> + explicit device(const DeviceSelector &deviceSelector) + : device(detail::SelectDevice(deviceSelector)) {} + + /// Returns the backend associated with this device. + /// + /// \return the backend associated with this device. + backend get_backend() const noexcept; + + /// Check if device is a CPU device. + /// + /// \return true if SYCL device is a CPU device. + bool is_cpu() const; + + /// Check if device is a GPU device. + /// + /// \return true if SYCL device is a GPU device. + bool is_gpu() const; + + /// Check if device is an accelerator device. + /// + /// \return true if SYCL device is an accelerator device. + bool is_accelerator() const; + + /// Get associated SYCL platform. + /// + /// \return The associated SYCL platform. + platform get_platform() const; + + /// Queries this SYCL device for information requested by the template + /// parameter param. + /// + /// \return device info of type described in 4.6.4.4. + template + detail::is_device_info_desc_t get_info() const; + + /// Queries this SYCL device for SYCL backend-specific information. + /// + /// The return type depends on information being queried. + template + typename detail::is_backend_info_desc::return_type + get_backend_info() const; + + /// Queries which optional features this device supports (if any). + /// + /// \return true if this device has the given aspect. + bool has(aspect asp) const; + + /// Partition device into sub devices. + /// + /// Available only when prop is info::partition_property::partition_equally. + /// If this SYCL device does not support + /// info::partition_property::partition_equally a feature_not_supported + /// exception will be thrown. + /// + /// \param ComputeUnits is a desired count of compute units in each sub + /// device. + /// \return sub devices partitioned from this SYCL device equally based on the + /// ComputeUnits parameter. + template + std::vector create_sub_devices(size_t ComputeUnits) const; + + /// Partition device into sub devices. + /// + /// Available only when prop is info::partition_property::partition_by_counts. + /// If this SYCL device does not support + /// info::partition_property::partition_by_counts a feature_not_supported + /// exception will be thrown. + /// + /// \param Counts is a std::vector of desired compute units in sub devices. + /// \return sub devices partitioned from this SYCL device by count sizes based + /// on the Counts parameter. + template + std::vector + create_sub_devices(const std::vector &Counts) const; + + /// Partition device into sub devices. + /// + /// Available only when prop is + /// info::partition_property::partition_by_affinity_domain. If this SYCL + /// device does not support + /// info::partition_property::partition_by_affinity_domain or the SYCL device + /// does not support provided info::affinity_domain provided a + /// feature_not_supported exception will be thrown. + /// + /// \param AffinityDomain is one of the values described in Table 4.20 of the + /// SYCL 2020 specification. + /// \return sub devices partitioned from this SYCL device by affinity domain + /// based on the AffinityDomain parameter. + template + std::vector + create_sub_devices(info::partition_affinity_domain AffinityDomain) const; + + /// Query available SYCL devices. + /// + /// \param deviceType is one of the values described in A.3 of the SYCL 2020 + /// specification. + /// \return all SYCL devices available in the system of the device type + /// specified. + static std::vector + get_devices(info::device_type deviceType = info::device_type::all); + +private: + device(detail::DeviceImpl &Impl) : impl(&Impl) {} + detail::DeviceImpl *impl; + + friend sycl::detail::ImplUtils; +}; // class device + +_LIBSYCL_END_NAMESPACE_SYCL + +template <> +struct std::hash : public sycl::detail::HashBase {}; + +#endif // _LIBSYCL___IMPL_DEVICE_HPP diff --git a/libsycl/include/sycl/__impl/device_selector.hpp b/libsycl/include/sycl/__impl/device_selector.hpp new file mode 100644 index 0000000000000..00a5f0ec594bf --- /dev/null +++ b/libsycl/include/sycl/__impl/device_selector.hpp @@ -0,0 +1,122 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains the declaration of the standard device selectors +/// (SYCL 2020 4.6.1.1. Device selector). +/// +//===----------------------------------------------------------------------===// + +#ifndef _LIBSYCL___IMPL_DEVICE_SELECTOR_HPP +#define _LIBSYCL___IMPL_DEVICE_SELECTOR_HPP + +#include +#include + +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL + +class device; + +namespace detail { + +// SYCL 2020 4.6.1.1. Device selector: +// The interface for a device selector is any object that meets the C++ named +// requirement Callable, taking a parameter of type const device & and returning +// a value that is implicitly convertible to int. +using DeviceSelectorInvocableType = std::function; + +template +using EnableIfDeviceSelectorIsInvocable = std::enable_if_t< + std::is_invocable_r_v>; + +/// Returns a SYCL device instance chosen by the device selector provided. +/// +/// \param DeviceSelector is SYCL 2020 device selector, a simple callable that +/// takes a device and returns an int. +/// \return device chosen by selector. +_LIBSYCL_EXPORT device +SelectDevice(const DeviceSelectorInvocableType &DeviceSelector); + +} // namespace detail + +/// Standard device selector to select SYCL device from any supported SYCL +/// backend based on an implementation-defined heuristic. +/// +/// \param Dev device to calculate the score for. +/// \return score value for the provided device. Further device selection is +/// based on score values. +_LIBSYCL_EXPORT int default_selector_v(const device &Dev); + +/// Standard device selector to select SYCL device from any supported SYCL +/// backend for which the device type is info::device_type::gpu. +/// +/// \param Dev device to calculate the score for. +/// \return score value for the provided device. Further device selection is +/// based on score values. +_LIBSYCL_EXPORT int gpu_selector_v(const device &Dev); + +/// Standard device selector to select SYCL device from any supported SYCL +/// backend for which the device type is info::device_type::cpu. +/// +/// \param Dev device to calculate the score for. +/// \return score value for the provided device. Further device selection is +/// based on score values. +_LIBSYCL_EXPORT int cpu_selector_v(const device &Dev); + +/// Standard device selector to select SYCL device from any supported SYCL +/// backend for which the device type is info::device_type::accelerator. +/// +/// \param Dev device to calculate the score for. +/// \return score value for the provided device. Further device selection is +/// based on score values. +_LIBSYCL_EXPORT int accelerator_selector_v(const device &Dev); + +/// Returns a selector object that selects a SYCL device from any supported SYCL +/// backend which contains all the requested aspects. +/// +/// \param RequireList requested aspects, i.e. for the specific device dev and +/// each aspect devAspect from RequireList dev.has(devAspect) equals true. +/// \param DenyList all the aspects that have to be avoided, i.e. for the +/// specific device dev and each aspect devAspect from denyList +/// dev.has(devAspect) equals false. +/// \return a selector object +_LIBSYCL_EXPORT detail::DeviceSelectorInvocableType +aspect_selector(const std::vector &RequireList, + const std::vector &DenyList = {}); + +/// Returns a selector object that selects a SYCL device from any supported SYCL +/// backend which contains all the requested aspects. +/// +/// \param AspectList requested aspects, i.e. for the specific device dev and +/// each aspect devAspect from AspectList dev.has(devAspect) equals true. +/// \return a selector object +template +detail::DeviceSelectorInvocableType aspect_selector(AspectListT... AspectList) { + std::vector RequireList; + RequireList.reserve(sizeof...(AspectList)); + (RequireList.emplace_back(AspectList), ...); + + return aspect_selector(RequireList, {}); +} + +/// Returns a selector object that selects a SYCL device from any supported SYCL +/// backend which contains all the requested aspects. +/// +/// \param AspectList requested aspects, i.e. for the specific device dev and +/// each aspect devAspect from AspectList dev.has(devAspect) equals true. +/// \return a selector object +template +detail::DeviceSelectorInvocableType aspect_selector() { + return aspect_selector({AspectList...}, {}); +} + +_LIBSYCL_END_NAMESPACE_SYCL + +#endif //_LIBSYCL___IMPL_DEVICE_SELECTOR_HPP diff --git a/libsycl/include/sycl/__impl/info/device.hpp b/libsycl/include/sycl/__impl/info/device.hpp new file mode 100644 index 0000000000000..ffdb2d4b0efd2 --- /dev/null +++ b/libsycl/include/sycl/__impl/info/device.hpp @@ -0,0 +1,79 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains the declaration of SYCL 2020 device info types. +/// +//===----------------------------------------------------------------------===// + +#ifndef _LIBSYCL___IMPL_INFO_DEVICE_HPP +#define _LIBSYCL___IMPL_INFO_DEVICE_HPP + +#include +#include +#include +#include + +#include +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL + +class device; +class platform; + +namespace detail { +template +using is_device_info_desc_t = typename is_info_desc::return_type; +} // namespace detail + +// SYCL 2020 A.3. Device information descriptors. +namespace info { + +enum class partition_property : std::uint32_t { + no_partition = 0, + partition_equally, + partition_by_counts, + partition_by_affinity_domain +}; + +enum class partition_affinity_domain : std::uint32_t { + not_applicable = 0, + numa, + L4_cache, + L3_cache, + L2_cache, + L1_cache, + next_partitionable +}; + +namespace device { +// SYCL 2020 4.6.4.4. Information descriptors. + +struct device_type : detail::info_desc_tag { + using return_type = sycl::info::device_type; +}; +struct name : detail::info_desc_tag { + using return_type = std::string; +}; +struct vendor : detail::info_desc_tag { + using return_type = std::string; +}; +struct driver_version : detail::info_desc_tag { + using return_type = std::string; +}; +struct platform : detail::info_desc_tag { + using return_type = sycl::platform; +}; + +} // namespace device +} // namespace info + +_LIBSYCL_END_NAMESPACE_SYCL + +#endif // _LIBSYCL___IMPL_INFO_DEVICE_HPP diff --git a/libsycl/include/sycl/__impl/info/device_type.hpp b/libsycl/include/sycl/__impl/info/device_type.hpp new file mode 100644 index 0000000000000..90db655063859 --- /dev/null +++ b/libsycl/include/sycl/__impl/info/device_type.hpp @@ -0,0 +1,35 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBSYCL___IMPL_INFO_DEVICE_TYPE_HPP +#define _LIBSYCL___IMPL_INFO_DEVICE_TYPE_HPP + +#include + +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL + +namespace info { + +// SYCL 2020 4.6.4.7.1. Device type. +enum class device_type : std::uint32_t { + cpu = 0, + gpu, + accelerator, + custom, + automatic, + host, // Deprecated by SYCL 2020 + all +}; + +} // namespace info + +_LIBSYCL_END_NAMESPACE_SYCL + +#endif // _LIBSYCL___IMPL_INFO_DEVICE_TYPE_HPP diff --git a/libsycl/include/sycl/__impl/platform.hpp b/libsycl/include/sycl/__impl/platform.hpp index c7915eaa224fe..63ded9b6f440f 100644 --- a/libsycl/include/sycl/__impl/platform.hpp +++ b/libsycl/include/sycl/__impl/platform.hpp @@ -15,9 +15,11 @@ #ifndef _LIBSYCL___IMPL_PLATFORM_HPP #define _LIBSYCL___IMPL_PLATFORM_HPP +#include #include #include #include +#include #include #include @@ -25,6 +27,8 @@ _LIBSYCL_BEGIN_NAMESPACE_SYCL +class device; + namespace detail { class PlatformImpl; } // namespace detail @@ -56,6 +60,16 @@ class _LIBSYCL_EXPORT platform { /// \return the backend associated with this platform. backend get_backend() const noexcept; + /// Returns all SYCL devices associated with this platform. + /// + /// If there are no devices that match given device + /// type, resulting vector is empty. + /// + /// \param DeviceType is a SYCL device type. + /// \return a vector of SYCL devices matching given device type. + std::vector + get_devices(info::device_type DeviceType = info::device_type::all) const; + /// Queries this SYCL platform for info. /// /// The return type depends on information being queried. @@ -69,6 +83,15 @@ class _LIBSYCL_EXPORT platform { typename detail::is_backend_info_desc::return_type get_backend_info() const; + /// Indicates if all of the SYCL devices on this platform have the + /// given aspect. + /// + /// \param Aspect is one of the values defined in SYCL 2020 Section 4.6.4.5. + /// + /// \return true if all of the SYCL devices on this platform have the + /// given aspect. + bool has(aspect Aspect) const; + /// Returns all SYCL platforms from all backends that are available in the /// system. /// diff --git a/libsycl/include/sycl/sycl.hpp b/libsycl/include/sycl/sycl.hpp index ef91ab2381770..3e7f81092256c 100644 --- a/libsycl/include/sycl/sycl.hpp +++ b/libsycl/include/sycl/sycl.hpp @@ -14,6 +14,8 @@ #ifndef _LIBSYCL_SYCL_HPP #define _LIBSYCL_SYCL_HPP +#include +#include #include #include diff --git a/libsycl/src/CMakeLists.txt b/libsycl/src/CMakeLists.txt index 7ee228c8f7485..0a83f2ef36443 100644 --- a/libsycl/src/CMakeLists.txt +++ b/libsycl/src/CMakeLists.txt @@ -83,7 +83,10 @@ endfunction(add_sycl_rt_library) set(LIBSYCL_SOURCES "exception.cpp" "exception_list.cpp" + "device.cpp" + "device_selector.cpp" "platform.cpp" + "detail/device_impl.cpp" "detail/global_objects.cpp" "detail/platform_impl.cpp" "detail/offload/offload_utils.cpp" diff --git a/libsycl/src/detail/device_impl.cpp b/libsycl/src/detail/device_impl.cpp new file mode 100644 index 0000000000000..de702cc4b7839 --- /dev/null +++ b/libsycl/src/detail/device_impl.cpp @@ -0,0 +1,55 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL + +namespace detail { + +bool DeviceImpl::has(aspect Aspect) const { + switch (Aspect) { + case (aspect::cpu): + return isCPU(); + case (aspect::gpu): + return isGPU(); + case (aspect::accelerator): + return isAccelerator(); + case (aspect::custom): + return false; + case (aspect::emulated): + return false; + case (aspect::host_debuggable): + return false; + default: + // Other aspects are not implemented yet + return false; + } +} + +info::device_type DeviceImpl::getDeviceType() const { + return getInfo(); +} + +bool DeviceImpl::isCPU() const { + return getDeviceType() == info::device_type::cpu; +} + +bool DeviceImpl::isGPU() const { + return getDeviceType() == info::device_type::gpu; +} + +bool DeviceImpl::isAccelerator() const { + return getDeviceType() == info::device_type::accelerator; +} + +backend DeviceImpl::getBackend() const { return MPlatform.getBackend(); } + +} // namespace detail +_LIBSYCL_END_NAMESPACE_SYCL diff --git a/libsycl/src/detail/device_impl.hpp b/libsycl/src/detail/device_impl.hpp new file mode 100644 index 0000000000000..5fd0893c99125 --- /dev/null +++ b/libsycl/src/detail/device_impl.hpp @@ -0,0 +1,127 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBSYCL_DEVICE_IMPL +#define _LIBSYCL_DEVICE_IMPL + +#include +#include + +#include +#include + +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL +namespace detail { + +class DeviceImpl { + // Helper to limit DeviceImpl creation. It must be created in platform ctor + // only. Using tag instead of private ctor + friend class to allow make_unique + // usage and to align with classes which impl is shared_ptr<>. + struct PrivateTag { + explicit PrivateTag() = default; + }; + friend class PlatformImpl; + +public: + /// Constructs a SYCL device instance using the provided + /// offload device instance. + /// + /// \param Device is a raw offload library handle representing device. + /// \param Platform is a platform this device belongs to. + /// All device impls must be created in corresponding platform ctor. + explicit DeviceImpl(ol_device_handle_t Device, PlatformImpl &Platform, + PrivateTag) + : MOffloadDevice(Device), MPlatform(Platform) {} + + ~DeviceImpl() = default; + + /// Queries device type from offloading runtime + /// + /// \return device type of the device + info::device_type getDeviceType() const; + + /// Check if device is a CPU device + /// + /// \return true if SYCL device is a CPU device + bool isCPU() const; + + /// Check if device is a GPU device + /// + /// \return true if SYCL device is a GPU device + bool isGPU() const; + + /// Check if device is an accelerator device + /// + /// \return true if SYCL device is an accelerator device + bool isAccelerator() const; + + /// Returns the backend associated with this device. + /// + /// \return the sycl::backend associated with this device. + backend getBackend() const; + + /// Returns the implementation class object of platform associated with this + /// device. + /// + /// \return platform implementation object this device belongs to. + PlatformImpl &getPlatformImpl() const { return MPlatform; } + + /// Checks if this device supports aspect. + /// + /// \param Aspect to perform a check of. + /// \return true if this device has the given aspect. + bool has(aspect Aspect) const; + + /// Queries this device for information requested by the template parameter + /// param. + /// The return type depends on information being queried. + template typename Param::return_type getInfo() const { + using namespace info::device; + using Map = info_ol_mapping; + + constexpr ol_device_info_t olInfo = map_info_desc( + Map::M{OL_DEVICE_INFO_TYPE}, + Map::M{OL_DEVICE_INFO_NAME}, + Map::M{OL_DEVICE_INFO_VENDOR}, + Map::M{OL_DEVICE_INFO_DRIVER_VERSION}); + + size_t ExpectedSize = 0; + callAndThrow(olGetDeviceInfoSize, MOffloadDevice, olInfo, &ExpectedSize); + + if constexpr (std::is_same_v) { + std::string Result; + // liboffload counts null terminator in the size while std::string + // doesn't. + Result.resize(ExpectedSize - 1); + callAndThrow(olGetDeviceInfo, MOffloadDevice, olInfo, ExpectedSize, + Result.data()); + return Result; + } else if constexpr (olInfo == OL_DEVICE_INFO_TYPE) { + assert((sizeof(typename Param::return_type) == ExpectedSize) && + "Size of info descriptor reported by backend doesn't match with " + "expected."); + ol_device_type_t olType{}; + callAndThrow(olGetDeviceInfo, MOffloadDevice, olInfo, sizeof(olType), + &olType); + return convertDeviceTypeToSYCL(olType); + } else + static_assert(false && "Info descriptor is not properly supported"); + } + +private: + ol_device_handle_t MOffloadDevice = {}; + PlatformImpl &MPlatform; +}; + +} // namespace detail + +_LIBSYCL_END_NAMESPACE_SYCL + +#endif // _LIBSYCL_DEVICE_IMPL diff --git a/libsycl/src/detail/global_objects.cpp b/libsycl/src/detail/global_objects.cpp index fe29f5e7d72c0..fa7274d137040 100644 --- a/libsycl/src/detail/global_objects.cpp +++ b/libsycl/src/detail/global_objects.cpp @@ -29,7 +29,7 @@ std::vector &getPlatformCache() { return PlatformCache; } -void shutdown() { +static void shutdown() { // No error reporting in shutdown std::ignore = olShutDown(); } diff --git a/libsycl/src/detail/offload/offload_topology.cpp b/libsycl/src/detail/offload/offload_topology.cpp index 624f987a5d1f4..5e595e520a452 100644 --- a/libsycl/src/detail/offload/offload_topology.cpp +++ b/libsycl/src/detail/offload/offload_topology.cpp @@ -11,18 +11,57 @@ #include #include -#include _LIBSYCL_BEGIN_NAMESPACE_SYCL namespace detail { +// Platforms for this backend +range_view OffloadTopology::getPlatforms() const { + return {MPlatforms.data(), MPlatforms.size()}; +} + +// Devices for a specific platform (PlatformId is index into Platforms) +range_view +OffloadTopology::getDevices(size_t PlatformId) const { + if (PlatformId >= MDeviceRange.size()) { + return {nullptr, 0}; + } + return MDeviceRange[PlatformId]; +} + +void OffloadTopology::registerNewPlatformsAndDevices( + Platform2DevContainer &PlatformsAndDev) { + if (!PlatformsAndDev.size()) + return; + + // MDeviceRange is populated with iterators of MDevices. Allocate required + // space in advance to keep them valid. + MDevices.reserve(PlatformsAndDev.size()); + + for (auto &[Platform, NewDev] : PlatformsAndDev) { + MDevices.push_back(NewDev); + + // Platform is not unique within PlatformsAndDev but the container is sorted + if (MPlatforms.empty() || MPlatforms.back() != Platform) { + MPlatforms.push_back(Platform); + range_view R{&MDevices.back(), 1 /*Size == 1*/}; + MDeviceRange.push_back(R); + } else { + // Device is inserted already, just increment device count for the current + // platform + MDeviceRange.back().len++; + } + } +} + void discoverOffloadDevices() { callAndThrow(olInit); + // liboffload returns devices sorted by backend + platform. We rely on this + // behavior during device enumeration. using PerBackendDataType = - std::array, - OL_PLATFORM_BACKEND_LAST>; + std::array; PerBackendDataType Mapping; // olIterateDevices() calls the lambda for each device. Devices that fail @@ -31,17 +70,19 @@ void discoverOffloadDevices() { // first failure and interrupt iteration. callNoCheck( olIterateDevices, - [](ol_device_handle_t Dev, void *User) -> bool { - auto *Data = static_cast(User); - ol_platform_handle_t Plat = nullptr; - ol_result_t Res = callNoCheck( - olGetDeviceInfo, Dev, OL_DEVICE_INFO_PLATFORM, sizeof(Plat), &Plat); + [](ol_device_handle_t Dev, void *UserData) -> bool { + auto *Data = static_cast(UserData); + + ol_platform_handle_t Platform = nullptr; + ol_result_t Res = + callNoCheck(olGetDeviceInfo, Dev, OL_DEVICE_INFO_PLATFORM, + sizeof(Platform), &Platform); // If an error occurs, ignore the device and continue iteration. if (Res != OL_SUCCESS) return true; ol_platform_backend_t OlBackend = OL_PLATFORM_BACKEND_UNKNOWN; - Res = callNoCheck(olGetPlatformInfo, Plat, OL_PLATFORM_INFO_BACKEND, + Res = callNoCheck(olGetPlatformInfo, Platform, OL_PLATFORM_INFO_BACKEND, sizeof(OlBackend), &OlBackend); // If an error occurs, ignore the device and continue iteration. if (Res != OL_SUCCESS) @@ -58,9 +99,7 @@ void discoverOffloadDevices() { if (OlBackend >= OL_PLATFORM_BACKEND_LAST) return true; - auto &[Map, DevCount] = (*Data)[static_cast(OlBackend)]; - Map[Plat].push_back(Dev); - DevCount++; + (*Data)[static_cast(OlBackend)].push_back({Platform, Dev}); return true; }, &Mapping); @@ -69,7 +108,7 @@ void discoverOffloadDevices() { for (size_t I = 0; I < OL_PLATFORM_BACKEND_LAST; ++I) { OffloadTopology &Topo = OffloadTopologies[I]; Topo.setBackend(static_cast(I)); - Topo.registerNewPlatformsAndDevices(Mapping[I].first, Mapping[I].second); + Topo.registerNewPlatformsAndDevices(Mapping[I]); } } diff --git a/libsycl/src/detail/offload/offload_topology.hpp b/libsycl/src/detail/offload/offload_topology.hpp index dbd98f953b7e4..4d811f1e444d5 100644 --- a/libsycl/src/detail/offload/offload_topology.hpp +++ b/libsycl/src/detail/offload/offload_topology.hpp @@ -14,7 +14,6 @@ #include #include -#include #include _LIBSYCL_BEGIN_NAMESPACE_SYCL @@ -31,8 +30,8 @@ template struct range_view { size_t size() const { return len; } }; -using PlatformWithDevStorageType = - std::unordered_map>; +using Platform2DevContainer = + std::vector>; /// Contiguous global storage of platform handlers and device handles (grouped /// by platform) for a backend. @@ -45,71 +44,42 @@ struct OffloadTopology { /// \param B new backend value. void setBackend(ol_platform_backend_t B) { MBackend = B; } + /// Queries backend of this topology. + /// + /// \returns backend of this topology. + ol_platform_backend_t getBackend() const { return MBackend; } + /// Returns all platforms associated with this topology. /// /// \returns minimal span-like view to platforms associated with this /// topology. - range_view platforms() const { - return {MPlatforms.data(), MPlatforms.size()}; - } + range_view getPlatforms() const; /// Returns all devices associated with specific platform. /// - /// \param PlatformId platform_id is index into MPlatforms. + /// \param PlatformId is index into MPlatforms. /// /// \returns minimal span-like view to devices associated with specified /// platform. - range_view - devicesForPlatform(size_t PlatformId) const { - if (PlatformId >= MDevRangePerPlatformId.size()) { - assert(false && "Platform index exceeds number of platforms."); - return {nullptr, 0}; - } - return MDevRangePerPlatformId[PlatformId]; - } + range_view getDevices(size_t PlatformId) const; /// Register new platform and devices into this topology. /// - /// \param PlatformsAndDev associative container with platforms & devices. - /// \param TotalDevCount total device count for the platform. - void - registerNewPlatformsAndDevices(PlatformWithDevStorageType &PlatformsAndDev, - size_t TotalDevCount) { - if (!PlatformsAndDev.size()) - return; - - MPlatforms.reserve(PlatformsAndDev.size()); - MDevRangePerPlatformId.reserve(MPlatforms.size()); - MDevices.reserve(TotalDevCount); - - for (auto &[NewPlatform, NewDevs] : PlatformsAndDev) { - MPlatforms.push_back(NewPlatform); - range_view R{MDevices.data() + MDevices.size(), - NewDevs.size()}; - MDevices.insert(MDevices.end(), NewDevs.begin(), NewDevs.end()); - MDevRangePerPlatformId.push_back(R); - } - - assert(TotalDevCount == MDevices.size()); - } - - /// Queries backend of this topology. - /// - /// \returns backend of this topology. - ol_platform_backend_t backend() const { return MBackend; } + /// \param PlatformsAndDev collection of platforms & devices. + void registerNewPlatformsAndDevices(Platform2DevContainer &PlatformsAndDev); private: ol_platform_backend_t MBackend = OL_PLATFORM_BACKEND_UNKNOWN; // Platforms and devices belonging to this backend (flattened) std::vector MPlatforms; - std::vector MDevices; // sorted by platform + + // Devices are sorted by platform (guarantee from liboffload) + std::vector MDevices; // Vector holding range of devices for each platform (index is platform index - // within MPlatforms) - std::vector> - MDevRangePerPlatformId; // MDevRangePerPlatformId.size() == - // MPlatforms.size() + // within Platforms), so MDeviceRange.size() == MPlatforms.size() + std::vector> MDeviceRange; }; // Initialize the topologies by calling olIterateDevices. diff --git a/libsycl/src/detail/offload/offload_utils.cpp b/libsycl/src/detail/offload/offload_utils.cpp index ed3d197672218..9a2609daddcee 100644 --- a/libsycl/src/detail/offload/offload_utils.cpp +++ b/libsycl/src/detail/offload/offload_utils.cpp @@ -56,8 +56,35 @@ backend convertBackend(ol_platform_backend_t Backend) { case OL_PLATFORM_BACKEND_AMDGPU: return backend::hip; default: - throw exception(make_error_code(errc::runtime), - "convertBackend: Unsupported backend"); + throw exception(make_error_code(errc::runtime), "Unsupported backend"); + } +} + +ol_device_type_t convertDeviceTypeToOL(info::device_type DeviceType) { + switch (DeviceType) { + case info::device_type::all: + return OL_DEVICE_TYPE_ALL; + case info::device_type::gpu: + return OL_DEVICE_TYPE_GPU; + case info::device_type::cpu: + return OL_DEVICE_TYPE_CPU; + case info::device_type::automatic: + return OL_DEVICE_TYPE_DEFAULT; + default: + throw exception(sycl::make_error_code(sycl::errc::runtime), + "Device type is not supported"); + } +} + +info::device_type convertDeviceTypeToSYCL(ol_device_type_t DeviceType) { + switch (DeviceType) { + case OL_DEVICE_TYPE_GPU: + return info::device_type::gpu; + case OL_DEVICE_TYPE_CPU: + return info::device_type::cpu; + default: + throw exception(sycl::make_error_code(sycl::errc::runtime), + "Device type is not supported"); } } diff --git a/libsycl/src/detail/offload/offload_utils.hpp b/libsycl/src/detail/offload/offload_utils.hpp index e6113e5479f97..f32326fb87fc9 100644 --- a/libsycl/src/detail/offload/offload_utils.hpp +++ b/libsycl/src/detail/offload/offload_utils.hpp @@ -12,6 +12,7 @@ #include #include #include +#include #include @@ -85,6 +86,20 @@ void callAndThrow(FunctionType &Function, ArgsT &&...Args) { /// \returns sycl::backend matching specified liboffload backend. backend convertBackend(ol_platform_backend_t Backend); +/// Converts SYCL device type to liboffload type. +/// +/// \param DeviceType SYCL device type. +/// +/// \returns ol_device_type_t matching specified SYCL device type. +ol_device_type_t convertDeviceTypeToOL(info::device_type DeviceType); + +/// Converts liboffload device type to SYCL type. +/// +/// \param DeviceType liboffload device type. +/// +/// \returns SYCL device type matching specified liboffload device type. +info::device_type convertDeviceTypeToSYCL(ol_device_type_t DeviceType); + /// Helper to map SYCL information descriptors to OL__INFO_. /// /// Typical usage: diff --git a/libsycl/src/detail/platform_impl.cpp b/libsycl/src/detail/platform_impl.cpp index 28bf709d5c074..0116ad68d4bdd 100644 --- a/libsycl/src/detail/platform_impl.cpp +++ b/libsycl/src/detail/platform_impl.cpp @@ -9,9 +9,13 @@ #include #include +#include #include #include +#include +#include + _LIBSYCL_BEGIN_NAMESPACE_SYCL namespace detail { @@ -19,6 +23,7 @@ namespace detail { PlatformImpl &PlatformImpl::getPlatformImpl(ol_platform_handle_t Platform) { auto &PlatformCache = getPlatformCache(); for (auto &PlatImpl : PlatformCache) { + assert(PlatImpl && "Platform impl can not be nullptr"); if (PlatImpl->getHandleRef() == Platform) return *PlatImpl; } @@ -32,10 +37,11 @@ PlatformImpl &PlatformImpl::getPlatformImpl(ol_platform_handle_t Platform) { const std::vector &PlatformImpl::getPlatforms() { [[maybe_unused]] static auto InitPlatformsOnce = []() { discoverOffloadDevices(); + auto &PlatformCache = getPlatformCache(); for (const auto &Topo : getOffloadTopologies()) { size_t PlatformIndex = 0; - for (const auto &OffloadPlatform : Topo.platforms()) { + for (const auto &OffloadPlatform : Topo.getPlatforms()) { PlatformCache.emplace_back(std::make_unique( OffloadPlatform, PlatformIndex++, PrivateTag{})); } @@ -53,6 +59,65 @@ PlatformImpl::PlatformImpl(ol_platform_handle_t Platform, size_t PlatformIndex, sizeof(Backend), &Backend); MBackend = convertBackend(Backend); MOffloadBackend = Backend; + + const auto &Topologies = getOffloadTopologies(); + auto RootTopologyIt = std::find_if( + Topologies.begin(), Topologies.end(), [&](const OffloadTopology &Topo) { + return Topo.getBackend() == MOffloadBackend; + }); + + assert(RootTopologyIt != Topologies.end() && + "Root topology for platform must always exist"); + auto DevRange = RootTopologyIt->getDevices(MOffloadPlatformIndex); + MRootDevices.reserve(DevRange.size()); + std::for_each(DevRange.begin(), DevRange.end(), + [&](const ol_device_handle_t &Device) { + MRootDevices.emplace_back(std::make_unique( + Device, *this, DeviceImpl::PrivateTag{})); + }); +} + +const std::vector &PlatformImpl::getRootDevices() const { + return MRootDevices; +} + +bool PlatformImpl::has(aspect Aspect) const { + const auto &Devices = getRootDevices(); + return std::all_of( + Devices.begin(), Devices.end(), + [&Aspect](const DeviceImplUPtr &Device) { return Device->has(Aspect); }); } + +void PlatformImpl::iterateDevices( + info::device_type DeviceType, + std::function callback) const { + // Early exit if host/custom/accelerator device is requested: + // - host device is deprecated and not required by the SYCL 2020 + // specification. + // - accelerator and custom devices are unsupported by liboffload. + if ((DeviceType == info::device_type::host) || + (DeviceType == info::device_type::custom) || + (DeviceType == info::device_type::accelerator)) + return; + + const auto &DeviceImpls = getRootDevices(); + assert(!DeviceImpls.empty() && + "Platform can't exist without at least one device."); + + // TODO: Need a way to get default device from liboffload. + // As a temporal solution just return the first device for DeviceType == + // automatic. + if (DeviceType == info::device_type::automatic) { + callback(DeviceImpls[0].get()); + return; + } + + bool KeepAll = DeviceType == info::device_type::all; + for (auto &Impl : DeviceImpls) { + if (KeepAll || DeviceType == Impl->getDeviceType()) + callback(Impl.get()); + } +} + } // namespace detail _LIBSYCL_END_NAMESPACE_SYCL diff --git a/libsycl/src/detail/platform_impl.hpp b/libsycl/src/detail/platform_impl.hpp index a17b5d70a1828..e23ce6a492281 100644 --- a/libsycl/src/detail/platform_impl.hpp +++ b/libsycl/src/detail/platform_impl.hpp @@ -13,10 +13,12 @@ #include #include +#include #include #include +#include #include #include #include @@ -26,9 +28,15 @@ _LIBSYCL_BEGIN_NAMESPACE_SYCL namespace detail { +class DeviceImpl; + using PlatformImplUPtr = std::unique_ptr; +using DeviceImplUPtr = std::unique_ptr; class PlatformImpl { + // Helper to limit PlatformImpl creation. It must be created in getPlatforms + // only. Using tag instead of private ctor + friend class to allow make_unique + // usage and to align with classes which impl is shared_ptr<>. struct PrivateTag { explicit PrivateTag() = default; }; @@ -73,7 +81,16 @@ class PlatformImpl { /// \return the PlatformImpl representing the offloading RT platform. static PlatformImpl &getPlatformImpl(ol_platform_handle_t Platform); - /// Queries this platform for info. + /// Indicates if all of the SYCL devices on this platform have the + /// given aspect. + /// + /// \param Aspect is one of the values defined in SYCL 2020 Section 4.6.4.5. + /// + /// \return true all of the SYCL devices on this platform have the + /// given aspect. + bool has(aspect Aspect) const; + + /// Queries this SYCL platform for info. /// /// The return type depends on information being queried. template typename Param::return_type getInfo() const { @@ -99,11 +116,20 @@ class PlatformImpl { return Result; } + /// Calls "callback" with every root device of type == DeviceType associated + /// with this platform + void iterateDevices(info::device_type DeviceType, + std::function callback) const; + private: + const std::vector &getRootDevices() const; + ol_platform_handle_t MOffloadPlatform{}; size_t MOffloadPlatformIndex{}; ol_platform_backend_t MOffloadBackend{OL_PLATFORM_BACKEND_UNKNOWN}; backend MBackend{}; + + std::vector MRootDevices; }; } // namespace detail diff --git a/libsycl/src/device.cpp b/libsycl/src/device.cpp new file mode 100644 index 0000000000000..db61d2ff3a22e --- /dev/null +++ b/libsycl/src/device.cpp @@ -0,0 +1,104 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL + +device::device() : device(default_selector_v) {} + +bool device::is_cpu() const { return impl->isCPU(); } + +bool device::is_gpu() const { return impl->isGPU(); } + +bool device::is_accelerator() const { return impl->isAccelerator(); } + +platform device::get_platform() const { + return detail::createSyclObjFromImpl(impl->getPlatformImpl()); +} + +backend device::get_backend() const noexcept { return impl->getBackend(); } + +std::vector device::get_devices(info::device_type DeviceType) { + std::vector Devices; + + // Not calling platform::get_devices to avoid multiple vector packing + for (auto &PlatformImpl : detail::PlatformImpl::getPlatforms()) { + assert(PlatformImpl && "PlatformImpl can not be nullptr"); + PlatformImpl->iterateDevices( + DeviceType, [&Devices](detail::DeviceImpl *DevImpl) { + assert(DevImpl && "Device impl can't be nullptr"); + Devices.push_back(detail::createSyclObjFromImpl(*DevImpl)); + }); + } + + return Devices; +} + +template +std::vector device::create_sub_devices(size_t ComputeUnits) const { + throw exception(make_error_code(errc::feature_not_supported), + "Partitioning is not supported."); +} + +template _LIBSYCL_EXPORT std::vector +device::create_sub_devices( + size_t ComputeUnits) const; + +template +std::vector +device::create_sub_devices(const std::vector &Counts) const { + throw exception(make_error_code(errc::feature_not_supported), + "Partitioning is not supported."); +} + +template _LIBSYCL_EXPORT std::vector +device::create_sub_devices( + const std::vector &Counts) const; + +template +std::vector device::create_sub_devices( + info::partition_affinity_domain AffinityDomain) const { + throw exception(make_error_code(errc::feature_not_supported), + "Partitioning is not supported."); +} + +template _LIBSYCL_EXPORT std::vector device::create_sub_devices< + info::partition_property::partition_by_affinity_domain>( + info::partition_affinity_domain AffinityDomain) const; + +bool device::has(aspect Aspect) const { return impl->has(Aspect); } + +template +detail::is_device_info_desc_t device::get_info() const { + return impl->getInfo(); +} + +template <> +_LIBSYCL_EXPORT detail::is_device_info_desc_t +device::get_info() const { + static_assert( + std::is_same_v); + return get_platform(); +} + +#define _LIBSYCL_EXPORT_GET_INFO(Desc) \ + template _LIBSYCL_EXPORT detail::is_device_info_desc_t \ + device::get_info() const; +_LIBSYCL_EXPORT_GET_INFO(device_type) +_LIBSYCL_EXPORT_GET_INFO(name) +_LIBSYCL_EXPORT_GET_INFO(vendor) +_LIBSYCL_EXPORT_GET_INFO(driver_version) +#undef _LIBSYCL_EXPORT_GET_INFO + +_LIBSYCL_END_NAMESPACE_SYCL diff --git a/libsycl/src/device_selector.cpp b/libsycl/src/device_selector.cpp new file mode 100644 index 0000000000000..86e5f5657c6b5 --- /dev/null +++ b/libsycl/src/device_selector.cpp @@ -0,0 +1,118 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#include + +#include + +_LIBSYCL_BEGIN_NAMESPACE_SYCL + +static constexpr int MatchedTypeDefaultScore = 1000; +static constexpr int GPUDeviceDefaultScore = 500; +static constexpr int CPUDeviceDefaultScore = 300; +static constexpr int AccDeviceDefaultScore = 75; +static constexpr int RejectDeviceScore = -1; + +static int getDevicePreference(const device &Device) { + int Score = 0; + const auto &DeviceImpl = detail::getSyclObjImpl(Device); + + // TODO: increase score for devices with compatible program images. + + if (DeviceImpl->getBackend() == backend::level_zero) + Score += 50; + + return Score; +} + +_LIBSYCL_EXPORT int default_selector_v(const device &dev) { + int Score = getDevicePreference(dev); + + if (dev.is_gpu()) + Score += GPUDeviceDefaultScore; + else if (dev.is_cpu()) + Score += CPUDeviceDefaultScore; + else if (dev.is_accelerator()) + Score += AccDeviceDefaultScore; + + return Score; +} + +_LIBSYCL_EXPORT int gpu_selector_v(const device &Dev) { + return Dev.is_gpu() ? MatchedTypeDefaultScore + getDevicePreference(Dev) + : RejectDeviceScore; +} + +_LIBSYCL_EXPORT int cpu_selector_v(const device &Dev) { + return Dev.is_cpu() ? MatchedTypeDefaultScore + getDevicePreference(Dev) + : RejectDeviceScore; +} + +_LIBSYCL_EXPORT int accelerator_selector_v(const device &Dev) { + return Dev.is_accelerator() + ? MatchedTypeDefaultScore + getDevicePreference(Dev) + : RejectDeviceScore; +} + +_LIBSYCL_EXPORT detail::DeviceSelectorInvocableType +aspect_selector(const std::vector &RequireList, + const std::vector &DenyList) { + return [=](const sycl::device &Dev) { + // 4.6.1.1. Device selector: + // If no aspects are passed in, the generated selector behaves like + // default_selector_v. + if (RequireList.empty() && DenyList.empty()) + return default_selector_v(Dev); + + auto HasAspect = [&Dev](const aspect &Aspect) -> bool { + return Dev.has(Aspect); + }; + if (!std::all_of(RequireList.begin(), RequireList.end(), HasAspect)) + return RejectDeviceScore; + + if (std::any_of(DenyList.begin(), DenyList.end(), HasAspect)) + return RejectDeviceScore; + + return MatchedTypeDefaultScore + getDevicePreference(Dev); + }; +} + +namespace detail { + +_LIBSYCL_EXPORT device +SelectDevice(const DeviceSelectorInvocableType &DeviceSelector) { + int ChosenDeviceScore = RejectDeviceScore; + const device *ChosenDevice = nullptr; + + std::vector Devices = device::get_devices(); + for (const auto &Device : Devices) { + int CurrentDevScore = DeviceSelector(Device); + if (CurrentDevScore < 0) + continue; + + if ((ChosenDeviceScore < CurrentDevScore) || + ((ChosenDeviceScore == CurrentDevScore) && + (getDevicePreference(*ChosenDevice) < getDevicePreference(Device)))) { + ChosenDevice = &Device; + ChosenDeviceScore = CurrentDevScore; + } + } + + if (ChosenDevice != nullptr) + return *ChosenDevice; + + throw exception(make_error_code(errc::runtime), + "No device of requested type is available"); +} + +} // namespace detail + +_LIBSYCL_END_NAMESPACE_SYCL diff --git a/libsycl/src/platform.cpp b/libsycl/src/platform.cpp index 7f401583d6693..c04c0a6281774 100644 --- a/libsycl/src/platform.cpp +++ b/libsycl/src/platform.cpp @@ -8,10 +8,9 @@ #include +#include #include -#include - _LIBSYCL_BEGIN_NAMESPACE_SYCL backend platform::get_backend() const noexcept { return impl->getBackend(); } @@ -21,12 +20,24 @@ std::vector platform::get_platforms() { std::vector Platforms; Platforms.reserve(PlatformImpls.size()); for (auto &PlatformImpl : PlatformImpls) { - platform Platform = detail::createSyclObjFromImpl(*PlatformImpl); - Platforms.push_back(std::move(Platform)); + Platforms.emplace_back( + detail::createSyclObjFromImpl(*PlatformImpl.get())); } return Platforms; } +std::vector platform::get_devices(info::device_type DeviceType) const { + std::vector Devices; + impl->iterateDevices(DeviceType, [&Devices](detail::DeviceImpl *DevImpl) { + assert(DevImpl && "Device impl can't be nullptr"); + Devices.push_back(detail::createSyclObjFromImpl(*DevImpl)); + }); + + return Devices; +} + +bool platform::has(aspect Aspect) const { return impl->has(Aspect); } + template detail::is_platform_info_desc_t platform::get_info() const { return impl->getInfo(); diff --git a/libsycl/tools/sycl-ls/sycl-ls.cpp b/libsycl/tools/sycl-ls/sycl-ls.cpp index bd6c10899d748..2938d767a404b 100644 --- a/libsycl/tools/sycl-ls/sycl-ls.cpp +++ b/libsycl/tools/sycl-ls/sycl-ls.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// The "sycl-ls" utility lists all platforms discovered by SYCL. +// The "sycl-ls" utility lists all platforms and devices discovered by SYCL. // // There are two types of output: // concise (default) and @@ -36,14 +36,69 @@ inline std::string_view getBackendName(const backend &Backend) { return ""; } +std::string getDeviceTypeName(const device &Device) { + auto DeviceType = Device.get_info(); + switch (DeviceType) { + case info::device_type::cpu: + return "cpu"; + case info::device_type::gpu: + return "gpu"; + case info::device_type::host: + return "host"; + case info::device_type::accelerator: + return "accelerator"; + default: + return "unknown"; + } +} + +static void printDeviceInfo(const device &Device, bool Verbose, + const std::string &Prepend) { + auto DeviceName = Device.get_info(); + auto DeviceVendor = Device.get_info(); + auto DeviceDriverVersion = Device.get_info(); + + if (Verbose) { + std::cout << Prepend << "Type : " << getDeviceTypeName(Device) + << std::endl; + std::cout << Prepend << "Name : " << DeviceName << std::endl; + std::cout << Prepend << "Vendor : " << DeviceVendor << std::endl; + std::cout << Prepend << "Driver : " << DeviceDriverVersion + << std::endl; + } else { + std::cout << Prepend << ", " << DeviceName << " [" << DeviceDriverVersion + << "]" << std::endl; + } +} + +static void +printSelectorChoice(const detail::DeviceSelectorInvocableType &Selector, + const std::string &Prepend) { + try { + const auto &Device = device(Selector); + std::string DeviceTypeName = getDeviceTypeName(Device); + auto Platform = Device.get_info(); + auto PlatformName = Platform.get_info(); + printDeviceInfo(Device, false /*Verbose*/, + Prepend + DeviceTypeName + ", " + PlatformName); + } catch (const sycl::exception &Exception) { + std::string What = Exception.what(); + constexpr size_t MaxLength = 80; + // Truncate long string so it can fit in one-line + if (What.length() > MaxLength) + What = What.substr(0, MaxLength) + "..."; + std::cout << Prepend << What << std::endl; + } +} + int main(int argc, char **argv) { llvm::cl::opt Verbose( - "verbose", - llvm::cl::desc("Verbosely prints all the discovered platforms")); + "verbose", llvm::cl::desc("Verbosely prints all the discovered devices")); llvm::cl::alias VerboseShort("v", llvm::cl::desc("Alias for -verbose"), llvm::cl::aliasopt(Verbose)); llvm::cl::ParseCommandLineOptions( - argc, argv, "This program lists all backends discovered by SYCL"); + argc, argv, + "This program lists all backends and devices discovered by SYCL"); try { const auto &Platforms = platform::get_platforms(); @@ -55,8 +110,17 @@ int main(int argc, char **argv) { for (const auto &Platform : Platforms) { backend Backend = Platform.get_backend(); - std::cout << "[" << getBackendName(Backend) << ":" - << "unknown" << "]" << std::endl; + auto PlatformName = Platform.get_info(); + const auto &Devices = Platform.get_devices(); + + for (const auto &Device : Devices) { + std::cout << "[" << getBackendName(Backend) << ":" + << getDeviceTypeName(Device) << "]"; + std::cout << " "; + // Verbose parameter is set to false to print regular devices output + // first + printDeviceInfo(Device, false, PlatformName); + } } if (Verbose) { @@ -71,8 +135,19 @@ int main(int argc, char **argv) { std::cout << " Version : " << PlatformVersion << std::endl; std::cout << " Name : " << PlatformName << std::endl; std::cout << " Vendor : " << PlatformVendor << std::endl; - std::cout << " Devices : " << "unknown" << std::endl; + + const auto &Devices = Platform.get_devices(); + std::cout << " Devices : " << Devices.size() << std::endl; + for (const auto &Device : Devices) { + printDeviceInfo(Device, true, " "); + } } + + // Print built-in device selectors choice + printSelectorChoice(default_selector_v, "default_selector() : "); + printSelectorChoice(accelerator_selector_v, "accelerator_selector() : "); + printSelectorChoice(cpu_selector_v, "cpu_selector() : "); + printSelectorChoice(gpu_selector_v, "gpu_selector() : "); } } catch (sycl::exception &e) { std::cerr << "SYCL Exception encountered: " << e.what() << std::endl diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp index 3bc9c98bcdbc3..699d53ca6d2e3 100644 --- a/lld/COFF/Driver.cpp +++ b/lld/COFF/Driver.cpp @@ -1339,7 +1339,7 @@ void LinkerDriver::parsePDBAltPath() { cursor = secondMark + 1; } - ctx.config.pdbAltPath = buf; + ctx.config.pdbAltPath = std::move(buf); } /// Convert resource files and potentially merge input resource object diff --git a/lld/ELF/OutputSections.cpp b/lld/ELF/OutputSections.cpp index c9c63b3620b15..1522e608563ab 100644 --- a/lld/ELF/OutputSections.cpp +++ b/lld/ELF/OutputSections.cpp @@ -303,8 +303,6 @@ static void nopInstrFill(Ctx &ctx, uint8_t *buf, size_t size) { if (size == 0) return; unsigned i = 0; - if (size == 0) - return; std::vector> nopFiller = *ctx.target->nopInstrs; unsigned num = size / nopFiller.back().size(); for (unsigned c = 0; c < num; ++c) { diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp index 9ea5758eea8c2..16c2e50364e29 100644 --- a/lld/ELF/Relocations.cpp +++ b/lld/ELF/Relocations.cpp @@ -1212,8 +1212,7 @@ unsigned RelocScan::handleTlsRelocation(RelExpr expr, RelType type, !sec->file->ppc64DisableTLSRelax; // If we are producing an executable and the symbol is non-preemptable, it - // must be defined and the code sequence can be optimized to use - // Local-Exesec-> + // must be defined and the code sequence can be optimized to use Local-Exec. // // ARM and RISC-V do not support any relaxations for TLS relocations, however, // we can omit the DTPMOD dynamic relocations and resolve them at link time @@ -1226,7 +1225,7 @@ unsigned RelocScan::handleTlsRelocation(RelExpr expr, RelType type, // module index, with a special value of 0 for the current module. GOT[e1] is // unused. There only needs to be one module index entry. if (oneof(expr)) { - // Local-Dynamic relocs can be optimized to Local-Exesec-> + // Local-Dynamic relocs can be optimized to Local-Exec. if (execOptimize) { sec->addReloc({ctx.target->adjustTlsExpr(type, R_RELAX_TLS_LD_TO_LE), type, offset, addend, &sym}); @@ -1239,7 +1238,7 @@ unsigned RelocScan::handleTlsRelocation(RelExpr expr, RelType type, return 1; } - // Local-Dynamic relocs can be optimized to Local-Exesec-> + // Local-Dynamic relocs can be optimized to Local-Exec. if (expr == R_DTPREL) { if (execOptimize) expr = ctx.target->adjustTlsExpr(type, R_RELAX_TLS_LD_TO_LE); @@ -1249,7 +1248,7 @@ unsigned RelocScan::handleTlsRelocation(RelExpr expr, RelType type, // Local-Dynamic sequence where offset of tls variable relative to dynamic // thread pointer is stored in the got. This cannot be optimized to - // Local-Exesec-> + // Local-Exec. if (expr == R_TLSLD_GOT_OFF) { sym.setFlags(NEEDS_GOT_DTPREL); sec->addReloc({expr, type, offset, addend, &sym}); @@ -1284,7 +1283,7 @@ unsigned RelocScan::handleTlsRelocation(RelExpr expr, RelType type, // // R_RISCV_TLSDESC_{LOAD_LO12,ADD_LO12_I,CALL} reference a non-preemptible // label, so TLSDESC=>IE will be categorized as R_RELAX_TLS_GD_TO_LE. We fix - // the categorization in RISCV::relocateAllosec-> + // the categorization in RISCV::relocateAlloc. if (sym.isPreemptible) { sym.setFlags(NEEDS_TLSIE); sec->addReloc({ctx.target->adjustTlsExpr(type, R_RELAX_TLS_GD_TO_IE), diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index d7b1071eb7075..2cfc88d8389b0 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -540,43 +540,6 @@ void EhFrameSection::finalizeContents() { this->size = off; } -static uint64_t readFdeAddr(Ctx &ctx, uint8_t *buf, int size) { - switch (size) { - case DW_EH_PE_udata2: - return read16(ctx, buf); - case DW_EH_PE_sdata2: - return (int16_t)read16(ctx, buf); - case DW_EH_PE_udata4: - return read32(ctx, buf); - case DW_EH_PE_sdata4: - return (int32_t)read32(ctx, buf); - case DW_EH_PE_udata8: - case DW_EH_PE_sdata8: - return read64(ctx, buf); - case DW_EH_PE_absptr: - return readUint(ctx, buf); - } - Err(ctx) << "unknown FDE size encoding"; - return 0; -} - -// Returns the VA to which a given FDE (on a mmap'ed buffer) is applied to. -// We need it to create .eh_frame_hdr section. -uint64_t EhFrameSection::getFdePc(uint8_t *buf, size_t fdeOff, - uint8_t enc) const { - // The starting address to which this FDE applies is - // stored at FDE + 8 byte. And this offset is within - // the .eh_frame section. - size_t off = fdeOff + 8; - uint64_t addr = readFdeAddr(ctx, buf + off, enc & 0xf); - if ((enc & 0x70) == DW_EH_PE_absptr) - return ctx.arg.is64 ? addr : uint32_t(addr); - if ((enc & 0x70) == DW_EH_PE_pcrel) - return addr + getParent()->addr + off + outSecOff; - Err(ctx) << "unknown FDE size relative encoding"; - return 0; -} - void EhFrameSection::writeTo(uint8_t *buf) { // Write CIE and FDE records. for (CieRecord *rec : cieRecords) { @@ -602,53 +565,31 @@ void EhFrameSection::writeTo(uint8_t *buf) { if (!hdr || !hdr->getParent()) return; - // Write the .eh_frame_hdr section, which contains a binary search table of - // pointers to FDEs. This must be written after .eh_frame relocation since - // the content depends on relocated initial_location fields in FDEs. - using FdeData = EhFrameSection::FdeData; - SmallVector fdes; - uint64_t va = hdr->getVA(); - for (CieRecord *rec : cieRecords) { - uint8_t enc = getFdeEncoding(rec->cie); - for (EhSectionPiece *fde : rec->fdes) { - uint64_t pc = getFdePc(buf, fde->outputOff, enc); - uint64_t fdeVA = getParent()->addr + fde->outputOff; - if (!isInt<32>(pc - va)) { - Err(ctx) << fde->sec << ": PC offset is too large: 0x" - << Twine::utohexstr(pc - va); - continue; - } - fdes.push_back({uint32_t(pc - va), uint32_t(fdeVA - va)}); - } - } - - // Sort the FDE list by their PC and uniqueify. Usually there is only - // one FDE for a PC (i.e. function), but if ICF merges two functions - // into one, there can be more than one FDEs pointing to the address. - llvm::stable_sort(fdes, [](const FdeData &a, const FdeData &b) { - return a.pcRel < b.pcRel; - }); - fdes.erase( - llvm::unique(fdes, [](auto &a, auto &b) { return a.pcRel == b.pcRel; }), - fdes.end()); + // Write the .eh_frame_hdr section using cached FDE data from updateAllocSize. + bool large = hdr->large; + int64_t ehFramePtr = getParent()->addr - hdr->getVA() - 4; + auto writeField = [&](uint8_t *buf, uint64_t val) { + large ? write64(ctx, buf, val) : write32(ctx, buf, val); + }; - // Write header. uint8_t *hdrBuf = ctx.bufferStart + hdr->getParent()->offset + hdr->outSecOff; - hdrBuf[0] = 1; // version - hdrBuf[1] = DW_EH_PE_pcrel | DW_EH_PE_sdata4; // eh_frame_ptr_enc - hdrBuf[2] = DW_EH_PE_udata4; // fde_count_enc - hdrBuf[3] = DW_EH_PE_datarel | DW_EH_PE_sdata4; // table_enc - write32(ctx, hdrBuf + 4, - getParent()->addr - hdr->getVA() - 4); // eh_frame_ptr - write32(ctx, hdrBuf + 8, fdes.size()); // fde_count - hdrBuf += 12; - - // Write binary search table. Each entry describes the starting PC and the FDE - // address. - for (FdeData &fde : fdes) { - write32(ctx, hdrBuf, fde.pcRel); - write32(ctx, hdrBuf + 4, fde.fdeVARel); - hdrBuf += 8; + // version + hdrBuf[0] = 1; + // eh_frame_ptr_enc + hdrBuf[1] = DW_EH_PE_pcrel | (large ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4); + // fde_count_enc + hdrBuf[2] = DW_EH_PE_udata4; + // table_enc + hdrBuf[3] = DW_EH_PE_datarel | (large ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4); + hdrBuf += 4; + writeField(hdrBuf, ehFramePtr); + hdrBuf += large ? 8 : 4; + write32(ctx, hdrBuf, hdr->fdes.size()); + hdrBuf += 4; + for (const FdeData &fde : hdr->fdes) { + writeField(hdrBuf, fde.pcRel); + writeField(hdrBuf + (large ? 8 : 4), fde.fdeVARel); + hdrBuf += large ? 16 : 8; } } @@ -659,15 +600,71 @@ void EhFrameHeader::writeTo(uint8_t *buf) { // The section content is written during EhFrameSection::writeTo. } -size_t EhFrameHeader::getSize() const { - // .eh_frame_hdr has a 12 bytes header followed by an array of FDEs. - return 12 + getPartition(ctx).ehFrame->numFdes * 8; -} - bool EhFrameHeader::isNeeded() const { return isLive() && getPartition(ctx).ehFrame->isNeeded(); } +void EhFrameHeader::finalizeContents() { + // Compute size: 4-byte header + eh_frame_ptr + fde_count + FDE table. + // Initially `large` is false; updateAllocSize may set it to true if addresses + // exceed the 32-bit range, then call finalizeContents again. + auto numFdes = getPartition(ctx).ehFrame->numFdes; + size = 4 + (large ? 8 : 4) + 4 + numFdes * (large ? 16 : 8); +} + +bool EhFrameHeader::updateAllocSize(Ctx &ctx) { + // This is called after `finalizeSynthetic`, so in the typical case without + // .relr.dyn, this function will not change the size and assignAddresses + // will not need another iteration. + EhFrameSection *ehFrame = getPartition(ctx).ehFrame.get(); + uint64_t hdrVA = getVA(); + int64_t ehFramePtr = ehFrame->getParent()->addr - hdrVA - 4; + // Determine if 64-bit encodings are needed. + bool newLarge = !isInt<32>(ehFramePtr); + + // Collect FDE entries. For each FDE, compute pcRel and fdeVARel relative to + // .eh_frame_hdr's VA. + fdes.clear(); + for (CieRecord *rec : ehFrame->getCieRecords()) { + uint8_t enc = getFdeEncoding(rec->cie); + if ((enc & 0x70) != DW_EH_PE_absptr && (enc & 0x70) != DW_EH_PE_pcrel) { + Err(ctx) << "unknown FDE size encoding"; + continue; + } + for (EhSectionPiece *fde : rec->fdes) { + // The FDE has passed `isFdeLive`, so the first relocation's symbol is a + // live Defined. + auto *isec = cast(fde->sec); + auto &reloc = isec->rels[fde->firstRelocation]; + assert(isa(reloc.sym) && "isFdeLive should have checked this"); + int64_t pcRel = reloc.sym->getVA(ctx) + reloc.addend - hdrVA; + int64_t fdeVARel = ehFrame->getParent()->addr + fde->outputOff - hdrVA; + fdes.push_back({pcRel, fdeVARel}); + newLarge |= !isInt<32>(pcRel) || !isInt<32>(fdeVARel); + } + } + + // Sort the FDE list by their PC and uniquify. Usually there is only one FDE + // at an address, but there can be more than one FDEs pointing to the address. + llvm::stable_sort( + fdes, [](const EhFrameSection::FdeData &a, + const EhFrameSection::FdeData &b) { return a.pcRel < b.pcRel; }); + fdes.erase(llvm::unique(fdes, + [](const EhFrameSection::FdeData &a, + const EhFrameSection::FdeData &b) { + return a.pcRel == b.pcRel; + }), + fdes.end()); + ehFrame->numFdes = fdes.size(); + + large = newLarge; + + // Compute size. + size_t oldSize = size; + finalizeContents(); + return size != oldSize; +} + GotSection::GotSection(Ctx &ctx) : SyntheticSection(ctx, ".got", SHT_PROGBITS, SHF_ALLOC | SHF_WRITE, ctx.target->gotEntrySize) { diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h index cad3779ee9675..64f0a477e2c23 100644 --- a/lld/ELF/SyntheticSections.h +++ b/lld/ELF/SyntheticSections.h @@ -64,8 +64,8 @@ class EhFrameSection final : public SyntheticSection { size_t numFdes = 0; struct FdeData { - uint32_t pcRel; - uint32_t fdeVARel; + int64_t pcRel; + int64_t fdeVARel; }; ArrayRef getCieRecords() const { return cieRecords; } @@ -86,8 +86,6 @@ class EhFrameSection final : public SyntheticSection { CieRecord *addCie(EhSectionPiece &piece, ArrayRef rels); Defined *isFdeLive(EhSectionPiece &piece, ArrayRef rels); - uint64_t getFdePc(uint8_t *buf, size_t off, uint8_t enc) const; - SmallVector cieRecords; // CIE records are uniquified by their contents and personality functions. @@ -101,8 +99,16 @@ class EhFrameHeader final : public SyntheticSection { public: EhFrameHeader(Ctx &); void writeTo(uint8_t *buf) override; - size_t getSize() const override; + size_t getSize() const override { return size; } bool isNeeded() const override; + void finalizeContents() override; + bool updateAllocSize(Ctx &) override; + + // Cached FDE data computed by updateAllocSize, used by + // EhFrameSection::writeTo. + SmallVector fdes; + bool large = false; // Whether to use sdata8 encoding. + size_t size = 0; }; class GotSection final : public SyntheticSection { diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index 17d2a77493d19..9220d73559b0b 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -1603,6 +1603,8 @@ template void Writer::finalizeAddressDependentContent() { changed |= part.relrAuthDyn->updateAllocSize(ctx); if (part.memtagGlobalDescriptors) changed |= part.memtagGlobalDescriptors->updateAllocSize(ctx); + if (part.ehFrameHdr && part.ehFrameHdr->isNeeded()) + changed |= part.ehFrameHdr->updateAllocSize(ctx); } std::pair changes = @@ -1627,6 +1629,10 @@ template void Writer::finalizeAddressDependentContent() { // Spilling can change relative section order. finalizeOrderDependentContent(); } + // If updateAllocSize reported errors (e.g. "unknown FDE size encoding" for + // part.ehFrameHdr), break to avoid duplicate diagnostics from the loop. + if (errCount(ctx)) + break; } if (!ctx.arg.relocatable) ctx.target->finalizeRelax(pass); diff --git a/lld/MachO/InputSection.cpp b/lld/MachO/InputSection.cpp index d5499babc3265..34847adc85954 100644 --- a/lld/MachO/InputSection.cpp +++ b/lld/MachO/InputSection.cpp @@ -89,15 +89,25 @@ uint64_t InputSection::getVA(uint64_t off) const { return parent->addr + getOffset(off); } -static uint64_t resolveSymbolVA(const Symbol *sym, uint8_t type) { +static uint64_t resolveSymbolOffsetVA(const Symbol *sym, uint8_t type, + int64_t offset) { const RelocAttrs &relocAttrs = target->getRelocAttrs(type); - if (relocAttrs.hasAttr(RelocAttrBits::BRANCH)) - return sym->resolveBranchVA(); - if (relocAttrs.hasAttr(RelocAttrBits::GOT)) - return sym->resolveGotVA(); - if (relocAttrs.hasAttr(RelocAttrBits::TLV)) - return sym->resolveTlvVA(); - return sym->getVA(); + uint64_t symVA; + if (relocAttrs.hasAttr(RelocAttrBits::BRANCH)) { + // For branch relocations with non-zero offsets, use the actual function + // address rather than the stub address. Branching to an interior point + // of a function (e.g., _func+16) implies reliance on the original + // function's layout, which an interposed replacement wouldn't preserve. + // There's no meaningful way to "interpose" an interior offset. + symVA = (offset != 0) ? sym->getVA() : sym->resolveBranchVA(); + } else if (relocAttrs.hasAttr(RelocAttrBits::GOT)) { + symVA = sym->resolveGotVA(); + } else if (relocAttrs.hasAttr(RelocAttrBits::TLV)) { + symVA = sym->resolveTlvVA(); + } else { + symVA = sym->getVA(); + } + return symVA + offset; } const Defined *InputSection::getContainingSymbol(uint64_t off) const { @@ -243,7 +253,7 @@ void ConcatInputSection::writeTo(uint8_t *buf) { target->handleDtraceReloc(referentSym, r, loc); continue; } - referentVA = resolveSymbolVA(referentSym, r.type) + r.addend; + referentVA = resolveSymbolOffsetVA(referentSym, r.type, r.addend); if (isThreadLocalVariables(getFlags()) && isa(referentSym)) { // References from thread-local variable sections are treated as offsets diff --git a/lld/include/lld/Common/BPSectionOrdererBase.inc b/lld/include/lld/Common/BPSectionOrdererBase.inc index 43de0f722a30e..7d13cd25c0e76 100644 --- a/lld/include/lld/Common/BPSectionOrdererBase.inc +++ b/lld/include/lld/Common/BPSectionOrdererBase.inc @@ -161,7 +161,7 @@ auto BPOrderer::computeOrder( sectionToIdx.try_emplace(isec, i); BPFunctionNode::UtilityNodeT maxUN = 0; - DenseMap startupSectionIdxUNs; + MapVector startupSectionIdxUNs; // Used to define the initial order for startup functions. DenseMap sectionIdxToTimestamp; std::unique_ptr reader; @@ -177,7 +177,7 @@ auto BPOrderer::computeOrder( } auto &traces = reader->getTemporalProfTraces(); - DenseMap sectionIdxToFirstUN; + MapVector sectionIdxToFirstUN; for (size_t traceIdx = 0; traceIdx < traces.size(); traceIdx++) { uint64_t currentSize = 0, cutoffSize = 1; size_t cutoffTimestamp = 1; diff --git a/lld/test/ELF/aarch64-fpic-add_abs_lo12_nc.s b/lld/test/ELF/aarch64-fpic-add_abs_lo12_nc.s index 01095d0b529f9..ee2b0533368b8 100644 --- a/lld/test/ELF/aarch64-fpic-add_abs_lo12_nc.s +++ b/lld/test/ELF/aarch64-fpic-add_abs_lo12_nc.s @@ -1,9 +1,10 @@ // REQUIRES: aarch64 // RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t.o -// RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s -// CHECK: error: relocation R_AARCH64_ADD_ABS_LO12_NC cannot be used against symbol 'dat'; recompile with -fPIC -// CHECK: >>> defined in {{.*}}.o -// CHECK: >>> referenced by {{.*}}.o:(.text+0x0) +// RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error: + +// CHECK: error: relocation R_AARCH64_ADD_ABS_LO12_NC cannot be used against symbol 'dat'; recompile with -fPIC +// CHECK-NEXT: >>> defined in {{.*}}.o +// CHECK-NEXT: >>> referenced by {{.*}}.o:(.text+0x0) add x0, x0, :lo12:dat .data diff --git a/lld/test/ELF/abs-conflict.s b/lld/test/ELF/abs-conflict.s deleted file mode 100644 index 4c6a62e96b637..0000000000000 --- a/lld/test/ELF/abs-conflict.s +++ /dev/null @@ -1,18 +0,0 @@ -// REQUIRES: x86 -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -// RUN: ld.lld %t.o %t.o -o %t.so -shared -// RUN: llvm-readobj --dyn-symbols %t.so | FileCheck %s - -// CHECK: Name: foo -// CHECK-NEXT: Value: 0x123 - -.global foo -foo = 0x123 - -// RUN: echo ".global foo; foo = 0x124" > %t2.s -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %t2.s -o %t2.o -// RUN: not ld.lld %t.o %t2.o -o /dev/null -shared 2>&1 | FileCheck --check-prefix=DUP %s - -// DUP: duplicate symbol: foo -// DUP-NEXT: >>> defined in {{.*}}.o -// DUP-NEXT: >>> defined in {{.*}}2.o diff --git a/lld/test/ELF/conflict-abs.s b/lld/test/ELF/conflict-abs.s new file mode 100644 index 0000000000000..033ed046abe18 --- /dev/null +++ b/lld/test/ELF/conflict-abs.s @@ -0,0 +1,18 @@ +// REQUIRES: x86 +// RUN: rm -rf %t && mkdir %t && cd %t +// RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o a.o +// RUN: ld.lld a.o a.o -o a.so -shared +// RUN: llvm-readobj --dyn-symbols a.so | FileCheck %s + +// CHECK: Name: foo +// CHECK-NEXT: Value: 0x123 + +.global foo +foo = 0x123 + +// RUN: echo ".global foo; foo = 0x124" | llvm-mc -filetype=obj -triple=x86_64 - -o b.o +// RUN: not ld.lld a.o b.o -shared 2>&1 | FileCheck --check-prefix=DUP %s --implicit-check-not=error: + +// DUP: error: duplicate symbol: foo +// DUP-NEXT: >>> defined in {{.*}} +// DUP-NEXT: >>> defined in {{.*}} diff --git a/lld/test/ELF/conflict.s b/lld/test/ELF/conflict.s index 66a7f3912dbea..b492508f7cda4 100644 --- a/lld/test/ELF/conflict.s +++ b/lld/test/ELF/conflict.s @@ -1,43 +1,44 @@ # REQUIRES: x86 +# RUN: rm -rf %t && mkdir %t && cd %t -# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1.o -# RUN: not ld.lld %t1.o %t1.o -o /dev/null 2>&1 | FileCheck -check-prefix=DEMANGLE %s +# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o a.o +# RUN: not ld.lld a.o a.o 2>&1 | FileCheck --check-prefix=DEMANGLE %s --implicit-check-not=error: -# DEMANGLE: duplicate symbol: mul(double, double) -# DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) -# DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) -# DEMANGLE: duplicate symbol: foo -# DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) -# DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) +# DEMANGLE: error: duplicate symbol: mul(double, double) +# DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) +# DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) +# DEMANGLE: error: duplicate symbol: foo +# DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) +# DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) -# RUN: not ld.lld %t1.o %t1.o -o /dev/null --no-demangle 2>&1 | \ -# RUN: FileCheck -check-prefix=NO_DEMANGLE %s +# RUN: not ld.lld a.o a.o --no-demangle 2>&1 | FileCheck --check-prefix=NO_DEMANGLE %s --implicit-check-not=error: -# NO_DEMANGLE: duplicate symbol: _Z3muldd +# NO_DEMANGLE: error: duplicate symbol: _Z3muldd # NO_DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) # NO_DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) -# NO_DEMANGLE: duplicate symbol: foo +# NO_DEMANGLE: error: duplicate symbol: foo # NO_DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) # NO_DEMANGLE-NEXT: >>> defined at {{.*}}:(.text+0x0) -# RUN: not ld.lld %t1.o %t1.o -o /dev/null --demangle --no-demangle 2>&1 | \ -# RUN: FileCheck -check-prefix=NO_DEMANGLE %s -# RUN: not ld.lld %t1.o %t1.o -o /dev/null --no-demangle --demangle 2>&1 | \ -# RUN: FileCheck -check-prefix=DEMANGLE %s +# RUN: not ld.lld a.o a.o --demangle --no-demangle 2>&1 | FileCheck --check-prefix=NO_DEMANGLE %s --implicit-check-not=error: +# RUN: not ld.lld a.o a.o --no-demangle --demangle 2>&1 | FileCheck --check-prefix=DEMANGLE %s --implicit-check-not=error: -# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %S/Inputs/conflict.s -o %t2.o -# RUN: rm -f %t3.a -# RUN: llvm-ar rcs %t3.a %t2.o -# RUN: not ld.lld %t1.o %t3.a -u baz -o /dev/null 2>&1 | FileCheck -check-prefix=ARCHIVE %s +# RUN: llvm-mc -filetype=obj -triple=x86_64 %S/Inputs/conflict.s -o b.o +# RUN: rm -f b.a +# RUN: llvm-ar rcs b.a b.o +# RUN: not ld.lld a.o b.a -u baz 2>&1 | FileCheck --check-prefix=ARCHIVE %s --implicit-check-not=error: -# ARCHIVE: duplicate symbol: foo +# ARCHIVE: error: duplicate symbol: mul(double, double) +# ARCHIVE-NEXT: >>> defined at {{.*}}:(.text+0x0) +# ARCHIVE-NEXT: >>> defined at {{.*}}:(.text+0x0) in archive {{.*}}.a +# ARCHIVE: error: duplicate symbol: foo # ARCHIVE-NEXT: >>> defined at {{.*}}:(.text+0x0) # ARCHIVE-NEXT: >>> defined at {{.*}}:(.text+0x0) in archive {{.*}}.a -# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %p/Inputs/conflict-debug.s -o %t-dbg.o -# RUN: not ld.lld %t-dbg.o %t-dbg.o -o /dev/null 2>&1 | FileCheck -check-prefix=DBGINFO %s +# RUN: llvm-mc -filetype=obj -triple=x86_64 %S/Inputs/conflict-debug.s -o dbg.o +# RUN: not ld.lld dbg.o dbg.o 2>&1 | FileCheck --check-prefix=DBGINFO %s --implicit-check-not=error: -# DBGINFO: duplicate symbol: zed +# DBGINFO: error: duplicate symbol: zed # DBGINFO-NEXT: >>> defined at conflict-debug.s:4 # DBGINFO-NEXT: >>> {{.*}}:(.text+0x0) # DBGINFO-NEXT: >>> defined at conflict-debug.s:4 diff --git a/lld/test/ELF/eh-frame-dyn-rel.s b/lld/test/ELF/eh-frame-dyn-rel.s index 04828e7b28b40..57d85660dfa42 100644 --- a/lld/test/ELF/eh-frame-dyn-rel.s +++ b/lld/test/ELF/eh-frame-dyn-rel.s @@ -1,10 +1,10 @@ // REQUIRES: x86 -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -// RUN: not ld.lld %t.o %t.o -o /dev/null -shared 2>&1 | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o +// RUN: not ld.lld %t.o %t.o -o /dev/null -shared 2>&1 | FileCheck %s --implicit-check-not=error: -// CHECK: error: relocation R_X86_64_64 cannot be used against symbol 'foo'; recompile with -fPIC -// CHECK: >>> defined in {{.*}}.o -// CHECK: >>> referenced by {{.*}}.o:(.eh_frame+0x12) +// CHECK: error: relocation R_X86_64_64 cannot be used against symbol 'foo'; recompile with -fPIC +// CHECK-NEXT: >>> defined in {{.*}}.o +// CHECK-NEXT: >>> referenced by {{.*}}.o:(.eh_frame+0x12) .section bar,"axG",@progbits,foo,comdat .cfi_startproc diff --git a/lld/test/ELF/eh-frame-fde-encoding.s b/lld/test/ELF/eh-frame-fde-encoding.s new file mode 100644 index 0000000000000..0a7943c8b2077 --- /dev/null +++ b/lld/test/ELF/eh-frame-fde-encoding.s @@ -0,0 +1,203 @@ +# REQUIRES: x86 +## Test that various DW_EH_PE_* encodings in CIE are accepted. + +# RUN: rm -rf %t && split-file %s %t && cd %t +# RUN: llvm-mc -filetype=obj -triple=x86_64 absptr.s -o absptr.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 sdata2.s -o sdata2.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 sdata4.s -o sdata4.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 sdata8.s -o sdata8.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 signed.s -o signed.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 udata2.s -o udata2.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 udata4.s -o udata4.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 udata8.s -o udata8.o + +# RUN: ld.lld --eh-frame-hdr sdata2.o -o /dev/null +# RUN: ld.lld --eh-frame-hdr sdata8.o -o /dev/null +# RUN: ld.lld --eh-frame-hdr signed.o -o /dev/null + +# RUN: ld.lld --eh-frame-hdr --image-base=0 -Ttext=0x1000 absptr.o -o absptr +# RUN: ld.lld --eh-frame-hdr --image-base=0 -Ttext=0x1000 udata2.o -o udata2 +# RUN: ld.lld --eh-frame-hdr --image-base=0 -Ttext=0x2000 sdata4.o -o sdata4 +# RUN: ld.lld --eh-frame-hdr --image-base=0 -Ttext=0x2000 udata4.o -o udata4 + +## absptr/udata2: Also verify .eh_frame content to test relocation with addend. +## .eh_frame_hdr initial_location: foo(0x1000)+0x234 - .eh_frame_hdr(0x2004) = 0xfffff230 +# RUN: llvm-readobj -x .eh_frame_hdr -x .eh_frame absptr | FileCheck %s --check-prefix=ABSPTR +# ABSPTR: Hex dump of section '.eh_frame_hdr': +# ABSPTR-NEXT: 0x00002004 011b033b 10000000 01000000 30f2ffff +# ABSPTR-NEXT: 0x00002014 24000000 +# ABSPTR: Hex dump of section '.eh_frame': +# ABSPTR-NEXT: 0x00002018 0c000000 00000000 01520001 010100ff +# ABSPTR-NEXT: 0x00002028 0c000000 14000000 34120000 00000000 +## CIE offset--^ ^-- PC begin = 0x1234 (foo + 0x234) + +# RUN: llvm-readobj -x .eh_frame_hdr -x .eh_frame udata2 | FileCheck %s --check-prefix=UDATA2 +# UDATA2: Hex dump of section '.eh_frame_hdr': +# UDATA2-NEXT: 0x00002004 011b033b 10000000 01000000 30f2ffff +# UDATA2-NEXT: 0x00002014 26000000 +# UDATA2: Hex dump of section '.eh_frame': +# UDATA2-NEXT: 0x00002018 0e000000 00000000 01525300 01010102 +# UDATA2-NEXT: 0x00002028 ff000600 00001600 00003412 +## CIE offset--^ ^-- PC begin = 0x1234 (foo + 0x234) + +# RUN: llvm-readelf -x .eh_frame_hdr sdata4 udata4 | FileCheck %s --check-prefix=HDR4 +# HDR4: 0x00003004 011b033b 10000000 01000000 fcefffff +# HDR4-NEXT: 0x00003014 24000000 +# HDR4: 0x00003004 011b033b 10000000 01000000 fcefffff +# HDR4-NEXT: 0x00003014 24000000 + +#--- absptr.s +## DW_EH_PE_absptr (0x00) with FDE for verification +.text +.globl foo +foo: + nop + +.section .eh_frame,"a",@unwind + .long 12 # Size + .long 0x00 # ID (CIE) + .byte 0x01 # Version + .byte 0x52 # Augmentation string: 'R','\0' + .byte 0x00 + .byte 0x01 # Code alignment + .byte 0x01 # Data alignment + .byte 0x01 # Return address register + .byte 0x00 # DW_EH_PE_absptr + .byte 0xFF + + .long 12 # Size + .long 0x14 # CIE offset + .quad foo + 0x234 # PC begin + +#--- sdata2.s +## DW_EH_PE_sdata2 (0x0A) +.section .eh_frame,"a",@unwind + .long 0x0E # Size + .long 0x00 # ID (CIE) + .byte 0x01 # Version + .byte 0x50 # Augmentation string: 'P','\0' + .byte 0x00 + .byte 0x01 # Code alignment + .byte 0x01 # Data alignment (LEB128) + .byte 0x01 # Return address register (LEB128) + .byte 0x0A # DW_EH_PE_sdata2 + .short 0xFFFF + .byte 0xFF + +#--- sdata4.s +## DW_EH_PE_sdata4 (0x0B) with FDE for verification +.text +.globl foo +foo: + nop + +.section .eh_frame,"a",@unwind + .long 12 # Size + .long 0x00 # ID (CIE) + .byte 0x01 # Version + .byte 0x52 # Augmentation string: 'R','\0' + .byte 0x00 + .byte 0x01 # Code alignment + .byte 0x01 # Data alignment + .byte 0x01 # Return address register + .byte 0x0B # DW_EH_PE_sdata4 + .byte 0xFF + + .long 12 # Size + .long 0x14 # CIE offset + .long foo # PC begin + .long 1 # PC range + +#--- sdata8.s +## DW_EH_PE_sdata8 (0x0C) +.section .eh_frame,"a",@unwind + .long 0x14 # Size + .long 0x00 # ID (CIE) + .byte 0x01 # Version + .byte 0x50 # Augmentation string: 'P','\0' + .byte 0x00 + .byte 0x01 # Code alignment + .byte 0x01 # Data alignment (LEB128) + .byte 0x01 # Return address register (LEB128) + .byte 0x0C # DW_EH_PE_sdata8 + .quad 0xFFFFFFFFFFFFFFFF + .byte 0xFF + +#--- signed.s +## DW_EH_PE_signed (0x08) +.section .eh_frame,"a",@unwind + .long 0x14 # Size + .long 0x00 # ID (CIE) + .byte 0x01 # Version + .byte 0x50 # Augmentation string: 'P','\0' + .byte 0x00 + .byte 0x01 # Code alignment + .byte 0x01 # Data alignment (LEB128) + .byte 0x01 # Return address register (LEB128) + .byte 0x08 # DW_EH_PE_signed + .quad 0xFFFFFFFFFFFFFFFF + .byte 0xFF + +#--- udata2.s +## DW_EH_PE_udata2 (0x02) with FDE for verification +.text +.globl foo +foo: + nop + +.section .eh_frame,"a",@unwind + .long 14 # Size + .long 0x00 # ID (CIE) + .byte 0x01 # Version + .byte 0x52 # Augmentation string: 'R','S','\0' + .byte 0x53 + .byte 0x00 + .byte 0x01 # Code alignment + .byte 0x01 # Data alignment + .byte 0x01 # Return address register + .byte 0x02 # DW_EH_PE_udata2 + .byte 0xFF + .byte 0x00 + + .long 6 # Size + .long 0x16 # CIE offset + .short foo + 0x234 # PC begin + +#--- udata4.s +## DW_EH_PE_udata4 (0x03) with FDE for verification +.text +.globl foo +foo: + nop + +.section .eh_frame,"a",@unwind + .long 12 # Size + .long 0x00 # ID (CIE) + .byte 0x01 # Version + .byte 0x52 # Augmentation string: 'R','\0' + .byte 0x00 + .byte 0x01 # Code alignment + .byte 0x01 # Data alignment + .byte 0x01 # Return address register + .byte 0x03 # DW_EH_PE_udata4 + .byte 0xFF + + .long 12 # Size + .long 0x14 # CIE offset + .long foo # PC begin + .long 1 # PC range + +#--- udata8.s +## DW_EH_PE_udata8 (0x04) +.section .eh_frame,"a",@unwind + .long 0x14 # Size + .long 0x00 # ID (CIE) + .byte 0x01 # Version + .byte 0x50 # Augmentation string: 'P','\0' + .byte 0x00 + .byte 0x01 # Code alignment + .byte 0x01 # Data alignment (LEB128) + .byte 0x01 # Return address register (LEB128) + .byte 0x04 # DW_EH_PE_udata8 + .quad 0xFFFFFFFFFFFFFFFF + .byte 0xFF diff --git a/lld/test/ELF/eh-frame-hdr-sdata8.s b/lld/test/ELF/eh-frame-hdr-sdata8.s new file mode 100644 index 0000000000000..f249e2418282c --- /dev/null +++ b/lld/test/ELF/eh-frame-hdr-sdata8.s @@ -0,0 +1,110 @@ +# REQUIRES: x86 + +## Test that .eh_frame_hdr uses DW_EH_PE_sdata8 instead of DW_EH_PE_sdata4 when +## eh_frame_ptr or a table entry exceeds the 32-bit range. + +# RUN: rm -rf %t && split-file %s %t && cd %t +# RUN: llvm-mc -filetype=obj -triple=x86_64 a.s --large-code-model -o a.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 bad.s -o bad.o + +## Case 1: .text at high address - pcRel exceeds 32-bit range. +# RUN: ld.lld --eh-frame-hdr -T 1.lds a.o -o out1 +# RUN: llvm-objdump -s -j .eh_frame_hdr out1 | FileCheck %s --check-prefix=CHECK1 + +## Case 2: .eh_frame at high address - eh_frame_ptr exceeds 32-bit range. +# RUN: ld.lld --eh-frame-hdr -T 2.lds a.o -o out2 +# RUN: llvm-objdump -s -j .eh_frame_hdr out2 | FileCheck %s --check-prefix=CHECK2 + +## Case 3: .eh_frame_hdr and .relr.dyn sizes are coupled, requiring multiple iterations +## to stabilize. +# RUN: ld.lld -pie --eh-frame-hdr -z pack-relative-relocs -T 3.lds a.o -o out3 +# RUN: llvm-objdump -s -j .eh_frame_hdr out3 | FileCheck %s --check-prefix=CHECK3 + +## Header: version=1, eh_frame_ptr_enc=0x1C (pcrel|sdata8), +## fde_count_enc=0x03 (udata4), table_enc=0x3C (datarel|sdata8) +## Layout: header (4) + eh_frame_ptr (8) + fde_count (4) + table entries (16 each) +## Each table entry: pcRel (8) + fdeVARel (8), relative to .eh_frame_hdr address +# CHECK1: section .eh_frame_hdr: +# CHECK1-NEXT: 011c033c 2c000000 00000000 02000000 +# CHECK1-NEXT: 00100000 01000000 48000000 00000000 +# CHECK1-NEXT: 01100000 01000000 68000000 00000000 +# CHECK1-EMPTY: +# CHECK2: section .eh_frame_hdr: +# CHECK2-NEXT: 011c033c f80f0000 01000000 02000000 +# CHECK2-NEXT: fcffffff ffffffff 14100000 01000000 +# CHECK2-NEXT: fdffffff ffffffff 34100000 01000000 +# CHECK2-EMPTY: +# CHECK3: 011c033c 2c000000 00000000 02000000 +# CHECK3-NEXT: 00800000 01000000 48000000 00000000 + +## A corrupted .eh_frame reports exactly one error (not duplicated by the loop). +# RUN: not ld.lld --eh-frame-hdr -T 1.lds a.o bad.o 2>&1 | FileCheck %s --check-prefix=ERR --implicit-check-not=error: +# ERR: error: corrupted .eh_frame: unexpected end of CIE + +#--- a.s +.text +.global _start +_start: + .cfi_startproc + nop + .cfi_endproc + .cfi_startproc + nop + .cfi_endproc + +.data +.balign 8 +## Two adjacent relocations use 2 RELR entries (1 address + 1 bitmap). +.dc.a __ehdr_start +.dc.a __ehdr_start + +.section .data.1,"aw" +.balign 8 +## A RELR bitmap entry can encode up to 63 relocations with word-sized stride. +## If .data.1 is >= 63*8 bytes from end(.data), this relocation cannot reuse +## the previous bitmap entry, requiring a third RELR entry. +.dc.a __ehdr_start + +#--- 1.lds +SECTIONS { + . = 0x1000; + .eh_frame_hdr : {} + .eh_frame : {} + .text 0x100002000 : {} +} + +#--- 2.lds +SECTIONS { + . = 0x1000; + .text : {} + .eh_frame_hdr : {} + .eh_frame 0x100002000 : {} +} + +#--- 3.lds +SECTIONS { + ## Test that .eh_frame_hdr and .relr.dyn sizes are coupled, requiring + ## multiple finalizeAddressDependentContent iterations to converge. + ## + ## The padding before .data.1 is set so that switching .eh_frame_hdr from + ## sdata4 (18 bytes) to sdata8 (48 bytes) pushes .data.1 past the 63*8-byte + ## RELR bitmap threshold, growing .relr.dyn from 16 to 24 bytes. + ## The .text address depends on SIZEOF(.relr.dyn), creating the coupling. + .eh_frame_hdr : {} + .eh_frame : {} + .relr.dyn : {} + .data : { *(.data) . += 63*8-40 + SIZEOF(.eh_frame_hdr); *(.data.*) } + . = SIZEOF(.relr.dyn) > 16 ? 0x100008000 : 0x3000; + .text : {} + ASSERT(SIZEOF(.relr.dyn) > 16, ".relr.dyn size should increase from 16 to 24") +} + +#--- bad.s +## Malformed CIE: length says 8 bytes but content is truncated. +.section .eh_frame,"a",@unwind + .long 8 # length + .long 0 # CIE id + .byte 1 # version + .byte 0 # augmentation string (empty) + ## Missing: code/data alignment, return column, etc. + .space 2 diff --git a/lld/test/ELF/eh-frame-invalid-cie.s b/lld/test/ELF/eh-frame-invalid-cie.s new file mode 100644 index 0000000000000..0a40a1121a9db --- /dev/null +++ b/lld/test/ELF/eh-frame-invalid-cie.s @@ -0,0 +1,77 @@ +# REQUIRES: x86 +## Test CIE structure errors in .eh_frame. + +# RUN: rm -rf %t && split-file %s %t && cd %t +# RUN: llvm-mc -filetype=obj -triple=x86_64 too-small.s -o too-small.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 unexpected-end.s -o unexpected-end.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 failed-string.s -o failed-string.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 failed-leb128.s -o failed-leb128.o + +# RUN: not ld.lld --eh-frame-hdr too-small.o 2>&1 | FileCheck %s --check-prefix=TOO-SMALL --implicit-check-not=error: +# RUN: not ld.lld --eh-frame-hdr unexpected-end.o 2>&1 | FileCheck %s --check-prefix=UNEXPECTED-END +# RUN: not ld.lld --eh-frame-hdr failed-string.o 2>&1 | FileCheck %s --check-prefix=FAILED-STRING --implicit-check-not=error: +# RUN: not ld.lld --eh-frame-hdr failed-leb128.o 2>&1 | FileCheck %s --check-prefix=FAILED-LEB128 + +# TOO-SMALL: error: corrupted .eh_frame: CIE is too small +# TOO-SMALL-NEXT: >>> defined in too-small.o:(.eh_frame+0x0) + +# UNEXPECTED-END: error: corrupted .eh_frame: unexpected end of CIE +# UNEXPECTED-END-NEXT: >>> defined in unexpected-end.o:(.eh_frame+0x8) + +# FAILED-STRING: error: corrupted .eh_frame: corrupted CIE (failed to read string) +# FAILED-STRING-NEXT: >>> defined in failed-string.o:(.eh_frame+0x9) + +# FAILED-LEB128: error: corrupted .eh_frame: corrupted CIE (failed to read LEB128) +# FAILED-LEB128-NEXT: >>> defined in failed-leb128.o:(.eh_frame+0xc) + +#--- too-small.s +.section .eh_frame,"a",@unwind + .byte 0x03 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + +#--- unexpected-end.s +.section .eh_frame,"a",@unwind + .byte 0x04 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + +#--- failed-string.s +.section .eh_frame,"a",@unwind +.align 1 + .byte 0x08 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x01 + .byte 0x01 + .byte 0x01 + .byte 0x01 + +#--- failed-leb128.s +.section .eh_frame,"a",@unwind + .byte 0x08 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x01 + .byte 0x01 + .byte 0x00 + .byte 0x01 diff --git a/lld/test/ELF/eh-frame-invalid-fde-encoding.s b/lld/test/ELF/eh-frame-invalid-fde-encoding.s new file mode 100644 index 0000000000000..9a463f95b5568 --- /dev/null +++ b/lld/test/ELF/eh-frame-invalid-fde-encoding.s @@ -0,0 +1,150 @@ +# REQUIRES: x86 +## Test EhReader::getFdeEncoding errors in .eh_frame. + +# RUN: rm -rf %t && split-file %s %t && cd %t +# RUN: llvm-mc -filetype=obj -triple=x86_64 unknown-aug.s -o unknown-aug.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 corrupted.s -o corrupted.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 unknown-fde-encoding.s -o unknown-fde-encoding.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 aligned-encoding.s -o aligned-encoding.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 unknown-size-encoding.s -o unknown-size-encoding.o + +# RUN: not ld.lld --eh-frame-hdr unknown-aug.o 2>&1 | FileCheck %s --check-prefix=UNKNOWN-AUG -DPREFIX=error --implicit-check-not=error: +# RUN: ld.lld --eh-frame-hdr unknown-aug.o --noinhibit-exec 2>&1 | FileCheck %s --check-prefix=UNKNOWN-AUG -DPREFIX=warning +# RUN: not ld.lld --eh-frame-hdr corrupted.o 2>&1 | FileCheck %s --check-prefix=CORRUPTED --implicit-check-not=error: +# RUN: not ld.lld --eh-frame-hdr unknown-fde-encoding.o 2>&1 | FileCheck %s --check-prefix=UNKNOWN-FDE --implicit-check-not=error: +# RUN: ld.lld --eh-frame-hdr unknown-fde-encoding.o --noinhibit-exec +# RUN: not ld.lld --eh-frame-hdr aligned-encoding.o 2>&1 | FileCheck %s --check-prefix=ALIGNED --implicit-check-not=error: +# RUN: not ld.lld --eh-frame-hdr unknown-size-encoding.o 2>&1 | FileCheck %s --check-prefix=UNKNOWN-SIZE --implicit-check-not=error: + +# UNKNOWN-AUG: [[PREFIX]]: corrupted .eh_frame: unknown .eh_frame augmentation string: {{.+}} + +# CORRUPTED: error: corrupted .eh_frame: corrupted CIE + +# UNKNOWN-FDE: error: corrupted .eh_frame: unknown FDE encoding +# UNKNOWN-FDE-NEXT: >>> defined in unknown-fde-encoding.o:(.eh_frame+0xe) + +# ALIGNED: error: corrupted .eh_frame: DW_EH_PE_aligned encoding is not supported + +# UNKNOWN-SIZE: error: unknown FDE size encoding + +#--- unknown-aug.s +.section .eh_frame,"a",@unwind + .byte 0x0E + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x01 + .byte 0x01 + .byte 0x00 + .byte 0x01 + + .byte 0x01 # LEB128 + .byte 0x01 # LEB128 + + .byte 0x01 + .byte 0x01 + .byte 0x01 + .byte 0x01 + +#--- corrupted.s +.section .eh_frame,"a",@unwind + .byte 0x0E + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x01 + + .byte 0x50 # Augmentation string: 'P','\0' + .byte 0x00 + + .byte 0x01 + + .byte 0x01 # LEB128 + .byte 0x01 # LEB128 + + .byte 0x03 + .byte 0x01 + .byte 0x01 + .byte 0x01 + +#--- unknown-fde-encoding.s +.section .eh_frame,"a",@unwind + .byte 0x0E + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x01 + + .byte 0x50 # Augmentation string: 'P','\0' + .byte 0x00 + + .byte 0x01 + + .byte 0x01 # LEB128 + .byte 0x01 # LEB128 + + .byte 0x01 + .byte 0x01 + .byte 0x01 + .byte 0x01 + +#--- aligned-encoding.s +.section .eh_frame,"a",@unwind + .byte 0x0E + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x00 + .byte 0x01 + + .byte 0x50 # Augmentation string: 'P','\0' + .byte 0x00 + + .byte 0x01 + + .byte 0x01 # LEB128 + .byte 0x01 # LEB128 + + .byte 0x51 + .byte 0x01 + .byte 0x01 + .byte 0x01 + +#--- unknown-size-encoding.s +.section .eh_frame,"a",@unwind + .long 12 # Size + .long 0x00 # ID + .byte 0x01 # Version. + + .byte 0x52 # Augmentation string: 'R','\0' + .byte 0x00 + +# Code and data alignment factors. + .byte 0x01 # LEB128 + .byte 0x01 # LEB128 + +# Return address register. + .byte 0x01 # LEB128 + + .byte 0xFE # 'R' value: invalid <0xFE> + + .byte 0xFF + + .long 12 # Size + .long 0x14 # ID + .quad .eh_frame diff --git a/lld/test/ELF/eh-frame-pcrel-overflow.s b/lld/test/ELF/eh-frame-pcrel-overflow.s deleted file mode 100644 index 3dfcf9ee1a7f9..0000000000000 --- a/lld/test/ELF/eh-frame-pcrel-overflow.s +++ /dev/null @@ -1,35 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/eh-frame-pcrel-overflow.s -o %t1.o -# RUN: ld.lld --eh-frame-hdr -Ttext=0x90000000 %t.o -o /dev/null -# RUN: not ld.lld --eh-frame-hdr %t.o %t1.o -o /dev/null 2>&1 | FileCheck %s -# RUN: ld.lld --eh-frame-hdr %t.o %t1.o -o /dev/null --noinhibit-exec 2>&1 | FileCheck %s --check-prefix=WARN -# CHECK: error: {{.*}}.o:(.eh_frame): PC offset is too large: 0x90001054 -# WARN: warning: {{.*}}.o:(.eh_frame): PC offset is too large: 0x90001054 - -.text -.global _start -_start: - ret - -.section .eh_frame,"a",@unwind - .long 12 # Size - .long 0x00 # ID - .byte 0x01 # Version. - - .byte 0x52 # Augmentation string: 'R','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x00 # DW_EH_PE_absptr - - .byte 0xFF - - .long 12 # Size - .long 0x14 # ID - .quad _start + 0x70000000 diff --git a/lld/test/ELF/eh-frame-value-format1.s b/lld/test/ELF/eh-frame-value-format1.s deleted file mode 100644 index da078eb79b425..0000000000000 --- a/lld/test/ELF/eh-frame-value-format1.s +++ /dev/null @@ -1,35 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null - -.section .eh_frame,"a",@unwind - .byte 0x14 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x04 # DW_EH_PE_udata8 - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - - .byte 0xFF diff --git a/lld/test/ELF/eh-frame-value-format2.s b/lld/test/ELF/eh-frame-value-format2.s deleted file mode 100644 index 1c907501ead31..0000000000000 --- a/lld/test/ELF/eh-frame-value-format2.s +++ /dev/null @@ -1,35 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null - -.section .eh_frame,"a",@unwind - .byte 0x14 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x0C # DW_EH_PE_sdata8 - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - - .byte 0xFF diff --git a/lld/test/ELF/eh-frame-value-format3.s b/lld/test/ELF/eh-frame-value-format3.s deleted file mode 100644 index 46e8db90ec18e..0000000000000 --- a/lld/test/ELF/eh-frame-value-format3.s +++ /dev/null @@ -1,28 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null - -.section .eh_frame,"a",@unwind - .byte 0x0E - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x0A # DW_EH_PE_sdata2 - .byte 0xFF - .byte 0xFF - .byte 0xFF diff --git a/lld/test/ELF/eh-frame-value-format4.s b/lld/test/ELF/eh-frame-value-format4.s deleted file mode 100644 index e3e516d4eed25..0000000000000 --- a/lld/test/ELF/eh-frame-value-format4.s +++ /dev/null @@ -1,28 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null - -.section .eh_frame,"a",@unwind - .byte 0x0E - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x02 # DW_EH_PE_udata2 - .byte 0xFF - .byte 0xFF - .byte 0xFF diff --git a/lld/test/ELF/eh-frame-value-format5.s b/lld/test/ELF/eh-frame-value-format5.s deleted file mode 100644 index cfa23723ea296..0000000000000 --- a/lld/test/ELF/eh-frame-value-format5.s +++ /dev/null @@ -1,35 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null - -.section .eh_frame,"a",@unwind - .byte 0x14 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x08 # DW_EH_PE_signed - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - - .byte 0xFF diff --git a/lld/test/ELF/eh-frame-value-format6.s b/lld/test/ELF/eh-frame-value-format6.s deleted file mode 100644 index 23093b204c501..0000000000000 --- a/lld/test/ELF/eh-frame-value-format6.s +++ /dev/null @@ -1,35 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null - -.section .eh_frame,"a",@unwind - .byte 0x14 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x00 # DW_EH_PE_absptr - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - .byte 0xFF - - .byte 0xFF diff --git a/lld/test/ELF/eh-frame-value-format7.s b/lld/test/ELF/eh-frame-value-format7.s deleted file mode 100644 index 2291f90f7c04a..0000000000000 --- a/lld/test/ELF/eh-frame-value-format7.s +++ /dev/null @@ -1,77 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -# RUN: ld.lld --eh-frame-hdr --image-base=0 -Ttext=0x1000 %t.o -o %t -# RUN: llvm-readobj -S --section-data %t | FileCheck %s - -## Check we are able to handle DW_EH_PE_udata2 encoding. - -# CHECK: Section { -# CHECK: Index: -# CHECK: Name: .eh_frame_hdr -# CHECK-NEXT: Type: SHT_PROGBITS -# CHECK-NEXT: Flags [ -# CHECK-NEXT: SHF_ALLOC -# CHECK-NEXT: ] -# CHECK-NEXT: Address: 0x2004 -# CHECK-NEXT: Offset: 0x1004 -# CHECK-NEXT: Size: 20 -# CHECK-NEXT: Link: 0 -# CHECK-NEXT: Info: 0 -# CHECK-NEXT: AddressAlignment: 4 -# CHECK-NEXT: EntrySize: 0 -# CHECK-NEXT: SectionData ( -# CHECK-NEXT: 0000: 011B033B 10000000 01000000 30F2FFFF -# CHECK-NEXT: 0010: 26000000 -# Header (always 4 bytes): 011B033B -# 10000000 = .eh_frame(0x2018) - .eh_frame_hdr(0x2004) - 4 -# 01000000 = 1 = the number of FDE pointers in the table. -# 30F2FFFF = foo(0x1000) - 0x234(addend) - .eh_frame_hdr(0x2004) - -# CHECK: Section { -# CHECK: Index: -# CHECK: Name: .eh_frame -# CHECK-NEXT: Type: SHT_PROGBITS -# CHECK-NEXT: Flags [ -# CHECK-NEXT: SHF_ALLOC -# CHECK-NEXT: ] -# CHECK-NEXT: Address: 0x2018 -# CHECK-NEXT: Offset: 0x1018 -# CHECK-NEXT: Size: -# CHECK-NEXT: Link: -# CHECK-NEXT: Info: -# CHECK-NEXT: AddressAlignment: -# CHECK-NEXT: EntrySize: -# CHECK-NEXT: SectionData ( -# CHECK-NEXT: 0000: 0E000000 00000000 01525300 01010102 -# CHECK-NEXT: 0010: FF000600 00001600 00003412 00000000 -# ^ -# ---> ADDR(foo) + 0x234 = 0x1234 - -.text -.global foo -foo: - nop - -.section .eh_frame,"a",@unwind - .long 14 # Size - .long 0x00 # ID - .byte 0x01 # Version. - - .byte 0x52 # Augmentation string: 'R','S','\0' - .byte 0x53 - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x02 # DW_EH_PE_udata2 - - .byte 0xFF - .byte 0 - - .long 0x6 # Size - .long 0x16 # ID - .short foo + 0x234 diff --git a/lld/test/ELF/eh-frame-value-format8.s b/lld/test/ELF/eh-frame-value-format8.s deleted file mode 100644 index 6e053ad558138..0000000000000 --- a/lld/test/ELF/eh-frame-value-format8.s +++ /dev/null @@ -1,74 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -# RUN: ld.lld --eh-frame-hdr --image-base=0 -Ttext=0x1000 %t.o -o %t -# RUN: llvm-readobj -S --section-data %t | FileCheck %s - -## Check we are able to handle DW_EH_PE_absptr encoding. - -# CHECK: Section { -# CHECK: Index: -# CHECK: Name: .eh_frame_hdr -# CHECK-NEXT: Type: SHT_PROGBITS -# CHECK-NEXT: Flags [ -# CHECK-NEXT: SHF_ALLOC -# CHECK-NEXT: ] -# CHECK-NEXT: Address: 0x2004 -# CHECK-NEXT: Offset: 0x1004 -# CHECK-NEXT: Size: 20 -# CHECK-NEXT: Link: 0 -# CHECK-NEXT: Info: 0 -# CHECK-NEXT: AddressAlignment: 4 -# CHECK-NEXT: EntrySize: 0 -# CHECK-NEXT: SectionData ( -# CHECK-NEXT: 0000: 011B033B 10000000 01000000 30F2FFFF -# CHECK-NEXT: 0010: 24000000 -# Header (always 4 bytes): 011B033B -# 10000000 = .eh_frame(0x2018) - .eh_frame_hdr(0x2004) - 4 -# 01000000 = 1 = the number of FDE pointers in the table. -# 30F2FFFF = foo(0x1000) - 0x234(addend) - .eh_frame_hdr(0x2004) - -# CHECK: Section { -# CHECK: Index: -# CHECK: Name: .eh_frame -# CHECK-NEXT: Type: SHT_PROGBITS -# CHECK-NEXT: Flags [ -# CHECK-NEXT: SHF_ALLOC -# CHECK-NEXT: ] -# CHECK-NEXT: Address: 0x2018 -# CHECK-NEXT: Offset: 0x1018 -# CHECK-NEXT: Size: -# CHECK-NEXT: Link: -# CHECK-NEXT: Info: -# CHECK-NEXT: AddressAlignment: -# CHECK-NEXT: EntrySize: -# CHECK-NEXT: SectionData ( -# CHECK-NEXT: 0000: 0C000000 00000000 01520001 010100FF -# CHECK-NEXT: 0010: 0C000000 14000000 34120000 00000000 -# ^ -# ---> ADDR(foo) + 0x234 = 0x1234 -.text -.global foo -foo: - nop - -.section .eh_frame,"a",@unwind - .long 12 # Size - .long 0x00 # ID - .byte 0x01 # Version. - - .byte 0x52 # Augmentation string: 'R','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x00 # DW_EH_PE_absptr - - .byte 0xFF - - .long 12 # Size - .long 0x14 # ID - .quad foo + 0x234 diff --git a/lld/test/ELF/eh-frame-value-format9.s b/lld/test/ELF/eh-frame-value-format9.s deleted file mode 100644 index 1c5ca3bbafd7e..0000000000000 --- a/lld/test/ELF/eh-frame-value-format9.s +++ /dev/null @@ -1,28 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -# RUN: not ld.lld --eh-frame-hdr %t.o -o /dev/null 2>&1 | FileCheck %s -# CHECK: error: unknown FDE size encoding - -.section .eh_frame,"a",@unwind - .long 12 # Size - .long 0x00 # ID - .byte 0x01 # Version. - - .byte 0x52 # Augmentation string: 'R','\0' - .byte 0x00 - -# Code and data alignment factors. - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - -# Return address register. - .byte 0x01 # LEB128 - - .byte 0xFE # 'R' value: invalid <0xFE> - - .byte 0xFF - - .long 12 # Size - .long 0x14 # ID - .quad .eh_frame diff --git a/lld/test/ELF/incompatible-section-flags.s b/lld/test/ELF/incompatible-section-flags.s index 30bbe75d766ad..8b52bc44ec807 100644 --- a/lld/test/ELF/incompatible-section-flags.s +++ b/lld/test/ELF/incompatible-section-flags.s @@ -1,13 +1,13 @@ // REQUIRES: x86 -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -// RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o +// RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error: // CHECK: error: incompatible section flags for .foo -// CHECK-NEXT: >>> {{.*}}incompatible-section-flags.s.tmp.o:(.foo): 0x3 +// CHECK-NEXT: >>> {{.*}}.o:(.foo): 0x3 // CHECK-NEXT: >>> output section .foo: 0x403 // CHECK: error: incompatible section flags for .bar -// CHECK-NEXT: >>> {{.*}}incompatible-section-flags.s.tmp.o:(.bar): 0x403 +// CHECK-NEXT: >>> {{.*}}.o:(.bar): 0x403 // CHECK-NEXT: >>> output section .bar: 0x3 .section .foo, "awT", @progbits, unique, 1 diff --git a/lld/test/ELF/invalid-cie-length.s b/lld/test/ELF/invalid-cie-length.s index d5465e854409c..2ea24c07202ae 100644 --- a/lld/test/ELF/invalid-cie-length.s +++ b/lld/test/ELF/invalid-cie-length.s @@ -1,10 +1,9 @@ // REQUIRES: x86 +// RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o +// RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error: -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -// RUN: not ld.lld %t -o /dev/null 2>&1 | FileCheck %s +// CHECK: error: corrupted .eh_frame: CIE/FDE too small +// CHECK-NEXT: >>> defined in {{.*}}:(.eh_frame+0x0) .section .eh_frame,"a",@unwind .byte 0 - -// CHECK: error: corrupted .eh_frame: CIE/FDE too small -// CHECK-NEXT: >>> defined in {{.*}}:(.eh_frame+0x0) diff --git a/lld/test/ELF/invalid-eh-frame.s b/lld/test/ELF/invalid-eh-frame.s deleted file mode 100644 index ccf433c6a6755..0000000000000 --- a/lld/test/ELF/invalid-eh-frame.s +++ /dev/null @@ -1,17 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s - -# CHECK: error: corrupted .eh_frame: unexpected end of CIE -# CHECK-NEXT: >>> defined in {{.*}}:(.eh_frame+0x8) - -.section .eh_frame,"a",@unwind - .byte 0x04 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 diff --git a/lld/test/ELF/invalid-eh-frame2.s b/lld/test/ELF/invalid-eh-frame2.s deleted file mode 100644 index 01f38738519b6..0000000000000 --- a/lld/test/ELF/invalid-eh-frame2.s +++ /dev/null @@ -1,23 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null --noinhibit-exec - -# CHECK: error: corrupted .eh_frame: corrupted CIE (failed to read string) -# CHECK-NEXT: >>> defined in {{.*}}:(.eh_frame+0x9) - -.section .eh_frame,"a",@unwind -.align 1 - .byte 0x08 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - .byte 0x01 - .byte 0x01 - .byte 0x01 diff --git a/lld/test/ELF/invalid-eh-frame3.s b/lld/test/ELF/invalid-eh-frame3.s deleted file mode 100644 index 6f7c7d957ab69..0000000000000 --- a/lld/test/ELF/invalid-eh-frame3.s +++ /dev/null @@ -1,21 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s - -# CHECK: error: corrupted .eh_frame: corrupted CIE (failed to read LEB128) -# CHECK-NEXT: >>> defined in {{.*}}:(.eh_frame+0xc) - -.section .eh_frame,"a",@unwind - .byte 0x08 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - .byte 0x01 - .byte 0x00 - .byte 0x01 diff --git a/lld/test/ELF/invalid-eh-frame4.s b/lld/test/ELF/invalid-eh-frame4.s deleted file mode 100644 index 51f276bc0014e..0000000000000 --- a/lld/test/ELF/invalid-eh-frame4.s +++ /dev/null @@ -1,30 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERROR --implicit-check-not=error: -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null --noinhibit-exec 2>&1 | FileCheck %s --check-prefix=WARN --implicit-check-not=error: - -# ERROR: error: corrupted .eh_frame: unknown .eh_frame augmentation string: {{.+}} -# WARN: warning: corrupted .eh_frame: unknown .eh_frame augmentation string: {{.+}} - -.section .eh_frame,"a",@unwind - .byte 0x0E - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - .byte 0x01 - .byte 0x00 - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x01 - .byte 0x01 - .byte 0x01 - .byte 0x01 diff --git a/lld/test/ELF/invalid-eh-frame5.s b/lld/test/ELF/invalid-eh-frame5.s deleted file mode 100644 index af86ed94d121f..0000000000000 --- a/lld/test/ELF/invalid-eh-frame5.s +++ /dev/null @@ -1,28 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error: - -# CHECK: error: corrupted .eh_frame: unknown .eh_frame augmentation string: {{.+}} - -.section .eh_frame,"a",@unwind - .byte 0x0E - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x03 - .byte 0x01 - .byte 0x00 - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x01 - .byte 0x01 - .byte 0x01 - .byte 0x01 diff --git a/lld/test/ELF/invalid-eh-frame6.s b/lld/test/ELF/invalid-eh-frame6.s deleted file mode 100644 index 6888419da3e3d..0000000000000 --- a/lld/test/ELF/invalid-eh-frame6.s +++ /dev/null @@ -1,32 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s -# RUN: ld.lld --eh-frame-hdr %t -o /dev/null --noinhibit-exec - -# CHECK: error: corrupted .eh_frame: unknown FDE encoding -# CHECK-NEXT: >>> defined in {{.*}}:(.eh_frame+0xe) - -.section .eh_frame,"a",@unwind - .byte 0x0E - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x01 - .byte 0x01 - .byte 0x01 - .byte 0x01 diff --git a/lld/test/ELF/invalid-eh-frame7.s b/lld/test/ELF/invalid-eh-frame7.s deleted file mode 100644 index 6955d51e7aef6..0000000000000 --- a/lld/test/ELF/invalid-eh-frame7.s +++ /dev/null @@ -1,30 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s - -# CHECK: error: corrupted .eh_frame: DW_EH_PE_aligned encoding is not supported - -.section .eh_frame,"a",@unwind - .byte 0x0E - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x51 - .byte 0x01 - .byte 0x01 - .byte 0x01 diff --git a/lld/test/ELF/invalid-eh-frame8.s b/lld/test/ELF/invalid-eh-frame8.s deleted file mode 100644 index 856fddb19c025..0000000000000 --- a/lld/test/ELF/invalid-eh-frame8.s +++ /dev/null @@ -1,30 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s - -# CHECK: error: corrupted .eh_frame: corrupted CIE - -.section .eh_frame,"a",@unwind - .byte 0x0E - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x01 - - .byte 0x50 # Augmentation string: 'P','\0' - .byte 0x00 - - .byte 0x01 - - .byte 0x01 # LEB128 - .byte 0x01 # LEB128 - - .byte 0x03 - .byte 0x01 - .byte 0x01 - .byte 0x01 diff --git a/lld/test/ELF/invalid-eh-frame9.s b/lld/test/ELF/invalid-eh-frame9.s deleted file mode 100644 index 436b34bb3a802..0000000000000 --- a/lld/test/ELF/invalid-eh-frame9.s +++ /dev/null @@ -1,15 +0,0 @@ -# REQUIRES: x86 - -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t -# RUN: not ld.lld --eh-frame-hdr %t -o /dev/null 2>&1 | FileCheck %s - -# CHECK: error: corrupted .eh_frame: CIE is too small - -.section .eh_frame,"a",@unwind - .byte 0x03 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 - .byte 0x00 diff --git a/lld/test/ELF/loongarch-branch.s b/lld/test/ELF/loongarch-branch.s index b223ff95bd89a..e099d5d96d883 100644 --- a/lld/test/ELF/loongarch-branch.s +++ b/lld/test/ELF/loongarch-branch.s @@ -1,12 +1,13 @@ # REQUIRES: loongarch +# RUN: rm -rf %t && mkdir %t && cd %t -# RUN: llvm-mc --filetype=obj --triple=loongarch32-unknown-elf %s -o %t.la32.o -# RUN: llvm-mc --filetype=obj --triple=loongarch64-unknown-elf %s -o %t.la64.o +# RUN: llvm-mc --filetype=obj --triple=loongarch32 %s -o 32.o +# RUN: llvm-mc --filetype=obj --triple=loongarch64 %s -o 64.o -# RUN: ld.lld %t.la32.o --defsym foo16=b16+4 --defsym bar16=b16 --defsym foo21=b21+4 --defsym bar21=b21 --defsym foo26=b26+4 --defsym bar26=b26 -o %t.la32 -# RUN: ld.lld %t.la64.o --defsym foo16=b16+4 --defsym bar16=b16 --defsym foo21=b21+4 --defsym bar21=b21 --defsym foo26=b26+4 --defsym bar26=b26 -o %t.la64 -# RUN: llvm-objdump --no-show-raw-insn -d %t.la32 | FileCheck %s --check-prefix=CHECK -# RUN: llvm-objdump --no-show-raw-insn -d %t.la64 | FileCheck %s --check-prefix=CHECK +# RUN: ld.lld 32.o --defsym foo16=b16+4 --defsym bar16=b16 --defsym foo21=b21+4 --defsym bar21=b21 --defsym foo26=b26+4 --defsym bar26=b26 -o 32 +# RUN: ld.lld 64.o --defsym foo16=b16+4 --defsym bar16=b16 --defsym foo21=b21+4 --defsym bar21=b21 --defsym foo26=b26+4 --defsym bar26=b26 -o 64 +# RUN: llvm-objdump --no-show-raw-insn -d 32 | FileCheck %s +# RUN: llvm-objdump --no-show-raw-insn -d 64 | FileCheck %s # CHECK: beq $zero, $zero, 4 # CHECK: bne $zero, $zero, -4 # CHECK: beqz $s8, 4 @@ -14,10 +15,10 @@ # CHECK: b 4 # CHECK: bl -4 -# RUN: ld.lld %t.la32.o --defsym foo16=b16+0x1fffc --defsym bar16=b16+4-0x20000 --defsym foo21=b21+0x3ffffc --defsym bar21=b21+4-0x400000 --defsym foo26=b26+0x7fffffc --defsym bar26=b26+4-0x8000000 -o %t.la32.limits -# RUN: ld.lld %t.la64.o --defsym foo16=b16+0x1fffc --defsym bar16=b16+4-0x20000 --defsym foo21=b21+0x3ffffc --defsym bar21=b21+4-0x400000 --defsym foo26=b26+0x7fffffc --defsym bar26=b26+4-0x8000000 -o %t.la64.limits -# RUN: llvm-objdump --no-show-raw-insn -d %t.la32.limits | FileCheck --check-prefix=LIMITS %s -# RUN: llvm-objdump --no-show-raw-insn -d %t.la64.limits | FileCheck --check-prefix=LIMITS %s +# RUN: ld.lld 32.o --defsym foo16=b16+0x1fffc --defsym bar16=b16+4-0x20000 --defsym foo21=b21+0x3ffffc --defsym bar21=b21+4-0x400000 --defsym foo26=b26+0x7fffffc --defsym bar26=b26+4-0x8000000 -o 32.limits +# RUN: ld.lld 64.o --defsym foo16=b16+0x1fffc --defsym bar16=b16+4-0x20000 --defsym foo21=b21+0x3ffffc --defsym bar21=b21+4-0x400000 --defsym foo26=b26+0x7fffffc --defsym bar26=b26+4-0x8000000 -o 64.limits +# RUN: llvm-objdump --no-show-raw-insn -d 32.limits | FileCheck --check-prefix=LIMITS %s +# RUN: llvm-objdump --no-show-raw-insn -d 64.limits | FileCheck --check-prefix=LIMITS %s # LIMITS: beq $zero, $zero, 131068 # LIMITS-NEXT: bne $zero, $zero, -131072 # LIMITS: beqz $s8, 4194300 @@ -25,32 +26,23 @@ # LIMITS: b 134217724 # LIMITS-NEXT: bl -134217728 -# RUN: not ld.lld %t.la32.o --defsym foo16=b16+0x20000 --defsym bar16=b16+4-0x20004 --defsym foo21=b21+0x400000 --defsym bar21=b21+4-0x400004 --defsym foo26=b26+0x8000000 --defsym bar26=b26+4-0x8000004 -o /dev/null 2>&1 | FileCheck -DFILE=%t.la32.o --check-prefix=ERROR-RANGE %s -# RUN: not ld.lld %t.la64.o --defsym foo16=b16+0x20000 --defsym bar16=b16+4-0x20004 --defsym foo21=b21+0x400000 --defsym bar21=b21+4-0x400004 --defsym foo26=b26+0x8000000 --defsym bar26=b26+4-0x8000004 -o /dev/null 2>&1 | FileCheck -DFILE=%t.la64.o --check-prefix=ERROR-RANGE %s -# ERROR-RANGE: error: [[FILE]]:(.text+0x0): relocation R_LARCH_B16 out of range: 131072 is not in [-131072, 131071]; references 'foo16' -# ERROR-RANGE: error: [[FILE]]:(.text+0x4): relocation R_LARCH_B16 out of range: -131076 is not in [-131072, 131071]; references 'bar16' -# ERROR-RANGE: error: [[FILE]]:(.text+0x8): relocation R_LARCH_B21 out of range: 4194304 is not in [-4194304, 4194303]; references 'foo21' -# ERROR-RANGE: error: [[FILE]]:(.text+0xc): relocation R_LARCH_B21 out of range: -4194308 is not in [-4194304, 4194303]; references 'bar21' -# ERROR-RANGE: error: [[FILE]]:(.text+0x10): relocation R_LARCH_B26 out of range: 134217728 is not in [-134217728, 134217727]; references 'foo26' -# ERROR-RANGE: error: [[FILE]]:(.text+0x14): relocation R_LARCH_B26 out of range: -134217732 is not in [-134217728, 134217727]; references 'bar26' +# RUN: not ld.lld 32.o --defsym foo16=b16+0x20000 --defsym bar16=b16+4-0x20004 --defsym foo21=b21+0x400000 --defsym bar21=b21+4-0x400004 --defsym foo26=b26+0x8000000 --defsym bar26=b26+4-0x8000004 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s --implicit-check-not=error: +# RUN: not ld.lld 64.o --defsym foo16=b16+0x20000 --defsym bar16=b16+4-0x20004 --defsym foo21=b21+0x400000 --defsym bar21=b21+4-0x400004 --defsym foo26=b26+0x8000000 --defsym bar26=b26+4-0x8000004 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s --implicit-check-not=error: +# ERROR-RANGE: error: {{.*}}:(.text+0x0): relocation R_LARCH_B16 out of range: 131072 is not in [-131072, 131071]; references 'foo16' +# ERROR-RANGE: error: {{.*}}:(.text+0x4): relocation R_LARCH_B16 out of range: -131076 is not in [-131072, 131071]; references 'bar16' +# ERROR-RANGE: error: {{.*}}:(.text+0x8): relocation R_LARCH_B21 out of range: 4194304 is not in [-4194304, 4194303]; references 'foo21' +# ERROR-RANGE: error: {{.*}}:(.text+0xc): relocation R_LARCH_B21 out of range: -4194308 is not in [-4194304, 4194303]; references 'bar21' +# ERROR-RANGE: error: {{.*}}:(.text+0x10): relocation R_LARCH_B26 out of range: 134217728 is not in [-134217728, 134217727]; references 'foo26' +# ERROR-RANGE: error: {{.*}}:(.text+0x14): relocation R_LARCH_B26 out of range: -134217732 is not in [-134217728, 134217727]; references 'bar26' -# RUN: not ld.lld %t.la32.o --defsym foo16=b16+1 --defsym bar16=b16-1 --defsym foo21=b21+1 --defsym bar21=b21-1 --defsym foo26=b26+1 --defsym bar26=b26-1 -o /dev/null 2>&1 | FileCheck -DFILE=%t.la32.o --check-prefix=ERROR-ALIGN-1 %s -# RUN: not ld.lld %t.la64.o --defsym foo16=b16+1 --defsym bar16=b16-1 --defsym foo21=b21+1 --defsym bar21=b21-1 --defsym foo26=b26+1 --defsym bar26=b26-1 -o /dev/null 2>&1 | FileCheck -DFILE=%t.la64.o --check-prefix=ERROR-ALIGN-1 %s -# ERROR-ALIGN-1: error: [[FILE]]:(.text+0x0): improper alignment for relocation R_LARCH_B16: 0x1 is not aligned to 4 bytes -# ERROR-ALIGN-1-NEXT: error: [[FILE]]:(.text+0x4): improper alignment for relocation R_LARCH_B16: 0xFFFFFFFFFFFFFFFB is not aligned to 4 bytes -# ERROR-ALIGN-1-NEXT: error: [[FILE]]:(.text+0x8): improper alignment for relocation R_LARCH_B21: 0x1 is not aligned to 4 bytes -# ERROR-ALIGN-1-NEXT: error: [[FILE]]:(.text+0xc): improper alignment for relocation R_LARCH_B21: 0xFFFFFFFFFFFFFFFB is not aligned to 4 bytes -# ERROR-ALIGN-1-NEXT: error: [[FILE]]:(.text+0x10): improper alignment for relocation R_LARCH_B26: 0x1 is not aligned to 4 bytes -# ERROR-ALIGN-1-NEXT: error: [[FILE]]:(.text+0x14): improper alignment for relocation R_LARCH_B26: 0xFFFFFFFFFFFFFFFB is not aligned to 4 bytes - -# RUN: not ld.lld %t.la32.o --defsym foo16=b16+2 --defsym bar16=b16-2 --defsym foo21=b21+2 --defsym bar21=b21-2 --defsym foo26=b26+2 --defsym bar26=b26-2 -o /dev/null 2>&1 | FileCheck -DFILE=%t.la32.o --check-prefix=ERROR-ALIGN-2 %s -# RUN: not ld.lld %t.la64.o --defsym foo16=b16+2 --defsym bar16=b16-2 --defsym foo21=b21+2 --defsym bar21=b21-2 --defsym foo26=b26+2 --defsym bar26=b26-2 -o /dev/null 2>&1 | FileCheck -DFILE=%t.la64.o --check-prefix=ERROR-ALIGN-2 %s -# ERROR-ALIGN-2: error: [[FILE]]:(.text+0x0): improper alignment for relocation R_LARCH_B16: 0x2 is not aligned to 4 bytes -# ERROR-ALIGN-2-NEXT: error: [[FILE]]:(.text+0x4): improper alignment for relocation R_LARCH_B16: 0xFFFFFFFFFFFFFFFA is not aligned to 4 bytes -# ERROR-ALIGN-2-NEXT: error: [[FILE]]:(.text+0x8): improper alignment for relocation R_LARCH_B21: 0x2 is not aligned to 4 bytes -# ERROR-ALIGN-2-NEXT: error: [[FILE]]:(.text+0xc): improper alignment for relocation R_LARCH_B21: 0xFFFFFFFFFFFFFFFA is not aligned to 4 bytes -# ERROR-ALIGN-2-NEXT: error: [[FILE]]:(.text+0x10): improper alignment for relocation R_LARCH_B26: 0x2 is not aligned to 4 bytes -# ERROR-ALIGN-2-NEXT: error: [[FILE]]:(.text+0x14): improper alignment for relocation R_LARCH_B26: 0xFFFFFFFFFFFFFFFA is not aligned to 4 bytes +# RUN: not ld.lld 32.o --defsym foo16=b16+1 --defsym bar16=b16+4+1 --defsym foo21=b21+1 --defsym bar21=b21+4+1 --defsym foo26=b26+1 --defsym bar26=b26+4+1 2>&1 | FileCheck --check-prefix=ERROR-ALIGN %s --implicit-check-not=error: +# RUN: not ld.lld 64.o --defsym foo16=b16+1 --defsym bar16=b16+4+1 --defsym foo21=b21+1 --defsym bar21=b21+4+1 --defsym foo26=b26+1 --defsym bar26=b26+4+1 2>&1 | FileCheck --check-prefix=ERROR-ALIGN %s --implicit-check-not=error: +# ERROR-ALIGN: error: {{.*}}:(.text+0x0): improper alignment for relocation R_LARCH_B16: 0x1 is not aligned to 4 bytes +# ERROR-ALIGN-NEXT: error: {{.*}}:(.text+0x4): improper alignment for relocation R_LARCH_B16: 0x1 is not aligned to 4 bytes +# ERROR-ALIGN-NEXT: error: {{.*}}:(.text+0x8): improper alignment for relocation R_LARCH_B21: 0x1 is not aligned to 4 bytes +# ERROR-ALIGN-NEXT: error: {{.*}}:(.text+0xc): improper alignment for relocation R_LARCH_B21: 0x1 is not aligned to 4 bytes +# ERROR-ALIGN-NEXT: error: {{.*}}:(.text+0x10): improper alignment for relocation R_LARCH_B26: 0x1 is not aligned to 4 bytes +# ERROR-ALIGN-NEXT: error: {{.*}}:(.text+0x14): improper alignment for relocation R_LARCH_B26: 0x1 is not aligned to 4 bytes .global _start .global b16 diff --git a/lld/test/ELF/mips-align-err.s b/lld/test/ELF/mips-align-err.s index be7f6aebf19e4..b436763a0cf6f 100644 --- a/lld/test/ELF/mips-align-err.s +++ b/lld/test/ELF/mips-align-err.s @@ -1,10 +1,11 @@ # REQUIRES: mips -# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o \ -# RUN: -mcpu=mips32r6 -# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \ -# RUN: -mcpu=mips32r6 %S/Inputs/mips-align-err.s -o %t2.o -# RUN: not ld.lld %t.o %t2.o -o /dev/null 2>&1 | FileCheck %s -# CHECK: error: {{.*}}:(.text+0x1): improper alignment for relocation R_MIPS_PC16: 0xB is not aligned to 4 bytes +# RUN: rm -rf %t && mkdir %t && cd %t +# RUN: llvm-mc -filetype=obj -triple=mips -mcpu=mips32r6 %s -o a.o +# RUN: llvm-mc -filetype=obj -triple=mips -mcpu=mips32r6 %S/Inputs/mips-align-err.s -o b.o +# RUN: not ld.lld a.o b.o 2>&1 | FileCheck %s --implicit-check-not=error: + +# CHECK: error: a.o:(.text+0x1): unsupported jump/branch instruction between ISA modes referenced by R_MIPS_PC16 relocation +# CHECK-NEXT: error: a.o:(.text+0x1): improper alignment for relocation R_MIPS_PC16: 0xB is not aligned to 4 bytes .globl __start __start: diff --git a/lld/test/ELF/ppc64-abs32-dyn.s b/lld/test/ELF/ppc64-abs32-dyn.s index 015a6b0f4ed2a..a14172f698deb 100644 --- a/lld/test/ELF/ppc64-abs32-dyn.s +++ b/lld/test/ELF/ppc64-abs32-dyn.s @@ -1,10 +1,12 @@ # REQUIRES: ppc # RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o %t.o -# RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s +# RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error: ## Test we don't create R_AARCH64_RELATIVE. -# CHECK: error: relocation R_PPC64_ADDR32 cannot be used against symbol 'hidden'; recompile with -fPIC +# CHECK: error: relocation R_PPC64_ADDR32 cannot be used against symbol 'hidden'; recompile with -fPIC +# CHECK-NEXT: >>> defined in {{.*}}.o +# CHECK-NEXT: >>> referenced by {{.*}}.o:(.data+0x0) .globl hidden .hidden hidden diff --git a/lld/test/ELF/ppc64-error-toc-tail-call.s b/lld/test/ELF/ppc64-error-toc-tail-call.s index 7f492a322f840..584509432674a 100644 --- a/lld/test/ELF/ppc64-error-toc-tail-call.s +++ b/lld/test/ELF/ppc64-error-toc-tail-call.s @@ -1,17 +1,18 @@ // REQUIRES: ppc +// RUN: rm -rf %t && mkdir %t && cd %t -// RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o -// RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %p/Inputs/shared-ppc64.s -o %t2.o -// RUN: ld.lld -shared %t2.o -o %t2.so -// RUN: not ld.lld %t.o %t2.so -o /dev/null 2>&1 | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=powerpc64le %s -o a.o +// RUN: llvm-mc -filetype=obj -triple=powerpc64le %p/Inputs/shared-ppc64.s -o b.o +// RUN: ld.lld -shared b.o -o b.so +// RUN: not ld.lld a.o b.so 2>&1 | FileCheck %s --implicit-check-not=error: -// RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o -// RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %p/Inputs/shared-ppc64.s -o %t2.o -// RUN: ld.lld -shared %t2.o -o %t2.so -// RUN: not ld.lld %t.o %t2.so -o /dev/null 2>&1 | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=powerpc64 %s -o a.o +// RUN: llvm-mc -filetype=obj -triple=powerpc64 %p/Inputs/shared-ppc64.s -o b.o +// RUN: ld.lld -shared b.o -o b.so +// RUN: not ld.lld a.o b.so 2>&1 | FileCheck %s --implicit-check-not=error: -# A tail call to an external function without a nop should issue an error. -// CHECK: call to foo lacks nop, can't restore toc +/// A tail call to an external function without a nop should issue an error. +// CHECK: error: a.o:(.text+0x0): call to foo lacks nop, can't restore toc // CHECK-NOT: lacks nop .text .abiversion 2 diff --git a/lld/test/ELF/relocation-nocopy.s b/lld/test/ELF/relocation-nocopy.s index 32b9dfe3bd033..1da532a5d0be7 100644 --- a/lld/test/ELF/relocation-nocopy.s +++ b/lld/test/ELF/relocation-nocopy.s @@ -1,15 +1,27 @@ // REQUIRES: x86 -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/relocation-copy.s -o %t2.o +// RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o +// RUN: llvm-mc -filetype=obj -triple=x86_64 %p/Inputs/relocation-copy.s -o %t2.o // RUN: ld.lld -shared %t2.o -o %t.so -// RUN: not ld.lld -z nocopyreloc %t.o %t.so -o /dev/null 2>&1 | FileCheck %s +// RUN: not ld.lld -z nocopyreloc %t.o %t.so -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error: -// CHECK: error: unresolvable relocation R_X86_64_32S against symbol 'x' -// CHECK: error: unresolvable relocation R_X86_64_32S against symbol 'y' -// CHECK: error: unresolvable relocation R_X86_64_32S against symbol 'z' -// CHECK: error: unresolvable relocation R_X86_64_32 against symbol 'x' -// CHECK: error: unresolvable relocation R_X86_64_32 against symbol 'y' -// CHECK: error: unresolvable relocation R_X86_64_32 against symbol 'z' +// CHECK: error: unresolvable relocation R_X86_64_32S against symbol 'x'; recompile with -fPIC or remove '-z nocopyreloc' +// CHECK-NEXT: >>> defined in {{.*}}.so +// CHECK-NEXT: >>> referenced by {{.*}}.o:(.text+0x{{.*}}) +// CHECK: error: unresolvable relocation R_X86_64_32S against symbol 'y'; recompile with -fPIC or remove '-z nocopyreloc' +// CHECK-NEXT: >>> defined in {{.*}}.so +// CHECK-NEXT: >>> referenced by {{.*}}.o:(.text+0x{{.*}}) +// CHECK: error: unresolvable relocation R_X86_64_32S against symbol 'z'; recompile with -fPIC or remove '-z nocopyreloc' +// CHECK-NEXT: >>> defined in {{.*}}.so +// CHECK-NEXT: >>> referenced by {{.*}}.o:(.text+0x{{.*}}) +// CHECK: error: unresolvable relocation R_X86_64_32 against symbol 'x'; recompile with -fPIC or remove '-z nocopyreloc' +// CHECK-NEXT: >>> defined in {{.*}}.so +// CHECK-NEXT: >>> referenced by {{.*}}.o:(.text+0x{{.*}}) +// CHECK: error: unresolvable relocation R_X86_64_32 against symbol 'y'; recompile with -fPIC or remove '-z nocopyreloc' +// CHECK-NEXT: >>> defined in {{.*}}.so +// CHECK-NEXT: >>> referenced by {{.*}}.o:(.text+0x{{.*}}) +// CHECK: error: unresolvable relocation R_X86_64_32 against symbol 'z'; recompile with -fPIC or remove '-z nocopyreloc' +// CHECK-NEXT: >>> defined in {{.*}}.so +// CHECK-NEXT: >>> referenced by {{.*}}.o:(.text+0x{{.*}}) .text .global _start diff --git a/lld/test/ELF/relocation-past-merge-end.s b/lld/test/ELF/relocation-past-merge-end.s index 9a096651da3ad..0aa201c31138f 100644 --- a/lld/test/ELF/relocation-past-merge-end.s +++ b/lld/test/ELF/relocation-past-merge-end.s @@ -1,9 +1,10 @@ // REQUIRES: x86 -// RUN: llvm-mc %s -o %t.o -filetype=obj -triple=x86_64-pc-linux -// RUN: not ld.lld %t.o -o /dev/null -shared 2>&1 | FileCheck %s -DPREFIX=error -// RUN: ld.lld %t.o -o /dev/null -shared --noinhibit-exec 2>&1 | FileCheck %s -DPREFIX=warning -// CHECK: [[PREFIX]]: {{.*}}:(.foo): offset is outside the section -// CHECK: [[PREFIX]]: {{.*}}:(.rodata.str1.1): offset is outside the section +// RUN: llvm-mc %s -o %t.o -filetype=obj -triple=x86_64 +// RUN: not ld.lld %t.o -o /dev/null -shared 2>&1 | FileCheck %s -DPREFIX=error --implicit-check-not=error: +// RUN: ld.lld %t.o -o /dev/null -shared --noinhibit-exec 2>&1 | FileCheck %s -DPREFIX=warning --implicit-check-not=warning: + +// CHECK: [[PREFIX]]: {{.*}}:(.foo): offset is outside the section +// CHECK-NEXT: [[PREFIX]]: {{.*}}:(.rodata.str1.1): offset is outside the section .data .quad .foo + 10 diff --git a/lld/test/ELF/undef-spell-corrector.s b/lld/test/ELF/undef-spell-corrector.s index 264d685178daa..7fde6870f5287 100644 --- a/lld/test/ELF/undef-spell-corrector.s +++ b/lld/test/ELF/undef-spell-corrector.s @@ -1,23 +1,22 @@ # REQUIRES: x86 - -# RUN: rm -rf %t && split-file %s %t -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/test.s -o %t/test.o -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/bcde-abcd-abde.s -o %t/bcde-abcd-abde.o -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/bbcde-abcdd.s -o %t/bbcde-abcdd.o -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/aabcde-abcdee.s -o %t/aabcde-abcdee.o -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/bacde.s -o %t/bacde.o -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/_Z3fooPi.s -o %t/_Z3fooPi.o -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/_Z3fooPKi-_Z3fooPi.s -o %t/_Z3fooPKi-_Z3fooPi.o -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/_Z3FOOPKi.s -o %t/_Z3FOOPKi.o -# RUN: llvm-mc -filetype=obj -triple=x86_64 %t/_Z3fooPKi-_Z3FOOPKi.s -o %t/_Z3fooPKi-_Z3FOOPKi.o +# RUN: rm -rf %t && split-file %s %t && cd %t +# RUN: llvm-mc -filetype=obj -triple=x86_64 test.s -o test.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 bcde-abcd-abde.s -o bcde-abcd-abde.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 bbcde-abcdd.s -o bbcde-abcdd.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 aabcde-abcdee.s -o aabcde-abcdee.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 bacde.s -o bacde.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 _Z3fooPi.s -o _Z3fooPi.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 _Z3fooPKi-_Z3fooPi.s -o _Z3fooPKi-_Z3fooPi.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 _Z3FOOPKi.s -o _Z3FOOPKi.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 _Z3fooPKi-_Z3FOOPKi.s -o _Z3fooPKi-_Z3FOOPKi.o ## Insert a character. ## The spell corrector is enabled for the first two "undefined symbol" diagnostics. -# RUN: not ld.lld %t/test.o %t/bcde-abcd-abde.o -o /dev/null 2>&1 | FileCheck --check-prefix=INSERT %s -DFILE=%t/test.o +# RUN: not ld.lld test.o bcde-abcd-abde.o 2>&1 | FileCheck --check-prefix=INSERT %s -DFILE=test.o --implicit-check-not=error: ## Symbols defined in DSO can be suggested. -# RUN: ld.lld %t/test.o -shared -o %t.so -# RUN: not ld.lld %t.so %t/bcde-abcd-abde.o -o /dev/null 2>&1 | FileCheck --check-prefix=INSERT %s -DFILE=%t.so +# RUN: ld.lld test.o -shared -o test.so +# RUN: not ld.lld test.so bcde-abcd-abde.o 2>&1 | FileCheck --check-prefix=INSERT %s -DFILE=test.so --implicit-check-not=error: # INSERT: error: undefined symbol: bcde # INSERT-NEXT: >>> referenced by {{.*}} @@ -29,10 +28,9 @@ # INSERT-NEXT: >>> defined in: [[FILE]] # INSERT: error: undefined symbol: abde # INSERT-NEXT: >>> referenced by {{.*}} -# INSERT-NOT: >>> ## Substitute a character. -# RUN: not ld.lld %t/test.o %t/bbcde-abcdd.o -o /dev/null 2>&1 | FileCheck --check-prefix=SUBST %s +# RUN: not ld.lld test.o bbcde-abcdd.o 2>&1 | FileCheck --check-prefix=SUBST %s --implicit-check-not=error: # SUBST: error: undefined symbol: bbcde # SUBST-NEXT: >>> referenced by {{.*}} @@ -42,7 +40,7 @@ # SUBST-NEXT: >>> did you mean: abcde ## Delete a character. -# RUN: not ld.lld %t/test.o %t/aabcde-abcdee.o -o /dev/null 2>&1 | FileCheck --check-prefix=DELETE %s +# RUN: not ld.lld test.o aabcde-abcdee.o 2>&1 | FileCheck --check-prefix=DELETE %s --implicit-check-not=error: # DELETE: error: undefined symbol: aabcde # DELETE-NEXT: >>> referenced by {{.*}} @@ -52,24 +50,24 @@ # DELETE-NEXT: >>> did you mean: abcde ## Transpose. -# RUN: not ld.lld %t/test.o %t/bacde.o -o /dev/null 2>&1 | FileCheck --check-prefix=TRANSPOSE %s +# RUN: not ld.lld test.o bacde.o 2>&1 | FileCheck --check-prefix=TRANSPOSE %s --implicit-check-not=error: # TRANSPOSE: error: undefined symbol: bacde # TRANSPOSE-NEXT: >>> referenced by {{.*}} # TRANSPOSE-NEXT: >>> did you mean: abcde ## Missing const qualifier. -# RUN: not ld.lld %t/test.o %t/_Z3fooPi.o -o /dev/null 2>&1 | FileCheck --check-prefix=CONST %s +# RUN: not ld.lld test.o _Z3fooPi.o 2>&1 | FileCheck --check-prefix=CONST %s --implicit-check-not=error: ## Local defined symbols. -# RUN: not ld.lld %t/_Z3fooPKi-_Z3fooPi.o -o /dev/null 2>&1 | FileCheck --check-prefix=CONST %s +# RUN: not ld.lld _Z3fooPKi-_Z3fooPi.o 2>&1 | FileCheck --check-prefix=CONST %s --implicit-check-not=error: # CONST: error: undefined symbol: foo(int*) # CONST-NEXT: >>> referenced by {{.*}} # CONST-NEXT: >>> did you mean: foo(int const*) ## Case mismatch. -# RUN: not ld.lld %t/test.o %t/_Z3FOOPKi.o -o /dev/null 2>&1 | FileCheck --check-prefix=CASE %s -# RUN: not ld.lld %t/_Z3fooPKi-_Z3FOOPKi.o -o /dev/null 2>&1 | FileCheck --check-prefix=CASE %s +# RUN: not ld.lld test.o _Z3FOOPKi.o 2>&1 | FileCheck --check-prefix=CASE %s --implicit-check-not=error: +# RUN: not ld.lld _Z3fooPKi-_Z3FOOPKi.o 2>&1 | FileCheck --check-prefix=CASE %s --implicit-check-not=error: # CASE: error: undefined symbol: FOO(int const*) # CASE-NEXT: >>> referenced by {{.*}} diff --git a/lld/test/ELF/vs-diagnostics-dynamic-relocation.s b/lld/test/ELF/vs-diagnostics-dynamic-relocation.s index 806ed81c438e3..cfa2e042d689b 100644 --- a/lld/test/ELF/vs-diagnostics-dynamic-relocation.s +++ b/lld/test/ELF/vs-diagnostics-dynamic-relocation.s @@ -1,13 +1,13 @@ // REQUIRES: x86 -// RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -// RUN: not ld.lld -shared --vs-diagnostics %t.o -o /dev/null 2>&1 | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o +// RUN: not ld.lld -shared --vs-diagnostics %t.o -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error: -// CHECK: dyn.s(15): error: relocation R_X86_64_64 cannot be used against local symbol; recompile with -fPIC +// CHECK: dyn.s(15): error: relocation R_X86_64_64 cannot be used against local symbol; recompile with -fPIC // CHECK-NEXT: >>> defined in {{.*}}.o // CHECK-NEXT: >>> referenced by dyn.s:15 // CHECK-NEXT: >>>{{.*}}.o:(.text+0x{{.+}}) -// CHECK: /tmp{{/|\\}}dyn.s(20): error: relocation R_X86_64_64 cannot be used against local symbol; recompile with -fPIC +// CHECK: /tmp{{/|\\}}dyn.s(20): error: relocation R_X86_64_64 cannot be used against local symbol; recompile with -fPIC // CHECK-NEXT: >>> defined in {{.*}}.o // CHECK-NEXT: >>> referenced by dyn.s:20 (/tmp{{/|\\}}dyn.s:20) // CHECK-NEXT: >>>{{.*}}.o:(.text+0x{{.+}}) diff --git a/lld/test/ELF/x86-64-tls-ie-err.s b/lld/test/ELF/x86-64-tls-ie-err.s index 3cc7cb0d41737..ab0296a626438 100644 --- a/lld/test/ELF/x86-64-tls-ie-err.s +++ b/lld/test/ELF/x86-64-tls-ie-err.s @@ -1,11 +1,11 @@ # REQUIRES: x86 # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t.o -# RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck -DFILE=%t.o %s +# RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error: -# CHECK: error: [[FILE]]:(.text+0x2): invalid prefix with R_X86_64_CODE_4_GOTTPOFF! -# CHECK-NEXT: error: [[FILE]]:(.text+0x8): invalid prefix with R_X86_64_CODE_6_GOTTPOFF! -# CHECK-NEXT: error: [[FILE]]:(.text+0x12): R_X86_64_CODE_4_GOTTPOFF must be used in MOVQ or ADDQ instructions only -# CHECK-NEXT: error: [[FILE]]:(.text+0x1a): R_X86_64_CODE_6_GOTTPOFF must be used in ADDQ instructions with NDD/NF/NDD+NF only +# CHECK: error: {{.*}}.o:(.text+0x2): invalid prefix with R_X86_64_CODE_4_GOTTPOFF! +# CHECK-NEXT: error: {{.*}}.o:(.text+0x8): invalid prefix with R_X86_64_CODE_6_GOTTPOFF! +# CHECK-NEXT: error: {{.*}}.o:(.text+0x12): R_X86_64_CODE_4_GOTTPOFF must be used in MOVQ or ADDQ instructions only +# CHECK-NEXT: error: {{.*}}.o:(.text+0x1a): R_X86_64_CODE_6_GOTTPOFF must be used in ADDQ instructions with NDD/NF/NDD+NF only ## These negative tests are to check if the invalid prefix and unsupported ## instructions for TLS relocation types with APX instructions are handled as diff --git a/lld/test/ELF/ztext.s b/lld/test/ELF/ztext.s index 11e89e025e060..37304f1c7db2e 100644 --- a/lld/test/ELF/ztext.s +++ b/lld/test/ELF/ztext.s @@ -1,20 +1,30 @@ # REQUIRES: x86 -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o -# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/ztext.s -o %t2.o -# RUN: ld.lld %t2.o -o %t2.so -shared -soname=so - -# RUN: ld.lld -z notext %t.o %t2.so -o %t -shared -# RUN: llvm-readobj --dynamic-table -r %t | FileCheck %s -# RUN: ld.lld -z notext %t.o %t2.so -o %t2 -pie -# RUN: llvm-readobj --dynamic-table -r %t2 | FileCheck %s -# RUN: ld.lld -z notext %t.o %t2.so -o %t3 -# RUN: llvm-readobj --dynamic-table -r %t3 | FileCheck --check-prefix=STATIC %s - -# RUN: not ld.lld %t.o %t2.so -o /dev/null -shared 2>&1 | FileCheck --check-prefix=ERR %s -# RUN: not ld.lld -z text %t.o %t2.so -o /dev/null -shared 2>&1 | FileCheck --check-prefix=ERR %s -# ERR: error: relocation R_X86_64_64 cannot be used against symbol 'bar'; recompile with -fPIC - -# If the preference is to have text relocations, don't create plt of copy relocations. +# RUN: rm -rf %t && mkdir %t && cd %t +# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o a.o +# RUN: llvm-mc -filetype=obj -triple=x86_64 %p/Inputs/ztext.s -o b.o +# RUN: ld.lld b.o -o b.so -shared -soname=so + +# RUN: ld.lld -z notext a.o b.so -o out -shared +# RUN: llvm-readobj --dynamic-table -r out | FileCheck %s +# RUN: ld.lld -z notext a.o b.so -o out.pie -pie +# RUN: llvm-readobj --dynamic-table -r out.pie | FileCheck %s +# RUN: ld.lld -z notext a.o b.so -o out.exe +# RUN: llvm-readobj --dynamic-table -r out.exe | FileCheck --check-prefix=STATIC %s + +# RUN: not ld.lld a.o b.so -shared 2>&1 | FileCheck --check-prefix=ERR %s --implicit-check-not=error: +# RUN: not ld.lld -z text a.o b.so -shared 2>&1 | FileCheck --check-prefix=ERR %s --implicit-check-not=error: + +# ERR: error: relocation R_X86_64_64 cannot be used against local symbol; recompile with -fPIC +# ERR-NEXT: >>> defined in a.o +# ERR-NEXT: >>> referenced by a.o:(.text+0x0) +# ERR: error: relocation R_X86_64_64 cannot be used against symbol 'bar'; recompile with -fPIC +# ERR-NEXT: >>> defined in b.so +# ERR-NEXT: >>> referenced by a.o:(.text+0x8) +# ERR: error: relocation R_X86_64_PC64 cannot be used against symbol 'zed'; recompile with -fPIC +# ERR-NEXT: >>> defined in b.so +# ERR-NEXT: >>> referenced by a.o:(.text+0x10) + +## If the preference is to have text relocations, don't create plt of copy relocations. # CHECK: DynamicSection [ # CHECK: FLAGS TEXTREL diff --git a/lld/test/MachO/arm64-branch-addend-stubs.s b/lld/test/MachO/arm64-branch-addend-stubs.s new file mode 100644 index 0000000000000..f1301f580275c --- /dev/null +++ b/lld/test/MachO/arm64-branch-addend-stubs.s @@ -0,0 +1,80 @@ +# REQUIRES: aarch64 + +## Test that branch relocations with non-zero addends correctly target the +## actual function address, not the stub address. When a symbol is accessed +## via both a regular call (goes through stub) and a branch with addend +## (targeting an interior point), the addend must be applied to the real +## function VA, not the stub VA. +## +## This test uses -flat_namespace on a dylib, which makes locally-defined +## symbols interposable and thus accessible via stubs. This creates the +## scenario where a function is both defined locally AND in stubs. + +# RUN: rm -rf %t; mkdir -p %t +# RUN: llvm-mc -filetype=obj -triple=arm64-apple-darwin %s -o %t/test.o +# RUN: %lld -arch arm64 -dylib -lSystem -flat_namespace %t/test.o -o %t/test.dylib + +# RUN: llvm-objdump --no-print-imm-hex --macho -d %t/test.dylib | FileCheck %s + +## With -flat_namespace, _target_func is interposable so regular calls go +## through stubs. But the branch with addend must go to the actual function +## address + addend, not stub + addend. +## +## Note: This means `bl _target_func` and `bl _target_func+16` could target +## different functions if interposition occurs at runtime. This is intentional: +## branching to an interior point implies reliance on the original function's +## layout, which an interposed replacement wouldn't preserve. There's no +## meaningful way to "interpose" an interior offset, so we target the original. + +## _target_func layout: +## offset 0: nop +## offset 4: nop +## offset 8: nop +## offset 12: nop +## offset 16: mov w0, #42 <- this is what _target_func+16 should reach +## offset 20: ret + +## Verify _target_func layout and capture the address of the mov instruction +## (which is at _target_func + 16) +# CHECK-LABEL: _target_func: +# CHECK: nop +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: [[#%x,INTERIOR:]]:{{.*}}mov w0, #42 +# CHECK-NEXT: ret + +## Verify the caller structure: +## - First bl goes to stub (marked with "symbol stub for:") +## - Second bl goes to [[INTERIOR]] (the _target_func+16 address captured above) +## +## The key assertion: the second bl MUST target _target_func+16 (INTERIOR), +## NOT stub+16. If the bug exists, it would target stub+16 which would be +## garbage (pointing past the stub section). +# CHECK-LABEL: _caller: +# CHECK: bl {{.*}} symbol stub for: _target_func +# CHECK-NEXT: bl 0x[[#INTERIOR]] +# CHECK-NEXT: ret + +.text +.globl _target_func, _caller +.p2align 2 + +_target_func: + ## 4 nops = 16 bytes to offset 0x10 + nop + nop + nop + nop + ## This is at _target_func + 16 + mov w0, #42 + ret + +_caller: + ## Regular call to _target_func - goes through stub due to -flat_namespace + bl _target_func + ## Branch with addend - must go to actual function + 16, not stub + 16 + bl _target_func + 16 + ret + +.subsections_via_symbols diff --git a/lld/test/wasm/Inputs/import-attributes.s b/lld/test/wasm/Inputs/import-attributes.s deleted file mode 100644 index 031d472a2e20d..0000000000000 --- a/lld/test/wasm/Inputs/import-attributes.s +++ /dev/null @@ -1,9 +0,0 @@ -.functype foo () -> () - - .globl call_foo -call_foo: - .functype call_foo () -> () - call foo - end_function - - .import_module foo, baz diff --git a/lld/test/wasm/import-attribute-mismatch.s b/lld/test/wasm/import-attribute-mismatch.s index 59988dc62f087..81ad8fef322ff 100644 --- a/lld/test/wasm/import-attribute-mismatch.s +++ b/lld/test/wasm/import-attribute-mismatch.s @@ -1,17 +1,58 @@ -# RUN: llvm-mc -filetype=obj -triple=wasm32-unknown-unknown -o %t1.o %s -# RUN: llvm-mc -filetype=obj -triple=wasm32-unknown-unknown %S/Inputs/import-attributes.s -o %t2.o -# RUN: not wasm-ld --export call_foo --allow-undefined -o %t.wasm %t1.o %t2.o 2>&1 | FileCheck %s +# RUN: split-file %s %t +# RUN: llvm-mc -filetype=obj -triple=wasm32-unknown-unknown -mattr=+reference-types -mattr=+exception-handling -o %t/main.o %t/main.s +# RUN: llvm-mc -filetype=obj -triple=wasm32-unknown-unknown -mattr=+reference-types -mattr=+exception-handling -o %t/other.o %t/other.s +# RUN: not wasm-ld --export call_foo --allow-undefined -o %t.wasm %t/main.o %t/other.o 2>&1 | FileCheck %s + +#--- main.s .functype foo () -> () +.tabletype mytable, funcref +.globaltype myglobal, i32 +.globaltype myglobal, i32 +.tagtype mytag i32 - .globl _start +.globl _start _start: .functype _start () -> () - call foo + i32.const foo + call_indirect mytable, () -> () + global.get myglobal + throw mytag end_function -.import_module foo, bar +#--- other.s + +.functype foo () -> () +.globaltype myglobal, i32 +.tabletype mytable, funcref +.tagtype mytag i32 + +.globl call_foo +call_foo: + .functype call_foo () -> () + i32.const foo + call_indirect mytable, () -> () + global.get myglobal + throw mytag + end_function + +.import_module foo, mod1 +.import_module mytable, mod2 +.import_module myglobal, mod3 +.import_module mytag, mod4 # CHECK: wasm-ld: error: import module mismatch for symbol: foo -# CHECK: >>> defined as bar in {{.*}}1.o -# CHECK: >>> defined as baz in {{.*}}2.o +# CHECK-NEXT: >>> defined as env in {{.*}}main.o +# CHECK-NEXT: >>> defined as mod1 in {{.*}}other.o + +# CHECK: wasm-ld: error: import module mismatch for symbol: mytable +# CHECK-NEXT: >>> defined as env in {{.*}}main.o +# CHECK-NEXT: >>> defined as mod2 in {{.*}}other.o + +# CHECK: wasm-ld: error: import module mismatch for symbol: myglobal +# CHECK-NEXT: >>> defined as env in {{.*}}main.o +# CHECK-NEXT: >>> defined as mod3 in {{.*}}other.o + +# CHECK: wasm-ld: error: import module mismatch for symbol: mytag +# CHECK-NEXT: >>> defined as env in {{.*}}main.o +# CHECK-NEXT: >>> defined as mod4 in {{.*}}other.o diff --git a/lld/wasm/OutputSections.cpp b/lld/wasm/OutputSections.cpp index 8ccd38f7895cb..d6348e459d31e 100644 --- a/lld/wasm/OutputSections.cpp +++ b/lld/wasm/OutputSections.cpp @@ -232,7 +232,7 @@ void CustomSection::finalizeInputSections() { return; mergedSection->finalizeContents(); - inputSections = newSections; + inputSections = std::move(newSections); } void CustomSection::finalizeContents() { diff --git a/lld/wasm/SymbolTable.cpp b/lld/wasm/SymbolTable.cpp index 01c2839a78c9e..011e4341519cd 100644 --- a/lld/wasm/SymbolTable.cpp +++ b/lld/wasm/SymbolTable.cpp @@ -738,7 +738,7 @@ Symbol *SymbolTable::addUndefinedGlobal(StringRef name, else if (s->isDefined()) checkGlobalType(s, file, type); else - updateExistingUndefined(s, flags, file); + updateExistingUndefined(s, flags, file, importName, importModule); return s; } @@ -764,7 +764,7 @@ Symbol *SymbolTable::addUndefinedTable(StringRef name, else if (s->isDefined()) checkTableType(s, file, type); else - updateExistingUndefined(s, flags, file); + updateExistingUndefined(s, flags, file, importName, importModule); return s; } @@ -790,7 +790,7 @@ Symbol *SymbolTable::addUndefinedTag(StringRef name, else if (s->isDefined()) checkTagType(s, file, sig); else - updateExistingUndefined(s, flags, file); + updateExistingUndefined(s, flags, file, importName, importModule); return s; } diff --git a/lld/wasm/Writer.cpp b/lld/wasm/Writer.cpp index a184cdbdfefa8..40a5832056087 100644 --- a/lld/wasm/Writer.cpp +++ b/lld/wasm/Writer.cpp @@ -1109,7 +1109,7 @@ void Writer::combineOutputSegments() { } } - segments = newSegments; + segments = std::move(newSegments); } static void createFunction(DefinedFunction *func, StringRef bodyContent) { diff --git a/lldb/bindings/interface/SBExpressionOptionsDocstrings.i b/lldb/bindings/interface/SBExpressionOptionsDocstrings.i index 2bb562778db79..827a5eced6461 100644 --- a/lldb/bindings/interface/SBExpressionOptionsDocstrings.i +++ b/lldb/bindings/interface/SBExpressionOptionsDocstrings.i @@ -61,3 +61,9 @@ %feature("docstring", "Sets whether to JIT an expression if it cannot be interpreted." ) lldb::SBExpressionOptions::SetAllowJIT; + +%feature("docstring", "Sets language-plugin specific boolean option for expression evaluation. LLDB currently doesn't validate whether the option being set is understood by the expression evaluator." +) lldb::SBExpressionOptions::SetBooleanLanguageOption; + +%feature("docstring", "Gets language-plugin specific boolean option for expression evaluation. LLDB currently doesn't validate whether the option being retrieved is one that is understood by the expression evaluator." +) lldb::SBExpressionOptions::GetBooleanLanguageOption; diff --git a/lldb/docs/index.rst b/lldb/docs/index.rst index 3f6e17fd5e6fb..10683c7593b01 100644 --- a/lldb/docs/index.rst +++ b/lldb/docs/index.rst @@ -73,7 +73,8 @@ are welcome: * iOS, tvOS, and watchOS simulator debugging on i386, x86_64 and AArch64 * iOS, tvOS, and watchOS device debugging on ARM and AArch64 * Linux user-space debugging for i386, x86_64, ARM, AArch64, PPC64le, s390x -* FreeBSD user-space debugging for i386, x86_64, ARM, AArch64, MIPS64, PPC +* FreeBSD user-space debugging for i386, x86_64, ARM, AArch64, PPC +* FreeBSD kernel debugging for i386, x86_64, AArch64 * NetBSD user-space debugging for i386 and x86_64 * Windows user-space debugging for i386, x86_64, ARM and AArch64 (*) diff --git a/lldb/include/lldb/API/SBExpressionOptions.h b/lldb/include/lldb/API/SBExpressionOptions.h index a9e929a4c0bd9..edfdbb5aaf62f 100644 --- a/lldb/include/lldb/API/SBExpressionOptions.h +++ b/lldb/include/lldb/API/SBExpressionOptions.h @@ -107,6 +107,10 @@ class LLDB_API SBExpressionOptions { // Sets whether we will JIT an expression if it cannot be interpreted void SetAllowJIT(bool allow); + bool GetBooleanLanguageOption(const char *option_name, SBError &error) const; + + SBError SetBooleanLanguageOption(const char *option_name, bool value); + protected: lldb_private::EvaluateExpressionOptions *get() const; diff --git a/lldb/include/lldb/Core/Module.h b/lldb/include/lldb/Core/Module.h index 10c5982ac3c2b..f46b3a13f4f18 100644 --- a/lldb/include/lldb/Core/Module.h +++ b/lldb/include/lldb/Core/Module.h @@ -1102,8 +1102,6 @@ class Module : public std::enable_shared_from_this, bool SetArchitecture(const ArchSpec &new_arch); - void SetUUID(const lldb_private::UUID &uuid); - SectionList *GetUnifiedSectionList(); friend class ModuleList; diff --git a/lldb/include/lldb/Core/ModuleList.h b/lldb/include/lldb/Core/ModuleList.h index dd17f7558e2b4..6f7224fdeb0b3 100644 --- a/lldb/include/lldb/Core/ModuleList.h +++ b/lldb/include/lldb/Core/ModuleList.h @@ -81,6 +81,8 @@ class ModuleListProperties : public Properties { bool SetClangModulesCachePath(const FileSpec &path); bool GetEnableExternalLookup() const; bool SetEnableExternalLookup(bool new_value); + bool GetSharedCacheBinaryLoading() const; + bool SetSharedCacheBinaryLoading(bool new_value); bool GetEnableLLDBIndexCache() const; bool SetEnableLLDBIndexCache(bool new_value); uint64_t GetLLDBIndexCacheMaxByteSize(); diff --git a/lldb/source/DataFormatters/FormatterBytecode.def b/lldb/include/lldb/DataFormatters/FormatterBytecode.def similarity index 100% rename from lldb/source/DataFormatters/FormatterBytecode.def rename to lldb/include/lldb/DataFormatters/FormatterBytecode.def diff --git a/lldb/source/DataFormatters/FormatterBytecode.h b/lldb/include/lldb/DataFormatters/FormatterBytecode.h similarity index 94% rename from lldb/source/DataFormatters/FormatterBytecode.h rename to lldb/include/lldb/DataFormatters/FormatterBytecode.h index 21454d9c7e231..41f999196b47f 100644 --- a/lldb/source/DataFormatters/FormatterBytecode.h +++ b/lldb/include/lldb/DataFormatters/FormatterBytecode.h @@ -6,6 +6,9 @@ // //===----------------------------------------------------------------------===// +#ifndef LLDB_DATAFORMATTERS_FORMATTERBYTECODE_H +#define LLDB_DATAFORMATTERS_FORMATTERBYTECODE_H + #include "lldb/DataFormatters/TypeSummary.h" #include "lldb/Symbol/CompilerType.h" @@ -62,3 +65,5 @@ std::string toString(FormatterBytecode::Selectors sel); std::string toString(FormatterBytecode::Signatures sig); } // namespace lldb_private + +#endif diff --git a/lldb/include/lldb/Expression/UserExpression.h b/lldb/include/lldb/Expression/UserExpression.h index 2fde73dafa035..977a0adef1cbe 100644 --- a/lldb/include/lldb/Expression/UserExpression.h +++ b/lldb/include/lldb/Expression/UserExpression.h @@ -313,6 +313,16 @@ class UserExpression : public Expression { lldb::ProcessSP &process_sp, lldb::StackFrameSP &frame_sp); + /// Called by expression evaluator when a parse error occurs. Gives this + /// UserExpression object a chance to inspect and adjust the error diagnostics + /// contained in the specified \c diagnostic_manager. + /// + /// \param[in,out] diagnostic_manager DiagnosticManager manager holding the + /// parse error diagnostics. This function may mutate the diagnostics. + /// + virtual void + FixupParseErrorDiagnostics(DiagnosticManager &diagnostic_manager) const {} + /// The address the process is stopped in. Address m_address; /// The text of the expression, as typed by the user. diff --git a/lldb/include/lldb/Host/HostInfoBase.h b/lldb/include/lldb/Host/HostInfoBase.h index 670fee19fca3d..149810ff53924 100644 --- a/lldb/include/lldb/Host/HostInfoBase.h +++ b/lldb/include/lldb/Host/HostInfoBase.h @@ -10,6 +10,7 @@ #define LLDB_HOST_HOSTINFOBASE_H #include "lldb/Utility/ArchSpec.h" +#include "lldb/Utility/DataExtractor.h" #include "lldb/Utility/FileSpec.h" #include "lldb/Utility/UUID.h" #include "lldb/Utility/UserIDResolver.h" @@ -28,8 +29,38 @@ namespace lldb_private { class FileSpec; struct SharedCacheImageInfo { - UUID uuid; - lldb::DataExtractorSP extractor_sp; + SharedCacheImageInfo() + : m_uuid(), m_extractor_sp(), m_create_data_extractor(nullptr), + m_image_baton(nullptr) {} + SharedCacheImageInfo(UUID uuid, lldb::DataExtractorSP extractor_sp) + : m_uuid(uuid), m_extractor_sp(extractor_sp), + m_create_data_extractor(nullptr), m_image_baton(nullptr) {} + SharedCacheImageInfo( + UUID uuid, lldb::DataExtractorSP (*create_data_extractor)(void *image), + void *image_baton) + : m_uuid(uuid), m_extractor_sp(), + m_create_data_extractor(create_data_extractor), + m_image_baton(image_baton) {} + + lldb::DataExtractorSP GetExtractor() { + if (!m_extractor_sp && m_image_baton) + m_extractor_sp = m_create_data_extractor(m_image_baton); + return m_extractor_sp; + } + const UUID &GetUUID() const { return m_uuid; } + void *GetImageBaton(); + void SetExtractor(lldb::DataExtractorSP extractor_sp) { + m_extractor_sp = extractor_sp; + } + void SetImageBaton(void *image_baton) { m_image_baton = image_baton; } + void SetDataExtractorCreateFunction( + lldb::DataExtractorSP (*create_data_extractor)(void *image)); + +private: + UUID m_uuid; + lldb::DataExtractorSP m_extractor_sp; + lldb::DataExtractorSP (*m_create_data_extractor)(void *image); + void *m_image_baton; }; namespace { diff --git a/lldb/include/lldb/Host/HostThread.h b/lldb/include/lldb/Host/HostThread.h index c969492f5b20a..28ccc629d4220 100644 --- a/lldb/include/lldb/Host/HostThread.h +++ b/lldb/include/lldb/Host/HostThread.h @@ -42,6 +42,7 @@ class HostThread { lldb::thread_result_t GetResult() const; bool EqualsThread(lldb::thread_t thread) const; + bool EqualsThread(const HostThread &thread) const; bool HasThread() const; diff --git a/lldb/include/lldb/Host/JSONTransport.h b/lldb/include/lldb/Host/JSONTransport.h index bd41d077c903b..6b114ee497a8b 100644 --- a/lldb/include/lldb/Host/JSONTransport.h +++ b/lldb/include/lldb/Host/JSONTransport.h @@ -166,8 +166,7 @@ class JSONTransport { /// /// If an unexpected error occurs, the MainLoop will be terminated and a log /// message will include additional information about the termination reason. - virtual llvm::Expected - RegisterMessageHandler(MainLoop &loop, MessageHandler &handler) = 0; + virtual llvm::Error RegisterMessageHandler(MessageHandler &handler) = 0; protected: template inline auto Logv(const char *Fmt, Ts &&...Vals) { @@ -182,29 +181,27 @@ template class IOTransport : public JSONTransport { using Message = typename JSONTransport::Message; using MessageHandler = typename JSONTransport::MessageHandler; - IOTransport(lldb::IOObjectSP in, lldb::IOObjectSP out) - : m_in(in), m_out(out) {} + IOTransport(MainLoop &loop, lldb::IOObjectSP in, lldb::IOObjectSP out) + : m_loop(loop), m_in(in), m_out(out) {} llvm::Error Send(const typename Proto::Evt &evt) override { return Write(evt); } + llvm::Error Send(const typename Proto::Req &req) override { return Write(req); } + llvm::Error Send(const typename Proto::Resp &resp) override { return Write(resp); } - llvm::Expected - RegisterMessageHandler(MainLoop &loop, MessageHandler &handler) override { + llvm::Error RegisterMessageHandler(MessageHandler &handler) override { Status status; - MainLoop::ReadHandleUP read_handle = loop.RegisterReadObject( + m_read_handle = m_loop.RegisterReadObject( m_in, [this, &handler](MainLoopBase &base) { OnRead(base, handler); }, status); - if (status.Fail()) { - return status.takeError(); - } - return read_handle; + return status.takeError(); } /// Public for testing purposes, otherwise this should be an implementation @@ -263,11 +260,15 @@ template class IOTransport : public JSONTransport { handler.OnError(llvm::make_error( std::string(m_buffer.str()))); handler.OnClosed(); + // On EOF, remove the read handle from the MainLoop. + m_read_handle.reset(); } } + MainLoop &m_loop; lldb::IOObjectSP m_in; lldb::IOObjectSP m_out; + MainLoop::ReadHandleUP m_read_handle; }; /// A transport class for JSON with a HTTP header. diff --git a/lldb/include/lldb/Protocol/MCP/Server.h b/lldb/include/lldb/Protocol/MCP/Server.h index f185d51f41192..498c54bed780e 100644 --- a/lldb/include/lldb/Protocol/MCP/Server.h +++ b/lldb/include/lldb/Protocol/MCP/Server.h @@ -21,6 +21,7 @@ #include "llvm/Support/FormatVariadic.h" #include "llvm/Support/JSON.h" #include "llvm/Support/Signals.h" +#include #include #include #include @@ -40,7 +41,7 @@ class Server { void AddTool(std::unique_ptr tool); void AddResourceProvider(std::unique_ptr resource_provider); - llvm::Error Accept(lldb_private::MainLoop &, MCPTransportUP); + llvm::Error Accept(MCPTransportUP); protected: MCPBinderUP Bind(MCPTransport &); @@ -70,7 +71,6 @@ class Server { LogCallback m_log_callback; struct Client { - ReadHandleUP handle; MCPTransportUP transport; MCPBinderUP binder; }; diff --git a/lldb/include/lldb/Protocol/MCP/Transport.h b/lldb/include/lldb/Protocol/MCP/Transport.h index b7a1eb778d660..ceadf1dbd82b8 100644 --- a/lldb/include/lldb/Protocol/MCP/Transport.h +++ b/lldb/include/lldb/Protocol/MCP/Transport.h @@ -83,8 +83,8 @@ using LogCallback = llvm::unique_function; class Transport final : public lldb_private::transport::JSONRPCTransport { public: - Transport(lldb::IOObjectSP in, lldb::IOObjectSP out, - LogCallback log_callback = {}); + Transport(lldb_private::MainLoop &loop, lldb::IOObjectSP in, + lldb::IOObjectSP out, LogCallback log_callback = {}); virtual ~Transport() = default; /// Transport is not copyable. diff --git a/lldb/include/lldb/Symbol/CompilerType.h b/lldb/include/lldb/Symbol/CompilerType.h index 869c5076ee0a7..5f152b6f26a89 100644 --- a/lldb/include/lldb/Symbol/CompilerType.h +++ b/lldb/include/lldb/Symbol/CompilerType.h @@ -144,7 +144,13 @@ class CompilerType { bool IsDefined() const; - bool IsFloatingPointType(bool &is_complex) const; + bool IsComplexType() const; + + /// Returns \c true for floating point types (including complex floats). + bool IsFloatingPointType() const; + + /// Returns \c true for non-complex float types. + bool IsRealFloatingPointType() const; bool IsFunctionType() const; @@ -199,8 +205,6 @@ class CompilerType { /// This is used when you don't care about the signedness of the integer. bool IsInteger() const; - bool IsFloat() const; - /// This is used when you don't care about the signedness of the enum. bool IsEnumerationType() const; diff --git a/lldb/include/lldb/Symbol/TypeSystem.h b/lldb/include/lldb/Symbol/TypeSystem.h index 99ea0585e5370..d7f4cfcf0ffc7 100644 --- a/lldb/include/lldb/Symbol/TypeSystem.h +++ b/lldb/include/lldb/Symbol/TypeSystem.h @@ -162,8 +162,7 @@ class TypeSystem : public PluginInterface, virtual bool IsDefined(lldb::opaque_compiler_type_t type) = 0; - virtual bool IsFloatingPointType(lldb::opaque_compiler_type_t type, - bool &is_complex) = 0; + virtual bool IsFloatingPointType(lldb::opaque_compiler_type_t type) = 0; virtual bool IsFunctionType(lldb::opaque_compiler_type_t type) = 0; diff --git a/lldb/include/lldb/Target/ExecutionContext.h b/lldb/include/lldb/Target/ExecutionContext.h index 8637234c4fb95..47bcd729abcdd 100644 --- a/lldb/include/lldb/Target/ExecutionContext.h +++ b/lldb/include/lldb/Target/ExecutionContext.h @@ -13,10 +13,13 @@ #include "lldb/Host/ProcessRunLock.h" #include "lldb/Target/StackID.h" +#include "lldb/Target/SyntheticFrameProvider.h" #include "lldb/lldb-private.h" namespace lldb_private { +struct StoppedExecutionContext; + //===----------------------------------------------------------------------===// /// Execution context objects refer to objects in the execution of the program /// that is being debugged. The consist of one or more of the following @@ -270,9 +273,12 @@ class ExecutionContextRef { void ClearFrame() { m_stack_id.Clear(); - m_frame_list_wp.reset(); + m_frame_list_id.reset(); } + friend llvm::Expected + GetStoppedExecutionContext(const ExecutionContextRef *exe_ctx_ref_ptr); + protected: // Member variables lldb::TargetWP m_target_wp; ///< A weak reference to a target @@ -283,13 +289,10 @@ class ExecutionContextRef { /// backing object changes StackID m_stack_id; ///< The stack ID that this object refers to in case the ///< backing object changes - mutable lldb::StackFrameListWP - m_frame_list_wp; ///< Weak reference to the - ///< frame list that contains - ///< this frame. If we can create a valid - ///< StackFrameListSP from it, we must use it to resolve - ///< the StackID, otherwise, we should ask the Thread's - ///< StackFrameList. + /// A map of identifiers to scripted frame providers used in this thread. + mutable std::optional< + std::pair> + m_frame_list_id; }; /// \class ExecutionContext ExecutionContext.h diff --git a/lldb/include/lldb/Target/Process.h b/lldb/include/lldb/Target/Process.h index 8614347d1f34a..7a15adebc63ee 100644 --- a/lldb/include/lldb/Target/Process.h +++ b/lldb/include/lldb/Target/Process.h @@ -2016,9 +2016,20 @@ class Process : public std::enable_shared_from_this, /// the instruction has completed executing. bool GetWatchpointReportedAfter(); - lldb::ModuleSP ReadModuleFromMemory(const FileSpec &file_spec, - lldb::addr_t header_addr, - size_t size_to_read = 512); + /// Creates and populates a module using an in-memory object file. + /// + /// \param[in] file_spec + /// The name or path to the module file. May be empty. + /// + /// \param[in] header_addr + /// The address pointing to the beginning of the object file's header. + /// + /// \param[in] size_to_read + /// The number of bytes to read from memory. This should be large enough to + /// identify the object file format. Defaults to 512. + llvm::Expected + ReadModuleFromMemory(const FileSpec &file_spec, lldb::addr_t header_addr, + size_t size_to_read = 512); /// Attempt to get the attributes for a region of memory in the process. /// @@ -2999,8 +3010,6 @@ void PruneThreadPlans(); return lldb::ThreadSP(); } - lldb::StateType GetPrivateState(); - /// The "private" side of resuming a process. This doesn't alter the state /// of m_run_lock, but just causes the process to resume. /// @@ -3064,10 +3073,14 @@ void PruneThreadPlans(); std::string m_exit_string; }; - bool PrivateStateThreadIsValid() const { - lldb::StateType state = m_private_state.GetValue(); + bool PrivateStateThreadIsRunning() const { + if (!m_current_private_state_thread || + !m_current_private_state_thread->IsRunning()) + return false; + + lldb::StateType state = m_current_private_state_thread->GetPrivateState(); return state != lldb::eStateInvalid && state != lldb::eStateDetached && - state != lldb::eStateExited && m_private_state_thread.IsJoinable(); + state != lldb::eStateExited; } void ForceNextEventDelivery() { m_force_next_event_delivery = true; } @@ -3185,12 +3198,176 @@ void PruneThreadPlans(); } }; + /// The PrivateStateThread struct gathers all the bits of state needed to + /// manage handling Process events, from receiving them on the Private State + /// to signaling when process events are broadcase publicly, to determining + /// when various actors can act on the process. It also holds the current + /// private state thread. + /// These need to be swappable as a group to manage the temporary modal + /// private state thread that we spin up when we need to run an expression on + /// the private state thread. + struct PrivateStateThread { + PrivateStateThread( + Process &process, lldb::StateType public_state, + lldb::StateType private_state, + bool is_secondary_thread, // FIXME: Can I get rid of this? + llvm::StringRef thread_name) + : m_process(process), m_public_state(public_state), + m_private_state(private_state), + m_is_secondary_thread(is_secondary_thread), + m_thread_name(thread_name) {} + // This returns false if we couldn't start up the thread. If that happens, + // you won't be doing any debugging today. + bool StartupThread(); + + bool IsOnThread(const HostThread &thread) const; + + bool IsJoinable() { return m_private_state_thread.IsJoinable(); } + + void JoinAndReset() { + lldb::thread_result_t result = {}; + m_private_state_thread.Join(&result); + m_private_state_thread.Reset(); + m_is_running = false; + } + + bool IsRunning() { return m_is_running; } + + void SetThreadName(llvm::StringRef new_name) { m_thread_name = new_name; } + + lldb::StateType GetPrivateState() const { + return m_private_state.GetValue(); + } + + lldb::StateType GetPublicState() const { return m_public_state.GetValue(); } + + void SetPublicState(lldb::StateType new_value) { + m_public_state.SetValue(new_value); + } + + void SetPrivateState(lldb::StateType new_value) { + m_private_state.SetValue(new_value); + } + + std::recursive_mutex &GetPrivateStateMutex() { + return m_private_state.GetMutex(); + } + + lldb::StateType GetPrivateStateNoLock() const { + return m_private_state.GetValueNoLock(); + } + + void SetPrivateStateNoLock(lldb::StateType new_state) { + m_private_state.SetValueNoLock(new_state); + } + + void SetPublicStateNoLock(lldb::StateType new_state) { + m_public_state.SetValueNoLock(new_state); + } + + bool SetPublicRunLockToRunning() { return m_public_run_lock.SetRunning(); } + + bool SetPrivateRunLockToRunning() { + return m_private_run_lock.SetRunning(); + } + + bool SetPublicRunLockToStopped() { return m_public_run_lock.SetStopped(); } + + bool SetPrivateRunLockToStopped() { + return m_private_run_lock.SetStopped(); + } + + ProcessRunLock &GetRunLock() { + if (IsOnThread(Host::GetCurrentThread())) + return m_private_run_lock; + else + return m_public_run_lock; + } + + Process &m_process; + ///< The process state that we show to client code. This will often differ + ///< from the actual process state, for instance when we've stopped in the + ///< middle of a ThreadPlan's operations, before we've decided to stop or + ///< continue. + ThreadSafeValue m_public_state; + ///< The actual state of our process + ThreadSafeValue m_private_state; + ///< HostThread for the thread that watches for internal state events + HostThread m_private_state_thread; + //< These are the locks that client code acquires both to wait on the + //< process stopping, and then to ensure that it stays in the stopped state + //< while the client code is operating on it. Again, we need a parallel + //set, < one for public client code and one for code working on behalf of + //the < private state management. + ProcessRunLock m_public_run_lock; + ProcessRunLock m_private_run_lock; + bool m_is_running = false; + /// If we need to run an expression modally in the private state thread, we + /// have to spin up a secondary private state thread to manage the events + /// that drive that interaction. This will be true if this is a modal + /// private state thread. + bool m_is_secondary_thread; + ///< This will be the thread name given to the Private State HostThread when + ///< it gets spun up. + std::string m_thread_name; + }; + + bool SetPrivateRunLockToStopped() { + assert(m_current_private_state_thread); + if (m_current_private_state_thread) + return m_current_private_state_thread->SetPrivateRunLockToStopped(); + return false; + } + bool SetPrivateRunLockToRunning() { + assert(m_current_private_state_thread); + if (m_current_private_state_thread) + return m_current_private_state_thread->SetPrivateRunLockToStopped(); + return false; + } + bool SetPublicRunLockToStopped() { + assert(m_current_private_state_thread); + if (m_current_private_state_thread) + return m_current_private_state_thread->SetPublicRunLockToStopped(); + return false; + } + bool SetPublicRunLockToRunning() { + assert(m_current_private_state_thread); + if (m_current_private_state_thread) + return m_current_private_state_thread->SetPublicRunLockToRunning(); + return false; + } + + std::recursive_mutex &GetPrivateStateMutex() { + assert(m_current_private_state_thread); + return m_current_private_state_thread->GetPrivateStateMutex(); + } + + lldb::StateType GetPublicState() const { + if (!m_current_private_state_thread) + return lldb::eStateUnloaded; + return m_current_private_state_thread->GetPublicState(); + } + + lldb::StateType GetPrivateState() const { + if (!m_current_private_state_thread) + return lldb::eStateUnloaded; + return m_current_private_state_thread->GetPrivateState(); + } + + lldb::StateType GetPrivateStateNoLock() const { + if (!m_current_private_state_thread) + return lldb::eStateUnloaded; + return m_current_private_state_thread->GetPrivateStateNoLock(); + } + + void SetPrivateStateNoLock(lldb::StateType new_state) { + assert(m_current_private_state_thread); + m_current_private_state_thread->SetPrivateStateNoLock(new_state); + } + // Member variables std::weak_ptr m_target_wp; ///< The target that owns this process. lldb::pid_t m_pid = LLDB_INVALID_PROCESS_ID; - ThreadSafeValue m_public_state; - ThreadSafeValue - m_private_state; // The actual state of our process Broadcaster m_private_state_broadcaster; // This broadcaster feeds state // changed events into the private // state thread's listener. @@ -3200,8 +3377,13 @@ void PruneThreadPlans(); // private state thread. lldb::ListenerSP m_private_state_listener_sp; // This is the listener for the // private state thread. - HostThread m_private_state_thread; ///< Thread ID for the thread that watches - ///internal state events + ///< This is filled on construction with the "main" private state which will + ///< be exposed to clients of this process. It won't have a running private + ///< state thread until you call StartupThread. This needs to be a pointer + ///< so I can transparently swap it out for the modal one, but there will + ///< always be a private state thread in this slot. + PrivateStateThread *m_current_private_state_thread; + ProcessModID m_mod_id; ///< Tracks the state of the process over stops and ///other alterations. uint32_t m_process_unique_id; ///< Each lldb_private::Process class that is @@ -3276,8 +3458,6 @@ void PruneThreadPlans(); InstrumentationRuntimeCollection m_instrumentation_runtimes; std::unique_ptr m_next_event_action_up; std::vector m_pre_resume_actions; - ProcessRunLock m_public_run_lock; - ProcessRunLock m_private_run_lock; bool m_currently_handling_do_on_removals; bool m_resume_requested; // If m_currently_handling_event or // m_currently_handling_do_on_removals are true, @@ -3348,7 +3528,11 @@ void PruneThreadPlans(); void SetPrivateState(lldb::StateType state); - bool StartPrivateStateThread(bool is_secondary_thread = false); + // Starts the private state thread and assigns it to + // m_current_private_state_thread. Clients who are making a secondary thread + // for now have to manage backing that up by hand. + bool StartPrivateStateThread(lldb::StateType state, bool run_lock_is_running, + bool is_secondary_thread = false); void StopPrivateStateThread(); @@ -3362,7 +3546,7 @@ void PruneThreadPlans(); // temporarily spin up a secondary state thread to handle events from a hand- // called function on the primary private state thread. - lldb::thread_result_t RunPrivateStateThread(bool is_secondary_thread); + lldb::thread_result_t RunPrivateStateThread(); protected: void HandlePrivateEvent(lldb::EventSP &event_sp); diff --git a/lldb/include/lldb/Target/StackFrame.h b/lldb/include/lldb/Target/StackFrame.h index 46922448d6e59..5cba9afe2a7e8 100644 --- a/lldb/include/lldb/Target/StackFrame.h +++ b/lldb/include/lldb/Target/StackFrame.h @@ -542,17 +542,17 @@ class StackFrame : public ExecutionContextScope, virtual lldb::RecognizedStackFrameSP GetRecognizedFrame(); - /// Get the StackFrameList that contains this frame. + /// Get the identifier of the StackFrameList that contains this frame. /// - /// Returns the StackFrameList that contains this frame, allowing + /// Returns the StackFrameList identifier that contains this frame, allowing /// frames to resolve execution contexts without calling /// Thread::GetStackFrameList(), which can cause circular dependencies /// during frame provider initialization. /// /// \return - /// The StackFrameList that contains this frame, or nullptr if not set. - virtual lldb::StackFrameListSP GetContainingStackFrameList() const { - return m_frame_list_wp.lock(); + /// The identifier of the containing StackFrameList + lldb::frame_list_id_t GetContainingStackFrameListIdentifier() const { + return m_frame_list_id; } protected: @@ -598,8 +598,8 @@ class StackFrame : public ExecutionContextScope, /// be the first address of its function). True for actual frame zero as /// well as any other frame with the same trait. bool m_behaves_like_zeroth_frame; + lldb::frame_list_id_t m_frame_list_id = 0; lldb::VariableListSP m_variable_list_sp; - lldb::StackFrameListWP m_frame_list_wp; /// Value objects for each variable in m_variable_list_sp. ValueObjectList m_variable_list_value_objects; std::optional m_recognized_frame_sp; diff --git a/lldb/include/lldb/Target/StackFrameList.h b/lldb/include/lldb/Target/StackFrameList.h index c096fe3ff61a0..715781abb83a3 100644 --- a/lldb/include/lldb/Target/StackFrameList.h +++ b/lldb/include/lldb/Target/StackFrameList.h @@ -24,7 +24,8 @@ class StackFrameList : public std::enable_shared_from_this { public: // Constructors and Destructors StackFrameList(Thread &thread, const lldb::StackFrameListSP &prev_frames_sp, - bool show_inline_frames); + bool show_inline_frames, + lldb::frame_list_id_t provider_id = 0); virtual ~StackFrameList(); @@ -104,6 +105,9 @@ class StackFrameList : public std::enable_shared_from_this { /// Get the thread associated with this frame list. Thread &GetThread() const { return m_thread; } + /// Get the unique identifier for this frame list. + lldb::frame_list_id_t GetIdentifier() const { return m_identifier; } + protected: friend class Thread; friend class ScriptedFrameProvider; @@ -212,6 +216,9 @@ class StackFrameList : public std::enable_shared_from_this { /// Whether or not to show synthetic (inline) frames. Immutable. const bool m_show_inlined_frames; + /// Unique identifier for this frame list instance. + lldb::frame_list_id_t m_identifier = 0; + /// Returns true if fetching frames was interrupted, false otherwise. virtual bool FetchFramesUpTo(uint32_t end_idx, InterruptionControl allow_interrupt); @@ -244,7 +251,8 @@ class SyntheticStackFrameList : public StackFrameList { SyntheticStackFrameList(Thread &thread, lldb::StackFrameListSP input_frames, const lldb::StackFrameListSP &prev_frames_sp, bool show_inline_frames, - lldb::SyntheticFrameProviderSP provider_sp); + lldb::SyntheticFrameProviderSP provider_sp, + uint64_t provider_id); protected: /// Override FetchFramesUpTo to lazily return frames from the provider diff --git a/lldb/include/lldb/Target/Target.h b/lldb/include/lldb/Target/Target.h index 812a638910b3b..4f5b022765f9e 100644 --- a/lldb/include/lldb/Target/Target.h +++ b/lldb/include/lldb/Target/Target.h @@ -38,6 +38,7 @@ #include "lldb/Utility/Broadcaster.h" #include "lldb/Utility/LLDBAssert.h" #include "lldb/Utility/RealpathPrefixes.h" +#include "lldb/Utility/StructuredData.h" #include "lldb/Utility/Timeout.h" #include "lldb/lldb-public.h" #include "llvm/ADT/StringRef.h" @@ -307,6 +308,8 @@ class TargetProperties : public Properties { class EvaluateExpressionOptions { public: + EvaluateExpressionOptions(); + // MSVC has a bug here that reports C4268: 'const' static/global data // initialized with compiler generated default constructor fills the object // with zeros. Confirmed that MSVC is *not* zero-initializing, it's just a @@ -323,8 +326,6 @@ class EvaluateExpressionOptions { static constexpr ExecutionPolicy default_execution_policy = eExecutionPolicyOnlyWhenNeeded; - EvaluateExpressionOptions() = default; - ExecutionPolicy GetExecutionPolicy() const { return m_execution_policy; } void SetExecutionPolicy(ExecutionPolicy policy = eExecutionPolicyAlways) { @@ -481,7 +482,26 @@ class EvaluateExpressionOptions { void SetIsForUtilityExpr(bool b) { m_running_utility_expression = b; } + /// Set language-plugin specific option called \c option_name to + /// the specified boolean \c value. + llvm::Error SetBooleanLanguageOption(llvm::StringRef option_name, bool value); + + /// Get the language-plugin specific boolean option called \c option_name. + /// + /// If the option doesn't exist or is not a boolean option, returns false. + /// Otherwise returns the boolean value of the option. + llvm::Expected + GetBooleanLanguageOption(llvm::StringRef option_name) const; + + void SetCppIgnoreContextQualifiers(bool value); + + bool GetCppIgnoreContextQualifiers() const; + private: + const StructuredData::Dictionary &GetLanguageOptions() const; + + StructuredData::Dictionary &GetLanguageOptions(); + ExecutionPolicy m_execution_policy = default_execution_policy; SourceLanguage m_language; std::string m_prefix; @@ -514,6 +534,10 @@ class EvaluateExpressionOptions { mutable std::string m_pound_line_file; mutable uint32_t m_pound_line_line = 0; + /// Dictionary mapping names of language-plugin specific options + /// to values. + StructuredData::DictionarySP m_language_options_sp = nullptr; + /// During expression evaluation, any SymbolContext in this list will be /// used for symbol/function lookup before any other context (except for /// the module corresponding to the current frame). @@ -776,6 +800,12 @@ class Target : public std::enable_shared_from_this, const llvm::DenseMap & GetScriptedFrameProviderDescriptors() const; +protected: + /// Invalidate all potentially cached frame providers for all threads + /// and trigger a stack changed event for all threads. + void InvalidateThreadFrameProviders(); + +public: // This part handles the breakpoints. BreakpointList &GetBreakpointList(bool internal = false); diff --git a/lldb/include/lldb/Target/Thread.h b/lldb/include/lldb/Target/Thread.h index bc1bec57bee5f..9cc86a37c63e5 100644 --- a/lldb/include/lldb/Target/Thread.h +++ b/lldb/include/lldb/Target/Thread.h @@ -19,6 +19,7 @@ #include "lldb/Target/ExecutionContextScope.h" #include "lldb/Target/RegisterCheckpoint.h" #include "lldb/Target/StackFrameList.h" +#include "lldb/Target/SyntheticFrameProvider.h" #include "lldb/Utility/Broadcaster.h" #include "lldb/Utility/CompletionRequest.h" #include "lldb/Utility/Event.h" @@ -26,6 +27,7 @@ #include "lldb/Utility/UnimplementedError.h" #include "lldb/Utility/UserID.h" #include "lldb/lldb-private.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/Support/MemoryBuffer.h" #define LLDB_THREAD_MAX_STOP_EXC_DATA 8 @@ -1297,12 +1299,18 @@ class Thread : public std::enable_shared_from_this, lldb::StackFrameListSP GetStackFrameList(); + /// Get a frame list by its unique identifier. + lldb::StackFrameListSP GetFrameListByIdentifier(lldb::frame_list_id_t id); + llvm::Error LoadScriptedFrameProvider(const ScriptedFrameProviderDescriptor &descriptor); + llvm::Expected + GetScriptedFrameProviderDescriptorForID(lldb::frame_list_id_t id) const; + void ClearScriptedFrameProvider(); - const llvm::SmallVector & + const llvm::DenseMap & GetFrameProviders() const { return m_frame_providers; } @@ -1384,6 +1392,8 @@ class Thread : public std::enable_shared_from_this, m_state_mutex; ///< Multithreaded protection for m_state. mutable std::recursive_mutex m_frame_mutex; ///< Multithreaded protection for m_state. + lldb::StackFrameListSP + m_unwinder_frames_sp; ///< The unwinder frame list (ID 0). lldb::StackFrameListSP m_curr_frames_sp; ///< The stack frames that get lazily ///populated after a thread stops. lldb::StackFrameListSP m_prev_frames_sp; ///< The previous stack frames from @@ -1410,8 +1420,23 @@ class Thread : public std::enable_shared_from_this, /// The Thread backed by this thread, if any. lldb::ThreadWP m_backed_thread; - /// The Scripted Frame Providers for this thread. - llvm::SmallVector m_frame_providers; + /// Map from frame list ID to its frame provider. + /// Cleared in ClearStackFrames(), repopulated in GetStackFrameList(). + llvm::DenseMap + m_frame_providers; + + /// Ordered chain of provider IDs. + /// Persists across ClearStackFrames() to maintain stable provider IDs. + std::vector> + m_provider_chain_ids; + + /// Map from frame list identifier to frame list weak pointer. + mutable llvm::DenseMap + m_frame_lists_by_id; + + /// Counter for assigning unique provider IDs. Starts at 1 since 0 is + /// reserved for normal unwinder frames. Persists across ClearStackFrames. + lldb::frame_list_id_t m_next_provider_id = 1; private: bool m_extended_info_fetched; // Have we tried to retrieve the m_extended_info diff --git a/lldb/include/lldb/Utility/DataExtractor.h b/lldb/include/lldb/Utility/DataExtractor.h index 7011fa93c2112..34c745518aa56 100644 --- a/lldb/include/lldb/Utility/DataExtractor.h +++ b/lldb/include/lldb/Utility/DataExtractor.h @@ -281,7 +281,7 @@ class DataExtractor { /// /// \return /// The total number of bytes of data this object refers to. - uint64_t GetByteSize() const { return m_end - m_start; } + virtual uint64_t GetByteSize() const { return m_end - m_start; } /// Extract a C string from \a *offset_ptr. /// @@ -858,7 +858,7 @@ class DataExtractor { return GetSubsetExtractorSP(0); } - lldb::DataBufferSP &GetSharedDataBuffer() { return m_data_sp; } + lldb::DataBufferSP GetSharedDataBuffer() const { return m_data_sp; } bool HasData() { return m_start && m_end && m_end - m_start > 0; } @@ -922,8 +922,8 @@ class DataExtractor { /// /// \return /// The number of bytes that this object now contains. - lldb::offset_t SetData(const void *bytes, lldb::offset_t length, - lldb::ByteOrder byte_order); + virtual lldb::offset_t SetData(const void *bytes, lldb::offset_t length, + lldb::ByteOrder byte_order); /// Adopt a subset of \a data. /// @@ -947,8 +947,8 @@ class DataExtractor { /// /// \return /// The number of bytes that this object now contains. - lldb::offset_t SetData(const DataExtractor &data, lldb::offset_t offset, - lldb::offset_t length); + virtual lldb::offset_t SetData(const DataExtractor &data, + lldb::offset_t offset, lldb::offset_t length); /// Adopt a subset of shared data in \a data_sp. /// @@ -972,9 +972,9 @@ class DataExtractor { /// /// \return /// The number of bytes that this object now contains. - lldb::offset_t SetData(const lldb::DataBufferSP &data_sp, - lldb::offset_t offset = 0, - lldb::offset_t length = LLDB_INVALID_OFFSET); + virtual lldb::offset_t SetData(const lldb::DataBufferSP &data_sp, + lldb::offset_t offset = 0, + lldb::offset_t length = LLDB_INVALID_OFFSET); /// Set the byte_order value. /// @@ -1028,7 +1028,7 @@ class DataExtractor { bool Append(void *bytes, lldb::offset_t length); - lldb::offset_t BytesLeft(lldb::offset_t offset) const { + virtual lldb::offset_t BytesLeft(lldb::offset_t offset) const { const lldb::offset_t size = GetByteSize(); if (size > offset) return size - offset; diff --git a/lldb/include/lldb/Utility/VirtualDataExtractor.h b/lldb/include/lldb/Utility/VirtualDataExtractor.h index bcd4054912315..c8dcb62df4104 100644 --- a/lldb/include/lldb/Utility/VirtualDataExtractor.h +++ b/lldb/include/lldb/Utility/VirtualDataExtractor.h @@ -59,6 +59,27 @@ class VirtualDataExtractor : public DataExtractor { llvm::ArrayRef GetData() const override; + /// GetByteSize is called by external users often, and we want to + /// return the virtual buffer size that the user expects to see. + uint64_t GetByteSize() const override { return GetVirtualByteSize(); } + + /// BytesLeft is mostly called by DataExtractor internal methods, to + /// ensure we don't read past the end of the DataBuffer. Use the + /// physical buffer size. + lldb::offset_t BytesLeft(lldb::offset_t offset) const override { + return PhysicalBytesLeft(offset); + } + + lldb::offset_t SetData(const void *bytes, lldb::offset_t length, + lldb::ByteOrder byte_order) override; + + lldb::offset_t SetData(const DataExtractor &data, lldb::offset_t offset, + lldb::offset_t length) override; + + lldb::offset_t SetData(const lldb::DataBufferSP &data_sp, + lldb::offset_t offset = 0, + lldb::offset_t length = LLDB_INVALID_OFFSET) override; + /// Unchecked overrides /// @{ uint8_t GetU8_unchecked(lldb::offset_t *offset_ptr) const override; @@ -76,6 +97,13 @@ class VirtualDataExtractor : public DataExtractor { bool ValidateVirtualRead(lldb::offset_t virtual_addr, lldb::offset_t length) const; + uint64_t GetVirtualByteSize() const; + uint64_t GetPhysicalByteSize() const; + lldb::offset_t VirtualBytesLeft(lldb::offset_t virtual_offset) const; + lldb::offset_t PhysicalBytesLeft(lldb::offset_t physical_offset) const; + + void ResetLookupTableToMatchPhysical(); + private: LookupTable m_lookup_table; }; diff --git a/lldb/include/lldb/lldb-defines.h b/lldb/include/lldb/lldb-defines.h index 52bf7c5cce947..8e1029387d2da 100644 --- a/lldb/include/lldb/lldb-defines.h +++ b/lldb/include/lldb/lldb-defines.h @@ -89,6 +89,7 @@ #define LLDB_INVALID_PROCESS_ID 0 #define LLDB_INVALID_THREAD_ID 0 #define LLDB_INVALID_FRAME_ID UINT32_MAX +#define LLDB_UNWINDER_FRAME_LIST_ID 0 #define LLDB_INVALID_SIGNAL_NUMBER INT32_MAX #define LLDB_INVALID_SYMBOL_ID UINT32_MAX #define LLDB_INVALID_OFFSET UINT64_MAX // Must match max of lldb::offset_t diff --git a/lldb/include/lldb/lldb-types.h b/lldb/include/lldb/lldb-types.h index e309fc8833ce9..bb4c34ef8e1f5 100644 --- a/lldb/include/lldb/lldb-types.h +++ b/lldb/include/lldb/lldb-types.h @@ -83,6 +83,7 @@ typedef uint64_t user_id_t; typedef uint64_t pid_t; typedef uint64_t tid_t; typedef uint64_t offset_t; +typedef uint32_t frame_list_id_t; typedef int32_t break_id_t; typedef int32_t watch_id_t; typedef uint32_t wp_resource_id_t; diff --git a/lldb/packages/Python/lldbsuite/test/lldbtest.py b/lldb/packages/Python/lldbsuite/test/lldbtest.py index 6bb4516948da5..6034eca3b93f2 100644 --- a/lldb/packages/Python/lldbsuite/test/lldbtest.py +++ b/lldb/packages/Python/lldbsuite/test/lldbtest.py @@ -2575,6 +2575,7 @@ def expect_expr( result_value=None, result_type=None, result_children=None, + options=None, ): """ Evaluates the given expression and verifies the result. @@ -2584,6 +2585,7 @@ def expect_expr( :param result_type: The type that the expression result should have. None if the type should not be checked. :param result_children: The expected children of the expression result as a list of ValueChecks. None if the children shouldn't be checked. + :param options: Expression evaluation options. None if a default set of options should be used. """ self.assertTrue( expr.strip() == expr, @@ -2591,13 +2593,15 @@ def expect_expr( ) frame = self.frame() - options = lldb.SBExpressionOptions() - # Disable fix-its that tests don't pass by accident. - options.SetAutoApplyFixIts(False) + if not options: + options = lldb.SBExpressionOptions() - # Set the usual default options for normal expressions. - options.SetIgnoreBreakpoints(True) + # Disable fix-its that tests don't pass by accident. + options.SetAutoApplyFixIts(False) + + # Set the usual default options for normal expressions. + options.SetIgnoreBreakpoints(True) if self.frame().IsValid(): options.SetLanguage(frame.GuessLanguage()) diff --git a/lldb/packages/Python/lldbsuite/test/make/Makefile.rules b/lldb/packages/Python/lldbsuite/test/make/Makefile.rules index a0d40ab868874..4109670ebe64c 100644 --- a/lldb/packages/Python/lldbsuite/test/make/Makefile.rules +++ b/lldb/packages/Python/lldbsuite/test/make/Makefile.rules @@ -37,6 +37,29 @@ # Uncomment line below for debugging shell commands # SHELL = /bin/sh -x +# Cross platform shell commands +ifeq "$(OS)" "Windows_NT" + MKDIR_P = md $(subst /,\,$(1)) > nul 2>&1 || (exit 0) + CP = copy $(subst /,\,$(1)) $(subst /,\,$(2)) + CP_R = xcopy $(subst /,\,$(1)) $(subst /,\,$(2)) /s /e /y + RM = del $(subst /,\,$(1)) > nul 2>&1 || (exit 0) + RM_F = del /f /q $(subst /,\,$(1)) + RM_RF = rd /s /q $(subst /,\,$(1)) + LN_SF = mklink /D "$(subst /,\,$(2))" "$(subst /,\,$(1))" + ECHO = echo $(1) + ECHO_TO_FILE = echo $(1) > $(subst /,\,$(2)) +else + MKDIR_P = mkdir -p $(1) + CP = cp $(1) $(2) + CP_R = cp -r $(1) $(2) + RM = rm $(1) > /dev/null 2>&1 || true + RM_F = rm -f $(1) + RM_RF = rm -rf $(1) + LN_SF = ln -sf $(1) $(2) + ECHO = echo "$(1)" + ECHO_TO_FILE = echo $(1) > $(2) +endif + # Suppress built-in suffix rules. We explicitly define rules for %.o. .SUFFIXES: diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py index 14391db74302c..fdccc9eae9fe4 100644 --- a/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py +++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py @@ -44,7 +44,7 @@ # A quiet period between events, used to determine if we're done receiving # events in a given window, otherwise 'wait_for_stopped' would need to wait # until the DEFAULT_TIMEOUT occurs, slows down tests significantly. -EVENT_QUIET_PERIOD = 0.25 +EVENT_QUIET_PERIOD = 0.25 * (20.0 if ("ASAN_OPTIONS" in os.environ) else 1.0) # See lldbtest.Base.spawnSubprocess, which should help ensure any processes @@ -300,6 +300,7 @@ def __init__( self.stopped_thread: Optional[dict] = None self.thread_stacks: Optional[Dict[int, List[dict]]] self.thread_stop_reasons: Dict[str, Any] = {} + self.focused_tid: Optional[int] = None self.frame_scopes: Dict[str, Any] = {} # keyed by breakpoint id self.resolved_breakpoints: dict[int, Breakpoint] = {} @@ -309,6 +310,7 @@ def __init__( # trigger enqueue thread self._recv_thread.start() + self.initialized_event = None @classmethod def encode_content(cls, s: str) -> bytes: @@ -515,6 +517,7 @@ def _handle_event(self, packet: Event) -> None: self.output[category] = output elif event == "initialized": self.initialized = True + self.initialized_event = packet elif event == "process": # When a new process is attached or launched, remember the # details that are available in the body of the event @@ -539,6 +542,8 @@ def _handle_event(self, packet: Event) -> None: self._process_stopped() tid = body["threadId"] self.thread_stop_reasons[tid] = body + if "preserveFocusHint" not in body or not body["preserveFocusHint"]: + self.focused_tid = tid elif event.startswith("progress"): # Progress events come in as 'progressStart', 'progressUpdate', # and 'progressEnd' events. Keep these around in case test @@ -599,6 +604,7 @@ def _process_continued(self, all_threads_continued: bool): self.frame_scopes = {} if all_threads_continued: self.thread_stop_reasons = {} + self.focused_tid = None def _update_verified_breakpoints(self, breakpoints: List[Breakpoint]): for bp in breakpoints: @@ -1137,18 +1143,24 @@ def request_writeMemory(self, memoryReference, data, offset=0, allowPartial=Fals def request_evaluate( self, expression, - frameIndex=0, + frameIndex: Optional[int] = 0, threadId=None, context=None, is_hex: Optional[bool] = None, ) -> Response: - stackFrame = self.get_stackFrame(frameIndex=frameIndex, threadId=threadId) - if stackFrame is None: - raise ValueError("invalid frameIndex") args_dict = { "expression": expression, - "frameId": stackFrame["id"], } + + if frameIndex is not None: + if threadId is None: + threadId = self.get_thread_id() + stackFrame = self.get_stackFrame(frameIndex=frameIndex, threadId=threadId) + + if stackFrame is None: + raise ValueError("invalid frameIndex") + args_dict["frameId"] = stackFrame["id"] + if context: args_dict["context"] = context if is_hex is not None: @@ -1171,7 +1183,9 @@ def request_exceptionInfo(self, threadId=None): } return self._send_recv(command_dict) - def request_initialize(self, sourceInitFile=False): + def request_initialize( + self, client_features: Optional[dict[str, bool]] = None, sourceInitFile=False + ): command_dict = { "command": "initialize", "type": "request", @@ -1192,6 +1206,13 @@ def request_initialize(self, sourceInitFile=False): "$__lldb_sourceInitFile": sourceInitFile, }, } + + if client_features is not None: + arguments = command_dict["arguments"] + # replace the default client features. + for key, value in client_features.items(): + arguments[key] = value + response = self._send_recv(command_dict) if response: if "body" in response: @@ -1593,7 +1614,7 @@ def request_threads(self): tid = thread["id"] if tid in self.thread_stop_reasons: thread_stop_info = self.thread_stop_reasons[tid] - copy_keys = ["reason", "description", "text"] + copy_keys = ["reason", "description", "text", "hitBreakpointIds"] for key in copy_keys: if key in thread_stop_info: thread[key] = thread_stop_info[key] @@ -1854,7 +1875,7 @@ def attach_options_specified(opts): def run_adapter(dbg: DebugCommunication, opts: argparse.Namespace) -> None: - dbg.request_initialize(opts.source_init_file) + dbg.request_initialize(sourceInitFile=opts.source_init_file) source_to_lines: Dict[str, List[int]] = {} for sbp in cast(List[str], opts.source_bp): diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py index d204e87a73acb..f14742365e70e 100644 --- a/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py +++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/lldbdap_testcase.py @@ -213,6 +213,7 @@ def verify_stop_exception_info( 'exception' with the description matching 'expected_description' and text match 'expected_text', if specified.""" stopped_events = self.dap_server.wait_for_stopped() + self.assertIsNotNone(stopped_events, "No stopped events detected") for stopped_event in stopped_events: body = stopped_event["body"] if body["reason"] != "exception": @@ -235,7 +236,7 @@ def verify_stop_exception_info( f"for stopped event {stopped_event!r}", ) return - self.fail(f"No valid stop exception info detected in {stopped_events}") + self.fail(f"No valid stop exception info detected in {stopped_events!r}") def verify_stop_on_entry(self) -> None: """Waits for the process to be stopped and then verifies at least one @@ -471,12 +472,17 @@ def continue_to_breakpoints(self, breakpoint_ids: List[int]): self.do_continue() self.verify_breakpoint_hit(breakpoint_ids) - def continue_to_exception_breakpoint(self, description, text=None): + def continue_to_exception_breakpoint( + self, expected_description, expected_text=None + ): self.do_continue() - self.verify_stop_exception_info(description, text) + self.verify_stop_exception_info(expected_description, expected_text) def continue_to_exit(self, exitCode=0): self.do_continue() + self.verify_process_exited(exitCode) + + def verify_process_exited(self, exitCode: int = 0): stopped_events = self.dap_server.wait_for_stopped() self.assertEqual( len(stopped_events), 1, "stopped_events = {}".format(stopped_events) @@ -529,6 +535,7 @@ def _build_error_message(self, base_message, response): def attach( self, *, + client_features: Optional[dict[str, bool]] = None, disconnectAutomatically=True, sourceInitFile=False, **kwargs, @@ -545,7 +552,9 @@ def cleanup(): # Execute the cleanup function during test case tear down. self.addTearDownHook(cleanup) # Initialize and launch the program - self.dap_server.request_initialize(sourceInitFile) + self.dap_server.request_initialize( + client_features=client_features, sourceInitFile=sourceInitFile + ) return self.dap_server.request_attach(**kwargs) def attach_and_configurationDone( @@ -562,6 +571,7 @@ def launch( self, program: str, *, + client_features: Optional[dict[str, bool]] = None, sourceInitFile=False, disconnectAutomatically=True, **kwargs, @@ -579,7 +589,9 @@ def cleanup(): self.addTearDownHook(cleanup) # Initialize and launch the program - self.dap_server.request_initialize(sourceInitFile) + self.dap_server.request_initialize( + client_features=client_features, sourceInitFile=sourceInitFile + ) return self.dap_server.request_launch(program, **kwargs) def launch_and_configurationDone( diff --git a/lldb/source/API/SBExpressionOptions.cpp b/lldb/source/API/SBExpressionOptions.cpp index 15ed403eaaea1..10ac4f26d0ba9 100644 --- a/lldb/source/API/SBExpressionOptions.cpp +++ b/lldb/source/API/SBExpressionOptions.cpp @@ -8,6 +8,7 @@ #include "lldb/API/SBExpressionOptions.h" #include "Utils.h" +#include "lldb/API/SBError.h" #include "lldb/API/SBStream.h" #include "lldb/Target/Target.h" #include "lldb/Utility/Instrumentation.h" @@ -256,6 +257,38 @@ void SBExpressionOptions::SetAllowJIT(bool allow) { : eExecutionPolicyNever); } +// FIXME: the language plugin should expression options dynamically and +// we should validate here (by asking the language plugin) that the options +// being set/retrieved are actually valid options. + +bool SBExpressionOptions::GetBooleanLanguageOption(const char *option_name, + SBError &error) const { + LLDB_INSTRUMENT_VA(this, option_name, error); + + error.Clear(); + + auto value_or_err = m_opaque_up->GetBooleanLanguageOption(option_name); + if (!value_or_err) { + error.SetErrorString(llvm::toString(value_or_err.takeError()).c_str()); + return false; + } + + return *value_or_err; +} + +SBError SBExpressionOptions::SetBooleanLanguageOption(const char *option_name, + bool value) { + LLDB_INSTRUMENT_VA(this, option_name, value); + + SBError error; + + if (llvm::Error err = + m_opaque_up->SetBooleanLanguageOption(option_name, value)) + error.SetErrorString(llvm::toString(std::move(err)).c_str()); + + return error; +} + EvaluateExpressionOptions *SBExpressionOptions::get() const { return m_opaque_up.get(); } diff --git a/lldb/source/API/SBModule.cpp b/lldb/source/API/SBModule.cpp index 32067ac1c650f..c48d1abd88c56 100644 --- a/lldb/source/API/SBModule.cpp +++ b/lldb/source/API/SBModule.cpp @@ -52,7 +52,14 @@ SBModule::SBModule(lldb::SBProcess &process, lldb::addr_t header_addr) { ProcessSP process_sp(process.GetSP()); if (process_sp) { - m_opaque_sp = process_sp->ReadModuleFromMemory(FileSpec(), header_addr); + llvm::Expected module_sp_or_err = + process_sp->ReadModuleFromMemory(FileSpec(), header_addr); + if (auto err = module_sp_or_err.takeError()) { + llvm::consumeError(std::move(err)); + return; + } + + m_opaque_sp = *module_sp_or_err; if (m_opaque_sp) { Target &target = process_sp->GetTarget(); bool changed = false; diff --git a/lldb/source/Commands/CommandObjectExpression.cpp b/lldb/source/Commands/CommandObjectExpression.cpp index 4919bd3639d3e..efc0df6cd738e 100644 --- a/lldb/source/Commands/CommandObjectExpression.cpp +++ b/lldb/source/Commands/CommandObjectExpression.cpp @@ -44,6 +44,9 @@ Status CommandObjectExpression::CommandOptions::SetOptionValue( const int short_option = GetDefinitions()[option_idx].short_option; switch (short_option) { + case 'Q': + cpp_ignore_context_qualifiers = true; + break; case 'l': language = Language::GetLanguageTypeFromString(option_arg); if (language == eLanguageTypeUnknown) { @@ -191,6 +194,7 @@ void CommandObjectExpression::CommandOptions::OptionParsingStarting( top_level = false; allow_jit = true; suppress_persistent_result = eLazyBoolCalculate; + cpp_ignore_context_qualifiers = false; } llvm::ArrayRef @@ -213,6 +217,7 @@ CommandObjectExpression::CommandOptions::GetEvaluateExpressionOptions( options.SetExecutionPolicy( allow_jit ? EvaluateExpressionOptions::default_execution_policy : lldb_private::eExecutionPolicyNever); + options.SetCppIgnoreContextQualifiers(cpp_ignore_context_qualifiers); bool auto_apply_fixits; if (this->auto_apply_fixits == eLazyBoolCalculate) diff --git a/lldb/source/Commands/CommandObjectExpression.h b/lldb/source/Commands/CommandObjectExpression.h index 6fccf10e5dbc1..0439ddffce925 100644 --- a/lldb/source/Commands/CommandObjectExpression.h +++ b/lldb/source/Commands/CommandObjectExpression.h @@ -57,6 +57,7 @@ class CommandObjectExpression : public CommandObjectRaw, LanguageRuntimeDescriptionDisplayVerbosity m_verbosity; LazyBool auto_apply_fixits; LazyBool suppress_persistent_result; + bool cpp_ignore_context_qualifiers; }; CommandObjectExpression(CommandInterpreter &interpreter); diff --git a/lldb/source/Commands/Options.td b/lldb/source/Commands/Options.td index d96354a39b8b8..8e1b921f47c3d 100644 --- a/lldb/source/Commands/Options.td +++ b/lldb/source/Commands/Options.td @@ -778,6 +778,13 @@ let Command = "expression" in { Desc<"Persist expression result in a variable for subsequent use. " "Expression results will be labeled with $-prefixed variables, " "e.g. $0, $1, etc.">; + def ignore_context_qualifiers + : Option<"c++-ignore-context-qualifiers", "Q">, + Groups<[1, 2]>, + Desc<"When specified, evaluates the expression without taking into " + "account the type ${Q}ualifiers of the scope. In C++, this would " + "permit calling a non-const method when stopped in a const-method " + "(which would be disallowed by language rules).">; } let Command = "frame diag" in { diff --git a/lldb/source/Core/CoreProperties.td b/lldb/source/Core/CoreProperties.td index 2bc62464f91bd..63efcae3d15d3 100644 --- a/lldb/source/Core/CoreProperties.td +++ b/lldb/source/Core/CoreProperties.td @@ -14,6 +14,10 @@ let Definition = "modulelist" in { DefaultEnumValue<"eSymbolDownloadOff">, EnumValues<"OptionEnumValues(g_auto_download_enum_values)">, Desc<"On macOS, automatically download symbols with dsymForUUID (or an equivalent script/binary) for relevant images in the debug session.">; + def SharedCacheBinaryLoading: Property<"shared-cache-binary-loading", "Boolean">, + Global, + DefaultTrue, + Desc<"On macOS, load the binaries from a shared cache blob directly, instead of loading them from lldb's own in-process shared cache.">; def ClangModulesCachePath: Property<"clang-modules-cache-path", "FileSpec">, Global, DefaultStringValue<"">, diff --git a/lldb/source/Core/DynamicLoader.cpp b/lldb/source/Core/DynamicLoader.cpp index 563a81fb8239b..8426d35cf4bff 100644 --- a/lldb/source/Core/DynamicLoader.cpp +++ b/lldb/source/Core/DynamicLoader.cpp @@ -180,8 +180,15 @@ ModuleSP DynamicLoader::LoadModuleAtAddress(const FileSpec &file, // We have a core file, try to load the image from memory if we didn't find // the module. if (!module_sp && !m_process->IsLiveDebugSession()) { - module_sp = m_process->ReadModuleFromMemory(file, base_addr); - m_process->GetTarget().GetImages().AppendIfNeeded(module_sp, false); + llvm::Expected memory_module_sp_or_err = + m_process->ReadModuleFromMemory(file, base_addr); + if (auto err = memory_module_sp_or_err.takeError()) + LLDB_LOG_ERROR(GetLog(LLDBLog::DynamicLoader), std::move(err), + "Failed to read module from memory: {0}"); + else { + module_sp = *memory_module_sp_or_err; + m_process->GetTarget().GetImages().AppendIfNeeded(module_sp, false); + } } if (module_sp) UpdateLoadedSections(module_sp, link_map_addr, base_addr, @@ -196,7 +203,14 @@ static ModuleSP ReadUnnamedMemoryModule(Process *process, addr_t addr, snprintf(namebuf, sizeof(namebuf), "memory-image-0x%" PRIx64, addr); name = namebuf; } - return process->ReadModuleFromMemory(FileSpec(name), addr); + llvm::Expected module_sp_or_err = + process->ReadModuleFromMemory(FileSpec(name), addr); + if (auto err = module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(GetLog(LLDBLog::DynamicLoader), std::move(err), + "Failed to read module from memory: {0}"); + return {}; + } + return *module_sp_or_err; } ModuleSP DynamicLoader::LoadBinaryWithUUIDAndAddress( diff --git a/lldb/source/Core/Module.cpp b/lldb/source/Core/Module.cpp index 0cce30a4f210f..659190833c20d 100644 --- a/lldb/source/Core/Module.cpp +++ b/lldb/source/Core/Module.cpp @@ -360,16 +360,6 @@ const lldb_private::UUID &Module::GetUUID() { return m_uuid; } -void Module::SetUUID(const lldb_private::UUID &uuid) { - std::lock_guard guard(m_mutex); - if (!m_did_set_uuid) { - m_uuid = uuid; - m_did_set_uuid = true; - } else { - lldbassert(0 && "Attempting to overwrite the existing module UUID"); - } -} - llvm::Expected Module::GetTypeSystemForLanguage(LanguageType language) { return m_type_system_map.GetTypeSystemForLanguage(language, this, true); diff --git a/lldb/source/Core/ModuleList.cpp b/lldb/source/Core/ModuleList.cpp index 613e469dc6318..fb4a80740200d 100644 --- a/lldb/source/Core/ModuleList.cpp +++ b/lldb/source/Core/ModuleList.cpp @@ -118,6 +118,16 @@ SymbolDownload ModuleListProperties::GetSymbolAutoDownload() const { g_modulelist_properties[idx].default_uint_value)); } +bool ModuleListProperties::GetSharedCacheBinaryLoading() const { + const uint32_t idx = ePropertySharedCacheBinaryLoading; + return GetPropertyAtIndexAs( + idx, g_modulelist_properties[idx].default_uint_value != 0); +} + +bool ModuleListProperties::SetSharedCacheBinaryLoading(bool new_value) { + return SetPropertyAtIndex(ePropertySharedCacheBinaryLoading, new_value); +} + FileSpec ModuleListProperties::GetClangModulesCachePath() const { const uint32_t idx = ePropertyClangModulesCachePath; return GetPropertyAtIndexAs(idx, {}); diff --git a/lldb/source/Core/Statusline.cpp b/lldb/source/Core/Statusline.cpp index 47d48b8474e37..bdc649580637c 100644 --- a/lldb/source/Core/Statusline.cpp +++ b/lldb/source/Core/Statusline.cpp @@ -92,35 +92,36 @@ void Statusline::UpdateScrollWindow(ScrollWindowMode mode) { return; const unsigned reduced_scroll_rows = m_terminal_height - 1; - LockedStreamFile locked_stream = stream_sp->Lock(); - - switch (mode) { - case EnableStatusline: - // Move everything on the screen up. - locked_stream << '\n'; - locked_stream.Printf(ANSI_UP_ROWS, 1); - // Reduce the scroll window. - locked_stream << ANSI_SAVE_CURSOR; - locked_stream.Printf(ANSI_SET_SCROLL_ROWS, reduced_scroll_rows); - locked_stream << ANSI_RESTORE_CURSOR; - break; - case DisableStatusline: - // Reset the scroll window. - locked_stream << ANSI_SAVE_CURSOR; - locked_stream.Printf(ANSI_SET_SCROLL_ROWS, - static_cast(m_terminal_height)); - locked_stream << ANSI_RESTORE_CURSOR; - // Clear the screen below to hide the old statusline. - locked_stream << ANSI_CLEAR_BELOW; - break; - case ResizeStatusline: - // Clear the screen and update the scroll window. - // FIXME: Find a better solution (#146919). - locked_stream << ANSI_CLEAR_SCREEN; - locked_stream.Printf(ANSI_SET_SCROLL_ROWS, reduced_scroll_rows); - break; + { // Scope for locked_stream: + LockedStreamFile locked_stream = stream_sp->Lock(); + + switch (mode) { + case EnableStatusline: + // Move everything on the screen up. + locked_stream << '\n'; + locked_stream.Printf(ANSI_UP_ROWS, 1); + // Reduce the scroll window. + locked_stream << ANSI_SAVE_CURSOR; + locked_stream.Printf(ANSI_SET_SCROLL_ROWS, reduced_scroll_rows); + locked_stream << ANSI_RESTORE_CURSOR; + break; + case DisableStatusline: + // Reset the scroll window. + locked_stream << ANSI_SAVE_CURSOR; + locked_stream.Printf(ANSI_SET_SCROLL_ROWS, + static_cast(m_terminal_height)); + locked_stream << ANSI_RESTORE_CURSOR; + // Clear the screen below to hide the old statusline. + locked_stream << ANSI_CLEAR_BELOW; + break; + case ResizeStatusline: + // Clear the screen and update the scroll window. + // FIXME: Find a better solution (#146919). + locked_stream << ANSI_CLEAR_SCREEN; + locked_stream.Printf(ANSI_SET_SCROLL_ROWS, reduced_scroll_rows); + break; + } } - m_debugger.RefreshIOHandler(); } diff --git a/lldb/source/DataFormatters/FormatterBytecode.cpp b/lldb/source/DataFormatters/FormatterBytecode.cpp index c56d0b2a55e5b..66f7d01ebaa7c 100644 --- a/lldb/source/DataFormatters/FormatterBytecode.cpp +++ b/lldb/source/DataFormatters/FormatterBytecode.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "FormatterBytecode.h" +#include "lldb/DataFormatters/FormatterBytecode.h" #include "lldb/Utility/LLDBLog.h" #include "lldb/ValueObject/ValueObject.h" #include "lldb/ValueObject/ValueObjectConstResult.h" @@ -26,7 +26,7 @@ std::string toString(FormatterBytecode::OpCodes op) { const char *s = MNEMONIC; \ return s ? s : #NAME; \ } -#include "FormatterBytecode.def" +#include "lldb/DataFormatters/FormatterBytecode.def" #undef DEFINE_OPCODE } return llvm::utostr(op); @@ -37,7 +37,7 @@ std::string toString(FormatterBytecode::Selectors sel) { #define DEFINE_SELECTOR(ID, NAME) \ case ID: \ return "@" #NAME; -#include "FormatterBytecode.def" +#include "lldb/DataFormatters/FormatterBytecode.def" #undef DEFINE_SELECTOR } return "@" + llvm::utostr(sel); @@ -48,7 +48,7 @@ std::string toString(FormatterBytecode::Signatures sig) { #define DEFINE_SIGNATURE(ID, NAME) \ case ID: \ return "@" #NAME; -#include "FormatterBytecode.def" +#include "lldb/DataFormatters/FormatterBytecode.def" #undef DEFINE_SIGNATURE } return llvm::utostr(sig); diff --git a/lldb/source/DataFormatters/FormatterSection.cpp b/lldb/source/DataFormatters/FormatterSection.cpp index 1de633f4998e0..63eb45b1637f2 100644 --- a/lldb/source/DataFormatters/FormatterSection.cpp +++ b/lldb/source/DataFormatters/FormatterSection.cpp @@ -6,7 +6,8 @@ // //===----------------------------------------------------------------------===// -#include "FormatterBytecode.h" +#include "lldb/DataFormatters/FormatterSection.h" + #include "lldb/Core/Module.h" #include "lldb/DataFormatters/DataVisualization.h" #include "lldb/Utility/LLDBLog.h" diff --git a/lldb/source/DataFormatters/TypeSummary.cpp b/lldb/source/DataFormatters/TypeSummary.cpp index 91ec1c27ab63a..dd43bdfdfdfe4 100644 --- a/lldb/source/DataFormatters/TypeSummary.cpp +++ b/lldb/source/DataFormatters/TypeSummary.cpp @@ -8,8 +8,8 @@ #include "lldb/DataFormatters/TypeSummary.h" -#include "FormatterBytecode.h" #include "lldb/Core/FormatEntity.h" +#include "lldb/DataFormatters/FormatterBytecode.h" #include "lldb/lldb-enumerations.h" #include "lldb/lldb-public.h" diff --git a/lldb/source/Expression/IRInterpreter.cpp b/lldb/source/Expression/IRInterpreter.cpp index 48b4dd67d2d89..5ca64843d5900 100644 --- a/lldb/source/Expression/IRInterpreter.cpp +++ b/lldb/source/Expression/IRInterpreter.cpp @@ -611,6 +611,8 @@ bool IRInterpreter::CanInterpret(llvm::Module &module, llvm::Function &function, } break; case Instruction::And: case Instruction::AShr: + case Instruction::FPToUI: + case Instruction::FPToSI: case Instruction::IntToPtr: case Instruction::PtrToInt: case Instruction::Load: @@ -635,6 +637,18 @@ bool IRInterpreter::CanInterpret(llvm::Module &module, llvm::Function &function, case Instruction::FMul: case Instruction::FDiv: break; + case Instruction::UIToFP: + case Instruction::SIToFP: + case Instruction::FPTrunc: + case Instruction::FPExt: + if (!ii.getType()->isFloatTy() && !ii.getType()->isDoubleTy()) { + LLDB_LOGF(log, "Unsupported instruction: %s", + PrintValue(&ii).c_str()); + error = + lldb_private::Status::FromErrorString(unsupported_opcode_error); + return false; + } + break; } for (unsigned oi = 0, oe = ii.getNumOperands(); oi != oe; ++oi) { @@ -1257,6 +1271,78 @@ bool IRInterpreter::Interpret(llvm::Module &module, llvm::Function &function, LLDB_LOGF(log, " = : %s", frame.SummarizeValue(inst).c_str()); } } break; + case Instruction::FPToUI: + case Instruction::FPToSI: { + Value *src_operand = inst->getOperand(0); + + lldb_private::Scalar S; + if (!frame.EvaluateValue(S, src_operand, module)) { + LLDB_LOGF(log, "Couldn't evaluate %s", PrintValue(src_operand).c_str()); + error = lldb_private::Status::FromErrorString(bad_value_error); + return false; + } + + assert(inst->getType()->isIntegerTy() && "Unexpected target type"); + llvm::APSInt result(inst->getType()->getIntegerBitWidth(), + /*isUnsigned=*/inst->getOpcode() == + Instruction::FPToUI); + assert(S.GetType() == lldb_private::Scalar::e_float && + "Unexpected source type"); + bool isExact; + llvm::APFloatBase::opStatus status = S.GetAPFloat().convertToInteger( + result, llvm::APFloat::rmTowardZero, &isExact); + // Casting floating point values that are out of bounds of the target type + // is undefined behaviour. + if (status & llvm::APFloatBase::opInvalidOp) { + std::string s; + raw_string_ostream rso(s); + rso << "Conversion error: " << S << " cannot be converted to "; + if (inst->getOpcode() == Instruction::FPToUI) + rso << "unsigned "; + rso << *inst->getType(); + LLDB_LOGF(log, "%s", s.c_str()); + error = lldb_private::Status::FromErrorString(s.c_str()); + return false; + } + lldb_private::Scalar R(result); + + frame.AssignValue(inst, R, module); + if (log) { + LLDB_LOGF(log, "Interpreted a %s", inst->getOpcodeName()); + LLDB_LOGF(log, " Src : %s", frame.SummarizeValue(src_operand).c_str()); + LLDB_LOGF(log, " = : %s", frame.SummarizeValue(inst).c_str()); + } + } break; + case Instruction::UIToFP: + case Instruction::SIToFP: + case Instruction::FPTrunc: + case Instruction::FPExt: { + Value *src_operand = inst->getOperand(0); + + lldb_private::Scalar S; + if (!frame.EvaluateValue(S, src_operand, module)) { + LLDB_LOGF(log, "Couldn't evaluate %s", PrintValue(src_operand).c_str()); + error = lldb_private::Status::FromErrorString(bad_value_error); + return false; + } + lldb_private::Scalar R; + + Type *result_type = inst->getType(); + assert( + (result_type->isFloatTy() || result_type->isDoubleTy()) && + "Unsupported result type; CanInterpret() should have checked that"); + if (result_type->isFloatTy()) + R = S.Float(); + else + R = S.Double(); + + frame.AssignValue(inst, R, module); + if (log) { + LLDB_LOGF(log, "Interpreted a %s", inst->getOpcodeName()); + LLDB_LOGF(log, " Src : %s", frame.SummarizeValue(src_operand).c_str()); + LLDB_LOGF(log, " = : %s", frame.SummarizeValue(inst).c_str()); + } + } break; case Instruction::Load: { const LoadInst *load_inst = cast(inst); diff --git a/lldb/source/Expression/UserExpression.cpp b/lldb/source/Expression/UserExpression.cpp index 16a6218759f8f..d39bcced48390 100644 --- a/lldb/source/Expression/UserExpression.cpp +++ b/lldb/source/Expression/UserExpression.cpp @@ -323,6 +323,9 @@ UserExpression::Evaluate(ExecutionContext &exe_ctx, } if (!parse_success) { + if (user_expression_sp) + user_expression_sp->FixupParseErrorDiagnostics(diagnostic_manager); + if (target->GetEnableNotifyAboutFixIts() && fixed_expression && !fixed_expression->empty()) { std::string fixit = diff --git a/lldb/source/Host/common/HostThread.cpp b/lldb/source/Host/common/HostThread.cpp index 8822be016b0a1..11bb86e4f2ad1 100644 --- a/lldb/source/Host/common/HostThread.cpp +++ b/lldb/source/Host/common/HostThread.cpp @@ -45,6 +45,11 @@ bool HostThread::EqualsThread(lldb::thread_t thread) const { return m_native_thread->EqualsThread(thread); } +bool HostThread::EqualsThread(const HostThread &thread) const { + return m_native_thread->EqualsThread( + thread.GetNativeThread().GetSystemHandle()); +} + bool HostThread::HasThread() const { if (!m_native_thread) return false; diff --git a/lldb/source/Host/macosx/objcxx/CMakeLists.txt b/lldb/source/Host/macosx/objcxx/CMakeLists.txt index 1d7573335b8ec..a47a1e5086eee 100644 --- a/lldb/source/Host/macosx/objcxx/CMakeLists.txt +++ b/lldb/source/Host/macosx/objcxx/CMakeLists.txt @@ -14,6 +14,7 @@ add_lldb_library(lldbHostMacOSXObjCXX NO_PLUGIN_DEPENDENCIES Support TargetParser LINK_LIBS + lldbCore lldbUtility ${EXTRA_LIBS} ) diff --git a/lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm b/lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm index 8effe4cc169e0..e8f416270cdb8 100644 --- a/lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm +++ b/lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "lldb/Host/macosx/HostInfoMacOSX.h" +#include "lldb/Core/ModuleList.h" #include "lldb/Host/FileSystem.h" #include "lldb/Host/Host.h" #include "lldb/Host/HostInfo.h" @@ -16,6 +17,7 @@ #include "lldb/Utility/LLDBLog.h" #include "lldb/Utility/Log.h" #include "lldb/Utility/Timer.h" +#include "lldb/Utility/VirtualDataExtractor.h" #include "llvm/ADT/ScopeExit.h" #include "llvm/ADT/SmallString.h" @@ -30,6 +32,7 @@ // C inclues #include +#include #include #include #include @@ -65,6 +68,7 @@ #include // for TARGET_OS_TV, TARGET_OS_WATCH +using namespace lldb; using namespace lldb_private; std::optional HostInfoMacOSX::GetOSBuildString() { @@ -649,30 +653,236 @@ static bool ResolveAndVerifyCandidateSupportDir(FileSpec &path) { dyld_shared_cache_dylib_text_info; } -extern "C" int dyld_shared_cache_iterate_text( +// All available on at least macOS 12 +extern "C" { +typedef struct dyld_process_s *dyld_process_t; +typedef struct dyld_process_snapshot_s *dyld_process_snapshot_t; +typedef struct dyld_shared_cache_s *dyld_shared_cache_t; +typedef struct dyld_image_s *dyld_image_t; + +int dyld_shared_cache_iterate_text( const uuid_t cacheUuid, void (^callback)(const dyld_shared_cache_dylib_text_info *info)); -extern "C" uint8_t *_dyld_get_shared_cache_range(size_t *length); -extern "C" bool _dyld_get_shared_cache_uuid(uuid_t uuid); +uint8_t *_dyld_get_shared_cache_range(size_t *length); +bool _dyld_get_shared_cache_uuid(uuid_t uuid); +bool dyld_image_for_each_segment_info(dyld_image_t image, + void (^)(const char *segmentName, + uint64_t vmAddr, uint64_t vmSize, + int perm)); +const char *dyld_shared_cache_file_path(void); +bool dyld_shared_cache_for_file(const char *filePath, + void (^block)(dyld_shared_cache_t cache)); +void dyld_shared_cache_copy_uuid(dyld_shared_cache_t cache, uuid_t *uuid); +uint64_t dyld_shared_cache_get_base_address(dyld_shared_cache_t cache); +void dyld_shared_cache_for_each_image(dyld_shared_cache_t cache, + void (^block)(dyld_image_t image)); +bool dyld_image_copy_uuid(dyld_image_t cache, uuid_t *uuid); +const char *dyld_image_get_installname(dyld_image_t image); +const char *dyld_image_get_file_path(dyld_image_t image); +} namespace { class SharedCacheInfo { public: - const UUID &GetUUID() const { return m_uuid; } - const llvm::StringMap &GetImages() const { - return m_images; + llvm::StringMap &GetImages() { + return m_caches[m_host_uuid]; } SharedCacheInfo(); private: bool CreateSharedCacheInfoWithInstrospectionSPIs(); + void CreateSharedCacheInfoLLDBsVirtualMemory(); + bool CreateHostSharedCacheImageList(); + + // Given the UUID and filepath to a shared cache on the local debug host + // system, open it and add all of the binary images to m_caches. + bool CreateSharedCacheImageList(UUID uuid, std::string filepath); + + std::map> m_caches; + UUID m_host_uuid; - llvm::StringMap m_images; - UUID m_uuid; + // macOS 26.4 and newer + void (*m_dyld_image_retain_4HWTrace)(void *image); + void (*m_dyld_image_release_4HWTrace)(void *image); + dispatch_data_t (*m_dyld_image_segment_data_4HWTrace)( + void *image, const char *segmentName); }; + +} // namespace + +SharedCacheInfo::SharedCacheInfo() { + // macOS 26.4 and newer + m_dyld_image_retain_4HWTrace = + (void (*)(void *))dlsym(RTLD_DEFAULT, "dyld_image_retain_4HWTrace"); + m_dyld_image_release_4HWTrace = + (void (*)(void *))dlsym(RTLD_DEFAULT, "dyld_image_release_4HWTrace"); + m_dyld_image_segment_data_4HWTrace = + (dispatch_data_t(*)(void *image, const char *segmentName))dlsym( + RTLD_DEFAULT, "dyld_image_segment_data_4HWTrace"); + + uuid_t dsc_uuid; + _dyld_get_shared_cache_uuid(dsc_uuid); + m_host_uuid = UUID(dsc_uuid); + + if (ModuleList::GetGlobalModuleListProperties() + .GetSharedCacheBinaryLoading() && + CreateHostSharedCacheImageList()) + return; + + if (CreateSharedCacheInfoWithInstrospectionSPIs()) + return; + + CreateSharedCacheInfoLLDBsVirtualMemory(); } +struct segment { + std::string name; + uint64_t vmaddr; + size_t vmsize; + + // Mapped into lldb's own address space via libdispatch: + const void *data; + size_t size; +}; + +static DataExtractorSP map_shared_cache_binary_segments(void *image) { + // dyld_image_segment_data_4HWTrace can't be called on + // multiple threads simultaneously. + static std::mutex g_mutex; + std::lock_guard guard(g_mutex); + + static dispatch_data_t (*g_dyld_image_segment_data_4HWTrace)( + void *image, const char *segmentName); + static std::once_flag g_once_flag; + std::call_once(g_once_flag, [&]() { + g_dyld_image_segment_data_4HWTrace = + (dispatch_data_t(*)(void *, const char *))dlsym( + RTLD_DEFAULT, "dyld_image_segment_data_4HWTrace"); + }); + if (!g_dyld_image_segment_data_4HWTrace) + return {}; + + __block std::vector segments; + __block dyld_image_t image_copy = (dyld_image_t)image; + dyld_image_for_each_segment_info( + (dyld_image_t)image, + ^(const char *segmentName, uint64_t vmAddr, uint64_t vmSize, int perm) { + segment seg; + seg.name = segmentName; + seg.vmaddr = vmAddr; + seg.vmsize = vmSize; + + dispatch_data_t data_from_libdyld = + g_dyld_image_segment_data_4HWTrace(image_copy, segmentName); + (void)dispatch_data_create_map(data_from_libdyld, &seg.data, &seg.size); + + segments.push_back(seg); + }); + + if (!segments.size()) + return {}; + + Log *log = GetLog(LLDBLog::Modules); + bool log_verbosely = log && log->GetVerbose(); + for (const segment &seg : segments) { + if (log_verbosely) + LLDB_LOGF( + log, + "image %p %s vmaddr 0x%llx vmsize 0x%zx mapped to lldb vm addr %p", + image, seg.name.c_str(), seg.vmaddr, seg.vmsize, seg.data); + } + + // Calculate the virtual address range in lldb's + // address space (lowest memory address to highest) so + // we can contain the entire range in an unowned data buffer. + uint64_t min_lldb_vm_addr = UINT64_MAX; + uint64_t max_lldb_vm_addr = 0; + // Calculate the minimum shared cache address seen; we want the first + // segment, __TEXT, at "vm offset" 0 in our DataExtractor. + // A __DATA segment which is at the __TEXT vm addr + 0x1000 needs to be + // listed as offset 0x1000. + uint64_t min_file_vm_addr = UINT64_MAX; + for (const segment &seg : segments) { + min_lldb_vm_addr = std::min(min_lldb_vm_addr, (uint64_t)seg.data); + max_lldb_vm_addr = + std::max(max_lldb_vm_addr, (uint64_t)seg.data + seg.vmsize); + min_file_vm_addr = std::min(min_file_vm_addr, (uint64_t)seg.vmaddr); + } + DataBufferSP data_sp = std::make_shared( + (uint8_t *)min_lldb_vm_addr, max_lldb_vm_addr - min_lldb_vm_addr); + VirtualDataExtractor::LookupTable remap_table; + for (const segment &seg : segments) + remap_table.Append(VirtualDataExtractor::LookupTable::Entry( + (uint64_t)seg.vmaddr - min_file_vm_addr, (uint64_t)seg.vmsize, + (uint64_t)seg.data - (uint64_t)min_lldb_vm_addr)); + + return std::make_shared(data_sp, remap_table); +} + +// Scan the binaries in the specified shared cache filepath +// if the UUID matches, using the macOS 26.4 libdyld SPI, +// create a new entry in m_caches. +bool SharedCacheInfo::CreateSharedCacheImageList(UUID uuid, + std::string filepath) { + if (!m_dyld_image_retain_4HWTrace || !m_dyld_image_release_4HWTrace || + !m_dyld_image_segment_data_4HWTrace) + return false; + + __block bool return_failed = false; + dyld_shared_cache_for_file(filepath.c_str(), ^(dyld_shared_cache_t cache) { + uuid_t sc_uuid; + dyld_shared_cache_copy_uuid(cache, &sc_uuid); + UUID this_cache(sc_uuid, sizeof(uuid_t)); + if (this_cache != uuid) { + return_failed = true; + return; + } + + dyld_shared_cache_for_each_image(cache, ^(dyld_image_t image) { + uuid_t uuid_tmp; + if (!dyld_image_copy_uuid(image, &uuid_tmp)) + return; + UUID image_uuid(uuid_tmp, sizeof(uuid_t)); + + Log *log = GetLog(LLDBLog::Modules); + if (log && log->GetVerbose()) + LLDB_LOGF(log, "sc file %s image %p", dyld_image_get_installname(image), + (void *)image); + + m_dyld_image_retain_4HWTrace(image); + m_caches[m_host_uuid][dyld_image_get_installname(image)] = + SharedCacheImageInfo(image_uuid, map_shared_cache_binary_segments, + image); + }); + }); + if (return_failed) + return false; + + return true; +} + +// Get the filename and uuid of lldb's own shared cache, scan +// the files in it using the macOS 26.4 and newer libdyld SPI. +bool SharedCacheInfo::CreateHostSharedCacheImageList() { + std::string host_shared_cache_file = dyld_shared_cache_file_path(); + __block UUID host_sc_uuid; + dyld_shared_cache_for_file(host_shared_cache_file.c_str(), + ^(dyld_shared_cache_t cache) { + uuid_t sc_uuid; + dyld_shared_cache_copy_uuid(cache, &sc_uuid); + host_sc_uuid = UUID(sc_uuid, sizeof(uuid_t)); + }); + + if (host_sc_uuid.IsValid()) + return CreateSharedCacheImageList(host_sc_uuid, host_shared_cache_file); + + return false; +} + +// Index the binaries in lldb's own shared cache memory, using +// libdyld SPI present on macOS 12 and newer, when building against +// the internal SDK, and add an entry to the m_caches map. bool SharedCacheInfo::CreateSharedCacheInfoWithInstrospectionSPIs() { #if defined(SDK_HAS_NEW_DYLD_INTROSPECTION_SPIS) dyld_process_t dyld_process = dyld_process_create_for_current_task(); @@ -713,33 +923,31 @@ static bool ResolveAndVerifyCandidateSupportDir(FileSpec &path) { lldb::DataBufferSP data_sp = std::make_shared( (uint8_t *)minVmAddr, maxVmAddr - minVmAddr); lldb::DataExtractorSP extractor_sp = std::make_shared(data_sp); - m_images[dyld_image_get_installname(image)] = SharedCacheImageInfo{ - UUID(uuid, 16), extractor_sp}; + m_caches[m_host_uuid][dyld_image_get_installname(image)] = + SharedCacheImageInfo{UUID(uuid, 16), extractor_sp}; }); return true; #endif return false; } -SharedCacheInfo::SharedCacheInfo() { - if (CreateSharedCacheInfoWithInstrospectionSPIs()) - return; - +// Index the binaries in lldb's own shared cache memory using +// libdyld SPI available on macOS 10.13 or newer, add an entry to +// m_caches. +void SharedCacheInfo::CreateSharedCacheInfoLLDBsVirtualMemory() { size_t shared_cache_size; uint8_t *shared_cache_start = _dyld_get_shared_cache_range(&shared_cache_size); - uuid_t dsc_uuid; - _dyld_get_shared_cache_uuid(dsc_uuid); - m_uuid = UUID(dsc_uuid); dyld_shared_cache_iterate_text( - dsc_uuid, ^(const dyld_shared_cache_dylib_text_info *info) { - lldb::DataBufferSP data_sp = std::make_shared( + m_host_uuid.GetBytes().data(), + ^(const dyld_shared_cache_dylib_text_info *info) { + lldb::DataBufferSP buffer_sp = std::make_shared( shared_cache_start + info->textSegmentOffset, shared_cache_size - info->textSegmentOffset); lldb::DataExtractorSP extractor_sp = - std::make_shared(data_sp); - m_images[info->path] = + std::make_shared(buffer_sp); + m_caches[m_host_uuid][info->path] = SharedCacheImageInfo{UUID(info->dylibUuid, 16), extractor_sp}; }); } diff --git a/lldb/source/Plugins/ABI/ARC/ABISysV_arc.cpp b/lldb/source/Plugins/ABI/ARC/ABISysV_arc.cpp index e41a28bd21c36..95f4057b1d3e8 100644 --- a/lldb/source/Plugins/ABI/ARC/ABISysV_arc.cpp +++ b/lldb/source/Plugins/ABI/ARC/ABISysV_arc.cpp @@ -479,19 +479,14 @@ ABISysV_arc::GetReturnValueObjectSimple(Thread &thread, value.SetValueType(Value::ValueType::Scalar); } // Floating point return type. - else if (type_flags & eTypeIsFloat) { - bool is_complex = false; - - if (compiler_type.IsFloatingPointType(is_complex) && - !compiler_type.IsVectorType() && !is_complex) { - const size_t byte_size = - llvm::expectedToOptional(compiler_type.GetByteSize(&thread)) - .value_or(0); - auto raw_value = ReadRawValue(reg_ctx, byte_size); - - if (!SetSizedFloat(value.GetScalar(), raw_value, byte_size)) - return ValueObjectSP(); - } + else if (compiler_type.IsRealFloatingPointType()) { + const size_t byte_size = + llvm::expectedToOptional(compiler_type.GetByteSize(&thread)) + .value_or(0); + auto raw_value = ReadRawValue(reg_ctx, byte_size); + + if (!SetSizedFloat(value.GetScalar(), raw_value, byte_size)) + return ValueObjectSP(); } // Unsupported return type. else diff --git a/lldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.cpp b/lldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.cpp index 8e690218843fa..84791a90a450d 100644 --- a/lldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.cpp +++ b/lldb/source/Plugins/ABI/ARM/ABIMacOSX_arm.cpp @@ -1695,7 +1695,6 @@ Status ABIMacOSX_arm::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -1766,13 +1765,6 @@ Status ABIMacOSX_arm::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else - error = Status::FromErrorString( - "We don't support returning float values at present"); } if (!set_it_simple) diff --git a/lldb/source/Plugins/ABI/ARM/ABISysV_arm.cpp b/lldb/source/Plugins/ABI/ARM/ABISysV_arm.cpp index 7258f5cc9acb5..5b6cdbf74504c 100644 --- a/lldb/source/Plugins/ABI/ARM/ABISysV_arm.cpp +++ b/lldb/source/Plugins/ABI/ARM/ABISysV_arm.cpp @@ -1549,7 +1549,6 @@ ValueObjectSP ABISysV_arm::GetReturnValueObjectImpl( return return_valobj_sp; bool is_signed; - bool is_complex; bool is_vfp_candidate = false; uint8_t vfp_count = 0; uint8_t vfp_byte_size = 0; @@ -1633,9 +1632,8 @@ ValueObjectSP ABISysV_arm::GetReturnValueObjectImpl( if (!GetReturnValuePassedInMemory(thread, reg_ctx, *byte_size, value)) return return_valobj_sp; } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - // Vector types are handled above. - if (!is_complex) { + } else if (compiler_type.IsFloatingPointType()) { + if (!compiler_type.IsCompleteType()) { switch (*bit_width) { default: return return_valobj_sp; @@ -1681,7 +1679,7 @@ ValueObjectSP ABISysV_arm::GetReturnValueObjectImpl( break; } } - } else if (is_complex) { + } else { if (IsArmHardFloat(thread)) { is_vfp_candidate = true; vfp_byte_size = *byte_size / 2; @@ -1689,9 +1687,7 @@ ValueObjectSP ABISysV_arm::GetReturnValueObjectImpl( } else if (!GetReturnValuePassedInMemory(thread, reg_ctx, *bit_width / 8, value)) return return_valobj_sp; - } else - // not handled yet - return return_valobj_sp; + } } else if (compiler_type.IsAggregateType()) { if (IsArmHardFloat(thread)) { CompilerType base_type; @@ -1709,9 +1705,8 @@ ValueObjectSP ABISysV_arm::GetReturnValueObjectImpl( vfp_count = (*base_byte_size == 8 ? homogeneous_count : homogeneous_count * 2); } - } else if (base_type.IsFloatingPointType(is_complex)) { - // Vector types are handled above. - if (!is_complex) { + } else if (base_type.IsFloatingPointType()) { + if (!base_type.IsComplexType()) { is_vfp_candidate = true; if (base_byte_size) vfp_byte_size = *base_byte_size; @@ -1728,10 +1723,11 @@ ValueObjectSP ABISysV_arm::GetReturnValueObjectImpl( base_type = compiler_type.GetFieldAtIndex(index, name, nullptr, nullptr, nullptr); - if (base_type.IsFloatingPointType(is_complex)) { + // TODO: is this correct for float vector types? + if (base_type.GetTypeInfo() & eTypeIsFloat) { std::optional base_byte_size = llvm::expectedToOptional(base_type.GetByteSize(&thread)); - if (is_complex) { + if (base_type.IsComplexType()) { if (index != 0 && base_byte_size && vfp_byte_size != *base_byte_size) break; @@ -1842,7 +1838,6 @@ Status ABISysV_arm::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -1884,13 +1879,6 @@ Status ABISysV_arm::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else - error = Status::FromErrorString( - "We don't support returning float values at present"); } if (!set_it_simple) diff --git a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp index 91b965d3b5715..d2a2cbe0643ac 100644 --- a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp +++ b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp @@ -509,16 +509,12 @@ ValueObjectSP ABISysV_loongarch::GetReturnValueObjectSimple( return ValueObjectConstResult::Create(thread.GetStackFrameAtIndex(0).get(), value, ConstString("")); } - if (type_flags & eTypeIsFloat) { - bool is_complex = false; - - if (compiler_type.IsFloatingPointType(is_complex) && - !(type_flags & eTypeIsVector) && !is_complex) { - return_valobj_sp = - GetValObjFromFPRegs(thread, reg_ctx, machine, type_flags, byte_size); - return return_valobj_sp; - } + if (compiler_type.IsRealFloatingPointType()) { + return_valobj_sp = + GetValObjFromFPRegs(thread, reg_ctx, machine, type_flags, byte_size); + return return_valobj_sp; } + return return_valobj_sp; } diff --git a/lldb/source/Plugins/ABI/Mips/ABISysV_mips.cpp b/lldb/source/Plugins/ABI/Mips/ABISysV_mips.cpp index e03604467ceec..338d5c152f612 100644 --- a/lldb/source/Plugins/ABI/Mips/ABISysV_mips.cpp +++ b/lldb/source/Plugins/ABI/Mips/ABISysV_mips.cpp @@ -708,7 +708,6 @@ Status ABISysV_mips::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -749,13 +748,6 @@ Status ABISysV_mips::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else - error = Status::FromErrorString( - "We don't support returning float values at present"); } if (!set_it_simple) @@ -795,7 +787,6 @@ ValueObjectSP ABISysV_mips::GetReturnValueObjectImpl( return return_valobj_sp; bool is_signed = false; - bool is_complex = false; // In MIPS register "r2" (v0) holds the integer function return values const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0); @@ -858,11 +849,9 @@ ValueObjectSP ABISysV_mips::GetReturnValueObjectImpl( return_valobj_sp = ValueObjectMemory::Create( &thread, "", Address(mem_address, nullptr), return_compiler_type); return return_valobj_sp; - } else if (return_compiler_type.IsFloatingPointType(is_complex)) { + } else if (return_compiler_type.IsRealFloatingPointType()) { if (IsSoftFloat(fp_flag)) { uint64_t raw_value = reg_ctx->ReadRegisterAsUnsigned(r2_reg_info, 0); - if (is_complex) - return return_valobj_sp; switch (*bit_width) { default: return return_valobj_sp; @@ -894,51 +883,46 @@ ValueObjectSP ABISysV_mips::GetReturnValueObjectImpl( f0_value.GetData(f0_data); lldb::offset_t offset = 0; - if (!return_compiler_type.IsVectorType() && !is_complex) { - switch (*bit_width) { - default: - return return_valobj_sp; - case 64: { - static_assert(sizeof(double) == sizeof(uint64_t)); - const RegisterInfo *f1_info = reg_ctx->GetRegisterInfoByName("f1", 0); - RegisterValue f1_value; - DataExtractor f1_data; - reg_ctx->ReadRegister(f1_info, f1_value); - DataExtractor *copy_from_extractor = nullptr; - WritableDataBufferSP data_sp(new DataBufferHeap(8, 0)); - DataExtractor return_ext( - data_sp, target_byte_order, - target->GetArchitecture().GetAddressByteSize()); - - if (target_byte_order == eByteOrderLittle) { - copy_from_extractor = &f0_data; - copy_from_extractor->CopyByteOrderedData( - offset, 4, data_sp->GetBytes(), 4, target_byte_order); - f1_value.GetData(f1_data); - copy_from_extractor = &f1_data; - copy_from_extractor->CopyByteOrderedData( - offset, 4, data_sp->GetBytes() + 4, 4, target_byte_order); - } else { - copy_from_extractor = &f0_data; - copy_from_extractor->CopyByteOrderedData( - offset, 4, data_sp->GetBytes() + 4, 4, target_byte_order); - f1_value.GetData(f1_data); - copy_from_extractor = &f1_data; - copy_from_extractor->CopyByteOrderedData( - offset, 4, data_sp->GetBytes(), 4, target_byte_order); - } - value.GetScalar() = (double)return_ext.GetDouble(&offset); - break; - } - case 32: { - static_assert(sizeof(float) == sizeof(uint32_t)); - value.GetScalar() = (float)f0_data.GetFloat(&offset); - break; - } - } - } else { - // not handled yet + switch (*bit_width) { + default: return return_valobj_sp; + case 64: { + static_assert(sizeof(double) == sizeof(uint64_t)); + const RegisterInfo *f1_info = reg_ctx->GetRegisterInfoByName("f1", 0); + RegisterValue f1_value; + DataExtractor f1_data; + reg_ctx->ReadRegister(f1_info, f1_value); + DataExtractor *copy_from_extractor = nullptr; + WritableDataBufferSP data_sp(new DataBufferHeap(8, 0)); + DataExtractor return_ext( + data_sp, target_byte_order, + target->GetArchitecture().GetAddressByteSize()); + + if (target_byte_order == eByteOrderLittle) { + copy_from_extractor = &f0_data; + copy_from_extractor->CopyByteOrderedData( + offset, 4, data_sp->GetBytes(), 4, target_byte_order); + f1_value.GetData(f1_data); + copy_from_extractor = &f1_data; + copy_from_extractor->CopyByteOrderedData( + offset, 4, data_sp->GetBytes() + 4, 4, target_byte_order); + } else { + copy_from_extractor = &f0_data; + copy_from_extractor->CopyByteOrderedData( + offset, 4, data_sp->GetBytes() + 4, 4, target_byte_order); + f1_value.GetData(f1_data); + copy_from_extractor = &f1_data; + copy_from_extractor->CopyByteOrderedData( + offset, 4, data_sp->GetBytes(), 4, target_byte_order); + } + value.GetScalar() = (double)return_ext.GetDouble(&offset); + break; + } + case 32: { + static_assert(sizeof(float) == sizeof(uint32_t)); + value.GetScalar() = (float)f0_data.GetFloat(&offset); + break; + } } } } else { diff --git a/lldb/source/Plugins/ABI/Mips/ABISysV_mips64.cpp b/lldb/source/Plugins/ABI/Mips/ABISysV_mips64.cpp index 0dd9db0948220..2cd49478878eb 100644 --- a/lldb/source/Plugins/ABI/Mips/ABISysV_mips64.cpp +++ b/lldb/source/Plugins/ABI/Mips/ABISysV_mips64.cpp @@ -922,7 +922,6 @@ ValueObjectSP ABISysV_mips64::GetReturnValueObjectImpl( // True if the result is copied into our data buffer bool sucess = false; std::string name; - bool is_complex; const uint32_t num_children = return_compiler_type.GetNumFields(); // A structure consisting of one or two FP values (and nothing else) will @@ -936,7 +935,7 @@ ValueObjectSP ABISysV_mips64::GetReturnValueObjectImpl( return_compiler_type.GetFieldAtIndex(idx, name, &field_bit_offset, nullptr, nullptr); - if (field_compiler_type.IsFloatingPointType(is_complex)) + if (field_compiler_type.GetTypeInfo() & eTypeIsFloat) use_fp_regs = true; else found_non_fp_field = true; @@ -1043,7 +1042,7 @@ ValueObjectSP ABISysV_mips64::GetReturnValueObjectImpl( if (field_compiler_type.IsIntegerOrEnumerationType(is_signed) || field_compiler_type.IsPointerType() || - field_compiler_type.IsFloatingPointType(is_complex)) { + field_compiler_type.GetTypeInfo() & eTypeIsFloat) { padding = field_byte_offset - integer_bytes; if (integer_bytes < 8) { diff --git a/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.cpp b/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.cpp index 0d25faef1c659..fea5174e8fbba 100644 --- a/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.cpp +++ b/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc.cpp @@ -426,7 +426,6 @@ Status ABISysV_ppc::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -453,38 +452,33 @@ Status ABISysV_ppc::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else { - std::optional bit_width = - llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); - if (!bit_width) { - error = Status::FromErrorString("can't get type size"); + } else if (compiler_type.IsRealFloatingPointType()) { + std::optional bit_width = + llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); + if (!bit_width) { + error = Status::FromErrorString("can't get type size"); + return error; + } + if (*bit_width <= 64) { + DataExtractor data; + Status data_error; + size_t num_bytes = new_value_sp->GetData(data, data_error); + if (data_error.Fail()) { + error = Status::FromErrorStringWithFormat( + "Couldn't convert return value to raw data: %s", + data_error.AsCString()); return error; } - if (*bit_width <= 64) { - DataExtractor data; - Status data_error; - size_t num_bytes = new_value_sp->GetData(data, data_error); - if (data_error.Fail()) { - error = Status::FromErrorStringWithFormat( - "Couldn't convert return value to raw data: %s", - data_error.AsCString()); - return error; - } - unsigned char buffer[16]; - ByteOrder byte_order = data.GetByteOrder(); + unsigned char buffer[16]; + ByteOrder byte_order = data.GetByteOrder(); - data.CopyByteOrderedData(0, num_bytes, buffer, 16, byte_order); - set_it_simple = true; - } else { - // FIXME - don't know how to do 80 bit long doubles yet. - error = Status::FromErrorString( - "We don't support returning float values > 64 bits at present"); - } + data.CopyByteOrderedData(0, num_bytes, buffer, 16, byte_order); + set_it_simple = true; + } else { + // FIXME - don't know how to do 80 bit long doubles yet. + error = Status::FromErrorString( + "We don't support returning float values > 64 bits at present"); } } @@ -693,7 +687,6 @@ ValueObjectSP ABISysV_ppc::GetReturnValueObjectImpl( std::string name; uint64_t field_bit_offset = 0; bool is_signed; - bool is_complex; CompilerType field_compiler_type = return_compiler_type.GetFieldAtIndex( idx, name, &field_bit_offset, nullptr, nullptr); @@ -739,7 +732,7 @@ ValueObjectSP ABISysV_ppc::GetReturnValueObjectImpl( // return a nullptr return value object. return return_valobj_sp; } - } else if (field_compiler_type.IsFloatingPointType(is_complex)) { + } else if (field_compiler_type.GetTypeInfo() & eTypeIsFloat) { // Structs with long doubles are always passed in memory. if (*field_bit_width == 128) { is_memory = true; diff --git a/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp b/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp index 63357618774d4..0895cd3d75df6 100644 --- a/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp +++ b/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp @@ -309,7 +309,6 @@ Status ABISysV_ppc64::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -338,38 +337,33 @@ Status ABISysV_ppc64::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else { - std::optional bit_width = - llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); - if (!bit_width) { - error = Status::FromErrorString("can't get size of type"); + } else if (compiler_type.IsRealFloatingPointType()) { + std::optional bit_width = + llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); + if (!bit_width) { + error = Status::FromErrorString("can't get size of type"); + return error; + } + if (*bit_width <= 64) { + DataExtractor data; + Status data_error; + size_t num_bytes = new_value_sp->GetData(data, data_error); + if (data_error.Fail()) { + error = Status::FromErrorStringWithFormat( + "Couldn't convert return value to raw data: %s", + data_error.AsCString()); return error; } - if (*bit_width <= 64) { - DataExtractor data; - Status data_error; - size_t num_bytes = new_value_sp->GetData(data, data_error); - if (data_error.Fail()) { - error = Status::FromErrorStringWithFormat( - "Couldn't convert return value to raw data: %s", - data_error.AsCString()); - return error; - } - unsigned char buffer[16]; - ByteOrder byte_order = data.GetByteOrder(); + unsigned char buffer[16]; + ByteOrder byte_order = data.GetByteOrder(); - data.CopyByteOrderedData(0, num_bytes, buffer, 16, byte_order); - set_it_simple = true; - } else { - // FIXME - don't know how to do 80 bit long doubles yet. - error = Status::FromErrorString( - "We don't support returning float values > 64 bits at present"); - } + data.CopyByteOrderedData(0, num_bytes, buffer, 16, byte_order); + set_it_simple = true; + } else { + // FIXME - don't know how to do 80 bit long doubles yet. + error = Status::FromErrorString( + "We don't support returning float values > 64 bits at present"); } } diff --git a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp index d209980d65589..dce905f08aa5f 100644 --- a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp +++ b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp @@ -642,18 +642,14 @@ ABISysV_riscv::GetReturnValueObjectSimple(Thread &thread, value, ConstString("")); } // Floating point return type. - else if (type_flags & eTypeIsFloat) { - bool is_complex = false; - - if (compiler_type.IsFloatingPointType(is_complex) && - !(type_flags & eTypeIsVector) && !is_complex) { - const uint32_t arch_fp_flags = - arch.GetFlags() & ArchSpec::eRISCV_float_abi_mask; - return_valobj_sp = GetValObjFromFPRegs( - thread, reg_ctx, machine, arch_fp_flags, type_flags, byte_size); - return return_valobj_sp; - } + else if (compiler_type.IsRealFloatingPointType()) { + const uint32_t arch_fp_flags = + arch.GetFlags() & ArchSpec::eRISCV_float_abi_mask; + return_valobj_sp = GetValObjFromFPRegs( + thread, reg_ctx, machine, arch_fp_flags, type_flags, byte_size); + return return_valobj_sp; } + // Unsupported return type. return return_valobj_sp; } diff --git a/lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp b/lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp index 301c3b309ffd5..063ca39c56475 100644 --- a/lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp +++ b/lldb/source/Plugins/ABI/SystemZ/ABISysV_s390x.cpp @@ -393,7 +393,6 @@ Status ABISysV_s390x::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -422,42 +421,37 @@ Status ABISysV_s390x::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else { - std::optional bit_width = - llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); - if (!bit_width) { - error = Status::FromErrorString("can't get type size"); + } else if (compiler_type.IsRealFloatingPointType()) { + std::optional bit_width = + llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); + if (!bit_width) { + error = Status::FromErrorString("can't get type size"); + return error; + } + if (*bit_width <= 64) { + const RegisterInfo *f0_info = reg_ctx->GetRegisterInfoByName("f0", 0); + RegisterValue f0_value; + DataExtractor data; + Status data_error; + size_t num_bytes = new_value_sp->GetData(data, data_error); + if (data_error.Fail()) { + error = Status::FromErrorStringWithFormat( + "Couldn't convert return value to raw data: %s", + data_error.AsCString()); return error; } - if (*bit_width <= 64) { - const RegisterInfo *f0_info = reg_ctx->GetRegisterInfoByName("f0", 0); - RegisterValue f0_value; - DataExtractor data; - Status data_error; - size_t num_bytes = new_value_sp->GetData(data, data_error); - if (data_error.Fail()) { - error = Status::FromErrorStringWithFormat( - "Couldn't convert return value to raw data: %s", - data_error.AsCString()); - return error; - } - unsigned char buffer[8]; - ByteOrder byte_order = data.GetByteOrder(); + unsigned char buffer[8]; + ByteOrder byte_order = data.GetByteOrder(); - data.CopyByteOrderedData(0, num_bytes, buffer, 8, byte_order); - f0_value.SetBytes(buffer, 8, byte_order); - reg_ctx->WriteRegister(f0_info, f0_value); - set_it_simple = true; - } else { - // FIXME - don't know how to do long doubles yet. - error = Status::FromErrorString( - "We don't support returning float values > 64 bits at present"); - } + data.CopyByteOrderedData(0, num_bytes, buffer, 8, byte_order); + f0_value.SetBytes(buffer, 8, byte_order); + reg_ctx->WriteRegister(f0_info, f0_value); + set_it_simple = true; + } else { + // FIXME - don't know how to do long doubles yet. + error = Status::FromErrorString( + "We don't support returning float values > 64 bits at present"); } } diff --git a/lldb/source/Plugins/ABI/X86/ABIMacOSX_i386.cpp b/lldb/source/Plugins/ABI/X86/ABIMacOSX_i386.cpp index ee79abe55ead0..8fd1752429535 100644 --- a/lldb/source/Plugins/ABI/X86/ABIMacOSX_i386.cpp +++ b/lldb/source/Plugins/ABI/X86/ABIMacOSX_i386.cpp @@ -198,7 +198,6 @@ Status ABIMacOSX_i386::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -239,13 +238,6 @@ Status ABIMacOSX_i386::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else - error = Status::FromErrorString( - "We don't support returning float values at present"); } if (!set_it_simple) diff --git a/lldb/source/Plugins/ABI/X86/ABISysV_x86_64.cpp b/lldb/source/Plugins/ABI/X86/ABISysV_x86_64.cpp index 29fd9f0eceb93..1d184d64f5a4e 100644 --- a/lldb/source/Plugins/ABI/X86/ABISysV_x86_64.cpp +++ b/lldb/source/Plugins/ABI/X86/ABISysV_x86_64.cpp @@ -307,7 +307,6 @@ Status ABISysV_x86_64::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -336,43 +335,37 @@ Status ABISysV_x86_64::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else { - std::optional bit_width = - llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); - if (!bit_width) { - error = Status::FromErrorString("can't get type size"); + } else if (compiler_type.IsRealFloatingPointType()) { + std::optional bit_width = + llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); + if (!bit_width) { + error = Status::FromErrorString("can't get type size"); + return error; + } + if (*bit_width <= 64) { + const RegisterInfo *xmm0_info = reg_ctx->GetRegisterInfoByName("xmm0", 0); + RegisterValue xmm0_value; + DataExtractor data; + Status data_error; + size_t num_bytes = new_value_sp->GetData(data, data_error); + if (data_error.Fail()) { + error = Status::FromErrorStringWithFormat( + "Couldn't convert return value to raw data: %s", + data_error.AsCString()); return error; } - if (*bit_width <= 64) { - const RegisterInfo *xmm0_info = - reg_ctx->GetRegisterInfoByName("xmm0", 0); - RegisterValue xmm0_value; - DataExtractor data; - Status data_error; - size_t num_bytes = new_value_sp->GetData(data, data_error); - if (data_error.Fail()) { - error = Status::FromErrorStringWithFormat( - "Couldn't convert return value to raw data: %s", - data_error.AsCString()); - return error; - } - unsigned char buffer[16]; - ByteOrder byte_order = data.GetByteOrder(); + unsigned char buffer[16]; + ByteOrder byte_order = data.GetByteOrder(); - data.CopyByteOrderedData(0, num_bytes, buffer, 16, byte_order); - xmm0_value.SetBytes(buffer, 16, byte_order); - reg_ctx->WriteRegister(xmm0_info, xmm0_value); - set_it_simple = true; - } else { - // FIXME - don't know how to do 80 bit long doubles yet. - error = Status::FromErrorString( - "We don't support returning float values > 64 bits at present"); - } + data.CopyByteOrderedData(0, num_bytes, buffer, 16, byte_order); + xmm0_value.SetBytes(buffer, 16, byte_order); + reg_ctx->WriteRegister(xmm0_info, xmm0_value); + set_it_simple = true; + } else { + // FIXME - don't know how to do 80 bit long doubles yet. + error = Status::FromErrorString( + "We don't support returning float values > 64 bits at present"); } } @@ -586,7 +579,6 @@ static bool FlattenAggregateType( for (uint32_t idx = 0; idx < num_children; ++idx) { std::string name; bool is_signed; - bool is_complex; uint64_t field_bit_offset = 0; CompilerType field_compiler_type = return_compiler_type.GetFieldAtIndex( @@ -604,7 +596,8 @@ static bool FlattenAggregateType( const uint32_t field_type_flags = field_compiler_type.GetTypeInfo(); if (field_compiler_type.IsIntegerOrEnumerationType(is_signed) || field_compiler_type.IsPointerType() || - field_compiler_type.IsFloatingPointType(is_complex)) { + // FIXME: is this correct for complex floats or float vector types? + field_type_flags & eTypeIsFloat) { aggregate_field_offsets.push_back(field_byte_offset); aggregate_compiler_types.push_back(field_compiler_type); } else if (field_type_flags & eTypeHasChildren) { @@ -694,7 +687,6 @@ ValueObjectSP ABISysV_x86_64::GetReturnValueObjectImpl( is_memory = false; for (uint32_t idx = 0; idx < num_children; idx++) { bool is_signed; - bool is_complex; CompilerType field_compiler_type = aggregate_compiler_types[idx]; uint32_t field_byte_width = @@ -733,7 +725,7 @@ ValueObjectSP ABISysV_x86_64::GetReturnValueObjectImpl( // return a nullptr return value object. return return_valobj_sp; } - } else if (field_compiler_type.IsFloatingPointType(is_complex)) { + } else if (field_compiler_type.GetTypeInfo() & eTypeIsFloat) { // Structs with long doubles are always passed in memory. if (field_bit_width == 128) { is_memory = true; diff --git a/lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.cpp b/lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.cpp index 6520af2f643ee..620a247be547e 100644 --- a/lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.cpp +++ b/lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.cpp @@ -312,7 +312,6 @@ Status ABIWindows_x86_64::SetReturnValueObject(lldb::StackFrameSP &frame_sp, Thread *thread = frame_sp->GetThread().get(); bool is_signed; - bool is_complex; RegisterContext *reg_ctx = thread->GetRegisterContext().get(); @@ -341,43 +340,37 @@ Status ABIWindows_x86_64::SetReturnValueObject(lldb::StackFrameSP &frame_sp, "We don't support returning longer than 64 bit " "integer values at present."); } - } else if (compiler_type.IsFloatingPointType(is_complex)) { - if (is_complex) - error = Status::FromErrorString( - "We don't support returning complex values at present"); - else { - std::optional bit_width = - llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); - if (!bit_width) { - error = Status::FromErrorString("can't get type size"); + } else if (compiler_type.IsRealFloatingPointType()) { + std::optional bit_width = + llvm::expectedToOptional(compiler_type.GetBitSize(frame_sp.get())); + if (!bit_width) { + error = Status::FromErrorString("can't get type size"); + return error; + } + if (*bit_width <= 64) { + const RegisterInfo *xmm0_info = reg_ctx->GetRegisterInfoByName("xmm0", 0); + RegisterValue xmm0_value; + DataExtractor data; + Status data_error; + size_t num_bytes = new_value_sp->GetData(data, data_error); + if (data_error.Fail()) { + error = Status::FromErrorStringWithFormat( + "Couldn't convert return value to raw data: %s", + data_error.AsCString()); return error; } - if (*bit_width <= 64) { - const RegisterInfo *xmm0_info = - reg_ctx->GetRegisterInfoByName("xmm0", 0); - RegisterValue xmm0_value; - DataExtractor data; - Status data_error; - size_t num_bytes = new_value_sp->GetData(data, data_error); - if (data_error.Fail()) { - error = Status::FromErrorStringWithFormat( - "Couldn't convert return value to raw data: %s", - data_error.AsCString()); - return error; - } - unsigned char buffer[16]; - ByteOrder byte_order = data.GetByteOrder(); + unsigned char buffer[16]; + ByteOrder byte_order = data.GetByteOrder(); - data.CopyByteOrderedData(0, num_bytes, buffer, 16, byte_order); - xmm0_value.SetBytes(buffer, 16, byte_order); - reg_ctx->WriteRegister(xmm0_info, xmm0_value); - set_it_simple = true; - } else { - // Windows doesn't support 80 bit FP - error = Status::FromErrorString( - "Windows-x86_64 doesn't allow FP larger than 64 bits."); - } + data.CopyByteOrderedData(0, num_bytes, buffer, 16, byte_order); + xmm0_value.SetBytes(buffer, 16, byte_order); + reg_ctx->WriteRegister(xmm0_info, xmm0_value); + set_it_simple = true; + } else { + // Windows doesn't support 80 bit FP + error = Status::FromErrorString( + "Windows-x86_64 doesn't allow FP larger than 64 bits."); } } @@ -557,7 +550,6 @@ static bool FlattenAggregateType( for (uint32_t idx = 0; idx < num_children; ++idx) { std::string name; bool is_signed; - bool is_complex; uint64_t field_bit_offset = 0; CompilerType field_compiler_type = return_compiler_type.GetFieldAtIndex( @@ -580,7 +572,8 @@ static bool FlattenAggregateType( const uint32_t field_type_flags = field_compiler_type.GetTypeInfo(); if (field_compiler_type.IsIntegerOrEnumerationType(is_signed) || field_compiler_type.IsPointerType() || - field_compiler_type.IsFloatingPointType(is_complex)) { + // FIXME: is this correct for complex floats or float vector types? + field_type_flags & eTypeIsFloat) { aggregate_field_offsets.push_back(field_byte_offset); aggregate_compiler_types.push_back(field_compiler_type); } else if (field_type_flags & eTypeHasChildren) { @@ -669,7 +662,6 @@ ValueObjectSP ABIWindows_x86_64::GetReturnValueObjectImpl( const uint32_t num_children = aggregate_compiler_types.size(); for (uint32_t idx = 0; idx < num_children; idx++) { bool is_signed; - bool is_complex; CompilerType field_compiler_type = aggregate_compiler_types[idx]; uint32_t field_byte_width = @@ -688,7 +680,8 @@ ValueObjectSP ABIWindows_x86_64::GetReturnValueObjectImpl( uint32_t copy_from_offset = 0; if (field_compiler_type.IsIntegerOrEnumerationType(is_signed) || field_compiler_type.IsPointerType() || - field_compiler_type.IsFloatingPointType(is_complex)) { + // FIXME: is this correct for complex floats or float vector types? + field_compiler_type.GetTypeInfo() & eTypeIsFloat) { copy_from_extractor = &rax_data; copy_from_offset = used_bytes; used_bytes += field_byte_width; diff --git a/lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp b/lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp index 2d0a4f67499ee..142ebb7d1ca6a 100644 --- a/lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp +++ b/lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp @@ -465,8 +465,15 @@ DynamicLoaderDarwinKernel::CheckForKernelImageAtAddress(lldb::addr_t addr, if (header.filetype == llvm::MachO::MH_EXECUTE && (header.flags & llvm::MachO::MH_DYLDLINK) == 0) { // Create a full module to get the UUID - ModuleSP memory_module_sp = + llvm::Expected memory_module_sp_or_err = process->ReadModuleFromMemory(FileSpec("temp_mach_kernel"), addr); + if (auto err = memory_module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(log, std::move(err), + "DynamicLoaderDarwinKernel::CheckForKernelImageAtAddress: " + "Failed to read module in memory -- {0}"); + return UUID(); + } + ModuleSP memory_module_sp = *memory_module_sp_or_err; if (!memory_module_sp.get()) return UUID(); @@ -663,9 +670,16 @@ bool DynamicLoaderDarwinKernel::KextImageInfo::ReadMemoryModule( size_to_read = sizeof(llvm::MachO::mach_header_64) + mh.sizeofcmds; } - ModuleSP memory_module_sp = + llvm::Expected memory_module_sp_or_err = process->ReadModuleFromMemory(file_spec, m_load_address, size_to_read); + if (auto err = memory_module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(log, std::move(err), + "KextImageInfo::ReadMemoryModule failed to read module from " + "memory: {0}"); + return false; + } + ModuleSP memory_module_sp = *memory_module_sp_or_err; if (memory_module_sp.get() == nullptr) return false; diff --git a/lldb/source/Plugins/DynamicLoader/FreeBSD-Kernel/DynamicLoaderFreeBSDKernel.cpp b/lldb/source/Plugins/DynamicLoader/FreeBSD-Kernel/DynamicLoaderFreeBSDKernel.cpp index a23ba3ad5c545..a0b3a4d85c4e4 100644 --- a/lldb/source/Plugins/DynamicLoader/FreeBSD-Kernel/DynamicLoaderFreeBSDKernel.cpp +++ b/lldb/source/Plugins/DynamicLoader/FreeBSD-Kernel/DynamicLoaderFreeBSDKernel.cpp @@ -200,9 +200,17 @@ lldb_private::UUID DynamicLoaderFreeBSDKernel::CheckForKernelImageAtAddress( if (header.e_type != llvm::ELF::ET_EXEC) return UUID(); - ModuleSP memory_module_sp = + llvm::Expected memory_module_sp_or_err = process->ReadModuleFromMemory(FileSpec("temp_freebsd_kernel"), addr); + if (auto err = memory_module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(log, std::move(err), + "DynamicLoaderFreeBSDKernel::CheckForKernelImageAtAddress: " + "Failed to read module in memory -- {0}"); + *read_error = true; + return UUID(); + } + ModuleSP memory_module_sp = *memory_module_sp_or_err; if (!memory_module_sp.get()) { *read_error = true; return UUID(); @@ -291,8 +299,15 @@ bool DynamicLoaderFreeBSDKernel::KModImageInfo::ReadMemoryModule( } } - memory_module_sp = + llvm::Expected memory_module_sp_or_err = process->ReadModuleFromMemory(file_spec, m_load_address, size_to_read); + if (auto err = memory_module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(log, std::move(err), + "KextImageInfo::ReadMemoryModule: Failed to read module " + "from memory -- {0}"); + return false; + } + memory_module_sp = *memory_module_sp_or_err; if (!memory_module_sp) return false; diff --git a/lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp b/lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp index e7128ca875b94..00cae1c6cea1e 100644 --- a/lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp +++ b/lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp @@ -124,7 +124,12 @@ ModuleSP DynamicLoaderDarwin::FindTargetModuleForImageInfo( if (module_sp || !can_create) return module_sp; - if (HostInfo::GetArchitecture().IsCompatibleMatch(target.GetArchitecture())) { + // See if we have this binary in the Target or the global Module + // cache already. + module_sp = target.GetOrCreateModule(module_spec, /*notify=*/false); + + if (!module_sp && + HostInfo::GetArchitecture().IsCompatibleMatch(target.GetArchitecture())) { // When debugging on the host, we are most likely using the same shared // cache as our inferior. The dylibs from the shared cache might not // exist on the filesystem, so let's use the images in our own memory @@ -135,21 +140,28 @@ ModuleSP DynamicLoaderDarwin::FindTargetModuleForImageInfo( // If we found it and it has the correct UUID, let's proceed with // creating a module from the memory contents. - if (image_info.uuid && - (!module_spec.GetUUID() || module_spec.GetUUID() == image_info.uuid)) { - ModuleSpec shared_cache_spec(module_spec.GetFileSpec(), image_info.uuid, - image_info.extractor_sp); + if (image_info.GetUUID() && + (!module_spec.GetUUID() || + module_spec.GetUUID() == image_info.GetUUID())) { + ModuleSpec shared_cache_spec(module_spec.GetFileSpec(), + image_info.GetUUID(), + image_info.GetExtractor()); module_sp = target.GetOrCreateModule(shared_cache_spec, false /* notify */); } } // We'll call Target::ModulesDidLoad after all the modules have been // added to the target, don't let it be called for every one. - if (!module_sp) - module_sp = target.GetOrCreateModule(module_spec, false /* notify */); - if (!module_sp || module_sp->GetObjectFile() == nullptr) - module_sp = m_process->ReadModuleFromMemory(image_info.file_spec, - image_info.address); + if (!module_sp || module_sp->GetObjectFile() == nullptr) { + llvm::Expected module_sp_or_err = m_process->ReadModuleFromMemory( + image_info.file_spec, image_info.address); + if (auto err = module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(GetLog(LLDBLog::DynamicLoader), std::move(err), + "Failed to load module from memory: {0}"); + return {}; + } + module_sp = *module_sp_or_err; + } if (did_create_ptr) *did_create_ptr = (bool)module_sp; @@ -722,19 +734,26 @@ bool DynamicLoaderDarwin::AddModulesUsingPreloadedModules( true /* notify */); if (!commpage_image_module_sp || commpage_image_module_sp->GetObjectFile() == nullptr) { - commpage_image_module_sp = m_process->ReadModuleFromMemory( - image_info.file_spec, image_info.address); - // Always load a memory image right away in the target in case - // we end up trying to read the symbol table from memory... The - // __LINKEDIT will need to be mapped so we can figure out where - // the symbol table bits are... - bool changed = false; - UpdateImageLoadAddress(commpage_image_module_sp.get(), - image_info); - target.GetImages().Append(commpage_image_module_sp); - if (changed) { - image_info.load_stop_id = m_process->GetStopID(); - loaded_module_list.AppendIfNeeded(commpage_image_module_sp); + llvm::Expected module_sp_or_err = + m_process->ReadModuleFromMemory(image_info.file_spec, + image_info.address); + if (auto err = module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(log, std::move(err), + "Failed to read module from memory: {0}"); + } else { + // Always load a memory image right away in the target in case + // we end up trying to read the symbol table from memory... + // The __LINKEDIT will need to be mapped so we can figure out + // where the symbol table bits are... + commpage_image_module_sp = *module_sp_or_err; + bool changed = false; + UpdateImageLoadAddress(commpage_image_module_sp.get(), + image_info); + target.GetImages().Append(commpage_image_module_sp); + if (changed) { + image_info.load_stop_id = m_process->GetStopID(); + loaded_module_list.AppendIfNeeded(commpage_image_module_sp); + } } } } diff --git a/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp b/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp index 6705ac139f0fb..1d814f93484d8 100644 --- a/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp +++ b/lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp @@ -597,16 +597,20 @@ void DynamicLoaderPOSIXDYLD::LoadVDSO() { FileSpec file("[vdso]"); + Log *log = GetLog(LLDBLog::DynamicLoader); MemoryRegionInfo info; Status status = m_process->GetMemoryRegionInfo(m_vdso_base, info); if (status.Fail()) { - Log *log = GetLog(LLDBLog::DynamicLoader); LLDB_LOG(log, "Failed to get vdso region info: {0}", status); return; } - if (ModuleSP module_sp = m_process->ReadModuleFromMemory( - file, m_vdso_base, info.GetRange().GetByteSize())) { + llvm::Expected module_sp_or_err = m_process->ReadModuleFromMemory( + file, m_vdso_base, info.GetRange().GetByteSize()); + if (auto err = module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(log, std::move(err), + "Failed to read module from memory: {0}"); + } else if (ModuleSP module_sp = *module_sp_or_err) { UpdateLoadedSections(module_sp, LLDB_INVALID_ADDRESS, m_vdso_base, false); m_process->GetTarget().GetImages().AppendIfNeeded(module_sp); } diff --git a/lldb/source/Plugins/DynamicLoader/wasm-DYLD/DynamicLoaderWasmDYLD.cpp b/lldb/source/Plugins/DynamicLoader/wasm-DYLD/DynamicLoaderWasmDYLD.cpp index d019415cb67a6..2aed7c9e00dc4 100644 --- a/lldb/source/Plugins/DynamicLoader/wasm-DYLD/DynamicLoaderWasmDYLD.cpp +++ b/lldb/source/Plugins/DynamicLoader/wasm-DYLD/DynamicLoaderWasmDYLD.cpp @@ -72,7 +72,15 @@ lldb::ModuleSP DynamicLoaderWasmDYLD::LoadModuleAtAddress( file, link_map_addr, base_addr, base_addr_is_offset)) return module_sp; - if (ModuleSP module_sp = m_process->ReadModuleFromMemory(file, base_addr)) { + llvm::Expected module_sp_or_err = + m_process->ReadModuleFromMemory(file, base_addr); + if (auto err = module_sp_or_err.takeError()) { + LLDB_LOG_ERROR(GetLog(LLDBLog::DynamicLoader), std::move(err), + "Failed to read module from memory: {0}"); + return nullptr; + } + + if (ModuleSP module_sp = *module_sp_or_err) { UpdateLoadedSections(module_sp, link_map_addr, base_addr, false); m_process->GetTarget().GetImages().AppendIfNeeded(module_sp); return module_sp; diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp index 664bcba0017a7..9f4ccc60c0b34 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.cpp @@ -88,10 +88,12 @@ ClangExpressionDeclMap::ClangExpressionDeclMap( bool keep_result_in_memory, Materializer::PersistentVariableDelegate *result_delegate, const lldb::TargetSP &target, - const std::shared_ptr &importer, ValueObject *ctx_obj) + const std::shared_ptr &importer, ValueObject *ctx_obj, + bool ignore_context_qualifiers) : ClangASTSource(target, importer), m_found_entities(), m_struct_members(), m_keep_result_in_memory(keep_result_in_memory), - m_result_delegate(result_delegate), m_ctx_obj(ctx_obj), m_parser_vars(), + m_result_delegate(result_delegate), m_ctx_obj(ctx_obj), + m_ignore_context_qualifiers(ignore_context_qualifiers), m_parser_vars(), m_struct_vars() { EnableStructVars(); } @@ -844,6 +846,12 @@ void ClangExpressionDeclMap::LookUpLldbClass(NameSearchContext &context) { QualType class_qual_type = m_ast_context->getCanonicalTagType(class_decl); + // The synthesized __lldb_expr will adopt the qualifiers from this class + // type. Make sure we use the qualifiers of the method that we're currently + // stopped in. + class_qual_type.addFastQualifiers( + method_decl->getMethodQualifiers().getFastQualifiers()); + TypeFromUser class_user_type( class_qual_type.getAsOpaquePtr(), function_decl_ctx.GetTypeSystem()->weak_from_this()); @@ -1991,7 +1999,8 @@ void ClangExpressionDeclMap::AddContextClassType(NameSearchContext &context, std::array args{void_clang_type.GetPointerType()}; CompilerType method_type = m_clang_ast_context->CreateFunctionType( - void_clang_type, args, false, 0); + void_clang_type, args, false, + m_ignore_context_qualifiers ? 0 : ut.GetTypeQualifiers()); const bool is_virtual = false; const bool is_static = false; diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.h b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.h index df74ebc37a5de..d44c95068f45d 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.h +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionDeclMap.h @@ -78,11 +78,18 @@ class ClangExpressionDeclMap : public ClangASTSource { /// \param[in] ctx_obj /// If not empty, then expression is evaluated in context of this object. /// See the comment to `UserExpression::Evaluate` for details. + /// + /// \param[in] ignore_context_qualifiers + /// If \c true, evaluates the expression without taking into account the + /// CV-qualifiers of the scope. E.g., this would permit calling a + /// non-const C++ method when stopped in a const-method (which would be + /// disallowed by C++ language rules). ClangExpressionDeclMap( bool keep_result_in_memory, Materializer::PersistentVariableDelegate *result_delegate, const lldb::TargetSP &target, - const std::shared_ptr &importer, ValueObject *ctx_obj); + const std::shared_ptr &importer, ValueObject *ctx_obj, + bool ignore_context_qualifiers); /// Destructor ~ClangExpressionDeclMap() override; @@ -306,6 +313,12 @@ class ClangExpressionDeclMap : public ClangASTSource { ///For details see the comment to ///`UserExpression::Evaluate`. + /// If \c true, evaluates the expression without taking into account the + /// CV-qualifiers of the scope. E.g., this would permit calling a + /// non-const C++ method when stopped in a const-method (which would be + /// disallowed by C++ language rules). + bool m_ignore_context_qualifiers = false; + /// The following values should not live beyond parsing class ParserVars { public: diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp index cfe187ffc4114..c711367cb6177 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp @@ -10,6 +10,7 @@ #include "ClangExpressionUtil.h" +#include "clang/AST/TypeBase.h" #include "clang/Basic/CharInfo.h" #include "clang/Basic/FileManager.h" #include "clang/Basic/SourceManager.h" @@ -189,6 +190,28 @@ static void AddMacros(const DebugMacros *dm, CompileUnit *comp_unit, } } +/// Return qualifers of the current C++ method. +static clang::Qualifiers GetFrameCVQualifiers(StackFrame *frame) { + if (!frame) + return {}; + + auto this_sp = frame->FindVariable(ConstString("this")); + if (!this_sp) + return {}; + + // Lambdas that capture 'this' have a member variable called 'this'. The class + // context of __lldb_expr for a lambda is the class type of the 'this' capture + // (not the anonymous lambda structure). So use the qualifiers of the captured + // 'this'. + if (auto this_this_sp = this_sp->GetChildMemberWithName("this")) + return clang::Qualifiers::fromCVRMask( + this_this_sp->GetCompilerType().GetPointeeType().GetTypeQualifiers()); + + // Not in a lambda. Return 'this' qualifiers. + return clang::Qualifiers::fromCVRMask( + this_sp->GetCompilerType().GetPointeeType().GetTypeQualifiers()); +} + lldb_private::ClangExpressionSourceCode::ClangExpressionSourceCode( llvm::StringRef filename, llvm::StringRef name, llvm::StringRef prefix, llvm::StringRef body, Wrapping wrap, WrapKind wrap_kind) @@ -340,9 +363,12 @@ void ClangExpressionSourceCode::AddLocalVariableDecls(StreamString &stream, } } -bool ClangExpressionSourceCode::GetText( - std::string &text, ExecutionContext &exe_ctx, bool add_locals, - bool force_add_all_locals, llvm::ArrayRef modules) const { +bool ClangExpressionSourceCode::GetText(std::string &text, + ExecutionContext &exe_ctx, + bool add_locals, + bool force_add_all_locals, + llvm::ArrayRef modules, + bool ignore_context_qualifiers) const { const char *target_specific_defines = "typedef signed char BOOL;\n"; std::string module_macros; llvm::raw_string_ostream module_macros_stream(module_macros); @@ -464,13 +490,18 @@ bool ClangExpressionSourceCode::GetText( break; case WrapKind::CppMemberFunction: wrap_stream.Printf("%s" - "void \n" - "$__lldb_class::%s(void *$__lldb_arg) \n" - "{ \n" - " %s; \n" + "void \n" + "$__lldb_class::%s(void *$__lldb_arg) %s \n" + "{ \n" + " %s; \n" "%s" - "} \n", + "} \n", module_imports.c_str(), m_name.c_str(), + ignore_context_qualifiers + ? "" + : GetFrameCVQualifiers(exe_ctx.GetFramePtr()) + .getAsString() + .c_str(), lldb_local_var_decls.GetData(), tagged_body.c_str()); break; case WrapKind::ObjCInstanceMethod: diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.h b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.h index f721bb2f319e1..914d405139193 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.h +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.h @@ -63,8 +63,8 @@ class ClangExpressionSourceCode : public ExpressionSourceCode { /// /// \return true iff the source code was successfully generated. bool GetText(std::string &text, ExecutionContext &exe_ctx, bool add_locals, - bool force_add_all_locals, - llvm::ArrayRef modules) const; + bool force_add_all_locals, llvm::ArrayRef modules, + bool ignore_context_qualifiers) const; // Given a string returned by GetText, find the beginning and end of the body // passed to CreateWrapped. Return true if the bounds could be found. This diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.cpp index 2cbbae11bd18a..4fcc640d90716 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.cpp +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.cpp @@ -27,6 +27,7 @@ #include "Plugins/TypeSystem/Clang/TypeSystemClang.h" #include "lldb/Core/Debugger.h" #include "lldb/Core/Module.h" +#include "lldb/Expression/DiagnosticManager.h" #include "lldb/Expression/ExpressionSourceCode.h" #include "lldb/Expression/IRExecutionUnit.h" #include "lldb/Expression/IRInterpreter.h" @@ -55,6 +56,8 @@ #include "clang/AST/DeclCXX.h" #include "clang/AST/DeclObjC.h" +#include "clang/Basic/DiagnosticSema.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/ScopeExit.h" #include "llvm/BinaryFormat/Dwarf.h" @@ -416,7 +419,8 @@ void ClangUserExpression::CreateSourceCode( m_filename, prefix, m_expr_text, GetWrapKind())); if (!m_source_code->GetText(m_transformed_text, exe_ctx, !m_ctx_obj, - for_completion, modules_to_import)) { + for_completion, modules_to_import, + m_options.GetCppIgnoreContextQualifiers())) { diagnostic_manager.PutString(lldb::eSeverityError, "couldn't construct expression body"); return; @@ -945,13 +949,82 @@ lldb::ExpressionVariableSP ClangUserExpression::GetResultAfterDematerialization( return m_result_delegate.GetVariable(); } +void ClangUserExpression::FixupCVRParseErrorDiagnostics( + DiagnosticManager &diagnostic_manager) const { + const bool is_fixable_cvr_error = llvm::any_of( + diagnostic_manager.Diagnostics(), + [](std::unique_ptr const &diag) { + switch (diag->GetCompilerID()) { + case clang::diag::err_member_function_call_bad_cvr: + return true; + case clang::diag::err_typecheck_assign_const: + // FIXME: can we split this particular error into a separate + // diagnostic ID so we don't need to scan the error message? + return diag->GetDetail().message.find( + "within const member function") != std::string::npos; + default: + return false; + } + }); + + // Nothing to report. + if (!is_fixable_cvr_error) + return; + + // If the user already tried ignoring function qualifiers but + // the expression still failed, we don't want to suggest the hint again. + if (m_options.GetCppIgnoreContextQualifiers()) { + // Hard to prove that we don't get here so don't emit a diagnostic n + // non-asserts builds. But we do want a signal in asserts builds. + assert(false && + "CppIgnoreContextQualifiers didn't resolve compiler diagnostic."); + return; + } + + diagnostic_manager.Printf( + lldb::eSeverityInfo, + "Possibly trying to mutate object in a const context. Try " + "running the expression with: expression --c++-ignore-context-qualifiers " + "-- %s", + !m_fixed_text.empty() ? m_fixed_text.c_str() : m_expr_text.c_str()); +} + +void ClangUserExpression::FixupTemplateLookupDiagnostics( + DiagnosticManager &diagnostic_manager) const { + if (llvm::none_of(diagnostic_manager.Diagnostics(), + [](std::unique_ptr const &diag) { + switch (diag->GetCompilerID()) { + // FIXME: should we also be checking + // clang::diag::err_no_member_template? + case clang::diag::err_no_template: + case clang::diag::err_non_template_in_template_id: + return true; + default: + return false; + } + })) + return; + + diagnostic_manager.AddDiagnostic( + "Naming template instantiation not yet supported. Template functions " + "can be invoked via their mangled name. For example, using " + "`_Z3fooIiEvi(123)` for `foo(123)`", + lldb::eSeverityInfo, eDiagnosticOriginLLDB); +} + +void ClangUserExpression::FixupParseErrorDiagnostics( + DiagnosticManager &diagnostic_manager) const { + FixupCVRParseErrorDiagnostics(diagnostic_manager); + FixupTemplateLookupDiagnostics(diagnostic_manager); +} + char ClangUserExpression::ClangUserExpressionHelper::ID; void ClangUserExpression::ClangUserExpressionHelper::ResetDeclMap( ExecutionContext &exe_ctx, Materializer::PersistentVariableDelegate &delegate, - bool keep_result_in_memory, - ValueObject *ctx_obj) { + bool keep_result_in_memory, ValueObject *ctx_obj, + bool ignore_context_qualifiers) { std::shared_ptr ast_importer; auto *state = exe_ctx.GetTargetSP()->GetPersistentExpressionStateForLanguage( lldb::eLanguageTypeC); @@ -961,7 +1034,7 @@ void ClangUserExpression::ClangUserExpressionHelper::ResetDeclMap( } m_expr_decl_map_up = std::make_unique( keep_result_in_memory, &delegate, exe_ctx.GetTargetSP(), ast_importer, - ctx_obj); + ctx_obj, ignore_context_qualifiers); } clang::ASTConsumer * diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.h b/lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.h index 7c0c6a0147e2a..74aceed1d637e 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.h +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangUserExpression.h @@ -71,8 +71,8 @@ class ClangUserExpression : public LLVMUserExpression { void ResetDeclMap(ExecutionContext &exe_ctx, Materializer::PersistentVariableDelegate &result_delegate, - bool keep_result_in_memory, - ValueObject *ctx_obj); + bool keep_result_in_memory, ValueObject *ctx_obj, + bool ignore_context_qualifiers); /// Return the object that the parser should allow to access ASTs. May be /// NULL if the ASTs do not need to be transformed. @@ -166,9 +166,9 @@ class ClangUserExpression : public LLVMUserExpression { void ResetDeclMap(ExecutionContext &exe_ctx, Materializer::PersistentVariableDelegate &result_delegate, bool keep_result_in_memory) { - m_type_system_helper.ResetDeclMap(exe_ctx, result_delegate, - keep_result_in_memory, - m_ctx_obj); + m_type_system_helper.ResetDeclMap( + exe_ctx, result_delegate, keep_result_in_memory, m_ctx_obj, + m_options.GetCppIgnoreContextQualifiers()); } lldb::ExpressionVariableSP @@ -179,6 +179,10 @@ class ClangUserExpression : public LLVMUserExpression { llvm::StringRef GetFilename() const { return m_filename; } +protected: + void FixupParseErrorDiagnostics( + DiagnosticManager &diagnostic_manager) const override; + private: /// Populate m_in_cplusplus_method and m_in_objectivec_method based on the /// environment. @@ -208,6 +212,12 @@ class ClangUserExpression : public LLVMUserExpression { lldb::addr_t GetCppObjectPointer(lldb::StackFrameSP frame, llvm::StringRef object_name, Status &err); + void + FixupCVRParseErrorDiagnostics(DiagnosticManager &diagnostic_manager) const; + + void + FixupTemplateLookupDiagnostics(DiagnosticManager &diagnostic_manager) const; + /// Defines how the current expression should be wrapped. ClangExpressionSourceCode::WrapKind GetWrapKind() const; bool SetupPersistentState(DiagnosticManager &diagnostic_manager, diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp index e6983066a12fa..112ce9be7bd1a 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangUtilityFunction.cpp @@ -187,5 +187,5 @@ void ClangUtilityFunction::ClangUtilityFunctionHelper::ResetDeclMap( } m_expr_decl_map_up = std::make_unique( keep_result_in_memory, nullptr, exe_ctx.GetTargetSP(), ast_importer, - nullptr); + nullptr, /*ignore_context_qualifiers=*/false); } diff --git a/lldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp b/lldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp index b6487d4e8ed4b..b8e33c6568eab 100644 --- a/lldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp +++ b/lldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp @@ -323,8 +323,16 @@ bool JITLoaderGDB::ReadJITDescriptorImpl(bool all_entries) { char jit_name[64]; snprintf(jit_name, 64, "JIT(0x%" PRIx64 ")", symbolfile_addr); - module_sp = m_process->ReadModuleFromMemory( - FileSpec(jit_name), symbolfile_addr, symbolfile_size); + llvm::Expected module_sp_or_err = + m_process->ReadModuleFromMemory(FileSpec(jit_name), symbolfile_addr, + symbolfile_size); + if (auto err = module_sp_or_err.takeError()) + LLDB_LOG_ERROR( + log, std::move(err), + "JITLoaderGDB::{1} failed to read module from memory: {0}", + __FUNCTION__); + else + module_sp = *module_sp_or_err; if (module_sp && module_sp->GetObjectFile()) { // Object formats (like ELF) have no representation for a JIT type. diff --git a/lldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp b/lldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp index bfa543adeffc2..bee84281ebd52 100644 --- a/lldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp +++ b/lldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp @@ -441,9 +441,8 @@ size_t ObjectContainerBSDArchive::GetModuleSpecifications( if (!file || !extractor_sp) return 0; - DataExtractorSP data_extractor_sp = extractor_sp->GetSubsetExtractorSP( - data_offset, - extractor_sp->GetSharedDataBuffer()->GetByteSize() - data_offset); + DataExtractorSP data_extractor_sp = + extractor_sp->GetSubsetExtractorSP(data_offset); // We have data, which means this is the first 512 bytes of the file Check to // see if the magic bytes match and if they do, read the entire table of // contents for the archive and cache it diff --git a/lldb/source/Plugins/ObjectContainer/Mach-O-Fileset/ObjectContainerMachOFileset.cpp b/lldb/source/Plugins/ObjectContainer/Mach-O-Fileset/ObjectContainerMachOFileset.cpp index b1b0d0067d404..0b99e3faafabd 100644 --- a/lldb/source/Plugins/ObjectContainer/Mach-O-Fileset/ObjectContainerMachOFileset.cpp +++ b/lldb/source/Plugins/ObjectContainer/Mach-O-Fileset/ObjectContainerMachOFileset.cpp @@ -227,8 +227,8 @@ size_t ObjectContainerMachOFileset::GetModuleSpecifications( if (!extractor_sp) return initial_count; - DataExtractorSP data_extractor_sp = extractor_sp->GetSubsetExtractorSP( - data_offset, extractor_sp->GetByteSize()); + DataExtractorSP data_extractor_sp = + extractor_sp->GetSubsetExtractorSP(data_offset); if (!data_extractor_sp) return initial_count; if (MagicBytesMatch(*data_extractor_sp)) { diff --git a/lldb/source/Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.cpp b/lldb/source/Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.cpp index 215c419a0a9c6..366a8852b9b5e 100644 --- a/lldb/source/Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.cpp +++ b/lldb/source/Plugins/ObjectContainer/Universal-Mach-O/ObjectContainerUniversalMachO.cpp @@ -195,8 +195,8 @@ size_t ObjectContainerUniversalMachO::GetModuleSpecifications( if (!extractor_sp) return initial_count; - DataExtractorSP data_extractor_sp = extractor_sp->GetSubsetExtractorSP( - data_offset, extractor_sp->GetByteSize()); + DataExtractorSP data_extractor_sp = + extractor_sp->GetSubsetExtractorSP(data_offset); if (ObjectContainerUniversalMachO::MagicBytesMatch(*data_extractor_sp)) { llvm::MachO::fat_header header; std::vector fat_archs; diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp index 90afd5b2dc93a..1a515852e7092 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp @@ -481,7 +481,7 @@ ObjectFile *ObjectFileELF::CreateMemoryInstance( return nullptr; } -bool ObjectFileELF::MagicBytesMatch(DataBufferSP &data_sp, +bool ObjectFileELF::MagicBytesMatch(DataBufferSP data_sp, lldb::addr_t data_offset, lldb::addr_t data_length) { if (data_sp && @@ -2241,6 +2241,12 @@ ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, // function will be resolved if it is referenced. symbol_type = eSymbolTypeResolver; break; + + case STT_TLS: + // The symbol is associated with a thread-local data object, such as + // a thread-local variable. + symbol_type = eSymbolTypeData; + break; } } @@ -2768,7 +2774,7 @@ static void ApplyELF64ABS64Relocation(Symtab *symtab, ELFRelocation &rel, symtab->FindSymbolByID(ELFRelocation::RelocSymbol64(rel)); if (symbol) { addr_t value = symbol->GetAddressRef().GetFileAddress(); - DataBufferSP &data_buffer_sp = debug_data.GetSharedDataBuffer(); + DataBufferSP data_buffer_sp = debug_data.GetSharedDataBuffer(); // ObjectFileELF creates a WritableDataBuffer in CreateInstance. WritableDataBuffer *data_buffer = llvm::cast(data_buffer_sp.get()); @@ -2795,7 +2801,7 @@ static void ApplyELF64ABS32Relocation(Symtab *symtab, ELFRelocation &rel, return; } uint32_t truncated_addr = (value & 0xFFFFFFFF); - DataBufferSP &data_buffer_sp = debug_data.GetSharedDataBuffer(); + DataBufferSP data_buffer_sp = debug_data.GetSharedDataBuffer(); // ObjectFileELF creates a WritableDataBuffer in CreateInstance. WritableDataBuffer *data_buffer = llvm::cast(data_buffer_sp.get()); @@ -2819,7 +2825,7 @@ static void ApplyELF32ABS32RelRelocation(Symtab *symtab, ELFRelocation &rel, return; } assert(llvm::isUInt<32>(value) && "Valid addresses are 32-bit"); - DataBufferSP &data_buffer_sp = debug_data.GetSharedDataBuffer(); + DataBufferSP data_buffer_sp = debug_data.GetSharedDataBuffer(); // ObjectFileELF creates a WritableDataBuffer in CreateInstance. WritableDataBuffer *data_buffer = llvm::cast(data_buffer_sp.get()); @@ -2896,7 +2902,7 @@ unsigned ObjectFileELF::ApplyRelocations( if (symbol) { addr_t f_offset = rel_section->GetFileOffset() + ELFRelocation::RelocOffset32(rel); - DataBufferSP &data_buffer_sp = debug_data.GetSharedDataBuffer(); + DataBufferSP data_buffer_sp = debug_data.GetSharedDataBuffer(); // ObjectFileELF creates a WritableDataBuffer in CreateInstance. WritableDataBuffer *data_buffer = llvm::cast(data_buffer_sp.get()); diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h index 4992e9e2482f3..9fc19bcd07f34 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h @@ -85,7 +85,7 @@ class ObjectFileELF : public lldb_private::ObjectFile { lldb::offset_t length, lldb_private::ModuleSpecList &specs); - static bool MagicBytesMatch(lldb::DataBufferSP &data_sp, lldb::addr_t offset, + static bool MagicBytesMatch(lldb::DataBufferSP data_sp, lldb::addr_t offset, lldb::addr_t length); // PluginInterface protocol diff --git a/lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp b/lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp index 0bcccfc059bbc..b34c03ea56a05 100644 --- a/lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp +++ b/lldb/source/Plugins/ObjectFile/XCOFF/ObjectFileXCOFF.cpp @@ -167,7 +167,7 @@ bool ObjectFileXCOFF::MagicBytesMatch(DataExtractorSP &extractor_sp, lldb::addr_t data_offset, lldb::addr_t data_length) { DataExtractorSP magic_extractor_sp = - extractor_sp->GetSubsetExtractorSP(data_offset, data_length); + extractor_sp->GetSubsetExtractorSP(data_offset); // Need to set this as XCOFF is only compatible with Big Endian magic_extractor_sp->SetByteOrder(eByteOrderBig); lldb::offset_t offset = 0; diff --git a/lldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp b/lldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp index d7584be2b95ee..b537813709bc1 100644 --- a/lldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp +++ b/lldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp @@ -123,8 +123,7 @@ PlatformFreeBSD::PlatformFreeBSD(bool is_host) } else { m_supported_architectures = CreateArchList( {llvm::Triple::x86_64, llvm::Triple::x86, llvm::Triple::aarch64, - llvm::Triple::arm, llvm::Triple::mips64, llvm::Triple::ppc64, - llvm::Triple::ppc}, + llvm::Triple::arm, llvm::Triple::ppc64, llvm::Triple::ppc}, llvm::Triple::FreeBSD); } } diff --git a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp index a6dc6759c16df..c1a04e801107e 100644 --- a/lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp +++ b/lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp @@ -323,10 +323,12 @@ lldb_private::Status PlatformDarwinDevice::GetSharedModuleWithLocalCache( // If we found it and it has the correct UUID, let's proceed with // creating a module from the memory contents. - if (image_info.uuid && - (!module_spec.GetUUID() || module_spec.GetUUID() == image_info.uuid)) { - ModuleSpec shared_cache_spec(module_spec.GetFileSpec(), image_info.uuid, - image_info.extractor_sp); + if (image_info.GetUUID() && + (!module_spec.GetUUID() || + module_spec.GetUUID() == image_info.GetUUID())) { + ModuleSpec shared_cache_spec(module_spec.GetFileSpec(), + image_info.GetUUID(), + image_info.GetExtractor()); err = ModuleList::GetSharedModule(shared_cache_spec, module_sp, old_modules, did_create_ptr); if (module_sp) { diff --git a/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt b/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt index 4c11d21b3e5ae..8574df58b4ada 100644 --- a/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt +++ b/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt @@ -3,7 +3,6 @@ add_lldb_library(lldbPluginProcessFreeBSD NativeRegisterContextFreeBSD.cpp NativeRegisterContextFreeBSD_arm.cpp NativeRegisterContextFreeBSD_arm64.cpp - NativeRegisterContextFreeBSD_mips64.cpp NativeRegisterContextFreeBSD_powerpc.cpp NativeRegisterContextFreeBSD_x86_64.cpp NativeThreadFreeBSD.cpp diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp index c434a3a91ffe3..7dd3d807d2096 100644 --- a/lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp +++ b/lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp @@ -996,10 +996,6 @@ Status NativeProcessFreeBSD::ReinitializeThreads() { return error; } -bool NativeProcessFreeBSD::SupportHardwareSingleStepping() const { - return !m_arch.IsMIPS(); -} - void NativeProcessFreeBSD::MonitorClone(::pid_t child_pid, bool is_vfork, NativeThreadFreeBSD &parent_thread) { Log *log = GetLog(POSIXLog::Process); diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.h b/lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.h index a6ecc5ce3ca16..fb7372817265d 100644 --- a/lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.h +++ b/lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.h @@ -90,8 +90,6 @@ class NativeProcessFreeBSD : public NativeProcessELF, static Status PtraceWrapper(int req, lldb::pid_t pid, void *addr = nullptr, int data = 0, int *result = nullptr); - bool SupportHardwareSingleStepping() const; - llvm::Expected SaveCore(llvm::StringRef path_hint) override; protected: diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp index d21dac221aa22..f50b28e2ebd1d 100644 --- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp +++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp @@ -54,12 +54,8 @@ NativeRegisterContextFreeBSD::CreateHostNativeRegisterContextFreeBSD( NativeRegisterContextFreeBSD_arm64::NativeRegisterContextFreeBSD_arm64( const ArchSpec &target_arch, NativeThreadFreeBSD &native_thread) : NativeRegisterContextRegisterInfo( - native_thread, new RegisterInfoPOSIX_arm64(target_arch, 0)) -#ifdef LLDB_HAS_FREEBSD_WATCHPOINT - , - m_read_dbreg(false) -#endif -{ + native_thread, new RegisterInfoPOSIX_arm64(target_arch, 0)), + m_read_dbreg(false) { g_register_flags_detector.UpdateRegisterInfo( GetRegisterInfoInterface().GetRegisterInfo(), GetRegisterInfoInterface().GetRegisterCount()); @@ -225,7 +221,6 @@ Status NativeRegisterContextFreeBSD_arm64::WriteAllRegisterValues( llvm::Error NativeRegisterContextFreeBSD_arm64::CopyHardwareWatchpointsFrom( NativeRegisterContextFreeBSD &source) { -#ifdef LLDB_HAS_FREEBSD_WATCHPOINT auto &r_source = static_cast(source); llvm::Error error = r_source.ReadHardwareDebugInfo(); if (error) @@ -240,13 +235,9 @@ llvm::Error NativeRegisterContextFreeBSD_arm64::CopyHardwareWatchpointsFrom( // on FreeBSD this writes both breakpoints and watchpoints return WriteHardwareDebugRegs(eDREGTypeWATCH); -#else - return llvm::Error::success(); -#endif } llvm::Error NativeRegisterContextFreeBSD_arm64::ReadHardwareDebugInfo() { -#ifdef LLDB_HAS_FREEBSD_WATCHPOINT Log *log = GetLog(POSIXLog::Registers); // we're fully stateful, so no need to reread control registers ever @@ -267,16 +258,10 @@ llvm::Error NativeRegisterContextFreeBSD_arm64::ReadHardwareDebugInfo() { m_read_dbreg = true; return llvm::Error::success(); -#else - return llvm::createStringError( - llvm::inconvertibleErrorCode(), - "Hardware breakpoints/watchpoints require FreeBSD 14.0"); -#endif } llvm::Error NativeRegisterContextFreeBSD_arm64::WriteHardwareDebugRegs(DREGType) { -#ifdef LLDB_HAS_FREEBSD_WATCHPOINT assert(m_read_dbreg && "dbregs must be read before writing them back"); // copy data from m_*_regs to m_dbreg before writing it back @@ -292,11 +277,6 @@ NativeRegisterContextFreeBSD_arm64::WriteHardwareDebugRegs(DREGType) { return NativeProcessFreeBSD::PtraceWrapper(PT_SETDBREGS, m_thread.GetID(), &m_dbreg) .ToError(); -#else - return llvm::createStringError( - llvm::inconvertibleErrorCode(), - "Hardware breakpoints/watchpoints require FreeBSD 14.0"); -#endif } #endif // defined (__aarch64__) diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h index 80ed328f08bdf..20cbd643e95cf 100644 --- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h +++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h @@ -23,10 +23,6 @@ #include -#if __FreeBSD_version >= 1300139 -#define LLDB_HAS_FREEBSD_WATCHPOINT 1 -#endif - namespace lldb_private { namespace process_freebsd { @@ -64,10 +60,8 @@ class NativeRegisterContextFreeBSD_arm64 // and sizes, so we do not have to worry about these (and we have // a unittest to assert that). std::array m_reg_data; -#ifdef LLDB_HAS_FREEBSD_WATCHPOINT dbreg m_dbreg; bool m_read_dbreg; -#endif Status ReadRegisterSet(uint32_t set); Status WriteRegisterSet(uint32_t set); diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_mips64.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_mips64.cpp deleted file mode 100644 index 2e0f5b707884f..0000000000000 --- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_mips64.cpp +++ /dev/null @@ -1,240 +0,0 @@ -//===-- NativeRegisterContextFreeBSD_mips64.cpp ---------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#if defined(__mips64__) - -#include "NativeRegisterContextFreeBSD_mips64.h" - -#include "lldb/Utility/DataBufferHeap.h" -#include "lldb/Utility/RegisterValue.h" -#include "lldb/Utility/Status.h" - -#include "Plugins/Process/FreeBSD/NativeProcessFreeBSD.h" -#include "Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h" - -// clang-format off -#include -#include -#include -// clang-format on -#include - -using namespace lldb; -using namespace lldb_private; -using namespace lldb_private::process_freebsd; - -NativeRegisterContextFreeBSD * -NativeRegisterContextFreeBSD::CreateHostNativeRegisterContextFreeBSD( - const ArchSpec &target_arch, NativeThreadFreeBSD &native_thread) { - return new NativeRegisterContextFreeBSD_mips64(target_arch, native_thread); -} - -NativeRegisterContextFreeBSD_mips64::NativeRegisterContextFreeBSD_mips64( - const ArchSpec &target_arch, NativeThreadFreeBSD &native_thread) - : NativeRegisterContextRegisterInfo( - native_thread, new RegisterContextFreeBSD_mips64(target_arch)) {} - -RegisterContextFreeBSD_mips64 & -NativeRegisterContextFreeBSD_mips64::GetRegisterInfo() const { - return static_cast( - *m_register_info_interface_up); -} - -uint32_t NativeRegisterContextFreeBSD_mips64::GetRegisterSetCount() const { - return GetRegisterInfo().GetRegisterSetCount(); -} - -const RegisterSet * -NativeRegisterContextFreeBSD_mips64::GetRegisterSet(uint32_t set_index) const { - return GetRegisterInfo().GetRegisterSet(set_index); -} - -uint32_t NativeRegisterContextFreeBSD_mips64::GetUserRegisterCount() const { - uint32_t count = 0; - for (uint32_t set_index = 0; set_index < GetRegisterSetCount(); ++set_index) - count += GetRegisterSet(set_index)->num_registers; - return count; -} - -std::optional -NativeRegisterContextFreeBSD_mips64::GetSetForNativeRegNum( - uint32_t reg_num) const { - switch (GetRegisterInfoInterface().GetTargetArchitecture().GetMachine()) { - case llvm::Triple::mips64: - if (reg_num >= k_first_gpr_mips64 && reg_num <= k_last_gpr_mips64) - return GPRegSet; - if (reg_num >= k_first_fpr_mips64 && reg_num <= k_last_fpr_mips64) - return FPRegSet; - break; - default: - llvm_unreachable("Unhandled target architecture."); - } - - llvm_unreachable("Register does not belong to any register set"); -} - -Status NativeRegisterContextFreeBSD_mips64::ReadRegisterSet(RegSetKind set) { - switch (set) { - case GPRegSet: - return NativeProcessFreeBSD::PtraceWrapper(PT_GETREGS, m_thread.GetID(), - m_reg_data.data()); - case FPRegSet: - return NativeProcessFreeBSD::PtraceWrapper( - PT_GETFPREGS, m_thread.GetID(), - m_reg_data.data() + GetRegisterInfo().GetGPRSize()); - } - llvm_unreachable("NativeRegisterContextFreeBSD_mips64::ReadRegisterSet"); -} - -Status NativeRegisterContextFreeBSD_mips64::WriteRegisterSet(RegSetKind set) { - switch (set) { - case GPRegSet: - return NativeProcessFreeBSD::PtraceWrapper(PT_SETREGS, m_thread.GetID(), - m_reg_data.data()); - case FPRegSet: - return NativeProcessFreeBSD::PtraceWrapper( - PT_SETFPREGS, m_thread.GetID(), - m_reg_data.data() + GetRegisterInfo().GetGPRSize()); - } - llvm_unreachable("NativeRegisterContextFreeBSD_mips64::WriteRegisterSet"); -} - -Status -NativeRegisterContextFreeBSD_mips64::ReadRegister(const RegisterInfo *reg_info, - RegisterValue ®_value) { - Status error; - - if (!reg_info) { - error = Status::FromErrorString("reg_info NULL"); - return error; - } - - const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; - - if (reg == LLDB_INVALID_REGNUM) - return Status("no lldb regnum for %s", reg_info && reg_info->name - ? reg_info->name - : ""); - - std::optional opt_set = GetSetForNativeRegNum(reg); - if (!opt_set) { - // This is likely an internal register for lldb use only and should not be - // directly queried. - error = Status::FromErrorStringWithFormat( - "register \"%s\" is in unrecognized set", reg_info->name); - return error; - } - - RegSetKind set = *opt_set; - error = ReadRegisterSet(set); - if (error.Fail()) - return error; - - assert(reg_info->byte_offset + reg_info->byte_size <= m_reg_data.size()); - reg_value.SetBytes(m_reg_data.data() + reg_info->byte_offset, - reg_info->byte_size, endian::InlHostByteOrder()); - return error; -} - -Status NativeRegisterContextFreeBSD_mips64::WriteRegister( - const RegisterInfo *reg_info, const RegisterValue ®_value) { - Status error; - - if (!reg_info) - return Status("reg_info NULL"); - - const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; - - if (reg == LLDB_INVALID_REGNUM) - return Status("no lldb regnum for %s", reg_info && reg_info->name - ? reg_info->name - : ""); - - std::optional opt_set = GetSetForNativeRegNum(reg); - if (!opt_set) { - // This is likely an internal register for lldb use only and should not be - // directly queried. - error = Status::FromErrorStringWithFormat( - "register \"%s\" is in unrecognized set", reg_info->name); - return error; - } - - RegSetKind set = *opt_set; - error = ReadRegisterSet(set); - if (error.Fail()) - return error; - - assert(reg_info->byte_offset + reg_info->byte_size <= m_reg_data.size()); - ::memcpy(m_reg_data.data() + reg_info->byte_offset, reg_value.GetBytes(), - reg_info->byte_size); - - return WriteRegisterSet(set); -} - -Status NativeRegisterContextFreeBSD_mips64::ReadAllRegisterValues( - lldb::WritableDataBufferSP &data_sp) { - Status error; - - error = ReadRegisterSet(GPRegSet); - if (error.Fail()) - return error; - - error = ReadRegisterSet(FPRegSet); - if (error.Fail()) - return error; - - data_sp.reset(new DataBufferHeap(m_reg_data.size(), 0)); - uint8_t *dst = data_sp->GetBytes(); - ::memcpy(dst, m_reg_data.data(), m_reg_data.size()); - - return error; -} - -Status NativeRegisterContextFreeBSD_mips64::WriteAllRegisterValues( - const lldb::DataBufferSP &data_sp) { - Status error; - - if (!data_sp) { - error = Status::FromErrorStringWithFormat( - "NativeRegisterContextFreeBSD_mips64::%s invalid data_sp provided", - __FUNCTION__); - return error; - } - - if (data_sp->GetByteSize() != m_reg_data.size()) { - error = Status::FromErrorStringWithFormat( - "NativeRegisterContextFreeBSD_mips64::%s data_sp contained mismatched " - "data size, expected %" PRIu64 ", actual %" PRIu64, - __FUNCTION__, m_reg_data.size(), data_sp->GetByteSize()); - return error; - } - - const uint8_t *src = data_sp->GetBytes(); - if (src == nullptr) { - error = Status::FromErrorStringWithFormat( - "NativeRegisterContextFreeBSD_mips64::%s " - "DataBuffer::GetBytes() returned a null " - "pointer", - __FUNCTION__); - return error; - } - ::memcpy(m_reg_data.data(), src, m_reg_data.size()); - - error = WriteRegisterSet(GPRegSet); - if (error.Fail()) - return error; - - return WriteRegisterSet(FPRegSet); -} - -llvm::Error NativeRegisterContextFreeBSD_mips64::CopyHardwareWatchpointsFrom( - NativeRegisterContextFreeBSD &source) { - return llvm::Error::success(); -} - -#endif // defined (__mips64__) diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_mips64.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_mips64.h deleted file mode 100644 index 286b4fd8d8b99..0000000000000 --- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_mips64.h +++ /dev/null @@ -1,75 +0,0 @@ -//===-- NativeRegisterContextFreeBSD_mips64.h -------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#if defined(__mips64__) - -#ifndef lldb_NativeRegisterContextFreeBSD_mips64_h -#define lldb_NativeRegisterContextFreeBSD_mips64_h - -// clang-format off -#include -#include -// clang-format on - -#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h" -#include "Plugins/Process/Utility/RegisterContextFreeBSD_mips64.h" - -#include -#include - -namespace lldb_private { -namespace process_freebsd { - -class NativeProcessFreeBSD; - -class NativeRegisterContextFreeBSD_mips64 - : public NativeRegisterContextFreeBSD { -public: - NativeRegisterContextFreeBSD_mips64(const ArchSpec &target_arch, - NativeThreadFreeBSD &native_thread); - - uint32_t GetRegisterSetCount() const override; - - uint32_t GetUserRegisterCount() const override; - - const RegisterSet *GetRegisterSet(uint32_t set_index) const override; - - Status ReadRegister(const RegisterInfo *reg_info, - RegisterValue ®_value) override; - - Status WriteRegister(const RegisterInfo *reg_info, - const RegisterValue ®_value) override; - - Status ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override; - - Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override; - - llvm::Error - CopyHardwareWatchpointsFrom(NativeRegisterContextFreeBSD &source) override; - -private: - enum RegSetKind { - GPRegSet, - FPRegSet, - }; - std::array m_reg_data; - - std::optional GetSetForNativeRegNum(uint32_t reg_num) const; - - Status ReadRegisterSet(RegSetKind set); - Status WriteRegisterSet(RegSetKind set); - - RegisterContextFreeBSD_mips64 &GetRegisterInfo() const; -}; - -} // namespace process_freebsd -} // namespace lldb_private - -#endif // #ifndef lldb_NativeRegisterContextFreeBSD_mips64_h - -#endif // defined (__mips64__) diff --git a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp index c7da9f215972f..196cb5a620f32 100644 --- a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp +++ b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp @@ -162,7 +162,7 @@ bool ProcessFreeBSDKernel::DoUpdateThreadList(ThreadList &old_thread_list, int32_t offset_td_name = ReadSignedIntegerFromMemory( FindSymbol("thread_off_td_name"), 4, -1, error); - // fail if we were not able to read any of the offsets + // Fail if we were not able to read any of the offsets. if (offset_p_list == -1 || offset_p_pid == -1 || offset_p_threads == -1 || offset_p_comm == -1 || offset_td_tid == -1 || offset_td_plist == -1 || offset_td_pcb == -1 || offset_td_oncpu == -1 || offset_td_name == -1) @@ -174,8 +174,8 @@ bool ProcessFreeBSDKernel::DoUpdateThreadList(ThreadList &old_thread_list, ReadSignedIntegerFromMemory(FindSymbol("dumptid"), 4, -1, error); lldb::addr_t dumppcb = FindSymbol("dumppcb"); - // stoppcbs is an array of PCBs on all CPUs - // each element is of size pcb_size + // stoppcbs is an array of PCBs on all CPUs. + // Each element is of size pcb_size. int32_t pcbsize = ReadSignedIntegerFromMemory(FindSymbol("pcb_size"), 4, -1, error); lldb::addr_t stoppcbs = FindSymbol("stoppcbs"); @@ -183,20 +183,30 @@ bool ProcessFreeBSDKernel::DoUpdateThreadList(ThreadList &old_thread_list, // from FreeBSD sys/param.h constexpr size_t fbsd_maxcomlen = 19; - // iterate through a linked list of all processes - // allproc is a pointer to the first list element, p_list field - // (found at offset_p_list) specifies the next element + // Iterate through a linked list of all processes. New processes are added + // to the head of this list. Which means that earlier PIDs are actually at + // the end of the list, so we have to walk it backwards. First collect all + // the processes in the list order. + std::vector process_addrs; for (lldb::addr_t proc = ReadPointerFromMemory(FindSymbol("allproc"), error); proc != 0 && proc != LLDB_INVALID_ADDRESS; proc = ReadPointerFromMemory(proc + offset_p_list, error)) { + process_addrs.push_back(proc); + } + + // Processes are in the linked list in descending PID order, so we must walk + // them in reverse to get ascending PID order. + for (auto proc_it = process_addrs.rbegin(); proc_it != process_addrs.rend(); + ++proc_it) { + lldb::addr_t proc = *proc_it; int32_t pid = ReadSignedIntegerFromMemory(proc + offset_p_pid, 4, -1, error); // process' command-line string char comm[fbsd_maxcomlen + 1]; ReadCStringFromMemory(proc + offset_p_comm, comm, sizeof(comm), error); - // iterate through a linked list of all process' threads + // Iterate through a linked list of all process' threads // the initial thread is found in process' p_threads, subsequent // elements are linked via td_plist field for (lldb::addr_t td = @@ -214,7 +224,7 @@ bool ProcessFreeBSDKernel::DoUpdateThreadList(ThreadList &old_thread_list, ReadCStringFromMemory(td + offset_td_name, thread_name, sizeof(thread_name), error); - // if we failed to read TID, ignore this thread + // If we failed to read TID, ignore this thread. if (tid == -1) continue; @@ -224,7 +234,7 @@ bool ProcessFreeBSDKernel::DoUpdateThreadList(ThreadList &old_thread_list, thread_desc += thread_name; } - // roughly: + // Roughly: // 1. if the thread crashed, its PCB is going to be at "dumppcb" // 2. if the thread was on CPU, its PCB is going to be on the CPU // 3. otherwise, its PCB is in the thread struct @@ -233,8 +243,8 @@ bool ProcessFreeBSDKernel::DoUpdateThreadList(ThreadList &old_thread_list, pcb_addr = dumppcb; thread_desc += " (crashed)"; } else if (oncpu != -1) { - // if we managed to read stoppcbs and pcb_size, use them to find - // the correct PCB + // If we managed to read stoppcbs and pcb_size, use them to find + // the correct PCB. if (stoppcbs != LLDB_INVALID_ADDRESS && pcbsize > 0) pcb_addr = stoppcbs + oncpu * pcbsize; else diff --git a/lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp b/lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp index a7352e625a07c..4144beae21937 100644 --- a/lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp +++ b/lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp @@ -770,26 +770,6 @@ void NativeProcessLinux::MonitorSIGTRAP(const siginfo_t &info, } case SI_KERNEL: -#if defined __mips__ - // For mips there is no special signal for watchpoint So we check for - // watchpoint in kernel trap - { - // If a watchpoint was hit, report it - uint32_t wp_index; - Status error = thread.GetRegisterContext().GetWatchpointHitIndex( - wp_index, LLDB_INVALID_ADDRESS); - if (error.Fail()) - LLDB_LOG(log, - "received error while checking for watchpoint hits, pid = " - "{0}, error = {1}", - thread.GetID(), error); - if (wp_index != LLDB_INVALID_INDEX32) { - MonitorWatchpoint(thread, wp_index); - break; - } - } -// NO BREAK -#endif case TRAP_BRKPT: MonitorBreakpoint(thread); break; @@ -1000,7 +980,7 @@ bool NativeProcessLinux::MonitorClone(NativeThreadLinux &parent, } bool NativeProcessLinux::SupportHardwareSingleStepping() const { - if (m_arch.IsMIPS() || m_arch.GetMachine() == llvm::Triple::arm || + if (m_arch.GetMachine() == llvm::Triple::arm || m_arch.GetTriple().isRISCV() || m_arch.GetTriple().isLoongArch()) return false; return true; diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt index b1e326ec064e4..9148465607b7d 100644 --- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt +++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt @@ -27,7 +27,6 @@ add_lldb_library(lldbPluginProcessUtility RegisterContextDarwin_x86_64.cpp RegisterContextDummy.cpp RegisterContextFreeBSD_i386.cpp - RegisterContextFreeBSD_mips64.cpp RegisterContextFreeBSD_powerpc.cpp RegisterContextFreeBSD_x86_64.cpp RegisterContextHistory.cpp @@ -44,7 +43,6 @@ add_lldb_library(lldbPluginProcessUtility RegisterContextPOSIX_arm.cpp RegisterContextPOSIX_arm64.cpp RegisterContextPOSIX_loongarch64.cpp - RegisterContextPOSIX_mips64.cpp RegisterContextPOSIX_riscv32.cpp RegisterContextPOSIX_powerpc.cpp RegisterContextPOSIX_ppc64le.cpp diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_i386.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_i386.cpp index df6a82c11255e..841ae170466b5 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_i386.cpp +++ b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_i386.cpp @@ -12,7 +12,7 @@ using namespace lldb_private; using namespace lldb; -// http://svnweb.freebsd.org/base/head/sys/x86/include/reg.h +// https://cgit.freebsd.org/src/tree/sys/x86/include/reg.h?h=stable/14 struct GPR { uint32_t fs; uint32_t es; diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp deleted file mode 100644 index 1f52c09df12e7..0000000000000 --- a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp +++ /dev/null @@ -1,179 +0,0 @@ -//===-- RegisterContextFreeBSD_mips64.cpp ---------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===---------------------------------------------------------------------===// - -#include "RegisterContextFreeBSD_mips64.h" -#include "RegisterContextPOSIX_mips64.h" -#include "lldb-mips-freebsd-register-enums.h" -#include - -using namespace lldb_private; -using namespace lldb; - -static const uint32_t g_gp_regnums_mips64[] = { - gpr_zero_mips64, gpr_r1_mips64, gpr_r2_mips64, gpr_r3_mips64, - gpr_r4_mips64, gpr_r5_mips64, gpr_r6_mips64, gpr_r7_mips64, - gpr_r8_mips64, gpr_r9_mips64, gpr_r10_mips64, gpr_r11_mips64, - gpr_r12_mips64, gpr_r13_mips64, gpr_r14_mips64, gpr_r15_mips64, - gpr_r16_mips64, gpr_r17_mips64, gpr_r18_mips64, gpr_r19_mips64, - gpr_r20_mips64, gpr_r21_mips64, gpr_r22_mips64, gpr_r23_mips64, - gpr_r24_mips64, gpr_r25_mips64, gpr_r26_mips64, gpr_r27_mips64, - gpr_gp_mips64, gpr_sp_mips64, gpr_r30_mips64, gpr_ra_mips64, - gpr_sr_mips64, gpr_mullo_mips64, gpr_mulhi_mips64, gpr_badvaddr_mips64, - gpr_cause_mips64, gpr_pc_mips64, gpr_ic_mips64, gpr_dummy_mips64, - LLDB_INVALID_REGNUM // register sets need to end with this flag -}; - -static_assert((sizeof(g_gp_regnums_mips64) / sizeof(g_gp_regnums_mips64[0])) - - 1 == - k_num_gpr_registers_mips64, - "g_gp_regnums_mips64 has wrong number of register infos"); - -const uint32_t g_fp_regnums_mips64[] = { - fpr_f0_mips64, fpr_f1_mips64, fpr_f2_mips64, fpr_f3_mips64, - fpr_f4_mips64, fpr_f5_mips64, fpr_f6_mips64, fpr_f7_mips64, - fpr_f8_mips64, fpr_f9_mips64, fpr_f10_mips64, fpr_f11_mips64, - fpr_f12_mips64, fpr_f13_mips64, fpr_f14_mips64, fpr_f15_mips64, - fpr_f16_mips64, fpr_f17_mips64, fpr_f18_mips64, fpr_f19_mips64, - fpr_f20_mips64, fpr_f21_mips64, fpr_f22_mips64, fpr_f23_mips64, - fpr_f24_mips64, fpr_f25_mips64, fpr_f26_mips64, fpr_f27_mips64, - fpr_f28_mips64, fpr_f29_mips64, fpr_f30_mips64, fpr_f31_mips64, - fpr_fcsr_mips64, fpr_fir_mips64, - LLDB_INVALID_REGNUM // register sets need to end with this flag -}; - -static_assert((sizeof(g_fp_regnums_mips64) / sizeof(g_fp_regnums_mips64[0])) - - 1 == - k_num_fpr_registers_mips64, - "g_fp_regnums_mips64 has wrong number of register infos"); - -// Number of register sets provided by this context. -constexpr size_t k_num_register_sets = 2; - -static const RegisterSet g_reg_sets_mips64[k_num_register_sets] = { - {"General Purpose Registers", "gpr", k_num_gpr_registers_mips64, - g_gp_regnums_mips64}, - {"Floating Point Registers", "fpu", k_num_fpr_registers_mips64, - g_fp_regnums_mips64}, -}; - -// http://svnweb.freebsd.org/base/head/sys/mips/include/regnum.h -typedef struct _GPR { - uint64_t zero; - uint64_t r1; - uint64_t r2; - uint64_t r3; - uint64_t r4; - uint64_t r5; - uint64_t r6; - uint64_t r7; - uint64_t r8; - uint64_t r9; - uint64_t r10; - uint64_t r11; - uint64_t r12; - uint64_t r13; - uint64_t r14; - uint64_t r15; - uint64_t r16; - uint64_t r17; - uint64_t r18; - uint64_t r19; - uint64_t r20; - uint64_t r21; - uint64_t r22; - uint64_t r23; - uint64_t r24; - uint64_t r25; - uint64_t r26; - uint64_t r27; - uint64_t gp; - uint64_t sp; - uint64_t r30; - uint64_t ra; - uint64_t sr; - uint64_t mullo; - uint64_t mulhi; - uint64_t badvaddr; - uint64_t cause; - uint64_t pc; - uint64_t ic; - uint64_t dummy; -} GPR_freebsd_mips; - -typedef struct _FPR { - uint64_t f0; - uint64_t f1; - uint64_t f2; - uint64_t f3; - uint64_t f4; - uint64_t f5; - uint64_t f6; - uint64_t f7; - uint64_t f8; - uint64_t f9; - uint64_t f10; - uint64_t f11; - uint64_t f12; - uint64_t f13; - uint64_t f14; - uint64_t f15; - uint64_t f16; - uint64_t f17; - uint64_t f18; - uint64_t f19; - uint64_t f20; - uint64_t f21; - uint64_t f22; - uint64_t f23; - uint64_t f24; - uint64_t f25; - uint64_t f26; - uint64_t f27; - uint64_t f28; - uint64_t f29; - uint64_t f30; - uint64_t f31; - uint64_t fcsr; - uint64_t fir; -} FPR_freebsd_mips; - -// Include RegisterInfos_mips64 to declare our g_register_infos_mips64 -// structure. -#define DECLARE_REGISTER_INFOS_MIPS64_STRUCT -#include "RegisterInfos_mips64.h" -#undef DECLARE_REGISTER_INFOS_MIPS64_STRUCT - -RegisterContextFreeBSD_mips64::RegisterContextFreeBSD_mips64( - const ArchSpec &target_arch) - : RegisterInfoInterface(target_arch) {} - -size_t RegisterContextFreeBSD_mips64::GetGPRSize() const { - return sizeof(GPR_freebsd_mips); -} - -const RegisterSet * -RegisterContextFreeBSD_mips64::GetRegisterSet(size_t set) const { - // Check if RegisterSet is available - if (set < k_num_register_sets) - return &g_reg_sets_mips64[set]; - return nullptr; -} - -size_t RegisterContextFreeBSD_mips64::GetRegisterSetCount() const { - return k_num_register_sets; -} - -const RegisterInfo *RegisterContextFreeBSD_mips64::GetRegisterInfo() const { - assert(GetTargetArchitecture().GetCore() == ArchSpec::eCore_mips64); - return g_register_infos_mips64; -} - -uint32_t RegisterContextFreeBSD_mips64::GetRegisterCount() const { - return static_cast(sizeof(g_register_infos_mips64) / - sizeof(g_register_infos_mips64[0])); -} diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.h b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.h deleted file mode 100644 index 39968eacf4755..0000000000000 --- a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.h +++ /dev/null @@ -1,30 +0,0 @@ -//===-- RegisterContextFreeBSD_mips64.h -------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTFREEBSD_MIPS64_H -#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTFREEBSD_MIPS64_H - -#include "RegisterInfoInterface.h" - -class RegisterContextFreeBSD_mips64 - : public lldb_private::RegisterInfoInterface { -public: - RegisterContextFreeBSD_mips64(const lldb_private::ArchSpec &target_arch); - - size_t GetGPRSize() const override; - - const lldb_private::RegisterSet *GetRegisterSet(size_t set) const; - - size_t GetRegisterSetCount() const; - - const lldb_private::RegisterInfo *GetRegisterInfo() const override; - - uint32_t GetRegisterCount() const override; -}; - -#endif diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_powerpc.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_powerpc.cpp index d8dfa434335be..cd422556752fc 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_powerpc.cpp +++ b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_powerpc.cpp @@ -13,7 +13,7 @@ using namespace lldb_private; using namespace lldb; -// http://svnweb.freebsd.org/base/head/sys/powerpc/include/reg.h +// https://cgit.freebsd.org/src/tree/sys/powerpc/include/reg.h typedef struct _GPR64 { uint64_t r0; uint64_t r1; diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_x86_64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_x86_64.cpp index c361b2abb726b..2a382175acfb3 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_x86_64.cpp +++ b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_x86_64.cpp @@ -15,7 +15,7 @@ using namespace lldb_private; using namespace lldb; -// http://svnweb.freebsd.org/base/head/sys/x86/include/reg.h +// https://cgit.freebsd.org/src/tree/sys/x86/include/reg.h typedef struct _GPR { uint64_t r15; uint64_t r14; diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp deleted file mode 100644 index 3685d6ac72ad3..0000000000000 --- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp +++ /dev/null @@ -1,138 +0,0 @@ -//===-- RegisterContextPOSIX_mips64.cpp -----------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include -#include -#include - -#include "lldb/Target/Process.h" -#include "lldb/Target/Target.h" -#include "lldb/Target/Thread.h" -#include "lldb/Utility/DataBufferHeap.h" -#include "lldb/Utility/DataExtractor.h" -#include "lldb/Utility/Endian.h" -#include "lldb/Utility/RegisterValue.h" -#include "lldb/Utility/Scalar.h" -#include "llvm/Support/Compiler.h" - -#include "RegisterContextPOSIX_mips64.h" -#include "RegisterContextFreeBSD_mips64.h" - -using namespace lldb_private; -using namespace lldb; - -bool RegisterContextPOSIX_mips64::IsGPR(unsigned reg) { - return reg < m_registers_count[gpr_registers_count]; // GPR's come first. -} - -bool RegisterContextPOSIX_mips64::IsFPR(unsigned reg) { - int set = GetRegisterSetCount(); - if (set > 1) - return reg < (m_registers_count[fpr_registers_count] - + m_registers_count[gpr_registers_count]); - return false; -} - -RegisterContextPOSIX_mips64::RegisterContextPOSIX_mips64( - Thread &thread, uint32_t concrete_frame_idx, - RegisterInfoInterface *register_info) - : RegisterContext(thread, concrete_frame_idx) { - m_register_info_up.reset(register_info); - m_num_registers = GetRegisterCount(); - int set = GetRegisterSetCount(); - - const RegisterSet *reg_set_ptr; - for(int i = 0; i < set; ++i) { - reg_set_ptr = GetRegisterSet(i); - m_registers_count[i] = reg_set_ptr->num_registers; - } - - assert(m_num_registers == - static_cast(m_registers_count[gpr_registers_count] + - m_registers_count[fpr_registers_count] + - m_registers_count[msa_registers_count])); -} - -RegisterContextPOSIX_mips64::~RegisterContextPOSIX_mips64() = default; - -void RegisterContextPOSIX_mips64::Invalidate() {} - -void RegisterContextPOSIX_mips64::InvalidateAllRegisters() {} - -unsigned RegisterContextPOSIX_mips64::GetRegisterOffset(unsigned reg) { - assert(reg < m_num_registers && "Invalid register number."); - return GetRegisterInfo()[reg].byte_offset; -} - -unsigned RegisterContextPOSIX_mips64::GetRegisterSize(unsigned reg) { - assert(reg < m_num_registers && "Invalid register number."); - return GetRegisterInfo()[reg].byte_size; -} - -size_t RegisterContextPOSIX_mips64::GetRegisterCount() { - return m_register_info_up->GetRegisterCount(); -} - -size_t RegisterContextPOSIX_mips64::GetGPRSize() { - return m_register_info_up->GetGPRSize(); -} - -const RegisterInfo *RegisterContextPOSIX_mips64::GetRegisterInfo() { - // Commonly, this method is overridden and g_register_infos is copied and - // specialized. So, use GetRegisterInfo() rather than g_register_infos in - // this scope. - return m_register_info_up->GetRegisterInfo(); -} - -const RegisterInfo * -RegisterContextPOSIX_mips64::GetRegisterInfoAtIndex(size_t reg) { - if (reg < m_num_registers) - return &GetRegisterInfo()[reg]; - else - return nullptr; -} - -size_t RegisterContextPOSIX_mips64::GetRegisterSetCount() { - const auto *context = static_cast( - m_register_info_up.get()); - return context->GetRegisterSetCount(); -} - -const RegisterSet *RegisterContextPOSIX_mips64::GetRegisterSet(size_t set) { - const auto *context = static_cast( - m_register_info_up.get()); - return context->GetRegisterSet(set); -} - -const char *RegisterContextPOSIX_mips64::GetRegisterName(unsigned reg) { - assert(reg < m_num_registers && "Invalid register offset."); - return GetRegisterInfo()[reg].name; -} - -bool RegisterContextPOSIX_mips64::IsRegisterSetAvailable(size_t set_index) { - size_t num_sets = GetRegisterSetCount(); - - return (set_index < num_sets); -} - -// Used when parsing DWARF and EH frame information and any other object file -// sections that contain register numbers in them. -uint32_t RegisterContextPOSIX_mips64::ConvertRegisterKindToRegisterNumber( - lldb::RegisterKind kind, uint32_t num) { - const uint32_t num_regs = m_num_registers; - - assert(kind < kNumRegisterKinds); - for (uint32_t reg_idx = 0; reg_idx < num_regs; ++reg_idx) { - const RegisterInfo *reg_info = GetRegisterInfoAtIndex(reg_idx); - - if (reg_info->kinds[kind] == num) - return reg_idx; - } - - return LLDB_INVALID_REGNUM; -} diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h deleted file mode 100644 index b66dc3f445249..0000000000000 --- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h +++ /dev/null @@ -1,78 +0,0 @@ -//===-- RegisterContextPOSIX_mips64.h ---------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_MIPS64_H -#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_MIPS64_H - -#include "RegisterContext_mips.h" -#include "RegisterInfoInterface.h" -#include "lldb/Target/RegisterContext.h" -#include "lldb/Utility/Log.h" - -class RegisterContextPOSIX_mips64 : public lldb_private::RegisterContext { -public: - - enum Register_count{ - gpr_registers_count = 0, - fpr_registers_count, - msa_registers_count, - register_set_count - }; - - RegisterContextPOSIX_mips64( - lldb_private::Thread &thread, uint32_t concrete_frame_idx, - lldb_private::RegisterInfoInterface *register_info); - - ~RegisterContextPOSIX_mips64() override; - - void Invalidate(); - - void InvalidateAllRegisters() override; - - size_t GetRegisterCount() override; - - virtual size_t GetGPRSize(); - - virtual unsigned GetRegisterSize(unsigned reg); - - virtual unsigned GetRegisterOffset(unsigned reg); - - const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override; - - size_t GetRegisterSetCount() override; - - const lldb_private::RegisterSet *GetRegisterSet(size_t set) override; - - const char *GetRegisterName(unsigned reg); - - uint32_t ConvertRegisterKindToRegisterNumber(lldb::RegisterKind kind, - uint32_t num) override; - -protected: - uint32_t m_num_registers; - uint8_t m_registers_count[register_set_count]; - std::unique_ptr - m_register_info_up; // Register Info Interface (FreeBSD or Linux) - - // Determines if an extended register set is supported on the processor - // running the inferior process. - virtual bool IsRegisterSetAvailable(size_t set_index); - - virtual const lldb_private::RegisterInfo *GetRegisterInfo(); - - bool IsGPR(unsigned reg); - - bool IsFPR(unsigned reg); - - virtual bool ReadGPR() = 0; - virtual bool ReadFPR() = 0; - virtual bool WriteGPR() = 0; - virtual bool WriteFPR() = 0; -}; - -#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_MIPS64_H diff --git a/lldb/source/Plugins/Process/Utility/StopInfoMachException.h b/lldb/source/Plugins/Process/Utility/StopInfoMachException.h index 26f93e0bb348f..147d53ad31e7e 100644 --- a/lldb/source/Plugins/Process/Utility/StopInfoMachException.h +++ b/lldb/source/Plugins/Process/Utility/StopInfoMachException.h @@ -9,6 +9,7 @@ #ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_STOPINFOMACHEXCEPTION_H #define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_STOPINFOMACHEXCEPTION_H +#include #include #include @@ -48,6 +49,33 @@ class StopInfoMachException : public StopInfo { const char *GetDescription() override; + uint32_t GetStopReasonDataCount() const override { + // We return the Exception Type as the first element, then the code and + // subcode. But we don't store any further exception data, so we can't + // return more than these three elements regardless of the data count. + // Not many exceptions we deal with have more than code & subcode, however + // so fixing that isn't urgent. + return std::min((uint32_t)3, m_exc_data_count + 1); + } + + uint64_t GetStopReasonDataAtIndex(uint32_t idx) override { + // FIXME: We really should return all the exception data, but for now we + // just cheese out and return only the exception type. + if (idx >= GetStopReasonDataCount()) + return 0; + + switch (idx) { + case 0: + return GetValue(); + case 1: + return m_exc_code; + case 2: + return m_exc_subcode; + default: + return 0; + } + } + // Returns the fault address, iff this is a EXC_ARM_MTE_TAG_FAULT. std::optional GetTagFaultAddress() const; diff --git a/lldb/source/Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h b/lldb/source/Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h deleted file mode 100644 index 000f6e3847e77..0000000000000 --- a/lldb/source/Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h +++ /dev/null @@ -1,103 +0,0 @@ -//===-- lldb-mips-freebsd-register-enums.h ----------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_MIPS_FREEBSD_REGISTER_ENUMS_H -#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_MIPS_FREEBSD_REGISTER_ENUMS_H - -namespace lldb_private { -// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB) - -// Internal codes for all mips registers. -enum { - k_first_gpr_mips64, - gpr_zero_mips64 = k_first_gpr_mips64, - gpr_r1_mips64, - gpr_r2_mips64, - gpr_r3_mips64, - gpr_r4_mips64, - gpr_r5_mips64, - gpr_r6_mips64, - gpr_r7_mips64, - gpr_r8_mips64, - gpr_r9_mips64, - gpr_r10_mips64, - gpr_r11_mips64, - gpr_r12_mips64, - gpr_r13_mips64, - gpr_r14_mips64, - gpr_r15_mips64, - gpr_r16_mips64, - gpr_r17_mips64, - gpr_r18_mips64, - gpr_r19_mips64, - gpr_r20_mips64, - gpr_r21_mips64, - gpr_r22_mips64, - gpr_r23_mips64, - gpr_r24_mips64, - gpr_r25_mips64, - gpr_r26_mips64, - gpr_r27_mips64, - gpr_gp_mips64, - gpr_sp_mips64, - gpr_r30_mips64, - gpr_ra_mips64, - gpr_sr_mips64, - gpr_mullo_mips64, - gpr_mulhi_mips64, - gpr_badvaddr_mips64, - gpr_cause_mips64, - gpr_pc_mips64, - gpr_ic_mips64, - gpr_dummy_mips64, - k_last_gpr_mips64 = gpr_dummy_mips64, - - k_first_fpr_mips64, - fpr_f0_mips64 = k_first_fpr_mips64, - fpr_f1_mips64, - fpr_f2_mips64, - fpr_f3_mips64, - fpr_f4_mips64, - fpr_f5_mips64, - fpr_f6_mips64, - fpr_f7_mips64, - fpr_f8_mips64, - fpr_f9_mips64, - fpr_f10_mips64, - fpr_f11_mips64, - fpr_f12_mips64, - fpr_f13_mips64, - fpr_f14_mips64, - fpr_f15_mips64, - fpr_f16_mips64, - fpr_f17_mips64, - fpr_f18_mips64, - fpr_f19_mips64, - fpr_f20_mips64, - fpr_f21_mips64, - fpr_f22_mips64, - fpr_f23_mips64, - fpr_f24_mips64, - fpr_f25_mips64, - fpr_f26_mips64, - fpr_f27_mips64, - fpr_f28_mips64, - fpr_f29_mips64, - fpr_f30_mips64, - fpr_f31_mips64, - fpr_fcsr_mips64, - fpr_fir_mips64, - k_last_fpr_mips64 = fpr_fir_mips64, - - k_num_registers_mips64, - - k_num_gpr_registers_mips64 = k_last_gpr_mips64 - k_first_gpr_mips64 + 1, - k_num_fpr_registers_mips64 = k_last_fpr_mips64 - k_first_fpr_mips64 + 1, -}; -} // namespace lldb_private -#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_MIPS_FREEBSD_REGISTER_ENUMS_H diff --git a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt index 0bc26bb0efbe3..73d2b9ac9957b 100644 --- a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt +++ b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt @@ -4,7 +4,6 @@ add_lldb_library(lldbPluginProcessElfCore PLUGIN RegisterContextLinuxCore_x86_64.cpp RegisterContextPOSIXCore_arm.cpp RegisterContextPOSIXCore_arm64.cpp - RegisterContextPOSIXCore_mips64.cpp RegisterContextPOSIXCore_powerpc.cpp RegisterContextPOSIXCore_ppc64le.cpp RegisterContextPOSIXCore_s390x.cpp diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp index 5e4c67af059db..4491d5a036e4e 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp @@ -282,9 +282,14 @@ Status ProcessElfCore::DoLoadCore() { break; } } - if (exe_header_addr.has_value()) - exe_module_sp = ReadModuleFromMemory(exe_module_spec.GetFileSpec(), - *exe_header_addr); + if (exe_header_addr) { + if (llvm::Expected module_sp_or_err = + ReadModuleFromMemory(exe_module_spec.GetFileSpec(), + *exe_header_addr)) + exe_module_sp = *module_sp_or_err; + else + llvm::consumeError(module_sp_or_err.takeError()); + } } if (exe_module_sp) GetTarget().SetExecutableModule(exe_module_sp, eLoadDependentsNo); @@ -669,7 +674,6 @@ ProcessElfCore::parseSegment(const DataExtractor &segment) { llvm::Error ProcessElfCore::parseFreeBSDNotes(llvm::ArrayRef notes) { ArchSpec arch = GetArchitecture(); bool lp64 = (arch.GetMachine() == llvm::Triple::aarch64 || - arch.GetMachine() == llvm::Triple::mips64 || arch.GetMachine() == llvm::Triple::ppc64 || arch.GetMachine() == llvm::Triple::x86_64); bool have_prstatus = false; diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_mips64.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_mips64.cpp deleted file mode 100644 index 56e68742ead77..0000000000000 --- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_mips64.cpp +++ /dev/null @@ -1,91 +0,0 @@ -//===-- RegisterContextPOSIXCore_mips64.cpp -------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "RegisterContextPOSIXCore_mips64.h" - -#include "lldb/Target/Thread.h" -#include "lldb/Utility/RegisterValue.h" - -#include - -using namespace lldb_private; - -RegisterContextCorePOSIX_mips64::RegisterContextCorePOSIX_mips64( - Thread &thread, RegisterInfoInterface *register_info, - const DataExtractor &gpregset, llvm::ArrayRef notes) - : RegisterContextPOSIX_mips64(thread, 0, register_info) { - m_gpr_buffer = std::make_shared(gpregset.GetDataStart(), - gpregset.GetByteSize()); - m_gpr.SetData(m_gpr_buffer); - m_gpr.SetByteOrder(gpregset.GetByteOrder()); - - DataExtractor fpregset = getRegset( - notes, register_info->GetTargetArchitecture().GetTriple(), FPR_Desc); - m_fpr_buffer = std::make_shared(fpregset.GetDataStart(), - fpregset.GetByteSize()); - m_fpr.SetData(m_fpr_buffer); - m_fpr.SetByteOrder(fpregset.GetByteOrder()); -} - -RegisterContextCorePOSIX_mips64::~RegisterContextCorePOSIX_mips64() = default; - -bool RegisterContextCorePOSIX_mips64::ReadGPR() { return true; } - -bool RegisterContextCorePOSIX_mips64::ReadFPR() { return false; } - -bool RegisterContextCorePOSIX_mips64::WriteGPR() { - assert(0); - return false; -} - -bool RegisterContextCorePOSIX_mips64::WriteFPR() { - assert(0); - return false; -} - -bool RegisterContextCorePOSIX_mips64::ReadRegister(const RegisterInfo *reg_info, - RegisterValue &value) { - - lldb::offset_t offset = reg_info->byte_offset; - lldb_private::ArchSpec arch = m_register_info_up->GetTargetArchitecture(); - uint64_t v; - if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) { - if (reg_info->byte_size == 4 && !(arch.GetMachine() == llvm::Triple::mips64el)) - // In case of 32bit core file, the register data are placed at 4 byte - // offset. - offset = offset / 2; - v = m_gpr.GetMaxU64(&offset, reg_info->byte_size); - value = v; - return true; - } else if (IsFPR(reg_info->kinds[lldb::eRegisterKindLLDB])) { - offset = offset - sizeof(GPR_linux_mips); - v =m_fpr.GetMaxU64(&offset, reg_info->byte_size); - value = v; - return true; - } - return false; -} - -bool RegisterContextCorePOSIX_mips64::ReadAllRegisterValues( - lldb::WritableDataBufferSP &data_sp) { - return false; -} - -bool RegisterContextCorePOSIX_mips64::WriteRegister( - const RegisterInfo *reg_info, const RegisterValue &value) { - return false; -} - -bool RegisterContextCorePOSIX_mips64::WriteAllRegisterValues( - const lldb::DataBufferSP &data_sp) { - return false; -} - -bool RegisterContextCorePOSIX_mips64::HardwareSingleStep(bool enable) { - return false; -} diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_mips64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_mips64.h deleted file mode 100644 index 529b00215e352..0000000000000 --- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_mips64.h +++ /dev/null @@ -1,55 +0,0 @@ -//===-- RegisterContextPOSIXCore_mips64.h -----------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_MIPS64_H -#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_MIPS64_H - -#include "Plugins/Process/Utility/RegisterContextPOSIX_mips64.h" -#include "Plugins/Process/elf-core/RegisterUtilities.h" -#include "lldb/Utility/DataBufferHeap.h" -#include "lldb/Utility/DataExtractor.h" - -class RegisterContextCorePOSIX_mips64 : public RegisterContextPOSIX_mips64 { -public: - RegisterContextCorePOSIX_mips64( - lldb_private::Thread &thread, - lldb_private::RegisterInfoInterface *register_info, - const lldb_private::DataExtractor &gpregset, - llvm::ArrayRef notes); - - ~RegisterContextCorePOSIX_mips64() override; - - bool ReadRegister(const lldb_private::RegisterInfo *reg_info, - lldb_private::RegisterValue &value) override; - - bool WriteRegister(const lldb_private::RegisterInfo *reg_info, - const lldb_private::RegisterValue &value) override; - - bool ReadAllRegisterValues(lldb::WritableDataBufferSP &data_sp) override; - - bool WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override; - - bool HardwareSingleStep(bool enable) override; - -protected: - bool ReadGPR() override; - - bool ReadFPR() override; - - bool WriteGPR() override; - - bool WriteFPR() override; - -private: - lldb::DataBufferSP m_gpr_buffer; - lldb::DataBufferSP m_fpr_buffer; - lldb_private::DataExtractor m_gpr; - lldb_private::DataExtractor m_fpr; -}; - -#endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_MIPS64_H diff --git a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp index 7015c3c65cc7d..b51d34a2614f1 100644 --- a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp +++ b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp @@ -17,7 +17,6 @@ #include "lldb/Utility/ProcessInfo.h" #include "Plugins/Process/Utility/RegisterContextFreeBSD_i386.h" -#include "Plugins/Process/Utility/RegisterContextFreeBSD_mips64.h" #include "Plugins/Process/Utility/RegisterContextFreeBSD_powerpc.h" #include "Plugins/Process/Utility/RegisterContextFreeBSD_x86_64.h" #include "Plugins/Process/Utility/RegisterContextLinux_i386.h" @@ -35,7 +34,6 @@ #include "RegisterContextPOSIXCore_arm.h" #include "RegisterContextPOSIXCore_arm64.h" #include "RegisterContextPOSIXCore_loongarch64.h" -#include "RegisterContextPOSIXCore_mips64.h" #include "RegisterContextPOSIXCore_powerpc.h" #include "RegisterContextPOSIXCore_ppc64le.h" #include "RegisterContextPOSIXCore_riscv32.h" @@ -99,9 +97,6 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame *frame) { case llvm::Triple::ppc64le: reg_interface = new RegisterContextFreeBSD_powerpc64(arch); break; - case llvm::Triple::mips64: - reg_interface = new RegisterContextFreeBSD_mips64(arch); - break; case llvm::Triple::x86: reg_interface = new RegisterContextFreeBSD_i386(arch); break; @@ -205,16 +200,6 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame *frame) { m_thread_reg_ctx_sp = RegisterContextCorePOSIX_riscv64::Create( *this, arch, m_gpregset_data, m_notes); break; - case llvm::Triple::mipsel: - case llvm::Triple::mips: - m_thread_reg_ctx_sp = std::make_shared( - *this, reg_interface, m_gpregset_data, m_notes); - break; - case llvm::Triple::mips64: - case llvm::Triple::mips64el: - m_thread_reg_ctx_sp = std::make_shared( - *this, reg_interface, m_gpregset_data, m_notes); - break; case llvm::Triple::ppc: case llvm::Triple::ppc64: m_thread_reg_ctx_sp = std::make_shared( @@ -286,19 +271,7 @@ ELFLinuxPrStatus::ELFLinuxPrStatus() { } size_t ELFLinuxPrStatus::GetSize(const lldb_private::ArchSpec &arch) { - constexpr size_t mips_linux_pr_status_size_o32 = 96; - constexpr size_t mips_linux_pr_status_size_n32 = 72; constexpr size_t num_ptr_size_members = 10; - if (arch.IsMIPS()) { - std::string abi = arch.GetTargetABI(); - assert(!abi.empty() && "ABI is not set"); - if (abi == "n64") - return sizeof(ELFLinuxPrStatus); - else if (abi == "o32") - return mips_linux_pr_status_size_o32; - // N32 ABI - return mips_linux_pr_status_size_n32; - } switch (arch.GetCore()) { case lldb_private::ArchSpec::eCore_x86_32_i386: case lldb_private::ArchSpec::eCore_x86_32_i486: @@ -386,14 +359,6 @@ ELFLinuxPrPsInfo::ELFLinuxPrPsInfo() { } size_t ELFLinuxPrPsInfo::GetSize(const lldb_private::ArchSpec &arch) { - constexpr size_t mips_linux_pr_psinfo_size_o32_n32 = 128; - if (arch.IsMIPS()) { - uint8_t address_byte_size = arch.GetAddressByteSize(); - if (address_byte_size == 8) - return sizeof(ELFLinuxPrPsInfo); - return mips_linux_pr_psinfo_size_o32_n32; - } - switch (arch.GetCore()) { case lldb_private::ArchSpec::eCore_s390x_generic: case lldb_private::ArchSpec::eCore_x86_64_x86_64: @@ -430,15 +395,9 @@ Status ELFLinuxPrPsInfo::Parse(const DataExtractor &data, pr_flag = data.GetAddress(&offset); - if (arch.IsMIPS()) { - // The pr_uid and pr_gid is always 32 bit irrespective of platforms - pr_uid = data.GetU32(&offset); - pr_gid = data.GetU32(&offset); - } else { - // 16 bit on 32 bit platforms, 32 bit on 64 bit platforms - pr_uid = data.GetMaxU64(&offset, data.GetAddressByteSize() >> 1); - pr_gid = data.GetMaxU64(&offset, data.GetAddressByteSize() >> 1); - } + // 16 bit on 32 bit platforms, 32 bit on 64 bit platforms + pr_uid = data.GetMaxU64(&offset, data.GetAddressByteSize() >> 1); + pr_gid = data.GetMaxU64(&offset, data.GetAddressByteSize() >> 1); pr_pid = data.GetU32(&offset); pr_ppid = data.GetU32(&offset); diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index 4fa92af59f8cd..e1f28674ae45c 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -2546,7 +2546,7 @@ void ProcessGDBRemote::RefreshStateAfterStop() { Status ProcessGDBRemote::DoHalt(bool &caused_stop) { Status error; - if (m_public_state.GetValue() == eStateAttaching) { + if (GetPublicState() == eStateAttaching) { // We are being asked to halt during an attach. We used to just close our // file handle and debugserver will go away, but with remote proxies, it // is better to send a positive signal, so let's send the interrupt first... @@ -2595,7 +2595,7 @@ Status ProcessGDBRemote::DoDestroy() { std::string exit_string; if (m_gdb_comm.IsConnected()) { - if (m_public_state.GetValue() != eStateAttaching) { + if (GetPublicState() != eStateAttaching) { llvm::Expected kill_res = m_gdb_comm.KillProcess(GetID()); if (kill_res) { diff --git a/lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp b/lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp index 77a3ba6574cde..c92f80bc166b7 100644 --- a/lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp +++ b/lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.cpp @@ -66,11 +66,11 @@ void ProtocolServerMCP::AcceptCallback(std::unique_ptr socket) { lldb::IOObjectSP io_sp = std::move(socket); auto transport_up = std::make_unique( - io_sp, io_sp, [client_name](llvm::StringRef message) { + m_loop, io_sp, io_sp, [client_name](llvm::StringRef message) { LLDB_LOG(GetLog(LLDBLog::Host), "{0}: {1}", client_name, message); }); - if (auto error = m_server->Accept(m_loop, std::move(transport_up))) + if (auto error = m_server->Accept(std::move(transport_up))) LLDB_LOG_ERROR(log, std::move(error), "{0}:"); } diff --git a/lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h b/lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h index e0f2a6ccea1f5..abcd251337052 100644 --- a/lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h +++ b/lldb/source/Plugins/Protocol/MCP/ProtocolServerMCP.h @@ -13,11 +13,12 @@ #include "lldb/Host/MainLoop.h" #include "lldb/Host/Socket.h" #include "lldb/Protocol/MCP/Server.h" -#include "lldb/Protocol/MCP/Transport.h" -#include +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/Error.h" +#include #include +#include #include -#include #include namespace lldb_private::mcp { diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp index a9945aa14a506..f5fcd3e571d0e 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp @@ -2041,10 +2041,9 @@ static std::optional MakeAPValue(const clang::ASTContext &ast, if (is_integral) return clang::APValue(apint); - bool is_complex; // FIXME: we currently support a limited set of floating point types. // E.g., 16-bit floats are not supported. - if (!clang_type.IsFloatingPointType(is_complex)) + if (!clang_type.IsRealFloatingPointType()) return std::nullopt; return clang::APValue(llvm::APFloat( diff --git a/lldb/source/Plugins/SymbolLocator/DebugSymbols/SymbolLocatorDebugSymbols.cpp b/lldb/source/Plugins/SymbolLocator/DebugSymbols/SymbolLocatorDebugSymbols.cpp index 1e51dda15d6e9..f4b572c9e88ac 100644 --- a/lldb/source/Plugins/SymbolLocator/DebugSymbols/SymbolLocatorDebugSymbols.cpp +++ b/lldb/source/Plugins/SymbolLocator/DebugSymbols/SymbolLocatorDebugSymbols.cpp @@ -208,8 +208,9 @@ std::optional SymbolLocatorDebugSymbols::LocateExecutableObjectFile( // If we found it and it has the correct UUID, let's proceed with // creating a module from the memory contents. - if (image_info.uuid && (!module_spec.GetUUID() || - module_spec.GetUUID() == image_info.uuid)) { + if (image_info.GetUUID() && + (!module_spec.GetUUID() || + module_spec.GetUUID() == image_info.GetUUID())) { success = true; return_module_spec.GetFileSpec() = module_spec.GetFileSpec(); LLDB_LOGF(log, @@ -650,8 +651,9 @@ static int LocateMacOSXFilesUsingDebugSymbols(const ModuleSpec &module_spec, // If we found it and it has the correct UUID, let's proceed with // creating a module from the memory contents. - if (image_info.uuid && (!module_spec.GetUUID() || - module_spec.GetUUID() == image_info.uuid)) { + if (image_info.GetUUID() && + (!module_spec.GetUUID() || + module_spec.GetUUID() == image_info.GetUUID())) { success = true; return_module_spec.GetFileSpec() = module_spec.GetFileSpec(); LLDB_LOGF(log, diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index 478f10a60a865..c9192938fca80 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -3473,38 +3473,15 @@ bool TypeSystemClang::IsReferenceType(lldb::opaque_compiler_type_t type, return false; } -bool TypeSystemClang::IsFloatingPointType(lldb::opaque_compiler_type_t type, - bool &is_complex) { - if (type) { - clang::QualType qual_type(GetCanonicalQualType(type)); +bool TypeSystemClang::IsFloatingPointType(lldb::opaque_compiler_type_t type) { + if (!type) + return false; - if (const clang::BuiltinType *BT = llvm::dyn_cast( - qual_type->getCanonicalTypeInternal())) { - clang::BuiltinType::Kind kind = BT->getKind(); - if (kind >= clang::BuiltinType::Float && - kind <= clang::BuiltinType::LongDouble) { - is_complex = false; - return true; - } - } else if (const clang::ComplexType *CT = - llvm::dyn_cast( - qual_type->getCanonicalTypeInternal())) { - if (IsFloatingPointType(CT->getElementType().getAsOpaquePtr(), - is_complex)) { - is_complex = true; - return true; - } - } else if (const clang::VectorType *VT = llvm::dyn_cast( - qual_type->getCanonicalTypeInternal())) { - if (IsFloatingPointType(VT->getElementType().getAsOpaquePtr(), - is_complex)) { - is_complex = false; - return true; - } - } - } - is_complex = false; - return false; + clang::QualType qual_type(GetCanonicalQualType(type)); + if (qual_type.isNull()) + return false; + + return qual_type->isFloatingType(); } bool TypeSystemClang::IsDefined(lldb::opaque_compiler_type_t type) { diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h index 22a4887dffb0b..40844f67b2445 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h @@ -657,8 +657,7 @@ class TypeSystemClang : public TypeSystem { bool IsDefined(lldb::opaque_compiler_type_t type) override; - bool IsFloatingPointType(lldb::opaque_compiler_type_t type, - bool &is_complex) override; + bool IsFloatingPointType(lldb::opaque_compiler_type_t type) override; unsigned GetPtrAuthKey(lldb::opaque_compiler_type_t type) override; unsigned GetPtrAuthDiscriminator(lldb::opaque_compiler_type_t type) override; diff --git a/lldb/source/Protocol/MCP/Server.cpp b/lldb/source/Protocol/MCP/Server.cpp index a8871ff5c39f0..ecbea4b9022c0 100644 --- a/lldb/source/Protocol/MCP/Server.cpp +++ b/lldb/source/Protocol/MCP/Server.cpp @@ -144,7 +144,7 @@ MCPBinderUP Server::Bind(MCPTransport &transport) { return binder_up; } -llvm::Error Server::Accept(MainLoop &loop, MCPTransportUP transport) { +llvm::Error Server::Accept(MCPTransportUP transport) { MCPBinderUP binder = Bind(*transport); MCPTransport *transport_ptr = transport.get(); binder->OnDisconnect([this, transport_ptr]() { @@ -156,12 +156,10 @@ llvm::Error Server::Accept(MainLoop &loop, MCPTransportUP transport) { Logv("Transport error: {0}", llvm::toString(std::move(err))); }); - auto handle = transport->RegisterMessageHandler(loop, *binder); - if (!handle) - return handle.takeError(); + if (llvm::Error err = transport->RegisterMessageHandler(*binder)) + return err; - m_instances[transport_ptr] = - Client{std::move(*handle), std::move(transport), std::move(binder)}; + m_instances[transport_ptr] = Client{std::move(transport), std::move(binder)}; return llvm::Error::success(); } diff --git a/lldb/source/Protocol/MCP/Transport.cpp b/lldb/source/Protocol/MCP/Transport.cpp index cccdc3b5bd65c..1dc01a9f59008 100644 --- a/lldb/source/Protocol/MCP/Transport.cpp +++ b/lldb/source/Protocol/MCP/Transport.cpp @@ -13,9 +13,10 @@ using namespace lldb_protocol::mcp; using namespace llvm; -Transport::Transport(lldb::IOObjectSP in, lldb::IOObjectSP out, - LogCallback log_callback) - : JSONRPCTransport(in, out), m_log_callback(std::move(log_callback)) {} +Transport::Transport(lldb_private::MainLoop &loop, lldb::IOObjectSP in, + lldb::IOObjectSP out, LogCallback log_callback) + : JSONRPCTransport(loop, in, out), m_log_callback(std::move(log_callback)) { +} void Transport::Log(StringRef message) { if (m_log_callback) diff --git a/lldb/source/Symbol/CompilerType.cpp b/lldb/source/Symbol/CompilerType.cpp index 1a39ea9476390..a568923e83201 100644 --- a/lldb/source/Symbol/CompilerType.cpp +++ b/lldb/source/Symbol/CompilerType.cpp @@ -20,6 +20,7 @@ #include "lldb/Utility/Scalar.h" #include "lldb/Utility/Stream.h" #include "lldb/Utility/StreamString.h" +#include "lldb/lldb-enumerations.h" #include #include @@ -240,15 +241,23 @@ bool CompilerType::ShouldTreatScalarValueAsAddress() const { return false; } -bool CompilerType::IsFloatingPointType(bool &is_complex) const { - if (IsValid()) { +bool CompilerType::IsComplexType() const { + return GetTypeClass() & eTypeClassComplexFloat || + GetTypeClass() & eTypeClassComplexInteger; +} + +bool CompilerType::IsFloatingPointType() const { + if (IsValid()) if (auto type_system_sp = GetTypeSystem()) - return type_system_sp->IsFloatingPointType(m_type, is_complex); - } - is_complex = false; + return type_system_sp->IsFloatingPointType(m_type); + return false; } +bool CompilerType::IsRealFloatingPointType() const { + return IsFloatingPointType() && !IsComplexType() && !IsVectorType(); +} + bool CompilerType::IsDefined() const { if (IsValid()) if (auto type_system_sp = GetTypeSystem()) @@ -328,11 +337,6 @@ bool CompilerType::IsInteger() const { return IsIntegerType(is_signed); } -bool CompilerType::IsFloat() const { - bool is_complex = false; - return IsFloatingPointType(is_complex); -} - bool CompilerType::IsEnumerationType() const { bool is_signed = false; // May be reset by the call below. return IsEnumerationType(is_signed); diff --git a/lldb/source/Target/ExecutionContext.cpp b/lldb/source/Target/ExecutionContext.cpp index b16ff26266c53..e4b2f07d8d8d1 100644 --- a/lldb/source/Target/ExecutionContext.cpp +++ b/lldb/source/Target/ExecutionContext.cpp @@ -160,6 +160,15 @@ lldb_private::GetStoppedExecutionContext( auto thread_sp = exe_ctx_ref_ptr->GetThreadSP(); auto frame_sp = exe_ctx_ref_ptr->GetFrameSP(); + + if (!frame_sp && exe_ctx_ref_ptr->m_frame_list_id) { + return llvm::createStringError( + "attempted to create a StoppedExecutionContext but " + "ScriptedFrameProvider (name = %s - id = %u) is no longer available", + exe_ctx_ref_ptr->m_frame_list_id->first.GetName().str().c_str(), + exe_ctx_ref_ptr->m_frame_list_id->second); + } + return StoppedExecutionContext(target_sp, process_sp, thread_sp, frame_sp, std::move(api_lock), std::move(stop_locker)); } @@ -466,12 +475,25 @@ operator=(const ExecutionContext &exe_ctx) { else m_tid = LLDB_INVALID_THREAD_ID; lldb::StackFrameSP frame_sp(exe_ctx.GetFrameSP()); - if (frame_sp) { - m_stack_id = frame_sp->GetStackID(); - m_frame_list_wp = frame_sp->GetContainingStackFrameList(); + + if (frame_sp && thread_sp) { + lldb::frame_list_id_t frame_list_id = + frame_sp->GetContainingStackFrameListIdentifier(); + auto frame_list_descriptor_or_err = + thread_sp->GetScriptedFrameProviderDescriptorForID(frame_list_id); + if (frame_list_descriptor_or_err) { + m_stack_id = frame_sp->GetStackID(); + m_frame_list_id = {*frame_list_descriptor_or_err, frame_list_id}; + } else { + LLDB_LOG_ERROR(GetLog(LLDBLog::Process), + frame_list_descriptor_or_err.takeError(), + "Failed to fetch scripted frame provider descriptor: {0}"); + m_stack_id.Clear(); + m_frame_list_id.reset(); + } } else { m_stack_id.Clear(); - m_frame_list_wp.reset(); + m_frame_list_id.reset(); } return *this; } @@ -512,11 +534,25 @@ void ExecutionContextRef::SetThreadSP(const lldb::ThreadSP &thread_sp) { } void ExecutionContextRef::SetFrameSP(const lldb::StackFrameSP &frame_sp) { - if (frame_sp) { + if (!frame_sp) { + Clear(); + return; + } + + lldb::ThreadSP thread_sp = frame_sp->GetThread(); + lldb::frame_list_id_t frame_list_id = + frame_sp->GetContainingStackFrameListIdentifier(); + auto frame_list_descriptor_or_err = + thread_sp->GetScriptedFrameProviderDescriptorForID(frame_list_id); + + if (frame_list_descriptor_or_err) { m_stack_id = frame_sp->GetStackID(); - m_frame_list_wp = frame_sp->GetContainingStackFrameList(); - SetThreadSP(frame_sp->GetThread()); + m_frame_list_id = {*frame_list_descriptor_or_err, frame_list_id}; + SetThreadSP(thread_sp); } else { + LLDB_LOG_ERROR(GetLog(LLDBLog::Process), + frame_list_descriptor_or_err.takeError(), + "Failed to fetch scripted frame provider descriptor: {0}"); ClearFrame(); ClearThread(); m_process_wp.reset(); @@ -641,21 +677,23 @@ lldb::ThreadSP ExecutionContextRef::GetThreadSP() const { } lldb::StackFrameSP ExecutionContextRef::GetFrameSP() const { - if (m_stack_id.IsValid()) { - // Try the remembered frame list first to avoid circular dependencies - // during frame provider initialization. - if (auto frame_list_sp = m_frame_list_wp.lock()) { + lldb::ThreadSP thread_sp(GetThreadSP()); + if (!thread_sp || !m_stack_id.IsValid()) + return lldb::StackFrameSP(); + + // Try the remembered frame list first to avoid circular dependencies + // during frame provider initialization. + if (m_frame_list_id) { + if (auto frame_list_sp = + thread_sp->GetFrameListByIdentifier(m_frame_list_id->second)) { if (auto frame_sp = frame_list_sp->GetFrameWithStackID(m_stack_id)) return frame_sp; } - - // Fallback: ask the thread, which might re-trigger the frame provider - // initialization. - lldb::ThreadSP thread_sp(GetThreadSP()); - if (thread_sp) - return thread_sp->GetFrameWithStackID(m_stack_id); } - return lldb::StackFrameSP(); + + // Fallback: ask the thread, which might re-trigger the frame provider + // initialization. + return thread_sp->GetFrameWithStackID(m_stack_id); } ExecutionContext diff --git a/lldb/source/Target/Process.cpp b/lldb/source/Target/Process.cpp index 5056a735c8f57..0cd46f2fc7408 100644 --- a/lldb/source/Target/Process.cpp +++ b/lldb/source/Target/Process.cpp @@ -436,14 +436,15 @@ Process::Process(lldb::TargetSP target_sp, ListenerSP listener_sp, : ProcessProperties(this), Broadcaster((target_sp->GetDebugger().GetBroadcasterManager()), Process::GetStaticBroadcasterClass().str()), - m_target_wp(target_sp), m_public_state(eStateUnloaded), - m_private_state(eStateUnloaded), + m_target_wp(target_sp), m_private_state_broadcaster(nullptr, "lldb.process.internal_state_broadcaster"), m_private_state_control_broadcaster( nullptr, "lldb.process.internal_state_control_broadcaster"), m_private_state_listener_sp( Listener::MakeListener("lldb.process.internal_state_listener")), + m_current_private_state_thread(new PrivateStateThread( + *this, eStateUnloaded, eStateUnloaded, false, "rename-this-thread")), m_mod_id(), m_process_unique_id(0), m_thread_index_id(0), m_thread_id_to_index_id_map(), m_exit_status(-1), m_thread_list_real(*this), m_thread_list(*this), m_thread_plans(*this), @@ -455,14 +456,13 @@ Process::Process(lldb::TargetSP target_sp, ListenerSP listener_sp, m_stdin_forward(false), m_stdout_data(), m_stderr_data(), m_profile_data_comm_mutex(), m_profile_data(), m_iohandler_sync(0), m_memory_cache(*this), m_allocated_memory_cache(*this), - m_should_detach(false), m_next_event_action_up(), m_public_run_lock(), - m_private_run_lock(), m_currently_handling_do_on_removals(false), - m_resume_requested(false), m_interrupt_tid(LLDB_INVALID_THREAD_ID), - m_finalizing(false), m_destructing(false), - m_clear_thread_plans_on_stop(false), m_force_next_event_delivery(false), - m_last_broadcast_state(eStateInvalid), m_destroy_in_process(false), - m_can_interpret_function_calls(false), m_run_thread_plan_lock(), - m_can_jit(eCanJITDontKnow), + m_should_detach(false), m_next_event_action_up(), + m_currently_handling_do_on_removals(false), m_resume_requested(false), + m_interrupt_tid(LLDB_INVALID_THREAD_ID), m_finalizing(false), + m_destructing(false), m_clear_thread_plans_on_stop(false), + m_force_next_event_delivery(false), m_last_broadcast_state(eStateInvalid), + m_destroy_in_process(false), m_can_interpret_function_calls(false), + m_run_thread_plan_lock(), m_can_jit(eCanJITDontKnow), m_crash_info_dict_sp(new StructuredData::Dictionary()) { CheckInWithManager(); @@ -585,8 +585,8 @@ void Process::Finalize(bool destructing) { // contain events that have ProcessSP values in them which can keep this // process around forever. These events need to be cleared out. m_private_state_listener_sp->Clear(); - m_public_run_lock.SetStopped(); - m_private_run_lock.SetStopped(); + SetPublicRunLockToStopped(); + SetPrivateRunLockToStopped(); m_structured_data_plugin_map.clear(); } @@ -689,7 +689,7 @@ StateType Process::WaitForProcessToStop( // We need to toggle the run lock as this won't get done in // SetPublicState() if the process is hijacked. if (hijack_listener_sp && use_run_lock) - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); return state; } @@ -711,7 +711,7 @@ StateType Process::WaitForProcessToStop( // We need to toggle the run lock as this won't get done in // SetPublicState() if the process is hijacked. if (hijack_listener_sp && use_run_lock) - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); return state; case eStateStopped: if (Process::ProcessEventData::GetRestartedFromEvent(event_sp.get())) @@ -720,7 +720,7 @@ StateType Process::WaitForProcessToStop( // We need to toggle the run lock as this won't get done in // SetPublicState() if the process is hijacked. if (hijack_listener_sp && use_run_lock) - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); return state; } default: @@ -1002,13 +1002,13 @@ bool Process::GetEventsPrivate(EventSP &event_sp, } bool Process::IsRunning() const { - return StateIsRunningState(m_public_state.GetValue()); + return StateIsRunningState(GetPublicState()); } int Process::GetExitStatus() { std::lock_guard guard(m_exit_status_mutex); - if (m_public_state.GetValue() == eStateExited) + if (GetPublicState() == eStateExited) return m_exit_status; return -1; } @@ -1016,7 +1016,7 @@ int Process::GetExitStatus() { const char *Process::GetExitDescription() { std::lock_guard guard(m_exit_status_mutex); - if (m_public_state.GetValue() == eStateExited && !m_exit_string.empty()) + if (GetPublicState() == eStateExited && !m_exit_string.empty()) return m_exit_string.c_str(); return nullptr; } @@ -1029,7 +1029,7 @@ bool Process::SetExitStatus(int status, llvm::StringRef exit_string) { GetPluginName(), status, exit_string); // We were already in the exited state - if (m_private_state.GetValue() == eStateExited) { + if (GetPrivateState() == eStateExited) { LLDB_LOG( log, "(plugin = {0}) ignoring exit status because state was already set " @@ -1080,7 +1080,10 @@ bool Process::SetExitStatus(int status, llvm::StringRef exit_string) { } bool Process::IsAlive() { - switch (m_private_state.GetValue()) { + if (!m_current_private_state_thread) + return false; + + switch (GetPrivateState()) { case eStateConnected: case eStateAttaching: case eStateLaunching: @@ -1283,10 +1286,13 @@ uint32_t Process::AssignIndexIDToThread(uint64_t thread_id) { } StateType Process::GetState() { + if (!m_current_private_state_thread) + return eStateUnloaded; + if (CurrentThreadPosesAsPrivateStateThread()) - return m_private_state.GetValue(); + return GetPrivateState(); else - return m_public_state.GetValue(); + return GetPublicState(); } void Process::SetPublicState(StateType new_state, bool restarted) { @@ -1304,8 +1310,8 @@ void Process::SetPublicState(StateType new_state, bool restarted) { Log *log(GetLog(LLDBLog::State | LLDBLog::Process)); LLDB_LOGF(log, "(plugin = %s, state = %s, restarted = %i)", GetPluginName().data(), StateAsCString(new_state), restarted); - const StateType old_state = m_public_state.GetValue(); - m_public_state.SetValue(new_state); + const StateType old_state = GetPublicState(); + m_current_private_state_thread->SetPublicState(new_state); // On the transition from Run to Stopped, we unlock the writer end of the run // lock. The lock gets locked in Resume, which is the public API to tell the @@ -1315,14 +1321,14 @@ void Process::SetPublicState(StateType new_state, bool restarted) { LLDB_LOGF(log, "(plugin = %s, state = %s) -- unlocking run lock for detach", GetPluginName().data(), StateAsCString(new_state)); - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); } else { const bool old_state_is_stopped = StateIsStoppedState(old_state, false); if ((old_state_is_stopped != new_state_is_stopped)) { if (new_state_is_stopped && !restarted) { LLDB_LOGF(log, "(plugin = %s, state = %s) -- unlocking run lock", GetPluginName().data(), StateAsCString(new_state)); - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); } } } @@ -1332,7 +1338,7 @@ void Process::SetPublicState(StateType new_state, bool restarted) { Status Process::Resume() { Log *log(GetLog(LLDBLog::State | LLDBLog::Process)); LLDB_LOGF(log, "(plugin = %s) -- locking run lock", GetPluginName().data()); - if (!m_public_run_lock.SetRunning()) { + if (!SetPublicRunLockToRunning()) { LLDB_LOGF(log, "(plugin = %s) -- SetRunning failed, not resuming.", GetPluginName().data()); return Status::FromErrorString( @@ -1341,7 +1347,7 @@ Status Process::Resume() { Status error = PrivateResume(); if (!error.Success()) { // Undo running state change - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); } return error; } @@ -1349,7 +1355,7 @@ Status Process::Resume() { Status Process::ResumeSynchronous(Stream *stream) { Log *log(GetLog(LLDBLog::State | LLDBLog::Process)); LLDB_LOGF(log, "Process::ResumeSynchronous -- locking run lock"); - if (!m_public_run_lock.SetRunning()) { + if (!SetPublicRunLockToRunning()) { LLDB_LOGF(log, "Process::Resume: -- SetRunning failed, not resuming."); return Status::FromErrorString( "resume request failed: process already running"); @@ -1372,7 +1378,7 @@ Status Process::ResumeSynchronous(Stream *stream) { StateAsCString(state)); } else { // Undo running state change - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); } // Undo the hijacking of process events... @@ -1399,8 +1405,6 @@ bool Process::StateChangedIsHijackedForSynchronousResume() { return false; } -StateType Process::GetPrivateState() { return m_private_state.GetValue(); } - void Process::SetPrivateState(StateType new_state) { // Use m_destructing not m_finalizing here. If we are finalizing a process // that we haven't started tearing down, we'd like to be able to nicely @@ -1411,6 +1415,9 @@ void Process::SetPrivateState(StateType new_state) { if (m_destructing) return; + if (!m_current_private_state_thread) + return; + Log *log(GetLog(LLDBLog::State | LLDBLog::Process | LLDBLog::Unwind)); bool state_changed = false; @@ -1418,22 +1425,22 @@ void Process::SetPrivateState(StateType new_state) { StateAsCString(new_state)); std::lock_guard thread_guard(m_thread_list.GetMutex()); - std::lock_guard guard(m_private_state.GetMutex()); + std::lock_guard guard(GetPrivateStateMutex()); - const StateType old_state = m_private_state.GetValueNoLock(); + const StateType old_state = GetPrivateStateNoLock(); state_changed = old_state != new_state; const bool old_state_is_stopped = StateIsStoppedState(old_state, false); const bool new_state_is_stopped = StateIsStoppedState(new_state, false); if (old_state_is_stopped != new_state_is_stopped) { if (new_state_is_stopped) - m_private_run_lock.SetStopped(); + SetPrivateRunLockToStopped(); else - m_private_run_lock.SetRunning(); + SetPrivateRunLockToRunning(); } if (state_changed) { - m_private_state.SetValueNoLock(new_state); + SetPrivateStateNoLock(new_state); EventSP event_sp( new Event(eBroadcastBitStateChanged, new ProcessEventData(shared_from_this(), new_state))); @@ -2619,32 +2626,30 @@ bool Process::GetWatchpointReportedAfter() { return reported_after; } -ModuleSP Process::ReadModuleFromMemory(const FileSpec &file_spec, - lldb::addr_t header_addr, - size_t size_to_read) { - Log *log = GetLog(LLDBLog::Host); - if (log) { - LLDB_LOGF(log, - "Process::ReadModuleFromMemory reading %s binary from memory", - file_spec.GetPath().c_str()); - } - ModuleSP module_sp(new Module(file_spec, ArchSpec())); - if (module_sp) { - Status error; - std::unique_ptr progress_up; - // Reading an ObjectFile from a local corefile is very fast, - // only print a progress update if we're reading from a - // live session which might go over gdb remote serial protocol. - if (IsLiveDebugSession()) - progress_up = std::make_unique( - "Reading binary from memory", file_spec.GetFilename().GetString()); +llvm::Expected +Process::ReadModuleFromMemory(const FileSpec &file_spec, + lldb::addr_t header_addr, size_t size_to_read) { + LLDB_LOGF(GetLog(LLDBLog::Host), + "Process::ReadModuleFromMemory reading %s binary from memory", + file_spec.GetPath().c_str()); + ModuleSP module_sp = std::make_shared(file_spec, ArchSpec()); + if (!module_sp) + return llvm::createStringError("Failed to allocate Module"); - ObjectFile *objfile = module_sp->GetMemoryObjectFile( - shared_from_this(), header_addr, error, size_to_read); - if (objfile) - return module_sp; - } - return ModuleSP(); + Status error; + std::unique_ptr progress_up; + // Reading an ObjectFile from a local corefile is very fast, + // only print a progress update if we're reading from a + // live session which might go over gdb remote serial protocol. + if (IsLiveDebugSession()) + progress_up = std::make_unique( + "Reading binary from memory", file_spec.GetFilename().GetString()); + + if (ObjectFile *_ = module_sp->GetMemoryObjectFile( + shared_from_this(), header_addr, error, size_to_read)) + return module_sp; + + return error.takeError(); } bool Process::GetLoadAddressPermissions(lldb::addr_t load_addr, @@ -2723,12 +2728,19 @@ Status Process::Launch(ProcessLaunchInfo &launch_info) { // stopped or crashed. Directly set the state. This is done to // prevent a stop message with a bunch of spurious output on thread // status, as well as not pop a ProcessIOHandler. - SetPublicState(state_after_launch, false); - if (PrivateStateThreadIsValid()) + if (PrivateStateThreadIsRunning()) { + SetPublicState(state_after_launch, false); ResumePrivateStateThread(); - else - StartPrivateStateThread(); + } else { + StartPrivateStateThread(state_after_launch, false); + if (!m_current_private_state_thread) { + // We are not going to get any further here. The only way this could fail + // is if we can't start a host thread, so we're pretty much toast at that + // point. + return Status::FromErrorString("could not start private state thread."); + } + } // Target was stopped at entry as was intended. Need to notify the // listeners about it. @@ -2786,7 +2798,7 @@ Status Process::LaunchPrivate(ProcessLaunchInfo &launch_info, StateType &state, HijackProcessEvents(listener_sp); llvm::scope_exit on_exit([this]() { RestoreProcessEvents(); }); - if (PrivateStateThreadIsValid()) + if (PrivateStateThreadIsRunning()) PausePrivateStateThread(); error = WillLaunch(exe_module); @@ -2800,7 +2812,7 @@ Status Process::LaunchPrivate(ProcessLaunchInfo &launch_info, StateType &state, SetPublicState(eStateLaunching, restarted); m_should_detach = false; - m_public_run_lock.SetRunning(); + SetPublicRunLockToRunning(); error = DoLaunch(exe_module, launch_info); if (error.Fail()) { @@ -2878,10 +2890,18 @@ Status Process::LoadCore() { Listener::MakeListener("lldb.process.load_core_listener")); HijackProcessEvents(listener_sp); - if (PrivateStateThreadIsValid()) + if (PrivateStateThreadIsRunning()) ResumePrivateStateThread(); - else - StartPrivateStateThread(); + else { + StartPrivateStateThread(lldb::eStateStopped, + /*RunLock is stopped*/ false); + if (!m_current_private_state_thread) { + // We are not going to get any further here. The only way this + // could fail is if we can't start a host thread, so we're pretty much + // toast at that point. + return Status::FromErrorString("could not start private state thread."); + } + } DynamicLoader *dyld = GetDynamicLoader(); if (dyld) @@ -3071,10 +3091,7 @@ Status Process::Attach(ProcessAttachInfo &attach_info) { if (wait_for_launch) { error = WillAttachToProcessWithName(process_name, wait_for_launch); if (error.Success()) { - m_public_run_lock.SetRunning(); m_should_detach = true; - const bool restarted = false; - SetPublicState(eStateAttaching, restarted); // Now attach using these arguments. error = DoAttachToProcessWithName(process_name, attach_info); @@ -3089,7 +3106,14 @@ Status Process::Attach(ProcessAttachInfo &attach_info) { } else { SetNextEventAction(new Process::AttachCompletionHandler( this, attach_info.GetResumeCount())); - StartPrivateStateThread(); + StartPrivateStateThread(lldb::eStateAttaching, true); + if (!m_current_private_state_thread) { + // We are not going to get any further here. The only way + // this could fail is if we can't start a host thread, and we're + // pretty much toast at that point. + return Status::FromErrorString( + "could not start private state thread."); + } } return error; } @@ -3137,18 +3161,22 @@ Status Process::Attach(ProcessAttachInfo &attach_info) { if (attach_pid != LLDB_INVALID_PROCESS_ID) { error = WillAttachToProcessWithID(attach_pid); if (error.Success()) { - m_public_run_lock.SetRunning(); - // Now attach using these arguments. m_should_detach = true; - const bool restarted = false; - SetPublicState(eStateAttaching, restarted); error = DoAttachToProcessWithID(attach_pid, attach_info); if (error.Success()) { SetNextEventAction(new Process::AttachCompletionHandler( this, attach_info.GetResumeCount())); - StartPrivateStateThread(); + + StartPrivateStateThread(lldb::eStateAttaching, true); + if (!m_current_private_state_thread) { + // We are not going to get any further here. The only way this + // could fail is if we can't start a host thread, so we're pretty much + // toast at thatpoint. + return Status::FromErrorString( + "could not start private state thread."); + } } else { if (GetID() != LLDB_INVALID_PROCESS_ID) SetID(LLDB_INVALID_PROCESS_ID); @@ -3324,10 +3352,18 @@ Status Process::ConnectRemote(llvm::StringRef remote_url) { } } - if (PrivateStateThreadIsValid()) + if (PrivateStateThreadIsRunning()) ResumePrivateStateThread(); - else - StartPrivateStateThread(); + else { + StartPrivateStateThread(lldb::eStateStopped, + /*RunLock is stopped */ false); + if (!m_current_private_state_thread) { + // We are not going to get any further here. The only way this + // could fail is if we can't start a host thread, so we're pretty much + // toast at that point. + return Status::FromErrorString("could not start private state thread."); + } + } } return error; } @@ -3344,8 +3380,8 @@ Status Process::PrivateResume() { LLDB_LOGF(log, "Process::PrivateResume() m_stop_id = %u, public state: %s " "private state: %s", - m_mod_id.GetStopID(), StateAsCString(m_public_state.GetValue()), - StateAsCString(m_private_state.GetValue())); + m_mod_id.GetStopID(), StateAsCString(GetPublicState()), + StateAsCString(GetPrivateState())); // If signals handing status changed we might want to update our signal // filters before resuming. @@ -3407,7 +3443,7 @@ Status Process::PrivateResume() { } Status Process::Halt(bool clear_thread_plans, bool use_run_lock) { - if (!StateIsRunningState(m_public_state.GetValue())) + if (!StateIsRunningState(GetPublicState())) return Status::FromErrorString("Process is not running."); // Don't clear the m_clear_thread_plans_on_stop, only set it to true if in @@ -3422,7 +3458,7 @@ Status Process::Halt(bool clear_thread_plans, bool use_run_lock) { SendAsyncInterrupt(); - if (m_public_state.GetValue() == eStateAttaching) { + if (GetPublicState() == eStateAttaching) { // Don't hijack and eat the eStateExited as the code that was doing the // attach will be waiting for this event... RestoreProcessEvents(); @@ -3514,8 +3550,7 @@ Status Process::StopForDestroyOrDetach(lldb::EventSP &exit_event_sp) { // Check both the public & private states here. If we're hung evaluating an // expression, for instance, then the public state will be stopped, but we // still need to interrupt. - if (m_public_state.GetValue() == eStateRunning || - m_private_state.GetValue() == eStateRunning) { + if (GetPublicState() == eStateRunning || GetPrivateState() == eStateRunning) { Log *log = GetLog(LLDBLog::Process); LLDB_LOGF(log, "Process::%s() About to stop.", __FUNCTION__); @@ -3536,7 +3571,7 @@ Status Process::StopForDestroyOrDetach(lldb::EventSP &exit_event_sp) { // doesn't need to do anything else, since they don't have a process // anymore... - if (state == eStateExited || m_private_state.GetValue() == eStateExited) { + if (state == eStateExited || GetPrivateState() == eStateExited) { LLDB_LOGF(log, "Process::%s() Process exited while waiting to stop.", __FUNCTION__); return error; @@ -3549,7 +3584,7 @@ Status Process::StopForDestroyOrDetach(lldb::EventSP &exit_event_sp) { // If we really couldn't stop the process then we should just error out // here, but if the lower levels just bobbled sending the event and we // really are stopped, then continue on. - StateType private_state = m_private_state.GetValue(); + StateType private_state = GetPrivateState(); if (private_state != eStateStopped) { return Status::FromErrorStringWithFormat( "Attempt to stop the target in order to detach timed out. " @@ -3609,7 +3644,7 @@ Status Process::Detach(bool keep_stopped) { // case we might strand the write lock. Unlock it here so when we do to tear // down the process we don't get an error destroying the lock. - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); return error; } @@ -3646,7 +3681,7 @@ Status Process::DestroyImpl(bool force_kill) { error = StopForDestroyOrDetach(exit_event_sp); } - if (m_public_state.GetValue() == eStateStopped) { + if (GetPublicState() == eStateStopped) { // Ditch all thread plans, and remove all our breakpoints: in case we // have to restart the target to kill it, we don't want it hitting a // breakpoint... Only do this if we've stopped, however, since if we @@ -3686,7 +3721,7 @@ Status Process::DestroyImpl(bool force_kill) { // may not end up propagating the last events through the event system, in // which case we might strand the write lock. Unlock it here so when we do // to tear down the process we don't get an error destroying the lock. - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); } m_destroy_in_process = false; @@ -3876,10 +3911,34 @@ bool Process::ShouldBroadcastEvent(Event *event_ptr) { return return_value; } -bool Process::StartPrivateStateThread(bool is_secondary_thread) { +bool Process::PrivateStateThread::StartupThread() { + llvm::Expected private_state_thread = + ThreadLauncher::LaunchThread( + m_thread_name, [this] { return m_process.RunPrivateStateThread(); }, + 8 * 1024 * 1024); + if (!private_state_thread) { + LLDB_LOG_ERROR(GetLog(LLDBLog::Host), private_state_thread.takeError(), + "failed to launch host thread: {0}"); + return false; + } + + assert(private_state_thread->IsJoinable()); + m_private_state_thread = *private_state_thread; + m_is_running = true; + m_process.ResumePrivateStateThread(); + return true; +} + +bool Process::PrivateStateThread::IsOnThread(const HostThread &thread) const { + return m_private_state_thread.EqualsThread(thread); +} + +bool Process::StartPrivateStateThread(lldb::StateType state, + bool run_lock_is_running, + bool is_secondary_thread) { Log *log = GetLog(LLDBLog::Events); - bool already_running = PrivateStateThreadIsValid(); + bool already_running = PrivateStateThreadIsRunning(); LLDB_LOGF(log, "Process::%s()%s ", __FUNCTION__, already_running ? " already running" : " starting private state thread"); @@ -3908,23 +3967,23 @@ bool Process::StartPrivateStateThread(bool is_secondary_thread) { "", GetID()); } - llvm::Expected private_state_thread = - ThreadLauncher::LaunchThread( - thread_name, - [this, is_secondary_thread] { - return RunPrivateStateThread(is_secondary_thread); - }, - 8 * 1024 * 1024); - if (!private_state_thread) { - LLDB_LOG_ERROR(GetLog(LLDBLog::Host), private_state_thread.takeError(), - "failed to launch host thread: {0}"); - return false; - } + if (is_secondary_thread) { + PrivateStateThread *new_private_state_thread = + new PrivateStateThread(*this, GetPublicState(), GetPrivateState(), + is_secondary_thread, thread_name); + // StartupThread expects the m_current_private_state_thread to be in place + // already, so do that first: + m_current_private_state_thread = new_private_state_thread; + } else + m_current_private_state_thread->SetThreadName(thread_name); - assert(private_state_thread->IsJoinable()); - m_private_state_thread = *private_state_thread; - ResumePrivateStateThread(); - return true; + SetPublicState(state, /*restarted=*/false); + if (run_lock_is_running) + SetPublicRunLockToRunning(); + else + SetPublicRunLockToStopped(); + + return m_current_private_state_thread->StartupThread(); } void Process::PausePrivateStateThread() { @@ -3936,7 +3995,10 @@ void Process::ResumePrivateStateThread() { } void Process::StopPrivateStateThread() { - if (m_private_state_thread.IsJoinable()) + if (!m_current_private_state_thread) + return; + + if (m_current_private_state_thread->IsJoinable()) ControlPrivateStateThread(eBroadcastInternalStateControlStop); else { Log *log = GetLog(LLDBLog::Process); @@ -3956,7 +4018,7 @@ void Process::ControlPrivateStateThread(uint32_t signal) { LLDB_LOGF(log, "Process::%s (signal = %d)", __FUNCTION__, signal); // Signal the private state thread - if (m_private_state_thread.IsJoinable()) { + if (m_current_private_state_thread->IsJoinable()) { // Broadcast the event. // It is important to do this outside of the if below, because it's // possible that the thread state is invalid but that the thread is waiting @@ -3969,7 +4031,7 @@ void Process::ControlPrivateStateThread(uint32_t signal) { // Wait for the event receipt or for the private state thread to exit bool receipt_received = false; - if (PrivateStateThreadIsValid()) { + if (PrivateStateThreadIsRunning()) { while (!receipt_received) { // Check for a receipt for n seconds and then check if the private // state thread is still around. @@ -3978,17 +4040,15 @@ void Process::ControlPrivateStateThread(uint32_t signal) { if (!receipt_received) { // Check if the private state thread is still around. If it isn't // then we are done waiting - if (!PrivateStateThreadIsValid()) + if (!PrivateStateThreadIsRunning()) break; // Private state thread exited or is exiting, we are done } } } - if (signal == eBroadcastInternalStateControlStop) { - thread_result_t result = {}; - m_private_state_thread.Join(&result); - m_private_state_thread.Reset(); - } + if (signal == eBroadcastInternalStateControlStop) + m_current_private_state_thread->JoinAndReset(); + } else { LLDB_LOGF( log, @@ -4001,7 +4061,7 @@ void Process::SendAsyncInterrupt(Thread *thread) { m_interrupt_tid = thread->GetProtocolID(); else m_interrupt_tid = LLDB_INVALID_THREAD_ID; - if (PrivateStateThreadIsValid()) + if (PrivateStateThreadIsRunning()) m_private_state_broadcaster.BroadcastEvent(Process::eBroadcastBitInterrupt, nullptr); else @@ -4133,7 +4193,7 @@ Status Process::HaltPrivate() { return error; } -thread_result_t Process::RunPrivateStateThread(bool is_secondary_thread) { +thread_result_t Process::RunPrivateStateThread() { bool control_only = true; Log *log = GetLog(LLDBLog::Process); @@ -4168,7 +4228,7 @@ thread_result_t Process::RunPrivateStateThread(bool is_secondary_thread) { continue; } else if (event_sp->GetType() == eBroadcastBitInterrupt) { - if (m_public_state.GetValue() == eStateAttaching) { + if (GetPublicState() == eStateAttaching) { LLDB_LOGF(log, "Process::%s (arg = %p, pid = %" PRIu64 ") woke up with an interrupt while attaching - " @@ -4262,11 +4322,7 @@ thread_result_t Process::RunPrivateStateThread(bool is_secondary_thread) { LLDB_LOGF(log, "Process::%s (arg = %p, pid = %" PRIu64 ") thread exiting...", __FUNCTION__, static_cast(this), GetID()); - // If we are a secondary thread, then the primary thread we are working for - // will have already acquired the public_run_lock, and isn't done with what - // it was doing yet, so don't try to change it on the way out. - if (!is_secondary_thread) - m_public_run_lock.SetStopped(); + SetPublicRunLockToStopped(); return {}; } @@ -5130,7 +5186,7 @@ Process::RunThreadPlan(ExecutionContext &exe_ctx, // and reverting the mark it once we are done running the expression. UtilityFunctionScope util_scope(options.IsForUtilityExpr() ? this : nullptr); - if (m_private_state.GetValue() != eStateStopped) { + if (GetPrivateState() != eStateStopped) { diagnostic_manager.PutString( lldb::eSeverityError, "RunThreadPlan called while the private state was not stopped."); @@ -5188,12 +5244,12 @@ Process::RunThreadPlan(ExecutionContext &exe_ctx, selected_tid = LLDB_INVALID_THREAD_ID; } - HostThread backup_private_state_thread; + PrivateStateThread *backup_private_state_thread = nullptr; lldb::StateType old_state = eStateInvalid; lldb::ThreadPlanSP stopper_base_plan_sp; Log *log(GetLog(LLDBLog::Step | LLDBLog::Process)); - if (m_private_state_thread.EqualsThread(Host::GetCurrentThread())) { + if (m_current_private_state_thread->IsOnThread(Host::GetCurrentThread())) { // Yikes, we are running on the private state thread! So we can't wait for // public events on this thread, since we are the thread that is generating // public events. The simplest thing to do is to spin up a temporary thread @@ -5202,7 +5258,7 @@ Process::RunThreadPlan(ExecutionContext &exe_ctx, LLDB_LOGF(log, "Running thread plan on private state thread, spinning up " "another state thread to handle the events."); - backup_private_state_thread = m_private_state_thread; + backup_private_state_thread = m_current_private_state_thread; // One other bit of business: we want to run just this thread plan and // anything it pushes, and then stop, returning control here. But in the @@ -5215,11 +5271,23 @@ Process::RunThreadPlan(ExecutionContext &exe_ctx, thread->QueueThreadPlan(stopper_base_plan_sp, false); // Have to make sure our public state is stopped, since otherwise the // reporting logic below doesn't work correctly. - old_state = m_public_state.GetValue(); - m_public_state.SetValueNoLock(eStateStopped); + old_state = GetPublicState(); + m_current_private_state_thread->SetPublicStateNoLock(eStateStopped); // Now spin up the private state thread: - StartPrivateStateThread(true); + StartPrivateStateThread(lldb::eStateStopped, /* RunLock is stopped*/ false, + /*secondary_thread=*/true); + if (!m_current_private_state_thread) { + // If we can't spin up a thread here we can't run this expression. But + // presumably the old private state thread is still good, so just put it + // back and return an error. + diagnostic_manager.Printf( + lldb::eSeverityError, + "could not spin up a thread to handle events for an expression" + " run on the private state thread."); + m_current_private_state_thread = backup_private_state_thread; + return eExpressionSetupError; + } } thread->QueueThreadPlan( @@ -5659,15 +5727,16 @@ Process::RunThreadPlan(ExecutionContext &exe_ctx, // If we had to start up a temporary private state thread to run this // thread plan, shut it down now. - if (backup_private_state_thread.IsJoinable()) { + if (backup_private_state_thread && + backup_private_state_thread->IsJoinable()) { StopPrivateStateThread(); Status error; - m_private_state_thread = backup_private_state_thread; + m_current_private_state_thread = backup_private_state_thread; if (stopper_base_plan_sp) { thread->DiscardThreadPlansUpToPlan(stopper_base_plan_sp); } if (old_state != eStateInvalid) - m_public_state.SetValueNoLock(old_state); + m_current_private_state_thread->SetPublicStateNoLock(old_state); } // If our thread went away on us, we need to get out of here without @@ -5970,22 +6039,23 @@ void Process::ClearPreResumeAction(PreResumeActionCallback callback, void *baton } ProcessRunLock &Process::GetRunLock() { - if (Process::CurrentThreadIsPrivateStateThread()) - return m_private_run_lock; - return m_public_run_lock; + return m_current_private_state_thread->GetRunLock(); } bool Process::CurrentThreadIsPrivateStateThread() { - return m_private_state_thread.EqualsThread(Host::GetCurrentThread()); + if (!m_current_private_state_thread) + return true; + return m_current_private_state_thread->IsOnThread(Host::GetCurrentThread()); } bool Process::CurrentThreadPosesAsPrivateStateThread() { // If we haven't started up the private state thread yet, then whatever thread // is fetching this event should be temporarily the private state thread. - if (!m_private_state_thread.HasThread()) + if (!m_current_private_state_thread || + !m_current_private_state_thread->IsRunning()) return true; - return m_private_state_thread.EqualsThread(Host::GetCurrentThread()); + return m_current_private_state_thread->IsOnThread(Host::GetCurrentThread()); } void Process::Flush() { diff --git a/lldb/source/Target/ProcessTrace.cpp b/lldb/source/Target/ProcessTrace.cpp index 02272b1651da5..8b7d194aa0767 100644 --- a/lldb/source/Target/ProcessTrace.cpp +++ b/lldb/source/Target/ProcessTrace.cpp @@ -16,6 +16,8 @@ #include "lldb/Target/ABI.h" #include "lldb/Target/SectionLoadList.h" #include "lldb/Target/Target.h" +#include "lldb/Utility/LLDBLog.h" +#include "lldb/Utility/Log.h" using namespace lldb; using namespace lldb_private; @@ -63,8 +65,12 @@ void ProcessTrace::DidAttach(ArchSpec &process_arch) { HijackProcessEvents(listener_sp); SetCanJIT(false); - StartPrivateStateThread(); - SetPrivateState(eStateStopped); + StartPrivateStateThread(lldb::eStateStopped, false); + if (!m_current_private_state_thread) { + LLDB_LOG(GetLog(LLDBLog::Process), "ProcessTrace: failed to start private " + "state thread."); + return; + } EventSP event_sp; WaitForProcessToStop(std::nullopt, &event_sp, true, listener_sp); diff --git a/lldb/source/Target/StackFrameList.cpp b/lldb/source/Target/StackFrameList.cpp index 1ad269e8783cc..4f4b06f30460b 100644 --- a/lldb/source/Target/StackFrameList.cpp +++ b/lldb/source/Target/StackFrameList.cpp @@ -38,12 +38,13 @@ using namespace lldb_private; // StackFrameList constructor StackFrameList::StackFrameList(Thread &thread, const lldb::StackFrameListSP &prev_frames_sp, - bool show_inline_frames) + bool show_inline_frames, + lldb::frame_list_id_t provider_id) : m_thread(thread), m_prev_frames_sp(prev_frames_sp), m_frames(), m_selected_frame_idx(), m_concrete_frames_fetched(0), m_current_inlined_depth(UINT32_MAX), m_current_inlined_pc(LLDB_INVALID_ADDRESS), - m_show_inlined_frames(show_inline_frames) { + m_show_inlined_frames(show_inline_frames), m_identifier(provider_id) { if (prev_frames_sp) { m_current_inlined_depth = prev_frames_sp->m_current_inlined_depth; m_current_inlined_pc = prev_frames_sp->m_current_inlined_pc; @@ -59,8 +60,8 @@ StackFrameList::~StackFrameList() { SyntheticStackFrameList::SyntheticStackFrameList( Thread &thread, lldb::StackFrameListSP input_frames, const lldb::StackFrameListSP &prev_frames_sp, bool show_inline_frames, - lldb::SyntheticFrameProviderSP provider_sp) - : StackFrameList(thread, prev_frames_sp, show_inline_frames), + lldb::SyntheticFrameProviderSP provider_sp, uint64_t provider_id) + : StackFrameList(thread, prev_frames_sp, show_inline_frames, provider_id), m_input_frames(std::move(input_frames)), m_provider(std::move(provider_sp)) {} @@ -70,12 +71,25 @@ bool SyntheticStackFrameList::FetchFramesUpTo( size_t num_synthetic_frames = 0; // Use the provider to generate frames lazily. if (m_provider) { + // Get starting index under lock. + uint32_t start_idx = 0; + { + std::shared_lock guard(m_list_mutex); + start_idx = m_frames.size(); + } + // Keep fetching until we reach end_idx or the provider returns an error. - for (uint32_t idx = m_frames.size(); idx <= end_idx; idx++) { + for (uint32_t idx = start_idx; idx <= end_idx; idx++) { if (allow_interrupt && m_thread.GetProcess()->GetTarget().GetDebugger().InterruptRequested()) return true; + + // Call Python WITHOUT holding lock - prevents deadlock. auto frame_or_err = m_provider->GetFrameAtIndex(idx); + + // Acquire lock to modify m_frames. + std::unique_lock guard(m_list_mutex); + if (!frame_or_err) { // Provider returned error - we've reached the end. LLDB_LOG_ERROR(GetLog(LLDBLog::Thread), frame_or_err.takeError(), @@ -89,7 +103,7 @@ bool SyntheticStackFrameList::FetchFramesUpTo( GetThread().GetProcess().get()); // Set the frame list weak pointer so ExecutionContextRef can resolve // the frame without calling Thread::GetStackFrameList(). - frame_sp->m_frame_list_wp = shared_from_this(); + frame_sp->m_frame_list_id = GetIdentifier(); m_frames.push_back(frame_sp); } @@ -375,7 +389,7 @@ void StackFrameList::SynthesizeTailCallFrames(StackFrame &next_frame) { m_thread.shared_from_this(), frame_idx, concrete_frame_idx, cfa, cfa_is_valid, pc, StackFrame::Kind::Regular, artificial, behaves_like_zeroth_frame, &sc); - synth_frame->m_frame_list_wp = shared_from_this(); + synth_frame->m_frame_list_id = GetIdentifier(); m_frames.push_back(synth_frame); LLDB_LOG(log, "Pushed frame {0} at {1:x}", callee->GetDisplayName(), pc); } @@ -410,6 +424,10 @@ bool StackFrameList::GetFramesUpTo(uint32_t end_idx, return false; } + // Release lock before FetchFramesUpTo which may call Python. + // FetchFramesUpTo will acquire locks as needed. + guard.unlock(); + // We're adding concrete and inlined frames now: was_interrupted = FetchFramesUpTo(end_idx, allow_interrupt); @@ -491,7 +509,7 @@ bool StackFrameList::FetchFramesUpTo(uint32_t end_idx, unwind_frame_sp = std::make_shared( m_thread.shared_from_this(), m_frames.size(), idx, reg_ctx_sp, cfa, pc, behaves_like_zeroth_frame, nullptr); - unwind_frame_sp->m_frame_list_wp = shared_from_this(); + unwind_frame_sp->m_frame_list_id = GetIdentifier(); m_frames.push_back(unwind_frame_sp); } } else { @@ -526,7 +544,7 @@ bool StackFrameList::FetchFramesUpTo(uint32_t end_idx, // although its concrete index will stay the same. SynthesizeTailCallFrames(*unwind_frame_sp.get()); - unwind_frame_sp->m_frame_list_wp = shared_from_this(); + unwind_frame_sp->m_frame_list_id = GetIdentifier(); m_frames.push_back(unwind_frame_sp); } @@ -551,7 +569,7 @@ bool StackFrameList::FetchFramesUpTo(uint32_t end_idx, unwind_frame_sp->GetRegisterContextSP(), cfa, next_frame_address, behaves_like_zeroth_frame, &next_frame_sc)); - frame_sp->m_frame_list_wp = shared_from_this(); + frame_sp->m_frame_list_id = GetIdentifier(); m_frames.push_back(frame_sp); unwind_sc = next_frame_sc; curr_frame_address = next_frame_address; @@ -608,7 +626,7 @@ bool StackFrameList::FetchFramesUpTo(uint32_t end_idx, prev_frame->UpdatePreviousFrameFromCurrentFrame(*curr_frame); // Now copy the fixed up previous frame into the current frames so the // pointer doesn't change. - prev_frame_sp->m_frame_list_wp = shared_from_this(); + prev_frame_sp->m_frame_list_id = GetIdentifier(); m_frames[curr_frame_idx] = prev_frame_sp; #if defined(DEBUG_STACK_FRAMES) diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp index f3e058c6cbc9b..787e66bfaf7a8 100644 --- a/lldb/source/Target/Target.cpp +++ b/lldb/source/Target/Target.cpp @@ -70,6 +70,7 @@ #include "llvm/ADT/ScopeExit.h" #include "llvm/ADT/SetVector.h" +#include "llvm/Support/ErrorExtras.h" #include "llvm/Support/ThreadPool.h" #include @@ -3725,47 +3726,45 @@ llvm::Expected Target::AddScriptedFrameProviderDescriptor( if (!descriptor.IsValid()) return llvm::createStringError("invalid frame provider descriptor"); + uint32_t descriptor_id = descriptor.GetID(); + llvm::StringRef name = descriptor.GetName(); if (name.empty()) return llvm::createStringError( "frame provider descriptor has no class name"); - std::lock_guard guard( - m_frame_provider_descriptors_mutex); - - uint32_t descriptor_id = descriptor.GetID(); - m_frame_provider_descriptors[descriptor_id] = descriptor; + { + std::unique_lock guard( + m_frame_provider_descriptors_mutex); + m_frame_provider_descriptors[descriptor_id] = descriptor; + } - // Clear frame providers on existing threads so they reload with new config. - if (ProcessSP process_sp = GetProcessSP()) - for (ThreadSP thread_sp : process_sp->Threads()) - thread_sp->ClearScriptedFrameProvider(); + InvalidateThreadFrameProviders(); return descriptor_id; } bool Target::RemoveScriptedFrameProviderDescriptor(uint32_t id) { - std::lock_guard guard( - m_frame_provider_descriptors_mutex); - bool removed = m_frame_provider_descriptors.erase(id); + bool removed = false; + { + std::lock_guard guard( + m_frame_provider_descriptors_mutex); + removed = m_frame_provider_descriptors.erase(id); + } if (removed) - if (ProcessSP process_sp = GetProcessSP()) - for (ThreadSP thread_sp : process_sp->Threads()) - thread_sp->ClearScriptedFrameProvider(); - + InvalidateThreadFrameProviders(); return removed; } void Target::ClearScriptedFrameProviderDescriptors() { - std::lock_guard guard( - m_frame_provider_descriptors_mutex); - - m_frame_provider_descriptors.clear(); + { + std::lock_guard guard( + m_frame_provider_descriptors_mutex); + m_frame_provider_descriptors.clear(); + } - if (ProcessSP process_sp = GetProcessSP()) - for (ThreadSP thread_sp : process_sp->Threads()) - thread_sp->ClearScriptedFrameProvider(); + InvalidateThreadFrameProviders(); } const llvm::DenseMap & @@ -3775,6 +3774,21 @@ Target::GetScriptedFrameProviderDescriptors() const { return m_frame_provider_descriptors; } +void Target::InvalidateThreadFrameProviders() { + ProcessSP process_sp = GetProcessSP(); + if (!process_sp) + return; + for (ThreadSP thread_sp : process_sp->Threads()) { + // Clear frame providers on existing threads so they reload with new config. + thread_sp->ClearScriptedFrameProvider(); + // Notify threads that the stack traces might have changed. + if (thread_sp->EventTypeHasListeners(Thread::eBroadcastBitStackChanged)) { + auto data_sp = std::make_shared(thread_sp); + thread_sp->BroadcastEvent(Thread::eBroadcastBitStackChanged, data_sp); + } + } +} + void Target::FinalizeFileActions(ProcessLaunchInfo &info) { Log *log = GetLog(LLDBLog::Process); @@ -5357,3 +5371,74 @@ void Target::NotifyBreakpointChanged( if (EventTypeHasListeners(Target::eBroadcastBitBreakpointChanged)) BroadcastEvent(Target::eBroadcastBitBreakpointChanged, breakpoint_data_sp); } + +// FIXME: the language plugin should expression options dynamically and +// we should validate here (by asking the language plugin) that the options +// being set/retrieved are actually valid options. + +llvm::Error +EvaluateExpressionOptions::SetBooleanLanguageOption(llvm::StringRef option_name, + bool value) { + if (option_name.empty()) + return llvm::createStringError("Can't set an option with an empty name."); + + if (StructuredData::ObjectSP existing_sp = + GetLanguageOptions().GetValueForKey(option_name); + existing_sp && existing_sp->GetType() != eStructuredDataTypeBoolean) + return llvm::createStringErrorV("Trying to override existing option '{0}' " + "of type '{1}' with a boolean value.", + option_name, existing_sp->GetType()); + + GetLanguageOptions().AddBooleanItem(option_name, value); + + return llvm::Error::success(); +} + +llvm::Expected EvaluateExpressionOptions::GetBooleanLanguageOption( + llvm::StringRef option_name) const { + const StructuredData::Dictionary &opts = GetLanguageOptions(); + + if (!opts.HasKey(option_name)) + return llvm::createStringErrorV("Option '{0}' does not exist.", + option_name); + + bool result; + if (!opts.GetValueForKeyAsBoolean(option_name, result)) + return llvm::createStringErrorV("Failed to get option '{0}' as boolean.", + option_name); + + return result; +} + +const StructuredData::Dictionary & +EvaluateExpressionOptions::GetLanguageOptions() const { + assert(m_language_options_sp); + + return *m_language_options_sp; +} + +StructuredData::Dictionary &EvaluateExpressionOptions::GetLanguageOptions() { + assert(m_language_options_sp); + + return *m_language_options_sp; +} + +// FIXME: this option is C++ plugin specific and should be registered by it, +// instead of hard-coding it here. +constexpr llvm::StringLiteral s_cpp_ignore_context_qualifiers_option = + "c++-ignore-context-qualifiers"; + +EvaluateExpressionOptions::EvaluateExpressionOptions() + : m_language_options_sp(std::make_shared()) { + SetCppIgnoreContextQualifiers(false); +} + +void EvaluateExpressionOptions::SetCppIgnoreContextQualifiers(bool value) { + llvm::cantFail( + SetBooleanLanguageOption(s_cpp_ignore_context_qualifiers_option, value)); +} + +bool EvaluateExpressionOptions::GetCppIgnoreContextQualifiers() const { + return llvm::cantFail( + GetBooleanLanguageOption(s_cpp_ignore_context_qualifiers_option)); +} diff --git a/lldb/source/Target/Thread.cpp b/lldb/source/Target/Thread.cpp index 70d8650662348..2c95c2d209b45 100644 --- a/lldb/source/Target/Thread.cpp +++ b/lldb/source/Target/Thread.cpp @@ -29,7 +29,6 @@ #include "lldb/Target/ScriptedThreadPlan.h" #include "lldb/Target/StackFrameRecognizer.h" #include "lldb/Target/StopInfo.h" -#include "lldb/Target/SyntheticFrameProvider.h" #include "lldb/Target/SystemRuntime.h" #include "lldb/Target/Target.h" #include "lldb/Target/ThreadPlan.h" @@ -57,6 +56,8 @@ #include "lldb/ValueObject/ValueObjectConstResult.h" #include "lldb/lldb-enumerations.h" +#include "llvm/Support/MathExtras.h" + #include #include @@ -262,7 +263,10 @@ void Thread::DestroyThread() { std::lock_guard guard(m_frame_mutex); m_curr_frames_sp.reset(); m_prev_frames_sp.reset(); + m_unwinder_frames_sp.reset(); m_frame_providers.clear(); + m_provider_chain_ids.clear(); + m_frame_lists_by_id.clear(); m_prev_framezero_pc.reset(); } @@ -1465,16 +1469,15 @@ StackFrameListSP Thread::GetStackFrameList() { const auto &descriptors = target.GetScriptedFrameProviderDescriptors(); // Collect all descriptors that apply to this thread. - std::vector - applicable_descriptors; + std::vector thread_descriptors; for (const auto &entry : descriptors) { const ScriptedFrameProviderDescriptor &descriptor = entry.second; if (descriptor.IsValid() && descriptor.AppliesToThread(*this)) - applicable_descriptors.push_back(&descriptor); + thread_descriptors.push_back(&descriptor); } // Sort by priority (lower number = higher priority). - llvm::sort(applicable_descriptors, + llvm::sort(thread_descriptors, [](const ScriptedFrameProviderDescriptor *a, const ScriptedFrameProviderDescriptor *b) { // nullopt (no priority) sorts last (UINT32_MAX). @@ -1484,7 +1487,7 @@ StackFrameListSP Thread::GetStackFrameList() { }); // Load ALL matching providers in priority order. - for (const auto *descriptor : applicable_descriptors) { + for (const auto *descriptor : thread_descriptors) { if (llvm::Error error = LoadScriptedFrameProvider(*descriptor)) { LLDB_LOG_ERROR(GetLog(LLDBLog::Thread), std::move(error), "Failed to load scripted frame provider: {0}"); @@ -1495,58 +1498,123 @@ StackFrameListSP Thread::GetStackFrameList() { } // Create the frame list based on whether we have providers. - if (!m_frame_providers.empty()) { + if (!m_provider_chain_ids.empty()) { // We have providers - use the last one in the chain. // The last provider has already been chained with all previous providers. - StackFrameListSP input_frames = m_frame_providers.back()->GetInputFrames(); - m_curr_frames_sp = std::make_shared( - *this, input_frames, m_prev_frames_sp, true, m_frame_providers.back()); + auto [last_desc, last_id] = m_provider_chain_ids.back(); + auto it = m_frame_providers.find(last_id); + if (it != m_frame_providers.end()) { + SyntheticFrameProviderSP last_provider = it->second; + StackFrameListSP input_frames = last_provider->GetInputFrames(); + m_curr_frames_sp = std::make_shared( + *this, input_frames, m_prev_frames_sp, true, last_provider, last_id); + } else { + LLDB_LOG(GetLog(LLDBLog::Thread), + "Missing frame provider (id = {0}) in Thread #{1:x}}", last_id, + GetID()); + } + } + + if (!m_curr_frames_sp) { + // No provider - use normal unwinder frames with stable ID = 0. + m_unwinder_frames_sp = std::make_shared( + *this, m_prev_frames_sp, true, /*provider_id=*/0); + m_curr_frames_sp = m_unwinder_frames_sp; } else { - // No provider - use normal unwinder frames. - m_curr_frames_sp = - std::make_shared(*this, m_prev_frames_sp, true); + // Register this frame list by its identifier for later lookup. + m_frame_lists_by_id.insert( + {m_curr_frames_sp->GetIdentifier(), m_curr_frames_sp}); } return m_curr_frames_sp; } +lldb::StackFrameListSP +Thread::GetFrameListByIdentifier(lldb::frame_list_id_t id) { + std::lock_guard guard(m_frame_mutex); + + // ID 0 is reserved for the unwinder frame list. Always return the unwinder + // frame list for ID 0. + if (id == 0) { + return m_unwinder_frames_sp; + } + + auto it = m_frame_lists_by_id.find(id); + if (it != m_frame_lists_by_id.end()) { + return it->second.lock(); + } + return nullptr; +} + llvm::Error Thread::LoadScriptedFrameProvider( const ScriptedFrameProviderDescriptor &descriptor) { std::lock_guard guard(m_frame_mutex); - // Create input frames for this provider: - // - If no providers exist yet, use real unwinder frames. - // - If providers exist, wrap the previous provider in a - // SyntheticStackFrameList. - // This creates the chain: each provider's OUTPUT becomes the next - // provider's INPUT. - StackFrameListSP new_provider_input_frames; + StackFrameListSP input_frames; if (m_frame_providers.empty()) { - // First provider gets real unwinder frames. - new_provider_input_frames = - std::make_shared(*this, m_prev_frames_sp, true); + // First provider gets real unwinder frames with stable ID = 0. + m_unwinder_frames_sp = + std::make_shared(*this, m_prev_frames_sp, true, + /*provider_id=*/0); + input_frames = m_unwinder_frames_sp; } else { - // Subsequent providers get the previous provider's OUTPUT. - // We create a SyntheticStackFrameList that wraps the previous provider. - SyntheticFrameProviderSP prev_provider = m_frame_providers.back(); - StackFrameListSP prev_provider_frames = prev_provider->GetInputFrames(); - new_provider_input_frames = std::make_shared( - *this, prev_provider_frames, m_prev_frames_sp, true, prev_provider); - } - - auto provider_or_err = SyntheticFrameProvider::CreateInstance( - new_provider_input_frames, descriptor); + // Subsequent providers wrap the previous provider. + auto [last_desc, last_id] = m_provider_chain_ids.back(); + auto it = m_frame_providers.find(last_id); + if (it == m_frame_providers.end()) + return llvm::createStringError("Previous frame provider not found"); + SyntheticFrameProviderSP last_provider = it->second; + StackFrameListSP last_provider_frames = last_provider->GetInputFrames(); + input_frames = std::make_shared( + *this, last_provider_frames, m_prev_frames_sp, true, last_provider, + last_id); + } + + auto provider_or_err = + SyntheticFrameProvider::CreateInstance(input_frames, descriptor); if (!provider_or_err) return provider_or_err.takeError(); - // Append to the chain. - m_frame_providers.push_back(*provider_or_err); + if (m_next_provider_id == std::numeric_limits::max()) + m_next_provider_id = 1; + else + m_next_provider_id++; + + lldb::frame_list_id_t provider_id = m_next_provider_id; + m_frame_providers.insert({provider_id, *provider_or_err}); + + // Add to the provider chain. + m_provider_chain_ids.push_back({descriptor, provider_id}); + return llvm::Error::success(); } +llvm::Expected +Thread::GetScriptedFrameProviderDescriptorForID( + lldb::frame_list_id_t id) const { + if (id == LLDB_UNWINDER_FRAME_LIST_ID) + return ScriptedFrameProviderDescriptor(); + + auto it = llvm::find_if( + m_provider_chain_ids, + [id](const std::pair &provider_id_pair) { + return provider_id_pair.second == id; + }); + + if (it == m_provider_chain_ids.end()) + return llvm::createStringError( + "Couldn't find ScriptedFrameProviderDescriptor for id = %u.", id); + + return it->first; +} + void Thread::ClearScriptedFrameProvider() { std::lock_guard guard(m_frame_mutex); m_frame_providers.clear(); + m_provider_chain_ids.clear(); + m_next_provider_id = 1; // Reset counter. + m_unwinder_frames_sp.reset(); m_curr_frames_sp.reset(); m_prev_frames_sp.reset(); } @@ -1570,8 +1638,13 @@ void Thread::ClearStackFrames() { if (m_curr_frames_sp && m_curr_frames_sp->WereAllFramesFetched()) m_prev_frames_sp.swap(m_curr_frames_sp); m_curr_frames_sp.reset(); + m_unwinder_frames_sp.reset(); + // Clear the provider instances, but keep the chain configuration + // (m_provider_chain_ids and m_next_provider_id) so provider IDs + // remain stable across ClearStackFrames() calls. m_frame_providers.clear(); + m_frame_lists_by_id.clear(); m_extended_info.reset(); m_extended_info_fetched = false; } diff --git a/lldb/source/Utility/VirtualDataExtractor.cpp b/lldb/source/Utility/VirtualDataExtractor.cpp index 83520072a95a8..fe7ed963d0bdd 100644 --- a/lldb/source/Utility/VirtualDataExtractor.cpp +++ b/lldb/source/Utility/VirtualDataExtractor.cpp @@ -86,6 +86,108 @@ const void *VirtualDataExtractor::GetData(offset_t *offset_ptr, return result; } +offset_t VirtualDataExtractor::SetData(const void *bytes, lldb::offset_t length, + lldb::ByteOrder byte_order) { + // Invoked from the base class ctor. + if (!m_data_sp || m_start == nullptr) + return DataExtractor::SetData(bytes, length, byte_order); + + // A no-op SetData that is setting the same data buffer again. + if (!m_data_sp && m_start == bytes && length == GetVirtualByteSize()) + return GetVirtualByteSize(); + + assert("SetData(1) called on VirtualDataExtractor that already had data" && + false); + + DataExtractor::SetData(bytes, length, byte_order); + ResetLookupTableToMatchPhysical(); + + return GetVirtualByteSize(); +} + +offset_t VirtualDataExtractor::SetData(const DataExtractor &data, + lldb::offset_t offset, + lldb::offset_t length) { + // Invoked from the base class ctor + if (!m_data_sp || m_start == nullptr) + return DataExtractor::SetData(data, offset, length); + + // A no-op SetData that is setting the same data buffer again + if (m_data_sp && data.GetSharedDataBuffer().get() == m_data_sp.get() && + offset == 0 && length == GetVirtualByteSize()) + return GetVirtualByteSize(); + assert("SetData(2) called on VirtualDataExtractor that already had data" && + false); + + DataExtractor::SetData(data, offset, length); + ResetLookupTableToMatchPhysical(); + + return GetVirtualByteSize(); +} + +offset_t VirtualDataExtractor::SetData(const lldb::DataBufferSP &data_sp, + lldb::offset_t offset, + lldb::offset_t length) { + // Invoked from the base class ctor + if (!m_data_sp || m_start == nullptr) + return DataExtractor::SetData(data_sp, offset, length); + + // A no-op SetData that is setting the same data buffer again + if (m_data_sp && data_sp.get() == m_data_sp.get() && offset == 0 && + length == GetVirtualByteSize()) + return GetVirtualByteSize(); + + assert("SetData(3) called on VirtualDataExtractor that already had data" && + false); + + DataExtractor::SetData(data_sp, offset, length); + ResetLookupTableToMatchPhysical(); + + return GetVirtualByteSize(); +} + +void VirtualDataExtractor::ResetLookupTableToMatchPhysical() { + // calling SetData on a VirtualDataExtractor that already has a + // data buffer means the LookupTable needs to be either replaced, or + // if we assume the buffer is a subset of the original, we need to + // update all the entries to have correct new offsets into the buffer + // and remove entries that are outside the new range. + // For now, zero out the LookupTable and behave as if this is a simple + // DataExtractor. + m_lookup_table.Clear(); + m_lookup_table.Append( + VirtualDataExtractor::LookupTable::Entry{0, GetPhysicalByteSize(), 0}); +} + +uint64_t VirtualDataExtractor::GetVirtualByteSize() const { + offset_t lowest = -1ULL; + offset_t highest = 0; + for (const auto ent : m_lookup_table) { + lowest = std::min(lowest, ent.base); + highest = std::max(highest, ent.base + ent.size); + } + return highest - lowest; +} + +uint64_t VirtualDataExtractor::GetPhysicalByteSize() const { + return m_end - m_start; +} + +offset_t VirtualDataExtractor::VirtualBytesLeft(offset_t virtual_offset) const { + const offset_t size = GetVirtualByteSize(); + if (size > virtual_offset) + return size - virtual_offset; + return 0; +} + +offset_t +VirtualDataExtractor::PhysicalBytesLeft(offset_t physical_offset) const { + const offset_t size = m_end - m_start; + if (size > physical_offset) + return size - physical_offset; + return 0; +} + const uint8_t *VirtualDataExtractor::PeekData(offset_t offset, offset_t length) const { // Override to treat offset as virtual address. diff --git a/lldb/source/ValueObject/DILEval.cpp b/lldb/source/ValueObject/DILEval.cpp index 5ffebc107bfb3..48aa4af1d9fd2 100644 --- a/lldb/source/ValueObject/DILEval.cpp +++ b/lldb/source/ValueObject/DILEval.cpp @@ -814,7 +814,7 @@ Interpreter::VerifyArithmeticCast(CompilerType source_type, CompilerType target_type, int location) { if (source_type.IsPointerType() || source_type.IsNullPtrType()) { // Cast from pointer to float/double is not allowed. - if (target_type.IsFloat()) { + if (target_type.GetTypeInfo() & lldb::eTypeIsFloat) { std::string errMsg = llvm::formatv("Cast from {0} to {1} is not allowed", source_type.TypeDescription(), target_type.TypeDescription()); @@ -951,7 +951,9 @@ llvm::Expected Interpreter::Visit(const CastNode &node) { switch (cast_kind) { case CastKind::eEnumeration: { - if (op_type.IsFloat() || op_type.IsInteger() || op_type.IsEnumerationType()) + // FIXME: is this correct for float vector types? + if (op_type.GetTypeInfo() & lldb::eTypeIsFloat || op_type.IsInteger() || + op_type.IsEnumerationType()) return operand->CastToEnumType(target_type); break; } diff --git a/lldb/source/ValueObject/ValueObject.cpp b/lldb/source/ValueObject/ValueObject.cpp index aed2b074a2b16..af67c1c93182c 100644 --- a/lldb/source/ValueObject/ValueObject.cpp +++ b/lldb/source/ValueObject/ValueObject.cpp @@ -48,7 +48,7 @@ #include "lldb/ValueObject/ValueObjectMemory.h" #include "lldb/ValueObject/ValueObjectSynthetic.h" #include "lldb/ValueObject/ValueObjectVTable.h" -#include "lldb/lldb-private-types.h" +#include "lldb/lldb-enumerations.h" #include "llvm/Support/Compiler.h" @@ -76,6 +76,14 @@ using namespace lldb_private; static user_id_t g_value_obj_uid = 0; +// FIXME: this will return true for vector types whose elements +// are floats. Audit all usages of this function and call +// IsFloatingPointType() instead if vectors of floats aren't intended +// to be supported. +static bool HasFloatingRepresentation(CompilerType ct) { + return ct.GetTypeInfo() & eTypeIsFloat; +} + // ValueObject constructor ValueObject::ValueObject(ValueObject &parent) : m_parent(&parent), m_update_point(parent.GetUpdatePoint()), @@ -1165,7 +1173,7 @@ llvm::Expected ValueObject::GetValueAsAPSInt() { } llvm::Expected ValueObject::GetValueAsAPFloat() { - if (!GetCompilerType().IsFloat()) + if (!HasFloatingRepresentation(GetCompilerType())) return llvm::make_error( "type cannot be converted to APFloat", llvm::inconvertibleErrorCode()); @@ -1188,7 +1196,7 @@ llvm::Expected ValueObject::GetValueAsBool() { if (value_or_err) return value_or_err->getBoolValue(); } - if (val_type.IsFloat()) { + if (HasFloatingRepresentation(val_type)) { auto value_or_err = GetValueAsAPFloat(); if (value_or_err) return value_or_err->isNonZero(); @@ -1204,7 +1212,7 @@ void ValueObject::SetValueFromInteger(const llvm::APInt &value, Status &error) { // Verify the current object is an integer object CompilerType val_type = GetCompilerType(); if (!val_type.IsInteger() && !val_type.IsUnscopedEnumerationType() && - !val_type.IsFloat() && !val_type.IsPointerType() && + !HasFloatingRepresentation(val_type) && !val_type.IsPointerType() && !val_type.IsScalarType()) { error = Status::FromErrorString("current value object is not an integer objet"); @@ -1244,7 +1252,7 @@ void ValueObject::SetValueFromInteger(lldb::ValueObjectSP new_val_sp, // Verify the current object is an integer object CompilerType val_type = GetCompilerType(); if (!val_type.IsInteger() && !val_type.IsUnscopedEnumerationType() && - !val_type.IsFloat() && !val_type.IsPointerType() && + !HasFloatingRepresentation(val_type) && !val_type.IsPointerType() && !val_type.IsScalarType()) { error = Status::FromErrorString("current value object is not an integer objet"); @@ -1261,7 +1269,7 @@ void ValueObject::SetValueFromInteger(lldb::ValueObjectSP new_val_sp, // Verify the proposed new value is the right type. CompilerType new_val_type = new_val_sp->GetCompilerType(); - if (!new_val_type.IsInteger() && !new_val_type.IsFloat() && + if (!new_val_type.IsInteger() && !HasFloatingRepresentation(new_val_type) && !new_val_type.IsPointerType()) { error = Status::FromErrorString( "illegal argument: new value should be of the same size"); @@ -1274,7 +1282,7 @@ void ValueObject::SetValueFromInteger(lldb::ValueObjectSP new_val_sp, SetValueFromInteger(*value_or_err, error); else error = Status::FromErrorString("error getting APSInt from new_val_sp"); - } else if (new_val_type.IsFloat()) { + } else if (HasFloatingRepresentation(new_val_type)) { auto value_or_err = new_val_sp->GetValueAsAPFloat(); if (value_or_err) SetValueFromInteger(value_or_err->bitcastToAPInt(), error); @@ -3142,7 +3150,7 @@ lldb::ValueObjectSP ValueObject::CastToBasicType(CompilerType type) { bool is_enum = GetCompilerType().IsEnumerationType(); bool is_pointer = GetCompilerType().IsPointerType() || GetCompilerType().IsNullPtrType(); - bool is_float = GetCompilerType().IsFloat(); + bool is_float = HasFloatingRepresentation(GetCompilerType()); bool is_integer = GetCompilerType().IsInteger(); ExecutionContext exe_ctx(GetExecutionContextRef()); @@ -3234,7 +3242,7 @@ lldb::ValueObjectSP ValueObject::CastToBasicType(CompilerType type) { } } - if (type.IsFloat()) { + if (HasFloatingRepresentation(type)) { if (!is_scalar) { auto int_value_or_err = GetValueAsAPSInt(); if (int_value_or_err) { @@ -3296,7 +3304,7 @@ lldb::ValueObjectSP ValueObject::CastToBasicType(CompilerType type) { lldb::ValueObjectSP ValueObject::CastToEnumType(CompilerType type) { bool is_enum = GetCompilerType().IsEnumerationType(); bool is_integer = GetCompilerType().IsInteger(); - bool is_float = GetCompilerType().IsFloat(); + bool is_float = HasFloatingRepresentation(GetCompilerType()); ExecutionContext exe_ctx(GetExecutionContextRef()); if (!is_enum && !is_integer && !is_float) diff --git a/lldb/test/API/commands/expression/expr_inside_lambda/TestExprInsideLambdas.py b/lldb/test/API/commands/expression/expr_inside_lambda/TestExprInsideLambdas.py index e35cfa6a289a7..0a7683b310f43 100644 --- a/lldb/test/API/commands/expression/expr_inside_lambda/TestExprInsideLambdas.py +++ b/lldb/test/API/commands/expression/expr_inside_lambda/TestExprInsideLambdas.py @@ -127,8 +127,8 @@ def test_expr_inside_lambda(self): # Inside non_capturing_method lldbutil.continue_to_breakpoint(process, bkpt) - self.expect_expr("local", result_type="int", result_value="5") - self.expect_expr("local2", result_type="int", result_value="10") + self.expect_expr("local", result_type="const int", result_value="5") + self.expect_expr("local2", result_type="const int", result_value="10") self.expect_expr("local2 * local", result_type="int", result_value="50") self.expectExprError( diff --git a/lldb/test/API/commands/expression/ir-interpreter/TestIRInterpreter.py b/lldb/test/API/commands/expression/ir-interpreter/TestIRInterpreter.py index 23188ef898d56..800c591def7c8 100644 --- a/lldb/test/API/commands/expression/ir-interpreter/TestIRInterpreter.py +++ b/lldb/test/API/commands/expression/ir-interpreter/TestIRInterpreter.py @@ -172,3 +172,112 @@ def test_type_conversions(self): self.assertEqual(short_val.GetValueAsSigned(), -1) long_val = target.EvaluateExpression("(long) " + short_val.GetName()) self.assertEqual(long_val.GetValueAsSigned(), -1) + + def test_fpconv(self): + self.build_and_run() + + interp_options = lldb.SBExpressionOptions() + interp_options.SetLanguage(lldb.eLanguageTypeC_plus_plus) + interp_options.SetAllowJIT(False) + + jit_options = lldb.SBExpressionOptions() + jit_options.SetLanguage(lldb.eLanguageTypeC_plus_plus) + jit_options.SetAllowJIT(True) + + set_up_expressions = [ + "int32_t $i = 3", + "int32_t $n = -3", + "uint32_t $u = 5", + "int64_t $l = -7", + "float $f = 9.0625", + "double $d = 13.75", + "float $nf = -11.25", + ] + + expressions = [ + "$i + $f", # sitofp i32 to float + "$d - $n", # sitofp i32 to double + "$u + $f", # uitofp i32 to float + "$u + $d", # uitofp i32 to double + "(int32_t)$d", # fptosi double to i32 + "(int32_t)$f", # fptosi float to i32 + "(int64_t)$d", # fptosi double to i64 + "(int16_t)$f", # fptosi float to i16 + "(int64_t)$nf", # fptosi float to i64 + "(uint16_t)$f", # fptoui float to i16 + "(uint32_t)$d", # fptoui double to i32 + "(uint64_t)$d", # fptoui double to i64 + "(float)$d", # fptrunc double to float + "(double)$f", # fpext float to double + "(double)$nf", # fpext float to double + ] + + for expression in set_up_expressions: + self.frame().EvaluateExpression(expression, interp_options) + + func_call = "(int)getpid()" + if lldbplatformutil.getPlatform() == "windows": + func_call = "(int)GetCurrentProcessId()" + + for expression in expressions: + interp_expression = expression + # Calling a function forces the expression to be executed with JIT. + jit_expression = func_call + "; " + expression + + interp_result = self.frame().EvaluateExpression( + interp_expression, interp_options + ) + jit_result = self.frame().EvaluateExpression(jit_expression, jit_options) + + self.assertEqual( + interp_result.GetValue(), + jit_result.GetValue(), + "Values match for " + expression, + ) + self.assertEqual( + interp_result.GetTypeName(), + jit_result.GetTypeName(), + "Types match for " + expression, + ) + + def test_fpconv_ub(self): + target = self.dbg.GetDummyTarget() + + set_up_expressions = [ + "float $f = 3e9", + "double $d = 1e20", + "float $nf = -1.5", + ] + + expressions = [ + ( + "(int32_t)$f", + "Conversion error: (float) 3.0E+9 cannot be converted to i32", + ), + ( + "(uint32_t)$nf", + "Conversion error: (float) -1.5 cannot be converted to unsigned i32", + ), + ( + "(int64_t)$d", + "Conversion error: (float) 1.0E+20 cannot be converted to i64", + ), + ( + "(uint64_t)$d", + "Conversion error: (float) 1.0E+20 cannot be converted to unsigned i64", + ), + ] + + for expression in set_up_expressions: + target.EvaluateExpression(expression) + + # The IR Interpreter returns an error if a value cannot be converted. + for expression in expressions: + result = target.EvaluateExpression(expression[0]) + self.assertIn(expression[1], str(result.GetError())) + + # The conversion should succeed if the destination type can represent the result. + self.expect_expr( + "(uint32_t)$f", result_type="uint32_t", result_value="3000000000" + ) + self.expect_expr("(int32_t)$nf", result_type="int32_t", result_value="-1") diff --git a/lldb/test/API/commands/expression/options/TestExprOptions.py b/lldb/test/API/commands/expression/options/TestExprOptions.py index 01899f3b97cf4..02f844b34cc2b 100644 --- a/lldb/test/API/commands/expression/options/TestExprOptions.py +++ b/lldb/test/API/commands/expression/options/TestExprOptions.py @@ -7,7 +7,6 @@ Test expression command options. """ - import lldb import lldbsuite.test.lldbutil as lldbutil from lldbsuite.test.decorators import * @@ -85,3 +84,38 @@ def test_expr_options_lang(self): val = frame.EvaluateExpression("id == 0", options) self.assertTrue(val.IsValid()) self.assertFalse(val.GetError().Success()) + + def test_expr_options_language_options(self): + """Test SetBooleanLanguageOption/GetBooleanLanguageOption SBAPIs""" + + error = lldb.SBError() + options = lldb.SBExpressionOptions() + + self.assertFalse(options.GetBooleanLanguageOption("foo", error)) + self.assertTrue(error.Fail()) + self.assertFalse(options.GetBooleanLanguageOption("bar", error)) + self.assertTrue(error.Fail()) + + self.assertTrue(options.SetBooleanLanguageOption("foo", True).Success()) + self.assertTrue(options.SetBooleanLanguageOption("bar", True).Success()) + self.assertTrue(options.GetBooleanLanguageOption("foo", error)) + self.assertTrue(error.Success()) + self.assertTrue(options.GetBooleanLanguageOption("bar", error)) + self.assertTrue(error.Success()) + + self.assertTrue(options.SetBooleanLanguageOption("foo", False).Success()) + self.assertTrue(options.SetBooleanLanguageOption("bar", False).Success()) + self.assertFalse(options.GetBooleanLanguageOption("foo", error)) + self.assertTrue(error.Success()) + self.assertFalse(options.GetBooleanLanguageOption("bar", error)) + self.assertTrue(error.Success()) + + self.assertFalse(options.GetBooleanLanguageOption("", error)) + self.assertTrue(error.Fail()) + self.assertTrue(options.SetBooleanLanguageOption("", True).Fail()) + self.assertFalse(options.GetBooleanLanguageOption("", error)) + self.assertTrue(error.Fail()) + + self.assertTrue(options.SetBooleanLanguageOption(None, True).Fail()) + self.assertFalse(options.GetBooleanLanguageOption(None, error)) + self.assertTrue(error.Fail()) diff --git a/lldb/test/API/driver/batch_mode/TestBatchMode.py b/lldb/test/API/driver/batch_mode/TestBatchMode.py index f58128278c249..aca4b7e5e6423 100644 --- a/lldb/test/API/driver/batch_mode/TestBatchMode.py +++ b/lldb/test/API/driver/batch_mode/TestBatchMode.py @@ -4,6 +4,7 @@ import lldb +import subprocess from lldbsuite.test.decorators import * from lldbsuite.test.lldbtest import * from lldbsuite.test import lldbutil @@ -13,6 +14,24 @@ class DriverBatchModeTest(PExpectTest): source = "main.c" + @skipIfRemote + def test_batch_mode_no_commands_quits(self): + """--batch should immediately quit if there are no commands given.""" + try: + proc = subprocess.run( + [lldbtest_config.lldbExec, "--batch"], + timeout=60, + stdout=subprocess.PIPE, + text=True, + ) + except subprocess.TimeoutExpired: + self.fail("lldb did not quit automatically.") + + # Exit succesfully. + self.assertEqual(proc.returncode, 0) + # No prompt printed. + self.assertEqual(proc.stdout, "") + @skipIf(macos_version=["<", "14.0"], asan=True) @skipIf(oslist=["linux"], archs=["arm$", "aarch64"]) # Randomly fails on buildbot @expectedFlakeyFreeBSD("llvm.org/pr25172 fails rarely on the buildbot") diff --git a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/TestWasHit.py b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/TestWasHit.py index 2e176239facf0..ac820b8d65be0 100644 --- a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/TestWasHit.py +++ b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/TestWasHit.py @@ -65,6 +65,15 @@ def do_test(self): ) self.assertEqual(thread.stop_reason_data[1], 1, "First location hit is 1") + # Check that we did increment our global: + values = target.FindGlobalVariables("g_change_me", 2, lldb.eSymbolTypeCode) + self.assertEqual(values.GetSize(), 1, "Got the change me global") + change_me = values.GetValueAtIndex(0) + change_me_value = 1 + self.assertEqual( + change_me.signed, change_me_value, "g_change_me had the right value" + ) + for loc in [3, 4]: process.Continue() self.assertEqual( @@ -76,6 +85,10 @@ def do_test(self): self.assertEqual( thread.stop_reason_data[1], loc, f"Hit the right location: {loc}" ) + change_me_value += 1 + self.assertEqual( + change_me.signed, change_me_value, "g_change_me was updated correctly" + ) # At this point we should have hit three of the four locations, and not location 1.2. # Check that that is true, and that the descriptions for the location are the ones diff --git a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/bkpt_resolver.py b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/bkpt_resolver.py index acc8513e3e3e0..0ddbf832c37c5 100644 --- a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/bkpt_resolver.py +++ b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/bkpt_resolver.py @@ -43,6 +43,15 @@ def was_hit(self, frame, bp_loc): if tmp_loc == self.loc_to_miss: return None + # Make sure we can call a function here as well: + options = lldb.SBExpressionOptions() + options.SetStopOthers(True) + options.SetTryAllThreads(False) + + result = frame.EvaluateExpression("change_him()", options) + if not result.error.success: + return lldb.LLDB_INVALID_BREAK_ID + return self.facade_locs[tmp_loc] def get_location_description(self, bp_loc, desc_level): diff --git a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/main.c b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/main.c index b8f977e493513..7fe5480f8623b 100644 --- a/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/main.c +++ b/lldb/test/API/functionalities/breakpoint/scripted_bkpt/was_hit/main.c @@ -1,5 +1,9 @@ #include +int g_change_me = 0; + +int change_him() { return ++g_change_me; } + int stop_symbol() { static int s_cnt = 0; printf("I am in the stop symbol: %d\n", s_cnt++); @@ -10,5 +14,6 @@ int main() { for (int i = 0; i < 100; i++) { stop_symbol(); } + change_him(); return 0; } diff --git a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ordering/TestDataFormatterStdOrdering.py b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ordering/TestDataFormatterStdOrdering.py index fc6142ac5d738..b5895792ee4cf 100644 --- a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ordering/TestDataFormatterStdOrdering.py +++ b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ordering/TestDataFormatterStdOrdering.py @@ -47,7 +47,7 @@ def do_test(self): self.assertEqual(frame.FindVariable("so_greater").summary, "greater") @add_test_categories(["libc++"]) - def test_libstdcxx(self): + def test_libcxx(self): self.build(dictionary={"USE_LIBCPP": 1}) self.do_test() diff --git a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vbool/TestDataFormatterStdVBool.py b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vbool/TestDataFormatterStdVBool.py index f74092ca3a0b8..03ebcba471776 100644 --- a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vbool/TestDataFormatterStdVBool.py +++ b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vbool/TestDataFormatterStdVBool.py @@ -106,7 +106,7 @@ def test_libstdcxx_debug(self): self.do_test() @add_test_categories(["msvcstl"]) - def test_libstdcxx(self): + def test_msvcstl(self): # No flags, because the "msvcstl" category checks that the MSVC STL is used by default. self.build() self.do_test() diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestWasm.py b/lldb/test/API/functionalities/gdb_remote_client/TestWasm.py index 73c81efb79347..f025a1f94de54 100644 --- a/lldb/test/API/functionalities/gdb_remote_client/TestWasm.py +++ b/lldb/test/API/functionalities/gdb_remote_client/TestWasm.py @@ -99,9 +99,6 @@ def qHostInfo(self): def QEnableErrorStrings(self): return "" - def qfThreadInfo(self): - return "m1," - def qRegisterInfo(self, index): if index == 0: return "name:pc;alt-name:pc;bitsize:64;offset:0;encoding:uint;format:hex;set:General Purpose Registers;gcc:16;dwarf:16;generic:pc;" diff --git a/lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py b/lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py index 7dd74013b90f8..8c2d8f0d5ad52 100644 --- a/lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py +++ b/lldb/test/API/functionalities/scripted_frame_provider/TestScriptedFrameProvider.py @@ -735,8 +735,11 @@ def test_get_values(self): """Test a frame that provides values.""" self.build() # Set the breakpoint after the variable_in_main variable exists and can be queried. - target, process, thread, bkpt = lldbutil.run_to_line_breakpoint( - self, lldb.SBFileSpec(self.source), 35, only_one_thread=False + target, process, thread, bkpt = lldbutil.run_to_source_breakpoint( + self, + "Breakpoint for variable tests", + lldb.SBFileSpec(self.source), + only_one_thread=False, ) # Get original frame count. @@ -771,7 +774,8 @@ def test_get_values(self): self.assertIsNotNone(frame0) # Get every variable visible at this point variables = frame0.GetVariables(True, True, True, False) - self.assertTrue(variables.IsValid() and variables.GetSize() == 1) + self.assertTrue(variables.IsValid()) + self.assertEqual(variables.GetSize(), 1) # Check that we can get values from paths. `_handler_one` is a special # value we provide through only our expression handler in the frame @@ -783,3 +787,403 @@ def test_get_values(self): self.assertEqual(var.unsigned, variables.GetValueAtIndex(0).unsigned) varp1 = frame0.GetValueForVariablePath("variable_in_main + 1") self.assertEqual(varp1.unsigned, 124) + + def test_frame_validity_after_step(self): + """Test that SBFrame references from ScriptedFrameProvider remain valid after stepping. + + This test verifies that ExecutionContextRef properly handles frame list identifiers + when the underlying stack changes. After stepping, old frame references should become + invalid gracefully without crashing. + """ + self.build() + target, process, thread, bkpt = lldbutil.run_to_source_breakpoint( + self, "Break here", lldb.SBFileSpec(self.source), only_one_thread=False + ) + + # Import the test frame provider. + script_path = os.path.join(self.getSourceDir(), "test_frame_providers.py") + self.runCmd("command script import " + script_path) + + # Register a provider that prepends synthetic frames. + error = lldb.SBError() + provider_id = target.RegisterScriptedFrameProvider( + "test_frame_providers.PrependFrameProvider", + lldb.SBStructuredData(), + error, + ) + self.assertTrue(error.Success(), f"Failed to register provider: {error}") + + # Get frame references before stepping. + frame0_before = thread.GetFrameAtIndex(0) + frame1_before = thread.GetFrameAtIndex(1) + frame2_before = thread.GetFrameAtIndex(2) + + self.assertIsNotNone(frame0_before) + self.assertIsNotNone(frame1_before) + self.assertIsNotNone(frame2_before) + + # Verify frames are valid and have expected PCs. + self.assertTrue(frame0_before.IsValid(), "Frame 0 should be valid before step") + self.assertTrue(frame1_before.IsValid(), "Frame 1 should be valid before step") + self.assertTrue(frame2_before.IsValid(), "Frame 2 should be valid before step") + + pc0_before = frame0_before.GetPC() + pc1_before = frame1_before.GetPC() + pc2_before = frame2_before.GetPC() + + self.assertEqual(pc0_before, 0x9000, "Frame 0 should have synthetic PC 0x9000") + self.assertEqual(pc1_before, 0xA000, "Frame 1 should have synthetic PC 0xA000") + + # Step the thread, which will invalidate the old frame list. + thread.StepInstruction(False) + + # After stepping, the frame list has changed. Old frame references should + # detect this and become invalid, but shouldn't crash. + # The key here is that GetPC() and other operations should handle the + # "frame provider no longer available" case gracefully. + + # Try to access the old frames - they should either: + # 1. Return invalid/default values gracefully, or + # 2. Still work if the frame provider is re-applied. + + # Get new frames after stepping. + frame0_after = thread.GetFrameAtIndex(0) + self.assertIsNotNone(frame0_after) + self.assertTrue( + frame0_after.IsValid(), "New frame 0 should be valid after step" + ) + + # The old frame references might or might not be valid depending on whether + # the frame provider is still active. What's important is that accessing + # them doesn't crash and handles the situation gracefully. + # We'll just verify we can call methods on them without crashing. + try: + _ = frame0_before.GetPC() + _ = frame0_before.IsValid() + _ = frame0_before.GetFunctionName() + except Exception as e: + self.fail(f"Accessing old frame reference should not crash: {e}") + + def test_provider_lifecycle_with_frame_validity(self): + """Test provider registration/removal at breakpoints and SBFrame validity across lifecycle. + + This test verifies: + 1. Registering a provider while stopped at a breakpoint. + 2. SBFrame references from synthetic frames persist across continues. + 3. SBFrame references can access variables in real frames while provider is active. + 4. Removing a provider while stopped at a breakpoint. + 5. SBFrame references from removed provider don't crash when accessed. + """ + self.build() + target = self.dbg.CreateTarget(self.getBuildArtifact("a.out")) + self.assertTrue(target.IsValid(), "Target should be valid") + + # Import the test frame provider. + script_path = os.path.join(self.getSourceDir(), "test_frame_providers.py") + self.runCmd("command script import " + script_path) + + # Set up breakpoints at the return statements in foo, bar, and baz. + # This ensures local variables are initialized. + bp_foo = target.BreakpointCreateBySourceRegex( + "Break in foo", lldb.SBFileSpec(self.source) + ) + bp_bar = target.BreakpointCreateBySourceRegex( + "Break in bar", lldb.SBFileSpec(self.source) + ) + bp_baz = target.BreakpointCreateBySourceRegex( + "Break in baz", lldb.SBFileSpec(self.source) + ) + + self.assertTrue(bp_foo.IsValid(), "Breakpoint at foo should be valid") + self.assertTrue(bp_bar.IsValid(), "Breakpoint at bar should be valid") + self.assertTrue(bp_baz.IsValid(), "Breakpoint at baz should be valid") + + # Launch the process. + process = target.LaunchSimple(None, None, self.get_process_working_directory()) + self.assertTrue(process.IsValid(), "Process should be valid") + + # We should hit the foo breakpoint first. + self.assertEqual( + process.GetState(), lldb.eStateStopped, "Process should be stopped at foo" + ) + thread = process.GetSelectedThread() + self.assertIsNotNone(thread, "Should have a selected thread") + + # Register the provider at foo breakpoint. + error = lldb.SBError() + provider_id = target.RegisterScriptedFrameProvider( + "test_frame_providers.PrependFrameProvider", + lldb.SBStructuredData(), + error, + ) + self.assertTrue(error.Success(), f"Failed to register provider: {error}") + self.assertNotEqual(provider_id, 0, "Provider ID should be non-zero") + + # Get individual frames BEFORE getting the full backtrace. + # This tests accessing frames before forcing evaluation of all frames. + frame0 = thread.GetFrameAtIndex(0) + frame1 = thread.GetFrameAtIndex(1) + frame2 = thread.GetFrameAtIndex(2) + + self.assertIsNotNone(frame0, "Frame 0 should exist") + self.assertIsNotNone(frame1, "Frame 1 should exist") + self.assertIsNotNone(frame2, "Frame 2 should exist") + + # First two frames should be synthetic with expected PCs. + pc0 = frame0.GetPC() + pc1 = frame1.GetPC() + + self.assertEqual(pc0, 0x9000, "Frame 0 should have synthetic PC 0x9000") + self.assertEqual(pc1, 0xA000, "Frame 1 should have synthetic PC 0xA000") + + # Frame 2 should be the real foo frame. + self.assertIn("foo", frame2.GetFunctionName(), "Frame 2 should be in foo") + + # Save references to the synthetic frames. + saved_frames = [frame0, frame1, frame2] + + # Test accessing saved frames at foo BEFORE getting full backtrace. + try: + _ = saved_frames[0].GetPC() + _ = saved_frames[1].GetPC() + _ = saved_frames[2].GetFunctionName() + except Exception as e: + self.fail( + f"Accessing saved frames at foo before full backtrace should not crash: {e}" + ) + + # Now verify the provider is active by checking frame count. + # PrependFrameProvider adds 2 synthetic frames. + # This forces a full backtrace evaluation. + original_frame_count = thread.GetNumFrames() + self.assertGreater( + original_frame_count, + 2, + "Should have at least synthetic frames + real frames", + ) + + # Test accessing saved frames at foo AFTER getting full backtrace. + try: + _ = saved_frames[0].GetPC() + _ = saved_frames[1].GetPC() + _ = saved_frames[2].GetFunctionName() + except Exception as e: + self.fail( + f"Accessing saved frames at foo after full backtrace should not crash: {e}" + ) + + # Verify we can access variables in frame2 (real frame). + foo_local = frame2.FindVariable("foo_local") + self.assertTrue(foo_local.IsValid(), "Should find foo_local variable") + self.assertEqual( + foo_local.GetValueAsUnsigned(), 20, "foo_local should be 20 (10 * 2)" + ) + + # Continue to bar breakpoint. + threads = lldbutil.continue_to_breakpoint(process, bp_bar) + self.assertIsNotNone(threads, "Should have stopped at bar breakpoint") + self.assertEqual(len(threads), 1, "Should have one thread stopped at bar") + thread = threads[0] + + # Verify the saved frames are still accessible without crashing at bar. + # Do this BEFORE getting the full backtrace. + # Note: They might not be "valid" in the traditional sense since we've moved + # to a different execution context, but they shouldn't crash. + try: + _ = saved_frames[0].GetPC() + _ = saved_frames[1].GetPC() + except Exception as e: + self.fail( + f"Accessing saved frames at bar before full backtrace should not crash: {e}" + ) + + # Verify the provider is still active by getting frame count. + # This forces full backtrace evaluation. + current_frame_count = thread.GetNumFrames() + self.assertGreater( + current_frame_count, 2, "Should still have synthetic frames at bar" + ) + + # Access the saved frames again AFTER getting the full backtrace. + # This ensures that forcing a full backtrace evaluation doesn't break + # the saved frame references. + try: + _ = saved_frames[0].GetPC() + _ = saved_frames[1].GetPC() + except Exception as e: + self.fail( + f"Accessing saved frames at bar after full backtrace should not crash: {e}" + ) + + # Get current frames at bar. + bar_frame0 = thread.GetFrameAtIndex(0) + bar_frame1 = thread.GetFrameAtIndex(1) + bar_frame2 = thread.GetFrameAtIndex(2) + + # Verify current frames have synthetic PCs. + self.assertEqual( + bar_frame0.GetPC(), 0x9000, "Frame 0 at bar should have synthetic PC" + ) + self.assertEqual( + bar_frame1.GetPC(), 0xA000, "Frame 1 at bar should have synthetic PC" + ) + self.assertIn("bar", bar_frame2.GetFunctionName(), "Frame 2 should be in bar") + + # Verify we can access variables in the bar frame. + bar_local = bar_frame2.FindVariable("bar_local") + self.assertTrue(bar_local.IsValid(), "Should find bar_local variable") + self.assertEqual( + bar_local.GetValueAsUnsigned(), 25, "bar_local should be 25 (5 * 5)" + ) + + # Continue to baz breakpoint. + threads = lldbutil.continue_to_breakpoint(process, bp_baz) + self.assertIsNotNone(threads, "Should have stopped at baz breakpoint") + self.assertEqual(len(threads), 1, "Should have one thread stopped at baz") + thread = threads[0] + + # Verify the saved frames are still accessible without crashing at baz. + # Do this BEFORE getting the full backtrace. + try: + _ = saved_frames[0].GetPC() + _ = saved_frames[1].GetPC() + _ = saved_frames[2].GetFunctionName() + except Exception as e: + self.fail( + f"Accessing saved frames at baz before full backtrace should not crash: {e}" + ) + + # Get the frame count to force full backtrace evaluation at baz. + baz_frame_count = thread.GetNumFrames() + self.assertGreater( + baz_frame_count, 2, "Should still have synthetic frames at baz" + ) + + # Verify the saved frames are still accessible AFTER getting full backtrace at baz. + try: + _ = saved_frames[0].GetPC() + _ = saved_frames[1].GetPC() + _ = saved_frames[2].GetFunctionName() + except Exception as e: + self.fail( + f"Accessing saved frames at baz after full backtrace should not crash: {e}" + ) + + # Now manually remove the provider. + result = target.RemoveScriptedFrameProvider(provider_id) + self.assertSuccess( + result, f"Should successfully remove provider with ID {provider_id}" + ) + # Verify frames no longer have synthetic frames. + final_frame_count = thread.GetNumFrames() + + # Without the provider, we should have fewer frames (no synthetic ones). + self.assertLess( + final_frame_count, + original_frame_count, + "Frame count should decrease after provider removal", + ) + + # First frame should now be the real baz frame (no synthetic frames). + baz_frame0 = thread.GetFrameAtIndex(0) + self.assertIn( + "baz", baz_frame0.GetFunctionName(), "Frame 0 should now be real baz frame" + ) + + # The synthetic PC values should no longer appear. + for i in range(final_frame_count): + frame = thread.GetFrameAtIndex(i) + pc = frame.GetPC() + self.assertNotEqual( + pc, 0x9000, f"Frame {i} should not have synthetic PC 0x9000" + ) + self.assertNotEqual( + pc, 0xA000, f"Frame {i} should not have synthetic PC 0xA000" + ) + + # Verify the originally saved frames are now truly invalid/stale. + # They should still not crash when accessed. + try: + _ = saved_frames[0].GetPC() + _ = saved_frames[0].IsValid() + _ = saved_frames[1].GetPC() + _ = saved_frames[1].IsValid() + except Exception as e: + self.fail(f"Accessing invalidated frames should not crash: {e}") + + def test_event_broadcasting(self): + """Test that adding/removing frame providers broadcasts eBroadcastBitStackChanged.""" + self.build() + + listener = lldb.SBListener("stack_changed_listener") + listener.StartListeningForEventClass( + self.dbg, + lldb.SBThread.GetBroadcasterClassName(), + lldb.SBThread.eBroadcastBitStackChanged, + ) + + target, process, thread, bkpt = lldbutil.run_to_source_breakpoint( + self, "Break here", lldb.SBFileSpec(self.source), only_one_thread=False + ) + + expected_thread_ids = { + process.GetThreadAtIndex(i).GetIndexID() + for i in range(process.GetNumThreads()) + } + + def collect_stack_changed_thread_ids(count): + event = lldb.SBEvent() + thread_ids = set() + for _ in range(count): + if not listener.WaitForEvent(5, event): + break + self.assertEqual( + event.GetType(), + lldb.SBThread.eBroadcastBitStackChanged, + "Event should be stack changed", + ) + thread_ids.add(lldb.SBThread.GetThreadFromEvent(event).GetIndexID()) + return thread_ids + + # Import the test frame provider. + script_path = os.path.join(self.getSourceDir(), "test_frame_providers.py") + self.runCmd("command script import " + script_path) + + # 1. Test registration. + error = lldb.SBError() + provider_id = target.RegisterScriptedFrameProvider( + "test_frame_providers.ReplaceFrameProvider", + lldb.SBStructuredData(), + error, + ) + self.assertSuccess(error, f"Failed to register provider: {error}") + self.assertEqual( + collect_stack_changed_thread_ids(len(expected_thread_ids)), + expected_thread_ids, + "All threads should broadcast eBroadcastBitStackChanged on registration", + ) + + # 2. Test removal. + result = target.RemoveScriptedFrameProvider(provider_id) + self.assertSuccess(result, f"Failed to remove provider: {result}") + self.assertEqual( + collect_stack_changed_thread_ids(len(expected_thread_ids)), + expected_thread_ids, + "All threads should broadcast eBroadcastBitStackChanged on removal", + ) + + # 3. Test clear. + target.RegisterScriptedFrameProvider( + "test_frame_providers.ReplaceFrameProvider", + lldb.SBStructuredData(), + error, + ) + # Consume registration + collect_stack_changed_thread_ids(len(expected_thread_ids)) + + self.runCmd("target frame-provider clear") + self.assertEqual( + collect_stack_changed_thread_ids(len(expected_thread_ids)), + expected_thread_ids, + "All threads should broadcast eBroadcastBitStackChanged on clear", + ) \ No newline at end of file diff --git a/lldb/test/API/functionalities/scripted_frame_provider/main.cpp b/lldb/test/API/functionalities/scripted_frame_provider/main.cpp index e1d346c29052b..e17226a459033 100644 --- a/lldb/test/API/functionalities/scripted_frame_provider/main.cpp +++ b/lldb/test/API/functionalities/scripted_frame_provider/main.cpp @@ -10,6 +10,24 @@ std::condition_variable cv; int ready_count = 0; constexpr int NUM_THREADS = 2; +int foo(int x) { + int foo_local = x * 2; + int foo_result = foo_local + 1; + return foo_result; // Break in foo. +} + +int bar(int x) { + int bar_local = x * x; + int bar_result = bar_local - 3; + return bar_result; // Break in bar. +} + +int baz(int x) { + int baz_local = x + 7; + int baz_result = baz_local / 2; + return baz_result; // Break in baz. +} + void thread_func(int thread_num) { std::cout << "Thread " << thread_num << " started\n"; @@ -31,7 +49,11 @@ int main(int argc, char **argv) { // Used as an existing C++ variable we can anchor on. int variable_in_main = 123; - (void)variable_in_main; + (void)variable_in_main; // Breakpoint for variable tests. + + // Call foo for first breakpoint. + int result_foo = foo(10); + (void)result_foo; for (int i = 0; i < NUM_THREADS; i++) { threads[i] = std::thread(thread_func, i); @@ -49,6 +71,14 @@ int main(int argc, char **argv) { std::cout << "Main thread at barrier\n"; + // Call bar for second breakpoint. + int result_bar = bar(5); + (void)result_bar; + + // Call baz for third breakpoint. + int result_baz = baz(11); + (void)result_baz; + for (int i = 0; i < NUM_THREADS; i++) threads[i].join(); diff --git a/lldb/test/API/lang/cpp/const_this/TestConstThis.py b/lldb/test/API/lang/cpp/const_this/TestConstThis.py index 4b7d3aadb62ab..c2df61fde2b58 100644 --- a/lldb/test/API/lang/cpp/const_this/TestConstThis.py +++ b/lldb/test/API/lang/cpp/const_this/TestConstThis.py @@ -11,10 +11,9 @@ def run_class_tests(self): # Expression not referencing context class. self.expect_expr("1 + 1", result_type="int", result_value="2") # Referencing context class. - # FIXME: This and the expression below should return const types. - self.expect_expr("member", result_type="int", result_value="3") + self.expect_expr("member", result_type="const int", result_value="3") # Check the type of context class. - self.expect_expr("this", result_type="ContextClass *") + self.expect_expr("this", result_type="const ContextClass *") def test_member_func(self): self.build() @@ -36,10 +35,9 @@ def run_template_class_tests(self): # Expression not referencing context class. self.expect_expr("1 + 1", result_type="int", result_value="2") # Referencing context class. - # FIXME: This and the expression below should return const types. - self.expect_expr("member", result_type="int", result_value="4") + self.expect_expr("member", result_type="const int", result_value="4") # Check the type of context class. - self.expect_expr("this", result_type="TemplatedContextClass *") + self.expect_expr("this", result_type="const TemplatedContextClass *") def test_template_member_func(self): self.build() diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/Makefile b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/TestExprInConstMethod.py b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/TestExprInConstMethod.py new file mode 100644 index 0000000000000..a00fe4d5f314b --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/TestExprInConstMethod.py @@ -0,0 +1,137 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestCase(TestBase): + def test(self): + self.build() + (_, process, _, _) = lldbutil.run_to_source_breakpoint( + self, "Break: const_method begin", lldb.SBFileSpec("main.cpp") + ) + + self.expect_expr("bar()", result_value="2", result_type="int") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + matching=False, + ) + self.expect( + "expression m_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("m_mem", result_value="-2") + + # Test short and long --c++-ignore-context-qualifiers option. + self.expect( + "expression --c++-ignore-context-qualifiers -- m_mem = 3.0", + error=False, + ) + self.expect_expr("m_mem", result_value="3") + + self.expect( + "expression -Q -- m_mem = 4.0", + error=False, + ) + self.expect_expr("m_mem", result_value="4") + + # Test --c++-ignore-context-qualifiers via SBExpressionOptions. + options = lldb.SBExpressionOptions() + options.SetBooleanLanguageOption("c++-ignore-context-qualifiers", True) + self.expect_expr("m_mem = -2.0; m_mem", options=options, result_value="-2") + + self.expect_expr("((Foo*)this)->bar()", result_type="double", result_value="5") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: const_method no-this lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect( + "expression x = 7.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("x", result_value="2") + + self.expect_expr("x = -5; x", options=options, result_value="-5") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: const_method mutable no-this lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("x = 7.0; x", result_value="7") + + lldbutil.continue_to_source_breakpoint( + self, process, "Break: const_method lambda", lldb.SBFileSpec("main.cpp") + ) + + # FIXME: mutating this capture should be disallowed in a non-mutable lambda. + self.expect_expr("y = 8.0") + self.expect_expr("bar()", result_value="2", result_type="int") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + matching=False, + ) + self.expect( + "expression m_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("m_mem", result_value="-2") + + self.expect_expr("m_mem = -1; m_mem", options=options, result_value="-1") + + self.expect_expr("((Foo*)this)->bar()", result_type="double", result_value="5") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: const_method mutable lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("y = 9.0") + self.expect_expr("bar()", result_value="2", result_type="int") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + matching=False, + ) + self.expect( + "expression m_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("m_mem", result_value="-1") + + self.expect_expr("m_mem = -2; m_mem", options=options, result_value="-2") diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/main.cpp b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/main.cpp new file mode 100644 index 0000000000000..7cb74767b458a --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_method/main.cpp @@ -0,0 +1,49 @@ +#include +#include + +struct Foo { + double bar() { return 5.0; } + + int bar() const { return 2; } + + int const_method() const { + auto x = bar(); + assert(x == 2); + std::puts("Break: const_method begin"); + + [x] { + std::puts("Keep on multiple lines..."); + std::puts("Break: const_method no-this lambda"); + }(); + + [x]() mutable { + std::puts("Keep on multiple lines..."); + std::puts("Break: const_method mutable no-this lambda"); + }(); + + [this, y = x] { + auto x = bar() + y; + std::puts("Break: const_method lambda"); + }(); + + [this, y = x]() mutable { + auto x = bar() + y; + std::puts("Break: const_method mutable lambda"); + }(); + + return 120; + } + + float m_mem = -2.0; + const float m_const_mem = -3.0; +}; + +int main() { + const Foo f; + f.bar(); + + Foo f2; + f2.bar(); + + return Foo{}.const_method(); +} diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/Makefile b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/TestExprInConstVolatileMethod.py b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/TestExprInConstVolatileMethod.py new file mode 100644 index 0000000000000..6d983dc5108a8 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/TestExprInConstVolatileMethod.py @@ -0,0 +1,95 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestCase(TestBase): + def test(self): + self.build() + (_, process, _, _) = lldbutil.run_to_source_breakpoint( + self, "Break here: const", lldb.SBFileSpec("main.cpp") + ) + + self.expect_expr("bar()", result_type="double", result_value="5") + self.expect_expr("const_volatile_method()") + self.expect_expr("const_method()") + self.expect( + "expression volatile_method()", + error=True, + substrs=[ + "has type 'const Foo'", + "but function is not marked const", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + + options = lldb.SBExpressionOptions() + options.SetBooleanLanguageOption("c++-ignore-context-qualifiers", True) + options.SetIgnoreBreakpoints(True) + self.expect_expr("volatile_method()", options=options) + self.expect( + "expression --c++-ignore-context-qualifiers -- bar()", + error=True, + substrs=["call to member function 'bar' is ambiguous"], + ) + + lldbutil.continue_to_source_breakpoint( + self, process, "Break here: volatile", lldb.SBFileSpec("main.cpp") + ) + + self.expect_expr( + "bar()", result_type="const char *", result_summary='"volatile_bar"' + ) + self.expect_expr("const_volatile_method()") + self.expect( + "expression const_method()", + error=True, + substrs=[ + "has type 'volatile Foo'", + "but function is not marked volatile", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("volatile_method()") + + self.expect_expr("const_method()", options=options) + self.expect( + "expression --c++-ignore-context-qualifiers -- bar()", + error=True, + substrs=["call to member function 'bar' is ambiguous"], + ) + + lldbutil.continue_to_source_breakpoint( + self, process, "Break here: const volatile", lldb.SBFileSpec("main.cpp") + ) + + self.expect_expr("bar()", result_type="int", result_value="2") + self.expect_expr("other_cv_method()") + + self.expect( + "expression const_method()", + error=True, + substrs=[ + "has type 'const volatile Foo'", + "but function is not marked const or volatile", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect( + "expression volatile_method()", + error=True, + substrs=[ + "has type 'const volatile Foo'", + "but function is not marked const or volatile", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + + self.expect_expr("const_method()", options=options) + self.expect_expr("volatile_method()", options=options) + self.expect( + "expression --c++-ignore-context-qualifiers -- bar()", + error=True, + substrs=["call to member function 'bar' is ambiguous"], + ) diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/main.cpp b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/main.cpp new file mode 100644 index 0000000000000..da0f7e7d1be95 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/const_volatile_method/main.cpp @@ -0,0 +1,43 @@ +#include +#include + +struct Foo { + double bar() const { return 5.0; } + const char *bar() volatile { return "volatile_bar"; } + int bar() volatile const { return 2; } + + int volatile_method() volatile { + std::puts("Break here: volatile"); + return 0; + } + int const_method() const { + std::puts("Break here: const"); + return 0; + } + int other_cv_method() const volatile { return 20; } + + int const_volatile_method() const volatile { + auto x = bar(); + assert(x == 2); + other_cv_method(); + + std::puts("Break here: const volatile"); + + return 120; + } +}; + +int main() { + const Foo f; + f.bar(); + f.const_method(); + + volatile Foo f2; + f2.bar(); + f2.volatile_method(); + + const volatile Foo f3; + f3.bar(); + + return Foo{}.const_volatile_method(); +} diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/Makefile b/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/TestExprOnCVQualifiedObjects.py b/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/TestExprOnCVQualifiedObjects.py new file mode 100644 index 0000000000000..0f661471df749 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/TestExprOnCVQualifiedObjects.py @@ -0,0 +1,21 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestCase(TestBase): + def test(self): + self.build() + lldbutil.run_to_source_breakpoint( + self, + "Break here", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("f.bar()", result_type="double", result_value="5") + self.expect_expr("cf.bar()", result_type="int", result_value="2") + self.expect_expr("vf.bar()", result_type="short", result_value="8") + self.expect_expr( + "cvf.bar()", result_type="const char *", result_summary='"volatile"' + ) diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/main.cpp b/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/main.cpp new file mode 100644 index 0000000000000..eb7f8b82f2695 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/cv_qualified_objects/main.cpp @@ -0,0 +1,25 @@ +#include + +struct Foo { + double bar() { return 5.0; } + int bar() const { return 2; } + short bar() volatile { return 8; } + char const *bar() const volatile { return "volatile"; } + + float m_mem = -2.0; + const float m_const_mem = -3.0; +}; + +int main() { + Foo f; + const Foo cf; + volatile Foo vf; + const volatile Foo cvf; + + f.bar(); + cf.bar(); + vf.bar(); + cvf.bar(); + + std::puts("Break here"); +} diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/Makefile b/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/TestExprInConstMethodWithFixit.py b/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/TestExprInConstMethodWithFixit.py new file mode 100644 index 0000000000000..80e657712a525 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/TestExprInConstMethodWithFixit.py @@ -0,0 +1,69 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestCase(TestBase): + def test(self): + self.build() + (_, process, _, _) = lldbutil.run_to_source_breakpoint( + self, "Break here", lldb.SBFileSpec("main.cpp") + ) + + self.expect( + "expression m_bar->method()", + error=True, + substrs=[ + "member reference type 'const Bar' is not a pointer", + "but function is not marked const", + "Possibly trying to mutate object in a const context. Try running the expression with", + "expression --c++-ignore-context-qualifiers -- m_bar.method()", + ], + ) + + # Two fix-its... + self.expect( + "expression -- m_bar->method() + m_bar->method()", + error=True, + substrs=[ + "member reference type 'const Bar' is not a pointer", + "but function is not marked const", + "member reference type 'const Bar' is not a pointer", + "but function is not marked const", + ], + ) + + # ...only emit a single hint. + self.assertEqual( + self.res.GetError().count( + "Possibly trying to mutate object in a const context." + ), + 1, + ) + + self.expect( + "expression -Q -- m_bar->method()", + error=True, + substrs=["Evaluated this expression after applying Fix-It(s):"], + ) + + self.expect( + "expression m_bar->method() + blah", + error=True, + substrs=[ + "member reference type 'const Bar' is not a pointer", + "but function is not marked const", + "Possibly trying to mutate object in a const context. Try running the expression with", + "expression --c++-ignore-context-qualifiers -- m_bar.method() + blah", + ], + ) + + self.expect( + "expression -Q -- m_bar->method() + blah", + error=True, + substrs=[ + "Possibly trying to mutate object in a const context. Try running the expression with", + ], + matching=False, + ) diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/main.cpp b/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/main.cpp new file mode 100644 index 0000000000000..1dab96e2986da --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/fixit/main.cpp @@ -0,0 +1,22 @@ +#include +#include + +struct Bar { + void method() {} +}; + +struct Foo { + int const_method() const { + std::puts("Break here"); + + return 120; + } + + Bar m_bar; +}; + +int main() { + Foo{}.m_bar.method(); + + return Foo{}.const_method(); +} diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/Makefile b/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/TestExprInNonConstMethod.py b/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/TestExprInNonConstMethod.py new file mode 100644 index 0000000000000..280cf9249d82e --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/TestExprInNonConstMethod.py @@ -0,0 +1,87 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestCase(TestBase): + def test(self): + self.build() + (_, process, _, _) = lldbutil.run_to_source_breakpoint( + self, "Break: non_const_method begin", lldb.SBFileSpec("main.cpp") + ) + + self.expect_expr("bar()", result_value="5", result_type="double") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: non_const_method no-this lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect( + "expression x = 7.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + + options = lldb.SBExpressionOptions() + options.SetBooleanLanguageOption("c++-ignore-context-qualifiers", True) + self.expect_expr("x = 6.0; x", options=options, result_value="6") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: non_const_method mutable no-this lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("x = 7.0; x", result_value="7") + + lldbutil.continue_to_source_breakpoint( + self, process, "Break: non_const_method lambda", lldb.SBFileSpec("main.cpp") + ) + + # FIXME: mutating this capture should be disallowed in a non-mutable lambda. + self.expect_expr("y = 8.0") + self.expect_expr("bar()", result_value="5", result_type="double") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + self.expect_expr("m_mem = 2.0; m_mem", result_value="2") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: non_const_method mutable lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("y = 9.0") + self.expect_expr("bar()", result_value="5", result_type="double") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + self.expect_expr("m_mem = 4.0; m_mem", result_value="4") diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/main.cpp b/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/main.cpp new file mode 100644 index 0000000000000..141f63b6f2f24 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/non_const_method/main.cpp @@ -0,0 +1,49 @@ +#include +#include + +struct Foo { + double bar() { return 5.0; } + + int bar() const { return 2; } + + int non_const_method() { + auto x = bar(); + assert(x == 5.0); + std::puts("Break: non_const_method begin"); + + [x] { + std::puts("Keep on multiple lines..."); + std::puts("Break: non_const_method no-this lambda"); + }(); + + [x]() mutable { + std::puts("Keep on multiple lines..."); + std::puts("Break: non_const_method mutable no-this lambda"); + }(); + + [this, y = x] { + auto x = bar() + y; + std::puts("Break: non_const_method lambda"); + }(); + + [this, y = x]() mutable { + auto x = bar() + y; + std::puts("Break: non_const_method mutable lambda"); + }(); + + return 120; + } + + float m_mem = -2.0; + const float m_const_mem = -3.0; +}; + +int main() { + const Foo f; + f.bar(); + + Foo f2; + f2.bar(); + + return Foo{}.non_const_method(); +} diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/Makefile b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/TestExprInTemplateConstMethod.py b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/TestExprInTemplateConstMethod.py new file mode 100644 index 0000000000000..f26bf618d4339 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/TestExprInTemplateConstMethod.py @@ -0,0 +1,115 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestCase(TestBase): + def test(self): + self.build() + (_, process, _, _) = lldbutil.run_to_source_breakpoint( + self, "Break: const_method begin", lldb.SBFileSpec("main.cpp") + ) + + self.expect_expr("bar()", result_value="2", result_type="int") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + self.expect( + "expression m_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("((Foo*)this)->bar()", result_type="double", result_value="5") + + options = lldb.SBExpressionOptions() + options.SetBooleanLanguageOption("c++-ignore-context-qualifiers", True) + self.expect_expr("m_mem = -2.0; m_mem", options=options, result_value="-2") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: const_method no-this lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect( + "expression x = 7.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("x = -7.0; x", options=options, result_value="-7") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: const_method mutable no-this lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("x = 7.0; x", result_value="7") + + lldbutil.continue_to_source_breakpoint( + self, process, "Break: const_method lambda", lldb.SBFileSpec("main.cpp") + ) + + # FIXME: mutating this capture should be disallowed in a non-mutable lambda. + self.expect_expr("y = 8.0") + self.expect_expr("bar()", result_value="2", result_type="int") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + self.expect( + "expression m_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("m_mem", result_value="-2") + self.expect_expr("((Foo*)this)->bar()", result_type="double", result_value="5") + self.expect_expr("m_mem = -8.0; m_mem", options=options, result_value="-8") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: const_method mutable lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("y = 9.0") + self.expect_expr("bar()", result_value="2", result_type="int") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + self.expect( + "expression m_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + ], + ) + self.expect_expr("m_mem = -11.0; m_mem", options=options, result_value="-11") diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/main.cpp b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/main.cpp new file mode 100644 index 0000000000000..8238f2a52f5aa --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_const_method/main.cpp @@ -0,0 +1,51 @@ +#include +#include + +struct Foo { + double bar() { return 5.0; } + + int bar() const { return 2; } + + void non_const_method() {} + + int template_const_method() const { + auto x = bar(); + assert(x == 2); + std::puts("Break: const_method begin"); + + [x] { + std::puts("Keep on multiple lines..."); + std::puts("Break: const_method no-this lambda"); + }(); + + [x]() mutable { + std::puts("Keep on multiple lines..."); + std::puts("Break: const_method mutable no-this lambda"); + }(); + + [this, y = x] { + auto x = bar() + y; + std::puts("Break: const_method lambda"); + }(); + + [this, y = x]() mutable { + auto x = bar() + y; + std::puts("Break: const_method mutable lambda"); + }(); + + return 120; + } + + float m_mem = -2.0; + const float m_const_mem = -3.0; +}; + +int main() { + const Foo f; + f.bar(); + + Foo f2; + f2.bar(); + + return Foo{}.template_const_method(); +} diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/Makefile b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/TestExprInTemplateNonConstMethod.py b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/TestExprInTemplateNonConstMethod.py new file mode 100644 index 0000000000000..dd84099d6060e --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/TestExprInTemplateNonConstMethod.py @@ -0,0 +1,88 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestCase(TestBase): + def test(self): + self.build() + (_, process, _, _) = lldbutil.run_to_source_breakpoint( + self, "Break: non_const_method begin", lldb.SBFileSpec("main.cpp") + ) + + self.expect_expr("bar()", result_value="5", result_type="double") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: non_const_method no-this lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect( + "expression x = 7.0", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "note: Possibly trying to mutate object in a const context. Try running the expression with", + "expression --c++-ignore-context-qualifiers -- x = 7.0", + ], + ) + + options = lldb.SBExpressionOptions() + options.SetBooleanLanguageOption("c++-ignore-context-qualifiers", True) + self.expect_expr("x = 6.0; x", options=options, result_value="6") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: non_const_method mutable no-this lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("x = 7.0; x", result_value="7") + + lldbutil.continue_to_source_breakpoint( + self, process, "Break: non_const_method lambda", lldb.SBFileSpec("main.cpp") + ) + + # FIXME: mutating this capture should be disallowed in a non-mutable lambda. + self.expect_expr("y = 8.0") + self.expect_expr("bar()", result_value="5", result_type="double") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + self.expect_expr("m_mem = 2.0; m_mem", result_value="2") + + lldbutil.continue_to_source_breakpoint( + self, + process, + "Break: non_const_method mutable lambda", + lldb.SBFileSpec("main.cpp"), + ) + + self.expect_expr("y = 9.0") + self.expect_expr("bar()", result_value="5", result_type="double") + self.expect( + "expression m_const_mem = 2.0", + error=True, + substrs=[ + "cannot assign to non-static data member", + "with const-qualified type", + ], + ) + self.expect_expr("m_mem = 4.0; m_mem", result_value="4") diff --git a/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/main.cpp b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/main.cpp new file mode 100644 index 0000000000000..1632555c69d01 --- /dev/null +++ b/lldb/test/API/lang/cpp/expression-context-qualifiers/template_non_const_method/main.cpp @@ -0,0 +1,49 @@ +#include +#include + +struct Foo { + double bar() { return 5.0; } + + int bar() const { return 2; } + + int template_non_const_method() { + auto x = bar(); + assert(x == 5.0); + std::puts("Break: non_const_method begin"); + + [x] { + std::puts("Keep on multiple lines..."); + std::puts("Break: non_const_method no-this lambda"); + }(); + + [x]() mutable { + std::puts("Keep on multiple lines..."); + std::puts("Break: non_const_method mutable no-this lambda"); + }(); + + [this, y = x] { + auto x = bar() + y; + std::puts("Break: non_const_method lambda"); + }(); + + [this, y = x]() mutable { + auto x = bar() + y; + std::puts("Break: non_const_method mutable lambda"); + }(); + + return 120; + } + + float m_mem = -2.0; + const float m_const_mem = -3.0; +}; + +int main() { + const Foo f; + f.bar(); + + Foo f2; + f2.bar(); + + return Foo{}.template_non_const_method(); +} diff --git a/lldb/test/API/lang/cpp/template-arguments/TestCppTemplateArguments.py b/lldb/test/API/lang/cpp/template-arguments/TestCppTemplateArguments.py index 83c057220410a..0a757d3368a44 100644 --- a/lldb/test/API/lang/cpp/template-arguments/TestCppTemplateArguments.py +++ b/lldb/test/API/lang/cpp/template-arguments/TestCppTemplateArguments.py @@ -79,16 +79,21 @@ def test(self): value = self.expect_expr("temp6", result_type="Foo") self.assertFalse(value.GetType().GetTemplateArgumentValue(target, 1)) - # FIXME: support wider range of floating point types - value = self.expect_expr("temp7", result_type="Foo<__fp16, __fp16>") - self.assertFalse(value.GetType().GetTemplateArgumentValue(target, 1)) + value = self.expect_expr("temp7", result_type="Foo<__fp16, 1.000000e+00>") + template_param_value = value.GetType().GetTemplateArgumentValue(target, 1) + self.assertEqual(template_param_value.GetTypeName(), "__fp16") + # FIXME: returns incorrect value? + self.assertEqual(template_param_value.GetValueAsSigned(), 0) # The target we use when evaluating these expressions for Arm leads to there # not being a __bf16 type in the AST so we fall back to __fp16 and evaluating # this fails. if lldbplatformutil.getArchitecture() != "arm": - value = self.expect_expr("temp8", result_type="Foo<__bf16, __bf16>") - self.assertFalse(value.GetType().GetTemplateArgumentValue(target, 1)) + value = self.expect_expr("temp8", result_type="Foo<__bf16, 1.000000e+00>") + # FIXME: typename should be __bf16 + self.assertEqual(template_param_value.GetTypeName(), "__fp16") + # FIXME: returns incorrect value? + self.assertEqual(template_param_value.GetValueAsSigned(), 0) value = self.expect_expr("temp9", result_type="Bar") template_param_value = value.GetType().GetTemplateArgumentValue(target, 1) diff --git a/lldb/test/API/lang/cpp/template-diagnostic-hint/Makefile b/lldb/test/API/lang/cpp/template-diagnostic-hint/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/lang/cpp/template-diagnostic-hint/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/lang/cpp/template-diagnostic-hint/TestTemplateDiagnosticHint.py b/lldb/test/API/lang/cpp/template-diagnostic-hint/TestTemplateDiagnosticHint.py new file mode 100644 index 0000000000000..cd6706b450aa5 --- /dev/null +++ b/lldb/test/API/lang/cpp/template-diagnostic-hint/TestTemplateDiagnosticHint.py @@ -0,0 +1,49 @@ +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestCase(TestBase): + @expectedFailureWindows + def test(self): + self.build() + (_, process, _, _) = lldbutil.run_to_source_breakpoint( + self, "main", lldb.SBFileSpec("main.cpp") + ) + + self.expect( + "expression some_template_func(5)", + error=True, + substrs=[ + "does not name a template but is followed by template arguments", + "note: Naming template instantiation not yet supported.", + "Template functions can be invoked via their mangled name.", + ], + ) + + self.expect( + "expression some_template_func(5) + some_template_func(5)", + error=True, + substrs=[ + "does not name a template but is followed by template arguments", + "does not name a template but is followed by template arguments", + ], + ) + + self.assertEqual( + self.res.GetError().count( + "note: Naming template instantiation not yet supported" + ), + 1, + ) + + self.expect( + "expression Foo::smethod()", + error=True, + substrs=[ + "no template named 'Foo'", + "note: Naming template instantiation not yet supported.", + "Template functions can be invoked via their mangled name.", + ], + ) diff --git a/lldb/test/API/lang/cpp/template-diagnostic-hint/main.cpp b/lldb/test/API/lang/cpp/template-diagnostic-hint/main.cpp new file mode 100644 index 0000000000000..914d9b59484de --- /dev/null +++ b/lldb/test/API/lang/cpp/template-diagnostic-hint/main.cpp @@ -0,0 +1,14 @@ +template static K some_template_func(int x) { + return (K)x; +} + +template struct Foo { + template T method(K k) { return (T)k; } + static T smethod() { return (T)10; } +}; + +int main() { + Foo f; + return some_template_func(5) + Foo::smethod() + + f.method(10); +} diff --git a/lldb/test/API/lang/cpp/this/TestCPPThis.py b/lldb/test/API/lang/cpp/this/TestCPPThis.py index c9dcf30b53443..81be8a80b84c0 100644 --- a/lldb/test/API/lang/cpp/this/TestCPPThis.py +++ b/lldb/test/API/lang/cpp/this/TestCPPThis.py @@ -1,6 +1,7 @@ """ Tests that C++ member and static variables are available where they should be. """ + import lldb from lldbsuite.test.decorators import * from lldbsuite.test.lldbtest import * @@ -37,10 +38,20 @@ def test_with_run_command(self): self.runCmd("process continue") - # This would be disallowed if we enforced const. But we don't. - self.expect("expression -- m_a = 2", startstr="(int) $1 = 2") + self.expect( + "expression -- m_a = 2", + error=True, + substrs=[ + "cannot assign to non-static data member within const member function", + "Possibly trying to mutate object in a const context. Try running the expression with: expression --c++-ignore-context-qualifiers -- m_a = 2", + ], + ) - self.expect("expression -- (int)getpid(); m_a", startstr="(int) $2 = 2") + self.expect("expression -- (int)getpid(); m_a", startstr="(const int) $1 = 3") + self.expect( + "expression --c++-ignore-context-qualifiers -- m_a = 2", + startstr="(int) $2 = 2", + ) self.runCmd("process continue") diff --git a/lldb/test/API/macosx/extended-backtrace-api/Makefile b/lldb/test/API/macosx/extended-backtrace-api/Makefile new file mode 100644 index 0000000000000..845553d5e3f2f --- /dev/null +++ b/lldb/test/API/macosx/extended-backtrace-api/Makefile @@ -0,0 +1,3 @@ +OBJC_SOURCES := main.m + +include Makefile.rules diff --git a/lldb/test/API/macosx/extended-backtrace-api/TestExtendedBacktraceAPI.py b/lldb/test/API/macosx/extended-backtrace-api/TestExtendedBacktraceAPI.py new file mode 100644 index 0000000000000..0e9ee0755065e --- /dev/null +++ b/lldb/test/API/macosx/extended-backtrace-api/TestExtendedBacktraceAPI.py @@ -0,0 +1,144 @@ +"""Test SBThread.GetExtendedBacktraceThread API with queue debugging.""" + +import os +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestExtendedBacktraceAPI(TestBase): + NO_DEBUG_INFO_TESTCASE = True + + def setUp(self): + TestBase.setUp(self) + self.main_source = "main.m" + + @skipUnlessDarwin + @add_test_categories(["objc", "pyapi"]) + def test_extended_backtrace_thread_api(self): + """Test GetExtendedBacktraceThread with queue debugging.""" + self.build() + exe = self.getBuildArtifact("a.out") + + # Get Xcode developer directory path. + # Try DEVELOPER_DIR environment variable first, then fall back to xcode-select. + xcode_dev_path = os.environ.get("DEVELOPER_DIR") + + if not xcode_dev_path: + import subprocess + + xcode_dev_path = ( + subprocess.check_output(["xcode-select", "-p"]).decode("utf-8").strip() + ) + + # Check for libBacktraceRecording.dylib. + libbtr_path = os.path.join( + xcode_dev_path, "usr/lib/libBacktraceRecording.dylib" + ) + + self.assertTrue( + os.path.isfile(libbtr_path), + f"libBacktraceRecording.dylib is not present at {libbtr_path}", + ) + + self.assertTrue( + os.path.isfile("/usr/lib/system/introspection/libdispatch.dylib"), + "introspection libdispatch dylib not installed.", + ) + + # Create launch info with environment variables for libBacktraceRecording. + launch_info = lldb.SBLaunchInfo(None) + launch_info.SetWorkingDirectory(self.get_process_working_directory()) + launch_info.SetEnvironmentEntries( + [ + f"DYLD_INSERT_LIBRARIES={libbtr_path}", + "DYLD_LIBRARY_PATH=/usr/lib/system/introspection", + ], + True, + ) + + # Launch the process and run to breakpoint. + target, process, thread, bp = lldbutil.run_to_name_breakpoint( + self, "do_work_level_5", launch_info=launch_info, bkpt_module="a.out" + ) + + self.assertTrue(target.IsValid(), VALID_TARGET) + self.assertTrue(process.IsValid(), PROCESS_IS_VALID) + self.assertTrue(thread.IsValid(), "Stopped thread is valid") + self.assertTrue(bp.IsValid(), VALID_BREAKPOINT) + + # Call GetNumQueues to ensure queue information is loaded. + num_queues = process.GetNumQueues() + + # Check that we can find the com.apple.main-thread queue. + main_thread_queue_found = False + for i in range(num_queues): + queue = process.GetQueueAtIndex(i) + if queue.GetName() == "com.apple.main-thread": + main_thread_queue_found = True + break + + # Verify we have at least 5 frames. + self.assertGreaterEqual( + thread.GetNumFrames(), + 5, + "Thread should have at least 5 frames in backtrace", + ) + + # Get frame 2 BEFORE calling GetExtendedBacktraceThread. + # This mimics what Xcode does - it has the frame objects ready. + frame2 = thread.GetFrameAtIndex(2) + self.assertTrue(frame2.IsValid(), "Frame 2 is valid") + + # Now test GetExtendedBacktraceThread. + # This is the critical part - getting the extended backtrace calls into + # libBacktraceRecording which does an inferior function call, and this + # invalidates/clears the unwinder state. + extended_thread = thread.GetExtendedBacktraceThread("libdispatch") + + # This should be valid since we injected libBacktraceRecording. + self.assertTrue( + extended_thread.IsValid(), + "Extended backtrace thread for 'libdispatch' should be valid with libBacktraceRecording loaded", + ) + + # The extended thread should have frames. + self.assertGreater( + extended_thread.GetNumFrames(), + 0, + "Extended backtrace thread should have at least one frame", + ) + + # Test frame 2 on the extended backtrace thread. + self.assertGreater( + extended_thread.GetNumFrames(), + 2, + "Extended backtrace thread should have at least 3 frames to access frame 2", + ) + + extended_frame2 = extended_thread.GetFrameAtIndex(2) + self.assertTrue(extended_frame2.IsValid(), "Extended thread frame 2 is valid") + + # NOW try to access variables from frame 2 of the ORIGINAL thread. + # This is the key test - after GetExtendedBacktraceThread() has executed + # an inferior function call, the unwinder state may be invalidated. + # Xcode exhibits this bug where variables show "register fp is not available" + # after extended backtrace retrieval. + + # Set frame 2 as the selected frame so expect_var_path works. + thread.SetSelectedFrame(2) + + variables = frame2.GetVariables(False, True, False, True) + self.assertGreater( + variables.GetSize(), 0, "Frame 2 should have at least one variable" + ) + + # Test all variables in frame 2, like Xcode does. + # Use expect_var_path to verify each variable is accessible without errors. + for i in range(variables.GetSize()): + var = variables.GetValueAtIndex(i) + var_name = var.GetName() + + # This will fail if the variable contains "not available" or has errors. + self.expect_var_path(var_name) diff --git a/lldb/test/API/macosx/extended-backtrace-api/main.m b/lldb/test/API/macosx/extended-backtrace-api/main.m new file mode 100644 index 0000000000000..8f2186845a651 --- /dev/null +++ b/lldb/test/API/macosx/extended-backtrace-api/main.m @@ -0,0 +1,53 @@ +#include +#include +#include +#include + +void do_work_level_5(void) { + // Frame 0 will have these variables. + int frame0_var = 100; + const char *frame0_string = "frame_zero"; + float frame0_float = 1.5f; + + // This is where we'll set the breakpoint. + printf("Level 5 work executing\n"); // Break here. + while (1) + sleep(1); +} + +void do_work_level_4(void) { + // Frame 1 will have these variables. + int frame1_var = 200; + const char *frame1_string = "frame_one"; + long frame1_long = 9876543210L; + + do_work_level_5(); +} + +void do_work_level_3(void) { + // Frame 2 will have these variables. + int test_variable = 42; + const char *test_string = "test_value"; + double test_double = 3.14159; + + do_work_level_4(); +} + +void do_work_level_2(void) { do_work_level_3(); } + +void do_work_level_1(void *context) { do_work_level_2(); } + +int main(int argc, const char *argv[]) { + // Create a serial dispatch queue. + dispatch_queue_t worker_queue = + dispatch_queue_create("com.test.worker_queue", DISPATCH_QUEUE_SERIAL); + dispatch_queue_t submitter_queue = + dispatch_queue_create("com.test.submitter_queue", DISPATCH_QUEUE_SERIAL); + + // Submit work from one queue to another to create extended backtrace. + dispatch_async_f(submitter_queue, &worker_queue, do_work_level_1); + + // Keep main thread alive. + dispatch_main(); + return 0; +} diff --git a/lldb/test/API/macosx/stop-reason-exception/Makefile b/lldb/test/API/macosx/stop-reason-exception/Makefile new file mode 100644 index 0000000000000..695335e068c0c --- /dev/null +++ b/lldb/test/API/macosx/stop-reason-exception/Makefile @@ -0,0 +1,4 @@ +C_SOURCES := main.c +CFLAGS_EXTRAS := -std=c99 + +include Makefile.rules diff --git a/lldb/test/API/macosx/stop-reason-exception/TestMachExceptionData.py b/lldb/test/API/macosx/stop-reason-exception/TestMachExceptionData.py new file mode 100644 index 0000000000000..36b1c21feefee --- /dev/null +++ b/lldb/test/API/macosx/stop-reason-exception/TestMachExceptionData.py @@ -0,0 +1,36 @@ +""" +Test that we get the type code and subcode for MachExceptions +""" + + +import lldb +import lldbsuite.test.lldbutil as lldbutil +from lldbsuite.test.lldbtest import * +from lldbsuite.test.decorators import * + + +class TestMachExceptionData(TestBase): + NO_DEBUG_INFO_TESTCASE = True + + @skipUnlessDarwin + def test_exc_bad_access(self): + """Test that we get type 1, code 1 and the right address for + a EXC_BAD_ACCESS mach exception.""" + self.build() + self.main_source_file = lldb.SBFileSpec("main.c") + + (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint( + self, "Set a breakpoint here", self.main_source_file + ) + + # Now continue and we should crash: + process.Continue() + self.assertEqual( + lldb.eStopReasonException, + thread.GetStopReason(), + "Got the right stop reason", + ) + self.assertEqual(thread.GetStopReasonDataCount(), 3, "Got all the codes") + self.assertEqual(thread.stop_reason_data[0], 1, "1 is EXC_BAD_ACCESS") + self.assertEqual(thread.stop_reason_data[1], 1, "1 is 'access invalid memory'") + self.assertEqual(thread.stop_reason_data[2], 0x400, "That's the bad address") diff --git a/lldb/test/API/macosx/stop-reason-exception/main.c b/lldb/test/API/macosx/stop-reason-exception/main.c new file mode 100644 index 0000000000000..85b9875c3870b --- /dev/null +++ b/lldb/test/API/macosx/stop-reason-exception/main.c @@ -0,0 +1,5 @@ +int main() { + char *bad_ptr = (char *)0x400; // Set a breakpoint here + bad_ptr[0] = 'a'; + return 0; +} diff --git a/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py b/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py index 3be0a85d59500..3d35c2994aebd 100644 --- a/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py +++ b/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py @@ -16,7 +16,7 @@ class AttachCancelTestCase(TestBase): @skipIf( remote=True, - hostoslist=["windows"], + hostoslist=["windows", "linux"], bugnumber="https://github.com/llvm/llvm-project/issues/115618", ) def test_scripted_implementation(self): diff --git a/lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py b/lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py index 5ed7e13fd0b44..2aac9310cb133 100644 --- a/lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py +++ b/lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_setExceptionBreakpoints.py @@ -35,5 +35,9 @@ def test_functionality(self): if response: self.assertTrue(response["success"]) - self.continue_to_exception_breakpoint(r"C\+\+ Throw") - self.continue_to_exception_breakpoint(r"C\+\+ Catch") + self.continue_to_exception_breakpoint( + expected_description=r"breakpoint 1\.1", expected_text=r"C\+\+ Throw" + ) + self.continue_to_exception_breakpoint( + expected_description=r"breakpoint 2\.1", expected_text=r"C\+\+ Catch" + ) diff --git a/lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py b/lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py index bc08462cfcba9..98ed0b9df228a 100644 --- a/lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py +++ b/lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py @@ -27,13 +27,15 @@ def assertEvaluate( want_varref=False, want_memref=True, want_locref=False, + frame_index: Optional[int] = 0, is_hex=None, ): resp = self.dap_server.request_evaluate( - expression, context=self.context, is_hex=is_hex + expression, context=self.context, is_hex=is_hex, frameIndex=frame_index ) self.assertTrue( - resp["success"], f"Failed to evaluate expression {expression!r}" + resp["success"], + f"Failed to evaluate expression {expression!r} in frame {frame_index}", ) body: EvaluateResponseBody = resp["body"] self.assertRegex( @@ -73,9 +75,14 @@ def assertEvaluate( ) def assertEvaluateFailure(self, expression): + response = self.dap_server.request_evaluate(expression, context=self.context) + self.assertFalse( + response["success"], + f"Expression:'{expression}' should fail in {self.context} context, got {response!r}", + ) self.assertNotIn( "result", - self.dap_server.request_evaluate(expression, context=self.context)["body"], + response["body"], ) def isResultExpandedDescription(self): @@ -203,10 +210,15 @@ def run_test_evaluate_expressions( "struct3", "0x.*0", want_varref=True, want_type="my_struct *" ) - if context == "repl": - # In the repl context expressions may be interpreted as lldb + if context == "repl" or context is None: + # In repl or unknown context expressions may be interpreted as lldb # commands since no variables have the same name as the command. self.assertEvaluate("list", r".*", want_memref=False) + # Changing the frame index should not make a difference + self.assertEvaluate( + "version", r".*lldb.+", want_memref=False, frame_index=1 + ) + else: self.assertEvaluateFailure("list") # local variable of a_function @@ -302,6 +314,21 @@ def run_test_evaluate_expressions( self.assertEvaluate("list", "42") self.assertEvaluate("static_int", "42") self.assertEvaluate("non_static_int", "43") + # variable from a different frame + self.assertEvaluate("var1", "20", frame_index=1) + + if self.isExpressionParsedExpected(): + # access global variable without a frame + # Run in variable mode to avoid interpreting it as a command + res = self.dap_server.request_evaluate( + "`lldb-dap repl-mode variable", context="repl" + ) + self.assertTrue(res["success"]) + self.assertEvaluate("static_int", "42", frame_index=None, want_memref=False) + res = self.dap_server.request_evaluate( + "`lldb-dap repl-mode auto", context="repl" + ) + self.assertTrue(res["success"]) self.assertEvaluateFailure("var1") self.assertEvaluateFailure("var2") diff --git a/lldb/test/API/tools/lldb-dap/eventStatistic/Makefile b/lldb/test/API/tools/lldb-dap/eventStatistic/Makefile new file mode 100644 index 0000000000000..b30baf48b972e --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/eventStatistic/Makefile @@ -0,0 +1,17 @@ +DYLIB_NAME := foo +DYLIB_CXX_SOURCES := foo.cpp +CXX_SOURCES := main.cpp + +LD_EXTRAS := -Wl,-rpath "-Wl,$(shell pwd)" +USE_LIBDL :=1 + +include Makefile.rules + +all: a.out.stripped + +a.out.stripped: + strip -o a.out.stripped a.out + +ifneq "$(CODESIGN)" "" + $(CODESIGN) -fs - a.out.stripped +endif \ No newline at end of file diff --git a/lldb/test/API/tools/lldb-dap/eventStatistic/TestVSCode_eventStatistic.py b/lldb/test/API/tools/lldb-dap/eventStatistic/TestVSCode_eventStatistic.py new file mode 100644 index 0000000000000..59a0bbcb5370e --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/eventStatistic/TestVSCode_eventStatistic.py @@ -0,0 +1,76 @@ +""" +Test lldb-dap terminated event +""" + +import dap_server +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +import json +import re + +import lldbdap_testcase +from lldbsuite.test import lldbutil + + +class TestDAP_eventStatistic(lldbdap_testcase.DAPTestCaseBase): + """ + + Test case that captures both initialized and terminated events. + + META-ONLY: Intended to succeed TestDAP_terminatedEvent.py, but upstream keeps updating that file, so both that and this file will probably exist for a while. + + """ + + def check_statistics_summary(self, statistics): + self.assertTrue(statistics["totalDebugInfoByteSize"] > 0) + self.assertTrue(statistics["totalDebugInfoEnabled"] > 0) + self.assertTrue(statistics["totalModuleCountHasDebugInfo"] > 0) + + self.assertNotIn("modules", statistics.keys()) + + def check_target_summary(self, statistics): + # lldb-dap debugs one target at a time + target = json.loads(statistics["targets"])[0] + self.assertIn("totalSharedLibraryEventHitCount", target) + + @skipIfWindows + @skipIfRemote + def test_terminated_event(self): + """ + Terminated Event + Now contains the statistics of a debug session: + metatdata: + totalDebugInfoByteSize > 0 + totalDebugInfoEnabled > 0 + totalModuleCountHasDebugInfo > 0 + ... + """ + + program_basename = "a.out.stripped" + program = self.getBuildArtifact(program_basename) + self.build_and_launch(program) + self.continue_to_exit() + + statistics = self.dap_server.wait_for_terminated()["body"]["$__lldb_statistics"] + self.check_statistics_summary(statistics) + self.check_target_summary(statistics) + + @skipIfWindows + @skipIfRemote + def test_initialized_event(self): + """ + Initialized Event + Now contains the statistics of a debug session: + totalDebugInfoByteSize > 0 + totalDebugInfoEnabled > 0 + totalModuleCountHasDebugInfo > 0 + ... + """ + + program_basename = "a.out" + program = self.getBuildArtifact(program_basename) + self.build_and_launch(program) + self.dap_server.wait_for_event("initialized") + statistics = self.dap_server.initialized_event["body"]["$__lldb_statistics"] + self.check_statistics_summary(statistics) + self.continue_to_exit() diff --git a/lldb/test/API/tools/lldb-dap/eventStatistic/foo.cpp b/lldb/test/API/tools/lldb-dap/eventStatistic/foo.cpp new file mode 100644 index 0000000000000..b6f33b8e070a4 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/eventStatistic/foo.cpp @@ -0,0 +1 @@ +int foo() { return 12; } diff --git a/lldb/test/API/tools/lldb-dap/eventStatistic/foo.h b/lldb/test/API/tools/lldb-dap/eventStatistic/foo.h new file mode 100644 index 0000000000000..5d5f8f0c9e786 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/eventStatistic/foo.h @@ -0,0 +1 @@ +int foo(); diff --git a/lldb/test/API/tools/lldb-dap/eventStatistic/main.cpp b/lldb/test/API/tools/lldb-dap/eventStatistic/main.cpp new file mode 100644 index 0000000000000..86044f561d257 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/eventStatistic/main.cpp @@ -0,0 +1,8 @@ +#include "foo.h" +#include + +int main(int argc, char const *argv[]) { + std::cout << "Hello World!" << std::endl; + foo(); + return 0; +} diff --git a/lldb/test/API/tools/lldb-dap/exception/asan/Makefile b/lldb/test/API/tools/lldb-dap/exception/asan/Makefile new file mode 100644 index 0000000000000..6f9c449a87cb7 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/exception/asan/Makefile @@ -0,0 +1,5 @@ +CXX_SOURCES := main.cpp +CXXFLAGS_EXTRAS := -fsanitize=address -g +LD_EXTRAS := -fsanitize=address + +include Makefile.rules diff --git a/lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py b/lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py new file mode 100644 index 0000000000000..0ce315d6e01b7 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/exception/asan/TestDAP_asan.py @@ -0,0 +1,26 @@ +""" +Test that we stop at runtime instrumentation locations (asan). +""" + +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +import lldbdap_testcase + + +class TestDAP_asan(lldbdap_testcase.DAPTestCaseBase): + @skipUnlessAddressSanitizer + def test_asan(self): + """ + Test that we stop at asan. + """ + program = self.getBuildArtifact("a.out") + self.build_and_launch(program) + self.do_continue() + + self.verify_stop_exception_info("Use of deallocated memory") + exceptionInfo = self.get_exceptionInfo() + self.assertEqual(exceptionInfo["breakMode"], "always") + self.assertRegex( + exceptionInfo["description"], r"fatal_error: heap-use-after-free" + ) + self.assertEqual(exceptionInfo["exceptionId"], "runtime-instrumentation") diff --git a/lldb/test/API/tools/lldb-dap/exception/runtime-instruments/categories b/lldb/test/API/tools/lldb-dap/exception/asan/categories similarity index 100% rename from lldb/test/API/tools/lldb-dap/exception/runtime-instruments/categories rename to lldb/test/API/tools/lldb-dap/exception/asan/categories diff --git a/lldb/test/API/tools/lldb-dap/exception/asan/main.cpp b/lldb/test/API/tools/lldb-dap/exception/asan/main.cpp new file mode 100644 index 0000000000000..ea5176d4fd06a --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/exception/asan/main.cpp @@ -0,0 +1,5 @@ +int main() { + int *array = new int[100]; + delete[] array; + return array[42]; // asan +} diff --git a/lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py b/lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py index 694cadb6ed2fe..89f96f428ec23 100644 --- a/lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py +++ b/lldb/test/API/tools/lldb-dap/exception/objc/TestDAP_exception_objc.py @@ -44,7 +44,10 @@ def test_break_on_throw_and_catch(self): if response: self.assertTrue(response["success"]) - self.continue_to_exception_breakpoint("Objective-C Throw") + self.continue_to_exception_breakpoint( + expected_description="hit Objective-C exception", + expected_text="Objective-C Throw", + ) # FIXME: Catching objc exceptions do not appear to be working. # Xcode appears to set a breakpoint on '__cxa_begin_catch' for objc diff --git a/lldb/test/API/tools/lldb-dap/exception/runtime-instruments/Makefile b/lldb/test/API/tools/lldb-dap/exception/ubsan/Makefile similarity index 100% rename from lldb/test/API/tools/lldb-dap/exception/runtime-instruments/Makefile rename to lldb/test/API/tools/lldb-dap/exception/ubsan/Makefile diff --git a/lldb/test/API/tools/lldb-dap/exception/runtime-instruments/TestDAP_runtime_instruments.py b/lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py similarity index 80% rename from lldb/test/API/tools/lldb-dap/exception/runtime-instruments/TestDAP_runtime_instruments.py rename to lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py index ffc02c9b60fd7..270c7f0a22a89 100644 --- a/lldb/test/API/tools/lldb-dap/exception/runtime-instruments/TestDAP_runtime_instruments.py +++ b/lldb/test/API/tools/lldb-dap/exception/ubsan/TestDAP_ubsan.py @@ -1,5 +1,5 @@ """ -Test that we stop at runtime instrumentation locations. +Test that we stop at runtime instrumentation locations (ubsan). """ from lldbsuite.test.decorators import * @@ -7,7 +7,7 @@ import lldbdap_testcase -class TestDAP_runtime_instruments(lldbdap_testcase.DAPTestCaseBase): +class TestDAP_ubsan(lldbdap_testcase.DAPTestCaseBase): @skipUnlessUndefinedBehaviorSanitizer def test_ubsan(self): """ @@ -23,7 +23,7 @@ def test_ubsan(self): self.assertRegex(exceptionInfo["description"], r"Out of bounds index") self.assertEqual(exceptionInfo["exceptionId"], "runtime-instrumentation") - # FIXME: Check on non macOS platform the stop infomation location heuristic + # FIXME: Check on non macOS platform the stop information location heuristic # may be wrong. enable when we have updated Ubsan stopInfo heuristic. if self.platformIsDarwin(): self.assertIn("main.c", exceptionInfo["details"]["stackTrace"]) diff --git a/lldb/test/API/tools/lldb-dap/exception/ubsan/categories b/lldb/test/API/tools/lldb-dap/exception/ubsan/categories new file mode 100644 index 0000000000000..c756cb1241945 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/exception/ubsan/categories @@ -0,0 +1 @@ +instrumentation-runtime diff --git a/lldb/test/API/tools/lldb-dap/exception/runtime-instruments/main.c b/lldb/test/API/tools/lldb-dap/exception/ubsan/main.c similarity index 100% rename from lldb/test/API/tools/lldb-dap/exception/runtime-instruments/main.c rename to lldb/test/API/tools/lldb-dap/exception/ubsan/main.c diff --git a/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py b/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py index 19da25b3df165..48398e5915069 100644 --- a/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py +++ b/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_commands.py @@ -47,7 +47,7 @@ def test(self): # Get output from the console. This should contain both the # "initCommands" and the "preRunCommands". - output = self.get_console() + output = self.collect_console(pattern=postRunCommands[-1]) # Verify all "initCommands" were found in console output self.verify_commands("initCommands", output, initCommands) # Verify all "preRunCommands" were found in console output @@ -71,14 +71,14 @@ def test(self): # Get output from the console. This should contain both the # "stopCommands" that were run after the first breakpoint was hit self.continue_to_breakpoints(breakpoint_ids) - output = self.get_console() + output = self.collect_console(pattern=stopCommands[-1]) self.verify_commands("stopCommands", output, stopCommands) # Continue again and hit the second breakpoint. # Get output from the console. This should contain both the # "stopCommands" that were run after the second breakpoint was hit self.continue_to_breakpoints(breakpoint_ids) - output = self.get_console() + output = self.collect_console(pattern=stopCommands[-1]) self.verify_commands("stopCommands", output, stopCommands) # Continue until the program exits diff --git a/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py b/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py index 8f36c509b3873..81501702624be 100644 --- a/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py +++ b/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection.py @@ -16,8 +16,8 @@ def test(self): program = self.getBuildArtifact("a.out") with tempfile.NamedTemporaryFile("rt") as f: - self.launch(program, stdio=[None, f.name]) - self.continue_to_exit() + self.launch_and_configurationDone(program, stdio=[None, f.name]) + self.verify_process_exited() lines = f.readlines() self.assertIn( program, lines[0], "make sure program path is in first argument" diff --git a/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py b/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py index 5f60daf026473..0ed8a5e11bf8b 100644 --- a/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py +++ b/lldb/test/API/tools/lldb-dap/launch/TestDAP_launch_stdio_redirection_and_console.py @@ -29,10 +29,10 @@ def test(self): program = self.getBuildArtifact("a.out") with tempfile.NamedTemporaryFile("rt") as f: - self.launch( + self.launch_and_configurationDone( program, console="integratedTerminal", stdio=[None, f.name, None] ) - self.continue_to_exit() + self.verify_process_exited() lines = f.readlines() self.assertIn( program, lines[0], "make sure program path is in first argument" diff --git a/lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io.py b/lldb/test/API/tools/lldb-dap/launch/io/DAP_launch_io.py similarity index 61% rename from lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io.py rename to lldb/test/API/tools/lldb-dap/launch/io/DAP_launch_io.py index bbd84c07d1d4f..f5253f6ba7935 100644 --- a/lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io.py +++ b/lldb/test/API/tools/lldb-dap/launch/io/DAP_launch_io.py @@ -11,18 +11,9 @@ """ from abc import abstractmethod -from typing import IO import lldbdap_testcase from tempfile import NamedTemporaryFile -from lldbsuite.test.decorators import ( - skip, - skipIfAsan, - skipIfBuildType, - skipIfRemote, - skipIfWindows, -) - class DAP_launchIO(lldbdap_testcase.DAPTestCaseBase): """The class holds the implementation different ways to redirect the debuggee I/O streams @@ -46,13 +37,13 @@ def all_redirection(self, console: str, with_args: bool = False): ) as stdout, NamedTemporaryFile("rt") as stderr: stdin.write(input_text) stdin.flush() - self.launch( + self.launch_and_configurationDone( program, stdio=[stdin.name, stdout.name, stderr.name], console=console, args=program_args, ) - self.continue_to_exit() + self.verify_process_exited() all_stdout = stdout.read() all_stderr = stderr.read() @@ -82,8 +73,10 @@ def stdin_redirection(self, console: str, with_args: bool = False): with NamedTemporaryFile("w+t") as stdin: stdin.write(input_text) stdin.flush() - self.launch(program, stdio=[stdin.name], console=console, args=program_args) - self.continue_to_exit() + self.launch_and_configurationDone( + program, stdio=[stdin.name], console=console, args=program_args + ) + self.verify_process_exited() stdout_text = self._get_debuggee_stdout() stderr_text = self._get_debuggee_stderr() @@ -111,14 +104,14 @@ def stdout_redirection(self, console: str, with_env: bool = False): env = {"FROM_ENV": env_text} if with_env else {} with NamedTemporaryFile("rt") as stdout: - self.launch( + self.launch_and_configurationDone( program, stdio=[None, stdout.name], console=console, args=program_args, env=env, ) - self.continue_to_exit() + self.verify_process_exited() # check stdout stdout_text = stdout.read() @@ -172,14 +165,14 @@ def stderr_redirection(self, console: str, with_env: bool = False): env = {"FROM_ENV": env_text} if with_env else {} with NamedTemporaryFile("rt") as stderr: - self.launch( + self.launch_and_configurationDone( program, stdio=[None, None, stderr.name], console=console, args=program_args, env=env, ) - self.continue_to_exit() + self.verify_process_exited() stdout_text = self._get_debuggee_stdout() stderr_text = stderr.read() if with_env: @@ -208,152 +201,3 @@ def _get_debuggee_stderr(self) -> str: It requires subclasses to implement the specific mechanism for obtaining the stderr stream. """ raise RuntimeError(f"NotImplemented for {self}") - - -@skipIfWindows -class TestDAP_launchInternalConsole(DAP_launchIO): - console = "internalConsole" - __debuggee_stdout = None - - # all redirection - def test_all_redirection(self): - self.all_redirection(console=self.console) - - def test_all_redirection_with_args(self): - self.all_redirection(console=self.console, with_args=True) - - # stdin - def test_stdin_redirection(self): - self.stdin_redirection(console=self.console) - - def test_stdin_redirection_with_args(self): - self.stdin_redirection(console=self.console, with_args=True) - - # stdout - def test_stdout_redirection(self): - self.stdout_redirection(console=self.console) - - def test_stdout_redirection_with_env(self): - self.stdout_redirection(console=self.console, with_env=True) - - # stderr - def test_stderr_redirection(self): - self.stderr_redirection(console=self.console) - - def test_stderr_redirection_with_env(self): - self.stderr_redirection(console=self.console, with_env=True) - - def _get_debuggee_stdout(self) -> str: - # self.get_stdout is not idempotent. - if self.__debuggee_stdout is None: - self.__debuggee_stdout = self.get_stdout() - return self.__debuggee_stdout - - def _get_debuggee_stderr(self) -> str: - # NOTE: In internalConsole stderr writes to stdout. - return self._get_debuggee_stdout() - - -@skipIfRemote -@skipIfAsan -@skipIfBuildType(["debug"]) -@skipIfWindows -class TestDAP_launchIntegratedTerminal(DAP_launchIO): - console = "integratedTerminal" - - # all redirection - def test_all_redirection(self): - self.all_redirection(console=self.console) - - def test_all_redirection_with_args(self): - self.all_redirection(console=self.console, with_args=True) - - # stdin - def test_stdin_redirection(self): - self.stdin_redirection(console=self.console) - - def test_stdin_redirection_with_args(self): - self.stdin_redirection(console=self.console, with_args=True) - - # stdout - def test_stdout_redirection(self): - self.stdout_redirection(console=self.console) - - def test_stdout_redirection_with_env(self): - self.stdout_redirection(console=self.console, with_env=True) - - # stderr - def test_stderr_redirection(self): - self.stderr_redirection(console=self.console) - - def test_stderr_redirection_with_env(self): - self.stderr_redirection(console=self.console, with_env=True) - - def _get_debuggee_stdout(self) -> str: - self.assertIsNotNone( - self.dap_server.reverse_process, "Expected a debuggee process." - ) - proc_stdout: IO = self.dap_server.reverse_process.stdout - self.assertIsNotNone(proc_stdout) - return proc_stdout.read().decode() - - def _get_debuggee_stderr(self) -> str: - self.assertIsNotNone( - self.dap_server.reverse_process, "Expected a debuggee process." - ) - proc_stderr = self.dap_server.reverse_process.stderr - self.assertIsNotNone(proc_stderr) - return proc_stderr.read().decode() - - -@skip # NOTE: Currently there is no difference between internal and externalTerminal. -@skipIfRemote -@skipIfAsan -@skipIfBuildType(["debug"]) -@skipIfWindows -class TestDAP_launchExternalTerminal(DAP_launchIO): - console = "externalTerminal" - - # all redirection - def test_all_redirection(self): - self.all_redirection(console=self.console) - - def test_all_redirection_with_args(self): - self.all_redirection(console=self.console, with_args=True) - - # stdin - def test_stdin_redirection(self): - self.stdin_redirection(console=self.console) - - def test_stdin_redirection_with_args(self): - self.stdin_redirection(console=self.console, with_args=True) - - # stdout - def test_stdout_redirection(self): - self.stdout_redirection(console=self.console) - - def test_stdout_redirection_with_env(self): - self.stdout_redirection(console=self.console, with_env=True) - - # stderr - def test_stderr_redirection(self): - self.stderr_redirection(console=self.console) - - def test_stderr_redirection_with_env(self): - self.stderr_redirection(console=self.console, with_env=True) - - def _get_debuggee_stdout(self) -> str: - self.assertIsNotNone( - self.dap_server.reverse_process, "Expected a debuggee process." - ) - proc_stdout: IO = self.dap_server.reverse_process.stdout - self.assertIsNotNone(proc_stdout) - return proc_stdout.read().decode() - - def _get_debuggee_stderr(self) -> str: - self.assertIsNotNone( - self.dap_server.reverse_process, "Expected a debuggee process." - ) - proc_stderr = self.dap_server.reverse_process.stderr - self.assertIsNotNone(proc_stderr) - return proc_stderr.read().decode() diff --git a/lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_integratedTerminal.py b/lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_integratedTerminal.py new file mode 100644 index 0000000000000..6fa1360e487a6 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_integratedTerminal.py @@ -0,0 +1,65 @@ +""" +Test the redirection after launching in the integrated terminal. +""" + +from typing import IO +from lldbsuite.test.decorators import ( + skipIfAsan, + skipIfBuildType, + skipIfRemote, + skipIfWindows, +) + +from DAP_launch_io import DAP_launchIO + + +@skipIfRemote +@skipIfAsan +@skipIfBuildType(["debug"]) +@skipIfWindows +class TestDAP_launch_io_IntegratedTerminal(DAP_launchIO): + console = "integratedTerminal" + + # all redirection + def test_all_redirection(self): + self.all_redirection(console=self.console) + + def test_all_redirection_with_args(self): + self.all_redirection(console=self.console, with_args=True) + + # stdin + def test_stdin_redirection(self): + self.stdin_redirection(console=self.console) + + def test_stdin_redirection_with_args(self): + self.stdin_redirection(console=self.console, with_args=True) + + # stdout + def test_stdout_redirection(self): + self.stdout_redirection(console=self.console) + + def test_stdout_redirection_with_env(self): + self.stdout_redirection(console=self.console, with_env=True) + + # stderr + def test_stderr_redirection(self): + self.stderr_redirection(console=self.console) + + def test_stderr_redirection_with_env(self): + self.stderr_redirection(console=self.console, with_env=True) + + def _get_debuggee_stdout(self) -> str: + self.assertIsNotNone( + self.dap_server.reverse_process, "Expected a debuggee process." + ) + proc_stdout: IO = self.dap_server.reverse_process.stdout + self.assertIsNotNone(proc_stdout) + return proc_stdout.read().decode() + + def _get_debuggee_stderr(self) -> str: + self.assertIsNotNone( + self.dap_server.reverse_process, "Expected a debuggee process." + ) + proc_stderr = self.dap_server.reverse_process.stderr + self.assertIsNotNone(proc_stderr) + return proc_stderr.read().decode() diff --git a/lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_internalConsole.py b/lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_internalConsole.py new file mode 100644 index 0000000000000..d1c47eb28351f --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/launch/io/TestDAP_launch_io_internalConsole.py @@ -0,0 +1,50 @@ +""" +Test the redirection after launching in the internal console. +""" + +from lldbsuite.test.decorators import skipIfWindows +from DAP_launch_io import DAP_launchIO + + +@skipIfWindows +class TestDAP_launch_io_InternalConsole(DAP_launchIO): + console = "internalConsole" + __debuggee_stdout = None + + # all redirection + def test_all_redirection(self): + self.all_redirection(console=self.console) + + def test_all_redirection_with_args(self): + self.all_redirection(console=self.console, with_args=True) + + # stdin + def test_stdin_redirection(self): + self.stdin_redirection(console=self.console) + + def test_stdin_redirection_with_args(self): + self.stdin_redirection(console=self.console, with_args=True) + + # stdout + def test_stdout_redirection(self): + self.stdout_redirection(console=self.console) + + def test_stdout_redirection_with_env(self): + self.stdout_redirection(console=self.console, with_env=True) + + # stderr + def test_stderr_redirection(self): + self.stderr_redirection(console=self.console) + + def test_stderr_redirection_with_env(self): + self.stderr_redirection(console=self.console, with_env=True) + + def _get_debuggee_stdout(self) -> str: + # self.get_stdout is not idempotent. + if self.__debuggee_stdout is None: + self.__debuggee_stdout = self.get_stdout() + return self.__debuggee_stdout + + def _get_debuggee_stderr(self) -> str: + # NOTE: In internalConsole stderr writes to stdout. + return self._get_debuggee_stdout() diff --git a/lldb/test/API/tools/lldb-dap/runInTerminal/TestDAP_runInTerminal.py b/lldb/test/API/tools/lldb-dap/runInTerminal/TestDAP_runInTerminal.py index a996a1a310bd0..dfb4906ae6a49 100644 --- a/lldb/test/API/tools/lldb-dap/runInTerminal/TestDAP_runInTerminal.py +++ b/lldb/test/API/tools/lldb-dap/runInTerminal/TestDAP_runInTerminal.py @@ -215,3 +215,15 @@ def test_NonAttachedRunInTerminalLauncher(self): _, stderr = proc.communicate() self.assertIn("Timed out trying to get messages from the debug adapter", stderr) + + def test_client_missing_runInTerminal_feature(self): + program = self.getBuildArtifact("a.out") + self.build_and_create_debug_adapter() + response = self.launch_and_configurationDone( + program, + console="integratedTerminal", + client_features={"supportsRunInTerminalRequest": False}, + ) + self.assertFalse(response["success"], f"Expected failure got {response!r}") + error_message = response["body"]["error"]["format"] + self.assertIn("Client does not support RunInTerminal.", error_message) diff --git a/lldb/test/API/tools/lldb-dap/stopped-events/Makefile b/lldb/test/API/tools/lldb-dap/stopped-events/Makefile new file mode 100644 index 0000000000000..99998b20bcb05 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/stopped-events/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/tools/lldb-dap/stopped-events/TestDAP_stopped_events.py b/lldb/test/API/tools/lldb-dap/stopped-events/TestDAP_stopped_events.py new file mode 100644 index 0000000000000..598ae49967989 --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/stopped-events/TestDAP_stopped_events.py @@ -0,0 +1,167 @@ +""" +Test lldb-dap 'stopped' events. +""" + +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +import lldbdap_testcase + + +@skipIfWindows # This is flakey on Windows: llvm.org/pr24668, llvm.org/pr38373 +@skipIfLinux +class TestDAP_stopped_events(lldbdap_testcase.DAPTestCaseBase): + """ + Test validates different operations that produce 'stopped' events. + """ + + ANY_THREAD = {} + + def matches(self, a: dict, b: dict) -> bool: + """Returns true if 'a' is a subset of 'b', otherwise false.""" + return a | b == a + + def verify_threads(self, expected_threads): + threads_resp = self.dap_server.request_threads() + self.assertTrue(threads_resp["success"]) + threads = threads_resp["body"]["threads"] + self.assertGreaterEqual( + len(threads), + len(expected_threads), + f"thread: {threads!r}\n expected threads: {expected_threads}", + ) + + for idx, expected_thread in enumerate(expected_threads): + thread = threads[idx] + self.assertTrue( + self.matches(thread, expected_thread), + f"Invalid thread state in {threads_resp!r} for {expected_thread!r}", + ) + + @expectedFailureAll( + oslist=["freebsd"], + bugnumber="llvm.org/pr18190 thread states not properly maintained", + ) + @expectedFailureNetBSD + def test_multiple_threads_same_breakpoint(self): + """ + Test that multiple threads being stopped on the same breakpoint produces multiple 'stopped' event. + """ + program = self.getBuildArtifact("a.out") + launch_seq = self.build_and_launch(program) + self.dap_server.wait_for_event(["initialized"]) + [bp] = self.set_function_breakpoints(["my_add"]) + self.verify_configuration_done() + response = self.dap_server.receive_response(launch_seq) + self.assertTrue(response["success"]) + + events = self.dap_server.wait_for_stopped() + if len(events) == 1: + # we may not catch both events at the same time if we run with sanitizers + # enabled or on slow or heavily used computer. + events.extend(self.dap_server.wait_for_stopped()) + + self.assertEqual( + len(events), + 2, + f"Expected two 'stopped' events, seen events: {events!r}", + ) + for event in events: + body = event["body"] + self.assertEqual(body["reason"], "breakpoint") + self.assertEqual(body["text"], "breakpoint 1.1") + self.assertEqual(body["description"], "breakpoint 1.1") + self.assertEqual(body["hitBreakpointIds"], [int(bp)]) + self.assertIsNotNone(body["threadId"]) + + # We should have three threads, something along the lines of: + # + # Process 1234 stopped + # thread #1: tid = 0x01, 0x0a libsystem_pthread.dylib`pthread_mutex_lock + 12, queue = 'com.apple.main-thread' + # * thread #2: tid = 0x02, 0x0b a.out`add(a=1, b=2) at main.cpp:10:32, stop reason = breakpoint 1.1 + # thread #3: tid = 0x03, 0x0c a.out`add(a=4, b=5) at main.cpp:10:32, stop reason = breakpoint 1.1 + self.verify_threads( + [ + self.ANY_THREAD, + { + "reason": "breakpoint", + "text": "breakpoint 1.1", + "description": "breakpoint 1.1", + }, + { + "reason": "breakpoint", + "text": "breakpoint 1.1", + "description": "breakpoint 1.1", + }, + ] + ) + + self.assertEqual( + self.dap_server.threads[1]["id"], + self.dap_server.focused_tid, + "Expected thread#2 to be focused", + ) + + self.continue_to_exit() + + @expectedFailureAll( + oslist=["freebsd"], + bugnumber="llvm.org/pr18190 thread states not properly maintained", + ) + @expectedFailureNetBSD + def test_multiple_breakpoints_same_location(self): + """ + Test stopping at a location that reports multiple overlapping breakpoints. + """ + program = self.getBuildArtifact("a.out") + launch_seq = self.build_and_launch(program) + self.dap_server.wait_for_event(["initialized"]) + line_1 = line_number("main.cpp", "breakpoint") + [bp1] = self.set_source_breakpoints("main.cpp", [line_1]) + [bp2] = self.set_function_breakpoints(["my_add"]) + self.verify_configuration_done() + response = self.dap_server.receive_response(launch_seq) + self.assertTrue(response["success"]) + + events = self.dap_server.wait_for_stopped() + if len(events) == 1: + # we may not catch both events at the same time if we run with sanitizers + # enabled or on slow or heavily used computer. + events.extend(self.dap_server.wait_for_stopped()) + + self.assertEqual(len(events), 2, "Expected two stopped events") + for event in events: + body = event["body"] + self.assertEqual(body["reason"], "breakpoint") + self.assertEqual(body["text"], "breakpoint 1.1 2.1") + self.assertEqual(body["description"], "breakpoint 1.1 2.1") + self.assertEqual(body["hitBreakpointIds"], [int(bp1), int(bp2)]) + self.assertIsNotNone(body["threadId"]) + + # Should return something like: + # Process 1234 stopped + # thread #1: tid = 0x01, 0x0a libsystem_pthread.dylib`pthread_mutex_lock + 12, queue = 'com.apple.main-thread' + # * thread #2: tid = 0x02, 0x0b a.out`add(a=1, b=2) at main.cpp:10:32, stop reason = breakpoint 1.1 2.1 + # thread #3: tid = 0x03, 0x0c a.out`add(a=4, b=5) at main.cpp:10:32, stop reason = breakpoint 1.1 2.1 + self.verify_threads( + [ + self.ANY_THREAD, + { + "reason": "breakpoint", + "description": "breakpoint 1.1 2.1", + "text": "breakpoint 1.1 2.1", + }, + { + "reason": "breakpoint", + "description": "breakpoint 1.1 2.1", + "text": "breakpoint 1.1 2.1", + }, + ] + ) + + self.assertEqual( + self.dap_server.threads[1]["id"], + self.dap_server.focused_tid, + "Expected thread#2 to be focused", + ) + + self.continue_to_exit() diff --git a/lldb/test/API/tools/lldb-dap/stopped-events/main.cpp b/lldb/test/API/tools/lldb-dap/stopped-events/main.cpp new file mode 100644 index 0000000000000..023a95cd76ada --- /dev/null +++ b/lldb/test/API/tools/lldb-dap/stopped-events/main.cpp @@ -0,0 +1,32 @@ +#include "pseudo_barrier.h" +#include + +pseudo_barrier_t g_barrier; + +static int my_add(int a, int b) { // breakpoint + return a + b; +} + +static void do_test() { + // Don't let either thread do anything until they're both ready. + pseudo_barrier_init(g_barrier, 2); + + std::thread t1([] { + // Wait until both threads are running + pseudo_barrier_wait(g_barrier); + my_add(1, 2); + }); + std::thread t2([] { + // Wait until both threads are running + pseudo_barrier_wait(g_barrier); + my_add(4, 5); + }); + + t1.join(); + t2.join(); +} + +int main(int argc, char const *argv[]) { + do_test(); + return 0; +} diff --git a/lldb/test/API/tools/lldb-dap/threads/TestDAP_threads.py b/lldb/test/API/tools/lldb-dap/threads/TestDAP_threads.py index acd6108853787..be6dd84ec4d44 100644 --- a/lldb/test/API/tools/lldb-dap/threads/TestDAP_threads.py +++ b/lldb/test/API/tools/lldb-dap/threads/TestDAP_threads.py @@ -39,8 +39,7 @@ def test_correct_thread(self): "breakpoint %s." % breakpoint_ids[0] ) ) - self.assertFalse(stopped_event[0]["body"]["preserveFocusHint"]) - self.assertTrue(stopped_event[0]["body"]["threadCausedFocus"]) + self.assertNotIn("preserveFocusHint", stopped_event[0]["body"]) # All threads should be named Thread {index} threads = self.dap_server.get_threads() self.assertTrue(all(len(t["name"]) > 0 for t in threads)) diff --git a/lldb/test/Shell/DAP/TestSTDINConsole.test b/lldb/test/Shell/DAP/TestSTDINConsole.test index ba2357d1b0fe4..0d6d25400260e 100644 --- a/lldb/test/Shell/DAP/TestSTDINConsole.test +++ b/lldb/test/Shell/DAP/TestSTDINConsole.test @@ -1,5 +1,5 @@ # REQUIRES: python, system-windows -# RUN: %python %s %lldb-dap > %t.out 2>&1 +# RUN: %python %s lldb-dap > %t.out 2>&1 # RUN: FileCheck %s --check-prefix=ERROR --allow-empty < %t.out # ERROR-NOT: DAP session error: diff --git a/lldb/test/Shell/ObjectFile/ELF/stt-tls-symbol.yaml b/lldb/test/Shell/ObjectFile/ELF/stt-tls-symbol.yaml new file mode 100644 index 0000000000000..b7374461b0ab5 --- /dev/null +++ b/lldb/test/Shell/ObjectFile/ELF/stt-tls-symbol.yaml @@ -0,0 +1,28 @@ +# Test that STT_TLS symbols are recognized and treated as data symbols. +# +# RUN: yaml2obj %s -o %t +# RUN: %lldb %t -o "image dump symtab" -b | FileCheck %s + +# CHECK: Index UserID DSX Type File Address/Value Load Address Size Flags Name +# CHECK: [ 0] 1 Data 0x0000000000001000 0x0000000000000004 {{0x[0-9a-f]+}} tls_var + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .tdata + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_WRITE, SHF_TLS ] + Address: 0x1000 + AddressAlign: 0x4 + Size: 0x4 +Symbols: + - Name: tls_var + Type: STT_TLS + Section: .tdata + Value: 0x1000 + Size: 0x4 +... diff --git a/lldb/tools/driver/Driver.cpp b/lldb/tools/driver/Driver.cpp index 48107717abd31..72ed9d02930d4 100644 --- a/lldb/tools/driver/Driver.cpp +++ b/lldb/tools/driver/Driver.cpp @@ -634,7 +634,7 @@ int Driver::MainLoop() { // Check if we have any data in the commands stream, and if so, save it to a // temp file // so we can then run the command interpreter using the file contents. - bool go_interactive = true; + bool go_interactive = !m_option_data.m_batch; if ((commands_stream.GetData() != nullptr) && (commands_stream.GetSize() != 0u)) { SBError error = m_debugger.SetInputString(commands_stream.GetData()); @@ -672,6 +672,7 @@ int Driver::MainLoop() { if (m_option_data.m_batch && results.GetResult() == lldb::eCommandInterpreterResultInferiorCrash && !m_option_data.m_after_crash_commands.empty()) { + go_interactive = true; SBStream crash_commands_stream; WriteCommandsForSourcing(eCommandPlacementAfterCrash, crash_commands_stream); diff --git a/lldb/tools/driver/Options.td b/lldb/tools/driver/Options.td index 311e2602cc41f..e8f1bd993176e 100644 --- a/lldb/tools/driver/Options.td +++ b/lldb/tools/driver/Options.td @@ -240,9 +240,4 @@ def arch : Separate<["--", "-"], "arch">, "starting and running the program.">; def : Separate<["-"], "a">, Alias, HelpText<"Alias for --arch">; -def debug : F<"debug">, - HelpText<"Tells the debugger to print out extra information for " - "debugging itself.">; -def : Flag<["-"], "d">, Alias, HelpText<"Alias for --debug">; - def REM : R<["--"], "">; diff --git a/lldb/tools/lldb-dap/DAP.cpp b/lldb/tools/lldb-dap/DAP.cpp index 5ef384706aab0..b76b05c5d1459 100644 --- a/lldb/tools/lldb-dap/DAP.cpp +++ b/lldb/tools/lldb-dap/DAP.cpp @@ -208,6 +208,11 @@ void DAP::PopulateExceptionBreakpoints() { } } +bool DAP::ProcessIsNotStopped() { + const lldb::StateType process_state = target.GetProcess().GetState(); + return !lldb::SBDebugger::StateIsStoppedState(process_state); +} + ExceptionBreakpoint *DAP::GetExceptionBreakpoint(llvm::StringRef filter) { for (auto &bp : exception_breakpoints) { if (bp.GetFilter() == filter) @@ -1046,9 +1051,8 @@ void DAP::TransportHandler() { m_queue_cv.notify_all(); }); - auto handle = transport.RegisterMessageHandler(m_loop, *this); - if (!handle) { - DAP_LOG_ERROR(log, handle.takeError(), + if (llvm::Error err = transport.RegisterMessageHandler(*this)) { + DAP_LOG_ERROR(log, std::move(err), "registering message handler failed: {0}"); std::lock_guard guard(m_queue_mutex); m_error_occurred = true; diff --git a/lldb/tools/lldb-dap/DAP.h b/lldb/tools/lldb-dap/DAP.h index 8d56a226dbb28..34d6a29b3c110 100644 --- a/lldb/tools/lldb-dap/DAP.h +++ b/lldb/tools/lldb-dap/DAP.h @@ -150,10 +150,9 @@ struct DAP final : public DAPTransport::MessageHandler { /// This is used to allow request_evaluate to handle empty expressions /// (ie the user pressed 'return' and expects the previous expression to - /// repeat). If the previous expression was a command, this string will be - /// empty; if the previous expression was a variable expression, this string - /// will contain that expression. - std::string last_nonempty_var_expression; + /// repeat). If the previous expression was a command, it will be empty. + /// Else it will contain the last valid variable expression. + std::string last_valid_variable_expression; /// The set of features supported by the connected client. llvm::DenseSet clientFeatures; @@ -256,6 +255,8 @@ struct DAP final : public DAPTransport::MessageHandler { void PopulateExceptionBreakpoints(); + bool ProcessIsNotStopped(); + /// Attempt to determine if an expression is a variable expression or /// lldb command using a heuristic based on the first term of the /// expression. diff --git a/lldb/tools/lldb-dap/EventHelper.cpp b/lldb/tools/lldb-dap/EventHelper.cpp index cc34b30f4244c..dbf4823408b11 100644 --- a/lldb/tools/lldb-dap/EventHelper.cpp +++ b/lldb/tools/lldb-dap/EventHelper.cpp @@ -20,14 +20,20 @@ #include "Protocol/ProtocolRequests.h" #include "Protocol/ProtocolTypes.h" #include "ProtocolUtils.h" +#include "SBAPIExtras.h" #include "lldb/API/SBEvent.h" #include "lldb/API/SBFileSpec.h" #include "lldb/API/SBListener.h" #include "lldb/API/SBPlatform.h" #include "lldb/API/SBStream.h" +#include "lldb/API/SBThread.h" +#include "lldb/lldb-defines.h" +#include "lldb/lldb-types.h" #include "llvm/Support/Error.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormatVariadic.h" #include "llvm/Support/Threading.h" +#include "llvm/Support/raw_ostream.h" #include #include @@ -172,8 +178,79 @@ void SendProcessEvent(DAP &dap, LaunchMethod launch_method) { dap.SendJSON(llvm::json::Value(std::move(event))); } -// Send a thread stopped event for all threads as long as the process -// is stopped. +static void SendStoppedEvent(DAP &dap, lldb::SBThread &thread, bool on_entry, + bool all_threads_stopped, bool preserve_focus) { + protocol::StoppedEventBody body; + if (on_entry) { + body.reason = protocol::eStoppedReasonEntry; + } else { + switch (thread.GetStopReason()) { + case lldb::eStopReasonTrace: + case lldb::eStopReasonPlanComplete: + case lldb::eStopReasonProcessorTrace: + case lldb::eStopReasonHistoryBoundary: + body.reason = protocol::eStoppedReasonStep; + break; + case lldb::eStopReasonBreakpoint: { + ExceptionBreakpoint *exc_bp = dap.GetExceptionBPFromStopReason(thread); + if (exc_bp) { + body.reason = protocol::eStoppedReasonException; + body.text = exc_bp->GetLabel(); + } else { + InstructionBreakpoint *inst_bp = + dap.GetInstructionBPFromStopReason(thread); + body.reason = inst_bp ? protocol::eStoppedReasonInstructionBreakpoint + : protocol::eStoppedReasonBreakpoint; + + llvm::raw_string_ostream OS(body.text); + OS << "breakpoint"; + for (size_t idx = 0; idx < thread.GetStopReasonDataCount(); idx += 2) { + lldb::break_id_t bp_id = thread.GetStopReasonDataAtIndex(idx); + lldb::break_id_t bp_loc_id = thread.GetStopReasonDataAtIndex(idx + 1); + body.hitBreakpointIds.push_back(bp_id); + OS << " " << bp_id << "." << bp_loc_id; + } + } + } break; + case lldb::eStopReasonWatchpoint: { + body.reason = protocol::eStoppedReasonDataBreakpoint; + lldb::break_id_t bp_id = thread.GetStopReasonDataAtIndex(0); + body.hitBreakpointIds.push_back(bp_id); + body.text = llvm::formatv("data breakpoint {0}", bp_id).str(); + } break; + case lldb::eStopReasonSignal: + case lldb::eStopReasonException: + case lldb::eStopReasonInstrumentation: + body.reason = protocol::eStoppedReasonException; + break; + case lldb::eStopReasonExec: + case lldb::eStopReasonFork: + case lldb::eStopReasonVFork: + case lldb::eStopReasonVForkDone: + body.reason = protocol::eStoppedReasonEntry; + break; + case lldb::eStopReasonInterrupt: + body.reason = protocol::eStoppedReasonPause; + break; + case lldb::eStopReasonThreadExiting: + case lldb::eStopReasonInvalid: + case lldb::eStopReasonNone: + return; + } + } + lldb::tid_t tid = thread.GetThreadID(); + lldb::SBStream description; + thread.GetStopDescription(description); + body.description = {description.GetData(), description.GetSize()}; + body.threadId = tid; + body.allThreadsStopped = all_threads_stopped; + body.preserveFocusHint = preserve_focus; + + dap.Send(protocol::Event{"stopped", std::move(body)}); +} + +// Send a thread stopped event for the first stopped thread as the process is +// stopped. llvm::Error SendThreadStoppedEvent(DAP &dap, bool on_entry) { lldb::SBMutex lock = dap.GetAPIMutex(); std::lock_guard guard(lock); @@ -188,63 +265,38 @@ llvm::Error SendThreadStoppedEvent(DAP &dap, bool on_entry) { llvm::DenseSet old_thread_ids; old_thread_ids.swap(dap.thread_ids); - uint32_t stop_id = on_entry ? 0 : process.GetStopID(); - const uint32_t num_threads = process.GetNumThreads(); - - // First make a pass through the threads to see if the focused thread - // has a stop reason. In case the focus thread doesn't have a stop - // reason, remember the first thread that has a stop reason so we can - // set it as the focus thread if below if needed. - lldb::tid_t first_tid_with_reason = LLDB_INVALID_THREAD_ID; - uint32_t num_threads_with_reason = 0; - bool focus_thread_exists = false; - for (uint32_t thread_idx = 0; thread_idx < num_threads; ++thread_idx) { - lldb::SBThread thread = process.GetThreadAtIndex(thread_idx); - const lldb::tid_t tid = thread.GetThreadID(); - const bool has_reason = ThreadHasStopReason(thread); - // If the focus thread doesn't have a stop reason, clear the thread ID - if (tid == dap.focus_tid) { - focus_thread_exists = true; - if (!has_reason) - dap.focus_tid = LLDB_INVALID_THREAD_ID; - } - if (has_reason) { - ++num_threads_with_reason; - if (first_tid_with_reason == LLDB_INVALID_THREAD_ID) - first_tid_with_reason = tid; - } - } - // We will have cleared dap.focus_tid if the focus thread doesn't have - // a stop reason, so if it was cleared, or wasn't set, or doesn't exist, - // then set the focus thread to the first thread with a stop reason. - if (!focus_thread_exists || dap.focus_tid == LLDB_INVALID_THREAD_ID) - dap.focus_tid = first_tid_with_reason; - - // If no threads stopped with a reason, then report the first one so - // we at least let the UI know we stopped. - if (num_threads_with_reason == 0) { - lldb::SBThread thread = process.GetThreadAtIndex(0); - dap.focus_tid = thread.GetThreadID(); - dap.SendJSON(CreateThreadStopped(dap, thread, stop_id)); - } else { - for (uint32_t thread_idx = 0; thread_idx < num_threads; ++thread_idx) { - lldb::SBThread thread = process.GetThreadAtIndex(thread_idx); - dap.thread_ids.insert(thread.GetThreadID()); - if (ThreadHasStopReason(thread)) { - dap.SendJSON(CreateThreadStopped(dap, thread, stop_id)); - } - } + lldb::tid_t focused_tid = LLDB_INVALID_THREAD_ID; + for (auto thread : process) { + // Collect all known thread ids for sending thread events. + dap.thread_ids.insert(thread.GetThreadID()); + + if (!ThreadHasStopReason(thread)) + continue; + + // When we stop, report allThreadsStopped for the *first* stopped thread to + // ensure the list of stopped threads is up to date. + bool first_stop = focused_tid == LLDB_INVALID_THREAD_ID; + SendStoppedEvent(dap, thread, on_entry, /*all_threads_stopped=*/first_stop, + /*preserve_focus=*/!first_stop); + + // Default focus to the first stopped thread. + if (focused_tid == LLDB_INVALID_THREAD_ID) + focused_tid = thread.GetThreadID(); } - for (const auto &tid : old_thread_ids) { - auto end = dap.thread_ids.end(); - auto pos = dap.thread_ids.find(tid); - if (pos == end) + if (focused_tid == LLDB_INVALID_THREAD_ID) + return make_error("no stopped threads"); + + // Update focused thread. + dap.focus_tid = focused_tid; + + for (const auto &tid : old_thread_ids) + if (!dap.thread_ids.contains(tid)) SendThreadExitedEvent(dap, tid); - } dap.RunStopCommands(); + return Error::success(); } diff --git a/lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp index 41e0551373aa7..4b6f5eff7c842 100644 --- a/lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp @@ -84,7 +84,7 @@ Error AttachRequestHandler::Run(const AttachRequestArguments &args) const { args.gdbRemotePort == LLDB_DAP_INVALID_PORT) && args.waitFor) dap.SendOutput(OutputType::Console, - llvm::formatv("Waiting to attach to \"{0}\"...", + llvm::formatv("Waiting to attach to \"{0}\"...\n", dap.target.GetExecutable().GetFilename()) .str()); diff --git a/lldb/tools/lldb-dap/Handler/DisassembleRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/DisassembleRequestHandler.cpp index 6d2eb74a9634c..8387f9ab5c387 100644 --- a/lldb/tools/lldb-dap/Handler/DisassembleRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/DisassembleRequestHandler.cpp @@ -156,22 +156,6 @@ static DisassembledInstruction ConvertSBInstructionToDisassembledInstruction( const auto column = line_entry.GetColumn(); if (column != 0 && column != LLDB_INVALID_COLUMN_NUMBER) disassembled_inst.column = column; - - lldb::SBAddress end_addr = line_entry.GetEndAddress(); - auto end_line_entry = GetLineEntryForAddress(target, end_addr); - if (end_line_entry.IsValid() && - end_line_entry.GetFileSpec() == line_entry.GetFileSpec()) { - const auto end_line = end_line_entry.GetLine(); - if (end_line != 0 && end_line != LLDB_INVALID_LINE_NUMBER && - end_line != line) { - disassembled_inst.endLine = end_line; - - const auto end_column = end_line_entry.GetColumn(); - if (end_column != 0 && end_column != LLDB_INVALID_COLUMN_NUMBER && - end_column != column) - disassembled_inst.endColumn = end_column - 1; - } - } } return disassembled_inst; diff --git a/lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp index ec26bb66e8aec..82a011b8088df 100644 --- a/lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/EvaluateRequestHandler.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "DAP.h" +#include "DAPError.h" #include "EventHelper.h" #include "JSONUtils.h" #include "LLDBUtils.h" @@ -23,24 +24,66 @@ using namespace lldb_dap::protocol; namespace lldb_dap { +static bool RunExpressionAsLLDBCommand(DAP &dap, lldb::SBFrame &frame, + std::string &expression, + EvaluateContext context) { + if (context != eEvaluateContextRepl && context != eEvaluateContextUnknown) + return false; + + // Since we don't know this context do not try to repeat the last command; + if (context == eEvaluateContextUnknown && expression.empty()) + return false; + + const bool repeat_last_command = + expression.empty() && dap.last_valid_variable_expression.empty(); + if (repeat_last_command) + return true; + + const ReplMode repl_mode = dap.DetectReplMode(frame, expression, false); + return repl_mode == ReplMode::Command; +} + +static lldb::SBValue EvaluateVariableExpression(lldb::SBTarget &target, + lldb::SBFrame &frame, + const std::string &expression, + bool run_as_expression) { + const char *expression_cstr = expression.c_str(); + + lldb::SBValue value; + if (frame) { + // Check if it is a variable or an expression path for a variable. i.e. + // 'foo->bar' finds the 'bar' variable. It is more reliable than the + // expression parser in many cases and it is faster. + value = frame.GetValueForVariablePath(expression_cstr, + lldb::eDynamicDontRunTarget); + if (value || !run_as_expression) + return value; + + return frame.EvaluateExpression(expression_cstr); + } + + if (run_as_expression) + value = target.EvaluateExpression(expression_cstr); + + return value; +} + /// Evaluates the given expression in the context of a stack frame. /// /// The expression has access to any variables and arguments that are in scope. Expected EvaluateRequestHandler::Run(const EvaluateArguments &arguments) const { + EvaluateResponseBody body; lldb::SBFrame frame = dap.GetLLDBFrame(arguments.frameId); - std::string expression = arguments.expression; - bool repeat_last_command = - expression.empty() && dap.last_nonempty_var_expression.empty(); - - if (arguments.context == protocol::eEvaluateContextRepl && - (repeat_last_command || - (!expression.empty() && - dap.DetectReplMode(frame, expression, false) == ReplMode::Command))) { + std::string expression = llvm::StringRef(arguments.expression).trim().str(); + const EvaluateContext evaluate_context = arguments.context; + const bool is_repl_context = evaluate_context == eEvaluateContextRepl; + + if (RunExpressionAsLLDBCommand(dap, frame, expression, evaluate_context)) { // Since the current expression is not for a variable, clear the - // last_nonempty_var_expression field. - dap.last_nonempty_var_expression.clear(); + // last_valid_variable_expression field. + dap.last_valid_variable_expression.clear(); // If we're evaluating a command relative to the current frame, set the // focus_tid to the current frame for any thread related events. if (frame.IsValid()) { @@ -54,47 +97,43 @@ EvaluateRequestHandler::Run(const EvaluateArguments &arguments) const { return body; } - if (arguments.context == eEvaluateContextRepl) { - // If the expression is empty and the last expression was for a - // variable, set the expression to the previous expression (repeat the - // evaluation); otherwise save the current non-empty expression for the - // next (possibly empty) variable expression. - if (expression.empty()) - expression = dap.last_nonempty_var_expression; - else - dap.last_nonempty_var_expression = expression; - } + if (dap.ProcessIsNotStopped()) + return llvm::make_error( + "Cannot evaluate expressions while the process is running. Pause " + "the process and try again.", + /**error_code=*/llvm::inconvertibleErrorCode(), + /**show_user=*/false); - // Always try to get the answer from the local variables if possible. If - // this fails, then if the context is not "hover", actually evaluate an - // expression using the expression parser. - // - // "frame variable" is more reliable than the expression parser in - // many cases and it is faster. - lldb::SBValue value = frame.GetValueForVariablePath( - expression.data(), lldb::eDynamicDontRunTarget); - - // Freeze dry the value in case users expand it later in the debug console - if (value.GetError().Success() && arguments.context == eEvaluateContextRepl) - value = value.Persist(); + // If the user expression is empty, evaluate the last valid variable + // expression. + if (expression.empty() && is_repl_context) + expression = dap.last_valid_variable_expression; - if (value.GetError().Fail() && arguments.context != eEvaluateContextHover) - value = frame.EvaluateExpression(expression.data()); + const bool run_as_expression = evaluate_context != eEvaluateContextHover; + lldb::SBValue value = EvaluateVariableExpression( + dap.target, frame, expression, run_as_expression); if (value.GetError().Fail()) return ToError(value.GetError(), /*show_user=*/false); - const bool hex = arguments.format ? arguments.format->hex : false; + if (is_repl_context) { + // save the new variable expression + dap.last_valid_variable_expression = std::move(expression); + // Freeze dry the value in case users expand it later in the debug console + value = value.Persist(); + } + + const bool hex = arguments.format ? arguments.format->hex : false; VariableDescription desc(value, dap.configuration.enableAutoVariableSummaries, hex); - body.result = desc.GetResult(arguments.context); + body.result = desc.GetResult(evaluate_context); body.type = desc.display_type_name; if (value.MightHaveChildren() || ValuePointsToCode(value)) - body.variablesReference = dap.variables.InsertVariable( - value, /*is_permanent=*/arguments.context == eEvaluateContextRepl); + body.variablesReference = + dap.variables.InsertVariable(value, /*is_permanent=*/is_repl_context); if (lldb::addr_t addr = value.GetLoadAddress(); addr != LLDB_INVALID_ADDRESS) body.memoryReference = EncodeMemoryReference(addr); diff --git a/lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp index 3a96533c9cd12..74ab9a2837034 100644 --- a/lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/ExceptionInfoRequestHandler.cpp @@ -19,6 +19,7 @@ #include "lldb/API/SBValue.h" #include "lldb/lldb-defines.h" #include "lldb/lldb-enumerations.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/BranchProbability.h" #include "llvm/Support/Error.h" @@ -49,10 +50,20 @@ struct MainThreadCheckerReport { std::string selector; }; -// FIXME: Support TSan, ASan, BoundsSafety formatting. +// See `ReportRetriever::RetrieveReportData`. +struct ASanReport { + std::string description; + lldb::addr_t address = LLDB_INVALID_ADDRESS; + lldb::addr_t program_counter = LLDB_INVALID_ADDRESS; + lldb::addr_t base_pointer = LLDB_INVALID_ADDRESS; + lldb::addr_t stack_pointer = LLDB_INVALID_ADDRESS; + std::string stop_type; +}; + +// FIXME: Support TSan, BoundsSafety formatting. using RuntimeInstrumentReport = - std::variant; + std::variant; static bool fromJSON(const json::Value ¶ms, UBSanReport &report, json::Path path) { @@ -73,6 +84,17 @@ static bool fromJSON(const json::Value ¶ms, MainThreadCheckerReport &report, O.mapOptional("selector", report.selector); } +static bool fromJSON(const json::Value ¶ms, ASanReport &report, + json::Path path) { + json::ObjectMapper O(params, path); + return O.mapOptional("description", report.description) && + O.mapOptional("address", report.address) && + O.mapOptional("pc", report.program_counter) && + O.mapOptional("bp", report.base_pointer) && + O.mapOptional("sp", report.stack_pointer) && + O.mapOptional("stop_type", report.stop_type); +} + static bool fromJSON(const json::Value ¶ms, RuntimeInstrumentReport &report, json::Path path) { json::ObjectMapper O(params, path); @@ -94,6 +116,13 @@ static bool fromJSON(const json::Value ¶ms, RuntimeInstrumentReport &report, report = std::move(inner_report); return success; } + if (instrumentation_class == "AddressSanitizer") { + ASanReport inner_report; + bool success = fromJSON(params, inner_report, path); + if (success) + report = std::move(inner_report); + return success; + } // FIXME: Support additional runtime instruments with specific formatters. return false; @@ -134,6 +163,25 @@ static raw_ostream &operator<<(raw_ostream &OS, return OS; } +static raw_ostream &operator<<(raw_ostream &OS, ASanReport &report) { + if (!report.stop_type.empty()) + OS << report.stop_type << ": "; + if (!report.description.empty()) + OS << report.description << "\n"; + + if (report.address != LLDB_INVALID_ADDRESS) + OS << "Address: 0x" << llvm::utohexstr(report.address) << "\n"; + if (report.program_counter != LLDB_INVALID_ADDRESS) + OS << "Program counter: 0x" << llvm::utohexstr(report.program_counter) + << "\n"; + if (report.base_pointer != LLDB_INVALID_ADDRESS) + OS << "Base pointer: 0x" << llvm::utohexstr(report.base_pointer) << "\n"; + if (report.stack_pointer != LLDB_INVALID_ADDRESS) + OS << "Stack pointer: 0x" << llvm::utohexstr(report.stack_pointer) << "\n"; + + return OS; +} + static raw_ostream &operator<<(raw_ostream &OS, RuntimeInstrumentReport &report) { std::visit([&](auto &r) { OS << r; }, report); diff --git a/lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp index 2b48350dfba1b..59df5498943f2 100644 --- a/lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/NextRequestHandler.cpp @@ -27,13 +27,13 @@ namespace lldb_dap { /// adapter first sends the response and then a `stopped` event (with reason /// `step`) after the step has completed. Error NextRequestHandler::Run(const NextArguments &args) const { + if (dap.ProcessIsNotStopped()) + return make_error(); + lldb::SBThread thread = dap.GetLLDBThread(args.threadId); if (!thread.IsValid()) return make_error("invalid thread"); - if (!SBDebugger::StateIsStoppedState(dap.target.GetProcess().GetState())) - return make_error(); - // Remember the thread ID that caused the resume so we can set the // "threadCausedFocus" boolean value in the "stopped" events. dap.focus_tid = thread.GetThreadID(); diff --git a/lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp index 374dc4516aa2d..32752f51284ec 100644 --- a/lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/ReadMemoryRequestHandler.cpp @@ -21,8 +21,7 @@ llvm::Expected ReadMemoryRequestHandler::Run(const protocol::ReadMemoryArguments &args) const { const lldb::addr_t raw_address = args.memoryReference + args.offset; - lldb::SBProcess process = dap.target.GetProcess(); - if (!lldb::SBDebugger::StateIsStoppedState(process.GetState())) + if (dap.ProcessIsNotStopped()) return llvm::make_error(); const uint64_t count_read = std::max(args.count, 1); diff --git a/lldb/tools/lldb-dap/Handler/RequestHandler.cpp b/lldb/tools/lldb-dap/Handler/RequestHandler.cpp index 5cb0055f034da..47ae9a7195a7d 100644 --- a/lldb/tools/lldb-dap/Handler/RequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/RequestHandler.cpp @@ -234,6 +234,10 @@ llvm::Error BaseRequestHandler::LaunchProcess( ScopeSyncMode scope_sync_mode(dap.debugger); if (arguments.console != protocol::eConsoleInternal) { + if (!dap.clientFeatures.contains(eClientFeatureRunInTerminalRequest)) + return llvm::make_error( + R"(Client does not support RunInTerminal. Please set '"console": "integratedConsole"' in your launch configuration)"); + if (llvm::Error err = RunInTerminal(dap, arguments)) return err; } else if (launchCommands.empty()) { diff --git a/lldb/tools/lldb-dap/Handler/RequestHandler.h b/lldb/tools/lldb-dap/Handler/RequestHandler.h index f435257d4dcce..9feb636fd5c28 100644 --- a/lldb/tools/lldb-dap/Handler/RequestHandler.h +++ b/lldb/tools/lldb-dap/Handler/RequestHandler.h @@ -11,6 +11,7 @@ #include "DAP.h" #include "DAPError.h" +#include "JSONUtils.h" #include "Protocol/ProtocolBase.h" #include "Protocol/ProtocolRequests.h" #include "Protocol/ProtocolTypes.h" @@ -197,8 +198,7 @@ class DelayedResponseRequestHandler : public BaseRequestHandler { // The 'configurationDone' request is not sent until after 'initialized' // triggers the breakpoints being sent and 'configurationDone' is the last // message in the chain. - protocol::Event initialized{"initialized"}; - dap.Send(initialized); + dap.SendJSON(CreateInitializedEventObject(dap.target)); }; protected: diff --git a/lldb/tools/lldb-dap/Handler/StackTraceRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/StackTraceRequestHandler.cpp index 7064d356a6479..6e6f9b0e5b285 100644 --- a/lldb/tools/lldb-dap/Handler/StackTraceRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/StackTraceRequestHandler.cpp @@ -14,6 +14,7 @@ #include "ProtocolUtils.h" #include "RequestHandler.h" #include "lldb/API/SBStream.h" +#include "lldb/lldb-enumerations.h" using namespace lldb_dap; using namespace lldb_dap::protocol; @@ -189,6 +190,9 @@ static bool FillStackFrames(DAP &dap, lldb::SBThread &thread, llvm::Expected StackTraceRequestHandler::Run(const protocol::StackTraceArguments &args) const { + if (dap.ProcessIsNotStopped()) + return llvm::make_error(); + lldb::SBThread thread = dap.GetLLDBThread(args.threadId); if (!thread.IsValid()) return llvm::make_error("invalid thread"); diff --git a/lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp index 6742c791a5486..ba4457e62731c 100644 --- a/lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/StepInRequestHandler.cpp @@ -32,6 +32,9 @@ namespace lldb_dap { // possible targets for a given source line can be retrieved via the // `stepInTargets` request. Error StepInRequestHandler::Run(const StepInArguments &args) const { + if (dap.ProcessIsNotStopped()) + return make_error(); + SBThread thread = dap.GetLLDBThread(args.threadId); if (!thread.IsValid()) return make_error("invalid thread"); @@ -40,9 +43,6 @@ Error StepInRequestHandler::Run(const StepInArguments &args) const { // "threadCausedFocus" boolean value in the "stopped" events. dap.focus_tid = thread.GetThreadID(); - if (!SBDebugger::StateIsStoppedState(dap.target.GetProcess().GetState())) - return make_error(); - lldb::SBError error; if (args.granularity == eSteppingGranularityInstruction) { thread.StepInstruction(/*step_over=*/false, error); diff --git a/lldb/tools/lldb-dap/Handler/StepInTargetsRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/StepInTargetsRequestHandler.cpp index 9295b6ceae36d..2b41626bb74fb 100644 --- a/lldb/tools/lldb-dap/Handler/StepInTargetsRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/StepInTargetsRequestHandler.cpp @@ -7,10 +7,12 @@ //===----------------------------------------------------------------------===// #include "DAP.h" +#include "DAPError.h" #include "Protocol/ProtocolRequests.h" #include "RequestHandler.h" #include "lldb/API/SBInstruction.h" #include "lldb/lldb-defines.h" +#include "llvm/Support/Error.h" using namespace lldb_dap::protocol; namespace lldb_dap { @@ -22,6 +24,9 @@ namespace lldb_dap { // `supportsStepInTargetsRequest` is true. llvm::Expected StepInTargetsRequestHandler::Run(const StepInTargetsArguments &args) const { + if (dap.ProcessIsNotStopped()) + return llvm::make_error(); + dap.step_in_targets.clear(); const lldb::SBFrame frame = dap.GetLLDBFrame(args.frameId); if (!frame.IsValid()) diff --git a/lldb/tools/lldb-dap/Handler/StepOutRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/StepOutRequestHandler.cpp index e896e03720b6b..61bde76e08a3d 100644 --- a/lldb/tools/lldb-dap/Handler/StepOutRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/StepOutRequestHandler.cpp @@ -14,6 +14,7 @@ #include "llvm/Support/Error.h" using namespace llvm; +using namespace lldb; using namespace lldb_dap::protocol; namespace lldb_dap { @@ -29,14 +30,13 @@ namespace lldb_dap { /// The debug adapter first sends the response and then a `stopped` event (with /// reason `step`) after the step has completed." Error StepOutRequestHandler::Run(const StepOutArguments &arguments) const { + if (dap.ProcessIsNotStopped()) + return make_error(); + lldb::SBThread thread = dap.GetLLDBThread(arguments.threadId); if (!thread.IsValid()) return make_error("invalid thread"); - if (!lldb::SBDebugger::StateIsStoppedState( - dap.target.GetProcess().GetState())) - return make_error(); - // Remember the thread ID that caused the resume so we can set the // "threadCausedFocus" boolean value in the "stopped" events. dap.focus_tid = thread.GetThreadID(); diff --git a/lldb/tools/lldb-dap/Handler/WriteMemoryRequestHandler.cpp b/lldb/tools/lldb-dap/Handler/WriteMemoryRequestHandler.cpp index 3e34e488d1158..17406ce1426e6 100644 --- a/lldb/tools/lldb-dap/Handler/WriteMemoryRequestHandler.cpp +++ b/lldb/tools/lldb-dap/Handler/WriteMemoryRequestHandler.cpp @@ -27,8 +27,7 @@ llvm::Expected WriteMemoryRequestHandler::Run(const WriteMemoryArguments &args) const { const lldb::addr_t address = args.memoryReference + args.offset; - lldb::SBProcess process = dap.target.GetProcess(); - if (!lldb::SBDebugger::StateIsStoppedState(process.GetState())) + if (dap.ProcessIsNotStopped()) return llvm::make_error(); if (args.data.empty()) { diff --git a/lldb/tools/lldb-dap/JSONUtils.cpp b/lldb/tools/lldb-dap/JSONUtils.cpp index 9c32e3fac64ae..5bcc2f9c71c2d 100644 --- a/lldb/tools/lldb-dap/JSONUtils.cpp +++ b/lldb/tools/lldb-dap/JSONUtils.cpp @@ -345,163 +345,6 @@ llvm::json::Object CreateEventObject(const llvm::StringRef event_name) { return event; } -// "StoppedEvent": { -// "allOf": [ { "$ref": "#/definitions/Event" }, { -// "type": "object", -// "description": "Event message for 'stopped' event type. The event -// indicates that the execution of the debuggee has stopped -// due to some condition. This can be caused by a break -// point previously set, a stepping action has completed, -// by executing a debugger statement etc.", -// "properties": { -// "event": { -// "type": "string", -// "enum": [ "stopped" ] -// }, -// "body": { -// "type": "object", -// "properties": { -// "reason": { -// "type": "string", -// "description": "The reason for the event. For backward -// compatibility this string is shown in the UI if -// the 'description' attribute is missing (but it -// must not be translated).", -// "_enum": [ "step", "breakpoint", "exception", "pause", "entry" ] -// }, -// "description": { -// "type": "string", -// "description": "The full reason for the event, e.g. 'Paused -// on exception'. This string is shown in the UI -// as is." -// }, -// "threadId": { -// "type": "integer", -// "description": "The thread which was stopped." -// }, -// "text": { -// "type": "string", -// "description": "Additional information. E.g. if reason is -// 'exception', text contains the exception name. -// This string is shown in the UI." -// }, -// "allThreadsStopped": { -// "type": "boolean", -// "description": "If allThreadsStopped is true, a debug adapter -// can announce that all threads have stopped. -// The client should use this information to -// enable that all threads can be expanded to -// access their stacktraces. If the attribute -// is missing or false, only the thread with the -// given threadId can be expanded." -// } -// }, -// "required": [ "reason" ] -// } -// }, -// "required": [ "event", "body" ] -// }] -// } -llvm::json::Value CreateThreadStopped(DAP &dap, lldb::SBThread &thread, - uint32_t stop_id) { - llvm::json::Object event(CreateEventObject("stopped")); - llvm::json::Object body; - switch (thread.GetStopReason()) { - case lldb::eStopReasonTrace: - case lldb::eStopReasonPlanComplete: - body.try_emplace("reason", "step"); - break; - case lldb::eStopReasonBreakpoint: { - ExceptionBreakpoint *exc_bp = dap.GetExceptionBPFromStopReason(thread); - if (exc_bp) { - body.try_emplace("reason", "exception"); - EmplaceSafeString(body, "description", exc_bp->GetLabel()); - } else { - InstructionBreakpoint *inst_bp = - dap.GetInstructionBPFromStopReason(thread); - if (inst_bp) { - body.try_emplace("reason", "instruction breakpoint"); - } else { - body.try_emplace("reason", "breakpoint"); - } - std::vector bp_ids; - std::ostringstream desc_sstream; - desc_sstream << "breakpoint"; - for (size_t idx = 0; idx < thread.GetStopReasonDataCount(); idx += 2) { - lldb::break_id_t bp_id = thread.GetStopReasonDataAtIndex(idx); - lldb::break_id_t bp_loc_id = thread.GetStopReasonDataAtIndex(idx + 1); - bp_ids.push_back(bp_id); - desc_sstream << " " << bp_id << "." << bp_loc_id; - } - std::string desc_str = desc_sstream.str(); - body.try_emplace("hitBreakpointIds", llvm::json::Array(bp_ids)); - EmplaceSafeString(body, "description", desc_str); - } - } break; - case lldb::eStopReasonWatchpoint: { - body.try_emplace("reason", "data breakpoint"); - lldb::break_id_t bp_id = thread.GetStopReasonDataAtIndex(0); - body.try_emplace("hitBreakpointIds", - llvm::json::Array{llvm::json::Value(bp_id)}); - EmplaceSafeString(body, "description", - llvm::formatv("data breakpoint {0}", bp_id).str()); - } break; - case lldb::eStopReasonInstrumentation: - body.try_emplace("reason", "exception"); - break; - case lldb::eStopReasonProcessorTrace: - body.try_emplace("reason", "processor trace"); - break; - case lldb::eStopReasonHistoryBoundary: - body.try_emplace("reason", "history boundary"); - break; - case lldb::eStopReasonSignal: - case lldb::eStopReasonException: - body.try_emplace("reason", "exception"); - break; - case lldb::eStopReasonExec: - body.try_emplace("reason", "entry"); - break; - case lldb::eStopReasonFork: - body.try_emplace("reason", "fork"); - break; - case lldb::eStopReasonVFork: - body.try_emplace("reason", "vfork"); - break; - case lldb::eStopReasonVForkDone: - body.try_emplace("reason", "vforkdone"); - break; - case lldb::eStopReasonInterrupt: - body.try_emplace("reason", "async interrupt"); - break; - case lldb::eStopReasonThreadExiting: - case lldb::eStopReasonInvalid: - case lldb::eStopReasonNone: - break; - } - if (stop_id == 0) - body["reason"] = "entry"; - const lldb::tid_t tid = thread.GetThreadID(); - body.try_emplace("threadId", (int64_t)tid); - // If no description has been set, then set it to the default thread stopped - // description. If we have breakpoints that get hit and shouldn't be reported - // as breakpoints, then they will set the description above. - if (!ObjectContainsKey(body, "description")) { - char description[1024]; - if (thread.GetStopDescription(description, sizeof(description))) { - EmplaceSafeString(body, "description", description); - } - } - // "threadCausedFocus" is used in tests to validate breaking behavior. - if (tid == dap.focus_tid) { - body.try_emplace("threadCausedFocus", true); - } - body.try_emplace("preserveFocusHint", tid != dap.focus_tid); - body.try_emplace("allThreadsStopped", true); - event.try_emplace("body", std::move(body)); - return llvm::json::Value(std::move(event)); -} - llvm::StringRef GetNonNullVariableName(lldb::SBValue &v) { const llvm::StringRef name = v.GetName(); return !name.empty() ? name : ""; @@ -747,6 +590,12 @@ llvm::json::Object CreateTerminatedEventObject(lldb::SBTarget &target) { return event; } +llvm::json::Object CreateInitializedEventObject(lldb::SBTarget &target) { + llvm::json::Object event(CreateEventObject("initialized")); + addStatistic(target, event); + return event; +} + std::string JSONToString(const llvm::json::Value &json) { std::string data; llvm::raw_string_ostream os(data); diff --git a/lldb/tools/lldb-dap/JSONUtils.h b/lldb/tools/lldb-dap/JSONUtils.h index 15449d6ece62a..232b1810a3cf4 100644 --- a/lldb/tools/lldb-dap/JSONUtils.h +++ b/lldb/tools/lldb-dap/JSONUtils.h @@ -234,36 +234,6 @@ void FillResponse(const llvm::json::Object &request, /// definition outlined by Microsoft. llvm::json::Object CreateEventObject(const llvm::StringRef event_name); -/// Create a "StoppedEvent" object for a LLDB thread object. -/// -/// This function will fill in the following keys in the returned -/// object's "body" object: -/// "reason" - With a valid stop reason enumeration string value -/// that Microsoft specifies -/// "threadId" - The thread ID as an integer -/// "description" - a stop description (like "breakpoint 12.3") as a -/// string -/// "preserveFocusHint" - a boolean value that states if this thread -/// should keep the focus in the GUI. -/// "allThreadsStopped" - set to True to indicate that all threads -/// stop when any thread stops. -/// -/// \param[in] dap -/// The DAP session associated with the stopped thread. -/// -/// \param[in] thread -/// The LLDB thread to use when populating out the "StoppedEvent" -/// object. -/// -/// \param[in] stop_id -/// The stop id for this event. -/// -/// \return -/// A "StoppedEvent" JSON object with that follows the formal JSON -/// definition outlined by Microsoft. -llvm::json::Value CreateThreadStopped(DAP &dap, lldb::SBThread &thread, - uint32_t stop_id); - /// \return /// The variable name of \a value or a default placeholder. llvm::StringRef GetNonNullVariableName(lldb::SBValue &value); @@ -363,6 +333,12 @@ llvm::json::Object CreateRunInTerminalReverseRequest( /// A body JSON object with debug info and breakpoint info llvm::json::Object CreateTerminatedEventObject(lldb::SBTarget &target); +/// Create a "Initialized" JSON object that contains statistics +/// +/// \return +/// A body JSON object with debug info +llvm::json::Object CreateInitializedEventObject(lldb::SBTarget &target); + /// Convert a given JSON object to a string. std::string JSONToString(const llvm::json::Value &json); diff --git a/lldb/tools/lldb-dap/Protocol/ProtocolEvents.cpp b/lldb/tools/lldb-dap/Protocol/ProtocolEvents.cpp index df6be06637a13..b1985cbb7d053 100644 --- a/lldb/tools/lldb-dap/Protocol/ProtocolEvents.cpp +++ b/lldb/tools/lldb-dap/Protocol/ProtocolEvents.cpp @@ -8,6 +8,8 @@ #include "Protocol/ProtocolEvents.h" #include "JSONUtils.h" +#include "lldb/lldb-defines.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/JSON.h" using namespace llvm; @@ -64,4 +66,49 @@ llvm::json::Value toJSON(const MemoryEventBody &MEB) { {"count", MEB.count}}; } +static llvm::json::Value toJSON(const StoppedReason &SR) { + assert(SR != eStoppedReasonUninitialized && "StopReason Uninitialized"); + switch (SR) { + case eStoppedReasonUninitialized: + return ""; + case eStoppedReasonStep: + return "step"; + case eStoppedReasonBreakpoint: + return "breakpoint"; + case eStoppedReasonException: + return "exception"; + case eStoppedReasonPause: + return "pause"; + case eStoppedReasonEntry: + return "entry"; + case eStoppedReasonGoto: + return "goto"; + case eStoppedReasonFunctionBreakpoint: + return "function breakpoint"; + case eStoppedReasonDataBreakpoint: + return "data breakpoint"; + case eStoppedReasonInstructionBreakpoint: + return "instruction breakpoint"; + } +} + +llvm::json::Value toJSON(const StoppedEventBody &SEB) { + llvm::json::Object Result{{"reason", SEB.reason}}; + + if (!SEB.description.empty()) + Result.insert({"description", SEB.description}); + if (SEB.threadId != LLDB_INVALID_THREAD_ID) + Result.insert({"threadId", SEB.threadId}); + if (SEB.preserveFocusHint) + Result.insert({"preserveFocusHint", SEB.preserveFocusHint}); + if (!SEB.text.empty()) + Result.insert({"text", SEB.text}); + if (SEB.allThreadsStopped) + Result.insert({"allThreadsStopped", SEB.allThreadsStopped}); + if (!SEB.hitBreakpointIds.empty()) + Result.insert({"hitBreakpointIds", SEB.hitBreakpointIds}); + + return Result; +} + } // namespace lldb_dap::protocol diff --git a/lldb/tools/lldb-dap/Protocol/ProtocolEvents.h b/lldb/tools/lldb-dap/Protocol/ProtocolEvents.h index 5cd5a843d284e..5c415f76c37fd 100644 --- a/lldb/tools/lldb-dap/Protocol/ProtocolEvents.h +++ b/lldb/tools/lldb-dap/Protocol/ProtocolEvents.h @@ -117,6 +117,68 @@ struct MemoryEventBody { }; llvm::json::Value toJSON(const MemoryEventBody &); +enum StoppedReason : unsigned { + eStoppedReasonUninitialized, + eStoppedReasonStep, + eStoppedReasonBreakpoint, + eStoppedReasonException, + eStoppedReasonPause, + eStoppedReasonEntry, + eStoppedReasonGoto, + eStoppedReasonFunctionBreakpoint, + eStoppedReasonDataBreakpoint, + eStoppedReasonInstructionBreakpoint, +}; + +/// The event indicates that the execution of the debuggee has stopped due to +/// some condition. +/// +/// This can be caused by a breakpoint previously set, a stepping request has +/// completed, by executing a debugger statement etc. +struct StoppedEventBody { + /// The reason for the event. + /// + /// For backward compatibility this string is shown in the UI if the + /// `description` attribute is missing (but it must not be translated). + StoppedReason reason = eStoppedReasonUninitialized; + + /// The full reason for the event, e.g. 'Paused on exception'. This string is + /// shown in the UI as is and can be translated. + std::string description; + + /// The thread which was stopped. + lldb::tid_t threadId = LLDB_INVALID_THREAD_ID; + + /// A value of true hints to the client that this event should not change the + /// focus. + bool preserveFocusHint = false; + + /// Additional information. E.g. if reason is `exception`, text contains the + /// exception name. This string is shown in the UI. + std::string text; + + /// "If `allThreadsStopped` is true, a debug adapter can announce that all + /// threads have stopped. + /// + /// - The client should use this information to enable that all threads can be + /// expanded to access their stacktraces. + /// - If the attribute is missing or false, only the thread with the given + /// `threadId` can be expanded. + bool allThreadsStopped = false; + + /// Ids of the breakpoints that triggered the event. In most cases there is + /// only a single breakpoint but here are some examples for multiple + /// breakpoints: + /// + /// - Different types of breakpoints map to the same location. + /// - Multiple source breakpoints get collapsed to the same instruction by the + /// compiler/runtime. + /// - Multiple function breakpoints with different function names map to the + /// same location. + std::vector hitBreakpointIds; +}; +llvm::json::Value toJSON(const StoppedEventBody &); + } // end namespace lldb_dap::protocol #endif diff --git a/lldb/tools/lldb-dap/SBAPIExtras.h b/lldb/tools/lldb-dap/SBAPIExtras.h index 0745b2e043c21..eb59cb08ea4fd 100644 --- a/lldb/tools/lldb-dap/SBAPIExtras.h +++ b/lldb/tools/lldb-dap/SBAPIExtras.h @@ -8,6 +8,7 @@ // Extensions on SB API. //===----------------------------------------------------------------------===// +#include "lldb/API/SBProcess.h" #include "lldb/API/SBStream.h" #include "lldb/API/SBStructuredData.h" #include "lldb/API/SBThread.h" @@ -34,11 +35,19 @@ struct iter { bool operator!=(const iter &other) { return index != other.index; } }; +/// SBProcess thread iterator. +using process_thread_iter = + iter; +inline process_thread_iter begin(SBProcess P) { return {P, 0}; } +inline process_thread_iter end(SBProcess P) { return {P, P.GetNumThreads()}; } + /// SBThreadCollection thread iterator. -using thread_iter = iter; -inline thread_iter begin(SBThreadCollection TC) { return {TC, 0}; } -inline thread_iter end(SBThreadCollection TC) { return {TC, TC.GetSize()}; } +using thread_collection_iter = iter; +inline thread_collection_iter begin(SBThreadCollection TC) { return {TC, 0}; } +inline thread_collection_iter end(SBThreadCollection TC) { + return {TC, TC.GetSize()}; +} /// SBThread frame iterator. using frame_iter = diff --git a/lldb/tools/lldb-dap/Transport.cpp b/lldb/tools/lldb-dap/Transport.cpp index b3512385d6579..b149a8ee8f026 100644 --- a/lldb/tools/lldb-dap/Transport.cpp +++ b/lldb/tools/lldb-dap/Transport.cpp @@ -17,9 +17,9 @@ using namespace lldb_private; namespace lldb_dap { -Transport::Transport(lldb_dap::Log &log, lldb::IOObjectSP input, - lldb::IOObjectSP output) - : HTTPDelimitedJSONTransport(input, output), m_log(log) {} +Transport::Transport(lldb_dap::Log &log, lldb_private::MainLoop &loop, + lldb::IOObjectSP input, lldb::IOObjectSP output) + : HTTPDelimitedJSONTransport(loop, input, output), m_log(log) {} void Transport::Log(llvm::StringRef message) { // Emit the message directly, since this log was forwarded. diff --git a/lldb/tools/lldb-dap/Transport.h b/lldb/tools/lldb-dap/Transport.h index b20a93475d2dd..42f7caf93831a 100644 --- a/lldb/tools/lldb-dap/Transport.h +++ b/lldb/tools/lldb-dap/Transport.h @@ -35,8 +35,8 @@ class Transport final : public lldb_private::transport::HTTPDelimitedJSONTransport< ProtocolDescriptor> { public: - Transport(lldb_dap::Log &log, lldb::IOObjectSP input, - lldb::IOObjectSP output); + Transport(lldb_dap::Log &log, lldb_private::MainLoop &loop, + lldb::IOObjectSP input, lldb::IOObjectSP output); virtual ~Transport() = default; void Log(llvm::StringRef message) override; diff --git a/lldb/tools/lldb-dap/extension/package-lock.json b/lldb/tools/lldb-dap/extension/package-lock.json index bdf227fb1c8f3..400991870f454 100644 --- a/lldb/tools/lldb-dap/extension/package-lock.json +++ b/lldb/tools/lldb-dap/extension/package-lock.json @@ -15,7 +15,7 @@ "@types/mocha": "^10.0.10", "@types/node": "^18.19.41", "@types/tabulator-tables": "^6.2.10", - "@types/vscode": "1.75.0", + "@types/vscode": "1.90.0", "@types/vscode-webview": "^1.57.5", "@vscode/debugprotocol": "^1.68.0", "@vscode/test-cli": "^0.0.12", @@ -31,7 +31,7 @@ "typescript": "^5.7.3" }, "engines": { - "vscode": "^1.75.0" + "vscode": "^1.90.0" } }, "node_modules/@azure/abort-controller": { @@ -1231,9 +1231,9 @@ "license": "MIT" }, "node_modules/@types/vscode": { - "version": "1.75.0", - "resolved": "https://registry.npmjs.org/@types/vscode/-/vscode-1.75.0.tgz", - "integrity": "sha512-SAr0PoOhJS6FUq5LjNr8C/StBKALZwDVm3+U4pjF/3iYkt3GioJOPV/oB1Sf1l7lROe4TgrMyL5N1yaEgTWycw==", + "version": "1.90.0", + "resolved": "https://registry.npmjs.org/@types/vscode/-/vscode-1.90.0.tgz", + "integrity": "sha512-oT+ZJL7qHS9Z8bs0+WKf/kQ27qWYR3trsXpq46YDjFqBsMLG4ygGGjPaJ2tyrH0wJzjOEmDyg9PDJBBhWg9pkQ==", "dev": true, "license": "MIT" }, diff --git a/lldb/tools/lldb-dap/extension/package.json b/lldb/tools/lldb-dap/extension/package.json index c90609cf7f760..923c437006556 100644 --- a/lldb/tools/lldb-dap/extension/package.json +++ b/lldb/tools/lldb-dap/extension/package.json @@ -22,7 +22,7 @@ "LLDB" ], "engines": { - "vscode": "^1.75.0" + "vscode": "^1.90.0" }, "categories": [ "Debuggers" @@ -34,7 +34,7 @@ "@types/mocha": "^10.0.10", "@types/node": "^18.19.41", "@types/tabulator-tables": "^6.2.10", - "@types/vscode": "1.75.0", + "@types/vscode": "1.90.0", "@types/vscode-webview": "^1.57.5", "@vscode/debugprotocol": "^1.68.0", "@vscode/test-cli": "^0.0.12", diff --git a/lldb/tools/lldb-dap/tool/lldb-dap.cpp b/lldb/tools/lldb-dap/tool/lldb-dap.cpp index 15c63543e86f5..babc3c98646cb 100644 --- a/lldb/tools/lldb-dap/tool/lldb-dap.cpp +++ b/lldb/tools/lldb-dap/tool/lldb-dap.cpp @@ -47,7 +47,6 @@ #include "llvm/Support/Threading.h" #include "llvm/Support/WithColor.h" #include "llvm/Support/raw_ostream.h" -#include #include #include #include @@ -463,7 +462,7 @@ static llvm::Error serveConnection( DAP_LOG(client_log, "client connected"); MainLoop loop; - Transport transport(client_log, io, io); + Transport transport(client_log, loop, io, io); DAP dap(client_log, default_repl_mode, pre_init_commands, no_lldbinit, client_name, transport, loop); @@ -738,7 +737,7 @@ int main(int argc, char *argv[]) { constexpr llvm::StringLiteral client_name = "stdio"; MainLoop loop; Log client_log = log.WithPrefix("(stdio)"); - Transport transport(client_log, input, output); + Transport transport(client_log, loop, input, output); DAP dap(client_log, default_repl_mode, pre_init_commands, no_lldbinit, client_name, transport, loop); diff --git a/lldb/unittests/DAP/CMakeLists.txt b/lldb/unittests/DAP/CMakeLists.txt index 9fef37e00ed5d..97f9cad7477ed 100644 --- a/lldb/unittests/DAP/CMakeLists.txt +++ b/lldb/unittests/DAP/CMakeLists.txt @@ -10,6 +10,7 @@ add_lldb_unittest(DAPTests Handler/ContinueTest.cpp JSONUtilsTest.cpp LLDBUtilsTest.cpp + ProtocolEventsTest.cpp ProtocolRequestsTest.cpp ProtocolTypesTest.cpp ProtocolUtilsTest.cpp diff --git a/lldb/unittests/DAP/ProtocolEventsTest.cpp b/lldb/unittests/DAP/ProtocolEventsTest.cpp new file mode 100644 index 0000000000000..b6efc2791e578 --- /dev/null +++ b/lldb/unittests/DAP/ProtocolEventsTest.cpp @@ -0,0 +1,45 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Protocol/ProtocolEvents.h" +#include "TestingSupport/TestUtilities.h" +#include "llvm/Testing/Support/Error.h" +#include + +using namespace llvm; +using namespace lldb_dap::protocol; +using lldb_private::PrettyPrint; +using llvm::json::parse; +using llvm::json::Value; + +TEST(ProtocolEventsTest, StoppedEventBody) { + StoppedEventBody body; + body.reason = lldb_dap::protocol::eStoppedReasonBreakpoint; + Expected expected_body = parse(R"({ + "reason": "breakpoint" + })"); + ASSERT_THAT_EXPECTED(expected_body, llvm::Succeeded()); + EXPECT_EQ(PrettyPrint(*expected_body), PrettyPrint(body)); + + body.reason = eStoppedReasonBreakpoint; + body.description = "desc"; + body.text = "text"; + body.preserveFocusHint = true; + body.allThreadsStopped = true; + body.hitBreakpointIds = {1, 2, 3}; + expected_body = parse(R"({ + "reason": "breakpoint", + "allThreadsStopped": true, + "description": "desc", + "text": "text", + "preserveFocusHint": true, + "hitBreakpointIds": [1, 2, 3] + })"); + ASSERT_THAT_EXPECTED(expected_body, llvm::Succeeded()); + EXPECT_EQ(PrettyPrint(*expected_body), PrettyPrint(body)); +} diff --git a/lldb/unittests/DAP/ProtocolTypesTest.cpp b/lldb/unittests/DAP/ProtocolTypesTest.cpp index 0d60329f30269..88af97248febc 100644 --- a/lldb/unittests/DAP/ProtocolTypesTest.cpp +++ b/lldb/unittests/DAP/ProtocolTypesTest.cpp @@ -21,15 +21,11 @@ using namespace llvm; using namespace lldb; using namespace lldb_dap; using namespace lldb_dap::protocol; +using lldb_private::PrettyPrint; using lldb_private::roundtripJSON; using llvm::json::parse; using llvm::json::Value; -/// Returns a pretty printed json string of a `llvm::json::Value`. -static std::string pp(const json::Value &E) { - return formatv("{0:2}", E).str(); -} - TEST(ProtocolTypesTest, ExceptionBreakpointsFilter) { ExceptionBreakpointsFilter filter; filter.filter = "testFilter"; @@ -597,7 +593,7 @@ TEST(ProtocolTypesTest, DisassembledInstruction) { })"; // Validate toJSON - EXPECT_EQ(json, pp(instruction)); + EXPECT_EQ(json, PrettyPrint(instruction)); // Validate fromJSON EXPECT_THAT_EXPECTED(parse(json), @@ -627,7 +623,7 @@ TEST(ProtocolTypesTest, Thread) { "name": "thr1" })"; // Validate toJSON - EXPECT_EQ(json, pp(thread)); + EXPECT_EQ(json, PrettyPrint(thread)); // Validate fromJSON EXPECT_THAT_EXPECTED(parse(json), HasValue(Value(thread))); // Validate parsing errors @@ -654,7 +650,7 @@ TEST(ProtocolTypesTest, ThreadResponseBody) { ] })"; // Validate toJSON - EXPECT_EQ(json, pp(body)); + EXPECT_EQ(json, PrettyPrint(body)); } TEST(ProtocolTypesTest, CapabilitiesEventBody) { @@ -672,7 +668,7 @@ TEST(ProtocolTypesTest, CapabilitiesEventBody) { } })"; // Validate toJSON - EXPECT_EQ(json, pp(body)); + EXPECT_EQ(json, PrettyPrint(body)); } TEST(ProtocolTypesTest, ExceptionFilterOptions) { @@ -741,7 +737,7 @@ TEST(ProtocolTypesTest, SetExceptionBreakpointsResponseBody) { } ] })", - pp(body)); + PrettyPrint(body)); } TEST(ProtocolTypesTest, StepInTarget) { @@ -794,7 +790,7 @@ TEST(ProtocolTypesTest, ReadMemoryResponseBody) { Expected expected = json::parse( R"({ "address": "0xDEADBEEF", "data": "aGVsbG8gd29ybGQh", "unreadableBytes": 1})"); ASSERT_THAT_EXPECTED(expected, llvm::Succeeded()); - EXPECT_EQ(pp(*expected), pp(response)); + EXPECT_EQ(PrettyPrint(*expected), PrettyPrint(response)); } TEST(ProtocolTypesTest, Modules) { @@ -825,7 +821,7 @@ TEST(ProtocolTypesTest, Modules) { "addressRange": "0xcafeface", "debugInfoSize": "1.5MB" })"); ASSERT_THAT_EXPECTED(expected, llvm::Succeeded()); - EXPECT_EQ(pp(*expected), pp(module)); + EXPECT_EQ(PrettyPrint(*expected), PrettyPrint(module)); // Test without optional values. module.path.clear(); @@ -837,14 +833,14 @@ TEST(ProtocolTypesTest, Modules) { module.dateTimeStamp.clear(); module.addressRange.clear(); module.debugInfoSizeBytes = 0; - EXPECT_NE(pp(*expected), pp(module)); + EXPECT_NE(PrettyPrint(*expected), PrettyPrint(module)); Expected expected_no_opt = json::parse( R"({ "id" : "AC805E8E-B6A4-CD92-4B05-5CFA7CE24AE8-8926C776", "name": "libm.so.6"})"); ASSERT_THAT_EXPECTED(expected_no_opt, llvm::Succeeded()); - EXPECT_EQ(pp(*expected_no_opt), pp(module)); + EXPECT_EQ(PrettyPrint(*expected_no_opt), PrettyPrint(module)); } TEST(ProtocolTypesTest, ModulesArguments) { @@ -885,7 +881,7 @@ TEST(ProtocolTypesTest, ModulesResponseBody) { ], "totalModules": 2 })"); ASSERT_THAT_EXPECTED(expected, llvm::Succeeded()); - EXPECT_EQ(pp(*expected), pp(response)); + EXPECT_EQ(PrettyPrint(*expected), PrettyPrint(response)); } TEST(ProtocolTypesTest, VariablePresentationHint) { @@ -906,7 +902,7 @@ TEST(ProtocolTypesTest, VariablePresentationHint) { "visibility": "public" })"; - EXPECT_EQ(pp(Value(hint)), json); + EXPECT_EQ(PrettyPrint(Value(hint)), json); EXPECT_THAT_EXPECTED(json::parse(json), HasValue(Value(hint))); } @@ -943,7 +939,7 @@ TEST(ProtocolTypesTest, Variable) { "variablesReference": 42 })"; - EXPECT_EQ(pp(Value(var)), json); + EXPECT_EQ(PrettyPrint(Value(var)), json); EXPECT_THAT_EXPECTED(json::parse(json), HasValue(Value(var))); } @@ -1002,7 +998,7 @@ TEST(ProtocolTypesTest, VariablesResponseBody) { ] })"); ASSERT_THAT_EXPECTED(expected, llvm::Succeeded()); - EXPECT_EQ(pp(*expected), pp(response)); + EXPECT_EQ(PrettyPrint(*expected), PrettyPrint(response)); } TEST(ProtocolTypesTest, CompletionItem) { @@ -1029,7 +1025,7 @@ TEST(ProtocolTypesTest, CompletionItem) { "type": "constructor" })"; - EXPECT_EQ(pp(Value(item)), json); + EXPECT_EQ(PrettyPrint(Value(item)), json); EXPECT_THAT_EXPECTED(json::parse(json), HasValue(Value(item))); } @@ -1071,7 +1067,7 @@ TEST(ProtocolTypesTest, CompletionsResponseBody) { ] })"); ASSERT_THAT_EXPECTED(expected, llvm::Succeeded()); - EXPECT_EQ(pp(*expected), pp(response)); + EXPECT_EQ(PrettyPrint(*expected), PrettyPrint(response)); } TEST(ProtocolTypesTest, InvalidatedEventBody) { @@ -1089,7 +1085,7 @@ TEST(ProtocolTypesTest, InvalidatedEventBody) { "threadId": 20 })"); ASSERT_THAT_EXPECTED(expected, llvm::Succeeded()); - EXPECT_EQ(pp(*expected), pp(body)); + EXPECT_EQ(PrettyPrint(*expected), PrettyPrint(body)); } TEST(ProtocolTypesTest, MemoryEventBody) { @@ -1102,7 +1098,7 @@ TEST(ProtocolTypesTest, MemoryEventBody) { "memoryReference": "0x3039", "offset": 0 })"; - EXPECT_EQ(json, pp(body)); + EXPECT_EQ(json, PrettyPrint(body)); } TEST(ProtocolTypesTest, DataBreakpointInfoArguments) { @@ -1150,7 +1146,7 @@ TEST(ProtocolTypesTest, ExceptionDetails) { // Check required keys. Expected expected = parse(R"({})"); ASSERT_THAT_EXPECTED(expected, llvm::Succeeded()); - EXPECT_EQ(pp(*expected), pp(details)); + EXPECT_EQ(PrettyPrint(*expected), PrettyPrint(details)); // Check optional keys. details.message = "SIGABRT exception"; @@ -1174,7 +1170,7 @@ TEST(ProtocolTypesTest, ExceptionDetails) { })"); ASSERT_THAT_EXPECTED(expected_opt, llvm::Succeeded()); - EXPECT_EQ(pp(*expected_opt), pp(details)); + EXPECT_EQ(PrettyPrint(*expected_opt), PrettyPrint(details)); } TEST(ProtocolTypesTest, StackFramePresentationHint) { @@ -1241,7 +1237,7 @@ TEST(ProtocolTypesTest, StackFrame) { })"); ASSERT_THAT_EXPECTED(expected_frame, llvm::Succeeded()); - EXPECT_EQ(pp(*expected_frame), pp(frame)); + EXPECT_EQ(PrettyPrint(*expected_frame), PrettyPrint(frame)); frame.id = 2; frame.canRestart = true; @@ -1260,7 +1256,7 @@ TEST(ProtocolTypesTest, StackFrame) { })"); ASSERT_THAT_EXPECTED(expected_frame, llvm::Succeeded()); - EXPECT_EQ(pp(*expected_frame), pp(frame)); + EXPECT_EQ(PrettyPrint(*expected_frame), PrettyPrint(frame)); } TEST(ProtocolTypesTest, DAPSession) { diff --git a/lldb/unittests/DAP/TestBase.cpp b/lldb/unittests/DAP/TestBase.cpp index a9231085637c9..1afac18833a03 100644 --- a/lldb/unittests/DAP/TestBase.cpp +++ b/lldb/unittests/DAP/TestBase.cpp @@ -35,7 +35,7 @@ using lldb_private::MainLoop; using lldb_private::Pipe; void TransportBase::SetUp() { - std::tie(to_client, to_server) = TestDAPTransport::createPair(); + std::tie(to_client, to_server) = TestDAPTransport::createPair(loop); log = std::make_unique(llvm::outs(), log_mutex); dap = std::make_unique( @@ -46,13 +46,8 @@ void TransportBase::SetUp() { /*client_name=*/"test_client", /*transport=*/*to_client, /*loop=*/loop); - auto server_handle = to_server->RegisterMessageHandler(loop, *dap); - EXPECT_THAT_EXPECTED(server_handle, Succeeded()); - handles[0] = std::move(*server_handle); - - auto client_handle = to_client->RegisterMessageHandler(loop, client); - EXPECT_THAT_EXPECTED(client_handle, Succeeded()); - handles[1] = std::move(*client_handle); + EXPECT_THAT_ERROR(to_server->RegisterMessageHandler(*dap), Succeeded()); + EXPECT_THAT_ERROR(to_client->RegisterMessageHandler(client), Succeeded()); } void TransportBase::Run() { diff --git a/lldb/unittests/DAP/TestBase.h b/lldb/unittests/DAP/TestBase.h index f1c7e6b989729..c354829377434 100644 --- a/lldb/unittests/DAP/TestBase.h +++ b/lldb/unittests/DAP/TestBase.h @@ -59,7 +59,6 @@ class TransportBase : public testing::Test { lldb_private::SubsystemRAII subsystems; lldb_private::MainLoop loop; - lldb_private::MainLoop::ReadHandleUP handles[2]; std::unique_ptr log; lldb_dap::Log::Mutex log_mutex; diff --git a/lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp b/lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp index 5e980c3e1913c..0956c55e9e880 100644 --- a/lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp +++ b/lldb/unittests/DataFormatter/FormatterBytecodeTest.cpp @@ -1,4 +1,4 @@ -#include "DataFormatters/FormatterBytecode.h" +#include "lldb/DataFormatters/FormatterBytecode.h" #include "lldb/Utility/StreamString.h" #include "gtest/gtest.h" diff --git a/lldb/unittests/Expression/ClangExpressionDeclMapTest.cpp b/lldb/unittests/Expression/ClangExpressionDeclMapTest.cpp index 1c07119d4497f..61905ee8df862 100644 --- a/lldb/unittests/Expression/ClangExpressionDeclMapTest.cpp +++ b/lldb/unittests/Expression/ClangExpressionDeclMapTest.cpp @@ -23,7 +23,7 @@ namespace { struct FakeClangExpressionDeclMap : public ClangExpressionDeclMap { FakeClangExpressionDeclMap(const std::shared_ptr &importer) : ClangExpressionDeclMap(false, nullptr, lldb::TargetSP(), importer, - nullptr) { + nullptr, /*ignore_context_qualifiers=*/false) { m_holder = std::make_unique("ast"); m_scratch_context = m_holder->GetAST(); } diff --git a/lldb/unittests/Expression/ExpressionTest.cpp b/lldb/unittests/Expression/ExpressionTest.cpp index ceb567c28ab99..19647c162fa5a 100644 --- a/lldb/unittests/Expression/ExpressionTest.cpp +++ b/lldb/unittests/Expression/ExpressionTest.cpp @@ -11,6 +11,7 @@ #include "TestingSupport/TestUtilities.h" #include "lldb/Expression/Expression.h" +#include "lldb/Target/Target.h" #include "llvm/Testing/Support/Error.h" using namespace lldb_private; @@ -127,3 +128,41 @@ TEST_P(ExpressionTestFixture, FunctionCallLabel) { INSTANTIATE_TEST_SUITE_P(FunctionCallLabelTest, ExpressionTestFixture, testing::ValuesIn(g_label_test_cases)); + +TEST(ExpressionTests, ExpressionOptions_Basic) { + EvaluateExpressionOptions options; + + EXPECT_THAT_EXPECTED(options.GetBooleanLanguageOption("foo"), + llvm::FailedWithMessage("Option 'foo' does not exist.")); + EXPECT_THAT_EXPECTED(options.GetBooleanLanguageOption("bar"), + llvm::FailedWithMessage("Option 'bar' does not exist.")); + + EXPECT_THAT_ERROR(options.SetBooleanLanguageOption("foo", true), + llvm::Succeeded()); + EXPECT_THAT_ERROR(options.SetBooleanLanguageOption("bar", false), + llvm::Succeeded()); + + EXPECT_THAT_EXPECTED(options.GetBooleanLanguageOption("foo"), + llvm::HasValue(true)); + EXPECT_THAT_EXPECTED(options.GetBooleanLanguageOption("bar"), + llvm::HasValue(false)); + + EXPECT_THAT_ERROR(options.SetBooleanLanguageOption("foo", false), + llvm::Succeeded()); + EXPECT_THAT_ERROR(options.SetBooleanLanguageOption("bar", true), + llvm::Succeeded()); + + EXPECT_THAT_EXPECTED(options.GetBooleanLanguageOption("foo"), + llvm::HasValue(false)); + EXPECT_THAT_EXPECTED(options.GetBooleanLanguageOption("bar"), + llvm::HasValue(true)); + + // Empty option names not allowed. + EXPECT_THAT_EXPECTED(options.GetBooleanLanguageOption(""), + llvm::FailedWithMessage("Option '' does not exist.")); + EXPECT_THAT_ERROR( + options.SetBooleanLanguageOption("", true), + llvm::FailedWithMessage("Can't set an option with an empty name.")); + EXPECT_THAT_EXPECTED(options.GetBooleanLanguageOption(""), + llvm::FailedWithMessage("Option '' does not exist.")); +} diff --git a/lldb/unittests/Host/JSONTransportTest.cpp b/lldb/unittests/Host/JSONTransportTest.cpp index 710907af3794a..2c26f94213773 100644 --- a/lldb/unittests/Host/JSONTransportTest.cpp +++ b/lldb/unittests/Host/JSONTransportTest.cpp @@ -247,19 +247,22 @@ template class JSONTransportTest : public PipePairTest { protected: SubsystemRAII subsystems; + MainLoop loop; test_protocol::MessageHandler message_handler; std::unique_ptr transport; - MainLoop loop; void SetUp() override { PipePairTest::SetUp(); transport = std::make_unique( - std::make_shared(input.GetReadFileDescriptor(), + loop, + std::make_shared(input.ReleaseReadFileDescriptor(), File::eOpenOptionReadOnly, - NativeFile::Unowned), - std::make_shared(output.GetWriteFileDescriptor(), + NativeFile::Owned), + std::make_shared(output.ReleaseWriteFileDescriptor(), File::eOpenOptionWriteOnly, - NativeFile::Unowned)); + NativeFile::Owned)); + EXPECT_THAT_ERROR(transport->RegisterMessageHandler(message_handler), + Succeeded()); } /// Run the transport MainLoop and return any messages received. @@ -272,17 +275,13 @@ template class JSONTransportTest : public PipePairTest { loop.RequestTermination(); }); } - bool addition_succeeded = loop.AddCallback( + bool registered_timeout = loop.AddCallback( [](MainLoopBase &loop) { loop.RequestTermination(); FAIL() << "timeout"; }, timeout); - EXPECT_TRUE(addition_succeeded); - auto handle = transport->RegisterMessageHandler(loop, message_handler); - if (!handle) - return handle.takeError(); - + EXPECT_TRUE(registered_timeout); return loop.Run().takeError(); } @@ -360,14 +359,13 @@ class TransportBinderTest : public testing::Test { MainLoop loop; void SetUp() override { - std::tie(to_remote, from_remote) = test_protocol::Transport::createPair(); + std::tie(to_remote, from_remote) = + test_protocol::Transport::createPair(loop); binder = std::make_unique(*to_remote); - auto binder_handle = to_remote->RegisterMessageHandler(loop, remote); - EXPECT_THAT_EXPECTED(binder_handle, Succeeded()); - - auto remote_handle = from_remote->RegisterMessageHandler(loop, *binder); - EXPECT_THAT_EXPECTED(remote_handle, Succeeded()); + EXPECT_THAT_ERROR(to_remote->RegisterMessageHandler(remote), Succeeded()); + EXPECT_THAT_ERROR(from_remote->RegisterMessageHandler(*binder), + Succeeded()); } void Run() { @@ -502,8 +500,8 @@ TEST_F(HTTPDelimitedJSONTransportTest, ReaderWithUnhandledData) { TEST_F(HTTPDelimitedJSONTransportTest, InvalidTransport) { transport = - std::make_unique(nullptr, nullptr); - ASSERT_THAT_ERROR(Run(/*close_input=*/false), + std::make_unique(loop, nullptr, nullptr); + ASSERT_THAT_ERROR(transport->RegisterMessageHandler(message_handler), FailedWithMessage("IO object is not valid.")); } @@ -624,8 +622,8 @@ TEST_F(JSONRPCTransportTest, Write) { } TEST_F(JSONRPCTransportTest, InvalidTransport) { - transport = std::make_unique(nullptr, nullptr); - ASSERT_THAT_ERROR(Run(/*close_input=*/false), + transport = std::make_unique(loop, nullptr, nullptr); + ASSERT_THAT_ERROR(transport->RegisterMessageHandler(message_handler), FailedWithMessage("IO object is not valid.")); } diff --git a/lldb/unittests/ObjectFile/MachO/CMakeLists.txt b/lldb/unittests/ObjectFile/MachO/CMakeLists.txt index b6c4225114a36..1b071ff1bd738 100644 --- a/lldb/unittests/ObjectFile/MachO/CMakeLists.txt +++ b/lldb/unittests/ObjectFile/MachO/CMakeLists.txt @@ -6,5 +6,6 @@ add_lldb_unittest(ObjectFileMachOTests lldbPluginSymbolFileSymtab lldbCore lldbUtilityHelpers + lldbPluginPlatformMacOSX LLVMTestingSupport ) diff --git a/lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp b/lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp index 3adb642c1108e..5b516fc2582f5 100644 --- a/lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp +++ b/lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp @@ -6,12 +6,14 @@ // //===----------------------------------------------------------------------===// -#include "lldb/Host/HostInfo.h" #include "Plugins/ObjectFile/Mach-O/ObjectFileMachO.h" +#include "Plugins/Platform/MacOSX/PlatformMacOSX.h" +#include "Plugins/Platform/MacOSX/PlatformRemoteMacOSX.h" #include "TestingSupport/SubsystemRAII.h" #include "TestingSupport/TestUtilities.h" #include "lldb/Core/Module.h" #include "lldb/Host/FileSystem.h" +#include "lldb/Host/HostInfo.h" #include "lldb/lldb-defines.h" #include "gtest/gtest.h" @@ -19,6 +21,7 @@ #include #endif +using namespace lldb; using namespace lldb_private; using namespace llvm; @@ -30,12 +33,16 @@ class ObjectFileMachOTest : public ::testing::Test { #if defined(__APPLE__) TEST_F(ObjectFileMachOTest, ModuleFromSharedCacheInfo) { + ArchSpec arch("arm64-apple-macosx-"); + + Platform::SetHostPlatform(PlatformRemoteMacOSX::CreateInstance(true, &arch)); + SharedCacheImageInfo image_info = HostInfo::GetSharedCacheImageInfo("/usr/lib/libobjc.A.dylib"); - EXPECT_TRUE(image_info.uuid); - EXPECT_TRUE(image_info.extractor_sp); + EXPECT_TRUE(image_info.GetUUID()); + EXPECT_TRUE(image_info.GetExtractor()); - ModuleSpec spec(FileSpec(), UUID(), image_info.extractor_sp); + ModuleSpec spec(FileSpec(), UUID(), image_info.GetExtractor()); lldb::ModuleSP module = std::make_shared(spec); ObjectFile *OF = module->GetObjectFile(); ASSERT_TRUE(llvm::isa(OF)); @@ -74,13 +81,13 @@ TEST_F(ObjectFileMachOTest, ModuleFromSharedCacheInfo) { // Read a symbol from the __TEXT segment... check_symbol("objc_msgSend"); // ... and one from the __DATA segment - check_symbol("OBJC_CLASS_$_NSObject"); + check_symbol("OBJC_IVAR_$_NSObject.isa"); } TEST_F(ObjectFileMachOTest, IndirectSymbolsInTheSharedCache) { SharedCacheImageInfo image_info = HostInfo::GetSharedCacheImageInfo( "/System/Library/Frameworks/AppKit.framework/Versions/C/AppKit"); - ModuleSpec spec(FileSpec(), UUID(), image_info.extractor_sp); + ModuleSpec spec(FileSpec(), UUID(), image_info.GetExtractor()); lldb::ModuleSP module = std::make_shared(spec); ObjectFile *OF = module->GetObjectFile(); diff --git a/lldb/unittests/Process/Utility/RegisterContextFreeBSDTest.cpp b/lldb/unittests/Process/Utility/RegisterContextFreeBSDTest.cpp index e541a34e6e22a..a74d27dd8d964 100644 --- a/lldb/unittests/Process/Utility/RegisterContextFreeBSDTest.cpp +++ b/lldb/unittests/Process/Utility/RegisterContextFreeBSDTest.cpp @@ -18,7 +18,6 @@ #include "gtest/gtest.h" #include "Plugins/Process/Utility/RegisterContextFreeBSD_i386.h" -#include "Plugins/Process/Utility/RegisterContextFreeBSD_mips64.h" #include "Plugins/Process/Utility/RegisterContextFreeBSD_powerpc.h" #include "Plugins/Process/Utility/RegisterContextFreeBSD_x86_64.h" #include "Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h" @@ -26,7 +25,6 @@ #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" #include "Plugins/Process/Utility/lldb-arm-register-enums.h" #include "Plugins/Process/Utility/lldb-arm64-register-enums.h" -#include "Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h" #include "Plugins/Process/Utility/lldb-x86-register-enums.h" using namespace lldb; @@ -404,73 +402,6 @@ TEST(RegisterContextFreeBSDTest, arm64) { #endif // defined(__aarch64__) -#if defined(__mips64__) - -#define EXPECT_GPR_MIPS64(lldb_reg, fbsd_regno) \ - EXPECT_THAT(GetRegParams(reg_ctx, gpr_##lldb_reg##_mips64), \ - ::testing::Pair(offsetof(reg, r_regs[fbsd_regno]), \ - sizeof(reg::r_regs[fbsd_regno]))) -#define EXPECT_FPU_MIPS64(lldb_reg, fbsd_regno) \ - EXPECT_THAT( \ - GetRegParams(reg_ctx, fpr_##lldb_reg##_mips64), \ - ::testing::Pair(offsetof(fpreg, r_regs[fbsd_regno]) + base_offset, \ - sizeof(fpreg::r_regs[fbsd_regno]))) - -TEST(RegisterContextFreeBSDTest, mips64) { - ArchSpec arch{"mips64-unknown-freebsd"}; - RegisterContextFreeBSD_mips64 reg_ctx{arch}; - - // we can not use aliases from because macros defined - // there are not namespaced and collide a lot, e.g. 'A1' - - EXPECT_GPR_MIPS64(zero, 0); - EXPECT_GPR_MIPS64(r1, 1); - EXPECT_GPR_MIPS64(r2, 2); - EXPECT_GPR_MIPS64(r3, 3); - EXPECT_GPR_MIPS64(r4, 4); - EXPECT_GPR_MIPS64(r5, 5); - EXPECT_GPR_MIPS64(r6, 6); - EXPECT_GPR_MIPS64(r7, 7); - EXPECT_GPR_MIPS64(r8, 8); - EXPECT_GPR_MIPS64(r9, 9); - EXPECT_GPR_MIPS64(r10, 10); - EXPECT_GPR_MIPS64(r11, 11); - EXPECT_GPR_MIPS64(r12, 12); - EXPECT_GPR_MIPS64(r13, 13); - EXPECT_GPR_MIPS64(r14, 14); - EXPECT_GPR_MIPS64(r15, 15); - EXPECT_GPR_MIPS64(r16, 16); - EXPECT_GPR_MIPS64(r17, 17); - EXPECT_GPR_MIPS64(r18, 18); - EXPECT_GPR_MIPS64(r19, 19); - EXPECT_GPR_MIPS64(r20, 20); - EXPECT_GPR_MIPS64(r21, 21); - EXPECT_GPR_MIPS64(r22, 22); - EXPECT_GPR_MIPS64(r23, 23); - EXPECT_GPR_MIPS64(r24, 24); - EXPECT_GPR_MIPS64(r25, 25); - EXPECT_GPR_MIPS64(r26, 26); - EXPECT_GPR_MIPS64(r27, 27); - EXPECT_GPR_MIPS64(gp, 28); - EXPECT_GPR_MIPS64(sp, 29); - EXPECT_GPR_MIPS64(r30, 30); - EXPECT_GPR_MIPS64(ra, 31); - EXPECT_GPR_MIPS64(sr, 32); - EXPECT_GPR_MIPS64(mullo, 33); - EXPECT_GPR_MIPS64(mulhi, 34); - EXPECT_GPR_MIPS64(badvaddr, 35); - EXPECT_GPR_MIPS64(cause, 36); - EXPECT_GPR_MIPS64(pc, 37); - EXPECT_GPR_MIPS64(ic, 38); - EXPECT_GPR_MIPS64(dummy, 39); - - size_t base_offset = reg_ctx.GetRegisterInfo()[fpr_f0_mips64].byte_offset; - - EXPECT_FPU_MIPS64(f0, 0); -} - -#endif // defined(__mips64__) - #if defined(__powerpc__) #define EXPECT_GPR_PPC(lldb_reg, fbsd_reg) \ diff --git a/lldb/unittests/Protocol/ProtocolMCPServerTest.cpp b/lldb/unittests/Protocol/ProtocolMCPServerTest.cpp index 97f32e2fbb1bf..9a5b75edeeb9d 100644 --- a/lldb/unittests/Protocol/ProtocolMCPServerTest.cpp +++ b/lldb/unittests/Protocol/ProtocolMCPServerTest.cpp @@ -157,22 +157,18 @@ class ProtocolServerMCPTest : public testing::Test { } void SetUp() override { - std::tie(to_client, to_server) = Transport::createPair(); + std::tie(to_client, to_server) = Transport::createPair(loop); server_up = std::make_unique( "lldb-mcp", "0.1.0", [this](StringRef msg) { logged_messages.push_back(msg.str()); }); binder = server_up->Bind(*to_client); - auto server_handle = to_server->RegisterMessageHandler(loop, *binder); - EXPECT_THAT_EXPECTED(server_handle, Succeeded()); binder->OnError([](llvm::Error error) { llvm::errs() << formatv("Server transport error: {0}", error); }); - handles[0] = std::move(*server_handle); - auto client_handle = to_client->RegisterMessageHandler(loop, client); - EXPECT_THAT_EXPECTED(client_handle, Succeeded()); - handles[1] = std::move(*client_handle); + EXPECT_THAT_ERROR(to_server->RegisterMessageHandler(*binder), Succeeded()); + EXPECT_THAT_ERROR(to_client->RegisterMessageHandler(client), Succeeded()); } template diff --git a/lldb/unittests/Symbol/TestTypeSystemClang.cpp b/lldb/unittests/Symbol/TestTypeSystemClang.cpp index c3290e0616c89..b88f14d2062f0 100644 --- a/lldb/unittests/Symbol/TestTypeSystemClang.cpp +++ b/lldb/unittests/Symbol/TestTypeSystemClang.cpp @@ -1350,6 +1350,71 @@ TEST_F(TestTypeSystemClang, TestGetTypeInfo) { (eTypeIsFloat | eTypeIsVector | eTypeHasChildren)); } +TEST_F(TestTypeSystemClang, TestIsRealFloatingPointType) { + // Tests CompilerType::IsRealFloatingPointType + + const ASTContext &ast = m_ast->getASTContext(); + + EXPECT_FALSE(m_ast->GetType(ast.getComplexType(ast.FloatTy)) + .IsRealFloatingPointType()); + EXPECT_FALSE( + m_ast->GetType(ast.getVectorType(ast.FloatTy, 1, VectorKind::Generic)) + .IsRealFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.HalfTy).IsRealFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.FloatTy).IsRealFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.DoubleTy).IsRealFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.LongDoubleTy).IsRealFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.Float128Ty).IsRealFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.BFloat16Ty).IsRealFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.Ibm128Ty).IsRealFloatingPointType()); +} + +TEST_F(TestTypeSystemClang, TestIsFloatingPointType) { + // Tests CompilerType::IsFloatingPointType + + const ASTContext &ast = m_ast->getASTContext(); + + // Vectors of floats + EXPECT_FALSE( + m_ast->GetType(ast.getVectorType(ast.FloatTy, 1, VectorKind::Generic)) + .IsFloatingPointType()); + EXPECT_FALSE( + m_ast->GetType(ast.getVectorType(ast.DoubleTy, 1, VectorKind::Generic)) + .IsFloatingPointType()); + + // Complex floats + EXPECT_TRUE( + m_ast->GetType(ast.getComplexType(ast.FloatTy)).IsFloatingPointType()); + EXPECT_TRUE( + m_ast->GetType(ast.getComplexType(ast.DoubleTy)).IsFloatingPointType()); + EXPECT_FALSE( + m_ast->GetType(ast.getComplexType(ast.IntTy)).IsFloatingPointType()); + + // Builtin floats + EXPECT_TRUE(m_ast->GetType(ast.HalfTy).IsFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.FloatTy).IsFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.DoubleTy).IsFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.LongDoubleTy).IsFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.Float128Ty).IsFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.BFloat16Ty).IsFloatingPointType()); + EXPECT_TRUE(m_ast->GetType(ast.Ibm128Ty).IsFloatingPointType()); +} + +TEST_F(TestTypeSystemClang, TestGetIsComplexType) { + // Tests CompilerType::IsComplexType + + const ASTContext &ast = m_ast->getASTContext(); + + EXPECT_TRUE(m_ast->GetType(ast.getComplexType(ast.IntTy)).IsComplexType()); + EXPECT_TRUE(m_ast->GetType(ast.getComplexType(ast.FloatTy)).IsComplexType()); + EXPECT_TRUE(m_ast->GetType(ast.getComplexType(ast.VoidTy)).IsComplexType()); + EXPECT_FALSE(m_ast + ->GetType(ast.getIncompleteArrayType( + ast.getComplexType(ast.FloatTy), /*ASM=*/{}, + /*IndexTypeQuals=*/{})) + .IsComplexType()); +} + TEST_F(TestTypeSystemClang, AsmLabel_CtorDtor) { // Tests TypeSystemClang::DeclGetMangledName for constructors/destructors // with and without AsmLabels. diff --git a/lldb/unittests/TestingSupport/Host/JSONTransportTestUtilities.h b/lldb/unittests/TestingSupport/Host/JSONTransportTestUtilities.h index bacf8ca36aa07..4623c365c960f 100644 --- a/lldb/unittests/TestingSupport/Host/JSONTransportTestUtilities.h +++ b/lldb/unittests/TestingSupport/Host/JSONTransportTestUtilities.h @@ -30,72 +30,51 @@ class TestTransport final static std::pair>, std::unique_ptr>> - createPair() { + createPair(lldb_private::MainLoop &loop) { std::unique_ptr> transports[2] = { - std::make_unique>(), - std::make_unique>()}; + std::make_unique>(loop), + std::make_unique>(loop)}; return std::make_pair(std::move(transports[0]), std::move(transports[1])); } - explicit TestTransport() { - llvm::Expected dummy_file = - lldb_private::FileSystem::Instance().Open( - lldb_private::FileSpec(lldb_private::FileSystem::DEV_NULL), - lldb_private::File::eOpenOptionReadWrite); - EXPECT_THAT_EXPECTED(dummy_file, llvm::Succeeded()); - m_dummy_file = std::move(*dummy_file); - } + explicit TestTransport(lldb_private::MainLoop &loop) : m_loop(loop) {} llvm::Error Send(const typename Proto::Evt &evt) override { - EXPECT_TRUE(m_loop && m_handler) - << "Send called before RegisterMessageHandler"; - m_loop->AddPendingCallback([this, evt](lldb_private::MainLoopBase &) { + EXPECT_TRUE(m_handler) << "Send called before RegisterMessageHandler"; + m_loop.AddPendingCallback([this, evt](lldb_private::MainLoopBase &) { m_handler->Received(evt); }); return llvm::Error::success(); } llvm::Error Send(const typename Proto::Req &req) override { - EXPECT_TRUE(m_loop && m_handler) - << "Send called before RegisterMessageHandler"; - m_loop->AddPendingCallback([this, req](lldb_private::MainLoopBase &) { + EXPECT_TRUE(m_handler) << "Send called before RegisterMessageHandler"; + m_loop.AddPendingCallback([this, req](lldb_private::MainLoopBase &) { m_handler->Received(req); }); return llvm::Error::success(); } llvm::Error Send(const typename Proto::Resp &resp) override { - EXPECT_TRUE(m_loop && m_handler) - << "Send called before RegisterMessageHandler"; - m_loop->AddPendingCallback([this, resp](lldb_private::MainLoopBase &) { + EXPECT_TRUE(m_handler) << "Send called before RegisterMessageHandler"; + m_loop.AddPendingCallback([this, resp](lldb_private::MainLoopBase &) { m_handler->Received(resp); }); return llvm::Error::success(); } - llvm::Expected - RegisterMessageHandler(lldb_private::MainLoop &loop, - MessageHandler &handler) override { - if (!m_loop) - m_loop = &loop; + llvm::Error RegisterMessageHandler(MessageHandler &handler) override { if (!m_handler) m_handler = &handler; - lldb_private::Status status; - auto handle = loop.RegisterReadObject( - m_dummy_file, [](lldb_private::MainLoopBase &) {}, status); - if (status.Fail()) - return status.takeError(); - return handle; + return llvm::Error::success(); } protected: void Log(llvm::StringRef message) override {}; private: - lldb_private::MainLoop *m_loop = nullptr; + lldb_private::MainLoop &m_loop; MessageHandler *m_handler = nullptr; - // Dummy file for registering with the MainLoop. - lldb::FileSP m_dummy_file = nullptr; }; template diff --git a/lldb/unittests/Utility/VirtualDataExtractorTest.cpp b/lldb/unittests/Utility/VirtualDataExtractorTest.cpp index 4ebe1429a78f8..5a1ec9d6332de 100644 --- a/lldb/unittests/Utility/VirtualDataExtractorTest.cpp +++ b/lldb/unittests/Utility/VirtualDataExtractorTest.cpp @@ -652,4 +652,12 @@ TEST(VirtualDataExtractorTest, SubsetExtractorGetU32) { lldb::DataExtractorSP middle_contiguous_subset = extractor->GetSubsetExtractorSP(4 * sizeof(uint32_t)); EXPECT_EQ(middle_contiguous_subset->GetByteSize(), 4 * sizeof(uint32_t)); + + // Set the data source of extractor to its current data source + // with offset 0 and same size -- this should be a no-op. + extractor->SetData(extractor->GetSharedDataBuffer(), 0, + extractor->GetByteSize()); + virtual_offset = 0; + // Entry(0x0, 4*sizeof(uint32_t), 12*sizeof(uint32_t)) + EXPECT_EQ(extractor->GetU32(&virtual_offset), 0xccccccccU); } diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index be028c1dab1f5..2e2c269c0abbc 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -104,14 +104,13 @@ endif() # This allows an easy way of setting up a build directory for llvm and another # one for llvm+clang+... using the same sources. # These projects will be included when "all" is included in LLVM_ENABLE_PROJECTS. -set(LLVM_ALL_PROJECTS "bolt;clang;clang-tools-extra;compiler-rt;cross-project-tests;libclc;lld;lldb;mlir;polly") +set(LLVM_ALL_PROJECTS "bolt;clang;clang-tools-extra;cross-project-tests;lld;lldb;mlir;polly") -# The "libc" project, which is not part of "all" projects, could be included in -# LLVM_ENABLE_PROJECTS. It is preferred to include "libc" in -# LLVM_ENABLE_RUNTIMES instead of LLVM_ENABLE_PROJECTS. +# The libc and compiler-rt projects are not part of LLVM_ALL_PROJECTS, because +# it is preferred to use LLVM_ENABLE_RUNTIMES for them instead. # # The flang project is not yet part of "all" projects (see C++ requirements). -set(LLVM_EXTRA_PROJECTS "flang" "libc") +set(LLVM_EXTRA_PROJECTS "flang" "libc" "compiler-rt") # List of all known projects in the mono repo set(LLVM_KNOWN_PROJECTS "${LLVM_ALL_PROJECTS};${LLVM_EXTRA_PROJECTS}") set(LLVM_ENABLE_PROJECTS "" CACHE STRING @@ -140,7 +139,7 @@ endforeach() # # As we migrate runtimes to using the bootstrapping build, the set of default runtimes # should grow as we remove those runtimes from LLVM_ENABLE_PROJECTS above. -set(LLVM_DEFAULT_RUNTIMES "libcxx;libcxxabi;libunwind") +set(LLVM_DEFAULT_RUNTIMES "libcxx;libcxxabi;libunwind;libclc;compiler-rt;openmp") set(LLVM_SUPPORTED_RUNTIMES "libc;libunwind;libcxxabi;libcxx;compiler-rt;openmp;llvm-libgcc;offload;flang-rt;libclc;libsycl;orc-rt") set(LLVM_ENABLE_RUNTIMES "" CACHE STRING "Semicolon-separated list of runtimes to build, or \"all\" (${LLVM_DEFAULT_RUNTIMES}). Supported runtimes are ${LLVM_SUPPORTED_RUNTIMES}.") diff --git a/llvm/Maintainers.md b/llvm/Maintainers.md index 0aa2c63d9f58c..f691dc0777eda 100644 --- a/llvm/Maintainers.md +++ b/llvm/Maintainers.md @@ -186,7 +186,7 @@ i@maskray.me (email), [MaskRay](https://github.com/MaskRay) (GitHub) #### Windows ABI and codegen Reid Kleckner \ -rnk@google.com (email), [rnk](https://github.com/rnk) (GitHub) +rnk@llvm.org (email), [rnk](https://github.com/rnk) (GitHub) ### Backends / Targets @@ -484,7 +484,7 @@ echristo@gmail.com (email), [echristo](https://github.com/echristo) (GitHub) #### Exception handling Reid Kleckner \ -rnk@google.com (email), [rnk](https://github.com/rnk) (GitHub) +rnk@llvm.org (email), [rnk](https://github.com/rnk) (GitHub) #### LLVM Buildbot diff --git a/llvm/cmake/modules/TableGen.cmake b/llvm/cmake/modules/TableGen.cmake index 84c03cd6432ed..1bac44c70d2c8 100644 --- a/llvm/cmake/modules/TableGen.cmake +++ b/llvm/cmake/modules/TableGen.cmake @@ -24,6 +24,14 @@ function(tablegen project ofn) # Filter out any empty include items. list(REMOVE_ITEM tblgen_includes "") + # Check for multi-output tablegen invocations BEFORE deciding on depfile mode. + # Ninja's depslog cannot handle multiple outputs with depfile, so we must use + # fallback mode (globbing) for these cases. + set(has_extra_outputs FALSE) + if("-gen-register-info" IN_LIST ARGN) + set(has_extra_outputs TRUE) + endif() + # Use depfile instead of globbing arbitrary *.td(s) for Ninja. We force # CMake versions older than v3.30 on Windows to use the fallback behavior # due to a depfile parsing bug on Windows paths in versions prior to 3.30. @@ -32,10 +40,28 @@ function(tablegen project ofn) # behavior as v3.22 and earlier fail to parse some depfiles that get # generated, and this behavior was fixed in CMake commit # e04a352cca523eba2ac0d60063a3799f5bb1c69e. + # CRITICAL: Ninja <1.10 has a depslog limitation: it cannot handle depfile + # mode when CMake generates implicit outputs (absolute path aliases for IDE + # support). For multi-output rules OR when using Ninja <1.10, we MUST use + # fallback mode (glob .td files) to avoid "multiple outputs aren't supported + # by depslog" errors. cmake_policy(GET CMP0116 cmp0116_state) + + # Check Ninja version to avoid depslog errors with implicit outputs + set(ninja_version_supports_depfile TRUE) + if(CMAKE_GENERATOR MATCHES "Ninja") + execute_process(COMMAND ${CMAKE_MAKE_PROGRAM} --version + OUTPUT_VARIABLE ninja_version + OUTPUT_STRIP_TRAILING_WHITESPACE) + if(ninja_version VERSION_LESS "1.10") + set(ninja_version_supports_depfile FALSE) + endif() + endif() if(CMAKE_GENERATOR MATCHES "Ninja" AND cmp0116_state STREQUAL NEW AND NOT (CMAKE_HOST_WIN32 AND CMAKE_VERSION VERSION_LESS 3.30) - AND NOT (CMAKE_VERSION VERSION_LESS 3.23)) + AND NOT (CMAKE_VERSION VERSION_LESS 3.23) + AND NOT has_extra_outputs + AND ninja_version_supports_depfile) # CMake emits build targets as relative paths but Ninja doesn't identify # absolute path (in *.d) as relative path (in build.ninja). Post CMP0116, # CMake handles this discrepancy for us, otherwise we use the fallback @@ -128,7 +154,7 @@ function(tablegen project ofn) # ("${${project}_TABLEGEN_TARGET}" STREQUAL "${${project}_TABLEGEN_EXE}") # but lets us having smaller and cleaner code here. set(tablegen_exe ${${project}_TABLEGEN_EXE}) - set(tablegen_depends ${${project}_TABLEGEN_TARGET} ${tablegen_exe}) + set(tablegen_target ${${project}_TABLEGEN_TARGET}) if(LLVM_PARALLEL_TABLEGEN_JOBS) set(LLVM_TABLEGEN_JOB_POOL JOB_POOL tablegen_job_pool) @@ -136,6 +162,20 @@ function(tablegen project ofn) set(LLVM_TABLEGEN_JOB_POOL "") endif() + # For Ninja with multiple outputs, we cannot add the target to DEPENDS due to + # depslog limitations. Instead, rely on the implicit tool dependency from COMMAND + # and the globbed .td files for proper dependency tracking. + # For single outputs or non-Ninja generators, include the target in DEPENDS. + set(tablegen_target_dep) + if(NOT EXTRA_OUTPUTS) + # Single output: safe to add explicit target dependency + set(tablegen_target_dep ${tablegen_target}) + elseif(NOT CMAKE_GENERATOR MATCHES "Ninja") + # Multiple outputs but not Ninja: Ninja's depslog is not a constraint + set(tablegen_target_dep ${tablegen_target}) + endif() + # Multiple outputs + Ninja: Don't add target dependency; rely on COMMAND implicit tracking + add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ofn} ${EXTRA_OUTPUTS} COMMAND ${tablegen_exe} ${ARG_UNPARSED_ARGUMENTS} ${tblgen_includes} @@ -146,7 +186,7 @@ function(tablegen project ofn) # The file in LLVM_TARGET_DEFINITIONS may be not in the current # directory and local_tds may not contain it, so we must # explicitly list it here: - DEPENDS ${ARG_DEPENDS} ${tablegen_depends} + DEPENDS ${ARG_DEPENDS} ${tablegen_target_dep} ${global_tds} ${LLVM_TARGET_DEFINITIONS_ABSOLUTE} ${LLVM_TARGET_DEPENDS} diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index cd5410a31b98f..c7d66a38a4e11 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -486,7 +486,7 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following work-item Add product IDs names. - **GCN GFX11 (RDNA 3.5)** [AMD-GCN-GFX11-RDNA3.5]_ + **GCN GFX11.5 (RDNA 3.5)** [AMD-GCN-GFX11-RDNA3.5]_ ----------------------------------------------------------------------------------------------------------------------- ``gfx1150`` ``amdgcn`` APU - cumode - Architected Radeon 890M - wavefrontsize64 flat @@ -516,6 +516,15 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following work-item Add product IDs names. + **GCN GFX11.7 (RDNA 4m)** + ----------------------------------------------------------------------------------------------------------------------- + ``gfx1170`` ``amdgcn`` APU - cumode - Architected *TBA* + - wavefrontsize64 flat + scratch .. TODO:: + - Packed + work-item Add product + IDs names. + **GCN GFX12 (RDNA 4)** [AMD-GCN-GFX12-RDNA4]_ ----------------------------------------------------------------------------------------------------------------------- ``gfx1200`` ``amdgcn`` dGPU - cumode - Architected - Radeon RX 9060 @@ -1678,7 +1687,6 @@ The AMDGPU backend implements the following LLVM IR intrinsics. Instruction cache prefetches are unsafe on invalid address. - llvm.amdgcn.s.barrier Performs a barrier *signal* operation immediately followed by a barrier *wait* operation on the *workgroup barrier* object. see :ref:`amdgpu-amdhsa-execution-barriers`. @@ -1691,6 +1699,32 @@ The AMDGPU backend implements the following LLVM IR intrinsics. See :ref:`amdgpu-amdhsa-execution-barriers`. Available starting GFX12. + llvm.amdgcn.flat.load.monitor Available on GFX12.5 only. + Corresponds to ``flat_load_monitor_b32/64/128`` (``.b32/64/128`` suffixes) + instructions. + For the purposes of the memory model, this is an atomic load operation in + the generic (flat) address space. + + This intrinsic has 3 operands: + + * Flat pointer. + * :ref:`Load Atomic Ordering`. + * :ref:`Synchronization Scope`. + Note that the scope used must ensure that the L2 cache will be hit. + + llvm.amdgcn.global.load.monitor Available on GFX12.5 only. + Corresponds to ``global_load_monitor_b32/64/128`` (``.b32/64/128`` suffixes) + instructions. + For the purposes of the memory model, this is an atomic load operation in + the global address space. + + This intrinsic has 3 operands: + + * Flat pointer. + * :ref:`Load Atomic Ordering`. + * :ref:`Synchronization Scope`. + Note that the scope used must ensure that the L2 cache will be hit. + ============================================== ========================================================== .. TODO:: @@ -1756,28 +1790,64 @@ then this intrinsic causes undefined behavior. The intrinsics are available for the global (``.p1`` suffix) and generic (``.p0`` suffix) address spaces. -The atomic ordering operand (3rd operand for ``.store``, 2nd for ``.load``) is an integer that follows the -C ABI encoding of atomic memory orderings. The supported values are in -:ref:`the table below`. +The 3rd operand for ``.store`` or 2nd for ``.load`` intrinsics is the +:ref:`atomic ordering` of the operation. + +The last operand of the intrinsic is the +:ref:`synchronization scope` of the operation. + +Intrinsic Operands +~~~~~~~~~~~~~~~~~~ + +.. _amdgpu-intrinsics-c-abi-atomic-memory-ordering-operand: + +C ABI Atomic Ordering Operand ++++++++++++++++++++++++++++++ + +Intrinsic operands in this format are always ``i32`` integer constants whose value is +determined by the C ABI encoding of atomic memory orderings. The supported values are in +:ref:`the table below`. + + .. table:: AMDGPU Intrinsics C ABI Atomic Memory Ordering Values + :name: amdgpu-intrinsics-c-abi-atomic-memory-orderings-table - .. table:: AMDGPU Cooperative Atomic Intrinsics Atomic Memory Orderings - :name: amdgpu-cooperative-atomic-intrinsics-atomic-memory-orderings-table + ========= ================ ================================= + Value Atomic Memory Notes + Ordering + ========= ================ ================================= + ``i32 0`` ``relaxed`` The default for unsupported values. - ====== ================ ================================= - Value Atomic Memory Notes - Ordering - ====== ================ ================================= - ``0`` ``relaxed`` The default for unsupported values. + ``i32 2`` ``acquire`` Only for loads. - ``2`` ``acquire`` Only for ``.load`` + ``i32 3`` ``release`` Only for stores. - ``3`` ``release`` Only for ``.store`` + ``i32 5`` ``seq_cst`` + ========= ================ ================================= - ``5`` ``seq_cst`` - ====== ================ ================================= +Example: -The last argument of the intrinsic is the synchronization scope -as a metadata string, which must be one of the supported :ref:`memory scopes`. +.. code:: + + ; "i32 5" is the atomic ordering operand + %0 = tail call i32 @llvm.amdgcn.cooperative.atomic.load.32x4B.p0(ptr %addr, i32 5, metadata !0) + +.. _amdgpu-intrinsics-syncscope-metadata-operand: + +Syncscope Metadata Operand +++++++++++++++++++++++++++ + +Intrinsics operand in this format are metadata strings which must be one of the supported +:ref:`memory scopes`. +The metadata node must be made of a single ``MDString`` at the top level. + +Example: + +.. code:: + + ; "metadata !0" is the syncscope metadata operand. + %0 = tail call i32 @llvm.amdgcn.cooperative.atomic.load.32x4B.p0(ptr %addr, i32 4, metadata !0) + + !0 = !{ !"agent" } .. _amdgpu_metadata: @@ -2671,6 +2741,7 @@ The AMDGPU backend uses the following ELF header: ``EF_AMDGPU_MACH_AMDGCN_GFX1153`` 0x058 ``gfx1153``. ``EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC`` 0x059 ``gfx12-generic`` ``EF_AMDGPU_MACH_AMDGCN_GFX1251`` 0x05a ``gfx1251`` + ``EF_AMDGPU_MACH_AMDGCN_GFX1170`` 0x05d ``gfx1170`` ``EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC`` 0x05f ``gfx9-4-generic`` ========================================== ========== ============================= @@ -5726,7 +5797,7 @@ The fields used by CP for code objects before V3 also match those specified in CP is responsible for filling in ``COMPUTE_PGM_RSRC1.DEBUG_MODE``. - 23 1 bit ENABLE_IEEE_MODE GFX9-GFX11 + 23 1 bit ENABLE_IEEE_MODE GFX9-GFX11 (except GFX1170) Wavefront starts execution with IEEE mode enabled. Floating point @@ -5742,6 +5813,8 @@ The fields used by CP for code objects before V3 also match those specified in Used by CP to set up ``COMPUTE_PGM_RSRC1.IEEE_MODE``. + GFX1170 + Reserved. Must be 0. DISABLE_PERF GFX12 Reserved. Must be 0. 24 1 bit BULKY Must be 0. @@ -17246,7 +17319,7 @@ For GFX125x: This section is currently incomplete as work on the compiler is still ongoing. The following is a non-exhaustive list of unimplemented/undocumented features: - non-volatile bit code sequences, monitor and wait, globally accessing scratch atomics, + non-volatile bit code sequences, globally accessing scratch atomics, multicast loads, barriers (including split barriers) and cooperative atomics. Scalar operations memory model needs more elaboration as well. @@ -17347,6 +17420,17 @@ For GFX125x: issued to every address at the same time. They are kept in order with other memory operations from the same wave. +* ``global_load_monitor_*`` and ``flat_load_monitor_*`` instructions load + data and request that the wave is notified (see ``s_monitor_sleep``) if + the L2 cache line that holds the data is evicted, or written to. + + * In order to monitor a cache line in the L2 cache, these instructions must + ensure that the L2 cache is always hit by setting the ``SCOPE`` of the instruction + appropriately. + * For non-atomic and atomic code sequences, it is valid to replace + ``global_load_b32/64/128`` with a ``global_load_monitor_b32/64/128`` and a + ``flat_load_b32/64/128`` with a ``flat_load_monitor_b32/64/128``. + Scalar memory operations are only used to access memory that is proven to not change during the execution of the kernel dispatch. This includes constant address space and global address space for program scope ``const`` variables. diff --git a/llvm/docs/CodingStandards.rst b/llvm/docs/CodingStandards.rst index 63f6663d687ea..593388db7ddf2 100644 --- a/llvm/docs/CodingStandards.rst +++ b/llvm/docs/CodingStandards.rst @@ -278,11 +278,23 @@ Use the ``\file`` command to turn the standard file header into a file-level comment. Include descriptive paragraphs for all public interfaces (public classes, -member and non-member functions). Avoid restating the information that can -be inferred from the API name. The first sentence (or a paragraph beginning -with ``\brief``) is used as an abstract. Try to use a single sentence as the -``\brief`` adds visual clutter. Put detailed discussion into separate -paragraphs. +member and non-member functions). Avoid restating the information that can be +inferred from the API name or signature. The first sentence (or a paragraph +beginning with ``\brief``) is used as an abstract. Try to use a single +sentence as the ``\brief`` adds visual clutter. Put detailed discussion into +separate paragraphs. + +A minimal documentation comment: + +.. code-block:: c++ + + /// Sets the xyzzy property to \p Baz. + void setXyzzy(bool Baz); + +Only include code examples, function parameters and return values when it +provides additional information, such as intent, usage, or behavior that’s +non-obvious. Use descriptive function and argument names to +eliminate the need for documentation comments when possible. To refer to parameter names inside a paragraph, use the ``\p name`` command. Don't use the ``\arg name`` command since it starts a new paragraph that @@ -298,13 +310,6 @@ respectively. To describe function return value, start a new paragraph with the ``\returns`` command. -A minimal documentation comment: - -.. code-block:: c++ - - /// Sets the xyzzy property to \p Baz. - void setXyzzy(bool Baz); - A documentation comment that uses all Doxygen features in a preferred way: .. code-block:: c++ diff --git a/llvm/docs/CommandGuide/llvm-objcopy.rst b/llvm/docs/CommandGuide/llvm-objcopy.rst index 343e1d8dbac90..9219a5a5852a8 100644 --- a/llvm/docs/CommandGuide/llvm-objcopy.rst +++ b/llvm/docs/CommandGuide/llvm-objcopy.rst @@ -251,6 +251,9 @@ multiple file formats. For COFF and Mach-O objects, remove all symbols, debug sections, and relocations from the output. + For WebAssembly objects, remove all custom sections except for those named + metadata.code.*. + .. option:: --strip-debug, -g Remove all debug sections from the output. diff --git a/llvm/docs/CommandGuide/llvm-readelf.rst b/llvm/docs/CommandGuide/llvm-readelf.rst index 5fd635778b63c..6b3b1da990b91 100644 --- a/llvm/docs/CommandGuide/llvm-readelf.rst +++ b/llvm/docs/CommandGuide/llvm-readelf.rst @@ -20,15 +20,15 @@ input. Otherwise, it will read from the specified ``filenames``. OPTIONS ------- -.. option:: --all, -a - - Equivalent to specifying all the main display options relevant to the file - format. - .. option:: --addrsig Display the address-significance table. + .. option:: --all, -a + + Equivalent to specifying all the main display options relevant to the file + format. + .. option:: --arch-specific, -A Display architecture-specific information, e.g. the ARM attributes section on ARM. @@ -55,6 +55,10 @@ OPTIONS Display the dependent libraries section. +.. option:: --dynamic-table, --dynamic, -d + + Display the dynamic table. + .. option:: --dyn-relocations Display the dynamic relocation entries. @@ -63,14 +67,6 @@ OPTIONS Display the dynamic symbol table. -.. option:: --dynamic-table, --dynamic, -d - - Display the dynamic table. - -.. option:: --histogram, -I - - Display a bucket list histogram for dynamic symbol hash tables. - .. option:: --elf-linker-options Display the linker options section. @@ -86,10 +82,6 @@ OPTIONS Display extra information (section name) when showing symbols. -.. option:: --section-groups, -g - - Display section groups. - .. option:: --expand-relocs When used with :option:`--relocations`, display each relocation in an expanded @@ -125,6 +117,10 @@ OPTIONS Display the specified section(s) as hexadecimal bytes. ``section`` may be a section index or section name. +.. option:: --histogram, -I + + Display a bucket list histogram for dynamic symbol hash tables. + .. option:: --memtag Display information about memory tagging present in the binary. This includes @@ -160,10 +156,6 @@ OPTIONS Display the relocation entries in the file. -.. option:: --sections, --section-headers, -S - - Display all sections. - .. option:: --section-data When used with :option:`--sections`, display section data for each section @@ -173,6 +165,10 @@ OPTIONS Display all section details. Used as an alternative to :option:`--sections`. +.. option:: --section-groups, -g + + Display section groups. + .. option:: --section-mapping Display the section to segment mapping. @@ -182,6 +178,10 @@ OPTIONS When used with :option:`--sections`, display relocations for each section shown. This option has no effect for GNU style output. +.. option:: --sections, --section-headers, -S + + Display all sections. + .. option:: --section-symbols When used with :option:`--sections`, display symbols for each section shown. diff --git a/llvm/docs/CommandGuide/llvm-readobj.rst b/llvm/docs/CommandGuide/llvm-readobj.rst index f3afd9c7c9648..183d9251a7ac2 100644 --- a/llvm/docs/CommandGuide/llvm-readobj.rst +++ b/llvm/docs/CommandGuide/llvm-readobj.rst @@ -47,15 +47,15 @@ GENERAL AND MULTI-FORMAT OPTIONS These options are applicable to more than one file format, or are unrelated to file formats. +.. option:: --addrsig + + Display the address-significance table. + .. option:: --all Equivalent to specifying all the main display options relevant to the file format. -.. option:: --addrsig - - Display the address-significance table. - .. option:: --decompress, -z Dump decompressed section content when used with ``-x`` or ``-p``. @@ -89,12 +89,6 @@ file formats. Display the specified section(s) as hexadecimal bytes. ``section`` may be a section index or section name. - .. option:: --memtag - - Display information about memory tagging present in the binary. This includes - various memtag-specific dynamic entries, decoded global descriptor sections, - and decoded Android-specific ELF notes. - .. option:: --needed-libs Display the needed libraries. @@ -112,10 +106,6 @@ file formats. Display the relocation entries in the file. -.. option:: --sections, --section-headers, -S - - Display all sections. - .. option:: --section-data, --sd When used with :option:`--sections`, display section data for each section @@ -126,6 +116,10 @@ file formats. When used with :option:`--sections`, display relocations for each section shown. This option has no effect for GNU style output. +.. option:: --sections, --section-headers, -S + + Display all sections. + .. option:: --section-symbols, --st When used with :option:`--sections`, display symbols for each section shown. @@ -189,6 +183,10 @@ The following options are implemented only for the ELF file format. Display the dependent libraries section. +.. option:: --dynamic-table, --dynamic, -d + + Display the dynamic table. + .. option:: --dyn-relocations Display the dynamic relocation entries. @@ -197,10 +195,6 @@ The following options are implemented only for the ELF file format. Display the dynamic symbol table. -.. option:: --dynamic-table, --dynamic, -d - - Display the dynamic table. - .. option:: --elf-linker-options Display the linker options section. @@ -331,10 +325,6 @@ The following options are implemented only for the PE/COFF file format. Display the debug directory. -.. option:: --coff-tls-directory - - Display the TLS directory. - .. option:: --coff-directives Display the .drectve section. @@ -355,6 +345,10 @@ The following options are implemented only for the PE/COFF file format. Display the .rsrc section. +.. option:: --coff-tls-directory + + Display the TLS directory. + XCOFF SPECIFIC OPTIONS ---------------------- @@ -372,14 +366,14 @@ The following options are implemented only for the XCOFF file format. Display XCOFF loader section header. -.. option:: --loader-section-symbols - - Display symbol table of loader section. - .. option:: --loader-section-relocations Display relocation entries of loader section. +.. option:: --loader-section-symbols + + Display symbol table of loader section. + EXIT STATUS ----------- diff --git a/llvm/docs/CommandGuide/llvm-strip.rst b/llvm/docs/CommandGuide/llvm-strip.rst index 9fd705237d2cc..a870e210dfea0 100644 --- a/llvm/docs/CommandGuide/llvm-strip.rst +++ b/llvm/docs/CommandGuide/llvm-strip.rst @@ -90,8 +90,11 @@ multiple file formats. within segments, except for .gnu.warning, .ARM.attribute sections and the section name table. - For COFF objects, remove all symbols, debug sections, and relocations from the - output. + For COFF and Mach-O objects, remove all symbols, debug sections, and + relocations from the output. + + For WebAssembly objects, remove all custom sections except for those named + metadata.code.*. .. option:: --strip-debug, -d, -g, -S diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 9c3ffb396649b..28edd439b6900 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -1671,7 +1671,7 @@ Currently, only the following parameter attributes are defined: This does not depend on the floating-point environment. For example, a function parameter marked ``nofpclass(zero)`` indicates no zero inputs. If this is applied to an argument in a function - marked with :ref:`\"denormal-fp-math\" ` + marked with :ref:`denormal_fpenv ` indicating zero treatment of input denormals, it does not imply the value cannot be a denormal value which would compare equal to 0. @@ -2655,28 +2655,28 @@ For example: might otherwise be set or cleared by calling this function. LLVM will not introduce any new floating-point instructions that may trap. -.. _denormal_fp_math: +.. _denormal_fpenv: -``"denormal-fp-math"`` +``denormal_fpenv`` This indicates the denormal (subnormal) handling that may be - assumed for the default floating-point environment. This is a - comma separated pair. The elements may be one of ``"ieee"``, - ``"preserve-sign"``, ``"positive-zero"``, or ``"dynamic"``. The - first entry indicates the flushing mode for the result of floating - point operations. The second indicates the handling of denormal inputs + assumed for the default floating-point environment. The base form + is a ``|`` separated pair. The elements may be one of ``ieee``, + ``preservesign``, ``positivezero``, or ``dynamic``. The first + entry indicates the flushing mode for the result of floating point + operations. The second indicates the handling of denormal inputs to floating point instructions. For compatibility with older bitcode, if the second value is omitted, both input and output modes will assume the same mode. - If this is attribute is not specified, the default is ``"ieee,ieee"``. + If this is attribute is not specified, the default is ``ieee|ieee``. - If the output mode is ``"preserve-sign"``, or ``"positive-zero"``, + If the output mode is ``preservesign``, or ``positivezero``, denormal outputs may be flushed to zero by standard floating-point operations. It is not mandated that flushing to zero occurs, but if a denormal output is flushed to zero, it must respect the sign mode. Not all targets support all modes. - If the mode is ``"dynamic"``, the behavior is derived from the + If the mode is ``dynamic``, the behavior is derived from the dynamic state of the floating-point environment. Transformations which depend on the behavior of denormal values should not be performed. @@ -2686,20 +2686,31 @@ For example: the mode is consistent. User or platform code is expected to set the floating point mode appropriately before function entry. - If the input mode is ``"preserve-sign"``, or ``"positive-zero"``, + This may optionally specify a second pair, prefixed with + ``float:``. This provides an override for the behavior of 32-bit + float type (or vectors of 32-bit floats). + + If the input mode is ``preservesign``, or ``positivezero``, a floating-point operation must treat any input denormal value as zero. In some situations, if an instruction does not respect this mode, the input may need to be converted to 0 as if by ``@llvm.canonicalize`` during lowering for correctness. -``"denormal-fp-math-f32"`` - Same as ``"denormal-fp-math"``, but only controls the behavior of - the 32-bit float type (or vectors of 32-bit floats). If both are - are present, this overrides ``"denormal-fp-math"``. Not all targets - support separately setting the denormal mode per type, and no - attempt is made to diagnose unsupported uses. Currently this + This may optionally specify a second pair, prefixed with + ``float:``. This provides an override for the behavior of 32-bit + float type. (or vectors of 32-bit floats). If this is present, + this overrides the base handling of the default mode. Not all + targets support separately setting the denormal mode per type, and + no attempt is made to diagnose unsupported uses. Currently this attribute is respected by the AMDGPU and NVPTX backends. +:Examples: + ``denormal_fpenv(preservesign)`` + ``denormal_fpenv(float: preservesign)`` + ``denormal_fpenv(dynamic, float: preservesign|ieee)`` + ``denormal_fpenv(ieee|ieee, float: preservesign|preservesign)`` + ``denormal_fpenv(ieee|dynamic, float: preservesign|ieee)`` + ``"thunk"`` This attribute indicates that the function will delegate to some other function with a tail call. The prototype of a thunk should not be used for @@ -4013,10 +4024,11 @@ not have side effects and may be speculated freely. Results assume the round-to-nearest rounding mode, and subnormals are assumed to be preserved. Running LLVM code in an environment where these assumptions are not met -typically leads to undefined behavior. The ``strictfp`` and ``denormal-fp-math`` -attributes as well as :ref:`Constrained Floating-Point Intrinsics -` can be used to weaken LLVM's assumptions and ensure defined -behavior in non-default floating-point environments; see their respective +typically leads to undefined behavior. The ``strictfp`` and +:ref:`denormal_fpenv ` attributes as well as +:ref:`Constrained Floating-Point Intrinsics ` can be +used to weaken LLVM's assumptions and ensure defined behavior in +non-default floating-point environments; see their respective documentation for details. .. _floatnan: @@ -4119,7 +4131,7 @@ exceptions.) Various flags, attributes, and metadata can alter the behavior of these operations and thus make them not bit-identical across machines and optimization levels any more: most notably, the :ref:`fast-math flags ` as well as -the :ref:`strictfp ` and :ref:`denormal-fp-math ` +the :ref:`strictfp ` and :ref:`denormal_fpenv ` attributes and :ref:`!fpmath metadata `. See their corresponding documentation for details. @@ -12751,8 +12763,8 @@ Example: %X = uitofp i32 257 to float ; yields float:257.0 %Y = uitofp i8 -1 to double ; yields double:255.0 - %a = uitofp nneg i32 256 to i32 ; yields float:256.0 - %b = uitofp nneg i32 -256 to i32 ; yields i32 poison + %a = uitofp nneg i32 256 to float ; yields float:256.0 + %b = uitofp nneg i32 -256 to float ; yields float poison '``sitofp .. to``' Instruction ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -16373,10 +16385,10 @@ support all bit widths however. :: - declare void @llvm.memset.inline.p0.p0i8.i32(ptr , i8 , - i32 , i1 ) - declare void @llvm.memset.inline.p0.p0.i64(ptr , i8 , - i64 , i1 ) + declare void @llvm.memset.inline.p0.i32(ptr , i8 , + i32 , i1 ) + declare void @llvm.memset.inline.p0.i64(ptr , i8 , + i64 , i1 ) Overview: """"""""" @@ -30256,8 +30268,8 @@ normal value. The function never raises floating-point exceptions. The function does not canonicalize its input value and does not depend on the floating-point environment. If the floating-point environment has a zeroing treatment of subnormal input values (such as indicated -by the ``"denormal-fp-math"`` attribute), a subnormal value will be -observed (will not be implicitly treated as zero). +by the :ref:`denormal_fpenv ` attribute), a subnormal +value will be observed (will not be implicitly treated as zero). General Intrinsics @@ -32234,3 +32246,51 @@ intrinsics that this intrinsic is lowered into. The intent is that the deactivation symbol represents a field identifier. This intrinsic is used to implement structure protection. + +'``llvm.cond.loop``' Intrinsic +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Syntax: +""""""" + +:: + + declare void @llvm.cond.loop(i1 pred) + +Overview: +""""""""" + +The '``llvm.cond.loop``' intrinsic spins in an infinite loop if the +given predicate ``pred`` is true, otherwise it does nothing. + +Arguments: +"""""""""" + +``pred`` is the predicate. + +Semantics: +"""""""""" + +This intrinsic is semantically equivalent to a conditional branch +conditioned on ``pred`` to a basic block consisting only of an +unconditional branch to itself. + +Unlike such a branch, certain backends guarantee that this intrinsic +will use specific instructions. This allows an interrupt handler or +other introspection mechanism to straightforwardly detect whether +the program is currently spinning in the infinite loop and possibly +terminate the program if so. The intent is that this intrinsic may +be used as a more efficient alternative to a conditional branch to +a call to ``llvm.trap`` in circumstances where the loop detection +is guaranteed to be present. This construct has been experimentally +determined to be executed more efficiently (when the branch is not taken) +than a conditional branch to a trap instruction on AMD and older Intel +microarchitectures, and is also more code size efficient by avoiding the +need to emit a trap instruction and possibly a long branch instruction. + +With the X86 backend, the infinite loop is guaranteed to +consist of a short conditional branch instruction that branches to +itself. Specifically, the first byte of the instruction will be between +0x70 and 0x7F, and the second byte will be 0xFE. + +There are currently no guarantees about instructions used by other backends. diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst index efb20520db1b1..f7df57d05baa0 100644 --- a/llvm/docs/MIRLangRef.rst +++ b/llvm/docs/MIRLangRef.rst @@ -495,13 +495,13 @@ In ``AArch64RegisterInfo.td``: def sub_32 : SubRegIndex<32>; -If the third operand is an immediate with the value ``15`` (a target-dependent +If the second operand is an immediate with the value ``15`` (a target-dependent value), based on the instruction's opcode and the operand's index the operand will be printed as ``%subreg.sub_32``: .. code-block:: text - %1:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %1:gpr64 = SUBREG_TO_REG %0, %subreg.sub_32 For integers larger than 64 bits, we use a special machine operand, ``MO_CImmediate``, which stores the immediate in a ``ConstantInt`` using an ``APInt`` (LLVM's diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index b58ecc105620a..7156ae6a95be8 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -356,6 +356,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smpmpmt`` LLVM implements the `0.6 draft specification `__. +``experimental-zvabd`` + LLVM implements the `0.7 draft specification `__. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions @@ -632,3 +635,43 @@ Sanitizers Some intrinsics will be handled correctly anyway, if the RISC-V intrinsic is auto-upgraded into cross-platform LLVM intrinsics. Some others will be "heuristically" handled (possibly incorrectly). The rest will default to the "strict" handler, which checks that all the parameters are fully initialized. MSan intrinsics support is only required if code (including dependencies) manually calls the intrinsic. + +Processor-Specific Tuning Feature String +======================================== +Due to RISC-V's highly configurable nature, it is often desirable to share a single scheduling model across multiple similar RISC-V processors that only differ in a small number of (uArch) tuning features. An example of such tuning feature could be whether the latency of vector operations depend on VL or not. This could be extended to tuning features that are not directly connected to scheduling model but other parts of the RISC-V backend, like the cost of ``vrgather.vv`` instruction. + +To that end, RISC-V LLVM supports a tuning feature string format that helps users to build a performance model by "configuring" an existing tune CPU, along with its scheduling model. For example, this string + +:: + "sifive-x280:single-element-vec-fp64" + +takes ``sifive-x280`` as the "base" tune CPU and configured it with ``single-element-vec-fp64``. This gives us a performance model that looks exactly like that of ``sifive-x280``, except some of the 64-bit vector floating point instructions now produce only a single element per cycle due to ``single-element-vec-fp64``. This string could eventually be used in places like ``-mtune`` at the frontend. + +More formally speaking, each tuning feature string has the following format: + +:: + [":"]? + +where + +:: + tune-cpu ::= 'tuning CPU name in lower case' + directive ::= "[a-zA-Z0-9\_-]+" + tune-features ::= directive ["," directive]* + +A *directive* can and can only _enable_ or _disable_ a certain tuning feature from the tuning CPU. A **positive directive**, like the ``single-element-vec-fp64`` we just saw, enables an additional tuning feature in the associated tuning model. A **negative directive**, on the other hand, removes a certain tuning feature. For example, ``sifive-x390`` already has the ``single-element-vec-fp64`` feature, and we can use + +:: + "sifive-x390:full-vec-fp64" + +to create a new performance model that looks nearly the same as ``sifive-x390`` except ``single-element-vec-fp64`` being cut out. In this case, ``full-vec-fp64`` is a negative directive. + +There are some rules for the list of directives, though: + +1. The same directive cannot appear more than once. + +2. The positive and negative directives that belong to the same feature cannot appear at the same time. + +3. If a feature implies other features -- for example, ``short-forward-branch-imul`` implies ``short-forward-branch-ialu`` -- then the _implied_ features are subject to the previous two rules, too. For example, we cannot write _"short-forward-branch-imul,no-short-forward-branch-ialu"_, because the feature implied by ``short-forward-branch-imul`` violates rule 2. + +In addition to the rules listed above, right now, this string only accepts directives that are explicitly supported by the tune CPU. For example, _"sifive-x280:prefer-w-inst"_ is not a valid string as ``prefer-w-inst`` is not supported by ``sifive-x280`` at this moment. Vendors of these processors are expected to maintain the compatibility of their supported directives across different versions. There have been lots of discussions on having "generic" features that are universally supported by all RISC-V CPUs, yet many concerns -- including the difficulty to maintain compatibility across _all_ CPU targets and versions -- make us decide to table this issue until we find a reliable process to select such features. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index c3ff79e5422ab..30e74acf973ed 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -63,6 +63,9 @@ Changes to the LLVM IR intrinsics. These are equivalent to `fptrunc` and `fpext` with half with a bitcast. +* "denormal-fp-math" and "denormal-fp-math-f32" string attributes were + migrated to first-class denormal_fpenv attribute. + Changes to LLVM infrastructure ------------------------------ @@ -125,6 +128,12 @@ Changes to the RISC-V Backend * `llvm-objdump` now has support for `--symbolize-operands` with RISC-V. * `-mcpu=spacemit-x100` was added. * Change P extension version to match the 019 draft specification. Encoded in `-march` as `0p19`. +* Mnemonics for MOP/HINT-based instructions (`lpad`, `pause`, `ntl.*`, `c.ntl.*`, + `sspush`, `sspopchk`, `ssrdp`, `c.sspush`, `c.sspopchk`) are now always + available in the assembler and disassembler without requiring their respective + extensions. +* Adds experimental assembler support for the 'Zvabd` (RISC-V Integer Vector + Absolute Difference) extension. Changes to the WebAssembly Backend ---------------------------------- @@ -170,6 +179,10 @@ Changes to the LLVM tools Changes to LLDB --------------- +* Support for FreeBSD on MIPS64 has been removed. +* The minimum assumed version of FreeBSD is now 14. The effect of which is that watchpoints are + assumed to be supported. + Changes to BOLT --------------- diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h index 2bd971983e287..3fa2801e4b4bd 100644 --- a/llvm/include/llvm-c/Core.h +++ b/llvm/include/llvm-c/Core.h @@ -731,6 +731,40 @@ LLVM_C_ABI LLVMAttributeRef LLVMCreateConstantRangeAttribute( LLVMContextRef C, unsigned KindID, unsigned NumBits, const uint64_t LowerWords[], const uint64_t UpperWords[]); +/** + * Represent different denormal handling kinds for use with + * LLVMCreateDenormalFPEnvAttribute. + */ +typedef enum { + LLVMDenormalModeKindIEEE = 0, + LLVMDenormalModeKindPreserveSign = 1, + LLVMDenormalModeKindPositiveZero = 2, + LLVMDenormalModeKindDynamic = 3 +} LLVMDenormalModeKind; + +/** + * Create a DenormalFPEnv attribute. + * + * \p DefaultModeOutput is the assumed denormal handling for the outputs of most + * floating-point types. + * + * \p DefaultModeInput is the assumed denormal handling for the inputs of most + * floating-point types. + * + * \p FloatModeOutput is the assumed denormal handling for the outputs of + * float. This should always be the same as as DefaultModeOutput for most + * targets. + * + * \p FloatModeInput is the assumed denormal handling for the inputs of + * float. This should always be the same as as DefaultModeInput for most + * targets. + * + */ +LLVM_C_ABI LLVMAttributeRef LLVMCreateDenormalFPEnvAttribute( + LLVMContextRef C, LLVMDenormalModeKind DefaultModeOutput, + LLVMDenormalModeKind DefaultModeInput, LLVMDenormalModeKind FloatModeOutput, + LLVMDenormalModeKind FloatModeInput); + /** * Create a string attribute. */ diff --git a/llvm/include/llvm/ADT/FloatingPointMode.h b/llvm/include/llvm/ADT/FloatingPointMode.h index 36e20d8f25c98..da1fd22d85e0b 100644 --- a/llvm/include/llvm/ADT/FloatingPointMode.h +++ b/llvm/include/llvm/ADT/FloatingPointMode.h @@ -75,16 +75,16 @@ struct DenormalMode { Invalid = -1, /// IEEE-754 denormal numbers preserved. - IEEE, + IEEE = 0, /// The sign of a flushed-to-zero number is preserved in the sign of 0 - PreserveSign, + PreserveSign = 1, /// Denormals are flushed to positive zero. - PositiveZero, + PositiveZero = 2, /// Denormals have unknown treatment. - Dynamic + Dynamic = 3 }; /// Denormal flushing mode for floating point instruction results in the @@ -130,19 +130,30 @@ struct DenormalMode { return DenormalMode(DenormalModeKind::Dynamic, DenormalModeKind::Dynamic); } - bool operator==(DenormalMode Other) const { + constexpr uint32_t toIntValue() const { + assert(Input != Invalid && Output != Invalid); + return (static_cast(Input) << 2) | static_cast(Output); + } + + static constexpr DenormalMode createFromIntValue(uint32_t Data) { + uint32_t OutputMode = Data & 0x3; + uint32_t InputMode = (Data >> 2) & 0x3; + + return {static_cast(OutputMode), + static_cast(InputMode)}; + } + + constexpr bool operator==(DenormalMode Other) const { return Output == Other.Output && Input == Other.Input; } - bool operator!=(DenormalMode Other) const { + constexpr bool operator!=(DenormalMode Other) const { return !(*this == Other); } - bool isSimple() const { - return Input == Output; - } + constexpr bool isSimple() const { return Input == Output; } - bool isValid() const { + constexpr bool isValid() const { return Output != DenormalModeKind::Invalid && Input != DenormalModeKind::Invalid; } @@ -184,7 +195,7 @@ struct DenormalMode { /// Get the effective denormal mode if the mode if this caller calls into a /// function with \p Callee. This promotes dynamic modes to the mode of the /// caller. - DenormalMode mergeCalleeMode(DenormalMode Callee) const { + constexpr DenormalMode mergeCalleeMode(DenormalMode Callee) const { DenormalMode MergedMode = Callee; if (Callee.Input == DenormalMode::Dynamic) MergedMode.Input = Input; @@ -193,7 +204,8 @@ struct DenormalMode { return MergedMode; } - inline void print(raw_ostream &OS) const; + inline void print(raw_ostream &OS, bool Legacy = true, + bool OmitIfSame = false) const; inline std::string str() const { std::string storage; @@ -214,22 +226,23 @@ parseDenormalFPAttributeComponent(StringRef Str) { // Assume ieee on unspecified attribute. return StringSwitch(Str) .Cases({"", "ieee"}, DenormalMode::IEEE) - .Case("preserve-sign", DenormalMode::PreserveSign) - .Case("positive-zero", DenormalMode::PositiveZero) + .Cases({"preservesign", "preserve-sign"}, DenormalMode::PreserveSign) + .Cases({"positivezero", "positive-zero"}, DenormalMode::PositiveZero) .Case("dynamic", DenormalMode::Dynamic) .Default(DenormalMode::Invalid); } /// Return the name used for the denormal handling mode used by the /// expected names from the denormal-fp-math attribute. -inline StringRef denormalModeKindName(DenormalMode::DenormalModeKind Mode) { +constexpr StringRef denormalModeKindName(DenormalMode::DenormalModeKind Mode, + bool LegacyName = true) { switch (Mode) { case DenormalMode::IEEE: return "ieee"; case DenormalMode::PreserveSign: - return "preserve-sign"; + return LegacyName ? "preserve-sign" : "preservesign"; case DenormalMode::PositiveZero: - return "positive-zero"; + return LegacyName ? "positive-zero" : "positivezero"; case DenormalMode::Dynamic: return "dynamic"; default: @@ -253,8 +266,71 @@ inline DenormalMode parseDenormalFPAttribute(StringRef Str) { return Mode; } -void DenormalMode::print(raw_ostream &OS) const { - OS << denormalModeKindName(Output) << ',' << denormalModeKindName(Input); +void DenormalMode::print(raw_ostream &OS, bool Legacy, bool OmitIfSame) const { + OS << denormalModeKindName(Output, Legacy); + if (!OmitIfSame || Input != Output) { + OS << (Legacy ? ',' : '|'); + OS << denormalModeKindName(Input, Legacy); + } +} + +/// Represents the full denormal controls for a function, including the default +/// mode and the f32 specific override. +struct DenormalFPEnv { +private: + static constexpr unsigned BitsPerEntry = 2; + static constexpr unsigned BitsPerMode = 4; + static constexpr unsigned ModeMask = (1 << BitsPerMode) - 1; + +public: + DenormalMode DefaultMode; + DenormalMode F32Mode; + + constexpr DenormalFPEnv(DenormalMode BaseMode, + DenormalMode FloatMode = DenormalMode::getInvalid()) + : DefaultMode(BaseMode), + F32Mode(FloatMode.Output == DenormalMode::Invalid ? BaseMode.Output + : FloatMode.Output, + FloatMode.Input == DenormalMode::Invalid ? BaseMode.Input + : FloatMode.Input) {} + + static constexpr DenormalFPEnv getDefault() { + return DenormalFPEnv(DenormalMode::getIEEE(), DenormalMode::getIEEE()); + } + + constexpr uint32_t toIntValue() const { + assert(DefaultMode.isValid() && F32Mode.isValid()); + uint32_t Data = + DefaultMode.toIntValue() | (F32Mode.toIntValue() << BitsPerMode); + + assert(isUInt<8>(Data)); + return Data; + } + + static constexpr DenormalFPEnv createFromIntValue(uint32_t Data) { + return {DenormalMode::createFromIntValue(Data), + DenormalMode::createFromIntValue(Data >> BitsPerMode)}; + } + + constexpr bool operator==(DenormalFPEnv Other) const { + return DefaultMode == Other.DefaultMode && F32Mode == Other.F32Mode; + } + + constexpr bool operator!=(DenormalFPEnv Other) const { + return !(*this == Other); + } + + LLVM_ABI void print(raw_ostream &OS, bool OmitIfSame = true) const; + + DenormalFPEnv mergeCalleeMode(DenormalFPEnv Callee) const { + return DenormalFPEnv{DefaultMode.mergeCalleeMode(Callee.DefaultMode), + F32Mode.mergeCalleeMode(Callee.F32Mode)}; + } +}; + +inline raw_ostream &operator<<(raw_ostream &OS, DenormalFPEnv FPEnv) { + FPEnv.print(OS); + return OS; } /// Floating-point class tests, supported by 'is_fpclass' intrinsic. Actual diff --git a/llvm/include/llvm/ADT/ScopeExit.h b/llvm/include/llvm/ADT/ScopeExit.h index 1c0d52eb58aca..a8943c680f4e1 100644 --- a/llvm/include/llvm/ADT/ScopeExit.h +++ b/llvm/include/llvm/ADT/ScopeExit.h @@ -20,7 +20,7 @@ namespace llvm { -template class scope_exit { +template class [[nodiscard]] scope_exit { Callable ExitFunction; bool Engaged = true; // False once moved-from or release()d. diff --git a/llvm/include/llvm/Analysis/ConstantFolding.h b/llvm/include/llvm/Analysis/ConstantFolding.h index ea22ed48ab763..5e77b2ae6f15b 100644 --- a/llvm/include/llvm/Analysis/ConstantFolding.h +++ b/llvm/include/llvm/Analysis/ConstantFolding.h @@ -114,7 +114,7 @@ ConstantFoldFPInstOperands(unsigned Opcode, Constant *LHS, Constant *RHS, /// floating point instructions can have their mode set separately, so the /// direction is also needed. /// -/// If the calling function's "denormal-fp-math" input mode is "dynamic" for the +/// If the calling function's denormal_fpenv input mode is dynamic for the /// floating-point type, returns nullptr for denormal inputs. LLVM_ABI Constant *FlushFPConstant(Constant *Operand, const Instruction *I, bool IsOutput); diff --git a/llvm/include/llvm/Analysis/IVDescriptors.h b/llvm/include/llvm/Analysis/IVDescriptors.h index 05c17632e0e49..377e60c76e560 100644 --- a/llvm/include/llvm/Analysis/IVDescriptors.h +++ b/llvm/include/llvm/Analysis/IVDescriptors.h @@ -58,19 +58,11 @@ enum class RecurKind { FMulAdd, ///< Sum of float products with llvm.fmuladd(a * b + sum). AnyOf, ///< AnyOf reduction with select(cmp(),x,y) where one of (x,y) is ///< loop invariant, and both x and y are integer type. - FindFirstIVSMin, /// FindFirst reduction with select(icmp(),x,y) where one of - ///< (x,y) is a decreasing loop induction, and both x and y - ///< are integer type, producing a SMin reduction. - FindFirstIVUMin, /// FindFirst reduction with select(icmp(),x,y) where one of - ///< (x,y) is a decreasing loop induction, and both x and y - ///< are integer type, producing a UMin reduction. - FindLastIVSMax, ///< FindLast reduction with select(cmp(),x,y) where one of - ///< (x,y) is increasing loop induction, and both x and y - ///< are integer type, producing a SMax reduction. - FindLastIVUMax, ///< FindLast reduction with select(cmp(),x,y) where one of - ///< (x,y) is increasing loop induction, and both x and y - ///< are integer type, producing a UMax reduction. - FindLast, ///< FindLast reduction with select(cmp(),x,y) where x and y + FindIV, ///< FindIV reduction with select(icmp(),x,y) where one of (x,y) is + ///< a loop induction variable (increasing or decreasing), and both + ///< x and y are integer type. The signedness and direction are + ///< stored separately. + FindLast, ///< FindLast reduction with select(cmp(),x,y) where x and y ///< are an integer type, one is the current recurrence value, ///< and the other is an arbitrary value. // clang-format on @@ -283,32 +275,9 @@ class RecurrenceDescriptor { } /// Returns true if the recurrence kind is of the form - /// select(cmp(),x,y) where one of (x,y) is decreasing loop induction. - static bool isFindFirstIVRecurrenceKind(RecurKind Kind) { - return Kind == RecurKind::FindFirstIVSMin || - Kind == RecurKind::FindFirstIVUMin; - } - - /// Returns true if the recurrence kind is of the form - /// select(cmp(),x,y) where one of (x,y) is increasing loop induction. - static bool isFindLastIVRecurrenceKind(RecurKind Kind) { - return Kind == RecurKind::FindLastIVSMax || - Kind == RecurKind::FindLastIVUMax; - } - - /// Returns true if recurrece kind is a signed redux kind. - static bool isSignedRecurrenceKind(RecurKind Kind) { - return Kind == RecurKind::SMax || Kind == RecurKind::SMin || - Kind == RecurKind::FindFirstIVSMin || - Kind == RecurKind::FindLastIVSMax; - } - - /// Returns true if the recurrence kind is of the form - /// select(cmp(),x,y) where one of (x,y) is an increasing or decreasing loop - /// induction. + /// select(cmp(),x,y) where one of (x,y) is a loop induction variable. static bool isFindIVRecurrenceKind(RecurKind Kind) { - return isFindFirstIVRecurrenceKind(Kind) || - isFindLastIVRecurrenceKind(Kind); + return Kind == RecurKind::FindIV; } /// Returns true if the recurrence kind is of the form @@ -326,21 +295,6 @@ class RecurrenceDescriptor { /// actual type of the Phi if the recurrence has been type-promoted. Type *getRecurrenceType() const { return RecurrenceType; } - /// Returns the sentinel value for FindFirstIV & FindLastIV recurrences to - /// replace the start value. - Value *getSentinelValue() const { - Type *Ty = StartValue->getType(); - unsigned BW = Ty->getIntegerBitWidth(); - if (isFindLastIVRecurrenceKind(Kind)) { - return ConstantInt::get(Ty, isSignedRecurrenceKind(Kind) - ? APInt::getSignedMinValue(BW) - : APInt::getMinValue(BW)); - } - return ConstantInt::get(Ty, isSignedRecurrenceKind(Kind) - ? APInt::getSignedMaxValue(BW) - : APInt::getMaxValue(BW)); - } - /// Returns a reference to the instructions used for type-promoting the /// recurrence. const SmallPtrSet &getCastInsts() const { return CastInsts; } @@ -357,8 +311,8 @@ class RecurrenceDescriptor { bool isOrdered() const { return IsOrdered; } /// Returns true if the reduction PHI has any uses outside the reduction - /// chain. This is relevant for min/max reductions that are part of a - /// FindLastIV pattern. + /// chain. This is relevant for min/max reductions that are part of a FindIV + /// pattern. bool hasUsesOutsideReductionChain() const { return PhiHasUsesOutsideReductionChain; } @@ -401,8 +355,7 @@ class RecurrenceDescriptor { // if it is also the only FAdd in the PHI's use chain. bool IsOrdered = false; // True if the reduction PHI has in-loop users outside the reduction chain. - // This is relevant for min/max reductions that are part of a FindLastIV - // pattern. + // This is relevant for min/max reductions that are part of a FindIV pattern. bool PhiHasUsesOutsideReductionChain = false; // Instructions used for type-promoting the recurrence. SmallPtrSet CastInsts; diff --git a/llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h b/llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h index f285eacc4c565..7b00d0109a68c 100644 --- a/llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h +++ b/llvm/include/llvm/Analysis/ScalarEvolutionPatternMatch.h @@ -186,6 +186,12 @@ m_scev_PtrToInt(const Op0_t &Op0) { return SCEVUnaryExpr_match(Op0); } +template +inline SCEVUnaryExpr_match +m_scev_PtrToAddr(const Op0_t &Op0) { + return SCEVUnaryExpr_match(Op0); +} + template inline SCEVUnaryExpr_match m_scev_Trunc(const Op0_t &Op0) { diff --git a/llvm/include/llvm/AsmParser/AsmParserContext.h b/llvm/include/llvm/AsmParser/AsmParserContext.h index 5e578062a345b..9ea7fe6f74dfe 100644 --- a/llvm/include/llvm/AsmParser/AsmParserContext.h +++ b/llvm/include/llvm/AsmParser/AsmParserContext.h @@ -39,6 +39,7 @@ class AsmParserContext { DenseMap Functions; FMap::Allocator FAllocator; FMap FunctionsInverse = FMap(FAllocator); + DenseMap Blocks; using BBMap = IntervalMap>; BBMap::Allocator BBAllocator; BBMap BlocksInverse = BBMap(BBAllocator); - DenseMap Instructions; - using IMap = - IntervalMap::LeafSize, + DenseMap InstructionsAndArguments; + using VMap = + IntervalMap::LeafSize, IntervalMapHalfOpenInfo>; - IMap::Allocator IAllocator; - IMap InstructionsInverse = IMap(IAllocator); + VMap::Allocator VAllocator; + VMap InstructionsAndArgumentsInverse = VMap(VAllocator); + + VMap ReferencedValues = VMap(VAllocator); public: LLVM_ABI std::optional @@ -60,7 +63,7 @@ class AsmParserContext { LLVM_ABI std::optional getBlockLocation(const BasicBlock *) const; LLVM_ABI std::optional - getInstructionLocation(const Instruction *) const; + getInstructionOrArgumentLocation(const Value *) const; /// Get the function at the requested location range. /// If no single function occupies the queried range, or the record is /// missing, a nullptr is returned. @@ -77,17 +80,27 @@ class AsmParserContext { /// If no block occupies the queried location, or the record is missing, a /// nullptr is returned. LLVM_ABI BasicBlock *getBlockAtLocation(const FileLoc &) const; - /// Get the instruction at the requested location range. + /// Get the instruction or function argument at the requested location range. /// If no single instruction occupies the queried range, or the record is /// missing, a nullptr is returned. - LLVM_ABI Instruction *getInstructionAtLocation(const FileLocRange &) const; - /// Get the instruction at the requested location. + LLVM_ABI Value * + getInstructionOrArgumentAtLocation(const FileLocRange &) const; + /// Get the instruction or function argument at the requested location. /// If no instruction occupies the queried location, or the record is missing, /// a nullptr is returned. - LLVM_ABI Instruction *getInstructionAtLocation(const FileLoc &) const; + LLVM_ABI Value *getInstructionOrArgumentAtLocation(const FileLoc &) const; + /// Get value referenced at the requested location. + /// If no value occupies the queried location, or the record is missing, + /// a nullptr is returned. + LLVM_ABI Value *getValueReferencedAtLocation(const FileLoc &) const; + /// Get value referenced at the requested location range. + /// If no value occupies the queried location, or the record is missing, + /// a nullptr is returned. + LLVM_ABI Value *getValueReferencedAtLocation(const FileLocRange &) const; LLVM_ABI bool addFunctionLocation(Function *, const FileLocRange &); LLVM_ABI bool addBlockLocation(BasicBlock *, const FileLocRange &); - LLVM_ABI bool addInstructionLocation(Instruction *, const FileLocRange &); + LLVM_ABI bool addInstructionOrArgumentLocation(Value *, const FileLocRange &); + LLVM_ABI bool addValueReferenceAtLocation(Value *, const FileLocRange &); }; } // namespace llvm diff --git a/llvm/include/llvm/AsmParser/LLParser.h b/llvm/include/llvm/AsmParser/LLParser.h index 185847f258cda..a7d90a8168960 100644 --- a/llvm/include/llvm/AsmParser/LLParser.h +++ b/llvm/include/llvm/AsmParser/LLParser.h @@ -181,6 +181,10 @@ namespace llvm { /// Keeps track of source locations for Values, BasicBlocks, and Functions. AsmParserContext *ParserContext; + /// retainedNodes of these subprograms should be cleaned up from incorrectly + /// scoped local types. + SmallVector NewDistinctSPs; + /// Only the llvm-as tool may set this to false to bypass /// UpgradeDebuginfo so it can generate broken bitcode. bool UpgradeDebugInfo; @@ -325,6 +329,8 @@ namespace llvm { bool parseOptionalUWTableKind(UWTableKind &Kind); bool parseAllocKind(AllocFnKind &Kind); std::optional parseMemoryAttr(); + std::optional parseDenormalFPEnvEntry(); + std::optional parseDenormalFPEnvAttr(); unsigned parseNoFPClassAttr(); bool parseScopeAndOrdering(bool IsAtomic, SyncScope::ID &SSID, AtomicOrdering &Ordering); @@ -614,10 +620,12 @@ namespace llvm { struct ArgInfo { LocTy Loc; Type *Ty; + std::optional IdentLoc; AttributeSet Attrs; std::string Name; - ArgInfo(LocTy L, Type *ty, AttributeSet Attr, const std::string &N) - : Loc(L), Ty(ty), Attrs(Attr), Name(N) {} + ArgInfo(LocTy L, Type *ty, std::optional IdentLoc, + AttributeSet Attr, const std::string &N) + : Loc(L), Ty(ty), IdentLoc(IdentLoc), Attrs(Attr), Name(N) {} }; bool parseArgumentList(SmallVectorImpl &ArgList, SmallVectorImpl &UnnamedArgNums, diff --git a/llvm/include/llvm/AsmParser/LLToken.h b/llvm/include/llvm/AsmParser/LLToken.h index 24f84cfa09e34..dfe51466c6152 100644 --- a/llvm/include/llvm/AsmParser/LLToken.h +++ b/llvm/include/llvm/AsmParser/LLToken.h @@ -222,6 +222,12 @@ enum Kind { kw_provenance, kw_read_provenance, + // denormal_fpenv attribute: + kw_ieee, + kw_preservesign, + kw_positivezero, + kw_dynamic, + // nofpclass attribute: kw_all, kw_nan, diff --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h index ae954167c3d3a..017b6fdd6baa1 100644 --- a/llvm/include/llvm/BinaryFormat/ELF.h +++ b/llvm/include/llvm/BinaryFormat/ELF.h @@ -862,6 +862,7 @@ enum : unsigned { EF_AMDGPU_MACH_AMDGCN_GFX1153 = 0x058, EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC = 0x059, EF_AMDGPU_MACH_AMDGCN_GFX1251 = 0x05a, + EF_AMDGPU_MACH_AMDGCN_GFX1170 = 0x05d, EF_AMDGPU_MACH_AMDGCN_GFX9_4_GENERIC = 0x05f, // clang-format on diff --git a/llvm/include/llvm/Bitcode/LLVMBitCodes.h b/llvm/include/llvm/Bitcode/LLVMBitCodes.h index 20d19f21a64ce..811116a3e1756 100644 --- a/llvm/include/llvm/Bitcode/LLVMBitCodes.h +++ b/llvm/include/llvm/Bitcode/LLVMBitCodes.h @@ -807,6 +807,7 @@ enum AttributeKindCodes { ATTR_KIND_DEAD_ON_RETURN = 103, ATTR_KIND_SANITIZE_ALLOC_TOKEN = 104, ATTR_KIND_NO_CREATE_UNDEF_OR_POISON = 105, + ATTR_KIND_DENORMAL_FPENV = 106, }; enum ComdatSelectionKindCodes { diff --git a/llvm/include/llvm/CAS/BuiltinObjectHasher.h b/llvm/include/llvm/CAS/BuiltinObjectHasher.h index c9b004216f796..7079e5ec448c8 100644 --- a/llvm/include/llvm/CAS/BuiltinObjectHasher.h +++ b/llvm/include/llvm/CAS/BuiltinObjectHasher.h @@ -39,6 +39,8 @@ template class BuiltinObjectHasher { return H.finish(); } + static Expected hashFile(StringRef FilePath); + private: HashT finish() { return Hasher.final(); } diff --git a/llvm/include/llvm/CAS/OnDiskGraphDB.h b/llvm/include/llvm/CAS/OnDiskGraphDB.h index 64ad83440bc9c..0c57893f465f9 100644 --- a/llvm/include/llvm/CAS/OnDiskGraphDB.h +++ b/llvm/include/llvm/CAS/OnDiskGraphDB.h @@ -264,6 +264,19 @@ class OnDiskGraphDB { LLVM_ABI_FOR_TEST Error store(ObjectID ID, ArrayRef Refs, ArrayRef Data); + /// Associates the data of a file with a particular object ID. If there is + /// already a record for this object the operation is a no-op. + /// + /// This is more than a convenience variant of \c store(), \c storeFile() can + /// perform optimizations that reduce I/O and disk space consumption. + /// + /// If there are any concurrent modifications to the file, the contents in the + /// CAS may be corrupt. + /// + /// \param ID the object ID to associate the data with. + /// \param FilePath the path of the file data. + LLVM_ABI_FOR_TEST Error storeFile(ObjectID ID, StringRef FilePath); + /// \returns \p nullopt if the object associated with \p Ref does not exist. LLVM_ABI_FOR_TEST Expected> load(ObjectID Ref); @@ -315,6 +328,31 @@ class OnDiskGraphDB { return make_range(Refs.begin(), Refs.end()); } + /// Encapsulates file info for an underlying object node. + struct FileBackedData { + /// The data of the object node. + ArrayRef Data; + + struct FileInfoTy { + /// The file path of the object node. + std::string FilePath; + /// Whether the file of the object leaf node has an extra nul appended at + /// the end. If the file is copied the extra nul needs to be removed. + bool IsFileNulTerminated; + }; + /// File information for the object, if available. + std::optional FileInfo; + }; + + /// Provides access to the underlying file path, that represents an object + /// leaf node, when available. + /// + /// This enables reducing I/O and disk space consumption, i.e. instead of + /// loading the data in memory and then writing it to a file, the client could + /// clone the underlying file directly. The client *must not* write to or + /// delete the underlying file, the path is provided only for reading/copying. + FileBackedData getInternalFileBackedObjectData(ObjectHandle Node) const; + /// \returns Total size of stored objects. /// /// NOTE: There's a possibility that the returned size is not including a @@ -398,12 +436,19 @@ class OnDiskGraphDB { Error importFullTree(ObjectID PrimaryID, ObjectHandle UpstreamNode); /// Import only the \param UpstreamNode. Error importSingleNode(ObjectID PrimaryID, ObjectHandle UpstreamNode); + Error importUpstreamData(ObjectID PrimaryID, ArrayRef PrimaryRefs, + ObjectHandle UpstreamNode); + + enum class InternalUpstreamImportKind { Leaf, Leaf0 }; + /// Private \c storeFile than optimizes internal upstream database imports. + Error storeFile(ObjectID ID, StringRef FilePath, + std::optional ImportKind); /// Found the IndexProxy for the hash. Expected indexHash(ArrayRef Hash); /// Get path for creating standalone data file. - void getStandalonePath(StringRef FileSuffix, const IndexProxy &I, + void getStandalonePath(StringRef FileSuffix, FileOffset IndexOffset, SmallVectorImpl &Path) const; /// Create a standalone leaf file. Error createStandaloneLeaf(IndexProxy &I, ArrayRef Data); diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index 7d273cfd4559d..fa08bfa476fae 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -979,7 +979,7 @@ class LLVM_ABI AsmPrinter : public MachineFunctionPass { virtual void emitModuleCommandLines(Module &M); GCMetadataPrinter *getOrCreateGCPrinter(GCStrategy &S); - void emitGlobalIFunc(Module &M, const GlobalIFunc &GI); + virtual void emitGlobalIFunc(Module &M, const GlobalIFunc &GI); /// This method decides whether the specified basic block requires a label. bool shouldEmitLabelForBasicBlock(const MachineBasicBlock &MBB) const; diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h b/llvm/include/llvm/CodeGen/CommandFlags.h index 6a907b64542ae..c83bce7771878 100644 --- a/llvm/include/llvm/CodeGen/CommandFlags.h +++ b/llvm/include/llvm/CodeGen/CommandFlags.h @@ -58,8 +58,6 @@ LLVM_ABI CodeGenFileType getFileType(); LLVM_ABI FramePointerKind getFramePointerUsage(); -LLVM_ABI bool getEnableNoInfsFPMath(); - LLVM_ABI bool getEnableNoNaNsFPMath(); LLVM_ABI bool getEnableNoSignedZerosFPMath(); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h index 6701ae0510581..19de00ee65cbc 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h @@ -218,8 +218,7 @@ class GISelCSEAnalysisWrapper { /// If CSEConfig is already set, and the CSE Analysis has been preserved, /// it will not use the new CSEOpt(use Recompute to force using the new /// CSEOpt). - LLVM_ABI GISelCSEInfo &get(std::unique_ptr CSEOpt, - bool ReCompute = false); + LLVM_ABI GISelCSEInfo &get(std::unique_ptr CSEOpt); void setMF(MachineFunction &MFunc) { MF = &MFunc; } void setComputed(bool Computed) { AlreadyComputed = Computed; } void releaseMemory() { Info.releaseMemory(); } diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h index fea900f37ec74..391c12001a2e8 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -19,6 +19,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/TargetCallingConv.h" +#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGenTypes/LowLevelType.h" #include "llvm/CodeGenTypes/MachineValueType.h" #include "llvm/IR/CallingConv.h" @@ -388,7 +389,7 @@ class LLVM_ABI CallLowering { void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, - SmallVectorImpl *Offsets = nullptr) const; + SmallVectorImpl *Offsets = nullptr) const; /// Analyze the argument list in \p Args, using \p Assigner to populate \p /// CCInfo. This will determine the types and locations to use for passed or @@ -485,6 +486,26 @@ class LLVM_ABI CallLowering { const CallBase &CB, CallLoweringInfo &Info) const; + /// Create a sequence of instructions to combine pieces split into register + /// typed values to the original IR value. \p OrigRegs contains the + /// destination value registers of type \p LLTy, and \p Regs contains the + /// legalized pieces with type \p PartLLT. This is used for incoming values + /// (physregs to vregs). + static void buildCopyFromRegs(MachineIRBuilder &B, + ArrayRef OrigRegs, + ArrayRef Regs, LLT LLTy, LLT PartLLT, + const ISD::ArgFlagsTy Flags); + + /// Create a sequence of instructions to expand the value in \p SrcReg (of + /// type + /// \p SrcTy) to the types in \p DstRegs (of type \p PartTy). \p ExtendOp + /// should contain the type of scalar value extension if necessary. + /// + /// This is used for outgoing values (vregs to physregs) + static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef DstRegs, + Register SrcReg, LLT SrcTy, LLT PartTy, + unsigned ExtendOp = TargetOpcode::G_ANYEXT); + /// \return True if the return type described by \p Outs can be returned /// without performing sret demotion. bool checkReturn(CCState &CCInfo, SmallVectorImpl &Outs, diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h index 3828d859212cb..2f3f55a58a517 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -299,7 +299,7 @@ class IRTranslator : public MachineFunctionPass { bool translateIntrinsic( const CallBase &CB, Intrinsic::ID ID, MachineIRBuilder &MIRBuilder, - const TargetLowering::IntrinsicInfo *TgtMemIntrinsicInfo = nullptr); + ArrayRef TgtMemIntrinsicInfos = {}); /// When an invoke or a cleanupret unwinds to the next EH pad, there are /// many places it could ultimately go. In the IR, we have a single unwind diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h index 36744de92128d..37936af6d853c 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h @@ -526,6 +526,7 @@ class LegalizerHelper { LLVM_ABI LegalizeResult lowerFPTRUNC_F64_TO_F16(MachineInstr &MI); LLVM_ABI LegalizeResult lowerFPTRUNC(MachineInstr &MI); LLVM_ABI LegalizeResult lowerFPOWI(MachineInstr &MI); + LLVM_ABI LegalizeResult lowerFMODF(MachineInstr &MI); LLVM_ABI LegalizeResult lowerISFPCLASS(MachineInstr &MI); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 30bf7e3a4a3d0..5114e979e58ea 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -2202,9 +2202,10 @@ class LLVM_ABI MachineIRBuilder { } /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1 - MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, - const SrcOp &Src1) { - return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1}); + MachineInstrBuilder + buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, + std::optional Flags = std::nullopt) { + return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1}, Flags); } /// Build and insert \p Res = G_UITOFP \p Src0 diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h index da2742e089f8f..de6606e7ed14a 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -132,12 +132,10 @@ LLVM_ABI Register constrainOperandRegClass( /// generic) virtual register operands to the instruction's register class. /// This could involve inserting COPYs before (for uses) or after (for defs). /// This requires the number of operands to match the instruction description. -/// \returns whether operand regclass constraining succeeded. -/// // FIXME: Not all instructions have the same number of operands. We should // probably expose a constrain helper per operand and let the target selector // constrain individual registers, like fast-isel. -LLVM_ABI bool constrainSelectedInstRegOperands(MachineInstr &I, +LLVM_ABI void constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI); diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index 2ebd2641944f5..b8c6788e0bc03 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -1441,6 +1441,10 @@ enum NodeType { /// debugging purposes. FAKE_USE, + /// COND_LOOP is a conditional branch to self, used for implementing efficient + /// conditional traps. + COND_LOOP, + /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the /// beginning and end of GC transition sequence, and carry arbitrary /// information that target might need for lowering. The first operand is diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 873cad4953541..29da32c931eea 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -672,7 +672,7 @@ class MachineInstr return true; if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) return true; - if (isSubregToReg() && OpIdx == 3) + if (isSubregToReg() && OpIdx == 2) return true; return false; } diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h index 1a33d760fb59e..1b3216aef8079 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h @@ -438,10 +438,10 @@ class MachineInstrBuilder { return *this; } - bool constrainAllUses(const TargetInstrInfo &TII, + void constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const { - return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); } }; diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h index 6326fd4862d92..cf7901ad697de 100644 --- a/llvm/include/llvm/CodeGen/MachinePipeliner.h +++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h @@ -776,16 +776,6 @@ class SMSchedule { /// Return the last cycle in the finalized schedule. int getFinalCycle() const { return FirstCycle + InitiationInterval - 1; } - /// Return the cycle of the earliest scheduled instruction in the dependence - /// chain. - int earliestCycleInChain(const SwingSchedulerDDGEdge &Dep, - const SwingSchedulerDDG *DDG); - - /// Return the cycle of the latest scheduled instruction in the dependence - /// chain. - int latestCycleInChain(const SwingSchedulerDDGEdge &Dep, - const SwingSchedulerDDG *DDG); - void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int II, SwingSchedulerDAG *DAG); bool insert(SUnit *SU, int StartCycle, int EndCycle, int II); diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index eed3769882545..b5458bf7180ca 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -438,10 +438,18 @@ class SelectionDAG { template static uint16_t getSyntheticNodeSubclassData(unsigned Opc, unsigned Order, - SDVTList VTs, EVT MemoryVT, - MachineMemOperand *MMO) { + SDVTList VTs, EVT MemoryVT, + MachineMemOperand *MMO) { return SDNodeTy(Opc, Order, DebugLoc(), VTs, MemoryVT, MMO) - .getRawSubclassData(); + .getRawSubclassData(); + } + + template + static uint16_t getSyntheticNodeSubclassData( + unsigned Opc, unsigned Order, SDVTList VTs, EVT MemoryVT, + PointerUnion MemRefs) { + return SDNodeTy(Opc, Order, DebugLoc(), VTs, MemoryVT, MemRefs) + .getRawSubclassData(); } void createOperands(SDNode *Node, ArrayRef Vals); @@ -1291,6 +1299,12 @@ class SelectionDAG { SDValue Size, const CallInst *CI); + /// Lower a strcmp operation into a target library call and return the + /// resulting chain and call result as SelectionDAG SDValues. + LLVM_ABI std::pair getStrcmp(SDValue Chain, const SDLoc &dl, + SDValue S0, SDValue S1, + const CallInst *CI); + /// Lower a strcpy operation into a target library call and return the /// resulting chain and call result as SelectionDAG SDValues. LLVM_ABI std::pair getStrcpy(SDValue Chain, const SDLoc &dl, @@ -1359,7 +1373,7 @@ class SelectionDAG { /// ISD::CondCode instead of an SDValue. SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain = SDValue(), - bool IsSignaling = false) { + bool IsSignaling = false, SDNodeFlags Flags = {}) { assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() && "Vector/scalar operand type mismatch for setcc"); assert(LHS.getValueType().isVector() == VT.isVector() && @@ -1368,8 +1382,9 @@ class SelectionDAG { "Cannot create a setCC of an invalid node."); if (Chain) return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL, - {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)}); - return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond)); + {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)}, + Flags); + return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond), Flags); } /// Helper function to make it easier to build VP_SETCCs if you just have an @@ -1475,6 +1490,12 @@ class SelectionDAG { SDVTList VTList, ArrayRef Ops, EVT MemVT, MachineMemOperand *MMO); + /// getMemIntrinsicNode - Creates a MemIntrinsicNode with multiple MMOs. + LLVM_ABI SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, + SDVTList VTList, ArrayRef Ops, + EVT MemVT, + ArrayRef MMOs); + /// Creates a LifetimeSDNode that starts (`IsStart==true`) or ends /// (`IsStart==false`) the lifetime of the `FrameIndex`. LLVM_ABI SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, @@ -2092,7 +2113,7 @@ class SelectionDAG { /// Constant fold a setcc to true or false. LLVM_ABI SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, - const SDLoc &dl); + const SDLoc &dl, SDNodeFlags Flags = {}); /// Return true if the sign bit of Op is known to be zero. /// We use this predicate to simplify operations downstream. diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index c94dc4241368e..38a7d70ef6db0 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -470,7 +470,7 @@ class SelectionDAGISel { } void SelectCodeCommon(SDNode *NodeToMatch, const uint8_t *MatcherTable, - unsigned TableSize); + unsigned TableSize, const uint8_t *OperandLists); /// Return true if complex patterns for this target can mutate the /// DAG. diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index a23b26e145185..3bbafe2d124e7 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -428,6 +428,9 @@ struct SDNodeFlags { // that affect the provenance may have been optimized away. InBounds = 1 << 15, + // Call does not require convergence guarantees. + NoConvergent = 1 << 16, + // NOTE: Please update LargestValue in LLVM_DECLARE_ENUM_AS_BITMASK below // the class definition when adding new flags. @@ -468,6 +471,7 @@ struct SDNodeFlags { void setNoFPExcept(bool b) { setFlag(b); } void setUnpredictable(bool b) { setFlag(b); } void setInBounds(bool b) { setFlag(b); } + void setNoConvergent(bool b) { setFlag(b); } // These are accessors for each flag. bool hasNoUnsignedWrap() const { return Flags & NoUnsignedWrap; } @@ -486,6 +490,7 @@ struct SDNodeFlags { bool hasNoFPExcept() const { return Flags & NoFPExcept; } bool hasUnpredictable() const { return Flags & Unpredictable; } bool hasInBounds() const { return Flags & InBounds; } + bool hasNoConvergent() const { return Flags & NoConvergent; } bool operator==(const SDNodeFlags &Other) const { return Flags == Other.Flags; @@ -495,7 +500,7 @@ struct SDNodeFlags { }; LLVM_DECLARE_ENUM_AS_BITMASK(decltype(SDNodeFlags::None), - SDNodeFlags::InBounds); + SDNodeFlags::NoConvergent); inline SDNodeFlags operator|(SDNodeFlags LHS, SDNodeFlags RHS) { LHS |= RHS; @@ -1411,19 +1416,26 @@ class MemSDNode : public SDNode { EVT MemoryVT; protected: - /// Memory reference information. - MachineMemOperand *MMO; + /// Memory reference information. Must always have at least one MMO. + /// - MachineMemOperand*: exactly 1 MMO (common case) + /// - MachineMemOperand**: pointer to array, size at offset -1 + PointerUnion MemRefs; public: - LLVM_ABI MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, - SDVTList VTs, EVT memvt, MachineMemOperand *MMO); + /// Constructor that supports single or multiple MMOs. For single MMO, pass + /// the MMO pointer directly. For multiple MMOs, pre-allocate storage with + /// count at offset -1 and pass pointer to array. + LLVM_ABI + MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, + EVT memvt, + PointerUnion memrefs); - bool readMem() const { return MMO->isLoad(); } - bool writeMem() const { return MMO->isStore(); } + bool readMem() const { return getMemOperand()->isLoad(); } + bool writeMem() const { return getMemOperand()->isStore(); } /// Returns alignment and volatility of the memory access - Align getBaseAlign() const { return MMO->getBaseAlign(); } - Align getAlign() const { return MMO->getAlign(); } + Align getBaseAlign() const { return getMemOperand()->getBaseAlign(); } + Align getAlign() const { return getMemOperand()->getAlign(); } /// Return the SubclassData value, without HasDebugValue. This contains an /// encoding of the volatile flag, as well as bits used by subclasses. This @@ -1450,36 +1462,40 @@ class MemSDNode : public SDNode { bool isInvariant() const { return MemSDNodeBits.IsInvariant; } // Returns the offset from the location of the access. - int64_t getSrcValueOffset() const { return MMO->getOffset(); } + int64_t getSrcValueOffset() const { return getMemOperand()->getOffset(); } /// Returns the AA info that describes the dereference. - AAMDNodes getAAInfo() const { return MMO->getAAInfo(); } + AAMDNodes getAAInfo() const { return getMemOperand()->getAAInfo(); } /// Returns the Ranges that describes the dereference. - const MDNode *getRanges() const { return MMO->getRanges(); } + const MDNode *getRanges() const { return getMemOperand()->getRanges(); } /// Returns the synchronization scope ID for this memory operation. - SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); } + SyncScope::ID getSyncScopeID() const { + return getMemOperand()->getSyncScopeID(); + } /// Return the atomic ordering requirements for this memory operation. For /// cmpxchg atomic operations, return the atomic ordering requirements when /// store occurs. AtomicOrdering getSuccessOrdering() const { - return MMO->getSuccessOrdering(); + return getMemOperand()->getSuccessOrdering(); } /// Return a single atomic ordering that is at least as strong as both the /// success and failure orderings for an atomic operation. (For operations /// other than cmpxchg, this is equivalent to getSuccessOrdering().) - AtomicOrdering getMergedOrdering() const { return MMO->getMergedOrdering(); } + AtomicOrdering getMergedOrdering() const { + return getMemOperand()->getMergedOrdering(); + } /// Return true if the memory operation ordering is Unordered or higher. - bool isAtomic() const { return MMO->isAtomic(); } + bool isAtomic() const { return getMemOperand()->isAtomic(); } /// Returns true if the memory operation doesn't imply any ordering /// constraints on surrounding memory operations beyond the normal memory /// aliasing rules. - bool isUnordered() const { return MMO->isUnordered(); } + bool isUnordered() const { return getMemOperand()->isUnordered(); } /// Returns true if the memory operation is neither atomic or volatile. bool isSimple() const { return !isAtomic() && !isVolatile(); } @@ -1487,12 +1503,37 @@ class MemSDNode : public SDNode { /// Return the type of the in-memory value. EVT getMemoryVT() const { return MemoryVT; } - /// Return a MachineMemOperand object describing the memory + /// Return the unique MachineMemOperand object describing the memory /// reference performed by operation. - MachineMemOperand *getMemOperand() const { return MMO; } + /// Asserts if multiple MMOs are present - use memoperands() instead. + MachineMemOperand *getMemOperand() const { + assert(!isa(MemRefs) && + "Use memoperands() for nodes with multiple memory operands"); + return cast(MemRefs); + } + + /// Return the number of memory operands. + size_t getNumMemOperands() const { + if (isa(MemRefs)) + return 1; + MachineMemOperand **Array = cast(MemRefs); + return reinterpret_cast(Array)[-1]; + } + + /// Return true if this node has exactly one memory operand. + bool hasUniqueMemOperand() const { return isa(MemRefs); } + + /// Return the memory operands for this node. + ArrayRef memoperands() const { + if (isa(MemRefs)) + return ArrayRef(MemRefs.getAddrOfPtr1(), 1); + MachineMemOperand **Array = cast(MemRefs); + size_t Count = reinterpret_cast(Array)[-1]; + return ArrayRef(Array, Count); + } const MachinePointerInfo &getPointerInfo() const { - return MMO->getPointerInfo(); + return getMemOperand()->getPointerInfo(); } /// Return the address space for the associated pointer @@ -1501,19 +1542,35 @@ class MemSDNode : public SDNode { } /// Update this MemSDNode's MachineMemOperand information - /// to reflect the alignment of NewMMO, if it has a greater alignment. + /// to reflect the alignment of NewMMOs, if they have greater alignment. /// This must only be used when the new alignment applies to all users of - /// this MachineMemOperand. - void refineAlignment(const MachineMemOperand *NewMMO) { - MMO->refineAlignment(NewMMO); + /// these MachineMemOperands. The NewMMOs array must parallel memoperands(). + void refineAlignment(ArrayRef NewMMOs) { + ArrayRef MMOs = memoperands(); + assert(NewMMOs.size() == MMOs.size() && "MMO count mismatch"); + for (auto [MMO, NewMMO] : zip(MMOs, NewMMOs)) + MMO->refineAlignment(NewMMO); + } + + void refineAlignment(MachineMemOperand *NewMMO) { + refineAlignment(ArrayRef(NewMMO)); } - void refineRanges(const MachineMemOperand *NewMMO) { - // If this node has range metadata that is different than NewMMO, clear the - // range metadata. + /// Refine range metadata for all MMOs. The NewMMOs array must parallel + /// memoperands(). For each pair, if ranges differ, the stored range is + /// cleared. + void refineRanges(ArrayRef NewMMOs) { + ArrayRef MMOs = memoperands(); + assert(NewMMOs.size() == MMOs.size() && "MMO count mismatch"); // FIXME: Union the ranges instead? - if (getRanges() && getRanges() != NewMMO->getRanges()) - MMO->clearRanges(); + for (auto [MMO, NewMMO] : zip(MMOs, NewMMOs)) { + if (MMO->getRanges() && MMO->getRanges() != NewMMO->getRanges()) + MMO->clearRanges(); + } + } + + void refineRanges(MachineMemOperand *NewMMO) { + refineRanges(ArrayRef(NewMMO)); } const SDValue &getChain() const { return getOperand(0); } @@ -1626,7 +1683,7 @@ class AtomicSDNode : public MemSDNode { /// when store does not occur. AtomicOrdering getFailureOrdering() const { assert(isCompareAndSwap() && "Must be cmpxchg operation"); - return MMO->getFailureOrdering(); + return getMemOperand()->getFailureOrdering(); } // Methods to support isa and dyn_cast @@ -1666,9 +1723,11 @@ class AtomicSDNode : public MemSDNode { /// opcode (see `SelectionDAGTargetInfo::isTargetMemoryOpcode`). class MemIntrinsicSDNode : public MemSDNode { public: - MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, - SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO) - : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) { + MemIntrinsicSDNode( + unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, + EVT MemoryVT, + PointerUnion MemRefs) + : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MemRefs) { SDNodeBits.IsMemIntrinsic = true; } @@ -2333,7 +2392,7 @@ class BuildVectorSDNode : public SDNode { /// integer, the value "" is returned. Arithmetic is performed modulo /// 2^BitWidth, so this also matches sequences that wrap around. Poison /// elements are ignored and can take any value. - LLVM_ABI std::optional> isConstantSequence() const; + LLVM_ABI std::optional> isArithmeticSequence() const; /// Recast bit data \p SrcBitElements to \p DstEltSizeInBits wide elements. /// Undef elements are treated as zero, and entirely undefined elements are diff --git a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h index 0b137a92fce19..508514a007819 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h @@ -161,11 +161,10 @@ class SelectionDAGTargetInfo { /// faster than a libcall. /// The first returned SDValue is the result of the strcmp and the second is /// the chain. Both SDValues can be null if a normal libcall should be used. - virtual std::pair - EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, - SDValue Op1, SDValue Op2, - MachinePointerInfo Op1PtrInfo, - MachinePointerInfo Op2PtrInfo) const { + virtual std::pair EmitTargetCodeForStrcmp( + SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, + SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo, + const CallInst *CI) const { return std::make_pair(SDValue(), SDValue()); } diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 91fddce7e7e47..45713360d44de 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -1021,35 +1021,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo { llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); } - /// Analyze the given select instruction, returning true if - /// it cannot be understood. It is assumed that MI->isSelect() is true. - /// - /// When successful, return the controlling condition and the operands that - /// determine the true and false result values. - /// - /// Result = SELECT Cond, TrueOp, FalseOp - /// - /// Some targets can optimize select instructions, for example by predicating - /// the instruction defining one of the operands. Such targets should set - /// Optimizable. - /// - /// @param MI Select instruction to analyze. - /// @param Cond Condition controlling the select. - /// @param TrueOp Operand number of the value selected when Cond is true. - /// @param FalseOp Operand number of the value selected when Cond is false. - /// @param Optimizable Returned as true if MI is optimizable. - /// @returns False on success. - virtual bool analyzeSelect(const MachineInstr &MI, - SmallVectorImpl &Cond, - unsigned &TrueOp, unsigned &FalseOp, - bool &Optimizable) const { - assert(MI.getDesc().isSelect() && "MI must be a select instruction"); - return true; - } - - /// Given a select instruction that was understood by - /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by - /// merging it with one of its operands. Returns NULL on failure. + /// Given an instruction marked as `isSelect = true`, attempt to optimize MI + /// by merging it with one of its operands. Returns nullptr on failure. /// /// When successful, returns the new select instruction. The client is /// responsible for deleting MI. @@ -1065,8 +1038,8 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo { virtual MachineInstr *optimizeSelect(MachineInstr &MI, SmallPtrSetImpl &NewMIs, bool PreferFalse = false) const { - // This function must be implemented if Optimizable is ever set. - llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); + assert(MI.isSelect() && "MI must be a select instruction"); + return nullptr; } /// Emit instructions to copy a pair of physical registers. diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 442225bdec01f..f6d5578412d1e 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -1244,15 +1244,32 @@ class LLVM_ABI TargetLoweringBase { }; /// Given an intrinsic, checks if on the target the intrinsic will need to map - /// to a MemIntrinsicNode (touches memory). If this is the case, it returns - /// true and store the intrinsic information into the IntrinsicInfo that was - /// passed to the function. + /// to a MemIntrinsicNode (touches memory). If this is the case, it stores + /// the intrinsic information into the IntrinsicInfo vector passed to the + /// function. The vector may contain multiple entries for intrinsics that + /// access multiple memory locations. + virtual void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, + unsigned Intrinsic) const { + // The default implementation forwards to the legacy single-info overload + // for compatibility. + IntrinsicInfo Info; + if (getTgtMemIntrinsic(Info, I, MF, Intrinsic)) + Infos.push_back(Info); + } + +protected: + /// This is a legacy single-info overload. New code should override the + /// SmallVectorImpl overload instead to support multiple memory operands. + /// + /// TODO: Remove this once the refactoring is complete. virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallBase &, MachineFunction &, unsigned /*Intrinsic*/) const { return false; } +public: /// Returns true if the target can instruction select the specified FP /// immediate natively. If false, the legalizer will materialize the FP /// immediate as a load from a constant pool. @@ -5425,7 +5442,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase { /// comparison may check if the operand is NAN, INF, zero, normal, etc. The /// result should be used as the condition operand for a select or branch. virtual SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, - const DenormalMode &Mode) const; + const DenormalMode &Mode, + SDNodeFlags Flags = {}) const; /// Return a target-dependent result if the input operand is not suitable for /// use with a square root estimate calculation. diff --git a/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h b/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h index 9f271dd502b24..8cb1609153045 100644 --- a/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h +++ b/llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h @@ -289,7 +289,7 @@ class TargetLoweringObjectFileXCOFF : public TargetLoweringObjectFile { static XCOFF::StorageClass getStorageClassForGlobal(const GlobalValue *GV); MCSection * - getSectionForFunctionDescriptor(const Function *F, + getSectionForFunctionDescriptor(const GlobalObject *F, const TargetMachine &TM) const override; MCSection *getSectionForTOCEntry(const MCSymbol *Sym, const TargetMachine &TM) const override; @@ -325,6 +325,8 @@ class TargetLoweringObjectFileGOFF : public TargetLoweringObjectFile { void getModuleMetadata(Module &M) override; + bool shouldPutJumpTableInFunctionSection(bool UsesLabelDifference, + const Function &F) const override; MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const override; MCSection *getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind, diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h index 35b14e8b8fd30..b69a91651e300 100644 --- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -1029,6 +1029,8 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo { /// the first time. Default value of 0 means we will use a callee-saved /// register if it is available. virtual unsigned getCSRFirstUseCost() const { return 0; } + /// FIXME: We should deprecate this usage. + virtual unsigned getCSRCost() const { return 0; } /// Returns true if the target requires (and can make use of) the register /// scavenger. diff --git a/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h b/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h index 4ffef9009e0d1..64812488923d7 100644 --- a/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h +++ b/llvm/include/llvm/DWARFLinker/Classic/DWARFStreamer.h @@ -280,6 +280,7 @@ class LLVM_ABI DwarfStreamer : public DwarfEmitter { /// \defgroup MCObjects MC layer objects constructed by the streamer /// @{ + MCTargetOptions MCOptions; std::unique_ptr MRI; std::unique_ptr MAI; std::unique_ptr MOFI; diff --git a/llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h b/llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h index 17b5bfac9ac31..7f70d4157c358 100644 --- a/llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h +++ b/llvm/include/llvm/DebugInfo/PDB/Native/FormatUtil.h @@ -61,49 +61,6 @@ LLVM_ABI std::string formatChunkKind(codeview::DebugSubsectionKind Kind, LLVM_ABI std::string formatSymbolKind(codeview::SymbolKind K); LLVM_ABI std::string formatTypeLeafKind(codeview::TypeLeafKind K); -/// Returns the number of digits in the given integer. -inline int NumDigits(uint64_t N) { - if (N < 10ULL) - return 1; - if (N < 100ULL) - return 2; - if (N < 1000ULL) - return 3; - if (N < 10000ULL) - return 4; - if (N < 100000ULL) - return 5; - if (N < 1000000ULL) - return 6; - if (N < 10000000ULL) - return 7; - if (N < 100000000ULL) - return 8; - if (N < 1000000000ULL) - return 9; - if (N < 10000000000ULL) - return 10; - if (N < 100000000000ULL) - return 11; - if (N < 1000000000000ULL) - return 12; - if (N < 10000000000000ULL) - return 13; - if (N < 100000000000000ULL) - return 14; - if (N < 1000000000000000ULL) - return 15; - if (N < 10000000000000000ULL) - return 16; - if (N < 100000000000000000ULL) - return 17; - if (N < 1000000000000000000ULL) - return 18; - if (N < 10000000000000000000ULL) - return 19; - return 20; -} - namespace detail { template struct EndianAdapter final diff --git a/llvm/include/llvm/DebugInfo/PDB/Native/InputFile.h b/llvm/include/llvm/DebugInfo/PDB/Native/InputFile.h index 71df1d59c2177..1f2c7e43002fa 100644 --- a/llvm/include/llvm/DebugInfo/PDB/Native/InputFile.h +++ b/llvm/include/llvm/DebugInfo/PDB/Native/InputFile.h @@ -183,7 +183,8 @@ Error iterateSymbolGroups(InputFile &Input, const PrintScope &HeaderScope, if (Filters.DumpModi) { uint32_t Modi = *Filters.DumpModi; SymbolGroup SG(&Input, Modi); - return iterateOneModule(Input, withLabelWidth(HeaderScope, NumDigits(Modi)), + return iterateOneModule(Input, + withLabelWidth(HeaderScope, NumDigitsBase10(Modi)), SG, Modi, Callback); } @@ -191,9 +192,9 @@ Error iterateSymbolGroups(InputFile &Input, const PrintScope &HeaderScope, for (const auto &SG : Input.symbol_groups()) { if (shouldDumpSymbolGroup(I, SG, Filters)) - if (auto Err = - iterateOneModule(Input, withLabelWidth(HeaderScope, NumDigits(I)), - SG, I, Callback)) + if (auto Err = iterateOneModule( + Input, withLabelWidth(HeaderScope, NumDigitsBase10(I)), SG, I, + Callback)) return Err; ++I; diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h index 037fcaa863fe7..f73e10c97e642 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h @@ -1482,6 +1482,9 @@ class OpenMPIRBuilder { /// \param Mergeable If the given task is `mergeable` /// \param Priority `priority-value' specifies the execution order of the /// tasks that is generated by the construct + /// \param NumOfCollapseLoops Defines the number of loops that are being + /// collapsed. The default value is 1, as thats the value when collapse is not + /// used. /// \param DupCB The callback to generate the duplication code. See /// documentation for \ref TaskDupCallbackTy. This can be nullptr. /// \param TaskContextStructPtrVal If non-null, a pointer to to be placed @@ -1494,7 +1497,8 @@ class OpenMPIRBuilder { Value *LBVal, Value *UBVal, Value *StepVal, bool Untied = false, Value *IfCond = nullptr, Value *GrainSize = nullptr, bool NoGroup = false, int Sched = 0, Value *Final = nullptr, bool Mergeable = false, - Value *Priority = nullptr, TaskDupCallbackTy DupCB = nullptr, + Value *Priority = nullptr, uint64_t NumOfCollapseLoops = 1, + TaskDupCallbackTy DupCB = nullptr, Value *TaskContextStructPtrVal = nullptr); /// Generator for `#omp task` @@ -1935,6 +1939,21 @@ class OpenMPIRBuilder { /// Get the function name of a reduction function. std::string getReductionFuncName(StringRef Name) const; + /// Generate a Fortran descriptor for array reductions + /// + /// \param DescriptorAddr Address of the descriptor to initialize + /// \param DataPtr Pointer to the actual data the descriptor should reference + /// \param ElemType Type of elements in the array (may be array type) + /// \param DescriptorType Type of the descriptor structure + /// \param DataPtrPtrGen Callback to get the base_ptr field in the descriptor + /// + /// \return Error if DataPtrPtrGen fails, otherwise success. + InsertPointOrErrorTy generateReductionDescriptor( + Value *DescriptorAddr, Value *DataPtr, Value *SrcDescriptorAddr, + Type *DescriptorType, + function_ref + DataPtrPtrGen); + /// Emits reduction function. /// \param ReducerName Name of the function calling the reduction. /// \param ReductionInfos Array type containing the ReductionOps. diff --git a/llvm/include/llvm/IR/Attributes.h b/llvm/include/llvm/IR/Attributes.h index 534d96d2c46e5..c88d230bc1321 100644 --- a/llvm/include/llvm/IR/Attributes.h +++ b/llvm/include/llvm/IR/Attributes.h @@ -47,6 +47,8 @@ class Instruction; class Type; class raw_ostream; enum FPClassTest : unsigned; +struct DenormalFPEnv; +struct DenormalMode; enum class AllocFnKind : uint64_t { Unknown = 0, @@ -341,6 +343,9 @@ class Attribute { /// Returns memory effects. LLVM_ABI MemoryEffects getMemoryEffects() const; + /// Returns denormal_fpenv. + LLVM_ABI struct DenormalFPEnv getDenormalFPEnv() const; + /// Returns information from captures attribute. LLVM_ABI CaptureInfo getCaptureInfo() const; @@ -1344,6 +1349,9 @@ class AttrBuilder { /// Add captures attribute. LLVM_ABI AttrBuilder &addCapturesAttr(CaptureInfo CI); + /// Add denormal_fpenv attribute. + LLVM_ABI AttrBuilder &addDenormalFPEnvAttr(DenormalFPEnv Mode); + // Add nofpclass attribute LLVM_ABI AttrBuilder &addNoFPClassAttr(FPClassTest NoFPClassMask); diff --git a/llvm/include/llvm/IR/Attributes.td b/llvm/include/llvm/IR/Attributes.td index e4db0e6984780..7c5457459f243 100644 --- a/llvm/include/llvm/IR/Attributes.td +++ b/llvm/include/llvm/IR/Attributes.td @@ -400,6 +400,10 @@ def CoroDestroyOnlyWhenComplete : EnumAttr<"coro_only_destroy_when_complete", In /// pipeline to perform elide on the call or invoke instruction. def CoroElideSafe : EnumAttr<"coro_elide_safe", IntersectPreserve, [FnAttr]>; +/// Indicate the denormal handling of the default floating-point +/// environment. +def DenormalFPEnv : IntAttr<"denormal_fpenv", IntersectPreserve, [FnAttr]>; + /// Function is marked for Windows Hot Patching def MarkedForWindowsSecureHotPatching : StrBoolAttr<"marked_for_windows_hot_patching">; @@ -412,7 +416,6 @@ def AllowDirectAccessInHotPatchFunction /// Target-independent string attributes. def LessPreciseFPMAD : StrBoolAttr<"less-precise-fpmad">; -def NoInfsFPMath : StrBoolAttr<"no-infs-fp-math">; def NoNansFPMath : StrBoolAttr<"no-nans-fp-math">; def NoSignedZerosFPMath : StrBoolAttr<"no-signed-zeros-fp-math">; def NoJumpTables : StrBoolAttr<"no-jump-tables">; @@ -421,9 +424,6 @@ def ProfileSampleAccurate : StrBoolAttr<"profile-sample-accurate">; def UseSampleProfile : StrBoolAttr<"use-sample-profile">; def LoaderReplaceable : StrBoolAttr<"loader-replaceable">; -def DenormalFPMath : ComplexStrAttr<"denormal-fp-math", [FnAttr]>; -def DenormalFPMathF32 : ComplexStrAttr<"denormal-fp-math-f32", [FnAttr]>; - // Attribute compatiblity rules are generated to check the attribute of the // caller and callee and decide whether inlining should be allowed. CompatRule // and child classes are used for the rule generation. CompatRule takes only a @@ -475,7 +475,6 @@ class MergeRule { } def : MergeRule<"setAND">; -def : MergeRule<"setAND">; def : MergeRule<"setAND">; def : MergeRule<"setAND">; def : MergeRule<"setOR">; diff --git a/llvm/include/llvm/IR/BasicBlock.h b/llvm/include/llvm/IR/BasicBlock.h index 07d411fcf07ae..d8d5990a9a997 100644 --- a/llvm/include/llvm/IR/BasicBlock.h +++ b/llvm/include/llvm/IR/BasicBlock.h @@ -623,9 +623,6 @@ class BasicBlock final : public Value, // Basic blocks are data objects also /// Split the basic block into two basic blocks at the specified instruction. /// - /// If \p Before is true, splitBasicBlockBefore handles the - /// block splitting. Otherwise, execution proceeds as described below. - /// /// Note that all instructions BEFORE the specified iterator /// stay as part of the original basic block, an unconditional branch is added /// to the original BB, and the rest of the instructions in the BB are moved @@ -639,11 +636,9 @@ class BasicBlock final : public Value, // Basic blocks are data objects also /// /// Also note that this doesn't preserve any passes. To split blocks while /// keeping loop information consistent, use the SplitBlock utility function. - LLVM_ABI BasicBlock *splitBasicBlock(iterator I, const Twine &BBName = "", - bool Before = false); - BasicBlock *splitBasicBlock(Instruction *I, const Twine &BBName = "", - bool Before = false) { - return splitBasicBlock(I->getIterator(), BBName, Before); + LLVM_ABI BasicBlock *splitBasicBlock(iterator I, const Twine &BBName = ""); + BasicBlock *splitBasicBlock(Instruction *I, const Twine &BBName = "") { + return splitBasicBlock(I->getIterator(), BBName); } /// Split the basic block into two basic blocks at the specified instruction diff --git a/llvm/include/llvm/IR/DIBuilder.h b/llvm/include/llvm/IR/DIBuilder.h index 9677c4b2bc200..9753c363166d9 100644 --- a/llvm/include/llvm/IR/DIBuilder.h +++ b/llvm/include/llvm/IR/DIBuilder.h @@ -49,7 +49,7 @@ namespace llvm { DICompileUnit *CUNode; ///< The one compile unit created by this DIBuiler. - SmallVector AllEnumTypes; + SmallVector EnumTypes; /// Track the RetainTypes, since they can be updated later on. SmallVector AllRetainTypes; SmallVector AllSubprograms; @@ -64,8 +64,8 @@ namespace llvm { SmallVector UnresolvedNodes; bool AllowUnresolvedNodes; - /// Each subprogram's preserved local variables, labels and imported - /// entities. + /// Each subprogram's preserved local variables, labels, imported entities, + /// and types. /// /// Do not use a std::vector. Some versions of libc++ apparently copy /// instead of move on grow operations, and TrackingMDRef is expensive to diff --git a/llvm/include/llvm/IR/DebugInfo.h b/llvm/include/llvm/IR/DebugInfo.h index 922658927ad6a..cb8f6fa1b132b 100644 --- a/llvm/include/llvm/IR/DebugInfo.h +++ b/llvm/include/llvm/IR/DebugInfo.h @@ -127,13 +127,16 @@ class DebugInfoFinder { void processScope(DIScope *Scope); void processType(DIType *DT); void processImportedEntity(const DIImportedEntity *Import); + void processMacroNode(DIMacroNode *Macro, DIMacroFile *CurrentMacroFile); bool addCompileUnit(DICompileUnit *CU); bool addGlobalVariable(DIGlobalVariableExpression *DIG); bool addScope(DIScope *Scope); bool addSubprogram(DISubprogram *SP); bool addType(DIType *DT); + bool addMacro(DIMacro *Macro, DIMacroFile *MacroFile); public: + using DIMacroEntry = std::pair; using compile_unit_iterator = SmallVectorImpl::const_iterator; using subprogram_iterator = SmallVectorImpl::const_iterator; @@ -141,6 +144,7 @@ class DebugInfoFinder { SmallVectorImpl::const_iterator; using type_iterator = SmallVectorImpl::const_iterator; using scope_iterator = SmallVectorImpl::const_iterator; + using macro_iterator = SmallVectorImpl::const_iterator; iterator_range compile_units() const { return CUs; } @@ -154,11 +158,14 @@ class DebugInfoFinder { iterator_range scopes() const { return Scopes; } + iterator_range macros() const { return Macros; } + unsigned compile_unit_count() const { return CUs.size(); } unsigned global_variable_count() const { return GVs.size(); } unsigned subprogram_count() const { return SPs.size(); } unsigned type_count() const { return TYs.size(); } unsigned scope_count() const { return Scopes.size(); } + unsigned macro_count() const { return Macros.size(); } private: SmallVector CUs; @@ -166,6 +173,7 @@ class DebugInfoFinder { SmallVector GVs; SmallVector TYs; SmallVector Scopes; + SmallVector Macros; SmallPtrSet NodesSeen; }; diff --git a/llvm/include/llvm/IR/DebugInfoMetadata.h b/llvm/include/llvm/IR/DebugInfoMetadata.h index 220b6e28fd225..3ce899db66217 100644 --- a/llvm/include/llvm/IR/DebugInfoMetadata.h +++ b/llvm/include/llvm/IR/DebugInfoMetadata.h @@ -2506,35 +2506,79 @@ class DISubprogram : public DILocalScope { /// For the given retained node of DISubprogram, applies one of the /// given functions depending on the type of the node. - template - static T - visitRetainedNode(const Metadata *N, FuncLVT &&FuncLV, FuncLabelT &&FuncLabel, - FuncImportedEntityT &&FuncIE, FuncUnknownT &&FuncUnknown) { - if (const auto *LV = dyn_cast(N)) + template + static T visitRetainedNode(MetadataT *N, FuncLVT &&FuncLV, + FuncLabelT &&FuncLabel, + FuncImportedEntityT &&FuncIE, FuncTypeT &&FuncType, + FuncUnknownT &&FuncUnknown) { + static_assert(std::is_base_of_v, + "N must point to Metadata or const Metadata"); + + if (auto *LV = dyn_cast(N)) return FuncLV(LV); - if (const auto *L = dyn_cast(N)) + if (auto *L = dyn_cast(N)) return FuncLabel(L); - if (const auto *IE = dyn_cast(N)) + if (auto *IE = dyn_cast(N)) return FuncIE(IE); + if (auto *Ty = dyn_cast(N)) + return FuncType(Ty); return FuncUnknown(N); } /// Returns the scope of subprogram's retainedNodes. static const DILocalScope *getRetainedNodeScope(const MDNode *N); + static DILocalScope *getRetainedNodeScope(MDNode *N); // For use in Verifier. static const DIScope *getRawRetainedNodeScope(const MDNode *N); + static DIScope *getRawRetainedNodeScope(MDNode *N); /// For each retained node, applies one of the given functions depending /// on the type of a node. - template + template void forEachRetainedNode(FuncLVT &&FuncLV, FuncLabelT &&FuncLabel, - FuncImportedEntityT &&FuncIE) const { + FuncImportedEntityT &&FuncIE, FuncTypeT &&FuncType) { for (MDNode *N : getRetainedNodes()) - visitRetainedNode(N, FuncLV, FuncLabel, FuncIE, - [](const Metadata *N) { - llvm_unreachable("Unexpected retained node!"); - }); + visitRetainedNode( + N, FuncLV, FuncLabel, FuncIE, FuncType, + [](auto *N) { llvm_unreachable("Unexpected retained node!"); }); + } + + /// When IR modules are merged, typically during LTO, the merged module + /// may contain several types having the same linkageName. They are + /// supposed to represent the same type included by multiple source code + /// files from a single header file. + /// + /// DebugTypeODRUniquing feature uniques (deduplicates) such types + /// based on their linkageName during metadata loading, to speed up + /// compilation and reduce debug info size. + /// + /// However, since function-local types are tracked in DISubprogram's + /// retainedNodes field, a single local type may be referenced by multiple + /// DISubprograms via retainedNodes as the result of DebugTypeODRUniquing. + /// But retainedNodes field of a DISubprogram is meant to hold only + /// subprogram's own local entities, therefore such references may + /// cause crashes. + /// + /// To address this problem, this method is called for each new subprogram + /// after module loading. It removes references to types belonging + /// to other DISubprograms from a subprogram's retainedNodes list. + /// If a corresponding IR function refers to local scopes from another + /// subprogram, emitted debug info (e.g. DWARF) should rely + /// on cross-subprogram references (and cross-CU references, as subprograms + /// may belong to different compile units). This is also a drawback: + /// when a subprogram refers to types that are local to another subprogram, + /// it is more complicated for debugger to properly discover local types + /// of a current scope for expression evaluation. + void cleanupRetainedNodes(); + + /// Calls SP->cleanupRetainedNodes() for a range of DISubprograms. + template + static void cleanupRetainedNodes(const RangeT &NewDistinctSPs) { + for (DISubprogram *SP : NewDistinctSPs) + SP->cleanupRetainedNodes(); } /// Check if this subprogram describes the given function. diff --git a/llvm/include/llvm/IR/Function.h b/llvm/include/llvm/IR/Function.h index fd94b4fd98b4e..8760e99d38169 100644 --- a/llvm/include/llvm/IR/Function.h +++ b/llvm/include/llvm/IR/Function.h @@ -49,6 +49,7 @@ class AssemblyAnnotationWriter; class Constant; class ConstantRange; class DataLayout; +struct DenormalFPEnv; struct DenormalMode; class DISubprogram; enum LibFunc : unsigned; @@ -717,14 +718,8 @@ class LLVM_ABI Function : public GlobalObject, public ilist_node { /// function. DenormalMode getDenormalMode(const fltSemantics &FPType) const; - /// Return the representational value of "denormal-fp-math". Code interested - /// in the semantics of the function should use getDenormalMode instead. - DenormalMode getDenormalModeRaw() const; - - /// Return the representational value of "denormal-fp-math-f32". Code - /// interested in the semantics of the function should use getDenormalMode - /// instead. - DenormalMode getDenormalModeF32Raw() const; + /// Return the representational value of the denormal_fpenv attribute. + DenormalFPEnv getDenormalFPEnv() const; /// copyAttributesFrom - copy all additional attributes (those not needed to /// create a Function) from the Function Src to this one. diff --git a/llvm/include/llvm/IR/IRBuilder.h b/llvm/include/llvm/IR/IRBuilder.h index 9ad9e59d9ceae..02c17575469a1 100644 --- a/llvm/include/llvm/IR/IRBuilder.h +++ b/llvm/include/llvm/IR/IRBuilder.h @@ -2294,6 +2294,13 @@ class IRBuilderBase { /// not specified. LLVM_ABI Value *CreateAggregateCast(Value *V, Type *DestTy); + /// Create a chain of casts to convert V to NewTy, preserving the bit pattern + /// of V. This may involve multiple casts (e.g., ptr -> i64 -> <2 x i32>). + /// The created cast instructions are inserted into the current basic block. + /// If no casts are needed, V is returned. + LLVM_ABI Value *CreateBitPreservingCastChain(const DataLayout &DL, Value *V, + Type *NewTy); + //===--------------------------------------------------------------------===// // Instruction creation methods: Compare Instructions //===--------------------------------------------------------------------===// diff --git a/llvm/include/llvm/IR/Intrinsics.h b/llvm/include/llvm/IR/Intrinsics.h index 2c86a43e114ea..5aecec9fd5925 100644 --- a/llvm/include/llvm/IR/Intrinsics.h +++ b/llvm/include/llvm/IR/Intrinsics.h @@ -50,7 +50,6 @@ namespace Intrinsic { // Get the intrinsic enums generated from Intrinsics.td #define GET_INTRINSIC_ENUM_VALUES #include "llvm/IR/IntrinsicEnums.inc" -#undef GET_INTRINSIC_ENUM_VALUES }; /// Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx". @@ -196,7 +195,6 @@ namespace Intrinsic { enum ArgKind { #define GET_INTRINSIC_ARGKIND #include "llvm/IR/IntrinsicEnums.inc" -#undef GET_INTRINSIC_ARGKIND }; unsigned getArgumentNumber() const { diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index ea6bd59c5aeca..46e7b4b5c9491 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -2631,6 +2631,10 @@ def int_load_relative: DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_a def int_asan_check_memaccess : Intrinsic<[],[llvm_ptr_ty, llvm_i32_ty], [ImmArg>]>; +// Spin in an infinite loop (using instructions specified by the target) iff the +// argument is true. Used to implement efficient conditional traps. +def int_cond_loop : Intrinsic<[], [llvm_i1_ty], [IntrNoMem, IntrHasSideEffects]>; + // HWASan intrinsics to test whether a pointer is addressable. //===----------------------------------------------------------------------===// // @@ -2924,6 +2928,19 @@ def int_ptrauth_resign : Intrinsic<[llvm_i64_ty], [IntrNoMem, ImmArg>, ImmArg>]>; +// Authenticate a signed pointer, load 32bit value at offset from pointer, add +// both, and sign it. The second (key) and third (discriminator) arguments +// specify the signing schema used for authenticating. The fourth and fifth +// arguments specify the schema used for signing. The sixth argument is addend +// added to pointer to load the relative offset. The signature must be valid. +// This is a combined form of int_ptrauth_resign for relative pointers +def int_ptrauth_resign_load_relative + : Intrinsic<[llvm_i64_ty], + [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty, llvm_i32_ty, + llvm_i64_ty, llvm_i64_ty], + [IntrReadMem, ImmArg>, ImmArg>, + ImmArg>]>; + // Strip the embedded signature out of a signed pointer. // The second argument specifies the key. // This behaves like @llvm.ptrauth.auth, but doesn't require the signature to diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index a8eba9ed126b7..28bd6c3409e4d 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2904,6 +2904,17 @@ class IntDSBVHStackRtn : def int_amdgcn_ds_bvh_stack_rtn : IntDSBVHStackRtn; +// Emit s_wait_event instruction. Note that between gfx11 and gfx12, +// the bit for the export_ready event changed. gfx11 expects bit 0 to +// be 0, and gfx12 expects bit 1 to be 0. Thus, an immediate value of +// 2 can be used as the universal value for export_ready. +def int_amdgcn_s_wait_event : + ClangBuiltin<"__builtin_amdgcn_s_wait_event">, + Intrinsic<[], [llvm_i16_ty], [ImmArg>, IntrNoMem, IntrHasSideEffects] +>; + +// Emits same instruction as s_wait_event, with a hardcoded immediate +// value. FIXME: This should be removed def int_amdgcn_s_wait_event_export_ready : ClangBuiltin<"__builtin_amdgcn_s_wait_event_export_ready">, Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn] @@ -4208,13 +4219,12 @@ class AMDGPULoadMonitor: Intrinsic< [llvm_any_ty], [ptr_ty, - llvm_i32_ty], // gfx12+ cachepolicy: - // bits [0-2] = th - // bits [3-4] = scope + llvm_i32_ty, // C ABI Atomic Ordering ID + llvm_metadata_ty], // syncscope [IntrArgMemOnly, IntrReadMem, ReadOnly>, NoCapture>, ImmArg>, IntrWillReturn, IntrConvergent, IntrNoCallback, IntrNoFree], "", - [SDNPMemOperand] + [SDNPMemOperand, SDNPMayLoad] >; def int_amdgcn_flat_load_monitor_b32 : AMDGPULoadMonitor; diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td index f3494450fa88f..88732bfa5a892 100644 --- a/llvm/include/llvm/IR/IntrinsicsDirectX.td +++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td @@ -180,6 +180,8 @@ def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrCon def int_dx_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>; def int_dx_wave_get_lane_count : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent]>; +def int_dx_wave_prefix_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; +def int_dx_wave_prefix_usum : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>; def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>], [IntrNoMem]>; def int_dx_splitdouble : DefaultAttrsIntrinsic<[llvm_anyint_ty, LLVMMatchType<0>], diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 873033c426873..e13d8bcede0f8 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -24,8 +24,8 @@ let TargetPrefix = "spv" in { def int_spv_unref_global : Intrinsic<[], [llvm_any_ty]>; def int_spv_gep : Intrinsic<[llvm_anyptr_ty], [llvm_i1_ty, llvm_any_ty, llvm_vararg_ty], [ImmArg>]>; - def int_spv_load : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty, llvm_i16_ty, llvm_i8_ty], [ImmArg>, ImmArg>]>; - def int_spv_store : Intrinsic<[], [llvm_any_ty, llvm_anyptr_ty, llvm_i16_ty, llvm_i8_ty], [ImmArg>, ImmArg>]>; + def int_spv_load : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty, llvm_i16_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; + def int_spv_store : Intrinsic<[], [llvm_any_ty, llvm_anyptr_ty, llvm_i16_ty, llvm_i32_ty], [ImmArg>, ImmArg>]>; def int_spv_extractv : Intrinsic<[llvm_any_ty], [llvm_i32_ty, llvm_vararg_ty]>; def int_spv_insertv : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_any_ty, llvm_vararg_ty]>; def int_spv_extractelt : Intrinsic<[llvm_any_ty], [llvm_any_ty, llvm_anyint_ty]>; @@ -35,11 +35,12 @@ let TargetPrefix = "spv" in { def int_spv_ptrcast : Intrinsic<[llvm_any_ty], [llvm_any_ty, llvm_metadata_ty, llvm_i32_ty], [ImmArg>]>; def int_spv_switch : Intrinsic<[], [llvm_any_ty, llvm_vararg_ty]>; def int_spv_loop_merge : Intrinsic<[], [llvm_vararg_ty]>; + def int_spv_loop_control_intel : Intrinsic<[], [llvm_vararg_ty]>; def int_spv_selection_merge : Intrinsic<[], [llvm_any_ty, llvm_i32_ty], [ImmArg>]>; def int_spv_cmpxchg : Intrinsic<[llvm_i32_ty], [llvm_any_ty, llvm_vararg_ty]>; def int_spv_unreachable : Intrinsic<[], []>; - def int_spv_alloca : Intrinsic<[llvm_any_ty], [llvm_i8_ty], [ImmArg>]>; - def int_spv_alloca_array : Intrinsic<[llvm_any_ty], [llvm_anyint_ty, llvm_i8_ty], [ImmArg>]>; + def int_spv_alloca : Intrinsic<[llvm_any_ty], [llvm_i32_ty], [ImmArg>]>; + def int_spv_alloca_array : Intrinsic<[llvm_any_ty], [llvm_anyint_ty, llvm_i32_ty], [ImmArg>]>; def int_spv_undef : Intrinsic<[llvm_i32_ty], []>; def int_spv_inline_asm : Intrinsic<[], [llvm_metadata_ty, llvm_metadata_ty, llvm_vararg_ty]>; @@ -132,6 +133,7 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty] def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>; def int_spv_wave_get_lane_count : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent]>; + def int_spv_wave_prefix_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>; def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; def int_spv_group_memory_barrier_with_group_sync : ClangBuiltin<"__builtin_spirv_group_barrier">, diff --git a/llvm/include/llvm/IR/ProfDataUtils.h b/llvm/include/llvm/IR/ProfDataUtils.h index 9cca8a4d2297f..5e2e94b0b6ce0 100644 --- a/llvm/include/llvm/IR/ProfDataUtils.h +++ b/llvm/include/llvm/IR/ProfDataUtils.h @@ -206,6 +206,11 @@ LLVM_ABI void setExplicitlyUnknownBranchWeightsIfProfiled(Instruction &I, StringRef PassName, const Function *F = nullptr); +/// Returns a metadata node containing unknown branch weights if the function +/// has an entry count, otherwise returns nullptr. +LLVM_ABI MDNode * +getExplicitlyUnknownBranchWeightsIfProfiled(Function &F, StringRef PassName); + /// Analogous to setExplicitlyUnknownBranchWeights, but for functions and their /// entry counts. LLVM_ABI void setExplicitlyUnknownFunctionEntryCount(Function &F, diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.td b/llvm/include/llvm/IR/RuntimeLibcalls.td index c22a3bc994457..cc7138850e0b3 100644 --- a/llvm/include/llvm/IR/RuntimeLibcalls.td +++ b/llvm/include/llvm/IR/RuntimeLibcalls.td @@ -540,6 +540,10 @@ def AEABI_MEMSET8 : RuntimeLibcall; def AEABI_MEMCLR : RuntimeLibcall; def AEABI_MEMCLR4 : RuntimeLibcall; def AEABI_MEMCLR8 : RuntimeLibcall; +def AEABI_UREAD4 : RuntimeLibcall; +def AEABI_UREAD8 : RuntimeLibcall; +def AEABI_UWRITE4 : RuntimeLibcall; +def AEABI_UWRITE8 : RuntimeLibcall; // Hexagon calls def HEXAGON_MEMCPY_LIKELY_ALIGNED_MIN32BYTES_MULT8BYTES : RuntimeLibcall; @@ -2296,6 +2300,13 @@ def __aeabi_ddiv : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS def __aeabi_dmul : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS def __aeabi_dsub : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS +// Unaligned memory access helper functions +// RTABI chapter 5.3.3 +def __aeabi_uread4 : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS +def __aeabi_uread8 : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS +def __aeabi_uwrite4 : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS +def __aeabi_uwrite8 : RuntimeLibcallImpl; // CallingConv::ARM_AAPCS + defvar AEABIOverrides = [ __eqsf2, __eqdf2, __nesf2, __nedf2, @@ -2610,6 +2621,15 @@ def AEABI45MemCalls : LibcallImpls< let CallingConv = ARM_AAPCS; } +// Unaligned Memory read/write operations +// RTABI chapter 5.3.3 +def AEABIUnalignedMemCalls : LibcallImpls< + (add __aeabi_uread4, __aeabi_uread8, + __aeabi_uwrite4, __aeabi_uwrite8), + RuntimeLibcallPredicate<[{hasAEABILibcalls(TT) && isAAPCS_ABI(TT, ABIName)}]>> { + let CallingConv = ARM_AAPCS; +} + def isARMOrThumb : RuntimeLibcallPredicate<"TT.isARM() || TT.isThumb()">; def ARMSystemLibrary @@ -2632,6 +2652,7 @@ def ARMSystemLibrary AEABICalls, AEABI45MemCalls, + AEABIUnalignedMemCalls, ARMLibgccHalfConvertCalls, EABIHalfConvertCalls, GNUEABIHalfConvertCalls, @@ -3125,6 +3146,7 @@ defset list PPC64AIXCallList = { def ___memmove64 : RuntimeLibcallImpl; def ___memset64 : RuntimeLibcallImpl; def ___bzero64 : RuntimeLibcallImpl; + def ___strcmp64 : RuntimeLibcallImpl; def ___strcpy64 : RuntimeLibcallImpl; def ___strlen64 : RuntimeLibcallImpl; def ___strstr64 : RuntimeLibcallImpl; @@ -3135,6 +3157,7 @@ defset list PPC32AIXCallList = { def ___memmove : RuntimeLibcallImpl; def ___memset : RuntimeLibcallImpl; def ___bzero : RuntimeLibcallImpl; + def ___strcmp : RuntimeLibcallImpl; def ___strcpy : RuntimeLibcallImpl; def ___strlen : RuntimeLibcallImpl; def ___strstr : RuntimeLibcallImpl; diff --git a/llvm/include/llvm/IR/SymbolTableListTraits.h b/llvm/include/llvm/IR/SymbolTableListTraits.h index e8fcab89005bb..67ffe50723333 100644 --- a/llvm/include/llvm/IR/SymbolTableListTraits.h +++ b/llvm/include/llvm/IR/SymbolTableListTraits.h @@ -16,7 +16,7 @@ // notified, allowing the symbol table to be updated. // // This generic class implements the traits class. It must be generic so that -// it can work for all uses it, which include lists of instructions, basic +// it can work for all its uses, which include lists of instructions, basic // blocks, arguments, functions, global variables, etc... // //===----------------------------------------------------------------------===// diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h index caf6ab0066d8a..801ab945730fb 100644 --- a/llvm/include/llvm/MC/MCDwarf.h +++ b/llvm/include/llvm/MC/MCDwarf.h @@ -778,13 +778,11 @@ struct MCDwarfFrameInfo { bool IsMTETaggedFrame = false; }; +// Emit DWARF call frame information and, when available, compact unwind +// information. class MCDwarfFrameEmitter { public: - // - // This emits the frame info section. - // - LLVM_ABI static void Emit(MCObjectStreamer &streamer, MCAsmBackend *MAB, - bool isEH); + LLVM_ABI static void emit(MCObjectStreamer &streamer, bool isEH); LLVM_ABI static void encodeAdvanceLoc(MCContext &Context, uint64_t AddrDelta, SmallVectorImpl &OS); }; diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h index 5da0728919673..5fc17b2b383b1 100644 --- a/llvm/include/llvm/MC/MCObjectStreamer.h +++ b/llvm/include/llvm/MC/MCObjectStreamer.h @@ -79,6 +79,7 @@ class LLVM_ABI MCObjectStreamer : public MCStreamer { bool isIntegratedAssemblerRequired() const override { return true; } void emitFrames(); + void generateCompactUnwindEncodings(); MCSymbol *emitCFILabel() override; void emitCFISections(bool EH, bool Debug, bool SFrame) override; diff --git a/llvm/include/llvm/MC/MCSection.h b/llvm/include/llvm/MC/MCSection.h index 6cb2cf64f1da7..4c36ed567de62 100644 --- a/llvm/include/llvm/MC/MCSection.h +++ b/llvm/include/llvm/MC/MCSection.h @@ -413,7 +413,6 @@ class MCSymbolIdFragment : public MCFragment { public: MCSymbolIdFragment(const MCSymbol *Sym) : MCFragment(FT_SymbolId), Sym(Sym) {} - const MCSymbol *getSymbol() { return Sym; } const MCSymbol *getSymbol() const { return Sym; } static bool classof(const MCFragment *F) { diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h index 95e719cb4ec2c..a60a3dd21859f 100644 --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -221,7 +221,6 @@ class LLVM_ABI MCStreamer { MCContext &Context; std::unique_ptr TargetStreamer; - std::vector DwarfFrameInfos; // This is a pair of index into DwarfFrameInfos and the MCSection associated // with the frame. Note, we use an index instead of an iterator because they // can be invalidated in std::vector. @@ -266,6 +265,8 @@ class LLVM_ABI MCStreamer { MCFragment *CurFrag = nullptr; + SmallVector DwarfFrameInfos; + MCStreamer(MCContext &Ctx); /// This is called by popSection and switchSection, if the current @@ -354,8 +355,6 @@ class LLVM_ABI MCStreamer { bool isInEpilogCFI() const { return CurrentWinEpilog; } - void generateCompactUnwindEncodings(MCAsmBackend *MAB); - /// \name Assembly File Formatting. /// @{ diff --git a/llvm/include/llvm/MC/MCSubtargetInfo.h b/llvm/include/llvm/MC/MCSubtargetInfo.h index 03ff85f6a8f47..708de6d98f40b 100644 --- a/llvm/include/llvm/MC/MCSubtargetInfo.h +++ b/llvm/include/llvm/MC/MCSubtargetInfo.h @@ -137,23 +137,23 @@ class LLVM_ABI MCSubtargetInfo { /// Toggle a feature and return the re-computed feature bits. /// This version does not change the implied bits. - FeatureBitset ToggleFeature(uint64_t FB); + const FeatureBitset &ToggleFeature(uint64_t FB); /// Toggle a feature and return the re-computed feature bits. /// This version does not change the implied bits. - FeatureBitset ToggleFeature(const FeatureBitset& FB); + const FeatureBitset &ToggleFeature(const FeatureBitset &FB); /// Toggle a set of features and return the re-computed feature bits. /// This version will also change all implied bits. - FeatureBitset ToggleFeature(StringRef FS); + const FeatureBitset &ToggleFeature(StringRef FS); /// Apply a feature flag and return the re-computed feature bits, including /// all feature bits implied by the flag. - FeatureBitset ApplyFeatureFlag(StringRef FS); + const FeatureBitset &ApplyFeatureFlag(StringRef FS); /// Set/clear additional feature bits, including all other bits they imply. - FeatureBitset SetFeatureBitsTransitively(const FeatureBitset& FB); - FeatureBitset ClearFeatureBitsTransitively(const FeatureBitset &FB); + const FeatureBitset &SetFeatureBitsTransitively(const FeatureBitset &FB); + const FeatureBitset &ClearFeatureBitsTransitively(const FeatureBitset &FB); /// Check whether the subtarget features are enabled/disabled as per /// the provided string, ignoring all other features. diff --git a/llvm/include/llvm/MC/MCSymbol.h b/llvm/include/llvm/MC/MCSymbol.h index eef248354b70f..8f59b110355e2 100644 --- a/llvm/include/llvm/MC/MCSymbol.h +++ b/llvm/include/llvm/MC/MCSymbol.h @@ -307,7 +307,6 @@ class MCSymbol { /// /// \param Size - The size of the symbol. /// \param Alignment - The alignment of the symbol. - /// \param Target - Is the symbol a target-specific common-like symbol. void setCommon(uint64_t Size, Align Alignment) { assert(getOffset() == 0); CommonSize = Size; diff --git a/llvm/include/llvm/MC/TargetRegistry.h b/llvm/include/llvm/MC/TargetRegistry.h index 234c587c8e951..4451dfa72a5f4 100644 --- a/llvm/include/llvm/MC/TargetRegistry.h +++ b/llvm/include/llvm/MC/TargetRegistry.h @@ -389,15 +389,6 @@ class Target { /// @name Feature Constructors /// @{ - // TODO(boomanaiden154): Remove this function after LLVM 22 branches. - [[deprecated("Use overload accepting Triple instead")]] - MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple, - const MCTargetOptions &Options) const { - if (!MCAsmInfoCtorFn) - return nullptr; - return MCAsmInfoCtorFn(MRI, Triple(TheTriple), Options); - } - /// Create a MCAsmInfo implementation for the specified /// target triple. /// @@ -441,14 +432,6 @@ class Target { return MCInstrAnalysisCtorFn(Info); } - // TODO(boomanaiden154): Remove this function after LLVM 22 branches. - [[deprecated("Use overload accepting Triple instead")]] - MCRegisterInfo *createMCRegInfo(StringRef TT) const { - if (!MCRegInfoCtorFn) - return nullptr; - return MCRegInfoCtorFn(Triple(TT)); - } - /// Create a MCRegisterInfo implementation. MCRegisterInfo *createMCRegInfo(const Triple &TT) const { if (!MCRegInfoCtorFn) @@ -456,15 +439,6 @@ class Target { return MCRegInfoCtorFn(TT); } - // TODO(boomanaiden154): Remove this function after LLVM 22 branches. - [[deprecated("Use overload accepting Triple instead")]] - MCSubtargetInfo *createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, - StringRef Features) const { - if (!MCSubtargetInfoCtorFn) - return nullptr; - return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features); - } - /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. /// /// \param TheTriple This argument is used to determine the target machine @@ -592,12 +566,6 @@ class Target { return nullptr; } - // TODO(boomanaiden154): Remove this function after LLVM 22 branches. - [[deprecated("Use overload accepting Triple instead")]] - MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx) const { - return createMCRelocationInfo(Triple(TT), Ctx); - } - /// createMCRelocationInfo - Create a target specific MCRelocationInfo. /// /// \param TT The target triple. @@ -610,17 +578,6 @@ class Target { return Fn(TT, Ctx); } - // TODO(boomanaiden154): Remove this function after LLVM 22 branches. - [[deprecated("Use overload accepting Triple instead")]] - MCSymbolizer * - createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, - LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, - MCContext *Ctx, - std::unique_ptr &&RelInfo) const { - return createMCSymbolizer(Triple(TT), GetOpInfo, SymbolLookUp, DisInfo, Ctx, - std::move(RelInfo)); - } - /// createMCSymbolizer - Create a target specific MCSymbolizer. /// /// \param TT The target triple. diff --git a/llvm/include/llvm/Object/ELFTypes.h b/llvm/include/llvm/Object/ELFTypes.h index 467ab6fd3c1e9..14a50646acc71 100644 --- a/llvm/include/llvm/Object/ELFTypes.h +++ b/llvm/include/llvm/Object/ELFTypes.h @@ -10,6 +10,7 @@ #define LLVM_OBJECT_ELFTYPES_H #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/BitmaskEnum.h" #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/Object/Error.h" @@ -25,6 +26,19 @@ #include namespace llvm { + +namespace callgraph { +// ELF call graph section entry Flag field supported values. +LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE(); +enum Flags : uint8_t { + None = 0, + IsIndirectTarget = 1u << 0, + HasDirectCallees = 1u << 1, + HasIndirectCallees = 1u << 2, + LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/HasIndirectCallees) +}; +} // namespace callgraph + namespace object { template struct Elf_Ehdr_Impl; diff --git a/llvm/include/llvm/Object/OffloadBinary.h b/llvm/include/llvm/Object/OffloadBinary.h index f3847c1624977..ff9c7d0d82dc2 100644 --- a/llvm/include/llvm/Object/OffloadBinary.h +++ b/llvm/include/llvm/Object/OffloadBinary.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the binary format used for budingling device metadata with +// This file contains the binary format used for bundling device metadata with // an associated device image. The data can then be stored inside a host object // file to create a fat binary and read by the linker. This is intended to be a // thin wrapper around the image itself. If this format becomes sufficiently @@ -52,6 +52,13 @@ enum ImageKind : uint16_t { IMG_LAST, }; +/// Flags associated with the Entry. +enum OffloadEntryFlags : uint32_t { + OIF_None = 0, + // Entry doesn't contain an image. Used to keep metadata only entries. + OIF_Metadata = (1 << 0), +}; + /// A simple binary serialization of an offloading file. We use this format to /// embed the offloading image into the host executable so it can be extracted /// and used by the linker. @@ -67,7 +74,7 @@ class OffloadBinary : public Binary { using string_iterator_range = iterator_range; /// The current version of the binary used for backwards compatibility. - static const uint32_t Version = 1; + static const uint32_t Version = 2; /// The offloading metadata that will be serialized to a memory buffer. struct OffloadingImage { @@ -78,12 +85,57 @@ class OffloadBinary : public Binary { std::unique_ptr Image; }; - /// Attempt to parse the offloading binary stored in \p Data. - LLVM_ABI static Expected> - create(MemoryBufferRef); + struct Header { + uint8_t Magic[4] = {0x10, 0xFF, 0x10, 0xAD}; // 0x10FF10AD magic bytes. + uint32_t Version = OffloadBinary::Version; // Version identifier. + uint64_t Size; // Size in bytes of this entire binary. + uint64_t EntriesOffset; // Offset in bytes to the start of entries block. + uint64_t EntriesCount; // Number of metadata entries in the binary. + }; + + struct Entry { + ImageKind TheImageKind; // The kind of the image stored. + OffloadKind TheOffloadKind; // The producer of this image. + uint32_t Flags; // Additional flags associated with the entry. + uint64_t StringOffset; // Offset in bytes to the string map. + uint64_t NumStrings; // Number of entries in the string map. + uint64_t ImageOffset; // Offset in bytes of the actual binary image. + uint64_t ImageSize; // Size in bytes of the binary image. + }; - /// Serialize the contents of \p File to a binary buffer to be read later. - LLVM_ABI static SmallString<0> write(const OffloadingImage &); + struct StringEntry { + uint64_t KeyOffset; + uint64_t ValueOffset; + uint64_t ValueSize; // Size of the value in bytes. + }; + + struct StringEntryV1 { + uint64_t KeyOffset; + uint64_t ValueOffset; + }; + + /// Attempt to extract and validate the header from the offloading binary in + /// \p Buf. + LLVM_ABI + static Expected extractHeader(MemoryBufferRef Buf); + + /// Attempt to parse the offloading binary stored in \p Buf. + /// For version 1 binaries, always returns a single OffloadBinary. + /// For version 2+ binaries: + /// - If \p Index is provided, returns the OffloadBinary at that index. + /// - If \p Index is std::nullopt, returns all OffloadBinary entries. + /// \param Buf The memory buffer containing the offload binary. + /// \param Index Optional index to select a specific entry. If not provided, + /// all entries are returned (version 2+ only). + /// \returns An array of unique pointers to OffloadBinary objects, or an + /// error. + LLVM_ABI static Expected>> + create(MemoryBufferRef Buf, std::optional Index = std::nullopt); + + /// Serialize the contents of \p OffloadingData to a binary buffer to be read + /// later. + LLVM_ABI static SmallString<0> + write(ArrayRef OffloadingData); static uint64_t getAlignment() { return 8; } @@ -92,6 +144,7 @@ class OffloadBinary : public Binary { uint32_t getVersion() const { return TheHeader->Version; } uint32_t getFlags() const { return TheEntry->Flags; } uint64_t getSize() const { return TheHeader->Size; } + uint64_t getIndex() const { return Index; } StringRef getTriple() const { return getString("triple"); } StringRef getArch() const { return getString("arch"); } @@ -106,39 +159,29 @@ class OffloadBinary : public Binary { static bool classof(const Binary *V) { return V->isOffloadFile(); } - struct Header { - uint8_t Magic[4] = {0x10, 0xFF, 0x10, 0xAD}; // 0x10FF10AD magic bytes. - uint32_t Version = OffloadBinary::Version; // Version identifier. - uint64_t Size; // Size in bytes of this entire binary. - uint64_t EntryOffset; // Offset of the metadata entry in bytes. - uint64_t EntrySize; // Size of the metadata entry in bytes. - }; - - struct Entry { - ImageKind TheImageKind; // The kind of the image stored. - OffloadKind TheOffloadKind; // The producer of this image. - uint32_t Flags; // Additional flags associated with the image. - uint64_t StringOffset; // Offset in bytes to the string map. - uint64_t NumStrings; // Number of entries in the string map. - uint64_t ImageOffset; // Offset in bytes of the actual binary image. - uint64_t ImageSize; // Size in bytes of the binary image. - }; - - struct StringEntry { - uint64_t KeyOffset; - uint64_t ValueOffset; - }; - private: OffloadBinary(MemoryBufferRef Source, const Header *TheHeader, - const Entry *TheEntry) + const Entry *TheEntry, const uint64_t Index = 0) : Binary(Binary::ID_Offload, Source), Buffer(Source.getBufferStart()), - TheHeader(TheHeader), TheEntry(TheEntry) { - const StringEntry *StringMapBegin = - reinterpret_cast(&Buffer[TheEntry->StringOffset]); + TheHeader(TheHeader), TheEntry(TheEntry), Index(Index) { + // StringEntryV1 and StringEntry have ABI compatible Key/ValueOffset fields, + // but different sizes, so we need to manually calculate offset. + const char *StringMapBegin = &Buffer[TheEntry->StringOffset]; + const size_t StringEntrySize = + TheHeader->Version == 1 ? sizeof(StringEntryV1) : sizeof(StringEntry); for (uint64_t I = 0, E = TheEntry->NumStrings; I != E; ++I) { - StringRef Key = &Buffer[StringMapBegin[I].KeyOffset]; - StringData[Key] = &Buffer[StringMapBegin[I].ValueOffset]; + const char *StringEntryPtr = StringMapBegin + I * StringEntrySize; + const StringEntryV1 *EntryV1 = + reinterpret_cast(StringEntryPtr); + StringRef Key = &Buffer[EntryV1->KeyOffset]; + if (TheHeader->Version == 1) { + StringData[Key] = &Buffer[EntryV1->ValueOffset]; + } else { + const StringEntry *Entry = + reinterpret_cast(StringEntryPtr); + StringData[Key] = + StringRef(&Buffer[Entry->ValueOffset], Entry->ValueSize); + } } } @@ -152,10 +195,13 @@ class OffloadBinary : public Binary { const Header *TheHeader; /// Location of the metadata entries within the binary. const Entry *TheEntry; + /// Index of the entry in the list of entries serialized in the Buffer. + const uint64_t Index; }; -/// A class to contain the binary information for a single OffloadBinary that -/// owns its memory. +/// A class to contain the binary information for a single OffloadBinary. +/// Memory is shared between multiple OffloadBinary instances read from +/// the single serialized offload binary. class OffloadFile : public OwningBinary { public: using TargetID = std::pair; @@ -171,11 +217,12 @@ class OffloadFile : public OwningBinary { getBinary()->getMemoryBufferRef().getBufferIdentifier()); // This parsing should never fail because it has already been parsed. - auto NewBinaryOrErr = OffloadBinary::create(*Buffer); + auto NewBinaryOrErr = + OffloadBinary::create(*Buffer, getBinary()->getIndex()); assert(NewBinaryOrErr && "Failed to parse a copy of the binary?"); if (!NewBinaryOrErr) llvm::consumeError(NewBinaryOrErr.takeError()); - return OffloadFile(std::move(*NewBinaryOrErr), std::move(Buffer)); + return OffloadFile(std::move((*NewBinaryOrErr)[0]), std::move(Buffer)); } /// We use the Triple and Architecture pair to group linker inputs together. diff --git a/llvm/include/llvm/ObjectYAML/OffloadYAML.h b/llvm/include/llvm/ObjectYAML/OffloadYAML.h index f897b52aa8b0e..63ff561f3fcbf 100644 --- a/llvm/include/llvm/ObjectYAML/OffloadYAML.h +++ b/llvm/include/llvm/ObjectYAML/OffloadYAML.h @@ -39,8 +39,8 @@ struct Binary { std::optional Version; std::optional Size; - std::optional EntryOffset; - std::optional EntrySize; + std::optional EntriesOffset; + std::optional EntriesCount; std::vector Members; }; diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 6942fc42ca721..68d13fefd7d8b 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -472,7 +472,7 @@ template class CodeGenPassBuilder { /// addOptimizedRegAlloc - Add passes related to register allocation. /// CodeGenTargetMachineImpl provides standard regalloc passes for most /// targets. - void addOptimizedRegAlloc(PassManagerWrapper &PMW) const; + Error addOptimizedRegAlloc(PassManagerWrapper &PMW) const; /// Add passes that optimize machine instructions after register allocation. void addMachineLateOptimization(PassManagerWrapper &PMW) const; @@ -505,10 +505,10 @@ template class CodeGenPassBuilder { /// regalloc pass. void addRegAllocPass(PassManagerWrapper &PMW, bool Optimized) const; - /// Add core register alloator passes which do the actual register assignment - /// and rewriting. \returns true if any passes were added. + /// Add core register allocator passes which do the actual register assignment + /// and rewriting. Error addRegAssignmentFast(PassManagerWrapper &PMW) const; - Error addRegAssignmentOptimized(PassManagerWrapper &PMWM) const; + Error addRegAssignmentOptimized(PassManagerWrapper &PMW) const; /// Allow the target to disable a specific pass by default. /// Backend can declare unwanted passes in constructor. @@ -977,12 +977,9 @@ Error CodeGenPassBuilder::addMachinePasses( // Run register allocation and passes that are tightly coupled with it, // including phi elimination and scheduling. - if (*Opt.OptimizeRegAlloc) { - derived().addOptimizedRegAlloc(PMW); - } else { - if (auto Err = derived().addFastRegAlloc(PMW)) - return Err; - } + if (auto Err = *Opt.OptimizeRegAlloc ? derived().addOptimizedRegAlloc(PMW) + : derived().addFastRegAlloc(PMW)) + return std::move(Err); // Run post-ra passes. derived().addPostRegAlloc(PMW); @@ -1212,7 +1209,7 @@ Error CodeGenPassBuilder::addFastRegAlloc( /// optimized register allocation, including coalescing, machine instruction /// scheduling, and register allocation itself. template -void CodeGenPassBuilder::addOptimizedRegAlloc( +Error CodeGenPassBuilder::addOptimizedRegAlloc( PassManagerWrapper &PMW) const { addMachineFunctionPass(DetectDeadLanesPass(), PMW); @@ -1255,10 +1252,8 @@ void CodeGenPassBuilder::addOptimizedRegAlloc( // PreRA instruction scheduling. addMachineFunctionPass(MachineSchedulerPass(&TM), PMW); - if (auto E = derived().addRegAssignmentOptimized(PMW)) { - // addRegAssignmentOptimized did not add a reg alloc pass, so do nothing. - return; - } + if (auto E = derived().addRegAssignmentOptimized(PMW)) + return std::move(E); addMachineFunctionPass(StackSlotColoringPass(), PMW); @@ -1274,6 +1269,8 @@ void CodeGenPassBuilder::addOptimizedRegAlloc( // // FIXME: can this move into MachineLateOptimization? addMachineFunctionPass(MachineLICMPass(), PMW); + + return Error::success(); } //===---------------------------------------------------------------------===// diff --git a/llvm/include/llvm/Support/KnownBits.h b/llvm/include/llvm/Support/KnownBits.h index a8756a4eedba2..2ac4d330714a1 100644 --- a/llvm/include/llvm/Support/KnownBits.h +++ b/llvm/include/llvm/Support/KnownBits.h @@ -160,6 +160,9 @@ struct KnownBits { return Max; } + /// Return if the value is known even (the low bit is 0). + bool isEven() const { return Zero[0]; } + /// Return known bits for a truncation of the value we're tracking. KnownBits trunc(unsigned BitWidth) const { return KnownBits(Zero.trunc(BitWidth), One.trunc(BitWidth)); diff --git a/llvm/include/llvm/Support/KnownFPClass.h b/llvm/include/llvm/Support/KnownFPClass.h index 6409a7e44a116..46dd99ff59796 100644 --- a/llvm/include/llvm/Support/KnownFPClass.h +++ b/llvm/include/llvm/Support/KnownFPClass.h @@ -21,6 +21,7 @@ namespace llvm { class APFloat; struct fltSemantics; +struct KnownBits; struct KnownFPClass { /// Floating-point classes the value could be one of. @@ -390,6 +391,15 @@ struct KnownFPClass { static LLVM_ABI KnownFPClass frexp_mant( const KnownFPClass &Src, DenormalMode Mode = DenormalMode::getDynamic()); + /// Propagate known class for ldexp + static LLVM_ABI KnownFPClass + ldexp(const KnownFPClass &Src, const KnownBits &N, const fltSemantics &Flt, + DenormalMode Mode = DenormalMode::getDynamic()); + + /// Propagate known class for powi + static LLVM_ABI KnownFPClass powi(const KnownFPClass &Src, + const KnownBits &N); + void resetAll() { *this = KnownFPClass(); } }; diff --git a/llvm/include/llvm/Support/MathExtras.h b/llvm/include/llvm/Support/MathExtras.h index 0a253efc2abcb..de2813094a950 100644 --- a/llvm/include/llvm/Support/MathExtras.h +++ b/llvm/include/llvm/Support/MathExtras.h @@ -786,6 +786,9 @@ using stack_float_t = volatile float; using stack_float_t = float; #endif +/// Returns the number of digits in the given integer. +int NumDigitsBase10(uint64_t X); + } // namespace llvm #endif diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 3217ffafc235a..e1809e364ad83 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -61,14 +61,14 @@ HANDLE_TARGET_OPCODE(IMPLICIT_DEF) /// early-clobber result operand. HANDLE_TARGET_OPCODE(INIT_UNDEF) -/// SUBREG_TO_REG - Assert the value of bits in a super register. -/// The result of this instruction is the value of the second operand inserted -/// into the subregister specified by the third operand. All other bits are -/// assumed to be equal to the bits in the immediate integer constant in the -/// first operand. This instruction just communicates information; No code -/// should be generated. -/// This is typically used after an instruction where the write to a subregister -/// implicitly cleared the bits in the super registers. +/// SUBREG_TO_REG - Expose the value of bits in a super register. +/// This is typically used after an instruction which writes its result to a +/// subregister but also, as a side effect, writes some value (often zero) into +/// a larger super register. +/// The result of this instruction is the value of the first operand inserted +/// into the subregister specified by the second operand. All other bits are +/// left undefined or however they were set by the preceding instruction. +/// This instruction just communicates information; No code should be generated. HANDLE_TARGET_OPCODE(SUBREG_TO_REG) /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain diff --git a/llvm/include/llvm/TableGen/CodeGenHelpers.h b/llvm/include/llvm/TableGen/CodeGenHelpers.h index 41b0adc49d1ad..e8e4886b0eefa 100644 --- a/llvm/include/llvm/TableGen/CodeGenHelpers.h +++ b/llvm/include/llvm/TableGen/CodeGenHelpers.h @@ -106,10 +106,21 @@ class NamespaceEmitter { Name.consume_front("::"); return Name; } + std::string Name; raw_ostream &OS; }; +// Simple RAII helper for emitting anonymous namespace scope. +class AnonNamespaceEmitter { +public: + AnonNamespaceEmitter(raw_ostream &OS) : OS(OS) { OS << "namespace {\n\n"; } + ~AnonNamespaceEmitter() { OS << "} // namespace\n"; } + +private: + raw_ostream &OS; +}; + } // end namespace llvm #endif // LLVM_TABLEGEN_CODEGENHELPERS_H diff --git a/llvm/include/llvm/Target/GlobalISel/Target.td b/llvm/include/llvm/Target/GlobalISel/Target.td index dd21efe077416..93b676470244e 100644 --- a/llvm/include/llvm/Target/GlobalISel/Target.td +++ b/llvm/include/llvm/Target/GlobalISel/Target.td @@ -22,8 +22,11 @@ class LLT; def s32 : LLT; def s64 : LLT; +def v2s64 : LLT; def v2s32 : LLT; +def v4s32 : LLT; def v4s16 : LLT; +def v8s16 : LLT; def v8s8 : LLT; // Defines a matcher for complex operands. This is analogous to ComplexPattern diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td index abe3a7d1701ee..3d3cfe6948ded 100644 --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -1291,7 +1291,7 @@ def INIT_UNDEF : StandardPseudoInstruction { } def SUBREG_TO_REG : StandardPseudoInstruction { let OutOperandList = (outs unknown:$dst); - let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); + let InOperandList = (ins unknown:$subsrc, i32imm:$subidx); let AsmString = ""; let hasSideEffects = false; } diff --git a/llvm/include/llvm/Target/TargetLoweringObjectFile.h b/llvm/include/llvm/Target/TargetLoweringObjectFile.h index 06508bf4d50af..3fa575f66042a 100644 --- a/llvm/include/llvm/Target/TargetLoweringObjectFile.h +++ b/llvm/include/llvm/Target/TargetLoweringObjectFile.h @@ -269,7 +269,7 @@ class LLVM_ABI TargetLoweringObjectFile : public MCObjectFileInfo { /// On targets that use separate function descriptor symbols, return a section /// for the descriptor given its symbol. Use only with defined functions. virtual MCSection * - getSectionForFunctionDescriptor(const Function *F, + getSectionForFunctionDescriptor(const GlobalObject *F, const TargetMachine &TM) const { return nullptr; } diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index d0fd483a8ddaa..800d398505785 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -538,6 +538,11 @@ class LLVM_ABI TargetMachine { const SmallPtrSetImpl &MIs) const { return 0; } + + /// Returns whether the backend can lower the llvm.cond.loop intrinsic. If + /// this function returns false, the intrinsic will be supported generically + /// but without loop detection support. + virtual bool canLowerCondLoop() const { return false; } }; } // end namespace llvm diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h index a9b86626cf598..e38ec301ff091 100644 --- a/llvm/include/llvm/Target/TargetOptions.h +++ b/llvm/include/llvm/Target/TargetOptions.h @@ -119,8 +119,8 @@ enum CodeObjectVersionKind { class TargetOptions { public: TargetOptions() - : NoInfsFPMath(false), NoNaNsFPMath(false), NoTrappingFPMath(true), - NoSignedZerosFPMath(false), EnableAIXExtendedAltivecABI(false), + : NoNaNsFPMath(false), NoTrappingFPMath(true), NoSignedZerosFPMath(false), + EnableAIXExtendedAltivecABI(false), HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false), GuaranteedTailCallOpt(false), StackSymbolOrdering(true), EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false), @@ -155,12 +155,6 @@ class TargetOptions { /// MCAsmInfo::BinutilsVersion. std::pair BinutilsVersion{0, 0}; - /// NoInfsFPMath - This flag is enabled when the - /// -enable-no-infs-fp-math flag is specified on the command line. When - /// this flag is off (the default), the code generator is not allowed to - /// assume the FP arithmetic arguments and results are never +-Infs. - unsigned NoInfsFPMath : 1; - /// NoNaNsFPMath - This flag is enabled when the /// -enable-no-nans-fp-math flag is specified on the command line. When /// this flag is off (the default), the code generator is not allowed to diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td index b297fd06711a5..62f1cee1cf1ac 100644 --- a/llvm/include/llvm/Target/TargetSelectionDAG.td +++ b/llvm/include/llvm/Target/TargetSelectionDAG.td @@ -918,6 +918,10 @@ def convergencectrl_loop : SDNode<"ISD::CONVERGENCECTRL_LOOP", def convergencectrl_glue : SDNode<"ISD::CONVERGENCECTRL_GLUE", SDTypeProfile<0, 1, [SDTCisVT<0, untyped>]>>; +def sponentry : SDNode< + "ISD::SPONENTRY", SDTypeProfile <1, 0, [SDTCisPtrTy<0>]> +>; + //===----------------------------------------------------------------------===// // Selection DAG Condition Codes diff --git a/llvm/include/llvm/TargetParser/AVRTargetParser.h b/llvm/include/llvm/TargetParser/AVRTargetParser.h new file mode 100644 index 0000000000000..6a44448d7b046 --- /dev/null +++ b/llvm/include/llvm/TargetParser/AVRTargetParser.h @@ -0,0 +1,28 @@ +//===-- AVRTargetParser - Parser for AVR target features ------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements a target parser to recognise AVR hardware features. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_TARGETPARSER_AVRTARGETPARSER_H +#define LLVM_TARGETPARSER_AVRTARGETPARSER_H + +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/Error.h" +#include + +namespace llvm { +namespace AVR { + +LLVM_ABI Expected getFeatureSetFromEFlag(const unsigned EFlag); + +} // namespace AVR +} // namespace llvm +#endif diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h index 0b4c45e445bb6..b0ed9efcb9d82 100644 --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -16,6 +16,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/Error.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" @@ -47,6 +48,22 @@ struct CPUInfo { bool is64Bit() const { return DefaultMarch.starts_with("rv64"); } }; +/// Fatal errors encountered during parsing. +struct ParserError : public ErrorInfo { + using ErrorInfo::ErrorInfo; + explicit ParserError(const Twine &S) + : ErrorInfo(S, inconvertibleErrorCode()) {} + static char ID; +}; + +/// Warnings encountered during parsing. +struct ParserWarning : public ErrorInfo { + using ErrorInfo::ErrorInfo; + explicit ParserWarning(const Twine &S) + : ErrorInfo(S, inconvertibleErrorCode()) {} + static char ID; +}; + // We use 64 bits as the known part in the scalable vector types. static constexpr unsigned RVVBitsPerBlock = 64; static constexpr unsigned RVVBytesPerBlock = RVVBitsPerBlock / 8; @@ -54,6 +71,15 @@ static constexpr unsigned RVVBytesPerBlock = RVVBitsPerBlock / 8; LLVM_ABI void getFeaturesForCPU(StringRef CPU, SmallVectorImpl &EnabledFeatures, bool NeedPlus = false); +LLVM_ABI void getAllTuneFeatures(SmallVectorImpl &TuneFeatures); +LLVM_ABI void +getCPUConfigurableTuneFeatures(StringRef CPU, + SmallVectorImpl &Directives); +/// Parse the tune feature string with the respective processor. If \p ProcName +/// is empty, directives are not filtered by processor. +LLVM_ABI Error +parseTuneFeatureString(StringRef ProcName, StringRef TFString, + SmallVectorImpl &TuneFeatures); LLVM_ABI bool parseCPU(StringRef CPU, bool IsRV64); LLVM_ABI bool parseTuneCPU(StringRef CPU, bool IsRV64); LLVM_ABI StringRef getMArchFromMcpu(StringRef CPU); diff --git a/llvm/include/llvm/TargetParser/TargetParser.h b/llvm/include/llvm/TargetParser/TargetParser.h index 96bf367eff2c0..0cb588dedfd02 100644 --- a/llvm/include/llvm/TargetParser/TargetParser.h +++ b/llvm/include/llvm/TargetParser/TargetParser.h @@ -110,6 +110,8 @@ enum GPUKind : uint32_t { GK_GFX1152, GK_GFX1153, + GK_GFX1170, + GK_GFX1200, GK_GFX1201, GK_GFX1250, diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 8559d7b088ee1..b082ed05d8358 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -253,7 +253,8 @@ class Triple { Vulkan, // Vulkan SPIR-V CheriotRTOS, ChipStar, - LastOSType = ChipStar + Firmware, + LastOSType = Firmware }; enum EnvironmentType { UnknownEnvironment, @@ -627,11 +628,18 @@ class Triple { return (getVendor() == Triple::Apple) && isOSBinFormatMachO(); } + /// Is this an Apple firmware triple. + bool isAppleFirmware() const { + return (getVendor() == Triple::Apple) && isOSFirmware(); + } + /// Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, DriverKit, XROS, or /// bridgeOS). bool isOSDarwin() const { return isMacOSX() || isiOS() || isWatchOS() || isDriverKit() || isXROS() || - isBridgeOS(); + isBridgeOS() || isAppleFirmware(); + // Apple firmware isn't necessarily a Darwin based OS, but for most intents + // and purposes it can be treated like a Darwin OS in the compiler. } bool isSimulatorEnvironment() const { @@ -893,6 +901,8 @@ class Triple { bool isOSManagarm() const { return getOS() == Triple::Managarm; } + bool isOSFirmware() const { return getOS() == Triple::Firmware; } + bool isShaderStageEnvironment() const { EnvironmentType Env = getEnvironment(); return Env == Triple::Pixel || Env == Triple::Vertex || @@ -1048,6 +1058,8 @@ class Triple { : PointerWidth == 64; } + bool isAVR() const { return getArch() == Triple::avr; } + /// Tests whether the target is 32-bit LoongArch. bool isLoongArch32() const { return getArch() == Triple::loongarch32; } diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def index 09592bcea27f4..bc05452400458 100644 --- a/llvm/include/llvm/TargetParser/X86TargetParser.def +++ b/llvm/include/llvm/TargetParser/X86TargetParser.def @@ -107,6 +107,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE, "arrowlake") X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE_S, "arrowlake-s") X86_CPU_SUBTYPE(INTEL_COREI7_PANTHERLAKE, "pantherlake") X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5, "znver5") +X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER6, "znver6") X86_CPU_SUBTYPE(INTEL_COREI7_DIAMONDRAPIDS, "diamondrapids") X86_CPU_SUBTYPE(INTEL_COREI7_NOVALAKE, "novalake") diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.h b/llvm/include/llvm/TargetParser/X86TargetParser.h index 46061f9d1fc7d..31d13ce29f7fc 100644 --- a/llvm/include/llvm/TargetParser/X86TargetParser.h +++ b/llvm/include/llvm/TargetParser/X86TargetParser.h @@ -146,6 +146,7 @@ enum CPUKind { CK_ZNVER3, CK_ZNVER4, CK_ZNVER5, + CK_ZNVER6, CK_x86_64, CK_x86_64_v2, CK_x86_64_v3, diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h index eb35e3644bd02..f2657a338ba76 100644 --- a/llvm/include/llvm/Transforms/IPO/Attributor.h +++ b/llvm/include/llvm/Transforms/IPO/Attributor.h @@ -6593,7 +6593,7 @@ struct AAIndirectCallInfo }; /// An abstract Attribute for specializing "dynamic" components of -/// "denormal-fp-math" and "denormal-fp-math-f32" to a known denormal mode. +/// denormal_fpenv to a known denormal mode. struct AADenormalFPMath : public StateWrapper { using Base = StateWrapper; @@ -6625,7 +6625,11 @@ enum AttributorRunOption { NONE = 0, MODULE = 1 << 0, CGSCC = 1 << 1, - ALL = MODULE | CGSCC + MODULE_LIGHT = 1 << 2, + CGSCC_LIGHT = 1 << 3, + + FULL = MODULE | CGSCC, + LIGHT = MODULE_LIGHT | CGSCC_LIGHT }; namespace AA { diff --git a/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h b/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h index a34cbaf72675b..bb8b40955077e 100644 --- a/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h +++ b/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h @@ -218,6 +218,7 @@ class LowerTypeTestsPass : public PassInfoMixin { lowertypetests::DropTestKind::None) : ExportSummary(ExportSummary), ImportSummary(ImportSummary), DropTypeTests(DropTypeTests) {} + static bool isRequired() { return true; } LLVM_ABI PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); }; diff --git a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h index c951597498033..8a80e7f1d8e9b 100644 --- a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h +++ b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h @@ -315,9 +315,6 @@ ehAwareSplitEdge(BasicBlock *BB, BasicBlock *Succ, /// Split the specified block at the specified instruction. /// -/// If \p Before is true, splitBlockBefore handles the block -/// splitting. Otherwise, execution proceeds as described below. -/// /// Everything before \p SplitPt stays in \p Old and everything starting with \p /// SplitPt moves to a new block. The two blocks are joined by an unconditional /// branch. The new block with name \p BBName is returned. @@ -326,19 +323,16 @@ ehAwareSplitEdge(BasicBlock *BB, BasicBlock *Succ, LLVM_ABI BasicBlock *SplitBlock(BasicBlock *Old, BasicBlock::iterator SplitPt, DominatorTree *DT, LoopInfo *LI = nullptr, MemorySSAUpdater *MSSAU = nullptr, - const Twine &BBName = "", bool Before = false); -inline BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt, DominatorTree *DT, - LoopInfo *LI = nullptr, - MemorySSAUpdater *MSSAU = nullptr, - const Twine &BBName = "", bool Before = false) { - return SplitBlock(Old, SplitPt->getIterator(), DT, LI, MSSAU, BBName, Before); + const Twine &BBName = ""); +inline BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt, + DominatorTree *DT, LoopInfo *LI = nullptr, + MemorySSAUpdater *MSSAU = nullptr, + const Twine &BBName = "") { + return SplitBlock(Old, SplitPt->getIterator(), DT, LI, MSSAU, BBName); } /// Split the specified block at the specified instruction. /// -/// If \p Before is true, splitBlockBefore handles the block -/// splitting. Otherwise, execution proceeds as described below. -/// /// Everything before \p SplitPt stays in \p Old and everything starting with \p /// SplitPt moves to a new block. The two blocks are joined by an unconditional /// branch. The new block with name \p BBName is returned. @@ -346,12 +340,13 @@ LLVM_ABI BasicBlock *SplitBlock(BasicBlock *Old, BasicBlock::iterator SplitPt, DomTreeUpdater *DTU = nullptr, LoopInfo *LI = nullptr, MemorySSAUpdater *MSSAU = nullptr, - const Twine &BBName = "", bool Before = false); + const Twine &BBName = ""); inline BasicBlock *SplitBlock(BasicBlock *Old, Instruction *SplitPt, - DomTreeUpdater *DTU = nullptr, LoopInfo *LI = nullptr, - MemorySSAUpdater *MSSAU = nullptr, - const Twine &BBName = "", bool Before = false) { - return SplitBlock(Old, SplitPt->getIterator(), DTU, LI, MSSAU, BBName, Before); + DomTreeUpdater *DTU = nullptr, + LoopInfo *LI = nullptr, + MemorySSAUpdater *MSSAU = nullptr, + const Twine &BBName = "") { + return SplitBlock(Old, SplitPt->getIterator(), DTU, LI, MSSAU, BBName); } /// Split the specified block at the specified instruction \p SplitPt. diff --git a/llvm/include/llvm/Transforms/Utils/CodeExtractor.h b/llvm/include/llvm/Transforms/Utils/CodeExtractor.h index 3e2c69b47bc48..e117a33d3435f 100644 --- a/llvm/include/llvm/Transforms/Utils/CodeExtractor.h +++ b/llvm/include/llvm/Transforms/Utils/CodeExtractor.h @@ -71,250 +71,240 @@ class CodeExtractorAnalysisCache { AllocaInst *Addr) const; }; - /// Utility class for extracting code into a new function. +/// Utility class for extracting code into a new function. +/// +/// This utility provides a simple interface for extracting some sequence of +/// code into its own function, replacing it with a call to that function. It +/// also provides various methods to query about the nature and result of such a +/// transformation. +/// +/// The rough algorithm used is: +/// 1) Find both the inputs and outputs for the extracted region. +/// 2) Pass the inputs as arguments, remapping them within the extracted +/// function to arguments. +/// 3) Add allocas for any scalar outputs, adding all of the outputs' allocas as +/// arguments, and inserting stores to the arguments for any scalars. +class LLVM_ABI CodeExtractor { + using ValueSet = SetVector; + + // Various bits of state computed on construction. + DominatorTree *const DT; + const bool AggregateArgs; + BlockFrequencyInfo *BFI; + BranchProbabilityInfo *BPI; + AssumptionCache *AC; + + // A block outside of the extraction set where any intermediate allocations + // will be placed inside. If this is null, allocations will be placed in the + // entry block of the function. + BasicBlock *AllocationBlock; + + // If true, varargs functions can be extracted. + bool AllowVarArgs; + + // Bits of intermediate state computed at various phases of extraction. + SetVector Blocks; + + /// Lists of blocks that are branched from the code region to be extracted, + /// also called the exit blocks. Each block is contained at most once. Its + /// order defines the return value of the extracted function. + /// + /// When there is just one (or no) exit block, the return value is irrelevant. /// - /// This utility provides a simple interface for extracting some sequence of - /// code into its own function, replacing it with a call to that function. It - /// also provides various methods to query about the nature and result of - /// such a transformation. + /// When there are exactly two exit blocks, the extracted function returns a + /// boolean. For ExtractedFuncRetVals[0], it returns 'true'. For + /// ExtractedFuncRetVals[1] it returns 'false'. + /// NOTE: Since a boolean is represented by i1, ExtractedFuncRetVals[0] + /// returns 1 and ExtractedFuncRetVals[1] returns 0, which opposite of + /// the regular pattern below. + /// + /// When there are 3 or more exit blocks, leaving the extracted function via + /// the first block it returns 0. When leaving via the second entry it returns + /// 1, etc. + SmallVector ExtractedFuncRetVals; + + // Suffix to use when creating extracted function (appended to the original + // function name + "."). If empty, the default is to use the entry block + // label, if non-empty, otherwise "extracted". + std::string Suffix; + + // If true, the outlined function has aggregate argument in zero address + // space. + bool ArgsInZeroAddressSpace; + +public: + /// Create a code extractor for a sequence of blocks. + /// + /// Given a sequence of basic blocks where the first block in the sequence + /// dominates the rest, prepare a code extractor object for pulling this + /// sequence out into its new function. When a DominatorTree is also given, + /// extra checking and transformations are enabled. If AllowVarArgs is true, + /// vararg functions can be extracted. This is safe, if all vararg handling + /// code is extracted, including vastart. If AllowAlloca is true, then + /// extraction of blocks containing alloca instructions would be possible, + /// however code extractor won't validate whether extraction is legal. Any new + /// allocations will be placed in the AllocationBlock, unless it is null, in + /// which case it will be placed in the entry block of the function from which + /// the code is being extracted. If ArgsInZeroAddressSpace param is set to + /// true, then the aggregate param pointer of the outlined function is + /// declared in zero address space. + CodeExtractor(ArrayRef BBs, DominatorTree *DT = nullptr, + bool AggregateArgs = false, BlockFrequencyInfo *BFI = nullptr, + BranchProbabilityInfo *BPI = nullptr, + AssumptionCache *AC = nullptr, bool AllowVarArgs = false, + bool AllowAlloca = false, BasicBlock *AllocationBlock = nullptr, + std::string Suffix = "", bool ArgsInZeroAddressSpace = false); + + /// Perform the extraction, returning the new function. + /// + /// Returns zero when called on a CodeExtractor instance where isEligible + /// returns false. + Function *extractCodeRegion(const CodeExtractorAnalysisCache &CEAC); + + /// Perform the extraction, returning the new function and providing an + /// interface to see what was categorized as inputs and outputs. /// - /// The rough algorithm used is: - /// 1) Find both the inputs and outputs for the extracted region. - /// 2) Pass the inputs as arguments, remapping them within the extracted - /// function to arguments. - /// 3) Add allocas for any scalar outputs, adding all of the outputs' allocas - /// as arguments, and inserting stores to the arguments for any scalars. - class CodeExtractor { - using ValueSet = SetVector; - - // Various bits of state computed on construction. - DominatorTree *const DT; - const bool AggregateArgs; - BlockFrequencyInfo *BFI; - BranchProbabilityInfo *BPI; - AssumptionCache *AC; - - // A block outside of the extraction set where any intermediate - // allocations will be placed inside. If this is null, allocations - // will be placed in the entry block of the function. - BasicBlock *AllocationBlock; - - // If true, varargs functions can be extracted. - bool AllowVarArgs; - - // Bits of intermediate state computed at various phases of extraction. - SetVector Blocks; - - /// Lists of blocks that are branched from the code region to be extracted, - /// also called the exit blocks. Each block is contained at most once. Its - /// order defines the return value of the extracted function. - /// - /// When there is just one (or no) exit block, the return value is - /// irrelevant. - /// - /// When there are exactly two exit blocks, the extracted function returns a - /// boolean. For ExtractedFuncRetVals[0], it returns 'true'. For - /// ExtractedFuncRetVals[1] it returns 'false'. - /// NOTE: Since a boolean is represented by i1, ExtractedFuncRetVals[0] - /// returns 1 and ExtractedFuncRetVals[1] returns 0, which opposite - /// of the regular pattern below. - /// - /// When there are 3 or more exit blocks, leaving the extracted function via - /// the first block it returns 0. When leaving via the second entry it - /// returns 1, etc. - SmallVector ExtractedFuncRetVals; - - // Suffix to use when creating extracted function (appended to the original - // function name + "."). If empty, the default is to use the entry block - // label, if non-empty, otherwise "extracted". - std::string Suffix; - - // If true, the outlined function has aggregate argument in zero address - // space. - bool ArgsInZeroAddressSpace; - - public: - /// Create a code extractor for a sequence of blocks. - /// - /// Given a sequence of basic blocks where the first block in the sequence - /// dominates the rest, prepare a code extractor object for pulling this - /// sequence out into its new function. When a DominatorTree is also given, - /// extra checking and transformations are enabled. If AllowVarArgs is true, - /// vararg functions can be extracted. This is safe, if all vararg handling - /// code is extracted, including vastart. If AllowAlloca is true, then - /// extraction of blocks containing alloca instructions would be possible, - /// however code extractor won't validate whether extraction is legal. - /// Any new allocations will be placed in the AllocationBlock, unless - /// it is null, in which case it will be placed in the entry block of - /// the function from which the code is being extracted. - /// If ArgsInZeroAddressSpace param is set to true, then the aggregate - /// param pointer of the outlined function is declared in zero address - /// space. - LLVM_ABI - CodeExtractor(ArrayRef BBs, DominatorTree *DT = nullptr, - bool AggregateArgs = false, BlockFrequencyInfo *BFI = nullptr, - BranchProbabilityInfo *BPI = nullptr, - AssumptionCache *AC = nullptr, bool AllowVarArgs = false, - bool AllowAlloca = false, - BasicBlock *AllocationBlock = nullptr, - std::string Suffix = "", bool ArgsInZeroAddressSpace = false); - - /// Perform the extraction, returning the new function. - /// - /// Returns zero when called on a CodeExtractor instance where isEligible - /// returns false. - LLVM_ABI Function * - extractCodeRegion(const CodeExtractorAnalysisCache &CEAC); - - /// Perform the extraction, returning the new function and providing an - /// interface to see what was categorized as inputs and outputs. - /// - /// \param CEAC - Cache to speed up operations for the CodeExtractor when - /// hoisting, and extracting lifetime values and assumes. - /// \param Inputs [in/out] - filled with values marked as inputs to the - /// newly outlined function. - /// \param Outputs [out] - filled with values marked as outputs to the - /// newly outlined function. - /// \returns zero when called on a CodeExtractor instance where isEligible - /// returns false. - LLVM_ABI Function *extractCodeRegion(const CodeExtractorAnalysisCache &CEAC, - ValueSet &Inputs, ValueSet &Outputs); - - /// Verify that assumption cache isn't stale after a region is extracted. - /// Returns true when verifier finds errors. AssumptionCache is passed as - /// parameter to make this function stateless. - LLVM_ABI static bool verifyAssumptionCache(const Function &OldFunc, - const Function &NewFunc, - AssumptionCache *AC); - - /// Test whether this code extractor is eligible. - /// - /// Based on the blocks used when constructing the code extractor, - /// determine whether it is eligible for extraction. - /// - /// Checks that varargs handling (with vastart and vaend) is only done in - /// the outlined blocks. - LLVM_ABI bool isEligible() const; - - /// Compute the set of input values and output values for the code. - /// - /// These can be used either when performing the extraction or to evaluate - /// the expected size of a call to the extracted function. Note that this - /// work cannot be cached between the two as once we decide to extract - /// a code sequence, that sequence is modified, including changing these - /// sets, before extraction occurs. These modifications won't have any - /// significant impact on the cost however. - LLVM_ABI void findInputsOutputs(ValueSet &Inputs, ValueSet &Outputs, - const ValueSet &Allocas, - bool CollectGlobalInputs = false) const; - - /// Check if life time marker nodes can be hoisted/sunk into the outline - /// region. - /// - /// Returns true if it is safe to do the code motion. - LLVM_ABI bool - isLegalToShrinkwrapLifetimeMarkers(const CodeExtractorAnalysisCache &CEAC, - Instruction *AllocaAddr) const; - - /// Find the set of allocas whose life ranges are contained within the - /// outlined region. - /// - /// Allocas which have life_time markers contained in the outlined region - /// should be pushed to the outlined function. The address bitcasts that - /// are used by the lifetime markers are also candidates for shrink- - /// wrapping. The instructions that need to be sunk are collected in - /// 'Allocas'. - LLVM_ABI void findAllocas(const CodeExtractorAnalysisCache &CEAC, - ValueSet &SinkCands, ValueSet &HoistCands, - BasicBlock *&ExitBlock) const; - - /// Find or create a block within the outline region for placing hoisted - /// code. - /// - /// CommonExitBlock is block outside the outline region. It is the common - /// successor of blocks inside the region. If there exists a single block - /// inside the region that is the predecessor of CommonExitBlock, that block - /// will be returned. Otherwise CommonExitBlock will be split and the - /// original block will be added to the outline region. - LLVM_ABI BasicBlock * - findOrCreateBlockForHoisting(BasicBlock *CommonExitBlock); - - /// Exclude a value from aggregate argument passing when extracting a code - /// region, passing it instead as a scalar. - LLVM_ABI void excludeArgFromAggregate(Value *Arg); - - private: - struct LifetimeMarkerInfo { - bool SinkLifeStart = false; - bool HoistLifeEnd = false; - Instruction *LifeStart = nullptr; - Instruction *LifeEnd = nullptr; - }; - - ValueSet ExcludeArgsFromAggregate; - - LifetimeMarkerInfo - getLifetimeMarkers(const CodeExtractorAnalysisCache &CEAC, - Instruction *Addr, BasicBlock *ExitBlock) const; - - /// Updates the list of SwitchCases (corresponding to exit blocks) after - /// changes of the control flow or the Blocks list. - void computeExtractedFuncRetVals(); - - /// Return the type used for the return code of the extracted function to - /// indicate which exit block to jump to. - Type *getSwitchType(); - - void severSplitPHINodesOfEntry(BasicBlock *&Header); - void severSplitPHINodesOfExits(); - void splitReturnBlocks(); - - void moveCodeToFunction(Function *newFunction); - - void calculateNewCallTerminatorWeights( - BasicBlock *CodeReplacer, - const DenseMap &ExitWeights, - BranchProbabilityInfo *BPI); - - /// Normalizes the control flow of the extracted regions, such as ensuring - /// that the extracted region does not contain a return instruction. - void normalizeCFGForExtraction(BasicBlock *&header); - - /// Generates the function declaration for the function containing the - /// extracted code. - Function *constructFunctionDeclaration(const ValueSet &inputs, - const ValueSet &outputs, - BlockFrequency EntryFreq, - const Twine &Name, - ValueSet &StructValues, - StructType *&StructTy); - - /// Generates the code for the extracted function. That is: a prolog, the - /// moved or copied code from the original function, and epilogs for each - /// exit. - void emitFunctionBody(const ValueSet &inputs, const ValueSet &outputs, - const ValueSet &StructValues, Function *newFunction, - StructType *StructArgTy, BasicBlock *header, - const ValueSet &SinkingCands, - SmallVectorImpl &NewValues); - - /// Generates a Basic Block that calls the extracted function. - CallInst *emitReplacerCall(const ValueSet &inputs, const ValueSet &outputs, - const ValueSet &StructValues, - Function *newFunction, StructType *StructArgTy, - Function *oldFunction, BasicBlock *ReplIP, - BlockFrequency EntryFreq, - ArrayRef LifetimesStart, - std::vector &Reloads); - - /// Connects the basic block containing the call to the extracted function - /// into the original function's control flow. - void insertReplacerCall( - Function *oldFunction, BasicBlock *header, BasicBlock *codeReplacer, - const ValueSet &outputs, ArrayRef Reloads, - const DenseMap &ExitWeights); + /// \param CEAC - Cache to speed up operations for the CodeExtractor when + /// hoisting, and extracting lifetime values and assumes. + /// \param Inputs [in/out] - filled with values marked as inputs to the newly + /// outlined function. + /// \param Outputs [out] - filled with values marked as outputs to the newly + /// outlined function. + /// \returns zero when called on a CodeExtractor instance where isEligible + /// returns false. + Function *extractCodeRegion(const CodeExtractorAnalysisCache &CEAC, + ValueSet &Inputs, ValueSet &Outputs); + + /// Verify that assumption cache isn't stale after a region is extracted. + /// Returns true when verifier finds errors. AssumptionCache is passed as + /// parameter to make this function stateless. + static bool verifyAssumptionCache(const Function &OldFunc, + const Function &NewFunc, + AssumptionCache *AC); + + /// Test whether this code extractor is eligible. + /// + /// Based on the blocks used when constructing the code extractor, determine + /// whether it is eligible for extraction. + /// + /// Checks that varargs handling (with vastart and vaend) is only done in the + /// outlined blocks. + bool isEligible() const; + + /// Compute the set of input values and output values for the code. + /// + /// These can be used either when performing the extraction or to evaluate the + /// expected size of a call to the extracted function. Note that this work + /// cannot be cached between the two as once we decide to extract a code + /// sequence, that sequence is modified, including changing these sets, before + /// extraction occurs. These modifications won't have any significant impact + /// on the cost however. + void findInputsOutputs(ValueSet &Inputs, ValueSet &Outputs, + const ValueSet &Allocas, + bool CollectGlobalInputs = false) const; + + /// Check if life time marker nodes can be hoisted/sunk into the outline + /// region. + /// + /// Returns true if it is safe to do the code motion. + bool + isLegalToShrinkwrapLifetimeMarkers(const CodeExtractorAnalysisCache &CEAC, + Instruction *AllocaAddr) const; + + /// Find the set of allocas whose life ranges are contained within the + /// outlined region. + /// + /// Allocas which have life_time markers contained in the outlined region + /// should be pushed to the outlined function. The address bitcasts that are + /// used by the lifetime markers are also candidates for shrink-wrapping. The + /// instructions that need to be sunk are collected in 'Allocas'. + void findAllocas(const CodeExtractorAnalysisCache &CEAC, ValueSet &SinkCands, + ValueSet &HoistCands, BasicBlock *&ExitBlock) const; + + /// Find or create a block within the outline region for placing hoisted code. + /// + /// CommonExitBlock is block outside the outline region. It is the common + /// successor of blocks inside the region. If there exists a single block + /// inside the region that is the predecessor of CommonExitBlock, that block + /// will be returned. Otherwise CommonExitBlock will be split and the original + /// block will be added to the outline region. + BasicBlock *findOrCreateBlockForHoisting(BasicBlock *CommonExitBlock); + + /// Exclude a value from aggregate argument passing when extracting a code + /// region, passing it instead as a scalar. + void excludeArgFromAggregate(Value *Arg); + +private: + struct LifetimeMarkerInfo { + bool SinkLifeStart = false; + bool HoistLifeEnd = false; + Instruction *LifeStart = nullptr; + Instruction *LifeEnd = nullptr; }; + ValueSet ExcludeArgsFromAggregate; + + LifetimeMarkerInfo getLifetimeMarkers(const CodeExtractorAnalysisCache &CEAC, + Instruction *Addr, + BasicBlock *ExitBlock) const; + + /// Updates the list of SwitchCases (corresponding to exit blocks) after + /// changes of the control flow or the Blocks list. + void computeExtractedFuncRetVals(); + + /// Return the type used for the return code of the extracted function to + /// indicate which exit block to jump to. + Type *getSwitchType(); + + void severSplitPHINodesOfEntry(BasicBlock *&Header); + void severSplitPHINodesOfExits(); + void splitReturnBlocks(); + + void moveCodeToFunction(Function *newFunction); + + void calculateNewCallTerminatorWeights( + BasicBlock *CodeReplacer, + const DenseMap &ExitWeights, + BranchProbabilityInfo *BPI); + + /// Normalizes the control flow of the extracted regions, such as ensuring + /// that the extracted region does not contain a return instruction. + void normalizeCFGForExtraction(BasicBlock *&header); + + /// Generates the function declaration for the function containing the + /// extracted code. + Function * + constructFunctionDeclaration(const ValueSet &inputs, const ValueSet &outputs, + BlockFrequency EntryFreq, const Twine &Name, + ValueSet &StructValues, StructType *&StructTy); + + /// Generates the code for the extracted function. That is: a prolog, the + /// moved or copied code from the original function, and epilogs for each + /// exit. + void emitFunctionBody(const ValueSet &inputs, const ValueSet &outputs, + const ValueSet &StructValues, Function *newFunction, + StructType *StructArgTy, BasicBlock *header, + const ValueSet &SinkingCands, + SmallVectorImpl &NewValues); + + /// Generates a Basic Block that calls the extracted function. + CallInst *emitReplacerCall(const ValueSet &inputs, const ValueSet &outputs, + const ValueSet &StructValues, + Function *newFunction, StructType *StructArgTy, + Function *oldFunction, BasicBlock *ReplIP, + BlockFrequency EntryFreq, + ArrayRef LifetimesStart, + std::vector &Reloads); + + /// Connects the basic block containing the call to the extracted function + /// into the original function's control flow. + void + insertReplacerCall(Function *oldFunction, BasicBlock *header, + BasicBlock *codeReplacer, const ValueSet &outputs, + ArrayRef Reloads, + const DenseMap &ExitWeights); +}; + } // end namespace llvm #endif // LLVM_TRANSFORMS_UTILS_CODEEXTRACTOR_H diff --git a/llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h b/llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h index 1ec150330484d..1feb614f043bf 100644 --- a/llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h +++ b/llvm/include/llvm/Transforms/Utils/LowerMemIntrinsics.h @@ -61,7 +61,15 @@ LLVM_ABI bool expandMemMoveAsLoop(MemMoveInst *MemMove, const TargetTransformInfo &TTI); /// Expand \p MemSet as a loop. \p MemSet is not deleted. -LLVM_ABI void expandMemSetAsLoop(MemSetInst *MemSet); +/// If \p TTI is provided, the memset is expanded according to the target's +/// preferences. Otherwise, it is expanded as a byte-wise loop. +LLVM_ABI void expandMemSetAsLoop(MemSetInst *MemSet, + const TargetTransformInfo *TTI = nullptr); + +/// Expand \p MemSet as a loop according to the target's preferences. \p MemSet +/// is not deleted. +LLVM_ABI void expandMemSetAsLoop(MemSetInst *MemSet, + const TargetTransformInfo &TTI); /// Expand \p MemSetPattern as a loop. \p MemSet is not deleted. LLVM_ABI void expandMemSetPatternAsLoop(MemSetPatternInst *MemSet); diff --git a/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h b/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h index 64d2512308935..9ba3455254f47 100644 --- a/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h +++ b/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h @@ -204,7 +204,7 @@ class LibCallSimplifier { Value *replacePowWithExp(CallInst *Pow, IRBuilderBase &B); Value *replacePowWithSqrt(CallInst *Pow, IRBuilderBase &B); Value *optimizeExp2(CallInst *CI, IRBuilderBase &B); - Value *optimizeFMinFMax(CallInst *CI, IRBuilderBase &B); + Value *optimizeFMinFMax(CallInst *CI, IRBuilderBase &B, Intrinsic::ID IID); Value *optimizeFMinimumnumFMaximumnum(CallInst *CI, IRBuilderBase &B); Value *optimizeLog(CallInst *CI, IRBuilderBase &B); Value *optimizeSqrt(CallInst *CI, IRBuilderBase &B); diff --git a/llvm/include/llvm/Transforms/Utils/VNCoercion.h b/llvm/include/llvm/Transforms/Utils/VNCoercion.h index ed4dbad50ee85..2c93f659d0f2c 100644 --- a/llvm/include/llvm/Transforms/Utils/VNCoercion.h +++ b/llvm/include/llvm/Transforms/Utils/VNCoercion.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// /// \file / This file provides routines used by LLVM's value numbering passes to /// perform various forms of value extraction from memory when the types are not /// identical. For example, given @@ -17,6 +18,8 @@ /// These routines know how to tell whether they can do that (the analyze* /// routines), and can also insert the necessary IR to do it (the get* /// routines). +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_TRANSFORMS_UTILS_VNCOERCION_H #define LLVM_TRANSFORMS_UTILS_VNCOERCION_H @@ -32,6 +35,7 @@ class IRBuilderBase; class Value; class Type; class DataLayout; + namespace VNCoercion { /// Return true if CoerceAvailableValueToLoadType would succeed if it was /// called. @@ -93,6 +97,7 @@ Value *getMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset, // It returns nullptr if it cannot produce a constant. Constant *getConstantMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset, Type *LoadTy, const DataLayout &DL); -} -} -#endif +} // namespace VNCoercion +} // namespace llvm + +#endif // LLVM_TRANSFORMS_UTILS_VNCOERCION_H diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp index c0754d3a41264..ab060b1b9320a 100644 --- a/llvm/lib/Analysis/ConstantFolding.cpp +++ b/llvm/lib/Analysis/ConstantFolding.cpp @@ -4748,6 +4748,17 @@ Constant *llvm::getLosslessInvCast(Constant *C, Type *InvCastTo, } return InvC; } + case Instruction::FPExt: { + Constant *InvC = + ConstantFoldCastOperand(Instruction::FPTrunc, C, InvCastTo, DL); + if (InvC) { + Constant *CastInvC = + ConstantFoldCastOperand(CastOp, InvC, C->getType(), DL); + if (CastInvC == C) + return InvC; + } + return nullptr; + } default: return nullptr; } diff --git a/llvm/lib/Analysis/IVDescriptors.cpp b/llvm/lib/Analysis/IVDescriptors.cpp index 3946a7ce8b8f6..2a213d6be1470 100644 --- a/llvm/lib/Analysis/IVDescriptors.cpp +++ b/llvm/lib/Analysis/IVDescriptors.cpp @@ -54,10 +54,7 @@ bool RecurrenceDescriptor::isIntegerRecurrenceKind(RecurKind Kind) { case RecurKind::UMax: case RecurKind::UMin: case RecurKind::AnyOf: - case RecurKind::FindFirstIVSMin: - case RecurKind::FindFirstIVUMin: - case RecurKind::FindLastIVSMax: - case RecurKind::FindLastIVUMax: + case RecurKind::FindIV: // TODO: Make type-agnostic. case RecurKind::FindLast: return true; @@ -656,11 +653,10 @@ bool RecurrenceDescriptor::AddReductionVar( // is saved as part of the RecurrenceDescriptor. // Save the description of this reduction variable. - RecurrenceDescriptor RD(RdxStart, ExitInstruction, IntermediateStore, Kind, - FMF, ExactFPMathInst, RecurrenceType, IsSigned, - IsOrdered, CastInsts, MinWidthCastToRecurrenceType); - RedDes = RD; - + RedDes = + RecurrenceDescriptor(RdxStart, ExitInstruction, IntermediateStore, Kind, + FMF, ExactFPMathInst, RecurrenceType, IsSigned, + IsOrdered, CastInsts, MinWidthCastToRecurrenceType); return true; } @@ -740,19 +736,6 @@ RecurrenceDescriptor::isAnyOfPattern(Loop *Loop, PHINode *OrigPhi, // %spec.select = select i1 %cmp, i32 %i, i32 %r // %inc = add nsw i32 %i, 1 // ... -// When searching for an induction variable (i), the reduction value after the -// loop will be the maximum (increasing induction) or minimum (decreasing -// induction) value of 'i' that the condition (src[i] > 3) is satisfied, or the -// start value (0 in the example above). When the start value of the induction -// variable 'i' is greater than the minimum (increasing induction) or maximum -// (decreasing induction) value of the data type, we can use the minimum -// (increasing induction) or maximum (decreasing induction) value of the data -// type as a sentinel value to replace the start value. This allows us to -// perform a single reduction max (increasing induction) or min (decreasing -// induction) operation to obtain the final reduction result. -// TODO: It is possible to solve the case where the start value is the minimum -// value of the data type or a non-constant value by using mask and multiple -// reduction operations. // // When searching for an arbitrary loop-varying value, the reduction value will // either be the initial value (0) if the condition was never met, or the value @@ -771,8 +754,6 @@ RecurrenceDescriptor::isFindPattern(Loop *TheLoop, PHINode *OrigPhi, // We are looking for selects of the form: // select(cmp(), phi, value) or // select(cmp(), value, phi) - // where 'value' must be a loop induction variable - // (for FindFirstIV/FindLastIV) or an arbitrary value (for FindLast). // TODO: Match selects with multi-use cmp conditions. Value *NonRdxPhi = nullptr; if (!match(I, m_CombineOr(m_Select(m_OneUse(m_Cmp()), m_Value(NonRdxPhi), @@ -781,74 +762,6 @@ RecurrenceDescriptor::isFindPattern(Loop *TheLoop, PHINode *OrigPhi, m_Value(NonRdxPhi))))) return InstDesc(false, I); - // Returns either FindFirstIV/FindLastIV, if such a pattern is found, or - // std::nullopt. - auto GetFindFirstLastIVRecurKind = [&](Value *V) -> std::optional { - Type *Ty = V->getType(); - if (!SE.isSCEVable(Ty)) - return std::nullopt; - - auto *AR = SE.getSCEV(V); - const SCEV *Step; - if (!match(AR, m_scev_AffineAddRec(m_SCEV(), m_SCEV(Step), - m_SpecificLoop(TheLoop)))) - return std::nullopt; - - // We must have a known positive or negative step for FindIV - const bool PositiveStep = SE.isKnownPositive(Step); - if (!SE.isKnownNonZero(Step)) - return std::nullopt; - - // Check if the minimum (FindLast) or maximum (FindFirst) value of the - // recurrence type can be used as a sentinel value. The maximum acceptable - // range for the induction variable, called the valid range will exclude - // , where is - // [Signed|Unsigned]Min() for FindLastIV or - // [Signed|Unsigned]Max() for FindFirstIV. - // TODO: This range restriction can be lifted by adding an additional - // virtual OR reduction. - auto CheckRange = [&](bool IsSigned) { - const ConstantRange IVRange = - IsSigned ? SE.getSignedRange(AR) : SE.getUnsignedRange(AR); - unsigned NumBits = Ty->getIntegerBitWidth(); - APInt Sentinel; - if (PositiveStep) { - Sentinel = IsSigned ? APInt::getSignedMinValue(NumBits) - : APInt::getMinValue(NumBits); - } else { - Sentinel = IsSigned ? APInt::getSignedMaxValue(NumBits) - : APInt::getMaxValue(NumBits); - } - ConstantRange ValidRange = ConstantRange(Sentinel).inverse(); - - LLVM_DEBUG( - dbgs() << "LV: " << (PositiveStep ? "FindLastIV" : "FindFirstIV") - << " valid range is " << ValidRange << ", and the range of " - << *AR << " is " << IVRange << "\n"); - - // Ensure the induction variable does not wrap around by verifying that - // its range is fully contained within the valid range. - return ValidRange.contains(IVRange); - }; - if (PositiveStep) { - if (CheckRange(true)) - return RecurKind::FindLastIVSMax; - if (CheckRange(false)) - return RecurKind::FindLastIVUMax; - return std::nullopt; - } - - if (CheckRange(true)) - return RecurKind::FindFirstIVSMin; - if (CheckRange(false)) - return RecurKind::FindFirstIVUMin; - return std::nullopt; - }; - - if (auto RK = GetFindFirstLastIVRecurKind(NonRdxPhi)) - return InstDesc(I, *RK); - - // If the recurrence is not specific to an IV, return a generic FindLast. return InstDesc(I, RecurKind::FindLast); } @@ -1302,10 +1215,7 @@ unsigned RecurrenceDescriptor::getOpcode(RecurKind Kind) { return Instruction::FCmp; case RecurKind::FindLast: case RecurKind::AnyOf: - case RecurKind::FindFirstIVSMin: - case RecurKind::FindFirstIVUMin: - case RecurKind::FindLastIVSMax: - case RecurKind::FindLastIVUMax: + case RecurKind::FindIV: // TODO: Set AnyOf and FindIV to Instruction::Select once in-loop reductions // are supported. default: diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp index 0e49b1903d410..e0054e3ed6ee2 100644 --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -1602,19 +1602,20 @@ bool CallAnalyzer::visitAlloca(AllocaInst &I) { } } - // Accumulate the allocated size. if (I.isStaticAlloca()) { - Type *Ty = I.getAllocatedType(); - AllocatedSize = SaturatingAdd(DL.getTypeAllocSize(Ty).getKnownMinValue(), - AllocatedSize); - } - - // FIXME: This is overly conservative. Dynamic allocas are inefficient for - // a variety of reasons, and so we would like to not inline them into - // functions which don't currently have a dynamic alloca. This simply - // disables inlining altogether in the presence of a dynamic alloca. - if (!I.isStaticAlloca()) + // Accumulate the allocated size if constant and executed once. + // Note: if AllocSize is a vscale value, this is an underestimate of the + // allocated size, and it also requires some of the cost of a dynamic + // alloca, but is recorded here as a constant size alloca. + TypeSize AllocSize = I.getAllocationSize(DL).value_or(TypeSize::getZero()); + AllocatedSize = SaturatingAdd(AllocSize.getKnownMinValue(), AllocatedSize); + } else { + // FIXME: This is overly conservative. Dynamic allocas are inefficient for + // a variety of reasons, and so we would like to not inline them into + // functions which don't currently have a dynamic alloca. This simply + // disables inlining altogether in the presence of a dynamic alloca. HasDynamicAlloca = true; + } return false; } @@ -1728,7 +1729,7 @@ bool CallAnalyzer::canFoldInboundsGEP(GetElementPtrInst &I) { return false; // Add the result as a new mapping to Base + Offset. - ConstantOffsetPtrs[&I] = BaseAndOffset; + ConstantOffsetPtrs[&I] = std::move(BaseAndOffset); return true; } diff --git a/llvm/lib/Analysis/LoopUnrollAnalyzer.cpp b/llvm/lib/Analysis/LoopUnrollAnalyzer.cpp index 9c78e2afaede7..7c8e300c016ba 100644 --- a/llvm/lib/Analysis/LoopUnrollAnalyzer.cpp +++ b/llvm/lib/Analysis/LoopUnrollAnalyzer.cpp @@ -66,7 +66,7 @@ bool UnrolledInstAnalyzer::simplifyInstWithSCEV(Instruction *I) { SimplifiedAddress Address; Address.Base = Base->getValue(); Address.Offset = *Offset; - SimplifiedAddresses[I] = Address; + SimplifiedAddresses[I] = std::move(Address); return false; } diff --git a/llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp b/llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp index 9d53c37461ba8..06ead92201d77 100644 --- a/llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp +++ b/llvm/lib/Analysis/ModuleDebugInfoPrinter.cpp @@ -103,6 +103,31 @@ static void printModuleDebugInfo(raw_ostream &O, const Module *M, } O << '\n'; } + + for (const auto &MacroEntry : Finder.macros()) { + const DIMacro *Macro = MacroEntry.first; + const DIMacroFile *MacroFile = MacroEntry.second; + + O << "Macro: "; + auto MacroType = dwarf::MacinfoString(Macro->getMacinfoType()); + if (!MacroType.empty()) + O << MacroType; + else + O << "unknown-macinfo(" << Macro->getMacinfoType() << ")"; + + O << " '" << Macro->getName() << "'"; + if (!Macro->getValue().empty()) + O << " = '" << Macro->getValue() << "'"; + + if (MacroFile && MacroFile->getFile()) { + const DIFile *File = MacroFile->getFile(); + printFile(O, File->getFilename(), File->getDirectory(), + MacroFile->getLine()); + } else { + O << " at line " << Macro->getLine(); + } + O << '\n'; + } } ModuleDebugInfoPrinterPass::ModuleDebugInfoPrinterPass(raw_ostream &OS) diff --git a/llvm/lib/Analysis/StaticDataProfileInfo.cpp b/llvm/lib/Analysis/StaticDataProfileInfo.cpp index 61d49350c7702..e7a01317ea3dc 100644 --- a/llvm/lib/Analysis/StaticDataProfileInfo.cpp +++ b/llvm/lib/Analysis/StaticDataProfileInfo.cpp @@ -12,6 +12,14 @@ using namespace llvm; namespace llvm { +// FIXME: This option is added for incremental rollout purposes. +// After the option, string literal partitioning should be implied by +// AnnotateStaticDataSectionPrefix in MemProfUse.cpp and this option should be +// cleaned up. +cl::opt AnnotateStringLiteralSectionPrefix( + "memprof-annotate-string-literal-section-prefix", cl::init(false), + cl::Hidden, + cl::desc("If true, annotate the string literal data section prefix")); namespace memprof { // Returns true iff the global variable has custom section either by // __attribute__((section("name"))) @@ -124,11 +132,23 @@ StringRef StaticDataProfileInfo::getConstantSectionPrefix( #endif if (EnableDataAccessProf) { - // Module flag `HasDataAccessProf` is 1 -> empty section prefix means - // unknown hotness except for string literals. + // Both data access profiles and PGO counters are available. Use the + // hotter one to be conservative. Basically, we want the non-unlikely + // sections to have max coverage of accessed symbols and meanwhile can + // tolerant some cold symbols in it, and the unlikely section variant to not + // have potentially hot symbols if possible, to avoid the penalty of access + // cold pages. if (const GlobalVariable *GV = dyn_cast(C); GV && llvm::memprof::IsAnnotationOK(*GV) && - !GV->getName().starts_with(".str")) { + (AnnotateStringLiteralSectionPrefix || + !GV->getName().starts_with(".str"))) { + // Note a global var is covered by data access profiles iff the + // symbol name is preserved in the symbol table; most notably, a string + // literal with private linkage (e.g., those not externalized by ThinLTO + // and with insignificant address) won't have an entry in the symbol + // table (unless there is another string with identical content that + // gets a symbol table entry). For the private-linkage string literals, + // their hotness will be at least lukewarm (i.e., empty prefix). auto HotnessFromDataAccessProf = getSectionHotnessUsingDataAccessProfile(GV->getSectionPrefix()); @@ -140,8 +160,6 @@ StringRef StaticDataProfileInfo::getConstantSectionPrefix( return Prefix; } - // Both data access profiles and PGO counters are available. Use the - // hotter one. auto HotnessFromPGO = getConstantHotnessUsingProfileCount(C, PSI, *Count); StaticDataHotness GlobalVarHotness = StaticDataHotness::LukewarmOrUnknown; if (HotnessFromDataAccessProf == StaticDataHotness::Hot || diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index b0d640e33cc28..8761b7bcb51a2 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -5361,88 +5361,36 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, computeKnownBits(Exp, isa(ExpTy) ? DemandedElts : APInt(1, 1), ExponentKnownBits, Q, Depth + 1); - if (ExponentKnownBits.Zero[0]) { // Is even - Known.knownNot(fcNegative); - break; + KnownFPClass KnownSrc; + if (!ExponentKnownBits.isEven()) { + computeKnownFPClass(II->getArgOperand(0), DemandedElts, fcNegative, + KnownSrc, Q, Depth + 1); } - // Given that exp is an integer, here are the - // ways that pow can return a negative value: - // - // pow(-x, exp) --> negative if exp is odd and x is negative. - // pow(-0, exp) --> -inf if exp is negative odd. - // pow(-0, exp) --> -0 if exp is positive odd. - // pow(-inf, exp) --> -0 if exp is negative odd. - // pow(-inf, exp) --> -inf if exp is positive odd. - KnownFPClass KnownSrc; - computeKnownFPClass(II->getArgOperand(0), DemandedElts, fcNegative, - KnownSrc, Q, Depth + 1); - if (KnownSrc.isKnownNever(fcNegative)) - Known.knownNot(fcNegative); + Known = KnownFPClass::powi(KnownSrc, ExponentKnownBits); break; } case Intrinsic::ldexp: { KnownFPClass KnownSrc; computeKnownFPClass(II->getArgOperand(0), DemandedElts, InterestedClasses, KnownSrc, Q, Depth + 1); - Known.propagateNaN(KnownSrc, /*PropagateSign=*/true); - - // Sign is preserved, but underflows may produce zeroes. - if (KnownSrc.isKnownNever(fcNegative)) - Known.knownNot(fcNegative); - else if (KnownSrc.cannotBeOrderedLessThanZero()) - Known.knownNot(KnownFPClass::OrderedLessThanZeroMask); - - if (KnownSrc.isKnownNever(fcPositive)) - Known.knownNot(fcPositive); - else if (KnownSrc.cannotBeOrderedGreaterThanZero()) - Known.knownNot(KnownFPClass::OrderedGreaterThanZeroMask); - // Can refine inf/zero handling based on the exponent operand. const FPClassTest ExpInfoMask = fcZero | fcSubnormal | fcInf; - if ((InterestedClasses & ExpInfoMask) == fcNone) - break; - if ((KnownSrc.KnownFPClasses & ExpInfoMask) == fcNone) - break; + + KnownBits ExpBits; + if ((KnownSrc.KnownFPClasses & ExpInfoMask) != fcNone) { + const Value *ExpArg = II->getArgOperand(1); + ExpBits = computeKnownBits(ExpArg, DemandedElts, Q, Depth + 1); + } const fltSemantics &Flt = II->getType()->getScalarType()->getFltSemantics(); - unsigned Precision = APFloat::semanticsPrecision(Flt); - const Value *ExpArg = II->getArgOperand(1); - ConstantRange ExpRange = computeConstantRange( - ExpArg, true, Q.IIQ.UseInstrInfo, Q.AC, Q.CxtI, Q.DT, Depth + 1); - - const int MantissaBits = Precision - 1; - if (ExpRange.getSignedMin().sge(static_cast(MantissaBits))) - Known.knownNot(fcSubnormal); const Function *F = II->getFunction(); - const APInt *ConstVal = ExpRange.getSingleElement(); - const fltSemantics &FltSem = - II->getType()->getScalarType()->getFltSemantics(); - if (ConstVal && ConstVal->isZero()) { - // ldexp(x, 0) -> x, so propagate everything. - Known.propagateCanonicalizingSrc(KnownSrc, F->getDenormalMode(FltSem)); - } else if (ExpRange.isAllNegative()) { - // If we know the power is <= 0, can't introduce inf - if (KnownSrc.isKnownNeverPosInfinity()) - Known.knownNot(fcPosInf); - if (KnownSrc.isKnownNeverNegInfinity()) - Known.knownNot(fcNegInf); - } else if (ExpRange.isAllNonNegative()) { - // If we know the power is >= 0, can't introduce subnormal or zero - if (KnownSrc.isKnownNeverPosSubnormal()) - Known.knownNot(fcPosSubnormal); - if (KnownSrc.isKnownNeverNegSubnormal()) - Known.knownNot(fcNegSubnormal); - if (F && - KnownSrc.isKnownNeverLogicalPosZero(F->getDenormalMode(FltSem))) - Known.knownNot(fcPosZero); - if (F && - KnownSrc.isKnownNeverLogicalNegZero(F->getDenormalMode(FltSem))) - Known.knownNot(fcNegZero); - } + DenormalMode Mode = + F ? F->getDenormalMode(Flt) : DenormalMode::getDynamic(); + Known = KnownFPClass::ldexp(KnownSrc, ExpBits, Flt, Mode); break; } case Intrinsic::arithmetic_fence: { @@ -5466,6 +5414,23 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, // TODO: Copy inf handling from instructions break; + + case Intrinsic::amdgcn_fract: { + Known.knownNot(fcInf); + + if (InterestedClasses & fcNan) { + KnownFPClass KnownSrc; + computeKnownFPClass(II->getArgOperand(0), DemandedElts, + InterestedClasses, KnownSrc, Q, Depth + 1); + + if (KnownSrc.isKnownNeverInfOrNaN()) + Known.knownNot(fcNan); + else if (KnownSrc.isKnownNever(fcSNan)) + Known.knownNot(fcSNan); + } + + break; + } case Intrinsic::amdgcn_rcp: { KnownFPClass KnownSrc; computeKnownFPClass(II->getArgOperand(0), DemandedElts, InterestedClasses, @@ -5534,6 +5499,10 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, break; } + case Intrinsic::amdgcn_trig_preop: { + Known.knownNot(fcNan | fcInf); + break; + } default: break; } diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp index d4083c49626fe..79723c9815445 100644 --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -65,12 +65,6 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) { case Intrinsic::smul_fix_sat: case Intrinsic::umul_fix: case Intrinsic::umul_fix_sat: - case Intrinsic::uadd_with_overflow: - case Intrinsic::sadd_with_overflow: - case Intrinsic::usub_with_overflow: - case Intrinsic::ssub_with_overflow: - case Intrinsic::umul_with_overflow: - case Intrinsic::smul_with_overflow: case Intrinsic::sqrt: // Begin floating-point. case Intrinsic::asin: case Intrinsic::acos: @@ -136,6 +130,15 @@ bool llvm::isTriviallyScalarizable(Intrinsic::ID ID, if (TTI && Intrinsic::isTargetIntrinsic(ID)) return TTI->isTargetIntrinsicTriviallyScalarizable(ID); + switch (ID) { + case Intrinsic::uadd_with_overflow: + case Intrinsic::sadd_with_overflow: + case Intrinsic::ssub_with_overflow: + case Intrinsic::usub_with_overflow: + case Intrinsic::umul_with_overflow: + case Intrinsic::smul_with_overflow: + return true; + } return false; } diff --git a/llvm/lib/AsmParser/AsmParserContext.cpp b/llvm/lib/AsmParser/AsmParserContext.cpp index 453e6994d2b9e..fdc9940bb44b3 100644 --- a/llvm/lib/AsmParser/AsmParserContext.cpp +++ b/llvm/lib/AsmParser/AsmParserContext.cpp @@ -25,8 +25,10 @@ AsmParserContext::getBlockLocation(const BasicBlock *BB) const { } std::optional -AsmParserContext::getInstructionLocation(const Instruction *I) const { - if (auto IIt = Instructions.find(I); IIt != Instructions.end()) +AsmParserContext::getInstructionOrArgumentLocation(const Value *IA) const { + assert(isa(IA) || isa(IA)); + if (auto IIt = InstructionsAndArguments.find(IA); + IIt != InstructionsAndArguments.end()) return IIt->second; return std::nullopt; } @@ -55,17 +57,30 @@ BasicBlock *AsmParserContext::getBlockAtLocation(const FileLoc &Query) const { return BlocksInverse.lookup(Query, nullptr); } -Instruction * -AsmParserContext::getInstructionAtLocation(const FileLocRange &Query) const { - auto It = InstructionsInverse.find(Query.Start); +Value *AsmParserContext::getInstructionOrArgumentAtLocation( + const FileLocRange &Query) const { + auto It = InstructionsAndArgumentsInverse.find(Query.Start); if (It.stop() <= Query.End) return *It; return nullptr; } -Instruction * -AsmParserContext::getInstructionAtLocation(const FileLoc &Query) const { - return InstructionsInverse.lookup(Query, nullptr); +Value *AsmParserContext::getInstructionOrArgumentAtLocation( + const FileLoc &Query) const { + return InstructionsAndArgumentsInverse.lookup(Query, nullptr); +} + +Value *AsmParserContext::getValueReferencedAtLocation( + const FileLocRange &Query) const { + auto It = ReferencedValues.find(Query.Start); + if (It.stop() <= Query.End) + return *It; + return nullptr; +} + +Value * +AsmParserContext::getValueReferencedAtLocation(const FileLoc &Query) const { + return ReferencedValues.lookup(Query, nullptr); } bool AsmParserContext::addFunctionLocation(Function *F, @@ -84,12 +99,19 @@ bool AsmParserContext::addBlockLocation(BasicBlock *BB, return Inserted; } -bool AsmParserContext::addInstructionLocation(Instruction *I, - const FileLocRange &Loc) { - bool Inserted = Instructions.insert({I, Loc}).second; +bool AsmParserContext::addInstructionOrArgumentLocation( + Value *IA, const FileLocRange &Loc) { + assert(isa(IA) || isa(IA)); + bool Inserted = InstructionsAndArguments.insert({IA, Loc}).second; if (Inserted) - InstructionsInverse.insert(Loc.Start, Loc.End, I); + InstructionsAndArgumentsInverse.insert(Loc.Start, Loc.End, IA); return Inserted; } +bool AsmParserContext::addValueReferenceAtLocation(Value *V, + const FileLocRange &Loc) { + ReferencedValues.insert(Loc.Start, Loc.End, V); + return true; +} + } // namespace llvm diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp index 4e7e31da09a52..f47579ca8fa9b 100644 --- a/llvm/lib/AsmParser/LLLexer.cpp +++ b/llvm/lib/AsmParser/LLLexer.cpp @@ -720,6 +720,12 @@ lltok::Kind LLLexer::LexIdentifier() { KEYWORD(provenance); KEYWORD(read_provenance); + // denormal_fpenv attribute + KEYWORD(ieee); + KEYWORD(preservesign); + KEYWORD(positivezero); + KEYWORD(dynamic); + // nofpclass attribute KEYWORD(all); KEYWORD(nan); diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index 068b52fcf0995..5b916711690ec 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -428,6 +428,9 @@ bool LLParser::validateEndOfModule(bool UpgradeDebugInfo) { N.second->resolveCycles(); } + DISubprogram::cleanupRetainedNodes(NewDistinctSPs); + NewDistinctSPs.clear(); + for (auto *Inst : InstsWithTBAATag) { MDNode *MD = Inst->getMetadata(LLVMContext::MD_tbaa); // With incomplete IR, the tbaa metadata may have been dropped. @@ -1655,6 +1658,14 @@ bool LLParser::parseEnumAttribute(Attribute::AttrKind Attr, AttrBuilder &B, B.addMemoryAttr(*ME); return false; } + case Attribute::DenormalFPEnv: { + std::optional Mode = parseDenormalFPEnvAttr(); + if (!Mode) + return true; + + B.addDenormalFPEnvAttr(*Mode); + return false; + } case Attribute::NoFPClass: { if (FPClassTest NoFPClass = static_cast(parseNoFPClassAttr())) { @@ -2600,6 +2611,22 @@ static std::optional keywordToModRef(lltok::Kind Tok) { } } +static std::optional +keywordToDenormalModeKind(lltok::Kind Tok) { + switch (Tok) { + case lltok::kw_ieee: + return DenormalMode::IEEE; + case lltok::kw_preservesign: + return DenormalMode::PreserveSign; + case lltok::kw_positivezero: + return DenormalMode::PositiveZero; + case lltok::kw_dynamic: + return DenormalMode::Dynamic; + default: + return std::nullopt; + } +} + std::optional LLParser::parseMemoryAttr() { MemoryEffects ME = MemoryEffects::none(); @@ -2655,6 +2682,87 @@ std::optional LLParser::parseMemoryAttr() { return std::nullopt; } +std::optional LLParser::parseDenormalFPEnvEntry() { + std::optional OutputMode = + keywordToDenormalModeKind(Lex.getKind()); + if (!OutputMode) { + tokError("expected denormal behavior kind (ieee, preservesign, " + "positivezero, dynamic)"); + return {}; + } + + Lex.Lex(); + + std::optional InputMode; + if (EatIfPresent(lltok::bar)) { + InputMode = keywordToDenormalModeKind(Lex.getKind()); + if (!InputMode) { + tokError("expected denormal behavior kind (ieee, preservesign, " + "positivezero, dynamic)"); + return {}; + } + + Lex.Lex(); + } else { + // Single item, input == output mode + InputMode = OutputMode; + } + + return DenormalMode(*OutputMode, *InputMode); +} + +std::optional LLParser::parseDenormalFPEnvAttr() { + // We use syntax like denormal_fpenv(float: preservesign), so the colon should + // not be interpreted as a label terminator. + Lex.setIgnoreColonInIdentifiers(true); + llvm::scope_exit _([&] { Lex.setIgnoreColonInIdentifiers(false); }); + + Lex.Lex(); + + if (parseToken(lltok::lparen, "expected '('")) + return {}; + + DenormalMode DefaultMode = DenormalMode::getIEEE(); + DenormalMode F32Mode = DenormalMode::getInvalid(); + + bool HasDefaultSection = false; + if (Lex.getKind() != lltok::Type) { + std::optional ParsedDefaultMode = parseDenormalFPEnvEntry(); + if (!ParsedDefaultMode) + return {}; + DefaultMode = *ParsedDefaultMode; + HasDefaultSection = true; + } + + bool HasComma = EatIfPresent(lltok::comma); + if (Lex.getKind() == lltok::Type) { + if (HasDefaultSection && !HasComma) { + tokError("expected ',' before float:"); + return {}; + } + + Type *Ty = nullptr; + if (parseType(Ty) || !Ty->isFloatTy()) { + tokError("expected float:"); + return {}; + } + + if (parseToken(lltok::colon, "expected ':' before float denormal_fpenv")) + return {}; + + std::optional ParsedF32Mode = parseDenormalFPEnvEntry(); + if (!ParsedF32Mode) + return {}; + + F32Mode = *ParsedF32Mode; + } + + if (parseToken(lltok::rparen, "unterminated denormal_fpenv")) + return {}; + + return DenormalFPEnv(DefaultMode, F32Mode); +} + static unsigned keywordToFPClassTest(lltok::Kind Tok) { switch (Tok) { case lltok::kw_all: @@ -3423,18 +3531,26 @@ bool LLParser::parseArgumentList(SmallVectorImpl &ArgList, return error(TypeLoc, "argument can not have void type"); std::string Name; + FileLoc IdentStart; + FileLoc IdentEnd; + bool Unnamed = false; if (Lex.getKind() == lltok::LocalVar) { Name = Lex.getStrVal(); + IdentStart = Lex.getTokLineColumnPos(); Lex.Lex(); + IdentEnd = Lex.getPrevTokEndLineColumnPos(); } else { unsigned ArgID; if (Lex.getKind() == lltok::LocalVarID) { ArgID = Lex.getUIntVal(); + IdentStart = Lex.getTokLineColumnPos(); if (checkValueID(TypeLoc, "argument", "%", CurValID, ArgID)) return true; Lex.Lex(); + IdentEnd = Lex.getPrevTokEndLineColumnPos(); } else { ArgID = CurValID; + Unnamed = true; } UnnamedArgNums.push_back(ArgID); CurValID = ArgID + 1; @@ -3443,9 +3559,11 @@ bool LLParser::parseArgumentList(SmallVectorImpl &ArgList, if (!FunctionType::isValidArgumentType(ArgTy)) return error(TypeLoc, "invalid type for function argument"); - ArgList.emplace_back(TypeLoc, ArgTy, - AttributeSet::get(ArgTy->getContext(), Attrs), - std::move(Name)); + ArgList.emplace_back( + TypeLoc, ArgTy, + Unnamed ? std::nullopt + : std::make_optional(FileLocRange(IdentStart, IdentEnd)), + AttributeSet::get(ArgTy->getContext(), Attrs), std::move(Name)); } while (EatIfPresent(lltok::comma)); } @@ -6032,6 +6150,10 @@ bool LLParser::parseDISubprogram(MDNode *&Result, bool IsDistinct) { thisAdjustment.Val, flags.Val, SPFlags, unit.Val, templateParams.Val, declaration.Val, retainedNodes.Val, thrownTypes.Val, annotations.Val, targetFuncName.Val, keyInstructions.Val)); + + if (IsDistinct) + NewDistinctSPs.push_back(cast(Result)); + return false; } @@ -6707,8 +6829,13 @@ bool LLParser::parseConstantValue(Type *Ty, Constant *&C) { bool LLParser::parseValue(Type *Ty, Value *&V, PerFunctionState *PFS) { V = nullptr; ValID ID; - return parseValID(ID, PFS, Ty) || - convertValIDToValue(Ty, ID, V, PFS); + + FileLoc Start = Lex.getTokLineColumnPos(); + bool Ret = parseValID(ID, PFS, Ty) || convertValIDToValue(Ty, ID, V, PFS); + FileLoc End = Lex.getPrevTokEndLineColumnPos(); + if (!Ret && ParserContext) + ParserContext->addValueReferenceAtLocation(V, FileLocRange(Start, End)); + return Ret; } bool LLParser::parseTypeAndValue(Value *&V, PerFunctionState *PFS) { @@ -6955,6 +7082,9 @@ bool LLParser::parseFunctionHeader(Function *&Fn, bool IsDefine, // Add all of the arguments we parsed to the function. Function::arg_iterator ArgIt = Fn->arg_begin(); for (unsigned i = 0, e = ArgList.size(); i != e; ++i, ++ArgIt) { + if (ParserContext && ArgList[i].IdentLoc) + ParserContext->addInstructionOrArgumentLocation( + &*ArgIt, ArgList[i].IdentLoc.value()); // If the argument has a name, insert it into the argument symbol table. if (ArgList[i].Name.empty()) continue; @@ -7164,7 +7294,7 @@ bool LLParser::parseBasicBlock(PerFunctionState &PFS) { BB->insertDbgRecordBefore(DR.release(), Inst->getIterator()); TrailingDbgRecord.clear(); if (ParserContext) { - ParserContext->addInstructionLocation( + ParserContext->addInstructionOrArgumentLocation( Inst, FileLocRange(InstStart, Lex.getPrevTokEndLineColumnPos())); } } while (!Inst->isTerminator()); diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 036f3c2964997..749df3f2fc612 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -2269,6 +2269,8 @@ static Attribute::AttrKind getAttrFromCode(uint64_t Code) { return Attribute::DeadOnReturn; case bitc::ATTR_KIND_NO_CREATE_UNDEF_OR_POISON: return Attribute::NoCreateUndefOrPoison; + case bitc::ATTR_KIND_DENORMAL_FPENV: + return Attribute::DenormalFPEnv; } } @@ -2442,6 +2444,10 @@ Error BitcodeReader::parseAttributeGroupBlock() { else if (Kind == Attribute::NoFPClass) B.addNoFPClassAttr( static_cast(Record[++i] & fcAllFlags)); + else if (Kind == Attribute::DenormalFPEnv) { + B.addDenormalFPEnvAttr( + DenormalFPEnv::createFromIntValue(Record[++i])); + } } else if (Record[i] == 3 || Record[i] == 4) { // String attribute bool HasValue = (Record[i++] == 4); SmallString<64> KindStr; diff --git a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp index a12176d5bfdbb..4bc55232a6df6 100644 --- a/llvm/lib/Bitcode/Reader/MetadataLoader.cpp +++ b/llvm/lib/Bitcode/Reader/MetadataLoader.cpp @@ -116,6 +116,8 @@ class BitcodeReaderMetadataList { RefsUpperBound(std::min((size_t)std::numeric_limits::max(), RefsUpperBound)) {} + using const_iterator = SmallVector::const_iterator; + // vector compatibility methods unsigned size() const { return MetadataPtrs.size(); } void resize(unsigned N) { MetadataPtrs.resize(N); } @@ -124,6 +126,8 @@ class BitcodeReaderMetadataList { Metadata *back() const { return MetadataPtrs.back(); } void pop_back() { MetadataPtrs.pop_back(); } bool empty() const { return MetadataPtrs.empty(); } + const_iterator begin() const { return MetadataPtrs.begin(); } + const_iterator end() const { return MetadataPtrs.end(); } Metadata *operator[](unsigned i) const { return MetadataPtrs[i]; } @@ -448,6 +452,11 @@ class MetadataLoader::MetadataLoaderImpl { /// metadata. SmallDenseMap FunctionsWithSPs; + /// retainedNodes of these subprograms should be cleaned up from incorrectly + /// scoped local types. + /// See \ref DISubprogram::cleanupRetainedNodes. + SmallVector NewDistinctSPs; + // Map the bitcode's custom MDKind ID to the Module's MDKind ID. DenseMap MDKindMap; @@ -538,56 +547,82 @@ class MetadataLoader::MetadataLoaderImpl { /// Move local imports from DICompileUnit's 'imports' field to /// DISubprogram's retainedNodes. + /// Move function-local enums from DICompileUnit's enums + /// to DISubprogram's retainedNodes. void upgradeCULocals() { - if (NamedMDNode *CUNodes = TheModule.getNamedMetadata("llvm.dbg.cu")) { - for (MDNode *N : CUNodes->operands()) { - auto *CU = dyn_cast(N); - if (!CU) - continue; - - if (CU->getRawImportedEntities()) { - // Collect a set of imported entities to be moved. - SetVector EntitiesToRemove; - for (Metadata *Op : CU->getImportedEntities()->operands()) { - auto *IE = cast(Op); - if (isa_and_nonnull(IE->getScope())) { - EntitiesToRemove.insert(IE); - } - } - - if (!EntitiesToRemove.empty()) { - // Make a new list of CU's 'imports'. - SmallVector NewImports; - for (Metadata *Op : CU->getImportedEntities()->operands()) { - if (!EntitiesToRemove.contains(cast(Op))) { - NewImports.push_back(Op); - } - } + NamedMDNode *CUNodes = TheModule.getNamedMetadata("llvm.dbg.cu"); + if (!CUNodes) + return; - // Find DISubprogram corresponding to each entity. - std::map> SPToEntities; - for (auto *I : EntitiesToRemove) { - auto *Entity = cast(I); - if (auto *SP = findEnclosingSubprogram( - cast(Entity->getScope()))) { - SPToEntities[SP].push_back(Entity); - } - } + // Filter out elements of ToRemove from tuple T. + auto FilterTuple = [this](MDNode *T, + const SetVector &ToRemove) { + SmallVector Result; + for (Metadata *Op : T->operands()) + if (!ToRemove.contains(Op)) + Result.push_back(Op); + return MDTuple::get(Context, Result); + }; - // Update DISubprograms' retainedNodes. - for (auto I = SPToEntities.begin(); I != SPToEntities.end(); ++I) { - auto *SP = I->first; - auto RetainedNodes = SP->getRetainedNodes(); - SmallVector MDs(RetainedNodes.begin(), - RetainedNodes.end()); - MDs.append(I->second); - SP->replaceRetainedNodes(MDNode::get(Context, MDs)); - } + // For each CU: + // - Collect local metadata nodes from CU's imports: and enums: lists in + // MetadataToRemove set. + // - Remove metadata nodes of MetadataToRemove set from CU's imports: and + // enums: lists. + // - Group MetadataToRemove items by their parent subprograms (in + // SPToEntities map). + // - For each subprogram SP in SPToEntities: + // - Append collected local metadata nodes to SP's retainedNodes: list. + for (MDNode *N : CUNodes->operands()) { + auto *CU = dyn_cast(N); + if (!CU) + continue; - // Remove entities with local scope from CU. - CU->replaceImportedEntities(MDTuple::get(Context, NewImports)); - } + SetVector MetadataToRemove; + // Collect imported entities to be moved. + if (CU->getRawImportedEntities()) + for (Metadata *Op : CU->getImportedEntities()->operands()) { + auto *IE = cast(Op); + if (isa_and_nonnull(IE->getScope())) + MetadataToRemove.insert(IE); + } + // Collect enums to be moved. + if (CU->getRawEnumTypes()) + for (Metadata *Op : CU->getEnumTypes()->operands()) { + auto *Enum = cast(Op); + if (isa_and_nonnull(Enum->getScope())) + MetadataToRemove.insert(Enum); } + + if (MetadataToRemove.empty()) + continue; + + // Remove entities with local scope from CU. + if (CU->getRawImportedEntities()) + CU->replaceImportedEntities( + FilterTuple(CU->getImportedEntities().get(), MetadataToRemove)); + + // Remove enums with local scope from CU. + if (CU->getRawEnumTypes()) + CU->replaceEnumTypes( + FilterTuple(CU->getEnumTypes().get(), MetadataToRemove)); + + // Find DISubprogram corresponding to each entity. + SmallDenseMap> SPToEntities; + for (auto *I : MetadataToRemove) { + DILocalScope *Scope = + DISubprogram::getRetainedNodeScope(cast(I)); + if (auto *SP = findEnclosingSubprogram(Scope)) + SPToEntities[SP].push_back(I); + } + + // Update DISubprograms' retainedNodes. + for (auto I = SPToEntities.begin(); I != SPToEntities.end(); ++I) { + auto *SP = I->first; + auto RetainedNodes = SP->getRetainedNodes(); + SmallVector MDs(RetainedNodes.begin(), RetainedNodes.end()); + MDs.append(I->second); + SP->replaceRetainedNodes(MDNode::get(Context, MDs)); } } @@ -703,13 +738,40 @@ class MetadataLoader::MetadataLoaderImpl { return Error::success(); } - void upgradeDebugInfo(bool ModuleLevel) { + /// Specifies which kind of debug info upgrade should be performed. + /// + /// The upgrade of compile units' enums: and imports: fields is performed + /// only when module level metadata block is loaded (i.e. all elements of + /// "llvm.dbg.cu" named metadata node are loaded). + enum class DebugInfoUpgradeMode { + /// No debug info upgrade. + None, + /// Debug info upgrade after loading function-level metadata block. + Partial, + /// Debug info upgrade after loading module-level metadata block. + ModuleLevel, + }; + + void upgradeDebugInfo(DebugInfoUpgradeMode Mode) { + if (Mode == DebugInfoUpgradeMode::None) + return; upgradeCUSubprograms(); upgradeCUVariables(); - if (ModuleLevel) + if (Mode == DebugInfoUpgradeMode::ModuleLevel) upgradeCULocals(); } + /// Prepare loaded metadata nodes to be used by loader clients. + void resolveLoadedMetadata(PlaceholderQueue &Placeholders, + DebugInfoUpgradeMode DIUpgradeMode) { + resolveForwardRefsAndPlaceholders(Placeholders); + upgradeDebugInfo(DIUpgradeMode); + DISubprogram::cleanupRetainedNodes(NewDistinctSPs); + LLVM_DEBUG(llvm::dbgs() << "Resolved loaded metadata. Cleaned up " + << NewDistinctSPs.size() << " subprogram(s).\n"); + NewDistinctSPs.clear(); + } + void callMDTypeCallback(Metadata **Val, unsigned TypeID); public: @@ -735,7 +797,8 @@ class MetadataLoader::MetadataLoaderImpl { if (ID < (MDStringRef.size() + GlobalMetadataBitPosIndex.size())) { PlaceholderQueue Placeholders; lazyLoadOneMetadata(ID, Placeholders); - resolveForwardRefsAndPlaceholders(Placeholders); + LLVM_DEBUG(llvm::dbgs() << "\nLazy metadata loading: "); + resolveLoadedMetadata(Placeholders, DebugInfoUpgradeMode::None); return MetadataList.lookup(ID); } return MetadataList.getMetadataFwdRef(ID); @@ -1060,6 +1123,8 @@ Error MetadataLoader::MetadataLoaderImpl::parseMetadata(bool ModuleLevel) { SmallVector Record; PlaceholderQueue Placeholders; + auto DIUpgradeMode = ModuleLevel ? DebugInfoUpgradeMode::ModuleLevel + : DebugInfoUpgradeMode::Partial; // We lazy-load module-level metadata: we build an index for each record, and // then load individual record as needed, starting with the named metadata. @@ -1084,8 +1149,8 @@ Error MetadataLoader::MetadataLoaderImpl::parseMetadata(bool ModuleLevel) { // Reading the named metadata created forward references and/or // placeholders, that we flush here. - resolveForwardRefsAndPlaceholders(Placeholders); - upgradeDebugInfo(ModuleLevel); + LLVM_DEBUG(llvm::dbgs() << "\nNamed metadata loading: "); + resolveLoadedMetadata(Placeholders, DIUpgradeMode); // Return at the beginning of the block, since it is easy to skip it // entirely from there. Stream.ReadBlockEnd(); // Pop the abbrev block context. @@ -1115,8 +1180,8 @@ Error MetadataLoader::MetadataLoaderImpl::parseMetadata(bool ModuleLevel) { case BitstreamEntry::Error: return error("Malformed block"); case BitstreamEntry::EndBlock: - resolveForwardRefsAndPlaceholders(Placeholders); - upgradeDebugInfo(ModuleLevel); + LLVM_DEBUG(llvm::dbgs() << "\nEager metadata loading: "); + resolveLoadedMetadata(Placeholders, DIUpgradeMode); return Error::success(); case BitstreamEntry::Record: // The interesting case. @@ -1999,6 +2064,9 @@ Error MetadataLoader::MetadataLoaderImpl::parseOneMetadata( MetadataList.assignValue(SP, NextMetadataNo); NextMetadataNo++; + if (IsDistinct) + NewDistinctSPs.push_back(SP); + // Upgrade sp->function mapping to function->sp mapping. if (HasFn) { if (auto *CMD = dyn_cast_or_null(CUorFn)) @@ -2482,7 +2550,8 @@ Error MetadataLoader::MetadataLoaderImpl::parseMetadataAttachment( case BitstreamEntry::Error: return error("Malformed block"); case BitstreamEntry::EndBlock: - resolveForwardRefsAndPlaceholders(Placeholders); + LLVM_DEBUG(llvm::dbgs() << "\nAttachment metadata loading: "); + resolveLoadedMetadata(Placeholders, DebugInfoUpgradeMode::None); return Error::success(); case BitstreamEntry::Record: // The interesting case. @@ -2525,7 +2594,8 @@ Error MetadataLoader::MetadataLoaderImpl::parseMetadataAttachment( // Load the attachment if it is in the lazy-loadable range and hasn't // been loaded yet. lazyLoadOneMetadata(Idx, Placeholders); - resolveForwardRefsAndPlaceholders(Placeholders); + LLVM_DEBUG(llvm::dbgs() << "\nLazy attachment metadata loading: "); + resolveLoadedMetadata(Placeholders, DebugInfoUpgradeMode::None); } Metadata *Node = MetadataList.getMetadataFwdRef(Idx); diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 8bc98c92bc698..2566b2a292300 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -954,6 +954,8 @@ static uint64_t getAttrKindEncoding(Attribute::AttrKind Kind) { return bitc::ATTR_KIND_DEAD_ON_RETURN; case Attribute::NoCreateUndefOrPoison: return bitc::ATTR_KIND_NO_CREATE_UNDEF_OR_POISON; + case Attribute::DenormalFPEnv: + return bitc::ATTR_KIND_DENORMAL_FPENV; case Attribute::EndAttrKinds: llvm_unreachable("Can not encode end-attribute kinds marker."); case Attribute::None: diff --git a/llvm/lib/CAS/BuiltinObjectHasher.cpp b/llvm/lib/CAS/BuiltinObjectHasher.cpp new file mode 100644 index 0000000000000..756954b0f0808 --- /dev/null +++ b/llvm/lib/CAS/BuiltinObjectHasher.cpp @@ -0,0 +1,51 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/CAS/BuiltinObjectHasher.h" +#include "llvm/Support/BLAKE3.h" + +using namespace llvm; +using namespace llvm::cas; + +template +Expected::HashT> +BuiltinObjectHasher::hashFile(StringRef FilePath) { + BuiltinObjectHasher H; + H.updateSize(0); // 0 refs + + sys::fs::file_t FD; + if (Error E = sys::fs::openNativeFileForRead(FilePath).moveInto(FD)) + return E; + + sys::fs::file_status Status; + std::error_code EC = sys::fs::status(FD, Status); + if (EC) + return createFileError(FilePath, EC); + // FIXME: Do we need to add a hash of the data size? If we remove that we can + // avoid needing to read the file size before reading the file contents. + H.updateSize(Status.getSize()); + + size_t ChunkSize = sys::fs::DefaultReadChunkSize; + SmallVector Buffer; + Buffer.resize_for_overwrite(ChunkSize); + for (;;) { + Expected ReadBytes = + sys::fs::readNativeFile(FD, MutableArrayRef(Buffer.begin(), ChunkSize)); + if (!ReadBytes) + return ReadBytes.takeError(); + if (*ReadBytes == 0) + break; + H.Hasher.update(toStringRef(ArrayRef(Buffer).take_front(*ReadBytes))); + } + + return H.finish(); +} + +// Provide the definition for when using the BLAKE3 hasher. +template Expected::HashT> +BuiltinObjectHasher::hashFile(StringRef FilePath); diff --git a/llvm/lib/CAS/CMakeLists.txt b/llvm/lib/CAS/CMakeLists.txt index 605c548ba994f..b17fa84558bab 100644 --- a/llvm/lib/CAS/CMakeLists.txt +++ b/llvm/lib/CAS/CMakeLists.txt @@ -6,6 +6,7 @@ add_llvm_component_library(LLVMCAS ActionCache.cpp ActionCaches.cpp BuiltinCAS.cpp + BuiltinObjectHasher.cpp BuiltinUnifiedCASDatabases.cpp CASNodeSchema.cpp DatabaseFile.cpp diff --git a/llvm/lib/CAS/OnDiskGraphDB.cpp b/llvm/lib/CAS/OnDiskGraphDB.cpp index 2aaec22b10701..3a92acda68462 100644 --- a/llvm/lib/CAS/OnDiskGraphDB.cpp +++ b/llvm/lib/CAS/OnDiskGraphDB.cpp @@ -65,6 +65,7 @@ #include #include #include +#include #define DEBUG_TYPE "on-disk-cas" @@ -353,6 +354,13 @@ struct DataRecordHandle { struct OnDiskContent { std::optional Record; std::optional> Bytes; + + ArrayRef getData() const { + if (Bytes) + return *Bytes; + assert(Record && "Expected record or bytes"); + return Record->getData(); + } }; /// Data loaded inside the memory from standalone file. @@ -360,9 +368,12 @@ class StandaloneDataInMemory { public: OnDiskContent getContent() const; + OnDiskGraphDB::FileBackedData + getInternalFileBackedObjectData(StringRef RootPath) const; + StandaloneDataInMemory(std::unique_ptr Region, - TrieRecord::StorageKind SK) - : Region(std::move(Region)), SK(SK) { + TrieRecord::StorageKind SK, FileOffset IndexOffset) + : Region(std::move(Region)), SK(SK), IndexOffset(IndexOffset) { #ifndef NDEBUG bool IsStandalone = false; switch (SK) { @@ -381,6 +392,7 @@ class StandaloneDataInMemory { private: std::unique_ptr Region; TrieRecord::StorageKind SK; + FileOffset IndexOffset; }; /// Container to lookup loaded standalone objects. @@ -389,7 +401,8 @@ template class StandaloneDataMap { public: uintptr_t insert(ArrayRef Hash, TrieRecord::StorageKind SK, - std::unique_ptr Region); + std::unique_ptr Region, + FileOffset IndexOffset); const StandaloneDataInMemory *lookup(ArrayRef Hash) const; bool count(ArrayRef Hash) const { return bool(lookup(Hash)); } @@ -476,12 +489,14 @@ struct OnDiskGraphDB::IndexProxy { template uintptr_t StandaloneDataMap::insert( ArrayRef Hash, TrieRecord::StorageKind SK, - std::unique_ptr Region) { + std::unique_ptr Region, + FileOffset IndexOffset) { auto &S = getShard(Hash); std::lock_guard Lock(S.Mutex); auto &V = S.Map[Hash.data()]; if (!V) - V = std::make_unique(std::move(Region), SK); + V = std::make_unique(std::move(Region), SK, + IndexOffset); return reinterpret_cast(V.get()); } @@ -949,7 +964,8 @@ Error OnDiskGraphDB::validate(bool Deep, HashingFuncT Hasher) const { case TrieRecord::StorageKind::StandaloneLeaf: case TrieRecord::StorageKind::StandaloneLeaf0: SmallString<256> Path; - getStandalonePath(TrieRecord::getStandaloneFilePrefix(D.SK), *I, Path); + getStandalonePath(TrieRecord::getStandaloneFilePrefix(D.SK), I->Offset, + Path); // If need to validate the content of the file later, just load the // buffer here. Otherwise, just check the existance of the file. if (Deep) { @@ -1201,28 +1217,37 @@ ArrayRef OnDiskGraphDB::getDigest(const IndexProxy &I) const { return I.Hash; } -static OnDiskContent getContentFromHandle(const OnDiskDataAllocator &DataPool, - ObjectHandle OH) { +static std::variant +getStandaloneDataOrDataRecord(const OnDiskDataAllocator &DataPool, + ObjectHandle OH) { // Decode ObjectHandle to locate the stored content. uint64_t Data = OH.getOpaqueData(); if (Data & 1) { const auto *SDIM = reinterpret_cast(Data & (-1ULL << 1)); - return SDIM->getContent(); + return SDIM; } auto DataHandle = cantFail(DataRecordHandle::getFromDataPool(DataPool, FileOffset(Data))); assert(DataHandle.getData().end()[0] == 0 && "Null termination"); - return OnDiskContent{DataHandle, std::nullopt}; + return DataHandle; +} + +static OnDiskContent getContentFromHandle(const OnDiskDataAllocator &DataPool, + ObjectHandle OH) { + auto SDIMOrRecord = getStandaloneDataOrDataRecord(DataPool, OH); + if (std::holds_alternative(SDIMOrRecord)) { + return std::get(SDIMOrRecord)->getContent(); + } else { + auto DataHandle = std::get(std::move(SDIMOrRecord)); + return OnDiskContent{std::move(DataHandle), std::nullopt}; + } } ArrayRef OnDiskGraphDB::getObjectData(ObjectHandle Node) const { OnDiskContent Content = getContentFromHandle(DataPool, Node); - if (Content.Bytes) - return *Content.Bytes; - assert(Content.Record && "Expected record or bytes"); - return Content.Record->getData(); + return Content.getData(); } InternalRefArrayRef OnDiskGraphDB::getInternalRefs(ObjectHandle Node) const { @@ -1232,6 +1257,18 @@ InternalRefArrayRef OnDiskGraphDB::getInternalRefs(ObjectHandle Node) const { return std::nullopt; } +OnDiskGraphDB::FileBackedData +OnDiskGraphDB::getInternalFileBackedObjectData(ObjectHandle Node) const { + auto SDIMOrRecord = getStandaloneDataOrDataRecord(DataPool, Node); + if (std::holds_alternative(SDIMOrRecord)) { + auto *SDIM = std::get(SDIMOrRecord); + return SDIM->getInternalFileBackedObjectData(RootPath); + } else { + auto DataHandle = std::get(std::move(SDIMOrRecord)); + return FileBackedData{DataHandle.getData(), /*FileInfo=*/std::nullopt}; + } +} + Expected> OnDiskGraphDB::load(ObjectID ExternalRef) { InternalRef Ref = getInternalRef(ExternalRef); @@ -1269,7 +1306,8 @@ OnDiskGraphDB::load(ObjectID ExternalRef) { // suitably 0-padded. Requiring null-termination here would be too expensive // for extremely large objects that happen to be page-aligned. SmallString<256> Path; - getStandalonePath(TrieRecord::getStandaloneFilePrefix(Object.SK), *I, Path); + getStandalonePath(TrieRecord::getStandaloneFilePrefix(Object.SK), I->Offset, + Path); auto BypassSandbox = sys::sandbox::scopedDisable(); @@ -1291,7 +1329,7 @@ OnDiskGraphDB::load(ObjectID ExternalRef) { return ObjectHandle::fromMemory( static_cast(StandaloneData) - ->insert(I->Hash, Object.SK, std::move(Region))); + ->insert(I->Hash, Object.SK, std::move(Region), I->Offset)); } Expected OnDiskGraphDB::isMaterialized(ObjectID Ref) { @@ -1337,11 +1375,17 @@ InternalRef OnDiskGraphDB::makeInternalRef(FileOffset IndexOffset) { return InternalRef::getFromOffset(IndexOffset); } -void OnDiskGraphDB::getStandalonePath(StringRef Prefix, const IndexProxy &I, - SmallVectorImpl &Path) const { +static void getStandalonePath(StringRef RootPath, StringRef Prefix, + FileOffset IndexOffset, + SmallVectorImpl &Path) { Path.assign(RootPath.begin(), RootPath.end()); sys::path::append(Path, - Prefix + Twine(I.Offset.get()) + "." + CASFormatVersion); + Prefix + Twine(IndexOffset.get()) + "." + CASFormatVersion); +} + +void OnDiskGraphDB::getStandalonePath(StringRef Prefix, FileOffset IndexOffset, + SmallVectorImpl &Path) const { + return ::getStandalonePath(RootPath, Prefix, IndexOffset, Path); } OnDiskContent StandaloneDataInMemory::getContent() const { @@ -1374,6 +1418,29 @@ OnDiskContent StandaloneDataInMemory::getContent() const { return OnDiskContent{Record, std::nullopt}; } +OnDiskGraphDB::FileBackedData +StandaloneDataInMemory::getInternalFileBackedObjectData( + StringRef RootPath) const { + switch (SK) { + case TrieRecord::StorageKind::Unknown: + case TrieRecord::StorageKind::DataPool: + llvm_unreachable("unexpected storage kind"); + case TrieRecord::StorageKind::Standalone: + return OnDiskGraphDB::FileBackedData{getContent().getData(), + /*FileInfo=*/std::nullopt}; + case TrieRecord::StorageKind::StandaloneLeaf0: + case TrieRecord::StorageKind::StandaloneLeaf: + bool IsFileNulTerminated = SK == TrieRecord::StorageKind::StandaloneLeaf0; + SmallString<256> Path; + ::getStandalonePath(RootPath, TrieRecord::getStandaloneFilePrefix(SK), + IndexOffset, Path); + return OnDiskGraphDB::FileBackedData{ + getContent().getData(), OnDiskGraphDB::FileBackedData::FileInfoTy{ + std::string(Path), IsFileNulTerminated}}; + } + llvm_unreachable("Unknown StorageKind enum"); +} + static Expected createTempFile(StringRef FinalPath, uint64_t Size, OnDiskCASLogger *Logger) { auto BypassSandbox = sys::sandbox::scopedDisable(); @@ -1413,7 +1480,7 @@ Error OnDiskGraphDB::createStandaloneLeaf(IndexProxy &I, ArrayRef Data) { SmallString<256> Path; int64_t FileSize = Data.size() + Leaf0; - getStandalonePath(TrieRecord::getStandaloneFilePrefix(SK), I, Path); + getStandalonePath(TrieRecord::getStandaloneFilePrefix(SK), I.Offset, Path); auto BypassSandbox = sys::sandbox::scopedDisable(); @@ -1484,7 +1551,7 @@ Error OnDiskGraphDB::store(ObjectID ID, ArrayRef Refs, auto AllocStandaloneFile = [&](size_t Size) -> Expected { getStandalonePath(TrieRecord::getStandaloneFilePrefix( TrieRecord::StorageKind::Standalone), - *I, Path); + I->Offset, Path); if (Error E = createTempFile(Path, Size, Logger.get()).moveInto(File)) return std::move(E); assert(File->size() == Size); @@ -1567,6 +1634,117 @@ Error OnDiskGraphDB::store(ObjectID ID, ArrayRef Refs, return Error::success(); } +Error OnDiskGraphDB::storeFile(ObjectID ID, StringRef FilePath) { + return storeFile(ID, FilePath, /*ImportKind=*/std::nullopt); +} + +Error OnDiskGraphDB::storeFile( + ObjectID ID, StringRef FilePath, + std::optional ImportKind) { + auto I = getIndexProxyFromRef(getInternalRef(ID)); + if (LLVM_UNLIKELY(!I)) + return I.takeError(); + + // Early return in case the node exists. + { + TrieRecord::Data Existing = I->Ref.load(); + if (Existing.SK != TrieRecord::StorageKind::Unknown) + return Error::success(); + } + + auto BypassSandbox = sys::sandbox::scopedDisable(); + + uint64_t FileSize; + if (std::error_code EC = sys::fs::file_size(FilePath, FileSize)) + return createFileError(FilePath, EC); + + if (FileSize <= TrieRecord::MaxEmbeddedSize) { + auto Buf = MemoryBuffer::getFile(FilePath); + if (!Buf) + return createFileError(FilePath, Buf.getError()); + return store(ID, {}, arrayRefFromStringRef((*Buf)->getBuffer())); + } + + StringRef FromPath; + SmallString<256> TmpPath; + + auto RemoveTmpFile = scope_exit([&TmpPath] { + if (!TmpPath.empty()) + sys::fs::remove(TmpPath); + }); + + // \c clonefile requires that the destination path doesn't exist. We create + // a "placeholder" temporary file, then modify its path a bit and use that + // for \c clonefile to write to. + // FIXME: Instead of creating a dummy file, add a new file system API for + // copying to a unique path that can loop while checking EEXIST. + SmallString<256> UniqueTmpPath; + if (std::error_code EC = + sys::fs::createUniqueFile(RootPath + "/tmp.%%%%%%%", UniqueTmpPath)) + return createFileError(RootPath + "/tmp.%%%%%%%", EC); + auto RemoveUniqueFile = + scope_exit([&UniqueTmpPath] { sys::fs::remove(UniqueTmpPath); }); + TmpPath = UniqueTmpPath; + TmpPath += 'c'; // modify so that there's no file at that path. + // \c copy_file will use \c clonefile when applicable. + if (std::error_code EC = sys::fs::copy_file(FilePath, TmpPath)) + return createFileError(FilePath, EC); + FromPath = TmpPath; + + TrieRecord::StorageKind SK; + if (ImportKind.has_value()) { + // Importing the file from upstream, the nul is already added if necessary. + switch (*ImportKind) { + case InternalUpstreamImportKind::Leaf: + SK = TrieRecord::StorageKind::StandaloneLeaf; + break; + case InternalUpstreamImportKind::Leaf0: + SK = TrieRecord::StorageKind::StandaloneLeaf0; + break; + } + } else { + bool Leaf0 = isAligned(Align(getPageSize()), FileSize); + SK = Leaf0 ? TrieRecord::StorageKind::StandaloneLeaf0 + : TrieRecord::StorageKind::StandaloneLeaf; + + if (Leaf0) { + // Add a nul byte at the end. + std::error_code EC; + raw_fd_ostream OS(FromPath, EC, sys::fs::CD_OpenExisting, + sys::fs::FA_Write, sys::fs::OF_Append); + if (EC) + return createFileError(FromPath, EC); + OS.write(0); + OS.close(); + if (OS.has_error()) + return createFileError(FromPath, OS.error()); + } + } + + SmallString<256> StandalonePath; + getStandalonePath(TrieRecord::getStandaloneFilePrefix(SK), I->Offset, + StandalonePath); + if (std::error_code EC = sys::fs::rename(FromPath, StandalonePath)) + return createFileError(FromPath, EC); + TmpPath.clear(); + + // Store the object reference. + TrieRecord::Data Existing; + { + TrieRecord::Data Leaf{SK, FileOffset()}; + if (I->Ref.compare_exchange_strong(Existing, Leaf)) { + recordStandaloneSizeIncrease(FileSize); + return Error::success(); + } + } + + // If there was a race, confirm that the new value has valid storage. + if (Existing.SK == TrieRecord::StorageKind::Unknown) + return createCorruptObjectError(getDigest(*I)); + + return Error::success(); +} + void OnDiskGraphDB::recordStandaloneSizeIncrease(size_t SizeIncrease) { standaloneStorageSize().fetch_add(SizeIncrease, std::memory_order_relaxed); } @@ -1715,8 +1893,6 @@ Error OnDiskGraphDB::importFullTree(ObjectID PrimaryID, UpstreamCursor &Cur = CursorStack.back(); if (Cur.RefI == Cur.RefE) { // Copy the node data into the primary store. - // FIXME: Use hard-link or cloning if the file-system supports it and data - // is stored into a separate file. // The bottom of \p PrimaryNodesStack contains the primary ID for the // current node plus the list of imported referenced IDs. @@ -1724,8 +1900,7 @@ Error OnDiskGraphDB::importFullTree(ObjectID PrimaryID, ObjectID PrimaryID = *(PrimaryNodesStack.end() - Cur.RefsCount - 1); auto PrimaryRefs = ArrayRef(PrimaryNodesStack) .slice(PrimaryNodesStack.size() - Cur.RefsCount); - auto Data = UpstreamDB->getObjectData(Cur.Node); - if (Error E = store(PrimaryID, PrimaryRefs, Data)) + if (Error E = importUpstreamData(PrimaryID, PrimaryRefs, Cur.Node)) return E; // Remove the current node and its IDs from the stack. PrimaryNodesStack.truncate(PrimaryNodesStack.size() - Cur.RefsCount); @@ -1760,10 +1935,6 @@ Error OnDiskGraphDB::importSingleNode(ObjectID PrimaryID, ObjectHandle UpstreamNode) { // Copies only a single node, it doesn't copy the referenced nodes. - // Copy the node data into the primary store. - // FIXME: Use hard-link or cloning if the file-system supports it and data is - // stored into a separate file. - auto Data = UpstreamDB->getObjectData(UpstreamNode); auto UpstreamRefs = UpstreamDB->getObjectRefs(UpstreamNode); SmallVector Refs; Refs.reserve(llvm::size(UpstreamRefs)); @@ -1774,7 +1945,29 @@ Error OnDiskGraphDB::importSingleNode(ObjectID PrimaryID, Refs.push_back(*Ref); } - return store(PrimaryID, Refs, Data); + return importUpstreamData(PrimaryID, Refs, UpstreamNode); +} + +Error OnDiskGraphDB::importUpstreamData(ObjectID PrimaryID, + ArrayRef PrimaryRefs, + ObjectHandle UpstreamNode) { + // If there are references we can't copy an upstream's standalone file because + // we need to re-resolve the reference offsets it contains. + if (PrimaryRefs.empty()) { + auto FBData = UpstreamDB->getInternalFileBackedObjectData(UpstreamNode); + if (FBData.FileInfo.has_value()) { + // Disk-space optimization, import the file directly since it is a + // standalone leaf. + return storeFile( + PrimaryID, FBData.FileInfo->FilePath, + /*InternalUpstreamImport=*/FBData.FileInfo->IsFileNulTerminated + ? InternalUpstreamImportKind::Leaf0 + : InternalUpstreamImportKind::Leaf); + } + } + + auto Data = UpstreamDB->getObjectData(UpstreamNode); + return store(PrimaryID, PrimaryRefs, Data); } Expected> diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index f58e4b82440be..d968ead83e5ed 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -222,17 +222,6 @@ class AddrLabelMapCallbackPtr final : CallbackVH { }; } // namespace -namespace callgraph { -LLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE(); -enum Flags : uint8_t { - None = 0, - IsIndirectTarget = 1u << 0, - HasDirectCallees = 1u << 1, - HasIndirectCallees = 1u << 2, - LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue*/ HasIndirectCallees) -}; -} // namespace callgraph - class llvm::AddrLabelMap { MCContext &Context; struct AddrLabelSymEntry { @@ -2558,9 +2547,6 @@ void AsmPrinter::emitGlobalAlias(const Module &M, const GlobalAlias &GA) { } void AsmPrinter::emitGlobalIFunc(Module &M, const GlobalIFunc &GI) { - assert(!TM.getTargetTriple().isOSBinFormatXCOFF() && - "IFunc is not supported on AIX."); - auto EmitLinkage = [&](MCSymbol *Sym) { if (GI.hasExternalLinkage() || !MAI->getWeakRefDirective()) OutStreamer->emitSymbolAttribute(Sym, MCSA_Global); @@ -2905,6 +2891,15 @@ bool AsmPrinter::doFinalization(Module &M) { // sections after DWARF. for (const auto &IFunc : M.ifuncs()) emitGlobalIFunc(M, IFunc); + if (TM.getTargetTriple().isOSBinFormatXCOFF() && hasDebugInfo()) { + // Emit section end. This is used to tell the debug line section where the + // end is for a text section if we don't use .loc to represent the debug + // line. + auto *Sec = OutContext.getObjectFileInfo()->getTextSection(); + OutStreamer->switchSectionNoPrint(Sec); + MCSymbol *Sym = Sec->getEndSymbol(OutContext); + OutStreamer->emitLabel(Sym); + } // Finalize debug and EH information. for (auto &Handler : Handlers) diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp index b815386e400cb..e87d3f3ee02a0 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp @@ -644,10 +644,9 @@ void DwarfCompileUnit::constructScopeDIE(LexicalScope *Scope, return; // Emit lexical blocks. - DIE *ScopeDIE = constructLexicalScopeDIE(Scope); + DIE *ScopeDIE = getOrCreateLexicalBlockDIE(Scope, ParentScopeDIE); assert(ScopeDIE && "Scope DIE should not be null."); - ParentScopeDIE.addChild(ScopeDIE); createAndAddScopeChildren(Scope, *ScopeDIE); } @@ -768,14 +767,15 @@ DIE *DwarfCompileUnit::constructInlinedScopeDIE(LexicalScope *Scope, return ScopeDIE; } -// Construct new DW_TAG_lexical_block for this scope and attach -// DW_AT_low_pc/DW_AT_high_pc labels. -DIE *DwarfCompileUnit::constructLexicalScopeDIE(LexicalScope *Scope) { +DIE *DwarfCompileUnit::getOrCreateLexicalBlockDIE(LexicalScope *Scope, + DIE &ParentScopeDIE) { if (DD->isLexicalScopeDIENull(Scope)) return nullptr; const auto *DS = Scope->getScopeNode(); auto ScopeDIE = DIE::get(DIEValueAllocator, dwarf::DW_TAG_lexical_block); + ParentScopeDIE.addChild(ScopeDIE); + if (Scope->isAbstractScope()) { assert(!getAbstractScopeDIEs().count(DS) && "Abstract DIE for this scope exists!"); @@ -1839,7 +1839,7 @@ void DwarfCompileUnit::createBaseTypeDIEs() { } } -DIE *DwarfCompileUnit::getLexicalBlockDIE(const DILexicalBlock *LB) { +DIE *DwarfCompileUnit::getLocalContextDIE(const DILexicalBlock *LB) { // Assume if there is an abstract tree all the DIEs are already emitted. bool isAbstract = getAbstractScopeDIEs().count(LB->getSubprogram()); if (isAbstract) { @@ -1849,8 +1849,14 @@ DIE *DwarfCompileUnit::getLexicalBlockDIE(const DILexicalBlock *LB) { } assert(!isAbstract && "Missed lexical block DIE in abstract tree!"); - // Return a concrete DIE if it exists or nullptr otherwise. - return LexicalBlockDIEs.lookup(LB); + // Check if we have a concrete DIE. + if (auto It = LexicalBlockDIEs.find(LB); It != LexicalBlockDIEs.end()) + return It->second; + + // If nothing available found, we cannot just create a new lexical block, + // because it isn't known where to put it into the DIE tree. + // So, we may only try to find the most close avaiable parent DIE. + return getOrCreateContextDIE(LB->getScope()->getNonLexicalBlockFileScope()); } DIE *DwarfCompileUnit::getOrCreateContextDIE(const DIScope *Context) { @@ -1858,7 +1864,7 @@ DIE *DwarfCompileUnit::getOrCreateContextDIE(const DIScope *Context) { if (auto *LFScope = dyn_cast(Context)) Context = LFScope->getNonLexicalBlockFileScope(); if (auto *LScope = dyn_cast(Context)) - return getLexicalBlockDIE(LScope); + return getLocalContextDIE(LScope); // Otherwise the context must be a DISubprogram. auto *SPScope = cast(Context); diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h index a90fec0da0837..04d4556c3ce52 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h @@ -257,14 +257,9 @@ class DwarfCompileUnit final : public DwarfUnit { /// DIE to represent this concrete inlined copy of the function. DIE *constructInlinedScopeDIE(LexicalScope *Scope, DIE &ParentScopeDIE); - /// Construct new DW_TAG_lexical_block for this scope and - /// attach DW_AT_low_pc/DW_AT_high_pc labels. - DIE *constructLexicalScopeDIE(LexicalScope *Scope); - - /// Get a DIE for the given DILexicalBlock. - /// Note that this function assumes that the DIE has been already created - /// and it's an error, if it hasn't. - DIE *getLexicalBlockDIE(const DILexicalBlock *LB); + /// Get if available or create a new DW_TAG_lexical_block for the given + /// LexicalScope and attach DW_AT_low_pc/DW_AT_high_pc labels. + DIE *getOrCreateLexicalBlockDIE(LexicalScope *Scope, DIE &ParentDIE); /// Construct a DIE for the given DbgVariable. DIE *constructVariableDIE(DbgVariable &DV, bool Abstract = false); @@ -283,6 +278,11 @@ class DwarfCompileUnit final : public DwarfUnit { /// This instance of 'getOrCreateContextDIE()' can handle DILocalScope. DIE *getOrCreateContextDIE(const DIScope *Ty) override; + /// Get DW_TAG_lexical_block for the given DILexicalBlock if available, + /// or the most close parent DIE, if no correspoding DW_TAG_lexical_block + /// exists. + DIE *getLocalContextDIE(const DILexicalBlock *LB); + DIE *getOrCreateSubprogramDIE(const DISubprogram *SP, const Function *F, bool Minimal = false) override; diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index ead5253c4d100..f8c2c753b91ce 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -1289,12 +1289,13 @@ void DwarfDebug::beginModule(Module *M) { CU.getOrCreateGlobalVariableDIE(GV, sortGlobalExprs(GVMap[GV])); } - for (auto *Ty : CUNode->getEnumTypes()) + for (auto *Ty : CUNode->getEnumTypes()) { + assert(!isa_and_nonnull(Ty->getScope()) && + "Unexpected function-local entity in 'enums' CU field."); CU.getOrCreateTypeDIE(cast(Ty)); + } for (auto *Ty : CUNode->getRetainedTypes()) { - // The retained types array by design contains pointers to - // MDNodes rather than DIRefs. Unique them here. if (DIType *RT = dyn_cast(Ty)) // There is no point in force-emitting a forward declaration. CU.getOrCreateTypeDIE(RT); @@ -1495,9 +1496,13 @@ void DwarfDebug::endModule() { "Unexpected function-local entity in 'imports' CU field."); CU->getOrCreateImportedEntityDIE(IE); } + + // Emit function-local entities. for (const auto *D : CU->getDeferredLocalDecls()) { if (auto *IE = dyn_cast(D)) CU->getOrCreateImportedEntityDIE(IE); + else if (auto *Ty = dyn_cast(D)) + CU->getOrCreateTypeDIE(Ty); else llvm_unreachable("Unexpected local retained node!"); } diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp index 3d2a52dab153e..6182c3bbd6a73 100644 --- a/llvm/lib/CodeGen/AtomicExpandPass.cpp +++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp @@ -331,7 +331,7 @@ bool AtomicExpandImpl::processAtomicInstr(Instruction *I) { } else if (RMWI && (isReleaseOrStronger(RMWI->getOrdering()) || isAcquireOrStronger(RMWI->getOrdering()))) { FenceOrdering = RMWI->getOrdering(); - RMWI->setOrdering(AtomicOrdering::Monotonic); + RMWI->setOrdering(TLI->atomicOperationOrderAfterFenceSplit(RMWI)); } else if (CASI && TLI->shouldExpandAtomicCmpXchgInIR(CASI) == TargetLoweringBase::AtomicExpansionKind::None && @@ -1681,6 +1681,9 @@ Value *AtomicExpandImpl::insertRMWCmpXchgLoop( std::prev(BB->end())->eraseFromParent(); Builder.SetInsertPoint(BB); LoadInst *InitLoaded = Builder.CreateAlignedLoad(ResultTy, Addr, AddrAlign); + // TODO: The initial load must be atomic with the same synchronization scope + // to avoid a data race with concurrent stores. If the instruction being + // emulated is volatile, issue a volatile load. Builder.CreateBr(LoopBB); // Start the main loop block now that we've taken care of the preliminaries. diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index 0fb1c744407e2..fec9a3db20142 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -56,10 +56,12 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeGCMachineCodeAnalysisPass(Registry); initializeGCModuleInfoPass(Registry); initializeGlobalMergePass(Registry); + initializeGlobalMergeFuncPassWrapperPass(Registry); initializeHardwareLoopsLegacyPass(Registry); initializeIfConverterPass(Registry); initializeImplicitNullChecksPass(Registry); initializeIndirectBrExpandLegacyPassPass(Registry); + initializeInsertCodePrefetchPass(Registry); initializeInitUndefLegacyPass(Registry); initializeInterleavedLoadCombinePass(Registry); initializeInterleavedAccessPass(Registry); diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index b9cf73a48ee22..bf56ffd3b4b7b 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -6464,8 +6464,7 @@ bool CodeGenPrepare::optimizeMulWithOverflow(Instruction *I, bool IsSigned, Type *LegalTy = Ty->getWithNewBitWidth(VTHalfBitWidth); // New BBs: - BasicBlock *OverflowEntryBB = - I->getParent()->splitBasicBlock(I, "", /*Before*/ true); + BasicBlock *OverflowEntryBB = I->getParent()->splitBasicBlockBefore(I, ""); OverflowEntryBB->takeName(I->getParent()); // Keep the 'br' instruction that is generated as a result of the split to be // erased/replaced later. @@ -6869,7 +6868,8 @@ bool CodeGenPrepare::splitLargeGEPOffsets() { NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt(); else if (InvokeInst *Invoke = dyn_cast(BaseI)) { NewBaseInsertBB = - SplitEdge(NewBaseInsertBB, Invoke->getNormalDest(), DT.get(), LI); + SplitEdge(NewBaseInsertBB, Invoke->getNormalDest(), + &getDT(*NewBaseInsertBB->getParent()), LI); NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt(); } else NewBaseInsertPt = std::next(BaseI->getIterator()); diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp index ef5eabccab480..24f74dbd28b61 100644 --- a/llvm/lib/CodeGen/CommandFlags.cpp +++ b/llvm/lib/CodeGen/CommandFlags.cpp @@ -74,7 +74,6 @@ CGOPT_EXP(uint64_t, LargeDataThreshold) CGOPT(ExceptionHandling, ExceptionModel) CGOPT_EXP(CodeGenFileType, FileType) CGOPT(FramePointerKind, FramePointerUsage) -CGOPT(bool, EnableNoInfsFPMath) CGOPT(bool, EnableNoNaNsFPMath) CGOPT(bool, EnableNoSignedZerosFPMath) CGOPT(bool, EnableNoTrappingFPMath) @@ -233,12 +232,6 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() { "Enable frame pointer elimination"))); CGBINDOPT(FramePointerUsage); - static cl::opt EnableNoInfsFPMath( - "enable-no-infs-fp-math", - cl::desc("Enable FP math optimizations that assume no +-Infs"), - cl::init(false)); - CGBINDOPT(EnableNoInfsFPMath); - static cl::opt EnableNoNaNsFPMath( "enable-no-nans-fp-math", cl::desc("Enable FP math optimizations that assume no NaNs"), @@ -596,7 +589,6 @@ TargetOptions codegen::InitTargetOptionsFromCodeGenFlags(const Triple &TheTriple) { TargetOptions Options; Options.AllowFPOpFusion = getFuseFPOps(); - Options.NoInfsFPMath = getEnableNoInfsFPMath(); Options.NoNaNsFPMath = getEnableNoNaNsFPMath(); Options.NoSignedZerosFPMath = getEnableNoSignedZerosFPMath(); Options.NoTrappingFPMath = getEnableNoTrappingFPMath(); @@ -747,27 +739,19 @@ void codegen::setFunctionAttributes(StringRef CPU, StringRef Features, if (getStackRealign()) NewAttrs.addAttribute("stackrealign"); - HANDLE_BOOL_ATTR(EnableNoInfsFPMathView, "no-infs-fp-math"); HANDLE_BOOL_ATTR(EnableNoNaNsFPMathView, "no-nans-fp-math"); HANDLE_BOOL_ATTR(EnableNoSignedZerosFPMathView, "no-signed-zeros-fp-math"); - if (DenormalFPMathView->getNumOccurrences() > 0 && - !F.hasFnAttribute("denormal-fp-math")) { + if ((DenormalFPMathView->getNumOccurrences() > 0 || + DenormalFP32MathView->getNumOccurrences() > 0) && + !F.hasFnAttribute(Attribute::DenormalFPEnv)) { DenormalMode::DenormalModeKind DenormKind = getDenormalFPMath(); + DenormalMode::DenormalModeKind DenormKindF32 = getDenormalFP32Math(); + DenormalFPEnv FPEnv(DenormalMode{DenormKind, DenormKind}, + DenormalMode{DenormKindF32, DenormKindF32}); // FIXME: Command line flag should expose separate input/output modes. - NewAttrs.addAttribute("denormal-fp-math", - DenormalMode(DenormKind, DenormKind).str()); - } - - if (DenormalFP32MathView->getNumOccurrences() > 0 && - !F.hasFnAttribute("denormal-fp-math-f32")) { - // FIXME: Command line flag should expose separate input/output modes. - DenormalMode::DenormalModeKind DenormKind = getDenormalFP32Math(); - - NewAttrs.addAttribute( - "denormal-fp-math-f32", - DenormalMode(DenormKind, DenormKind).str()); + NewAttrs.addDenormalFPEnvAttr(FPEnv); } if (TrapFuncNameView->getNumOccurrences() > 0) diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp index d2522fd5eb0e3..78111fc038b29 100644 --- a/llvm/lib/CodeGen/DetectDeadLanes.cpp +++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp @@ -94,15 +94,7 @@ static bool isCrossCopy(const MachineRegisterInfo &MRI, } } - unsigned PreA, PreB; // Unused. - if (SrcSubIdx && DstSubIdx) - return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, - PreB); - if (SrcSubIdx) - return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); - if (DstSubIdx) - return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); - return !TRI.getCommonSubClass(SrcRC, DstRC); + return !TRI.findCommonRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx); } void DeadLaneDetector::addUsedLanesOnOperand(const MachineOperand &MO, diff --git a/llvm/lib/CodeGen/ExpandIRInsts.cpp b/llvm/lib/CodeGen/ExpandIRInsts.cpp index 6cbdda6b9870e..07a07872ea86f 100644 --- a/llvm/lib/CodeGen/ExpandIRInsts.cpp +++ b/llvm/lib/CodeGen/ExpandIRInsts.cpp @@ -554,13 +554,15 @@ static void expandFPToI(Instruction *FPToI) { // entry: Builder.SetInsertPoint(Entry); - Value *FloatVal0 = FloatVal; + // We're going to introduce branches on the value, so freeze it. + if (!isGuaranteedNotToBeUndefOrPoison(FloatVal)) + FloatVal = Builder.CreateFreeze(FloatVal); // fp80 conversion is implemented by fpext to fp128 first then do the // conversion. if (FloatVal->getType()->isX86_FP80Ty()) - FloatVal0 = + FloatVal = Builder.CreateFPExt(FloatVal, Type::getFP128Ty(Builder.getContext())); - Value *ARep = Builder.CreateBitCast(FloatVal0, FloatIntTy); + Value *ARep = Builder.CreateBitCast(FloatVal, FloatIntTy); Value *PosOrNeg = Builder.CreateICmpSGT(ARep, ConstantInt::getSigned(FloatIntTy, -1)); Value *Sign = Builder.CreateSelect(PosOrNeg, ConstantInt::getSigned(IntTy, 1), @@ -740,8 +742,17 @@ static void expandIToFP(Instruction *IToFP) { unsigned FloatWidth = PowerOf2Ceil(FPMantissaWidth); bool IsSigned = IToFP->getOpcode() == Instruction::SIToFP; - assert(BitWidth > FloatWidth && "Unexpected conversion. expandIToFP() " - "assumes integer width is larger than fp."); + // We're going to introduce branches on the value, so freeze it. + if (!isGuaranteedNotToBeUndefOrPoison(IntVal)) + IntVal = Builder.CreateFreeze(IntVal); + + // The expansion below assumes that int width >= float width. Zero or sign + // extend the integer accordingly. + if (BitWidth < FloatWidth) { + BitWidth = FloatWidth; + IntTy = Builder.getIntNTy(BitWidth); + IntVal = Builder.CreateIntCast(IntVal, IntTy, IsSigned); + } Value *Temp1 = Builder.CreateShl(Builder.getIntN(BitWidth, 1), diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp index a94b609532c82..94e7ee4fa0855 100644 --- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp +++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp @@ -75,15 +75,14 @@ INITIALIZE_PASS(ExpandPostRALegacy, DEBUG_TYPE, bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); - assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && - MI->getOperand(1).isImm() && - (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && - MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); + assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && + MI->getOperand(1).isReg() && MI->getOperand(1).isUse() && + MI->getOperand(2).isImm() && "Invalid subreg_to_reg"); Register DstReg = MI->getOperand(0).getReg(); - Register InsReg = MI->getOperand(2).getReg(); - assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); - unsigned SubIdx = MI->getOperand(3).getImm(); + Register InsReg = MI->getOperand(1).getReg(); + assert(!MI->getOperand(1).getSubReg() && "SubIdx on physreg?"); + unsigned SubIdx = MI->getOperand(2).getImm(); assert(SubIdx != 0 && "Invalid index for insert_subreg"); Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); @@ -95,39 +94,26 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI); - if (MI->allDefsAreDead()) { + if (MI->allDefsAreDead() || DstSubReg == InsReg) { + // No need to insert an identity copy instruction. + // Watch out for case like this: + // %rax = SUBREG_TO_REG killed %eax, 3 + // We must leave %rax live. MI->setDesc(TII->get(TargetOpcode::KILL)); - MI->removeOperand(3); // SubIdx - MI->removeOperand(1); // Imm + MI->removeOperand(2); // SubIdx LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI); return true; } - if (DstSubReg == InsReg) { - // No need to insert an identity copy instruction. - // Watch out for case like this: - // %rax = SUBREG_TO_REG 0, killed %eax, 3 - // We must leave %rax live. - if (DstReg != InsReg) { - MI->setDesc(TII->get(TargetOpcode::KILL)); - MI->removeOperand(3); // SubIdx - MI->removeOperand(1); // Imm - LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI); - return true; - } - LLVM_DEBUG(dbgs() << "subreg: eliminated!"); - } else { - TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, - MI->getOperand(2).isKill()); - - // Implicitly define DstReg for subsequent uses. - MachineBasicBlock::iterator CopyMI = MI; - --CopyMI; - CopyMI->addRegisterDefined(DstReg); - LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI); - } + TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, + MI->getOperand(1).isKill()); + + // Implicitly define DstReg for subsequent uses. + MachineBasicBlock::iterator CopyMI = MI; + --CopyMI; + CopyMI->addRegisterDefined(DstReg); + LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI); - LLVM_DEBUG(dbgs() << '\n'); MBB->erase(MI); return true; } diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp index d8bb6700188d4..123fecac92a3d 100644 --- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp @@ -435,9 +435,8 @@ const GISelInstProfileBuilder &GISelInstProfileBuilder::addNodeIDMachineOperand( } GISelCSEInfo & -GISelCSEAnalysisWrapper::get(std::unique_ptr CSEOpt, - bool Recompute) { - if (!AlreadyComputed || Recompute) { +GISelCSEAnalysisWrapper::get(std::unique_ptr CSEOpt) { + if (!AlreadyComputed) { Info.releaseMemory(); Info.setCSEConfig(std::move(CSEOpt)); Info.analyze(*MF); diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp index 66b6570e7659c..4256e9a42b889 100644 --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -292,33 +292,28 @@ void CallLowering::splitToValueTypes(const ArgInfo &OrigArg, SmallVectorImpl &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, - SmallVectorImpl *Offsets) const { - LLVMContext &Ctx = OrigArg.Ty->getContext(); + SmallVectorImpl *Offsets) const { + SmallVector SplitTys; + ComputeValueTypes(DL, OrigArg.Ty, SplitTys, Offsets); - SmallVector SplitVTs; - ComputeValueVTs(*TLI, DL, OrigArg.Ty, SplitVTs, /*MemVTs=*/nullptr, Offsets, - 0); - - if (SplitVTs.size() == 0) + if (SplitTys.size() == 0) return; - if (SplitVTs.size() == 1) { + if (SplitTys.size() == 1) { // No splitting to do, but we want to replace the original type (e.g. [1 x // double] -> double). - SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx), - OrigArg.OrigArgIndex, OrigArg.Flags[0], - OrigArg.OrigValue); + SplitArgs.emplace_back(OrigArg.Regs[0], SplitTys[0], OrigArg.OrigArgIndex, + OrigArg.Flags[0], OrigArg.OrigValue); return; } // Create one ArgInfo for each virtual register in the original ArgInfo. - assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch"); + assert(OrigArg.Regs.size() == SplitTys.size() && "Regs / types mismatch"); bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters( OrigArg.Ty, CallConv, false, DL); - for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) { - Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx); - SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex, + for (unsigned i = 0, e = SplitTys.size(); i < e; ++i) { + SplitArgs.emplace_back(OrigArg.Regs[i], SplitTys[i], OrigArg.OrigArgIndex, OrigArg.Flags[0]); if (NeedsRegBlock) SplitArgs.back().Flags[0].setInConsecutiveRegs(); @@ -371,13 +366,10 @@ mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef DstRegs, return B.buildUnmerge(PadDstRegs, UnmergeSrcReg); } -/// Create a sequence of instructions to combine pieces split into register -/// typed values to the original IR value. \p OrigRegs contains the destination -/// value registers of type \p LLTy, and \p Regs contains the legalized pieces -/// with type \p PartLLT. This is used for incoming values (physregs to vregs). -static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef OrigRegs, - ArrayRef Regs, LLT LLTy, LLT PartLLT, - const ISD::ArgFlagsTy Flags) { +void CallLowering::buildCopyFromRegs(MachineIRBuilder &B, + ArrayRef OrigRegs, + ArrayRef Regs, LLT LLTy, + LLT PartLLT, const ISD::ArgFlagsTy Flags) { MachineRegisterInfo &MRI = *B.getMRI(); if (PartLLT == LLTy) { @@ -555,14 +547,9 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef OrigRegs, } } -/// Create a sequence of instructions to expand the value in \p SrcReg (of type -/// \p SrcTy) to the types in \p DstRegs (of type \p PartTy). \p ExtendOp should -/// contain the type of scalar value extension if necessary. -/// -/// This is used for outgoing values (vregs to physregs) -static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef DstRegs, - Register SrcReg, LLT SrcTy, LLT PartTy, - unsigned ExtendOp = TargetOpcode::G_ANYEXT) { +void CallLowering::buildCopyToRegs(MachineIRBuilder &B, + ArrayRef DstRegs, Register SrcReg, + LLT SrcTy, LLT PartTy, unsigned ExtendOp) { // We could just insert a regular copy, but this is unreachable at the moment. assert(SrcTy != PartTy && "identical part types shouldn't reach here"); @@ -700,11 +687,12 @@ bool CallLowering::determineAssignments(ValueAssigner &Assigner, SmallVectorImpl &Args, CCState &CCInfo) const { LLVMContext &Ctx = CCInfo.getContext(); + const DataLayout &DL = CCInfo.getMachineFunction().getDataLayout(); const CallingConv::ID CallConv = CCInfo.getCallingConv(); unsigned NumArgs = Args.size(); for (unsigned i = 0; i != NumArgs; ++i) { - EVT CurVT = EVT::getEVT(Args[i].Ty); + EVT CurVT = TLI->getValueType(DL, Args[i].Ty); MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT); @@ -809,8 +797,9 @@ bool CallLowering::handleAssignments(ValueHandler &Handler, const LLT LocTy(LocVT); const LLT ValTy(ValVT); const LLT NewLLT = Handler.isIncomingArgumentHandler() ? LocTy : ValTy; - const EVT OrigVT = EVT::getEVT(Args[i].Ty); - const LLT OrigTy = getLLTForType(*Args[i].Ty, DL); + const EVT OrigVT = TLI->getValueType(DL, Args[i].Ty); + // Use the EVT here to strip pointerness. + const LLT OrigTy = getLLTForType(*OrigVT.getTypeForEVT(F.getContext()), DL); const LLT PointerTy = LLT::pointer( AllocaAddressSpace, DL.getPointerSizeInBits(AllocaAddressSpace)); diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp index 34692f0b4c4ee..fce06dfde0edc 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp @@ -491,6 +491,26 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known, Known = KnownBits::shl(LHSKnown, RHSKnown); break; } + case TargetOpcode::G_ROTL: + case TargetOpcode::G_ROTR: { + MachineInstr *AmtOpMI = MRI.getVRegDef(MI.getOperand(2).getReg()); + auto MaybeAmtOp = isConstantOrConstantSplatVector(*AmtOpMI, MRI); + if (!MaybeAmtOp) + break; + + Register SrcReg = MI.getOperand(1).getReg(); + computeKnownBitsImpl(SrcReg, Known, DemandedElts, Depth + 1); + + unsigned Amt = MaybeAmtOp->urem(BitWidth); + + // Canonicalize to ROTR. + if (Opcode == TargetOpcode::G_ROTL) + Amt = BitWidth - Amt; + + Known.Zero = Known.Zero.rotr(Amt); + Known.One = Known.One.rotr(Amt); + break; + } case TargetOpcode::G_INTTOPTR: case TargetOpcode::G_PTRTOINT: if (DstTy.isVector()) @@ -681,6 +701,18 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known, Known.Zero.setBitsFrom(LowBits); break; } + case TargetOpcode::G_CTLS: { + Register Reg = MI.getOperand(1).getReg(); + unsigned MinRedundantSignBits = computeNumSignBits(Reg, Depth + 1) - 1; + + unsigned MaxUpperRedundantSignBits = MRI.getType(Reg).getScalarSizeInBits(); + + ConstantRange Range(APInt(BitWidth, MinRedundantSignBits), + APInt(BitWidth, MaxUpperRedundantSignBits)); + + Known = Range.toKnownBits(); + break; + } case TargetOpcode::G_EXTRACT_VECTOR_ELT: { GExtractVectorElement &Extract = cast(MI); Register InVec = Extract.getVectorReg(); diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index a0fe900778cca..56da65cf1ad54 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -258,14 +258,24 @@ int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) { if (!Inserted) return MapEntry->second; - uint64_t Size = - AI.getAllocationSize(*DL).value_or(TypeSize::getZero()).getFixedValue(); + TypeSize TySize = AI.getAllocationSize(*DL).value_or(TypeSize::getZero()); + uint64_t Size = TySize.getKnownMinValue(); // Always allocate at least one byte. Size = std::max(Size, 1u); int &FI = MapEntry->second; FI = MF->getFrameInfo().CreateStackObject(Size, AI.getAlign(), false, &AI); + + // Scalable vectors and structures that contain scalable vectors may + // need a special StackID to distinguish them from other (fixed size) + // stack objects. + if (TySize.isScalable()) { + auto StackID = + MF->getSubtarget().getFrameLowering()->getStackIDForScalableVectors(); + MF->getFrameInfo().setStackID(FI, StackID); + } + return FI; } @@ -2819,20 +2829,16 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { if (translateKnownIntrinsic(CI, ID, MIRBuilder)) return true; - TargetLowering::IntrinsicInfo Info; - bool IsTgtMemIntrinsic = TLI->getTgtMemIntrinsic(Info, CI, *MF, ID); + SmallVector Infos; + TLI->getTgtMemIntrinsic(Infos, CI, *MF, ID); - return translateIntrinsic(CI, ID, MIRBuilder, - IsTgtMemIntrinsic ? &Info : nullptr); + return translateIntrinsic(CI, ID, MIRBuilder, Infos); } /// Translate a call or callbr to an intrinsic. -/// Depending on whether TLI->getTgtMemIntrinsic() is true, TgtMemIntrinsicInfo -/// is a pointer to the correspondingly populated IntrinsicInfo object. -/// Otherwise, this pointer is null. bool IRTranslator::translateIntrinsic( const CallBase &CB, Intrinsic::ID ID, MachineIRBuilder &MIRBuilder, - const TargetLowering::IntrinsicInfo *TgtMemIntrinsicInfo) { + ArrayRef TgtMemIntrinsicInfos) { ArrayRef ResultRegs; if (!CB.getType()->isVoidTy()) ResultRegs = getOrCreateVRegs(CB); @@ -2874,30 +2880,25 @@ bool IRTranslator::translateIntrinsic( } } - // Add a MachineMemOperand if it is a target mem intrinsic. - if (TgtMemIntrinsicInfo) { - const Function *F = CB.getCalledFunction(); + // Add MachineMemOperands for each memory access described by the target. + for (const auto &Info : TgtMemIntrinsicInfos) { + Align Alignment = Info.align.value_or( + DL->getABITypeAlign(Info.memVT.getTypeForEVT(CB.getContext()))); + LLT MemTy = Info.memVT.isSimple() + ? getLLTForMVT(Info.memVT.getSimpleVT()) + : LLT::scalar(Info.memVT.getStoreSizeInBits()); - Align Alignment = TgtMemIntrinsicInfo->align.value_or(DL->getABITypeAlign( - TgtMemIntrinsicInfo->memVT.getTypeForEVT(F->getContext()))); - LLT MemTy = - TgtMemIntrinsicInfo->memVT.isSimple() - ? getLLTForMVT(TgtMemIntrinsicInfo->memVT.getSimpleVT()) - : LLT::scalar(TgtMemIntrinsicInfo->memVT.getStoreSizeInBits()); - - // TODO: We currently just fallback to address space 0 if getTgtMemIntrinsic - // didn't yield anything useful. + // TODO: We currently just fallback to address space 0 if + // getTgtMemIntrinsic didn't yield anything useful. MachinePointerInfo MPI; - if (TgtMemIntrinsicInfo->ptrVal) { - MPI = MachinePointerInfo(TgtMemIntrinsicInfo->ptrVal, - TgtMemIntrinsicInfo->offset); - } else if (TgtMemIntrinsicInfo->fallbackAddressSpace) { - MPI = MachinePointerInfo(*TgtMemIntrinsicInfo->fallbackAddressSpace); + if (Info.ptrVal) { + MPI = MachinePointerInfo(Info.ptrVal, Info.offset); + } else if (Info.fallbackAddressSpace) { + MPI = MachinePointerInfo(*Info.fallbackAddressSpace); } MIB.addMemOperand(MF->getMachineMemOperand( - MPI, TgtMemIntrinsicInfo->flags, MemTy, Alignment, CB.getAAMetadata(), - /*Ranges=*/nullptr, TgtMemIntrinsicInfo->ssid, - TgtMemIntrinsicInfo->order, TgtMemIntrinsicInfo->failureOrder)); + MPI, Info.flags, MemTy, Alignment, CB.getAAMetadata(), + /*Ranges=*/nullptr, Info.ssid, Info.order, Info.failureOrder)); } if (CB.isConvergent()) { @@ -3197,11 +3198,20 @@ bool IRTranslator::translateAlloca(const User &U, } Type *Ty = AI.getAllocatedType(); + TypeSize TySize = DL->getTypeAllocSize(Ty); Register AllocSize = MRI->createGenericVirtualRegister(IntPtrTy); - Register TySize = - getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, DL->getTypeAllocSize(Ty))); - MIRBuilder.buildMul(AllocSize, NumElts, TySize); + Register TySizeReg; + if (TySize.isScalable()) { + // For scalable types, use vscale * min_value + TySizeReg = MRI->createGenericVirtualRegister(IntPtrTy); + MIRBuilder.buildVScale(TySizeReg, TySize.getKnownMinValue()); + } else { + // For fixed types, use a constant + TySizeReg = + getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, TySize.getFixedValue())); + } + MIRBuilder.buildMul(AllocSize, NumElts, TySizeReg); // Round the size of the allocation up to the stack alignment size // by add SA-1 to the size. This doesn't overflow because we're computing diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp index a1f3d6b53d949..6481d0e180352 100644 --- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp @@ -408,14 +408,23 @@ bool InlineAsmLowering::lowerInlineAsm( ArrayRef SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); assert(SrcRegs.size() == 1 && "Single register is expected here"); - // When Def is physreg: use given input. - Register In = SrcRegs[0]; - // When Def is vreg: copy input to new vreg with same reg class as Def. - if (Def.isVirtual()) { - In = MRI->createVirtualRegister(MRI->getRegClass(Def)); - if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder)) - return false; - } + // We need the tied input to live in the same register class as the def. + // + // - if Def is a vreg, we can just use its regclass. + // - if Def is a physreg, create a vreg in the minimal regclass for that + // physreg. + // + // Otherwise RegBankSelect may leave it in the wrong bank (e.g. GPR even + // though it's tied to an FP physreg). + const TargetRegisterClass *RC = Def.isVirtual() + ? MRI->getRegClass(Def) + : TRI->getMinimalPhysRegClass(Def); + + // Materialize `In` in a new vreg that has a register class that matches + // the register class of `Def`. + Register In = MRI->createVirtualRegister(RC); + if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder)) + return false; // Add Flag and input register operand (In) to Inst. Tie In to Def. InlineAsm::Flag UseFlag(InlineAsm::Kind::RegUse, 1); diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index ace08c2f77df8..e6eec3194b716 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -4762,6 +4762,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { return lowerFPTRUNC(MI); case G_FPOWI: return lowerFPOWI(MI); + case G_FMODF: + return lowerFMODF(MI); case G_SMIN: case G_SMAX: case G_UMIN: @@ -8719,6 +8721,35 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { return Legalized; } +LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMODF(MachineInstr &MI) { + auto [DstFrac, DstInt, Src] = MI.getFirst3Regs(); + LLT Ty = MRI.getType(Src); + auto Flags = MI.getFlags(); + + auto IntPart = MIRBuilder.buildIntrinsicTrunc(Ty, Src, Flags); + auto FracPart = MIRBuilder.buildFSub(Ty, Src, IntPart, Flags); + + Register FracToUse; + if (MI.getFlag(MachineInstr::FmNoInfs)) { + FracToUse = FracPart.getReg(0); + } else { + auto Abs = MIRBuilder.buildFAbs(Ty, Src, Flags); + const fltSemantics &Semantics = getFltSemanticForLLT(Ty.getScalarType()); + auto Inf = MIRBuilder.buildFConstant(Ty, APFloat::getInf(Semantics)); + auto IsInf = MIRBuilder.buildFCmp(CmpInst::FCMP_OEQ, + Ty.changeElementSize(1), Abs, Inf); + auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); + auto Select = MIRBuilder.buildSelect(Ty, IsInf, Zero, FracPart); + FracToUse = Select.getReg(0); + } + + MIRBuilder.buildFCopysign(DstFrac, FracToUse, Src, Flags); + MIRBuilder.buildCopy(DstInt, IntPart.getReg(0)); + + MI.eraseFromParent(); + return Legalized; +} + static CmpInst::Predicate minMaxToCompare(unsigned Opc) { switch (Opc) { case TargetOpcode::G_SMIN: diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index 5db631be32acd..4dfd5179a4e56 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -51,6 +51,12 @@ using namespace llvm; +/// Cost value representing an impossible or invalid repairing. +/// This matches the value returned by RegisterBankInfo::copyCost() and +/// RegisterBankInfo::getBreakDownCost() when the cost cannot be computed. +static constexpr unsigned ImpossibleRepairCost = + std::numeric_limits::max(); + static cl::opt RegBankSelectMode( cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional, cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast", @@ -278,12 +284,11 @@ uint64_t RegBankSelect::getRepairCost( // repairing placement. unsigned Cost = RBI->copyCost(*DesiredRegBank, *CurRegBank, RBI->getSizeInBits(MO.getReg(), *MRI, *TRI)); - // TODO: use a dedicated constant for ImpossibleCost. - if (Cost != std::numeric_limits::max()) + if (Cost != ImpossibleRepairCost) return Cost; // Return the legalization cost of that repairing. } - return std::numeric_limits::max(); + return ImpossibleRepairCost; } const RegisterBankInfo::InstructionMapping &RegBankSelect::findBestMapping( @@ -535,7 +540,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping( uint64_t RepairCost = getRepairCost(MO, ValMapping); // This is an impossible to repair cost. - if (RepairCost == std::numeric_limits::max()) + if (RepairCost == ImpossibleRepairCost) return MappingCost::ImpossibleCost(); // Bias used for splitting: 5%. diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index 658774ec3fcb9..e3ec021085a29 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -152,7 +152,7 @@ Register llvm::constrainOperandRegClass( RegMO); } -bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, +void llvm::constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) { @@ -195,7 +195,6 @@ bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, I.tieOperands(DefIdx, OpI); } } - return true; } bool llvm::canReplaceReg(Register DstReg, Register SrcReg, diff --git a/llvm/lib/CodeGen/GlobalMergeFunctions.cpp b/llvm/lib/CodeGen/GlobalMergeFunctions.cpp index 81ab317c15889..dee20d601359f 100644 --- a/llvm/lib/CodeGen/GlobalMergeFunctions.cpp +++ b/llvm/lib/CodeGen/GlobalMergeFunctions.cpp @@ -208,6 +208,10 @@ static Function *createMergedFunction(FuncMergeInfo &FI, if (auto *SP = MergedFunc->getSubprogram()) NewFunction->setSubprogram(SP); NewFunction->copyAttributesFrom(MergedFunc); + // Preserve entry count for the merged function. Branch weights for blocks + // are automatically preserved via splice() which moves the basic blocks. + if (auto EC = MergedFunc->getEntryCount()) + NewFunction->setEntryCount(*EC); NewFunction->setDLLStorageClass(GlobalValue::DefaultStorageClass); NewFunction->setLinkage(GlobalValue::InternalLinkage); @@ -254,6 +258,10 @@ static void createThunk(FuncMergeInfo &FI, ArrayRef Params, assert(Thunk->arg_size() + Params.size() == ToFunc->getFunctionType()->getNumParams()); + + // Save entry count before dropping references (which clears metadata). + auto EC = Thunk->getEntryCount(); + Thunk->dropAllReferences(); BasicBlock *BB = BasicBlock::Create(Thunk->getContext(), "", Thunk); @@ -289,6 +297,10 @@ static void createThunk(FuncMergeInfo &FI, ArrayRef Params, Builder.CreateRetVoid(); else Builder.CreateRet(Builder.CreateAggregateCast(CI, Thunk->getReturnType())); + + // Restore the thunk's original entry count. + if (EC) + Thunk->setEntryCount(*EC); } // Check if the old merged/optimized IndexOperandHashMap is compatible with @@ -571,7 +583,7 @@ class GlobalMergeFuncPassWrapper : public ModulePass { public: static char ID; - GlobalMergeFuncPassWrapper(); + GlobalMergeFuncPassWrapper() : ModulePass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addUsedIfAvailable(); @@ -594,11 +606,6 @@ ModulePass *llvm::createGlobalMergeFuncPass() { return new GlobalMergeFuncPassWrapper(); } -GlobalMergeFuncPassWrapper::GlobalMergeFuncPassWrapper() : ModulePass(ID) { - initializeGlobalMergeFuncPassWrapperPass( - *llvm::PassRegistry::getPassRegistry()); -} - bool GlobalMergeFuncPassWrapper::runOnModule(Module &M) { const ModuleSummaryIndex *Index = nullptr; if (auto *IndexWrapperPass = diff --git a/llvm/lib/CodeGen/InsertCodePrefetch.cpp b/llvm/lib/CodeGen/InsertCodePrefetch.cpp index 44864cbc99c52..d54e4408a0dcb 100644 --- a/llvm/lib/CodeGen/InsertCodePrefetch.cpp +++ b/llvm/lib/CodeGen/InsertCodePrefetch.cpp @@ -36,9 +36,7 @@ class InsertCodePrefetch : public MachineFunctionPass { public: static char ID; - InsertCodePrefetch() : MachineFunctionPass(ID) { - initializeInsertCodePrefetchPass(*PassRegistry::getPassRegistry()); - } + InsertCodePrefetch() : MachineFunctionPass(ID) {} StringRef getPassName() const override { return "Code Prefetch Inserter Pass"; diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index 6dda0fddbcec8..0164e04cdb9a6 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -444,9 +444,7 @@ class TransferTracker { if (!Op.IsConst) ActiveMLocs[Op.Loc].insert(VarID); auto NewValue = ResolvedDbgValue{ResolvedDbgOps, Value.Properties}; - auto Result = ActiveVLocs.insert(std::make_pair(VarID, NewValue)); - if (!Result.second) - Result.first->second = NewValue; + ActiveVLocs.insert_or_assign(VarID, std::move(NewValue)); } /// Load object with live-in variable values. \p mlocs contains the live-in diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 8d7694537e07d..fb35c7e62dad6 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -1119,8 +1119,8 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI) SubReg = Cpy.getOperand(1).getSubReg(); } else if (Cpy.isSubregToReg()) { OldReg = Cpy.getOperand(0).getReg(); - NewReg = Cpy.getOperand(2).getReg(); - SubReg = Cpy.getOperand(3).getImm(); + NewReg = Cpy.getOperand(1).getReg(); + SubReg = Cpy.getOperand(2).getImm(); } else { auto CopyDetails = *TII.isCopyInstr(Cpy); const MachineOperand &Src = *CopyDetails.Source; diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 945a10cd69842..43bb19bf4f181 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -291,10 +291,12 @@ class LoopCarriedOrderDepsTracker { InstrTag getTag() const { return InstrTag(getInt()); } }; - /// Holds loads and stores with memory related information. - struct LoadStoreChunk { + /// Holds instructions that may form loop-carried order-dependencies, but not + /// global barriers. + struct NoBarrierInstsChunk { SmallVector Loads; SmallVector Stores; + SmallVector FPExceptions; void append(SUnit *SU); }; @@ -341,8 +343,8 @@ class LoopCarriedOrderDepsTracker { /// Tags to \p SU if the instruction may affect the order-dependencies. std::optional getInstrTag(SUnit *SU) const; - void addLoopCarriedDepenenciesForChunks(const LoadStoreChunk &From, - const LoadStoreChunk &To); + void addLoopCarriedDepenenciesForChunks(const NoBarrierInstsChunk &From, + const NoBarrierInstsChunk &To); /// Add a loop-carried order dependency between \p Src and \p Dst if we /// cannot prove they are independent. @@ -350,6 +352,10 @@ class LoopCarriedOrderDepsTracker { const SUnitWithMemInfo &Dst); void computeDependenciesAux(); + + void setLoopCarriedDep(const SUnit *Src, const SUnit *Dst) { + LoopCarried[Src->NodeNum].set(Dst->NodeNum); + } }; } // end anonymous namespace @@ -1088,11 +1094,16 @@ static bool hasLoopCarriedMemDep(const SUnitWithMemInfo &Src, return false; } -void LoopCarriedOrderDepsTracker::LoadStoreChunk::append(SUnit *SU) { +void LoopCarriedOrderDepsTracker::NoBarrierInstsChunk::append(SUnit *SU) { const MachineInstr *MI = SU->getInstr(); - if (!MI->mayLoadOrStore()) - return; - (MI->mayStore() ? Stores : Loads).emplace_back(SU); + if (MI->mayStore()) + Stores.emplace_back(SU); + else if (MI->mayLoad()) + Loads.emplace_back(SU); + else if (MI->mayRaiseFPException()) + FPExceptions.emplace_back(SU); + else + llvm_unreachable("Unexpected instruction type."); } LoopCarriedOrderDepsTracker::LoopCarriedOrderDepsTracker( @@ -1138,11 +1149,11 @@ void LoopCarriedOrderDepsTracker::addDependenciesBetweenSUs( return; if (hasLoopCarriedMemDep(Src, Dst, *BAA, TII, TRI, DAG)) - LoopCarried[Src.SU->NodeNum].set(Dst.SU->NodeNum); + setLoopCarriedDep(Src.SU, Dst.SU); } void LoopCarriedOrderDepsTracker::addLoopCarriedDepenenciesForChunks( - const LoadStoreChunk &From, const LoadStoreChunk &To) { + const NoBarrierInstsChunk &From, const NoBarrierInstsChunk &To) { // Add load-to-store dependencies (WAR). for (const SUnitWithMemInfo &Src : From.Loads) for (const SUnitWithMemInfo &Dst : To.Stores) @@ -1160,19 +1171,22 @@ void LoopCarriedOrderDepsTracker::addLoopCarriedDepenenciesForChunks( } void LoopCarriedOrderDepsTracker::computeDependenciesAux() { - SmallVector Chunks(1); + SmallVector Chunks(1); + SUnit *FirstBarrier = nullptr; + SUnit *LastBarrier = nullptr; for (const auto &TSU : TaggedSUnits) { InstrTag Tag = TSU.getTag(); SUnit *SU = TSU.getPointer(); switch (Tag) { case InstrTag::Barrier: + if (!FirstBarrier) + FirstBarrier = SU; + LastBarrier = SU; Chunks.emplace_back(); break; case InstrTag::LoadOrStore: - Chunks.back().append(SU); - break; case InstrTag::FPExceptions: - // TODO: Handle this properly. + Chunks.back().append(SU); break; } } @@ -1180,12 +1194,58 @@ void LoopCarriedOrderDepsTracker::computeDependenciesAux() { // Add dependencies between memory operations. If there are one or more // barrier events between two memory instructions, we don't add a // loop-carried dependence for them. - for (const LoadStoreChunk &Chunk : Chunks) + for (const NoBarrierInstsChunk &Chunk : Chunks) addLoopCarriedDepenenciesForChunks(Chunk, Chunk); - // TODO: If there are multiple barrier instructions, dependencies from the - // last barrier instruction (or load/store below it) to the first barrier - // instruction (or load/store above it). + // There is no barrier instruction between load/store/fp-exception + // instructions in the same chunk. If there are one or more barrier + // instructions, the instructions sequence is as follows: + // + // Loads/Stores/FPExceptions (Chunks.front()) + // Barrier (FirstBarrier) + // Loads/Stores/FPExceptions + // Barrier + // ... + // Loads/Stores/FPExceptions + // Barrier (LastBarrier) + // Loads/Stores/FPExceptions (Chunks.back()) + // + // Since loads/stores/fp-exceptions must not be reordered across barrier + // instructions, and the order of barrier instructions must be preserved, add + // the following loop-carried dependences: + // + // Loads/Stores/FPExceptions (Chunks.front()) <-----+ + // +--> Barrier (FirstBarrier) <----------------------+ | + // | Loads/Stores/FPExceptions | | + // | Barrier | | + // | ... | | + // | Loads/Stores/FPExceptions | | + // | Barrier (LastBarrier) ------------------------+--+ + // +--- Loads/Stores/FPExceptions (Chunks.back()) + // + if (FirstBarrier) { + assert(LastBarrier && "Both barriers should be set."); + + // LastBarrier -> Loads/Stores/FPExceptions in Chunks.front() + for (const SUnitWithMemInfo &Dst : Chunks.front().Loads) + setLoopCarriedDep(LastBarrier, Dst.SU); + for (const SUnitWithMemInfo &Dst : Chunks.front().Stores) + setLoopCarriedDep(LastBarrier, Dst.SU); + for (const SUnitWithMemInfo &Dst : Chunks.front().FPExceptions) + setLoopCarriedDep(LastBarrier, Dst.SU); + + // Loads/Stores/FPExceptions in Chunks.back() -> FirstBarrier + for (const SUnitWithMemInfo &Src : Chunks.back().Loads) + setLoopCarriedDep(Src.SU, FirstBarrier); + for (const SUnitWithMemInfo &Src : Chunks.back().Stores) + setLoopCarriedDep(Src.SU, FirstBarrier); + for (const SUnitWithMemInfo &Src : Chunks.back().FPExceptions) + setLoopCarriedDep(Src.SU, FirstBarrier); + + // LastBarrier -> FirstBarrier (if they are different) + if (FirstBarrier != LastBarrier) + setLoopCarriedDep(LastBarrier, FirstBarrier); + } } /// Add a chain edge between a load and store if the store can be an @@ -3258,54 +3318,6 @@ bool SMSchedule::insert(SUnit *SU, int StartCycle, int EndCycle, int II) { return false; } -// Return the cycle of the earliest scheduled instruction in the chain. -int SMSchedule::earliestCycleInChain(const SwingSchedulerDDGEdge &Dep, - const SwingSchedulerDDG *DDG) { - SmallPtrSet Visited; - SmallVector Worklist; - Worklist.push_back(Dep); - int EarlyCycle = INT_MAX; - while (!Worklist.empty()) { - const SwingSchedulerDDGEdge &Cur = Worklist.pop_back_val(); - SUnit *PrevSU = Cur.getSrc(); - if (Visited.count(PrevSU)) - continue; - std::map::const_iterator it = InstrToCycle.find(PrevSU); - if (it == InstrToCycle.end()) - continue; - EarlyCycle = std::min(EarlyCycle, it->second); - for (const auto &IE : DDG->getInEdges(PrevSU)) - if (IE.isOrderDep() || IE.isOutputDep()) - Worklist.push_back(IE); - Visited.insert(PrevSU); - } - return EarlyCycle; -} - -// Return the cycle of the latest scheduled instruction in the chain. -int SMSchedule::latestCycleInChain(const SwingSchedulerDDGEdge &Dep, - const SwingSchedulerDDG *DDG) { - SmallPtrSet Visited; - SmallVector Worklist; - Worklist.push_back(Dep); - int LateCycle = INT_MIN; - while (!Worklist.empty()) { - const SwingSchedulerDDGEdge &Cur = Worklist.pop_back_val(); - SUnit *SuccSU = Cur.getDst(); - if (Visited.count(SuccSU) || SuccSU->isBoundaryNode()) - continue; - std::map::const_iterator it = InstrToCycle.find(SuccSU); - if (it == InstrToCycle.end()) - continue; - LateCycle = std::max(LateCycle, it->second); - for (const auto &OE : DDG->getOutEdges(SuccSU)) - if (OE.isOrderDep() || OE.isOutputDep()) - Worklist.push_back(OE); - Visited.insert(SuccSU); - } - return LateCycle; -} - /// If an instruction has a use that spans multiple iterations, then /// return true. These instructions are characterized by having a back-ege /// to a Phi, which contains a reference to another Phi. @@ -3331,12 +3343,6 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, for (SUnit *I : getInstructions(cycle)) { for (const auto &IE : DDG->getInEdges(SU)) { if (IE.getSrc() == I) { - // FIXME: Add reverse edge to `DDG` instead of calling - // `isLoopCarriedDep` - if (DAG->isLoopCarriedDep(IE)) { - int End = earliestCycleInChain(IE, DDG) + (II - 1); - *MinLateStart = std::min(*MinLateStart, End); - } int EarlyStart = cycle + IE.getLatency() - IE.getDistance() * II; *MaxEarlyStart = std::max(*MaxEarlyStart, EarlyStart); } @@ -3344,12 +3350,6 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, for (const auto &OE : DDG->getOutEdges(SU)) { if (OE.getDst() == I) { - // FIXME: Add reverse edge to `DDG` instead of calling - // `isLoopCarriedDep` - if (DAG->isLoopCarriedDep(OE)) { - int Start = latestCycleInChain(OE, DDG) + 1 - II; - *MaxEarlyStart = std::max(*MaxEarlyStart, Start); - } int LateStart = cycle - OE.getLatency() + OE.getDistance() * II; *MinLateStart = std::min(*MinLateStart, LateStart); } diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp index a28bdd3aefc4e..6cb59717c4997 100644 --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -833,14 +833,14 @@ bool PeepholeOptimizer::optimizeExtInstr( // // %reg1025 = %reg1024 // ... - // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4 + // %reg1026 = SUBREG_TO_REG %reg1024, 4 // // into this: // // %reg1025 = %reg1024 // ... // %reg1027 = COPY %reg1025:4 - // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4 + // %reg1026 = SUBREG_TO_REG %reg1027, 4 // // The problem here is that SUBREG_TO_REG is there to assert that an // implicit zext occurs. It doesn't insert a zext instruction. If we allow @@ -959,14 +959,7 @@ bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr &MI) { /// Optimize a select instruction. bool PeepholeOptimizer::optimizeSelect( MachineInstr &MI, SmallPtrSetImpl &LocalMIs) { - unsigned TrueOp = 0; - unsigned FalseOp = 0; - bool Optimizable = false; - SmallVector Cond; - if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable)) - return false; - if (!Optimizable) - return false; + assert(MI.isSelect() && "Should only be called when MI->isSelect() is true"); if (!TII->optimizeSelect(MI, LocalMIs)) return false; LLVM_DEBUG(dbgs() << "Deleting select: " << MI); @@ -2131,21 +2124,21 @@ ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() { ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() { assert(Def->isSubregToReg() && "Invalid definition"); // We are looking at: - // Def = SUBREG_TO_REG Imm, v0, sub0 + // Def = SUBREG_TO_REG v0, sub0 // Bail if we have to compose sub registers. // If DefSubReg != sub0, we would have to check that all the bits // we track are included in sub0 and if yes, we would have to // determine the right subreg in v0. - if (DefSubReg != Def->getOperand(3).getImm()) + if (DefSubReg != Def->getOperand(2).getImm()) return ValueTrackerResult(); // Bail if we have to compose sub registers. // Likewise, if v0.subreg != 0, we would have to compose it with sub0. - if (Def->getOperand(2).getSubReg()) + if (Def->getOperand(1).getSubReg()) return ValueTrackerResult(); - return ValueTrackerResult(Def->getOperand(2).getReg(), - Def->getOperand(3).getImm()); + return ValueTrackerResult(Def->getOperand(1).getReg(), + Def->getOperand(2).getImm()); } /// Explore each PHI incoming operand and return its sources. diff --git a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp index 490f014aaf220..a8f94afe8c023 100644 --- a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp +++ b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp @@ -28,6 +28,7 @@ #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Metadata.h" #include "llvm/IR/Module.h" +#include "llvm/IR/ProfDataUtils.h" #include "llvm/IR/RuntimeLibcalls.h" #include "llvm/IR/Type.h" #include "llvm/IR/Use.h" @@ -36,12 +37,15 @@ #include "llvm/Support/Casting.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/BuildLibCalls.h" #include "llvm/Transforms/Utils/LowerMemIntrinsics.h" #include "llvm/Transforms/Utils/LowerVectorIntrinsics.h" using namespace llvm; +#define DEBUG_TYPE "pre-isel-intrinsic-lowering" + /// Threshold to leave statically sized memory intrinsic calls. Calls of known /// size larger than this will be expanded by the pass. Calls of unknown or /// lower size will be left for expansion in codegen. @@ -381,7 +385,7 @@ bool PreISelIntrinsicLowering::expandMemIntrinsicUses( canEmitLibcall(ModuleLibcalls, TM, ParentFunc, RTLIB::MEMSET)) break; - expandMemSetAsLoop(Memset); + expandMemSetAsLoop(Memset, TTI); Changed = true; Memset->eraseFromParent(); } @@ -396,7 +400,9 @@ bool PreISelIntrinsicLowering::expandMemIntrinsicUses( if (isa(Memset->getLength())) break; - expandMemSetAsLoop(Memset); + Function *ParentFunc = Memset->getFunction(); + const TargetTransformInfo &TTI = LookupTTI(*ParentFunc); + expandMemSetAsLoop(Memset, TTI); Changed = true; Memset->eraseFromParent(); break; @@ -611,6 +617,20 @@ static bool expandProtectedFieldPtr(Function &Intr) { return true; } +static bool expandCondLoop(Function &Intr) { + for (User *U : llvm::make_early_inc_range(Intr.users())) { + auto *Call = cast(U); + + auto *Br = cast( + SplitBlockAndInsertIfThen(Call->getArgOperand(0), Call, false, + getExplicitlyUnknownBranchWeightsIfProfiled( + *Call->getFunction(), DEBUG_TYPE))); + Br->setSuccessor(0, Br->getParent()); + Call->eraseFromParent(); + } + return true; +} + bool PreISelIntrinsicLowering::lowerIntrinsics(Module &M) const { // Map unique constants to globals. DenseMap CMap; @@ -756,6 +776,10 @@ bool PreISelIntrinsicLowering::lowerIntrinsics(Module &M) const { case Intrinsic::protected_field_ptr: Changed |= expandProtectedFieldPtr(F); break; + case Intrinsic::cond_loop: + if (!TM->canLowerCondLoop()) + Changed |= expandCondLoop(F); + break; } } return Changed; diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 26149f8137cac..8565a7233d32c 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -107,12 +107,18 @@ static cl::opt ExhaustiveSearch( "and interference cutoffs of last chance recoloring"), cl::Hidden); +// This option should be deprecated! // FIXME: Find a good default for this flag and remove the flag. static cl::opt CSRFirstTimeCost("regalloc-csr-first-time-cost", cl::desc("Cost for first time use of callee-saved register."), cl::init(0), cl::Hidden); +static cl::opt CSRCostScale( + "regalloc-csr-cost-scale", + cl::desc("Scale for the callee-saved register cost, in percentage."), + cl::init(80), cl::Hidden); + static cl::opt GrowRegionComplexityBudget( "grow-region-complexity-budget", cl::desc("growRegion() does not scale with the number of BB edges, so " @@ -977,9 +983,9 @@ bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) { return true; } -/// calcSpillCost - Compute how expensive it would be to split the live range in -/// SA around all use blocks instead of forming bundle regions. -BlockFrequency RAGreedy::calcSpillCost() { +/// calcBlockSplitCost - Compute how expensive it would be to split the live +/// range in SA around all use blocks instead of forming bundle regions. +BlockFrequency RAGreedy::calcBlockSplitCost() { BlockFrequency Cost = BlockFrequency(0); ArrayRef UseBlocks = SA->getUseBlocks(); for (const SplitAnalysis::BlockInfo &BI : UseBlocks) { @@ -1197,7 +1203,7 @@ MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg, if (!TRI->shouldRegionSplitForVirtReg(*MF, VirtReg)) return MCRegister::NoRegister; unsigned NumCands = 0; - BlockFrequency SpillCost = calcSpillCost(); + BlockFrequency SpillCost = calcBlockSplitCost(); BlockFrequency BestCost; // Check if we can split this live range around a compact region. @@ -2339,6 +2345,30 @@ MCRegister RAGreedy::selectOrSplit(const LiveInterval &VirtReg, return Reg; } +/// calcSpillCost - Compute how expensive it would be to spill the live range in +/// LI into memory. +BlockFrequency RAGreedy::calcSpillCost(const LiveInterval &LI) { + uint64_t SpillCost = 0; + SmallPtrSet Visited; + + for (MachineRegisterInfo::reg_instr_nodbg_iterator + I = MRI->reg_instr_nodbg_begin(LI.reg()), + E = MRI->reg_instr_nodbg_end(); + I != E;) { + MachineInstr *MI = &*(I++); + if (MI->isMetaInstruction()) + continue; + if (!Visited.insert(MI).second) + continue; + + auto [Reads, Writes] = MI->readsWritesVirtualRegister(LI.reg()); + auto MBBFreq = SpillPlacer->getBlockFrequency(MI->getParent()->getNumber()); + SpillCost += (Reads + Writes) * MBBFreq.getFrequency(); + } + + return BlockFrequency(SpillCost); +} + /// Using a CSR for the first time has a cost because it causes push|pop /// to be added to prologue|epilogue. Splitting a cold section of the live /// range can have lower cost than using the CSR for the first time; @@ -2352,7 +2382,7 @@ MCRegister RAGreedy::tryAssignCSRFirstTime( // We choose spill over using the CSR for the first time if the spill cost // is lower than CSRCost. SA->analyze(&VirtReg); - if (calcSpillCost() >= CSRCost) + if (calcSpillCost(VirtReg) >= CSRCost) return PhysReg; // We are going to spill, set CostPerUseLimit to 1 to make sure that @@ -2385,31 +2415,43 @@ void RAGreedy::aboutToRemoveInterval(const LiveInterval &LI) { } void RAGreedy::initializeCSRCost() { - // We use the command-line option if it is explicitly set, otherwise use the - // larger one out of the command-line option and the value reported by TRI. - CSRCost = BlockFrequency( - CSRFirstTimeCost.getNumOccurrences() - ? CSRFirstTimeCost - : std::max((unsigned)CSRFirstTimeCost, TRI->getCSRFirstUseCost())); - if (!CSRCost.getFrequency()) - return; - - // Raw cost is relative to Entry == 2^14; scale it appropriately. - uint64_t ActualEntry = MBFI->getEntryFreq().getFrequency(); - if (!ActualEntry) { - CSRCost = BlockFrequency(0); - return; + if (!CSRCostScale.getNumOccurrences() && + (CSRFirstTimeCost.getNumOccurrences() || TRI->getCSRCost())) { + // We should deprecate the usage of CSRFirstTimeCost! + // We use the command-line option if it is explicitly set, otherwise use the + // larger one out of the command-line option and the value reported by TRI. + CSRCost = BlockFrequency( + CSRFirstTimeCost.getNumOccurrences() + ? CSRFirstTimeCost + : std::max((unsigned)CSRFirstTimeCost, TRI->getCSRCost())); + if (!CSRCost.getFrequency()) + return; + + // Raw cost is relative to Entry == 2^14; scale it appropriately. + uint64_t ActualEntry = MBFI->getEntryFreq().getFrequency(); + if (!ActualEntry) { + CSRCost = BlockFrequency(0); + return; + } + uint64_t FixedEntry = 1 << 14; + if (ActualEntry < FixedEntry) { + CSRCost *= BranchProbability(ActualEntry, FixedEntry); + } else if (ActualEntry <= UINT32_MAX) { + // Invert the fraction and divide. + CSRCost /= BranchProbability(FixedEntry, ActualEntry); + } else { + // Can't use BranchProbability in general, since it takes 32-bit numbers. + CSRCost = + BlockFrequency(CSRCost.getFrequency() * (ActualEntry / FixedEntry)); + } + } else { + uint64_t EntryFreq = MBFI->getEntryFreq().getFrequency(); + CSRCost = BlockFrequency(TRI->getCSRFirstUseCost() * EntryFreq); + if (CSRCostScale < 100) + CSRCost *= BranchProbability(CSRCostScale, 100); + else + CSRCost /= BranchProbability(100, CSRCostScale); } - uint64_t FixedEntry = 1 << 14; - if (ActualEntry < FixedEntry) - CSRCost *= BranchProbability(ActualEntry, FixedEntry); - else if (ActualEntry <= UINT32_MAX) - // Invert the fraction and divide. - CSRCost /= BranchProbability(FixedEntry, ActualEntry); - else - // Can't use BranchProbability in general, since it takes 32-bit numbers. - CSRCost = - BlockFrequency(CSRCost.getFrequency() * (ActualEntry / FixedEntry)); } /// Collect the hint info for \p Reg. diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h b/llvm/lib/CodeGen/RegAllocGreedy.h index 081ea368f505e..465be0d76809e 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.h +++ b/llvm/lib/CodeGen/RegAllocGreedy.h @@ -312,7 +312,7 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase, const LiveInterval *dequeue(PQueue &CurQueue); bool hasVirtRegAlloc(); - BlockFrequency calcSpillCost(); + BlockFrequency calcBlockSplitCost(); bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency &); bool addThroughConstraints(InterferenceCache::Cursor, ArrayRef); bool growRegion(GlobalSplitCandidate &Cand); @@ -360,6 +360,7 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase, AllocationOrder &Order, MCRegister PhysReg, uint8_t &CostPerUseLimit, SmallVectorImpl &NewVRegs); + BlockFrequency calcSpillCost(const LiveInterval &LI); void initializeCSRCost(); MCRegister tryBlockSplit(const LiveInterval &, AllocationOrder &, SmallVectorImpl &); diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 527ecca6eab47..586c27b7e3baf 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -430,9 +430,9 @@ INITIALIZE_PASS_END(RegisterCoalescerLegacy, "register-coalescer", } else if (MI->isSubregToReg()) { Dst = MI->getOperand(0).getReg(); DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), - MI->getOperand(3).getImm()); - Src = MI->getOperand(2).getReg(); - SrcSub = MI->getOperand(2).getSubReg(); + MI->getOperand(2).getImm()); + Src = MI->getOperand(1).getReg(); + SrcSub = MI->getOperand(1).getSubReg(); } else return false; return true; diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8d7d8a905abfc..b05157289892b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -662,9 +662,9 @@ namespace { bool InexpensiveOnly = false, std::optional OutVT = std::nullopt); SDValue BuildDivEstimate(SDValue N, SDValue Op, SDNodeFlags Flags); - SDValue buildRsqrtEstimate(SDValue Op); - SDValue buildSqrtEstimate(SDValue Op); - SDValue buildSqrtEstimateImpl(SDValue Op, bool Recip); + SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags); + SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags); + SDValue buildSqrtEstimateImpl(SDValue Op, bool Recip, SDNodeFlags Flags); SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations, bool Reciprocal); SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations, @@ -1208,7 +1208,7 @@ bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc, for (SDNode *Node : N->users()) { auto *LoadStore = dyn_cast(Node); - if (!LoadStore) + if (!LoadStore || !LoadStore->hasUniqueMemOperand()) return false; // Is x[offset2] a legal addressing mode? If so then @@ -5236,12 +5236,16 @@ SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) { EVT VT = N->getValueType(0); EVT CCVT = getSetCCResultType(VT); unsigned BitWidth = VT.getScalarSizeInBits(); + unsigned MaxLegalDivRemBitWidth = TLI.getMaxDivRemBitWidthSupported(); // fold (sdiv X, pow2) -> simple ops after legalize // FIXME: We check for the exact bit here because the generic lowering gives // better results in that case. The target-specific lowering should learn how - // to handle exact sdivs efficiently. - if (!N->getFlags().hasExact() && isDivisorPowerOfTwo(N1)) { + // to handle exact sdivs efficiently. An exception is made for large bitwidths + // exceeding what the target can natively support, as division expansion was + // skipped in favor of this optimization. + if ((!N->getFlags().hasExact() || BitWidth > MaxLegalDivRemBitWidth) && + isDivisorPowerOfTwo(N1)) { // Target-specific implementation of sdiv x, pow2. if (SDValue Res = BuildSDIVPow2(N)) return Res; @@ -6704,8 +6708,9 @@ static unsigned getMinMaxOpcodeForClamp(bool IsMin, SDValue Operand1, // FIXME: use FMINIMUMNUM if possible, such as for RISC-V. static unsigned getMinMaxOpcodeForCompareFold( - SDValue Operand1, SDValue Operand2, ISD::CondCode CC, unsigned OrAndOpcode, - SelectionDAG &DAG, bool isFMAXNUMFMINNUM_IEEE, bool isFMAXNUMFMINNUM) { + SDValue Operand1, SDValue Operand2, bool SetCCNoNaNs, ISD::CondCode CC, + unsigned OrAndOpcode, SelectionDAG &DAG, bool isFMAXNUMFMINNUM_IEEE, + bool isFMAXNUMFMINNUM) { // The optimization cannot be applied for all the predicates because // of the way FMINNUM/FMAXNUM and FMINNUM_IEEE/FMAXNUM_IEEE handle // NaNs. For FMINNUM_IEEE/FMAXNUM_IEEE, the optimization cannot be @@ -6715,7 +6720,7 @@ static unsigned getMinMaxOpcodeForCompareFold( // are non NaN values. if (((CC == ISD::SETLT || CC == ISD::SETLE) && (OrAndOpcode == ISD::OR)) || ((CC == ISD::SETGT || CC == ISD::SETGE) && (OrAndOpcode == ISD::AND))) { - return arebothOperandsNotNan(Operand1, Operand2, DAG) && + return (SetCCNoNaNs || arebothOperandsNotNan(Operand1, Operand2, DAG)) && isFMAXNUMFMINNUM_IEEE ? ISD::FMINNUM_IEEE : ISD::DELETED_NODE; @@ -6723,7 +6728,7 @@ static unsigned getMinMaxOpcodeForCompareFold( if (((CC == ISD::SETGT || CC == ISD::SETGE) && (OrAndOpcode == ISD::OR)) || ((CC == ISD::SETLT || CC == ISD::SETLE) && (OrAndOpcode == ISD::AND))) { - return arebothOperandsNotNan(Operand1, Operand2, DAG) && + return (SetCCNoNaNs || arebothOperandsNotNan(Operand1, Operand2, DAG)) && isFMAXNUMFMINNUM_IEEE ? ISD::FMAXNUM_IEEE : ISD::DELETED_NODE; @@ -6772,6 +6777,8 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) { !LHS->hasOneUse() || !RHS->hasOneUse()) return SDValue(); + SDNodeFlags LHSSetCCFlags = LHS->getFlags(); + SDNodeFlags RHSSetCCFlags = RHS->getFlags(); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); AndOrSETCCFoldKind TargetPreference = TLI.isDesirableToCombineLogicOpOfSETCC( LogicOp, LHS.getNode(), RHS.getNode()); @@ -6864,13 +6871,17 @@ static SDValue foldAndOrOfSETCC(SDNode *LogicOp, SelectionDAG &DAG) { NewOpcode = IsSigned ? ISD::SMAX : ISD::UMAX; } else if (OpVT.isFloatingPoint()) NewOpcode = getMinMaxOpcodeForCompareFold( - Operand1, Operand2, CC, LogicOp->getOpcode(), DAG, - isFMAXNUMFMINNUM_IEEE, isFMAXNUMFMINNUM); + Operand1, Operand2, + LHSSetCCFlags.hasNoNaNs() && RHSSetCCFlags.hasNoNaNs(), CC, + LogicOp->getOpcode(), DAG, isFMAXNUMFMINNUM_IEEE, isFMAXNUMFMINNUM); if (NewOpcode != ISD::DELETED_NODE) { + // Propagate fast-math flags from setcc. + SDNodeFlags Flags = LHS->getFlags() & RHS->getFlags(); SDValue MinMaxValue = - DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2); - return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC); + DAG.getNode(NewOpcode, DL, OpVT, Operand1, Operand2, Flags); + return DAG.getSetCC(DL, VT, MinMaxValue, CommonValue, CC, /*Chain=*/{}, + /*IsSignaling=*/false, Flags); } } } @@ -11742,10 +11753,29 @@ SDValue DAGCombiner::foldABSToABD(SDNode *N, const SDLoc &DL) { EVT VT = N->getValueType(0); SDValue Op0, Op1; - if (!sd_match(N, m_Abs(m_Sub(m_Value(Op0), m_Value(Op1))))) + if (!sd_match(N, m_Abs(m_AnyOf(m_Sub(m_Value(Op0), m_Value(Op1)), + m_Add(m_Value(Op0), m_Value(Op1)))))) return SDValue(); SDValue AbsOp0 = N->getOperand(0); + bool IsAdd = AbsOp0.getOpcode() == ISD::ADD; + // Make sure (neg B) is positive. + if (IsAdd) { + // Elements of Op1 must be constant and != VT.minSignedValue() (or undef) + std::function IsNotMinSignedInt = + [VT](ConstantSDNode *C) { + if (C == nullptr) + return true; + return !C->getAPIntValue() + .trunc(VT.getScalarSizeInBits()) + .isMinSignedValue(); + }; + + if (!ISD::matchUnaryPredicate(Op1, IsNotMinSignedInt, /*AllowUndefs=*/true, + /*AllowTruncation=*/true)) + return SDValue(); + } + unsigned Opc0 = Op0.getOpcode(); // Check if the operands of the sub are (zero|sign)-extended, otherwise @@ -11754,22 +11784,36 @@ SDValue DAGCombiner::foldABSToABD(SDNode *N, const SDLoc &DL) { (Opc0 != ISD::ZERO_EXTEND && Opc0 != ISD::SIGN_EXTEND && Opc0 != ISD::SIGN_EXTEND_INREG)) { // fold (abs (sub nsw x, y)) -> abds(x, y) + // fold (abs (add nsw x, -y)) -> abds(x, y) + bool AbsOpWillNSW = + AbsOp0->getFlags().hasNoSignedWrap() || + (IsAdd ? DAG.willNotOverflowAdd(/*IsSigned=*/true, Op0, Op1) + : DAG.willNotOverflowSub(/*IsSigned=*/true, Op0, Op1)); + // Don't fold this for unsupported types as we lose the NSW handling. if (hasOperation(ISD::ABDS, VT) && TLI.preferABDSToABSWithNSW(VT) && - (AbsOp0->getFlags().hasNoSignedWrap() || - DAG.willNotOverflowSub(/*IsSigned=*/true, Op0, Op1))) { + AbsOpWillNSW) { + if (IsAdd) + Op1 = DAG.getNegative(Op1, SDLoc(Op1), VT); SDValue ABD = DAG.getNode(ISD::ABDS, DL, VT, Op0, Op1); return DAG.getZExtOrTrunc(ABD, DL, SrcVT); } // fold (abs (sub x, y)) -> abdu(x, y) if (hasOperation(ISD::ABDU, VT) && DAG.SignBitIsZero(Op0) && DAG.SignBitIsZero(Op1)) { + if (IsAdd) + Op1 = DAG.getNegative(Op1, SDLoc(Op1), VT); SDValue ABD = DAG.getNode(ISD::ABDU, DL, VT, Op0, Op1); return DAG.getZExtOrTrunc(ABD, DL, SrcVT); } return SDValue(); } + // The IsAdd case explicitly checks for const/bv-of-const. This implies either + // (Opc0 != Op1.getOpcode() || Opc0 is not in {zext/sext/sign_ext_inreg}. This + // implies it was alrady handled by the above if statement. + assert(!IsAdd && "Unexpected abs(add(x,y)) pattern"); + EVT VT0, VT1; if (Opc0 == ISD::SIGN_EXTEND_INREG) { VT0 = cast(Op0.getOperand(1))->getVT(); @@ -14596,27 +14640,39 @@ static SDValue tryToFoldExtOfExtload(SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType) { - SDNode *N0Node = N0.getNode(); - bool isAExtLoad = (ExtLoadType == ISD::SEXTLOAD) ? ISD::isSEXTLoad(N0Node) - : ISD::isZEXTLoad(N0Node); - if ((!isAExtLoad && !ISD::isEXTLoad(N0Node)) || - !ISD::isUNINDEXEDLoad(N0Node) || !N0.hasOneUse()) + bool Frozen = N0.getOpcode() == ISD::FREEZE; + auto *OldExtLoad = dyn_cast(Frozen ? N0.getOperand(0) : N0); + if (!OldExtLoad) return SDValue(); - LoadSDNode *LN0 = cast(N0); - EVT MemVT = LN0->getMemoryVT(); - if ((LegalOperations || !LN0->isSimple() || - VT.isVector()) && + bool isAExtLoad = (ExtLoadType == ISD::SEXTLOAD) + ? ISD::isSEXTLoad(OldExtLoad) + : ISD::isZEXTLoad(OldExtLoad); + if ((!isAExtLoad && !ISD::isEXTLoad(OldExtLoad)) || + !ISD::isUNINDEXEDLoad(OldExtLoad) || !OldExtLoad->hasNUsesOfValue(1, 0)) + return SDValue(); + + EVT MemVT = OldExtLoad->getMemoryVT(); + if ((LegalOperations || !OldExtLoad->isSimple() || VT.isVector()) && !TLI.isLoadExtLegal(ExtLoadType, VT, MemVT)) return SDValue(); - SDValue ExtLoad = - DAG.getExtLoad(ExtLoadType, SDLoc(LN0), VT, LN0->getChain(), - LN0->getBasePtr(), MemVT, LN0->getMemOperand()); - Combiner.CombineTo(N, ExtLoad); - DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1)); - if (LN0->use_empty()) - Combiner.recursivelyDeleteUnusedNodes(LN0); + SDLoc DL(OldExtLoad); + SDValue ExtLoad = DAG.getExtLoad(ExtLoadType, DL, VT, OldExtLoad->getChain(), + OldExtLoad->getBasePtr(), MemVT, + OldExtLoad->getMemOperand()); + SDValue Res = ExtLoad; + if (Frozen) { + Res = DAG.getFreeze(ExtLoad); + Res = DAG.getNode( + ExtLoadType == ISD::SEXTLOAD ? ISD::AssertSext : ISD::AssertZext, DL, + Res.getValueType(), Res, + DAG.getValueType(OldExtLoad->getValueType(0).getScalarType())); + } + Combiner.CombineTo(N, Res); + DAG.ReplaceAllUsesOfValueWith(SDValue(OldExtLoad, 1), ExtLoad.getValue(1)); + if (N0->use_empty()) + Combiner.recursivelyDeleteUnusedNodes(N0.getNode()); return SDValue(N, 0); // Return N so it doesn't get rechecked! } @@ -14809,7 +14865,7 @@ SDValue DAGCombiner::foldSextSetcc(SDNode *N) { SDLoc DL(N); // Propagate fast-math-flags. - SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags()); + SDNodeFlags Flags = N0->getFlags(); // On some architectures (such as SSE/NEON/etc) the SETCC result type is // the same size as the compared operands. Try to optimize sext(setcc()) @@ -14827,14 +14883,16 @@ SDValue DAGCombiner::foldSextSetcc(SDNode *N) { // we know that the element size of the sext'd result matches the // element size of the compare operands. if (VT.getSizeInBits() == SVT.getSizeInBits()) - return DAG.getSetCC(DL, VT, N00, N01, CC); + return DAG.getSetCC(DL, VT, N00, N01, CC, /*Chain=*/{}, + /*Signaling=*/false, Flags); // If the desired elements are smaller or larger than the source // elements, we can use a matching integer vector type and then // truncate/sign extend. EVT MatchingVecType = N00VT.changeVectorElementTypeToInteger(); if (SVT == MatchingVecType) { - SDValue VsetCC = DAG.getSetCC(DL, MatchingVecType, N00, N01, CC); + SDValue VsetCC = DAG.getSetCC(DL, MatchingVecType, N00, N01, CC, + /*Chain=*/{}, /*Signaling=*/false, Flags); return DAG.getSExtOrTrunc(VsetCC, DL, VT); } } @@ -14880,7 +14938,8 @@ SDValue DAGCombiner::foldSextSetcc(SDNode *N) { if (IsFreeToExtend(N00) && IsFreeToExtend(N01)) { SDValue Ext0 = DAG.getNode(ExtOpcode, DL, VT, N00); SDValue Ext1 = DAG.getNode(ExtOpcode, DL, VT, N01); - return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); + return DAG.getSetCC(DL, VT, Ext0, Ext1, CC, /*Chain=*/{}, + /*Signaling=*/false, Flags); } } } @@ -14912,8 +14971,9 @@ SDValue DAGCombiner::foldSextSetcc(SDNode *N) { // because a sext is likely cheaper than a select? if (SetCCVT.getScalarSizeInBits() != 1 && (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, N00VT))) { - SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC); - return DAG.getSelect(DL, VT, SetCC, ExtTrueVal, Zero); + SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC, /*Chain=*/{}, + /*Signaling=*/false, Flags); + return DAG.getSelect(DL, VT, SetCC, ExtTrueVal, Zero, Flags); } } @@ -15652,7 +15712,8 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { if (N0.getOpcode() == ISD::SETCC) { // Propagate fast-math-flags. - SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags()); + SDNodeFlags Flags = N0->getFlags(); + SelectionDAG::FlagInserter FlagsInserter(DAG, Flags); // For vectors: // aext(setcc) -> vsetcc @@ -15671,7 +15732,8 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { // element size of the compare operands. if (VT.getSizeInBits() == N00VT.getSizeInBits()) return DAG.getSetCC(DL, VT, N0.getOperand(0), N0.getOperand(1), - cast(N0.getOperand(2))->get()); + cast(N0.getOperand(2))->get(), + /*Chain=*/{}, /*Signaling=*/false, Flags); // If the desired elements are smaller or larger than the source // elements we can use a matching integer vector type and then @@ -15679,7 +15741,8 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { EVT MatchingVectorType = N00VT.changeVectorElementTypeToInteger(); SDValue VsetCC = DAG.getSetCC( DL, MatchingVectorType, N0.getOperand(0), N0.getOperand(1), - cast(N0.getOperand(2))->get()); + cast(N0.getOperand(2))->get(), /*Chain=*/{}, + /*Signaling=*/false, Flags); return DAG.getAnyExtOrTrunc(VsetCC, DL, VT); } @@ -18959,19 +19022,21 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) { // into a target-specific square root estimate instruction. bool N1AllowReciprocal = N1->getFlags().hasAllowReciprocal(); if (N1.getOpcode() == ISD::FSQRT) { - if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0))) + if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0), N1->getFlags())) return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); } else if (N1.getOpcode() == ISD::FP_EXTEND && N1.getOperand(0).getOpcode() == ISD::FSQRT && N1AllowReciprocal) { - if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0).getOperand(0))) { + if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0).getOperand(0), + N1.getOperand(0)->getFlags())) { RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV); AddToWorklist(RV.getNode()); return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); } } else if (N1.getOpcode() == ISD::FP_ROUND && N1.getOperand(0).getOpcode() == ISD::FSQRT) { - if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0).getOperand(0))) { + if (SDValue RV = buildRsqrtEstimate(N1.getOperand(0).getOperand(0), + N1.getOperand(0)->getFlags())) { RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1)); AddToWorklist(RV.getNode()); return DAG.getNode(ISD::FMUL, DL, VT, N0, RV); @@ -19003,7 +19068,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) { SDValue AA = DAG.getNode(ISD::FMUL, DL, VT, A, A); SDValue AAZ = DAG.getNode(ISD::FMUL, DL, VT, AA, Sqrt.getOperand(0)); - if (SDValue Rsqrt = buildRsqrtEstimate(AAZ)) + if (SDValue Rsqrt = buildRsqrtEstimate(AAZ, Sqrt->getFlags())) return DAG.getNode(ISD::FMUL, DL, VT, N0, Rsqrt); // Estimate creation failed. Clean up speculatively created nodes. @@ -19013,7 +19078,8 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) { // We found a FSQRT, so try to make this fold: // X / (Y * sqrt(Z)) -> X * (rsqrt(Z) / Y) - if (SDValue Rsqrt = buildRsqrtEstimate(Sqrt.getOperand(0))) { + if (SDValue Rsqrt = + buildRsqrtEstimate(Sqrt.getOperand(0), Sqrt->getFlags())) { SDValue Div = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, Rsqrt, Y); AddToWorklist(Div.getNode()); return DAG.getNode(ISD::FMUL, DL, VT, N0, Div); @@ -19116,7 +19182,7 @@ SDValue DAGCombiner::visitFSQRT(SDNode *N) { // transform the fdiv, we may produce a sub-optimal estimate sequence // because the reciprocal calculation may not have to filter out a // 0.0 input. - return buildSqrtEstimate(N0); + return buildSqrtEstimate(N0, Flags); } /// copysign(x, fp_extend(y)) -> copysign(x, y) @@ -30380,7 +30446,8 @@ SDValue DAGCombiner::buildSqrtNRTwoConst(SDValue Arg, SDValue Est, /// Build code to calculate either rsqrt(Op) or sqrt(Op). In the latter case /// Op*rsqrt(Op) is actually computed, so additional postprocessing is needed if /// Op can be zero. -SDValue DAGCombiner::buildSqrtEstimateImpl(SDValue Op, bool Reciprocal) { +SDValue DAGCombiner::buildSqrtEstimateImpl(SDValue Op, bool Reciprocal, + SDNodeFlags Flags) { if (LegalDAG) return SDValue(); @@ -30413,7 +30480,8 @@ SDValue DAGCombiner::buildSqrtEstimateImpl(SDValue Op, bool Reciprocal) { if (!Reciprocal) { SDLoc DL(Op); // Try the target specific test first. - SDValue Test = TLI.getSqrtInputTest(Op, DAG, DAG.getDenormalMode(VT)); + SDValue Test = + TLI.getSqrtInputTest(Op, DAG, DAG.getDenormalMode(VT), Flags); // The estimate is now completely wrong if the input was exactly 0.0 or // possibly a denormal. Force the answer to 0.0 or value provided by @@ -30427,12 +30495,12 @@ SDValue DAGCombiner::buildSqrtEstimateImpl(SDValue Op, bool Reciprocal) { return SDValue(); } -SDValue DAGCombiner::buildRsqrtEstimate(SDValue Op) { - return buildSqrtEstimateImpl(Op, true); +SDValue DAGCombiner::buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags) { + return buildSqrtEstimateImpl(Op, true, Flags); } -SDValue DAGCombiner::buildSqrtEstimate(SDValue Op) { - return buildSqrtEstimateImpl(Op, false); +SDValue DAGCombiner::buildSqrtEstimate(SDValue Op, SDNodeFlags Flags) { + return buildSqrtEstimateImpl(Op, false, Flags); } /// Return true if there is any possibility that the two addresses overlap. diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index bb203f6367b5b..a404dcc2660be 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -574,10 +574,17 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap, } } else if (Opc == TargetOpcode::INSERT_SUBREG || Opc == TargetOpcode::SUBREG_TO_REG) { - SDValue N0 = Node->getOperand(0); - SDValue N1 = Node->getOperand(1); - SDValue N2 = Node->getOperand(2); - unsigned SubIdx = N2->getAsZExtVal(); + SDValue Reg; + SDValue SubReg; + unsigned SubIdx; + if (Opc == TargetOpcode::INSERT_SUBREG) { + Reg = Node->getOperand(0); + SubReg = Node->getOperand(1); + SubIdx = Node->getOperand(2)->getAsZExtVal(); + } else { + SubReg = Node->getOperand(0); + SubIdx = Node->getOperand(1)->getAsZExtVal(); + } // Figure out the register class to create for the destreg. It should be // the largest legal register class supporting SubIdx sub-registers. @@ -605,17 +612,15 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap, MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); - // If creating a subreg_to_reg, then the first input operand - // is an implicit value immediate, otherwise it's a register - if (Opc == TargetOpcode::SUBREG_TO_REG) { - const ConstantSDNode *SD = cast(N0); - MIB.addImm(SD->getZExtValue()); - } else - AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false, - IsClone, IsCloned); + // If creating an insert_subreg, then the first input operand + // is a register + if (Reg) { + AddOperand(MIB, Reg, 0, nullptr, VRBaseMap, /*IsDebug=*/false, IsClone, + IsCloned); + } // Add the subregister being inserted - AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false, - IsClone, IsCloned); + AddOperand(MIB, SubReg, 0, nullptr, VRBaseMap, /*IsDebug=*/false, IsClone, + IsCloned); MIB.addImm(SubIdx); MBB->insert(InsertPos, MIB); } else @@ -1115,6 +1120,9 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, if (Flags.hasSameSign()) MI->setFlag(MachineInstr::MIFlag::SameSign); + + if (Flags.hasNoConvergent()) + MI->setFlag(MachineInstr::MIFlag::NoConvergent); } // Emit all of the actual operands of this instruction, adding them to the diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index d9a2409b35e4c..9ab0c9d475e94 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -184,6 +184,7 @@ class SelectionDAGLegalize { SDValue ExpandFNEG(SDNode *Node) const; SDValue expandLdexp(SDNode *Node) const; SDValue expandFrexp(SDNode *Node) const; + SDValue expandModf(SDNode *Node) const; SDValue ExpandLegalINT_TO_FP(SDNode *Node, SDValue &Chain); void PromoteLegalINT_TO_FP(SDNode *N, const SDLoc &dl, @@ -2771,6 +2772,34 @@ SDValue SelectionDAGLegalize::expandFrexp(SDNode *Node) const { return DAG.getMergeValues({Result0, Result1}, dl); } +SDValue SelectionDAGLegalize::expandModf(SDNode *Node) const { + SDLoc dl(Node); + SDValue Val = Node->getOperand(0); + EVT VT = Val.getValueType(); + SDNodeFlags Flags = Node->getFlags(); + + SDValue IntPart = DAG.getNode(ISD::FTRUNC, dl, VT, Val, Flags); + SDValue FracPart = DAG.getNode(ISD::FSUB, dl, VT, Val, IntPart, Flags); + + SDValue FracToUse; + if (Flags.hasNoInfs()) { + FracToUse = FracPart; + } else { + SDValue Abs = DAG.getNode(ISD::FABS, dl, VT, Val, Flags); + SDValue Inf = + DAG.getConstantFP(APFloat::getInf(VT.getFltSemantics()), dl, VT); + EVT SetCCVT = + TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); + SDValue IsInf = DAG.getSetCC(dl, SetCCVT, Abs, Inf, ISD::SETOEQ); + SDValue Zero = DAG.getConstantFP(0.0, dl, VT); + FracToUse = DAG.getSelect(dl, VT, IsInf, Zero, FracPart); + } + + SDValue ResultFrac = + DAG.getNode(ISD::FCOPYSIGN, dl, VT, FracToUse, Val, Flags); + return DAG.getMergeValues({ResultFrac, IntPart}, dl); +} + /// This function is responsible for legalizing a /// INT_TO_FP operation of the specified operand when the target requests that /// we expand it. At this point, we know that the result and operand types are @@ -3920,6 +3949,19 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { } break; } + case ISD::FMODF: { + RTLIB::Libcall LC = RTLIB::getMODF(Node->getValueType(0)); + // Use the LibCall instead, it is very likely faster + // FIXME: Use separate LibCall action. + if (DAG.getLibcalls().getLibcallImpl(LC) != RTLIB::Unsupported) + break; + + if (SDValue Expanded = expandModf(Node)) { + Results.push_back(Expanded); + Results.push_back(Expanded.getValue(1)); + } + break; + } case ISD::FSINCOS: { if (isSinCosLibcallAvailable(Node, DAG.getLibcalls())) break; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 5b32c5f945a75..4d08a22f25ab9 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -738,18 +738,15 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { // Subtract off the extra leading bits in the bigger type. SDValue ExtractLeadingBits = DAG.getConstant( NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl, NVT); + // Zero extend to the promoted type and do the count there. + SDValue Op = ZExtPromotedInteger(N->getOperand(0)); - if (!N->isVPOpcode()) { - // Zero extend to the promoted type and do the count there. - SDValue Op = ZExtPromotedInteger(N->getOperand(0)); + if (!N->isVPOpcode()) return DAG.getNode(ISD::SUB, dl, NVT, DAG.getNode(N->getOpcode(), dl, NVT, Op), ExtractLeadingBits); - } SDValue Mask = N->getOperand(1); SDValue EVL = N->getOperand(2); - // Zero extend to the promoted type and do the count there. - SDValue Op = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL); return DAG.getNode(ISD::VP_SUB, dl, NVT, DAG.getNode(N->getOpcode(), dl, NVT, Op, Mask, EVL), ExtractLeadingBits, Mask, EVL); @@ -806,14 +803,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) { } // Zero extend to the promoted type and do the count or parity there. - if (!N->isVPOpcode()) { - SDValue Op = ZExtPromotedInteger(N->getOperand(0)); + SDValue Op = ZExtPromotedInteger(N->getOperand(0)); + if (!N->isVPOpcode()) return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op); - } SDValue Mask = N->getOperand(1); SDValue EVL = N->getOperand(2); - SDValue Op = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL); return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op, Mask, EVL); } @@ -1483,17 +1478,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FFREXP(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { SDValue LHS = GetPromotedInteger(N->getOperand(0)); SDValue RHS = N->getOperand(1); - if (N->getOpcode() != ISD::VP_SHL) { - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) - RHS = ZExtPromotedInteger(RHS); - + if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) + RHS = ZExtPromotedInteger(RHS); + if (N->getOpcode() != ISD::VP_SHL) return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS); - } SDValue Mask = N->getOperand(2); SDValue EVL = N->getOperand(3); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) - RHS = VPZExtPromotedInteger(RHS, Mask, EVL); return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS, Mask, EVL); } @@ -1519,37 +1510,30 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) { - if (N->getNumOperands() == 2) { - // Sign extend the input. - SDValue LHS = SExtPromotedInteger(N->getOperand(0)); - SDValue RHS = SExtPromotedInteger(N->getOperand(1)); + // Sign extend the input. + SDValue LHS = SExtPromotedInteger(N->getOperand(0)); + SDValue RHS = SExtPromotedInteger(N->getOperand(1)); + if (N->getNumOperands() == 2) return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS); - } assert(N->getNumOperands() == 4 && "Unexpected number of operands!"); assert(N->isVPOpcode() && "Expected VP opcode"); SDValue Mask = N->getOperand(2); SDValue EVL = N->getOperand(3); - // Sign extend the input. - SDValue LHS = VPSExtPromotedInteger(N->getOperand(0), Mask, EVL); - SDValue RHS = VPSExtPromotedInteger(N->getOperand(1), Mask, EVL); return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS, Mask, EVL); } SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) { - if (N->getNumOperands() == 2) { - // Zero extend the input. - SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); - SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); + // Zero extend the input. + SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); + SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); + if (N->getNumOperands() == 2) return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS); - } assert(N->getNumOperands() == 4 && "Unexpected number of operands!"); assert(N->isVPOpcode() && "Expected VP opcode"); // Zero extend the input. SDValue Mask = N->getOperand(2); SDValue EVL = N->getOperand(3); - SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL); - SDValue RHS = VPZExtPromotedInteger(N->getOperand(1), Mask, EVL); return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS, Mask, EVL); } @@ -1567,41 +1551,31 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { + // The input value must be properly sign extended. + SDValue LHS = SExtPromotedInteger(N->getOperand(0)); SDValue RHS = N->getOperand(1); - if (N->getOpcode() != ISD::VP_SRA) { - // The input value must be properly sign extended. - SDValue LHS = SExtPromotedInteger(N->getOperand(0)); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) - RHS = ZExtPromotedInteger(RHS); + if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) + RHS = ZExtPromotedInteger(RHS); + if (N->getOpcode() != ISD::VP_SRA) return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS); - } SDValue Mask = N->getOperand(2); SDValue EVL = N->getOperand(3); - // The input value must be properly sign extended. - SDValue LHS = VPSExtPromotedInteger(N->getOperand(0), Mask, EVL); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) - RHS = VPZExtPromotedInteger(RHS, Mask, EVL); return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS, Mask, EVL); } SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { SDValue RHS = N->getOperand(1); - if (N->getOpcode() != ISD::VP_SRL) { - // The input value must be properly zero extended. - SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) - RHS = ZExtPromotedInteger(RHS); + // The input value must be properly zero extended. + SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); + if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) + RHS = ZExtPromotedInteger(RHS); + if (N->getOpcode() != ISD::VP_SRL) return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS); - } SDValue Mask = N->getOperand(2); SDValue EVL = N->getOperand(3); - // The input value must be properly zero extended. - SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL); - if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger) - RHS = VPZExtPromotedInteger(RHS, Mask, EVL); return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS, Mask, EVL); } @@ -1671,7 +1645,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VPFunnelShift(SDNode *N) { SDValue Mask = N->getOperand(3); SDValue EVL = N->getOperand(4); if (getTypeAction(Amt.getValueType()) == TargetLowering::TypePromoteInteger) - Amt = VPZExtPromotedInteger(Amt, Mask, EVL); + Amt = ZExtPromotedInteger(Amt); EVT AmtVT = Amt.getValueType(); SDLoc DL(N); @@ -2056,6 +2030,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; + case ISD::COND_LOOP: + Res = PromoteIntOp_COND_LOOP(N, OpNo); + break; case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; case ISD::FAKE_USE: Res = PromoteIntOp_FAKE_USE(N); @@ -2369,6 +2346,16 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { N->getOperand(2)), 0); } +SDValue DAGTypeLegalizer::PromoteIntOp_COND_LOOP(SDNode *N, unsigned OpNo) { + assert(OpNo == 1 && "only know how to promote condition"); + + // Promote all the way up to the canonical SetCC type. + SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other); + + // The chain (Op#0) is always a legal type. + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond), 0); +} + SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { // Since the result type is legal, the operands must promote to it. EVT OVT = N->getOperand(0).getValueType(); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index f10b6dfa902ec..1201949cfb366 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -273,27 +273,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer { return DAG.getZeroExtendInReg(Op, dl, OldVT); } - /// Get a promoted operand and zero extend it to the final size. - SDValue VPSExtPromotedInteger(SDValue Op, SDValue Mask, SDValue EVL) { - EVT OldVT = Op.getValueType(); - SDLoc dl(Op); - Op = GetPromotedInteger(Op); - // FIXME: Add VP_SIGN_EXTEND_INREG. - EVT VT = Op.getValueType(); - unsigned BitsDiff = VT.getScalarSizeInBits() - OldVT.getScalarSizeInBits(); - SDValue ShiftCst = DAG.getShiftAmountConstant(BitsDiff, VT, dl); - SDValue Shl = DAG.getNode(ISD::VP_SHL, dl, VT, Op, ShiftCst, Mask, EVL); - return DAG.getNode(ISD::VP_SRA, dl, VT, Shl, ShiftCst, Mask, EVL); - } - - /// Get a promoted operand and zero extend it to the final size. - SDValue VPZExtPromotedInteger(SDValue Op, SDValue Mask, SDValue EVL) { - EVT OldVT = Op.getValueType(); - SDLoc dl(Op); - Op = GetPromotedInteger(Op); - return DAG.getVPZeroExtendInReg(Op, Mask, EVL, dl, OldVT); - } - // Promote the given operand V (vector or scalar) according to N's specific // reduction kind. N must be an integer VECREDUCE_* or VP_REDUCE_*. Returns // the nominal extension opcode (ISD::(ANY|ZERO|SIGN)_EXTEND) and the @@ -395,6 +374,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer { SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo); + SDValue PromoteIntOp_COND_LOOP(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N); SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo); SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 4db9c5d009ae8..1fd5166ec148a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -6604,11 +6604,14 @@ SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) { N->getMemoryVT(), N->getMemOperand()); SDValue NewVal = NewLoad; - // Manually merge with vp.select + // Manually merge with vselect if (!N->getPassThru()->isUndef()) { assert(WidenVT.isScalableVector()); - NewVal = - DAG.getNode(ISD::VP_SELECT, dl, WidenVT, Mask, NewVal, PassThru, EVL); + NewVal = DAG.getNode(ISD::VSELECT, dl, WidenVT, Mask, NewVal, PassThru); + // The lanes past EVL are poison. + NewVal = DAG.getNode(ISD::VP_MERGE, dl, WidenVT, + DAG.getAllOnesConstant(dl, WideMaskVT), NewVal, + DAG.getPOISON(WidenVT), EVL); } // Modified the chain - switch anything that used the old chain to use diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 00d42100d8d7d..d36fd3e6853f5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -989,9 +989,11 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) { // to check. if (auto *MN = dyn_cast(N)) { ID.AddInteger(MN->getRawSubclassData()); - ID.AddInteger(MN->getPointerInfo().getAddrSpace()); - ID.AddInteger(MN->getMemOperand()->getFlags()); ID.AddInteger(MN->getMemoryVT().getRawBits()); + for (const MachineMemOperand *MMO : MN->memoperands()) { + ID.AddInteger(MMO->getPointerInfo().getAddrSpace()); + ID.AddInteger(MMO->getFlags()); + } } } @@ -1304,7 +1306,7 @@ SelectionDAG::AddModifiedNodeToCSEMaps(SDNode *N) { // recursive merging of other unrelated nodes down the line. Existing->intersectFlagsWith(N->getFlags()); if (auto *MemNode = dyn_cast(Existing)) - MemNode->refineRanges(cast(N)->getMemOperand()); + MemNode->refineRanges(cast(N)->memoperands()); ReplaceAllUsesWith(N, Existing); // N is now dead. Inform the listeners and delete it. @@ -2667,7 +2669,8 @@ SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) { } SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2, - ISD::CondCode Cond, const SDLoc &dl) { + ISD::CondCode Cond, const SDLoc &dl, + SDNodeFlags Flags) { EVT OpVT = N1.getValueType(); auto GetUndefBooleanConstant = [&]() { @@ -2796,7 +2799,8 @@ SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode SwappedCond = ISD::getSetCCSwappedOperands(Cond); if (!TLI->isCondCodeLegal(SwappedCond, OpVT.getSimpleVT())) return SDValue(); - return getSetCC(dl, VT, N2, N1, SwappedCond); + return getSetCC(dl, VT, N2, N1, SwappedCond, /*Chian=*/{}, + /*IsSignaling=*/false, Flags); } else if ((N2CFP && N2CFP->getValueAPF().isNaN()) || (OpVT.isFloatingPoint() && (N1.isUndef() || N2.isUndef()))) { // If an operand is known to be a nan (or undef that could be a nan), we can @@ -6059,6 +6063,8 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, const APInt &DemandedElts, return false; return true; } + case ISD::SPLAT_VECTOR: + return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1); case ISD::AssertNoFPClass: { FPClassTest NoFPClass = static_cast(Op.getConstantOperandVal(1)); @@ -8336,7 +8342,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, N1.getValueType().getVectorElementCount()) && "SETCC vector element counts must match!"); // Use FoldSetCC to simplify SETCC's. - if (SDValue V = FoldSetCC(VT, N1, N2, cast(N3)->get(), DL)) + if (SDValue V = + FoldSetCC(VT, N1, N2, cast(N3)->get(), DL, Flags)) return V; break; } @@ -9274,6 +9281,16 @@ getRuntimeCallSDValueHelper(SDValue Chain, const SDLoc &dl, return TLI->LowerCallTo(CLI); } +std::pair SelectionDAG::getStrcmp(SDValue Chain, + const SDLoc &dl, SDValue S1, + SDValue S2, + const CallInst *CI) { + PointerType *PT = PointerType::getUnqual(*getContext()); + TargetLowering::ArgListTy Args = {{S1, PT}, {S2, PT}}; + return getRuntimeCallSDValueHelper(Chain, dl, std::move(Args), CI, + RTLIB::STRCMP, this, TLI); +} + std::pair SelectionDAG::getStrstr(SDValue Chain, const SDLoc &dl, SDValue S1, SDValue S2, @@ -9821,6 +9838,14 @@ SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef Ops, EVT MemVT, MachineMemOperand *MMO) { + return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, ArrayRef(MMO)); +} + +SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, + SDVTList VTList, + ArrayRef Ops, EVT MemVT, + ArrayRef MMOs) { + assert(!MMOs.empty() && "Must have at least one MMO"); assert( (Opcode == ISD::INTRINSIC_VOID || Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::PREFETCH || @@ -9828,30 +9853,47 @@ SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, Opcode >= ISD::BUILTIN_OP_END && TSI->isTargetMemoryOpcode(Opcode))) && "Opcode is not a memory-accessing opcode!"); + PointerUnion MemRefs; + if (MMOs.size() == 1) { + MemRefs = MMOs[0]; + } else { + // Allocate: [size_t count][MMO*][MMO*]... + size_t AllocSize = + sizeof(size_t) + MMOs.size() * sizeof(MachineMemOperand *); + void *Buffer = Allocator.Allocate(AllocSize, alignof(size_t)); + size_t *CountPtr = static_cast(Buffer); + *CountPtr = MMOs.size(); + MachineMemOperand **Array = + reinterpret_cast(CountPtr + 1); + llvm::copy(MMOs, Array); + MemRefs = Array; + } + // Memoize the node unless it returns a glue result. MemIntrinsicSDNode *N; if (VTList.VTs[VTList.NumVTs-1] != MVT::Glue) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, VTList, Ops); ID.AddInteger(getSyntheticNodeSubclassData( - Opcode, dl.getIROrder(), VTList, MemVT, MMO)); - ID.AddInteger(MMO->getPointerInfo().getAddrSpace()); - ID.AddInteger(MMO->getFlags()); + Opcode, dl.getIROrder(), VTList, MemVT, MemRefs)); ID.AddInteger(MemVT.getRawBits()); + for (const MachineMemOperand *MMO : MMOs) { + ID.AddInteger(MMO->getPointerInfo().getAddrSpace()); + ID.AddInteger(MMO->getFlags()); + } void *IP = nullptr; if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) { - cast(E)->refineAlignment(MMO); + cast(E)->refineAlignment(MMOs); return SDValue(E, 0); } N = newSDNode(Opcode, dl.getIROrder(), dl.getDebugLoc(), - VTList, MemVT, MMO); + VTList, MemVT, MemRefs); createOperands(N, Ops); - - CSEMap.InsertNode(N, IP); + CSEMap.InsertNode(N, IP); } else { N = newSDNode(Opcode, dl.getIROrder(), dl.getDebugLoc(), - VTList, MemVT, MMO); + VTList, MemVT, MemRefs); createOperands(N, Ops); } InsertNode(N); @@ -13275,21 +13317,33 @@ HandleSDNode::~HandleSDNode() { DropOperands(); } -MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, - SDVTList VTs, EVT memvt, MachineMemOperand *mmo) - : SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) { - MemSDNodeBits.IsVolatile = MMO->isVolatile(); - MemSDNodeBits.IsNonTemporal = MMO->isNonTemporal(); - MemSDNodeBits.IsDereferenceable = MMO->isDereferenceable(); - MemSDNodeBits.IsInvariant = MMO->isInvariant(); - - // We check here that the size of the memory operand fits within the size of - // the MMO. This is because the MMO might indicate only a possible address - // range instead of specifying the affected memory addresses precisely. - assert( - (!MMO->getType().isValid() || - TypeSize::isKnownLE(memvt.getStoreSize(), MMO->getSize().getValue())) && - "Size mismatch!"); +MemSDNode::MemSDNode( + unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt, + PointerUnion memrefs) + : SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MemRefs(memrefs) { + bool IsVolatile = false; + bool IsNonTemporal = false; + bool IsDereferenceable = true; + bool IsInvariant = true; + for (const MachineMemOperand *MMO : memoperands()) { + IsVolatile |= MMO->isVolatile(); + IsNonTemporal |= MMO->isNonTemporal(); + IsDereferenceable &= MMO->isDereferenceable(); + IsInvariant &= MMO->isInvariant(); + } + MemSDNodeBits.IsVolatile = IsVolatile; + MemSDNodeBits.IsNonTemporal = IsNonTemporal; + MemSDNodeBits.IsDereferenceable = IsDereferenceable; + MemSDNodeBits.IsInvariant = IsInvariant; + + // For the single-MMO case, we check here that the size of the memory operand + // fits within the size of the MMO. This is because the MMO might indicate + // only a possible address range instead of specifying the affected memory + // addresses precisely. + assert((getNumMemOperands() != 1 || !getMemOperand()->getType().isValid() || + TypeSize::isKnownLE(memvt.getStoreSize(), + getMemOperand()->getSize().getValue())) && + "Size mismatch!"); } /// Profile - Gather unique data for the node. @@ -14206,7 +14260,7 @@ bool BuildVectorSDNode::isConstant() const { } std::optional> -BuildVectorSDNode::isConstantSequence() const { +BuildVectorSDNode::isArithmeticSequence() const { unsigned NumOps = getNumOperands(); if (NumOps < 2) return std::nullopt; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 52e0d8fefdf2f..7c762ed6d91ce 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2480,7 +2480,11 @@ SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, FCmpInst::Predicate Pred = InvertCond ? FC->getInversePredicate() : FC->getPredicate(); Condition = getFCmpCondCode(Pred); - if (TM.Options.NoNaNsFPMath) + if (FC->hasNoNaNs() || + (isKnownNeverNaN(FC->getOperand(0), + SimplifyQuery(DAG.getDataLayout(), FC)) && + isKnownNeverNaN(FC->getOperand(1), + SimplifyQuery(DAG.getDataLayout(), FC)))) Condition = getFCmpCodeWithoutNaN(Condition); } @@ -3514,10 +3518,12 @@ void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { /// - they do not need custom argument handling (no /// TLI.CollectTargetIntrinsicOperands()) void SelectionDAGBuilder::visitCallBrIntrinsic(const CallBrInst &I) { - TargetLowering::IntrinsicInfo Info; - assert(!DAG.getTargetLoweringInfo().getTgtMemIntrinsic( - Info, I, DAG.getMachineFunction(), I.getIntrinsicID()) && - "Intrinsic touches memory"); +#ifndef NDEBUG + SmallVector Infos; + DAG.getTargetLoweringInfo().getTgtMemIntrinsic( + Infos, I, DAG.getMachineFunction(), I.getIntrinsicID()); + assert(Infos.empty() && "Intrinsic touches memory"); +#endif auto [HasChain, OnlyLoad] = getTargetIntrinsicCallProperties(I); @@ -3793,7 +3799,8 @@ void SelectionDAGBuilder::visitFCmp(const FCmpInst &I) { ISD::CondCode Condition = getFCmpCondCode(predicate); auto *FPMO = cast(&I); - if (FPMO->hasNoNaNs() || TM.Options.NoNaNsFPMath) + if (FPMO->hasNoNaNs() || + (DAG.isKnownNeverNaN(Op1) && DAG.isKnownNeverNaN(Op2))) Condition = getFCmpCodeWithoutNaN(Condition); SDNodeFlags Flags; @@ -3802,7 +3809,8 @@ void SelectionDAGBuilder::visitFCmp(const FCmpInst &I) { EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), I.getType()); - setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); + setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition, + /*Chian=*/{}, /*IsSignaling=*/false, Flags)); } // Check if the condition of the select has one use or two users that are both @@ -5485,14 +5493,15 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic) { auto [HasChain, OnlyLoad] = getTargetIntrinsicCallProperties(I); - // Info is set by getTgtMemIntrinsic - TargetLowering::IntrinsicInfo Info; + // Infos is set by getTgtMemIntrinsic. + SmallVector Infos; const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - bool IsTgtMemIntrinsic = - TLI.getTgtMemIntrinsic(Info, I, DAG.getMachineFunction(), Intrinsic); + TLI.getTgtMemIntrinsic(Infos, I, DAG.getMachineFunction(), Intrinsic); + // Use the first (primary) info determines the node opcode. + TargetLowering::IntrinsicInfo *Info = !Infos.empty() ? &Infos[0] : nullptr; - SmallVector Ops = getTargetIntrinsicOperands( - I, HasChain, OnlyLoad, IsTgtMemIntrinsic ? &Info : nullptr); + SmallVector Ops = + getTargetIntrinsicOperands(I, HasChain, OnlyLoad, Info); SDVTList VTs = getTargetIntrinsicVTList(I, HasChain); // Propagate fast-math-flags from IR to node(s). @@ -5506,26 +5515,32 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, // In some cases, custom collection of operands from CallInst I may be needed. TLI.CollectTargetIntrinsicOperands(I, Ops, DAG); - if (IsTgtMemIntrinsic) { + if (!Infos.empty()) { // This is target intrinsic that touches memory - // - // TODO: We currently just fallback to address space 0 if getTgtMemIntrinsic - // didn't yield anything useful. - MachinePointerInfo MPI; - if (Info.ptrVal) - MPI = MachinePointerInfo(Info.ptrVal, Info.offset); - else if (Info.fallbackAddressSpace) - MPI = MachinePointerInfo(*Info.fallbackAddressSpace); - EVT MemVT = Info.memVT; - LocationSize Size = LocationSize::precise(Info.size); - if (Size.hasValue() && !Size.getValue()) - Size = LocationSize::precise(MemVT.getStoreSize()); - Align Alignment = Info.align.value_or(DAG.getEVTAlign(MemVT)); - MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( - MPI, Info.flags, Size, Alignment, I.getAAMetadata(), /*Ranges=*/nullptr, - Info.ssid, Info.order, Info.failureOrder); - Result = - DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops, MemVT, MMO); + // Create MachineMemOperands for each memory access described by the target. + MachineFunction &MF = DAG.getMachineFunction(); + SmallVector MMOs; + for (const auto &Info : Infos) { + // TODO: We currently just fallback to address space 0 if + // getTgtMemIntrinsic didn't yield anything useful. + MachinePointerInfo MPI; + if (Info.ptrVal) + MPI = MachinePointerInfo(Info.ptrVal, Info.offset); + else if (Info.fallbackAddressSpace) + MPI = MachinePointerInfo(*Info.fallbackAddressSpace); + EVT MemVT = Info.memVT; + LocationSize Size = LocationSize::precise(Info.size); + if (Size.hasValue() && !Size.getValue()) + Size = LocationSize::precise(MemVT.getStoreSize()); + Align Alignment = Info.align.value_or(DAG.getEVTAlign(MemVT)); + MachineMemOperand *MMO = MF.getMachineMemOperand( + MPI, Info.flags, Size, Alignment, I.getAAMetadata(), + /*Ranges=*/nullptr, Info.ssid, Info.order, Info.failureOrder); + MMOs.push_back(MMO); + } + + Result = DAG.getMemIntrinsicNode(Info->opc, getCurSDLoc(), VTs, Ops, + Info->memVT, MMOs); } else { Result = getTargetNonMemIntrinsicNode(*I.getType(), HasChain, Ops, VTs); } @@ -7524,7 +7539,8 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, case Intrinsic::type_test: case Intrinsic::public_type_test: - setValue(&I, getValue(ConstantInt::getTrue(I.getType()))); + reportFatalUsageError("llvm.type.test intrinsic must be lowered by the " + "LowerTypeTests pass before code generation"); return; case Intrinsic::assume: @@ -7873,6 +7889,16 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, return; } + case Intrinsic::cond_loop: { + SDValue InputChain = DAG.getRoot(); + SDValue P = getValue(I.getArgOperand(0)); + Res = DAG.getNode(ISD::COND_LOOP, sdl, DAG.getVTList(MVT::Other), + {InputChain, P}); + setValue(&I, Res); + DAG.setRoot(Res); + return; + } + case Intrinsic::eh_exceptionpointer: case Intrinsic::eh_exceptioncode: { // Get the exception pointer vreg, copy from it, and resize it to fit. @@ -8534,7 +8560,7 @@ void SelectionDAGBuilder::visitConstrainedFPIntrinsic( case ISD::STRICT_FSETCCS: { auto *FPCmp = dyn_cast(&FPI); ISD::CondCode Condition = getFCmpCondCode(FPCmp->getPredicate()); - if (TM.Options.NoNaNsFPMath) + if (DAG.isKnownNeverNaN(Opers[1]) && DAG.isKnownNeverNaN(Opers[2])) Condition = getFCmpCodeWithoutNaN(Condition); Opers.push_back(DAG.getCondCode(Condition)); break; @@ -8816,16 +8842,7 @@ void SelectionDAGBuilder::visitVPCmp(const VPCmpIntrinsic &VPIntrin) { ISD::CondCode Condition; CmpInst::Predicate CondCode = VPIntrin.getPredicate(); bool IsFP = VPIntrin.getOperand(0)->getType()->isFPOrFPVectorTy(); - if (IsFP) { - // FIXME: Regular fcmps are FPMathOperators which may have fast-math (nnan) - // flags, but calls that don't return floating-point types can't be - // FPMathOperators, like vp.fcmp. This affects constrained fcmp too. - Condition = getFCmpCondCode(CondCode); - if (TM.Options.NoNaNsFPMath) - Condition = getFCmpCodeWithoutNaN(Condition); - } else { - Condition = getICmpCondCode(CondCode); - } + Condition = IsFP ? getFCmpCondCode(CondCode) : getICmpCondCode(CondCode); SDValue Op1 = getValue(VPIntrin.getOperand(0)); SDValue Op2 = getValue(VPIntrin.getOperand(1)); @@ -8839,6 +8856,8 @@ void SelectionDAGBuilder::visitVPCmp(const VPCmpIntrinsic &VPIntrin) { EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), VPIntrin.getType()); + if (DAG.isKnownNeverNaN(Op1) && DAG.isKnownNeverNaN(Op2)) + Condition = getFCmpCodeWithoutNaN(Condition); setValue(&VPIntrin, DAG.getSetCCVP(DL, DestVT, Op1, Op2, Condition, MaskOp, EVL)); } @@ -9444,11 +9463,9 @@ bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) { const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1); const SelectionDAGTargetInfo &TSI = DAG.getSelectionDAGInfo(); - std::pair Res = - TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(), - getValue(Arg0), getValue(Arg1), - MachinePointerInfo(Arg0), - MachinePointerInfo(Arg1)); + std::pair Res = TSI.EmitTargetCodeForStrcmp( + DAG, getCurSDLoc(), DAG.getRoot(), getValue(Arg0), getValue(Arg1), + MachinePointerInfo(Arg0), MachinePointerInfo(Arg1), &I); if (Res.first.getNode()) { processIntegerCallValue(I, Res.first, true); PendingLoads.push_back(Res.second); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index 66ecb40e48954..9453036455727 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -483,6 +483,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { return "fake_use"; case ISD::RELOC_NONE: return "reloc_none"; + case ISD::COND_LOOP: + return "cond_loop"; case ISD::PSEUDO_PROBE: return "pseudoprobe"; case ISD::GC_TRANSITION_START: return "gc_transition.start"; @@ -733,6 +735,9 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { if (getFlags().hasNoFPExcept()) OS << " nofpexcept"; + if (getFlags().hasNoConvergent()) + OS << " noconvergent"; + if (const MachineSDNode *MN = dyn_cast(this)) { if (!MN->memoperands_empty()) { OS << "<"; @@ -933,7 +938,9 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { OS << ">"; } else if (const MemSDNode *M = dyn_cast(this)) { OS << "<"; - printMemOperand(OS, *M->getMemOperand(), G); + interleaveComma(M->memoperands(), OS, [&](const MachineMemOperand *MMO) { + printMemOperand(OS, *MMO, G); + }); if (auto *A = dyn_cast(M)) if (A->getOpcode() == ISD::ATOMIC_LOAD) { bool doExt = true; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index bd21c95c0ff93..ab70b200d2965 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3350,7 +3350,8 @@ class MatchStateUpdater : public SelectionDAG::DAGUpdateListener void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, const uint8_t *MatcherTable, - unsigned TableSize) { + unsigned TableSize, + const uint8_t *OperandLists) { // FIXME: Should these even be selected? Handle these cases in the caller? switch (NodeToMatch->getOpcode()) { default: @@ -3597,7 +3598,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, } case OPC_RecordMemRef: if (auto *MN = dyn_cast(N)) - MatchedMemRefs.push_back(MN->getMemOperand()); + llvm::append_range(MatchedMemRefs, MN->memoperands()); else { LLVM_DEBUG(dbgs() << "Expected MemSDNode "; N->dump(CurDAG); dbgs() << '\n'); @@ -4307,14 +4308,22 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, // Get the operand list. unsigned NumOps = MatcherTable[MatcherIndex++]; - SmallVector Ops; - for (unsigned i = 0; i != NumOps; ++i) { - unsigned RecNo = MatcherTable[MatcherIndex++]; - if (RecNo & 128) - RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); - assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); - Ops.push_back(RecordedNodes[RecNo].first); + SmallVector Ops; + if (NumOps != 0) { + // Get the index into the OperandLists. + size_t OperandIndex = MatcherTable[MatcherIndex++]; + if (OperandIndex & 128) + OperandIndex = GetVBR(OperandIndex, MatcherTable, MatcherIndex); + + for (unsigned i = 0; i != NumOps; ++i) { + unsigned RecNo = OperandLists[OperandIndex++]; + if (RecNo & 128) + RecNo = GetVBR(RecNo, OperandLists, OperandIndex); + + assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); + Ops.push_back(RecordedNodes[RecNo].first); + } } // If there are variadic operands to add, handle them now. diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 1ee7085c67179..aee9f0d36b3f0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3700,6 +3700,13 @@ bool TargetLowering::SimplifyDemandedVectorElts( SDLoc DL(Op); EVT SrcVT = Src.getValueType(); EVT SrcSVT = SrcVT.getScalarType(); + + // If we're after type legalization and SrcSVT is not legal, use the + // promoted type for creating constants to avoid creating nodes with + // illegal types. + if (AfterLegalizeTypes) + SrcSVT = getLegalTypeToTransformTo(*TLO.DAG.getContext(), SrcSVT); + SmallVector MaskElts; MaskElts.push_back(TLO.DAG.getAllOnesConstant(DL, SrcSVT)); MaskElts.append(NumSrcElts - 1, TLO.DAG.getConstant(0, DL, SrcSVT)); @@ -7501,7 +7508,8 @@ TargetLowering::prepareSREMEqFold(EVT SETCCVT, SDValue REMNode, } SDValue TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, - const DenormalMode &Mode) const { + const DenormalMode &Mode, + SDNodeFlags Flags) const { SDLoc DL(Op); EVT VT = Op.getValueType(); EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); @@ -7512,7 +7520,8 @@ SDValue TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, if (Mode.Input == DenormalMode::PreserveSign || Mode.Input == DenormalMode::PositiveZero) { // Test = X == 0.0 - return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); + return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ, /*Chain=*/{}, + /*Signaling=*/false, Flags); } // Testing it with denormal inputs to avoid wrong estimate. @@ -7521,8 +7530,9 @@ SDValue TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, const fltSemantics &FltSem = VT.getFltSemantics(); APFloat SmallestNorm = APFloat::getSmallestNormalized(FltSem); SDValue NormC = DAG.getConstantFP(SmallestNorm, DL, VT); - SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op); - return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT); + SDValue Fabs = DAG.getNode(ISD::FABS, DL, VT, Op, Flags); + return DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT, /*Chain=*/{}, + /*Signaling=*/false, Flags); } SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG, diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp index fac0a17d4c0da..47ee485a2cca9 100644 --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -2392,7 +2392,9 @@ MCSymbol * TargetLoweringObjectFileXCOFF::getTargetSymbol(const GlobalValue *GV, const TargetMachine &TM) const { // We always use a qualname symbol for a GV that represents - // a declaration, a function descriptor, or a common symbol. + // a declaration, a function descriptor, or a common symbol. An IFunc is + // lowered as a special trampoline function which has an entry point and a + // descriptor. // If a GV represents a GlobalVariable and -fdata-sections is enabled, we // also return a qualname so that a label symbol could be avoided. // It is inherently ambiguous when the GO represents the address of a @@ -2411,6 +2413,11 @@ TargetLoweringObjectFileXCOFF::getTargetSymbol(const GlobalValue *GV, SectionForGlobal(GVar, SectionKind::getData(), TM)) ->getQualNameSymbol(); + if (isa(GO)) + return static_cast( + getSectionForFunctionDescriptor(GO, TM)) + ->getQualNameSymbol(); + SectionKind GOKind = getKindForGlobal(GO, TM); if (GOKind.isText()) return static_cast( @@ -2683,7 +2690,7 @@ TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(const GlobalValue *GV) { MCSymbol *TargetLoweringObjectFileXCOFF::getFunctionEntryPointSymbol( const GlobalValue *Func, const TargetMachine &TM) const { - assert((isa(Func) || + assert((isa(Func) || isa(Func) || (isa(Func) && isa_and_nonnull( cast(Func)->getAliaseeObject()))) && @@ -2700,7 +2707,7 @@ MCSymbol *TargetLoweringObjectFileXCOFF::getFunctionEntryPointSymbol( // undefined symbols gets treated as csect with XTY_ER property. if (((TM.getFunctionSections() && !Func->hasSection()) || Func->isDeclarationForLinker()) && - isa(Func)) { + (isa(Func) || isa(Func))) { return getContext() .getXCOFFSection( NameStr, SectionKind::getText(), @@ -2714,7 +2721,9 @@ MCSymbol *TargetLoweringObjectFileXCOFF::getFunctionEntryPointSymbol( } MCSection *TargetLoweringObjectFileXCOFF::getSectionForFunctionDescriptor( - const Function *F, const TargetMachine &TM) const { + const GlobalObject *F, const TargetMachine &TM) const { + assert((isa(F) || isa(F)) && + "F must be a function or ifunc object."); SmallString<128> NameStr; getNameWithPrefix(NameStr, F, TM); return getContext().getXCOFFSection( @@ -2801,6 +2810,11 @@ void TargetLoweringObjectFileGOFF::getModuleMetadata(Module &M) { ADAPR->setBeginSymbol(ADASym); } +bool TargetLoweringObjectFileGOFF::shouldPutJumpTableInFunctionSection( + bool UsesLabelDifference, const Function &F) const { + return true; +} + MCSection *TargetLoweringObjectFileGOFF::getExplicitSectionGlobal( const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { return SelectSectionForGlobal(GO, Kind, TM); diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index cffb3ed1b8779..a56285679929e 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -646,7 +646,7 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg, CopySrcReg = MI->getOperand(1).getReg(); else { assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike"); - CopySrcReg = MI->getOperand(2).getReg(); + CopySrcReg = MI->getOperand(1).getReg(); } if (!CopySrcReg.isVirtual()) @@ -669,7 +669,7 @@ Register TargetRegisterInfo::lookThruSingleUseCopyChain( CopySrcReg = MI->getOperand(1).getReg(); else { assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike"); - CopySrcReg = MI->getOperand(2).getReg(); + CopySrcReg = MI->getOperand(1).getReg(); } // Continue only if the next definition in the chain is for a virtual diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index ff339d4a23915..fe67e434a4de3 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -357,10 +357,10 @@ bool TwoAddressInstructionImpl::isCopyToReg(MachineInstr &MI, Register &SrcReg, bool &IsDstPhys) const { SrcReg = 0; DstReg = 0; - if (MI.isCopy()) { + if (MI.isCopy() || MI.isSubregToReg()) { DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(1).getReg(); - } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { + } else if (MI.isInsertSubreg()) { DstReg = MI.getOperand(0).getReg(); SrcReg = MI.getOperand(2).getReg(); } else { diff --git a/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp b/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp index 1c0ddc8e1ca30..268f1a5b6f81b 100644 --- a/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp +++ b/llvm/lib/DWARFLinker/Classic/DWARFStreamer.cpp @@ -61,7 +61,7 @@ Error DwarfStreamer::init(Triple TheTriple, "no register info for target %s", TripleName.c_str()); - MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); + MCOptions = mc::InitMCTargetOptionsFromFlags(); MCOptions.AsmVerbose = true; MCOptions.MCUseDwarfDirectory = MCTargetOptions::EnableDwarfDirectory; MAI.reset(TheTarget->createMCAsmInfo(*MRI, TheTriple, MCOptions)); diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp index 9222235d7a41e..0049026481110 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp +++ b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.cpp @@ -41,7 +41,7 @@ Error DwarfEmitterImpl::init(Triple TheTriple, "no register info for target %s", TripleName.c_str()); - MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); + MCOptions = mc::InitMCTargetOptionsFromFlags(); MCOptions.AsmVerbose = true; MCOptions.MCUseDwarfDirectory = MCTargetOptions::EnableDwarfDirectory; MAI.reset(TheTarget->createMCAsmInfo(*MRI, TheTriple, MCOptions)); diff --git a/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h index bdebee42f396e..1496c1dbbff1b 100644 --- a/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h +++ b/llvm/lib/DWARFLinker/Parallel/DWARFEmitterImpl.h @@ -104,6 +104,7 @@ class DwarfEmitterImpl { /// \defgroup MCObjects MC layer objects constructed by the streamer /// @{ + MCTargetOptions MCOptions; std::unique_ptr MRI; std::unique_ptr MAI; std::unique_ptr MOFI; diff --git a/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h b/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h index 03c0566f58f82..aa9d1fe64bc73 100644 --- a/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h +++ b/llvm/lib/DWARFLinker/Parallel/DebugLineSectionEmitter.h @@ -79,7 +79,7 @@ class DebugLineSectionEmitter { "no register info for target %s", TripleName.c_str()); - MCTargetOptions MCOptions = mc::InitMCTargetOptionsFromFlags(); + MCOptions = mc::InitMCTargetOptionsFromFlags(); MAI.reset(TheTarget->createMCAsmInfo(*MRI, TheTriple, MCOptions)); if (!MAI) return createStringError(std::errc::invalid_argument, @@ -419,6 +419,7 @@ class DebugLineSectionEmitter { Triple TheTriple; DwarfUnit &U; + MCTargetOptions MCOptions; std::unique_ptr MRI; std::unique_ptr MAI; std::unique_ptr MC; diff --git a/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp b/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp index 3a92140ede9d0..05191f68e0ddd 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp @@ -182,8 +182,8 @@ bool DWARFVerifier::verifyUnitHeader(const DWARFDataExtractor DebugInfoData, bool HeaderShown = false; auto ShowHeaderOnce = [&]() { if (!HeaderShown) { - error() << format("Units[%d] - start offset: 0x%08" PRIx64 " \n", - UnitIndex, OffsetStart); + error() << formatv("Units[{0}] - start offset: {1:x+8}\n", UnitIndex, + OffsetStart); HeaderShown = true; } }; @@ -272,8 +272,8 @@ unsigned DWARFVerifier::verifyUnitContents(DWARFUnit &Unit, if (Die.hasChildren()) { if (Die.getFirstChild().isValid() && Die.getFirstChild().getTag() == DW_TAG_null) { - warn() << dwarf::TagString(Die.getTag()) - << " has DW_CHILDREN_yes but DIE has no children: "; + warn() << formatv("{0} has DW_CHILDREN_yes but DIE has no children: ", + dwarf::TagString(Die.getTag())); Die.dump(OS); } } @@ -292,8 +292,8 @@ unsigned DWARFVerifier::verifyUnitContents(DWARFUnit &Unit, if (!dwarf::isUnitType(Die.getTag())) { ErrorCategory.Report("Compilation unit root DIE is not a unit DIE", [&]() { - error() << "Compilation unit root DIE is not a unit DIE: " - << dwarf::TagString(Die.getTag()) << ".\n"; + error() << formatv("Compilation unit root DIE is not a unit DIE: {0}.\n", + dwarf::TagString(Die.getTag())); }); NumUnitErrors++; } @@ -301,9 +301,9 @@ unsigned DWARFVerifier::verifyUnitContents(DWARFUnit &Unit, uint8_t UnitType = Unit.getUnitType(); if (!DWARFUnit::isMatchingUnitTypeAndTag(UnitType, Die.getTag())) { ErrorCategory.Report("Mismatched unit type", [&]() { - error() << "Compilation unit type (" << dwarf::UnitTypeString(UnitType) - << ") and root DIE (" << dwarf::TagString(Die.getTag()) - << ") do not match.\n"; + error() << formatv( + "Compilation unit type ({0}) and root DIE ({1}) do not match.\n", + dwarf::UnitTypeString(UnitType), dwarf::TagString(Die.getTag())); }); NumUnitErrors++; } @@ -389,8 +389,9 @@ unsigned DWARFVerifier::verifyAbbrevSection(const DWARFDebugAbbrev *Abbrev) { if (!Result.second) { ErrorCategory.Report( "Abbreviation declartion contains multiple attributes", [&]() { - error() << "Abbreviation declaration contains multiple " - << AttributeString(Attribute.Attr) << " attributes.\n"; + error() << formatv("Abbreviation declaration contains multiple " + "{0} attributes.\n", + AttributeString(Attribute.Attr)); AbbrDecl.dump(OS); }); ++NumErrors; @@ -418,10 +419,11 @@ unsigned DWARFVerifier::verifyUnits(const DWARFUnitVector &Units) { ReferenceMap CrossUnitReferences; unsigned Index = 1; + for (const auto &Unit : Units) { - OS << "Verifying unit: " << Index << " / " << Units.getNumUnits(); + OS << formatv("Verifying unit: {0} / {1}", Index, Units.getNumUnits()); if (const char* Name = Unit->getUnitDIE(true).getShortName()) - OS << ", \"" << Name << '\"'; + OS << formatv(", \"{0}\"", Name); OS << '\n'; OS.flush(); ReferenceMap UnitLocalReferences; @@ -600,7 +602,7 @@ unsigned DWARFVerifier::verifyDieRanges(const DWARFDie &Die, if (!Range.valid()) { ++NumErrors; ErrorCategory.Report("Invalid address range", [&]() { - error() << "Invalid address range " << Range << "\n"; + error() << formatv("Invalid address range {0}\n", Range); DumpDieAfterError = true; }); continue; @@ -615,8 +617,9 @@ unsigned DWARFVerifier::verifyDieRanges(const DWARFDie &Die, if (auto PrevRange = RI.insert(Range)) { ++NumErrors; ErrorCategory.Report("DIE has overlapping DW_AT_ranges", [&]() { - error() << "DIE has overlapping ranges in DW_AT_ranges attribute: " - << *PrevRange << " and " << Range << '\n'; + error() << formatv("DIE has overlapping ranges in DW_AT_ranges " + "attribute: {0} and {1}\n", + *PrevRange, Range); DumpDieAfterError = true; }); } @@ -693,7 +696,7 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, auto ReportError = [&](StringRef category, const Twine &TitleMsg) { ++NumErrors; ErrorCategory.Report(category, [&]() { - error() << TitleMsg << '\n'; + error() << formatv("{0}\n", TitleMsg); dump(Die) << '\n'; }); }; @@ -712,11 +715,12 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, if (U->isDWOUnit() && RangeSection.Data.empty()) break; if (*SectionOffset >= RangeSection.Data.size()) - ReportError("DW_AT_ranges offset out of bounds", - "DW_AT_ranges offset is beyond " + - StringRef(DwarfVersion < 5 ? ".debug_ranges" - : ".debug_rnglists") + - " bounds: " + llvm::formatv("{0:x8}", *SectionOffset)); + ReportError( + "DW_AT_ranges offset out of bounds", + llvm::formatv("DW_AT_ranges offset is beyond {0} bounds: {1:x8}", + StringRef(DwarfVersion < 5 ? ".debug_ranges" + : ".debug_rnglists"), + *SectionOffset)); break; } ReportError("Invalid DW_AT_ranges encoding", @@ -726,9 +730,11 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, // Make sure the offset in the DW_AT_stmt_list attribute is valid. if (auto SectionOffset = AttrValue.Value.getAsSectionOffset()) { if (*SectionOffset >= U->getLineSection().Data.size()) - ReportError("DW_AT_stmt_list offset out of bounds", - "DW_AT_stmt_list offset is beyond .debug_line bounds: " + - llvm::formatv("{0:x8}", *SectionOffset)); + ReportError( + "DW_AT_stmt_list offset out of bounds", + llvm::formatv( + "DW_AT_stmt_list offset is beyond .debug_line bounds: {0:x8}", + *SectionOffset)); break; } ReportError("Invalid DW_AT_stmt_list encoding", @@ -782,11 +788,10 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, if (DieTag == DW_TAG_GNU_call_site && RefTag == DW_TAG_subprogram) break; ReportError("Incompatible DW_AT_abstract_origin tag reference", - "DIE with tag " + TagString(DieTag) + " has " + - AttributeString(Attr) + - " that points to DIE with " - "incompatible tag " + - TagString(RefTag)); + formatv("DIE with tag {0} has {1} that points to DIE with " + "incompatible tag {2}", + TagString(DieTag), AttributeString(Attr), + TagString(RefTag))); } break; } @@ -794,8 +799,8 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, DWARFDie TypeDie = Die.getAttributeValueAsReferencedDie(DW_AT_type); if (TypeDie && !isType(TypeDie.getTag())) { ReportError("Incompatible DW_AT_type attribute tag", - "DIE has " + AttributeString(Attr) + - " with incompatible tag " + TagString(TypeDie.getTag())); + formatv("DIE has {0} with incompatible tag {1}", + AttributeString(Attr), TagString(TypeDie.getTag()))); } break; } @@ -811,32 +816,30 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, if (std::optional LastFileIdx = LT->getLastValidFileIndex()) { ReportError("Invalid file index in DW_AT_decl_file", - "DIE has " + AttributeString(Attr) + - " with an invalid file index " + - llvm::formatv("{0}", *FileIdx) + - " (valid values are [" + - (IsZeroIndexed ? "0-" : "1-") + - llvm::formatv("{0}", *LastFileIdx) + "])"); + llvm::formatv("DIE has {0} with an invalid file index " + "{1} (valid values are [{2}-{3}])", + AttributeString(Attr), *FileIdx, + (IsZeroIndexed ? "0" : "1"), + *LastFileIdx)); } else { - ReportError("Invalid file index in DW_AT_decl_file", - "DIE has " + AttributeString(Attr) + - " with an invalid file index " + - llvm::formatv("{0}", *FileIdx) + - " (the file table in the prologue is empty)"); + ReportError( + "Invalid file index in DW_AT_decl_file", + llvm::formatv("DIE has {0} with an invalid file index {1} (the " + "file table in the prologue is empty)", + AttributeString(Attr), *FileIdx)); } } } else { ReportError( "File index in DW_AT_decl_file reference CU with no line table", - "DIE has " + AttributeString(Attr) + - " that references a file with index " + - llvm::formatv("{0}", *FileIdx) + - " and the compile unit has no line table"); + llvm::formatv("DIE has {0} that references a file with index {1} " + "and the compile unit has no line table", + AttributeString(Attr), *FileIdx)); } } else { ReportError("Invalid encoding in DW_AT_decl_file", - "DIE has " + AttributeString(Attr) + - " with invalid encoding"); + llvm::formatv("DIE has {0} with invalid encoding", + AttributeString(Attr))); } break; } @@ -846,7 +849,7 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, ReportError( Attr == DW_AT_call_line ? "Invalid file index in DW_AT_decl_line" : "Invalid file index in DW_AT_call_line", - "DIE has " + AttributeString(Attr) + " with invalid encoding"); + formatv("DIE has {0} with invalid encoding", AttributeString(Attr))); } break; } @@ -907,11 +910,9 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, // Check if the offset is within the bounds of this specific line table if (*SectionOffset < SequencesStart || *SectionOffset >= LineTableEnd) { ReportError("DW_AT_LLVM_stmt_sequence offset out of line table bounds", - "DW_AT_LLVM_stmt_sequence offset " + - llvm::formatv("{0:x8}", *SectionOffset) + - " is not within the line table bounds [" + - llvm::formatv("{0:x8}", SequencesStart) + ", " + - llvm::formatv("{0:x8}", LineTableEnd) + ")"); + llvm::formatv("DW_AT_LLVM_stmt_sequence offset {0:x8} is not " + "within the line table bounds [{1:x8}, {2:x8})", + *SectionOffset, SequencesStart, LineTableEnd)); break; } @@ -924,9 +925,9 @@ unsigned DWARFVerifier::verifyDebugInfoAttribute(const DWARFDie &Die, if (It == LineTable->Sequences.end()) ReportError( "Invalid DW_AT_LLVM_stmt_sequence offset", - "DW_AT_LLVM_stmt_sequence offset " + - llvm::formatv("{0:x8}", *SectionOffset) + - " does not point to a valid sequence offset in the line table"); + llvm::formatv("DW_AT_LLVM_stmt_sequence offset {0:x8} does not point " + "to a valid sequence offset in the line table", + *SectionOffset)); break; } default: @@ -957,10 +958,9 @@ unsigned DWARFVerifier::verifyDebugInfoForm(const DWARFDie &Die, if (CUOffset >= CUSize) { ++NumErrors; ErrorCategory.Report("Invalid CU offset", [&]() { - error() << FormEncodingString(Form) << " CU offset " - << format("0x%08" PRIx64, CUOffset) - << " is invalid (must be less than CU size of " - << format("0x%08" PRIx64, CUSize) << "):\n"; + error() << formatv("{0} CU offset {1:x+8} is invalid (must be less " + "than CU size of {2:x+8}):\n", + FormEncodingString(Form), CUOffset, CUSize); Die.dump(OS, 0, DumpOpts); dump(Die) << '\n'; }); @@ -1005,7 +1005,7 @@ unsigned DWARFVerifier::verifyDebugInfoForm(const DWARFDie &Die, ++NumErrors; std::string ErrMsg = toString(std::move(E)); ErrorCategory.Report("Invalid DW_FORM attribute", [&]() { - error() << ErrMsg << ":\n"; + error() << formatv("{0}:\n", ErrMsg); dump(Die) << '\n'; }); } @@ -1032,8 +1032,9 @@ unsigned DWARFVerifier::verifyDebugInfoReferences( continue; ++NumErrors; ErrorCategory.Report("Invalid DIE reference", [&]() { - error() << "invalid DIE reference " << format("0x%08" PRIx64, Pair.first) - << ". Offset is in between DIEs:\n"; + error() << formatv( + "invalid DIE reference {0:x+8}. Offset is in between DIEs:\n", + Pair.first); for (auto Offset : Pair.second) dump(GetDIEForOffset(Offset)) << '\n'; OS << "\n"; @@ -1058,8 +1059,9 @@ void DWARFVerifier::verifyDebugLineStmtOffsets() { if (!LineTable) { ++NumDebugLineErrors; ErrorCategory.Report("Unparsable .debug_line entry", [&]() { - error() << ".debug_line[" << format("0x%08" PRIx64, LineTableOffset) - << "] was not able to be parsed for CU:\n"; + error() << formatv( + ".debug_line[{0:x+8}] was not able to be parsed for CU:\n", + LineTableOffset); dump(Die) << '\n'; }); continue; @@ -1076,10 +1078,9 @@ void DWARFVerifier::verifyDebugLineStmtOffsets() { ++NumDebugLineErrors; const auto &OldDie = Iter->second; ErrorCategory.Report("Identical DW_AT_stmt_list section offset", [&]() { - error() << "two compile unit DIEs, " - << format("0x%08" PRIx64, OldDie.getOffset()) << " and " - << format("0x%08" PRIx64, Die.getOffset()) - << ", have the same DW_AT_stmt_list section offset:\n"; + error() << formatv("two compile unit DIEs, {0:x+8} and {1:x+8}, have " + "the same DW_AT_stmt_list section offset:\n", + OldDie.getOffset(), Die.getOffset()); dump(OldDie); dump(Die) << '\n'; }); @@ -1110,12 +1111,10 @@ void DWARFVerifier::verifyDebugLineRows() { ErrorCategory.Report( "Invalid index in .debug_line->prologue.file_names->dir_idx", [&]() { - error() << ".debug_line[" - << format("0x%08" PRIx64, - *toSectionOffset(Die.find(DW_AT_stmt_list))) - << "].prologue.file_names[" << FileIndex - << "].dir_idx contains an invalid index: " - << FileName.DirIdx << "\n"; + error() << formatv(".debug_line[{0:x+8}].prologue.file_names[{1}]" + ".dir_idx contains an invalid index: {2}\n", + *toSectionOffset(Die.find(DW_AT_stmt_list)), + FileIndex, FileName.DirIdx); }); } @@ -1128,11 +1127,10 @@ void DWARFVerifier::verifyDebugLineRows() { (void)HasFullPath; auto [It, Inserted] = FullPathMap.try_emplace(FullPath, FileIndex); if (!Inserted && It->second != FileIndex && DumpOpts.Verbose) { - warn() << ".debug_line[" - << format("0x%08" PRIx64, - *toSectionOffset(Die.find(DW_AT_stmt_list))) - << "].prologue.file_names[" << FileIndex - << "] is a duplicate of file_names[" << It->second << "]\n"; + warn() << formatv(".debug_line[{0:x+8}].prologue.file_names[{1}] is a " + "duplicate of file_names[{2}]\n", + *toSectionOffset(Die.find(DW_AT_stmt_list)), + FileIndex, It->second); } FileIndex++; @@ -1152,11 +1150,10 @@ void DWARFVerifier::verifyDebugLineRows() { ++NumDebugLineErrors; ErrorCategory.Report( "decreasing address between debug_line rows", [&]() { - error() << ".debug_line[" - << format("0x%08" PRIx64, - *toSectionOffset(Die.find(DW_AT_stmt_list))) - << "] row[" << RowIndex - << "] decreases in address from previous row:\n"; + error() << formatv(".debug_line[{0:x+8}] row[{1}] decreases in " + "address from previous row:\n", + *toSectionOffset(Die.find(DW_AT_stmt_list)), + RowIndex); DWARFDebugLine::Row::dumpTableHeader(OS, 0); if (RowIndex > 0) @@ -1169,13 +1166,12 @@ void DWARFVerifier::verifyDebugLineRows() { if (!LineTable->hasFileAtIndex(Row.File)) { ++NumDebugLineErrors; ErrorCategory.Report("Invalid file index in debug_line", [&]() { - error() << ".debug_line[" - << format("0x%08" PRIx64, - *toSectionOffset(Die.find(DW_AT_stmt_list))) - << "][" << RowIndex << "] has invalid file index " << Row.File - << " (valid values are [" << MinFileIndex << ',' - << LineTable->Prologue.FileNames.size() - << (isDWARF5 ? ")" : "]") << "):\n"; + error() << formatv(".debug_line[{0:x+8}][{1}] has invalid file index " + "{2} (valid values are [{3},{4}{5}):\n", + *toSectionOffset(Die.find(DW_AT_stmt_list)), + RowIndex, Row.File, MinFileIndex, + LineTable->Prologue.FileNames.size(), + (isDWARF5 ? ")" : "]")); DWARFDebugLine::Row::dumpTableHeader(OS, 0); Row.dump(OS); OS << '\n'; @@ -1247,8 +1243,8 @@ void DWARFVerifier::verifyAppleAccelTable(const DWARFSection *AccelSection, uint32_t HashIdx = AccelSectionData.getU32(&BucketsOffset); if (HashIdx >= NumHashes && HashIdx != UINT32_MAX) { ErrorCategory.Report("Invalid hash index", [&]() { - error() << format("Bucket[%d] has invalid hash index: %u.\n", BucketIdx, - HashIdx); + error() << formatv("Bucket[{0}] has invalid hash index: {1}.\n", + BucketIdx, HashIdx); }); } } @@ -1274,9 +1270,8 @@ void DWARFVerifier::verifyAppleAccelTable(const DWARFSection *AccelSection, if (!AccelSectionData.isValidOffsetForDataOfSize(HashDataOffset, sizeof(uint64_t))) { ErrorCategory.Report("Invalid HashData offset", [&]() { - error() << format("Hash[%d] has invalid HashData offset: " - "0x%08" PRIx64 ".\n", - HashIdx, HashDataOffset); + error() << formatv("Hash[{0}] has invalid HashData offset: {1:x+8}.\n", + HashIdx, HashDataOffset); }); } @@ -1301,21 +1296,21 @@ void DWARFVerifier::verifyAppleAccelTable(const DWARFSection *AccelSection, Name = ""; ErrorCategory.Report("Invalid DIE offset", [&]() { - error() << format( - "%s Bucket[%d] Hash[%d] = 0x%08x " - "Str[%u] = 0x%08" PRIx64 " DIE[%d] = 0x%08" PRIx64 " " - "is not a valid DIE offset for \"%s\".\n", - SectionName, BucketIdx, HashIdx, Hash, StringCount, StrpOffset, - HashDataIdx, Offset, Name); + error() << formatv("{0} Bucket[{1}] Hash[{2}] = {3:x+8} " + "Str[{4}] = {5:x+8} DIE[{6}] = {7:x+8} " + "is not a valid DIE offset for \"{8}\".\n", + SectionName, BucketIdx, HashIdx, Hash, + StringCount, StrpOffset, HashDataIdx, Offset, + Name); }); continue; } if ((Tag != dwarf::DW_TAG_null) && (Die.getTag() != Tag)) { ErrorCategory.Report("Mismatched Tag in accellerator table", [&]() { - error() << "Tag " << dwarf::TagString(Tag) - << " in accelerator table does not match Tag " - << dwarf::TagString(Die.getTag()) << " of DIE[" - << HashDataIdx << "].\n"; + error() << formatv("Tag {0} in accelerator table does not match " + "Tag {1} of DIE[{2}].\n", + dwarf::TagString(Tag), + dwarf::TagString(Die.getTag()), HashDataIdx); }); } } @@ -2317,7 +2312,7 @@ bool DWARFVerifier::verifyDebugStrOffsets( if (Error E = C.takeError()) { std::string Msg = toString(std::move(E)); ErrorCategory.Report("String offset error", [&]() { - error() << SectionName << ": " << Msg << '\n'; + error() << formatv("{0}: {1}\n", SectionName, Msg); return false; }); } @@ -2364,7 +2359,7 @@ void DWARFVerifier::summarize() { if (DumpOpts.ShowAggregateErrors && ErrorCategory.GetNumCategories()) { error() << "Aggregated error counts:\n"; ErrorCategory.EnumerateResults([&](StringRef s, unsigned count) { - error() << s << " occurred " << count << " time(s).\n"; + error() << formatv("{0} occurred {1} time(s).\n", s, count); }); } if (!DumpOpts.JsonErrSummaryFile.empty()) { @@ -2372,9 +2367,9 @@ void DWARFVerifier::summarize() { raw_fd_ostream JsonStream(DumpOpts.JsonErrSummaryFile, EC, sys::fs::OF_Text); if (EC) { - error() << "unable to open json summary file '" - << DumpOpts.JsonErrSummaryFile - << "' for writing: " << EC.message() << '\n'; + error() << formatv( + "unable to open json summary file {0} for writing: {1}\n", + DumpOpts.JsonErrSummaryFile, EC.message()); return; } diff --git a/llvm/lib/DebugInfo/Symbolize/DIPrinter.cpp b/llvm/lib/DebugInfo/Symbolize/DIPrinter.cpp index 989fde9749b18..957c0c4c8f9a9 100644 --- a/llvm/lib/DebugInfo/Symbolize/DIPrinter.cpp +++ b/llvm/lib/DebugInfo/Symbolize/DIPrinter.cpp @@ -84,7 +84,7 @@ class SourceCode { void format(raw_ostream &OS) { if (!PrunedSource) return; - size_t MaxLineNumberWidth = std::ceil(std::log10(LastLine)); + size_t MaxLineNumberWidth = NumDigitsBase10(LastLine); int64_t L = FirstLine; for (size_t Pos = 0; Pos < PrunedSource->size(); ++L) { size_t PosEnd = PrunedSource->find('\n', Pos); diff --git a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp index 5f101cc6c946b..5e341ada1889e 100644 --- a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp +++ b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp @@ -161,7 +161,7 @@ GlobalVariable *createBinDesc(Module &M, ArrayRef> Bufs, Binary.bytes_begin()); const auto *Entry = reinterpret_cast( - Binary.bytes_begin() + Header->EntryOffset); + Binary.bytes_begin() + Header->EntriesOffset); BeginOffset = Entry->ImageOffset; EndOffset = Entry->ImageOffset + Entry->ImageSize; } diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp index 2cf18dfafcdf7..464ec5b5a2ece 100644 --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -2098,7 +2098,8 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createTaskloop( llvm::function_ref()> LoopInfo, Value *LBVal, Value *UBVal, Value *StepVal, bool Untied, Value *IfCond, Value *GrainSize, bool NoGroup, int Sched, Value *Final, bool Mergeable, - Value *Priority, TaskDupCallbackTy DupCB, Value *TaskContextStructPtrVal) { + Value *Priority, uint64_t NumOfCollapseLoops, TaskDupCallbackTy DupCB, + Value *TaskContextStructPtrVal) { if (!updateToLocation(Loc)) return InsertPointTy(); @@ -2175,8 +2176,8 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createTaskloop( OI.PostOutlineCB = [this, Ident, LBVal, UBVal, StepVal, Untied, TaskloopAllocaBB, CLI, Loc, TaskDupFn, ToBeDeleted, IfCond, GrainSize, NoGroup, Sched, FakeLB, FakeUB, - FakeStep, Final, Mergeable, - Priority](Function &OutlinedFn) mutable { + FakeStep, Final, Mergeable, Priority, + NumOfCollapseLoops](Function &OutlinedFn) mutable { // Replace the Stale CI by appropriate RTL function call. assert(OutlinedFn.hasOneUse() && "there must be a single user for the outlined function"); @@ -2359,29 +2360,53 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createTaskloop( Builder.SetInsertPoint(CLI->getBody(), CLI->getBody()->getFirstInsertionPt()); - // The canonical loop is generated with a fixed lower bound. We need to - // update the index calculation code to use the task's lower bound. The - // generated code looks like this: - // %omp_loop.iv = phi ... - // ... - // %tmp = mul [type] %omp_loop.iv, step - // %user_index = add [type] tmp, lb - // OpenMPIRBuilder constructs canonical loops to have exactly three uses of - // the normalised induction variable: - // 1. This one: converting the normalised IV to the user IV - // 2. The increment (add) - // 3. The comparison against the trip count (icmp) - // (1) is the only use that is a mul followed by an add so this cannot match - // other IR. - assert(CLI->getIndVar()->getNumUses() == 3 && - "Canonical loop should have exactly three uses of the ind var"); - for (User *IVUser : CLI->getIndVar()->users()) { - if (auto *Mul = dyn_cast(IVUser)) { - if (Mul->getOpcode() == Instruction::Mul) { - for (User *MulUser : Mul->users()) { - if (auto *Add = dyn_cast(MulUser)) { - if (Add->getOpcode() == Instruction::Add) { - Add->setOperand(1, CastedTaskLB); + if (NumOfCollapseLoops > 1) { + llvm::SmallVector UsersToReplace; + // When using the collapse clause, the bounds of the loop have to be + // adjusted to properly represent the iterator of the outer loop. + Value *IVPlusTaskLB = Builder.CreateAdd( + CLI->getIndVar(), + Builder.CreateSub(CastedTaskLB, ConstantInt::get(IVTy, 1))); + // To ensure every Use is correctly captured, we first want to record + // which users to replace the value in, and then replace the value. + for (auto IVUse = CLI->getIndVar()->uses().begin(); + IVUse != CLI->getIndVar()->uses().end(); IVUse++) { + User *IVUser = IVUse->getUser(); + if (auto *Op = dyn_cast(IVUser)) { + if (Op->getOpcode() == Instruction::URem || + Op->getOpcode() == Instruction::UDiv) { + UsersToReplace.push_back(IVUser); + } + } + } + for (User *User : UsersToReplace) { + User->replaceUsesOfWith(CLI->getIndVar(), IVPlusTaskLB); + } + } else { + // The canonical loop is generated with a fixed lower bound. We need to + // update the index calculation code to use the task's lower bound. The + // generated code looks like this: + // %omp_loop.iv = phi ... + // ... + // %tmp = mul [type] %omp_loop.iv, step + // %user_index = add [type] tmp, lb + // OpenMPIRBuilder constructs canonical loops to have exactly three uses + // of the normalised induction variable: + // 1. This one: converting the normalised IV to the user IV + // 2. The increment (add) + // 3. The comparison against the trip count (icmp) + // (1) is the only use that is a mul followed by an add so this cannot + // match other IR. + assert(CLI->getIndVar()->getNumUses() == 3 && + "Canonical loop should have exactly three uses of the ind var"); + for (User *IVUser : CLI->getIndVar()->users()) { + if (auto *Mul = dyn_cast(IVUser)) { + if (Mul->getOpcode() == Instruction::Mul) { + for (User *MulUser : Mul->users()) { + if (auto *Add = dyn_cast(MulUser)) { + if (Add->getOpcode() == Instruction::Add) { + Add->setOperand(1, CastedTaskLB); + } } } } @@ -3075,19 +3100,16 @@ Error OpenMPIRBuilder::emitReductionListCopy( RemoteLaneOffset, ReductionArrayTy, IsByRefElem); if (IsByRefElem) { - Value *GEP; - InsertPointOrErrorTy GenResult = - RI.DataPtrPtrGen(Builder.saveIP(), - Builder.CreatePointerBitCastOrAddrSpaceCast( - DestAlloca, Builder.getPtrTy(), ".ascast"), - GEP); + // Copy descriptor from source and update base_ptr to shuffled data + Value *DestDescriptorAddr = Builder.CreatePointerBitCastOrAddrSpaceCast( + DestAlloca, Builder.getPtrTy(), ".ascast"); + + InsertPointOrErrorTy GenResult = generateReductionDescriptor( + DestDescriptorAddr, LocalStorage, SrcElementAddr, + RI.ByRefAllocatedType, RI.DataPtrPtrGen); if (!GenResult) return GenResult.takeError(); - - Builder.CreateStore(Builder.CreatePointerBitCastOrAddrSpaceCast( - LocalStorage, Builder.getPtrTy(), ".ascast"), - GEP); } } else { switch (RI.EvaluationKind) { @@ -3577,6 +3599,37 @@ Expected OpenMPIRBuilder::emitShuffleAndReduceFunction( return SarFunc; } +OpenMPIRBuilder::InsertPointOrErrorTy +OpenMPIRBuilder::generateReductionDescriptor( + Value *DescriptorAddr, Value *DataPtr, Value *SrcDescriptorAddr, + Type *DescriptorType, + function_ref + DataPtrPtrGen) { + + // Copy the source descriptor to preserve all metadata (rank, extents, + // strides, etc.) + Value *DescriptorSize = + Builder.getInt64(M.getDataLayout().getTypeStoreSize(DescriptorType)); + Builder.CreateMemCpy( + DescriptorAddr, M.getDataLayout().getPrefTypeAlign(DescriptorType), + SrcDescriptorAddr, M.getDataLayout().getPrefTypeAlign(DescriptorType), + DescriptorSize); + + // Update the base pointer field to point to the local shuffled data + Value *DataPtrField; + InsertPointOrErrorTy GenResult = + DataPtrPtrGen(Builder.saveIP(), DescriptorAddr, DataPtrField); + + if (!GenResult) + return GenResult.takeError(); + + Builder.CreateStore(Builder.CreatePointerBitCastOrAddrSpaceCast( + DataPtr, Builder.getPtrTy(), ".ascast"), + DataPtrField); + + return Builder.saveIP(); +} + Expected OpenMPIRBuilder::emitListToGlobalCopyFunction( ArrayRef ReductionInfos, Type *ReductionsBufferTy, AttributeList FuncAttrs, ArrayRef IsByRef) { @@ -3789,15 +3842,24 @@ Expected OpenMPIRBuilder::emitListToGlobalReduceFunction( ReductionsBufferTy, BufferVD, 0, En.index()); if (!IsByRef.empty() && IsByRef[En.index()]) { - Value *ByRefDataPtr; + // Get source descriptor from the reduce list argument + Value *ReduceList = + Builder.CreateLoad(Builder.getPtrTy(), ReduceListArgAddrCast); + Value *SrcElementPtrPtr = + Builder.CreateInBoundsGEP(RedListArrayTy, ReduceList, + {ConstantInt::get(IndexTy, 0), + ConstantInt::get(IndexTy, En.index())}); + Value *SrcDescriptorAddr = + Builder.CreateLoad(Builder.getPtrTy(), SrcElementPtrPtr); + // Copy descriptor from source and update base_ptr to global buffer data InsertPointOrErrorTy GenResult = - RI.DataPtrPtrGen(Builder.saveIP(), ByRefAlloc, ByRefDataPtr); + generateReductionDescriptor(ByRefAlloc, GlobValPtr, SrcDescriptorAddr, + RI.ByRefAllocatedType, RI.DataPtrPtrGen); if (!GenResult) return GenResult.takeError(); - Builder.CreateStore(GlobValPtr, ByRefDataPtr); Builder.CreateStore(ByRefAlloc, TargetElementPtrPtr); } else { Builder.CreateStore(GlobValPtr, TargetElementPtrPtr); @@ -4023,13 +4085,23 @@ Expected OpenMPIRBuilder::emitGlobalToListReduceFunction( ReductionsBufferTy, BufferVD, 0, En.index()); if (!IsByRef.empty() && IsByRef[En.index()]) { - Value *ByRefDataPtr; + // Get source descriptor from the reduce list + Value *ReduceListVal = + Builder.CreateLoad(Builder.getPtrTy(), ReduceListArgAddrCast); + Value *SrcElementPtrPtr = + Builder.CreateInBoundsGEP(RedListArrayTy, ReduceListVal, + {ConstantInt::get(IndexTy, 0), + ConstantInt::get(IndexTy, En.index())}); + Value *SrcDescriptorAddr = + Builder.CreateLoad(Builder.getPtrTy(), SrcElementPtrPtr); + + // Copy descriptor from source and update base_ptr to global buffer data InsertPointOrErrorTy GenResult = - RI.DataPtrPtrGen(Builder.saveIP(), ByRefAlloc, ByRefDataPtr); + generateReductionDescriptor(ByRefAlloc, GlobValPtr, SrcDescriptorAddr, + RI.ByRefAllocatedType, RI.DataPtrPtrGen); if (!GenResult) return GenResult.takeError(); - Builder.CreateStore(GlobValPtr, ByRefDataPtr); Builder.CreateStore(ByRefAlloc, TargetElementPtrPtr); } else { Builder.CreateStore(GlobValPtr, TargetElementPtrPtr); @@ -5830,8 +5902,8 @@ OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::applyWorkshareLoopTarget( // Mark the body loop as region which needs to be extracted OI.EntryBB = CLI->getBody(); - OI.ExitBB = CLI->getLatch()->splitBasicBlock(CLI->getLatch()->begin(), - "omp.prelatch", true); + OI.ExitBB = CLI->getLatch()->splitBasicBlockBefore(CLI->getLatch()->begin(), + "omp.prelatch"); // Prepare loop body for extraction Builder.restoreIP({CLI->getPreheader(), CLI->getPreheader()->begin()}); @@ -5955,11 +6027,11 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::applyWorkshareLoop( case OMPScheduleType::BaseGreedy: case OMPScheduleType::BaseBalanced: case OMPScheduleType::BaseSteal: - case OMPScheduleType::BaseGuidedSimd: case OMPScheduleType::BaseRuntimeSimd: assert(!ChunkSize && "schedule type does not support user-defined chunk sizes"); [[fallthrough]]; + case OMPScheduleType::BaseGuidedSimd: case OMPScheduleType::BaseDynamicChunked: case OMPScheduleType::BaseGuidedChunked: case OMPScheduleType::BaseGuidedIterativeChunked: @@ -6649,8 +6721,8 @@ void OpenMPIRBuilder::createIfVersion(CanonicalLoopInfo *CanonicalLoop, // The loop latch must have only one predecessor. Currently it is branched to // from both the 'then' and 'else' branches. - L->getLoopLatch()->splitBasicBlock( - L->getLoopLatch()->begin(), NamePrefix + ".pre_latch", /*Before=*/true); + L->getLoopLatch()->splitBasicBlockBefore(L->getLoopLatch()->begin(), + NamePrefix + ".pre_latch"); // Ensure that the then block is added to the loop so we add the attributes in // the next step diff --git a/llvm/lib/IR/Attributes.cpp b/llvm/lib/IR/Attributes.cpp index 726a3d8dd906f..696bc6fffc035 100644 --- a/llvm/lib/IR/Attributes.cpp +++ b/llvm/lib/IR/Attributes.cpp @@ -513,6 +513,10 @@ CaptureInfo Attribute::getCaptureInfo() const { return CaptureInfo::createFromIntValue(pImpl->getValueAsInt()); } +DenormalFPEnv Attribute::getDenormalFPEnv() const { + return DenormalFPEnv::createFromIntValue(pImpl->getValueAsInt()); +} + FPClassTest Attribute::getNoFPClass() const { assert(hasAttribute(Attribute::NoFPClass) && "Can only call getNoFPClass() on nofpclass attribute"); @@ -693,6 +697,17 @@ std::string Attribute::getAsString(bool InAttrGrp) const { return Result; } + if (hasAttribute(Attribute::DenormalFPEnv)) { + std::string Result = "denormal_fpenv("; + raw_string_ostream OS(Result); + + struct DenormalFPEnv FPEnv = getDenormalFPEnv(); + FPEnv.print(OS, /*OmitIfSame=*/true); + + OS << ')'; + return Result; + } + if (hasAttribute(Attribute::NoFPClass)) { std::string Result = "nofpclass"; raw_string_ostream(Result) << getNoFPClass(); @@ -2285,6 +2300,10 @@ AttrBuilder &AttrBuilder::addCapturesAttr(CaptureInfo CI) { return addRawIntAttr(Attribute::Captures, CI.toIntValue()); } +AttrBuilder &AttrBuilder::addDenormalFPEnvAttr(DenormalFPEnv FPEnv) { + return addRawIntAttr(Attribute::DenormalFPEnv, FPEnv.toIntValue()); +} + AttrBuilder &AttrBuilder::addNoFPClassAttr(FPClassTest Mask) { if (Mask == fcNone) return *this; @@ -2543,16 +2562,16 @@ static bool denormModeCompatible(DenormalMode CallerMode, } static bool checkDenormMode(const Function &Caller, const Function &Callee) { - DenormalMode CallerMode = Caller.getDenormalModeRaw(); - DenormalMode CalleeMode = Callee.getDenormalModeRaw(); + DenormalFPEnv CallerEnv = Caller.getDenormalFPEnv(); + DenormalFPEnv CalleeEnv = Callee.getDenormalFPEnv(); - if (denormModeCompatible(CallerMode, CalleeMode)) { - DenormalMode CallerModeF32 = Caller.getDenormalModeF32Raw(); - DenormalMode CalleeModeF32 = Callee.getDenormalModeF32Raw(); + if (denormModeCompatible(CallerEnv.DefaultMode, CalleeEnv.DefaultMode)) { + DenormalMode CallerModeF32 = CallerEnv.F32Mode; + DenormalMode CalleeModeF32 = CalleeEnv.F32Mode; if (CallerModeF32 == DenormalMode::getInvalid()) - CallerModeF32 = CallerMode; + CallerModeF32 = CallerEnv.DefaultMode; if (CalleeModeF32 == DenormalMode::getInvalid()) - CalleeModeF32 = CalleeMode; + CalleeModeF32 = CalleeEnv.DefaultMode; return denormModeCompatible(CallerModeF32, CalleeModeF32); } diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 70a409b729e68..0efeeb999d3dd 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -63,6 +63,15 @@ static cl::opt static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } +// Report a fatal error along with the +// Call Instruction which caused the error +[[noreturn]] static void reportFatalUsageErrorWithCI(StringRef reason, + CallBase *CI) { + CI->print(llvm::errs()); + llvm::errs() << "\n"; + reportFatalUsageError(reason); +} + // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have // changed their type from v4f32 to v2i64. static bool upgradePTESTIntrinsic(Function *F, Intrinsic::ID IID, @@ -3030,7 +3039,8 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, Intrinsic::ID IID; switch (VecWidth) { default: - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); + break; case 128: IID = Intrinsic::x86_avx512_vpshufbitqmb_128; break; @@ -3063,7 +3073,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 512 && EltWidth == 64) IID = Intrinsic::x86_avx512_fpclass_pd_512; else - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); Rep = Builder.CreateIntrinsic(IID, {CI->getOperand(0), CI->getArgOperand(1)}); @@ -3087,7 +3097,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 512 && EltWidth == 64) IID = Intrinsic::x86_avx512_mask_cmp_pd_512; else - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); Value *Mask = Constant::getAllOnesValue(CI->getType()); if (VecWidth == 512) @@ -3257,7 +3267,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, Name.ends_with("d") || Name.ends_with("q")) IsSigned = true; else - llvm_unreachable("Unknown suffix"); + reportFatalUsageErrorWithCI("Intrinsic has unknown suffix", CI); unsigned Imm; if (CI->arg_size() == 3) { @@ -3631,6 +3641,9 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, unsigned Imm = cast(CI->getArgOperand(1))->getZExtValue(); unsigned NumElts = cast(CI->getType())->getNumElements(); + if (Name == "sse2.pshufl.w" && NumElts % 8 != 0) + reportFatalUsageErrorWithCI("Intrinsic has invalid signature", CI); + SmallVector Idxs(NumElts); for (unsigned l = 0; l != NumElts; l += 8) { for (unsigned i = 0; i != 4; ++i) @@ -3650,6 +3663,9 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, unsigned Imm = cast(CI->getArgOperand(1))->getZExtValue(); unsigned NumElts = cast(CI->getType())->getNumElements(); + if (Name == "sse2.pshufh.w" && NumElts % 8 != 0) + reportFatalUsageErrorWithCI("Intrinsic has invalid signature", CI); + SmallVector Idxs(NumElts); for (unsigned l = 0; l != NumElts; l += 8) { for (unsigned i = 0; i != 4; ++i) @@ -3901,7 +3917,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi IID = Intrinsic::x86_avx512_psllv_w_512; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else if (Name.ends_with(".128")) { if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d @@ -3913,7 +3929,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w : Intrinsic::x86_sse2_psll_w; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else if (Name.ends_with(".256")) { if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d @@ -3925,7 +3941,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w : Intrinsic::x86_avx2_psll_w; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else { if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 @@ -3939,7 +3955,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 : Intrinsic::x86_avx512_psll_w_512; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } Rep = upgradeX86MaskedShift(Builder, *CI, IID); @@ -3968,7 +3984,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi IID = Intrinsic::x86_avx512_psrlv_w_512; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else if (Name.ends_with(".128")) { if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d @@ -3980,7 +3996,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w : Intrinsic::x86_sse2_psrl_w; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else if (Name.ends_with(".256")) { if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d @@ -3992,7 +4008,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w : Intrinsic::x86_avx2_psrl_w; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else { if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 @@ -4006,7 +4022,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 : Intrinsic::x86_avx512_psrl_w_512; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } Rep = upgradeX86MaskedShift(Builder, *CI, IID); @@ -4031,7 +4047,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi IID = Intrinsic::x86_avx512_psrav_w_512; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else if (Name.ends_with(".128")) { if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d @@ -4044,7 +4060,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w : Intrinsic::x86_sse2_psra_w; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else if (Name.ends_with(".256")) { if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d @@ -4057,7 +4073,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w : Intrinsic::x86_avx2_psra_w; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } else { if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 @@ -4071,7 +4087,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 : Intrinsic::x86_avx512_psra_w_512; else - llvm_unreachable("Unexpected size"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected size", CI); } Rep = upgradeX86MaskedShift(Builder, *CI, IID); @@ -4240,7 +4256,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 256 && EltWidth == 64) IID = Intrinsic::x86_fma_vfmaddsub_pd_256; else - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); Value *Ops[] = {CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2)}; @@ -4315,7 +4331,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 512 && EltWidth == 64) IID = Intrinsic::x86_avx512_pternlog_q_512; else - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); Value *Args[] = {CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), CI->getArgOperand(3)}; @@ -4342,7 +4358,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 512 && High) IID = Intrinsic::x86_avx512_vpmadd52h_uq_512; else - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); Value *Args[] = {CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2)}; @@ -4377,7 +4393,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 512 && IsSaturating) IID = Intrinsic::x86_avx512_vpdpbusds_512; else - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); Value *Args[] = {CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2)}; @@ -4401,7 +4417,8 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 512) NewArgType = VectorType::get(Builder.getInt8Ty(), 64, false); else - llvm_unreachable("Unexpected vector bit width"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected vector bit width", + CI); Args[1] = Builder.CreateBitCast(Args[1], NewArgType); Args[2] = Builder.CreateBitCast(Args[2], NewArgType); @@ -4432,7 +4449,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 512 && IsSaturating) IID = Intrinsic::x86_avx512_vpdpwssds_512; else - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); Value *Args[] = {CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2)}; @@ -4456,7 +4473,8 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (VecWidth == 512) NewArgType = VectorType::get(Builder.getInt16Ty(), 32, false); else - llvm_unreachable("Unexpected vector bit width"); + reportFatalUsageErrorWithCI("Intrinsic has unexpected vector bit width", + CI); Args[1] = Builder.CreateBitCast(Args[1], NewArgType); Args[2] = Builder.CreateBitCast(Args[2], NewArgType); @@ -4479,7 +4497,7 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, else if (Name[0] == 's' && Name.back() == '4') IID = Intrinsic::x86_subborrow_64; else - llvm_unreachable("Unexpected intrinsic"); + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); // Make a call with 3 operands. Value *Args[] = {CI->getArgOperand(0), CI->getArgOperand(1), @@ -4497,7 +4515,8 @@ static Value *upgradeX86IntrinsicCall(StringRef Name, CallBase *CI, Function *F, } else if (Name.starts_with("avx512.mask.") && upgradeAVX512MaskToSelect(Name, Builder, *CI, Rep)) { // Rep will be updated by the call in the condition. - } + } else + reportFatalUsageErrorWithCI("Unexpected intrinsic", CI); return Rep; } @@ -6313,12 +6332,17 @@ void llvm::UpgradeFunctionAttributes(Function &F) { Arg.removeAttrs( AttributeFuncs::typeIncompatible(Arg.getType(), Arg.getAttributes())); + bool AddingAttrs = false, RemovingAttrs = false; + AttrBuilder AttrsToAdd(F.getContext()); + AttributeMask AttrsToRemove; + // Older versions of LLVM treated an "implicit-section-name" attribute // similarly to directly setting the section on a Function. if (Attribute A = F.getFnAttribute("implicit-section-name"); A.isValid() && A.isStringAttribute()) { F.setSection(A.getValueAsString()); - F.removeFnAttr("implicit-section-name"); + AttrsToRemove.addAttribute("implicit-section-name"); + RemovingAttrs = true; } if (!F.empty()) { @@ -6335,9 +6359,46 @@ void llvm::UpgradeFunctionAttributes(Function &F) { // We will leave behind dead attribute uses on external declarations, but // clang never added these to declarations anyway. - F.removeFnAttr("amdgpu-unsafe-fp-atomics"); + AttrsToRemove.addAttribute("amdgpu-unsafe-fp-atomics"); + RemovingAttrs = true; + } + } + + DenormalMode DenormalFPMath = DenormalMode::getIEEE(); + DenormalMode DenormalFPMathF32 = DenormalMode::getInvalid(); + + bool HandleDenormalMode = false; + + if (Attribute Attr = F.getFnAttribute("denormal-fp-math"); Attr.isValid()) { + DenormalMode ParsedMode = parseDenormalFPAttribute(Attr.getValueAsString()); + if (ParsedMode.isValid()) { + DenormalFPMath = ParsedMode; + AttrsToRemove.addAttribute("denormal-fp-math"); + AddingAttrs = RemovingAttrs = true; + HandleDenormalMode = true; + } + } + + if (Attribute Attr = F.getFnAttribute("denormal-fp-math-f32"); + Attr.isValid()) { + DenormalMode ParsedMode = parseDenormalFPAttribute(Attr.getValueAsString()); + if (ParsedMode.isValid()) { + DenormalFPMathF32 = ParsedMode; + AttrsToRemove.addAttribute("denormal-fp-math-f32"); + AddingAttrs = RemovingAttrs = true; + HandleDenormalMode = true; } } + + if (HandleDenormalMode) + AttrsToAdd.addDenormalFPEnvAttr( + DenormalFPEnv(DenormalFPMath, DenormalFPMathF32)); + + if (RemovingAttrs) + F.removeFnAttrs(AttrsToRemove); + + if (AddingAttrs) + F.addFnAttrs(AttrsToAdd); } // Check if the function attribute is not present and set it. diff --git a/llvm/lib/IR/BasicBlock.cpp b/llvm/lib/IR/BasicBlock.cpp index 3642e935397cb..e89231cac32b7 100644 --- a/llvm/lib/IR/BasicBlock.cpp +++ b/llvm/lib/IR/BasicBlock.cpp @@ -552,11 +552,7 @@ bool BasicBlock::isEntryBlock() const { return this == &F->getEntryBlock(); } -BasicBlock *BasicBlock::splitBasicBlock(iterator I, const Twine &BBName, - bool Before) { - if (Before) - return splitBasicBlockBefore(I, BBName); - +BasicBlock *BasicBlock::splitBasicBlock(iterator I, const Twine &BBName) { assert(getTerminator() && "Can't use splitBasicBlock on degenerate BB!"); assert(I != InstList.end() && "Trying to get me to create degenerate basic block!"); diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp index d31322a3013b6..448171b2bbbb1 100644 --- a/llvm/lib/IR/Core.cpp +++ b/llvm/lib/IR/Core.cpp @@ -209,6 +209,22 @@ LLVMAttributeRef LLVMCreateConstantRangeAttribute(LLVMContextRef C, APInt(NumBits, ArrayRef(UpperWords, NumWords))))); } +LLVMAttributeRef LLVMCreateDenormalFPEnvAttribute( + LLVMContextRef C, LLVMDenormalModeKind DefaultModeOutput, + LLVMDenormalModeKind DefaultModeInput, LLVMDenormalModeKind FloatModeOutput, + LLVMDenormalModeKind FloatModeInput) { + auto &Ctx = *unwrap(C); + + DenormalFPEnv Env( + DenormalMode( + static_cast(DefaultModeOutput), + static_cast(DefaultModeInput)), + DenormalMode( + static_cast(FloatModeOutput), + static_cast(FloatModeInput))); + return wrap(Attribute::get(Ctx, Attribute::DenormalFPEnv, Env.toIntValue())); +} + LLVMAttributeRef LLVMCreateStringAttribute(LLVMContextRef C, const char *K, unsigned KLength, const char *V, unsigned VLength) { diff --git a/llvm/lib/IR/DIBuilder.cpp b/llvm/lib/IR/DIBuilder.cpp index 05c9d58bf6e85..ec6fd8e8b895a 100644 --- a/llvm/lib/IR/DIBuilder.cpp +++ b/llvm/lib/IR/DIBuilder.cpp @@ -29,7 +29,7 @@ DIBuilder::DIBuilder(Module &m, bool AllowUnresolvedNodes, DICompileUnit *CU) AllowUnresolvedNodes(AllowUnresolvedNodes) { if (CUNode) { if (const auto &ETs = CUNode->getEnumTypes()) - AllEnumTypes.assign(ETs.begin(), ETs.end()); + EnumTypes.assign(ETs.begin(), ETs.end()); if (const auto &RTs = CUNode->getRetainedTypes()) AllRetainTypes.assign(RTs.begin(), RTs.end()); if (const auto &GVs = CUNode->getGlobalVariables()) @@ -66,10 +66,10 @@ void DIBuilder::finalize() { return; } - if (!AllEnumTypes.empty()) - CUNode->replaceEnumTypes(MDTuple::get( - VMContext, SmallVector(AllEnumTypes.begin(), - AllEnumTypes.end()))); + if (!EnumTypes.empty()) + CUNode->replaceEnumTypes( + MDTuple::get(VMContext, SmallVector(EnumTypes.begin(), + EnumTypes.end()))); SmallVector RetainValues; // Declarations and definitions of the same type may be retained. Some @@ -379,10 +379,13 @@ DIDerivedType *DIBuilder::createTypedef(DIType *Ty, StringRef Name, DIScope *Context, uint32_t AlignInBits, DINode::DIFlags Flags, DINodeArray Annotations) { - return DIDerivedType::get(VMContext, dwarf::DW_TAG_typedef, Name, File, - LineNo, getNonCompileUnitScope(Context), Ty, - (uint64_t)0, AlignInBits, (uint64_t)0, std::nullopt, - std::nullopt, Flags, nullptr, Annotations); + auto *T = DIDerivedType::get( + VMContext, dwarf::DW_TAG_typedef, Name, File, LineNo, + getNonCompileUnitScope(Context), Ty, (uint64_t)0, AlignInBits, + (uint64_t)0, std::nullopt, std::nullopt, Flags, nullptr, Annotations); + if (isa_and_nonnull(Context)) + getSubprogramNodesTrackingVector(Context).emplace_back(T); + return T; } DIDerivedType * @@ -390,10 +393,14 @@ DIBuilder::createTemplateAlias(DIType *Ty, StringRef Name, DIFile *File, unsigned LineNo, DIScope *Context, DINodeArray TParams, uint32_t AlignInBits, DINode::DIFlags Flags, DINodeArray Annotations) { - return DIDerivedType::get(VMContext, dwarf::DW_TAG_template_alias, Name, File, - LineNo, getNonCompileUnitScope(Context), Ty, - (uint64_t)0, AlignInBits, (uint64_t)0, std::nullopt, - std::nullopt, Flags, TParams.get(), Annotations); + auto *T = + DIDerivedType::get(VMContext, dwarf::DW_TAG_template_alias, Name, File, + LineNo, getNonCompileUnitScope(Context), Ty, + (uint64_t)0, AlignInBits, (uint64_t)0, std::nullopt, + std::nullopt, Flags, TParams.get(), Annotations); + if (isa_and_nonnull(Context)) + getSubprogramNodesTrackingVector(Context).emplace_back(T); + return T; } DIDerivedType *DIBuilder::createFriend(DIType *Ty, DIType *FriendTy) { @@ -584,6 +591,8 @@ DICompositeType *DIBuilder::createClassType( OffsetInBits, Flags, Elements, RunTimeLang, /*EnumKind=*/std::nullopt, VTableHolder, cast_or_null(TemplateParams), UniqueIdentifier); trackIfUnresolved(R); + if (isa_and_nonnull(Context)) + getSubprogramNodesTrackingVector(Context).emplace_back(R); return R; } @@ -600,6 +609,8 @@ DICompositeType *DIBuilder::createStructType( nullptr, UniqueIdentifier, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, Specification, NumExtraInhabitants); trackIfUnresolved(R); + if (isa_and_nonnull(Context)) + getSubprogramNodesTrackingVector(Context).emplace_back(R); return R; } @@ -616,6 +627,8 @@ DICompositeType *DIBuilder::createStructType( nullptr, UniqueIdentifier, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr, Specification, NumExtraInhabitants); trackIfUnresolved(R); + if (isa_and_nonnull(Context)) + getSubprogramNodesTrackingVector(Context).emplace_back(R); return R; } @@ -629,6 +642,8 @@ DICompositeType *DIBuilder::createUnionType( Elements, RunTimeLang, /*EnumKind=*/std::nullopt, nullptr, nullptr, UniqueIdentifier); trackIfUnresolved(R); + if (isa_and_nonnull(Scope)) + getSubprogramNodesTrackingVector(Scope).emplace_back(R); return R; } @@ -663,7 +678,10 @@ DICompositeType *DIBuilder::createEnumerationType( getNonCompileUnitScope(Scope), UnderlyingType, SizeInBits, AlignInBits, 0, IsScoped ? DINode::FlagEnumClass : DINode::FlagZero, Elements, RunTimeLang, EnumKind, nullptr, nullptr, UniqueIdentifier); - AllEnumTypes.emplace_back(CTy); + if (isa_and_nonnull(Scope)) + getSubprogramNodesTrackingVector(Scope).emplace_back(CTy); + else + EnumTypes.emplace_back(CTy); trackIfUnresolved(CTy); return CTy; } @@ -677,6 +695,8 @@ DIDerivedType *DIBuilder::createSetType(DIScope *Scope, StringRef Name, SizeInBits, AlignInBits, 0, std::nullopt, std::nullopt, DINode::FlagZero); trackIfUnresolved(R); + if (isa_and_nonnull(Scope)) + getSubprogramNodesTrackingVector(Scope).emplace_back(R); return R; } @@ -712,6 +732,8 @@ DICompositeType *DIBuilder::createArrayType( : (Metadata *)cast(RK), nullptr, nullptr, 0, BitStride); trackIfUnresolved(R); + if (isa_and_nonnull(Scope)) + getSubprogramNodesTrackingVector(Scope).emplace_back(R); return R; } @@ -770,7 +792,8 @@ void DIBuilder::retainType(DIScope *T) { assert((isa(T) || (isa(T) && cast(T)->isDefinition() == false)) && "Expected type or subprogram declaration"); - AllRetainTypes.emplace_back(T); + if (!isa_and_nonnull(T->getScope())) + AllRetainTypes.emplace_back(T); } DIBasicType *DIBuilder::createUnspecifiedParameter() { return nullptr; } @@ -786,6 +809,8 @@ DICompositeType *DIBuilder::createForwardDecl( SizeInBits, AlignInBits, 0, DINode::FlagFwdDecl, nullptr, RuntimeLang, /*EnumKind=*/EnumKind, nullptr, nullptr, UniqueIdentifier); trackIfUnresolved(RetTy); + if (isa_and_nonnull(Scope)) + getSubprogramNodesTrackingVector(Scope).emplace_back(RetTy); return RetTy; } @@ -802,6 +827,8 @@ DICompositeType *DIBuilder::createReplaceableCompositeType( nullptr, nullptr, Annotations) .release(); trackIfUnresolved(RetTy); + if (isa_and_nonnull(Scope)) + getSubprogramNodesTrackingVector(Scope).emplace_back(RetTy); return RetTy; } @@ -861,9 +888,12 @@ DISubrangeType *DIBuilder::createSubrangeType( uint64_t SizeInBits, uint32_t AlignInBits, DINode::DIFlags Flags, DIType *Ty, Metadata *LowerBound, Metadata *UpperBound, Metadata *Stride, Metadata *Bias) { - return DISubrangeType::get(VMContext, Name, File, LineNo, Scope, SizeInBits, - AlignInBits, Flags, Ty, LowerBound, UpperBound, - Stride, Bias); + auto *T = DISubrangeType::get(VMContext, Name, File, LineNo, Scope, + SizeInBits, AlignInBits, Flags, Ty, LowerBound, + UpperBound, Stride, Bias); + if (isa_and_nonnull(Scope)) + getSubprogramNodesTrackingVector(Scope).emplace_back(T); + return T; } static void checkGlobalVariableScope(DIScope *Context) { diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp index 1859bc468cac9..1a83a29ec24e7 100644 --- a/llvm/lib/IR/DebugInfo.cpp +++ b/llvm/lib/IR/DebugInfo.cpp @@ -176,6 +176,7 @@ void DebugInfoFinder::reset() { GVs.clear(); TYs.clear(); Scopes.clear(); + Macros.clear(); NodesSeen.clear(); } @@ -212,6 +213,8 @@ void DebugInfoFinder::processCompileUnit(DICompileUnit *CU) { processSubprogram(cast(RT)); for (auto *Import : CU->getImportedEntities()) processImportedEntity(Import); + for (auto *Macro : CU->getMacros()) + processMacroNode(Macro, nullptr); } void DebugInfoFinder::processInstruction(const Module &M, @@ -275,6 +278,36 @@ void DebugInfoFinder::processImportedEntity(const DIImportedEntity *Import) { processScope(M->getScope()); } +/// Process a macro debug info node (DIMacroNode). +/// +/// A DIMacroNode is one of two types: +/// - DIMacro: A single macro definition. Add it to the Macros list along with +/// its containing DIMacroFile. +/// - DIMacroFile: A file containing macros. Recursively process all nested +/// macro nodes within it (avoiding duplicates by tracking visited nodes). +void DebugInfoFinder::processMacroNode(DIMacroNode *Macro, + DIMacroFile *CurrentMacroFile) { + if (!Macro) + return; + + if (auto *M = dyn_cast(Macro)) { + addMacro(M, CurrentMacroFile); + return; + } + + auto *MF = dyn_cast(Macro); + assert(MF && + "Expected a DIMacroFile (it can't be any other type at this point)"); + + // Check if we've already seen this macro file to avoid infinite recursion + if (!NodesSeen.insert(MF).second) + return; + + // Recursively process nested macros in the macro file + for (auto *Element : MF->getElements()) + processMacroNode(Element, MF); +} + void DebugInfoFinder::processScope(DIScope *Scope) { if (!Scope) return; @@ -324,9 +357,9 @@ void DebugInfoFinder::processSubprogram(DISubprogram *SP) { } SP->forEachRetainedNode( - [this](const DILocalVariable *LV) { processVariable(LV); }, - [](const DILabel *L) {}, - [this](const DIImportedEntity *IE) { processImportedEntity(IE); }); + [this](DILocalVariable *LV) { processVariable(LV); }, [](DILabel *L) {}, + [this](DIImportedEntity *IE) { processImportedEntity(IE); }, + [this](DIType *T) { processType(T); }); } void DebugInfoFinder::processVariable(const DILocalVariable *DV) { @@ -389,6 +422,17 @@ bool DebugInfoFinder::addScope(DIScope *Scope) { return true; } +bool DebugInfoFinder::addMacro(DIMacro *Macro, DIMacroFile *MacroFile) { + if (!Macro) + return false; + + if (!NodesSeen.insert(Macro).second) + return false; + + Macros.push_back(std::make_pair(Macro, MacroFile)); + return true; +} + /// Recursively handle DILocations in followup metadata etc. /// /// TODO: If for example a followup loop metadata would reference itself this diff --git a/llvm/lib/IR/DebugInfoMetadata.cpp b/llvm/lib/IR/DebugInfoMetadata.cpp index 79b512d09822b..5db2c86aafc3d 100644 --- a/llvm/lib/IR/DebugInfoMetadata.cpp +++ b/llvm/lib/IR/DebugInfoMetadata.cpp @@ -1445,18 +1445,69 @@ bool DISubprogram::describes(const Function *F) const { return F->getSubprogram() == this; } +template +static ScopeT getRawRetainedNodeScopeInternal(NodeT *N) { + auto getScope = [](auto *N) { return N->getScope(); }; + + return DISubprogram::visitRetainedNode( + N, getScope, getScope, getScope, getScope, + [](auto *N) { return nullptr; }); +} + const DIScope *DISubprogram::getRawRetainedNodeScope(const MDNode *N) { - return visitRetainedNode( - N, [](const DILocalVariable *LV) { return LV->getScope(); }, - [](const DILabel *L) { return L->getScope(); }, - [](const DIImportedEntity *IE) { return IE->getScope(); }, - [](const Metadata *N) { return nullptr; }); + return getRawRetainedNodeScopeInternal(N); +} + +DIScope *DISubprogram::getRawRetainedNodeScope(MDNode *N) { + return getRawRetainedNodeScopeInternal(N); } const DILocalScope *DISubprogram::getRetainedNodeScope(const MDNode *N) { return cast(getRawRetainedNodeScope(N)); } +DILocalScope *DISubprogram::getRetainedNodeScope(MDNode *N) { + return cast(getRawRetainedNodeScope(N)); +} + +void DISubprogram::cleanupRetainedNodes() { + // Checks if a metadata node from retainedTypes is a type not belonging to + // this subprogram. + auto IsAlienType = [this](DINode *N) { + auto *T = dyn_cast_or_null(N); + if (!T) + return false; + + DISubprogram *TypeSP = nullptr; + // The type might have been global in the previously loaded IR modules. + if (auto *LS = dyn_cast_or_null(T->getScope())) + TypeSP = LS->getSubprogram(); + + return this != TypeSP; + }; + + // As this is expected to be called during module loading, before + // stripping old or incorrect debug info, perform minimal sanity check. + if (!isa_and_present(getRawRetainedNodes())) + return; + + MDTuple *RetainedNodes = cast(getRawRetainedNodes()); + SmallVector MDs; + MDs.reserve(RetainedNodes->getNumOperands()); + for (const MDOperand &Node : RetainedNodes->operands()) { + // Ignore malformed retainedNodes. + if (Node && !isa(Node)) + return; + + auto *N = cast_or_null(Node); + if (!IsAlienType(N)) + MDs.push_back(N); + } + + if (MDs.size() != RetainedNodes->getNumOperands()) + replaceRetainedNodes(MDNode::get(getContext(), MDs)); +} + DILexicalBlockBase::DILexicalBlockBase(LLVMContext &C, unsigned ID, StorageType Storage, ArrayRef Ops) diff --git a/llvm/lib/IR/Dominators.cpp b/llvm/lib/IR/Dominators.cpp index e1e88bb2aaff5..7bd1cef88dbaf 100644 --- a/llvm/lib/IR/Dominators.cpp +++ b/llvm/lib/IR/Dominators.cpp @@ -419,9 +419,7 @@ PreservedAnalyses DominatorTreeVerifierPass::run(Function &F, char DominatorTreeWrapperPass::ID = 0; -DominatorTreeWrapperPass::DominatorTreeWrapperPass() : FunctionPass(ID) { - initializeDominatorTreeWrapperPassPass(*PassRegistry::getPassRegistry()); -} +DominatorTreeWrapperPass::DominatorTreeWrapperPass() : FunctionPass(ID) {} INITIALIZE_PASS(DominatorTreeWrapperPass, "domtree", "Dominator Tree Construction", true, true) diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp index 467bd80d818fe..ef94c218edb27 100644 --- a/llvm/lib/IR/Function.cpp +++ b/llvm/lib/IR/Function.cpp @@ -803,31 +803,17 @@ void Function::addRangeRetAttr(const ConstantRange &CR) { } DenormalMode Function::getDenormalMode(const fltSemantics &FPType) const { - if (&FPType == &APFloat::IEEEsingle()) { - DenormalMode Mode = getDenormalModeF32Raw(); - // If the f32 variant of the attribute isn't specified, try to use the - // generic one. - if (Mode.isValid()) - return Mode; - } - - return getDenormalModeRaw(); -} + Attribute Attr = getFnAttribute(Attribute::DenormalFPEnv); + if (!Attr.isValid()) + return DenormalMode::getDefault(); -DenormalMode Function::getDenormalModeRaw() const { - Attribute Attr = getFnAttribute("denormal-fp-math"); - StringRef Val = Attr.getValueAsString(); - return parseDenormalFPAttribute(Val); + DenormalFPEnv FPEnv = Attr.getDenormalFPEnv(); + return &FPType == &APFloat::IEEEsingle() ? FPEnv.F32Mode : FPEnv.DefaultMode; } -DenormalMode Function::getDenormalModeF32Raw() const { - Attribute Attr = getFnAttribute("denormal-fp-math-f32"); - if (Attr.isValid()) { - StringRef Val = Attr.getValueAsString(); - return parseDenormalFPAttribute(Val); - } - - return DenormalMode::getInvalid(); +DenormalFPEnv Function::getDenormalFPEnv() const { + Attribute Attr = getFnAttribute(Attribute::DenormalFPEnv); + return Attr.isValid() ? Attr.getDenormalFPEnv() : DenormalFPEnv::getDefault(); } const std::string &Function::getGC() const { diff --git a/llvm/lib/IR/IRBuilder.cpp b/llvm/lib/IR/IRBuilder.cpp index c87fd1b444c0e..fb282441b9082 100644 --- a/llvm/lib/IR/IRBuilder.cpp +++ b/llvm/lib/IR/IRBuilder.cpp @@ -103,6 +103,79 @@ Value *IRBuilderBase::CreateAggregateCast(Value *V, Type *DestTy) { return CreateBitOrPointerCast(V, DestTy); } +Value *IRBuilderBase::CreateBitPreservingCastChain(const DataLayout &DL, + Value *V, Type *NewTy) { + Type *OldTy = V->getType(); + + if (OldTy == NewTy) + return V; + + assert(!(isa(OldTy) && isa(NewTy)) && + "Integer types must be the exact same to convert."); + + // A variant of bitcast that supports a mixture of fixed and scalable types + // that are know to have the same size. + auto CreateBitCastLike = [this](Value *In, Type *Ty) -> Value * { + Type *InTy = In->getType(); + if (InTy == Ty) + return In; + + if (isa(InTy) && isa(Ty)) { + // For vscale_range(2) expand <4 x i32> to --> + // <4 x i32> to to + auto *VTy = VectorType::getWithSizeAndScalar(cast(Ty), InTy); + return CreateBitCast( + CreateInsertVector(VTy, PoisonValue::get(VTy), In, getInt64(0)), Ty); + } + + if (isa(InTy) && isa(Ty)) { + // For vscale_range(2) expand to <4 x i32> --> + // to to <4 x i32> + auto *VTy = VectorType::getWithSizeAndScalar(cast(InTy), Ty); + return CreateExtractVector(Ty, CreateBitCast(In, VTy), getInt64(0)); + } + + return CreateBitCast(In, Ty); + }; + + // See if we need inttoptr for this type pair. May require additional bitcast. + if (OldTy->isIntOrIntVectorTy() && NewTy->isPtrOrPtrVectorTy()) { + // Expand <2 x i32> to i8* --> <2 x i32> to i64 to i8* + // Expand i128 to <2 x i8*> --> i128 to <2 x i64> to <2 x i8*> + // Expand <4 x i32> to <2 x i8*> --> <4 x i32> to <2 x i64> to <2 x i8*> + // Directly handle i64 to i8* + return CreateIntToPtr(CreateBitCastLike(V, DL.getIntPtrType(NewTy)), NewTy); + } + + // See if we need ptrtoint for this type pair. May require additional bitcast. + if (OldTy->isPtrOrPtrVectorTy() && NewTy->isIntOrIntVectorTy()) { + // Expand <2 x i8*> to i128 --> <2 x i8*> to <2 x i64> to i128 + // Expand i8* to <2 x i32> --> i8* to i64 to <2 x i32> + // Expand <2 x i8*> to <4 x i32> --> <2 x i8*> to <2 x i64> to <4 x i32> + // Expand i8* to i64 --> i8* to i64 to i64 + return CreateBitCastLike(CreatePtrToInt(V, DL.getIntPtrType(OldTy)), NewTy); + } + + if (OldTy->isPtrOrPtrVectorTy() && NewTy->isPtrOrPtrVectorTy()) { + unsigned OldAS = OldTy->getPointerAddressSpace(); + unsigned NewAS = NewTy->getPointerAddressSpace(); + // To convert pointers with different address spaces (they are already + // checked convertible, i.e. they have the same pointer size), so far we + // cannot use `bitcast` (which has restrict on the same address space) or + // `addrspacecast` (which is not always no-op casting). Instead, use a pair + // of no-op `ptrtoint`/`inttoptr` casts through an integer with the same bit + // size. + if (OldAS != NewAS) { + return CreateIntToPtr( + CreateBitCastLike(CreatePtrToInt(V, DL.getIntPtrType(OldTy)), + DL.getIntPtrType(NewTy)), + NewTy); + } + } + + return CreateBitCastLike(V, NewTy); +} + CallInst * IRBuilderBase::createCallHelper(Function *Callee, ArrayRef Ops, const Twine &Name, FMFSource FMFSource, diff --git a/llvm/lib/IR/Intrinsics.cpp b/llvm/lib/IR/Intrinsics.cpp index 48abead0929dd..186bd1edb8c52 100644 --- a/llvm/lib/IR/Intrinsics.cpp +++ b/llvm/lib/IR/Intrinsics.cpp @@ -40,7 +40,6 @@ using namespace llvm; /// Table of string intrinsic names indexed by enum value. #define GET_INTRINSIC_NAME_TABLE #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_INTRINSIC_NAME_TABLE StringRef Intrinsic::getBaseName(ID id) { assert(id < num_intrinsics && "Invalid intrinsic ID!"); @@ -196,7 +195,6 @@ std::string Intrinsic::getNameNoUnnamedTypes(ID Id, ArrayRef Tys) { enum IIT_Info { #define GET_INTRINSIC_IITINFO #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_INTRINSIC_IITINFO }; static void @@ -434,34 +432,43 @@ DecodeIITType(unsigned &NextElt, ArrayRef Infos, #define GET_INTRINSIC_GENERATOR_GLOBAL #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_INTRINSIC_GENERATOR_GLOBAL void Intrinsic::getIntrinsicInfoTableEntries( ID id, SmallVectorImpl &T) { - static_assert(sizeof(IIT_Table[0]) == 2, - "Expect 16-bit entries in IIT_Table"); - // Check to see if the intrinsic's type was expressible by the table. - uint16_t TableVal = IIT_Table[id - 1]; + // Note that `FixedEncodingTy` is defined in IntrinsicImpl.inc and can be + // uint16_t or uint32_t based on the the value of `Use16BitFixedEncoding` in + // IntrinsicEmitter.cpp. + constexpr unsigned FixedEncodingBits = sizeof(FixedEncodingTy) * CHAR_BIT; + constexpr unsigned MSBPosition = FixedEncodingBits - 1; + // Mask with all bits 1 except the most significant bit. + constexpr unsigned Mask = (1U << MSBPosition) - 1; + + FixedEncodingTy TableVal = IIT_Table[id - 1]; + + // Array to hold the inlined fixed encoding values expanded from nibbles to + // bytes. Its size can be be atmost FixedEncodingBits / 4 i.e., number + // of nibbles that can fit in `FixedEncodingTy`. + unsigned char IITValues[FixedEncodingBits / 4]; - // Decode the TableVal into an array of IITValues. - SmallVector IITValues; ArrayRef IITEntries; unsigned NextElt = 0; - if (TableVal >> 15) { + // Check to see if the intrinsic's type was inlined in the fixed encoding + // table. + if (TableVal >> MSBPosition) { // This is an offset into the IIT_LongEncodingTable. IITEntries = IIT_LongEncodingTable; // Strip sentinel bit. - NextElt = TableVal & 0x7fff; + NextElt = TableVal & Mask; } else { // If the entry was encoded into a single word in the table itself, decode // it from an array of nibbles to an array of bytes. do { - IITValues.push_back(TableVal & 0xF); + IITValues[NextElt++] = TableVal & 0xF; TableVal >>= 4; } while (TableVal); - IITEntries = IITValues; + IITEntries = ArrayRef(IITValues).take_front(NextElt); NextElt = 0; } @@ -599,19 +606,16 @@ FunctionType *Intrinsic::getType(LLVMContext &Context, ID id, bool Intrinsic::isOverloaded(ID id) { #define GET_INTRINSIC_OVERLOAD_TABLE #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_INTRINSIC_OVERLOAD_TABLE } bool Intrinsic::hasPrettyPrintedArgs(ID id){ #define GET_INTRINSIC_PRETTY_PRINT_TABLE #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_INTRINSIC_PRETTY_PRINT_TABLE } /// Table of per-target intrinsic name tables. #define GET_INTRINSIC_TARGET_DATA #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_INTRINSIC_TARGET_DATA bool Intrinsic::isTargetIntrinsic(Intrinsic::ID IID) { return IID > TargetInfos[0].Count; @@ -725,7 +729,6 @@ Intrinsic::ID Intrinsic::lookupIntrinsicID(StringRef Name) { /// This defines the "Intrinsic::getAttributes(ID id)" method. #define GET_INTRINSIC_ATTRIBUTES #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_INTRINSIC_ATTRIBUTES static Function *getOrInsertIntrinsicDeclarationImpl(Module *M, Intrinsic::ID id, @@ -802,12 +805,10 @@ Function *Intrinsic::getDeclarationIfExists(Module *M, ID id, // This defines the "Intrinsic::getIntrinsicForClangBuiltin()" method. #define GET_LLVM_INTRINSIC_FOR_CLANG_BUILTIN #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_LLVM_INTRINSIC_FOR_CLANG_BUILTIN // This defines the "Intrinsic::getIntrinsicForMSBuiltin()" method. #define GET_LLVM_INTRINSIC_FOR_MS_BUILTIN #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_LLVM_INTRINSIC_FOR_MS_BUILTIN bool Intrinsic::isConstrainedFPIntrinsic(ID QID) { switch (QID) { @@ -1194,4 +1195,3 @@ Intrinsic::ID Intrinsic::getDeinterleaveIntrinsicID(unsigned Factor) { #define GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS #include "llvm/IR/IntrinsicImpl.inc" -#undef GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS diff --git a/llvm/lib/IR/ProfDataUtils.cpp b/llvm/lib/IR/ProfDataUtils.cpp index 15cb7f9b2927f..00410a74f20a9 100644 --- a/llvm/lib/IR/ProfDataUtils.cpp +++ b/llvm/lib/IR/ProfDataUtils.cpp @@ -289,6 +289,18 @@ void llvm::setExplicitlyUnknownBranchWeightsIfProfiled(Instruction &I, setExplicitlyUnknownBranchWeights(I, PassName); } +MDNode *llvm::getExplicitlyUnknownBranchWeightsIfProfiled(Function &F, + StringRef PassName) { + if (std::optional EC = F.getEntryCount(); + !EC || EC->getCount() == 0) + return nullptr; + MDBuilder MDB(F.getContext()); + return MDNode::get( + F.getContext(), + {MDB.createString(MDProfLabels::UnknownBranchWeightsMarker), + MDB.createString(PassName)}); +} + void llvm::setExplicitlyUnknownFunctionEntryCount(Function &F, StringRef PassName) { MDBuilder MDB(F.getContext()); diff --git a/llvm/lib/IR/SafepointIRVerifier.cpp b/llvm/lib/IR/SafepointIRVerifier.cpp index e35b5b30a7cc1..d3dba17de2b0e 100644 --- a/llvm/lib/IR/SafepointIRVerifier.cpp +++ b/llvm/lib/IR/SafepointIRVerifier.cpp @@ -209,9 +209,7 @@ namespace { struct SafepointIRVerifier : public FunctionPass { static char ID; // Pass identification, replacement for typeid - SafepointIRVerifier() : FunctionPass(ID) { - initializeSafepointIRVerifierPass(*PassRegistry::getPassRegistry()); - } + SafepointIRVerifier() : FunctionPass(ID) {} bool runOnFunction(Function &F) override { auto &DT = getAnalysis().getDomTree(); diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 3d44d1317ecc7..3f0f6c127b456 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -1623,11 +1623,11 @@ void Verifier::visitDISubprogram(const DISubprogram &N) { auto True = [](const Metadata *) { return true; }; auto False = [](const Metadata *) { return false; }; - bool IsTypeCorrect = - DISubprogram::visitRetainedNode(Op, True, True, True, False); + bool IsTypeCorrect = DISubprogram::visitRetainedNode( + Op, True, True, True, True, False); CheckDI(IsTypeCorrect, - "invalid retained nodes, expected DILocalVariable, DILabel or " - "DIImportedEntity", + "invalid retained nodes, expected DILocalVariable, DILabel, " + "DIImportedEntity or DIType", &N, Node, Op); auto *RetainedNode = cast(Op); @@ -1636,10 +1636,15 @@ void Verifier::visitDISubprogram(const DISubprogram &N) { CheckDI(RetainedNodeScope, "invalid retained nodes, retained node is not local", &N, Node, RetainedNode); + + DISubprogram *RetainedNodeSP = RetainedNodeScope->getSubprogram(); + DICompileUnit *RetainedNodeUnit = + RetainedNodeSP ? RetainedNodeSP->getUnit() : nullptr; CheckDI( - RetainedNodeScope->getSubprogram() == &N, + RetainedNodeSP == &N, "invalid retained nodes, retained node does not belong to subprogram", - &N, Node, RetainedNode, RetainedNodeScope); + &N, Node, RetainedNode, RetainedNodeScope, RetainedNodeSP, + RetainedNodeUnit); } } CheckDI(!hasConflictingReferenceFlags(N.getFlags()), @@ -2620,19 +2625,6 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT, AttributeList Attrs, CheckFailed("invalid name for a VFABI variant: " + S, V); } - if (auto A = Attrs.getFnAttr("denormal-fp-math"); A.isValid()) { - StringRef S = A.getValueAsString(); - if (!parseDenormalFPAttribute(S).isValid()) - CheckFailed("invalid value for 'denormal-fp-math' attribute: " + S, V); - } - - if (auto A = Attrs.getFnAttr("denormal-fp-math-f32"); A.isValid()) { - StringRef S = A.getValueAsString(); - if (!parseDenormalFPAttribute(S).isValid()) - CheckFailed("invalid value for 'denormal-fp-math-f32' attribute: " + S, - V); - } - if (auto A = Attrs.getFnAttr("modular-format"); A.isValid()) { StringRef S = A.getValueAsString(); SmallVector Args; @@ -3905,6 +3897,9 @@ void Verifier::visitCallBase(CallBase &Call) { "llvm.call.preallocated.arg"); } + Check(!Attrs.hasFnAttr(Attribute::DenormalFPEnv), + "denormal_fpenv attribute may not apply to call sites", Call); + // Verify call attributes. verifyFunctionAttrs(FTy, Attrs, &Call, IsIntrinsic, Call.isInlineAsm()); @@ -7207,6 +7202,13 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) { &Call); break; } + case Intrinsic::sponentry: { + const unsigned StackAS = DL.getAllocaAddrSpace(); + const Type *RetTy = Call.getFunctionType()->getReturnType(); + Check(RetTy->getPointerAddressSpace() == StackAS, + "llvm.sponentry must return a pointer to the stack", &Call); + break; + } }; // Verify that there aren't any unmediated control transfers between funclets. @@ -7907,14 +7909,9 @@ struct VerifierLegacyPass : public FunctionPass { std::unique_ptr V; bool FatalErrors = true; - VerifierLegacyPass() : FunctionPass(ID) { - initializeVerifierLegacyPassPass(*PassRegistry::getPassRegistry()); - } + VerifierLegacyPass() : FunctionPass(ID) {} explicit VerifierLegacyPass(bool FatalErrors) - : FunctionPass(ID), - FatalErrors(FatalErrors) { - initializeVerifierLegacyPassPass(*PassRegistry::getPassRegistry()); - } + : FunctionPass(ID), FatalErrors(FatalErrors) {} bool doInitialization(Module &M) override { V = std::make_unique( diff --git a/llvm/lib/LTO/LTOModule.cpp b/llvm/lib/LTO/LTOModule.cpp index 9d5b0f54f7f21..e821abb6f65bc 100644 --- a/llvm/lib/LTO/LTOModule.cpp +++ b/llvm/lib/LTO/LTOModule.cpp @@ -401,7 +401,7 @@ void LTOModule::addDefinedFunctionSymbol(ModuleSymbolTable::Symbol Sym) { } auto *GV = cast(Sym); - assert((isa(GV) || + assert((isa(GV) || isa(GV) || (isa(GV) && isa(cast(GV)->getAliasee()))) && "Not function or function alias"); @@ -611,6 +611,11 @@ void LTOModule::parseSymbols() { continue; } + if (getTargetTriple().isOSBinFormatXCOFF() && isa(GV)) { + addDefinedFunctionSymbol(Sym); + continue; + } + assert(isa(GV)); if (isa(cast(GV)->getAliasee())) diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp index 35f442a55f8cc..0e3c1f8c465c2 100644 --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -1902,8 +1902,7 @@ struct CIEKey { } // end anonymous namespace -void MCDwarfFrameEmitter::Emit(MCObjectStreamer &Streamer, MCAsmBackend *MAB, - bool IsEH) { +void MCDwarfFrameEmitter::emit(MCObjectStreamer &Streamer, bool IsEH) { MCContext &Context = Streamer.getContext(); const MCObjectFileInfo *MOFI = Context.getObjectFileInfo(); const MCAsmInfo *AsmInfo = Context.getAsmInfo(); @@ -1913,7 +1912,7 @@ void MCDwarfFrameEmitter::Emit(MCObjectStreamer &Streamer, MCAsmBackend *MAB, // Emit the compact unwind info if available. bool NeedsEHFrameSection = !MOFI->getSupportsCompactUnwindWithoutEHFrame(); if (IsEH && MOFI->getCompactUnwindSection()) { - Streamer.generateCompactUnwindEncodings(MAB); + Streamer.generateCompactUnwindEncodings(); bool SectionEmitted = false; for (const MCDwarfFrameInfo &Frame : FrameArray) { if (Frame.CompactUnwindEncoding == 0) continue; diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp b/llvm/lib/MC/MCObjectFileInfo.cpp index 5afe00eee2242..f2917179e1fc1 100644 --- a/llvm/lib/MC/MCObjectFileInfo.cpp +++ b/llvm/lib/MC/MCObjectFileInfo.cpp @@ -10,6 +10,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/BinaryFormat/COFF.h" #include "llvm/BinaryFormat/ELF.h" +#include "llvm/BinaryFormat/GOFF.h" #include "llvm/BinaryFormat/SFrame.h" #include "llvm/BinaryFormat/Wasm.h" #include "llvm/MC/MCAsmInfo.h" @@ -24,6 +25,7 @@ #include "llvm/MC/MCSectionSPIRV.h" #include "llvm/MC/MCSectionWasm.h" #include "llvm/MC/MCSectionXCOFF.h" +#include "llvm/MC/MCSymbolGOFF.h" #include "llvm/TargetParser/Triple.h" using namespace llvm; @@ -608,6 +610,65 @@ void MCObjectFileInfo::initGOFFMCObjectFileInfo(const Triple &T) { GOFF::ESD_LB_NoLoad, GOFF::ESD_RQ_0, GOFF::ESD_ALIGN_Doubleword, 0}, RootSDSection); + + // Debug Info Sections. The ED name is the same used by the XL compiler. + auto InitDebugSection = [this, + RootSDSection](StringRef EDName, + StringRef LDName) -> MCSectionGOFF * { + MCSectionGOFF *ED = Ctx->getGOFFSection( + SectionKind::getMetadata(), EDName, + GOFF::EDAttr{false, GOFF::ESD_RMODE_64, GOFF::ESD_NS_Parts, + GOFF::ESD_TS_ByteOriented, GOFF::ESD_BA_Concatenate, + GOFF::ESD_LB_NoLoad, GOFF::ESD_RQ_0, + GOFF::ESD_ALIGN_Doubleword, 0}, + RootSDSection); + // At least for llc, this function is called twice! (See function + // compileModule() in llc.cpp). Since the context is not cleared, the + // already allocated section is returned above. We only add the begin symbol + // if it is not yet set to avoid an assertion. + MCSymbolGOFF *LD = static_cast(ED->getBeginSymbol()); + if (!LD) { + LD = static_cast(getContext().getOrCreateSymbol(LDName)); + LD->setCodeData(GOFF::ESD_EXE_DATA); + LD->setWeak(false); + LD->setLinkage(GOFF::ESD_LT_XPLink); + LD->setExternal(false); + ED->setBeginSymbol(LD); + } else + assert(LD->getName() == LDName && "Wrong label name"); + return ED; + }; + DwarfAbbrevSection = InitDebugSection("D_ABREV", ".debug_abbrev"); + DwarfInfoSection = InitDebugSection("D_INFO", ".debug_info"); + DwarfLineSection = InitDebugSection("D_LINE", ".debug_line"); + DwarfFrameSection = InitDebugSection("D_FRAME", ".debug_frame"); + DwarfPubNamesSection = InitDebugSection("D_PBNMS", ".debug_pubnames"); + DwarfPubTypesSection = InitDebugSection("D_PTYPES", ".debug_pubtypes"); + DwarfStrSection = InitDebugSection("D_STR", ".debug_str"); + DwarfLocSection = InitDebugSection("D_LOC", ".debug_loc"); + DwarfARangesSection = InitDebugSection("D_ARNGE", ".debug_aranges"); + DwarfRangesSection = InitDebugSection("D_RNGES", ".debug_ranges"); + DwarfMacinfoSection = InitDebugSection("D_MACIN", ".debug_macinfo"); + + // DWARF 5 sections. + DwarfDebugNamesSection = InitDebugSection("D_NAMES", ".debug_names"); + DwarfStrOffSection = InitDebugSection("D_STROFFS", ".debug_str_offsets"); + DwarfAddrSection = InitDebugSection("D_ADDR", ".debug_addr"); + DwarfRnglistsSection = InitDebugSection("D_RNGLISTS", ".debug_rnglists"); + DwarfLoclistsSection = InitDebugSection("D_LOCLISTS", ".debug_loclists"); + DwarfLineStrSection = InitDebugSection("D_LINESTR", ".debug_line_str"); + + // Special GNU sections. + DwarfGnuPubNamesSection = InitDebugSection("D_GPBNMS", ".debug_gnu_pubnames"); + DwarfGnuPubTypesSection = + InitDebugSection("D_GPTYPES", ".debug_gnu_pubtypes"); + + // Accelerator Tables. + DwarfAccelNamesSection = InitDebugSection("D_APPLNMS", ".apple_names"); + DwarfAccelNamespaceSection = + InitDebugSection("D_APPLNMSP", ".apple_namespaces"); + DwarfAccelTypesSection = InitDebugSection("D_APPLTYPS", ".apple_types"); + DwarfAccelObjCSection = InitDebugSection("D_APPLOBJC", ".apple_objc"); } void MCObjectFileInfo::initCOFFMCObjectFileInfo(const Triple &T) { diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp index 039e339878b5e..453d4d20d9727 100644 --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -181,16 +181,21 @@ void MCObjectStreamer::reset() { MCStreamer::reset(); } +void MCObjectStreamer::generateCompactUnwindEncodings() { + auto &Backend = getAssembler().getBackend(); + for (auto &FI : DwarfFrameInfos) + FI.CompactUnwindEncoding = + Backend.generateCompactUnwindEncoding(&FI, &getContext()); +} + void MCObjectStreamer::emitFrames() { if (!getNumFrameInfos()) return; - auto *MAB = &getAssembler().getBackend(); if (EmitEHFrame) - MCDwarfFrameEmitter::Emit(*this, MAB, true); - + MCDwarfFrameEmitter::emit(*this, true); if (EmitDebugFrame) - MCDwarfFrameEmitter::Emit(*this, MAB, false); + MCDwarfFrameEmitter::emit(*this, false); if (EmitSFrame || (getContext().getTargetOptions() && getContext().getTargetOptions()->EmitSFrameUnwind)) diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp index b1eb1a4a6ca8e..5c7ebcf6b66e4 100644 --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -13,7 +13,6 @@ #include "llvm/BinaryFormat/COFF.h" #include "llvm/BinaryFormat/MachO.h" #include "llvm/DebugInfo/CodeView/SymbolRecord.h" -#include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCCodeView.h" #include "llvm/MC/MCContext.h" @@ -121,12 +120,6 @@ void MCStreamer::emitRawComment(const Twine &T, bool TabPrefix) {} void MCStreamer::addExplicitComment(const Twine &T) {} void MCStreamer::emitExplicitComments() {} -void MCStreamer::generateCompactUnwindEncodings(MCAsmBackend *MAB) { - for (auto &FI : DwarfFrameInfos) - FI.CompactUnwindEncoding = - (MAB ? MAB->generateCompactUnwindEncoding(&FI, &Context) : 0); -} - /// EmitIntValue - Special case of EmitValue that avoids the client having to /// pass in a MCExpr for constant integers. void MCStreamer::emitIntValue(uint64_t Value, unsigned Size) { diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp index 89a08327dd259..7ad6c76978793 100644 --- a/llvm/lib/MC/MCSubtargetInfo.cpp +++ b/llvm/lib/MC/MCSubtargetInfo.cpp @@ -259,24 +259,24 @@ MCSubtargetInfo::MCSubtargetInfo( InitMCProcessorInfo(CPU, TuneCPU, FS); } -FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) { +const FeatureBitset &MCSubtargetInfo::ToggleFeature(uint64_t FB) { FeatureBits.flip(FB); return FeatureBits; } -FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) { +const FeatureBitset &MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) { FeatureBits ^= FB; return FeatureBits; } -FeatureBitset MCSubtargetInfo::SetFeatureBitsTransitively( - const FeatureBitset &FB) { +const FeatureBitset & +MCSubtargetInfo::SetFeatureBitsTransitively(const FeatureBitset &FB) { SetImpliedBits(FeatureBits, FB, ProcFeatures); return FeatureBits; } -FeatureBitset MCSubtargetInfo::ClearFeatureBitsTransitively( - const FeatureBitset &FB) { +const FeatureBitset & +MCSubtargetInfo::ClearFeatureBitsTransitively(const FeatureBitset &FB) { for (unsigned I = 0, E = FB.size(); I < E; I++) { if (FB[I]) { FeatureBits.reset(I); @@ -286,7 +286,7 @@ FeatureBitset MCSubtargetInfo::ClearFeatureBitsTransitively( return FeatureBits; } -FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef Feature) { +const FeatureBitset &MCSubtargetInfo::ToggleFeature(StringRef Feature) { // Find feature in table. const SubtargetFeatureKV *FeatureEntry = Find(SubtargetFeatures::StripFlag(Feature), ProcFeatures); @@ -311,7 +311,7 @@ FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef Feature) { return FeatureBits; } -FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) { +const FeatureBitset &MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) { ::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures); return FeatureBits; } diff --git a/llvm/lib/MC/MCWasmStreamer.cpp b/llvm/lib/MC/MCWasmStreamer.cpp index 1d3cf38d4bfdb..8b4ae4cee3e79 100644 --- a/llvm/lib/MC/MCWasmStreamer.cpp +++ b/llvm/lib/MC/MCWasmStreamer.cpp @@ -14,6 +14,7 @@ #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCObjectStreamer.h" @@ -129,7 +130,9 @@ bool MCWasmStreamer::emitSymbolAttribute(MCSymbol *S, MCSymbolAttr Attribute) { void MCWasmStreamer::emitCommonSymbol(MCSymbol *S, uint64_t Size, Align ByteAlignment) { - llvm_unreachable("Common symbols are not yet implemented for Wasm"); + getContext().reportError(getStartTokLoc(), + "common symbols are not yet implemented for Wasm: " + + S->getName()); } void MCWasmStreamer::emitELFSize(MCSymbol *Symbol, const MCExpr *Value) { @@ -138,7 +141,10 @@ void MCWasmStreamer::emitELFSize(MCSymbol *Symbol, const MCExpr *Value) { void MCWasmStreamer::emitLocalCommonSymbol(MCSymbol *S, uint64_t Size, Align ByteAlignment) { - llvm_unreachable("Local common symbols are not yet implemented for Wasm"); + getContext().reportError(getStartTokLoc(), + "local common symbols are not yet implemented " + "for Wasm: " + + S->getName()); } void MCWasmStreamer::emitIdent(StringRef IdentString) { diff --git a/llvm/lib/MC/MCXCOFFStreamer.cpp b/llvm/lib/MC/MCXCOFFStreamer.cpp index 4bf14c11068cb..b459b26045ae7 100644 --- a/llvm/lib/MC/MCXCOFFStreamer.cpp +++ b/llvm/lib/MC/MCXCOFFStreamer.cpp @@ -45,8 +45,12 @@ void MCXCOFFStreamer::changeSection(MCSection *Section, uint32_t Subsection) { // sections because we don't have other cases that hit this problem yet. // if (IsDwarfSec || CsectProp->MappingClass == XCOFF::XMC_PR) // QualName->setFragment(F); - if (Sec->isDwarfSect() || Sec->getMappingClass() == XCOFF::XMC_PR) - Sec->getQualNameSymbol()->setFragment(CurFrag); + if (Sec->isDwarfSect() || Sec->getMappingClass() == XCOFF::XMC_PR) { + MCSymbol *QualNameSymbol = Sec->getQualNameSymbol(); + // Only set the fragment the first time we're switching to the section. + if (!QualNameSymbol->isInSection()) + QualNameSymbol->setFragment(CurFrag); + } } bool MCXCOFFStreamer::emitSymbolAttribute(MCSymbol *Sym, diff --git a/llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp b/llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp index faf5b0fa56539..8ced4ed327833 100644 --- a/llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp +++ b/llvm/lib/ObjCopy/wasm/WasmObjcopy.cpp @@ -25,16 +25,9 @@ static bool isDebugSection(const Section &Sec) { return Sec.Name.starts_with(".debug") || Sec.Name.starts_with("reloc..debug"); } -static bool isLinkerSection(const Section &Sec) { - return Sec.Name.starts_with("reloc.") || Sec.Name == "linking"; -} - -static bool isNameSection(const Section &Sec) { return Sec.Name == "name"; } - -// Sections which are known to be "comments" or informational and do not affect -// program semantics. -static bool isCommentSection(const Section &Sec) { - return Sec.Name == "producers"; +static bool isEngineInterpretedSection(const Section &Sec) { + return Sec.SectionType != llvm::wasm::WASM_SEC_CUSTOM || + Sec.Name.starts_with("metadata.code."); } static Error dumpSectionToFile(StringRef SecName, StringRef Filename, @@ -75,8 +68,7 @@ static void removeSections(const CommonConfig &Config, Object &Obj) { if (Config.StripAll) { RemovePred = [RemovePred](const Section &Sec) { - return RemovePred(Sec) || isDebugSection(Sec) || isLinkerSection(Sec) || - isNameSection(Sec) || isCommentSection(Sec); + return RemovePred(Sec) || !isEngineInterpretedSection(Sec); }; } diff --git a/llvm/lib/Object/Binary.cpp b/llvm/lib/Object/Binary.cpp index da2a7bb0a19da..30414257fa90b 100644 --- a/llvm/lib/Object/Binary.cpp +++ b/llvm/lib/Object/Binary.cpp @@ -93,8 +93,12 @@ Expected> object::createBinary(MemoryBufferRef Buffer, case file_magic::spirv_object: // Unrecognized object file format. return errorCodeToError(object_error::invalid_file_type); - case file_magic::offload_binary: - return OffloadBinary::create(Buffer); + case file_magic::offload_binary: { + auto OffloadBinaryOrErr = OffloadBinary::create(Buffer); + if (!OffloadBinaryOrErr) + return OffloadBinaryOrErr.takeError(); + return std::move((*OffloadBinaryOrErr)[0]); + } case file_magic::minidump: return MinidumpFile::create(Buffer); case file_magic::tapi_file: diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp index 5bdb4a9262a1b..4d495e7a77e9e 100644 --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -595,6 +595,8 @@ StringRef ELFObjectFileBase::getAMDGPUCPUName() const { return "gfx1152"; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153: return "gfx1153"; + case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170: + return "gfx1170"; // AMDGCN GFX12. case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: diff --git a/llvm/lib/Object/OffloadBinary.cpp b/llvm/lib/Object/OffloadBinary.cpp index ef93bf1e9bfa7..79c1e42392920 100644 --- a/llvm/lib/Object/OffloadBinary.cpp +++ b/llvm/lib/Object/OffloadBinary.cpp @@ -28,6 +28,26 @@ using namespace llvm::object; namespace { +/// A MemoryBuffer that shares ownership of the underlying memory. +/// This allows multiple OffloadBinary instances to share the same buffer. +class SharedMemoryBuffer : public MemoryBuffer { +public: + SharedMemoryBuffer(std::shared_ptr Buf) + : SharedBuf(std::move(Buf)) { + init(SharedBuf->getBufferStart(), SharedBuf->getBufferEnd(), + /*RequiresNullTerminator=*/false); + } + + BufferKind getBufferKind() const override { return MemoryBuffer_Malloc; } + + StringRef getBufferIdentifier() const override { + return SharedBuf->getBufferIdentifier(); + } + +private: + const std::shared_ptr SharedBuf; +}; + /// Attempts to extract all the embedded device images contained inside the /// buffer \p Contents. The buffer is expected to contain a valid offloading /// binary format. @@ -35,7 +55,7 @@ Error extractOffloadFiles(MemoryBufferRef Contents, SmallVectorImpl &Binaries) { uint64_t Offset = 0; // There could be multiple offloading binaries stored at this section. - while (Offset < Contents.getBuffer().size()) { + while (Offset < Contents.getBufferSize()) { std::unique_ptr Buffer = MemoryBuffer::getMemBuffer(Contents.getBuffer().drop_front(Offset), "", /*RequiresNullTerminator*/ false); @@ -43,21 +63,32 @@ Error extractOffloadFiles(MemoryBufferRef Contents, Buffer->getBufferStart())) Buffer = MemoryBuffer::getMemBufferCopy(Buffer->getBuffer(), Buffer->getBufferIdentifier()); - auto BinaryOrErr = OffloadBinary::create(*Buffer); - if (!BinaryOrErr) - return BinaryOrErr.takeError(); - OffloadBinary &Binary = **BinaryOrErr; - // Create a new owned binary with a copy of the original memory. + auto HeaderOrErr = OffloadBinary::extractHeader(*Buffer); + if (!HeaderOrErr) + return HeaderOrErr.takeError(); + const OffloadBinary::Header *Header = *HeaderOrErr; + + // Create a copy of original memory containing only the current binary. std::unique_ptr BufferCopy = MemoryBuffer::getMemBufferCopy( - Binary.getData().take_front(Binary.getSize()), + Buffer->getBuffer().take_front(Header->Size), Contents.getBufferIdentifier()); - auto NewBinaryOrErr = OffloadBinary::create(*BufferCopy); - if (!NewBinaryOrErr) - return NewBinaryOrErr.takeError(); - Binaries.emplace_back(std::move(*NewBinaryOrErr), std::move(BufferCopy)); - Offset += Binary.getSize(); + auto BinariesOrErr = OffloadBinary::create(*BufferCopy); + if (!BinariesOrErr) + return BinariesOrErr.takeError(); + + // Share ownership among multiple OffloadFiles. + std::shared_ptr SharedBuffer = + std::shared_ptr(std::move(BufferCopy)); + + for (auto &Binary : *BinariesOrErr) { + std::unique_ptr SharedBufferPtr = + std::make_unique(SharedBuffer); + Binaries.emplace_back(std::move(Binary), std::move(SharedBufferPtr)); + } + + Offset += Header->Size; } return Error::success(); @@ -167,8 +198,8 @@ Error extractFromArchive(const Archive &Library, } // namespace -Expected> -OffloadBinary::create(MemoryBufferRef Buf) { +Expected +OffloadBinary::extractHeader(MemoryBufferRef Buf) { if (Buf.getBufferSize() < sizeof(Header) + sizeof(Entry)) return errorCodeToError(object_error::parse_failed); @@ -182,83 +213,146 @@ OffloadBinary::create(MemoryBufferRef Buf) { const char *Start = Buf.getBufferStart(); const Header *TheHeader = reinterpret_cast(Start); - if (TheHeader->Version != OffloadBinary::Version) + if (TheHeader->Version == 0 || TheHeader->Version > OffloadBinary::Version) return errorCodeToError(object_error::parse_failed); if (TheHeader->Size > Buf.getBufferSize() || TheHeader->Size < sizeof(Entry) || TheHeader->Size < sizeof(Header)) return errorCodeToError(object_error::unexpected_eof); - if (TheHeader->EntryOffset > TheHeader->Size - sizeof(Entry) || - TheHeader->EntrySize > TheHeader->Size - sizeof(Header)) + uint64_t EntriesCount = + (TheHeader->Version == 1) ? 1 : TheHeader->EntriesCount; + uint64_t EntriesSize = sizeof(Entry) * EntriesCount; + if (TheHeader->EntriesOffset > TheHeader->Size - EntriesSize || + EntriesSize > TheHeader->Size - sizeof(Header)) return errorCodeToError(object_error::unexpected_eof); - const Entry *TheEntry = - reinterpret_cast(&Start[TheHeader->EntryOffset]); + return TheHeader; +} + +Expected>> +OffloadBinary::create(MemoryBufferRef Buf, std::optional Index) { + auto HeaderOrErr = OffloadBinary::extractHeader(Buf); + if (!HeaderOrErr) + return HeaderOrErr.takeError(); + const Header *TheHeader = *HeaderOrErr; - if (TheEntry->ImageOffset > Buf.getBufferSize() || - TheEntry->StringOffset > Buf.getBufferSize() || - TheEntry->StringOffset + TheEntry->NumStrings * sizeof(StringEntry) > - Buf.getBufferSize()) - return errorCodeToError(object_error::unexpected_eof); + const char *Start = Buf.getBufferStart(); + const Entry *Entries = + reinterpret_cast(&Start[TheHeader->EntriesOffset]); + + auto validateEntry = [&](const Entry *TheEntry) -> Error { + if (TheEntry->ImageOffset > Buf.getBufferSize() || + TheEntry->StringOffset > Buf.getBufferSize() || + TheEntry->StringOffset + TheEntry->NumStrings * sizeof(StringEntry) > + Buf.getBufferSize()) + return errorCodeToError(object_error::unexpected_eof); + return Error::success(); + }; + + SmallVector> Binaries; + if (TheHeader->Version > 1 && Index.has_value()) { + if (*Index >= TheHeader->EntriesCount) + return errorCodeToError(object_error::parse_failed); + const Entry *TheEntry = &Entries[*Index]; + if (auto Err = validateEntry(TheEntry)) + return std::move(Err); + + Binaries.emplace_back(new OffloadBinary(Buf, TheHeader, TheEntry, *Index)); + return std::move(Binaries); + } + + uint64_t EntriesCount = TheHeader->Version == 1 ? 1 : TheHeader->EntriesCount; + for (uint64_t I = 0; I < EntriesCount; ++I) { + const Entry *TheEntry = &Entries[I]; + if (auto Err = validateEntry(TheEntry)) + return std::move(Err); + + Binaries.emplace_back(new OffloadBinary(Buf, TheHeader, TheEntry, I)); + } - return std::unique_ptr( - new OffloadBinary(Buf, TheHeader, TheEntry)); + return std::move(Binaries); } -SmallString<0> OffloadBinary::write(const OffloadingImage &OffloadingData) { +SmallString<0> OffloadBinary::write(ArrayRef OffloadingData) { + uint64_t EntriesCount = OffloadingData.size(); + assert(EntriesCount > 0 && "At least one offloading image is required"); + // Create a null-terminated string table with all the used strings. + // Also calculate total size of images. StringTableBuilder StrTab(StringTableBuilder::ELF); - for (auto &KeyAndValue : OffloadingData.StringData) { - StrTab.add(KeyAndValue.first); - StrTab.add(KeyAndValue.second); + uint64_t TotalStringEntries = 0; + uint64_t TotalImagesSize = 0; + for (const OffloadingImage &Img : OffloadingData) { + for (auto &KeyAndValue : Img.StringData) { + StrTab.add(KeyAndValue.first); + StrTab.add(KeyAndValue.second); + } + TotalStringEntries += Img.StringData.size(); + TotalImagesSize += Img.Image->getBufferSize(); } StrTab.finalize(); - uint64_t StringEntrySize = - sizeof(StringEntry) * OffloadingData.StringData.size(); + uint64_t StringEntrySize = sizeof(StringEntry) * TotalStringEntries; + uint64_t EntriesSize = sizeof(Entry) * EntriesCount; + uint64_t StrTabOffset = sizeof(Header) + EntriesSize + StringEntrySize; // Make sure the image we're wrapping around is aligned as well. - uint64_t BinaryDataSize = alignTo(sizeof(Header) + sizeof(Entry) + - StringEntrySize + StrTab.getSize(), - getAlignment()); + uint64_t BinaryDataSize = + alignTo(StrTabOffset + StrTab.getSize(), getAlignment()); - // Create the header and fill in the offsets. The entry will be directly + // Create the header and fill in the offsets. The entries will be directly // placed after the header in memory. Align the size to the alignment of the // header so this can be placed contiguously in a single section. Header TheHeader; - TheHeader.Size = alignTo( - BinaryDataSize + OffloadingData.Image->getBufferSize(), getAlignment()); - TheHeader.EntryOffset = sizeof(Header); - TheHeader.EntrySize = sizeof(Entry); - - // Create the entry using the string table offsets. The string table will be - // placed directly after the entry in memory, and the image after that. - Entry TheEntry; - TheEntry.TheImageKind = OffloadingData.TheImageKind; - TheEntry.TheOffloadKind = OffloadingData.TheOffloadKind; - TheEntry.Flags = OffloadingData.Flags; - TheEntry.StringOffset = sizeof(Header) + sizeof(Entry); - TheEntry.NumStrings = OffloadingData.StringData.size(); - - TheEntry.ImageOffset = BinaryDataSize; - TheEntry.ImageSize = OffloadingData.Image->getBufferSize(); + TheHeader.Size = alignTo(BinaryDataSize + TotalImagesSize, getAlignment()); + TheHeader.EntriesOffset = sizeof(Header); + TheHeader.EntriesCount = EntriesCount; SmallString<0> Data; Data.reserve(TheHeader.Size); raw_svector_ostream OS(Data); OS << StringRef(reinterpret_cast(&TheHeader), sizeof(Header)); - OS << StringRef(reinterpret_cast(&TheEntry), sizeof(Entry)); - for (auto &KeyAndValue : OffloadingData.StringData) { - uint64_t Offset = sizeof(Header) + sizeof(Entry) + StringEntrySize; - StringEntry Map{Offset + StrTab.getOffset(KeyAndValue.first), - Offset + StrTab.getOffset(KeyAndValue.second)}; - OS << StringRef(reinterpret_cast(&Map), sizeof(StringEntry)); + + // Create the entries using the string table offsets. The string table will be + // placed directly after the set of entries in memory, and all the images are + // after that. + uint64_t StringEntryOffset = sizeof(Header) + EntriesSize; + uint64_t ImageOffset = BinaryDataSize; + for (const OffloadingImage &Img : OffloadingData) { + Entry TheEntry; + + TheEntry.TheImageKind = Img.TheImageKind; + TheEntry.TheOffloadKind = Img.TheOffloadKind; + TheEntry.Flags = Img.Flags; + + TheEntry.StringOffset = StringEntryOffset; + StringEntryOffset += sizeof(StringEntry) * Img.StringData.size(); + TheEntry.NumStrings = Img.StringData.size(); + + TheEntry.ImageOffset = ImageOffset; + ImageOffset += Img.Image->getBufferSize(); + TheEntry.ImageSize = Img.Image->getBufferSize(); + + OS << StringRef(reinterpret_cast(&TheEntry), sizeof(Entry)); + } + + // Create the string map entries. + for (const OffloadingImage &Img : OffloadingData) { + for (auto &KeyAndValue : Img.StringData) { + StringEntry Map{StrTabOffset + StrTab.getOffset(KeyAndValue.first), + StrTabOffset + StrTab.getOffset(KeyAndValue.second), + KeyAndValue.second.size()}; + OS << StringRef(reinterpret_cast(&Map), sizeof(StringEntry)); + } } + StrTab.write(OS); // Add padding to required image alignment. - OS.write_zeros(TheEntry.ImageOffset - OS.tell()); - OS << OffloadingData.Image->getBuffer(); + OS.write_zeros(BinaryDataSize - OS.tell()); + + for (const OffloadingImage &Img : OffloadingData) + OS << Img.Image->getBuffer(); // Add final padding to required alignment. assert(TheHeader.Size >= OS.tell() && "Too much data written?"); diff --git a/llvm/lib/ObjectYAML/ELFYAML.cpp b/llvm/lib/ObjectYAML/ELFYAML.cpp index 21dee1f4a341e..3e9940c048f9e 100644 --- a/llvm/lib/ObjectYAML/ELFYAML.cpp +++ b/llvm/lib/ObjectYAML/ELFYAML.cpp @@ -649,6 +649,7 @@ void ScalarBitSetTraits::bitset(IO &IO, BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1151, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1152, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1153, EF_AMDGPU_MACH); + BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1170, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1200, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1201, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1250, EF_AMDGPU_MACH); diff --git a/llvm/lib/ObjectYAML/OffloadEmitter.cpp b/llvm/lib/ObjectYAML/OffloadEmitter.cpp index 131da68d77506..51167bd812df3 100644 --- a/llvm/lib/ObjectYAML/OffloadEmitter.cpp +++ b/llvm/lib/ObjectYAML/OffloadEmitter.cpp @@ -18,6 +18,7 @@ namespace llvm { namespace yaml { bool yaml2offload(Binary &Doc, raw_ostream &Out, ErrorHandler EH) { + SmallVector Images; for (const auto &Member : Doc.Members) { object::OffloadBinary::OffloadingImage Image{}; if (Member.ImageKind) @@ -36,23 +37,24 @@ bool yaml2offload(Binary &Doc, raw_ostream &Out, ErrorHandler EH) { if (Member.Content) Member.Content->writeAsBinary(OS); Image.Image = MemoryBuffer::getMemBufferCopy(OS.str()); - - // Copy the data to a new buffer so we can modify the bytes directly. - auto Buffer = object::OffloadBinary::write(Image); - auto *TheHeader = - reinterpret_cast(&Buffer[0]); - if (Doc.Version) - TheHeader->Version = *Doc.Version; - if (Doc.Size) - TheHeader->Size = *Doc.Size; - if (Doc.EntryOffset) - TheHeader->EntryOffset = *Doc.EntryOffset; - if (Doc.EntrySize) - TheHeader->EntrySize = *Doc.EntrySize; - - Out.write(Buffer.begin(), Buffer.size()); + Images.push_back(std::move(Image)); } + // Copy the data to a new buffer so we can modify the bytes directly. + auto Buffer = object::OffloadBinary::write(Images); + auto *TheHeader = + reinterpret_cast(&Buffer[0]); + if (Doc.Version) + TheHeader->Version = *Doc.Version; + if (Doc.Size) + TheHeader->Size = *Doc.Size; + if (Doc.EntriesOffset) + TheHeader->EntriesOffset = *Doc.EntriesOffset; + if (Doc.EntriesCount) + TheHeader->EntriesCount = *Doc.EntriesCount; + + Out.write(Buffer.begin(), Buffer.size()); + return true; } diff --git a/llvm/lib/ObjectYAML/OffloadYAML.cpp b/llvm/lib/ObjectYAML/OffloadYAML.cpp index d5a0edde2179f..c0e0ed41aaca9 100644 --- a/llvm/lib/ObjectYAML/OffloadYAML.cpp +++ b/llvm/lib/ObjectYAML/OffloadYAML.cpp @@ -38,6 +38,7 @@ void ScalarEnumerationTraits::enumeration( ECase(OFK_OpenMP); ECase(OFK_Cuda); ECase(OFK_HIP); + ECase(OFK_SYCL); ECase(OFK_LAST); #undef ECase IO.enumFallback(Value); @@ -50,8 +51,8 @@ void MappingTraits::mapping(IO &IO, IO.mapTag("!Offload", true); IO.mapOptional("Version", O.Version); IO.mapOptional("Size", O.Size); - IO.mapOptional("EntryOffset", O.EntryOffset); - IO.mapOptional("EntrySize", O.EntrySize); + IO.mapOptional("EntriesOffset", O.EntriesOffset); + IO.mapOptional("EntriesCount", O.EntriesCount); IO.mapRequired("Members", O.Members); IO.setContext(nullptr); } diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp index 1584d30875570..675d941c39c13 100644 --- a/llvm/lib/Passes/PassBuilderPipelines.cpp +++ b/llvm/lib/Passes/PassBuilderPipelines.cpp @@ -285,12 +285,18 @@ static cl::opt EnableConstraintElimination( static cl::opt AttributorRun( "attributor-enable", cl::Hidden, cl::init(AttributorRunOption::NONE), cl::desc("Enable the attributor inter-procedural deduction pass"), - cl::values(clEnumValN(AttributorRunOption::ALL, "all", - "enable all attributor runs"), + cl::values(clEnumValN(AttributorRunOption::FULL, "full", + "enable all full attributor runs"), + clEnumValN(AttributorRunOption::LIGHT, "light", + "enable all attributor-light runs"), clEnumValN(AttributorRunOption::MODULE, "module", "enable module-wide attributor runs"), + clEnumValN(AttributorRunOption::MODULE_LIGHT, "module-light", + "enable module-wide attributor-light runs"), clEnumValN(AttributorRunOption::CGSCC, "cgscc", "enable call graph SCC attributor runs"), + clEnumValN(AttributorRunOption::CGSCC_LIGHT, "cgscc-light", + "enable call graph SCC attributor-light runs"), clEnumValN(AttributorRunOption::NONE, "none", "disable attributor runs"))); @@ -984,6 +990,8 @@ PassBuilder::buildInlinerPipeline(OptimizationLevel Level, if (AttributorRun & AttributorRunOption::CGSCC) MainCGPipeline.addPass(AttributorCGSCCPass()); + else if (AttributorRun & AttributorRunOption::CGSCC_LIGHT) + MainCGPipeline.addPass(AttributorLightCGSCCPass()); // Deduce function attributes. We do another run of this after the function // simplification pipeline, so this only needs to run when it could affect the @@ -1171,6 +1179,8 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, if (AttributorRun & AttributorRunOption::MODULE) MPM.addPass(AttributorPass()); + else if (AttributorRun & AttributorRunOption::MODULE_LIGHT) + MPM.addPass(AttributorLightPass()); // Lower type metadata and the type.test intrinsic in the ThinLTO // post link pipeline after ICP. This is to enable usage of the type diff --git a/llvm/lib/Support/FloatingPointMode.cpp b/llvm/lib/Support/FloatingPointMode.cpp index f2cd008277236..a81a2644a3713 100644 --- a/llvm/lib/Support/FloatingPointMode.cpp +++ b/llvm/lib/Support/FloatingPointMode.cpp @@ -107,6 +107,22 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, FPClassTest Mask) { return OS; } +void DenormalFPEnv::print(raw_ostream &OS, bool OmitIfSame) const { + if (F32Mode == DefaultMode) { + DefaultMode.print(OS, /*Legacy=*/false, OmitIfSame); + return; + } + + // Omit printing the base mode if only the f32 mode isn't the default. + if (DefaultMode != DenormalMode::getDefault()) { + DefaultMode.print(OS, /*Legacy=*/false, OmitIfSame); + OS << ", "; + } + + OS << "float: "; + F32Mode.print(OS, /*Legacy=*/false, OmitIfSame); +} + static bool cannotOrderStrictlyGreaterImpl(FPClassTest LHS, FPClassTest RHS, bool OrEqual, bool OrderedZero) { LHS &= ~fcNan; diff --git a/llvm/lib/Support/KnownFPClass.cpp b/llvm/lib/Support/KnownFPClass.cpp index e7662523d3f95..99d29119b8d86 100644 --- a/llvm/lib/Support/KnownFPClass.cpp +++ b/llvm/lib/Support/KnownFPClass.cpp @@ -14,6 +14,7 @@ #include "llvm/Support/KnownFPClass.h" #include "llvm/ADT/APFloat.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/KnownBits.h" using namespace llvm; @@ -626,3 +627,72 @@ KnownFPClass KnownFPClass::frexp_mant(const KnownFPClass &KnownSrc, Known.propagateNaN(KnownSrc); return Known; } + +KnownFPClass KnownFPClass::ldexp(const KnownFPClass &KnownSrc, + const KnownBits &ExpBits, + const fltSemantics &Flt, DenormalMode Mode) { + KnownFPClass Known; + Known.propagateNaN(KnownSrc, /*PropagateSign=*/true); + + // Sign is preserved, but underflows may produce zeroes. + if (KnownSrc.isKnownNever(fcNegative)) + Known.knownNot(fcNegative); + else if (KnownSrc.cannotBeOrderedLessThanZero()) + Known.knownNot(OrderedLessThanZeroMask); + + if (KnownSrc.isKnownNever(fcPositive)) + Known.knownNot(fcPositive); + else if (KnownSrc.cannotBeOrderedGreaterThanZero()) + Known.knownNot(OrderedGreaterThanZeroMask); + + unsigned Precision = APFloat::semanticsPrecision(Flt); + const int MantissaBits = Precision - 1; + + if (ExpBits.getSignedMinValue().sge(static_cast(MantissaBits))) + Known.knownNot(fcSubnormal); + + if (ExpBits.isConstant() && ExpBits.getConstant().isZero()) { + // ldexp(x, 0) -> x, so propagate everything. + Known.propagateCanonicalizingSrc(KnownSrc, Mode); + } else if (ExpBits.isNegative()) { + // If we know the power is <= 0, can't introduce inf + if (KnownSrc.isKnownNeverPosInfinity()) + Known.knownNot(fcPosInf); + if (KnownSrc.isKnownNeverNegInfinity()) + Known.knownNot(fcNegInf); + } else if (ExpBits.isNonNegative()) { + // If we know the power is >= 0, can't introduce subnormal or zero + if (KnownSrc.isKnownNeverPosSubnormal()) + Known.knownNot(fcPosSubnormal); + if (KnownSrc.isKnownNeverNegSubnormal()) + Known.knownNot(fcNegSubnormal); + if (KnownSrc.isKnownNeverLogicalPosZero(Mode)) + Known.knownNot(fcPosZero); + if (KnownSrc.isKnownNeverLogicalNegZero(Mode)) + Known.knownNot(fcNegZero); + } + + return Known; +} + +KnownFPClass KnownFPClass::powi(const KnownFPClass &KnownSrc, + const KnownBits &ExponentKnownBits) { + KnownFPClass Known; + if (ExponentKnownBits.isEven()) { + Known.knownNot(fcNegative); + return Known; + } + + // Given that exp is an integer, here are the + // ways that pow can return a negative value: + // + // pow(-x, exp) --> negative if exp is odd and x is negative. + // pow(-0, exp) --> -inf if exp is negative odd. + // pow(-0, exp) --> -0 if exp is positive odd. + // pow(-inf, exp) --> -0 if exp is negative odd. + // pow(-inf, exp) --> -inf if exp is positive odd. + if (KnownSrc.isKnownNever(fcNegative)) + Known.knownNot(fcNegative); + + return Known; +} diff --git a/llvm/lib/Support/MathExtras.cpp b/llvm/lib/Support/MathExtras.cpp index ad44b1a21676c..4424cdd935fef 100644 --- a/llvm/lib/Support/MathExtras.cpp +++ b/llvm/lib/Support/MathExtras.cpp @@ -28,4 +28,39 @@ namespace llvm { const float huge_valf = HUGE_VALF; #endif + /// Returns the number of digits in the given integer. + int NumDigitsBase10(uint64_t X) { + static constexpr struct ConstexprData { + uint8_t AtLeast[65] = {}; + uint64_t Boundaries[20] = {}; + static constexpr int NumDigitsConstexpr(uint64_t N) { + int res = 1; + while (N >= 10) { + res++; + N /= 10; + } + return res; + } + constexpr ConstexprData() { + uint64_t Val = ~0ull; + for (uint64_t i = 0; i <= 64; i++) { + uint64_t Digits = NumDigitsConstexpr(Val) - 1; + AtLeast[i] = Digits; + Val >>= 1; + } + // Special case because X=0 should return 1 and not 0 + Boundaries[0] = 0; + Val = 10; + for (uint64_t i = 1; i < 20; i++) { + Boundaries[i] = Val; + Val *= 10; + } + } + } Data; + + uint64_t Base2 = X ? countl_zero(X) : 64; + uint64_t Digits = Data.AtLeast[Base2]; + return Digits + (X >= Data.Boundaries[Digits]); + } + } // namespace llvm diff --git a/llvm/lib/Support/VirtualFileSystem.cpp b/llvm/lib/Support/VirtualFileSystem.cpp index 49a5cefe6a7d7..8a7ca35a8dd25 100644 --- a/llvm/lib/Support/VirtualFileSystem.cpp +++ b/llvm/lib/Support/VirtualFileSystem.cpp @@ -278,7 +278,7 @@ class RealFileSystem : public FileSystem { if (!LinkCWDToProcess) { SmallString<128> PWD, RealPWD; if (std::error_code EC = llvm::sys::fs::current_path(PWD)) - WD = EC; + WD = std::move(EC); else if (llvm::sys::fs::real_path(PWD, RealPWD)) WD = WorkingDirectory{PWD, PWD}; else diff --git a/llvm/lib/Support/Windows/Path.inc b/llvm/lib/Support/Windows/Path.inc index c03b85b2f4bb3..5c8bd5077c7aa 100644 --- a/llvm/lib/Support/Windows/Path.inc +++ b/llvm/lib/Support/Windows/Path.inc @@ -607,10 +607,12 @@ std::error_code rename(const Twine &From, const Twine &To) { for (unsigned Retry = 0; Retry != 200; ++Retry) { if (Retry != 0) ::Sleep(10); + // `FILE_FLAG_BACKUP_SEMANTICS` must be used to create a handle to a + // directory. FromHandle = ::CreateFileW(WideFrom.begin(), GENERIC_READ | DELETE, FILE_SHARE_READ | FILE_SHARE_WRITE | FILE_SHARE_DELETE, - NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL); + NULL, OPEN_EXISTING, FILE_FLAG_BACKUP_SEMANTICS, NULL); if (FromHandle) break; diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index 57867fc8afb7d..2b8db27599d3c 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -199,11 +199,11 @@ class AArch64AsmPrinter : public AsmPrinter { bool AddrDiscIsKilled; }; - // Emit the sequence for AUT or AUTPAC. + // Emit the sequence for AUT or AUTPAC. Addend if AUTRELLOADPAC void emitPtrauthAuthResign(Register Pointer, Register Scratch, PtrAuthSchema AuthSchema, std::optional SignSchema, - Value *DS); + std::optional Addend, Value *DS); // Emit R_AARCH64_PATCHINST, the deactivation symbol relocation. Returns true // if no instruction should be emitted because the deactivation symbol is @@ -2237,9 +2237,10 @@ AArch64AsmPrinter::PtrAuthSchema::PtrAuthSchema( void AArch64AsmPrinter::emitPtrauthAuthResign( Register Pointer, Register Scratch, PtrAuthSchema AuthSchema, - std::optional SignSchema, Value *DS) { + std::optional SignSchema, std::optional OptAddend, + Value *DS) { const bool IsResign = SignSchema.has_value(); - + const bool HasLoad = OptAddend.has_value(); // We expand AUT/AUTPAC into a sequence of the form // // ; authenticate x16 @@ -2301,12 +2302,76 @@ void AArch64AsmPrinter::emitPtrauthAuthResign( } // We already emitted unchecked and checked-but-non-trapping AUTs. - // That left us with trapping AUTs, and AUTPACs. + // That left us with trapping AUTs, and AUTPA/AUTRELLOADPACs. // Trapping AUTs don't need PAC: we're done. if (!IsResign) return; - // Compute pac discriminator + if (HasLoad) { + int64_t Addend = *OptAddend; + // incoming rawpointer in X16, X17 is not live at this point. + // LDSRWpre x17, x16, simm9 ; note: x16+simm9 used later. + if (isInt<9>(Addend)) { + EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::LDRSWpre) + .addReg(AArch64::X16) + .addReg(AArch64::X17) + .addReg(AArch64::X16) + .addImm(/*simm9:*/ Addend)); + } else { + // x16 = x16 + Addend computation has 2 variants + if (isUInt<24>(Addend)) { + // variant 1: add x16, x16, Addend >> shift12 ls shift12 + // This can take upto 2 instructions. + for (int BitPos = 0; BitPos != 24 && (Addend >> BitPos); BitPos += 12) { + EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ADDXri) + .addReg(AArch64::X16) + .addReg(AArch64::X16) + .addImm((Addend >> BitPos) & 0xfff) + .addImm(AArch64_AM::getShifterImm( + AArch64_AM::LSL, BitPos))); + } + } else { + // variant 2: accumulate constant in X17 16 bits at a time, and add to + // X16 This can take 2-5 instructions. + EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::MOVZXi) + .addReg(AArch64::X17) + .addImm(Addend & 0xffff) + .addImm(AArch64_AM::getShifterImm( + AArch64_AM::LSL, 0))); + + for (int Offset = 16; Offset < 64; Offset += 16) { + uint16_t Fragment = static_cast(Addend >> Offset); + if (!Fragment) + continue; + EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::MOVKXi) + .addReg(AArch64::X17) + .addReg(AArch64::X17) + .addImm(Fragment) + .addImm(/*shift:*/ Offset)); + } + // addx x16, x16, x17 + EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ADDXrs) + .addReg(AArch64::X16) + .addReg(AArch64::X16) + .addReg(AArch64::X17) + .addImm(0)); + } + // ldrsw x17,x16(0) + EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::LDRSWui) + .addReg(AArch64::X17) + .addReg(AArch64::X16) + .addImm(0)); + } + // addx x16, x16, x17 + EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::ADDXrs) + .addReg(AArch64::X16) + .addReg(AArch64::X16) + .addReg(AArch64::X17) + .addImm(0)); + + } /* HasLoad == true */ + + // Compute pac discriminator into x17 Register PACDiscReg = emitPtrauthDiscriminator(SignSchema->IntDisc, SignSchema->AddrDisc, Scratch); emitPAC(SignSchema->Key, Pointer, PACDiscReg); @@ -3221,7 +3286,7 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) { MI->getOperand(1).getImm(), MI->getOperand(2)); emitPtrauthAuthResign(Pointer, Scratch, AuthSchema, std::nullopt, - MI->getDeactivationSymbol()); + std::nullopt, MI->getDeactivationSymbol()); return; } @@ -3233,7 +3298,7 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) { MI->getOperand(4).getImm(), MI->getOperand(5)); emitPtrauthAuthResign(Pointer, Scratch, AuthSchema, std::nullopt, - MI->getDeactivationSymbol()); + std::nullopt, MI->getDeactivationSymbol()); return; } @@ -3248,7 +3313,24 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) { MI->getOperand(4).getImm(), MI->getOperand(5)); emitPtrauthAuthResign(Pointer, Scratch, AuthSchema, SignSchema, + std::nullopt, MI->getDeactivationSymbol()); + return; + } + + case AArch64::AUTRELLOADPAC: { + const Register Pointer = AArch64::X16; + const Register Scratch = AArch64::X17; + + PtrAuthSchema AuthSchema((AArch64PACKey::ID)MI->getOperand(0).getImm(), + MI->getOperand(1).getImm(), MI->getOperand(2)); + + PtrAuthSchema SignSchema((AArch64PACKey::ID)MI->getOperand(3).getImm(), + MI->getOperand(4).getImm(), MI->getOperand(5)); + + emitPtrauthAuthResign(Pointer, Scratch, AuthSchema, SignSchema, + MI->getOperand(6).getImm(), MI->getDeactivationSymbol()); + return; } diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 7cd32ebe2e2f7..8c0377fa5550f 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -484,7 +484,6 @@ Register AArch64FastISel::materializeGV(const GlobalValue *GV) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG)) .addDef(Result64) - .addImm(0) .addReg(ResultReg, RegState::Kill) .addImm(AArch64::sub_32); return Result64; @@ -1873,7 +1872,6 @@ Register AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, Register Reg64 = createResultReg(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), Reg64) - .addImm(0) .addReg(ResultReg, getKillRegState(true)) .addImm(AArch64::sub_32); ResultReg = Reg64; @@ -4031,7 +4029,6 @@ Register AArch64FastISel::emiti1Ext(Register SrcReg, MVT DestVT, bool IsZExt) { Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), Reg64) - .addImm(0) .addReg(ResultReg) .addImm(AArch64::sub_32); ResultReg = Reg64; @@ -4178,7 +4175,6 @@ Register AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, Register Op0, Register TmpReg = MRI.createVirtualRegister(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), TmpReg) - .addImm(0) .addReg(Op0) .addImm(AArch64::sub_32); Op0 = TmpReg; @@ -4295,7 +4291,6 @@ Register AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, Register Op0, Register TmpReg = MRI.createVirtualRegister(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), TmpReg) - .addImm(0) .addReg(Op0) .addImm(AArch64::sub_32); Op0 = TmpReg; @@ -4401,7 +4396,6 @@ Register AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, Register Op0, Register TmpReg = MRI.createVirtualRegister(RC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), TmpReg) - .addImm(0) .addReg(Op0) .addImm(AArch64::sub_32); Op0 = TmpReg; @@ -4459,7 +4453,6 @@ Register AArch64FastISel::emitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), Src64) - .addImm(0) .addReg(SrcReg) .addImm(AArch64::sub_32); SrcReg = Src64; @@ -4556,7 +4549,6 @@ bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT, Register Reg64 = createResultReg(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), Reg64) - .addImm(0) .addReg(Reg, getKillRegState(true)) .addImm(AArch64::sub_32); Reg = Reg64; @@ -4599,7 +4591,6 @@ bool AArch64FastISel::selectIntExt(const Instruction *I) { Register ResultReg = createResultReg(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AArch64::SUBREG_TO_REG), ResultReg) - .addImm(0) .addReg(SrcReg) .addImm(AArch64::sub_32); SrcReg = ResultReg; diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 7b566e432b6bc..67f4e127b0c87 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -479,9 +479,14 @@ class AArch64DAGToDAGISel : public SelectionDAGISel { bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) { return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); } - bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width); + template + bool SelectCVTFixedPointVec(SDValue N, SDValue &FixedPos) { + return SelectCVTFixedPointVec(N, FixedPos, RegWidth); + } + bool SelectCVTFixedPointVec(SDValue N, SDValue &FixedPos, unsigned Width); + template bool SelectCVTFixedPosRecipOperand(SDValue N, SDValue &FixedPos) { return SelectCVTFixedPosRecipOperand(N, FixedPos, RegWidth); @@ -1577,12 +1582,15 @@ void AArch64DAGToDAGISel::SelectPtrauthAuth(SDNode *N) { void AArch64DAGToDAGISel::SelectPtrauthResign(SDNode *N) { SDLoc DL(N); - // IntrinsicID is operand #0 - SDValue Val = N->getOperand(1); - SDValue AUTKey = N->getOperand(2); - SDValue AUTDisc = N->getOperand(3); - SDValue PACKey = N->getOperand(4); - SDValue PACDisc = N->getOperand(5); + // IntrinsicID is operand #0, if W_CHAIN it is #1 + int OffsetBase = N->getOpcode() == ISD::INTRINSIC_W_CHAIN ? 1 : 0; + SDValue Val = N->getOperand(OffsetBase + 1); + SDValue AUTKey = N->getOperand(OffsetBase + 2); + SDValue AUTDisc = N->getOperand(OffsetBase + 3); + SDValue PACKey = N->getOperand(OffsetBase + 4); + SDValue PACDisc = N->getOperand(OffsetBase + 5); + uint32_t IntNum = N->getConstantOperandVal(OffsetBase + 0); + bool HasLoad = IntNum == Intrinsic::ptrauth_resign_load_relative; unsigned AUTKeyC = cast(AUTKey)->getZExtValue(); unsigned PACKeyC = cast(PACKey)->getZExtValue(); @@ -1601,11 +1609,23 @@ void AArch64DAGToDAGISel::SelectPtrauthResign(SDNode *N) { SDValue X16Copy = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, AArch64::X16, Val, SDValue()); - SDValue Ops[] = {AUTKey, AUTConstDisc, AUTAddrDisc, PACKey, - PACConstDisc, PACAddrDisc, X16Copy.getValue(1)}; + if (HasLoad) { + SDValue Addend = N->getOperand(OffsetBase + 6); + SDValue IncomingChain = N->getOperand(0); + SDValue Ops[] = {AUTKey, AUTConstDisc, AUTAddrDisc, + PACKey, PACConstDisc, PACAddrDisc, + Addend, IncomingChain, X16Copy.getValue(1)}; - SDNode *AUTPAC = CurDAG->getMachineNode(AArch64::AUTPAC, DL, MVT::i64, Ops); - ReplaceNode(N, AUTPAC); + SDNode *AUTRELLOADPAC = CurDAG->getMachineNode(AArch64::AUTRELLOADPAC, DL, + MVT::i64, MVT::Other, Ops); + ReplaceNode(N, AUTRELLOADPAC); + } else { + SDValue Ops[] = {AUTKey, AUTConstDisc, AUTAddrDisc, PACKey, + PACConstDisc, PACAddrDisc, X16Copy.getValue(1)}; + + SDNode *AUTPAC = CurDAG->getMachineNode(AArch64::AUTPAC, DL, MVT::i64, Ops); + ReplaceNode(N, AUTPAC); + } } bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) { @@ -1736,12 +1756,9 @@ bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) { SDValue LoadedVal = SDValue(Res, 1); if (InsertTo64) { SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); - LoadedVal = - SDValue(CurDAG->getMachineNode( - AArch64::SUBREG_TO_REG, dl, MVT::i64, - CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal, - SubReg), - 0); + LoadedVal = SDValue(CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, dl, + MVT::i64, LoadedVal, SubReg), + 0); } ReplaceUses(SDValue(N, 0), LoadedVal); @@ -3969,9 +3986,8 @@ bool AArch64DAGToDAGISel::tryShiftAmountMod(SDNode *N) { NewShiftAmt = narrowIfNeeded(CurDAG, NewShiftAmt); else if (VT == MVT::i64 && NewShiftAmt->getValueType(0) == MVT::i32) { SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, DL, MVT::i32); - MachineSDNode *Ext = CurDAG->getMachineNode( - AArch64::SUBREG_TO_REG, DL, VT, - CurDAG->getTargetConstant(0, DL, MVT::i64), NewShiftAmt, SubReg); + MachineSDNode *Ext = CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL, VT, + NewShiftAmt, SubReg); NewShiftAmt = SDValue(Ext, 0); } @@ -3999,48 +4015,81 @@ static bool checkCVTFixedPointOperandWithFBits(SelectionDAG *CurDAG, SDValue N, } else return false; - // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits - // is between 1 and 32 for a destination w-register, or 1 and 64 for an - // x-register. - // - // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we - // want THIS_NODE to be 2^fbits. This is much easier to deal with using - // integers. - bool IsExact; - - if (isReciprocal) - if (!FVal.getExactInverse(&FVal)) - return false; - - // fbits is between 1 and 64 in the worst-case, which means the fmul - // could have 2^64 as an actual operand. Need 65 bits of precision. - APSInt IntVal(65, true); - FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact); - - // N.b. isPowerOf2 also checks for > 0. - if (!IsExact || !IntVal.isPowerOf2()) - return false; - unsigned FBits = IntVal.logBase2(); - - // Checks above should have guaranteed that we haven't lost information in - // finding FBits, but it must still be in range. - if (FBits == 0 || FBits > RegWidth) return false; + if (unsigned FBits = + CheckFixedPointOperandConstant(FVal, RegWidth, isReciprocal)) { + FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32); + return true; + } - FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32); - return true; + return false; } bool AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth) { return checkCVTFixedPointOperandWithFBits(CurDAG, N, FixedPos, RegWidth, - false); + /*isReciprocal*/ false); +} + +bool AArch64DAGToDAGISel::SelectCVTFixedPointVec(SDValue N, SDValue &FixedPos, + unsigned RegWidth) { + if ((N.getOpcode() == AArch64ISD::NVCAST || N.getOpcode() == ISD::BITCAST) && + N.getValueType().getScalarSizeInBits() == + N.getOperand(0).getValueType().getScalarSizeInBits()) + N = N.getOperand(0); + + auto ImmToFloat = [RegWidth](APInt Imm) { + switch (RegWidth) { + case 16: + return APFloat(APFloat::IEEEhalf(), Imm); + case 32: + return APFloat(APFloat::IEEEsingle(), Imm); + case 64: + return APFloat(APFloat::IEEEdouble(), Imm); + default: + llvm_unreachable("Unexpected RegWidth!"); + }; + }; + + APFloat FVal(0.0); + switch (N->getOpcode()) { + case AArch64ISD::MOVIshift: + FVal = ImmToFloat(APInt(RegWidth, N.getConstantOperandVal(0) + << N.getConstantOperandVal(1))); + break; + case AArch64ISD::FMOV: + assert(RegWidth == 32 || RegWidth == 64); + if (RegWidth == 32) + FVal = ImmToFloat( + APInt(RegWidth, (uint32_t)AArch64_AM::decodeAdvSIMDModImmType11( + N.getConstantOperandVal(0)))); + else + FVal = ImmToFloat(APInt(RegWidth, AArch64_AM::decodeAdvSIMDModImmType12( + N.getConstantOperandVal(0)))); + break; + case AArch64ISD::DUP: + if (isa(N.getOperand(0))) + FVal = ImmToFloat(N.getConstantOperandAPInt(0).trunc(RegWidth)); + else + return false; + break; + default: + return false; + } + + if (unsigned FBits = CheckFixedPointOperandConstant(FVal, RegWidth, + /*isReciprocal*/ false)) { + FixedPos = CurDAG->getTargetConstant(FBits, SDLoc(N), MVT::i32); + return true; + } + + return false; } bool AArch64DAGToDAGISel::SelectCVTFixedPosRecipOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth) { return checkCVTFixedPointOperandWithFBits(CurDAG, N, FixedPos, RegWidth, - true); + /*isReciprocal*/ true); } // Inspects a register string of the form o0:op1:CRn:CRm:op2 gets the fields @@ -4625,8 +4674,8 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) { SDValue MOVIV = SDValue(MOV, 0); SDValue ZSub = CurDAG->getTargetConstant(AArch64::zsub, DL, MVT::i32); - SDNode *SubRegToReg = CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL, - VT, Zero, MOVIV, ZSub); + SDNode *SubRegToReg = + CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL, VT, MOVIV, ZSub); R1 = N1->getOperand(1); R2 = SDValue(SubRegToReg, 0); @@ -5766,6 +5815,9 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) { {AArch64::BF2CVT_2ZZ_BtoH, AArch64::F2CVT_2ZZ_BtoH})) SelectCVTIntrinsicFP8(Node, 2, Opc); return; + case Intrinsic::ptrauth_resign_load_relative: + SelectPtrauthResign(Node); + return; } } break; case ISD::INTRINSIC_WO_CHAIN: { diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 9ed05681de32d..add3a92343943 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1413,7 +1413,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::SMUL_LOHI, VT, Expand); setOperationAction(ISD::UMUL_LOHI, VT, Expand); - setOperationAction(ISD::BSWAP, VT, Expand); + if (VT == MVT::v4i16 || VT == MVT::v8i16 || VT == MVT::v2i32 || + VT == MVT::v4i32 || VT == MVT::v2i64) + setOperationAction(ISD::BSWAP, VT, Legal); + else + setOperationAction(ISD::BSWAP, VT, Expand); setOperationAction(ISD::CTTZ, VT, Expand); for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { @@ -3378,7 +3382,7 @@ static const MachineInstr *stripVRegCopies(const MachineRegisterInfo &MRI, continue; } if (Opcode == AArch64::SUBREG_TO_REG) { - Reg = DefMI->getOperand(2).getReg(); + Reg = DefMI->getOperand(1).getReg(); continue; } @@ -3566,6 +3570,7 @@ static SDValue convertFixedMaskToScalableVector(SDValue Mask, static SDValue getPredicateForVector(SelectionDAG &DAG, SDLoc &DL, EVT VT); static SDValue getPredicateForScalableVector(SelectionDAG &DAG, SDLoc &DL, EVT VT); +static SDValue getSVEPredicateBitCast(EVT VT, SDValue Op, SelectionDAG &DAG); /// isZerosVector - Check whether SDNode N is a zero-filled vector. static bool isZerosVector(const SDNode *N) { @@ -6027,6 +6032,43 @@ static SDValue optimizeIncrementingWhile(SDNode *N, SelectionDAG &DAG, return SDValue(); } +// Match get.active.lane.mask(0, cttz.elts(x)) -> brkb(x) +// Match get.active.lane.mask(0, add(cttz.elts(x), 1)) -> brka(x) +static SDValue optimizeBrk(SDNode *N, SelectionDAG &DAG) { + SDLoc DL(N); + EVT VT = N->getValueType(0); + // Lower bound must be 0. + if (!isZeroOrZeroSplat(N->getOperand(0))) + return SDValue(); + + SDValue Upper = N->getOperand(1); + + // Default to brkb, switch to brka if we find a +1. + unsigned BrkID = Intrinsic::aarch64_sve_brkb_z; + if (Upper->getOpcode() == ISD::ADD && isOneOrOneSplat(Upper.getOperand(1))) { + Upper = Upper.getOperand(0); + BrkID = Intrinsic::aarch64_sve_brka_z; + } + + // We're looking for an upper bound based on CTTZ_ELTS; this would be selected + // as a cntp(brk(Pg, Mask)), but if we're just going to make a whilelo based + // on that then we just need the brk. + if (Upper.getOpcode() != AArch64ISD::CTTZ_ELTS || !VT.isScalableVector()) + return SDValue(); + + SDValue Pg = Upper->getOperand(0); + SDValue Mask = Upper->getOperand(1); + + // brk{a,b} only support .b forms, so cast to make sure all our p regs match. + Pg = getSVEPredicateBitCast(MVT::nxv16i1, Pg, DAG); + SDValue MaskR = + DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv16i1, Mask); + SDValue ID = DAG.getTargetConstant(BrkID, DL, MVT::i64); + SDValue Brk = + DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::nxv16i1, ID, Pg, MaskR); + return DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, VT, Brk); +} + // Returns a safe bitcast between two scalable vector predicates, where // any newly created lanes from a widening bitcast are defined as zero. static SDValue getSVEPredicateBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) { @@ -6911,13 +6953,14 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, if (VT.isFixedLengthVector()) { // We can use SVE instructions to lower this intrinsic by first creating // an SVE predicate register mask from the fixed-width vector. - EVT NewVT = getTypeToTransformTo(*DAG.getContext(), VT); - SDValue Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, CttzOp); + VT = getTypeToTransformTo(*DAG.getContext(), VT); + SDValue Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, CttzOp); CttzOp = convertFixedMaskToScalableVector(Mask, DAG); } + SDValue Pg = getPredicateForVector(DAG, DL, VT); SDValue NewCttzElts = - DAG.getNode(AArch64ISD::CTTZ_ELTS, DL, MVT::i64, CttzOp); + DAG.getNode(AArch64ISD::CTTZ_ELTS, DL, MVT::i64, Pg, CttzOp); return DAG.getZExtOrTrunc(NewCttzElts, DL, Op.getValueType()); } case Intrinsic::experimental_vector_match: { @@ -13138,14 +13181,15 @@ static SDValue getEstimate(const AArch64Subtarget *ST, unsigned Opcode, return SDValue(); } -SDValue -AArch64TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, - const DenormalMode &Mode) const { +SDValue AArch64TargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, + const DenormalMode &Mode, + SDNodeFlags Flags) const { SDLoc DL(Op); EVT VT = Op.getValueType(); EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); SDValue FPZero = DAG.getConstantFP(0.0, DL, VT); - return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ); + return DAG.getSetCC(DL, CCVT, Op, FPZero, ISD::SETEQ, /*Chain=*/{}, + /*Signaling=*/false, Flags); } SDValue @@ -15912,7 +15956,7 @@ SDValue AArch64TargetLowering::LowerFixedLengthBuildVectorToSVE( EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT); auto *BVN = cast(Op); - if (auto SeqInfo = BVN->isConstantSequence()) { + if (auto SeqInfo = BVN->isArithmeticSequence()) { SDValue Start = DAG.getConstant(SeqInfo->first, DL, ContainerVT); SDValue Steps = DAG.getStepVector(DL, ContainerVT, SeqInfo->second); SDValue Seq = DAG.getNode(ISD::ADD, DL, ContainerVT, Start, Steps); @@ -15969,7 +16013,7 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, EVT VT = Op.getValueType(); bool OverrideNEON = !Subtarget->isNeonAvailable() || - cast(Op)->isConstantSequence(); + cast(Op)->isArithmeticSequence(); if (useSVEForFixedLengthVectorVT(VT, OverrideNEON)) return LowerFixedLengthBuildVectorToSVE(Op, DAG); @@ -17453,7 +17497,7 @@ SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op, /// Set the IntrinsicInfo for the `aarch64_sve_st` intrinsics. template -static bool +static void setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL, AArch64TargetLowering::IntrinsicInfo &Info, const CallBase &CI) { Info.opc = ISD::INTRINSIC_VOID; @@ -17473,24 +17517,29 @@ setInfoSVEStN(const AArch64TargetLowering &TLI, const DataLayout &DL, Info.offset = 0; Info.align.reset(); Info.flags = MachineMemOperand::MOStore; - return true; } /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment /// specified in the intrinsic calls. -bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void AArch64TargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; auto &DL = I.getDataLayout(); switch (Intrinsic) { case Intrinsic::aarch64_sve_st2: - return setInfoSVEStN<2>(*this, DL, Info, I); + setInfoSVEStN<2>(*this, DL, Info, I); + Infos.push_back(Info); + return; case Intrinsic::aarch64_sve_st3: - return setInfoSVEStN<3>(*this, DL, Info, I); + setInfoSVEStN<3>(*this, DL, Info, I); + Infos.push_back(Info); + return; case Intrinsic::aarch64_sve_st4: - return setInfoSVEStN<4>(*this, DL, Info, I); + setInfoSVEStN<4>(*this, DL, Info, I); + Infos.push_back(Info); + return; case Intrinsic::aarch64_neon_ld2: case Intrinsic::aarch64_neon_ld3: case Intrinsic::aarch64_neon_ld4: @@ -17505,7 +17554,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); // volatile loads with NEON intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_neon_ld2lane: case Intrinsic::aarch64_neon_ld3lane: @@ -17526,7 +17576,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); // volatile loads with NEON intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_neon_st2: case Intrinsic::aarch64_neon_st3: @@ -17548,7 +17599,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); // volatile stores with NEON intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_neon_st2lane: case Intrinsic::aarch64_neon_st3lane: @@ -17572,7 +17624,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); // volatile stores with NEON intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_ldaxr: case Intrinsic::aarch64_ldxr: { @@ -17583,7 +17636,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ValTy); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_stlxr: case Intrinsic::aarch64_stxr: { @@ -17594,7 +17648,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ValTy); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_ldaxp: case Intrinsic::aarch64_ldxp: @@ -17604,7 +17659,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(16); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::aarch64_stlxp: case Intrinsic::aarch64_stxp: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -17613,7 +17669,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(16); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::aarch64_sve_ldnt1: { Type *ElTy = cast(I.getType())->getElementType(); Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -17622,7 +17679,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ElTy); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MONonTemporal; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_sve_stnt1: { Type *ElTy = @@ -17633,7 +17691,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ElTy); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MONonTemporal; - return true; + Infos.push_back(Info); + return; } case Intrinsic::aarch64_mops_memset_tag: { Value *Dst = I.getArgOperand(0); @@ -17646,13 +17705,12 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags = MachineMemOperand::MOStore; // The size of the memory being operated on is unknown at this point Info.size = MemoryLocation::UnknownSize; - return true; + Infos.push_back(Info); + return; } default: break; } - - return false; } bool AArch64TargetLowering::shouldReduceLoadWidth( @@ -19452,6 +19510,9 @@ performActiveLaneMaskCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, if (DCI.isBeforeLegalize()) return SDValue(); + if (SDValue Brk = optimizeBrk(N, DCI.DAG)) + return Brk; + if (SDValue While = optimizeIncrementingWhile(N, DCI.DAG, /*IsSigned=*/false, /*IsEqual=*/false)) return While; @@ -20631,70 +20692,7 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, tryToReplaceScalarFPConversionWithSVE(N, DAG, DCI, Subtarget)) return Res; - if (!Subtarget->isNeonAvailable()) - return SDValue(); - - if (!N->getValueType(0).isSimple()) - return SDValue(); - - SDValue Op = N->getOperand(0); - if (!Op.getValueType().isSimple() || Op.getOpcode() != ISD::FMUL) - return SDValue(); - - if (!Op.getValueType().is64BitVector() && !Op.getValueType().is128BitVector()) - return SDValue(); - - SDValue ConstVec = Op->getOperand(1); - if (!isa(ConstVec)) - return SDValue(); - - MVT FloatTy = Op.getSimpleValueType().getVectorElementType(); - uint32_t FloatBits = FloatTy.getSizeInBits(); - if (FloatBits != 32 && FloatBits != 64 && - (FloatBits != 16 || !Subtarget->hasFullFP16())) - return SDValue(); - - MVT IntTy = N->getSimpleValueType(0).getVectorElementType(); - uint32_t IntBits = IntTy.getSizeInBits(); - if (IntBits != 16 && IntBits != 32 && IntBits != 64) - return SDValue(); - - // Avoid conversions where iN is larger than the float (e.g., float -> i64). - if (IntBits > FloatBits) - return SDValue(); - - BitVector UndefElements; - BuildVectorSDNode *BV = cast(ConstVec); - int32_t Bits = IntBits == 64 ? 64 : 32; - int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, Bits + 1); - if (C == -1 || C == 0 || C > Bits) - return SDValue(); - - EVT ResTy = Op.getValueType().changeVectorElementTypeToInteger(); - if (!DAG.getTargetLoweringInfo().isTypeLegal(ResTy)) - return SDValue(); - - if (N->getOpcode() == ISD::FP_TO_SINT_SAT || - N->getOpcode() == ISD::FP_TO_UINT_SAT) { - EVT SatVT = cast(N->getOperand(1))->getVT(); - if (SatVT.getScalarSizeInBits() != IntBits || IntBits != FloatBits) - return SDValue(); - } - - SDLoc DL(N); - bool IsSigned = (N->getOpcode() == ISD::FP_TO_SINT || - N->getOpcode() == ISD::FP_TO_SINT_SAT); - unsigned IntrinsicOpcode = IsSigned ? Intrinsic::aarch64_neon_vcvtfp2fxs - : Intrinsic::aarch64_neon_vcvtfp2fxu; - SDValue FixConv = - DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, ResTy, - DAG.getTargetConstant(IntrinsicOpcode, DL, MVT::i32), - Op->getOperand(0), DAG.getTargetConstant(C, DL, MVT::i32)); - // We can handle smaller integers by generating an extra trunc. - if (IntBits < FloatBits) - FixConv = DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), FixConv); - - return FixConv; + return SDValue(); } // Given a tree of and/or(csel(0, 1, cc0), csel(0, 1, cc1)), we may be able to diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index aa6110a4ce39d..7f4f28ebf1ade 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -208,8 +208,8 @@ class AArch64TargetLowering : public TargetLowering { EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, @@ -824,7 +824,8 @@ class AArch64TargetLowering : public TargetLowering { SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps) const override; SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, - const DenormalMode &Mode) const override; + const DenormalMode &Mode, + SDNodeFlags Flags = {}) const override; SDValue getSqrtResultForDenormInput(SDValue Operand, SelectionDAG &DAG) const override; unsigned combineRepeatedFPDivisors() const override; diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td index 5d9215dd71233..21982300f5213 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td +++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td @@ -313,19 +313,19 @@ def ldxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{ } def : Pat<(ldxr_1 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRB GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_2 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRH GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_4 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRW GPR64sp:$addr), sub_32)>; def : Pat<(ldxr_8 GPR64sp:$addr), (LDXRX GPR64sp:$addr)>; def : Pat<(and (ldxr_1 GPR64sp:$addr), 0xff), - (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRB GPR64sp:$addr), sub_32)>; def : Pat<(and (ldxr_2 GPR64sp:$addr), 0xffff), - (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRH GPR64sp:$addr), sub_32)>; def : Pat<(and (ldxr_4 GPR64sp:$addr), 0xffffffff), - (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDXRW GPR64sp:$addr), sub_32)>; // Load-exclusives. @@ -354,19 +354,19 @@ def ldaxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{ } def : Pat<(ldaxr_1 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRB GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_2 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRH GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_4 GPR64sp:$addr), - (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRW GPR64sp:$addr), sub_32)>; def : Pat<(ldaxr_8 GPR64sp:$addr), (LDAXRX GPR64sp:$addr)>; def : Pat<(and (ldaxr_1 GPR64sp:$addr), 0xff), - (SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRB GPR64sp:$addr), sub_32)>; def : Pat<(and (ldaxr_2 GPR64sp:$addr), 0xffff), - (SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRH GPR64sp:$addr), sub_32)>; def : Pat<(and (ldaxr_4 GPR64sp:$addr), 0xffffffff), - (SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>; + (SUBREG_TO_REG (LDAXRW GPR64sp:$addr), sub_32)>; // Store-exclusives. @@ -596,7 +596,7 @@ let Predicates = [HasRCPC3, HasNEON] in { // by the patterns above. We only need to cover the v1f64 case manually. def : Pat<(releasing_store GPR64sp:$Rn, (i64 (bitconvert (v1f64 VecListOne64:$Vt)))), - (STL1 (SUBREG_TO_REG (i64 0), VecListOne64:$Vt, dsub), (i64 0), GPR64sp:$Rn)>; + (STL1 (SUBREG_TO_REG VecListOne64:$Vt, dsub), (i64 0), GPR64sp:$Rn)>; } // v8.4a FEAT_LRCPC2 patterns diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index ed2028c552dbf..7d4e034ca16c8 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -2768,11 +2768,11 @@ multiclass Shift shift_type, string asm, SDNode OpNode> { def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (sext GPR32:$Rm)))), (!cast(NAME # "Xr") GPR64:$Rn, - (SUBREG_TO_REG (i32 0), GPR32:$Rm, sub_32))>; + (SUBREG_TO_REG GPR32:$Rm, sub_32))>; def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (zext GPR32:$Rm)))), (!cast(NAME # "Xr") GPR64:$Rn, - (SUBREG_TO_REG (i32 0), GPR32:$Rm, sub_32))>; + (SUBREG_TO_REG GPR32:$Rm, sub_32))>; } class ShiftAlias @@ -9468,7 +9468,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (AArch64dup (f16 FPR16Op_lo:$Rm)))), (!cast(INST # "v8i16_indexed") V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>; + (SUBREG_TO_REG (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>; def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (AArch64duplane16 (v8f16 V128_lo:$Rm), @@ -9478,7 +9478,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (AArch64dup (f16 FPR16Op_lo:$Rm)))), (!cast(INST # "v4i16_indexed") V64:$Rd, V64:$Rn, - (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>; + (SUBREG_TO_REG (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>; def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn), (vector_extract (v8f16 V128_lo:$Rm), VectorIndexH:$idx))), @@ -9500,7 +9500,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (AArch64dup (f32 FPR32Op:$Rm)))), (!cast(INST # "v2i32_indexed") V64:$Rd, V64:$Rn, - (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; + (SUBREG_TO_REG FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar. @@ -9512,7 +9512,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (AArch64dup (f32 FPR32Op:$Rm)))), (!cast(INST # "v4i32_indexed") V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; + (SUBREG_TO_REG FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar. def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), @@ -9523,7 +9523,7 @@ multiclass SIMDFPIndexedTiedPatterns { def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (AArch64dup (f64 FPR64Op:$Rm)))), (!cast(INST # "v2i64_indexed") V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; + (SUBREG_TO_REG FPR64Op:$Rm, dsub), (i64 0))>; // Covers 2 variants for 32-bit scalar version: extract from .2s or from .4s def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), @@ -9632,7 +9632,7 @@ multiclass SIMDIndexedHSPatterns(NAME # v4i16_indexed) $Rn, - (SUBREG_TO_REG (i32 0), (v4i16 V64_lo:$Rm), dsub), + (SUBREG_TO_REG (v4i16 V64_lo:$Rm), dsub), (UImmS1XForm $idx))>; def : Pat<(v4i16 (OpNodeLaneQ @@ -9645,7 +9645,7 @@ multiclass SIMDIndexedHSPatterns(NAME # v8i16_indexed) $Rn, - (SUBREG_TO_REG (i32 0), $Rm, dsub), + (SUBREG_TO_REG $Rm, dsub), (UImmS1XForm $idx))>; def : Pat<(v8i16 (OpNodeLaneQ @@ -9658,7 +9658,7 @@ multiclass SIMDIndexedHSPatterns(NAME # v2i32_indexed) $Rn, - (SUBREG_TO_REG (i32 0), (v2i32 V64_lo:$Rm), dsub), + (SUBREG_TO_REG (v2i32 V64_lo:$Rm), dsub), (UImmS1XForm $idx))>; def : Pat<(v2i32 (OpNodeLaneQ @@ -9671,7 +9671,7 @@ multiclass SIMDIndexedHSPatterns(NAME # v4i32_indexed) $Rn, - (SUBREG_TO_REG (i32 0), $Rm, dsub), + (SUBREG_TO_REG $Rm, dsub), (UImmS1XForm $idx))>; def : Pat<(v4i32 (OpNodeLaneQ diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 1775e3de8c8c5..a6ca2c5cdaa07 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -823,15 +823,13 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, case AArch64::SUBREG_TO_REG: // Check for the following way to define an 64-bit immediate: // %0:gpr32 = MOVi32imm 1 - // %1:gpr64 = SUBREG_TO_REG 0, %0:gpr32, %subreg.sub_32 - if (!DefMI->getOperand(1).isImm() || DefMI->getOperand(1).getImm() != 0) + // %1:gpr64 = SUBREG_TO_REG %0:gpr32, %subreg.sub_32 + if (!DefMI->getOperand(1).isReg()) return 0; - if (!DefMI->getOperand(2).isReg()) + if (!DefMI->getOperand(2).isImm() || + DefMI->getOperand(2).getImm() != AArch64::sub_32) return 0; - if (!DefMI->getOperand(3).isImm() || - DefMI->getOperand(3).getImm() != AArch64::sub_32) - return 0; - DefMI = MRI.getVRegDef(DefMI->getOperand(2).getReg()); + DefMI = MRI.getVRegDef(DefMI->getOperand(1).getReg()); if (DefMI->getOpcode() != AArch64::MOVi32imm) return 0; if (!DefMI->getOperand(1).isImm() || DefMI->getOperand(1).getImm() != 1) @@ -3557,12 +3555,11 @@ bool AArch64InstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, // ldr Xd, [Xn, Wm, uxtw #N] // Zero-extension looks like an ORRWrs followed by a SUBREG_TO_REG. - if (AddrI.getOperand(1).getImm() != 0 || - AddrI.getOperand(3).getImm() != AArch64::sub_32) + if (AddrI.getOperand(2).getImm() != AArch64::sub_32) return false; const MachineRegisterInfo &MRI = AddrI.getMF()->getRegInfo(); - Register OffsetReg = AddrI.getOperand(2).getReg(); + Register OffsetReg = AddrI.getOperand(1).getReg(); if (!OffsetReg.isVirtual() || !MRI.hasOneNonDBGUse(OffsetReg)) return false; @@ -8029,7 +8026,7 @@ static bool getGatherLanePattern(MachineInstr &Root, return false; // Verify that the subreg to reg loads an integer into the first lane. - auto Lane0LoadReg = CurrInstr->getOperand(2).getReg(); + auto Lane0LoadReg = CurrInstr->getOperand(1).getReg(); unsigned SingleLaneSizeInBits = 128 / NumLanes; if (TRI->getRegSizeInBits(Lane0LoadReg, MRI) != SingleLaneSizeInBits) return false; @@ -8133,7 +8130,7 @@ generateGatherLanePattern(MachineInstr &Root, MachineInstr *SubregToReg = CurrInstr; LoadToLaneInstrs.push_back( - MRI.getUniqueVRegDef(SubregToReg->getOperand(2).getReg())); + MRI.getUniqueVRegDef(SubregToReg->getOperand(1).getReg())); auto LoadToLaneInstrsAscending = llvm::reverse(LoadToLaneInstrs); const TargetRegisterClass *FPR128RegClass = @@ -8237,7 +8234,6 @@ generateGatherLanePattern(MachineInstr &Root, auto SubRegToRegInstr = BuildMI(MF, MIMetadata(Root), TII->get(SubregToReg->getOpcode()), DestRegForSubregToReg) - .addImm(0) .addReg(DestRegForMiddleIndex, getKillRegState(true)) .addImm(SubregType); InstrIdxForVirtReg.insert( diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 212c3891e1387..3206649221dd3 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -1224,8 +1224,9 @@ def AArch64rshrnb_pf : PatFrags<(ops node:$rs, node:$i), [(AArch64rshrnb node:$rs, node:$i), (int_aarch64_sve_rshrnb node:$rs, node:$i)]>; -def AArch64CttzElts : SDNode<"AArch64ISD::CTTZ_ELTS", SDTypeProfile<1, 1, - [SDTCisInt<0>, SDTCisVec<1>]>, []>; +// res = cttz.elts(pg, op) +def AArch64CttzElts : SDNode<"AArch64ISD::CTTZ_ELTS", SDTypeProfile<1, 2, + [SDTCisInt<0>, SDTCVecEltisVT<1,i1>, SDTCisSameAs<1,2>]>, []>; // NEON Load/Store with post-increment base updates. // TODO: Complete SDTypeProfile constraints. @@ -2213,10 +2214,21 @@ let Predicates = [HasPAuth] in { let Uses = [X16]; } + // AArch64AsmPrinter can clobber the $AddrDisc register as long as it is + // marked "killed", otherwise an assertion in emitPtrauthDiscriminator checks + // that $Scratch != $AddrDisc. The problem is that it is always correct to + // *omit* the "killed" flag, thus an instruction like this is valid: + // + // $x8, $x9 = AUTxMxN $x8, 0, 12345, /* is actually killed */ $x9, implicit-def $nzcv + // // $x9 is dead past this point + // + // While it is possible to allow emitPtrauthDiscriminator to clobber $Scratch + // iff ($AddrDisc is killed OR $Scratch == $AddrDisc), it is easier and more + // straightforward to mark $Scratch as @earlyclobber. def AUTxMxN : Pseudo<(outs GPR64:$AuthVal, GPR64common:$Scratch), (ins GPR64:$Val, i32imm:$Key, i64imm:$Disc, GPR64:$AddrDisc), - [], "$AuthVal = $Val">, Sched<[WriteI, ReadI]> { + [], "$AuthVal = $Val,@earlyclobber $Scratch">, Sched<[WriteI, ReadI]> { let isCodeGenOnly = 1; let hasSideEffects = 1; let mayStore = 0; @@ -2264,6 +2276,26 @@ let Predicates = [HasPAuth] in { let Uses = [X16]; } + // Similiar to AUTPAC, except a 32bit value is loaded at Addend offset from + // pointer and this value is added to the pointer before signing. This + // directly manipulates x16/x17, which are the only registers the OS + // guarantees are safe to use for sensitive operations. + def AUTRELLOADPAC + : Pseudo<(outs), + (ins i32imm:$AUTKey, i64imm:$AUTDisc, GPR64:$AUTAddrDisc, + i32imm:$PACKey, i64imm:$PACDisc, GPR64noip:$PACAddrDisc, + i64imm:$Addend), + []>, + Sched<[WriteI, ReadI]> { + let isCodeGenOnly = 1; + let hasSideEffects = 1; + let mayStore = 0; + let mayLoad = 1; + let Size = 84; + let Defs = [X16, X17, NZCV]; + let Uses = [X16]; + } + // Materialize a signed global address, with adrp+add and PAC. def MOVaddrPAC : Pseudo<(outs), (ins i64imm:$Addr, i32imm:$Key, @@ -2638,7 +2670,7 @@ let Predicates = [OptimizedGISelOrOtherSelector] in { // The SUBREG_TO_REG isn't eliminated at -O0, which can result in pointless // copies. def : Pat<(i64 i64imm_32bit:$src), - (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>; + (SUBREG_TO_REG (MOVi32imm (trunc_imm imm:$src)), sub_32)>; } // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model). @@ -3294,7 +3326,7 @@ def : Pat<(not logical_shifted_reg64:$Rm_and_shift), // Emit (and 0xFFFFFFFF) as a ORRWrr move which may be eliminated. let AddedComplexity = 6 in def : Pat<(i64 (and GPR64:$Rn, 0xffffffff)), - (SUBREG_TO_REG (i64 0), (ORRWrr WZR, (EXTRACT_SUBREG GPR64:$Rn, sub_32)), sub_32)>; + (SUBREG_TO_REG (ORRWrr WZR, (EXTRACT_SUBREG GPR64:$Rn, sub_32)), sub_32)>; //===----------------------------------------------------------------------===// @@ -3876,13 +3908,11 @@ let Predicates = [IsLE] in { multiclass ExtLoadTo64ROPat { def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), - (SUBREG_TO_REG (i64 0), - (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), + (SUBREG_TO_REG (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), sub_32)>; def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), - (SUBREG_TO_REG (i64 0), - (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), + (SUBREG_TO_REG (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), sub_32)>; } @@ -4008,15 +4038,15 @@ defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb", uimm12s1:$offset)))]>; // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), - (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; + (SUBREG_TO_REG (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), - (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; + (SUBREG_TO_REG (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; // zextloadi1 -> zextloadi8 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), - (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; + (SUBREG_TO_REG (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; // extload -> zextload def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), @@ -4026,13 +4056,13 @@ def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>; def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), - (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; + (SUBREG_TO_REG (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), - (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; + (SUBREG_TO_REG (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>; def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), - (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; + (SUBREG_TO_REG (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))), - (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; + (SUBREG_TO_REG (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>; // load sign-extended half-word defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh", @@ -4062,7 +4092,7 @@ defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw", // load zero-extended word def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))), - (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; + (SUBREG_TO_REG (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>; // Pre-fetch. def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm", @@ -4105,7 +4135,7 @@ def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw", let AddedComplexity = 20 in { def : Pat<(i64 (zextloadi32 (AArch64adr alignedglobal:$label))), - (SUBREG_TO_REG (i64 0), (LDRWl $label), sub_32)>; + (SUBREG_TO_REG (LDRWl $label), sub_32)>; } // prefetch @@ -4195,13 +4225,13 @@ def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; // unscaled zext def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), (LDURHHi GPR64sp:$Rn, simm9:$offset)>; @@ -4210,13 +4240,13 @@ def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), (LDURBBi GPR64sp:$Rn, simm9:$offset)>; def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; //--- @@ -4273,9 +4303,9 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]", // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>; def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), - (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; + (SUBREG_TO_REG (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>; // load sign-extended half-word defm LDURSHW @@ -4329,33 +4359,33 @@ multiclass LoadInsertVTPatterns; + (SUBREG_TO_REG (LoadInst GPR64sp:$Rn, AddrImm:$offset), SubReg)>; // Unscaled def : Pat <(vector_insert (VT immAllZerosV), (ScalarVT (LoadOp (UnscaledAddr GPR64sp:$Rn, simm9:$offset))), (i64 0)), - (SUBREG_TO_REG (i64 0), (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>; + (SUBREG_TO_REG (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>; // roW def : Pat <(vector_insert (VT immAllZerosV), (ScalarVT (LoadOp (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))), (i64 0)), - (SUBREG_TO_REG (i64 0), (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>; + (SUBREG_TO_REG (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>; // roX def : Pat <(vector_insert (VT immAllZerosV), (ScalarVT (LoadOp (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))), (i64 0)), - (SUBREG_TO_REG (i64 0), (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>; + (SUBREG_TO_REG (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>; // Undef equivalents of the patterns above. def : Pat <(VT (vec_ins_or_scal_vec (ScalarVT (LoadOp (Addr GPR64sp:$Rn, AddrImm:$offset))))), - (SUBREG_TO_REG (i64 0), (LoadInst GPR64sp:$Rn, AddrImm:$offset), SubReg)>; + (SUBREG_TO_REG (LoadInst GPR64sp:$Rn, AddrImm:$offset), SubReg)>; def : Pat <(VT (vec_ins_or_scal_vec (ScalarVT (LoadOp (UnscaledAddr GPR64sp:$Rn, simm9:$offset))))), - (SUBREG_TO_REG (i64 0), (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>; + (SUBREG_TO_REG (UnscaledLoadInst GPR64sp:$Rn, simm9:$offset), SubReg)>; def : Pat <(VT (vec_ins_or_scal_vec (ScalarVT (LoadOp (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))))), - (SUBREG_TO_REG (i64 0), (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>; + (SUBREG_TO_REG (ROWLoadInst GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend), SubReg)>; def : Pat <(VT (vec_ins_or_scal_vec (ScalarVT (LoadOp (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))))), - (SUBREG_TO_REG (i64 0), (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>; + (SUBREG_TO_REG (ROXLoadInst GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend), SubReg)>; } multiclass LoadInsertPatterns { // 8-bit loads. def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))), - (SUBREG_TO_REG (i64 0), (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; + (SUBREG_TO_REG (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))), - (SUBREG_TO_REG (i64 0), (LDURBi GPR64sp:$Rn, simm9:$offset), bsub)>; + (SUBREG_TO_REG (LDURBi GPR64sp:$Rn, simm9:$offset), bsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$extend), bsub)>; + (SUBREG_TO_REG (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$extend), bsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp8 (ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$extend), bsub)>; + (SUBREG_TO_REG (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$extend), bsub)>; // 16-bit loads. def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))), - (SUBREG_TO_REG (i64 0), (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; + (SUBREG_TO_REG (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))), - (SUBREG_TO_REG (i64 0), (LDURHi GPR64sp:$Rn, simm9:$offset), hsub)>; + (SUBREG_TO_REG (LDURHi GPR64sp:$Rn, simm9:$offset), hsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$extend), hsub)>; + (SUBREG_TO_REG (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$extend), hsub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp16 (ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$extend), hsub)>; + (SUBREG_TO_REG (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$extend), hsub)>; } // Extended multiclass that includes 32-bit loads in addition to 8-bit and 16-bit. @@ -4450,13 +4480,13 @@ multiclass ExtLoad8_16_32AllModes; + (SUBREG_TO_REG (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))), - (SUBREG_TO_REG (i64 0), (LDURSi GPR64sp:$Rn, simm9:$offset), ssub)>; + (SUBREG_TO_REG (LDURSi GPR64sp:$Rn, simm9:$offset), ssub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$extend), ssub)>; + (SUBREG_TO_REG (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$extend), ssub)>; def : Pat<(OutTy (OuterOp (InnerTy (LoadOp32 (ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$extend))))), - (SUBREG_TO_REG (i64 0), (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$extend), ssub)>; + (SUBREG_TO_REG (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$extend), ssub)>; } // Instantiate bitconvert patterns for floating-point types. @@ -7027,7 +7057,7 @@ def : Pat<(v1i64 (AArch64vashr (v1i64 V64:$Rn), (i32 63))), // f16 -> i16 conversions leave the bit pattern in a f32 class F16ToI16ScalarPat : Pat<(f32 (cvt_isd (f16 FPR16:$Rn))), - (f32 (SUBREG_TO_REG (i64 0), (instr FPR16:$Rn), hsub))>; + (f32 (SUBREG_TO_REG (instr FPR16:$Rn), hsub))>; let Predicates = [HasFullFP16] in { def : F16ToI16ScalarPat; @@ -7429,7 +7459,7 @@ multiclass AddSubHNPatterns; + (ADDHN2 (SUBREG_TO_REG V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; def : Pat<(VT64 (trunc (VT128 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 Shift))))), (SUBHN V128:$Rn, V128:$Rm)>; @@ -7437,7 +7467,7 @@ multiclass AddSubHNPatterns; + (SUBHN2 (SUBREG_TO_REG V64:$Rd, dsub), V128:$Rn, V128:$Rm)>; // xor by -1 can also be treated as sub def : Pat<(VT64 (trunc (VT128 (AArch64vlshr (xor V128:$Rn, immAllOnesV:$Rm), (i32 Shift))))), @@ -7446,7 +7476,7 @@ multiclass AddSubHNPatterns; + (SUBHN2 (SUBREG_TO_REG V64:$Rd, dsub), V128:$Rm, V128:$Rn)>; } defm : AddSubHNPatterns { V64:$Rm, (i32 imm:$imm))), (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, - (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), + (SUBREG_TO_REG V64:$Rm, dsub), (AdjustExtImm imm:$imm)), dsub)>; } @@ -7865,36 +7895,32 @@ def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx), def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx)))), (i64 0xff))), - (SUBREG_TO_REG (i64 0), (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx)), sub_32)>; + (SUBREG_TO_REG (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx)), sub_32)>; def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx)))), (i64 0xffff))), - (SUBREG_TO_REG (i64 0), (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx)), sub_32)>; + (SUBREG_TO_REG (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx)), sub_32)>; defm INS : SIMDIns; def : Pat<(v16i8 (vec_ins_or_scal_vec GPR32:$Rn)), - (SUBREG_TO_REG (i32 0), - (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v8i8 (vec_ins_or_scal_vec GPR32:$Rn)), - (SUBREG_TO_REG (i32 0), - (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; // The top bits will be zero from the FMOVWSr def : Pat<(v8i8 (bitconvert (i64 (zext GPR32:$Rn)))), - (SUBREG_TO_REG (i32 0), (f32 (FMOVWSr GPR32:$Rn)), ssub)>; + (SUBREG_TO_REG (f32 (FMOVWSr GPR32:$Rn)), ssub)>; def: Pat<(f64 (bitconvert (i64 (zext (i32 (bitconvert (f32 FPR32:$Rn))))))), - (SUBREG_TO_REG (i32 0), (f32 (FMOVSr FPR32:$Rn)), ssub)>; + (SUBREG_TO_REG (f32 (FMOVSr FPR32:$Rn)), ssub)>; def: Pat<(f32 (bitconvert (i32 (trunc (i64 (bitconvert (f64 FPR64:$Rn))))))), (f32 (EXTRACT_SUBREG FPR64:$Rn, ssub))>; def : Pat<(v8i16 (vec_ins_or_scal_vec GPR32:$Rn)), - (SUBREG_TO_REG (i32 0), - (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v4i16 (vec_ins_or_scal_vec GPR32:$Rn)), - (SUBREG_TO_REG (i32 0), - (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; + (SUBREG_TO_REG (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; def : Pat<(v2i32 (vec_ins_or_scal_vec GPR32:$Rn)), (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GPR32:$Rn, ssub)>; @@ -8074,7 +8100,7 @@ multiclass Neon_INS_elt_pattern; // Extracting from another NEON vector @@ -8092,12 +8118,12 @@ multiclass Neon_INS_elt_pattern; + (VT128 (SUBREG_TO_REG V64:$Rn, dsub)), imm:$Immn)>; def : Pat<(VT64 (vector_insert V64:$src, (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))), (i64 imm:$Immd))), - (EXTRACT_SUBREG (INS (VT128 (SUBREG_TO_REG (i64 0), V64:$src, dsub)), + (EXTRACT_SUBREG (INS (VT128 (SUBREG_TO_REG V64:$src, dsub)), imm:$Immd, V128:$Rn, imm:$Immn), dsub)>; @@ -8105,8 +8131,8 @@ multiclass Neon_INS_elt_pattern; } @@ -8149,7 +8175,6 @@ multiclass Neon_INS_elt_ext_pattern; @@ -8159,13 +8184,12 @@ multiclass Neon_INS_elt_ext_pattern; def : Pat<(OutVT (scalar_to_vector (i32 (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))))), (EXTRACT_SUBREG (VT128 (SUBREG_TO_REG - (i64 0), (DUP V128:$Rn, imm:$Immn), DUPSub)), dsub)>; @@ -8188,9 +8212,9 @@ def : Pat<(f64 (bitconvert (i64 (vector_extract v2i64:$src, (i64 0))))), // f32 bitcast(vector_extract(v4i32 src, lane)) -> DUPi32(src, lane) def : Pat<(f32 (bitconvert (i32 (vector_extract v16i8:$src, imm:$Immd)))), - (EXTRACT_SUBREG (v16i8 (SUBREG_TO_REG (i64 0), (DUPi8 V128:$src, imm:$Immd), bsub)), ssub)>; + (EXTRACT_SUBREG (v16i8 (SUBREG_TO_REG (DUPi8 V128:$src, imm:$Immd), bsub)), ssub)>; def : Pat<(f32 (bitconvert (i32 (vector_extract v8i16:$src, imm:$Immd)))), - (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (DUPi16 V128:$src, imm:$Immd), hsub)), ssub)>; + (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (DUPi16 V128:$src, imm:$Immd), hsub)), ssub)>; def : Pat<(f32 (bitconvert (i32 (vector_extract v4i32:$src, imm:$Immd)))), (DUPi32 V128:$src, imm:$Immd)>; def : Pat<(f64 (bitconvert (i64 (vector_extract v2i64:$src, imm:$Immd)))), @@ -8230,7 +8254,7 @@ multiclass ConcatPatd register mov, which // will implicitly clear the upper bits. def : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), immAllZerosV)), - (SUBREG_TO_REG (i64 0), (FMOVDr V64:$Rn), dsub)>; + (SUBREG_TO_REG (FMOVDr V64:$Rn), dsub)>; // If the high lanes are undef we can just ignore them: def : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)), @@ -8269,17 +8293,17 @@ defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", AArch64fminnmv>; defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", AArch64fminv>; def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (sext (v8i8 V64:$op))))), (i64 0))), - (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (SADDLVv8i8v V64:$op), hsub)), ssub)>; + (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (SADDLVv8i8v V64:$op), hsub)), ssub)>; def : Pat<(i32 (vector_extract (v8i16 (AArch64uaddv (v8i16 (zext (v8i8 V64:$op))))), (i64 0))), - (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub)), ssub)>; + (EXTRACT_SUBREG (v8i16 (SUBREG_TO_REG (UADDLVv8i8v V64:$op), hsub)), ssub)>; def : Pat<(v8i16 (AArch64uaddv (v8i16 (sext (v8i8 V64:$op))))), - (v8i16 (SUBREG_TO_REG (i64 0), (SADDLVv8i8v V64:$op), hsub))>; + (v8i16 (SUBREG_TO_REG (SADDLVv8i8v V64:$op), hsub))>; def : Pat<(v8i16 (AArch64uaddv (v8i16 (zext (v8i8 V64:$op))))), - (v8i16 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>; + (v8i16 (SUBREG_TO_REG (UADDLVv8i8v V64:$op), hsub))>; def : Pat<(v4i32 (AArch64uaddv (v4i32 (sext (v4i16 V64:$op))))), - (v4i32 (SUBREG_TO_REG (i64 0), (SADDLVv4i16v V64:$op), ssub))>; + (v4i32 (SUBREG_TO_REG (SADDLVv4i16v V64:$op), ssub))>; def : Pat<(v4i32 (AArch64uaddv (v4i32 (zext (v4i16 V64:$op))))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv4i16v V64:$op), ssub))>; + (v4i32 (SUBREG_TO_REG (UADDLVv4i16v V64:$op), ssub))>; multiclass SIMDAcrossLaneLongPairIntrinsic { // Patterns for addv(addlp(x)) ==> addlv @@ -8325,29 +8349,29 @@ defm : SIMDAcrossLaneLongPairIntrinsicGISel<"UADDLV", AArch64uaddlp>; defm : SIMDAcrossLaneLongPairIntrinsicGISel<"SADDLV", AArch64saddlp>; def : Pat<(v2i64 (AArch64uaddlv (v4i32 (AArch64uaddlp (v8i16 V128:$op))))), - (v2i64 (SUBREG_TO_REG (i64 0), (UADDLVv8i16v V128:$op), ssub))>; + (v2i64 (SUBREG_TO_REG (UADDLVv8i16v V128:$op), ssub))>; def : Pat<(v4i32 (AArch64uaddlv (v8i16 (AArch64uaddlp (v16i8 V128:$op))))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv16i8v V128:$op), hsub))>; + (v4i32 (SUBREG_TO_REG (UADDLVv16i8v V128:$op), hsub))>; def : Pat<(v4i32 (AArch64uaddlv (v4i16 (AArch64uaddlp (v8i8 V64:$op))))), - (v4i32 (SUBREG_TO_REG (i64 0), (UADDLVv8i8v V64:$op), hsub))>; + (v4i32 (SUBREG_TO_REG (UADDLVv8i8v V64:$op), hsub))>; multiclass SIMDAcrossLaneLongReductionIntrinsic { def : Pat<(v4i32 (addlv (v8i8 V64:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v8i8v") V64:$Rn), hsub))>; + (v4i32 (SUBREG_TO_REG (!cast(Opc#"v8i8v") V64:$Rn), hsub))>; def : Pat<(v4i32 (addlv (v4i16 V64:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v4i16v") V64:$Rn), ssub))>; + (v4i32 (SUBREG_TO_REG (!cast(Opc#"v4i16v") V64:$Rn), ssub))>; def : Pat<(v4i32 (addlv (v16i8 V128:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v16i8v") V128:$Rn), hsub))>; + (v4i32 (SUBREG_TO_REG (!cast(Opc#"v16i8v") V128:$Rn), hsub))>; def : Pat<(v4i32 (addlv (v8i16 V128:$Rn))), - (v4i32 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v8i16v") V128:$Rn), ssub))>; + (v4i32 (SUBREG_TO_REG (!cast(Opc#"v8i16v") V128:$Rn), ssub))>; def : Pat<(v2i64 (addlv (v4i32 V128:$Rn))), - (v2i64 (SUBREG_TO_REG (i64 0), (!cast(Opc#"v4i32v") V128:$Rn), dsub))>; + (v2i64 (SUBREG_TO_REG (!cast(Opc#"v4i32v") V128:$Rn), dsub))>; } defm : SIMDAcrossLaneLongReductionIntrinsic<"UADDLV", AArch64uaddlv>; @@ -8636,19 +8660,19 @@ def : Pat<(v8bf16 immAllZerosV), (MOVIv2d_ns (i32 0))>; // Prefer NEON instructions when zeroing ZPRs because they are potentially zero-latency. let AddedComplexity = 5 in { -def : Pat<(nxv2i64 (splat_vector (i64 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv4i32 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv8i16 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv16i8 (splat_vector (i32 0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv2f64 (splat_vector (f64 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv2f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv4f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv2f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv4f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv8f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv2bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv4bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; -def : Pat<(nxv8bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (i32 0), (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2i64 (splat_vector (i64 0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv4i32 (splat_vector (i32 0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv8i16 (splat_vector (i32 0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv16i8 (splat_vector (i32 0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2f64 (splat_vector (f64 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv4f32 (splat_vector (f32 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv4f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv8f16 (splat_vector (f16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv2bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv4bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; +def : Pat<(nxv8bf16 (splat_vector (bf16 fpimm0))), (SUBREG_TO_REG (MOVIv2d_ns (i32 0)), zsub)>; } def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>; @@ -8827,12 +8851,12 @@ multiclass FMLSIndexedAfterNegPatterns { (i64 0))), VectorIndexS:$idx)))), (FMLSv2i32_indexed V64:$Rd, V64:$Rn, - (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), + (SUBREG_TO_REG V64:$Rm, dsub), VectorIndexS:$idx)>; def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (AArch64dup (f32 (fneg FPR32Op:$Rm))))), (FMLSv2i32_indexed V64:$Rd, V64:$Rn, - (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; + (SUBREG_TO_REG FPR32Op:$Rm, ssub), (i64 0))>; // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit // and DUP scalar. @@ -8848,12 +8872,12 @@ multiclass FMLSIndexedAfterNegPatterns { (i64 0))), VectorIndexS:$idx)))), (FMLSv4i32_indexed V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), + (SUBREG_TO_REG V64:$Rm, dsub), VectorIndexS:$idx)>; def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (AArch64dup (f32 (fneg FPR32Op:$Rm))))), (FMLSv4i32_indexed V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>; + (SUBREG_TO_REG FPR32Op:$Rm, ssub), (i64 0))>; // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar // (DUPLANE from 64-bit would be trivial). @@ -8865,7 +8889,7 @@ multiclass FMLSIndexedAfterNegPatterns { def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (AArch64dup (f64 (fneg FPR64Op:$Rm))))), (FMLSv2i64_indexed V128:$Rd, V128:$Rn, - (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>; + (SUBREG_TO_REG FPR64Op:$Rm, dsub), (i64 0))>; // 2 variants for 32-bit scalar version: extract from .2s or from .4s def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn), @@ -8879,7 +8903,7 @@ multiclass FMLSIndexedAfterNegPatterns { (i64 0))), VectorIndexS:$idx))), (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn, - (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>; + (SUBREG_TO_REG V64:$Rm, dsub), VectorIndexS:$idx)>; // 1 variant for 64-bit scalar version: extract from .1d or from .2d def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn), @@ -9081,6 +9105,38 @@ defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf", defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn", AArch64rshrn>; defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>; +class fixedpoint_vec_f64 + : ComplexPattern">; +class fixedpoint_vec_f32 + : ComplexPattern">; +class fixedpoint_vec_f16 + : ComplexPattern">; +// This thing just allows us to change the type of the node produced. The imm +// value we want is already in V from SelectCVTFixedPointVec. +def fixedpoint_vec_xform : SDNodeXForm; +def gi_fixedpoint_vec_xform : GICustomOperandRenderer<"renderFixedPointXForm">, + GISDNodeXFormEquiv; + +def fixedpoint_v2f64 : fixedpoint_vec_f64; +def fixedpoint_v2f32 : fixedpoint_vec_f32; +def fixedpoint_v4f32 : fixedpoint_vec_f32; +def fixedpoint_v4f16 : fixedpoint_vec_f16; +def fixedpoint_v8f16 : fixedpoint_vec_f16; + +def gi_fixedpoint_v2f64 : GIComplexOperandMatcher, + GIComplexPatternEquiv; +def gi_fixedpoint_v2f32 : GIComplexOperandMatcher, + GIComplexPatternEquiv; +def gi_fixedpoint_v4f32 : GIComplexOperandMatcher, + GIComplexPatternEquiv; +def gi_fixedpoint_v4f16 : GIComplexOperandMatcher, + GIComplexPatternEquiv; +def gi_fixedpoint_v8f16 : GIComplexOperandMatcher, + GIComplexPatternEquiv; + let Predicates = [HasNEON] in { def : Pat<(v2f32 (sint_to_fp (v2i32 (AArch64vashr_exact v2i32:$Vn, i32:$shift)))), (SCVTFv2i32_shift $Vn, vecshiftR32:$shift)>; @@ -9097,7 +9153,7 @@ def : Pat<(v8f16 (sint_to_fp (v8i16 (AArch64vashr_exact v8i16:$Vn, i32:$shift))) (SCVTFv8i16_shift $Vn, vecshiftR16:$shift)>; } -multiclass FCVTPat { +multiclass FCVTPat { // fptosi(fadd(x, x)) -> FCVTZS_shift x, 1 def : Pat<(IVT (fp_to_sint (FVT (fadd RC:$Vn, RC:$Vn)))), (!cast("FCVTZS"#IVT#"_shift") (FVT RC:$Vn), (i32 1))>; @@ -9113,16 +9169,32 @@ multiclass FCVTPat("FCVTZU"#IVT#"_shift") (FVT RC:$Vn), (i32 1))>; def : Pat<(IVT (fp_to_uint_sat_gi (FVT (fadd RC:$Vn, RC:$Vn)))), (!cast("FCVTZU"#IVT#"_shift") (FVT RC:$Vn), (i32 1))>; + + // fptosi(fmul(x, power2)) -> FCVTZS_shift x, log2(power2) + def : Pat<(IVT (fp_to_sint (FVT (fmul FVT:$Vn, fixedpoint:$scale)))), + (!cast("FCVTZS"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>; + def : Pat<(IVT (fp_to_sint_sat (FVT (fmul FVT:$Vn, fixedpoint:$scale)), ScalarVT)), + (!cast("FCVTZS"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>; + def : Pat<(IVT (fp_to_sint_sat_gi (FVT (fmul FVT:$Vn, fixedpoint:$scale)))), + (!cast("FCVTZS"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>; + + // fptoui(fmul(x, power2)) -> FCVTZU_shift x, log2(power2) + def : Pat<(IVT (fp_to_uint (FVT (fmul FVT:$Vn, fixedpoint:$scale)))), + (!cast("FCVTZU"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>; + def : Pat<(IVT (fp_to_uint_sat (FVT (fmul FVT:$Vn, fixedpoint:$scale)), ScalarVT)), + (!cast("FCVTZU"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>; + def : Pat<(IVT (fp_to_uint_sat_gi (FVT (fmul FVT:$Vn, fixedpoint:$scale)))), + (!cast("FCVTZU"#IVT#"_shift") $Vn, (fixedpoint_vec_xform fixedpoint:$scale))>; } let Predicates = [HasNEON] in { -defm : FCVTPat; -defm : FCVTPat; -defm : FCVTPat; +defm : FCVTPat; +defm : FCVTPat; +defm : FCVTPat; } let Predicates = [HasNEON, HasFullFP16] in { -defm : FCVTPat; -defm : FCVTPat; +defm : FCVTPat; +defm : FCVTPat; } // X << 1 ==> X + X @@ -9370,7 +9442,7 @@ def : InstAlias<"uxtl2 $dst.2d, $src1.4s", let Predicates = [HasNEON] in { def : Pat<(f32 (any_fpextend (bf16 FPR16:$Rn))), (f32 (EXTRACT_SUBREG - (v4i32 (SHLLv4i16 (v4i16 (SUBREG_TO_REG (i64 0), (bf16 FPR16:$Rn), hsub)))), + (v4i32 (SHLLv4i16 (v4i16 (SUBREG_TO_REG (bf16 FPR16:$Rn), hsub)))), ssub))>; def : Pat<(v4f32 (any_fpextend (v4bf16 V64:$Rn))), (SHLLv4i16 V64:$Rn)>; @@ -9381,7 +9453,7 @@ def : Pat<(v4f32 (any_fpextend (extract_high_v8bf16 (v8bf16 V128:$Rn)))), def : Pat<(f32 (any_fpextend (bf16 FPR16:$Rn))), (f32 (COPY_TO_REGCLASS (i32 (UBFMWri (COPY_TO_REGCLASS - (f32 (SUBREG_TO_REG (i32 0), (bf16 FPR16:$Rn), hsub)), + (f32 (SUBREG_TO_REG (bf16 FPR16:$Rn), hsub)), GPR32), (i64 16), (i64 15))), FPR32))>; @@ -9706,7 +9778,7 @@ class Ld1Lane64IdxOpPat; @@ -9746,7 +9818,7 @@ class Ld1Lane64Pat; @@ -9794,7 +9866,7 @@ class St1Lane64Pat; def : St1Lane64Pat; @@ -9810,13 +9882,13 @@ multiclass St1LanePost64Pat; def : Pat<(scalar_store (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)), GPR64sp:$Rn, GPR64:$Rm), - (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub), + (ST1 (SUBREG_TO_REG VecListOne64:$Vt, dsub), VecIndex:$idx, GPR64sp:$Rn, $Rm)>; } @@ -9933,14 +10005,14 @@ def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0 // FIXME: Like for X86, these should go in their own separate .td file. // For an anyext, we don't care what the high bits are, so we can perform an -// INSERT_SUBREF into an IMPLICIT_DEF. +// INSERT_SUBREG into an IMPLICIT_DEF. def : Pat<(i64 (anyext GPR32:$src)), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and // then assert the extension has happened. def : Pat<(i64 (zext GPR32:$src)), - (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>; + (SUBREG_TO_REG (ORRWrs WZR, GPR32:$src, 0), sub_32)>; // To sign extend, we use a signed bitfield move instruction (SBFM) on the // containing super-reg. @@ -10861,7 +10933,7 @@ class NTStore64Pat : Pat<(nontemporalstore (VT FPR64:$Rt), (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)), (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub), - (DUPi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)), + (DUPi32 (SUBREG_TO_REG FPR64:$Rt, dsub), (i64 1)), GPR64sp:$Rn, simm7s4:$offset)>; // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64? diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp index 6d7c986eccffc..21ff921da9b8a 100644 --- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp +++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp @@ -26,14 +26,14 @@ // 4. Remove redundant ORRWrs which is generated by zero-extend. // // %3:gpr32 = ORRWrs $wzr, %2, 0 -// %4:gpr64 = SUBREG_TO_REG 0, %3, %subreg.sub_32 +// %4:gpr64 = SUBREG_TO_REG %3, %subreg.sub_32 // // If AArch64's 32-bit form of instruction defines the source operand of // ORRWrs, we can remove the ORRWrs because the upper 32 bits of the source // operand are set to zero. // // 5. %reg = INSERT_SUBREG %reg(tied-def 0), %subreg, subidx -// ==> %reg:subidx = SUBREG_TO_REG 0, %subreg, subidx +// ==> %reg:subidx = SUBREG_TO_REG %subreg, subidx // // 6. %intermediate:gpr32 = COPY %src:fpr128 // %dst:fpr128 = INSvi32gpr %dst_vec:fpr128, dst_index, %intermediate:gpr32 @@ -281,7 +281,7 @@ bool AArch64MIPeepholeOpt::visitORR(MachineInstr &MI) { // Check this ORR comes from below zero-extend pattern. // // def : Pat<(i64 (zext GPR32:$src)), - // (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>; + // (SUBREG_TO_REG (ORRWrs WZR, GPR32:$src, 0), sub_32)>; if (MI.getOperand(3).getImm() != 0) return false; @@ -365,7 +365,7 @@ bool AArch64MIPeepholeOpt::visitINSERT(MachineInstr &MI) { // Check this INSERT_SUBREG comes from below zero-extend pattern. // // From %reg = INSERT_SUBREG %reg(tied-def 0), %subreg, subidx - // To %reg:subidx = SUBREG_TO_REG 0, %subreg, subidx + // To %reg:subidx = SUBREG_TO_REG %subreg, subidx // // We're assuming the first operand to INSERT_SUBREG is irrelevant because a // COPY would destroy the upper part of the register anyway @@ -396,7 +396,6 @@ bool AArch64MIPeepholeOpt::visitINSERT(MachineInstr &MI) { MachineInstr *SubregMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(TargetOpcode::SUBREG_TO_REG), DstReg) - .addImm(0) .add(MI.getOperand(2)) .add(MI.getOperand(3)); LLVM_DEBUG(dbgs() << MI << " replace by:\n: " << *SubregMI << "\n"); @@ -541,7 +540,7 @@ bool AArch64MIPeepholeOpt::checkMovImmInstr(MachineInstr &MI, SubregToRegMI = nullptr; if (MovMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) { SubregToRegMI = MovMI; - MovMI = MRI->getUniqueVRegDef(MovMI->getOperand(2).getReg()); + MovMI = MRI->getUniqueVRegDef(MovMI->getOperand(1).getReg()); if (!MovMI) return false; } @@ -812,7 +811,6 @@ bool AArch64MIPeepholeOpt::visitUBFMXri(MachineInstr &MI) { .addImm(Imms); BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::SUBREG_TO_REG), DstReg64) - .addImm(0) .addReg(DstReg32) .addImm(AArch64::sub_32); MI.eraseFromParent(); @@ -851,10 +849,10 @@ bool AArch64MIPeepholeOpt::visitCopy(MachineInstr &MI) { // Look for SUBREG_TO_REG(ORRWrr(WZR, COPY(X.sub_32))) auto getUXTWSrcReg = [&](MachineInstr *SrcMI) -> Register { if (SrcMI->getOpcode() != AArch64::SUBREG_TO_REG || - SrcMI->getOperand(3).getImm() != AArch64::sub_32 || - !MRI->hasOneNonDBGUse(SrcMI->getOperand(2).getReg())) + SrcMI->getOperand(2).getImm() != AArch64::sub_32 || + !MRI->hasOneNonDBGUse(SrcMI->getOperand(1).getReg())) return AArch64::NoRegister; - MachineInstr *Orr = MRI->getUniqueVRegDef(SrcMI->getOperand(2).getReg()); + MachineInstr *Orr = MRI->getUniqueVRegDef(SrcMI->getOperand(1).getReg()); if (!Orr || Orr->getOpcode() != AArch64::ORRWrr || Orr->getOperand(1).getReg() != AArch64::WZR || !MRI->hasOneNonDBGUse(Orr->getOperand(2).getReg())) diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 8f17adba34cf9..7803dacfcefa4 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -743,6 +743,7 @@ def TuneNeoverseV3 : SubtargetFeature<"neoversev3", "ARMProcFamily", "NeoverseV3 FeatureFuseCmpCSet, FeaturePostRAScheduler, FeatureEnableSelectOptimize, + FeatureUseFixedOverScalableIfEqualCost, FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive, FeatureMaxInterleaveFactor4]>; @@ -756,6 +757,7 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover FeatureFuseCmpCSet, FeaturePostRAScheduler, FeatureEnableSelectOptimize, + FeatureUseFixedOverScalableIfEqualCost, FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive, FeatureMaxInterleaveFactor4]>; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h index 89d1802ab98d5..ac58d8d6b1cc7 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h @@ -53,12 +53,16 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo { const uint32_t *getDarwinCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const; - unsigned getCSRFirstUseCost() const override { + unsigned getCSRCost() const override { // The cost will be compared against BlockFrequency where entry has the // value of 1 << 14. A value of 5 will choose to spill or split really // cold path instead of using a callee-saved register. return 5; } + unsigned getCSRFirstUseCost() const override { + // The cost of 2 means push and pop for each CSR. + return 2; + } const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index dd90bf2622ec3..61db07493260c 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -262,15 +262,15 @@ def AArch64fmaxnm_p_nnan : PatFrag<(ops node:$op1, node:$op2, node:$op3), def SDT_AArch64Arith_Imm : SDTypeProfile<1, 3, [ SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVT<3,i32>, - SDTCVecEltisVT<1,i1>, SDTCisSameAs<0,2> + SDTCVecEltisVT<1,i1>, SDTCisSameNumEltsAs<0,1>, SDTCisSameAs<0,2> ]>; def AArch64asrd_m1 : SDNode<"AArch64ISD::ASRD_MERGE_OP1", SDT_AArch64Arith_Imm>; -def AArch64urshri_p_node : SDNode<"AArch64ISD::URSHR_I_PRED", SDT_AArch64Arith_Imm>; +def AArch64urshri_p : SDNode<"AArch64ISD::URSHR_I_PRED", SDT_AArch64Arith_Imm>; -def AArch64urshri_p : PatFrags<(ops node:$op1, node:$op2, node:$op3), - [(int_aarch64_sve_urshr node:$op1, node:$op2, node:$op3), - (AArch64urshri_p_node node:$op1, node:$op2, node:$op3)]>; +def AArch64urshr : PatFrags<(ops node:$op1, node:$op2, node:$op3), + [(int_aarch64_sve_urshr node:$op1, node:$op2, node:$op3), + (AArch64urshri_p node:$op1, node:$op2, node:$op3)]>; def SDT_AArch64IntExtend : SDTypeProfile<1, 4, [ SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVT<3, OtherVT>, SDTCisVec<4>, @@ -359,6 +359,10 @@ def AArch64ssra : PatFrags<(ops node:$op1, node:$op2, node:$op3), [(int_aarch64_sve_ssra node:$op1, node:$op2, node:$op3), (add node:$op1, (AArch64asr_p (SVEAnyPredicate), node:$op2, (SVEShiftSplatImmR (i32 node:$op3))))]>; +def AArch64ursra : PatFrags<(ops node:$op1, node:$op2, node:$op3), + [(int_aarch64_sve_ursra node:$op1, node:$op2, node:$op3), + (add node:$op1, (AArch64urshri_p (SVEAllActive), node:$op2, node:$op3))]>; + // Replace pattern min(max(v1,v2),v3) by clamp def AArch64sclamp : PatFrags<(ops node:$Zd, node:$Zn, node:$Zm), [(int_aarch64_sve_sclamp node:$Zd, node:$Zn, node:$Zm), @@ -2273,21 +2277,21 @@ let Predicates = [HasSVE_or_SME] in { defm CNTD_XPiI : sve_int_count<0b110, "cntd", int_aarch64_sve_cntd>; defm CNTP_XPP : sve_int_pcount_pred<0b000, "cntp", int_aarch64_sve_cntp>; - def : Pat<(i64 (AArch64CttzElts nxv16i1:$Op1)), - (CNTP_XPP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op1), - (BRKB_PPzP (PTRUE_B 31), PPR:$Op1))>; + def : Pat<(i64 (AArch64CttzElts nxv16i1:$Pg, nxv16i1:$Op1)), + (CNTP_XPP_B (BRKB_PPzP PPR:$Pg, PPR:$Op1), + (BRKB_PPzP PPR:$Pg, PPR:$Op1))>; - def : Pat<(i64 (AArch64CttzElts nxv8i1:$Op1)), - (CNTP_XPP_H (BRKB_PPzP (PTRUE_H 31), PPR:$Op1), - (BRKB_PPzP (PTRUE_H 31), PPR:$Op1))>; + def : Pat<(i64 (AArch64CttzElts nxv8i1:$Pg, nxv8i1:$Op1)), + (CNTP_XPP_H (BRKB_PPzP PPR:$Pg, PPR:$Op1), + (BRKB_PPzP PPR:$Pg, PPR:$Op1))>; - def : Pat<(i64 (AArch64CttzElts nxv4i1:$Op1)), - (CNTP_XPP_S (BRKB_PPzP (PTRUE_S 31), PPR:$Op1), - (BRKB_PPzP (PTRUE_S 31), PPR:$Op1))>; + def : Pat<(i64 (AArch64CttzElts nxv4i1:$Pg, nxv4i1:$Op1)), + (CNTP_XPP_S (BRKB_PPzP PPR:$Pg, PPR:$Op1), + (BRKB_PPzP PPR:$Pg, PPR:$Op1))>; - def : Pat<(i64 (AArch64CttzElts nxv2i1:$Op1)), - (CNTP_XPP_D (BRKB_PPzP (PTRUE_D 31), PPR:$Op1), - (BRKB_PPzP (PTRUE_D 31), PPR:$Op1))>; + def : Pat<(i64 (AArch64CttzElts nxv2i1:$Pg, nxv2i1:$Op1)), + (CNTP_XPP_D (BRKB_PPzP PPR:$Pg, PPR:$Op1), + (BRKB_PPzP PPR:$Pg, PPR:$Op1))>; } defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb", add, int_aarch64_sve_cntb>; @@ -2373,35 +2377,35 @@ let Predicates = [HasSVE_or_SME] in { defm INCP_ZP : sve_int_count_v<0b10000, "incp">; defm DECP_ZP : sve_int_count_v<0b10100, "decp">; - def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv16i1:$Op2)))), - (INCP_XP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op2), GPR64:$Op1)>; + def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv16i1:$Pg, nxv16i1:$Op2)))), + (INCP_XP_B (BRKB_PPzP PPR:$Pg, PPR:$Op2), GPR64:$Op1)>; - def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv16i1:$Op2))))), - (EXTRACT_SUBREG (INCP_XP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op2), + def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv16i1:$Pg, nxv16i1:$Op2))))), + (EXTRACT_SUBREG (INCP_XP_B (BRKB_PPzP PPR:$Pg, PPR:$Op2), (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Op1, sub_32)), sub_32)>; - def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv8i1:$Op2)))), - (INCP_XP_H (BRKB_PPzP (PTRUE_H 31), PPR:$Op2), GPR64:$Op1)>; + def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv8i1:$Pg, nxv8i1:$Op2)))), + (INCP_XP_H (BRKB_PPzP PPR:$Pg, PPR:$Op2), GPR64:$Op1)>; - def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv8i1:$Op2))))), - (EXTRACT_SUBREG (INCP_XP_H (BRKB_PPzP (PTRUE_H 31), PPR:$Op2), + def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv8i1:$Pg, nxv8i1:$Op2))))), + (EXTRACT_SUBREG (INCP_XP_H (BRKB_PPzP PPR:$Pg, PPR:$Op2), (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Op1, sub_32)), sub_32)>; - def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv4i1:$Op2)))), - (INCP_XP_S (BRKB_PPzP (PTRUE_S 31), PPR:$Op2), GPR64:$Op1)>; + def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv4i1:$Pg, nxv4i1:$Op2)))), + (INCP_XP_S (BRKB_PPzP PPR:$Pg, PPR:$Op2), GPR64:$Op1)>; - def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv4i1:$Op2))))), - (EXTRACT_SUBREG (INCP_XP_S (BRKB_PPzP (PTRUE_S 31), PPR:$Op2), + def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv4i1:$Pg, nxv4i1:$Op2))))), + (EXTRACT_SUBREG (INCP_XP_S (BRKB_PPzP PPR:$Pg, PPR:$Op2), (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Op1, sub_32)), sub_32)>; - def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv2i1:$Op2)))), - (INCP_XP_D (BRKB_PPzP (PTRUE_D 31), PPR:$Op2), GPR64:$Op1)>; + def : Pat<(i64 (add GPR64:$Op1, (i64 (AArch64CttzElts nxv2i1:$Pg, nxv2i1:$Op2)))), + (INCP_XP_D (BRKB_PPzP PPR:$Pg, PPR:$Op2), GPR64:$Op1)>; - def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv2i1:$Op2))))), - (EXTRACT_SUBREG (INCP_XP_D (BRKB_PPzP (PTRUE_D 31), PPR:$Op2), + def : Pat<(i32 (add GPR32:$Op1, (trunc (i64 (AArch64CttzElts nxv2i1:$Pg, nxv2i1:$Op2))))), + (EXTRACT_SUBREG (INCP_XP_D (BRKB_PPzP PPR:$Pg, PPR:$Op2), (INSERT_SUBREG (IMPLICIT_DEF), GPR32:$Op1, sub_32)), sub_32)>; @@ -3638,9 +3642,9 @@ let Predicates = [HasSVE_or_SME] in { def : Pat<(i32 (and (vector_extract nxv8i16:$vec, VectorIndexH:$index), 0xffff)), (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>; def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index)))), (i64 0xff))), - (SUBREG_TO_REG (i64 0), (i32 (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)), sub_32)>; + (SUBREG_TO_REG (i32 (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)), sub_32)>; def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index)))), (i64 0xffff))), - (SUBREG_TO_REG (i64 0), (i32 (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)), sub_32)>; + (SUBREG_TO_REG (i32 (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)), sub_32)>; } // End HasNEON // Extract first element from vector. @@ -3936,7 +3940,7 @@ let Predicates = [HasSVE2_or_SME] in { defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left_dup<0b0110, "sqshl", "SQSHL_ZPZI", int_aarch64_sve_sqshl>; defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left_dup<0b0111, "uqshl", "UQSHL_ZPZI", int_aarch64_sve_uqshl>; defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right< 0b1100, "srshr", "SRSHR_ZPZI", int_aarch64_sve_srshr>; - defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right< 0b1101, "urshr", "URSHR_ZPZI", AArch64urshri_p>; + defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right< 0b1101, "urshr", "URSHR_ZPZI", AArch64urshr>; defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu", "SQSHLU_ZPZI", int_aarch64_sve_sqshlu>; defm SQSHL_ZPZI : sve_int_shift_pred_bhsd; @@ -3997,7 +4001,7 @@ let Predicates = [HasSVE2_or_SME] in { defm SSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b00, "ssra", AArch64ssra>; defm USRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b01, "usra", AArch64usra>; defm SRSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b10, "srsra", int_aarch64_sve_srsra, int_aarch64_sve_srshr>; - defm URSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b11, "ursra", int_aarch64_sve_ursra, AArch64urshri_p>; + defm URSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b11, "ursra", AArch64ursra, int_aarch64_sve_urshr>; // SVE2 complex integer add defm CADD_ZZI : sve2_int_cadd<0b0, "cadd", int_aarch64_sve_cadd_x>; diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index bdf06e39d7367..c9d775367f929 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -1071,9 +1071,11 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, EVT VecVT = getTLI()->getValueType(DL, RetTy); unsigned EltSizeInBytes = cast(ICA.getArgs()[2])->getZExtValue(); - if (is_contained({1u, 2u, 4u, 8u}, EltSizeInBytes) && - VecVT.getVectorMinNumElements() == (16 / EltSizeInBytes)) - return 1; + if (!is_contained({1u, 2u, 4u, 8u}, EltSizeInBytes) || + VecVT.getVectorMinNumElements() != (16 / EltSizeInBytes)) + break; + // For fixed-vector types we need to AND the mask with a ptrue vl. + return isa(RetTy) ? 2 : 1; } break; } diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index b05da9376d966..32c91831d9fb7 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -482,6 +482,12 @@ class AArch64InstructionSelector : public InstructionSelector { ComplexRendererFns selectExtractHigh(MachineOperand &Root) const; + ComplexRendererFns selectCVTFixedPointVec(MachineOperand &Root) const; + ComplexRendererFns + selectCVTFixedPointVecBase(const MachineOperand &Root) const; + void renderFixedPointXForm(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx = -1) const; + void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx = -1) const; void renderLogicalImm32(MachineInstrBuilder &MIB, const MachineInstr &I, @@ -1071,7 +1077,6 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, Register PromoteReg = MRI.createVirtualRegister(PromotionRC); BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG), PromoteReg) - .addImm(0) .addUse(SrcReg) .addImm(SubReg); MachineOperand &RegOp = I.getOperand(1); @@ -1792,7 +1797,8 @@ bool AArch64InstructionSelector::selectCompareBranch( .addImm(AArch64CC::NE) .addMBB(I.getOperand(1).getMBB()); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI); + return true; } /// Returns the element immediate value of a vector shift operand if found. @@ -2290,7 +2296,8 @@ bool AArch64InstructionSelector::earlySelectSHL(MachineInstr &I, RenderFn(NewI); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI); + return true; } bool AArch64InstructionSelector::contractCrossBankCopyIntoStore( @@ -2529,8 +2536,10 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { if (!I.isPreISelOpcode() || Opcode == TargetOpcode::G_PHI) { // Certain non-generic instructions also need some special handling. - if (Opcode == TargetOpcode::LOAD_STACK_GUARD) - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + if (Opcode == TargetOpcode::LOAD_STACK_GUARD) { + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; + } if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) { const Register DefReg = I.getOperand(0).getReg(); @@ -2618,7 +2627,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { .addImm(LSB) .addImm(LSB + Width - 1); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*BitfieldInst, TII, TRI, RBI); + constrainSelectedInstRegOperands(*BitfieldInst, TII, TRI, RBI); + return true; } case TargetOpcode::G_BRCOND: return selectCompareBranch(I, MF, MRI); @@ -2632,10 +2642,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { MI.addImm(*BADisc); MI.addReg(/*AddrDisc=*/AArch64::XZR); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + return true; } I.setDesc(TII.get(AArch64::BR)); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } case TargetOpcode::G_BRJT: @@ -2650,7 +2662,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { if (BaseMI->getOpcode() != AArch64::ADRP) { I.setDesc(TII.get(AArch64::ADDXri)); I.addOperand(MachineOperand::CreateImm(0)); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } assert(TM.getCodeModel() == CodeModel::Small && "Expected small code model"); @@ -2662,7 +2675,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { .addGlobalAddress(Op2.getGlobal(), Op2.getOffset(), Op2.getTargetFlags()); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MovAddr, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MovAddr, TII, TRI, RBI); + return true; } case TargetOpcode::G_FCONSTANT: @@ -2837,7 +2851,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { if (SrcSize < 64) { assert(SrcSize == 32 && DstTy.getSizeInBits() == 16 && "unexpected G_EXTRACT types"); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); @@ -2848,7 +2863,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { AArch64::GPR32RegClass, MRI); I.getOperand(0).setReg(DstReg); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } case TargetOpcode::G_INSERT: { @@ -2869,21 +2885,22 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { if (DstSize < 64) { assert(DstSize == 32 && SrcTy.getSizeInBits() == 16 && "unexpected G_INSERT types"); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } Register SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); BuildMI(MBB, I.getIterator(), I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG)) .addDef(SrcReg) - .addImm(0) .addUse(I.getOperand(2).getReg()) .addImm(AArch64::sub_32); RBI.constrainGenericRegister(I.getOperand(2).getReg(), AArch64::GPR32RegClass, MRI); I.getOperand(2).setReg(SrcReg); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } case TargetOpcode::G_FRAME_INDEX: { // allocas and G_FRAME_INDEX are only supported in addrspace(0). @@ -2898,7 +2915,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { I.addOperand(MachineOperand::CreateImm(0)); I.addOperand(MachineOperand::CreateImm(0)); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } case TargetOpcode::G_GLOBAL_VALUE: { @@ -2940,7 +2958,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(), OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC); } - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } case TargetOpcode::G_PTRAUTH_GLOBAL_VALUE: @@ -3041,7 +3060,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { // Generate a SUBREG_TO_REG to extend it. MIB.setInsertPt(MIB.getMBB(), std::next(LdSt.getIterator())); MIB.buildInstr(AArch64::SUBREG_TO_REG, {OldDst}, {}) - .addImm(0) .addUse(NewDst) .addImm(SubReg); auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB); @@ -3116,14 +3134,14 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { MIB.setInsertPt(MIB.getMBB(), std::next(LoadStore->getIterator())); MIB.buildInstr(AArch64::SUBREG_TO_REG, {DstReg}, {}) - .addImm(0) .addUse(LdReg) .addImm(AArch64::sub_32); constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI); return RBI.constrainGenericRegister(DstReg, AArch64::GPR64allRegClass, MRI); } - return constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI); + constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI); + return true; } case TargetOpcode::G_INDEXED_ZEXTLOAD: @@ -3183,7 +3201,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { // Now that we selected an opcode, we need to constrain the register // operands to use appropriate classes. - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } case TargetOpcode::G_PTR_ADD: { @@ -3214,7 +3233,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { I.getOperand(2).ChangeToImmediate( AArch64_AM::encodeLogicalImmediate(Mask, 64)); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } case TargetOpcode::G_PTRTOINT: case TargetOpcode::G_TRUNC: { @@ -3332,7 +3352,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass); BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG)) .addDef(ExtSrc) - .addImm(0) .addUse(SrcReg) .addImm(AArch64::sub_32); I.getOperand(1).setReg(ExtSrc); @@ -3396,7 +3415,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { .addImm(0); MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {}) - .addImm(0) .addUse(SubregToRegSrc) .addImm(AArch64::sub_32); @@ -3428,7 +3446,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { } SrcReg = MIB.buildInstr(AArch64::SUBREG_TO_REG, {&AArch64::GPR64RegClass}, {}) - .addImm(0) .addUse(SrcReg) .addImm(AArch64::sub_32) .getReg(0); @@ -3567,7 +3584,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { I.getOperand(1).getBlockAddress(), /* Offset */ 0, AArch64II::MO_NC | AArch64II::MO_PAGEOFF); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI); + return true; } } case AArch64::G_DUP: { @@ -3590,7 +3608,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { I.setDesc(TII.get(AArch64::DUPv8i16gpr)); else return false; - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } case TargetOpcode::G_BUILD_VECTOR: return selectBuildVector(I, MRI); @@ -3725,7 +3744,8 @@ bool AArch64InstructionSelector::selectBrJT(MachineInstr &I, // Build the indirect branch. MIB.buildInstr(AArch64::BR, {}, {TargetReg}); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*JumpTableInst, TII, TRI, RBI); + constrainSelectedInstRegOperands(*JumpTableInst, TII, TRI, RBI); + return true; } bool AArch64InstructionSelector::selectJumpTable(MachineInstr &I, @@ -3741,7 +3761,8 @@ bool AArch64InstructionSelector::selectJumpTable(MachineInstr &I, .addJumpTableIndex(JTI, AArch64II::MO_PAGE) .addJumpTableIndex(JTI, AArch64II::MO_NC | AArch64II::MO_PAGEOFF); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI); + return true; } bool AArch64InstructionSelector::selectTLSGlobalValue( @@ -3886,17 +3907,15 @@ bool AArch64InstructionSelector::selectMergeValues( MachineInstr &SubRegMI = *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG)) .addDef(SubToRegDef) - .addImm(0) .addUse(I.getOperand(1).getReg()) .addImm(AArch64::sub_32); Register SubToRegDef2 = MRI.createVirtualRegister(DstRC); // Need to anyext the second scalar before we can use bfm MachineInstr &SubRegMI2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII.get(TargetOpcode::SUBREG_TO_REG)) - .addDef(SubToRegDef2) - .addImm(0) - .addUse(I.getOperand(2).getReg()) - .addImm(AArch64::sub_32); + TII.get(TargetOpcode::SUBREG_TO_REG)) + .addDef(SubToRegDef2) + .addUse(I.getOperand(2).getReg()) + .addImm(AArch64::sub_32); MachineInstr &BFM = *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri)) .addDef(I.getOperand(0).getReg()) @@ -5291,7 +5310,6 @@ bool AArch64InstructionSelector::selectUSMovFromExtend( Register NewReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); MIB.buildInstr(Opcode, {NewReg}, {Src0}).addImm(Lane); ExtI = MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {}) - .addImm(0) .addUse(NewReg) .addImm(AArch64::sub_32); RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); @@ -5560,7 +5578,6 @@ bool AArch64InstructionSelector::selectIndexedExtLoad( if (InsertIntoSubReg) { // Generate a SUBREG_TO_REG. auto SubToReg = MIB.buildInstr(TargetOpcode::SUBREG_TO_REG, {Dst}, {}) - .addImm(0) .addUse(LdMI.getReg(1)) .addImm(InsertIntoSubReg); RBI.constrainGenericRegister( @@ -5852,7 +5869,6 @@ bool AArch64InstructionSelector::tryOptBuildVecToSubregToReg( if (!getSubRegForClass(EltRC, TRI, SubReg)) return false; auto SubregToReg = MIB.buildInstr(AArch64::SUBREG_TO_REG, {Dst}, {}) - .addImm(0) .addUse(EltReg) .addImm(SubReg); I.eraseFromParent(); @@ -6613,6 +6629,42 @@ bool AArch64InstructionSelector::selectIntrinsicWithSideEffects( constrainSelectedInstRegOperands(*Memset, TII, TRI, RBI); break; } + case Intrinsic::ptrauth_resign_load_relative: { + Register DstReg = I.getOperand(0).getReg(); + Register ValReg = I.getOperand(2).getReg(); + uint64_t AUTKey = I.getOperand(3).getImm(); + Register AUTDisc = I.getOperand(4).getReg(); + uint64_t PACKey = I.getOperand(5).getImm(); + Register PACDisc = I.getOperand(6).getReg(); + int64_t Addend = I.getOperand(7).getImm(); + + Register AUTAddrDisc = AUTDisc; + uint16_t AUTConstDiscC = 0; + std::tie(AUTConstDiscC, AUTAddrDisc) = + extractPtrauthBlendDiscriminators(AUTDisc, MRI); + + Register PACAddrDisc = PACDisc; + uint16_t PACConstDiscC = 0; + std::tie(PACConstDiscC, PACAddrDisc) = + extractPtrauthBlendDiscriminators(PACDisc, MRI); + + MIB.buildCopy({AArch64::X16}, {ValReg}); + + MIB.buildInstr(AArch64::AUTRELLOADPAC) + .addImm(AUTKey) + .addImm(AUTConstDiscC) + .addUse(AUTAddrDisc) + .addImm(PACKey) + .addImm(PACConstDiscC) + .addUse(PACAddrDisc) + .addImm(Addend) + .constrainAllUses(TII, TRI, RBI); + MIB.buildCopy({DstReg}, Register(AArch64::X16)); + + RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI); + I.eraseFromParent(); + return true; + } } I.eraseFromParent(); @@ -7847,6 +7899,62 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const { return std::nullopt; } +InstructionSelector::ComplexRendererFns +AArch64InstructionSelector::selectCVTFixedPointVecBase( + const MachineOperand &Root) const { + if (!Root.isReg()) + return std::nullopt; + const MachineRegisterInfo &MRI = + Root.getParent()->getParent()->getParent()->getRegInfo(); + + MachineInstr *Dup = getDefIgnoringCopies(Root.getReg(), MRI); + if (Dup->getOpcode() != AArch64::G_DUP) + return std::nullopt; + std::optional CstVal = + getAnyConstantVRegValWithLookThrough(Dup->getOperand(1).getReg(), MRI); + if (!CstVal) + return std::nullopt; + + unsigned RegWidth = MRI.getType(Root.getReg()).getScalarSizeInBits(); + APFloat FVal(0.0); + switch (RegWidth) { + case 16: + FVal = APFloat(APFloat::IEEEhalf(), CstVal->Value); + break; + case 32: + FVal = APFloat(APFloat::IEEEsingle(), CstVal->Value); + break; + case 64: + FVal = APFloat(APFloat::IEEEdouble(), CstVal->Value); + break; + default: + return std::nullopt; + }; + if (unsigned FBits = CheckFixedPointOperandConstant(FVal, RegWidth, + /*isReciprocal*/ false)) + return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(FBits); }}}; + + return std::nullopt; +} + +InstructionSelector::ComplexRendererFns +AArch64InstructionSelector::selectCVTFixedPointVec(MachineOperand &Root) const { + return selectCVTFixedPointVecBase(Root); +} + +void AArch64InstructionSelector::renderFixedPointXForm(MachineInstrBuilder &MIB, + const MachineInstr &MI, + int OpIdx) const { + // FIXME: This is only needed to satisfy the type checking in tablegen, and + // should be able to reuse the Renderers already calculated by + // selectCVTFixedPointVecBase. + InstructionSelector::ComplexRendererFns Renderer = + selectCVTFixedPointVecBase(MI.getOperand(2)); + assert((Renderer && Renderer->size() == 1) && + "Expected selectCVTFixedPointVec to provide a function\n"); + (Renderer->front())(MIB); +} + void AArch64InstructionSelector::renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const { diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h index 35f729a5ef96c..1d3f089e2130b 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h @@ -769,7 +769,7 @@ static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) { if (Imm & 0x04) EncVal |= 0x0004000000000000ULL; if (Imm & 0x02) EncVal |= 0x0002000000000000ULL; if (Imm & 0x01) EncVal |= 0x0001000000000000ULL; - return (EncVal << 32) | EncVal; + return EncVal; } /// Returns true if Imm is the concatenation of a repeating pattern of type T. diff --git a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp index 39c2bff0ffca4..07abaf92d23d5 100644 --- a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp +++ b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp @@ -201,23 +201,6 @@ class EmitContext { Register AgnosticZABufferPtr = AArch64::NoRegister; }; -/// Checks if \p State is a legal edge bundle state. For a state to be a legal -/// bundle state, it must be possible to transition from it to any other bundle -/// state without losing any ZA state. This is the case for ACTIVE/LOCAL_SAVED, -/// as you can transition between those states by saving/restoring ZA. The OFF -/// state would not be legal, as transitioning to it drops the content of ZA. -static bool isLegalEdgeBundleZAState(ZAState State) { - switch (State) { - case ZAState::ACTIVE: // ZA state within the accumulator/ZT0. - case ZAState::ACTIVE_ZT0_SAVED: // ZT0 is saved (ZA is active). - case ZAState::LOCAL_SAVED: // ZA state may be saved on the stack. - case ZAState::LOCAL_COMMITTED: // ZA state is saved on the stack. - return true; - default: - return false; - } -} - StringRef getZAStateString(ZAState State) { #define MAKE_CASE(V) \ case V: \ @@ -315,8 +298,8 @@ struct MachineSMEABI : public MachineFunctionPass { /// within the machine function. FunctionInfo collectNeededZAStates(SMEAttrs SMEFnAttrs); - /// Assigns each edge bundle a ZA state based on the needed states of blocks - /// that have incoming or outgoing edges in that bundle. + /// Assigns each edge bundle a ZA state based on the desired states of + /// incoming and outgoing blocks in the bundle. SmallVector assignBundleZAStates(const EdgeBundles &Bundles, const FunctionInfo &FnInfo); @@ -326,11 +309,6 @@ struct MachineSMEABI : public MachineFunctionPass { const EdgeBundles &Bundles, ArrayRef BundleStates); - /// Propagates desired states forwards (from predecessors -> successors) if - /// \p Forwards, otherwise, propagates backwards (from successors -> - /// predecessors). - void propagateDesiredStates(FunctionInfo &FnInfo, bool Forwards = true); - void addSMELibCall(MachineInstrBuilder &MIB, RTLIB::Libcall LC, CallingConv::ID ExpectedCC); @@ -536,110 +514,36 @@ FunctionInfo MachineSMEABI::collectNeededZAStates(SMEAttrs SMEFnAttrs) { PhysLiveRegsAfterSMEPrologue}; } -void MachineSMEABI::propagateDesiredStates(FunctionInfo &FnInfo, - bool Forwards) { - // If `Forwards`, this propagates desired states from predecessors to - // successors, otherwise, this propagates states from successors to - // predecessors. - auto GetBlockState = [](BlockInfo &Block, bool Incoming) -> ZAState & { - return Incoming ? Block.DesiredIncomingState : Block.DesiredOutgoingState; - }; - - SmallVector Worklist; - for (auto [BlockID, BlockInfo] : enumerate(FnInfo.Blocks)) { - if (!isLegalEdgeBundleZAState(GetBlockState(BlockInfo, Forwards))) - Worklist.push_back(MF->getBlockNumbered(BlockID)); - } - - while (!Worklist.empty()) { - MachineBasicBlock *MBB = Worklist.pop_back_val(); - BlockInfo &Block = FnInfo.Blocks[MBB->getNumber()]; - - // Pick a legal edge bundle state that matches the majority of - // predecessors/successors. - int StateCounts[ZAState::NUM_ZA_STATE] = {0}; - for (MachineBasicBlock *PredOrSucc : - Forwards ? predecessors(MBB) : successors(MBB)) { - BlockInfo &PredOrSuccBlock = FnInfo.Blocks[PredOrSucc->getNumber()]; - ZAState ZAState = GetBlockState(PredOrSuccBlock, !Forwards); - if (isLegalEdgeBundleZAState(ZAState)) - StateCounts[ZAState]++; - } - - ZAState PropagatedState = ZAState(max_element(StateCounts) - StateCounts); - ZAState &CurrentState = GetBlockState(Block, Forwards); - if (PropagatedState != CurrentState) { - CurrentState = PropagatedState; - ZAState &OtherState = GetBlockState(Block, !Forwards); - // Propagate to the incoming/outgoing state if that is also "ANY". - if (OtherState == ZAState::ANY) - OtherState = PropagatedState; - // Push any successors/predecessors that may need updating to the - // worklist. - for (MachineBasicBlock *SuccOrPred : - Forwards ? successors(MBB) : predecessors(MBB)) { - BlockInfo &SuccOrPredBlock = FnInfo.Blocks[SuccOrPred->getNumber()]; - if (!isLegalEdgeBundleZAState(GetBlockState(SuccOrPredBlock, Forwards))) - Worklist.push_back(SuccOrPred); - } - } - } -} - -/// Assigns each edge bundle a ZA state based on the needed states of blocks -/// that have incoming or outgoing edges in that bundle. +/// Assigns each edge bundle a ZA state based on the desired states of incoming +/// and outgoing blocks in the bundle. SmallVector MachineSMEABI::assignBundleZAStates(const EdgeBundles &Bundles, const FunctionInfo &FnInfo) { SmallVector BundleStates(Bundles.getNumBundles()); for (unsigned I = 0, E = Bundles.getNumBundles(); I != E; ++I) { - LLVM_DEBUG(dbgs() << "Assigning ZA state for edge bundle: " << I << '\n'); - - // Attempt to assign a ZA state for this bundle that minimizes state - // transitions. Edges within loops are given a higher weight as we assume - // they will be executed more than once. - int EdgeStateCounts[ZAState::NUM_ZA_STATE] = {0}; + std::optional BundleState; for (unsigned BlockID : Bundles.getBlocks(I)) { - LLVM_DEBUG(dbgs() << "- bb." << BlockID); - const BlockInfo &Block = FnInfo.Blocks[BlockID]; - bool InEdge = Bundles.getBundle(BlockID, /*Out=*/false) == I; - bool OutEdge = Bundles.getBundle(BlockID, /*Out=*/true) == I; - - bool LegalInEdge = - InEdge && isLegalEdgeBundleZAState(Block.DesiredIncomingState); - bool LegalOutEgde = - OutEdge && isLegalEdgeBundleZAState(Block.DesiredOutgoingState); - if (LegalInEdge) { - LLVM_DEBUG(dbgs() << " DesiredIncomingState: " - << getZAStateString(Block.DesiredIncomingState)); - EdgeStateCounts[Block.DesiredIncomingState]++; - } - if (LegalOutEgde) { - LLVM_DEBUG(dbgs() << " DesiredOutgoingState: " - << getZAStateString(Block.DesiredOutgoingState)); - EdgeStateCounts[Block.DesiredOutgoingState]++; - } - if (!LegalInEdge && !LegalOutEgde) - LLVM_DEBUG(dbgs() << " (no state preference)"); - LLVM_DEBUG(dbgs() << '\n'); + // Check if the block is an incoming block in the bundle. Note: We skip + // Block.FixedEntryState != ANY to ignore EH pads (which are only + // reachable via exceptions). + if (Block.FixedEntryState != ZAState::ANY || + Bundles.getBundle(BlockID, /*Out=*/false) != I) + continue; + + // Pick a state that matches all incoming blocks. Fall back to "ACTIVE" if + // any incoming state doesn't match. This will hoist the state from + // incoming blocks to outgoing blocks. + if (!BundleState) + BundleState = Block.DesiredIncomingState; + else if (BundleState != Block.DesiredIncomingState) + BundleState = ZAState::ACTIVE; } - ZAState BundleState = - ZAState(max_element(EdgeStateCounts) - EdgeStateCounts); - - if (BundleState == ZAState::ANY) + if (!BundleState || BundleState == ZAState::ANY) BundleState = ZAState::ACTIVE; - LLVM_DEBUG({ - dbgs() << "Chosen ZA state: " << getZAStateString(BundleState) << '\n' - << "Edge counts:"; - for (auto [State, Count] : enumerate(EdgeStateCounts)) - dbgs() << " " << getZAStateString(ZAState(State)) << ": " << Count; - dbgs() << "\n\n"; - }); - - BundleStates[I] = BundleState; + BundleStates[I] = *BundleState; } return BundleStates; @@ -1232,6 +1136,7 @@ void MachineSMEABI::emitStateChange(EmitContext &Context, case transitionFrom(ZAState::LOCAL_COMMITTED).to(ZAState::ACTIVE): case transitionFrom(ZAState::LOCAL_COMMITTED).to(ZAState::ACTIVE_ZT0_SAVED): case transitionFrom(ZAState::LOCAL_SAVED).to(ZAState::ACTIVE): + case transitionFrom(ZAState::LOCAL_SAVED).to(ZAState::ACTIVE_ZT0_SAVED): if (HasZAState) emitZARestore(Context, MBB, InsertPt, PhysLiveRegs); else @@ -1288,42 +1193,6 @@ bool MachineSMEABI::runOnMachineFunction(MachineFunction &MF) { FunctionInfo FnInfo = collectNeededZAStates(SMEFnAttrs); - if (OptLevel != CodeGenOptLevel::None) { - // Propagate desired states forward, then backwards. Most of the propagation - // should be done in the forward step, and backwards propagation is then - // used to fill in the gaps. Note: Doing both in one step can give poor - // results. For example, consider this subgraph: - // - // ┌─────┐ - // ┌─┤ BB0 ◄───┐ - // │ └─┬───┘ │ - // │ ┌─▼───◄──┐│ - // │ │ BB1 │ ││ - // │ └─┬┬──┘ ││ - // │ │└─────┘│ - // │ ┌─▼───┐ │ - // │ │ BB2 ├───┘ - // │ └─┬───┘ - // │ ┌─▼───┐ - // └─► BB3 │ - // └─────┘ - // - // If: - // - "BB0" and "BB2" (outer loop) has no state preference - // - "BB1" (inner loop) desires the ACTIVE state on entry/exit - // - "BB3" desires the LOCAL_SAVED state on entry - // - // If we propagate forwards first, ACTIVE is propagated from BB1 to BB2, - // then from BB2 to BB0. Which results in the inner and outer loops having - // the "ACTIVE" state. This avoids any state changes in the loops. - // - // If we propagate backwards first, we _could_ propagate LOCAL_SAVED from - // BB3 to BB0, which would result in a transition from ACTIVE -> LOCAL_SAVED - // in the outer loop. - for (bool Forwards : {true, false}) - propagateDesiredStates(FnInfo, Forwards); - } - SmallVector BundleStates = assignBundleZAStates(Bundles, FnInfo); EmitContext Context; diff --git a/llvm/lib/Target/AArch64/SMEABIPass.cpp b/llvm/lib/Target/AArch64/SMEABIPass.cpp index 6bdad036c1f71..4245afbbf6beb 100644 --- a/llvm/lib/Target/AArch64/SMEABIPass.cpp +++ b/llvm/lib/Target/AArch64/SMEABIPass.cpp @@ -119,7 +119,7 @@ bool SMEABI::updateNewStateFunctions(Module *M, Function *F, // to commit the lazy save. if (FnAttrs.hasPrivateZAInterface()) { // Create the new blocks for reading TPIDR2_EL0 & enabling ZA state. - auto *SaveBB = OrigBB->splitBasicBlock(OrigBB->begin(), "save.za", true); + auto *SaveBB = OrigBB->splitBasicBlockBefore(OrigBB->begin(), "save.za"); auto *PreludeBB = BasicBlock::Create(Context, "prelude", F, SaveBB); // Read TPIDR2_EL0 in PreludeBB & branch to SaveBB if not 0. diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 35b0872dc593c..9d988b5654a6e 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1496,35 +1496,35 @@ multiclass sve_int_perm_dup_i { def : Pat<(nxv16i8 (splat_vector (i32 (vector_extract (nxv16i8 ZPR:$vec), sve_elm_idx_extdup_b:$index)))), (!cast(NAME # _B) ZPR:$vec, sve_elm_idx_extdup_b:$index)>; def : Pat<(nxv16i8 (splat_vector (i32 (vector_extract (v16i8 V128:$vec), sve_elm_idx_extdup_b:$index)))), - (!cast(NAME # _B) (SUBREG_TO_REG (i64 0), $vec, zsub), sve_elm_idx_extdup_b:$index)>; + (!cast(NAME # _B) (SUBREG_TO_REG $vec, zsub), sve_elm_idx_extdup_b:$index)>; def : Pat<(nxv16i8 (splat_vector (i32 (vector_extract (v8i8 V64:$vec), sve_elm_idx_extdup_b:$index)))), - (!cast(NAME # _B) (SUBREG_TO_REG (i64 0), $vec, dsub), sve_elm_idx_extdup_b:$index)>; + (!cast(NAME # _B) (SUBREG_TO_REG $vec, dsub), sve_elm_idx_extdup_b:$index)>; foreach VT = [nxv8i16, nxv2f16, nxv4f16, nxv8f16, nxv2bf16, nxv4bf16, nxv8bf16] in { def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.Packed ZPR:$vec), sve_elm_idx_extdup_h:$index)))), (!cast(NAME # _H) ZPR:$vec, sve_elm_idx_extdup_h:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.ZSub V128:$vec), sve_elm_idx_extdup_h:$index)))), - (!cast(NAME # _H) (SUBREG_TO_REG (i64 0), $vec, zsub), sve_elm_idx_extdup_h:$index)>; + (!cast(NAME # _H) (SUBREG_TO_REG $vec, zsub), sve_elm_idx_extdup_h:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.DSub V64:$vec), sve_elm_idx_extdup_h:$index)))), - (!cast(NAME # _H) (SUBREG_TO_REG (i64 0), $vec, dsub), sve_elm_idx_extdup_h:$index)>; + (!cast(NAME # _H) (SUBREG_TO_REG $vec, dsub), sve_elm_idx_extdup_h:$index)>; } foreach VT = [nxv4i32, nxv2f32, nxv4f32 ] in { def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.Packed ZPR:$vec), sve_elm_idx_extdup_s:$index)))), (!cast(NAME # _S) ZPR:$vec, sve_elm_idx_extdup_s:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.ZSub V128:$vec), sve_elm_idx_extdup_s:$index)))), - (!cast(NAME # _S) (SUBREG_TO_REG (i64 0), $vec, zsub), sve_elm_idx_extdup_s:$index)>; + (!cast(NAME # _S) (SUBREG_TO_REG $vec, zsub), sve_elm_idx_extdup_s:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.DSub V64:$vec), sve_elm_idx_extdup_s:$index)))), - (!cast(NAME # _S) (SUBREG_TO_REG (i64 0), $vec, dsub), sve_elm_idx_extdup_s:$index)>; + (!cast(NAME # _S) (SUBREG_TO_REG $vec, dsub), sve_elm_idx_extdup_s:$index)>; } foreach VT = [nxv2i64, nxv2f64] in { def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (VT ZPR:$vec), sve_elm_idx_extdup_d:$index)))), (!cast(NAME # _D) ZPR:$vec, sve_elm_idx_extdup_d:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.ZSub V128:$vec), sve_elm_idx_extdup_d:$index)))), - (!cast(NAME # _D) (SUBREG_TO_REG (i64 0), $vec, zsub), sve_elm_idx_extdup_d:$index)>; + (!cast(NAME # _D) (SUBREG_TO_REG $vec, zsub), sve_elm_idx_extdup_d:$index)>; def : Pat<(VT (splat_vector (SVEType.EltAsScalar (vector_extract (SVEType.DSub V64:$vec), sve_elm_idx_extdup_d:$index)))), - (!cast(NAME # _D) (SUBREG_TO_REG (i64 0), $vec, dsub), sve_elm_idx_extdup_d:$index)>; + (!cast(NAME # _D) (SUBREG_TO_REG $vec, dsub), sve_elm_idx_extdup_d:$index)>; } // When extracting from an unpacked vector the index must be scaled to account @@ -6329,7 +6329,7 @@ multiclass sve_int_index_ir(NAME # "_D") (i64 0), (!cast("MOVi64imm") $imm))>; def : Pat<(nxv2i64 (step_vector i64imm_32bit_tgt:$imm)), - (!cast(NAME # "_D") (i64 0), (SUBREG_TO_REG (i64 0), (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; + (!cast(NAME # "_D") (i64 0), (SUBREG_TO_REG (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; // add(step_vector(step), dup(X)) -> index(X, step). def : Pat<(add (nxv16i8 (step_vector_oneuse i8:$imm)), (nxv16i8 (splat_vector(simm5_8b:$imm5)))), @@ -6341,7 +6341,7 @@ multiclass sve_int_index_ir(NAME # "_D") simm5_64b:$imm5, (!cast("MOVi64imm") $imm))>; def : Pat<(add (nxv2i64 (step_vector_oneuse i64imm_32bit_tgt:$imm)), (nxv2i64 (splat_vector(simm5_64b:$imm5)))), - (!cast(NAME # "_D") simm5_64b:$imm5, (SUBREG_TO_REG (i64 0), (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; + (!cast(NAME # "_D") simm5_64b:$imm5, (SUBREG_TO_REG (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; // mul(step_vector(1), dup(Y)) -> index(0, Y). def : Pat<(mulop (nxv16i1 (SVEAllActive)), (nxv16i8 (step_vector_oneuse (i8 1))), (nxv16i8 (splat_vector(i32 GPR32:$Rm)))), @@ -6435,7 +6435,7 @@ multiclass sve_int_index_rr { def : Pat<(add (nxv2i64 (step_vector_oneuse i64:$imm)), (nxv2i64 (splat_vector(i64 GPR64:$Rn)))), (!cast(NAME # "_D") GPR64:$Rn, (!cast("MOVi64imm") $imm))>; def : Pat<(add (nxv2i64 (step_vector_oneuse i64imm_32bit_tgt:$imm)), (nxv2i64 (splat_vector(i64 GPR64:$Rn)))), - (!cast(NAME # "_D") GPR64:$Rn, (SUBREG_TO_REG (i64 0), (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; + (!cast(NAME # "_D") GPR64:$Rn, (SUBREG_TO_REG (!cast("MOVi32imm") (!cast("trunc_imm") $imm)), sub_32))>; // add(mul(step_vector(1), dup(Y)), dup(X)) -> index(X, Y). def : Pat<(add (mulop (nxv16i1 (SVEAllActive)), (nxv16i8 (step_vector_oneuse (i8 1))), (nxv16i8 (splat_vector(i32 GPR32:$Rm)))), (nxv16i8 (splat_vector(i32 GPR32:$Rn)))), diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h index 0c98fdc75cacd..97777dec45863 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -19,6 +19,8 @@ // FIXME: Is it easiest to fix this layering violation by moving the .inc // #includes from AArch64MCTargetDesc.h to here? #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends. +#include "llvm/ADT/APFloat.h" +#include "llvm/ADT/APSInt.h" #include "llvm/ADT/BitmaskEnum.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -247,6 +249,38 @@ static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) { return false; } +inline unsigned CheckFixedPointOperandConstant(APFloat &FVal, unsigned RegWidth, + bool isReciprocal) { + // An FCVT[SU] instruction performs: convertToInt(Val * 2^fbits) where fbits + // is between 1 and 32 for a destination w-register, or 1 and 64 for an + // x-register. + // + // By this stage, we've detected (fp_to_[su]int (fmul Val, THIS_NODE)) so we + // want THIS_NODE to be 2^fbits. This is much easier to deal with using + // integers. + bool IsExact; + + if (isReciprocal) + if (!FVal.getExactInverse(&FVal)) + return 0; + + // fbits is between 1 and 64 in the worst-case, which means the fmul + // could have 2^64 as an actual operand. Need 65 bits of precision. + APSInt IntVal(65, true); + FVal.convertToInteger(IntVal, APFloat::rmTowardZero, &IsExact); + + // N.b. isPowerOf2 also checks for > 0. + if (!IsExact || !IntVal.isPowerOf2()) + return 0; + unsigned FBits = IntVal.logBase2(); + + // Checks above should have guaranteed that we haven't lost information in + // finding FBits, but it must still be in range. + if (FBits == 0 || FBits > RegWidth) + return 0; + return FBits; +} + namespace AArch64CC { // The CondCodes constants map directly to the 4-bit encoding of the condition diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 1a9bdb6634629..9d723c86031f2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -457,6 +457,14 @@ defm McastLoadInsts : AMDGPUSubtargetFeature<"mcast-load-insts", "Has multicast load instructions" >; +defm SWakeupImm : AMDGPUSubtargetFeature<"s-wakeup-imm", + "s_wakeup takes an immediate operand" +>; + +defm SBarrierLeaveImm : AMDGPUSubtargetFeature<"s-barrier-leave-imm", + "s_barrier_leave takes an immediate operand" +>; + defm GFX950Insts : AMDGPUSubtargetFeature<"gfx950-insts", "Additional instructions for GFX950+", /*GenPredicate=*/1, @@ -498,7 +506,11 @@ defm GFX1250Insts : AMDGPUSubtargetFeature<"gfx1250-insts", defm GFX13Insts : AMDGPUSubtargetFeature<"gfx13-insts", "Additional instructions for GFX13+", - /*GenPredicate=*/0 + /*GenPredicate=*/0, + /*GenAssemblerPredicate=*/0, + [FeatureSWakeupImm, + FeatureSBarrierLeaveImm, + ] >; defm GFX10_3Insts : AMDGPUSubtargetFeature<"gfx10-3-insts", @@ -1451,7 +1463,7 @@ def FeatureGFX13 : GCNSubtargetFeatureGeneration<"GFX13", FeatureVOP3Literal, FeatureDPP8, FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureA16, FeatureFastDenormalF32, FeatureG16, - FeatureUnalignedBufferAccess, FeatureUnalignedScratchAccess, + FeatureUnalignedBufferAccess, FeatureUnalignedScratchAccess, FeatureImageInsts, FeatureUnalignedDSAccess, FeatureTrue16BitInsts, FeatureDefaultComponentBroadcast, FeatureMaxHardClauseLength32, FeatureAtomicFMinFMaxF32GlobalInsts, FeatureAtomicFMinFMaxF32FlatInsts, @@ -1869,6 +1881,12 @@ def FeatureISAVersion11_5_3 : FeatureSet< !listconcat(FeatureISAVersion11_5_Common.Features, [])>; +def FeatureISAVersion11_7_0 : FeatureSet< + !listconcat(FeatureISAVersion11_Common.Features, + [FeatureSALUFloatInsts, + FeatureDPPSrc1SGPR, + FeatureFP8ConversionInsts])>; + def FeatureISAVersion12 : FeatureSet< [FeatureGFX12, FeatureBackOffBarrier, @@ -1993,25 +2011,32 @@ def FeatureISAVersion12_50_Common : FeatureSet< FeatureXNACK, FeatureClusters, FeatureD16Writes32BitVgpr, - FeatureCubeInsts, - FeatureLerpInst, - FeatureSadInsts, - FeatureQsadInsts, - FeatureCvtNormInsts, - FeatureCvtPkNormVOP2Insts, - FeatureCvtPkNormVOP3Insts, FeatureMcastLoadInsts ]>; def FeatureISAVersion12_50 : FeatureSet< !listconcat(FeatureISAVersion12_50_Common.Features, [FeatureAddressableLocalMemorySize327680, - FeatureSetregVGPRMSBFixup])>; + FeatureSetregVGPRMSBFixup, + FeatureCubeInsts, + FeatureLerpInst, + FeatureSadInsts, + FeatureQsadInsts, + FeatureCvtNormInsts, + FeatureCvtPkNormVOP2Insts, + FeatureCvtPkNormVOP3Insts])>; def FeatureISAVersion12_51 : FeatureSet< !listconcat(FeatureISAVersion12_50_Common.Features, [FeatureAddressableLocalMemorySize327680, - FeatureDPALU_DPP])>; + FeatureDPALU_DPP, + FeatureCubeInsts, + FeatureLerpInst, + FeatureSadInsts, + FeatureQsadInsts, + FeatureCvtNormInsts, + FeatureCvtPkNormVOP2Insts, + FeatureCvtPkNormVOP3Insts])>; def FeatureISAVersion12_Generic: FeatureSet< !listconcat(FeatureISAVersion12.Features, @@ -2249,6 +2274,11 @@ def isGFX8GFX9GFX10GFX11 : "Subtarget->getGeneration() == AMDGPUSubtarget::GFX11">, AssemblerPredicate<(all_of FeatureGFX8Insts, (not FeatureGFX12Insts))>; +def isGFX8GFX9GFX10GFX11GFX12 : + Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&" + "Subtarget->getGeneration() < AMDGPUSubtarget::GFX13">, + AssemblerPredicate<(all_of FeatureGFX8Insts, (not FeatureGFX13Insts))>; + def isGFX7Plus : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">, AssemblerPredicate<(all_of FeatureCIInsts)>; @@ -2359,6 +2389,11 @@ def isGFX11Plus : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX11">, AssemblerPredicate<(all_of FeatureGFX11Insts)>; +def isGFX11PlusNot12_50 : + Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX11 &&" + "(Subtarget->getGeneration() >= AMDGPUSubtarget::GFX13 || !Subtarget->hasGFX1250Insts())">, + AssemblerPredicate<(all_of FeatureGFX11Insts, (any_of FeatureGFX13Insts, (not FeatureGFX1250Insts)))>; + def isGFX12Only : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX12">, AssemblerPredicate<(all_of FeatureGFX12Insts, (not FeatureGFX13Insts))>; @@ -2444,7 +2479,7 @@ def HasFormattedMUBUFInsts : Predicate<"Subtarget->hasFormattedMUBUFInsts()">, AssemblerPredicate<(all_of (not FeatureGFX1250Insts))>; def HasExportInsts : Predicate<"Subtarget->hasExportInsts()">, - AssemblerPredicate<(all_of (not FeatureGFX90AInsts), (not FeatureGFX1250Insts))>; + AssemblerPredicate<(any_of FeatureGFX13Insts, (all_of (not FeatureGFX90AInsts), (not FeatureGFX1250Insts)))>; def HasVINTERPEncoding : Predicate<"Subtarget->hasVINTERPEncoding()">, AssemblerPredicate<(all_of FeatureGFX11Insts, (not FeatureGFX1250Insts))>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h index f41739ac6c169..f38e49b947e3e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h @@ -19,8 +19,6 @@ namespace llvm { -void initializeAMDGPUArgumentUsageInfoWrapperLegacyPass(PassRegistry &); - class Function; class LLT; class raw_ostream; @@ -200,10 +198,7 @@ class AMDGPUArgumentUsageInfoWrapperLegacy : public ImmutablePass { public: static char ID; - AMDGPUArgumentUsageInfoWrapperLegacy() : ImmutablePass(ID) { - initializeAMDGPUArgumentUsageInfoWrapperLegacyPass( - *PassRegistry::getPassRegistry()); - } + AMDGPUArgumentUsageInfoWrapperLegacy() : ImmutablePass(ID) {} AMDGPUArgumentUsageInfo &getArgUsageInfo() { return *AUIP; } const AMDGPUArgumentUsageInfo &getArgUsageInfo() const { return *AUIP; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp index 80bc17f91aa3b..5c6affdae0c5b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -421,7 +421,7 @@ void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg, LLT PtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64); SmallVector SplitArgs; - SmallVector FieldOffsets; + SmallVector FieldOffsets; splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv(), &FieldOffsets); unsigned Idx = 0; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td index 55ce4f1738e37..cfef04644835c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -329,6 +329,12 @@ def : GINodeEquiv; // G_AMDGPU_WHOLE_WAVE_FUNC_RETURN is simpler than AMDGPUwhole_wave_return, // so we don't mark it as equivalent. +def : GINodeEquiv; + +def : GINodeEquiv; +def : GINodeEquiv; + + class GISelSop2Pat < SDPatternOperator node, Instruction inst, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp new file mode 100644 index 0000000000000..37f86781659c8 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.cpp @@ -0,0 +1,77 @@ +//===--- AMDGPUHazardLatency.cpp - AMDGPU Hazard Latency Adjustment -------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +/// \file This file contains a DAG scheduling mutation to adjust the +/// latency of data edges between instructions which use registers +/// potentially subject to additional hazard waits not accounted +/// for in the normal scheduling model. +/// While the scheduling model is typically still accurate in these +/// scenarios, adjusting latency of relevant edges can improve wait +/// merging and reduce pipeline impact of any required waits. +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUHazardLatency.h" +#include "GCNSubtarget.h" +#include "MCTargetDesc/AMDGPUMCTargetDesc.h" +#include "SIInstrInfo.h" +#include "llvm/CodeGen/ScheduleDAGInstrs.h" + +using namespace llvm; + +namespace { + +class HazardLatency : public ScheduleDAGMutation { +private: + const GCNSubtarget &ST; + const SIRegisterInfo &TRI; + const MachineRegisterInfo &MRI; + +public: + HazardLatency(MachineFunction *MF) + : ST(MF->getSubtarget()), TRI(*ST.getRegisterInfo()), + MRI(MF->getRegInfo()) {} + void apply(ScheduleDAGInstrs *DAG) override; +}; + +void HazardLatency::apply(ScheduleDAGInstrs *DAG) { + constexpr unsigned MaskLatencyBoost = 3; + + // Hazard only manifests in Wave64 + if (!ST.hasVALUMaskWriteHazard() || !ST.isWave64()) + return; + + for (SUnit &SU : DAG->SUnits) { + const MachineInstr *MI = SU.getInstr(); + if (!SIInstrInfo::isVALU(*MI)) + continue; + if (MI->getOpcode() == AMDGPU::V_READLANE_B32 || + MI->getOpcode() == AMDGPU::V_READFIRSTLANE_B32) + continue; + for (SDep &SuccDep : SU.Succs) { + if (SuccDep.isCtrl()) + continue; + // Boost latency on VALU writes to SGPRs used by VALUs. + // Reduce risk of premature VALU pipeline stall on associated reads. + MachineInstr *DestMI = SuccDep.getSUnit()->getInstr(); + if (!SIInstrInfo::isVALU(*DestMI)) + continue; + Register Reg = SuccDep.getReg(); + if (!TRI.isSGPRReg(MRI, Reg)) + continue; + SuccDep.setLatency(SuccDep.getLatency() * MaskLatencyBoost); + } + } +} + +} // end namespace + +std::unique_ptr +llvm::createAMDGPUHazardLatencyDAGMutation(MachineFunction *MF) { + return std::make_unique(MF); +} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.h b/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.h new file mode 100644 index 0000000000000..134cc27743cd1 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/AMDGPUHazardLatency.h @@ -0,0 +1,24 @@ +//===- AMDGPUHazardLatency.h - Hazard Latency Adjustment --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUHAZARDLATENCY_H +#define LLVM_LIB_TARGET_AMDGPU_AMDGPUHAZARDLATENCY_H + +#include "llvm/CodeGen/ScheduleDAGMutation.h" +#include + +namespace llvm { + +class MachineFunction; + +std::unique_ptr +createAMDGPUHazardLatencyDAGMutation(MachineFunction *MF); + +} // namespace llvm + +#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUHAZARDLATENCY_H diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 1446c84ef733b..238f06fbd33c0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -4284,7 +4284,7 @@ static std::pair BitOp3_Op(SDValue In, SmallVector Backup(Src.begin(), Src.end()); if (!getOperandBits(LHS, LHSBits) || !getOperandBits(RHS, RHSBits)) { - Src = Backup; + Src = std::move(Backup); return std::make_pair(0, 0); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 466cc6a5156d4..da21033388532 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2776,7 +2776,6 @@ SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op, const bool IsLog10 = Op.getOpcode() == ISD::FLOG10; assert(IsLog10 || Op.getOpcode() == ISD::FLOG); - const auto &Options = getTargetMachine().Options; if (VT == MVT::f16 || Flags.hasApproximateFuncs()) { if (VT == MVT::f16 && !isTypeLegal(MVT::f16)) { @@ -2845,8 +2844,7 @@ SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op, R = getMad(DAG, DL, VT, YH, CH, Mad1); } - const bool IsFiniteOnly = - (Flags.hasNoNaNs() || Options.NoNaNsFPMath) && Flags.hasNoInfs(); + const bool IsFiniteOnly = Flags.hasNoNaNs() && Flags.hasNoInfs(); // TODO: Check if known finite from source value. if (!IsFiniteOnly) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp index 2cd1902785546..376184e81c738 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp @@ -553,6 +553,89 @@ static CallInst *rewriteCall(IRBuilderBase &B, CallInst &Old, return NewCall; } +// Return true for sequences of instructions that effectively assign +// each lane to its thread ID +static bool isThreadID(const GCNSubtarget &ST, Value *V) { + // Case 1: + // wave32: mbcnt_lo(-1, 0) + // wave64: mbcnt_hi(-1, mbcnt_lo(-1, 0)) + auto W32Pred = m_Intrinsic(m_ConstantInt<-1>(), + m_ConstantInt<0>()); + auto W64Pred = m_Intrinsic( + m_ConstantInt<-1>(), m_Intrinsic( + m_ConstantInt<-1>(), m_ConstantInt<0>())); + if (ST.isWave32() && match(V, W32Pred)) + return true; + if (ST.isWave64() && match(V, W64Pred)) + return true; + + return false; +} + +// Attempt to capture situations where the index argument matches +// a DPP pattern, and convert to a DPP-based mov +static std::optional +tryWaveShuffleDPP(const GCNSubtarget &ST, InstCombiner &IC, IntrinsicInst &II) { + Value *Val = II.getArgOperand(0); + Value *Idx = II.getArgOperand(1); + auto &B = IC.Builder; + + // DPP16 Row Share requires known wave size, architecture support + if (!ST.isWaveSizeKnown() || !ST.hasDPPRowShare()) + return std::nullopt; + + Value *Tid; + uint64_t Mask; + uint64_t RowIdx; + bool CanDPP16RowShare = false; + + // wave32 requires Mask & 0x1F == 0x10 + // wave64 requires Mask & 0x3F == 0x30 + uint64_t MaskCheck = (1UL << ST.getWavefrontSizeLog2()) - 1; + uint64_t MaskTarget = MaskCheck & 0xF0; + + // DPP16 Row Share 0: Idx = Tid & Mask + auto RowShare0Pred = m_And(m_Value(Tid), m_ConstantInt(Mask)); + + // DPP16 Row Share (0 < Row < 15): Idx = (Tid & Mask) | RowIdx + auto RowSharePred = + m_Or(m_And(m_Value(Tid), m_ConstantInt(Mask)), m_ConstantInt(RowIdx)); + + // DPP16 Row Share 15: Idx = Tid | 0xF + auto RowShare15Pred = m_Or(m_Value(Tid), m_ConstantInt<0xF>()); + + if (match(Idx, RowShare0Pred) && isThreadID(ST, Tid)) { + if ((Mask & MaskCheck) != MaskTarget) + return std::nullopt; + + RowIdx = 0; + CanDPP16RowShare = true; + } else if (match(Idx, RowSharePred) && isThreadID(ST, Tid) && RowIdx < 15 && + RowIdx > 0) { + if ((Mask & MaskCheck) != MaskTarget) + return std::nullopt; + + CanDPP16RowShare = true; + } else if (match(Idx, RowShare15Pred) && isThreadID(ST, Tid)) { + RowIdx = 15; + CanDPP16RowShare = true; + } + + if (CanDPP16RowShare) { + CallInst *UpdateDPP = + B.CreateIntrinsic(Intrinsic::amdgcn_update_dpp, Val->getType(), + {PoisonValue::get(Val->getType()), Val, + B.getInt32(AMDGPU::DPP::ROW_SHARE0 | RowIdx), + B.getInt32(0xF), B.getInt32(0xF), B.getFalse()}); + UpdateDPP->takeName(&II); + UpdateDPP->copyMetadata(II); + return IC.replaceInstUsesWith(II, UpdateDPP); + } + + // No valid DPP detected + return std::nullopt; +} + Instruction * GCNTTIImpl::hoistLaneIntrinsicThroughOperand(InstCombiner &IC, IntrinsicInst &II) const { @@ -1459,30 +1542,30 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { if (isa(Src) || isa(Segment)) return IC.replaceInstUsesWith(II, PoisonValue::get(II.getType())); - if (isa(Src)) { - auto *QNaN = ConstantFP::get( - II.getType(), APFloat::getQNaN(II.getType()->getFltSemantics())); - return IC.replaceInstUsesWith(II, QNaN); - } + if (isa(Segment)) + return IC.replaceInstUsesWith(II, ConstantFP::getZero(II.getType())); - const ConstantFP *Csrc = dyn_cast(Src); - if (!Csrc) + if (II.isStrictFP()) break; - if (II.isStrictFP()) + const ConstantFP *CSrc = dyn_cast(Src); + if (!CSrc && !isa(Src)) break; - const APFloat &Fsrc = Csrc->getValueAPF(); - if (Fsrc.isNaN()) { - auto *Quieted = ConstantFP::get(II.getType(), Fsrc.makeQuiet()); - return IC.replaceInstUsesWith(II, Quieted); - } + // The instruction ignores special cases, and literally just extracts the + // exponents. Fold undef to nan, and index the table as normal. + APInt FSrcInt = CSrc ? CSrc->getValueAPF().bitcastToAPInt() + : APFloat::getQNaN(II.getType()->getFltSemantics()) + .bitcastToAPInt(); const ConstantInt *Cseg = dyn_cast(Segment); - if (!Cseg) + if (!Cseg) { + if (isa(Src)) + return IC.replaceInstUsesWith(II, ConstantFP::getZero(II.getType())); break; + } - unsigned Exponent = Fsrc.bitcastToAPInt().extractBitsAsZExtValue(11, 52); + unsigned Exponent = FSrcInt.extractBitsAsZExtValue(11, 52); unsigned SegmentVal = Cseg->getValue().trunc(5).getZExtValue(); unsigned Shift = SegmentVal * 53; if (Exponent > 1077) @@ -1759,6 +1842,12 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { NewII->copyMetadata(II); return IC.eraseInstFromFunction(II); } + case Intrinsic::amdgcn_wave_shuffle: { + if (!ST->hasDPP()) + return std::nullopt; + + return tryWaveShuffleDPP(*ST, IC, II); + } } if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr = AMDGPU::getImageDimIntrinsicInfo(II.getIntrinsicID())) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td index 8a43c2da38346..8dc5d45aa73ba 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -402,6 +402,15 @@ def AMDGPUExportOp : SDTypeProfile<0, 8, [ ]>; +def AMDGPUflat_load_monitor : SDNode< + "AMDGPUISD::FLAT_LOAD_MONITOR", SDTLoad, + [SDNPHasChain, SDNPMemOperand] +>; + +def AMDGPUglobal_load_monitor : SDNode< + "AMDGPUISD::GLOBAL_LOAD_MONITOR", SDTLoad, + [SDNPHasChain, SDNPMemOperand] +>; //===----------------------------------------------------------------------===// // Flow Control Profile Types diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index e239e6f56cb44..b96c2ef70dd83 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -242,8 +242,7 @@ bool AMDGPUInstructionSelector::selectCOPY_SCC_VCC(MachineInstr &I) const { .addReg(VCCReg); } - if (!constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI); Register DstReg = I.getOperand(0).getReg(); BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(AMDGPU::SCC); @@ -284,7 +283,8 @@ bool AMDGPUInstructionSelector::selectCOPY_VCC_SCC(MachineInstr &I) const { .addImm(0); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectReadAnyLane(MachineInstr &I) const { @@ -298,7 +298,8 @@ bool AMDGPUInstructionSelector::selectReadAnyLane(MachineInstr &I) const { .addReg(SrcReg); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*RFL, TII, TRI, RBI); + constrainSelectedInstRegOperands(*RFL, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const { @@ -415,10 +416,11 @@ bool AMDGPUInstructionSelector::selectG_AND_OR_XOR(MachineInstr &I) const { // Dead implicit-def of scc I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef - true, // isImp - false, // isKill - true)); // isDead - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + true, // isImp + false, // isKill + true)); // isDead + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const { @@ -444,7 +446,8 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const { .add(I.getOperand(2)) .setOperandDead(3); // Dead scc I.eraseFromParent(); - return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); + return true; } if (STI.hasAddNoCarryInsts()) { @@ -452,7 +455,8 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const { I.setDesc(TII.get(Opc)); I.addOperand(*MF, MachineOperand::CreateImm(0)); I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } const unsigned Opc = Sub ? AMDGPU::V_SUB_CO_U32_e64 : AMDGPU::V_ADD_CO_U32_e64; @@ -465,7 +469,8 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const { .add(I.getOperand(2)) .addImm(0); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); + return true; } assert(!Sub && "illegal sub should not reach here"); @@ -506,8 +511,7 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const { .addReg(CarryReg, RegState::Kill) .addImm(0); - if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI); } BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg) @@ -543,7 +547,8 @@ bool AMDGPUInstructionSelector::selectG_UADDO_USUBO_UADDE_USUBE( I.setDesc(TII.get(HasCarryIn ? CarryOpc : NoCarryOpc)); I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); I.addOperand(*MF, MachineOperand::CreateImm(0)); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } Register Src0Reg = I.getOperand(2).getReg(); @@ -609,7 +614,8 @@ bool AMDGPUInstructionSelector::selectG_AMDGPU_MAD_64_32( I.addOperand(*MF, MachineOperand::CreateImm(0)); I.addImplicitDefUseOperands(*MF); I.getOperand(0).setIsEarlyClobber(true); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } // TODO: We should probably legalize these to only using 32-bit results. @@ -825,15 +831,13 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const { auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) .addImm(0xFFFF) .addReg(Src0); - if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) .addReg(Src1) .addImm(16) .addReg(TmpReg); - if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); MI.eraseFromParent(); return true; @@ -879,7 +883,8 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const { .setOperandDead(3); // Dead scc MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } if (STI.hasSPackHL()) { Opc = AMDGPU::S_PACK_HL_B32_B16; @@ -888,7 +893,8 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const { } MI.setDesc(TII.get(Opc)); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const { @@ -986,7 +992,8 @@ bool AMDGPUInstructionSelector::selectG_SBFX_UBFX(MachineInstr &MI) const { .addReg(OffsetReg) .addReg(WidthReg); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectInterpP1F16(MachineInstr &MI) const { @@ -1088,7 +1095,8 @@ bool AMDGPUInstructionSelector::selectWritelane(MachineInstr &MI) const { MIB.addReg(VDstIn); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } // We need to handle this here because tablegen doesn't support matching @@ -1129,7 +1137,8 @@ bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const { .addImm(0); // $omod MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const { @@ -1486,8 +1495,8 @@ bool AMDGPUInstructionSelector::selectG_ICMP_or_FCMP(MachineInstr &I) const { .add(I.getOperand(3)); BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg) .addReg(AMDGPU::SCC); + constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); bool Ret = - constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) && RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI); I.eraseFromParent(); return Ret; @@ -1517,9 +1526,9 @@ bool AMDGPUInstructionSelector::selectG_ICMP_or_FCMP(MachineInstr &I) const { RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(), *TRI.getBoolRC(), *MRI); - bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); + constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); I.eraseFromParent(); - return Ret; + return true; } bool AMDGPUInstructionSelector::selectIntrinsicCmp(MachineInstr &I) const { @@ -1573,8 +1582,7 @@ bool AMDGPUInstructionSelector::selectIntrinsicCmp(MachineInstr &I) const { SelectedMI.addImm(0); // op_sel RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI); - if (!constrainSelectedInstRegOperands(*SelectedMI, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*SelectedMI, TII, TRI, RBI); I.eraseFromParent(); return true; @@ -1660,8 +1668,7 @@ bool AMDGPUInstructionSelector::selectBallot(MachineInstr &I) const { .addReg(SrcReg) .addReg(TRI.getExec()) .setOperandDead(3); // Dead scc - if (!constrainSelectedInstRegOperands(*And, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*And, TII, TRI, RBI); } } @@ -1728,7 +1735,8 @@ bool AMDGPUInstructionSelector::selectGroupStaticSize(MachineInstr &I) const { } I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectReturnAddress(MachineInstr &I) const { @@ -1852,9 +1860,9 @@ bool AMDGPUInstructionSelector::selectDSOrderedIntrinsic( if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI)) return false; - bool Ret = constrainSelectedInstRegOperands(*DS, TII, TRI, RBI); + constrainSelectedInstRegOperands(*DS, TII, TRI, RBI); MI.eraseFromParent(); - return Ret; + return true; } static unsigned gwsIntrinToOpcode(unsigned IntrID) { @@ -2028,7 +2036,8 @@ bool AMDGPUInstructionSelector::selectDSAppendConsume(MachineInstr &MI, .addImm(IsGDS ? -1 : 0) .cloneMemRefs(MI); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectInitWholeWave(MachineInstr &MI) const { @@ -2340,7 +2349,8 @@ bool AMDGPUInstructionSelector::selectDSBvhStackIntrinsic( .cloneMemRefs(MI); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS( @@ -2442,11 +2452,10 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const { .add(I.getOperand(2)) .add(I.getOperand(3)); - bool Ret = false; - Ret |= constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); - Ret |= constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); + constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI); I.eraseFromParent(); - return Ret; + return true; } // Wide VGPR select should have been split in RegBankSelect. @@ -2461,9 +2470,9 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const { .add(I.getOperand(2)) .add(I.getOperand(1)); - bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); I.eraseFromParent(); - return Ret; + return true; } bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const { @@ -2679,7 +2688,8 @@ bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const { .addImm(Mask) .addReg(SrcReg); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); + return true; } const unsigned BFE = Signed ? AMDGPU::V_BFE_I32_e64 : AMDGPU::V_BFE_U32_e64; @@ -2689,7 +2699,8 @@ bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const { .addImm(0) // Offset .addImm(SrcSize); // Width I.eraseFromParent(); - return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); + return true; } if (SrcBank->getID() == AMDGPU::SGPRRegBankID && DstSize <= 64) { @@ -3163,7 +3174,8 @@ bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const { .addReg(MaskReg) .setOperandDead(3); // Dead scc I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32; @@ -3538,7 +3550,8 @@ bool AMDGPUInstructionSelector::selectBufferLoadLds(MachineInstr &MI) const { MIB.setMemRefs({LoadMMO, StoreMMO}); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } /// Match a zero extend from a 32-bit value to 64-bits. @@ -3725,7 +3738,8 @@ bool AMDGPUInstructionSelector::selectGlobalLoadLds(MachineInstr &MI) const{ MIB.setMemRefs({LoadMMO, StoreMMO}); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectBVHIntersectRayIntrinsic( @@ -3735,7 +3749,8 @@ bool AMDGPUInstructionSelector::selectBVHIntersectRayIntrinsic( MI.setDesc(TII.get(MI.getOperand(OpcodeOpIdx).getImm())); MI.removeOperand(OpcodeOpIdx); MI.addImplicitDefUseOperands(*MI.getMF()); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } // FIXME: This should be removed and let the patterns select. We just need the @@ -3865,7 +3880,8 @@ bool AMDGPUInstructionSelector::selectPermlaneSwapIntrin( MachineOperand &FI = MI.getOperand(4); FI.setImm(FI.getImm() ? AMDGPU::DPP::DPP_FI_1 : AMDGPU::DPP::DPP_FI_0); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectWaveAddress(MachineInstr &MI) const { @@ -4100,7 +4116,7 @@ static std::pair BitOp3_Op(Register R, SmallVector Backup(Src.begin(), Src.end()); if (!getOperandBits(LHS, LHSBits) || !getOperandBits(RHS, RHSBits)) { - Src = Backup; + Src = std::move(Backup); return std::make_pair(0, 0); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td index 37904872d775c..f77b4c9d9642c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -743,6 +743,8 @@ int FP32_ONE = 0x3f800000; int FP32_NEG_ONE = 0xbf800000; int FP64_ONE = 0x3ff0000000000000; int FP64_NEG_ONE = 0xbff0000000000000; +int BF16_ONE = 0x3F80; +int BF16_NEG_ONE = 0xBF80; } def CONST : Constants; diff --git a/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h b/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h index df80196d95176..95d88c7af368c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h +++ b/llvm/lib/Target/AMDGPU/AMDGPULaneMaskUtils.h @@ -31,10 +31,12 @@ class LaneMaskConstants { const unsigned AndSaveExecTermOpc; const unsigned BfmOpc; const unsigned CMovOpc; + const unsigned CmpLGOp; const unsigned CSelectOpc; const unsigned MovOpc; const unsigned MovTermOpc; const unsigned OrOpc; + const unsigned OrN2Op; const unsigned OrTermOpc; const unsigned OrSaveExecOpc; const unsigned XorOpc; @@ -57,10 +59,12 @@ class LaneMaskConstants { : AMDGPU::S_AND_SAVEEXEC_B64_term), BfmOpc(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64), CMovOpc(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64), + CmpLGOp(IsWave32 ? AMDGPU::S_CMP_LG_U32 : AMDGPU::S_CMP_LG_U64), CSelectOpc(IsWave32 ? AMDGPU::S_CSELECT_B32 : AMDGPU::S_CSELECT_B64), MovOpc(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), MovTermOpc(IsWave32 ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term), OrOpc(IsWave32 ? AMDGPU::S_OR_B32 : AMDGPU::S_OR_B64), + OrN2Op(IsWave32 ? AMDGPU::S_ORN2_B32 : AMDGPU::S_ORN2_B64), OrTermOpc(IsWave32 ? AMDGPU::S_OR_B32_term : AMDGPU::S_OR_B64_term), OrSaveExecOpc(IsWave32 ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64), diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 2b2046fb9f65b..5a993a456439e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -30,6 +30,7 @@ #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/PseudoSourceValueManager.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/IR/DiagnosticInfo.h" @@ -1056,6 +1057,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, .customFor({{S32, S32}, {S64, S32}, {S16, S16}, {S16, S32}}) .scalarize(0) .lower(); + + getActionDefinitionsBuilder(G_FMODF) + .lowerFor({S16, S32, S64}) + .scalarize(0) + .lower(); } else { getActionDefinitionsBuilder(G_FSQRT) .customFor({S32, S64, S16}) @@ -1089,6 +1095,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, .minScalar(0, S32) .clampScalar(1, S32, S32) .lower(); + + getActionDefinitionsBuilder(G_FMODF) + .lowerFor({S32, S64}) + .scalarize(0) + .lower(); } auto &FPTruncActions = getActionDefinitionsBuilder(G_FPTRUNC); @@ -3543,14 +3554,10 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI, Register X = MI.getOperand(1).getReg(); unsigned Flags = MI.getFlags(); const LLT Ty = MRI.getType(X); - MachineFunction &MF = B.getMF(); const LLT F32 = LLT::scalar(32); const LLT F16 = LLT::scalar(16); - const AMDGPUTargetMachine &TM = - static_cast(MF.getTarget()); - if (Ty == F16 || MI.getFlag(MachineInstr::FmAfn)) { if (Ty == F16 && !ST.has16BitInsts()) { Register LogVal = MRI.createGenericVirtualRegister(F32); @@ -3619,8 +3626,7 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI, } const bool IsFiniteOnly = - (MI.getFlag(MachineInstr::FmNoNans) || TM.Options.NoNaNsFPMath) && - MI.getFlag(MachineInstr::FmNoInfs); + MI.getFlag(MachineInstr::FmNoNans) && MI.getFlag(MachineInstr::FmNoInfs); if (!IsFiniteOnly) { // Expand isfinite(x) => fabs(x) < inf @@ -7759,6 +7765,24 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, // Replace the use G_BRCOND with the exec manipulate and branch pseudos. auto IntrID = cast(MI).getIntrinsicID(); switch (IntrID) { + case Intrinsic::sponentry: + if (B.getMF().getInfo()->isBottomOfStack()) { + // FIXME: The imported pattern checks for i32 instead of p5; if we fix + // that we can remove this cast. + const LLT S32 = LLT::scalar(32); + Register TmpReg = MRI.createGenericVirtualRegister(S32); + B.buildInstr(AMDGPU::G_AMDGPU_SPONENTRY).addDef(TmpReg); + + Register DstReg = MI.getOperand(0).getReg(); + B.buildIntToPtr(DstReg, TmpReg); + MI.eraseFromParent(); + } else { + int FI = B.getMF().getFrameInfo().CreateFixedObject( + 1, 0, /*IsImmutable=*/false); + B.buildFrameIndex(MI.getOperand(0), FI); + MI.eraseFromParent(); + } + return true; case Intrinsic::amdgcn_if: case Intrinsic::amdgcn_else: { MachineInstr *Br = nullptr; @@ -8180,6 +8204,26 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, B.buildStore(MI.getOperand(2), MI.getOperand(1), **MI.memoperands_begin()); MI.eraseFromParent(); return true; + case Intrinsic::amdgcn_flat_load_monitor_b32: + case Intrinsic::amdgcn_flat_load_monitor_b64: + case Intrinsic::amdgcn_flat_load_monitor_b128: + assert(MI.hasOneMemOperand() && "Expected IRTranslator to set MemOp!"); + B.buildInstr(AMDGPU::G_AMDGPU_FLAT_LOAD_MONITOR) + .add(MI.getOperand(0)) + .add(MI.getOperand(2)) + .addMemOperand(*MI.memoperands_begin()); + MI.eraseFromParent(); + return true; + case Intrinsic::amdgcn_global_load_monitor_b32: + case Intrinsic::amdgcn_global_load_monitor_b64: + case Intrinsic::amdgcn_global_load_monitor_b128: + assert(MI.hasOneMemOperand() && "Expected IRTranslator to set MemOp!"); + B.buildInstr(AMDGPU::G_AMDGPU_GLOBAL_LOAD_MONITOR) + .add(MI.getOperand(0)) + .add(MI.getOperand(2)) + .addMemOperand(*MI.memoperands_begin()); + MI.eraseFromParent(); + return true; default: { if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr = AMDGPU::getImageDimIntrinsicInfo(IntrID)) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp index 4a553beb63bb1..4de9349fe5166 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp @@ -1041,22 +1041,33 @@ bool AMDGPULibCalls::fold_pow(FPMathOperator *FPOp, IRBuilder<> &B, opr1 = B.CreateSIToFP(opr1, nval->getType(), "pownI2F"); } nval = B.CreateFMul(opr1, nval, "__ylogx"); - nval = CreateCallEx(B,ExpExpr, nval, "__exp2"); + + CallInst *Exp2Call = CreateCallEx(B, ExpExpr, nval, "__exp2"); + + // TODO: Generalized fpclass logic for pow + FPClassTest KnownNot = FPClassTest::fcNegative; + if (FPOp->hasNoNaNs()) + KnownNot |= FPClassTest::fcNan; + + Exp2Call->addRetAttr( + Attribute::getWithNoFPClass(Exp2Call->getContext(), KnownNot)); + nval = Exp2Call; if (needcopysign) { Type* nTyS = B.getIntNTy(eltType->getPrimitiveSizeInBits()); Type *nTy = FPOp->getType()->getWithNewType(nTyS); - unsigned size = nTy->getScalarSizeInBits(); Value *opr_n = FPOp->getOperand(1); if (opr_n->getType()->getScalarType()->isIntegerTy()) opr_n = B.CreateZExtOrTrunc(opr_n, nTy, "__ytou"); else opr_n = B.CreateFPToSI(opr1, nTy, "__ytou"); + unsigned size = nTy->getScalarSizeInBits(); Value *sign = B.CreateShl(opr_n, size-1, "__yeven"); sign = B.CreateAnd(B.CreateBitCast(opr0, nTy), sign, "__pow_sign"); - nval = B.CreateOr(B.CreateBitCast(nval, nTy), sign); - nval = B.CreateBitCast(nval, opr0->getType()); + + nval = B.CreateCopySign(nval, B.CreateBitCast(sign, nval->getType()), + nullptr, "__pow_sign"); } LLVM_DEBUG(errs() << "AMDIC: " << *FPOp << " ---> " diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp index 97e7a239e1099..c4762602fa169 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp @@ -635,7 +635,8 @@ bool StoreFatPtrsAsIntsAndExpandMemcpyVisitor::visitMemSetInst( MemSetInst &MSI) { if (MSI.getDestAddressSpace() != AMDGPUAS::BUFFER_FAT_POINTER) return false; - llvm::expandMemSetAsLoop(&MSI); + llvm::expandMemSetAsLoop(&MSI, + TM->getTargetTransformInfo(*MSI.getFunction())); MSI.eraseFromParent(); return true; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp index 0137b3f5943d7..a43600af8b085 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp @@ -46,10 +46,7 @@ class AMDGPUPrepareAGPRAllocLegacy : public MachineFunctionPass { public: static char ID; - AMDGPUPrepareAGPRAllocLegacy() : MachineFunctionPass(ID) { - initializeAMDGPUPrepareAGPRAllocLegacyPass( - *PassRegistry::getPassRegistry()); - } + AMDGPUPrepareAGPRAllocLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; @@ -62,10 +59,8 @@ class AMDGPUPrepareAGPRAllocLegacy : public MachineFunctionPass { }; } // End anonymous namespace. -INITIALIZE_PASS_BEGIN(AMDGPUPrepareAGPRAllocLegacy, DEBUG_TYPE, - "AMDGPU Prepare AGPR Alloc", false, false) -INITIALIZE_PASS_END(AMDGPUPrepareAGPRAllocLegacy, DEBUG_TYPE, - "AMDGPU Prepare AGPR Alloc", false, false) +INITIALIZE_PASS(AMDGPUPrepareAGPRAllocLegacy, DEBUG_TYPE, + "AMDGPU Prepare AGPR Alloc", false, false) char AMDGPUPrepareAGPRAllocLegacy::ID = 0; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index d18d3a13b29ea..ed676c3fde2f8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -606,21 +606,6 @@ static Value *promoteAllocaUserToVector(Instruction *Inst, const DataLayout &DL, InstSimplifyFolder(DL)); Builder.SetInsertPoint(Inst); - const auto CreateTempPtrIntCast = [&Builder, DL](Value *Val, - Type *PtrTy) -> Value * { - assert(DL.getTypeStoreSize(Val->getType()) == DL.getTypeStoreSize(PtrTy)); - const unsigned Size = DL.getTypeStoreSizeInBits(PtrTy); - if (!PtrTy->isVectorTy()) - return Builder.CreateBitOrPointerCast(Val, Builder.getIntNTy(Size)); - const unsigned NumPtrElts = cast(PtrTy)->getNumElements(); - // If we want to cast to cast, e.g. a <2 x ptr> into a <4 x i32>, we need to - // first cast the ptr vector to <2 x i64>. - assert((Size % NumPtrElts == 0) && "Vector size not divisble"); - Type *EltTy = Builder.getIntNTy(Size / NumPtrElts); - return Builder.CreateBitOrPointerCast( - Val, FixedVectorType::get(EltTy, NumPtrElts)); - }; - Type *VecEltTy = AA.Vector.Ty->getElementType(); switch (Inst->getOpcode()) { @@ -634,12 +619,8 @@ static Value *promoteAllocaUserToVector(Instruction *Inst, const DataLayout &DL, TypeSize AccessSize = DL.getTypeStoreSize(AccessTy); if (Constant *CI = dyn_cast(Index)) { if (CI->isZeroValue() && AccessSize == VecStoreSize) { - if (AccessTy->isPtrOrPtrVectorTy()) - CurVal = CreateTempPtrIntCast(CurVal, AccessTy); - else if (CurVal->getType()->isPtrOrPtrVectorTy()) - CurVal = CreateTempPtrIntCast(CurVal, CurVal->getType()); - Value *NewVal = Builder.CreateBitOrPointerCast(CurVal, AccessTy); - Inst->replaceAllUsesWith(NewVal); + Inst->replaceAllUsesWith( + Builder.CreateBitPreservingCastChain(DL, CurVal, AccessTy)); return nullptr; } } @@ -689,13 +670,8 @@ static Value *promoteAllocaUserToVector(Instruction *Inst, const DataLayout &DL, SubVec, Builder.CreateExtractElement(CurVal, CurIdx), K); } - if (AccessTy->isPtrOrPtrVectorTy()) - SubVec = CreateTempPtrIntCast(SubVec, AccessTy); - else if (SubVecTy->isPtrOrPtrVectorTy()) - SubVec = CreateTempPtrIntCast(SubVec, SubVecTy); - - SubVec = Builder.CreateBitOrPointerCast(SubVec, AccessTy); - Inst->replaceAllUsesWith(SubVec); + Inst->replaceAllUsesWith( + Builder.CreateBitPreservingCastChain(DL, SubVec, AccessTy)); return nullptr; } @@ -719,15 +695,9 @@ static Value *promoteAllocaUserToVector(Instruction *Inst, const DataLayout &DL, // We're storing the full vector, we can handle this without knowing CurVal. Type *AccessTy = Val->getType(); TypeSize AccessSize = DL.getTypeStoreSize(AccessTy); - if (Constant *CI = dyn_cast(Index)) { - if (CI->isZeroValue() && AccessSize == VecStoreSize) { - if (AccessTy->isPtrOrPtrVectorTy()) - Val = CreateTempPtrIntCast(Val, AccessTy); - else if (AA.Vector.Ty->isPtrOrPtrVectorTy()) - Val = CreateTempPtrIntCast(Val, AA.Vector.Ty); - return Builder.CreateBitOrPointerCast(Val, AA.Vector.Ty); - } - } + if (Constant *CI = dyn_cast(Index)) + if (CI->isZeroValue() && AccessSize == VecStoreSize) + return Builder.CreateBitPreservingCastChain(DL, Val, AA.Vector.Ty); // Storing a subvector. if (isa(AccessTy)) { @@ -738,13 +708,7 @@ static Value *promoteAllocaUserToVector(Instruction *Inst, const DataLayout &DL, auto *SubVecTy = FixedVectorType::get(VecEltTy, NumWrittenElts); assert(DL.getTypeStoreSize(SubVecTy) == DL.getTypeStoreSize(AccessTy)); - if (SubVecTy->isPtrOrPtrVectorTy()) - Val = CreateTempPtrIntCast(Val, SubVecTy); - else if (AccessTy->isPtrOrPtrVectorTy()) - Val = CreateTempPtrIntCast(Val, AccessTy); - - Val = Builder.CreateBitOrPointerCast(Val, SubVecTy); - + Val = Builder.CreateBitPreservingCastChain(DL, Val, SubVecTy); Value *CurVec = GetCurVal(); for (unsigned K = 0, NumElts = std::min(NumWrittenElts, NumVecElts); K < NumElts; ++K) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp index c77a4e79d70ea..888717f13ebe9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp @@ -468,16 +468,8 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) { // Opcodes that support pretty much all combinations of reg banks and LLTs // (except S1). There is no point in writing rules for them. - if (Opc == AMDGPU::G_BUILD_VECTOR || Opc == AMDGPU::G_UNMERGE_VALUES || - Opc == AMDGPU::G_MERGE_VALUES || Opc == AMDGPU::G_CONCAT_VECTORS || - Opc == AMDGPU::G_BITCAST) { - RBLHelper.applyMappingTrivial(*MI); - continue; - } - - // Opcodes that also support S1. - if (Opc == G_FREEZE && - MRI.getType(MI->getOperand(0).getReg()) != LLT::scalar(1)) { + if (Opc == AMDGPU::G_BUILD_VECTOR || Opc == AMDGPU::G_MERGE_VALUES || + Opc == AMDGPU::G_CONCAT_VECTORS || Opc == AMDGPU::G_BITCAST) { RBLHelper.applyMappingTrivial(*MI); continue; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp index e7687a250d1a4..d262f074679a8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp @@ -650,13 +650,8 @@ bool RegBankLegalizeHelper::lowerS_BFE(MachineInstr &MI) { // copies from reg class to reg bank. auto S_BFE = B.buildInstr(Opc, {{SgprRB, Ty}}, {B.buildCopy(Ty, Src), B.buildCopy(S32, Src1)}); - if (!constrainSelectedInstRegOperands(*S_BFE, *ST.getInstrInfo(), - *ST.getRegisterInfo(), RBI)) { - reportGISelFailure( - MF, MORE, "amdgpu-regbanklegalize", - "AMDGPU RegBankLegalize: lowerS_BFE, failed to constrain BFE", MI); - return false; - } + constrainSelectedInstRegOperands(*S_BFE, *ST.getInstrInfo(), + *ST.getRegisterInfo(), RBI); B.buildCopy(DstReg, S_BFE->getOperand(0).getReg()); MI.eraseFromParent(); @@ -1012,6 +1007,55 @@ bool RegBankLegalizeHelper::lower(MachineInstr &MI, return lowerUnpackAExt(MI); case WidenMMOToS32: return widenMMOToS32(cast(MI)); + case VerifyAllSgpr: { + assert(llvm::all_of(MI.operands(), [&](const MachineOperand &Op) { + return MRI.getRegBankOrNull(Op.getReg()) == SgprRB; + })); + return true; + } + case ApplyAllVgpr: { + assert(llvm::all_of(MI.defs(), [&](const MachineOperand &Op) { + return MRI.getRegBankOrNull(Op.getReg()) == VgprRB; + })); + B.setInstrAndDebugLoc(MI); + for (unsigned i = MI.getNumDefs(); i < MI.getNumOperands(); ++i) { + Register Reg = MI.getOperand(i).getReg(); + if (MRI.getRegBank(Reg) != VgprRB) { + auto Copy = B.buildCopy({VgprRB, MRI.getType(Reg)}, Reg); + MI.getOperand(i).setReg(Copy.getReg(0)); + } + } + return true; + } + case UnmergeToShiftTrunc: { + GUnmerge *Unmerge = dyn_cast(&MI); + LLT Ty = MRI.getType(Unmerge->getSourceReg()); + if (Ty.getSizeInBits() % 32 != 0) { + reportGISelFailure(MF, MORE, "amdgpu-regbanklegalize", + "AMDGPU RegBankLegalize: unmerge not multiple of 32", + MI); + return false; + } + + B.setInstrAndDebugLoc(MI); + if (Ty.getSizeInBits() > 32) { + auto UnmergeV2S16 = + B.buildUnmerge({SgprRB, V2S16}, Unmerge->getSourceReg()); + for (unsigned i = 0; i < UnmergeV2S16->getNumDefs(); ++i) { + auto [Dst0S32, Dst1S32] = + unpackAExt(UnmergeV2S16->getOperand(i).getReg()); + B.buildTrunc(MI.getOperand(i * 2).getReg(), Dst0S32); + B.buildTrunc(MI.getOperand(i * 2 + 1).getReg(), Dst1S32); + } + } else { + auto [Dst0S32, Dst1S32] = unpackAExt(MI.getOperand(2).getReg()); + B.buildTrunc(MI.getOperand(0).getReg(), Dst0S32); + B.buildTrunc(MI.getOperand(1).getReg(), Dst1S32); + } + + MI.eraseFromParent(); + return true; + } } if (!WaterfallSgprs.empty()) { @@ -1134,6 +1178,11 @@ LLT RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) { isAnyPtr(Ty, 128)) return Ty; return LLT(); + case VgprB160: + case UniInVgprB160: + if (Ty.getSizeInBits() == 160) + return Ty; + return LLT(); case SgprB256: case VgprB256: case UniInVgprB256: @@ -1148,6 +1197,21 @@ LLT RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) { Ty == LLT::fixed_vector(8, 64)) return Ty; return LLT(); + case SgprBRC: { + const SIRegisterInfo *TRI = + static_cast(MRI.getTargetRegisterInfo()); + unsigned LLTSize = Ty.getSizeInBits(); + if (LLTSize >= 32 && TRI->getSGPRClassForBitWidth(LLTSize)) + return Ty; + return LLT(); + } + case VgprBRC: { + const SIRegisterInfo *TRI = + static_cast(MRI.getTargetRegisterInfo()); + if (TRI->getSGPRClassForBitWidth(Ty.getSizeInBits())) + return Ty; + return LLT(); + } default: return LLT(); } @@ -1183,6 +1247,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) { case SgprB128: case SgprB256: case SgprB512: + case SgprBRC: case UniInVcc: case UniInVgprS16: case UniInVgprS32: @@ -1195,6 +1260,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) { case UniInVgprB64: case UniInVgprB96: case UniInVgprB128: + case UniInVgprB160: case UniInVgprB256: case UniInVgprB512: case Sgpr32Trunc: @@ -1225,8 +1291,10 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) { case VgprB64: case VgprB96: case VgprB128: + case VgprB160: case VgprB256: case VgprB512: + case VgprBRC: case Vgpr32AExt: case Vgpr32SExt: case Vgpr32ZExt: @@ -1290,6 +1358,7 @@ bool RegBankLegalizeHelper::applyMappingDst( case SgprB128: case SgprB256: case SgprB512: + case SgprBRC: case SgprPtr32: case SgprPtr64: case SgprPtr128: @@ -1297,8 +1366,10 @@ bool RegBankLegalizeHelper::applyMappingDst( case VgprB64: case VgprB96: case VgprB128: + case VgprB160: case VgprB256: case VgprB512: + case VgprBRC: case VgprPtr32: case VgprPtr64: case VgprPtr128: { @@ -1348,6 +1419,7 @@ bool RegBankLegalizeHelper::applyMappingDst( case UniInVgprB64: case UniInVgprB96: case UniInVgprB128: + case UniInVgprB160: case UniInVgprB256: case UniInVgprB512: { assert(Ty == getBTyFromID(MethodIDs[OpIdx], Ty)); @@ -1434,6 +1506,7 @@ bool RegBankLegalizeHelper::applyMappingSrc( case SgprB128: case SgprB256: case SgprB512: + case SgprBRC: case SgprPtr32: case SgprPtr64: case SgprPtr128: { @@ -1469,8 +1542,10 @@ bool RegBankLegalizeHelper::applyMappingSrc( case VgprB64: case VgprB96: case VgprB128: + case VgprB160: case VgprB256: case VgprB512: + case VgprBRC: case VgprPtr32: case VgprPtr64: case VgprPtr128: { diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp index b2fbea7f36a43..ae97cef14ced9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp @@ -90,6 +90,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID, return MRI.getType(Reg).getSizeInBits() == 96; case B128: return MRI.getType(Reg).getSizeInBits() == 128; + case B160: + return MRI.getType(Reg).getSizeInBits() == 160; case B256: return MRI.getType(Reg).getSizeInBits() == 256; case B512: @@ -136,10 +138,23 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID, return MRI.getType(Reg).getSizeInBits() == 96 && MUI.isUniform(Reg); case UniB128: return MRI.getType(Reg).getSizeInBits() == 128 && MUI.isUniform(Reg); + case UniB160: + return MRI.getType(Reg).getSizeInBits() == 160 && MUI.isUniform(Reg); case UniB256: return MRI.getType(Reg).getSizeInBits() == 256 && MUI.isUniform(Reg); case UniB512: return MRI.getType(Reg).getSizeInBits() == 512 && MUI.isUniform(Reg); + case UniBRC: { + if (!MUI.isUniform(Reg)) + return false; + // Check if there is SGPR register class of same size as the LLT. + const SIRegisterInfo *TRI = + static_cast(MRI.getTargetRegisterInfo()); + // There is no 16 bit SGPR register class. Extra size check is required + // since getSGPRClassForBitWidth returns SReg_32RegClass for Size 16. + unsigned LLTSize = MRI.getType(Reg).getSizeInBits(); + return LLTSize >= 32 && TRI->getSGPRClassForBitWidth(LLTSize); + } case DivS1: return MRI.getType(Reg) == LLT::scalar(1) && MUI.isDivergent(Reg); case DivS16: @@ -180,10 +195,20 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID, return MRI.getType(Reg).getSizeInBits() == 96 && MUI.isDivergent(Reg); case DivB128: return MRI.getType(Reg).getSizeInBits() == 128 && MUI.isDivergent(Reg); + case DivB160: + return MRI.getType(Reg).getSizeInBits() == 160 && MUI.isDivergent(Reg); case DivB256: return MRI.getType(Reg).getSizeInBits() == 256 && MUI.isDivergent(Reg); case DivB512: return MRI.getType(Reg).getSizeInBits() == 512 && MUI.isDivergent(Reg); + case DivBRC: { + if (!MUI.isDivergent(Reg)) + return false; + // Check if there is VGPR register class of same size as the LLT. + const SIRegisterInfo *TRI = + static_cast(MRI.getTargetRegisterInfo()); + return TRI->getSGPRClassForBitWidth(MRI.getType(Reg).getSizeInBits()); + } case _: return true; default: @@ -250,7 +275,8 @@ UniformityLLTOpPredicateID LLTToBId(LLT Ty) { return B64; if (Ty == LLT::fixed_vector(3, 32)) return B96; - if (Ty == LLT::fixed_vector(4, 32) || isAnyPtr(Ty, 128)) + if (Ty == LLT::fixed_vector(4, 32) || Ty == LLT::fixed_vector(2, 64) || + Ty == LLT::fixed_vector(8, 16) || isAnyPtr(Ty, 128)) return B128; return _; } @@ -292,14 +318,14 @@ void SetOfRulesForOpcode::addFastRuleDivergent(UniformityLLTOpPredicateID Ty, RegBankLLTMapping RuleApplyIDs) { int Slot = getFastPredicateSlot(Ty); assert(Slot != -1 && "Ty unsupported in this FastRulesTypes"); - Div[Slot] = RuleApplyIDs; + Div[Slot] = std::move(RuleApplyIDs); } void SetOfRulesForOpcode::addFastRuleUniform(UniformityLLTOpPredicateID Ty, RegBankLLTMapping RuleApplyIDs) { int Slot = getFastPredicateSlot(Ty); assert(Slot != -1 && "Ty unsupported in this FastRulesTypes"); - Uni[Slot] = RuleApplyIDs; + Uni[Slot] = std::move(RuleApplyIDs); } int SetOfRulesForOpcode::getFastPredicateSlot( @@ -491,7 +517,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(S32, {{Sgpr32, Sgpr32Trunc}, {Sgpr32, Sgpr32}}) .Div(S32, {{Vgpr32, Vcc}, {Vgpr32, Vgpr32}}); - addRulesForGOpcs({G_UADDE, G_USUBE}, Standard) + addRulesForGOpcs({G_UADDE, G_USUBE, G_SADDE, G_SSUBE}, Standard) .Uni(S32, {{Sgpr32, Sgpr32Trunc}, {Sgpr32, Sgpr32, Sgpr32AExtBoolInReg}}) .Div(S32, {{Vgpr32, Vcc}, {Vgpr32, Vgpr32, Vcc}}); @@ -598,12 +624,23 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}, UnpackMinMax}) .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}}); - // Note: we only write S1 rules for G_IMPLICIT_DEF, G_CONSTANT, G_FCONSTANT - // and G_FREEZE here, rest is trivially regbankselected earlier + // Note: we only write S1 rules for G_IMPLICIT_DEF, G_CONSTANT and G_FCONSTANT + // here, rest is trivially regbankselected earlier addRulesForGOpcs({G_IMPLICIT_DEF}).Any({{UniS1}, {{Sgpr32Trunc}, {}}}); addRulesForGOpcs({G_CONSTANT}) .Any({{UniS1, _}, {{Sgpr32Trunc}, {None}, UniCstExt}}); - addRulesForGOpcs({G_FREEZE}).Any({{DivS1}, {{Vcc}, {Vcc}}}); + + addRulesForGOpcs({G_FREEZE}) + .Any({{UniS1}, {{Sgpr32Trunc}, {Sgpr32AExt}}}) + .Any({{DivS1}, {{Vcc}, {Vcc}}}) + .Any({{UniS16}, {{Sgpr16}, {Sgpr16}}}) + .Any({{UniBRC}, {{SgprBRC}, {SgprBRC}}}) + .Any({{DivBRC}, {{VgprBRC}, {VgprBRC}}}); + + addRulesForGOpcs({G_UNMERGE_VALUES}) + .Any({{UniS16}, {{}, {}, UnmergeToShiftTrunc}}) + .Any({{UniBRC}, {{}, {}, VerifyAllSgpr}}) + .Any({{DivBRC}, {{}, {}, ApplyAllVgpr}}); Predicate isSignedICmp([](const MachineInstr &MI) -> bool { auto Pred = @@ -991,18 +1028,43 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Div(B32, {{VgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) .Uni(B32, {{UniInVgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}); - addRulesForGOpcs({G_AMDGPU_BUFFER_STORE, G_AMDGPU_BUFFER_STORE_FORMAT, + addRulesForGOpcs( + {G_AMDGPU_BUFFER_LOAD_UBYTE_TFE, G_AMDGPU_BUFFER_LOAD_USHORT_TFE}, + StandardB) + .Div(B64, {{VgprB64}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Uni(B64, {{UniInVgprB64}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}); + + addRulesForGOpcs({G_AMDGPU_BUFFER_LOAD_TFE, G_AMDGPU_BUFFER_LOAD_FORMAT_TFE}, + StandardB) + .Div(B64, {{VgprB64}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Uni(B64, {{UniInVgprB64}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Div(B96, {{VgprB96}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Uni(B96, {{UniInVgprB96}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Div(B128, {{VgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Uni(B128, {{UniInVgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Any({{DivB160}, {{VgprB160}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}) + .Any({{UniB160}, + {{UniInVgprB160}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}); + + addRulesForGOpcs( + {G_AMDGPU_BUFFER_LOAD_FORMAT_D16, G_AMDGPU_TBUFFER_LOAD_FORMAT_D16}, + StandardB) + .Div(B32, {{VgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Uni(B32, {{UniInVgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Div(B64, {{VgprB64}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Uni(B64, {{UniInVgprB64}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Div(B128, {{VgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}) + .Uni(B128, {{UniInVgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}); + + addRulesForGOpcs({G_AMDGPU_BUFFER_STORE, G_AMDGPU_BUFFER_STORE_BYTE, + G_AMDGPU_BUFFER_STORE_SHORT, G_AMDGPU_BUFFER_STORE_FORMAT, G_AMDGPU_BUFFER_STORE_FORMAT_D16, - G_AMDGPU_TBUFFER_STORE_FORMAT}) + G_AMDGPU_TBUFFER_STORE_FORMAT, + G_AMDGPU_TBUFFER_STORE_FORMAT_D16}) .Any({{B32}, {{}, {VgprB32, SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}) .Any({{B64}, {{}, {VgprB64, SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}) - .Any({{B128}, {{}, {VgprB128, SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}) - .Any( - {{V2S32}, {{}, {VgprV2S32, SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}) - .Any( - {{V3S32}, {{}, {VgprV3S32, SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}) - .Any({{V4S32}, - {{}, {VgprV4S32, SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}); + .Any({{B96}, {{}, {VgprB96, SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}) + .Any({{B128}, {{}, {VgprB128, SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}}}); addRulesForGOpcs({G_PTR_ADD}) .Any({{UniPtr32}, {{SgprPtr32}, {SgprPtr32, Sgpr32}}}) @@ -1096,7 +1158,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr32}}) .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr32}}); - addRulesForGOpcs({G_FMA}, Standard) + addRulesForGOpcs({G_FMA, G_STRICT_FMA}, Standard) .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16, Vgpr16}}) .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}}) .Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr64, Vgpr64}}) @@ -1158,14 +1220,29 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Any({{UniV2S32}, {{UniInVgprV2S32}, {VgprV2S32}}}) .Any({{DivV2S32}, {{VgprV2S32}, {VgprV2S32}}}); - addRulesForGOpcs({G_FPTOUI}) + addRulesForGOpcs({G_FPTOUI, G_FPTOSI}) + .Any({{UniS16, S16}, {{UniInVgprS16}, {Vgpr16}}}) + .Any({{DivS16, S16}, {{Vgpr16}, {Vgpr16}}}) + .Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}}, hasSALUFloat) + .Any({{UniS32, S16}, {{UniInVgprS32}, {Vgpr16}}}, !hasSALUFloat) + .Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}}) .Any({{UniS32, S32}, {{Sgpr32}, {Sgpr32}}}, hasSALUFloat) - .Any({{UniS32, S32}, {{UniInVgprS32}, {Vgpr32}}}, !hasSALUFloat); - - addRulesForGOpcs({G_UITOFP}) + .Any({{UniS32, S32}, {{UniInVgprS32}, {Vgpr32}}}, !hasSALUFloat) .Any({{DivS32, S32}, {{Vgpr32}, {Vgpr32}}}) + .Any({{UniS32, S64}, {{UniInVgprS32}, {Vgpr64}}}) + .Any({{DivS32, S64}, {{Vgpr32}, {Vgpr64}}}); + + addRulesForGOpcs({G_UITOFP, G_SITOFP}) + .Any({{UniS16, S16}, {{UniInVgprS16}, {Vgpr16}}}) + .Any({{DivS16, S16}, {{Vgpr16}, {Vgpr16}}}) + .Any({{UniS16, S32}, {{Sgpr16}, {Sgpr32}}}, hasSALUFloat) + .Any({{UniS16, S32}, {{UniInVgprS16}, {Vgpr32}}}, !hasSALUFloat) + .Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}}) .Any({{UniS32, S32}, {{Sgpr32}, {Sgpr32}}}, hasSALUFloat) - .Any({{UniS32, S32}, {{UniInVgprS32}, {Vgpr32}}}, !hasSALUFloat); + .Any({{UniS32, S32}, {{UniInVgprS32}, {Vgpr32}}}, !hasSALUFloat) + .Any({{DivS32, S32}, {{Vgpr32}, {Vgpr32}}}) + .Any({{UniS64, S32}, {{UniInVgprS64}, {Vgpr32}}}) + .Any({{DivS64, S32}, {{Vgpr64}, {Vgpr32}}}); addRulesForGOpcs({G_FPEXT}) .Any({{DivS32, S16}, {{Vgpr32}, {Vgpr16}}}) @@ -1213,6 +1290,16 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST, .Any({{UniS1, _, S64}, {{UniInVcc}, {None, Vgpr64, Vgpr64}}}) .Any({{DivS1, _, S64}, {{Vcc}, {None, Vgpr64, Vgpr64}}}); + addRulesForGOpcs({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUNDEVEN, G_FFLOOR, G_FCEIL, + G_FEXP2, G_FLOG2}, + Standard) + .Uni(S16, {{UniInVgprS16}, {Vgpr16}}) + .Div(S16, {{Vgpr16}, {Vgpr16}}) + .Uni(S32, {{UniInVgprS32}, {Vgpr32}}) + .Div(S32, {{Vgpr32}, {Vgpr32}}) + .Uni(S64, {{UniInVgprS64}, {Vgpr64}}) + .Div(S64, {{Vgpr64}, {Vgpr64}}); + using namespace Intrinsic; addRulesForIOpcs({amdgcn_s_getpc}).Any({{UniS64, _}, {{Sgpr64}, {None}}}); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h index de76773d0aff1..eee4f6276b925 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h @@ -110,6 +110,7 @@ enum UniformityLLTOpPredicateID { B64, B96, B128, + B160, B256, B512, @@ -117,15 +118,19 @@ enum UniformityLLTOpPredicateID { UniB64, UniB96, UniB128, + UniB160, UniB256, UniB512, + UniBRC, DivB32, DivB64, DivB96, DivB128, + DivB160, DivB256, DivB512, + DivBRC }; // How to apply register bank on register operand. @@ -163,6 +168,7 @@ enum RegBankLLTMappingApplyID { SgprB128, SgprB256, SgprB512, + SgprBRC, // vgpr scalars, pointers, vectors and B-types Vgpr16, @@ -185,8 +191,10 @@ enum RegBankLLTMappingApplyID { VgprB64, VgprB96, VgprB128, + VgprB160, VgprB256, VgprB512, + VgprBRC, VgprV4S32, VgprV2S64, @@ -203,6 +211,7 @@ enum RegBankLLTMappingApplyID { UniInVgprB64, UniInVgprB96, UniInVgprB128, + UniInVgprB160, UniInVgprB256, UniInVgprB512, @@ -249,7 +258,10 @@ enum LoweringMethodID { SplitLoad, WidenLoad, WidenMMOToS32, - UnpackAExt + UnpackAExt, + VerifyAllSgpr, + ApplyAllVgpr, + UnmergeToShiftTrunc }; enum FastRulesTypes { diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index bd9ea1f6beb1a..04dbc0721ebf4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -1562,8 +1562,7 @@ bool AMDGPURegisterBankInfo::applyMappingBFE(MachineIRBuilder &B, (Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64); auto MIB = B.buildInstr(Opc, {DstReg}, {SrcReg, MergedInputs}); - if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this)) - llvm_unreachable("failed to constrain BFE"); + constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this); MI.eraseFromParent(); return true; @@ -3500,6 +3499,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl( executeInWaterfallLoop(B, make_range(Start, End), SGPROperandRegs); break; } + case AMDGPU::G_AMDGPU_FLAT_LOAD_MONITOR: + case AMDGPU::G_AMDGPU_GLOBAL_LOAD_MONITOR: case AMDGPU::G_LOAD: case AMDGPU::G_ZEXTLOAD: case AMDGPU::G_SEXTLOAD: { @@ -4585,6 +4586,11 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OpdsMapping[0] = getSGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI); OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI); break; + case AMDGPU::G_AMDGPU_SPONENTRY: { + unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); + OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); + break; + } case AMDGPU::G_INTRINSIC: case AMDGPU::G_INTRINSIC_CONVERGENT: { switch (cast(MI).getIntrinsicID()) { @@ -5338,12 +5344,6 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case Intrinsic::amdgcn_ds_load_tr16_b128: case Intrinsic::amdgcn_ds_load_tr4_b64: case Intrinsic::amdgcn_ds_load_tr6_b96: - case Intrinsic::amdgcn_flat_load_monitor_b32: - case Intrinsic::amdgcn_flat_load_monitor_b64: - case Intrinsic::amdgcn_flat_load_monitor_b128: - case Intrinsic::amdgcn_global_load_monitor_b32: - case Intrinsic::amdgcn_global_load_monitor_b64: - case Intrinsic::amdgcn_global_load_monitor_b128: case Intrinsic::amdgcn_ds_read_tr4_b64: case Intrinsic::amdgcn_ds_read_tr6_b96: case Intrinsic::amdgcn_ds_read_tr8_b64: @@ -5758,6 +5758,14 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_AMDGPU_WHOLE_WAVE_FUNC_RETURN: OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); break; + case AMDGPU::G_AMDGPU_FLAT_LOAD_MONITOR: + case AMDGPU::G_AMDGPU_GLOBAL_LOAD_MONITOR: { + unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); + unsigned PtrSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI); + OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); + OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize); + break; + } } return getInstructionMapping(/*ID*/1, /*Cost*/1, diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp index ffbb1c183ca9e..7a5db42c7a89a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp @@ -595,10 +595,7 @@ class AMDGPURewriteAGPRCopyMFMALegacy : public MachineFunctionPass { static char ID; RegisterClassInfo RegClassInfo; - AMDGPURewriteAGPRCopyMFMALegacy() : MachineFunctionPass(ID) { - initializeAMDGPURewriteAGPRCopyMFMALegacyPass( - *PassRegistry::getPassRegistry()); - } + AMDGPURewriteAGPRCopyMFMALegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f8a83e72bc3ef..49c60c254f6f7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -22,6 +22,7 @@ #include "AMDGPUCtorDtorLowering.h" #include "AMDGPUExportClustering.h" #include "AMDGPUExportKernelRuntimeHandles.h" +#include "AMDGPUHazardLatency.h" #include "AMDGPUIGroupLP.h" #include "AMDGPUISelDAGToDAG.h" #include "AMDGPULowerVGPREncoding.h" @@ -158,10 +159,14 @@ class AMDGPUCodeGenPassBuilder Error addRegAssignmentOptimized(PassManagerWrapper &PMW) const; void addPreRegAlloc(PassManagerWrapper &PMW) const; Error addFastRegAlloc(PassManagerWrapper &PMW) const; - void addOptimizedRegAlloc(PassManagerWrapper &PMW) const; + Error addOptimizedRegAlloc(PassManagerWrapper &PMW) const; void addPreSched2(PassManagerWrapper &PMW) const; void addPostBBSections(PassManagerWrapper &PMW) const; +private: + Error validateRegAllocOptions() const; + +public: /// Check if a pass is enabled given \p Opt option. The option always /// overrides defaults if explicitly used. Otherwise its default will be used /// given that a pass shall work at an optimization \p Level minimum. @@ -243,6 +248,63 @@ static cl::opt SGPRRegAllocNPM( + "sgpr-regalloc-npm", cl::Hidden, cl::init(RegAllocType::Default), + cl::desc("Register allocator for SGPRs (new pass manager)")); + +static cl::opt VGPRRegAllocNPM( + "vgpr-regalloc-npm", cl::Hidden, cl::init(RegAllocType::Default), + cl::desc("Register allocator for VGPRs (new pass manager)")); + +static cl::opt WWMRegAllocNPM( + "wwm-regalloc-npm", cl::Hidden, cl::init(RegAllocType::Default), + cl::desc("Register allocator for WWM registers (new pass manager)")); + +/// Check if the given RegAllocType is supported for AMDGPU NPM register +/// allocation. Only Fast and Greedy are supported; Basic and PBQP are not. +static Error checkRegAllocSupported(RegAllocType RAType, StringRef RegName) { + if (RAType == RegAllocType::Basic || RAType == RegAllocType::PBQP) { + return make_error( + Twine("unsupported register allocator '") + + (RAType == RegAllocType::Basic ? "basic" : "pbqp") + "' for " + + RegName + " registers", + inconvertibleErrorCode()); + } + return Error::success(); +} + +Error AMDGPUCodeGenPassBuilder::validateRegAllocOptions() const { + // 1. Generic --regalloc-npm is not supported for AMDGPU. + if (Opt.RegAlloc != RegAllocType::Unset) { + return make_error( + "-regalloc-npm not supported for amdgcn. Use -sgpr-regalloc-npm, " + "-vgpr-regalloc-npm, and -wwm-regalloc-npm", + inconvertibleErrorCode()); + } + + // 2. Legacy PM regalloc options are not compatible with NPM. + if (SGPRRegAlloc.getNumOccurrences() > 0 || + VGPRRegAlloc.getNumOccurrences() > 0 || + WWMRegAlloc.getNumOccurrences() > 0) { + return make_error( + "-sgpr-regalloc, -vgpr-regalloc, and -wwm-regalloc are legacy PM " + "options. Use -sgpr-regalloc-npm, -vgpr-regalloc-npm, and " + "-wwm-regalloc-npm with the new pass manager", + inconvertibleErrorCode()); + } + + // 3. Only Fast and Greedy allocators are supported for AMDGPU. + if (auto Err = checkRegAllocSupported(SGPRRegAllocNPM, "SGPR")) + return Err; + if (auto Err = checkRegAllocSupported(WWMRegAllocNPM, "WWM")) + return Err; + if (auto Err = checkRegAllocSupported(VGPRRegAllocNPM, "VGPR")) + return Err; + + return Error::success(); +} + static void initializeDefaultSGPRRegisterAllocatorOnce() { RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault(); @@ -653,6 +715,7 @@ createGCNMaxOccupancyMachineScheduler(MachineSchedContext *C) { DAG->addMutation(createAMDGPUMacroFusionDAGMutation()); DAG->addMutation(createAMDGPUExportClusteringDAGMutation()); DAG->addMutation(createAMDGPUBarrierLatencyDAGMutation(C->MF)); + DAG->addMutation(createAMDGPUHazardLatencyDAGMutation(C->MF)); return DAG; } @@ -674,6 +737,7 @@ createGCNMaxMemoryClauseMachineScheduler(MachineSchedContext *C) { DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); DAG->addMutation(createAMDGPUExportClusteringDAGMutation()); DAG->addMutation(createAMDGPUBarrierLatencyDAGMutation(C->MF)); + DAG->addMutation(createAMDGPUHazardLatencyDAGMutation(C->MF)); return DAG; } @@ -1216,6 +1280,7 @@ GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const { DAG->addMutation(createVOPDPairingMutation()); DAG->addMutation(createAMDGPUExportClusteringDAGMutation()); DAG->addMutation(createAMDGPUBarrierLatencyDAGMutation(C->MF)); + DAG->addMutation(createAMDGPUHazardLatencyDAGMutation(C->MF)); return DAG; } //===----------------------------------------------------------------------===// @@ -2323,12 +2388,17 @@ Error AMDGPUCodeGenPassBuilder::addFastRegAlloc(PassManagerWrapper &PMW) const { Error AMDGPUCodeGenPassBuilder::addRegAssignmentFast( PassManagerWrapper &PMW) const { - // TODO: handle default regalloc override error (with regalloc-npm) + if (auto Err = validateRegAllocOptions()) + return Err; addMachineFunctionPass(GCNPreRALongBranchRegPass(), PMW); - addMachineFunctionPass(RegAllocFastPass({onlyAllocateSGPRs, "sgpr", false}), - PMW); + // SGPR allocation - default to fast at -O0. + if (SGPRRegAllocNPM == RegAllocType::Greedy) + addMachineFunctionPass(RAGreedyPass({onlyAllocateSGPRs, "sgpr"}), PMW); + else + addMachineFunctionPass(RegAllocFastPass({onlyAllocateSGPRs, "sgpr", false}), + PMW); // Equivalent of PEI for SGPRs. addMachineFunctionPass(SILowerSGPRSpillsPass(), PMW); @@ -2336,20 +2406,26 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentFast( // To Allocate wwm registers used in whole quad mode operations (for shaders). addMachineFunctionPass(SIPreAllocateWWMRegsPass(), PMW); - // For allocating other wwm register operands. - addMachineFunctionPass(RegAllocFastPass({onlyAllocateWWMRegs, "wwm", false}), - PMW); + // WWM allocation - default to fast at -O0. + if (WWMRegAllocNPM == RegAllocType::Greedy) + addMachineFunctionPass(RAGreedyPass({onlyAllocateWWMRegs, "wwm"}), PMW); + else + addMachineFunctionPass( + RegAllocFastPass({onlyAllocateWWMRegs, "wwm", false}), PMW); addMachineFunctionPass(SILowerWWMCopiesPass(), PMW); addMachineFunctionPass(AMDGPUReserveWWMRegsPass(), PMW); - // For allocating per-thread VGPRs. - addMachineFunctionPass(RegAllocFastPass({onlyAllocateVGPRs, "vgpr"}), PMW); + // VGPR allocation - default to fast at -O0. + if (VGPRRegAllocNPM == RegAllocType::Greedy) + addMachineFunctionPass(RAGreedyPass({onlyAllocateVGPRs, "vgpr"}), PMW); + else + addMachineFunctionPass(RegAllocFastPass({onlyAllocateVGPRs, "vgpr"}), PMW); return Error::success(); } -void AMDGPUCodeGenPassBuilder::addOptimizedRegAlloc( +Error AMDGPUCodeGenPassBuilder::addOptimizedRegAlloc( PassManagerWrapper &PMW) const { if (EnableDCEInRA) insertPass(DeadMachineInstructionElimPass()); @@ -2385,7 +2461,7 @@ void AMDGPUCodeGenPassBuilder::addOptimizedRegAlloc( if (TM.getOptLevel() > CodeGenOptLevel::Less) insertPass(SIFormMemoryClausesPass()); - Base::addOptimizedRegAlloc(PMW); + return Base::addOptimizedRegAlloc(PMW); } void AMDGPUCodeGenPassBuilder::addPreRegAlloc(PassManagerWrapper &PMW) const { @@ -2395,11 +2471,17 @@ void AMDGPUCodeGenPassBuilder::addPreRegAlloc(PassManagerWrapper &PMW) const { Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized( PassManagerWrapper &PMW) const { - // TODO: Check --regalloc-npm option + if (auto Err = validateRegAllocOptions()) + return Err; addMachineFunctionPass(GCNPreRALongBranchRegPass(), PMW); - addMachineFunctionPass(RAGreedyPass({onlyAllocateSGPRs, "sgpr"}), PMW); + // SGPR allocation - default to greedy at -O1 and above. + if (SGPRRegAllocNPM == RegAllocType::Fast) + addMachineFunctionPass(RegAllocFastPass({onlyAllocateSGPRs, "sgpr", false}), + PMW); + else + addMachineFunctionPass(RAGreedyPass({onlyAllocateSGPRs, "sgpr"}), PMW); // Commit allocated register changes. This is mostly necessary because too // many things rely on the use lists of the physical registers, such as the @@ -2418,14 +2500,21 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized( // To Allocate wwm registers used in whole quad mode operations (for shaders). addMachineFunctionPass(SIPreAllocateWWMRegsPass(), PMW); - // For allocating other wwm register operands. - addMachineFunctionPass(RAGreedyPass({onlyAllocateWWMRegs, "wwm"}), PMW); + // WWM allocation - default to greedy at -O1 and above. + if (WWMRegAllocNPM == RegAllocType::Fast) + addMachineFunctionPass( + RegAllocFastPass({onlyAllocateWWMRegs, "wwm", false}), PMW); + else + addMachineFunctionPass(RAGreedyPass({onlyAllocateWWMRegs, "wwm"}), PMW); addMachineFunctionPass(SILowerWWMCopiesPass(), PMW); addMachineFunctionPass(VirtRegRewriterPass(false), PMW); addMachineFunctionPass(AMDGPUReserveWWMRegsPass(), PMW); - // For allocating per-thread VGPRs. - addMachineFunctionPass(RAGreedyPass({onlyAllocateVGPRs, "vgpr"}), PMW); + // VGPR allocation - default to greedy at -O1 and above. + if (VGPRRegAllocNPM == RegAllocType::Fast) + addMachineFunctionPass(RegAllocFastPass({onlyAllocateVGPRs, "vgpr"}), PMW); + else + addMachineFunctionPass(RAGreedyPass({onlyAllocateVGPRs, "vgpr"}), PMW); addPreRewrite(PMW); addMachineFunctionPass(VirtRegRewriterPass(true), PMW); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index 3e02587f61336..4f07aaef909e4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -80,7 +80,8 @@ static cl::opt InlineMaxBB( static cl::opt MemcpyLoopUnroll( "amdgpu-memcpy-loop-unroll", cl::desc("Unroll factor (affecting 4x32-bit operations) to use for memory " - "operations when lowering memcpy as a loop"), + "operations when lowering statically-sized memcpy, memmove, or" + "memset as a loop"), cl::init(16), cl::Hidden); static bool dependsOnLocalPhi(const Loop *L, const Value *Cond, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUniformIntrinsicCombine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUUniformIntrinsicCombine.cpp index 47d56adf18b7c..864d877fe9ac0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUUniformIntrinsicCombine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUUniformIntrinsicCombine.cpp @@ -165,10 +165,7 @@ namespace { class AMDGPUUniformIntrinsicCombineLegacy : public FunctionPass { public: static char ID; - AMDGPUUniformIntrinsicCombineLegacy() : FunctionPass(ID) { - initializeAMDGPUUniformIntrinsicCombineLegacyPass( - *PassRegistry::getPassRegistry()); - } + AMDGPUUniformIntrinsicCombineLegacy() : FunctionPass(ID) {} private: bool runOnFunction(Function &F) override; diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 02abad3eb45a8..7729d27c6311b 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -143,10 +143,13 @@ class AMDGPUOperand : public MCParsedAsmOperand { ImmTyExpTgt, ImmTyExpCompr, ImmTyExpVM, + ImmTyDone, + ImmTyRowEn, ImmTyFORMAT, ImmTyHwreg, ImmTyOff, ImmTySendMsg, + ImmTyWaitEvent, ImmTyInterpSlot, ImmTyInterpAttr, ImmTyInterpAttrChan, @@ -413,6 +416,8 @@ class AMDGPUOperand : public MCParsedAsmOperand { bool isNegLo() const { return isImmTy(ImmTyNegLo); } bool isNegHi() const { return isImmTy(ImmTyNegHi); } bool isBitOp3() const { return isImmTy(ImmTyBitOp3) && isUInt<8>(getImm()); } + bool isDone() const { return isImmTy(ImmTyDone); } + bool isRowEn() const { return isImmTy(ImmTyRowEn); } bool isRegOrImm() const { return isReg() || isImm(); @@ -963,6 +968,7 @@ class AMDGPUOperand : public MCParsedAsmOperand { bool isSDelayALU() const; bool isHwreg() const; bool isSendMsg() const; + bool isWaitEvent() const; bool isSplitBarrier() const; bool isSwizzle() const; bool isSMRDOffset8() const; @@ -1140,8 +1146,11 @@ class AMDGPUOperand : public MCParsedAsmOperand { case ImmTyExpTgt: OS << "ExpTgt"; break; case ImmTyExpCompr: OS << "ExpCompr"; break; case ImmTyExpVM: OS << "ExpVM"; break; + case ImmTyDone: OS << "Done"; break; + case ImmTyRowEn: OS << "RowEn"; break; case ImmTyHwreg: OS << "Hwreg"; break; case ImmTySendMsg: OS << "SendMsg"; break; + case ImmTyWaitEvent: OS << "WaitEvent"; break; case ImmTyInterpSlot: OS << "InterpSlot"; break; case ImmTyInterpAttr: OS << "InterpAttr"; break; case ImmTyInterpAttrChan: OS << "InterpAttrChan"; break; @@ -1688,7 +1697,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser { ParseStatus parseNamedBit(StringRef Name, OperandVector &Operands, - AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone); + AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone, + bool IgnoreNegative = false); unsigned getCPolKind(StringRef Id, StringRef Mnemo, bool &Disabling) const; ParseStatus parseCPol(OperandVector &Operands); ParseStatus parseScope(OperandVector &Operands, int64_t &Scope); @@ -1776,7 +1786,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser { bool IsSymbolic = false; bool IsDefined = false; - OperandInfoTy(int64_t Val) : Val(Val) {} + constexpr OperandInfoTy(int64_t Val) : Val(Val) {} }; struct StructuredOpField : OperandInfoTy { @@ -1785,8 +1795,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser { unsigned Width; bool IsDefined = false; - StructuredOpField(StringLiteral Id, StringLiteral Desc, unsigned Width, - int64_t Default) + constexpr StructuredOpField(StringLiteral Id, StringLiteral Desc, + unsigned Width, int64_t Default) : OperandInfoTy(Default), Id(Id), Desc(Desc), Width(Width) {} virtual ~StructuredOpField() = default; @@ -1917,6 +1927,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser { ParseStatus parseExpTgt(OperandVector &Operands); ParseStatus parseSendMsg(OperandVector &Operands); + ParseStatus parseWaitEvent(OperandVector &Operands); ParseStatus parseInterpSlot(OperandVector &Operands); ParseStatus parseInterpAttr(OperandVector &Operands); ParseStatus parseSOPPBrTarget(OperandVector &Operands); @@ -5544,12 +5555,9 @@ bool AMDGPUAsmParser::validateWMMA(const MCInst &Inst, if (RegSize == AMDGPU::wmmaScaleF8F6F4FormatToNumRegs(Fmt) * 32) return true; - static const char *FmtNames[] = {"MATRIX_FMT_FP8", "MATRIX_FMT_BF8", - "MATRIX_FMT_FP6", "MATRIX_FMT_BF6", - "MATRIX_FMT_FP4"}; - Error(getOperandLoc(Operands, SrcIdx), - "wrong register tuple size for " + Twine(FmtNames[Fmt])); + "wrong register tuple size for " + + Twine(WMMAMods::ModMatrixFmt[Fmt])); return false; }; @@ -7046,13 +7054,16 @@ ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix( ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name, OperandVector &Operands, - AMDGPUOperand::ImmTy ImmTy) { + AMDGPUOperand::ImmTy ImmTy, + bool IgnoreNegative) { int64_t Bit; SMLoc S = getLoc(); if (trySkipId(Name)) { Bit = 1; } else if (trySkipId("no", Name)) { + if (IgnoreNegative) + return ParseStatus::Success; Bit = 0; } else { return ParseStatus::NoMatch; @@ -7409,10 +7420,7 @@ ParseStatus AMDGPUAsmParser::parseIndexKey32bit(OperandVector &Operands) { ParseStatus AMDGPUAsmParser::tryParseMatrixFMT(OperandVector &Operands, StringRef Name, AMDGPUOperand::ImmTy Type) { - return parseStringOrIntWithPrefix(Operands, Name, - {"MATRIX_FMT_FP8", "MATRIX_FMT_BF8", - "MATRIX_FMT_FP6", "MATRIX_FMT_BF6", - "MATRIX_FMT_FP4"}, + return parseStringOrIntWithPrefix(Operands, Name, WMMAMods::ModMatrixFmt, Type); } @@ -7429,8 +7437,8 @@ ParseStatus AMDGPUAsmParser::parseMatrixBFMT(OperandVector &Operands) { ParseStatus AMDGPUAsmParser::tryParseMatrixScale(OperandVector &Operands, StringRef Name, AMDGPUOperand::ImmTy Type) { - return parseStringOrIntWithPrefix( - Operands, Name, {"MATRIX_SCALE_ROW0", "MATRIX_SCALE_ROW1"}, Type); + return parseStringOrIntWithPrefix(Operands, Name, WMMAMods::ModMatrixScale, + Type); } ParseStatus AMDGPUAsmParser::parseMatrixAScale(OperandVector &Operands) { @@ -7446,10 +7454,8 @@ ParseStatus AMDGPUAsmParser::parseMatrixBScale(OperandVector &Operands) { ParseStatus AMDGPUAsmParser::tryParseMatrixScaleFmt(OperandVector &Operands, StringRef Name, AMDGPUOperand::ImmTy Type) { - return parseStringOrIntWithPrefix( - Operands, Name, - {"MATRIX_SCALE_FMT_E8", "MATRIX_SCALE_FMT_E5M3", "MATRIX_SCALE_FMT_E4M3"}, - Type); + return parseStringOrIntWithPrefix(Operands, Name, WMMAMods::ModMatrixScaleFmt, + Type); } ParseStatus AMDGPUAsmParser::parseMatrixAScaleFmt(OperandVector &Operands) { @@ -8247,6 +8253,41 @@ bool AMDGPUOperand::isSendMsg() const { return isImmTy(ImmTySendMsg); } +ParseStatus AMDGPUAsmParser::parseWaitEvent(OperandVector &Operands) { + using namespace llvm::AMDGPU::WaitEvent; + + SMLoc Loc = getLoc(); + int64_t ImmVal = 0; + + StructuredOpField DontWaitExportReady("dont_wait_export_ready", "bit value", + 1, 0); + StructuredOpField ExportReady("export_ready", "bit value", 1, 0); + + StructuredOpField *TargetBitfield = + isGFX11() ? &DontWaitExportReady : &ExportReady; + + ParseStatus Res = parseStructuredOpFields({TargetBitfield}); + if (Res.isNoMatch() && parseExpr(ImmVal, "structured immediate")) + Res = ParseStatus::Success; + else if (Res.isSuccess()) { + if (!validateStructuredOpFields({TargetBitfield})) + return ParseStatus::Failure; + ImmVal = TargetBitfield->Val; + } + + if (!Res.isSuccess()) + return ParseStatus::Failure; + + if (!isUInt<16>(ImmVal)) + return Error(Loc, "invalid immediate: only 16-bit values are legal"); + + Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, + AMDGPUOperand::ImmTyWaitEvent)); + return ParseStatus::Success; +} + +bool AMDGPUOperand::isWaitEvent() const { return isImmTy(ImmTyWaitEvent); } + //===----------------------------------------------------------------------===// // v_interp //===----------------------------------------------------------------------===// @@ -9523,6 +9564,8 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands, Opc == AMDGPU::V_CVT_SCALEF32_PK_FP4_BF16_vi || Opc == AMDGPU::V_CVT_SR_BF8_F32_vi || Opc == AMDGPU::V_CVT_SR_FP8_F32_vi || + Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx11 || + Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx11 || Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx12 || Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx12) { Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods @@ -9532,7 +9575,19 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands, // Adding vdst_in operand is already covered for these DPP instructions in // cvtVOP3DPP. if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in) && - !(Opc == AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp_gfx12 || + !(Opc == AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp_gfx11 || + Opc == AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp_gfx11 || + Opc == AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx11 || + Opc == AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx11 || + Opc == AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp_gfx11 || + Opc == AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx11 || + Opc == AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx11 || + Opc == AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx11 || + Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx11 || + Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx11 || + Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx11 || + Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx11 || + Opc == AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp_gfx12 || Opc == AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp_gfx12 || Opc == AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx12 || Opc == AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx12 || @@ -10448,7 +10503,7 @@ ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, case MCK_addr64: return parseTokenOp("addr64", Operands); case MCK_done: - return parseTokenOp("done", Operands); + return parseNamedBit("done", Operands, AMDGPUOperand::ImmTyDone, true); case MCK_idxen: return parseTokenOp("idxen", Operands); case MCK_lds: @@ -10458,7 +10513,7 @@ ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, case MCK_off: return parseTokenOp("off", Operands); case MCK_row_95_en: - return parseTokenOp("row_en", Operands); + return parseNamedBit("row_en", Operands, AMDGPUOperand::ImmTyRowEn, true); case MCK_gds: return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS); case MCK_tfe: @@ -10489,6 +10544,10 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op, return Operand.isOffen() ? Match_Success : Match_InvalidOperand; case MCK_tfe: return Operand.isTFE() ? Match_Success : Match_InvalidOperand; + case MCK_done: + return Operand.isDone() ? Match_Success : Match_InvalidOperand; + case MCK_row_95_en: + return Operand.isRowEn() ? Match_Success : Match_InvalidOperand; case MCK_SSrc_b32: // When operands have expression values, they will return true for isToken, // because it is not possible to distinguish between a token and an diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index ca8099736c187..fde67e9e2d83b 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -393,7 +393,7 @@ class MUBUF_Invalidate : let sccb_value = 0; } -class getBUFVDataRegisterOperand { +class getBUFVDataRegisterOperand { defvar tfeVDataOp = !cond(!eq(Size, 16) : AVLdSt_64, !eq(Size, 32) : AVLdSt_64, @@ -402,7 +402,7 @@ class getBUFVDataRegisterOperand { !eq(Size, 128) : AVLdSt_160); defvar VDataOp = - !cond(!eq(Size, 16) : AVLdSt_32, + !cond(!eq(Size, 16) : !if(isTrue16, VGPROp_16, AVLdSt_32), !eq(Size, 32) : AVLdSt_32, !eq(Size, 64) : AVLdSt_64, !eq(Size, 96) : AVLdSt_96, @@ -417,10 +417,10 @@ class getBUFVDataRegisterOperandForOp { } class getMUBUFInsDA vdataList, - list vaddrList, bit isTFE, bit hasRestrictedSOffset> { + list vaddrList, bit isTFE, bit hasRestrictedSOffset, bit isTrue16 = false> { RegisterOperand vdataClass = !if(!empty(vdataList), ?, !head(vdataList)); RegisterClassLike vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList)); - RegisterOperand vdata_op = getBUFVDataRegisterOperand(vdataClass.RegClass).Size, isTFE>.ret; + RegisterOperand vdata_op = getBUFVDataRegisterOperand(vdataClass.RegClass).Size, isTFE, isTrue16>.ret; dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset)); dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz)); @@ -448,13 +448,13 @@ class getMUBUFElements { ); } -class getMUBUFIns vdataList, bit isTFE, bit hasRestrictedSOffset> { +class getMUBUFIns vdataList, bit isTFE, bit hasRestrictedSOffset, bit isTrue16 = false> { dag ret = - !if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA.ret, - !if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA.ret, - !if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA.ret, - !if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA.ret, - !if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA.ret, + !if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA.ret, + !if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA.ret, + !if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA.ret, + !if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA.ret, + !if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA.ret, (ins)))))); } @@ -509,7 +509,7 @@ class MUBUF_Load_Pseudo { + def _OFFSET : MUBUF_Load_Pseudo , + MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>, True16D16Table; + + def _ADDR64 : MUBUF_Load_Pseudo , + MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>, True16D16Table; + + def _OFFEN : MUBUF_Load_Pseudo , + True16D16Table; + def _IDXEN : MUBUF_Load_Pseudo , + True16D16Table; + def _BOTHEN : MUBUF_Load_Pseudo , + True16D16Table; + + let DisableWQM = 1 in { + def _OFFSET_exact : MUBUF_Load_Pseudo , + True16D16Table; + def _OFFEN_exact : MUBUF_Load_Pseudo , + True16D16Table; + def _IDXEN_exact : MUBUF_Load_Pseudo , + True16D16Table; + def _BOTHEN_exact : MUBUF_Load_Pseudo , + True16D16Table; + } +} + multiclass MUBUF_Pseudo_Loads { defm NAME : MUBUF_Pseudo_Loads_Helper; @@ -577,6 +604,23 @@ multiclass MUBUF_Pseudo_Loads { + let True16Predicate = NotUseRealTrue16Insts in { + defm NAME : MUBUF_Pseudo_Loads_Helper; + defm _VBUFFER : MUBUF_Pseudo_Loads_Helper; + } + let True16Predicate = UseRealTrue16Insts in { + defvar NAME16 = opName#"_t16"; + defm _t16 : MUBUF_Pseudo_Loads_Helper_t16; + defm _t16_VBUFFER : MUBUF_Pseudo_Loads_Helper_t16; + } + if !not(isLds) then { + defm _TFE : MUBUF_Pseudo_Loads_Helper; + defm _TFE_VBUFFER : MUBUF_Pseudo_Loads_Helper; + } +} + multiclass MUBUF_Pseudo_Loads_Lds { defm NAME : MUBUF_Pseudo_Loads; @@ -595,10 +639,11 @@ class MUBUF_Store_Pseudo pattern=[]> + list pattern=[], + bit isTrue16 = false> : MUBUF_Pseudo.ret], isTFE, hasRestrictedSOffset>.ret, + getMUBUFIns.ret], isTFE, hasRestrictedSOffset, isTrue16>.ret, getMUBUFAsmOps.ret, pattern>, MUBUF_SetupAddr { @@ -650,6 +695,33 @@ multiclass MUBUF_Pseudo_Stores_Helper { + def _OFFSET : MUBUF_Store_Pseudo , + MUBUFAddr64Table<0, NAME>, True16D16Table; + + def _ADDR64 : MUBUF_Store_Pseudo , + MUBUFAddr64Table<1, NAME>, True16D16Table; + + def _OFFEN : MUBUF_Store_Pseudo , + True16D16Table; + def _IDXEN : MUBUF_Store_Pseudo , + True16D16Table; + def _BOTHEN : MUBUF_Store_Pseudo , + True16D16Table; + + let DisableWQM = 1 in { + def _OFFSET_exact : MUBUF_Store_Pseudo , + True16D16Table; + def _OFFEN_exact : MUBUF_Store_Pseudo , + True16D16Table; + def _IDXEN_exact : MUBUF_Store_Pseudo , + True16D16Table; + def _BOTHEN_exact : MUBUF_Store_Pseudo , + True16D16Table; + } +} + multiclass MUBUF_Pseudo_Stores { defm NAME : MUBUF_Pseudo_Stores_Helper; defm _TFE : MUBUF_Pseudo_Stores_Helper; @@ -658,6 +730,22 @@ multiclass MUBUF_Pseudo_Stores { defm _TFE_VBUFFER : MUBUF_Pseudo_Stores_Helper; } +multiclass MUBUF_Pseudo_Stores_t16 { + defm _TFE : MUBUF_Pseudo_Stores_Helper; + defm _TFE_VBUFFER : MUBUF_Pseudo_Stores_Helper; + + let True16Predicate = NotUseRealTrue16Insts in { + defm NAME : MUBUF_Pseudo_Stores_Helper; + + defm _VBUFFER : MUBUF_Pseudo_Stores_Helper; + } + let True16Predicate = UseRealTrue16Insts, SubtargetPredicate = HasD16LoadStore in { + defvar NAME16 = opName#"_t16"; + defm _t16 : MUBUF_Pseudo_Stores_Helper_t16; + defm _t16_VBUFFER : MUBUF_Pseudo_Stores_Helper_t16; + } +} + class MUBUF_Pseudo_Store_Lds : MUBUF_Pseudo; } // End OtherPredicates = [HasUnpackedD16VMem], D16Buf = 1. + +let TiedSourceNotRead = 1, SubtargetPredicate = HasD16LoadStore, OtherPredicates = [HasFormattedMUBUFInsts] in +defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Pseudo_Loads < + "buffer_load_format_d16_hi_x", i32 +>; + let OtherPredicates = [HasPackedD16VMem], D16Buf = 1 in { let TiedSourceNotRead = 1 in { - defm BUFFER_LOAD_FORMAT_D16_X : MUBUF_Pseudo_Loads < - "buffer_load_format_d16_x", f16 + defm BUFFER_LOAD_FORMAT_D16_X : MUBUF_Pseudo_Loads_t16 < + "buffer_load_format_d16_x", f16, 0, 0, "BUFFER_LOAD_FORMAT_D16_HI_X" >; defm BUFFER_LOAD_FORMAT_D16_XY : MUBUF_Pseudo_Loads < "buffer_load_format_d16_xy", v2f16 @@ -930,9 +1024,6 @@ defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_aext_8_globa defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_zext_8_global>; defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_aext_16_global>; defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_zext_16_global>; -defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_aext_8_global>; -defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_zext_8_global>; -defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i16, atomic_load_nonext_16_global>; defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, extloadi8_global>; defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, zextloadi8_global>; defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_SBYTE", i32, sextloadi8_global>; @@ -959,12 +1050,23 @@ foreach vt = VReg_128.RegTypes in { defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_DWORDX4", vt, load_global>; } -defm BUFFER_STORE_BYTE : MUBUF_Pseudo_Stores < +let SubtargetPredicate = HasD16LoadStore in { +defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Pseudo_Stores < + "buffer_store_byte_d16_hi", i32 +>; + +defm BUFFER_STORE_SHORT_D16_HI : MUBUF_Pseudo_Stores < + "buffer_store_short_d16_hi", i32 +>; +} + +defm BUFFER_STORE_BYTE : MUBUF_Pseudo_Stores_t16 < "buffer_store_byte", i32 >; -defm BUFFER_STORE_SHORT : MUBUF_Pseudo_Stores < +defm BUFFER_STORE_SHORT : MUBUF_Pseudo_Stores_t16 < "buffer_store_short", i32 >; + defm BUFFER_STORE_DWORD : MUBUF_Pseudo_Stores < "buffer_store_dword", i32 >; @@ -1121,43 +1223,30 @@ defm BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_Pseudo_Atomics < let SubtargetPredicate = HasD16LoadStore in { let TiedSourceNotRead = 1 in { -defm BUFFER_LOAD_UBYTE_D16 : MUBUF_Pseudo_Loads < - "buffer_load_ubyte_d16", i32, 1 ->; - defm BUFFER_LOAD_UBYTE_D16_HI : MUBUF_Pseudo_Loads < "buffer_load_ubyte_d16_hi", i32, 1 >; -defm BUFFER_LOAD_SBYTE_D16 : MUBUF_Pseudo_Loads < - "buffer_load_sbyte_d16", i32, 1 ->; - defm BUFFER_LOAD_SBYTE_D16_HI : MUBUF_Pseudo_Loads < "buffer_load_sbyte_d16_hi", i32, 1 >; -defm BUFFER_LOAD_SHORT_D16 : MUBUF_Pseudo_Loads < - "buffer_load_short_d16", i32, 1 ->; - defm BUFFER_LOAD_SHORT_D16_HI : MUBUF_Pseudo_Loads < "buffer_load_short_d16_hi", i32, 1 >; -let OtherPredicates = [HasFormattedMUBUFInsts] in -defm BUFFER_LOAD_FORMAT_D16_HI_X : MUBUF_Pseudo_Loads < - "buffer_load_format_d16_hi_x", i32 +defm BUFFER_LOAD_UBYTE_D16 : MUBUF_Pseudo_Loads_t16 < + "buffer_load_ubyte_d16", i32, 1 >; -} // End TiedSourceNotRead -defm BUFFER_STORE_BYTE_D16_HI : MUBUF_Pseudo_Stores < - "buffer_store_byte_d16_hi", i32 +defm BUFFER_LOAD_SBYTE_D16 : MUBUF_Pseudo_Loads_t16 < + "buffer_load_sbyte_d16", i32, 1 >; -defm BUFFER_STORE_SHORT_D16_HI : MUBUF_Pseudo_Stores < - "buffer_store_short_d16_hi", i32 +defm BUFFER_LOAD_SHORT_D16 : MUBUF_Pseudo_Loads_t16 < + "buffer_load_short_d16", i32, 1 >; +} // End TiedSourceNotRead let OtherPredicates = [HasFormattedMUBUFInsts] in defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Pseudo_Stores < @@ -1166,6 +1255,18 @@ defm BUFFER_STORE_FORMAT_D16_HI_X : MUBUF_Pseudo_Stores < } // End HasD16LoadStore +let True16Predicate = NotUseRealTrue16Insts in { +defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_aext_8_global>; +defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_zext_8_global>; +defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i16, atomic_load_nonext_16_global>; +} + +let True16Predicate = UseRealTrue16Insts in { +defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE_D16_t16", i16, atomic_load_aext_8_global>; +defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE_D16_t16", i16, atomic_load_zext_8_global>; +defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_SHORT_D16_t16", i16, atomic_load_nonext_16_global>; +} + let SubtargetPredicate = isNotGFX940Plus in def BUFFER_WBINVL1 : MUBUF_Invalidate < "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1 @@ -1367,8 +1468,14 @@ let OtherPredicates = [HasUnpackedD16VMem, HasFormattedMUBUFInsts] in { } // End OtherPredicates = [HasUnpackedD16VMem, HasFormattedMUBUFInsts]. let OtherPredicates = [HasPackedD16VMem, HasFormattedMUBUFInsts] in { +let True16Predicate = NotUseRealTrue16Insts in { defm : MUBUF_LoadIntrinsicPat; defm : MUBUF_LoadIntrinsicPat; +} +let True16Predicate = UseRealTrue16Insts in { + defm : MUBUF_LoadIntrinsicPat; + defm : MUBUF_LoadIntrinsicPat; +} defm : MUBUF_LoadIntrinsicPat; defm : MUBUF_LoadIntrinsicPat; defm : MUBUF_LoadIntrinsicPat; @@ -1934,15 +2041,26 @@ multiclass MUBUFLoad_PatternOffset ; defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_UBYTE", i16, extloadi8_constant>; defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_UBYTE", i16, zextloadi8_constant>; defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_SBYTE", i16, sextloadi8_global>; defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_UBYTE", i16, extloadi8_global>; defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_UBYTE", i16, zextloadi8_global>; - defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_USHORT", i16, load_global>; +} + +let True16Predicate = UseRealTrue16Insts in { +defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_SBYTE_D16_t16", i16, sextloadi8_constant>; +defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_UBYTE_D16_t16", i16, extloadi8_constant>; +defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_UBYTE_D16_t16", i16, zextloadi8_constant>; +defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_SBYTE_D16_t16", i16, sextloadi8_global>; +defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_UBYTE_D16_t16", i16, extloadi8_global>; +defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_UBYTE_D16_t16", i16, zextloadi8_global>; +defm : MUBUFLoad_PatternOffset <"BUFFER_LOAD_SHORT_D16_t16", i16, load_global>; +} + } // End OtherPredicates = [Has16BitInsts] @@ -1982,6 +2100,19 @@ multiclass MUBUFScratchLoadPat_D16_Common ; } +multiclass MUBUFScratchLoadPat_D16_Common_t16 { + def : GCNPat < + (vt (ld_frag (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, i32:$soffset, i32:$offset))), + (!cast(Instr # _OFFEN) $vaddr, $srsrc, $soffset, $offset) + >; + + def : GCNPat < + (vt (ld_frag (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, i32:$offset))), + (!cast(Instr # _OFFSET) $srsrc, $soffset, $offset) + >; +} + + multiclass MUBUFScratchLoadPat_D16 { let SubtargetPredicate = HasUnrestrictedSOffset in { @@ -1990,17 +2121,35 @@ multiclass MUBUFScratchLoadPat_D16 ; } +multiclass MUBUFScratchLoadPat_D16_t16 { + let SubtargetPredicate = HasUnrestrictedSOffset in { + defm : MUBUFScratchLoadPat_D16_Common_t16; + } + defm : MUBUFScratchLoadPat_D16_Common_t16; +} + let OtherPredicates = [NotHasFlatScratchEnabled] in { defm : MUBUFScratchLoadPat <"BUFFER_LOAD_SBYTE", i32, sextloadi8_private>; defm : MUBUFScratchLoadPat <"BUFFER_LOAD_UBYTE", i32, extloadi8_private>; defm : MUBUFScratchLoadPat <"BUFFER_LOAD_UBYTE", i32, zextloadi8_private>; -defm : MUBUFScratchLoadPat <"BUFFER_LOAD_SBYTE", i16, sextloadi8_private>; -defm : MUBUFScratchLoadPat <"BUFFER_LOAD_UBYTE", i16, extloadi8_private>; -defm : MUBUFScratchLoadPat <"BUFFER_LOAD_UBYTE", i16, zextloadi8_private>; defm : MUBUFScratchLoadPat <"BUFFER_LOAD_SSHORT", i32, sextloadi16_private>; defm : MUBUFScratchLoadPat <"BUFFER_LOAD_USHORT", i32, extloadi16_private>; defm : MUBUFScratchLoadPat <"BUFFER_LOAD_USHORT", i32, zextloadi16_private>; + +let True16Predicate = NotUseRealTrue16Insts in { +defm : MUBUFScratchLoadPat <"BUFFER_LOAD_SBYTE", i16, sextloadi8_private>; +defm : MUBUFScratchLoadPat <"BUFFER_LOAD_UBYTE", i16, extloadi8_private>; +defm : MUBUFScratchLoadPat <"BUFFER_LOAD_UBYTE", i16, zextloadi8_private>; defm : MUBUFScratchLoadPat <"BUFFER_LOAD_USHORT", i16, load_private>; +} + +let True16Predicate = UseRealTrue16Insts in { +defm : MUBUFScratchLoadPat_D16_t16 <"BUFFER_LOAD_SBYTE_D16_t16", i16, sextloadi8_private>; +defm : MUBUFScratchLoadPat_D16_t16 <"BUFFER_LOAD_UBYTE_D16_t16", i16, extloadi8_private>; +defm : MUBUFScratchLoadPat_D16_t16 <"BUFFER_LOAD_UBYTE_D16_t16", i16, zextloadi8_private>; +defm : MUBUFScratchLoadPat_D16_t16 <"BUFFER_LOAD_SHORT_D16_t16", i16, load_private>; +} foreach vt = Reg32Types.types in { defm : MUBUFScratchLoadPat <"BUFFER_LOAD_DWORD", vt, load_private>; @@ -2066,8 +2215,15 @@ multiclass MUBUFStore_PatternOffset ; } +let True16Predicate = NotUseRealTrue16Insts in { defm : MUBUFStore_PatternOffset <"BUFFER_STORE_BYTE", i16, truncstorei8_global>; defm : MUBUFStore_PatternOffset <"BUFFER_STORE_SHORT", i16, store_global>; +} + +let True16Predicate = UseRealTrue16Insts in { +defm : MUBUFStore_PatternOffset <"BUFFER_STORE_BYTE_t16", i16, truncstorei8_global>; +defm : MUBUFStore_PatternOffset <"BUFFER_STORE_SHORT_t16", i16, store_global>; +} multiclass MUBUFScratchStorePat_Common ; defm : MUBUFScratchStorePat <"BUFFER_STORE_SHORT", i32, truncstorei16_private>; + +let True16Predicate = NotUseRealTrue16Insts in { defm : MUBUFScratchStorePat <"BUFFER_STORE_BYTE", i16, truncstorei8_private>; defm : MUBUFScratchStorePat <"BUFFER_STORE_SHORT", i16, store_private>; +} + +let True16Predicate = UseRealTrue16Insts in { +defm : MUBUFScratchStorePat <"BUFFER_STORE_BYTE_t16", i16, truncstorei8_private, VGPR_16>; +defm : MUBUFScratchStorePat <"BUFFER_STORE_SHORT_t16", i16, store_private, VGPR_16>; +} foreach vt = Reg32Types.types in { defm : MUBUFScratchStorePat <"BUFFER_STORE_DWORD", vt, store_private>; diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt index 782cbfa76e6e9..ae684a58cfd26 100644 --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -59,6 +59,7 @@ add_llvm_target(AMDGPUCodeGen AMDGPUFrameLowering.cpp AMDGPUGlobalISelDivergenceLowering.cpp AMDGPUGlobalISelUtils.cpp + AMDGPUHazardLatency.cpp AMDGPUHSAMetadataStreamer.cpp AMDGPUInsertDelayAlu.cpp AMDGPUInstCombineIntrinsic.cpp diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 36d54309181ae..feecd5825ac74 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -398,7 +398,7 @@ class FLAT_Global_Load_LDS_Pseudo { - let LGKM_CNT = !not(IsAsync); + let LGKM_CNT = 0; let VM_CNT = !not(IsAsync); let ASYNC_CNT = IsAsync; let is_flat_global = 1; @@ -2389,13 +2389,13 @@ let WaveSizePredicate = isWave32, OtherPredicates = [HasTransposeLoadF4F6Insts] } let OtherPredicates = [isGFX125xOnly] in { - def : FlatLoadPat_CPOL ; - def : FlatLoadPat_CPOL ; - def : FlatLoadPat_CPOL ; + def : FlatLoadPat ; + def : FlatLoadPat ; + def : FlatLoadPat ; - defm : GlobalFLATLoadPats_CPOL ; - defm : GlobalFLATLoadPats_CPOL ; - defm : GlobalFLATLoadPats_CPOL ; + defm : GlobalFLATLoadPats ; + defm : GlobalFLATLoadPats ; + defm : GlobalFLATLoadPats ; } // End SubtargetPredicate = isGFX125xOnly let OtherPredicates = [isGFX1250Plus] in { diff --git a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp index f253a841f16a6..dff153cebdd4c 100644 --- a/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -381,10 +381,14 @@ void GCNIterativeScheduler::scheduleRegion(Region &R, Range &&Schedule, auto Top = R.Begin; for (const auto &I : Schedule) { auto MI = getMachineInstr(I); - if (MI != &*Top) { + + MachineBasicBlock::iterator MII = MI->getIterator(); + if (MII != Top) { + bool NonDebugReordered = + !MI->isDebugInstr() && skipDebugInstructionsForward(Top, MII) != MII; BB->remove(MI); BB->insert(Top, MI); - if (!MI->isDebugInstr()) + if (NonDebugReordered) LIS->handleMove(*MI, true); } if (!MI->isDebugInstr()) { diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp index 1682abbdea169..5529808e632cf 100644 --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp @@ -81,9 +81,7 @@ class GCNNSAReassignLegacy : public MachineFunctionPass { public: static char ID; - GCNNSAReassignLegacy() : MachineFunctionPass(ID) { - initializeGCNNSAReassignLegacyPass(*PassRegistry::getPassRegistry()); - } + GCNNSAReassignLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp index 355bbeb2ffeba..5e9ac56c32a60 100644 --- a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp +++ b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp @@ -57,9 +57,7 @@ class GCNPreRALongBranchReg { class GCNPreRALongBranchRegLegacy : public MachineFunctionPass { public: static char ID; - GCNPreRALongBranchRegLegacy() : MachineFunctionPass(ID) { - initializeGCNPreRALongBranchRegLegacyPass(*PassRegistry::getPassRegistry()); - } + GCNPreRALongBranchRegLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override { return GCNPreRALongBranchReg().run(MF); diff --git a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp index 27c122ca54ffe..cd56887fd46a8 100644 --- a/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp +++ b/llvm/lib/Target/AMDGPU/GCNPreRAOptimizations.cpp @@ -63,9 +63,7 @@ class GCNPreRAOptimizationsLegacy : public MachineFunctionPass { public: static char ID; - GCNPreRAOptimizationsLegacy() : MachineFunctionPass(ID) { - initializeGCNPreRAOptimizationsLegacyPass(*PassRegistry::getPassRegistry()); - } + GCNPreRAOptimizationsLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/GCNProcessors.td b/llvm/lib/Target/AMDGPU/GCNProcessors.td index 56cb6287d6ef5..9949208fa8c90 100644 --- a/llvm/lib/Target/AMDGPU/GCNProcessors.td +++ b/llvm/lib/Target/AMDGPU/GCNProcessors.td @@ -304,6 +304,10 @@ def : ProcessorModel<"gfx1153", GFX11SpeedModel, FeatureISAVersion11_5_3.Features >; +def : ProcessorModel<"gfx1170", GFX11SpeedModel, + FeatureISAVersion11_7_0.Features +>; + // [gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, gfx1151, gfx1152, gfx1153] def : ProcessorModel<"gfx11-generic", GFX11SpeedModel, FeatureISAVersion11_Generic.Features diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp index 4994ce413c2a1..92c09b12c1230 100644 --- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -28,12 +28,19 @@ #include "GCNRegPressure.h" #include "SIMachineFunctionInfo.h" #include "Utils/AMDGPUBaseInfo.h" +#include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/CalcSpillWeights.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineBlockFrequencyInfo.h" +#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" #include "llvm/CodeGen/MachineCycleAnalysis.h" #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/RegisterClassInfo.h" #include "llvm/MC/LaneBitmask.h" +#include "llvm/MC/MCInstrItineraries.h" +#include "llvm/MC/MCSchedule.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" #define DEBUG_TYPE "machine-scheduler" @@ -979,6 +986,8 @@ void GCNScheduleDAGMILive::schedule() { GCNRegPressure GCNScheduleDAGMILive::getRealRegPressure(unsigned RegionIdx) const { + if (Regions[RegionIdx].first == Regions[RegionIdx].second) + return llvm::getRegPressure(MRI, LiveIns[RegionIdx]); GCNDownwardRPTracker RPTracker(*LIS); RPTracker.advance(Regions[RegionIdx].first, Regions[RegionIdx].second, &LiveIns[RegionIdx]); @@ -1387,33 +1396,222 @@ bool ClusteredLowOccStage::initGCNSchedStage() { #define REMAT_PREFIX "[PreRARemat] " #define REMAT_DEBUG(X) LLVM_DEBUG(dbgs() << REMAT_PREFIX; X;) +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +Printable PreRARematStage::ScoredRemat::print() const { + return Printable([&](raw_ostream &OS) { + OS << '(' << MaxFreq << ", " << FreqDiff << ", " << RegionImpact << ')'; + }); +} +#endif + bool PreRARematStage::initGCNSchedStage() { // FIXME: This pass will invalidate cached BBLiveInMap and MBBLiveIns for // regions inbetween the defs and region we sinked the def to. Will need to be // fixed if there is another pass after this pass. assert(!S.hasNextStage()); - if (!GCNSchedStage::initGCNSchedStage() || DAG.Regions.size() == 1) + if (!GCNSchedStage::initGCNSchedStage() || DAG.Regions.size() <= 1) return false; + // Maps all MIs (except lone terminators, which are not part of any region) to + // their parent region. Non-lone terminators are considered part of the region + // they delimitate. + DenseMap MIRegion(MF.getInstructionCount()); + // Before performing any IR modification record the parent region of each MI // and the parent MBB of each region. const unsigned NumRegions = DAG.Regions.size(); - RegionBB.reserve(NumRegions); for (unsigned I = 0; I < NumRegions; ++I) { RegionBoundaries Region = DAG.Regions[I]; for (auto MI = Region.first; MI != Region.second; ++MI) MIRegion.insert({&*MI, I}); - RegionBB.push_back(Region.first->getParent()); + MachineBasicBlock *ParentMBB = Region.first->getParent(); + if (Region.second != ParentMBB->end()) + MIRegion.insert({&*Region.second, I}); + RegionBB.push_back(ParentMBB); } - if (!canIncreaseOccupancyOrReduceSpill()) +#ifndef NDEBUG + auto PrintTargetRegions = [&]() -> void { + if (TargetRegions.none()) { + dbgs() << REMAT_PREFIX << "No target regions\n"; + return; + } + dbgs() << REMAT_PREFIX << "Target regions:\n"; + for (unsigned I : TargetRegions.set_bits()) + dbgs() << REMAT_PREFIX << " [" << I << "] " << RPTargets[I] << '\n'; + }; + auto PrintRematReg = [&](const RematReg &Remat) -> Printable { + return Printable([&, Remat](raw_ostream &OS) { + // Concatenate all region numbers in which the register is unused and + // live-through. + bool HasLiveThroughRegion = false; + OS << '[' << Remat.DefRegion << " -"; + for (unsigned I = 0; I < NumRegions; ++I) { + if (Remat.isUnusedLiveThrough(I)) { + if (HasLiveThroughRegion) { + OS << ','; + } else { + OS << "- "; + HasLiveThroughRegion = true; + } + OS << I; + } + } + if (HasLiveThroughRegion) + OS << " -"; + OS << "-> " << Remat.UseRegion << "] "; + Remat.DefMI->print(OS, /*IsStandalone=*/true, /*SkipOpers=*/false, + /*SkipDebugLoc=*/false, /*AddNewLine=*/false); + }); + }; +#endif + + // Set an objective for the stage based on current RP in each region. + REMAT_DEBUG({ + dbgs() << "Analyzing "; + MF.getFunction().printAsOperand(dbgs(), false); + dbgs() << ": "; + }); + if (!setObjective()) { + LLVM_DEBUG(dbgs() << "no objective to achieve, occupancy is maximal at " + << MFI.getMaxWavesPerEU() << '\n'); return false; + } + LLVM_DEBUG({ + if (TargetOcc) { + dbgs() << "increase occupancy from " << *TargetOcc - 1 << '\n'; + } else { + dbgs() << "reduce spilling (minimum target occupancy is " + << MFI.getMinWavesPerEU() << ")\n"; + } + PrintTargetRegions(); + }); + + if (!collectRematRegs(MIRegion)) { + REMAT_DEBUG(dbgs() << "No rematerializable registers\n"); + return false; + } + const ScoredRemat::FreqInfo FreqInfo(MF, DAG); + REMAT_DEBUG({ + dbgs() << "Rematerializable registers:\n"; + for (const RematReg &Remat : RematRegs) + dbgs() << REMAT_PREFIX << " " << PrintRematReg(Remat) << '\n'; + dbgs() << REMAT_PREFIX << "Region frequencies\n"; + for (auto [I, Freq] : enumerate(FreqInfo.Regions)) { + dbgs() << REMAT_PREFIX << " [" << I << "] "; + if (Freq) + dbgs() << Freq; + else + dbgs() << "unknown "; + dbgs() << " | " << *DAG.Regions[I].first; + } + }); + + SmallVector ScoredRemats; + for (RematReg &Remat : RematRegs) + ScoredRemats.emplace_back(&Remat, FreqInfo, DAG); + +// Rematerialize registers in successive rounds until all RP targets are +// satisifed or until we run out of rematerialization candidates. +#ifndef NDEBUG + unsigned RoundNum = 0; +#endif + BitVector RecomputeRP(NumRegions); + do { + assert(!ScoredRemats.empty() && "no more remat candidates"); + + // (Re-)Score and (re-)sort all remats in increasing score order. + for (ScoredRemat &Remat : ScoredRemats) + Remat.update(TargetRegions, RPTargets, FreqInfo, !TargetOcc); + sort(ScoredRemats); + + REMAT_DEBUG({ + dbgs() << "==== ROUND " << RoundNum++ << " ====\n" + << REMAT_PREFIX + << "Candidates with non-null score, in rematerialization order:\n"; + for (const ScoredRemat &RematDecision : reverse(ScoredRemats)) { + if (RematDecision.hasNullScore()) + break; + dbgs() << REMAT_PREFIX << " " << RematDecision.print() << " | " + << *RematDecision.Remat->DefMI; + } + PrintTargetRegions(); + }); + + RecomputeRP.reset(); + unsigned RematIdx = ScoredRemats.size(); + + // Rematerialize registers in decreasing score order until we estimate + // that all RP targets are satisfied or until rematerialization candidates + // are no longer useful to decrease RP. + for (; RematIdx && TargetRegions.any(); --RematIdx) { + const ScoredRemat &Candidate = ScoredRemats[RematIdx - 1]; + // Stop rematerializing on encountering a null score. Since scores + // monotonically decrease as we rematerialize, we know there is nothing + // useful left to do in such cases, even if we were to re-score. + if (Candidate.hasNullScore()) { + RematIdx = 0; + break; + } + + RematReg &Remat = *Candidate.Remat; + // When previous rematerializations in this round have already satisfied + // RP targets in all regions this rematerialization can impact, we have a + // good indication that our scores have diverged significantly from + // reality, in which case we interrupt this round and re-score. This also + // ensures that every rematerialization we perform is possibly impactful + // in at least one target region. + if (!Remat.maybeBeneficial(TargetRegions, RPTargets)) + break; + + REMAT_DEBUG(dbgs() << "** REMAT " << PrintRematReg(Remat) << '\n';); + // Every rematerialization we do here is likely to move the instruction + // into a higher frequency region, increasing the total sum latency of the + // instruction itself. This is acceptable if we are eliminating a spill in + // the process, but when the goal is increasing occupancy we get nothing + // out of rematerialization if occupancy is not increased in the end; in + // such cases we want to roll back the rematerialization. + RollbackInfo *Rollback = + TargetOcc ? &Rollbacks.emplace_back(&Remat) : nullptr; + rematerialize(Remat, RecomputeRP, Rollback); + unsetSatisifedRPTargets(Remat.Live); + } + + REMAT_DEBUG({ + if (!TargetRegions.any()) { + dbgs() << "** Interrupt round on all targets achieved\n"; + } else if (RematIdx) { + dbgs() << "** Interrupt round on stale score for " + << *ScoredRemats[RematIdx - 1].Remat->DefMI; + } else { + dbgs() << "** Stop on exhausted rematerialization candidates\n"; + } + }); + + // Peel off registers we already rematerialized from the vector's tail. + ScoredRemats.truncate(RematIdx); + } while ((updateAndVerifyRPTargets(RecomputeRP) || TargetRegions.any()) && + !ScoredRemats.empty()); + if (RescheduleRegions.none()) + return false; + + // Commit all pressure changes to the DAG and compute minimum achieved + // occupancy in impacted regions. + REMAT_DEBUG(dbgs() << "==== REMAT RESULTS ====\n"); + unsigned DynamicVGPRBlockSize = MFI.getDynamicVGPRBlockSize(); + for (unsigned I : RescheduleRegions.set_bits()) { + DAG.Pressure[I] = RPTargets[I].getCurrentRP(); + REMAT_DEBUG(dbgs() << '[' << I << "] Achieved occupancy " + << DAG.Pressure[I].getOccupancy(ST, DynamicVGPRBlockSize) + << " (" << RPTargets[I] << ")\n"); + } + AchievedOcc = MFI.getMaxWavesPerEU(); + for (const GCNRegPressure &RP : DAG.Pressure) { + AchievedOcc = + std::min(AchievedOcc, RP.getOccupancy(ST, DynamicVGPRBlockSize)); + } - // Rematerialize identified instructions and update scheduler's state. - rematerialize(); - if (GCNTrackers) - DAG.RegionLiveOuts.buildLiveRegMap(); REMAT_DEBUG({ dbgs() << "Retrying function scheduling with new min. occupancy of " << AchievedOcc << " from rematerializing (original was " @@ -1452,6 +1650,10 @@ void UnclusteredHighRPStage::finalizeGCNSchedStage() { } bool GCNSchedStage::initGCNRegion() { + // Skip empty scheduling region. + if (DAG.begin() == DAG.end()) + return false; + // Check whether this new region is also a new block. if (DAG.RegionBegin->getParent() != CurrentMBB) setupNewBlock(); @@ -1459,8 +1661,8 @@ bool GCNSchedStage::initGCNRegion() { unsigned NumRegionInstrs = std::distance(DAG.begin(), DAG.end()); DAG.enterRegion(CurrentMBB, DAG.begin(), DAG.end(), NumRegionInstrs); - // Skip empty scheduling regions (0 or 1 schedulable instructions). - if (DAG.begin() == DAG.end() || DAG.begin() == std::prev(DAG.end())) + // Skip regions with 1 schedulable instruction. + if (DAG.begin() == std::prev(DAG.end())) return false; LLVM_DEBUG(dbgs() << "********** MI Scheduling **********\n"); @@ -2502,37 +2704,21 @@ unsigned PreRARematStage::getStageTargetOccupancy() const { return TargetOcc ? *TargetOcc : MFI.getMinWavesPerEU(); } -bool PreRARematStage::canIncreaseOccupancyOrReduceSpill() { +bool PreRARematStage::setObjective() { const Function &F = MF.getFunction(); - // Maps optimizable regions (i.e., regions at minimum and register-limited - // occupancy, or regions with spilling) to the target RP we would like to - // reach. - DenseMap OptRegions; + // Set up "spilling targets" for all regions. unsigned MaxSGPRs = ST.getMaxNumSGPRs(F); unsigned MaxVGPRs = ST.getMaxNumVGPRs(F); - bool HasVectorRegisterExcess; - - auto ResetTargetRegions = [&]() { - OptRegions.clear(); - HasVectorRegisterExcess = false; - for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) { - const GCNRegPressure &RP = DAG.Pressure[I]; - GCNRPTarget Target(MaxSGPRs, MaxVGPRs, MF, RP); - if (!Target.satisfied()) - OptRegions.insert({I, Target}); - // We are willing to consider a RP that does not satisfy the target - // as long as it doesn't result in spilling to memory. We - // tolerate SGPR spills to VGPR since these have a lower impact on the - // performance. - // VGPR/AGPR excess could be aliviated by copying to an AGPR/VGPR. - // Currently, we consider any spilling as bad (we should consider this - // case in the future). - HasVectorRegisterExcess |= Target.hasVectorRegisterExcess(); - } - }; + bool HasVectorRegisterExcess = false; + for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) { + const GCNRegPressure &RP = DAG.Pressure[I]; + GCNRPTarget &Target = RPTargets.emplace_back(MaxSGPRs, MaxVGPRs, MF, RP); + if (!Target.satisfied()) + TargetRegions.set(I); + HasVectorRegisterExcess |= Target.hasVectorRegisterExcess(); + } - ResetTargetRegions(); if (HasVectorRegisterExcess || DAG.MinOccupancy >= MFI.getMaxWavesPerEU()) { // In addition to register usage being above addressable limits, occupancy // below the minimum is considered like "spilling" as well. @@ -2541,94 +2727,68 @@ bool PreRARematStage::canIncreaseOccupancyOrReduceSpill() { // There is no spilling and room to improve occupancy; set up "increased // occupancy targets" for all regions. TargetOcc = DAG.MinOccupancy + 1; - unsigned VGPRBlockSize = - MF.getInfo()->getDynamicVGPRBlockSize(); + const unsigned VGPRBlockSize = MFI.getDynamicVGPRBlockSize(); MaxSGPRs = ST.getMaxNumSGPRs(*TargetOcc, false); MaxVGPRs = ST.getMaxNumVGPRs(*TargetOcc, VGPRBlockSize); - ResetTargetRegions(); - } - REMAT_DEBUG({ - dbgs() << "Analyzing "; - MF.getFunction().printAsOperand(dbgs(), false); - dbgs() << ": "; - if (OptRegions.empty()) { - dbgs() << "no objective to achieve, occupancy is maximal at " - << MFI.getMaxWavesPerEU(); - } else if (!TargetOcc) { - dbgs() << "reduce spilling (minimum target occupancy is " - << MFI.getMinWavesPerEU() << ')'; - } else { - dbgs() << "increase occupancy from " << DAG.MinOccupancy << " to " - << TargetOcc; - } - dbgs() << '\n'; - for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) { - if (auto OptIt = OptRegions.find(I); OptIt != OptRegions.end()) { - dbgs() << REMAT_PREFIX << " [" << I << "] " << OptIt->getSecond() - << '\n'; - } + for (auto [I, Target] : enumerate(RPTargets)) { + Target.setTarget(MaxSGPRs, MaxVGPRs); + if (!Target.satisfied()) + TargetRegions.set(I); } - }); - if (OptRegions.empty()) - return false; + } - // Accounts for a reduction in RP in an optimizable region. Returns whether we - // estimate that we have identified enough rematerialization opportunities to - // achieve our goal, and sets Progress to true when this particular reduction - // in pressure was helpful toward that goal. - auto ReduceRPInRegion = [&](auto OptIt, Register Reg, LaneBitmask Mask, - bool &Progress) -> bool { - GCNRPTarget &Target = OptIt->getSecond(); - if (!Target.isSaveBeneficial(Reg)) - return false; - Progress = true; - Target.saveReg(Reg, Mask, DAG.MRI); - if (Target.satisfied()) - OptRegions.erase(OptIt->getFirst()); - return OptRegions.empty(); - }; + return TargetRegions.any(); +} +bool PreRARematStage::collectRematRegs( + const DenseMap &MIRegion) { // We need up-to-date live-out info. to query live-out register masks in // regions containing rematerializable instructions. DAG.RegionLiveOuts.buildLiveRegMap(); - // Cache set of registers that are going to be rematerialized. - DenseSet RematRegs; + // Set of registers already marked for potential remterialization; used to + // avoid rematerialization chains. + SmallSet MarkedRegs; + auto IsMarkedForRemat = [&MarkedRegs](const MachineOperand &MO) -> bool { + return MO.isReg() && MarkedRegs.contains(MO.getReg()); + }; // Identify rematerializable instructions in the function. for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) { - auto Region = DAG.Regions[I]; - for (auto MI = Region.first; MI != Region.second; ++MI) { + RegionBoundaries Bounds = DAG.Regions[I]; + for (auto MI = Bounds.first; MI != Bounds.second; ++MI) { // The instruction must be rematerializable. MachineInstr &DefMI = *MI; if (!isReMaterializable(DefMI)) continue; - // We only support rematerializing virtual registers with one definition. + // We only support rematerializing virtual registers with one + // definition. Register Reg = DefMI.getOperand(0).getReg(); if (!Reg.isVirtual() || !DAG.MRI.hasOneDef(Reg)) continue; // We only care to rematerialize the instruction if it has a single - // non-debug user in a different region. The using MI may not belong to a - // region if it is a lone region terminator. + // non-debug user in a different region. + // FIXME: Allow rematerializations with multiple uses. This should be + // relatively easy to support using the current cost model. MachineInstr *UseMI = DAG.MRI.getOneNonDBGUser(Reg); if (!UseMI) continue; auto UseRegion = MIRegion.find(UseMI); - if (UseRegion != MIRegion.end() && UseRegion->second == I) + if (UseRegion == MIRegion.end() || UseRegion->second == I) continue; // Do not rematerialize an instruction if it uses or is used by an // instruction that we have designated for rematerialization. // FIXME: Allow for rematerialization chains: this requires 1. updating - // remat points to account for uses that are rematerialized, and 2. either - // rematerializing the candidates in careful ordering, or deferring the - // MBB RP walk until the entire chain has been rematerialized. - if (Rematerializations.contains(UseMI) || - llvm::any_of(DefMI.operands(), [&RematRegs](MachineOperand &MO) { - return MO.isReg() && RematRegs.contains(MO.getReg()); - })) + // remat points to account for uses that are rematerialized, and 2. + // either rematerializing the candidates in careful ordering, or + // deferring the MBB RP walk until the entire chain has been + // rematerialized. + const MachineOperand &UseMO = UseMI->getOperand(0); + if (IsMarkedForRemat(UseMO) || + llvm::any_of(DefMI.operands(), IsMarkedForRemat)) continue; // Do not rematerialize an instruction it it uses registers that aren't @@ -2639,188 +2799,283 @@ bool PreRARematStage::canIncreaseOccupancyOrReduceSpill() { *DAG.TII)) continue; - REMAT_DEBUG(dbgs() << "Region " << I << ": remat instruction " << DefMI); - RematInstruction &Remat = - Rematerializations.try_emplace(&DefMI, UseMI).first->second; - - bool RematUseful = false; - if (auto It = OptRegions.find(I); It != OptRegions.end()) { - // Optimistically consider that moving the instruction out of its - // defining region will reduce RP in the latter; this assumes that - // maximum RP in the region is reached somewhere between the defining - // instruction and the end of the region. - REMAT_DEBUG(dbgs() << " Defining region is optimizable\n"); - LaneBitmask Mask = DAG.RegionLiveOuts.getLiveRegsForRegionIdx(I)[Reg]; - if (ReduceRPInRegion(It, Reg, Mask, RematUseful)) - return true; - } - - for (unsigned LIRegion = 0; LIRegion != E; ++LIRegion) { - // We are only collecting regions in which the register is a live-in - // (and may be live-through). - auto It = DAG.LiveIns[LIRegion].find(Reg); - if (It == DAG.LiveIns[LIRegion].end() || It->second.none()) - continue; - Remat.LiveInRegions.insert(LIRegion); - - // Account for the reduction in RP due to the rematerialization in an - // optimizable region in which the defined register is a live-in. This - // is exact for live-through region but optimistic in the using region, - // where RP is actually reduced only if maximum RP is reached somewhere - // between the beginning of the region and the rematerializable - // instruction's use. - if (auto It = OptRegions.find(LIRegion); It != OptRegions.end()) { - REMAT_DEBUG(dbgs() << " Live-in in region " << LIRegion << '\n'); - if (ReduceRPInRegion(It, Reg, DAG.LiveIns[LIRegion][Reg], - RematUseful)) - return true; - } - } - - // If the instruction is not a live-in or live-out in any optimizable - // region then there is no point in rematerializing it. - if (!RematUseful) { - Rematerializations.pop_back(); - REMAT_DEBUG(dbgs() << " No impact, not rematerializing instruction\n"); - } else { - RematRegs.insert(Reg); - } + // Add the instruction to the rematerializable list. + MarkedRegs.insert(Reg); + RematRegs.emplace_back(&DefMI, UseMI, DAG, MIRegion); } } - if (TargetOcc) { - // We were trying to increase occupancy but failed, abort the stage. - REMAT_DEBUG(dbgs() << "Cannot increase occupancy\n"); - Rematerializations.clear(); - return false; + return !RematRegs.empty(); +} + +PreRARematStage::RematReg::RematReg( + MachineInstr *DefMI, MachineInstr *UseMI, GCNScheduleDAGMILive &DAG, + const DenseMap &MIRegion) + : DefMI(DefMI), UseMI(UseMI), LiveIn(DAG.Regions.size()), + LiveOut(DAG.Regions.size()), Live(DAG.Regions.size()), + DefRegion(MIRegion.at(DefMI)), UseRegion(MIRegion.at(UseMI)) { + + // Mark regions in which the rematerializable register is live. + Register Reg = getReg(); + for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) { + auto LiveInIt = DAG.LiveIns[I].find(Reg); + if (LiveInIt != DAG.LiveIns[I].end()) + LiveIn.set(I); + const auto &LiveOuts = DAG.RegionLiveOuts.getLiveRegsForRegionIdx(I); + if (auto LiveOutIt = LiveOuts.find(Reg); LiveOutIt != LiveOuts.end()) + LiveOut.set(I); + } + Live |= LiveIn; + Live |= LiveOut; + Mask = DAG.RegionLiveOuts.getLiveRegsForRegionIdx(DefRegion).at(Reg); +} + +bool PreRARematStage::RematReg::maybeBeneficial( + const BitVector &TargetRegions, ArrayRef RPTargets) const { + Register Reg = getReg(); + for (unsigned I : TargetRegions.set_bits()) { + if (Live[I] && RPTargets[I].isSaveBeneficial(Reg)) + return true; } - REMAT_DEBUG(dbgs() << "Can reduce but not eliminate spilling\n"); - return !Rematerializations.empty(); + return false; } -void PreRARematStage::rematerialize() { - const SIInstrInfo *TII = MF.getSubtarget().getInstrInfo(); +void PreRARematStage::RematReg::insertMI(unsigned RegionIdx, + MachineInstr *RematMI, + GCNScheduleDAGMILive &DAG) const { + RegionBoundaries &Bounds = DAG.Regions[RegionIdx]; + if (Bounds.first == std::next(MachineBasicBlock::iterator(RematMI))) + Bounds.first = RematMI; + DAG.LIS->InsertMachineInstrInMaps(*RematMI); + DAG.LIS->createAndComputeVirtRegInterval(RematMI->getOperand(0).getReg()); +} + +PreRARematStage::ScoredRemat::FreqInfo::FreqInfo( + MachineFunction &MF, const GCNScheduleDAGMILive &DAG) { + assert(DAG.MLI && "MLI not defined in DAG"); + MachineBranchProbabilityInfo MBPI; + MachineBlockFrequencyInfo MBFI(MF, MBPI, *DAG.MLI); + + const unsigned NumRegions = DAG.Regions.size(); + MinFreq = MBFI.getEntryFreq().getFrequency(); + MaxFreq = 0; + Regions.reserve(NumRegions); + for (unsigned I = 0; I < NumRegions; ++I) { + MachineBasicBlock *MBB = DAG.Regions[I].first->getParent(); + uint64_t BlockFreq = MBFI.getBlockFreq(MBB).getFrequency(); + Regions.push_back(BlockFreq); + if (BlockFreq && BlockFreq < MinFreq) + MinFreq = BlockFreq; + else if (BlockFreq > MaxFreq) + MaxFreq = BlockFreq; + } + if (!MinFreq) + return; + + // Scale everything down if frequencies are high. + if (MinFreq >= ScaleFactor * ScaleFactor) { + for (uint64_t &Freq : Regions) + Freq /= ScaleFactor; + MinFreq /= ScaleFactor; + MaxFreq /= ScaleFactor; + } +} + +PreRARematStage::ScoredRemat::ScoredRemat(RematReg *Remat, const FreqInfo &Freq, + const GCNScheduleDAGMILive &DAG) + : Remat(Remat), NumRegs(getNumRegs(DAG)), FreqDiff(getFreqDiff(Freq)) {} + +unsigned PreRARematStage::ScoredRemat::getNumRegs( + const GCNScheduleDAGMILive &DAG) const { + const TargetRegisterClass &RC = *DAG.MRI.getRegClass(Remat->getReg()); + unsigned RegSize = DAG.TRI->getRegSizeInBits(RC); + if (unsigned SubIdx = Remat->DefMI->getOperand(0).getSubReg()) { + // The following may return -1 (i.e., a large unsigned number) on indices + // that may be used to access subregisters of multiple sizes; in such cases + // fallback on the size derived from the register class. + unsigned SubRegSize = DAG.TRI->getSubRegIdxSize(SubIdx); + if (SubRegSize < RegSize) + RegSize = SubRegSize; + } + return divideCeil(RegSize, 32); +} + +int64_t PreRARematStage::ScoredRemat::getFreqDiff(const FreqInfo &Freq) const { + // Get frequencies of defining and using regions. A rematerialization from the + // least frequent region to the most frequent region will yield the greatest + // latency penalty and therefore should get minimum score. Reciprocally, a + // rematerialization in the other direction should get maximum score. Default + // to values that will yield the worst possible score given known frequencies + // in order to penalize rematerializations from or into regions whose + // frequency is unknown. + int64_t DefOrMin = std::max(Freq.Regions[Remat->DefRegion], Freq.MinFreq); + int64_t UseOrMax = Freq.Regions[Remat->UseRegion]; + if (!UseOrMax) + UseOrMax = Freq.MaxFreq; + return DefOrMin - UseOrMax; +} + +void PreRARematStage::ScoredRemat::update(const BitVector &TargetRegions, + ArrayRef RPTargets, + const FreqInfo &FreqInfo, + bool ReduceSpill) { + MaxFreq = 0; + RegionImpact = 0; + for (unsigned I : TargetRegions.set_bits()) { + if (!Remat->Live[I] || !RPTargets[I].isSaveBeneficial(Remat->getReg())) + continue; + bool UnusedLT = Remat->isUnusedLiveThrough(I); - // Collect regions whose RP changes in unpredictable way; we will have to - // fully recompute their RP after all rematerailizations. - DenseSet RecomputeRP; - - // Rematerialize all instructions. - for (auto &[DefMI, Remat] : Rematerializations) { - MachineBasicBlock::iterator InsertPos(Remat.UseMI); - Register Reg = DefMI->getOperand(0).getReg(); - unsigned DefRegion = MIRegion.at(DefMI); - - // Rematerialize DefMI to its use block. - TII->reMaterialize(*InsertPos->getParent(), InsertPos, Reg, - AMDGPU::NoSubRegister, *DefMI); - Remat.RematMI = &*std::prev(InsertPos); - DAG.LIS->InsertMachineInstrInMaps(*Remat.RematMI); - - // Update region boundaries in regions we sinked from (remove defining MI) - // and to (insert MI rematerialized in use block). Only then we can erase - // the original MI. - DAG.updateRegionBoundaries(DAG.Regions[DefRegion], DefMI, nullptr); - auto UseRegion = MIRegion.find(Remat.UseMI); - if (UseRegion != MIRegion.end()) { - DAG.updateRegionBoundaries(DAG.Regions[UseRegion->second], InsertPos, - Remat.RematMI); + // Regions in which RP is guaranteed to decrease have more weight. + RegionImpact += UnusedLT ? 2 : 1; + + if (ReduceSpill) { + uint64_t Freq = FreqInfo.Regions[I]; + if (!UnusedLT) { + // Apply a frequency penalty in regions in which we are not sure that RP + // will decrease. + Freq /= 2; + } + MaxFreq = std::max(MaxFreq, Freq); } - DAG.LIS->RemoveMachineInstrFromMaps(*DefMI); - DefMI->eraseFromParent(); + } + RegionImpact *= NumRegs; +} - // Collect all regions impacted by the rematerialization and update their - // live-in/RP information. - for (unsigned I : Remat.LiveInRegions) { - ImpactedRegions.insert({I, DAG.Pressure[I]}); - GCNRPTracker::LiveRegSet &RegionLiveIns = DAG.LiveIns[I]; +void PreRARematStage::rematerialize(const RematReg &Remat, + BitVector &RecomputeRP, + RollbackInfo *Rollback) { + const SIInstrInfo *TII = MF.getSubtarget().getInstrInfo(); + MachineInstr &DefMI = *Remat.DefMI; + Register Reg = DefMI.getOperand(0).getReg(); + Register NewReg = DAG.MRI.cloneVirtualRegister(Reg); + + // Rematerialize the register in the region where it is used. + MachineBasicBlock::iterator InsertPos = Remat.UseMI; + TII->reMaterialize(*InsertPos->getParent(), InsertPos, NewReg, 0, DefMI); + MachineInstr *RematMI = &*std::prev(InsertPos); + Remat.UseMI->substituteRegister(Reg, NewReg, 0, *DAG.TRI); + Remat.insertMI(Remat.UseRegion, RematMI, DAG); + if (Rollback) { + Rollback->RematMI = RematMI; + // Make the original MI a debug value so that it does not influence + // scheduling and replace all read registers with a sentinel register to + // prevent operands to appear in use-lists of other MIs during LIS + // updates. Store mappings between operand indices and original registers + // for potential rollback. + DefMI.setDesc(TII->get(TargetOpcode::DBG_VALUE)); + for (auto [Idx, MO] : enumerate(Remat.DefMI->operands())) { + if (MO.isReg() && MO.readsReg()) { + Rollback->RegMap.insert({Idx, MO.getReg()}); + MO.setReg(Register()); + } + } + } else { + // Just delete the original instruction if it cannot be rolled back. + DAG.deleteMI(Remat.DefRegion, &DefMI); + } #ifdef EXPENSIVE_CHECKS - // All uses are known to be available / live at the remat point. Thus, the - // uses should already be live in to the region. - for (MachineOperand &MO : DefMI->operands()) { - if (!MO.isReg() || !MO.getReg() || !MO.readsReg()) - continue; + // All uses are known to be available / live at the remat point. Thus, + // the uses should already be live in to the using region. + for (MachineOperand &MO : DefMI.operands()) { + if (!MO.isReg() || !MO.getReg() || !MO.readsReg()) + continue; - Register UseReg = MO.getReg(); - if (!UseReg.isVirtual()) - continue; + Register UseReg = MO.getReg(); + if (!UseReg.isVirtual()) + continue; - LiveInterval &LI = DAG.LIS->getInterval(UseReg); - LaneBitmask LM = DAG.MRI.getMaxLaneMaskForVReg(MO.getReg()); - if (LI.hasSubRanges() && MO.getSubReg()) - LM = DAG.TRI->getSubRegIndexLaneMask(MO.getSubReg()); - - LaneBitmask LiveInMask = RegionLiveIns.at(UseReg); - LaneBitmask UncoveredLanes = LM & ~(LiveInMask & LM); - // If this register has lanes not covered by the LiveIns, be sure they - // do not map to any subrange. ref: - // machine-scheduler-sink-trivial-remats.mir::omitted_subrange - if (UncoveredLanes.any()) { - assert(LI.hasSubRanges()); - for (LiveInterval::SubRange &SR : LI.subranges()) - assert((SR.LaneMask & UncoveredLanes).none()); - } - } + LiveInterval &LI = DAG.LIS->getInterval(UseReg); + LaneBitmask LM = DAG.MRI.getMaxLaneMaskForVReg(MO.getReg()); + if (LI.hasSubRanges() && MO.getSubReg()) + LM = DAG.TRI->getSubRegIndexLaneMask(MO.getSubReg()); + + LaneBitmask LiveInMask = DAG.LiveIns[Remat.UseRegion].at(UseReg); + LaneBitmask UncoveredLanes = LM & ~(LiveInMask & LM); + // If this register has lanes not covered by the LiveIns, be sure they + // do not map to any subrange. ref: + // machine-scheduler-sink-trivial-remats.mir::omitted_subrange + if (UncoveredLanes.any()) { + assert(LI.hasSubRanges()); + for (LiveInterval::SubRange &SR : LI.subranges()) + assert((SR.LaneMask & UncoveredLanes).none()); + } + } #endif - // The register is no longer a live-in in all regions but the one that - // contains the single use. In live-through regions, maximum register - // pressure decreases predictably so we can directly update it. In the - // using region, maximum RP may or may not decrease, so we will mark it - // for re-computation after all materializations have taken place. - LaneBitmask PrevMask = RegionLiveIns[Reg]; - RegionLiveIns.erase(Reg); - RegMasks.insert({{I, Remat.RematMI->getOperand(0).getReg()}, PrevMask}); - if (Remat.UseMI->getParent() != DAG.Regions[I].first->getParent()) - DAG.Pressure[I].inc(Reg, PrevMask, LaneBitmask::getNone(), DAG.MRI); - else - RecomputeRP.insert(I); + // Remove the register from all regions where it is a live-in or live-out + // and adjust RP targets. The save is guaranteed in regions in which the + // register is live-through and unused but optimistic in all other regions + // where the register is live. + for (unsigned I : Remat.Live.set_bits()) { + RPTargets[I].saveReg(Reg, Remat.Mask, DAG.MRI); + DAG.LiveIns[I].erase(Reg); + DAG.RegionLiveOuts.getLiveRegsForRegionIdx(I).erase(Reg); + if (!Remat.isUnusedLiveThrough(I)) + RecomputeRP.set(I); + } + + RescheduleRegions |= Remat.Live; +} + +void PreRARematStage::rollback(const RollbackInfo &Rollback) const { + const auto &[Remat, RematMI, RegMap] = Rollback; + + // Restore the original defining instruction to its original state. + Remat->DefMI->setDesc(DAG.TII->get(RematMI->getOpcode())); + for (const auto &[MOIdx, Reg] : RegMap) + Remat->DefMI->getOperand(MOIdx).setReg(Reg); + + // Switch back to using the original register and delete the + // rematerialization. + Register Reg = RematMI->getOperand(0).getReg(); + Register OriginalReg = Remat->DefMI->getOperand(0).getReg(); + Remat->UseMI->substituteRegister(Reg, OriginalReg, 0, *DAG.TRI); + REMAT_DEBUG(dbgs() << '[' << Remat->UseRegion + << "] Deleting rematerialization " << *RematMI); + DAG.deleteMI(Remat->UseRegion, RematMI); + + // Re-add the defined register as a live-in/live-out in all regions it used to + // be one in. + std::pair LiveReg(OriginalReg, Remat->Mask); + for (unsigned I : Remat->LiveIn.set_bits()) + DAG.LiveIns[I].insert(LiveReg); + for (unsigned I : Remat->LiveOut.set_bits()) + DAG.RegionLiveOuts.getLiveRegsForRegionIdx(I).insert(LiveReg); +} + +void PreRARematStage::commitRematerializations() const { + REMAT_DEBUG(dbgs() << "Commiting all rematerializations\n"); + for (const RollbackInfo &Rollback : Rollbacks) + DAG.deleteMI(Rollback.Remat->DefRegion, Rollback.Remat->DefMI); +} + +void PreRARematStage::unsetSatisifedRPTargets(const BitVector &Regions) { + for (unsigned I : Regions.set_bits()) { + if (TargetRegions[I] && RPTargets[I].satisfied()) { + REMAT_DEBUG(dbgs() << " [" << I << "] Target reached!\n"); + TargetRegions.reset(I); } - // RP in the region from which the instruction was rematerialized may or may - // not decrease. - ImpactedRegions.insert({DefRegion, DAG.Pressure[DefRegion]}); - RecomputeRP.insert(DefRegion); - - // Recompute live interval to reflect the register's rematerialization. - Register RematReg = Remat.RematMI->getOperand(0).getReg(); - DAG.LIS->removeInterval(RematReg); - DAG.LIS->createAndComputeVirtRegInterval(RematReg); - } - - // All regions impacted by at least one rematerialization must be rescheduled. - // Maximum pressure must also be recomputed for all regions where it changed - // non-predictably and checked against the target occupancy. - unsigned DynamicVGPRBlockSize = - MF.getInfo()->getDynamicVGPRBlockSize(); - AchievedOcc = MFI.getMaxWavesPerEU(); - for (auto &[I, OriginalRP] : ImpactedRegions) { - bool IsEmptyRegion = DAG.Regions[I].first == DAG.Regions[I].second; - RescheduleRegions[I] = !IsEmptyRegion; - if (!RecomputeRP.contains(I)) - continue; + } +} - GCNRegPressure RP; - if (IsEmptyRegion) { - RP = getRegPressure(DAG.MRI, DAG.LiveIns[I]); - } else { - GCNDownwardRPTracker RPT(*DAG.LIS); - auto *NonDbgMI = &*skipDebugInstructionsForward(DAG.Regions[I].first, - DAG.Regions[I].second); - if (NonDbgMI == DAG.Regions[I].second) { - // Region is non-empty but contains only debug instructions. - RP = getRegPressure(DAG.MRI, DAG.LiveIns[I]); - } else { - RPT.reset(*NonDbgMI, &DAG.LiveIns[I]); - RPT.advance(DAG.Regions[I].second); - RP = RPT.moveMaxPressure(); - } +bool PreRARematStage::updateAndVerifyRPTargets(const BitVector &Regions) { + bool TooOptimistic = false; + for (unsigned I : Regions.set_bits()) { + GCNRPTarget &Target = RPTargets[I]; + Target.setRP(DAG.getRealRegPressure(I)); + + // Since we were optimistic in assessing RP decreases in these regions, we + // may need to remark the target as a target region if RP didn't decrease + // as expected. + if (!TargetRegions[I] && !Target.satisfied()) { + REMAT_DEBUG(dbgs() << " [" << I << "] Incorrect RP estimation\n"); + TooOptimistic = true; + TargetRegions.set(I); } - DAG.Pressure[I] = RP; - AchievedOcc = - std::min(AchievedOcc, RP.getOccupancy(ST, DynamicVGPRBlockSize)); } - REMAT_DEBUG(dbgs() << "Achieved occupancy " << AchievedOcc << "\n"); + return TooOptimistic; } // Copied from MachineLICM @@ -2850,8 +3105,10 @@ void PreRARematStage::finalizeGCNSchedStage() { // When increasing occupancy, it is possible that re-scheduling is not able to // achieve the target occupancy in all regions, in which case re-scheduling in // all regions should be reverted. - if (DAG.MinOccupancy >= *TargetOcc) + if (DAG.MinOccupancy >= *TargetOcc) { + commitRematerializations(); return; + } for (const auto &[RegionIdx, OrigMIOrder, MaxPressure] : RegionReverts) { REMAT_DEBUG(dbgs() << "Reverting re-scheduling in region " << RegionIdx << '\n'); @@ -2863,77 +3120,45 @@ void PreRARematStage::finalizeGCNSchedStage() { // just through rematerializations, in which case we revert re-scheduling in // all regions but do not roll back rematerializations. if (AchievedOcc >= *TargetOcc) { + commitRematerializations(); DAG.setTargetOccupancy(AchievedOcc); return; } // Reset the target occupancy to what it was pre-rematerialization. DAG.setTargetOccupancy(*TargetOcc - 1); - REMAT_DEBUG(dbgs() << "Rolling back all rematerializations\n"); - const SIInstrInfo *TII = MF.getSubtarget().getInstrInfo(); - - // Rollback the rematerializations. - for (const auto &[DefMI, Remat] : Rematerializations) { - MachineInstr &RematMI = *Remat.RematMI; - unsigned DefRegion = MIRegion.at(DefMI); - MachineBasicBlock::iterator InsertPos(DAG.Regions[DefRegion].second); - MachineBasicBlock *MBB = RegionBB[DefRegion]; - Register Reg = RematMI.getOperand(0).getReg(); - - // Re-rematerialize MI at the end of its original region. Note that it may - // not be rematerialized exactly in the same position as originally within - // the region, but it should not matter much. - TII->reMaterialize(*MBB, InsertPos, Reg, AMDGPU::NoSubRegister, RematMI); - MachineInstr *NewMI = &*std::prev(InsertPos); - DAG.LIS->InsertMachineInstrInMaps(*NewMI); - - auto UseRegion = MIRegion.find(Remat.UseMI); - if (UseRegion != MIRegion.end()) { - DAG.updateRegionBoundaries(DAG.Regions[UseRegion->second], RematMI, - nullptr); + // Rollback, then recompute pressure in all affected regions. + REMAT_DEBUG(dbgs() << "==== ROLLBACK ====\n"); + BitVector RecomputeRP(DAG.Regions.size()); + DenseSet RecomputeLI; + for (const RollbackInfo &Rollback : Rollbacks) { + rollback(Rollback); + RecomputeRP |= Rollback.Remat->Live; + // Regenerate intervals for all register operands of rematerialized MIs as + // slot indices may have changed slightly from before re-scheduling. + for (MachineOperand &MO : Rollback.Remat->DefMI->operands()) { + if (MO.isReg() && MO.getReg().isVirtual()) + RecomputeLI.insert(MO.getReg()); } - DAG.updateRegionBoundaries(DAG.Regions[DefRegion], InsertPos, NewMI); - - // Erase rematerialized MI. - DAG.LIS->RemoveMachineInstrFromMaps(RematMI); - RematMI.eraseFromParent(); - - // Recompute live interval for the re-rematerialized register + } + for (Register Reg : RecomputeLI) { DAG.LIS->removeInterval(Reg); DAG.LIS->createAndComputeVirtRegInterval(Reg); - - // Re-add the register as a live-in in all regions it used to be one in. - for (unsigned LIRegion : Remat.LiveInRegions) - DAG.LiveIns[LIRegion].insert({Reg, RegMasks.at({LIRegion, Reg})}); } - - // Reset RP in all impacted regions. - for (auto &[I, OriginalRP] : ImpactedRegions) - DAG.Pressure[I] = OriginalRP; + for (unsigned I : RecomputeRP.set_bits()) + DAG.Pressure[I] = DAG.getRealRegPressure(I); GCNSchedStage::finalizeGCNSchedStage(); } -void GCNScheduleDAGMILive::updateRegionBoundaries( - RegionBoundaries &RegionBounds, MachineBasicBlock::iterator MI, - MachineInstr *NewMI) { - assert((!NewMI || NewMI != RegionBounds.second) && - "cannot remove at region end"); - - if (RegionBounds.first == RegionBounds.second) { - assert(NewMI && "cannot remove from an empty region"); - RegionBounds.first = NewMI; - return; - } - - // We only care for modifications at the beginning of a non-empty region since - // the upper region boundary is exclusive. - if (MI != RegionBounds.first) - return; - if (!NewMI) - RegionBounds.first = std::next(MI); // Removal - else - RegionBounds.first = NewMI; // Insertion +void GCNScheduleDAGMILive::deleteMI(unsigned RegionIdx, MachineInstr *MI) { + // It's not possible for the deleted instruction to be upper region boundary + // since we don't delete region terminators. + if (Regions[RegionIdx].first == MI) + Regions[RegionIdx].first = std::next(MachineBasicBlock::iterator(MI)); + LIS->removeInterval(MI->getOperand(0).getReg()); + LIS->RemoveMachineInstrFromMaps(*MI); + MI->eraseFromParent(); } void GCNScheduleDAGMILive::setTargetOccupancy(unsigned TargetOccupancy) { diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h index d934dc90ebd92..ea97e8e74f41b 100644 --- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h +++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.h @@ -202,8 +202,7 @@ class ScheduleMetrics { }; inline raw_ostream &operator<<(raw_ostream &OS, const ScheduleMetrics &Sm) { - dbgs() << "\n Schedule Metric (scaled by " - << ScheduleMetrics::ScaleFactor + dbgs() << "\n Schedule Metric (scaled by " << ScheduleMetrics::ScaleFactor << " ) is: " << Sm.getMetric() << " [ " << Sm.getBubbles() << "/" << Sm.getLength() << " ]\n"; return OS; @@ -305,14 +304,6 @@ class GCNScheduleDAGMILive final : public ScheduleDAGMILive { // Compute and cache live-ins and pressure for all regions in block. void computeBlockPressure(unsigned RegionIdx, const MachineBasicBlock *MBB); - /// If necessary, updates a region's boundaries following insertion ( \p NewMI - /// != nullptr) or removal ( \p NewMI == nullptr) of a \p MI in the region. - /// For an MI removal, this must be called before the MI is actually erased - /// from its parent MBB. - void updateRegionBoundaries(RegionBoundaries &RegionBounds, - MachineBasicBlock::iterator MI, - MachineInstr *NewMI); - /// Makes the scheduler try to achieve an occupancy of \p TargetOccupancy. void setTargetOccupancy(unsigned TargetOccupancy); @@ -320,6 +311,8 @@ class GCNScheduleDAGMILive final : public ScheduleDAGMILive { std::unique_ptr createSchedStage(GCNSchedStageID SchedStageID); + void deleteMI(unsigned RegionIdx, MachineInstr *MI); + public: GCNScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr S); @@ -516,49 +509,184 @@ class ClusteredLowOccStage : public GCNSchedStage { }; /// Attempts to reduce function spilling or, if there is no spilling, to -/// increase function occupancy by one with respect to ArchVGPR usage by sinking -/// rematerializable instructions to their use. When the stage -/// estimates reducing spilling or increasing occupancy is possible, as few -/// instructions as possible are rematerialized to reduce potential negative +/// increase function occupancy by one with respect to register usage by sinking +/// rematerializable instructions to their use. When the stage estimates that +/// reducing spilling or increasing occupancy is possible, it tries to +/// rematerialize as few registers as possible to reduce potential negative /// effects on function latency. +/// +/// The stage only supports rematerializing registers that meet all of the +/// following constraints. +/// 1. The register is virtual and has a single defining instruction. +/// 2. The single defining instruction is either deemed rematerializable by the +/// target-independent logic, or if not, has no non-constant and +/// non-ignorable physical register use. +/// 3 The register has no virtual register use whose live range would be +/// extended by the rematerialization. +/// 4. The register has a single non-debug user in a different region from its +/// defining region. +/// 5. The register is not used by or using another register that is going to be +/// rematerialized. class PreRARematStage : public GCNSchedStage { private: - /// Useful information about a rematerializable instruction. - struct RematInstruction { - /// Single use of the rematerializable instruction's defined register, - /// located in a different block. + /// A rematerializable register. + struct RematReg { + /// Single MI defining the rematerializable register. + MachineInstr *DefMI; + /// Single user of the rematerializable register. MachineInstr *UseMI; - /// Rematerialized version of \p DefMI, set in - /// PreRARematStage::rematerialize. Used for reverting rematerializations. - MachineInstr *RematMI; - /// Set of regions in which the rematerializable instruction's defined - /// register is a live-in. - SmallDenseSet LiveInRegions; + /// Regions in which the register is live-in/live-out/live anywhere. + BitVector LiveIn, LiveOut, Live; + /// The rematerializable register's lane bitmask. + LaneBitmask Mask; + /// Defining and using regions. + unsigned DefRegion, UseRegion; + + RematReg(MachineInstr *DefMI, MachineInstr *UseMI, + GCNScheduleDAGMILive &DAG, + const DenseMap &MIRegion); + + /// Returns the rematerializable register. Do not call after deleting the + /// original defining instruction. + Register getReg() const { return DefMI->getOperand(0).getReg(); } + + /// Determines whether this rematerialization may be beneficial in at least + /// one target region. + bool maybeBeneficial(const BitVector &TargetRegions, + ArrayRef RPTargets) const; + + /// Determines if the register is both unused and live-through in region \p + /// I. This guarantees that rematerializing it will reduce RP in the region. + bool isUnusedLiveThrough(unsigned I) const { + assert(I < Live.size() && "region index out of range"); + return LiveIn[I] && LiveOut[I] && I != UseRegion; + } + + /// Updates internal structures following a MI rematerialization. Part of + /// the stage instead of the DAG because it makes assumptions that are + /// specific to the rematerialization process. + void insertMI(unsigned RegionIdx, MachineInstr *RematMI, + GCNScheduleDAGMILive &DAG) const; + }; + + /// A scored rematerialization candidate. Higher scores indicate more + /// beneficial rematerializations. A null score indicate the rematerialization + /// is not helpful to reduce RP in target regions. + struct ScoredRemat { + /// The rematerializable register under consideration. + RematReg *Remat; + + /// Execution frequency information required by scoring heuristics. + /// Frequencies are scaled down if they are high to avoid overflow/underflow + /// when combining them. + struct FreqInfo { + /// Per-region execution frequencies. 0 when unknown. + SmallVector Regions; + /// Minimum and maximum observed frequencies. + uint64_t MinFreq, MaxFreq; + + FreqInfo(MachineFunction &MF, const GCNScheduleDAGMILive &DAG); + + private: + static const uint64_t ScaleFactor = 1024; + }; + + /// This only initializes state-independent characteristics of \p Remat, not + /// the actual score. + ScoredRemat(RematReg *Remat, const FreqInfo &Freq, + const GCNScheduleDAGMILive &DAG); + + /// Updates the rematerialization's score w.r.t. the current \p RPTargets. + /// \p RegionFreq indicates the frequency of each region + void update(const BitVector &TargetRegions, ArrayRef RPTargets, + const FreqInfo &Freq, bool ReduceSpill); + + /// Returns whether the current score is null, indicating the + /// rematerialization is useless. + bool hasNullScore() const { return !RegionImpact; } + + /// Compare score components of non-null scores pair-wise. A null score is + /// always strictly lesser than another non-null score. + bool operator<(const ScoredRemat &O) const { + if (hasNullScore()) + return !O.hasNullScore(); + if (O.hasNullScore()) + return false; + if (MaxFreq != O.MaxFreq) + return MaxFreq < O.MaxFreq; + if (FreqDiff != O.FreqDiff) + return FreqDiff < O.FreqDiff; + if (RegionImpact != O.RegionImpact) + return RegionImpact < O.RegionImpact; + // Break ties using pointer to rematerializable register. Rematerializable + // registers are collected in instruction order so, within the same + // region, this will prefer registers defined earlier that have longer + // live ranges in their defining region (since the registers we consider + // are always live-out in their defining region). + return Remat > O.Remat; + } + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + Printable print() const; +#endif - RematInstruction(MachineInstr *UseMI) : UseMI(UseMI) {} + private: + /// Number of 32-bit registers this rematerialization covers. + unsigned NumRegs; + + // The three members below are the scoring components, top to bottom from + // most important to least important when comparing candidates. + + /// Frequency of impacted target region with highest known frequency. This + /// only matters when the stage is trying to reduce spilling, so it is + /// always 0 when it is not. + uint64_t MaxFreq; + /// Frequency difference between defining and using regions. Negative values + /// indicate we are rematerializing to higher frequency regions; positive + /// values indicate the contrary. + int64_t FreqDiff; + /// Expected number of target regions impacted by the rematerialization, + /// scaled by the size of the register being rematerialized. + unsigned RegionImpact; + + unsigned getNumRegs(const GCNScheduleDAGMILive &DAG) const; + + int64_t getFreqDiff(const FreqInfo &Freq) const; }; - /// Maps all MIs to their parent region. MI terminators are considered to be - /// outside the region they delimitate, and as such are not stored in the map. - DenseMap MIRegion; /// Parent MBB to each region, in region order. SmallVector RegionBB; - /// Collects instructions to rematerialize. - MapVector Rematerializations; - /// Collects regions whose live-ins or register pressure will change due to - /// rematerializations. - DenseMap ImpactedRegions; - /// In case we need to rollback rematerializations, save lane masks for all - /// rematerialized registers in all regions in which they are live-ins. - DenseMap, LaneBitmask> RegMasks; - /// After successful stage initialization, indicates which regions should be - /// rescheduled. - BitVector RescheduleRegions; - /// The target occupancy the stage is trying to achieve. Empty when the + /// Register pressure targets for all regions. + SmallVector RPTargets; + /// Regions which are above the stage's RP target. + BitVector TargetRegions; + /// The target occupancy the set is trying to achieve. Empty when the /// objective is spilling reduction. std::optional TargetOcc; /// Achieved occupancy *only* through rematerializations (pre-rescheduling). unsigned AchievedOcc; + /// After successful stage initialization, indicates which regions should be + /// rescheduled. + BitVector RescheduleRegions; + + /// List of rematerializable registers. + SmallVector RematRegs; + + /// Holds enough information to rollback a rematerialization decision post + /// re-scheduling. + struct RollbackInfo { + /// The rematerializable register under consideration. + const RematReg *Remat; + /// The rematerialized MI replacing the original defining MI. + MachineInstr *RematMI; + /// Maps register machine operand indices to their original register. + SmallDenseMap RegMap; + + RollbackInfo(const RematReg *Remat) : Remat(Remat) {} + }; + /// List of rematerializations to rollback if rematerialization does not end + /// up being beneficial. + SmallVector Rollbacks; /// State of a region pre-re-scheduling but post-rematerializations that we /// must keep to be able to revert re-scheduling effects. @@ -582,20 +710,46 @@ class PreRARematStage : public GCNSchedStage { /// Returns the occupancy the stage is trying to achieve. unsigned getStageTargetOccupancy() const; - /// Returns whether remat can reduce spilling or increase function occupancy - /// by 1 through rematerialization. If it can do one, collects instructions in - /// PreRARematStage::Rematerializations and sets the target occupancy in - /// PreRARematStage::TargetOccupancy. - bool canIncreaseOccupancyOrReduceSpill(); + /// Determines the stage's objective (increasing occupancy or reducing + /// spilling, set in \ref TargetOcc). Defines \ref RPTargets in all regions to + /// achieve that objective and mark those that don't achieve it in \ref + /// TargetRegions. Returns whether there is any target region. + bool setObjective(); + + /// Unsets target regions in \p Regions whose RP target has been reached. + void unsetSatisifedRPTargets(const BitVector &Regions); + + /// Fully recomputes RP from the DAG in \p Regions. Among those regions, sets + /// again all \ref TargetRegions that were optimistically marked as satisfied + /// but are actually not, and returns whether there were any such regions. + bool updateAndVerifyRPTargets(const BitVector &Regions); + + /// Collects all rematerializable registers and appends them to \ref + /// RematRegs. \p MIRegion maps MIs to their region. Returns whether any + /// rematerializable register was found. + bool collectRematRegs(const DenseMap &MIRegion); + + /// Rematerializes \p Remat. This removes the rematerialized register from + /// live-in/out lists in the DAG and updates RP targets in all affected + /// regions, which are also marked in \ref RescheduleRegions. Regions in which + /// RP savings are not guaranteed are set in \p RecomputeRP. When \p Rollback + /// is non-null, fills it with required information to be able to rollback the + /// rematerialization post-rescheduling. + void rematerialize(const RematReg &Remat, BitVector &RecomputeRP, + RollbackInfo *Rollback); + + /// Rollbacks the rematerialization decision represented by \p Rollback. This + /// update live-in/out lists in the DAG but does not update cached register + /// pressures. + void rollback(const RollbackInfo &Rollback) const; + + /// Deletes all rematerialized MIs from the MIR when they were kept around for + /// potential rollback. + void commitRematerializations() const; /// Whether the MI is rematerializable bool isReMaterializable(const MachineInstr &MI); - /// Rematerializes all instructions in PreRARematStage::Rematerializations - /// and stores the achieved occupancy after remat in - /// PreRARematStage::AchievedOcc. - void rematerialize(); - /// If remat alone did not increase occupancy to the target one, rollbacks all /// rematerializations and resets live-ins/RP in all regions impacted by the /// stage to their pre-stage values. @@ -611,7 +765,12 @@ class PreRARematStage : public GCNSchedStage { bool shouldRevertScheduling(unsigned WavesAfter) override; PreRARematStage(GCNSchedStageID StageID, GCNScheduleDAGMILive &DAG) - : GCNSchedStage(StageID, DAG), RescheduleRegions(DAG.Regions.size()) {} + : GCNSchedStage(StageID, DAG), TargetRegions(DAG.Regions.size()), + RescheduleRegions(DAG.Regions.size()) { + const unsigned NumRegions = DAG.Regions.size(); + RPTargets.reserve(NumRegions); + RegionBB.reserve(NumRegions); + } }; class ILPInitialScheduleStage : public GCNSchedStage { diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index d27a7384a7da1..b308e0d77305f 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -475,6 +475,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo, return HasDPP && getGeneration() < GFX10; } + bool hasDPPRowShare() const { + return HasDPP && (HasGFX90AInsts || getGeneration() >= GFX10); + } + // Has V_PK_MOV_B32 opcode bool hasPkMovB32() const { return HasGFX90AInsts; } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index 5a00cb8a4b6cb..4aa4083b6c2ab 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -1468,26 +1468,10 @@ void AMDGPUInstPrinter::printMatrixFMT(const MCInst *MI, unsigned OpNo, return; O << " matrix_" << AorB << "_fmt:"; - switch (Imm) { - default: + if (Imm < static_cast(std::size(WMMAMods::ModMatrixFmt))) + O << WMMAMods::ModMatrixFmt[Imm]; + else O << Imm; - break; - case WMMA::MatrixFMT::MATRIX_FMT_FP8: - O << "MATRIX_FMT_FP8"; - break; - case WMMA::MatrixFMT::MATRIX_FMT_BF8: - O << "MATRIX_FMT_BF8"; - break; - case WMMA::MatrixFMT::MATRIX_FMT_FP6: - O << "MATRIX_FMT_FP6"; - break; - case WMMA::MatrixFMT::MATRIX_FMT_BF6: - O << "MATRIX_FMT_BF6"; - break; - case WMMA::MatrixFMT::MATRIX_FMT_FP4: - O << "MATRIX_FMT_FP4"; - break; - } } void AMDGPUInstPrinter::printMatrixAFMT(const MCInst *MI, unsigned OpNo, @@ -1510,17 +1494,10 @@ void AMDGPUInstPrinter::printMatrixScale(const MCInst *MI, unsigned OpNo, return; O << " matrix_" << AorB << "_scale:"; - switch (Imm) { - default: + if (Imm < static_cast(std::size(WMMAMods::ModMatrixScale))) + O << WMMAMods::ModMatrixScale[Imm]; + else O << Imm; - break; - case WMMA::MatrixScale::MATRIX_SCALE_ROW0: - O << "MATRIX_SCALE_ROW0"; - break; - case WMMA::MatrixScale::MATRIX_SCALE_ROW1: - O << "MATRIX_SCALE_ROW1"; - break; - } } void AMDGPUInstPrinter::printMatrixAScale(const MCInst *MI, unsigned OpNo, @@ -1543,20 +1520,10 @@ void AMDGPUInstPrinter::printMatrixScaleFmt(const MCInst *MI, unsigned OpNo, return; O << " matrix_" << AorB << "_scale_fmt:"; - switch (Imm) { - default: + if (Imm < static_cast(std::size(WMMAMods::ModMatrixScaleFmt))) + O << WMMAMods::ModMatrixScaleFmt[Imm]; + else O << Imm; - break; - case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E8: - O << "MATRIX_SCALE_FMT_E8"; - break; - case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E5M3: - O << "MATRIX_SCALE_FMT_E5M3"; - break; - case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E4M3: - O << "MATRIX_SCALE_FMT_E4M3"; - break; - } } void AMDGPUInstPrinter::printMatrixAScaleFmt(const MCInst *MI, unsigned OpNo, @@ -1694,6 +1661,19 @@ void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo, } } +void AMDGPUInstPrinter::printWaitEvent(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + using namespace llvm::AMDGPU::WaitEvent; + const uint16_t Imm16 = static_cast(MI->getOperand(OpNo).getImm()); + + StringRef EventName = getWaitEventMaskName(Imm16, STI); + if (EventName.empty()) + O << formatHex(static_cast(Imm16)); + else + O << EventName; +} + static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h index 564d6eea52328..5e9ebc6716c7f 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -235,6 +235,8 @@ class AMDGPUInstPrinter : public MCInstPrinter { raw_ostream &O); void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printWaitEvent(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printSWaitCnt(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp index 093c85ecabab0..63437779121a7 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp @@ -455,7 +455,7 @@ static void unaryOpKnownBitsMapHelper(const MCExpr *Expr, KnownBitsMap &KBM, return; case MCUnaryExpr::Opcode::Minus: { KB.makeNegative(); - KBM[Expr] = KB; + KBM[Expr] = std::move(KB); return; } case MCUnaryExpr::Opcode::Not: { @@ -466,7 +466,7 @@ static void unaryOpKnownBitsMapHelper(const MCExpr *Expr, KnownBitsMap &KBM, } case MCUnaryExpr::Opcode::Plus: { KB.makeNonNegative(); - KBM[Expr] = KB; + KBM[Expr] = std::move(KB); return; } } @@ -488,7 +488,7 @@ static void targetOpKnownBitsMapHelper(const MCExpr *Expr, KnownBitsMap &KBM, knownBitsMapHelper(Arg, KBM, Depth + 1); KB |= KBM[Arg]; } - KBM[Expr] = KB; + KBM[Expr] = std::move(KB); return; } case AMDGPUMCExpr::VariantKind::AGVK_Max: { @@ -498,7 +498,7 @@ static void targetOpKnownBitsMapHelper(const MCExpr *Expr, KnownBitsMap &KBM, knownBitsMapHelper(Arg, KBM, Depth + 1); KB = KnownBits::umax(KB, KBM[Arg]); } - KBM[Expr] = KB; + KBM[Expr] = std::move(KB); return; } case AMDGPUMCExpr::VariantKind::AGVK_ExtraSGPRs: diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp index f86b42bdc53cf..86c5d1c3a2532 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -114,6 +114,7 @@ StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) { case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: AK = GK_GFX1151; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152: AK = GK_GFX1152; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153: AK = GK_GFX1153; break; + case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170: AK = GK_GFX1170; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: AK = GK_GFX1200; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201: AK = GK_GFX1201; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250: AK = GK_GFX1250; break; @@ -202,6 +203,7 @@ unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) { case GK_GFX1151: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151; case GK_GFX1152: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1152; case GK_GFX1153: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1153; + case GK_GFX1170: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1170; case GK_GFX1200: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200; case GK_GFX1201: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201; case GK_GFX1250: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1250; diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td index 65dce74a1e894..b023c96296b2c 100644 --- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -2076,12 +2076,12 @@ class VIMAGE_TENSOR_Pseudo : string AsmOperands = " $vaddr0, $vaddr1"#!if(UpTo2D, "", ", $vaddr2, $vaddr3")#"$r128$cpol"; } -let SubtargetPredicate = isGFX1250Plus in { +let SubtargetPredicate = isGFX125xOnly in { def TENSOR_LOAD_TO_LDS : VIMAGE_TENSOR_Pseudo<"tensor_load_to_lds">; def TENSOR_STORE_FROM_LDS : VIMAGE_TENSOR_Pseudo<"tensor_store_from_lds">; def TENSOR_LOAD_TO_LDS_D2 : VIMAGE_TENSOR_Pseudo<"tensor_load_to_lds", 1>; def TENSOR_STORE_FROM_LDS_D2 : VIMAGE_TENSOR_Pseudo<"tensor_store_from_lds", 1>; -} // End SubtargetPredicate = isGFX1250Plus. +} // End SubtargetPredicate = isGFX125xOnly. class TensorPat : GCNPat < (node v4i32:$vaddr0, v8i32:$vaddr1, v4i32:$vaddr2, v4i32:$vaddr3, (i32 timm:$cpol)), @@ -2093,12 +2093,12 @@ class TensorD2Pat : GCNPat < (inst $vaddr0, $vaddr1, 0, $cpol) >; -let SubtargetPredicate = isGFX1250Plus in { +let SubtargetPredicate = isGFX125xOnly in { def : TensorPat ; def : TensorPat ; def : TensorD2Pat ; def : TensorD2Pat ; -} +} // End SubtargetPredicate = isGFX125xOnly. class VIMAGE_TENSOR_Real op, VIMAGE_TENSOR_Pseudo ps, string opName = ps.Mnemonic> : InstSI , @@ -2130,7 +2130,7 @@ class VIMAGE_TENSOR_Real op, VIMAGE_TENSOR_Pseudo ps, string opName = p } multiclass VIMAGE_TENSOR_Real_gfx1250 op> { - let AssemblerPredicate = isGFX1250Plus, DecoderNamespace = "GFX1250" in { + let AssemblerPredicate = isGFX125xOnly, DecoderNamespace = "GFX1250" in { foreach DSuffix = ["_D2", ""] in { defvar ps = !cast(NAME # DSuffix); def DSuffix # _gfx1250 : VIMAGE_TENSOR_Real, diff --git a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp index d2a204ed97914..9e1a97e95dc23 100644 --- a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -222,8 +222,8 @@ MachineInstr *R600VectorRegMerger::RebuildVector( // Update RSI RSI->Instr = NewMI; - RSI->RegToChan = UpdatedRegToChan; - RSI->UndefReg = UpdatedUndef; + RSI->RegToChan = std::move(UpdatedRegToChan); + RSI->UndefReg = std::move(UpdatedUndef); return NewMI; } diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index 147ef9dddebf6..0c7c64220d72a 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -450,7 +450,6 @@ enum Id { // Message ID, width(4) [3:0]. ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10 ID_GS_ALLOC_REQ = 9, // added in GFX9 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11 - ID_SAVEWAVE_HAS_TDM = 10, // added in GFX1250 ID_GET_DDID = 11, // added in GFX10, removed in GFX11 ID_SYSMSG = 15, @@ -464,6 +463,7 @@ enum Id { // Message ID, width(4) [3:0]. ID_RTN_GET_SE_AID_ID = 135, ID_RTN_GET_CLUSTER_BARRIER_STATE = 136, // added in GFX1250 + ID_RTN_SAVE_WAVE_HAS_TDM = 152, // added in GFX1250 ID_MASK_PreGFX11_ = 0xF, ID_MASK_GFX11Plus_ = 0xFF @@ -501,6 +501,14 @@ enum StreamId : unsigned { // Stream ID, (2) [9:8]. } // namespace SendMsg +namespace WaitEvent { // Encoding of SIMM16 used in s_wait_event +enum Id { + DONT_WAIT_EXPORT_READY = 1 << 0, // Only used in gfx11 + EXPORT_READY = 1 << 1, // gfx12+ +}; + +} // namespace WaitEvent + namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. enum Id { // HwRegCode, (6) [5:0] diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 074c404349234..8782fc5fc9bb7 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -1013,7 +1013,7 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) { AnalysisWorklist.push_back(U); } } - V2SCopies[Info.ID] = Info; + V2SCopies[Info.ID] = std::move(Info); } // The main function that computes the VGPR to SGPR copy score diff --git a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp index d0d679221eee0..b368e2036e404 100644 --- a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp @@ -27,9 +27,7 @@ class SIFixVGPRCopiesLegacy : public MachineFunctionPass { public: static char ID; - SIFixVGPRCopiesLegacy() : MachineFunctionPass(ID) { - initializeSIFixVGPRCopiesLegacyPass(*PassRegistry::getPassRegistry()); - } + SIFixVGPRCopiesLegacy() : MachineFunctionPass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 3f72b65e8148a..a2fe31bd849c3 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -1445,6 +1445,7 @@ void SIFoldOperandsImpl::foldOperand( return; UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32)); + UseMI->clearFlag(MachineInstr::NoConvergent); if (OpToFold.isImm()) { UseMI->getOperand(1).ChangeToImmediate( @@ -1476,6 +1477,7 @@ void SIFoldOperandsImpl::foldOperand( UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); UseMI->getOperand(1).setIsKill(false); UseMI->removeOperand(2); // Remove exec read (or src1 for readlane) + UseMI->clearFlag(MachineInstr::NoConvergent); return; } } diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp index e9aec826f5c72..982034189892c 100644 --- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp +++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp @@ -61,9 +61,7 @@ class SIFormMemoryClausesLegacy : public MachineFunctionPass { public: static char ID; - SIFormMemoryClausesLegacy() : MachineFunctionPass(ID) { - initializeSIFormMemoryClausesLegacyPass(*PassRegistry::getPassRegistry()); - } + SIFormMemoryClausesLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 0ef81a83d1be8..a0952b3b566a7 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -724,14 +724,7 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF, FrameInfo.getMaxAlign()); MFI->setScratchReservedForDynamicVGPRs(VGPRSize); - BuildMI(MBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), FPReg) - .addImm(AMDGPU::Hwreg::HwregEncoding::encode( - AMDGPU::Hwreg::ID_HW_ID2, AMDGPU::Hwreg::OFFSET_ME_ID, 2)); - // The MicroEngine ID is 0 for the graphics queue, and 1 or 2 for compute - // (3 is unused, so we ignore it). Unfortunately, S_GETREG doesn't set - // SCC, so we need to check for 0 manually. - BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32)).addImm(0).addReg(FPReg); - BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CMOVK_I32), FPReg).addImm(VGPRSize); + BuildMI(MBB, I, DL, TII->get(AMDGPU::GET_STACK_BASE), FPReg); if (requiresStackPointerReference(MF)) { Register SPReg = MFI->getStackPtrOffsetReg(); assert(SPReg != AMDGPU::SP_REG); diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index b043d5354042d..44535f471b70d 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1293,57 +1293,61 @@ static unsigned getIntrMemWidth(unsigned IntrID) { case Intrinsic::amdgcn_global_store_async_from_lds_b32: case Intrinsic::amdgcn_cooperative_atomic_load_32x4B: case Intrinsic::amdgcn_cooperative_atomic_store_32x4B: + case Intrinsic::amdgcn_flat_load_monitor_b32: + case Intrinsic::amdgcn_global_load_monitor_b32: return 32; case Intrinsic::amdgcn_global_load_async_to_lds_b64: case Intrinsic::amdgcn_cluster_load_async_to_lds_b64: case Intrinsic::amdgcn_global_store_async_from_lds_b64: case Intrinsic::amdgcn_cooperative_atomic_load_16x8B: case Intrinsic::amdgcn_cooperative_atomic_store_16x8B: + case Intrinsic::amdgcn_flat_load_monitor_b64: + case Intrinsic::amdgcn_global_load_monitor_b64: return 64; case Intrinsic::amdgcn_global_load_async_to_lds_b128: case Intrinsic::amdgcn_cluster_load_async_to_lds_b128: case Intrinsic::amdgcn_global_store_async_from_lds_b128: case Intrinsic::amdgcn_cooperative_atomic_load_8x16B: case Intrinsic::amdgcn_cooperative_atomic_store_8x16B: + case Intrinsic::amdgcn_flat_load_monitor_b128: + case Intrinsic::amdgcn_global_load_monitor_b128: return 128; default: llvm_unreachable("Unknown width"); } } -static void getCoopAtomicOperandsInfo(const CallBase &CI, bool IsLoad, - TargetLoweringBase::IntrinsicInfo &Info) { - Value *OrderingArg = CI.getArgOperand(IsLoad ? 1 : 2); +static AtomicOrdering parseAtomicOrderingCABIArg(const CallBase &CI, + unsigned ArgIdx) { + Value *OrderingArg = CI.getArgOperand(ArgIdx); unsigned Ord = cast(OrderingArg)->getZExtValue(); switch (AtomicOrderingCABI(Ord)) { case AtomicOrderingCABI::acquire: - Info.order = AtomicOrdering::Acquire; + return AtomicOrdering::Acquire; break; case AtomicOrderingCABI::release: - Info.order = AtomicOrdering::Release; + return AtomicOrdering::Release; break; case AtomicOrderingCABI::seq_cst: - Info.order = AtomicOrdering::SequentiallyConsistent; + return AtomicOrdering::SequentiallyConsistent; break; default: - Info.order = AtomicOrdering::Monotonic; - break; + return AtomicOrdering::Monotonic; } +} - Info.flags = - (IsLoad ? MachineMemOperand::MOLoad : MachineMemOperand::MOStore); - Info.flags |= MOCooperative; - +static unsigned parseSyncscopeMDArg(const CallBase &CI, unsigned ArgIdx) { MDNode *ScopeMD = cast( - cast(CI.getArgOperand(IsLoad ? 2 : 3))->getMetadata()); + cast(CI.getArgOperand(ArgIdx))->getMetadata()); StringRef Scope = cast(ScopeMD->getOperand(0))->getString(); - Info.ssid = CI.getContext().getOrInsertSyncScopeID(Scope); + return CI.getContext().getOrInsertSyncScopeID(Scope); } -bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, +void SITargetLowering::getTgtMemIntrinsic(SmallVectorImpl &Infos, const CallBase &CI, MachineFunction &MF, unsigned IntrID) const { + IntrinsicInfo Info; Info.flags = MachineMemOperand::MONone; if (CI.hasMetadata(LLVMContext::MD_invariant_load)) Info.flags |= MachineMemOperand::MOInvariant; @@ -1357,7 +1361,7 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Intrinsic::getFnAttributes(CI.getContext(), (Intrinsic::ID)IntrID); MemoryEffects ME = Attr.getMemoryEffects(); if (ME.doesNotAccessMemory()) - return false; + return; // TODO: Should images get their own address space? Info.fallbackAddressSpace = AMDGPUAS::BUFFER_RESOURCE; @@ -1451,9 +1455,27 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::amdgcn_struct_buffer_load_lds: case Intrinsic::amdgcn_struct_ptr_buffer_load_lds: { unsigned Width = cast(CI.getArgOperand(2))->getZExtValue(); + + // Entry 0: Load from buffer. + // Don't set an offset, since the pointer value always represents the + // base of the buffer. Info.memVT = EVT::getIntegerVT(CI.getContext(), Width * 8); - Info.ptrVal = CI.getArgOperand(1); - return true; + Info.flags &= ~MachineMemOperand::MOStore; + Infos.push_back(Info); + + // Entry 1: Store to LDS. + // Instruction offset is applied, and an additional per-lane offset + // which we simulate using a larger memory type. + Info.memVT = EVT::getIntegerVT( + CI.getContext(), Width * 8 * Subtarget->getWavefrontSize()); + Info.ptrVal = CI.getArgOperand(1); // LDS destination pointer + Info.offset = cast(CI.getArgOperand(CI.arg_size() - 2)) + ->getZExtValue(); + Info.fallbackAddressSpace = AMDGPUAS::LOCAL_ADDRESS; + Info.flags &= ~MachineMemOperand::MOLoad; + Info.flags |= MachineMemOperand::MOStore; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_raw_atomic_buffer_load: case Intrinsic::amdgcn_raw_ptr_atomic_buffer_load: @@ -1463,11 +1485,13 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, memVTFromLoadIntrReturn(*this, MF.getDataLayout(), CI.getType(), std::numeric_limits::max()); Info.flags &= ~MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } } } - return true; + Infos.push_back(Info); + return; } switch (IntrID) { @@ -1483,7 +1507,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, if (!Vol->isZero()) Info.flags |= MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_add_gs_reg_rtn: case Intrinsic::amdgcn_ds_sub_gs_reg_rtn: { @@ -1492,7 +1517,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.ptrVal = nullptr; Info.fallbackAddressSpace = AMDGPUAS::STREAMOUT_REGISTER; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_append: case Intrinsic::amdgcn_ds_consume: { @@ -1506,7 +1532,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, if (!Vol->isZero()) Info.flags |= MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_atomic_async_barrier_arrive_b64: case Intrinsic::amdgcn_ds_atomic_barrier_arrive_rtn_b64: { @@ -1519,7 +1546,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.size = 8; Info.align.reset(); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_image_bvh_dual_intersect_ray: case Intrinsic::amdgcn_image_bvh_intersect_ray: @@ -1535,7 +1563,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align.reset(); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_global_atomic_fmin_num: case Intrinsic::amdgcn_global_atomic_fmax_num: @@ -1549,14 +1578,9 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MODereferenceable | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } - case Intrinsic::amdgcn_flat_load_monitor_b32: - case Intrinsic::amdgcn_flat_load_monitor_b64: - case Intrinsic::amdgcn_flat_load_monitor_b128: - case Intrinsic::amdgcn_global_load_monitor_b32: - case Intrinsic::amdgcn_global_load_monitor_b64: - case Intrinsic::amdgcn_global_load_monitor_b128: case Intrinsic::amdgcn_cluster_load_b32: case Intrinsic::amdgcn_cluster_load_b64: case Intrinsic::amdgcn_cluster_load_b128: @@ -1577,7 +1601,24 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.ptrVal = CI.getOperand(0); Info.align.reset(); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; + } + case Intrinsic::amdgcn_flat_load_monitor_b32: + case Intrinsic::amdgcn_flat_load_monitor_b64: + case Intrinsic::amdgcn_flat_load_monitor_b128: + case Intrinsic::amdgcn_global_load_monitor_b32: + case Intrinsic::amdgcn_global_load_monitor_b64: + case Intrinsic::amdgcn_global_load_monitor_b128: { + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.memVT = EVT::getIntegerVT(CI.getContext(), getIntrMemWidth(IntrID)); + Info.ptrVal = CI.getOperand(0); + Info.align.reset(); + Info.flags = MachineMemOperand::MOLoad; + Info.order = parseAtomicOrderingCABIArg(CI, 1); + Info.ssid = parseSyncscopeMDArg(CI, 2); + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_cooperative_atomic_load_32x4B: case Intrinsic::amdgcn_cooperative_atomic_load_16x8B: @@ -1586,8 +1627,11 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(CI.getContext(), getIntrMemWidth(IntrID)); Info.ptrVal = CI.getOperand(0); Info.align.reset(); - getCoopAtomicOperandsInfo(CI, /*IsLoad=*/true, Info); - return true; + Info.flags = (MachineMemOperand::MOLoad | MOCooperative); + Info.order = parseAtomicOrderingCABIArg(CI, 1); + Info.ssid = parseSyncscopeMDArg(CI, 2); + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_cooperative_atomic_store_32x4B: case Intrinsic::amdgcn_cooperative_atomic_store_16x8B: @@ -1596,8 +1640,11 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(CI.getContext(), getIntrMemWidth(IntrID)); Info.ptrVal = CI.getArgOperand(0); Info.align.reset(); - getCoopAtomicOperandsInfo(CI, /*IsLoad=*/false, Info); - return true; + Info.flags = (MachineMemOperand::MOStore | MOCooperative); + Info.order = parseAtomicOrderingCABIArg(CI, 2); + Info.ssid = parseSyncscopeMDArg(CI, 3); + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_gws_init: case Intrinsic::amdgcn_ds_gws_barrier: @@ -1622,7 +1669,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags |= MachineMemOperand::MOLoad; else Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_global_load_async_to_lds_b8: case Intrinsic::amdgcn_global_load_async_to_lds_b32: @@ -1632,33 +1680,66 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::amdgcn_cluster_load_async_to_lds_b32: case Intrinsic::amdgcn_cluster_load_async_to_lds_b64: case Intrinsic::amdgcn_cluster_load_async_to_lds_b128: { + // Entry 0: Load from source (global/flat). Info.opc = ISD::INTRINSIC_VOID; Info.memVT = EVT::getIntegerVT(CI.getContext(), getIntrMemWidth(IntrID)); - Info.ptrVal = CI.getArgOperand(1); - Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Info.ptrVal = CI.getArgOperand(0); // Global pointer + Info.offset = cast(CI.getArgOperand(2))->getSExtValue(); + Info.flags |= MachineMemOperand::MOLoad; + Infos.push_back(Info); + + // Entry 1: Store to LDS (same offset). + Info.flags &= ~MachineMemOperand::MOLoad; + Info.flags |= MachineMemOperand::MOStore; + Info.ptrVal = CI.getArgOperand(1); // LDS pointer + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_global_store_async_from_lds_b8: case Intrinsic::amdgcn_global_store_async_from_lds_b32: case Intrinsic::amdgcn_global_store_async_from_lds_b64: case Intrinsic::amdgcn_global_store_async_from_lds_b128: { + // Entry 0: Load from LDS. Info.opc = ISD::INTRINSIC_VOID; Info.memVT = EVT::getIntegerVT(CI.getContext(), getIntrMemWidth(IntrID)); - Info.ptrVal = CI.getArgOperand(0); - Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Info.ptrVal = CI.getArgOperand(1); // LDS pointer + Info.offset = cast(CI.getArgOperand(2))->getSExtValue(); + Info.flags |= MachineMemOperand::MOLoad; + Infos.push_back(Info); + + // Entry 1: Store to global (same offset). + Info.flags &= ~MachineMemOperand::MOLoad; + Info.flags |= MachineMemOperand::MOStore; + Info.ptrVal = CI.getArgOperand(0); // Global pointer + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_load_to_lds: case Intrinsic::amdgcn_global_load_lds: { - Info.opc = ISD::INTRINSIC_VOID; unsigned Width = cast(CI.getArgOperand(2))->getZExtValue(); - Info.memVT = EVT::getIntegerVT(CI.getContext(), Width * 8); - Info.ptrVal = CI.getArgOperand(1); - Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore; auto *Aux = cast(CI.getArgOperand(CI.arg_size() - 1)); - if (Aux->getZExtValue() & AMDGPU::CPol::VOLATILE) + bool IsVolatile = Aux->getZExtValue() & AMDGPU::CPol::VOLATILE; + + // Entry 0: Load from source (global/flat). + Info.opc = ISD::INTRINSIC_VOID; + Info.memVT = EVT::getIntegerVT(CI.getContext(), Width * 8); + Info.ptrVal = CI.getArgOperand(0); // Source pointer + Info.offset = cast(CI.getArgOperand(3))->getSExtValue(); + Info.flags |= MachineMemOperand::MOLoad; + if (IsVolatile) Info.flags |= MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + + // Entry 1: Store to LDS. + // Same offset from the instruction, but an additional per-lane offset is + // added. Represent that using a wider memory type. + Info.memVT = EVT::getIntegerVT(CI.getContext(), + Width * 8 * Subtarget->getWavefrontSize()); + Info.ptrVal = CI.getArgOperand(1); // LDS destination pointer + Info.flags &= ~MachineMemOperand::MOLoad; + Info.flags |= MachineMemOperand::MOStore; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_ds_bvh_stack_rtn: case Intrinsic::amdgcn_ds_bvh_stack_push4_pop1_rtn: @@ -1678,7 +1759,8 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(4); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::amdgcn_s_prefetch_data: case Intrinsic::amdgcn_flat_prefetch: @@ -1687,10 +1769,11 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(CI.getContext(), 8); Info.ptrVal = CI.getArgOperand(0); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } default: - return false; + return; } } @@ -1735,15 +1818,9 @@ bool SITargetLowering::getAddrModeArguments(const IntrinsicInst *II, case Intrinsic::amdgcn_ds_atomic_barrier_arrive_rtn_b64: case Intrinsic::amdgcn_flat_atomic_fmax_num: case Intrinsic::amdgcn_flat_atomic_fmin_num: - case Intrinsic::amdgcn_flat_load_monitor_b128: - case Intrinsic::amdgcn_flat_load_monitor_b32: - case Intrinsic::amdgcn_flat_load_monitor_b64: case Intrinsic::amdgcn_global_atomic_fmax_num: case Intrinsic::amdgcn_global_atomic_fmin_num: case Intrinsic::amdgcn_global_atomic_ordered_add_b64: - case Intrinsic::amdgcn_global_load_monitor_b128: - case Intrinsic::amdgcn_global_load_monitor_b32: - case Intrinsic::amdgcn_global_load_monitor_b64: case Intrinsic::amdgcn_global_load_tr_b64: case Intrinsic::amdgcn_global_load_tr_b128: case Intrinsic::amdgcn_global_load_tr4_b64: @@ -6966,6 +7043,8 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { return LowerBRCOND(Op, DAG); case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); + case ISD::SPONENTRY: + return LowerSPONENTRY(Op, DAG); case ISD::LOAD: { SDValue Result = LowerLOAD(Op, DAG); assert((!Result.getNode() || Result.getNode()->getNumValues() == 2) && @@ -7979,6 +8058,20 @@ SDValue SITargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT); } +SDValue SITargetLowering::LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + SIMachineFunctionInfo *MFI = MF.getInfo(); + + // For functions that set up their own stack, select the GET_STACK_BASE + // pseudo. + if (MFI->isBottomOfStack()) + return Op; + + // For everything else, create a dummy stack object. + int FI = MF.getFrameInfo().CreateFixedObject(1, 0, /*IsImmutable=*/false); + return DAG.getFrameIndex(FI, Op.getValueType()); +} + SDValue SITargetLowering::getFPExtOrFPRound(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, EVT VT) const { return Op.getValueType().bitsLE(VT) @@ -11183,6 +11276,26 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, return DAG.getAtomicLoad(ISD::NON_EXTLOAD, DL, MII->getMemoryVT(), VT, Chain, Ptr, MII->getMemOperand()); } + case Intrinsic::amdgcn_flat_load_monitor_b32: + case Intrinsic::amdgcn_flat_load_monitor_b64: + case Intrinsic::amdgcn_flat_load_monitor_b128: { + MemIntrinsicSDNode *MII = cast(Op); + SDValue Chain = Op->getOperand(0); + SDValue Ptr = Op->getOperand(2); + return DAG.getMemIntrinsicNode(AMDGPUISD::FLAT_LOAD_MONITOR, DL, + Op->getVTList(), {Chain, Ptr}, + MII->getMemoryVT(), MII->getMemOperand()); + } + case Intrinsic::amdgcn_global_load_monitor_b32: + case Intrinsic::amdgcn_global_load_monitor_b64: + case Intrinsic::amdgcn_global_load_monitor_b128: { + MemIntrinsicSDNode *MII = cast(Op); + SDValue Chain = Op->getOperand(0); + SDValue Ptr = Op->getOperand(2); + return DAG.getMemIntrinsicNode(AMDGPUISD::GLOBAL_LOAD_MONITOR, DL, + Op->getVTList(), {Chain, Ptr}, + MII->getMemoryVT(), MII->getMemOperand()); + } default: if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr = @@ -11326,7 +11439,6 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, SDLoc DL(Op); SDValue Chain = Op.getOperand(0); unsigned IntrinsicID = Op.getConstantOperandVal(1); - MachineFunction &MF = DAG.getMachineFunction(); switch (IntrinsicID) { case Intrinsic::amdgcn_exp_compr: { @@ -11601,29 +11713,8 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, Ops.push_back(M0Val.getValue(1)); // Glue auto *M = cast(Op); - MachineMemOperand *LoadMMO = M->getMemOperand(); - // Don't set the offset value here because the pointer points to the base of - // the buffer. - MachinePointerInfo LoadPtrI = LoadMMO->getPointerInfo(); - - MachinePointerInfo StorePtrI = LoadPtrI; - LoadPtrI.V = PoisonValue::get( - PointerType::get(*DAG.getContext(), AMDGPUAS::BUFFER_RESOURCE)); - LoadPtrI.AddrSpace = AMDGPUAS::BUFFER_RESOURCE; - StorePtrI.AddrSpace = AMDGPUAS::LOCAL_ADDRESS; - - auto F = LoadMMO->getFlags() & - ~(MachineMemOperand::MOStore | MachineMemOperand::MOLoad); - LoadMMO = - MF.getMachineMemOperand(LoadPtrI, F | MachineMemOperand::MOLoad, Size, - LoadMMO->getBaseAlign(), LoadMMO->getAAInfo()); - - MachineMemOperand *StoreMMO = MF.getMachineMemOperand( - StorePtrI, F | MachineMemOperand::MOStore, sizeof(int32_t), - LoadMMO->getBaseAlign(), LoadMMO->getAAInfo()); - auto *Load = DAG.getMachineNode(Opc, DL, M->getVTList(), Ops); - DAG.setNodeMemRefs(Load, {LoadMMO, StoreMMO}); + DAG.setNodeMemRefs(Load, M->memoperands()); return SDValue(Load, 0); } @@ -11705,25 +11796,8 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, Ops.push_back(M0Val.getValue(1)); // Glue auto *M = cast(Op); - MachineMemOperand *LoadMMO = M->getMemOperand(); - MachinePointerInfo LoadPtrI = LoadMMO->getPointerInfo(); - LoadPtrI.Offset = Op->getConstantOperandVal(5); - MachinePointerInfo StorePtrI = LoadPtrI; - LoadPtrI.V = PoisonValue::get( - PointerType::get(*DAG.getContext(), AMDGPUAS::GLOBAL_ADDRESS)); - LoadPtrI.AddrSpace = AMDGPUAS::GLOBAL_ADDRESS; - StorePtrI.AddrSpace = AMDGPUAS::LOCAL_ADDRESS; - auto F = LoadMMO->getFlags() & - ~(MachineMemOperand::MOStore | MachineMemOperand::MOLoad); - LoadMMO = - MF.getMachineMemOperand(LoadPtrI, F | MachineMemOperand::MOLoad, Size, - LoadMMO->getBaseAlign(), LoadMMO->getAAInfo()); - MachineMemOperand *StoreMMO = MF.getMachineMemOperand( - StorePtrI, F | MachineMemOperand::MOStore, sizeof(int32_t), Align(4), - LoadMMO->getAAInfo()); - auto *Load = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops); - DAG.setNodeMemRefs(Load, {LoadMMO, StoreMMO}); + DAG.setNodeMemRefs(Load, M->memoperands()); return SDValue(Load, 0); } @@ -14780,6 +14854,7 @@ SDValue SITargetLowering::performRcpCombine(SDNode *N, } bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op, + SDNodeFlags UserFlags, unsigned MaxDepth) const { unsigned Opcode = Op.getOpcode(); if (Opcode == ISD::FCANONICALIZE) @@ -14979,7 +15054,7 @@ bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op, // FIXME: denormalsEnabledForType is broken for dynamic return denormalsEnabledForType(DAG, Op.getValueType()) && - DAG.isKnownNeverSNaN(Op); + (UserFlags.hasNoNaNs() || DAG.isKnownNeverSNaN(Op)); } bool SITargetLowering::isCanonicalized(Register Reg, const MachineFunction &MF, diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index d56e5ea1f9685..59b8f434957ce 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -132,6 +132,7 @@ class SITargetLowering final : public AMDGPUTargetLowering { SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, SelectionDAG &DAG, ArrayRef Ops, bool IsIntrinsic = false) const; @@ -336,7 +337,7 @@ class SITargetLowering final : public AMDGPUTargetLowering { MVT getPointerTy(const DataLayout &DL, unsigned AS) const override; MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &, const CallBase &, + void getTgtMemIntrinsic(SmallVectorImpl &, const CallBase &, MachineFunction &MF, unsigned IntrinsicID) const override; @@ -559,7 +560,7 @@ class SITargetLowering final : public AMDGPUTargetLowering { Register N1) const override; bool isCanonicalized(SelectionDAG &DAG, SDValue Op, - unsigned MaxDepth = 5) const; + SDNodeFlags UserFlags = {}, unsigned MaxDepth = 5) const; bool isCanonicalized(Register Reg, const MachineFunction &MF, unsigned MaxDepth = 5) const; bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index b39975fdb0561..2014a415f3121 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -410,15 +410,6 @@ void WaitEventSet::dump() const { dbgs() << "\n"; } -// Mapping from event to counter according to the table masks. -InstCounterType eventCounter(const WaitEventSet *masks, WaitEventType E) { - for (auto T : inst_counter_types()) { - if (masks[T].contains(E)) - return T; - } - llvm_unreachable("event type has no associated counter"); -} - class WaitcntBrackets; // This abstracts the logic for generating and updating S_WAIT* instructions @@ -429,8 +420,8 @@ class WaitcntBrackets; // otherwise have had to become. class WaitcntGenerator { protected: - const GCNSubtarget *ST = nullptr; - const SIInstrInfo *TII = nullptr; + const GCNSubtarget &ST; + const SIInstrInfo &TII; AMDGPU::IsaVersion IV; InstCounterType MaxCounter; bool OptNone; @@ -442,8 +433,8 @@ class WaitcntGenerator { WaitcntGenerator(const WaitcntGenerator &) = delete; WaitcntGenerator(const MachineFunction &MF, InstCounterType MaxCounter, const AMDGPU::HardwareLimits *Limits) - : ST(&MF.getSubtarget()), TII(ST->getInstrInfo()), - IV(AMDGPU::getIsaVersion(ST->getCPU())), MaxCounter(MaxCounter), + : ST(MF.getSubtarget()), TII(*ST.getInstrInfo()), + IV(AMDGPU::getIsaVersion(ST.getCPU())), MaxCounter(MaxCounter), OptNone(MF.getFunction().hasOptNone() || MF.getTarget().getOptLevel() == CodeGenOptLevel::None), ExpandWaitcntProfiling( @@ -483,9 +474,17 @@ class WaitcntGenerator { AMDGPU::Waitcnt Wait, const WaitcntBrackets &ScoreBrackets) = 0; - // Returns an array of WaitEventSets which can be used to map values in - // WaitEventType to corresponding counter values in InstCounterType. - virtual const WaitEventSet *getWaitEventMask() const = 0; + // Returns the WaitEventSet that corresponds to counter \p T. + virtual const WaitEventSet &getWaitEvents(InstCounterType T) const = 0; + + /// \returns the counter that corresponds to event \p E. + InstCounterType getCounterFromEvent(WaitEventType E) const { + for (auto T : inst_counter_types()) { + if (getWaitEvents(T).contains(E)) + return T; + } + llvm_unreachable("event type has no associated counter"); + } // Returns a new waitcnt with all counters except VScnt set to 0. If // IncludeVSCnt is true, VScnt is set to 0, otherwise it is set to ~0u. @@ -522,9 +521,8 @@ class WaitcntGeneratorPreGFX12 final : public WaitcntGenerator { AMDGPU::Waitcnt Wait, const WaitcntBrackets &ScoreBrackets) override; - const WaitEventSet *getWaitEventMask() const override { - assert(ST); - return WaitEventMaskForInstPreGFX12; + const WaitEventSet &getWaitEvents(InstCounterType T) const override { + return WaitEventMaskForInstPreGFX12[T]; } AMDGPU::Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const override; @@ -566,9 +564,8 @@ class WaitcntGeneratorGFX12Plus final : public WaitcntGenerator { AMDGPU::Waitcnt Wait, const WaitcntBrackets &ScoreBrackets) override; - const WaitEventSet *getWaitEventMask() const override { - assert(ST); - return WaitEventMaskForInstGFX12Plus; + const WaitEventSet &getWaitEvents(InstCounterType T) const override { + return WaitEventMaskForInstGFX12Plus[T]; } AMDGPU::Waitcnt getAllZeroWaitcnt(bool IncludeVSCnt) const override; @@ -734,8 +731,11 @@ class SIInsertWaitcnts { bool ExpertMode) const; AtomicRMWState getAtomicRMWState(MachineInstr &MI, AtomicRMWState PrevState) const; - const WaitEventSet *getWaitEventMask() const { - return WCG->getWaitEventMask(); + const WaitEventSet &getWaitEvents(InstCounterType T) const { + return WCG->getWaitEvents(T); + } + InstCounterType getCounterFromEvent(WaitEventType E) const { + return WCG->getCounterFromEvent(E); } }; @@ -783,6 +783,18 @@ class WaitcntBrackets { return T == X_CNT ? 1 : 0; } + unsigned getOutstanding(InstCounterType T) const { + return ScoreUBs[T] - ScoreLBs[T]; + } + + bool hasPendingVMEM(VMEMID ID, InstCounterType T) const { + return getVMemScore(ID, T) > getScoreLB(T); + } + + /// \Return true if we have no score entries for counter \p T. + bool empty(InstCounterType T) const { return getScoreRange(T) == 0; } + +private: unsigned getScoreLB(InstCounterType T) const { assert(T < NUM_INST_CNTS); return ScoreLBs[T]; @@ -807,6 +819,7 @@ class WaitcntBrackets { return It != VMem.end() ? It->second.Scores[T] : 0; } +public: bool merge(const WaitcntBrackets &Other); bool counterOutOfOrder(InstCounterType T) const; @@ -836,14 +849,14 @@ class WaitcntBrackets { return PendingEvents.contains(E); } bool hasPendingEvent(InstCounterType T) const { - bool HasPending = PendingEvents & Context->getWaitEventMask()[T]; - assert(HasPending == (getScoreRange(T) != 0) && - "Expected no pending events iff scoreboard is empty"); + bool HasPending = PendingEvents & Context->getWaitEvents(T); + assert(HasPending == !empty(T) && + "Expected pending events iff scoreboard is not empty"); return HasPending; } bool hasMixedPendingEvents(InstCounterType T) const { - WaitEventSet Events = PendingEvents & Context->getWaitEventMask()[T]; + WaitEventSet Events = PendingEvents & Context->getWaitEvents(T); // Return true if more than one bit is set in Events. return Events.twoOrMore(); } @@ -895,7 +908,7 @@ class WaitcntBrackets { void setStateOnFunctionEntryOrReturn() { setScoreUB(STORE_CNT, getScoreUB(STORE_CNT) + getWaitCountMax(Context->getLimits(), STORE_CNT)); - PendingEvents |= Context->getWaitEventMask()[STORE_CNT]; + PendingEvents |= Context->getWaitEvents(STORE_CNT); } ArrayRef getLDSDMAStores() const { @@ -1090,7 +1103,7 @@ bool WaitcntBrackets::hasPointSamplePendingVmemTypes(const MachineInstr &MI, } void WaitcntBrackets::updateByEvent(WaitEventType E, MachineInstr &Inst) { - InstCounterType T = eventCounter(Context->getWaitEventMask(), E); + InstCounterType T = Context->getCounterFromEvent(E); assert(T < Context->MaxCounter); unsigned UB = getScoreUB(T); @@ -1510,7 +1523,7 @@ void WaitcntBrackets::tryClearSCCWriteEvent(MachineInstr *Inst) { PendingSCCWrite->getOperand(0).getImm() == Inst->getOperand(0).getImm()) { WaitEventSet SCC_WRITE_PendingEvent(SCC_WRITE); // If this SCC_WRITE is the only pending KM_CNT event, clear counter. - if ((PendingEvents & Context->getWaitEventMask()[KM_CNT]) == + if ((PendingEvents & Context->getWaitEvents(KM_CNT)) == SCC_WRITE_PendingEvent) { setScoreLB(KM_CNT, getScoreUB(KM_CNT)); } @@ -1543,7 +1556,7 @@ void WaitcntBrackets::applyWaitcnt(InstCounterType T, unsigned Count) { setScoreLB(T, std::max(getScoreLB(T), UB - Count)); } else { setScoreLB(T, UB); - PendingEvents.remove(Context->getWaitEventMask()[T]); + PendingEvents.remove(Context->getWaitEvents(T)); } if (T == KM_CNT && Count == 0 && hasPendingEvent(SMEM_GROUP)) { @@ -1644,7 +1657,7 @@ bool WaitcntGenerator::promoteSoftWaitCnt(MachineInstr *Waitcnt) const { if (Opcode == Waitcnt->getOpcode()) return false; - Waitcnt->setDesc(TII->get(Opcode)); + Waitcnt->setDesc(TII.get(Opcode)); return true; } @@ -1656,7 +1669,6 @@ bool WaitcntGenerator::promoteSoftWaitCnt(MachineInstr *Waitcnt) const { bool WaitcntGeneratorPreGFX12::applyPreexistingWaitcnt( WaitcntBrackets &ScoreBrackets, MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait, MachineBasicBlock::instr_iterator It) const { - assert(ST); assert(isNormalMode(MaxCounter)); bool Modified = false; @@ -1698,7 +1710,7 @@ bool WaitcntGeneratorPreGFX12::applyPreexistingWaitcnt( } else WaitcntInstr = &II; } else if (Opcode == AMDGPU::S_WAITCNT_lds_direct) { - assert(ST->hasVMemToLDSLoad()); + assert(ST.hasVMemToLDSLoad()); LLVM_DEBUG(dbgs() << "Processing S_WAITCNT_lds_direct: " << II << "Before: " << Wait << '\n';); ScoreBrackets.determineWaitForLDSDMA(LOAD_CNT, LDSDMA_BEGIN, Wait); @@ -1716,7 +1728,7 @@ bool WaitcntGeneratorPreGFX12::applyPreexistingWaitcnt( assert(II.getOperand(0).getReg() == AMDGPU::SGPR_NULL); unsigned OldVSCnt = - TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + TII.getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); if (TrySimplify) ScoreBrackets.simplifyWaitcnt(InstCounterType::STORE_CNT, OldVSCnt); Wait.StoreCnt = std::min(Wait.StoreCnt, OldVSCnt); @@ -1774,7 +1786,6 @@ bool WaitcntGeneratorPreGFX12::applyPreexistingWaitcnt( bool WaitcntGeneratorPreGFX12::createNewWaitcnt( MachineBasicBlock &Block, MachineBasicBlock::instr_iterator It, AMDGPU::Waitcnt Wait, const WaitcntBrackets &ScoreBrackets) { - assert(ST); assert(isNormalMode(MaxCounter)); bool Modified = false; @@ -1811,7 +1822,7 @@ bool WaitcntGeneratorPreGFX12::createNewWaitcnt( if (AnyOutOfOrder) { // Fall back to non-expanded wait unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); - BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(Enc); + BuildMI(Block, It, DL, TII.get(AMDGPU::S_WAITCNT)).addImm(Enc); Modified = true; } else { // All counters are in-order, safe to expand @@ -1820,13 +1831,12 @@ bool WaitcntGeneratorPreGFX12::createNewWaitcnt( if (WaitCnt == ~0u) continue; - unsigned Outstanding = std::min(ScoreBrackets.getScoreUB(CT) - - ScoreBrackets.getScoreLB(CT), + unsigned Outstanding = std::min(ScoreBrackets.getOutstanding(CT), getWaitCountMax(getLimits(), CT) - 1); EmitExpandedWaitcnt(Outstanding, WaitCnt, [&](unsigned Count) { AMDGPU::Waitcnt W; getCounterRef(W, CT) = Count; - BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT)) + BuildMI(Block, It, DL, TII.get(AMDGPU::S_WAITCNT)) .addImm(AMDGPU::encodeWaitcnt(IV, W)); }); } @@ -1835,7 +1845,7 @@ bool WaitcntGeneratorPreGFX12::createNewWaitcnt( // Normal behavior: emit single combined waitcnt unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); [[maybe_unused]] auto SWaitInst = - BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(Enc); + BuildMI(Block, It, DL, TII.get(AMDGPU::S_WAITCNT)).addImm(Enc); Modified = true; LLVM_DEBUG(dbgs() << "PreGFX12::createNewWaitcnt\n"; @@ -1845,23 +1855,22 @@ bool WaitcntGeneratorPreGFX12::createNewWaitcnt( } if (Wait.hasWaitStoreCnt()) { - assert(ST->hasVscnt()); + assert(ST.hasVscnt()); if (ExpandWaitcntProfiling && Wait.StoreCnt != ~0u && !ScoreBrackets.counterOutOfOrder(STORE_CNT)) { // Only expand if counter is not out-of-order unsigned Outstanding = - std::min(ScoreBrackets.getScoreUB(STORE_CNT) - - ScoreBrackets.getScoreLB(STORE_CNT), + std::min(ScoreBrackets.getOutstanding(STORE_CNT), getWaitCountMax(getLimits(), STORE_CNT) - 1); EmitExpandedWaitcnt(Outstanding, Wait.StoreCnt, [&](unsigned Count) { - BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT_VSCNT)) + BuildMI(Block, It, DL, TII.get(AMDGPU::S_WAITCNT_VSCNT)) .addReg(AMDGPU::SGPR_NULL, RegState::Undef) .addImm(Count); }); } else { [[maybe_unused]] auto SWaitInst = - BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT_VSCNT)) + BuildMI(Block, It, DL, TII.get(AMDGPU::S_WAITCNT_VSCNT)) .addReg(AMDGPU::SGPR_NULL, RegState::Undef) .addImm(Wait.StoreCnt); Modified = true; @@ -1877,7 +1886,7 @@ bool WaitcntGeneratorPreGFX12::createNewWaitcnt( AMDGPU::Waitcnt WaitcntGeneratorPreGFX12::getAllZeroWaitcnt(bool IncludeVSCnt) const { - return AMDGPU::Waitcnt(0, 0, 0, IncludeVSCnt && ST->hasVscnt() ? 0 : ~0u); + return AMDGPU::Waitcnt(0, 0, 0, IncludeVSCnt && ST.hasVscnt() ? 0 : ~0u); } AMDGPU::Waitcnt @@ -1894,7 +1903,6 @@ WaitcntGeneratorGFX12Plus::getAllZeroWaitcnt(bool IncludeVSCnt) const { bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( WaitcntBrackets &ScoreBrackets, MachineInstr &OldWaitcntInstr, AMDGPU::Waitcnt &Wait, MachineBasicBlock::instr_iterator It) const { - assert(ST); assert(!isNormalMode(MaxCounter)); bool Modified = false; @@ -1937,7 +1945,7 @@ bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( if (Opcode == AMDGPU::S_WAIT_LOADCNT_DSCNT) { unsigned OldEnc = - TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + TII.getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); AMDGPU::Waitcnt OldWait = AMDGPU::decodeLoadcntDscnt(IV, OldEnc); if (TrySimplify) Wait = Wait.combined(OldWait); @@ -1946,7 +1954,7 @@ bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( UpdatableInstr = &CombinedLoadDsCntInstr; } else if (Opcode == AMDGPU::S_WAIT_STORECNT_DSCNT) { unsigned OldEnc = - TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + TII.getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); AMDGPU::Waitcnt OldWait = AMDGPU::decodeStorecntDscnt(IV, OldEnc); if (TrySimplify) Wait = Wait.combined(OldWait); @@ -1955,7 +1963,7 @@ bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( UpdatableInstr = &CombinedStoreDsCntInstr; } else if (Opcode == AMDGPU::S_WAITCNT_DEPCTR) { unsigned OldEnc = - TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + TII.getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); AMDGPU::Waitcnt OldWait; OldWait.VaVdst = AMDGPU::DepCtr::decodeFieldVaVdst(OldEnc); OldWait.VmVsrc = AMDGPU::DepCtr::decodeFieldVmVsrc(OldEnc); @@ -1972,7 +1980,7 @@ bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( std::optional CT = counterTypeForInstr(Opcode); assert(CT.has_value()); unsigned OldCnt = - TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + TII.getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); if (TrySimplify) addWait(Wait, CT.value(), OldCnt); else @@ -1990,11 +1998,11 @@ bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( // VM_VSRC subfields of the operand are set to the "no wait" // values. - unsigned Enc = TII->getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); + unsigned Enc = TII.getNamedOperand(II, AMDGPU::OpName::simm16)->getImm(); Enc = AMDGPU::DepCtr::encodeFieldVmVsrc(Enc, ~0u); Enc = AMDGPU::DepCtr::encodeFieldVaVdst(Enc, ~0u); - if (Enc != (unsigned)AMDGPU::DepCtr::getDefaultDepCtrEncoding(*ST)) { + if (Enc != (unsigned)AMDGPU::DepCtr::getDefaultDepCtrEncoding(ST)) { Modified |= updateOperandIfDifferent(II, AMDGPU::OpName::simm16, Enc); Modified |= promoteSoftWaitCnt(&II); } else { @@ -2132,7 +2140,7 @@ bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( // Get the encoded Depctr immediate and override the VA_VDST and VM_VSRC // subfields with the new required values. unsigned Enc = - TII->getNamedOperand(*WaitcntDepctrInstr, AMDGPU::OpName::simm16) + TII.getNamedOperand(*WaitcntDepctrInstr, AMDGPU::OpName::simm16) ->getImm(); Enc = AMDGPU::DepCtr::encodeFieldVmVsrc(Enc, Wait.VmVsrc); Enc = AMDGPU::DepCtr::encodeFieldVaVdst(Enc, Wait.VaVdst); @@ -2145,7 +2153,7 @@ bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( // If that new encoded Depctr immediate would actually still wait // for anything, update the instruction's operand. Otherwise it can // just be deleted. - if (Enc != (unsigned)AMDGPU::DepCtr::getDefaultDepCtrEncoding(*ST)) { + if (Enc != (unsigned)AMDGPU::DepCtr::getDefaultDepCtrEncoding(ST)) { Modified |= updateOperandIfDifferent(*WaitcntDepctrInstr, AMDGPU::OpName::simm16, Enc); LLVM_DEBUG(It.isEnd() ? dbgs() << "applyPreexistingWaitcnt\n" @@ -2167,7 +2175,6 @@ bool WaitcntGeneratorGFX12Plus::applyPreexistingWaitcnt( bool WaitcntGeneratorGFX12Plus::createNewWaitcnt( MachineBasicBlock &Block, MachineBasicBlock::instr_iterator It, AMDGPU::Waitcnt Wait, const WaitcntBrackets &ScoreBrackets) { - assert(ST); assert(!isNormalMode(MaxCounter)); bool Modified = false; @@ -2192,17 +2199,16 @@ bool WaitcntGeneratorGFX12Plus::createNewWaitcnt( // Skip expansion for out-of-order counters - emit normal wait instead if (ScoreBrackets.counterOutOfOrder(CT)) { - BuildMI(Block, It, DL, TII->get(instrsForExtendedCounterTypes[CT])) + BuildMI(Block, It, DL, TII.get(instrsForExtendedCounterTypes[CT])) .addImm(Count); Modified = true; continue; } - unsigned Outstanding = - std::min(ScoreBrackets.getScoreUB(CT) - ScoreBrackets.getScoreLB(CT), - getWaitCountMax(getLimits(), CT) - 1); + unsigned Outstanding = std::min(ScoreBrackets.getOutstanding(CT), + getWaitCountMax(getLimits(), CT) - 1); EmitExpandedWaitcnt(Outstanding, Count, [&](unsigned Val) { - BuildMI(Block, It, DL, TII->get(instrsForExtendedCounterTypes[CT])) + BuildMI(Block, It, DL, TII.get(instrsForExtendedCounterTypes[CT])) .addImm(Val); }); } @@ -2217,7 +2223,7 @@ bool WaitcntGeneratorGFX12Plus::createNewWaitcnt( if (Wait.LoadCnt != ~0u) { unsigned Enc = AMDGPU::encodeLoadcntDscnt(IV, Wait); - SWaitInst = BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAIT_LOADCNT_DSCNT)) + SWaitInst = BuildMI(Block, It, DL, TII.get(AMDGPU::S_WAIT_LOADCNT_DSCNT)) .addImm(Enc); Wait.LoadCnt = ~0u; @@ -2225,9 +2231,8 @@ bool WaitcntGeneratorGFX12Plus::createNewWaitcnt( } else if (Wait.StoreCnt != ~0u) { unsigned Enc = AMDGPU::encodeStorecntDscnt(IV, Wait); - SWaitInst = - BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAIT_STORECNT_DSCNT)) - .addImm(Enc); + SWaitInst = BuildMI(Block, It, DL, TII.get(AMDGPU::S_WAIT_STORECNT_DSCNT)) + .addImm(Enc); Wait.StoreCnt = ~0u; Wait.DsCnt = ~0u; @@ -2251,7 +2256,7 @@ bool WaitcntGeneratorGFX12Plus::createNewWaitcnt( continue; [[maybe_unused]] auto SWaitInst = - BuildMI(Block, It, DL, TII->get(instrsForExtendedCounterTypes[CT])) + BuildMI(Block, It, DL, TII.get(instrsForExtendedCounterTypes[CT])) .addImm(Count); Modified = true; @@ -2263,11 +2268,11 @@ bool WaitcntGeneratorGFX12Plus::createNewWaitcnt( if (Wait.hasWaitDepctr()) { assert(IsExpertMode); - unsigned Enc = AMDGPU::DepCtr::encodeFieldVmVsrc(Wait.VmVsrc, *ST); + unsigned Enc = AMDGPU::DepCtr::encodeFieldVmVsrc(Wait.VmVsrc, ST); Enc = AMDGPU::DepCtr::encodeFieldVaVdst(Enc, Wait.VaVdst); [[maybe_unused]] auto SWaitInst = - BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT_DEPCTR)).addImm(Enc); + BuildMI(Block, It, DL, TII.get(AMDGPU::S_WAITCNT_DEPCTR)).addImm(Enc); Modified = true; @@ -2332,7 +2337,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore( if (ST->hasExtendedWaitCounts() && !ScoreBrackets.hasPendingEvent(VMEM_ACCESS)) AllZeroWait.LoadCnt = ~0u; - Wait = Wait.combined(AllZeroWait); + Wait = AllZeroWait; break; } case AMDGPU::S_ENDPGM: @@ -2345,7 +2350,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore( // to send a message to explicitly release all VGPRs before the stores have // completed, but it is only safe to do this if there are no outstanding // scratch stores. - EndPgmInsts[&MI] = ScoreBrackets.getScoreRange(STORE_CNT) != 0 && + EndPgmInsts[&MI] = !ScoreBrackets.empty(STORE_CNT) && !ScoreBrackets.hasPendingEvent(SCRATCH_WRITE_ACCESS); break; } @@ -2779,7 +2784,11 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst, if (!SIInstrInfo::isLDSDMA(Inst) && FlatASCount > 1) ScoreBrackets->setPendingFlat(); } else if (SIInstrInfo::isVMEM(Inst) && - !llvm::AMDGPU::getMUBUFIsBufferInv(Inst.getOpcode())) { + (!AMDGPU::getMUBUFIsBufferInv(Inst.getOpcode()) || + Inst.getOpcode() == AMDGPU::BUFFER_WBL2)) { + // BUFFER_WBL2 is included here because unlike invalidates, has to be + // followed "S_WAITCNT vmcnt(0)" is needed after to ensure the writeback has + // completed. IsVMEMAccess = true; ScoreBrackets->updateByEvent(getVmemWaitEventType(Inst), Inst); @@ -2862,7 +2871,7 @@ bool WaitcntBrackets::merge(const WaitcntBrackets &Other) { for (auto T : inst_counter_types(Context->MaxCounter)) { // Merge event flags for this counter - const WaitEventSet &EventsForT = Context->getWaitEventMask()[T]; + const WaitEventSet &EventsForT = Context->getWaitEvents(T); const WaitEventSet OldEvents = PendingEvents & EventsForT; const WaitEventSet OtherEvents = Other.PendingEvents & EventsForT; if (!OldEvents.contains(OtherEvents)) @@ -3272,19 +3281,14 @@ SIInsertWaitcnts::getPreheaderFlushFlags(MachineLoop *ML, // Check if this register has a pending VMEM load from outside the // loop (value loaded outside and used inside). VMEMID ID = toVMEMID(RU); - bool HasPendingVMEM = - Brackets.getVMemScore(ID, LOAD_CNT) > - Brackets.getScoreLB(LOAD_CNT) || - Brackets.getVMemScore(ID, SAMPLE_CNT) > - Brackets.getScoreLB(SAMPLE_CNT) || - Brackets.getVMemScore(ID, BVH_CNT) > Brackets.getScoreLB(BVH_CNT); - if (HasPendingVMEM) + if (Brackets.hasPendingVMEM(ID, LOAD_CNT) || + Brackets.hasPendingVMEM(ID, SAMPLE_CNT) || + Brackets.hasPendingVMEM(ID, BVH_CNT)) UsesVgprLoadedOutsideVMEM = true; // Check if loaded outside the loop via DS (not VMEM/FLAT). // Only consider it a DS load if there's no pending VMEM load for // this register, since FLAT can set both counters. - if (!HasPendingVMEM && - Brackets.getVMemScore(ID, DS_CNT) > Brackets.getScoreLB(DS_CNT)) + else if (Brackets.hasPendingVMEM(ID, DS_CNT)) UsesVgprLoadedOutsideDS = true; } } @@ -3402,7 +3406,7 @@ bool SIInsertWaitcnts::run(MachineFunction &MF) { for (auto T : inst_counter_types()) ForceEmitWaitcnt[T] = false; - SmemAccessCounter = eventCounter(WCG->getWaitEventMask(), SMEM_ACCESS); + SmemAccessCounter = getCounterFromEvent(SMEM_ACCESS); BlockInfos.clear(); bool Modified = false; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 09efba485f6f8..7ad086a869bdf 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -2410,11 +2410,10 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { Register Dst = MI.getOperand(0).getReg(); Register VecReg = MI.getOperand(1).getReg(); bool IsUndef = MI.getOperand(1).isUndef(); - Register Idx = MI.getOperand(2).getReg(); Register SubReg = MI.getOperand(3).getImm(); MachineInstr *SetOn = BuildMI(MBB, MI, DL, get(AMDGPU::S_SET_GPR_IDX_ON)) - .addReg(Idx) + .add(MI.getOperand(2)) .addImm(AMDGPU::VGPRIndexMode::SRC0_ENABLE); SetOn->getOperand(3).setIsUndef(); @@ -2567,6 +2566,38 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { Op1->setImm(Op1->getImm() | SISrcMods::OP_SEL_1); break; } + + case AMDGPU::GET_STACK_BASE: + // The stack starts at offset 0 unless we need to reserve some space at the + // bottom. + if (ST.getFrameLowering()->mayReserveScratchForCWSR(*MBB.getParent())) { + // When CWSR is used in dynamic VGPR mode, the trap handler needs to save + // some of the VGPRs. The size of the required scratch space has already + // been computed by prolog epilog insertion. + const SIMachineFunctionInfo *MFI = + MBB.getParent()->getInfo(); + unsigned VGPRSize = MFI->getScratchReservedForDynamicVGPRs(); + Register DestReg = MI.getOperand(0).getReg(); + BuildMI(MBB, MI, DL, get(AMDGPU::S_GETREG_B32), DestReg) + .addImm(AMDGPU::Hwreg::HwregEncoding::encode( + AMDGPU::Hwreg::ID_HW_ID2, AMDGPU::Hwreg::OFFSET_ME_ID, 2)); + // The MicroEngine ID is 0 for the graphics queue, and 1 or 2 for compute + // (3 is unused, so we ignore it). Unfortunately, S_GETREG doesn't set + // SCC, so we need to check for 0 manually. + BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32)).addImm(0).addReg(DestReg); + // Change the implicif-def of SCC to an explicit use (but first remove + // the dead flag if present). + MI.getOperand(MI.getNumExplicitOperands()).setIsDead(false); + MI.getOperand(MI.getNumExplicitOperands()).setIsUse(); + MI.setDesc(get(AMDGPU::S_CMOVK_I32)); + MI.addOperand(MachineOperand::CreateImm(VGPRSize)); + } else { + MI.setDesc(get(AMDGPU::S_MOV_B32)); + MI.addOperand(MachineOperand::CreateImm(0)); + MI.removeOperand( + MI.getNumExplicitOperands()); // Drop implicit def of SCC. + } + break; } return true; @@ -9759,7 +9790,14 @@ unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { LiteralSize = 8; break; case AMDGPU::OPERAND_REG_IMM_INT64: - if (!Op.isImm() || !AMDGPU::isValid32BitLiteral(Op.getImm(), false)) + // A 32-bit literal is only valid when the value fits in BOTH signed + // and unsigned 32-bit ranges [0, 2^31-1], matching the MC code + // emitter's getLit64Encoding logic. This is because of the lack of + // abilility to tell signedness of the literal, therefore we need to + // be conservative and assume values outside this range require a + // 64-bit literal encoding (8 bytes). + if (!Op.isImm() || !isInt<32>(Op.getImm()) || + !isUInt<32>(Op.getImm())) LiteralSize = 8; break; } @@ -9897,6 +9935,7 @@ SIInstrInfo::getSerializableMachineMemOperandTargetFlags() const { {MONoClobber, "amdgpu-noclobber"}, {MOLastUse, "amdgpu-last-use"}, {MOCooperative, "amdgpu-cooperative"}, + {MOThreadPrivate, "amdgpu-thread-private"}, }; return ArrayRef(TargetFlags); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 05cf804d08ffc..85585cbfc628a 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -52,6 +52,11 @@ static const MachineMemOperand::Flags MOLastUse = static const MachineMemOperand::Flags MOCooperative = MachineMemOperand::MOTargetFlag3; +/// Mark the MMO of accesses to memory locations that are +/// never written to by other threads. +static const MachineMemOperand::Flags MOThreadPrivate = + MachineMemOperand::MOTargetFlag4; + /// Utility to store machine instructions worklist. struct SIInstrWorklist { SIInstrWorklist() = default; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 41074dd75b90a..d38e08d6c79a7 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1004,11 +1004,13 @@ def MFMALdScaleXForm : SDNodeXFormgetTargetConstant(New, SDLoc(N), MVT::i32); }]>; -def is_canonicalized : PatLeaf<(fAny srcvalue:$src), [{ +def fcanonicalize_canonicalized + : PatFrag<(ops node:$op), (fcanonicalize node:$op), [{ const SITargetLowering &Lowering = *static_cast(getTargetLowering()); - return Lowering.isCanonicalized(*CurDAG, Op); + return Lowering.isCanonicalized(*CurDAG, Op->getOperand(0), N->getFlags()); }]> { + // FIXME: This predicate for GlobalISel is dead code. let GISelPredicateCode = [{ const SITargetLowering *TLI = static_cast( MF.getSubtarget().getTargetLowering()); @@ -1087,6 +1089,8 @@ def VReg32OrOffClass : AsmOperandClass { def SendMsg : CustomOperand; +def WaitEvent : CustomOperand; + def Swizzle : CustomOperand; def Endpgm : CustomOperand; @@ -1200,12 +1204,12 @@ class NamedIntOperand !if(AlwaysPrint, "true", "false")#"); }"; } -class NamedBitOperand +class NamedBitOperand : CustomOperand { let PredicateMethod = "isImmTy"; let ParserMethod = "[this](OperandVector &Operands) -> ParseStatus { "# - "return parseNamedBit(\""#Id#"\", Operands, AMDGPUOperand::"#ImmTy#"); }"; + "return parseNamedBit(\""#Id#"\", Operands, AMDGPUOperand::"#ImmTy# !if(AlwaysIgnoreNegative, ", true", ", false")#"); }"; let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, "# "const MCSubtargetInfo &STI, raw_ostream &O) { "# "printNamedBit(MI, OpNo, O, \""#Id#"\"); }"; @@ -1270,8 +1274,10 @@ def R128A16 : CustomOperand; def A16 : NamedBitOperand<"a16">; def D16 : NamedBitOperand<"d16">; def LWE : NamedBitOperand<"lwe">; -def exp_compr : NamedBitOperand<"compr", "ExpCompr">; -def exp_vm : NamedBitOperand<"vm", "ExpVM">; +def exp_compr : NamedBitOperand<"compr", "ExpCompr", 1>; +def exp_vm : NamedBitOperand<"vm", "ExpVM", 1>; +def exp_done : NamedBitOperand<"done", "Done", 1>; +def exp_row_en : NamedBitOperand<"row_en", "RowEn", 1>; def FORMAT : CustomOperand; diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index d30e7fd0523a5..cde352313f86a 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -930,6 +930,7 @@ multiclass si_cs_chain_tc_dvgpr_patterns< defm : si_cs_chain_tc_dvgpr_patterns; // On GFX12, dVGPR mode is wave32-only. +let Defs = [SCC] in { def ADJCALLSTACKUP : SPseudoInstSI< (outs), (ins i32imm:$amt0, i32imm:$amt1), [(callseq_start timm:$amt0, timm:$amt1)], @@ -939,7 +940,6 @@ def ADJCALLSTACKUP : SPseudoInstSI< let hasSideEffects = 1; let usesCustomInserter = 1; let SchedRW = [WriteSALU]; - let Defs = [SCC]; } def ADJCALLSTACKDOWN : SPseudoInstSI< @@ -950,9 +950,16 @@ def ADJCALLSTACKDOWN : SPseudoInstSI< let hasSideEffects = 1; let usesCustomInserter = 1; let SchedRW = [WriteSALU]; - let Defs = [SCC]; } +// Get the offset of the base of the stack, skipping any reserved areas. +def GET_STACK_BASE : SPseudoInstSI<(outs SGPR_32:$dst), (ins), + [(set p5:$dst, (sponentry))]> { + let Size = 16; // Worst case (s_getreg, s_cmp, s_cselect + constant). + let SchedRW = [WriteSALU]; +} +} // End Defs = [SCC] + let Defs = [M0, EXEC, SCC], UseNamedOperandTable = 1 in { @@ -3580,10 +3587,7 @@ def : GCNPat< // If fcanonicalize's operand is implicitly canonicalized, we only need a copy. let AddedComplexity = 8 in { foreach vt = [f16, v2f16, f32, v2f32, f64] in { - def : GCNPat< - (fcanonicalize (vt is_canonicalized:$src)), - (COPY vt:$src) - >; + def : GCNPat<(fcanonicalize_canonicalized vt:$src), (COPY vt:$src)>; } } @@ -4830,6 +4834,23 @@ def G_AMDGPU_READANYLANE : AMDGPUGenericInstruction { let hasSideEffects = 0; } +// llvm.sponentry +def G_AMDGPU_SPONENTRY : AMDGPUGenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins); + let hasSideEffects = 0; +} + +class LoadMonitorInstruction : AMDGPUGenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins ptype1:$ptr); + let hasSideEffects = 0; + let mayLoad = 1; +} + +def G_AMDGPU_FLAT_LOAD_MONITOR : LoadMonitorInstruction; +def G_AMDGPU_GLOBAL_LOAD_MONITOR : LoadMonitorInstruction; + //============================================================================// // Dummy Instructions //============================================================================// diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp index 5b329f46930ca..0b8c71a4a2453 100644 --- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp @@ -888,9 +888,7 @@ class SILowerI1CopiesLegacy : public MachineFunctionPass { public: static char ID; - SILowerI1CopiesLegacy() : MachineFunctionPass(ID) { - initializeSILowerI1CopiesLegacyPass(*PassRegistry::getPassRegistry()); - } + SILowerI1CopiesLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp index ef384c2a1a215..4aa4186ed1fa8 100644 --- a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp @@ -53,9 +53,7 @@ class SILowerWWMCopiesLegacy : public MachineFunctionPass { public: static char ID; - SILowerWWMCopiesLegacy() : MachineFunctionPass(ID) { - initializeSILowerWWMCopiesLegacyPass(*PassRegistry::getPassRegistry()); - } + SILowerWWMCopiesLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index c819c5641dbcf..af3226d4d944c 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -692,7 +692,7 @@ convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, if (Arg.isMasked()) SA.Mask = Arg.getMask(); - A = SA; + A = std::move(SA); return true; }; diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp index 2f3ad39c75fcc..fb0c7e6c917b4 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -922,7 +922,7 @@ void SIScheduleBlockCreator::colorEndsAccordingToDependencies() { // combination of children. PendingColoring[SU->NodeNum] = NextNonReservedID++; } - CurrentColoring = PendingColoring; + CurrentColoring = std::move(PendingColoring); } diff --git a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp index c16aa3e8a0352..0daeecd5624ac 100644 --- a/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp +++ b/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp @@ -398,6 +398,10 @@ class SICacheControl { bool IsCrossAddrSpaceOrdering, Position Pos) const = 0; + /// Handle operations that are considered non-volatile. + /// See \ref isNonVolatileMemoryAccess + virtual bool handleNonVolatile(MachineInstr &MI) const { return false; } + /// Virtual destructor to allow derivations to be deleted. virtual ~SICacheControl() = default; }; @@ -555,6 +559,8 @@ class SIGfx12CacheControl final : public SICacheControl { SIAtomicAddrSpace AddrSpace) const override { return setAtomicScope(MI, Scope, AddrSpace); } + + bool handleNonVolatile(MachineInstr &MI) const override; }; class SIMemoryLegalizer final { @@ -899,6 +905,18 @@ SIMemOpAccess::getLDSDMAInfo(const MachineBasicBlock::iterator &MI) const { return constructFromMIWithMMO(MI); } +/// \returns true if \p MI has one or more MMO, and all of them are fit for +/// being marked as non-volatile. This means that either they are accessing the +/// constant address space, are accessing a known invariant memory location, or +/// that they are marked with the non-volatile metadata/MMO flag. +static bool isNonVolatileMemoryAccess(const MachineInstr &MI) { + if (MI.getNumMemOperands() == 0) + return false; + return all_of(MI.memoperands(), [&](const MachineMemOperand *MMO) { + return MMO->getFlags() & (MOThreadPrivate | MachineMemOperand::MOInvariant); + }); +} + SICacheControl::SICacheControl(const GCNSubtarget &ST) : ST(ST) { TII = ST.getInstrInfo(); IV = getIsaVersion(ST.getCPU()); @@ -2061,6 +2079,17 @@ bool SIGfx12CacheControl::insertRelease(MachineBasicBlock::iterator &MI, return Changed; } +bool SIGfx12CacheControl::handleNonVolatile(MachineInstr &MI) const { + // On GFX12.5, set the NV CPol bit. + if (!ST.hasGFX1250Insts()) + return false; + MachineOperand *CPol = TII->getNamedOperand(MI, OpName::cpol); + if (!CPol) + return false; + CPol->setImm(CPol->getImm() | AMDGPU::CPol::NV); + return true; +} + bool SIGfx12CacheControl::enableVolatileAndOrNonTemporal( MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op, bool IsVolatile, bool IsNonTemporal, bool IsLastUse = false) const { @@ -2456,20 +2485,21 @@ bool SIMemoryLegalizer::run(MachineFunction &MF) { MI = II->getIterator(); } - if (!(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic)) - continue; - - if (const auto &MOI = MOA.getLoadInfo(MI)) { - Changed |= expandLoad(*MOI, MI); - } else if (const auto &MOI = MOA.getStoreInfo(MI)) { - Changed |= expandStore(*MOI, MI); - } else if (const auto &MOI = MOA.getLDSDMAInfo(MI)) { - Changed |= expandLDSDMA(*MOI, MI); - } else if (const auto &MOI = MOA.getAtomicFenceInfo(MI)) { - Changed |= expandAtomicFence(*MOI, MI); - } else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI)) { - Changed |= expandAtomicCmpxchgOrRmw(*MOI, MI); + if (MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic) { + if (const auto &MOI = MOA.getLoadInfo(MI)) + Changed |= expandLoad(*MOI, MI); + else if (const auto &MOI = MOA.getStoreInfo(MI)) + Changed |= expandStore(*MOI, MI); + else if (const auto &MOI = MOA.getLDSDMAInfo(MI)) + Changed |= expandLDSDMA(*MOI, MI); + else if (const auto &MOI = MOA.getAtomicFenceInfo(MI)) + Changed |= expandAtomicFence(*MOI, MI); + else if (const auto &MOI = MOA.getAtomicCmpxchgOrRmwInfo(MI)) + Changed |= expandAtomicCmpxchgOrRmw(*MOI, MI); } + + if (isNonVolatileMemoryAccess(*MI)) + Changed |= CC->handleNonVolatile(*MI); } } diff --git a/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp b/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp index f9efee6d39341..9a58382e13c6e 100644 --- a/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp +++ b/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp @@ -28,19 +28,9 @@ SIModeRegisterDefaults::SIModeRegisterDefaults(const Function &F, DX10Clamp = DX10ClampAttr == "true"; } - StringRef DenormF32Attr = - F.getFnAttribute("denormal-fp-math-f32").getValueAsString(); - if (!DenormF32Attr.empty()) - FP32Denormals = parseDenormalFPAttribute(DenormF32Attr); - - StringRef DenormAttr = - F.getFnAttribute("denormal-fp-math").getValueAsString(); - if (!DenormAttr.empty()) { - DenormalMode DenormMode = parseDenormalFPAttribute(DenormAttr); - if (DenormF32Attr.empty()) - FP32Denormals = DenormMode; - FP64FP16Denormals = DenormMode; - } + DenormalFPEnv FPEnv = F.getDenormalFPEnv(); + FP64FP16Denormals = FPEnv.DefaultMode; + FP32Denormals = FPEnv.F32Mode; } using namespace AMDGPU; diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp index aa028c850bd49..47bc218ed9577 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp @@ -76,9 +76,7 @@ class SIOptimizeExecMaskingLegacy : public MachineFunctionPass { public: static char ID; - SIOptimizeExecMaskingLegacy() : MachineFunctionPass(ID) { - initializeSIOptimizeExecMaskingLegacyPass(*PassRegistry::getPassRegistry()); - } + SIOptimizeExecMaskingLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp index a9ab38bffb731..ac24f2f46b3b2 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -54,10 +54,7 @@ class SIOptimizeExecMaskingPreRALegacy : public MachineFunctionPass { public: static char ID; - SIOptimizeExecMaskingPreRALegacy() : MachineFunctionPass(ID) { - initializeSIOptimizeExecMaskingPreRALegacyPass( - *PassRegistry::getPassRegistry()); - } + SIOptimizeExecMaskingPreRALegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp b/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp index b537e44aaa9ea..787f7b30458dd 100644 --- a/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp +++ b/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp @@ -29,9 +29,7 @@ class SIPostRABundlerLegacy : public MachineFunctionPass { static char ID; public: - SIPostRABundlerLegacy() : MachineFunctionPass(ID) { - initializeSIPostRABundlerLegacyPass(*PassRegistry::getPassRegistry()); - } + SIPostRABundlerLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp index 385127cb26eea..3edc98f21a074 100644 --- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp @@ -85,9 +85,7 @@ class SIPreEmitPeepholeLegacy : public MachineFunctionPass { public: static char ID; - SIPreEmitPeepholeLegacy() : MachineFunctionPass(ID) { - initializeSIPreEmitPeepholeLegacyPass(*PassRegistry::getPassRegistry()); - } + SIPreEmitPeepholeLegacy() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override { return SIPreEmitPeephole().run(MF); diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 96c2f6530fe4c..ee461575b509f 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1549,7 +1549,10 @@ void SIRegisterInfo::buildSpillLoadStore( int64_t Offset = InstOffset + MFI.getObjectOffset(Index); int64_t MaterializedOffset = Offset; - int64_t MaxOffset = Offset + Size + RemSize - EltSize; + // Maxoffset is the starting offset for the last chunk to be spilled. + // In case of non-zero remainder element, max offset will be the + // last address(offset + Size) after spilling all the EltSize chunks. + int64_t MaxOffset = Offset + Size - (RemSize ? 0 : EltSize); int64_t ScratchOffsetRegDelta = 0; if (IsFlat && EltSize > 4) { @@ -1836,10 +1839,12 @@ void SIRegisterInfo::buildSpillLoadStore( IsKill = false; } + // Create the MMO, additional set the NonVolatile flag as scratch memory + // used for spills will not be used outside the thread. MachinePointerInfo PInfo = BasePtrInfo.getWithOffset(RegOffset); - MachineMemOperand *NewMMO = - MF->getMachineMemOperand(PInfo, MMO->getFlags(), RemEltSize, - commonAlignment(Alignment, RegOffset)); + MachineMemOperand *NewMMO = MF->getMachineMemOperand( + PInfo, MMO->getFlags() | MOThreadPrivate, RemEltSize, + commonAlignment(Alignment, RegOffset)); auto MIB = BuildMI(MBB, MI, DL, *Desc) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 2e2916f68f584..9d1a9eae75020 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -107,9 +107,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo { // Stack access is very expensive. CSRs are also the high registers, and we // want to minimize the number of used registers. - unsigned getCSRFirstUseCost() const override { - return 100; - } + unsigned getCSRCost() const override { return 100; } // When building a block VGPR load, we only really transfer a subset of the // registers in the block, based on a mask. Liveness analysis is not aware of diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 5b32bd0b72a59..14ed778f44f3a 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -909,9 +909,21 @@ bool SIShrinkInstructions::run(MachineFunction &MF) { } } + // Shrink scalar logic operations. + if (MI.getOpcode() == AMDGPU::S_AND_B32 || + MI.getOpcode() == AMDGPU::S_OR_B32 || + MI.getOpcode() == AMDGPU::S_XOR_B32) { + ChangeKind CK = shrinkScalarLogicOp(MI); + if (CK == ChangeKind::UpdateHint) + continue; + Changed |= (CK == ChangeKind::UpdateInst); + } + // Try to use S_ADDK_I32 and S_MULK_I32. if (MI.getOpcode() == AMDGPU::S_ADD_I32 || - MI.getOpcode() == AMDGPU::S_MUL_I32) { + MI.getOpcode() == AMDGPU::S_MUL_I32 || + (MI.getOpcode() == AMDGPU::S_OR_B32 && + MI.getFlag(MachineInstr::MIFlag::Disjoint))) { const MachineOperand *Dest = &MI.getOperand(0); MachineOperand *Src0 = &MI.getOperand(1); MachineOperand *Src1 = &MI.getOperand(2); @@ -931,12 +943,11 @@ bool SIShrinkInstructions::run(MachineFunction &MF) { MRI->setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); continue; } - if (Src0->isReg() && Src0->getReg() == Dest->getReg()) { if (Src1->isImm() && isKImmOperand(*Src1)) { - unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ? - AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32; - + unsigned Opc = (MI.getOpcode() == AMDGPU::S_MUL_I32) + ? AMDGPU::S_MULK_I32 + : AMDGPU::S_ADDK_I32; Src1->setImm(SignExtend64(Src1->getImm(), 32)); MI.setDesc(TII->get(Opc)); MI.tieOperands(0, 1); @@ -974,16 +985,6 @@ bool SIShrinkInstructions::run(MachineFunction &MF) { continue; } - // Shrink scalar logic operations. - if (MI.getOpcode() == AMDGPU::S_AND_B32 || - MI.getOpcode() == AMDGPU::S_OR_B32 || - MI.getOpcode() == AMDGPU::S_XOR_B32) { - ChangeKind CK = shrinkScalarLogicOp(MI); - if (CK == ChangeKind::UpdateHint) - continue; - Changed |= (CK == ChangeKind::UpdateInst); - } - if (IsPostRA && TII->isMIMG(MI.getOpcode()) && ST->getGeneration() >= AMDGPUSubtarget::GFX10) { Changed |= shrinkMIMG(MI); diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index c74db384a49bb..2a13acb6b0ceb 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1650,23 +1650,34 @@ def S_BARRIER_WAIT : SOPP_Pseudo <"s_barrier_wait", (ins i16imm:$simm16), "$simm let isConvergent = 1; } + +let SchedRW = [WriteBarrier], isConvergent = 1 in { + let SubtargetPredicate = isGFX12Only in def S_BARRIER_LEAVE : SOPP_Pseudo <"s_barrier_leave", (ins), "", [(int_amdgcn_s_barrier_leave (i16 srcvalue))] > { - let SchedRW = [WriteBarrier]; - let simm16 = 0; - let fixed_imm = 1; - let isConvergent = 1; - let Defs = [SCC]; + let simm16 = 0; + let fixed_imm = 1; + let Defs = [SCC]; + } + + let SubtargetPredicate = HasSBarrierLeaveImm in + def S_BARRIER_LEAVE_IMM : SOPP_Pseudo <"s_barrier_leave", + (ins i16imm:$simm16), "$simm16", [(int_amdgcn_s_barrier_leave timm:$simm16)]>; } def S_WAKEUP : SOPP_Pseudo <"s_wakeup", (ins) > { - let SubtargetPredicate = isGFX8Plus; + let SubtargetPredicate = isGFX8GFX9GFX10GFX11GFX12; let simm16 = 0; let fixed_imm = 1; let mayLoad = 1; let mayStore = 1; } +let SubtargetPredicate = HasSWakeupImm in { + def S_WAKEUP_imm : SOPP_Pseudo <"s_wakeup", + (ins i16imm:$simm16), "$simm16">; +} // End SubtargetPredicate = HasSWakeupImm + let SubtargetPredicate = isNotGFX1250Plus in { def S_WAITCNT : SOPP_Pseudo <"s_waitcnt" , (ins SWaitCnt:$simm16), "$simm16", [(int_amdgcn_s_waitcnt timm:$simm16)]>; @@ -1823,8 +1834,8 @@ let SubtargetPredicate = isGFX10Plus in { let SubtargetPredicate = isGFX11Plus in { let OtherPredicates = [HasExportInsts] in - def S_WAIT_EVENT : SOPP_Pseudo<"s_wait_event", (ins s16imm:$simm16), - "$simm16"> { + def S_WAIT_EVENT : SOPP_Pseudo<"s_wait_event", (ins WaitEvent:$simm16), + "$simm16", [(int_amdgcn_s_wait_event timm:$simm16)]> { let hasSideEffects = 1; } def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins SDelayALU:$simm16), @@ -1947,9 +1958,7 @@ def : GCNPat< (S_SEXT_I32_I16 $src) >; -let SubtargetPredicate = isNotGFX12Plus in - def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 0))>; -let SubtargetPredicate = isGFX12Plus in +let SubtargetPredicate = isGFX11Plus in def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 2))>; // The first 10 bits of the mode register are the core FP mode on all @@ -2670,6 +2679,51 @@ defm S_BFE_U64 : SOP2_Real_gfx6_gfx7_gfx10_gfx13<0x029>; defm S_BFE_I64 : SOP2_Real_gfx6_gfx7_gfx10_gfx13<0x02a>; defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx13<0x02c>; + +//===----------------------------------------------------------------------===// +// SOPK - GFX10 Only +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real32_gfx10 op> { + defvar ps = !cast(NAME); + def _gfx10 : SOPK_Real32, + Select; +} + +multiclass SOPK_Real64_gfx10 op> { + defvar ps = !cast(NAME); + def _gfx10 : SOPK_Real64, + Select; +} + +defm S_WAITCNT_VSCNT : SOPK_Real32_gfx10<0x017>; +defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>; +defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>; +defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>; +defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx10<0x01b>; +defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>; + +//===----------------------------------------------------------------------===// +// SOPK - GFX11 Only +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real32_gfx11 op> { + def _gfx11 : SOPK_Real32(NAME)>, + Select(NAME).PseudoInstr>; +} + +multiclass SOPK_Real64_gfx11 op> { + def _gfx11 : SOPK_Real64(NAME)>, + Select(NAME).PseudoInstr>; +} + +defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx11<0x016>; +defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx11<0x017>; +defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11<0x018>; +defm S_WAITCNT_VMCNT : SOPK_Real32_gfx11<0x019>; +defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx11<0x01a>; +defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>; + //===----------------------------------------------------------------------===// // SOPK - GFX11, GFX12. //===----------------------------------------------------------------------===// @@ -2684,21 +2738,11 @@ multiclass SOPK_Real32_gfx12 op, string name = !tolower(NAME)> { } } -multiclass SOPK_Real32_gfx11 op> { - def _gfx11 : SOPK_Real32(NAME)>, - Select(NAME).PseudoInstr>; -} - multiclass SOPK_Real64_gfx12 op> { def _gfx12 : SOPK_Real64(NAME)>, Select(NAME).PseudoInstr>; } -multiclass SOPK_Real64_gfx11 op> { - def _gfx11 : SOPK_Real64(NAME)>, - Select(NAME).PseudoInstr>; -} - multiclass SOPK_Real32_gfx11_gfx12 op> : SOPK_Real32_gfx11, SOPK_Real32_gfx12; @@ -2720,43 +2764,39 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>; let OtherPredicates = [isNotGFX1250Plus] in defm S_CALL_B64 : SOPK_Real32_gfx11_gfx12<0x014>; defm S_CALL_B64 : SOPK_Real32_gfx1250<0x014, "s_call_i64">; -defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx11<0x016>; -defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx11<0x017>; -defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11<0x018>; -defm S_WAITCNT_VMCNT : SOPK_Real32_gfx11<0x019>; -defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx11<0x01a>; -defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>; //===----------------------------------------------------------------------===// -// SOPK - GFX10. +// SOPK - GFX10, GFX11, GFX12, GFX13. //===----------------------------------------------------------------------===// -multiclass SOPK_Real32_gfx10 op> { +multiclass SOPK_Real32_gfx13 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); - def _gfx10 : SOPK_Real32, - Select; + def _gfx13 : SOPK_Real32, + Select; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias, Requires<[isGFX13Only]>; } -multiclass SOPK_Real64_gfx10 op> { +multiclass SOPK_Real64_gfx13 op> { defvar ps = !cast(NAME); - def _gfx10 : SOPK_Real64, - Select; + def _gfx13 : SOPK_Real64, + Select; } -multiclass SOPK_Real32_gfx10_gfx11 op> : - SOPK_Real32_gfx10, SOPK_Real32_gfx11; +multiclass SOPK_Real32_gfx10_gfx11_gfx12_gfx13 op> : + SOPK_Real32_gfx10, SOPK_Real32_gfx11, SOPK_Real32_gfx12, + SOPK_Real32_gfx13; -multiclass SOPK_Real32_gfx10_gfx11_gfx12 op> : - SOPK_Real32_gfx10, SOPK_Real32_gfx11_gfx12; +defm S_VERSION : SOPK_Real32_gfx10_gfx11_gfx12_gfx13<0x001>; -defm S_VERSION : SOPK_Real32_gfx10_gfx11_gfx12<0x001>; -defm S_CALL_B64 : SOPK_Real32_gfx10<0x016>; -defm S_WAITCNT_VSCNT : SOPK_Real32_gfx10<0x017>; -defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>; -defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>; -defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>; -defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx10<0x01b>; -defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>; +//===----------------------------------------------------------------------===// +// SOPK - GFX10, GFX13. +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real32_gfx10_Renamed_gfx13 op, string gfx13_name> : + SOPK_Real32_gfx10, SOPK_Real32_gfx13; + +defm S_CALL_B64 : SOPK_Real32_gfx10_Renamed_gfx13<0x016, "s_call_i64">; //===----------------------------------------------------------------------===// // SOPK - GFX6, GFX7. @@ -2768,32 +2808,15 @@ multiclass SOPK_Real32_gfx6_gfx7 op> { Select_gfx6_gfx7; } -multiclass SOPK_Real64_gfx6_gfx7 op> { - defvar ps = !cast(NAME); - def _gfx6_gfx7 : SOPK_Real64, - Select_gfx6_gfx7; -} - -multiclass SOPK_Real32_gfx6_gfx7_gfx10 op> : - SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10; +defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>; -multiclass SOPK_Real64_gfx6_gfx7_gfx10 op> : - SOPK_Real64_gfx6_gfx7, SOPK_Real64_gfx10; +//===----------------------------------------------------------------------===// +// SOPK - GFX6, GFX7, GFX10, GFX11. +//===----------------------------------------------------------------------===// multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11 op> : - SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10_gfx11; - -multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12 op> : - SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10_gfx11_gfx12; - -multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12 op, string gfx12_name> : - SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10, SOPK_Real32_gfx11, - SOPK_Real32_gfx12; + SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10, SOPK_Real32_gfx11; -defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>; - -defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x000>; -defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x002>; defm S_CMPK_EQ_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x003>; defm S_CMPK_LG_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x004>; defm S_CMPK_GT_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x005>; @@ -2806,11 +2829,71 @@ defm S_CMPK_GT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00b>; defm S_CMPK_GE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00c>; defm S_CMPK_LT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00d>; defm S_CMPK_LE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00e>; -defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x00f, "s_addk_co_i32">; -defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x010>; -defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x012>; -defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x013>; -defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>; + +//===----------------------------------------------------------------------===// +// SOPK - GFX6, GFX7, GFX10, GFX13. +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real64_gfx6_gfx7 op> { + defvar ps = !cast(NAME); + def _gfx6_gfx7 : SOPK_Real64, + Select_gfx6_gfx7; +} + +multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx13 op> : + SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10, SOPK_Real32_gfx13; + +multiclass SOPK_Real64_gfx6_gfx7_gfx10_gfx13 op> : + SOPK_Real64_gfx6_gfx7, SOPK_Real64_gfx10, SOPK_Real64_gfx13; + +defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx13<0x012>; +defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx13<0x013>; +defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10_gfx13<0x015>; + +//===----------------------------------------------------------------------===// +// SOPK - GFX6, GFX7, GFX10, GFX11, GFX12, GFX13. +//===----------------------------------------------------------------------===// + +multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13 op> : + SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10, SOPK_Real32_gfx11, + SOPK_Real32_gfx12, SOPK_Real32_gfx13; + +multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12_gfx13 op, string gfx12_gfx13_name> : + SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10, SOPK_Real32_gfx11, + SOPK_Real32_gfx12, SOPK_Real32_gfx13; + +defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<0x000>; +defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<0x002>; +defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12_gfx13<0x00f, "s_addk_co_i32">; +defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12_gfx13<0x010>; + + +//===----------------------------------------------------------------------===// +// SOPP - GFX13 only +//===----------------------------------------------------------------------===// + +multiclass SOPP_Real_32_gfx13 op, string name = !cast(NAME).Mnemonic, bit compat_alias = 1> { + defvar ps = !cast(NAME); + def _gfx13 : SOPP_Real_32, + Select, + SOPPRelaxTable<0, ps.KeyName, "_gfx13">; + if !and(compat_alias, !ne(ps.Mnemonic, name)) then + def : MnemonicAlias, Requires<[isGFX13Only]>; +} + +multiclass SOPP_Real_64_gfx13 op> { + defvar ps = !cast(NAME); + def _gfx13 : SOPP_Real_64, + Select, + SOPPRelaxTable<1, ps.KeyName, "_gfx13">; +} + +defm S_WAKEUP_imm : SOPP_Real_32_gfx13<0x003>; +defm S_BARRIER_WAIT : SOPP_Real_32_gfx13<0x2b>; +defm S_MONITOR_SLEEP : SOPP_Real_32_gfx13<0x2c>; +defm S_DELAY_ALU : SOPP_Real_32_gfx13<0x2e>; +defm S_WAIT_EVENT : SOPP_Real_32_gfx13<0x2f>; +defm S_BARRIER_LEAVE_IMM : SOPP_Real_32_gfx13<0x31>; //===----------------------------------------------------------------------===// // SOPP - GFX12 only. @@ -2822,36 +2905,24 @@ multiclass SOPP_Real_32_gfx12 op, string name = !tolower(NAME)> { Select; if !ne(ps.Mnemonic, name) then def : AMDGPUMnemonicAlias { - let AssemblerPredicate = isGFX12Plus; + let AssemblerPredicate = isGFX12Only; } } +multiclass SOPP_Real_64_gfx12 op> { + def _gfx12 : SOPP_Real_64(NAME), !cast(NAME).Mnemonic>, + Select(NAME).PseudoInstr>, + SOPPRelaxTable<1, !cast(NAME).KeyName, "_gfx12">; +} + defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>; defm S_BARRIER_LEAVE : SOPP_Real_32_gfx12<0x015>; -defm S_WAIT_LOADCNT : SOPP_Real_32_gfx12<0x040>; -defm S_WAIT_STORECNT : SOPP_Real_32_gfx12<0x041>; -defm S_WAIT_SAMPLECNT : SOPP_Real_32_gfx12<0x042>; defm S_WAIT_BVHCNT : SOPP_Real_32_gfx12<0x043>; -defm S_WAIT_EXPCNT : SOPP_Real_32_gfx12<0x044>; -defm S_WAIT_DSCNT : SOPP_Real_32_gfx12<0x046>; -defm S_WAIT_KMCNT : SOPP_Real_32_gfx12<0x047>; -defm S_WAIT_LOADCNT_DSCNT : SOPP_Real_32_gfx12<0x048>; -defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>; //===----------------------------------------------------------------------===// -// SOPP - GFX1250 only. -//===----------------------------------------------------------------------===// -defm S_SET_VGPR_MSB : SOPP_Real_32_gfx12<0x006>; -defm S_SETPRIO_INC_WG : SOPP_Real_32_gfx12<0x03e>; -defm S_WAIT_XCNT : SOPP_Real_32_gfx12<0x045>; -defm S_WAIT_ASYNCCNT : SOPP_Real_32_gfx12<0x04a>; -defm S_WAIT_TENSORCNT : SOPP_Real_32_gfx12<0x04b>; - -//===----------------------------------------------------------------------===// -// SOPP - GFX11, GFX12. +// SOPP - GFX11 only. //===----------------------------------------------------------------------===// - multiclass SOPP_Real_32_gfx11 op, string name = !tolower(NAME)> { defvar ps = !cast(NAME); def _gfx11 : SOPP_Real_32, @@ -2863,94 +2934,91 @@ multiclass SOPP_Real_32_gfx11 op, string name = !tolower(NAME)> { } } -multiclass SOPP_Real_64_gfx12 op> { - def _gfx12 : SOPP_Real_64(NAME), !cast(NAME).Mnemonic>, - Select(NAME).PseudoInstr>, - SOPPRelaxTable<1, !cast(NAME).KeyName, "_gfx12">; -} - multiclass SOPP_Real_64_gfx11 op> { def _gfx11 : SOPP_Real_64(NAME), !cast(NAME).Mnemonic>, Select(NAME).PseudoInstr>, SOPPRelaxTable<1, !cast(NAME).KeyName, "_gfx11">; } -multiclass SOPP_Real_32_gfx11_gfx12 op> : - SOPP_Real_32_gfx11, SOPP_Real_32_gfx12; - -multiclass SOPP_Real_32_gfx11_Renamed_gfx12 op, string gfx12_name> : - SOPP_Real_32_gfx11, SOPP_Real_32_gfx12; - -multiclass SOPP_Real_With_Relaxation_gfx12 op> { - defm "" : SOPP_Real_32_gfx12; - let isCodeGenOnly = 1 in - defm _pad_s_nop : SOPP_Real_64_gfx12; -} - multiclass SOPP_Real_With_Relaxation_gfx11 op> { defm "" : SOPP_Real_32_gfx11; let isCodeGenOnly = 1 in defm _pad_s_nop : SOPP_Real_64_gfx11; } -multiclass SOPP_Real_With_Relaxation_gfx11_gfx12op> : - SOPP_Real_With_Relaxation_gfx11, SOPP_Real_With_Relaxation_gfx12; - -defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>; -defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>; -defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>; defm S_INST_PREFETCH : SOPP_Real_32_gfx11<0x004, "s_set_inst_prefetch_distance">; -defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>; -defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>; -defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11_Renamed_gfx12<0x008, "s_wait_alu">; -defm S_WAITCNT : SOPP_Real_32_gfx11_gfx12<0x009>; -defm S_WAIT_IDLE : SOPP_Real_32_gfx11_gfx12<0x00a>; -defm S_WAIT_EVENT : SOPP_Real_32_gfx11_gfx12<0x00b>; -defm S_TRAP : SOPP_Real_32_gfx11_gfx12<0x010>; -defm S_ROUND_MODE : SOPP_Real_32_gfx11_gfx12<0x011>; -defm S_DENORM_MODE : SOPP_Real_32_gfx11_gfx12<0x012>; -defm S_BRANCH : SOPP_Real_With_Relaxation_gfx11_gfx12<0x020>; -defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x021>; -defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x022>; -defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x023>; -defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x024>; -defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x025>; -defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x026>; defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx11<0x027>; defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx11<0x028>; defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx11<0x029>; defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx11<0x02a>; -defm S_ENDPGM : SOPP_Real_32_gfx11_gfx12<0x030>; -defm S_ENDPGM_SAVED : SOPP_Real_32_gfx11_gfx12<0x031>; defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx11<0x032>; -defm S_WAKEUP : SOPP_Real_32_gfx11_gfx12<0x034>; -defm S_SETPRIO : SOPP_Real_32_gfx11_gfx12<0x035>; -defm S_SENDMSG : SOPP_Real_32_gfx11_gfx12<0x036>; -defm S_SENDMSGHALT : SOPP_Real_32_gfx11_gfx12<0x037>; -defm S_INCPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x038>; -defm S_DECPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x039>; -defm S_TTRACEDATA : SOPP_Real_32_gfx11_gfx12<0x03a>; -defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx11_gfx12<0x03b>; -defm S_ICACHE_INV : SOPP_Real_32_gfx11_gfx12<0x03c>; - defm S_BARRIER : SOPP_Real_32_gfx11<0x03d>; //===----------------------------------------------------------------------===// -// SOPP - GFX1250. +// SOPP - GFX10 only. //===----------------------------------------------------------------------===// -defm S_MONITOR_SLEEP : SOPP_Real_32_gfx12<0x004>; +multiclass SOPP_Real_32_gfx10 op> { + defvar ps = !cast(NAME); + def _gfx10 : SOPP_Real_32, + Select, + SOPPRelaxTable<0, ps.KeyName, "_gfx10">; +} + +defm S_INST_PREFETCH : SOPP_Real_32_gfx10<0x020>; //===----------------------------------------------------------------------===// -// SOPP - GFX6, GFX7, GFX8, GFX9, GFX10 +// SOPP - GFX12, GFX13. //===----------------------------------------------------------------------===// -multiclass SOPP_Real_32_gfx6_gfx7 op> { - defvar ps = !cast(NAME); - def _gfx6_gfx7 : SOPP_Real_32(NAME).Mnemonic>, - Select_gfx6_gfx7, - SOPPRelaxTable<0, ps.KeyName, "_gfx6_gfx7">; -} +multiclass SOPP_Real_32_gfx12_gfx13 op> : + SOPP_Real_32_gfx12, SOPP_Real_32_gfx13; + +defm S_WAIT_LOADCNT : SOPP_Real_32_gfx12_gfx13<0x040>; +defm S_WAIT_STORECNT : SOPP_Real_32_gfx12_gfx13<0x041>; +defm S_WAIT_SAMPLECNT : SOPP_Real_32_gfx12_gfx13<0x042>; +defm S_WAIT_EXPCNT : SOPP_Real_32_gfx12_gfx13<0x044>; +defm S_WAIT_DSCNT : SOPP_Real_32_gfx12_gfx13<0x046>; +defm S_WAIT_KMCNT : SOPP_Real_32_gfx12_gfx13<0x047>; +defm S_WAIT_LOADCNT_DSCNT : SOPP_Real_32_gfx12_gfx13<0x048>; +defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12_gfx13<0x049>; + +//===----------------------------------------------------------------------===// +// SOPP - GFX1250 only. +//===----------------------------------------------------------------------===// + +defm S_MONITOR_SLEEP : SOPP_Real_32_gfx12<0x004>; +defm S_SET_VGPR_MSB : SOPP_Real_32_gfx12<0x006>; +defm S_WAIT_XCNT : SOPP_Real_32_gfx12<0x045>; + +//===----------------------------------------------------------------------===// +// SOPP - GFX1250, GFX13 +//===----------------------------------------------------------------------===// + +defm S_SETPRIO_INC_WG : SOPP_Real_32_gfx12_gfx13<0x03e>; +defm S_WAIT_ASYNCCNT : SOPP_Real_32_gfx12_gfx13<0x04a>; +defm S_WAIT_TENSORCNT : SOPP_Real_32_gfx12_gfx13<0x04b>; + +//===----------------------------------------------------------------------===// +// SOPP - GFX10, GFX13 +//===----------------------------------------------------------------------===// + +multiclass SOPP_Real_32_gfx10_gfx13 op> : + SOPP_Real_32_gfx10, SOPP_Real_32_gfx13; + +multiclass SOPP_Real_32_gfx10_Renamed_gfx13 op, string gfx13_name> : + SOPP_Real_32_gfx10, SOPP_Real_32_gfx13; + +defm S_CLAUSE : SOPP_Real_32_gfx10_gfx13<0x021>; +defm S_WAIT_IDLE : SOPP_Real_32_gfx10_gfx13<0x022>; +defm S_ROUND_MODE : SOPP_Real_32_gfx10_gfx13<0x024>; +defm S_DENORM_MODE : SOPP_Real_32_gfx10_gfx13<0x025>; +defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx10_gfx13<0x028>; +defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx10_Renamed_gfx13<0x023, "s_wait_alu">; + +//===----------------------------------------------------------------------===// +// SOPP - GFX8, GFX9. +//===----------------------------------------------------------------------===// multiclass SOPP_Real_32_gfx8_gfx9 op> { defvar ps = !cast(NAME); @@ -2959,27 +3027,46 @@ multiclass SOPP_Real_32_gfx8_gfx9 op> { SOPPRelaxTable<0, ps.KeyName, "_vi">; } -multiclass SOPP_Real_32_gfx10 op> { +defm S_SET_GPR_IDX_OFF : SOPP_Real_32_gfx8_gfx9<0x01c>; +defm S_SET_GPR_IDX_MODE : SOPP_Real_32_gfx8_gfx9<0x01d>; + +//===----------------------------------------------------------------------===// +// SOPP - GFX6, GFX7, GFX8, GFX9, GFX10. +//===----------------------------------------------------------------------===// + +multiclass SOPP_Real_32_gfx6_gfx7 op> { defvar ps = !cast(NAME); - def _gfx10 : SOPP_Real_32, - Select, - SOPPRelaxTable<0, ps.KeyName, "_gfx10">; + def _gfx6_gfx7 : SOPP_Real_32(NAME).Mnemonic>, + Select_gfx6_gfx7, + SOPPRelaxTable<0, ps.KeyName, "_gfx6_gfx7">; } -multiclass SOPP_Real_32_gfx8_gfx9_gfx10 op> : - SOPP_Real_32_gfx8_gfx9, SOPP_Real_32_gfx10; - multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9 op> : SOPP_Real_32_gfx6_gfx7, SOPP_Real_32_gfx8_gfx9; multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10 op> : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9, SOPP_Real_32_gfx10; -multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12 op> : - SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10, SOPP_Real_32_gfx11_gfx12; +defm S_BARRIER : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00a>; +defm S_WAITCNT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00c>; + +//===----------------------------------------------------------------------===// +// SOPP - GFX6, GFX7, GFX8, GFX9, GFX10, GFX11, GFX12, GFX13. +//===----------------------------------------------------------------------===// + +multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13 op> : + SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10, SOPP_Real_32_gfx11, + SOPP_Real_32_gfx12, SOPP_Real_32_gfx13; -multiclass SOPP_Real_32_gfx10_gfx11_gfx12 op> : - SOPP_Real_32_gfx10, SOPP_Real_32_gfx11_gfx12; +defm S_NOP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x000>; + +//===----------------------------------------------------------------------===// +// SOPP - GFX6, GFX7, GFX8, GFX9, GFX10, GFX13. +//===----------------------------------------------------------------------===// + +multiclass SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13 op> : + SOPP_Real_32_gfx6_gfx7_gfx8_gfx9, SOPP_Real_32_gfx10, + SOPP_Real_32_gfx13; //64 bit encodings, for Relaxation multiclass SOPP_Real_64_gfx6_gfx7 op> { @@ -3006,6 +3093,44 @@ multiclass SOPP_Real_64_gfx10 op> { multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9 op> : SOPP_Real_64_gfx6_gfx7, SOPP_Real_64_gfx8_gfx9; +multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13 op> : + SOPP_Real_64_gfx6_gfx7_gfx8_gfx9, SOPP_Real_64_gfx10, + SOPP_Real_64_gfx13; + +multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13 op> { + defm "" : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13; + let isCodeGenOnly = 1 in + defm _pad_s_nop : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13; +} + +defm S_ENDPGM : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x001>; +defm S_SETHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x00d>; +defm S_SETKILL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x00b>; +defm S_SLEEP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x00e>; +defm S_SETPRIO : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x00f>; +defm S_SENDMSG : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x010>; +defm S_SENDMSGHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x011>; +defm S_TRAP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x012>; +defm S_ICACHE_INV : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x013>; +defm S_INCPERFLEVEL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x014>; +defm S_DECPERFLEVEL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x015>; +defm S_TTRACEDATA : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x016>; +defm S_ENDPGM_SAVED : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x01B>; + +let isBranch = 1 in { +defm S_BRANCH : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x002>; +defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x004>; +defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x005>; +defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x006>; +defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x007>; +defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x008>; +defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10_gfx13<0x009>; +} + +//===----------------------------------------------------------------------===// +// SOPP - GFX6, GFX7, GFX8, GFX9, GFX10. +//===----------------------------------------------------------------------===// + multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10 op> : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9, SOPP_Real_64_gfx10; @@ -3016,49 +3141,84 @@ multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10 op> { defm _pad_s_nop : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10; } -defm S_NOP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x000>; -defm S_ENDPGM : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x001>; -defm S_WAKEUP : SOPP_Real_32_gfx8_gfx9_gfx10<0x003>; -defm S_BARRIER : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00a>; -defm S_WAITCNT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00c>; -defm S_SETHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00d>; -defm S_SETKILL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00b>; -defm S_SLEEP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00e>; -defm S_SETPRIO : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00f>; -defm S_SENDMSG : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x010>; -defm S_SENDMSGHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x011>; -defm S_TRAP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x012>; -defm S_ICACHE_INV : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x013>; -defm S_INCPERFLEVEL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x014>; -defm S_DECPERFLEVEL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x015>; -defm S_TTRACEDATA : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x016>; -defm S_ENDPGM_SAVED : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x01B>; -defm S_SET_GPR_IDX_OFF : SOPP_Real_32_gfx8_gfx9<0x01c>; -defm S_SET_GPR_IDX_MODE : SOPP_Real_32_gfx8_gfx9<0x01d>; -defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx8_gfx9_gfx10<0x01e>; -defm S_CODE_END : SOPP_Real_32_gfx10_gfx11_gfx12<0x01f>; -defm S_INST_PREFETCH : SOPP_Real_32_gfx10<0x020>; -defm S_CLAUSE : SOPP_Real_32_gfx10<0x021>; -defm S_WAIT_IDLE : SOPP_Real_32_gfx10<0x022>; -defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx10<0x023>; -defm S_ROUND_MODE : SOPP_Real_32_gfx10<0x024>; -defm S_DENORM_MODE : SOPP_Real_32_gfx10<0x025>; -defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx10<0x028>; - let isBranch = 1 in { -defm S_BRANCH : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x002>; -defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x004>; -defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x005>; -defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x006>; -defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x007>; -defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x008>; -defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x009>; defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x017>; defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x018>; defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x019>; defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x01A>; } +//===----------------------------------------------------------------------===// +// SOPP - GFX10, GFX11, GFX12, GFX13. +//===----------------------------------------------------------------------===// + +multiclass SOPP_Real_32_gfx10_gfx11_gfx12_gfx13 op> : + SOPP_Real_32_gfx10, SOPP_Real_32_gfx11, SOPP_Real_32_gfx12, + SOPP_Real_32_gfx13; + +defm S_CODE_END : SOPP_Real_32_gfx10_gfx11_gfx12_gfx13<0x01f>; + +//===----------------------------------------------------------------------===// +// SOPP - GFX11, GFX12. +//===----------------------------------------------------------------------===// + +multiclass SOPP_Real_32_gfx11_gfx12 op> : + SOPP_Real_32_gfx11, SOPP_Real_32_gfx12; + +multiclass SOPP_Real_32_gfx11_Renamed_gfx12 op, string gfx12_name> : + SOPP_Real_32_gfx11, SOPP_Real_32_gfx12; + +multiclass SOPP_Real_With_Relaxation_gfx12 op> { + defm "" : SOPP_Real_32_gfx12; + let isCodeGenOnly = 1 in + defm _pad_s_nop : SOPP_Real_64_gfx12; +} + +multiclass SOPP_Real_With_Relaxation_gfx11_gfx12op> : + SOPP_Real_With_Relaxation_gfx11, SOPP_Real_With_Relaxation_gfx12; + +defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>; +defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>; +defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>; +defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>; +defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>; +defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11_Renamed_gfx12<0x008, "s_wait_alu">; +defm S_WAITCNT : SOPP_Real_32_gfx11_gfx12<0x009>; +defm S_WAIT_IDLE : SOPP_Real_32_gfx11_gfx12<0x00a>; +defm S_WAIT_EVENT : SOPP_Real_32_gfx11_gfx12<0x00b>; +defm S_TRAP : SOPP_Real_32_gfx11_gfx12<0x010>; +defm S_ROUND_MODE : SOPP_Real_32_gfx11_gfx12<0x011>; +defm S_DENORM_MODE : SOPP_Real_32_gfx11_gfx12<0x012>; +defm S_BRANCH : SOPP_Real_With_Relaxation_gfx11_gfx12<0x020>; +defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x021>; +defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x022>; +defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x023>; +defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x024>; +defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x025>; +defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x026>; +defm S_ENDPGM : SOPP_Real_32_gfx11_gfx12<0x030>; +defm S_ENDPGM_SAVED : SOPP_Real_32_gfx11_gfx12<0x031>; +defm S_WAKEUP : SOPP_Real_32_gfx11_gfx12<0x034>; +defm S_SETPRIO : SOPP_Real_32_gfx11_gfx12<0x035>; +defm S_SENDMSG : SOPP_Real_32_gfx11_gfx12<0x036>; +defm S_SENDMSGHALT : SOPP_Real_32_gfx11_gfx12<0x037>; +defm S_INCPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x038>; +defm S_DECPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x039>; +defm S_TTRACEDATA : SOPP_Real_32_gfx11_gfx12<0x03a>; +defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx11_gfx12<0x03b>; +defm S_ICACHE_INV : SOPP_Real_32_gfx11_gfx12<0x03c>; + +//===----------------------------------------------------------------------===// +// SOPP - GFX8, GFX9, GFX10. +//===----------------------------------------------------------------------===// + +multiclass SOPP_Real_32_gfx8_gfx9_gfx10 op> : + SOPP_Real_32_gfx8_gfx9, SOPP_Real_32_gfx10; + +defm S_WAKEUP : SOPP_Real_32_gfx8_gfx9_gfx10<0x003>; +defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx8_gfx9_gfx10<0x01e>; + + //===----------------------------------------------------------------------===// // SOPC - GFX11, GFX12. //===----------------------------------------------------------------------===// @@ -3080,41 +3240,61 @@ defm S_CMP_EQ_U64 : SOPC_Real_gfx11_gfx12<0x10>; defm S_CMP_LG_U64 : SOPC_Real_gfx11_gfx12<0x11>; //===----------------------------------------------------------------------===// -// SOPC - GFX1150, GFX12 +// SOPC - GFX1150, GFX12, GFX13 //===----------------------------------------------------------------------===// -defm S_CMP_LT_F32 : SOPC_Real_gfx11_gfx12<0x41>; -defm S_CMP_EQ_F32 : SOPC_Real_gfx11_gfx12<0x42>; -defm S_CMP_LE_F32 : SOPC_Real_gfx11_gfx12<0x43>; -defm S_CMP_GT_F32 : SOPC_Real_gfx11_gfx12<0x44>; -defm S_CMP_LG_F32 : SOPC_Real_gfx11_gfx12<0x45>; -defm S_CMP_GE_F32 : SOPC_Real_gfx11_gfx12<0x46>; -defm S_CMP_O_F32 : SOPC_Real_gfx11_gfx12<0x47>; -defm S_CMP_U_F32 : SOPC_Real_gfx11_gfx12<0x48>; -defm S_CMP_NGE_F32 : SOPC_Real_gfx11_gfx12<0x49>; -defm S_CMP_NLG_F32 : SOPC_Real_gfx11_gfx12<0x4a>; -defm S_CMP_NGT_F32 : SOPC_Real_gfx11_gfx12<0x4b>; -defm S_CMP_NLE_F32 : SOPC_Real_gfx11_gfx12<0x4c>; -defm S_CMP_NEQ_F32 : SOPC_Real_gfx11_gfx12<0x4d>; -defm S_CMP_NLT_F32 : SOPC_Real_gfx11_gfx12<0x4e>; +multiclass SOPC_Real_gfx13 op> { + def _gfx13 : SOPC_Real(NAME)>, + Select(NAME).Mnemonic>; +} + +multiclass SOPC_Real_gfx11_gfx12_gfx13 op> : + SOPC_Real_gfx11, SOPC_Real_gfx12, SOPC_Real_gfx13; + +defm S_CMP_LT_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x41>; +defm S_CMP_EQ_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x42>; +defm S_CMP_LE_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x43>; +defm S_CMP_GT_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x44>; +defm S_CMP_LG_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x45>; +defm S_CMP_GE_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x46>; +defm S_CMP_O_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x47>; +defm S_CMP_U_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x48>; +defm S_CMP_NGE_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x49>; +defm S_CMP_NLG_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x4a>; +defm S_CMP_NGT_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x4b>; +defm S_CMP_NLE_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x4c>; +defm S_CMP_NEQ_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x4d>; +defm S_CMP_NLT_F32 : SOPC_Real_gfx11_gfx12_gfx13<0x4e>; -defm S_CMP_LT_F16 : SOPC_Real_gfx11_gfx12<0x51>; -defm S_CMP_EQ_F16 : SOPC_Real_gfx11_gfx12<0x52>; -defm S_CMP_LE_F16 : SOPC_Real_gfx11_gfx12<0x53>; -defm S_CMP_GT_F16 : SOPC_Real_gfx11_gfx12<0x54>; -defm S_CMP_LG_F16 : SOPC_Real_gfx11_gfx12<0x55>; -defm S_CMP_GE_F16 : SOPC_Real_gfx11_gfx12<0x56>; -defm S_CMP_O_F16 : SOPC_Real_gfx11_gfx12<0x57>; -defm S_CMP_U_F16 : SOPC_Real_gfx11_gfx12<0x58>; -defm S_CMP_NGE_F16 : SOPC_Real_gfx11_gfx12<0x59>; -defm S_CMP_NLG_F16 : SOPC_Real_gfx11_gfx12<0x5a>; -defm S_CMP_NGT_F16 : SOPC_Real_gfx11_gfx12<0x5b>; -defm S_CMP_NLE_F16 : SOPC_Real_gfx11_gfx12<0x5c>; -defm S_CMP_NEQ_F16 : SOPC_Real_gfx11_gfx12<0x5d>; -defm S_CMP_NLT_F16 : SOPC_Real_gfx11_gfx12<0x5e>; +defm S_CMP_LT_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x51>; +defm S_CMP_EQ_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x52>; +defm S_CMP_LE_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x53>; +defm S_CMP_GT_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x54>; +defm S_CMP_LG_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x55>; +defm S_CMP_GE_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x56>; +defm S_CMP_O_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x57>; +defm S_CMP_U_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x58>; +defm S_CMP_NGE_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x59>; +defm S_CMP_NLG_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x5a>; +defm S_CMP_NGT_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x5b>; +defm S_CMP_NLE_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x5c>; +defm S_CMP_NEQ_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x5d>; +defm S_CMP_NLT_F16 : SOPC_Real_gfx11_gfx12_gfx13<0x5e>; //===----------------------------------------------------------------------===// -// SOPC - GFX6, GFX7, GFX8, GFX9, GFX10 +// SOPC - GFX8, GFX9. +//===----------------------------------------------------------------------===// + +multiclass SOPC_Real_gfx8_gfx9 op> { + defvar ps = !cast(NAME); + def _vi : SOPC_Real, + Select_vi; +} + +defm S_SET_GPR_IDX_ON : SOPC_Real_gfx8_gfx9<0x11>; + +//===----------------------------------------------------------------------===// +// SOPC - GFX6, GFX7, GFX8, GFX9. //===----------------------------------------------------------------------===// multiclass SOPC_Real_gfx6_gfx7 op> { @@ -3123,11 +3303,14 @@ multiclass SOPC_Real_gfx6_gfx7 op> { Select_gfx6_gfx7; } -multiclass SOPC_Real_gfx8_gfx9 op> { - defvar ps = !cast(NAME); - def _vi : SOPC_Real, - Select_vi; -} +multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9 op> : + SOPC_Real_gfx6_gfx7, SOPC_Real_gfx8_gfx9; + +defm S_SETVSKIP : SOPC_Real_gfx6_gfx7_gfx8_gfx9<0x10>; + +//===----------------------------------------------------------------------===// +// SOPC - GFX6, GFX7, GFX8, GFX9, GFX10, GFX13 +//===----------------------------------------------------------------------===// multiclass SOPC_Real_gfx10 op> { defvar ps = !cast(NAME); @@ -3135,36 +3318,36 @@ multiclass SOPC_Real_gfx10 op> { Select; } -multiclass SOPC_Real_gfx8_gfx9_gfx10 op> : - SOPC_Real_gfx8_gfx9, SOPC_Real_gfx10; +multiclass SOPC_Real_gfx8_gfx9_gfx10_gfx13 op> : + SOPC_Real_gfx8_gfx9, SOPC_Real_gfx10, SOPC_Real_gfx13; -multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9 op> : - SOPC_Real_gfx6_gfx7, SOPC_Real_gfx8_gfx9; +defm S_CMP_EQ_U64 : SOPC_Real_gfx8_gfx9_gfx10_gfx13<0x12>; +defm S_CMP_LG_U64 : SOPC_Real_gfx8_gfx9_gfx10_gfx13<0x13>; -multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12 op> : +//===----------------------------------------------------------------------===// +// SOPC - GFX6, GFX7, GFX8, GFX9, GFX10, GFX11, GFX12, GFX13 +//===----------------------------------------------------------------------===// + +multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13 op> : SOPC_Real_gfx6_gfx7_gfx8_gfx9, SOPC_Real_gfx10, SOPC_Real_gfx11, - SOPC_Real_gfx12; - -defm S_CMP_EQ_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x00>; -defm S_CMP_LG_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x01>; -defm S_CMP_GT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x02>; -defm S_CMP_GE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x03>; -defm S_CMP_LT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x04>; -defm S_CMP_LE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x05>; -defm S_CMP_EQ_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x06>; -defm S_CMP_LG_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x07>; -defm S_CMP_GT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x08>; -defm S_CMP_GE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x09>; -defm S_CMP_LT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0a>; -defm S_CMP_LE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0b>; -defm S_BITCMP0_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0c>; -defm S_BITCMP1_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0d>; -defm S_BITCMP0_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0e>; -defm S_BITCMP1_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0f>; -defm S_SETVSKIP : SOPC_Real_gfx6_gfx7_gfx8_gfx9<0x10>; -defm S_SET_GPR_IDX_ON : SOPC_Real_gfx8_gfx9<0x11>; -defm S_CMP_EQ_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x12>; -defm S_CMP_LG_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x13>; + SOPC_Real_gfx12, SOPC_Real_gfx13; + +defm S_CMP_EQ_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x00>; +defm S_CMP_LG_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x01>; +defm S_CMP_GT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x02>; +defm S_CMP_GE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x03>; +defm S_CMP_LT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x04>; +defm S_CMP_LE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x05>; +defm S_CMP_EQ_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x06>; +defm S_CMP_LG_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x07>; +defm S_CMP_GT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x08>; +defm S_CMP_GE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x09>; +defm S_CMP_LT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x0a>; +defm S_CMP_LE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x0b>; +defm S_BITCMP0_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x0c>; +defm S_BITCMP1_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x0d>; +defm S_BITCMP0_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x0e>; +defm S_BITCMP1_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12_gfx13<0x0f>; //===----------------------------------------------------------------------===// // GFX8 (VI), GFX9. diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp index ee5a10fb6e8f9..fddd9c76337f0 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp @@ -99,7 +99,6 @@ static constexpr CustomOperand MsgOperands[] = { {{"MSG_EARLY_PRIM_DEALLOC"}, ID_EARLY_PRIM_DEALLOC, isGFX9_GFX10}, {{"MSG_GS_ALLOC_REQ"}, ID_GS_ALLOC_REQ, isGFX9Plus}, {{"MSG_GET_DOORBELL"}, ID_GET_DOORBELL, isGFX9_GFX10}, - {{"MSG_SAVEWAVE_HAS_TDM"}, ID_SAVEWAVE_HAS_TDM, isGFX1250Plus}, {{"MSG_GET_DDID"}, ID_GET_DDID, isGFX10}, {{"MSG_SYSMSG"}, ID_SYSMSG}, {{"MSG_RTN_GET_DOORBELL"}, ID_RTN_GET_DOORBELL, isGFX11Plus}, @@ -112,6 +111,7 @@ static constexpr CustomOperand MsgOperands[] = { {{"MSG_RTN_GET_SE_AID_ID"}, ID_RTN_GET_SE_AID_ID, isGFX12Plus}, {{"MSG_RTN_GET_CLUSTER_BARRIER_STATE"}, ID_RTN_GET_CLUSTER_BARRIER_STATE, isGFX1250Plus}, + {{"MSG_RTN_SAVE_WAVE_HAS_TDM"}, ID_RTN_SAVE_WAVE_HAS_TDM, isGFX1250Plus} }; static constexpr CustomOperand SysMsgOperands[] = { @@ -156,6 +156,26 @@ StringRef getMsgOpName(int64_t MsgId, uint64_t Encoding, } // namespace SendMsg +namespace WaitEvent { + +// clang-format off +static constexpr CustomOperand WaitEventOperands[] = { + {{"{ export_ready: 0 }"}, 0, isGFX12Plus}, + {{"{ dont_wait_export_ready: 0 }"}, 0, isGFX11}, + {{"{ dont_wait_export_ready: 1 }"}, DONT_WAIT_EXPORT_READY, isGFX11}, + {{"{ export_ready: 1 }"}, EXPORT_READY, isGFX12Plus} +}; +// clang-format on + +int64_t getWaitEventMask(StringRef Name, const MCSubtargetInfo &STI) { + return getEncodingFromOperandTable(WaitEventOperands, Name, STI); +} + +StringRef getWaitEventMaskName(uint64_t Encoding, const MCSubtargetInfo &STI) { + return getNameFromOperandTable(WaitEventOperands, Encoding, STI); +} +} // namespace WaitEvent + namespace Hwreg { // Disable lint checking for this block since it makes the table unreadable. diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h index c84c1a7dc18c4..5916e27ad7282 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h @@ -84,6 +84,11 @@ StringRef getMsgOpName(int64_t MsgId, uint64_t Encoding, } // namespace SendMsg +namespace WaitEvent { +int64_t getWaitEventMask(StringRef Name, const MCSubtargetInfo &STI); +StringRef getWaitEventMaskName(uint64_t Encoding, const MCSubtargetInfo &STI); +} // namespace WaitEvent + namespace Hwreg { // Symbolic names for the hwreg(...) syntax. int64_t getHwregId(StringRef Name, const MCSubtargetInfo &STI); @@ -127,6 +132,20 @@ ArrayRef getGFXVersions(); } // namespace UCVersion +namespace WMMAMods { +// These should match enum values in SIDefines.h + +constexpr const char *const ModMatrixFmt[] = { + "MATRIX_FMT_FP8", "MATRIX_FMT_BF8", "MATRIX_FMT_FP6", "MATRIX_FMT_BF6", + "MATRIX_FMT_FP4"}; + +constexpr const char *const ModMatrixScale[] = {"MATRIX_SCALE_ROW0", + "MATRIX_SCALE_ROW1"}; + +constexpr const char *const ModMatrixScaleFmt[] = { + "MATRIX_SCALE_FMT_E8", "MATRIX_SCALE_FMT_E5M3", "MATRIX_SCALE_FMT_E4M3"}; +} // namespace WMMAMods + } // namespace AMDGPU } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 1f053201da226..56e7623496eea 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -760,9 +760,9 @@ def V_CVT_F16_F8_True16_Profile : VOP3_Profile_True16; def V_CVT_F16_F8_Fake16_Profile : VOP3_Profile_Fake16; } -let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts], +let SubtargetPredicate = isGFX11Plus, OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in { - let SubtargetPredicate = isGFX12PlusNot12_50 in + let SubtargetPredicate = isGFX11PlusNot12_50 in defm V_CVT_F32_FP8_OP_SEL : VOP1Inst<"v_cvt_f32_fp8_op_sel", VOPProfile_Base_CVT_F_F8_ByteSel>; let SubtargetPredicate = isGFX125xOnly in defm V_CVT_F32_FP8_gfx1250 : VOP1Inst<"v_cvt_f32_fp8_gfx1250", VOPProfile_Base_CVT_F_F8_ByteSel>; @@ -786,7 +786,7 @@ class Cvt_F_F8_Pat_ByteSel; let OtherPredicates = [HasFP8ConversionInsts] in { - let SubtargetPredicate = isGFX12PlusNot12_50 in + let SubtargetPredicate = isGFX11PlusNot12_50 in def : Cvt_F_F8_Pat_ByteSel; let SubtargetPredicate = isGFX125xOnly in { def : GCNPat<(int_amdgcn_cvt_f32_fp8 i32:$src0, timm:$byte_sel), @@ -794,7 +794,7 @@ let OtherPredicates = [HasFP8ConversionInsts] in { def : GCNPat<(int_amdgcn_cvt_f32_fp8_e5m3 i32:$src0, timm:$byte_sel), (V_CVT_F32_FP8_gfx1250_e64 $src0, DSTCLAMP.ENABLE, (as_i32timm $byte_sel))>; } - let SubtargetPredicate = isGFX12Plus in + let SubtargetPredicate = isGFX11Plus in def : Cvt_F_F8_Pat_ByteSel; } @@ -806,7 +806,7 @@ class Cvt_PK_F32_F8_Pat_OpSel; -let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts] in { +let SubtargetPredicate = isGFX11Plus, OtherPredicates = [HasFP8ConversionInsts] in { foreach Index = [0, -1] in { def : Cvt_PK_F32_F8_Pat_OpSel; @@ -1140,8 +1140,9 @@ multiclass VOP1Only_Real_gfx11_gfx12_gfx13 op> : multiclass VOP1_Real_FULL_gfx11_gfx12 op> : VOP1_Real_FULL, VOP1_Real_FULL; -multiclass VOP1_Real_e32_with_name_gfx12_gfx13 op, string opName, - string asmName> : +multiclass VOP1_Real_e32_with_name_gfx11_gfx12_gfx13 op, string opName, + string asmName> : + VOP1_Real_e32_with_name, VOP1_Real_e32_with_name, VOP1_Real_e32_with_name; @@ -1179,16 +1180,16 @@ multiclass VOP1_Real_OpSelIsDPP_gfx1250_gfx13 op> : defm V_CVT_F32_FP8 : VOP1_Real_FULL_with_name_gfx11_gfx12_gfx13_not_gfx1250<0x06c, "V_CVT_F32_FP8_OP_SEL", "v_cvt_f32_fp8">; defm V_CVT_F32_FP8 : VOP1_Real_FULL_with_name; -defm V_CVT_F32_BF8 : VOP1_Real_FULL_with_name_gfx12_gfx13<0x06d, "V_CVT_F32_BF8_OP_SEL", "v_cvt_f32_bf8">; +defm V_CVT_F32_BF8 : VOP1_Real_FULL_with_name_gfx11_gfx12_gfx13<0x06d, "V_CVT_F32_BF8_OP_SEL", "v_cvt_f32_bf8">; -defm V_CVT_PK_F32_FP8_fake16 : VOP1_Real_e32_with_name_gfx12_gfx13<0x06e, "V_CVT_PK_F32_FP8_fake16", "v_cvt_pk_f32_fp8">; -defm V_CVT_PK_F32_FP8_t16 : VOP1_Real_e32_with_name_gfx12_gfx13<0x06e, "V_CVT_PK_F32_FP8_t16", "v_cvt_pk_f32_fp8">; -defm V_CVT_PK_F32_FP8_fake16 : VOP3_Real_with_name_gfx12_gfx13<0x1ee, "V_CVT_PK_F32_FP8_fake16", "v_cvt_pk_f32_fp8">; -defm V_CVT_PK_F32_FP8_t16 : VOP3_Real_with_name_gfx12_gfx13<0x1ee, "V_CVT_PK_F32_FP8_t16", "v_cvt_pk_f32_fp8">; -defm V_CVT_PK_F32_BF8_fake16 : VOP1_Real_e32_with_name_gfx12_gfx13<0x06f, "V_CVT_PK_F32_BF8_fake16", "v_cvt_pk_f32_bf8">; -defm V_CVT_PK_F32_BF8_t16 : VOP1_Real_e32_with_name_gfx12_gfx13<0x06f, "V_CVT_PK_F32_BF8_t16", "v_cvt_pk_f32_bf8">; -defm V_CVT_PK_F32_BF8_fake16 : VOP3_Real_with_name_gfx12_gfx13<0x1ef, "V_CVT_PK_F32_BF8_fake16", "v_cvt_pk_f32_bf8">; -defm V_CVT_PK_F32_BF8_t16 : VOP3_Real_with_name_gfx12_gfx13<0x1ef, "V_CVT_PK_F32_BF8_t16", "v_cvt_pk_f32_bf8">; +defm V_CVT_PK_F32_FP8_fake16 : VOP1_Real_e32_with_name_gfx11_gfx12_gfx13<0x06e, "V_CVT_PK_F32_FP8_fake16", "v_cvt_pk_f32_fp8">; +defm V_CVT_PK_F32_FP8_t16 : VOP1_Real_e32_with_name_gfx11_gfx12_gfx13<0x06e, "V_CVT_PK_F32_FP8_t16", "v_cvt_pk_f32_fp8">; +defm V_CVT_PK_F32_FP8_fake16 : VOP3_Real_with_name_gfx11_gfx12_gfx13<0x1ee, "V_CVT_PK_F32_FP8_fake16", "v_cvt_pk_f32_fp8">; +defm V_CVT_PK_F32_FP8_t16 : VOP3_Real_with_name_gfx11_gfx12_gfx13<0x1ee, "V_CVT_PK_F32_FP8_t16", "v_cvt_pk_f32_fp8">; +defm V_CVT_PK_F32_BF8_fake16 : VOP1_Real_e32_with_name_gfx11_gfx12_gfx13<0x06f, "V_CVT_PK_F32_BF8_fake16", "v_cvt_pk_f32_bf8">; +defm V_CVT_PK_F32_BF8_t16 : VOP1_Real_e32_with_name_gfx11_gfx12_gfx13<0x06f, "V_CVT_PK_F32_BF8_t16", "v_cvt_pk_f32_bf8">; +defm V_CVT_PK_F32_BF8_fake16 : VOP3_Real_with_name_gfx11_gfx12_gfx13<0x1ef, "V_CVT_PK_F32_BF8_fake16", "v_cvt_pk_f32_bf8">; +defm V_CVT_PK_F32_BF8_t16 : VOP3_Real_with_name_gfx11_gfx12_gfx13<0x1ef, "V_CVT_PK_F32_BF8_t16", "v_cvt_pk_f32_bf8">; defm V_CVT_NEAREST_I32_F32 : VOP1_Real_FULL_with_name_gfx11_gfx12_gfx13<0x00c, "V_CVT_RPI_I32_F32", "v_cvt_nearest_i32_f32">; diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 56127c7e2f48f..bdcf04f734291 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -638,19 +638,13 @@ class ThreeOpFrag : ThreeOpFragSDA } def shl_0_to_4 : PatFrag< - (ops node:$src0, node:$src1), (shl node:$src0, node:$src1), - [{ - if (auto *C = dyn_cast(N->getOperand(1))) { - return C->getZExtValue() <= 4; - } - return false; - }]> { + (ops node:$src0, node:$src1), (shl node:$src0, node:$src1), [{ + KnownBits KB = CurDAG->computeKnownBits(N->getOperand(1)); + return KB.getMaxValue().getZExtValue() <= 4; + }]> { let GISelPredicateCode = [{ - int64_t Imm = 0; - if (!mi_match(MI.getOperand(2).getReg(), MRI, m_ICst(Imm)) && - !mi_match(MI.getOperand(2).getReg(), MRI, m_Copy(m_ICst(Imm)))) - return false; - return (uint64_t)Imm <= 4; + KnownBits KB = VT->getKnownBits(MI.getOperand(2).getReg()); + return KB.getMaxValue().getZExtValue() <= 4; }]; } @@ -821,13 +815,13 @@ let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0, VOP3_CVT_PK_F8_F32_Profile_t16<>, VOP3_CVT_PK_F8_F32_Profile_fake16<>>; - let SubtargetPredicate = isGFX12Plus in { + let SubtargetPredicate = isGFX11Plus in { let OtherPredicates = [HasFP8ConversionInsts, NotHasFP8E5M3Insts] in defm V_CVT_SR_FP8_F32_gfx12 : VOP3Inst<"v_cvt_sr_fp8_f32_gfx12", VOP3_CVT_SR_F8_ByteSel_Profile>; let OtherPredicates = [HasFP8ConversionInsts, HasFP8E5M3Insts] in defm V_CVT_SR_FP8_F32_gfx1250 : VOP3Inst<"v_cvt_sr_fp8_f32_gfx1250", VOP3_CVT_SR_F8_ByteSel_Profile>; defm V_CVT_SR_BF8_F32_gfx12 : VOP3Inst<"v_cvt_sr_bf8_f32_gfx12", VOP3_CVT_SR_F8_ByteSel_Profile>; - } + } // End SubtargetPredicate = isGFX11Plus } // These instructions have non-standard use of op_sel. In particular they are @@ -931,7 +925,7 @@ let SubtargetPredicate = isGFX940Plus in { } } -let SubtargetPredicate = isGFX12Plus in { +let SubtargetPredicate = isGFX11Plus in { let OtherPredicates = [HasFP8ConversionInsts, NotHasFP8E5M3Insts] in def : Cvt_SR_F8_ByteSel_Pat; let OtherPredicates = [HasFP8ConversionInsts, HasFP8E5M3Insts] in { @@ -939,7 +933,7 @@ let SubtargetPredicate = isGFX12Plus in { def : Cvt_SR_F8_ByteSel_E5M3_Pat; } def : Cvt_SR_F8_ByteSel_Pat; -} +} // End SubtargetPredicate = isGFX11Plus } class ThreeOp_i32_Pats : GCNPat < diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index d111b8996ae75..256dd0bb027ad 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -182,6 +182,8 @@ multiclass MadFmaMixFP32Pats { defvar VOP3PMadMixModsPat = !if (!eq(VT, bf16), VOP3PMadMixBF16Mods, VOP3PMadMixMods); defvar VOP3PMadMixModsExtPat = !if (!eq(VT, bf16), VOP3PMadMixBF16ModsExt, VOP3PMadMixModsExt); + defvar OneImm = !if (!eq(VT, bf16), CONST.BF16_ONE, CONST.FP16_ONE); + defvar NegOneImm = !if (!eq(VT, bf16), CONST.BF16_NEG_ONE, CONST.FP16_NEG_ONE); // At least one of the operands needs to be an fpextend of an f16 // for this to be worthwhile, so we need three patterns here. // TODO: Could we use a predicate to inspect src1/2/3 instead? @@ -203,6 +205,34 @@ multiclass MadFmaMixFP32Pats; + + // (fadd x, y) -> (fma x, 1.0, y) + def : GCNPat < + (f32 (fadd (f32 (VOP3PMadMixModsExtPat VT:$src0, i32:$src0_mods)), + (f32 (VOP3PMadMixModsPat f32:$src1, i32:$src1_mods)))), + (mix_inst $src0_mods, $src0, (i32 8), (i32 OneImm), $src1_mods, $src1, + DSTCLAMP.NONE)>; + + // (fmul x, y) -> (fma x, y, -0.0) + def : GCNPat < + (f32 (fmul (f32 (VOP3PMadMixModsExtPat VT:$src0, i32:$src0_mods)), + (f32 (VOP3PMadMixModsPat f32:$src1, i32:$src1_mods)))), + (mix_inst $src0_mods, $src0, $src1_mods, $src1, (i32 SRCMODS.NEG), (i32 0), + DSTCLAMP.NONE)>; + + // (fsub x, y) -> (fma y, -1.0, x) + def : GCNPat < + (f32 (fsub (f32 (VOP3PMadMixModsExtPat VT:$src0, i32:$src0_mods)), + (f32 (VOP3PMadMixModsPat f32:$src1, i32:$src1_mods)))), + (mix_inst $src1_mods, $src1, (i32 8), (i32 NegOneImm), $src0_mods, $src0, + DSTCLAMP.NONE)>; + + // (fsub x, y) -> (fma y, -1.0, x) + def : GCNPat < + (f32 (fsub (f32 (VOP3PMadMixModsPat f32:$src0, i32:$src0_mods)), + (f32 (VOP3PMadMixModsExtPat VT:$src1, i32:$src1_mods)))), + (mix_inst $src1_mods, $src1, (i32 8), (i32 NegOneImm), $src0_mods, $src0, + DSTCLAMP.NONE)>; } multiclass MadFmaMixFP16Pats op, string opName, } } -multiclass VOP3_Real_with_name_gfx12_gfx13< +multiclass VOP3_Real_with_name_gfx11_gfx12_gfx13< bits<10> op, string opName, string asmName, string pseudo_mnemonic = "", bit isSingle = 0> : + VOP3_Real_with_name, VOP3_Real_with_name, VOP3_Real_with_name; diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index e7d30aec14860..1f894bb76c027 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -651,13 +651,12 @@ static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, } // Returns true if all functions definitions have the same denormal mode. // It also returns true when the module has no functions. -static bool checkDenormalAttributeConsistency(const Module &M, StringRef Attr, - DenormalMode Value) { +static bool checkDenormalAttributeConsistency(const Module &M, + DenormalFPEnv Value) { return !any_of(M, [&](const Function &F) { if (F.isDeclaration()) return false; - StringRef AttrVal = F.getFnAttribute(Attr).getValueAsString(); - return parseDenormalFPAttribute(AttrVal) != Value; + return F.getDenormalFPEnv() != Value; }); } @@ -667,10 +666,10 @@ static bool checkDenormalAttributeInconsistency(const Module &M) { auto E = M.functions().end(); if (F == E) return false; - DenormalMode Value = F->getDenormalModeRaw(); + DenormalFPEnv Value = F->getDenormalFPEnv(); ++F; return std::any_of(F, E, [&](const Function &F) { - return !F.isDeclaration() && F.getDenormalModeRaw() != Value; + return !F.isDeclaration() && F.getDenormalFPEnv() != Value; }); } @@ -731,18 +730,21 @@ void ARMAsmPrinter::emitAttributes() { } // Set FP Denormals. - if (checkDenormalAttributeConsistency(*MMI->getModule(), "denormal-fp-math", - DenormalMode::getPreserveSign())) + if (auto *DM = mdconst::extract_or_null( + MMI->getModule()->getModuleFlag("arm-eabi-fp-denormal"))) { + if (unsigned TagVal = DM->getZExtValue()) + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, TagVal); + } else if (checkDenormalAttributeConsistency(*MMI->getModule(), + DenormalMode::getPreserveSign())) ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::PreserveFPSign); else if (checkDenormalAttributeConsistency(*MMI->getModule(), - "denormal-fp-math", DenormalMode::getPositiveZero())) ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::PositiveZero); else if (checkDenormalAttributeInconsistency(*MMI->getModule()) || - checkDenormalAttributeConsistency( - *MMI->getModule(), "denormal-fp-math", DenormalMode::getIEEE())) + checkDenormalAttributeConsistency(*MMI->getModule(), + DenormalMode::getIEEE())) ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::IEEEDenormals); else { @@ -772,9 +774,13 @@ void ARMAsmPrinter::emitAttributes() { } // Set FP exceptions and rounding - if (checkFunctionsAttributeConsistency(*MMI->getModule(), - "no-trapping-math", "true") || - TM.Options.NoTrappingFPMath) + if (auto *Ex = mdconst::extract_or_null( + MMI->getModule()->getModuleFlag("arm-eabi-fp-exceptions"))) { + if (unsigned TagVal = Ex->getZExtValue()) + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, TagVal); + } else if (checkFunctionsAttributeConsistency(*MMI->getModule(), + "no-trapping-math", "true") || + TM.Options.NoTrappingFPMath) ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Not_Allowed); else { @@ -786,12 +792,12 @@ void ARMAsmPrinter::emitAttributes() { ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed); } - // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the - // equivalent of GCC's -ffinite-math-only flag. - if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath) - ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model, - ARMBuildAttrs::Allowed); - else + // Generate ABI tags from module flags. + if (auto *NumModel = mdconst::extract_or_null( + MMI->getModule()->getModuleFlag("arm-eabi-fp-number-model"))) { + if (unsigned TagVal = NumModel->getZExtValue()) + ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model, TagVal); + } else ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model, ARMBuildAttrs::AllowIEEE754); diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index ea427d1679f24..bc5a89bc5d7f4 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2167,27 +2167,6 @@ ARMBaseInstrInfo::canFoldIntoMOVCC(Register Reg, const MachineRegisterInfo &MRI, return MI; } -bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI, - SmallVectorImpl &Cond, - unsigned &TrueOp, unsigned &FalseOp, - bool &Optimizable) const { - assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) && - "Unknown select instruction"); - // MOVCC operands: - // 0: Def. - // 1: True use. - // 2: False use. - // 3: Condition code. - // 4: CPSR use. - TrueOp = 1; - FalseOp = 2; - Cond.push_back(MI.getOperand(3)); - Cond.push_back(MI.getOperand(4)); - // We can always fold a def. - Optimizable = true; - return false; -} - MachineInstr * ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI, SmallPtrSetImpl &SeenMIs, diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 60ef40b459097..2818f13c5d000 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -304,10 +304,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo { Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override; - bool analyzeSelect(const MachineInstr &MI, - SmallVectorImpl &Cond, unsigned &TrueOp, - unsigned &FalseOp, bool &Optimizable) const override; - MachineInstr *optimizeSelect(MachineInstr &MI, SmallPtrSetImpl &SeenMIs, bool) const override; diff --git a/llvm/lib/Target/ARM/ARMCallingConv.cpp b/llvm/lib/Target/ARM/ARMCallingConv.cpp index a206e993394f7..795476b3f386b 100644 --- a/llvm/lib/Target/ARM/ARMCallingConv.cpp +++ b/llvm/lib/Target/ARM/ARMCallingConv.cpp @@ -186,9 +186,10 @@ static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT, if (!ArgFlags.isInConsecutiveRegsLast()) return true; + const MachineFunction &MF = State.getMachineFunction(); // Try to allocate a contiguous block of registers, each of the correct // size to hold one member. - auto &DL = State.getMachineFunction().getDataLayout(); + auto &DL = MF.getDataLayout(); const MaybeAlign StackAlign = DL.getStackAlignment(); assert(StackAlign && "data layout string is missing stack alignment"); const Align FirstMemberAlign(PendingMembers[0].getExtraInfo()); @@ -265,7 +266,7 @@ static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT, State.AllocateReg(Reg); // Clamp the alignment between 4 and 8. - if (State.getMachineFunction().getSubtarget().isTargetAEABI()) + if (MF.getTarget().getTargetTriple().isTargetAEABI()) Alignment = ArgFlags.getNonZeroMemAlign() <= 4 ? Align(4) : Align(8); // After the first item has been allocated, the rest are packed as tightly as diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 7b240462c66fb..f9ce14b079826 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -939,11 +939,24 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_, setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); } + // Custom loads/stores to possible use __aeabi_uread/write* + if (TT.isTargetAEABI() && !Subtarget->allowsUnalignedMem()) { + setOperationAction(ISD::STORE, MVT::i32, Custom); + setOperationAction(ISD::STORE, MVT::i64, Custom); + setOperationAction(ISD::LOAD, MVT::i32, Custom); + setOperationAction(ISD::LOAD, MVT::i64, Custom); + } + setOperationAction(ISD::SADDO, MVT::i32, Custom); setOperationAction(ISD::UADDO, MVT::i32, Custom); setOperationAction(ISD::SSUBO, MVT::i32, Custom); setOperationAction(ISD::USUBO, MVT::i32, Custom); + if (!Subtarget->isThumb1Only()) { + setOperationAction(ISD::UMULO, MVT::i32, Custom); + setOperationAction(ISD::SMULO, MVT::i32, Custom); + } + setOperationAction(ISD::UADDO_CARRY, MVT::i32, Custom); setOperationAction(ISD::USUBO_CARRY, MVT::i32, Custom); if (Subtarget->hasDSP()) { @@ -2429,17 +2442,18 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, bool isDirect = false; const TargetMachine &TM = getTargetMachine(); + const Triple &TT = TM.getTargetTriple(); const GlobalValue *GVal = nullptr; if (GlobalAddressSDNode *G = dyn_cast(Callee)) GVal = G->getGlobal(); - bool isStub = !TM.shouldAssumeDSOLocal(GVal) && Subtarget->isTargetMachO(); + bool isStub = !TM.shouldAssumeDSOLocal(GVal) && TT.isOSBinFormatMachO(); bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass()); bool isLocalARMFunc = false; auto PtrVt = getPointerTy(DAG.getDataLayout()); if (Subtarget->genLongCalls()) { - assert((!isPositionIndependent() || Subtarget->isTargetWindows()) && + assert((!isPositionIndependent() || TT.isOSWindows()) && "long-calls codegen is not position independent!"); // Handle a global address or an external symbol. If it's not one of // those, the target's already in a register, so we don't need to do @@ -2494,7 +2508,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking); // tBX takes a register source operand. if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { - assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"); + assert(TT.isOSBinFormatMachO() && "WrapperPIC use on non-MachO?"); Callee = DAG.getNode( ARMISD::WrapperPIC, dl, PtrVt, DAG.getTargetGlobalAddress(GVal, dl, PtrVt, 0, ARMII::MO_NONLAZY)); @@ -3286,7 +3300,7 @@ SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, SDValue ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const { - assert(Subtarget->isTargetDarwin() && + assert(getTargetMachine().getTargetTriple().isOSDarwin() && "This function expects a Darwin target"); SDLoc DL(Op); @@ -3330,7 +3344,8 @@ ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op, SDValue ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const { - assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering"); + assert(getTargetMachine().getTargetTriple().isOSWindows() && + "Windows specific TLS lowering"); SDValue Chain = DAG.getEntryNode(); EVT PtrVT = getPointerTy(DAG.getDataLayout()); @@ -3480,14 +3495,15 @@ ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { if (DAG.getTarget().useEmulatedTLS()) return LowerToTLSEmulatedModel(GA, DAG); - if (Subtarget->isTargetDarwin()) + const Triple &TT = getTargetMachine().getTargetTriple(); + if (TT.isOSDarwin()) return LowerGlobalTLSAddressDarwin(Op, DAG); - if (Subtarget->isTargetWindows()) + if (TT.isOSWindows()) return LowerGlobalTLSAddressWindows(Op, DAG); // TODO: implement the "local dynamic" model - assert(Subtarget->isTargetELF() && "Only ELF implemented here"); + assert(TT.isOSBinFormatELF() && "Only ELF implemented here"); TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal()); switch (model) { @@ -3731,7 +3747,8 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const { - assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported"); + assert(getTargetMachine().getTargetTriple().isOSWindows() && + "non-Windows COFF is not supported"); assert(Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"); assert(!Subtarget->isROPI() && !Subtarget->isRWPI() && @@ -4646,7 +4663,7 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG, break; case ISD::UADDO: ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32); - // We use ADDC here to correspond to its use in LowerUnsignedALUO. + // We use ADDC here to correspond to its use in LowerALUO. // We do not use it in the USUBO case as Value may not be used. Value = DAG.getNode(ARMISD::ADDC, dl, DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS) @@ -4669,7 +4686,7 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG, Value = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(Op.getValueType(), Op.getValueType()), LHS, RHS); - OverflowCmp = DAG.getNode(ARMISD::CMP, dl, FlagsVT, Value.getValue(1), + OverflowCmp = DAG.getNode(ARMISD::CMPZ, dl, FlagsVT, Value.getValue(1), DAG.getConstant(0, dl, MVT::i32)); Value = Value.getValue(0); // We only want the low 32 bits for the result. break; @@ -4680,7 +4697,7 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG, Value = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(Op.getValueType(), Op.getValueType()), LHS, RHS); - OverflowCmp = DAG.getNode(ARMISD::CMP, dl, FlagsVT, Value.getValue(1), + OverflowCmp = DAG.getNode(ARMISD::CMPZ, dl, FlagsVT, Value.getValue(1), DAG.getNode(ISD::SRA, dl, Op.getValueType(), Value.getValue(0), DAG.getConstant(31, dl, MVT::i32))); @@ -4691,28 +4708,6 @@ ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG, return std::make_pair(Value, OverflowCmp); } -SDValue -ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const { - // Let legalize expand this if it isn't a legal type yet. - if (!isTypeLegal(Op.getValueType())) - return SDValue(); - - SDValue Value, OverflowCmp; - SDValue ARMcc; - std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc); - SDLoc dl(Op); - // We use 0 and 1 as false and true values. - SDValue TVal = DAG.getConstant(1, dl, MVT::i32); - SDValue FVal = DAG.getConstant(0, dl, MVT::i32); - EVT VT = Op.getValueType(); - - SDValue Overflow = - DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal, ARMcc, OverflowCmp); - - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); - return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); -} - static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry, SelectionDAG &DAG) { SDLoc DL(BoolCarry); @@ -4737,8 +4732,7 @@ static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT, DAG.getConstant(0, DL, MVT::i32), Flags); } -SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op, - SelectionDAG &DAG) const { +SDValue ARMTargetLowering::LowerALUO(SDValue Op, SelectionDAG &DAG) const { // Let legalize expand this if it isn't a legal type yet. if (!isTypeLegal(Op.getValueType())) return SDValue(); @@ -4752,14 +4746,12 @@ SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op, SDValue Value; SDValue Overflow; switch (Op.getOpcode()) { - default: - llvm_unreachable("Unknown overflow instruction!"); case ISD::UADDO: Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS); // Convert the carry flag into a boolean value. Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG); break; - case ISD::USUBO: { + case ISD::USUBO: Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS); // Convert the carry flag into a boolean value. Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG); @@ -4768,6 +4760,20 @@ SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op, Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32, DAG.getConstant(1, dl, MVT::i32), Overflow); break; + default: { + // Handle other operations with getARMXALUOOp + SDValue OverflowCmp, ARMcc; + std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc); + // We use 0 and 1 as false and true values. + // ARMcc represents the "no overflow" condition (e.g., VC for signed ops). + // CMOV operand order is (FalseVal, TrueVal), so we put 1 in FalseVal + // position to get Overflow=1 when the "no overflow" condition is false. + Overflow = + DAG.getNode(ARMISD::CMOV, dl, MVT::i32, + DAG.getConstant(1, dl, MVT::i32), // FalseVal: overflow + DAG.getConstant(0, dl, MVT::i32), // TrueVal: no overflow + ARMcc, OverflowCmp); + break; } } @@ -9737,6 +9743,95 @@ void ARMTargetLowering::ExpandDIV_Windows( Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lower, Upper)); } +std::pair +ARMTargetLowering::LowerAEABIUnalignedLoad(SDValue Op, + SelectionDAG &DAG) const { + // If we have an unaligned load from a i32 or i64 that would normally be + // split into separate ldrb's, we can use the __aeabi_uread4/__aeabi_uread8 + // functions instead. + LoadSDNode *LD = cast(Op.getNode()); + EVT MemVT = LD->getMemoryVT(); + if (MemVT != MVT::i32 && MemVT != MVT::i64) + return std::make_pair(SDValue(), SDValue()); + + const auto &MF = DAG.getMachineFunction(); + unsigned AS = LD->getAddressSpace(); + Align Alignment = LD->getAlign(); + const DataLayout &DL = DAG.getDataLayout(); + bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); + + if (MF.getFunction().hasMinSize() && !AllowsUnaligned && + Alignment <= llvm::Align(2)) { + + RTLIB::Libcall LC = + (MemVT == MVT::i32) ? RTLIB::AEABI_UREAD4 : RTLIB::AEABI_UREAD8; + + MakeLibCallOptions Opts; + SDLoc dl(Op); + + auto Pair = makeLibCall(DAG, LC, MemVT.getSimpleVT(), LD->getBasePtr(), + Opts, dl, LD->getChain()); + + // If necessary, extend the node to 64bit + if (LD->getExtensionType() != ISD::NON_EXTLOAD) { + unsigned ExtType = LD->getExtensionType() == ISD::SEXTLOAD + ? ISD::SIGN_EXTEND + : ISD::ZERO_EXTEND; + SDValue EN = DAG.getNode(ExtType, dl, LD->getValueType(0), Pair.first); + Pair.first = EN; + } + return Pair; + } + + // Default expand to individual loads + if (!allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Alignment)) + return expandUnalignedLoad(LD, DAG); + return std::make_pair(SDValue(), SDValue()); +} + +SDValue ARMTargetLowering::LowerAEABIUnalignedStore(SDValue Op, + SelectionDAG &DAG) const { + // If we have an unaligned store to a i32 or i64 that would normally be + // split into separate ldrb's, we can use the __aeabi_uwrite4/__aeabi_uwrite8 + // functions instead. + StoreSDNode *ST = cast(Op.getNode()); + EVT MemVT = ST->getMemoryVT(); + if (MemVT != MVT::i32 && MemVT != MVT::i64) + return SDValue(); + + const auto &MF = DAG.getMachineFunction(); + unsigned AS = ST->getAddressSpace(); + Align Alignment = ST->getAlign(); + const DataLayout &DL = DAG.getDataLayout(); + bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); + + if (MF.getFunction().hasMinSize() && !AllowsUnaligned && + Alignment <= llvm::Align(2)) { + + SDLoc dl(Op); + + // If necessary, trunc the value to 32bit + SDValue StoreVal = ST->getOperand(1); + if (ST->isTruncatingStore()) + StoreVal = DAG.getNode(ISD::TRUNCATE, dl, MemVT, ST->getOperand(1)); + + RTLIB::Libcall LC = + (MemVT == MVT::i32) ? RTLIB::AEABI_UWRITE4 : RTLIB::AEABI_UWRITE8; + + MakeLibCallOptions Opts; + auto CallResult = + makeLibCall(DAG, LC, MVT::isVoid, {StoreVal, ST->getBasePtr()}, Opts, + dl, ST->getChain()); + + return CallResult.second; + } + + // Default expand to individual stores + if (!allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Alignment)) + return expandUnalignedStore(ST, DAG); + return SDValue(); +} + static SDValue LowerPredicateLoad(SDValue Op, SelectionDAG &DAG) { LoadSDNode *LD = cast(Op.getNode()); EVT MemVT = LD->getMemoryVT(); @@ -9779,11 +9874,11 @@ void ARMTargetLowering::LowerLOAD(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const { LoadSDNode *LD = cast(N); EVT MemVT = LD->getMemoryVT(); - assert(LD->isUnindexed() && "Loads should be unindexed at this point."); if (MemVT == MVT::i64 && Subtarget->hasV5TEOps() && !Subtarget->isThumb1Only() && LD->isVolatile() && LD->getAlign() >= Subtarget->getDualLoadStoreAlignment()) { + assert(LD->isUnindexed() && "Loads should be unindexed at this point."); SDLoc dl(N); SDValue Result = DAG.getMemIntrinsicNode( ARMISD::LDRD, dl, DAG.getVTList({MVT::i32, MVT::i32, MVT::Other}), @@ -9792,6 +9887,12 @@ void ARMTargetLowering::LowerLOAD(SDNode *N, SmallVectorImpl &Results, SDValue Hi = Result.getValue(DAG.getDataLayout().isLittleEndian() ? 1 : 0); SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); Results.append({Pair, Result.getValue(2)}); + } else if (MemVT == MVT::i32 || MemVT == MVT::i64) { + auto Pair = LowerAEABIUnalignedLoad(SDValue(N, 0), DAG); + if (Pair.first) { + Results.push_back(Pair.first); + Results.push_back(Pair.second); + } } } @@ -9833,15 +9934,15 @@ static SDValue LowerPredicateStore(SDValue Op, SelectionDAG &DAG) { ST->getMemOperand()); } -static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, - const ARMSubtarget *Subtarget) { +SDValue ARMTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG, + const ARMSubtarget *Subtarget) const { StoreSDNode *ST = cast(Op.getNode()); EVT MemVT = ST->getMemoryVT(); - assert(ST->isUnindexed() && "Stores should be unindexed at this point."); if (MemVT == MVT::i64 && Subtarget->hasV5TEOps() && !Subtarget->isThumb1Only() && ST->isVolatile() && ST->getAlign() >= Subtarget->getDualLoadStoreAlignment()) { + assert(ST->isUnindexed() && "Stores should be unindexed at this point."); SDNode *N = Op.getNode(); SDLoc dl(N); @@ -9861,8 +9962,9 @@ static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, ((MemVT == MVT::v2i1 || MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || MemVT == MVT::v16i1))) { return LowerPredicateStore(Op, DAG); + } else if (MemVT == MVT::i32 || MemVT == MVT::i64) { + return LowerAEABIUnalignedStore(Op, DAG); } - return SDValue(); } @@ -10373,29 +10475,43 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { return LowerRESET_FPMODE(Op, DAG); case ISD::MUL: return LowerMUL(Op, DAG); case ISD::SDIV: - if (Subtarget->isTargetWindows() && !Op.getValueType().isVector()) + if (getTargetMachine().getTargetTriple().isOSWindows() && + !Op.getValueType().isVector()) return LowerDIV_Windows(Op, DAG, /* Signed */ true); return LowerSDIV(Op, DAG, Subtarget); case ISD::UDIV: - if (Subtarget->isTargetWindows() && !Op.getValueType().isVector()) + if (getTargetMachine().getTargetTriple().isOSWindows() && + !Op.getValueType().isVector()) return LowerDIV_Windows(Op, DAG, /* Signed */ false); return LowerUDIV(Op, DAG, Subtarget); case ISD::UADDO_CARRY: case ISD::USUBO_CARRY: return LowerUADDSUBO_CARRY(Op, DAG); - case ISD::SADDO: - case ISD::SSUBO: - return LowerSignedALUO(Op, DAG); case ISD::UADDO: case ISD::USUBO: - return LowerUnsignedALUO(Op, DAG); + case ISD::UMULO: + case ISD::SADDO: + case ISD::SSUBO: + case ISD::SMULO: + return LowerALUO(Op, DAG); case ISD::SADDSAT: case ISD::SSUBSAT: case ISD::UADDSAT: case ISD::USUBSAT: return LowerADDSUBSAT(Op, DAG, Subtarget); - case ISD::LOAD: - return LowerPredicateLoad(Op, DAG); + case ISD::LOAD: { + auto *LD = cast(Op); + EVT MemVT = LD->getMemoryVT(); + if (Subtarget->hasMVEIntegerOps() && + (MemVT == MVT::v2i1 || MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || + MemVT == MVT::v16i1)) + return LowerPredicateLoad(Op, DAG); + + auto Pair = LowerAEABIUnalignedLoad(Op, DAG); + if (Pair.first) + return DAG.getMergeValues({Pair.first, Pair.second}, SDLoc(Pair.first)); + return SDValue(); + } case ISD::STORE: return LowerSTORE(Op, DAG, Subtarget); case ISD::MLOAD: @@ -10421,7 +10537,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SDIVREM: case ISD::UDIVREM: return LowerDivRem(Op, DAG); case ISD::DYNAMIC_STACKALLOC: - if (Subtarget->isTargetWindows()) + if (getTargetMachine().getTargetTriple().isOSWindows()) return LowerDYNAMIC_STACKALLOC(Op, DAG); llvm_unreachable("Don't know how to custom lower this!"); case ISD::STRICT_FP_ROUND: @@ -10525,7 +10641,8 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N, return; case ISD::UDIV: case ISD::SDIV: - assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows"); + assert(getTargetMachine().getTargetTriple().isOSWindows() && + "can only expand DIV on Windows"); return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV, Results); case ISD::ATOMIC_CMP_SWAP: @@ -10536,6 +10653,9 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N, case ISD::LOAD: LowerLOAD(N, Results, DAG); break; + case ISD::STORE: + Res = LowerAEABIUnalignedStore(SDValue(N, 0), DAG); + break; case ISD::TRUNCATE: Res = LowerTruncate(N, DAG, Subtarget); break; @@ -11465,7 +11585,7 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI, const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); DebugLoc DL = MI.getDebugLoc(); - assert(Subtarget->isTargetWindows() && + assert(TM.getTargetTriple().isOSWindows() && "__chkstk is only supported on Windows"); assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode"); @@ -19591,31 +19711,45 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, EVT VT; SDValue Ptr; Align Alignment; + unsigned AS = 0; bool isSEXTLoad = false; bool IsMasked = false; if (LoadSDNode *LD = dyn_cast(N)) { Ptr = LD->getBasePtr(); VT = LD->getMemoryVT(); Alignment = LD->getAlign(); + AS = LD->getAddressSpace(); isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; } else if (StoreSDNode *ST = dyn_cast(N)) { Ptr = ST->getBasePtr(); VT = ST->getMemoryVT(); Alignment = ST->getAlign(); + AS = ST->getAddressSpace(); } else if (MaskedLoadSDNode *LD = dyn_cast(N)) { Ptr = LD->getBasePtr(); VT = LD->getMemoryVT(); Alignment = LD->getAlign(); + AS = LD->getAddressSpace(); isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; IsMasked = true; } else if (MaskedStoreSDNode *ST = dyn_cast(N)) { Ptr = ST->getBasePtr(); VT = ST->getMemoryVT(); Alignment = ST->getAlign(); + AS = ST->getAddressSpace(); IsMasked = true; } else return false; + unsigned Fast = 0; + if (!allowsMisalignedMemoryAccesses(VT, AS, Alignment, + MachineMemOperand::MONone, &Fast)) { + // Only generate post-increment or pre-increment forms when a real + // hardware instruction exists for them. Do not emit postinc/preinc + // if the operation will end up as a libcall. + return false; + } + bool isInc; bool isLegal = false; if (VT.isVector()) @@ -20370,7 +20504,7 @@ static TargetLowering::ArgListTy getDivRemArgList( Entry.IsZExt = !isSigned; Args.push_back(Entry); } - if (Subtarget->isTargetWindows() && Args.size() >= 2) + if (Subtarget->getTargetTriple().isOSWindows() && Args.size() >= 2) std::swap(Args[0], Args[1]); return Args; } @@ -20436,7 +20570,7 @@ SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { Type *RetTy = StructType::get(Ty, Ty); - if (Subtarget->isTargetWindows()) + if (getTM().getTargetTriple().isOSWindows()) InChain = WinDBZCheckDenominator(DAG, Op.getNode(), InChain); TargetLowering::CallLoweringInfo CLI(DAG); @@ -20492,7 +20626,7 @@ SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const { SDValue Callee = DAG.getExternalSymbol(LCImpl, getPointerTy(DAG.getDataLayout())); - if (Subtarget->isTargetWindows()) + if (getTM().getTargetTriple().isOSWindows()) InChain = WinDBZCheckDenominator(DAG, N, InChain); // Lower call @@ -20513,7 +20647,8 @@ SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const { SDValue ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const { - assert(Subtarget->isTargetWindows() && "unsupported target platform"); + assert(getTM().getTargetTriple().isOSWindows() && + "unsupported target platform"); SDLoc DL(Op); // Get the inputs. @@ -20681,10 +20816,10 @@ bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment /// specified in the intrinsic calls. -bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void ARMTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { case Intrinsic::arm_neon_vld1: case Intrinsic::arm_neon_vld2: @@ -20707,7 +20842,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = cast(AlignArg)->getMaybeAlignValue(); // volatile loads with NEON intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_neon_vld1x2: case Intrinsic::arm_neon_vld1x3: @@ -20722,7 +20858,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = I.getParamAlign(I.arg_size() - 1).valueOrOne(); // volatile loads with NEON intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_neon_vst1: case Intrinsic::arm_neon_vst2: @@ -20748,7 +20885,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = cast(AlignArg)->getMaybeAlignValue(); // volatile stores with NEON intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_neon_vst1x2: case Intrinsic::arm_neon_vst1x3: @@ -20769,7 +20907,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = I.getParamAlign(0).valueOrOne(); // volatile stores with NEON intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vld2q: case Intrinsic::arm_mve_vld4q: { @@ -20783,7 +20922,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(VecTy->getScalarSizeInBits() / 8); // volatile loads with MVE intrinsics not supported Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vst2q: case Intrinsic::arm_mve_vst4q: { @@ -20797,7 +20937,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(VecTy->getScalarSizeInBits() / 8); // volatile stores with MVE intrinsics not supported Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vldr_gather_base: case Intrinsic::arm_mve_vldr_gather_base_predicated: { @@ -20806,7 +20947,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVT(I.getType()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vldr_gather_base_wb: case Intrinsic::arm_mve_vldr_gather_base_wb_predicated: { @@ -20815,7 +20957,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVT(I.getType()->getContainedType(0)); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vldr_gather_offset: case Intrinsic::arm_mve_vldr_gather_offset_predicated: { @@ -20827,7 +20970,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, DataVT.getVectorNumElements()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vstr_scatter_base: case Intrinsic::arm_mve_vstr_scatter_base_predicated: { @@ -20836,7 +20980,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVT(I.getArgOperand(2)->getType()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vstr_scatter_base_wb: case Intrinsic::arm_mve_vstr_scatter_base_wb_predicated: { @@ -20845,7 +20990,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVT(I.getArgOperand(2)->getType()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_mve_vstr_scatter_offset: case Intrinsic::arm_mve_vstr_scatter_offset_predicated: { @@ -20857,7 +21003,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, DataVT.getVectorNumElements()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_ldaex: case Intrinsic::arm_ldrex: { @@ -20869,7 +21016,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ValTy); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_stlex: case Intrinsic::arm_strex: { @@ -20881,7 +21029,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(ValTy); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::arm_stlexd: case Intrinsic::arm_strexd: @@ -20891,7 +21040,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(8); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::arm_ldaexd: case Intrinsic::arm_ldrexd: @@ -20901,13 +21051,12 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(8); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; default: break; } - - return false; } /// Returns true if it is beneficial to convert a load of a constant @@ -21196,7 +21345,7 @@ bool ARMTargetLowering::isMaskAndCmp0FoldingBeneficial( TargetLowering::ShiftLegalizationStrategy ARMTargetLowering::preferredShiftLegalizationStrategy( SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const { - if (Subtarget->hasMinSize() && !Subtarget->isTargetWindows()) + if (Subtarget->hasMinSize() && !getTM().getTargetTriple().isOSWindows()) return ShiftLegalizationStrategy::LowerToLibcall; return TargetLowering::preferredShiftLegalizationStrategy(DAG, N, ExpansionFactor); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index bc84654f8bd5a..e58d872c548e4 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -317,8 +317,8 @@ class VectorType; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize = false) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; /// Returns true if it is beneficial to convert a load of a constant @@ -567,8 +567,7 @@ class VectorType; SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerALUO(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; @@ -605,10 +604,14 @@ class VectorType; SDValue LowerSPONENTRY(SDValue Op, SelectionDAG &DAG) const; void LowerLOAD(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const; + SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, + const ARMSubtarget *Subtarget) const; + std::pair + LowerAEABIUnalignedLoad(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerAEABIUnalignedStore(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFP_TO_BF16(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCMP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const; - Register getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const override; diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index dc62a09f942e2..572c260b8d92f 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -7403,28 +7403,28 @@ def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>; let Predicates = [HasNEON] in { def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)), (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG - (SHA1H (SUBREG_TO_REG (i64 0), + (SHA1H (INSERT_SUBREG (IMPLICIT_DEF), (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)), ssub_0)), ssub_0)), GPR)>; def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1C v4i32:$hash_abcd, - (SUBREG_TO_REG (i64 0), + (INSERT_SUBREG (IMPLICIT_DEF), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1M v4i32:$hash_abcd, - (SUBREG_TO_REG (i64 0), + (INSERT_SUBREG (IMPLICIT_DEF), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)), (SHA1P v4i32:$hash_abcd, - (SUBREG_TO_REG (i64 0), + (INSERT_SUBREG (IMPLICIT_DEF), (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)), ssub_0), v4i32:$wk)>; diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp index 2d3cb71fbc3fd..c2ee75205d888 100644 --- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -583,16 +583,14 @@ bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I, .addUse(LHSReg) .addUse(RHSReg) .add(predOps(ARMCC::AL)); - if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI); // Read the comparison flags (if necessary). if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) { auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ReadFlagsOpcode)) .add(predOps(ARMCC::AL)); - if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI); } // Select either 1 or the previous result based on the value of the flags. @@ -602,8 +600,7 @@ bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I, .addUse(PrevRes) .addImm(1) .add(predOps(Cond, ARM::CPSR)); - if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI); return true; } @@ -701,21 +698,22 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, .add(predOps(ARMCC::AL)); addGOTMemOperand(MIBLoad); - if (!constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI); } else { addGOTMemOperand(MIB); } } - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } bool isReadOnly = STI.getTargetLowering()->isReadOnly(GV); if (STI.isROPI() && isReadOnly) { unsigned Opc = UseMovt ? Opcodes.MOV_ga_pcrel : Opcodes.LDRLIT_ga_pcrel; MIB->setDesc(TII.get(Opc)); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } if (STI.isRWPI() && !isReadOnly) { auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass); @@ -730,8 +728,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, TII.get(Opcodes.ConstPoolLoad), Offset); addOpsForConstantPoolLoad(OffsetMIB, GV, /*IsSBREL*/ true); } - if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI); // Add the offset to the SB register. MIB->setDesc(TII.get(Opcodes.ADDrr)); @@ -741,7 +738,8 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, .add(predOps(ARMCC::AL)) .add(condCodeOp()); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } if (STI.isTargetELF()) { @@ -763,7 +761,8 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, return false; } - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB, @@ -780,8 +779,7 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB, .addUse(CondReg) .addImm(1) .add(predOps(ARMCC::AL)); - if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI); // Move a value into the result register based on the result of the // comparison. @@ -796,8 +794,7 @@ bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB, .addUse(TrueReg) .addUse(FalseReg) .add(predOps(ARMCC::EQ, ARM::CPSR)); - if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI); MIB->eraseFromParent(); return true; @@ -809,7 +806,8 @@ bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, MIB->setDesc(TII.get(ARM::MOVsr)); MIB.addImm(ShiftOpc); MIB.add(predOps(ARMCC::AL)).add(condCodeOp()); - return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); + return true; } void ARMInstructionSelector::renderVFPF32Imm( @@ -900,8 +898,7 @@ bool ARMInstructionSelector::select(MachineInstr &I) { .addImm(0) .add(predOps(ARMCC::AL)) .add(condCodeOp()); - if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI); } break; } @@ -948,8 +945,7 @@ bool ARMInstructionSelector::select(MachineInstr &I) { .addDef(IgnoredBits) .addUse(SrcReg) .add(predOps(ARMCC::AL)); - if (!constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI); MIB->eraseFromParent(); return true; @@ -1116,8 +1112,7 @@ bool ARMInstructionSelector::select(MachineInstr &I) { .addImm(0) .add(predOps(ARMCC::AL)) .addMemOperand(&MemOp); - if (!constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI); I.eraseFromParent(); return true; } @@ -1157,16 +1152,14 @@ bool ARMInstructionSelector::select(MachineInstr &I) { .addReg(I.getOperand(0).getReg()) .addImm(1) .add(predOps(ARMCC::AL)); - if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Test, TII, TRI, RBI); // Branch conditionally. auto Branch = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc)) .add(I.getOperand(1)) .add(predOps(ARMCC::NE, ARM::CPSR)); - if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI); I.eraseFromParent(); return true; } @@ -1185,5 +1178,6 @@ bool ARMInstructionSelector::select(MachineInstr &I) { return false; } - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 590d4c70592f8..d74d7737995a1 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -230,7 +230,7 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { if (F.hasMinSize()) Key += "+minsize"; - DenormalMode DM = F.getDenormalModeRaw(); + DenormalMode DM = F.getDenormalFPEnv().DefaultMode; if (DM != DenormalMode::getIEEE()) Key += "denormal-fp-math=" + DM.str(); diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp index 50b30bb97f19e..fd26345920a71 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -812,7 +812,7 @@ SDValue BPFTargetLowering::LowerTRAP(SDValue Op, SelectionDAG &DAG) const { CLI.IsTailCall = false; CLI.CallConv = CallingConv::C; CLI.IsVarArg = false; - CLI.DL = DL; + CLI.DL = std::move(DL); CLI.NoMerge = false; CLI.DoesNotReturn = true; return LowerCall(CLI, InVals); diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td index bdacf9cc3a6ab..3d2050e26ca0d 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.td +++ b/llvm/lib/Target/BPF/BPFInstrInfo.td @@ -1343,17 +1343,17 @@ let Predicates = [BPFHasALU32] in { } def : Pat<(i64 (zextloadi8 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDB32 ADDRri:$src), sub_32)>; def : Pat<(i64 (zextloadi16 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDH32 ADDRri:$src), sub_32)>; def : Pat<(i64 (zextloadi32 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDW32 ADDRri:$src), sub_32)>; def : Pat<(i64 (extloadi8 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDB32 ADDRri:$src), sub_32)>; def : Pat<(i64 (extloadi16 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDH32 ADDRri:$src), sub_32)>; def : Pat<(i64 (extloadi32 ADDRri:$src)), - (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; + (SUBREG_TO_REG (LDW32 ADDRri:$src), sub_32)>; let Predicates = [BPFHasLoadAcqStoreRel] in { foreach P = [[relaxed_load, LDW32], diff --git a/llvm/lib/Target/BPF/BPFMIPeephole.cpp b/llvm/lib/Target/BPF/BPFMIPeephole.cpp index 6275d5b7721c6..b8e4db78955f5 100644 --- a/llvm/lib/Target/BPF/BPFMIPeephole.cpp +++ b/llvm/lib/Target/BPF/BPFMIPeephole.cpp @@ -227,7 +227,8 @@ bool BPFMIPeephole::eliminateZExtSeq() { } BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg) - .addImm(0).addReg(SubReg).addImm(BPF::sub_32); + .addReg(SubReg) + .addImm(BPF::sub_32); SllMI->eraseFromParent(); MovMI->eraseFromParent(); @@ -278,7 +279,8 @@ bool BPFMIPeephole::eliminateZExt() { // Build a SUBREG_TO_REG instruction. BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), dst) - .addImm(0).addReg(src).addImm(BPF::sub_32); + .addReg(src) + .addImm(BPF::sub_32); ToErase = &MI; Eliminated = true; diff --git a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp index c9b1cbc7ae959..9d6de2044b2b6 100644 --- a/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp +++ b/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp @@ -197,7 +197,7 @@ void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, // We can optimize such a pattern: // %1:gpr = LD_imm64 @"llvm.s:0:4$0:2" // %2:gpr32 = LDW32 %1:gpr, 0 - // %3:gpr = SUBREG_TO_REG 0, %2:gpr32, %subreg.sub_32 + // %3:gpr = SUBREG_TO_REG %2:gpr32, %subreg.sub_32 // %4:gpr = ADD_rr %0:gpr, %3:gpr // or similar patterns below for non-alu32 case. auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp index 4d9b1b5d7d7a5..46a1df28b8f1d 100644 --- a/llvm/lib/Target/BPF/BTFDebug.cpp +++ b/llvm/lib/Target/BPF/BTFDebug.cpp @@ -1125,7 +1125,7 @@ std::string BTFDebug::populateFileContent(const DIFile *File) { for (line_iterator I(*Buf, false), E; I != E; ++I) Content.push_back(std::string(*I)); - FileContent[FileName] = Content; + FileContent[FileName] = std::move(Content); return FileName; } diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td index 4c1456fd5abb8..8751484496395 100644 --- a/llvm/lib/Target/DirectX/DXIL.td +++ b/llvm/lib/Target/DirectX/DXIL.td @@ -1124,6 +1124,30 @@ def WaveActiveOp : DXILOp<119, waveActiveOp> { let attributes = [Attributes]; } +def WavePrefixOp : DXILOp<121, wavePrefixOp> { + let Doc = "returns partial result of the computation in the corresponding lane"; + let intrinsics = [ + IntrinSelect, IntrinArgI8, + IntrinArgI8 + ]>, + IntrinSelect, IntrinArgI8, + IntrinArgI8 + ]>, + ]; + + let arguments = [OverloadTy, Int8Ty, Int8Ty]; + let result = OverloadTy; + let overloads = [ + Overloads + ]; + let stages = [Stages]; + let attributes = [Attributes]; +} + def WavePrefixBitCount : DXILOp<136, wavePrefixOp> { let Doc = "returns the count of bits of Expr set to 1 on prior lanes"; let intrinsics = [IntrinSelect]; diff --git a/llvm/lib/Target/DirectX/DXILDataScalarization.cpp b/llvm/lib/Target/DirectX/DXILDataScalarization.cpp index b752c49c75dbf..1e069e24e0ade 100644 --- a/llvm/lib/Target/DirectX/DXILDataScalarization.cpp +++ b/llvm/lib/Target/DirectX/DXILDataScalarization.cpp @@ -367,18 +367,14 @@ static Constant *transformInitializer(Constant *Init, Type *OrigType, if (isa(OrigType) && isa(NewType)) { // Convert vector initializer to array initializer SmallVector ArrayElements; - if (ConstantVector *ConstVecInit = dyn_cast(Init)) { - for (unsigned I = 0; I < ConstVecInit->getNumOperands(); ++I) - ArrayElements.push_back(ConstVecInit->getOperand(I)); - } else if (ConstantDataVector *ConstDataVecInit = - llvm::dyn_cast(Init)) { - for (unsigned I = 0; I < ConstDataVecInit->getNumElements(); ++I) - ArrayElements.push_back(ConstDataVecInit->getElementAsConstant(I)); - } else { - assert(false && "Expected a ConstantVector or ConstantDataVector for " - "vector initializer!"); - } + unsigned E = cast(OrigType)->getNumElements(); + for (unsigned I = 0; I != E; ++I) + if (Constant *Elt = Init->getAggregateElement(I)) + ArrayElements.push_back(Elt); + + assert(ArrayElements.size() == E && + "Expected fixed length constant aggregate for vector initializer!"); return ConstantArray::get(cast(NewType), ArrayElements); } diff --git a/llvm/lib/Target/DirectX/DXILShaderFlags.cpp b/llvm/lib/Target/DirectX/DXILShaderFlags.cpp index 57a6097aedcc0..54cf56f92277b 100644 --- a/llvm/lib/Target/DirectX/DXILShaderFlags.cpp +++ b/llvm/lib/Target/DirectX/DXILShaderFlags.cpp @@ -97,6 +97,9 @@ static bool checkWaveOps(Intrinsic::ID IID) { case Intrinsic::dx_wave_reduce_umax: case Intrinsic::dx_wave_reduce_min: case Intrinsic::dx_wave_reduce_umin: + // Wave Prefix Op Variants + case Intrinsic::dx_wave_prefix_sum: + case Intrinsic::dx_wave_prefix_usum: return true; } } diff --git a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp index 48a9085820471..57b94ebe19375 100644 --- a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp +++ b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp @@ -2016,7 +2016,7 @@ void DXILBitcodeWriter::writeConstants(unsigned FirstVal, unsigned LastVal, } } else if (const ConstantFP *CFP = dyn_cast(C)) { Code = bitc::CST_CODE_FLOAT; - Type *Ty = CFP->getType(); + Type *Ty = CFP->getType()->getScalarType(); if (Ty->isHalfTy() || Ty->isFloatTy() || Ty->isDoubleTy()) { Record.push_back(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); } else if (Ty->isX86_FP80Ty()) { diff --git a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp index 23f45b5fe2270..4d6f6d6472b25 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp +++ b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp @@ -61,9 +61,11 @@ bool DirectXTTIImpl::isTargetIntrinsicTriviallyScalarizable( case Intrinsic::dx_wave_reduce_max: case Intrinsic::dx_wave_reduce_min: case Intrinsic::dx_wave_reduce_sum: + case Intrinsic::dx_wave_prefix_sum: case Intrinsic::dx_wave_reduce_umax: case Intrinsic::dx_wave_reduce_umin: case Intrinsic::dx_wave_reduce_usum: + case Intrinsic::dx_wave_prefix_usum: case Intrinsic::dx_imad: case Intrinsic::dx_umad: case Intrinsic::dx_ddx_coarse: diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt b/llvm/lib/Target/Hexagon/CMakeLists.txt index 85ec5c7c2d45e..bd87b9c894292 100644 --- a/llvm/lib/Target/Hexagon/CMakeLists.txt +++ b/llvm/lib/Target/Hexagon/CMakeLists.txt @@ -38,6 +38,8 @@ add_llvm_target(HexagonCodeGen HexagonGenMemAbsolute.cpp HexagonGenMux.cpp HexagonGenPredicate.cpp + HexagonGlobalRegion.cpp + HexagonLiveVariables.cpp HexagonHardwareLoops.cpp HexagonHazardRecognizer.cpp HexagonInstrInfo.cpp diff --git a/llvm/lib/Target/Hexagon/Hexagon.h b/llvm/lib/Target/Hexagon/Hexagon.h index 422ab20891b94..b3be89abd527b 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.h +++ b/llvm/lib/Target/Hexagon/Hexagon.h @@ -26,6 +26,7 @@ class Pass; extern char &HexagonCopyHoistingID; extern char &HexagonExpandCondsetsID; extern char &HexagonTfrCleanupID; +extern char &HexagonLiveVariablesID; void initializeHexagonAsmPrinterPass(PassRegistry &); void initializeHexagonBitSimplifyPass(PassRegistry &); void initializeHexagonBranchRelaxationPass(PassRegistry &); @@ -41,6 +42,7 @@ void initializeHexagonExpandCondsetsPass(PassRegistry &); void initializeHexagonGenMemAbsolutePass(PassRegistry &); void initializeHexagonGenMuxPass(PassRegistry &); void initializeHexagonHardwareLoopsPass(PassRegistry &); +void initializeHexagonLiveVariablesPass(PassRegistry &); void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); void initializeHexagonLoopAlignPass(PassRegistry &); void initializeHexagonLoopReschedulingPass(PassRegistry &); diff --git a/llvm/lib/Target/Hexagon/HexagonGlobalRegion.cpp b/llvm/lib/Target/Hexagon/HexagonGlobalRegion.cpp new file mode 100644 index 0000000000000..836e1a0db8909 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonGlobalRegion.cpp @@ -0,0 +1,252 @@ +//===-- HexagonGlobalRegion.cpp - VLIW global scheduling infrastructure ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Basic infrastructure for global scheduling. Liveness update. +// This is the least complete portion. Basically it is empty infrastructure +// to be extended and improved. +// Currently in place only trace region formation routines and non fully +// functional skeleton for incremental liveness update. +// +//===----------------------------------------------------------------------===// +#define DEBUG_TYPE "global_sched" +#include "HexagonGlobalRegion.h" +#include "HexagonTargetMachine.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +LivenessInfo::LivenessInfo(const TargetInstrInfo *TII, + const TargetRegisterInfo *TRI, + MachineBasicBlock *MBB) + : TII(TII), TRI(TRI) { + LiveIns.resize(TRI->getNumRegs()); + LiveOuts.resize(TRI->getNumRegs()); + + LiveIns.reset(); + LiveOuts.reset(); + + // Live-ins are simple, just copy from MBB. + for (const auto &LI : MBB->liveins()) + setUsed(LiveIns, LI.PhysReg); + + // Live-outs are concatenation of all the BB successors. + // As of now, we are only dealing with a-cyclic regions + // with side exits, but no side entrances. + for (const MachineBasicBlock *Succ : MBB->successors()) + for (const auto &LI : Succ->liveins()) + setUsed(LiveOuts, LI.PhysReg); +} + +// Pessimistically check if at least one def of this register in this +// instruction (bundle or not) is done under predication. +static bool isPredicatedDef(MachineInstr *MI, unsigned Reg, + const HexagonInstrInfo *QII) { + if (!MI->isBundle()) + return QII->isPredicated(*MI); + MachineBasicBlock *Parent = MI->getParent(); + if (!Parent) + return false; + MachineBasicBlock::instr_iterator MII = MI->getIterator(); + MachineBasicBlock::instr_iterator MIIE = Parent->instr_end(); + for (++MII; MII != MIIE && MII->isInsideBundle(); ++MII) { + if (!QII->isPredicated(*MII)) + continue; + for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MII->getOperand(i); + if (!MO.isReg()) + continue; + if (MO.isDef() && !MO.isDead() && MO.getReg() == Reg) { + LLVM_DEBUG(dbgs() << "\t\tCond def: "; MII->dump()); + return true; + } + } + } + return false; +} + +/// Determine def/use set for MI. +/// Beware, if def is conditional, like here: +/// BUNDLE %PC, %R0, %P0, %R16 +/// * %R0 = LDriuh_cdnNotPt %P0, %R16, 0; +/// * %P0 = C2_cmpeqi %R16, 0; +/// It is not a statefull definition of R0. +/// +void LivenessInfo::parseOperands(MachineInstr *MI, BitVector &Gen, + BitVector &Kill, BitVector &Use) { + const auto *QII = static_cast(TII); + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg()) + continue; + // If it is a predicated instruction, it may, or may not + // be setting its destination, and we do not know it + // at the compile time. + if (MO.isDef() && !MO.isDead()) { + if (isPredicatedDef(MI, MO.getReg(), QII)) + LLVM_DEBUG(dbgs() << "\tConditional define of " + << printReg(MO.getReg(), TRI) << " in "; + MI->dump()); + else + setUsed(Gen, MO.getReg()); + } + if (MO.isKill()) + setUsed(Kill, MO.getReg()); + if (MO.isUse()) + setUsed(Use, MO.getReg()); + } +} + +void LivenessInfo::parseOperandsWithReset(MachineInstr *MI, BitVector &Gen, + BitVector &Kill, BitVector &Use) { + Gen.reset(); + Use.reset(); + Kill.reset(); + parseOperands(MI, Gen, Kill, Use); +} + +/// setUsed - Set the register and its sub-registers as being used. +/// Taken from RegScavenger::setUsed(). +void LivenessInfo::setUsed(BitVector &Set, unsigned Reg) { + Set.set(Reg); + + for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) + Set.set(*SubRegs); +} + +#ifndef NDEBUG +static void dumpRI(const TargetRegisterInfo *TRI, BitVector &Set) { + for (unsigned i = 0; i < Set.size(); i++) + if (Set.test(i)) + LLVM_DEBUG(dbgs() << " " << printReg(i, TRI)); +} +#endif + +// This function incrementally updates liveness for the given BB. +// First it gathers LiveOut set, and then iterates bottom-up +// over bundles/instructions while updating live set. +void LivenessInfo::UpdateLiveness(MachineBasicBlock *MBB) { + BitVector NewLiveIns(TRI->getNumRegs()); + BitVector NewLiveOuts(TRI->getNumRegs()); + BitVector LiveIns(TRI->getNumRegs()); + BitVector LocalGen(TRI->getNumRegs()); + BitVector LocalUse(TRI->getNumRegs()); + BitVector LocalKill(TRI->getNumRegs()); + + NewLiveIns.reset(); + NewLiveOuts.reset(); + + LLVM_DEBUG(dbgs() << "\n\t\tUpdateLiveness for BB(" << MBB->getNumber() + << ")\n"); + + // Original Live-ins are simple, just copy from MBB. + for (const auto &LI : MBB->liveins()) + setUsed(NewLiveIns, LI.PhysReg); + + // Live-outs are concatenation of all the BB successors. + // As of now, we are only dealing with a-cyclic regions + // with side exits, but no side entrances. + for (const MachineBasicBlock *Succ : MBB->successors()) + for (const auto &LI : Succ->liveins()) + setUsed(NewLiveOuts, LI.PhysReg); + + LiveIns = NewLiveIns; + // This needs to be a sequential walk, not parallel update. + LLVM_DEBUG(dbgs() << "\t\tOriginal live ins :\t"; dumpRI(TRI, NewLiveIns); + dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\t\tOriginal live outs:\t"; dumpRI(TRI, NewLiveOuts); + dbgs() << "\n"); + + NewLiveIns = NewLiveOuts; + // Scan BB backwards to get exposed uses. + // TODO: Handle predicates if needed. + std::vector BundleList; + for (MachineBasicBlock::iterator MI = MBB->begin(), MIE = MBB->end(); + MI != MIE; ++MI) + if (!MI->isDebugInstr()) + BundleList.push_back(&*MI); + + while (!BundleList.empty()) { + MachineInstr *MI = BundleList.back(); + BundleList.pop_back(); + parseOperandsWithReset(MI, LocalGen, LocalKill, LocalUse); + LLVM_DEBUG(dbgs() << "\t\tIncr gen:\t"; dumpRI(TRI, LocalGen); + dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "\t\tIncr use:\t"; dumpRI(TRI, LocalUse); + dbgs() << "\n"); + // NewLiveIns = (NewLiveIns - LocalGen) U LocalUse. + BitVector NotGen(LocalGen); + NotGen.flip(); + NewLiveIns &= NotGen; + NewLiveIns |= LocalUse; + } + + LLVM_DEBUG(dbgs() << "\t\tAnswer:\t"; dumpRI(TRI, NewLiveIns); + dbgs() << "\n"); + + // TODO: Consider implementing a register aliasing filter if duplicate + // live-in entries become problematic. + + // Set new live in. + LLVM_DEBUG(dbgs() << "\t\tNew LiveIn :\t"); + + for (unsigned i = 0; i < LiveIns.size(); ++i) { + if (NewLiveIns.test(i)) + LLVM_DEBUG(dbgs() << " " << printReg(i, TRI)); + if (LiveIns.test(i) == NewLiveIns.test(i)) + continue; + if (LiveIns.test(i)) + MBB->removeLiveIn(i); + if (NewLiveIns.test(i)) + MBB->addLiveIn(i); + } + LLVM_DEBUG(dbgs() << "\n"); +} + +void LivenessInfo::dump() { + for (unsigned i = 0; i < LiveIns.size(); i++) + if (LiveIns.test(i)) + LLVM_DEBUG(dbgs() << "\t\tlive-in: " << printReg(i, TRI) << "\n"); + for (unsigned i = 0; i < LiveOuts.size(); i++) + if (LiveOuts.test(i)) + LLVM_DEBUG(dbgs() << "\t\tlive-out: " << printReg(i, TRI) << "\n"); +} + +/// +/// BasicBlockRegion Methods. +/// +BasicBlockRegion::BasicBlockRegion(const TargetInstrInfo *TII, + const TargetRegisterInfo *TRI, + MachineBasicBlock *MBB) + : TII(TII), TRI(TRI) { + // Should be the root BB. + Elements.push_back(MBB); + ElementIndex[MBB] = 0; + LiveInfo[MBB] = std::make_unique(TII, TRI, MBB); +} + +BasicBlockRegion::~BasicBlockRegion() { + LiveInfo.clear(); + Elements.clear(); + ElementIndex.clear(); +} + +LivenessInfo *BasicBlockRegion::getLivenessInfoForBB(MachineBasicBlock *MBB) { + auto It = LiveInfo.find(MBB); + assert(It != LiveInfo.end() && "Missing Liveness info"); + assert(It->second && "Missing Liveness info"); + return It->second.get(); +} + +void BasicBlockRegion::addBBtoRegion(MachineBasicBlock *MBB) { + // It is OK to have duplicates if we reparse for additional BBs. + if (LiveInfo.find(MBB) != LiveInfo.end()) + return; + ElementIndex[MBB] = static_cast(Elements.size()); + Elements.push_back(MBB); + LiveInfo[MBB] = std::make_unique(TII, TRI, MBB); +} diff --git a/llvm/lib/Target/Hexagon/HexagonGlobalRegion.h b/llvm/lib/Target/Hexagon/HexagonGlobalRegion.h new file mode 100644 index 0000000000000..bb4bffa96306d --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonGlobalRegion.h @@ -0,0 +1,109 @@ +//===-- HexagonGlobalRegion.h - VLIW global scheduling infrastructure -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Basic infrastructure for global scheduling. +// +//===----------------------------------------------------------------------===// + +#ifndef HEXAGON_GLOBAL_REGION_H +#define HEXAGON_GLOBAL_REGION_H + +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Target/TargetMachine.h" + +#include +#include +#include + +namespace llvm { +/// Class to track incremental liveness update. +class LivenessInfo { + const TargetInstrInfo *TII; + const TargetRegisterInfo *TRI; + BitVector LiveIns; + BitVector LiveOuts; + +public: + LivenessInfo(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, + MachineBasicBlock *MBB); + ~LivenessInfo() {} + void parseOperands(MachineInstr *MI, BitVector &Gen, BitVector &Kill, + BitVector &Use); + void parseOperandsWithReset(MachineInstr *MI, BitVector &Gen, BitVector &Kill, + BitVector &Use); + void setUsed(BitVector &Set, unsigned Reg); + // Update Liveness for BB. + void UpdateLiveness(MachineBasicBlock *MBB); + void dump(); +}; + +/// Generic sequence of BBs. A trace or SB. +/// Maintains its own liveness info. +class BasicBlockRegion { + const TargetInstrInfo *TII; + const TargetRegisterInfo *TRI; + // Sequence of BBs in a larger block. + std::vector Elements; + std::map> LiveInfo; + llvm::DenseMap ElementIndex; + +public: + BasicBlockRegion(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, + MachineBasicBlock *MBB); + ~BasicBlockRegion(); + + void addBBtoRegion(MachineBasicBlock *MBB); + + MachineBasicBlock *getEntryBB() { return Elements.front(); } + + MachineBasicBlock *findMBB(MachineBasicBlock *MBB) { + return ElementIndex.find(MBB) != ElementIndex.end() ? MBB : nullptr; + } + + void RemoveBBFromRegion(MachineBasicBlock *MBB) { + auto It = ElementIndex.find(MBB); + if (It == ElementIndex.end()) + return; + unsigned Index = It->second; + Elements.erase(Elements.begin() + Index); + ElementIndex.erase(It); + LiveInfo.erase(MBB); + for (unsigned I = Index, E = static_cast(Elements.size()); I != E; + ++I) + ElementIndex[Elements[I]] = I; + } + + MachineBasicBlock *findNextMBB(MachineBasicBlock *MBB) { + auto It = ElementIndex.find(MBB); + if (It == ElementIndex.end()) + return nullptr; + unsigned Next = It->second + 1; + if (Next >= Elements.size()) + return nullptr; + return Elements[Next]; + } + + unsigned size() { return static_cast(Elements.size()); } + + std::vector::iterator getRootMBB() { + return Elements.begin(); + } + + std::vector::iterator getLastMBB() { + return Elements.end(); + } + + LivenessInfo *getLivenessInfoForBB(MachineBasicBlock *MBB); +}; +} // namespace llvm + +#endif diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index eadf02043841e..017a4fe85002e 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1785,7 +1785,8 @@ static bool isOpcodeHandled(const SDNode *N) { case ISD::SHL: // We only handle constant shifts because these can be easily flattened // into multiplications by 2^Op1. - return isa(N->getOperand(1).getNode()); + return N->getNumOperands() >= 2 && + isa(N->getOperand(1).getNode()); default: return false; } @@ -1909,7 +1910,7 @@ WeightedLeaf LeafPrioQueue::findSHL(uint64_t MaxAmount) { for (int Pos = 0, End = Q.size(); Pos != End; ++Pos) { const WeightedLeaf &L = Q[Pos]; const SDValue &Val = L.Value; - if (Val.getOpcode() != ISD::SHL || + if (Val.getOpcode() != ISD::SHL || Val.getNumOperands() < 2 || !isa(Val.getOperand(1)) || Val.getConstantOperandVal(1) > MaxAmount) continue; @@ -1936,7 +1937,7 @@ WeightedLeaf LeafPrioQueue::findMULbyConst() { for (int Pos = 0, End = Q.size(); Pos != End; ++Pos) { const WeightedLeaf &L = Q[Pos]; const SDValue &Val = L.Value; - if (Val.getOpcode() != ISD::MUL || + if (Val.getOpcode() != ISD::MUL || Val.getNumOperands() < 2 || !isa(Val.getOperand(1)) || Val.getConstantOperandVal(1) > 127) continue; @@ -1957,6 +1958,8 @@ WeightedLeaf LeafPrioQueue::findMULbyConst() { } SDValue HexagonDAGToDAGISel::getMultiplierForSHL(SDNode *N) { + if (N->getNumOperands() < 2) + return SDValue(); uint64_t MulFactor = 1ull << N->getConstantOperandVal(1); return CurDAG->getConstant(MulFactor, SDLoc(N), N->getOperand(1).getValueType()); @@ -1965,6 +1968,8 @@ SDValue HexagonDAGToDAGISel::getMultiplierForSHL(SDNode *N) { /// @returns the value x for which 2^x is a factor of Val static unsigned getPowerOf2Factor(SDValue Val) { if (Val.getOpcode() == ISD::MUL) { + if (Val.getNumOperands() < 2) + return 0; unsigned MaxFactor = 0; for (int i = 0; i < 2; ++i) { ConstantSDNode *C = dyn_cast(Val.getOperand(i)); @@ -1977,7 +1982,8 @@ static unsigned getPowerOf2Factor(SDValue Val) { return MaxFactor; } if (Val.getOpcode() == ISD::SHL) { - if (!isa(Val.getOperand(1).getNode())) + if (Val.getNumOperands() < 2 || + !isa(Val.getOperand(1).getNode())) return 0; return (unsigned) Val.getConstantOperandVal(1); } @@ -1988,6 +1994,8 @@ static unsigned getPowerOf2Factor(SDValue Val) { /// @returns true if V>>Amount will eliminate V's operation on its child static bool willShiftRightEliminate(SDValue V, unsigned Amount) { if (V.getOpcode() == ISD::MUL) { + if (V.getNumOperands() < 2) + return false; SDValue Ops[] = { V.getOperand(0), V.getOperand(1) }; for (int i = 0; i < 2; ++i) if (isa(Ops[i].getNode()) && @@ -1996,6 +2004,9 @@ static bool willShiftRightEliminate(SDValue V, unsigned Amount) { return (NewConst == 1); } } else if (V.getOpcode() == ISD::SHL) { + if (V.getNumOperands() < 2 || + !isa(V.getOperand(1).getNode())) + return false; return (Amount == V.getConstantOperandVal(1)); } @@ -2003,6 +2014,10 @@ static bool willShiftRightEliminate(SDValue V, unsigned Amount) { } SDValue HexagonDAGToDAGISel::factorOutPowerOf2(SDValue V, unsigned Power) { + // Ensure the node has at least 2 operands before accessing them. + if (V.getNumOperands() < 2) + return V; + SDValue Ops[] = { V.getOperand(0), V.getOperand(1) }; if (V.getOpcode() == ISD::MUL) { for (int i=0; i < 2; ++i) { @@ -2017,6 +2032,8 @@ SDValue HexagonDAGToDAGISel::factorOutPowerOf2(SDValue V, unsigned Power) { } } } else if (V.getOpcode() == ISD::SHL) { + if (!isa(V.getOperand(1).getNode())) + return V; uint64_t ShiftAmount = V.getConstantOperandVal(1); if (ShiftAmount == Power) return Ops[0]; @@ -2066,6 +2083,9 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { assert(isOpcodeHandled(N)); + if (N->getNumOperands() < 2) + return SDValue(N, 0); + SDValue Op0 = N->getOperand(0); SDValue Op1 = N->getOperand(1); @@ -2080,7 +2100,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { } else Weight = getWeight(Op0N); - SDNode *Op1N = N->getOperand(1).getNode(); // Op1 may have been RAUWd + SDNode *Op1N = Op1.getNode(); if (isOpcodeHandled(Op1N) && RootWeights[Op1N] == -1) { Weight += getWeight(balanceSubTree(Op1N).getNode()); // Weight += calculateWeight(Op1N); @@ -2088,8 +2108,18 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { Weight += getWeight(Op1N); RootWeights[N] = Weight; - RootHeights[N] = std::max(getHeight(N->getOperand(0).getNode()), - getHeight(N->getOperand(1).getNode())) + 1; + + // After recursive calls, check if Op0/Op1 are still valid before getting + // height + int Height0 = 0, Height1 = 0; + if (isOpcodeHandled(Op0N) && RootWeights.count(Op0N) && + RootWeights[Op0N] >= 0) + Height0 = getHeight(Op0N); + if (isOpcodeHandled(Op1N) && RootWeights.count(Op1N) && + RootWeights[Op1N] >= 0) + Height1 = getHeight(Op1N); + + RootHeights[N] = std::max(Height0, Height1) + 1; LLVM_DEBUG(dbgs() << "--> No need to balance root (Weight=" << Weight << " Height=" << RootHeights[N] << "): "); @@ -2121,9 +2151,9 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { bool HaveTopLevelShift = false; if (TopLevel && ((isOpcodeHandled(Op0.getNode()) && Op0.getOpcode() == ISD::SHL && - Op0.getConstantOperandVal(1) < 4) || + Op0.getNumOperands() >= 2 && Op0.getConstantOperandVal(1) < 4) || (isOpcodeHandled(Op1.getNode()) && Op1.getOpcode() == ISD::SHL && - Op1.getConstantOperandVal(1) < 4))) + Op1.getNumOperands() >= 2 && Op1.getConstantOperandVal(1) < 4))) HaveTopLevelShift = true; // Flatten the subtree into an ordered list of leaves; at the same time @@ -2194,11 +2224,21 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { assert(ChildOpcode == NOpcode || (NOpcode == ISD::MUL && ChildOpcode == ISD::SHL)); + if (Child->getNumOperands() < 2) { + // Treat as a leaf if not enough operands + int Weight = getWeight(Child.getNode()); + NodeHeights[Child] = getHeight(Child.getNode()); + CurrentWeight += Weight; + Leaves.push(WeightedLeaf(Child, Weight, InsertionOrder++)); + continue; + } + // Convert SHL to MUL SDValue Op1; - if (ChildOpcode == ISD::SHL) + if (ChildOpcode == ISD::SHL) { Op1 = getMultiplierForSHL(Child.getNode()); - else + assert(Op1.getNode() && "getMultiplierForSHL returned null"); + } else Op1 = Child->getOperand(1); if (!NodeHeights.count(Op1) || !NodeHeights.count(Child->getOperand(0))) { @@ -2253,7 +2293,8 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { // amount of additional constant extenders introduced by this optimization. bool CombinedGA = false; if (NOpcode == ISD::ADD && GA.Value.getNode() && Leaves.hasConst() && - GA.Value.hasOneUse() && N->use_size() < 3) { + GA.Value.hasOneUse() && N->use_size() < 3 && + GA.Value.getNumOperands() >= 1) { GlobalAddressSDNode *GANode = cast(GA.Value.getOperand(0)); ConstantSDNode *Offset = cast(Leaves.top().Value); @@ -2379,7 +2420,7 @@ SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) { int Height = NodeHeights[NewRoot]; // Restore SHL if we earlier converted it to a MUL - if (NewRoot.getOpcode() == ISD::MUL) { + if (NewRoot.getOpcode() == ISD::MUL && NewRoot->getNumOperands() >= 2) { ConstantSDNode *V1C = dyn_cast(NewRoot.getOperand(1)); if (V1C && V1C->getAPIntValue().isPowerOf2()) { EVT VT = NewRoot.getValueType(); @@ -2430,6 +2471,9 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() { // FindRoots SmallVector Worklist; + if (BasePtr->getNumOperands() < 2) + continue; + Worklist.push_back(BasePtr.getOperand(0).getNode()); Worklist.push_back(BasePtr.getOperand(1).getNode()); @@ -2440,6 +2484,9 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() { if (!isOpcodeHandled(N)) continue; + if (N->getNumOperands() < 2) + continue; + Worklist.push_back(N->getOperand(0).getNode()); Worklist.push_back(N->getOperand(1).getNode()); @@ -2455,12 +2502,15 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() { RootWeights[BasePtr.getNode()] = -1; SDValue NewBasePtr = balanceSubTree(BasePtr.getNode(), /*TopLevel=*/ true); - if (N->getOpcode() == ISD::LOAD) - N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), - NewBasePtr, N->getOperand(2)); - else - N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), - NewBasePtr, N->getOperand(3)); + if (N->getOpcode() == ISD::LOAD) { + if (N->getNumOperands() >= 3) + N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewBasePtr, + N->getOperand(2)); + } else { + if (N->getNumOperands() >= 4) + N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), + NewBasePtr, N->getOperand(3)); + } LLVM_DEBUG(dbgs() << "--> Final node: "); LLVM_DEBUG(N->dump(CurDAG)); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 9557f31957ded..87c31eba8e9b9 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2026,13 +2026,12 @@ static Value *getUnderLyingObjectForBrevLdIntr(Value *V) { } /// Given an intrinsic, checks if on the target the intrinsic will need to map -/// to a MemIntrinsicNode (touches memory). If this is the case, it returns -/// true and store the intrinsic information into the IntrinsicInfo that was -/// passed to the function. -bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +/// to a MemIntrinsicNode (touches memory). If this is the case, it stores +/// the intrinsic information into the Infos vector. +void HexagonTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { case Intrinsic::hexagon_L2_loadrd_pbr: case Intrinsic::hexagon_L2_loadri_pbr: @@ -2055,7 +2054,8 @@ bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = DL.getABITypeAlign(Info.memVT.getTypeForEVT(Cont)); Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::hexagon_V6_vgathermw: case Intrinsic::hexagon_V6_vgathermw_128B: @@ -2079,15 +2079,14 @@ bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8); - Info.flags = MachineMemOperand::MOLoad | - MachineMemOperand::MOStore | + Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } default: break; } - return false; } bool HexagonTargetLowering::hasBitTest(SDValue X, SDValue Y) const { @@ -2343,9 +2342,18 @@ HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) default: llvm_unreachable("Unexpected shift opcode"); } + if (SDValue Sp = getSplatValue(Op.getOperand(1), DAG)) { + const SDLoc dl(Op); + // Canonicalize shift amount to i32 as required. + SDValue Sh = Sp; + if (Sh.getValueType() != MVT::i32) + Sh = DAG.getZExtOrTrunc(Sh, dl, MVT::i32); + + assert(Sh.getValueType() == MVT::i32 && + "Hexagon vector shift-by-int must use i32 shift operand"); + return DAG.getNode(NewOpc, dl, ty(Op), Op.getOperand(0), Sh); + } - if (SDValue Sp = getSplatValue(Op.getOperand(1), DAG)) - return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), Sp); return SDValue(); } diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index d576de4049e6b..f882fe03d465a 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -49,8 +49,8 @@ class HexagonTargetLowering : public TargetLowering { const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, SelectionDAG& DAG) const; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; bool isTruncateFree(Type *Ty1, Type *Ty2) const override; diff --git a/llvm/lib/Target/Hexagon/HexagonLiveVariables.cpp b/llvm/lib/Target/Hexagon/HexagonLiveVariables.cpp new file mode 100644 index 0000000000000..62ce823a58b99 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonLiveVariables.cpp @@ -0,0 +1,914 @@ + +//===----------------- HexagonLiveVariables.cpp ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Hexagon Live Variable Analysis +// This file implements the Hexagon specific LiveVariables analysis pass. +// This pass recomputes physical register liveness and updates live-ins for +// non-entry blocks based on use/def information. +//===----------------------------------------------------------------------===// +#define DEBUG_TYPE "hexagon_live_vars" + +#include "HexagonLiveVariables.h" +#include "HexagonTargetMachine.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachinePostDominators.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/InitializePasses.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm; + +char HexagonLiveVariables::ID = 0; +char &llvm::HexagonLiveVariablesID = HexagonLiveVariables::ID; + +INITIALIZE_PASS(HexagonLiveVariables, "hexagon-live-vars", + "Hexagon Live Variable Analysis", false, false) + +// TODO: Establish a protocol to handle liveness of predicated instructions. +// Liveness for predicated instruction is a little convoluted. +// TODO: In PhysRegDef and PhysRegUse, use a bit vector instead of 126 elems. +class HexagonLiveVariablesImpl { + // Intermediate data structures + friend class llvm::HexagonLiveVariables; + typedef MachineBasicBlock::const_instr_iterator MICInstIterType; + + MachineFunction *MF; + + MachineRegisterInfo *MRI; + + const TargetRegisterInfo *TRI; + + const HexagonInstrInfo *QII; + + unsigned NumRegs; + + /// PhysRegInfo - Keep track of which instruction was the last def of a + /// physical register (possibly after a use). This is purely local to a BB. + SmallVector PhysRegDef; + + /// PhysRegInfo - Keep track of which instruction was the last use of a + /// physical register (before any def). This is purely local property to a BB. + SmallVector PhysRegUse; + + /// MBB -> (Uses, Defs) + /// Uses - use before any def in that MBB. + /// Defs - def before any uses in that MBB. + MBBUseDef_t MBBUseDefs; + + /// MI -> (Uses, Defs) + MIUseDef_t MIUseDefs; + + /// Live-out data for each MBB => U LiveIns (For all Successors of a MBB). + DenseMap MBBLiveOuts; + + /// Each MachineBasicBlock is assigned a Distance which is + /// an approximation of MBB->size()*INSTR_SIZE+Some offsets. + /// This is helpful in quickly finding distance between + /// a branch and its target. + /// @note A pass which moves instructions should update this. + /// @note The data in distance map should be used carefully because + /// difference in the distances of two MI might not give relative distances + /// between them. The DistanceMap is mainly useful during pullup. + DenseMap DistanceMap; + + // Blocks in depth first order + SmallVector BlocksDepthFirst; + + /// @brief Constructs use-defs of \p MBB by analyzing each MachineOperand. + /// Collects relevant information so that global liveness can be updated. + void constructUseDef(MachineBasicBlock *MBB); + + /// Collects used-before-define set of registers. + /// A register is considered to be completely defined if + /// 1. The register + /// 2. Any of its super-reg + /// 3. All of its subregs + /// are defined. In these cases the register is not considered as + /// used-before-defined. In case of partial definition of a register + /// before its use, only the remaining subregs are included in the use-set. + /// @note: Assumes that a register can be completely defined, by defining + /// all of its sub-regs (if any). + void handlePhysRegUse(MachineOperand *MO, MachineInstr *MI, BitVector &Uses); + + /// Collects defined-before-use set of registers. If there is any + /// use of register or its aliases then the register is not counted + /// as defined-before-use + /// @note: Assumes that a register can be completely defined, by defining + /// all of its sub-regs (if any). + void handlePhysRegDef(MachineOperand *MO, MachineInstr *MI, BitVector &Defs); + + /// updateGlobalLiveness - wrapper around another overload + inline bool updateGlobalLiveness(MachineFunction &Fn); + bool updateGlobalLiveness(MachineBasicBlock *X, MachineBasicBlock *Y); + + /// updateGlobalLiveness - updates liveness based on + /// livein and liveout entries. + bool updateGlobalLiveness(MachineBasicBlock *MBB, BitVector &Defs, + BitVector &LiveIns); + + /// update live-ins when live-out has been calculated + bool updateLiveIns(MachineBasicBlock *MBB, BitVector &LiveIns, + const BitVector &LiveOuts); + + bool updateLiveOuts(MachineBasicBlock *MBB, BitVector &LiveOuts); + + /// updateLocalLiveness - update only kill flags of operands. + inline bool updateLocalLiveness(MachineFunction &Fn); + + /// updateLocalLiveness - update only kill flags of operands. + bool updateLocalLiveness(MachineBasicBlock *MBB, bool UpdateBundle); + + /// incrementalUpdate - update the liveness when \p MIDelta is moved from + /// \p From to \p To. + /// @note: This is extremely fragile now. It 'assumes' that the other + /// successor(s) of \p To do not use Defs of MIDelta. + /// It deletes the live-in of the \p From MBB. + bool incrementalUpdate(MICInstIterType MIDelta, MachineBasicBlock *From, + MachineBasicBlock *To); + + /// addNewMBB - inform the LiveVariable Analysis that new MBB has been added. + /// update the liveness of this new MBB. + /// @note MBB should be empty. If we want to add an MI, add it after calling + /// this function. + void addNewMBB(MachineBasicBlock *MBB); + + void addNewMI(MachineInstr *MI, MachineBasicBlock *MBB); + unsigned getNumRegs() const { return NumRegs; } + + // Useful for clearing out after passes which move instructions around. + // e.g. GlobalScheduler. + void clearDistanceMap() { DistanceMap.clear(); } + + /// Computes \p DistanceMap. + void generateDistanceMap(const MachineFunction &Fn); + +public: + bool runOnMachineFunction(MachineFunction &Fn, MachineDominatorTree &MDT, + MachinePostDominatorTree &MPDT); +}; + +//===----------------------------------------------------------------------===// +// HexagonLiveVariables Functions +//===----------------------------------------------------------------------===// +HexagonLiveVariables::HexagonLiveVariables() + : MachineFunctionPass(ID), HLVComplete(false), + HLV(std::make_unique()) { + initializeHexagonLiveVariablesPass(*PassRegistry::getPassRegistry()); +} + +void HexagonLiveVariables::getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesCFG(); + AU.addRequired(); + AU.addRequired(); + AU.addPreserved(); + AU.addPreserved(); + AU.addPreserved("packets"); + MachineFunctionPass::getAnalysisUsage(AU); +} + +void HexagonLiveVariables::recalculate(MachineFunction &MF) { + if (HLVComplete) + return; + auto &MDT = getAnalysis().getDomTree(); + auto &MPDT = + getAnalysis().getPostDomTree(); + HLV->runOnMachineFunction(MF, MDT, MPDT); +} + +bool HexagonLiveVariables::updateLocalLiveness(MachineFunction &Fn) { + return HLV->updateLocalLiveness(Fn); +} + +bool HexagonLiveVariables::updateLocalLiveness(MachineBasicBlock *MBB, + bool updateBundle) { + HLV->constructUseDef(MBB); // XXX: This destroys MBBLiveOuts! + return HLV->updateLocalLiveness(MBB, updateBundle); +} + +bool HexagonLiveVariables::incrementalUpdate(MICInstIterType MIDelta, + MachineBasicBlock *From, + MachineBasicBlock *To) { + assert(MIDelta->getParent() == To); + assert(From != To); + return HLV->incrementalUpdate(MIDelta, From, To); +} + +void HexagonLiveVariables::addNewMBB(MachineBasicBlock *MBB) { + assert(MBB->empty()); + HLV->addNewMBB(MBB); +} + +void HexagonLiveVariables::addNewMI(MachineInstr *MI, MachineBasicBlock *MBB) { + HLV->addNewMI(MI, MBB); +} + +void HexagonLiveVariables::constructUseDef(MachineBasicBlock *MBB) { + HLV->constructUseDef(MBB); +} + +bool HexagonLiveVariables::runOnMachineFunction(MachineFunction &Fn) { + auto &MDT = getAnalysis().getDomTree(); + auto &MPDT = + getAnalysis().getPostDomTree(); + HLVComplete = !HLV->runOnMachineFunction(Fn, MDT, MPDT); + return HLVComplete; +} + +bool HexagonLiveVariables::isLiveOut(const MachineBasicBlock *MBB, + unsigned Reg) const { + assert(HLVComplete && "Liveness Analysis not available"); + auto It = HLV->MBBLiveOuts.find(MBB); + if (It == HLV->MBBLiveOuts.end()) + llvm_unreachable("MBB not found in liveness map"); + if (Reg >= It->second.size()) + llvm_unreachable("Register index out of bounds"); + return It->second[Reg]; +} + +const BitVector & +HexagonLiveVariables::getLiveOuts(const MachineBasicBlock *MBB) const { + assert(HLVComplete && "Liveness Analysis not available"); + auto It = HLV->MBBLiveOuts.find(MBB); + if (It == HLV->MBBLiveOuts.end()) + llvm_unreachable("MBB not found in liveness map"); + return It->second; +} + +// Returns true when \p Reg is used within [MIBegin, MIEnd) +// @note: MIBegin and MIEnd should be from same MBB +// @note: It returns just the first use found in the range. +// The Use is closest to MIEnd. +// Takes care of aliases and predicated defs as well. +bool HexagonLiveVariables::isUsedWithin( + MICInstIterType MIBegin, MICInstIterType MIEnd, unsigned Reg, + MICInstIterType &Use, + SmallPtrSet *ExceptionsList) const { + assert(HLVComplete && "Liveness Analysis not available"); + Use = MIEnd; + if (MIBegin == MIEnd) // NULL Range. + return false; + MICInstIterType MII = MIEnd; + do { + --MII; + if (MII->isBundle() || MII->isDebugInstr()) + continue; + if (ExceptionsList && ExceptionsList->contains(&*MII)) + continue; + auto It = HLV->MIUseDefs.find(&*MII); + assert(It != HLV->MIUseDefs.end()); + for (MCRegAliasIterator AI(Reg, HLV->TRI, true); AI.isValid(); ++AI) + if (It->second.first[*AI]) { + Use = MII; + return true; + } + } while (MII != MIBegin); + return false; +} + +// Returns true when \p Reg id defined within [MIBegin, MIEnd) +// @note: MIBegin and MIEnd should be from same MBB +// The Def is closest to MIEnd. +// Takes care of aliases and predicated defs as well. +bool HexagonLiveVariables::isDefinedWithin(MICInstIterType MIBegin, + MICInstIterType MIEnd, unsigned Reg, + MICInstIterType &Def) const { + assert(HLVComplete && "Liveness Analysis not available"); + Def = MIEnd; + if (MIBegin == MIEnd) // NULL Range. + return false; + MICInstIterType MII = MIEnd; + do { + --MII; + if (MII->isBundle() || MII->isDebugInstr()) + continue; + auto It = HLV->MIUseDefs.find(&*MII); + assert(It != HLV->MIUseDefs.end()); + for (MCRegAliasIterator AI(Reg, HLV->TRI, true); AI.isValid(); ++AI) + if (It->second.second[*AI]) { + Def = MII; + return true; + } + } while (MII != MIBegin); + return false; +} + +// Returns true if any of the defs of MII is live-in in the MBB. +bool HexagonLiveVariables::isDefLiveIn(const MachineInstr *MI, + const MachineBasicBlock *MBB) const { + assert(HLVComplete && "Liveness Analysis not available"); + assert(MI && "Invalid machine instruction"); + assert(MBB && "Invalid machine basic block"); + auto It = HLV->MIUseDefs.find(MI); + assert(It != HLV->MIUseDefs.end() && "Missing MI use/def information"); + BitVector MBBLiveIns(HLV->NumRegs); + for (MachineBasicBlock::livein_iterator lit = MBB->livein_begin(); + lit != MBB->livein_end(); ++lit) { + // Include all the aliases of reg *lit. + for (MCRegAliasIterator AI((*lit).PhysReg, HLV->TRI, true); AI.isValid(); + ++AI) + MBBLiveIns.set(*AI); + } + // Intersect. + return MBBLiveIns.anyCommon(It->second.second); +} + +MBBUseDef_t &HexagonLiveVariables::getMBBUseDefs() { return HLV->MBBUseDefs; } + +MIUseDef_t &HexagonLiveVariables::getMIUseDefs() { return HLV->MIUseDefs; } + +unsigned HexagonLiveVariables::getDistanceBetween(const MachineBasicBlock *From, + const MachineBasicBlock *To, + unsigned BufferPerMBB) const { + assert(HLV->DistanceMap.find(From) != HLV->DistanceMap.end()); + assert(HLV->DistanceMap.find(To) != HLV->DistanceMap.end()); + unsigned FromSize = HLV->DistanceMap[From]; + if (From == To) + return FromSize; + const MachineFunction *MF = From->getParent(); + MachineFunction::const_iterator MBBI = MF->begin(); + unsigned S = BufferPerMBB; + bool ToFirst = false; + while (MBBI != MF->end()) { + const MachineBasicBlock *MBB = &*MBBI; + if (MBB == From) + break; + else if (MBB == To) { + ToFirst = true; + break; + } + ++MBBI; + } + const MachineBasicBlock *ToFind = To; + if (ToFirst) + ToFind = From; + while (MBBI != MF->end()) { + const MachineBasicBlock *MBB = &*MBBI; + if (MBB == ToFind) + break; + S += HLV->DistanceMap[MBB] + BufferPerMBB; + ++MBBI; + } + if (ToFirst) // Jump in the opposite direction. + S += FromSize + HLV->DistanceMap[To] + 2 * BufferPerMBB; + return S; +} + +void HexagonLiveVariables::regenerateDistanceMap(const MachineFunction &Fn) { + HLV->clearDistanceMap(); + HLV->generateDistanceMap(Fn); +} + +//===----------------------------------------------------------------------===// +// HexagonLiveVariablesImpl Functions +//===----------------------------------------------------------------------===// +bool HexagonLiveVariablesImpl::runOnMachineFunction( + MachineFunction &Fn, MachineDominatorTree &MDT, + MachinePostDominatorTree &MPDT) { + LLVM_DEBUG(dbgs() << "\nHexagon Live Variables";); + Fn.RenumberBlocks(); + // Update the block numbers in the dominator tree since we preserve it. + MDT.updateBlockNumbers(); + MPDT.updateBlockNumbers(); + + MF = &Fn; + MRI = &Fn.getRegInfo(); + auto &ST = Fn.getSubtarget(); + TRI = ST.getRegisterInfo(); + QII = ST.getInstrInfo(); + + NumRegs = TRI->getNumRegs(); + + MBBUseDefs.clear(); + MIUseDefs.clear(); + MBBLiveOuts.clear(); + + LLVM_DEBUG(dbgs() << "\nNumber of registers in Hexagon is:" << NumRegs); + + PhysRegDef.resize(NumRegs); + PhysRegUse.resize(NumRegs); + + for (MachineFunction::iterator MBBI = Fn.begin(), E = Fn.end(); MBBI != E; + ++MBBI) { + constructUseDef(&*MBBI); + } + updateGlobalLiveness(Fn); + return false; +} + +void HexagonLiveVariablesImpl::constructUseDef(MachineBasicBlock *MBB) { + std::fill(PhysRegDef.begin(), PhysRegDef.end(), (MachineInstr *)0); + std::fill(PhysRegUse.begin(), PhysRegUse.end(), (MachineInstr *)0); + + // Loop over all of the instructions, processing them. + std::pair &UseDef = MBBUseDefs[MBB]; + // Use before any def in a BB. + BitVector &Uses = UseDef.first; + // Defs before any use in a BB. + BitVector &Defs = UseDef.second; + // Initializing the LiveOut bit vector. + BitVector &LiveOuts = MBBLiveOuts[MBB]; + Uses.resize(NumRegs, false); + Defs.resize(NumRegs, false); + LiveOuts.resize(NumRegs, false); + // BitVector might contain set bits out of previous liveness updates. + Uses.reset(); + Defs.reset(); + LiveOuts.reset(); + LLVM_DEBUG(dbgs() << "\nBB#" << MBB->getNumber();); + // MBB Number in the MSB 32 bits. + unsigned MBBInsSize = 0; + for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(), + E = MBB->instr_end(); + MII != E; ++MII) { + MachineInstr *MI = &*MII; + MBBInsSize += QII->getSize(*MI); + // TODO: Handle isDebugInstr + if (MI->isBundle() || MI->isDebugInstr()) + continue; + LLVM_DEBUG(dbgs() << "\n\n" << *MI;); + // Clear kill and dead markers. LV will recompute them. + UseDef_t &MIUseDef = MIUseDefs[MI]; + MIUseDef.first.resize(NumRegs); // Uses + MIUseDef.second.resize(NumRegs); // Defs + MIUseDef.first.reset(); // Uses + MIUseDef.second.reset(); // Defs + + SmallVector UseRegs; + SmallVector DefRegs; + SmallVector RegMasks; + // Process all of the operands of the instruction... + unsigned NumOperandsToProcess = MI->getNumOperands(); + for (unsigned i = 0; i != NumOperandsToProcess; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isRegMask()) { + // Assuming that predicated defs are not defs, for now. + if (!QII->isPredicated(*MI)) + DefRegs.push_back(&MO); + continue; + } + if (!MO.isReg() || MO.getReg() == 0) + continue; + unsigned Reg = MO.getReg(); + if (MO.isUse()) { + // Assuming that the kill-flags on call-instructions are correct. + MO.setIsKill(false); + UseRegs.push_back(&MO); + MIUseDef.first.set(Reg); + } else /*MO.isDef()*/ { + assert(MO.isDef()); + if (!QII->isPredicated(*MI) && !MI->isKill()) { + // Assuming that predicated defs are not defs, for now. + // KILL instructions are no-ops + MO.setIsDead(false); + DefRegs.push_back(&MO); + } + MIUseDef.second.set(Reg); // Set all defs (including predicated). + } + } + // Process all uses. + for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) + handlePhysRegUse(UseRegs[i], MI, Uses); + // Process all defs. + for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) + handlePhysRegDef(DefRegs[i], MI, Defs); + } + DistanceMap[MBB] = MBBInsSize; +} + +void HexagonLiveVariablesImpl::handlePhysRegUse(MachineOperand *MO, + MachineInstr *MI, + BitVector &Uses) { + unsigned Reg = MO->getReg(); + LLVM_DEBUG(dbgs() << "\nLooking at:";); + // If the reg/super-reg is already defined in this MBB => return. + for (MCSuperRegIterator SupI(Reg, TRI, true); SupI.isValid(); ++SupI) { + LLVM_DEBUG(dbgs() << printReg(*SupI, TRI);); + if (PhysRegDef[*SupI]) + return; + } + // Handle if sub-regs are defined. + SmallVector undefSubRegs; + bool subRegDefined = false; + for (MCSubRegIterator SubI(Reg, TRI); SubI.isValid(); ++SubI) { + LLVM_DEBUG(dbgs() << printReg(*SubI, TRI);); + if (PhysRegDef[*SubI]) + subRegDefined = true; + else + undefSubRegs.push_back(*SubI); + } + + LLVM_DEBUG(dbgs() << "\nUses:"); + if (undefSubRegs.empty()) { + if (!subRegDefined) { // None of the subregs are defined. + // Include all subregs (including self) to the uses. + for (MCSubRegIterator SubI(Reg, TRI, true); SubI.isValid(); ++SubI) { + LLVM_DEBUG(dbgs() << printReg(*SubI, TRI)); + PhysRegUse[*SubI] = MI; + Uses.set(*SubI); + } + } // All subregs defined. + return; + } + // Some subregs are defined. + for (unsigned i = 0; i < undefSubRegs.size(); ++i) { + LLVM_DEBUG(dbgs() << printReg(undefSubRegs[i], TRI)); + PhysRegUse[undefSubRegs[i]] = MI; + Uses.set(undefSubRegs[i]); + } +} + +// Assumes that an MI cannot have a reg and its super/sub reg as uses. +void HexagonLiveVariablesImpl::handlePhysRegDef(MachineOperand *MO, + MachineInstr *MI, + BitVector &Defs) { + auto SetRegDef = [&](unsigned Reg) -> void { + PhysRegDef[Reg] = MI; + for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { + if (PhysRegUse[*AI]) { + LLVM_DEBUG(dbgs() << "\nUsed in current BB:" << printReg(*AI, TRI)); + return; + } + } + LLVM_DEBUG(dbgs() << "\nDefs:" << printReg(Reg, TRI)); + Defs.set(Reg); + }; + + if (MO->isReg()) { + SetRegDef(MO->getReg()); + } else if (MO->isRegMask()) { + for (unsigned R = 1, NR = TRI->getNumRegs(); R != NR; ++R) + if (MO->clobbersPhysReg(R)) + SetRegDef(R); + } +} + +namespace { +struct BlockState { + bool SuccQueued : 1; + bool Done : 1; + BlockState() : SuccQueued(false), Done(false) {} +}; +} // namespace + +// Populates 'Blocks' with basic blocks of 'Fn' in depth-first order +static void gatherBlocksDF(MachineFunction &Fn, + SmallVectorImpl *Blocks) { + Blocks->clear(); + Blocks->reserve(Fn.size()); + + SmallVector State(Fn.size()); + SmallVector WorkStack; + WorkStack.push_back(&Fn.front()); + while (!WorkStack.empty()) { + MachineBasicBlock *W = WorkStack.back(); + BlockState &WState = State[W->getNumber()]; + if (WState.Done) { + WorkStack.pop_back(); + continue; + } + if (W->succ_empty() || WState.SuccQueued) { + WorkStack.pop_back(); + Blocks->push_back(W); + WState.SuccQueued = true; + WState.Done = true; + continue; + } + WState.SuccQueued = true; + for (MachineBasicBlock::succ_iterator I = W->succ_begin(), + E = W->succ_end(); + I != E; ++I) { + MachineBasicBlock *S = *I; + if (State[S->getNumber()].SuccQueued) + continue; + WorkStack.push_back(S); + } + } + + LLVM_DEBUG( + dbgs() << "gatherBlocksDF: {"; + for (SmallVectorImpl::iterator B = Blocks->begin(), + BE = Blocks->end(); + B != BE; ++B) { dbgs() << " BB#" << (*B)->getNumber(); } dbgs() + << " }\n";); +} + +bool HexagonLiveVariablesImpl::updateGlobalLiveness(MachineFunction &Fn) { + bool Changed = false; + // Removing live-ins and recomputing. + MachineFunction::iterator I = Fn.begin(), E = Fn.end(); + // Not touching the live-ins of entry basic block. + for (++I; I != E; ++I) { + std::vector OldLiveIn( + I->livein_begin(), I->livein_end()); + for (unsigned i = 0; i < OldLiveIn.size(); ++i) + I->removeLiveIn(OldLiveIn[i].PhysReg); + } + + gatherBlocksDF(Fn, &BlocksDepthFirst); + + BitVector Defs; + BitVector LiveIns; + bool Repeat; + do { + Repeat = false; + for (SmallVectorImpl::iterator + B = BlocksDepthFirst.begin(), + BE = BlocksDepthFirst.end(); + B != BE; ++B) { + Repeat |= updateGlobalLiveness(*B, Defs, LiveIns); + } + Changed |= Repeat; + } while (Repeat); + + Changed |= updateLocalLiveness(Fn); + return Changed; +} + +bool HexagonLiveVariablesImpl::updateGlobalLiveness(MachineBasicBlock *X, + MachineBasicBlock *Y) { + assert(X && "Invalid start block"); + assert(Y && "Invalid end block"); + + bool Changed = false; + BitVector Defs; + BitVector LiveIns; + + const SmallVectorImpl::iterator BE = + BlocksDepthFirst.end(); + SmallVectorImpl::iterator B; + for (B = BlocksDepthFirst.begin(); (B != BE); ++B) { + if (*B == X) + break; + if (*B == Y) + break; + } + + bool Repeat; + do { + Repeat = false; + for (; B != BE; ++B) + Repeat |= updateGlobalLiveness(*B, Defs, LiveIns); + Changed |= Repeat; + B = BlocksDepthFirst.begin(); + } while (Repeat); + + return Changed; +} + +// Defs and LiveIns could be local variables within updateGlobalLiveness, but +// have been pulled out to (hopefully) improve performance. +bool HexagonLiveVariablesImpl::updateGlobalLiveness(MachineBasicBlock *MBB, + BitVector &Defs, + BitVector &LiveIns) { + LLVM_DEBUG(dbgs() << "\nTrying to Update Liveness MBB#" << MBB->getNumber()); + bool Changed = false; + LLVM_DEBUG(dbgs() << "\nUpdating Liveness MBB#" << MBB->getNumber()); + // Update live-outs + auto LiveOutIt = MBBLiveOuts.find(MBB); + if (LiveOutIt == MBBLiveOuts.end()) + LiveOutIt = MBBLiveOuts.insert({MBB, BitVector(NumRegs)}).first; + BitVector &LiveOuts = LiveOutIt->second; + for (MachineBasicBlock::succ_iterator MBBSucc = MBB->succ_begin(); + MBBSucc != MBB->succ_end(); ++MBBSucc) { + MachineBasicBlock *Succ = *MBBSucc; + LLVM_DEBUG(dbgs() << "\n\t\tAdding LiveOut:";); + for (MachineBasicBlock::livein_iterator LI = Succ->livein_begin(), + LE = Succ->livein_end(); + LI != LE; ++LI) { + if (!LiveOuts[(*LI).PhysReg]) { + LLVM_DEBUG(dbgs() << " " << printReg((*LI).PhysReg, TRI);); + LiveOuts.set((*LI).PhysReg); + Changed = true; + } + } + } + LLVM_DEBUG(dbgs() << "\nUpdated Successors of MBB#" << MBB->getNumber()); + // Update live-ins + Changed |= updateLiveIns(MBB, LiveIns, LiveOuts); + + return Changed; +} + +// update live-ins when live-out has been calculated +bool HexagonLiveVariablesImpl::updateLiveIns(MachineBasicBlock *MBB, + BitVector &LiveIns, + const BitVector &LiveOuts) { + LLVM_DEBUG(dbgs() << "\n[updateLiveIns] MBB#" << MBB->getNumber()); + bool Changed = false; + const std::pair &UseDefs = MBBUseDefs[MBB]; + LiveIns = LiveOuts; + // LiveIns = (LiveOuts - Defs) | Uses + // Equivalent to: LiveIns = (LiveOuts & ~Defs) | Uses + LiveIns.reset(UseDefs.second); + LiveIns |= UseDefs.first; + LLVM_DEBUG(dbgs() << "\n\t\tAdded LiveIn:";); + for (int i = LiveIns.find_first(); i >= 0; i = LiveIns.find_next(i)) { + // TODO: remove costly check of MBB->isLiveIn when fully functional. + if (!MBB->isLiveIn(i) && MRI->isAllocatable(i)) { + LLVM_DEBUG(dbgs() << " " << printReg(i, TRI)); + MBB->addLiveIn(i); + Changed = true; + } + } + return Changed; +} + +bool HexagonLiveVariablesImpl::updateLiveOuts(MachineBasicBlock *MBB, + BitVector &LiveOuts) { + bool Changed = false; + for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) { + MachineBasicBlock *SB = *SI; + for (auto I = SB->livein_begin(), E = SB->livein_end(); I != E; ++I) { + unsigned R = (*I).PhysReg; + if (LiveOuts[R]) + continue; + LiveOuts.set(R); + Changed = true; + } + } + return Changed; +} + +bool HexagonLiveVariablesImpl::updateLocalLiveness(MachineFunction &Fn) { + LLVM_DEBUG(dbgs() << "\n[updateLocalLiveness]"); + for (MachineFunction::iterator B = Fn.begin(), E = Fn.end(); B != E; ++B) + updateLocalLiveness(&*B, false); + return true; +} + +bool HexagonLiveVariablesImpl::updateLocalLiveness(MachineBasicBlock *MBB, + bool UpdateBundle) { + assert(MBB && "Invalid basic block"); + LLVM_DEBUG(dbgs() << "\n[updateLocalLiveness] MBB#" << MBB->getNumber()); + + BitVector &LiveOut = MBBLiveOuts[MBB]; + updateLiveOuts(MBB, LiveOut); + + BitVector Used = LiveOut; + SmallVector BundleHeads; + // Bottom up traversal of MBB. + for (MachineBasicBlock::reverse_instr_iterator MII = MBB->instr_rbegin(), + MIREnd = MBB->instr_rend(); + MII != MIREnd; ++MII) { + MachineInstr *MI = &*MII; + // The bundle liveness is updated differently. + if (MI->isBundle()) { + if (UpdateBundle) + BundleHeads.push_back(MI); + continue; + } + if (MI->isDebugInstr()) // DBG_VALUE may have invalid reg. + continue; + SmallVector UseRegs; + SmallVector DefRegs; + for (unsigned i = 0; i < MI->getNumOperands(); ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isReg()) { // DBG_VALUE may have invalid reg. + if (MO.isUse()) + UseRegs.push_back(&MO); + else { // Def + if (!QII->isPredicated(*MI) && !MI->isKill()) { + // Assuming that predicated defs are not defs, for now. + // KILL instructions are no-ops + DefRegs.push_back(&MO); + } + } + } else if (MO.isRegMask()) { + if (!QII->isPredicated(*MI)) + DefRegs.push_back(&MO); + } + } + // In case of a def. remove Reg and its sub-regs from Used list + // such that uses in the same MI can be marked as kill. + auto RemoveDef = [&](unsigned Reg, bool Implicit) -> void { + for (MCSubRegIterator SI(Reg, TRI, true); SI.isValid(); ++SI) { + Used.reset(*SI); + if (Implicit) { + // For implicit defs, check if there is an implicit use of an + // aliased register. If so, mark the aliased reg as used. + for (auto *UseOp : UseRegs) + if (UseOp->isImplicit() && TRI->regsOverlap(*SI, UseOp->getReg())) + Used.set(UseOp->getReg()); + } + } + }; + for (unsigned i = 0; i < DefRegs.size(); ++i) { + MachineOperand &MO = *DefRegs[i]; + if (MO.isReg()) { + RemoveDef(MO.getReg(), MO.isImplicit()); + } else if (MO.isRegMask()) { + for (unsigned R = 1, NR = TRI->getNumRegs(); R != NR; ++R) + if (MO.clobbersPhysReg(R)) + RemoveDef(R, true); + } + } + // The order is important as we are looking from right to left. + for (unsigned i = UseRegs.size(); i > 0;) { + --i; + unsigned UseReg = UseRegs[i]->getReg(); + bool Killed = true; + for (MCRegAliasIterator AI(UseReg, TRI, true); AI.isValid(); ++AI) { + if (Used[*AI]) + Killed = false; + } + Used.set(UseReg); + if (Killed && !UseRegs[i]->isDebug()) + UseRegs[i]->setIsKill(true); + } + } + // Recreates bundle for updating liveness. + for (SmallVectorImpl::iterator MII = BundleHeads.begin(); + MII != BundleHeads.end(); ++MII) { + MachineInstr *MI = *MII; + assert(MI && "Invalid bundle head"); + assert(MI->isBundle() && "Expected a bundle head instruction"); + assert(MI->getParent() == MBB && "Bundle head not in expected block"); + MachineBasicBlock::instr_iterator BS = MI->getIterator(); + MachineBasicBlock::instr_iterator BE = getBundleEnd(BS); + for (++BS; BS != BE; ++BS) + // Remove from bundle so that BUNDLE head can be erased. + BS->unbundleFromPred(); + + BS = MI->getIterator(); + ++BS; + bool memShufDisabled = QII->getBundleNoShuf(*MI); + MI->eraseFromParent(); + finalizeBundle(*MBB, BS, BE); + MachineBasicBlock::instr_iterator BundleMII = std::prev(BS); + if (memShufDisabled) + QII->setBundleNoShuf(BundleMII); + } + return true; +} + +// It deletes the live-in of the \p From MBB. +bool HexagonLiveVariablesImpl::incrementalUpdate(MICInstIterType MIDelta, + MachineBasicBlock *From, + MachineBasicBlock *To) { + while (!From->livein_empty()) + From->removeLiveIn((*From->livein_begin()).PhysReg); + // Handle MI use-def of From. + constructUseDef(From); + // Handle MI use-def of To. + constructUseDef(To); + // Calculate live-in of From and To + // Reuse this by setting all MBBs except From and To as visited. + updateGlobalLiveness(From, To); + // Update local liveness of To. + updateLocalLiveness(From, true); + updateLocalLiveness(To, true); + + // Do this after the liveness update because MIDelta might not be in the + // MIUseDefs before liveness update (since MIDelta might be newly inserted). + MIUseDef_t::const_iterator MIUseDef = MIUseDefs.find(&*MIDelta); + if (MIUseDef == MIUseDefs.end()) + llvm_unreachable("MIDelta not found in MIUseDefs after liveness update"); + const BitVector &Defs = MIUseDef->second.second; + int Reg = Defs.find_first(); + // Adding all the defs as live-ins. This is conservative approach but we + // need to add them so as to avoid dealing with callee saved registers and + // any unwanted errors in liveness that might arise. + while (Reg >= 0) { + From->addLiveIn(Reg); + Reg = Defs.find_next(Reg); + } + return true; +} + +void HexagonLiveVariablesImpl::addNewMBB(MachineBasicBlock *MBB) { + // Resize and init. + constructUseDef(MBB); // This is to set up some containers for MBB. + gatherBlocksDF(*MBB->getParent(), &BlocksDepthFirst); + updateGlobalLiveness(MBB, MBB); +} + +// TODO: This is a slow implementation because constructUseDef destroys +// the MBBLiveOuts which is generated again by updateGlobalLiveness. +void HexagonLiveVariablesImpl::addNewMI(MachineInstr *MI, + MachineBasicBlock *MBB) { + constructUseDef(MBB); // This is to set up some containers for MBB. + updateGlobalLiveness(MBB, MBB); +} + +void HexagonLiveVariablesImpl::generateDistanceMap(const MachineFunction &Fn) { + assert(DistanceMap.empty() && "DistanceMap not empty, first clear!"); + for (MachineFunction::const_iterator MBBI = Fn.begin(), E = Fn.end(); + MBBI != E; ++MBBI) { + const MachineBasicBlock *MBB = &*MBBI; + unsigned MBBInsSize = 0; + for (MachineBasicBlock::const_instr_iterator MII = MBB->instr_begin(), + E = MBB->instr_end(); + MII != E; ++MII) { + const MachineInstr *MI = &*MII; + MBBInsSize += QII->getSize(*MI); + } + DistanceMap[MBB] = MBBInsSize; + } +} diff --git a/llvm/lib/Target/Hexagon/HexagonLiveVariables.h b/llvm/lib/Target/Hexagon/HexagonLiveVariables.h new file mode 100644 index 0000000000000..396145d49db45 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonLiveVariables.h @@ -0,0 +1,134 @@ +//===----------------- HexagonLiveVariables.h ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// Hexagon Live Variable Analysis +// This file implements the Hexagon specific LiveVariables analysis pass. +// 1. Computes the live variables by analyzing the use-defs. +// - The use-def specifiers are 'assumed' to be correct for each operand. +// 2. Re-calculates the MBB numbers to that they are in sequence. +// TODO: Mark dead instructions. +// TODO: Provide APIs like the target independent Liveness Analysis so that +// other passes can reuse the liveness information. +//===----------------------------------------------------------------------===// + +#ifndef HEXAGON_LIVEVARIABLES_H +#define HEXAGON_LIVEVARIABLES_H + +#include "Hexagon.h" +#include "HexagonInstrInfo.h" + +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" +#include +#include +#include + +class HexagonLiveVariablesImpl; + +namespace llvm { + +typedef std::pair UseDef_t; // (Use, Def) +typedef DenseMap MBBUseDef_t; +typedef DenseMap MIUseDef_t; + +// List of intervals [From, To). +typedef std::list> IntervalList_t; +// Intervals stored in indexed form. +typedef SmallVector IndexedLiveIntervals_t; + +class HexagonLiveVariables : public MachineFunctionPass { +public: + typedef MachineBasicBlock::const_instr_iterator MICInstIterType; + + static char ID; // Pass identification, replacement for typeid + bool HLVComplete; + HexagonLiveVariables(); + + bool runOnMachineFunction(MachineFunction &MF) override; + void getAnalysisUsage(AnalysisUsage &AU) const override; + StringRef getPassName() const override { + return "Hexagon Live Variables Analysis"; + } + + /// recalculate - recalculates the liveness from scratch. It is like + /// calling the runOnMachineFunction. + void recalculate(MachineFunction &MF); + + /// updateLocalLiveness - update only kill flags of operands. + /// Assumes that global liveness is correct. + bool updateLocalLiveness(MachineFunction &Fn); + + /// updateLocalLiveness - update only kill flags of operands in MBB. + /// Assumes that global liveness is correct. + /// This is useful when a local transformation modifies MIs, + /// which only changes the local liveness. + bool updateLocalLiveness(MachineBasicBlock *MBB, bool updateBundle); + + /// incrementalUpdate - update the liveness when \p MIDelta is moved from + /// \p From to \p To. + /// @note: This is extremely fragile now. It 'assumes' that the other + /// successor(s) of \p To do not use Defs of MIDelta. + bool incrementalUpdate(MICInstIterType MIDelta, MachineBasicBlock *From, + MachineBasicBlock *To); + // addNewMI - update internal data-structures of Live Variable Analysis. + void addNewMI(MachineInstr *MI, MachineBasicBlock *MBB); + + /// addNewMBB - inform the LiveVariable Analysis that new MBB has been added. + /// update the liveness of this new MBB. + /// @note MBB should be empty. If we want to add an MI, add it after calling + /// this function. + void addNewMBB(MachineBasicBlock *MBB); + + /// @brief Constructs use-defs of \p MBB by analyzing each MachineOperand. + /// Collects relevant information so that global liveness can be updated. + void constructUseDef(MachineBasicBlock *MBB); + + bool isLiveOut(const MachineBasicBlock *MBB, unsigned Reg) const; + const BitVector &getLiveOuts(const MachineBasicBlock *MBB) const; + + // Returns true when \p Reg is used within [MIBegin, MIEnd) + // @note: MIBegin and MIEnd should be from same MBB + // @note: It returns just the first use found in the range. + // The Use is closest to MIEnd. + // Takes care of aliases as well. + bool + isUsedWithin(MICInstIterType MIBegin, MICInstIterType MIEnd, unsigned Reg, + MICInstIterType &Use, + SmallPtrSet *ExceptionsList = nullptr) const; + // Returns true when \p Reg id defined within [MIBegin, MIEnd) + // @note: MIBegin and MIEnd should be from same MBB + // The Def is closest to MIEnd. + // Takes care of aliases as well. + bool isDefinedWithin(MICInstIterType MIBegin, MICInstIterType MIEnd, + unsigned Reg, MICInstIterType &Def) const; + bool isDefLiveIn(const MachineInstr *MI, const MachineBasicBlock *MBB) const; + MBBUseDef_t &getMBBUseDefs(); + MIUseDef_t &getMIUseDefs(); + + /// Returns the linear distance (as per layout) of \p MI from the Function. + /// \p BufferPerMBB is to allow some room for .falign (if added later). + unsigned getDistanceBetween(const MachineBasicBlock *From, + const MachineBasicBlock *To, + unsigned BufferPerMBB = HEXAGON_INSTR_SIZE) const; + + // recalculate the distance map. + void regenerateDistanceMap(const MachineFunction &Fn); + +private: + std::unique_ptr HLV; +}; + +} // namespace llvm + +#endif diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 2f14622cab57c..cfe898fe767dc 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -66,6 +66,9 @@ static cl::opt DisableHexagonMask( "disable-mask", cl::Hidden, cl::desc("Disable Hexagon specific Mask generation pass")); +static cl::opt DisableHexagonLiveVars( + "disable-hlv", cl::Hidden, + cl::desc("Disable Hexagon specific post-RA live-variable analysis")); static cl::opt DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening")); @@ -192,6 +195,7 @@ LLVMInitializeHexagonTarget() { initializeHexagonEarlyIfConversionPass(PR); initializeHexagonGenMemAbsolutePass(PR); initializeHexagonGenMuxPass(PR); + initializeHexagonLiveVariablesPass(PR); initializeHexagonHardwareLoopsPass(PR); initializeHexagonLoopIdiomRecognizeLegacyPassPass(PR); initializeHexagonNewValueJumpPass(PR); @@ -448,6 +452,10 @@ void HexagonPassConfig::addPreSched2() { addPass(createHexagonSplitConst32AndConst64()); if (!NoOpt && !DisableHexagonMask) addPass(createHexagonMask()); + + if (!NoOpt && !DisableHexagonLiveVars) { + addPass(&HexagonLiveVariablesID); + } } void HexagonPassConfig::addPreEmitPass() { @@ -464,6 +472,8 @@ void HexagonPassConfig::addPreEmitPass() { // Generate MUX from pairs of conditional transfers. if (EnableGenMux) addPass(createHexagonGenMux()); + if (!DisableHexagonLiveVars) + addPass(&HexagonLiveVariablesID); } // Packetization is mandatory: it handles gather/scatter at all opt levels. diff --git a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp index 2ff5843b19429..40c10c27ae4a2 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp @@ -486,7 +486,7 @@ void HexagonVectorLoopCarriedReuse::findValueToReuse() { LLVM_DEBUG(dbgs() << "Found Value for reuse.\n"); ReuseCandidate.Inst2Replace = I; ReuseCandidate.BackedgeInst = BEUser; - ReuseCandidate.DepChains = DepChains; + ReuseCandidate.DepChains = std::move(DepChains); ReuseCandidate.Iterations = Iters; return; } diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index 67f429c0ea4bc..18bddf9c2fc35 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -436,23 +436,6 @@ bool LanaiInstrInfo::optimizeCompareInstr( return false; } -bool LanaiInstrInfo::analyzeSelect(const MachineInstr &MI, - SmallVectorImpl &Cond, - unsigned &TrueOp, unsigned &FalseOp, - bool &Optimizable) const { - assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction"); - // Select operands: - // 0: Def. - // 1: True use. - // 2: False use. - // 3: Condition code. - TrueOp = 1; - FalseOp = 2; - Cond.push_back(MI.getOperand(3)); - Optimizable = true; - return false; -} - // Identify instructions that can be folded into a SELECT instruction, and // return the defining instruction. static MachineInstr *canFoldIntoSelect(Register Reg, diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h index 01b7d8a802805..f9b9d91b5b6b7 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h @@ -109,20 +109,6 @@ class LanaiInstrInfo : public LanaiGenInstrInfo { Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override; - // Analyze the given select instruction, returning true if it cannot be - // understood. It is assumed that MI->isSelect() is true. - // - // When successful, return the controlling condition and the operands that - // determine the true and false result values. - // - // Result = SELECT Cond, TrueOp, FalseOp - // - // Lanai can optimize certain select instructions, for example by predicating - // the instruction defining one of the operands and sets Optimizable to true. - bool analyzeSelect(const MachineInstr &MI, - SmallVectorImpl &Cond, unsigned &TrueOp, - unsigned &FalseOp, bool &Optimizable) const override; - // Given a select instruction that was understood by analyzeSelect and // returned Optimizable = true, attempt to optimize MI by merging it with one // of its operands. Returns NULL on failure. diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 486500e5f3f2d..7b050c3715f6c 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -7258,7 +7258,6 @@ emitPseudoXVINSGR2VR(MachineInstr &MI, MachineBasicBlock *BB, .addImm(Idx); BuildMI(*BB, MI, DL, TII->get(LoongArch::SUBREG_TO_REG), XDst) - .addImm(0) .addReg(ScratchSubReg2) .addImm(LoongArch::sub_128); } else { @@ -9037,17 +9036,17 @@ bool LoongArchTargetLowering::hasAndNot(SDValue Y) const { return VT.isScalarInteger() && !isa(Y); } -bool LoongArchTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void LoongArchTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { switch (Intrinsic) { default: - return false; + return; case Intrinsic::loongarch_masked_atomicrmw_xchg_i32: case Intrinsic::loongarch_masked_atomicrmw_add_i32: case Intrinsic::loongarch_masked_atomicrmw_sub_i32: - case Intrinsic::loongarch_masked_atomicrmw_nand_i32: + case Intrinsic::loongarch_masked_atomicrmw_nand_i32: { + IntrinsicInfo Info; Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i32; Info.ptrVal = I.getArgOperand(0); @@ -9055,9 +9054,11 @@ bool LoongArchTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(4); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; // TODO: Add more Intrinsics later. } + } } // When -mlamcas is enabled, MinCmpXchgSizeInBits will be set to 8, diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h index 126ea055829eb..1fd9b6b237fe5 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h @@ -78,8 +78,8 @@ class LoongArchTargetLowering : public TargetLowering { Value *NewVal, Value *Mask, AtomicOrdering Ord) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td index fa4b720e7ba98..92ba17f5707a1 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td @@ -1731,17 +1731,17 @@ def : Pat<(loongarch_xvinsve0 v8f32:$xd, v8f32:$xj, uimm3:$imm), def : Pat<(loongarch_xvinsve0 v4f64:$xd, v4f64:$xj, uimm2:$imm), (XVINSVE0_D v4f64:$xd, v4f64:$xj, uimm2:$imm)>; def : Pat<(vector_insert v8f32:$xd, FPR32:$fj, uimm3:$imm), - (XVINSVE0_W v8f32:$xd, (SUBREG_TO_REG(i64 0), FPR32:$fj, sub_32), + (XVINSVE0_W v8f32:$xd, (SUBREG_TO_REG FPR32:$fj, sub_32), uimm3:$imm)>; def : Pat<(vector_insert v4f64:$xd, FPR64:$fj, uimm2:$imm), - (XVINSVE0_D v4f64:$xd, (SUBREG_TO_REG(i64 0), FPR64:$fj, sub_64), + (XVINSVE0_D v4f64:$xd, (SUBREG_TO_REG FPR64:$fj, sub_64), uimm2:$imm)>; // scalar_to_vector def : Pat<(v8f32 (scalar_to_vector FPR32:$fj)), - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>; + (SUBREG_TO_REG FPR32:$fj, sub_32)>; def : Pat<(v4f64 (scalar_to_vector FPR64:$fj)), - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>; + (SUBREG_TO_REG FPR64:$fj, sub_64)>; // XVPICKVE2GR_W[U] def : Pat<(loongarch_vpick_sext_elt v8i32:$xd, uimm3:$imm, i32), @@ -1926,9 +1926,9 @@ def : Pat<(loongarch_xvreplve0 v8f32:$xj), def : Pat<(loongarch_xvreplve0 v4f64:$xj), (XVREPLVE0_D v4f64:$xj)>; def : Pat<(lasxsplatf32 FPR32:$fj), - (XVREPLVE0_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32))>; + (XVREPLVE0_W (SUBREG_TO_REG FPR32:$fj, sub_32))>; def : Pat<(lasxsplatf64 FPR64:$fj), - (XVREPLVE0_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64))>; + (XVREPLVE0_D (SUBREG_TO_REG FPR64:$fj, sub_64))>; foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64] in def : Pat<(vt (loongarch_xvreplve0q LASX256:$xj)), (XVREPLVE0_Q LASX256:$xj)>; @@ -1997,7 +1997,7 @@ def : Pat<(fneg (v4f64 LASX256:$xj)), (XVBITREVI_D LASX256:$xj, 63)>; def : Pat<(v8f32 (sint_to_fp v8i32:$vj)), (XVFFINT_S_W v8i32:$vj)>; def : Pat<(v4f64 (sint_to_fp v4i64:$vj)), (XVFFINT_D_L v4i64:$vj)>; def : Pat<(v4f64 (sint_to_fp v4i32:$vj)), - (XVFFINT_D_L (VEXT2XV_D_W (SUBREG_TO_REG (i64 0), v4i32:$vj, + (XVFFINT_D_L (VEXT2XV_D_W (SUBREG_TO_REG v4i32:$vj, sub_128)))>; def : Pat<(v4f32 (sint_to_fp v4i64:$vj)), (EXTRACT_SUBREG (XVFCVT_S_D (XVPERMI_D (XVFFINT_D_L v4i64:$vj), 238), @@ -2008,7 +2008,7 @@ def : Pat<(v4f32 (sint_to_fp v4i64:$vj)), def : Pat<(v8f32 (uint_to_fp v8i32:$vj)), (XVFFINT_S_WU v8i32:$vj)>; def : Pat<(v4f64 (uint_to_fp v4i64:$vj)), (XVFFINT_D_LU v4i64:$vj)>; def : Pat<(v4f64 (uint_to_fp v4i32:$vj)), - (XVFFINT_D_LU (VEXT2XV_DU_WU (SUBREG_TO_REG (i64 0), v4i32:$vj, + (XVFFINT_D_LU (VEXT2XV_DU_WU (SUBREG_TO_REG v4i32:$vj, sub_128)))>; def : Pat<(v4f32 (uint_to_fp v4i64:$vj)), (EXTRACT_SUBREG (XVFCVT_S_D (XVPERMI_D (XVFFINT_D_LU v4i64:$vj), 238), @@ -2018,7 +2018,7 @@ def : Pat<(v4f32 (uint_to_fp v4i64:$vj)), // XVFTINTRZ_{W_S/L_D} def : Pat<(v8i32 (fp_to_sint v8f32:$vj)), (XVFTINTRZ_W_S v8f32:$vj)>; def : Pat<(v4i64 (fp_to_sint v4f64:$vj)), (XVFTINTRZ_L_D v4f64:$vj)>; -def : Pat<(v4i64(fp_to_sint v4f32:$vj)), (VEXT2XV_D_W(SUBREG_TO_REG(i64 0), +def : Pat<(v4i64(fp_to_sint v4f32:$vj)), (VEXT2XV_D_W(SUBREG_TO_REG (VFTINTRZ_W_S v4f32:$vj), sub_128))>; def : Pat<(v4i32(fp_to_sint v4f64:$vj)), @@ -2029,7 +2029,7 @@ def : Pat<(v4i32(fp_to_sint v4f64:$vj)), // XVFTINTRZ_{W_SU/L_DU} def : Pat<(v8i32 (fp_to_uint v8f32:$vj)), (XVFTINTRZ_WU_S v8f32:$vj)>; def : Pat<(v4i64 (fp_to_uint v4f64:$vj)), (XVFTINTRZ_LU_D v4f64:$vj)>; -def : Pat<(v4i64(fp_to_uint v4f32:$vj)), (VEXT2XV_DU_WU(SUBREG_TO_REG(i64 0), +def : Pat<(v4i64(fp_to_uint v4f32:$vj)), (VEXT2XV_DU_WU(SUBREG_TO_REG (VFTINTRZ_WU_S v4f32:$vj), sub_128))>; def : Pat<(v4i32(fp_to_uint v4f64:$vj)), diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td index da7b6e833c996..2c06d9f827548 100644 --- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td @@ -1907,20 +1907,20 @@ def : Pat<(vector_insert v2f64:$vd, (f64 (bitconvert i64:$rj)), uimm1:$imm), foreach imm = 0...3 in { defvar Imm = !shl(imm, 4); def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, imm), - (VEXTRINS_W $vd, (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), Imm)>; + (VEXTRINS_W $vd, (SUBREG_TO_REG FPR32:$fj, sub_32), Imm)>; } foreach imm = 0...1 in { defvar Imm = !shl(imm, 4); def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, imm), - (VEXTRINS_D $vd, (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), Imm)>; + (VEXTRINS_D $vd, (SUBREG_TO_REG FPR64:$fj, sub_64), Imm)>; } // scalar_to_vector def : Pat<(v4f32 (scalar_to_vector FPR32:$fj)), - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>; + (SUBREG_TO_REG FPR32:$fj, sub_32)>; def : Pat<(v2f64 (scalar_to_vector FPR64:$fj)), - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>; + (SUBREG_TO_REG FPR64:$fj, sub_64)>; // VPICKVE2GR_{B/H/W}[U] def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8), @@ -2090,9 +2090,9 @@ def : Pat<(loongarch_vreplvei v2f64:$vj, immZExt1:$ui1), // VREPLVEI_{W/D} def : Pat<(lsxsplatf32 FPR32:$fj), - (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>; + (VREPLVEI_W (SUBREG_TO_REG FPR32:$fj, sub_32), 0)>; def : Pat<(lsxsplatf64 FPR64:$fj), - (VREPLVEI_D (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)>; + (VREPLVEI_D (SUBREG_TO_REG FPR64:$fj, sub_64), 0)>; defm : VstelmPat; defm : VstelmPat; @@ -2547,28 +2547,28 @@ def : Pat<(loongarch_vfrsqrte v2f64:$src), // Vector floating-point conversion def : Pat<(f32 (fceil FPR32:$fj)), (f32 (EXTRACT_SUBREG (VFRINTRP_S (VREPLVEI_W - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; + (SUBREG_TO_REG FPR32:$fj, sub_32), 0)), sub_32))>; def : Pat<(f64 (fceil FPR64:$fj)), (f64 (EXTRACT_SUBREG (VFRINTRP_D (VREPLVEI_D - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; + (SUBREG_TO_REG FPR64:$fj, sub_64), 0)), sub_64))>; def : Pat<(f32 (ffloor FPR32:$fj)), (f32 (EXTRACT_SUBREG (VFRINTRM_S (VREPLVEI_W - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; + (SUBREG_TO_REG FPR32:$fj, sub_32), 0)), sub_32))>; def : Pat<(f64 (ffloor FPR64:$fj)), (f64 (EXTRACT_SUBREG (VFRINTRM_D (VREPLVEI_D - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; + (SUBREG_TO_REG FPR64:$fj, sub_64), 0)), sub_64))>; def : Pat<(f32 (ftrunc FPR32:$fj)), (f32 (EXTRACT_SUBREG (VFRINTRZ_S (VREPLVEI_W - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; + (SUBREG_TO_REG FPR32:$fj, sub_32), 0)), sub_32))>; def : Pat<(f64 (ftrunc FPR64:$fj)), (f64 (EXTRACT_SUBREG (VFRINTRZ_D (VREPLVEI_D - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; + (SUBREG_TO_REG FPR64:$fj, sub_64), 0)), sub_64))>; def : Pat<(f32 (froundeven FPR32:$fj)), (f32 (EXTRACT_SUBREG (VFRINTRNE_S (VREPLVEI_W - (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)), sub_32))>; + (SUBREG_TO_REG FPR32:$fj, sub_32), 0)), sub_32))>; def : Pat<(f64 (froundeven FPR64:$fj)), (f64 (EXTRACT_SUBREG (VFRINTRNE_D (VREPLVEI_D - (SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64), 0)), sub_64))>; + (SUBREG_TO_REG FPR64:$fj, sub_64), 0)), sub_64))>; defm : PatVrF; defm : PatVrF; diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.td b/llvm/lib/Target/MSP430/MSP430InstrInfo.td index 546ba6fd8e3b4..f25c96e3109a9 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.td +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.td @@ -398,7 +398,7 @@ def def8 : PatLeaf<(i8 GR8:$src), [{ // In the case of a 8-bit def that is known to implicitly zero-extend, // we can use a SUBREG_TO_REG. def : Pat<(i16 (zext def8:$src)), - (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; + (SUBREG_TO_REG GR8:$src, subreg_8bit)>; def MOV8mc : I8mc<0b0100, (outs), (ins memdst:$dst, cg8imm:$imm), @@ -909,7 +909,7 @@ def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; // anyext def : Pat<(i16 (anyext GR8:$src)), - (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; + (SUBREG_TO_REG GR8:$src, subreg_8bit)>; // truncs def : Pat<(i8 (trunc GR16:$src)), diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td index 47e3d48921155..810c8ffe13514 100644 --- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td @@ -229,19 +229,19 @@ def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f def : MipsPat< (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f), (OR64 (SELEQZ64 i64:$t, - (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), + (SUBREG_TO_REG (SLTi64 i64:$cond, (Plus1 imm:$imm)), sub_32)), (SELNEZ64 i64:$f, - (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)), + (SUBREG_TO_REG (SLTi64 i64:$cond, (Plus1 imm:$imm)), sub_32)))>, ISA_MIPS64R6; def : MipsPat< (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f), (OR64 (SELEQZ64 i64:$t, - (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)), + (SUBREG_TO_REG (SLTiu64 i64:$cond, (Plus1 imm:$imm)), sub_32)), (SELNEZ64 i64:$f, - (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)), + (SUBREG_TO_REG (SLTiu64 i64:$cond, (Plus1 imm:$imm)), sub_32)))>, ISA_MIPS64R6; diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index ece81880964c7..cd763e2748995 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -1493,7 +1493,7 @@ bool MipsFastISel::fastLowerArguments() { // Account for the reserved argument area on ABI's that have one (O32). // It seems strange to do this on the caller side but it's necessary in // SelectionDAG's implementation. - IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC), + IncomingArgSizeInBytes = std::max(getABI().GetCalleeAllocdArgSizeInBytes(CC), IncomingArgSizeInBytes); MF->getInfo()->setFormalArgInfo(IncomingArgSizeInBytes, diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index f7e2825edcc5d..5ebfda1eacf1b 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -3364,6 +3364,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (IsTailCall) { if (!UseMipsTailCalls) { IsTailCall = false; + if (IsMustTail) + report_fatal_error("failed to perform tail call elimination on a call " + "site marked musttail"); } else { bool Eligible = isEligibleForTailCallOptimization( CCInfo, StackSize, *MF.getInfo()); diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index bd02b57bfc860..2099df11f5b53 100644 --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -153,20 +153,23 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm, MachineInstr *Inst = B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}) .addImm(Imm.getLoBits(16).getLimitedValue()); - return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); + return true; } // Lui places immediate in high 16 bits and sets low 16 bits to zero. if (Imm.getLoBits(16).isZero()) { MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {}) .addImm(Imm.getHiBits(16).getLimitedValue()); - return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); + return true; } // ADDiu sign extends immediate. Used for values with 1s in high 17 bits. if (Imm.isSignedIntN(16)) { MachineInstr *Inst = B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) .addImm(Imm.getLoBits(16).getLimitedValue()); - return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); + return true; } // Values that cannot be materialized with single immediate instruction. Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); @@ -174,10 +177,8 @@ bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm, .addImm(Imm.getHiBits(16).getLimitedValue()); MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg}) .addImm(Imm.getLoBits(16).getLimitedValue()); - if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) - return false; - if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI); + constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI); return true; } @@ -268,8 +269,7 @@ bool MipsInstructionSelector::buildUnalignedStore( .add(BaseAddr) .addImm(Offset) .addMemOperand(MMO); - if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI); return true; } @@ -283,8 +283,7 @@ bool MipsInstructionSelector::buildUnalignedLoad( .addImm(Offset) .addUse(TiedDest) .addMemOperand(*I.memoperands_begin()); - if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI); return true; } @@ -307,8 +306,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .add(I.getOperand(0)) .add(I.getOperand(1)) .add(I.getOperand(2)); - if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI); Mul->getOperand(3).setIsDead(true); Mul->getOperand(4).setIsDead(true); @@ -331,14 +329,12 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addDef(PseudoMULTuReg) .add(I.getOperand(1)) .add(I.getOperand(2)); - if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI); PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) .addDef(I.getOperand(0).getReg()) .addUse(PseudoMULTuReg); - if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI); I.eraseFromParent(); return true; @@ -373,16 +369,14 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addDef(JTIndex) .addUse(I.getOperand(2).getReg()) .addImm(Log2_32(EntrySize)); - if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI); Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) .addDef(DestAddress) .addUse(I.getOperand(0).getReg()) .addUse(JTIndex); - if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI); Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); MachineInstr *LW = @@ -392,8 +386,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO) .addMemOperand(MF.getMachineMemOperand( MachinePointerInfo(), MachineMemOperand::MOLoad, 4, Align(4))); - if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*LW, TII, TRI, RBI); if (MF.getTarget().isPositionIndependent()) { Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); @@ -403,15 +396,13 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addUse(DestTmp) .addUse(MF.getInfo() ->getGlobalBaseRegForGlobalISel(MF)); - if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI); } MachineInstr *Branch = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch)) .addUse(Dest); - if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI); I.eraseFromParent(); return true; @@ -518,15 +509,13 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addDef(HILOReg) .add(I.getOperand(1)) .add(I.getOperand(2)); - if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI); PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI)) .addDef(I.getOperand(0).getReg()) .addUse(HILOReg); - if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI); I.eraseFromParent(); return true; @@ -557,15 +546,13 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addDef(Lo) .addUse(Src) .addImm(0); - if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI); MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) .addDef(Hi) .addUse(Src) .addImm(1); - if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI); I.eraseFromParent(); return true; @@ -601,8 +588,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { MachineInstrBuilder MTC1 = B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); - if (!MTC1.constrainAllUses(TII, TRI, RBI)) - return false; + MTC1.constrainAllUses(TII, TRI, RBI); } if (Size == 64) { Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass); @@ -616,8 +602,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { MachineInstrBuilder PairF64 = B.buildInstr( STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh}); - if (!PairF64.constrainAllUses(TII, TRI, RBI)) - return false; + PairF64.constrainAllUses(TII, TRI, RBI); } I.eraseFromParent(); @@ -650,14 +635,12 @@ bool MipsInstructionSelector::select(MachineInstr &I) { MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) .addDef(ResultInFPR) .addUse(I.getOperand(1).getReg()); - if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI); MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) .addDef(I.getOperand(0).getReg()) .addUse(ResultInFPR); - if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Move, TII, TRI, RBI); I.eraseFromParent(); return true; @@ -681,8 +664,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { LWGOT->addMemOperand( MF, MF.getMachineMemOperand(MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, 4, Align(4))); - if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI); if (GVal->hasLocalLinkage()) { Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); @@ -694,8 +676,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addReg(LWGOTDef) .addGlobalAddress(GVal); ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); - if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI); } } else { Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); @@ -704,8 +685,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addDef(LUiReg) .addGlobalAddress(GVal); LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI); - if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI); MachineInstr *ADDiu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) @@ -713,8 +693,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addUse(LUiReg) .addGlobalAddress(GVal); ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); - if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI); } I.eraseFromParent(); return true; @@ -810,8 +789,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { else MIB.addUse(Instruction.RHS); - if (!MIB.constrainAllUses(TII, TRI, RBI)) - return false; + MIB.constrainAllUses(TII, TRI, RBI); } I.eraseFromParent(); @@ -881,16 +859,14 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .addImm(MipsFCMPCondCode); - if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI); MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode)) .addDef(I.getOperand(0).getReg()) .addUse(Mips::ZERO) .addUse(Mips::FCC0) .addUse(TrueInReg); - if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Move, TII, TRI, RBI); I.eraseFromParent(); return true; @@ -909,15 +885,13 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addDef(LeaReg) .addFrameIndex(FI) .addImm(0); - if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI); MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW)) .addUse(LeaReg) .addUse(I.getOperand(0).getReg()) .addImm(0); - if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Store, TII, TRI, RBI); I.eraseFromParent(); return true; @@ -927,7 +901,8 @@ bool MipsInstructionSelector::select(MachineInstr &I) { } I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + return true; } namespace llvm { diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index 8468dd6a22119..e487d80e845f5 100644 --- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -470,13 +470,12 @@ static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode, MachineIRBuilder &MIRBuilder, const MipsSubtarget &ST) { assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA."); - if (!MIRBuilder.buildInstr(Opcode) - .add(MI.getOperand(0)) - .add(MI.getOperand(2)) - .add(MI.getOperand(3)) - .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), - *ST.getRegBankInfo())) - return false; + MIRBuilder.buildInstr(Opcode) + .add(MI.getOperand(0)) + .add(MI.getOperand(2)) + .add(MI.getOperand(3)) + .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), + *ST.getRegBankInfo()); MI.eraseFromParent(); return true; } diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 1a6ebc72684b7..5cb1e12854564 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -1159,10 +1159,8 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { Hi ? SDValue(Res, 0) : ZeroVal, LoVal); Res = CurDAG->getMachineNode( - Mips::SUBREG_TO_REG, DL, MVT::i64, - CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64), - SDValue(Res, 0), - CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); + Mips::SUBREG_TO_REG, DL, MVT::i64, SDValue(Res, 0), + CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0)); @@ -1265,16 +1263,12 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { if (HiResNonZero) HiRes = CurDAG->getMachineNode( - Mips::SUBREG_TO_REG, DL, MVT::i64, - CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64), - SDValue(HiRes, 0), + Mips::SUBREG_TO_REG, DL, MVT::i64, SDValue(HiRes, 0), CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); if (ResNonZero) Res = CurDAG->getMachineNode( - Mips::SUBREG_TO_REG, DL, MVT::i64, - CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64), - SDValue(Res, 0), + Mips::SUBREG_TO_REG, DL, MVT::i64, SDValue(Res, 0), CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64)); // We have 3 cases: diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 442839975c3f5..001d1326649fe 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -3336,7 +3336,6 @@ MipsSETargetLowering::emitINSERT_FW(MachineInstr &MI, : &Mips::MSA128WEvensRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) - .addImm(0) .addReg(Fs) .addImm(Mips::sub_lo); BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) @@ -3370,7 +3369,6 @@ MipsSETargetLowering::emitINSERT_FD(MachineInstr &MI, Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) - .addImm(0) .addReg(Fs) .addImm(Mips::sub_64); BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) @@ -3455,7 +3453,6 @@ MachineBasicBlock *MipsSETargetLowering::emitINSERT_DF_VIDX( if (IsFP) { Register Wt = RegInfo.createVirtualRegister(VecRC); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) - .addImm(0) .addReg(SrcValReg) .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo); SrcValReg = Wt; @@ -3611,7 +3608,6 @@ MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI, if(!UsingMips32) { Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp) - .addImm(0) .addReg(Rs) .addImm(Mips::sub_32); Rs = Tmp; diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index bf8c3cc46f550..4fbf54c72060d 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -77,10 +77,11 @@ static std::pair readsWritesFloatRegister(MachineInstr &MI, Register Reg) { bool Reads = false; bool Writes = false; - unsigned Idx = 0; + int Idx = -1; Register RegF32 = getFloatRegFromFReg(Reg); assert(RegF32 != Mips::NoRegister && "Reg is not a Float Register"); for (llvm::MachineOperand &MO : MI.operands()) { + Idx++; if (!MO.isReg()) continue; Register MORegF32 = getFloatRegFromFReg(MO.getReg()); @@ -92,7 +93,6 @@ static std::pair readsWritesFloatRegister(MachineInstr &MI, else Reads = true; } - Idx++; } return std::make_pair(Reads, Writes); } @@ -242,7 +242,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, Opc = Mips::FMOV_D64; unsigned DestRegOff = DestReg.id() - Mips::D0_64; unsigned SrcRegOff = SrcReg.id() - Mips::F0; - if (SrcRegOff == DestRegOff && SrcRegOff >= 0 && SrcRegOff <= 31) + if (SrcRegOff == DestRegOff && SrcRegOff <= 31) return; } } else if (Opc == 0 && Mips::FGR32RegClass.contains(DestReg) && @@ -253,7 +253,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, Opc = Mips::FMOV_D32; unsigned DestRegOff = DestReg.id() - Mips::F0; unsigned SrcRegOff = SrcReg.id() - Mips::D0_64; - if (SrcRegOff == DestRegOff && SrcRegOff >= 0 && SrcRegOff <= 31) + if (SrcRegOff == DestRegOff && SrcRegOff <= 31) return; } } diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp index 5ff5fa36ac467..5a5793bc7bc13 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp @@ -535,3 +535,15 @@ void NVPTXInstPrinter::printCallOperand(const MCInst *MI, int OpNum, } llvm_unreachable("Invalid modifier"); } + +template +void NVPTXInstPrinter::printHexUImm(const MCInst *MI, int OpNum, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNum); + assert(MO.isImm() && "Expected immediate operand"); + assert(isInt(MO.getImm()) && + "Immediate value does not fit in specified bits"); + uint64_t Imm = MO.getImm(); + Imm &= maskTrailingOnes(Bits); + O << formatHex(Imm) << "U"; +} diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h index 3d172441adfcc..09d4e6b1f18ed 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h @@ -56,6 +56,9 @@ class NVPTXInstPrinter : public MCInstPrinter { void printCallOperand(const MCInst *MI, int OpNum, raw_ostream &O, StringRef Modifier = {}); void printFTZFlag(const MCInst *MI, int OpNum, raw_ostream &O); + + template + void printHexUImm(const MCInst *MI, int OpNum, raw_ostream &O); }; } diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 1be35a1c67457..755d270563786 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -4247,13 +4247,13 @@ void NVPTXTargetLowering::LowerAsmOperandForConstraint( // because we need the information that is only available in the "Value" type // of destination // pointer. In particular, the address space information. -bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void NVPTXTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { default: - return false; + return; case Intrinsic::nvvm_match_all_sync_i32p: case Intrinsic::nvvm_match_all_sync_i64p: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -4264,7 +4264,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, // Our result depends on both our and other thread's arguments. Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col: case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_row: case Intrinsic::nvvm_wmma_m16n16k16_load_a_f16_col_stride: @@ -4295,7 +4296,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_load_a_s8_col: case Intrinsic::nvvm_wmma_m16n16k16_load_a_s8_col_stride: @@ -4327,7 +4329,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(8); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m32n8k16_load_a_s8_col: @@ -4376,7 +4379,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m32n8k16_load_b_s8_col: @@ -4418,7 +4422,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(4); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_load_c_f16_col: @@ -4439,7 +4444,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_load_c_f32_col: @@ -4464,7 +4470,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m32n8k16_load_a_bf16_col: @@ -4495,7 +4502,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k128_load_c_s32_col: @@ -4519,7 +4527,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(8); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k4_load_a_f64_col: @@ -4537,7 +4546,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(8); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k4_load_c_f64_col: @@ -4550,7 +4560,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_store_d_f16_col: @@ -4571,7 +4582,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_store_d_f32_col: @@ -4596,7 +4608,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m16n16k16_store_d_s32_col: @@ -4617,7 +4630,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k128_store_d_s32_col: @@ -4637,7 +4651,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(8); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_wmma_m8n8k4_store_d_f64_col: @@ -4650,7 +4665,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_stmatrix_sync_aligned_m8n8_x1_b16: @@ -4662,7 +4678,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(4); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_stmatrix_sync_aligned_m8n8_x4_b16: @@ -4674,7 +4691,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_atomic_add_gen_f_cta: @@ -4706,7 +4724,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_prefetch_tensormap: { @@ -4718,7 +4737,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tensormap_replace_global_address: @@ -4729,7 +4749,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tensormap_replace_rank: @@ -4747,7 +4768,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_ldu_global_i: @@ -4760,7 +4782,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags = MachineMemOperand::MOLoad; Info.align = cast(I.getArgOperand(1))->getMaybeAlignValue(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tex_1d_v4f32_s32: case Intrinsic::nvvm_tex_1d_v4f32_f32: @@ -4826,7 +4849,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_tex_1d_v4s32_s32: case Intrinsic::nvvm_tex_1d_v4s32_f32: @@ -4950,7 +4974,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_suld_1d_i8_clamp: case Intrinsic::nvvm_suld_1d_v2i8_clamp: @@ -5003,7 +5028,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_suld_1d_i16_clamp: case Intrinsic::nvvm_suld_1d_v2i16_clamp: @@ -5056,7 +5082,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_suld_1d_i32_clamp: case Intrinsic::nvvm_suld_1d_v2i32_clamp: @@ -5109,7 +5136,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_suld_1d_i64_clamp: case Intrinsic::nvvm_suld_1d_v2i64_clamp: @@ -5147,7 +5175,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; case Intrinsic::nvvm_tcgen05_ld_16x64b_x1: case Intrinsic::nvvm_tcgen05_ld_32x32b_x1: @@ -5158,7 +5187,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x2: @@ -5173,7 +5203,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_red_32x32b_x2_f32: @@ -5184,7 +5215,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x4: @@ -5200,7 +5232,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_red_32x32b_x4_f32: @@ -5211,7 +5244,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x8: @@ -5227,7 +5261,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_red_32x32b_x8_f32: @@ -5238,7 +5273,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x16: @@ -5254,7 +5290,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_red_32x32b_x16_f32: @@ -5265,7 +5302,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x32: @@ -5281,7 +5319,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_red_32x32b_x32_f32: @@ -5292,7 +5331,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x64: @@ -5308,7 +5348,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_red_32x32b_x64_f32: @@ -5319,7 +5360,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_16x64b_x128: @@ -5335,7 +5377,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_ld_red_32x32b_x128_f32: @@ -5346,7 +5389,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x1: @@ -5358,7 +5402,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x2: @@ -5371,7 +5416,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x4: @@ -5385,7 +5431,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x8: @@ -5399,7 +5446,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x16: @@ -5413,7 +5461,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x32: @@ -5427,7 +5476,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x64: @@ -5441,7 +5491,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_st_16x64b_x128: @@ -5455,7 +5506,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOStore; Info.align.reset(); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_mma_shared_disable_output_lane_cg1: case Intrinsic::nvvm_tcgen05_mma_shared_scale_d_disable_output_lane_cg1: @@ -5478,7 +5530,8 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } case Intrinsic::nvvm_tcgen05_mma_shared_disable_output_lane_cg2: @@ -5502,10 +5555,10 @@ bool NVPTXTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; Info.align = Align(16); - return true; + Infos.push_back(Info); + return; } } - return false; } /// getFunctionParamOptimizedAlign - since function arguments are passed via @@ -7382,46 +7435,84 @@ NVPTXTargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const { bool NVPTXTargetLowering::shouldInsertFencesForAtomic( const Instruction *I) const { - auto *CI = dyn_cast(I); - // When CAS bitwidth is not supported on the hardware, the CAS is emulated - // using a retry loop that uses a higher-bitwidth monotonic CAS. We enforce - // the memory order using explicit fences around the retry loop. - // The memory order of natively supported CAS operations can be enforced - // by lowering to an atom.cas with the right memory synchronizing effect. - // However, atom.cas only supports relaxed, acquire, release and acq_rel. - // So we also use explicit fences for enforcing memory order for - // seq_cast CAS with natively-supported bitwidths. - return CI && - (cast(CI->getCompareOperand()->getType())->getBitWidth() < - STI.getMinCmpXchgSizeInBits() || - CI->getMergedOrdering() == AtomicOrdering::SequentiallyConsistent); + // This function returns true iff the operation is emulated using a CAS-loop, + // or if it has the memory order seq_cst (which is not natively supported in + // the PTX `atom` instruction). + // + // atomicrmw and cmpxchg instructions not efficiently supported by PTX + // are lowered to CAS emulation loops that preserve their memory order, + // syncscope, and volatile semantics. For PTX, it is more efficient to use + // atom.cas.relaxed.sco instructions within the loop, and fences before and + // after the loop to restore order. + // + // Atomic instructions efficiently supported by PTX are lowered to + // `atom...(I)) + return (cast(CI->getCompareOperand()->getType()) + ->getBitWidth() < STI.getMinCmpXchgSizeInBits()) || + CI->getMergedOrdering() == AtomicOrdering::SequentiallyConsistent; + if (auto *RI = dyn_cast(I)) + return shouldExpandAtomicRMWInIR(RI) == AtomicExpansionKind::CmpXChg || + RI->getOrdering() == AtomicOrdering::SequentiallyConsistent; + return false; } AtomicOrdering NVPTXTargetLowering::atomicOperationOrderAfterFenceSplit( const Instruction *I) const { - auto *CI = dyn_cast(I); - bool BitwidthSupportedAndIsSeqCst = + // If the operation is emulated by a CAS-loop, we lower the instruction to + // atom..relaxed, since AtomicExpandPass will insert fences for enforcing + // the correct memory ordering around the CAS loop. + // + // When the operation is not emulated, but the memory order is seq_cst, + // we must lower to "fence.sc.; atom..acquire.;" to conform + // to the PTX atomics ABI. + // https://docs.nvidia.com/cuda/ptx-writers-guide-to-interoperability/atomic-abi.html + // For such cases, emitLeadingFence() will separately insert the leading + // "fence.sc.;". Here, we only set the memory order to acquire. + // + // Otherwise, the operation is not emulated, and the memory order is not + // seq_cst. In this case, the LLVM memory order is natively supported by the + // PTX `atom` instruction, and we just lower to the corresponding + // `atom..relaxed|acquire|release|acq_rel". For such cases, this function + // will NOT be called. + // prerequisite: shouldInsertFencesForAtomic() should have returned `true` for + // I before its memory order was modified. + if (auto *CI = dyn_cast(I); CI && CI->getMergedOrdering() == AtomicOrdering::SequentiallyConsistent && cast(CI->getCompareOperand()->getType())->getBitWidth() >= - STI.getMinCmpXchgSizeInBits(); - return BitwidthSupportedAndIsSeqCst ? AtomicOrdering::Acquire - : AtomicOrdering::Monotonic; + STI.getMinCmpXchgSizeInBits()) + return AtomicOrdering::Acquire; + else if (auto *RI = dyn_cast(I); + RI && RI->getOrdering() == AtomicOrdering::SequentiallyConsistent && + shouldExpandAtomicRMWInIR(RI) == AtomicExpansionKind::None) + return AtomicOrdering::Acquire; + + return AtomicOrdering::Monotonic; } Instruction *NVPTXTargetLowering::emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { - if (!isa(Inst)) + // prerequisite: shouldInsertFencesForAtomic() should have returned `true` for + // `Inst` before its memory order was modified. We cannot enforce this with an + // assert, because AtomicExpandPass will have modified the memory order + // between the initial call to shouldInsertFencesForAtomic() and the call to + // this function. + if (!isa(Inst) && !isa(Inst)) return TargetLoweringBase::emitLeadingFence(Builder, Inst, Ord); - // Specialize for cmpxchg - // Emit a fence.sc leading fence for cmpxchg seq_cst which are not emulated - SyncScope::ID SSID = cast(Inst)->getSyncScopeID(); + // Specialize for cmpxchg and atomicrmw + auto SSID = getAtomicSyncScopeID(Inst); + assert(SSID.has_value() && "Expected an atomic operation"); + if (isReleaseOrStronger(Ord)) return Builder.CreateFence(Ord == AtomicOrdering::SequentiallyConsistent - ? Ord + ? AtomicOrdering::SequentiallyConsistent : AtomicOrdering::Release, - SSID); + SSID.value()); return nullptr; } @@ -7429,19 +7520,25 @@ Instruction *NVPTXTargetLowering::emitLeadingFence(IRBuilderBase &Builder, Instruction *NVPTXTargetLowering::emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { - // Specialize for cmpxchg - if (!isa(Inst)) + // prerequisite: shouldInsertFencesForAtomic() should have returned `true` for + // `Inst` before its memory order was modified. See `emitLeadingFence` for why + // this cannot be enforced with an assert. Specialize for cmpxchg and + // atomicrmw + auto *CI = dyn_cast(Inst); + auto *RI = dyn_cast(Inst); + if (!CI && !RI) return TargetLoweringBase::emitTrailingFence(Builder, Inst, Ord); - auto *CI = cast(Inst); - auto CASWidth = - cast(CI->getCompareOperand()->getType())->getBitWidth(); - SyncScope::ID SSID = CI->getSyncScopeID(); - // Do not emit a trailing fence for cmpxchg seq_cst which are not emulated - if (isAcquireOrStronger(Ord) && - (Ord != AtomicOrdering::SequentiallyConsistent || - CASWidth < STI.getMinCmpXchgSizeInBits())) - return Builder.CreateFence(AtomicOrdering::Acquire, SSID); + auto SSID = getAtomicSyncScopeID(Inst); + assert(SSID.has_value() && "Expected an atomic operation"); + + bool IsEmulated = + CI ? cast(CI->getCompareOperand()->getType()) + ->getBitWidth() < STI.getMinCmpXchgSizeInBits() + : shouldExpandAtomicRMWInIR(RI) == AtomicExpansionKind::CmpXChg; + + if (isAcquireOrStronger(Ord) && IsEmulated) + return Builder.CreateFence(AtomicOrdering::Acquire, SSID.value()); return nullptr; } diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h index 20d49f7a6b252..9f35fe1e866fa 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h @@ -32,8 +32,8 @@ class NVPTXTargetLowering : public TargetLowering { const NVPTXSubtarget &STI); SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; Align getFunctionArgumentAlignment(const Function *F, Type *Ty, unsigned Idx, diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td index 8c07d96fcd010..e5a492fa90fbd 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td @@ -2499,7 +2499,7 @@ def NVPTX_fma_oneuse_and_nnan : PatFrag<(ops node:$a, node:$b, node:$c), // PatFrag is for a fmaxnum node with nsz def NVPTX_fmaxnum_nsz : PatFrag<(ops node:$a, node:$b), (fmaxnum node:$a, node:$b), [{ - return N->getFlags().hasNoSignedZeros() || TM.Options.NoSignedZerosFPMath; + return N->getFlags().hasNoSignedZeros(); }]>; class FMARELUInst diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td index ad5dd356ee90f..fd307a3cff604 100644 --- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td +++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td @@ -1331,10 +1331,14 @@ def INT_NVVM_NANOSLEEP_R : BasicNVPTXInst<(outs), (ins B32:$i), "nanosleep.u32", [(int_nvvm_nanosleep i32:$i)]>, Requires<[hasPTX<63>, hasSM<70>]>; +def Hexu16imm : Operand { + let PrintMethod = "printHexUImm<16>"; +} + let hasSideEffects = 1 in { // Performance Monitor events def INT_PM_EVENT_MASK : BasicNVPTXInst<(outs), - (ins i16imm:$mask), + (ins Hexu16imm:$mask), "pmevent.mask", [(int_nvvm_pm_event_mask timm:$mask)]>, Requires<[hasSM<20>, hasPTX<30>]>; @@ -2372,16 +2376,7 @@ def INT_FNS_iii : INT_FNS_MBO<(ins i32imm:$mask, i32imm:$base, i32imm:$ // Atomic Functions //----------------------------------- -class ATOMIC_GLOBAL_CHK - : PatFrag; -class ATOMIC_SHARED_CHK - : PatFrag; -class ATOMIC_SHARED_CLUSTER_CHK - : PatFrag; -class ATOMIC_GENERIC_CHK - : PatFrag; - -multiclass F_ATOMIC_2 preds> { defvar asm_str = "atom" # sem_str # as_str # "." # op_str; let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { @@ -2397,8 +2392,48 @@ multiclass F_ATOMIC_2 { + SDNodeXForm GetSem = SDNodeXForm(N)), SDLoc(N)); + }]>; + + SDNodeXForm GetScope = SDNodeXForm(N)), SDLoc(N)); + }]>; + + SDNodeXForm GetAddSp = SDNodeXForm(N)), SDLoc(N)); + }]>; +} + +multiclass F_ATOMIC_2 preds = []> { + defvar asm_str = "atom${sem:sem}${scope:scope}${addsp:addsp}" # "." # op_str; + let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { + def _r : BasicFlagsNVPTXInst<(outs t.RC:$dst), + (ins ADDR:$addr, t.RC:$b), + (ins AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp), + asm_str>, + Requires; + if t.SupportsImm then + def _i : BasicFlagsNVPTXInst<(outs t.RC:$dst), + (ins ADDR:$addr, t.Imm:$b), + (ins AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp), + asm_str>, + Requires; + } + + defvar XForm = AtomicSDNodeXForm; + + def : Pat<(op:$this addr:$addr, t.Ty:$b), + (!cast(NAME # _r) ADDR:$addr, t.Ty:$b, (XForm.GetSem $this), (XForm.GetScope $this), (XForm.GetAddSp $this))>; + + if t.SupportsImm then + def : Pat<(op:$this addr:$addr, (t.Ty t.ImmNode:$b)), + (!cast(NAME # _i) ADDR:$addr, (t.Ty t.ImmNode:$b), (XForm.GetSem $this), (XForm.GetScope $this), (XForm.GetAddSp $this))>; +} + multiclass F_ATOMIC_3 { - defvar asm_str = "atom${sem:sem}${scope:scope}${addsp:addsp}" # op_str; + defvar asm_str = "atom${sem:sem}${scope:scope}${addsp:addsp}" # "." # op_str; let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { def _rr : BasicFlagsNVPTXInst<(outs t.RC:$dst), @@ -2422,87 +2457,80 @@ multiclass F_ATOMIC_3; } - defvar GetSem = SDNodeXForm(N)), SDLoc(N)); - }]>; - - defvar GetScope = SDNodeXForm(N)), SDLoc(N)); - }]>; - - defvar GetAddSp = SDNodeXForm(N)), SDLoc(N)); - }]>; + defvar XForm = AtomicSDNodeXForm; def : Pat<(op:$this addr:$addr, t.Ty:$b, t.Ty:$c), - (!cast(NAME # _rr) ADDR:$addr, t.Ty:$b, t.Ty:$c, (GetSem $this), (GetScope $this), (GetAddSp $this))>; + (!cast(NAME # _rr) ADDR:$addr, t.Ty:$b, t.Ty:$c, (XForm.GetSem $this), (XForm.GetScope $this), (XForm.GetAddSp $this))>; def : Pat<(op:$this addr:$addr, (t.Ty t.ImmNode:$b), t.Ty:$c), - (!cast(NAME # _ir) ADDR:$addr, (t.Ty t.ImmNode:$b), t.Ty:$c, (GetSem $this), (GetScope $this), (GetAddSp $this))>; + (!cast(NAME # _ir) ADDR:$addr, (t.Ty t.ImmNode:$b), t.Ty:$c, (XForm.GetSem $this), (XForm.GetScope $this), (XForm.GetAddSp $this))>; def : Pat<(op:$this addr:$addr, t.Ty:$b, (t.Ty t.ImmNode:$c)), - (!cast(NAME # _ri) ADDR:$addr, t.Ty:$b, (t.Ty t.ImmNode:$c), (GetSem $this), (GetScope $this), (GetAddSp $this))>; + (!cast(NAME # _ri) ADDR:$addr, t.Ty:$b, (t.Ty t.ImmNode:$c), (XForm.GetSem $this), (XForm.GetScope $this), (XForm.GetAddSp $this))>; def : Pat<(op:$this addr:$addr, (t.Ty t.ImmNode:$b), (t.Ty t.ImmNode:$c)), - (!cast(NAME # _ii) ADDR:$addr, (t.Ty t.ImmNode:$b), (t.Ty t.ImmNode:$c), (GetSem $this), (GetScope $this), (GetAddSp $this))>; + (!cast(NAME # _ii) ADDR:$addr, (t.Ty t.ImmNode:$b), (t.Ty t.ImmNode:$c), (XForm.GetSem $this), (XForm.GetScope $this), (XForm.GetAddSp $this))>; } -multiclass F_ATOMIC_2_AS preds = []> { - defvar frag_pat = (frag node:$a, node:$b); - defm _G : F_ATOMIC_2, preds>; - defm _S : F_ATOMIC_2, preds>; - defm _S_C : F_ATOMIC_2, !listconcat([hasClusters], preds)>; - defm _GEN : F_ATOMIC_2, preds>; -} +defm atomic_load_fadd : binary_atomic_op_fp; // atom_add -defm INT_PTX_ATOM_ADD_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOM_ADD_64 : F_ATOMIC_2_AS; +defm INT_PTX_ATOM_ADD_32 : F_ATOMIC_2; +defm INT_PTX_ATOM_ADD_64 : F_ATOMIC_2; -defm INT_PTX_ATOM_ADD_F16 : F_ATOMIC_2_AS, hasPTX<63>]>; -defm INT_PTX_ATOM_ADD_BF16 : F_ATOMIC_2_AS, hasPTX<78>]>; -defm INT_PTX_ATOM_ADD_F32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOM_ADD_F64 : F_ATOMIC_2_AS; +defm INT_PTX_ATOM_ADD_F16 : F_ATOMIC_2, hasPTX<63>]>; +defm INT_PTX_ATOM_ADD_BF16 : F_ATOMIC_2, hasPTX<78>]>; +defm INT_PTX_ATOM_ADD_F32 : F_ATOMIC_2; +defm INT_PTX_ATOM_ADD_F64 : F_ATOMIC_2; // atom_swap -defm INT_PTX_ATOM_SWAP_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOM_SWAP_64 : F_ATOMIC_2_AS; +defm INT_PTX_ATOM_SWAP_32 : F_ATOMIC_2; +defm INT_PTX_ATOM_SWAP_64 : F_ATOMIC_2; // atom_max -defm INT_PTX_ATOMIC_MAX_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOMIC_MAX_64 : F_ATOMIC_2_AS]>; -defm INT_PTX_ATOMIC_UMAX_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOMIC_UMAX_64 : F_ATOMIC_2_AS]>; +defm INT_PTX_ATOMIC_MAX_32 : F_ATOMIC_2; +defm INT_PTX_ATOMIC_MAX_64 : F_ATOMIC_2]>; +defm INT_PTX_ATOMIC_UMAX_32 : F_ATOMIC_2; +defm INT_PTX_ATOMIC_UMAX_64 : F_ATOMIC_2]>; // atom_min -defm INT_PTX_ATOMIC_MIN_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOMIC_MIN_64 : F_ATOMIC_2_AS]>; -defm INT_PTX_ATOMIC_UMIN_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOMIC_UMIN_64 : F_ATOMIC_2_AS]>; +defm INT_PTX_ATOMIC_MIN_32 : F_ATOMIC_2; +defm INT_PTX_ATOMIC_MIN_64 : F_ATOMIC_2]>; +defm INT_PTX_ATOMIC_UMIN_32 : F_ATOMIC_2; +defm INT_PTX_ATOMIC_UMIN_64 : F_ATOMIC_2]>; + +// NOTE: The semantics for atomicrmw fmin (and fmax) upholds LangRef +// requirements. The LangRef requires the semantics of fmin/fmax to follow +// llvm.minimum/llvm.maximum[1], but allows sNaNs to be treated as qNaNs[2], +// that is the llvm.minnum(sNaN, NUM) -> qNaN case can be handled as (qNaN, NUM) +// -> NUM. NVPTX implements this by lowering to atom.min.f32[3], which has those +// semantics. +// [1] https://llvm.org/docs/LangRef.html#llvm-implementation +// [2] https://llvm.org/docs/LangRef.html#behavior-of-floating-point-nan-values +// [3] https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-min // atom_inc atom_dec -defm INT_PTX_ATOM_INC_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOM_DEC_32 : F_ATOMIC_2_AS; +defm INT_PTX_ATOM_INC_32 : F_ATOMIC_2; +defm INT_PTX_ATOM_DEC_32 : F_ATOMIC_2; // atom_and -defm INT_PTX_ATOM_AND_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOM_AND_64 : F_ATOMIC_2_AS]>; +defm INT_PTX_ATOM_AND_32 : F_ATOMIC_2; +defm INT_PTX_ATOM_AND_64 : F_ATOMIC_2]>; // atom_or -defm INT_PTX_ATOM_OR_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOM_OR_64 : F_ATOMIC_2_AS]>; +defm INT_PTX_ATOM_OR_32 : F_ATOMIC_2; +defm INT_PTX_ATOM_OR_64 : F_ATOMIC_2]>; // atom_xor -defm INT_PTX_ATOM_XOR_32 : F_ATOMIC_2_AS; -defm INT_PTX_ATOM_XOR_64 : F_ATOMIC_2_AS]>; - +defm INT_PTX_ATOM_XOR_32 : F_ATOMIC_2; +defm INT_PTX_ATOM_XOR_64 : F_ATOMIC_2]>; // Define atom.cas for all combinations of size x addrspace x memory order // supported in PTX *and* on the hardware. foreach t = [I16RT, I32RT, I64RT] in { defvar atomic_cmp_swap_pat = !cast("atomic_cmp_swap_i"#t.Size); defm INT_PTX_ATOM_CAS_#t.Size - : F_ATOMIC_3; + : F_ATOMIC_3; } // Support for scoped atomic operations. Matches @@ -2518,7 +2546,7 @@ foreach t = [I16RT, I32RT, I64RT] in { multiclass ATOM2N_impl Preds> { - defm "" : F_ATOMIC_2(MemCall)) { expandMemMoveAsLoop(Memmove, TTI); } else if (MemSetInst *Memset = dyn_cast(MemCall)) { - expandMemSetAsLoop(Memset); + expandMemSetAsLoop(Memset, TTI); } MemCall->eraseFromParent(); } diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt index 53d565013c4bc..b7601bf1e21cd 100644 --- a/llvm/lib/Target/PowerPC/CMakeLists.txt +++ b/llvm/lib/Target/PowerPC/CMakeLists.txt @@ -42,6 +42,7 @@ add_llvm_target(PowerPCCodeGen PPCMachineScheduler.cpp PPCMacroFusion.cpp PPCMIPeephole.cpp + PPCPrepareIFuncsOnAIX.cpp PPCRegisterInfo.cpp PPCSelectionDAGInfo.cpp PPCSubtarget.cpp diff --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp index 3283a5bb69404..e60ee32520f23 100644 --- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp +++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp @@ -205,7 +205,8 @@ bool PPCInstructionSelector::selectIntToFP(MachineInstr &I, BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + return true; } bool PPCInstructionSelector::selectFPToInt(MachineInstr &I, @@ -235,7 +236,8 @@ bool PPCInstructionSelector::selectFPToInt(MachineInstr &I, BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + return true; } bool PPCInstructionSelector::selectZExt(MachineInstr &I, MachineBasicBlock &MBB, @@ -269,7 +271,8 @@ bool PPCInstructionSelector::selectZExt(MachineInstr &I, MachineBasicBlock &MBB, .addImm(32); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + return true; } // For any 32 < Num < 64, check if the Imm contains at least Num consecutive @@ -301,16 +304,20 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, // 1-1) Patterns : {zeros}{15-bit valve} // {ones}{15-bit valve} - if (isInt<16>(Imm)) - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), Reg) + if (isInt<16>(Imm)) { + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), Reg) .addImm(Imm) .constrainAllUses(TII, TRI, RBI); + return true; + } // 1-2) Patterns : {zeros}{15-bit valve}{16 zeros} // {ones}{15-bit valve}{16 zeros} - if (TZ > 15 && (LZ > 32 || LO > 32)) - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Reg) + if (TZ > 15 && (LZ > 32 || LO > 32)) { + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Reg) .addImm((Imm >> 16) & 0xffff) .constrainAllUses(TII, TRI, RBI); + return true; + } // Following patterns use 2 instructions to materialize the Imm. @@ -323,14 +330,14 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, uint64_t ImmHi16 = (Imm >> 16) & 0xffff; unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8; Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) - .addImm((Imm >> 16) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) + .addImm((Imm >> 16) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Reg) .addReg(TmpReg, RegState::Kill) .addImm(Imm & 0xffff) .constrainAllUses(TII, TRI, RBI); + return true; } // 2-2) Patterns : {zeros}{ones}{15-bit value}{zeros} // {zeros}{15-bit value}{zeros} @@ -340,15 +347,15 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, // ones, and then use RLDIC to mask off the ones in both sides after rotation. if ((LZ + FO + TZ) > 48) { Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) - .addImm((Imm >> TZ) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) + .addImm((Imm >> TZ) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), Reg) .addReg(TmpReg, RegState::Kill) .addImm(TZ) .addImm(LZ) .constrainAllUses(TII, TRI, RBI); + return true; } // 2-3) Pattern : {zeros}{15-bit value}{ones} // Shift right the Imm by (48 - LZ) bits to construct a negtive 16 bits value, @@ -371,15 +378,15 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, // the Imm by a negative value. assert(LZ <= 32 && "Unexpected shift value."); Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) - .addImm(Imm >> (48 - LZ) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) + .addImm(Imm >> (48 - LZ) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) .addReg(TmpReg, RegState::Kill) .addImm(48 - LZ) .addImm(LZ) .constrainAllUses(TII, TRI, RBI); + return true; } // 2-4) Patterns : {zeros}{ones}{15-bit value}{ones} // {ones}{15-bit value}{ones} @@ -399,15 +406,15 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, // LI8: sext many leading zeros RLDICL: rotate left TO, clear left LZ if ((LZ + FO + TO) > 48) { Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) - .addImm((Imm >> TO) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) + .addImm((Imm >> TO) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) .addReg(TmpReg, RegState::Kill) .addImm(TO) .addImm(LZ) .constrainAllUses(TII, TRI, RBI); + return true; } // 2-5) Pattern : {32 zeros}{****}{0}{15-bit value} // If Hi32 is zero and the Lo16(in Lo32) can be presented as a positive 16 bit @@ -415,14 +422,14 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, // Hi16(in Lo32). if (LZ == 32 && ((Lo32 & 0x8000) == 0)) { Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) - .addImm(Lo32 & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORIS8), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) + .addImm(Lo32 & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORIS8), Reg) .addReg(TmpReg, RegState::Kill) .addImm(Lo32 >> 16) .constrainAllUses(TII, TRI, RBI); + return true; } // 2-6) Patterns : {******}{49 zeros}{******} // {******}{49 ones}{******} @@ -446,15 +453,15 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, (Shift = findContiguousZerosAtLeast(~Imm, 49))) { uint64_t RotImm = APInt(64, Imm).rotr(Shift).getZExtValue(); Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) - .addImm(RotImm & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), TmpReg) + .addImm(RotImm & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) .addReg(TmpReg, RegState::Kill) .addImm(Shift) .addImm(0) .constrainAllUses(TII, TRI, RBI); + return true; } // Following patterns use 3 instructions to materialize the Imm. @@ -471,20 +478,19 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8; Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) - .addImm(ImmHi16) - .constrainAllUses(TII, TRI, RBI)) - return false; - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) - .addReg(TmpReg, RegState::Kill) - .addImm((Imm >> TZ) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) + .addImm(ImmHi16) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) + .addReg(TmpReg, RegState::Kill) + .addImm((Imm >> TZ) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIC), Reg) .addReg(Tmp2Reg, RegState::Kill) .addImm(TZ) .addImm(LZ) .constrainAllUses(TII, TRI, RBI); + return true; } // 3-2) Pattern : {zeros}{31-bit value}{ones} // Shift right the Imm by (32 - LZ) bits to construct a negative 32 bits @@ -498,20 +504,19 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, assert(LZ <= 32 && "Unexpected shift value."); Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg) - .addImm((Imm >> (48 - LZ)) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) - .addReg(TmpReg, RegState::Kill) - .addImm((Imm >> (32 - LZ)) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg) + .addImm((Imm >> (48 - LZ)) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) + .addReg(TmpReg, RegState::Kill) + .addImm((Imm >> (32 - LZ)) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) .addReg(Tmp2Reg, RegState::Kill) .addImm(32 - LZ) .addImm(LZ) .constrainAllUses(TII, TRI, RBI); + return true; } // 3-3) Patterns : {zeros}{ones}{31-bit value}{ones} // {ones}{31-bit value}{ones} @@ -522,20 +527,19 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, if ((LZ + FO + TO) > 32) { Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg) - .addImm((Imm >> (TO + 16)) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) - .addReg(TmpReg, RegState::Kill) - .addImm((Imm >> TO) & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), TmpReg) + .addImm((Imm >> (TO + 16)) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) + .addReg(TmpReg, RegState::Kill) + .addImm((Imm >> TO) & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) .addReg(Tmp2Reg, RegState::Kill) .addImm(TO) .addImm(LZ) .constrainAllUses(TII, TRI, RBI); + return true; } // 3-4) Patterns : High word == Low word if (Hi32 == Lo32) { @@ -544,21 +548,20 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8; Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) - .addImm(ImmHi16) - .constrainAllUses(TII, TRI, RBI)) - return false; - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) - .addReg(TmpReg, RegState::Kill) - .addImm(Lo32 & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIMI), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) + .addImm(ImmHi16) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) + .addReg(TmpReg, RegState::Kill) + .addImm(Lo32 & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDIMI), Reg) .addReg(Tmp2Reg) .addReg(Tmp2Reg, RegState::Kill) .addImm(32) .addImm(0) .constrainAllUses(TII, TRI, RBI); + return true; } // 3-5) Patterns : {******}{33 zeros}{******} // {******}{33 ones}{******} @@ -574,20 +577,19 @@ std::optional PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I, unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8; Register TmpReg = MRI.createVirtualRegister(&PPC::G8RCRegClass); Register Tmp2Reg = MRI.createVirtualRegister(&PPC::G8RCRegClass); - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) - .addImm(ImmHi16) - .constrainAllUses(TII, TRI, RBI)) - return false; - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) - .addReg(TmpReg, RegState::Kill) - .addImm(RotImm & 0xffff) - .constrainAllUses(TII, TRI, RBI)) - return false; - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode), TmpReg) + .addImm(ImmHi16) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), Tmp2Reg) + .addReg(TmpReg, RegState::Kill) + .addImm(RotImm & 0xffff) + .constrainAllUses(TII, TRI, RBI); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), Reg) .addReg(Tmp2Reg, RegState::Kill) .addImm(Shift) .addImm(0) .constrainAllUses(TII, TRI, RBI); + return true; } // If we end up here then no instructions were inserted. @@ -627,19 +629,17 @@ bool PPCInstructionSelector::selectI64Imm(MachineInstr &I, if (Hi16) { Register TmpReg = Lo16 ? MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg; - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORIS8), TmpReg) - .addReg(Reg, RegState::Kill) - .addImm(Hi16) - .constrainAllUses(TII, TRI, RBI)) - return false; + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORIS8), TmpReg) + .addReg(Reg, RegState::Kill) + .addImm(Hi16) + .constrainAllUses(TII, TRI, RBI); Reg = TmpReg; } if (Lo16) { - if (!BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), DstReg) - .addReg(Reg, RegState::Kill) - .addImm(Lo16) - .constrainAllUses(TII, TRI, RBI)) - return false; + BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::ORI8), DstReg) + .addReg(Reg, RegState::Kill) + .addImm(Lo16) + .constrainAllUses(TII, TRI, RBI); } I.eraseFromParent(); return true; @@ -702,7 +702,8 @@ bool PPCInstructionSelector::selectConstantPool( } I.eraseFromParent(); - return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + return true; } bool PPCInstructionSelector::select(MachineInstr &I) { @@ -760,7 +761,8 @@ bool PPCInstructionSelector::select(MachineInstr &I) { if (!LoadStore) return false; - return constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI); + constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI); + return true; } case TargetOpcode::G_SITOFP: case TargetOpcode::G_UITOFP: diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp index 132d5a4a21adc..b9e03f087082d 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp @@ -82,8 +82,7 @@ void PPCELFStreamer::emitPrefixedInstruction(const MCInst &Inst, void PPCELFStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { - PPCMCCodeEmitter *Emitter = - static_cast(getAssembler().getEmitterPtr()); + auto &Emitter = static_cast(getAssembler().getEmitter()); // If the instruction is a part of the GOT to PC-Rel link time optimization // instruction pair, return a value, otherwise return std::nullopt. A true @@ -100,7 +99,7 @@ void PPCELFStreamer::emitInstruction(const MCInst &Inst, emitGOTToPCRelReloc(Inst); // Special handling is only for prefixed instructions. - if (!Emitter->isPrefixedInstruction(Inst)) { + if (!Emitter.isPrefixedInstruction(Inst)) { MCELFStreamer::emitInstruction(Inst, STI); return; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp index 2a6da4c097fc1..54163ee306cba 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp @@ -53,11 +53,10 @@ void PPCXCOFFStreamer::emitPrefixedInstruction(const MCInst &Inst, void PPCXCOFFStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { - PPCMCCodeEmitter *Emitter = - static_cast(getAssembler().getEmitterPtr()); + auto &Emitter = static_cast(getAssembler().getEmitter()); // Special handling is only for prefixed instructions. - if (!Emitter->isPrefixedInstruction(Inst)) { + if (!Emitter.isPrefixedInstruction(Inst)) { MCXCOFFStreamer::emitInstruction(Inst, STI); return; } diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h index a7cd5cde16b4f..88a54ac33f5a9 100644 --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -53,6 +53,7 @@ class ModulePass; FunctionPass *createPPCPreEmitPeepholePass(); FunctionPass *createPPCExpandAtomicPseudoPass(); FunctionPass *createPPCCTRLoopsPass(); + ModulePass *createPPCPrepareIFuncsOnAIXPass(); void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP); bool LowerPPCMachineOperandToMCOperand(const MachineOperand &MO, @@ -78,6 +79,7 @@ class ModulePass; void initializePPCExpandAtomicPseudoPass(PassRegistry &); void initializePPCCTRLoopsPass(PassRegistry &); void initializePPCDAGToDAGISelLegacyPass(PassRegistry &); + void initializePPCPrepareIFuncsOnAIXPass(PassRegistry &); void initializePPCLinuxAsmPrinterPass(PassRegistry &); void initializePPCAIXAsmPrinterPass(PassRegistry &); diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 45025f47333c3..64102e7b6fdae 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -48,6 +48,7 @@ #include "llvm/IR/GlobalValue.h" #include "llvm/IR/GlobalVariable.h" #include "llvm/IR/Module.h" +#include "llvm/IR/PatternMatch.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDirectives.h" @@ -83,6 +84,7 @@ using namespace llvm; using namespace llvm::XCOFF; +using namespace PatternMatch; #define DEBUG_TYPE "asmprinter" @@ -101,6 +103,19 @@ static cl::opt EnableSSPCanaryBitInTB( "aix-ssp-tb-bit", cl::init(false), cl::desc("Enable Passing SSP Canary info in Trackback on AIX"), cl::Hidden); +static cl::opt IFuncLocalIfProven( + "ifunc-local-if-proven", cl::init(false), + cl::desc("During ifunc lowering, the compiler assumes the resolver returns " + "dso-local functions and bails out if non-local functions are " + "detected; this flag flips the assumption: resolver returns " + "preemptible functions unless the compiler can prove all paths " + "return local functions."), + cl::Hidden); + +// this flag is used for testing only as it might generate bad code. +static cl::opt IFuncWarnInsteadOfError("test-ifunc-warn-noerror", + cl::init(false), cl::ReallyHidden); + // Specialize DenseMapInfo to allow // std::pair in DenseMap. // This specialization is needed here because that type is used as keys in the @@ -308,6 +323,8 @@ class PPCAIXAsmPrinter : public PPCAsmPrinter { void emitModuleCommandLines(Module &M) override; void emitRefMetadata(const GlobalObject *); + + void emitGlobalIFunc(Module &M, const GlobalIFunc &GI) override; }; } // end anonymous namespace @@ -779,6 +796,16 @@ static MCSymbol *getMCSymbolForTOCPseudoMO(const MachineOperand &MO, } } +static PPCAsmPrinter::TOCEntryType +getTOCEntryTypeForLinkage(GlobalValue::LinkageTypes Linkage) { + if (Linkage == GlobalValue::ExternalLinkage || + Linkage == GlobalValue::AvailableExternallyLinkage || + Linkage == GlobalValue::ExternalWeakLinkage) + return PPCAsmPrinter::TOCType_GlobalExternal; + + return PPCAsmPrinter::TOCType_GlobalInternal; +} + static PPCAsmPrinter::TOCEntryType getTOCEntryTypeForMO(const MachineOperand &MO) { // Use the target flags to determine if this MO is Thread Local. @@ -789,13 +816,7 @@ getTOCEntryTypeForMO(const MachineOperand &MO) { switch (MO.getType()) { case MachineOperand::MO_GlobalAddress: { const GlobalValue *GlobalV = MO.getGlobal(); - GlobalValue::LinkageTypes Linkage = GlobalV->getLinkage(); - if (Linkage == GlobalValue::ExternalLinkage || - Linkage == GlobalValue::AvailableExternallyLinkage || - Linkage == GlobalValue::ExternalWeakLinkage) - return PPCAsmPrinter::TOCType_GlobalExternal; - - return PPCAsmPrinter::TOCType_GlobalInternal; + return getTOCEntryTypeForLinkage(GlobalV->getLinkage()); } case MachineOperand::MO_ConstantPoolIndex: return PPCAsmPrinter::TOCType_ConstantPool; @@ -2909,8 +2930,10 @@ void PPCAIXAsmPrinter::emitFunctionDescriptor() { static_cast(CurrentFnDescSym)->getRepresentedCsect()); // Emit aliasing label for function descriptor csect. - for (const GlobalAlias *Alias : GOAliasMap[&MF->getFunction()]) - OutStreamer->emitLabel(getSymbol(Alias)); + // An Ifunc doesn't have a corresponding machine function. + if (MF) + for (const GlobalAlias *Alias : GOAliasMap[&MF->getFunction()]) + OutStreamer->emitLabel(getSymbol(Alias)); // Emit function entry point address. OutStreamer->emitValue(MCSymbolRefExpr::create(CurrentFnSym, OutContext), @@ -2930,11 +2953,14 @@ void PPCAIXAsmPrinter::emitFunctionDescriptor() { void PPCAIXAsmPrinter::emitFunctionEntryLabel() { // For functions without user defined section, it's not necessary to emit the // label when we have individual function in its own csect. - if (!TM.getFunctionSections() || MF->getFunction().hasSection()) + if (!TM.getFunctionSections() || (MF && MF->getFunction().hasSection())) PPCAsmPrinter::emitFunctionEntryLabel(); - const Function *F = &MF->getFunction(); + // an ifunc does not have an associated MachineFunction + if (!MF) + return; + const Function *F = &MF->getFunction(); // Emit aliasing label for function entry point label. for (const GlobalAlias *Alias : GOAliasMap[F]) OutStreamer->emitLabel( @@ -3280,17 +3306,6 @@ void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) { } bool PPCAIXAsmPrinter::doFinalization(Module &M) { - // Do streamer related finalization for DWARF. - if (hasDebugInfo()) { - // Emit section end. This is used to tell the debug line section where the - // end is for a text section if we don't use .loc to represent the debug - // line. - auto *Sec = OutContext.getObjectFileInfo()->getTextSection(); - OutStreamer->switchSectionNoPrint(Sec); - MCSymbol *Sym = Sec->getEndSymbol(OutContext); - OutStreamer->emitLabel(Sym); - } - for (MCSymbol *Sym : ExtSymSDNodeSymbols) OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern); return PPCAsmPrinter::doFinalization(M); @@ -3385,12 +3400,15 @@ void PPCAIXAsmPrinter::emitTTypeReference(const GlobalValue *GV, void PPCAIXAsmPrinter::emitRefMetadata(const GlobalObject *GO) { SmallVector MDs; GO->getMetadata(LLVMContext::MD_implicit_ref, MDs); - assert(MDs.size() && "Expected asscoiated metadata nodes"); + assert(MDs.size() && "Expected !implicit.ref metadata nodes"); for (const MDNode *MD : MDs) { const ValueAsMetadata *VAM = cast(MD->getOperand(0).get()); const GlobalValue *GV = cast(VAM->getValue()); - MCSymbol *Referenced = TM.getSymbol(GV); + MCSymbol *Referenced = + isa(GV) + ? getObjFileLowering().getFunctionEntryPointSymbol(GV, TM) + : TM.getSymbol(GV); OutStreamer->emitXCOFFRefDirective(Referenced); } } @@ -3426,6 +3444,234 @@ void PPCAIXAsmPrinter::emitModuleCommandLines(Module &M) { OutStreamer->emitXCOFFCInfoSym(".GCC.command.line", RSOS.str()); } +static bool TOCRestoreNeededForCallToImplementation(const GlobalIFunc &GI) { + enum class IsLocal { + Unknown, // Structure of the llvm::Value is not one of the recognizable + // structures, and so it's unknown if the llvm::Value is the + // address of a local function at runtime. + True, // We can statically prove that all runtime values of the + // llvm::Value is an address of a local function. + False // We can statically prove that one of the runtime values of the + // llvm::Value is the address of a non-local function; it could be + // the case that at runtime the non-local function is never + // selected but we don't care. + }; + auto Combine = [](IsLocal LHS, IsLocal RHS) -> IsLocal { + if (LHS == IsLocal::False || RHS == IsLocal::False) + return IsLocal::False; + if (LHS == IsLocal::True && RHS == IsLocal::True) + return IsLocal::True; + return IsLocal::Unknown; + }; + + // Query if the given function is local to the load module. + auto IsLocalFunc = [](const Function *F) -> IsLocal { + bool Result = F->isDSOLocal(); + LLVM_DEBUG(dbgs() << F->getName() << " is " + << (Result ? "dso_local\n" : "not dso_local\n")); + return Result ? IsLocal::True : IsLocal::False; + }; + + // Recursive walker that visits certain patterns that make up the given Value, + // and returns + // - false if at least one non-local function was seen, + // - otherwise, return unknown if some unrecognizable pattern was seen, + // - otherwise, return true (which means only recognizable patterns were seen + // and all possible values are local functions). + std::function ValueIsALocalFunc = + [&IsLocalFunc, &Combine, &ValueIsALocalFunc](const Value *V) -> IsLocal { + if (auto *F = dyn_cast(V)) + return IsLocalFunc(F); + if (!isa(V)) + return IsLocal::Unknown; + + auto *I = cast(V); + // return isP9 ? foo_p9 : foo_default; + if (auto *SI = dyn_cast(I)) + return Combine(ValueIsALocalFunc(SI->getTrueValue()), + ValueIsALocalFunc(SI->getFalseValue())); + else if (auto *PN = dyn_cast(I)) { + IsLocal Res = IsLocal::True; + for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { + Res = Combine(Res, ValueIsALocalFunc(PN->getIncomingValue(i))); + if (Res == IsLocal::False) + return Res; + } + return Res; + } + // clang-format off + // @switch.table.resolve_foo = private unnamed_addr constant [3 x ptr] [ptr @foo_static, ptr @foo_hidden, ptr @foo_protected] + // %switch.gep = getelementptr inbounds nuw ptr, ptr @switch.table, i64 %2 + // V = load ptr, ptr %switch.gep, + // clang-format on + else if (auto *Op = getPointerOperand(I)) { + while (isa(Op)) + Op = cast(Op)->getPointerOperand(); + + if (!isa(Op)) + return IsLocal::Unknown; + auto *GV = dyn_cast(Op); + if (!GV->hasInitializer() || !isa(GV->getInitializer())) + return IsLocal::Unknown; + auto *Init = cast(GV->getInitializer()); + IsLocal Res = IsLocal::True; + for (unsigned Idx = 0, End = Init->getNumOperands(); Idx != End; ++Idx) { + Res = Combine(Res, ValueIsALocalFunc(Init->getOperand(Idx))); + if (Res == IsLocal::False) + return Res; + } + return Res; + } + return IsLocal::Unknown; + }; + + auto *Resolver = GI.getResolverFunction(); + // If the resolver is preemptible then we cannot rely on its implementation. + if (IsLocalFunc(Resolver) == IsLocal::False && IFuncLocalIfProven) + return true; + + // If one of the return values of the resolver function is not a + // local function, then we have to conservatively do a TOC save/restore. + IsLocal Res = IsLocal::True; + for (auto &BB : *Resolver) { + if (!isa(BB.getTerminator())) + continue; + auto *Ret = cast(BB.getTerminator()); + Value *RV = Ret->getReturnValue(); + assert(RV); + Res = Combine(Res, ValueIsALocalFunc(RV)); + if (Res == IsLocal::False) + break; + } + // no TOC save/restore needed if either all functions were local or we're + // being optimistic and no preemptible functions were seen. + if (Res == IsLocal::True || (Res == IsLocal::Unknown && !IFuncLocalIfProven)) + return false; + return true; +} +/* + * .csect .foo[PR],5 + * .globl foo[DS] + * .globl .foo[PR] + * .lglobl ifunc_sec.foo[RW] + * .align 4 + * .csect foo[DS],2 + * .vbyte 4, .foo[PR] + * .vbyte 4, TOC[TC0] + * .vbyte 4, 0 + * .csect .foo[PR],5 + * .ref ifunc_sec.foo[RW] + * lwz 12, L..foo_desc(2) # load foo's descriptor address + * lwz 11, 8(12) # load the env pointer (for non-C/C++ functions) + * lwz 12, 0(12) # load foo.addr + * mtctr 12 + * bctr # branch to CR without setting LR so that callee + * # returns to the caller of .foo + * # -- End function + */ +void PPCAIXAsmPrinter::emitGlobalIFunc(Module &M, const GlobalIFunc &GI) { + // Set the Subtarget to that of the resolver. + const TargetSubtargetInfo *STI = + TM.getSubtargetImpl(*GI.getResolverFunction()); + bool IsPPC64 = static_cast(STI)->isPPC64(); + + // Create syms and sections that are part of the ifunc implementation: + // - Function descriptor symbol foo[RW] + // - Function entry symbol .foo[PR] + MCSectionXCOFF *FnDescSec = static_cast( + getObjFileLowering().getSectionForFunctionDescriptor(&GI, TM)); + FnDescSec->setAlignment(Align(IsPPC64 ? 8 : 4)); + + CurrentFnDescSym = FnDescSec->getQualNameSymbol(); + + CurrentFnSym = getObjFileLowering().getFunctionEntryPointSymbol(&GI, TM); + + // Start codegen: + if (TM.getFunctionSections()) + OutStreamer->switchSection( + static_cast(CurrentFnSym)->getRepresentedCsect()); + else + OutStreamer->switchSection(getObjFileLowering().getTextSection()); + + if (GI.hasMetadata(LLVMContext::MD_implicit_ref)) + emitRefMetadata(&GI); + + // generate linkage for foo and .foo + emitLinkage(&GI, CurrentFnDescSym); + emitLinkage(&GI, CurrentFnSym); + + // .align 4 + Align Alignment(STI->getTargetLowering()->getMinFunctionAlignment()); + emitAlignment(Alignment, nullptr); + + // generate foo's function descriptor + emitFunctionDescriptor(); + + emitFunctionEntryLabel(); + + // generate the code for .foo now: + if (TOCRestoreNeededForCallToImplementation(GI)) { + Twine Msg = "unimplemented: TOC register save/restore needed for ifunc \"" + + Twine(GI.getName()) + + "\", because couldn't prove all candidates " + "are static or hidden/protected visibility definitions"; + if (!IFuncWarnInsteadOfError) + reportFatalUsageError(Msg); + else + dbgs() << Msg << "\n"; + } + + auto FnDescTOCEntryType = getTOCEntryTypeForLinkage(GI.getLinkage()); + auto *FnDescTOCEntrySym = + lookUpOrCreateTOCEntry(CurrentFnDescSym, FnDescTOCEntryType); + + if (TM.getCodeModel() == CodeModel::Large) { + // addis 12, L..foo_desc@u(2) + // lwz 12, L..foo_desc@l(12) + auto *Exp_U = symbolWithSpecifier(FnDescTOCEntrySym, PPC::S_U); + OutStreamer->emitInstruction(MCInstBuilder(PPC::ADDIS) + .addReg(PPC::X12) + .addReg(PPC::X2) + .addExpr(Exp_U), + *Subtarget); + auto *Exp_L = symbolWithSpecifier(FnDescTOCEntrySym, PPC::S_L); + OutStreamer->emitInstruction(MCInstBuilder(IsPPC64 ? PPC::LD : PPC::LWZ) + .addReg(PPC::X12) + .addExpr(Exp_L) + .addReg(PPC::X12), + *Subtarget); + } else { + // lwz 12, L..foo_desc(2) + auto *Exp = MCSymbolRefExpr::create(FnDescTOCEntrySym, OutContext); + // Exp = getTOCEntryLoadingExprForXCOFF(MOSymbol, Exp, VK); + // TODO: do we need to uncomment this? + OutStreamer->emitInstruction(MCInstBuilder(IsPPC64 ? PPC::LD : PPC::LWZ) + .addReg(PPC::X12) + .addExpr(Exp) + .addReg(PPC::X2), + *Subtarget); + } + // lwz 11, 8(12) + OutStreamer->emitInstruction(MCInstBuilder(IsPPC64 ? PPC::LD : PPC::LWZ) + .addReg(PPC::X11) + .addImm(IsPPC64 ? 16 : 8) + .addReg(PPC::X12), + *Subtarget); + // lwz 12, 0(12) + OutStreamer->emitInstruction(MCInstBuilder(IsPPC64 ? PPC::LD : PPC::LWZ) + .addReg(PPC::X12) + .addImm(0) + .addReg(PPC::X12), + *Subtarget); + // mtctr 12 + OutStreamer->emitInstruction( + MCInstBuilder(IsPPC64 ? PPC::MTCTR8 : PPC::MTCTR).addReg(PPC::X12), + *Subtarget); + // bctr + OutStreamer->emitInstruction(MCInstBuilder(IsPPC64 ? PPC::BCTR8 : PPC::BCTR), + *Subtarget); +} + char PPCAIXAsmPrinter::ID = 0; INITIALIZE_PASS(PPCAIXAsmPrinter, "ppc-aix-asm-printer", diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 5451b5fe9e36a..3c2ad1b30b139 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -5438,7 +5438,6 @@ static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG, const GlobalValue *GV = cast(Callee)->getGlobal(); if (Subtarget.isAIXABI()) { - assert(!isa(GV) && "IFunc is not supported on AIX."); return getAIXFuncEntryPointSymbolSDNode(GV); } return DAG.getTargetGlobalAddress(GV, dl, Callee.getValueType(), 0, @@ -8176,7 +8175,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { // general, fsel-based lowering of select is a finite-math-only optimization. // For more information, see section F.3 of the 2.06 ISA specification. // With ISA 3.0 - if ((!DAG.getTarget().Options.NoInfsFPMath && !Flags.hasNoInfs()) || + if (!Flags.hasNoInfs() || (!DAG.getTarget().Options.NoNaNsFPMath && !Flags.hasNoNaNs()) || ResVT == MVT::f128) return Op; @@ -14646,7 +14645,6 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, Register Val64 = MRI.createVirtualRegister(&PPC::G8RCRegClass); if (IsLwat) BuildMI(*BB, MI, DL, TII->get(TargetOpcode::SUBREG_TO_REG), Val64) - .addImm(0) .addReg(ValReg) .addImm(PPC::sub_32); else @@ -14725,17 +14723,18 @@ static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) { } SDValue PPCTargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG, - const DenormalMode &Mode) const { + const DenormalMode &Mode, + SDNodeFlags Flags) const { // We only have VSX Vector Test for software Square Root. EVT VT = Op.getValueType(); if (!isTypeLegal(MVT::i1) || (VT != MVT::f64 && ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))) - return TargetLowering::getSqrtInputTest(Op, DAG, Mode); + return TargetLowering::getSqrtInputTest(Op, DAG, Mode, Flags); SDLoc DL(Op); // The output register of FTSQRT is CR field. - SDValue FTSQRT = DAG.getNode(PPCISD::FTSQRT, DL, MVT::i32, Op); + SDValue FTSQRT = DAG.getNode(PPCISD::FTSQRT, DL, MVT::i32, Op, Flags); // ftsqrt BF,FRB // Let e_b be the unbiased exponent of the double-precision // floating-point operand in register FRB. @@ -18631,10 +18630,10 @@ PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { return false; } -bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void PPCTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { case Intrinsic::ppc_atomicrmw_xchg_i128: case Intrinsic::ppc_atomicrmw_add_i128: @@ -18651,7 +18650,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(16); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::ppc_atomic_load_i128: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i128; @@ -18659,7 +18659,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(16); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::ppc_atomic_store_i128: Info.opc = ISD::INTRINSIC_VOID; Info.memVT = MVT::i128; @@ -18667,7 +18668,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(16); Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::ppc_altivec_lvx: case Intrinsic::ppc_altivec_lvxl: case Intrinsic::ppc_altivec_lvebx: @@ -18706,7 +18708,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.size = 2*VT.getStoreSize()-1; Info.align = Align(1); Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; } case Intrinsic::ppc_altivec_stvx: case Intrinsic::ppc_altivec_stvxl: @@ -18746,7 +18749,8 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.size = 2*VT.getStoreSize()-1; Info.align = Align(1); Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } case Intrinsic::ppc_stdcx: case Intrinsic::ppc_stwcx: @@ -18777,13 +18781,12 @@ bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Alignment; Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } default: break; } - - return false; } /// It returns EVT::Other if the type should be determined using generic diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 52e79469c78da..4e816790b3f02 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -492,8 +492,8 @@ namespace llvm { bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; /// It returns EVT::Other if the type should be determined using generic @@ -890,7 +890,8 @@ namespace llvm { SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override; SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, - const DenormalMode &Mode) const override; + const DenormalMode &Mode, + SDNodeFlags Flags = {}) const override; SDValue getSqrtResultForDenormInput(SDValue Operand, SelectionDAG &DAG) const override; unsigned combineRepeatedFPDivisors() const override; diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td index bd9a999237c09..1b03a3db7d112 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrP10.td +++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td @@ -1341,7 +1341,7 @@ let Predicates = [PCRelativeMemops, HasFPU] in { (PSTFDpc $FRS, $ga, 0)>; def : Pat<(v4f32 (PPCldvsxlh (PPCmatpcreladdr PCRelForm:$addr))), - (SUBREG_TO_REG (i64 1), (PLFDpc $addr, 0), sub_64)>; + (SUBREG_TO_REG (PLFDpc $addr, 0), sub_64)>; } let Predicates = [PCRelativeMemops, HasP10Vector] in { @@ -2843,7 +2843,7 @@ let Predicates = [PrefixInstrs, HasFPU] in { def : Pat<(store f64:$FRS, PDForm:$dst), (PSTFD $FRS, memri34:$dst)>; // Prefixed fpext to v2f64 def : Pat<(v4f32 (PPCldvsxlh PDForm:$src)), - (SUBREG_TO_REG (i64 1), (PLFD PDForm:$src), sub_64)>; + (SUBREG_TO_REG (PLFD PDForm:$src), sub_64)>; } diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index ed4b58fef3a26..01cc8059f6924 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -2253,7 +2253,7 @@ def VectorExtractions { def AlignValues { dag F32_TO_BE_WORD1 = (v4f32 (XSCVDPSPN $B)); - dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (i64 1), (MTVSRWZ $B), sub_64); + dag I32_TO_BE_WORD1 = (SUBREG_TO_REG (MTVSRWZ $B), sub_64); } // Integer extend helper dags 32 -> 64 @@ -2404,14 +2404,14 @@ def LoadFP { // FP merge dags (for f32 -> v4f32) def MrgFP { - dag LD32A = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64); - dag LD32B = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$B), sub_64); - dag LD32C = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$C), sub_64); - dag LD32D = (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$D), sub_64); - dag AC = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $A, sub_64), - (SUBREG_TO_REG (i64 1), $C, sub_64), 0)); - dag BD = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), - (SUBREG_TO_REG (i64 1), $D, sub_64), 0)); + dag LD32A = (SUBREG_TO_REG (LIWZX ForceXForm:$A), sub_64); + dag LD32B = (SUBREG_TO_REG (LIWZX ForceXForm:$B), sub_64); + dag LD32C = (SUBREG_TO_REG (LIWZX ForceXForm:$C), sub_64); + dag LD32D = (SUBREG_TO_REG (LIWZX ForceXForm:$D), sub_64); + dag AC = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG $A, sub_64), + (SUBREG_TO_REG $C, sub_64), 0)); + dag BD = (XVCVDPSP (XXPERMDI (SUBREG_TO_REG $B, sub_64), + (SUBREG_TO_REG $D, sub_64), 0)); dag ABhToFlt = (XVCVDPSP (XXPERMDI $A, $B, 0)); dag ABlToFlt = (XVCVDPSP (XXPERMDI $A, $B, 3)); dag BAhToFlt = (XVCVDPSP (XXPERMDI $B, $A, 0)); @@ -2438,10 +2438,10 @@ def MrgWords { // For big endian, we merge hi doublewords of (A, C) and (B, D), convert // then merge. - dag AC = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$A, sub_64), - (SUBREG_TO_REG (i64 1), f64:$C, sub_64), 0)); - dag BD = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$B, sub_64), - (SUBREG_TO_REG (i64 1), f64:$D, sub_64), 0)); + dag AC = (v2f64 (XXPERMDI (SUBREG_TO_REG f64:$A, sub_64), + (SUBREG_TO_REG f64:$C, sub_64), 0)); + dag BD = (v2f64 (XXPERMDI (SUBREG_TO_REG f64:$B, sub_64), + (SUBREG_TO_REG f64:$D, sub_64), 0)); dag CVACS = (v4i32 (XVCVDPSXWS AC)); dag CVBDS = (v4i32 (XVCVDPSXWS BD)); dag CVACU = (v4i32 (XVCVDPUXWS AC)); @@ -2449,10 +2449,10 @@ def MrgWords { // For little endian, we merge hi doublewords of (D, B) and (C, A), convert // then merge. - dag DB = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$D, sub_64), - (SUBREG_TO_REG (i64 1), f64:$B, sub_64), 0)); - dag CA = (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), f64:$C, sub_64), - (SUBREG_TO_REG (i64 1), f64:$A, sub_64), 0)); + dag DB = (v2f64 (XXPERMDI (SUBREG_TO_REG f64:$D, sub_64), + (SUBREG_TO_REG f64:$B, sub_64), 0)); + dag CA = (v2f64 (XXPERMDI (SUBREG_TO_REG f64:$C, sub_64), + (SUBREG_TO_REG f64:$A, sub_64), 0)); dag CVDBS = (v4i32 (XVCVDPSXWS DB)); dag CVCAS = (v4i32 (XVCVDPSXWS CA)); dag CVDBU = (v4i32 (XVCVDPUXWS DB)); @@ -2863,31 +2863,31 @@ def : Pat<(v2i64 immAllZerosV), // Build vectors of floating point converted to i32. def : Pat<(v4i32 (build_vector DblToInt.A, DblToInt.A, DblToInt.A, DblToInt.A)), - (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS $A), sub_64), 1))>; + (v4i32 (XXSPLTW (SUBREG_TO_REG (XSCVDPSXWS $A), sub_64), 1))>; def : Pat<(v4i32 (build_vector DblToUInt.A, DblToUInt.A, DblToUInt.A, DblToUInt.A)), - (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS $A), sub_64), 1))>; + (v4i32 (XXSPLTW (SUBREG_TO_REG (XSCVDPUXWS $A), sub_64), 1))>; def : Pat<(v2i64 (build_vector DblToLong.A, DblToLong.A)), - (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), - (SUBREG_TO_REG (i64 1), (XSCVDPSXDS $A), sub_64), 0))>; + (v2i64 (XXPERMDI (SUBREG_TO_REG (XSCVDPSXDS $A), sub_64), + (SUBREG_TO_REG (XSCVDPSXDS $A), sub_64), 0))>; def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)), - (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), - (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 0))>; + (v2i64 (XXPERMDI (SUBREG_TO_REG (XSCVDPUXDS $A), sub_64), + (SUBREG_TO_REG (XSCVDPUXDS $A), sub_64), 0))>; def : Pat<(v4i32 (PPCSToV DblToInt.A)), - (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>; + (v4i32 (SUBREG_TO_REG (XSCVDPSXWS f64:$A), sub_64))>; def : Pat<(v4i32 (PPCSToV DblToUInt.A)), - (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPUXWS f64:$A), sub_64))>; + (v4i32 (SUBREG_TO_REG (XSCVDPUXWS f64:$A), sub_64))>; defm : ScalToVecWPermute< v4i32, FltToIntLoad.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; defm : ScalToVecWPermute< v4i32, FltToUIntLoad.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPUXWSs (XFLOADf32 ForceXForm:$A)), sub_64)>; def : Pat<(v4f32 (build_vector (f32 (fpround f64:$A)), (f32 (fpround f64:$A)), (f32 (fpround f64:$A)), (f32 (fpround f64:$A)))), - (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$A), sub_64), 0))>; + (v4f32 (XXSPLTW (SUBREG_TO_REG (XSCVDPSP f64:$A), sub_64), 0))>; def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)), (v4f32 (XXSPLTW (v4f32 (XSCVDPSPN $A)), 0))>; @@ -2896,11 +2896,11 @@ def : Pat<(v4f32 (build_vector f32:$A, f32:$A, f32:$A, f32:$A)), def : Pat<(v2f64 (PPCldsplat ForceXForm:$A)), (v2f64 (LXVDSX ForceXForm:$A))>; def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)), - (v4f32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>; + (v4f32 (XXSPLTW (SUBREG_TO_REG (LFIWZX ForceXForm:$A), sub_64), 1))>; def : Pat<(v2i64 (PPCldsplat ForceXForm:$A)), (v2i64 (LXVDSX ForceXForm:$A))>; def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)), - (v4i32 (XXSPLTW (SUBREG_TO_REG (i64 1), (LFIWZX ForceXForm:$A), sub_64), 1))>; + (v4i32 (XXSPLTW (SUBREG_TO_REG (LFIWZX ForceXForm:$A), sub_64), 1))>; def : Pat<(v2i64 (PPCzextldsplat ForceXForm:$A)), (v2i64 (XXPERMDIs (LFIWZX ForceXForm:$A), 0))>; def : Pat<(v2i64 (PPCsextldsplat ForceXForm:$A)), @@ -2967,7 +2967,7 @@ def : Pat<(PPCstore_scal_int_from_vsr f128:$src, XForm:$dst, 8), // Any big endian VSX subtarget. let Predicates = [HasVSX, IsBigEndian] in { def : Pat<(v2f64 (scalar_to_vector f64:$A)), - (v2f64 (SUBREG_TO_REG (i64 1), $A, sub_64))>; + (v2f64 (SUBREG_TO_REG $A, sub_64))>; def : Pat<(f64 (extractelt v2f64:$S, 0)), (f64 (EXTRACT_SUBREG $S, sub_64))>; @@ -2987,8 +2987,8 @@ def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), (v2f64 (XXPERMDI - (SUBREG_TO_REG (i64 1), $A, sub_64), - (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; + (SUBREG_TO_REG $A, sub_64), + (SUBREG_TO_REG $B, sub_64), 0))>; // Using VMRGEW to assemble the final vector would be a lower latency // solution. However, we choose to go with the slightly higher latency // XXPERMDI for 2 reasons: @@ -3072,17 +3072,17 @@ def : Pat; def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)), - (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>; + (v2f64 (XXPERMDI (SUBREG_TO_REG $B, sub_64), $A, 1))>; def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)), - (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; + (v2f64 (XXPERMDI $A, (SUBREG_TO_REG $B, sub_64), 0))>; } // HasVSX, IsBigEndian // Any little endian VSX subtarget. let Predicates = [HasVSX, IsLittleEndian] in { defm : ScalToVecWPermute; + (XXPERMDI (SUBREG_TO_REG $A, sub_64), + (SUBREG_TO_REG $A, sub_64), 0), + (SUBREG_TO_REG $A, sub_64)>; def : Pat<(f64 (extractelt v2f64:$S, 0)), (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>; @@ -3112,8 +3112,8 @@ def : Pat<(f64 (vector_extract v2f64:$S, i64:$Idx)), // Little endian, available on all targets with VSX def : Pat<(v2f64 (build_vector f64:$A, f64:$B)), (v2f64 (XXPERMDI - (SUBREG_TO_REG (i64 1), $B, sub_64), - (SUBREG_TO_REG (i64 1), $A, sub_64), 0))>; + (SUBREG_TO_REG $B, sub_64), + (SUBREG_TO_REG $A, sub_64), 0))>; // Using VMRGEW to assemble the final vector would be a lower latency // solution. However, we choose to go with the slightly higher latency // XXPERMDI for 2 reasons: @@ -3197,9 +3197,9 @@ def : Pat; def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)), - (v2f64 (XXPERMDI $A, (SUBREG_TO_REG (i64 1), $B, sub_64), 0))>; + (v2f64 (XXPERMDI $A, (SUBREG_TO_REG $B, sub_64), 0))>; def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)), - (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>; + (v2f64 (XXPERMDI (SUBREG_TO_REG $B, sub_64), $A, 1))>; } // HasVSX, IsLittleEndian // Any pre-Power9 VSX subtarget. @@ -3212,21 +3212,21 @@ def : Pat<(PPCstore_scal_int_from_vsr f128:$src, ForceXForm:$dst, 8), // Load-and-splat with fp-to-int conversion (using X-Form VSX/FP loads). defm : ScalToVecWPermute< v4i32, DblToIntLoad.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPSXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; defm : ScalToVecWPermute< v4i32, DblToUIntLoad.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPUXWS (XFLOADf64 ForceXForm:$A)), sub_64)>; defm : ScalToVecWPermute< v2i64, FltToLongLoad.A, (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0), - (SUBREG_TO_REG (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), + (SUBREG_TO_REG (XSCVDPSXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), sub_64)>; defm : ScalToVecWPermute< v2i64, FltToULongLoad.A, (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), 0), - (SUBREG_TO_REG (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), + (SUBREG_TO_REG (XSCVDPUXDS (COPY_TO_REGCLASS (XFLOADf32 ForceXForm:$A), VSFRC)), sub_64)>; } // HasVSX, NoP9Vector @@ -3236,11 +3236,11 @@ let Predicates = [HasVSX, NoP9Vector, IsLittleEndian] in { defm : ScalToVecWPermute< v2i64, (i64 (load ForceXForm:$src)), (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v2f64, (f64 (load ForceXForm:$src)), (XXPERMDIs (XFLOADf64 ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 ForceXForm:$src), sub_64)>; // Splat loads. def : Pat<(v8i16 (PPCldsplatAlign16 ForceXForm:$A)), @@ -3284,7 +3284,7 @@ let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in { def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, ForceXForm:$dst), (STXVW4X $rS, ForceXForm:$dst)>; def : Pat<(v2i64 (scalar_to_vector (i64 (load ForceXForm:$src)))), - (SUBREG_TO_REG (i64 1), (XFLOADf64 ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 ForceXForm:$src), sub_64)>; } // HasVSX, HasOnlySwappingMemOps, IsBigEndian // Target before Power8 with VSX. @@ -3450,11 +3450,11 @@ def : Pat<(f64 (vector_extract v2f64:$S, i32:$Idx)), defm : ScalToVecWPermute< v4i32, (i32 (load ForceXForm:$src)), (XXSLDWIs (LIWZX ForceXForm:$src), 1), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4f32, (f32 (load ForceXForm:$src)), (XXSLDWIs (LIWZX ForceXForm:$src), 1), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; } // HasVSX, HasP8Vector, IsBigEndian // Big endian Power8 64Bit VSX subtarget. @@ -3466,9 +3466,9 @@ def : Pat<(f32 (vector_extract v4f32:$S, i64:$Idx)), // LIWZX - This instruction will be emitted for i32, f32, and when // zero-extending i32 to i64 (zext i32 -> i64). def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 ForceXForm:$src)))), - (v2i64 (SUBREG_TO_REG (i64 1), (LIWAX ForceXForm:$src), sub_64))>; + (v2i64 (SUBREG_TO_REG (LIWAX ForceXForm:$src), sub_64))>; def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 ForceXForm:$src)))), - (v2i64 (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64))>; + (v2i64 (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64))>; def : Pat; + (SUBREG_TO_REG (LIWAX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v2i64, (i64 (zextloadi32 ForceXForm:$src)), (XXPERMDIs (LIWZX ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4i32, (i32 (load ForceXForm:$src)), (XXPERMDIs (LIWZX ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4f32, (f32 (load ForceXForm:$src)), (XXPERMDIs (LIWZX ForceXForm:$src), 2), - (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LIWZX ForceXForm:$src), sub_64)>; def : Pat; + (v8i16 (SUBREG_TO_REG (MTVSRWZ $A), sub_64))>; def : Pat<(v16i8 (PPCmtvsrz i32:$A)), - (v16i8 (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64))>; + (v16i8 (SUBREG_TO_REG (MTVSRWZ $A), sub_64))>; // Endianness-neutral constant splat on P8 and newer targets. The reason // for this pattern is that on targets with direct moves, we don't expand @@ -3685,18 +3685,18 @@ let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in { // v16i8 scalar <-> vector conversions (BE) defm : ScalToVecWPermute< v16i8, (i32 i32:$A), - (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; + (SUBREG_TO_REG MovesToVSR.BE_BYTE_0, sub_64), + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; defm : ScalToVecWPermute< v8i16, (i32 i32:$A), - (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; + (SUBREG_TO_REG MovesToVSR.BE_HALF_0, sub_64), + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; defm : ScalToVecWPermute< v4i32, (i32 i32:$A), - (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; + (SUBREG_TO_REG MovesToVSR.BE_WORD_0, sub_64), + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; def : Pat<(v2i64 (scalar_to_vector i64:$A)), - (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>; + (v2i64 (SUBREG_TO_REG MovesToVSR.BE_DWORD_0, sub_64))>; // v2i64 scalar <-> vector conversions (BE) def : Pat<(i64 (vector_extract v2i64:$S, 0)), @@ -3717,7 +3717,7 @@ let Predicates = [HasVSX, HasDirectMove, IsLittleEndian] in { (COPY_TO_REGCLASS MovesToVSR.LE_WORD_0, VSRC), (COPY_TO_REGCLASS MovesToVSR.LE_WORD_1, VSRC)>; defm : ScalToVecWPermute; + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; defm : ScalToVecWPermute; @@ -3875,16 +3875,16 @@ let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64] in { // Big endian integer vectors using direct moves. def : Pat<(v2i64 (build_vector i64:$A, i64:$B)), (v2i64 (XXPERMDI - (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), 0))>; + (SUBREG_TO_REG (MTVSRD $A), sub_64), + (SUBREG_TO_REG (MTVSRD $B), sub_64), 0))>; def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), (XXPERMDI - (SUBREG_TO_REG (i64 1), + (SUBREG_TO_REG (MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), sub_64), - (SUBREG_TO_REG (i64 1), + (SUBREG_TO_REG (MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), sub_64), 0)>; def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), - (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>; + (XXSPLTW (SUBREG_TO_REG (MTVSRWZ $A), sub_64), 1)>; } // HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64 // Little endian pre-Power9 VSX subtarget that has direct moves. @@ -3892,16 +3892,16 @@ let Predicates = [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian] in { // Little endian integer vectors using direct moves. def : Pat<(v2i64 (build_vector i64:$A, i64:$B)), (v2i64 (XXPERMDI - (SUBREG_TO_REG (i64 1), (MTVSRD $B), sub_64), - (SUBREG_TO_REG (i64 1), (MTVSRD $A), sub_64), 0))>; + (SUBREG_TO_REG (MTVSRD $B), sub_64), + (SUBREG_TO_REG (MTVSRD $A), sub_64), 0))>; def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)), (XXPERMDI - (SUBREG_TO_REG (i64 1), + (SUBREG_TO_REG (MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), sub_64), - (SUBREG_TO_REG (i64 1), + (SUBREG_TO_REG (MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), sub_64), 0)>; def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), - (XXSPLTW (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64), 1)>; + (XXSPLTW (SUBREG_TO_REG (MTVSRWZ $A), sub_64), 1)>; } // Any Power9 VSX subtarget. @@ -4006,39 +4006,39 @@ def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, XForm:$dst), // Build vectors from i8 loads defm : ScalToVecWPermute; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4i32, ScalarLoads.SELi8, (XXSPLTWs (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), 1), - (SUBREG_TO_REG (i64 1), (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>; + (SUBREG_TO_REG (VEXTSB2Ws (LXSIBZX ForceXForm:$src)), sub_64)>; defm : ScalToVecWPermute< v2i64, ScalarLoads.SELi8i64, (XXPERMDIs (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), 0), - (SUBREG_TO_REG (i64 1), (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>; + (SUBREG_TO_REG (VEXTSB2Ds (LXSIBZX ForceXForm:$src)), sub_64)>; // Build vectors from i16 loads defm : ScalToVecWPermute< v4i32, ScalarLoads.ZELi16, (XXSPLTWs (LXSIHZX ForceXForm:$src), 1), - (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIHZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v2i64, ScalarLoads.ZELi16i64, (XXPERMDIs (LXSIHZX ForceXForm:$src), 0), - (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIHZX ForceXForm:$src), sub_64)>; defm : ScalToVecWPermute< v4i32, ScalarLoads.SELi16, (XXSPLTWs (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), 1), - (SUBREG_TO_REG (i64 1), (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>; + (SUBREG_TO_REG (VEXTSH2Ws (LXSIHZX ForceXForm:$src)), sub_64)>; defm : ScalToVecWPermute< v2i64, ScalarLoads.SELi16i64, (XXPERMDIs (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), 0), - (SUBREG_TO_REG (i64 1), (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>; + (SUBREG_TO_REG (VEXTSH2Ds (LXSIHZX ForceXForm:$src)), sub_64)>; // Load/convert and convert/store patterns for f16. def : Pat<(f128 (extloadf16 ForceXForm:$src)), @@ -4073,9 +4073,9 @@ def : Pat<(f32 (fpround (f64 (extloadf32 DSForm:$src)))), (f32 (DFLOADf32 DSForm:$src))>; def : Pat<(v4f32 (PPCldvsxlh XForm:$src)), - (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64)>; def : Pat<(v4f32 (PPCldvsxlh DSForm:$src)), - (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; + (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64)>; // Convert (Un)Signed DWord in memory -> QP def : Pat<(f128 (sint_to_fp (i64 (load XForm:$src)))), @@ -4137,7 +4137,7 @@ def : Pat<(f32 (PPCxsminc f32:$XA, f32:$XB)), // Endianness-neutral patterns for const splats with ISA 3.0 instructions. defm : ScalToVecWPermute; + (SUBREG_TO_REG (MTVSRWZ $A), sub_64)>; def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)), (v4i32 (MTVSRWS $A))>; def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, @@ -4152,30 +4152,28 @@ def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A, defm : ScalToVecWPermute< v4i32, FltToIntLoad.A, (XVCVSPSXWS (LXVWSX ForceXForm:$A)), - (XVCVSPSXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>; + (XVCVSPSXWS (SUBREG_TO_REG (LIWZX ForceXForm:$A), sub_64))>; defm : ScalToVecWPermute< v4i32, FltToUIntLoad.A, (XVCVSPUXWS (LXVWSX ForceXForm:$A)), - (XVCVSPUXWS (SUBREG_TO_REG (i64 1), (LIWZX ForceXForm:$A), sub_64))>; + (XVCVSPUXWS (SUBREG_TO_REG (LIWZX ForceXForm:$A), sub_64))>; defm : ScalToVecWPermute< v4i32, DblToIntLoadP9.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPSXWS (DFLOADf64 DSForm:$A)), sub_64)>; defm : ScalToVecWPermute< v4i32, DblToUIntLoadP9.A, - (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1), - (SUBREG_TO_REG (i64 1), (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>; + (XXSPLTW (SUBREG_TO_REG (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64), 1), + (SUBREG_TO_REG (XSCVDPUXWS (DFLOADf64 DSForm:$A)), sub_64)>; defm : ScalToVecWPermute< v2i64, FltToLongLoadP9.A, (XXPERMDIs (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0), (SUBREG_TO_REG - (i64 1), (XSCVDPSXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>; defm : ScalToVecWPermute< v2i64, FltToULongLoadP9.A, (XXPERMDIs (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), 0), (SUBREG_TO_REG - (i64 1), (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 DSForm:$A), VSFRC)), sub_64)>; def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)), (v4f32 (LXVWSX ForceXForm:$A))>; @@ -4201,12 +4199,12 @@ let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in { defm : ScalToVecWPermute< v16i8, ScalarLoads.Li8, (VSPLTBs 7, (LXSIBZX ForceXForm:$src)), - (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; // Build vectors from i16 loads defm : ScalToVecWPermute< v8i16, ScalarLoads.Li16, (VSPLTHs 3, (LXSIHZX ForceXForm:$src)), - (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIHZX ForceXForm:$src), sub_64)>; } // HasVSX, HasP9Vector, NoP10Vector // Any big endian Power9 VSX subtarget @@ -4217,12 +4215,12 @@ let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in { defm : ScalToVecWPermute< v16i8, ScalarLoads.Li8, (VSPLTBs 7, (LXSIBZX ForceXForm:$src)), - (SUBREG_TO_REG (i64 1), (LXSIBZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIBZX ForceXForm:$src), sub_64)>; // Build vectors from i16 loads defm : ScalToVecWPermute< v8i16, ScalarLoads.Li16, (VSPLTHs 3, (LXSIHZX ForceXForm:$src)), - (SUBREG_TO_REG (i64 1), (LXSIHZX ForceXForm:$src), sub_64)>; + (SUBREG_TO_REG (LXSIHZX ForceXForm:$src), sub_64)>; def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))), (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>; @@ -4244,49 +4242,41 @@ def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 12))>; def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 0))>; @@ -4299,16 +4289,16 @@ def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 0))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 4))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 8))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 12))>; // Scalar stores of i8 def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$S, 0)), ForceXForm:$dst), @@ -4366,14 +4356,14 @@ def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst), // Big endian 64Bit Power9 subtarget. let Predicates = [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] in { def : Pat<(v2i64 (scalar_to_vector (i64 (load DSForm:$src)))), - (v2i64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>; + (v2i64 (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64))>; def : Pat<(v2i64 (scalar_to_vector (i64 (load XForm:$src)))), - (v2i64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>; + (v2i64 (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64))>; def : Pat<(v2f64 (scalar_to_vector (f64 (load DSForm:$src)))), - (v2f64 (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64))>; + (v2f64 (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64))>; def : Pat<(v2f64 (scalar_to_vector (f64 (load XForm:$src)))), - (v2f64 (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64))>; + (v2f64 (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64))>; def : Pat<(store (i64 (extractelt v2i64:$A, 1)), XForm:$src), (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), sub_64), XForm:$src)>; @@ -4503,7 +4493,7 @@ foreach Idx = 0-15 in { // Unsiged int in vsx register -> QP def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), (f128 (XSCVUDQP - (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 4)))>; + (XXEXTRACTUW (SUBREG_TO_REG $src, sub_64), 4)))>; } // HasVSX, HasP9Vector, IsBigEndian, IsPPC64 // Little endian Power9 subtarget. @@ -4528,49 +4518,41 @@ def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 0)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 0)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 0)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 12))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 1)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 1)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 1)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 8))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 2)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 2)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 2)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 4))>; def : Pat<(v4i32 (insertelt v4i32:$A, i32:$B, 3)), (v4i32 (XXINSERTW v4i32:$A, AlignValues.I32_TO_BE_WORD1, 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToInt.B, 3)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPSXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPSXWS f64:$B), sub_64), 0))>; def : Pat<(v4i32 (insertelt v4i32:$A, DblToUInt.B, 3)), (v4i32 (XXINSERTW v4i32:$A, - (SUBREG_TO_REG (i64 1), - (XSCVDPUXWS f64:$B), sub_64), + (SUBREG_TO_REG (XSCVDPUXWS f64:$B), sub_64), 0))>; def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 0)), (v4f32 (XXINSERTW v4f32:$A, AlignValues.F32_TO_BE_WORD1, 12))>; @@ -4583,16 +4565,16 @@ def : Pat<(v4f32 (insertelt v4f32:$A, f32:$B, 3)), def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 0)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 12))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 12))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 1)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 8))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 8))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 2)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 4))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 4))>; def : Pat<(v4f32 (insertelt v4f32:$A, (f32 (fpround f64:$B)), 3)), (v4f32 (XXINSERTW v4f32:$A, - (SUBREG_TO_REG (i64 1), (XSCVDPSP f64:$B), sub_64), 0))>; + (SUBREG_TO_REG (XSCVDPSP f64:$B), sub_64), 0))>; def : Pat<(v8i16 (PPCld_vec_be ForceXForm:$src)), (COPY_TO_REGCLASS (LXVH8X ForceXForm:$src), VRRC)>; @@ -4659,19 +4641,19 @@ def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$S, 7)), ForceXForm:$dst), defm : ScalToVecWPermute< v2i64, (i64 (load DSForm:$src)), (XXPERMDIs (DFLOADf64 DSForm:$src), 2), - (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; + (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64)>; defm : ScalToVecWPermute< v2i64, (i64 (load XForm:$src)), (XXPERMDIs (XFLOADf64 XForm:$src), 2), - (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64)>; defm : ScalToVecWPermute< v2f64, (f64 (load DSForm:$src)), (XXPERMDIs (DFLOADf64 DSForm:$src), 2), - (SUBREG_TO_REG (i64 1), (DFLOADf64 DSForm:$src), sub_64)>; + (SUBREG_TO_REG (DFLOADf64 DSForm:$src), sub_64)>; defm : ScalToVecWPermute< v2f64, (f64 (load XForm:$src)), (XXPERMDIs (XFLOADf64 XForm:$src), 2), - (SUBREG_TO_REG (i64 1), (XFLOADf64 XForm:$src), sub_64)>; + (SUBREG_TO_REG (XFLOADf64 XForm:$src), sub_64)>; def : Pat<(store (i64 (extractelt v2i64:$A, 0)), XForm:$src), (XFSTOREf64 (EXTRACT_SUBREG (XXPERMDI $A, $A, 2), @@ -4826,7 +4808,7 @@ foreach Idx = [[0,15],[1,14],[2,13],[3,12],[4,11],[5,10],[6,9],[7,8],[8,7], // Unsiged int in vsx register -> QP def : Pat<(f128 (uint_to_fp (i32 (PPCmfvsr f64:$src)))), (f128 (XSCVUDQP - (XXEXTRACTUW (SUBREG_TO_REG (i64 1), $src, sub_64), 8)))>; + (XXEXTRACTUW (SUBREG_TO_REG $src, sub_64), 8)))>; } // HasVSX, HasP9Vector, IsLittleEndian // Any Power9 VSX subtarget that supports Power9 Altivec. diff --git a/llvm/lib/Target/PowerPC/PPCPrepareIFuncsOnAIX.cpp b/llvm/lib/Target/PowerPC/PPCPrepareIFuncsOnAIX.cpp new file mode 100644 index 0000000000000..5b6a6d6b95c52 --- /dev/null +++ b/llvm/lib/Target/PowerPC/PPCPrepareIFuncsOnAIX.cpp @@ -0,0 +1,114 @@ +//===-- PPCPrepareIFuncsOnAIX.cpp - Prepare for ifunc lowering in codegen ===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This pass generates... +// +//===----------------------------------------------------------------------===// + +#include "PPC.h" +#include "PPCSubtarget.h" +#include "PPCTargetMachine.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Module.h" +#include + +using namespace llvm; + +#define DEBUG_TYPE "ppc-prep-ifunc-aix" + +STATISTIC(NumIFuncs, "Number of IFuncs prepared"); + +namespace { +class PPCPrepareIFuncsOnAIX : public ModulePass { +public: + static char ID; + + PPCPrepareIFuncsOnAIX() : ModulePass(ID) {} + + bool runOnModule(Module &M) override; + + StringRef getPassName() const override { + return "PPC Prepare for AIX IFunc lowering"; + } +}; +} // namespace + +char PPCPrepareIFuncsOnAIX::ID = 0; + +INITIALIZE_PASS(PPCPrepareIFuncsOnAIX, DEBUG_TYPE, + "PPC Prepare for AIX IFunc lowering", false, false) + +ModulePass *llvm::createPPCPrepareIFuncsOnAIXPass() { + return new PPCPrepareIFuncsOnAIX(); +} + +// For each ifunc `foo` with a resolver `foo_resolver`, create a global variable +// `__update_foo` in the `ifunc_sec` section, representing the pair: +// { ptr @foo, ptr @foo_resolver } +// The compiler arranges for the constructor function `__init_ifuncs` to be +// included on the link step. The constructor walks the `ifunc_sec` section, +// calling the resolver function and storing the result in foo's descriptor. +// On AIX, the address of a function is the address of its descriptor, so the +// constructor accesses foo's descriptor from the first field of the pair. +// +// Since the global `__update_foo` is unreferenced, it's liveness needs to be +// associated to the liveness of ifunc `foo` +// +bool PPCPrepareIFuncsOnAIX::runOnModule(Module &M) { + if (M.ifuncs().empty()) + return false; + + const DataLayout &DL = M.getDataLayout(); + LLVMContext &Ctx = M.getContext(); + auto *PtrTy = PointerType::getUnqual(Ctx); + StringRef IFuncUpdatePrefix = "__update_"; + StringRef IFuncUpdateSectionName = "__ifunc_sec"; + StructType *IFuncPairType = StructType::get(PtrTy, PtrTy); + + StringRef IFuncConstructorName = "__init_ifuncs"; + auto *IFuncConstructorFnType = + FunctionType::get(Type::getVoidTy(Ctx), {}, /*isVarArg=*/false); + auto *IFuncConstructorDecl = cast( + M.getOrInsertFunction(IFuncConstructorName, IFuncConstructorFnType) + .getCallee()); + + for (GlobalIFunc &IFunc : M.ifuncs()) { + NumIFuncs++; + LLVM_DEBUG(dbgs() << "expanding ifunc " << IFunc.getName() << "\n"); + // @__update_foo = private global { ptr @foo, ptr @foo_resolver }, + // section "ifunc_sec" + std::string Name = (Twine(IFuncUpdatePrefix) + IFunc.getName()).str(); + auto *GV = new GlobalVariable(M, IFuncPairType, /*isConstant*/ false, + GlobalValue::PrivateLinkage, nullptr, Name); + GV->setAlignment(DL.getPointerPrefAlignment()); + GV->setSection(IFuncUpdateSectionName); + + // Note that on AIX, the address of a function is the address of it's + // function descriptor, which is what these two values end up being + // in assembly. + Constant *InitVals[] = {&IFunc, IFunc.getResolver()}; + GV->setInitializer(ConstantStruct::get(IFuncPairType, InitVals)); + + // Liveness of __update_foo is dependent on liveness of ifunc foo. + IFunc.setMetadata(LLVMContext::MD_implicit_ref, + MDNode::get(Ctx, ValueAsMetadata::get(GV))); + + // An implicit.ref creates linkage dependency, so make function foo require + // the constructor that calls each ifunc's resolver and saves the result in + // the ifunc's function descriptor. + IFunc.addMetadata( + LLVMContext::MD_implicit_ref, + *MDNode::get(Ctx, ValueAsMetadata::get(IFuncConstructorDecl))); + } + + return true; +} diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp index 6f087ec47ddc2..dc8434fc703bf 100644 --- a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp @@ -81,6 +81,13 @@ std::pair PPCSelectionDAGInfo::EmitTargetCodeForMemcmp( return DAG.getMemcmp(Chain, dl, Op1, Op2, Op3, CI); } +std::pair PPCSelectionDAGInfo::EmitTargetCodeForStrcmp( + SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, + MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo, + const CallInst *CI) const { + return DAG.getStrcmp(Chain, DL, Op1, Op2, CI); +} + std::pair PPCSelectionDAGInfo::EmitTargetCodeForStrcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, diff --git a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h index d617501366cb8..ae6ae85d0b0e9 100644 --- a/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h +++ b/llvm/lib/Target/PowerPC/PPCSelectionDAGInfo.h @@ -76,7 +76,10 @@ class PPCSelectionDAGInfo : public SelectionDAGGenTargetInfo { EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, const CallInst *CI) const override; - + std::pair EmitTargetCodeForStrcmp( + SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, + SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo, + const CallInst *CI) const override; std::pair EmitTargetCodeForStrcpy(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest, SDValue Src, diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 4ff489d482fa5..ccfb5391ff897 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -145,6 +145,7 @@ LLVMInitializePowerPCTarget() { initializeGlobalISel(PR); initializePPCCTRLoopsPass(PR); initializePPCDAGToDAGISelLegacyPass(PR); + initializePPCPrepareIFuncsOnAIXPass(PR); initializePPCLinuxAsmPrinterPass(PR); initializePPCAIXAsmPrinterPass(PR); } @@ -438,6 +439,9 @@ void PPCPassConfig::addIRPasses() { addPass(createLICMPass()); } + if (TM->getTargetTriple().isOSAIX()) + addPass(createPPCPrepareIFuncsOnAIXPass()); + TargetPassConfig::addIRPasses(); } diff --git a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp index 2bf05e7518803..85a90992816e5 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp @@ -394,10 +394,10 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() { // (FIXME) a cost model could be used. However, introduced // swaps could potentially be CSEd, so this is not trivial. if (isVecReg(MI.getOperand(0).getReg()) && - isVecReg(MI.getOperand(2).getReg())) + isVecReg(MI.getOperand(1).getReg())) SwapVector[VecIdx].IsSwappable = 1; else if (isVecReg(MI.getOperand(0).getReg()) && - isScalarVecReg(MI.getOperand(2).getReg())) { + isScalarVecReg(MI.getOperand(1).getReg())) { SwapVector[VecIdx].IsSwappable = 1; SwapVector[VecIdx].SpecialHandling = SHValues::SH_COPYWIDEN; } @@ -559,13 +559,9 @@ unsigned PPCVSXSwapRemoval::lookThruCopyLike(unsigned SrcReg, if (!MI->isCopyLike()) return SrcReg; - unsigned CopySrcReg; - if (MI->isCopy()) - CopySrcReg = MI->getOperand(1).getReg(); - else { - assert(MI->isSubregToReg() && "bad opcode for lookThruCopyLike"); - CopySrcReg = MI->getOperand(2).getReg(); - } + assert((MI->isCopy() || MI->isSubregToReg()) && + "bad opcode for lookThruCopyLike"); + unsigned CopySrcReg = MI->getOperand(1).getReg(); if (!Register::isVirtualRegister(CopySrcReg)) { if (!isScalarVecReg(CopySrcReg)) diff --git a/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp b/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp index 2ec566ddb0b8e..741aa20eab479 100644 --- a/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp @@ -93,8 +93,6 @@ struct PPCVSXWACCCopy : public MachineFunctionPass { Register NewVReg = MRI.createVirtualRegister(SrcRC); BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg) - .addImm(1) // add 1, not 0, because there is no implicit clearing - // of the high bits. .add(SrcMO) .addImm(PPC::sub_64); diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 83a21bdb45408..ea5713159fe48 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -246,8 +246,12 @@ class RISCVAsmParser : public MCTargetAsmParser { void setFeatureBits(uint64_t Feature, StringRef FeatureString) { if (!(getSTI().hasFeature(Feature))) { MCSubtargetInfo &STI = copySTI(); - setAvailableFeatures( - ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); + STI.ToggleFeature(FeatureString); + + // Update the C and Zce implications. + RISCV::updateCZceFeatureImplications(STI); + + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } } @@ -3812,9 +3816,9 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst, } if (Opcode == RISCV::CM_MVSA01 || Opcode == RISCV::QC_CM_MVSA01) { - MCRegister Rd1 = Inst.getOperand(0).getReg(); - MCRegister Rd2 = Inst.getOperand(1).getReg(); - if (Rd1 == Rd2) { + MCRegister Rs1 = Inst.getOperand(0).getReg(); + MCRegister Rs2 = Inst.getOperand(1).getReg(); + if (Rs1 == Rs2) { SMLoc Loc = Operands[1]->getStartLoc(); return Error(Loc, "rs1 and rs2 must be different"); } diff --git a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp index eb41588286f4a..8b136cb7e79fd 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp @@ -114,7 +114,7 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler { }; if (Thunk) { - *Thunk = assignFunc; + *Thunk = std::move(assignFunc); return 1; } @@ -155,7 +155,7 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler { }; if (Thunk) { - *Thunk = assignFunc; + *Thunk = std::move(assignFunc); return 2; } diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 8769bb2238980..5d584e99ccc81 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -808,7 +808,8 @@ bool RISCVInstructionSelector::selectIntrinsicWithSideEffects( PseudoMI.cloneMemRefs(I); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + return true; } case Intrinsic::riscv_vloxei: case Intrinsic::riscv_vloxei_mask: @@ -872,7 +873,8 @@ bool RISCVInstructionSelector::selectIntrinsicWithSideEffects( PseudoMI.cloneMemRefs(I); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + return true; } case Intrinsic::riscv_vsm: case Intrinsic::riscv_vse: @@ -914,7 +916,8 @@ bool RISCVInstructionSelector::selectIntrinsicWithSideEffects( PseudoMI.cloneMemRefs(I); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + return true; } case Intrinsic::riscv_vsoxei: case Intrinsic::riscv_vsoxei_mask: @@ -964,7 +967,8 @@ bool RISCVInstructionSelector::selectIntrinsicWithSideEffects( PseudoMI.cloneMemRefs(I); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + return true; } } } @@ -1029,7 +1033,8 @@ bool RISCVInstructionSelector::selectIntrinsic(MachineInstr &I, .addImm(AVL) .addImm(VTypeI); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + return true; } } } @@ -1037,7 +1042,8 @@ bool RISCVInstructionSelector::selectIntrinsic(MachineInstr &I, auto PseudoMI = MIB.buildInstr(Opcode, {DstReg}, {VLOperand}).addImm(VTypeI); I.eraseFromParent(); - return constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*PseudoMI, TII, TRI, RBI); + return true; } } } @@ -1162,14 +1168,16 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { if (IsSigned && SrcSize == 32) { MI.setDesc(TII.get(RISCV::ADDIW)); MI.addOperand(MachineOperand::CreateImm(0)); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } // Use add.uw SrcReg, X0 (zext.w) for i32 with Zba. if (!IsSigned && SrcSize == 32 && STI.hasStdExtZba()) { MI.setDesc(TII.get(RISCV::ADD_UW)); MI.addOperand(MachineOperand::CreateReg(RISCV::X0, /*isDef=*/false)); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } // Use sext.h/zext.h for i16 with Zbb. @@ -1177,14 +1185,16 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { MI.setDesc(TII.get(IsSigned ? RISCV::SEXT_H : STI.isRV64() ? RISCV::ZEXT_H_RV64 : RISCV::ZEXT_H_RV32)); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } // Use pack(w) SrcReg, X0 for i16 zext with Zbkb. if (!IsSigned && SrcSize == 16 && STI.hasStdExtZbkb()) { MI.setDesc(TII.get(STI.is64Bit() ? RISCV::PACKW : RISCV::PACK)); MI.addOperand(MachineOperand::CreateReg(RISCV::X0, /*isDef=*/false)); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } // Fall back to shift pair. @@ -1219,8 +1229,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { : Size == 32 ? RISCV::FMV_W_X : RISCV::FMV_H_X; auto FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg}); - if (!FMV.constrainAllUses(TII, TRI, RBI)) - return false; + FMV.constrainAllUses(TII, TRI, RBI); } else { // s64 on rv32 assert(Size == 64 && !Subtarget->is64Bit() && @@ -1231,8 +1240,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { MachineInstrBuilder FCVT = MIB.buildInstr(RISCV::FCVT_D_W, {DstReg}, {Register(RISCV::X0)}) .addImm(RISCVFPRndMode::RNE); - if (!FCVT.constrainAllUses(TII, TRI, RBI)) - return false; + FCVT.constrainAllUses(TII, TRI, RBI); MI.eraseFromParent(); return true; @@ -1249,8 +1257,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { return false; MachineInstrBuilder PairF64 = MIB.buildInstr( RISCV::BuildPairF64Pseudo, {DstReg}, {GPRRegLow, GPRRegHigh}); - if (!PairF64.constrainAllUses(TII, TRI, RBI)) - return false; + PairF64.constrainAllUses(TII, TRI, RBI); } MI.eraseFromParent(); @@ -1276,12 +1283,14 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(CC), {}, {LHS, RHS}) .addMBB(MI.getOperand(1).getMBB()); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI); + return true; } case TargetOpcode::G_BRINDIRECT: MI.setDesc(TII.get(RISCV::PseudoBRIND)); MI.addOperand(MachineOperand::CreateImm(0)); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; case TargetOpcode::G_SELECT: return selectSelect(MI, MIB); case TargetOpcode::G_FCMP: @@ -1327,7 +1336,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { if (isStrongerThanMonotonic(Order)) { MI.setDesc(TII.get(selectZalasrLoadStoreOp(Opc, MemSize))); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } const unsigned NewOpc = selectRegImmLoadStoreOp(MI.getOpcode(), MemSize); @@ -1350,7 +1360,8 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { Fn(NewInst); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI); + constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI); + return true; } case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: return selectIntrinsicWithSideEffects(MI, MIB); @@ -1380,12 +1391,10 @@ bool RISCVInstructionSelector::selectUnmergeValues( return false; MachineInstr *ExtractLo = MIB.buildInstr(RISCV::FMV_X_W_FPR64, {Lo}, {Src}); - if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI); MachineInstr *ExtractHi = MIB.buildInstr(RISCV::FMVH_X_D, {Hi}, {Src}); - if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI); MI.eraseFromParent(); return true; @@ -1629,8 +1638,7 @@ bool RISCVInstructionSelector::materializeImm(Register DstReg, int64_t Imm, break; } - if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); SrcReg = TmpReg; } @@ -1661,7 +1669,8 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI, // pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym)) // %pcrel_lo(auipc)). MI.setDesc(TII.get(RISCV::PseudoLLA)); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } // Use PC-relative addressing to access the GOT for this symbol, then @@ -1679,8 +1688,7 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI, .addDisp(DispMO, 0) .addMemOperand(MemOp); - if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); MI.eraseFromParent(); return true; @@ -1700,14 +1708,12 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI, MachineInstr *AddrHi = MIB.buildInstr(RISCV::LUI, {AddrHiDest}, {}) .addDisp(DispMO, 0, RISCVII::MO_HI); - if (!constrainSelectedInstRegOperands(*AddrHi, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*AddrHi, TII, TRI, RBI); auto Result = MIB.buildInstr(RISCV::ADDI, {DefReg}, {AddrHiDest}) .addDisp(DispMO, 0, RISCVII::MO_LO); - if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); MI.eraseFromParent(); return true; @@ -1733,8 +1739,7 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI, .addDisp(DispMO, 0) .addMemOperand(MemOp); - if (!constrainSelectedInstRegOperands(*Result, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); MI.eraseFromParent(); return true; @@ -1744,7 +1749,8 @@ bool RISCVInstructionSelector::selectAddr(MachineInstr &MI, // within the address space. This generates the pattern (PseudoLLA sym), // which expands to (addi (auipc %pcrel_hi(sym)) %pcrel_lo(auipc)). MI.setDesc(TII.get(RISCV::PseudoLLA)); - return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + return true; } return false; @@ -1775,7 +1781,8 @@ bool RISCVInstructionSelector::selectSelect(MachineInstr &MI, .addReg(SelectMI.getTrueReg()) .addReg(SelectMI.getFalseReg()); MI.eraseFromParent(); - return constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); + constrainSelectedInstRegOperands(*Result, TII, TRI, RBI); + return true; } // Convert an FCMP predicate to one of the supported F or D instructions. @@ -1850,51 +1857,43 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI, if (NeedInvert) TmpReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); auto Cmp = MIB.buildInstr(getFCmpOpcode(Pred, Size), {TmpReg}, {LHS, RHS}); - if (!Cmp.constrainAllUses(TII, TRI, RBI)) - return false; + Cmp.constrainAllUses(TII, TRI, RBI); } else if (Pred == CmpInst::FCMP_ONE || Pred == CmpInst::FCMP_UEQ) { // fcmp one LHS, RHS => (OR (FLT LHS, RHS), (FLT RHS, LHS)) NeedInvert = Pred == CmpInst::FCMP_UEQ; auto Cmp1 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OLT, Size), {&RISCV::GPRRegClass}, {LHS, RHS}); - if (!Cmp1.constrainAllUses(TII, TRI, RBI)) - return false; + Cmp1.constrainAllUses(TII, TRI, RBI); auto Cmp2 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OLT, Size), {&RISCV::GPRRegClass}, {RHS, LHS}); - if (!Cmp2.constrainAllUses(TII, TRI, RBI)) - return false; + Cmp2.constrainAllUses(TII, TRI, RBI); if (NeedInvert) TmpReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); auto Or = MIB.buildInstr(RISCV::OR, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)}); - if (!Or.constrainAllUses(TII, TRI, RBI)) - return false; + Or.constrainAllUses(TII, TRI, RBI); } else if (Pred == CmpInst::FCMP_ORD || Pred == CmpInst::FCMP_UNO) { // fcmp ord LHS, RHS => (AND (FEQ LHS, LHS), (FEQ RHS, RHS)) // FIXME: If LHS and RHS are the same we can use a single FEQ. NeedInvert = Pred == CmpInst::FCMP_UNO; auto Cmp1 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OEQ, Size), {&RISCV::GPRRegClass}, {LHS, LHS}); - if (!Cmp1.constrainAllUses(TII, TRI, RBI)) - return false; + Cmp1.constrainAllUses(TII, TRI, RBI); auto Cmp2 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OEQ, Size), {&RISCV::GPRRegClass}, {RHS, RHS}); - if (!Cmp2.constrainAllUses(TII, TRI, RBI)) - return false; + Cmp2.constrainAllUses(TII, TRI, RBI); if (NeedInvert) TmpReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); auto And = MIB.buildInstr(RISCV::AND, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)}); - if (!And.constrainAllUses(TII, TRI, RBI)) - return false; + And.constrainAllUses(TII, TRI, RBI); } else llvm_unreachable("Unhandled predicate"); // Emit an XORI to invert the result if needed. if (NeedInvert) { auto Xor = MIB.buildInstr(RISCV::XORI, {DstReg}, {TmpReg}).addImm(1); - if (!Xor.constrainAllUses(TII, TRI, RBI)) - return false; + Xor.constrainAllUses(TII, TRI, RBI); } MI.eraseFromParent(); diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index 6d278106646a1..1270cdd8189d9 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -27,7 +27,7 @@ struct VXMemOpInfo { unsigned Log2IdxEEW : 3; unsigned IsOrdered : 1; unsigned IsStore : 1; - unsigned NF : 4; + unsigned NFields : 4; unsigned BaseInstr; }; @@ -269,7 +269,7 @@ unsigned RISCVInstrumentManager::getSchedClassID( // the DataEEW and DataEMUL are equal to SEW and LMUL, respectively. unsigned IndexEMUL = ((1 << VXMO->Log2IdxEEW) * LMUL) / SEW; - if (!VXMO->NF) { + if (!VXMO->NFields) { // Indexed Load / Store. if (VXMO->IsStore) { if (const auto *VXP = RISCV::getVSXPseudo( @@ -285,14 +285,14 @@ unsigned RISCVInstrumentManager::getSchedClassID( } else { // Segmented Indexed Load / Store. if (VXMO->IsStore) { - if (const auto *VXP = - RISCV::getVSXSEGPseudo(VXMO->NF, /*Masked=*/0, VXMO->IsOrdered, - VXMO->Log2IdxEEW, LMUL, IndexEMUL)) + if (const auto *VXP = RISCV::getVSXSEGPseudo( + VXMO->NFields, /*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, + LMUL, IndexEMUL)) VPOpcode = VXP->Pseudo; } else { - if (const auto *VXP = - RISCV::getVLXSEGPseudo(VXMO->NF, /*Masked=*/0, VXMO->IsOrdered, - VXMO->Log2IdxEEW, LMUL, IndexEMUL)) + if (const auto *VXP = RISCV::getVLXSEGPseudo( + VXMO->NFields, /*Masked=*/0, VXMO->IsOrdered, VXMO->Log2IdxEEW, + LMUL, IndexEMUL)) VPOpcode = VXP->Pseudo; } } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp index eb51dba20c8a4..38d154d90d7e0 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -83,8 +83,66 @@ createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, return MOFI; } -static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, - StringRef CPU, StringRef FS) { +void RISCV::updateCZceFeatureImplications(MCSubtargetInfo &STI) { + // Add Zcd if C and D are enabled. + if (STI.hasFeature(RISCV::FeatureStdExtC) && + STI.hasFeature(RISCV::FeatureStdExtD) && + !STI.hasFeature(RISCV::FeatureStdExtZcd)) + STI.ToggleFeature(RISCV::FeatureStdExtZcd); + + // Add Zcf if F and C or Zce are enabled on RV32. + if (!STI.hasFeature(RISCV::FeatureStdExtZcf) && + !STI.hasFeature(RISCV::Feature64Bit) && + STI.hasFeature(RISCV::FeatureStdExtF) && + (STI.hasFeature(RISCV::FeatureStdExtC) || + STI.hasFeature(RISCV::FeatureStdExtZce))) + STI.ToggleFeature(RISCV::FeatureStdExtZcf); + + // Add C if Zca is enabled and the conditions are met. + // This follows the RISC-V spec rules for MISA.C and matches GCC behavior + // (PR119122). The rule is: + // For RV32: + // - No F and no D: Zca alone implies C + // - F but no D: Zca + Zcf implies C + // - F and D: Zca + Zcf + Zcd implies C + // For RV64: + // - No D: Zca alone implies C + // - D: Zca + Zcd implies C + if (!STI.hasFeature(RISCV::FeatureStdExtC) && + STI.hasFeature(RISCV::FeatureStdExtZca)) { + bool ShouldAddC = false; + if (!STI.hasFeature(RISCV::Feature64Bit)) + ShouldAddC = (!STI.hasFeature(RISCV::FeatureStdExtD) || + STI.hasFeature(RISCV::FeatureStdExtZcd)) && + (!STI.hasFeature(RISCV::FeatureStdExtF) || + STI.hasFeature(RISCV::FeatureStdExtZcf)); + else + ShouldAddC = (!STI.hasFeature(RISCV::FeatureStdExtD) || + STI.hasFeature(RISCV::FeatureStdExtZcd)); + if (ShouldAddC) + STI.ToggleFeature(RISCV::FeatureStdExtC); + } + + // Add Zce if Zca+Zcb+Zcmp+Zcmt are enabled and the conditions are met. + // For RV32: + // - No F and no D: Zca+Zcb+Zcmp+Zcmt alone implies Zce + // - F: Zca+Zcb+Zcmp+Zcmt + Zcf implies Zce + // For RV64: + // - Zca+Zcb+Zcmp+Zcmt alone implies Zce + if (!STI.hasFeature(RISCV::FeatureStdExtZce) && + STI.hasFeature(RISCV::FeatureStdExtZca) && + STI.hasFeature(RISCV::FeatureStdExtZcb) && + STI.hasFeature(RISCV::FeatureStdExtZcmp) && + STI.hasFeature(RISCV::FeatureStdExtZcmt)) { + if (STI.hasFeature(RISCV::Feature64Bit) || + !STI.hasFeature(RISCV::FeatureStdExtF) || + STI.hasFeature(RISCV::FeatureStdExtZcf)) + STI.ToggleFeature(RISCV::FeatureStdExtZce); + } +} + +static MCSubtargetInfo * +createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { if (CPU.empty() || CPU == "generic") CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; @@ -103,6 +161,8 @@ static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, X->setFeatureBits(Features); } + RISCV::updateCZceFeatureImplications(*X); + return X; } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h index 7ee6a20393e66..d1733886637f8 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h @@ -39,6 +39,11 @@ std::unique_ptr createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit); std::unique_ptr createRISCVMachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype); + +namespace RISCV { +void updateCZceFeatureImplications(MCSubtargetInfo &STI); +} + } // namespace llvm // Defines symbolic names for RISC-V registers. diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 70bf802cb4625..7a4d8a6fd55d5 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -61,6 +61,7 @@ include "RISCVSchedSiFiveP500.td" include "RISCVSchedSiFiveP600.td" include "RISCVSchedSiFiveP800.td" include "RISCVSchedSpacemitX60.td" +include "RISCVSchedSpacemitX100.td" include "RISCVSchedSyntacoreSCR1.td" include "RISCVSchedSyntacoreSCR345.td" include "RISCVSchedSyntacoreSCR7.td" diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d681bb78014af..92720be8a03dc 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -390,7 +390,7 @@ def FeatureStdExtZca // Note: Zca conditionally implies C (see RISCVISAInfo::updateImplication). def HasStdExtZca : Predicate<"Subtarget->hasStdExtZca()">, - AssemblerPredicate<(any_of FeatureStdExtZca), + AssemblerPredicate<(all_of FeatureStdExtZca), "'C' (Compressed Instructions) or " "'Zca' (part of the C extension, excluding " "compressed floating point loads/stores)">; @@ -398,9 +398,6 @@ def HasStdExtZca def FeatureStdExtC : RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>, RISCVExtensionBitmask<0, 2>; -def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, - AssemblerPredicate<(all_of FeatureStdExtC), - "'C' (Compressed Instructions)">; def FeatureStdExtZcb : RISCVExtension<1, 0, "Compressed basic bit manipulation instructions", @@ -410,24 +407,30 @@ def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, AssemblerPredicate<(all_of FeatureStdExtZcb), "'Zcb' (Compressed basic bit manipulation instructions)">; +def FeatureStdExtZcf + : RISCVExtension<1, 0, + "Compressed Single-Precision Floating-Point Instructions", + [FeatureStdExtF, FeatureStdExtZca]>, + RISCVExtensionBitmask<1, 5>; + +def HasStdExtZcf + : Predicate<"Subtarget->hasStdExtZcf()">, + AssemblerPredicate<(all_of FeatureStdExtZcf), + "'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or " + "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; + def FeatureStdExtZcd : RISCVExtension<1, 0, "Compressed Double-Precision Floating-Point Instructions", [FeatureStdExtD, FeatureStdExtZca]>, RISCVExtensionBitmask<1, 4>; -def HasStdExtCOrZcd - : Predicate<"Subtarget->hasStdExtCOrZcd()">, - AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd), - "'C' (Compressed Instructions) or " +def HasStdExtZcd + : Predicate<"Subtarget->hasStdExtZcd()">, + AssemblerPredicate<(all_of FeatureStdExtZcd), + "'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or " "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; -def FeatureStdExtZcf - : RISCVExtension<1, 0, - "Compressed Single-Precision Floating-Point Instructions", - [FeatureStdExtF, FeatureStdExtZca]>, - RISCVExtensionBitmask<1, 5>; - def FeatureStdExtZclsd : RISCVExtension<1, 0, "Compressed Load/Store Pair Instructions", @@ -460,14 +463,6 @@ def FeatureStdExtZce [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>; -def HasStdExtCOrZcfOrZce - : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() ||" - "Subtarget->hasStdExtZce()">, - AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf, - FeatureStdExtZce), - "'C' (Compressed Instructions) or " - "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; - def FeatureStdExtZcmop : RISCVExtension<1, 0, "Compressed May-Be-Operations", [FeatureStdExtZca]>, @@ -691,6 +686,12 @@ def FeatureStdExtV [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, RISCVExtensionBitmask<0, 21>; +def FeatureStdExtZvabd + : RISCVExperimentalExtension<0, 7, "Vector Absolute Difference">; +def HasStdExtZvabd : Predicate<"Subtarget->hasStdExtZvabd()">, + AssemblerPredicate<(all_of FeatureStdExtZvabd), + "'Zvabd' (Vector Absolute Difference)">; + def FeatureStdExtZvfbfa : RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support", [FeatureStdExtZve32f, FeatureStdExtZfbfmin]>; @@ -1749,6 +1750,21 @@ def HasXAIFET : Predicate<"Subtarget->hasXAIFET()">, // LLVM specific features and extensions //===----------------------------------------------------------------------===// +class RISCVTuneFeature implied_features = []> + : SubtargetFeature { + let Implies = implied_features; + + string PositiveDirectiveName = pos_directive; + string NegativeDirectiveName = neg_directive; +} +class RISCVSimpleTuneFeature implied_features = []> + : RISCVTuneFeature; + // Feature32Bit exists to mark CPUs that support RV32 to distinguish them from // tuning CPU names. def Feature32Bit @@ -1839,32 +1855,54 @@ def TuneNLogNVRGather : SubtargetFeature<"log-vrgather", "RISCVVRGatherCostModel", "NLog2N", "Has vrgather.vv with LMUL*log2(LMUL) latency">; -def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler", - "UsePostRAScheduler", "true", "Schedule again after register allocation">; - -def TuneDisableMISchedLoadClustering : SubtargetFeature<"disable-misched-load-clustering", - "EnableMISchedLoadClustering", "false", "Disable load clustering in the machine scheduler">; - -def TuneDisableMISchedStoreClustering : SubtargetFeature<"disable-misched-store-clustering", - "EnableMISchedStoreClustering", "false", "Disable store clustering in the machine scheduler">; - -def TuneDisablePostMISchedLoadClustering : SubtargetFeature<"disable-postmisched-load-clustering", - "EnablePostMISchedLoadClustering", "false", "Disable PostRA load clustering in the machine scheduler">; - -def TuneDisablePostMISchedStoreClustering : SubtargetFeature<"disable-postmisched-store-clustering", - "EnablePostMISchedStoreClustering", "false", "Disable PostRA store clustering in the machine scheduler">; +def TunePostRAScheduler + : RISCVSimpleTuneFeature<"use-postra-scheduler", "UsePostRAScheduler", + "true", + "Schedule again after register allocation">; + +def TuneDisableMISchedLoadClustering + : RISCVTuneFeature< + "disable-misched-load-clustering", "disable-misched-load-clustering", + "enable-misched-load-clustering", "EnableMISchedLoadClustering", + "false", "Disable load clustering in the machine scheduler">; + +def TuneDisableMISchedStoreClustering + : RISCVTuneFeature<"disable-misched-store-clustering", + "disable-misched-store-clustering", + "enable-misched-store-clustering", + "EnableMISchedStoreClustering", "false", + "Disable store clustering in the machine scheduler">; + +def TuneDisablePostMISchedLoadClustering + : RISCVTuneFeature< + "disable-postmisched-load-clustering", + "disable-postmisched-load-clustering", + "enable-postmisched-load-clustering", + "EnablePostMISchedLoadClustering", "false", + "Disable PostRA load clustering in the machine scheduler">; + +def TuneDisablePostMISchedStoreClustering + : RISCVTuneFeature< + "disable-postmisched-store-clustering", + "disable-postmisched-store-clustering", + "enable-postmisched-store-clustering", + "EnablePostMISchedStoreClustering", "false", + "Disable PostRA store clustering in the machine scheduler">; def TuneDisableLatencySchedHeuristic - : SubtargetFeature<"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", - "Disable latency scheduling heuristic">; + : RISCVTuneFeature< + "disable-latency-sched-heuristic", "disable-latency-sched-heuristic", + "enable-latency-sched-heuristic", "DisableLatencySchedHeuristic", + "true", "Disable latency scheduling heuristic">; def TuneEnableVsetvliSchedHeuristic : SubtargetFeature<"enable-vsetvli-sched-heuristic", "EnableVsetvliSchedHeuristic", "true", "Enable vsetvli-based scheduling heuristic">; def TunePredictableSelectIsExpensive - : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true", - "Prefer likely predicted branches over selects">; + : RISCVSimpleTuneFeature<"predictable-select-expensive", + "PredictableSelectIsExpensive", "true", + "Prefer likely predicted branches over selects">; def TuneOptimizedZeroStrideLoad : SubtargetFeature<"optimized-zero-stride-load", "HasOptimizedZeroStrideLoad", @@ -1883,9 +1921,10 @@ foreach nf = {2-8} in "implemented as a wide memory op and shuffle">; def TuneVLDependentLatency - : SubtargetFeature<"vl-dependent-latency", "HasVLDependentLatency", "true", - "Latency of vector instructions is dependent on the " - "dynamic value of vl">; + : RISCVSimpleTuneFeature< + "vl-dependent-latency", "HasVLDependentLatency", "true", + "Latency of vector instructions is dependent on the " + "dynamic value of vl">; def Experimental : SubtargetFeature<"experimental", "HasExperimental", @@ -1899,7 +1938,8 @@ def TuneDLenFactor2 "Vector unit DLEN(data path width) is half of VLEN">; def TuneNoDefaultUnroll - : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false", + : RISCVTuneFeature<"no-default-unroll", "no-default-unroll", + "enable-default-unroll", "EnableDefaultUnroll", "false", "Disable default unroll preference.">; // Many Microarchitectures are able to fuse a branch over a single instruction @@ -1924,59 +1964,68 @@ def TuneNoDefaultUnroll // the vendor-specific instructions should only be enabled for vendor // cores. def TuneShortForwardBranchIALU - : SubtargetFeature<"short-forward-branch-ialu", "HasShortForwardBranchIALU", - "true", "Enable short forward branch optimization for RVI base instructions">; + : RISCVSimpleTuneFeature< + "short-forward-branch-ialu", "HasShortForwardBranchIALU", "true", + "Enable short forward branch optimization for RVI base instructions">; def HasShortForwardBranchIALU : Predicate<"Subtarget->hasShortForwardBranchIALU()">; def NoShortForwardBranch : Predicate<"!Subtarget->hasShortForwardBranchIALU()">; def TuneShortForwardBranchIMinMax - : SubtargetFeature<"short-forward-branch-iminmax", "HasShortForwardBranchIMinMax", - "true", "Enable short forward branch optimization for MIN,MAX instructions in Zbb", - [TuneShortForwardBranchIALU]>; + : RISCVSimpleTuneFeature<"short-forward-branch-iminmax", + "HasShortForwardBranchIMinMax", "true", + "Enable short forward branch optimization for " + "MIN,MAX instructions in Zbb", + [TuneShortForwardBranchIALU]>; def HasShortForwardBranchIMinMax : Predicate<"Subtarget->hasShortForwardBranchIMinMax()">; def TuneShortForwardBranchIMul - : SubtargetFeature<"short-forward-branch-imul", "HasShortForwardBranchIMul", - "true", "Enable short forward branch optimization for MUL instruction", - [TuneShortForwardBranchIALU]>; + : RISCVSimpleTuneFeature< + "short-forward-branch-imul", "HasShortForwardBranchIMul", "true", + "Enable short forward branch optimization for MUL instruction", + [TuneShortForwardBranchIALU]>; def HasShortForwardBranchIMul : Predicate<"Subtarget->hasShortForwardBranchIMul()">; def TuneShortForwardBranchILoad - : SubtargetFeature<"short-forward-branch-iload", "HasShortForwardBranchILoad", - "true", "Enable short forward branch optimization for load instructions", - [TuneShortForwardBranchIALU]>; + : RISCVSimpleTuneFeature< + "short-forward-branch-iload", "HasShortForwardBranchILoad", "true", + "Enable short forward branch optimization for load instructions", + [TuneShortForwardBranchIALU]>; def HasShortForwardBranchILoad : Predicate<"Subtarget->hasShortForwardBranchILoad()">; // Some subtargets require a S2V transfer buffer to move scalars into vectors. // FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure. def TuneNoSinkSplatOperands - : SubtargetFeature<"no-sink-splat-operands", "SinkSplatOperands", - "false", "Disable sink splat operands to enable .vx, .vf," - ".wx, and .wf instructions">; + : RISCVTuneFeature<"no-sink-splat-operands", "no-sink-splat-operands", + "sink-splat-operands", "SinkSplatOperands", "false", + "Disable sink splat operands to enable .vx, .vf,.wx, " + "and .wf instructions">; def TunePreferWInst - : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true", - "Prefer instructions with W suffix">; + : RISCVSimpleTuneFeature<"prefer-w-inst", "PreferWInst", "true", + "Prefer instructions with W suffix">; def TuneConditionalCompressedMoveFusion - : SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion", - "true", "Enable branch+c.mv fusion">; + : RISCVSimpleTuneFeature<"conditional-cmv-fusion", + "HasConditionalCompressedMoveFusion", "true", + "Enable branch+c.mv fusion">; def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()">; def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion()">; def TuneHasSingleElementVecFP64 - : SubtargetFeature<"single-element-vec-fp64", "HasSingleElementVectorFP64", "true", - "Certain vector FP64 operations produce a single result " - "element per cycle">; + : RISCVTuneFeature<"single-element-vec-fp64", + "single-element-vec-fp64", "full-vec-fp64", + "HasSingleElementVectorFP64", "true", + "Certain vector FP64 operations produce a single result " + "element per cycle">; -def TuneVXRMPipelineFlush : SubtargetFeature<"vxrm-pipeline-flush", "HasVXRMPipelineFlush", - "true", "VXRM writes causes pipeline flush">; +def TuneVXRMPipelineFlush + : RISCVSimpleTuneFeature<"vxrm-pipeline-flush", "HasVXRMPipelineFlush", + "true", "VXRM writes causes pipeline flush">; def TunePreferVsetvliOverReadVLENB - : SubtargetFeature<"prefer-vsetvli-over-read-vlenb", - "PreferVsetvliOverReadVLENB", - "true", - "Prefer vsetvli over read vlenb CSR to calculate VLEN">; + : RISCVSimpleTuneFeature< + "prefer-vsetvli-over-read-vlenb", "PreferVsetvliOverReadVLENB", + "true", "Prefer vsetvli over read vlenb CSR to calculate VLEN">; //===----------------------------------------------------------------------===// // CPU Families (alphabetized by vendor). diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 8246623e8e5aa..24b83026bf824 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -2148,13 +2148,17 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters( } } else if (const char *SpillLibCall = getSpillLibCallName(*MF, CSI)) { // Add spill libcall via non-callee-saved register t0. - BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5) - .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL) - .setMIFlag(MachineInstr::FrameSetup); + MachineInstrBuilder NewMI = + BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5) + .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL) + .setMIFlag(MachineInstr::FrameSetup); - // Add registers spilled in libcall as liveins. - for (auto &CS : CSI) + for (auto &CS : CSI) { + // Add registers spilled as implicit used. + NewMI.addUse(CS.getReg(), RegState::Implicit); + // Add registers spilled in libcall as liveins. MBB.addLiveIn(CS.getReg()); + } } // Manually spill values not spilled by libcall & Push/Pop. @@ -2291,21 +2295,22 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters( for (unsigned i = 0; i < RVFI->getRVPushRegs(); i++) PopBuilder.addDef(FixedCSRFIMap[i], RegState::ImplicitDefine); } - } else { - const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI); - if (RestoreLibCall) { - // Add restore libcall via tail call. - MachineBasicBlock::iterator NewMI = - BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL)) - .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL) - .setMIFlag(MachineInstr::FrameDestroy); + } else if (const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI)) { + // Add restore libcall via tail call. + MachineInstrBuilder NewMI = + BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL)) + .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL) + .setMIFlag(MachineInstr::FrameDestroy); + + // Add registers restored as implicit defined. + for (auto &CS : CSI) + NewMI.addDef(CS.getReg(), RegState::ImplicitDefine); - // Remove trailing returns, since the terminator is now a tail call to the - // restore function. - if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) { - NewMI->copyImplicitOps(*MF, *MI); - MI->eraseFromParent(); - } + // Remove trailing returns, since the terminator is now a tail call to the + // restore function. + if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) { + NewMI.getInstr()->copyImplicitOps(*MF, *MI); + MI->eraseFromParent(); } } return true; diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index b51ed9cddbeb2..04258cd804888 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -1757,6 +1757,40 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { ReplaceNode(Node, MULHU); return; } + case ISD::SMUL_LOHI: + case ISD::UMUL_LOHI: + case RISCVISD::WMULSU: { + // Custom select (S/U)MUL_LOHI to WMUL(U) for RV32P. + assert(Subtarget->hasStdExtP() && !Subtarget->is64Bit() && VT == MVT::i32 && + "Unexpected opcode"); + + unsigned Opc; + switch (Node->getOpcode()) { + default: + llvm_unreachable("Unexpected opcode"); + case ISD::SMUL_LOHI: + Opc = RISCV::WMUL; + break; + case ISD::UMUL_LOHI: + Opc = RISCV::WMULU; + break; + case RISCVISD::WMULSU: + Opc = RISCV::WMULSU; + break; + } + + SDNode *WMUL = CurDAG->getMachineNode( + Opc, DL, MVT::Untyped, Node->getOperand(0), Node->getOperand(1)); + + SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL, + MVT::i32, SDValue(WMUL, 0)); + SDValue Hi = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_odd, DL, + MVT::i32, SDValue(WMUL, 0)); + ReplaceUses(SDValue(Node, 0), Lo); + ReplaceUses(SDValue(Node, 1), Hi); + CurDAG->RemoveDeadNode(Node); + return; + } case ISD::LOAD: { if (tryIndexedLoad(Node)) return; @@ -1876,38 +1910,100 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { CurDAG->RemoveDeadNode(Node); return; } - case RISCVISD::PPACK_DH: { - assert(Subtarget->enablePExtSIMDCodeGen() && Subtarget->isRV32()); + case RISCVISD::WMACCU: + case RISCVISD::WMACC: { + assert(!Subtarget->is64Bit() && Subtarget->hasStdExtP() && + "Unexpected opcode"); + + // WMACCU/WMACC has 4 operands: (m1, m2, addlo, addhi) -> (lo, hi) + SDValue M1 = Node->getOperand(0); + SDValue M2 = Node->getOperand(1); + SDValue AddLo = Node->getOperand(2); + SDValue AddHi = Node->getOperand(3); + + // Build the register pair for the accumulator input + SDValue AccOps[] = { + CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32), + AddLo, CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32), + AddHi, CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)}; + SDValue Acc = SDValue(CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, + MVT::Untyped, AccOps), + 0); + + unsigned Opc = + Node->getOpcode() == RISCVISD::WMACCU ? RISCV::WMACCU : RISCV::WMACC; + + // Instruction format: WMACCU rd, rs1, rs2 (rd is accumulator, comes first) + MachineSDNode *New = + CurDAG->getMachineNode(Opc, DL, MVT::Untyped, Acc, M1, M2); + + SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL, + MVT::i32, SDValue(New, 0)); + SDValue Hi = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_odd, DL, + MVT::i32, SDValue(New, 0)); - SDValue Val0 = Node->getOperand(0); - SDValue Val1 = Node->getOperand(1); - SDValue Val2 = Node->getOperand(2); - SDValue Val3 = Node->getOperand(3); + ReplaceUses(SDValue(Node, 0), Lo); + ReplaceUses(SDValue(Node, 1), Hi); + CurDAG->RemoveDeadNode(Node); + return; + } + case RISCVISD::ADDD: + case RISCVISD::SUBD: + case RISCVISD::PPAIRE_DB: { + assert(!Subtarget->is64Bit() && "Unexpected opcode"); + assert((Node->getOpcode() != RISCVISD::PPAIRE_DB || + Subtarget->enablePExtSIMDCodeGen()) && + "Unexpected opcode"); + + SDValue Op0Lo = Node->getOperand(0); + SDValue Op0Hi = Node->getOperand(1); + + SDValue Op0; + if (isNullConstant(Op0Lo) && isNullConstant(Op0Hi)) { + Op0 = CurDAG->getRegister(RISCV::X0_Pair, MVT::Untyped); + } else { + SDValue Ops[] = { + CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32), + Op0Lo, CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32), + Op0Hi, CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)}; + Op0 = SDValue(CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, + MVT::Untyped, Ops), + 0); + } + SDValue Op1Lo = Node->getOperand(2); + SDValue Op1Hi = Node->getOperand(3); SDValue Ops[] = { - CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32), Val0, - CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32), Val2, - CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)}; - SDValue RegPair0 = - SDValue(CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, - MVT::Untyped, Ops), - 0); - SDValue Ops1[] = { - CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32), Val1, - CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32), Val3, - CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)}; - SDValue RegPair1 = - SDValue(CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, - MVT::Untyped, Ops1), - 0); + CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32), + Op1Lo, CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32), + Op1Hi, CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)}; - MachineSDNode *PackDH = CurDAG->getMachineNode( - RISCV::PPAIRE_DB, DL, MVT::Untyped, {RegPair0, RegPair1}); + SDValue Op1 = SDValue(CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, + MVT::Untyped, Ops), + 0); + + unsigned Opc; + switch (Node->getOpcode()) { + default: + llvm_unreachable("Unexpected opcode"); + case RISCVISD::ADDD: + Opc = RISCV::ADDD; + break; + case RISCVISD::SUBD: + Opc = RISCV::SUBD; + break; + case RISCVISD::PPAIRE_DB: + Opc = RISCV::PPAIRE_DB; + break; + } + + MachineSDNode *New = + CurDAG->getMachineNode(Opc, DL, MVT::Untyped, Op0, Op1); SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL, - MVT::i32, SDValue(PackDH, 0)); + MVT::i32, SDValue(New, 0)); SDValue Hi = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_odd, DL, - MVT::i32, SDValue(PackDH, 0)); + MVT::i32, SDValue(New, 0)); ReplaceUses(SDValue(Node, 0), Lo); ReplaceUses(SDValue(Node, 1), Hi); CurDAG->RemoveDeadNode(Node); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 90809828e9653..9b88bc5c39ce4 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -358,6 +358,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, MVT::i32, Custom); setOperationAction({ISD::UADDO, ISD::USUBO}, MVT::i32, Custom); setOperationAction({ISD::SADDO, ISD::SSUBO}, MVT::i32, Custom); + } else { + // Custom legalize i64 ADD/SUB for RV32+P. + if (Subtarget.hasStdExtP()) + setOperationAction({ISD::ADD, ISD::SUB}, MVT::i64, Custom); } if (!Subtarget.hasStdExtZmmul()) { setOperationAction({ISD::MUL, ISD::MULHS, ISD::MULHU}, XLenVT, Expand); @@ -376,9 +380,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, {MVT::i8, MVT::i16, MVT::i32}, Custom); } - setOperationAction( - {ISD::SDIVREM, ISD::UDIVREM, ISD::SMUL_LOHI, ISD::UMUL_LOHI}, XLenVT, - Expand); + setOperationAction({ISD::SDIVREM, ISD::UDIVREM}, XLenVT, Expand); + + // On RV32, the P extension has a WMUL(U) instruction we can use for + // (S/U)MUL_LOHI. + // FIXME: Does P imply Zmmul? + if (!Subtarget.hasStdExtP() || !Subtarget.hasStdExtZmmul() || + Subtarget.is64Bit()) + setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, XLenVT, Expand); setOperationAction({ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, XLenVT, Custom); @@ -550,8 +559,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, {MVT::v2i16, MVT::v4i8}, Custom); } else { VTs = RV32VTs; - setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8, Custom); } + // By default everything must be expanded. + for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) + setOperationAction(Op, VTs, Expand); + setOperationAction({ISD::LOAD, ISD::STORE}, VTs, Legal); + setOperationAction({ISD::ADD, ISD::SUB}, VTs, Legal); + setOperationAction({ISD::AND, ISD::OR, ISD::XOR}, VTs, Legal); + setOperationAction({ISD::MUL, ISD::MULHS, ISD::MULHU}, VTs, Legal); setOperationAction(ISD::UADDSAT, VTs, Legal); setOperationAction(ISD::SADDSAT, VTs, Legal); setOperationAction(ISD::USUBSAT, VTs, Legal); @@ -560,20 +575,25 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::AVGFLOORS, ISD::AVGFLOORU}, VTs, Legal); setOperationAction({ISD::ABDS, ISD::ABDU}, VTs, Legal); setOperationAction(ISD::SPLAT_VECTOR, VTs, Legal); + setOperationAction(ISD::BUILD_VECTOR, VTs, Legal); + setOperationAction(ISD::SCALAR_TO_VECTOR, VTs, Legal); setOperationAction({ISD::SHL, ISD::SRL, ISD::SRA}, VTs, Custom); setOperationAction(ISD::BITCAST, VTs, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, VTs, Custom); - setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, - ISD::SDIVREM, ISD::UDIVREM}, - VTs, Expand); + setOperationAction({ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}, VTs, + Custom); setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, VTs, Legal); setOperationAction(ISD::SELECT, VTs, Custom); setOperationAction(ISD::SELECT_CC, VTs, Expand); + setOperationAction(ISD::VSELECT, VTs, Legal); setOperationAction(ISD::SETCC, VTs, Legal); setCondCodeAction({ISD::SETNE, ISD::SETGT, ISD::SETGE, ISD::SETUGT, ISD::SETUGE, ISD::SETULE, ISD::SETLE}, VTs, Expand); + + if (!Subtarget.is64Bit()) + setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8, Custom); + // P extension vector comparisons produce all 1s for true, all 0s for false setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); } @@ -985,7 +1005,16 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, Legal); - setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); + if (Subtarget.hasStdExtZvabd()) { + setOperationAction(ISD::ABS, VT, Legal); + // Only SEW=8/16 are supported in Zvabd. + if (VT.getVectorElementType() == MVT::i8 || + VT.getVectorElementType() == MVT::i16) + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Legal); + else + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); + } else + setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Custom); // Custom-lower extensions and truncations from/to mask types. setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, @@ -1953,10 +1982,10 @@ bool RISCVTargetLowering::shouldExpandCttzElements(EVT VT) const { VT.getVectorElementType() != MVT::i1 || !isTypeLegal(VT); } -bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void RISCVTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; auto &DL = I.getDataLayout(); auto SetRVVLoadStoreInfo = [&](unsigned PtrOp, bool IsStore, @@ -1997,7 +2026,7 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.size = MemoryLocation::UnknownSize; Info.flags |= IsStore ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); }; if (I.hasMetadata(LLVMContext::MD_nontemporal)) @@ -2006,7 +2035,7 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.flags |= RISCVTargetLowering::getTargetMMOFlags(I); switch (Intrinsic) { default: - return false; + return; case Intrinsic::riscv_masked_atomicrmw_xchg: case Intrinsic::riscv_masked_atomicrmw_add: case Intrinsic::riscv_masked_atomicrmw_sub: @@ -2028,7 +2057,8 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(4); Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; case Intrinsic::riscv_seg2_load_mask: case Intrinsic::riscv_seg3_load_mask: case Intrinsic::riscv_seg4_load_mask: @@ -2043,8 +2073,9 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_sseg6_load_mask: case Intrinsic::riscv_sseg7_load_mask: case Intrinsic::riscv_sseg8_load_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 0, /*IsStore*/ false, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ 0, /*IsStore*/ false, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_seg2_store_mask: case Intrinsic::riscv_seg3_store_mask: case Intrinsic::riscv_seg4_store_mask: @@ -2053,9 +2084,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_seg7_store_mask: case Intrinsic::riscv_seg8_store_mask: // Operands are (vec, ..., vec, ptr, mask, vl) - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, - /*IsStore*/ true, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, + /*IsStore*/ true, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_sseg2_store_mask: case Intrinsic::riscv_sseg3_store_mask: case Intrinsic::riscv_sseg4_store_mask: @@ -2064,47 +2096,53 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_sseg7_store_mask: case Intrinsic::riscv_sseg8_store_mask: // Operands are (vec, ..., vec, ptr, offset, mask, vl) - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, - /*IsStore*/ true, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, + /*IsStore*/ true, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vlm: - return SetRVVLoadStoreInfo(/*PtrOp*/ 0, - /*IsStore*/ false, - /*IsUnitStrided*/ true, - /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ 0, + /*IsStore*/ false, + /*IsUnitStrided*/ true, + /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vle: case Intrinsic::riscv_vle_mask: case Intrinsic::riscv_vleff: case Intrinsic::riscv_vleff_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 1, - /*IsStore*/ false, - /*IsUnitStrided*/ true, - /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ 1, + /*IsStore*/ false, + /*IsUnitStrided*/ true, + /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vsm: case Intrinsic::riscv_vse: case Intrinsic::riscv_vse_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 1, - /*IsStore*/ true, - /*IsUnitStrided*/ true, - /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ 1, + /*IsStore*/ true, + /*IsUnitStrided*/ true, + /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vlse: case Intrinsic::riscv_vlse_mask: case Intrinsic::riscv_vloxei: case Intrinsic::riscv_vloxei_mask: case Intrinsic::riscv_vluxei: case Intrinsic::riscv_vluxei_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 1, - /*IsStore*/ false, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ 1, + /*IsStore*/ false, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vsse: case Intrinsic::riscv_vsse_mask: case Intrinsic::riscv_vsoxei: case Intrinsic::riscv_vsoxei_mask: case Intrinsic::riscv_vsuxei: case Intrinsic::riscv_vsuxei_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ 1, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ 1, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vlseg2: case Intrinsic::riscv_vlseg3: case Intrinsic::riscv_vlseg4: @@ -2119,9 +2157,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vlseg6ff: case Intrinsic::riscv_vlseg7ff: case Intrinsic::riscv_vlseg8ff: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, - /*IsStore*/ false, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, + /*IsStore*/ false, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vlseg2_mask: case Intrinsic::riscv_vlseg3_mask: case Intrinsic::riscv_vlseg4_mask: @@ -2136,9 +2175,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vlseg6ff_mask: case Intrinsic::riscv_vlseg7ff_mask: case Intrinsic::riscv_vlseg8ff_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 5, - /*IsStore*/ false, - /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 5, + /*IsStore*/ false, + /*IsUnitStrided*/ false, /*UsePtrVal*/ true); + return; case Intrinsic::riscv_vlsseg2: case Intrinsic::riscv_vlsseg3: case Intrinsic::riscv_vlsseg4: @@ -2160,9 +2200,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vluxseg6: case Intrinsic::riscv_vluxseg7: case Intrinsic::riscv_vluxseg8: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, - /*IsStore*/ false, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, + /*IsStore*/ false, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vlsseg2_mask: case Intrinsic::riscv_vlsseg3_mask: case Intrinsic::riscv_vlsseg4_mask: @@ -2184,9 +2225,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vluxseg6_mask: case Intrinsic::riscv_vluxseg7_mask: case Intrinsic::riscv_vluxseg8_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 6, - /*IsStore*/ false, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 6, + /*IsStore*/ false, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vsseg2: case Intrinsic::riscv_vsseg3: case Intrinsic::riscv_vsseg4: @@ -2194,9 +2236,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vsseg6: case Intrinsic::riscv_vsseg7: case Intrinsic::riscv_vsseg8: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 3, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vsseg2_mask: case Intrinsic::riscv_vsseg3_mask: case Intrinsic::riscv_vsseg4_mask: @@ -2204,9 +2247,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vsseg6_mask: case Intrinsic::riscv_vsseg7_mask: case Intrinsic::riscv_vsseg8_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vssseg2: case Intrinsic::riscv_vssseg3: case Intrinsic::riscv_vssseg4: @@ -2228,9 +2272,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vsuxseg6: case Intrinsic::riscv_vsuxseg7: case Intrinsic::riscv_vsuxseg8: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 4, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_vssseg2_mask: case Intrinsic::riscv_vssseg3_mask: case Intrinsic::riscv_vssseg4_mask: @@ -2252,9 +2297,10 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, case Intrinsic::riscv_vsuxseg6_mask: case Intrinsic::riscv_vsuxseg7_mask: case Intrinsic::riscv_vsuxseg8_mask: - return SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 5, - /*IsStore*/ true, - /*IsUnitStrided*/ false); + SetRVVLoadStoreInfo(/*PtrOp*/ I.arg_size() - 5, + /*IsStore*/ true, + /*IsUnitStrided*/ false); + return; case Intrinsic::riscv_sf_vlte8: case Intrinsic::riscv_sf_vlte16: case Intrinsic::riscv_sf_vlte32: @@ -2281,7 +2327,8 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, } Info.size = MemoryLocation::UnknownSize; Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::riscv_sf_vste8: case Intrinsic::riscv_sf_vste16: case Intrinsic::riscv_sf_vste32: @@ -2308,7 +2355,8 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, } Info.size = MemoryLocation::UnknownSize; Info.flags |= MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; } } @@ -4569,7 +4617,7 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, if (VT != MVT::v4i8) return SDValue(); - // <4 x i8> BUILD_VECTOR a, b, c, d -> PACK(PPACK.DH pair(a, b), pair(c, d)) + // <4 x i8> BUILD_VECTOR a, b, c, d -> PACK(PPACK.DH pair(a, c), pair(b, d)) SDValue Val0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v4i8, Op->getOperand(0)); SDValue Val1 = @@ -4578,17 +4626,17 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v4i8, Op->getOperand(2)); SDValue Val3 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v4i8, Op->getOperand(3)); - SDValue PackDH = - DAG.getNode(RISCVISD::PPACK_DH, DL, {MVT::v2i16, MVT::v2i16}, - {Val0, Val1, Val2, Val3}); + SDValue PPairDB = + DAG.getNode(RISCVISD::PPAIRE_DB, DL, {MVT::v4i8, MVT::v4i8}, + {Val0, Val2, Val1, Val3}); return DAG.getNode( ISD::BITCAST, DL, MVT::v4i8, SDValue( DAG.getMachineNode( RISCV::PACK, DL, MVT::i32, - {DAG.getNode(ISD::BITCAST, DL, MVT::i32, PackDH.getValue(0)), - DAG.getNode(ISD::BITCAST, DL, MVT::i32, PackDH.getValue(1))}), + {DAG.getNode(ISD::BITCAST, DL, MVT::i32, PPairDB.getValue(0)), + DAG.getNode(ISD::BITCAST, DL, MVT::i32, PPairDB.getValue(1))}), 0)); } @@ -6735,7 +6783,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, bool RISCVTargetLowering::isShuffleMaskLegal(ArrayRef M, EVT VT) const { // Only support legal VTs for other shuffles for now. - if (!isTypeLegal(VT)) + if (!isTypeLegal(VT) || !Subtarget.hasVInstructions()) return false; // Support splats for any type. These should type legalize well. @@ -7497,6 +7545,8 @@ static unsigned getRISCVVLOp(SDValue Op) { OP_CASE(SMAX) OP_CASE(UMIN) OP_CASE(UMAX) + OP_CASE(ABDS) + OP_CASE(ABDU) OP_CASE(STRICT_FADD) OP_CASE(STRICT_FSUB) OP_CASE(STRICT_FMUL) @@ -8157,6 +8207,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, return DAG.getMergeValues({Res, FP2Int.getValue(1)}, DL); } SDValue FP2Int = DAG.getNode(Op.getOpcode(), DL, IVecVT, Src); + if (EltSize == 1) + // The integer should be 0 or 1/-1, so compare the integer result to 0. + return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, IVecVT), FP2Int, + ISD::SETNE); return DAG.getNode(ISD::TRUNCATE, DL, VT, FP2Int); } @@ -8785,8 +8839,14 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, return lowerToScalableOp(Op, DAG); case ISD::ABDS: case ISD::ABDU: { - SDLoc dl(Op); EVT VT = Op->getValueType(0); + // Only SEW=8/16 are supported in Zvabd. + if (Subtarget.hasStdExtZvabd() && VT.isVector() && + (VT.getVectorElementType() == MVT::i8 || + VT.getVectorElementType() == MVT::i16)) + return lowerToScalableOp(Op, DAG); + + SDLoc dl(Op); SDValue LHS = DAG.getFreeze(Op->getOperand(0)); SDValue RHS = DAG.getFreeze(Op->getOperand(1)); bool IsSigned = Op->getOpcode() == ISD::ABDS; @@ -9388,7 +9448,8 @@ SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op, GlobalAddressSDNode *N = cast(Op); assert(N->getOffset() == 0 && "unexpected offset in global node"); const GlobalValue *GV = N->getGlobal(); - return getAddr(N, DAG, GV->isDSOLocal(), GV->hasExternalWeakLinkage()); + bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(GV); + return getAddr(N, DAG, IsLocal, GV->hasExternalWeakLinkage()); } SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op, @@ -10658,6 +10719,52 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op, return DAG.getBitcast(VecVT, IntInsert); } + if (Subtarget.enablePExtSIMDCodeGen() && VecVT.isFixedLengthVector()) { + auto *IdxC = dyn_cast(Idx); + if (!IdxC) + return SDValue(); + + unsigned IdxVal = IdxC->getZExtValue(); + unsigned NumElts = VecVT.getVectorNumElements(); + MVT EltVT = VecVT.getVectorElementType(); + Vec = DAG.getBitcast(XLenVT, Vec); + SDValue ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Val); + + // For 2-element vectors, BUILD_VECTOR is more efficient since it only needs + // at most 2 instructions. + if (NumElts == 2) { + unsigned EltBits = EltVT.getSizeInBits(); + SDValue Elt0, Elt1; + if (IdxVal == 0) { + Elt0 = ExtVal; + Elt1 = DAG.getNode(ISD::SRL, DL, XLenVT, Vec, + DAG.getConstant(EltBits, DL, XLenVT)); + } else { + Elt0 = Vec; + Elt1 = ExtVal; + } + return DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, Elt0, Elt1); + } + + // For 4/8-element vectors, use MVM(or MERGE) instruction which does bitwise + // select: rd = (~mask & rd) | (mask & rs1). + // This generates: slli + lui/li + mvm + if (NumElts == 4 || NumElts == 8) { + unsigned EltBits = EltVT.getSizeInBits(); + unsigned ShiftAmt = IdxVal * EltBits; + uint64_t PosMask = ((1ULL << EltBits) - 1) << ShiftAmt; + + SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, XLenVT, ExtVal, + DAG.getConstant(ShiftAmt, DL, XLenVT)); + SDValue Mask = DAG.getConstant(PosMask, DL, XLenVT); + SDValue Result = + DAG.getNode(RISCVISD::MVM, DL, XLenVT, Vec, ShiftedVal, Mask); + return DAG.getBitcast(VecVT, Result); + } + + return SDValue(); + } + MVT ContainerVT = VecVT; // If the operand is a fixed-length vector, convert to a scalable one. if (VecVT.isFixedLengthVector()) { @@ -13664,17 +13771,22 @@ SDValue RISCVTargetLowering::lowerABS(SDValue Op, SelectionDAG &DAG) const { } else std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); - SDValue SplatZero = DAG.getNode( - RISCVISD::VMV_V_X_VL, DL, ContainerVT, DAG.getUNDEF(ContainerVT), - DAG.getConstant(0, DL, Subtarget.getXLenVT()), VL); - SDValue NegX = DAG.getNode(RISCVISD::SUB_VL, DL, ContainerVT, SplatZero, X, - DAG.getUNDEF(ContainerVT), Mask, VL); - SDValue Max = DAG.getNode(RISCVISD::SMAX_VL, DL, ContainerVT, X, NegX, - DAG.getUNDEF(ContainerVT), Mask, VL); - + SDValue Result; + if (Subtarget.hasStdExtZvabd()) { + Result = DAG.getNode(RISCVISD::ABS_VL, DL, ContainerVT, X, + DAG.getUNDEF(ContainerVT), Mask, VL); + } else { + SDValue SplatZero = DAG.getNode( + RISCVISD::VMV_V_X_VL, DL, ContainerVT, DAG.getUNDEF(ContainerVT), + DAG.getConstant(0, DL, Subtarget.getXLenVT()), VL); + SDValue NegX = DAG.getNode(RISCVISD::SUB_VL, DL, ContainerVT, SplatZero, X, + DAG.getUNDEF(ContainerVT), Mask, VL); + Result = DAG.getNode(RISCVISD::SMAX_VL, DL, ContainerVT, X, NegX, + DAG.getUNDEF(ContainerVT), Mask, VL); + } if (VT.isFixedLengthVector()) - Max = convertFromScalableVector(VT, Max, DAG, Subtarget); - return Max; + Result = convertFromScalableVector(VT, Result, DAG, Subtarget); + return Result; } SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op, @@ -13892,7 +14004,7 @@ SDValue RISCVTargetLowering::lowerVPSetCCMaskOp(SDValue Op, case ISD::SETULE: { SDValue Temp = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Op1, AllOneMask, VL); - Result = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Temp, Op2, VL); + Result = DAG.getNode(RISCVISD::VMOR_VL, DL, ContainerVT, Temp, Op2, VL); break; } // X <=s Y --> X == 1 | Y == 0 --> ~Y | X @@ -13901,7 +14013,7 @@ SDValue RISCVTargetLowering::lowerVPSetCCMaskOp(SDValue Op, case ISD::SETUGE: { SDValue Temp = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Op2, AllOneMask, VL); - Result = DAG.getNode(RISCVISD::VMXOR_VL, DL, ContainerVT, Temp, Op1, VL); + Result = DAG.getNode(RISCVISD::VMOR_VL, DL, ContainerVT, Temp, Op1, VL); break; } } @@ -15015,37 +15127,53 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, case ISD::MUL: { unsigned Size = N->getSimpleValueType(0).getSizeInBits(); unsigned XLen = Subtarget.getXLen(); - // This multiply needs to be expanded, try to use MULHSU+MUL if possible. if (Size > XLen) { + // This multiply needs to be expanded, try to use MULH+MUL or WMUL if + // possible. We duplicate the default legalization to + // MULHU/MULHS/UMUL_LOHI/SMUL_LOHI to minimize the number of calls to + // MaskedValueIsZero and ComputeNumSignBits + // FIXME: Should we have a target independent MULHSU/WMULSU node? Are + // there are other targets that could use it? assert(Size == (XLen * 2) && "Unexpected custom legalisation"); + + auto MakeMULPair = [&](SDValue L, SDValue R, unsigned HighOpc, + unsigned LoHiOpc) { + MVT XLenVT = Subtarget.getXLenVT(); + L = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, L); + R = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, R); + SDValue Lo, Hi; + if (Subtarget.hasStdExtP() && !Subtarget.is64Bit()) { + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32); + Lo = DAG.getNode(LoHiOpc, DL, VTs, L, R); + Hi = Lo.getValue(1); + } else { + Lo = DAG.getNode(ISD::MUL, DL, XLenVT, L, R); + Hi = DAG.getNode(HighOpc, DL, XLenVT, L, R); + } + return DAG.getNode(ISD::BUILD_PAIR, DL, N->getValueType(0), Lo, Hi); + }; + SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); - APInt HighMask = APInt::getHighBitsSet(Size, XLen); + APInt HighMask = APInt::getHighBitsSet(Size, XLen); bool LHSIsU = DAG.MaskedValueIsZero(LHS, HighMask); bool RHSIsU = DAG.MaskedValueIsZero(RHS, HighMask); - // We need exactly one side to be unsigned. - if (LHSIsU == RHSIsU) + if (LHSIsU && RHSIsU) { + Results.push_back(MakeMULPair(LHS, RHS, ISD::MULHU, ISD::UMUL_LOHI)); return; - - auto MakeMULPair = [&](SDValue S, SDValue U) { - MVT XLenVT = Subtarget.getXLenVT(); - S = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, S); - U = DAG.getNode(ISD::TRUNCATE, DL, XLenVT, U); - SDValue Lo = DAG.getNode(ISD::MUL, DL, XLenVT, S, U); - SDValue Hi = DAG.getNode(RISCVISD::MULHSU, DL, XLenVT, S, U); - return DAG.getNode(ISD::BUILD_PAIR, DL, N->getValueType(0), Lo, Hi); - }; + } bool LHSIsS = DAG.ComputeNumSignBits(LHS) > XLen; bool RHSIsS = DAG.ComputeNumSignBits(RHS) > XLen; - - // The other operand should be signed, but still prefer MULH when - // possible. - if (RHSIsU && LHSIsS && !RHSIsS) - Results.push_back(MakeMULPair(LHS, RHS)); - else if (LHSIsU && RHSIsS && !LHSIsS) - Results.push_back(MakeMULPair(RHS, LHS)); + if (LHSIsS && RHSIsS) + Results.push_back(MakeMULPair(LHS, RHS, ISD::MULHS, ISD::SMUL_LOHI)); + else if (RHSIsU && LHSIsS) + Results.push_back( + MakeMULPair(LHS, RHS, RISCVISD::MULHSU, RISCVISD::WMULSU)); + else if (LHSIsU && RHSIsS) + Results.push_back( + MakeMULPair(RHS, LHS, RISCVISD::MULHSU, RISCVISD::WMULSU)); return; } @@ -15053,6 +15181,24 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, } case ISD::ADD: case ISD::SUB: + if (N->getValueType(0) == MVT::i64) { + assert(!Subtarget.is64Bit() && Subtarget.hasStdExtP() && + "Unexpected custom legalisation"); + + // Expand to ADDD/SUBD. + auto [LHSLo, LHSHi] = + DAG.SplitScalar(N->getOperand(0), DL, MVT::i32, MVT::i32); + auto [RHSLo, RHSHi] = + DAG.SplitScalar(N->getOperand(1), DL, MVT::i32, MVT::i32); + unsigned Opc = + N->getOpcode() == ISD::ADD ? RISCVISD::ADDD : RISCVISD::SUBD; + SDValue Res = DAG.getNode(Opc, DL, DAG.getVTList(MVT::i32, MVT::i32), + LHSLo, LHSHi, RHSLo, RHSHi); + Res = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Res, Res.getValue(1)); + Results.push_back(Res); + return; + } + assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() && "Unexpected custom legalisation"); Results.push_back(customLegalizeToWOpWithSExt(N, DAG)); @@ -15382,20 +15528,20 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NewRes)); break; } - case RISCVISD::PASUB: - case RISCVISD::PASUBU: - case RISCVISD::PMULHSU: - case RISCVISD::PMULHR: - case RISCVISD::PMULHRU: - case RISCVISD::PMULHRSU: { + case RISCVISD::ASUB: + case RISCVISD::ASUBU: + case RISCVISD::MULHSU: + case RISCVISD::MULHR: + case RISCVISD::MULHRU: + case RISCVISD::MULHRSU: { MVT VT = N->getSimpleValueType(0); SDValue Op0 = N->getOperand(0); SDValue Op1 = N->getOperand(1); unsigned Opcode = N->getOpcode(); // PMULH* variants don't support i8 [[maybe_unused]] bool IsMulH = - Opcode == RISCVISD::PMULHSU || Opcode == RISCVISD::PMULHR || - Opcode == RISCVISD::PMULHRU || Opcode == RISCVISD::PMULHRSU; + Opcode == RISCVISD::MULHSU || Opcode == RISCVISD::MULHR || + Opcode == RISCVISD::MULHRU || Opcode == RISCVISD::MULHRSU; assert(VT == MVT::v2i16 || (!IsMulH && VT == MVT::v4i8)); MVT NewVT = MVT::v4i16; if (VT == MVT::v4i8) @@ -16501,9 +16647,9 @@ static SDValue combineTruncSelectToSMaxUSat(SDNode *N, SelectionDAG &DAG) { } // Handle P extension truncate patterns: -// PASUB/PASUBU: (trunc (srl (sub ([s|z]ext a), ([s|z]ext b)), 1)) -// PMULHSU: (trunc (srl (mul (sext a), (zext b)), EltBits)) -// PMULHR*: (trunc (srl (add (mul (sext a), (zext b)), round_const), EltBits)) +// ASUB/ASUBU: (trunc (srl (sub ([s|z]ext a), ([s|z]ext b)), 1)) +// MULHSU: (trunc (srl (mul (sext a), (zext b)), EltBits)) +// MULHR*: (trunc (srl (add (mul (sext a), (zext b)), round_const), EltBits)) static SDValue combinePExtTruncate(SDNode *N, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { SDValue N0 = N->getOperand(0); @@ -16578,23 +16724,23 @@ static SDValue combinePExtTruncate(SDNode *N, SelectionDAG &DAG, if (ShAmtVal != 1) return SDValue(); if (LHSIsSExt && RHSIsSExt) - Opc = RISCVISD::PASUB; + Opc = RISCVISD::ASUB; else if (LHSIsZExt && RHSIsZExt) - Opc = RISCVISD::PASUBU; + Opc = RISCVISD::ASUBU; else return SDValue(); break; case ISD::MUL: - // PMULH*/PMULHR*: shift amount must be element size, only for i16/i32 + // MULH*/MULHR*: shift amount must be element size, only for i16/i32 if (ShAmtVal != EltBits || (EltBits != 16 && EltBits != 32)) return SDValue(); if (IsRounding) { if (LHSIsSExt && RHSIsSExt) { - Opc = RISCVISD::PMULHR; + Opc = RISCVISD::MULHR; } else if (LHSIsZExt && RHSIsZExt) { - Opc = RISCVISD::PMULHRU; + Opc = RISCVISD::MULHRU; } else if ((LHSIsSExt && RHSIsZExt) || (LHSIsZExt && RHSIsSExt)) { - Opc = RISCVISD::PMULHRSU; + Opc = RISCVISD::MULHRSU; // commuted case if (LHSIsZExt && RHSIsSExt) std::swap(A, B); @@ -16603,7 +16749,7 @@ static SDValue combinePExtTruncate(SDNode *N, SelectionDAG &DAG, } } else { if ((LHSIsSExt && RHSIsZExt) || (LHSIsZExt && RHSIsSExt)) { - Opc = RISCVISD::PMULHSU; + Opc = RISCVISD::MULHSU; // commuted case if (LHSIsZExt && RHSIsSExt) std::swap(A, B); @@ -17560,8 +17706,7 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y, ISD::CondCode CC, SDValue Mask = DAG.getAllOnesConstant(DL, CmpVT); SDValue VL = DAG.getConstant(VecSize, DL, XLenVT); - SDValue Cmp = DAG.getNode(ISD::VP_SETCC, DL, CmpVT, VecX, VecY, - DAG.getCondCode(ISD::SETNE), Mask, VL); + SDValue Cmp = DAG.getSetCC(DL, CmpVT, VecX, VecY, ISD::SETNE); return DAG.getSetCC(DL, VT, DAG.getNode(ISD::VP_REDUCE_OR, DL, XLenVT, DAG.getConstant(0, DL, XLenVT), Cmp, Mask, @@ -20918,6 +21063,64 @@ static SDValue performSHLCombine(SDNode *N, Passthru, Mask, VL); } +// Combine (ADDD (UMUL_LOHI x, y).0, (UMUL_LOHI x, y).1, a, b) into +// (WMACCU x, y, a, b). +// Combine (ADDD (SMUL_LOHI x, y).0, (SMUL_LOHI x, y).1, a, b) into +// (WMACC x, y, a, b). +static SDValue combineADDDToWMACC(SDNode *N, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + assert(N->getOpcode() == RISCVISD::ADDD && "Expected ADDD"); + assert(!Subtarget.is64Bit() && Subtarget.hasStdExtP() && + "ADDD requires RV32 with P extension"); + + // ADDD has 4 operands: (op0_lo, op0_hi, op1_lo, op1_hi) + // Try to match UMUL_LOHI or SMUL_LOHI in either operand pair due to + // commutativity + SDValue Op0Lo = N->getOperand(0); + SDValue Op0Hi = N->getOperand(1); + SDValue Op1Lo = N->getOperand(2); + SDValue Op1Hi = N->getOperand(3); + + SDNode *MulNode = nullptr; + SDValue AddLo, AddHi; + + // Check if first operand pair is UMUL_LOHI or SMUL_LOHI + if ((Op0Lo.getOpcode() == ISD::UMUL_LOHI || + Op0Lo.getOpcode() == ISD::SMUL_LOHI) && + Op0Lo.getNode() == Op0Hi.getNode() && Op0Lo.getResNo() == 0 && + Op0Hi.getResNo() == 1) { + MulNode = Op0Lo.getNode(); + AddLo = Op1Lo; + AddHi = Op1Hi; + } + // Check if second operand pair is UMUL_LOHI or SMUL_LOHI (commutative case) + else if ((Op1Lo.getOpcode() == ISD::UMUL_LOHI || + Op1Lo.getOpcode() == ISD::SMUL_LOHI) && + Op1Lo.getNode() == Op1Hi.getNode() && Op1Lo.getResNo() == 0 && + Op1Hi.getResNo() == 1) { + MulNode = Op1Lo.getNode(); + AddLo = Op0Lo; + AddHi = Op0Hi; + } else { + return SDValue(); + } + + // Only combine if both multiply results are only used by this ADDD + if (!SDValue(MulNode, 0).hasOneUse() || !SDValue(MulNode, 1).hasOneUse()) + return SDValue(); + + // Extract the multiply operands + SDValue MulOp0 = MulNode->getOperand(0); + SDValue MulOp1 = MulNode->getOperand(1); + + // Create WMACCU or WMACC node: (m1, m2, addlo, addhi) -> (lo, hi) + SDLoc DL(N); + bool IsSigned = MulNode->getOpcode() == ISD::SMUL_LOHI; + unsigned Opc = IsSigned ? RISCVISD::WMACC : RISCVISD::WMACCU; + return DAG.getNode(Opc, DL, DAG.getVTList(MVT::i32, MVT::i32), MulOp0, MulOp1, + AddLo, AddHi); +} + SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { SelectionDAG &DAG = DCI.DAG; @@ -21008,6 +21211,17 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, return SDValue(N, 0); break; } + case RISCVISD::ADDD: + return combineADDDToWMACC(N, DAG, Subtarget); + case RISCVISD::WMULSU: { + // Convert to MULHSU if only the upper half is used. + if (!N->hasAnyUseOfValue(0)) { + SDValue Res = DAG.getNode(RISCVISD::MULHSU, DL, N->getValueType(1), + N->getOperand(0), N->getOperand(1)); + return DCI.CombineTo(N, Res, Res); + } + break; + } case RISCVISD::FMV_W_X_RV64: { // If the input to FMV_W_X_RV64 is just FMV_X_ANYEXTW_RV64 the the // conversion is unnecessary and can be replaced with the @@ -25934,11 +26148,6 @@ bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const { !isa(&Inst)) return true; - if (const AllocaInst *AI = dyn_cast(&Inst)) { - if (AI->getAllocatedType()->isScalableTy()) - return true; - } - return false; } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index c203a6460992c..4a27bef2013ac 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -35,8 +35,8 @@ class RISCVTargetLowering : public TargetLowering { const RISCVSubtarget &getSubtarget() const { return Subtarget; } - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td index b912e379580a1..8aa3fb341e3b4 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td @@ -35,16 +35,20 @@ def MOPSTIndexedUnord : RISCVMOP<0b01>; def MOPSTStrided : RISCVMOP<0b10>; def MOPSTIndexedOrder : RISCVMOP<0b11>; -class RISCVLSUMOP val> { +class RISCVLUMOP val> { bits<5> Value = val; } -def LUMOPUnitStride : RISCVLSUMOP<0b00000>; -def LUMOPUnitStrideMask : RISCVLSUMOP<0b01011>; -def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>; -def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>; -def SUMOPUnitStride : RISCVLSUMOP<0b00000>; -def SUMOPUnitStrideMask : RISCVLSUMOP<0b01011>; -def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>; +def LUMOPUnitStride : RISCVLUMOP<0b00000>; +def LUMOPUnitStrideMask : RISCVLUMOP<0b01011>; +def LUMOPUnitStrideWholeReg : RISCVLUMOP<0b01000>; +def LUMOPUnitStrideFF: RISCVLUMOP<0b10000>; + +class RISCVSUMOP val> { + bits<5> Value = val; +} +def SUMOPUnitStride : RISCVSUMOP<0b00000>; +def SUMOPUnitStrideMask : RISCVSUMOP<0b01011>; +def SUMOPUnitStrideWholeReg : RISCVSUMOP<0b01000>; class RISCVWidth val> { bits<4> Value = val; @@ -158,21 +162,20 @@ class RVInstVUnaryRd funct6, bits<5> vs1, RISCVVFormat opv, dag outs, let RVVConstraint = NoConstraint; } -class RVInstVLU nf, bit mew, RISCVLSUMOP lumop, - bits<3> width, dag outs, dag ins, string opcodestr, - string argstr> +class RVInstVLoadBase nf, RISCVWidth width, RISCVMOP mop, + dag outs, dag ins, string opcodestr, string argstr> : RVInst { bits<5> rs1; bits<5> vd; bit vm; let Inst{31-29} = nf; - let Inst{28} = mew; - let Inst{27-26} = MOPLDUnitStride.Value; + let Inst{28} = width.Value{3}; + let Inst{27-26} = mop.Value; let Inst{25} = vm; - let Inst{24-20} = lumop.Value; + // Inst{24-20} provided by subclasses let Inst{19-15} = rs1; - let Inst{14-12} = width; + let Inst{14-12} = width.Value{2-0}; let Inst{11-7} = vd; let Inst{6-0} = OPC_LOAD_FP.Value; @@ -180,109 +183,69 @@ class RVInstVLU nf, bit mew, RISCVLSUMOP lumop, let RVVConstraint = VMConstraint; } -class RVInstVLS nf, bit mew, bits<3> width, - dag outs, dag ins, string opcodestr, string argstr> - : RVInst { +class RVInstVLU nf, RISCVWidth width, RISCVLUMOP lumop, dag outs, + dag ins, string opcodestr, string argstr> + : RVInstVLoadBase { + let Inst{24-20} = lumop.Value; +} + +class RVInstVLS nf, RISCVWidth width, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstVLoadBase { bits<5> rs2; - bits<5> rs1; - bits<5> vd; - bit vm; - let Inst{31-29} = nf; - let Inst{28} = mew; - let Inst{27-26} = MOPLDStrided.Value; - let Inst{25} = vm; let Inst{24-20} = rs2; - let Inst{19-15} = rs1; - let Inst{14-12} = width; - let Inst{11-7} = vd; - let Inst{6-0} = OPC_LOAD_FP.Value; - - let Uses = [VL, VTYPE]; - let RVVConstraint = VMConstraint; } -class RVInstVLX nf, bit mew, RISCVMOP mop, bits<3> width, - dag outs, dag ins, string opcodestr, string argstr> - : RVInst { +class RVInstVLX nf, RISCVWidth width, RISCVMOP mop, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstVLoadBase { bits<5> vs2; - bits<5> rs1; - bits<5> vd; - bit vm; - let Inst{31-29} = nf; - let Inst{28} = mew; - let Inst{27-26} = mop.Value; - let Inst{25} = vm; let Inst{24-20} = vs2; - let Inst{19-15} = rs1; - let Inst{14-12} = width; - let Inst{11-7} = vd; - let Inst{6-0} = OPC_LOAD_FP.Value; - - let Uses = [VL, VTYPE]; - let RVVConstraint = VMConstraint; } -class RVInstVSU nf, bit mew, RISCVLSUMOP sumop, - bits<3> width, dag outs, dag ins, string opcodestr, - string argstr> +class RVInstVStoreBase nf, RISCVWidth width, RISCVMOP mop, dag outs, + dag ins, string opcodestr, string argstr> : RVInst { bits<5> rs1; bits<5> vs3; bit vm; let Inst{31-29} = nf; - let Inst{28} = mew; - let Inst{27-26} = MOPSTUnitStride.Value; + let Inst{28} = width.Value{3}; + let Inst{27-26} = mop.Value; let Inst{25} = vm; - let Inst{24-20} = sumop.Value; + // Inst{24-20} provided by subclasses let Inst{19-15} = rs1; - let Inst{14-12} = width; + let Inst{14-12} = width.Value{2-0}; let Inst{11-7} = vs3; let Inst{6-0} = OPC_STORE_FP.Value; let Uses = [VL, VTYPE]; } -class RVInstVSS nf, bit mew, bits<3> width, - dag outs, dag ins, string opcodestr, string argstr> - : RVInst { +class RVInstVSU nf, RISCVWidth width, RISCVSUMOP sumop, dag outs, + dag ins, string opcodestr, string argstr> + : RVInstVStoreBase { + let Inst{24-20} = sumop.Value; +} + +class RVInstVSS nf, RISCVWidth width, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstVStoreBase { bits<5> rs2; - bits<5> rs1; - bits<5> vs3; - bit vm; - let Inst{31-29} = nf; - let Inst{28} = mew; - let Inst{27-26} = MOPSTStrided.Value; - let Inst{25} = vm; let Inst{24-20} = rs2; - let Inst{19-15} = rs1; - let Inst{14-12} = width; - let Inst{11-7} = vs3; - let Inst{6-0} = OPC_STORE_FP.Value; - - let Uses = [VL, VTYPE]; } -class RVInstVSX nf, bit mew, RISCVMOP mop, bits<3> width, - dag outs, dag ins, string opcodestr, string argstr> - : RVInst { +class RVInstVSX nf, RISCVWidth width, RISCVMOP mop, dag outs, dag ins, + string opcodestr, string argstr> + : RVInstVStoreBase { bits<5> vs2; - bits<5> rs1; - bits<5> vs3; - bit vm; - let Inst{31-29} = nf; - let Inst{28} = mew; - let Inst{27-26} = mop.Value; - let Inst{25} = vm; let Inst{24-20} = vs2; - let Inst{19-15} = rs1; - let Inst{14-12} = width; - let Inst{11-7} = vs3; - let Inst{6-0} = OPC_STORE_FP.Value; - - let Uses = [VL, VTYPE]; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index a17986484d9db..2156d1919ddbe 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1898,29 +1898,6 @@ static MachineInstr *canFoldAsPredicatedOp(Register Reg, return MI; } -bool RISCVInstrInfo::analyzeSelect(const MachineInstr &MI, - SmallVectorImpl &Cond, - unsigned &TrueOp, unsigned &FalseOp, - bool &Optimizable) const { - assert(MI.getOpcode() == RISCV::PseudoCCMOVGPR && - "Unknown select instruction"); - // CCMOV operands: - // 0: Def. - // 1: LHS of compare. - // 2: RHS of compare. - // 3: Condition code. - // 4: False use. - // 5: True use. - TrueOp = 5; - FalseOp = 4; - Cond.push_back(MI.getOperand(1)); - Cond.push_back(MI.getOperand(2)); - Cond.push_back(MI.getOperand(3)); - // We can only fold when we support short forward branch opt. - Optimizable = STI.hasShortForwardBranchIALU(); - return false; -} - MachineInstr * RISCVInstrInfo::optimizeSelect(MachineInstr &MI, SmallPtrSetImpl &SeenMIs, @@ -3849,10 +3826,6 @@ std::string RISCVInstrInfo::createMIROperandComment( if (!GenericComment.empty()) return GenericComment; - // If not, we must have an immediate operand. - if (!Op.isImm()) - return std::string(); - const MCInstrDesc &Desc = MI.getDesc(); if (OpIdx >= Desc.getNumOperands()) return std::string(); @@ -3889,7 +3862,7 @@ std::string RISCVInstrInfo::createMIROperandComment( OS << "e" << SEW; break; } - case RISCVOp::OPERAND_VEC_POLICY: + case RISCVOp::OPERAND_VEC_POLICY: { unsigned Policy = Op.getImm(); assert(Policy <= (RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC) && "Invalid Policy Value"); @@ -3897,6 +3870,24 @@ std::string RISCVInstrInfo::createMIROperandComment( << (Policy & RISCVVType::MASK_AGNOSTIC ? "ma" : "mu"); break; } + case RISCVOp::OPERAND_AVL: + if (Op.isImm() && Op.getImm() == -1) + OS << "vl=VLMAX"; + else + OS << "vl"; + break; + case RISCVOp::OPERAND_VEC_RM: + if (RISCVII::usesVXRM(Desc.TSFlags)) { + assert(RISCVVXRndMode::isValidRoundingMode(Op.getImm())); + auto VXRM = static_cast(Op.getImm()); + OS << "vxrm=" << RISCVVXRndMode::roundingModeToString(VXRM); + } else { + assert(RISCVFPRndMode::isValidRoundingMode(Op.getImm())); + auto FRM = static_cast(Op.getImm()); + OS << "frm=" << RISCVFPRndMode::roundingModeToString(FRM); + } + break; + } return Comment; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 158e6b41044a5..2932efffdb814 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -175,10 +175,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override; - bool analyzeSelect(const MachineInstr &MI, - SmallVectorImpl &Cond, unsigned &TrueOp, - unsigned &FalseOp, bool &Optimizable) const override; - MachineInstr *optimizeSelect(MachineInstr &MI, SmallPtrSetImpl &SeenMIs, bool) const override; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 21cc5b49f04ce..699a1b0bf3cd3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1115,7 +1115,8 @@ def : InstAlias<"jalr $rd, (${rs})", (JALR GPR:$rd, GPR:$rs, 0), 0>; def : InstAlias<"fence", (FENCE 0xF, 0xF)>; // 0xF == iorw -let Predicates = [HasStdExtZihintpause] in +// pause is always available in the assembler and disassembler, even without +// enabling Zihintpause, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474). def : InstAlias<"pause", (FENCE 0x1, 0x0)>; // 0x1 == w def : InstAlias<"rdinstret $rd", (CSRRS GPR:$rd, INSTRET.Encoding, X0), 2>; @@ -1156,12 +1157,13 @@ def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>; def : InstAlias<"hfence.vvma", (HFENCE_VVMA X0, X0), 2>; def : InstAlias<"hfence.vvma $rs", (HFENCE_VVMA GPR:$rs, X0)>; -let Predicates = [HasStdExtZihintntl] in { - def : InstAlias<"ntl.p1", (ADD X0, X0, X2)>; - def : InstAlias<"ntl.pall", (ADD X0, X0, X3)>; - def : InstAlias<"ntl.s1", (ADD X0, X0, X4)>; - def : InstAlias<"ntl.all", (ADD X0, X0, X5)>; -} // Predicates = [HasStdExtZihintntl] +// ntl.* hints are always available in the assembler and disassembler, even +// without enabling Zihintntl, per psABI decision +// (riscv-non-isa/riscv-elf-psabi-doc#474). +def : InstAlias<"ntl.p1", (ADD X0, X0, X2)>; +def : InstAlias<"ntl.pall", (ADD X0, X0, X3)>; +def : InstAlias<"ntl.s1", (ADD X0, X0, X4)>; +def : InstAlias<"ntl.all", (ADD X0, X0, X5)>; let EmitPriority = 0 in { def : InstAlias<"lb $rd, (${rs1})", @@ -1229,9 +1231,9 @@ def : MnemonicAlias<"sbreak", "ebreak">; def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>; -let Predicates = [HasStdExtZicfilp] in { +// lpad is always available in the assembler and disassembler, even without +// enabling Zicfilp, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474). def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>; -} //===----------------------------------------------------------------------===// // .insn directive instructions @@ -1685,7 +1687,7 @@ class SelectCompressOpt def OptForMinSize : Predicate<"MF ? MF->getFunction().hasMinSize() : false">; -let Predicates = [HasStdExtC, OptForMinSize] in { +let Predicates = [HasStdExtZca, OptForMinSize] in { def : SelectCompressOpt; def : SelectCompressOpt; } @@ -2351,6 +2353,7 @@ include "RISCVInstrInfoZk.td" // Vector include "RISCVInstrInfoV.td" +include "RISCVInstrInfoZvabd.td" include "RISCVInstrInfoZvk.td" include "RISCVInstrInfoZvqdotq.td" include "RISCVInstrInfoZvfofp8min.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index 68663e01edcf9..8f76fa3b5bfd3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -516,7 +516,7 @@ def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>, } // Predicates = [HasStdExtZca] let DecoderNamespace = "RV32Only", - Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in { + Predicates = [HasStdExtZcf, IsRV32] in { def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>, Sched<[WriteFLD32, ReadFMemBase]> { bits<7> imm; @@ -542,9 +542,9 @@ let DecoderNamespace = "RV32Only", Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> { let Inst{8-7} = imm{7-6}; } -} // DecoderNamespace = "RV32Only", Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] +} // DecoderNamespace = "RV32Only", Predicates = [HasStdExtZcf, IsRV32] -let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { +let Predicates = [HasStdExtZcd] in { def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>, Sched<[WriteFLD64, ReadFMemBase]> { bits<8> imm; @@ -568,7 +568,7 @@ let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> { let Inst{9-7} = imm{8-6}; } -} // Predicates = [HasStdExtCOrZcd, HasStdExtD] in { +} // Predicates = [HasStdExtZcd] in { //===----------------------------------------------------------------------===// // HINT Instructions @@ -596,12 +596,14 @@ def : InstAlias<"c.srli64 $rs1", (C_SRLI GPRC:$rs1, 0), 0>; def : InstAlias<"c.srai64 $rs1", (C_SRAI GPRC:$rs1, 0), 0>; } -let Predicates = [HasStdExtC, HasStdExtZihintntl] in { +// c.ntl.* hints are always available when Zca is present, even without +// enabling Zihintntl, per psABI decision (riscv-non-isa/riscv-elf-psabi-doc#474). +let Predicates = [HasStdExtZca] in { def : InstAlias<"c.ntl.p1", (C_ADD X0, X2)>; def : InstAlias<"c.ntl.pall", (C_ADD X0, X3)>; def : InstAlias<"c.ntl.s1", (C_ADD X0, X4)>; def : InstAlias<"c.ntl.all", (C_ADD X0, X5)>; -} // Predicates = [HasStdExtC, HasStdExtZihintntl] +} // Predicates = [HasStdExtZca] let EmitPriority = 0 in { let Predicates = [HasStdExtZca] in { @@ -618,14 +620,14 @@ def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRNoX0:$rd, SPMem:$rs1, 0)>; def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPR:$rs2, SPMem:$rs1, 0)>; } -let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in { +let Predicates = [HasStdExtZcf, IsRV32] in { def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>; def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>; def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32:$rd, SPMem:$rs1, 0)>; def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32:$rs2, SPMem:$rs1, 0)>; } -let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { +let Predicates = [HasStdExtZcd] in { def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>; def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>; def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64:$rd, SPMem:$rs1, 0)>; @@ -910,7 +912,7 @@ def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm), } // Predicates = [HasStdExtZca, IsRV64] // Zcf Instructions -let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in { +let Predicates = [HasStdExtZcf, IsRV32] in { // Quadrant 0 def : CompressPat<(FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm), (C_FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>; @@ -922,10 +924,10 @@ let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in { (C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>; def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm), (C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>; -} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] +} // Predicates = [HasStdExtZcf, IsRV32] // Zcd Instructions -let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { +let Predicates = [HasStdExtZcd] in { // Quadrant 0 def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm), (C_FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>; @@ -937,4 +939,4 @@ let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>; def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm), (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>; -} // Predicates = [HasStdExtCOrZcd, HasStdExtD] +} // Predicates = [HasStdExtZcd] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index 0ace05d044047..560320465d1c9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -24,12 +24,14 @@ def SImm8UnsignedAsmOperand : SImmAsmOperand<8, "Unsigned"> { let RenderMethod = "addSImm8UnsignedOperands"; } -// (<2 x i16>, <2 x i16>) PPACK_DH (<4 x i8>, <4 x i8>, <4 x i8>, <4 x i8>) -def SDT_RISCVPPackDH - : SDTypeProfile<2, 4, [SDTCisVT<0, v2i16>, SDTCisSameAs<0, 1>, - SDTCisVT<2, v4i8>, SDTCisSameAs<0, 3>, - SDTCisSameAs<0, 4>, SDTCisSameAs<0, 5>]>; -def riscv_ppack_dh : RVSDNode<"PPACK_DH", SDT_RISCVPPackDH>; +// (rdlo, rdhi) PPAIRE_DB (rs1plo, rs1phi, rs2plo, rs2phi) +def SDT_RISCVPPairE_DB : SDTypeProfile<2, 4, [SDTCisVT<0, v4i8>, + SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisSameAs<0, 4>, + SDTCisSameAs<0, 5>]>; +def riscv_ppaire_db : RVSDNode<"PPAIRE_DB", SDT_RISCVPPairE_DB>; // A 8-bit signed immediate allowing range [-128, 255] // but represented as [-128, 127]. @@ -854,8 +856,14 @@ let Predicates = [HasStdExtP] in { def PPAIRO_B : RVPBinary_rr<0b0110, 0b00, 0b100, "ppairo.b">; def PPAIRO_H : RVPBinary_rr<0b0110, 0b01, 0b100, "ppairo.h">; } // Predicates = [HasStdExtP] +let Predicates = [HasStdExtP, IsRV32] in { + // This should be a MnemonicAlias, but InstAlias produces better errors. + def : InstAlias<"ppaire.h $rd, $rs1, $rs2", (PACK GPR:$rd, GPR:$rs1, GPR:$rs2), 0>; +} let Predicates = [HasStdExtP, IsRV64] in { def PPAIRE_H : RVPBinary_rr<0b0000, 0b01, 0b100, "ppaire.h">; + // This should be a MnemonicAlias, but InstAlias produces better errors. + def : InstAlias<"ppaire.w $rd, $rs1, $rs2", (PACK GPR:$rd, GPR:$rs1, GPR:$rs2), 0>; def PPAIREO_W : RVPBinary_rr<0b0010, 0b11, 0b100, "ppaireo.w">; @@ -1269,9 +1277,9 @@ let Predicates = [HasStdExtP, IsRV32] in { def PNSRAI_H : RVPNarrowingShiftH_ri<0b100, "pnsrai.h">; def NSRAI : RVPNarrowingShiftW_ri<0b100, "nsrai">; - def PNSARI_B : RVPNarrowingShiftB_ri<0b101, "pnsari.b">; - def PNSARI_H : RVPNarrowingShiftH_ri<0b101, "pnsari.h">; - def NSARI : RVPNarrowingShiftW_ri<0b101, "nsari">; + def PNSRARI_B : RVPNarrowingShiftB_ri<0b101, "pnsrari.b">; + def PNSRARI_H : RVPNarrowingShiftH_ri<0b101, "pnsrari.h">; + def NSRARI : RVPNarrowingShiftW_ri<0b101, "nsrari">; def PNCLIPI_B : RVPNarrowingShiftB_ri<0b110, "pnclipi.b">; def PNCLIPI_H : RVPNarrowingShiftH_ri<0b110, "pnclipi.h">; @@ -1435,7 +1443,7 @@ let Predicates = [HasStdExtP, IsRV32] in { def PSAS_DHX : RVPPairBinaryExchanged_rr<0b0010, 0b00, "psas.dhx">; def PSSA_DHX : RVPPairBinaryExchanged_rr<0b0010, 0b10, "pssa.dhx">; - def PAAX_DHX : RVPPairBinaryExchanged_rr<0b0011, 0b00, "paax.dhx">; + def PAAS_DHX : RVPPairBinaryExchanged_rr<0b0011, 0b00, "paas.dhx">; def PASA_DHX : RVPPairBinaryExchanged_rr<0b0011, 0b10, "pasa.dhx">; def PMSEQ_DH : RVPPairBinaryExchanged_rr<0b1000, 0b00, "pmseq.dh", Commutable=1>; @@ -1475,16 +1483,44 @@ let Predicates = [HasStdExtP, IsRV32] in { def riscv_absw : RVSDNode<"ABSW", SDT_RISCVIntUnaryOpW>; def riscv_clsw : RVSDNode<"CLSW", SDT_RISCVIntUnaryOpW>; -def SDT_RISCVPBinOp : SDTypeProfile<1, 2, [SDTCisVec<0>, - SDTCisInt<0>, - SDTCisSameAs<0, 1>, - SDTCisSameAs<0, 2>]>; -def riscv_pasub : RVSDNode<"PASUB", SDT_RISCVPBinOp>; -def riscv_pasubu : RVSDNode<"PASUBU", SDT_RISCVPBinOp>; -def riscv_pmulhsu : RVSDNode<"PMULHSU", SDT_RISCVPBinOp>; -def riscv_pmulhr : RVSDNode<"PMULHR", SDT_RISCVPBinOp>; -def riscv_pmulhru : RVSDNode<"PMULHRU", SDT_RISCVPBinOp>; -def riscv_pmulhrsu : RVSDNode<"PMULHRSU", SDT_RISCVPBinOp>; +def SDT_RISCVIntBinOpD : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, + SDTCisVT<1, i32>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<1, 3>, + SDTCisSameAs<0, 4>, + SDTCisSameAs<1, 5>]>; +def riscv_addd : RVSDNode<"ADDD", SDT_RISCVIntBinOpD, + [SDNPCommutative, SDNPAssociative]>; +def riscv_subd : RVSDNode<"SUBD", SDT_RISCVIntBinOpD>; + +def riscv_wmulsu : RVSDNode<"WMULSU", SDTIntBinHiLoOp>; + +// Averaging subtraction, (a - b) >> 2 +def riscv_asub : RVSDNode<"ASUB", SDTIntBinOp>; +def riscv_asubu : RVSDNode<"ASUBU", SDTIntBinOp>; + +// Widening multiply add (lo, hi) = wmacc(m1, m2, addlo, addhi) +def SDT_RISCVWideningMAccW : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, + SDTCisVT<1, i32>, + SDTCisVT<2, i32>, + SDTCisVT<3, i32>, + SDTCisSameAs<0, 4>, + SDTCisSameAs<0, 5>]>; +def riscv_wmacc : RVSDNode<"WMACC", SDT_RISCVWideningMAccW, + [SDNPCommutative]>; +def riscv_wmaccu : RVSDNode<"WMACCU", SDT_RISCVWideningMAccW, + [SDNPCommutative]>; + +// MULH/MULHU/MULHSU with rounding. +def riscv_mulhr : RVSDNode<"MULHR", SDTIntBinOp>; +def riscv_mulhru : RVSDNode<"MULHRU", SDTIntBinOp>; +def riscv_mulhrsu : RVSDNode<"MULHRSU", SDTIntBinOp>; + +def SDT_RISCVMVM : SDTypeProfile<1, 3, [SDTCisInt<0>, + SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>]>; +def riscv_mvm : RVSDNode<"MVM", SDT_RISCVMVM>; let Predicates = [HasStdExtP] in { def : PatGpr; @@ -1495,6 +1531,10 @@ let Predicates = [HasStdExtP] in { def : Pat<(XLenVT (fshr GPR:$rs1, GPR:$rd, shiftMaskXLen:$rs2)), (SRX GPR:$rd, GPR:$rs1, shiftMaskXLen:$rs2)>; + // Pattern for insert_vector_elt + def : Pat<(XLenVT (riscv_mvm GPR:$rd, GPR:$rs1, GPR:$rs2)), + (MVM GPR:$rd, GPR:$rs1, GPR:$rs2)>; + // Basic 8-bit arithmetic patterns def: Pat<(XLenVecI8VT (add GPR:$rs1, GPR:$rs2)), (PADD_B GPR:$rs1, GPR:$rs2)>; def: Pat<(XLenVecI8VT (sub GPR:$rs1, GPR:$rs2)), (PSUB_B GPR:$rs1, GPR:$rs2)>; @@ -1540,14 +1580,14 @@ let Predicates = [HasStdExtP] in { // 8-bit averaging patterns def: Pat<(XLenVecI8VT (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_B GPR:$rs1, GPR:$rs2)>; def: Pat<(XLenVecI8VT (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_B GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI8VT (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_B GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI8VT (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (riscv_asub GPR:$rs1, GPR:$rs2)), (PASUB_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (riscv_asubu GPR:$rs1, GPR:$rs2)), (PASUBU_B GPR:$rs1, GPR:$rs2)>; // 16-bit averaging patterns def: Pat<(XLenVecI16VT (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_H GPR:$rs1, GPR:$rs2)>; def: Pat<(XLenVecI16VT (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_H GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI16VT (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_H GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI16VT (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (riscv_asub GPR:$rs1, GPR:$rs2)), (PASUB_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (riscv_asubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>; // 8-bit absolute difference patterns def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PABD_B GPR:$rs1, GPR:$rs2)>; @@ -1560,12 +1600,12 @@ let Predicates = [HasStdExtP] in { // 16-bit multiply high patterns def: Pat<(XLenVecI16VT (mulhs GPR:$rs1, GPR:$rs2)), (PMULH_H GPR:$rs1, GPR:$rs2)>; def: Pat<(XLenVecI16VT (mulhu GPR:$rs1, GPR:$rs2)), (PMULHU_H GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI16VT (riscv_pmulhsu GPR:$rs1, GPR:$rs2)), (PMULHSU_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (riscv_mulhsu GPR:$rs1, GPR:$rs2)), (PMULHSU_H GPR:$rs1, GPR:$rs2)>; // 16-bit multiply high rounding patterns - def: Pat<(XLenVecI16VT (riscv_pmulhr GPR:$rs1, GPR:$rs2)), (PMULHR_H GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI16VT (riscv_pmulhru GPR:$rs1, GPR:$rs2)), (PMULHRU_H GPR:$rs1, GPR:$rs2)>; - def: Pat<(XLenVecI16VT (riscv_pmulhrsu GPR:$rs1, GPR:$rs2)), (PMULHRSU_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (riscv_mulhr GPR:$rs1, GPR:$rs2)), (PMULHR_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (riscv_mulhru GPR:$rs1, GPR:$rs2)), (PMULHRU_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (riscv_mulhrsu GPR:$rs1, GPR:$rs2)), (PMULHRSU_H GPR:$rs1, GPR:$rs2)>; // 8-bit logical shift left/right patterns def: Pat<(XLenVecI8VT (shl GPR:$rs1, (XLenVecI8VT (splat_vector uimm3:$shamt)))), @@ -1716,18 +1756,18 @@ let Predicates = [HasStdExtP, IsRV64] in { def: Pat<(v2i32 (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_W GPR:$rs1, GPR:$rs2)>; // 32-bit averaging-sub patterns - def: Pat<(v2i32 (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_W GPR:$rs1, GPR:$rs2)>; - def: Pat<(v2i32 (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (riscv_asub GPR:$rs1, GPR:$rs2)), (PASUB_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (riscv_asubu GPR:$rs1, GPR:$rs2)), (PASUBU_W GPR:$rs1, GPR:$rs2)>; // 32-bit multiply high patterns def: Pat<(v2i32 (mulhs GPR:$rs1, GPR:$rs2)), (PMULH_W GPR:$rs1, GPR:$rs2)>; def: Pat<(v2i32 (mulhu GPR:$rs1, GPR:$rs2)), (PMULHU_W GPR:$rs1, GPR:$rs2)>; - def: Pat<(v2i32 (riscv_pmulhsu GPR:$rs1, GPR:$rs2)), (PMULHSU_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (riscv_mulhsu GPR:$rs1, GPR:$rs2)), (PMULHSU_W GPR:$rs1, GPR:$rs2)>; // 32-bit multiply high rounding patterns - def: Pat<(v2i32 (riscv_pmulhr GPR:$rs1, GPR:$rs2)), (PMULHR_W GPR:$rs1, GPR:$rs2)>; - def: Pat<(v2i32 (riscv_pmulhru GPR:$rs1, GPR:$rs2)), (PMULHRU_W GPR:$rs1, GPR:$rs2)>; - def: Pat<(v2i32 (riscv_pmulhrsu GPR:$rs1, GPR:$rs2)), (PMULHRSU_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (riscv_mulhr GPR:$rs1, GPR:$rs2)), (PMULHR_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (riscv_mulhru GPR:$rs1, GPR:$rs2)), (PMULHRU_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (riscv_mulhrsu GPR:$rs1, GPR:$rs2)), (PMULHRSU_W GPR:$rs1, GPR:$rs2)>; // 8/16/32-bit multiply low patterns def: Pat<(v8i8 (mul GPR:$rs1, GPR:$rs2)), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index e674a48957b43..7280823b6735b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -263,76 +263,72 @@ class VLFSched : SchedCommon< class VLFSchedMC: VLFSched<"WorstCase", forceMasked=1>; // Unit-Stride Segment Loads and Stores -class VLSEGSched : SchedCommon< - [!cast("WriteVLSEG" #nf #"e" #eew #"_" #emul)], - [ReadVLDX], emul, eew, forceMasked +class VLSEGSched + : SchedCommon<[!cast("WriteVLSEG" # nfields #"e" #eew #"_" #emul)], + [ReadVLDX], emul, eew, forceMasked >; -class VLSEGSchedMC : VLSEGSched; - -class VSSEGSched : SchedCommon< - [!cast("WriteVSSEG" # nf # "e" # eew # "_" # emul)], - [!cast("ReadVSTEV_" #emul), ReadVSTX], emul, eew, forceMasked ->; -class VSSEGSchedMC : VSSEGSched; - -class VLSEGFFSched : SchedCommon< - [!cast("WriteVLSEGFF" # nf # "e" # eew # "_" # emul)], - [ReadVLDX], emul, eew, forceMasked ->; -class VLSEGFFSchedMC : VLSEGFFSched; +class VLSEGSchedMC + : VLSEGSched; + +class VSSEGSched + : SchedCommon<[!cast("WriteVSSEG" # nfields # "e" # eew # "_" # emul)], + [!cast("ReadVSTEV_" #emul), ReadVSTX], emul, eew, + forceMasked>; +class VSSEGSchedMC + : VSSEGSched; + +class VLSEGFFSched + : SchedCommon<[!cast("WriteVLSEGFF" # nfields # "e" # eew # "_" # emul)], + [ReadVLDX], emul, eew, forceMasked>; +class VLSEGFFSchedMC + : VLSEGFFSched; // Strided Segment Loads and Stores -class VLSSEGSched : SchedCommon< - [!cast("WriteVLSSEG" #nf #"e" #eew #"_" #emul)], - [ReadVLDX, ReadVLDSX], emul, eew, forceMasked ->; -class VLSSEGSchedMC : VLSSEGSched; - -class VSSSEGSched : SchedCommon< - [!cast("WriteVSSSEG" #nf #"e" #eew #"_" #emul)], - [!cast("ReadVSTS" #eew #"V_" #emul), - ReadVSTX, ReadVSTSX], emul, eew, forceMasked ->; -class VSSSEGSchedMC : VSSSEGSched; +class VLSSEGSched + : SchedCommon<[!cast("WriteVLSSEG" # nfields #"e" #eew #"_" #emul)], + [ReadVLDX, ReadVLDSX], emul, eew, forceMasked>; +class VLSSEGSchedMC + : VLSSEGSched; + +class VSSSEGSched + : SchedCommon<[!cast("WriteVSSSEG" # nfields #"e" #eew #"_" #emul)], + [!cast("ReadVSTS" #eew #"V_" #emul), ReadVSTX, ReadVSTSX], + emul, eew, forceMasked>; +class VSSSEGSchedMC + : VSSSEGSched; // Indexed Segment Loads and Stores -class VLXSEGSched : SchedCommon< - [!cast("WriteVL" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)], - [ReadVLDX, !cast("ReadVLD" #!if(isOrdered, "O", "U") #"XV_" #emul)], - emul, eew, forceMasked ->; -class VLXSEGSchedMC: - VLXSEGSched; +class VLXSEGSched + : SchedCommon<[!cast("WriteVL" #!if(isOrdered, "O", "U") #"XSEG" # nfields #"e" #eew #"_" #emul)], + [ReadVLDX, !cast("ReadVLD" #!if(isOrdered, "O", "U") #"XV_" #emul)], + emul, eew, forceMasked>; +class VLXSEGSchedMC + : VLXSEGSched; // Passes sew=0 instead of eew=0 since this pseudo does not follow MX_E form. -class VSXSEGSched : SchedCommon< - [!cast("WriteVS" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)], + [!cast("WriteVS" #!if(isOrdered, "O", "U") #"XSEG" #nfields #"e" #eew #"_" #emul)], [!cast("ReadVST" #!if(isOrdered, "O", "U") #"X" #eew #"_" #emul), ReadVSTX, !cast("ReadVST" #!if(isOrdered, "O", "U") #"XV_" #emul)], emul, sew=0, forceMasked=forceMasked >; -class VSXSEGSchedMC: - VSXSEGSched; +class VSXSEGSchedMC: + VSXSEGSched; -class RISCVVXMemOpMC E, bit Ordered, bit Store, bits<4> N = 0> { - bits<3> Log2EEW = E; +class RISCVVXMemOpMC N = 0> { + bits<3> Log2EEW = !logtwo(EEW); bits<1> IsOrdered = Ordered; bits<1> IsStore = Store; - bits<4> NF = N; + bits<4> NFields = N; Instruction BaseInstr = !cast(NAME); } def RISCVBaseVXMemOpTable : GenericTable { let FilterClass = "RISCVVXMemOpMC"; let CppTypeName = "VXMemOpInfo"; - let Fields = ["Log2EEW", "IsOrdered", "IsStore", "NF", "BaseInstr"]; + let Fields = ["Log2EEW", "IsOrdered", "IsStore", "NFields", "BaseInstr"]; let PrimaryKey = ["BaseInstr"]; let PrimaryKeyName = "getVXMemOpInfo"; } @@ -344,127 +340,147 @@ def RISCVBaseVXMemOpTable : GenericTable { let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { // unit-stride load vd, (rs1), vm class VUnitStrideLoad - : RVInstVLU<0b000, width.Value{3}, LUMOPUnitStride, width.Value{2-0}, - (outs VR:$vd), - (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">; + : RVInstVLU<0b000, width, LUMOPUnitStride, + (outs VR:$vd), (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), + opcodestr, "$vd, $rs1$vm">; -let vm = 1, RVVConstraint = NoConstraint in { // unit-stride whole register load vlr.v vd, (rs1) -class VWholeLoad nf, RISCVWidth width, string opcodestr, RegisterClass VRC> - : RVInstVLU + : RVInstVLU { + assert !and(!ge(lmul, 1), !le(lmul, 8)), "lmul must be 1-8"; + + let vm = 1; + let Uses = []; + let RVVConstraint = NoConstraint; } // unit-stride mask load vd, (rs1) -class VUnitStrideLoadMask - : RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0}, - (outs VR:$vd), - (ins GPRMemZeroOffset:$rs1), opcodestr, "$vd, $rs1">; -} // vm = 1, RVVConstraint = NoConstraint +class VUnitStrideMaskLoad + : RVInstVLU<0b000, LSWidth8, LUMOPUnitStrideMask, (outs VR:$vd), + (ins GPRMemZeroOffset:$rs1), opcodestr, "$vd, $rs1"> { + let vm = 1; + + let RVVConstraint = NoConstraint; +} // unit-stride fault-only-first load vd, (rs1), vm class VUnitStrideLoadFF - : RVInstVLU<0b000, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0}, - (outs VR:$vd), - (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">; + : RVInstVLU<0b000, width, LUMOPUnitStrideFF, (outs VR:$vd), + (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, + "$vd, $rs1$vm">; // strided load vd, (rs1), rs2, vm class VStridedLoad - : RVInstVLS<0b000, width.Value{3}, width.Value{2-0}, - (outs VR:$vd), + : RVInstVLS<0b000, width, (outs VR:$vd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, "$vd, $rs1, $rs2$vm">; // indexed load vd, (rs1), vs2, vm class VIndexedLoad - : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0}, - (outs VR:$vd), + : RVInstVLX<0b000, width, mop, (outs VR:$vd), (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, "$vd, $rs1, $vs2$vm">; // unit-stride segment load vd, (rs1), vm -class VUnitStrideSegmentLoad nf, RISCVWidth width, string opcodestr> - : RVInstVLU; +class VUnitStrideSegmentLoad + : RVInstVLU { + assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8"; +} // segment fault-only-first load vd, (rs1), vm -class VUnitStrideSegmentLoadFF nf, RISCVWidth width, string opcodestr> - : RVInstVLU; +class VUnitStrideSegmentLoadFF + : RVInstVLU { + assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8"; +} // strided segment load vd, (rs1), rs2, vm -class VStridedSegmentLoad nf, RISCVWidth width, string opcodestr> - : RVInstVLS + : RVInstVLS; + "$vd, $rs1, $rs2$vm"> { + assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8"; +} // indexed segment load vd, (rs1), vs2, vm -class VIndexedSegmentLoad nf, RISCVMOP mop, RISCVWidth width, +class VIndexedSegmentLoad - : RVInstVLX; + "$vd, $rs1, $vs2$vm"> { + assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8"; +} } // hasSideEffects = 0, mayLoad = 1, mayStore = 0 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { // unit-stride store vd, vs3, (rs1), vm class VUnitStrideStore - : RVInstVSU<0b000, width.Value{3}, SUMOPUnitStride, width.Value{2-0}, - (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, - "$vs3, ${rs1}$vm">; - -let vm = 1 in { -// vsr.v vd, (rs1) -class VWholeStore nf, string opcodestr, RegisterClass VRC> - : RVInstVSU; + +// vsr.v vd, (rs1) +class VWholeStore + : RVInstVSU { + assert !and(!ge(lmul, 1), !le(lmul, 8)), "lmul must be 1-8"; + + let vm = 1; + let Uses = []; } // unit-stride mask store vd, vs3, (rs1) -class VUnitStrideStoreMask - : RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0}, - (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1), opcodestr, - "$vs3, $rs1">; -} // vm = 1 +class VUnitStrideMaskStore + : RVInstVSU<0b000, LSWidth8, SUMOPUnitStrideMask, (outs), + (ins VR:$vs3, GPRMemZeroOffset:$rs1), opcodestr, + "$vs3, $rs1"> { + let vm = 1; +} // strided store vd, vs3, (rs1), rs2, vm class VStridedStore - : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs), + : RVInstVSS<0b000, width, (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, "$vs3, $rs1, $rs2$vm">; // indexed store vd, vs3, (rs1), vs2, vm class VIndexedStore - : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs), + : RVInstVSX<0b000, width, mop, (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, "$vs3, $rs1, $vs2$vm">; // segment store vd, vs3, (rs1), vm -class VUnitStrideSegmentStore nf, RISCVWidth width, string opcodestr> - : RVInstVSU; +class VUnitStrideSegmentStore + : RVInstVSU { + assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8"; +} // segment store vd, vs3, (rs1), rs2, vm -class VStridedSegmentStore nf, RISCVWidth width, string opcodestr> - : RVInstVSS + : RVInstVSS; + opcodestr, "$vs3, $rs1, $rs2$vm"> { + assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8"; +} // segment store vd, vs3, (rs1), vs2, vm -class VIndexedSegmentStore nf, RISCVMOP mop, RISCVWidth width, +class VIndexedSegmentStore - : RVInstVSX; + opcodestr, "$vs3, $rs1, $vs2$vm"> { + assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8"; +} } // hasSideEffects = 0, mayLoad = 0, mayStore = 1 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { @@ -587,20 +603,20 @@ multiclass VIndexLoadStore { def VLUXEI # eew # _V : VIndexedLoad, - RISCVVXMemOpMC, + RISCVVXMemOpMC, VLXSchedMC; def VLOXEI # eew # _V : VIndexedLoad, - RISCVVXMemOpMC, + RISCVVXMemOpMC, VLXSchedMC; def VSUXEI # eew # _V : VIndexedStore, - RISCVVXMemOpMC, + RISCVVXMemOpMC, VSXSchedMC; def VSOXEI # eew # _V : VIndexedStore, - RISCVVXMemOpMC, + RISCVVXMemOpMC, VSXSchedMC; } @@ -677,6 +693,20 @@ multiclass VMRG_IV_V_X_I funct6> { SchedUnaryMC<"WriteVIMergeI", "ReadVIMergeV">; } +multiclass VMV_IV_V_X_I funct6> { + let vs2 = 0, vm = 1, RVVConstraint = NoConstraint in { + def _V : RVInstVV, + SchedUnaryMC<"WriteVIMovV", "ReadVIMovV", forceMasked=0>; + def _X : RVInstVX, + SchedUnaryMC<"WriteVIMovX", "ReadVIMovX", forceMasked=0>; + def _I : RVInstIVI, + SchedNullaryMC<"WriteVIMovI", forceMasked=0>; + } +} + multiclass VALUm_IV_V_X funct6> { // if LSB of funct6 is 1, it's a mask-producing instruction that // uses a different scheduling class. @@ -1065,12 +1095,12 @@ multiclass VCPR_MV_Mask funct6, string vm = "v"> { SchedBinaryMC<"WriteVCompressV", "ReadVCompressV", "ReadVCompressV">; } -multiclass VWholeLoadN nf, string opcodestr, RegisterClass VRC> { - defvar w = !cast("LSWidth" # l); - defvar s = !cast("WriteVLD" # !add(nf, 1) # "R"); +multiclass VWholeLoadN { + defvar w = !cast("LSWidth" # eew); + defvar s = !cast("WriteVLD" # lmul # "R"); - def E # l # _V : VWholeLoad, - Sched<[s, ReadVLDX]>; + def E # eew # _V : VWholeLoad, + Sched<[s, ReadVLDX]>; } //===----------------------------------------------------------------------===// @@ -1108,10 +1138,10 @@ foreach eew = [8, 16, 32, 64] in { def VLSE#eew#_V : VStridedLoad, VLSSchedMC; def VSSE#eew#_V : VStridedStore, VSSSchedMC; - defm VL1R : VWholeLoadN; - defm VL2R : VWholeLoadN; - defm VL4R : VWholeLoadN; - defm VL8R : VWholeLoadN; + defm VL1R : VWholeLoadN; + defm VL2R : VWholeLoadN; + defm VL4R : VWholeLoadN; + defm VL8R : VWholeLoadN; } let Predicates = !if(!eq(eew, 64), [IsRV64, HasVInstructionsI64], @@ -1120,20 +1150,20 @@ foreach eew = [8, 16, 32, 64] in { } let Predicates = [HasVInstructions] in { -def VLM_V : VUnitStrideLoadMask<"vlm.v">, +def VLM_V : VUnitStrideMaskLoad<"vlm.v">, Sched<[WriteVLDM_WorstCase, ReadVLDX]>; -def VSM_V : VUnitStrideStoreMask<"vsm.v">, +def VSM_V : VUnitStrideMaskStore<"vsm.v">, Sched<[WriteVSTM_WorstCase, ReadVSTM_WorstCase, ReadVSTX]>; def : MnemonicAlias<"vle1.v", "vlm.v">; def : MnemonicAlias<"vse1.v", "vsm.v">; -def VS1R_V : VWholeStore<0, "vs1r.v", VR>, +def VS1R_V : VWholeStore<1, "vs1r.v", VR>, Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>; -def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>, +def VS2R_V : VWholeStore<2, "vs2r.v", VRM2>, Sched<[WriteVST2R, ReadVST2R, ReadVSTX]>; -def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>, +def VS4R_V : VWholeStore<4, "vs4r.v", VRM4>, Sched<[WriteVST4R, ReadVST4R, ReadVSTX]>; -def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>, +def VS8R_V : VWholeStore<8, "vs8r.v", VRM8>, Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>; def : InstAlias<"vl1r.v $vd, $rs1", (VL1RE8_V VR:$vd, GPRMemZeroOffset:$rs1)>; @@ -1343,21 +1373,8 @@ defm VWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>; defm VMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>; // Vector Integer Move Instructions -let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1, - RVVConstraint = NoConstraint in { -// op vd, vs1 -def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd), - (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">, - SchedUnaryMC<"WriteVIMovV", "ReadVIMovV", forceMasked=0>; -// op vd, rs1 -def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd), - (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">, - SchedUnaryMC<"WriteVIMovX", "ReadVIMovX", forceMasked=0>; -// op vd, imm -def VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd), - (ins simm5:$imm), "vmv.v.i", "$vd, $imm">, - SchedNullaryMC<"WriteVIMovI", forceMasked=0>; -} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +defm VMV_V : VMV_IV_V_X_I<"vmv.v", 0b010111>; // Vector Fixed-Point Arithmetic Instructions defm VSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>; @@ -1503,11 +1520,14 @@ def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd), } // Vector Floating-Point Move Instruction -let RVVConstraint = NoConstraint in -let vm = 1, vs2 = 0 in def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd), (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">, - SchedUnaryMC<"WriteVFMovV", "ReadVFMovF", forceMasked=0>; + SchedUnaryMC<"WriteVFMovV", "ReadVFMovF", forceMasked=0> { + let vm = 1; + let vs2 = 0; + + let RVVConstraint = NoConstraint; +} } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 @@ -1674,27 +1694,28 @@ defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>; // Vector Element Index Instruction let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { -let vs2 = 0 in def VID_V : RVInstVUnary<0b010100, 0b10001, OPMVV, (outs VR:$vd), (ins VMaskOp:$vm), "vid.v", "$vd$vm">, - SchedNullaryMC<"WriteVIdxV">; + SchedNullaryMC<"WriteVIdxV"> { + let vs2 = 0; +} // Integer Scalar Move Instructions -let vm = 1 in { def VMV_X_S : RVInstVUnaryRd<0b010000, 0b00000, OPMVV, (outs GPR:$rd), (ins VR:$vs2), "vmv.x.s", "$rd, $vs2">, Sched<[WriteVMovXS, ReadVMovXS]> { + let vm = 1; let Uses = [VTYPE]; } def VMV_S_X : RVInstVX<0b010000, OPMVX, (outs VR:$vd_wb), (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">, Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]> { + let vm = 1; let vs2 = 0; let Constraints = "$vd = $vd_wb"; let RVVConstraint = NoConstraint; } -} // vm = 1 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 @@ -1773,93 +1794,93 @@ foreach n = [1, 2, 4, 8] in { } // Predicates = [HasVInstructions] let Predicates = [HasVInstructions] in { - foreach nf=2-8 in { + foreach nfields=2-8 in { foreach eew = [8, 16, 32] in { defvar w = !cast("LSWidth"#eew); - def VLSEG#nf#E#eew#_V : - VUnitStrideSegmentLoad, - VLSEGSchedMC; - def VLSEG#nf#E#eew#FF_V : - VUnitStrideSegmentLoadFF, - VLSEGFFSchedMC; - def VSSEG#nf#E#eew#_V : - VUnitStrideSegmentStore, - VSSEGSchedMC; + def VLSEG#nfields#E#eew#_V : + VUnitStrideSegmentLoad, + VLSEGSchedMC; + def VLSEG#nfields#E#eew#FF_V : + VUnitStrideSegmentLoadFF, + VLSEGFFSchedMC; + def VSSEG#nfields#E#eew#_V : + VUnitStrideSegmentStore, + VSSEGSchedMC; // Vector Strided Instructions - def VLSSEG#nf#E#eew#_V : - VStridedSegmentLoad, - VLSSEGSchedMC; - def VSSSEG#nf#E#eew#_V : - VStridedSegmentStore, - VSSSEGSchedMC; + def VLSSEG#nfields#E#eew#_V : + VStridedSegmentLoad, + VLSSEGSchedMC; + def VSSSEG#nfields#E#eew#_V : + VStridedSegmentStore, + VSSSEGSchedMC; // Vector Indexed Instructions - def VLUXSEG#nf#EI#eew#_V : - VIndexedSegmentLoad, - RISCVVXMemOpMC, - VLXSEGSchedMC; - def VLOXSEG#nf#EI#eew#_V : - VIndexedSegmentLoad, - RISCVVXMemOpMC, - VLXSEGSchedMC; - def VSUXSEG#nf#EI#eew#_V : - VIndexedSegmentStore, - RISCVVXMemOpMC, - VSXSEGSchedMC; - def VSOXSEG#nf#EI#eew#_V : - VIndexedSegmentStore, - RISCVVXMemOpMC, - VSXSEGSchedMC; + def VLUXSEG#nfields#EI#eew#_V : + VIndexedSegmentLoad, + RISCVVXMemOpMC, + VLXSEGSchedMC; + def VLOXSEG#nfields#EI#eew#_V : + VIndexedSegmentLoad, + RISCVVXMemOpMC, + VLXSEGSchedMC; + def VSUXSEG#nfields#EI#eew#_V : + VIndexedSegmentStore, + RISCVVXMemOpMC, + VSXSEGSchedMC; + def VSOXSEG#nfields#EI#eew#_V : + VIndexedSegmentStore, + RISCVVXMemOpMC, + VSXSEGSchedMC; } } } // Predicates = [HasVInstructions] let Predicates = [HasVInstructionsI64] in { - foreach nf=2-8 in { + foreach nfields=2-8 in { // Vector Unit-strided Segment Instructions - def VLSEG#nf#E64_V : - VUnitStrideSegmentLoad, - VLSEGSchedMC; - def VLSEG#nf#E64FF_V : - VUnitStrideSegmentLoadFF, - VLSEGFFSchedMC; - def VSSEG#nf#E64_V : - VUnitStrideSegmentStore, - VSSEGSchedMC; + def VLSEG#nfields#E64_V : + VUnitStrideSegmentLoad, + VLSEGSchedMC; + def VLSEG#nfields#E64FF_V : + VUnitStrideSegmentLoadFF, + VLSEGFFSchedMC; + def VSSEG#nfields#E64_V : + VUnitStrideSegmentStore, + VSSEGSchedMC; // Vector Strided Segment Instructions - def VLSSEG#nf#E64_V : - VStridedSegmentLoad, - VLSSEGSchedMC; - def VSSSEG#nf#E64_V : - VStridedSegmentStore, - VSSSEGSchedMC; + def VLSSEG#nfields#E64_V : + VStridedSegmentLoad, + VLSSEGSchedMC; + def VSSSEG#nfields#E64_V : + VStridedSegmentStore, + VSSSEGSchedMC; } } // Predicates = [HasVInstructionsI64] let Predicates = [HasVInstructionsI64, IsRV64] in { - foreach nf = 2 - 8 in { + foreach nfields = 2 - 8 in { // Vector Indexed Segment Instructions - def VLUXSEG #nf #EI64_V - : VIndexedSegmentLoad, - VLXSEGSchedMC; - def VLOXSEG #nf #EI64_V - : VIndexedSegmentLoad, - VLXSEGSchedMC; - def VSUXSEG #nf #EI64_V - : VIndexedSegmentStore, - VSXSEGSchedMC; - def VSOXSEG #nf #EI64_V - : VIndexedSegmentStore, - VSXSEGSchedMC; + def VLUXSEG #nfields #EI64_V + : VIndexedSegmentLoad, + VLXSEGSchedMC; + def VLOXSEG #nfields #EI64_V + : VIndexedSegmentLoad, + VLXSEGSchedMC; + def VSUXSEG #nfields #EI64_V + : VIndexedSegmentStore, + VSXSEGSchedMC; + def VSOXSEG #nfields #EI64_V + : VIndexedSegmentStore, + VSXSEGSchedMC; } } // Predicates = [HasVInstructionsI64, IsRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 8aff5b3c62f6d..fe7dc2a21bd7f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1838,7 +1838,7 @@ multiclass VPseudoFFLoad { } } -multiclass VPseudoLoadMask { +multiclass VPseudoMaskLoad { foreach mti = AllMasks in { defvar mx = mti.LMul.MX; defvar WriteVLDM_MX = !cast("WriteVLDM_" # mx); @@ -1914,7 +1914,7 @@ multiclass VPseudoUSStore { } } -multiclass VPseudoStoreMask { +multiclass VPseudoMaskStore { foreach mti = AllMasks in { defvar mx = mti.LMul.MX; defvar WriteVSTM_MX = !cast("WriteVSTM_" # mx); @@ -2817,14 +2817,19 @@ multiclass VPseudoVFRDIV_VF_RM { } } -multiclass VPseudoVALU_VV_VX { - foreach m = MxList in { - defm "" : VPseudoBinaryV_VV, - SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX, - forcePassthruRead=true>; +multiclass VPseudoVALU_VV { + foreach m = MxList in { + defm "" : VPseudoBinaryV_VV, + SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX, + forcePassthruRead=true>; + } +} + +multiclass VPseudoVALU_VV_VX : VPseudoVALU_VV { + foreach m = MxList in { defm "" : VPseudoBinaryV_VX, - SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX, - forcePassthruRead=true>; + SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX, + forcePassthruRead=true>; } } @@ -6074,8 +6079,8 @@ def PseudoVSETIVLI : Pseudo<(outs GPR:$rd), (ins uimm5:$rs1, VTypeIOp10:$vtypei) defm PseudoVL : VPseudoUSLoad; defm PseudoVS : VPseudoUSStore; -defm PseudoVLM : VPseudoLoadMask; -defm PseudoVSM : VPseudoStoreMask; +defm PseudoVLM : VPseudoMaskLoad; +defm PseudoVSM : VPseudoMaskStore; //===----------------------------------------------------------------------===// // 7.5 Vector Strided Instructions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index 82103233ee67d..a469d7a04ec36 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -42,7 +42,7 @@ multiclass VPatUSLoadStoreSDNode; } -multiclass VPatUSLoadStoreMaskSDNode { +multiclass VPatUSMaskLoadStoreSDNode { defvar load_instr = !cast("PseudoVLM_V_"#m.BX); defvar store_instr = !cast("PseudoVSM_V_"#m.BX); // Load @@ -123,20 +123,29 @@ class VPatBinarySDNode_XI; +multiclass VPatBinarySDNode_VV vtilist = AllIntegerVectors, + bit isSEWAware = 0, + list ExtraPreds = []> { + foreach vti = vtilist in { + let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in + def : VPatBinarySDNode_VV; + } +} + multiclass VPatBinarySDNode_VV_VX vtilist = AllIntegerVectors, bit isSEWAware = 0, - list ExtraPreds = []> { + list ExtraPreds = []> + : VPatBinarySDNode_VV { foreach vti = vtilist in { - let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in { - def : VPatBinarySDNode_VV; - def : VPatBinarySDNode_XI; - } + let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in + def : VPatBinarySDNode_XI; } } @@ -879,7 +888,7 @@ foreach vti = AllVectors in vti.AVL, vti.RegClass>; foreach mti = AllMasks in let Predicates = [HasVInstructions] in - defm : VPatUSLoadStoreMaskSDNode; + defm : VPatUSMaskLoadStoreSDNode; // 11. Vector Integer Arithmetic Instructions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 51c7175a07474..46dd45876a384 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -910,21 +910,31 @@ class VPatBinaryVL_XI; +multiclass VPatBinaryVL_VV vtilist = AllIntegerVectors, + bit isSEWAware = 0, + list ExtraPreds = []> { + foreach vti = vtilist in { + let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in { + def : VPatBinaryVL_V; + } + } +} + multiclass VPatBinaryVL_VV_VX vtilist = AllIntegerVectors, bit isSEWAware = 0, - list ExtraPreds = []> { + list ExtraPreds = []> + : VPatBinaryVL_VV{ foreach vti = vtilist in { - let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in { - def : VPatBinaryVL_V; - def : VPatBinaryVL_XI; - } + let Predicates = !listconcat(ExtraPreds, GetVTypePredicates.Predicates) in + def : VPatBinaryVL_XI; } } @@ -1945,6 +1955,26 @@ multiclass VPatAVGADDVL_VV_VX_RM { } } +multiclass VPatUnaryVL_V { + foreach vti = AllIntegerVectors in { + let Predicates = !listconcat([predicate], + GetVTypePredicates.Predicates) in { + def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1), + (vti.Vector vti.RegClass:$passthru), + (vti.Mask VMV0:$vm), + VLOpFrag)), + (!cast(instruction_name#"_V_"#vti.LMul.MX#"_MASK") + vti.RegClass:$passthru, + vti.RegClass:$rs1, + (vti.Mask VMV0:$vm), + GPR:$vl, + vti.Log2SEW, + TAIL_AGNOSTIC)>; + } + } +} + //===----------------------------------------------------------------------===// // Patterns. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 4516ba9f79a1b..6051cf1aa5abf 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -182,14 +182,20 @@ class SiFiveVMACCScheds { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class CustomSiFiveVMACC funct6, RISCVVFormat opv, string opcodestr> - : RVInstVCCustom2, + : RVInstVV, SchedTernaryMC.write, SiFiveVMACCScheds.read, SiFiveVMACCScheds.read, SiFiveVMACCScheds.read> { let vm = 1; - let funct6_lo2 = funct6{1-0}; + + let Inst{6-0} = OPC_CUSTOM_2.Value; + + let Constraints = "$vd = $vd_wb"; + let RVVConstraint = NoConstraint; + let ElementsDependOn = EltDepsVLMask; + let ReadsPastVL = true; } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td index 7493ca1c56e3a..862c310ee9196 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td @@ -20,7 +20,9 @@ class CMOPInst imm3, string opcodestr> let Inst{12-11} = 0; } -foreach n = [1, 3, 5, 7, 9, 11, 13, 15] in { +// c.mop.1 and c.mop.5 are aliases for c.sspush and c.sspopchk respectively, +// defined in RISCVInstrInfoZicfiss.td. +foreach n = [3, 7, 9, 11, 13, 15] in { let Predicates = [HasStdExtZcmop] in def C_MOP_ # n : CMOPInst, Sched<[]>; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td index efd06c29dc99f..38440e0301aa1 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td @@ -24,7 +24,10 @@ class RVC_SSInst rs1val, RegisterClass reg_class, string opcodestr> : // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZicfiss] in { +// Zicfiss instructions that use Zimop encoding space are available when Zimop +// is enabled, without requiring Zicfiss explicitly. Per psABI decision +// (riscv-non-isa/riscv-elf-psabi-doc#474). +let Predicates = [HasStdExtZimop] in { let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in def SSPOPCHK : RVInstI<0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs1), "sspopchk", "$rs1"> { @@ -45,16 +48,19 @@ def SSPUSH : RVInstR<0b1100111, 0b100, OPC_SYSTEM, (outs), (ins GPRX1X5:$rs2), let rd = 0b00000; let rs1 = 0b00000; } -} // Predicates = [HasStdExtZicfiss] +} // Predicates = [HasStdExtZimop] -let Predicates = [HasStdExtZicfiss, HasStdExtZcmop], +// Compressed Zicfiss instructions use Zcmop encoding space and are available +// when Zcmop is enabled, without requiring Zicfiss explicitly. Per psABI +// decision (riscv-non-isa/riscv-elf-psabi-doc#474). +let Predicates = [HasStdExtZcmop], DecoderNamespace = "Zicfiss" in { let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in def C_SSPUSH : RVC_SSInst<0b00001, GPRX1, "c.sspush">; let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in def C_SSPOPCHK : RVC_SSInst<0b00101, GPRX5, "c.sspopchk">; -} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop] +} // Predicates = [HasStdExtZcmop] let Predicates = [HasStdExtZicfiss] in defm SSAMOSWAP_W : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">; @@ -74,14 +80,21 @@ def PseudoMOP_SSPOPCHK : Pseudo<(outs), (ins GPRX1X5:$rs1), []>, let Predicates = [HasStdExtZcmop] in { let Uses = [X1], hasSideEffects = 1, mayLoad = 0, mayStore = 1 in def PseudoMOP_C_SSPUSH : Pseudo<(outs), (ins), []>, - PseudoInstExpansion<(C_MOP_1)>; + PseudoInstExpansion<(C_SSPUSH X1)>; } // Predicates = [HasStdExtZcmop] //===----------------------------------------------------------------------===/ // Compress Instruction tablegen backend. //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZicfiss, HasStdExtZcmop] in { +let Predicates = [HasStdExtZcmop] in { def : CompressPat<(SSPUSH X1), (C_SSPUSH X1)>; def : CompressPat<(SSPOPCHK X5), (C_SSPOPCHK X5)>; -} // Predicates = [HasStdExtZicfiss, HasStdExtZcmop] +} // Predicates = [HasStdExtZcmop] + +// c.mop.1 and c.mop.5 are aliases for c.sspush ra and c.sspopchk t0. +// Use EmitPriority=0 so disassembler prints c.sspush/c.sspopchk. +let Predicates = [HasStdExtZcmop], EmitPriority = 0 in { +def : InstAlias<"c.mop.1", (C_SSPUSH X1)>; +def : InstAlias<"c.mop.5", (C_SSPOPCHK X5)>; +} // Predicates = [HasStdExtZcmop], EmitPriority = 0 diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td new file mode 100644 index 0000000000000..9c2d41e1aaa26 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td @@ -0,0 +1,82 @@ +//===-- RISCVInstrInfoZvabd.td - 'Zvabd' instructions ------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions for 'Zvabd' (Vector Absolute +/// Difference). +/// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Definitions +//===----------------------------------------------------------------------===// +let Predicates = [HasStdExtZvabd] in { + def VABS_V : VALUVs2<0b010010, 0b10000, OPMVV, "vabs.v">; + + def VABD_VV : VALUVV<0b010001, OPMVV, "vabd.vv">; + def VABDU_VV : VALUVV<0b010011, OPMVV, "vabdu.vv">; + + let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { + def VWABDA_VV : VALUVV<0b010101, OPMVV, "vwabda.vv">; + def VWABDAU_VV : VALUVV<0b010110, OPMVV, "vwabdau.vv">; + } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV +} // Predicates = [HasStdExtZvabd] + +//===----------------------------------------------------------------------===// +// Pseudos +//===----------------------------------------------------------------------===// + +multiclass PseudoVABS { + foreach m = MxList in { + defvar mx = m.MX; + let VLMul = m.value in { + def "_V_" # mx : VPseudoUnaryNoMask, + SchedUnary<"WriteVIALUV", "ReadVIALUV", mx, forcePassthruRead=true>; + def "_V_" # mx # "_MASK" : + VPseudoUnaryMask, + RISCVMaskedPseudo, + SchedUnary<"WriteVIALUV", "ReadVIALUV", mx, forcePassthruRead=true>; + } + } +} + +let Predicates = [HasStdExtZvabd] in { + defm PseudoVABS : PseudoVABS; + defm PseudoVABD : VPseudoVALU_VV; + defm PseudoVABDU : VPseudoVALU_VV; +} // Predicates = [HasStdExtZvabd] + +//===----------------------------------------------------------------------===// +// CodeGen Patterns +//===----------------------------------------------------------------------===// +let HasPassthruOp = true, HasMaskOp = true in { +def riscv_abs_vl : RVSDNode<"ABS_VL", SDT_RISCVIntUnOp_VL>; +def riscv_abds_vl : RVSDNode<"ABDS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; +def riscv_abdu_vl : RVSDNode<"ABDU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; +} // let HasPassthruOp = true, HasMaskOp = true + +// These instructions are defined for SEW=8 and SEW=16, otherwise the instruction +// encoding is reserved. +defvar ABDIntVectors = !filter(vti, AllIntegerVectors, !or(!eq(vti.SEW, 8), + !eq(vti.SEW, 16))); + +let Predicates = [HasStdExtZvabd] in { +defm : VPatBinarySDNode_VV; +defm : VPatBinarySDNode_VV; + +defm : VPatBinaryVL_VV; +defm : VPatBinaryVL_VV; + +foreach vti = AllIntegerVectors in { + def : Pat<(vti.Vector (abs (vti.Vector vti.RegClass:$rs2))), + (!cast("PseudoVABS_V_"#vti.LMul.MX) + (vti.Vector (IMPLICIT_DEF)), + vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>; +} + +defm : VPatUnaryVL_V; +} // Predicates = [HasStdExtZvabd] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index 560ba32caf3bd..3a5ddb8b2b994 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -693,6 +693,22 @@ foreach vtiToWti = AllWidenableIntVectors in { (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, uimm5:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>; + + // Patterns where the LHS is an any_extend. + // TODO: vv pattern when we have a test. + def : Pat<(shl (wti.Vector (anyext_oneuse (vti.Vector vti.RegClass:$rs2))), + (wti.Vector (Low8BitsSplatPat (XLenVT GPR:$rs1)))), + (!cast("PseudoVWSLL_VX_"#vti.LMul.MX) + (wti.Vector (IMPLICIT_DEF)), + vti.RegClass:$rs2, GPR:$rs1, + vti.AVL, vti.Log2SEW, TA_MA)>; + + def : Pat<(shl (wti.Vector (anyext_oneuse (vti.Vector vti.RegClass:$rs2))), + (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), + (!cast("PseudoVWSLL_VI_"#vti.LMul.MX) + (wti.Vector (IMPLICIT_DEF)), + vti.RegClass:$rs2, uimm5:$rs1, + vti.AVL, vti.Log2SEW, TA_MA)>; } } @@ -703,26 +719,6 @@ defm : VPatBinarySDNode_VV_VX { - foreach vti = AllIntegerVectors in { - let Predicates = !listconcat([predicate], - GetVTypePredicates.Predicates) in { - def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1), - (vti.Vector vti.RegClass:$passthru), - (vti.Mask VMV0:$vm), - VLOpFrag)), - (!cast(instruction_name#"_V_"#vti.LMul.MX#"_MASK") - vti.RegClass:$passthru, - vti.RegClass:$rs1, - (vti.Mask VMV0:$vm), - GPR:$vl, - vti.Log2SEW, - TAIL_AGNOSTIC)>; - } - } -} - foreach vti = AllIntegerVectors in { let Predicates = !listconcat([HasStdExtZvkb], GetVTypePredicates.Predicates) in { diff --git a/llvm/lib/Target/RISCV/RISCVMacroFusion.td b/llvm/lib/Target/RISCV/RISCVMacroFusion.td index 39e099bc947b2..d2c1fc11831d9 100644 --- a/llvm/lib/Target/RISCV/RISCVMacroFusion.td +++ b/llvm/lib/Target/RISCV/RISCVMacroFusion.td @@ -93,6 +93,14 @@ def TuneLDADDFusion ]>>; defvar Load = [LB, LH, LW, LD, LBU, LHU, LWU]; +defvar LoadStore = [LB, LBU, LH, LHU, LW, LWU, LD, + FLH, FLW, FLD, + SB, SH, SW, SD, + FSH, FSW, FSD]; +defvar LogicOp = [AND, OR, XOR]; +defvar LogicImmOp = [ANDI, ORI, XORI]; +defvar ShiftLeft = [SLLI, SLLIW]; +defvar ShiftRight = [SRLI, SRLIW, SRAI, SRAIW]; // Fuse add(.uw) followed by a load (lb, lh, lw, ld, lbu, lhu, lwu): // add(.uw) rd, rs1, rs2 @@ -147,3 +155,103 @@ def TuneSHXADDLoadFusion "Enable SH(1|2|3)ADD(.UW) + load macrofusion", CheckOpcode<[SH1ADD, SH2ADD, SH3ADD, SH1ADD_UW, SH2ADD_UW, SH3ADD_UW]>, CheckOpcode>; + +// Fuse logic operation followed by another logic operation: +// and/or/xor rd, rs1, rs2 +// and/or/xor rd, rd, rs3 +let IsCommutable = 1 in +def TuneFusionLogicRegReg + : SimpleFusion<"fusion-logic-reg-reg", "HasFusionLogicRegReg", + "Enable AND/OR/XOR+AND/OR/XOR macrofusion", + CheckOpcode, + CheckOpcode>; + +// Fuse logic operation followed by logic immediate operation: +// and/or/xor rd, rs1, rs2 +// andi/ori/xori rd, rd, imm +def TuneFusionLogicRegImm + : SimpleFusion<"fusion-logic-reg-imm", "HasFusionLogicRegImm", + "Enable AND/OR/XOR+ANDI/ORI/XORI macrofusion", + CheckOpcode, + CheckOpcode>; + +// Fuse logic immediate operation followed by logic operation: +// andi/ori/xori rd, rs1, imm +// and/or/xor rd, rd, rs2 +let IsCommutable = 1 in +def TuneFusionLogicImmReg + : SimpleFusion<"fusion-logic-imm-reg", "HasFusionLogicImmReg", + "Enable ANDI/ORI/XORI+AND/OR/XOR macrofusion", + CheckOpcode, + CheckOpcode>; + +// Fuse multiply followed by add: +// mul(w) rd, rs1, rs2 +// add(w) rd, rd, rs3 +def TuneFusionMulAdd + : SimpleFusion<"fusion-mul-add", "HasFusionMulAdd", + "Enable MUL+ADD macrofusion", + CheckOpcode<[MUL, MULW]>, + CheckOpcode<[ADD, ADDW]>, + epilog = [ + // Check that both instructions have the same width + FusionPredicateWithCode<[{ + if ((FirstMI->getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask) != + (SecondMI.getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask)) + return false; + }]>, + SecondFusionPredicateWithMCInstPredicate< + CheckNot> + > + ]>; + +// Fuse add with load or store with zero offset: +// add rd, rs1, rs2 +// load/store rt, 0(rd) +def TuneFusionAddMem + : Fusion<"fusion-add-mem", "HasFusionAddMem", + "Enable ADD+LOAD/STORE macrofusion", + [ + SecondFusionPredicateWithMCInstPredicate< + CheckAll<[ + CheckOpcode, + CheckIsImmOperand<2>, + CheckImmOperand<2, 0> + ]> + >, + WildcardTrue, + FirstFusionPredicateWithMCInstPredicate< + CheckAll<[ + CheckOpcode<[ADD]>, + CheckNot>, + CheckNot> + ]> + >, + TieReg<0, 1> + ]>; + +// Fuse shift left followed by shift right for bit extraction: +// slli(w) rd, rs1, imm1 +// srli(w)/srai(w) rd, rd, imm2 +// where imm1 <= imm2 +def TuneFusionShiftBitExtract + : SimpleFusion<"fusion-shift-bit-extract", "HasFusionShiftBitExtract", + "Enable SLLI+SRLI/SRAI macrofusion", + CheckOpcode, + CheckOpcode, + epilog = [ + // Check that both instructions have the same width + FusionPredicateWithCode<[{ + if ((FirstMI->getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask) != + (SecondMI.getDesc().TSFlags & RISCVII::IsSignExtendingOpWMask)) + return false; + }]>, + // Check that FirstMI's immediate <= SecondMI's immediate + FusionPredicateWithCode<[{ + if (!(FirstMI->getOperand(2).isImm() && + SecondMI.getOperand(2).isImm() && + FirstMI->getOperand(2).getImm() <= + SecondMI.getOperand(2).getImm())) + return false; + }]>, + ]>; diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp index 0c4f22e4f4331..68a752534d4fa 100644 --- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp +++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp @@ -225,9 +225,9 @@ static bool isCompressibleLoad(const MachineInstr &MI) { case RISCV::LD_RV32: return STI.hasStdExtZclsd(); case RISCV::FLW: - return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce(); + return !STI.is64Bit() && STI.hasStdExtZcf(); case RISCV::FLD: - return STI.hasStdExtCOrZcd(); + return STI.hasStdExtZcd(); // For the Xqcilo loads we mark it as compressible only if Xqcilia is also // enabled so that QC_E_ADDI can be used to create the new base. case RISCV::QC_E_LBU: @@ -258,9 +258,9 @@ static bool isCompressibleStore(const MachineInstr &MI) { case RISCV::SD_RV32: return STI.hasStdExtZclsd(); case RISCV::FSW: - return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce(); + return !STI.is64Bit() && STI.hasStdExtZcf(); case RISCV::FSD: - return STI.hasStdExtCOrZcd(); + return STI.hasStdExtZcd(); // For the Xqcilo stores we mark it as compressible only if Xqcilia is also // enabled so that QC_E_ADDI can be used to create the new base. case RISCV::QC_E_SB: diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 9a8444c0bbe9f..ca291052466be 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -78,13 +78,16 @@ class RISCVProcessorModel ConfigurableTuneFeatures = []; } -class RISCVTuneProcessorModel tunef = [], list f = []> - : ProcessorModel; + : ProcessorModel { + list ConfigurableTuneFeatures = []; +} defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore]; @@ -294,7 +297,9 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, FeatureStdExtZvfh, FeatureStdExtZba, FeatureStdExtZbb], - SiFiveIntelligenceTuneFeatures>; + SiFiveIntelligenceTuneFeatures> { + let ConfigurableTuneFeatures = [TuneHasSingleElementVecFP64]; +} def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390", SiFiveX390Model, @@ -340,7 +345,9 @@ def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390", FeatureVendorXSiFivecdiscarddlone, FeatureVendorXSiFivecflushdlone], !listconcat(SiFiveIntelligenceTuneFeatures, - [TuneHasSingleElementVecFP64])>; + [TuneHasSingleElementVecFP64])> { + let ConfigurableTuneFeatures = [TuneHasSingleElementVecFP64]; +} defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll, TuneConditionalCompressedMoveFusion, @@ -768,7 +775,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", } def SPACEMIT_X100 : RISCVProcessorModel<"spacemit-x100", - NoSchedModel, + SpacemitX100Model, !listconcat(RVA23U64Features, [FeatureStdExtZbc, FeatureStdExtZbkc, @@ -788,7 +795,13 @@ def SPACEMIT_X100 : RISCVProcessorModel<"spacemit-x100", TuneOptimizedNF2SegmentLoadStore, TuneOptimizedNF3SegmentLoadStore, TuneOptimizedNF4SegmentLoadStore, - TuneVXRMPipelineFlush]> { + TuneVXRMPipelineFlush, + TuneFusionLogicRegReg, + TuneFusionLogicRegImm, + TuneFusionLogicImmReg, + TuneFusionMulAdd, + TuneFusionAddMem, + TuneFusionShiftBitExtract]> { let MVendorID = 0x710; let MArchID = 0x8000000058000002; let MImpID = 0x33d8a600; diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h index f29f85e4987f6..df8a1b072b21c 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h @@ -68,7 +68,7 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo { const uint32_t *getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override; - unsigned getCSRFirstUseCost() const override { + unsigned getCSRCost() const override { // The cost will be compared against BlockFrequency where entry has the // value of 1 << 14. A value of 5 will choose to spill or split cold // path instead of using a callee-saved register. diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td index 71563b0ac136b..e183ad947a0a1 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td +++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td @@ -82,6 +82,81 @@ class Andes45GetLMULValue { ); } +// (VLEN/DLEN)*LMUL +// When fractional LMUL is used, the LMUL used in calculation is 1. +class Andes45GetCyclesDefault { + int c = !cond( + !eq(mx, "M1") : !mul(Andes45VLEN_DLEN_RATIO, 1), + !eq(mx, "M2") : !mul(Andes45VLEN_DLEN_RATIO, 2), + !eq(mx, "M4") : !mul(Andes45VLEN_DLEN_RATIO, 4), + !eq(mx, "M8") : !mul(Andes45VLEN_DLEN_RATIO, 8), + !eq(mx, "MF2") : !mul(Andes45VLEN_DLEN_RATIO, 1), + !eq(mx, "MF4") : !mul(Andes45VLEN_DLEN_RATIO, 1), + !eq(mx, "MF8") : !mul(Andes45VLEN_DLEN_RATIO, 1) + ); +} + +// (VLEN/DLEN)*LMUL*2, if LMUL >= 1, +// (VLEN != DLEN) ? 4 : 1, if LMUL < 1. +class Andes45GetCyclesWidening { + int c = !cond( + !eq(mx, "M1") : !mul(Andes45VLEN_DLEN_RATIO, 2), + !eq(mx, "M2") : !mul(Andes45VLEN_DLEN_RATIO, 4), + !eq(mx, "M4") : !mul(Andes45VLEN_DLEN_RATIO, 8), + // FIXME: .v* and .w* are different if LMUL < 1. + !eq(mx, "MF2") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1), + !eq(mx, "MF4") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1), + !eq(mx, "MF8") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1), + ); +} + +class Andes45GetLatencyDiv { + int c = !add(sew, 4); +} + +// (VLEN/DLEN)*LMUL*SEW+(VLEN/DLEN)*LMUL*2+1 +// = (VLEN/DLEN)*LMUL*(SEW+2)+1 +class Andes45GetCyclesDiv { + defvar a = !mul(Andes45VLEN_DLEN_RATIO, !add(sew, 2)); + int b = !cond( + !eq(mx, "M1") : !mul(a, 1), + !eq(mx, "M2") : !mul(a, 2), + !eq(mx, "M4") : !mul(a, 4), + !eq(mx, "M8") : !mul(a, 8), + !eq(mx, "MF2") : !mul(a, 1), + !eq(mx, "MF4") : !mul(a, 1), + !eq(mx, "MF8") : !mul(a, 1) + ); + + int c = !add(b, 1); +} + +// (VLEN/DLEN)*LMUL*2, if LMUL >= 1, +// (VLEN != DLEN) ? : 4 : 1, if LMUL < 1. +class Andes45GetCyclesNarrowing { + int c = !cond( + !eq(mx, "M1") : !mul(Andes45VLEN_DLEN_RATIO, 2), + !eq(mx, "M2") : !mul(Andes45VLEN_DLEN_RATIO, 4), + !eq(mx, "M4") : !mul(Andes45VLEN_DLEN_RATIO, 8), + !eq(mx, "MF2") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1), + !eq(mx, "MF4") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1), + !eq(mx, "MF8") : !if(!ne(Andes45VLEN, Andes45DLEN), 4, 1) + ); +} + +// 3, if LMUL >= 1, +// (VLEN != DLEN) ? 3 : 2, if LMUL <1. +class Andes45GetLatencyNarrowing { + int c = !cond( + !eq(mx, "M1") : 3, + !eq(mx, "M2") : 3, + !eq(mx, "M4") : 3, + !eq(mx, "MF2") : !if(!ne(Andes45VLEN, Andes45DLEN), 3, 2), + !eq(mx, "MF4") : !if(!ne(Andes45VLEN, Andes45DLEN), 3, 2), + !eq(mx, "MF8") : !if(!ne(Andes45VLEN, Andes45DLEN), 3, 2) + ); +} + def Andes45Model : SchedMachineModel { let MicroOpBufferSize = 0; // Andes45 is in-order processor let IssueWidth = 2; // 2 micro-ops dispatched per cycle @@ -588,70 +663,100 @@ foreach LMul = [1, 2, 4, 8] in { // 11. Vector Integer Arithmetic Instructions foreach mx = SchedMxList in { + defvar Cycles = Andes45GetCyclesDefault.c; defvar IsWorstCase = Andes45IsWorstCaseMX.c; - defm "" : LMULWriteResMX<"WriteVIALUV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIALUX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIALUI", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVExtV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUI", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUMV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUMX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICALUMI", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICmpV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICmpX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVICmpI", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMinMaxV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMinMaxX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMergeV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMergeX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMergeI", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMovV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMovX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMovI", [Andes45VALU], mx, IsWorstCase>; - - defm "" : LMULWriteResMX<"WriteVShiftV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVShiftX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVShiftI", [Andes45VALU], mx, IsWorstCase>; - - defm "" : LMULWriteResMX<"WriteVIMulV", [Andes45VMAC], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMulX", [Andes45VMAC], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMulAddV", [Andes45VMAC], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIMulAddX", [Andes45VMAC], mx, IsWorstCase>; + let Latency = 2, ReleaseAtCycles = [Cycles] in { + defm "" : LMULWriteResMX<"WriteVIALUV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIALUX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIALUI", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUI", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUMV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUMX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICALUMI", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMinMaxV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMinMaxX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMergeV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMergeX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMergeI", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMovV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMovX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMovI", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVShiftV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVShiftX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVShiftI", [Andes45VALU], mx, IsWorstCase>; + } + + let Latency = 2, ReleaseAtCycles = [Cycles] in + defm "" : LMULWriteResMX<"WriteVExtV", [Andes45VPERMUT], mx, IsWorstCase>; + + // Mask results can't chain. + let Latency = !add(Cycles, 2), + ReleaseAtCycles = [!add(Cycles, !ne(Andes45VLEN, Andes45DLEN))] in { + defm "" : LMULWriteResMX<"WriteVICmpV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICmpX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVICmpI", [Andes45VALU], mx, IsWorstCase>; + } +} + +foreach mx = SchedMxList in { + defvar Cycles = Andes45GetCyclesDefault.c; + defvar IsWorstCase = Andes45IsWorstCaseMX.c; + + let Latency = 4, ReleaseAtCycles = [Cycles] in { + defm "" : LMULWriteResMX<"WriteVIMulV", [Andes45VMAC], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulX", [Andes45VMAC], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulAddV", [Andes45VMAC], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIMulAddX", [Andes45VMAC], mx, IsWorstCase>; + } } // Widening foreach mx = SchedMxListW in { + defvar Cycles = Andes45GetCyclesWidening.c; defvar IsWorstCase = Andes45IsWorstCaseMX.c; - defm "" : LMULWriteResMX<"WriteVIWALUV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWALUX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWALUI", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWMulV", [Andes45VMAC], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWMulX", [Andes45VMAC], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWMulAddV", [Andes45VMAC], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVIWMulAddX", [Andes45VMAC], mx, IsWorstCase>; + let Latency = 2, ReleaseAtCycles = [Cycles] in { + defm "" : LMULWriteResMX<"WriteVIWALUV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWALUX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWALUI", [Andes45VALU], mx, IsWorstCase>; + } + + let Latency = 4, ReleaseAtCycles = [Cycles] in { + defm "" : LMULWriteResMX<"WriteVIWMulV", [Andes45VMAC], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulX", [Andes45VMAC], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulAddV", [Andes45VMAC], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIWMulAddX", [Andes45VMAC], mx, IsWorstCase>; + } } // Vector Integer Division and Remainder foreach mx = SchedMxList in { foreach sew = SchedSEWSet.val in { + defvar Latency = Andes45GetLatencyDiv.c; + defvar Cycles = Andes45GetCyclesDiv.c; defvar IsWorstCase = Andes45IsWorstCaseMXSEW.c; - defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [Andes45VDIV], mx, sew, IsWorstCase>; - defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [Andes45VDIV], mx, sew, IsWorstCase>; + let Latency = Latency, ReleaseAtCycles = [Cycles] in { + defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [Andes45VDIV], mx, sew, IsWorstCase>; + defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [Andes45VDIV], mx, sew, IsWorstCase>; + } } } // Narrowing Shift foreach mx = SchedMxListW in { + defvar Latency = Andes45GetLatencyNarrowing.c; + defvar Cycles = Andes45GetCyclesNarrowing.c; defvar IsWorstCase = Andes45IsWorstCaseMX.c; - defm "" : LMULWriteResMX<"WriteVNShiftV", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVNShiftX", [Andes45VALU], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVNShiftI", [Andes45VALU], mx, IsWorstCase>; + let Latency = Latency, ReleaseAtCycles = [Cycles] in { + defm "" : LMULWriteResMX<"WriteVNShiftV", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNShiftX", [Andes45VALU], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVNShiftI", [Andes45VALU], mx, IsWorstCase>; + } } // 12. Vector Fixed-Point Arithmetic Instructions diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td new file mode 100644 index 0000000000000..141fcb617ae7a --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td @@ -0,0 +1,370 @@ +//- RISCVSchedSpacemitX100.td - Spacemit X100 Scheduling Defs -*- tablegen -*-// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// Scheduler model for the SpacemiT-X100 processor. +// +//===----------------------------------------------------------------------===// + +def SpacemitX100Model : SchedMachineModel { + let IssueWidth = 4; // 4 micro-ops are dispatched per cycle. + let MicroOpBufferSize = 192; // Max micro-ops that can be buffered. + // 64 entry ROB. Max 3 micro-ops share one entry. + let LoadLatency = 3; // Cycles for loads to access the cache. + let MispredictPenalty = 9; // Extra cycles for a mispredicted branch. + + let CompleteModel = 0; + + let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, + HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, + HasVInstructions]; +} + +let SchedModel = SpacemitX100Model in { + +//===----------------------------------------------------------------------===// +// Define processor resources for Spacemit-X100 +let BufferSize = 6 in { + // IQ0, IQ1, BQ: 12 entry queue, can accept 2 ops and issue 1 op per cycle + // To model the accept bandwidth, split into 2 sub-queues of 6 entry each + def SMTX100_IQ0 : ProcResource<2>; //Integer Queue 0 + def SMTX100_IQ1 : ProcResource<2>; //Integer Queue 1 + def SMTX100_BQ : ProcResource<2>; //Branch Queue +} + +let BufferSize = 4 in { + // LSQ: 16 entry queue, can accept 4 ops and issue 2 op per cycle + // To model the accept bandwidth, split into 4 sub-queues of 4 entry each + def SMTX100_LSQ : ProcResource<4>; //Load Store Queue + // FQ0, FQ1: 8 entry queue, can accept 2 ops and issue 1 op per cycle + // To model the accept bandwidth, split into 2 sub-queues of 4 entry each + def SMTX100_FQ0 : ProcResource<2>; //Float Queue 0 + def SMTX100_FQ1 : ProcResource<2>; //Float Queue 1 +} + +def SMTX100_IQ : ProcResGroup<[SMTX100_IQ0, SMTX100_IQ1]>; +def SMTX100_FQ : ProcResGroup<[SMTX100_FQ0, SMTX100_FQ1]>; + +//===----------------------------------------------------------------------===// + +// Branching +let Latency = 2 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; +} + +// Integer arithmetic and logic +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// Integer multiplication +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 3; } + +// Integer division/remainder +// Latency is 4-14, Worst case latency is used +let Latency = 14, ReleaseAtCycles = [14] in { + def : WriteRes; + def : WriteRes; +} +// Latency is 4-22, Worst case latency is used +let Latency = 22, ReleaseAtCycles = [22] in { + def : WriteRes; + def : WriteRes; +} + +// Bitmanip +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +let Latency = 2 in { + def : WriteRes; + def : WriteRes; +} + +def : WriteRes; +def : WriteRes; +def : WriteRes; + +def : WriteRes; +def : WriteRes; + +def : WriteRes { let Latency = 2; } + +// Single-bit instructions +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +// Memory/Atomic memory +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; + +let Latency = 3 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; +} + +let Latency = 4 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; +} + +// Atomics +// Latency is at least 7, not sure worst case latency now +let Latency = 7 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; +} + +// Floating point units Half precision +let Latency = 3 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; +} +def : WriteRes { let Latency = 5; } + + +// Latency is 4-12, Worst case latency is used +let Latency = 12, ReleaseAtCycles = [12] in { + def : WriteRes; + def : WriteRes; +} + +// Single precision +let Latency = 3 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; +} +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 5; } + +// Latency is 4-12, Worst case latency is used +let Latency = 12, ReleaseAtCycles = [12] in { + def : WriteRes; + def : WriteRes; +} + +// Double precision +let Latency = 3 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; +} +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 4; } + +// Latency is 4-20, Worst case latency is used +let Latency = 20, ReleaseAtCycles = [20] in { + def : WriteRes; + def : WriteRes; +} + +// Zfa +let Latency = 3 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; + + def : WriteRes; + def : WriteRes; + def : WriteRes; +} + +// Conversions +let Latency = 3 in { + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + + def : WriteRes; + def : WriteRes; + def : WriteRes; + + def : WriteRes; + def : WriteRes; + def : WriteRes; + + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; + def : WriteRes; +} + +// Others +def : WriteRes; +def : WriteRes; + +//===----------------------------------------------------------------------===// +// Bypass and advance +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +// Bitmanip +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +// Single-bit instructions +def : ReadAdvance; +def : ReadAdvance; +// Zfa +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; + +//===----------------------------------------------------------------------===// +// Unsupported extensions +defm : UnsupportedSchedQ; +defm : UnsupportedSchedV; +defm : UnsupportedSchedZabha; +defm : UnsupportedSchedZbkb; +defm : UnsupportedSchedZbkx; +defm : UnsupportedSchedZfaWithQ; +defm : UnsupportedSchedZvk; +defm : UnsupportedSchedSFB; +defm : UnsupportedSchedXsf; +} + diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp index 88d32f25cb45f..ee86818805530 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -98,6 +98,15 @@ RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, assert(TuneInfo && "TuneInfo shouldn't be nullptr!"); ParseSubtargetFeatures(CPU, TuneCPU, FS); + + RISCV::updateCZceFeatureImplications(*this); + + // Re-sync the flags. + HasStdExtZcd = hasFeature(RISCV::FeatureStdExtZcd); + HasStdExtZcf = hasFeature(RISCV::FeatureStdExtZcf); + HasStdExtC = hasFeature(RISCV::FeatureStdExtC); + HasStdExtZce = hasFeature(RISCV::FeatureStdExtZce); + TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); RISCVFeatures::validate(TT, getFeatureBits()); return *this; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index cb45efe64dadf..4503b6fc44e24 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -170,12 +170,10 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool GETTER() const { return ATTRIBUTE; } #include "RISCVGenSubtargetInfo.inc" - LLVM_DEPRECATED("Now Equivalent to hasStdExtZca", "hasStdExtZca") - bool hasStdExtCOrZca() const { return HasStdExtZca; } - bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; } - bool hasStdExtCOrZcfOrZce() const { - return HasStdExtC || HasStdExtZcf || HasStdExtZce; - } + LLVM_DEPRECATED("Now Equivalent to hasStdExtZcd", "hasStdExtZcd") + bool hasStdExtCOrZcd() const { return HasStdExtZcd; } + LLVM_DEPRECATED("Now Equivalent to hasStdExtZcf", "hasStdExtZcf") + bool hasStdExtCOrZcfOrZce() const { return HasStdExtZcf; } bool hasStdExtZvl() const { return ZvlLen != 0; } bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; } bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; } diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 7eb56f52c2e66..fe4e0b6cfaebd 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -609,6 +609,11 @@ void RISCVPassConfig::addPreEmitPass2() { } void RISCVPassConfig::addMachineSSAOptimization() { + // It's beneficial to reduce the VL to enable more + // Machine SSA optimizations. + if (TM->getOptLevel() != CodeGenOptLevel::None) + addPass(createRISCVVLOptimizerPass()); + addPass(createRISCVVectorPeepholePass()); addPass(createRISCVFoldMemOffsetPass()); @@ -623,7 +628,6 @@ void RISCVPassConfig::addPreRegAlloc() { addPass(createRISCVPreRAExpandPseudoPass()); if (TM->getOptLevel() != CodeGenOptLevel::None) { addPass(createRISCVMergeBaseOffsetOptPass()); - addPass(createRISCVVLOptimizerPass()); // Add Zilsd pre-allocation load/store optimization addPass(createRISCVPreAllocZilsdOptPass()); } diff --git a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp index bc90cf8f53aba..f4d912541c849 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp @@ -10,6 +10,7 @@ #include "MCTargetDesc/RISCVMCObjectFileInfo.h" #include "RISCVTargetMachine.h" #include "llvm/BinaryFormat/ELF.h" +#include "llvm/IR/Mangler.h" #include "llvm/IR/Module.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSectionELF.h" @@ -179,3 +180,11 @@ MCSection *RISCVELFTargetObjectFile::getSectionForConstant( return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Alignment); } + +void RISCVMachOTargetObjectFile::getNameWithPrefix( + SmallVectorImpl &OutName, const GlobalValue *GV, + const TargetMachine &TM) const { + // RISC-V does not use section-relative relocations so any global symbol must + // be accessed via at least a linker-private symbol. + getMangler().getNameWithPrefix(OutName, GV, /*CannotUsePrivateLabel=*/true); +} diff --git a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h index 66790436f6ba2..c1947c8376798 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h +++ b/llvm/lib/Target/RISCV/RISCVTargetObjectFile.h @@ -58,6 +58,9 @@ class RISCVELFTargetObjectFile : public TargetLoweringObjectFileELF { class RISCVMachOTargetObjectFile : public TargetLoweringObjectFileMachO { public: RISCVMachOTargetObjectFile() {}; + + void getNameWithPrefix(SmallVectorImpl &OutName, const GlobalValue *GV, + const TargetMachine &TM) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index dc4bf0784e2d1..2fb9795ff87c8 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -1577,6 +1577,11 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, case Intrinsic::abs: { auto LT = getTypeLegalizationCost(RetTy); if (ST->hasVInstructions() && LT.second.isVector()) { + // vabs.v v10, v8 + if (ST->hasStdExtZvabd()) + return LT.first * + getRISCVInstructionCost({RISCV::VABS_V}, LT.second, CostKind); + // vrsub.vi v10, v8, 0 // vmax.vv v8, v8, v10 return LT.first * @@ -1628,6 +1633,19 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, getRISCVInstructionCost(RISCV::VADD_VX, LT.second, CostKind); return 1 + (LT.first - 1); } + case Intrinsic::vector_splice_left: + case Intrinsic::vector_splice_right: { + auto LT = getTypeLegalizationCost(RetTy); + // Constant offsets fall through to getShuffleCost. + if (!ICA.isTypeBasedOnly() && isa(ICA.getArgs()[2])) + break; + if (ST->hasVInstructions() && LT.second.isVector()) { + return LT.first * + getRISCVInstructionCost({RISCV::VSLIDEDOWN_VX, RISCV::VSLIDEUP_VX}, + LT.second, CostKind); + } + break; + } case Intrinsic::experimental_cttz_elts: { Type *ArgTy = ICA.getArgTypes()[0]; EVT ArgType = TLI->getValueType(DL, ArgTy, true); diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp index b00244af1a875..eea350b1d1725 100644 --- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp +++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp @@ -773,10 +773,11 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const { // If True has a passthru operand then it needs to be the same as vmerge's // False, since False will be used for the result's passthru operand. - Register TruePassthru = - lookThruCopies(True.getOperand(True.getNumExplicitDefs()).getReg()); - if (RISCVII::isFirstDefTiedToFirstUse(True.getDesc()) && TruePassthru && - !(TruePassthru.isVirtual() && TruePassthru == FalseReg)) { + Register TruePassthru; + if (RISCVII::isFirstDefTiedToFirstUse(True.getDesc())) + TruePassthru = + lookThruCopies(True.getOperand(True.getNumExplicitDefs()).getReg()); + if (TruePassthru && !(TruePassthru.isVirtual() && TruePassthru == FalseReg)) { // If True's passthru != False, check if it uses False in another operand // and try to commute it. int OtherIdx = True.findRegisterUseOperandIdx(FalseReg, TRI); @@ -804,6 +805,9 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const { MinVL = TrueVL; else if (RISCV::isVLKnownLE(VMergeVL, TrueVL)) MinVL = VMergeVL; + else if (!TruePassthru && !True.mayLoadOrStore()) + // If True's passthru is undef, we can use vmerge's vl. + MinVL = VMergeVL; else return false; diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp index 42de884840dc9..66500f5626fd1 100644 --- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp +++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp @@ -155,7 +155,8 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address, break; case SPIRV::OpExecutionMode: case SPIRV::OpExecutionModeId: - case SPIRV::OpLoopMerge: { + case SPIRV::OpLoopMerge: + case SPIRV::OpLoopControlINTEL: { // Print any literals after the OPERAND_UNKNOWN argument normally. printRemainingVariableOps(MI, NumFixedOps, OS); break; diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp index 23c5798f9d0af..f80926f9ff7f6 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp @@ -47,12 +47,14 @@ bool SPIRVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, // TODO: handle the case of multiple registers. if (VRegs.size() > 1) return false; + if (Val) { const auto &STI = MIRBuilder.getMF().getSubtarget(); - return MIRBuilder.buildInstr(SPIRV::OpReturnValue) + MIRBuilder.buildInstr(SPIRV::OpReturnValue) .addUse(VRegs[0]) .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), *STI.getRegBankInfo()); + return true; } MIRBuilder.buildInstr(SPIRV::OpReturn); return true; @@ -221,41 +223,17 @@ static SPIRVType *getArgSPIRVType(const Function &F, unsigned ArgIdx, static SPIRV::ExecutionModel::ExecutionModel getExecutionModel(const SPIRVSubtarget &STI, const Function &F) { + assert(STI.getEnv() != SPIRVSubtarget::Unknown && + "Environment must be resolved before lowering entry points."); + if (STI.isKernel()) return SPIRV::ExecutionModel::Kernel; - if (STI.isShader()) { - auto attribute = F.getFnAttribute("hlsl.shader"); - if (!attribute.isValid()) { - report_fatal_error( - "This entry point lacks mandatory hlsl.shader attribute."); - } - - const auto value = attribute.getValueAsString(); - if (value == "compute") - return SPIRV::ExecutionModel::GLCompute; - if (value == "vertex") - return SPIRV::ExecutionModel::Vertex; - if (value == "pixel") - return SPIRV::ExecutionModel::Fragment; - - report_fatal_error( - "This HLSL entry point is not supported by this backend."); - } - - assert(STI.getEnv() == SPIRVSubtarget::Unknown); - // "hlsl.shader" attribute is mandatory for Vulkan, so we can set Env to - // Shader whenever we find it, and to Kernel otherwise. - - // We will now change the Env based on the attribute, so we need to strip - // `const` out of the ref to STI. - SPIRVSubtarget *NonConstSTI = const_cast(&STI); auto attribute = F.getFnAttribute("hlsl.shader"); if (!attribute.isValid()) { - NonConstSTI->setEnv(SPIRVSubtarget::Kernel); - return SPIRV::ExecutionModel::Kernel; + report_fatal_error( + "This entry point lacks mandatory hlsl.shader attribute."); } - NonConstSTI->setEnv(SPIRVSubtarget::Shader); const auto value = attribute.getValueAsString(); if (value == "compute") @@ -432,11 +410,6 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, // Handle entry points and function linkage. if (isEntryPoint(F)) { - // EntryPoints can help us to determine the environment we're working on. - // Therefore, we need a non-const pointer to SPIRVSubtarget to update the - // environment if we need to. - const SPIRVSubtarget *ST = - static_cast(&MIRBuilder.getMF().getSubtarget()); auto MIB = MIRBuilder.buildInstr(SPIRV::OpEntryPoint) .addImm(static_cast(getExecutionModel(*ST, F))) .addUse(FuncVReg); @@ -698,6 +671,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, } } - return MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(), - *ST->getRegBankInfo()); + MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(), + *ST->getRegBankInfo()); + return true; } diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp index 8de1c7188a80f..1bb6b504ce8a9 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp @@ -182,7 +182,9 @@ static const std::map SPIRV::Extension::Extension:: SPV_ALTERA_arbitrary_precision_fixed_point}, {"SPV_EXT_image_raw10_raw12", - SPIRV::Extension::Extension::SPV_EXT_image_raw10_raw12}}; + SPIRV::Extension::Extension::SPV_EXT_image_raw10_raw12}, + {"SPV_INTEL_unstructured_loop_controls", + SPIRV::Extension::Extension::SPV_INTEL_unstructured_loop_controls}}; bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName, StringRef ArgValue, diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp index 0ae30a2cdf1ac..1903ec4ab90d5 100644 --- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp @@ -207,6 +207,8 @@ class SPIRVEmitIntrinsics void useRoundingMode(ConstrainedFPIntrinsic *FPI, IRBuilder<> &B); + void emitUnstructuredLoopControls(Function &F, IRBuilder<> &B); + // Tries to walk the type accessed by the given GEP instruction. // For each nested type access, one of the 2 callbacks is called: // - OnLiteralIndexing when the index is a known constant value. @@ -2029,7 +2031,7 @@ Instruction *SPIRVEmitIntrinsics::visitLoadInst(LoadInst &I) { auto *NewI = B.CreateIntrinsic(Intrinsic::spv_load, {I.getOperand(0)->getType()}, {I.getPointerOperand(), B.getInt16(Flags), - B.getInt8(I.getAlign().value())}); + B.getInt32(I.getAlign().value())}); replaceMemInstrUses(&I, NewI, B); return NewI; } @@ -2060,7 +2062,7 @@ Instruction *SPIRVEmitIntrinsics::visitStoreInst(StoreInst &I) { auto *NewI = B.CreateIntrinsic( Intrinsic::spv_store, {I.getValueOperand()->getType(), PtrOp->getType()}, {I.getValueOperand(), PtrOp, B.getInt16(Flags), - B.getInt8(I.getAlign().value())}); + B.getInt32(I.getAlign().value())}); NewI->copyMetadata(I); I.eraseFromParent(); return NewI; @@ -2086,9 +2088,9 @@ Instruction *SPIRVEmitIntrinsics::visitAllocaInst(AllocaInst &I) { ArraySize ? B.CreateIntrinsic(Intrinsic::spv_alloca_array, {PtrTy, ArraySize->getType()}, - {ArraySize, B.getInt8(I.getAlign().value())}) + {ArraySize, B.getInt32(I.getAlign().value())}) : B.CreateIntrinsic(Intrinsic::spv_alloca, {PtrTy}, - {B.getInt8(I.getAlign().value())}); + {B.getInt32(I.getAlign().value())}); replaceAllUsesWithAndErase(B, &I, NewI); return NewI; } @@ -2121,7 +2123,7 @@ void SPIRVEmitIntrinsics::processGlobalValue(GlobalVariable &GV, IRBuilder<> &B) { // Skip special artificial variables. static const StringSet<> ArtificialGlobals{"llvm.global.annotations", - "llvm.compiler.used"}; + "llvm.compiler.used", "llvm.used"}; if (ArtificialGlobals.contains(GV.getName())) return; @@ -2878,6 +2880,38 @@ SPIRVEmitIntrinsics::simplifyZeroLengthArrayGepInst(GetElementPtrInst *GEP) { return nullptr; } +void SPIRVEmitIntrinsics::emitUnstructuredLoopControls(Function &F, + IRBuilder<> &B) { + const SPIRVSubtarget *ST = TM->getSubtargetImpl(F); + // Shaders use SPIRVStructurizer which emits OpLoopMerge via spv_loop_merge. + if (ST->isShader()) + return; + if (!ST->canUseExtension( + SPIRV::Extension::SPV_INTEL_unstructured_loop_controls)) + return; + + for (BasicBlock &BB : F) { + Instruction *Term = BB.getTerminator(); + MDNode *LoopMD = Term->getMetadata(LLVMContext::MD_loop); + if (!LoopMD) + continue; + + SmallVector Ops = + getSpirvLoopControlOperandsFromLoopMetadata(LoopMD); + unsigned LC = Ops[0]; + if (LC == SPIRV::LoopControl::None) + continue; + + // Emit intrinsic: loop control mask + optional parameters. + B.SetInsertPoint(Term); + SmallVector IntrArgs; + IntrArgs.push_back(B.getInt32(LC)); + for (unsigned I = 1; I < Ops.size(); ++I) + IntrArgs.push_back(B.getInt32(Ops[I])); + B.CreateIntrinsic(Intrinsic::spv_loop_control_intel, IntrArgs); + } +} + bool SPIRVEmitIntrinsics::runOnFunction(Function &Func) { if (Func.isDeclaration()) return false; @@ -2994,6 +3028,8 @@ bool SPIRVEmitIntrinsics::runOnFunction(Function &Func) { processInstrAfterVisit(I, B); } + emitUnstructuredLoopControls(Func, B); + return true; } diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp index 5200f1ead9a13..14f1c97741ccc 100644 --- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp @@ -378,8 +378,17 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull) { - const IntegerType *Ty = cast(getTypeForSPIRVType(SpvType)); - auto *const CI = ConstantInt::get(const_cast(Ty), Val); + return getOrCreateConstInt(APInt(getScalarOrVectorBitWidth(SpvType), Val), I, + SpvType, TII, ZeroAsNull); +} + +Register SPIRVGlobalRegistry::getOrCreateConstInt(const APInt &Val, + MachineInstr &I, + const SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + bool ZeroAsNull) { + auto *const CI = ConstantInt::get( + cast(getTypeForSPIRVType(SpvType))->getContext(), Val); const MachineInstr *MI = findMI(CI, CurMF); if (MI && (MI->getOpcode() == SPIRV::OpConstantNull || MI->getOpcode() == SPIRV::OpConstantI)) @@ -525,8 +534,8 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister( } assert(Type->getOpcode() == SPIRV::OpTypeInt); SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII); - return getOrCreateConstInt(Val->getUniqueInteger().getZExtValue(), I, - SpvBaseType, TII, ZeroAsNull); + return getOrCreateConstInt(Val->getUniqueInteger(), I, SpvBaseType, TII, + ZeroAsNull); } Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull( @@ -578,12 +587,23 @@ Register SPIRVGlobalRegistry::getOrCreateConstVector(uint64_t Val, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull) { + return getOrCreateConstVector(APInt(getScalarOrVectorBitWidth(SpvType), Val), + I, SpvType, TII, ZeroAsNull); +} + +Register SPIRVGlobalRegistry::getOrCreateConstVector(const APInt &Val, + MachineInstr &I, + const SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + bool ZeroAsNull) { const Type *LLVMTy = getTypeForSPIRVType(SpvType); - assert(LLVMTy->isVectorTy()); + assert(LLVMTy->isVectorTy() && + "Expected vector type for constant vector creation"); const FixedVectorType *LLVMVecTy = cast(LLVMTy); Type *LLVMBaseTy = LLVMVecTy->getElementType(); - assert(LLVMBaseTy->isIntegerTy()); - auto *ConstVal = ConstantInt::get(LLVMBaseTy, Val); + assert(LLVMBaseTy->isIntegerTy() && + "Expected integer element type for APInt constant vector"); + auto *ConstVal = cast(ConstantInt::get(LLVMBaseTy, Val)); auto *ConstVec = ConstantVector::getSplat(LLVMVecTy->getElementCount(), ConstVal); unsigned BW = getScalarOrVectorBitWidth(SpvType); @@ -629,9 +649,10 @@ Register SPIRVGlobalRegistry::getOrCreateConstIntArray( // that would be a truly unique but dangerous key, because it could lead to // the creation of constants of arbitrary length (that is, the parameter of // memset) which were missing in the original module. + Type *I64Ty = Type::getInt64Ty(LLVMBaseTy->getContext()); Constant *UniqueKey = ConstantStruct::getAnon( {PoisonValue::get(const_cast(LLVMArrTy)), - ConstantInt::get(LLVMBaseTy, Val), ConstantInt::get(LLVMBaseTy, Num)}); + ConstantInt::get(LLVMBaseTy, Val), ConstantInt::get(I64Ty, Num)}); return getOrCreateCompositeOrNull(CI, I, SpvType, TII, UniqueKey, BW, LLVMArrTy->getNumElements()); } diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h index fa45f169f8561..b7cfa4f6f2ac1 100644 --- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h +++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h @@ -520,6 +520,10 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping { Register getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull = true); + Register getOrCreateConstInt(const APInt &Val, MachineInstr &I, + const SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + bool ZeroAsNull = true); Register createConstInt(const ConstantInt *CI, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull); @@ -535,6 +539,10 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping { Register getOrCreateConstVector(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull = true); + Register getOrCreateConstVector(const APInt &Val, MachineInstr &I, + const SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + bool ZeroAsNull = true); Register getOrCreateConstVector(APFloat Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, bool ZeroAsNull = true); diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp index 36fa5fa9a70cb..5f0c33bb44b4b 100644 --- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp @@ -93,10 +93,10 @@ MVT SPIRVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, return getRegisterType(Context, VT); } -bool SPIRVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void SPIRVTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; unsigned AlignIdx = 3; switch (Intrinsic) { case Intrinsic::spv_load: @@ -112,13 +112,12 @@ bool SPIRVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::i64; // TODO: take into account opaque pointers (don't use getElementType). // MVT::getVT(PtrTy->getElementType()); - return true; - break; + Infos.push_back(Info); + return; } default: break; } - return false; } std::pair @@ -152,14 +151,12 @@ static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, SPIRVType *NewPtrType) { MachineIRBuilder MIB(I); Register NewReg = createVirtualRegister(NewPtrType, &GR, MRI, MIB.getMF()); - bool Res = MIB.buildInstr(SPIRV::OpBitcast) - .addDef(NewReg) - .addUse(GR.getSPIRVTypeID(NewPtrType)) - .addUse(OpReg) - .constrainAllUses(*STI.getInstrInfo(), *STI.getRegisterInfo(), - *STI.getRegBankInfo()); - if (!Res) - report_fatal_error("insert validation bitcast: cannot constrain all uses"); + MIB.buildInstr(SPIRV::OpBitcast) + .addDef(NewReg) + .addUse(GR.getSPIRVTypeID(NewPtrType)) + .addUse(OpReg) + .constrainAllUses(*STI.getInstrInfo(), *STI.getRegisterInfo(), + *STI.getRegBankInfo()); I.getOperand(OpIdx).setReg(NewReg); } @@ -620,10 +617,11 @@ bool SPIRVTargetLowering::insertLogicalCopyOnResult( OldType.setReg(NewTypeReg); MachineIRBuilder MIB(*I.getNextNode()); - return MIB.buildInstr(SPIRV::OpCopyLogical) + MIB.buildInstr(SPIRV::OpCopyLogical) .addDef(OldResultReg) .addUse(OldTypeReg) .addUse(NewResultReg) .constrainAllUses(*STI.getInstrInfo(), *STI.getRegisterInfo(), *STI.getRegBankInfo()); + return true; } diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h index 5746832c8fd95..462605ab6fe36 100644 --- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h +++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h @@ -48,8 +48,8 @@ class SPIRVTargetLowering : public TargetLowering { EVT VT) const override; MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; std::pair diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td index 811a1273ed6e0..18c8ed91a9481 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td +++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td @@ -527,7 +527,7 @@ def OpUDotAccSat: Op<4454, (outs ID:$res), (ins TYPE:$type, ID:$vec1, ID:$vec2, def OpSUDotAccSat: Op<4455, (outs ID:$res), (ins TYPE:$type, ID:$vec1, ID:$vec2, ID:$acc, variable_ops), "$res = OpSUDotAccSat $type $vec1 $vec2 $acc">; -def OpFmaKHR: Op<6034, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c), +def OpFmaKHR: Op<4427, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c), "$res = OpFmaKHR $type $a $b $c">; // 3.42.14 Bit Instructions @@ -625,6 +625,8 @@ def OpPhi: Op<245, (outs ID:$res), (ins TYPE:$type, ID:$var0, ID:$block0, variab "$res = OpPhi $type $var0 $block0">; def OpLoopMerge: Op<246, (outs), (ins unknown:$merge, unknown:$continue, LoopControl:$lc, variable_ops), "OpLoopMerge $merge $continue $lc">; +def OpLoopControlINTEL: Op<5887, (outs), (ins LoopControl:$lc, variable_ops), + "OpLoopControlINTEL $lc">; def OpSelectionMerge: Op<247, (outs), (ins unknown:$merge, SelectionControl:$sc), "OpSelectionMerge $merge $sc">; def OpLabel: Op<248, (outs ID:$label), (ins), "$label = OpLabel">; diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 0d0806def7537..8c0bf64e8fcd0 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -241,6 +241,14 @@ class SPIRVInstructionSelector : public InstructionSelector { bool selectWaveReduceSum(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; + template + bool selectWaveExclusiveScan(Register ResVReg, const SPIRVType *ResType, + MachineInstr &I, bool IsUnsigned, + PickOpcodeFn &&PickOpcode) const; + + bool selectWaveExclusiveScanSum(Register ResVReg, const SPIRVType *ResType, + MachineInstr &I) const; + bool selectConst(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; @@ -345,12 +353,13 @@ class SPIRVInstructionSelector : public InstructionSelector { MachineInstr &I) const; bool selectFrexp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; + bool selectSincos(Register ResVReg, const SPIRVType *ResType, + MachineInstr &I) const; bool selectDerivativeInst(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, const unsigned DPdOpCode) const; // Utilities - std::pair - buildI32Constant(uint32_t Val, MachineInstr &I, - const SPIRVType *ResType = nullptr) const; + Register buildI32Constant(uint32_t Val, MachineInstr &I, + const SPIRVType *ResType = nullptr) const; Register buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const; bool isScalarOrVectorIntConstantZero(Register Reg) const; @@ -784,7 +793,8 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) { // Make all vregs 64 bits (for SPIR-V IDs). MRI->setType(I.getOperand(0).getReg(), LLT::scalar(64)); } - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } if (DeadMIs.contains(&I)) { @@ -836,11 +846,11 @@ bool SPIRVInstructionSelector::BuildCOPY(Register DestReg, Register SrcReg, const TargetRegisterClass *SrcRC = MRI->getRegClassOrNull(SrcReg); if (DstRC != SrcRC && SrcRC) MRI->setRegClass(DestReg, SrcRC); - return BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII.get(TargetOpcode::COPY)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY)) .addDef(DestReg) .addUse(SrcReg) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::spvSelect(Register ResVReg, @@ -882,7 +892,8 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, .addUse(I.getOperand(2).getReg()); for (auto V : I.getOperand(3).getShuffleMask()) MIB.addImm(V); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } case TargetOpcode::G_MEMMOVE: case TargetOpcode::G_MEMCPY: @@ -955,7 +966,8 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(regForLround); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } case TargetOpcode::G_STRICT_FMA: case TargetOpcode::G_FMA: { @@ -968,7 +980,8 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .setMIFlags(I.getFlags()); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma); } @@ -987,6 +1000,8 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, return selectExtInst(ResVReg, ResType, I, CL::exp2, GL::Exp2); case TargetOpcode::G_FMODF: return selectModf(ResVReg, ResType, I); + case TargetOpcode::G_FSINCOS: + return selectSincos(ResVReg, ResType, I); case TargetOpcode::G_FLOG: return selectExtInst(ResVReg, ResType, I, CL::log, GL::Log); @@ -1156,18 +1171,17 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, .addDef(NewVReg) .addUse(ResTypeReg) .addUse(GV); - return MIB.constrainAllUses(TII, TRI, RBI) && - BuildMI(BB, I, I.getDebugLoc(), - TII.get(STI.isLogicalSPIRV() - ? SPIRV::OpInBoundsAccessChain - : SPIRV::OpInBoundsPtrAccessChain)) - .addDef(ResVReg) - .addUse(ResTypeReg) - .addUse(NewVReg) - .addUse(I.getOperand(2).getReg()) - .constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), + TII.get(STI.isLogicalSPIRV() ? SPIRV::OpInBoundsAccessChain + : SPIRV::OpInBoundsPtrAccessChain)) + .addDef(ResVReg) + .addUse(ResTypeReg) + .addUse(NewVReg) + .addUse(I.getOperand(2).getReg()) + .constrainAllUses(TII, TRI, RBI); } else { - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addImm( @@ -1176,6 +1190,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, .addUse(I.getOperand(2).getReg()) .constrainAllUses(TII, TRI, RBI); } + return true; } // It's possible to translate G_PTR_ADD to OpSpecConstantOp: either to // initialize a global variable with a constant expression (e.g., the test @@ -1189,7 +1204,8 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, .addUse(GV) .addUse(Idx) .addUse(I.getOperand(2).getReg()); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } case TargetOpcode::G_ATOMICRMW_OR: @@ -1259,8 +1275,9 @@ bool SPIRVInstructionSelector::selectDebugTrap(Register ResVReg, MachineInstr &I) const { unsigned Opcode = SPIRV::OpNop; MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, @@ -1321,7 +1338,8 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg, Index = 2; for (; Index < NumOps; ++Index) MIB.add(I.getOperand(Index)); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } } return false; @@ -1381,30 +1399,83 @@ bool SPIRVInstructionSelector::selectFrexp(Register ResVReg, createVirtualRegister(PointerType, &GR, MRI, MRI->getMF()); auto It = getOpVariableMBBIt(I); - auto MIB = BuildMI(*It->getParent(), It, It->getDebugLoc(), - TII.get(SPIRV::OpVariable)) - .addDef(PointerVReg) - .addUse(GR.getSPIRVTypeID(PointerType)) - .addImm(static_cast(SPIRV::StorageClass::Function)) - .constrainAllUses(TII, TRI, RBI); - - MIB = MIB & - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addImm(static_cast(Ex.first)) - .addImm(Opcode) - .add(I.getOperand(2)) - .addUse(PointerVReg) - .constrainAllUses(TII, TRI, RBI); - - MIB = MIB & - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) - .addDef(I.getOperand(1).getReg()) - .addUse(GR.getSPIRVTypeID(PointeeTy)) - .addUse(PointerVReg) - .constrainAllUses(TII, TRI, RBI); - return MIB; + BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable)) + .addDef(PointerVReg) + .addUse(GR.getSPIRVTypeID(PointerType)) + .addImm(static_cast(SPIRV::StorageClass::Function)) + .constrainAllUses(TII, TRI, RBI); + + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addImm(static_cast(Ex.first)) + .addImm(Opcode) + .add(I.getOperand(2)) + .addUse(PointerVReg) + .constrainAllUses(TII, TRI, RBI); + + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) + .addDef(I.getOperand(1).getReg()) + .addUse(GR.getSPIRVTypeID(PointeeTy)) + .addUse(PointerVReg) + .constrainAllUses(TII, TRI, RBI); + return true; + } + return false; +} + +bool SPIRVInstructionSelector::selectSincos(Register ResVReg, + const SPIRVType *ResType, + MachineInstr &I) const { + Register CosResVReg = I.getOperand(1).getReg(); + unsigned SrcIdx = I.getNumExplicitDefs(); + Register ResTypeReg = GR.getSPIRVTypeID(ResType); + + if (STI.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) { + // OpenCL.std sincos(x, cosval*) -> returns sin(x), writes cos(x) to ptr. + MachineIRBuilder MIRBuilder(I); + const SPIRVType *PointerType = GR.getOrCreateSPIRVPointerType( + ResType, MIRBuilder, SPIRV::StorageClass::Function); + Register PointerVReg = + createVirtualRegister(PointerType, &GR, MRI, MRI->getMF()); + + auto It = getOpVariableMBBIt(I); + BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable)) + .addDef(PointerVReg) + .addUse(GR.getSPIRVTypeID(PointerType)) + .addImm(static_cast(SPIRV::StorageClass::Function)) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) + .addDef(ResVReg) + .addUse(ResTypeReg) + .addImm(static_cast(SPIRV::InstructionSet::OpenCL_std)) + .addImm(CL::sincos) + .add(I.getOperand(SrcIdx)) + .addUse(PointerVReg) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) + .addDef(CosResVReg) + .addUse(ResTypeReg) + .addUse(PointerVReg) + .constrainAllUses(TII, TRI, RBI); + return true; + } else if (STI.canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450)) { + // GLSL.std.450 has no combined sincos; emit separate Sin and Cos. + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) + .addDef(ResVReg) + .addUse(ResTypeReg) + .addImm(static_cast(SPIRV::InstructionSet::GLSL_std_450)) + .addImm(GL::Sin) + .add(I.getOperand(SrcIdx)) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) + .addDef(CosResVReg) + .addUse(ResTypeReg) + .addImm(static_cast(SPIRV::InstructionSet::GLSL_std_450)) + .addImm(GL::Cos) + .add(I.getOperand(SrcIdx)) + .constrainAllUses(TII, TRI, RBI); + return true; } return false; } @@ -1420,7 +1491,8 @@ bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg, for (Register SReg : Srcs) { MIB.addUse(SReg); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectUnOp(Register ResVReg, @@ -1457,14 +1529,16 @@ bool SPIRVInstructionSelector::selectUnOp(Register ResVReg, SpecOpcode = static_cast(SPIRV::Opcode::ConvertUToPtr); break; } - if (SpecOpcode) - return BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII.get(SPIRV::OpSpecConstantOp)) + if (SpecOpcode) { + BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(SPIRV::OpSpecConstantOp)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addImm(SpecOpcode) .addUse(SrcReg) .constrainAllUses(TII, TRI, RBI); + return true; + } } } return selectOpWithSrcs(ResVReg, ResType, I, {I.getOperand(1).getReg()}, @@ -1573,7 +1647,8 @@ bool SPIRVInstructionSelector::selectLoad(Register ResVReg, MachineIRBuilder MIRBuilder(I); addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const { @@ -1606,7 +1681,8 @@ bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const { if (sampledTypeIsSignedInteger(LLVMHandleType)) BMI.addImm(0x1000); // SignExtend - return BMI.constrainAllUses(TII, TRI, RBI); + BMI.constrainAllUses(TII, TRI, RBI); + return true; } } @@ -1623,7 +1699,8 @@ bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const { MachineIRBuilder MIRBuilder(I); addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectStackSave(Register ResVReg, @@ -1635,10 +1712,11 @@ bool SPIRVInstructionSelector::selectStackSave(Register ResVReg, "SPIR-V extension: SPV_INTEL_variable_length_array", false); MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSaveMemoryINTEL)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSaveMemoryINTEL)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectStackRestore(MachineInstr &I) const { @@ -1650,9 +1728,10 @@ bool SPIRVInstructionSelector::selectStackRestore(MachineInstr &I) const { if (!I.getOperand(0).isReg()) return false; MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpRestoreMemoryINTEL)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpRestoreMemoryINTEL)) .addUse(I.getOperand(0).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; } Register @@ -1687,8 +1766,7 @@ SPIRVInstructionSelector::getOrCreateMemSetGlobal(MachineInstr &I) const { .addUse(GR.getSPIRVTypeID(VarTy)) .addImm(SPIRV::StorageClass::UniformConstant) .addUse(Const); - if (!MIBVar.constrainAllUses(TII, TRI, RBI)) - return Register(); + MIBVar.constrainAllUses(TII, TRI, RBI); GR.add(GV, MIBVar); GR.addGlobalObject(GV, GR.CurMF, VarReg); @@ -1722,7 +1800,8 @@ bool SPIRVInstructionSelector::selectCopyMemory(MachineInstr &I, MachineIRBuilder MIRBuilder(I); addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectCopyMemorySized(MachineInstr &I, @@ -1736,13 +1815,13 @@ bool SPIRVInstructionSelector::selectCopyMemorySized(MachineInstr &I, MachineIRBuilder MIRBuilder(I); addMemoryOperands(*I.memoperands_begin(), MIB, MIRBuilder, GR); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg, MachineInstr &I) const { Register SrcReg = I.getOperand(1).getReg(); - bool Result = true; if (I.getOpcode() == TargetOpcode::G_MEMSET) { Register VarReg = getOrCreateMemSetGlobal(I); if (!VarReg.isValid()) @@ -1751,16 +1830,20 @@ bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg, SPIRVType *SourceTy = GR.getOrCreateSPIRVPointerType( ValTy, I, SPIRV::StorageClass::UniformConstant); SrcReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); - Result &= selectOpWithSrcs(SrcReg, SourceTy, I, {VarReg}, SPIRV::OpBitcast); + if (!selectOpWithSrcs(SrcReg, SourceTy, I, {VarReg}, SPIRV::OpBitcast)) + return false; } if (STI.isLogicalSPIRV()) { - Result &= selectCopyMemory(I, SrcReg); + if (!selectCopyMemory(I, SrcReg)) + return false; } else { - Result &= selectCopyMemorySized(I, SrcReg); + if (!selectCopyMemorySized(I, SrcReg)) + return false; } if (ResVReg.isValid() && ResVReg != I.getOperand(0).getReg()) - Result &= BuildCOPY(ResVReg, I.getOperand(0).getReg(), I); - return Result; + if (!BuildCOPY(ResVReg, I.getOperand(0).getReg(), I)) + return false; + return true; } bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, @@ -1768,14 +1851,11 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, MachineInstr &I, unsigned NewOpcode, unsigned NegateOpcode) const { - bool Result = true; assert(I.hasOneMemOperand()); const MachineMemOperand *MemOp = *I.memoperands_begin(); uint32_t Scope = static_cast(getMemScope( GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID())); - auto ScopeConstant = buildI32Constant(Scope, I); - Register ScopeReg = ScopeConstant.first; - Result &= ScopeConstant.second; + Register ScopeReg = buildI32Constant(Scope, I); Register Ptr = I.getOperand(1).getReg(); // TODO: Changed as it's implemented in the translator. See test/atomicrmw.ll @@ -1783,19 +1863,17 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, // getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr)); AtomicOrdering AO = MemOp->getSuccessOrdering(); uint32_t MemSem = static_cast(getMemSemantics(AO)); - auto MemSemConstant = buildI32Constant(MemSem /*| ScSem*/, I); - Register MemSemReg = MemSemConstant.first; - Result &= MemSemConstant.second; + Register MemSemReg = buildI32Constant(MemSem /*| ScSem*/, I); Register ValueReg = I.getOperand(2).getReg(); if (NegateOpcode != 0) { // Translation with negative value operand is requested Register TmpReg = createVirtualRegister(ResType, &GR, MRI, MRI->getMF()); - Result &= selectOpWithSrcs(TmpReg, ResType, I, {ValueReg}, NegateOpcode); + if (!selectOpWithSrcs(TmpReg, ResType, I, {ValueReg}, NegateOpcode)) + return false; ValueReg = TmpReg; } - return Result && BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) @@ -1804,6 +1882,7 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, .addUse(MemSemReg) .addUse(ValueReg) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { @@ -1819,7 +1898,6 @@ bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { SPIRVType *ScalarType = GR.getSPIRVTypeForVReg(SrcType->getOperand(1).getReg()); MachineBasicBlock &BB = *I.getParent(); - bool Res = false; unsigned CurrentIndex = 0; for (unsigned i = 0; i < I.getNumDefs(); ++i) { Register ResVReg = I.getOperand(i).getReg(); @@ -1850,7 +1928,7 @@ bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { MIB.addImm(CurrentIndex + j); } CurrentIndex += NumElements; - Res |= MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); } else { auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) @@ -1859,30 +1937,26 @@ bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { .addUse(SrcReg) .addImm(CurrentIndex); CurrentIndex++; - Res |= MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); } } - return Res; + return true; } bool SPIRVInstructionSelector::selectFence(MachineInstr &I) const { AtomicOrdering AO = AtomicOrdering(I.getOperand(0).getImm()); uint32_t MemSem = static_cast(getMemSemantics(AO)); - auto MemSemConstant = buildI32Constant(MemSem, I); - Register MemSemReg = MemSemConstant.first; - bool Result = MemSemConstant.second; + Register MemSemReg = buildI32Constant(MemSem, I); SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm()); uint32_t Scope = static_cast( getMemScope(GR.CurMF->getFunction().getContext(), Ord)); - auto ScopeConstant = buildI32Constant(Scope, I); - Register ScopeReg = ScopeConstant.first; - Result &= ScopeConstant.second; + Register ScopeReg = buildI32Constant(Scope, I); MachineBasicBlock &BB = *I.getParent(); - return Result && - BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemoryBarrier)) - .addUse(ScopeReg) - .addUse(MemSemReg) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemoryBarrier)) + .addUse(ScopeReg) + .addUse(MemSemReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectOverflowArith(Register ResVReg, @@ -1926,7 +2000,7 @@ bool SPIRVInstructionSelector::selectOverflowArith(Register ResVReg, .addUse(GR.getSPIRVTypeID(StructType)); for (unsigned i = I.getNumDefs(); i < I.getNumOperands(); ++i) MIB.addUse(I.getOperand(i).getReg()); - bool Result = MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); // Build instructions to extract fields of the instruction's result. // A new virtual register to store the higher part of the result struct. Register HigherVReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); @@ -1938,21 +2012,21 @@ bool SPIRVInstructionSelector::selectOverflowArith(Register ResVReg, .addUse(GR.getSPIRVTypeID(ResType)) .addUse(StructVReg) .addImm(i); - Result &= MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); } // Build boolean value from the higher part. - return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) - .addDef(I.getOperand(1).getReg()) - .addUse(BoolTypeReg) - .addUse(HigherVReg) - .addUse(ZeroReg) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) + .addDef(I.getOperand(1).getReg()) + .addUse(BoolTypeReg) + .addUse(HigherVReg) + .addUse(ZeroReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { - bool Result = true; Register ScopeReg; Register MemSemEqReg; Register MemSemNeqReg; @@ -1962,25 +2036,19 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg, const MachineMemOperand *MemOp = *I.memoperands_begin(); unsigned Scope = static_cast(getMemScope( GR.CurMF->getFunction().getContext(), MemOp->getSyncScopeID())); - auto ScopeConstant = buildI32Constant(Scope, I); - ScopeReg = ScopeConstant.first; - Result &= ScopeConstant.second; + ScopeReg = buildI32Constant(Scope, I); unsigned ScSem = static_cast( getMemSemanticsForStorageClass(GR.getPointerStorageClass(Ptr))); AtomicOrdering AO = MemOp->getSuccessOrdering(); unsigned MemSemEq = static_cast(getMemSemantics(AO)) | ScSem; - auto MemSemEqConstant = buildI32Constant(MemSemEq, I); - MemSemEqReg = MemSemEqConstant.first; - Result &= MemSemEqConstant.second; + Register MemSemEqReg = buildI32Constant(MemSemEq, I); AtomicOrdering FO = MemOp->getFailureOrdering(); unsigned MemSemNeq = static_cast(getMemSemantics(FO)) | ScSem; if (MemSemEq == MemSemNeq) MemSemNeqReg = MemSemEqReg; else { - auto MemSemNeqConstant = buildI32Constant(MemSemEq, I); - MemSemNeqReg = MemSemNeqConstant.first; - Result &= MemSemNeqConstant.second; + MemSemNeqReg = buildI32Constant(MemSemEq, I); } } else { ScopeReg = I.getOperand(5).getReg(); @@ -1993,41 +2061,40 @@ bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg, SPIRVType *SpvValTy = GR.getSPIRVTypeForVReg(Val); Register ACmpRes = createVirtualRegister(SpvValTy, &GR, MRI, *I.getMF()); const DebugLoc &DL = I.getDebugLoc(); - Result &= - BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange)) - .addDef(ACmpRes) - .addUse(GR.getSPIRVTypeID(SpvValTy)) - .addUse(Ptr) - .addUse(ScopeReg) - .addUse(MemSemEqReg) - .addUse(MemSemNeqReg) - .addUse(Val) - .addUse(Cmp) - .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange)) + .addDef(ACmpRes) + .addUse(GR.getSPIRVTypeID(SpvValTy)) + .addUse(Ptr) + .addUse(ScopeReg) + .addUse(MemSemEqReg) + .addUse(MemSemNeqReg) + .addUse(Val) + .addUse(Cmp) + .constrainAllUses(TII, TRI, RBI); SPIRVType *BoolTy = GR.getOrCreateSPIRVBoolType(I, TII); Register CmpSuccReg = createVirtualRegister(BoolTy, &GR, MRI, *I.getMF()); - Result &= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual)) - .addDef(CmpSuccReg) - .addUse(GR.getSPIRVTypeID(BoolTy)) - .addUse(ACmpRes) - .addUse(Cmp) - .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual)) + .addDef(CmpSuccReg) + .addUse(GR.getSPIRVTypeID(BoolTy)) + .addUse(ACmpRes) + .addUse(Cmp) + .constrainAllUses(TII, TRI, RBI); Register TmpReg = createVirtualRegister(ResType, &GR, MRI, *I.getMF()); - Result &= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) - .addDef(TmpReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(ACmpRes) - .addUse(GR.getOrCreateUndef(I, ResType, TII)) - .addImm(0) - .constrainAllUses(TII, TRI, RBI); - return Result && - BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(CmpSuccReg) - .addUse(TmpReg) - .addImm(1) - .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) + .addDef(TmpReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(ACmpRes) + .addUse(GR.getOrCreateUndef(I, ResType, TII)) + .addImm(0) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(CmpSuccReg) + .addUse(TmpReg) + .addImm(1) + .constrainAllUses(TII, TRI, RBI); + return true; } static bool isUSMStorageClass(SPIRV::StorageClass::StorageClass SC) { @@ -2130,18 +2197,18 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg, // be addressed in the emit-intrinsic step to infer a correct // OpConstantComposite type. if (SpecOpcode) { - return buildSpecConstantOp(I, ResVReg, SrcPtr, - getUcharPtrTypeReg(I, DstSC), SpecOpcode) + buildSpecConstantOp(I, ResVReg, SrcPtr, getUcharPtrTypeReg(I, DstSC), + SpecOpcode) .constrainAllUses(TII, TRI, RBI); } else if (isGenericCastablePtr(SrcSC) && isGenericCastablePtr(DstSC)) { MachineInstrBuilder MIB = buildConstGenericPtr(I, SrcPtr, SrcPtrTy); - return MIB.constrainAllUses(TII, TRI, RBI) && - buildSpecConstantOp( - I, ResVReg, MIB->getOperand(0).getReg(), - getUcharPtrTypeReg(I, DstSC), - static_cast(SPIRV::Opcode::GenericCastToPtr)) - .constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + buildSpecConstantOp( + I, ResVReg, MIB->getOperand(0).getReg(), getUcharPtrTypeReg(I, DstSC), + static_cast(SPIRV::Opcode::GenericCastToPtr)) + .constrainAllUses(TII, TRI, RBI); } + return true; } // don't generate a cast between identical storage classes @@ -2165,16 +2232,17 @@ bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg, SPIRVType *GenericPtrTy = GR.changePointerStorageClass(SrcPtrTy, SPIRV::StorageClass::Generic, I); Register Tmp = createVirtualRegister(GenericPtrTy, &GR, MRI, MRI->getMF()); - bool Result = BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric)) - .addDef(Tmp) - .addUse(GR.getSPIRVTypeID(GenericPtrTy)) - .addUse(SrcPtr) - .constrainAllUses(TII, TRI, RBI); - return Result && BuildMI(BB, I, DL, TII.get(SPIRV::OpGenericCastToPtr)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Tmp) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric)) + .addDef(Tmp) + .addUse(GR.getSPIRVTypeID(GenericPtrTy)) + .addUse(SrcPtr) + .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, DL, TII.get(SPIRV::OpGenericCastToPtr)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Tmp) + .constrainAllUses(TII, TRI, RBI); + return true; } // Check if instructions from the SPV_INTEL_usm_storage_classes extension may @@ -2345,27 +2413,25 @@ bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg, SpvBoolTy = GR.getOrCreateSPIRVVectorType(SpvBoolTy, NumElts, I, TII); } - bool Result = true; if (!IsBoolTy) { Register ConstZeroReg = IsFloatTy ? buildZerosValF(InputType, I) : buildZerosVal(InputType, I); - Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SpirvNotEqualId)) - .addDef(NotEqualReg) - .addUse(GR.getSPIRVTypeID(SpvBoolTy)) - .addUse(InputRegister) - .addUse(ConstZeroReg) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SpirvNotEqualId)) + .addDef(NotEqualReg) + .addUse(GR.getSPIRVTypeID(SpvBoolTy)) + .addUse(InputRegister) + .addUse(ConstZeroReg) + .constrainAllUses(TII, TRI, RBI); } - if (!IsVectorTy) - return Result; - - return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(OpAnyOrAll)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(SpvBoolScalarTy)) - .addUse(NotEqualReg) - .constrainAllUses(TII, TRI, RBI); + if (IsVectorTy) + BuildMI(BB, I, I.getDebugLoc(), TII.get(OpAnyOrAll)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(SpvBoolScalarTy)) + .addUse(NotEqualReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectAll(Register ResVReg, @@ -2401,12 +2467,13 @@ bool SPIRVInstructionSelector::selectFloatDot(Register ResVReg, assert(EltType->getOpcode() == SPIRV::OpTypeFloat); MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpDot)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpDot)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectIntegerDot(Register ResVReg, @@ -2419,12 +2486,13 @@ bool SPIRVInstructionSelector::selectIntegerDot(Register ResVReg, MachineBasicBlock &BB = *I.getParent(); auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot; - return BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; } // Since pre-1.6 SPIRV has no integer dot implementation, @@ -2442,29 +2510,28 @@ bool SPIRVInstructionSelector::selectIntegerDotExpansion( Register TmpVec = MRI->createVirtualRegister(GR.getRegClass(ResType)); SPIRVType *VecType = GR.getSPIRVTypeForVReg(Vec0); - bool Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulV)) - .addDef(TmpVec) - .addUse(GR.getSPIRVTypeID(VecType)) - .addUse(Vec0) - .addUse(Vec1) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulV)) + .addDef(TmpVec) + .addUse(GR.getSPIRVTypeID(VecType)) + .addUse(Vec0) + .addUse(Vec1) + .constrainAllUses(TII, TRI, RBI); assert(VecType->getOpcode() == SPIRV::OpTypeVector && GR.getScalarOrVectorComponentCount(VecType) > 1 && "dot product requires a vector of at least 2 components"); Register Res = MRI->createVirtualRegister(GR.getRegClass(ResType)); - Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) - .addDef(Res) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(TmpVec) - .addImm(0) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) + .addDef(Res) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(TmpVec) + .addImm(0) + .constrainAllUses(TII, TRI, RBI); for (unsigned i = 1; i < GR.getScalarOrVectorComponentCount(VecType); i++) { Register Elt = MRI->createVirtualRegister(GR.getRegClass(ResType)); - Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) .addDef(Elt) .addUse(GR.getSPIRVTypeID(ResType)) @@ -2476,38 +2543,40 @@ bool SPIRVInstructionSelector::selectIntegerDotExpansion( ? MRI->createVirtualRegister(GR.getRegClass(ResType)) : ResVReg; - Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) - .addDef(Sum) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Res) - .addUse(Elt) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) + .addDef(Sum) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Res) + .addUse(Elt) + .constrainAllUses(TII, TRI, RBI); Res = Sum; } - return Result; + return true; } bool SPIRVInstructionSelector::selectOpIsInf(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsInf)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsInf)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectOpIsNan(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsNan)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsNan)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; } template @@ -2526,19 +2595,21 @@ bool SPIRVInstructionSelector::selectDot4AddPacked(Register ResVReg, auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot; Register Dot = MRI->createVirtualRegister(GR.getRegClass(ResType)); - bool Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp)) - .addDef(Dot) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(X) - .addUse(Y) - .constrainAllUses(TII, TRI, RBI); + auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp)) + .addDef(Dot) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(X) + .addUse(Y); + MIB.addImm(SPIRV::BuiltIn::PackedVectorFormat4x8Bit); + MIB.constrainAllUses(TII, TRI, RBI); - return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Dot) - .addUse(Acc) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Dot) + .addUse(Acc) + .constrainAllUses(TII, TRI, RBI); + return true; } // Since pre-1.6 SPIRV has no DotProductInput4x8BitPacked implementation, @@ -2553,8 +2624,6 @@ bool SPIRVInstructionSelector::selectDot4AddPackedExpansion( assert(I.getOperand(4).isReg()); MachineBasicBlock &BB = *I.getParent(); - bool Result = true; - Register Acc = I.getOperand(2).getReg(); Register X = I.getOperand(3).getReg(); Register Y = I.getOperand(4).getReg(); @@ -2568,60 +2637,57 @@ bool SPIRVInstructionSelector::selectDot4AddPackedExpansion( for (unsigned i = 0; i < 4; i++) { // A[i] Register AElt = MRI->createVirtualRegister(&SPIRV::IDRegClass); - Result &= - BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) - .addDef(AElt) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(X) - .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII, ZeroAsNull)) - .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull)) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) + .addDef(AElt) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(X) + .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII, ZeroAsNull)) + .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull)) + .constrainAllUses(TII, TRI, RBI); // B[i] Register BElt = MRI->createVirtualRegister(&SPIRV::IDRegClass); - Result &= - BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) - .addDef(BElt) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Y) - .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII, ZeroAsNull)) - .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull)) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) + .addDef(BElt) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Y) + .addUse(GR.getOrCreateConstInt(i * 8, I, EltType, TII, ZeroAsNull)) + .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull)) + .constrainAllUses(TII, TRI, RBI); // A[i] * B[i] Register Mul = MRI->createVirtualRegister(&SPIRV::IDRegClass); - Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulS)) - .addDef(Mul) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(AElt) - .addUse(BElt) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIMulS)) + .addDef(Mul) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(AElt) + .addUse(BElt) + .constrainAllUses(TII, TRI, RBI); // Discard 24 highest-bits so that stored i32 register is i8 equivalent Register MaskMul = MRI->createVirtualRegister(&SPIRV::IDRegClass); - Result &= - BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) - .addDef(MaskMul) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Mul) - .addUse(GR.getOrCreateConstInt(0, I, EltType, TII, ZeroAsNull)) - .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull)) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(ExtractOp)) + .addDef(MaskMul) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Mul) + .addUse(GR.getOrCreateConstInt(0, I, EltType, TII, ZeroAsNull)) + .addUse(GR.getOrCreateConstInt(8, I, EltType, TII, ZeroAsNull)) + .constrainAllUses(TII, TRI, RBI); // Acc = Acc + A[i] * B[i] Register Sum = i < 3 ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg; - Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) - .addDef(Sum) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Acc) - .addUse(MaskMul) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) + .addDef(Sum) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Acc) + .addUse(MaskMul) + .constrainAllUses(TII, TRI, RBI); Acc = Sum; } - return Result; + return true; } /// Transform saturate(x) to clamp(x, 0.0f, 1.0f) as SPIRV @@ -2635,7 +2701,7 @@ bool SPIRVInstructionSelector::selectSaturate(Register ResVReg, Register VZero = buildZerosValF(ResType, I); Register VOne = buildOnesValF(ResType, I); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addImm(static_cast(SPIRV::InstructionSet::GLSL_std_450)) @@ -2644,6 +2710,7 @@ bool SPIRVInstructionSelector::selectSaturate(Register ResVReg, .addUse(VZero) .addUse(VOne) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectSign(Register ResVReg, @@ -2671,7 +2738,6 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg; - bool Result = BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst)) .addDef(SignReg) .addUse(GR.getSPIRVTypeID(InputType)) @@ -2682,14 +2748,14 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, if (NeedsConversion) { auto ConvertOpcode = IsFloatTy ? SPIRV::OpConvertFToS : SPIRV::OpSConvert; - Result &= BuildMI(*I.getParent(), I, DL, TII.get(ConvertOpcode)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(SignReg) - .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, DL, TII.get(ConvertOpcode)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(SignReg) + .constrainAllUses(TII, TRI, RBI); } - return Result; + return true; } bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg, @@ -2709,7 +2775,8 @@ bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg, BMI.addUse(I.getOperand(J).getReg()); } - return BMI.constrainAllUses(TII, TRI, RBI); + BMI.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectWaveActiveCountBits( @@ -2718,21 +2785,22 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits( SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII); SPIRVType *BallotType = GR.getOrCreateSPIRVVectorType(IntTy, 4, I, TII); Register BallotReg = MRI->createVirtualRegister(GR.getRegClass(BallotType)); - bool Result = selectWaveOpInst(BallotReg, BallotType, I, - SPIRV::OpGroupNonUniformBallot); + if (!selectWaveOpInst(BallotReg, BallotType, I, + SPIRV::OpGroupNonUniformBallot)) + return false; MachineBasicBlock &BB = *I.getParent(); - Result &= BuildMI(BB, I, I.getDebugLoc(), - TII.get(SPIRV::OpGroupNonUniformBallotBitCount)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, - TII, !STI.isShader())) - .addImm(SPIRV::GroupOperation::Reduce) - .addUse(BallotReg) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), + TII.get(SPIRV::OpGroupNonUniformBallotBitCount)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII, + !STI.isShader())) + .addImm(SPIRV::GroupOperation::Reduce) + .addUse(BallotReg) + .constrainAllUses(TII, TRI, RBI); - return Result; + return true; } bool SPIRVInstructionSelector::selectWavePrefixBitCount( @@ -2842,7 +2910,7 @@ bool SPIRVInstructionSelector::selectWaveReduce( SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII); const unsigned Opcode = PickOpcode(InputRegister, IsUnsigned); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII, @@ -2850,17 +2918,57 @@ bool SPIRVInstructionSelector::selectWaveReduce( .addImm(SPIRV::GroupOperation::Reduce) .addUse(I.getOperand(2).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; +} + +bool SPIRVInstructionSelector::selectWaveExclusiveScanSum( + Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { + return selectWaveExclusiveScan(ResVReg, ResType, I, /*IsUnsigned*/ false, + [&](Register InputRegister, bool IsUnsigned) { + bool IsFloatTy = GR.isScalarOrVectorOfType( + InputRegister, SPIRV::OpTypeFloat); + return IsFloatTy + ? SPIRV::OpGroupNonUniformFAdd + : SPIRV::OpGroupNonUniformIAdd; + }); +} + +template +bool SPIRVInstructionSelector::selectWaveExclusiveScan( + Register ResVReg, const SPIRVType *ResType, MachineInstr &I, + bool IsUnsigned, PickOpcodeFn &&PickOpcode) const { + assert(I.getNumOperands() == 3); + assert(I.getOperand(2).isReg()); + MachineBasicBlock &BB = *I.getParent(); + Register InputRegister = I.getOperand(2).getReg(); + SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister); + + if (!InputType) + report_fatal_error("Input Type could not be determined."); + + SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII); + const unsigned Opcode = PickOpcode(InputRegister, IsUnsigned); + BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII, + !STI.isShader())) + .addImm(SPIRV::GroupOperation::ExclusiveScan) + .addUse(I.getOperand(2).getReg()) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitReverse)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitReverse)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(1).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectFreeze(Register ResVReg, @@ -2897,10 +3005,11 @@ bool SPIRVInstructionSelector::selectFreeze(Register ResVReg, DestOpCode = TargetOpcode::COPY; Reg = OpReg; } - return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DestOpCode)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DestOpCode)) .addDef(I.getOperand(0).getReg()) .addUse(Reg) .constrainAllUses(TII, TRI, RBI); + return true; } return false; } @@ -2937,7 +3046,8 @@ bool SPIRVInstructionSelector::selectBuildVector(Register ResVReg, .addUse(GR.getSPIRVTypeID(ResType)); for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i) MIB.addUse(I.getOperand(i).getReg()); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg, @@ -2971,7 +3081,8 @@ bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg, .addUse(GR.getSPIRVTypeID(ResType)); for (unsigned i = 0; i < N; ++i) MIB.addUse(OpReg); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectDiscard(Register ResVReg, @@ -2994,8 +3105,9 @@ bool SPIRVInstructionSelector::selectDiscard(Register ResVReg, } MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectCmp(Register ResVReg, @@ -3007,13 +3119,14 @@ bool SPIRVInstructionSelector::selectCmp(Register ResVReg, assert(GR.getSPIRVTypeForVReg(Cmp0)->getOpcode() == GR.getSPIRVTypeForVReg(Cmp1)->getOpcode() && "CMP operands should have the same type"); - return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CmpOpc)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CmpOpc)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(Cmp0) .addUse(Cmp1) .setMIFlags(I.getFlags()) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectICmp(Register ResVReg, @@ -3032,7 +3145,7 @@ bool SPIRVInstructionSelector::selectICmp(Register ResVReg, return selectCmp(ResVReg, ResType, CmpOpc, I); } -std::pair +Register SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I, const SPIRVType *ResType) const { Type *LLVMTy = IntegerType::get(GR.CurMF->getFunction().getContext(), 32); @@ -3041,7 +3154,6 @@ SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I, // Find a constant in DT or build a new one. auto ConstInt = ConstantInt::get(LLVMTy, Val); Register NewReg = GR.find(ConstInt, GR.CurMF); - bool Result = true; if (!NewReg.isValid()) { NewReg = MRI->createGenericVirtualRegister(LLT::scalar(64)); MachineBasicBlock &BB = *I.getParent(); @@ -3054,10 +3166,10 @@ SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I, .addDef(NewReg) .addUse(GR.getSPIRVTypeID(SpvI32Ty)) .addImm(APInt(32, Val).getZExtValue()); - Result &= constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); + constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); GR.add(ConstInt, MI); } - return {NewReg, Result}; + return NewReg; } bool SPIRVInstructionSelector::selectFCmp(Register ResVReg, @@ -3149,8 +3261,8 @@ Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes, APInt One = AllOnes ? APInt::getAllOnes(BitWidth) : APInt::getOneBitSet(BitWidth, 0); if (ResType->getOpcode() == SPIRV::OpTypeVector) - return GR.getOrCreateConstVector(One.getZExtValue(), I, ResType, TII); - return GR.getOrCreateConstInt(One.getZExtValue(), I, ResType, TII); + return GR.getOrCreateConstVector(One, I, ResType, TII); + return GR.getOrCreateConstInt(One, I, ResType, TII); } bool SPIRVInstructionSelector::selectSelect(Register ResVReg, @@ -3188,13 +3300,14 @@ bool SPIRVInstructionSelector::selectSelect(Register ResVReg, Opcode = IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond; } } - return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(1).getReg()) .addUse(SelectFirstArg) .addUse(SelectSecondArg) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectSelectDefaultArgs(Register ResVReg, @@ -3208,13 +3321,14 @@ bool SPIRVInstructionSelector::selectSelectDefaultArgs(Register ResVReg, GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool); unsigned Opcode = IsScalarBool ? SPIRV::OpSelectSISCond : SPIRV::OpSelectVIVCond; - return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(1).getReg()) .addUse(OneReg) .addUse(ZeroReg) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectIToF(Register ResVReg, @@ -3271,24 +3385,23 @@ bool SPIRVInstructionSelector::selectSUCmp(Register ResVReg, Register IsLessEqReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); MRI->setType(IsLessEqReg, LLT::scalar(64)); GR.assignSPIRVTypeToVReg(ResType, IsLessEqReg, MIRBuilder.getMF()); - bool Result = BuildMI(BB, I, I.getDebugLoc(), - TII.get(IsSigned ? SPIRV::OpSLessThanEqual - : SPIRV::OpULessThanEqual)) - .addDef(IsLessEqReg) - .addUse(BoolTypeReg) - .addUse(I.getOperand(1).getReg()) - .addUse(I.getOperand(2).getReg()) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), + TII.get(IsSigned ? SPIRV::OpSLessThanEqual : SPIRV::OpULessThanEqual)) + .addDef(IsLessEqReg) + .addUse(BoolTypeReg) + .addUse(I.getOperand(1).getReg()) + .addUse(I.getOperand(2).getReg()) + .constrainAllUses(TII, TRI, RBI); Register IsLessReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); MRI->setType(IsLessReg, LLT::scalar(64)); GR.assignSPIRVTypeToVReg(ResType, IsLessReg, MIRBuilder.getMF()); - Result &= BuildMI(BB, I, I.getDebugLoc(), - TII.get(IsSigned ? SPIRV::OpSLessThan : SPIRV::OpULessThan)) - .addDef(IsLessReg) - .addUse(BoolTypeReg) - .addUse(I.getOperand(1).getReg()) - .addUse(I.getOperand(2).getReg()) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), + TII.get(IsSigned ? SPIRV::OpSLessThan : SPIRV::OpULessThan)) + .addDef(IsLessReg) + .addUse(BoolTypeReg) + .addUse(I.getOperand(1).getReg()) + .addUse(I.getOperand(2).getReg()) + .constrainAllUses(TII, TRI, RBI); // Build selects. Register ResTypeReg = GR.getSPIRVTypeID(ResType); Register NegOneOrZeroReg = @@ -3297,20 +3410,21 @@ bool SPIRVInstructionSelector::selectSUCmp(Register ResVReg, GR.assignSPIRVTypeToVReg(ResType, NegOneOrZeroReg, MIRBuilder.getMF()); unsigned SelectOpcode = N > 1 ? SPIRV::OpSelectVIVCond : SPIRV::OpSelectSISCond; - Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode)) - .addDef(NegOneOrZeroReg) - .addUse(ResTypeReg) - .addUse(IsLessReg) - .addUse(buildOnesVal(true, ResType, I)) // -1 - .addUse(buildZerosVal(ResType, I)) - .constrainAllUses(TII, TRI, RBI); - return Result & BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode)) - .addDef(ResVReg) - .addUse(ResTypeReg) - .addUse(IsLessEqReg) - .addUse(NegOneOrZeroReg) // -1 or 0 - .addUse(buildOnesVal(false, ResType, I)) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode)) + .addDef(NegOneOrZeroReg) + .addUse(ResTypeReg) + .addUse(IsLessReg) + .addUse(buildOnesVal(true, ResType, I)) // -1 + .addUse(buildZerosVal(ResType, I)) + .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SelectOpcode)) + .addDef(ResVReg) + .addUse(ResTypeReg) + .addUse(IsLessEqReg) + .addUse(NegOneOrZeroReg) // -1 or 0 + .addUse(buildOnesVal(false, ResType, I)) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectIntToBool(Register IntReg, @@ -3325,18 +3439,19 @@ bool SPIRVInstructionSelector::selectIntToBool(Register IntReg, Register Zero = buildZerosVal(IntTy, I); Register One = buildOnesVal(false, IntTy, I); MachineBasicBlock &BB = *I.getParent(); - bool Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) - .addDef(BitIntReg) - .addUse(GR.getSPIRVTypeID(IntTy)) - .addUse(IntReg) - .addUse(One) - .constrainAllUses(TII, TRI, RBI); - return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(BoolTy)) - .addUse(BitIntReg) - .addUse(Zero) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) + .addDef(BitIntReg) + .addUse(GR.getSPIRVTypeID(IntTy)) + .addUse(IntReg) + .addUse(One) + .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(BoolTy)) + .addUse(BitIntReg) + .addUse(Zero) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectTrunc(Register ResVReg, @@ -3369,7 +3484,7 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg, Reg = GR.getOrCreateConstFP(I.getOperand(1).getFPImm()->getValue(), I, ResType, TII, !STI.isShader()); } else { - Reg = GR.getOrCreateConstInt(I.getOperand(1).getCImm()->getZExtValue(), I, + Reg = GR.getOrCreateConstInt(I.getOperand(1).getCImm()->getValue(), I, ResType, TII, !STI.isShader()); } return Reg == ResVReg ? true : BuildCOPY(ResVReg, Reg, I); @@ -3378,10 +3493,11 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg, bool SPIRVInstructionSelector::selectOpUndef(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { - return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg, @@ -3397,7 +3513,8 @@ bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg, .addUse(I.getOperand(2).getReg()); for (unsigned i = 4; i < I.getNumOperands(); i++) MIB.addImm(foldImm(I.getOperand(i), MRI)); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg, @@ -3407,9 +3524,8 @@ bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg, StringRef ResName; if (GR.findValueAttrs(&I, MaybeResTy, ResName) && MaybeResTy != GR.getTypeForSPIRVType(ResType)) { - assert(!MaybeResTy || - MaybeResTy->isAggregateType() && - "Expected aggregate type for extractv instruction"); + assert((!MaybeResTy || MaybeResTy->isAggregateType()) && + "Expected aggregate type for extractv instruction"); ResType = GR.getOrCreateSPIRVType(MaybeResTy, I, SPIRV::AccessQualifier::ReadWrite, false); GR.assignSPIRVTypeToVReg(ResType, ResVReg, *I.getMF()); @@ -3421,7 +3537,8 @@ bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg, .addUse(I.getOperand(2).getReg()); for (unsigned i = 3; i < I.getNumOperands(); i++) MIB.addImm(foldImm(I.getOperand(i), MRI)); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg, @@ -3430,13 +3547,14 @@ bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg, if (getImm(I.getOperand(4), MRI)) return selectInsertVal(ResVReg, ResType, I); MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorInsertDynamic)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorInsertDynamic)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .addUse(I.getOperand(4).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg, @@ -3445,12 +3563,13 @@ bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg, if (getImm(I.getOperand(3), MRI)) return selectExtractVal(ResVReg, ResType, I); MachineBasicBlock &BB = *I.getParent(); - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorExtractDynamic)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorExtractDynamic)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectGEP(Register ResVReg, @@ -3485,13 +3604,13 @@ bool SPIRVInstructionSelector::selectGEP(Register ResVReg, : 4; for (unsigned i = StartingIndex; i < I.getNumExplicitOperands(); ++i) Res.addUse(I.getOperand(i).getReg()); - return Res.constrainAllUses(TII, TRI, RBI); + Res.constrainAllUses(TII, TRI, RBI); + return true; } // Maybe wrap a value into OpSpecConstantOp bool SPIRVInstructionSelector::wrapIntoSpecConstantOp( MachineInstr &I, SmallVector &CompositeArgs) const { - bool Result = true; unsigned Lim = I.getNumExplicitOperands(); for (unsigned i = I.getNumExplicitDefs() + 1; i < Lim; ++i) { Register OpReg = I.getOperand(i).getReg(); @@ -3526,11 +3645,9 @@ bool SPIRVInstructionSelector::wrapIntoSpecConstantOp( .addImm(static_cast(SPIRV::Opcode::Bitcast)) .addUse(OpReg); GR.add(OpDefine, MIB); - Result = MIB.constrainAllUses(TII, TRI, RBI); - if (!Result) - break; + MIB.constrainAllUses(TII, TRI, RBI); } - return Result; + return true; } bool SPIRVInstructionSelector::selectDerivativeInst( @@ -3564,24 +3681,22 @@ bool SPIRVInstructionSelector::selectDerivativeInst( Register ConvertToVReg = MRI->createVirtualRegister(RegClass); Register DpdOpVReg = MRI->createVirtualRegister(RegClass); - bool Result = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) .addDef(ConvertToVReg) .addUse(GR.getSPIRVTypeID(F32ConvertTy)) .addUse(SrcReg) .constrainAllUses(TII, TRI, RBI); - Result &= BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode)) - .addDef(DpdOpVReg) - .addUse(GR.getSPIRVTypeID(F32ConvertTy)) - .addUse(ConvertToVReg) - .constrainAllUses(TII, TRI, RBI); - Result &= + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode)) + .addDef(DpdOpVReg) + .addUse(GR.getSPIRVTypeID(F32ConvertTy)) + .addUse(ConvertToVReg) + .constrainAllUses(TII, TRI, RBI); BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(DpdOpVReg) .constrainAllUses(TII, TRI, RBI); - return Result; + return true; } bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, @@ -3620,7 +3735,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, : nullptr; assert(MI); Register GVarVReg = MI->getOperand(0).getReg(); - bool Res = selectGlobalValue(GVarVReg, *MI, Init); + if (!selectGlobalValue(GVarVReg, *MI, Init)) + return false; // We violate SSA form by inserting OpVariable and still having a gMIR // instruction %vreg = G_GLOBAL_VALUE @gvar. We need to fix this by erasing // the duplicated definition. @@ -3628,13 +3744,14 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, GR.invalidateMachineInstr(MI); MI->removeFromParent(); } - return Res; + return true; } case Intrinsic::spv_undef: { auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } case Intrinsic::spv_const_composite: { // If no values are attached, the composite is null constant. @@ -3653,15 +3770,15 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, GR.getSPIRVTypeID(ResType)); for (auto *Instr : Instructions) { Instr->setDebugLoc(I.getDebugLoc()); - if (!constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI)) - return false; + constrainSelectedInstRegOperands(*Instr, TII, TRI, RBI); } return true; } else { auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } } case Intrinsic::spv_assign_name: { @@ -3671,7 +3788,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, i < I.getNumExplicitOperands(); ++i) { MIB.addImm(I.getOperand(i).getImm()); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } case Intrinsic::spv_switch: { auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSwitch)); @@ -3685,7 +3803,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, else llvm_unreachable("Unexpected OpSwitch operand"); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } case Intrinsic::spv_loop_merge: { auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoopMerge)); @@ -3695,7 +3814,16 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, else MIB.addImm(foldImm(I.getOperand(i), MRI)); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; + } + case Intrinsic::spv_loop_control_intel: { + auto MIB = + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpLoopControlINTEL)); + for (unsigned J = 1; J < I.getNumExplicitOperands(); ++J) + MIB.addImm(foldImm(I.getOperand(J), MRI)); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } case Intrinsic::spv_selection_merge: { auto MIB = @@ -3704,41 +3832,47 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, "operand 1 to spv_selection_merge must be a basic block"); MIB.addMBB(I.getOperand(1).getMBB()); MIB.addImm(getSelectionOperandForImm(I.getOperand(2).getImm())); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } case Intrinsic::spv_cmpxchg: return selectAtomicCmpXchg(ResVReg, ResType, I); case Intrinsic::spv_unreachable: - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUnreachable)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUnreachable)) .constrainAllUses(TII, TRI, RBI); + return true; case Intrinsic::spv_alloca: return selectFrameIndex(ResVReg, ResType, I); case Intrinsic::spv_alloca_array: return selectAllocaArray(ResVReg, ResType, I); case Intrinsic::spv_assume: - if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAssumeTrueKHR)) + if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) { + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAssumeTrueKHR)) .addUse(I.getOperand(1).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; + } break; case Intrinsic::spv_expect: - if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) - return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExpectKHR)) + if (STI.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) { + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExpectKHR)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .addUse(I.getOperand(3).getReg()) .constrainAllUses(TII, TRI, RBI); + return true; + } break; case Intrinsic::arithmetic_fence: - if (STI.canUseExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence)) - return BuildMI(BB, I, I.getDebugLoc(), - TII.get(SPIRV::OpArithmeticFenceEXT)) + if (STI.canUseExtension(SPIRV::Extension::SPV_EXT_arithmetic_fence)) { + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpArithmeticFenceEXT)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(I.getOperand(2).getReg()) .constrainAllUses(TII, TRI, RBI); - else + return true; + } else return BuildCOPY(ResVReg, I.getOperand(2).getReg(), I); break; case Intrinsic::spv_thread_id: @@ -3860,21 +3994,16 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, case Intrinsic::spv_firstbitlow: // There is no CL equivlent of FindILsb return selectFirstBitLow(ResVReg, ResType, I); case Intrinsic::spv_group_memory_barrier_with_group_sync: { - bool Result = true; - auto MemSemConstant = + Register MemSemReg = buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I); - Register MemSemReg = MemSemConstant.first; - Result &= MemSemConstant.second; - auto ScopeConstant = buildI32Constant(SPIRV::Scope::Workgroup, I); - Register ScopeReg = ScopeConstant.first; - Result &= ScopeConstant.second; + Register ScopeReg = buildI32Constant(SPIRV::Scope::Workgroup, I); MachineBasicBlock &BB = *I.getParent(); - return Result && - BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier)) - .addUse(ScopeReg) - .addUse(ScopeReg) - .addUse(MemSemReg) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier)) + .addUse(ScopeReg) + .addUse(ScopeReg) + .addUse(MemSemReg) + .constrainAllUses(TII, TRI, RBI); + return true; } case Intrinsic::spv_generic_cast_to_ptr_explicit: { Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 1).getReg(); @@ -3883,13 +4012,13 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, if (!isGenericCastablePtr(ResSC)) report_fatal_error("The target storage class is not castable from the " "Generic storage class"); - return BuildMI(BB, I, I.getDebugLoc(), - TII.get(SPIRV::OpGenericCastToPtrExplicit)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpGenericCastToPtrExplicit)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(PtrReg) .addImm(ResSC) .constrainAllUses(TII, TRI, RBI); + return true; } case Intrinsic::spv_lifetime_start: case Intrinsic::spv_lifetime_end: { @@ -3899,10 +4028,11 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 2).getReg(); if (Size == -1) Size = 0; - return BuildMI(BB, I, I.getDebugLoc(), TII.get(Op)) + BuildMI(BB, I, I.getDebugLoc(), TII.get(Op)) .addUse(PtrReg) .addImm(Size) .constrainAllUses(TII, TRI, RBI); + return true; } case Intrinsic::spv_saturate: return selectSaturate(ResVReg, ResType, I); @@ -3938,6 +4068,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, case Intrinsic::spv_wave_readlane: return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformShuffle); + case Intrinsic::spv_wave_prefix_sum: + return selectWaveExclusiveScanSum(ResVReg, ResType, I); case Intrinsic::spv_step: return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step); case Intrinsic::spv_radians: @@ -4090,47 +4222,34 @@ bool SPIRVInstructionSelector::selectUpdateCounter(Register &ResVReg, SPIRVType *IntPtrType = GR.getOrCreateSPIRVPointerType( LLVMIntType, MIRBuilder, SPIRV::StorageClass::StorageBuffer); - auto Zero = buildI32Constant(0, I); - if (!Zero.second) - return false; + Register Zero = buildI32Constant(0, I); Register PtrToCounter = MRI->createVirtualRegister(GR.getRegClass(IntPtrType)); - if (!BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII.get(SPIRV::OpAccessChain)) - .addDef(PtrToCounter) - .addUse(GR.getSPIRVTypeID(IntPtrType)) - .addUse(CounterHandleReg) - .addUse(Zero.first) - .constrainAllUses(TII, TRI, RBI)) { - return false; - } + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAccessChain)) + .addDef(PtrToCounter) + .addUse(GR.getSPIRVTypeID(IntPtrType)) + .addUse(CounterHandleReg) + .addUse(Zero) + .constrainAllUses(TII, TRI, RBI); // For UAV/SSBO counters, the scope is Device. The counter variable is not // used as a flag. So the memory semantics can be None. - auto Scope = buildI32Constant(SPIRV::Scope::Device, I); - if (!Scope.second) - return false; - auto Semantics = buildI32Constant(SPIRV::MemorySemantics::None, I); - if (!Semantics.second) - return false; + Register Scope = buildI32Constant(SPIRV::Scope::Device, I); + Register Semantics = buildI32Constant(SPIRV::MemorySemantics::None, I); int64_t IncrVal = getIConstValSext(IncrReg, MRI); - auto Incr = buildI32Constant(static_cast(IncrVal), I); - if (!Incr.second) - return false; + Register Incr = buildI32Constant(static_cast(IncrVal), I); Register AtomicRes = MRI->createVirtualRegister(GR.getRegClass(ResType)); - if (!BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAtomicIAdd)) - .addDef(AtomicRes) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(PtrToCounter) - .addUse(Scope.first) - .addUse(Semantics.first) - .addUse(Incr.first) - .constrainAllUses(TII, TRI, RBI)) { - return false; - } + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAtomicIAdd)) + .addDef(AtomicRes) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(PtrToCounter) + .addUse(Scope) + .addUse(Semantics) + .addUse(Incr) + .constrainAllUses(TII, TRI, RBI); if (IncrVal >= 0) { return BuildCOPY(ResVReg, AtomicRes, I); } @@ -4140,12 +4259,13 @@ bool SPIRVInstructionSelector::selectUpdateCounter(Register &ResVReg, // to the same atomic intrinsic which returns the value *before* the // operation. So for decrements (negative IncrVal), we must subtract the // increment value from the result to get the post-decrement value. - return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(AtomicRes) - .addUse(Incr.first) + .addUse(Incr) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectReadImageIntrinsic( Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const { @@ -4209,14 +4329,12 @@ bool SPIRVInstructionSelector::selectSampleIntrinsic(Register &ResVReg, Register SampledImageReg = MRI->createVirtualRegister(GR.getRegClass(SampledImageType)); - bool Succeed = BuildMI(*I.getParent(), I, Loc, TII.get(SPIRV::OpSampledImage)) - .addDef(SampledImageReg) - .addUse(GR.getSPIRVTypeID(SampledImageType)) - .addUse(NewImageReg) - .addUse(NewSamplerReg) - .constrainAllUses(TII, TRI, RBI); - if (!Succeed) - return false; + BuildMI(*I.getParent(), I, Loc, TII.get(SPIRV::OpSampledImage)) + .addDef(SampledImageReg) + .addUse(GR.getSPIRVTypeID(SampledImageType)) + .addUse(NewImageReg) + .addUse(NewSamplerReg) + .constrainAllUses(TII, TRI, RBI); auto MIB = BuildMI(*I.getParent(), I, Loc, TII.get(SPIRV::OpImageSampleImplicitLod)) @@ -4242,7 +4360,8 @@ bool SPIRVInstructionSelector::selectSampleIntrinsic(Register &ResVReg, MIB.addUse(*ClampReg); } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::generateImageReadOrFetch( @@ -4271,7 +4390,8 @@ bool SPIRVInstructionSelector::generateImageReadOrFetch( if (IsSignedInteger) BMI.addImm(0x1000); // SignExtend - return BMI.constrainAllUses(TII, TRI, RBI); + BMI.constrainAllUses(TII, TRI, RBI); + return true; } SPIRVType *ReadType = widenTypeToVec4(ResType, Pos); @@ -4285,18 +4405,16 @@ bool SPIRVInstructionSelector::generateImageReadOrFetch( .addUse(IdxReg); if (IsSignedInteger) BMI.addImm(0x1000); // SignExtend - bool Succeed = BMI.constrainAllUses(TII, TRI, RBI); - if (!Succeed) - return false; + BMI.constrainAllUses(TII, TRI, RBI); if (ResultSize == 1) { - return BuildMI(*Pos.getParent(), Pos, Loc, - TII.get(SPIRV::OpCompositeExtract)) + BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpCompositeExtract)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(ReadReg) .addImm(0) .constrainAllUses(TII, TRI, RBI); + return true; } return extractSubvector(ResVReg, ResType, ReadReg, Pos); } @@ -4319,14 +4437,14 @@ bool SPIRVInstructionSelector::selectResourceGetPointer( Register IndexReg = I.getOperand(3).getReg(); Register ZeroReg = buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I); - return BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII.get(SPIRV::OpAccessChain)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpAccessChain)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(ResourcePtr) .addUse(ZeroReg) .addUse(IndexReg) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectPushConstantGetPointer( @@ -4399,16 +4517,13 @@ bool SPIRVInstructionSelector::extractSubvector( const TargetRegisterClass *ScalarRegClass = GR.getRegClass(ScalarType); for (uint64_t I = 0; I < ResultSize; I++) { Register ComponentReg = MRI->createVirtualRegister(ScalarRegClass); - bool Succeed = BuildMI(*InsertionPoint.getParent(), InsertionPoint, - InsertionPoint.getDebugLoc(), - TII.get(SPIRV::OpCompositeExtract)) - .addDef(ComponentReg) - .addUse(ScalarType->getOperand(0).getReg()) - .addUse(ReadReg) - .addImm(I) - .constrainAllUses(TII, TRI, RBI); - if (!Succeed) - return false; + BuildMI(*InsertionPoint.getParent(), InsertionPoint, + InsertionPoint.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) + .addDef(ComponentReg) + .addUse(ScalarType->getOperand(0).getReg()) + .addUse(ReadReg) + .addImm(I) + .constrainAllUses(TII, TRI, RBI); ComponentRegisters.emplace_back(ComponentReg); } @@ -4420,7 +4535,8 @@ bool SPIRVInstructionSelector::extractSubvector( for (Register ComponentReg : ComponentRegisters) MIB.addUse(ComponentReg); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectImageWriteIntrinsic( @@ -4443,12 +4559,12 @@ bool SPIRVInstructionSelector::selectImageWriteIntrinsic( Register DataReg = I.getOperand(3).getReg(); assert(GR.getResultType(DataReg)->getOpcode() == SPIRV::OpTypeVector); assert(GR.getScalarOrVectorComponentCount(GR.getResultType(DataReg)) == 4); - return BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII.get(SPIRV::OpImageWrite)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpImageWrite)) .addUse(NewImageReg) .addUse(CoordinateReg) .addUse(DataReg) .constrainAllUses(TII, TRI, RBI); + return true; } Register SPIRVInstructionSelector::buildPointerToResource( @@ -4488,23 +4604,24 @@ bool SPIRVInstructionSelector::selectFirstBitSet16( Register ResVReg, const SPIRVType *ResType, MachineInstr &I, unsigned ExtendOpcode, unsigned BitSetOpcode) const { Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); - bool Result = selectOpWithSrcs(ExtReg, ResType, I, {I.getOperand(2).getReg()}, - ExtendOpcode); + if (!selectOpWithSrcs(ExtReg, ResType, I, {I.getOperand(2).getReg()}, + ExtendOpcode)) + return false; - return Result && - selectFirstBitSet32(ResVReg, ResType, I, ExtReg, BitSetOpcode); + return selectFirstBitSet32(ResVReg, ResType, I, ExtReg, BitSetOpcode); } bool SPIRVInstructionSelector::selectFirstBitSet32( Register ResVReg, const SPIRVType *ResType, MachineInstr &I, Register SrcReg, unsigned BitSetOpcode) const { - return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) .addDef(ResVReg) .addUse(GR.getSPIRVTypeID(ResType)) .addImm(static_cast(SPIRV::InstructionSet::GLSL_std_450)) .addImm(BitSetOpcode) .addUse(SrcReg) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectFirstBitSet64Overflow( @@ -4545,8 +4662,7 @@ bool SPIRVInstructionSelector::selectFirstBitSet64Overflow( .addImm(CurrentComponent) .addImm(CurrentComponent + 1); - if (!MIB.constrainAllUses(TII, TRI, RBI)) - return false; + MIB.constrainAllUses(TII, TRI, RBI); Register SubVecBitSetReg = MRI->createVirtualRegister(GR.getRegClass(Vec2ResType)); @@ -4649,8 +4765,7 @@ bool SPIRVInstructionSelector::selectFirstBitSet64( MIB.addImm(J); } - if (!MIB.constrainAllUses(TII, TRI, RBI)) - return false; + MIB.constrainAllUses(TII, TRI, RBI); MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle)) @@ -4664,8 +4779,7 @@ bool SPIRVInstructionSelector::selectFirstBitSet64( for (unsigned J = 1; J < ComponentCount * 2; J += 2) { MIB.addImm(J); } - if (!MIB.constrainAllUses(TII, TRI, RBI)) - return false; + MIB.constrainAllUses(TII, TRI, RBI); } // 4. Check the result. When primary bits == -1 use secondary, otherwise use @@ -4786,17 +4900,16 @@ bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg, // there was an allocation size parameter to the allocation instruction // that is not 1 MachineBasicBlock &BB = *I.getParent(); - bool Res = BuildMI(BB, I, I.getDebugLoc(), - TII.get(SPIRV::OpVariableLengthArrayINTEL)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(I.getOperand(2).getReg()) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVariableLengthArrayINTEL)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(I.getOperand(2).getReg()) + .constrainAllUses(TII, TRI, RBI); if (!STI.isShader()) { unsigned Alignment = I.getOperand(3).getImm(); buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::Alignment, {Alignment}); } - return Res; + return true; } bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg, @@ -4805,18 +4918,17 @@ bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg, // Change order of instructions if needed: all OpVariable instructions in a // function must be the first instructions in the first block auto It = getOpVariableMBBIt(I); - bool Res = BuildMI(*It->getParent(), It, It->getDebugLoc(), - TII.get(SPIRV::OpVariable)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addImm(static_cast(SPIRV::StorageClass::Function)) - .constrainAllUses(TII, TRI, RBI); + BuildMI(*It->getParent(), It, It->getDebugLoc(), TII.get(SPIRV::OpVariable)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addImm(static_cast(SPIRV::StorageClass::Function)) + .constrainAllUses(TII, TRI, RBI); if (!STI.isShader()) { unsigned Alignment = I.getOperand(2).getImm(); buildOpDecorate(ResVReg, *It, TII, SPIRV::Decoration::Alignment, {Alignment}); } - return Res; + return true; } bool SPIRVInstructionSelector::selectBranch(MachineInstr &I) const { @@ -4827,15 +4939,17 @@ bool SPIRVInstructionSelector::selectBranch(MachineInstr &I) const { const MachineInstr *PrevI = I.getPrevNode(); MachineBasicBlock &MBB = *I.getParent(); if (PrevI != nullptr && PrevI->getOpcode() == TargetOpcode::G_BRCOND) { - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) .addUse(PrevI->getOperand(0).getReg()) .addMBB(PrevI->getOperand(1).getMBB()) .addMBB(I.getOperand(0).getMBB()) .constrainAllUses(TII, TRI, RBI); + return true; } - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranch)) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranch)) .addMBB(I.getOperand(0).getMBB()) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectBranchCond(MachineInstr &I) const { @@ -4858,11 +4972,12 @@ bool SPIRVInstructionSelector::selectBranchCond(MachineInstr &I) const { MachineBasicBlock &MBB = *I.getParent(); unsigned NextMBBNum = MBB.getNextNode()->getNumber(); MachineBasicBlock *NextMBB = I.getMF()->getBlockNumbered(NextMBBNum); - return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) + BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) .addUse(I.getOperand(0).getReg()) .addMBB(I.getOperand(1).getMBB()) .addMBB(NextMBB) .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectPhi(Register ResVReg, @@ -4876,10 +4991,10 @@ bool SPIRVInstructionSelector::selectPhi(Register ResVReg, MIB.addUse(I.getOperand(i + 0).getReg()); MIB.addMBB(I.getOperand(i + 1).getMBB()); } - bool Res = MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); MIB->setDesc(TII.get(TargetOpcode::PHI)); MIB->removeOperand(1); - return Res; + return true; } bool SPIRVInstructionSelector::selectGlobalValue( @@ -4945,15 +5060,17 @@ bool SPIRVInstructionSelector::selectGlobalValue( GR.add(ConstVal, MIB2); // mapping the function pointer to the used Function GR.recordFunctionPointer(&MIB2.getInstr()->getOperand(2), GVFun); - return MIB1.constrainAllUses(TII, TRI, RBI) && - MIB2.constrainAllUses(TII, TRI, RBI); + MIB1.constrainAllUses(TII, TRI, RBI); + MIB2.constrainAllUses(TII, TRI, RBI); + return true; } MachineInstrBuilder MIB3 = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) .addDef(NewReg) .addUse(GR.getSPIRVTypeID(ResType)); GR.add(ConstVal, MIB3); - return MIB3.constrainAllUses(TII, TRI, RBI); + MIB3.constrainAllUses(TII, TRI, RBI); + return true; } assert(NewReg != ResVReg); return BuildCOPY(ResVReg, NewReg, I); @@ -5008,14 +5125,13 @@ bool SPIRVInstructionSelector::selectLog10(Register ResVReg, // Build log2(x). Register VarReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); - bool Result = - BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) - .addDef(VarReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addImm(static_cast(SPIRV::InstructionSet::GLSL_std_450)) - .addImm(GL::Log2) - .add(I.getOperand(1)) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) + .addDef(VarReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addImm(static_cast(SPIRV::InstructionSet::GLSL_std_450)) + .addImm(GL::Log2) + .add(I.getOperand(1)) + .constrainAllUses(TII, TRI, RBI); // Build 0.30103. assert(ResType->getOpcode() == SPIRV::OpTypeVector || @@ -5032,12 +5148,13 @@ bool SPIRVInstructionSelector::selectLog10(Register ResVReg, auto Opcode = ResType->getOpcode() == SPIRV::OpTypeVector ? SPIRV::OpVectorTimesScalar : SPIRV::OpFMulS; - return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(VarReg) - .addUse(ScaleReg) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(VarReg) + .addUse(ScaleReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectModf(Register ResVReg, @@ -5103,10 +5220,12 @@ bool SPIRVInstructionSelector::selectModf(Register ResVReg, .addDef(IntegralPartReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(Variable); - return LoadMIB.constrainAllUses(TII, TRI, RBI); + LoadMIB.constrainAllUses(TII, TRI, RBI); + return true; } - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } else if (STI.canUseExtInstSet(SPIRV::InstructionSet::GLSL_std_450)) { assert(false && "GLSL::Modf is deprecated."); // FIXME: GL::Modf is deprecated, use Modfstruct instead. @@ -5148,11 +5267,10 @@ bool SPIRVInstructionSelector::loadVec3BuiltinInputID( GR.assignSPIRVTypeToVReg(Vec3Ty, LoadedRegister, MIRBuilder.getMF()); // Load v3uint value from the global variable. - bool Result = - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) - .addDef(LoadedRegister) - .addUse(GR.getSPIRVTypeID(Vec3Ty)) - .addUse(Variable); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) + .addDef(LoadedRegister) + .addUse(GR.getSPIRVTypeID(Vec3Ty)) + .addUse(Variable); // Get the input ID index. Expecting operand is a constant immediate value, // wrapped in a type assignment. @@ -5166,7 +5284,8 @@ bool SPIRVInstructionSelector::loadVec3BuiltinInputID( .addUse(GR.getSPIRVTypeID(ResType)) .addUse(LoadedRegister) .addImm(ThreadId); - return Result && MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } // Generate the instructions to load 32-bit integer builtin input IDs/Indices. @@ -5200,7 +5319,8 @@ bool SPIRVInstructionSelector::loadBuiltinInputID( .addUse(GR.getSPIRVTypeID(ResType)) .addUse(Variable); - return MIB.constrainAllUses(TII, TRI, RBI); + MIB.constrainAllUses(TII, TRI, RBI); + return true; } SPIRVType *SPIRVInstructionSelector::widenTypeToVec4(const SPIRVType *Type, @@ -5249,12 +5369,12 @@ bool SPIRVInstructionSelector::loadHandleBeforePosition( uint32_t LoadOpcode = IsStructuredBuffer ? SPIRV::OpCopyObject : SPIRV::OpLoad; GR.assignSPIRVTypeToVReg(ResType, HandleReg, *Pos.getMF()); - return BuildMI(*Pos.getParent(), Pos, HandleDef.getDebugLoc(), - TII.get(LoadOpcode)) + BuildMI(*Pos.getParent(), Pos, HandleDef.getDebugLoc(), TII.get(LoadOpcode)) .addDef(HandleReg) .addUse(GR.getSPIRVTypeID(ResType)) .addUse(VarReg) .constrainAllUses(TII, TRI, RBI); + return true; } void SPIRVInstructionSelector::errorIfInstrOutsideShader( diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp index 7d745847468d1..1050a1a1a10c2 100644 --- a/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVLegalizePointerCast.cpp @@ -194,7 +194,7 @@ class SPIRVLegalizePointerCast : public FunctionPass { Types = {Element->getType(), ElementPtr->getType()}; Align NewAlign = commonAlignment(Alignment, i * ElemSize); - Args = {Element, ElementPtr, B.getInt16(2), B.getInt8(NewAlign.value())}; + Args = {Element, ElementPtr, B.getInt16(2), B.getInt32(NewAlign.value())}; B.CreateIntrinsic(Intrinsic::spv_store, {Types}, {Args}); } } diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizeZeroSizeArrays.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizeZeroSizeArrays.cpp index ac51aa9ea93a8..06e4561aafd26 100644 --- a/llvm/lib/Target/SPIRV/SPIRVLegalizeZeroSizeArrays.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVLegalizeZeroSizeArrays.cpp @@ -193,25 +193,21 @@ Constant *SPIRVLegalizeZeroSizeArraysImpl::legalizeConstant(Constant *C) { } void SPIRVLegalizeZeroSizeArraysImpl::visitAllocaInst(AllocaInst &AI) { - if (!hasZeroSizeArray(AI.getAllocatedType())) + // Check if allocation size is known-zero + const DataLayout &DL = AI.getModule()->getDataLayout(); + std::optional Size = AI.getAllocationSize(DL); + if (!Size || !Size->isZero()) return; - // TODO: Handle structs containing zero-size arrays. - ArrayType *ArrTy = dyn_cast(AI.getAllocatedType()); - if (shouldLegalizeInstType(ArrTy)) { - // Allocate a generic pointer instead of an empty array. - IRBuilder<> Builder(&AI); - AllocaInst *NewAI = Builder.CreateAlloca( - PointerType::get( - ArrTy->getContext(), - storageClassToAddressSpace(SPIRV::StorageClass::Generic)), - /*ArraySize=*/nullptr, AI.getName()); - NewAI->setAlignment(AI.getAlign()); - NewAI->setDebugLoc(AI.getDebugLoc()); - AI.replaceAllUsesWith(NewAI); - ToErase.push_back(&AI); - Modified = true; - } + // Allocate a byte instead of an empty alloca. + IRBuilder<> Builder(&AI); + AllocaInst *NewAI = Builder.CreateAlloca(Builder.getInt8Ty()); + NewAI->takeName(&AI); + NewAI->setAlignment(AI.getAlign()); + NewAI->setDebugLoc(AI.getDebugLoc()); + AI.replaceAllUsesWith(NewAI); + ToErase.push_back(&AI); + Modified = true; } void SPIRVLegalizeZeroSizeArraysImpl::visitLoadInst(LoadInst &LI) { diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp index 03d846cb90b4c..dc5906cfa9ceb 100644 --- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp @@ -434,10 +434,12 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) { // tighten these requirements. Many of these math functions are only legal on // specific bitwidths, so they are not selectable for // allFloatScalarsAndVectors. + // clang-format off getActionDefinitionsBuilder({G_STRICT_FSQRT, G_FPOW, G_FEXP, G_FMODF, + G_FSINCOS, G_FEXP2, G_FLOG, G_FLOG2, @@ -466,6 +468,7 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) { G_FMAXIMUM, G_INTRINSIC_ROUNDEVEN}) .legalFor(allFloatScalarsAndVectors); + // clang-format on getActionDefinitionsBuilder(G_FCOPYSIGN) .legalForCartesianProduct(allFloatScalarsAndVectors, diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index b3b56d4c67e5b..ecdf1c47d6926 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -2337,6 +2337,11 @@ void addInstrRequirements(const MachineInstr &MI, Reqs.addCapability(SPIRV::Capability::DerivativeControl); break; } + case SPIRV::OpLoopControlINTEL: { + Reqs.addExtension(SPIRV::Extension::SPV_INTEL_unstructured_loop_controls); + Reqs.addCapability(SPIRV::Capability::UnstructuredLoopControlsINTEL); + break; + } default: break; diff --git a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp index a3425704f050d..54f8b58114f7f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp @@ -23,6 +23,7 @@ #include "SPIRVTargetMachine.h" #include "SPIRVUtils.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/CodeGen/IntrinsicLowering.h" #include "llvm/IR/IRBuilder.h" @@ -96,7 +97,8 @@ static Function *getOrCreateFunction(Module *M, Type *RetTy, return NewF; } -static bool lowerIntrinsicToFunction(IntrinsicInst *Intrinsic) { +static bool lowerIntrinsicToFunction(IntrinsicInst *Intrinsic, + const TargetTransformInfo &TTI) { // For @llvm.memset.* intrinsic cases with constant value and length arguments // are emulated via "storing" a constant array to the destination. For other // cases we wrap the intrinsic in @spirv.llvm_memset_* function and expand the @@ -140,7 +142,7 @@ static bool lowerIntrinsicToFunction(IntrinsicInst *Intrinsic) { auto *MemSet = IRB.CreateMemSet(Dest, Val, Len, MSI->getDestAlign(), MSI->isVolatile()); IRB.CreateRetVoid(); - expandMemSetAsLoop(cast(MemSet)); + expandMemSetAsLoop(cast(MemSet), TTI); MemSet->eraseFromParent(); break; } @@ -427,6 +429,7 @@ bool SPIRVPrepareFunctions::substituteIntrinsicCalls(Function *F) { bool Changed = false; const SPIRVSubtarget &STI = TM.getSubtarget(*F); SmallVector EraseFromParent; + const TargetTransformInfo &TTI = TM.getTargetTransformInfo(*F); for (BasicBlock &BB : *F) { for (Instruction &I : make_early_inc_range(BB)) { auto Call = dyn_cast(&I); @@ -439,7 +442,7 @@ bool SPIRVPrepareFunctions::substituteIntrinsicCalls(Function *F) { switch (II->getIntrinsicID()) { case Intrinsic::memset: case Intrinsic::bswap: - Changed |= lowerIntrinsicToFunction(II); + Changed |= lowerIntrinsicToFunction(II, TTI); break; case Intrinsic::fshl: case Intrinsic::fshr: @@ -491,7 +494,7 @@ bool SPIRVPrepareFunctions::substituteIntrinsicCalls(Function *F) { return false; return II->getCalledFunction()->getName().starts_with(Prefix); })) - Changed |= lowerIntrinsicToFunction(II); + Changed |= lowerIntrinsicToFunction(II, TTI); break; } } @@ -656,6 +659,13 @@ bool SPIRVPrepareFunctions::removeAggregateTypesFromCalls(Function *F) { } bool SPIRVPrepareFunctions::runOnModule(Module &M) { + // Resolve the SPIR-V environment from module content before any + // function-level processing. This must happen before legalization so that + // isShader()/isKernel() return correct values. + const_cast(TM) + .getMutableSubtargetImpl() + ->resolveEnvFromModule(M); + bool Changed = false; for (Function &F : M) { Changed |= substituteIntrinsicCalls(&F); diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp index ad6c9cd421b7c..6a798057240de 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp @@ -173,6 +173,42 @@ void SPIRVSubtarget::initAvailableExtInstSets() { accountForAMDShaderTrinaryMinmax(); } +void SPIRVSubtarget::setEnv(SPIRVEnvType E) { + if (E == Unknown) + report_fatal_error("Unknown environment is not allowed."); + if (Env != Unknown && Env != E) + report_fatal_error("Environment is already set to a different value."); + if (Env == E) + return; + + Env = E; + + // Reinitialize Env-dependent state aka ExtInstSet and legalizer info. + initAvailableExtInstSets(); + Legalizer = std::make_unique(*this); +} + +void SPIRVSubtarget::resolveEnvFromModule(const Module &M) { + if (Env != Unknown) { + assert(!(isKernel() && any_of(M, + [](const Function &F) { + return F.hasFnAttribute("hlsl.shader"); + })) && + "Module has hlsl.shader attributes but environment is Kernel"); + return; + } + + bool HasShaderAttr = false; + for (const Function &F : M) { + if (F.hasFnAttribute("hlsl.shader")) { + HasShaderAttr = true; + break; + } + } + + setEnv(HasShaderAttr ? Shader : Kernel); +} + // Set available extensions after SPIRVSubtarget is created. void SPIRVSubtarget::initAvailableExtensions( const std::set &AllowedExtIds) { diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h index ad3e38d296ed7..18f7e0179270c 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.h +++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.h @@ -25,6 +25,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DataLayout.h" +#include "llvm/IR/Module.h" #include "llvm/Target/TargetMachine.h" #include "llvm/TargetParser/Triple.h" @@ -62,8 +63,6 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo { std::unique_ptr InstSelector; std::unique_ptr InlineAsmInfo; - // TODO: Initialise the available extensions, extended instruction sets - // based on the environment settings. void initAvailableExtInstSets(); void accountForAMDShaderTrinaryMinmax(); @@ -76,6 +75,7 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo { void initAvailableExtensions( const std::set &AllowedExtIds); + void resolveEnvFromModule(const Module &M); // Parses features string setting specified subtarget options. // The definition of this function is auto generated by tblgen. @@ -83,14 +83,7 @@ class SPIRVSubtarget : public SPIRVGenSubtargetInfo { unsigned getPointerSize() const { return PointerSize; } unsigned getBound() const { return GR->getBound(); } bool canDirectlyComparePointers() const; - void setEnv(SPIRVEnvType E) { - if (E == Unknown) - report_fatal_error("Unknown environment is not allowed."); - if (Env != Unknown) - report_fatal_error("Environment is already set."); - - Env = E; - } + void setEnv(SPIRVEnvType E); SPIRVEnvType getEnv() const { return Env; } bool isKernel() const { return getEnv() == Kernel; } bool isShader() const { return getEnv() == Shader; } diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td index 1a2d3d140ba39..ed460212fa761 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td +++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td @@ -572,7 +572,7 @@ defm FloatControls2 : CapabilityOperand<6029, 0x10200, 0, [SPV_KHR_float_controls2], []>; defm AtomicFloat32AddEXT : CapabilityOperand<6033, 0, 0, [SPV_EXT_shader_atomic_float_add], []>; defm AtomicFloat64AddEXT : CapabilityOperand<6034, 0, 0, [SPV_EXT_shader_atomic_float_add], []>; -defm FmaKHR : CapabilityOperand<6035, 0, 0, [SPV_KHR_fma], []>; +defm FmaKHR : CapabilityOperand<6030, 0, 0, [SPV_KHR_fma], []>; defm AtomicFloat16AddEXT : CapabilityOperand<6095, 0, 0, [SPV_EXT_shader_atomic_float16_add], []>; defm AtomicBFloat16AddINTEL : CapabilityOperand<6255, 0, 0, [SPV_INTEL_16bit_atomics], []>; defm AtomicFloat16MinMaxEXT : CapabilityOperand<5616, 0, 0, [SPV_EXT_shader_atomic_float_min_max], []>; @@ -625,6 +625,7 @@ defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloa defm BlockingPipesALTERA : CapabilityOperand<5945, 0, 0, [SPV_ALTERA_blocking_pipes], []>; defm ArbitraryPrecisionFixedPointALTERA : CapabilityOperand<5922, 0, 0, [SPV_ALTERA_arbitrary_precision_fixed_point], []>; defm ArbitraryPrecisionFloatingPointALTERA : CapabilityOperand<5845, 0, 0,[SPV_ALTERA_arbitrary_precision_floating_point], []>; +defm UnstructuredLoopControlsINTEL : CapabilityOperand<5886, 0, 0, [SPV_INTEL_unstructured_loop_controls], []>; //===----------------------------------------------------------------------===// // Multiclass used to define SourceLanguage enum values and at the same time diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h index 9c59d021dfc1b..ea09fe98c55ee 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.h @@ -35,6 +35,8 @@ class SPIRVTargetMachine : public CodeGenTargetMachineImpl { return &Subtarget; } + SPIRVSubtarget *getMutableSubtargetImpl() { return &Subtarget; } + TargetTransformInfo getTargetTransformInfo(const Function &F) const override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override; diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp index 9c0473e69e076..9147611de495d 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp @@ -986,25 +986,31 @@ createContinuedInstructions(MachineIRBuilder &MIRBuilder, unsigned Opcode, return Instructions; } -SmallVector getSpirvLoopControlOperandsFromLoopMetadata(Loop *L) { +SmallVector +getSpirvLoopControlOperandsFromLoopMetadata(MDNode *LoopMD) { unsigned LC = SPIRV::LoopControl::None; // Currently used only to store PartialCount value. Later when other // LoopControls are added - this map should be sorted before making // them loop_merge operands to satisfy 3.23. Loop Control requirements. std::vector> MaskToValueMap; - if (getBooleanLoopAttribute(L, "llvm.loop.unroll.disable")) { + if (findOptionMDForLoopID(LoopMD, "llvm.loop.unroll.disable")) { LC |= SPIRV::LoopControl::DontUnroll; } else { - if (getBooleanLoopAttribute(L, "llvm.loop.unroll.enable") || - getBooleanLoopAttribute(L, "llvm.loop.unroll.full")) { + if (findOptionMDForLoopID(LoopMD, "llvm.loop.unroll.enable") || + findOptionMDForLoopID(LoopMD, "llvm.loop.unroll.full")) { LC |= SPIRV::LoopControl::Unroll; } - std::optional Count = - getOptionalIntLoopAttribute(L, "llvm.loop.unroll.count"); - if (Count && Count != 1) { - LC |= SPIRV::LoopControl::PartialCount; - MaskToValueMap.emplace_back( - std::make_pair(SPIRV::LoopControl::PartialCount, *Count)); + if (MDNode *CountMD = + findOptionMDForLoopID(LoopMD, "llvm.loop.unroll.count")) { + if (auto *CI = + mdconst::extract_or_null(CountMD->getOperand(1))) { + unsigned Count = CI->getZExtValue(); + if (Count != 1) { + LC |= SPIRV::LoopControl::PartialCount; + MaskToValueMap.emplace_back( + std::make_pair(SPIRV::LoopControl::PartialCount, Count)); + } + } } } SmallVector Result = {LC}; @@ -1013,6 +1019,10 @@ SmallVector getSpirvLoopControlOperandsFromLoopMetadata(Loop *L) { return Result; } +SmallVector getSpirvLoopControlOperandsFromLoopMetadata(Loop *L) { + return getSpirvLoopControlOperandsFromLoopMetadata(L->getLoopID()); +} + const std::set &getTypeFoldingSupportedOpcodes() { // clang-format off static const std::set TypeFoldingSupportingOpcs = { diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h index 33e28627bcf89..50042c90a86d3 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.h +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.h @@ -571,6 +571,8 @@ bool isTypeFoldingSupported(unsigned Opcode); // Get loop controls from llvm.loop. metadata. SmallVector getSpirvLoopControlOperandsFromLoopMetadata(Loop *L); +SmallVector +getSpirvLoopControlOperandsFromLoopMetadata(MDNode *LoopMD); // Traversing [g]MIR accounting for pseudo-instructions. MachineInstr *passCopy(MachineInstr *Def, const MachineRegisterInfo *MRI); diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index 15ac5a4af0d29..58c8b30f96b4c 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -159,6 +159,36 @@ static MCInst lowerVecEltInsertion(const MachineInstr *MI, unsigned Opcode) { .addImm(0); } +bool SystemZAsmPrinter::doInitialization(Module &M) { + SM.reset(); + + // In HLASM, the only way to represent aliases is to use the + // extra-label-at-definition strategy. This is similar to the AIX + // implementation with the additional caveat that all symbol attributes must + // be emitted before the label is emitted. + if (TM.getTargetTriple().isOSzOS()) { + // Construct an aliasing list for each GlobalObject. + for (const auto &Alias : M.aliases()) { + const GlobalObject *Aliasee = Alias.getAliaseeObject(); + if (!Aliasee) + OutContext.reportError( + {}, "Alias without a base object is not yet supported on z/OS."); + + bool IsFunc = isa(Aliasee->stripPointerCasts()); + if (IsFunc) { + if (Alias.hasWeakLinkage() || Alias.hasLinkOnceLinkage()) + OutContext.reportError({}, + "Weak alias/reference not supported on z/OS"); + + GOAliasMap[Aliasee].push_back(&Alias); + } else + OutContext.reportError( + {}, "Only aliases to functions is supported in GOFF."); + } + } + return AsmPrinter::doInitialization(M); +} + // The XPLINK ABI requires that a no-op encoding the call type is emitted after // each call to a subroutine. This information can be used by the called // function to determine its entry point, e.g. for generating a backtrace. The @@ -1784,6 +1814,58 @@ void SystemZAsmPrinter::emitPPA2(Module &M) { OutStreamer->popSection(); } +void SystemZAsmPrinter::emitGlobalAlias(const Module &M, + const GlobalAlias &GA) { + if (!TM.getTargetTriple().isOSzOS()) + return AsmPrinter::emitGlobalAlias(M, GA); + + // Aliased function labels have already been emitted for z/OS +} + +const MCExpr *SystemZAsmPrinter::lowerConstant(const Constant *CV, + const Constant *BaseCV, + uint64_t Offset) { + const Triple &TargetTriple = TM.getTargetTriple(); + + if (TargetTriple.isOSzOS()) { + const GlobalAlias *GA = dyn_cast(CV); + const GlobalVariable *GV = dyn_cast(CV); + const Function *FV = dyn_cast(CV); + bool IsFunc = !GV && (FV || (GA && isa(GA->getAliaseeObject()))); + + MCSymbol *Sym = NULL; + + if (GA) + Sym = getSymbol(GA); + else if (IsFunc) + Sym = getSymbol(FV); + else if (GV) + Sym = getSymbol(GV); + + if (IsFunc) { + OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction); + if (FV->hasExternalLinkage()) + return MCSpecifierExpr::create(MCSymbolRefExpr::create(Sym, OutContext), + SystemZ::S_VCon, OutContext); + // Trigger creation of function descriptor in ADA for internal + // functions. + unsigned Disp = ADATable.insert(Sym, SystemZII::MO_ADA_DIRECT_FUNC_DESC); + return MCBinaryExpr::createAdd( + MCSpecifierExpr::create( + MCSymbolRefExpr::create( + getObjFileLowering().getADASection()->getBeginSymbol(), + OutContext), + SystemZ::S_None, OutContext), + MCConstantExpr::create(Disp, OutContext), OutContext); + } + if (Sym) { + OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeObject); + return MCSymbolRefExpr::create(Sym, OutContext); + } + } + return AsmPrinter::lowerConstant(CV); +} + void SystemZAsmPrinter::emitFunctionEntryLabel() { const SystemZSubtarget &Subtarget = MF->getSubtarget(); @@ -1843,6 +1925,18 @@ void SystemZAsmPrinter::emitFunctionEntryLabel() { } AsmPrinter::emitFunctionEntryLabel(); + + if (Subtarget.getTargetTriple().isOSzOS()) { + const Function *F = &MF->getFunction(); + // Emit aliasing label for function entry point label. + for (const GlobalAlias *Alias : GOAliasMap[F]) { + MCSymbol *Sym = getSymbol(Alias); + OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction); + emitVisibility(Sym, Alias->getVisibility()); + emitLinkage(Alias, Sym); + OutStreamer->emitLabel(Sym); + } + } } char SystemZAsmPrinter::ID = 0; diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h index 663a0b2b295f9..0f87eb0307911 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h @@ -93,6 +93,12 @@ class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter { AssociatedDataAreaTable ADATable; + // Record a list of GlobalAlias associated with a GlobalObject. + // This is used for z/OS's extra-label-at-definition aliasing strategy. + // This is similar to what is done for AIX. + DenseMap> + GOAliasMap; + void emitPPA1(MCSymbol *FnEndSym); void emitPPA2(Module &M); void emitADASection(); @@ -125,13 +131,14 @@ class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter { return false; } - bool doInitialization(Module &M) override { - SM.reset(); - return AsmPrinter::doInitialization(M); - } + bool doInitialization(Module &M) override; void emitFunctionEntryLabel() override; void emitFunctionBodyEnd() override; void emitStartOfAsmFile(Module &M) override; + void emitGlobalAlias(const Module &M, const GlobalAlias &GA) override; + const MCExpr *lowerConstant(const Constant *CV, + const Constant *BaseCV = nullptr, + uint64_t Offset = 0) override; private: void emitCallInformation(CallType CT); diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp index 570bbd884a244..d4c8f61245ae1 100644 --- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp @@ -12,6 +12,7 @@ #include "SystemZMachineFunctionInfo.h" #include "SystemZRegisterInfo.h" #include "SystemZSubtarget.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" @@ -1027,8 +1028,10 @@ bool SystemZXPLINKFrameLowering::assignCalleeSavedSpillSlots( // If this function has an associated personality function then the // environment register R5 must be saved in the DSA. - if (!MF.getLandingPads().empty()) + if (!MF.getLandingPads().empty()) { CSI.push_back(CalleeSavedInfo(Regs.getADARegister())); + CSI.back().setRestored(false); + } // Scan the call-saved GPRs and find the bounds of the register spill area. Register LowRestoreGPR = 0; @@ -1152,7 +1155,11 @@ bool SystemZXPLINKFrameLowering::spillCalleeSavedRegisters( } // Spill FPRs to the stack in the normal TargetInstrInfo way - for (const CalleeSavedInfo &I : CSI) { + // Registers in CSI are in inverted order so registers with large + // numbers will be assigned to high address. + // Reverse the order at spilling and restoring so instructions on + // registers with small numbers are emitted first. + for (const CalleeSavedInfo &I : llvm::reverse(CSI)) { MCRegister Reg = I.getReg(); if (SystemZ::FP64BitRegClass.contains(Reg)) { MBB.addLiveIn(Reg); @@ -1185,7 +1192,7 @@ bool SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters( DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); // Restore FPRs in the normal TargetInstrInfo way. - for (const CalleeSavedInfo &I : CSI) { + for (const CalleeSavedInfo &I : llvm::reverse(CSI)) { MCRegister Reg = I.getReg(); if (SystemZ::FP64BitRegClass.contains(Reg)) TII->loadRegFromStackSlot(MBB, MBBI, Reg, I.getFrameIdx(), diff --git a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp index afffeb52da879..eec37a9df386f 100644 --- a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp @@ -238,8 +238,8 @@ std::pair SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy( std::pair SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, - SDValue Src2, MachinePointerInfo Op1PtrInfo, - MachinePointerInfo Op2PtrInfo) const { + SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo, + const CallInst *CI) const { SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other); // Swap operands to invert CC == 1 vs. CC == 2 cases. SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src2, Src1, diff --git a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h index 6da36c9bc4225..8e6da4fe8b0ae 100644 --- a/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h @@ -74,11 +74,10 @@ class SystemZSelectionDAGInfo : public SelectionDAGGenTargetInfo { MachinePointerInfo SrcPtrInfo, bool isStpcpy, const CallInst *CI) const override; - std::pair - EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, - SDValue Src1, SDValue Src2, - MachinePointerInfo Op1PtrInfo, - MachinePointerInfo Op2PtrInfo) const override; + std::pair EmitTargetCodeForStrcmp( + SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, + SDValue Src2, MachinePointerInfo Op1PtrInfo, + MachinePointerInfo Op2PtrInfo, const CallInst *CI) const override; std::pair EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index f8f13a042fec0..3494637237c69 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -158,7 +158,6 @@ void TargetMachine::resetTargetOptions(const Function &F) const { Options.X = F.getFnAttribute(Y).getValueAsBool(); \ } while (0) - RESET_OPTION(NoInfsFPMath, "no-infs-fp-math"); RESET_OPTION(NoNaNsFPMath, "no-nans-fp-math"); RESET_OPTION(NoSignedZerosFPMath, "no-signed-zeros-fp-math"); } diff --git a/llvm/lib/Target/WebAssembly/CMakeLists.txt b/llvm/lib/Target/WebAssembly/CMakeLists.txt index 17df119d62709..1ad99f7e468df 100644 --- a/llvm/lib/Target/WebAssembly/CMakeLists.txt +++ b/llvm/lib/Target/WebAssembly/CMakeLists.txt @@ -9,13 +9,27 @@ tablegen(LLVM WebAssemblyGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel) tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info) tablegen(LLVM WebAssemblyGenMCCodeEmitter.inc -gen-emitter) +tablegen(LLVM WebAssemblyGenRegisterBank.inc -gen-register-bank) tablegen(LLVM WebAssemblyGenRegisterInfo.inc -gen-register-info) tablegen(LLVM WebAssemblyGenSDNodeInfo.inc -gen-sd-node-info) tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget) +set(LLVM_TARGET_DEFINITIONS WebAssemblyGISel.td) +tablegen(LLVM WebAssemblyGenGlobalISel.inc -gen-global-isel) +tablegen(LLVM WebAssemblyGenPreLegalizeGICombiner.inc -gen-global-isel-combiner + -combiners="WebAssemblyPreLegalizerCombiner") +tablegen(LLVM WebAssemblyGenPostLegalizeGICombiner.inc -gen-global-isel-combiner + -combiners="WebAssemblyPostLegalizerCombiner") + add_public_tablegen_target(WebAssemblyCommonTableGen) add_llvm_target(WebAssemblyCodeGen + GISel/WebAssemblyCallLowering.cpp + GISel/WebAssemblyInstructionSelector.cpp + GISel/WebAssemblyPostLegalizerCombiner.cpp + GISel/WebAssemblyPreLegalizerCombiner.cpp + GISel/WebAssemblyLegalizerInfo.cpp + GISel/WebAssemblyRegisterBankInfo.cpp WebAssemblyAddMissingPrototypes.cpp WebAssemblyArgumentMove.cpp WebAssemblyAsmPrinter.cpp @@ -72,6 +86,7 @@ add_llvm_target(WebAssemblyCodeGen CodeGen CodeGenTypes Core + GlobalISel MC Scalar SelectionDAG diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp new file mode 100644 index 0000000000000..3d0bbcc9a1c7b --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.cpp @@ -0,0 +1,65 @@ +//===-- WebAssemblyCallLowering.cpp - Call lowering for GlobalISel -*- C++ -*-// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the lowering of LLVM calls to machine code calls for +/// GlobalISel. +/// +//===----------------------------------------------------------------------===// + +#include "WebAssemblyCallLowering.h" +#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" +#include "WebAssemblyISelLowering.h" +#include "WebAssemblyMachineFunctionInfo.h" +#include "WebAssemblySubtarget.h" +#include "WebAssemblyUtilities.h" +#include "llvm/CodeGen/Analysis.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/DebugLoc.h" +#include "llvm/IR/Value.h" + +#define DEBUG_TYPE "wasm-call-lowering" + +using namespace llvm; + +WebAssemblyCallLowering::WebAssemblyCallLowering( + const WebAssemblyTargetLowering &TLI) + : CallLowering(&TLI) {} + +bool WebAssemblyCallLowering::canLowerReturn(MachineFunction &MF, + CallingConv::ID CallConv, + SmallVectorImpl &Outs, + bool IsVarArg) const { + return WebAssembly::canLowerReturn(Outs.size(), + &MF.getSubtarget()); +} + +bool WebAssemblyCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, + const Value *Val, + ArrayRef VRegs, + FunctionLoweringInfo &FLI, + Register SwiftErrorVReg) const { + if (!Val) + return true; // allow only void returns for now + + return false; +} + +bool WebAssemblyCallLowering::lowerFormalArguments( + MachineIRBuilder &MIRBuilder, const Function &F, + ArrayRef> VRegs, FunctionLoweringInfo &FLI) const { + if (VRegs.empty()) + return true; // allow only empty signatures for now + + return false; +} + +bool WebAssemblyCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, + CallLoweringInfo &Info) const { + return false; +} diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.h b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.h new file mode 100644 index 0000000000000..d22f7cbd17eb3 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyCallLowering.h @@ -0,0 +1,43 @@ +//===-- WebAssemblyCallLowering.h - Call lowering for GlobalISel -*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file describes how to lower LLVM calls to machine code calls. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_GISEL_WEBASSEMBLYCALLLOWERING_H +#define LLVM_LIB_TARGET_WEBASSEMBLY_GISEL_WEBASSEMBLYCALLLOWERING_H + +#include "WebAssemblyISelLowering.h" +#include "llvm/CodeGen/GlobalISel/CallLowering.h" +#include "llvm/IR/CallingConv.h" + +namespace llvm { + +class WebAssemblyTargetLowering; + +class WebAssemblyCallLowering : public CallLowering { +public: + WebAssemblyCallLowering(const WebAssemblyTargetLowering &TLI); + + bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, + SmallVectorImpl &Outs, + bool IsVarArg) const override; + bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, + ArrayRef VRegs, FunctionLoweringInfo &FLI, + Register SwiftErrorVReg) const override; + bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, + ArrayRef> VRegs, + FunctionLoweringInfo &FLI) const override; + bool lowerCall(MachineIRBuilder &MIRBuilder, + CallLoweringInfo &Info) const override; +}; +} // namespace llvm + +#endif diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp new file mode 100644 index 0000000000000..d6eee444af992 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp @@ -0,0 +1,100 @@ +//===- WebAssemblyInstructionSelector.cpp ------------------------*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file implements the targeting of the InstructionSelector class for +/// WebAssembly. +/// \todo This should be generated by TableGen. +//===----------------------------------------------------------------------===// + +#include "GISel/WebAssemblyRegisterBankInfo.h" +#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" +#include "WebAssemblyRegisterInfo.h" +#include "WebAssemblySubtarget.h" +#include "WebAssemblyTargetMachine.h" +#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h" +#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineOperand.h" +#include "llvm/CodeGen/TargetLowering.h" +#include "llvm/IR/IntrinsicsWebAssembly.h" + +#define DEBUG_TYPE "wasm-isel" + +using namespace llvm; + +namespace { + +#define GET_GLOBALISEL_PREDICATE_BITSET +#include "WebAssemblyGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATE_BITSET + +class WebAssemblyInstructionSelector : public InstructionSelector { +public: + WebAssemblyInstructionSelector(const WebAssemblyTargetMachine &TM, + const WebAssemblySubtarget &STI, + const WebAssemblyRegisterBankInfo &RBI); + + bool select(MachineInstr &I) override; + + static const char *getName() { return DEBUG_TYPE; } + +private: + bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; + + const WebAssemblyTargetMachine &TM; + // const WebAssemblySubtarget &STI; + const WebAssemblyInstrInfo &TII; + const WebAssemblyRegisterInfo &TRI; + const WebAssemblyRegisterBankInfo &RBI; + +#define GET_GLOBALISEL_PREDICATES_DECL +#include "WebAssemblyGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATES_DECL + +#define GET_GLOBALISEL_TEMPORARIES_DECL +#include "WebAssemblyGenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_DECL +}; + +} // end anonymous namespace + +#define GET_GLOBALISEL_IMPL +#include "WebAssemblyGenGlobalISel.inc" +#undef GET_GLOBALISEL_IMPL + +WebAssemblyInstructionSelector::WebAssemblyInstructionSelector( + const WebAssemblyTargetMachine &TM, const WebAssemblySubtarget &STI, + const WebAssemblyRegisterBankInfo &RBI) + : TM(TM), /*STI(STI),*/ TII(*STI.getInstrInfo()), + TRI(*STI.getRegisterInfo()), RBI(RBI), + +#define GET_GLOBALISEL_PREDICATES_INIT +#include "WebAssemblyGenGlobalISel.inc" +#undef GET_GLOBALISEL_PREDICATES_INIT +#define GET_GLOBALISEL_TEMPORARIES_INIT +#include "WebAssemblyGenGlobalISel.inc" +#undef GET_GLOBALISEL_TEMPORARIES_INIT +{ +} + +bool WebAssemblyInstructionSelector::select(MachineInstr &I) { + if (selectImpl(I, *CoverageInfo)) + return true; + + return false; +} + +namespace llvm { +InstructionSelector * +createWebAssemblyInstructionSelector(const WebAssemblyTargetMachine &TM, + const WebAssemblySubtarget &Subtarget, + const WebAssemblyRegisterBankInfo &RBI) { + return new WebAssemblyInstructionSelector(TM, Subtarget, RBI); +} +} // namespace llvm diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp new file mode 100644 index 0000000000000..82b8a48266e31 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp @@ -0,0 +1,23 @@ +//===- WebAssemblyLegalizerInfo.cpp ------------------------------*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file implements the targeting of the Machinelegalizer class for +/// WebAssembly. +//===----------------------------------------------------------------------===// + +#include "WebAssemblyLegalizerInfo.h" + +#define DEBUG_TYPE "wasm-legalinfo" + +using namespace llvm; +using namespace LegalizeActions; + +WebAssemblyLegalizerInfo::WebAssemblyLegalizerInfo( + const WebAssemblySubtarget &ST) { + getLegacyLegalizerInfo().computeTables(); +} diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.h b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.h new file mode 100644 index 0000000000000..61f4aa621d44f --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.h @@ -0,0 +1,29 @@ +//===- WebAssemblyLegalizerInfo.h --------------------------------*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file declares the targeting of the Machinelegalizer class for +/// WebAssembly. +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_GISEL_WEBASSEMBLYMACHINELEGALIZER_H +#define LLVM_LIB_TARGET_WEBASSEMBLY_GISEL_WEBASSEMBLYMACHINELEGALIZER_H + +#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" + +namespace llvm { + +class WebAssemblySubtarget; + +/// This class provides the information for the WebAssembly target legalizer for +/// GlobalISel. +class WebAssemblyLegalizerInfo : public LegalizerInfo { +public: + WebAssemblyLegalizerInfo(const WebAssemblySubtarget &ST); +}; +} // namespace llvm +#endif diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyPostLegalizerCombiner.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyPostLegalizerCombiner.cpp new file mode 100644 index 0000000000000..aa7e4c4e91136 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyPostLegalizerCombiner.cpp @@ -0,0 +1,176 @@ +//=== WebAssemblyPostLegalizerCombiner.cpp ----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// Post-legalization combines on generic MachineInstrs. +/// +/// The combines here must preserve instruction legality. +/// +/// Combines which don't rely on instruction legality should go in the +/// WebAssemblyPreLegalizerCombiner. +/// +//===----------------------------------------------------------------------===// + +#include "WebAssembly.h" +#include "WebAssemblyTargetMachine.h" +#include "llvm/CodeGen/GlobalISel/CSEInfo.h" +#include "llvm/CodeGen/GlobalISel/Combiner.h" +#include "llvm/CodeGen/GlobalISel/CombinerHelper.h" +#include "llvm/CodeGen/GlobalISel/CombinerInfo.h" +#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h" +#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/TargetPassConfig.h" + +#define GET_GICOMBINER_DEPS +#include "WebAssemblyGenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_DEPS + +#define DEBUG_TYPE "wasm-postlegalizer-combiner" + +using namespace llvm; + +namespace { + +#define GET_GICOMBINER_TYPES +#include "WebAssemblyGenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_TYPES + +class WebAssemblyPostLegalizerCombinerImpl : public Combiner { +protected: + const CombinerHelper Helper; + const WebAssemblyPostLegalizerCombinerImplRuleConfig &RuleConfig; + const WebAssemblySubtarget &STI; + +public: + WebAssemblyPostLegalizerCombinerImpl( + MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC, + GISelValueTracking &VT, GISelCSEInfo *CSEInfo, + const WebAssemblyPostLegalizerCombinerImplRuleConfig &RuleConfig, + const WebAssemblySubtarget &STI, MachineDominatorTree *MDT, + const LegalizerInfo *LI); + + static const char *getName() { return "WebAssemblyPostLegalizerCombiner"; } + + bool tryCombineAll(MachineInstr &I) const override; + +private: +#define GET_GICOMBINER_CLASS_MEMBERS +#include "WebAssemblyGenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_CLASS_MEMBERS +}; + +#define GET_GICOMBINER_IMPL +#include "WebAssemblyGenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_IMPL + +WebAssemblyPostLegalizerCombinerImpl::WebAssemblyPostLegalizerCombinerImpl( + MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC, + GISelValueTracking &VT, GISelCSEInfo *CSEInfo, + const WebAssemblyPostLegalizerCombinerImplRuleConfig &RuleConfig, + const WebAssemblySubtarget &STI, MachineDominatorTree *MDT, + const LegalizerInfo *LI) + : Combiner(MF, CInfo, TPC, &VT, CSEInfo), + Helper(Observer, B, /*IsPreLegalize*/ false, &VT, MDT, LI), + RuleConfig(RuleConfig), STI(STI), +#define GET_GICOMBINER_CONSTRUCTOR_INITS +#include "WebAssemblyGenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_CONSTRUCTOR_INITS +{ +} + +class WebAssemblyPostLegalizerCombiner : public MachineFunctionPass { +public: + static char ID; + + WebAssemblyPostLegalizerCombiner(); + + StringRef getPassName() const override { + return "WebAssemblyPostLegalizerCombiner"; + } + + bool runOnMachineFunction(MachineFunction &MF) override; + void getAnalysisUsage(AnalysisUsage &AU) const override; + +private: + WebAssemblyPostLegalizerCombinerImplRuleConfig RuleConfig; +}; +} // end anonymous namespace + +void WebAssemblyPostLegalizerCombiner::getAnalysisUsage( + AnalysisUsage &AU) const { + AU.addRequired(); + AU.setPreservesCFG(); + getSelectionDAGFallbackAnalysisUsage(AU); + AU.addRequired(); + AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); + MachineFunctionPass::getAnalysisUsage(AU); +} + +WebAssemblyPostLegalizerCombiner::WebAssemblyPostLegalizerCombiner() + : MachineFunctionPass(ID) { + if (!RuleConfig.parseCommandLineOption()) + report_fatal_error("Invalid rule identifier"); +} + +bool WebAssemblyPostLegalizerCombiner::runOnMachineFunction( + MachineFunction &MF) { + if (MF.getProperties().hasFailedISel()) + return false; + assert(MF.getProperties().hasLegalized() && "Expected a legalized function?"); + auto *TPC = &getAnalysis(); + const Function &F = MF.getFunction(); + bool EnableOpt = + MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); + + const WebAssemblySubtarget &ST = MF.getSubtarget(); + const auto *LI = ST.getLegalizerInfo(); + + GISelValueTracking *VT = + &getAnalysis().get(MF); + MachineDominatorTree *MDT = nullptr; + GISelCSEInfo *CSEInfo = nullptr; + + MDT = &getAnalysis().getDomTree(); + + GISelCSEAnalysisWrapper &Wrapper = + getAnalysis().getCSEWrapper(); + CSEInfo = &Wrapper.get(TPC->getCSEConfig()); + + CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false, + /*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(), + F.hasMinSize()); + // Disable fixed-point iteration to reduce compile-time + CInfo.MaxIterations = 1; + CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass; + // Legalizer performs DCE, so a full DCE pass is unnecessary. + CInfo.EnableFullDCE = false; + WebAssemblyPostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *VT, CSEInfo, + RuleConfig, ST, MDT, LI); + return Impl.combineMachineInstrs(); +} + +char WebAssemblyPostLegalizerCombiner::ID = 0; +INITIALIZE_PASS_BEGIN(WebAssemblyPostLegalizerCombiner, DEBUG_TYPE, + "Combine WebAssembly MachineInstrs after legalization", + false, false) +INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) +INITIALIZE_PASS_END(WebAssemblyPostLegalizerCombiner, DEBUG_TYPE, + "Combine WebAssembly MachineInstrs after legalization", + false, false) + +FunctionPass *llvm::createWebAssemblyPostLegalizerCombiner() { + return new WebAssemblyPostLegalizerCombiner(); +} diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyPreLegalizerCombiner.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyPreLegalizerCombiner.cpp new file mode 100644 index 0000000000000..81f424db67227 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyPreLegalizerCombiner.cpp @@ -0,0 +1,176 @@ +//=== WebAssemblyPreLegalizerCombiner.cpp ---------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This pass does combining of machine instructions at the generic MI level, +// before the legalizer. +// +//===----------------------------------------------------------------------===// + +#include "WebAssembly.h" +#include "WebAssemblySubtarget.h" +#include "llvm/CodeGen/GlobalISel/CSEInfo.h" +#include "llvm/CodeGen/GlobalISel/Combiner.h" +#include "llvm/CodeGen/GlobalISel/CombinerHelper.h" +#include "llvm/CodeGen/GlobalISel/CombinerInfo.h" +#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h" +#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/Target/TargetMachine.h" + +#define GET_GICOMBINER_DEPS +#include "WebAssemblyGenPreLegalizeGICombiner.inc" +#undef GET_GICOMBINER_DEPS + +#define DEBUG_TYPE "wasm-prelegalizer-combiner" + +using namespace llvm; + +namespace { + +#define GET_GICOMBINER_TYPES +#include "WebAssemblyGenPreLegalizeGICombiner.inc" +#undef GET_GICOMBINER_TYPES + +class WebAssemblyPreLegalizerCombinerImpl : public Combiner { +protected: + const CombinerHelper Helper; + const WebAssemblyPreLegalizerCombinerImplRuleConfig &RuleConfig; + const WebAssemblySubtarget &STI; + +public: + WebAssemblyPreLegalizerCombinerImpl( + MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC, + GISelValueTracking &VT, GISelCSEInfo *CSEInfo, + const WebAssemblyPreLegalizerCombinerImplRuleConfig &RuleConfig, + const WebAssemblySubtarget &STI, MachineDominatorTree *MDT, + const LegalizerInfo *LI); + + static const char *getName() { return "WebAssembly00PreLegalizerCombiner"; } + + bool tryCombineAll(MachineInstr &I) const override; + +private: +#define GET_GICOMBINER_CLASS_MEMBERS +#include "WebAssemblyGenPreLegalizeGICombiner.inc" +#undef GET_GICOMBINER_CLASS_MEMBERS +}; + +#define GET_GICOMBINER_IMPL +#include "WebAssemblyGenPreLegalizeGICombiner.inc" +#undef GET_GICOMBINER_IMPL + +WebAssemblyPreLegalizerCombinerImpl::WebAssemblyPreLegalizerCombinerImpl( + MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC, + GISelValueTracking &VT, GISelCSEInfo *CSEInfo, + const WebAssemblyPreLegalizerCombinerImplRuleConfig &RuleConfig, + const WebAssemblySubtarget &STI, MachineDominatorTree *MDT, + const LegalizerInfo *LI) + : Combiner(MF, CInfo, TPC, &VT, CSEInfo), + Helper(Observer, B, /*IsPreLegalize*/ true, &VT, MDT, LI), + RuleConfig(RuleConfig), STI(STI), +#define GET_GICOMBINER_CONSTRUCTOR_INITS +#include "WebAssemblyGenPreLegalizeGICombiner.inc" +#undef GET_GICOMBINER_CONSTRUCTOR_INITS +{ +} + +// Pass boilerplate +// ================ + +class WebAssemblyPreLegalizerCombiner : public MachineFunctionPass { +public: + static char ID; + + WebAssemblyPreLegalizerCombiner(); + + StringRef getPassName() const override { + return "WebAssemblyPreLegalizerCombiner"; + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override; + +private: + WebAssemblyPreLegalizerCombinerImplRuleConfig RuleConfig; +}; +} // end anonymous namespace + +void WebAssemblyPreLegalizerCombiner::getAnalysisUsage( + AnalysisUsage &AU) const { + AU.addRequired(); + AU.setPreservesCFG(); + getSelectionDAGFallbackAnalysisUsage(AU); + AU.addRequired(); + AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); + MachineFunctionPass::getAnalysisUsage(AU); +} + +WebAssemblyPreLegalizerCombiner::WebAssemblyPreLegalizerCombiner() + : MachineFunctionPass(ID) { + if (!RuleConfig.parseCommandLineOption()) + report_fatal_error("Invalid rule identifier"); +} + +bool WebAssemblyPreLegalizerCombiner::runOnMachineFunction( + MachineFunction &MF) { + if (MF.getProperties().hasFailedISel()) + return false; + auto &TPC = getAnalysis(); + + // Enable CSE. + GISelCSEAnalysisWrapper &Wrapper = + getAnalysis().getCSEWrapper(); + auto *CSEInfo = &Wrapper.get(TPC.getCSEConfig()); + + const WebAssemblySubtarget &ST = MF.getSubtarget(); + const auto *LI = ST.getLegalizerInfo(); + + const Function &F = MF.getFunction(); + bool EnableOpt = + MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F); + GISelValueTracking *VT = + &getAnalysis().get(MF); + MachineDominatorTree *MDT = + &getAnalysis().getDomTree(); + CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false, + /*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(), + F.hasMinSize()); + // Disable fixed-point iteration to reduce compile-time + CInfo.MaxIterations = 1; + CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass; + // This is the first Combiner, so the input IR might contain dead + // instructions. + CInfo.EnableFullDCE = true; + WebAssemblyPreLegalizerCombinerImpl Impl(MF, CInfo, &TPC, *VT, CSEInfo, + RuleConfig, ST, MDT, LI); + return Impl.combineMachineInstrs(); +} + +char WebAssemblyPreLegalizerCombiner::ID = 0; +INITIALIZE_PASS_BEGIN(WebAssemblyPreLegalizerCombiner, DEBUG_TYPE, + "Combine WebAssembly machine instrs before legalization", + false, false) +INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) +INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass) +INITIALIZE_PASS_END(WebAssemblyPreLegalizerCombiner, DEBUG_TYPE, + "Combine WebAssembly machine instrs before legalization", + false, false) + +FunctionPass *llvm::createWebAssemblyPreLegalizerCombiner() { + return new WebAssemblyPreLegalizerCombiner(); +} diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp new file mode 100644 index 0000000000000..ff0bc298dc1da --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp @@ -0,0 +1,34 @@ +//===-- WebAssemblyRegisterBankInfo.cpp -------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file implements the targeting of the RegisterBankInfo class for +/// WebAssembly. +/// \todo This should be generated by TableGen. +//===----------------------------------------------------------------------===// + +#include "WebAssemblyRegisterBankInfo.h" +#include "MCTargetDesc/WebAssemblyMCTargetDesc.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" + +#define GET_TARGET_REGBANK_IMPL + +#include "WebAssemblyGenRegisterBank.inc" + +namespace llvm { +namespace WebAssembly {} // namespace WebAssembly +} // namespace llvm + +using namespace llvm; + +WebAssemblyRegisterBankInfo::WebAssemblyRegisterBankInfo( + const TargetRegisterInfo &TRI) {} + +const RegisterBankInfo::InstructionMapping & +WebAssemblyRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { + return getInvalidInstructionMapping(); +} diff --git a/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.h b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.h new file mode 100644 index 0000000000000..9c11a3075e3d2 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.h @@ -0,0 +1,41 @@ +//===- WebAssemblyRegisterBankInfo.h ----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file declares the targeting of the RegisterBankInfo class for +/// WebAssembly. +/// \todo This should be generated by TableGen. +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYREGISTERBANKINFO_H +#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYREGISTERBANKINFO_H + +#include "llvm/CodeGen/RegisterBankInfo.h" + +#define GET_REGBANK_DECLARATIONS +#include "WebAssemblyGenRegisterBank.inc" + +namespace llvm { + +class TargetRegisterInfo; + +class WebAssemblyGenRegisterBankInfo : public RegisterBankInfo { +#define GET_TARGET_REGBANK_CLASS +#include "WebAssemblyGenRegisterBank.inc" +}; + +/// This class provides the information for the target register banks. +class WebAssemblyRegisterBankInfo final + : public WebAssemblyGenRegisterBankInfo { +public: + WebAssemblyRegisterBankInfo(const TargetRegisterInfo &TRI); + + const InstructionMapping & + getInstrMapping(const MachineInstr &MI) const override; +}; +} // end namespace llvm +#endif diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h index 2dbd597f01cc9..71647974b2843 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.h +++ b/llvm/lib/Target/WebAssembly/WebAssembly.h @@ -15,6 +15,9 @@ #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLY_H #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLY_H +#include "GISel/WebAssemblyRegisterBankInfo.h" +#include "WebAssemblySubtarget.h" +#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/PassRegistry.h" #include "llvm/Support/CodeGen.h" @@ -32,6 +35,18 @@ FunctionPass *createWebAssemblyOptimizeReturned(); FunctionPass *createWebAssemblyLowerRefTypesIntPtrConv(); FunctionPass *createWebAssemblyRefTypeMem2Local(); +// GlobalISel +InstructionSelector * +createWebAssemblyInstructionSelector(const WebAssemblyTargetMachine &, + const WebAssemblySubtarget &, + const WebAssemblyRegisterBankInfo &); + +FunctionPass *createWebAssemblyPostLegalizerCombiner(); +void initializeWebAssemblyPostLegalizerCombinerPass(PassRegistry &); + +FunctionPass *createWebAssemblyPreLegalizerCombiner(); +void initializeWebAssemblyPreLegalizerCombinerPass(PassRegistry &); + // ISel and immediate followup passes. FunctionPass *createWebAssemblyISelDag(WebAssemblyTargetMachine &TM, CodeGenOptLevel OptLevel); diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td index 67015ffcfc760..67a2331b26b6e 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.td +++ b/llvm/lib/Target/WebAssembly/WebAssembly.td @@ -101,6 +101,7 @@ def FeatureWideArithmetic : //===----------------------------------------------------------------------===// include "WebAssemblyRegisterInfo.td" +include "WebAssemblyRegisterBanks.td" //===----------------------------------------------------------------------===// // Instruction Descriptions diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index 44733f1d58924..1cacdb04fa74d 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -180,6 +180,13 @@ MCSymbolWasm *WebAssemblyAsmPrinter::getMCSymbolForFunction( } void WebAssemblyAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { + if (GV->hasCommonLinkage()) { + OutContext.reportError(SMLoc(), + "common symbols are not yet implemented for Wasm: " + + getSymbol(GV)->getName()); + return; + } + if (!WebAssembly::isWasmVarAddressSpace(GV->getAddressSpace())) { AsmPrinter::emitGlobalVariable(GV); return; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCombine.td b/llvm/lib/Target/WebAssembly/WebAssemblyCombine.td new file mode 100644 index 0000000000000..82c4a2f523e67 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCombine.td @@ -0,0 +1,22 @@ +//=- WebAssemblyCombine.td - Define Wasm Combine Rules -------*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +include "llvm/Target/GlobalISel/Combine.td" + +def WebAssemblyPreLegalizerCombiner: GICombiner< + "WebAssemblyPreLegalizerCombinerImpl", []> { +} + +// Post-legalization combines which are primarily optimizations. +def WebAssemblyPostLegalizerCombiner + : GICombiner<"WebAssemblyPostLegalizerCombinerImpl", + []> { +} diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index f4860e21e310e..c869164d96945 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -478,8 +478,8 @@ unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V, .addImm(~(~uint64_t(0) << MVT(From).getSizeInBits())); Register Result = createResultReg(&WebAssembly::I32RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, - TII.get(WebAssembly::AND_I32), Result) + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(WebAssembly::AND_I32), + Result) .addReg(Reg) .addReg(Imm); @@ -502,14 +502,26 @@ unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V, return 0; } + if (Subtarget->hasSignExt()) { + if (From == MVT::i8 || From == MVT::i16) { + Register Result = createResultReg(&WebAssembly::I32RegClass); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, + TII.get(From == MVT::i16 ? WebAssembly::I32_EXTEND16_S_I32 + : WebAssembly::I32_EXTEND8_S_I32), + Result) + .addReg(Reg); + return Result; + } + } + Register Imm = createResultReg(&WebAssembly::I32RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(WebAssembly::CONST_I32), Imm) .addImm(32 - MVT(From).getSizeInBits()); Register Left = createResultReg(&WebAssembly::I32RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, - TII.get(WebAssembly::SHL_I32), Left) + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(WebAssembly::SHL_I32), + Left) .addReg(Reg) .addReg(Imm); @@ -551,12 +563,45 @@ unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V, if (From == MVT::i64) return copyValue(Reg); - Reg = signExtendToI32(Reg, V, From); - Register Result = createResultReg(&WebAssembly::I64RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, - TII.get(WebAssembly::I64_EXTEND_S_I32), Result) - .addReg(Reg); + + if (Subtarget->hasSignExt()) { + if (From != MVT::i32) { + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, + TII.get(WebAssembly::I64_EXTEND_U_I32), Result) + .addReg(Reg); + + Reg = Result; + Result = createResultReg(&WebAssembly::I64RegClass); + } + + switch (From) { + case MVT::i8: + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, + TII.get(WebAssembly::I64_EXTEND8_S_I64), Result) + .addReg(Reg); + return Result; + case MVT::i16: + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, + TII.get(WebAssembly::I64_EXTEND16_S_I64), Result) + .addReg(Reg); + return Result; + case MVT::i32: + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, + TII.get(WebAssembly::I64_EXTEND_S_I32), Result) + .addReg(Reg); + return Result; + default: + break; + } + } else { + Reg = signExtendToI32(Reg, V, From); + + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, + TII.get(WebAssembly::I64_EXTEND_S_I32), Result) + .addReg(Reg); + } + return Result; } @@ -597,8 +642,8 @@ unsigned WebAssemblyFastISel::notValue(unsigned Reg) { assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass); Register NotReg = createResultReg(&WebAssembly::I32RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, - TII.get(WebAssembly::EQZ_I32), NotReg) + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(WebAssembly::EQZ_I32), + NotReg) .addReg(Reg); return NotReg; } @@ -1210,8 +1255,8 @@ bool WebAssemblyFastISel::selectBitCast(const Instruction *I) { return true; } - Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), - In); + Register Reg = + fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), In); if (!Reg) return false; MachineBasicBlock::iterator Iter = FuncInfo.InsertPt; @@ -1273,8 +1318,8 @@ bool WebAssemblyFastISel::selectLoad(const Instruction *I) { materializeLoadStoreOperands(Addr); Register ResultReg = createResultReg(RC); - auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), - ResultReg); + auto MIB = + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg); addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Load)); @@ -1422,8 +1467,7 @@ bool WebAssemblyFastISel::selectRet(const Instruction *I) { if (Reg == 0) return false; - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, - TII.get(WebAssembly::RETURN)) + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(WebAssembly::RETURN)) .addReg(Reg); return true; } diff --git a/libclc/opencl/lib/clspv/math/fma.cl b/llvm/lib/Target/WebAssembly/WebAssemblyGISel.td similarity index 53% rename from libclc/opencl/lib/clspv/math/fma.cl rename to llvm/lib/Target/WebAssembly/WebAssemblyGISel.td index 172ec32b8a3b3..0e49d61deca67 100644 --- a/libclc/opencl/lib/clspv/math/fma.cl +++ b/llvm/lib/Target/WebAssembly/WebAssemblyGISel.td @@ -1,16 +1,17 @@ -//===----------------------------------------------------------------------===// +//===-- WebAssemblyGISel.td - Wasm GlobalISel Patterns -----*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +// +/// \file +/// This file contains patterns that are relevant to GlobalISel, including +/// GIComplexOperandMatcher definitions for equivalent SelectionDAG +/// ComplexPatterns. +// +//===----------------------------------------------------------------------===// -#include - -#define __CLC_FLOAT_ONLY -#define __CLC_FUNCTION fma -#define __CLC_IMPL_FUNCTION(x) __clc_sw_fma -#define __CLC_BODY - -#include +include "WebAssembly.td" +include "WebAssemblyCombine.td" diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 5abf0e8f59d2a..2799b0ee0c804 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -1065,10 +1065,10 @@ EVT WebAssemblyTargetLowering::getSetCCResultType(const DataLayout &DL, return EVT::getIntegerVT(C, 32); } -bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void WebAssemblyTargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; switch (Intrinsic) { case Intrinsic::wasm_memory_atomic_notify: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -1083,7 +1083,8 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, // instructions are treated as volatiles in the backend, so we should be // consistent. The same applies for wasm_atomic_wait intrinsics too. Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::wasm_memory_atomic_wait32: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i32; @@ -1091,7 +1092,8 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(4); Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::wasm_memory_atomic_wait64: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::i64; @@ -1099,7 +1101,8 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(8); Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::wasm_loadf16_f32: Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = MVT::f16; @@ -1107,7 +1110,8 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(2); Info.flags = MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::wasm_storef16_f32: Info.opc = ISD::INTRINSIC_VOID; Info.memVT = MVT::f16; @@ -1115,9 +1119,10 @@ bool WebAssemblyTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.offset = 0; Info.align = Align(2); Info.flags = MachineMemOperand::MOStore; - return true; + Infos.push_back(Info); + return; default: - return false; + return; } } @@ -2289,13 +2294,14 @@ WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, static SDValue GetExtendHigh(SDValue Op, unsigned UserOpc, EVT VT, SelectionDAG &DAG) { - if (Op.getOpcode() != ISD::VECTOR_SHUFFLE) + SDValue Source = peekThroughBitcasts(Op); + if (Source.getOpcode() != ISD::VECTOR_SHUFFLE) return SDValue(); assert((UserOpc == WebAssemblyISD::EXTEND_LOW_U || UserOpc == WebAssemblyISD::EXTEND_LOW_S) && "expected extend_low"); - auto *Shuffle = cast(Op.getNode()); + auto *Shuffle = cast(Source.getNode()); ArrayRef Mask = Shuffle->getMask(); // Look for a shuffle which moves from the high half to the low half. @@ -2310,7 +2316,11 @@ static SDValue GetExtendHigh(SDValue Op, unsigned UserOpc, EVT VT, unsigned Opc = UserOpc == WebAssemblyISD::EXTEND_LOW_S ? WebAssemblyISD::EXTEND_HIGH_S : WebAssemblyISD::EXTEND_HIGH_U; - return DAG.getNode(Opc, DL, VT, Shuffle->getOperand(0)); + SDValue ShuffleSrc = Shuffle->getOperand(0); + if (Op.getOpcode() == ISD::BITCAST) + ShuffleSrc = DAG.getBitcast(Op.getValueType(), ShuffleSrc); + + return DAG.getNode(Opc, DL, VT, ShuffleSrc); } SDValue diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h index 204384f06ab25..b1c9db37a2b18 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h @@ -61,8 +61,8 @@ class WebAssemblyTargetLowering final : public TargetLowering { bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override; - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegisterBanks.td b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterBanks.td new file mode 100644 index 0000000000000..f0fa33b68de16 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegisterBanks.td @@ -0,0 +1,22 @@ +//=- WebAssemblyRegisterBank.td - Describe the Wasm Banks ----*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + + +def I32RegBank : RegisterBank<"I32RegBank", [I32]>; +def I64RegBank : RegisterBank<"I64RegBank", [I64]>; +def F32RegBank : RegisterBank<"F32RegBank", [F32]>; +def F64RegBank : RegisterBank<"F64RegBank", [F64]>; + +def V128RegBank : RegisterBank<"V128RegBank", [V128]>; + +def EXTERNREFRegBank : RegisterBank<"EXTERNREFRegBank", [EXTERNREF]>; +def FUNCREFRegBank : RegisterBank<"FUNCREFRegBank", [FUNCREF]>; +def EXNREFRegBank : RegisterBank<"EXNREFRegBank", [EXNREF]>; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp index a3ce40f0297ec..641eef73044cd 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp @@ -13,8 +13,13 @@ //===----------------------------------------------------------------------===// #include "WebAssemblySubtarget.h" +#include "GISel/WebAssemblyCallLowering.h" +#include "GISel/WebAssemblyLegalizerInfo.h" +#include "GISel/WebAssemblyRegisterBankInfo.h" #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" +#include "WebAssembly.h" #include "WebAssemblyInstrInfo.h" +#include "WebAssemblyTargetMachine.h" #include "llvm/MC/TargetRegistry.h" using namespace llvm; @@ -66,7 +71,15 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT, const TargetMachine &TM) : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), - TLInfo(TM, *this) {} + TLInfo(TM, *this) { + CallLoweringInfo.reset(new WebAssemblyCallLowering(*getTargetLowering())); + Legalizer.reset(new WebAssemblyLegalizerInfo(*this)); + auto *RBI = new WebAssemblyRegisterBankInfo(*getRegisterInfo()); + RegBankInfo.reset(RBI); + + InstSelector.reset(createWebAssemblyInstructionSelector( + *static_cast(&TM), *this, *RBI)); +} bool WebAssemblySubtarget::enableAtomicExpand() const { // If atomics are disabled, atomic ops are lowered instead of expanded @@ -81,3 +94,19 @@ bool WebAssemblySubtarget::enableMachineScheduler() const { } bool WebAssemblySubtarget::useAA() const { return true; } + +const CallLowering *WebAssemblySubtarget::getCallLowering() const { + return CallLoweringInfo.get(); +} + +InstructionSelector *WebAssemblySubtarget::getInstructionSelector() const { + return InstSelector.get(); +} + +const LegalizerInfo *WebAssemblySubtarget::getLegalizerInfo() const { + return Legalizer.get(); +} + +const RegisterBankInfo *WebAssemblySubtarget::getRegBankInfo() const { + return RegBankInfo.get(); +} diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h index 2f88bbba05d00..c195f995009b1 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h @@ -20,6 +20,10 @@ #include "WebAssemblyISelLowering.h" #include "WebAssemblyInstrInfo.h" #include "WebAssemblySelectionDAGInfo.h" +#include "llvm/CodeGen/GlobalISel/CallLowering.h" +#include "llvm/CodeGen/GlobalISel/InstructionSelector.h" +#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" +#include "llvm/CodeGen/RegisterBankInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include @@ -64,6 +68,11 @@ class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo { WebAssemblySelectionDAGInfo TSInfo; WebAssemblyTargetLowering TLInfo; + std::unique_ptr CallLoweringInfo; + std::unique_ptr InstSelector; + std::unique_ptr Legalizer; + std::unique_ptr RegBankInfo; + WebAssemblySubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); @@ -118,6 +127,11 @@ class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo { /// Parses features string setting specified subtarget options. Definition of /// function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); + + const CallLowering *getCallLowering() const override; + InstructionSelector *getInstructionSelector() const override; + const LegalizerInfo *getLegalizerInfo() const override; + const RegisterBankInfo *getRegBankInfo() const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index a57ebfad03b1c..ab1b24a4fd9b1 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -20,6 +20,10 @@ #include "WebAssemblyTargetObjectFile.h" #include "WebAssemblyTargetTransformInfo.h" #include "WebAssemblyUtilities.h" +#include "llvm/CodeGen/GlobalISel/IRTranslator.h" +#include "llvm/CodeGen/GlobalISel/InstructionSelect.h" +#include "llvm/CodeGen/GlobalISel/Legalizer.h" +#include "llvm/CodeGen/GlobalISel/RegBankSelect.h" #include "llvm/CodeGen/MIRParser/MIParser.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" @@ -92,6 +96,9 @@ LLVMInitializeWebAssemblyTarget() { // Register backend passes auto &PR = *PassRegistry::getPassRegistry(); + initializeGlobalISel(PR); + initializeWebAssemblyPreLegalizerCombinerPass(PR); + initializeWebAssemblyPostLegalizerCombinerPass(PR); initializeWebAssemblyAddMissingPrototypesPass(PR); initializeWebAssemblyLowerEmscriptenEHSjLjPass(PR); initializeLowerGlobalDtorsLegacyPassPass(PR); @@ -442,6 +449,13 @@ class WebAssemblyPassConfig final : public TargetPassConfig { // No reg alloc bool addRegAssignAndRewriteOptimized() override { return false; } + + bool addIRTranslator() override; + void addPreLegalizeMachineIR() override; + bool addLegalizeMachineIR() override; + void addPreRegBankSelect() override; + bool addRegBankSelect() override; + bool addGlobalInstructionSelect() override; }; } // end anonymous namespace @@ -662,6 +676,46 @@ bool WebAssemblyPassConfig::addPreISel() { return false; } +bool WebAssemblyPassConfig::addIRTranslator() { + addPass(new IRTranslator()); + return false; +} + +void WebAssemblyPassConfig::addPreLegalizeMachineIR() { + if (getOptLevel() != CodeGenOptLevel::None) { + addPass(createWebAssemblyPreLegalizerCombiner()); + } +} +bool WebAssemblyPassConfig::addLegalizeMachineIR() { + addPass(new Legalizer()); + return false; +} + +void WebAssemblyPassConfig::addPreRegBankSelect() { + if (getOptLevel() != CodeGenOptLevel::None) { + addPass(createWebAssemblyPostLegalizerCombiner()); + } +} + +bool WebAssemblyPassConfig::addRegBankSelect() { + addPass(new RegBankSelect()); + return false; +} + +bool WebAssemblyPassConfig::addGlobalInstructionSelect() { + addPass(new InstructionSelect(getOptLevel())); + + // We insert only if ISelDAG won't insert these at a later point. + if (isGlobalISelAbortEnabled()) { + addPass(createWebAssemblyArgumentMove()); + addPass(createWebAssemblySetP2AlignOperands()); + addPass(createWebAssemblyFixBrTableDefaults()); + addPass(createWebAssemblyCleanCodeAfterTrap()); + } + + return false; +} + yaml::MachineFunctionInfo * WebAssemblyTargetMachine::createDefaultFuncInfoYAML() const { return new yaml::WebAssemblyFunctionInfo(); diff --git a/llvm/lib/Target/X86/CMakeLists.txt b/llvm/lib/Target/X86/CMakeLists.txt index f2880d6c6ea5e..5cffe98e8dc81 100644 --- a/llvm/lib/Target/X86/CMakeLists.txt +++ b/llvm/lib/Target/X86/CMakeLists.txt @@ -21,7 +21,8 @@ tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget) tablegen(LLVM X86GenFoldTables.inc -gen-x86-fold-tables -asmwriternum=1) tablegen(LLVM X86GenPreLegalizeGICombiner.inc -gen-global-isel-combiner -combiners="X86PreLegalizerCombiner") - +tablegen(LLVM X86GenPostLegalizeGICombiner.inc -gen-global-isel-combiner + -combiners="X86PostLegalizerCombiner") add_public_tablegen_target(X86CommonTableGen) set(sources @@ -30,6 +31,7 @@ set(sources X86AvoidTrailingCall.cpp X86CallFrameOptimization.cpp X86CallingConv.cpp + X86CleanupLocalDynamicTLS.cpp X86CmovConversion.cpp X86CodeGenPassBuilder.cpp X86DomainReassignment.cpp @@ -89,6 +91,7 @@ set(sources GISel/X86CallLowering.cpp GISel/X86InstructionSelector.cpp GISel/X86LegalizerInfo.cpp + GISel/X86PostLegalizerCombiner.cpp GISel/X86PreLegalizerCombiner.cpp GISel/X86RegisterBankInfo.cpp ) diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp index d07185e1b62e1..bbc7f464eda4a 100644 --- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp +++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp @@ -304,7 +304,6 @@ bool X86InstructionSelector::selectCopy(MachineInstr &I, BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG)) .addDef(ExtSrc) - .addImm(0) .addReg(SrcReg) .addImm(getSubRegIndex(SrcRC)); @@ -322,7 +321,6 @@ bool X86InstructionSelector::selectCopy(MachineInstr &I, Register ExtReg = MRI.createVirtualRegister(&X86::GR32RegClass); BuildMI(*I.getParent(), I, DL, TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) - .addImm(0) .addReg(SrcReg) .addImm(X86::sub_16bit); @@ -725,9 +723,9 @@ bool X86InstructionSelector::selectLoadStoreOp(MachineInstr &I, I.removeOperand(0); addFullAddress(MIB, AM).addUse(DefReg); } - bool Constrained = constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); I.addImplicitDefUseOperands(MF); - return Constrained; + return true; } static unsigned getLeaOP(LLT Ty, const X86Subtarget &STI) { @@ -764,7 +762,8 @@ bool X86InstructionSelector::selectFrameIndexOrGep(MachineInstr &I, MIB.addImm(0).addReg(0); } - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } bool X86InstructionSelector::selectGlobalValue(MachineInstr &I, @@ -787,7 +786,8 @@ bool X86InstructionSelector::selectGlobalValue(MachineInstr &I, I.removeOperand(1); addFullAddress(MIB, AM); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } bool X86InstructionSelector::selectConstant(MachineInstr &I, @@ -834,7 +834,8 @@ bool X86InstructionSelector::selectConstant(MachineInstr &I, } I.setDesc(TII.get(NewOpc)); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } // Helper function for selectTruncOrPtrToInt and selectAnyext. @@ -1040,7 +1041,6 @@ bool X86InstructionSelector::selectAnyext(MachineInstr &I, BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG)) .addDef(DstReg) - .addImm(0) .addReg(SrcReg) .addImm(getSubRegIndex(SrcRC)); @@ -1301,8 +1301,8 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I, BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), CarryOutReg) .addImm(X86::COND_B); - if (!constrainSelectedInstRegOperands(Inst, TII, TRI, RBI) || - !RBI.constrainGenericRegister(CarryOutReg, *CarryRC, MRI)) + constrainSelectedInstRegOperands(Inst, TII, TRI, RBI); + if (!RBI.constrainGenericRegister(CarryOutReg, *CarryRC, MRI)) return false; I.eraseFromParent(); @@ -1363,7 +1363,8 @@ bool X86InstructionSelector::selectExtract(MachineInstr &I, Index = Index / DstTy.getSizeInBits(); I.getOperand(2).setImm(Index); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } bool X86InstructionSelector::emitExtractSubreg(Register DstReg, Register SrcReg, @@ -1497,7 +1498,8 @@ bool X86InstructionSelector::selectInsert(MachineInstr &I, I.getOperand(3).setImm(Index); - return constrainSelectedInstRegOperands(I, TII, TRI, RBI); + constrainSelectedInstRegOperands(I, TII, TRI, RBI); + return true; } bool X86InstructionSelector::selectUnmergeValues( @@ -1870,7 +1872,6 @@ bool X86InstructionSelector::selectMulDivRem(MachineInstr &I, } else if (RegTy.getSizeInBits() == 64) { BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) - .addImm(0) .addReg(Zero32) .addImm(X86::sub_32bit); } diff --git a/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp b/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp new file mode 100644 index 0000000000000..373d46d1b53a9 --- /dev/null +++ b/llvm/lib/Target/X86/GISel/X86PostLegalizerCombiner.cpp @@ -0,0 +1,187 @@ +//===--------------- X86PostLegalizerCombiner.cpp ---------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// Post-legalization combines on generic MachineInstrs. +/// +/// The combines here must preserve instruction legality. +/// +/// Lowering combines (e.g. pseudo matching) should be handled by +/// X86PostLegalizerLowering. +/// +/// Combines which don't rely on instruction legality should go in the +/// X86PreLegalizerCombiner. +/// +//===----------------------------------------------------------------------===// +#include "X86.h" +#include "X86TargetMachine.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/CodeGen/GlobalISel/CSEInfo.h" +#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h" +#include "llvm/CodeGen/GlobalISel/Combiner.h" +#include "llvm/CodeGen/GlobalISel/CombinerHelper.h" +#include "llvm/CodeGen/GlobalISel/CombinerInfo.h" +#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h" +#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" +#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h" +#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h" +#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetOpcodes.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/Support/Debug.h" + +#define GET_GICOMBINER_DEPS +#include "X86GenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_DEPS + +#define DEBUG_TYPE "X86-postlegalizer-combiner" + +using namespace llvm; +using namespace MIPatternMatch; + +namespace { + +#define GET_GICOMBINER_TYPES +#include "X86GenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_TYPES + +class X86PostLegalizerCombinerImpl : public Combiner { +protected: + const CombinerHelper Helper; + const X86PostLegalizerCombinerImplRuleConfig &RuleConfig; + const X86Subtarget &STI; + +public: + X86PostLegalizerCombinerImpl( + MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC, + GISelValueTracking &VT, GISelCSEInfo *CSEInfo, + const X86PostLegalizerCombinerImplRuleConfig &RuleConfig, + const X86Subtarget &STI, MachineDominatorTree *MDT, + const LegalizerInfo *LI); + + static const char *getName() { return "X86PostLegalizerCombiner"; } + + bool tryCombineAll(MachineInstr &I) const override; + bool tryCombineAllImpl(MachineInstr &I) const; + +private: +#define GET_GICOMBINER_CLASS_MEMBERS +#include "X86GenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_CLASS_MEMBERS +}; + +#define GET_GICOMBINER_IMPL +#include "X86GenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_IMPL + +X86PostLegalizerCombinerImpl::X86PostLegalizerCombinerImpl( + MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC, + GISelValueTracking &VT, GISelCSEInfo *CSEInfo, + const X86PostLegalizerCombinerImplRuleConfig &RuleConfig, + const X86Subtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI) + : Combiner(MF, CInfo, TPC, &VT, CSEInfo), + Helper(Observer, B, /*IsPreLegalize=*/false, &VT, MDT, LI), + RuleConfig(RuleConfig), STI(STI), +#define GET_GICOMBINER_CONSTRUCTOR_INITS +#include "X86GenPostLegalizeGICombiner.inc" +#undef GET_GICOMBINER_CONSTRUCTOR_INITS +{ +} + +bool X86PostLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const { + return tryCombineAllImpl(MI); +} + +class X86PostLegalizerCombiner : public MachineFunctionPass { +public: + static char ID; + + X86PostLegalizerCombiner(); + + StringRef getPassName() const override { return "X86PostLegalizerCombiner"; } + + bool runOnMachineFunction(MachineFunction &MF) override; + void getAnalysisUsage(AnalysisUsage &AU) const override; + +private: + X86PostLegalizerCombinerImplRuleConfig RuleConfig; +}; +} // end anonymous namespace + +void X86PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.setPreservesCFG(); + getSelectionDAGFallbackAnalysisUsage(AU); + AU.addRequired(); + AU.addPreserved(); + // This is only added when processing level is not OptNone. + AU.addRequired(); + AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); + + MachineFunctionPass::getAnalysisUsage(AU); +} + +X86PostLegalizerCombiner::X86PostLegalizerCombiner() : MachineFunctionPass(ID) { + if (!RuleConfig.parseCommandLineOption()) + reportFatalInternalError("Invalid rule identifier"); +} + +bool X86PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { + if (MF.getProperties().hasFailedISel()) + return false; + assert(MF.getProperties().hasLegalized() && "Expected a legalized function?"); + auto *TPC = &getAnalysis(); + const Function &F = MF.getFunction(); + + const X86Subtarget &ST = MF.getSubtarget(); + const auto *LI = ST.getLegalizerInfo(); + + GISelValueTracking *VT = + &getAnalysis().get(MF); + MachineDominatorTree *MDT = + &getAnalysis().getDomTree(); + GISelCSEAnalysisWrapper &Wrapper = + getAnalysis().getCSEWrapper(); + auto *CSEInfo = &Wrapper.get(TPC->getCSEConfig()); + + CombinerInfo CInfo(/*AllowIllegalOps=*/true, + /*ShouldLegalizeIllegal=*/false, + /*LegalizerInfo=*/nullptr, !skipFunction(F), + F.hasOptSize(), F.hasMinSize()); + // Disable fixed-point iteration to reduce compile-time + CInfo.MaxIterations = 1; + CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass; + // Legalizer performs DCE, so a full DCE pass is unnecessary. + CInfo.EnableFullDCE = false; + X86PostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *VT, CSEInfo, RuleConfig, + ST, MDT, LI); + return Impl.combineMachineInstrs(); +} + +char X86PostLegalizerCombiner::ID = 0; +INITIALIZE_PASS_BEGIN(X86PostLegalizerCombiner, DEBUG_TYPE, + "Combine X86 MachineInstrs after legalization", false, + false) +INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) +INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy) +INITIALIZE_PASS_END(X86PostLegalizerCombiner, DEBUG_TYPE, + "Combine X86 MachineInstrs after legalization", false, + false) + +namespace llvm { +FunctionPass *createX86PostLegalizerCombiner() { + return new X86PostLegalizerCombiner(); +} +} // end namespace llvm diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h index 718c5a0c96e49..8f2a852faef28 100644 --- a/llvm/lib/Target/X86/X86.h +++ b/llvm/lib/Target/X86/X86.h @@ -40,7 +40,14 @@ FunctionPass *createX86GlobalBaseRegPass(); /// This pass combines multiple accesses to local-dynamic TLS variables so that /// the TLS base address for the module is only fetched once per execution path /// through the function. -FunctionPass *createCleanupLocalDynamicTLSPass(); +class X86CleanupLocalDynamicTLSPass + : public PassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +FunctionPass *createCleanupLocalDynamicTLSLegacyPass(); /// This function returns a pass which converts floating-point register /// references and pseudo instructions into floating-point stack references and @@ -59,7 +66,14 @@ FunctionPass *createX86IssueVZeroUpperPass(); /// This pass inserts ENDBR instructions before indirect jump/call /// destinations as part of CET IBT mechanism. -FunctionPass *createX86IndirectBranchTrackingPass(); +class X86IndirectBranchTrackingPass + : public PassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +FunctionPass *createX86IndirectBranchTrackingLegacyPass(); /// Return a pass that pads short functions with NOOPs. /// This will prevent a stall when returning on the Atom. @@ -307,7 +321,14 @@ class X86PartialReductionPass : public PassInfoMixin { FunctionPass *createX86PartialReductionLegacyPass(); /// // Analyzes and emits pseudos to support Win x64 Unwind V2. -FunctionPass *createX86WinEHUnwindV2Pass(); +class X86WinEHUnwindV2Pass : public PassInfoMixin { +public: + X86WinEHUnwindV2Pass() = default; + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +FunctionPass *createX86WinEHUnwindV2LegacyPass(); /// The pass transforms load/store <256 x i32> to AMX load/store intrinsics /// or split the data to two <128 x i32>. @@ -352,8 +373,17 @@ InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM, const X86Subtarget &, const X86RegisterBankInfo &); +FunctionPass *createX86PostLegalizerCombiner(); FunctionPass *createX86PreLegalizerCombiner(); -FunctionPass *createX86LoadValueInjectionLoadHardeningPass(); + +class X86LoadValueInjectionLoadHardeningPass + : public PassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +FunctionPass *createX86LoadValueInjectionLoadHardeningLegacyPass(); class X86LoadValueInjectionRetHardeningPass : public PassInfoMixin { @@ -413,7 +443,8 @@ void initializeX86FastPreTileConfigLegacyPass(PassRegistry &); void initializeX86FastTileConfigLegacyPass(PassRegistry &); void initializeX86FixupSetCCLegacyPass(PassRegistry &); void initializeX86FlagsCopyLoweringLegacyPass(PassRegistry &); -void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &); +void initializeX86IndirectBranchTrackingLegacyPass(PassRegistry &); +void initializeX86LoadValueInjectionLoadHardeningLegacyPass(PassRegistry &); void initializeX86LoadValueInjectionRetHardeningLegacyPass(PassRegistry &); void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &); void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &); @@ -427,8 +458,9 @@ void initializeX86SpeculativeExecutionSideEffectSuppressionLegacyPass( void initializeX86SpeculativeLoadHardeningLegacyPass(PassRegistry &); void initializeX86SuppressAPXForRelocationLegacyPass(PassRegistry &); void initializeX86TileConfigLegacyPass(PassRegistry &); -void initializeX86WinEHUnwindV2Pass(PassRegistry &); +void initializeX86WinEHUnwindV2LegacyPass(PassRegistry &); void initializeX86PreLegalizerCombinerPass(PassRegistry &); +void initializeX86PostLegalizerCombinerPass(PassRegistry &); namespace X86AS { enum : unsigned { diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 1b9a6ee2b4ef4..fa41d7a7a7c5e 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -1631,6 +1631,15 @@ def ProcessorFeatures { ]; list ZN5Features = !listconcat(ZN4Features, ZN5AdditionalFeatures); + + list ZN6Tuning = ZN5Tuning; + list ZN6AdditionalFeatures = [FeatureFP16, + FeatureAVXVNNIINT8, + FeatureAVXNECONVERT, + FeatureAVXIFMA + ]; + list ZN6Features = + !listconcat(ZN5Features, ZN6AdditionalFeatures); } //===----------------------------------------------------------------------===// @@ -1993,6 +2002,8 @@ def : ProcModel<"znver4", Znver4Model, ProcessorFeatures.ZN4Features, ProcessorFeatures.ZN4Tuning>; def : ProcModel<"znver5", Znver4Model, ProcessorFeatures.ZN5Features, ProcessorFeatures.ZN5Tuning>; +def : ProcModel<"znver6", Znver4Model, ProcessorFeatures.ZN6Features, + ProcessorFeatures.ZN6Tuning>; def : Proc<"geode", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW], [TuningSlowUAMem16, TuningInsertVZEROUPPER]>; diff --git a/llvm/lib/Target/X86/X86CleanupLocalDynamicTLS.cpp b/llvm/lib/Target/X86/X86CleanupLocalDynamicTLS.cpp new file mode 100644 index 0000000000000..e3cc7a185651b --- /dev/null +++ b/llvm/lib/Target/X86/X86CleanupLocalDynamicTLS.cpp @@ -0,0 +1,165 @@ +//===- X86CleanupLocalDynamicTLS.cpp - Cleanup local dynamic TLS access ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This pass combines multiple accesses to local-dynamic TLS variables so that +// the TLS base address for the module is only fetched once per execution path +// through the function. +// +//===----------------------------------------------------------------------===// + +#include "X86.h" +#include "X86InstrInfo.h" +#include "X86MachineFunctionInfo.h" +#include "X86Subtarget.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/InitializePasses.h" + +using namespace llvm; + +#define DEBUG_TYPE "x86-cleanup-local-dynamic-tls" + +namespace { +class X86CleanupLocalDynamicTLSLegacy : public MachineFunctionPass { +public: + static char ID; + + X86CleanupLocalDynamicTLSLegacy() : MachineFunctionPass(ID) {} + + StringRef getPassName() const override { + return "Local Dynamic TLS Access Clean-up"; + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + AU.addRequired(); + MachineFunctionPass::getAnalysisUsage(AU); + } +}; +} // end anonymous namespace + +char X86CleanupLocalDynamicTLSLegacy::ID = 0; + +FunctionPass *llvm::createCleanupLocalDynamicTLSLegacyPass() { + return new X86CleanupLocalDynamicTLSLegacy(); +} + +// Replace the TLS_base_addr instruction I with a copy from +// TLSBaseAddrReg, returning the new instruction. +static MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I, + Register TLSBaseAddrReg) { + MachineFunction *MF = I.getParent()->getParent(); + const X86Subtarget &STI = MF->getSubtarget(); + const bool is64Bit = STI.is64Bit(); + const X86InstrInfo *TII = STI.getInstrInfo(); + + // Insert a Copy from TLSBaseAddrReg to RAX/EAX. + MachineInstr *Copy = + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII->get(TargetOpcode::COPY), + is64Bit ? X86::RAX : X86::EAX) + .addReg(TLSBaseAddrReg); + + // Erase the TLS_base_addr instruction. + I.eraseFromParent(); + + return Copy; +} + +// Create a virtual register in *TLSBaseAddrReg, and populate it by +// inserting a copy instruction after I. Returns the new instruction. +static MachineInstr *SetRegister(MachineInstr &I, Register *TLSBaseAddrReg) { + MachineFunction *MF = I.getParent()->getParent(); + const X86Subtarget &STI = MF->getSubtarget(); + const bool is64Bit = STI.is64Bit(); + const X86InstrInfo *TII = STI.getInstrInfo(); + + // Create a virtual register for the TLS base address. + MachineRegisterInfo &RegInfo = MF->getRegInfo(); + *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit ? &X86::GR64RegClass + : &X86::GR32RegClass); + + // Insert a copy from RAX/EAX to TLSBaseAddrReg. + MachineInstr *Next = I.getNextNode(); + MachineInstr *Copy = BuildMI(*I.getParent(), Next, I.getDebugLoc(), + TII->get(TargetOpcode::COPY), *TLSBaseAddrReg) + .addReg(is64Bit ? X86::RAX : X86::EAX); + + return Copy; +} + +// Visit the dominator subtree rooted at Node in pre-order. +// If TLSBaseAddrReg is non-null, then use that to replace any +// TLS_base_addr instructions. Otherwise, create the register +// when the first such instruction is seen, and then use it +// as we encounter more instructions. +static bool VisitNode(MachineDomTreeNode *Node, Register TLSBaseAddrReg) { + MachineBasicBlock *BB = Node->getBlock(); + bool Changed = false; + + // Traverse the current block. + for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; + ++I) { + switch (I->getOpcode()) { + case X86::TLS_base_addr32: + case X86::TLS_base_addr64: + if (TLSBaseAddrReg) + I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg); + else + I = SetRegister(*I, &TLSBaseAddrReg); + Changed = true; + break; + default: + break; + } + } + + // Visit the children of this block in the dominator tree. + for (MachineDomTreeNode *I : Node->children()) + Changed |= VisitNode(I, TLSBaseAddrReg); + + return Changed; +} + +static bool cleanupLocalDynamicTLS(MachineDominatorTree &DT) { + return VisitNode(DT.getRootNode(), Register()); +} + +static bool shouldSkipLocalDynamicTLS(MachineFunction &MF) { + X86MachineFunctionInfo *MFI = MF.getInfo(); + if (MFI->getNumLocalDynamicTLSAccesses() < 2) { + // No point folding accesses if there isn't at least two. + return true; + } + return false; +} + +bool X86CleanupLocalDynamicTLSLegacy::runOnMachineFunction( + MachineFunction &MF) { + if (skipFunction(MF.getFunction()) || shouldSkipLocalDynamicTLS(MF)) + return false; + + MachineDominatorTree &DT = + getAnalysis().getDomTree(); + return cleanupLocalDynamicTLS(DT); +} + +PreservedAnalyses +X86CleanupLocalDynamicTLSPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + if (shouldSkipLocalDynamicTLS(MF)) + return PreservedAnalyses::all(); + + MachineDominatorTree &DT = MFAM.getResult(MF); + return cleanupLocalDynamicTLS(DT) ? getMachineFunctionPassPreservedAnalyses() + .preserveSet() + : PreservedAnalyses::all(); +} diff --git a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp index 22de8da64290d..9405761fb6714 100644 --- a/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp +++ b/llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp @@ -105,8 +105,7 @@ Error X86CodeGenPassBuilder::addInstSelector(PassManagerWrapper &PMW) const { // For ELF, cleanup any local-dynamic TLS accesses if (TM.getTargetTriple().isOSBinFormatELF() && getOptLevel() != CodeGenOptLevel::None) { - // TODO(boomanaiden154): Add CleanupLocalDynamicTLSPass here once it has - // been ported. + addMachineFunctionPass(X86CleanupLocalDynamicTLSPass(), PMW); } // TODO(boomanaiden154): Add X86GlobalPassRegPass here once it has been @@ -158,7 +157,7 @@ void X86CodeGenPassBuilder::addPostRegAlloc(PassManagerWrapper &PMW) const { // mitigation. This is to prevent slow downs due to // analyses needed by the LVIHardening pass when compiling at -O0. if (getOptLevel() != CodeGenOptLevel::None) { - addMachineFunctionPass(X86LoadValueInjectionRetHardeningPass(), PMW); + addMachineFunctionPass(X86LoadValueInjectionLoadHardeningPass(), PMW); } } @@ -174,8 +173,7 @@ void X86CodeGenPassBuilder::addPreEmitPass(PassManagerWrapper &PMW) const { addMachineFunctionPass(BreakFalseDepsPass(), PMW); } - // TODO(boomanaiden154): Add X86IndirectBranchTrackingPass here once it has - // been ported. + addMachineFunctionPass(X86IndirectBranchTrackingPass(), PMW); // TODO(boomanaiden154): Add X86IssueVZeroUpperPass here once it has been // ported. @@ -234,8 +232,7 @@ void X86CodeGenPassBuilder::addPreEmitPass2(PassManagerWrapper &PMW) const { // ported. } - // TODO(boomanaiden154): Add X86LoadValueInjectionRetHardeningPass here once - // it has been ported. + addMachineFunctionPass(X86LoadValueInjectionRetHardeningPass(), PMW); // Insert pseudo probe annotation for callsite profiling // TODO(boomanaiden154): Add PseudoProberInserterPass here once it has been @@ -249,8 +246,7 @@ void X86CodeGenPassBuilder::addPreEmitPass2(PassManagerWrapper &PMW) const { // Analyzes and emits pseudos to support Win x64 Unwind V2. This pass must run // after all real instructions have been added to the epilog. if (TT.isOSWindows() && TT.isX86_64()) { - // TODO(boomanaiden154): Add X86WinEHUnwindV2Pass here once it has been - // ported. + addMachineFunctionPass(X86WinEHUnwindV2Pass(), PMW); } } diff --git a/llvm/lib/Target/X86/X86Combine.td b/llvm/lib/Target/X86/X86Combine.td index 99d1edadc83f1..b6d010c41e25f 100644 --- a/llvm/lib/Target/X86/X86Combine.td +++ b/llvm/lib/Target/X86/X86Combine.td @@ -18,3 +18,6 @@ def all_x86combines : GICombineGroup<[identity_combines, reassocs, def X86PreLegalizerCombiner : GICombiner<"X86PreLegalizerCombinerImpl", [all_x86combines]> { let CombineAllMethodName = "tryCombineAllImpl"; } +def X86PostLegalizerCombiner : GICombiner<"X86PostLegalizerCombinerImpl", [redundant_or, constant_fold_fp_ops, identity_combines, copy_prop]> { + let CombineAllMethodName = "tryCombineAllImpl"; +} diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 934ab80ae8133..bd36f2ccf4aed 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -1098,7 +1098,6 @@ bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) { Register ExtReg = createResultReg(&X86::GR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) - .addImm(0) .addReg(CopyReg) .addImm(X86::sub_32bit); Reg = ExtReg; @@ -1574,9 +1573,10 @@ bool X86FastISel::X86SelectZExt(const Instruction *I) { .addReg(ResultReg); ResultReg = createResultReg(&X86::GR64RegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG), - ResultReg) - .addImm(0).addReg(Result32).addImm(X86::sub_32bit); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, + TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) + .addReg(Result32) + .addImm(X86::sub_32bit); } else if (DstVT == MVT::i16) { // i8->i16 doesn't exist in the autogenerated isel table. Need to zero // extend to 32-bits and then extract down to 16-bits. @@ -1989,7 +1989,8 @@ bool X86FastISel::X86SelectDivRem(const Instruction *I) { } else if (VT == MVT::i64) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) - .addImm(0).addReg(Zero32).addImm(X86::sub_32bit); + .addReg(Zero32) + .addImm(X86::sub_32bit); } } } @@ -3708,7 +3709,8 @@ Register X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) { Register ResultReg = createResultReg(&X86::GR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) - .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit); + .addReg(SrcReg) + .addImm(X86::sub_32bit); return ResultReg; } } diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index c81d36a9295c0..7607fad150db0 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -486,8 +486,7 @@ namespace { if (VT == MVT::i64) { Zero = SDValue( CurDAG->getMachineNode( - TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, - CurDAG->getTargetConstant(0, dl, MVT::i64), Zero, + TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, Zero, CurDAG->getTargetConstant(X86::sub_32bit, dl, MVT::i32)), 0); } @@ -1720,11 +1719,11 @@ void X86DAGToDAGISel::PostprocessISelDAG() { } // Attempt to remove vectors moves that were inserted to zero upper bits. case TargetOpcode::SUBREG_TO_REG: { - unsigned SubRegIdx = N->getConstantOperandVal(2); + unsigned SubRegIdx = N->getConstantOperandVal(1); if (SubRegIdx != X86::sub_xmm && SubRegIdx != X86::sub_ymm) continue; - SDValue Move = N->getOperand(1); + SDValue Move = N->getOperand(0); if (!Move.isMachineOpcode()) continue; @@ -1764,7 +1763,7 @@ void X86DAGToDAGISel::PostprocessISelDAG() { // Producing instruction is another vector instruction. We can drop the // move. - CurDAG->UpdateNodeOperands(N, N->getOperand(0), In, N->getOperand(2)); + CurDAG->UpdateNodeOperands(N, In, N->getOperand(1)); MadeChange = true; } } @@ -1852,6 +1851,11 @@ bool X86DAGToDAGISel::foldOffsetIntoAddress(uint64_t Offset, !isDispSafeForFrameIndexOrRegBase((uint32_t)Val) && !AM.hasBaseOrIndexReg()) return true; + } else if (Subtarget->is16Bit()) { + // In 16-bit mode, displacements are limited to [-65535,65535] for FK_Data_2 + // fixups of unknown signedness. See X86AsmBackend::applyFixup. + if (Val < -(int64_t)UINT16_MAX || Val > (int64_t)UINT16_MAX) + return true; } else if (AM.hasBaseOrIndexReg() && !isDispSafeForFrameIndexOrRegBase(Val)) // For 32-bit X86, make sure the displacement still isn't close to the // expressible limit. @@ -5969,13 +5973,11 @@ void X86DAGToDAGISel::Select(SDNode *Node) { case MVT::i32: break; case MVT::i64: - ClrNode = - SDValue(CurDAG->getMachineNode( - TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, - CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode, - CurDAG->getTargetConstant(X86::sub_32bit, dl, - MVT::i32)), - 0); + ClrNode = SDValue( + CurDAG->getMachineNode( + TargetOpcode::SUBREG_TO_REG, dl, MVT::i64, ClrNode, + CurDAG->getTargetConstant(X86::sub_32bit, dl, MVT::i32)), + 0); break; default: llvm_unreachable("Unexpected division source"); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 15f0815fe4e06..239359b5b039e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -500,6 +500,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::SETCC, VT, Custom); } + setOperationAction(ISD::COND_LOOP, MVT::Other, Custom); + // Custom action for SELECT MMX and expand action for SELECT_CC MMX setOperationAction(ISD::SELECT, MVT::x86mmx, Custom); setOperationAction(ISD::SELECT_CC, MVT::x86mmx, Expand); @@ -1154,6 +1156,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::AND, MVT::i128, Custom); setOperationAction(ISD::OR, MVT::i128, Custom); setOperationAction(ISD::XOR, MVT::i128, Custom); + setOperationAction(ISD::SELECT, MVT::i128, Custom); if (Subtarget.hasPCLMUL()) { for (auto VT : {MVT::i64, MVT::v4i32, MVT::v2i64}) { @@ -1353,6 +1356,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, for (auto VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) { setOperationAction(ISD::BITREVERSE, VT, Custom); } + + setOperationAction(ISD::CTLZ, MVT::v16i8, Custom); + setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); } if (!Subtarget.useSoftFloat() && Subtarget.hasSSSE3()) { @@ -1507,6 +1513,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::AND, MVT::i256, Custom); setOperationAction(ISD::OR, MVT::i256, Custom); setOperationAction(ISD::XOR, MVT::i256, Custom); + setOperationAction(ISD::SELECT, MVT::i256, Custom); // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted // even though v8i16 is a legal type. @@ -1732,6 +1739,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) setOperationAction(ISD::MGATHER, VT, Custom); } + + if (Subtarget.hasGFNI()) { + setOperationAction(ISD::CTLZ, MVT::v32i8, Custom); + setOperationAction(ISD::CTTZ, MVT::v32i8, Custom); + } } if (!Subtarget.useSoftFloat() && !Subtarget.hasFP16() && @@ -1874,6 +1886,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::AND, MVT::i512, Custom); setOperationAction(ISD::OR, MVT::i512, Custom); setOperationAction(ISD::XOR, MVT::i512, Custom); + setOperationAction(ISD::ADD, MVT::i512, Custom); + setOperationAction(ISD::SUB, MVT::i512, Custom); + setOperationAction(ISD::SELECT, MVT::i512, Custom); for (MVT VT : { MVT::v16i1, MVT::v16i8 }) { setOperationPromotedToType(ISD::FP_TO_SINT , VT, MVT::v16i32); @@ -2131,6 +2146,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::FNEG, MVT::v32f16, Custom); setOperationAction(ISD::FABS, MVT::v32f16, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::v32f16, Custom); + + if (Subtarget.hasGFNI()) { + setOperationAction(ISD::CTLZ, MVT::v64i8, Custom); + setOperationAction(ISD::CTTZ, MVT::v64i8, Custom); + } }// useAVX512Regs if (!Subtarget.useSoftFloat() && Subtarget.hasVBMI2()) { @@ -2895,12 +2915,33 @@ bool X86::mayFoldIntoZeroExtend(SDValue Op) { } // Return true if its cheap to bitcast this to a vector type. -static bool mayFoldIntoVector(SDValue Op, const X86Subtarget &Subtarget, +static bool mayFoldIntoVector(SDValue Op, const SelectionDAG &DAG, + const X86Subtarget &Subtarget, bool AssumeSingleUse = false) { if (peekThroughBitcasts(Op).getValueType().isVector()) return true; if (isa(Op) || isa(Op)) return true; + EVT VT = Op.getValueType(); + unsigned Opcode = Op.getOpcode(); + if ((VT == MVT::i128 || VT == MVT::i256 || VT == MVT::i512) && + DAG.getTargetLoweringInfo().getOperationAction(Opcode, VT) == + TargetLowering::LegalizeAction::Custom) { + // Check for larger than legal scalar integer ops that might have been + // custom lowered to vector instruction. + switch (Opcode) { + case ISD::AND: + case ISD::OR: + case ISD::XOR: + case ISD::ADD: + case ISD::SUB: + return mayFoldIntoVector(Op.getOperand(0), DAG, Subtarget) && + mayFoldIntoVector(Op.getOperand(1), DAG, Subtarget); + case ISD::SELECT: + return mayFoldIntoVector(Op.getOperand(1), DAG, Subtarget) && + mayFoldIntoVector(Op.getOperand(2), DAG, Subtarget); + } + } return X86::mayFoldLoad(Op, Subtarget, AssumeSingleUse, /*IgnoreAlignment=*/true); } @@ -3164,10 +3205,10 @@ static bool useVPTERNLOG(const X86Subtarget &Subtarget, MVT VT) { VT.is512BitVector(); } -bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallBase &I, - MachineFunction &MF, - unsigned Intrinsic) const { +void X86TargetLowering::getTgtMemIntrinsic( + SmallVectorImpl &Infos, const CallBase &I, + MachineFunction &MF, unsigned Intrinsic) const { + IntrinsicInfo Info; Info.flags = MachineMemOperand::MONone; Info.offset = 0; @@ -3181,7 +3222,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::x86_aesenc256kl: case Intrinsic::x86_aesdec256kl: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -3189,7 +3231,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::x86_aesencwide128kl: case Intrinsic::x86_aesdecwide128kl: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -3197,7 +3240,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 48); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::x86_aesencwide256kl: case Intrinsic::x86_aesdecwide256kl: Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -3205,7 +3249,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), 64); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - return true; + Infos.push_back(Info); + return; case Intrinsic::x86_cmpccxadd32: case Intrinsic::x86_cmpccxadd64: case Intrinsic::x86_atomic_bts: @@ -3218,7 +3263,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(Size); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::x86_atomic_bts_rm: case Intrinsic::x86_atomic_btc_rm: @@ -3230,7 +3276,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(Size); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } case Intrinsic::x86_aadd32: case Intrinsic::x86_aadd64: @@ -3252,10 +3299,11 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.align = Align(Size); Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | MachineMemOperand::MOVolatile; - return true; + Infos.push_back(Info); + return; } } - return false; + return; } switch (IntrData->Type) { @@ -3276,7 +3324,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVectorVT(ScalarVT, VT.getVectorNumElements()); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - break; + Infos.push_back(Info); + return; } case GATHER: case GATHER_AVX2: { @@ -3289,7 +3338,8 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts); Info.align = Align(1); Info.flags |= MachineMemOperand::MOLoad; - break; + Infos.push_back(Info); + return; } case SCATTER: { Info.opc = ISD::INTRINSIC_VOID; @@ -3301,13 +3351,12 @@ bool X86TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, Info.memVT = MVT::getVectorVT(DataVT.getVectorElementType(), NumElts); Info.align = Align(1); Info.flags |= MachineMemOperand::MOStore; - break; + Infos.push_back(Info); + return; } default: - return false; + return; } - - return true; } /// Returns true if the target can instruction select the @@ -18313,6 +18362,16 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef Mask, DAG.getVectorShuffle(OpVT, DL, Op1, DAG.getUNDEF(OpVT), Mask), CC); } + // If this is a sequential shuffle with zero'd elements - then lower to AND. + bool IsBlendWithZero = all_of(enumerate(Mask), [&Zeroable](auto M) { + return Zeroable[M.index()] || (M.value() == (int)M.index()); + }); + if (IsBlendWithZero) { + EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), NumElts); + SDValue BlendMask = DAG.getConstant(~Zeroable, DL, IntVT); + return DAG.getNode(ISD::AND, DL, VT, V1, DAG.getBitcast(VT, BlendMask)); + } + MVT ExtVT; switch (VT.SimpleTy) { default: @@ -23229,8 +23288,8 @@ static SDValue combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y, // Don't perform this combine if constructing the vector will be expensive. // TODO: Drop AssumeSingleUse = true override. - if ((!mayFoldIntoVector(X, Subtarget, /*AssumeSingleUse=*/true) || - !mayFoldIntoVector(Y, Subtarget, /*AssumeSingleUse=*/true)) && + if ((!mayFoldIntoVector(X, DAG, Subtarget, /*AssumeSingleUse=*/true) || + !mayFoldIntoVector(Y, DAG, Subtarget, /*AssumeSingleUse=*/true)) && !IsOrXorXorTreeCCZero) return SDValue(); @@ -26063,12 +26122,24 @@ static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { Op.getOperand(1).hasOneUse()); } -SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { +SDValue X86TargetLowering::LowerConditionalBranch(SDValue Op, + SelectionDAG &DAG) const { SDValue Chain = Op.getOperand(0); SDValue Cond = Op.getOperand(1); - SDValue Dest = Op.getOperand(2); + SDValue Dest; + if (Op.getOpcode() == ISD::BRCOND) + Dest = Op.getOperand(2); + SDLoc dl(Op); + auto GetLoweredBranch = [&](SDValue CC, SDValue EFLAGS) { + if (Op.getOpcode() == ISD::BRCOND) + return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC, + EFLAGS, Op->getFlags()); + return DAG.getNode(X86ISD::BRCOND_SELF, dl, MVT::Other, Chain, CC, EFLAGS, + Op->getFlags()); + }; + // Bail out when we don't have native compare instructions. if (Cond.getOpcode() == ISD::SETCC && Cond.getOperand(0).getValueType() != MVT::f128 && @@ -26091,15 +26162,13 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { X86Cond = X86::GetOppositeBranchCondition(X86Cond); SDValue CCVal = DAG.getTargetConstant(X86Cond, dl, MVT::i8); - return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, - Overflow, Op->getFlags()); + return GetLoweredBranch(CCVal, Overflow); } if (LHS.getSimpleValueType().isInteger()) { SDValue CCVal; SDValue EFLAGS = emitFlagsForSetcc(LHS, RHS, CC, SDLoc(Cond), DAG, CCVal); - return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, - EFLAGS, Op->getFlags()); + return GetLoweredBranch(CCVal, EFLAGS); } if (CC == ISD::SETOEQ) { @@ -26108,7 +26177,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { // separate test. However, we only do this if this block doesn't // have a fall-through edge, because this requires an explicit // jmp when the condition is false. - if (Op.getNode()->hasOneUse()) { + if (Op.getOpcode() == ISD::BRCOND && Op.getNode()->hasOneUse()) { SDNode *User = *Op.getNode()->user_begin(); // Look for an unconditional branch following this conditional branch. // We need this because we need to reverse the successors in order @@ -26124,11 +26193,9 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { SDValue Cmp = DAG.getNode(X86ISD::FCMP, SDLoc(Cond), MVT::i32, LHS, RHS); SDValue CCVal = DAG.getTargetConstant(X86::COND_NE, dl, MVT::i8); - Chain = DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, - CCVal, Cmp, Op->getFlags()); + Chain = GetLoweredBranch(CCVal, Cmp); CCVal = DAG.getTargetConstant(X86::COND_P, dl, MVT::i8); - return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, - Cmp, Op->getFlags()); + return GetLoweredBranch(CCVal, Cmp); } } } else if (CC == ISD::SETUNE) { @@ -26137,18 +26204,15 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { // separate test. SDValue Cmp = DAG.getNode(X86ISD::FCMP, SDLoc(Cond), MVT::i32, LHS, RHS); SDValue CCVal = DAG.getTargetConstant(X86::COND_NE, dl, MVT::i8); - Chain = DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, - Cmp, Op->getFlags()); + Chain = GetLoweredBranch(CCVal, Cmp); CCVal = DAG.getTargetConstant(X86::COND_P, dl, MVT::i8); - return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, - Cmp, Op->getFlags()); + return GetLoweredBranch(CCVal, Cmp); } else { X86::CondCode X86Cond = TranslateX86CC(CC, dl, /*IsFP*/ true, LHS, RHS, DAG); SDValue Cmp = DAG.getNode(X86ISD::FCMP, SDLoc(Cond), MVT::i32, LHS, RHS); SDValue CCVal = DAG.getTargetConstant(X86Cond, dl, MVT::i8); - return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, - Cmp, Op->getFlags()); + return GetLoweredBranch(CCVal, Cmp); } } @@ -26158,8 +26222,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { std::tie(Value, Overflow) = getX86XALUOOp(X86Cond, Cond.getValue(0), DAG); SDValue CCVal = DAG.getTargetConstant(X86Cond, dl, MVT::i8); - return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, - Overflow, Op->getFlags()); + return GetLoweredBranch(CCVal, Overflow); } // Look past the truncate if the high bits are known zero. @@ -26178,8 +26241,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { SDValue CCVal; SDValue EFLAGS = emitFlagsForSetcc(LHS, RHS, ISD::SETNE, dl, DAG, CCVal); - return DAG.getNode(X86ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, EFLAGS, - Op->getFlags()); + return GetLoweredBranch(CCVal, EFLAGS); } // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. @@ -29215,6 +29277,9 @@ uint64_t getGFNICtrlImm(unsigned Opcode, unsigned Amt = 0) { switch (Opcode) { case ISD::BITREVERSE: return 0x8040201008040201ULL; + case ISD::CTTZ: + // Special case - only works for zero/single bit input. + return 0xAACCF0FF00000000ULL; case ISD::SHL: return ((0x0102040810204080ULL >> (Amt)) & (0x0101010101010101ULL * (0xFF >> (Amt)))); @@ -29368,10 +29433,16 @@ static SDValue LowerVectorCTLZ(SDValue Op, const SDLoc &DL, const X86Subtarget &Subtarget, SelectionDAG &DAG) { MVT VT = Op.getSimpleValueType(); + MVT EltVT = VT.getVectorElementType(); + + // GFNI targets - fold vXi8 as cttz(bitreverse()) + if (Subtarget.hasGFNI() && EltVT == MVT::i8) + return DAG.getNode(ISD::CTTZ, DL, VT, + DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(0))); if (Subtarget.hasCDI() && // vXi8 vectors need to be promoted to 512-bits for vXi32. - (Subtarget.canExtendTo512DQ() || VT.getVectorElementType() != MVT::i8)) + (Subtarget.canExtendTo512DQ() || EltVT != MVT::i8)) return LowerVectorCTLZ_AVX512CDI(Op, DAG, Subtarget); // Decompose 256-bit ops into smaller 128-bit ops. @@ -29386,30 +29457,6 @@ static SDValue LowerVectorCTLZ(SDValue Op, const SDLoc &DL, return LowerVectorCTLZInRegLUT(Op, DL, Subtarget, DAG); } -static SDValue LowerVectorCTLZ_GFNI(SDValue Op, const SDLoc &DL, - SelectionDAG &DAG, - const X86Subtarget &Subtarget) { - MVT VT = Op.getSimpleValueType(); - SDValue Input = Op.getOperand(0); - - assert(VT.isVector() && VT.getVectorElementType() == MVT::i8 && - "Expected vXi8 input for GFNI-based CTLZ lowering"); - - SDValue Reversed = DAG.getNode(ISD::BITREVERSE, DL, VT, Input); - - SDValue Neg = DAG.getNegative(Reversed, DL, VT); - SDValue Filtered = DAG.getNode(ISD::AND, DL, VT, Reversed, Neg); - - MVT VT64 = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64); - SDValue CTTZConst = DAG.getConstant(0xAACCF0FF00000000ULL, DL, VT64); - SDValue CTTZMatrix = DAG.getBitcast(VT, CTTZConst); - - SDValue LZCNT = - DAG.getNode(X86ISD::GF2P8AFFINEQB, DL, VT, Filtered, CTTZMatrix, - DAG.getTargetConstant(8, DL, MVT::i8)); - return LZCNT; -} - static SDValue LowerCTLZ(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG) { MVT VT = Op.getSimpleValueType(); @@ -29418,9 +29465,6 @@ static SDValue LowerCTLZ(SDValue Op, const X86Subtarget &Subtarget, SDLoc dl(Op); unsigned Opc = Op.getOpcode(); - if (VT.isVector() && VT.getScalarType() == MVT::i8 && Subtarget.hasGFNI()) - return LowerVectorCTLZ_GFNI(Op, dl, DAG, Subtarget); - if (VT.isVector()) return LowerVectorCTLZ(Op, dl, Subtarget, DAG); @@ -29467,6 +29511,15 @@ static SDValue LowerCTTZ(SDValue Op, const X86Subtarget &Subtarget, SDLoc dl(Op); bool NonZeroSrc = DAG.isKnownNeverZero(N0); + // GFNI - isolate LSB and perform GF2P8AFFINEQB lookup. + if (Subtarget.hasGFNI() && VT.isVector() && + VT.getVectorElementType() == MVT::i8) { + SDValue B = DAG.getNode(ISD::AND, dl, VT, N0, DAG.getNegative(N0, dl, VT)); + SDValue M = getGFNICtrlMask(ISD::CTTZ, DAG, dl, VT); + return DAG.getNode(X86ISD::GF2P8AFFINEQB, dl, VT, B, M, + DAG.getTargetConstant(0x8, dl, MVT::i8)); + } + assert(!VT.isVector() && Op.getOpcode() == ISD::CTTZ && "Only scalar CTTZ requires custom lowering"); @@ -34092,7 +34145,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::STRICT_FSETCCS: return LowerSETCC(Op, DAG); case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG); case ISD::SELECT: return LowerSELECT(Op, DAG); - case ISD::BRCOND: return LowerBRCOND(Op, DAG); + case ISD::COND_LOOP: + case ISD::BRCOND: return LowerConditionalBranch(Op, DAG); case ISD::JumpTable: return LowerJumpTable(Op, DAG); case ISD::VASTART: return LowerVASTART(Op, DAG); case ISD::VAARG: return LowerVAARG(Op, DAG); @@ -34235,13 +34289,107 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, "Unexpected VT!"); // See if this is free to perform on the FPU to avoid splitting. MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64); - if (!mayFoldIntoVector(N0, Subtarget) || !mayFoldIntoVector(N1, Subtarget)) + if (!mayFoldIntoVector(N0, DAG, Subtarget) || + !mayFoldIntoVector(N1, DAG, Subtarget)) return; SDValue Op = DAG.getNode(Opc, dl, VecVT, DAG.getBitcast(VecVT, N0), DAG.getBitcast(VecVT, N1)); Results.push_back(DAG.getBitcast(VT, Op)); return; } + case ISD::SELECT: { + SDValue Cond = N->getOperand(0); + SDValue TVal = N->getOperand(1); + SDValue FVal = N->getOperand(2); + EVT VT = N->getValueType(0); + assert((VT == MVT::i128 || VT == MVT::i256 || VT == MVT::i512) && + "Unexpected VT!"); + // See if this is free to perform on the FPU to avoid splitting. + if (Cond.getValueType() != MVT::i1 || + !mayFoldIntoVector(TVal, DAG, Subtarget) || + !mayFoldIntoVector(FVal, DAG, Subtarget)) + return; + // Splat selection bit to all-bit selection mask. + MVT VecVT = MVT::getVectorVT(MVT::i32, VT.getSizeInBits() / 32); + MVT CondVT = VecVT.changeVectorElementType(MVT::i1); + if (isTypeLegal(CondVT)) { + MVT CondIntVT = MVT::getIntegerVT(CondVT.getVectorNumElements()); + Cond = DAG.getNode(ISD::SIGN_EXTEND, dl, CondIntVT, Cond); + Cond = DAG.getBitcast(CondVT, Cond); + } else { + Cond = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, Cond); + Cond = DAG.getSetCC(dl, CondVT, DAG.getConstant(0, dl, VecVT), + DAG.getSplatBuildVector(VecVT, dl, Cond), + ISD::CondCode::SETGT); + } + SDValue Op = DAG.getSelect(dl, VecVT, Cond, DAG.getBitcast(VecVT, TVal), + DAG.getBitcast(VecVT, FVal)); + Results.push_back(DAG.getBitcast(VT, Op)); + return; + } + case ISD::ADD: + case ISD::SUB: { + // TODO: ISD::UADDO_CARRY + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + EVT VT = N->getValueType(0); + bool IsAdd = Opc == ISD::ADD; + assert(Subtarget.useAVX512Regs() && "AVX512 required"); + assert(VT == MVT::i512 && "Unexpected VT!"); + + if (!mayFoldIntoVector(LHS, DAG, Subtarget) || + !mayFoldIntoVector(RHS, DAG, Subtarget)) + return; + + MVT VecVT = MVT::v8i64; + MVT BoolVT = MVT::v8i1; + + if (isOneConstant(RHS)) { + RHS = DAG.getAllOnesConstant(dl, VecVT); + ; + Opc = (IsAdd ? ISD::SUB : ISD::ADD); + IsAdd = !IsAdd; + // LHS + 1 => LHS - (- 1 , LHS - 1 => LHS + (- 1) + // we utilize var `AllOnes` to do less work, this optimization makes snese + // since inc/dec operations are common :) + } + + SDValue Vec0 = DAG.getBitcast(VecVT, LHS); + SDValue Vec1 = DAG.getBitcast(VecVT, RHS); + + SDValue Partial = DAG.getNode(Opc, dl, VecVT, Vec0, Vec1); + + ISD::CondCode CarryCC = IsAdd ? ISD::SETULT : ISD::SETUGT; + SDValue Carry = DAG.getSetCC(dl, BoolVT, Partial, Vec0, CarryCC); + + SDValue PropCmp = IsAdd ? DAG.getAllOnesConstant(dl, VecVT) + : DAG.getConstant(0, dl, VecVT); + SDValue Propagate = DAG.getSetCC(dl, BoolVT, Partial, PropCmp, ISD::SETEQ); + + SDValue CarryIn = DAG.getBitcast(MVT::i8, Carry); + SDValue PropIn = DAG.getBitcast(MVT::i8, Propagate); + CarryIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, CarryIn); + PropIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, PropIn); + + SDValue ShiftedCarry = + DAG.getNode(ISD::SHL, dl, MVT::i32, CarryIn, + DAG.getShiftAmountConstant(1, MVT::i8, dl)); + SDValue CarryOut = + DAG.getNode(ISD::ADD, dl, MVT::i32, ShiftedCarry, PropIn); + + SDValue CorrMask = DAG.getNode(ISD::XOR, dl, MVT::i32, PropIn, CarryOut); + CorrMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CorrMask); + SDValue CorrVec = DAG.getBitcast(BoolVT, CorrMask); + + unsigned AdjustOpc = IsAdd ? ISD::SUB : ISD::ADD; + SDValue Adjusted = DAG.getNode(AdjustOpc, dl, VecVT, Partial, + DAG.getAllOnesConstant(dl, VecVT)); + SDValue Res = + DAG.getNode(ISD::VSELECT, dl, VecVT, CorrVec, Adjusted, Partial); + + Results.push_back(DAG.getBitcast(VT, Res)); + return; + } case ISD::CTPOP: { assert(N->getValueType(0) == MVT::i64 && "Unexpected VT!"); // If we have at most 32 active bits, then perform as i32 CTPOP. @@ -34287,7 +34435,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, EVT VT = N->getValueType(0); assert(Subtarget.hasCDI() && "AVX512CD required"); assert((VT == MVT::i256 || VT == MVT::i512) && "Unexpected VT!"); - if (VT == MVT::i256 && !mayFoldIntoVector(N0, Subtarget)) + if (VT == MVT::i256 && !mayFoldIntoVector(N0, DAG, Subtarget)) return; unsigned SizeInBits = VT.getSizeInBits(); @@ -35494,6 +35642,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(FSETCCM_SAE) NODE_NAME_CASE(CMOV) NODE_NAME_CASE(BRCOND) + NODE_NAME_CASE(BRCOND_SELF) NODE_NAME_CASE(RET_GLUE) NODE_NAME_CASE(IRET) NODE_NAME_CASE(REP_STOS) @@ -36498,7 +36647,6 @@ X86TargetLowering::EmitVAARGWithCustomInserter(MachineInstr &MI, // Zero-extend the offset Register OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); BuildMI(offsetMBB, MIMD, TII->get(X86::SUBREG_TO_REG), OffsetReg64) - .addImm(0) .addReg(OffsetReg) .addImm(X86::sub_32bit); @@ -37761,9 +37909,8 @@ X86TargetLowering::emitLongJmpShadowStackFix(MachineInstr &MI, if (PVT == MVT::i64) { Register TmpZReg = MRI.createVirtualRegister(PtrRC); BuildMI(checkSspMBB, MIMD, TII->get(X86::SUBREG_TO_REG), TmpZReg) - .addImm(0) - .addReg(ZReg) - .addImm(X86::sub_32bit); + .addReg(ZReg) + .addImm(X86::sub_32bit); ZReg = TmpZReg; } @@ -38137,7 +38284,6 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI, .addReg(0); // movzx IReg64, IReg BuildMI(DispContBB, MIMD, TII->get(TargetOpcode::SUBREG_TO_REG), IReg64) - .addImm(0) .addReg(IReg) .addImm(X86::sub_32bit); @@ -39286,7 +39432,6 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, // If the mask control (lower 8 bits) is less than the bitwidth, then the // upper bits are set to zero: dst[BW:IMM8] = 0 - // TODO: Generalise this to use Known2 getMinValue() + getMaxValue(). Known2 = Known2.trunc(8); if (Known2.isConstant()) { uint64_t Mask = Known2.getConstant().getZExtValue(); @@ -39298,6 +39443,27 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op, } } + // If the mask control minimum value is >= bitwidth, + // the src knownbits are valid and can be returned + APInt MaskMinValue = Known2.getMinValue(); + if (MaskMinValue.uge(BitWidth)) + break; + + // If the mask control maximum value is < bitwidth, + // all src knownbits above maximum value are cleared to zero + // all src knownbits below minimum value stay + // in between only src known zero bits remain + APInt MaskMaxValue = Known2.getMaxValue(); + if (MaskMaxValue.ult(BitWidth)) { + uint64_t MinValue = MaskMinValue.getZExtValue(); + uint64_t MaxValue = MaskMaxValue.getZExtValue(); + Known.One.clearBits(MaxValue, BitWidth); + Known.Zero.setBits(MaxValue, BitWidth); + + Known.One.clearBits(MinValue, MaxValue); + break; + } + // Zeros are retained from the src operand. But not necessarily ones. Known.One.clearAllBits(); break; @@ -43463,6 +43629,15 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL, return SDValue(); } + case X86ISD::EXPAND: { + SDValue ExpVec = N.getOperand(0); + SDValue PassThru = N.getOperand(1); + SDValue ExpMask = N.getOperand(2); + if (auto *Msk = dyn_cast(peekThroughBitcasts(ExpMask))) + if (Msk->getAPIntValue().isMask()) + return DAG.getSelect(DL, VT, ExpMask, ExpVec, PassThru); + return SDValue(); + } case X86ISD::VPERMV: { // Combine VPERMV to VPERMV3 if the source operand can be freely split. SmallVector Mask; @@ -48500,6 +48675,8 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, } if (Opcode) { + // Propagate fast-math-flags. + SelectionDAG::FlagInserter FlagsInserter(DAG, N->getFlags()); if (IsStrict) { SDValue Ret = DAG.getNode(Opcode == X86ISD::FMIN ? X86ISD::STRICT_FMIN : X86ISD::STRICT_FMAX, @@ -54043,8 +54220,8 @@ static SDValue combineMaskedLoad(SDNode *N, SelectionDAG &DAG, return SDValue(); } -/// If exactly one element of the mask is set for a non-truncating masked store, -/// it is a vector extract and scalar store. +/// If exactly one element of the mask is set for a masked store, it is a vector +/// extract, truncate (iff truncating store) and scalar store. /// Note: It is expected that the degenerate cases of an all-zeros or all-ones /// mask have already been optimized in IR, so we don't bother with those here. static SDValue reduceMaskedStoreToScalarStore(MaskedStoreSDNode *MS, @@ -54073,6 +54250,14 @@ static SDValue reduceMaskedStoreToScalarStore(MaskedStoreSDNode *MS, SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Value, VecIndex); + if (MS->isTruncatingStore()) { + if (EltVT.isFloatingPoint()) + return SDValue(); + + Extract = DAG.getNode(ISD::TRUNCATE, DL, + MS->getMemoryVT().getVectorElementType(), Extract); + } + // Store that element at the appropriate offset from the base pointer. return DAG.getStore(MS->getChain(), DL, Extract, Addr, MS->getPointerInfo().getWithOffset(Offset), @@ -54102,7 +54287,8 @@ static SDValue combineMaskedStore(SDNode *N, SelectionDAG &DAG, if (VT.isVector() && MemVT.isVector() && VT.getScalarType().isInteger() && MemVT.getScalarType().isInteger() && VT.getVectorNumElements() == MemVT.getVectorNumElements() && - Subtarget.hasBWI() && Subtarget.hasVLX()) { + Subtarget.hasBWI() && + (VT.getSizeInBits() == 512 || Subtarget.hasVLX())) { SDValue SatSrc; unsigned Opc; @@ -54553,10 +54739,7 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG, if (VT == MVT::i256 || VT == MVT::i512) { MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64); if (TLI.isTypeLegal(VecVT) && ISD::isNormalStore(St) && - (mayFoldIntoVector(StoredVal, Subtarget) || - (DCI.isBeforeLegalize() && - TLI.getOperationAction(StoredVal.getOpcode(), VT) == - TargetLowering::LegalizeAction::Custom))) + mayFoldIntoVector(StoredVal, DAG, Subtarget)) return DAG.getStore(St->getChain(), dl, DAG.getBitcast(VecVT, StoredVal), St->getBasePtr(), St->getPointerInfo(), St->getBaseAlign(), St->getMemOperand()->getFlags()); @@ -55850,6 +56033,32 @@ static SDValue foldXor1SetCC(SDNode *N, const SDLoc &DL, SelectionDAG &DAG) { return getSETCC(NewCC, LHS->getOperand(1), DL, DAG); } +static SDValue combineXorWithGF2P8AFFINEQB(SDNode *N, const SDLoc &DL, + SelectionDAG &DAG, EVT VT) { + using namespace SDPatternMatch; + + SDValue X, Y, SplatOp; + APInt Imm; + // Use sd_match for structure matching - m_Xor handles commutation + if (!sd_match(N, m_Xor(m_OneUse(m_TernaryOp(X86ISD::GF2P8AFFINEQB, m_Value(X), + m_Value(Y), m_ConstInt(Imm))), + m_Value(SplatOp)))) + return SDValue(); + + // GF2P8AFFINEQB only operates on i8 vector types + assert((VT == MVT::v16i8 || VT == MVT::v32i8 || VT == MVT::v64i8) && + "Unsupported GFNI type"); + + // Use X86::isConstantSplat for robust splat constant extraction + APInt SplatVal; + if (!X86::isConstantSplat(SplatOp, SplatVal, /*AllowPartialUndefs=*/false)) + return SDValue(); + + uint64_t NewImm = Imm.getZExtValue() ^ SplatVal.getZExtValue(); + return DAG.getNode(X86ISD::GF2P8AFFINEQB, DL, VT, X, Y, + DAG.getTargetConstant(NewImm, DL, MVT::i8)); +} + static SDValue combineXorSubCTLZ(SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const X86Subtarget &Subtarget) { assert((N->getOpcode() == ISD::XOR || N->getOpcode() == ISD::SUB) && @@ -55952,6 +56161,8 @@ static SDValue combineXor(SDNode *N, SelectionDAG &DAG, if (SDValue RV = foldXorTruncShiftIntoCmp(N, DL, DAG)) return RV; + if (SDValue R = combineXorWithGF2P8AFFINEQB(N, DL, DAG, VT)) + return R; // Fold not(iX bitcast(vXi1)) -> (iX bitcast(not(vec))) for legal boolvecs. const TargetLowering &TLI = DAG.getTargetLoweringInfo(); @@ -56157,8 +56368,9 @@ static SDValue combineFMinFMax(SDNode *N, SelectionDAG &DAG) { assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX); // FMIN/FMAX are commutative if no NaNs and no negative zeros are allowed. - if (!DAG.getTarget().Options.NoNaNsFPMath || - !DAG.getTarget().Options.NoSignedZerosFPMath) + if ((!DAG.getTarget().Options.NoNaNsFPMath && !N->getFlags().hasNoNaNs()) || + (!DAG.getTarget().Options.NoSignedZerosFPMath && + !N->getFlags().hasNoSignedZeros())) return SDValue(); // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes @@ -57276,12 +57488,6 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG, EVT OpVT = LHS.getValueType(); SDLoc DL(N); - if (CC == ISD::SETNE || CC == ISD::SETEQ) { - if (SDValue V = combineVectorSizedSetCCEquality(VT, LHS, RHS, CC, DL, DAG, - Subtarget)) - return V; - } - if (VT == MVT::i1) { X86::CondCode X86CC; if (SDValue V = @@ -57397,6 +57603,10 @@ static SDValue combineSetCC(SDNode *N, SelectionDAG &DAG, } } } + + if (SDValue V = combineVectorSizedSetCCEquality(VT, LHS, RHS, CC, DL, DAG, + Subtarget)) + return V; } if (VT.isVector() && VT.getVectorElementType() == MVT::i1 && @@ -58309,7 +58519,11 @@ static SDValue combineFunnelShift(SDNode *N, SelectionDAG &DAG, static bool needCarryOrOverflowFlag(SDValue Flags) { assert(Flags.getValueType() == MVT::i32 && "Unexpected VT!"); - for (const SDNode *User : Flags->users()) { + for (const SDUse &Use : Flags->uses()) { + // Only check things that use the flags. + if (Use.getResNo() != Flags.getResNo()) + continue; + const SDNode *User = Use.getUser(); X86::CondCode CC; switch (User->getOpcode()) { default: @@ -58653,7 +58867,7 @@ static SDValue combineADC(SDNode *N, SelectionDAG &DAG, // Fold ADC(ADD(X,Y),0,Carry) -> ADC(X,Y,Carry) // iff the flag result is dead. if (LHS.getOpcode() == ISD::ADD && RHSC && RHSC->isZero() && - !N->hasAnyUseOfValue(1)) + !needCarryOrOverflowFlag(SDValue(N, 1))) return DAG.getNode(X86ISD::ADC, SDLoc(N), N->getVTList(), LHS.getOperand(0), LHS.getOperand(1), CarryIn); diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 30faca54e13f6..fc16053caa705 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -143,6 +143,11 @@ namespace llvm { /// or TEST instruction. BRCOND, + /// X86 conditional branch to self, used for implementing efficient + /// conditional traps. Operand 0 is the chain operand, operand 1 is the + /// condition code, and operand 2 is the flag operand. + BRCOND_SELF, + /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and /// operand 1 is the target address. NT_BRIND, @@ -1503,12 +1508,12 @@ namespace llvm { unsigned SelectOpcode, SDValue X, SDValue Y) const override; - /// Given an intrinsic, checks if on the target the intrinsic will need to map - /// to a MemIntrinsicNode (touches memory). If this is the case, it returns - /// true and stores the intrinsic information into the IntrinsicInfo that was - /// passed to the function. - bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, - MachineFunction &MF, + /// Given an intrinsic, checks if on the target the intrinsic will need to + /// map to a MemIntrinsicNode (touches memory). If this is the case, it + /// returns true and stores the intrinsic information into the IntrinsicInfo + /// that was passed to the function. + void getTgtMemIntrinsic(SmallVectorImpl &Infos, + const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override; /// Returns true if the target can instruction select the @@ -1798,7 +1803,7 @@ namespace llvm { SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerConditionalBranch(SDValue Op, SelectionDAG &DAG) const; SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp b/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp index 52be14228e555..6ccad26a890dd 100644 --- a/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp +++ b/llvm/lib/Target/X86/X86IndirectBranchTracking.cpp @@ -36,42 +36,29 @@ cl::opt IndirectBranchTracking( STATISTIC(NumEndBranchAdded, "Number of ENDBR instructions added"); namespace { -class X86IndirectBranchTrackingPass : public MachineFunctionPass { +class X86IndirectBranchTrackingLegacy : public MachineFunctionPass { public: - X86IndirectBranchTrackingPass() : MachineFunctionPass(ID) {} + static char ID; + + X86IndirectBranchTrackingLegacy() : MachineFunctionPass(ID) {} StringRef getPassName() const override { return "X86 Indirect Branch Tracking"; } bool runOnMachineFunction(MachineFunction &MF) override; - -private: - static char ID; - - /// Machine instruction info used throughout the class. - const X86InstrInfo *TII = nullptr; - - /// Endbr opcode for the current machine function. - unsigned int EndbrOpcode = 0; - - /// Adds a new ENDBR instruction to the beginning of the MBB. - /// The function will not add it if already exists. - /// It will add ENDBR32 or ENDBR64 opcode, depending on the target. - /// \returns true if the ENDBR was added and false otherwise. - bool addENDBR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; }; -} // end anonymous namespace - -char X86IndirectBranchTrackingPass::ID = 0; - -FunctionPass *llvm::createX86IndirectBranchTrackingPass() { - return new X86IndirectBranchTrackingPass(); -} +/// Adds a new ENDBR instruction to the beginning of the MBB. +/// The function will not add it if already exists. +/// It will add ENDBR32 or ENDBR64 opcode, depending on the target. +/// \returns true if the ENDBR was added and false otherwise. +static bool addENDBR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) { + MachineFunction &MF = *MBB.getParent(); + const X86Subtarget &SubTarget = MF.getSubtarget(); + const X86InstrInfo *TII = SubTarget.getInstrInfo(); + unsigned EndbrOpcode = SubTarget.is64Bit() ? X86::ENDBR64 : X86::ENDBR32; -bool X86IndirectBranchTrackingPass::addENDBR( - MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { assert(TII && "Target instruction info was not initialized"); assert((X86::ENDBR64 == EndbrOpcode || X86::ENDBR32 == EndbrOpcode) && "Unexpected Endbr opcode"); @@ -86,6 +73,17 @@ bool X86IndirectBranchTrackingPass::addENDBR( return false; } +} // end anonymous namespace + +char X86IndirectBranchTrackingLegacy::ID = 0; + +INITIALIZE_PASS(X86IndirectBranchTrackingLegacy, DEBUG_TYPE, + "X86 Indirect Branch Tracking", false, false) + +FunctionPass *llvm::createX86IndirectBranchTrackingLegacyPass() { + return new X86IndirectBranchTrackingLegacy(); +} + static bool IsCallReturnTwice(llvm::MachineOperand &MOp) { if (!MOp.isGlobal()) return false; @@ -113,9 +111,7 @@ static bool needsPrologueENDBR(MachineFunction &MF, const Module *M) { } } -bool X86IndirectBranchTrackingPass::runOnMachineFunction(MachineFunction &MF) { - const X86Subtarget &SubTarget = MF.getSubtarget(); - +static bool runIndirectBranchTracking(MachineFunction &MF) { const Module *M = MF.getFunction().getParent(); // Check that the cf-protection-branch is enabled. Metadata *isCFProtectionSupported = M->getModuleFlag("cf-protection-branch"); @@ -135,9 +131,6 @@ bool X86IndirectBranchTrackingPass::runOnMachineFunction(MachineFunction &MF) { // True if the current MF was changed and false otherwise. bool Changed = false; - TII = SubTarget.getInstrInfo(); - EndbrOpcode = SubTarget.is64Bit() ? X86::ENDBR64 : X86::ENDBR32; - // If function is reachable indirectly, mark the first BB with ENDBR. if (needsPrologueENDBR(MF, M)) { auto MBB = MF.begin(); @@ -189,3 +182,17 @@ bool X86IndirectBranchTrackingPass::runOnMachineFunction(MachineFunction &MF) { } return Changed; } + +bool X86IndirectBranchTrackingLegacy::runOnMachineFunction( + MachineFunction &MF) { + return runIndirectBranchTracking(MF); +} + +PreservedAnalyses +X86IndirectBranchTrackingPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + return runIndirectBranchTracking(MF) + ? getMachineFunctionPassPreservedAnalyses() + .preserveSet() + : PreservedAnalyses::all(); +} diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 0392100f8c6c3..df0d614a0251f 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2724,7 +2724,7 @@ def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))), (KMOVWrk VK16:$src)>; def : Pat<(i64 (zext (i16 (bitconvert (v16i1 VK16:$src))))), - (SUBREG_TO_REG (i64 0), (KMOVWrk VK16:$src), sub_32bit)>; + (SUBREG_TO_REG (KMOVWrk VK16:$src), sub_32bit)>; def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), (COPY_TO_REGCLASS VK16:$src, GR32)>; def : Pat<(i64 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), @@ -2733,7 +2733,7 @@ def : Pat<(i64 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))), (KMOVBrk VK8:$src)>, Requires<[HasDQI]>; def : Pat<(i64 (zext (i8 (bitconvert (v8i1 VK8:$src))))), - (SUBREG_TO_REG (i64 0), (KMOVBrk VK8:$src), sub_32bit)>, Requires<[HasDQI]>; + (SUBREG_TO_REG (KMOVBrk VK8:$src), sub_32bit)>, Requires<[HasDQI]>; def : Pat<(i32 (anyext (i8 (bitconvert (v8i1 VK8:$src))))), (COPY_TO_REGCLASS VK8:$src, GR32)>; def : Pat<(i64 (anyext (i8 (bitconvert (v8i1 VK8:$src))))), @@ -4455,20 +4455,20 @@ let Predicates = [HasAVX512, OptForSize] in { // Move low f32 and clear high bits. def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), (v4f32 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), (v4i32 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VMOVSSZrr (v4f32 (AVX512_128_SET0)), (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VMOVSSZrr (v4i32 (AVX512_128_SET0)), (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)))), sub_xmm)>; } @@ -4477,12 +4477,12 @@ let Predicates = [HasAVX512, OptForSize] in { // VMOVSS/SD. Unfortunately, loses the ability to use XMM16-31. let Predicates = [HasAVX512, OptForSpeed] in { def : Pat<(v16f32 (X86vzmovl (v16f32 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VBLENDPSrri (v4f32 (V_SET0)), (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm)), (i8 1))), sub_xmm)>; def : Pat<(v16i32 (X86vzmovl (v16i32 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VPBLENDWrri (v4i32 (V_SET0)), (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm)), (i8 3))), sub_xmm)>; @@ -4497,16 +4497,16 @@ let Predicates = [HasAVX512] in { // Represent the same patterns above but in the form they appear for // 256-bit types def : Pat<(v8f32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSSZrm addr:$src), sub_xmm)>; def : Pat<(v4f64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSDZrm addr:$src), sub_xmm)>; // Represent the same patterns above but in the form they appear for // 512-bit types def : Pat<(v16f32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSSZrm addr:$src), sub_xmm)>; def : Pat<(v8f64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSDZrm addr:$src), sub_xmm)>; } let Predicates = [HasFP16] in { def : Pat<(v8f16 (X86vzmovl (v8f16 VR128X:$src))), @@ -4516,21 +4516,21 @@ let Predicates = [HasFP16] in { // FIXME we need better canonicalization in dag combine def : Pat<(v16f16 (X86vzmovl (v16f16 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v8f16 (VMOVSHZrr (v8f16 (AVX512_128_SET0)), (v8f16 (EXTRACT_SUBREG (v16f16 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v16i16 (X86vzmovl (v16i16 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v8i16 (VMOVSHZrr (v8i16 (AVX512_128_SET0)), (v8i16 (EXTRACT_SUBREG (v16i16 VR256X:$src), sub_xmm)))), sub_xmm)>; // FIXME we need better canonicalization in dag combine def : Pat<(v32f16 (X86vzmovl (v32f16 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v8f16 (VMOVSHZrr (v8f16 (AVX512_128_SET0)), (v8f16 (EXTRACT_SUBREG (v32f16 VR512:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v32i16 (X86vzmovl (v32i16 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v8i16 (VMOVSHZrr (v8i16 (AVX512_128_SET0)), (v8i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_xmm)))), sub_xmm)>; @@ -4538,10 +4538,10 @@ let Predicates = [HasFP16] in { (VMOVSHZrm addr:$src)>; def : Pat<(v16f16 (X86vzload16 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSHZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSHZrm addr:$src), sub_xmm)>; def : Pat<(v32f16 (X86vzload16 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSHZrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSHZrm addr:$src), sub_xmm)>; } let ExeDomain = SSEPackedInt, SchedRW = [SchedWriteVecLogic.XMM] in { @@ -4567,38 +4567,38 @@ let Predicates = [HasAVX512] in { def : Pat<(v4i32 (X86vzload32 addr:$src)), (VMOVDI2PDIZrm addr:$src)>; def : Pat<(v8i32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))), (VMOVZPQILo2PQIZrr VR128X:$src)>; def : Pat<(v2i64 (X86vzload64 addr:$src)), (VMOVQI2PQIZrm addr:$src)>; def : Pat<(v4i64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext. def : Pat<(v16i32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v4i32 (VMOVDI2PDIZrm addr:$src)), sub_xmm)>; def : Pat<(v8i64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v2i64 (VMOVQI2PQIZrm addr:$src)), sub_xmm)>; def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2f64 (VMOVZPQILo2PQIZrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2i64 (VMOVZPQILo2PQIZrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v8f64 (X86vzmovl (v8f64 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2f64 (VMOVZPQILo2PQIZrr (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v8i64 (X86vzmovl (v8i64 VR512:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2i64 (VMOVZPQILo2PQIZrr (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm)))), sub_xmm)>; @@ -13033,13 +13033,13 @@ def : Pat<(v8i32 (X86vzmovl (v4i32 (scalar_to_vector (and GR32:$src, 0xffff))), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVW2SHrr GR32:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVW2SHrr GR32:$src), sub_xmm)>; def : Pat<(v16i32 (X86vzmovl (insert_subvector undef, (v4i32 (scalar_to_vector (and GR32:$src, 0xffff))), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVW2SHrr GR32:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVW2SHrr GR32:$src), sub_xmm)>; def : Pat<(v8i16 (X86vzmovl (scalar_to_vector (i16 GR16:$src)))), (VMOVW2SHrr (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit))>; @@ -13048,11 +13048,11 @@ def : Pat<(v8i16 (X86vzmovl (scalar_to_vector (i16 GR16:$src)))), def : Pat<(v8i16 (X86vzload16 addr:$src)), (VMOVWrm addr:$src)>; def : Pat<(v16i16 (X86vzload16 addr:$src)), - (SUBREG_TO_REG (i32 0), (v8i16 (VMOVWrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v8i16 (VMOVWrm addr:$src)), sub_xmm)>; // Use regular 128-bit instructions to match 512-bit scalar_to_vec+zext. def : Pat<(v32i16 (X86vzload16 addr:$src)), - (SUBREG_TO_REG (i32 0), (v8i16 (VMOVWrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v8i16 (VMOVWrm addr:$src)), sub_xmm)>; def : Pat<(v4i32 (scalar_to_vector (i32 (extloadi16 addr:$src)))), (VMOVWrm addr:$src)>; @@ -13063,13 +13063,13 @@ def : Pat<(v8i32 (X86vzmovl (v4i32 (scalar_to_vector (i32 (zextloadi16 addr:$src)))), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVWrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVWrm addr:$src), sub_xmm)>; def : Pat<(v16i32 (X86vzmovl (insert_subvector undef, (v4i32 (scalar_to_vector (i32 (zextloadi16 addr:$src)))), (iPTR 0)))), - (SUBREG_TO_REG (i32 0), (VMOVWrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVWrm addr:$src), sub_xmm)>; // Move word from xmm register to r/m16 def VMOVSH2Wrr : AVX512<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src), diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td index 83294d7d6d3bd..6c8a7d7c83f0a 100644 --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -330,7 +330,7 @@ def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "", let AddedComplexity = 10 in { def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>; def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>; -def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>; +def : Pat<(i64 0), (SUBREG_TO_REG (MOV32r0), sub_32bit)>; } let Predicates = [OptForSize, Not64BitMode], @@ -1456,7 +1456,7 @@ def : Pat<(zextloadi16i1 addr:$src), (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>; def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; def : Pat<(zextloadi64i1 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm8 addr:$src), sub_32bit)>; // extload bool -> extload byte // When extloading from 16-bit and smaller memory locations into 64-bit @@ -1477,13 +1477,13 @@ def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; // NOTE: The extloadi64i32 pattern needs to be first as it will try to form // 32-bit loads for 4 byte aligned i8/i16 loads. def : Pat<(extloadi64i32 addr:$src), - (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOV32rm addr:$src), sub_32bit)>; def : Pat<(extloadi64i1 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm8 addr:$src), sub_32bit)>; def : Pat<(extloadi64i8 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm8 addr:$src), sub_32bit)>; def : Pat<(extloadi64i16 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm16 addr:$src), sub_32bit)>; // anyext. Define these to do an explicit zero-extend to // avoid partial-register updates. @@ -1496,9 +1496,9 @@ def : Pat<(i32 (anyext GR16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>; def : Pat<(i64 (anyext GR8 :$src)), - (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr8 GR8 :$src), sub_32bit)>; def : Pat<(i64 (anyext GR16:$src)), - (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr16 GR16 :$src), sub_32bit)>; def : Pat<(i64 (anyext GR32:$src)), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>; @@ -1507,9 +1507,9 @@ def : Pat<(i32 (anyext_sdiv GR8:$src)), (MOVSX32rr8 GR8:$src)>; // In the case of a 32-bit def that is known to implicitly zero-extend, // we can use a SUBREG_TO_REG. def : Pat<(i64 (zext def32:$src)), - (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; + (SUBREG_TO_REG GR32:$src, sub_32bit)>; def : Pat<(i64 (and (anyext def32:$src), 0x00000000FFFFFFFF)), - (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>; + (SUBREG_TO_REG GR32:$src, sub_32bit)>; //===----------------------------------------------------------------------===// // Pattern match OR as ADD @@ -1676,7 +1676,6 @@ let AddedComplexity = 1 in { let Predicates = [NoNDD] in { def : Pat<(and GR64:$src, i64immZExt32:$imm), (SUBREG_TO_REG - (i64 0), (AND32ri (EXTRACT_SUBREG GR64:$src, sub_32bit), (i32 (GetLo32XForm imm:$imm))), @@ -1685,7 +1684,6 @@ let AddedComplexity = 1 in { let Predicates = [HasNDD] in { def : Pat<(and GR64:$src, i64immZExt32:$imm), (SUBREG_TO_REG - (i64 0), (AND32ri_ND (EXTRACT_SUBREG GR64:$src, sub_32bit), (i32 (GetLo32XForm imm:$imm))), @@ -1711,18 +1709,15 @@ def : Pat<(and GR16:$src1, 0xff), // r & (2^32-1) ==> movz def : Pat<(and GR64:$src, 0x00000000FFFFFFFF), - (SUBREG_TO_REG (i64 0), - (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), + (SUBREG_TO_REG (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)), sub_32bit)>; // r & (2^16-1) ==> movz def : Pat<(and GR64:$src, 0xffff), - (SUBREG_TO_REG (i64 0), - (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), - sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))), + sub_32bit)>; // r & (2^8-1) ==> movz def : Pat<(and GR64:$src, 0xff), - (SUBREG_TO_REG (i64 0), - (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), + (SUBREG_TO_REG (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))), sub_32bit)>; } // AddedComplexity = 1 @@ -1846,19 +1841,16 @@ def : Pat<(srl (and_su GR32:$src, immff00_ffff), (i8 8)), // h-register extract and zero-extend. def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)), (SUBREG_TO_REG - (i64 0), (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)), sub_32bit)>; def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))), (SUBREG_TO_REG - (i64 0), (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), sub_32bit)>; def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))), (SUBREG_TO_REG - (i64 0), (MOVZX32rr8_NOREX (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)), sub_32bit)>; @@ -2253,13 +2245,13 @@ defm : EFLAGSDefiningPats<"_ND", HasNDD>; let Predicates = [HasZU] in { // zext (mul reg/mem, imm) -> imulzu def : Pat<(i32 (zext (i16 (mul GR16:$src1, imm:$src2)))), - (SUBREG_TO_REG (i32 0), (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>; + (SUBREG_TO_REG (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>; def : Pat<(i32 (zext (i16 (mul (loadi16 addr:$src1), imm:$src2)))), - (SUBREG_TO_REG (i32 0), (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>; + (SUBREG_TO_REG (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>; def : Pat<(i64 (zext (i16 (mul GR16:$src1, imm:$src2)))), - (SUBREG_TO_REG (i64 0), (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>; + (SUBREG_TO_REG (IMULZU16rri GR16:$src1, imm:$src2), sub_16bit)>; def : Pat<(i64 (zext (i16 (mul (loadi16 addr:$src1), imm:$src2)))), - (SUBREG_TO_REG (i64 0), (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>; + (SUBREG_TO_REG (IMULZU16rmi addr:$src1, imm:$src2), sub_16bit)>; } // mul reg, imm diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td index c67feb7668234..1b2dbefce6f1c 100644 --- a/llvm/lib/Target/X86/X86InstrControl.td +++ b/llvm/lib/Target/X86/X86InstrControl.td @@ -88,6 +88,10 @@ let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump], } } +let hasSideEffects = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in +def JCC_SELF : PseudoI<(outs), (ins ccode:$cond), + [(X86brcond_self timm:$cond, EFLAGS)]>; + // jcx/jecx/jrcx instructions. let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { // These are the 32-bit versions of this instruction for the asmparser. In diff --git a/llvm/lib/Target/X86/X86InstrExtension.td b/llvm/lib/Target/X86/X86InstrExtension.td index 46554dfc5167a..7bf0cb1d64755 100644 --- a/llvm/lib/Target/X86/X86InstrExtension.td +++ b/llvm/lib/Target/X86/X86InstrExtension.td @@ -202,14 +202,14 @@ def MOVZX64rm16 : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a // 32-bit register. def : Pat<(i64 (zext GR8:$src)), - (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr8 GR8:$src), sub_32bit)>; def : Pat<(zextloadi64i8 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm8 addr:$src), sub_32bit)>; def : Pat<(i64 (zext GR16:$src)), - (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rr16 GR16:$src), sub_32bit)>; def : Pat<(zextloadi64i16 addr:$src), - (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOVZX32rm16 addr:$src), sub_32bit)>; // The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible @@ -217,6 +217,6 @@ def : Pat<(zextloadi64i16 addr:$src), // where the high bits aren't necessarily all zero. In such cases, we fall back // to these explicit zext instructions. def : Pat<(i64 (zext GR32:$src)), - (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>; + (SUBREG_TO_REG (MOV32rr GR32:$src), sub_32bit)>; def : Pat<(i64 (zextloadi64i32 addr:$src)), - (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>; + (SUBREG_TO_REG (MOV32rm addr:$src), sub_32bit)>; diff --git a/llvm/lib/Target/X86/X86InstrFragments.td b/llvm/lib/Target/X86/X86InstrFragments.td index 38ab02667317e..0d6443d002d02 100644 --- a/llvm/lib/Target/X86/X86InstrFragments.td +++ b/llvm/lib/Target/X86/X86InstrFragments.td @@ -50,6 +50,9 @@ def SDTX86BrCond : SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; +def SDTX86BrCondSelf : SDTypeProfile<0, 2, + [SDTCisVT<0, i8>, SDTCisVT<1, i32>]>; + def SDTX86SetCC : SDTypeProfile<1, 2, [SDTCisVT<0, i8>, SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; @@ -154,6 +157,8 @@ def X86cstore : SDNode<"X86ISD::CSTORE", SDTX86Cstore, [SDNPHasChain, SDNPMay def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, [SDNPHasChain]>; +def X86brcond_self : SDNode<"X86ISD::BRCOND_SELF", SDTX86BrCondSelf, + [SDNPHasChain]>; def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index c99865cc2dfcd..d85d9b600c2d6 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -1070,17 +1070,12 @@ findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr, } if (CmpInstr.getOpcode() == X86::TEST64rr) { - // As seen in X86 td files, CmpValDefInstr.getOperand(1).getImm() is - // typically 0. - if (CmpValDefInstr.getOperand(1).getImm() != 0) - return false; - // As seen in X86 td files, CmpValDefInstr.getOperand(3) is typically // sub_32bit or sub_xmm. - if (CmpValDefInstr.getOperand(3).getImm() != X86::sub_32bit) + if (CmpValDefInstr.getOperand(2).getImm() != X86::sub_32bit) return false; - VregDefInstr = MRI->getVRegDef(CmpValDefInstr.getOperand(2).getReg()); + VregDefInstr = MRI->getVRegDef(CmpValDefInstr.getOperand(1).getReg()); } assert(VregDefInstr && "Must have a definition (SSA)"); @@ -1098,7 +1093,7 @@ findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr, // Get a sequence of instructions like // %reg = and* ... // Set EFLAGS // ... // EFLAGS not changed - // %extended_reg = subreg_to_reg 0, %reg, %subreg.sub_32bit + // %extended_reg = subreg_to_reg %reg, %subreg.sub_32bit // test64rr %extended_reg, %extended_reg, implicit-def $eflags // or // %reg = and32* ... @@ -4618,13 +4613,10 @@ bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI, if (MI.isSubregToReg()) { // We use following pattern to setup 64b immediate. // %8:gr32 = MOV32r0 implicit-def dead $eflags - // %6:gr64 = SUBREG_TO_REG 0, killed %8:gr32, %subreg.sub_32bit - if (!MI.getOperand(1).isImm()) - return false; - unsigned FillBits = MI.getOperand(1).getImm(); - unsigned SubIdx = MI.getOperand(3).getImm(); - MovReg = MI.getOperand(2).getReg(); - if (SubIdx != X86::sub_32bit || FillBits != 0) + // %6:gr64 = SUBREG_TO_REG killed %8:gr32, %subreg.sub_32bit + unsigned SubIdx = MI.getOperand(2).getImm(); + MovReg = MI.getOperand(1).getReg(); + if (SubIdx != X86::sub_32bit) return false; const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); MovMI = MRI.getUniqueVRegDef(MovReg); @@ -5391,7 +5383,7 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, // Example for test64rr: // %reg = and32ri %in_reg, 5 // ... // EFLAGS not changed. - // %src_reg = subreg_to_reg 0, %reg, %subreg.sub_index + // %src_reg = subreg_to_reg %reg, %subreg.sub_index // test64rr %src_reg, %src_reg, implicit-def $eflags MachineInstr *AndInstr = nullptr; if (IsCmpZero && @@ -10515,119 +10507,6 @@ struct CGBR : public MachineFunctionPass { char CGBR::ID = 0; FunctionPass *llvm::createX86GlobalBaseRegPass() { return new CGBR(); } -namespace { -struct LDTLSCleanup : public MachineFunctionPass { - static char ID; - LDTLSCleanup() : MachineFunctionPass(ID) {} - - bool runOnMachineFunction(MachineFunction &MF) override { - if (skipFunction(MF.getFunction())) - return false; - - X86MachineFunctionInfo *MFI = MF.getInfo(); - if (MFI->getNumLocalDynamicTLSAccesses() < 2) { - // No point folding accesses if there isn't at least two. - return false; - } - - MachineDominatorTree *DT = - &getAnalysis().getDomTree(); - return VisitNode(DT->getRootNode(), Register()); - } - - // Visit the dominator subtree rooted at Node in pre-order. - // If TLSBaseAddrReg is non-null, then use that to replace any - // TLS_base_addr instructions. Otherwise, create the register - // when the first such instruction is seen, and then use it - // as we encounter more instructions. - bool VisitNode(MachineDomTreeNode *Node, Register TLSBaseAddrReg) { - MachineBasicBlock *BB = Node->getBlock(); - bool Changed = false; - - // Traverse the current block. - for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; - ++I) { - switch (I->getOpcode()) { - case X86::TLS_base_addr32: - case X86::TLS_base_addr64: - if (TLSBaseAddrReg) - I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg); - else - I = SetRegister(*I, &TLSBaseAddrReg); - Changed = true; - break; - default: - break; - } - } - - // Visit the children of this block in the dominator tree. - for (MachineDomTreeNode *I : Node->children()) - Changed |= VisitNode(I, TLSBaseAddrReg); - - return Changed; - } - - // Replace the TLS_base_addr instruction I with a copy from - // TLSBaseAddrReg, returning the new instruction. - MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I, - Register TLSBaseAddrReg) { - MachineFunction *MF = I.getParent()->getParent(); - const X86Subtarget &STI = MF->getSubtarget(); - const bool is64Bit = STI.is64Bit(); - const X86InstrInfo *TII = STI.getInstrInfo(); - - // Insert a Copy from TLSBaseAddrReg to RAX/EAX. - MachineInstr *Copy = - BuildMI(*I.getParent(), I, I.getDebugLoc(), - TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX) - .addReg(TLSBaseAddrReg); - - // Erase the TLS_base_addr instruction. - I.eraseFromParent(); - - return Copy; - } - - // Create a virtual register in *TLSBaseAddrReg, and populate it by - // inserting a copy instruction after I. Returns the new instruction. - MachineInstr *SetRegister(MachineInstr &I, Register *TLSBaseAddrReg) { - MachineFunction *MF = I.getParent()->getParent(); - const X86Subtarget &STI = MF->getSubtarget(); - const bool is64Bit = STI.is64Bit(); - const X86InstrInfo *TII = STI.getInstrInfo(); - - // Create a virtual register for the TLS base address. - MachineRegisterInfo &RegInfo = MF->getRegInfo(); - *TLSBaseAddrReg = RegInfo.createVirtualRegister( - is64Bit ? &X86::GR64RegClass : &X86::GR32RegClass); - - // Insert a copy from RAX/EAX to TLSBaseAddrReg. - MachineInstr *Next = I.getNextNode(); - MachineInstr *Copy = BuildMI(*I.getParent(), Next, I.getDebugLoc(), - TII->get(TargetOpcode::COPY), *TLSBaseAddrReg) - .addReg(is64Bit ? X86::RAX : X86::EAX); - - return Copy; - } - - StringRef getPassName() const override { - return "Local Dynamic TLS Access Clean-up"; - } - - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); - AU.addRequired(); - MachineFunctionPass::getAnalysisUsage(AU); - } -}; -} // namespace - -char LDTLSCleanup::ID = 0; -FunctionPass *llvm::createCleanupLocalDynamicTLSPass() { - return new LDTLSCleanup(); -} - /// Constants defining how certain sequences should be outlined. /// /// \p MachineOutlinerDefault implies that the function is called with a call diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index 290d91bb2ce69..d94108754d555 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1340,23 +1340,19 @@ def AndMask64 : ImmLeaf; + (SUBREG_TO_REG (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), (BEXTR64rm addr:$src, - (SUBREG_TO_REG (i64 0), - (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + (SUBREG_TO_REG (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; } let Predicates = [HasBMI, NoBMI2, NoTBM, HasEGPR] in { def : Pat<(and GR64:$src, AndMask64:$mask), (BEXTR64rr_EVEX GR64:$src, - (SUBREG_TO_REG (i64 0), - (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + (SUBREG_TO_REG (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), (BEXTR64rm_EVEX addr:$src, - (SUBREG_TO_REG (i64 0), - (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; + (SUBREG_TO_REG (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; } // Use BZHI for 64-bit 'and' with large immediate 'mask'. diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index e915e47046d9c..f67bc0e74acc8 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -301,9 +301,9 @@ let Predicates = [UseAVX] in { // Represent the same patterns above but in the form they appear for // 256-bit types def : Pat<(v8f32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSSrm addr:$src), sub_xmm)>; def : Pat<(v4f64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>; + (SUBREG_TO_REG (VMOVSDrm addr:$src), sub_xmm)>; } let Predicates = [UseAVX, OptForSize] in { @@ -316,11 +316,11 @@ let Predicates = [UseAVX, OptForSize] in { // Move low f32 and clear high bits. def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VMOVSSrr (v4f32 (V_SET0)), (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VMOVSSrr (v4i32 (V_SET0)), (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)))), sub_xmm)>; } @@ -4293,7 +4293,7 @@ let Predicates = [UseAVX] in { def : Pat<(v4i32 (X86vzload32 addr:$src)), (VMOVDI2PDIrm addr:$src)>; def : Pat<(v8i32 (X86vzload32 addr:$src)), - (SUBREG_TO_REG (i64 0), (v4i32 (VMOVDI2PDIrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v4i32 (VMOVDI2PDIrm addr:$src)), sub_xmm)>; } let Predicates = [UseSSE2] in { @@ -4373,7 +4373,7 @@ let Predicates = [UseAVX] in { def : Pat<(v2i64 (X86vzload64 addr:$src)), (VMOVQI2PQIrm addr:$src)>; def : Pat<(v4i64 (X86vzload64 addr:$src)), - (SUBREG_TO_REG (i64 0), (v2i64 (VMOVQI2PQIrm addr:$src)), sub_xmm)>; + (SUBREG_TO_REG (v2i64 (VMOVQI2PQIrm addr:$src)), sub_xmm)>; def : Pat<(X86vextractstore64 (v2i64 VR128:$src), addr:$dst), (VMOVPQI2QImr addr:$dst, VR128:$src)>; @@ -4412,12 +4412,12 @@ let Predicates = [UseSSE2] in { let Predicates = [UseAVX] in { def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2f64 (VMOVZPQILo2PQIrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)))), sub_xmm)>; def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v2i64 (VMOVZPQILo2PQIrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)))), sub_xmm)>; @@ -6442,12 +6442,12 @@ let Predicates = [HasAVX, OptForSpeed] in { // Move low f32 and clear high bits. def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4f32 (VBLENDPSrri (v4f32 (V_SET0)), (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), (i8 1))), sub_xmm)>; def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))), - (SUBREG_TO_REG (i32 0), + (SUBREG_TO_REG (v4i32 (VPBLENDWrri (v4i32 (V_SET0)), (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), (i8 3))), sub_xmm)>; diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td index eb0b5a43afdf9..fdf576baba02d 100644 --- a/llvm/lib/Target/X86/X86InstrSystem.td +++ b/llvm/lib/Target/X86/X86InstrSystem.td @@ -749,14 +749,14 @@ let Predicates = [HasINVPCID, NoEGPR] in { // type),/ so it doesn't hurt us that one can't supply a 64 bit value here. def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), (INVPCID64 - (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), + (SUBREG_TO_REG (MOV32rr GR32:$src1), sub_32bit), addr:$src2)>; } let Predicates = [HasINVPCID, HasEGPR] in { def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2), (INVPCID64_EVEX - (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit), + (SUBREG_TO_REG (MOV32rr GR32:$src1), sub_32bit), addr:$src2)>; } diff --git a/llvm/lib/Target/X86/X86InstrVecCompiler.td b/llvm/lib/Target/X86/X86InstrVecCompiler.td index 122627ca45d31..9cd479b518543 100644 --- a/llvm/lib/Target/X86/X86InstrVecCompiler.td +++ b/llvm/lib/Target/X86/X86InstrVecCompiler.td @@ -120,7 +120,7 @@ multiclass subvec_zero_lowering { def : Pat<(DstTy (insert_subvector immAllZerosV, (SrcTy RC:$src), (iPTR 0))), - (SUBREG_TO_REG (i64 0), + (SUBREG_TO_REG (SrcTy (!cast("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>; } diff --git a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp index 9f797f4d6d5f3..871081e328724 100644 --- a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp @@ -133,17 +133,27 @@ struct MachineGadgetGraph : ImmutableGraph { int NumGadgets; }; -class X86LoadValueInjectionLoadHardeningPass : public MachineFunctionPass { +constexpr StringRef X86LVILHPassName = + "X86 Load Value Injection (LVI) Load Hardening"; + +class X86LoadValueInjectionLoadHardeningLegacy : public MachineFunctionPass { public: - X86LoadValueInjectionLoadHardeningPass() : MachineFunctionPass(ID) {} + X86LoadValueInjectionLoadHardeningLegacy() : MachineFunctionPass(ID) {} - StringRef getPassName() const override { - return "X86 Load Value Injection (LVI) Load Hardening"; - } + StringRef getPassName() const override { return X86LVILHPassName; } void getAnalysisUsage(AnalysisUsage &AU) const override; bool runOnMachineFunction(MachineFunction &MF) override; static char ID; +}; + +class X86LoadValueInjectionLoadHardeningImpl { +public: + X86LoadValueInjectionLoadHardeningImpl() = default; + + bool run(MachineFunction &MF, const MachineLoopInfo &MLI, + const MachineDominatorTree &MDT, + const MachineDominanceFrontier &MDF); private: using GraphBuilder = ImmutableGraphBuilder; @@ -227,9 +237,9 @@ struct DOTGraphTraits : DefaultDOTGraphTraits { } // end namespace llvm -char X86LoadValueInjectionLoadHardeningPass::ID = 0; +char X86LoadValueInjectionLoadHardeningLegacy::ID = 0; -void X86LoadValueInjectionLoadHardeningPass::getAnalysisUsage( +void X86LoadValueInjectionLoadHardeningLegacy::getAnalysisUsage( AnalysisUsage &AU) const { MachineFunctionPass::getAnalysisUsage(AU); AU.addRequired(); @@ -244,30 +254,21 @@ static void writeGadgetGraph(raw_ostream &OS, MachineFunction &MF, "Speculative gadgets for \"" + MF.getName() + "\" function"); } -bool X86LoadValueInjectionLoadHardeningPass::runOnMachineFunction( - MachineFunction &MF) { - LLVM_DEBUG(dbgs() << "***** " << getPassName() << " : " << MF.getName() +bool X86LoadValueInjectionLoadHardeningImpl::run( + MachineFunction &MF, const MachineLoopInfo &MLI, + const MachineDominatorTree &MDT, const MachineDominanceFrontier &MDF) { + LLVM_DEBUG(dbgs() << "***** " << X86LVILHPassName << " : " << MF.getName() << " *****\n"); STI = &MF.getSubtarget(); - if (!STI->useLVILoadHardening()) - return false; // FIXME: support 32-bit if (!STI->is64Bit()) report_fatal_error("LVI load hardening is only supported on 64-bit", false); - // Don't skip functions with the "optnone" attr but participate in opt-bisect. - const Function &F = MF.getFunction(); - if (!F.hasOptNone() && skipFunction(F)) - return false; - ++NumFunctionsConsidered; TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); LLVM_DEBUG(dbgs() << "Building gadget graph...\n"); - const auto &MLI = getAnalysis().getLI(); - const auto &MDT = getAnalysis().getDomTree(); - const auto &MDF = getAnalysis().getMDF(); std::unique_ptr Graph = getGadgetGraph(MF, MLI, MDT, MDF); LLVM_DEBUG(dbgs() << "Building gadget graph... Done\n"); if (Graph == nullptr) @@ -319,7 +320,7 @@ bool X86LoadValueInjectionLoadHardeningPass::runOnMachineFunction( } std::unique_ptr -X86LoadValueInjectionLoadHardeningPass::getGadgetGraph( +X86LoadValueInjectionLoadHardeningImpl::getGadgetGraph( MachineFunction &MF, const MachineLoopInfo &MLI, const MachineDominatorTree &MDT, const MachineDominanceFrontier &MDF) const { @@ -532,7 +533,7 @@ X86LoadValueInjectionLoadHardeningPass::getGadgetGraph( } // Returns the number of remaining gadget edges that could not be eliminated -int X86LoadValueInjectionLoadHardeningPass::elimMitigatedEdgesAndNodes( +int X86LoadValueInjectionLoadHardeningImpl::elimMitigatedEdgesAndNodes( MachineGadgetGraph &G, EdgeSet &ElimEdges /* in, out */, NodeSet &ElimNodes /* in, out */) const { if (G.NumFences > 0) { @@ -587,7 +588,7 @@ int X86LoadValueInjectionLoadHardeningPass::elimMitigatedEdgesAndNodes( } std::unique_ptr -X86LoadValueInjectionLoadHardeningPass::trimMitigatedEdges( +X86LoadValueInjectionLoadHardeningImpl::trimMitigatedEdges( std::unique_ptr Graph) const { NodeSet ElimNodes{*Graph}; EdgeSet ElimEdges{*Graph}; @@ -603,7 +604,7 @@ X86LoadValueInjectionLoadHardeningPass::trimMitigatedEdges( return Graph; } -int X86LoadValueInjectionLoadHardeningPass::hardenLoadsWithPlugin( +int X86LoadValueInjectionLoadHardeningImpl::hardenLoadsWithPlugin( MachineFunction &MF, std::unique_ptr Graph) const { int FencesInserted = 0; @@ -648,7 +649,7 @@ int X86LoadValueInjectionLoadHardeningPass::hardenLoadsWithPlugin( return FencesInserted; } -int X86LoadValueInjectionLoadHardeningPass::hardenLoadsWithHeuristic( +int X86LoadValueInjectionLoadHardeningImpl::hardenLoadsWithHeuristic( MachineFunction &MF, std::unique_ptr Graph) const { // If `MF` does not have any fences, then no gadgets would have been // mitigated at this point. @@ -714,7 +715,7 @@ int X86LoadValueInjectionLoadHardeningPass::hardenLoadsWithHeuristic( return FencesInserted; } -int X86LoadValueInjectionLoadHardeningPass::insertFences( +int X86LoadValueInjectionLoadHardeningImpl::insertFences( MachineFunction &MF, MachineGadgetGraph &G, EdgeSet &CutEdges /* in, out */) const { int FencesInserted = 0; @@ -758,7 +759,7 @@ int X86LoadValueInjectionLoadHardeningPass::insertFences( return FencesInserted; } -bool X86LoadValueInjectionLoadHardeningPass::instrUsesRegToAccessMemory( +bool X86LoadValueInjectionLoadHardeningImpl::instrUsesRegToAccessMemory( const MachineInstr &MI, Register Reg) const { if (!MI.mayLoadOrStore() || MI.getOpcode() == X86::MFENCE || MI.getOpcode() == X86::SFENCE || MI.getOpcode() == X86::LFENCE) @@ -782,7 +783,7 @@ bool X86LoadValueInjectionLoadHardeningPass::instrUsesRegToAccessMemory( TRI->regsOverlap(IndexMO.getReg(), Reg)); } -bool X86LoadValueInjectionLoadHardeningPass::instrUsesRegToBranch( +bool X86LoadValueInjectionLoadHardeningImpl::instrUsesRegToBranch( const MachineInstr &MI, Register Reg) const { if (!MI.isConditionalBranch()) return false; @@ -792,14 +793,53 @@ bool X86LoadValueInjectionLoadHardeningPass::instrUsesRegToBranch( return false; } -INITIALIZE_PASS_BEGIN(X86LoadValueInjectionLoadHardeningPass, PASS_KEY, +bool X86LoadValueInjectionLoadHardeningLegacy::runOnMachineFunction( + MachineFunction &MF) { + // Don't skip functions with the "optnone" attr but participate in opt-bisect. + // Note: Not needed for new PM impl, where it is handled at the PM level. + const Function &F = MF.getFunction(); + if (!F.hasOptNone() && skipFunction(F)) + return false; + + // Bail early (without computing analyses) if LVI load hardening is disabled. + if (!MF.getSubtarget().useLVILoadHardening()) { + return false; + } + + const auto &MLI = getAnalysis().getLI(); + const auto &MDT = getAnalysis().getDomTree(); + const auto &MDF = getAnalysis().getMDF(); + + X86LoadValueInjectionLoadHardeningImpl Impl; + return Impl.run(MF, MLI, MDT, MDF); +} + +PreservedAnalyses X86LoadValueInjectionLoadHardeningPass::run( + MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { + // Bail early (without computing analyses) if LVI load hardening is disabled. + if (!MF.getSubtarget().useLVILoadHardening()) { + return PreservedAnalyses::all(); + } + + const auto &MLI = MFAM.getResult(MF); + const auto &MDT = MFAM.getResult(MF); + const auto &MDF = MFAM.getResult(MF); + + X86LoadValueInjectionLoadHardeningImpl Impl; + const bool Modified = Impl.run(MF, MLI, MDT, MDF); + return Modified ? getMachineFunctionPassPreservedAnalyses() + .preserveSet() + : PreservedAnalyses::all(); +} + +INITIALIZE_PASS_BEGIN(X86LoadValueInjectionLoadHardeningLegacy, PASS_KEY, "X86 LVI load hardening", false, false) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontierWrapperPass) -INITIALIZE_PASS_END(X86LoadValueInjectionLoadHardeningPass, PASS_KEY, +INITIALIZE_PASS_END(X86LoadValueInjectionLoadHardeningLegacy, PASS_KEY, "X86 LVI load hardening", false, false) -FunctionPass *llvm::createX86LoadValueInjectionLoadHardeningPass() { - return new X86LoadValueInjectionLoadHardeningPass(); +FunctionPass *llvm::createX86LoadValueInjectionLoadHardeningLegacyPass() { + return new X86LoadValueInjectionLoadHardeningLegacy(); } diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index 243763e0080ac..4ef4718e1b01c 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -2616,6 +2616,15 @@ void X86AsmPrinter::emitInstruction(const MachineInstr *MI) { EmitAndCountInstruction(MCInstBuilder(X86::DS_PREFIX)); } break; + + case X86::JCC_SELF: + MCSymbol *Sym = OutContext.createTempSymbol(); + OutStreamer->emitLabel(Sym); + EmitAndCountInstruction( + MCInstBuilder(X86::JCC_1) + .addExpr(MCSymbolRefExpr::create(Sym, OutContext)) + .addImm(MI->getOperand(0).getImm())); + return; } MCInst TmpInst; diff --git a/llvm/lib/Target/X86/X86PassRegistry.def b/llvm/lib/Target/X86/X86PassRegistry.def index bb2db80248b74..91156260d2c7c 100644 --- a/llvm/lib/Target/X86/X86PassRegistry.def +++ b/llvm/lib/Target/X86/X86PassRegistry.def @@ -33,6 +33,7 @@ MACHINE_FUNCTION_PASS("x86-argument-stack-slot", X86ArgumentStackSlotPass()) MACHINE_FUNCTION_PASS("x86-avoid-sfb", X86AvoidStoreForwardingBlocksPass()) MACHINE_FUNCTION_PASS("x86-avoid-trailing-call", X86AvoidTrailingCallPass()) MACHINE_FUNCTION_PASS("x86-cf-opt", X86CallFrameOptimizationPass()) +MACHINE_FUNCTION_PASS("x86-cleanup-local-dynamic-tls", X86CleanupLocalDynamicTLSPass()) MACHINE_FUNCTION_PASS("x86-cmov-conversion", X86CmovConversionPass()) MACHINE_FUNCTION_PASS("x86-compress-evex", X86CompressEVEXPass()) MACHINE_FUNCTION_PASS("x86-domain-reassignment", X86DomainReassignmentPass()) @@ -47,8 +48,10 @@ MACHINE_FUNCTION_PASS("x86-fixup-setcc", X86FixupSetCCPass()) MACHINE_FUNCTION_PASS("x86-fixup-vector-constants", X86FixupVectorConstantsPass()) MACHINE_FUNCTION_PASS("x86-flags-copy-lowering", X86FlagsCopyLoweringPass()) MACHINE_FUNCTION_PASS("x86-fp-stackifier", X86FPStackifierPass()) +MACHINE_FUNCTION_PASS("x86-indirect-branch-tracking", X86IndirectBranchTrackingPass()) MACHINE_FUNCTION_PASS("x86-isel", X86ISelDAGToDAGPass(*this)) MACHINE_FUNCTION_PASS("x86-lower-tile-copy", X86LowerTileCopyPass()) +MACHINE_FUNCTION_PASS("x86-lvi-load", X86LoadValueInjectionLoadHardeningPass()) MACHINE_FUNCTION_PASS("x86-lvi-ret", X86LoadValueInjectionRetHardeningPass()) MACHINE_FUNCTION_PASS("x86-optimize-leas", X86OptimizeLEAsPass()) MACHINE_FUNCTION_PASS("x86-pre-tile-config", X86PreTileConfigPass()) @@ -57,19 +60,16 @@ MACHINE_FUNCTION_PASS("x86-seses", X86SpeculativeExecutionSideEffectSuppressionP MACHINE_FUNCTION_PASS("x86-slh", X86SpeculativeLoadHardeningPass()) MACHINE_FUNCTION_PASS("x86-suppress-apx-for-relocation", X86SuppressAPXForRelocationPass()) MACHINE_FUNCTION_PASS("x86-tile-config", X86TileConfigPass()) +MACHINE_FUNCTION_PASS("x86-wineh-unwindv2", X86WinEHUnwindV2Pass()) #undef MACHINE_FUNCTION_PASS #ifndef DUMMY_MACHINE_FUNCTION_PASS #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) #endif -DUMMY_MACHINE_FUNCTION_PASS("x86-cleanup-local-dynamic-tls", X86CleanupLocalDynamicTLSPass()) DUMMY_MACHINE_FUNCTION_PASS("x86-execution-domain-fix", X86ExecutionDomainFix()) DUMMY_MACHINE_FUNCTION_PASS("x86-global-base-reg", X86GlobalBaseRegPass()) -DUMMY_MACHINE_FUNCTION_PASS("x86-indirect-branch-tracking", X86IndirectBranchTrackingPass()) DUMMY_MACHINE_FUNCTION_PASS("x86-indirect-thunks", X86IndirectThunks()) DUMMY_MACHINE_FUNCTION_PASS("x86-insert-x87-wait", X86InsertX87WaitPass()) DUMMY_MACHINE_FUNCTION_PASS("x86-issue-vzero-upper", X86IssueVZeroUpperPass()) -DUMMY_MACHINE_FUNCTION_PASS("x86-lvi-load", X86LoadValueInjectionLoadHardeningPass()) DUMMY_MACHINE_FUNCTION_PASS("x86-pad-short-functions", X86PadShortFunctionsPass()) -DUMMY_MACHINE_FUNCTION_PASS("x86-wineh-unwindv2", X86WinEHUnwindV2()) #undef DUMMY_MACHINE_FUNCTION_PASS diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td index b299633446410..9d2a1ce01c273 100644 --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -387,3 +387,4 @@ def ZnVer4PfmCounters : ProcPfmCounters { } def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>; def : PfmCountersBinding<"znver5", ZnVer4PfmCounters>; +def : PfmCountersBinding<"znver6", ZnVer4PfmCounters>; diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index e0b17ce1be79d..817cc86a63cdf 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -501,7 +501,6 @@ bool X86SpeculativeLoadHardeningImpl::run(MachineFunction &MF) { ZeroEFLAGSDefOp->setIsDead(true); BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::SUBREG_TO_REG), PS->InitialReg) - .addImm(0) .addReg(PredStateSubReg) .addImm(X86::sub_32bit); } diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 1affb7c9dd16c..95ad484d04ccd 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -94,7 +94,7 @@ extern "C" LLVM_C_ABI void LLVMInitializeX86Target() { initializeX86SpeculativeLoadHardeningLegacyPass(PR); initializeX86SpeculativeExecutionSideEffectSuppressionLegacyPass(PR); initializeX86FlagsCopyLoweringLegacyPass(PR); - initializeX86LoadValueInjectionLoadHardeningPassPass(PR); + initializeX86LoadValueInjectionLoadHardeningLegacyPass(PR); initializeX86LoadValueInjectionRetHardeningLegacyPass(PR); initializeX86OptimizeLEAsLegacyPass(PR); initializeX86PartialReductionLegacyPass(PR); @@ -106,7 +106,7 @@ extern "C" LLVM_C_ABI void LLVMInitializeX86Target() { initializeX86FixupVectorConstantsLegacyPass(PR); initializeX86DynAllocaExpanderLegacyPass(PR); initializeX86SuppressAPXForRelocationLegacyPass(PR); - initializeX86WinEHUnwindV2Pass(PR); + initializeX86WinEHUnwindV2LegacyPass(PR); initializeX86PreLegalizerCombinerPass(PR); } @@ -372,6 +372,7 @@ class X86PassConfig : public TargetPassConfig { bool addInstSelector() override; bool addIRTranslator() override; bool addLegalizeMachineIR() override; + void addPreRegBankSelect() override; bool addRegBankSelect() override; bool addGlobalInstructionSelect() override; void addPreLegalizeMachineIR() override; @@ -459,7 +460,7 @@ bool X86PassConfig::addInstSelector() { // For ELF, cleanup any local-dynamic TLS accesses. if (TM->getTargetTriple().isOSBinFormatELF() && getOptLevel() != CodeGenOptLevel::None) - addPass(createCleanupLocalDynamicTLSPass()); + addPass(createCleanupLocalDynamicTLSLegacyPass()); addPass(createX86GlobalBaseRegPass()); addPass(createX86ArgumentStackSlotLegacyPass()); @@ -471,6 +472,12 @@ bool X86PassConfig::addIRTranslator() { return false; } +void X86PassConfig::addPreRegBankSelect() { + bool IsOptNone = getOptLevel() == CodeGenOptLevel::None; + if (!IsOptNone) { + addPass(createX86PostLegalizerCombiner()); + } +} bool X86PassConfig::addLegalizeMachineIR() { addPass(new Legalizer()); return false; @@ -545,7 +552,7 @@ void X86PassConfig::addPostRegAlloc() { // mitigation. This is to prevent slow downs due to // analyses needed by the LVIHardening pass when compiling at -O0. if (getOptLevel() != CodeGenOptLevel::None) - addPass(createX86LoadValueInjectionLoadHardeningPass()); + addPass(createX86LoadValueInjectionLoadHardeningLegacyPass()); } void X86PassConfig::addPreSched2() { @@ -559,7 +566,7 @@ void X86PassConfig::addPreEmitPass() { addPass(createBreakFalseDeps()); } - addPass(createX86IndirectBranchTrackingPass()); + addPass(createX86IndirectBranchTrackingLegacyPass()); addPass(createX86IssueVZeroUpperPass()); @@ -631,7 +638,7 @@ void X86PassConfig::addPreEmitPass2() { // Analyzes and emits pseudos to support Win x64 Unwind V2. This pass must run // after all real instructions have been added to the epilog. if (TT.isOSWindows() && TT.isX86_64()) - addPass(createX86WinEHUnwindV2Pass()); + addPass(createX86WinEHUnwindV2LegacyPass()); } bool X86PassConfig::addPostFastRegAllocRewrite() { diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h index ced0a9c71fdd8..fea108a483a9f 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.h +++ b/llvm/lib/Target/X86/X86TargetMachine.h @@ -83,6 +83,8 @@ class X86TargetMachine final : public CodeGenTargetMachineImpl { createMachineScheduler(MachineSchedContext *C) const override; ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override; + + bool canLowerCondLoop() const override { return true; } }; } // end namespace llvm diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index e4ef221e53b12..96541daaeef8e 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -1566,7 +1566,8 @@ InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, // Treat Transpose as 2-op shuffles - there's no difference in lowering. if (Kind == TTI::SK_Transpose) - Kind = TTI::SK_PermuteTwoSrc; + if (LT.second != MVT::v4f64 && LT.second != MVT::v4i64) + Kind = TTI::SK_PermuteTwoSrc; if (Kind == TTI::SK_Broadcast) { // For Broadcasts we are splatting the first element from the first input @@ -1974,6 +1975,9 @@ InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, { TTI::SK_PermuteSingleSrc, MVT::v16f16, { 1, 1, 1, 1 } }, // vpshufb { TTI::SK_PermuteSingleSrc, MVT::v32i8, { 1, 1, 1, 1 } }, // vpshufb + { TTI::SK_Transpose, MVT::v4f64, { 1, 1, 1, 1 } }, // vshufpd/vunpck + { TTI::SK_Transpose, MVT::v4i64, { 1, 1, 1, 1 } }, // vshufpd/vunpck + { TTI::SK_PermuteTwoSrc, MVT::v4f64, { 2, 2, 2, 2 } }, // 2*vshufpd + vblendpd { TTI::SK_PermuteTwoSrc, MVT::v8f32, { 2, 2, 2, 2 } }, // 2*vshufps + vblendps { TTI::SK_PermuteTwoSrc, MVT::v4i64, { 2, 2, 2, 2 } }, // 2*vpshufd + vpblendd @@ -2078,6 +2082,9 @@ InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, { TTI::SK_PermuteSingleSrc, MVT::v32i8, { 4, 4, 4, 4 } }, // vextractf128 + 2*pshufb // + vpor + vinsertf128 + { TTI::SK_Transpose, MVT::v4f64, { 1, 1, 1, 1 } }, // vshufpd/vunpck + { TTI::SK_Transpose, MVT::v4i64, { 1, 1, 1, 1 } }, // vshufpd/vunpck + { TTI::SK_PermuteTwoSrc, MVT::v4f64, { 2, 2, 2, 2 } }, // 2*vshufpd + vblendpd { TTI::SK_PermuteTwoSrc, MVT::v8f32, { 2, 2, 2, 2 } }, // 2*vshufps + vblendps { TTI::SK_PermuteTwoSrc, MVT::v4i64, { 2, 2, 2, 2 } }, // 2*vpermilpd + vblendpd diff --git a/llvm/lib/Target/X86/X86WinEHUnwindV2.cpp b/llvm/lib/Target/X86/X86WinEHUnwindV2.cpp index a1082cd584648..f4a5bdd842c65 100644 --- a/llvm/lib/Target/X86/X86WinEHUnwindV2.cpp +++ b/llvm/lib/Target/X86/X86WinEHUnwindV2.cpp @@ -64,29 +64,31 @@ struct FrameInfo { SmallVector EpilogInfos; }; -class X86WinEHUnwindV2 : public MachineFunctionPass { +class X86WinEHUnwindV2Legacy : public MachineFunctionPass { public: static char ID; - X86WinEHUnwindV2() : MachineFunctionPass(ID) { - initializeX86WinEHUnwindV2Pass(*PassRegistry::getPassRegistry()); + X86WinEHUnwindV2Legacy() : MachineFunctionPass(ID) { + initializeX86WinEHUnwindV2LegacyPass(*PassRegistry::getPassRegistry()); } StringRef getPassName() const override { return "WinEH Unwind V2"; } bool runOnMachineFunction(MachineFunction &MF) override; +}; -private: - /// Rejects the current function due to an internal error within LLVM. - static std::nullopt_t rejectCurrentFunctionInternalError( - const MachineFunction &MF, WinX64EHUnwindV2Mode Mode, StringRef Reason); +/// Rejects the current function due to an internal error within LLVM. +std::nullopt_t rejectCurrentFunctionInternalError(const MachineFunction &MF, + WinX64EHUnwindV2Mode Mode, + StringRef Reason) { + if (Mode == WinX64EHUnwindV2Mode::Required) + reportFatalInternalError("Windows x64 Unwind v2 is required, but LLVM has " + "generated incompatible code in function '" + + MF.getName() + "': " + Reason); - // Continues running the analysis on the given function or funclet. - static std::optional - runAnalysisOnFuncOrFunclet(MachineFunction &MF, - MachineFunction::iterator &Iter, - WinX64EHUnwindV2Mode Mode); -}; + FailsUnwindV2Criteria++; + return std::nullopt; +} enum class FunctionState { InProlog, @@ -97,14 +99,14 @@ enum class FunctionState { } // end anonymous namespace -char X86WinEHUnwindV2::ID = 0; +char X86WinEHUnwindV2Legacy::ID = 0; -INITIALIZE_PASS(X86WinEHUnwindV2, "x86-wineh-unwindv2", +INITIALIZE_PASS(X86WinEHUnwindV2Legacy, "x86-wineh-unwindv2", "Analyze and emit instructions for Win64 Unwind v2", false, false) -FunctionPass *llvm::createX86WinEHUnwindV2Pass() { - return new X86WinEHUnwindV2(); +FunctionPass *llvm::createX86WinEHUnwindV2LegacyPass() { + return new X86WinEHUnwindV2Legacy(); } DebugLoc findDebugLoc(const MachineBasicBlock &MBB) { @@ -115,10 +117,10 @@ DebugLoc findDebugLoc(const MachineBasicBlock &MBB) { return DebugLoc::getUnknown(); } +// Continues running the analysis on the given function or funclet. std::optional -X86WinEHUnwindV2::runAnalysisOnFuncOrFunclet(MachineFunction &MF, - MachineFunction::iterator &Iter, - WinX64EHUnwindV2Mode Mode) { +runAnalysisOnFuncOrFunclet(MachineFunction &MF, MachineFunction::iterator &Iter, + WinX64EHUnwindV2Mode Mode) { const TargetFrameLowering &TFL = *MF.getSubtarget().getFrameLowering(); // Current state of processing the function. We'll assume that all functions @@ -370,7 +372,7 @@ X86WinEHUnwindV2::runAnalysisOnFuncOrFunclet(MachineFunction &MF, EpilogInfos}; } -bool X86WinEHUnwindV2::runOnMachineFunction(MachineFunction &MF) { +bool runX86WinEHUnwindV2(MachineFunction &MF) { WinX64EHUnwindV2Mode Mode = ForceMode.getNumOccurrences() ? static_cast(ForceMode.getValue()) @@ -433,13 +435,15 @@ bool X86WinEHUnwindV2::runOnMachineFunction(MachineFunction &MF) { return true; } -std::nullopt_t X86WinEHUnwindV2::rejectCurrentFunctionInternalError( - const MachineFunction &MF, WinX64EHUnwindV2Mode Mode, StringRef Reason) { - if (Mode == WinX64EHUnwindV2Mode::Required) - reportFatalInternalError("Windows x64 Unwind v2 is required, but LLVM has " - "generated incompatible code in function '" + - MF.getName() + "': " + Reason); +PreservedAnalyses +X86WinEHUnwindV2Pass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + const bool Modified = runX86WinEHUnwindV2(MF); + return Modified ? getMachineFunctionPassPreservedAnalyses() + .preserveSet() + : PreservedAnalyses::all(); +} - FailsUnwindV2Criteria++; - return std::nullopt; +bool X86WinEHUnwindV2Legacy::runOnMachineFunction(MachineFunction &MF) { + return runX86WinEHUnwindV2(MF); } diff --git a/llvm/lib/TargetParser/AVRTargetParser.cpp b/llvm/lib/TargetParser/AVRTargetParser.cpp new file mode 100644 index 0000000000000..ef4a5cf09c20f --- /dev/null +++ b/llvm/lib/TargetParser/AVRTargetParser.cpp @@ -0,0 +1,50 @@ +//===-- AVRTargetParser - Parser for AVR target features ------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements a target parser to recognise AVR hardware features. +/// +//===----------------------------------------------------------------------===// + +#include "llvm/TargetParser/AVRTargetParser.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/Support/Errc.h" + +using namespace llvm; + +Expected AVR::getFeatureSetFromEFlag(const unsigned EFlag) { + static const DenseMap EFlagToFeatureSet = { + {ELF::EF_AVR_ARCH_AVR1, "avr1"}, + {ELF::EF_AVR_ARCH_AVR2, "avr2"}, + {ELF::EF_AVR_ARCH_AVR25, "avr25"}, + {ELF::EF_AVR_ARCH_AVR3, "avr3"}, + {ELF::EF_AVR_ARCH_AVR31, "avr31"}, + {ELF::EF_AVR_ARCH_AVR35, "avr35"}, + {ELF::EF_AVR_ARCH_AVR4, "avr4"}, + {ELF::EF_AVR_ARCH_AVR5, "avr5"}, + {ELF::EF_AVR_ARCH_AVR51, "avr51"}, + {ELF::EF_AVR_ARCH_AVR6, "avr6"}, + {ELF::EF_AVR_ARCH_AVRTINY, "avrtiny"}, + {ELF::EF_AVR_ARCH_XMEGA1, "xmega1"}, + {ELF::EF_AVR_ARCH_XMEGA2, "xmega2"}, + {ELF::EF_AVR_ARCH_XMEGA3, "xmega3"}, + {ELF::EF_AVR_ARCH_XMEGA4, "xmega4"}, + {ELF::EF_AVR_ARCH_XMEGA5, "xmega"}, + {ELF::EF_AVR_ARCH_XMEGA6, "xmega"}, + {ELF::EF_AVR_ARCH_XMEGA7, "xmega"}, + }; + + auto It = EFlagToFeatureSet.find(EFlag); + if (It != EFlagToFeatureSet.end()) + return It->second.str(); + + return createStringError(errc::invalid_argument, + "unrecognised AVR version, 0x" + + Twine::utohexstr(EFlag)); +} diff --git a/llvm/lib/TargetParser/CMakeLists.txt b/llvm/lib/TargetParser/CMakeLists.txt index e1a30199e1ade..8d474497f5308 100644 --- a/llvm/lib/TargetParser/CMakeLists.txt +++ b/llvm/lib/TargetParser/CMakeLists.txt @@ -17,6 +17,7 @@ add_llvm_component_library(LLVMTargetParser AArch64TargetParser.cpp ARMTargetParserCommon.cpp ARMTargetParser.cpp + AVRTargetParser.cpp CSKYTargetParser.cpp Host.cpp LoongArchTargetParser.cpp diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index b01dca93dee0c..e1bdfbe42d07f 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -1340,6 +1340,12 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family, *Subtype = X86::AMDFAM1AH_ZNVER5; break; // "znver5" } + if ((Model >= 0x50 && Model <= 0x5f) || (Model >= 0x80 && Model <= 0xcf) || + (Model >= 0xd8 && Model <= 0xe7)) { + CPU = "znver6"; + *Subtype = X86::AMDFAM1AH_ZNVER6; + break; // "znver6" + } break; default: diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index d0bd39f15afc4..eef426d7c9aee 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -12,13 +12,20 @@ //===----------------------------------------------------------------------===// #include "llvm/TargetParser/RISCVTargetParser.h" +#include "llvm/ADT/SetOperations.h" +#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" +#include "llvm/ADT/StringTable.h" #include "llvm/TargetParser/RISCVISAInfo.h" namespace llvm { namespace RISCV { +char ParserError::ID = 0; +char ParserWarning::ID = 0; + enum CPUKind : unsigned { #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \ FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \ @@ -145,6 +152,204 @@ void getFeaturesForCPU(StringRef CPU, EnabledFeatures.push_back(F.substr(1)); } +namespace { +class RISCVTuneFeatureLookupTable { + struct RISCVTuneFeature { + unsigned PosIdx; + unsigned NegIdx; + unsigned FeatureIdx; + }; + + struct RISCVImpliedTuneFeature { + unsigned FeatureIdx; + unsigned ImpliedFeatureIdx; + }; + + struct RISCVConfigurableTuneFeatures { + StringRef Processor; + unsigned DirectiveIdx; + + bool operator<(const RISCVConfigurableTuneFeatures &RHS) const { + return Processor < RHS.Processor; + } + }; + +#define GET_TUNE_FEATURES +#define GET_CONFIGURABLE_TUNE_FEATURES +#include "llvm/TargetParser/RISCVTargetParserDef.inc" + + // Positive directive name -> Feature name + StringMap PositiveMap; + // Negative directive name -> Feature name + StringMap NegativeMap; + + StringMap> ImpliedFeatureMap; + StringMap> InvImpliedFeatureMap; + +public: + using SmallStringSet = SmallSet; + + static void getAllTuneFeatures(SmallVectorImpl &Features) { + for (const auto &TuneFeature : TuneFeatures) + Features.push_back(TuneFeatureStrings[TuneFeature.FeatureIdx]); + } + + static void getConfigurableFeatures(StringRef ProcName, + SmallStringSet &Directives) { + // Entries for the same processor are always put together. + auto [ItFirst, ItEnd] = + std::equal_range(std::begin(ConfigurableTuneFeatures), + std::end(ConfigurableTuneFeatures), + RISCVConfigurableTuneFeatures{ProcName, 0}); + for (; ItFirst != ItEnd; ++ItFirst) + Directives.insert(TuneFeatureStrings[ItFirst->DirectiveIdx]); + } + + RISCVTuneFeatureLookupTable() { + for (const auto &TuneFeature : TuneFeatures) { + StringRef PosDirective = TuneFeatureStrings[TuneFeature.PosIdx]; + StringRef NegDirective = TuneFeatureStrings[TuneFeature.NegIdx]; + StringRef FeatureName = TuneFeatureStrings[TuneFeature.FeatureIdx]; + PositiveMap[PosDirective] = FeatureName; + NegativeMap[NegDirective] = FeatureName; + } + + for (const auto &Imp : ImpliedTuneFeatures) { + StringRef Feature = TuneFeatureStrings[Imp.FeatureIdx]; + StringRef ImpliedFeature = TuneFeatureStrings[Imp.ImpliedFeatureIdx]; + ImpliedFeatureMap[Feature].push_back(ImpliedFeature); + InvImpliedFeatureMap[ImpliedFeature].push_back(Feature); + } + } + + /// Returns {Feature name, Is positive or not}, or empty feature name + /// if not found. + std::pair getFeature(StringRef DirectiveName) const { + auto It = PositiveMap.find(DirectiveName); + if (It != PositiveMap.end()) + return {It->getValue(), /*IsPositive=*/true}; + + return {NegativeMap.lookup(DirectiveName), /*IsPositive=*/false}; + } + + /// Returns the implied features, or empty ArrayRef if not found. Note: + /// ImpliedFeatureMap / InvImpliedFeatureMap are the owners of these implied + /// feature lists, so we can just return the ArrayRef. + ArrayRef featureImplies(StringRef FeatureName, + bool Inverse = false) const { + const auto &Map = Inverse ? InvImpliedFeatureMap : ImpliedFeatureMap; + auto It = Map.find(FeatureName); + if (It == Map.end()) + return {}; + return It->second; + } +}; +} // namespace + +void getAllTuneFeatures(SmallVectorImpl &Features) { + RISCVTuneFeatureLookupTable::getAllTuneFeatures(Features); +} + +Error parseTuneFeatureString(StringRef ProcName, StringRef TFString, + SmallVectorImpl &ResFeatures) { + RISCVTuneFeatureLookupTable TFLookup; + using SmallStringSet = RISCVTuneFeatureLookupTable::SmallStringSet; + + // Do not create ParserWarning right away. Instead, we store the warning + // message until the last moment. + std::string WarningMsg; + + TFString = TFString.trim(); + if (TFString.empty()) + return Error::success(); + + // Note: StringSet is not really ergonomic to use in this case here. + SmallStringSet PositiveFeatures; + SmallStringSet NegativeFeatures; + SmallStringSet PerProcDirectives; + RISCVTuneFeatureLookupTable::getConfigurableFeatures(ProcName, + PerProcDirectives); + if (PerProcDirectives.empty() && !ProcName.empty()) + return make_error("Processor '" + Twine(ProcName) + + "' has no " + "configurable tuning features"); + + // Phase 1: Collect explicit features. + StringRef DirectiveStr; + do { + std::tie(DirectiveStr, TFString) = TFString.split(","); + auto [FeatureName, IsPositive] = TFLookup.getFeature(DirectiveStr); + if (FeatureName.empty()) { + raw_string_ostream SS(WarningMsg); + SS << "unrecognized tune feature directive '" << DirectiveStr << "'"; + continue; + } + + auto &Features = IsPositive ? PositiveFeatures : NegativeFeatures; + if (!Features.insert(FeatureName).second) + return make_error( + "cannot specify more than one instance of '" + Twine(DirectiveStr) + + "'"); + + if (!PerProcDirectives.count(DirectiveStr) && !ProcName.empty()) + return make_error("Directive '" + Twine(DirectiveStr) + + "' is not " + "allowed to be used with processor '" + + Twine(ProcName) + "'"); + } while (!TFString.empty()); + + auto Intersection = + llvm::set_intersection(PositiveFeatures, NegativeFeatures); + if (!Intersection.empty()) { + std::string IntersectedStr = join(Intersection, "', '"); + return make_error("Feature(s) '" + Twine(IntersectedStr) + + "' cannot appear in both " + "positive and negative directives"); + } + + // Phase 2: Derive implied features. + SmallStringSet DerivedPosFeatures; + SmallStringSet DerivedNegFeatures; + for (StringRef PF : PositiveFeatures) { + if (auto FeatureList = TFLookup.featureImplies(PF); !FeatureList.empty()) + DerivedPosFeatures.insert_range(FeatureList); + } + for (StringRef NF : NegativeFeatures) { + if (auto FeatureList = TFLookup.featureImplies(NF, /*Inverse=*/true); + !FeatureList.empty()) + DerivedNegFeatures.insert_range(FeatureList); + } + PositiveFeatures.insert_range(DerivedPosFeatures); + NegativeFeatures.insert_range(DerivedNegFeatures); + + Intersection = llvm::set_intersection(PositiveFeatures, NegativeFeatures); + if (!Intersection.empty()) { + std::string IntersectedStr = join(Intersection, "', '"); + return make_error("Feature(s) '" + Twine(IntersectedStr) + + "' were implied by both " + "positive and negative directives"); + } + + // Export the result. + const std::string PosPrefix("+"); + const std::string NegPrefix("-"); + for (StringRef PF : PositiveFeatures) + ResFeatures.emplace_back(PosPrefix + PF.str()); + for (StringRef NF : NegativeFeatures) + ResFeatures.emplace_back(NegPrefix + NF.str()); + + if (WarningMsg.empty()) + return Error::success(); + + return make_error(WarningMsg); +} + +void getCPUConfigurableTuneFeatures(StringRef CPU, + SmallVectorImpl &Directives) { + RISCVTuneFeatureLookupTable::SmallStringSet DirectiveSet; + RISCVTuneFeatureLookupTable::getConfigurableFeatures(CPU, DirectiveSet); + Directives.assign(DirectiveSet.begin(), DirectiveSet.end()); +} } // namespace RISCV namespace RISCVVType { diff --git a/llvm/lib/TargetParser/TargetParser.cpp b/llvm/lib/TargetParser/TargetParser.cpp index 4f9d94a1a8fcd..d317ca4e1194a 100644 --- a/llvm/lib/TargetParser/TargetParser.cpp +++ b/llvm/lib/TargetParser/TargetParser.cpp @@ -172,6 +172,7 @@ constexpr GPUInfo AMDGCNGPUs[] = { {{"gfx1151"}, {"gfx1151"}, GK_GFX1151, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1152"}, {"gfx1152"}, GK_GFX1152, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1153"}, {"gfx1153"}, GK_GFX1153, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, + {{"gfx1170"}, {"gfx1170"}, GK_GFX1170, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1200"}, {"gfx1200"}, GK_GFX1200, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1201"}, {"gfx1201"}, GK_GFX1201, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1250"}, {"gfx1250"}, GK_GFX1250, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK_ALWAYS}, @@ -329,6 +330,7 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) { case GK_GFX1151: return {11, 5, 1}; case GK_GFX1152: return {11, 5, 2}; case GK_GFX1153: return {11, 5, 3}; + case GK_GFX1170: return {11, 7, 0}; case GK_GFX1200: return {12, 0, 0}; case GK_GFX1201: return {12, 0, 1}; case GK_GFX1250: return {12, 5, 0}; @@ -515,6 +517,10 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["fp8-conversion-insts"] = true; Features["atomic-fmin-fmax-global-f32"] = true; break; + case GK_GFX1170: + // TODO-GFX1170: Update features map for gfx1170 + Features["fp8-conversion-insts"] = true; + [[fallthrough]]; case GK_GFX1153: case GK_GFX1152: case GK_GFX1151: diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index e6a9eedab5954..a3ea5d823033d 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -343,6 +343,8 @@ StringRef Triple::getOSTypeName(OSType Kind) { return "cheriotrtos"; case ChipStar: return "chipstar"; + case Firmware: + return "firmware"; } llvm_unreachable("Invalid OSType"); @@ -757,6 +759,7 @@ static Triple::OSType parseOS(StringRef OSName) { .StartsWith("vulkan", Triple::Vulkan) .StartsWith("cheriotrtos", Triple::CheriotRTOS) .StartsWith("chipstar", Triple::ChipStar) + .StartsWith("firmware", Triple::Firmware) .Default(Triple::UnknownOS); } @@ -1395,6 +1398,12 @@ std::string Triple::normalize(StringRef Str, CanonicalForm Form) { } } + // Currently the firmware OS is an Apple specific concept. + if ((Components.size() > 2) && (Components[2] == "firmware") && + (Components[1] != "apple")) + llvm::reportFatalUsageError( + "the firmware target os is only supported for the apple vendor"); + // Canonicalize the components if necessary. switch (Form) { case CanonicalForm::ANY: @@ -1528,6 +1537,8 @@ bool Triple::getMacOSXVersion(VersionTuple &Version) const { llvm_unreachable("OSX version isn't relevant for xrOS"); case DriverKit: llvm_unreachable("OSX version isn't relevant for DriverKit"); + case Firmware: + llvm_unreachable("OSX version isn't relevant for Firmware"); } return true; } @@ -1578,6 +1589,8 @@ VersionTuple Triple::getiOSVersion() const { llvm_unreachable("conflicting triple info"); case DriverKit: llvm_unreachable("DriverKit doesn't have an iOS version"); + case Firmware: + llvm_unreachable("iOS version isn't relevant for Firmware"); } } @@ -1603,6 +1616,8 @@ VersionTuple Triple::getWatchOSVersion() const { llvm_unreachable("watchOS version isn't relevant for xrOS"); case DriverKit: llvm_unreachable("DriverKit doesn't have a WatchOS version"); + case Firmware: + llvm_unreachable("watchOS version isn't relevant for Firmware"); } } diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp index 2810849e4af9e..f848b1ac08607 100644 --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -255,6 +255,10 @@ static constexpr FeatureBitset FeaturesZNVER5 = FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B | FeatureAVX512VP2INTERSECT | FeaturePREFETCHI | FeatureAVXVNNI; +static constexpr FeatureBitset FeaturesZNVER6 = + FeaturesZNVER5 | FeatureAVXVNNIINT8 | FeatureAVX512FP16 | FeatureAVXIFMA | + FeatureAVXNECONVERT; + // D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from // X86TargetParser.def to here. They are assigned by following ways: // 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign @@ -440,6 +444,7 @@ constexpr ProcInfo Processors[] = { { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false }, { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false }, { {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false }, + { {"znver6"}, CK_ZNVER6, FEATURE_AVX512FP16, FeaturesZNVER6, '\0', false }, // Generic 64-bit processor. { {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false }, { {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false }, diff --git a/llvm/lib/Transforms/Coroutines/CoroCleanup.cpp b/llvm/lib/Transforms/Coroutines/CoroCleanup.cpp index 6b68cf5bc2c20..c44eaddd7ee55 100644 --- a/llvm/lib/Transforms/Coroutines/CoroCleanup.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroCleanup.cpp @@ -8,6 +8,7 @@ #include "llvm/Transforms/Coroutines/CoroCleanup.h" #include "CoroInternal.h" +#include "llvm/Analysis/PtrUseVisitor.h" #include "llvm/IR/DIBuilder.h" #include "llvm/IR/Function.h" #include "llvm/IR/IRBuilder.h" @@ -15,6 +16,7 @@ #include "llvm/IR/Module.h" #include "llvm/IR/PassManager.h" #include "llvm/Transforms/Scalar/SimplifyCFG.h" +#include "llvm/Transforms/Utils/Local.h" using namespace llvm; @@ -30,9 +32,28 @@ struct Lowerer : coro::LowererBase { bool lower(Function &F); private: - void elideCoroNoop(IntrinsicInst *II); void lowerCoroNoop(IntrinsicInst *II); }; + +// Recursively walk and eliminate resume/destroy call on noop coro +class NoopCoroElider : public PtrUseVisitor { + using Base = PtrUseVisitor; + + IRBuilder<> Builder; + +public: + NoopCoroElider(const DataLayout &DL, LLVMContext &C) : Base(DL), Builder(C) {} + + void run(IntrinsicInst *II); + + void visitLoadInst(LoadInst &I) { enqueueUsers(I); } + void visitCallBase(CallBase &CB); + void visitIntrinsicInst(IntrinsicInst &II); + +private: + bool tryEraseCallInvoke(Instruction *I); + void eraseFromWorklist(Instruction *I); +}; } static void lowerSubFn(IRBuilder<> &Builder, CoroSubFnInst *SubFn) { @@ -73,6 +94,7 @@ bool Lowerer::lower(Function &F) { bool IsPrivateAndUnprocessed = F.isPresplitCoroutine() && F.hasLocalLinkage(); bool Changed = false; + NoopCoroElider NCE(F.getDataLayout(), F.getContext()); SmallPtrSet DeadInsts{}; for (Instruction &I : instructions(F)) { if (auto *II = dyn_cast(&I)) { @@ -100,7 +122,7 @@ bool Lowerer::lower(Function &F) { II->replaceAllUsesWith(ConstantTokenNone::get(Context)); break; case Intrinsic::coro_noop: - elideCoroNoop(II); + NCE.run(II); if (!II->user_empty()) lowerCoroNoop(II); break; @@ -142,28 +164,6 @@ bool Lowerer::lower(Function &F) { return Changed; } -void Lowerer::elideCoroNoop(IntrinsicInst *II) { - for (User *U : make_early_inc_range(II->users())) { - auto *Fn = dyn_cast(U); - if (Fn == nullptr) - continue; - - auto *User = Fn->getUniqueUndroppableUser(); - if (auto *Call = dyn_cast(User)) { - Call->eraseFromParent(); - Fn->eraseFromParent(); - continue; - } - - if (auto *I = dyn_cast(User)) { - Builder.SetInsertPoint(I); - Builder.CreateBr(I->getNormalDest()); - I->eraseFromParent(); - Fn->eraseFromParent(); - } - } -} - void Lowerer::lowerCoroNoop(IntrinsicInst *II) { if (!NoopCoro) { LLVMContext &C = Builder.getContext(); @@ -200,6 +200,60 @@ void Lowerer::lowerCoroNoop(IntrinsicInst *II) { II->replaceAllUsesWith(NoopCoroVoidPtr); } +void NoopCoroElider::run(IntrinsicInst *II) { + visitPtr(*II); + + Worklist.clear(); + VisitedUses.clear(); +} + +void NoopCoroElider::visitCallBase(CallBase &CB) { + auto *V = U->get(); + bool ResumeOrDestroy = V == CB.getCalledOperand(); + if (ResumeOrDestroy) { + [[maybe_unused]] bool Success = tryEraseCallInvoke(&CB); + assert(Success && "Unexpected CallBase"); + + auto AboutToDeleteCallback = [this](Value *V) { + eraseFromWorklist(cast(V)); + }; + RecursivelyDeleteTriviallyDeadInstructions(V, nullptr, nullptr, + AboutToDeleteCallback); + } +} + +void NoopCoroElider::visitIntrinsicInst(IntrinsicInst &II) { + if (auto *SubFn = dyn_cast(&II)) { + auto *User = SubFn->getUniqueUndroppableUser(); + if (!tryEraseCallInvoke(cast(User))) + return; + SubFn->eraseFromParent(); + } +} + +bool NoopCoroElider::tryEraseCallInvoke(Instruction *I) { + if (auto *Call = dyn_cast(I)) { + eraseFromWorklist(Call); + Call->eraseFromParent(); + return true; + } + + if (auto *II = dyn_cast(I)) { + Builder.SetInsertPoint(II); + Builder.CreateBr(II->getNormalDest()); + eraseFromWorklist(II); + II->eraseFromParent(); + return true; + } + return false; +} + +void NoopCoroElider::eraseFromWorklist(Instruction *I) { + erase_if(Worklist, [I](UseToVisit &U) { + return I == U.UseAndIsOffsetKnown.getPointer()->getUser(); + }); +} + static bool declaresCoroCleanupIntrinsics(const Module &M) { return coro::declaresIntrinsics( M, diff --git a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp index 675a5af368e7f..cfbf9dec01619 100644 --- a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp +++ b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp @@ -50,6 +50,7 @@ #include "llvm/IR/BasicBlock.h" #include "llvm/IR/CFG.h" #include "llvm/IR/Constants.h" +#include "llvm/IR/DIBuilder.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Dominators.h" @@ -432,6 +433,16 @@ doPromotion(Function *F, FunctionAnalysisManager &FAM, PromoteMemToReg(Allocas, DT, &AC); } + // If argument(s) are dead (hence removed) or promoted, the function probably + // does not follow the standard calling convention anymore. Add DW_CC_nocall + // to DISubroutineType to inform debugger that it may not be safe to call this + // function. + DISubprogram *SP = NF->getSubprogram(); + if (SP) { + auto Temp = SP->getType()->cloneWithCC(llvm::dwarf::DW_CC_nocall); + SP->replaceType(MDNode::replaceWithPermanent(std::move(Temp))); + } + return NF; } diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index 3b59ebbbb9322..9a35696b7627c 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -3931,7 +3931,8 @@ static bool runAttributorLightOnFunctions(InformationCache &InfoCache, &AANoFree::ID, &AANoReturn::ID, &AAMemoryLocation::ID, &AAMemoryBehavior::ID, &AAUnderlyingObjects::ID, &AANoCapture::ID, &AAInterFnReachability::ID, &AAIntraFnReachability::ID, &AACallEdges::ID, - &AANoFPClass::ID, &AAMustProgress::ID, &AANonNull::ID}); + &AANoFPClass::ID, &AAMustProgress::ID, &AANonNull::ID, + &AADenormalFPMath::ID}); AC.Allowed = &Allowed; AC.UseLiveness = false; diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp index 86bdb7c49c0e3..37bf2b9c1a966 100644 --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -9016,15 +9016,9 @@ struct AADenormalFPMathFunction final : AADenormalFPMathImpl { void initialize(Attributor &A) override { const Function *F = getAnchorScope(); - DenormalMode Mode = F->getDenormalModeRaw(); - DenormalMode ModeF32 = F->getDenormalModeF32Raw(); - - // TODO: Handling this here prevents handling the case where a callee has a - // fixed denormal-fp-math with dynamic denormal-fp-math-f32, but called from - // a function with a fully fixed mode. - if (ModeF32 == DenormalMode::getInvalid()) - ModeF32 = Mode; - Known = DenormalState{Mode, ModeF32}; + DenormalFPEnv DenormEnv = F->getDenormalFPEnv(); + + Known = DenormalState{DenormEnv.DefaultMode, DenormEnv.F32Mode}; if (isModeFixed()) indicateFixpoint(); } @@ -9060,19 +9054,17 @@ struct AADenormalFPMathFunction final : AADenormalFPMathImpl { LLVMContext &Ctx = getAssociatedFunction()->getContext(); SmallVector AttrToAdd; - SmallVector AttrToRemove; - if (Known.Mode == DenormalMode::getDefault()) { - AttrToRemove.push_back("denormal-fp-math"); - } else { - AttrToAdd.push_back( - Attribute::get(Ctx, "denormal-fp-math", Known.Mode.str())); - } + SmallVector AttrToRemove; + + // TODO: Change to use DenormalFPEnv everywhere. + DenormalFPEnv KnownEnv(Known.Mode, Known.ModeF32); - if (Known.ModeF32 != Known.Mode) { - AttrToAdd.push_back( - Attribute::get(Ctx, "denormal-fp-math-f32", Known.ModeF32.str())); + if (KnownEnv == DenormalFPEnv::getDefault()) { + AttrToRemove.push_back(Attribute::DenormalFPEnv); } else { - AttrToRemove.push_back("denormal-fp-math-f32"); + AttrToAdd.push_back(Attribute::get( + Ctx, Attribute::DenormalFPEnv, + DenormalFPEnv(Known.Mode, Known.ModeF32).toIntValue())); } auto &IRP = getIRPosition(); @@ -9083,7 +9075,7 @@ struct AADenormalFPMathFunction final : AADenormalFPMathImpl { } void trackStatistics() const override { - STATS_DECLTRACK_FN_ATTR(denormal_fp_math) + STATS_DECLTRACK_FN_ATTR(denormal_fpenv) } }; } // namespace diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp index 50130da01c7ba..855692db006f9 100644 --- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp +++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp @@ -2394,10 +2394,7 @@ static bool addNoRecurseAttrsTopDown(Function &F) { // also detects if F is directly recursive as F is not yet marked as // a norecurse function. for (auto &U : F.uses()) { - auto *I = dyn_cast(U.getUser()); - if (!I) - return false; - CallBase *CB = dyn_cast(I); + const CallBase *CB = dyn_cast(U.getUser()); if (!CB || !CB->isCallee(&U) || !CB->getParent()->getParent()->doesNotRecurse()) return false; diff --git a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp index 234698ec6227a..9c168c9d31b25 100644 --- a/llvm/lib/Transforms/IPO/OpenMPOpt.cpp +++ b/llvm/lib/Transforms/IPO/OpenMPOpt.cpp @@ -908,8 +908,11 @@ struct OffloadArray { GetPointerBaseWithConstantOffset(S->getPointerOperand(), Offset, DL); if (Dst == &Array) { int64_t Idx = Offset / PointerSize; - StoredValues[Idx] = getUnderlyingObject(S->getValueOperand()); - LastAccesses[Idx] = S; + // Ignore updates that must be UB (probably in dead code at runtime) + if ((uint64_t)Idx < NumValues) { + StoredValues[Idx] = getUnderlyingObject(S->getValueOperand()); + LastAccesses[Idx] = S; + } } } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index 72a6e64ccdc10..8eeeccbc86523 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -2987,9 +2987,13 @@ static Instruction *foldFNegIntoConstant(Instruction &I, const DataLayout &DL) { return BinaryOperator::CreateFMulFMF(X, NegC, FMF); } // -(X / C) --> X / (-C) - if (match(FNegOp, m_FDiv(m_Value(X), m_Constant(C)))) - if (Constant *NegC = ConstantFoldUnaryOpOperand(Instruction::FNeg, C, DL)) - return BinaryOperator::CreateFDivFMF(X, NegC, &I); + if (match(FNegOp, m_FDiv(m_Value(X), m_Constant(C)))) { + if (Constant *NegC = ConstantFoldUnaryOpOperand(Instruction::FNeg, C, DL)) { + Instruction *FDiv = BinaryOperator::CreateFDivFMF(X, NegC, &I); + FDiv->copyMetadata(*FNegOp); + return FDiv; + } + } // -(C / X) --> (-C) / X if (match(FNegOp, m_FDiv(m_Constant(C), m_Value(X)))) if (Constant *NegC = ConstantFoldUnaryOpOperand(Instruction::FNeg, C, DL)) { @@ -3002,6 +3006,7 @@ static Instruction *foldFNegIntoConstant(Instruction &I, const DataLayout &DL) { FastMathFlags OpFMF = FNegOp->getFastMathFlags(); FDiv->setHasNoSignedZeros(FMF.noSignedZeros() && OpFMF.noSignedZeros()); FDiv->setHasNoInfs(FMF.noInfs() && OpFMF.noInfs()); + FDiv->copyMetadata(*FNegOp); return FDiv; } // With NSZ [ counter-example with -0.0: -(-0.0 + 0.0) != 0.0 + -0.0 ]: @@ -3024,8 +3029,10 @@ Instruction *InstCombinerImpl::hoistFNegAboveFMulFDiv(Value *FNegOp, } if (match(FNegOp, m_FDiv(m_Value(X), m_Value(Y)))) { - return cast(Builder.CreateFDivFMF( + auto *FDiv = cast(Builder.CreateFDivFMF( Builder.CreateFNegFMF(X, &FMFSource), Y, &FMFSource)); + FDiv->copyMetadata(*cast(FNegOp)); + return FDiv; } if (IntrinsicInst *II = dyn_cast(FNegOp)) { diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index fcd0c89ea1e11..90bbd102868c5 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -51,6 +51,7 @@ #include "llvm/IR/LLVMContext.h" #include "llvm/IR/Metadata.h" #include "llvm/IR/PatternMatch.h" +#include "llvm/IR/ProfDataUtils.h" #include "llvm/IR/Statepoint.h" #include "llvm/IR/Type.h" #include "llvm/IR/User.h" @@ -2117,8 +2118,9 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) { return nullptr; Value *Cmp = Builder.CreateICmpEQ(X, ConstantInt::get(X->getType(), 0)); - Value *NewSelect = - Builder.CreateSelect(Cmp, ConstantInt::get(X->getType(), 1), A); + Value *NewSelect = nullptr; + NewSelect = Builder.CreateSelectWithUnknownProfile( + Cmp, ConstantInt::get(X->getType(), 1), A, DEBUG_TYPE); return replaceInstUsesWith(*II, NewSelect); }; @@ -2868,14 +2870,26 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) { } // m((fpext X), (fpext Y)) -> fpext (m(X, Y)) - if (match(Arg0, m_OneUse(m_FPExt(m_Value(X)))) && - match(Arg1, m_OneUse(m_FPExt(m_Value(Y)))) && + if (match(Arg0, m_FPExt(m_Value(X))) && match(Arg1, m_FPExt(m_Value(Y))) && + (Arg0->hasOneUse() || Arg1->hasOneUse()) && X->getType() == Y->getType()) { Value *NewCall = Builder.CreateBinaryIntrinsic(IID, X, Y, II, II->getName()); return new FPExtInst(NewCall, II->getType()); } + // m(fpext X, C) -> fpext m(X, TruncC) if C can be losslessly truncated. + Constant *C; + if (match(Arg0, m_OneUse(m_FPExt(m_Value(X)))) && + match(Arg1, m_ImmConstant(C))) { + if (Constant *TruncC = + getLosslessInvCast(C, X->getType(), Instruction::FPExt, DL)) { + Value *NewCall = + Builder.CreateBinaryIntrinsic(IID, X, TruncC, II, II->getName()); + return new FPExtInst(NewCall, II->getType()); + } + } + // max X, -X --> fabs X // min X, -X --> -(fabs X) // TODO: Remove one-use limitation? That is obviously better for max, @@ -3657,6 +3671,16 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) { continue; return CallBase::removeOperandBundle(II, OBU.getTagID()); } + + if (OBU.getTagName() == "nonnull" && OBU.Inputs.size() == 1) { + RetainedKnowledge RK = getKnowledgeFromOperandInAssume( + *cast(II), II->arg_size() + Idx); + if (!RK || RK.AttrKind != Attribute::NonNull || + !isKnownNonZero(RK.WasOn, + getSimplifyQuery().getWithInstruction(II))) + continue; + return CallBase::removeOperandBundle(II, OBU.getTagID()); + } } // Convert nonnull assume like: @@ -3685,8 +3709,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) { // into // call void @llvm.assume(i1 true) [ "align"(i32* [[A]], i64 Constant + 1)] uint64_t AlignMask = 1; - if (EnableKnowledgeRetention && - (match(IIOperand, m_Not(m_Trunc(m_Value(A)))) || + if ((match(IIOperand, m_Not(m_Trunc(m_Value(A)))) || match(IIOperand, m_SpecificICmp(ICmpInst::ICMP_EQ, m_And(m_Value(A), m_ConstantInt(AlignMask)), @@ -3700,7 +3723,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) { /// TODO: we can generate a GEP instead of merging the alignment with /// the offset. RetainedKnowledge RK{Attribute::Alignment, - (unsigned)MinAlign(Offset, AlignMask + 1), A}; + MinAlign(Offset, AlignMask + 1), A}; if (auto *Replacement = buildAssumeFromKnowledge(RK, Next, &AC, &DT)) { diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp index 0cd2c09726a2d..a75c24bb91219 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -698,6 +698,10 @@ static Instruction *foldVecExtTruncToExtElt(TruncInst &Trunc, auto VecElts = VecOpTy->getElementCount(); uint64_t BitCastNumElts = VecElts.getKnownMinValue() * TruncRatio; + // Make sure we don't overflow in the calculation of the new index. + // (VecOpIdx + 1) * TruncRatio should not overflow. + if (Cst->uge(std::numeric_limits::max() / TruncRatio)) + return nullptr; uint64_t VecOpIdx = Cst->getZExtValue(); uint64_t NewIdx = IC.getDataLayout().isBigEndian() ? (VecOpIdx + 1) * TruncRatio - 1 @@ -711,17 +715,21 @@ static Instruction *foldVecExtTruncToExtElt(TruncInst &Trunc, return nullptr; uint64_t IdxOfs = ShiftAmount->udiv(DstBits).getZExtValue(); + // IdxOfs is guaranteed to be less than TruncRatio, so we won't overflow in + // the adjustment. + assert(IdxOfs < TruncRatio && + "IdxOfs is expected to be less than TruncRatio."); NewIdx = IC.getDataLayout().isBigEndian() ? (NewIdx - IdxOfs) : (NewIdx + IdxOfs); } assert(BitCastNumElts <= std::numeric_limits::max() && - NewIdx <= std::numeric_limits::max() && "overflow 32-bits"); + "overflow 32-bits"); auto *BitCastTo = VectorType::get(DstType, BitCastNumElts, VecElts.isScalable()); Value *BitCast = IC.Builder.CreateBitCast(VecOp, BitCastTo); - return ExtractElementInst::Create(BitCast, IC.Builder.getInt32(NewIdx)); + return ExtractElementInst::Create(BitCast, IC.Builder.getInt64(NewIdx)); } /// Funnel/Rotate left/right may occur in a wider type than necessary because of diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index aa762753130b0..bce609275ffa9 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -1786,11 +1786,8 @@ Instruction *InstCombinerImpl::foldICmpAndConstConst(ICmpInst &Cmp, const APInt &C1) { bool isICMP_NE = Cmp.getPredicate() == ICmpInst::ICMP_NE; - // For vectors: icmp ne (and X, 1), 0 --> trunc X to N x i1 - // TODO: We canonicalize to the longer form for scalars because we have - // better analysis/folds for icmp, and codegen may be better with icmp. - if (isICMP_NE && Cmp.getType()->isVectorTy() && C1.isZero() && - match(And->getOperand(1), m_One())) + // icmp ne (and X, 1), 0 --> trunc X to i1 + if (isICMP_NE && C1.isZero() && match(And->getOperand(1), m_One())) return new TruncInst(And->getOperand(0), Cmp.getType()); const APInt *C2; @@ -2009,8 +2006,8 @@ Instruction *InstCombinerImpl::foldICmpAndConstant(ICmpInst &Cmp, { Value *A; const APInt *Addend, *Msk; - if (match(And, m_And(m_OneUse(m_Add(m_Value(A), m_APInt(Addend))), - m_LowBitMask(Msk))) && + if (match(And, m_OneUse(m_And(m_OneUse(m_Add(m_Value(A), m_APInt(Addend))), + m_LowBitMask(Msk)))) && C.ule(*Msk)) { APInt NewComperand = (C - *Addend) & *Msk; Value *MaskA = Builder.CreateAnd(A, ConstantInt::get(A->getType(), *Msk)); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h index 8c8b300bb2002..8a478bf344536 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h +++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h @@ -805,6 +805,7 @@ class LLVM_LIBRARY_VISIBILITY InstCombinerImpl final Instruction *foldSelectExtConst(SelectInst &Sel); Instruction *foldSelectEqualityTest(SelectInst &SI); Instruction *foldSelectOpOp(SelectInst &SI, Instruction *TI, Instruction *FI); + Instruction *foldSelectIntrinsic(SelectInst &SI); Instruction *foldSelectIntoOp(SelectInst &SI, Value *, Value *); Instruction *foldSPFofSPF(Instruction *Inner, SelectPatternFlavor SPF1, Value *A, Value *B, Instruction &Outer, diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 759af82ebbbdc..8d053bd499fce 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -41,6 +41,10 @@ using namespace llvm; using namespace PatternMatch; +namespace llvm { +extern cl::opt ProfcheckDisableMetadataFixes; +} + /// The specific integer value is used in a context where it is known to be /// non-zero. If this allows us to simplify the computation, do so and return /// the new operand, otherwise return null. @@ -1619,7 +1623,9 @@ Value *InstCombinerImpl::takeLog2(Value *Op, unsigned Depth, bool AssumeNonZero, if (Value *LogY = takeLog2(SI->getOperand(2), Depth, AssumeNonZero, DoFold)) return IfFold([&]() { - return Builder.CreateSelect(SI->getOperand(0), LogX, LogY); + return Builder.CreateSelect(SI->getOperand(0), LogX, LogY, "", + ProfcheckDisableMetadataFixes ? nullptr + : SI); }); // log2(umin(X, Y)) -> umin(log2(X), log2(Y)) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index fb30a4545cffe..1a8be9436f4ff 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -493,6 +493,51 @@ Instruction *InstCombinerImpl::foldSelectOpOp(SelectInst &SI, Instruction *TI, return nullptr; } +/// This transforms patterns of the form: +/// select cond, intrinsic(x, ...), intrinsic(y, ...) +/// into: +/// intrinsic(select cond, x, y, ...) +Instruction *InstCombinerImpl::foldSelectIntrinsic(SelectInst &SI) { + auto *LHSIntrinsic = dyn_cast(SI.getTrueValue()); + if (!LHSIntrinsic) + return nullptr; + auto *RHSIntrinsic = dyn_cast(SI.getFalseValue()); + if (!RHSIntrinsic || + LHSIntrinsic->getIntrinsicID() != RHSIntrinsic->getIntrinsicID() || + !LHSIntrinsic->hasOneUse() || !RHSIntrinsic->hasOneUse()) + return nullptr; + + const Intrinsic::ID IID = LHSIntrinsic->getIntrinsicID(); + switch (IID) { + case Intrinsic::abs: + case Intrinsic::cttz: + case Intrinsic::ctlz: { + auto *TZ = cast(LHSIntrinsic->getArgOperand(1)); + auto *FZ = cast(RHSIntrinsic->getArgOperand(1)); + + Value *TV = LHSIntrinsic->getArgOperand(0); + Value *FV = RHSIntrinsic->getArgOperand(0); + + Value *NewSel = Builder.CreateSelect(SI.getCondition(), TV, FV, "", &SI); + Value *NewPoisonFlag = Builder.CreateAnd(TZ, FZ); + Value *NewCall = Builder.CreateBinaryIntrinsic(IID, NewSel, NewPoisonFlag); + + return replaceInstUsesWith(SI, NewCall); + } + case Intrinsic::ctpop: { + Value *TV = LHSIntrinsic->getArgOperand(0); + Value *FV = RHSIntrinsic->getArgOperand(0); + + Value *NewSel = Builder.CreateSelect(SI.getCondition(), TV, FV, "", &SI); + Value *NewCall = Builder.CreateUnaryIntrinsic(IID, NewSel); + + return replaceInstUsesWith(SI, NewCall); + } + default: + return nullptr; + } +} + static bool isSelect01(const APInt &C1I, const APInt &C2I) { if (!C1I.isZero() && !C2I.isZero()) // One side must be zero. return false; @@ -1147,39 +1192,48 @@ static Value *canonicalizeSaturatedAddSigned(ICmpInst *Cmp, Value *TVal, Value *Cmp0 = Cmp->getOperand(0); Value *Cmp1 = Cmp->getOperand(1); ICmpInst::Predicate Pred = Cmp->getPredicate(); - Value *X; - const APInt *C; - // Canonicalize INT_MAX to true value of the select. - if (match(FVal, m_MaxSignedValue())) { + // Canonicalize TVal to be the saturation constant. + if (match(FVal, m_MaxSignedValue()) || match(FVal, m_SignMask())) { std::swap(TVal, FVal); Pred = CmpInst::getInversePredicate(Pred); } - if (!match(TVal, m_MaxSignedValue())) + const APInt *SatC; + if (!match(TVal, m_APInt(SatC)) || + !(SatC->isMaxSignedValue() || SatC->isSignMask())) return nullptr; + bool IsMax = SatC->isMaxSignedValue(); + // sge maximum signed value is canonicalized to eq maximum signed value and - // requires special handling (a == INT_MAX) ? INT_MAX : a + 1 -> sadd.sat(a, - // 1) - if (Pred == ICmpInst::ICMP_EQ) { - if (match(FVal, m_Add(m_Specific(Cmp0), m_One())) && Cmp1 == TVal) { + // requires special handling. sle minimum signed value is similarly + // canonicalized to eq minimum signed value. + if (Pred == ICmpInst::ICMP_EQ && Cmp1 == TVal) { + // (a == INT_MAX) ? INT_MAX : a + 1 -> sadd.sat(a, 1) + if (IsMax && match(FVal, m_Add(m_Specific(Cmp0), m_One()))) { return Builder.CreateBinaryIntrinsic( Intrinsic::sadd_sat, Cmp0, ConstantInt::get(Cmp0->getType(), 1)); } + + // (a == INT_MIN) ? INT_MIN : a + -1 -> sadd.sat(a, -1) + if (!IsMax && match(FVal, m_Add(m_Specific(Cmp0), m_AllOnes()))) { + return Builder.CreateBinaryIntrinsic( + Intrinsic::sadd_sat, Cmp0, + ConstantInt::getAllOnesValue(Cmp0->getType())); + } return nullptr; } + const APInt *C; + // (X > Y) ? INT_MAX : (X + C) --> sadd.sat(X, C) // (X >= Y) ? INT_MAX : (X + C) --> sadd.sat(X, C) - // where Y is INT_MAX - C or INT_MAX - C - 1, and C > 0 - if ((Pred == ICmpInst::ICMP_SGT || Pred == ICmpInst::ICMP_SGE) && + // where C > 0 and Y is INT_MAX - C or INT_MAX - C - 1 + if (IsMax && (Pred == ICmpInst::ICMP_SGT || Pred == ICmpInst::ICMP_SGE) && isa(Cmp1) && match(FVal, m_Add(m_Specific(Cmp0), m_StrictlyPositive(C)))) { - APInt IntMax = - APInt::getSignedMaxValue(Cmp1->getType()->getScalarSizeInBits()); - - // For SGE, try to flip to SGT to normalize the comparison constant. + // Normalize SGE to SGT for threshold comparison. if (Pred == ICmpInst::ICMP_SGE) { if (auto Flipped = getFlippedStrictnessPredicateAndConstant( Pred, cast(Cmp1))) { @@ -1187,11 +1241,35 @@ static Value *canonicalizeSaturatedAddSigned(ICmpInst *Cmp, Value *TVal, Cmp1 = Flipped->second; } } - - // Check the pattern: X > INT_MAX - C or X > INT_MAX - C - 1 + // Check: X > INT_MAX - C or X > INT_MAX - C - 1 + APInt Threshold = *SatC - *C; if (Pred == ICmpInst::ICMP_SGT && - (match(Cmp1, m_SpecificIntAllowPoison(IntMax - *C)) || - match(Cmp1, m_SpecificIntAllowPoison(IntMax - *C - 1)))) + (match(Cmp1, m_SpecificIntAllowPoison(Threshold)) || + match(Cmp1, m_SpecificIntAllowPoison(Threshold - 1)))) + return Builder.CreateBinaryIntrinsic( + Intrinsic::sadd_sat, Cmp0, ConstantInt::get(Cmp0->getType(), *C)); + } + + // (X < Y) ? INT_MIN : (X + C) --> sadd.sat(X, C) + // (X <= Y) ? INT_MIN : (X + C) --> sadd.sat(X, C) + // where C < 0 and Y is INT_MIN - C or INT_MIN - C + 1 + if (!IsMax && (Pred == ICmpInst::ICMP_SLT || Pred == ICmpInst::ICMP_SLE) && + isa(Cmp1) && + match(FVal, m_Add(m_Specific(Cmp0), m_Negative(C)))) { + // Normalize SLE to SLT for threshold comparison. + if (Pred == ICmpInst::ICMP_SLE) { + if (auto Flipped = getFlippedStrictnessPredicateAndConstant( + Pred, cast(Cmp1))) { + Pred = Flipped->first; + Cmp1 = Flipped->second; + } + } + // Check: X < INT_MIN - C or X < INT_MIN - C + 1 + // INT_MIN - C for negative C is like INT_MIN + |C| + APInt Threshold = *SatC - *C; + if (Pred == ICmpInst::ICMP_SLT && + (match(Cmp1, m_SpecificIntAllowPoison(Threshold)) || + match(Cmp1, m_SpecificIntAllowPoison(Threshold + 1)))) return Builder.CreateBinaryIntrinsic( Intrinsic::sadd_sat, Cmp0, ConstantInt::get(Cmp0->getType(), *C)); } @@ -1205,13 +1283,24 @@ static Value *canonicalizeSaturatedAddSigned(ICmpInst *Cmp, Value *TVal, if (Pred != ICmpInst::ICMP_SLT && Pred != ICmpInst::ICMP_SLE) return nullptr; - if (match(Cmp0, m_NSWSub(m_MaxSignedValue(), m_Value(X))) && + Value *X; + + // (INT_MAX - X s< Y) ? INT_MAX : (X + Y) --> sadd.sat(X, Y) + // (INT_MAX - X s< Y) ? INT_MAX : (Y + X) --> sadd.sat(X, Y) + if (IsMax && match(Cmp0, m_NSWSub(m_SpecificInt(*SatC), m_Value(X))) && match(FVal, m_c_Add(m_Specific(X), m_Specific(Cmp1)))) { - // (INT_MAX - X s< Y) ? INT_MAX : (X + Y) --> sadd.sat(X, Y) - // (INT_MAX - X s< Y) ? INT_MAX : (Y + X) --> sadd.sat(X, Y) return Builder.CreateBinaryIntrinsic(Intrinsic::sadd_sat, X, Cmp1); } + // (INT_MIN - X s> Y) ? INT_MIN : (X + Y) --> sadd.sat(X, Y) + // (INT_MIN - X s> Y) ? INT_MIN : (Y + X) --> sadd.sat(X, Y) + // After swapping operands from the SGT/SGE canonicalization above, + // this becomes (Y s< INT_MIN - X). + if (!IsMax && match(Cmp1, m_NSWSub(m_SpecificInt(*SatC), m_Value(X))) && + match(FVal, m_c_Add(m_Specific(X), m_Specific(Cmp0)))) { + return Builder.CreateBinaryIntrinsic(Intrinsic::sadd_sat, X, Cmp0); + } + return nullptr; } @@ -4441,6 +4530,9 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) { if (Instruction *IV = foldSelectOpOp(SI, TI, FI)) return IV; + if (Instruction *I = foldSelectIntrinsic(SI)) + return I; + if (Instruction *I = foldSelectExtConst(SI)) return I; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index f6c3198cd6d5e..c097e74456ff7 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -605,6 +605,12 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Instruction *I, SimplifyDemandedBits(I, 0, DemandedFromLHS, LHSKnown, Q, Depth + 1)) return disableWrapFlagsBasedOnUnusedHighBits(I, NLZ); + unsigned NtzLHS = (~DemandedMask & LHSKnown.Zero).countr_one(); + APInt DemandedFromRHS = DemandedFromOps; + DemandedFromRHS.clearLowBits(NtzLHS); + if (ShrinkDemandedConstant(I, 1, DemandedFromRHS)) + return disableWrapFlagsBasedOnUnusedHighBits(I, NLZ); + // If we are known to be adding zeros to every bit below // the highest demanded bit, we just return the other side. if (DemandedFromOps.isSubsetOf(RHSKnown.Zero)) @@ -2212,8 +2218,10 @@ simplifyDemandedFPClassMinMax(KnownFPClass &Known, Intrinsic::ID IID, break; } + case Intrinsic::maxnum: case Intrinsic::maximumnum: { - OpKind = KnownFPClass::MinMaxKind::maximumnum; + OpKind = IID == Intrinsic::maxnum ? KnownFPClass::MinMaxKind::maxnum + : KnownFPClass::MinMaxKind::maximumnum; if (cannotOrderStrictlyLess(KnownLHS.KnownFPClasses, KnownRHS.KnownFPClasses, OrderedZeroSign) && @@ -2227,8 +2235,10 @@ simplifyDemandedFPClassMinMax(KnownFPClass &Known, Intrinsic::ID IID, break; } + case Intrinsic::minnum: case Intrinsic::minimumnum: { - OpKind = KnownFPClass::MinMaxKind::minimumnum; + OpKind = IID == Intrinsic::minnum ? KnownFPClass::MinMaxKind::minnum + : KnownFPClass::MinMaxKind::minimumnum; if (cannotOrderStrictlyGreater(KnownLHS.KnownFPClasses, KnownRHS.KnownFPClasses, OrderedZeroSign) && @@ -2261,6 +2271,8 @@ simplifyDemandedUseFPClassFPTrunc(InstCombinerImpl &IC, Instruction &I, KnownFPClass &Known, unsigned Depth) { FPClassTest SrcDemandedMask = DemandedMask; + if (DemandedMask & fcNan) + SrcDemandedMask |= fcNan; // Zero results may have been rounded from subnormal or normal sources. if (DemandedMask & fcNegZero) @@ -2366,6 +2378,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, DenormalMode Mode = F.getDenormalMode(EltTy->getFltSemantics()); FPClassTest SrcDemandedMask = DemandedMask; + if (DemandedMask & fcNan) + SrcDemandedMask |= fcNan; // Doubling a subnormal could have resulted in a normal value. if (DemandedMask & fcPosNormal) @@ -2465,7 +2479,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, if (DemandedMask & fcNan) { // mul +/-inf, 0 => nan - SrcDemandedMask |= fcZero | fcInf; + SrcDemandedMask |= fcZero | fcInf | fcNan; // TODO: Mode check // mul +/-inf, sub => nan if daz @@ -2645,7 +2659,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, // Subnormal is added in case of DAZ, but this isn't strictly // necessary. Every other input class implies a possible subnormal source, // so this only could matter in the degenerate case of only-nan results. - SrcDemandedMask |= fcZero | fcInf; + SrcDemandedMask |= fcZero | fcInf | fcNan; } // Zero outputs may be the result of underflow. @@ -2731,6 +2745,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, Known, Depth); case Instruction::FPExt: { FPClassTest SrcDemandedMask = DemandedMask; + if (DemandedMask & fcNan) + SrcDemandedMask |= fcNan; // No subnormal result does not imply not-subnormal in the source type. if ((DemandedMask & fcNegNormal) != fcNone) @@ -2828,7 +2844,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, case Intrinsic::fmuladd: { // We can't do any simplification on the source besides stripping out // unneeded nans. - FPClassTest SrcDemandedMask = (DemandedMask & fcNan) | ~fcNan; + FPClassTest SrcDemandedMask = DemandedMask | ~fcNan; + if (DemandedMask & fcNan) + SrcDemandedMask |= fcNan; KnownFPClass KnownSrc[3]; @@ -2862,7 +2880,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, case Intrinsic::maximum: case Intrinsic::minimum: case Intrinsic::maximumnum: - case Intrinsic::minimumnum: { + case Intrinsic::minimumnum: + case Intrinsic::maxnum: + case Intrinsic::minnum: { const bool PropagateNaN = IID == Intrinsic::maximum || IID == Intrinsic::minimum; @@ -2870,7 +2890,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, // operands (e.g., a known-positive result could have been clamped), but // we can still prune known-nan inputs. FPClassTest SrcDemandedMask = - PropagateNaN ? DemandedMask | ~fcNan : fcAllFlags; + PropagateNaN && ((DemandedMask & fcNan) == fcNone) + ? DemandedMask | ~fcNan + : fcAllFlags; KnownFPClass KnownLHS, KnownRHS; if (SimplifyDemandedFPClass(CI, 1, SrcDemandedMask, KnownRHS, @@ -2937,6 +2959,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, } FPClassTest SrcDemandedMask = DemandedMask & fcNan; + if (DemandedMask & fcNan) + SrcDemandedMask |= fcNan; if (DemandedMask & fcZero) { // exp(-infinity) = 0 @@ -3022,6 +3046,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, case Intrinsic::log2: case Intrinsic::log10: { FPClassTest DemandedSrcMask = DemandedMask & (fcNan | fcPosInf); + if (DemandedMask & fcNan) + DemandedSrcMask |= fcNan; Type *EltTy = VTy->getScalarType(); DenormalMode Mode = F.getDenormalMode(EltTy->getFltSemantics()); @@ -3061,7 +3087,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, DemandedMask & (fcNegZero | fcPositive | fcNan); if (DemandedMask & fcNan) - DemandedSrcMask |= (fcNegative & ~fcNegZero); + DemandedSrcMask |= fcNan | (fcNegative & ~fcNegZero); // sqrt(max_subnormal) is a normal value if (DemandedMask & fcPosNormal) @@ -3111,6 +3137,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseFPClass(Instruction *I, case Intrinsic::round: case Intrinsic::roundeven: { FPClassTest DemandedSrcMask = DemandedMask; + if (DemandedMask & fcNan) + DemandedSrcMask |= fcNan; // Zero results imply valid subnormal sources. if (DemandedMask & fcNegZero) @@ -3464,6 +3492,8 @@ Value *InstCombinerImpl::SimplifyMultipleUseDemandedFPClass( Known = KnownFPClass::copysign(KnownMag, KnownSign); break; } + case Intrinsic::maxnum: + case Intrinsic::minnum: case Intrinsic::maximum: case Intrinsic::minimum: case Intrinsic::maximumnum: @@ -3476,9 +3506,10 @@ Value *InstCombinerImpl::SimplifyMultipleUseDemandedFPClass( KnownFPClass KnownLHS = computeKnownFPClass( CI->getArgOperand(0), DemandedMask, CxtI, Depth + 1); - return simplifyDemandedFPClassMinMax( - Known, IID, CI, DemandedMask, KnownLHS, KnownRHS, F, - cast(CI)->hasNoSignedZeros()); + // Cannot use NSZ in the multiple use case. + return simplifyDemandedFPClassMinMax(Known, IID, CI, DemandedMask, + KnownLHS, KnownRHS, F, + /*NSZ=*/false); } default: break; diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index a9904f7867e94..fd699381c22fa 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -2392,6 +2392,48 @@ static Constant *constantFoldBinOpWithSplat(unsigned Opcode, Constant *Vector, return ConstantFoldBinaryOpOperands(Opcode, LHS, RHS, DL); } +template +static Instruction *foldSpliceBinOp(BinaryOperator &Inst, + InstCombiner::BuilderTy &Builder) { + Value *LHS = Inst.getOperand(0), *RHS = Inst.getOperand(1); + auto CreateBinOpSplice = [&](Value *X, Value *Y, Value *Offset) { + Value *V = Builder.CreateBinOp(Inst.getOpcode(), X, Y, Inst.getName()); + if (auto *BO = dyn_cast(V)) + BO->copyIRFlags(&Inst); + Module *M = Inst.getModule(); + Function *F = Intrinsic::getOrInsertDeclaration(M, SpliceID, V->getType()); + return CallInst::Create(F, {V, PoisonValue::get(V->getType()), Offset}); + }; + Value *V1, *V2, *Offset; + if (match(LHS, + m_Intrinsic(m_Value(V1), m_Poison(), m_Value(Offset)))) { + // Op(splice(V1, poison, offset), splice(V2, poison, offset)) + // -> splice(Op(V1, V2), poison, offset) + if (match(RHS, m_Intrinsic(m_Value(V2), m_Poison(), + m_Specific(Offset))) && + (LHS->hasOneUse() || RHS->hasOneUse() || + (LHS == RHS && LHS->hasNUses(2)))) + return CreateBinOpSplice(V1, V2, Offset); + + // Op(splice(V1, poison, offset), RHSSplat) + // -> splice(Op(V1, RHSSplat), poison, offset) + if (LHS->hasOneUse() && isSplatValue(RHS)) + return CreateBinOpSplice(V1, RHS, Offset); + } + // Op(LHSSplat, splice(V2, poison, offset)) + // -> splice(Op(LHSSplat, V2), poison, offset) + else if (isSplatValue(LHS) && + match(RHS, m_OneUse(m_Intrinsic(m_Value(V2), m_Poison(), + m_Value(Offset))))) + return CreateBinOpSplice(LHS, V2, Offset); + + // TODO: Fold binops of the form + // Op(splice(poison, V1, offset), splice(poison, V2, offset)) + // -> splice(poison, Op(V1, V2), offset) + + return nullptr; +} + Instruction *InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) { if (!isa(Inst.getType())) return nullptr; @@ -2520,6 +2562,13 @@ Instruction *InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) { m_Value(V2), m_AllOnes(), m_Value(EVL)))) return createBinOpVPReverse(LHS, V2, EVL); + if (Instruction *Folded = + foldSpliceBinOp(Inst, Builder)) + return Folded; + if (Instruction *Folded = + foldSpliceBinOp(Inst, Builder)) + return Folded; + // It may not be safe to reorder shuffles and things like div, urem, etc. // because we may trap when executing those ops on unknown vector elements. // See PR20059. @@ -3622,6 +3671,25 @@ Instruction *InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) { if (Instruction *R = foldSelectGEP(GEP, Builder)) return R; + // srem -> (and/urem) for inbounds+nuw GEP + if (Indices.size() == 1 && GEP.isInBounds() && GEP.hasNoUnsignedWrap()) { + Value *X, *Y; + + // Match: idx = srem X, Y -- where Y is a power-of-two value. + if (match(Indices[0], m_OneUse(m_SRem(m_Value(X), m_Value(Y)))) && + isKnownToBeAPowerOfTwo(Y, /*OrZero=*/true, &GEP)) { + // If GEP is inbounds+nuw, the offset cannot be negative + // -> srem by power-of-two can be treated as urem, + // and urem by power-of-two folds to 'and' later. + // OrZero=true is fine here because division by zero is UB. + Instruction *OldIdxI = cast(Indices[0]); + Value *NewIdx = Builder.CreateURem(X, Y, OldIdxI->getName()); + + return GetElementPtrInst::Create(GEPEltType, PtrOp, {NewIdx}, + GEP.getNoWrapFlags()); + } + } + return nullptr; } @@ -6262,9 +6330,7 @@ bool InstructionCombiningPass::runOnFunction(Function &F) { char InstructionCombiningPass::ID = 0; -InstructionCombiningPass::InstructionCombiningPass() : FunctionPass(ID) { - initializeInstructionCombiningPassPass(*PassRegistry::getPassRegistry()); -} +InstructionCombiningPass::InstructionCombiningPass() : FunctionPass(ID) {} INITIALIZE_PASS_BEGIN(InstructionCombiningPass, "instcombine", "Combine redundant instructions", false, false) @@ -6280,7 +6346,7 @@ INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass) INITIALIZE_PASS_END(InstructionCombiningPass, "instcombine", "Combine redundant instructions", false, false) -// Initialization Routines +// Initialization Routines. void llvm::initializeInstCombine(PassRegistry &Registry) { initializeInstructionCombiningPassPass(Registry); } diff --git a/llvm/lib/Transforms/Instrumentation/MemProfUse.cpp b/llvm/lib/Transforms/Instrumentation/MemProfUse.cpp index 72d2c4d1239eb..2717a1e271850 100644 --- a/llvm/lib/Transforms/Instrumentation/MemProfUse.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemProfUse.cpp @@ -45,6 +45,7 @@ namespace llvm { extern cl::opt PGOWarnMissing; extern cl::opt NoPGOWarnMismatch; extern cl::opt NoPGOWarnMismatchComdatWeak; +extern cl::opt AnnotateStringLiteralSectionPrefix; } // namespace llvm // By default disable matching of allocation profiles onto operator new that @@ -92,14 +93,6 @@ static cl::opt AnnotateStaticDataSectionPrefix( "memprof-annotate-static-data-prefix", cl::init(false), cl::Hidden, cl::desc("If true, annotate the static data section prefix")); -// FIXME: This option is added for incremental rollout purposes. -// After the option, string literal partitioning should be implied by -// AnnotateStaticDataSectionPrefix above and this option should be cleaned up. -static cl::opt AnnotateStringLiteralSectionPrefix( - "memprof-annotate-string-literal-section-prefix", cl::init(false), - cl::Hidden, - cl::desc("If true, annotate the string literal data section prefix")); - // Matching statistics STATISTIC(NumOfMemProfMissing, "Number of functions without memory profile."); STATISTIC(NumOfMemProfMismatch, diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 412f6ba18fc77..3e7eafd756e89 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -2422,6 +2422,85 @@ struct MemorySanitizerVisitor : public InstVisitor { I.setSuccessOrdering(addReleaseOrdering(I.getSuccessOrdering())); } + /// Generic handler to compute shadow for == and != comparisons. + /// + /// This function is used by handleEqualityComparison and visitSwitchInst. + /// + /// Sometimes the comparison result is known even if some of the bits of the + /// arguments are not. + Value *propagateEqualityComparison(IRBuilder<> &IRB, Value *A, Value *B, + Value *Sa, Value *Sb) { + assert(getShadowTy(A) == Sa->getType()); + assert(getShadowTy(B) == Sb->getType()); + + // Get rid of pointers and vectors of pointers. + // For ints (and vectors of ints), types of A and Sa match, + // and this is a no-op. + A = IRB.CreatePointerCast(A, Sa->getType()); + B = IRB.CreatePointerCast(B, Sb->getType()); + + // A == B <==> (C = A^B) == 0 + // A != B <==> (C = A^B) != 0 + // Sc = Sa | Sb + Value *C = IRB.CreateXor(A, B); + Value *Sc = IRB.CreateOr(Sa, Sb); + // Now dealing with i = (C == 0) comparison (or C != 0, does not matter now) + // Result is defined if one of the following is true + // * there is a defined 1 bit in C + // * C is fully defined + // Si = !(C & ~Sc) && Sc + Value *Zero = Constant::getNullValue(Sc->getType()); + Value *MinusOne = Constant::getAllOnesValue(Sc->getType()); + Value *LHS = IRB.CreateICmpNE(Sc, Zero); + Value *RHS = + IRB.CreateICmpEQ(IRB.CreateAnd(IRB.CreateXor(Sc, MinusOne), C), Zero); + Value *Si = IRB.CreateAnd(LHS, RHS); + Si->setName("_msprop_icmp"); + + return Si; + } + + // Instrument: + // switch i32 %Val, label %else [ i32 0, label %A + // i32 1, label %B + // i32 2, label %C ] + // + // Typically, the switch input value (%Val) is fully initialized. + // + // Sometimes the compiler may convert (icmp + br) into a switch statement. + // MSan allows icmp eq/ne with partly initialized inputs to still result in a + // fully initialized output, if there exists a bit that is initialized in + // both inputs with a differing value. For compatibility, we support this in + // the switch instrumentation as well. Note that this edge case only applies + // if the switch input value does not match *any* of the cases (matching any + // of the cases requires an exact, fully initialized match). + // + // ShadowCases = 0 + // | propagateEqualityComparison(Val, 0) + // | propagateEqualityComparison(Val, 1) + // | propagateEqualityComparison(Val, 2)) + void visitSwitchInst(SwitchInst &SI) { + IRBuilder<> IRB(&SI); + + Value *Val = SI.getCondition(); + Value *ShadowVal = getShadow(Val); + + Value *ShadowCases = nullptr; + for (auto Case : SI.cases()) { + Value *Comparator = Case.getCaseValue(); + Value *ComparisonShadow = propagateEqualityComparison( + IRB, Val, Comparator, ShadowVal, getShadow(Comparator)); + + if (ShadowCases) + ShadowCases = IRB.CreateOr(ShadowCases, ComparisonShadow); + else + ShadowCases = ComparisonShadow; + } + + if (ShadowCases) + insertCheckShadow(ShadowCases, getOrigin(Val), &SI); + } + // Vector manipulation. void visitExtractElementInst(ExtractElementInst &I) { insertCheckShadowOf(I.getOperand(1), &I); @@ -2992,29 +3071,8 @@ struct MemorySanitizerVisitor : public InstVisitor { Value *Sa = getShadow(A); Value *Sb = getShadow(B); - // Get rid of pointers and vectors of pointers. - // For ints (and vectors of ints), types of A and Sa match, - // and this is a no-op. - A = IRB.CreatePointerCast(A, Sa->getType()); - B = IRB.CreatePointerCast(B, Sb->getType()); + Value *Si = propagateEqualityComparison(IRB, A, B, Sa, Sb); - // A == B <==> (C = A^B) == 0 - // A != B <==> (C = A^B) != 0 - // Sc = Sa | Sb - Value *C = IRB.CreateXor(A, B); - Value *Sc = IRB.CreateOr(Sa, Sb); - // Now dealing with i = (C == 0) comparison (or C != 0, does not matter now) - // Result is defined if one of the following is true - // * there is a defined 1 bit in C - // * C is fully defined - // Si = !(C & ~Sc) && Sc - Value *Zero = Constant::getNullValue(Sc->getType()); - Value *MinusOne = Constant::getAllOnesValue(Sc->getType()); - Value *LHS = IRB.CreateICmpNE(Sc, Zero); - Value *RHS = - IRB.CreateICmpEQ(IRB.CreateAnd(IRB.CreateXor(Sc, MinusOne), C), Zero); - Value *Si = IRB.CreateAnd(LHS, RHS); - Si->setName("_msprop_icmp"); setShadow(&I, Si); setOriginForNaryOp(I); } @@ -4117,6 +4175,9 @@ struct MemorySanitizerVisitor : public InstVisitor { // (<2 x float> %A, <2 x float>) // - <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32 // (<2 x float> %A, <2 x float>) + // + // Bonus: this also handles scalar cases e.g., + // - i32 @llvm.aarch64.neon.facgt.i32.f32(float %A, float %B) void handleVectorComparePackedIntrinsic(IntrinsicInst &I, bool PredicateAsOperand) { if (PredicateAsOperand) { @@ -5036,7 +5097,7 @@ struct MemorySanitizerVisitor : public InstVisitor { setOriginForNaryOp(I); } - // Handle llvm.x86.avx512.* instructions that take a vector of floating-point + // Handle llvm.x86.avx512.* instructions that take vector(s) of floating-point // values and perform an operation whose shadow propagation should be handled // as all-or-nothing [*], with masking provided by a vector and a mask // supplied as an integer. @@ -5050,44 +5111,63 @@ struct MemorySanitizerVisitor : public InstVisitor { // // <2 x double> @llvm.x86.avx512.rcp14.pd.128 // (<2 x double>, <2 x double>, i8) + // A WriteThru Mask // // <8 x double> @llvm.x86.avx512.mask.rndscale.pd.512 // (<8 x double>, i32, <8 x double>, i8, i32) // A Imm WriteThru Mask Rounding // - // All operands other than A and WriteThru (e.g., Mask, Imm, Rounding) must - // be fully initialized. + // <16 x float> @llvm.x86.avx512.mask.scalef.ps.512 + // (<16 x float>, <16 x float>, <16 x float>, i16, i32) + // WriteThru A B Mask Rnd + // + // All operands other than A, B, ..., and WriteThru (e.g., Mask, Imm, + // Rounding) must be fully initialized. // - // Dst[i] = Mask[i] ? some_op(A[i]) : WriteThru[i] - // Dst_shadow[i] = Mask[i] ? all_or_nothing(A_shadow[i]) : WriteThru_shadow[i] - void handleAVX512VectorGenericMaskedFP(IntrinsicInst &I, unsigned AIndex, + // Dst[i] = Mask[i] ? some_op(A[i], B[i], ...) + // : WriteThru[i] + // Dst_shadow[i] = Mask[i] ? all_or_nothing(A_shadow[i] | B_shadow[i] | ...) + // : WriteThru_shadow[i] + void handleAVX512VectorGenericMaskedFP(IntrinsicInst &I, + SmallVector DataIndices, unsigned WriteThruIndex, unsigned MaskIndex) { IRBuilder<> IRB(&I); unsigned NumArgs = I.arg_size(); - assert(AIndex < NumArgs); + assert(WriteThruIndex < NumArgs); assert(MaskIndex < NumArgs); - assert(AIndex != WriteThruIndex); - assert(AIndex != MaskIndex); assert(WriteThruIndex != MaskIndex); - - Value *A = I.getOperand(AIndex); Value *WriteThru = I.getOperand(WriteThruIndex); - Value *Mask = I.getOperand(MaskIndex); - - assert(isFixedFPVector(A)); - assert(isFixedFPVector(WriteThru)); - [[maybe_unused]] unsigned ANumElements = - cast(A->getType())->getNumElements(); unsigned OutputNumElements = cast(WriteThru->getType())->getNumElements(); - assert(ANumElements == OutputNumElements); + + assert(DataIndices.size() > 0); + + bool isData[16] = {false}; + assert(NumArgs <= 16); + for (unsigned i : DataIndices) { + assert(i < NumArgs); + assert(i != WriteThruIndex); + assert(i != MaskIndex); + + isData[i] = true; + + Value *A = I.getOperand(i); + assert(isFixedFPVector(A)); + [[maybe_unused]] unsigned ANumElements = + cast(A->getType())->getNumElements(); + assert(ANumElements == OutputNumElements); + } + + Value *Mask = I.getOperand(MaskIndex); + + assert(isFixedFPVector(WriteThru)); for (unsigned i = 0; i < NumArgs; ++i) { - if (i != AIndex && i != WriteThruIndex) { + if (!isData[i] && i != WriteThruIndex) { // Imm, Mask, Rounding etc. are "control" data, hence we require that // they be fully initialized. assert(I.getOperand(i)->getType()->isIntegerTy()); @@ -5096,24 +5176,32 @@ struct MemorySanitizerVisitor : public InstVisitor { } // The mask has 1 bit per element of A, but a minimum of 8 bits. - if (Mask->getType()->getScalarSizeInBits() == 8 && ANumElements < 8) - Mask = IRB.CreateTrunc(Mask, Type::getIntNTy(*MS.C, ANumElements)); - assert(Mask->getType()->getScalarSizeInBits() == ANumElements); + if (Mask->getType()->getScalarSizeInBits() == 8 && OutputNumElements < 8) + Mask = IRB.CreateTrunc(Mask, Type::getIntNTy(*MS.C, OutputNumElements)); + assert(Mask->getType()->getScalarSizeInBits() == OutputNumElements); assert(I.getType() == WriteThru->getType()); Mask = IRB.CreateBitCast( Mask, FixedVectorType::get(IRB.getInt1Ty(), OutputNumElements)); - Value *AShadow = getShadow(A); + Value *DataShadow = nullptr; + for (unsigned i : DataIndices) { + Value *A = I.getOperand(i); + if (DataShadow) + DataShadow = IRB.CreateOr(DataShadow, getShadow(A)); + else + DataShadow = getShadow(A); + } // All-or-nothing shadow - AShadow = IRB.CreateSExt(IRB.CreateICmpNE(AShadow, getCleanShadow(AShadow)), - AShadow->getType()); + DataShadow = + IRB.CreateSExt(IRB.CreateICmpNE(DataShadow, getCleanShadow(DataShadow)), + DataShadow->getType()); Value *WriteThruShadow = getShadow(WriteThru); - Value *Shadow = IRB.CreateSelect(Mask, AShadow, WriteThruShadow); + Value *Shadow = IRB.CreateSelect(Mask, DataShadow, WriteThruShadow); setShadow(&I, Shadow); setOriginForNaryOp(I); @@ -5413,16 +5501,27 @@ struct MemorySanitizerVisitor : public InstVisitor { } } - // <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8 - // (<4 x i32> %R, <16 x i8> %X, <16 x i8> %Y) - // <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8 - // (<4 x i32> %R, <16 x i8> %X, <16 x i8> %Y) - // <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8 - // (<4 x i32> R%, <16 x i8> %X, <16 x i8> %Y) + // Integer matrix multiplication: + // - <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8 + // (<4 x i32> %R, <16 x i8> %X, <16 x i8> %Y) + // - <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8 + // (<4 x i32> %R, <16 x i8> %X, <16 x i8> %Y) + // - <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8 + // (<4 x i32> %R, <16 x i8> %X, <16 x i8> %Y) // // Note: - // - < 4 x *> is a 2x2 matrix - // - <16 x *> is a 2x8 matrix and 8x2 matrix respectively + // - <4 x i32> is a 2x2 matrix + // - <16 x i8> %X and %Y are 2x8 and 8x2 matrices respectively + // + // 2x8 %X 8x2 %Y + // [ X01 X02 X03 X04 X05 X06 X07 X08 ] [ Y01 Y09 ] + // [ X09 X10 X11 X12 X13 X14 X15 X16 ] x [ Y02 Y10 ] + // [ Y03 Y11 ] + // [ Y04 Y12 ] + // [ Y05 Y13 ] + // [ Y06 Y14 ] + // [ Y07 Y15 ] + // [ Y08 Y16 ] // // The general shadow propagation approach is: // 1) get the shadows of the input matrices %X and %Y @@ -5436,14 +5535,30 @@ struct MemorySanitizerVisitor : public InstVisitor { // TODO: consider allowing multiplication of zero with an uninitialized value // to result in an initialized value. // - // TODO: handle floating-point matrix multiply using ummla on the shadows: - // case Intrinsic::aarch64_neon_bfmmla: - // handleNEONMatrixMultiply(I, /*ARows=*/ 2, /*ACols=*/ 4, - // /*BRows=*/ 4, /*BCols=*/ 2); + // Floating-point matrix multiplication: + // - <4 x float> @llvm.aarch64.neon.bfmmla + // (<4 x float> %R, <8 x bfloat> %X, <8 x bfloat> %Y) + // %X and %Y are 2x4 and 4x2 matrices respectively + // + // Although there are half as many elements of %X and %Y compared to the + // integer case, each element is twice the bit-width. Thus, we can reuse the + // shadow propagation logic if we cast the shadows to the same type as the + // integer case, and apply ummla to the shadows: + // + // 2x4 %X 4x2 %Y + // [ A01:A02 A03:A04 A05:A06 A07:A08 ] [ B01:B02 B09:B10 ] + // [ A09:A10 A11:A12 A13:A14 A15:A16 ] x [ B03:B04 B11:B12 ] + // [ B05:B06 B13:B14 ] + // [ B07:B08 B15:B16 ] // - void handleNEONMatrixMultiply(IntrinsicInst &I, unsigned int ARows, - unsigned int ACols, unsigned int BRows, - unsigned int BCols) { + // For example, consider multiplying the first row of %X with the first + // column of Y. We want to know if + // A01:A02*B01:B02 + A03:A04*B03:B04 + A05:A06*B06:B06 + A07:A08*B07:B08 is + // fully initialized, which will be true if and only if (A01, A02, ..., A08) + // and (B01, B02, ..., B08) are each fully initialized. This latter condition + // is equivalent to what is tested by the instrumentation for the integer + // form. + void handleNEONMatrixMultiply(IntrinsicInst &I) { IRBuilder<> IRB(&I); assert(I.arg_size() == 3); @@ -5461,47 +5576,70 @@ struct MemorySanitizerVisitor : public InstVisitor { [[maybe_unused]] FixedVectorType *ATy = cast(A->getType()); [[maybe_unused]] FixedVectorType *BTy = cast(B->getType()); - assert(ACols == BRows); - assert(ATy->getNumElements() == ARows * ACols); - assert(BTy->getNumElements() == BRows * BCols); - assert(RTy->getNumElements() == ARows * BCols); + Value *ShadowR = getShadow(&I, 0); + Value *ShadowA = getShadow(&I, 1); + Value *ShadowB = getShadow(&I, 2); + + // We will use ummla to compute the shadow. These are the types it expects. + // These are also the types of the corresponding shadows. + FixedVectorType *ExpectedRTy = + FixedVectorType::get(IntegerType::get(*MS.C, 32), 4); + FixedVectorType *ExpectedATy = + FixedVectorType::get(IntegerType::get(*MS.C, 8), 16); + FixedVectorType *ExpectedBTy = + FixedVectorType::get(IntegerType::get(*MS.C, 8), 16); - LLVM_DEBUG(dbgs() << "### R: " << *RTy->getElementType() << "\n"); - LLVM_DEBUG(dbgs() << "### A: " << *ATy->getElementType() << "\n"); if (RTy->getElementType()->isIntegerTy()) { - // Types are not identical e.g., <4 x i32> %R, <16 x i8> %A + // Types of R and A/B are not identical e.g., <4 x i32> %R, <16 x i8> %A assert(ATy->getElementType()->isIntegerTy()); + + assert(RTy == ExpectedRTy); + assert(ATy == ExpectedATy); + assert(BTy == ExpectedBTy); } else { - assert(RTy->getElementType()->isFloatingPointTy()); assert(ATy->getElementType()->isFloatingPointTy()); + assert(BTy->getElementType()->isFloatingPointTy()); + + // Technically, what we care about is that: + // getShadowTy(RTy)->canLosslesslyBitCastTo(ExpectedRTy)) etc. + // but that is equivalent. + assert(RTy->canLosslesslyBitCastTo(ExpectedRTy)); + assert(ATy->canLosslesslyBitCastTo(ExpectedATy)); + assert(BTy->canLosslesslyBitCastTo(ExpectedBTy)); + + ShadowA = IRB.CreateBitCast(ShadowA, getShadowTy(ExpectedATy)); + ShadowB = IRB.CreateBitCast(ShadowB, getShadowTy(ExpectedBTy)); } assert(ATy->getElementType() == BTy->getElementType()); - Value *ShadowR = getShadow(&I, 0); - Value *ShadowA = getShadow(&I, 1); - Value *ShadowB = getShadow(&I, 2); + // From this point on, use Expected{R,A,B}Type. // If the value is fully initialized, the shadow will be 000...001. // Otherwise, the shadow will be all zero. // (This is the opposite of how we typically handle shadows.) - ShadowA = IRB.CreateZExt(IRB.CreateICmpEQ(ShadowA, getCleanShadow(A)), - ShadowA->getType()); - ShadowB = IRB.CreateZExt(IRB.CreateICmpEQ(ShadowB, getCleanShadow(B)), - ShadowB->getType()); - - Value *ShadowAB = IRB.CreateIntrinsic( - I.getType(), I.getIntrinsicID(), {getCleanShadow(R), ShadowA, ShadowB}); - + ShadowA = + IRB.CreateZExt(IRB.CreateICmpEQ(ShadowA, getCleanShadow(ExpectedATy)), + getShadowTy(ExpectedATy)); + ShadowB = + IRB.CreateZExt(IRB.CreateICmpEQ(ShadowB, getCleanShadow(ExpectedBTy)), + getShadowTy(ExpectedBTy)); + + Value *ShadowAB = + IRB.CreateIntrinsic(ExpectedRTy, Intrinsic::aarch64_neon_ummla, + {getCleanShadow(ExpectedRTy), ShadowA, ShadowB}); + + // ummla multiplies a 2x8 matrix with an 8x2 matrix. If all entries of the + // input matrices are equal to 0x1, all entries of the output matrix will + // be 0x8. Value *FullyInit = ConstantVector::getSplat( - RTy->getElementCount(), - ConstantInt::get(cast(getShadowTy(R))->getElementType(), - ACols)); + ExpectedRTy->getElementCount(), + ConstantInt::get(ExpectedRTy->getElementType(), 0x8)); ShadowAB = IRB.CreateSExt(IRB.CreateICmpNE(ShadowAB, FullyInit), ShadowAB->getType()); - ShadowR = IRB.CreateSExt(IRB.CreateICmpNE(ShadowR, getCleanShadow(R)), - ShadowR->getType()); + ShadowR = IRB.CreateSExt( + IRB.CreateICmpNE(ShadowR, getCleanShadow(ExpectedRTy)), ExpectedRTy); setShadow(&I, IRB.CreateOr(ShadowAB, ShadowR)); setOriginForNaryOp(I); @@ -6607,7 +6745,8 @@ struct MemorySanitizerVisitor : public InstVisitor { case Intrinsic::x86_avx512fp16_mask_rsqrt_ph_512: case Intrinsic::x86_avx512fp16_mask_rsqrt_ph_256: case Intrinsic::x86_avx512fp16_mask_rsqrt_ph_128: - handleAVX512VectorGenericMaskedFP(I, /*AIndex=*/0, /*WriteThruIndex=*/1, + handleAVX512VectorGenericMaskedFP(I, /*DataIndices=*/{0}, + /*WriteThruIndex=*/1, /*MaskIndex=*/2); break; @@ -6659,7 +6798,8 @@ struct MemorySanitizerVisitor : public InstVisitor { case Intrinsic::x86_avx512fp16_mask_rcp_ph_512: case Intrinsic::x86_avx512fp16_mask_rcp_ph_256: case Intrinsic::x86_avx512fp16_mask_rcp_ph_128: - handleAVX512VectorGenericMaskedFP(I, /*AIndex=*/0, /*WriteThruIndex=*/1, + handleAVX512VectorGenericMaskedFP(I, /*DataIndices=*/{0}, + /*WriteThruIndex=*/1, /*MaskIndex=*/2); break; @@ -6715,7 +6855,8 @@ struct MemorySanitizerVisitor : public InstVisitor { case Intrinsic::x86_avx10_mask_rndscale_bf16_512: case Intrinsic::x86_avx10_mask_rndscale_bf16_256: case Intrinsic::x86_avx10_mask_rndscale_bf16_128: - handleAVX512VectorGenericMaskedFP(I, /*AIndex=*/0, /*WriteThruIndex=*/2, + handleAVX512VectorGenericMaskedFP(I, /*DataIndices=*/{0}, + /*WriteThruIndex=*/2, /*MaskIndex=*/3); break; @@ -6950,8 +7091,8 @@ struct MemorySanitizerVisitor : public InstVisitor { case Intrinsic::aarch64_neon_smmla: case Intrinsic::aarch64_neon_ummla: case Intrinsic::aarch64_neon_usmmla: - handleNEONMatrixMultiply(I, /*ARows=*/2, /*ACols=*/8, /*BRows=*/8, - /*BCols=*/2); + case Intrinsic::aarch64_neon_bfmmla: + handleNEONMatrixMultiply(I); break; // <2 x i32> @llvm.aarch64.neon.{u,s,us}dot.v2i32.v8i8 @@ -6978,6 +7119,12 @@ struct MemorySanitizerVisitor : public InstVisitor { /*Lanes=*/kBothLanes); break; + // Floating-Point Absolute Compare Greater Than/Equal + case Intrinsic::aarch64_neon_facge: + case Intrinsic::aarch64_neon_facgt: + handleVectorComparePackedIntrinsic(I, /*PredicateAsOperand=*/false); + break; + default: return false; } @@ -7493,11 +7640,51 @@ struct MemorySanitizerVisitor : public InstVisitor { } void dumpInst(Instruction &I) { + // Instruction name only + // For intrinsics, the full/overloaded name is used + // + // e.g., "call llvm.aarch64.neon.uqsub.v16i8" if (CallInst *CI = dyn_cast(&I)) { errs() << "ZZZ call " << CI->getCalledFunction()->getName() << "\n"; } else { errs() << "ZZZ " << I.getOpcodeName() << "\n"; } + + // Instruction prototype (including return type and parameter types) + // For intrinsics, we use the base/non-overloaded name + // + // e.g., "call <16 x i8> @llvm.aarch64.neon.uqsub(<16 x i8>, <16 x i8>)" + unsigned NumOperands = I.getNumOperands(); + if (CallInst *CI = dyn_cast(&I)) { + errs() << "YYY call " << *I.getType() << " @"; + + if (IntrinsicInst *II = dyn_cast(CI)) + errs() << Intrinsic::getBaseName(II->getIntrinsicID()); + else + errs() << CI->getCalledFunction()->getName(); + + errs() << "("; + + // The last operand of a CallInst is the function itself. + NumOperands--; + } else + errs() << "YYY " << *I.getType() << " " << I.getOpcodeName() << "("; + + for (size_t i = 0; i < NumOperands; i++) { + if (i > 0) + errs() << ", "; + + errs() << *(I.getOperand(i)->getType()); + } + + errs() << ")\n"; + + // Full instruction, including types and operand values + // For intrinsics, the full/overloaded name is used + // + // e.g., "%vqsubq_v.i15 = call noundef <16 x i8> + // @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> %vext21.i, + // <16 x i8> splat (i8 1)), !dbg !66" errs() << "QQQ " << I << "\n"; } diff --git a/llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp index 66d570b3f831e..f9ef67923ed48 100644 --- a/llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/NumericalStabilitySanitizer.cpp @@ -2020,7 +2020,6 @@ static void moveFastMathFlags(Function &F, F.removeFnAttr(attr); \ FMF.set##setter(); \ } - MOVE_FLAG("no-infs-fp-math", NoInfs) MOVE_FLAG("no-nans-fp-math", NoNaNs) MOVE_FLAG("no-signed-zeros-fp-math", NoSignedZeros) #undef MOVE_FLAG diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp index 582ec1dbcec98..e056f0c1f6390 100644 --- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp +++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp @@ -1227,7 +1227,11 @@ struct DSEState { int64_t ValueOffset; [[maybe_unused]] const Value *BaseValue = GetPointerBaseWithConstantOffset(Ptr, ValueOffset, DL); - assert(BaseValue == V); + // If we are not able to find a constant offset from the UO, we have to + // pessimistically assume that the store writes to memory out of the + // dead_on_return bounds. + if (BaseValue != V) + return false; // This store is only invisible after return if we are in bounds of the // range marked dead. if (StoreSize.hasValue() && diff --git a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp index 03efc156df1e8..93da510c5fbc0 100644 --- a/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp +++ b/llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp @@ -1102,7 +1102,8 @@ bool InferAddressSpacesImpl::updateAddressSpace( } else { // Otherwise, infer the address space from its pointer operands. SmallVector ConstantPtrOps; - for (Value *PtrOperand : getPointerOperands(V, *DL, TTI)) { + SmallVector PtrOps = getPointerOperands(V, *DL, TTI); + for (Value *PtrOperand : PtrOps) { auto I = InferredAddrSpace.find(PtrOperand); unsigned OperandAS; if (I == InferredAddrSpace.end()) { @@ -1133,12 +1134,18 @@ bool InferAddressSpacesImpl::updateAddressSpace( if (NewAS == FlatAddrSpace) break; } + if (NewAS != FlatAddrSpace && NewAS != UninitializedAddressSpace) { if (any_of(ConstantPtrOps, [=](Constant *C) { return !isSafeToCastConstAddrSpace(C, NewAS); })) NewAS = FlatAddrSpace; } + + // operator(flat const, flat const, ...) -> flat + if (NewAS == UninitializedAddressSpace && + PtrOps.size() == ConstantPtrOps.size()) + NewAS = FlatAddrSpace; } unsigned OldAS = InferredAddrSpace.lookup(&V); diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp index e9d78baece25b..839942fac6716 100644 --- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -6488,7 +6488,8 @@ struct SCEVDbgValueBuilder { } else if (const SCEVCastExpr *Cast = dyn_cast(S)) { // Assert if a new and unknown SCEVCastEXpr type is encountered. assert((isa(Cast) || isa(Cast) || - isa(Cast) || isa(Cast)) && + isa(Cast) || isa(Cast) || + isa(Cast)) && "Unexpected cast type in SCEV."); Success &= pushCast(Cast, (isa(Cast))); diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp index a26cbeef0c6a6..6050650eb937c 100644 --- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp +++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp @@ -1310,7 +1310,7 @@ tryToUnrollLoop(Loop *L, DominatorTree &DT, LoopInfo *LI, ScalarEvolution &SE, ORE.emit([&]() { return OptimizationRemark(DEBUG_TYPE, "Peeled", L->getStartLoc(), L->getHeader()) - << " peeled loop by " << ore::NV("PeelCount", PP.PeelCount) + << "peeled loop by " << ore::NV("PeelCount", PP.PeelCount) << " iterations"; }); diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp index 83eabdae3db7f..f0a1aa3367f5b 100644 --- a/llvm/lib/Transforms/Scalar/SROA.cpp +++ b/llvm/lib/Transforms/Scalar/SROA.cpp @@ -2051,99 +2051,6 @@ static bool canConvertValue(const DataLayout &DL, Type *OldTy, Type *NewTy, return true; } -/// Generic routine to convert an SSA value to a value of a different -/// type. -/// -/// This will try various different casting techniques, such as bitcasts, -/// inttoptr, and ptrtoint casts. Use the \c canConvertValue predicate to test -/// two types for viability with this routine. -static Value *convertValue(const DataLayout &DL, IRBuilderTy &IRB, Value *V, - Type *NewTy) { - Type *OldTy = V->getType(); - -#ifndef NDEBUG - BasicBlock *BB = IRB.GetInsertBlock(); - assert(BB && BB->getParent() && "VScale unknown!"); - unsigned VScale = BB->getParent()->getVScaleValue(); - assert(canConvertValue(DL, OldTy, NewTy, VScale) && - "Value not convertable to type"); -#endif - - if (OldTy == NewTy) - return V; - - assert(!(isa(OldTy) && isa(NewTy)) && - "Integer types must be the exact same to convert."); - - // A variant of bitcast that supports a mixture of fixed and scalable types - // that are know to have the same size. - auto CreateBitCastLike = [&IRB](Value *In, Type *Ty) -> Value * { - Type *InTy = In->getType(); - if (InTy == Ty) - return In; - - if (isa(InTy) && isa(Ty)) { - // For vscale_range(2) expand <4 x i32> to --> - // <4 x i32> to to - auto *VTy = VectorType::getWithSizeAndScalar(cast(Ty), InTy); - return IRB.CreateBitCast(IRB.CreateInsertVector(VTy, - PoisonValue::get(VTy), In, - IRB.getInt64(0)), - Ty); - } - - if (isa(InTy) && isa(Ty)) { - // For vscale_range(2) expand to <4 x i32> --> - // to to <4 x i32> - auto *VTy = VectorType::getWithSizeAndScalar(cast(InTy), Ty); - return IRB.CreateExtractVector(Ty, IRB.CreateBitCast(In, VTy), - IRB.getInt64(0)); - } - - return IRB.CreateBitCast(In, Ty); - }; - - // See if we need inttoptr for this type pair. May require additional bitcast. - if (OldTy->isIntOrIntVectorTy() && NewTy->isPtrOrPtrVectorTy()) { - // Expand <2 x i32> to i8* --> <2 x i32> to i64 to i8* - // Expand i128 to <2 x i8*> --> i128 to <2 x i64> to <2 x i8*> - // Expand <4 x i32> to <2 x i8*> --> <4 x i32> to <2 x i64> to <2 x i8*> - // Directly handle i64 to i8* - return IRB.CreateIntToPtr(CreateBitCastLike(V, DL.getIntPtrType(NewTy)), - NewTy); - } - - // See if we need ptrtoint for this type pair. May require additional bitcast. - if (OldTy->isPtrOrPtrVectorTy() && NewTy->isIntOrIntVectorTy()) { - // Expand <2 x i8*> to i128 --> <2 x i8*> to <2 x i64> to i128 - // Expand i8* to <2 x i32> --> i8* to i64 to <2 x i32> - // Expand <2 x i8*> to <4 x i32> --> <2 x i8*> to <2 x i64> to <4 x i32> - // Expand i8* to i64 --> i8* to i64 to i64 - return CreateBitCastLike(IRB.CreatePtrToInt(V, DL.getIntPtrType(OldTy)), - NewTy); - } - - if (OldTy->isPtrOrPtrVectorTy() && NewTy->isPtrOrPtrVectorTy()) { - unsigned OldAS = OldTy->getPointerAddressSpace(); - unsigned NewAS = NewTy->getPointerAddressSpace(); - // To convert pointers with different address spaces (they are already - // checked convertible, i.e. they have the same pointer size), so far we - // cannot use `bitcast` (which has restrict on the same address space) or - // `addrspacecast` (which is not always no-op casting). Instead, use a pair - // of no-op `ptrtoint`/`inttoptr` casts through an integer with the same bit - // size. - if (OldAS != NewAS) { - assert(DL.getPointerSize(OldAS) == DL.getPointerSize(NewAS)); - return IRB.CreateIntToPtr( - CreateBitCastLike(IRB.CreatePtrToInt(V, DL.getIntPtrType(OldTy)), - DL.getIntPtrType(NewTy)), - NewTy); - } - } - - return CreateBitCastLike(V, NewTy); -} - /// Test whether the given slice use can be promoted to a vector. /// /// This function is called to test each entry in a partition which is slated @@ -3243,7 +3150,7 @@ class AllocaSliceRewriter : public InstVisitor { assert(!LI.isVolatile()); Value *V = IRB.CreateAlignedLoad(NewAllocaTy, &NewAI, NewAI.getAlign(), "load"); - V = convertValue(DL, IRB, V, IntTy); + V = IRB.CreateBitPreservingCastChain(DL, V, IntTy); assert(NewBeginOffset >= NewAllocaBeginOffset && "Out of bounds offset"); uint64_t Offset = NewBeginOffset - NewAllocaBeginOffset; if (Offset > 0 || NewEndOffset < NewAllocaEndOffset) { @@ -3336,7 +3243,7 @@ class AllocaSliceRewriter : public InstVisitor { V = NewLI; IsPtrAdjusted = true; } - V = convertValue(DL, IRB, V, TargetTy); + V = IRB.CreateBitPreservingCastChain(DL, V, TargetTy); if (IsSplit) { assert(!LI.isVolatile()); @@ -3391,7 +3298,7 @@ class AllocaSliceRewriter : public InstVisitor { ? ElementTy : FixedVectorType::get(ElementTy, NumElements); if (V->getType() != SliceTy) - V = convertValue(DL, IRB, V, SliceTy); + V = IRB.CreateBitPreservingCastChain(DL, V, SliceTy); // Mix in the existing elements. Value *Old = @@ -3420,12 +3327,12 @@ class AllocaSliceRewriter : public InstVisitor { IntTy->getBitWidth()) { Value *Old = IRB.CreateAlignedLoad(NewAllocaTy, &NewAI, NewAI.getAlign(), "oldload"); - Old = convertValue(DL, IRB, Old, IntTy); + Old = IRB.CreateBitPreservingCastChain(DL, Old, IntTy); assert(BeginOffset >= NewAllocaBeginOffset && "Out of bounds offset"); uint64_t Offset = BeginOffset - NewAllocaBeginOffset; V = insertInteger(DL, IRB, Old, SI.getValueOperand(), Offset, "insert"); } - V = convertValue(DL, IRB, V, NewAllocaTy); + V = IRB.CreateBitPreservingCastChain(DL, V, NewAllocaTy); StoreInst *Store = IRB.CreateAlignedStore(V, &NewAI, NewAI.getAlign()); Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access, LLVMContext::MD_access_group}); @@ -3477,7 +3384,7 @@ class AllocaSliceRewriter : public InstVisitor { if (NewBeginOffset == NewAllocaBeginOffset && NewEndOffset == NewAllocaEndOffset && canConvertValue(DL, V->getType(), NewAllocaTy)) { - V = convertValue(DL, IRB, V, NewAllocaTy); + V = IRB.CreateBitPreservingCastChain(DL, V, NewAllocaTy); Value *NewPtr = getPtrToNewAI(SI.getPointerAddressSpace(), SI.isVolatile()); @@ -3628,7 +3535,7 @@ class AllocaSliceRewriter : public InstVisitor { Value *Splat = getIntegerSplat( II.getValue(), DL.getTypeSizeInBits(ElementTy).getFixedValue() / 8); - Splat = convertValue(DL, IRB, Splat, ElementTy); + Splat = IRB.CreateBitPreservingCastChain(DL, Splat, ElementTy); if (NumElements > 1) Splat = getVectorSplat(Splat, NumElements); @@ -3643,18 +3550,18 @@ class AllocaSliceRewriter : public InstVisitor { uint64_t Size = NewEndOffset - NewBeginOffset; V = getIntegerSplat(II.getValue(), Size); - if (IntTy && (BeginOffset != NewAllocaBeginOffset || - EndOffset != NewAllocaBeginOffset)) { + if (IntTy && (NewBeginOffset != NewAllocaBeginOffset || + NewEndOffset != NewAllocaEndOffset)) { Value *Old = IRB.CreateAlignedLoad(NewAllocaTy, &NewAI, NewAI.getAlign(), "oldload"); - Old = convertValue(DL, IRB, Old, IntTy); + Old = IRB.CreateBitPreservingCastChain(DL, Old, IntTy); uint64_t Offset = NewBeginOffset - NewAllocaBeginOffset; V = insertInteger(DL, IRB, Old, V, Offset, "insert"); } else { assert(V->getType() == IntTy && "Wrong type for an alloca wide integer!"); } - V = convertValue(DL, IRB, V, NewAllocaTy); + V = IRB.CreateBitPreservingCastChain(DL, V, NewAllocaTy); } else { // Established these invariants above. assert(NewBeginOffset == NewAllocaBeginOffset); @@ -3666,7 +3573,7 @@ class AllocaSliceRewriter : public InstVisitor { V = getVectorSplat( V, cast(AllocaVecTy)->getNumElements()); - V = convertValue(DL, IRB, V, NewAllocaTy); + V = IRB.CreateBitPreservingCastChain(DL, V, NewAllocaTy); } Value *NewPtr = getPtrToNewAI(II.getDestAddressSpace(), II.isVolatile()); @@ -3868,7 +3775,7 @@ class AllocaSliceRewriter : public InstVisitor { } else if (IntTy && !IsWholeAlloca && !IsDest) { Src = IRB.CreateAlignedLoad(NewAllocaTy, &NewAI, NewAI.getAlign(), "load"); - Src = convertValue(DL, IRB, Src, IntTy); + Src = IRB.CreateBitPreservingCastChain(DL, Src, IntTy); uint64_t Offset = NewBeginOffset - NewAllocaBeginOffset; Src = extractInteger(DL, IRB, Src, SubIntTy, Offset, "extract"); } else { @@ -3889,10 +3796,10 @@ class AllocaSliceRewriter : public InstVisitor { } else if (IntTy && !IsWholeAlloca && IsDest) { Value *Old = IRB.CreateAlignedLoad(NewAllocaTy, &NewAI, NewAI.getAlign(), "oldload"); - Old = convertValue(DL, IRB, Old, IntTy); + Old = IRB.CreateBitPreservingCastChain(DL, Old, IntTy); uint64_t Offset = NewBeginOffset - NewAllocaBeginOffset; Src = insertInteger(DL, IRB, Old, Src, Offset, "insert"); - Src = convertValue(DL, IRB, Src, NewAllocaTy); + Src = IRB.CreateBitPreservingCastChain(DL, Src, NewAllocaTy); } StoreInst *Store = cast( diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp index 67b22ec33ef61..e01b5797e6622 100644 --- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp +++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp @@ -295,10 +295,6 @@ class ConstantOffsetExtractor { bool CanTraceInto(bool SignExtended, bool ZeroExtended, BinaryOperator *BO, bool NonNegative); - /// Analyze XOR instruction to extract disjoint constant bits that behave - /// like addition operations for improved address mode folding. - APInt extractDisjointBitsFromXor(BinaryOperator *XorInst); - /// The path from the constant offset to the old GEP index. e.g., if the GEP /// index is "a * b + (c + 5)". After running function find, UserChain[0] will /// be the constant 5, UserChain[1] will be the subexpression "c + 5", and @@ -601,9 +597,6 @@ APInt ConstantOffsetExtractor::find(Value *V, bool SignExtended, // Trace into subexpressions for more hoisting opportunities. if (CanTraceInto(SignExtended, ZeroExtended, BO, NonNegative)) ConstantOffset = findInEitherOperand(BO, SignExtended, ZeroExtended); - // Handle XOR with disjoint bits that can be treated as addition. - else if (BO->getOpcode() == Instruction::Xor) - ConstantOffset = extractDisjointBitsFromXor(BO); } else if (isa(V)) { ConstantOffset = find(U->getOperand(0), SignExtended, ZeroExtended, NonNegative) @@ -723,20 +716,11 @@ Value *ConstantOffsetExtractor::removeConstOffset(unsigned ChainIndex) { Value *NextInChain = removeConstOffset(ChainIndex - 1); Value *TheOther = BO->getOperand(1 - OpNo); + // If NextInChain is 0 and not the LHS of a sub, we can simplify the + // sub-expression to be just TheOther. if (ConstantInt *CI = dyn_cast(NextInChain)) { - if (CI->isZero()) { - // Custom XOR handling for disjoint bits - preserves original XOR - // with non-disjoint constant bits. - // TODO: The design should be updated to support partial constant - // extraction. - if (BO->getOpcode() == Instruction::Xor) - return BO; - - // If NextInChain is 0 and not the LHS of a sub, we can simplify the - // sub-expression to be just TheOther. - if (!(BO->getOpcode() == Instruction::Sub && OpNo == 0)) - return TheOther; - } + if (CI->isZero() && !(BO->getOpcode() == Instruction::Sub && OpNo == 0)) + return TheOther; } BinaryOperator::BinaryOps NewOp = BO->getOpcode(); @@ -767,67 +751,6 @@ Value *ConstantOffsetExtractor::removeConstOffset(unsigned ChainIndex) { return NewBO; } -/// Analyze XOR instruction to extract disjoint constant bits for address -/// folding -/// -/// This function identifies bits in an XOR constant operand that are disjoint -/// from the base operand's known set bits. For these disjoint bits, XOR behaves -/// identically to addition, allowing us to extract them as constant offsets -/// that can be folded into addressing modes. -/// -/// Transformation: `Base ^ Const` becomes `(Base ^ NonDisjointBits) + -/// DisjointBits` where DisjointBits = Const & KnownZeros(Base) -/// -/// Example with ptr having known-zero low bit: -/// Original: `xor %ptr, 3` ; 3 = 0b11 -/// Analysis: DisjointBits = 3 & KnownZeros(%ptr) = 0b11 & 0b01 = 0b01 -/// Result: `(xor %ptr, 2) + 1` where 1 can be folded into address mode -/// -/// \param XorInst The XOR binary operator to analyze -/// \return APInt containing the disjoint bits that can be extracted as offset, -/// or zero if no disjoint bits exist -APInt ConstantOffsetExtractor::extractDisjointBitsFromXor( - BinaryOperator *XorInst) { - assert(XorInst && XorInst->getOpcode() == Instruction::Xor && - "Expected XOR instruction"); - - const unsigned BitWidth = XorInst->getType()->getScalarSizeInBits(); - Value *BaseOperand; - ConstantInt *XorConstant; - - // Match pattern: xor BaseOperand, Constant. - if (!match(XorInst, m_Xor(m_Value(BaseOperand), m_ConstantInt(XorConstant)))) - return APInt::getZero(BitWidth); - - // Compute known bits for the base operand. - const SimplifyQuery SQ(DL); - const KnownBits BaseKnownBits = computeKnownBits(BaseOperand, SQ); - const APInt &ConstantValue = XorConstant->getValue(); - - // Identify disjoint bits: constant bits that are known zero in base. - const APInt DisjointBits = ConstantValue & BaseKnownBits.Zero; - - // Early exit if no disjoint bits found. - if (DisjointBits.isZero()) - return APInt::getZero(BitWidth); - - // Compute the remaining non-disjoint bits that stay in the XOR. - const APInt NonDisjointBits = ConstantValue & ~DisjointBits; - - // FIXME: Enhance XOR constant extraction to handle nested binary operations. - // Currently we only extract disjoint bits from the immediate XOR constant, - // but we could recursively process cases like: - // xor (add %base, C1), C2 -> add %base, (C1 ^ disjoint_bits(C2)) - // This requires careful analysis to ensure the transformation preserves - // semantics, particularly around sign extension and overflow behavior. - - // Add the non-disjoint constant to the user chain for later transformation - // This will replace the original constant in the XOR with the new - // constant. - UserChain.push_back(ConstantInt::get(XorInst->getType(), NonDisjointBits)); - return DisjointBits; -} - /// A helper function to check if reassociating through an entry in the user /// chain would invalidate the GEP's nuw flag. static bool allowsPreservingNUW(const User *U) { diff --git a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp index 7e8cc03f7b002..531922babc50a 100644 --- a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp +++ b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp @@ -669,7 +669,7 @@ static bool unswitchTrivialBranch(Loop &L, BranchInst &BI, DominatorTree &DT, UnswitchedBB = LoopExitBB; } else { UnswitchedBB = - SplitBlock(LoopExitBB, LoopExitBB->begin(), &DT, &LI, MSSAU, "", false); + SplitBlock(LoopExitBB, LoopExitBB->begin(), &DT, &LI, MSSAU, ""); } if (MSSAU && VerifyMemorySSA) @@ -2576,12 +2576,14 @@ static void unswitchNontrivialInvariants( if (MSSAU && VerifyMemorySSA) MSSAU->getMemorySSA()->verifyMemorySSA(); +#ifdef EXPENSIVE_CHECKS // This transformation has a high risk of corrupting the dominator tree, and // the below steps to rebuild loop structures will result in hard to debug // errors in that case so verify that the dominator tree is sane first. // FIXME: Remove this when the bugs stop showing up and rely on existing // verification steps. assert(DT.verify(DominatorTree::VerificationLevel::Fast)); +#endif if (BI && !PartiallyInvariant) { // If we unswitched a branch which collapses the condition to a known @@ -2687,7 +2689,7 @@ static void unswitchNontrivialInvariants( OuterL = OuterL->getParentLoop()) UpdateLoop(*OuterL); -#ifndef NDEBUG +#ifdef EXPENSIVE_CHECKS // Verify the entire loop structure to catch any incorrect updates before we // progress in the pass pipeline. LI.verify(DT); @@ -3751,9 +3753,11 @@ PreservedAnalyses SimpleLoopUnswitchPass::run(Loop &L, LoopAnalysisManager &AM, if (AR.MSSA && VerifyMemorySSA) AR.MSSA->verifyMemorySSA(); +#ifdef EXPENSIVE_CHECKS // Historically this pass has had issues with the dominator tree so verify it // in asserts builds. assert(AR.DT.verify(DominatorTree::VerificationLevel::Fast)); +#endif auto PA = getLoopPassPreservedAnalyses(); if (AR.MSSA) diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp index b0c04086f5e84..6472e1771ec73 100644 --- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -679,8 +679,8 @@ BasicBlock *llvm::SplitEdge(BasicBlock *BB, BasicBlock *Succ, DominatorTree *DT, // block. assert(SP == BB && "CFG broken"); (void)SP; - return SplitBlock(Succ, &Succ->front(), DT, LI, MSSAU, BBName, - /*Before=*/true); + DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Lazy); + return splitBlockBefore(Succ, &Succ->front(), &DTU, LI, MSSAU, BBName); } // Otherwise, if BB has a single successor, split it at the bottom of the @@ -996,13 +996,7 @@ llvm::SplitAllCriticalEdges(Function &F, static BasicBlock *SplitBlockImpl(BasicBlock *Old, BasicBlock::iterator SplitPt, DomTreeUpdater *DTU, DominatorTree *DT, LoopInfo *LI, MemorySSAUpdater *MSSAU, - const Twine &BBName, bool Before) { - if (Before) { - DomTreeUpdater LocalDTU(DT, DomTreeUpdater::UpdateStrategy::Lazy); - return splitBlockBefore(Old, SplitPt, - DTU ? DTU : (DT ? &LocalDTU : nullptr), LI, MSSAU, - BBName); - } + const Twine &BBName) { BasicBlock::iterator SplitIt = SplitPt; while (isa(SplitIt) || SplitIt->isEHPad()) { ++SplitIt; @@ -1051,62 +1045,13 @@ static BasicBlock *SplitBlockImpl(BasicBlock *Old, BasicBlock::iterator SplitPt, BasicBlock *llvm::SplitBlock(BasicBlock *Old, BasicBlock::iterator SplitPt, DominatorTree *DT, LoopInfo *LI, - MemorySSAUpdater *MSSAU, const Twine &BBName, - bool Before) { - return SplitBlockImpl(Old, SplitPt, /*DTU=*/nullptr, DT, LI, MSSAU, BBName, - Before); + MemorySSAUpdater *MSSAU, const Twine &BBName) { + return SplitBlockImpl(Old, SplitPt, /*DTU=*/nullptr, DT, LI, MSSAU, BBName); } BasicBlock *llvm::SplitBlock(BasicBlock *Old, BasicBlock::iterator SplitPt, DomTreeUpdater *DTU, LoopInfo *LI, - MemorySSAUpdater *MSSAU, const Twine &BBName, - bool Before) { - return SplitBlockImpl(Old, SplitPt, DTU, /*DT=*/nullptr, LI, MSSAU, BBName, - Before); -} - -BasicBlock *llvm::splitBlockBefore(BasicBlock *Old, BasicBlock::iterator SplitPt, - DomTreeUpdater *DTU, LoopInfo *LI, - MemorySSAUpdater *MSSAU, - const Twine &BBName) { - - BasicBlock::iterator SplitIt = SplitPt; - while (isa(SplitIt) || SplitIt->isEHPad()) - ++SplitIt; - std::string Name = BBName.str(); - BasicBlock *New = Old->splitBasicBlock( - SplitIt, Name.empty() ? Old->getName() + ".split" : Name, - /* Before=*/true); - - // The new block lives in whichever loop the old one did. This preserves - // LCSSA as well, because we force the split point to be after any PHI nodes. - if (LI) - if (Loop *L = LI->getLoopFor(Old)) - L->addBasicBlockToLoop(New, *LI); - - if (DTU) { - SmallVector DTUpdates; - // New dominates Old. The predecessor nodes of the Old node dominate - // New node. - SmallPtrSet UniquePredecessorsOfOld; - DTUpdates.push_back({DominatorTree::Insert, New, Old}); - DTUpdates.reserve(DTUpdates.size() + 2 * pred_size(New)); - for (BasicBlock *PredecessorOfOld : predecessors(New)) - if (UniquePredecessorsOfOld.insert(PredecessorOfOld).second) { - DTUpdates.push_back({DominatorTree::Insert, PredecessorOfOld, New}); - DTUpdates.push_back({DominatorTree::Delete, PredecessorOfOld, Old}); - } - - DTU->applyUpdates(DTUpdates); - - // Move MemoryAccesses still tracked in Old, but part of New now. - // Update accesses in successor blocks accordingly. - if (MSSAU) { - MSSAU->applyUpdates(DTUpdates, DTU->getDomTree()); - if (VerifyMemorySSA) - MSSAU->getMemorySSA()->verifyMemorySSA(); - } - } - return New; + MemorySSAUpdater *MSSAU, const Twine &BBName) { + return SplitBlockImpl(Old, SplitPt, DTU, /*DT=*/nullptr, LI, MSSAU, BBName); } /// Update DominatorTree, LoopInfo, and LCCSA analysis information. @@ -1223,6 +1168,25 @@ static void UpdateAnalysisInformation(BasicBlock *OldBB, BasicBlock *NewBB, } } +BasicBlock *llvm::splitBlockBefore(BasicBlock *Old, + BasicBlock::iterator SplitPt, + DomTreeUpdater *DTU, LoopInfo *LI, + MemorySSAUpdater *MSSAU, + const Twine &BBName) { + BasicBlock::iterator SplitIt = SplitPt; + while (isa(SplitIt) || SplitIt->isEHPad()) + ++SplitIt; + SmallVector Preds(predecessors(Old)); + BasicBlock *New = Old->splitBasicBlockBefore( + SplitIt, BBName.isTriviallyEmpty() ? Old->getName() + ".split" : BBName); + + bool HasLoopExit = false; + UpdateAnalysisInformation(Old, New, Preds, DTU, nullptr, LI, MSSAU, false, + HasLoopExit); + + return New; +} + /// Update the PHI nodes in OrigBB to include the values coming from NewBB. /// This also updates AliasAnalysis, if available. static void UpdatePHINodes(BasicBlock *OrigBB, BasicBlock *NewBB, diff --git a/llvm/lib/Transforms/Utils/CloneFunction.cpp b/llvm/lib/Transforms/Utils/CloneFunction.cpp index 260dc3a12df43..192d313b23798 100644 --- a/llvm/lib/Transforms/Utils/CloneFunction.cpp +++ b/llvm/lib/Transforms/Utils/CloneFunction.cpp @@ -88,8 +88,8 @@ createIdentityMDPredicate(const Function &F, CloneFunctionChangeType Changes) { }; return [=](const Metadata *MD) { - // Avoid cloning types, compile units, and (other) subprograms. - if (isa(MD) || isa(MD)) + // Avoid cloning compile units. + if (isa(MD)) return true; if (auto *SP = dyn_cast(MD)) @@ -104,6 +104,29 @@ createIdentityMDPredicate(const Function &F, CloneFunctionChangeType Changes) { if (auto *S = dyn_cast_or_null(DV->getScope())) return ShouldKeep(S->getSubprogram()); + // Clone types that are local to subprograms being cloned. + // Avoid cloning other types. + auto *Type = dyn_cast(MD); + if (!Type) + return false; + + // No need to clone types if subprograms are not cloned. + if (SPClonedWithinModule == nullptr) + return true; + + // Scopeless types may be derived from local types (e.g. pointers to local + // types). They may need cloning. + if (const DIDerivedType *DTy = dyn_cast_or_null(Type); + DTy && !DTy->getScope()) + return false; + + auto *LScope = dyn_cast_or_null(Type->getScope()); + if (!LScope) + return true; + + if (ShouldKeep(LScope->getSubprogram())) + return true; + return false; }; } diff --git a/llvm/lib/Transforms/Utils/CodeExtractor.cpp b/llvm/lib/Transforms/Utils/CodeExtractor.cpp index a6ba42f5bec2a..fe8758b942938 100644 --- a/llvm/lib/Transforms/Utils/CodeExtractor.cpp +++ b/llvm/lib/Transforms/Utils/CodeExtractor.cpp @@ -982,6 +982,7 @@ Function *CodeExtractor::constructFunctionDeclaration( case Attribute::MustProgress: case Attribute::NoProfile: case Attribute::SkipProfile: + case Attribute::DenormalFPEnv: break; // These attributes cannot be applied to functions. case Attribute::Alignment: diff --git a/llvm/lib/Transforms/Utils/Evaluator.cpp b/llvm/lib/Transforms/Utils/Evaluator.cpp index 3a5c7a3b1738e..b2ee1da143ba7 100644 --- a/llvm/lib/Transforms/Utils/Evaluator.cpp +++ b/llvm/lib/Transforms/Utils/Evaluator.cpp @@ -431,10 +431,9 @@ bool Evaluator::EvaluateBlock(BasicBlock::iterator CurInst, BasicBlock *&NextBB, Value *PtrArg = getVal(II->getArgOperand(1)); Value *Ptr = PtrArg->stripPointerCasts(); if (GlobalVariable *GV = dyn_cast(Ptr)) { - Type *ElemTy = GV->getValueType(); + uint64_t MinGVSize = GV->getGlobalSize(DL); if (!Size->isMinusOne() && - Size->getValue().getLimitedValue() >= - DL.getTypeStoreSize(ElemTy)) { + Size->getValue().getLimitedValue() >= MinGVSize) { Invariants.insert(GV); LLVM_DEBUG(dbgs() << "Found a global var that is an invariant: " << *GV << "\n"); diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp index aa902f687d8aa..3230b306f17d1 100644 --- a/llvm/lib/Transforms/Utils/InlineFunction.cpp +++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp @@ -1543,6 +1543,8 @@ static AttrBuilder IdentifyValidPoisonGeneratingAttributes(CallBase &CB) { Valid.addAlignmentAttr(CB.getRetAlign()); if (std::optional Range = CB.getRange()) Valid.addRangeAttr(*Range); + if (CB.hasRetAttr(Attribute::NoFPClass)) + Valid.addNoFPClassAttr(CB.getRetNoFPClass()); return Valid; } @@ -1648,6 +1650,14 @@ static void AddReturnAttributes(CallBase &CB, ValueToValueMapTy &VMap, CBRange.getRange().intersectWith(NewRange.getRange())); } } + + Attribute CBNoFPClass = ValidPG.getAttribute(Attribute::NoFPClass); + if (CBNoFPClass.isValid() && AL.hasRetAttr(Attribute::NoFPClass)) { + ValidPG.addNoFPClassAttr( + CBNoFPClass.getNoFPClass() | + AL.getRetAttr(Attribute::NoFPClass).getNoFPClass()); + } + // Three checks. // If the callsite has `noundef`, then a poison due to violating the // return attribute will create UB anyways so we can always propagate. diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 9b9516da9c552..aa52003e8dfe1 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -457,6 +457,7 @@ bool llvm::wouldInstructionBeTriviallyDead(const Instruction *I, case Intrinsic::wasm_trunc_unsigned: case Intrinsic::ptrauth_auth: case Intrinsic::ptrauth_resign: + case Intrinsic::ptrauth_resign_load_relative: return true; default: return false; diff --git a/llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp b/llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp index e77cdbe7a3876..7623f3b9a6c08 100644 --- a/llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp +++ b/llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp @@ -317,11 +317,13 @@ void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr, "Atomic memcpy lowering is not supported for vector operand type"); Type *Int8Type = Type::getInt8Ty(Ctx); - unsigned LoopOpSize = DL.getTypeStoreSize(LoopOpType); + TypeSize LoopOpSize = DL.getTypeStoreSize(LoopOpType); + assert(LoopOpSize.isFixed() && "LoopOpType cannot be a scalable vector type"); assert((!AtomicElementSize || LoopOpSize % *AtomicElementSize == 0) && "Atomic memcpy lowering is not supported for selected operand size"); - uint64_t LoopEndCount = alignDown(CopyLen->getZExtValue(), LoopOpSize); + uint64_t LoopEndCount = + alignDown(CopyLen->getZExtValue(), LoopOpSize.getFixedValue()); // Skip the loop expansion entirely if the loop would never be taken. if (LoopEndCount != 0) { @@ -379,7 +381,7 @@ void llvm::createMemCpyLoopKnownSize(Instruction *InsertBefore, Value *SrcAddr, Align PartSrcAlign(commonAlignment(SrcAlign, BytesCopied)); Align PartDstAlign(commonAlignment(DstAlign, BytesCopied)); - unsigned OperandSize = DL.getTypeStoreSize(OpTy); + TypeSize OperandSize = DL.getTypeStoreSize(OpTy); assert((!AtomicElementSize || OperandSize % *AtomicElementSize == 0) && "Atomic memcpy lowering is not supported for selected operand size"); @@ -432,7 +434,7 @@ void llvm::createMemCpyLoopUnknownSize( Ctx, CopyLen, SrcAS, DstAS, SrcAlign, DstAlign, AtomicElementSize); assert((!AtomicElementSize || !LoopOpType->isVectorTy()) && "Atomic memcpy lowering is not supported for vector operand type"); - unsigned LoopOpSize = DL.getTypeStoreSize(LoopOpType); + TypeSize LoopOpSize = DL.getTypeStoreSize(LoopOpType); assert((!AtomicElementSize || LoopOpSize % *AtomicElementSize == 0) && "Atomic memcpy lowering is not supported for selected operand size"); @@ -441,7 +443,7 @@ void llvm::createMemCpyLoopUnknownSize( Type *ResidualLoopOpType = AtomicElementSize ? Type::getIntNTy(Ctx, *AtomicElementSize * 8) : Int8Type; - unsigned ResidualLoopOpSize = DL.getTypeStoreSize(ResidualLoopOpType); + TypeSize ResidualLoopOpSize = DL.getTypeStoreSize(ResidualLoopOpType); assert(ResidualLoopOpSize == (AtomicElementSize ? *AtomicElementSize : 1) && "Store size is expected to match type size"); @@ -576,7 +578,7 @@ static void createMemMoveLoopUnknownSize(Instruction *InsertBefore, Type *LoopOpType = TTI.getMemcpyLoopLoweringType(Ctx, CopyLen, SrcAS, DstAS, SrcAlign, DstAlign); - unsigned LoopOpSize = DL.getTypeStoreSize(LoopOpType); + TypeSize LoopOpSize = DL.getTypeStoreSize(LoopOpType); Type *Int8Type = Type::getInt8Ty(Ctx); bool LoopOpIsInt8 = LoopOpType == Int8Type; @@ -585,7 +587,7 @@ static void createMemMoveLoopUnknownSize(Instruction *InsertBefore, bool RequiresResidual = !LoopOpIsInt8; Type *ResidualLoopOpType = Int8Type; - unsigned ResidualLoopOpSize = DL.getTypeStoreSize(ResidualLoopOpType); + TypeSize ResidualLoopOpSize = DL.getTypeStoreSize(ResidualLoopOpType); // Calculate the loop trip count and remaining bytes to copy after the loop. IntegerType *ILengthType = cast(TypeOfCopyLen); @@ -847,11 +849,13 @@ static void createMemMoveLoopKnownSize(Instruction *InsertBefore, Type *LoopOpType = TTI.getMemcpyLoopLoweringType(Ctx, CopyLen, SrcAS, DstAS, SrcAlign, DstAlign); - unsigned LoopOpSize = DL.getTypeStoreSize(LoopOpType); + TypeSize LoopOpSize = DL.getTypeStoreSize(LoopOpType); + assert(LoopOpSize.isFixed() && "LoopOpType cannot be a scalable vector type"); Type *Int8Type = Type::getInt8Ty(Ctx); // Calculate the loop trip count and remaining bytes to copy after the loop. - uint64_t BytesCopiedInLoop = alignDown(CopyLen->getZExtValue(), LoopOpSize); + uint64_t BytesCopiedInLoop = + alignDown(CopyLen->getZExtValue(), LoopOpSize.getFixedValue()); uint64_t RemainingBytes = CopyLen->getZExtValue() - BytesCopiedInLoop; IntegerType *ILengthType = cast(TypeOfCopyLen); @@ -886,7 +890,7 @@ static void createMemMoveLoopKnownSize(Instruction *InsertBefore, Align ResSrcAlign(commonAlignment(SrcAlign, BytesCopied)); Align ResDstAlign(commonAlignment(DstAlign, BytesCopied)); - unsigned OperandSize = DL.getTypeStoreSize(OpTy); + TypeSize OperandSize = DL.getTypeStoreSize(OpTy); // If we used LoopOpType as GEP element type, we would iterate over the // buffers in TypeStoreSize strides while copying TypeAllocSize bytes, i.e., @@ -1007,10 +1011,200 @@ static void createMemMoveLoopKnownSize(Instruction *InsertBefore, } } +/// Create a Value of \p DstType that consists of a sequence of copies of +/// \p SetValue, using bitcasts and a vector splat. +static Value *createMemSetSplat(const DataLayout &DL, IRBuilderBase &B, + Value *SetValue, Type *DstType) { + TypeSize DstSize = DL.getTypeStoreSize(DstType); + Type *SetValueType = SetValue->getType(); + TypeSize SetValueSize = DL.getTypeStoreSize(SetValueType); + assert(SetValueSize == DL.getTypeAllocSize(SetValueType) && + "Store size and alloc size of SetValue's type must match"); + assert(SetValueSize != 0 && DstSize % SetValueSize == 0 && + "DstType size must be a multiple of SetValue size"); + + Value *Result = SetValue; + if (DstSize != SetValueSize) { + if (!SetValueType->isIntegerTy() && !SetValueType->isFloatingPointTy()) { + // If the type cannot be put into a vector, bitcast to iN first. + LLVMContext &Ctx = SetValue->getContext(); + Result = B.CreateBitCast(Result, Type::getIntNTy(Ctx, SetValueSize * 8), + "setvalue.toint"); + } + // Form a sufficiently large vector consisting of SetValue, repeated. + Result = + B.CreateVectorSplat(DstSize / SetValueSize, Result, "setvalue.splat"); + } + + // The value has the right size, but we might have to bitcast it to the right + // type. + Result = B.CreateBitCast(Result, DstType, "setvalue.splat.cast"); + return Result; +} + +static void +createMemSetLoopKnownSize(Instruction *InsertBefore, Value *DstAddr, + ConstantInt *Len, Value *SetValue, Align DstAlign, + bool IsVolatile, const TargetTransformInfo *TTI, + std::optional AverageTripCount) { + // No need to expand zero length memsets. + if (Len->isZero()) + return; + + BasicBlock *PreLoopBB = InsertBefore->getParent(); + Function *ParentFunc = PreLoopBB->getParent(); + const DataLayout &DL = ParentFunc->getDataLayout(); + LLVMContext &Ctx = PreLoopBB->getContext(); + + unsigned DstAS = cast(DstAddr->getType())->getAddressSpace(); + + Type *TypeOfLen = Len->getType(); + Type *Int8Type = Type::getInt8Ty(Ctx); + assert(SetValue->getType() == Int8Type && "Can only set bytes"); + + Type *LoopOpType = Int8Type; + if (TTI) { + // Use the same memory access type as for a memcpy with the same Dst and Src + // alignment and address space. + LoopOpType = TTI->getMemcpyLoopLoweringType( + Ctx, Len, DstAS, DstAS, DstAlign, DstAlign, std::nullopt); + } + TypeSize LoopOpSize = DL.getTypeStoreSize(LoopOpType); + assert(LoopOpSize.isFixed() && "LoopOpType cannot be a scalable vector type"); + + uint64_t LoopEndCount = + alignDown(Len->getZExtValue(), LoopOpSize.getFixedValue()); + + if (LoopEndCount != 0) { + Value *SplatSetValue = nullptr; + { + IRBuilder<> PreLoopBuilder(InsertBefore); + SplatSetValue = + createMemSetSplat(DL, PreLoopBuilder, SetValue, LoopOpType); + } + + // Don't generate a residual loop, the remaining bytes are set with + // straight-line code. + LoopExpansionInfo LEI = insertLoopExpansion( + InsertBefore, Len, LoopOpSize, 0, "static-memset", AverageTripCount); + + // Fill MainLoopBB + IRBuilder<> MainLoopBuilder(LEI.MainLoopIP); + Align PartDstAlign(commonAlignment(DstAlign, LoopOpSize)); + + Value *DstGEP = + MainLoopBuilder.CreateInBoundsGEP(Int8Type, DstAddr, LEI.MainLoopIndex); + + MainLoopBuilder.CreateAlignedStore(SplatSetValue, DstGEP, PartDstAlign, + IsVolatile); + + assert(!LEI.ResidualLoopIP && !LEI.ResidualLoopIndex && + "No residual loop was requested"); + } + + uint64_t BytesSet = LoopEndCount; + uint64_t RemainingBytes = Len->getZExtValue() - BytesSet; + if (RemainingBytes == 0) + return; + + IRBuilder<> RBuilder(InsertBefore); + + assert(TTI && "there cannot be a residual loop without TTI"); + SmallVector RemainingOps; + TTI->getMemcpyLoopResidualLoweringType(RemainingOps, Ctx, RemainingBytes, + DstAS, DstAS, DstAlign, DstAlign, + std::nullopt); + + Type *PreviousOpTy = nullptr; + Value *SplatSetValue = nullptr; + for (auto *OpTy : RemainingOps) { + TypeSize OperandSize = DL.getTypeStoreSize(OpTy); + assert(OperandSize.isFixed() && + "Operand types cannot be scalable vector types"); + Align PartDstAlign(commonAlignment(DstAlign, BytesSet)); + + // Avoid recomputing the splat SetValue if it's the same as for the last + // iteration. + if (OpTy != PreviousOpTy) + SplatSetValue = createMemSetSplat(DL, RBuilder, SetValue, OpTy); + + Value *DstGEP = RBuilder.CreateInBoundsGEP( + Int8Type, DstAddr, ConstantInt::get(TypeOfLen, BytesSet)); + RBuilder.CreateAlignedStore(SplatSetValue, DstGEP, PartDstAlign, + IsVolatile); + BytesSet += OperandSize; + PreviousOpTy = OpTy; + } + assert(BytesSet == Len->getZExtValue() && + "Bytes set should match size in the call!"); +} + +static void +createMemSetLoopUnknownSize(Instruction *InsertBefore, Value *DstAddr, + Value *Len, Value *SetValue, Align DstAlign, + bool IsVolatile, const TargetTransformInfo *TTI, + std::optional AverageTripCount) { + BasicBlock *PreLoopBB = InsertBefore->getParent(); + Function *ParentFunc = PreLoopBB->getParent(); + const DataLayout &DL = ParentFunc->getDataLayout(); + LLVMContext &Ctx = PreLoopBB->getContext(); + + unsigned DstAS = cast(DstAddr->getType())->getAddressSpace(); + + Type *Int8Type = Type::getInt8Ty(Ctx); + assert(SetValue->getType() == Int8Type && "Can only set bytes"); + + Type *LoopOpType = Int8Type; + if (TTI) { + LoopOpType = TTI->getMemcpyLoopLoweringType( + Ctx, Len, DstAS, DstAS, DstAlign, DstAlign, std::nullopt); + } + TypeSize LoopOpSize = DL.getTypeStoreSize(LoopOpType); + assert(LoopOpSize.isFixed() && "LoopOpType cannot be a scalable vector type"); + + Type *ResidualLoopOpType = Int8Type; + TypeSize ResidualLoopOpSize = DL.getTypeStoreSize(ResidualLoopOpType); + + Value *SplatSetValue = SetValue; + { + IRBuilder<> PreLoopBuilder(InsertBefore); + SplatSetValue = createMemSetSplat(DL, PreLoopBuilder, SetValue, LoopOpType); + } + + LoopExpansionInfo LEI = + insertLoopExpansion(InsertBefore, Len, LoopOpSize, ResidualLoopOpSize, + "dynamic-memset", AverageTripCount); + + // Fill MainLoopBB + IRBuilder<> MainLoopBuilder(LEI.MainLoopIP); + Align PartDstAlign(commonAlignment(DstAlign, LoopOpSize)); + + Value *DstGEP = + MainLoopBuilder.CreateInBoundsGEP(Int8Type, DstAddr, LEI.MainLoopIndex); + MainLoopBuilder.CreateAlignedStore(SplatSetValue, DstGEP, PartDstAlign, + IsVolatile); + + // Fill ResidualLoopBB + if (!LEI.ResidualLoopIP) + return; + + Align ResDstAlign(commonAlignment(PartDstAlign, ResidualLoopOpSize)); + + IRBuilder<> ResLoopBuilder(LEI.ResidualLoopIP); + + Value *ResDstGEP = ResLoopBuilder.CreateInBoundsGEP(Int8Type, DstAddr, + LEI.ResidualLoopIndex); + ResLoopBuilder.CreateAlignedStore(SetValue, ResDstGEP, ResDstAlign, + IsVolatile); +} + static void createMemSetLoop(Instruction *InsertBefore, Value *DstAddr, Value *CopyLen, Value *SetValue, Align DstAlign, std::optional AverageTripCount, bool IsVolatile) { + // Currently no longer used for memset, only for memset.pattern. + // TODO: Update the memset.pattern lowering to also use the loop expansion + // framework and remove this function. Type *TypeOfCopyLen = CopyLen->getType(); BasicBlock *OrigBB = InsertBefore->getParent(); Function *F = OrigBB->getParent(); @@ -1036,7 +1230,7 @@ static void createMemSetLoop(Instruction *InsertBefore, Value *DstAddr, OrigBB->getTerminator()->eraseFromParent(); - unsigned PartSize = DL.getTypeStoreSize(SetValue->getType()); + TypeSize PartSize = DL.getTypeStoreSize(SetValue->getType()); Align PartAlign(commonAlignment(DstAlign, PartSize)); IRBuilder<> LoopBuilder(LoopBB); @@ -1080,32 +1274,32 @@ void llvm::expandMemCpyAsLoop(MemCpyInst *Memcpy, auto TripCount = getAverageMemOpLoopTripCount(*Memcpy); if (ConstantInt *CI = dyn_cast(Memcpy->getLength())) { createMemCpyLoopKnownSize( - /* InsertBefore */ Memcpy, - /* SrcAddr */ Memcpy->getRawSource(), - /* DstAddr */ Memcpy->getRawDest(), - /* CopyLen */ CI, - /* SrcAlign */ Memcpy->getSourceAlign().valueOrOne(), - /* DestAlign */ Memcpy->getDestAlign().valueOrOne(), - /* SrcIsVolatile */ Memcpy->isVolatile(), - /* DstIsVolatile */ Memcpy->isVolatile(), - /* CanOverlap */ CanOverlap, - /* TargetTransformInfo */ TTI, - /* AtomicElementSize */ std::nullopt, - /* AverageTripCount */ TripCount); + /*InsertBefore=*/Memcpy, + /*SrcAddr=*/Memcpy->getRawSource(), + /*DstAddr=*/Memcpy->getRawDest(), + /*CopyLen=*/CI, + /*SrcAlign=*/Memcpy->getSourceAlign().valueOrOne(), + /*DstAlign=*/Memcpy->getDestAlign().valueOrOne(), + /*SrcIsVolatile=*/Memcpy->isVolatile(), + /*DstIsVolatile=*/Memcpy->isVolatile(), + /*CanOverlap=*/CanOverlap, + /*TTI=*/TTI, + /*AtomicElementSize=*/std::nullopt, + /*AverageTripCount=*/TripCount); } else { createMemCpyLoopUnknownSize( - /* InsertBefore */ Memcpy, - /* SrcAddr */ Memcpy->getRawSource(), - /* DstAddr */ Memcpy->getRawDest(), - /* CopyLen */ Memcpy->getLength(), - /* SrcAlign */ Memcpy->getSourceAlign().valueOrOne(), - /* DestAlign */ Memcpy->getDestAlign().valueOrOne(), - /* SrcIsVolatile */ Memcpy->isVolatile(), - /* DstIsVolatile */ Memcpy->isVolatile(), - /* CanOverlap */ CanOverlap, - /* TargetTransformInfo */ TTI, - /* AtomicElementSize */ std::nullopt, - /* AverageTripCount */ TripCount); + /*InsertBefore=*/Memcpy, + /*SrcAddr=*/Memcpy->getRawSource(), + /*DstAddr=*/Memcpy->getRawDest(), + /*CopyLen=*/Memcpy->getLength(), + /*SrcAlign=*/Memcpy->getSourceAlign().valueOrOne(), + /*DstAlign=*/Memcpy->getDestAlign().valueOrOne(), + /*SrcIsVolatile=*/Memcpy->isVolatile(), + /*DstIsVolatile=*/Memcpy->isVolatile(), + /*CanOverlap=*/CanOverlap, + /*TTI=*/TTI, + /*AtomicElementSize=*/std::nullopt, + /*AverageTripCount=*/TripCount); } } @@ -1167,24 +1361,45 @@ bool llvm::expandMemMoveAsLoop(MemMoveInst *Memmove, return true; } -void llvm::expandMemSetAsLoop(MemSetInst *Memset) { - createMemSetLoop(/* InsertBefore */ Memset, - /* DstAddr */ Memset->getRawDest(), - /* CopyLen */ Memset->getLength(), - /* SetValue */ Memset->getValue(), - /* Alignment */ Memset->getDestAlign().valueOrOne(), - /* AverageTripCount */ getAverageMemOpLoopTripCount(*Memset), - /* IsVolatile */ Memset->isVolatile()); +void llvm::expandMemSetAsLoop(MemSetInst *Memset, + const TargetTransformInfo *TTI) { + auto AverageTripCount = getAverageMemOpLoopTripCount(*Memset); + if (ConstantInt *CI = dyn_cast(Memset->getLength())) { + createMemSetLoopKnownSize( + /*InsertBefore=*/Memset, + /*DstAddr=*/Memset->getRawDest(), + /*Len=*/CI, + /*SetValue=*/Memset->getValue(), + /*DstAlign=*/Memset->getDestAlign().valueOrOne(), + /*IsVolatile=*/Memset->isVolatile(), + /*TTI=*/TTI, + /*AverageTripCount=*/AverageTripCount); + } else { + createMemSetLoopUnknownSize( + /*InsertBefore=*/Memset, + /*DstAddr=*/Memset->getRawDest(), + /*Len=*/Memset->getLength(), + /*SetValue=*/Memset->getValue(), + /*DstAlign=*/Memset->getDestAlign().valueOrOne(), + /*IsVolatile=*/Memset->isVolatile(), + /*TTI=*/TTI, + /*AverageTripCount=*/AverageTripCount); + } +} + +void llvm::expandMemSetAsLoop(MemSetInst *MemSet, + const TargetTransformInfo &TTI) { + expandMemSetAsLoop(MemSet, &TTI); } void llvm::expandMemSetPatternAsLoop(MemSetPatternInst *Memset) { - createMemSetLoop(/* InsertBefore=*/Memset, - /* DstAddr=*/Memset->getRawDest(), - /* CopyLen=*/Memset->getLength(), - /* SetValue=*/Memset->getValue(), - /* Alignment=*/Memset->getDestAlign().valueOrOne(), - /* AverageTripCount */ getAverageMemOpLoopTripCount(*Memset), - /* IsVolatile */ Memset->isVolatile()); + createMemSetLoop(/*InsertBefore=*/Memset, + /*DstAddr=*/Memset->getRawDest(), + /*CopyLen=*/Memset->getLength(), + /*SetValue=*/Memset->getValue(), + /*DstAlign=*/Memset->getDestAlign().valueOrOne(), + /*AverageTripCount=*/getAverageMemOpLoopTripCount(*Memset), + /*IsVolatile=*/Memset->isVolatile()); } void llvm::expandAtomicMemCpyAsLoop(AnyMemCpyInst *AtomicMemcpy, @@ -1193,29 +1408,29 @@ void llvm::expandAtomicMemCpyAsLoop(AnyMemCpyInst *AtomicMemcpy, assert(AtomicMemcpy->isAtomic()); if (ConstantInt *CI = dyn_cast(AtomicMemcpy->getLength())) { createMemCpyLoopKnownSize( - /* InsertBefore */ AtomicMemcpy, - /* SrcAddr */ AtomicMemcpy->getRawSource(), - /* DstAddr */ AtomicMemcpy->getRawDest(), - /* CopyLen */ CI, - /* SrcAlign */ AtomicMemcpy->getSourceAlign().valueOrOne(), - /* DestAlign */ AtomicMemcpy->getDestAlign().valueOrOne(), - /* SrcIsVolatile */ AtomicMemcpy->isVolatile(), - /* DstIsVolatile */ AtomicMemcpy->isVolatile(), - /* CanOverlap */ false, // SrcAddr & DstAddr may not overlap by spec. - /* TargetTransformInfo */ TTI, - /* AtomicElementSize */ AtomicMemcpy->getElementSizeInBytes()); + /*InsertBefore=*/AtomicMemcpy, + /*SrcAddr=*/AtomicMemcpy->getRawSource(), + /*DstAddr=*/AtomicMemcpy->getRawDest(), + /*CopyLen=*/CI, + /*SrcAlign=*/AtomicMemcpy->getSourceAlign().valueOrOne(), + /*DstAlign=*/AtomicMemcpy->getDestAlign().valueOrOne(), + /*SrcIsVolatile=*/AtomicMemcpy->isVolatile(), + /*DstIsVolatile=*/AtomicMemcpy->isVolatile(), + /*CanOverlap=*/false, // SrcAddr & DstAddr may not overlap by spec. + /*TTI=*/TTI, + /*AtomicElementSize=*/AtomicMemcpy->getElementSizeInBytes()); } else { createMemCpyLoopUnknownSize( - /* InsertBefore */ AtomicMemcpy, - /* SrcAddr */ AtomicMemcpy->getRawSource(), - /* DstAddr */ AtomicMemcpy->getRawDest(), - /* CopyLen */ AtomicMemcpy->getLength(), - /* SrcAlign */ AtomicMemcpy->getSourceAlign().valueOrOne(), - /* DestAlign */ AtomicMemcpy->getDestAlign().valueOrOne(), - /* SrcIsVolatile */ AtomicMemcpy->isVolatile(), - /* DstIsVolatile */ AtomicMemcpy->isVolatile(), - /* CanOverlap */ false, // SrcAddr & DstAddr may not overlap by spec. - /* TargetTransformInfo */ TTI, - /* AtomicElementSize */ AtomicMemcpy->getElementSizeInBytes()); + /*InsertBefore=*/AtomicMemcpy, + /*SrcAddr=*/AtomicMemcpy->getRawSource(), + /*DstAddr=*/AtomicMemcpy->getRawDest(), + /*CopyLen=*/AtomicMemcpy->getLength(), + /*SrcAlign=*/AtomicMemcpy->getSourceAlign().valueOrOne(), + /*DstAlign=*/AtomicMemcpy->getDestAlign().valueOrOne(), + /*SrcIsVolatile=*/AtomicMemcpy->isVolatile(), + /*DstIsVolatile=*/AtomicMemcpy->isVolatile(), + /*CanOverlap=*/false, // SrcAddr & DstAddr may not overlap by spec. + /*TargetTransformInfo=*/TTI, + /*AtomicElementSize=*/AtomicMemcpy->getElementSizeInBytes()); } } diff --git a/llvm/lib/Transforms/Utils/PredicateInfo.cpp b/llvm/lib/Transforms/Utils/PredicateInfo.cpp index 79ef0a608b35e..a5fff94b60d18 100644 --- a/llvm/lib/Transforms/Utils/PredicateInfo.cpp +++ b/llvm/lib/Transforms/Utils/PredicateInfo.cpp @@ -365,7 +365,7 @@ void PredicateInfoBuilder::processAssume( if (II->hasOperandBundles()) { for (auto BOI : II->bundle_op_infos()) { if (RetainedKnowledge RK = getKnowledgeFromBundle(*II, BOI)) { - if (RK.AttrKind == Attribute::NonNull) + if (RK.AttrKind == Attribute::NonNull && shouldRename(RK.WasOn)) addInfoFor(OpsToRename, RK.WasOn, new (Allocator) PredicateBundleAssume(RK.WasOn, II, Attribute::NonNull)); diff --git a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp index cccb944618e07..84562ecfcffe8 100644 --- a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp +++ b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp @@ -1254,6 +1254,22 @@ Value *SCEVExpander::tryToReuseLCSSAPhi(const SCEVAddRecExpr *S) { !SE.DT.dominates(EB, Builder.GetInsertBlock())) return nullptr; + // Helper to check if the diff between S and ExitSCEV is simple enough to + // allow reusing the LCSSA phi. + auto CanReuse = [&](const SCEV *ExitSCEV) -> const SCEV * { + if (isa(ExitSCEV)) + return nullptr; + const SCEV *Diff = SE.getMinusSCEV(S, ExitSCEV); + const SCEV *Op = Diff; + match(Op, m_scev_Add(m_SCEVConstant(), m_SCEV(Op))); + match(Op, m_scev_Mul(m_scev_AllOnes(), m_SCEV(Op))); + match(Op, m_scev_PtrToAddr(m_SCEV(Op))) || + match(Op, m_scev_PtrToInt(m_SCEV(Op))); + if (!isa(Op)) + return nullptr; + return Diff; + }; + for (auto &PN : EB->phis()) { if (!SE.isSCEVable(PN.getType())) continue; @@ -1261,22 +1277,20 @@ Value *SCEVExpander::tryToReuseLCSSAPhi(const SCEVAddRecExpr *S) { if (!isa(ExitSCEV)) continue; Type *PhiTy = PN.getType(); - if (STy->isIntegerTy() && PhiTy->isPointerTy()) { - ExitSCEV = SE.getPtrToIntExpr(ExitSCEV, STy); - if (isa(ExitSCEV)) - continue; - } else if (S->getType() != PN.getType()) { - continue; + const SCEV *Diff = nullptr; + if (STy->isIntegerTy() && PhiTy->isPointerTy() && + DL.getAddressType(PhiTy) == STy) { + // Prefer ptrtoaddr over ptrtoint. + const SCEV *AddrSCEV = SE.getPtrToAddrExpr(ExitSCEV); + Diff = CanReuse(AddrSCEV); + if (!Diff) { + const SCEV *IntSCEV = SE.getPtrToIntExpr(ExitSCEV, STy); + Diff = CanReuse(IntSCEV); + } + } else if (STy == PhiTy) { + Diff = CanReuse(ExitSCEV); } - - // Check if we can re-use the existing PN, by adjusting it with an expanded - // offset, if the offset is simpler. - const SCEV *Diff = SE.getMinusSCEV(S, ExitSCEV); - const SCEV *Op = Diff; - match(Op, m_scev_Add(m_SCEVConstant(), m_SCEV(Op))); - match(Op, m_scev_Mul(m_scev_AllOnes(), m_SCEV(Op))); - match(Op, m_scev_PtrToInt(m_SCEV(Op))); - if (!isa(Op)) + if (!Diff) continue; assert(Diff->getType()->isIntegerTy() && @@ -1286,7 +1300,7 @@ Value *SCEVExpander::tryToReuseLCSSAPhi(const SCEVAddRecExpr *S) { if (PhiTy->isPointerTy()) { if (STy->isPointerTy()) return Builder.CreatePtrAdd(BaseV, DiffV); - BaseV = Builder.CreatePtrToInt(BaseV, DiffV->getType()); + BaseV = Builder.CreatePtrToAddr(BaseV); } return Builder.CreateAdd(BaseV, DiffV); } diff --git a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp index 1e8a184fc51b8..d3ba4018845dd 100644 --- a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp @@ -2015,10 +2015,11 @@ static Value *optimizeDoubleFP(CallInst *CI, IRBuilderBase &B, R = isBinary ? B.CreateIntrinsic(IID, B.getFloatTy(), V) : B.CreateIntrinsic(IID, B.getFloatTy(), V[0]); } else { - AttributeList CalleeAttrs = CalleeFn->getAttributes(); - R = isBinary ? emitBinaryFloatFnCall(V[0], V[1], TLI, CalleeName, B, - CalleeAttrs) - : emitUnaryFloatFnCall(V[0], TLI, CalleeName, B, CalleeAttrs); + AttributeList CallsiteAttrs = CI->getAttributes(); + R = isBinary + ? emitBinaryFloatFnCall(V[0], V[1], TLI, CalleeName, B, + CallsiteAttrs) + : emitUnaryFloatFnCall(V[0], TLI, CalleeName, B, CallsiteAttrs); } return B.CreateFPExt(R, B.getDoubleTy()); } @@ -2520,17 +2521,8 @@ Value *LibCallSimplifier::optimizeExp2(CallInst *CI, IRBuilderBase &B) { return Ret; } -Value *LibCallSimplifier::optimizeFMinFMax(CallInst *CI, IRBuilderBase &B) { - Module *M = CI->getModule(); - - // If we can shrink the call to a float function rather than a double - // function, do that first. - Function *Callee = CI->getCalledFunction(); - StringRef Name = Callee->getName(); - if ((Name == "fmin" || Name == "fmax") && hasFloatVersion(M, Name)) - if (Value *Ret = optimizeBinaryDoubleFP(CI, B, TLI)) - return Ret; - +Value *LibCallSimplifier::optimizeFMinFMax(CallInst *CI, IRBuilderBase &B, + Intrinsic::ID IID) { // The LLVM intrinsics minnum/maxnum correspond to fmin/fmax. Canonicalize to // the intrinsics for improved optimization (for example, vectorization). // No-signed-zeros is implied by the definitions of fmax/fmin themselves. @@ -2540,9 +2532,6 @@ Value *LibCallSimplifier::optimizeFMinFMax(CallInst *CI, IRBuilderBase &B) { // might be impractical." FastMathFlags FMF = CI->getFastMathFlags(); FMF.setNoSignedZeros(); - - Intrinsic::ID IID = Callee->getName().starts_with("fmin") ? Intrinsic::minnum - : Intrinsic::maxnum; return copyFlags(*CI, B.CreateBinaryIntrinsic(IID, CI->getArgOperand(0), CI->getArgOperand(1), FMF)); } @@ -4147,10 +4136,11 @@ Value *LibCallSimplifier::optimizeFloatingPointLibCall(CallInst *CI, case LibFunc_fminf: case LibFunc_fmin: case LibFunc_fminl: + return optimizeFMinFMax(CI, Builder, Intrinsic::minnum); case LibFunc_fmaxf: case LibFunc_fmax: case LibFunc_fmaxl: - return optimizeFMinFMax(CI, Builder); + return optimizeFMinFMax(CI, Builder, Intrinsic::maxnum); case LibFunc_fminimum_numf: case LibFunc_fminimum_num: case LibFunc_fminimum_numl: diff --git a/llvm/lib/Transforms/Utils/VNCoercion.cpp b/llvm/lib/Transforms/Utils/VNCoercion.cpp index c1bce01239dcc..03306daeeafce 100644 --- a/llvm/lib/Transforms/Utils/VNCoercion.cpp +++ b/llvm/lib/Transforms/Utils/VNCoercion.cpp @@ -6,16 +6,16 @@ #define DEBUG_TYPE "vncoerce" -namespace llvm { -namespace VNCoercion { +using namespace llvm; +using namespace VNCoercion; static bool isFirstClassAggregateOrScalableType(Type *Ty) { return Ty->isStructTy() || Ty->isArrayTy() || isa(Ty); } /// Return true if coerceAvailableValueToLoadType will succeed. -bool canCoerceMustAliasedValueToLoad(Value *StoredVal, Type *LoadTy, - Function *F) { +bool VNCoercion::canCoerceMustAliasedValueToLoad(Value *StoredVal, Type *LoadTy, + Function *F) { Type *StoredTy = StoredVal->getType(); if (StoredTy == LoadTy) return true; @@ -87,8 +87,10 @@ bool canCoerceMustAliasedValueToLoad(Value *StoredVal, Type *LoadTy, /// IRB is IRBuilder used to insert new instructions. /// /// If we can't do it, return null. -Value *coerceAvailableValueToLoadType(Value *StoredVal, Type *LoadedTy, - IRBuilderBase &Helper, Function *F) { +Value *VNCoercion::coerceAvailableValueToLoadType(Value *StoredVal, + Type *LoadedTy, + IRBuilderBase &Helper, + Function *F) { assert(canCoerceMustAliasedValueToLoad(StoredVal, LoadedTy, F) && "precondition violation - materialization can't fail"); const DataLayout &DL = F->getDataLayout(); @@ -231,8 +233,9 @@ static int analyzeLoadFromClobberingWrite(Type *LoadTy, Value *LoadPtr, /// This function is called when we have a /// memdep query of a load that ends up being a clobbering store. -int analyzeLoadFromClobberingStore(Type *LoadTy, Value *LoadPtr, - StoreInst *DepSI, const DataLayout &DL) { +int VNCoercion::analyzeLoadFromClobberingStore(Type *LoadTy, Value *LoadPtr, + StoreInst *DepSI, + const DataLayout &DL) { auto *StoredVal = DepSI->getValueOperand(); // Cannot handle reading from store of first-class aggregate or scalable type. @@ -252,8 +255,9 @@ int analyzeLoadFromClobberingStore(Type *LoadTy, Value *LoadPtr, /// This function is called when we have a /// memdep query of a load that ends up being clobbered by another load. See if /// the other load can feed into the second load. -int analyzeLoadFromClobberingLoad(Type *LoadTy, Value *LoadPtr, LoadInst *DepLI, - const DataLayout &DL) { +int VNCoercion::analyzeLoadFromClobberingLoad(Type *LoadTy, Value *LoadPtr, + LoadInst *DepLI, + const DataLayout &DL) { // Cannot handle reading from store of first-class aggregate or scalable type. if (isFirstClassAggregateOrScalableType(DepLI->getType())) return -1; @@ -266,8 +270,9 @@ int analyzeLoadFromClobberingLoad(Type *LoadTy, Value *LoadPtr, LoadInst *DepLI, return analyzeLoadFromClobberingWrite(LoadTy, LoadPtr, DepPtr, DepSize, DL); } -int analyzeLoadFromClobberingMemInst(Type *LoadTy, Value *LoadPtr, - MemIntrinsic *MI, const DataLayout &DL) { +int VNCoercion::analyzeLoadFromClobberingMemInst(Type *LoadTy, Value *LoadPtr, + MemIntrinsic *MI, + const DataLayout &DL) { // If the mem operation is a non-constant size, we can't handle it. ConstantInt *SizeCst = dyn_cast(MI->getLength()); if (!SizeCst) @@ -276,9 +281,9 @@ int analyzeLoadFromClobberingMemInst(Type *LoadTy, Value *LoadPtr, // If this is memset, we just need to see if the offset is valid in the size // of the memset.. - if (const auto *memset_inst = dyn_cast(MI)) { + if (const auto *Memset = dyn_cast(MI)) { if (DL.isNonIntegralPointerType(LoadTy->getScalarType())) { - auto *CI = dyn_cast(memset_inst->getValue()); + auto *CI = dyn_cast(Memset->getValue()); if (!CI || !CI->isZero()) return -1; } @@ -372,8 +377,8 @@ static Value *getStoreValueForLoadHelper(Value *SrcVal, unsigned Offset, return SrcVal; } -Value *getValueForLoad(Value *SrcVal, unsigned Offset, Type *LoadTy, - Instruction *InsertPt, Function *F) { +Value *VNCoercion::getValueForLoad(Value *SrcVal, unsigned Offset, Type *LoadTy, + Instruction *InsertPt, Function *F) { const DataLayout &DL = F->getDataLayout(); #ifndef NDEBUG TypeSize MinSrcValSize = DL.getTypeStoreSize(SrcVal->getType()); @@ -393,8 +398,9 @@ Value *getValueForLoad(Value *SrcVal, unsigned Offset, Type *LoadTy, return coerceAvailableValueToLoadType(SrcVal, LoadTy, Builder, F); } -Constant *getConstantValueForLoad(Constant *SrcVal, unsigned Offset, - Type *LoadTy, const DataLayout &DL) { +Constant *VNCoercion::getConstantValueForLoad(Constant *SrcVal, unsigned Offset, + Type *LoadTy, + const DataLayout &DL) { #ifndef NDEBUG unsigned SrcValSize = DL.getTypeStoreSize(SrcVal->getType()).getFixedValue(); unsigned LoadSize = DL.getTypeStoreSize(LoadTy).getFixedValue(); @@ -405,9 +411,10 @@ Constant *getConstantValueForLoad(Constant *SrcVal, unsigned Offset, /// This function is called when we have a /// memdep query of a load that ends up being a clobbering mem intrinsic. -Value *getMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset, - Type *LoadTy, Instruction *InsertPt, - const DataLayout &DL) { +Value *VNCoercion::getMemInstValueForLoad(MemIntrinsic *SrcInst, + unsigned Offset, Type *LoadTy, + Instruction *InsertPt, + const DataLayout &DL) { LLVMContext &Ctx = LoadTy->getContext(); uint64_t LoadSize = DL.getTypeSizeInBits(LoadTy).getFixedValue() / 8; IRBuilder<> Builder(InsertPt); @@ -453,8 +460,10 @@ Value *getMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset, DL); } -Constant *getConstantMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset, - Type *LoadTy, const DataLayout &DL) { +Constant *VNCoercion::getConstantMemInstValueForLoad(MemIntrinsic *SrcInst, + unsigned Offset, + Type *LoadTy, + const DataLayout &DL) { LLVMContext &Ctx = LoadTy->getContext(); uint64_t LoadSize = DL.getTypeSizeInBits(LoadTy).getFixedValue() / 8; @@ -476,5 +485,3 @@ Constant *getConstantMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset, return ConstantFoldLoadFromConstPtr(Src, LoadTy, APInt(IndexSize, Offset), DL); } -} // namespace VNCoercion -} // namespace llvm diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp index 44502ac143857..e6bb7bd076e4d 100644 --- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp @@ -380,10 +380,7 @@ class LoadStoreVectorizerLegacyPass : public FunctionPass { public: static char ID; - LoadStoreVectorizerLegacyPass() : FunctionPass(ID) { - initializeLoadStoreVectorizerLegacyPassPass( - *PassRegistry::getPassRegistry()); - } + LoadStoreVectorizerLegacyPass() : FunctionPass(ID) {} bool runOnFunction(Function &F) override; diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp index 1b000be130e49..e57e0cf636501 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp @@ -1746,8 +1746,9 @@ bool LoopVectorizationLegality::isVectorizableEarlyExitLoop() { } // Sort exiting blocks by dominance order to establish a clear chain. + DT->updateDFSNumbers(); llvm::sort(UncountableExitingBlocks, [this](BasicBlock *A, BasicBlock *B) { - return DT->properlyDominates(A, B); + return DT->getNode(A)->getDFSNumIn() < DT->getNode(B)->getDFSNumIn(); }); // Verify that exits form a strict dominance chain: each block must diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h index 44d4d92d4a7e2..0b8796f646ae3 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h +++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h @@ -211,21 +211,35 @@ class VPBuilder { VPRecipeWithIRFlags::DisjointFlagsTy(false), {}, DL, Name)); } + VPInstruction * + createAdd(VPValue *LHS, VPValue *RHS, DebugLoc DL = DebugLoc::getUnknown(), + const Twine &Name = "", + VPRecipeWithIRFlags::WrapFlagsTy WrapFlags = {false, false}) { + return createOverflowingOp(Instruction::Add, {LHS, RHS}, WrapFlags, DL, + Name); + } + + VPInstruction * + createSub(VPValue *LHS, VPValue *RHS, DebugLoc DL = DebugLoc::getUnknown(), + const Twine &Name = "", + VPRecipeWithIRFlags::WrapFlagsTy WrapFlags = {false, false}) { + return createOverflowingOp(Instruction::Sub, {LHS, RHS}, WrapFlags, DL, + Name); + } + VPInstruction *createLogicalAnd(VPValue *LHS, VPValue *RHS, DebugLoc DL = DebugLoc::getUnknown(), const Twine &Name = "") { return createNaryOp(VPInstruction::LogicalAnd, {LHS, RHS}, DL, Name); } - VPInstruction * - createSelect(VPValue *Cond, VPValue *TrueVal, VPValue *FalseVal, - DebugLoc DL = DebugLoc::getUnknown(), const Twine &Name = "", - std::optional FMFs = std::nullopt) { - if (!FMFs) - return createNaryOp(Instruction::Select, {Cond, TrueVal, FalseVal}, DL, - Name); + VPInstruction *createSelect(VPValue *Cond, VPValue *TrueVal, + VPValue *FalseVal, + DebugLoc DL = DebugLoc::getUnknown(), + const Twine &Name = "", + const VPIRFlags &Flags = {}) { return tryInsertInstruction(new VPInstruction( - Instruction::Select, {Cond, TrueVal, FalseVal}, *FMFs, {}, DL, Name)); + Instruction::Select, {Cond, TrueVal, FalseVal}, Flags, {}, DL, Name)); } /// Create a new ICmp VPInstruction with predicate \p Pred and operands \p A @@ -247,7 +261,8 @@ class VPBuilder { assert(Pred >= CmpInst::FIRST_FCMP_PREDICATE && Pred <= CmpInst::LAST_FCMP_PREDICATE && "invalid predicate"); return tryInsertInstruction( - new VPInstruction(Instruction::FCmp, {A, B}, Pred, {}, DL, Name)); + new VPInstruction(Instruction::FCmp, {A, B}, + VPIRFlags(Pred, FastMathFlags()), {}, DL, Name)); } VPInstruction *createPtrAdd(VPValue *Ptr, VPValue *Offset, @@ -274,9 +289,10 @@ class VPBuilder { GEPNoWrapFlags::none(), {}, DL, Name)); } - VPPhi *createScalarPhi(ArrayRef IncomingValues, DebugLoc DL, - const Twine &Name = "") { - return tryInsertInstruction(new VPPhi(IncomingValues, DL, Name)); + VPPhi *createScalarPhi(ArrayRef IncomingValues, + DebugLoc DL = DebugLoc::getUnknown(), + const Twine &Name = "", const VPIRFlags &Flags = {}) { + return tryInsertInstruction(new VPPhi(IncomingValues, Flags, DL, Name)); } VPValue *createElementCount(Type *Ty, ElementCount EC) { @@ -305,7 +321,15 @@ class VPBuilder { VPInstruction *createScalarCast(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy, DebugLoc DL, - const VPIRFlags &Flags = {}, + const VPIRMetadata &Metadata = {}) { + return tryInsertInstruction(new VPInstructionWithType( + Opcode, Op, ResultTy, VPIRFlags::getDefaultFlags(Opcode), Metadata, + DL)); + } + + VPInstruction *createScalarCast(Instruction::CastOps Opcode, VPValue *Op, + Type *ResultTy, DebugLoc DL, + const VPIRFlags &Flags, const VPIRMetadata &Metadata = {}) { return tryInsertInstruction( new VPInstructionWithType(Opcode, Op, ResultTy, Flags, Metadata, DL)); @@ -335,13 +359,8 @@ class VPBuilder { VPWidenCastRecipe *createWidenCast(Instruction::CastOps Opcode, VPValue *Op, Type *ResultTy) { - VPIRFlags Flags; - if (Opcode == Instruction::Trunc) - Flags = VPIRFlags::TruncFlagsTy(false, false); - else if (Opcode == Instruction::ZExt) - Flags = VPIRFlags::NonNegFlagsTy(false); - return tryInsertInstruction( - new VPWidenCastRecipe(Opcode, Op, ResultTy, nullptr, Flags)); + return tryInsertInstruction(new VPWidenCastRecipe( + Opcode, Op, ResultTy, nullptr, VPIRFlags::getDefaultFlags(Opcode))); } VPScalarIVStepsRecipe * @@ -631,8 +650,8 @@ class LoopVectorizationPlanner { /// legal to vectorize the loop. This method creates VPlans using VPRecipes. void buildVPlansWithVPRecipes(ElementCount MinVF, ElementCount MaxVF); - /// Add recipes to compute the final reduction result (ComputeFindIVResult, - /// ComputeAnyOfResult, ComputeReductionResult depending on the reduction) in + /// Add recipes to compute the final reduction result (ComputeAnyOfResult, + /// ComputeReductionResult depending on the reduction) in /// the middle block. Selects are introduced for reductions between the phi /// and users outside the vector region when folding the tail. void addReductionResultComputation(VPlanPtr &Plan, diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 383a74d420f4e..b5978c670dd94 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -1250,6 +1250,10 @@ class LoopVectorizationCostModel { getPredBlockCostDivisor(TargetTransformInfo::TargetCostKind CostKind, const BasicBlock *BB); + /// Returns true if an artificially high cost for emulated masked memrefs + /// should be used. + bool useEmulatedMaskMemRefHack(Instruction *I, ElementCount VF); + /// Return the costs for our two available strategies for lowering a /// div/rem operation which requires speculating at least one lane. /// First result is for scalarization (will be invalid for scalable @@ -1562,10 +1566,6 @@ class LoopVectorizationCostModel { InstructionCost getScalarizationOverhead(Instruction *I, ElementCount VF) const; - /// Returns true if an artificially high cost for emulated masked memrefs - /// should be used. - bool useEmulatedMaskMemRefHack(Instruction *I, ElementCount VF); - /// Map of scalar integer values to the smallest bitwidth they can be legally /// represented as. The vector equivalents of these values should be truncated /// to this type. @@ -6886,6 +6886,10 @@ unsigned VPCostContext::getPredBlockCostDivisor(BasicBlock *BB) const { return CM.getPredBlockCostDivisor(CostKind, BB); } +bool VPCostContext::useEmulatedMaskMemRefHack(Instruction *I, ElementCount VF) { + return CM.useEmulatedMaskMemRefHack(I, VF); +} + InstructionCost LoopVectorizationPlanner::precomputeCosts(VPlan &Plan, ElementCount VF, VPCostContext &CostCtx) const { @@ -6999,6 +7003,11 @@ LoopVectorizationPlanner::precomputeCosts(VPlan &Plan, ElementCount VF, Cost += BranchCost; } + // Don't apply special costs when instruction cost is forced to make sure the + // forced cost is used for each recipe. + if (ForceTargetInstructionCost.getNumOccurrences()) + return Cost; + // Pre-compute costs for instructions that are forced-scalar or profitable to // scalarize. Their costs will be computed separately in the legacy cost // model. @@ -7163,6 +7172,13 @@ static bool planContainsAdditionalSimplifications(VPlan &Plan, cast(R).getPredicate() != cast(UI)->getPredicate()) return true; + + // Recipes with underlying instructions being moved out of the loop + // region by LICM may cause discrepancies between the legacy cost model + // and the VPlan-based cost model. + if (!VPBB->getEnclosingLoopRegion()) + return true; + SeenInstrs.insert(UI); } } @@ -7697,9 +7713,9 @@ VPRecipeBase *VPRecipeBuilder::tryToWidenMemory(VPInstruction *VPI, if (!LoopVectorizationPlanner::getDecisionAndClampRange(WillWiden, Range)) return nullptr; - VPValue *Mask = nullptr; - if (Legal->isMaskRequired(I)) - Mask = getBlockInMask(Builder.getInsertBlock()); + // If a mask is not required, drop it - use unmasked version for safe loads. + // TODO: Determine if mask is needed in VPlan. + VPValue *Mask = Legal->isMaskRequired(I) ? VPI->getMask() : nullptr; // Determine if the pointer operand of the access is either consecutive or // reverse consecutive. @@ -7864,20 +7880,18 @@ VPSingleDefRecipe *VPRecipeBuilder::tryToWidenCall(VPInstruction *VPI, if (ShouldUseVectorCall) { if (MaskPos.has_value()) { // We have 2 cases that would require a mask: - // 1) The block needs to be predicated, either due to a conditional + // 1) The call needs to be predicated, either due to a conditional // in the scalar loop or use of an active lane mask with // tail-folding, and we use the appropriate mask for the block. - // 2) No mask is required for the block, but the only available - // vector variant at this VF requires a mask, so we synthesize an - // all-true mask. - VPValue *Mask = Legal->isMaskRequired(CI) - ? getBlockInMask(Builder.getInsertBlock()) - : Plan.getTrue(); + // 2) No mask is required for the call instruction, but the only + // available vector variant at this VF requires a mask, so we + // synthesize an all-true mask. + VPValue *Mask = VPI->isMasked() ? VPI->getMask() : Plan.getTrue(); Ops.insert(Ops.begin() + *MaskPos, Mask); } - Ops.push_back(VPI->getOperand(VPI->getNumOperands() - 1)); + Ops.push_back(VPI->getOperand(VPI->getNumOperandsWithoutMask() - 1)); return new VPWidenCallRecipe(CI, Variant, Ops, *VPI, *VPI, VPI->getDebugLoc()); } @@ -7911,8 +7925,8 @@ VPWidenRecipe *VPRecipeBuilder::tryToWiden(VPInstruction *VPI) { // If not provably safe, use a select to form a safe divisor before widening the // div/rem operation itself. Otherwise fall through to general handling below. if (CM.isPredicatedInst(I)) { - SmallVector Ops(VPI->operands()); - VPValue *Mask = getBlockInMask(Builder.getInsertBlock()); + SmallVector Ops(VPI->operandsWithoutMask()); + VPValue *Mask = VPI->getMask(); VPValue *One = Plan.getConstantInt(I->getType(), 1u); auto *SafeRHS = Builder.createSelect(Mask, Ops[1], One, VPI->getDebugLoc()); @@ -7940,10 +7954,10 @@ VPWidenRecipe *VPRecipeBuilder::tryToWiden(VPInstruction *VPI) { case Instruction::Sub: case Instruction::Xor: case Instruction::Freeze: - return new VPWidenRecipe(*I, VPI->operands(), *VPI, *VPI, + return new VPWidenRecipe(*I, VPI->operandsWithoutMask(), *VPI, *VPI, VPI->getDebugLoc()); case Instruction::ExtractValue: { - SmallVector NewOps(VPI->operands()); + SmallVector NewOps(VPI->operandsWithoutMask()); auto *EVI = cast(I); assert(EVI->getNumIndices() == 1 && "Expected one extractvalue index"); unsigned Idx = EVI->getIndices()[0]; @@ -7969,7 +7983,7 @@ VPHistogramRecipe *VPRecipeBuilder::tryToWidenHistogram(const HistogramInfo *HI, // In case of predicated execution (due to tail-folding, or conditional // execution, or both), pass the relevant mask. if (Legal->isMaskRequired(HI->Store)) - HGramOps.push_back(getBlockInMask(Builder.getInsertBlock())); + HGramOps.push_back(VPI->getMask()); return new VPHistogramRecipe(Opcode, HGramOps, VPI->getDebugLoc()); } @@ -8023,7 +8037,7 @@ VPReplicateRecipe *VPRecipeBuilder::handleReplication(VPInstruction *VPI, // added initially. Masked replicate recipes will later be placed under an // if-then construct to prevent side-effects. Generate recipes to compute // the block mask for this region. - BlockInMask = getBlockInMask(Builder.getInsertBlock()); + BlockInMask = VPI->getMask(); } // Note that there is some custom logic to mark some intrinsics as uniform @@ -8033,8 +8047,8 @@ VPReplicateRecipe *VPRecipeBuilder::handleReplication(VPInstruction *VPI, (Range.Start.isScalable() && isa(I))) && "Should not predicate a uniform recipe"); auto *Recipe = - new VPReplicateRecipe(I, VPI->operands(), IsUniform, BlockInMask, *VPI, - *VPI, VPI->getDebugLoc()); + new VPReplicateRecipe(I, VPI->operandsWithoutMask(), IsUniform, + BlockInMask, *VPI, *VPI, VPI->getDebugLoc()); return Recipe; } @@ -8072,8 +8086,9 @@ VPRecipeBuilder::tryToCreateWidenNonPhiRecipe(VPSingleDefRecipe *R, return nullptr; if (VPI->getOpcode() == Instruction::GetElementPtr) - return new VPWidenGEPRecipe(cast(Instr), R->operands(), - *VPI, VPI->getDebugLoc()); + return new VPWidenGEPRecipe(cast(Instr), + VPI->operandsWithoutMask(), *VPI, + VPI->getDebugLoc()); if (Instruction::isCast(VPI->getOpcode())) { auto *CI = cast(Instr); @@ -8215,14 +8230,13 @@ VPlanPtr LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes( // --------------------------------------------------------------------------- // Predicate and linearize the top-level loop region. // --------------------------------------------------------------------------- - auto BlockMaskCache = VPlanTransforms::introduceMasksAndLinearize( - *Plan, CM.foldTailByMasking()); + VPlanTransforms::introduceMasksAndLinearize(*Plan, CM.foldTailByMasking()); // --------------------------------------------------------------------------- // Construct wide recipes and apply predication for original scalar // VPInstructions in the loop. // --------------------------------------------------------------------------- - VPRecipeBuilder RecipeBuilder(*Plan, TLI, Legal, CM, Builder, BlockMaskCache); + VPRecipeBuilder RecipeBuilder(*Plan, TLI, Legal, CM, Builder); // Scan the body of the loop in a topological order to visit each basic block // after having visited its predecessor basic blocks. @@ -8232,9 +8246,6 @@ VPlanPtr LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes( auto *MiddleVPBB = Plan->getMiddleBlock(); VPBasicBlock::iterator MBIP = MiddleVPBB->getFirstNonPhi(); - // Mapping from VPValues in the initial plan to their widened VPValues. Needed - // temporarily to update created block masks. - DenseMap Old2New; // Collect blocks that need predication for in-loop reduction recipes. DenseSet BlocksNeedingPredication; @@ -8242,8 +8253,8 @@ VPlanPtr LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes( if (CM.blockNeedsPredicationForAnyReason(BB)) BlocksNeedingPredication.insert(BB); - VPlanTransforms::createInLoopReductionRecipes( - *Plan, BlockMaskCache, BlocksNeedingPredication, Range.Start); + VPlanTransforms::createInLoopReductionRecipes(*Plan, BlocksNeedingPredication, + Range.Start); // Now process all other blocks and instructions. for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly(RPOT)) { @@ -8272,8 +8283,8 @@ VPlanPtr LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes( // Only create recipe for the final invariant store of the reduction. if (Legal->isInvariantStoreOfReduction(SI)) { auto *Recipe = new VPReplicateRecipe( - SI, R.operands(), true /* IsUniform */, nullptr /*Mask*/, *VPI, - *VPI, VPI->getDebugLoc()); + SI, VPI->operandsWithoutMask(), true /* IsUniform */, + nullptr /*Mask*/, *VPI, *VPI, VPI->getDebugLoc()); Recipe->insertBefore(*MiddleVPBB, MBIP); } R.eraseFromParent(); @@ -8296,23 +8307,14 @@ VPlanPtr LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes( } if (Recipe->getNumDefinedValues() == 1) { VPI->replaceAllUsesWith(Recipe->getVPSingleValue()); - Old2New[VPI] = Recipe->getVPSingleValue(); } else { assert(Recipe->getNumDefinedValues() == 0 && "Unexpected multidef recipe"); - R.eraseFromParent(); } + R.eraseFromParent(); } } - // replaceAllUsesWith above may invalidate the block masks. Update them here. - // TODO: Include the masks as operands in the predicated VPlan directly - // to remove the need to keep a map of masks beyond the predication - // transform. - RecipeBuilder.updateBlockMaskCache(Old2New); - for (VPValue *Old : Old2New.keys()) - Old->getDefiningRecipe()->eraseFromParent(); - assert(isa(LoopRegion) && !LoopRegion->getEntryBasicBlock()->empty() && "entry block must be set to a VPRegionBlock having a non-empty entry " @@ -8331,6 +8333,10 @@ VPlanPtr LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes( addReductionResultComputation(Plan, RecipeBuilder, Range.Start); + // Optimize FindIV reductions to use sentinel-based approach when possible. + RUN_VPLAN_PASS(VPlanTransforms::optimizeFindIVReductions, *Plan, PSE, + *OrigLoop); + // Apply mandatory transformation to handle reductions with multiple in-loop // uses if possible, bail out otherwise. if (!RUN_VPLAN_PASS(VPlanTransforms::handleMultiUseReductions, *Plan)) @@ -8470,13 +8476,12 @@ void LoopVectorizationPlanner::addReductionResultComputation( auto *RR = dyn_cast(OrigExitingVPV->getDefiningRecipe()); if (!PhiR->isInLoop() && CM.foldTailByMasking() && (!RR || !RR->isPartialReduction())) { - VPValue *Cond = RecipeBuilder.getBlockInMask(PhiR->getParent()); - std::optional FMFs = - PhiTy->isFloatingPointTy() - ? std::make_optional(RdxDesc.getFastMathFlags()) - : std::nullopt; + VPValue *Cond = vputils::findHeaderMask(*Plan); + VPIRFlags Flags = PhiTy->isFloatingPointTy() + ? VPIRFlags(RdxDesc.getFastMathFlags()) + : VPIRFlags(); NewExitingVPV = - Builder.createSelect(Cond, OrigExitingVPV, PhiR, {}, "", FMFs); + Builder.createSelect(Cond, OrigExitingVPV, PhiR, {}, "", Flags); OrigExitingVPV->replaceUsesWithIf(NewExitingVPV, [](VPUser &U, unsigned) { using namespace VPlanPatternMatch; return match( @@ -8513,26 +8518,7 @@ void LoopVectorizationPlanner::addReductionResultComputation( return match(U, m_Select(m_VPValue(), m_VPValue(), m_VPValue())); })); } - if (RecurrenceDescriptor::isFindIVRecurrenceKind(RecurrenceKind)) { - VPValue *Start = PhiR->getStartValue(); - VPValue *Sentinel = Plan->getOrAddLiveIn(RdxDesc.getSentinelValue()); - RecurKind MinMaxKind; - bool IsSigned = - RecurrenceDescriptor::isSignedRecurrenceKind(RecurrenceKind); - if (RecurrenceDescriptor::isFindLastIVRecurrenceKind(RecurrenceKind)) - MinMaxKind = IsSigned ? RecurKind::SMax : RecurKind::UMax; - else - MinMaxKind = IsSigned ? RecurKind::SMin : RecurKind::UMin; - VPIRFlags Flags(MinMaxKind, /*IsOrdered=*/false, /*IsInLoop=*/false, - FastMathFlags()); - auto *ReducedIV = - Builder.createNaryOp(VPInstruction::ComputeReductionResult, - {NewExitingVPV}, Flags, ExitDL); - auto *Cmp = - Builder.createICmp(CmpInst::ICMP_NE, ReducedIV, Sentinel, ExitDL); - FinalReductionResult = cast( - Builder.createSelect(Cmp, ReducedIV, Start, ExitDL)); - } else if (AnyOfSelect) { + if (AnyOfSelect) { VPValue *Start = PhiR->getStartValue(); // NewVal is the non-phi operand of the select. VPValue *NewVal = AnyOfSelect->getOperand(1) == PhiR @@ -8633,13 +8619,6 @@ void LoopVectorizationPlanner::addReductionResultComputation( continue; } - if (RecurrenceDescriptor::isFindIVRecurrenceKind( - RdxDesc.getRecurrenceKind())) { - // Adjust the start value for FindFirstIV/FindLastIV recurrences to use - // the sentinel value after generating the ResumePhi recipe, which uses - // the original start value. - PhiR->setOperand(0, Plan->getOrAddLiveIn(RdxDesc.getSentinelValue())); - } RecurKind RK = RdxDesc.getRecurrenceKind(); if ((!RecurrenceDescriptor::isAnyOfRecurrenceKind(RK) && !RecurrenceDescriptor::isFindIVRecurrenceKind(RK) && @@ -9165,7 +9144,7 @@ static SmallVector preparePlanForEpilogueVectorLoop( "the canonical IV should only be used by its increment or " "ScalarIVSteps when resetting the start value"); VPBuilder Builder(Header, Header->getFirstNonPhi()); - VPInstruction *Add = Builder.createNaryOp(Instruction::Add, {IV, VPV}); + VPInstruction *Add = Builder.createAdd(IV, VPV); IV->replaceAllUsesWith(Add); Add->setOperand(0, IV); diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 11f56a26f1380..f89c22fafcf04 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -2100,12 +2100,16 @@ class slpvectorizer::BoUpSLP { VectorizableTree.front()->getVectorFactor()); } - /// Returns the opcode of the root node, or 0, if the root node is gather. + /// Returns true if the tree results in one of the reduced bitcasts variants. bool isReducedBitcastRoot() const { return VectorizableTree.front()->hasState() && (VectorizableTree.front()->CombinedOp == TreeEntry::ReducedBitcast || VectorizableTree.front()->CombinedOp == - TreeEntry::ReducedBitcastBSwap) && + TreeEntry::ReducedBitcastBSwap || + VectorizableTree.front()->CombinedOp == + TreeEntry::ReducedBitcastLoads || + VectorizableTree.front()->CombinedOp == + TreeEntry::ReducedBitcastBSwapLoads) && VectorizableTree.front()->State == TreeEntry::Vectorize; } @@ -2270,23 +2274,6 @@ class slpvectorizer::BoUpSLP { /// effectively than the base graph. bool isTreeNotExtendable() const; - /// Assume that a legal-sized 'or'-reduction of shifted/zexted loaded values - /// can be load combined in the backend. Load combining may not be allowed in - /// the IR optimizer, so we do not want to alter the pattern. For example, - /// partially transforming a scalar bswap() pattern into vector code is - /// effectively impossible for the backend to undo. - /// TODO: If load combining is allowed in the IR optimizer, this analysis - /// may not be necessary. - bool isLoadCombineReductionCandidate(RecurKind RdxKind) const; - - /// Assume that a vector of stores of bitwise-or/shifted/zexted loaded values - /// can be load combined in the backend. Load combining may not be allowed in - /// the IR optimizer, so we do not want to alter the pattern. For example, - /// partially transforming a scalar bswap() pattern into vector code is - /// effectively impossible for the backend to undo. - /// TODO: If load combining is allowed in the IR optimizer, this analysis - /// may not be necessary. - bool isLoadCombineCandidate(ArrayRef Stores) const; bool isStridedLoad(ArrayRef PointerOps, Type *ScalarTy, Align Alignment, const int64_t Diff, const size_t Sz) const; @@ -3932,8 +3919,9 @@ class slpvectorizer::BoUpSLP { /// .., 56))-like pattern. /// If the int shifts unique, also strided, but not ordered, sets \p Order. /// If the node can be represented as a bitcast + bswap, sets \p IsBSwap. - bool matchesShlZExt(const TreeEntry &TE, OrdersType &Order, - bool &IsBSwap) const; + /// If the root nodes are loads, sets \p ForLoads to true. + bool matchesShlZExt(const TreeEntry &TE, OrdersType &Order, bool &IsBSwap, + bool &ForLoads) const; class TreeEntry { public: @@ -4066,6 +4054,8 @@ class slpvectorizer::BoUpSLP { FMulAdd, ReducedBitcast, ReducedBitcastBSwap, + ReducedBitcastLoads, + ReducedBitcastBSwapLoads, }; CombinedOpcode CombinedOp = NotCombinedOp; @@ -13353,10 +13343,11 @@ static InstructionCost canConvertToFMA(ArrayRef VL, } bool BoUpSLP::matchesShlZExt(const TreeEntry &TE, OrdersType &Order, - bool &IsBSwap) const { + bool &IsBSwap, bool &ForLoads) const { assert(TE.hasState() && TE.getOpcode() == Instruction::Shl && "Expected Shl node."); IsBSwap = false; + ForLoads = false; if (TE.State != TreeEntry::Vectorize || !TE.ReorderIndices.empty() || !TE.ReuseShuffleIndices.empty() || MinBWs.contains(&TE) || any_of(TE.Scalars, [](Value *V) { return !V->hasOneUse(); })) @@ -13463,6 +13454,44 @@ bool BoUpSLP::matchesShlZExt(const TreeEntry &TE, OrdersType &Order, if (BSwapCost <= BitcastCost) { BitcastCost = BSwapCost; IsBSwap = true; + Order.clear(); + // Check for loads in the ZExt node. + const TreeEntry *SrcTE = getOperandEntry(LhsTE, /*Idx=*/0); + if (SrcTE->State == TreeEntry::Vectorize && + SrcTE->ReorderIndices.empty() && SrcTE->ReuseShuffleIndices.empty() && + SrcTE->getOpcode() == Instruction::Load && !SrcTE->isAltShuffle() && + all_of(SrcTE->Scalars, [](Value *V) { return V->hasOneUse(); })) { + auto *LI = cast(SrcTE->getMainOp()); + IntrinsicCostAttributes CostAttrs(Intrinsic::bswap, ScalarTy, + {ScalarTy}); + InstructionCost BSwapCost = + TTI->getMemoryOpCost(Instruction::Load, ScalarTy, LI->getAlign(), + LI->getPointerAddressSpace(), CostKind) + + TTI->getIntrinsicInstrCost(CostAttrs, CostKind); + if (BSwapCost <= BitcastCost) { + VecCost += + TTI->getMemoryOpCost(Instruction::Load, SrcVecTy, LI->getAlign(), + LI->getPointerAddressSpace(), CostKind); + BitcastCost = BSwapCost; + ForLoads = true; + } + } + } + } else if (Order.empty() && DL->getTypeSizeInBits(SrcScalarTy) == ByteSize) { + // Check for loads in the ZExt node. + const TreeEntry *SrcTE = getOperandEntry(LhsTE, /*Idx=*/0); + if (SrcTE->State == TreeEntry::Vectorize && SrcTE->ReorderIndices.empty() && + SrcTE->ReuseShuffleIndices.empty() && + SrcTE->getOpcode() == Instruction::Load && !SrcTE->isAltShuffle() && + all_of(SrcTE->Scalars, [](Value *V) { return V->hasOneUse(); })) { + auto *LI = cast(SrcTE->getMainOp()); + BitcastCost = + TTI->getMemoryOpCost(Instruction::Load, ScalarTy, LI->getAlign(), + LI->getPointerAddressSpace(), CostKind); + VecCost += + TTI->getMemoryOpCost(Instruction::Load, SrcVecTy, LI->getAlign(), + LI->getPointerAddressSpace(), CostKind); + ForLoads = true; } } return BitcastCost < VecCost; @@ -13873,7 +13902,7 @@ void BoUpSLP::transformNodes() { break; } case Instruction::Shl: { - if (E.Idx != 0) + if (E.Idx != 0 || DL->isBigEndian()) break; if (!UserIgnoreList) break; @@ -13884,14 +13913,17 @@ void BoUpSLP::transformNodes() { break; OrdersType Order; bool IsBSwap; - if (!matchesShlZExt(E, Order, IsBSwap)) + bool ForLoads; + if (!matchesShlZExt(E, Order, IsBSwap, ForLoads)) break; // This node is a (reduced disjoint or) bitcast node. TreeEntry::CombinedOpcode Code = - IsBSwap ? TreeEntry::ReducedBitcastBSwap : TreeEntry::ReducedBitcast; + IsBSwap ? (ForLoads ? TreeEntry::ReducedBitcastBSwapLoads + : TreeEntry::ReducedBitcastBSwap) + : (ForLoads ? TreeEntry::ReducedBitcastLoads + : TreeEntry::ReducedBitcast); E.CombinedOp = Code; - if (!IsBSwap) - E.ReorderIndices = std::move(Order); + E.ReorderIndices = std::move(Order); TreeEntry *ZExtEntry = getOperandEntry(&E, 0); assert(ZExtEntry->UserTreeIndex && ZExtEntry->State == TreeEntry::Vectorize && @@ -13900,6 +13932,16 @@ void BoUpSLP::transformNodes() { // The ZExt node is part of the combined node. ZExtEntry->State = TreeEntry::CombinedVectorize; ZExtEntry->CombinedOp = Code; + if (ForLoads) { + TreeEntry *LoadsEntry = getOperandEntry(ZExtEntry, 0); + assert(LoadsEntry->UserTreeIndex && + LoadsEntry->State == TreeEntry::Vectorize && + LoadsEntry->getOpcode() == Instruction::Load && + "Expected Load node."); + // The Load node is part of the combined node. + LoadsEntry->State = TreeEntry::CombinedVectorize; + LoadsEntry->CombinedOp = Code; + } TreeEntry *ConstEntry = getOperandEntry(&E, 1); assert(ConstEntry->UserTreeIndex && ConstEntry->isGather() && "Expected ZExt node."); @@ -15559,6 +15601,44 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, }; return GetCostDiff(GetScalarCost, GetVectorCost); } + case TreeEntry::ReducedBitcastLoads: + case TreeEntry::ReducedBitcastBSwapLoads: { + auto GetScalarCost = [&, &TTI = *TTI](unsigned Idx) { + if (isa(UniqueValues[Idx])) + return InstructionCost(TTI::TCC_Free); + auto *Shl = dyn_cast(UniqueValues[Idx]); + if (!Shl) + return InstructionCost(TTI::TCC_Free); + InstructionCost ScalarCost = TTI.getInstructionCost(Shl, CostKind); + auto *ZExt = dyn_cast(Shl->getOperand(0)); + if (!ZExt) + return ScalarCost; + ScalarCost += TTI.getInstructionCost(ZExt, CostKind); + auto *Load = dyn_cast(ZExt->getOperand(0)); + if (!Load) + return ScalarCost; + ScalarCost += TTI.getInstructionCost(Load, CostKind); + return ScalarCost; + }; + auto GetVectorCost = [&, &TTI = *TTI](InstructionCost CommonCost) { + const TreeEntry *LhsTE = getOperandEntry(E, /*Idx=*/0); + const TreeEntry *LoadTE = getOperandEntry(LhsTE, /*Idx=*/0); + auto *LI0 = cast(LoadTE->getMainOp()); + auto *OrigScalarTy = E->getMainOp()->getType(); + InstructionCost LoadCost = + TTI.getMemoryOpCost(Instruction::Load, OrigScalarTy, LI0->getAlign(), + LI0->getPointerAddressSpace(), CostKind); + if (ShuffleOrOp == TreeEntry::ReducedBitcastBSwapLoads) { + IntrinsicCostAttributes CostAttrs(Intrinsic::bswap, OrigScalarTy, + {OrigScalarTy}); + InstructionCost IntrinsicCost = + TTI.getIntrinsicInstrCost(CostAttrs, CostKind); + LoadCost += IntrinsicCost; + } + return LoadCost + CommonCost; + }; + return GetCostDiff(GetScalarCost, GetVectorCost); + } case Instruction::FNeg: case Instruction::Add: case Instruction::FAdd: @@ -16043,69 +16123,6 @@ bool BoUpSLP::isFullyVectorizableTinyTree(bool ForReduction) const { return true; } -static bool isLoadCombineCandidateImpl(Value *Root, unsigned NumElts, - TargetTransformInfo *TTI, - bool MustMatchOrInst) { - // Look past the root to find a source value. Arbitrarily follow the - // path through operand 0 of any 'or'. Also, peek through optional - // shift-left-by-multiple-of-8-bits. - Value *ZextLoad = Root; - const APInt *ShAmtC; - bool FoundOr = false; - while (!isa(ZextLoad) && - (match(ZextLoad, m_Or(m_Value(), m_Value())) || - (match(ZextLoad, m_Shl(m_Value(), m_APInt(ShAmtC))) && - ShAmtC->urem(8) == 0))) { - auto *BinOp = cast(ZextLoad); - ZextLoad = BinOp->getOperand(0); - if (BinOp->getOpcode() == Instruction::Or) - FoundOr = true; - } - // Check if the input is an extended load of the required or/shift expression. - Value *Load; - if ((MustMatchOrInst && !FoundOr) || ZextLoad == Root || - !match(ZextLoad, m_ZExt(m_Value(Load))) || !isa(Load)) - return false; - - // Require that the total load bit width is a legal integer type. - // For example, <8 x i8> --> i64 is a legal integer on a 64-bit target. - // But <16 x i8> --> i128 is not, so the backend probably can't reduce it. - Type *SrcTy = Load->getType(); - unsigned LoadBitWidth = SrcTy->getIntegerBitWidth() * NumElts; - if (!TTI->isTypeLegal(IntegerType::get(Root->getContext(), LoadBitWidth))) - return false; - - // Everything matched - assume that we can fold the whole sequence using - // load combining. - LLVM_DEBUG(dbgs() << "SLP: Assume load combining for tree starting at " - << *(cast(Root)) << "\n"); - - return true; -} - -bool BoUpSLP::isLoadCombineReductionCandidate(RecurKind RdxKind) const { - if (RdxKind != RecurKind::Or) - return false; - - unsigned NumElts = VectorizableTree[0]->Scalars.size(); - Value *FirstReduced = VectorizableTree[0]->Scalars[0]; - return isLoadCombineCandidateImpl(FirstReduced, NumElts, TTI, - /* MatchOr */ false); -} - -bool BoUpSLP::isLoadCombineCandidate(ArrayRef Stores) const { - // Peek through a final sequence of stores and check if all operations are - // likely to be load-combined. - unsigned NumElts = Stores.size(); - for (Value *Scalar : Stores) { - Value *X; - if (!match(Scalar, m_Store(m_Value(X), m_Value())) || - !isLoadCombineCandidateImpl(X, NumElts, TTI, /* MatchOr */ true)) - return false; - } - return true; -} - bool BoUpSLP::isTreeTinyAndNotFullyVectorizable(bool ForReduction) const { if (!DebugCounter::shouldExecute(VectorizedGraphs)) return true; @@ -16334,7 +16351,9 @@ InstructionCost BoUpSLP::getSpillCost() { SmallPtrSet ScalarOrPseudoEntries; for (const auto &TEPtr : VectorizableTree) { if (TEPtr->CombinedOp == TreeEntry::ReducedBitcast || - TEPtr->CombinedOp == TreeEntry::ReducedBitcastBSwap) { + TEPtr->CombinedOp == TreeEntry::ReducedBitcastBSwap || + TEPtr->CombinedOp == TreeEntry::ReducedBitcastLoads || + TEPtr->CombinedOp == TreeEntry::ReducedBitcastBSwapLoads) { ScalarOrPseudoEntries.insert(TEPtr.get()); continue; } @@ -20269,6 +20288,8 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E) { switch (E->CombinedOp) { case TreeEntry::ReducedBitcast: case TreeEntry::ReducedBitcastBSwap: + case TreeEntry::ReducedBitcastLoads: + case TreeEntry::ReducedBitcastBSwapLoads: ShuffleOrOp = E->CombinedOp; break; default: @@ -21236,6 +21257,31 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E) { ++NumVectorInstructions; return V; } + case TreeEntry::ReducedBitcastLoads: + case TreeEntry::ReducedBitcastBSwapLoads: { + assert(UserIgnoreList && "Expected reduction operations only."); + TreeEntry *ZExt = getOperandEntry(E, /*Idx=*/0); + TreeEntry *Load = getOperandEntry(ZExt, /*Idx=*/0); + setInsertPointAfterBundle(Load); + ZExt->VectorizedValue = PoisonValue::get(getWidenedType( + ZExt->getMainOp()->getType(), ZExt->getVectorFactor())); + TreeEntry *Const = getOperandEntry(E, /*Idx=*/1); + Const->VectorizedValue = PoisonValue::get(getWidenedType( + Const->Scalars.front()->getType(), Const->getVectorFactor())); + Load->VectorizedValue = PoisonValue::get(getWidenedType( + Load->getMainOp()->getType(), Load->getVectorFactor())); + LoadInst *LI = cast(Load->getMainOp()); + Value *PO = LI->getPointerOperand(); + Type *ScalarTy = ZExt->getMainOp()->getType(); + Value *V = Builder.CreateAlignedLoad(ScalarTy, PO, LI->getAlign()); + ++NumVectorInstructions; + if (ShuffleOrOp == TreeEntry::ReducedBitcastBSwapLoads) { + V = Builder.CreateUnaryIntrinsic(Intrinsic::bswap, V); + ++NumVectorInstructions; + } + E->VectorizedValue = V; + return V; + } default: llvm_unreachable("unknown inst"); } @@ -21260,10 +21306,15 @@ Value *BoUpSLP::vectorizeTree( // Cache last instructions for the nodes to avoid side effects, which may // appear during vectorization, like extra uses, etc. for (const std::unique_ptr &TE : VectorizableTree) { + // Need to generate insertion point for loads nodes of the bitcast/bswap + // ops. if (TE->isGather() || DeletedNodes.contains(TE.get()) || (TE->State == TreeEntry::CombinedVectorize && (TE->CombinedOp == TreeEntry::ReducedBitcast || - TE->CombinedOp == TreeEntry::ReducedBitcastBSwap))) + TE->CombinedOp == TreeEntry::ReducedBitcastBSwap || + ((TE->CombinedOp == TreeEntry::ReducedBitcastLoads || + TE->CombinedOp == TreeEntry::ReducedBitcastBSwapLoads) && + (!TE->hasState() || TE->getOpcode() != Instruction::Load))))) continue; (void)getLastInstructionInBundle(TE.get()); } @@ -21822,7 +21873,9 @@ Value *BoUpSLP::vectorizeTree( continue; if (Entry->CombinedOp == TreeEntry::ReducedBitcast || - Entry->CombinedOp == TreeEntry::ReducedBitcastBSwap) { + Entry->CombinedOp == TreeEntry::ReducedBitcastBSwap || + Entry->CombinedOp == TreeEntry::ReducedBitcastLoads || + Entry->CombinedOp == TreeEntry::ReducedBitcastBSwapLoads) { // Skip constant node if (!Entry->hasState()) { assert(allConstant(Entry->Scalars) && "Expected constants only."); @@ -24138,8 +24191,6 @@ SLPVectorizerPass::vectorizeStoreChain(ArrayRef Chain, BoUpSLP &R, return false; } } - if (R.isLoadCombineCandidate(Chain)) - return true; R.buildTree(Chain); // Check if tree tiny and store itself or its value is not vectorized. if (R.isTreeTinyAndNotFullyVectorizable()) { @@ -24480,8 +24531,6 @@ bool SLPVectorizerPass::vectorizeStores( // Mark the vectorized stores so that we don't vectorize them // again. VectorizedStores.insert_range(Slice); - // Mark the vectorized stores so that we don't vectorize them - // again. AnyProfitableGraph = RepeatChanged = Changed = true; // If we vectorized initial block, no need to try to vectorize // it again. @@ -24563,19 +24612,19 @@ bool SLPVectorizerPass::vectorizeStores( find_if(RangeSizes, IsNotVectorized)) + 1)); unsigned VF = bit_ceil(CandidateVFs.front()) * 2; - unsigned Limit = - getFloorFullVectorNumberOfElements(*TTI, StoreTy, MaxTotalNum); - CandidateVFs.clear(); - if (bit_floor(Limit) == VF) - CandidateVFs.push_back(Limit); if (VF > MaxTotalNum || VF >= StoresLimit) break; for (std::pair &P : RangeSizes) { if (P.first != 0) P.first = std::max(P.second, P.first); } - // Last attempt to vectorize max number of elements, if all previous + // Attempt again to vectorize even larger chains if all previous // attempts were unsuccessful because of the cost issues. + CandidateVFs.clear(); + unsigned Limit = + getFloorFullVectorNumberOfElements(*TTI, StoreTy, MaxTotalNum); + if (bit_floor(Limit) == VF && Limit != VF) + CandidateVFs.push_back(Limit); CandidateVFs.push_back(VF); } } @@ -25746,11 +25795,6 @@ class HorizontalReduction { V.analyzedReductionVals(VL); continue; } - if (V.isLoadCombineReductionCandidate(RdxKind)) { - if (!AdjustReducedVals()) - V.analyzedReductionVals(VL); - continue; - } V.reorderTopToBottom(); // No need to reorder the root node at all for reassociative reduction. V.reorderBottomToTop(/*IgnoreReorder=*/RdxFMF.allowReassoc() || @@ -26447,10 +26491,7 @@ class HorizontalReduction { case RecurKind::FMul: case RecurKind::FMulAdd: case RecurKind::AnyOf: - case RecurKind::FindFirstIVSMin: - case RecurKind::FindFirstIVUMin: - case RecurKind::FindLastIVSMax: - case RecurKind::FindLastIVUMax: + case RecurKind::FindIV: case RecurKind::FindLast: case RecurKind::FMaxNum: case RecurKind::FMinNum: @@ -26589,10 +26630,7 @@ class HorizontalReduction { case RecurKind::FMul: case RecurKind::FMulAdd: case RecurKind::AnyOf: - case RecurKind::FindFirstIVSMin: - case RecurKind::FindFirstIVUMin: - case RecurKind::FindLastIVSMax: - case RecurKind::FindLastIVUMax: + case RecurKind::FindIV: case RecurKind::FindLast: case RecurKind::FMaxNum: case RecurKind::FMinNum: @@ -26696,10 +26734,7 @@ class HorizontalReduction { case RecurKind::FMul: case RecurKind::FMulAdd: case RecurKind::AnyOf: - case RecurKind::FindFirstIVSMin: - case RecurKind::FindFirstIVUMin: - case RecurKind::FindLastIVSMax: - case RecurKind::FindLastIVUMax: + case RecurKind::FindIV: case RecurKind::FindLast: case RecurKind::FMaxNum: case RecurKind::FMinNum: diff --git a/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h b/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h index 3280fc4827239..64315df74dda5 100644 --- a/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h +++ b/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h @@ -38,11 +38,6 @@ class VPRecipeBuilder { VPBuilder &Builder; - /// The mask of each VPBB, generated earlier and used for predicating recipes - /// in VPBB. - /// TODO: remove by applying predication when generating the masks. - DenseMap &BlockMaskCache; - // VPlan construction support: Hold a mapping from ingredients to // their recipe. DenseMap Ingredient2Recipe; @@ -87,10 +82,8 @@ class VPRecipeBuilder { public: VPRecipeBuilder(VPlan &Plan, const TargetLibraryInfo *TLI, LoopVectorizationLegality *Legal, - LoopVectorizationCostModel &CM, VPBuilder &Builder, - DenseMap &BlockMaskCache) - : Plan(Plan), TLI(TLI), Legal(Legal), CM(CM), Builder(Builder), - BlockMaskCache(BlockMaskCache) {} + LoopVectorizationCostModel &CM, VPBuilder &Builder) + : Plan(Plan), TLI(TLI), Legal(Legal), CM(CM), Builder(Builder) {} /// Create and return a widened recipe for a non-phi recipe \p R if one can be /// created within the given VF \p Range. @@ -104,12 +97,6 @@ class VPRecipeBuilder { Ingredient2Recipe[I] = R; } - /// Returns the *entry* mask for block \p VPBB or null if the mask is - /// all-true. - VPValue *getBlockInMask(VPBasicBlock *VPBB) const { - return BlockMaskCache.lookup(VPBB); - } - /// Return the recipe created for given ingredient. VPRecipeBase *getRecipe(Instruction *I) { assert(Ingredient2Recipe.count(I) && @@ -131,15 +118,6 @@ class VPRecipeBuilder { } return Plan.getOrAddLiveIn(V); } - - void updateBlockMaskCache(DenseMap &Old2New) { - for (auto &[_, V] : BlockMaskCache) { - if (auto *New = Old2New.lookup(V)) { - V->replaceAllUsesWith(New); - V = New; - } - } - } }; } // end namespace llvm diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index ae6988d86e194..eac5b58841e80 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -705,6 +705,7 @@ class VPIRFlags { private: struct ExactFlagsTy { char IsExact : 1; + ExactFlagsTy(bool Exact) : IsExact(Exact) {} }; struct FastMathFlagsTy { char AllowReassoc : 1; @@ -816,6 +817,9 @@ class VPIRFlags { VPIRFlags(NonNegFlagsTy NonNegFlags) : OpType(OperationType::NonNegOp), NonNegFlags(NonNegFlags) {} + VPIRFlags(ExactFlagsTy ExactFlags) + : OpType(OperationType::PossiblyExactOp), ExactFlags(ExactFlags) {} + VPIRFlags(GEPNoWrapFlags GEPFlags) : OpType(OperationType::GEPOp), GEPFlags(GEPFlags) {} @@ -1015,9 +1019,17 @@ class VPIRFlags { } public: + /// Returns default flags for \p Opcode for opcodes that support it, asserts + /// otherwise. Opcodes not supporting default flags include compares and + /// ComputeReductionResult. + static VPIRFlags getDefaultFlags(unsigned Opcode); + #if !defined(NDEBUG) /// Returns true if the set flags are valid for \p Opcode. LLVM_ABI_FOR_TEST bool flagsValidForOpcode(unsigned Opcode) const; + + /// Returns true if \p Opcode has its required flags set. + LLVM_ABI_FOR_TEST bool hasRequiredFlagsForOpcode(unsigned Opcode) const; #endif #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) @@ -1034,7 +1046,8 @@ struct VPRecipeWithIRFlags : public VPSingleDefRecipe, public VPIRFlags { : VPSingleDefRecipe(SC, Operands, DL), VPIRFlags(Flags) {} static inline bool classof(const VPRecipeBase *R) { - return R->getVPRecipeID() == VPRecipeBase::VPInstructionSC || + return R->getVPRecipeID() == VPRecipeBase::VPBlendSC || + R->getVPRecipeID() == VPRecipeBase::VPInstructionSC || R->getVPRecipeID() == VPRecipeBase::VPWidenSC || R->getVPRecipeID() == VPRecipeBase::VPWidenGEPSC || R->getVPRecipeID() == VPRecipeBase::VPWidenCallSC || @@ -1135,7 +1148,9 @@ class VPIRMetadata { /// This is a concrete Recipe that models a single VPlan-level instruction. /// While as any Recipe it may generate a sequence of IR instructions when /// executed, these instructions would always form a single-def expression as -/// the VPInstruction is also a single def-use vertex. +/// the VPInstruction is also a single def-use vertex. Most VPInstruction +/// opcodes can take an optional mask. Masks may be assigned during +/// predication. class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags, public VPIRMetadata, public VPUnrollPartAccessor<1> { @@ -1250,7 +1265,12 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags, /// Returns the value for vscale. VScale, - OpsEnd = VScale, + /// Compute the exiting value of a wide induction after vectorization, that + /// is the value of the last lane of the induction increment (i.e. its + /// backedge value). Takes the wide induction recipe and the original + /// backedge value as operands. + ExitingIVValue, + OpsEnd = ExitingIVValue, }; /// Returns true if this VPInstruction generates scalar values for all lanes. @@ -1262,9 +1282,9 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags, bool doesGeneratePerAllLanes() const; /// Return the number of operands determined by the opcode of the - /// VPInstruction. Returns -1u if the number of operands cannot be determined - /// directly by the opcode. - static unsigned getNumOperandsForOpcode(unsigned Opcode); + /// VPInstruction, excluding mask. Returns -1u if the number of operands + /// cannot be determined directly by the opcode. + unsigned getNumOperandsForOpcode() const; private: typedef unsigned char OpcodeTy; @@ -1282,6 +1302,16 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags, /// existing value is returned rather than a generated one. Value *generate(VPTransformState &State); + /// Returns true if the VPInstruction does not need masking. + bool alwaysUnmasked() const { + // For now only VPInstructions with underlying values use masks. + // TODO: provide masks to VPInstructions w/o underlying values. + if (!getUnderlyingValue()) + return true; + + return Opcode == Instruction::PHI || Opcode == Instruction::GetElementPtr; + } + public: VPInstruction(unsigned Opcode, ArrayRef Operands, const VPIRFlags &Flags = {}, const VPIRMetadata &MD = {}, @@ -1336,6 +1366,44 @@ class LLVM_ABI_FOR_TEST VPInstruction : public VPRecipeWithIRFlags, } } + /// Returns true if the VPInstruction has a mask operand. + bool isMasked() const { + unsigned NumOpsForOpcode = getNumOperandsForOpcode(); + // VPInstructions without a fixed number of operands cannot be masked. + if (NumOpsForOpcode == -1u) + return false; + return NumOpsForOpcode + 1 == getNumOperands(); + } + + /// Returns the number of operands, excluding the mask if the VPInstruction is + /// masked. + unsigned getNumOperandsWithoutMask() const { + return getNumOperands() - isMasked(); + } + + /// Add mask \p Mask to an unmasked VPInstruction, if it needs masking. + void addMask(VPValue *Mask) { + assert(!isMasked() && "recipe is already masked"); + if (alwaysUnmasked()) + return; + addOperand(Mask); + } + + /// Returns the mask for the VPInstruction. Returns nullptr for unmasked + /// VPInstructions. + VPValue *getMask() const { + return isMasked() ? getOperand(getNumOperands() - 1) : nullptr; + } + + /// Returns an iterator range over the operands excluding the mask operand + /// if present. + iterator_range operandsWithoutMask() { + return make_range(op_begin(), op_begin() + getNumOperandsWithoutMask()); + } + iterator_range operandsWithoutMask() const { + return make_range(op_begin(), op_begin() + getNumOperandsWithoutMask()); + } + /// Returns true if the underlying opcode may read from or write to memory. bool opcodeMayReadOrWriteFromMemory() const; @@ -1493,8 +1561,9 @@ class VPPhiAccessors { }; struct LLVM_ABI_FOR_TEST VPPhi : public VPInstruction, public VPPhiAccessors { - VPPhi(ArrayRef Operands, DebugLoc DL, const Twine &Name = "") - : VPInstruction(Instruction::PHI, Operands, {}, {}, DL, Name) {} + VPPhi(ArrayRef Operands, const VPIRFlags &Flags, DebugLoc DL, + const Twine &Name = "") + : VPInstruction(Instruction::PHI, Operands, Flags, {}, DL, Name) {} static inline bool classof(const VPUser *U) { auto *VPI = dyn_cast(U); @@ -1512,7 +1581,7 @@ struct LLVM_ABI_FOR_TEST VPPhi : public VPInstruction, public VPPhiAccessors { } VPPhi *clone() override { - auto *PhiR = new VPPhi(operands(), getDebugLoc(), getName()); + auto *PhiR = new VPPhi(operands(), *this, getDebugLoc(), getName()); PhiR->setUnderlyingValue(getUnderlyingValue()); return PhiR; } @@ -1539,8 +1608,7 @@ class VPIRInstruction : public VPRecipeBase { /// VPIRInstruction::create() should be used to create VPIRInstructions, as /// subclasses may need to be created, e.g. VPIRPhi. VPIRInstruction(Instruction &I) - : VPRecipeBase(VPRecipeBase::VPIRInstructionSC, ArrayRef()), - I(I) {} + : VPRecipeBase(VPRecipeBase::VPIRInstructionSC, {}), I(I) {} public: ~VPIRInstruction() override = default; @@ -1701,6 +1769,8 @@ class VPWidenCastRecipe : public VPRecipeWithIRFlags, public VPIRMetadata { VPIRMetadata(Metadata), Opcode(Opcode), ResultTy(ResultTy) { assert(flagsValidForOpcode(Opcode) && "Set flags not supported for the provided opcode"); + assert(hasRequiredFlagsForOpcode(Opcode) && + "Opcode requires specific flags to be set"); setUnderlyingValue(CI); } @@ -2006,8 +2076,8 @@ class VPVectorEndPointerRecipe : public VPRecipeWithIRFlags, public: VPVectorEndPointerRecipe(VPValue *Ptr, VPValue *VF, Type *SourceElementTy, int64_t Stride, GEPNoWrapFlags GEPFlags, DebugLoc DL) - : VPRecipeWithIRFlags(VPRecipeBase::VPVectorEndPointerSC, - ArrayRef({Ptr, VF}), GEPFlags, DL), + : VPRecipeWithIRFlags(VPRecipeBase::VPVectorEndPointerSC, {Ptr, VF}, + GEPFlags, DL), SourceElementTy(SourceElementTy), Stride(Stride) { assert(Stride < 0 && "Stride must be negative"); } @@ -2142,8 +2212,7 @@ class LLVM_ABI_FOR_TEST VPHeaderPHIRecipe : public VPSingleDefRecipe, protected: VPHeaderPHIRecipe(unsigned char VPRecipeID, Instruction *UnderlyingInstr, VPValue *Start, DebugLoc DL = DebugLoc::getUnknown()) - : VPSingleDefRecipe(VPRecipeID, ArrayRef({Start}), - UnderlyingInstr, DL) {} + : VPSingleDefRecipe(VPRecipeID, Start, UnderlyingInstr, DL) {} const VPRecipeBase *getAsRecipe() const override { return this; } @@ -2536,7 +2605,7 @@ class VPReductionPHIRecipe : public VPHeaderPHIRecipe, ReductionStyle Style; - /// The phi is part of a multi-use reduction (e.g., used in FindLastIV + /// The phi is part of a multi-use reduction (e.g., used in FindIV /// patterns for argmin/argmax). /// TODO: Also support cases where the phi itself has a single use, but its /// compare has multiple uses. @@ -2623,20 +2692,22 @@ class VPReductionPHIRecipe : public VPHeaderPHIRecipe, /// A recipe for vectorizing a phi-node as a sequence of mask-based select /// instructions. -class LLVM_ABI_FOR_TEST VPBlendRecipe : public VPSingleDefRecipe { +class LLVM_ABI_FOR_TEST VPBlendRecipe : public VPRecipeWithIRFlags { public: /// The blend operation is a User of the incoming values and of their /// respective masks, ordered [I0, M0, I1, M1, I2, M2, ...]. Note that M0 can /// be omitted (implied by passing an odd number of operands) in which case /// all other incoming values are merged into it. - VPBlendRecipe(PHINode *Phi, ArrayRef Operands, DebugLoc DL) - : VPSingleDefRecipe(VPRecipeBase::VPBlendSC, Operands, Phi, DL) { + VPBlendRecipe(PHINode *Phi, ArrayRef Operands, + const VPIRFlags &Flags, DebugLoc DL) + : VPRecipeWithIRFlags(VPRecipeBase::VPBlendSC, Operands, Flags, DL) { assert(Operands.size() >= 2 && "Expected at least two operands!"); + setUnderlyingValue(Phi); } VPBlendRecipe *clone() override { return new VPBlendRecipe(cast_or_null(getUnderlyingValue()), - operands(), getDebugLoc()); + operands(), *this, getDebugLoc()); } VP_CLASSOF_IMPL(VPRecipeBase::VPBlendSC) @@ -2788,9 +2859,8 @@ class LLVM_ABI_FOR_TEST VPInterleaveBase : public VPRecipeBase, /// Return the VPValues stored by this interleave group. If it is a load /// interleave group, return an empty ArrayRef. ArrayRef getStoredValues() const { - return ArrayRef(op_end() - - (getNumStoreOperands() + (HasMask ? 1 : 0)), - getNumStoreOperands()); + return {op_end() - (getNumStoreOperands() + (HasMask ? 1 : 0)), + getNumStoreOperands()}; } }; @@ -2843,10 +2913,10 @@ class LLVM_ABI_FOR_TEST VPInterleaveRecipe final : public VPInterleaveBase { class LLVM_ABI_FOR_TEST VPInterleaveEVLRecipe final : public VPInterleaveBase { public: VPInterleaveEVLRecipe(VPInterleaveRecipe &R, VPValue &EVL, VPValue *Mask) - : VPInterleaveBase( - VPRecipeBase::VPInterleaveEVLSC, R.getInterleaveGroup(), - ArrayRef({R.getAddr(), &EVL}), R.getStoredValues(), Mask, - R.needsMaskForGaps(), R, R.getDebugLoc()) { + : VPInterleaveBase(VPRecipeBase::VPInterleaveEVLSC, + R.getInterleaveGroup(), {R.getAddr(), &EVL}, + R.getStoredValues(), Mask, R.needsMaskForGaps(), R, + R.getDebugLoc()) { assert(!getInterleaveGroup()->isReverse() && "Reversed interleave-group with tail folding is not supported."); assert(!needsMaskForGaps() && "Interleaved access with gap mask is not " @@ -2918,15 +2988,13 @@ class LLVM_ABI_FOR_TEST VPReductionRecipe : public VPRecipeWithIRFlags { VPValue *ChainOp, VPValue *VecOp, VPValue *CondOp, ReductionStyle Style, DebugLoc DL = DebugLoc::getUnknown()) : VPReductionRecipe(VPRecipeBase::VPReductionSC, RdxKind, FMFs, I, - ArrayRef({ChainOp, VecOp}), CondOp, Style, - DL) {} + {ChainOp, VecOp}, CondOp, Style, DL) {} VPReductionRecipe(const RecurKind RdxKind, FastMathFlags FMFs, VPValue *ChainOp, VPValue *VecOp, VPValue *CondOp, ReductionStyle Style, DebugLoc DL = DebugLoc::getUnknown()) : VPReductionRecipe(VPRecipeBase::VPReductionSC, RdxKind, FMFs, nullptr, - ArrayRef({ChainOp, VecOp}), CondOp, Style, - DL) {} + {ChainOp, VecOp}, CondOp, Style, DL) {} ~VPReductionRecipe() override = default; @@ -3006,12 +3074,12 @@ class LLVM_ABI_FOR_TEST VPReductionEVLRecipe : public VPReductionRecipe { public: VPReductionEVLRecipe(VPReductionRecipe &R, VPValue &EVL, VPValue *CondOp, DebugLoc DL = DebugLoc::getUnknown()) - : VPReductionRecipe( - VPRecipeBase::VPReductionEVLSC, R.getRecurrenceKind(), - R.getFastMathFlags(), - cast_or_null(R.getUnderlyingValue()), - ArrayRef({R.getChainOp(), R.getVecOp(), &EVL}), CondOp, - getReductionStyle(/*InLoop=*/true, R.isOrdered(), 1), DL) {} + : VPReductionRecipe(VPRecipeBase::VPReductionEVLSC, R.getRecurrenceKind(), + R.getFastMathFlags(), + cast_or_null(R.getUnderlyingValue()), + {R.getChainOp(), R.getVecOp(), &EVL}, CondOp, + getReductionStyle(/*InLoop=*/true, R.isOrdered(), 1), + DL) {} ~VPReductionEVLRecipe() override = default; @@ -3910,8 +3978,8 @@ class LLVM_ABI_FOR_TEST VPScalarIVStepsRecipe : public VPRecipeWithIRFlags { VPScalarIVStepsRecipe(VPValue *IV, VPValue *Step, VPValue *VF, Instruction::BinaryOps Opcode, FastMathFlags FMFs, DebugLoc DL) - : VPRecipeWithIRFlags(VPRecipeBase::VPScalarIVStepsSC, - ArrayRef({IV, Step, VF}), FMFs, DL), + : VPRecipeWithIRFlags(VPRecipeBase::VPScalarIVStepsSC, {IV, Step, VF}, + FMFs, DL), InductionOpcode(Opcode) {} VPScalarIVStepsRecipe(const InductionDescriptor &IndDesc, VPValue *IV, diff --git a/llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp b/llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp index 8fbe7d93e6f45..4f97f8000c187 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp @@ -59,7 +59,8 @@ Type *VPTypeAnalysis::inferScalarTypeForRecipe(const VPInstruction *R) { // other operands match and cache them. auto SetResultTyFromOp = [this, R]() { Type *ResTy = inferScalarType(R->getOperand(0)); - for (unsigned Op = 1; Op != R->getNumOperands(); ++Op) { + unsigned NumOperands = R->getNumOperandsWithoutMask(); + for (unsigned Op = 1; Op != NumOperands; ++Op) { VPValue *OtherV = R->getOperand(Op); assert(inferScalarType(OtherV) == ResTy && "different types inferred for different operands"); @@ -78,6 +79,7 @@ Type *VPTypeAnalysis::inferScalarTypeForRecipe(const VPInstruction *R) { case Instruction::PHI: case VPInstruction::Broadcast: case VPInstruction::ComputeReductionResult: + case VPInstruction::ExitingIVValue: case VPInstruction::ExtractLastLane: case VPInstruction::ExtractPenultimateElement: case VPInstruction::ExtractLastPart: diff --git a/llvm/lib/Transforms/Vectorize/VPlanCFG.h b/llvm/lib/Transforms/Vectorize/VPlanCFG.h index c79485c4cea71..ec3016f700fc2 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanCFG.h +++ b/llvm/lib/Transforms/Vectorize/VPlanCFG.h @@ -25,90 +25,136 @@ namespace llvm { // GraphTraits specializations for VPlan Hierarchical Control-Flow Graphs // //===----------------------------------------------------------------------===// -/// Iterator to traverse all successors of a VPBlockBase node. This includes the -/// entry node of VPRegionBlocks. Exit blocks of a region implicitly have their -/// parent region's successors. This ensures all blocks in a region are visited -/// before any blocks in a successor region when doing a reverse post-order -// traversal of the graph. Region blocks themselves traverse only their entries -// directly and not their successors. Those will be traversed when a region's -// exiting block is traversed -template -class VPAllSuccessorsIterator - : public iterator_facade_base, - std::bidirectional_iterator_tag, - VPBlockBase> { +/// Iterator to traverse all successors/predecessors of a VPBlockBase node, +/// including its hierarchical successors/predecessors: +/// +/// A +/// | +/// +-----+ <- Region R +/// | b | +/// | | +/// | ... | +/// | | +/// | e | +/// +-----+ +/// | +/// B +/// +/// Forward == true: +/// Region blocks themselves traverse only their entries directly. +/// Region's successor is implictly traversed when processing its exiting +/// block. +/// children(A) == {R} +/// children(R) == {b} +/// children(e) == {B} +/// +/// Forward == false: +/// Region blocks themselves traverse only their exiting blocks directly. +/// Region's predecessor is implicitly traversed when processing its entry +/// block. +/// children(B) == {R} +/// children(R) == {e} +/// children(b) == {A} +/// +/// The scheme described above ensures that all blocks of the region are visited +/// before continuing traversal outside the region when doing a reverse +/// post-order traversal of the VPlan. +template +class VPHierarchicalChildrenIterator + : public iterator_facade_base< + VPHierarchicalChildrenIterator, + std::bidirectional_iterator_tag, VPBlockBase> { BlockPtrTy Block; - /// Index of the current successor. For VPBasicBlock nodes, this simply is the - /// index for the successor array. For VPRegionBlock, SuccessorIdx == 0 is - /// used for the region's entry block, and SuccessorIdx - 1 are the indices - /// for the successor array. - size_t SuccessorIdx; - - static BlockPtrTy getBlockWithSuccs(BlockPtrTy Current) { - while (Current && Current->getNumSuccessors() == 0) + /// Index of the current successor/predecessor. For VPBasicBlock nodes, this + /// simply is the index for the successors/predecessors array. For + /// VPRegionBlock, EdgeIdx == 0 is used for the region's entry/exiting block, + /// and EdgeIdx - 1 are the indices for the successors/predecessors array. + size_t EdgeIdx; + + static size_t getNumOutgoingEdges(BlockPtrTy Current) { + if constexpr (Forward) + return Current->getNumSuccessors(); + else + return Current->getNumPredecessors(); + } + + static ArrayRef getOutgoingEdges(BlockPtrTy Current) { + if constexpr (Forward) + return Current->getSuccessors(); + else + return Current->getPredecessors(); + } + + static BlockPtrTy getBlockWithOutgoingEdges(BlockPtrTy Current) { + while (Current && getNumOutgoingEdges(Current) == 0) Current = Current->getParent(); return Current; } - /// Templated helper to dereference successor \p SuccIdx of \p Block. Used by - /// both the const and non-const operator* implementations. - template static T1 deref(T1 Block, unsigned SuccIdx) { + /// Templated helper to dereference successor/predecessor \p EdgeIdx of \p + /// Block. Used by both the const and non-const operator* implementations. + template static T1 deref(T1 Block, unsigned EdgeIdx) { if (auto *R = dyn_cast(Block)) { - assert(SuccIdx == 0); - return R->getEntry(); + assert(EdgeIdx == 0); + if constexpr (Forward) + return R->getEntry(); + else + return R->getExiting(); } // For exit blocks, use the next parent region with successors. - return getBlockWithSuccs(Block)->getSuccessors()[SuccIdx]; + return getOutgoingEdges(getBlockWithOutgoingEdges(Block))[EdgeIdx]; } public: /// Used by iterator_facade_base with bidirectional_iterator_tag. using reference = BlockPtrTy; - VPAllSuccessorsIterator(BlockPtrTy Block, size_t Idx = 0) - : Block(Block), SuccessorIdx(Idx) {} - VPAllSuccessorsIterator(const VPAllSuccessorsIterator &Other) - : Block(Other.Block), SuccessorIdx(Other.SuccessorIdx) {} + VPHierarchicalChildrenIterator(BlockPtrTy Block, size_t Idx = 0) + : Block(Block), EdgeIdx(Idx) {} + VPHierarchicalChildrenIterator(const VPHierarchicalChildrenIterator &Other) + : Block(Other.Block), EdgeIdx(Other.EdgeIdx) {} - VPAllSuccessorsIterator &operator=(const VPAllSuccessorsIterator &R) { + VPHierarchicalChildrenIterator & + operator=(const VPHierarchicalChildrenIterator &R) { Block = R.Block; - SuccessorIdx = R.SuccessorIdx; + EdgeIdx = R.EdgeIdx; return *this; } - static VPAllSuccessorsIterator end(BlockPtrTy Block) { + static VPHierarchicalChildrenIterator end(BlockPtrTy Block) { if (auto *R = dyn_cast(Block)) { - // Traverse through the region's entry node. + // Traverse through the region's entry/exiting (based on Forward) node. return {R, 1}; } - BlockPtrTy ParentWithSuccs = getBlockWithSuccs(Block); - unsigned NumSuccessors = - ParentWithSuccs ? ParentWithSuccs->getNumSuccessors() : 0; - return {Block, NumSuccessors}; + BlockPtrTy ParentWithOutgoingEdges = getBlockWithOutgoingEdges(Block); + unsigned NumOutgoingEdges = + ParentWithOutgoingEdges ? getNumOutgoingEdges(ParentWithOutgoingEdges) + : 0; + return {Block, NumOutgoingEdges}; } - bool operator==(const VPAllSuccessorsIterator &R) const { - return Block == R.Block && SuccessorIdx == R.SuccessorIdx; + bool operator==(const VPHierarchicalChildrenIterator &R) const { + return Block == R.Block && EdgeIdx == R.EdgeIdx; } - const VPBlockBase *operator*() const { return deref(Block, SuccessorIdx); } + const VPBlockBase *operator*() const { return deref(Block, EdgeIdx); } - BlockPtrTy operator*() { return deref(Block, SuccessorIdx); } + BlockPtrTy operator*() { return deref(Block, EdgeIdx); } - VPAllSuccessorsIterator &operator++() { - SuccessorIdx++; + VPHierarchicalChildrenIterator &operator++() { + EdgeIdx++; return *this; } - VPAllSuccessorsIterator &operator--() { - SuccessorIdx--; + VPHierarchicalChildrenIterator &operator--() { + EdgeIdx--; return *this; } - VPAllSuccessorsIterator operator++(int X) { - VPAllSuccessorsIterator Orig = *this; - SuccessorIdx++; + VPHierarchicalChildrenIterator operator++(int X) { + VPHierarchicalChildrenIterator Orig = *this; + EdgeIdx++; return Orig; } }; @@ -129,7 +175,7 @@ template class VPBlockDeepTraversalWrapper { /// reverse post-order traversal of the graph. template <> struct GraphTraits> { using NodeRef = VPBlockBase *; - using ChildIteratorType = VPAllSuccessorsIterator; + using ChildIteratorType = VPHierarchicalChildrenIterator; static NodeRef getEntryNode(VPBlockDeepTraversalWrapper N) { return N.getEntry(); @@ -147,7 +193,7 @@ template <> struct GraphTraits> { template <> struct GraphTraits> { using NodeRef = const VPBlockBase *; - using ChildIteratorType = VPAllSuccessorsIterator; + using ChildIteratorType = VPHierarchicalChildrenIterator; static NodeRef getEntryNode(VPBlockDeepTraversalWrapper N) { @@ -257,7 +303,7 @@ vp_depth_first_deep(const VPBlockBase *G) { template <> struct GraphTraits { using NodeRef = VPBlockBase *; - using ChildIteratorType = VPAllSuccessorsIterator; + using ChildIteratorType = VPHierarchicalChildrenIterator; static NodeRef getEntryNode(NodeRef N) { return N; } @@ -272,7 +318,7 @@ template <> struct GraphTraits { template <> struct GraphTraits { using NodeRef = const VPBlockBase *; - using ChildIteratorType = VPAllSuccessorsIterator; + using ChildIteratorType = VPHierarchicalChildrenIterator; static NodeRef getEntryNode(NodeRef N) { return N; } @@ -285,23 +331,19 @@ template <> struct GraphTraits { } }; -/// Inverse graph traits are not implemented yet. -/// TODO: Implement a version of VPBlockNonRecursiveTraversalWrapper to traverse -/// predecessors recursively through regions. template <> struct GraphTraits> { using NodeRef = VPBlockBase *; - using ChildIteratorType = SmallVectorImpl::iterator; + using ChildIteratorType = + VPHierarchicalChildrenIterator; - static NodeRef getEntryNode(Inverse B) { - llvm_unreachable("not implemented"); - } + static NodeRef getEntryNode(Inverse B) { return B.Graph; } static inline ChildIteratorType child_begin(NodeRef N) { - llvm_unreachable("not implemented"); + return ChildIteratorType(N); } static inline ChildIteratorType child_end(NodeRef N) { - llvm_unreachable("not implemented"); + return ChildIteratorType::end(N); } }; diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp index 4e7b1bbab5227..91d73671cf26a 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp @@ -221,7 +221,8 @@ void PlainCFGBuilder::createVPInstructionsForVPBB(VPBasicBlock *VPBB, // Phi node's operands may not have been visited at this point. We create // an empty VPInstruction that we will fix once the whole plain CFG has // been built. - NewR = VPIRBuilder.createScalarPhi({}, Phi->getDebugLoc(), "vec.phi"); + NewR = + VPIRBuilder.createScalarPhi({}, Phi->getDebugLoc(), "vec.phi", *Phi); NewR->setUnderlyingValue(Phi); if (isHeaderBB(Phi->getParent(), LI->getLoopFor(Phi->getParent()))) { // Header phis need to be fixed after the VPBB for the latch has been @@ -476,9 +477,8 @@ static void addCanonicalIVRecipes(VPlan &Plan, VPBasicBlock *HeaderVPBB, // Add a VPInstruction to increment the scalar canonical IV by VF * UF. // Initially the induction increment is guaranteed to not wrap, but that may // change later, e.g. when tail-folding, when the flags need to be dropped. - auto *CanonicalIVIncrement = Builder.createOverflowingOp( - Instruction::Add, {CanonicalIVPHI, &Plan.getVFxUF()}, {true, false}, DL, - "index.next"); + auto *CanonicalIVIncrement = Builder.createAdd( + CanonicalIVPHI, &Plan.getVFxUF(), DL, "index.next", {true, false}); CanonicalIVPHI->addOperand(CanonicalIVIncrement); // Add the BranchOnCount VPInstruction to the latch. @@ -644,8 +644,31 @@ createWidenInductionRecipe(PHINode *Phi, VPPhi *PhiR, VPIRValue *Start, // used, so it is safe. VPIRFlags Flags = vputils::getFlagsFromIndDesc(IndDesc); - return new VPWidenIntOrFpInductionRecipe(Phi, Start, Step, &Plan.getVF(), - IndDesc, Flags, DL); + auto *WideIV = new VPWidenIntOrFpInductionRecipe( + Phi, Start, Step, &Plan.getVF(), IndDesc, Flags, DL); + + // Replace live-out extracts of WideIV's backedge value by ExitingIVValue + // recipes. + VPValue *BackedgeVal = PhiR->getOperand(1); + for (VPUser *U : to_vector(BackedgeVal->users())) { + if (!match(U, m_ExtractLastPart(m_VPValue()))) + continue; + auto *ExtractLastPart = cast(U); + if (!match(ExtractLastPart->getSingleUser(), + m_ExtractLastLane(m_VPValue()))) + continue; + auto *ExtractLastLane = + cast(ExtractLastPart->getSingleUser()); + assert(is_contained(ExtractLastLane->getParent()->successors(), + Plan.getScalarPreheader()) && + "last lane must be extracted in the middle block"); + VPBuilder Builder(ExtractLastLane); + ExtractLastLane->replaceAllUsesWith(Builder.createNaryOp( + VPInstruction::ExitingIVValue, {WideIV, BackedgeVal})); + ExtractLastLane->eraseFromParent(); + ExtractLastPart->eraseFromParent(); + } + return WideIV; } void VPlanTransforms::createHeaderPhiRecipes( @@ -713,8 +736,7 @@ void VPlanTransforms::createHeaderPhiRecipes( } void VPlanTransforms::createInLoopReductionRecipes( - VPlan &Plan, const DenseMap &BlockMaskCache, - const DenseSet &BlocksNeedingPredication, + VPlan &Plan, const DenseSet &BlocksNeedingPredication, ElementCount MinVF) { VPTypeAnalysis TypeInfo(Plan); VPBasicBlock *Header = Plan.getVectorLoopRegion()->getEntryBasicBlock(); @@ -813,11 +835,10 @@ void VPlanTransforms::createInLoopReductionRecipes( match(CurrentLink, m_Sub(m_VPValue(), m_VPValue()))) { Type *PhiTy = TypeInfo.inferScalarType(PhiR); auto *Zero = Plan.getConstantInt(PhiTy, 0); - auto *Sub = new VPInstruction(Instruction::Sub, - {Zero, CurrentLink->getOperand(1)}, {}, - {}, CurrentLinkI->getDebugLoc()); + VPBuilder Builder(LinkVPBB, CurrentLink->getIterator()); + auto *Sub = Builder.createSub(Zero, CurrentLink->getOperand(1), + CurrentLinkI->getDebugLoc()); Sub->setUnderlyingValue(CurrentLinkI); - LinkVPBB->insert(Sub, CurrentLink->getIterator()); VecOp = Sub; } else { // Index of the first operand which holds a non-mask vector operand. @@ -837,17 +858,18 @@ void VPlanTransforms::createInLoopReductionRecipes( ? IndexOfFirstOperand + 1 : IndexOfFirstOperand; VecOp = CurrentLink->getOperand(VecOpId); - assert(VecOp != PreviousLink && - CurrentLink->getOperand(CurrentLink->getNumOperands() - 1 - - (VecOpId - IndexOfFirstOperand)) == - PreviousLink && - "PreviousLink must be the operand other than VecOp"); + assert( + VecOp != PreviousLink && + CurrentLink->getOperand( + cast(CurrentLink)->getNumOperandsWithoutMask() - + 1 - (VecOpId - IndexOfFirstOperand)) == PreviousLink && + "PreviousLink must be the operand other than VecOp"); } - // Get block mask from BlockMaskCache if the block needs predication. + // Get block mask from CurrentLink, if it needs predication. VPValue *CondOp = nullptr; if (BlocksNeedingPredication.contains(CurrentLinkI->getParent())) - CondOp = BlockMaskCache.lookup(LinkVPBB); + CondOp = cast(CurrentLink)->getMask(); assert(PhiR->getVFScaleFactor() == 1 && "inloop reductions must be unscaled"); @@ -1061,9 +1083,8 @@ void VPlanTransforms::addMinimumIterationCheck( // Get the maximum unsigned value for the type. VPValue *MaxUIntTripCount = Plan.getConstantInt(cast(TripCountTy)->getMask()); - VPValue *DistanceToMax = Builder.createNaryOp( - Instruction::Sub, {MaxUIntTripCount, TripCountVPV}, - DebugLoc::getUnknown()); + VPValue *DistanceToMax = + Builder.createSub(MaxUIntTripCount, TripCountVPV); // Don't execute the vector loop if (UMax - n) < (VF * UF). // FIXME: Should only check VF * UF, but currently checks Step=max(VF*UF, @@ -1111,9 +1132,8 @@ void VPlanTransforms::addMinimumVectorEpilogueIterationCheck( VPBuilder Builder(cast(Plan.getEntry())); VPValue *VFxUF = Builder.createExpandSCEV(SE.getElementCount( TripCount->getType(), (EpilogueVF * EpilogueUF), SCEV::FlagNUW)); - VPValue *Count = Builder.createNaryOp( - Instruction::Sub, {TC, Plan.getOrAddLiveIn(VectorTripCount)}, - DebugLoc::getUnknown(), "n.vec.remaining"); + VPValue *Count = Builder.createSub(TC, Plan.getOrAddLiveIn(VectorTripCount), + DebugLoc::getUnknown(), "n.vec.remaining"); // Generate code to check if the loop's trip count is less than VF * UF of // the vector epilogue loop. @@ -1262,8 +1282,7 @@ bool VPlanTransforms::handleMaxMinNumReductions(VPlan &Plan) { auto *IsLatchExitTaken = LatchBuilder.createICmp( CmpInst::ICMP_EQ, LatchExitingBranch->getOperand(0), LatchExitingBranch->getOperand(1)); - auto *AnyExitTaken = LatchBuilder.createNaryOp( - Instruction::Or, {AnyNaNLane, IsLatchExitTaken}); + auto *AnyExitTaken = LatchBuilder.createOr(AnyNaNLane, IsLatchExitTaken); LatchBuilder.createNaryOp(VPInstruction::BranchOnCond, AnyExitTaken); LatchExitingBranch->eraseFromParent(); @@ -1469,10 +1488,22 @@ bool VPlanTransforms::handleMultiUseReductions(VPlan &Plan) { } auto *FindIVPhiR = dyn_cast(FindIV); - if (!FindIVPhiR || !RecurrenceDescriptor::isFindLastIVRecurrenceKind( + if (!FindIVPhiR || !RecurrenceDescriptor::isFindIVRecurrenceKind( FindIVPhiR->getRecurrenceKind())) return false; + // Check if FindIVPhiR is a FindLast pattern by checking the MinMaxKind + // on its ComputeReductionResult. SMax/UMax indicates FindLast. + VPInstruction *FindIVResult = + vputils::findUserOf( + FindIVPhiR->getBackedgeValue()); + assert(FindIVResult && + "must be able to retrieve the FindIVResult VPInstruction"); + RecurKind FindIVMinMaxKind = FindIVResult->getRecurKind(); + if (FindIVMinMaxKind != RecurKind::SMax && + FindIVMinMaxKind != RecurKind::UMax) + return false; + // TODO: Support cases where IVOp is the IV increment. if (!match(IVOp, m_TruncOrSelf(m_VPValue(IVOp))) || !isa(IVOp)) diff --git a/llvm/lib/Transforms/Vectorize/VPlanHelpers.h b/llvm/lib/Transforms/Vectorize/VPlanHelpers.h index 26e4d31696f8a..bab7e25cbf407 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanHelpers.h +++ b/llvm/lib/Transforms/Vectorize/VPlanHelpers.h @@ -383,6 +383,11 @@ struct VPCostContext { Type *ResultTy, ArrayRef Operands, ElementCount VF, TTI::VectorInstrContext VIC = TTI::VectorInstrContext::None, bool AlwaysIncludeReplicatingR = false); + + /// Returns true if an artificially high cost for emulated masked memrefs + /// should be used. Forwards to + /// LoopVectorizationCostModel::useEmulatedMaskMemRefHack. + bool useEmulatedMaskMemRefHack(Instruction *I, ElementCount VF); }; /// This class can be used to assign names to VPValues. For VPValues without diff --git a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h index 9428070b02f1a..c0b736de1bc51 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h +++ b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h @@ -206,6 +206,16 @@ struct bind_const_int { } }; +struct match_poison { + bool match(VPValue *V) const { + return isa(V) && + isa(cast(V)->getValue()); + } +}; + +/// Match a VPIRValue that's poison. +inline match_poison m_Poison() { return match_poison(); } + /// Match a plain integer constant no wider than 64-bits, capturing it if we /// match. inline bind_const_int m_ConstantInt(uint64_t &C) { return C; } @@ -284,10 +294,10 @@ struct Recipe_match { if ((!matchRecipeAndOpcode(R) && ...)) return false; - if (R->getNumOperands() != std::tuple_size_v) { + if (R->getNumOperands() < std::tuple_size::value) { [[maybe_unused]] auto *RepR = dyn_cast(R); assert(((isa(R) && - VPInstruction::getNumOperandsForOpcode(Opcode) == -1u) || + cast(R)->getNumOperandsForOpcode() == -1u) || (RepR && std::tuple_size_v == RepR->getNumOperands() - RepR->isPredicated())) && "non-variadic recipe with matched opcode does not have the " @@ -295,6 +305,16 @@ struct Recipe_match { return false; } + // If the recipe has more operands than expected, we only support matching + // masked VPInstructions where the number of operands of the matcher is the + // same as the number of operands excluding mask. + if (R->getNumOperands() > std::tuple_size::value) { + auto *VPI = dyn_cast(R); + if (!VPI || !VPI->isMasked() || + VPI->getNumOperandsWithoutMask() != std::tuple_size::value) + return false; + } + auto IdxSeq = std::make_index_sequence::value>(); if (all_of_tuple_elements(IdxSeq, [R](auto Op, unsigned Idx) { return Op.match(R->getOperand(Idx)); @@ -505,6 +525,12 @@ inline VPInstruction_match m_StepVector() { return m_VPInstruction(); } +template +inline VPInstruction_match +m_ExitingIVValue(const Op0_t &Op0, const Op1_t &Op1) { + return m_VPInstruction(Op0, Op1); +} + template inline AllRecipe_match m_Unary(const Op0_t &Op0) { return AllRecipe_match(Op0); @@ -1053,6 +1079,10 @@ template inline OneUse_match m_OneUse(const T &SubPattern) { return SubPattern; } +inline bind_ty m_ReductionPhi(VPReductionPHIRecipe *&V) { + return V; +} + } // namespace llvm::VPlanPatternMatch #endif diff --git a/llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp b/llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp index f7e7fc29bc203..216efaf4b2fe9 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp @@ -76,14 +76,12 @@ class VPPredicator { /// Compute and return the mask for the vector loop header block. void createHeaderMask(VPBasicBlock *HeaderVPBB, bool FoldTail); - /// Compute and return the predicate of \p VPBB, assuming that the header - /// block of the loop is set to True, or to the loop mask when tail folding. - VPValue *createBlockInMask(VPBasicBlock *VPBB); + /// Compute the predicate of \p VPBB, assuming that the header block of the + /// loop is set to True, or to the loop mask when tail folding. + void createBlockInMask(VPBasicBlock *VPBB); /// Convert phi recipes in \p VPBB to VPBlendRecipes. void convertPhisToBlends(VPBasicBlock *VPBB); - - const BlockMaskCacheTy getBlockMaskCache() const { return BlockMaskCache; } }; } // namespace @@ -128,7 +126,7 @@ VPValue *VPPredicator::createEdgeMask(VPBasicBlock *Src, VPBasicBlock *Dst) { return setEdgeMask(Src, Dst, EdgeMask); } -VPValue *VPPredicator::createBlockInMask(VPBasicBlock *VPBB) { +void VPPredicator::createBlockInMask(VPBasicBlock *VPBB) { // Start inserting after the block's phis, which be replaced by blends later. Builder.setInsertPoint(VPBB, VPBB->getFirstNonPhi()); // All-one mask is modelled as no-mask following the convention for masked @@ -141,7 +139,7 @@ VPValue *VPPredicator::createBlockInMask(VPBasicBlock *VPBB) { if (!EdgeMask) { // Mask of predecessor is all-one so mask of block is // too. setBlockInMask(VPBB, EdgeMask); - return EdgeMask; + return; } if (!BlockMask) { // BlockMask has its initial nullptr value. @@ -153,7 +151,6 @@ VPValue *VPPredicator::createBlockInMask(VPBasicBlock *VPBB) { } setBlockInMask(VPBB, BlockMask); - return BlockMask; } void VPPredicator::createHeaderMask(VPBasicBlock *HeaderVPBB, bool FoldTail) { @@ -225,6 +222,10 @@ void VPPredicator::createSwitchEdgeMasks(VPInstruction *SI) { DefaultMask = Builder.createNot(DefaultMask); if (SrcMask) DefaultMask = Builder.createLogicalAnd(SrcMask, DefaultMask); + } else { + // There are no destinations other than the default destination, so this is + // an unconditional branch. + DefaultMask = SrcMask; } setEdgeMask(Src, DefaultDst, DefaultMask); } @@ -240,7 +241,9 @@ void VPPredicator::convertPhisToBlends(VPBasicBlock *VPBB) { // be duplications since this is a simple recursive scan, but future // optimizations will clean it up. - if (all_equal(PhiR->incoming_values())) { + if (all_equal(make_filter_range(PhiR->incoming_values(), [](VPValue *V) { + return !match(V, m_Poison()); + }))) { PhiR->replaceAllUsesWith(PhiR->getIncomingValue(0)); PhiR->eraseFromParent(); continue; @@ -253,15 +256,14 @@ void VPPredicator::convertPhisToBlends(VPBasicBlock *VPBB) { } PHINode *IRPhi = cast_or_null(PhiR->getUnderlyingValue()); auto *Blend = - new VPBlendRecipe(IRPhi, OperandsWithMask, PhiR->getDebugLoc()); + new VPBlendRecipe(IRPhi, OperandsWithMask, *PhiR, PhiR->getDebugLoc()); Builder.insert(Blend); PhiR->replaceAllUsesWith(Blend); PhiR->eraseFromParent(); } } -DenseMap -VPlanTransforms::introduceMasksAndLinearize(VPlan &Plan, bool FoldTail) { +void VPlanTransforms::introduceMasksAndLinearize(VPlan &Plan, bool FoldTail) { VPRegionBlock *LoopRegion = Plan.getVectorLoopRegion(); // Scan the body of the loop in a topological order to visit each basic block // after having visited its predecessor basic blocks. @@ -277,11 +279,20 @@ VPlanTransforms::introduceMasksAndLinearize(VPlan &Plan, bool FoldTail) { // header. if (VPBB == Header) { Predicator.createHeaderMask(Header, FoldTail); - continue; + } else { + Predicator.createBlockInMask(VPBB); + Predicator.convertPhisToBlends(VPBB); } - Predicator.createBlockInMask(VPBB); - Predicator.convertPhisToBlends(VPBB); + VPValue *BlockMask = Predicator.getBlockInMask(VPBB); + if (!BlockMask) + continue; + + // Mask all VPInstructions in the block. + for (VPRecipeBase &R : *VPBB) { + if (auto *VPI = dyn_cast(&R)) + VPI->addMask(BlockMask); + } } // Linearize the blocks of the loop into one serial chain. @@ -315,7 +326,9 @@ VPlanTransforms::introduceMasksAndLinearize(VPlan &Plan, bool FoldTail) { VPBuilder B(Plan.getMiddleBlock()->getTerminator()); for (VPRecipeBase &R : *Plan.getMiddleBlock()) { VPValue *Op; - if (!match(&R, m_ExtractLastLane(m_ExtractLastPart(m_VPValue(Op))))) + if (!match(&R, m_CombineOr( + m_ExitingIVValue(m_VPValue(), m_VPValue(Op)), + m_ExtractLastLane(m_ExtractLastPart(m_VPValue(Op)))))) continue; // Compute the index of the last active lane. @@ -327,5 +340,4 @@ VPlanTransforms::introduceMasksAndLinearize(VPlan &Plan, bool FoldTail) { R.getVPSingleValue()->replaceAllUsesWith(Ext); } } - return Predicator.getBlockMaskCache(); } diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index 6fb4225f32800..f6bafae3e2acb 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -425,13 +425,14 @@ VPInstruction::VPInstruction(unsigned Opcode, ArrayRef Operands, VPIRMetadata(MD), Opcode(Opcode), Name(Name.str()) { assert(flagsValidForOpcode(getOpcode()) && "Set flags not supported for the provided opcode"); - assert((getNumOperandsForOpcode(Opcode) == -1u || - getNumOperandsForOpcode(Opcode) == getNumOperands()) && + assert(hasRequiredFlagsForOpcode(getOpcode()) && + "Opcode requires specific flags to be set"); + assert((getNumOperandsForOpcode() == -1u || + getNumOperandsForOpcode() == getNumOperands()) && "number of operands does not match opcode"); } -#ifndef NDEBUG -unsigned VPInstruction::getNumOperandsForOpcode(unsigned Opcode) { +unsigned VPInstruction::getNumOperandsForOpcode() const { if (Instruction::isUnaryOp(Opcode) || Instruction::isCast(Opcode)) return 1; @@ -448,11 +449,7 @@ unsigned VPInstruction::getNumOperandsForOpcode(unsigned Opcode) { case Instruction::Load: case VPInstruction::BranchOnCond: case VPInstruction::Broadcast: - case VPInstruction::BuildStructVector: - case VPInstruction::BuildVector: case VPInstruction::CalculateTripCountMinusVF: - case VPInstruction::CanonicalIVIncrementForPart: - case VPInstruction::ComputeReductionResult: case VPInstruction::ExplicitVectorLength: case VPInstruction::ExtractLastLane: case VPInstruction::ExtractLastPart: @@ -468,6 +465,7 @@ unsigned VPInstruction::getNumOperandsForOpcode(unsigned Opcode) { case Instruction::Store: case VPInstruction::BranchOnCount: case VPInstruction::BranchOnTwoConds: + case VPInstruction::ExitingIVValue: case VPInstruction::FirstOrderRecurrenceSplice: case VPInstruction::LogicalAnd: case VPInstruction::PtrAdd: @@ -476,15 +474,26 @@ unsigned VPInstruction::getNumOperandsForOpcode(unsigned Opcode) { return 2; case Instruction::Select: case VPInstruction::ActiveLaneMask: - case VPInstruction::ComputeAnyOfResult: case VPInstruction::ReductionStartVector: case VPInstruction::ExtractLastActive: return 3; - case Instruction::Call: + case Instruction::Call: { + // For unmasked calls, the last argument will the called function. Use that + // to compute the number of operands without the mask. + VPValue *LastOp = getOperand(getNumOperands() - 1); + if (isa(LastOp) && isa(LastOp->getLiveInIRValue())) + return getNumOperands(); + return getNumOperands() - 1; + } case Instruction::GetElementPtr: case Instruction::PHI: case Instruction::Switch: case VPInstruction::AnyOf: + case VPInstruction::BuildStructVector: + case VPInstruction::BuildVector: + case VPInstruction::CanonicalIVIncrementForPart: + case VPInstruction::ComputeAnyOfResult: + case VPInstruction::ComputeReductionResult: case VPInstruction::FirstActiveLane: case VPInstruction::LastActiveLane: case VPInstruction::SLPLoad: @@ -495,7 +504,6 @@ unsigned VPInstruction::getNumOperandsForOpcode(unsigned Opcode) { } llvm_unreachable("all cases should be handled above"); } -#endif bool VPInstruction::doesGeneratePerAllLanes() const { return Opcode == VPInstruction::PtrAdd && !vputils::onlyFirstLaneUsed(this); @@ -575,7 +583,9 @@ Value *VPInstruction::generate(VPTransformState &State) { OnlyFirstLaneUsed || vputils::isSingleScalar(getOperand(0))); Value *Op1 = State.get(getOperand(1), OnlyFirstLaneUsed); Value *Op2 = State.get(getOperand(2), OnlyFirstLaneUsed); - return Builder.CreateSelect(Cond, Op1, Op2, Name); + FastMathFlags FMFs = + hasFastMathFlags() ? getFastMathFlags() : FastMathFlags(); + return Builder.CreateSelectFMF(Cond, Op1, Op2, FMFs, Name); } case VPInstruction::ActiveLaneMask: { // Get first lane of vector induction variable. @@ -804,7 +814,7 @@ Value *VPInstruction::generate(VPTransformState &State) { return Builder.CreateLogicalAnd(A, B, Name); } case VPInstruction::PtrAdd: { - assert(vputils::onlyFirstLaneUsed(this) && + assert((State.VF.isScalar() || vputils::onlyFirstLaneUsed(this)) && "can only generate first lane for PtrAdd"); Value *Ptr = State.get(getOperand(0), VPLane(0)); Value *Addend = State.get(getOperand(1), VPLane(0)); @@ -1271,10 +1281,13 @@ bool VPInstruction::isSingleScalar() const { } void VPInstruction::execute(VPTransformState &State) { + assert(!isMasked() && "cannot execute masked VPInstruction"); assert(!State.Lane && "VPInstruction executing an Lane"); IRBuilderBase::FastMathFlagGuard FMFGuard(State.Builder); assert(flagsValidForOpcode(getOpcode()) && "Set flags not supported for the provided opcode"); + assert(hasRequiredFlagsForOpcode(getOpcode()) && + "Opcode requires specific flags to be set"); if (hasFastMathFlags()) State.Builder.setFastMathFlags(getFastMathFlags()); Value *GeneratedValue = generate(State); @@ -1318,6 +1331,7 @@ bool VPInstruction::opcodeMayReadOrWriteFromMemory() const { case VPInstruction::ExtractLastPart: case VPInstruction::ExtractPenultimateElement: case VPInstruction::ActiveLaneMask: + case VPInstruction::ExitingIVValue: case VPInstruction::ExplicitVectorLength: case VPInstruction::FirstActiveLane: case VPInstruction::LastActiveLane: @@ -1381,6 +1395,7 @@ bool VPInstruction::usesFirstLaneOnly(const VPValue *Op) const { return false; case VPInstruction::ComputeAnyOfResult: return Op == getOperand(0) || Op == getOperand(1); + case VPInstruction::ExitingIVValue: case VPInstruction::ExtractLane: return Op == getOperand(0); }; @@ -1466,6 +1481,9 @@ void VPInstruction::printRecipe(raw_ostream &O, const Twine &Indent, case VPInstruction::BuildVector: O << "buildvector"; break; + case VPInstruction::ExitingIVValue: + O << "exiting-iv-value"; + break; case VPInstruction::ExtractLane: O << "extract-lane"; break; @@ -1603,7 +1621,8 @@ void VPPhi::printRecipe(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { O << Indent << "EMIT" << (isSingleScalar() ? "-SCALAR" : "") << " "; printAsOperand(O, SlotTracker); - O << " = phi "; + O << " = phi"; + printFlags(O); printPhiOperands(O, SlotTracker); } #endif @@ -1662,7 +1681,7 @@ void VPIRPhi::execute(VPTransformState &State) { BasicBlock *PredBB = State.CFG.VPBB2IRBB[PredVPBB]; // Set insertion point in PredBB in case an extract needs to be generated. // TODO: Model extracts explicitly. - State.Builder.SetInsertPoint(PredBB, PredBB->getFirstNonPHIIt()); + State.Builder.SetInsertPoint(PredBB->getTerminator()); Value *V = State.get(ExitValue, VPLane(Lane)); // If there is no existing block for PredBB in the phi, add a new incoming // value. Otherwise update the existing incoming value for PredBB. @@ -1830,12 +1849,7 @@ void VPWidenIntrinsicRecipe::execute(VPTransformState &State) { if (isVectorIntrinsicWithOverloadTypeAtArg(VectorIntrinsicID, -1, State.TTI)) { Type *RetTy = toVectorizedTy(getResultType(), State.VF); - ArrayRef ContainedTys = getContainedTypes(RetTy); - for (auto [Idx, Ty] : enumerate(ContainedTys)) { - if (isVectorIntrinsicWithStructReturnOverloadAtField(VectorIntrinsicID, - Idx, State.TTI)) - TysForDecl.push_back(Ty); - } + append_range(TysForDecl, getContainedTypes(RetTy)); } SmallVector Args; for (const auto &I : enumerate(operands())) { @@ -2052,6 +2066,48 @@ VPIRFlags::FastMathFlagsTy::FastMathFlagsTy(const FastMathFlags &FMF) { ApproxFunc = FMF.approxFunc(); } +VPIRFlags VPIRFlags::getDefaultFlags(unsigned Opcode) { + switch (Opcode) { + case Instruction::Add: + case Instruction::Sub: + case Instruction::Mul: + case Instruction::Shl: + case VPInstruction::CanonicalIVIncrementForPart: + return WrapFlagsTy(false, false); + case Instruction::Trunc: + return TruncFlagsTy(false, false); + case Instruction::Or: + return DisjointFlagsTy(false); + case Instruction::AShr: + case Instruction::LShr: + case Instruction::UDiv: + case Instruction::SDiv: + return ExactFlagsTy(false); + case Instruction::GetElementPtr: + case VPInstruction::PtrAdd: + case VPInstruction::WidePtrAdd: + return GEPNoWrapFlags::none(); + case Instruction::ZExt: + case Instruction::UIToFP: + return NonNegFlagsTy(false); + case Instruction::FAdd: + case Instruction::FSub: + case Instruction::FMul: + case Instruction::FDiv: + case Instruction::FRem: + case Instruction::FNeg: + case Instruction::FPExt: + case Instruction::FPTrunc: + return FastMathFlags(); + case Instruction::ICmp: + case Instruction::FCmp: + case VPInstruction::ComputeReductionResult: + llvm_unreachable("opcode requires explicit flags"); + default: + return VPIRFlags(); + } +} + #if !defined(NDEBUG) bool VPIRFlags::flagsValidForOpcode(unsigned Opcode) const { switch (OpType) { @@ -2075,7 +2131,8 @@ bool VPIRFlags::flagsValidForOpcode(unsigned Opcode) const { Opcode == Instruction::FMul || Opcode == Instruction::FSub || Opcode == Instruction::FNeg || Opcode == Instruction::FDiv || Opcode == Instruction::FRem || Opcode == Instruction::FPExt || - Opcode == Instruction::FPTrunc || Opcode == Instruction::Select || + Opcode == Instruction::FPTrunc || Opcode == Instruction::PHI || + Opcode == Instruction::Select || Opcode == VPInstruction::WideIVStep || Opcode == VPInstruction::ReductionStartVector; case OperationType::FCmp: @@ -2091,6 +2148,19 @@ bool VPIRFlags::flagsValidForOpcode(unsigned Opcode) const { } llvm_unreachable("Unknown OperationType enum"); } + +bool VPIRFlags::hasRequiredFlagsForOpcode(unsigned Opcode) const { + // Handle opcodes without default flags. + if (Opcode == Instruction::ICmp) + return OpType == OperationType::Cmp; + if (Opcode == Instruction::FCmp) + return OpType == OperationType::FCmp; + if (Opcode == VPInstruction::ComputeReductionResult) + return OpType == OperationType::ReductionOp; + + OperationType Required = getDefaultFlags(Opcode).OpType; + return Required == OperationType::Other || Required == OpType; +} #endif #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) @@ -2673,14 +2743,15 @@ void VPBlendRecipe::printRecipe(raw_ostream &O, const Twine &Indent, O << Indent << "BLEND "; printAsOperand(O, SlotTracker); O << " ="; + printFlags(O); if (getNumIncomingValues() == 1) { // Not a User of any mask: not really blending, this is a // single-predecessor phi. - O << " "; getIncomingValue(0)->printAsOperand(O, SlotTracker); } else { for (unsigned I = 0, E = getNumIncomingValues(); I < E; ++I) { - O << " "; + if (I != 0) + O << " "; getIncomingValue(I)->printAsOperand(O, SlotTracker); if (I == 0) continue; @@ -3410,12 +3481,6 @@ InstructionCost VPReplicateRecipe::computeCost(ElementCount VF, } case Instruction::Load: case Instruction::Store: { - // TODO: See getMemInstScalarizationCost for how to handle replicating and - // predicated cases. - const VPRegionBlock *ParentRegion = getRegion(); - if (ParentRegion && ParentRegion->isReplicator()) - break; - bool IsLoad = UI->getOpcode() == Instruction::Load; const VPValue *PtrOp = getOperand(!IsLoad); const SCEV *PtrSCEV = getAddressAccessSCEV(PtrOp, Ctx.PSE, Ctx.L); @@ -3427,13 +3492,14 @@ InstructionCost VPReplicateRecipe::computeCost(ElementCount VF, const Align Alignment = getLoadStoreAlignment(UI); unsigned AS = cast(ScalarPtrTy)->getAddressSpace(); TTI::OperandValueInfo OpInfo = TTI::getOperandInfo(UI->getOperand(0)); - InstructionCost ScalarMemOpCost = Ctx.TTI.getMemoryOpCost( - UI->getOpcode(), ValTy, Alignment, AS, Ctx.CostKind, OpInfo); - - Type *PtrTy = isSingleScalar() ? ScalarPtrTy : toVectorTy(ScalarPtrTy, VF); bool PreferVectorizedAddressing = Ctx.TTI.prefersVectorizedAddressing(); bool UsedByLoadStoreAddress = !PreferVectorizedAddressing && isUsedByLoadStoreAddress(this); + InstructionCost ScalarMemOpCost = Ctx.TTI.getMemoryOpCost( + UI->getOpcode(), ValTy, Alignment, AS, Ctx.CostKind, OpInfo, + UsedByLoadStoreAddress ? UI : nullptr); + + Type *PtrTy = isSingleScalar() ? ScalarPtrTy : toVectorTy(ScalarPtrTy, VF); InstructionCost ScalarCost = ScalarMemOpCost + Ctx.TTI.getAddressComputationCost( @@ -3461,9 +3527,32 @@ InstructionCost VPReplicateRecipe::computeCost(ElementCount VF, TTI::VectorInstrContext VIC = IsLoad ? TTI::VectorInstrContext::Load : TTI::VectorInstrContext::Store; - return (ScalarCost * VF.getFixedValue()) + - Ctx.getScalarizationOverhead(ResultTy, OpsToScalarize, VF, VIC, - true); + InstructionCost Cost = + (ScalarCost * VF.getFixedValue()) + + Ctx.getScalarizationOverhead(ResultTy, OpsToScalarize, VF, VIC, true); + + const VPRegionBlock *ParentRegion = getRegion(); + if (ParentRegion && ParentRegion->isReplicator()) { + // TODO: Handle loop-invariant pointers in predicated blocks. For now, + // fall back to the legacy cost model. + if (!PtrSCEV || Ctx.PSE.getSE()->isLoopInvariant(PtrSCEV, Ctx.L)) + break; + Cost /= Ctx.getPredBlockCostDivisor(UI->getParent()); + Cost += Ctx.TTI.getCFInstrCost(Instruction::Br, Ctx.CostKind); + + auto *VecI1Ty = VectorType::get( + IntegerType::getInt1Ty(Ctx.L->getHeader()->getContext()), VF); + Cost += Ctx.TTI.getScalarizationOverhead( + VecI1Ty, APInt::getAllOnes(VF.getFixedValue()), + /*Insert=*/false, /*Extract=*/true, Ctx.CostKind); + + if (Ctx.useEmulatedMaskMemRefHack(UI, VF)) { + // Artificially setting to a high enough value to practically disable + // vectorization with such operations. + return 3000000; + } + } + return Cost; } case Instruction::SExt: case Instruction::ZExt: diff --git a/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp b/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp index fd1176d4f5541..fb7e1dd5b1e4e 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp @@ -517,8 +517,9 @@ VPInstruction *VPlanSlp::buildGraph(ArrayRef Values) { assert(CombinedOperands.size() > 0 && "Need more some operands"); auto *Inst = cast(Values[0])->getUnderlyingInstr(); - auto *VPI = - new VPInstruction(Opcode, CombinedOperands, {}, {}, Inst->getDebugLoc()); + auto *VPI = new VPInstruction(Opcode, CombinedOperands, + VPIRFlags::getDefaultFlags(Opcode), {}, + Inst->getDebugLoc()); LLVM_DEBUG(dbgs() << "Create VPInstruction " << *VPI << " " << Values[0] << "\n"); diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 43cffe5d30d6b..839b4cdf4219c 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -967,15 +967,14 @@ static VPValue *optimizeEarlyExitInductionUser(VPlan &Plan, Type *FirstActiveLaneType = TypeInfo.inferScalarType(FirstActiveLane); FirstActiveLane = B.createScalarZExtOrTrunc(FirstActiveLane, CanonicalIVType, FirstActiveLaneType, DL); - VPValue *EndValue = - B.createNaryOp(Instruction::Add, {CanonicalIV, FirstActiveLane}, DL); + VPValue *EndValue = B.createAdd(CanonicalIV, FirstActiveLane, DL); // `getOptimizableIVOf()` always returns the pre-incremented IV, so if it // changed it means the exit is using the incremented value, so we need to // add the step. if (Incoming != WideIV) { VPValue *One = Plan.getConstantInt(CanonicalIVType, 1); - EndValue = B.createNaryOp(Instruction::Add, {EndValue, One}, DL); + EndValue = B.createAdd(EndValue, One, DL); } if (!WideIntOrFp || !WideIntOrFp->isCanonical()) { @@ -996,10 +995,14 @@ static VPValue *optimizeLatchExitInductionUser( VPlan &Plan, VPTypeAnalysis &TypeInfo, VPBlockBase *PredVPBB, VPValue *Op, DenseMap &EndValues, PredicatedScalarEvolution &PSE) { VPValue *Incoming; - if (!match(Op, m_ExtractLastLaneOfLastPart(m_VPValue(Incoming)))) - return nullptr; + VPWidenInductionRecipe *WideIV = nullptr; + if (match(Op, m_ExitingIVValue(m_VPValue(), m_VPValue(Incoming)))) { + WideIV = getOptimizableIVOf(Op->getDefiningRecipe()->getOperand(0), PSE); + assert(WideIV && "must have an optimizable IV"); + } else if (match(Op, m_ExtractLastLaneOfLastPart(m_VPValue(Incoming)))) { + WideIV = getOptimizableIVOf(Incoming, PSE); + } - auto *WideIV = getOptimizableIVOf(Incoming, PSE); if (!WideIV) return nullptr; @@ -1017,13 +1020,11 @@ static VPValue *optimizeLatchExitInductionUser( VPValue *Step = WideIV->getStepValue(); Type *ScalarTy = TypeInfo.inferScalarType(WideIV); if (ScalarTy->isIntegerTy()) - return B.createNaryOp(Instruction::Sub, {EndValue, Step}, - DebugLoc::getUnknown(), "ind.escape"); + return B.createSub(EndValue, Step, DebugLoc::getUnknown(), "ind.escape"); if (ScalarTy->isPointerTy()) { Type *StepTy = TypeInfo.inferScalarType(Step); auto *Zero = Plan.getConstantInt(StepTy, 0); - return B.createPtrAdd(EndValue, - B.createNaryOp(Instruction::Sub, {Zero, Step}), + return B.createPtrAdd(EndValue, B.createSub(Zero, Step), DebugLoc::getUnknown(), "ind.escape"); } if (ScalarTy->isFloatingPointTy()) { @@ -1258,9 +1259,9 @@ static void simplifyRecipe(VPSingleDefRecipe *Def, VPTypeAnalysis &TypeInfo) { #endif } - // Simplify (X && Y) || (X && !Y) -> X. - // TODO: Split up into simpler, modular combines: (X && Y) || (X && Z) into X - // && (Y || Z) and (X || !X) into true. This requires queuing newly created + // Simplify (X && Y) | (X && !Y) -> X. + // TODO: Split up into simpler, modular combines: (X && Y) | (X && Z) into X + // && (Y | Z) and (X | !X) into true. This requires queuing newly created // recipes to be visited during simplification. VPValue *X, *Y, *Z; if (match(Def, @@ -1289,11 +1290,15 @@ static void simplifyRecipe(VPSingleDefRecipe *Def, VPTypeAnalysis &TypeInfo) { if (match(Def, m_c_BinaryAnd(m_VPValue(X), m_ZeroInt()))) return Def->replaceAllUsesWith(Def->getOperand(Def->getOperand(0) == X)); + // x & AllOnes -> x + if (match(Def, m_c_BinaryAnd(m_VPValue(X), m_AllOnes()))) + return Def->replaceAllUsesWith(X); + // x && false -> false if (match(Def, m_LogicalAnd(m_VPValue(X), m_False()))) return Def->replaceAllUsesWith(Def->getOperand(1)); - // (x && y) || (x && z) -> x && (y || z) + // (x && y) | (x && z) -> x && (y | z) if (match(Def, m_c_BinaryOr(m_LogicalAnd(m_VPValue(X), m_VPValue(Y)), m_LogicalAnd(m_Deferred(X), m_VPValue(Z)))) && // Simplify only if one of the operands has one use to avoid creating an @@ -1357,8 +1362,8 @@ static void simplifyRecipe(VPSingleDefRecipe *Def, VPTypeAnalysis &TypeInfo) { APC->isPowerOf2()) return Def->replaceAllUsesWith(Builder.createNaryOp( Instruction::LShr, - {A, Plan->getConstantInt(APC->getBitWidth(), APC->exactLogBase2())}, {}, - Def->getDebugLoc())); + {A, Plan->getConstantInt(APC->getBitWidth(), APC->exactLogBase2())}, + *cast(Def), Def->getDebugLoc())); if (match(Def, m_Not(m_VPValue(A)))) { if (match(A, m_Not(m_VPValue(A)))) @@ -1791,7 +1796,7 @@ static void simplifyBlends(VPlan &Plan) { auto *NewBlend = new VPBlendRecipe(cast_or_null(Blend->getUnderlyingValue()), - OperandsWithMask, Blend->getDebugLoc()); + OperandsWithMask, *Blend, Blend->getDebugLoc()); NewBlend->insertBefore(&R); VPValue *DeadMask = Blend->getMask(StartIndex); @@ -1874,7 +1879,8 @@ static bool optimizeVectorInductionWidthForTCAndVFUF(VPlan &Plan, WideIV->setStepValue(NewStep); auto *NewBTC = new VPWidenCastRecipe( - Instruction::Trunc, Plan.getOrCreateBackedgeTakenCount(), NewIVTy); + Instruction::Trunc, Plan.getOrCreateBackedgeTakenCount(), NewIVTy, + nullptr, VPIRFlags::getDefaultFlags(Instruction::Trunc)); Plan.getVectorPreheader()->appendRecipe(NewBTC); auto *Cmp = cast(WideIV->getSingleUser()); Cmp->setOperand(1, NewBTC); @@ -2381,8 +2387,7 @@ bool VPlanTransforms::adjustFixedOrderRecurrences(VPlan &Plan, Type *I64Ty = Type::getInt64Ty(Plan.getContext()); VPValue *Zero = Plan.getOrAddLiveIn(ConstantInt::get(I64Ty, 0)); VPValue *One = Plan.getOrAddLiveIn(ConstantInt::get(I64Ty, 1)); - VPValue *PenultimateIndex = - B.createNaryOp(Instruction::Sub, {LastActiveLane, One}); + VPValue *PenultimateIndex = B.createSub(LastActiveLane, One); VPValue *PenultimateLastIter = B.createNaryOp(VPInstruction::ExtractLane, {PenultimateIndex, FOR->getBackedgeValue()}); @@ -2555,6 +2560,66 @@ static void licm(VPlan &Plan) { R.moveBefore(*Preheader, Preheader->end()); } } + +#ifndef NDEBUG + VPDominatorTree VPDT(Plan); +#endif + // Sink recipes with no users inside the vector loop region if all users are + // in the same exit block of the region. + // TODO: Extend to sink recipes from inner loops. + for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly( + vp_post_order_shallow(LoopRegion->getEntry()))) { + for (VPRecipeBase &R : make_early_inc_range(reverse(*VPBB))) { + if (cannotHoistOrSinkRecipe(R)) + continue; + + // TODO: Support sinking VPReplicateRecipe after ensuring replicateByVF + // handles sunk recipes correctly. + if (isa(&R)) + continue; + + // TODO: Use R.definedValues() instead of casting to VPSingleDefRecipe to + // support recipes with multiple defined values (e.g., interleaved loads). + auto *Def = cast(&R); + // Skip recipes without users as we cannot determine a sink block. + // TODO: Clone sinkable recipes without users to all exit blocks to reduce + // their execution frequency. + if (Def->getNumUsers() == 0) + continue; + + VPBasicBlock *SinkBB = nullptr; + // Cannot sink the recipe if any user + // * is defined in any loop region, or + // * is a phi, or + // * multiple users in different blocks. + if (any_of(Def->users(), [&SinkBB](VPUser *U) { + auto *UserR = cast(U); + VPBasicBlock *Parent = UserR->getParent(); + // TODO: If the user is a PHI node, we should check the block of + // incoming value. Support PHI node users if needed. + if (UserR->isPhi() || Parent->getEnclosingLoopRegion()) + return true; + // TODO: Support sinking when users are in multiple blocks. + if (SinkBB && SinkBB != Parent) + return true; + SinkBB = Parent; + return false; + })) + continue; + + // Only sink to dedicated exit blocks of the loop region. + if (SinkBB->getSinglePredecessor() != LoopRegion) + continue; + + // TODO: This will need to be a check instead of a assert after + // conditional branches in vectorized loops are supported. + assert(VPDT.properlyDominates(VPBB, SinkBB) && + "Defining block must dominate sink block"); + // TODO: Clone the recipe if users are on multiple exit paths, instead of + // just moving. + Def->moveBefore(*SinkBB, SinkBB->getFirstNonPhi()); + } + } } void VPlanTransforms::truncateToMinimalBitwidths( @@ -2604,8 +2669,9 @@ void VPlanTransforms::truncateToMinimalBitwidths( if (OldResSizeInBits != NewResSizeInBits && !match(&R, m_ICmp(m_VPValue(), m_VPValue()))) { // Extend result to original width. - auto *Ext = - new VPWidenCastRecipe(Instruction::ZExt, ResultVPV, OldResTy); + auto *Ext = new VPWidenCastRecipe( + Instruction::ZExt, ResultVPV, OldResTy, nullptr, + VPIRFlags::getDefaultFlags(Instruction::ZExt)); Ext->insertAfter(&R); ResultVPV->replaceAllUsesWith(Ext); Ext->setOperand(0, ResultVPV); @@ -2811,52 +2877,6 @@ static VPActiveLaneMaskPHIRecipe *addVPLaneMaskPhiAndUpdateExitBranch( return LaneMaskPhi; } -/// Collect the header mask with the pattern: -/// (ICMP_ULE, WideCanonicalIV, backedge-taken-count) -/// TODO: Introduce explicit recipe for header-mask instead of searching -/// for the header-mask pattern manually. -static VPSingleDefRecipe *findHeaderMask(VPlan &Plan) { - VPRegionBlock *LoopRegion = Plan.getVectorLoopRegion(); - SmallVector WideCanonicalIVs; - auto *FoundWidenCanonicalIVUser = find_if( - LoopRegion->getCanonicalIV()->users(), IsaPred); - assert(count_if(LoopRegion->getCanonicalIV()->users(), - IsaPred) <= 1 && - "Must have at most one VPWideCanonicalIVRecipe"); - if (FoundWidenCanonicalIVUser != - LoopRegion->getCanonicalIV()->users().end()) { - auto *WideCanonicalIV = - cast(*FoundWidenCanonicalIVUser); - WideCanonicalIVs.push_back(WideCanonicalIV); - } - - // Also include VPWidenIntOrFpInductionRecipes that represent a widened - // version of the canonical induction. - VPBasicBlock *HeaderVPBB = LoopRegion->getEntryBasicBlock(); - for (VPRecipeBase &Phi : HeaderVPBB->phis()) { - auto *WidenOriginalIV = dyn_cast(&Phi); - if (WidenOriginalIV && WidenOriginalIV->isCanonical()) - WideCanonicalIVs.push_back(WidenOriginalIV); - } - - // Walk users of wide canonical IVs and find the single compare of the form - // (ICMP_ULE, WideCanonicalIV, backedge-taken-count). - VPSingleDefRecipe *HeaderMask = nullptr; - for (auto *Wide : WideCanonicalIVs) { - for (VPUser *U : Wide->users()) { - auto *VPI = dyn_cast(U); - if (!VPI || !vputils::isHeaderMask(VPI, Plan)) - continue; - - assert(VPI->getOperand(0) == Wide && - "WidenCanonicalIV must be the first operand of the compare"); - assert(!HeaderMask && "Multiple header masks found?"); - HeaderMask = VPI; - } - } - return HeaderMask; -} - void VPlanTransforms::addActiveLaneMask( VPlan &Plan, bool UseActiveLaneMaskForControlFlow, bool DataAndControlFlowWithoutRuntimeCheck) { @@ -2870,7 +2890,7 @@ void VPlanTransforms::addActiveLaneMask( LoopRegion->getCanonicalIV()->users(), IsaPred); assert(FoundWidenCanonicalIVUser && "Must have widened canonical IV when tail folding!"); - VPSingleDefRecipe *HeaderMask = findHeaderMask(Plan); + VPSingleDefRecipe *HeaderMask = vputils::findHeaderMask(Plan); auto *WideCanonicalIV = cast(*FoundWidenCanonicalIVUser); VPSingleDefRecipe *LaneMask; @@ -3009,8 +3029,9 @@ static VPRecipeBase *optimizeMaskToEVL(VPValue *HeaderMask, Type *Ty = TypeInfo.inferScalarType(CurRecipe.getVPSingleValue()); VPValue *ZExt = VPBuilder(&CurRecipe).createScalarCast(Instruction::ZExt, &EVL, Ty, DL); - return new VPInstruction(Instruction::Sub, - {ZExt, Plan->getConstantInt(Ty, 1)}, {}, {}, DL); + return new VPInstruction( + Instruction::Sub, {ZExt, Plan->getConstantInt(Ty, 1)}, + VPIRFlags::getDefaultFlags(Instruction::Sub), {}, DL); } return nullptr; @@ -3122,7 +3143,7 @@ static void fixupVFUsersForEVL(VPlan &Plan, VPValue &EVL) { } } - VPValue *HeaderMask = findHeaderMask(Plan); + VPValue *HeaderMask = vputils::findHeaderMask(Plan); if (!HeaderMask) return; @@ -3234,16 +3255,15 @@ void VPlanTransforms::addExplicitVectorLength( OpVPEVL = Builder.createScalarZExtOrTrunc( OpVPEVL, CanIVTy, I32Ty, CanonicalIVIncrement->getDebugLoc()); - auto *NextEVLIV = Builder.createOverflowingOp( - Instruction::Add, {OpVPEVL, EVLPhi}, + auto *NextEVLIV = Builder.createAdd( + OpVPEVL, EVLPhi, CanonicalIVIncrement->getDebugLoc(), "index.evl.next", {CanonicalIVIncrement->hasNoUnsignedWrap(), - CanonicalIVIncrement->hasNoSignedWrap()}, - CanonicalIVIncrement->getDebugLoc(), "index.evl.next"); + CanonicalIVIncrement->hasNoSignedWrap()}); EVLPhi->addOperand(NextEVLIV); - VPValue *NextAVL = Builder.createOverflowingOp( - Instruction::Sub, {AVLPhi, OpVPEVL}, {/*hasNUW=*/true, /*hasNSW=*/false}, - DebugLoc::getCompilerGenerated(), "avl.next"); + VPValue *NextAVL = + Builder.createSub(AVLPhi, OpVPEVL, DebugLoc::getCompilerGenerated(), + "avl.next", {/*NUW=*/true, /*NSW=*/false}); AVLPhi->addOperand(NextAVL); fixupVFUsersForEVL(Plan, *VPEVL); @@ -3443,9 +3463,8 @@ void VPlanTransforms::dropPoisonGeneratingRecipes( if (match(RecWithFlags, m_BinaryOr(m_VPValue(A), m_VPValue(B))) && RecWithFlags->isDisjoint()) { VPBuilder Builder(RecWithFlags); - VPInstruction *New = Builder.createOverflowingOp( - Instruction::Add, {A, B}, {false, false}, - RecWithFlags->getDebugLoc()); + VPInstruction *New = + Builder.createAdd(A, B, RecWithFlags->getDebugLoc()); New->setUnderlyingValue(RecWithFlags->getUnderlyingValue()); RecWithFlags->replaceAllUsesWith(New); RecWithFlags->eraseFromParent(); @@ -3764,8 +3783,8 @@ static void expandVPWidenPointerInduction(VPWidenPointerInductionRecipe *R, Type *StepTy = TypeInfo.inferScalarType(Step); VPValue *Offset = Builder.createNaryOp(VPInstruction::StepVector, {}, StepTy); Offset = Builder.createOverflowingOp(Instruction::Mul, {Offset, Step}); - VPValue *PtrAdd = Builder.createNaryOp( - VPInstruction::WidePtrAdd, {ScalarPtrPhi, Offset}, DL, "vector.gep"); + VPValue *PtrAdd = + Builder.createWidePtrAdd(ScalarPtrPhi, Offset, DL, "vector.gep"); R->replaceAllUsesWith(PtrAdd); // Create the backedge value for the scalar pointer phi. @@ -3879,7 +3898,7 @@ void VPlanTransforms::convertToConcreteRecipes(VPlan &Plan) { for (unsigned I = 1; I != Blend->getNumIncomingValues(); ++I) Select = Builder.createSelect(Blend->getMask(I), Blend->getIncomingValue(I), Select, - R.getDebugLoc(), "predphi"); + R.getDebugLoc(), "predphi", *Blend); Blend->replaceAllUsesWith(Select); ToRemove.push_back(Blend); } @@ -3908,9 +3927,9 @@ void VPlanTransforms::convertToConcreteRecipes(VPlan &Plan) { // Subtract 1 to get the last active lane. VPValue *One = Plan.getOrAddLiveIn( ConstantInt::get(Type::getInt64Ty(Plan.getContext()), 1)); - VPValue *LastLane = Builder.createNaryOp( - Instruction::Sub, {FirstInactiveLane, One}, - LastActiveL->getDebugLoc(), "last.active.lane"); + VPValue *LastLane = + Builder.createSub(FirstInactiveLane, One, + LastActiveL->getDebugLoc(), "last.active.lane"); LastActiveL->replaceAllUsesWith(LastLane); ToRemove.push_back(LastActiveL); @@ -3951,11 +3970,15 @@ void VPlanTransforms::convertToConcreteRecipes(VPlan &Plan) { } VPIRFlags Flags; - if (IVTy->isFloatingPointTy()) - Flags = {VPI->getFastMathFlags()}; + unsigned MulOpc; + if (IVTy->isFloatingPointTy()) { + MulOpc = Instruction::FMul; + Flags = VPI->getFastMathFlags(); + } else { + MulOpc = Instruction::Mul; + Flags = VPIRFlags::getDefaultFlags(MulOpc); + } - unsigned MulOpc = - IVTy->isFloatingPointTy() ? Instruction::FMul : Instruction::Mul; VPInstruction *Mul = Builder.createNaryOp( MulOpc, {VectorStep, ScalarStep}, Flags, R.getDebugLoc()); VectorStep = Mul; @@ -4702,9 +4725,9 @@ void VPlanTransforms::materializeBackedgeTakenCount(VPlan &Plan, VPBuilder Builder(VectorPH, VectorPH->begin()); auto *TCTy = VPTypeAnalysis(Plan).inferScalarType(Plan.getTripCount()); - auto *TCMO = Builder.createNaryOp( - Instruction::Sub, {Plan.getTripCount(), Plan.getConstantInt(TCTy, 1)}, - DebugLoc::getCompilerGenerated(), "trip.count.minus.1"); + auto *TCMO = + Builder.createSub(Plan.getTripCount(), Plan.getConstantInt(TCTy, 1), + DebugLoc::getCompilerGenerated(), "trip.count.minus.1"); BTC->replaceAllUsesWith(TCMO); } @@ -4825,10 +4848,8 @@ void VPlanTransforms::materializeVectorTripCount(VPlan &Plan, // For scalable vectors the VF is not guaranteed to be a power of 2, but this // is accounted for in emitIterationCountCheck that adds an overflow check. if (TailByMasking) { - TC = Builder.createNaryOp( - Instruction::Add, - {TC, Builder.createNaryOp(Instruction::Sub, - {Step, Plan.getConstantInt(TCTy, 1)})}, + TC = Builder.createAdd( + TC, Builder.createSub(Step, Plan.getConstantInt(TCTy, 1)), DebugLoc::getCompilerGenerated(), "n.rnd.up"); } @@ -4855,8 +4876,8 @@ void VPlanTransforms::materializeVectorTripCount(VPlan &Plan, R = Builder.createSelect(IsZero, Step, R); } - VPValue *Res = Builder.createNaryOp( - Instruction::Sub, {TC, R}, DebugLoc::getCompilerGenerated(), "n.vec"); + VPValue *Res = + Builder.createSub(TC, R, DebugLoc::getCompilerGenerated(), "n.vec"); VectorTC.replaceAllUsesWith(Res); } @@ -5409,6 +5430,101 @@ void VPlanTransforms::addExitUsersForFirstOrderRecurrences(VPlan &Plan, } } +void VPlanTransforms::optimizeFindIVReductions(VPlan &Plan, + PredicatedScalarEvolution &PSE, + Loop &L) { + ScalarEvolution &SE = *PSE.getSE(); + VPRegionBlock *VectorLoopRegion = Plan.getVectorLoopRegion(); + + // Helper lambda to check if the IV range excludes the sentinel value. + auto CheckSentinel = [&SE](const SCEV *IVSCEV, bool UseMax, + bool Signed) -> std::optional { + unsigned BW = IVSCEV->getType()->getScalarSizeInBits(); + APInt Sentinel = + UseMax + ? (Signed ? APInt::getSignedMinValue(BW) : APInt::getMinValue(BW)) + : (Signed ? APInt::getSignedMaxValue(BW) : APInt::getMaxValue(BW)); + + ConstantRange IVRange = + Signed ? SE.getSignedRange(IVSCEV) : SE.getUnsignedRange(IVSCEV); + if (!IVRange.contains(Sentinel)) + return Sentinel; + return std::nullopt; + }; + + for (VPRecipeBase &Phi : + make_early_inc_range(VectorLoopRegion->getEntryBasicBlock()->phis())) { + auto *PhiR = dyn_cast(&Phi); + if (!PhiR || !RecurrenceDescriptor::isFindLastRecurrenceKind( + PhiR->getRecurrenceKind())) + continue; + + // Get the IV from the backedge value of the reduction phi. + // The backedge value should be a select between the phi and the IV. + VPValue *BackedgeVal = PhiR->getBackedgeValue(); + VPValue *TrueVal, *FalseVal; + if (!match(BackedgeVal, + m_Select(m_VPValue(), m_VPValue(TrueVal), m_VPValue(FalseVal)))) + continue; + + // The non-phi operand of the select is the IV. + assert(is_contained(BackedgeVal->getDefiningRecipe()->operands(), PhiR)); + VPValue *IV = TrueVal == PhiR ? FalseVal : TrueVal; + + const SCEV *IVSCEV = vputils::getSCEVExprForVPValue(IV, PSE, &L); + const SCEV *Step; + if (!match(IVSCEV, m_scev_AffineAddRec(m_SCEV(), m_SCEV(Step)))) + continue; + + // Determine direction from SCEV step. + if (!SE.isKnownNonZero(Step)) + continue; + + // Positive step means we need UMax/SMax to find the last IV value, and + // UMin/SMin otherwise. + bool UseMax = SE.isKnownPositive(Step); + bool UseSigned = true; + std::optional SentinelVal = + CheckSentinel(IVSCEV, UseMax, /*IsSigned=*/true); + if (!SentinelVal) { + SentinelVal = CheckSentinel(IVSCEV, UseMax, /*IsSigned=*/false); + if (!SentinelVal) + continue; + UseSigned = false; + } + + auto *RdxResult = cast(vputils::findRecipe( + BackedgeVal, + match_fn(m_VPInstruction()))); + + // Create the reduction result in the middle block using sentinel directly. + RecurKind MinMaxKind = + UseMax ? (UseSigned ? RecurKind::SMax : RecurKind::UMax) + : (UseSigned ? RecurKind::SMin : RecurKind::UMin); + VPIRFlags Flags(MinMaxKind, /*IsOrdered=*/false, /*IsInLoop=*/false, + FastMathFlags()); + VPValue *Sentinel = Plan.getConstantInt(*SentinelVal); + DebugLoc ExitDL = RdxResult->getDebugLoc(); + VPBuilder MiddleBuilder(RdxResult); + VPValue *ReducedIV = + MiddleBuilder.createNaryOp(VPInstruction::ComputeReductionResult, + RdxResult->getOperand(0), Flags, ExitDL); + auto *Cmp = + MiddleBuilder.createICmp(CmpInst::ICMP_NE, ReducedIV, Sentinel, ExitDL); + VPInstruction *NewRdxResult = MiddleBuilder.createSelect( + Cmp, ReducedIV, PhiR->getStartValue(), ExitDL); + RdxResult->replaceAllUsesWith(NewRdxResult); + RdxResult->eraseFromParent(); + + auto *NewPhiR = new VPReductionPHIRecipe( + cast(PhiR->getUnderlyingInstr()), RecurKind::FindIV, *Sentinel, + *BackedgeVal, RdxUnordered{1}, PhiR->hasUsesOutsideReductionChain()); + NewPhiR->insertBefore(PhiR); + PhiR->replaceAllUsesWith(NewPhiR); + PhiR->eraseFromParent(); + } +} + namespace { /// A chain of recipes that form a partial reduction. Matches either @@ -5517,12 +5633,6 @@ static bool transformToPartialReduction(const VPPartialReductionChain &Chain, auto *NewScaleFactor = Plan.getConstantInt(32, ScaleFactor); StartInst->setOperand(2, NewScaleFactor); - // Find the ComputeReductionResult that uses the WidenRecipe (the exit - // value). Look through selects for predicated reductions. - if (auto *RdxResult = vputils::findComputeReductionResult(RdxPhi)) { - ExitValue = RdxResult->getOperand(0); - match(ExitValue, m_Select(m_VPValue(Cond), m_VPValue(), m_VPValue())); - } } // Handle SUB by negating the operand and using ADD for the partial reduction. @@ -5539,6 +5649,16 @@ static bool transformToPartialReduction(const VPPartialReductionChain &Chain, BinOp = NegRecipe; } + // Check if WidenRecipe is the final result of the reduction. If so look + // through selects for predicated reductions. + VPReductionPHIRecipe *RdxPhi; + ExitValue = cast_or_null(vputils::findUserOf( + WidenRecipe, m_Select(m_VPValue(Cond), m_Specific(WidenRecipe), + m_ReductionPhi(RdxPhi)))); + assert(!ExitValue || RdxPhi->getBackedgeValue() == WidenRecipe || + RdxPhi->getBackedgeValue() == ExitValue && + "if we found ExitValue, it must match RdxPhi's backedge value"); + RecurKind RdxKind = PhiType->isFloatingPointTy() ? RecurKind::FAdd : RecurKind::Add; auto *PartialRed = new VPReductionRecipe( diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h index 49d15f15ece94..dec8b4fd6a1d8 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h @@ -127,11 +127,9 @@ struct VPlanTransforms { /// Create VPReductionRecipes for in-loop reductions. This processes chains /// of operations contributing to in-loop reductions and creates appropriate - /// VPReductionRecipe instances. Block masks from \p BlockMaskCache are used - /// to add predication for blocks in \p BlocksNeedingPredication. + /// VPReductionRecipe instances. static void createInLoopReductionRecipes( - VPlan &Plan, const DenseMap &BlockMaskCache, - const DenseSet &BlocksNeedingPredication, + VPlan &Plan, const DenseSet &BlocksNeedingPredication, ElementCount MinVF); /// Update \p Plan to account for all early exits. @@ -429,12 +427,8 @@ struct VPlanTransforms { /// Predicate and linearize the control-flow in the only loop region of /// \p Plan. If \p FoldTail is true, create a mask guarding the loop - /// header, otherwise use all-true for the header mask. Masks for blocks are - /// added to a block-to-mask map which is returned in order to be used later - /// for wide recipe construction. This argument is temporary and will be - /// removed in the future. - static DenseMap - introduceMasksAndLinearize(VPlan &Plan, bool FoldTail); + /// header, otherwise use all-true for the header mask. + static void introduceMasksAndLinearize(VPlan &Plan, bool FoldTail); /// Add branch weight metadata, if the \p Plan's middle block is terminated by /// a BranchOnCond recipe. @@ -455,6 +449,11 @@ struct VPlanTransforms { /// LCSSA phi. static void addExitUsersForFirstOrderRecurrences(VPlan &Plan, VFRange &Range); + /// Optimize FindLast reductions selecting IVs by converting them to FindIV + /// reductions, if their IV range excludes a suitable sentinel value. + static void optimizeFindIVReductions(VPlan &Plan, + PredicatedScalarEvolution &PSE, Loop &L); + /// Detect and create partial reduction recipes for scaled reductions in /// \p Plan. Must be called after recipe construction. If partial reductions /// are only valid for a subset of VFs in Range, Range.End is updated. diff --git a/llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp b/llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp index 75b8164a33a7f..53cac9fcd80d6 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp @@ -210,22 +210,28 @@ void UnrollState::unrollWidenInductionByUF( VPValue *Prev = IV; Builder.setInsertPoint(IV->getParent(), InsertPtForPhi); unsigned AddOpc; - if (IVTy->isPointerTy()) + VPIRFlags AddFlags; + if (IVTy->isPointerTy()) { AddOpc = VPInstruction::WidePtrAdd; - else if (IVTy->isFloatingPointTy()) + AddFlags = GEPNoWrapFlags::none(); + } else if (IVTy->isFloatingPointTy()) { AddOpc = ID.getInductionOpcode(); - else + AddFlags = Flags; // FMF flags + } else { AddOpc = Instruction::Add; + AddFlags = VPIRFlags::getDefaultFlags(AddOpc); + } for (unsigned Part = 1; Part != UF; ++Part) { std::string Name = Part > 1 ? "step.add." + std::to_string(Part) : "step.add"; - VPInstruction *Add = Builder.createNaryOp(AddOpc, - { - Prev, - VectorStep, - }, - Flags, IV->getDebugLoc(), Name); + VPInstruction *Add = + Builder.createNaryOp(AddOpc, + { + Prev, + VectorStep, + }, + AddFlags, IV->getDebugLoc(), Name); ToSkip.insert(Add); addRecipeForPart(IV, Add, Part); Prev = Add; @@ -581,6 +587,9 @@ cloneForLane(VPlan &Plan, VPBuilder &Builder, Type *IdxTy, } void VPlanTransforms::replicateByVF(VPlan &Plan, ElementCount VF) { + if (Plan.hasScalarVFOnly()) + return; + Type *IdxTy = IntegerType::get( Plan.getScalarHeader()->getIRBasicBlock()->getContext(), 32); diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp index 9c013b27c17ab..7de505f688e8b 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp @@ -563,6 +563,48 @@ vputils::getRecipesForUncountableExit(VPlan &Plan, return UncountableCondition; } +VPSingleDefRecipe *vputils::findHeaderMask(VPlan &Plan) { + VPRegionBlock *LoopRegion = Plan.getVectorLoopRegion(); + SmallVector WideCanonicalIVs; + auto *FoundWidenCanonicalIVUser = find_if( + LoopRegion->getCanonicalIV()->users(), IsaPred); + assert(count_if(LoopRegion->getCanonicalIV()->users(), + IsaPred) <= 1 && + "Must have at most one VPWideCanonicalIVRecipe"); + if (FoundWidenCanonicalIVUser != + LoopRegion->getCanonicalIV()->users().end()) { + auto *WideCanonicalIV = + cast(*FoundWidenCanonicalIVUser); + WideCanonicalIVs.push_back(WideCanonicalIV); + } + + // Also include VPWidenIntOrFpInductionRecipes that represent a widened + // version of the canonical induction. + VPBasicBlock *HeaderVPBB = LoopRegion->getEntryBasicBlock(); + for (VPRecipeBase &Phi : HeaderVPBB->phis()) { + auto *WidenOriginalIV = dyn_cast(&Phi); + if (WidenOriginalIV && WidenOriginalIV->isCanonical()) + WideCanonicalIVs.push_back(WidenOriginalIV); + } + + // Walk users of wide canonical IVs and find the single compare of the form + // (ICMP_ULE, WideCanonicalIV, backedge-taken-count). + VPSingleDefRecipe *HeaderMask = nullptr; + for (auto *Wide : WideCanonicalIVs) { + for (VPUser *U : Wide->users()) { + auto *VPI = dyn_cast(U); + if (!VPI || !vputils::isHeaderMask(VPI, Plan)) + continue; + + assert(VPI->getOperand(0) == Wide && + "WidenCanonicalIV must be the first operand of the compare"); + assert(!HeaderMask && "Multiple header masks found?"); + HeaderMask = VPI; + } + } + return HeaderMask; +} + bool VPBlockUtils::isHeader(const VPBlockBase *VPB, const VPDominatorTree &VPDT) { auto *VPBB = dyn_cast(VPB); diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.h b/llvm/lib/Transforms/Vectorize/VPlanUtils.h index a789f3cbb2815..a5692699d9d76 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanUtils.h +++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.h @@ -145,6 +145,12 @@ template static VPInstruction *findUserOf(VPValue *V) { /// inserted for predicated reductions or tail folding. VPInstruction *findComputeReductionResult(VPReductionPHIRecipe *PhiR); +/// Collect the header mask with the pattern: +/// (ICMP_ULE, WideCanonicalIV, backedge-taken-count) +/// TODO: Introduce explicit recipe for header-mask instead of searching +/// the header-mask pattern manually. +VPSingleDefRecipe *findHeaderMask(VPlan &Plan); + } // namespace vputils //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index 1746d3e4b06f4..963e6e1076eec 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -2543,8 +2543,8 @@ bool VectorCombine::foldPermuteOfBinops(Instruction &I) { bool VectorCombine::foldShuffleOfBinops(Instruction &I) { ArrayRef OldMask; Instruction *LHS, *RHS; - if (!match(&I, m_Shuffle(m_OneUse(m_Instruction(LHS)), - m_OneUse(m_Instruction(RHS)), m_Mask(OldMask)))) + if (!match(&I, m_Shuffle(m_Instruction(LHS), m_Instruction(RHS), + m_Mask(OldMask)))) return false; // TODO: Add support for addlike etc. @@ -2575,6 +2575,7 @@ bool VectorCombine::foldShuffleOfBinops(Instruction &I) { if (!ShuffleDstTy || !BinResTy || !BinOpTy || X->getType() != Z->getType()) return false; + bool SameBinOp = LHS == RHS; unsigned NumSrcElts = BinOpTy->getNumElements(); // If we have something like "add X, Y" and "add Z, X", swap ops to match. @@ -2605,12 +2606,17 @@ bool VectorCombine::foldShuffleOfBinops(Instruction &I) { } // Try to replace a binop with a shuffle if the shuffle is not costly. - InstructionCost OldCost = - TTI.getInstructionCost(LHS, CostKind) + - TTI.getInstructionCost(RHS, CostKind) + - TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, ShuffleDstTy, - BinResTy, OldMask, CostKind, 0, nullptr, {LHS, RHS}, - &I); + // When SameBinOp, only count the binop cost once. + InstructionCost LHSCost = TTI.getInstructionCost(LHS, CostKind); + InstructionCost RHSCost = TTI.getInstructionCost(RHS, CostKind); + + InstructionCost OldCost = LHSCost; + if (!SameBinOp) { + OldCost += RHSCost; + } + OldCost += TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, + ShuffleDstTy, BinResTy, OldMask, CostKind, 0, + nullptr, {LHS, RHS}, &I); // Handle shuffle(binop(shuffle(x),y),binop(z,shuffle(w))) style patterns // where one use shuffles have gotten split across the binop/cmp. These @@ -2642,7 +2648,9 @@ bool VectorCombine::foldShuffleOfBinops(Instruction &I) { ReducedInstCount |= MergeInner(Z, NumSrcElts, NewMask0, CostKind); ReducedInstCount |= MergeInner(W, NumSrcElts, NewMask1, CostKind); bool SingleSrcBinOp = (X == Y) && (Z == W) && (NewMask0 == NewMask1); - ReducedInstCount |= SingleSrcBinOp; + // SingleSrcBinOp only reduces instruction count if we also eliminate the + // original binop(s). If binops have multiple uses, they won't be eliminated. + ReducedInstCount |= SingleSrcBinOp && LHS->hasOneUser() && RHS->hasOneUser(); auto *ShuffleCmpTy = FixedVectorType::get(BinOpTy->getElementType(), ShuffleDstTy); @@ -2660,6 +2668,12 @@ bool VectorCombine::foldShuffleOfBinops(Instruction &I) { TTI.getCmpSelInstrCost(LHS->getOpcode(), ShuffleCmpTy, ShuffleDstTy, PredLHS, CostKind, Op0Info, Op1Info); } + // If LHS/RHS have other uses, we need to account for the cost of keeping + // the original instructions. When SameBinOp, only add the cost once. + if (!LHS->hasOneUser()) + NewCost += LHSCost; + if (!SameBinOp && !RHS->hasOneUser()) + NewCost += RHSCost; LLVM_DEBUG(dbgs() << "Found a shuffle feeding two binops: " << I << "\n OldCost: " << OldCost << " vs NewCost: " << NewCost @@ -4603,6 +4617,10 @@ bool VectorCombine::foldEquivalentReductionCmp(Instruction &I) { return false; const auto IsValidOrUmaxCmp = [&]() { + // or === umax for i1 + if (CmpVal->getBitWidth() == 1) + return true; + // Cases a and e bool IsEquality = (CmpVal->isZero() || CmpVal->isOne()) && ICmpInst::isEquality(Pred); @@ -4615,6 +4633,10 @@ bool VectorCombine::foldEquivalentReductionCmp(Instruction &I) { }; const auto IsValidAndUminCmp = [&]() { + // and === umin for i1 + if (CmpVal->getBitWidth() == 1) + return true; + const auto LeadingOnes = CmpVal->countl_one(); // Cases g and k @@ -5420,7 +5442,7 @@ bool VectorCombine::shrinkLoadForShuffles(Instruction &I) { // Get the range of vector elements used by shufflevector instructions. if (std::optional Indices = GetIndexRangeInShuffles()) { - unsigned const NewNumElements = (Indices->second + 1) - Indices->first; + unsigned const NewNumElements = Indices->second + 1u; // If the range of vector elements is smaller than the full load, attempt // to create a smaller load. @@ -5442,28 +5464,24 @@ bool VectorCombine::shrinkLoadForShuffles(Instruction &I) { using UseEntry = std::pair>; SmallVector NewUses; - unsigned const LowOffset = Indices->first; - unsigned const HighOffset = OldNumElements - (Indices->second + 1); + unsigned const MaxIndex = NewNumElements * 2u; for (llvm::Use &Use : I.uses()) { auto *Shuffle = cast(Use.getUser()); + + // Ignore shufflevector instructions that have no uses. + if (Shuffle->use_empty()) + continue; + ArrayRef OldMask = Shuffle->getShuffleMask(); // Create entry for new use. - NewUses.push_back({Shuffle, {}}); - std::vector &NewMask = NewUses.back().second; + NewUses.push_back({Shuffle, OldMask}); + + // Validate mask indices. for (int Index : OldMask) { - // Preserve poison indices without modification. - if (Index == PoisonMaskElem) { - NewMask.push_back(Index); - continue; - } - int NewIndex = Index >= static_cast(OldNumElements) - ? Index - LowOffset - HighOffset - : Index - LowOffset; - if (NewIndex >= static_cast(NewNumElements * 2u)) + if (Index >= static_cast(MaxIndex)) return false; - NewMask.push_back(NewIndex); } // Update costs. @@ -5472,7 +5490,7 @@ bool VectorCombine::shrinkLoadForShuffles(Instruction &I) { OldLoadTy, OldMask, CostKind); NewCost += TTI.getShuffleCost(TTI::SK_PermuteSingleSrc, Shuffle->getType(), - NewLoadTy, NewMask, CostKind); + NewLoadTy, OldMask, CostKind); } LLVM_DEBUG( @@ -5484,16 +5502,8 @@ bool VectorCombine::shrinkLoadForShuffles(Instruction &I) { return false; // Create new load of smaller vector. - Type *IndexTy = DL->getIndexType(PtrOp->getType()); - TypeSize ElemSize = DL->getTypeAllocSize(ElemTy); - Value *NewPtr = - LowOffset > 0u - ? Builder.CreateInBoundsPtrAdd( - PtrOp, ConstantInt::get(IndexTy, LowOffset * ElemSize)) - : PtrOp; - auto *NewLoad = cast( - Builder.CreateAlignedLoad(NewLoadTy, NewPtr, OldLoad->getAlign())); + Builder.CreateAlignedLoad(NewLoadTy, PtrOp, OldLoad->getAlign())); NewLoad->copyMetadata(I); // Replace all uses. diff --git a/llvm/test/Analysis/CostModel/AArch64/bswap.ll b/llvm/test/Analysis/CostModel/AArch64/bswap.ll index 2df508ebe40bc..43b1d252d04ee 100644 --- a/llvm/test/Analysis/CostModel/AArch64/bswap.ll +++ b/llvm/test/Analysis/CostModel/AArch64/bswap.ll @@ -44,7 +44,7 @@ define void @neon() { ; CHECK-NEXT: Cost Model: Found costs of 1 for: %v2i64 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> undef) ; CHECK-NEXT: Cost Model: Found costs of 2 for: %v4i64 = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> undef) ; CHECK-NEXT: Cost Model: Found costs of 1 for: %v3i32 = call <3 x i32> @llvm.bswap.v3i32(<3 x i32> undef) -; CHECK-NEXT: Cost Model: Found costs of RThru:12 CodeSize:8 Lat:12 SizeLat:12 for: %v4i48 = call <4 x i48> @llvm.bswap.v4i48(<4 x i48> undef) +; CHECK-NEXT: Cost Model: Found costs of 4 for: %v4i48 = call <4 x i48> @llvm.bswap.v4i48(<4 x i48> undef) ; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; %v4i16 = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> undef) diff --git a/llvm/test/Analysis/CostModel/AArch64/insert-extract.ll b/llvm/test/Analysis/CostModel/AArch64/insert-extract.ll index a33bbd8057f33..55a14b8695a18 100644 --- a/llvm/test/Analysis/CostModel/AArch64/insert-extract.ll +++ b/llvm/test/Analysis/CostModel/AArch64/insert-extract.ll @@ -5,6 +5,12 @@ ; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=neoverse-v1 | FileCheck --check-prefixes=CHECK,GENERIC %s ; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=neoverse-v2 | FileCheck --check-prefixes=CHECK,GENERIC %s ; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=kryo | FileCheck --check-prefixes=CHECK,GENERIC %s +; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=apple-m1 | FileCheck --check-prefixes=CHECK,FAST-LD1 %s +; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=apple-m2 | FileCheck --check-prefixes=CHECK,FAST-LD1 %s +; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=apple-m3 | FileCheck --check-prefixes=CHECK,FAST-LD1 %s +; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=apple-m4 | FileCheck --check-prefixes=CHECK,FAST-LD1 %s +; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=apple-m5 | FileCheck --check-prefixes=CHECK,FAST-LD1 %s +; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mcpu=apple-latest | FileCheck --check-prefixes=CHECK,FAST-LD1 %s ; RUN: opt < %s -passes="print" -cost-kind=all 2>&1 -disable-output -mattr=+fast-ld1-single | FileCheck --check-prefixes=CHECK,FAST-LD1 %s target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" @@ -155,17 +161,11 @@ entry: ;; Multi-use tests: Check that Load context is only applied when load has one use define <8 x i8> @LD1_multi_use_load(<8 x i8> %vec, ptr noundef %i, ptr noundef %out) { -; GENERIC-LABEL: 'LD1_multi_use_load' -; GENERIC-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i8, ptr %i, align 1 -; GENERIC-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2 = insertelement <8 x i8> %vec, i8 %v1, i32 1 -; GENERIC-NEXT: Cost Model: Found costs of 1 for: store i8 %v1, ptr %out, align 1 -; GENERIC-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <8 x i8> %v2 -; -; FAST-LD1-LABEL: 'LD1_multi_use_load' -; FAST-LD1-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i8, ptr %i, align 1 -; FAST-LD1-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2 = insertelement <8 x i8> %vec, i8 %v1, i32 1 -; FAST-LD1-NEXT: Cost Model: Found costs of 1 for: store i8 %v1, ptr %out, align 1 -; FAST-LD1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <8 x i8> %v2 +; CHECK-LABEL: 'LD1_multi_use_load' +; CHECK-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:4 SizeLat:1 for: %v1 = load i8, ptr %i, align 1 +; CHECK-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %v2 = insertelement <8 x i8> %vec, i8 %v1, i32 1 +; CHECK-NEXT: Cost Model: Found costs of 1 for: store i8 %v1, ptr %out, align 1 +; CHECK-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret <8 x i8> %v2 ; entry: %v1 = load i8, ptr %i, align 1 diff --git a/llvm/test/Analysis/CostModel/AArch64/loop_dependence_mask.ll b/llvm/test/Analysis/CostModel/AArch64/loop_dependence_mask.ll index 5b3070fcf347e..74bd41db4a64d 100644 --- a/llvm/test/Analysis/CostModel/AArch64/loop_dependence_mask.ll +++ b/llvm/test/Analysis/CostModel/AArch64/loop_dependence_mask.ll @@ -17,10 +17,10 @@ define void @loop_dependence_war_mask(ptr %a, ptr %b) { ; CHECK-EXPANDED-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-LABEL: 'loop_dependence_war_mask' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res1 = call <16 x i1> @llvm.loop.dependence.war.mask.v16i1(ptr %a, ptr %b, i64 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res2 = call <8 x i1> @llvm.loop.dependence.war.mask.v8i1(ptr %a, ptr %b, i64 2) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res3 = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1(ptr %a, ptr %b, i64 4) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res4 = call <2 x i1> @llvm.loop.dependence.war.mask.v2i1(ptr %a, ptr %b, i64 8) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res1 = call <16 x i1> @llvm.loop.dependence.war.mask.v16i1(ptr %a, ptr %b, i64 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res2 = call <8 x i1> @llvm.loop.dependence.war.mask.v8i1(ptr %a, ptr %b, i64 2) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res3 = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1(ptr %a, ptr %b, i64 4) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res4 = call <2 x i1> @llvm.loop.dependence.war.mask.v2i1(ptr %a, ptr %b, i64 8) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res5 = call @llvm.loop.dependence.war.mask.nxv16i1(ptr %a, ptr %b, i64 1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res6 = call @llvm.loop.dependence.war.mask.nxv8i1(ptr %a, ptr %b, i64 2) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res7 = call @llvm.loop.dependence.war.mask.nxv4i1(ptr %a, ptr %b, i64 4) @@ -54,10 +54,10 @@ define void @loop_dependence_raw_mask(ptr %a, ptr %b) { ; CHECK-EXPANDED-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-LABEL: 'loop_dependence_raw_mask' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res1 = call <16 x i1> @llvm.loop.dependence.raw.mask.v16i1(ptr %a, ptr %b, i64 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res2 = call <8 x i1> @llvm.loop.dependence.raw.mask.v8i1(ptr %a, ptr %b, i64 2) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res3 = call <4 x i1> @llvm.loop.dependence.raw.mask.v4i1(ptr %a, ptr %b, i64 4) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res4 = call <2 x i1> @llvm.loop.dependence.raw.mask.v2i1(ptr %a, ptr %b, i64 8) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res1 = call <16 x i1> @llvm.loop.dependence.raw.mask.v16i1(ptr %a, ptr %b, i64 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res2 = call <8 x i1> @llvm.loop.dependence.raw.mask.v8i1(ptr %a, ptr %b, i64 2) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res3 = call <4 x i1> @llvm.loop.dependence.raw.mask.v4i1(ptr %a, ptr %b, i64 4) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res4 = call <2 x i1> @llvm.loop.dependence.raw.mask.v2i1(ptr %a, ptr %b, i64 8) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res5 = call @llvm.loop.dependence.raw.mask.nxv16i1(ptr %a, ptr %b, i64 1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res6 = call @llvm.loop.dependence.raw.mask.nxv8i1(ptr %a, ptr %b, i64 2) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res7 = call @llvm.loop.dependence.raw.mask.nxv4i1(ptr %a, ptr %b, i64 4) diff --git a/llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll b/llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll index ab9d7f9dc859d..99a9bc2ec04f7 100644 --- a/llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll +++ b/llvm/test/Analysis/CostModel/AMDGPU/fdiv.ll @@ -739,5 +739,5 @@ define i32 @frem(i32 %arg) { ret i32 undef } -attributes #0 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: ieee|ieee) } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll b/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll index adb1a72bb93ea..a953ba8a532c2 100644 --- a/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll +++ b/llvm/test/Analysis/CostModel/ARM/arith-overflow.ll @@ -431,57 +431,57 @@ declare {<64 x i8>, <64 x i1>} @llvm.smul.with.overflow.v64i8(<64 x i8>, <64 x define i32 @smul(i32 %arg) { ; V8M-LABEL: 'smul' -; V8M-NEXT: Cost Model: Found costs of 15 for: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) -; V8M-NEXT: Cost Model: Found costs of RThru:82 CodeSize:30 Lat:30 SizeLat:30 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:164 CodeSize:56 Lat:56 SizeLat:56 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:328 CodeSize:108 Lat:108 SizeLat:108 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-NEXT: Cost Model: Found costs of 8 for: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) -; V8M-NEXT: Cost Model: Found costs of RThru:68 CodeSize:30 Lat:30 SizeLat:30 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:136 CodeSize:58 Lat:58 SizeLat:58 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:272 CodeSize:114 Lat:114 SizeLat:114 for: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-NEXT: Cost Model: Found costs of 6 for: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) -; V8M-NEXT: Cost Model: Found costs of RThru:56 CodeSize:42 Lat:42 SizeLat:42 for: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:112 CodeSize:82 Lat:82 SizeLat:82 for: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:224 CodeSize:162 Lat:162 SizeLat:162 for: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-NEXT: Cost Model: Found costs of 6 for: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) -; V8M-NEXT: Cost Model: Found costs of RThru:112 CodeSize:82 Lat:82 SizeLat:82 for: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:224 CodeSize:162 Lat:162 SizeLat:162 for: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:448 CodeSize:322 Lat:322 SizeLat:322 for: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) +; V8M-NEXT: Cost Model: Found costs of 8 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-NEXT: Cost Model: Found costs of 16 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-NEXT: Cost Model: Found costs of 32 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) +; V8M-NEXT: Cost Model: Found costs of 8 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-NEXT: Cost Model: Found costs of 16 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-NEXT: Cost Model: Found costs of 32 for: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-NEXT: Cost Model: Found costs of 2 for: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) +; V8M-NEXT: Cost Model: Found costs of 16 for: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-NEXT: Cost Model: Found costs of 32 for: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-NEXT: Cost Model: Found costs of 64 for: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-NEXT: Cost Model: Found costs of 2 for: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) +; V8M-NEXT: Cost Model: Found costs of 32 for: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-NEXT: Cost Model: Found costs of 64 for: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-NEXT: Cost Model: Found costs of 128 for: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef ; ; NEON-LABEL: 'smul' -; NEON-NEXT: Cost Model: Found costs of RThru:15 CodeSize:8 Lat:8 SizeLat:8 for: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) +; NEON-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) ; NEON-NEXT: Cost Model: Found costs of RThru:83 CodeSize:12 Lat:12 SizeLat:12 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:162 CodeSize:13 Lat:13 SizeLat:13 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:320 CodeSize:15 Lat:15 SizeLat:15 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-NEXT: Cost Model: Found costs of RThru:8 CodeSize:6 Lat:6 SizeLat:6 for: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) +; NEON-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) ; NEON-NEXT: Cost Model: Found costs of RThru:21 CodeSize:10 Lat:10 SizeLat:10 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:38 CodeSize:11 Lat:11 SizeLat:11 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:72 CodeSize:13 Lat:13 SizeLat:13 for: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-NEXT: Cost Model: Found costs of 6 for: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) +; NEON-NEXT: Cost Model: Found costs of 2 for: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) ; NEON-NEXT: Cost Model: Found costs of RThru:23 CodeSize:8 Lat:8 SizeLat:8 for: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:46 CodeSize:9 Lat:9 SizeLat:9 for: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:92 CodeSize:11 Lat:11 SizeLat:11 for: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-NEXT: Cost Model: Found costs of 6 for: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) +; NEON-NEXT: Cost Model: Found costs of 2 for: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) ; NEON-NEXT: Cost Model: Found costs of RThru:23 CodeSize:8 Lat:8 SizeLat:8 for: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:46 CodeSize:9 Lat:9 SizeLat:9 for: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:92 CodeSize:11 Lat:11 SizeLat:11 for: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef ; ; MVE-LABEL: 'smul' -; MVE-NEXT: Cost Model: Found costs of 15 for: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) +; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 undef, i64 undef) ; MVE-NEXT: Cost Model: Found costs of RThru:508 CodeSize:74 Lat:108 SizeLat:108 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:1016 CodeSize:144 Lat:212 SizeLat:212 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.smul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:2032 CodeSize:284 Lat:420 SizeLat:420 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.smul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-NEXT: Cost Model: Found costs of 8 for: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) +; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 undef, i32 undef) ; MVE-NEXT: Cost Model: Found costs of RThru:284 CodeSize:150 Lat:152 SizeLat:152 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.smul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:872 CodeSize:328 Lat:332 SizeLat:332 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.smul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:2832 CodeSize:652 Lat:660 SizeLat:660 for: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.smul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-NEXT: Cost Model: Found costs of 6 for: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) +; MVE-NEXT: Cost Model: Found costs of 2 for: %I16 = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 undef, i16 undef) ; MVE-NEXT: Cost Model: Found costs of RThru:64 CodeSize:40 Lat:46 SizeLat:46 for: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.smul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:232 CodeSize:142 Lat:154 SizeLat:154 for: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.smul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:624 CodeSize:282 Lat:306 SizeLat:306 for: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.smul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-NEXT: Cost Model: Found costs of 6 for: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) +; MVE-NEXT: Cost Model: Found costs of 2 for: %I8 = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 undef, i8 undef) ; MVE-NEXT: Cost Model: Found costs of RThru:96 CodeSize:72 Lat:78 SizeLat:78 for: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.smul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:360 CodeSize:270 Lat:282 SizeLat:282 for: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.smul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:880 CodeSize:538 Lat:562 SizeLat:562 for: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.smul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) @@ -532,57 +532,57 @@ declare {<64 x i8>, <64 x i1>} @llvm.umul.with.overflow.v64i8(<64 x i8>, <64 x define i32 @umul(i32 %arg) { ; V8M-LABEL: 'umul' -; V8M-NEXT: Cost Model: Found costs of 13 for: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) -; V8M-NEXT: Cost Model: Found costs of RThru:78 CodeSize:26 Lat:26 SizeLat:26 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:156 CodeSize:48 Lat:48 SizeLat:48 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:312 CodeSize:92 Lat:92 SizeLat:92 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; V8M-NEXT: Cost Model: Found costs of 7 for: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) -; V8M-NEXT: Cost Model: Found costs of RThru:64 CodeSize:26 Lat:26 SizeLat:26 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:128 CodeSize:50 Lat:50 SizeLat:50 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:256 CodeSize:98 Lat:98 SizeLat:98 for: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; V8M-NEXT: Cost Model: Found costs of 5 for: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) -; V8M-NEXT: Cost Model: Found costs of RThru:48 CodeSize:34 Lat:34 SizeLat:34 for: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:96 CodeSize:66 Lat:66 SizeLat:66 for: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:192 CodeSize:130 Lat:130 SizeLat:130 for: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; V8M-NEXT: Cost Model: Found costs of 5 for: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) -; V8M-NEXT: Cost Model: Found costs of RThru:96 CodeSize:66 Lat:66 SizeLat:66 for: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:192 CodeSize:130 Lat:130 SizeLat:130 for: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) -; V8M-NEXT: Cost Model: Found costs of RThru:384 CodeSize:258 Lat:258 SizeLat:258 for: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) +; V8M-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) +; V8M-NEXT: Cost Model: Found costs of 8 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) +; V8M-NEXT: Cost Model: Found costs of 16 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) +; V8M-NEXT: Cost Model: Found costs of 32 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) +; V8M-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) +; V8M-NEXT: Cost Model: Found costs of 8 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) +; V8M-NEXT: Cost Model: Found costs of 16 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) +; V8M-NEXT: Cost Model: Found costs of 32 for: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) +; V8M-NEXT: Cost Model: Found costs of 2 for: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) +; V8M-NEXT: Cost Model: Found costs of 16 for: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) +; V8M-NEXT: Cost Model: Found costs of 32 for: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) +; V8M-NEXT: Cost Model: Found costs of 64 for: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) +; V8M-NEXT: Cost Model: Found costs of 2 for: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) +; V8M-NEXT: Cost Model: Found costs of 32 for: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) +; V8M-NEXT: Cost Model: Found costs of 64 for: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) +; V8M-NEXT: Cost Model: Found costs of 128 for: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; V8M-NEXT: Cost Model: Found costs of 1 for: ret i32 undef ; ; NEON-LABEL: 'umul' -; NEON-NEXT: Cost Model: Found costs of RThru:13 CodeSize:7 Lat:7 SizeLat:7 for: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) +; NEON-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) ; NEON-NEXT: Cost Model: Found costs of RThru:77 CodeSize:7 Lat:7 SizeLat:7 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:154 CodeSize:8 Lat:8 SizeLat:8 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:308 CodeSize:10 Lat:10 SizeLat:10 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; NEON-NEXT: Cost Model: Found costs of RThru:7 CodeSize:5 Lat:5 SizeLat:5 for: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) +; NEON-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) ; NEON-NEXT: Cost Model: Found costs of RThru:19 CodeSize:9 Lat:9 SizeLat:9 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:34 CodeSize:10 Lat:10 SizeLat:10 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:64 CodeSize:12 Lat:12 SizeLat:12 for: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; NEON-NEXT: Cost Model: Found costs of 5 for: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) +; NEON-NEXT: Cost Model: Found costs of 2 for: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) ; NEON-NEXT: Cost Model: Found costs of RThru:21 CodeSize:7 Lat:7 SizeLat:7 for: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:42 CodeSize:8 Lat:8 SizeLat:8 for: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:84 CodeSize:10 Lat:10 SizeLat:10 for: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; NEON-NEXT: Cost Model: Found costs of 5 for: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) +; NEON-NEXT: Cost Model: Found costs of 2 for: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) ; NEON-NEXT: Cost Model: Found costs of RThru:21 CodeSize:7 Lat:7 SizeLat:7 for: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:42 CodeSize:8 Lat:8 SizeLat:8 for: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:84 CodeSize:10 Lat:10 SizeLat:10 for: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) ; NEON-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret i32 undef ; ; MVE-LABEL: 'umul' -; MVE-NEXT: Cost Model: Found costs of 13 for: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) +; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 undef, i64 undef) ; MVE-NEXT: Cost Model: Found costs of RThru:472 CodeSize:38 Lat:72 SizeLat:72 for: %V2I64 = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> undef, <2 x i64> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:944 CodeSize:72 Lat:140 SizeLat:140 for: %V4I64 = call { <4 x i64>, <4 x i1> } @llvm.umul.with.overflow.v4i64(<4 x i64> undef, <4 x i64> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:1888 CodeSize:140 Lat:276 SizeLat:276 for: %V8I64 = call { <8 x i64>, <8 x i1> } @llvm.umul.with.overflow.v8i64(<8 x i64> undef, <8 x i64> undef) -; MVE-NEXT: Cost Model: Found costs of 7 for: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) +; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 undef, i32 undef) ; MVE-NEXT: Cost Model: Found costs of RThru:186 CodeSize:149 Lat:150 SizeLat:150 for: %V4I32 = call { <4 x i32>, <4 x i1> } @llvm.umul.with.overflow.v4i32(<4 x i32> undef, <4 x i32> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:484 CodeSize:326 Lat:328 SizeLat:328 for: %V8I32 = call { <8 x i32>, <8 x i1> } @llvm.umul.with.overflow.v8i32(<8 x i32> undef, <8 x i32> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:1288 CodeSize:648 Lat:652 SizeLat:652 for: %V16I32 = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> undef, <16 x i32> undef) -; MVE-NEXT: Cost Model: Found costs of 5 for: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) +; MVE-NEXT: Cost Model: Found costs of 2 for: %I16 = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 undef, i16 undef) ; MVE-NEXT: Cost Model: Found costs of RThru:62 CodeSize:39 Lat:44 SizeLat:44 for: %V8I16 = call { <8 x i16>, <8 x i1> } @llvm.umul.with.overflow.v8i16(<8 x i16> undef, <8 x i16> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:228 CodeSize:140 Lat:150 SizeLat:150 for: %V16I16 = call { <16 x i16>, <16 x i1> } @llvm.umul.with.overflow.v16i16(<16 x i16> undef, <16 x i16> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:616 CodeSize:278 Lat:298 SizeLat:298 for: %V32I16 = call { <32 x i16>, <32 x i1> } @llvm.umul.with.overflow.v32i16(<32 x i16> undef, <32 x i16> undef) -; MVE-NEXT: Cost Model: Found costs of 5 for: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) +; MVE-NEXT: Cost Model: Found costs of 2 for: %I8 = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 undef, i8 undef) ; MVE-NEXT: Cost Model: Found costs of RThru:94 CodeSize:71 Lat:76 SizeLat:76 for: %V16I8 = call { <16 x i8>, <16 x i1> } @llvm.umul.with.overflow.v16i8(<16 x i8> undef, <16 x i8> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:356 CodeSize:268 Lat:278 SizeLat:278 for: %V32I8 = call { <32 x i8>, <32 x i1> } @llvm.umul.with.overflow.v32i8(<32 x i8> undef, <32 x i8> undef) ; MVE-NEXT: Cost Model: Found costs of RThru:872 CodeSize:534 Lat:554 SizeLat:554 for: %V64I8 = call { <64 x i8>, <64 x i1> } @llvm.umul.with.overflow.v64i8(<64 x i8> undef, <64 x i8> undef) diff --git a/llvm/test/Analysis/CostModel/RISCV/abs.ll b/llvm/test/Analysis/CostModel/RISCV/abs.ll index b1f93f3811580..80dd006c6ee77 100644 --- a/llvm/test/Analysis/CostModel/RISCV/abs.ll +++ b/llvm/test/Analysis/CostModel/RISCV/abs.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt < %s -passes="print" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v | FileCheck %s +; RUN: opt < %s -passes="print" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefix=ZVABD ; Check that we don't crash querying costs when vectors are not enabled. ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 @@ -38,6 +39,41 @@ define i32 @abs(i32 %arg) { ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %31 = call @llvm.abs.nxv32i8( undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %32 = call @llvm.abs.nxv64i8( undef, i1 false) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; ZVABD-LABEL: 'abs' +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %3 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = call @llvm.abs.nxv2i64( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %5 = call @llvm.abs.nxv4i64( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = call @llvm.abs.nxv8i64( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call <2 x i32> @llvm.abs.v2i32(<2 x i32> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %9 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %10 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %11 = call @llvm.abs.nxv2i32( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %12 = call @llvm.abs.nxv4i32( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %13 = call @llvm.abs.nxv8i32( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %14 = call @llvm.abs.nxv16i32( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %15 = call <2 x i16> @llvm.abs.v2i16(<2 x i16> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %16 = call <4 x i16> @llvm.abs.v4i16(<4 x i16> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %17 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %18 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %19 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %20 = call @llvm.abs.nxv2i16( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %21 = call @llvm.abs.nxv4i16( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %22 = call @llvm.abs.nxv8i16( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %23 = call @llvm.abs.nxv16i16( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %24 = call @llvm.abs.nxv32i16( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %25 = call <8 x i8> @llvm.abs.v8i8(<8 x i8> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %26 = call <16 x i8> @llvm.abs.v16i8(<16 x i8> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %27 = call <32 x i8> @llvm.abs.v32i8(<32 x i8> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %28 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %29 = call @llvm.abs.nxv8i8( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %30 = call @llvm.abs.nxv16i8( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %31 = call @llvm.abs.nxv32i8( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %32 = call @llvm.abs.nxv64i8( undef, i1 false) +; ZVABD-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; call <2 x i64> @llvm.abs.v2i64(<2 x i64> undef, i1 false) call <4 x i64> @llvm.abs.v4i64(<4 x i64> undef, i1 false) diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll index 56b8aa343310b..5830a358a0c1a 100644 --- a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll +++ b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll @@ -148,39 +148,22 @@ define void @vector_reverse() { } define void @vector_splice() { -; ARGBASED-LABEL: 'vector_splice' -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = call @llvm.vector.splice.left.nxv16i8( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %2 = call @llvm.vector.splice.left.nxv32i8( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = call @llvm.vector.splice.left.nxv2i16( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = call @llvm.vector.splice.left.nxv4i16( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %5 = call @llvm.vector.splice.left.nxv8i16( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = call @llvm.vector.splice.left.nxv16i16( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %7 = call @llvm.vector.splice.left.nxv4i32( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %8 = call @llvm.vector.splice.left.nxv8i32( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %9 = call @llvm.vector.splice.left.nxv2i64( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %10 = call @llvm.vector.splice.left.nxv4i64( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call @llvm.vector.splice.left.nxv16i1( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %12 = call @llvm.vector.splice.left.nxv8i1( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %13 = call @llvm.vector.splice.left.nxv4i1( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %14 = call @llvm.vector.splice.left.nxv2i1( zeroinitializer, zeroinitializer, i32 1) -; ARGBASED-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void -; -; TYPEBASED-LABEL: 'vector_splice' -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %1 = call @llvm.vector.splice.left.nxv16i8( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %2 = call @llvm.vector.splice.left.nxv32i8( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %3 = call @llvm.vector.splice.left.nxv2i16( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %4 = call @llvm.vector.splice.left.nxv4i16( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %5 = call @llvm.vector.splice.left.nxv8i16( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.vector.splice.left.nxv16i16( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.vector.splice.left.nxv4i32( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.vector.splice.left.nxv8i32( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.vector.splice.left.nxv2i64( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.vector.splice.left.nxv4i64( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %11 = call @llvm.vector.splice.left.nxv16i1( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %12 = call @llvm.vector.splice.left.nxv8i1( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %13 = call @llvm.vector.splice.left.nxv4i1( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Invalid cost for instruction: %14 = call @llvm.vector.splice.left.nxv2i1( zeroinitializer, zeroinitializer, i32 1) -; TYPEBASED-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; CHECK-LABEL: 'vector_splice' +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = call @llvm.vector.splice.left.nxv16i8( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %2 = call @llvm.vector.splice.left.nxv32i8( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = call @llvm.vector.splice.left.nxv2i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = call @llvm.vector.splice.left.nxv4i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %5 = call @llvm.vector.splice.left.nxv8i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %6 = call @llvm.vector.splice.left.nxv16i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %7 = call @llvm.vector.splice.left.nxv4i32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %8 = call @llvm.vector.splice.left.nxv8i32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %9 = call @llvm.vector.splice.left.nxv2i64( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %10 = call @llvm.vector.splice.left.nxv4i64( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call @llvm.vector.splice.left.nxv16i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %12 = call @llvm.vector.splice.left.nxv8i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %13 = call @llvm.vector.splice.left.nxv4i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %14 = call @llvm.vector.splice.left.nxv2i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'vector_splice' ; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = call @llvm.vector.splice.left.nxv16i8( zeroinitializer, zeroinitializer, i32 1) diff --git a/llvm/test/Analysis/CostModel/RISCV/splice.ll b/llvm/test/Analysis/CostModel/RISCV/splice.ll index 5250c3dc1171a..0dad42c945809 100644 --- a/llvm/test/Analysis/CostModel/RISCV/splice.ll +++ b/llvm/test/Analysis/CostModel/RISCV/splice.ll @@ -4,7 +4,7 @@ ; RUN: opt < %s -passes="print" -cost-kind=code-size 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh | FileCheck %s --check-prefix=SIZE ; RUN: opt < %s -passes="print" -cost-kind=code-size 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfhmin | FileCheck %s --check-prefix=SIZE -define void @vector_splice(i32 zeroext %offset) { +define void @vector_splice() { ; CHECK-LABEL: 'vector_splice' ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = call @llvm.vector.splice.right.nxv1i8( zeroinitializer, zeroinitializer, i32 1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %2 = call @llvm.vector.splice.right.nxv2i8( zeroinitializer, zeroinitializer, i32 1) @@ -62,8 +62,6 @@ define void @vector_splice(i32 zeroext %offset) { ; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %54 = call @llvm.vector.splice.right.nxv16f64( zeroinitializer, zeroinitializer, i32 1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %55 = call @llvm.vector.splice.right.nxv32f64( zeroinitializer, zeroinitializer, i32 1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %56 = call @llvm.vector.splice.right.nxv64f64( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %left.variable = call @llvm.vector.splice.left.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %right.variable = call @llvm.vector.splice.right.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'vector_splice' @@ -123,8 +121,6 @@ define void @vector_splice(i32 zeroext %offset) { ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %54 = call @llvm.vector.splice.right.nxv16f64( zeroinitializer, zeroinitializer, i32 1) ; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %55 = call @llvm.vector.splice.right.nxv32f64( zeroinitializer, zeroinitializer, i32 1) ; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %56 = call @llvm.vector.splice.right.nxv64f64( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Invalid cost for instruction: %left.variable = call @llvm.vector.splice.left.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) -; SIZE-NEXT: Cost Model: Invalid cost for instruction: %right.variable = call @llvm.vector.splice.right.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %splice.nxv1i8 = call @llvm.vector.splice.nxv1i8( zeroinitializer, zeroinitializer, i32 -1) @@ -191,8 +187,377 @@ define void @vector_splice(i32 zeroext %offset) { %splice.nxv32f64 = call @llvm.vector.splice.nxv32f64( zeroinitializer, zeroinitializer, i32 -1) %splice.nxv64f64 = call @llvm.vector.splice.nxv64f64( zeroinitializer, zeroinitializer, i32 -1) - %left.variable = call @llvm.vector.splice.left( zeroinitializer, zeroinitializer, i32 %offset) - %right.variable = call @llvm.vector.splice.right( zeroinitializer, zeroinitializer, i32 %offset) + ret void +} + +define void @vector_splice_left_variable(i32 zeroext %offset) { +; CHECK-LABEL: 'vector_splice_left_variable' +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i8 = call @llvm.vector.splice.left.nxv1i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i8 = call @llvm.vector.splice.left.nxv2i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i8 = call @llvm.vector.splice.left.nxv4i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i8 = call @llvm.vector.splice.left.nxv8i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16i8 = call @llvm.vector.splice.left.nxv16i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32i8 = call @llvm.vector.splice.left.nxv32i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64i8 = call @llvm.vector.splice.left.nxv64i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i16 = call @llvm.vector.splice.left.nxv1i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i16 = call @llvm.vector.splice.left.nxv2i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i16 = call @llvm.vector.splice.left.nxv4i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8i16 = call @llvm.vector.splice.left.nxv8i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16i16 = call @llvm.vector.splice.left.nxv16i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32i16 = call @llvm.vector.splice.left.nxv32i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64i16 = call @llvm.vector.splice.left.nxv64i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i32 = call @llvm.vector.splice.left.nxv1i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i32 = call @llvm.vector.splice.left.nxv2i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv4i32 = call @llvm.vector.splice.left.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv8i32 = call @llvm.vector.splice.left.nxv8i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv16i32 = call @llvm.vector.splice.left.nxv16i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv32i32 = call @llvm.vector.splice.left.nxv32i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv64i32 = call @llvm.vector.splice.left.nxv64i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i64 = call @llvm.vector.splice.left.nxv1i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv2i64 = call @llvm.vector.splice.left.nxv2i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv4i64 = call @llvm.vector.splice.left.nxv4i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv8i64 = call @llvm.vector.splice.left.nxv8i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv16i64 = call @llvm.vector.splice.left.nxv16i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv32i64 = call @llvm.vector.splice.left.nxv32i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %splice.nxv64i64 = call @llvm.vector.splice.left.nxv64i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1bf16 = call @llvm.vector.splice.left.nxv1bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2bf16 = call @llvm.vector.splice.left.nxv2bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4bf16 = call @llvm.vector.splice.left.nxv4bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8bf16 = call @llvm.vector.splice.left.nxv8bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16bf16 = call @llvm.vector.splice.left.nxv16bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32bf16 = call @llvm.vector.splice.left.nxv32bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64bf16 = call @llvm.vector.splice.left.nxv64bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f16 = call @llvm.vector.splice.left.nxv1f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f16 = call @llvm.vector.splice.left.nxv2f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f16 = call @llvm.vector.splice.left.nxv4f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8f16 = call @llvm.vector.splice.left.nxv8f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16f16 = call @llvm.vector.splice.left.nxv16f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32f16 = call @llvm.vector.splice.left.nxv32f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64f16 = call @llvm.vector.splice.left.nxv64f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f32 = call @llvm.vector.splice.left.nxv1f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f32 = call @llvm.vector.splice.left.nxv2f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv4f32 = call @llvm.vector.splice.left.nxv4f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv8f32 = call @llvm.vector.splice.left.nxv8f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv16f32 = call @llvm.vector.splice.left.nxv16f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv32f32 = call @llvm.vector.splice.left.nxv32f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv64f32 = call @llvm.vector.splice.left.nxv64f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f64 = call @llvm.vector.splice.left.nxv1f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv2f64 = call @llvm.vector.splice.left.nxv2f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv4f64 = call @llvm.vector.splice.left.nxv4f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv8f64 = call @llvm.vector.splice.left.nxv8f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv16f64 = call @llvm.vector.splice.left.nxv16f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv32f64 = call @llvm.vector.splice.left.nxv32f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %splice.nxv64f64 = call @llvm.vector.splice.left.nxv64f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; SIZE-LABEL: 'vector_splice_left_variable' +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i8 = call @llvm.vector.splice.left.nxv1i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i8 = call @llvm.vector.splice.left.nxv2i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i8 = call @llvm.vector.splice.left.nxv4i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i8 = call @llvm.vector.splice.left.nxv8i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i8 = call @llvm.vector.splice.left.nxv16i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32i8 = call @llvm.vector.splice.left.nxv32i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv64i8 = call @llvm.vector.splice.left.nxv64i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i16 = call @llvm.vector.splice.left.nxv1i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i16 = call @llvm.vector.splice.left.nxv2i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i16 = call @llvm.vector.splice.left.nxv4i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i16 = call @llvm.vector.splice.left.nxv8i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i16 = call @llvm.vector.splice.left.nxv16i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32i16 = call @llvm.vector.splice.left.nxv32i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv64i16 = call @llvm.vector.splice.left.nxv64i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i32 = call @llvm.vector.splice.left.nxv1i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i32 = call @llvm.vector.splice.left.nxv2i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i32 = call @llvm.vector.splice.left.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i32 = call @llvm.vector.splice.left.nxv8i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i32 = call @llvm.vector.splice.left.nxv16i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv32i32 = call @llvm.vector.splice.left.nxv32i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv64i32 = call @llvm.vector.splice.left.nxv64i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i64 = call @llvm.vector.splice.left.nxv1i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i64 = call @llvm.vector.splice.left.nxv2i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i64 = call @llvm.vector.splice.left.nxv4i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i64 = call @llvm.vector.splice.left.nxv8i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16i64 = call @llvm.vector.splice.left.nxv16i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32i64 = call @llvm.vector.splice.left.nxv32i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64i64 = call @llvm.vector.splice.left.nxv64i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv1bf16 = call @llvm.vector.splice.left.nxv1bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv2bf16 = call @llvm.vector.splice.left.nxv2bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv4bf16 = call @llvm.vector.splice.left.nxv4bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv8bf16 = call @llvm.vector.splice.left.nxv8bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv16bf16 = call @llvm.vector.splice.left.nxv16bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv32bf16 = call @llvm.vector.splice.left.nxv32bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv64bf16 = call @llvm.vector.splice.left.nxv64bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f16 = call @llvm.vector.splice.left.nxv1f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f16 = call @llvm.vector.splice.left.nxv2f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f16 = call @llvm.vector.splice.left.nxv4f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f16 = call @llvm.vector.splice.left.nxv8f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16f16 = call @llvm.vector.splice.left.nxv16f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32f16 = call @llvm.vector.splice.left.nxv32f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv64f16 = call @llvm.vector.splice.left.nxv64f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f32 = call @llvm.vector.splice.left.nxv1f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f32 = call @llvm.vector.splice.left.nxv2f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f32 = call @llvm.vector.splice.left.nxv4f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f32 = call @llvm.vector.splice.left.nxv8f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16f32 = call @llvm.vector.splice.left.nxv16f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv32f32 = call @llvm.vector.splice.left.nxv32f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv64f32 = call @llvm.vector.splice.left.nxv64f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f64 = call @llvm.vector.splice.left.nxv1f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f64 = call @llvm.vector.splice.left.nxv2f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f64 = call @llvm.vector.splice.left.nxv4f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f64 = call @llvm.vector.splice.left.nxv8f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16f64 = call @llvm.vector.splice.left.nxv16f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32f64 = call @llvm.vector.splice.left.nxv32f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64f64 = call @llvm.vector.splice.left.nxv64f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; + %splice.nxv1i8 = call @llvm.vector.splice.left.nxv1i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2i8 = call @llvm.vector.splice.left.nxv2i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4i8 = call @llvm.vector.splice.left.nxv4i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8i8 = call @llvm.vector.splice.left.nxv8i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16i8 = call @llvm.vector.splice.left.nxv16i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32i8 = call @llvm.vector.splice.left.nxv32i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64i8 = call @llvm.vector.splice.left.nxv64i8( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1i16 = call @llvm.vector.splice.left.nxv1i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2i16 = call @llvm.vector.splice.left.nxv2i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4i16 = call @llvm.vector.splice.left.nxv4i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8i16 = call @llvm.vector.splice.left.nxv8i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16i16 = call @llvm.vector.splice.left.nxv16i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32i16 = call @llvm.vector.splice.left.nxv32i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64i16 = call @llvm.vector.splice.left.nxv64i16( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1i32 = call @llvm.vector.splice.left.nxv1i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2i32 = call @llvm.vector.splice.left.nxv2i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4i32 = call @llvm.vector.splice.left.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8i32 = call @llvm.vector.splice.left.nxv8i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16i32 = call @llvm.vector.splice.left.nxv16i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32i32 = call @llvm.vector.splice.left.nxv32i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64i32 = call @llvm.vector.splice.left.nxv64i32( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1i64 = call @llvm.vector.splice.left.nxv1i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2i64 = call @llvm.vector.splice.left.nxv2i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4i64 = call @llvm.vector.splice.left.nxv4i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8i64 = call @llvm.vector.splice.left.nxv8i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16i64 = call @llvm.vector.splice.left.nxv16i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32i64 = call @llvm.vector.splice.left.nxv32i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64i64 = call @llvm.vector.splice.left.nxv64i64( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1bf16 = call @llvm.vector.splice.left.nxv1bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2bf16 = call @llvm.vector.splice.left.nxv2bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4bf16 = call @llvm.vector.splice.left.nxv4bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8bf16 = call @llvm.vector.splice.left.nxv8bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16bf16 = call @llvm.vector.splice.left.nxv16bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32bf16 = call @llvm.vector.splice.left.nxv32bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64bf16 = call @llvm.vector.splice.left.nxv64bf16( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1f16 = call @llvm.vector.splice.left.nxv1f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2f16 = call @llvm.vector.splice.left.nxv2f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4f16 = call @llvm.vector.splice.left.nxv4f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8f16 = call @llvm.vector.splice.left.nxv8f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16f16 = call @llvm.vector.splice.left.nxv16f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32f16 = call @llvm.vector.splice.left.nxv32f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64f16 = call @llvm.vector.splice.left.nxv64f16( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1f32 = call @llvm.vector.splice.left.nxv1f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2f32 = call @llvm.vector.splice.left.nxv2f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4f32 = call @llvm.vector.splice.left.nxv4f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8f32 = call @llvm.vector.splice.left.nxv8f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16f32 = call @llvm.vector.splice.left.nxv16f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32f32 = call @llvm.vector.splice.left.nxv32f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64f32 = call @llvm.vector.splice.left.nxv64f32( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1f64 = call @llvm.vector.splice.left.nxv1f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2f64 = call @llvm.vector.splice.left.nxv2f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4f64 = call @llvm.vector.splice.left.nxv4f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8f64 = call @llvm.vector.splice.left.nxv8f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16f64 = call @llvm.vector.splice.left.nxv16f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32f64 = call @llvm.vector.splice.left.nxv32f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64f64 = call @llvm.vector.splice.left.nxv64f64( zeroinitializer, zeroinitializer, i32 %offset) + + ret void +} + +define void @vector_splice_right_variable(i32 zeroext %offset) { +; CHECK-LABEL: 'vector_splice_right_variable' +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i8 = call @llvm.vector.splice.right.nxv1i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i8 = call @llvm.vector.splice.right.nxv2i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i8 = call @llvm.vector.splice.right.nxv4i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i8 = call @llvm.vector.splice.right.nxv8i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16i8 = call @llvm.vector.splice.right.nxv16i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32i8 = call @llvm.vector.splice.right.nxv32i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64i8 = call @llvm.vector.splice.right.nxv64i8( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i16 = call @llvm.vector.splice.right.nxv1i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i16 = call @llvm.vector.splice.right.nxv2i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i16 = call @llvm.vector.splice.right.nxv4i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8i16 = call @llvm.vector.splice.right.nxv8i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16i16 = call @llvm.vector.splice.right.nxv16i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32i16 = call @llvm.vector.splice.right.nxv32i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64i16 = call @llvm.vector.splice.right.nxv64i16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i32 = call @llvm.vector.splice.right.nxv1i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i32 = call @llvm.vector.splice.right.nxv2i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv4i32 = call @llvm.vector.splice.right.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv8i32 = call @llvm.vector.splice.right.nxv8i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv16i32 = call @llvm.vector.splice.right.nxv16i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv32i32 = call @llvm.vector.splice.right.nxv32i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv64i32 = call @llvm.vector.splice.right.nxv64i32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i64 = call @llvm.vector.splice.right.nxv1i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv2i64 = call @llvm.vector.splice.right.nxv2i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv4i64 = call @llvm.vector.splice.right.nxv4i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv8i64 = call @llvm.vector.splice.right.nxv8i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv16i64 = call @llvm.vector.splice.right.nxv16i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv32i64 = call @llvm.vector.splice.right.nxv32i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %splice.nxv64i64 = call @llvm.vector.splice.right.nxv64i64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1bf16 = call @llvm.vector.splice.right.nxv1bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2bf16 = call @llvm.vector.splice.right.nxv2bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4bf16 = call @llvm.vector.splice.right.nxv4bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8bf16 = call @llvm.vector.splice.right.nxv8bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16bf16 = call @llvm.vector.splice.right.nxv16bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32bf16 = call @llvm.vector.splice.right.nxv32bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64bf16 = call @llvm.vector.splice.right.nxv64bf16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f16 = call @llvm.vector.splice.right.nxv1f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f16 = call @llvm.vector.splice.right.nxv2f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f16 = call @llvm.vector.splice.right.nxv4f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8f16 = call @llvm.vector.splice.right.nxv8f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16f16 = call @llvm.vector.splice.right.nxv16f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32f16 = call @llvm.vector.splice.right.nxv32f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64f16 = call @llvm.vector.splice.right.nxv64f16( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f32 = call @llvm.vector.splice.right.nxv1f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f32 = call @llvm.vector.splice.right.nxv2f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv4f32 = call @llvm.vector.splice.right.nxv4f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv8f32 = call @llvm.vector.splice.right.nxv8f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv16f32 = call @llvm.vector.splice.right.nxv16f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv32f32 = call @llvm.vector.splice.right.nxv32f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv64f32 = call @llvm.vector.splice.right.nxv64f32( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f64 = call @llvm.vector.splice.right.nxv1f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv2f64 = call @llvm.vector.splice.right.nxv2f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv4f64 = call @llvm.vector.splice.right.nxv4f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv8f64 = call @llvm.vector.splice.right.nxv8f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv16f64 = call @llvm.vector.splice.right.nxv16f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv32f64 = call @llvm.vector.splice.right.nxv32f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %splice.nxv64f64 = call @llvm.vector.splice.right.nxv64f64( zeroinitializer, zeroinitializer, i32 %offset) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; SIZE-LABEL: 'vector_splice_right_variable' +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i8 = call @llvm.vector.splice.right.nxv1i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i8 = call @llvm.vector.splice.right.nxv2i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i8 = call @llvm.vector.splice.right.nxv4i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i8 = call @llvm.vector.splice.right.nxv8i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i8 = call @llvm.vector.splice.right.nxv16i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32i8 = call @llvm.vector.splice.right.nxv32i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv64i8 = call @llvm.vector.splice.right.nxv64i8( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i16 = call @llvm.vector.splice.right.nxv1i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i16 = call @llvm.vector.splice.right.nxv2i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i16 = call @llvm.vector.splice.right.nxv4i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i16 = call @llvm.vector.splice.right.nxv8i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i16 = call @llvm.vector.splice.right.nxv16i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32i16 = call @llvm.vector.splice.right.nxv32i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv64i16 = call @llvm.vector.splice.right.nxv64i16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i32 = call @llvm.vector.splice.right.nxv1i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i32 = call @llvm.vector.splice.right.nxv2i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i32 = call @llvm.vector.splice.right.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i32 = call @llvm.vector.splice.right.nxv8i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i32 = call @llvm.vector.splice.right.nxv16i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv32i32 = call @llvm.vector.splice.right.nxv32i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv64i32 = call @llvm.vector.splice.right.nxv64i32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i64 = call @llvm.vector.splice.right.nxv1i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i64 = call @llvm.vector.splice.right.nxv2i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i64 = call @llvm.vector.splice.right.nxv4i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i64 = call @llvm.vector.splice.right.nxv8i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16i64 = call @llvm.vector.splice.right.nxv16i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32i64 = call @llvm.vector.splice.right.nxv32i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64i64 = call @llvm.vector.splice.right.nxv64i64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv1bf16 = call @llvm.vector.splice.right.nxv1bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv2bf16 = call @llvm.vector.splice.right.nxv2bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv4bf16 = call @llvm.vector.splice.right.nxv4bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv8bf16 = call @llvm.vector.splice.right.nxv8bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv16bf16 = call @llvm.vector.splice.right.nxv16bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv32bf16 = call @llvm.vector.splice.right.nxv32bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %splice.nxv64bf16 = call @llvm.vector.splice.right.nxv64bf16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f16 = call @llvm.vector.splice.right.nxv1f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f16 = call @llvm.vector.splice.right.nxv2f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f16 = call @llvm.vector.splice.right.nxv4f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f16 = call @llvm.vector.splice.right.nxv8f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16f16 = call @llvm.vector.splice.right.nxv16f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32f16 = call @llvm.vector.splice.right.nxv32f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv64f16 = call @llvm.vector.splice.right.nxv64f16( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f32 = call @llvm.vector.splice.right.nxv1f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f32 = call @llvm.vector.splice.right.nxv2f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f32 = call @llvm.vector.splice.right.nxv4f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f32 = call @llvm.vector.splice.right.nxv8f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16f32 = call @llvm.vector.splice.right.nxv16f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv32f32 = call @llvm.vector.splice.right.nxv32f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv64f32 = call @llvm.vector.splice.right.nxv64f32( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f64 = call @llvm.vector.splice.right.nxv1f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f64 = call @llvm.vector.splice.right.nxv2f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f64 = call @llvm.vector.splice.right.nxv4f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f64 = call @llvm.vector.splice.right.nxv8f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16f64 = call @llvm.vector.splice.right.nxv16f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32f64 = call @llvm.vector.splice.right.nxv32f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64f64 = call @llvm.vector.splice.right.nxv64f64( zeroinitializer, zeroinitializer, i32 %offset) +; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; + %splice.nxv1i8 = call @llvm.vector.splice.right.nxv1i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2i8 = call @llvm.vector.splice.right.nxv2i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4i8 = call @llvm.vector.splice.right.nxv4i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8i8 = call @llvm.vector.splice.right.nxv8i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16i8 = call @llvm.vector.splice.right.nxv16i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32i8 = call @llvm.vector.splice.right.nxv32i8( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64i8 = call @llvm.vector.splice.right.nxv64i8( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1i16 = call @llvm.vector.splice.right.nxv1i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2i16 = call @llvm.vector.splice.right.nxv2i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4i16 = call @llvm.vector.splice.right.nxv4i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8i16 = call @llvm.vector.splice.right.nxv8i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16i16 = call @llvm.vector.splice.right.nxv16i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32i16 = call @llvm.vector.splice.right.nxv32i16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64i16 = call @llvm.vector.splice.right.nxv64i16( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1i32 = call @llvm.vector.splice.right.nxv1i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2i32 = call @llvm.vector.splice.right.nxv2i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4i32 = call @llvm.vector.splice.right.nxv4i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8i32 = call @llvm.vector.splice.right.nxv8i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16i32 = call @llvm.vector.splice.right.nxv16i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32i32 = call @llvm.vector.splice.right.nxv32i32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64i32 = call @llvm.vector.splice.right.nxv64i32( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1i64 = call @llvm.vector.splice.right.nxv1i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2i64 = call @llvm.vector.splice.right.nxv2i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4i64 = call @llvm.vector.splice.right.nxv4i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8i64 = call @llvm.vector.splice.right.nxv8i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16i64 = call @llvm.vector.splice.right.nxv16i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32i64 = call @llvm.vector.splice.right.nxv32i64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64i64 = call @llvm.vector.splice.right.nxv64i64( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1bf16 = call @llvm.vector.splice.right.nxv1bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2bf16 = call @llvm.vector.splice.right.nxv2bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4bf16 = call @llvm.vector.splice.right.nxv4bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8bf16 = call @llvm.vector.splice.right.nxv8bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16bf16 = call @llvm.vector.splice.right.nxv16bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32bf16 = call @llvm.vector.splice.right.nxv32bf16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64bf16 = call @llvm.vector.splice.right.nxv64bf16( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1f16 = call @llvm.vector.splice.right.nxv1f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2f16 = call @llvm.vector.splice.right.nxv2f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4f16 = call @llvm.vector.splice.right.nxv4f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8f16 = call @llvm.vector.splice.right.nxv8f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16f16 = call @llvm.vector.splice.right.nxv16f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32f16 = call @llvm.vector.splice.right.nxv32f16( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64f16 = call @llvm.vector.splice.right.nxv64f16( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1f32 = call @llvm.vector.splice.right.nxv1f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2f32 = call @llvm.vector.splice.right.nxv2f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4f32 = call @llvm.vector.splice.right.nxv4f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8f32 = call @llvm.vector.splice.right.nxv8f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16f32 = call @llvm.vector.splice.right.nxv16f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32f32 = call @llvm.vector.splice.right.nxv32f32( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64f32 = call @llvm.vector.splice.right.nxv64f32( zeroinitializer, zeroinitializer, i32 %offset) + + %splice.nxv1f64 = call @llvm.vector.splice.right.nxv1f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv2f64 = call @llvm.vector.splice.right.nxv2f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv4f64 = call @llvm.vector.splice.right.nxv4f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv8f64 = call @llvm.vector.splice.right.nxv8f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv16f64 = call @llvm.vector.splice.right.nxv16f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv32f64 = call @llvm.vector.splice.right.nxv32f64( zeroinitializer, zeroinitializer, i32 %offset) + %splice.nxv64f64 = call @llvm.vector.splice.right.nxv64f64( zeroinitializer, zeroinitializer, i32 %offset) ret void } diff --git a/llvm/test/Analysis/CostModel/X86/clmul.ll b/llvm/test/Analysis/CostModel/X86/clmul.ll index 53f852093cb4d..1ce85f9c6f897 100644 --- a/llvm/test/Analysis/CostModel/X86/clmul.ll +++ b/llvm/test/Analysis/CostModel/X86/clmul.ll @@ -3,11 +3,12 @@ ; RUN: opt < %s -passes="print" 2>&1 -disable-output -mtriple=x86_64-unknown-linux-gnu -mattr=-pclmul | FileCheck %s --check-prefix=NO-PCLMUL -define void @clmul(i128 %a128, i128 %b128, i64 %a64, i64 %b64, i32 %a32, i32 %b32, i8 %a8, i8 %b8) { +define void @clmul(i128 %a128, i128 %b128, i64 %a64, i64 %b64, i32 %a32, i32 %b32, i16 %a16, i16 %b16, i8 %a8, i8 %b8) { ; PCLMUL-LABEL: 'clmul' ; PCLMUL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %call_i128 = call i128 @llvm.clmul.i128(i128 %a128, i128 %b128) ; PCLMUL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %call_i64 = call i64 @llvm.clmul.i64(i64 %a64, i64 %b64) ; PCLMUL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %call_i32 = call i32 @llvm.clmul.i32(i32 %a32, i32 %b32) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %call_i16 = call i16 @llvm.clmul.i16(i16 %a16, i16 %b16) ; PCLMUL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %call_i8 = call i8 @llvm.clmul.i8(i8 %a8, i8 %b8) ; PCLMUL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; @@ -15,12 +16,89 @@ define void @clmul(i128 %a128, i128 %b128, i64 %a64, i64 %b64, i32 %a32, i32 %b3 ; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %call_i128 = call i128 @llvm.clmul.i128(i128 %a128, i128 %b128) ; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %call_i64 = call i64 @llvm.clmul.i64(i64 %a64, i64 %b64) ; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %call_i32 = call i32 @llvm.clmul.i32(i32 %a32, i32 %b32) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %call_i16 = call i16 @llvm.clmul.i16(i16 %a16, i16 %b16) ; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %call_i8 = call i8 @llvm.clmul.i8(i8 %a8, i8 %b8) ; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %call_i128 = call i128 @llvm.clmul.i128(i128 %a128, i128 %b128) %call_i64 = call i64 @llvm.clmul.i64(i64 %a64, i64 %b64) %call_i32 = call i32 @llvm.clmul.i32(i32 %a32, i32 %b32) + %call_i16 = call i16 @llvm.clmul.i16(i16 %a16, i16 %b16) %call_i8 = call i8 @llvm.clmul.i8(i8 %a8, i8 %b8) ret void } + +define void @clmul_128(<1 x i128> %a128, <1 x i128> %b128, <2 x i64> %a64, <2 x i64> %b64, <4 x i32> %a32, <4 x i32> %b32, <8 x i16> %a16, <8 x i16> %b16, <16 x i8> %a8, <16 x i8> %b8) { +; PCLMUL-LABEL: 'clmul_128' +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %call_i128 = call <1 x i128> @llvm.clmul.v1i128(<1 x i128> %a128, <1 x i128> %b128) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %call_i64 = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> %a64, <2 x i64> %b64) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %call_i32 = call <4 x i32> @llvm.clmul.v4i32(<4 x i32> %a32, <4 x i32> %b32) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %call_i16 = call <8 x i16> @llvm.clmul.v8i16(<8 x i16> %a16, <8 x i16> %b16) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %call_i8 = call <16 x i8> @llvm.clmul.v16i8(<16 x i8> %a8, <16 x i8> %b8) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; NO-PCLMUL-LABEL: 'clmul_128' +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %call_i128 = call <1 x i128> @llvm.clmul.v1i128(<1 x i128> %a128, <1 x i128> %b128) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 576 for instruction: %call_i64 = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> %a64, <2 x i64> %b64) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %call_i32 = call <4 x i32> @llvm.clmul.v4i32(<4 x i32> %a32, <4 x i32> %b32) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %call_i16 = call <8 x i16> @llvm.clmul.v8i16(<8 x i16> %a16, <8 x i16> %b16) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %call_i8 = call <16 x i8> @llvm.clmul.v16i8(<16 x i8> %a8, <16 x i8> %b8) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %call_i128 = call <1 x i128> @llvm.clmul.v1i128(<1 x i128> %a128, <1 x i128> %b128) + %call_i64 = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> %a64, <2 x i64> %b64) + %call_i32 = call <4 x i32> @llvm.clmul.v4i32(<4 x i32> %a32, <4 x i32> %b32) + %call_i16 = call <8 x i16> @llvm.clmul.v8i16(<8 x i16> %a16, <8 x i16> %b16) + %call_i8 = call <16 x i8> @llvm.clmul.v16i8(<16 x i8> %a8, <16 x i8> %b8) + ret void +} + +define void @clmul_256(<2 x i128> %a128, <2 x i128> %b128, <4 x i64> %a64, <4 x i64> %b64, <8 x i32> %a32, <8 x i32> %b32, <16 x i16> %a16, <16 x i16> %b16, <32 x i8> %a8, <32 x i8> %b8) { +; PCLMUL-LABEL: 'clmul_256' +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %call_i128 = call <2 x i128> @llvm.clmul.v2i128(<2 x i128> %a128, <2 x i128> %b128) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %call_i64 = call <4 x i64> @llvm.clmul.v4i64(<4 x i64> %a64, <4 x i64> %b64) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %call_i32 = call <8 x i32> @llvm.clmul.v8i32(<8 x i32> %a32, <8 x i32> %b32) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %call_i16 = call <16 x i16> @llvm.clmul.v16i16(<16 x i16> %a16, <16 x i16> %b16) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %call_i8 = call <32 x i8> @llvm.clmul.v32i8(<32 x i8> %a8, <32 x i8> %b8) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; NO-PCLMUL-LABEL: 'clmul_256' +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 2048 for instruction: %call_i128 = call <2 x i128> @llvm.clmul.v2i128(<2 x i128> %a128, <2 x i128> %b128) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 1152 for instruction: %call_i64 = call <4 x i64> @llvm.clmul.v4i64(<4 x i64> %a64, <4 x i64> %b64) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 512 for instruction: %call_i32 = call <8 x i32> @llvm.clmul.v8i32(<8 x i32> %a32, <8 x i32> %b32) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %call_i16 = call <16 x i16> @llvm.clmul.v16i16(<16 x i16> %a16, <16 x i16> %b16) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %call_i8 = call <32 x i8> @llvm.clmul.v32i8(<32 x i8> %a8, <32 x i8> %b8) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %call_i128 = call <2 x i128> @llvm.clmul.v2i128(<2 x i128> %a128, <2 x i128> %b128) + %call_i64 = call <4 x i64> @llvm.clmul.v4i64(<4 x i64> %a64, <4 x i64> %b64) + %call_i32 = call <8 x i32> @llvm.clmul.v8i32(<8 x i32> %a32, <8 x i32> %b32) + %call_i16 = call <16 x i16> @llvm.clmul.v16i16(<16 x i16> %a16, <16 x i16> %b16) + %call_i8 = call <32 x i8> @llvm.clmul.v32i8(<32 x i8> %a8, <32 x i8> %b8) + ret void +} + +define void @clmul_512(<4 x i128> %a128, <4 x i128> %b128, <8 x i64> %a64, <8 x i64> %b64, <16 x i32> %a32, <16 x i32> %b32, <32 x i16> %a16, <32 x i16> %b16, <64 x i8> %a8, <64 x i8> %b8) { +; PCLMUL-LABEL: 'clmul_512' +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %call_i128 = call <4 x i128> @llvm.clmul.v4i128(<4 x i128> %a128, <4 x i128> %b128) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %call_i64 = call <8 x i64> @llvm.clmul.v8i64(<8 x i64> %a64, <8 x i64> %b64) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %call_i32 = call <16 x i32> @llvm.clmul.v16i32(<16 x i32> %a32, <16 x i32> %b32) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %call_i16 = call <32 x i16> @llvm.clmul.v32i16(<32 x i16> %a16, <32 x i16> %b16) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %call_i8 = call <64 x i8> @llvm.clmul.v64i8(<64 x i8> %a8, <64 x i8> %b8) +; PCLMUL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; NO-PCLMUL-LABEL: 'clmul_512' +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 4096 for instruction: %call_i128 = call <4 x i128> @llvm.clmul.v4i128(<4 x i128> %a128, <4 x i128> %b128) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 2304 for instruction: %call_i64 = call <8 x i64> @llvm.clmul.v8i64(<8 x i64> %a64, <8 x i64> %b64) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 1024 for instruction: %call_i32 = call <16 x i32> @llvm.clmul.v16i32(<16 x i32> %a32, <16 x i32> %b32) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %call_i16 = call <32 x i16> @llvm.clmul.v32i16(<32 x i16> %a16, <32 x i16> %b16) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %call_i8 = call <64 x i8> @llvm.clmul.v64i8(<64 x i8> %a8, <64 x i8> %b8) +; NO-PCLMUL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %call_i128 = call <4 x i128> @llvm.clmul.v4i128(<4 x i128> %a128, <4 x i128> %b128) + %call_i64 = call <8 x i64> @llvm.clmul.v8i64(<8 x i64> %a64, <8 x i64> %b64) + %call_i32 = call <16 x i32> @llvm.clmul.v16i32(<16 x i32> %a32, <16 x i32> %b32) + %call_i16 = call <32 x i16> @llvm.clmul.v32i16(<32 x i16> %a16, <32 x i16> %b16) + %call_i8 = call <64 x i8> @llvm.clmul.v64i8(<64 x i8> %a8, <64 x i8> %b8) + ret void +} diff --git a/llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll b/llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll index c2e1e9213fcc3..44d3a7c1e81dd 100644 --- a/llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll +++ b/llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll @@ -25,13 +25,13 @@ define void @test_vXf64(<2 x double> %a128, <2 x double> %b128, <4 x double> %a2 ; ; AVX-LABEL: 'test_vXf64' ; AVX-NEXT: Cost Model: Found costs of 1 for: %V128 = shufflevector <2 x double> %a128, <2 x double> %b128, <2 x i32> -; AVX-NEXT: Cost Model: Found costs of 2 for: %V256 = shufflevector <4 x double> %a256, <4 x double> %b256, <4 x i32> -; AVX-NEXT: Cost Model: Found costs of 4 for: %V512 = shufflevector <8 x double> %a512, <8 x double> %b512, <8 x i32> +; AVX-NEXT: Cost Model: Found costs of 1 for: %V256 = shufflevector <4 x double> %a256, <4 x double> %b256, <4 x i32> +; AVX-NEXT: Cost Model: Found costs of 2 for: %V512 = shufflevector <8 x double> %a512, <8 x double> %b512, <8 x i32> ; AVX-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; AVX512-LABEL: 'test_vXf64' ; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V128 = shufflevector <2 x double> %a128, <2 x double> %b128, <2 x i32> -; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V256 = shufflevector <4 x double> %a256, <4 x double> %b256, <4 x i32> +; AVX512-NEXT: Cost Model: Found costs of 1 for: %V256 = shufflevector <4 x double> %a256, <4 x double> %b256, <4 x i32> ; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V512 = shufflevector <8 x double> %a512, <8 x double> %b512, <8 x i32> ; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; @@ -50,13 +50,13 @@ define void @test_vXi64(<2 x i64> %a128, <2 x i64> %b128, <4 x i64> %a256, <4 x ; ; AVX-LABEL: 'test_vXi64' ; AVX-NEXT: Cost Model: Found costs of 1 for: %V128 = shufflevector <2 x i64> %a128, <2 x i64> %b128, <2 x i32> -; AVX-NEXT: Cost Model: Found costs of 2 for: %V256 = shufflevector <4 x i64> %a256, <4 x i64> %b256, <4 x i32> -; AVX-NEXT: Cost Model: Found costs of 4 for: %V512 = shufflevector <8 x i64> %a512, <8 x i64> %b512, <8 x i32> +; AVX-NEXT: Cost Model: Found costs of 1 for: %V256 = shufflevector <4 x i64> %a256, <4 x i64> %b256, <4 x i32> +; AVX-NEXT: Cost Model: Found costs of 2 for: %V512 = shufflevector <8 x i64> %a512, <8 x i64> %b512, <8 x i32> ; AVX-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; ; AVX512-LABEL: 'test_vXi64' ; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V128 = shufflevector <2 x i64> %a128, <2 x i64> %b128, <2 x i32> -; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V256 = shufflevector <4 x i64> %a256, <4 x i64> %b256, <4 x i32> +; AVX512-NEXT: Cost Model: Found costs of 1 for: %V256 = shufflevector <4 x i64> %a256, <4 x i64> %b256, <4 x i32> ; AVX512-NEXT: Cost Model: Found costs of RThru:1 CodeSize:1 Lat:3 SizeLat:1 for: %V512 = shufflevector <8 x i64> %a512, <8 x i64> %b512, <8 x i32> ; AVX512-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void ; diff --git a/llvm/test/Analysis/DependenceAnalysis/rdiv-large-btc.ll b/llvm/test/Analysis/DependenceAnalysis/rdiv-large-btc.ll new file mode 100644 index 0000000000000..541f3e0cda014 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/rdiv-large-btc.ll @@ -0,0 +1,83 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output "-passes=print" 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-ALL +; RUN: opt < %s -disable-output "-passes=print" -da-enable-dependence-test=exact-rdiv 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-EXACT-RDIV +; RUN: opt < %s -disable-output "-passes=print" -da-enable-dependence-test=symbolic-rdiv 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-SYMBOLIC-RDIV + +; for (i0 = INT64_MIN; i0 != INT64_MAX; i0++) { +; if (i0 == 0) +; A[i0] = 0; +; } +; for (i1 = INT64_MIN; i1 != INT64_MAX - 1; i1++) { +; if (i1 == 0) +; A[i1] = 0; +; } +; +; FIXME: Both `A[i0] = 0` and `A[i1] = 0` must be executed, so there is a +; dependency between them. +; +define void @rdiv_large_btc(ptr %A) { +; CHECK-ALL-LABEL: 'rdiv_large_btc' +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep.1, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-EXACT-RDIV-LABEL: 'rdiv_large_btc' +; CHECK-EXACT-RDIV-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.0, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - none! +; CHECK-EXACT-RDIV-NEXT: Src: store i8 0, ptr %gep.1, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-EXACT-RDIV-NEXT: da analyze - consistent output [*]! +; +; CHECK-SYMBOLIC-RDIV-LABEL: 'rdiv_large_btc' +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.0, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - none! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - none! +; CHECK-SYMBOLIC-RDIV-NEXT: Src: store i8 0, ptr %gep.1, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-SYMBOLIC-RDIV-NEXT: da analyze - none! +; +entry: + br label %loop.0.header + +loop.0.header: + %i.0 = phi i64 [ -9223372036854775808, %entry ], [ %i.0.inc, %loop.0.latch ] + %cond.0 = icmp eq i64 %i.0, 0 + br i1 %cond.0, label %if.then.0, label %loop.0.latch + +if.then.0: + %gep.0 = getelementptr i8, ptr %A, i64 %i.0 + store i8 0, ptr %gep.0 + br label %loop.0.latch + +loop.0.latch: + %i.0.inc = add i64 %i.0, 1 + %ec.0 = icmp eq i64 %i.0.inc, 9223372036854775807 + br i1 %ec.0, label %loop.1.header, label %loop.0.header + +loop.1.header: + %i.1 = phi i64 [ -9223372036854775808, %loop.0.latch ], [ %i.1.inc, %loop.1.latch ] + %cond.1 = icmp eq i64 %i.1, 0 + br i1 %cond.1, label %if.then.1, label %loop.1.latch + +if.then.1: + %gep.1 = getelementptr i8, ptr %A, i64 %i.1 + store i8 0, ptr %gep.1 + br label %loop.1.latch + +loop.1.latch: + %i.1.inc = add i64 %i.1, 1 + %ec.1 = icmp eq i64 %i.1.inc, 9223372036854775806 + br i1 %ec.1, label %exit, label %loop.1.header + +exit: + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/Analysis/DependenceAnalysis/strong-siv-large-btc.ll b/llvm/test/Analysis/DependenceAnalysis/strong-siv-large-btc.ll new file mode 100644 index 0000000000000..1b3312419bc62 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/strong-siv-large-btc.ll @@ -0,0 +1,62 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output "-passes=print" 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-ALL +; RUN: opt < %s -disable-output "-passes=print" -da-enable-dependence-test=strong-siv 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-STRONG-SIV +; +; i0 = INT64_MIN; +; i1 = INT64_MIN + 1; +; for (; i1 != INT64_MAX; i0++, i1++) { +; if (i0 == 0) +; A[i0] = 0; +; if (i1 == 0) +; A[i1] = 0; +; } +; +; FIXME: Both `A[i0] = 0` and `A[i1] = 0` must be executed, so there is a +; dependency between them. +; +define void @strong_siv_large_btc(ptr %A) { +; CHECK-LABEL: 'strong_siv_large_btc' +; CHECK-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.0, align 1 +; CHECK-NEXT: da analyze - none! +; CHECK-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-NEXT: da analyze - none! +; CHECK-NEXT: Src: store i8 0, ptr %gep.1, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-NEXT: da analyze - none! +; +entry: + br label %loop.header + +loop.header: + %i.0 = phi i64 [ -9223372036854775808, %entry ], [ %i.0.inc, %loop.latch ] + %i.1 = phi i64 [ -9223372036854775807, %entry ], [ %i.1.inc, %loop.latch ] + %cond.0 = icmp eq i64 %i.0, 0 + br i1 %cond.0, label %if.then.0, label %loop.middle + +if.then.0: + %gep.0 = getelementptr i8, ptr %A, i64 %i.0 + store i8 0, ptr %gep.0 + br label %loop.middle + +loop.middle: + %cond.1 = icmp eq i64 %i.1, 0 + br i1 %cond.1, label %if.then.1, label %loop.latch + +if.then.1: + %gep.1 = getelementptr i8, ptr %A, i64 %i.1 + store i8 0, ptr %gep.1 + br label %loop.latch + +loop.latch: + %i.0.inc = add i64 %i.0, 1 + %i.1.inc = add i64 %i.1, 1 + %ec = icmp eq i64 %i.1.inc, 9223372036854775807 + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-ALL: {{.*}} +; CHECK-STRONG-SIV: {{.*}} diff --git a/llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll b/llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll new file mode 100644 index 0000000000000..b097c06e31202 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll @@ -0,0 +1,69 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output "-passes=print" 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-ALL +; RUN: opt < %s -disable-output "-passes=print" -da-enable-dependence-test=weak-crossing-siv 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-WEAK-CROSSING-SIV +; +; i0 = INT64_MIN; +; i1 = INT64_MAX; +; for (; i0 != INT64_MAX; i0++, i1-) { +; if (i0 == 0) +; A[i0] = 0; +; if (i1 == 0) +; A[i1] = 0; +; } +; +; FIXME: Both `A[i0] = 0` and `A[i1] = 0` must be executed, so there is a +; dependency between them. +; +define void @weak_crossing_siv_large_btc(ptr %A) { +; CHECK-ALL-LABEL: 'weak_crossing_siv_large_btc' +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.0, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep.1, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-WEAK-CROSSING-SIV-LABEL: 'weak_crossing_siv_large_btc' +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.0, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 0, ptr %gep.0, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - none! +; CHECK-WEAK-CROSSING-SIV-NEXT: Src: store i8 0, ptr %gep.1, align 1 --> Dst: store i8 0, ptr %gep.1, align 1 +; CHECK-WEAK-CROSSING-SIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop.header + +loop.header: + %i.0 = phi i64 [ -9223372036854775808, %entry ], [ %i.0.inc, %loop.latch ] + %i.1 = phi i64 [ 9223372036854775807, %entry ], [ %i.1.dec, %loop.latch ] + %cond.0 = icmp eq i64 %i.0, 0 + br i1 %cond.0, label %if.then.0, label %loop.middle + +if.then.0: + %gep.0 = getelementptr i8, ptr %A, i64 %i.0 + store i8 0, ptr %gep.0 + br label %loop.middle + +loop.middle: + %cond.1 = icmp eq i64 %i.1, 0 + br i1 %cond.1, label %if.then.1, label %loop.latch + +if.then.1: + %gep.1 = getelementptr i8, ptr %A, i64 %i.1 + store i8 0, ptr %gep.1 + br label %loop.latch + +loop.latch: + %i.0.inc = add i64 %i.0, 1 + %i.1.dec = sub i64 %i.1, 1 + %ec = icmp eq i64 %i.0.inc, 9223372036854775807 + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll b/llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll new file mode 100644 index 0000000000000..c06032798c792 --- /dev/null +++ b/llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll @@ -0,0 +1,106 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -disable-output "-passes=print" 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-ALL +; RUN: opt < %s -disable-output "-passes=print" -da-enable-dependence-test=weak-zero-siv 2>&1 \ +; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-WEAK-ZERO-SRC-SIV +; +; for (i = INT64_MIN + 1; i != INT64_MAX; i++) { +; if (i == 0) +; A[i] = 0; +; A[0] = 1; +; } +; +; FIXME: `A[i] = 0` will be executed (when i == 0), so there is a ; dependency +; between the ; two stores. +; +define void @weak_zero_src_siv_large_btc(ptr %A) { +; CHECK-ALL-LABEL: 'weak_zero_src_siv_large_btc' +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 1, ptr %A, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %A, align 1 --> Dst: store i8 1, ptr %A, align 1 +; CHECK-ALL-NEXT: da analyze - consistent output [S]! +; +; CHECK-WEAK-ZERO-SRC-SIV-LABEL: 'weak_zero_src_siv_large_btc' +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: da analyze - consistent output [*]! +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 1, ptr %A, align 1 +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: da analyze - none! +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: Src: store i8 1, ptr %A, align 1 --> Dst: store i8 1, ptr %A, align 1 +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: da analyze - consistent output [S]! +; +entry: + br label %loop.header + +loop.header: + %i = phi i64 [ -9223372036854775807, %entry ], [ %i.inc, %loop.latch ] + %cond = icmp eq i64 %i, 0 + br i1 %cond, label %if.then, label %loop.latch + +if.then: + %gep = getelementptr i8, ptr %A, i64 %i + store i8 0, ptr %gep + br label %loop.latch + +loop.latch: + store i8 1, ptr %A + %i.inc = add i64 %i, 1 + %ec = icmp eq i64 %i.inc, 9223372036854775807 + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} + +; +; for (i = INT64_MIN + 1; i != INT64_MAX; i++) { +; A[0] = 1; +; if (i == 0) +; A[i] = 0; +; } +; +; FIXME: `A[i] = 0` will be executed (when i == 0), so there is a ; dependency +; between the ; two stores. +; +define void @weak_zero_dst_siv_large_btc(ptr %A) { +; CHECK-ALL-LABEL: 'weak_zero_dst_siv_large_btc' +; CHECK-ALL-NEXT: Src: store i8 1, ptr %A, align 1 --> Dst: store i8 1, ptr %A, align 1 +; CHECK-ALL-NEXT: da analyze - consistent output [S]! +; CHECK-ALL-NEXT: Src: store i8 1, ptr %A, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; CHECK-ALL-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-ALL-NEXT: da analyze - none! +; +; CHECK-WEAK-ZERO-SRC-SIV-LABEL: 'weak_zero_dst_siv_large_btc' +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: Src: store i8 1, ptr %A, align 1 --> Dst: store i8 1, ptr %A, align 1 +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: da analyze - consistent output [S]! +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: Src: store i8 1, ptr %A, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: da analyze - none! +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: Src: store i8 0, ptr %gep, align 1 --> Dst: store i8 0, ptr %gep, align 1 +; CHECK-WEAK-ZERO-SRC-SIV-NEXT: da analyze - consistent output [*]! +; +entry: + br label %loop.header + +loop.header: + %i = phi i64 [ -9223372036854775807, %entry ], [ %i.inc, %loop.latch ] + store i8 1, ptr %A + %cond = icmp eq i64 %i, 0 + br i1 %cond, label %if.then, label %loop.latch + +if.then: + %gep = getelementptr i8, ptr %A, i64 %i + store i8 0, ptr %gep + br label %loop.latch + +loop.latch: + %i.inc = add i64 %i, 1 + %ec = icmp eq i64 %i.inc, 9223372036854775807 + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/Analysis/ValueTracking/assume-queries-counter.ll b/llvm/test/Analysis/ValueTracking/assume-queries-counter.ll index 754e43d327f50..0cb8279f3db38 100644 --- a/llvm/test/Analysis/ValueTracking/assume-queries-counter.ll +++ b/llvm/test/Analysis/ValueTracking/assume-queries-counter.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -passes=instcombine --debug-counter=assume-queries-counter=0 -S | FileCheck %s --check-prefixes=COUNTER1 -; RUN: opt < %s -passes=instcombine --debug-counter=assume-queries-counter=1-2 -S | FileCheck %s --check-prefixes=COUNTER2 -; RUN: opt < %s -passes=instcombine --debug-counter=assume-queries-counter=2-6 -S | FileCheck %s --check-prefixes=COUNTER3 +; RUN: opt < %s -passes=instcombine --debug-counter=assume-queries-counter=1 -S | FileCheck %s --check-prefixes=COUNTER1 +; RUN: opt < %s -passes=instcombine --debug-counter=assume-queries-counter=2-3 -S | FileCheck %s --check-prefixes=COUNTER2 +; RUN: opt < %s -passes=instcombine --debug-counter=assume-queries-counter=4-7 -S | FileCheck %s --check-prefixes=COUNTER3 declare i1 @get_val() declare void @llvm.assume(i1) @@ -38,8 +38,9 @@ define dso_local i1 @test2(ptr readonly %0) { ; COUNTER2-NEXT: ret i1 false ; ; COUNTER3-LABEL: @test2( -; COUNTER3-NEXT: call void @llvm.assume(i1 true) [ "nonnull"(ptr [[TMP0:%.*]]) ] -; COUNTER3-NEXT: ret i1 false +; COUNTER3-NEXT: [[TMP2:%.*]] = icmp eq ptr [[TMP0:%.*]], null +; COUNTER3-NEXT: call void @llvm.assume(i1 true) [ "nonnull"(ptr [[TMP0]]) ] +; COUNTER3-NEXT: ret i1 [[TMP2]] ; %2 = icmp eq ptr %0, null call void @llvm.assume(i1 true) ["nonnull"(ptr %0)] diff --git a/llvm/test/Analysis/ValueTracking/knownbits-bmi-pattern.ll b/llvm/test/Analysis/ValueTracking/knownbits-bmi-pattern.ll index 663de281f19ba..868e340c266ad 100644 --- a/llvm/test/Analysis/ValueTracking/knownbits-bmi-pattern.ll +++ b/llvm/test/Analysis/ValueTracking/knownbits-bmi-pattern.ll @@ -221,8 +221,7 @@ define i1 @blsmsk_gt_is_false_assume(i32 %x) { define i32 @blsmsk_add_eval_assume(i32 %x) { ; CHECK-LABEL: @blsmsk_add_eval_assume( -; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: ret i32 33 ; @@ -261,8 +260,7 @@ define <2 x i32> @blsmsk_add_eval_assume_vec(<2 x i32> %x) { define i32 @blsmsk_sub_eval_assume(i32 %x) { ; CHECK-LABEL: @blsmsk_sub_eval_assume( -; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: ret i32 -31 ; @@ -277,8 +275,7 @@ define i32 @blsmsk_sub_eval_assume(i32 %x) { define i32 @blsmsk_or_eval_assume(i32 %x) { ; CHECK-LABEL: @blsmsk_or_eval_assume( -; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: ret i32 33 ; @@ -545,8 +542,7 @@ define <2 x i1> @blsi_cmp_eq_diff_bits_vec(<2 x i32> %x) { define i32 @blsi_xor_eval_assume(i32 %x) { ; CHECK-LABEL: @blsi_xor_eval_assume( -; CHECK-NEXT: [[LB:%.*]] = and i32 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[LB]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[X:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: ret i32 33 ; diff --git a/llvm/test/Assembler/denormal_fpenv.ll b/llvm/test/Assembler/denormal_fpenv.ll new file mode 100644 index 0000000000000..95f70bfb44503 --- /dev/null +++ b/llvm/test/Assembler/denormal_fpenv.ll @@ -0,0 +1,295 @@ +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s + +define void @func_ieee() denormal_fpenv(ieee) { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @func_ieee( +; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_preservesign() denormal_fpenv(preservesign) { +; CHECK: Function Attrs: denormal_fpenv(preservesign) +; CHECK-LABEL: define void @func_preservesign( +; CHECK-SAME: ) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_positivezero() denormal_fpenv(positivezero) { +; CHECK: Function Attrs: denormal_fpenv(positivezero) +; CHECK-LABEL: define void @func_positivezero( +; CHECK-SAME: ) #[[ATTR2:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_dynamic() denormal_fpenv(dynamic) { +; CHECK: Function Attrs: denormal_fpenv(dynamic) +; CHECK-LABEL: define void @func_dynamic( +; CHECK-SAME: ) #[[ATTR3:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_ieee_ieee() denormal_fpenv(ieee|ieee) { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @func_ieee_ieee( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_preservesign_preservesign() denormal_fpenv(preservesign|preservesign) { +; CHECK: Function Attrs: denormal_fpenv(preservesign) +; CHECK-LABEL: define void @func_preservesign_preservesign( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_positivezero_positivezero() denormal_fpenv(positivezero|positivezero) { +; CHECK: Function Attrs: denormal_fpenv(positivezero) +; CHECK-LABEL: define void @func_positivezero_positivezero( +; CHECK-SAME: ) #[[ATTR2]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_dynamic_dynamic() denormal_fpenv(dynamic|dynamic) { +; CHECK: Function Attrs: denormal_fpenv(dynamic) +; CHECK-LABEL: define void @func_dynamic_dynamic( +; CHECK-SAME: ) #[[ATTR3]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_ieee_preservesign() denormal_fpenv(ieee|preservesign) { +; CHECK-LABEL: define void @func_ieee_preservesign( +; CHECK-SAME: ) #[[ATTR4:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_preservesign_ieee() denormal_fpenv(preservesign|ieee) { +; CHECK-LABEL: define void @func_preservesign_ieee( +; CHECK-SAME: ) #[[ATTR5:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_ieee_dynamic() denormal_fpenv(ieee|dynamic) { +; CHECK-LABEL: define void @func_ieee_dynamic( +; CHECK-SAME: ) #[[ATTR6:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_dynamic_ieee() denormal_fpenv(dynamic|ieee) { +; CHECK-LABEL: define void @func_dynamic_ieee( +; CHECK-SAME: ) #[[ATTR7:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_ieee_positivezero() denormal_fpenv(ieee|positivezero) { +; CHECK-LABEL: define void @func_ieee_positivezero( +; CHECK-SAME: ) #[[ATTR8:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_positivezero_ieee() denormal_fpenv(positivezero|ieee) { +; CHECK-LABEL: define void @func_positivezero_ieee( +; CHECK-SAME: ) #[[ATTR9:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_positivezero_dynamic() denormal_fpenv(positivezero|dynamic) { +; CHECK-LABEL: define void @func_positivezero_dynamic( +; CHECK-SAME: ) #[[ATTR10:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_dynamic_positivezero() denormal_fpenv(dynamic|positivezero) { +; CHECK-LABEL: define void @func_dynamic_positivezero( +; CHECK-SAME: ) #[[ATTR11:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_attr_group0() #0 { +; CHECK-LABEL: define void @func_attr_group0( +; CHECK-SAME: ) #[[ATTR12:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_attr_group1() #1 { +; CHECK: Function Attrs: denormal_fpenv(preservesign) +; CHECK-LABEL: define void @func_attr_group1( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_ieee() denormal_fpenv(float:ieee) { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @func_f32_ieee( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_preservesign() denormal_fpenv(float: preservesign) { +; CHECK: Function Attrs: denormal_fpenv(float: preservesign) +; CHECK-LABEL: define void @func_f32_preservesign( +; CHECK-SAME: ) #[[ATTR13:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_positivezero() denormal_fpenv(float: positivezero) { +; CHECK: Function Attrs: denormal_fpenv(float: positivezero) +; CHECK-LABEL: define void @func_f32_positivezero( +; CHECK-SAME: ) #[[ATTR14:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_dynamic() denormal_fpenv(float: dynamic) { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) +; CHECK-LABEL: define void @func_f32_dynamic( +; CHECK-SAME: ) #[[ATTR15:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_ieee_ieee() denormal_fpenv(float: ieee|ieee) { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @func_f32_ieee_ieee( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_preservesign_preservesign() denormal_fpenv(float: preservesign|preservesign) { +; CHECK: Function Attrs: denormal_fpenv(float: preservesign) +; CHECK-LABEL: define void @func_f32_preservesign_preservesign( +; CHECK-SAME: ) #[[ATTR13]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_positivezero_positivezero() denormal_fpenv(float: positivezero|positivezero) { +; CHECK: Function Attrs: denormal_fpenv(float: positivezero) +; CHECK-LABEL: define void @func_f32_positivezero_positivezero( +; CHECK-SAME: ) #[[ATTR14]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_dynamic_dynamic() denormal_fpenv(float: dynamic|dynamic) { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) +; CHECK-LABEL: define void @func_f32_dynamic_dynamic( +; CHECK-SAME: ) #[[ATTR15]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_preservesign_ieee() denormal_fpenv(float: preservesign|ieee) { +; CHECK-LABEL: define void @func_f32_preservesign_ieee( +; CHECK-SAME: ) #[[ATTR16:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f32_dynamic_positivezero() denormal_fpenv(float:dynamic|positivezero) { +; CHECK-LABEL: define void @func_f32_dynamic_positivezero( +; CHECK-SAME: ) #[[ATTR17:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f64_dynamic__f32_ieee() denormal_fpenv(dynamic, float:ieee) { +; CHECK: Function Attrs: denormal_fpenv(dynamic, float: ieee) +; CHECK-LABEL: define void @func_f64_dynamic__f32_ieee( +; CHECK-SAME: ) #[[ATTR18:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f64_dynamic__f32_preservesign() denormal_fpenv(dynamic, float:preservesign) { +; CHECK: Function Attrs: denormal_fpenv(dynamic, float: preservesign) +; CHECK-LABEL: define void @func_f64_dynamic__f32_preservesign( +; CHECK-SAME: ) #[[ATTR19:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @func_f64_dynamic_ieee__f32_preservesign_ieee() denormal_fpenv(dynamic|ieee, float:preservesign|ieee) { +; +; CHECK-LABEL: define void @func_f64_dynamic_ieee__f32_preservesign_ieee( +; CHECK-SAME: ) #[[ATTR20:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +attributes #0 = { denormal_fpenv(preservesign|dynamic) } +attributes #1 = { denormal_fpenv(preservesign) } +;. +; CHECK: attributes #[[ATTR0]] = { denormal_fpenv(ieee) } +; CHECK: attributes #[[ATTR1]] = { denormal_fpenv(preservesign) } +; CHECK: attributes #[[ATTR2]] = { denormal_fpenv(positivezero) } +; CHECK: attributes #[[ATTR3]] = { denormal_fpenv(dynamic) } +; CHECK: attributes #[[ATTR4]] = { denormal_fpenv(ieee|preservesign) } +; CHECK: attributes #[[ATTR5]] = { denormal_fpenv(preservesign|ieee) } +; CHECK: attributes #[[ATTR6]] = { denormal_fpenv(ieee|dynamic) } +; CHECK: attributes #[[ATTR7]] = { denormal_fpenv(dynamic|ieee) } +; CHECK: attributes #[[ATTR8]] = { denormal_fpenv(ieee|positivezero) } +; CHECK: attributes #[[ATTR9]] = { denormal_fpenv(positivezero|ieee) } +; CHECK: attributes #[[ATTR10]] = { denormal_fpenv(positivezero|dynamic) } +; CHECK: attributes #[[ATTR11]] = { denormal_fpenv(dynamic|positivezero) } +; CHECK: attributes #[[ATTR12]] = { denormal_fpenv(preservesign|dynamic) } +; CHECK: attributes #[[ATTR13]] = { denormal_fpenv(float: preservesign) } +; CHECK: attributes #[[ATTR14]] = { denormal_fpenv(float: positivezero) } +; CHECK: attributes #[[ATTR15]] = { denormal_fpenv(float: dynamic) } +; CHECK: attributes #[[ATTR16]] = { denormal_fpenv(float: preservesign|ieee) } +; CHECK: attributes #[[ATTR17]] = { denormal_fpenv(float: dynamic|positivezero) } +; CHECK: attributes #[[ATTR18]] = { denormal_fpenv(dynamic, float: ieee) } +; CHECK: attributes #[[ATTR19]] = { denormal_fpenv(dynamic, float: preservesign) } +; CHECK: attributes #[[ATTR20]] = { denormal_fpenv(dynamic|ieee, float: preservesign|ieee) } +;. diff --git a/llvm/test/Assembler/invalid_denormal_fpenv.ll b/llvm/test/Assembler/invalid_denormal_fpenv.ll new file mode 100644 index 0000000000000..ce8aa65fedea4 --- /dev/null +++ b/llvm/test/Assembler/invalid_denormal_fpenv.ll @@ -0,0 +1,201 @@ +; RUN: rm -rf %t && split-file %s %t +; RUN: not llvm-as %t/denormal_fpenv_no_parens.ll -disable-output 2>&1 | FileCheck -check-prefix=NOPARENS %s +; RUN: not llvm-as %t/denormal_fpenv_lparen.ll -disable-output 2>&1 | FileCheck -check-prefix=LPAREN %s +; RUN: not llvm-as %t/denormal_fpenv_rparen.ll -disable-output 2>&1 | FileCheck -check-prefix=RPAREN %s +; RUN: not llvm-as %t/denormal_fpenv_empty_parens.ll -disable-output 2>&1 | FileCheck -check-prefix=EMPTYPARENS %s +; RUN: not llvm-as %t/invalid_single_entry.ll -disable-output 2>&1 | FileCheck -check-prefix=INVALID_SINGLE_ENTRY %s +; RUN: not llvm-as %t/invalid_multi_entry0.ll -disable-output 2>&1 | FileCheck -check-prefix=INVALID_MULTI_ENTRY0 %s +; RUN: not llvm-as %t/invalid_multi_entry1.ll -disable-output 2>&1 | FileCheck -check-prefix=INVALID_MULTI_ENTRY1 %s +; RUN: not llvm-as %t/invalid_second_element.ll -disable-output 2>&1 | FileCheck -check-prefix=INVALID_SECOND_ELEMENT %s +; RUN: not llvm-as %t/missing_bar.ll -disable-output 2>&1 | FileCheck -check-prefix=MISSING_BAR %s +; RUN: not llvm-as %t/with_comma.ll -disable-output 2>&1 | FileCheck -check-prefix=WITH_COMMA %s +; RUN: not llvm-as %t/missing_rparen_one_elt.ll -disable-output 2>&1 | FileCheck -check-prefix=MISSING_RPAREN_ONEELT %s +; RUN: not llvm-as %t/missing_rparen_two_elt.ll -disable-output 2>&1 | FileCheck -check-prefix=MISSING_RPAREN_TWOELT %s +; RUN: not llvm-as %t/extra_elt.ll -disable-output 2>&1 | FileCheck -check-prefix=EXTRA_ELT %s +; RUN: not llvm-as %t/arg_attr.ll -disable-output 2>&1 | FileCheck -check-prefix=ARG_ATTR %s +; RUN: not llvm-as %t/ret_attr.ll -disable-output 2>&1 | FileCheck -check-prefix=RET_ATTR %s +; RUN: not llvm-as %t/start_not_float_type.ll -disable-output 2>&1 | FileCheck -check-prefix=START_NOT_FLOAT %s +; RUN: not llvm-as %t/only_float.ll -disable-output 2>&1 | FileCheck -check-prefix=ONLY_FLOAT %s +; RUN: not llvm-as %t/only_float_colon.ll -disable-output 2>&1 | FileCheck -check-prefix=ONLY_FLOAT_COLON %s +; RUN: not llvm-as %t/only_float_mode_invalid_single_entry.ll -disable-output 2>&1 | FileCheck -check-prefix=FLOAT_INVALID_SINGLE_ELT %s +; RUN: not llvm-as %t/only_float_mode_invalid_two_entries.ll -disable-output 2>&1 | FileCheck -check-prefix=FLOAT_INVALID_TWO_ELT %s +; RUN: not llvm-as %t/only_float_mode_invalid_second_entry.ll -disable-output 2>&1 | FileCheck -check-prefix=FLOAT_INVALID_SECOND_ENTRY %s +; RUN: not llvm-as %t/both_sections_wrong_type.ll -disable-output 2>&1 | FileCheck -check-prefix=BOTH_SECTIONS_WRONG_TYPE %s +; RUN: not llvm-as %t/both_sections_invalid_float_entry0.ll -disable-output 2>&1 | FileCheck -check-prefix=BOTH_SECTIONS_INVALID_FLOAT_ENTRY0 %s +; RUN: not llvm-as %t/both_sections_invalid_float_entry1.ll -disable-output 2>&1 | FileCheck -check-prefix=BOTH_SECTIONS_INVALID_FLOAT_ENTRY1 %s +; RUN: not llvm-as %t/missing_comma_float.ll -disable-output 2>&1 | FileCheck -check-prefix=MISSING_COMMA_FLOAT %s + + +;--- denormal_fpenv_no_parens.ll + +; NOPARENS: :36: error: expected '(' +define void @func() denormal_fpenv { + ret void +} + +;--- denormal_fpenv_lparen.ll +; LPAREN: 37: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv( { + ret void +} + +;--- denormal_fpenv_rparen.ll + +; RPAREN: :35: error: expected '(' +define void @func() denormal_fpenv) { + ret void +} + +;--- denormal_fpenv_empty_parens.ll + +; EMPTYPARENS: :36: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv() { + ret void +} + +;--- invalid_single_entry.ll + +; INVALID_SINGLE_ENTRY: :36: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(invalid) { + ret void +} + +;--- invalid_multi_entry0.ll + +; INVALID_MULTI_ENTRY0: :36: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(invalid|invalid) { + ret void +} + +;--- invalid_multi_entry1.ll + +; INVALID_MULTI_ENTRY1: :36: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(invalid0|invalid1) { + ret void +} + +;--- invalid_second_element.ll + +; INVALID_SECOND_ELEMENT: :44: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(dynamic|invalid1) { + ret void +} + +;--- missing_bar.ll + +; MISSING_BAR: :49: error: unterminated denormal_fpenv +define void @func() denormal_fpenv(preservesign preservesign) { + ret void +} + +;--- with_comma.ll + +; WITH_COMMA: :49: error: unterminated denormal_fpenv +define void @func() denormal_fpenv(preservesign,preservesign) { + ret void +} + +;--- missing_rparen_one_elt.ll + +; MISSING_RPAREN_ONEELT: :49: error: unterminated denormal_fpenv +define void @func() denormal_fpenv(preservesign { + ret void +} + +;--- missing_rparen_two_elt.ll + +; MISSING_RPAREN_TWOELT: :58: error: unterminated denormal_fpenv +define void @func() denormal_fpenv(preservesign| dynamic { + ret void +} + +;--- extra_elt.ll + +; EXTRA_ELT: :53: error: unterminated denormal_fpenv +define void @func() denormal_fpenv(preservesign|ieee|preservesign) { + ret void +} + +;--- arg_attr.ll + +; ARG_ATTR: :25: error: this attribute does not apply to parameters +define void @func(float denormal_fpenv(preservesign) %arg) { + ret void +} + +;--- ret_attr.ll + +; RET_ATTR: :8: error: this attribute does not apply to return values +define denormal_fpenv(preservesign) float @func() { + ret void +} + +;--- start_not_float_type.ll + +; START_NOT_FLOAT: :42: error: expected float: +define void @func() denormal_fpenv(double) { + ret void +} + +;--- only_float.ll + +; ONLY_FLOAT: :41: error: expected ':' before float denormal_fpenv +define void @func() denormal_fpenv(float) { + ret void +} + +;--- only_float_colon.ll + +; ONLY_FLOAT_COLON: :42: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(float:) { + ret void +} + +;--- only_float_mode_invalid_single_entry.ll + +; FLOAT_INVALID_SINGLE_ELT: :42: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(float:invalid) { + ret void +} + +;--- only_float_mode_invalid_two_entries.ll + +; FLOAT_INVALID_TWO_ELT: :42: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(float:invalid|invalid) { + ret void +} + +;--- only_float_mode_invalid_second_entry.ll + +; FLOAT_INVALID_SECOND_ENTRY: :55: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(float:preservesign|invalid) { + ret void +} + +;--- both_sections_wrong_type.ll + +; BOTH_SECTIONS_WRONG_TYPE: :61: error: expected float: +define void @func() denormal_fpenv(preservesign|ieee, double:dynamic|preservesign) { + ret void +} + +;--- both_sections_invalid_float_entry0.ll + +; BOTH_SECTIONS_INVALID_FLOAT_ENTRY0: :61: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(preservesign|ieee, float:invalid|dynamic) { + ret void +} + +;--- both_sections_invalid_float_entry1.ll + +; BOTH_SECTIONS_INVALID_FLOAT_ENTRY1: :69: error: expected denormal behavior kind (ieee, preservesign, positivezero, dynamic) +define void @func() denormal_fpenv(preservesign|ieee, float:dynamic|invalid) { + ret void +} + +;--- missing_comma_float.ll + +; MISSING_COMMA_FLOAT: :54: error: expected ',' before float: +define void @func() denormal_fpenv(preservesign|ieee float:dynamic|invalid) { + ret void +} diff --git a/llvm/test/Bitcode/auto_upgrade_denormal_fp_math.ll b/llvm/test/Bitcode/auto_upgrade_denormal_fp_math.ll new file mode 100644 index 0000000000000..ccbd7189910ce --- /dev/null +++ b/llvm/test/Bitcode/auto_upgrade_denormal_fp_math.ll @@ -0,0 +1,378 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s + +; Invalid but didn't fail the verifier +define void @str_denormal_fp_math_no_val() "denormal-fp-math" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_no_val( +; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +; Invalid but didn't fail the verifier +define void @str_denormal_fp_math_empty_str() "denormal-fp-math"="" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_empty_str( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_ieee() "denormal-fp-math"="ieee" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_ieee( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_ieee_ieee() "denormal-fp-math"="ieee,ieee" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_ieee_ieee( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_preserve_sign() "denormal-fp-math"="preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_preserve_sign( +; CHECK-SAME: ) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_preserve_sign_preserve_sign() "denormal-fp-math"="preserve-sign,preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_preserve_sign_preserve_sign( +; CHECK-SAME: ) #[[ATTR1]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_dynamic() "denormal-fp-math"="dynamic" { +; CHECK: Function Attrs: denormal_fpenv(dynamic) +; CHECK-LABEL: define void @str_denormal_fp_math_dynamic( +; CHECK-SAME: ) #[[ATTR2:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_dynamic_dynamic() "denormal-fp-math"="dynamic,dynamic" { +; CHECK: Function Attrs: denormal_fpenv(dynamic) +; CHECK-LABEL: define void @str_denormal_fp_math_dynamic_dynamic( +; CHECK-SAME: ) #[[ATTR2]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_positivezero() "denormal-fp-math"="positive-zero" { +; CHECK: Function Attrs: denormal_fpenv(positivezero) +; CHECK-LABEL: define void @str_denormal_fp_math_positivezero( +; CHECK-SAME: ) #[[ATTR3:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_positivezero_positivezero() "denormal-fp-math"="positive-zero,positive-zero" { +; CHECK: Function Attrs: denormal_fpenv(positivezero) +; CHECK-LABEL: define void @str_denormal_fp_math_positivezero_positivezero( +; CHECK-SAME: ) #[[ATTR3]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_ieee_preservesign() "denormal-fp-math"="ieee,preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(ieee|preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_ieee_preservesign( +; CHECK-SAME: ) #[[ATTR4:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_preservesign_ieee() "denormal-fp-math"="preserve-sign,ieee" { +; CHECK: Function Attrs: denormal_fpenv(preservesign|ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_preservesign_ieee( +; CHECK-SAME: ) #[[ATTR5:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + + +; Invalid but didn't fail the verifier +define void @str_denormal_fp_math_f32_no_val() "denormal-fp-math-f32" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_no_val( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +; Invalid but didn't fail the verifier +define void @str_denormal_fp_math_f32_empty_str() "denormal-fp-math-f32"="" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_empty_str( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_ieee() "denormal-fp-math-f32"="ieee" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_ieee( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_ieee_ieee() "denormal-fp-math-f32"="ieee,ieee" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_ieee_ieee( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_preserve_sign() "denormal-fp-math-f32"="preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(float: preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_preserve_sign( +; CHECK-SAME: ) #[[ATTR6:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_preserve_sign_preserve_sign() "denormal-fp-math-f32"="preserve-sign,preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(float: preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_preserve_sign_preserve_sign( +; CHECK-SAME: ) #[[ATTR6]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_dynamic() "denormal-fp-math-f32"="dynamic" { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_dynamic( +; CHECK-SAME: ) #[[ATTR7:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_dynamic_dynamic() "denormal-fp-math-f32"="dynamic,dynamic" { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_dynamic_dynamic( +; CHECK-SAME: ) #[[ATTR7]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_positivezero() "denormal-fp-math-f32"="positive-zero" { +; CHECK: Function Attrs: denormal_fpenv(float: positivezero) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_positivezero( +; CHECK-SAME: ) #[[ATTR8:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_positivezero_positivezero() "denormal-fp-math-f32"="positive-zero,positive-zero" { +; CHECK: Function Attrs: denormal_fpenv(float: positivezero) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_positivezero_positivezero( +; CHECK-SAME: ) #[[ATTR8]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_ieee_preservesign() "denormal-fp-math-f32"="ieee,preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(float: ieee|preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_ieee_preservesign( +; CHECK-SAME: ) #[[ATTR9:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_f32_preservesign_ieee() "denormal-fp-math-f32"="preserve-sign,ieee" { +; CHECK: Function Attrs: denormal_fpenv(float: preservesign|ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_f32_preservesign_ieee( +; CHECK-SAME: ) #[[ATTR10:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_ieee__denormal_fp_math_f32_ieee() "denormal-fp-math"="ieee" "denormal-fp-math-f32"="ieee" { +; CHECK: Function Attrs: denormal_fpenv(ieee) +; CHECK-LABEL: define void @str_denormal_fp_math_ieee__denormal_fp_math_f32_ieee( +; CHECK-SAME: ) #[[ATTR0]] { +; CHECK-NEXT: ret void +; + ret void +} + + +define void @str_denormal_fp_math_ieee__denormal_fp_math_f32_preserve_sign() "denormal-fp-math"="ieee" "denormal-fp-math-f32"="preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(float: preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_ieee__denormal_fp_math_f32_preserve_sign( +; CHECK-SAME: ) #[[ATTR6]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_ieee_ieee__denormal_fp_math_f32_preserve_sign_preserve_sign() "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="preserve-sign,preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(float: preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_ieee_ieee__denormal_fp_math_f32_preserve_sign_preserve_sign( +; CHECK-SAME: ) #[[ATTR6]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_ieee_ieee__denormal_fp_math_f32_preserve_sign_dynamic_dynamic() "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="dynamic,dynamic" { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) +; CHECK-LABEL: define void @str_denormal_fp_math_ieee_ieee__denormal_fp_math_f32_preserve_sign_dynamic_dynamic( +; CHECK-SAME: ) #[[ATTR7]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_dynamic_dynamic__denormal_fp_math_f32_preserve_sign_dynamic_dynamic() "denormal-fp-math"="dynamic,dynamic" "denormal-fp-math-f32"="dynamic,dynamic" { +; CHECK: Function Attrs: denormal_fpenv(dynamic) +; CHECK-LABEL: define void @str_denormal_fp_math_dynamic_dynamic__denormal_fp_math_f32_preserve_sign_dynamic_dynamic( +; CHECK-SAME: ) #[[ATTR2]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_dynamic_dynamic__denormal_fp_math_f32_preserve_sign_preserve_sign() "denormal-fp-math"="dynamic,dynamic" "denormal-fp-math-f32"="preserve-sign,preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(dynamic, float: preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_dynamic_dynamic__denormal_fp_math_f32_preserve_sign_preserve_sign( +; CHECK-SAME: ) #[[ATTR11:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +define void @str_denormal_fp_math_dynamic_positive_zero__denormal_fp_math_f32_preserve_sign_dynamic_preserve_sign() "denormal-fp-math"="dynamic,positive-zero" "denormal-fp-math-f32"="dynamic,preserve-sign" { +; CHECK: Function Attrs: denormal_fpenv(dynamic|positivezero, float: dynamic|preservesign) +; CHECK-LABEL: define void @str_denormal_fp_math_dynamic_positive_zero__denormal_fp_math_f32_preserve_sign_dynamic_preserve_sign( +; CHECK-SAME: ) #[[ATTR12:[0-9]+]] { +; CHECK-NEXT: ret void +; + ret void +} + +declare void @func() + +; These never did anything, but the new attribute fails the verifier +; on call sites. +define void @ignore_callsite_attrs() { +; CHECK-LABEL: define void @ignore_callsite_attrs() { +; CHECK-NEXT: call void @func() #[[ATTR19:[0-9]+]] +; CHECK-NEXT: call void @func() #[[ATTR20:[0-9]+]] +; CHECK-NEXT: call void @func() #[[ATTR21:[0-9]+]] +; CHECK-NEXT: ret void +; + call void @func() "denormal-fp-math"="preserve-sign,preserve-sign" + call void @func() "denormal-fp-math-f32"="preserve-sign,preserve-sign" + call void @func() "denormal-fp-math"="dynamic,ieee" "denormal-fp-math-f32"="preserve-sign,preserve-sign" + ret void +} + +define float @test_denormal_fp_math_invalid1() "denormal-fp-math"="foo,ieee" { +; CHECK-LABEL: define float @test_denormal_fp_math_invalid1( +; CHECK-SAME: ) #[[ATTR13:[0-9]+]] { +; CHECK-NEXT: ret float 1.000000e+00 +; + ret float 1.0 +} + +define float @test_denormal_fp_math_invalid2() "denormal-fp-math"="ieee,ieee,ieee" { +; CHECK-LABEL: define float @test_denormal_fp_math_invalid2( +; CHECK-SAME: ) #[[ATTR14:[0-9]+]] { +; CHECK-NEXT: ret float 1.000000e+00 +; + ret float 1.0 +} + +define float @test_denormal_fp_math_f32_invalid() "denormal-fp-math-f32"="foo,ieee" { +; CHECK-LABEL: define float @test_denormal_fp_math_f32_invalid( +; CHECK-SAME: ) #[[ATTR15:[0-9]+]] { +; CHECK-NEXT: ret float 1.000000e+00 +; + ret float 1.0 +} + +define float @test_both_denormal_fp_math_invalid() "denormal-fp-math"="bar" "denormal-fp-math-f32"="foo,ieee" { +; CHECK-LABEL: define float @test_both_denormal_fp_math_invalid( +; CHECK-SAME: ) #[[ATTR16:[0-9]+]] { +; CHECK-NEXT: ret float 1.000000e+00 +; + ret float 1.0 +} + +define float @test_denormal_fp_math_invalid_with_invalid_f32() "denormal-fp-math"="dynamic,dynamic" "denormal-fp-math-f32"="foo,ieee" { +; CHECK: Function Attrs: denormal_fpenv(dynamic) +; CHECK-LABEL: define float @test_denormal_fp_math_invalid_with_invalid_f32( +; CHECK-SAME: ) #[[ATTR17:[0-9]+]] { +; CHECK-NEXT: ret float 1.000000e+00 +; + ret float 1.0 +} + +define float @test_invalid_denormal_fp_math_with_valid_f32() "denormal-fp-math"="foo,dynamic" "denormal-fp-math-f32"="dynamic,dynamic" { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) +; CHECK-LABEL: define float @test_invalid_denormal_fp_math_with_valid_f32( +; CHECK-SAME: ) #[[ATTR18:[0-9]+]] { +; CHECK-NEXT: ret float 1.000000e+00 +; + ret float 1.0 +} + +;. +; CHECK: attributes #[[ATTR0]] = { denormal_fpenv(ieee) } +; CHECK: attributes #[[ATTR1]] = { denormal_fpenv(preservesign) } +; CHECK: attributes #[[ATTR2]] = { denormal_fpenv(dynamic) } +; CHECK: attributes #[[ATTR3]] = { denormal_fpenv(positivezero) } +; CHECK: attributes #[[ATTR4]] = { denormal_fpenv(ieee|preservesign) } +; CHECK: attributes #[[ATTR5]] = { denormal_fpenv(preservesign|ieee) } +; CHECK: attributes #[[ATTR6]] = { denormal_fpenv(float: preservesign) } +; CHECK: attributes #[[ATTR7]] = { denormal_fpenv(float: dynamic) } +; CHECK: attributes #[[ATTR8]] = { denormal_fpenv(float: positivezero) } +; CHECK: attributes #[[ATTR9]] = { denormal_fpenv(float: ieee|preservesign) } +; CHECK: attributes #[[ATTR10]] = { denormal_fpenv(float: preservesign|ieee) } +; CHECK: attributes #[[ATTR11]] = { denormal_fpenv(dynamic, float: preservesign) } +; CHECK: attributes #[[ATTR12]] = { denormal_fpenv(dynamic|positivezero, float: dynamic|preservesign) } +; CHECK: attributes #[[ATTR13]] = { "denormal-fp-math"="foo,ieee" } +; CHECK: attributes #[[ATTR14]] = { "denormal-fp-math"="ieee,ieee,ieee" } +; CHECK: attributes #[[ATTR15]] = { "denormal-fp-math-f32"="foo,ieee" } +; CHECK: attributes #[[ATTR16]] = { "denormal-fp-math"="bar" "denormal-fp-math-f32"="foo,ieee" } +; CHECK: attributes #[[ATTR17]] = { denormal_fpenv(dynamic) "denormal-fp-math-f32"="foo,ieee" } +; CHECK: attributes #[[ATTR18]] = { denormal_fpenv(float: dynamic) "denormal-fp-math"="foo,dynamic" } +; CHECK: attributes #[[ATTR19]] = { "denormal-fp-math"="preserve-sign,preserve-sign" } +; CHECK: attributes #[[ATTR20]] = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +; CHECK: attributes #[[ATTR21]] = { "denormal-fp-math"="dynamic,ieee" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +;. diff --git a/llvm/test/Bitcode/compatibility.ll b/llvm/test/Bitcode/compatibility.ll index 53cbe2d6ffd37..7ecc92ae16e97 100644 --- a/llvm/test/Bitcode/compatibility.ll +++ b/llvm/test/Bitcode/compatibility.ll @@ -1722,7 +1722,7 @@ exit: ; CHECK: select <2 x i1> , <2 x i8> , <2 x i8> call void @f.nobuiltin() builtin - ; CHECK: call void @f.nobuiltin() #55 + ; CHECK: call void @f.nobuiltin() #87 call fastcc noalias ptr @f.noalias() noinline ; CHECK: call fastcc noalias ptr @f.noalias() #12 @@ -2237,6 +2237,200 @@ define float @nofpclass_callsites(float %arg, { float } %arg1) { ret float %add1 } +; CHECK: define void @denormal_fpenv__ieee_ieee() #55 { +define void @denormal_fpenv__ieee_ieee() denormal_fpenv(ieee|ieee) { + ret void +} + +; CHECK: define void @denormal_fpenv__ieee_preservesign() #56 { +define void @denormal_fpenv__ieee_preservesign() denormal_fpenv(ieee|preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv__ieee_positivezero() #57 { +define void @denormal_fpenv__ieee_positivezero() denormal_fpenv(ieee|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv__ieee_dynamic() #58 { +define void @denormal_fpenv__ieee_dynamic() denormal_fpenv(ieee|dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv__preservesign_ieee() #59 { +define void @denormal_fpenv__preservesign_ieee() denormal_fpenv(preservesign|ieee) { + ret void +} + +; CHECK: define void @denormal_fpenv__preservesign_preservesign() #60 { +define void @denormal_fpenv__preservesign_preservesign() denormal_fpenv(preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv__preservesign_positivezero() #61 { +define void @denormal_fpenv__preservesign_positivezero() denormal_fpenv(preservesign|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv__preservesign_dynamic() #62 { +define void @denormal_fpenv__preservesign_dynamic() denormal_fpenv(preservesign|dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv__positivezero_ieee() #63 { +define void @denormal_fpenv__positivezero_ieee() denormal_fpenv(positivezero|ieee) { + ret void +} + +; CHECK: define void @denormal_fpenv__positivezero_preservesign() #64 { +define void @denormal_fpenv__positivezero_preservesign() denormal_fpenv(positivezero|preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv__positivezero_positivezero() #65 { +define void @denormal_fpenv__positivezero_positivezero() denormal_fpenv(positivezero|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv__positivezero_dynamix() #66 { +define void @denormal_fpenv__positivezero_dynamix() denormal_fpenv(positivezero|dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv__dynamic_ieee() #67 { +define void @denormal_fpenv__dynamic_ieee() denormal_fpenv(dynamic|ieee) { + ret void +} + +; CHECK: define void @denormal_fpenv__dynamic_preservesign() #68 { +define void @denormal_fpenv__dynamic_preservesign() denormal_fpenv(dynamic|preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv__dynamic_positivezero() #69 { +define void @denormal_fpenv__dynamic_positivezero() denormal_fpenv(dynamic|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv__dynamic_dynamic() #70 { +define void @denormal_fpenv__dynamic_dynamic() denormal_fpenv(dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__ieee_ieee() #55 { +define void @denormal_fpenv_float__ieee_ieee() denormal_fpenv(float: ieee|ieee) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__ieee_preservesign() #71 { +define void @denormal_fpenv_float__ieee_preservesign() denormal_fpenv(float: ieee|preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__ieee_positivezero() #72 { +define void @denormal_fpenv_float__ieee_positivezero() denormal_fpenv(float: ieee|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__ieee_dynamic() #73 { +define void @denormal_fpenv_float__ieee_dynamic() denormal_fpenv(float: ieee|dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__preservesign_ieee() #74 { +define void @denormal_fpenv_float__preservesign_ieee() denormal_fpenv(float: preservesign|ieee) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__preservesign_preservesign() #75 { +define void @denormal_fpenv_float__preservesign_preservesign() denormal_fpenv(float: preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__preservesign_positivezero() #76 { +define void @denormal_fpenv_float__preservesign_positivezero() denormal_fpenv(float: preservesign|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__preservesign_dynamic() #77 { +define void @denormal_fpenv_float__preservesign_dynamic() denormal_fpenv(float: preservesign|dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__positivezero_ieee() #78 { +define void @denormal_fpenv_float__positivezero_ieee() denormal_fpenv(float: positivezero|ieee) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__positivezero_preservesign() #79 { +define void @denormal_fpenv_float__positivezero_preservesign() denormal_fpenv(float: positivezero|preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__positivezero_positivezero() #80 { +define void @denormal_fpenv_float__positivezero_positivezero() denormal_fpenv(float: positivezero|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__positivezero_dynamix() #81 { +define void @denormal_fpenv_float__positivezero_dynamix() denormal_fpenv(float: positivezero|dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__dynamic_ieee() #82 { +define void @denormal_fpenv_float__dynamic_ieee() denormal_fpenv(float: dynamic|ieee) { + ret void +} + +; Function Attrs: denormal_fpenv(float: dynamic|preservesign) +define void @denormal_fpenv_float__dynamic_preservesign() denormal_fpenv(float: dynamic|preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__dynamic_positivezero() #84 { +define void @denormal_fpenv_float__dynamic_positivezero() denormal_fpenv(float: dynamic|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv_float__dynamic_dynamic() #85 { +define void @denormal_fpenv_float__dynamic_dynamic() denormal_fpenv(float: dynamic|dynamic) { + ret void +} +; CHECK: define void @denormal_fpenv__ieee_ieee_float_ieee_ieee() #55 { +define void @denormal_fpenv__ieee_ieee_float_ieee_ieee() denormal_fpenv(ieee|ieee, float: ieee|ieee) { + ret void +} + +; CHECK: define void @denormal_fpenv__ieee_ieee_float_preservesign_preservesign() #75 { +define void @denormal_fpenv__ieee_ieee_float_preservesign_preservesign() denormal_fpenv(ieee|ieee, float: preservesign|preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv__preservesign_preservesign_float_preservesign_preservesign() #60 { +define void @denormal_fpenv__preservesign_preservesign_float_preservesign_preservesign() denormal_fpenv(preservesign|preservesign, float: preservesign|preservesign) { + ret void +} + +; CHECK: define void @denormal_fpenv__positivezero_positivezero_float_positivezero_positivezero() #65 { +define void @denormal_fpenv__positivezero_positivezero_float_positivezero_positivezero() denormal_fpenv(positivezero|positivezero, float: positivezero|positivezero) { + ret void +} + +; CHECK: define void @denormal_fpenv__dynamic_dynamic_float_dynamic_dynamic() #70 { +define void @denormal_fpenv__dynamic_dynamic_float_dynamic_dynamic() denormal_fpenv(dynamic|dynamic, float: dynamic|dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv__ieee_ieee_float_dynamic_dynamic() #85 { +define void @denormal_fpenv__ieee_ieee_float_dynamic_dynamic() denormal_fpenv(ieee|ieee, float: dynamic|dynamic) { + ret void +} + +; CHECK: define void @denormal_fpenv__preservesign_preservesign_float_dynamic_dynamic() #86 { +define void @denormal_fpenv__preservesign_preservesign_float_dynamic_dynamic() denormal_fpenv(preservesign|preservesign, float: dynamic|dynamic) { + ret void +} + ; CHECK: attributes #0 = { alignstack=4 } ; CHECK: attributes #1 = { alignstack=8 } ; CHECK: attributes #2 = { alwaysinline } @@ -2292,7 +2486,39 @@ define float @nofpclass_callsites(float %arg, { float } %arg1) { ; CHECK: attributes #52 = { sanitize_realtime } ; CHECK: attributes #53 = { sanitize_realtime_blocking } ; CHECK: attributes #54 = { sanitize_alloc_token } -; CHECK: attributes #55 = { builtin } +; CHECK: attributes #55 = { denormal_fpenv(ieee) } +; CHECK: attributes #56 = { denormal_fpenv(ieee|preservesign) } +; CHECK: attributes #57 = { denormal_fpenv(ieee|positivezero) } +; CHECK: attributes #58 = { denormal_fpenv(ieee|dynamic) } +; CHECK: attributes #59 = { denormal_fpenv(preservesign|ieee) } +; CHECK: attributes #60 = { denormal_fpenv(preservesign) } +; CHECK: attributes #61 = { denormal_fpenv(preservesign|positivezero) } +; CHECK: attributes #62 = { denormal_fpenv(preservesign|dynamic) } +; CHECK: attributes #63 = { denormal_fpenv(positivezero|ieee) } +; CHECK: attributes #64 = { denormal_fpenv(positivezero|preservesign) } +; CHECK: attributes #65 = { denormal_fpenv(positivezero) } +; CHECK: attributes #66 = { denormal_fpenv(positivezero|dynamic) } +; CHECK: attributes #67 = { denormal_fpenv(dynamic|ieee) } +; CHECK: attributes #68 = { denormal_fpenv(dynamic|preservesign) } +; CHECK: attributes #69 = { denormal_fpenv(dynamic|positivezero) } +; CHECK: attributes #70 = { denormal_fpenv(dynamic) } +; CHECK: attributes #71 = { denormal_fpenv(float: ieee|preservesign) } +; CHECK: attributes #72 = { denormal_fpenv(float: ieee|positivezero) } +; CHECK: attributes #73 = { denormal_fpenv(float: ieee|dynamic) } +; CHECK: attributes #74 = { denormal_fpenv(float: preservesign|ieee) } +; CHECK: attributes #75 = { denormal_fpenv(float: preservesign) } +; CHECK: attributes #76 = { denormal_fpenv(float: preservesign|positivezero) } +; CHECK: attributes #77 = { denormal_fpenv(float: preservesign|dynamic) } +; CHECK: attributes #78 = { denormal_fpenv(float: positivezero|ieee) } +; CHECK: attributes #79 = { denormal_fpenv(float: positivezero|preservesign) } +; CHECK: attributes #80 = { denormal_fpenv(float: positivezero) } +; CHECK: attributes #81 = { denormal_fpenv(float: positivezero|dynamic) } +; CHECK: attributes #82 = { denormal_fpenv(float: dynamic|ieee) } +; CHECK: attributes #83 = { denormal_fpenv(float: dynamic|preservesign) } +; CHECK: attributes #84 = { denormal_fpenv(float: dynamic|positivezero) } +; CHECK: attributes #85 = { denormal_fpenv(float: dynamic) } +; CHECK: attributes #86 = { denormal_fpenv(preservesign, float: dynamic) } +; CHECK: attributes #87 = { builtin } ;; Metadata diff --git a/llvm/test/Bitcode/upgrade-cu-locals.ll b/llvm/test/Bitcode/upgrade-cu-locals.ll index 9a590f0fc0774..da175f5f91ced 100644 --- a/llvm/test/Bitcode/upgrade-cu-locals.ll +++ b/llvm/test/Bitcode/upgrade-cu-locals.ll @@ -1,7 +1,7 @@ -; Test moving of local imports from DICompileUnit's 'imports' to DISubprogram's 'retainedNodes' -; ; RUN: llvm-dis -o - %s.bc | FileCheck %s +; Test moving of local imports/enums from DICompileUnit to DISubprogram's 'retainedNodes' + %"struct.ns::t1" = type { i8 } declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 @@ -31,31 +31,36 @@ attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memo ; CHECK: !4 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t4" ; CHECK: !5 = !{} -; CHECK: !6 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !7, producer: "clang version 14.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, imports: !5, nameTableKind: GNU) - -; CHECK: !14 = distinct !DISubprogram(name: "main", scope: !7, file: !7, line: 2, type: !15, scopeLine: 2, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !6, retainedNodes: !18) -; CHECK: !18 = !{!19} -; CHECK: !19 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !20, entity: !23, -; CHECK: !20 = !DILexicalBlock(scope: !21, file: !7, line: 7, column: 35) -; CHECK: !21 = !DILexicalBlock(scope: !22, file: !7, line: 7, column: 35) -; CHECK: !22 = !DILexicalBlock(scope: !14, file: !7, line: 7, column: 35) -; CHECK: !23 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t5", scope: !20, - -; CHECK: !25 = distinct !DISubprogram(name: "f1", linkageName: "_Z2f1v", scope: !1, file: !1, line: 3, type: !26, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !28) -; CHECK: !28 = !{!29, !32, !34} -; CHECK: !29 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !25, entity: !30, -; CHECK: !30 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t1", -; CHECK: !32 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !25, entity: !33, -; CHECK: !33 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t2", -; CHECK: !34 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !25, entity: !35, -; CHECK: !35 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t3", - -; CHECK: !40 = distinct !DISubprogram(name: "main2", scope: !7, file: !7, line: 10, type: !15, scopeLine: 10, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !6, retainedNodes: !41) -; CHECK: !41 = !{!42, !44} -; CHECK: !42 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !40, entity: !43, -; CHECK: !43 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t6" -; CHECK: !44 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !40, entity: !45, -; CHECK: !45 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t7", +; CHECK: !6 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !7, producer: "clang version 14.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !8, imports: !5, nameTableKind: GNU) +; CHECK: !7 = !DIFile(filename: "b.cpp" +; CHECK: !8 = !{!9} +; CHECK: !9 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Enum2", scope: !6, file: !7, line: 4, size: 8, align: 8, elements: !5) + +; CHECK: !16 = distinct !DISubprogram(name: "main", scope: !7, file: !7, line: 2, type: !17, scopeLine: 2, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !6, retainedNodes: !20) +; CHECK: !20 = !{!21} +; CHECK: !21 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !22, entity: !25, +; CHECK: !22 = !DILexicalBlock(scope: !23, file: !7, line: 7, column: 35) +; CHECK: !23 = !DILexicalBlock(scope: !24, file: !7, line: 7, column: 35) +; CHECK: !24 = !DILexicalBlock(scope: !16, file: !7, line: 7, column: 35) +; CHECK: !25 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t5", scope: !22, + +; CHECK: !27 = distinct !DISubprogram(name: "f1", linkageName: "_Z2f1v", scope: !1, file: !1, line: 3, type: !28, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !30) +; CHECK: !30 = !{!31, !34, !36} +; CHECK: !31 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !27, entity: !32, +; CHECK: !32 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t1", +; CHECK: !34 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !27, entity: !35, +; CHECK: !35 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t2", +; CHECK: !36 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !27, entity: !37, +; CHECK: !37 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t3", + +; CHECK: !42 = distinct !DISubprogram(name: "main2", scope: !7, file: !7, line: 10, type: !17, scopeLine: 10, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !6, retainedNodes: !43) +; CHECK: !43 = !{!44, !46, !48, !49} +; CHECK: !44 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !42, entity: !45, +; CHECK: !45 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t6" +; CHECK: !46 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !42, entity: !47, +; CHECK: !47 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t7", +; CHECK: !48 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Enum", scope: !42, file: !7, line: 3, size: 8, align: 8, elements: !5) +; CHECK: !49 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Enum3", scope: !42, file: !7, line: 5, size: 8, align: 8, elements: !5) !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 14.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, imports: !2, nameTableKind: GNU) @@ -82,7 +87,7 @@ attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memo ; Leave t4 in CU !14 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !0, entity: !15, file: !1, line: 3) !15 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "t4", scope: !0, file: !1, line: 1, size: 8, flags: DIFlagTypePassByValue, elements: !7, identifier: "_ZTSN2ns2t4E") -!16 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !17, producer: "clang version 14.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, imports: !18, nameTableKind: GNU) +!16 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !17, producer: "clang version 14.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, imports: !18, enums: !50, nameTableKind: GNU) !17 = !DIFile(filename: "b.cpp", directory: "/") !18 = !{!19, !28, !31} @@ -116,3 +121,12 @@ attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memo !41 = distinct !DILocation(line: 3, column: 3, scope: !23) !42 = !DILocation(line: 3, column: 41, scope: !4, inlinedAt: !41) !43 = !DILocation(line: 4, column: 1, scope: !23) + +!50 = !{!51, !52, !53} +; Move to main2 +!51 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Enum", scope: !29, file: !17, line: 3, size: 8, align: 8, elements: !7) +; Leave in b.cpp's CU +!52 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Enum2", scope: !16, file: !17, line: 4, size: 8, align: 8, elements: !7) +; Move to main2 +!53 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "Enum3", scope: !29, file: !17, line: 5, size: 8, align: 8, elements: !7) + diff --git a/llvm/test/Bitcode/upgrade-cu-locals.ll.bc b/llvm/test/Bitcode/upgrade-cu-locals.ll.bc index 9d0ea8fd9a370..f73d05668af5b 100644 Binary files a/llvm/test/Bitcode/upgrade-cu-locals.ll.bc and b/llvm/test/Bitcode/upgrade-cu-locals.ll.bc differ diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir b/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir index 12e362e7b7fd2..b2bb44e551f81 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/166563.mir @@ -16,7 +16,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 457873110 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK-NEXT: TBNZW [[MOVi32imm1]], 0, %bb.2 ; CHECK-NEXT: B %bb.1 @@ -132,7 +132,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 457873110 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK-NEXT: TBNZW [[MOVi32imm1]], 0, %bb.2 ; CHECK-NEXT: B %bb.1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir index 99bb62b117080..2771cead06da4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir @@ -49,10 +49,10 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: [[BFMWri:%[0-9]+]]:gpr32 = BFMWri [[DEF]], [[COPY2]], 0, 15 - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG1]] ; CHECK-NEXT: [[BFMWri1:%[0-9]+]]:gpr32 = BFMWri [[BFMWri]], [[COPY3]], 16, 15 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64sp = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/inline-asm.ll index 6da0fcf4dd07c..15ad4b14f496d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/inline-asm.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/inline-asm.ll @@ -1,10 +1,78 @@ -; RUN: llc -mtriple=aarch64 -global-isel %s -o - | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=aarch64 -global-isel -O0 %s -o - | FileCheck %s --check-prefixes=CHECK,O0 +; RUN: llc -mtriple=aarch64 -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,O2 -; CHECK-LABEL: test_asm: -; CHECK: {{APP|InlineAsm Start}} -; CHECK: mov x0, {{x[0-9]+}} -; CHECK: {{NO_APP|InlineAsm End}} define void @test_asm() { +; O0-LABEL: test_asm: +; O0: // %bb.0: +; O0-NEXT: mov w8, #42 // =0x2a +; O0-NEXT: // kill: def $x8 killed $w8 +; O0-NEXT: //APP +; O0-NEXT: mov x0, x8 +; O0-NEXT: //NO_APP +; O0-NEXT: ret +; +; O2-LABEL: test_asm: +; O2: // %bb.0: +; O2-NEXT: mov w8, #42 // =0x2a +; O2-NEXT: //APP +; O2-NEXT: mov x0, x8 +; O2-NEXT: //NO_APP +; O2-NEXT: ret call void asm sideeffect "mov x0, $0", "r"(i64 42) ret void } + +; regression test for https://github.com/llvm/llvm-project/issues/79822 +define i16 @test_16bit_reg(i16 %x) { +; O0-LABEL: test_16bit_reg: +; O0: // %bb.0: +; O0-NEXT: fmov s0, w0 +; O0-NEXT: // kill: def $h0 killed $h0 killed $s0 +; O0-NEXT: //APP +; O0-NEXT: nop +; O0-NEXT: //NO_APP +; O0-NEXT: // kill: def $s0 killed $h0 +; O0-NEXT: fmov w0, s0 +; O0-NEXT: ret +; +; O2-LABEL: test_16bit_reg: +; O2: // %bb.0: +; O2-NEXT: fmov s0, w0 +; O2-NEXT: // kill: def $h0 killed $h0 killed $s0 +; O2-NEXT: //APP +; O2-NEXT: nop +; O2-NEXT: //NO_APP +; O2-NEXT: // kill: def $h0 killed $h0 def $s0 +; O2-NEXT: fmov w0, s0 +; O2-NEXT: ret + %ret = call i16 asm "nop", "=&{h0},0"(i16 %x) + ret i16 %ret +} + + +define i32 @test_32bit_reg(i32 %x) { +; CHECK-LABEL: test_32bit_reg: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: //APP +; CHECK-NEXT: nop +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %ret = call i32 asm "nop", "=&{s0},0"(i32 %x) + ret i32 %ret +} + +define i64 @test_64bit_reg(i64 %x) { +; CHECK-LABEL: test_64bit_reg: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov d0, x0 +; CHECK-NEXT: //APP +; CHECK-NEXT: nop +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %ret = call i64 asm "nop", "=&{d0},0"(i64 %x) + ret i64 %ret +} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dynamic-alloca-scalable.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dynamic-alloca-scalable.ll new file mode 100644 index 0000000000000..04bf589a17505 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-dynamic-alloca-scalable.ll @@ -0,0 +1,14 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -mtriple=aarch64 -mattr=+sve -global-isel -aarch64-enable-gisel-sve %s -o - -stop-after=irtranslator | FileCheck %s +; Tests for scalable vector allocas in GlobalISel + +; Test basic scalable vector alloca (single allocation) +define ptr @test_single_scalable_alloca() { + ; CHECK-LABEL: name: test_single_scalable_alloca + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.local0 + ; CHECK-NEXT: $x0 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: RET_ReallyLR implicit $x0 + %local0 = alloca + ret ptr %local0 +} \ No newline at end of file diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll index 2a490bc7d3d1c..74c60a1a3ecbd 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll @@ -269,8 +269,9 @@ define i16 @test_anyext_input_with_matching_constraint() { define i64 @test_input_with_matching_constraint_to_physical_register() { ; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register ; CHECK: bb.1 (%ir-block.0): - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[C]](tied-def 3)(s64) + ; CHECK-NEXT: %0:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: %1:gpr64arg = COPY %0(s64) + ; CHECK-NEXT: INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, %1(tied-def 3) ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x2 ; CHECK-NEXT: $x0 = COPY [[COPY]](s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir new file mode 100644 index 0000000000000..4bb2b3d5bc205 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir @@ -0,0 +1,195 @@ +# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=aarch64 -passes="print" -filetype=null %s 2>&1 | FileCheck %s + +--- +name: CTLSConst8AmbigousMaxSignbitNum +body: | + bb.1: + ; NOTE: Currently we do not estimate max sign bits in KnownBits, + ; so while we could get more accurate here, this is currently + ; not possible. + ; CHECK-LABEL: name: @CTLSConst8AmbigousMaxSignbitNum + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00110000 SignBits:2 + ; CHECK-NEXT: %2:_ KnownBits:00001000 SignBits:4 + ; CHECK-NEXT: %3:_ KnownBits:00??0000 SignBits:2 + ; CHECK-NEXT: %4:_ KnownBits:00??1000 SignBits:2 + ; CHECK-NEXT: %5:_ KnownBits:00000??? SignBits:5 + %0:_(s8) = COPY $b0 + %1:_(s8) = G_CONSTANT i8 48 + %2:_(s8) = G_CONSTANT i8 8 + %3:_(s8) = G_AND %0, %1 + %4:_(s8) = G_OR %3, %2 + %5:_(s8) = G_CTLS %4 +... + +--- +name: CTLSNoKnown8 +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSNoKnown8 + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:0000000000000??? SignBits:13 + %0:_(s8) = COPY $b0 + %1:_(s16) = G_CTLS %0 +... + +--- +name: CTLSNoKnown16 +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSNoKnown16 + ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:000000000000???? SignBits:12 + %0:_(s16) = COPY $h0 + %1:_(s16) = G_CTLS %0 +... + +--- +name: CTLSNoKnown32 +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSNoKnown32 + ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00000000000????? SignBits:11 + %0:_(s32) = COPY $s0 + %1:_(s16) = G_CTLS %0 +... + + +--- +name: CTLSHalfKnown8 +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSHalfKnown8 + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5 + ; CHECK-NEXT: %2:_ KnownBits:00000?00 SignBits:5 + ; CHECK-NEXT: %3:_ KnownBits:000001?? SignBits:5 + %0:_(s8) = COPY $b0 + %1:_(s8) = G_CONSTANT i8 4 + %2:_(s8) = G_AND %0, %1 + %3:_(s8) = G_CTLS %2 +... + +--- +name: CTLSHalfKnown16 +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSHalfKnown16 + ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:0000000001000000 SignBits:9 + ; CHECK-NEXT: %2:_ KnownBits:000000000?000000 SignBits:9 + ; CHECK-NEXT: %3:_ KnownBits:0000000000001??? SignBits:12 + %0:_(s16) = COPY $h0 + %1:_(s16) = G_CONSTANT i16 64 + %2:_(s16) = G_AND %0, %1 + %3:_(s16) = G_CTLS %2 +... + +--- +name: CTLSHalfConst8Zero +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSHalfConst8Zero + ; CHECK-NEXT: %0:_ KnownBits:00000000 SignBits:8 + ; CHECK-NEXT: %1:_ KnownBits:00000111 SignBits:5 + %0:_(s8) = G_CONSTANT i8 0 + %1:_(s8) = G_CTLS %0 +... + +--- +name: CTLSHalfConst16Zero +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSHalfConst16Zero + ; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16 + ; CHECK-NEXT: %1:_ KnownBits:0000000000001111 SignBits:12 + %0:_(s16) = G_CONSTANT i16 0 + %1:_(s16) = G_CTLS %0 +... + +--- +name: VectorCTLSConst16Zero +body: | + bb.1: + ; CHECK-LABEL: name: @VectorCTLSConst16Zero + ; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16 + ; CHECK-NEXT: %1:_ KnownBits:0000000000000000 SignBits:16 + ; CHECK-NEXT: %2:_ KnownBits:0000000000001111 SignBits:12 + %0:_(s16) = G_CONSTANT i16 0 + %1:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0 + %3:_(<4 x s16>) = G_CTLS %1 +... + +--- +name: VectorCTLSNoneKnown +body: | + bb.1: + ; CHECK-LABEL: name: @VectorCTLSNoneKnown + ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:0000000000001000 SignBits:12 + ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:9 + ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %5:_ KnownBits:000000000000???? SignBits:12 + %0:_(s16) = COPY $h0 + %1:_(s16) = G_CONSTANT i16 8 + %2:_(s16) = G_ASHR %0, %1 + %3:_(s16) = COPY $h1 + %4:_(<4 x s16>) = G_BUILD_VECTOR %2, %3, %2, %3 + %5:_(<4 x s16>) = G_CTLS %4 +... + +--- +name: VectorCTLSHighBitKnown +body: | + bb.1: + ; CHECK-LABEL: name: @VectorCTLSHighBitKnown + ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:0000000000001000 SignBits:12 + ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:9 + ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %4:_ KnownBits:0000000000001010 SignBits:12 + ; CHECK-NEXT: %5:_ KnownBits:000000000000???? SignBits:12 + ; CHECK-NEXT: %6:_ KnownBits:???????????????? SignBits:9 + ; CHECK-NEXT: %7:_ KnownBits:0000000000001??? SignBits:12 + %0:_(s16) = COPY $h0 + %1:_(s16) = G_CONSTANT i16 8 + %2:_(s16) = G_ASHR %0, %1 + %3:_(s16) = COPY $h1 + %4:_(s16) = G_CONSTANT i16 10 + %5:_(s16) = G_ASHR %4, %5 + %6:_(<4 x s16>) = G_BUILD_VECTOR %2, %5, %2, %4 + %7:_(<4 x s16>) = G_CTLS %6 +... + +--- +name: CTLSLargeEnough +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSLargeEnough + ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000010000 SignBits:27 + ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:17 + ; CHECK-NEXT: %3:_ KnownBits:0000000000000000000000000001???? SignBits:27 + %0:_(s32) = COPY $s0 + %1:_(s32) = G_CONSTANT i32 16 + %2:_(s32) = G_ASHR %0, %1 + %3:_(s32) = G_CTLS %2 +... + +--- +name: CTLSTooSmallToTrigger +body: | + bb.1: + ; CHECK-LABEL: name: @CTLSTooSmallToTrigger + ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000000000001111 SignBits:28 + ; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:16 + ; CHECK-NEXT: %3:_ KnownBits:000000000000000000000000000????? SignBits:27 + %0:_(s32) = COPY $s0 + %1:_(s32) = G_CONSTANT i32 15 + %2:_(s32) = G_ASHR %0, %1 + %3:_(s32) = G_CTLS %2 +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir new file mode 100644 index 0000000000000..d468c84ce899f --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-rotl-rotr.mir @@ -0,0 +1,270 @@ +# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple aarch64 -passes="print" %s -o - 2>&1 | FileCheck %s + +--- +name: Cst +body: | + bb.1: + ; CHECK-LABEL: name: @Cst + ; CHECK-NEXT: %0:_ KnownBits:11100010 SignBits:3 + ; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6 + ; CHECK-NEXT: %2:_ KnownBits:10111000 SignBits:1 + %0:_(s8) = G_CONSTANT i8 226 + %1:_(s8) = G_CONSTANT i8 2 + %2:_(s8) = G_ROTR %0, %1 +... +--- +name: CstBig +body: | + bb.1: + ; CHECK-LABEL: name: @CstBig + ; CHECK-NEXT: %0:_ KnownBits:11111001 SignBits:5 + ; CHECK-NEXT: %1:_ KnownBits:00000110 SignBits:5 + ; CHECK-NEXT: %2:_ KnownBits:11100111 SignBits:3 + %0:_(s8) = G_CONSTANT i8 249 + %1:_(s8) = G_CONSTANT i8 6 + %2:_(s8) = G_ROTR %0, %1 +... +--- +name: CstSext +body: | + bb.1: + ; CHECK-LABEL: name: @CstSext + ; CHECK-NEXT: %0:_ KnownBits:10000001 SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5 + ; CHECK-NEXT: %2:_ KnownBits:11111000 SignBits:5 + ; CHECK-NEXT: %3:_ KnownBits:00000100 SignBits:5 + ; CHECK-NEXT: %4:_ KnownBits:10001111 SignBits:1 + %0:_(s8) = G_CONSTANT i8 129 + %1:_(s8) = G_CONSTANT i8 4 + %2:_(s8) = G_ASHR %0, %1 + %3:_(s8) = G_CONSTANT i8 4 + %4:_(s8) = G_ROTR %2, %3 +... +--- +name: CstSextBig +body: | + bb.1: + ; CHECK-LABEL: name: @CstSextBig + ; CHECK-NEXT: %0:_ KnownBits:10000001 SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5 + ; CHECK-NEXT: %2:_ KnownBits:11111000 SignBits:5 + ; CHECK-NEXT: %3:_ KnownBits:00000110 SignBits:5 + ; CHECK-NEXT: %4:_ KnownBits:11100011 SignBits:3 + %0:_(s8) = G_CONSTANT i8 129 + %1:_(s8) = G_CONSTANT i8 4 + %2:_(s8) = G_ASHR %0, %1 + %3:_(s8) = G_CONSTANT i8 6 + %4:_(s8) = G_ROTR %2, %3 +... +--- +name: ScalarVar +body: | + bb.1: + ; CHECK-LABEL: name: @ScalarVar + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1 + %0:_(s8) = COPY $b0 + %1:_(s8) = COPY $b1 + %2:_(s8) = G_ROTR %0, %1 +... +--- +name: ScalarCst +body: | + bb.1: + ; CHECK-LABEL: name: @ScalarCst + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6 + ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1 + %0:_(s8) = COPY $b0 + %1:_(s8) = G_CONSTANT i8 3 + %2:_(s8) = G_ROTR %0, %1 +... +--- +name: VectorVar +body: | + bb.1: + ; CHECK-LABEL: name: @VectorVar + ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1 + %0:_(<4 x s16>) = COPY $d0 + %1:_(<4 x s16>) = COPY $d1 + %2:_(<4 x s16>) = G_ROTR %0, %1 +... +--- +name: VectorSimple +body: | + bb.1: + ; CHECK-LABEL: name: @VectorSimple + ; CHECK-NEXT: %0:_ KnownBits:0000000000010011 SignBits:11 + ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %2:_ KnownBits:0000000000010011 SignBits:11 + ; CHECK-NEXT: %3:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %4:_ KnownBits:0110000000000010 SignBits:1 + %0:_(s16) = G_CONSTANT i16 19 + %1:_(s16) = G_CONSTANT i16 3 + %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %0, %0, %0 + %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1 + %4:_(<4 x s16>) = G_ROTR %2, %3 +... +--- +name: VectorCst +body: | + bb.1: + ; CHECK-LABEL: name: @VectorCst + ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1 + %0:_(<4 x s16>) = COPY $d0 + %1:_(s16) = G_CONSTANT i16 3 + %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1 + %3:_(<4 x s16>) = G_ROTR %0, %2 +... +--- +name: VectorCst36 +body: | + bb.1: + ; CHECK-LABEL: name: @VectorCst36 + ; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13 + ; CHECK-NEXT: %2:_ KnownBits:0000000000000?1? SignBits:13 + ; CHECK-NEXT: %3:_ KnownBits:0000000000000?1? SignBits:13 + ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1 + %0:_(s16) = G_CONSTANT i16 3 + %1:_(s16) = G_CONSTANT i16 6 + %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0 + %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0 + %4:_(<4 x s16>) = G_ROTR %2, %3 +... + +--- +name: VectorCst3unknown +body: | + bb.1: + ; CHECK-LABEL: name: @VectorCst3unknown + ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1 + ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1 + %0:_(<4 x s16>) = COPY $d0 + %1:_(s16) = COPY $h0 + %2:_(s16) = G_CONSTANT i16 3 + %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1 + %4:_(<4 x s16>) = G_ROTR %0, %3 +... +--- +name: VectorSext +body: | + bb.1: + ; CHECK-LABEL: name: @VectorSext + ; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3 + ; CHECK-NEXT: %1:_ KnownBits:1111111111101110 SignBits:11 + ; CHECK-NEXT: %2:_ KnownBits:1111111111101110 SignBits:11 + ; CHECK-NEXT: %3:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %4:_ KnownBits:0000000000000110 SignBits:13 + ; CHECK-NEXT: %5:_ KnownBits:0000000000000?1? SignBits:13 + ; CHECK-NEXT: %6:_ KnownBits:???????????????? SignBits:1 + %0:_(s8) = G_CONSTANT i8 238 + %1:_(s16) = G_SEXT %0(s8) + %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1 + %3:_(s16) = G_CONSTANT i16 3 + %4:_(s16) = G_CONSTANT i16 6 + %5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3 + %6:_(<4 x s16>) = G_ROTR %2, %5 +... +--- +name: VectorSextBig +body: | + bb.1: + ; CHECK-LABEL: name: @VectorSextBig + ; CHECK-NEXT: %0:_ KnownBits:11101110 SignBits:3 + ; CHECK-NEXT: %1:_ KnownBits:1111111111101110 SignBits:11 + ; CHECK-NEXT: %2:_ KnownBits:1111111111101110 SignBits:11 + ; CHECK-NEXT: %3:_ KnownBits:0000000000001000 SignBits:12 + ; CHECK-NEXT: %4:_ KnownBits:0000000000001001 SignBits:12 + ; CHECK-NEXT: %5:_ KnownBits:000000000000100? SignBits:12 + ; CHECK-NEXT: %6:_ KnownBits:???????????????? SignBits:1 + %0:_(s8) = G_CONSTANT i8 238 + %1:_(s16) = G_SEXT %0(s8) + %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1 + %3:_(s16) = G_CONSTANT i16 8 + %4:_(s16) = G_CONSTANT i16 9 + %5:_(<4 x s16>) = G_BUILD_VECTOR %3, %4, %4, %3 + %6:_(<4 x s16>) = G_ROTR %2, %5 +... +--- +name: ROTRless +body: | + bb.1: + ; CHECK-LABEL: name: @ROTRless + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9 + ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1 + %0:_(s8) = COPY $b0 + %1:_(s16) = G_SEXT %0(s8) + %2:_(s16) = G_CONSTANT i16 3 + %3:_(s16) = G_ROTR %1, %2 +... +--- +name: ROTReq +body: | + bb.1: + ; CHECK-LABEL: name: @ROTReq + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9 + ; CHECK-NEXT: %2:_ KnownBits:0000000000001000 SignBits:12 + ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1 + %0:_(s8) = COPY $b0 + %1:_(s16) = G_SEXT %0(s8) + %2:_(s16) = G_CONSTANT i16 8 + %3:_(s16) = G_ROTR %1, %2 +... +--- +name: ROTRmore +body: | + bb.1: + ; CHECK-LABEL: name: @ROTRmore + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9 + ; CHECK-NEXT: %2:_ KnownBits:0000000000001101 SignBits:12 + ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1 + %0:_(s8) = COPY $b0 + %1:_(s16) = G_SEXT %0(s8) + %2:_(s16) = G_CONSTANT i16 13 + %3:_(s16) = G_ROTR %1, %2 +... +--- +name: SignBitsThroughZext +body: | + bb.1: + ; CHECK-LABEL: name: @SignBitsThroughZext + ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 + ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14 + ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:4 + ; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8 + ; CHECK-NEXT: %4:_ KnownBits:0000000000001000 SignBits:12 + ; CHECK-NEXT: %5:_ KnownBits:????????00000000 SignBits:1 + %0:_(s8) = COPY $b0 + %1:_(s16) = G_CONSTANT i16 3 + %2:_(s8) = G_ASHR %0, %1 + %3:_(s16) = G_ZEXT %2 + %4:_(s16) = G_CONSTANT i16 8 + %5:_(s16) = G_ROTR %3, %4 +... +--- +name: ROTRCanonicalize +body: | + bb.1: + ; CHECK-LABEL: name: @ROTRCanonicalize + ; CHECK-NEXT: %0:_ KnownBits:11100000 SignBits:3 + ; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6 + ; CHECK-NEXT: %2:_ KnownBits:10000011 SignBits:1 + %0:_(s8) = G_CONSTANT i8 224 + %1:_(s8) = G_CONSTANT i8 2 + %2:_(s8) = G_ROTL %0, %1 +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir index dc2e1c5dc28d4..2aee1bbc8ddd4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir @@ -139,7 +139,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103 ; CHECK-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) ; CHECK-NEXT: RET_ReallyLR implicit [[LDRHHroX]] @@ -393,7 +393,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 7 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load (s64) from %ir.addr) @@ -427,7 +427,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[SUBREG_TO_REG]], [[COPY]], $xzr ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1 ; CHECK-NEXT: [[LDRDroX:%[0-9]+]]:fpr64 = LDRDroX [[COPY1]], [[MADDXrrr]], 0, 0 :: (load (s64) from %ir.addr) @@ -496,7 +496,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103 ; CHECK-NEXT: [[LDRXroX:%[0-9]+]]:gpr64 = LDRXroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s64)) ; CHECK-NEXT: [[LDRXroX1:%[0-9]+]]:gpr64 = LDRXroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s64)) @@ -578,7 +578,7 @@ body: | ; CHECK-FAST-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-FAST-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-FAST-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-FAST-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103 ; CHECK-FAST-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) ; CHECK-FAST-NEXT: [[LDRHHroX1:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) @@ -592,7 +592,7 @@ body: | ; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-SLOW-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-SLOW-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY [[COPY]] @@ -636,7 +636,7 @@ body: | ; CHECK-FAST-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-FAST-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-FAST-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-FAST-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-FAST-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 4103 ; CHECK-FAST-NEXT: [[LDRHHroX:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) ; CHECK-FAST-NEXT: [[LDRHHroX1:%[0-9]+]]:gpr32 = LDRHHroX [[COPY]], [[ANDXri]], 0, 1 :: (load (s16)) @@ -650,7 +650,7 @@ body: | ; CHECK-SLOW-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-SLOW-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 9, 31 ; CHECK-SLOW-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[UBFMWri]], 0 - ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-SLOW-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-SLOW-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-SLOW-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]] ; CHECK-SLOW-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY [[COPY]] @@ -695,7 +695,7 @@ body: | ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY2]], [[UBFMXri]] ; CHECK-NEXT: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[COPY1]], [[COPY]], 0, 1 :: (load (s32) from %ir.addr) ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[LDRWroX]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64common = ADDXri [[UBFMXri]], 2, 0 ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr [[SUBREG_TO_REG]], [[ADDXri]] ; CHECK-NEXT: [[ADDXrr2:%[0-9]+]]:gpr64 = ADDXrr [[ADDXrr]], [[ADDXrr1]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir index 85c2b61aa6740..9283adfaf20df 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir @@ -80,7 +80,7 @@ body: | ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $h0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG $h0, %subreg.hsub ; CHECK-NEXT: %copy:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %copy ; CHECK-NEXT: TBNZW [[COPY]], 3, %bb.1 @@ -117,7 +117,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %copy:gpr32 = COPY $w0 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %zext.sub_32 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; CHECK-NEXT: TBNZW [[COPY1]], 3, %bb.1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir index 64d09ea682e4a..205064a851618 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir @@ -136,7 +136,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK-NEXT: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[COPY]] ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ORNWrr]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: TBNZX [[SUBREG_TO_REG]], 63, %bb.1 ; CHECK-NEXT: B %bb.0 ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir index a422f60aacc0f..d083e49e1e596 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir @@ -163,7 +163,7 @@ body: | ; SELECT-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY %reg.sub_32 ; SELECT-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]] ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234567 - ; SELECT-NEXT: %cmp_rhs:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; SELECT-NEXT: %cmp_rhs:gpr64sp = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; SELECT-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %cmp_rhs, [[COPY1]], 32, implicit-def $nzcv ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; SELECT-NEXT: $w0 = COPY %cmp @@ -481,7 +481,7 @@ body: | ; SELECT-NEXT: %cmp_rhs:gpr64 = COPY $x1 ; SELECT-NEXT: %shl_lhs:gpr64 = COPY $x0 ; SELECT-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 64 - ; SELECT-NEXT: %too_large:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; SELECT-NEXT: %too_large:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; SELECT-NEXT: %cmp_lhs:gpr64 = LSLVXr %shl_lhs, %too_large ; SELECT-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; SELECT-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir index e53380c18beb1..5721f235de460 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir @@ -30,7 +30,7 @@ body: | ; CHECK-NEXT: FCMPSrr [[COPY3]], [[COPY4]], implicit-def $nzcv, implicit $fpcr ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv ; CHECK-NEXT: [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY1]], 1, 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[SUBWri]], %subreg.sub_32 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[DEF]] ; CHECK-NEXT: FCMPSrr [[COPY5]], [[COPY4]], implicit-def $nzcv, implicit $fpcr ; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv @@ -64,7 +64,7 @@ body: | FCMPSrr %29, %4, implicit-def $nzcv, implicit $fpcr %28:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv %7:gpr32 = SUBSWri %1, 1, 0, implicit-def $nzcv - %8:gpr64 = SUBREG_TO_REG 0, %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG %7, %subreg.sub_32 %30:fpr32 = COPY %3 FCMPSrr %30, %4, implicit-def $nzcv, implicit $fpcr %27:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir index 34dbad5a94977..7620c729d580e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir @@ -32,7 +32,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2 ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]], implicit $fpcr - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[FCVTHSr]], %subreg.hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `ptr undef`) ; CHECK-NEXT: B %bb.2 @@ -163,7 +163,7 @@ body: | ; CHECK-NEXT: %gp_phi1:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2 ; CHECK-NEXT: %gp_phi2:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2 ; CHECK-NEXT: %gp_phi3:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %fp_phi, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %fp_phi, %subreg.hsub ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir index 2ca371beb5028..e4d6ad8320ab7 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir @@ -677,7 +677,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) @@ -713,7 +713,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) @@ -749,7 +749,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) @@ -785,7 +785,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]] ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir index 6b4bbb85b2ec4..da3c962f2468e 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir @@ -51,7 +51,7 @@ body: | ; CHECK-LABEL: name: anyext_load_monotonic_i32 ; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $xzr ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load monotonic (s32) from `ptr null`) - ; CHECK-NEXT: %ld:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32 + ; CHECK-NEXT: %ld:gpr64all = SUBREG_TO_REG [[LDRWui]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY %ld ; CHECK-NEXT: RET_ReallyLR implicit $x0 %1:gpr(p0) = G_CONSTANT i64 0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir index 5efa45dd78075..457c5d6411b64 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir @@ -32,7 +32,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr) ; CHECK-NEXT: $x0 = COPY [[SWPX]] %0:gpr(p0) = COPY $x0 @@ -54,7 +54,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr) ; CHECK-NEXT: $x0 = COPY [[LDADDX]] %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir index d3d413c34ea72..0b2121db4e7c4 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir @@ -250,7 +250,7 @@ body: | ; CHECK: liveins: $s0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %val:fpr32 = COPY $s0 - ; CHECK-NEXT: %bv:fpr128 = SUBREG_TO_REG 0, %val, %subreg.ssub + ; CHECK-NEXT: %bv:fpr128 = SUBREG_TO_REG %val, %subreg.ssub ; CHECK-NEXT: $q0 = COPY %bv ; CHECK-NEXT: RET_ReallyLR implicit $q0 %val:fpr(s32) = COPY $s0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir index df4e7ddaac8b9..6154fd27406bf 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir @@ -62,7 +62,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK-NEXT: $w0 = COPY [[CSINCWr]] @@ -231,7 +231,7 @@ body: | ; CHECK-LABEL: name: cmp_arith_extended_s32 ; CHECK: liveins: $w0, $w1, $h0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG $h0, %subreg.hsub ; CHECK-NEXT: %reg0:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: %reg1:gpr32sp = COPY $w1 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0 @@ -266,7 +266,7 @@ body: | ; CHECK-NEXT: %reg0:gpr32 = COPY $w0 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg0, 0 - ; CHECK-NEXT: %ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv ; CHECK-NEXT: $w0 = COPY %cmp @@ -425,7 +425,7 @@ body: | ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0 - ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs ; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext ; CHECK-NEXT: $x0 = COPY %or @@ -461,7 +461,7 @@ body: | ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0 - ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], %cmp, %subreg.sub_32 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir index be5939c346223..33cb75f7b8f46 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir @@ -47,7 +47,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[CASX:%[0-9]+]]:gpr64 = CASX [[COPY1]], [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr) ; CHECK-NEXT: $x0 = COPY [[CASX]] %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir index 417ac91113f2c..72e691bf520ea 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir @@ -213,7 +213,7 @@ body: | bb.0: ; CHECK-LABEL: name: opt_i64 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s64) = G_CONSTANT i64 42 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir index 55dfbcd7a88a8..69f97f449b430 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir @@ -67,7 +67,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK-NEXT: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[COPY]], 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UMOVvi32_]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:fpr(<4 x s32>) = COPY $q0 @@ -95,7 +95,7 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub ; CHECK-NEXT: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[INSERT_SUBREG]], 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UMOVvi32_]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:fpr(<2 x s32>) = COPY $d0 @@ -323,7 +323,7 @@ body: | ; CHECK-LABEL: name: skip_anyext_to_16 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr8 = COPY [[DEF]].bsub - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[COPY]], %subreg.bsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] %5:fpr(<16 x s8>) = G_IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir index 80c2f8ca08608..b485cd2e88edd 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir @@ -17,7 +17,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -44,7 +44,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -71,7 +71,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpost [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -98,7 +98,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -125,7 +125,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpost [[COPY]], 4 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -152,7 +152,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpost [[COPY]], 4 :: (load (s32)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.ssub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -179,7 +179,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr16 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $h0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -206,7 +206,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -233,7 +233,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr8 = LDRBpre [[COPY]], 4 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.bsub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -260,7 +260,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %4, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG %4, %subreg.hsub ; CHECK-NEXT: $s0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -287,7 +287,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr16 = LDRHpre [[COPY]], 4 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.hsub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 @@ -314,7 +314,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: early-clobber %3:gpr64sp, %4:fpr32 = LDRSpre [[COPY]], 4 :: (load (s32)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, %4, %subreg.ssub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG %4, %subreg.ssub ; CHECK-NEXT: $d0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY %3 ; CHECK-NEXT: RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir index 9f02f31a15e32..ce7dc4feb187c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir @@ -62,14 +62,14 @@ body: | ; CHECK: liveins: $w0, $w1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; ; CHECK-TINY-LABEL: name: imm_s64_gpr ; CHECK-TINY: liveins: $w0, $w1 ; CHECK-TINY-NEXT: {{ $}} ; CHECK-TINY-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1234 - ; CHECK-TINY-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-TINY-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-TINY-NEXT: $x0 = COPY [[SUBREG_TO_REG]] %0(s64) = G_CONSTANT i64 1234 $x0 = COPY %0(s64) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir index f4675e1b752aa..78d86a6821877 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir @@ -15,9 +15,9 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY]], %subreg.sub_32 ; CHECK-NEXT: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG]], 0, 31 - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY]], %subreg.sub_32 ; CHECK-NEXT: [[BFMXri1:%[0-9]+]]:gpr64 = BFMXri [[DEF]], [[SUBREG_TO_REG1]], 51, 31 ; CHECK-NEXT: $x0 = COPY [[BFMXri]] ; CHECK-NEXT: $x1 = COPY [[BFMXri1]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir index e3712db51ad3a..c2d03330cf41c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -176,7 +176,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] %0(s32) = COPY $w0 %1(s64) = G_ZEXT %0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir index 4ac009de19113..92121b0b42162 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir @@ -26,7 +26,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv ; CHECK-NEXT: Bcc 8, %bb.3, implicit $nzcv ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir index afc5ea2e64b7e..8b1f73ec11937 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def dead $nzcv ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[SUBSWri]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv ; CHECK-NEXT: Bcc 8, %bb.4, implicit $nzcv ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir index 79b0e678a62de..6526cd977eb55 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir @@ -22,7 +22,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDAXRB:%[0-9]+]]:gpr32 = LDAXRB [[COPY]] :: (volatile load (s8) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRB]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRB]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 @@ -45,7 +45,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDAXRH:%[0-9]+]]:gpr32 = LDAXRH [[COPY]] :: (volatile load (s16) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRH]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRH]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 @@ -68,7 +68,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDAXRW:%[0-9]+]]:gpr32 = LDAXRW [[COPY]] :: (volatile load (s32) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRW]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDAXRW]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir index 93d3aec10235f..1eaafd517d986 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir @@ -21,7 +21,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load (s8) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRB]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRB]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 @@ -44,7 +44,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load (s16) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRH]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRH]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 @@ -67,7 +67,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load (s32) from %ir.addr) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRW]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDXRW]], %subreg.sub_32 ; CHECK-NEXT: $x1 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x1 %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir index bd97890866fd5..bc094e7703b97 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir @@ -711,7 +711,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRHui:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRHui]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[LDRHui]], %subreg.hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] ; CHECK-NEXT: RET_ReallyLR @@ -745,7 +745,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[LDRBui]], %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[LDRBui]], %subreg.bsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] ; CHECK-NEXT: RET_ReallyLR diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir index d0314682a441c..349513158e41c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir @@ -52,7 +52,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10000 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[SUBREG_TO_REG]] ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir index d2caee5683f99..87acc06df1940 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir @@ -18,7 +18,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>)) ; CHECK-NEXT: [[ADDVv16i8v:%[0-9]+]]:fpr8 = ADDVv16i8v [[LDRQui]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv16i8v]], %subreg.bsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[ADDVv16i8v]], %subreg.bsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] ; CHECK-NEXT: RET_ReallyLR implicit $w0 @@ -49,7 +49,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>)) ; CHECK-NEXT: [[ADDVv8i16v:%[0-9]+]]:fpr16 = ADDVv8i16v [[LDRQui]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv8i16v]], %subreg.hsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG [[ADDVv8i16v]], %subreg.hsub ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: $w0 = COPY [[COPY1]] ; CHECK-NEXT: RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir index 4e7affc12b092..3103ef512ad00 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir @@ -21,7 +21,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]] ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ADDWrr]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s32) = COPY $w0 @@ -48,7 +48,7 @@ body: | ; CHECK: liveins: $w0, $w1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[DEF]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[DEF]], %subreg.sub_32 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 @@ -74,7 +74,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %copy:gpr32 = COPY $w0 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %copy, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY %zext ; CHECK-NEXT: RET_ReallyLR implicit $x0 %copy:gpr(s32) = COPY $w0 @@ -100,7 +100,7 @@ body: | ; CHECK-NEXT: %copy:gpr32all = COPY $w0 ; CHECK-NEXT: %bitcast1:gpr32 = COPY %copy ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %bitcast1, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY %zext ; CHECK-NEXT: RET_ReallyLR implicit $x0 %copy:gpr(s32) = COPY $w0 @@ -128,7 +128,7 @@ body: | ; CHECK-NEXT: %copy:gpr64sp = COPY $x0 ; CHECK-NEXT: %trunc:gpr32common = COPY %copy.sub_32 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %trunc, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY %zext ; CHECK-NEXT: RET_ReallyLR implicit $x0 %copy:gpr(s64) = COPY $x0 @@ -161,7 +161,7 @@ body: | ; CHECK-NEXT: bb.2: ; CHECK-NEXT: %phi:gpr32 = PHI %copy1, %bb.0, %copy2, %bb.1 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %phi, 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 ; We should have a ORRWrs here, because isDef32 disallows phis. @@ -202,7 +202,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]] ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ADDWrr]], 0 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(s32) = COPY $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir index dc213520f320d..42b1c61949b94 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir @@ -25,8 +25,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY $w1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32 - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_32 ; CHECK-NEXT: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[SUBREG_TO_REG]], [[SUBREG_TO_REG1]], 32, 31 ; CHECK-NEXT: $x0 = COPY [[BFMXri]] %0(s32) = COPY $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir index 0cb95de0640be..c802914bbb981 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir @@ -193,7 +193,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32 ; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] @@ -220,7 +220,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64common = ANDXri [[SUBREG_TO_REG]], 8000 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32 ; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir index e26c143135097..e36e8c8b5ab29 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir @@ -575,7 +575,7 @@ body: | ; CHECK-NEXT: %t:gpr64 = COPY $x2 ; CHECK-NEXT: %negative_one:gpr32 = MOVi32imm -1 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %negative_one, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: %xor:gpr64 = EORXrr %reg1, %zext ; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv ; CHECK-NEXT: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir index b207c851c8ba4..33c56c4a6d044 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir @@ -25,7 +25,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: STLRW [[COPY2]], [[COPY]] :: (store release (s32)) ; CHECK-NEXT: {{ $}} @@ -71,7 +71,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: STLRH [[COPY2]], [[COPY]] :: (store release (s16)) ; CHECK-NEXT: {{ $}} @@ -117,7 +117,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 4 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: STLRB [[COPY2]], [[COPY]] :: (store release (s8)) ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir index d3636c1380d2e..ae10f4a5b30ab 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir @@ -24,7 +24,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096 ; CHECK-NEXT: $x0 = COPY [[ANDXri]] diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir index bbf573c3a6c81..0cf16ec9f8e95 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir @@ -52,7 +52,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRWui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRWui]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 @@ -74,7 +74,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRHHui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRHHui]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 @@ -96,7 +96,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8)) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir index 92a37ebf87d9a..8995d2616e52b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir @@ -55,7 +55,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %reg:gpr32 = COPY $w0 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg, 0 - ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 + ; CHECK-NEXT: %zext:gpr64 = SUBREG_TO_REG [[ORRWrs]], %subreg.sub_32 ; CHECK-NEXT: TBZX %zext, 33, %bb.1 ; CHECK-NEXT: B %bb.0 ; CHECK-NEXT: {{ $}} @@ -90,7 +90,7 @@ body: | ; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %reg:gpr32 = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %reg, %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG %reg, %subreg.sub_32 ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15 ; CHECK-NEXT: TBZX %zext, 33, %bb.1 ; CHECK-NEXT: B %bb.0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir b/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir index 0f430dcc8f5c8..4bf7a93239eff 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir @@ -51,7 +51,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %copy:gpr64sp = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 61440 - ; CHECK-NEXT: %cst:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: %cst:gpr64 = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: %load:gpr64 = LDRXroX %copy, %cst, 0, 0 :: (volatile load (s64)) ; CHECK-NEXT: RET_ReallyLR %copy:gpr(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir index 17c15124e787e..95ca948a30fd6 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir @@ -13,7 +13,7 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], killed [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD_LANE_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, killed [[COPY2]] ; CHECK-NEXT: [[LD_LANE_2:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_1]], 2, killed [[COPY3]] ; CHECK-NEXT: [[LD_LANE_3:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_2]], 3, killed [[COPY4]] @@ -25,7 +25,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, killed %2 %8:fpr128 = LD1i32 %7, 2, killed %3 %9:fpr128 = LD1i32 %8, 3, killed %4 diff --git a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir index 6b338d98afb53..dee222faf20b1 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir @@ -20,7 +20,7 @@ body: | ; CHECK-NEXT: [[PTR_2:%[0-9]+]]:gpr64common = COPY $x2 ; CHECK-NEXT: [[PTR_3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[BASE_REG]], killed [[PTR_1]], 0, 1 - ; CHECK-NEXT: [[LD_LANE_0:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[LD_LANE_0:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD_LANE_1:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_0]], 1, [[PTR_2]] ; CHECK-NEXT: $x0 = COPY [[PTR_2]] ; CHECK-NEXT: BL @external_func, csr_aarch64_aapcs, implicit-def $lr, implicit $x0, implicit-def $x0 @@ -34,7 +34,7 @@ body: | %2:gpr64common = COPY $x2 %3:gpr64common = COPY $x3 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, %2 $x0 = COPY %2 BL @external_func, csr_aarch64_aapcs, implicit-def $lr, implicit $x0, implicit-def $x0 diff --git a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir index a7570d2293f8a..be4448928fdcf 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir @@ -14,10 +14,10 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, [[COPY2]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr32 = LDRSui [[COPY3]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.ssub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.ssub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i32 [[SECOND_REG]], 1, [[COPY4]] ; CHECK-NEXT: [[ZIP:%[0-9]+]]:fpr128 = ZIP1v2i64 [[LD0_1]], [[LD1_1]] ; CHECK-NEXT: $q0 = COPY [[ZIP]] @@ -28,7 +28,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSroX %0, %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, %2 %8:fpr128 = LD1i32 %7, 2, %3 %9:fpr128 = LD1i32 %8, 3, %4 @@ -48,10 +48,10 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSui [[COPY]], 0 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, killed [[COPY1]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr32 = LDRSui [[COPY2]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.ssub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.ssub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i32 [[SECOND_REG]], 1, killed [[COPY3]] ; CHECK-NEXT: [[ZIP:%[0-9]+]]:fpr128 = ZIP1v2i64 [[LD0_1]], [[LD1_1]] ; CHECK-NEXT: $q0 = COPY [[ZIP]] @@ -62,7 +62,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSui %0, 0 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, killed %1 %8:fpr128 = LD1i32 %7, 2, killed %2 %9:fpr128 = LD1i32 %8, 3, killed %3 @@ -86,12 +86,12 @@ body: | ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr64common = COPY $x7 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr64common = COPY $x8 ; CHECK-NEXT: [[LD_i16:%[0-9]+]]:fpr16 = LDRHroX [[COPY]], killed [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i16]], %subreg.hsub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i16]], %subreg.hsub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i16 [[FIRST_REG]], 1, killed [[COPY2]] ; CHECK-NEXT: [[LD0_2:%[0-9]+]]:fpr128 = LD1i16 [[LD0_1]], 2, killed [[COPY3]] ; CHECK-NEXT: [[LD0_3:%[0-9]+]]:fpr128 = LD1i16 [[LD0_2]], 3, killed [[COPY4]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr16 = LDRHui [[COPY5]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.hsub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.hsub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i16 [[SECOND_REG]], 1, killed [[COPY6]] ; CHECK-NEXT: [[LD1_2:%[0-9]+]]:fpr128 = LD1i16 [[LD1_1]], 2, killed [[COPY7]] ; CHECK-NEXT: [[LD1_3:%[0-9]+]]:fpr128 = LD1i16 [[LD1_2]], 3, killed [[COPY8]] @@ -108,7 +108,7 @@ body: | %7:gpr64common = COPY $x7 %8:gpr64common = COPY $x8 %9:fpr16 = LDRHroX %0, killed %1, 0, 1 - %10:fpr128 = SUBREG_TO_REG 0, killed %9, %subreg.hsub + %10:fpr128 = SUBREG_TO_REG killed %9, %subreg.hsub %11:fpr128 = LD1i16 %10, 1, killed %2 %12:fpr128 = LD1i16 %11, 2, killed %3 %13:fpr128 = LD1i16 %12, 3, killed %4 @@ -136,12 +136,12 @@ body: | ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr64common = COPY $x7 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr64common = COPY $x8 ; CHECK-NEXT: [[LD_i16:%[0-9]+]]:fpr16 = LDRHui [[COPY]], 0 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i16]], %subreg.hsub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i16]], %subreg.hsub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i16 [[FIRST_REG]], 1, killed [[COPY1]] ; CHECK-NEXT: [[LD0_2:%[0-9]+]]:fpr128 = LD1i16 [[LD0_1]], 2, killed [[COPY2]] ; CHECK-NEXT: [[LD0_3:%[0-9]+]]:fpr128 = LD1i16 [[LD0_2]], 3, killed [[COPY3]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr16 = LDRHui [[COPY4]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.hsub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.hsub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i16 [[SECOND_REG]], 1, killed [[COPY5]] ; CHECK-NEXT: [[LD1_2:%[0-9]+]]:fpr128 = LD1i16 [[LD1_1]], 2, killed [[COPY6]] ; CHECK-NEXT: [[LD1_3:%[0-9]+]]:fpr128 = LD1i16 [[LD1_2]], 3, killed [[COPY7]] @@ -158,7 +158,7 @@ body: | %7:gpr64common = COPY $x7 %8:gpr64common = COPY $x8 %9:fpr16 = LDRHui %0, 0 - %10:fpr128 = SUBREG_TO_REG 0, killed %9, %subreg.hsub + %10:fpr128 = SUBREG_TO_REG killed %9, %subreg.hsub %11:fpr128 = LD1i16 %10, 1, killed %1 %12:fpr128 = LD1i16 %11, 2, killed %2 %13:fpr128 = LD1i16 %12, 3, killed %3 @@ -194,7 +194,7 @@ body: | ; CHECK-NEXT: [[COPY15:%[0-9]+]]:gpr64common = COPY $x15 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:gpr64common = COPY $x16 ; CHECK-NEXT: [[LD_i8:%[0-9]+]]:fpr8 = LDRBroX [[COPY]], killed [[COPY1]], 0, 0 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i8]], %subreg.bsub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i8]], %subreg.bsub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i8 [[FIRST_REG]], 1, killed [[COPY2]] ; CHECK-NEXT: [[LD0_2:%[0-9]+]]:fpr128 = LD1i8 [[LD0_1]], 2, killed [[COPY3]] ; CHECK-NEXT: [[LD0_3:%[0-9]+]]:fpr128 = LD1i8 [[LD0_2]], 3, killed [[COPY4]] @@ -203,7 +203,7 @@ body: | ; CHECK-NEXT: [[LD0_6:%[0-9]+]]:fpr128 = LD1i8 [[LD0_5]], 6, killed [[COPY7]] ; CHECK-NEXT: [[LD0_7:%[0-9]+]]:fpr128 = LD1i8 [[LD0_6]], 7, killed [[COPY8]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr8 = LDRBui [[COPY9]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.bsub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.bsub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i8 [[SECOND_REG]], 1, killed [[COPY10]] ; CHECK-NEXT: [[LD1_2:%[0-9]+]]:fpr128 = LD1i8 [[LD1_1]], 2, killed [[COPY11]] ; CHECK-NEXT: [[LD1_3:%[0-9]+]]:fpr128 = LD1i8 [[LD1_2]], 3, killed [[COPY12]] @@ -232,7 +232,7 @@ body: | %15:gpr64common = COPY $x15 %16:gpr64common = COPY $x16 %17:fpr8 = LDRBroX %0, killed %1, 0, 0 - %18:fpr128 = SUBREG_TO_REG 0, killed %17, %subreg.bsub + %18:fpr128 = SUBREG_TO_REG killed %17, %subreg.bsub %19:fpr128 = LD1i8 %18, 1, killed %2 %20:fpr128 = LD1i8 %19, 2, killed %3 %21:fpr128 = LD1i8 %20, 3, killed %4 @@ -280,10 +280,10 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], killed [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD0_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, killed [[COPY3]] ; CHECK-NEXT: [[LD1_0:%[0-9]+]]:fpr32 = LDRSui [[COPY2]], 0 - ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD1_0]], %subreg.ssub + ; CHECK-NEXT: [[SECOND_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD1_0]], %subreg.ssub ; CHECK-NEXT: [[LD1_1:%[0-9]+]]:fpr128 = LD1i32 [[SECOND_REG]], 1, killed [[COPY4]] ; CHECK-NEXT: [[ZIP:%[0-9]+]]:fpr128 = ZIP1v2i64 [[LD0_1]], [[LD1_1]] ; CHECK-NEXT: $q0 = COPY [[ZIP]] @@ -294,7 +294,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 2, killed %2 %8:fpr128 = LD1i32 %7, 1, killed %3 %9:fpr128 = LD1i32 %8, 3, killed %4 @@ -342,7 +342,7 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64common = COPY $x4 ; CHECK-NEXT: [[LD_i32:%[0-9]+]]:fpr32 = LDRSroX [[COPY]], killed [[COPY1]], 0, 1 - ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LD_i32]], %subreg.ssub + ; CHECK-NEXT: [[FIRST_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LD_i32]], %subreg.ssub ; CHECK-NEXT: [[LD_LANE_1:%[0-9]+]]:fpr128 = LD1i32 [[FIRST_REG]], 1, killed [[COPY2]] ; CHECK-NEXT: [[LD_LANE_2:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_1]], 2, killed [[COPY3]] ; CHECK-NEXT: [[LD_LANE_3:%[0-9]+]]:fpr128 = LD1i32 [[LD_LANE_2]], 3, killed [[COPY4]] @@ -355,7 +355,7 @@ body: | %3:gpr64common = COPY $x3 %4:gpr64common = COPY $x4 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, killed %2 %8:fpr128 = LD1i32 %7, 2, killed %3 %9:fpr128 = LD1i32 %8, 3, killed %4 @@ -377,7 +377,7 @@ body: | ; CHECK-NEXT: [[ALIAS_ADDR:%[0-9]+]]:gpr64common = COPY $x2 ; CHECK-NEXT: [[OTHER_ADDR:%[0-9]+]]:gpr64common = COPY $x3 ; CHECK-NEXT: [[LOAD0:%[0-9]+]]:fpr32 = LDRSroX [[BASE_PTR]], killed [[OFFSET_PTR]], 0, 1 - ; CHECK-NEXT: [[VEC0:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, killed [[LOAD0]], %subreg.ssub + ; CHECK-NEXT: [[VEC0:%[0-9]+]]:fpr128 = SUBREG_TO_REG killed [[LOAD0]], %subreg.ssub ; CHECK-NEXT: [[VEC1:%[0-9]+]]:fpr128 = LD1i32 [[VEC0]], 1, [[ALIAS_ADDR]] ; CHECK-NEXT: [[CONST:%[0-9]+]]:gpr32 = MOVi32imm 99 ; CHECK-NEXT: STRWui [[CONST]], [[ALIAS_ADDR]], 0 @@ -390,7 +390,7 @@ body: | %2:gpr64common = COPY $x2 %3:gpr64common = COPY $x3 %5:fpr32 = LDRSroX %0, killed %1, 0, 1 - %6:fpr128 = SUBREG_TO_REG 0, killed %5, %subreg.ssub + %6:fpr128 = SUBREG_TO_REG killed %5, %subreg.ssub %7:fpr128 = LD1i32 %6, 1, %2 %10:gpr32 = MOVi32imm 99 STRWui %10, %2, 0 diff --git a/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir b/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir index 431e457ad38a3..851944b1beec0 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir @@ -15,7 +15,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY $xzr ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[COPY1]] ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.13: ; CHECK-NEXT: successors: %bb.14(0x80000000), %bb.15(0x00000000) @@ -23,7 +23,7 @@ body: | ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = nsw SUBSXri [[SUBREG_TO_REG]], 1, 0, implicit-def $nzcv ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64all = COPY [[SUBSXri]] - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: Bcc 0, %bb.15, implicit $nzcv ; CHECK-NEXT: B %bb.14 ; CHECK-NEXT: {{ $}} @@ -36,7 +36,7 @@ body: | ; CHECK-NEXT: STRDui [[PHI2]], [[COPY]], 0 ; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 ; CHECK-NEXT: [[SUBSXri1:%[0-9]+]]:gpr64 = nsw SUBSXri [[PHI]], 1, 0, implicit-def $nzcv - ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr64all = COPY [[SUBSXri1]] ; CHECK-NEXT: Bcc 1, %bb.14, implicit $nzcv ; CHECK-NEXT: B %bb.15 @@ -170,7 +170,7 @@ body: | %1:gpr64sp = COPY $xzr %2:gpr64all = COPY %1 %3:gpr32 = MOVi32imm 1 - %4:gpr64all = SUBREG_TO_REG 0, %3, %subreg.sub_32 + %4:gpr64all = SUBREG_TO_REG %3, %subreg.sub_32 bb.1: successors: %bb.2(0x04000000), %bb.1(0x7c000000) @@ -181,7 +181,7 @@ body: | STRDui killed %9, %0, 0 %10:gpr64 = nsw SUBSXri %5, 1, 0, implicit-def $nzcv %6:gpr64all = COPY %10 - %8:gpr64all = SUBREG_TO_REG 0, %3, %subreg.sub_32 + %8:gpr64all = SUBREG_TO_REG %3, %subreg.sub_32 Bcc 1, %bb.1, implicit $nzcv B %bb.2 diff --git a/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir b/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir index 48f02452e3597..fae2bdcd5e073 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir +++ b/llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir @@ -14,7 +14,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 ; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64sp = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000) @@ -80,7 +80,7 @@ body: | %0:gpr64common = COPY $x0 %1:fpr64 = FMOVD0 %2:gpr32 = MOVi32imm 1 - %3:gpr64all = SUBREG_TO_REG 0, killed %2, %subreg.sub_32 + %3:gpr64all = SUBREG_TO_REG killed %2, %subreg.sub_32 bb.1: successors: %bb.2(0x04000000), %bb.1(0x7c000000) diff --git a/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir b/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir index f6c0ec083096e..8f01a17568cda 100644 --- a/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir +++ b/llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir @@ -38,12 +38,12 @@ body: | ; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64common = ADDXri [[ADDXri]], 3549, 0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ADDXri1]].sub_32 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 28, 31 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UBFMWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UBFMWri]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr64 = COPY $x0 %1:gpr32 = MOVi32imm 1121757 - %2:gpr64 = SUBREG_TO_REG 0, %1, %subreg.sub_32 + %2:gpr64 = SUBREG_TO_REG %1, %subreg.sub_32 %3:gpr64 = ADDXrr %0, killed %2 %4:gpr64 = UBFMXri %3, 28, 31 $x0 = COPY %4 @@ -62,7 +62,7 @@ body: | ; CHECK-NEXT: [[SUBXri1:%[0-9]+]]:gpr64common = SUBXri [[SUBXri]], 3549, 0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[SUBXri1]].sub_32 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 28, 31 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UBFMWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[UBFMWri]], %subreg.sub_32 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr64 = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/addsub.ll b/llvm/test/CodeGen/AArch64/addsub.ll index bb0d38aff1eb1..b8e5884866476 100644 --- a/llvm/test/CodeGen/AArch64/addsub.ll +++ b/llvm/test/CodeGen/AArch64/addsub.ll @@ -379,7 +379,7 @@ define i1 @uadd_add(i8 %a, i8 %b, ptr %p) { ; This is a unique edge case that will generate the following MIR ; MOVi32imm -1000000 -; SUBREG_TO_REG 0, killed %1, %subreg.sub_32 +; SUBREG_TO_REG killed %1, %subreg.sub_32 ; When using a 64-bit unsigned for the "-1000000" immediate, the code ; must make sure to zero out the top 32 bits since SUBREG_TO_REG is ; zero extending the value diff --git a/llvm/test/CodeGen/AArch64/arm64-constrained-fcmp-no-nans-opt.ll b/llvm/test/CodeGen/AArch64/arm64-constrained-fcmp-no-nans-opt.ll index 968acb2565b4e..2ddaf0ecf7619 100644 --- a/llvm/test/CodeGen/AArch64/arm64-constrained-fcmp-no-nans-opt.ll +++ b/llvm/test/CodeGen/AArch64/arm64-constrained-fcmp-no-nans-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm64-eabi -mattr=+fullfp16 -enable-no-nans-fp-math | FileCheck %s +; RUN: llc < %s -mtriple=arm64-eabi -mattr=+fullfp16 | FileCheck %s declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata) declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata) @@ -7,7 +7,7 @@ declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, met ; CHECK: fcmp s0, s1 ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret -define i1 @f32_constrained_fcmp_ueq(float %a, float %b) nounwind ssp strictfp { +define i1 @f32_constrained_fcmp_ueq(float nofpclass(nan) %a, float nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ueq", metadata !"fpexcept.strict") ret i1 %cmp } @@ -16,7 +16,7 @@ define i1 @f32_constrained_fcmp_ueq(float %a, float %b) nounwind ssp strictfp { ; CHECK: fcmp s0, s1 ; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret -define i1 @f32_constrained_fcmp_une(float %a, float %b) nounwind ssp strictfp { +define i1 @f32_constrained_fcmp_une(float nofpclass(nan) %a, float nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") ret i1 %cmp } @@ -25,7 +25,7 @@ define i1 @f32_constrained_fcmp_une(float %a, float %b) nounwind ssp strictfp { ; CHECK: fcmp s0, s1 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret -define i1 @f32_constrained_fcmp_ugt(float %a, float %b) nounwind ssp strictfp { +define i1 @f32_constrained_fcmp_ugt(float nofpclass(nan) %a, float nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ugt", metadata !"fpexcept.strict") ret i1 %cmp } @@ -34,7 +34,7 @@ define i1 @f32_constrained_fcmp_ugt(float %a, float %b) nounwind ssp strictfp { ; CHECK: fcmp s0, s1 ; CHECK-NEXT: cset w0, ge ; CHECK-NEXT: ret -define i1 @f32_constrained_fcmp_uge(float %a, float %b) nounwind ssp strictfp { +define i1 @f32_constrained_fcmp_uge(float nofpclass(nan) %a, float nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"uge", metadata !"fpexcept.strict") ret i1 %cmp } @@ -43,7 +43,7 @@ define i1 @f32_constrained_fcmp_uge(float %a, float %b) nounwind ssp strictfp { ; CHECK: fcmp s0, s1 ; CHECK-NEXT: cset w0, lt ; CHECK-NEXT: ret -define i1 @f32_constrained_fcmp_ult(float %a, float %b) nounwind ssp strictfp { +define i1 @f32_constrained_fcmp_ult(float nofpclass(nan) %a, float nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ult", metadata !"fpexcept.strict") ret i1 %cmp } @@ -52,7 +52,7 @@ define i1 @f32_constrained_fcmp_ult(float %a, float %b) nounwind ssp strictfp { ; CHECK: fcmp s0, s1 ; CHECK-NEXT: cset w0, le ; CHECK-NEXT: ret -define i1 @f32_constrained_fcmp_ule(float %a, float %b) nounwind ssp strictfp { +define i1 @f32_constrained_fcmp_ule(float nofpclass(nan) %a, float nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ule", metadata !"fpexcept.strict") ret i1 %cmp } @@ -61,7 +61,7 @@ define i1 @f32_constrained_fcmp_ule(float %a, float %b) nounwind ssp strictfp { ; CHECK: fcmp d0, d1 ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret -define i1 @f64_constrained_fcmp_ueq(double %a, double %b) nounwind ssp strictfp { +define i1 @f64_constrained_fcmp_ueq(double nofpclass(nan) %a, double nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ueq", metadata !"fpexcept.strict") ret i1 %cmp } @@ -70,7 +70,7 @@ define i1 @f64_constrained_fcmp_ueq(double %a, double %b) nounwind ssp strictfp ; CHECK: fcmp d0, d1 ; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret -define i1 @f64_constrained_fcmp_une(double %a, double %b) nounwind ssp strictfp { +define i1 @f64_constrained_fcmp_une(double nofpclass(nan) %a, double nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict") ret i1 %cmp } @@ -79,7 +79,7 @@ define i1 @f64_constrained_fcmp_une(double %a, double %b) nounwind ssp strictfp ; CHECK: fcmp d0, d1 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret -define i1 @f64_constrained_fcmp_ugt(double %a, double %b) nounwind ssp strictfp { +define i1 @f64_constrained_fcmp_ugt(double nofpclass(nan) %a, double nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ugt", metadata !"fpexcept.strict") ret i1 %cmp } @@ -88,7 +88,7 @@ define i1 @f64_constrained_fcmp_ugt(double %a, double %b) nounwind ssp strictfp ; CHECK: fcmp d0, d1 ; CHECK-NEXT: cset w0, ge ; CHECK-NEXT: ret -define i1 @f64_constrained_fcmp_uge(double %a, double %b) nounwind ssp strictfp { +define i1 @f64_constrained_fcmp_uge(double nofpclass(nan) %a, double nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"uge", metadata !"fpexcept.strict") ret i1 %cmp } @@ -97,7 +97,7 @@ define i1 @f64_constrained_fcmp_uge(double %a, double %b) nounwind ssp strictfp ; CHECK: fcmp d0, d1 ; CHECK-NEXT: cset w0, lt ; CHECK-NEXT: ret -define i1 @f64_constrained_fcmp_ult(double %a, double %b) nounwind ssp strictfp { +define i1 @f64_constrained_fcmp_ult(double nofpclass(nan) %a, double nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ult", metadata !"fpexcept.strict") ret i1 %cmp } @@ -106,7 +106,7 @@ define i1 @f64_constrained_fcmp_ult(double %a, double %b) nounwind ssp strictfp ; CHECK: fcmp d0, d1 ; CHECK-NEXT: cset w0, le ; CHECK-NEXT: ret -define i1 @f64_constrained_fcmp_ule(double %a, double %b) nounwind ssp strictfp { +define i1 @f64_constrained_fcmp_ule(double nofpclass(nan) %a, double nofpclass(nan) %b) nounwind ssp strictfp { %cmp = tail call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ule", metadata !"fpexcept.strict") ret i1 %cmp } diff --git a/llvm/test/CodeGen/AArch64/bf16_fast_math.ll b/llvm/test/CodeGen/AArch64/bf16_fast_math.ll index e52c76fcc3f20..c01b12b0ff202 100644 --- a/llvm/test/CodeGen/AArch64/bf16_fast_math.ll +++ b/llvm/test/CodeGen/AArch64/bf16_fast_math.ll @@ -12,10 +12,10 @@ define bfloat @normal_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: {{ $}} ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -36,10 +36,10 @@ define bfloat @normal_fadd(bfloat %x, bfloat %y) { ; CHECK-BF16-NEXT: {{ $}} ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -58,10 +58,10 @@ define bfloat @fast_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: {{ $}} ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -82,10 +82,10 @@ define bfloat @fast_fadd(bfloat %x, bfloat %y) { ; CHECK-BF16-NEXT: {{ $}} ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -104,10 +104,10 @@ define bfloat @ninf_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: {{ $}} ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -128,10 +128,10 @@ define bfloat @ninf_fadd(bfloat %x, bfloat %y) { ; CHECK-BF16-NEXT: {{ $}} ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY3]], killed [[COPY2]], implicit $fpcr @@ -154,10 +154,10 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr @@ -169,10 +169,10 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31 ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]] ; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[COPY7]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-NOBF16-NEXT: [[COPY8:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr @@ -193,18 +193,18 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr ; CHECK-BF16-NEXT: [[BFCVT:%[0-9]+]]:fpr16 = nofpexcept BFCVT killed [[FADDSrr]], implicit $fpcr - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[BFCVT]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[BFCVT]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-BF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-BF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-BF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nofpexcept FADDSrr killed [[COPY5]], killed [[COPY6]], implicit $fpcr @@ -225,10 +225,10 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr @@ -240,10 +240,10 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) ; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31 ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]] ; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[COPY7]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-NOBF16-NEXT: [[COPY8:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr @@ -264,14 +264,14 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-BF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub ; CHECK-BF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = nnan ninf contract nofpexcept FADDSrr killed [[FADDSrr]], killed [[COPY5]], implicit $fpcr @@ -292,10 +292,10 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-NOBF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-NOBF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-NOBF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-NOBF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr @@ -307,10 +307,10 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri killed [[ADDWrr1]], 16, 31 ; CHECK-NOBF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY killed [[UBFMWri1]] ; CHECK-NOBF16-NEXT: [[COPY7:%[0-9]+]]:fpr16 = COPY [[COPY6]].hsub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[COPY7]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[COPY7]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-NOBF16-NEXT: [[COPY8:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-NOBF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-NOBF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-NOBF16-NEXT: [[COPY9:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-NOBF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY8]], killed [[COPY9]], implicit $fpcr @@ -331,18 +331,18 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-BF16-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h2 ; CHECK-BF16-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $h1 ; CHECK-BF16-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY1]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG]] ; CHECK-BF16-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY2]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY2]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_1:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG1]] ; CHECK-BF16-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_1]].ssub ; CHECK-BF16-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY4]], killed [[COPY3]], implicit $fpcr ; CHECK-BF16-NEXT: [[BFCVT:%[0-9]+]]:fpr16 = ninf nofpexcept BFCVT killed [[FADDSrr]], implicit $fpcr - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, killed [[BFCVT]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:fpr64 = SUBREG_TO_REG killed [[BFCVT]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_2:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG2]] ; CHECK-BF16-NEXT: [[COPY5:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_2]].ssub - ; CHECK-BF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub + ; CHECK-BF16-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:fpr64 = SUBREG_TO_REG [[COPY]], %subreg.hsub ; CHECK-BF16-NEXT: [[SHLLv4i16_3:%[0-9]+]]:fpr128 = SHLLv4i16 killed [[SUBREG_TO_REG3]] ; CHECK-BF16-NEXT: [[COPY6:%[0-9]+]]:fpr32 = COPY [[SHLLv4i16_3]].ssub ; CHECK-BF16-NEXT: [[FADDSrr1:%[0-9]+]]:fpr32 = ninf nofpexcept FADDSrr killed [[COPY5]], killed [[COPY6]], implicit $fpcr diff --git a/llvm/test/CodeGen/AArch64/build-vector-dup-simd-nnan.ll b/llvm/test/CodeGen/AArch64/build-vector-dup-simd-nnan.ll new file mode 100644 index 0000000000000..440fd2ba7f8f7 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/build-vector-dup-simd-nnan.ll @@ -0,0 +1,294 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK + +define <1 x float> @dup_v1i32_oeq(float %a, float %b) { +; CHECK-LABEL: dup_v1i32_oeq: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmeq s0, s0, s1 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan oeq float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_ogt(float %a, float %b) { +; CHECK-LABEL: dup_v1i32_ogt: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s0, s0, s1 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ogt float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_oge(float %a, float %b) { +; CHECK-LABEL: dup_v1i32_oge: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s0, s0, s1 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan oge float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_olt(float %a, float %b) { +; CHECK-LABEL: dup_v1i32_olt: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s0, s1, s0 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan olt float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_ole(float %a, float %b) { +; CHECK-LABEL: dup_v1i32_ole: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s0, s1, s0 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ole float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_one(float %a, float %b) { +; +; +; CHECK-LABEL: dup_v1i32_one: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmeq s0, s0, s1 +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan one float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_ord(float %a, float %b) { +; CHECK-LABEL: dup_v1i32_ord: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s2, s0, s1 +; CHECK-NEXT: fcmgt s0, s1, s0 +; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ord float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_ueq(float %a, float %b) { +; +; +; CHECK-LABEL: dup_v1i32_ueq: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmeq s0, s0, s1 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ueq float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_ugt(float %a, float %b) { +; +; +; CHECK-LABEL: dup_v1i32_ugt: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s0, s0, s1 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ugt float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_uge(float %a, float %b) { +; +; +; CHECK-LABEL: dup_v1i32_uge: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s0, s0, s1 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan uge float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_ult(float %a, float %b) { +; +; +; CHECK-LABEL: dup_v1i32_ult: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s0, s1, s0 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ult float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_ule(float %a, float %b) { +; +; +; CHECK-LABEL: dup_v1i32_ule: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s0, s1, s0 +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ule float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_une(float %a, float %b) { +; CHECK-LABEL: dup_v1i32_une: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmeq s0, s0, s1 +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan une float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <1 x float> @dup_v1i32_uno(float %a, float %b) { +; CHECK-LABEL: dup_v1i32_uno: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s2, s0, s1 +; CHECK-NEXT: fcmgt s0, s1, s0 +; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan uno float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <1 x i32> %vecinit.i to <1 x float> + ret <1 x float> %1 +} + +define <4 x float> @dup_v4i32(float %a, float %b) { +; CHECK-LABEL: dup_v4i32: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s0, s0, s1 +; CHECK-NEXT: dup v0.4s, v0.s[0] +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan oge float %a, %b + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <4 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <4 x i32> %vecinit.i to <4 x float> + %2 = shufflevector <4 x float> %1, <4 x float> poison, <4 x i32> zeroinitializer + ret <4 x float> %2 +} + +define <4 x float> @dup_v4i32_reversed(float %a, float %b) { +; CHECK-LABEL: dup_v4i32_reversed: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s0, s1, s0 +; CHECK-NEXT: dup v0.4s, v0.s[0] +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ogt float %b, %a + %vcmpd.i = sext i1 %0 to i32 + %vecinit.i = insertelement <4 x i32> poison, i32 %vcmpd.i, i64 0 + %1 = bitcast <4 x i32> %vecinit.i to <4 x float> + %2 = shufflevector <4 x float> %1, <4 x float> poison, <4 x i32> zeroinitializer + ret <4 x float> %2 +} + +define <2 x double> @dup_v2i64(double %a, double %b) { +; CHECK-LABEL: dup_v2i64: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt d0, d0, d1 +; CHECK-NEXT: dup v0.2d, v0.d[0] +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan ogt double %a, %b + %vcmpd.i = sext i1 %0 to i64 + %vecinit.i = insertelement <2 x i64> poison, i64 %vcmpd.i, i64 0 + %1 = bitcast <2 x i64> %vecinit.i to <2 x double> + %2 = shufflevector <2 x double> %1, <2 x double> poison, <2 x i32> zeroinitializer + ret <2 x double> %2 +} + +define <8 x half> @dup_v8i16(half %a, half %b) { +; +; +; FIXME: Could be replaced with fcmeq + dup but the type of the former is +; promoted to i32 during selection and then the optimization does not apply. +; CHECK-LABEL: dup_v8i16: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmeq s0, s0, s1 +; CHECK-NEXT: ret + entry: + %0 = fcmp nnan oeq half %a, %b + %vcmpd.i = sext i1 %0 to i16 + %vecinit.i = insertelement <8 x i16> poison, i16 %vcmpd.i, i64 0 + %1 = bitcast <8 x i16> %vecinit.i to <8 x half> + ret <8 x half> %1 +} + +define i32 @mask_i32(float %a, float %b) { +; CHECK-LABEL: mask_i32: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: csetm w0, eq +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan oeq float %a, %b + %vcmpd.i = sext i1 %0 to i32 + ret i32 %vcmpd.i +} + +; Verify that a mask is not emitted when (allOnes, allZeros) are not the +; operands for the SELECT_CC. +define i32 @bool_i32(float %a, float %b) { +; CHECK-LABEL: bool_i32: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret +entry: + %0 = fcmp nnan oeq float %a, %b + %vcmpd.i = zext i1 %0 to i32 + ret i32 %vcmpd.i +} diff --git a/llvm/test/CodeGen/AArch64/build-vector-dup-simd.ll b/llvm/test/CodeGen/AArch64/build-vector-dup-simd.ll index ac0b8e89519dd..2649215d97203 100644 --- a/llvm/test/CodeGen/AArch64/build-vector-dup-simd.ll +++ b/llvm/test/CodeGen/AArch64/build-vector-dup-simd.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFULLFP16 -; RUN: llc < %s -mtriple=aarch64 --enable-no-nans-fp-math | FileCheck %s --check-prefixes=CHECK,CHECK-NONANS ; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FULLFP16 define <1 x float> @dup_v1i32_oeq(float %a, float %b) { @@ -69,27 +68,13 @@ entry: } define <1 x float> @dup_v1i32_one(float %a, float %b) { -; CHECK-NOFULLFP16-LABEL: dup_v1i32_one: -; CHECK-NOFULLFP16: // %bb.0: // %entry -; CHECK-NOFULLFP16-NEXT: fcmgt s2, s0, s1 -; CHECK-NOFULLFP16-NEXT: fcmgt s0, s1, s0 -; CHECK-NOFULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b -; CHECK-NOFULLFP16-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-NOFULLFP16-NEXT: ret -; -; CHECK-NONANS-LABEL: dup_v1i32_one: -; CHECK-NONANS: // %bb.0: // %entry -; CHECK-NONANS-NEXT: fcmeq s0, s0, s1 -; CHECK-NONANS-NEXT: mvn v0.8b, v0.8b -; CHECK-NONANS-NEXT: ret -; -; CHECK-FULLFP16-LABEL: dup_v1i32_one: -; CHECK-FULLFP16: // %bb.0: // %entry -; CHECK-FULLFP16-NEXT: fcmgt s2, s0, s1 -; CHECK-FULLFP16-NEXT: fcmgt s0, s1, s0 -; CHECK-FULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b -; CHECK-FULLFP16-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-FULLFP16-NEXT: ret +; CHECK-LABEL: dup_v1i32_one: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s2, s0, s1 +; CHECK-NEXT: fcmgt s0, s1, s0 +; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = fcmp one float %a, %b %vcmpd.i = sext i1 %0 to i32 @@ -115,26 +100,13 @@ entry: } define <1 x float> @dup_v1i32_ueq(float %a, float %b) { -; CHECK-NOFULLFP16-LABEL: dup_v1i32_ueq: -; CHECK-NOFULLFP16: // %bb.0: // %entry -; CHECK-NOFULLFP16-NEXT: fcmgt s2, s0, s1 -; CHECK-NOFULLFP16-NEXT: fcmgt s0, s1, s0 -; CHECK-NOFULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b -; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-NOFULLFP16-NEXT: ret -; -; CHECK-NONANS-LABEL: dup_v1i32_ueq: -; CHECK-NONANS: // %bb.0: // %entry -; CHECK-NONANS-NEXT: fcmeq s0, s0, s1 -; CHECK-NONANS-NEXT: ret -; -; CHECK-FULLFP16-LABEL: dup_v1i32_ueq: -; CHECK-FULLFP16: // %bb.0: // %entry -; CHECK-FULLFP16-NEXT: fcmgt s2, s0, s1 -; CHECK-FULLFP16-NEXT: fcmgt s0, s1, s0 -; CHECK-FULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b -; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-FULLFP16-NEXT: ret +; CHECK-LABEL: dup_v1i32_ueq: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s2, s0, s1 +; CHECK-NEXT: fcmgt s0, s1, s0 +; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: ret entry: %0 = fcmp ueq float %a, %b %vcmpd.i = sext i1 %0 to i32 @@ -144,22 +116,11 @@ entry: } define <1 x float> @dup_v1i32_ugt(float %a, float %b) { -; CHECK-NOFULLFP16-LABEL: dup_v1i32_ugt: -; CHECK-NOFULLFP16: // %bb.0: // %entry -; CHECK-NOFULLFP16-NEXT: fcmge s0, s1, s0 -; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-NOFULLFP16-NEXT: ret -; -; CHECK-NONANS-LABEL: dup_v1i32_ugt: -; CHECK-NONANS: // %bb.0: // %entry -; CHECK-NONANS-NEXT: fcmgt s0, s0, s1 -; CHECK-NONANS-NEXT: ret -; -; CHECK-FULLFP16-LABEL: dup_v1i32_ugt: -; CHECK-FULLFP16: // %bb.0: // %entry -; CHECK-FULLFP16-NEXT: fcmge s0, s1, s0 -; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-FULLFP16-NEXT: ret +; CHECK-LABEL: dup_v1i32_ugt: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s0, s1, s0 +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: ret entry: %0 = fcmp ugt float %a, %b %vcmpd.i = sext i1 %0 to i32 @@ -169,22 +130,11 @@ entry: } define <1 x float> @dup_v1i32_uge(float %a, float %b) { -; CHECK-NOFULLFP16-LABEL: dup_v1i32_uge: -; CHECK-NOFULLFP16: // %bb.0: // %entry -; CHECK-NOFULLFP16-NEXT: fcmgt s0, s1, s0 -; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-NOFULLFP16-NEXT: ret -; -; CHECK-NONANS-LABEL: dup_v1i32_uge: -; CHECK-NONANS: // %bb.0: // %entry -; CHECK-NONANS-NEXT: fcmge s0, s0, s1 -; CHECK-NONANS-NEXT: ret -; -; CHECK-FULLFP16-LABEL: dup_v1i32_uge: -; CHECK-FULLFP16: // %bb.0: // %entry -; CHECK-FULLFP16-NEXT: fcmgt s0, s1, s0 -; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-FULLFP16-NEXT: ret +; CHECK-LABEL: dup_v1i32_uge: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s0, s1, s0 +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: ret entry: %0 = fcmp uge float %a, %b %vcmpd.i = sext i1 %0 to i32 @@ -194,22 +144,11 @@ entry: } define <1 x float> @dup_v1i32_ult(float %a, float %b) { -; CHECK-NOFULLFP16-LABEL: dup_v1i32_ult: -; CHECK-NOFULLFP16: // %bb.0: // %entry -; CHECK-NOFULLFP16-NEXT: fcmge s0, s0, s1 -; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-NOFULLFP16-NEXT: ret -; -; CHECK-NONANS-LABEL: dup_v1i32_ult: -; CHECK-NONANS: // %bb.0: // %entry -; CHECK-NONANS-NEXT: fcmgt s0, s1, s0 -; CHECK-NONANS-NEXT: ret -; -; CHECK-FULLFP16-LABEL: dup_v1i32_ult: -; CHECK-FULLFP16: // %bb.0: // %entry -; CHECK-FULLFP16-NEXT: fcmge s0, s0, s1 -; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-FULLFP16-NEXT: ret +; CHECK-LABEL: dup_v1i32_ult: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmge s0, s0, s1 +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: ret entry: %0 = fcmp ult float %a, %b %vcmpd.i = sext i1 %0 to i32 @@ -219,22 +158,11 @@ entry: } define <1 x float> @dup_v1i32_ule(float %a, float %b) { -; CHECK-NOFULLFP16-LABEL: dup_v1i32_ule: -; CHECK-NOFULLFP16: // %bb.0: // %entry -; CHECK-NOFULLFP16-NEXT: fcmgt s0, s0, s1 -; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-NOFULLFP16-NEXT: ret -; -; CHECK-NONANS-LABEL: dup_v1i32_ule: -; CHECK-NONANS: // %bb.0: // %entry -; CHECK-NONANS-NEXT: fcmge s0, s1, s0 -; CHECK-NONANS-NEXT: ret -; -; CHECK-FULLFP16-LABEL: dup_v1i32_ule: -; CHECK-FULLFP16: // %bb.0: // %entry -; CHECK-FULLFP16-NEXT: fcmgt s0, s0, s1 -; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b -; CHECK-FULLFP16-NEXT: ret +; CHECK-LABEL: dup_v1i32_ule: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fcmgt s0, s0, s1 +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: ret entry: %0 = fcmp ule float %a, %b %vcmpd.i = sext i1 %0 to i32 @@ -326,13 +254,6 @@ define <8 x half> @dup_v8i16(half %a, half %b) { ; CHECK-NOFULLFP16-NEXT: fcmeq s0, s0, s1 ; CHECK-NOFULLFP16-NEXT: ret ; -; CHECK-NONANS-LABEL: dup_v8i16: -; CHECK-NONANS: // %bb.0: // %entry -; CHECK-NONANS-NEXT: fcvt s1, h1 -; CHECK-NONANS-NEXT: fcvt s0, h0 -; CHECK-NONANS-NEXT: fcmeq s0, s0, s1 -; CHECK-NONANS-NEXT: ret -; ; CHECK-FULLFP16-LABEL: dup_v8i16: ; CHECK-FULLFP16: // %bb.0: // %entry ; CHECK-FULLFP16-NEXT: fcmp h0, h1 diff --git a/llvm/test/CodeGen/AArch64/cgdata-merge-preserve-entry-count.ll b/llvm/test/CodeGen/AArch64/cgdata-merge-preserve-entry-count.ll new file mode 100644 index 0000000000000..c8ff51a81376d --- /dev/null +++ b/llvm/test/CodeGen/AArch64/cgdata-merge-preserve-entry-count.ll @@ -0,0 +1,54 @@ +; This test checks that profile data is preserved after GlobalMergeFunctions: +; - Merged function (.Tgm): preserves entry count and branch weights for blocks +; - Thunk: preserves its original entry count + +; RUN: opt -mtriple=arm64-apple-darwin -S --passes=global-merge-func %s | FileCheck %s + +; CHECK: @f1.Tgm(i32 %0, ptr %1){{.*}} !prof [[PROF1:![0-9]+]] +; CHECK: br i1 %cmp, label %if.then, label %if.end, !prof [[BRANCH:![0-9]+]] +; CHECK: @f1(i32 %a){{.*}} !prof [[PROF1]] + +; CHECK: @f2.Tgm(i32 %0, ptr %1){{.*}} !prof [[PROF2:![0-9]+]] +; CHECK: br i1 %cmp, label %if.then, label %if.end, !prof [[BRANCH]] +; CHECK: @f2(i32 %a){{.*}} !prof [[PROF2]] + +; CHECK-DAG: [[PROF1]] = !{!"function_entry_count", i64 1000} +; CHECK-DAG: [[PROF2]] = !{!"function_entry_count", i64 500} +; CHECK-DAG: [[BRANCH]] = !{!"branch_weights", i32 99, i32 1} + +@g1 = external global i32, align 4 +@g2 = external global i32, align 4 + +define i32 @f1(i32 %a) !prof !0 { +entry: + %cmp = icmp sgt i32 %a, 0 + br i1 %cmp, label %if.then, label %if.end, !prof !2 + +if.then: + %0 = load volatile i32, ptr @g1, align 4 + %mul = mul nsw i32 %0, %a + br label %if.end + +if.end: + %result = phi i32 [ %mul, %if.then ], [ %a, %entry ] + ret i32 %result +} + +define i32 @f2(i32 %a) !prof !1 { +entry: + %cmp = icmp sgt i32 %a, 0 + br i1 %cmp, label %if.then, label %if.end, !prof !2 + +if.then: + %0 = load volatile i32, ptr @g2, align 4 + %mul = mul nsw i32 %0, %a + br label %if.end + +if.end: + %result = phi i32 [ %mul, %if.then ], [ %a, %entry ] + ret i32 %result +} + +!0 = !{!"function_entry_count", i64 1000} +!1 = !{!"function_entry_count", i64 500} +!2 = !{!"branch_weights", i32 99, i32 1} diff --git a/llvm/test/CodeGen/AArch64/clmul-fixed.ll b/llvm/test/CodeGen/AArch64/clmul-fixed.ll new file mode 100644 index 0000000000000..94fb2fb915951 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/clmul-fixed.ll @@ -0,0 +1,4545 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=aarch64-linux-unknown-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-NEON +; RUN: llc -mtriple=aarch64-linux-unknown-gnu %s -o - -mattr=+aes | FileCheck %s --check-prefixes=CHECK,CHECK-AES + +define <16 x i8> @clmul_v16i8_neon(<16 x i8> %x, <16 x i8> %y) { +; CHECK-LABEL: clmul_v16i8_neon: +; CHECK: // %bb.0: +; CHECK-NEXT: pmul v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret + %a = call <16 x i8> @llvm.clmul.v16i8(<16 x i8> %x, <16 x i8> %y) + ret <16 x i8> %a +} + +define <8 x i8> @clmul_v8i8_neon(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: clmul_v8i8_neon: +; CHECK: // %bb.0: +; CHECK-NEXT: pmul v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret + %a = call <8 x i8> @llvm.clmul.v8i8(<8 x i8> %x, <8 x i8> %y) + ret <8 x i8> %a +} + +define <8 x i16> @clmul_v8i16_neon(<8 x i16> %x, <8 x i16> %y) { +; CHECK-LABEL: clmul_v8i16_neon: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.8h, #2 +; CHECK-NEXT: movi v3.8h, #1 +; CHECK-NEXT: movi v4.8h, #4 +; CHECK-NEXT: movi v5.8h, #8 +; CHECK-NEXT: movi v6.8h, #16 +; CHECK-NEXT: movi v7.8h, #32 +; CHECK-NEXT: movi v16.8h, #128 +; CHECK-NEXT: movi v17.8h, #1, lsl #8 +; CHECK-NEXT: movi v18.8h, #8, lsl #8 +; CHECK-NEXT: movi v19.8h, #16, lsl #8 +; CHECK-NEXT: movi v20.8h, #64 +; CHECK-NEXT: movi v21.8h, #2, lsl #8 +; CHECK-NEXT: and v2.16b, v1.16b, v2.16b +; CHECK-NEXT: and v3.16b, v1.16b, v3.16b +; CHECK-NEXT: and v4.16b, v1.16b, v4.16b +; CHECK-NEXT: and v5.16b, v1.16b, v5.16b +; CHECK-NEXT: movi v22.8h, #32, lsl #8 +; CHECK-NEXT: and v6.16b, v1.16b, v6.16b +; CHECK-NEXT: and v7.16b, v1.16b, v7.16b +; CHECK-NEXT: and v16.16b, v1.16b, v16.16b +; CHECK-NEXT: and v17.16b, v1.16b, v17.16b +; CHECK-NEXT: and v18.16b, v1.16b, v18.16b +; CHECK-NEXT: and v19.16b, v1.16b, v19.16b +; CHECK-NEXT: mul v2.8h, v0.8h, v2.8h +; CHECK-NEXT: mul v3.8h, v0.8h, v3.8h +; CHECK-NEXT: mul v4.8h, v0.8h, v4.8h +; CHECK-NEXT: mul v5.8h, v0.8h, v5.8h +; CHECK-NEXT: and v20.16b, v1.16b, v20.16b +; CHECK-NEXT: movi v23.8h, #4, lsl #8 +; CHECK-NEXT: movi v24.8h, #64, lsl #8 +; CHECK-NEXT: mul v6.8h, v0.8h, v6.8h +; CHECK-NEXT: mul v7.8h, v0.8h, v7.8h +; CHECK-NEXT: mul v16.8h, v0.8h, v16.8h +; CHECK-NEXT: mul v17.8h, v0.8h, v17.8h +; CHECK-NEXT: and v21.16b, v1.16b, v21.16b +; CHECK-NEXT: mul v18.8h, v0.8h, v18.8h +; CHECK-NEXT: mul v19.8h, v0.8h, v19.8h +; CHECK-NEXT: and v22.16b, v1.16b, v22.16b +; CHECK-NEXT: eor v2.16b, v3.16b, v2.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v5.16b +; CHECK-NEXT: mul v4.8h, v0.8h, v20.8h +; CHECK-NEXT: movi v20.8h, #128, lsl #8 +; CHECK-NEXT: mul v5.8h, v0.8h, v21.8h +; CHECK-NEXT: and v21.16b, v1.16b, v23.16b +; CHECK-NEXT: and v23.16b, v1.16b, v24.16b +; CHECK-NEXT: mul v22.8h, v0.8h, v22.8h +; CHECK-NEXT: eor v6.16b, v6.16b, v7.16b +; CHECK-NEXT: eor v7.16b, v16.16b, v17.16b +; CHECK-NEXT: eor v16.16b, v18.16b, v19.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: and v1.16b, v1.16b, v20.16b +; CHECK-NEXT: mul v3.8h, v0.8h, v21.8h +; CHECK-NEXT: mul v17.8h, v0.8h, v23.8h +; CHECK-NEXT: eor v4.16b, v6.16b, v4.16b +; CHECK-NEXT: eor v5.16b, v7.16b, v5.16b +; CHECK-NEXT: eor v6.16b, v16.16b, v22.16b +; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h +; CHECK-NEXT: eor v1.16b, v2.16b, v4.16b +; CHECK-NEXT: eor v2.16b, v5.16b, v3.16b +; CHECK-NEXT: eor v3.16b, v6.16b, v17.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v2.16b +; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b +; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b +; CHECK-NEXT: ret + %a = call <8 x i16> @llvm.clmul.v8i16(<8 x i16> %x, <8 x i16> %y) + ret <8 x i16> %a +} + +define <4 x i16> @clmul_v4i16_neon(<4 x i16> %x, <4 x i16> %y) { +; CHECK-LABEL: clmul_v4i16_neon: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.4h, #2 +; CHECK-NEXT: movi v3.4h, #1 +; CHECK-NEXT: movi v4.4h, #4 +; CHECK-NEXT: movi v5.4h, #8 +; CHECK-NEXT: movi v6.4h, #16 +; CHECK-NEXT: movi v7.4h, #32 +; CHECK-NEXT: movi v16.4h, #128 +; CHECK-NEXT: movi v17.4h, #1, lsl #8 +; CHECK-NEXT: movi v18.4h, #8, lsl #8 +; CHECK-NEXT: movi v19.4h, #16, lsl #8 +; CHECK-NEXT: movi v20.4h, #64 +; CHECK-NEXT: movi v21.4h, #2, lsl #8 +; CHECK-NEXT: and v2.8b, v1.8b, v2.8b +; CHECK-NEXT: and v3.8b, v1.8b, v3.8b +; CHECK-NEXT: and v4.8b, v1.8b, v4.8b +; CHECK-NEXT: and v5.8b, v1.8b, v5.8b +; CHECK-NEXT: movi v22.4h, #32, lsl #8 +; CHECK-NEXT: and v6.8b, v1.8b, v6.8b +; CHECK-NEXT: and v7.8b, v1.8b, v7.8b +; CHECK-NEXT: and v16.8b, v1.8b, v16.8b +; CHECK-NEXT: and v17.8b, v1.8b, v17.8b +; CHECK-NEXT: and v18.8b, v1.8b, v18.8b +; CHECK-NEXT: and v19.8b, v1.8b, v19.8b +; CHECK-NEXT: mul v2.4h, v0.4h, v2.4h +; CHECK-NEXT: mul v3.4h, v0.4h, v3.4h +; CHECK-NEXT: mul v4.4h, v0.4h, v4.4h +; CHECK-NEXT: mul v5.4h, v0.4h, v5.4h +; CHECK-NEXT: and v20.8b, v1.8b, v20.8b +; CHECK-NEXT: movi v23.4h, #4, lsl #8 +; CHECK-NEXT: movi v24.4h, #64, lsl #8 +; CHECK-NEXT: mul v6.4h, v0.4h, v6.4h +; CHECK-NEXT: mul v7.4h, v0.4h, v7.4h +; CHECK-NEXT: mul v16.4h, v0.4h, v16.4h +; CHECK-NEXT: mul v17.4h, v0.4h, v17.4h +; CHECK-NEXT: and v21.8b, v1.8b, v21.8b +; CHECK-NEXT: mul v18.4h, v0.4h, v18.4h +; CHECK-NEXT: mul v19.4h, v0.4h, v19.4h +; CHECK-NEXT: and v22.8b, v1.8b, v22.8b +; CHECK-NEXT: eor v2.8b, v3.8b, v2.8b +; CHECK-NEXT: eor v3.8b, v4.8b, v5.8b +; CHECK-NEXT: mul v4.4h, v0.4h, v20.4h +; CHECK-NEXT: movi v20.4h, #128, lsl #8 +; CHECK-NEXT: mul v5.4h, v0.4h, v21.4h +; CHECK-NEXT: and v21.8b, v1.8b, v23.8b +; CHECK-NEXT: and v23.8b, v1.8b, v24.8b +; CHECK-NEXT: mul v22.4h, v0.4h, v22.4h +; CHECK-NEXT: eor v6.8b, v6.8b, v7.8b +; CHECK-NEXT: eor v7.8b, v16.8b, v17.8b +; CHECK-NEXT: eor v16.8b, v18.8b, v19.8b +; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b +; CHECK-NEXT: and v1.8b, v1.8b, v20.8b +; CHECK-NEXT: mul v3.4h, v0.4h, v21.4h +; CHECK-NEXT: mul v17.4h, v0.4h, v23.4h +; CHECK-NEXT: eor v4.8b, v6.8b, v4.8b +; CHECK-NEXT: eor v5.8b, v7.8b, v5.8b +; CHECK-NEXT: eor v6.8b, v16.8b, v22.8b +; CHECK-NEXT: mul v0.4h, v0.4h, v1.4h +; CHECK-NEXT: eor v1.8b, v2.8b, v4.8b +; CHECK-NEXT: eor v2.8b, v5.8b, v3.8b +; CHECK-NEXT: eor v3.8b, v6.8b, v17.8b +; CHECK-NEXT: eor v1.8b, v1.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v3.8b, v0.8b +; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b +; CHECK-NEXT: ret + %a = call <4 x i16> @llvm.clmul.v4i16(<4 x i16> %x, <4 x i16> %y) + ret <4 x i16> %a +} + +define <4 x i32> @clmul_v4i32_neon(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: clmul_v4i32_neon: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.4s, #2 +; CHECK-NEXT: movi v3.4s, #1 +; CHECK-NEXT: movi v4.4s, #4 +; CHECK-NEXT: movi v5.4s, #8 +; CHECK-NEXT: movi v6.4s, #16 +; CHECK-NEXT: movi v7.4s, #32 +; CHECK-NEXT: movi v16.4s, #64 +; CHECK-NEXT: movi v17.4s, #128 +; CHECK-NEXT: movi v18.4s, #1, lsl #8 +; CHECK-NEXT: movi v19.4s, #2, lsl #8 +; CHECK-NEXT: movi v20.4s, #8, lsl #8 +; CHECK-NEXT: movi v21.4s, #128, lsl #16 +; CHECK-NEXT: and v2.16b, v1.16b, v2.16b +; CHECK-NEXT: and v3.16b, v1.16b, v3.16b +; CHECK-NEXT: and v4.16b, v1.16b, v4.16b +; CHECK-NEXT: and v5.16b, v1.16b, v5.16b +; CHECK-NEXT: and v6.16b, v1.16b, v6.16b +; CHECK-NEXT: and v7.16b, v1.16b, v7.16b +; CHECK-NEXT: and v16.16b, v1.16b, v16.16b +; CHECK-NEXT: and v17.16b, v1.16b, v17.16b +; CHECK-NEXT: and v18.16b, v1.16b, v18.16b +; CHECK-NEXT: mul v2.4s, v0.4s, v2.4s +; CHECK-NEXT: mul v3.4s, v0.4s, v3.4s +; CHECK-NEXT: mul v4.4s, v0.4s, v4.4s +; CHECK-NEXT: mul v5.4s, v0.4s, v5.4s +; CHECK-NEXT: mul v6.4s, v0.4s, v6.4s +; CHECK-NEXT: mul v7.4s, v0.4s, v7.4s +; CHECK-NEXT: and v21.16b, v1.16b, v21.16b +; CHECK-NEXT: movi v22.4s, #8, lsl #16 +; CHECK-NEXT: movi v23.4s, #2, lsl #24 +; CHECK-NEXT: movi v25.4s, #4, lsl #24 +; CHECK-NEXT: movi v24.4s, #32, lsl #16 +; CHECK-NEXT: movi v26.4s, #8, lsl #24 +; CHECK-NEXT: eor v2.16b, v3.16b, v2.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v5.16b +; CHECK-NEXT: movi v4.4s, #16, lsl #8 +; CHECK-NEXT: mul v5.4s, v0.4s, v16.4s +; CHECK-NEXT: mul v16.4s, v0.4s, v17.4s +; CHECK-NEXT: mul v17.4s, v0.4s, v18.4s +; CHECK-NEXT: eor v6.16b, v6.16b, v7.16b +; CHECK-NEXT: and v7.16b, v1.16b, v19.16b +; CHECK-NEXT: movi v19.4s, #32, lsl #8 +; CHECK-NEXT: and v18.16b, v1.16b, v20.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: movi v20.4s, #64, lsl #8 +; CHECK-NEXT: mul v21.4s, v0.4s, v21.4s +; CHECK-NEXT: and v3.16b, v1.16b, v4.16b +; CHECK-NEXT: eor v5.16b, v6.16b, v5.16b +; CHECK-NEXT: movi v4.4s, #1, lsl #16 +; CHECK-NEXT: eor v6.16b, v16.16b, v17.16b +; CHECK-NEXT: movi v16.4s, #2, lsl #16 +; CHECK-NEXT: mul v7.4s, v0.4s, v7.4s +; CHECK-NEXT: mul v18.4s, v0.4s, v18.4s +; CHECK-NEXT: and v19.16b, v1.16b, v19.16b +; CHECK-NEXT: movi v17.4s, #4, lsl #8 +; CHECK-NEXT: mul v3.4s, v0.4s, v3.4s +; CHECK-NEXT: eor v2.16b, v2.16b, v5.16b +; CHECK-NEXT: and v23.16b, v1.16b, v23.16b +; CHECK-NEXT: and v4.16b, v1.16b, v4.16b +; CHECK-NEXT: and v5.16b, v1.16b, v16.16b +; CHECK-NEXT: movi v16.4s, #64, lsl #16 +; CHECK-NEXT: eor v6.16b, v6.16b, v7.16b +; CHECK-NEXT: mul v7.4s, v0.4s, v19.4s +; CHECK-NEXT: movi v19.4s, #4, lsl #16 +; CHECK-NEXT: and v17.16b, v1.16b, v17.16b +; CHECK-NEXT: eor v3.16b, v18.16b, v3.16b +; CHECK-NEXT: and v18.16b, v1.16b, v20.16b +; CHECK-NEXT: movi v20.4s, #1, lsl #24 +; CHECK-NEXT: mul v4.4s, v0.4s, v4.4s +; CHECK-NEXT: mul v5.4s, v0.4s, v5.4s +; CHECK-NEXT: and v16.16b, v1.16b, v16.16b +; CHECK-NEXT: mul v17.4s, v0.4s, v17.4s +; CHECK-NEXT: eor v3.16b, v3.16b, v7.16b +; CHECK-NEXT: and v7.16b, v1.16b, v19.16b +; CHECK-NEXT: mul v18.4s, v0.4s, v18.4s +; CHECK-NEXT: and v20.16b, v1.16b, v20.16b +; CHECK-NEXT: movi v19.4s, #128, lsl #8 +; CHECK-NEXT: mul v16.4s, v0.4s, v16.4s +; CHECK-NEXT: eor v4.16b, v4.16b, v5.16b +; CHECK-NEXT: mul v5.4s, v0.4s, v7.4s +; CHECK-NEXT: and v7.16b, v1.16b, v22.16b +; CHECK-NEXT: movi v22.4s, #16, lsl #16 +; CHECK-NEXT: mul v20.4s, v0.4s, v20.4s +; CHECK-NEXT: eor v6.16b, v6.16b, v17.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v18.16b +; CHECK-NEXT: and v17.16b, v1.16b, v19.16b +; CHECK-NEXT: mul v18.4s, v0.4s, v23.4s +; CHECK-NEXT: and v19.16b, v1.16b, v25.16b +; CHECK-NEXT: eor v16.16b, v16.16b, v21.16b +; CHECK-NEXT: and v21.16b, v1.16b, v24.16b +; CHECK-NEXT: movi v23.4s, #32, lsl #24 +; CHECK-NEXT: eor v4.16b, v4.16b, v5.16b +; CHECK-NEXT: mul v5.4s, v0.4s, v7.4s +; CHECK-NEXT: and v7.16b, v1.16b, v22.16b +; CHECK-NEXT: movi v22.4s, #16, lsl #24 +; CHECK-NEXT: movi v24.4s, #64, lsl #24 +; CHECK-NEXT: mul v17.4s, v0.4s, v17.4s +; CHECK-NEXT: eor v16.16b, v16.16b, v20.16b +; CHECK-NEXT: and v20.16b, v1.16b, v26.16b +; CHECK-NEXT: mul v19.4s, v0.4s, v19.4s +; CHECK-NEXT: mul v7.4s, v0.4s, v7.4s +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: mul v6.4s, v0.4s, v21.4s +; CHECK-NEXT: eor v4.16b, v4.16b, v5.16b +; CHECK-NEXT: and v21.16b, v1.16b, v23.16b +; CHECK-NEXT: eor v5.16b, v16.16b, v18.16b +; CHECK-NEXT: movi v16.4s, #128, lsl #24 +; CHECK-NEXT: mul v18.4s, v0.4s, v20.4s +; CHECK-NEXT: and v20.16b, v1.16b, v22.16b +; CHECK-NEXT: and v22.16b, v1.16b, v24.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v17.16b +; CHECK-NEXT: eor v4.16b, v4.16b, v7.16b +; CHECK-NEXT: eor v5.16b, v5.16b, v19.16b +; CHECK-NEXT: and v1.16b, v1.16b, v16.16b +; CHECK-NEXT: mul v7.4s, v0.4s, v20.4s +; CHECK-NEXT: mul v16.4s, v0.4s, v21.4s +; CHECK-NEXT: mul v17.4s, v0.4s, v22.4s +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v6.16b +; CHECK-NEXT: eor v4.16b, v5.16b, v18.16b +; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s +; CHECK-NEXT: eor v1.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v2.16b, v4.16b, v7.16b +; CHECK-NEXT: eor v3.16b, v16.16b, v17.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v2.16b +; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b +; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b +; CHECK-NEXT: ret + %a = call <4 x i32> @llvm.clmul.v4i32(<4 x i32> %x, <4 x i32> %y) + ret <4 x i32> %a +} + +define <2 x i32> @clmul_v2i32_neon(<2 x i32> %x, <2 x i32> %y) { +; CHECK-LABEL: clmul_v2i32_neon: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.2s, #2 +; CHECK-NEXT: movi v3.2s, #1 +; CHECK-NEXT: movi v4.2s, #4 +; CHECK-NEXT: movi v5.2s, #8 +; CHECK-NEXT: movi v6.2s, #16 +; CHECK-NEXT: movi v7.2s, #32 +; CHECK-NEXT: movi v16.2s, #64 +; CHECK-NEXT: movi v17.2s, #128 +; CHECK-NEXT: movi v18.2s, #1, lsl #8 +; CHECK-NEXT: movi v19.2s, #2, lsl #8 +; CHECK-NEXT: movi v20.2s, #8, lsl #8 +; CHECK-NEXT: movi v21.2s, #128, lsl #16 +; CHECK-NEXT: and v2.8b, v1.8b, v2.8b +; CHECK-NEXT: and v3.8b, v1.8b, v3.8b +; CHECK-NEXT: and v4.8b, v1.8b, v4.8b +; CHECK-NEXT: and v5.8b, v1.8b, v5.8b +; CHECK-NEXT: and v6.8b, v1.8b, v6.8b +; CHECK-NEXT: and v7.8b, v1.8b, v7.8b +; CHECK-NEXT: and v16.8b, v1.8b, v16.8b +; CHECK-NEXT: and v17.8b, v1.8b, v17.8b +; CHECK-NEXT: and v18.8b, v1.8b, v18.8b +; CHECK-NEXT: mul v2.2s, v0.2s, v2.2s +; CHECK-NEXT: mul v3.2s, v0.2s, v3.2s +; CHECK-NEXT: mul v4.2s, v0.2s, v4.2s +; CHECK-NEXT: mul v5.2s, v0.2s, v5.2s +; CHECK-NEXT: mul v6.2s, v0.2s, v6.2s +; CHECK-NEXT: mul v7.2s, v0.2s, v7.2s +; CHECK-NEXT: and v21.8b, v1.8b, v21.8b +; CHECK-NEXT: movi v22.2s, #8, lsl #16 +; CHECK-NEXT: movi v23.2s, #2, lsl #24 +; CHECK-NEXT: movi v25.2s, #4, lsl #24 +; CHECK-NEXT: movi v24.2s, #32, lsl #16 +; CHECK-NEXT: movi v26.2s, #8, lsl #24 +; CHECK-NEXT: eor v2.8b, v3.8b, v2.8b +; CHECK-NEXT: eor v3.8b, v4.8b, v5.8b +; CHECK-NEXT: movi v4.2s, #16, lsl #8 +; CHECK-NEXT: mul v5.2s, v0.2s, v16.2s +; CHECK-NEXT: mul v16.2s, v0.2s, v17.2s +; CHECK-NEXT: mul v17.2s, v0.2s, v18.2s +; CHECK-NEXT: eor v6.8b, v6.8b, v7.8b +; CHECK-NEXT: and v7.8b, v1.8b, v19.8b +; CHECK-NEXT: movi v19.2s, #32, lsl #8 +; CHECK-NEXT: and v18.8b, v1.8b, v20.8b +; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b +; CHECK-NEXT: movi v20.2s, #64, lsl #8 +; CHECK-NEXT: mul v21.2s, v0.2s, v21.2s +; CHECK-NEXT: and v3.8b, v1.8b, v4.8b +; CHECK-NEXT: eor v5.8b, v6.8b, v5.8b +; CHECK-NEXT: movi v4.2s, #1, lsl #16 +; CHECK-NEXT: eor v6.8b, v16.8b, v17.8b +; CHECK-NEXT: movi v16.2s, #2, lsl #16 +; CHECK-NEXT: mul v7.2s, v0.2s, v7.2s +; CHECK-NEXT: mul v18.2s, v0.2s, v18.2s +; CHECK-NEXT: and v19.8b, v1.8b, v19.8b +; CHECK-NEXT: movi v17.2s, #4, lsl #8 +; CHECK-NEXT: mul v3.2s, v0.2s, v3.2s +; CHECK-NEXT: eor v2.8b, v2.8b, v5.8b +; CHECK-NEXT: and v23.8b, v1.8b, v23.8b +; CHECK-NEXT: and v4.8b, v1.8b, v4.8b +; CHECK-NEXT: and v5.8b, v1.8b, v16.8b +; CHECK-NEXT: movi v16.2s, #64, lsl #16 +; CHECK-NEXT: eor v6.8b, v6.8b, v7.8b +; CHECK-NEXT: mul v7.2s, v0.2s, v19.2s +; CHECK-NEXT: movi v19.2s, #4, lsl #16 +; CHECK-NEXT: and v17.8b, v1.8b, v17.8b +; CHECK-NEXT: eor v3.8b, v18.8b, v3.8b +; CHECK-NEXT: and v18.8b, v1.8b, v20.8b +; CHECK-NEXT: movi v20.2s, #1, lsl #24 +; CHECK-NEXT: mul v4.2s, v0.2s, v4.2s +; CHECK-NEXT: mul v5.2s, v0.2s, v5.2s +; CHECK-NEXT: and v16.8b, v1.8b, v16.8b +; CHECK-NEXT: mul v17.2s, v0.2s, v17.2s +; CHECK-NEXT: eor v3.8b, v3.8b, v7.8b +; CHECK-NEXT: and v7.8b, v1.8b, v19.8b +; CHECK-NEXT: mul v18.2s, v0.2s, v18.2s +; CHECK-NEXT: and v20.8b, v1.8b, v20.8b +; CHECK-NEXT: movi v19.2s, #128, lsl #8 +; CHECK-NEXT: mul v16.2s, v0.2s, v16.2s +; CHECK-NEXT: eor v4.8b, v4.8b, v5.8b +; CHECK-NEXT: mul v5.2s, v0.2s, v7.2s +; CHECK-NEXT: and v7.8b, v1.8b, v22.8b +; CHECK-NEXT: movi v22.2s, #16, lsl #16 +; CHECK-NEXT: mul v20.2s, v0.2s, v20.2s +; CHECK-NEXT: eor v6.8b, v6.8b, v17.8b +; CHECK-NEXT: eor v3.8b, v3.8b, v18.8b +; CHECK-NEXT: and v17.8b, v1.8b, v19.8b +; CHECK-NEXT: mul v18.2s, v0.2s, v23.2s +; CHECK-NEXT: and v19.8b, v1.8b, v25.8b +; CHECK-NEXT: eor v16.8b, v16.8b, v21.8b +; CHECK-NEXT: and v21.8b, v1.8b, v24.8b +; CHECK-NEXT: movi v23.2s, #32, lsl #24 +; CHECK-NEXT: eor v4.8b, v4.8b, v5.8b +; CHECK-NEXT: mul v5.2s, v0.2s, v7.2s +; CHECK-NEXT: and v7.8b, v1.8b, v22.8b +; CHECK-NEXT: movi v22.2s, #16, lsl #24 +; CHECK-NEXT: movi v24.2s, #64, lsl #24 +; CHECK-NEXT: mul v17.2s, v0.2s, v17.2s +; CHECK-NEXT: eor v16.8b, v16.8b, v20.8b +; CHECK-NEXT: and v20.8b, v1.8b, v26.8b +; CHECK-NEXT: mul v19.2s, v0.2s, v19.2s +; CHECK-NEXT: mul v7.2s, v0.2s, v7.2s +; CHECK-NEXT: eor v2.8b, v2.8b, v6.8b +; CHECK-NEXT: mul v6.2s, v0.2s, v21.2s +; CHECK-NEXT: eor v4.8b, v4.8b, v5.8b +; CHECK-NEXT: and v21.8b, v1.8b, v23.8b +; CHECK-NEXT: eor v5.8b, v16.8b, v18.8b +; CHECK-NEXT: movi v16.2s, #128, lsl #24 +; CHECK-NEXT: mul v18.2s, v0.2s, v20.2s +; CHECK-NEXT: and v20.8b, v1.8b, v22.8b +; CHECK-NEXT: and v22.8b, v1.8b, v24.8b +; CHECK-NEXT: eor v3.8b, v3.8b, v17.8b +; CHECK-NEXT: eor v4.8b, v4.8b, v7.8b +; CHECK-NEXT: eor v5.8b, v5.8b, v19.8b +; CHECK-NEXT: and v1.8b, v1.8b, v16.8b +; CHECK-NEXT: mul v7.2s, v0.2s, v20.2s +; CHECK-NEXT: mul v16.2s, v0.2s, v21.2s +; CHECK-NEXT: mul v17.2s, v0.2s, v22.2s +; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b +; CHECK-NEXT: eor v3.8b, v4.8b, v6.8b +; CHECK-NEXT: eor v4.8b, v5.8b, v18.8b +; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s +; CHECK-NEXT: eor v1.8b, v2.8b, v3.8b +; CHECK-NEXT: eor v2.8b, v4.8b, v7.8b +; CHECK-NEXT: eor v3.8b, v16.8b, v17.8b +; CHECK-NEXT: eor v1.8b, v1.8b, v2.8b +; CHECK-NEXT: eor v0.8b, v3.8b, v0.8b +; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b +; CHECK-NEXT: ret + %a = call <2 x i32> @llvm.clmul.v2i32(<2 x i32> %x, <2 x i32> %y) + ret <2 x i32> %a +} + +; TODO: Fix +; define <2 x i64> @clmul_v2i64_neon(<2 x i64> %x, <2 x i64> %y) { +; %a = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> %x, <2 x i64> %y) +; ret <2 x i64> %a +; } +; TODO: Fix +; define <1 x i64> @clmul_v1i64_neon(<1 x i64> %x, <1 x i64> %y) { +; %a = call <1 x i64> @llvm.clmul.v1i64(<1 x i64> %x, <1 x i64> %y) +; ret <1 x i64> %a +; } + +define <1 x i128> @clmul_v1i128_neon(<1 x i128> %x, <1 x i128> %y) { +; CHECK-LABEL: clmul_v1i128_neon: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x29, x30, [sp, #-96]! // 16-byte Folded Spill +; CHECK-NEXT: stp x28, x27, [sp, #16] // 16-byte Folded Spill +; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill +; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill +; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill +; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill +; CHECK-NEXT: sub sp, sp, #1952 +; CHECK-NEXT: .cfi_def_cfa_offset 2048 +; CHECK-NEXT: .cfi_offset w19, -8 +; CHECK-NEXT: .cfi_offset w20, -16 +; CHECK-NEXT: .cfi_offset w21, -24 +; CHECK-NEXT: .cfi_offset w22, -32 +; CHECK-NEXT: .cfi_offset w23, -40 +; CHECK-NEXT: .cfi_offset w24, -48 +; CHECK-NEXT: .cfi_offset w25, -56 +; CHECK-NEXT: .cfi_offset w26, -64 +; CHECK-NEXT: .cfi_offset w27, -72 +; CHECK-NEXT: .cfi_offset w28, -80 +; CHECK-NEXT: .cfi_offset w30, -88 +; CHECK-NEXT: .cfi_offset w29, -96 +; CHECK-NEXT: rbit x8, x2 +; CHECK-NEXT: rbit x9, x0 +; CHECK-NEXT: and x7, x2, #0x2 +; CHECK-NEXT: and x18, x2, #0x1 +; CHECK-NEXT: and x4, x2, #0x4 +; CHECK-NEXT: and x5, x2, #0x10 +; CHECK-NEXT: and x10, x8, #0x2 +; CHECK-NEXT: and x6, x2, #0x80 +; CHECK-NEXT: and x17, x2, #0x800 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1944] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1936] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1928] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1920] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1912] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1904] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1888] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1896] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x100 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1880] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x200 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1864] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x400 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1872] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x800 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1856] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1832] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x2000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1840] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1824] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1848] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1816] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1792] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1784] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1808] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x100000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1776] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x200000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1800] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x400000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1768] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x800000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1728] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1760] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x2000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1720] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1752] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1736] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1744] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1696] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1656] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1688] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x100000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1672] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x200000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1680] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x400000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1664] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x800000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1704] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1712] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x2000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1640] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1608] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1584] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1632] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1600] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1616] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1592] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x100000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1624] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x200000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1648] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x400000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1568] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x800000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1520] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1536] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x2000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1512] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1560] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1504] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1552] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1528] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1576] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1544] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x100000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1480] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x200000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1448] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x400000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1472] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x800000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1456] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1000000000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #1488] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x2000000000000000 +; CHECK-NEXT: and x8, x8, #0x4000000000000000 +; CHECK-NEXT: mul x8, x9, x8 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x8, [sp, #1496] // 8-byte Spill +; CHECK-NEXT: mul x8, x1, x7 +; CHECK-NEXT: str x10, [sp, #1464] // 8-byte Spill +; CHECK-NEXT: str x8, [sp, #1032] // 8-byte Spill +; CHECK-NEXT: mul x8, x1, x18 +; CHECK-NEXT: mul x18, x0, x18 +; CHECK-NEXT: str x8, [sp, #1008] // 8-byte Spill +; CHECK-NEXT: mul x8, x1, x4 +; CHECK-NEXT: str x18, [sp, #1128] // 8-byte Spill +; CHECK-NEXT: mul x18, x0, x4 +; CHECK-NEXT: str x8, [sp, #992] // 8-byte Spill +; CHECK-NEXT: and x8, x2, #0x8 +; CHECK-NEXT: mul x9, x1, x8 +; CHECK-NEXT: str x18, [sp, #1120] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x9, [sp, #976] // 8-byte Spill +; CHECK-NEXT: mul x9, x1, x5 +; CHECK-NEXT: str x8, [sp, #1112] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x5 +; CHECK-NEXT: str x9, [sp, #952] // 8-byte Spill +; CHECK-NEXT: and x9, x2, #0x20 +; CHECK-NEXT: mul x10, x1, x9 +; CHECK-NEXT: str x8, [sp, #1096] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x9 +; CHECK-NEXT: ldr x9, [sp, #1008] // 8-byte Reload +; CHECK-NEXT: str x10, [sp, #928] // 8-byte Spill +; CHECK-NEXT: and x10, x2, #0x40 +; CHECK-NEXT: mul x11, x1, x10 +; CHECK-NEXT: str x8, [sp, #1072] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x10 +; CHECK-NEXT: ldr x10, [sp, #976] // 8-byte Reload +; CHECK-NEXT: str x11, [sp, #944] // 8-byte Spill +; CHECK-NEXT: mul x11, x1, x6 +; CHECK-NEXT: str x8, [sp, #1104] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x6 +; CHECK-NEXT: str x11, [sp, #936] // 8-byte Spill +; CHECK-NEXT: and x11, x2, #0x100 +; CHECK-NEXT: mul x12, x1, x11 +; CHECK-NEXT: str x8, [sp, #1064] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x11 +; CHECK-NEXT: ldr x11, [sp, #928] // 8-byte Reload +; CHECK-NEXT: str x12, [sp, #920] // 8-byte Spill +; CHECK-NEXT: and x12, x2, #0x200 +; CHECK-NEXT: mul x13, x1, x12 +; CHECK-NEXT: str x8, [sp, #1048] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x12 +; CHECK-NEXT: str x13, [sp, #968] // 8-byte Spill +; CHECK-NEXT: and x13, x2, #0x400 +; CHECK-NEXT: mul x14, x1, x13 +; CHECK-NEXT: str x8, [sp, #1040] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x13 +; CHECK-NEXT: str x14, [sp, #960] // 8-byte Spill +; CHECK-NEXT: mul x14, x1, x17 +; CHECK-NEXT: str x8, [sp, #1088] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x17 +; CHECK-NEXT: str x14, [sp, #848] // 8-byte Spill +; CHECK-NEXT: and x14, x2, #0x1000 +; CHECK-NEXT: mul x15, x1, x14 +; CHECK-NEXT: str x8, [sp, #1000] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x14 +; CHECK-NEXT: str x15, [sp, #824] // 8-byte Spill +; CHECK-NEXT: and x15, x2, #0x2000 +; CHECK-NEXT: mul x16, x1, x15 +; CHECK-NEXT: ldr x12, [sp, #824] // 8-byte Reload +; CHECK-NEXT: str x8, [sp, #984] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x15 +; CHECK-NEXT: str x16, [sp, #896] // 8-byte Spill +; CHECK-NEXT: and x16, x2, #0x4000 +; CHECK-NEXT: mul x19, x1, x16 +; CHECK-NEXT: str x8, [sp, #1024] // 8-byte Spill +; CHECK-NEXT: mul x8, x0, x16 +; CHECK-NEXT: str x19, [sp, #888] // 8-byte Spill +; CHECK-NEXT: and x19, x2, #0x8000 +; CHECK-NEXT: mul x20, x1, x19 +; CHECK-NEXT: str x8, [sp, #1016] // 8-byte Spill +; CHECK-NEXT: ldr x8, [sp, #1032] // 8-byte Reload +; CHECK-NEXT: eor x8, x9, x8 +; CHECK-NEXT: ldr x9, [sp, #992] // 8-byte Reload +; CHECK-NEXT: str x20, [sp, #904] // 8-byte Spill +; CHECK-NEXT: and x20, x2, #0x10000 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: mul x21, x1, x20 +; CHECK-NEXT: ldr x10, [sp, #952] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #944] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: mul x11, x0, x19 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: ldr x10, [sp, #936] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #968] // 8-byte Reload +; CHECK-NEXT: str x21, [sp, #880] // 8-byte Spill +; CHECK-NEXT: and x21, x2, #0x20000 +; CHECK-NEXT: mul x22, x1, x21 +; CHECK-NEXT: str x11, [sp, #1032] // 8-byte Spill +; CHECK-NEXT: ldr x11, [sp, #920] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #848] // 8-byte Reload +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: ldr x10, [sp, #896] // 8-byte Reload +; CHECK-NEXT: str x22, [sp, #840] // 8-byte Spill +; CHECK-NEXT: and x22, x2, #0x40000 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x23, x1, x22 +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: ldr x11, [sp, #960] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: ldr x11, [sp, #888] // 8-byte Reload +; CHECK-NEXT: mul x12, x0, x20 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #904] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: mul x11, x0, x21 +; CHECK-NEXT: str x23, [sp, #832] // 8-byte Spill +; CHECK-NEXT: and x23, x2, #0x80000 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: mul x24, x1, x23 +; CHECK-NEXT: ldr x10, [sp, #880] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: str x12, [sp, #1008] // 8-byte Spill +; CHECK-NEXT: str x11, [sp, #992] // 8-byte Spill +; CHECK-NEXT: ldr x11, [sp, #840] // 8-byte Reload +; CHECK-NEXT: str x24, [sp, #872] // 8-byte Spill +; CHECK-NEXT: and x24, x2, #0x100000 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: mul x25, x1, x24 +; CHECK-NEXT: ldr x11, [sp, #832] // 8-byte Reload +; CHECK-NEXT: ldr x9, [sp, #872] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: str x25, [sp, #864] // 8-byte Spill +; CHECK-NEXT: and x25, x2, #0x200000 +; CHECK-NEXT: mul x26, x1, x25 +; CHECK-NEXT: str x26, [sp, #912] // 8-byte Spill +; CHECK-NEXT: and x26, x2, #0x400000 +; CHECK-NEXT: mul x27, x1, x26 +; CHECK-NEXT: str x27, [sp, #760] // 8-byte Spill +; CHECK-NEXT: and x27, x2, #0x800000 +; CHECK-NEXT: mul x28, x1, x27 +; CHECK-NEXT: ldr x11, [sp, #760] // 8-byte Reload +; CHECK-NEXT: str x28, [sp, #736] // 8-byte Spill +; CHECK-NEXT: and x28, x2, #0x1000000 +; CHECK-NEXT: mul x29, x1, x28 +; CHECK-NEXT: ldr x12, [sp, #736] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x12, x0, x22 +; CHECK-NEXT: str x29, [sp, #784] // 8-byte Spill +; CHECK-NEXT: and x29, x2, #0x2000000 +; CHECK-NEXT: mul x30, x1, x29 +; CHECK-NEXT: ldr x10, [sp, #784] // 8-byte Reload +; CHECK-NEXT: str x12, [sp, #976] // 8-byte Spill +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: ldr x11, [sp, #864] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: str x30, [sp, #776] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x4000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: ldr x11, [sp, #776] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: mul x11, x0, x23 +; CHECK-NEXT: str x30, [sp, #800] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x4000000 +; CHECK-NEXT: str x30, [sp, #1144] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x8000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x11, [sp, #968] // 8-byte Spill +; CHECK-NEXT: ldr x11, [sp, #912] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: ldr x11, [sp, #800] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: str x30, [sp, #792] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x8000000 +; CHECK-NEXT: str x30, [sp, #1152] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x10000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #816] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x10000000 +; CHECK-NEXT: str x30, [sp, #1160] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x20000000 +; CHECK-NEXT: ldr x9, [sp, #816] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #728] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x20000000 +; CHECK-NEXT: str x30, [sp, #1168] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x40000000 +; CHECK-NEXT: ldr x11, [sp, #728] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #696] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x40000000 +; CHECK-NEXT: str x30, [sp, #1176] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x80000000 +; CHECK-NEXT: ldr x12, [sp, #696] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #792] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: str x30, [sp, #688] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x80000000 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: str x30, [sp, #1184] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x100000000 +; CHECK-NEXT: ldr x12, [sp, #688] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x12, x0, x24 +; CHECK-NEXT: str x30, [sp, #744] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x100000000 +; CHECK-NEXT: str x30, [sp, #1192] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x200000000 +; CHECK-NEXT: ldr x10, [sp, #744] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x12, [sp, #960] // 8-byte Spill +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: str x30, [sp, #720] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x200000000 +; CHECK-NEXT: str x30, [sp, #1200] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x400000000 +; CHECK-NEXT: ldr x11, [sp, #720] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: str x30, [sp, #768] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x400000000 +; CHECK-NEXT: str x30, [sp, #1208] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x800000000 +; CHECK-NEXT: ldr x9, [sp, #768] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: str x30, [sp, #808] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x800000000 +; CHECK-NEXT: str x30, [sp, #1216] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x1000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #856] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x1000000000 +; CHECK-NEXT: str x30, [sp, #1224] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x2000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #648] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x2000000000 +; CHECK-NEXT: str x30, [sp, #1232] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x4000000000 +; CHECK-NEXT: ldr x11, [sp, #648] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #632] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x4000000000 +; CHECK-NEXT: str x30, [sp, #1240] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x8000000000 +; CHECK-NEXT: ldr x12, [sp, #632] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x12, x0, x25 +; CHECK-NEXT: str x30, [sp, #664] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x8000000000 +; CHECK-NEXT: str x30, [sp, #1248] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x10000000000 +; CHECK-NEXT: ldr x10, [sp, #664] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x12, [sp, #952] // 8-byte Spill +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: str x30, [sp, #640] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x10000000000 +; CHECK-NEXT: str x30, [sp, #1256] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x20000000000 +; CHECK-NEXT: ldr x11, [sp, #640] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: str x30, [sp, #680] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x20000000000 +; CHECK-NEXT: str x30, [sp, #1264] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x40000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #672] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x40000000000 +; CHECK-NEXT: str x30, [sp, #1272] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x80000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #712] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x80000000000 +; CHECK-NEXT: str x30, [sp, #1280] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x100000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #704] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x100000000000 +; CHECK-NEXT: str x30, [sp, #1288] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x200000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #752] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x200000000000 +; CHECK-NEXT: str x30, [sp, #1296] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x400000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #520] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x400000000000 +; CHECK-NEXT: str x30, [sp, #1304] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x800000000000 +; CHECK-NEXT: ldr x11, [sp, #520] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #504] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x800000000000 +; CHECK-NEXT: str x30, [sp, #1312] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x1000000000000 +; CHECK-NEXT: ldr x12, [sp, #504] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x12, x0, x26 +; CHECK-NEXT: str x30, [sp, #560] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x1000000000000 +; CHECK-NEXT: str x30, [sp, #1320] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x2000000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x12, [sp, #944] // 8-byte Spill +; CHECK-NEXT: ldr x12, [sp, #808] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: ldr x12, [sp, #680] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #560] // 8-byte Reload +; CHECK-NEXT: str x30, [sp, #552] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x2000000000000 +; CHECK-NEXT: str x30, [sp, #1328] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x4000000000000 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: ldr x12, [sp, #672] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #552] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x12, x0, x27 +; CHECK-NEXT: str x30, [sp, #584] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x4000000000000 +; CHECK-NEXT: str x30, [sp, #1336] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x8000000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x12, [sp, #936] // 8-byte Spill +; CHECK-NEXT: ldr x12, [sp, #856] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: ldr x12, [sp, #712] // 8-byte Reload +; CHECK-NEXT: str x30, [sp, #576] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x8000000000000 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: str x30, [sp, #1344] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x10000000000000 +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: ldr x12, [sp, #584] // 8-byte Reload +; CHECK-NEXT: ldr x9, [sp, #752] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #704] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #576] // 8-byte Reload +; CHECK-NEXT: str x30, [sp, #608] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x10000000000000 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: str x30, [sp, #1352] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x20000000000000 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: ldr x10, [sp, #608] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: mul x12, x0, x28 +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: str x30, [sp, #592] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x20000000000000 +; CHECK-NEXT: str x30, [sp, #1360] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x40000000000000 +; CHECK-NEXT: ldr x11, [sp, #592] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x12, [sp, #928] // 8-byte Spill +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: str x30, [sp, #624] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x40000000000000 +; CHECK-NEXT: str x30, [sp, #1368] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x80000000000000 +; CHECK-NEXT: ldr x9, [sp, #624] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: str x30, [sp, #616] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x80000000000000 +; CHECK-NEXT: str x30, [sp, #1376] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x100000000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #528] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x100000000000000 +; CHECK-NEXT: str x30, [sp, #1384] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x200000000000000 +; CHECK-NEXT: ldr x11, [sp, #528] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #512] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x200000000000000 +; CHECK-NEXT: str x30, [sp, #1392] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x400000000000000 +; CHECK-NEXT: ldr x12, [sp, #512] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: mul x12, x0, x29 +; CHECK-NEXT: str x30, [sp, #544] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x400000000000000 +; CHECK-NEXT: str x30, [sp, #1400] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x800000000000000 +; CHECK-NEXT: ldr x10, [sp, #544] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x12, [sp, #920] // 8-byte Spill +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: ldr x11, [sp, #616] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: eor x21, x8, x9 +; CHECK-NEXT: str x30, [sp, #536] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x800000000000000 +; CHECK-NEXT: str x30, [sp, #1408] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x1000000000000000 +; CHECK-NEXT: ldr x11, [sp, #536] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #1144] // 8-byte Reload +; CHECK-NEXT: mul x11, x0, x11 +; CHECK-NEXT: str x30, [sp, #568] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x1000000000000000 +; CHECK-NEXT: str x30, [sp, #1416] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x2000000000000000 +; CHECK-NEXT: ldr x8, [sp, #568] // 8-byte Reload +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: eor x8, x10, x8 +; CHECK-NEXT: str x11, [sp, #1144] // 8-byte Spill +; CHECK-NEXT: str x30, [sp, #600] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x2000000000000000 +; CHECK-NEXT: str x30, [sp, #1424] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x4000000000000000 +; CHECK-NEXT: mul x30, x1, x30 +; CHECK-NEXT: str x30, [sp, #656] // 8-byte Spill +; CHECK-NEXT: and x30, x2, #0x4000000000000000 +; CHECK-NEXT: and x2, x2, #0x8000000000000000 +; CHECK-NEXT: str x30, [sp, #1432] // 8-byte Spill +; CHECK-NEXT: mul x30, x1, x2 +; CHECK-NEXT: and x1, x3, #0x2 +; CHECK-NEXT: str x2, [sp, #1440] // 8-byte Spill +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x1 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: stp x1, x2, [sp, #488] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x4 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x8 +; CHECK-NEXT: ldp x10, x9, [sp, #488] // 16-byte Folded Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: str x1, [sp, #456] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x10 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x11, [sp, #456] // 8-byte Reload +; CHECK-NEXT: stp x2, x1, [sp, #472] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x20 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x10, [sp, #472] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #1152] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #480] // 8-byte Reload +; CHECK-NEXT: mul x11, x0, x11 +; CHECK-NEXT: str x1, [sp, #464] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x40 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x80 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: str x11, [sp, #1152] // 8-byte Spill +; CHECK-NEXT: ldr x11, [sp, #600] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x11 +; CHECK-NEXT: ldr x11, [sp, #464] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #424] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x100 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: str x1, [sp, #384] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x200 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x12, [sp, #384] // 8-byte Reload +; CHECK-NEXT: stp x1, x2, [sp, #440] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x400 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x800 +; CHECK-NEXT: ldr x11, [sp, #448] // 8-byte Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #424] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #440] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #1160] // 8-byte Reload +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: mul x12, x0, x12 +; CHECK-NEXT: str x1, [sp, #392] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x1000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: str x12, [sp, #1160] // 8-byte Spill +; CHECK-NEXT: ldr x12, [sp, #656] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #376] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x2000 +; CHECK-NEXT: eor x8, x8, x12 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x12, [sp, #376] // 8-byte Reload +; CHECK-NEXT: eor x16, x8, x30 +; CHECK-NEXT: stp x1, x2, [sp, #408] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x4000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x11, [sp, #416] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #392] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #408] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #1168] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #400] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x8000 +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: mul x12, x0, x12 +; CHECK-NEXT: str x1, [sp, #432] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x10000 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x20000 +; CHECK-NEXT: str x12, [sp, #1168] // 8-byte Spill +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: str x1, [sp, #328] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x40000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x12, [sp, #328] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #320] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x80000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: stp x1, x2, [sp, #352] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x100000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x11, [sp, #360] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #400] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #320] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #344] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x200000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #1176] // 8-byte Reload +; CHECK-NEXT: mul x12, x0, x12 +; CHECK-NEXT: str x1, [sp, #368] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x400000 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x800000 +; CHECK-NEXT: str x12, [sp, #1176] // 8-byte Spill +; CHECK-NEXT: ldr x12, [sp, #432] // 8-byte Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #352] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #368] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: str x1, [sp, #232] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x1000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x13, [sp, #232] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #224] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x2000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: stp x2, x1, [sp, #280] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x4000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x12, [sp, #280] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #344] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x13 +; CHECK-NEXT: ldr x13, [sp, #224] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #272] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x8000000 +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x10000000 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #1184] // 8-byte Reload +; CHECK-NEXT: ldr x11, [sp, #288] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x11, x12, x11 +; CHECK-NEXT: ldr x12, [sp, #272] // 8-byte Reload +; CHECK-NEXT: mul x13, x0, x13 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: stp x1, x2, [sp, #304] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x20000000 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x40000000 +; CHECK-NEXT: ldr x10, [sp, #312] // 8-byte Reload +; CHECK-NEXT: str x13, [sp, #1184] // 8-byte Spill +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: stp x1, x2, [sp, #168] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x80000000 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x100000000 +; CHECK-NEXT: ldp x13, x12, [sp, #168] // 16-byte Folded Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #1192] // 8-byte Reload +; CHECK-NEXT: mul x13, x0, x13 +; CHECK-NEXT: stp x1, x2, [sp, #200] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x200000000 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x400000000 +; CHECK-NEXT: ldr x11, [sp, #208] // 8-byte Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x11, x12, x11 +; CHECK-NEXT: ldr x12, [sp, #304] // 8-byte Reload +; CHECK-NEXT: str x13, [sp, #1192] // 8-byte Spill +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #200] // 8-byte Reload +; CHECK-NEXT: eor x8, x9, x10 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #1200] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #216] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x800000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x10, [sp, #216] // 8-byte Reload +; CHECK-NEXT: mul x12, x0, x12 +; CHECK-NEXT: stp x2, x1, [sp, #256] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x1000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x9, [sp, #256] // 8-byte Reload +; CHECK-NEXT: str x12, [sp, #1200] // 8-byte Spill +; CHECK-NEXT: eor x9, x11, x9 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: str x1, [sp, #336] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x2000000000 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x4000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: str x1, [sp, #136] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x8000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x11, [sp, #136] // 8-byte Reload +; CHECK-NEXT: stp x1, x2, [sp, #152] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x10000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x10, [sp, #160] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #1208] // 8-byte Reload +; CHECK-NEXT: mul x11, x0, x11 +; CHECK-NEXT: str x1, [sp, #144] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x20000000000 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x40000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: str x11, [sp, #1208] // 8-byte Spill +; CHECK-NEXT: ldr x11, [sp, #264] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: ldr x11, [sp, #152] // 8-byte Reload +; CHECK-NEXT: stp x1, x2, [sp, #184] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x80000000000 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: mul x2, x0, x1 +; CHECK-NEXT: and x1, x3, #0x100000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: stp x1, x2, [sp, #240] // 16-byte Folded Spill +; CHECK-NEXT: and x1, x3, #0x200000000000 +; CHECK-NEXT: and x2, x3, #0x1000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: mul x2, x0, x2 +; CHECK-NEXT: str x1, [sp, #296] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x400000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: str x1, [sp, #40] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x800000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x11, [sp, #40] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #16] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x2000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x12, [sp, #16] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #144] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x2 +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #1216] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #56] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x4000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: mul x23, x0, x12 +; CHECK-NEXT: ldr x12, [sp, #336] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: ldr x12, [sp, #192] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #48] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x8000000000000 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #56] // 8-byte Reload +; CHECK-NEXT: ldr x9, [sp, #248] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #184] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #48] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #96] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x10000000000000 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x10, [sp, #96] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #1224] // 8-byte Reload +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: ldr x11, [sp, #240] // 8-byte Reload +; CHECK-NEXT: mul x24, x0, x12 +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: str x1, [sp, #88] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x20000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x11, [sp, #88] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #1232] // 8-byte Reload +; CHECK-NEXT: mul x25, x0, x11 +; CHECK-NEXT: ldr x11, [sp, #296] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #112] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x40000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: ldr x11, [sp, #112] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: str x1, [sp, #104] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x80000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: str x1, [sp, #120] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x100000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x9, [sp, #120] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #80] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x200000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x11, [sp, #80] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #32] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x400000000000000 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x12, [sp, #32] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #104] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: str x1, [sp, #24] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x800000000000000 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: ldr x12, [sp, #24] // 8-byte Reload +; CHECK-NEXT: eor x15, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #1248] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #1240] // 8-byte Reload +; CHECK-NEXT: mul x27, x0, x9 +; CHECK-NEXT: ldr x9, [sp, #1944] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #72] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x1000000000000000 +; CHECK-NEXT: mul x26, x0, x12 +; CHECK-NEXT: ldr x10, [sp, #72] // 8-byte Reload +; CHECK-NEXT: ldr x12, [sp, #1904] // 8-byte Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: ldr x11, [sp, #1920] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #64] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x2000000000000000 +; CHECK-NEXT: ldr x8, [sp, #64] // 8-byte Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x8, x10, x8 +; CHECK-NEXT: ldr x10, [sp, #1936] // 8-byte Reload +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: ldr x10, [sp, #1928] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #128] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x4000000000000000 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #1912] // 8-byte Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #1888] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #1792] // 8-byte Reload +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: ldr x11, [sp, #1256] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #1880] // 8-byte Reload +; CHECK-NEXT: mul x28, x0, x11 +; CHECK-NEXT: ldr x11, [sp, #128] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #1056] // 8-byte Spill +; CHECK-NEXT: and x1, x3, #0x8000000000000000 +; CHECK-NEXT: eor x14, x8, x11 +; CHECK-NEXT: ldr x8, [sp, #1896] // 8-byte Reload +; CHECK-NEXT: ldr x11, [sp, #1832] // 8-byte Reload +; CHECK-NEXT: mul x1, x0, x1 +; CHECK-NEXT: eor x10, x8, x10 +; CHECK-NEXT: ldr x8, [sp, #1864] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x8 +; CHECK-NEXT: ldr x8, [sp, #1856] // 8-byte Reload +; CHECK-NEXT: eor x11, x8, x11 +; CHECK-NEXT: ldr x8, [sp, #1264] // 8-byte Reload +; CHECK-NEXT: str x1, [sp, #1080] // 8-byte Spill +; CHECK-NEXT: mul x1, x0, x7 +; CHECK-NEXT: mul x29, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #1872] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x8 +; CHECK-NEXT: ldr x8, [sp, #1840] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: str x1, [sp, #1136] // 8-byte Spill +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1816] // 8-byte Reload +; CHECK-NEXT: eor x12, x8, x12 +; CHECK-NEXT: ldr x8, [sp, #1824] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1784] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1272] // 8-byte Reload +; CHECK-NEXT: mul x30, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #1848] // 8-byte Reload +; CHECK-NEXT: eor x10, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1808] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: eor x11, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1776] // 8-byte Reload +; CHECK-NEXT: ldr x12, [sp, #1728] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1768] // 8-byte Reload +; CHECK-NEXT: eor x12, x8, x12 +; CHECK-NEXT: ldr x8, [sp, #1280] // 8-byte Reload +; CHECK-NEXT: mul x22, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #1800] // 8-byte Reload +; CHECK-NEXT: eor x10, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1760] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: eor x11, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1720] // 8-byte Reload +; CHECK-NEXT: ldr x12, [sp, #1656] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1696] // 8-byte Reload +; CHECK-NEXT: eor x12, x8, x12 +; CHECK-NEXT: ldr x8, [sp, #1288] // 8-byte Reload +; CHECK-NEXT: mul x20, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #1752] // 8-byte Reload +; CHECK-NEXT: eor x10, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1688] // 8-byte Reload +; CHECK-NEXT: eor x11, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1736] // 8-byte Reload +; CHECK-NEXT: ldr x12, [sp, #1608] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x8 +; CHECK-NEXT: ldr x8, [sp, #1672] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1296] // 8-byte Reload +; CHECK-NEXT: mul x19, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #1744] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x8 +; CHECK-NEXT: ldr x8, [sp, #1680] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1640] // 8-byte Reload +; CHECK-NEXT: eor x12, x8, x12 +; CHECK-NEXT: ldr x8, [sp, #1664] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1584] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1304] // 8-byte Reload +; CHECK-NEXT: mul x7, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #1704] // 8-byte Reload +; CHECK-NEXT: eor x10, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1632] // 8-byte Reload +; CHECK-NEXT: eor x11, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1600] // 8-byte Reload +; CHECK-NEXT: ldr x12, [sp, #1520] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1568] // 8-byte Reload +; CHECK-NEXT: eor x12, x8, x12 +; CHECK-NEXT: ldr x8, [sp, #1312] // 8-byte Reload +; CHECK-NEXT: mul x6, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #1712] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x8 +; CHECK-NEXT: ldr x8, [sp, #1616] // 8-byte Reload +; CHECK-NEXT: eor x13, x9, x10 +; CHECK-NEXT: ldr x9, [sp, #1448] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1536] // 8-byte Reload +; CHECK-NEXT: eor x6, x7, x6 +; CHECK-NEXT: ldr x7, [sp, #1424] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1592] // 8-byte Reload +; CHECK-NEXT: mul x7, x0, x7 +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1512] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1320] // 8-byte Reload +; CHECK-NEXT: mul x5, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #1624] // 8-byte Reload +; CHECK-NEXT: eor x10, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1560] // 8-byte Reload +; CHECK-NEXT: eor x11, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #1504] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldr x8, [sp, #1480] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #1328] // 8-byte Reload +; CHECK-NEXT: mul x4, x0, x9 +; CHECK-NEXT: ldr x9, [sp, #1648] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x9 +; CHECK-NEXT: ldr x9, [sp, #1552] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x10 +; CHECK-NEXT: ldr x10, [sp, #1576] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x9 +; CHECK-NEXT: ldr x9, [sp, #1472] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #1528] // 8-byte Reload +; CHECK-NEXT: eor x9, x11, x9 +; CHECK-NEXT: ldr x11, [sp, #1456] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #1488] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x11 +; CHECK-NEXT: ldr x11, [sp, #1336] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: ldr x10, [sp, #1544] // 8-byte Reload +; CHECK-NEXT: mul x3, x0, x11 +; CHECK-NEXT: ldr x11, [sp, #992] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #1464] // 8-byte Reload +; CHECK-NEXT: eor x9, x13, x9 +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: ldr x10, [sp, #1344] // 8-byte Reload +; CHECK-NEXT: mul x1, x0, x10 +; CHECK-NEXT: ldr x10, [sp, #1056] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x10 +; CHECK-NEXT: ldr x10, [sp, #1496] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: ldr x10, [sp, #1080] // 8-byte Reload +; CHECK-NEXT: eor x8, x9, x8 +; CHECK-NEXT: ldr x9, [sp, #1352] // 8-byte Reload +; CHECK-NEXT: eor x13, x14, x10 +; CHECK-NEXT: eor x14, x21, x16 +; CHECK-NEXT: rbit x8, x8 +; CHECK-NEXT: mul x18, x0, x9 +; CHECK-NEXT: eor x13, x15, x13 +; CHECK-NEXT: ldr x9, [sp, #1360] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x10, [sp, #1112] // 8-byte Reload +; CHECK-NEXT: mul x17, x0, x9 +; CHECK-NEXT: eor x2, x13, x8, lsr #1 +; CHECK-NEXT: ldr x8, [sp, #1136] // 8-byte Reload +; CHECK-NEXT: ldr x9, [sp, #1128] // 8-byte Reload +; CHECK-NEXT: eor x8, x9, x8 +; CHECK-NEXT: ldr x9, [sp, #1120] // 8-byte Reload +; CHECK-NEXT: eor x13, x9, x10 +; CHECK-NEXT: ldr x9, [sp, #1096] // 8-byte Reload +; CHECK-NEXT: ldr x10, [sp, #1072] // 8-byte Reload +; CHECK-NEXT: eor x13, x8, x13 +; CHECK-NEXT: ldr x8, [sp, #1104] // 8-byte Reload +; CHECK-NEXT: eor x14, x9, x10 +; CHECK-NEXT: ldr x9, [sp, #1368] // 8-byte Reload +; CHECK-NEXT: ldr x10, [sp, #984] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x8 +; CHECK-NEXT: ldr x8, [sp, #1064] // 8-byte Reload +; CHECK-NEXT: mul x21, x0, x9 +; CHECK-NEXT: ldr x9, [sp, #1048] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #1040] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #1000] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #1376] // 8-byte Reload +; CHECK-NEXT: mul x16, x0, x10 +; CHECK-NEXT: ldr x10, [sp, #1088] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: ldr x10, [sp, #1024] // 8-byte Reload +; CHECK-NEXT: eor x8, x13, x8 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #1016] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #1008] // 8-byte Reload +; CHECK-NEXT: eor x14, x10, x11 +; CHECK-NEXT: ldr x10, [sp, #1384] // 8-byte Reload +; CHECK-NEXT: ldr x11, [sp, #936] // 8-byte Reload +; CHECK-NEXT: mul x15, x0, x10 +; CHECK-NEXT: ldr x10, [sp, #1032] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #976] // 8-byte Reload +; CHECK-NEXT: eor x13, x14, x10 +; CHECK-NEXT: eor x10, x8, x9 +; CHECK-NEXT: ldr x8, [sp, #968] // 8-byte Reload +; CHECK-NEXT: eor x9, x13, x8 +; CHECK-NEXT: ldr x8, [sp, #1392] // 8-byte Reload +; CHECK-NEXT: mul x13, x0, x8 +; CHECK-NEXT: ldr x8, [sp, #960] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x8 +; CHECK-NEXT: ldr x8, [sp, #944] // 8-byte Reload +; CHECK-NEXT: eor x14, x8, x11 +; CHECK-NEXT: ldr x8, [sp, #1168] // 8-byte Reload +; CHECK-NEXT: ldr x11, [sp, #1176] // 8-byte Reload +; CHECK-NEXT: eor x13, x15, x13 +; CHECK-NEXT: eor x8, x8, x11 +; CHECK-NEXT: ldr x11, [sp, #928] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x11 +; CHECK-NEXT: ldr x11, [sp, #1184] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x11 +; CHECK-NEXT: ldr x11, [sp, #1400] // 8-byte Reload +; CHECK-NEXT: mul x12, x0, x11 +; CHECK-NEXT: ldr x11, [sp, #952] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: ldr x11, [sp, #920] // 8-byte Reload +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: ldr x10, [sp, #1152] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x11 +; CHECK-NEXT: ldr x11, [sp, #1192] // 8-byte Reload +; CHECK-NEXT: eor x12, x13, x12 +; CHECK-NEXT: ldr x13, [sp, #1440] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x11 +; CHECK-NEXT: ldr x11, [sp, #1144] // 8-byte Reload +; CHECK-NEXT: mul x13, x0, x13 +; CHECK-NEXT: eor x14, x14, x11 +; CHECK-NEXT: ldr x11, [sp, #1200] // 8-byte Reload +; CHECK-NEXT: eor x10, x14, x10 +; CHECK-NEXT: ldr x14, [sp, #1208] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x11 +; CHECK-NEXT: ldr x11, [sp, #1408] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x14 +; CHECK-NEXT: ldr x14, [sp, #1160] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x23 +; CHECK-NEXT: mul x11, x0, x11 +; CHECK-NEXT: eor x10, x10, x14 +; CHECK-NEXT: ldr x14, [sp, #1416] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x24 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: eor x10, x25, x26 +; CHECK-NEXT: eor x10, x10, x27 +; CHECK-NEXT: eor x8, x9, x8 +; CHECK-NEXT: mul x14, x0, x14 +; CHECK-NEXT: eor x9, x10, x28 +; CHECK-NEXT: eor x10, x6, x5 +; CHECK-NEXT: eor x10, x10, x4 +; CHECK-NEXT: ldr x4, [sp, #1432] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x29 +; CHECK-NEXT: eor x10, x10, x3 +; CHECK-NEXT: eor x9, x9, x30 +; CHECK-NEXT: eor x11, x12, x11 +; CHECK-NEXT: mul x4, x0, x4 +; CHECK-NEXT: eor x10, x10, x1 +; CHECK-NEXT: eor x9, x9, x22 +; CHECK-NEXT: eor x10, x10, x18 +; CHECK-NEXT: eor x9, x9, x20 +; CHECK-NEXT: eor x11, x11, x14 +; CHECK-NEXT: eor x10, x10, x17 +; CHECK-NEXT: eor x9, x9, x19 +; CHECK-NEXT: eor x11, x11, x7 +; CHECK-NEXT: eor x10, x10, x21 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: mov x1, x2 +; CHECK-NEXT: eor x9, x10, x16 +; CHECK-NEXT: eor x10, x11, x4 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x9, x10, x13 +; CHECK-NEXT: eor x0, x8, x9 +; CHECK-NEXT: add sp, sp, #1952 +; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload +; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload +; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload +; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload +; CHECK-NEXT: ldp x28, x27, [sp, #16] // 16-byte Folded Reload +; CHECK-NEXT: ldp x29, x30, [sp], #96 // 16-byte Folded Reload +; CHECK-NEXT: ret + %a = call <1 x i128> @llvm.clmul.v1i128(<1 x i128> %x, <1 x i128> %y) + ret <1 x i128> %a +} + +define <8 x i16> @clmul_v8i16_neon_zext(<8 x i8> %x, <8 x i8> %y) { +; CHECK-LABEL: clmul_v8i16_neon_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.8h, #2 +; CHECK-NEXT: movi v3.8h, #1 +; CHECK-NEXT: movi v4.8h, #4 +; CHECK-NEXT: movi v5.8h, #8 +; CHECK-NEXT: movi v6.8h, #16 +; CHECK-NEXT: movi v7.8h, #32 +; CHECK-NEXT: ushll v1.8h, v1.8b, #0 +; CHECK-NEXT: movi v16.8h, #64 +; CHECK-NEXT: movi v17.8h, #128 +; CHECK-NEXT: and v2.16b, v1.16b, v2.16b +; CHECK-NEXT: and v3.16b, v1.16b, v3.16b +; CHECK-NEXT: and v4.16b, v1.16b, v4.16b +; CHECK-NEXT: and v5.16b, v1.16b, v5.16b +; CHECK-NEXT: and v6.16b, v1.16b, v6.16b +; CHECK-NEXT: and v7.16b, v1.16b, v7.16b +; CHECK-NEXT: and v16.16b, v1.16b, v16.16b +; CHECK-NEXT: and v1.16b, v1.16b, v17.16b +; CHECK-NEXT: xtn v2.8b, v2.8h +; CHECK-NEXT: xtn v3.8b, v3.8h +; CHECK-NEXT: xtn v4.8b, v4.8h +; CHECK-NEXT: xtn v5.8b, v5.8h +; CHECK-NEXT: xtn v6.8b, v6.8h +; CHECK-NEXT: xtn v7.8b, v7.8h +; CHECK-NEXT: xtn v16.8b, v16.8h +; CHECK-NEXT: xtn v1.8b, v1.8h +; CHECK-NEXT: umull v2.8h, v0.8b, v2.8b +; CHECK-NEXT: umull v3.8h, v0.8b, v3.8b +; CHECK-NEXT: umull v4.8h, v0.8b, v4.8b +; CHECK-NEXT: umull v5.8h, v0.8b, v5.8b +; CHECK-NEXT: umull v6.8h, v0.8b, v6.8b +; CHECK-NEXT: umull v7.8h, v0.8b, v7.8b +; CHECK-NEXT: umull v16.8h, v0.8b, v16.8b +; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b +; CHECK-NEXT: eor v2.16b, v3.16b, v2.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v5.16b +; CHECK-NEXT: eor v4.16b, v6.16b, v7.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v16.16b +; CHECK-NEXT: eor v1.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b +; CHECK-NEXT: ret + %zextx = zext <8 x i8> %x to <8 x i16> + %zexty = zext <8 x i8> %y to <8 x i16> + %a = call <8 x i16> @llvm.clmul.v8i16(<8 x i16> %zextx, <8 x i16> %zexty) + ret <8 x i16> %a +} + +define <16 x i16> @clmul_v16i16_neon_zext(<16 x i8> %x, <16 x i8> %y) { +; CHECK-LABEL: clmul_v16i16_neon_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v4.8h, #2 +; CHECK-NEXT: ushll v2.8h, v1.8b, #0 +; CHECK-NEXT: movi v5.8h, #1 +; CHECK-NEXT: movi v6.8h, #4 +; CHECK-NEXT: movi v7.8h, #8 +; CHECK-NEXT: movi v17.8h, #16 +; CHECK-NEXT: ushll2 v3.8h, v1.16b, #0 +; CHECK-NEXT: movi v18.8h, #32 +; CHECK-NEXT: movi v1.8h, #128 +; CHECK-NEXT: movi v19.8h, #64 +; CHECK-NEXT: movi v25.2d, #0000000000000000 +; CHECK-NEXT: and v16.16b, v2.16b, v4.16b +; CHECK-NEXT: and v20.16b, v2.16b, v5.16b +; CHECK-NEXT: and v21.16b, v2.16b, v6.16b +; CHECK-NEXT: and v22.16b, v2.16b, v7.16b +; CHECK-NEXT: and v4.16b, v3.16b, v4.16b +; CHECK-NEXT: and v5.16b, v3.16b, v5.16b +; CHECK-NEXT: and v6.16b, v3.16b, v6.16b +; CHECK-NEXT: and v7.16b, v3.16b, v7.16b +; CHECK-NEXT: and v23.16b, v3.16b, v17.16b +; CHECK-NEXT: and v24.16b, v3.16b, v18.16b +; CHECK-NEXT: and v26.16b, v3.16b, v1.16b +; CHECK-NEXT: and v17.16b, v2.16b, v17.16b +; CHECK-NEXT: and v18.16b, v2.16b, v18.16b +; CHECK-NEXT: uzp1 v4.16b, v0.16b, v4.16b +; CHECK-NEXT: uzp1 v5.16b, v0.16b, v5.16b +; CHECK-NEXT: uzp1 v6.16b, v0.16b, v6.16b +; CHECK-NEXT: uzp1 v7.16b, v0.16b, v7.16b +; CHECK-NEXT: uzp1 v23.16b, v0.16b, v23.16b +; CHECK-NEXT: uzp1 v24.16b, v0.16b, v24.16b +; CHECK-NEXT: and v3.16b, v3.16b, v19.16b +; CHECK-NEXT: uzp1 v26.16b, v0.16b, v26.16b +; CHECK-NEXT: uzp1 v25.16b, v0.16b, v25.16b +; CHECK-NEXT: xtn v16.8b, v16.8h +; CHECK-NEXT: xtn v20.8b, v20.8h +; CHECK-NEXT: xtn v21.8b, v21.8h +; CHECK-NEXT: xtn v22.8b, v22.8h +; CHECK-NEXT: xtn v17.8b, v17.8h +; CHECK-NEXT: xtn v18.8b, v18.8h +; CHECK-NEXT: and v19.16b, v2.16b, v19.16b +; CHECK-NEXT: uzp1 v3.16b, v0.16b, v3.16b +; CHECK-NEXT: umull2 v4.8h, v0.16b, v4.16b +; CHECK-NEXT: umull2 v5.8h, v0.16b, v5.16b +; CHECK-NEXT: umull2 v6.8h, v0.16b, v6.16b +; CHECK-NEXT: umull2 v7.8h, v0.16b, v7.16b +; CHECK-NEXT: umull2 v23.8h, v0.16b, v23.16b +; CHECK-NEXT: umull2 v24.8h, v0.16b, v24.16b +; CHECK-NEXT: umull2 v26.8h, v0.16b, v26.16b +; CHECK-NEXT: umull2 v25.8h, v0.16b, v25.16b +; CHECK-NEXT: xtn v19.8b, v19.8h +; CHECK-NEXT: umull v16.8h, v0.8b, v16.8b +; CHECK-NEXT: umull v20.8h, v0.8b, v20.8b +; CHECK-NEXT: umull v21.8h, v0.8b, v21.8b +; CHECK-NEXT: umull v22.8h, v0.8b, v22.8b +; CHECK-NEXT: umull v17.8h, v0.8b, v17.8b +; CHECK-NEXT: umull v18.8h, v0.8b, v18.8b +; CHECK-NEXT: umull2 v3.8h, v0.16b, v3.16b +; CHECK-NEXT: eor v4.16b, v5.16b, v4.16b +; CHECK-NEXT: eor v5.16b, v6.16b, v7.16b +; CHECK-NEXT: eor v6.16b, v23.16b, v24.16b +; CHECK-NEXT: eor v7.16b, v26.16b, v25.16b +; CHECK-NEXT: eor v23.16b, v25.16b, v25.16b +; CHECK-NEXT: and v1.16b, v2.16b, v1.16b +; CHECK-NEXT: umull v2.8h, v0.8b, v19.8b +; CHECK-NEXT: eor v16.16b, v20.16b, v16.16b +; CHECK-NEXT: eor v19.16b, v21.16b, v22.16b +; CHECK-NEXT: eor v17.16b, v17.16b, v18.16b +; CHECK-NEXT: eor v4.16b, v4.16b, v5.16b +; CHECK-NEXT: eor v3.16b, v6.16b, v3.16b +; CHECK-NEXT: eor v5.16b, v7.16b, v25.16b +; CHECK-NEXT: eor v6.16b, v23.16b, v25.16b +; CHECK-NEXT: xtn v1.8b, v1.8h +; CHECK-NEXT: eor v7.16b, v16.16b, v19.16b +; CHECK-NEXT: eor v2.16b, v17.16b, v2.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b +; CHECK-NEXT: eor v4.16b, v5.16b, v25.16b +; CHECK-NEXT: eor v5.16b, v6.16b, v25.16b +; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b +; CHECK-NEXT: eor v1.16b, v7.16b, v2.16b +; CHECK-NEXT: eor v2.16b, v3.16b, v4.16b +; CHECK-NEXT: eor v3.16b, v5.16b, v25.16b +; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b +; CHECK-NEXT: eor v1.16b, v2.16b, v3.16b +; CHECK-NEXT: ret + %zextx = zext <16 x i8> %x to <16 x i16> + %zexty = zext <16 x i8> %y to <16 x i16> + %a = call <16 x i16> @llvm.clmul.v16i16(<16 x i16> %zextx, <16 x i16> %zexty) + ret <16 x i16> %a +} + +define <4 x i32> @clmul_v4i32_neon_zext(<4 x i16> %x, <4 x i16> %y) { +; CHECK-LABEL: clmul_v4i32_neon_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.4s, #2 +; CHECK-NEXT: movi v3.4s, #1 +; CHECK-NEXT: movi v4.4s, #4 +; CHECK-NEXT: movi v5.4s, #8 +; CHECK-NEXT: ushll v1.4s, v1.4h, #0 +; CHECK-NEXT: movi v6.4s, #16 +; CHECK-NEXT: movi v7.4s, #32 +; CHECK-NEXT: movi v16.4s, #128 +; CHECK-NEXT: movi v17.4s, #1, lsl #8 +; CHECK-NEXT: movi v18.4s, #8, lsl #8 +; CHECK-NEXT: movi v19.4s, #16, lsl #8 +; CHECK-NEXT: movi v20.4s, #64 +; CHECK-NEXT: and v2.16b, v1.16b, v2.16b +; CHECK-NEXT: and v3.16b, v1.16b, v3.16b +; CHECK-NEXT: and v4.16b, v1.16b, v4.16b +; CHECK-NEXT: and v5.16b, v1.16b, v5.16b +; CHECK-NEXT: movi v21.4s, #2, lsl #8 +; CHECK-NEXT: movi v22.4s, #32, lsl #8 +; CHECK-NEXT: and v6.16b, v1.16b, v6.16b +; CHECK-NEXT: and v7.16b, v1.16b, v7.16b +; CHECK-NEXT: and v16.16b, v1.16b, v16.16b +; CHECK-NEXT: and v17.16b, v1.16b, v17.16b +; CHECK-NEXT: and v18.16b, v1.16b, v18.16b +; CHECK-NEXT: and v19.16b, v1.16b, v19.16b +; CHECK-NEXT: xtn v2.4h, v2.4s +; CHECK-NEXT: xtn v3.4h, v3.4s +; CHECK-NEXT: xtn v4.4h, v4.4s +; CHECK-NEXT: xtn v5.4h, v5.4s +; CHECK-NEXT: movi v23.4s, #4, lsl #8 +; CHECK-NEXT: movi v24.4s, #64, lsl #8 +; CHECK-NEXT: xtn v6.4h, v6.4s +; CHECK-NEXT: xtn v7.4h, v7.4s +; CHECK-NEXT: and v20.16b, v1.16b, v20.16b +; CHECK-NEXT: xtn v16.4h, v16.4s +; CHECK-NEXT: xtn v17.4h, v17.4s +; CHECK-NEXT: and v21.16b, v1.16b, v21.16b +; CHECK-NEXT: xtn v18.4h, v18.4s +; CHECK-NEXT: xtn v19.4h, v19.4s +; CHECK-NEXT: and v22.16b, v1.16b, v22.16b +; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h +; CHECK-NEXT: umull v3.4s, v0.4h, v3.4h +; CHECK-NEXT: umull v4.4s, v0.4h, v4.4h +; CHECK-NEXT: umull v5.4s, v0.4h, v5.4h +; CHECK-NEXT: movi v25.4s, #128, lsl #8 +; CHECK-NEXT: xtn v20.4h, v20.4s +; CHECK-NEXT: xtn v21.4h, v21.4s +; CHECK-NEXT: and v23.16b, v1.16b, v23.16b +; CHECK-NEXT: xtn v22.4h, v22.4s +; CHECK-NEXT: and v24.16b, v1.16b, v24.16b +; CHECK-NEXT: umull v6.4s, v0.4h, v6.4h +; CHECK-NEXT: umull v7.4s, v0.4h, v7.4h +; CHECK-NEXT: umull v16.4s, v0.4h, v16.4h +; CHECK-NEXT: umull v17.4s, v0.4h, v17.4h +; CHECK-NEXT: umull v18.4s, v0.4h, v18.4h +; CHECK-NEXT: umull v19.4s, v0.4h, v19.4h +; CHECK-NEXT: eor v2.16b, v3.16b, v2.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v5.16b +; CHECK-NEXT: and v1.16b, v1.16b, v25.16b +; CHECK-NEXT: xtn v4.4h, v23.4s +; CHECK-NEXT: xtn v5.4h, v24.4s +; CHECK-NEXT: umull v20.4s, v0.4h, v20.4h +; CHECK-NEXT: umull v21.4s, v0.4h, v21.4h +; CHECK-NEXT: umull v22.4s, v0.4h, v22.4h +; CHECK-NEXT: eor v6.16b, v6.16b, v7.16b +; CHECK-NEXT: eor v7.16b, v16.16b, v17.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v16.16b, v18.16b, v19.16b +; CHECK-NEXT: xtn v1.4h, v1.4s +; CHECK-NEXT: umull v3.4s, v0.4h, v4.4h +; CHECK-NEXT: umull v4.4s, v0.4h, v5.4h +; CHECK-NEXT: eor v5.16b, v6.16b, v20.16b +; CHECK-NEXT: eor v6.16b, v7.16b, v21.16b +; CHECK-NEXT: eor v7.16b, v16.16b, v22.16b +; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h +; CHECK-NEXT: eor v1.16b, v2.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v6.16b, v3.16b +; CHECK-NEXT: eor v3.16b, v7.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v2.16b +; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b +; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b +; CHECK-NEXT: ret + %zextx = zext <4 x i16> %x to <4 x i32> + %zexty = zext <4 x i16> %y to <4 x i32> + %a = call <4 x i32> @llvm.clmul.v4i32(<4 x i32> %zextx, <4 x i32> %zexty) + ret <4 x i32> %a +} + +define <8 x i32> @clmul_v8i32_neon_zext(<8 x i16> %x, <8 x i16> %y) { +; CHECK-LABEL: clmul_v8i32_neon_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: stp d9, d8, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset b8, -8 +; CHECK-NEXT: .cfi_offset b9, -16 +; CHECK-NEXT: movi v4.4s, #2 +; CHECK-NEXT: movi v5.4s, #1 +; CHECK-NEXT: movi v6.4s, #4 +; CHECK-NEXT: ushll v2.4s, v1.4h, #0 +; CHECK-NEXT: movi v3.4s, #8 +; CHECK-NEXT: ushll2 v1.4s, v1.8h, #0 +; CHECK-NEXT: movi v20.4s, #16 +; CHECK-NEXT: movi v21.4s, #32 +; CHECK-NEXT: and v17.16b, v2.16b, v4.16b +; CHECK-NEXT: and v7.16b, v2.16b, v5.16b +; CHECK-NEXT: and v16.16b, v2.16b, v6.16b +; CHECK-NEXT: and v4.16b, v1.16b, v4.16b +; CHECK-NEXT: and v5.16b, v1.16b, v5.16b +; CHECK-NEXT: and v6.16b, v1.16b, v6.16b +; CHECK-NEXT: and v18.16b, v1.16b, v3.16b +; CHECK-NEXT: and v3.16b, v2.16b, v3.16b +; CHECK-NEXT: and v24.16b, v1.16b, v20.16b +; CHECK-NEXT: xtn v17.4h, v17.4s +; CHECK-NEXT: xtn v7.4h, v7.4s +; CHECK-NEXT: xtn v19.4h, v16.4s +; CHECK-NEXT: uzp1 v4.8h, v0.8h, v4.8h +; CHECK-NEXT: uzp1 v22.8h, v0.8h, v5.8h +; CHECK-NEXT: uzp1 v23.8h, v0.8h, v6.8h +; CHECK-NEXT: uzp1 v18.8h, v0.8h, v18.8h +; CHECK-NEXT: and v25.16b, v1.16b, v21.16b +; CHECK-NEXT: movi v6.4s, #128 +; CHECK-NEXT: uzp1 v24.8h, v0.8h, v24.8h +; CHECK-NEXT: and v28.16b, v2.16b, v20.16b +; CHECK-NEXT: and v21.16b, v2.16b, v21.16b +; CHECK-NEXT: umull v5.4s, v0.4h, v17.4h +; CHECK-NEXT: umull v16.4s, v0.4h, v7.4h +; CHECK-NEXT: umull v17.4s, v0.4h, v19.4h +; CHECK-NEXT: xtn v19.4h, v3.4s +; CHECK-NEXT: movi v3.4s, #64 +; CHECK-NEXT: movi v7.4s, #1, lsl #8 +; CHECK-NEXT: umull2 v26.4s, v0.8h, v4.8h +; CHECK-NEXT: umull2 v22.4s, v0.8h, v22.8h +; CHECK-NEXT: umull2 v23.4s, v0.8h, v23.8h +; CHECK-NEXT: umull2 v27.4s, v0.8h, v18.8h +; CHECK-NEXT: uzp1 v25.8h, v0.8h, v25.8h +; CHECK-NEXT: movi v4.4s, #2, lsl #8 +; CHECK-NEXT: and v30.16b, v1.16b, v6.16b +; CHECK-NEXT: movi v18.4s, #8, lsl #8 +; CHECK-NEXT: movi v20.4s, #16, lsl #8 +; CHECK-NEXT: and v29.16b, v1.16b, v3.16b +; CHECK-NEXT: and v31.16b, v1.16b, v7.16b +; CHECK-NEXT: umull2 v24.4s, v0.8h, v24.8h +; CHECK-NEXT: eor v22.16b, v22.16b, v26.16b +; CHECK-NEXT: xtn v28.4h, v28.4s +; CHECK-NEXT: umull v19.4s, v0.4h, v19.4h +; CHECK-NEXT: eor v23.16b, v23.16b, v27.16b +; CHECK-NEXT: umull2 v25.4s, v0.8h, v25.8h +; CHECK-NEXT: uzp1 v27.8h, v0.8h, v30.8h +; CHECK-NEXT: uzp1 v26.8h, v0.8h, v29.8h +; CHECK-NEXT: uzp1 v29.8h, v0.8h, v31.8h +; CHECK-NEXT: and v30.16b, v1.16b, v4.16b +; CHECK-NEXT: xtn v31.4h, v21.4s +; CHECK-NEXT: movi v21.4s, #32, lsl #8 +; CHECK-NEXT: and v8.16b, v1.16b, v20.16b +; CHECK-NEXT: eor v22.16b, v22.16b, v23.16b +; CHECK-NEXT: and v23.16b, v1.16b, v18.16b +; CHECK-NEXT: umull v28.4s, v0.4h, v28.4h +; CHECK-NEXT: eor v24.16b, v24.16b, v25.16b +; CHECK-NEXT: umull2 v27.4s, v0.8h, v27.8h +; CHECK-NEXT: eor v16.16b, v16.16b, v5.16b +; CHECK-NEXT: umull2 v25.4s, v0.8h, v26.8h +; CHECK-NEXT: uzp1 v26.8h, v0.8h, v30.8h +; CHECK-NEXT: umull2 v29.4s, v0.8h, v29.8h +; CHECK-NEXT: movi v30.2d, #0000000000000000 +; CHECK-NEXT: uzp1 v23.8h, v0.8h, v23.8h +; CHECK-NEXT: uzp1 v8.8h, v0.8h, v8.8h +; CHECK-NEXT: and v9.16b, v1.16b, v21.16b +; CHECK-NEXT: umull v31.4s, v0.4h, v31.4h +; CHECK-NEXT: eor v17.16b, v17.16b, v19.16b +; CHECK-NEXT: and v6.16b, v2.16b, v6.16b +; CHECK-NEXT: and v7.16b, v2.16b, v7.16b +; CHECK-NEXT: and v18.16b, v2.16b, v18.16b +; CHECK-NEXT: umull2 v26.4s, v0.8h, v26.8h +; CHECK-NEXT: eor v27.16b, v27.16b, v29.16b +; CHECK-NEXT: eor v24.16b, v24.16b, v25.16b +; CHECK-NEXT: uzp1 v29.8h, v0.8h, v9.8h +; CHECK-NEXT: uzp1 v30.8h, v0.8h, v30.8h +; CHECK-NEXT: movi v9.4s, #64, lsl #8 +; CHECK-NEXT: umull2 v23.4s, v0.8h, v23.8h +; CHECK-NEXT: umull2 v8.4s, v0.8h, v8.8h +; CHECK-NEXT: movi v25.4s, #4, lsl #8 +; CHECK-NEXT: eor v22.16b, v22.16b, v24.16b +; CHECK-NEXT: eor v19.16b, v28.16b, v31.16b +; CHECK-NEXT: movi v28.4s, #128, lsl #8 +; CHECK-NEXT: eor v24.16b, v27.16b, v26.16b +; CHECK-NEXT: and v20.16b, v2.16b, v20.16b +; CHECK-NEXT: xtn v6.4h, v6.4s +; CHECK-NEXT: umull2 v27.4s, v0.8h, v29.8h +; CHECK-NEXT: umull2 v5.4s, v0.8h, v30.8h +; CHECK-NEXT: and v29.16b, v1.16b, v9.16b +; CHECK-NEXT: eor v23.16b, v23.16b, v8.16b +; CHECK-NEXT: and v26.16b, v1.16b, v25.16b +; CHECK-NEXT: xtn v7.4h, v7.4s +; CHECK-NEXT: and v1.16b, v1.16b, v28.16b +; CHECK-NEXT: and v4.16b, v2.16b, v4.16b +; CHECK-NEXT: xtn v18.4h, v18.4s +; CHECK-NEXT: xtn v20.4h, v20.4s +; CHECK-NEXT: and v3.16b, v2.16b, v3.16b +; CHECK-NEXT: and v21.16b, v2.16b, v21.16b +; CHECK-NEXT: eor v23.16b, v23.16b, v27.16b +; CHECK-NEXT: uzp1 v27.8h, v0.8h, v29.8h +; CHECK-NEXT: eor v29.16b, v5.16b, v5.16b +; CHECK-NEXT: uzp1 v26.8h, v0.8h, v26.8h +; CHECK-NEXT: uzp1 v1.8h, v0.8h, v1.8h +; CHECK-NEXT: xtn v4.4h, v4.4s +; CHECK-NEXT: xtn v3.4h, v3.4s +; CHECK-NEXT: umull v6.4s, v0.4h, v6.4h +; CHECK-NEXT: umull v7.4s, v0.4h, v7.4h +; CHECK-NEXT: eor v29.16b, v29.16b, v5.16b +; CHECK-NEXT: and v25.16b, v2.16b, v25.16b +; CHECK-NEXT: umull v18.4s, v0.4h, v18.4h +; CHECK-NEXT: umull2 v27.4s, v0.8h, v27.8h +; CHECK-NEXT: umull v20.4s, v0.4h, v20.4h +; CHECK-NEXT: xtn v21.4h, v21.4s +; CHECK-NEXT: umull2 v26.4s, v0.8h, v26.8h +; CHECK-NEXT: and v30.16b, v2.16b, v9.16b +; CHECK-NEXT: umull2 v1.4s, v0.8h, v1.8h +; CHECK-NEXT: eor v29.16b, v29.16b, v5.16b +; CHECK-NEXT: xtn v25.4h, v25.4s +; CHECK-NEXT: umull v4.4s, v0.4h, v4.4h +; CHECK-NEXT: and v2.16b, v2.16b, v28.16b +; CHECK-NEXT: umull v3.4s, v0.4h, v3.4h +; CHECK-NEXT: eor v6.16b, v6.16b, v7.16b +; CHECK-NEXT: eor v23.16b, v23.16b, v27.16b +; CHECK-NEXT: xtn v27.4h, v30.4s +; CHECK-NEXT: eor v7.16b, v18.16b, v20.16b +; CHECK-NEXT: eor v24.16b, v24.16b, v26.16b +; CHECK-NEXT: eor v26.16b, v29.16b, v5.16b +; CHECK-NEXT: umull v18.4s, v0.4h, v21.4h +; CHECK-NEXT: xtn v2.4h, v2.4s +; CHECK-NEXT: eor v16.16b, v16.16b, v17.16b +; CHECK-NEXT: umull v17.4s, v0.4h, v25.4h +; CHECK-NEXT: eor v1.16b, v23.16b, v1.16b +; CHECK-NEXT: eor v4.16b, v6.16b, v4.16b +; CHECK-NEXT: eor v3.16b, v19.16b, v3.16b +; CHECK-NEXT: eor v20.16b, v22.16b, v24.16b +; CHECK-NEXT: eor v21.16b, v26.16b, v5.16b +; CHECK-NEXT: umull v6.4s, v0.4h, v27.4h +; CHECK-NEXT: eor v7.16b, v7.16b, v18.16b +; CHECK-NEXT: umull v0.4s, v0.4h, v2.4h +; CHECK-NEXT: eor v3.16b, v16.16b, v3.16b +; CHECK-NEXT: eor v4.16b, v4.16b, v17.16b +; CHECK-NEXT: eor v1.16b, v20.16b, v1.16b +; CHECK-NEXT: eor v18.16b, v21.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v7.16b, v6.16b +; CHECK-NEXT: eor v3.16b, v3.16b, v4.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v18.16b +; CHECK-NEXT: eor v6.16b, v18.16b, v5.16b +; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v6.16b +; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v5.16b +; CHECK-NEXT: ldp d9, d8, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret + %zextx = zext <8 x i16> %x to <8 x i32> + %zexty = zext <8 x i16> %y to <8 x i32> + %a = call <8 x i32> @llvm.clmul.v8i32(<8 x i32> %zextx, <8 x i32> %zexty) + ret <8 x i32> %a +} + +define <2 x i64> @clmul_v2i64_neon_zext(<2 x i32> %x, <2 x i32> %y) { +; CHECK-LABEL: clmul_v2i64_neon_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #2 // =0x2 +; CHECK-NEXT: mov w9, #4 // =0x4 +; CHECK-NEXT: ushll v1.2d, v1.2s, #0 +; CHECK-NEXT: dup v2.2d, x8 +; CHECK-NEXT: mov w8, #1 // =0x1 +; CHECK-NEXT: dup v4.2d, x9 +; CHECK-NEXT: dup v3.2d, x8 +; CHECK-NEXT: mov w8, #8 // =0x8 +; CHECK-NEXT: mov w9, #32 // =0x20 +; CHECK-NEXT: dup v5.2d, x8 +; CHECK-NEXT: mov w8, #16 // =0x10 +; CHECK-NEXT: dup v7.2d, x9 +; CHECK-NEXT: dup v6.2d, x8 +; CHECK-NEXT: and v2.16b, v1.16b, v2.16b +; CHECK-NEXT: and v4.16b, v1.16b, v4.16b +; CHECK-NEXT: and v3.16b, v1.16b, v3.16b +; CHECK-NEXT: mov w8, #64 // =0x40 +; CHECK-NEXT: movi v24.2d, #0000000000000000 +; CHECK-NEXT: and v5.16b, v1.16b, v5.16b +; CHECK-NEXT: and v7.16b, v1.16b, v7.16b +; CHECK-NEXT: dup v16.2d, x8 +; CHECK-NEXT: and v6.16b, v1.16b, v6.16b +; CHECK-NEXT: xtn v2.2s, v2.2d +; CHECK-NEXT: mov w8, #128 // =0x80 +; CHECK-NEXT: xtn v3.2s, v3.2d +; CHECK-NEXT: xtn v4.2s, v4.2d +; CHECK-NEXT: dup v17.2d, x8 +; CHECK-NEXT: xtn v5.2s, v5.2d +; CHECK-NEXT: mov w8, #256 // =0x100 +; CHECK-NEXT: xtn v7.2s, v7.2d +; CHECK-NEXT: xtn v6.2s, v6.2d +; CHECK-NEXT: and v16.16b, v1.16b, v16.16b +; CHECK-NEXT: dup v18.2d, x8 +; CHECK-NEXT: mov w8, #512 // =0x200 +; CHECK-NEXT: umull v2.2d, v0.2s, v2.2s +; CHECK-NEXT: and v17.16b, v1.16b, v17.16b +; CHECK-NEXT: umull v3.2d, v0.2s, v3.2s +; CHECK-NEXT: umull v4.2d, v0.2s, v4.2s +; CHECK-NEXT: fmov v26.2d, #2.00000000 +; CHECK-NEXT: umull v5.2d, v0.2s, v5.2s +; CHECK-NEXT: umull v7.2d, v0.2s, v7.2s +; CHECK-NEXT: xtn v16.2s, v16.2d +; CHECK-NEXT: umull v6.2d, v0.2s, v6.2s +; CHECK-NEXT: fneg v24.2d, v24.2d +; CHECK-NEXT: eor v2.16b, v3.16b, v2.16b +; CHECK-NEXT: and v26.16b, v1.16b, v26.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v5.16b +; CHECK-NEXT: and v4.16b, v1.16b, v18.16b +; CHECK-NEXT: dup v5.2d, x8 +; CHECK-NEXT: mov w8, #2048 // =0x800 +; CHECK-NEXT: eor v6.16b, v6.16b, v7.16b +; CHECK-NEXT: umull v7.2d, v0.2s, v16.2s +; CHECK-NEXT: xtn v16.2s, v17.2d +; CHECK-NEXT: dup v17.2d, x8 +; CHECK-NEXT: mov w8, #4096 // =0x1000 +; CHECK-NEXT: dup v18.2d, x8 +; CHECK-NEXT: mov w8, #1024 // =0x400 +; CHECK-NEXT: xtn v4.2s, v4.2d +; CHECK-NEXT: and v5.16b, v1.16b, v5.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: dup v3.2d, x8 +; CHECK-NEXT: mov w8, #8192 // =0x2000 +; CHECK-NEXT: and v17.16b, v1.16b, v17.16b +; CHECK-NEXT: eor v6.16b, v6.16b, v7.16b +; CHECK-NEXT: and v7.16b, v1.16b, v18.16b +; CHECK-NEXT: umull v16.2d, v0.2s, v16.2s +; CHECK-NEXT: dup v18.2d, x8 +; CHECK-NEXT: mov w8, #65536 // =0x10000 +; CHECK-NEXT: xtn v5.2s, v5.2d +; CHECK-NEXT: umull v4.2d, v0.2s, v4.2s +; CHECK-NEXT: xtn v17.2s, v17.2d +; CHECK-NEXT: eor v2.16b, v2.16b, v6.16b +; CHECK-NEXT: and v3.16b, v1.16b, v3.16b +; CHECK-NEXT: xtn v6.2s, v7.2d +; CHECK-NEXT: dup v7.2d, x8 +; CHECK-NEXT: mov w8, #131072 // =0x20000 +; CHECK-NEXT: dup v19.2d, x8 +; CHECK-NEXT: mov w8, #16384 // =0x4000 +; CHECK-NEXT: and v18.16b, v1.16b, v18.16b +; CHECK-NEXT: umull v5.2d, v0.2s, v5.2s +; CHECK-NEXT: eor v4.16b, v16.16b, v4.16b +; CHECK-NEXT: xtn v3.2s, v3.2d +; CHECK-NEXT: umull v16.2d, v0.2s, v17.2s +; CHECK-NEXT: dup v17.2d, x8 +; CHECK-NEXT: mov w8, #262144 // =0x40000 +; CHECK-NEXT: umull v6.2d, v0.2s, v6.2s +; CHECK-NEXT: and v7.16b, v1.16b, v7.16b +; CHECK-NEXT: and v19.16b, v1.16b, v19.16b +; CHECK-NEXT: xtn v18.2s, v18.2d +; CHECK-NEXT: eor v4.16b, v4.16b, v5.16b +; CHECK-NEXT: dup v5.2d, x8 +; CHECK-NEXT: mov w8, #32768 // =0x8000 +; CHECK-NEXT: xtn v7.2s, v7.2d +; CHECK-NEXT: xtn v19.2s, v19.2d +; CHECK-NEXT: umull v3.2d, v0.2s, v3.2s +; CHECK-NEXT: eor v6.16b, v16.16b, v6.16b +; CHECK-NEXT: dup v16.2d, x8 +; CHECK-NEXT: mov w8, #4194304 // =0x400000 +; CHECK-NEXT: and v17.16b, v1.16b, v17.16b +; CHECK-NEXT: and v5.16b, v1.16b, v5.16b +; CHECK-NEXT: dup v20.2d, x8 +; CHECK-NEXT: mov w8, #8388608 // =0x800000 +; CHECK-NEXT: umull v18.2d, v0.2s, v18.2s +; CHECK-NEXT: dup v21.2d, x8 +; CHECK-NEXT: mov w8, #16777216 // =0x1000000 +; CHECK-NEXT: umull v7.2d, v0.2s, v7.2s +; CHECK-NEXT: xtn v17.2s, v17.2d +; CHECK-NEXT: umull v19.2d, v0.2s, v19.2s +; CHECK-NEXT: xtn v5.2s, v5.2d +; CHECK-NEXT: and v16.16b, v1.16b, v16.16b +; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b +; CHECK-NEXT: dup v4.2d, x8 +; CHECK-NEXT: mov w8, #524288 // =0x80000 +; CHECK-NEXT: and v20.16b, v1.16b, v20.16b +; CHECK-NEXT: and v21.16b, v1.16b, v21.16b +; CHECK-NEXT: dup v22.2d, x8 +; CHECK-NEXT: mov w8, #1048576 // =0x100000 +; CHECK-NEXT: eor v6.16b, v6.16b, v18.16b +; CHECK-NEXT: umull v17.2d, v0.2s, v17.2s +; CHECK-NEXT: xtn v16.2s, v16.2d +; CHECK-NEXT: eor v7.16b, v7.16b, v19.16b +; CHECK-NEXT: umull v5.2d, v0.2s, v5.2s +; CHECK-NEXT: and v4.16b, v1.16b, v4.16b +; CHECK-NEXT: xtn v19.2s, v20.2d +; CHECK-NEXT: xtn v20.2s, v21.2d +; CHECK-NEXT: and v18.16b, v1.16b, v22.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: movi v22.4s, #128, lsl #24 +; CHECK-NEXT: xtn v21.2s, v4.2d +; CHECK-NEXT: eor v3.16b, v6.16b, v17.16b +; CHECK-NEXT: dup v17.2d, x8 +; CHECK-NEXT: mov w8, #2097152 // =0x200000 +; CHECK-NEXT: umull v4.2d, v0.2s, v16.2s +; CHECK-NEXT: eor v5.16b, v7.16b, v5.16b +; CHECK-NEXT: umull v7.2d, v0.2s, v19.2s +; CHECK-NEXT: umull v16.2d, v0.2s, v20.2s +; CHECK-NEXT: xtn v6.2s, v18.2d +; CHECK-NEXT: dup v18.2d, x8 +; CHECK-NEXT: mov w8, #33554432 // =0x2000000 +; CHECK-NEXT: fneg v22.2d, v22.2d +; CHECK-NEXT: dup v20.2d, x8 +; CHECK-NEXT: mov w8, #67108864 // =0x4000000 +; CHECK-NEXT: umull v19.2d, v0.2s, v21.2s +; CHECK-NEXT: dup v21.2d, x8 +; CHECK-NEXT: mov w8, #536870912 // =0x20000000 +; CHECK-NEXT: and v17.16b, v1.16b, v17.16b +; CHECK-NEXT: eor v7.16b, v7.16b, v16.16b +; CHECK-NEXT: dup v16.2d, x8 +; CHECK-NEXT: mov w8, #1073741824 // =0x40000000 +; CHECK-NEXT: and v20.16b, v1.16b, v20.16b +; CHECK-NEXT: dup v23.2d, x8 +; CHECK-NEXT: mov w8, #134217728 // =0x8000000 +; CHECK-NEXT: and v21.16b, v1.16b, v21.16b +; CHECK-NEXT: xtn v17.2s, v17.2d +; CHECK-NEXT: and v18.16b, v1.16b, v18.16b +; CHECK-NEXT: eor v7.16b, v7.16b, v19.16b +; CHECK-NEXT: dup v19.2d, x8 +; CHECK-NEXT: mov w8, #268435456 // =0x10000000 +; CHECK-NEXT: xtn v20.2s, v20.2d +; CHECK-NEXT: and v16.16b, v1.16b, v16.16b +; CHECK-NEXT: and v23.16b, v1.16b, v23.16b +; CHECK-NEXT: xtn v21.2s, v21.2d +; CHECK-NEXT: dup v25.2d, x8 +; CHECK-NEXT: and v22.16b, v1.16b, v22.16b +; CHECK-NEXT: and v19.16b, v1.16b, v19.16b +; CHECK-NEXT: umull v6.2d, v0.2s, v6.2s +; CHECK-NEXT: xtn v18.2s, v18.2d +; CHECK-NEXT: xtn v16.2s, v16.2d +; CHECK-NEXT: xtn v23.2s, v23.2d +; CHECK-NEXT: umull v17.2d, v0.2s, v17.2s +; CHECK-NEXT: umull v20.2d, v0.2s, v20.2s +; CHECK-NEXT: and v25.16b, v1.16b, v25.16b +; CHECK-NEXT: xtn v22.2s, v22.2d +; CHECK-NEXT: xtn v19.2s, v19.2d +; CHECK-NEXT: umull v21.2d, v0.2s, v21.2s +; CHECK-NEXT: eor v3.16b, v3.16b, v4.16b +; CHECK-NEXT: eor v4.16b, v5.16b, v6.16b +; CHECK-NEXT: and v1.16b, v1.16b, v24.16b +; CHECK-NEXT: umull v18.2d, v0.2s, v18.2s +; CHECK-NEXT: umull v16.2d, v0.2s, v16.2s +; CHECK-NEXT: umull v23.2d, v0.2s, v23.2s +; CHECK-NEXT: xtn v6.2s, v25.2d +; CHECK-NEXT: eor v5.16b, v7.16b, v20.16b +; CHECK-NEXT: xtn v7.2s, v26.2d +; CHECK-NEXT: umull v20.2d, v0.2s, v22.2s +; CHECK-NEXT: umull v19.2d, v0.2s, v19.2s +; CHECK-NEXT: eor v4.16b, v4.16b, v17.16b +; CHECK-NEXT: xtn v1.2s, v1.2d +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v5.16b, v5.16b, v21.16b +; CHECK-NEXT: eor v16.16b, v16.16b, v23.16b +; CHECK-NEXT: umull v3.2d, v0.2s, v6.2s +; CHECK-NEXT: umull v6.2d, v0.2s, v7.2s +; CHECK-NEXT: eor v4.16b, v4.16b, v18.16b +; CHECK-NEXT: umull v0.2d, v0.2s, v1.2s +; CHECK-NEXT: eor v5.16b, v5.16b, v19.16b +; CHECK-NEXT: eor v7.16b, v16.16b, v20.16b +; CHECK-NEXT: eor v1.16b, v2.16b, v4.16b +; CHECK-NEXT: eor v2.16b, v5.16b, v3.16b +; CHECK-NEXT: eor v3.16b, v7.16b, v6.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v2.16b +; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b +; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b +; CHECK-NEXT: ret + %zextx = zext <2 x i32> %x to <2 x i64> + %zexty = zext <2 x i32> %y to <2 x i64> + %a = call <2 x i64> @llvm.clmul.v2i64(<2 x i64> %zextx, <2 x i64> %zexty) + ret <2 x i64> %a +} + +define <4 x i64> @clmul_v4i64_neon_zext(<4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: clmul_v4i64_neon_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #320 +; CHECK-NEXT: stp d15, d14, [sp, #240] // 16-byte Folded Spill +; CHECK-NEXT: stp d13, d12, [sp, #256] // 16-byte Folded Spill +; CHECK-NEXT: stp d11, d10, [sp, #272] // 16-byte Folded Spill +; CHECK-NEXT: stp d9, d8, [sp, #288] // 16-byte Folded Spill +; CHECK-NEXT: str x29, [sp, #304] // 8-byte Spill +; CHECK-NEXT: .cfi_def_cfa_offset 320 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_offset b8, -24 +; CHECK-NEXT: .cfi_offset b9, -32 +; CHECK-NEXT: .cfi_offset b10, -40 +; CHECK-NEXT: .cfi_offset b11, -48 +; CHECK-NEXT: .cfi_offset b12, -56 +; CHECK-NEXT: .cfi_offset b13, -64 +; CHECK-NEXT: .cfi_offset b14, -72 +; CHECK-NEXT: .cfi_offset b15, -80 +; CHECK-NEXT: mov w8, #2 // =0x2 +; CHECK-NEXT: mov w9, #1 // =0x1 +; CHECK-NEXT: ushll v6.2d, v1.2s, #0 +; CHECK-NEXT: dup v23.2d, x8 +; CHECK-NEXT: dup v22.2d, x9 +; CHECK-NEXT: mov w8, #4 // =0x4 +; CHECK-NEXT: mov w10, #16 // =0x10 +; CHECK-NEXT: dup v28.2d, x8 +; CHECK-NEXT: mov w9, #8 // =0x8 +; CHECK-NEXT: dup v24.2d, x10 +; CHECK-NEXT: ushll2 v5.2d, v1.4s, #0 +; CHECK-NEXT: dup v25.2d, x9 +; CHECK-NEXT: and v3.16b, v6.16b, v23.16b +; CHECK-NEXT: and v4.16b, v6.16b, v22.16b +; CHECK-NEXT: mov w8, #32 // =0x20 +; CHECK-NEXT: and v7.16b, v6.16b, v28.16b +; CHECK-NEXT: dup v26.2d, x8 +; CHECK-NEXT: mov w8, #64 // =0x40 +; CHECK-NEXT: and v17.16b, v6.16b, v24.16b +; CHECK-NEXT: and v16.16b, v6.16b, v25.16b +; CHECK-NEXT: and v25.16b, v5.16b, v25.16b +; CHECK-NEXT: xtn v3.2s, v3.2d +; CHECK-NEXT: xtn v4.2s, v4.2d +; CHECK-NEXT: mov w9, #256 // =0x100 +; CHECK-NEXT: xtn v19.2s, v7.2d +; CHECK-NEXT: dup v18.2d, x8 +; CHECK-NEXT: mov w8, #128 // =0x80 +; CHECK-NEXT: xtn v29.2s, v17.2d +; CHECK-NEXT: and v27.16b, v6.16b, v26.16b +; CHECK-NEXT: ldr x29, [sp, #304] // 8-byte Reload +; CHECK-NEXT: and v24.16b, v5.16b, v24.16b +; CHECK-NEXT: and v26.16b, v5.16b, v26.16b +; CHECK-NEXT: uzp1 v25.4s, v0.4s, v25.4s +; CHECK-NEXT: umull v3.2d, v0.2s, v3.2s +; CHECK-NEXT: umull v4.2d, v0.2s, v4.2s +; CHECK-NEXT: dup v1.2d, x8 +; CHECK-NEXT: mov w8, #512 // =0x200 +; CHECK-NEXT: dup v8.2d, x9 +; CHECK-NEXT: mov w9, #2048 // =0x800 +; CHECK-NEXT: umull v20.2d, v0.2s, v19.2s +; CHECK-NEXT: umull v19.2d, v0.2s, v29.2s +; CHECK-NEXT: uzp1 v29.4s, v0.4s, v24.4s +; CHECK-NEXT: uzp1 v26.4s, v0.4s, v26.4s +; CHECK-NEXT: and v30.16b, v5.16b, v18.16b +; CHECK-NEXT: dup v2.2d, x8 +; CHECK-NEXT: mov w8, #1024 // =0x400 +; CHECK-NEXT: stp q8, q1, [sp, #192] // 32-byte Folded Spill +; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b +; CHECK-NEXT: and v4.16b, v5.16b, v22.16b +; CHECK-NEXT: and v22.16b, v5.16b, v28.16b +; CHECK-NEXT: dup v7.2d, x8 +; CHECK-NEXT: mov w8, #4096 // =0x1000 +; CHECK-NEXT: and v31.16b, v5.16b, v1.16b +; CHECK-NEXT: and v8.16b, v5.16b, v8.16b +; CHECK-NEXT: str q3, [sp, #224] // 16-byte Spill +; CHECK-NEXT: and v3.16b, v5.16b, v23.16b +; CHECK-NEXT: umull2 v9.2d, v0.4s, v25.4s +; CHECK-NEXT: str q7, [sp, #96] // 16-byte Spill +; CHECK-NEXT: uzp1 v4.4s, v0.4s, v4.4s +; CHECK-NEXT: uzp1 v28.4s, v0.4s, v22.4s +; CHECK-NEXT: xtn v21.2s, v16.2d +; CHECK-NEXT: dup v16.2d, x9 +; CHECK-NEXT: mov w9, #32768 // =0x8000 +; CHECK-NEXT: uzp1 v3.4s, v0.4s, v3.4s +; CHECK-NEXT: dup v17.2d, x8 +; CHECK-NEXT: mov w8, #8192 // =0x2000 +; CHECK-NEXT: uzp1 v30.4s, v0.4s, v30.4s +; CHECK-NEXT: umull2 v29.2d, v0.4s, v29.4s +; CHECK-NEXT: umull2 v26.2d, v0.4s, v26.4s +; CHECK-NEXT: stp q16, q2, [sp, #160] // 32-byte Folded Spill +; CHECK-NEXT: umull2 v4.2d, v0.4s, v4.4s +; CHECK-NEXT: umull2 v28.2d, v0.4s, v28.4s +; CHECK-NEXT: uzp1 v31.4s, v0.4s, v31.4s +; CHECK-NEXT: uzp1 v8.4s, v0.4s, v8.4s +; CHECK-NEXT: dup v23.2d, x8 +; CHECK-NEXT: mov w8, #16384 // =0x4000 +; CHECK-NEXT: umull2 v3.2d, v0.4s, v3.4s +; CHECK-NEXT: and v10.16b, v5.16b, v17.16b +; CHECK-NEXT: umull2 v30.2d, v0.4s, v30.4s +; CHECK-NEXT: eor v29.16b, v29.16b, v26.16b +; CHECK-NEXT: dup v24.2d, x8 +; CHECK-NEXT: mov w8, #65536 // =0x10000 +; CHECK-NEXT: stp q17, q23, [sp, #128] // 32-byte Folded Spill +; CHECK-NEXT: eor v9.16b, v28.16b, v9.16b +; CHECK-NEXT: and v28.16b, v5.16b, v16.16b +; CHECK-NEXT: umull2 v31.2d, v0.4s, v31.4s +; CHECK-NEXT: umull2 v8.2d, v0.4s, v8.4s +; CHECK-NEXT: str q24, [sp, #112] // 16-byte Spill +; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b +; CHECK-NEXT: and v4.16b, v5.16b, v2.16b +; CHECK-NEXT: uzp1 v10.4s, v0.4s, v10.4s +; CHECK-NEXT: and v13.16b, v5.16b, v23.16b +; CHECK-NEXT: dup v1.2d, x8 +; CHECK-NEXT: mov w8, #131072 // =0x20000 +; CHECK-NEXT: uzp1 v12.4s, v0.4s, v28.4s +; CHECK-NEXT: and v11.16b, v5.16b, v7.16b +; CHECK-NEXT: uzp1 v4.4s, v0.4s, v4.4s +; CHECK-NEXT: dup v17.2d, x8 +; CHECK-NEXT: mov w8, #524288 // =0x80000 +; CHECK-NEXT: eor v3.16b, v3.16b, v9.16b +; CHECK-NEXT: eor v29.16b, v29.16b, v30.16b +; CHECK-NEXT: uzp1 v9.4s, v0.4s, v13.4s +; CHECK-NEXT: dup v22.2d, x9 +; CHECK-NEXT: mov w9, #262144 // =0x40000 +; CHECK-NEXT: eor v31.16b, v31.16b, v8.16b +; CHECK-NEXT: stp q17, q1, [sp, #64] // 32-byte Folded Spill +; CHECK-NEXT: umull2 v8.2d, v0.4s, v12.4s +; CHECK-NEXT: umull2 v10.2d, v0.4s, v10.4s +; CHECK-NEXT: umull2 v4.2d, v0.4s, v4.4s +; CHECK-NEXT: dup v2.2d, x9 +; CHECK-NEXT: mov w9, #536870912 // =0x20000000 +; CHECK-NEXT: str q22, [sp, #16] // 16-byte Spill +; CHECK-NEXT: uzp1 v30.4s, v0.4s, v11.4s +; CHECK-NEXT: eor v7.16b, v3.16b, v29.16b +; CHECK-NEXT: and v29.16b, v5.16b, v24.16b +; CHECK-NEXT: and v11.16b, v5.16b, v1.16b +; CHECK-NEXT: and v12.16b, v5.16b, v17.16b +; CHECK-NEXT: dup v16.2d, x8 +; CHECK-NEXT: mov w8, #4194304 // =0x400000 +; CHECK-NEXT: eor v8.16b, v8.16b, v10.16b +; CHECK-NEXT: eor v4.16b, v31.16b, v4.16b +; CHECK-NEXT: umull2 v31.2d, v0.4s, v9.4s +; CHECK-NEXT: and v9.16b, v5.16b, v22.16b +; CHECK-NEXT: uzp1 v10.4s, v0.4s, v29.4s +; CHECK-NEXT: uzp1 v11.4s, v0.4s, v11.4s +; CHECK-NEXT: uzp1 v12.4s, v0.4s, v12.4s +; CHECK-NEXT: stp q16, q2, [sp, #32] // 32-byte Folded Spill +; CHECK-NEXT: and v13.16b, v5.16b, v2.16b +; CHECK-NEXT: xtn v14.2s, v27.2d +; CHECK-NEXT: umull2 v30.2d, v0.4s, v30.4s +; CHECK-NEXT: dup v1.2d, x8 +; CHECK-NEXT: mov w8, #8388608 // =0x800000 +; CHECK-NEXT: umull v21.2d, v0.2s, v21.2s +; CHECK-NEXT: uzp1 v9.4s, v0.4s, v9.4s +; CHECK-NEXT: eor v8.16b, v8.16b, v31.16b +; CHECK-NEXT: and v31.16b, v5.16b, v16.16b +; CHECK-NEXT: uzp1 v13.4s, v0.4s, v13.4s +; CHECK-NEXT: dup v29.2d, x8 +; CHECK-NEXT: mov w8, #16777216 // =0x1000000 +; CHECK-NEXT: str q1, [sp] // 16-byte Spill +; CHECK-NEXT: umull2 v10.2d, v0.4s, v10.4s +; CHECK-NEXT: umull2 v11.2d, v0.4s, v11.4s +; CHECK-NEXT: umull2 v12.2d, v0.4s, v12.4s +; CHECK-NEXT: eor v2.16b, v4.16b, v30.16b +; CHECK-NEXT: umull v15.2d, v0.2s, v14.2s +; CHECK-NEXT: uzp1 v4.4s, v0.4s, v31.4s +; CHECK-NEXT: dup v31.2d, x8 +; CHECK-NEXT: mov w8, #1048576 // =0x100000 +; CHECK-NEXT: and v3.16b, v5.16b, v1.16b +; CHECK-NEXT: and v1.16b, v5.16b, v29.16b +; CHECK-NEXT: umull2 v9.2d, v0.4s, v9.4s +; CHECK-NEXT: eor v14.16b, v20.16b, v21.16b +; CHECK-NEXT: umull2 v21.2d, v0.4s, v13.4s +; CHECK-NEXT: eor v20.16b, v8.16b, v10.16b +; CHECK-NEXT: eor v2.16b, v7.16b, v2.16b +; CHECK-NEXT: eor v7.16b, v11.16b, v12.16b +; CHECK-NEXT: eor v15.16b, v19.16b, v15.16b +; CHECK-NEXT: uzp1 v3.4s, v0.4s, v3.4s +; CHECK-NEXT: uzp1 v1.4s, v0.4s, v1.4s +; CHECK-NEXT: and v19.16b, v5.16b, v31.16b +; CHECK-NEXT: umull2 v8.2d, v0.4s, v4.4s +; CHECK-NEXT: dup v10.2d, x8 +; CHECK-NEXT: mov w8, #33554432 // =0x2000000 +; CHECK-NEXT: eor v20.16b, v20.16b, v9.16b +; CHECK-NEXT: eor v7.16b, v7.16b, v21.16b +; CHECK-NEXT: dup v9.2d, x8 +; CHECK-NEXT: mov w8, #67108864 // =0x4000000 +; CHECK-NEXT: dup v28.2d, x9 +; CHECK-NEXT: uzp1 v19.4s, v0.4s, v19.4s +; CHECK-NEXT: umull2 v11.2d, v0.4s, v3.4s +; CHECK-NEXT: umull2 v1.2d, v0.4s, v1.4s +; CHECK-NEXT: eor v25.16b, v2.16b, v20.16b +; CHECK-NEXT: movi v2.4s, #128, lsl #24 +; CHECK-NEXT: eor v23.16b, v7.16b, v8.16b +; CHECK-NEXT: dup v8.2d, x8 +; CHECK-NEXT: mov w8, #1073741824 // =0x40000000 +; CHECK-NEXT: and v12.16b, v5.16b, v9.16b +; CHECK-NEXT: dup v27.2d, x8 +; CHECK-NEXT: mov w8, #2097152 // =0x200000 +; CHECK-NEXT: and v3.16b, v5.16b, v28.16b +; CHECK-NEXT: umull2 v7.2d, v0.4s, v19.4s +; CHECK-NEXT: eor v4.16b, v11.16b, v1.16b +; CHECK-NEXT: and v11.16b, v5.16b, v10.16b +; CHECK-NEXT: fneg v30.2d, v2.2d +; CHECK-NEXT: dup v13.2d, x8 +; CHECK-NEXT: mov w8, #134217728 // =0x8000000 +; CHECK-NEXT: and v1.16b, v5.16b, v27.16b +; CHECK-NEXT: and v2.16b, v5.16b, v8.16b +; CHECK-NEXT: dup v24.2d, x8 +; CHECK-NEXT: mov w8, #268435456 // =0x10000000 +; CHECK-NEXT: uzp1 v12.4s, v0.4s, v12.4s +; CHECK-NEXT: uzp1 v17.4s, v0.4s, v3.4s +; CHECK-NEXT: eor v19.16b, v4.16b, v7.16b +; CHECK-NEXT: uzp1 v7.4s, v0.4s, v11.4s +; CHECK-NEXT: and v3.16b, v5.16b, v13.16b +; CHECK-NEXT: uzp1 v16.4s, v0.4s, v1.4s +; CHECK-NEXT: uzp1 v11.4s, v0.4s, v2.4s +; CHECK-NEXT: and v1.16b, v5.16b, v30.16b +; CHECK-NEXT: and v2.16b, v5.16b, v24.16b +; CHECK-NEXT: movi v22.2d, #0000000000000000 +; CHECK-NEXT: and v4.16b, v6.16b, v18.16b +; CHECK-NEXT: umull2 v12.2d, v0.4s, v12.4s +; CHECK-NEXT: umull2 v18.2d, v0.4s, v17.4s +; CHECK-NEXT: dup v26.2d, x8 +; CHECK-NEXT: umull2 v20.2d, v0.4s, v7.4s +; CHECK-NEXT: uzp1 v7.4s, v0.4s, v3.4s +; CHECK-NEXT: uzp1 v3.4s, v0.4s, v1.4s +; CHECK-NEXT: umull2 v17.2d, v0.4s, v16.4s +; CHECK-NEXT: uzp1 v16.4s, v0.4s, v2.4s +; CHECK-NEXT: umull2 v11.2d, v0.4s, v11.4s +; CHECK-NEXT: ldp q1, q2, [sp, #192] // 32-byte Folded Reload +; CHECK-NEXT: xtn v21.2s, v4.2d +; CHECK-NEXT: eor v19.16b, v19.16b, v12.16b +; CHECK-NEXT: umull2 v7.2d, v0.4s, v7.4s +; CHECK-NEXT: umull2 v4.2d, v0.4s, v3.4s +; CHECK-NEXT: and v3.16b, v5.16b, v26.16b +; CHECK-NEXT: and v12.16b, v6.16b, v2.16b +; CHECK-NEXT: uzp1 v2.4s, v0.4s, v22.4s +; CHECK-NEXT: ldr q22, [sp, #176] // 16-byte Reload +; CHECK-NEXT: and v1.16b, v6.16b, v1.16b +; CHECK-NEXT: eor v20.16b, v23.16b, v20.16b +; CHECK-NEXT: eor v17.16b, v18.16b, v17.16b +; CHECK-NEXT: umull2 v16.2d, v0.4s, v16.4s +; CHECK-NEXT: eor v19.16b, v19.16b, v11.16b +; CHECK-NEXT: and v22.16b, v6.16b, v22.16b +; CHECK-NEXT: xtn v18.2s, v12.2d +; CHECK-NEXT: uzp1 v11.4s, v0.4s, v3.4s +; CHECK-NEXT: and v23.16b, v6.16b, v28.16b +; CHECK-NEXT: xtn v1.2s, v1.2d +; CHECK-NEXT: umull2 v3.2d, v0.4s, v2.4s +; CHECK-NEXT: eor v2.16b, v20.16b, v7.16b +; CHECK-NEXT: ldp q12, q20, [sp, #144] // 32-byte Folded Reload +; CHECK-NEXT: eor v4.16b, v17.16b, v4.16b +; CHECK-NEXT: ldr q17, [sp, #96] // 16-byte Reload +; CHECK-NEXT: umull v7.2d, v0.2s, v21.2s +; CHECK-NEXT: ldr q21, [sp, #128] // 16-byte Reload +; CHECK-NEXT: eor v16.16b, v19.16b, v16.16b +; CHECK-NEXT: xtn v19.2s, v22.2d +; CHECK-NEXT: umull v18.2d, v0.2s, v18.2s +; CHECK-NEXT: and v17.16b, v6.16b, v17.16b +; CHECK-NEXT: and v20.16b, v6.16b, v20.16b +; CHECK-NEXT: and v21.16b, v6.16b, v21.16b +; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s +; CHECK-NEXT: umull2 v22.2d, v0.4s, v11.4s +; CHECK-NEXT: ldr q11, [sp, #224] // 16-byte Reload +; CHECK-NEXT: eor v4.16b, v4.16b, v3.16b +; CHECK-NEXT: and v12.16b, v6.16b, v12.16b +; CHECK-NEXT: eor v2.16b, v25.16b, v2.16b +; CHECK-NEXT: xtn v17.2s, v17.2d +; CHECK-NEXT: xtn v20.2s, v20.2d +; CHECK-NEXT: xtn v21.2s, v21.2d +; CHECK-NEXT: umull v19.2d, v0.2s, v19.2s +; CHECK-NEXT: eor v11.16b, v11.16b, v14.16b +; CHECK-NEXT: eor v7.16b, v15.16b, v7.16b +; CHECK-NEXT: ldp d15, d14, [sp, #240] // 16-byte Folded Reload +; CHECK-NEXT: eor v1.16b, v18.16b, v1.16b +; CHECK-NEXT: eor v4.16b, v4.16b, v3.16b +; CHECK-NEXT: eor v16.16b, v16.16b, v22.16b +; CHECK-NEXT: ldr q22, [sp, #112] // 16-byte Reload +; CHECK-NEXT: umull v17.2d, v0.2s, v17.2s +; CHECK-NEXT: umull v18.2d, v0.2s, v20.2s +; CHECK-NEXT: umull v20.2d, v0.2s, v21.2s +; CHECK-NEXT: xtn v21.2s, v12.2d +; CHECK-NEXT: eor v1.16b, v1.16b, v19.16b +; CHECK-NEXT: and v22.16b, v6.16b, v22.16b +; CHECK-NEXT: ldp q25, q19, [sp, #64] // 32-byte Folded Reload +; CHECK-NEXT: eor v4.16b, v4.16b, v3.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v16.16b +; CHECK-NEXT: ldr q16, [sp, #16] // 16-byte Reload +; CHECK-NEXT: eor v7.16b, v11.16b, v7.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v17.16b +; CHECK-NEXT: eor v17.16b, v18.16b, v20.16b +; CHECK-NEXT: ldr q20, [sp, #48] // 16-byte Reload +; CHECK-NEXT: umull v18.2d, v0.2s, v21.2s +; CHECK-NEXT: and v16.16b, v6.16b, v16.16b +; CHECK-NEXT: and v19.16b, v6.16b, v19.16b +; CHECK-NEXT: xtn v22.2s, v22.2d +; CHECK-NEXT: and v25.16b, v6.16b, v25.16b +; CHECK-NEXT: eor v4.16b, v4.16b, v3.16b +; CHECK-NEXT: and v20.16b, v6.16b, v20.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v1.16b, v7.16b, v1.16b +; CHECK-NEXT: xtn v16.2s, v16.2d +; CHECK-NEXT: xtn v19.2s, v19.2d +; CHECK-NEXT: xtn v21.2s, v25.2d +; CHECK-NEXT: eor v4.16b, v4.16b, v3.16b +; CHECK-NEXT: eor v17.16b, v17.16b, v18.16b +; CHECK-NEXT: xtn v18.2s, v20.2d +; CHECK-NEXT: ldr q20, [sp, #32] // 16-byte Reload +; CHECK-NEXT: umull v7.2d, v0.2s, v22.2s +; CHECK-NEXT: ldr q22, [sp] // 16-byte Reload +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: and v25.16b, v6.16b, v10.16b +; CHECK-NEXT: ldp d11, d10, [sp, #272] // 16-byte Folded Reload +; CHECK-NEXT: and v20.16b, v6.16b, v20.16b +; CHECK-NEXT: eor v4.16b, v4.16b, v3.16b +; CHECK-NEXT: umull v16.2d, v0.2s, v16.2s +; CHECK-NEXT: umull v19.2d, v0.2s, v19.2s +; CHECK-NEXT: umull v21.2d, v0.2s, v21.2s +; CHECK-NEXT: and v22.16b, v6.16b, v22.16b +; CHECK-NEXT: eor v7.16b, v17.16b, v7.16b +; CHECK-NEXT: xtn v17.2s, v20.2d +; CHECK-NEXT: and v20.16b, v6.16b, v29.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v4.16b, v4.16b, v3.16b +; CHECK-NEXT: umull v18.2d, v0.2s, v18.2s +; CHECK-NEXT: and v29.16b, v6.16b, v31.16b +; CHECK-NEXT: xtn v22.2s, v22.2d +; CHECK-NEXT: eor v7.16b, v7.16b, v16.16b +; CHECK-NEXT: eor v16.16b, v19.16b, v21.16b +; CHECK-NEXT: xtn v19.2s, v20.2d +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v4.16b, v4.16b, v3.16b +; CHECK-NEXT: umull v17.2d, v0.2s, v17.2s +; CHECK-NEXT: xtn v20.2s, v25.2d +; CHECK-NEXT: xtn v21.2s, v29.2d +; CHECK-NEXT: and v25.16b, v6.16b, v9.16b +; CHECK-NEXT: eor v16.16b, v16.16b, v18.16b +; CHECK-NEXT: umull v18.2d, v0.2s, v22.2s +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: umull v19.2d, v0.2s, v19.2s +; CHECK-NEXT: eor v22.16b, v4.16b, v3.16b +; CHECK-NEXT: eor v4.16b, v1.16b, v7.16b +; CHECK-NEXT: xtn v7.2s, v25.2d +; CHECK-NEXT: and v1.16b, v6.16b, v13.16b +; CHECK-NEXT: and v25.16b, v6.16b, v27.16b +; CHECK-NEXT: ldp d13, d12, [sp, #256] // 16-byte Folded Reload +; CHECK-NEXT: eor v16.16b, v16.16b, v17.16b +; CHECK-NEXT: umull v17.2d, v0.2s, v20.2s +; CHECK-NEXT: umull v20.2d, v0.2s, v21.2s +; CHECK-NEXT: and v21.16b, v6.16b, v8.16b +; CHECK-NEXT: ldp d9, d8, [sp, #288] // 16-byte Folded Reload +; CHECK-NEXT: eor v22.16b, v22.16b, v3.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v18.16b, v18.16b, v19.16b +; CHECK-NEXT: and v19.16b, v6.16b, v24.16b +; CHECK-NEXT: umull v7.2d, v0.2s, v7.2s +; CHECK-NEXT: xtn v21.2s, v21.2d +; CHECK-NEXT: xtn v1.2s, v1.2d +; CHECK-NEXT: eor v22.16b, v22.16b, v3.16b +; CHECK-NEXT: eor v16.16b, v16.16b, v17.16b +; CHECK-NEXT: and v24.16b, v6.16b, v26.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v17.16b, v18.16b, v20.16b +; CHECK-NEXT: xtn v20.2s, v25.2d +; CHECK-NEXT: movi v25.2d, #0000000000000000 +; CHECK-NEXT: xtn v18.2s, v19.2d +; CHECK-NEXT: xtn v19.2s, v23.2d +; CHECK-NEXT: fmov v23.2d, #2.00000000 +; CHECK-NEXT: eor v22.16b, v22.16b, v3.16b +; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v7.16b, v17.16b, v7.16b +; CHECK-NEXT: umull v17.2d, v0.2s, v21.2s +; CHECK-NEXT: and v21.16b, v6.16b, v30.16b +; CHECK-NEXT: umull v20.2d, v0.2s, v20.2s +; CHECK-NEXT: fneg v25.2d, v25.2d +; CHECK-NEXT: eor v22.16b, v22.16b, v3.16b +; CHECK-NEXT: umull v18.2d, v0.2s, v18.2s +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: umull v19.2d, v0.2s, v19.2s +; CHECK-NEXT: and v26.16b, v6.16b, v23.16b +; CHECK-NEXT: xtn v21.2s, v21.2d +; CHECK-NEXT: eor v7.16b, v7.16b, v17.16b +; CHECK-NEXT: eor v1.16b, v16.16b, v1.16b +; CHECK-NEXT: xtn v16.2s, v24.2d +; CHECK-NEXT: eor v17.16b, v22.16b, v3.16b +; CHECK-NEXT: and v22.16b, v5.16b, v23.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: and v6.16b, v6.16b, v25.16b +; CHECK-NEXT: and v5.16b, v5.16b, v25.16b +; CHECK-NEXT: xtn v23.2s, v26.2d +; CHECK-NEXT: eor v7.16b, v7.16b, v18.16b +; CHECK-NEXT: eor v18.16b, v19.16b, v20.16b +; CHECK-NEXT: umull v19.2d, v0.2s, v21.2s +; CHECK-NEXT: eor v17.16b, v17.16b, v3.16b +; CHECK-NEXT: uzp1 v20.4s, v0.4s, v22.4s +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: umull v16.2d, v0.2s, v16.2s +; CHECK-NEXT: xtn v6.2s, v6.2d +; CHECK-NEXT: uzp1 v5.4s, v0.4s, v5.4s +; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b +; CHECK-NEXT: umull v21.2d, v0.2s, v23.2s +; CHECK-NEXT: eor v17.16b, v17.16b, v3.16b +; CHECK-NEXT: eor v18.16b, v18.16b, v19.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v4.16b, v7.16b, v16.16b +; CHECK-NEXT: umull v6.2d, v0.2s, v6.2s +; CHECK-NEXT: umull2 v7.2d, v0.4s, v20.4s +; CHECK-NEXT: umull2 v0.2d, v0.4s, v5.4s +; CHECK-NEXT: eor v16.16b, v17.16b, v3.16b +; CHECK-NEXT: eor v5.16b, v18.16b, v21.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b +; CHECK-NEXT: eor v1.16b, v1.16b, v4.16b +; CHECK-NEXT: eor v4.16b, v16.16b, v7.16b +; CHECK-NEXT: eor v3.16b, v5.16b, v6.16b +; CHECK-NEXT: eor v2.16b, v2.16b, v0.16b +; CHECK-NEXT: eor v0.16b, v1.16b, v3.16b +; CHECK-NEXT: eor v1.16b, v2.16b, v4.16b +; CHECK-NEXT: add sp, sp, #320 +; CHECK-NEXT: ret + %zextx = zext <4 x i32> %x to <4 x i64> + %zexty = zext <4 x i32> %y to <4 x i64> + %a = call <4 x i64> @llvm.clmul.v4i64(<4 x i64> %zextx, <4 x i64> %zexty) + ret <4 x i64> %a +} + +define <1 x i128> @clmul_v1i128_neon_zext(<1 x i64> %x, <1 x i64> %y) { +; CHECK-LABEL: clmul_v1i128_neon_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x29, x30, [sp, #-96]! // 16-byte Folded Spill +; CHECK-NEXT: stp x28, x27, [sp, #16] // 16-byte Folded Spill +; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill +; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill +; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill +; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill +; CHECK-NEXT: sub sp, sp, #624 +; CHECK-NEXT: .cfi_def_cfa_offset 720 +; CHECK-NEXT: .cfi_offset w19, -8 +; CHECK-NEXT: .cfi_offset w20, -16 +; CHECK-NEXT: .cfi_offset w21, -24 +; CHECK-NEXT: .cfi_offset w22, -32 +; CHECK-NEXT: .cfi_offset w23, -40 +; CHECK-NEXT: .cfi_offset w24, -48 +; CHECK-NEXT: .cfi_offset w25, -56 +; CHECK-NEXT: .cfi_offset w26, -64 +; CHECK-NEXT: .cfi_offset w27, -72 +; CHECK-NEXT: .cfi_offset w28, -80 +; CHECK-NEXT: .cfi_offset w30, -88 +; CHECK-NEXT: .cfi_offset w29, -96 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: fmov x10, d1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: fmov x11, d0 +; CHECK-NEXT: and x8, x10, #0x2 +; CHECK-NEXT: mul x13, x11, x8 +; CHECK-NEXT: and x8, x10, #0x1 +; CHECK-NEXT: mul x14, x11, x8 +; CHECK-NEXT: and x8, x10, #0x4 +; CHECK-NEXT: mul x15, x11, x8 +; CHECK-NEXT: and x8, x10, #0x8 +; CHECK-NEXT: mul x16, x11, x8 +; CHECK-NEXT: and x8, x10, #0x10 +; CHECK-NEXT: mul x17, x11, x8 +; CHECK-NEXT: and x8, x10, #0x20 +; CHECK-NEXT: mul x18, x11, x8 +; CHECK-NEXT: and x8, x10, #0x40 +; CHECK-NEXT: mul x0, x11, x8 +; CHECK-NEXT: and x8, x10, #0x80 +; CHECK-NEXT: mul x1, x11, x8 +; CHECK-NEXT: and x8, x10, #0x100 +; CHECK-NEXT: mul x3, x11, x8 +; CHECK-NEXT: and x8, x10, #0x200 +; CHECK-NEXT: mul x2, x11, x8 +; CHECK-NEXT: and x8, x10, #0x400 +; CHECK-NEXT: mul x4, x11, x8 +; CHECK-NEXT: and x8, x10, #0x800 +; CHECK-NEXT: mul x5, x11, x8 +; CHECK-NEXT: and x8, x10, #0x1000 +; CHECK-NEXT: mul x20, x11, x8 +; CHECK-NEXT: and x8, x10, #0x2000 +; CHECK-NEXT: mul x6, x11, x8 +; CHECK-NEXT: and x8, x10, #0x4000 +; CHECK-NEXT: mul x7, x11, x8 +; CHECK-NEXT: and x8, x10, #0x8000 +; CHECK-NEXT: mul x19, x11, x8 +; CHECK-NEXT: and x8, x10, #0x10000 +; CHECK-NEXT: mul x21, x11, x8 +; CHECK-NEXT: and x8, x10, #0x20000 +; CHECK-NEXT: mul x22, x11, x8 +; CHECK-NEXT: and x8, x10, #0x40000 +; CHECK-NEXT: mul x23, x11, x8 +; CHECK-NEXT: and x8, x10, #0x80000 +; CHECK-NEXT: mul x24, x11, x8 +; CHECK-NEXT: and x8, x10, #0x100000 +; CHECK-NEXT: mul x25, x11, x8 +; CHECK-NEXT: and x8, x10, #0x200000 +; CHECK-NEXT: mul x26, x11, x8 +; CHECK-NEXT: and x8, x10, #0x400000 +; CHECK-NEXT: mul x27, x11, x8 +; CHECK-NEXT: and x8, x10, #0x800000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #592] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x1000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #584] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x2000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #616] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x4000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #576] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x8000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #608] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x10000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #600] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x20000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #568] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x40000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #512] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x80000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #536] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x100000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #528] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x200000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #560] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x400000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #520] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x800000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #552] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x1000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #544] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x2000000000 +; CHECK-NEXT: mul x9, x11, x8 +; CHECK-NEXT: and x8, x10, #0x4000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #440] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x8000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #464] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x10000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #456] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x20000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: stp x8, x9, [sp, #488] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x10, #0x40000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #448] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x80000000000 +; CHECK-NEXT: mul x9, x11, x8 +; CHECK-NEXT: and x8, x10, #0x100000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: stp x8, x9, [sp, #472] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x10, #0x200000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #504] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x400000000000 +; CHECK-NEXT: mul x9, x11, x8 +; CHECK-NEXT: and x8, x10, #0x800000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #392] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x1000000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #416] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x2000000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #408] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x4000000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: stp x8, x9, [sp, #424] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x10, #0x8000000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: str x8, [sp, #400] // 8-byte Spill +; CHECK-NEXT: and x8, x10, #0x100000000000000 +; CHECK-NEXT: mul x9, x11, x8 +; CHECK-NEXT: and x8, x10, #0x200000000000000 +; CHECK-NEXT: mul x8, x11, x8 +; CHECK-NEXT: stp x8, x9, [sp, #376] // 16-byte Folded Spill +; CHECK-NEXT: and x9, x10, #0x400000000000000 +; CHECK-NEXT: rbit x8, x10 +; CHECK-NEXT: mul x9, x11, x9 +; CHECK-NEXT: and x12, x8, #0x2 +; CHECK-NEXT: str x9, [sp, #368] // 8-byte Spill +; CHECK-NEXT: rbit x9, x11 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #360] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x1 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #352] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x4 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #344] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x8 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #336] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x10 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #328] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x20 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #320] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x40 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #312] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x80 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #304] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x100 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #296] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x200 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #288] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x400 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #280] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x800 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #272] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x1000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #256] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x2000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #248] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x4000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #264] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x8000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #240] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x10000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #232] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x20000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #200] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x40000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #224] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x80000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #192] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x100000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #216] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x200000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #208] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x400000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #184] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x800000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #136] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x1000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #168] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x2000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #160] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x4000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #176] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x8000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #152] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x10000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #144] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x20000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #128] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x40000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #120] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x80000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #112] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x100000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #104] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x200000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #96] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x400000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #88] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x800000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #80] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x1000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #72] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x2000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #64] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x4000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #56] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x8000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #48] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x10000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #40] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x20000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #32] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x40000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #24] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x80000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: str x12, [sp, #16] // 8-byte Spill +; CHECK-NEXT: eor x12, x14, x13 +; CHECK-NEXT: and x14, x8, #0x100000000000 +; CHECK-NEXT: mul x14, x9, x14 +; CHECK-NEXT: eor x13, x15, x16 +; CHECK-NEXT: and x15, x8, #0x200000000000 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: eor x13, x17, x18 +; CHECK-NEXT: ldr x16, [sp, #608] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x0 +; CHECK-NEXT: mul x30, x9, x15 +; CHECK-NEXT: and x15, x8, #0x400000000000 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: mul x29, x9, x15 +; CHECK-NEXT: and x15, x8, #0x800000000000 +; CHECK-NEXT: str x14, [sp, #8] // 8-byte Spill +; CHECK-NEXT: eor x14, x1, x3 +; CHECK-NEXT: eor x13, x14, x2 +; CHECK-NEXT: eor x14, x5, x20 +; CHECK-NEXT: mul x28, x9, x15 +; CHECK-NEXT: eor x13, x13, x4 +; CHECK-NEXT: ldr x15, [sp, #592] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: eor x13, x14, x6 +; CHECK-NEXT: eor x14, x21, x22 +; CHECK-NEXT: eor x13, x13, x7 +; CHECK-NEXT: eor x14, x14, x23 +; CHECK-NEXT: eor x15, x27, x15 +; CHECK-NEXT: eor x13, x13, x19 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: eor x13, x14, x24 +; CHECK-NEXT: and x14, x8, #0x1000000000000 +; CHECK-NEXT: eor x13, x13, x25 +; CHECK-NEXT: mul x27, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #584] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x26 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #616] // 8-byte Reload +; CHECK-NEXT: eor x14, x15, x14 +; CHECK-NEXT: and x15, x8, #0x2000000000000 +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: ldr x14, [sp, #576] // 8-byte Reload +; CHECK-NEXT: mul x25, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #512] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #568] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #536] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: and x15, x8, #0x4000000000000 +; CHECK-NEXT: mul x24, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #600] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: ldr x16, [sp, #552] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #528] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #560] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: and x15, x8, #0x8000000000000 +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: ldr x14, [sp, #520] // 8-byte Reload +; CHECK-NEXT: mul x23, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #440] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #496] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #464] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: and x15, x8, #0x10000000000000 +; CHECK-NEXT: mul x21, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #544] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: ldr x16, [sp, #256] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #456] // 8-byte Reload +; CHECK-NEXT: eor x26, x12, x13 +; CHECK-NEXT: ldr x12, [sp, #488] // 8-byte Reload +; CHECK-NEXT: ldr x13, [sp, #448] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: and x15, x8, #0x20000000000000 +; CHECK-NEXT: eor x12, x14, x12 +; CHECK-NEXT: mul x20, x9, x15 +; CHECK-NEXT: ldr x14, [sp, #392] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #432] // 8-byte Reload +; CHECK-NEXT: ldr x15, [sp, #480] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: and x14, x8, #0x40000000000000 +; CHECK-NEXT: eor x12, x12, x15 +; CHECK-NEXT: ldr x15, [sp, #416] // 8-byte Reload +; CHECK-NEXT: mul x7, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #472] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #504] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x14 +; CHECK-NEXT: ldr x14, [sp, #408] // 8-byte Reload +; CHECK-NEXT: eor x22, x12, x15 +; CHECK-NEXT: ldr x12, [sp, #424] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: and x14, x8, #0x80000000000000 +; CHECK-NEXT: eor x12, x13, x12 +; CHECK-NEXT: ldr x13, [sp, #400] // 8-byte Reload +; CHECK-NEXT: mul x5, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #368] // 8-byte Reload +; CHECK-NEXT: eor x19, x12, x13 +; CHECK-NEXT: ldp x13, x12, [sp, #376] // 16-byte Folded Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: and x13, x8, #0x100000000000000 +; CHECK-NEXT: eor x6, x12, x14 +; CHECK-NEXT: ldp x14, x12, [sp, #352] // 16-byte Folded Reload +; CHECK-NEXT: mul x4, x9, x13 +; CHECK-NEXT: eor x12, x14, x12 +; CHECK-NEXT: ldp x14, x13, [sp, #336] // 16-byte Folded Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldp x15, x14, [sp, #320] // 16-byte Folded Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #312] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: and x15, x8, #0x200000000000000 +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: mul x3, x9, x15 +; CHECK-NEXT: and x15, x8, #0x400000000000000 +; CHECK-NEXT: eor x14, x12, x13 +; CHECK-NEXT: ldp x13, x12, [sp, #296] // 16-byte Folded Reload +; CHECK-NEXT: mul x2, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #280] // 8-byte Reload +; CHECK-NEXT: eor x13, x12, x13 +; CHECK-NEXT: ldr x12, [sp, #288] // 8-byte Reload +; CHECK-NEXT: eor x3, x4, x3 +; CHECK-NEXT: and x4, x10, #0x2000000000000000 +; CHECK-NEXT: eor x13, x13, x12 +; CHECK-NEXT: ldr x12, [sp, #272] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #248] // 8-byte Reload +; CHECK-NEXT: eor x2, x3, x2 +; CHECK-NEXT: eor x12, x12, x16 +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: ldr x14, [sp, #264] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x15 +; CHECK-NEXT: and x15, x8, #0x800000000000000 +; CHECK-NEXT: mul x3, x11, x4 +; CHECK-NEXT: eor x14, x12, x14 +; CHECK-NEXT: mul x1, x9, x15 +; CHECK-NEXT: ldp x12, x15, [sp, #232] // 16-byte Folded Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: ldr x15, [sp, #200] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldp x16, x14, [sp, #216] // 16-byte Folded Reload +; CHECK-NEXT: eor x15, x12, x15 +; CHECK-NEXT: and x12, x8, #0x1000000000000000 +; CHECK-NEXT: eor x1, x2, x1 +; CHECK-NEXT: mul x0, x9, x12 +; CHECK-NEXT: and x2, x10, #0x4000000000000000 +; CHECK-NEXT: eor x14, x15, x14 +; CHECK-NEXT: ldp x12, x15, [sp, #184] // 16-byte Folded Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: ldr x15, [sp, #136] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: ldr x16, [sp, #168] // 8-byte Reload +; CHECK-NEXT: eor x0, x1, x0 +; CHECK-NEXT: eor x15, x12, x15 +; CHECK-NEXT: and x12, x8, #0x2000000000000000 +; CHECK-NEXT: and x8, x8, #0x4000000000000000 +; CHECK-NEXT: mul x18, x9, x12 +; CHECK-NEXT: ldr x12, [sp, #208] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: eor x14, x14, x12 +; CHECK-NEXT: ldr x12, [sp, #160] // 8-byte Reload +; CHECK-NEXT: mul x17, x9, x8 +; CHECK-NEXT: ldr x8, [sp, #152] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: eor x15, x15, x12 +; CHECK-NEXT: ldr x12, [sp, #176] // 8-byte Reload +; CHECK-NEXT: mul x1, x11, x2 +; CHECK-NEXT: eor x18, x0, x18 +; CHECK-NEXT: eor x14, x15, x12 +; CHECK-NEXT: and x15, x10, #0x10000000000000 +; CHECK-NEXT: eor x9, x14, x8 +; CHECK-NEXT: ldp x12, x8, [sp, #120] // 16-byte Folded Reload +; CHECK-NEXT: mul x16, x11, x15 +; CHECK-NEXT: eor x14, x8, x12 +; CHECK-NEXT: ldr x8, [sp, #144] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x8 +; CHECK-NEXT: ldr x8, [sp, #112] // 8-byte Reload +; CHECK-NEXT: eor x9, x13, x9 +; CHECK-NEXT: eor x14, x14, x8 +; CHECK-NEXT: ldr x8, [sp, #104] // 8-byte Reload +; CHECK-NEXT: eor x13, x14, x8 +; CHECK-NEXT: ldr x8, [sp, #96] // 8-byte Reload +; CHECK-NEXT: and x14, x10, #0x20000000000000 +; CHECK-NEXT: mul x15, x11, x14 +; CHECK-NEXT: eor x13, x13, x8 +; CHECK-NEXT: ldp x12, x8, [sp, #56] // 16-byte Folded Reload +; CHECK-NEXT: eor x8, x8, x12 +; CHECK-NEXT: ldp x14, x12, [sp, #80] // 16-byte Folded Reload +; CHECK-NEXT: eor x13, x13, x12 +; CHECK-NEXT: ldr x12, [sp, #48] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #40] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x12 +; CHECK-NEXT: and x12, x10, #0x40000000000000 +; CHECK-NEXT: eor x8, x8, x14 +; CHECK-NEXT: mul x14, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #72] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x12 +; CHECK-NEXT: ldr x12, [sp, #32] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x13 +; CHECK-NEXT: ldr x13, [sp, #24] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x12 +; CHECK-NEXT: and x12, x10, #0x80000000000000 +; CHECK-NEXT: eor x8, x8, x13 +; CHECK-NEXT: ldr x13, [sp, #16] // 8-byte Reload +; CHECK-NEXT: mul x12, x11, x12 +; CHECK-NEXT: eor x8, x8, x13 +; CHECK-NEXT: eor x13, x29, x28 +; CHECK-NEXT: ldr x29, [sp, #8] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x27 +; CHECK-NEXT: and x28, x10, #0x800000000000000 +; CHECK-NEXT: eor x8, x8, x29 +; CHECK-NEXT: eor x13, x13, x25 +; CHECK-NEXT: mul x27, x11, x28 +; CHECK-NEXT: eor x8, x8, x30 +; CHECK-NEXT: and x25, x10, #0x1000000000000000 +; CHECK-NEXT: and x10, x10, #0x8000000000000000 +; CHECK-NEXT: eor x8, x9, x8 +; CHECK-NEXT: eor x9, x13, x24 +; CHECK-NEXT: mul x13, x11, x25 +; CHECK-NEXT: eor x9, x9, x23 +; CHECK-NEXT: eor x9, x9, x21 +; CHECK-NEXT: mul x10, x11, x10 +; CHECK-NEXT: eor x11, x19, x16 +; CHECK-NEXT: eor x9, x9, x20 +; CHECK-NEXT: eor x16, x6, x27 +; CHECK-NEXT: eor x9, x9, x7 +; CHECK-NEXT: eor x9, x9, x5 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x9, x18, x17 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x9, x11, x15 +; CHECK-NEXT: eor x11, x16, x13 +; CHECK-NEXT: rbit x8, x8 +; CHECK-NEXT: eor x9, x9, x14 +; CHECK-NEXT: eor x11, x11, x3 +; CHECK-NEXT: eor x13, x26, x22 +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: eor x11, x11, x1 +; CHECK-NEXT: lsr x1, x8, #1 +; CHECK-NEXT: eor x8, x13, x9 +; CHECK-NEXT: eor x9, x11, x10 +; CHECK-NEXT: eor x0, x8, x9 +; CHECK-NEXT: add sp, sp, #624 +; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload +; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload +; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload +; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload +; CHECK-NEXT: ldp x28, x27, [sp, #16] // 16-byte Folded Reload +; CHECK-NEXT: ldp x29, x30, [sp], #96 // 16-byte Folded Reload +; CHECK-NEXT: ret + %zextx = zext <1 x i64> %x to <1 x i128> + %zexty = zext <1 x i64> %y to <1 x i128> + %a = call <1 x i128> @llvm.clmul.v2i128(<1 x i128> %zextx, <1 x i128> %zexty) + ret <1 x i128> %a +} + +define <2 x i128> @clmul_v2i128_neon_zext(<2 x i64> %x, <2 x i64> %y) { +; CHECK-LABEL: clmul_v2i128_neon_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x29, x30, [sp, #-96]! // 16-byte Folded Spill +; CHECK-NEXT: stp x28, x27, [sp, #16] // 16-byte Folded Spill +; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill +; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill +; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill +; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill +; CHECK-NEXT: sub sp, sp, #1376 +; CHECK-NEXT: .cfi_def_cfa_offset 1472 +; CHECK-NEXT: .cfi_offset w19, -8 +; CHECK-NEXT: .cfi_offset w20, -16 +; CHECK-NEXT: .cfi_offset w21, -24 +; CHECK-NEXT: .cfi_offset w22, -32 +; CHECK-NEXT: .cfi_offset w23, -40 +; CHECK-NEXT: .cfi_offset w24, -48 +; CHECK-NEXT: .cfi_offset w25, -56 +; CHECK-NEXT: .cfi_offset w26, -64 +; CHECK-NEXT: .cfi_offset w27, -72 +; CHECK-NEXT: .cfi_offset w28, -80 +; CHECK-NEXT: .cfi_offset w30, -88 +; CHECK-NEXT: .cfi_offset w29, -96 +; CHECK-NEXT: fmov x9, d1 +; CHECK-NEXT: fmov x8, d0 +; CHECK-NEXT: and x10, x9, #0x2 +; CHECK-NEXT: mul x0, x8, x10 +; CHECK-NEXT: and x10, x9, #0x1 +; CHECK-NEXT: mul x5, x8, x10 +; CHECK-NEXT: and x10, x9, #0x4 +; CHECK-NEXT: mul x7, x8, x10 +; CHECK-NEXT: and x10, x9, #0x8 +; CHECK-NEXT: mul x24, x8, x10 +; CHECK-NEXT: and x10, x9, #0x10 +; CHECK-NEXT: eor x0, x5, x0 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: eor x5, x7, x24 +; CHECK-NEXT: str x10, [sp, #1368] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1360] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1352] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: ldr x7, [sp, #1352] // 8-byte Reload +; CHECK-NEXT: str x10, [sp, #1344] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1328] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: ldr x24, [sp, #1328] // 8-byte Reload +; CHECK-NEXT: str x10, [sp, #1320] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1336] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1312] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1304] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1296] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1288] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1280] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x10000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1272] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1248] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1240] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1264] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1232] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1256] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1216] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1176] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1208] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1200] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1192] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1184] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x10000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1224] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1168] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1120] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1112] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1160] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1152] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1136] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1128] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1144] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1104] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1048] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1040] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x10000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1080] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1072] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1064] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1056] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1096] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1088] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1008] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #968] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #960] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #992] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #984] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1000] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x10000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #976] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1032] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1024] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #1016] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #944] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #904] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #936] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #928] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #920] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2000000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #912] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4000000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #952] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8000000000000000 +; CHECK-NEXT: rbit x9, x9 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: rbit x8, x8 +; CHECK-NEXT: str x10, [sp, #448] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #896] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #888] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #880] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #872] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x10 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #864] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #856] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #848] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #840] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #832] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #824] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #816] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #808] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #800] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #792] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #784] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #776] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x10000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #768] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #744] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #736] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #760] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #728] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #752] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #720] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #672] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #704] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #696] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #688] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #680] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x10000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #712] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #664] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #616] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #608] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #632] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #624] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #656] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #648] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #640] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x2000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #600] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x4000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #576] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x8000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #568] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x10000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #560] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #552] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x40000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #544] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #536] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #592] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x200000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #584] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #520] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800000000000 +; CHECK-NEXT: mul x11, x8, x10 +; CHECK-NEXT: and x10, x9, #0x1000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: stp x10, x11, [sp, #456] // 16-byte Folded Spill +; CHECK-NEXT: and x10, x9, #0x2000000000000 +; CHECK-NEXT: mul x11, x8, x10 +; CHECK-NEXT: and x10, x9, #0x4000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: stp x10, x11, [sp, #480] // 16-byte Folded Spill +; CHECK-NEXT: and x10, x9, #0x8000000000000 +; CHECK-NEXT: mul x11, x8, x10 +; CHECK-NEXT: and x10, x9, #0x10000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #472] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x20000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: stp x10, x11, [sp, #504] // 16-byte Folded Spill +; CHECK-NEXT: and x10, x9, #0x40000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #496] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x80000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #528] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x100000000000000 +; CHECK-NEXT: mul x11, x8, x10 +; CHECK-NEXT: and x10, x9, #0x200000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #400] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x400000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #424] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x800000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: str x10, [sp, #416] // 8-byte Spill +; CHECK-NEXT: and x10, x9, #0x1000000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: stp x10, x11, [sp, #432] // 16-byte Folded Spill +; CHECK-NEXT: and x10, x9, #0x2000000000000000 +; CHECK-NEXT: and x9, x9, #0x4000000000000000 +; CHECK-NEXT: mul x10, x8, x10 +; CHECK-NEXT: mov x11, v1.d[1] +; CHECK-NEXT: mul x8, x8, x9 +; CHECK-NEXT: str x10, [sp, #408] // 8-byte Spill +; CHECK-NEXT: mov x10, v0.d[1] +; CHECK-NEXT: str x8, [sp, #392] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x2 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #296] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x1 +; CHECK-NEXT: mul x9, x10, x8 +; CHECK-NEXT: and x8, x11, #0x4 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #224] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x8 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #168] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x10 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #272] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x20 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #216] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x40 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: stp x8, x9, [sp, #248] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x11, #0x80 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #136] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x100 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #88] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x200 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: ldr x28, [sp, #88] // 8-byte Reload +; CHECK-NEXT: str x8, [sp, #104] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x400 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #160] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x800 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #264] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x1000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #208] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x2000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #240] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x4000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #288] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x8000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #304] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x10000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #48] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x20000 +; CHECK-NEXT: mul x26, x10, x8 +; CHECK-NEXT: and x8, x11, #0x40000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #16] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x80000 +; CHECK-NEXT: mul x9, x10, x8 +; CHECK-NEXT: and x8, x11, #0x100000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: stp x9, x8, [sp, #72] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x11, #0x200000 +; CHECK-NEXT: mul x9, x10, x8 +; CHECK-NEXT: and x8, x11, #0x400000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #184] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x800000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #128] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x1000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #120] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x2000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: stp x8, x9, [sp, #144] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x11, #0x4000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #200] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x8000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #232] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x10000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #280] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x20000000 +; CHECK-NEXT: mul x20, x10, x8 +; CHECK-NEXT: and x8, x11, #0x40000000 +; CHECK-NEXT: mul x15, x10, x8 +; CHECK-NEXT: and x8, x11, #0x80000000 +; CHECK-NEXT: mul x19, x10, x8 +; CHECK-NEXT: and x8, x11, #0x100000000 +; CHECK-NEXT: mul x22, x10, x8 +; CHECK-NEXT: and x8, x11, #0x200000000 +; CHECK-NEXT: eor x15, x20, x15 +; CHECK-NEXT: mul x25, x10, x8 +; CHECK-NEXT: and x8, x11, #0x400000000 +; CHECK-NEXT: eor x15, x15, x19 +; CHECK-NEXT: mul x29, x10, x8 +; CHECK-NEXT: and x8, x11, #0x800000000 +; CHECK-NEXT: eor x15, x15, x22 +; CHECK-NEXT: mul x9, x10, x8 +; CHECK-NEXT: and x8, x11, #0x1000000000 +; CHECK-NEXT: eor x15, x15, x25 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: eor x15, x15, x29 +; CHECK-NEXT: str x8, [sp, #64] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x2000000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: stp x8, x9, [sp, #32] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x11, #0x4000000000 +; CHECK-NEXT: and x9, x11, #0x400000000000000 +; CHECK-NEXT: mul x27, x10, x8 +; CHECK-NEXT: and x8, x11, #0x8000000000 +; CHECK-NEXT: mul x30, x10, x8 +; CHECK-NEXT: and x8, x11, #0x10000000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: mul x13, x10, x9 +; CHECK-NEXT: rbit x9, x10 +; CHECK-NEXT: str x8, [sp, #24] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x20000000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #56] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x40000000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #96] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x80000000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #112] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x100000000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #176] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x200000000000 +; CHECK-NEXT: mul x8, x10, x8 +; CHECK-NEXT: str x8, [sp, #192] // 8-byte Spill +; CHECK-NEXT: and x8, x11, #0x400000000000 +; CHECK-NEXT: mul x17, x10, x8 +; CHECK-NEXT: and x8, x11, #0x800000000000 +; CHECK-NEXT: mul x12, x10, x8 +; CHECK-NEXT: and x8, x11, #0x1000000000000 +; CHECK-NEXT: mul x14, x10, x8 +; CHECK-NEXT: and x8, x11, #0x2000000000000 +; CHECK-NEXT: mul x18, x10, x8 +; CHECK-NEXT: and x8, x11, #0x4000000000000 +; CHECK-NEXT: eor x12, x17, x12 +; CHECK-NEXT: mul x1, x10, x8 +; CHECK-NEXT: and x8, x11, #0x8000000000000 +; CHECK-NEXT: eor x12, x12, x14 +; CHECK-NEXT: mul x3, x10, x8 +; CHECK-NEXT: and x8, x11, #0x10000000000000 +; CHECK-NEXT: eor x12, x12, x18 +; CHECK-NEXT: mul x6, x10, x8 +; CHECK-NEXT: and x8, x11, #0x20000000000000 +; CHECK-NEXT: eor x12, x12, x1 +; CHECK-NEXT: mul x21, x10, x8 +; CHECK-NEXT: and x8, x11, #0x40000000000000 +; CHECK-NEXT: eor x12, x12, x3 +; CHECK-NEXT: mul x23, x10, x8 +; CHECK-NEXT: and x8, x11, #0x100000000000000 +; CHECK-NEXT: eor x12, x12, x6 +; CHECK-NEXT: mul x4, x10, x8 +; CHECK-NEXT: and x8, x11, #0x200000000000000 +; CHECK-NEXT: eor x12, x12, x21 +; CHECK-NEXT: mul x2, x10, x8 +; CHECK-NEXT: rbit x8, x11 +; CHECK-NEXT: eor x12, x12, x23 +; CHECK-NEXT: and x16, x8, #0x2 +; CHECK-NEXT: and x14, x8, #0x800000000 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: mul x14, x9, x14 +; CHECK-NEXT: str x16, [sp, #384] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x1 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #376] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x4 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #368] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x8 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #360] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x10 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #352] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x20 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #336] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x40 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #344] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x80 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #328] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x100 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #320] // 8-byte Spill +; CHECK-NEXT: and x16, x8, #0x200 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: str x16, [sp, #312] // 8-byte Spill +; CHECK-NEXT: eor x16, x0, x5 +; CHECK-NEXT: ldr x0, [sp, #1368] // 8-byte Reload +; CHECK-NEXT: ldr x5, [sp, #1360] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: and x5, x8, #0x400 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #1344] // 8-byte Reload +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #1320] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x24 +; CHECK-NEXT: ldr x24, [sp, #1304] // 8-byte Reload +; CHECK-NEXT: eor x0, x7, x0 +; CHECK-NEXT: ldr x7, [sp, #1336] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1360] // 8-byte Spill +; CHECK-NEXT: and x5, x8, #0x800 +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: ldr x7, [sp, #1312] // 8-byte Reload +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #1296] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x24 +; CHECK-NEXT: ldr x24, [sp, #1248] // 8-byte Reload +; CHECK-NEXT: eor x0, x7, x0 +; CHECK-NEXT: ldr x7, [sp, #1288] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1352] // 8-byte Spill +; CHECK-NEXT: and x5, x8, #0x1000 +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: ldr x7, [sp, #1272] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x24 +; CHECK-NEXT: ldr x24, [sp, #1256] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1336] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #1280] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: ldr x5, [sp, #1240] // 8-byte Reload +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #1264] // 8-byte Reload +; CHECK-NEXT: eor x5, x7, x5 +; CHECK-NEXT: and x7, x8, #0x2000 +; CHECK-NEXT: eor x0, x5, x0 +; CHECK-NEXT: mul x5, x9, x7 +; CHECK-NEXT: ldr x7, [sp, #1176] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1328] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #1232] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: ldr x5, [sp, #1216] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x24 +; CHECK-NEXT: ldr x24, [sp, #1208] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x7 +; CHECK-NEXT: and x7, x8, #0x4000 +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #1200] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x24 +; CHECK-NEXT: mul x7, x9, x7 +; CHECK-NEXT: ldr x24, [sp, #1120] // 8-byte Reload +; CHECK-NEXT: str x14, [sp, #1120] // 8-byte Spill +; CHECK-NEXT: ldr x14, [sp, #112] // 8-byte Reload +; CHECK-NEXT: eor x0, x5, x0 +; CHECK-NEXT: and x5, x8, #0x8000 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: str x7, [sp, #1320] // 8-byte Spill +; CHECK-NEXT: ldr x7, [sp, #1192] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #1168] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1312] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #1184] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x24 +; CHECK-NEXT: ldr x24, [sp, #1224] // 8-byte Reload +; CHECK-NEXT: str x12, [sp, #1184] // 8-byte Spill +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: ldr x5, [sp, #1112] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x24 +; CHECK-NEXT: ldr x24, [sp, #1160] // 8-byte Reload +; CHECK-NEXT: eor x5, x7, x5 +; CHECK-NEXT: and x7, x8, #0x10000 +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: mul x7, x9, x7 +; CHECK-NEXT: ldr x0, [sp, #1152] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x24 +; CHECK-NEXT: ldr x24, [sp, #1048] // 8-byte Reload +; CHECK-NEXT: eor x0, x5, x0 +; CHECK-NEXT: and x5, x8, #0x20000 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: str x7, [sp, #1304] // 8-byte Spill +; CHECK-NEXT: ldr x7, [sp, #1136] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #1104] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1296] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #1128] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x24 +; CHECK-NEXT: ldr x24, [sp, #1144] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: ldr x5, [sp, #1040] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x24 +; CHECK-NEXT: ldr x24, [sp, #1080] // 8-byte Reload +; CHECK-NEXT: eor x5, x7, x5 +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #1072] // 8-byte Reload +; CHECK-NEXT: and x7, x8, #0x40000 +; CHECK-NEXT: eor x5, x5, x24 +; CHECK-NEXT: ldr x24, [sp, #968] // 8-byte Reload +; CHECK-NEXT: mul x7, x9, x7 +; CHECK-NEXT: eor x0, x5, x0 +; CHECK-NEXT: and x5, x8, #0x80000 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: str x7, [sp, #1288] // 8-byte Spill +; CHECK-NEXT: ldr x7, [sp, #1064] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1280] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #1056] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #1008] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: ldr x5, [sp, #960] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x24 +; CHECK-NEXT: ldr x24, [sp, #1096] // 8-byte Reload +; CHECK-NEXT: eor x5, x7, x5 +; CHECK-NEXT: and x7, x8, #0x100000 +; CHECK-NEXT: mul x7, x9, x7 +; CHECK-NEXT: eor x0, x0, x24 +; CHECK-NEXT: ldr x24, [sp, #992] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x24 +; CHECK-NEXT: ldr x24, [sp, #1032] // 8-byte Reload +; CHECK-NEXT: str x7, [sp, #1272] // 8-byte Spill +; CHECK-NEXT: ldr x7, [sp, #1088] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #984] // 8-byte Reload +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #1000] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x7 +; CHECK-NEXT: and x7, x8, #0x200000 +; CHECK-NEXT: eor x0, x5, x0 +; CHECK-NEXT: mul x5, x9, x7 +; CHECK-NEXT: ldr x7, [sp, #904] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1264] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #976] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: ldr x5, [sp, #944] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x24 +; CHECK-NEXT: ldr x24, [sp, #936] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x7 +; CHECK-NEXT: and x7, x8, #0x400000 +; CHECK-NEXT: mul x7, x9, x7 +; CHECK-NEXT: eor x5, x5, x24 +; CHECK-NEXT: ldr x24, [sp, #1016] // 8-byte Reload +; CHECK-NEXT: str x7, [sp, #1256] // 8-byte Spill +; CHECK-NEXT: ldr x7, [sp, #1024] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #928] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x24 +; CHECK-NEXT: ldr x24, [sp, #920] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x7 +; CHECK-NEXT: and x7, x8, #0x800000 +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: mul x7, x9, x7 +; CHECK-NEXT: and x0, x8, #0x1000000 +; CHECK-NEXT: str x16, [sp, #1368] // 8-byte Spill +; CHECK-NEXT: ldr x16, [sp, #912] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x24 +; CHECK-NEXT: ldr x24, [sp, #168] // 8-byte Reload +; CHECK-NEXT: mul x0, x9, x0 +; CHECK-NEXT: eor x16, x5, x16 +; CHECK-NEXT: ldr x5, [sp, #296] // 8-byte Reload +; CHECK-NEXT: str x7, [sp, #1240] // 8-byte Spill +; CHECK-NEXT: ldr x7, [sp, #256] // 8-byte Reload +; CHECK-NEXT: eor x5, x7, x5 +; CHECK-NEXT: ldr x7, [sp, #224] // 8-byte Reload +; CHECK-NEXT: str x0, [sp, #1232] // 8-byte Spill +; CHECK-NEXT: ldr x0, [sp, #952] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x24 +; CHECK-NEXT: ldr x24, [sp, #216] // 8-byte Reload +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: eor x0, x5, x7 +; CHECK-NEXT: and x5, x8, #0x2000000 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: ldr x7, [sp, #272] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x24 +; CHECK-NEXT: ldr x24, [sp, #136] // 8-byte Reload +; CHECK-NEXT: eor x24, x24, x28 +; CHECK-NEXT: str x5, [sp, #1224] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #248] // 8-byte Reload +; CHECK-NEXT: eor x5, x7, x5 +; CHECK-NEXT: ldr x7, [sp, #104] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: ldr x5, [sp, #160] // 8-byte Reload +; CHECK-NEXT: eor x7, x24, x7 +; CHECK-NEXT: and x24, x8, #0x4000000 +; CHECK-NEXT: eor x5, x7, x5 +; CHECK-NEXT: mul x7, x9, x24 +; CHECK-NEXT: ldr x24, [sp, #288] // 8-byte Reload +; CHECK-NEXT: str x7, [sp, #1216] // 8-byte Spill +; CHECK-NEXT: ldr x7, [sp, #448] // 8-byte Reload +; CHECK-NEXT: eor x16, x16, x7 +; CHECK-NEXT: ldr x7, [sp, #208] // 8-byte Reload +; CHECK-NEXT: str x16, [sp, #1344] // 8-byte Spill +; CHECK-NEXT: eor x16, x0, x5 +; CHECK-NEXT: and x0, x8, #0x8000000 +; CHECK-NEXT: mul x0, x9, x0 +; CHECK-NEXT: ldr x5, [sp, #264] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x7 +; CHECK-NEXT: ldr x7, [sp, #48] // 8-byte Reload +; CHECK-NEXT: eor x7, x7, x26 +; CHECK-NEXT: str x0, [sp, #1208] // 8-byte Spill +; CHECK-NEXT: ldr x0, [sp, #240] // 8-byte Reload +; CHECK-NEXT: eor x0, x5, x0 +; CHECK-NEXT: ldr x5, [sp, #16] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x24 +; CHECK-NEXT: ldr x24, [sp, #72] // 8-byte Reload +; CHECK-NEXT: eor x5, x7, x5 +; CHECK-NEXT: and x7, x8, #0x10000000 +; CHECK-NEXT: mul x7, x9, x7 +; CHECK-NEXT: eor x5, x5, x24 +; CHECK-NEXT: str x7, [sp, #1192] // 8-byte Spill +; CHECK-NEXT: ldr x7, [sp, #304] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #80] // 8-byte Reload +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #152] // 8-byte Reload +; CHECK-NEXT: eor x5, x5, x7 +; CHECK-NEXT: and x7, x8, #0x20000000 +; CHECK-NEXT: eor x0, x5, x0 +; CHECK-NEXT: mul x5, x9, x7 +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #184] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1176] // 8-byte Spill +; CHECK-NEXT: ldp x7, x5, [sp, #120] // 16-byte Folded Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: and x5, x8, #0x40000000 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #200] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1160] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #144] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: and x5, x8, #0x80000000 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: ldr x7, [sp, #280] // 8-byte Reload +; CHECK-NEXT: str x5, [sp, #1152] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #232] // 8-byte Reload +; CHECK-NEXT: eor x0, x0, x5 +; CHECK-NEXT: and x5, x8, #0x100000000 +; CHECK-NEXT: mul x5, x9, x5 +; CHECK-NEXT: eor x0, x0, x7 +; CHECK-NEXT: eor x16, x16, x0 +; CHECK-NEXT: ldr x0, [sp, #40] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x0 +; CHECK-NEXT: and x0, x8, #0x200000000 +; CHECK-NEXT: mul x0, x9, x0 +; CHECK-NEXT: str x5, [sp, #1144] // 8-byte Spill +; CHECK-NEXT: ldr x5, [sp, #64] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x5 +; CHECK-NEXT: ldr x5, [sp, #32] // 8-byte Reload +; CHECK-NEXT: eor x15, x16, x15 +; CHECK-NEXT: and x16, x8, #0x400000000 +; CHECK-NEXT: mul x16, x9, x16 +; CHECK-NEXT: eor x5, x5, x27 +; CHECK-NEXT: str x0, [sp, #1136] // 8-byte Spill +; CHECK-NEXT: ldr x0, [sp, #24] // 8-byte Reload +; CHECK-NEXT: str x15, [sp, #1248] // 8-byte Spill +; CHECK-NEXT: eor x15, x5, x30 +; CHECK-NEXT: eor x15, x15, x0 +; CHECK-NEXT: str x16, [sp, #1128] // 8-byte Spill +; CHECK-NEXT: ldr x16, [sp, #56] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: ldr x16, [sp, #96] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: ldr x16, [sp, #176] // 8-byte Reload +; CHECK-NEXT: eor x14, x15, x14 +; CHECK-NEXT: and x15, x8, #0x1000000000 +; CHECK-NEXT: mul x15, x9, x15 +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: ldr x16, [sp, #832] // 8-byte Reload +; CHECK-NEXT: str x15, [sp, #1112] // 8-byte Spill +; CHECK-NEXT: ldr x15, [sp, #192] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: eor x15, x4, x2 +; CHECK-NEXT: eor x12, x15, x13 +; CHECK-NEXT: str x14, [sp, #1200] // 8-byte Spill +; CHECK-NEXT: and x14, x8, #0x2000000000 +; CHECK-NEXT: str x12, [sp, #1168] // 8-byte Spill +; CHECK-NEXT: and x12, x8, #0x4000000000 +; CHECK-NEXT: mul x28, x9, x14 +; CHECK-NEXT: ldr x13, [sp, #896] // 8-byte Reload +; CHECK-NEXT: ldr x14, [sp, #888] // 8-byte Reload +; CHECK-NEXT: ldr x15, [sp, #872] // 8-byte Reload +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: ldr x14, [sp, #880] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: ldr x15, [sp, #848] // 8-byte Reload +; CHECK-NEXT: str x12, [sp, #1104] // 8-byte Spill +; CHECK-NEXT: eor x12, x13, x14 +; CHECK-NEXT: ldr x13, [sp, #864] // 8-byte Reload +; CHECK-NEXT: ldr x14, [sp, #856] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: and x14, x8, #0x8000000000 +; CHECK-NEXT: mul x14, x9, x14 +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #840] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #824] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: ldr x16, [sp, #800] // 8-byte Reload +; CHECK-NEXT: eor x13, x15, x13 +; CHECK-NEXT: ldr x15, [sp, #816] // 8-byte Reload +; CHECK-NEXT: str x14, [sp, #1096] // 8-byte Spill +; CHECK-NEXT: and x14, x8, #0x10000000000 +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: mul x14, x9, x14 +; CHECK-NEXT: ldr x15, [sp, #808] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #792] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: ldr x16, [sp, #744] // 8-byte Reload +; CHECK-NEXT: eor x13, x15, x13 +; CHECK-NEXT: ldr x15, [sp, #784] // 8-byte Reload +; CHECK-NEXT: str x14, [sp, #1088] // 8-byte Spill +; CHECK-NEXT: and x14, x8, #0x20000000000 +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: mul x26, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #776] // 8-byte Reload +; CHECK-NEXT: ldr x15, [sp, #768] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #736] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #760] // 8-byte Reload +; CHECK-NEXT: ldr x16, [sp, #752] // 8-byte Reload +; CHECK-NEXT: eor x14, x15, x14 +; CHECK-NEXT: and x15, x8, #0x40000000000 +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: ldr x14, [sp, #728] // 8-byte Reload +; CHECK-NEXT: mul x25, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #672] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #720] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #704] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: and x15, x8, #0x80000000000 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #696] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: mul x27, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #688] // 8-byte Reload +; CHECK-NEXT: ldr x16, [sp, #616] // 8-byte Reload +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: and x14, x8, #0x100000000000 +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #664] // 8-byte Reload +; CHECK-NEXT: mul x29, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #680] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: ldr x16, [sp, #712] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #608] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #632] // 8-byte Reload +; CHECK-NEXT: eor x14, x15, x14 +; CHECK-NEXT: and x15, x8, #0x200000000000 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #624] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: mul x30, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #656] // 8-byte Reload +; CHECK-NEXT: ldr x16, [sp, #576] // 8-byte Reload +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: and x14, x8, #0x400000000000 +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #600] // 8-byte Reload +; CHECK-NEXT: mul x24, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #648] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: ldr x16, [sp, #640] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #568] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #560] // 8-byte Reload +; CHECK-NEXT: eor x14, x15, x14 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #552] // 8-byte Reload +; CHECK-NEXT: and x15, x8, #0x800000000000 +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: ldr x16, [sp, #464] // 8-byte Reload +; CHECK-NEXT: mul x23, x9, x15 +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: and x14, x8, #0x1000000000000 +; CHECK-NEXT: ldr x15, [sp, #544] // 8-byte Reload +; CHECK-NEXT: mul x22, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #536] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #520] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #456] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: ldr x16, [sp, #592] // 8-byte Reload +; CHECK-NEXT: eor x14, x15, x14 +; CHECK-NEXT: and x15, x8, #0x2000000000000 +; CHECK-NEXT: mul x20, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #584] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #488] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #480] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldp x16, x13, [sp, #504] // 16-byte Folded Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: and x15, x8, #0x4000000000000 +; CHECK-NEXT: mul x7, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #400] // 8-byte Reload +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: ldr x14, [sp, #472] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #440] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #424] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: and x15, x8, #0x8000000000000 +; CHECK-NEXT: mul x6, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #496] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: ldr x16, [sp, #528] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: ldr x15, [sp, #416] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #432] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x15 +; CHECK-NEXT: eor x21, x12, x13 +; CHECK-NEXT: ldr x12, [sp, #408] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x16 +; CHECK-NEXT: and x13, x8, #0x20000000000000 +; CHECK-NEXT: and x15, x8, #0x10000000000000 +; CHECK-NEXT: eor x12, x14, x12 +; CHECK-NEXT: ldr x14, [sp, #392] // 8-byte Reload +; CHECK-NEXT: mul x4, x9, x13 +; CHECK-NEXT: ldr x16, [sp, #1336] // 8-byte Reload +; CHECK-NEXT: eor x19, x12, x14 +; CHECK-NEXT: ldp x14, x12, [sp, #376] // 16-byte Folded Reload +; CHECK-NEXT: mul x5, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #336] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x12 +; CHECK-NEXT: ldp x13, x12, [sp, #360] // 16-byte Folded Reload +; CHECK-NEXT: eor x13, x12, x13 +; CHECK-NEXT: ldr x12, [sp, #352] // 8-byte Reload +; CHECK-NEXT: eor x14, x14, x13 +; CHECK-NEXT: ldr x13, [sp, #344] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x15 +; CHECK-NEXT: and x15, x8, #0x40000000000000 +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: mul x3, x9, x15 +; CHECK-NEXT: and x15, x8, #0x80000000000000 +; CHECK-NEXT: eor x14, x14, x12 +; CHECK-NEXT: ldp x13, x12, [sp, #320] // 16-byte Folded Reload +; CHECK-NEXT: mul x2, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #1360] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #312] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #1352] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x15 +; CHECK-NEXT: ldr x15, [sp, #1328] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: eor x12, x14, x12 +; CHECK-NEXT: ldr x14, [sp, #1320] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: and x15, x8, #0x100000000000000 +; CHECK-NEXT: ldr x16, [sp, #1272] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #1312] // 8-byte Reload +; CHECK-NEXT: mul x1, x9, x15 +; CHECK-NEXT: ldr x15, [sp, #1296] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #1304] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #1288] // 8-byte Reload +; CHECK-NEXT: eor x15, x14, x15 +; CHECK-NEXT: and x14, x8, #0x200000000000000 +; CHECK-NEXT: mul x0, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #1280] // 8-byte Reload +; CHECK-NEXT: eor x13, x15, x13 +; CHECK-NEXT: ldr x15, [sp, #1240] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #1256] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #1232] // 8-byte Reload +; CHECK-NEXT: eor x15, x14, x15 +; CHECK-NEXT: and x14, x8, #0x400000000000000 +; CHECK-NEXT: mul x18, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #1264] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: ldr x16, [sp, #1192] // 8-byte Reload +; CHECK-NEXT: eor x0, x1, x0 +; CHECK-NEXT: and x1, x11, #0x2000000000000000 +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #1224] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: ldr x13, [sp, #1216] // 8-byte Reload +; CHECK-NEXT: eor x15, x15, x14 +; CHECK-NEXT: and x14, x8, #0x800000000000000 +; CHECK-NEXT: mul x17, x9, x14 +; CHECK-NEXT: ldr x14, [sp, #1208] // 8-byte Reload +; CHECK-NEXT: eor x13, x15, x13 +; CHECK-NEXT: ldr x15, [sp, #1160] // 8-byte Reload +; CHECK-NEXT: eor x18, x0, x18 +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: ldr x14, [sp, #1176] // 8-byte Reload +; CHECK-NEXT: mul x0, x10, x1 +; CHECK-NEXT: eor x13, x13, x16 +; CHECK-NEXT: ldr x16, [sp, #1152] // 8-byte Reload +; CHECK-NEXT: eor x15, x14, x15 +; CHECK-NEXT: and x14, x8, #0x1000000000000000 +; CHECK-NEXT: eor x15, x15, x16 +; CHECK-NEXT: mul x16, x9, x14 +; CHECK-NEXT: eor x14, x12, x13 +; CHECK-NEXT: ldr x12, [sp, #1144] // 8-byte Reload +; CHECK-NEXT: eor x17, x18, x17 +; CHECK-NEXT: and x18, x11, #0x4000000000000000 +; CHECK-NEXT: eor x13, x15, x12 +; CHECK-NEXT: ldr x12, [sp, #1136] // 8-byte Reload +; CHECK-NEXT: and x15, x8, #0x2000000000000000 +; CHECK-NEXT: and x8, x8, #0x4000000000000000 +; CHECK-NEXT: mul x15, x9, x15 +; CHECK-NEXT: eor x13, x13, x12 +; CHECK-NEXT: ldr x12, [sp, #1104] // 8-byte Reload +; CHECK-NEXT: eor x16, x17, x16 +; CHECK-NEXT: mul x8, x9, x8 +; CHECK-NEXT: ldr x9, [sp, #1112] // 8-byte Reload +; CHECK-NEXT: eor x12, x28, x12 +; CHECK-NEXT: ldr x28, [sp, #1128] // 8-byte Reload +; CHECK-NEXT: mul x17, x10, x18 +; CHECK-NEXT: eor x13, x13, x28 +; CHECK-NEXT: ldr x28, [sp, #1096] // 8-byte Reload +; CHECK-NEXT: eor x15, x16, x15 +; CHECK-NEXT: eor x12, x12, x28 +; CHECK-NEXT: ldr x28, [sp, #1120] // 8-byte Reload +; CHECK-NEXT: eor x8, x15, x8 +; CHECK-NEXT: eor x13, x13, x28 +; CHECK-NEXT: ldr x28, [sp, #1088] // 8-byte Reload +; CHECK-NEXT: eor x9, x13, x9 +; CHECK-NEXT: and x13, x11, #0x80000000000000 +; CHECK-NEXT: eor x12, x12, x28 +; CHECK-NEXT: eor x9, x14, x9 +; CHECK-NEXT: eor x14, x24, x23 +; CHECK-NEXT: eor x12, x12, x26 +; CHECK-NEXT: eor x14, x14, x22 +; CHECK-NEXT: and x23, x11, #0x800000000000000 +; CHECK-NEXT: eor x12, x12, x25 +; CHECK-NEXT: eor x14, x14, x20 +; CHECK-NEXT: mul x22, x10, x23 +; CHECK-NEXT: eor x12, x12, x27 +; CHECK-NEXT: and x20, x11, #0x1000000000000000 +; CHECK-NEXT: and x11, x11, #0x8000000000000000 +; CHECK-NEXT: eor x12, x12, x29 +; CHECK-NEXT: mul x13, x10, x13 +; CHECK-NEXT: eor x12, x12, x30 +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: eor x12, x14, x7 +; CHECK-NEXT: mul x14, x10, x20 +; CHECK-NEXT: eor x12, x12, x6 +; CHECK-NEXT: eor x12, x12, x5 +; CHECK-NEXT: mul x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #1168] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x4 +; CHECK-NEXT: eor x12, x12, x3 +; CHECK-NEXT: eor x11, x11, x22 +; CHECK-NEXT: eor x12, x12, x2 +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: eor x12, x21, x19 +; CHECK-NEXT: eor x8, x9, x8 +; CHECK-NEXT: eor x9, x11, x14 +; CHECK-NEXT: rbit x11, x12 +; CHECK-NEXT: ldr x12, [sp, #1248] // 8-byte Reload +; CHECK-NEXT: ldr x14, [sp, #1200] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x0 +; CHECK-NEXT: rbit x8, x8 +; CHECK-NEXT: eor x9, x9, x17 +; CHECK-NEXT: lsr x1, x11, #1 +; CHECK-NEXT: eor x12, x12, x14 +; CHECK-NEXT: ldr x14, [sp, #1184] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #1368] // 8-byte Reload +; CHECK-NEXT: ldr x11, [sp, #1344] // 8-byte Reload +; CHECK-NEXT: lsr x3, x8, #1 +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: eor x8, x12, x13 +; CHECK-NEXT: eor x0, x10, x11 +; CHECK-NEXT: eor x2, x8, x9 +; CHECK-NEXT: add sp, sp, #1376 +; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload +; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload +; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload +; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload +; CHECK-NEXT: ldp x28, x27, [sp, #16] // 16-byte Folded Reload +; CHECK-NEXT: ldp x29, x30, [sp], #96 // 16-byte Folded Reload +; CHECK-NEXT: ret + %zextx = zext <2 x i64> %x to <2 x i128> + %zexty = zext <2 x i64> %y to <2 x i128> + %a = call <2 x i128> @llvm.clmul.v2i128(<2 x i128> %zextx, <2 x i128> %zexty) + ret <2 x i128> %a +} + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-AES: {{.*}} +; CHECK-NEON: {{.*}} diff --git a/llvm/test/CodeGen/AArch64/clmul-scalable.ll b/llvm/test/CodeGen/AArch64/clmul-scalable.ll new file mode 100644 index 0000000000000..58dbba833f67b --- /dev/null +++ b/llvm/test/CodeGen/AArch64/clmul-scalable.ll @@ -0,0 +1,2242 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=aarch64-linux-unknown-gnu %s -o - -mattr=+sve | FileCheck %s --check-prefix=CHECK-SVE +; RUN: llc -mtriple=aarch64-linux-unknown-gnu %s -o - -mattr=+sve2 | FileCheck %s --check-prefix=CHECK-SVE2 +; RUN: llc -mtriple=aarch64-linux-unknown-gnu %s -o - -mattr=+sve2-aes | FileCheck %s --check-prefix=CHECK-SVE2-AES + +define @clmul_nxv16i8( %x, %y) { +; CHECK-SVE-LABEL: clmul_nxv16i8: +; CHECK-SVE: // %bb.0: +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: ptrue p0.b +; CHECK-SVE-NEXT: and z1.b, z1.b, #0x80 +; CHECK-SVE-NEXT: and z2.b, z2.b, #0x2 +; CHECK-SVE-NEXT: and z3.b, z3.b, #0x1 +; CHECK-SVE-NEXT: and z4.b, z4.b, #0x4 +; CHECK-SVE-NEXT: and z5.b, z5.b, #0x8 +; CHECK-SVE-NEXT: and z6.b, z6.b, #0x10 +; CHECK-SVE-NEXT: and z7.b, z7.b, #0x20 +; CHECK-SVE-NEXT: and z24.b, z24.b, #0x40 +; CHECK-SVE-NEXT: mul z2.b, p0/m, z2.b, z0.b +; CHECK-SVE-NEXT: mul z3.b, p0/m, z3.b, z0.b +; CHECK-SVE-NEXT: mul z4.b, p0/m, z4.b, z0.b +; CHECK-SVE-NEXT: mul z5.b, p0/m, z5.b, z0.b +; CHECK-SVE-NEXT: mul z6.b, p0/m, z6.b, z0.b +; CHECK-SVE-NEXT: mul z7.b, p0/m, z7.b, z0.b +; CHECK-SVE-NEXT: mul z24.b, p0/m, z24.b, z0.b +; CHECK-SVE-NEXT: mul z0.b, p0/m, z0.b, z1.b +; CHECK-SVE-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z5.d +; CHECK-SVE-NEXT: eor z4.d, z6.d, z7.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z24.d +; CHECK-SVE-NEXT: eor z1.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z0.d, z1.d, z0.d +; CHECK-SVE-NEXT: ret +; +; CHECK-SVE2-LABEL: clmul_nxv16i8: +; CHECK-SVE2: // %bb.0: +; CHECK-SVE2-NEXT: pmul z0.b, z0.b, z1.b +; CHECK-SVE2-NEXT: ret +; +; CHECK-SVE2-AES-LABEL: clmul_nxv16i8: +; CHECK-SVE2-AES: // %bb.0: +; CHECK-SVE2-AES-NEXT: pmul z0.b, z0.b, z1.b +; CHECK-SVE2-AES-NEXT: ret + %a = call @llvm.clmul.nxv16i8( %x, %y) + ret %a +} + +define @clmul_nxv8i16( %x, %y) { +; CHECK-SVE-LABEL: clmul_nxv8i16: +; CHECK-SVE: // %bb.0: +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: ptrue p0.h +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: and z2.h, z2.h, #0x2 +; CHECK-SVE-NEXT: and z3.h, z3.h, #0x1 +; CHECK-SVE-NEXT: and z4.h, z4.h, #0x4 +; CHECK-SVE-NEXT: and z5.h, z5.h, #0x8 +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: and z6.h, z6.h, #0x10 +; CHECK-SVE-NEXT: and z7.h, z7.h, #0x20 +; CHECK-SVE-NEXT: and z24.h, z24.h, #0x80 +; CHECK-SVE-NEXT: mul z2.h, p0/m, z2.h, z0.h +; CHECK-SVE-NEXT: mul z3.h, p0/m, z3.h, z0.h +; CHECK-SVE-NEXT: and z25.h, z25.h, #0x100 +; CHECK-SVE-NEXT: mul z4.h, p0/m, z4.h, z0.h +; CHECK-SVE-NEXT: mul z5.h, p0/m, z5.h, z0.h +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: mul z6.h, p0/m, z6.h, z0.h +; CHECK-SVE-NEXT: mul z7.h, p0/m, z7.h, z0.h +; CHECK-SVE-NEXT: and z26.h, z26.h, #0x800 +; CHECK-SVE-NEXT: mul z24.h, p0/m, z24.h, z0.h +; CHECK-SVE-NEXT: mul z25.h, p0/m, z25.h, z0.h +; CHECK-SVE-NEXT: and z27.h, z27.h, #0x1000 +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: mov z30.d, z1.d +; CHECK-SVE-NEXT: and z28.h, z28.h, #0x40 +; CHECK-SVE-NEXT: mul z26.h, p0/m, z26.h, z0.h +; CHECK-SVE-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z5.d +; CHECK-SVE-NEXT: mul z27.h, p0/m, z27.h, z0.h +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: mul z28.h, p0/m, z28.h, z0.h +; CHECK-SVE-NEXT: and z29.h, z29.h, #0x200 +; CHECK-SVE-NEXT: and z30.h, z30.h, #0x2000 +; CHECK-SVE-NEXT: eor z6.d, z6.d, z7.d +; CHECK-SVE-NEXT: eor z7.d, z24.d, z25.d +; CHECK-SVE-NEXT: and z1.h, z1.h, #0x8000 +; CHECK-SVE-NEXT: and z4.h, z4.h, #0x400 +; CHECK-SVE-NEXT: and z5.h, z5.h, #0x4000 +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: mul z29.h, p0/m, z29.h, z0.h +; CHECK-SVE-NEXT: mul z30.h, p0/m, z30.h, z0.h +; CHECK-SVE-NEXT: eor z24.d, z26.d, z27.d +; CHECK-SVE-NEXT: eor z3.d, z6.d, z28.d +; CHECK-SVE-NEXT: mul z4.h, p0/m, z4.h, z0.h +; CHECK-SVE-NEXT: mul z5.h, p0/m, z5.h, z0.h +; CHECK-SVE-NEXT: mul z0.h, p0/m, z0.h, z1.h +; CHECK-SVE-NEXT: eor z6.d, z7.d, z29.d +; CHECK-SVE-NEXT: eor z7.d, z24.d, z30.d +; CHECK-SVE-NEXT: eor z1.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z2.d, z6.d, z4.d +; CHECK-SVE-NEXT: eor z3.d, z7.d, z5.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z2.d +; CHECK-SVE-NEXT: eor z0.d, z3.d, z0.d +; CHECK-SVE-NEXT: eor z0.d, z1.d, z0.d +; CHECK-SVE-NEXT: ret +; +; CHECK-SVE2-LABEL: clmul_nxv8i16: +; CHECK-SVE2: // %bb.0: +; CHECK-SVE2-NEXT: mov z2.d, z1.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z2.h, z2.h, #0x2 +; CHECK-SVE2-NEXT: and z3.h, z3.h, #0x1 +; CHECK-SVE2-NEXT: and z4.h, z4.h, #0x8 +; CHECK-SVE2-NEXT: and z5.h, z5.h, #0x4 +; CHECK-SVE2-NEXT: and z6.h, z6.h, #0x20 +; CHECK-SVE2-NEXT: mul z2.h, z0.h, z2.h +; CHECK-SVE2-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-NEXT: mul z4.h, z0.h, z4.h +; CHECK-SVE2-NEXT: mul z5.h, z0.h, z5.h +; CHECK-SVE2-NEXT: mul z6.h, z0.h, z6.h +; CHECK-SVE2-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z3.h, z3.h, #0x10 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-NEXT: and z4.h, z4.h, #0x80 +; CHECK-SVE2-NEXT: and z5.h, z5.h, #0x40 +; CHECK-SVE2-NEXT: mul z4.h, z0.h, z4.h +; CHECK-SVE2-NEXT: mul z5.h, z0.h, z5.h +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.h, z3.h, #0x200 +; CHECK-SVE2-NEXT: and z6.h, z6.h, #0x100 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-NEXT: mul z6.h, z0.h, z6.h +; CHECK-SVE2-NEXT: and z4.h, z4.h, #0x800 +; CHECK-SVE2-NEXT: and z5.h, z5.h, #0x400 +; CHECK-SVE2-NEXT: mul z4.h, z0.h, z4.h +; CHECK-SVE2-NEXT: mul z5.h, z0.h, z5.h +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.h, z3.h, #0x2000 +; CHECK-SVE2-NEXT: and z6.h, z6.h, #0x1000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: and z1.h, z1.h, #0x4000 +; CHECK-SVE2-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-NEXT: mul z4.h, z0.h, z6.h +; CHECK-SVE2-NEXT: and z5.h, z5.h, #0x8000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-NEXT: mul z3.h, z0.h, z5.h +; CHECK-SVE2-NEXT: mul z0.h, z0.h, z1.h +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mov z0.d, z2.d +; CHECK-SVE2-NEXT: ret +; +; CHECK-SVE2-AES-LABEL: clmul_nxv8i16: +; CHECK-SVE2-AES: // %bb.0: +; CHECK-SVE2-AES-NEXT: mov z2.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z2.h, z2.h, #0x2 +; CHECK-SVE2-AES-NEXT: and z3.h, z3.h, #0x1 +; CHECK-SVE2-AES-NEXT: and z4.h, z4.h, #0x8 +; CHECK-SVE2-AES-NEXT: and z5.h, z5.h, #0x4 +; CHECK-SVE2-AES-NEXT: and z6.h, z6.h, #0x20 +; CHECK-SVE2-AES-NEXT: mul z2.h, z0.h, z2.h +; CHECK-SVE2-AES-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-AES-NEXT: mul z4.h, z0.h, z4.h +; CHECK-SVE2-AES-NEXT: mul z5.h, z0.h, z5.h +; CHECK-SVE2-AES-NEXT: mul z6.h, z0.h, z6.h +; CHECK-SVE2-AES-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.h, z3.h, #0x10 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-AES-NEXT: and z4.h, z4.h, #0x80 +; CHECK-SVE2-AES-NEXT: and z5.h, z5.h, #0x40 +; CHECK-SVE2-AES-NEXT: mul z4.h, z0.h, z4.h +; CHECK-SVE2-AES-NEXT: mul z5.h, z0.h, z5.h +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.h, z3.h, #0x200 +; CHECK-SVE2-AES-NEXT: and z6.h, z6.h, #0x100 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-AES-NEXT: mul z6.h, z0.h, z6.h +; CHECK-SVE2-AES-NEXT: and z4.h, z4.h, #0x800 +; CHECK-SVE2-AES-NEXT: and z5.h, z5.h, #0x400 +; CHECK-SVE2-AES-NEXT: mul z4.h, z0.h, z4.h +; CHECK-SVE2-AES-NEXT: mul z5.h, z0.h, z5.h +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.h, z3.h, #0x2000 +; CHECK-SVE2-AES-NEXT: and z6.h, z6.h, #0x1000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: and z1.h, z1.h, #0x4000 +; CHECK-SVE2-AES-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-AES-NEXT: mul z4.h, z0.h, z6.h +; CHECK-SVE2-AES-NEXT: and z5.h, z5.h, #0x8000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z3.h, z0.h, z5.h +; CHECK-SVE2-AES-NEXT: mul z0.h, z0.h, z1.h +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z0.d, z2.d +; CHECK-SVE2-AES-NEXT: ret + %a = call @llvm.clmul.nxv8i16( %x, %y) + ret %a +} + +define @clmul_nxv4i32( %x, %y) { +; CHECK-SVE-LABEL: clmul_nxv4i32: +; CHECK-SVE: // %bb.0: +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: ptrue p0.s +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: and z2.s, z2.s, #0x2 +; CHECK-SVE-NEXT: and z3.s, z3.s, #0x1 +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: and z4.s, z4.s, #0x4 +; CHECK-SVE-NEXT: and z5.s, z5.s, #0x8 +; CHECK-SVE-NEXT: and z6.s, z6.s, #0x10 +; CHECK-SVE-NEXT: and z7.s, z7.s, #0x20 +; CHECK-SVE-NEXT: and z24.s, z24.s, #0x80 +; CHECK-SVE-NEXT: and z25.s, z25.s, #0x100 +; CHECK-SVE-NEXT: mul z2.s, p0/m, z2.s, z0.s +; CHECK-SVE-NEXT: mul z3.s, p0/m, z3.s, z0.s +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: mul z4.s, p0/m, z4.s, z0.s +; CHECK-SVE-NEXT: mul z5.s, p0/m, z5.s, z0.s +; CHECK-SVE-NEXT: and z26.s, z26.s, #0x40 +; CHECK-SVE-NEXT: mul z6.s, p0/m, z6.s, z0.s +; CHECK-SVE-NEXT: mul z7.s, p0/m, z7.s, z0.s +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: mul z24.s, p0/m, z24.s, z0.s +; CHECK-SVE-NEXT: mul z25.s, p0/m, z25.s, z0.s +; CHECK-SVE-NEXT: and z27.s, z27.s, #0x200 +; CHECK-SVE-NEXT: mul z26.s, p0/m, z26.s, z0.s +; CHECK-SVE-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: eor z4.d, z4.d, z5.d +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: and z28.s, z28.s, #0x8000 +; CHECK-SVE-NEXT: mul z27.s, p0/m, z27.s, z0.s +; CHECK-SVE-NEXT: eor z5.d, z6.d, z7.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: and z3.s, z3.s, #0x400 +; CHECK-SVE-NEXT: eor z6.d, z24.d, z25.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mul z28.s, p0/m, z28.s, z0.s +; CHECK-SVE-NEXT: eor z2.d, z2.d, z4.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z26.d +; CHECK-SVE-NEXT: and z7.s, z7.s, #0x800 +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: mul z3.s, p0/m, z3.s, z0.s +; CHECK-SVE-NEXT: eor z5.d, z6.d, z27.d +; CHECK-SVE-NEXT: and z24.s, z24.s, #0x1000 +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: and z25.s, z25.s, #0x800000 +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: mul z7.s, p0/m, z7.s, z0.s +; CHECK-SVE-NEXT: eor z2.d, z2.d, z4.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mul z24.s, p0/m, z24.s, z0.s +; CHECK-SVE-NEXT: and z26.s, z26.s, #0x40000 +; CHECK-SVE-NEXT: and z29.s, z29.s, #0x100000 +; CHECK-SVE-NEXT: mul z25.s, p0/m, z25.s, z0.s +; CHECK-SVE-NEXT: eor z3.d, z5.d, z3.d +; CHECK-SVE-NEXT: and z6.s, z6.s, #0x2000 +; CHECK-SVE-NEXT: and z4.s, z4.s, #0x10000 +; CHECK-SVE-NEXT: and z27.s, z27.s, #0x1000000 +; CHECK-SVE-NEXT: mul z26.s, p0/m, z26.s, z0.s +; CHECK-SVE-NEXT: mul z29.s, p0/m, z29.s, z0.s +; CHECK-SVE-NEXT: mul z6.s, p0/m, z6.s, z0.s +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: mul z4.s, p0/m, z4.s, z0.s +; CHECK-SVE-NEXT: mul z27.s, p0/m, z27.s, z0.s +; CHECK-SVE-NEXT: eor z5.d, z7.d, z24.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: and z3.s, z3.s, #0x20000 +; CHECK-SVE-NEXT: eor z5.d, z5.d, z6.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: and z24.s, z24.s, #0x400000 +; CHECK-SVE-NEXT: and z7.s, z7.s, #0x4000 +; CHECK-SVE-NEXT: mul z3.s, p0/m, z3.s, z0.s +; CHECK-SVE-NEXT: and z6.s, z6.s, #0x80000 +; CHECK-SVE-NEXT: mul z24.s, p0/m, z24.s, z0.s +; CHECK-SVE-NEXT: mul z7.s, p0/m, z7.s, z0.s +; CHECK-SVE-NEXT: eor z3.d, z4.d, z3.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mul z6.s, p0/m, z6.s, z0.s +; CHECK-SVE-NEXT: eor z24.d, z24.d, z25.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: eor z5.d, z5.d, z7.d +; CHECK-SVE-NEXT: and z4.s, z4.s, #0x2000000 +; CHECK-SVE-NEXT: eor z3.d, z3.d, z26.d +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: and z25.s, z25.s, #0x4000000 +; CHECK-SVE-NEXT: eor z7.d, z24.d, z27.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mul z4.s, p0/m, z4.s, z0.s +; CHECK-SVE-NEXT: eor z3.d, z3.d, z6.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: and z26.s, z26.s, #0x200000 +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: eor z5.d, z5.d, z28.d +; CHECK-SVE-NEXT: mul z25.s, p0/m, z25.s, z0.s +; CHECK-SVE-NEXT: and z24.s, z24.s, #0x20000000 +; CHECK-SVE-NEXT: and z6.s, z6.s, #0x8000000 +; CHECK-SVE-NEXT: eor z3.d, z3.d, z29.d +; CHECK-SVE-NEXT: eor z4.d, z7.d, z4.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mul z26.s, p0/m, z26.s, z0.s +; CHECK-SVE-NEXT: and z27.s, z27.s, #0x40000000 +; CHECK-SVE-NEXT: mul z24.s, p0/m, z24.s, z0.s +; CHECK-SVE-NEXT: and z1.s, z1.s, #0x80000000 +; CHECK-SVE-NEXT: mul z6.s, p0/m, z6.s, z0.s +; CHECK-SVE-NEXT: eor z2.d, z2.d, z5.d +; CHECK-SVE-NEXT: and z7.s, z7.s, #0x10000000 +; CHECK-SVE-NEXT: eor z4.d, z4.d, z25.d +; CHECK-SVE-NEXT: mul z27.s, p0/m, z27.s, z0.s +; CHECK-SVE-NEXT: eor z3.d, z3.d, z26.d +; CHECK-SVE-NEXT: mul z7.s, p0/m, z7.s, z0.s +; CHECK-SVE-NEXT: eor z4.d, z4.d, z6.d +; CHECK-SVE-NEXT: mul z0.s, p0/m, z0.s, z1.s +; CHECK-SVE-NEXT: eor z1.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z3.d, z24.d, z27.d +; CHECK-SVE-NEXT: eor z2.d, z4.d, z7.d +; CHECK-SVE-NEXT: eor z0.d, z3.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z2.d +; CHECK-SVE-NEXT: eor z0.d, z1.d, z0.d +; CHECK-SVE-NEXT: ret +; +; CHECK-SVE2-LABEL: clmul_nxv4i32: +; CHECK-SVE2: // %bb.0: +; CHECK-SVE2-NEXT: mov z2.d, z1.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z2.s, z2.s, #0x2 +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x1 +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x8 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x4 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x20 +; CHECK-SVE2-NEXT: mul z2.s, z0.s, z2.s +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x10 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x80 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x40 +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x200 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x100 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x800 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x400 +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x2000 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x1000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x8000 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x4000 +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x20000 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x10000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x80000 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x40000 +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x200000 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x100000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x800000 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x400000 +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x2000000 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x1000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x8000000 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x4000000 +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x20000000 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x10000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: and z1.s, z1.s, #0x40000000 +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z6.s +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x80000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z5.s +; CHECK-SVE2-NEXT: mul z0.s, z0.s, z1.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mov z0.d, z2.d +; CHECK-SVE2-NEXT: ret +; +; CHECK-SVE2-AES-LABEL: clmul_nxv4i32: +; CHECK-SVE2-AES: // %bb.0: +; CHECK-SVE2-AES-NEXT: mov z2.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z2.s, z2.s, #0x2 +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x1 +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x8 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x4 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x20 +; CHECK-SVE2-AES-NEXT: mul z2.s, z0.s, z2.s +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x10 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x80 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x40 +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x200 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x100 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x800 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x400 +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x2000 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x1000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x8000 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x4000 +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x20000 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x10000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x80000 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x40000 +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x200000 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x100000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x800000 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x400000 +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x2000000 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x1000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x8000000 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x4000000 +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x20000000 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x10000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: and z1.s, z1.s, #0x40000000 +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x80000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: mul z0.s, z0.s, z1.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z0.d, z2.d +; CHECK-SVE2-AES-NEXT: ret + %a = call @llvm.clmul.nxv4i32( %x, %y) + ret %a +} + +define @clmul_nxv2i64( %x, %y) { +; CHECK-SVE-LABEL: clmul_nxv2i64: +; CHECK-SVE: // %bb.0: +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: ptrue p0.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: and z2.d, z2.d, #0x2 +; CHECK-SVE-NEXT: and z3.d, z3.d, #0x1 +; CHECK-SVE-NEXT: and z4.d, z4.d, #0x4 +; CHECK-SVE-NEXT: and z5.d, z5.d, #0x8 +; CHECK-SVE-NEXT: and z6.d, z6.d, #0x10 +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x20 +; CHECK-SVE-NEXT: and z24.d, z24.d, #0x40 +; CHECK-SVE-NEXT: and z25.d, z25.d, #0x80 +; CHECK-SVE-NEXT: mul z2.d, p0/m, z2.d, z0.d +; CHECK-SVE-NEXT: mul z3.d, p0/m, z3.d, z0.d +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: mul z4.d, p0/m, z4.d, z0.d +; CHECK-SVE-NEXT: mul z5.d, p0/m, z5.d, z0.d +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x100 +; CHECK-SVE-NEXT: mul z6.d, p0/m, z6.d, z0.d +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: mul z24.d, p0/m, z24.d, z0.d +; CHECK-SVE-NEXT: mul z25.d, p0/m, z25.d, z0.d +; CHECK-SVE-NEXT: and z27.d, z27.d, #0x20000 +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z5.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: and z28.d, z28.d, #0x400000 +; CHECK-SVE-NEXT: mul z27.d, p0/m, z27.d, z0.d +; CHECK-SVE-NEXT: eor z4.d, z6.d, z7.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: and z29.d, z29.d, #0x800000 +; CHECK-SVE-NEXT: mov z30.d, z1.d +; CHECK-SVE-NEXT: mul z28.d, p0/m, z28.d, z0.d +; CHECK-SVE-NEXT: and z5.d, z5.d, #0x200 +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: and z6.d, z6.d, #0x800 +; CHECK-SVE-NEXT: eor z3.d, z4.d, z24.d +; CHECK-SVE-NEXT: eor z4.d, z25.d, z26.d +; CHECK-SVE-NEXT: mul z29.d, p0/m, z29.d, z0.d +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x1000 +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: mul z5.d, p0/m, z5.d, z0.d +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mul z6.d, p0/m, z6.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: and z30.d, z30.d, #0x800000000 +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: and z25.d, z25.d, #0x2000 +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x10000 +; CHECK-SVE-NEXT: and z24.d, z24.d, #0x400 +; CHECK-SVE-NEXT: mul z30.d, p0/m, z30.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z5.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: mul z25.d, p0/m, z25.d, z0.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z0.d +; CHECK-SVE-NEXT: mul z24.d, p0/m, z24.d, z0.d +; CHECK-SVE-NEXT: eor z6.d, z6.d, z7.d +; CHECK-SVE-NEXT: and z5.d, z5.d, #0x40000 +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: and z4.d, z4.d, #0x4000 +; CHECK-SVE-NEXT: eor z6.d, z6.d, z25.d +; CHECK-SVE-NEXT: mul z5.d, p0/m, z5.d, z0.d +; CHECK-SVE-NEXT: eor z25.d, z26.d, z27.d +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: mul z4.d, p0/m, z4.d, z0.d +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x80000 +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: eor z3.d, z3.d, z24.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: and z27.d, z27.d, #0x1000000 +; CHECK-SVE-NEXT: eor z5.d, z25.d, z5.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x8000 +; CHECK-SVE-NEXT: eor z4.d, z6.d, z4.d +; CHECK-SVE-NEXT: and z24.d, z24.d, #0x2000000 +; CHECK-SVE-NEXT: mul z27.d, p0/m, z27.d, z0.d +; CHECK-SVE-NEXT: eor z6.d, z28.d, z29.d +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: and z25.d, z25.d, #0x100000 +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z0.d +; CHECK-SVE-NEXT: mul z24.d, p0/m, z24.d, z0.d +; CHECK-SVE-NEXT: eor z5.d, z5.d, z7.d +; CHECK-SVE-NEXT: and z28.d, z28.d, #0x4000000 +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mul z25.d, p0/m, z25.d, z0.d +; CHECK-SVE-NEXT: eor z6.d, z6.d, z27.d +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: and z29.d, z29.d, #0x40000000 +; CHECK-SVE-NEXT: mul z28.d, p0/m, z28.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z26.d +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x200000 +; CHECK-SVE-NEXT: and z27.d, z27.d, #0x20000000 +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z25.d +; CHECK-SVE-NEXT: eor z5.d, z6.d, z24.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mul z29.d, p0/m, z29.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z2.d, z3.d +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: mul z27.d, p0/m, z27.d, z0.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x4000000000 +; CHECK-SVE-NEXT: and z6.d, z6.d, #0x80000000 +; CHECK-SVE-NEXT: eor z2.d, z5.d, z28.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: eor z4.d, z4.d, z7.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: and z25.d, z25.d, #0x2000000000 +; CHECK-SVE-NEXT: mul z6.d, p0/m, z6.d, z0.d +; CHECK-SVE-NEXT: and z5.d, z5.d, #0x100000000 +; CHECK-SVE-NEXT: eor z24.d, z27.d, z29.d +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z0.d +; CHECK-SVE-NEXT: and z28.d, z28.d, #0x8000000000 +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x8000000 +; CHECK-SVE-NEXT: mul z25.d, p0/m, z25.d, z0.d +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: mul z5.d, p0/m, z5.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z3.d, z4.d +; CHECK-SVE-NEXT: eor z6.d, z24.d, z6.d +; CHECK-SVE-NEXT: and z27.d, z27.d, #0x200000000 +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: mul z28.d, p0/m, z28.d, z0.d +; CHECK-SVE-NEXT: and z29.d, z29.d, #0x10000000 +; CHECK-SVE-NEXT: eor z25.d, z25.d, z26.d +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: eor z5.d, z6.d, z5.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mul z27.d, p0/m, z27.d, z0.d +; CHECK-SVE-NEXT: and z24.d, z24.d, #0x400000000 +; CHECK-SVE-NEXT: mul z29.d, p0/m, z29.d, z0.d +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x20000000000 +; CHECK-SVE-NEXT: eor z2.d, z2.d, z7.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: and z6.d, z6.d, #0x10000000000 +; CHECK-SVE-NEXT: eor z4.d, z25.d, z28.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: mul z24.d, p0/m, z24.d, z0.d +; CHECK-SVE-NEXT: eor z5.d, z5.d, z27.d +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z0.d +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x40000000000 +; CHECK-SVE-NEXT: eor z2.d, z2.d, z29.d +; CHECK-SVE-NEXT: mul z6.d, p0/m, z6.d, z0.d +; CHECK-SVE-NEXT: and z25.d, z25.d, #0x400000000000 +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: and z27.d, z27.d, #0x800000000000 +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: eor z5.d, z5.d, z24.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: mul z25.d, p0/m, z25.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE-NEXT: and z28.d, z28.d, #0x400000000000000 +; CHECK-SVE-NEXT: eor z4.d, z4.d, z6.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mul z27.d, p0/m, z27.d, z0.d +; CHECK-SVE-NEXT: and z24.d, z24.d, #0x1000000000 +; CHECK-SVE-NEXT: eor z5.d, z5.d, z30.d +; CHECK-SVE-NEXT: mov z30.d, z1.d +; CHECK-SVE-NEXT: mul z28.d, p0/m, z28.d, z0.d +; CHECK-SVE-NEXT: and z29.d, z29.d, #0x200000000000 +; CHECK-SVE-NEXT: and z6.d, z6.d, #0x80000000000 +; CHECK-SVE-NEXT: eor z4.d, z4.d, z26.d +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: mul z24.d, p0/m, z24.d, z0.d +; CHECK-SVE-NEXT: and z30.d, z30.d, #0x800000000000000 +; CHECK-SVE-NEXT: mul z29.d, p0/m, z29.d, z0.d +; CHECK-SVE-NEXT: mul z6.d, p0/m, z6.d, z0.d +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x1000000000000 +; CHECK-SVE-NEXT: eor z4.d, z4.d, z7.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mul z30.d, p0/m, z30.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z5.d, z24.d +; CHECK-SVE-NEXT: eor z5.d, z25.d, z27.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z0.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x2000000000000 +; CHECK-SVE-NEXT: eor z4.d, z4.d, z6.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: and z24.d, z24.d, #0x100000000000000 +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: and z25.d, z25.d, #0x200000000000000 +; CHECK-SVE-NEXT: and z27.d, z27.d, #0x100000000000 +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: and z6.d, z6.d, #0x4000000000000 +; CHECK-SVE-NEXT: eor z5.d, z5.d, z26.d +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: mul z24.d, p0/m, z24.d, z0.d +; CHECK-SVE-NEXT: mul z25.d, p0/m, z25.d, z0.d +; CHECK-SVE-NEXT: mul z27.d, p0/m, z27.d, z0.d +; CHECK-SVE-NEXT: mul z6.d, p0/m, z6.d, z0.d +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x8000000000000 +; CHECK-SVE-NEXT: eor z5.d, z5.d, z7.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: eor z4.d, z4.d, z27.d +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x10000000000000 +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z0.d +; CHECK-SVE-NEXT: eor z5.d, z5.d, z6.d +; CHECK-SVE-NEXT: eor z6.d, z24.d, z25.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z29.d +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: and z24.d, z24.d, #0x20000000000000 +; CHECK-SVE-NEXT: and z25.d, z25.d, #0x1000000000000000 +; CHECK-SVE-NEXT: eor z5.d, z5.d, z26.d +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: eor z6.d, z6.d, z28.d +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: mul z24.d, p0/m, z24.d, z0.d +; CHECK-SVE-NEXT: mul z25.d, p0/m, z25.d, z0.d +; CHECK-SVE-NEXT: eor z5.d, z5.d, z7.d +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x40000000000000 +; CHECK-SVE-NEXT: and z28.d, z28.d, #0x2000000000000000 +; CHECK-SVE-NEXT: eor z6.d, z6.d, z30.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mov z30.d, z1.d +; CHECK-SVE-NEXT: and z1.d, z1.d, #0x8000000000000000 +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z0.d +; CHECK-SVE-NEXT: mul z28.d, p0/m, z28.d, z0.d +; CHECK-SVE-NEXT: eor z5.d, z5.d, z24.d +; CHECK-SVE-NEXT: and z7.d, z7.d, #0x80000000000000 +; CHECK-SVE-NEXT: and z30.d, z30.d, #0x4000000000000000 +; CHECK-SVE-NEXT: eor z6.d, z6.d, z25.d +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z0.d +; CHECK-SVE-NEXT: mul z30.d, p0/m, z30.d, z0.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z26.d +; CHECK-SVE-NEXT: eor z5.d, z6.d, z28.d +; CHECK-SVE-NEXT: mul z0.d, p0/m, z0.d, z1.d +; CHECK-SVE-NEXT: eor z1.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z2.d, z4.d, z7.d +; CHECK-SVE-NEXT: eor z3.d, z5.d, z30.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z2.d +; CHECK-SVE-NEXT: eor z0.d, z3.d, z0.d +; CHECK-SVE-NEXT: eor z0.d, z1.d, z0.d +; CHECK-SVE-NEXT: ret +; +; CHECK-SVE2-LABEL: clmul_nxv2i64: +; CHECK-SVE2: // %bb.0: +; CHECK-SVE2-NEXT: mov z2.d, z1.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z2.d, z2.d, #0x2 +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x1 +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x8 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x4 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x20 +; CHECK-SVE2-NEXT: mul z2.d, z0.d, z2.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x10 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x80 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x40 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x200 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x100 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x800 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x400 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x2000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x1000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x8000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x4000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x20000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x10000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x80000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x40000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x200000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x100000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x800000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x400000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x2000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x1000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x8000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x4000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x20000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x10000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x80000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x40000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x200000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x100000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x800000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x400000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x2000000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x1000000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x8000000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x4000000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x20000000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x10000000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x80000000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x40000000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x200000000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x100000000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x800000000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x400000000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x2000000000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x1000000000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x8000000000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x4000000000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x20000000000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x10000000000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x80000000000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x40000000000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x200000000000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x100000000000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x800000000000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x400000000000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x2000000000000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x1000000000000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: and z1.d, z1.d, #0x4000000000000000 +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x8000000000000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z5.d +; CHECK-SVE2-NEXT: mul z0.d, z0.d, z1.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mov z0.d, z2.d +; CHECK-SVE2-NEXT: ret +; +; CHECK-SVE2-AES-LABEL: clmul_nxv2i64: +; CHECK-SVE2-AES: // %bb.0: +; CHECK-SVE2-AES-NEXT: mov z2.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z2.d, z2.d, #0x2 +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x1 +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x8 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x4 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x20 +; CHECK-SVE2-AES-NEXT: mul z2.d, z0.d, z2.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x10 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x80 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x40 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x200 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x100 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x800 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x400 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x2000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x1000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x8000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x4000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x20000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x10000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x80000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x40000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x200000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x100000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x800000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x400000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x2000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x1000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x8000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x4000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x20000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x10000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x80000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x40000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x200000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x100000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x800000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x400000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x2000000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x1000000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x8000000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x4000000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x20000000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x10000000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x80000000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x40000000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x200000000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x100000000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x800000000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x400000000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x2000000000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x1000000000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x8000000000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x4000000000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x20000000000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x10000000000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x80000000000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x40000000000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x200000000000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x100000000000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x800000000000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x400000000000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x2000000000000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x1000000000000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: and z1.d, z1.d, #0x4000000000000000 +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x8000000000000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: mul z0.d, z0.d, z1.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z0.d, z2.d +; CHECK-SVE2-AES-NEXT: ret + %a = call @llvm.clmul.nxv2i64( %x, %y) + ret %a +} + +; TODO: fix +; define @clmul_nxv1i128( %x, %y) { +; %a = call @llvm.clmul.nxv1i128( %x, %y) +; ret %a +; } + +define @clmul_nxv16i8_zext( %x, %y) { +; CHECK-SVE-LABEL: clmul_nxv16i8_zext: +; CHECK-SVE: // %bb.0: +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: and z0.b, z0.b, #0xf +; CHECK-SVE-NEXT: and z1.b, z1.b, #0x8 +; CHECK-SVE-NEXT: ptrue p0.b +; CHECK-SVE-NEXT: and z2.b, z2.b, #0x2 +; CHECK-SVE-NEXT: and z3.b, z3.b, #0x1 +; CHECK-SVE-NEXT: and z4.b, z4.b, #0x4 +; CHECK-SVE-NEXT: mul z1.b, p0/m, z1.b, z0.b +; CHECK-SVE-NEXT: mul z2.b, p0/m, z2.b, z0.b +; CHECK-SVE-NEXT: mul z3.b, p0/m, z3.b, z0.b +; CHECK-SVE-NEXT: mul z4.b, p0/m, z4.b, z0.b +; CHECK-SVE-NEXT: mul z0.b, z0.b, #0 +; CHECK-SVE-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE-NEXT: eor z1.d, z4.d, z1.d +; CHECK-SVE-NEXT: eor z3.d, z0.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z2.d, z1.d +; CHECK-SVE-NEXT: eor z2.d, z3.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z2.d +; CHECK-SVE-NEXT: eor z0.d, z1.d, z0.d +; CHECK-SVE-NEXT: ret +; +; CHECK-SVE2-LABEL: clmul_nxv16i8_zext: +; CHECK-SVE2: // %bb.0: +; CHECK-SVE2-NEXT: and z0.b, z0.b, #0xf +; CHECK-SVE2-NEXT: and z1.b, z1.b, #0xf +; CHECK-SVE2-NEXT: pmul z0.b, z0.b, z1.b +; CHECK-SVE2-NEXT: ret +; +; CHECK-SVE2-AES-LABEL: clmul_nxv16i8_zext: +; CHECK-SVE2-AES: // %bb.0: +; CHECK-SVE2-AES-NEXT: and z0.b, z0.b, #0xf +; CHECK-SVE2-AES-NEXT: and z1.b, z1.b, #0xf +; CHECK-SVE2-AES-NEXT: pmul z0.b, z0.b, z1.b +; CHECK-SVE2-AES-NEXT: ret + %zextx = zext %x to + %zexty = zext %y to + %a = call @llvm.clmul.nxv16i8( %zextx, %zexty) + ret %a +} + +define @clmul_nxv8i16_zext( %x, %y) { +; CHECK-SVE-LABEL: clmul_nxv8i16_zext: +; CHECK-SVE: // %bb.0: +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: and z0.h, z0.h, #0xff +; CHECK-SVE-NEXT: and z1.h, z1.h, #0x80 +; CHECK-SVE-NEXT: and z2.h, z2.h, #0x2 +; CHECK-SVE-NEXT: and z3.h, z3.h, #0x1 +; CHECK-SVE-NEXT: and z4.h, z4.h, #0x4 +; CHECK-SVE-NEXT: and z5.h, z5.h, #0x8 +; CHECK-SVE-NEXT: and z6.h, z6.h, #0x10 +; CHECK-SVE-NEXT: and z7.h, z7.h, #0x20 +; CHECK-SVE-NEXT: and z24.h, z24.h, #0x40 +; CHECK-SVE-NEXT: ptrue p0.h +; CHECK-SVE-NEXT: mul z2.h, p0/m, z2.h, z0.h +; CHECK-SVE-NEXT: mul z3.h, p0/m, z3.h, z0.h +; CHECK-SVE-NEXT: mul z4.h, p0/m, z4.h, z0.h +; CHECK-SVE-NEXT: mul z5.h, p0/m, z5.h, z0.h +; CHECK-SVE-NEXT: mul z6.h, p0/m, z6.h, z0.h +; CHECK-SVE-NEXT: mul z7.h, p0/m, z7.h, z0.h +; CHECK-SVE-NEXT: mul z24.h, p0/m, z24.h, z0.h +; CHECK-SVE-NEXT: mul z1.h, p0/m, z1.h, z0.h +; CHECK-SVE-NEXT: mul z0.h, z0.h, #0 +; CHECK-SVE-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z5.d +; CHECK-SVE-NEXT: eor z4.d, z6.d, z7.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z5.d, z0.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z24.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z2.d, z1.d +; CHECK-SVE-NEXT: eor z0.d, z3.d, z0.d +; CHECK-SVE-NEXT: eor z0.d, z1.d, z0.d +; CHECK-SVE-NEXT: ret +; +; CHECK-SVE2-LABEL: clmul_nxv8i16_zext: +; CHECK-SVE2: // %bb.0: +; CHECK-SVE2-NEXT: mov z2.d, z1.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z0.h, z0.h, #0xff +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z2.h, z2.h, #0x2 +; CHECK-SVE2-NEXT: and z3.h, z3.h, #0x1 +; CHECK-SVE2-NEXT: and z4.h, z4.h, #0x8 +; CHECK-SVE2-NEXT: and z5.h, z5.h, #0x4 +; CHECK-SVE2-NEXT: and z6.h, z6.h, #0x20 +; CHECK-SVE2-NEXT: mul z2.h, z0.h, z2.h +; CHECK-SVE2-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-NEXT: mul z4.h, z0.h, z4.h +; CHECK-SVE2-NEXT: mul z5.h, z0.h, z5.h +; CHECK-SVE2-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z3.h, z3.h, #0x10 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z4.h, z0.h, z6.h +; CHECK-SVE2-NEXT: and z1.h, z1.h, #0x40 +; CHECK-SVE2-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-NEXT: and z5.h, z5.h, #0x80 +; CHECK-SVE2-NEXT: mul z1.h, z0.h, z1.h +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z3.d, z4.d +; CHECK-SVE2-NEXT: mul z3.h, z0.h, z5.h +; CHECK-SVE2-NEXT: mul z0.h, z0.h, #0 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z1.d, z3.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: mov z0.d, z2.d +; CHECK-SVE2-NEXT: ret +; +; CHECK-SVE2-AES-LABEL: clmul_nxv8i16_zext: +; CHECK-SVE2-AES: // %bb.0: +; CHECK-SVE2-AES-NEXT: mov z2.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z0.h, z0.h, #0xff +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z2.h, z2.h, #0x2 +; CHECK-SVE2-AES-NEXT: and z3.h, z3.h, #0x1 +; CHECK-SVE2-AES-NEXT: and z4.h, z4.h, #0x8 +; CHECK-SVE2-AES-NEXT: and z5.h, z5.h, #0x4 +; CHECK-SVE2-AES-NEXT: and z6.h, z6.h, #0x20 +; CHECK-SVE2-AES-NEXT: mul z2.h, z0.h, z2.h +; CHECK-SVE2-AES-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-AES-NEXT: mul z4.h, z0.h, z4.h +; CHECK-SVE2-AES-NEXT: mul z5.h, z0.h, z5.h +; CHECK-SVE2-AES-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.h, z3.h, #0x10 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z4.h, z0.h, z6.h +; CHECK-SVE2-AES-NEXT: and z1.h, z1.h, #0x40 +; CHECK-SVE2-AES-NEXT: mul z3.h, z0.h, z3.h +; CHECK-SVE2-AES-NEXT: and z5.h, z5.h, #0x80 +; CHECK-SVE2-AES-NEXT: mul z1.h, z0.h, z1.h +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z3.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z3.h, z0.h, z5.h +; CHECK-SVE2-AES-NEXT: mul z0.h, z0.h, #0 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z1.d, z3.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: mov z0.d, z2.d +; CHECK-SVE2-AES-NEXT: ret + %zextx = zext %x to + %zexty = zext %y to + %a = call @llvm.clmul.nxv8i16( %zextx, %zexty) + ret %a +} + +define @clmul_nxv4i32_zext( %x, %y) { +; CHECK-SVE-LABEL: clmul_nxv4i32_zext: +; CHECK-SVE: // %bb.0: +; CHECK-SVE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-SVE-NEXT: addvl sp, sp, #-1 +; CHECK-SVE-NEXT: str z8, [sp] // 16-byte Folded Spill +; CHECK-SVE-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG +; CHECK-SVE-NEXT: .cfi_offset w29, -16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16 +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mov z7.d, z1.d +; CHECK-SVE-NEXT: mov z24.d, z1.d +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: mov z30.d, z1.d +; CHECK-SVE-NEXT: mov z31.d, z1.d +; CHECK-SVE-NEXT: mov z8.d, z1.d +; CHECK-SVE-NEXT: and z0.s, z0.s, #0xffff +; CHECK-SVE-NEXT: and z2.s, z2.s, #0x2 +; CHECK-SVE-NEXT: and z3.s, z3.s, #0x1 +; CHECK-SVE-NEXT: and z4.s, z4.s, #0x4 +; CHECK-SVE-NEXT: and z5.s, z5.s, #0x8 +; CHECK-SVE-NEXT: and z6.s, z6.s, #0x10 +; CHECK-SVE-NEXT: and z7.s, z7.s, #0x20 +; CHECK-SVE-NEXT: and z24.s, z24.s, #0x40 +; CHECK-SVE-NEXT: and z25.s, z25.s, #0x80 +; CHECK-SVE-NEXT: and z26.s, z26.s, #0x100 +; CHECK-SVE-NEXT: and z27.s, z27.s, #0x200 +; CHECK-SVE-NEXT: and z28.s, z28.s, #0x400 +; CHECK-SVE-NEXT: and z29.s, z29.s, #0x800 +; CHECK-SVE-NEXT: and z30.s, z30.s, #0x1000 +; CHECK-SVE-NEXT: and z31.s, z31.s, #0x2000 +; CHECK-SVE-NEXT: and z8.s, z8.s, #0x4000 +; CHECK-SVE-NEXT: and z1.s, z1.s, #0x8000 +; CHECK-SVE-NEXT: ptrue p0.s +; CHECK-SVE-NEXT: mul z2.s, p0/m, z2.s, z0.s +; CHECK-SVE-NEXT: mul z3.s, p0/m, z3.s, z0.s +; CHECK-SVE-NEXT: mul z4.s, p0/m, z4.s, z0.s +; CHECK-SVE-NEXT: mul z5.s, p0/m, z5.s, z0.s +; CHECK-SVE-NEXT: mul z6.s, p0/m, z6.s, z0.s +; CHECK-SVE-NEXT: mul z7.s, p0/m, z7.s, z0.s +; CHECK-SVE-NEXT: mul z24.s, p0/m, z24.s, z0.s +; CHECK-SVE-NEXT: mul z25.s, p0/m, z25.s, z0.s +; CHECK-SVE-NEXT: mul z26.s, p0/m, z26.s, z0.s +; CHECK-SVE-NEXT: mul z27.s, p0/m, z27.s, z0.s +; CHECK-SVE-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE-NEXT: mul z28.s, p0/m, z28.s, z0.s +; CHECK-SVE-NEXT: mul z29.s, p0/m, z29.s, z0.s +; CHECK-SVE-NEXT: eor z3.d, z4.d, z5.d +; CHECK-SVE-NEXT: mul z30.s, p0/m, z30.s, z0.s +; CHECK-SVE-NEXT: mul z31.s, p0/m, z31.s, z0.s +; CHECK-SVE-NEXT: eor z4.d, z6.d, z7.d +; CHECK-SVE-NEXT: mul z8.s, p0/m, z8.s, z0.s +; CHECK-SVE-NEXT: mul z1.s, p0/m, z1.s, z0.s +; CHECK-SVE-NEXT: mul z0.s, z0.s, #0 +; CHECK-SVE-NEXT: eor z5.d, z25.d, z26.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z24.d +; CHECK-SVE-NEXT: eor z6.d, z29.d, z30.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z27.d +; CHECK-SVE-NEXT: eor z7.d, z0.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z5.d, z6.d, z31.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z28.d +; CHECK-SVE-NEXT: eor z6.d, z7.d, z0.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z8.d +; CHECK-SVE-NEXT: ldr z8, [sp] // 16-byte Folded Reload +; CHECK-SVE-NEXT: eor z2.d, z2.d, z3.d +; CHECK-SVE-NEXT: eor z5.d, z6.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z4.d, z1.d +; CHECK-SVE-NEXT: eor z3.d, z5.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z2.d, z1.d +; CHECK-SVE-NEXT: eor z2.d, z3.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z2.d +; CHECK-SVE-NEXT: eor z0.d, z2.d, z0.d +; CHECK-SVE-NEXT: eor z0.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z0.d, z0.d, z6.d +; CHECK-SVE-NEXT: addvl sp, sp, #1 +; CHECK-SVE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-SVE-NEXT: ret +; +; CHECK-SVE2-LABEL: clmul_nxv4i32_zext: +; CHECK-SVE2: // %bb.0: +; CHECK-SVE2-NEXT: mov z2.d, z1.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z0.s, z0.s, #0xffff +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z2.s, z2.s, #0x2 +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x1 +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x8 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x4 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x20 +; CHECK-SVE2-NEXT: mul z2.s, z0.s, z2.s +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x10 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x80 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x40 +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x200 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x100 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-NEXT: and z4.s, z4.s, #0x800 +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x400 +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.s, z3.s, #0x2000 +; CHECK-SVE2-NEXT: and z6.s, z6.s, #0x1000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: and z1.s, z1.s, #0x4000 +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-NEXT: mul z4.s, z0.s, z6.s +; CHECK-SVE2-NEXT: and z5.s, z5.s, #0x8000 +; CHECK-SVE2-NEXT: mul z1.s, z0.s, z1.s +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-NEXT: mul z3.s, z0.s, z5.s +; CHECK-SVE2-NEXT: mul z0.s, z0.s, #0 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z1.d, z3.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: mov z0.d, z2.d +; CHECK-SVE2-NEXT: ret +; +; CHECK-SVE2-AES-LABEL: clmul_nxv4i32_zext: +; CHECK-SVE2-AES: // %bb.0: +; CHECK-SVE2-AES-NEXT: mov z2.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z0.s, z0.s, #0xffff +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z2.s, z2.s, #0x2 +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x1 +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x8 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x4 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x20 +; CHECK-SVE2-AES-NEXT: mul z2.s, z0.s, z2.s +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x10 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x80 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x40 +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x200 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x100 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z6.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: and z4.s, z4.s, #0x800 +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x400 +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z4.s +; CHECK-SVE2-AES-NEXT: mul z5.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.s, z3.s, #0x2000 +; CHECK-SVE2-AES-NEXT: and z6.s, z6.s, #0x1000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: and z1.s, z1.s, #0x4000 +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z3.s +; CHECK-SVE2-AES-NEXT: mul z4.s, z0.s, z6.s +; CHECK-SVE2-AES-NEXT: and z5.s, z5.s, #0x8000 +; CHECK-SVE2-AES-NEXT: mul z1.s, z0.s, z1.s +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z3.s, z0.s, z5.s +; CHECK-SVE2-AES-NEXT: mul z0.s, z0.s, #0 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z1.d, z3.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: mov z0.d, z2.d +; CHECK-SVE2-AES-NEXT: ret + %zextx = zext %x to + %zexty = zext %y to + %a = call @llvm.clmul.nxv4i32( %zextx, %zexty) + ret %a +} + +define @clmul_nxv2i64_zext( %x, %y) { +; CHECK-SVE-LABEL: clmul_nxv2i64_zext: +; CHECK-SVE: // %bb.0: +; CHECK-SVE-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-SVE-NEXT: addvl sp, sp, #-16 +; CHECK-SVE-NEXT: str z23, [sp] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z22, [sp, #1, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z21, [sp, #2, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z20, [sp, #3, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z19, [sp, #4, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z18, [sp, #5, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z17, [sp, #6, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z16, [sp, #7, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z15, [sp, #8, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z14, [sp, #9, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z13, [sp, #10, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z12, [sp, #11, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z11, [sp, #12, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z10, [sp, #13, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z9, [sp, #14, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: str z8, [sp, #15, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: addvl sp, sp, #-3 +; CHECK-SVE-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0x98, 0x01, 0x1e, 0x22 // sp + 16 + 152 * VG +; CHECK-SVE-NEXT: .cfi_offset w29, -16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16 +; CHECK-SVE-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16 +; CHECK-SVE-NEXT: mov z6.d, z1.d +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: and z0.d, z0.d, #0xffffffff +; CHECK-SVE-NEXT: ptrue p0.d +; CHECK-SVE-NEXT: mov z30.d, z1.d +; CHECK-SVE-NEXT: mov z10.d, z1.d +; CHECK-SVE-NEXT: mov z11.d, z1.d +; CHECK-SVE-NEXT: mov z12.d, z1.d +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: and z6.d, z6.d, #0x10 +; CHECK-SVE-NEXT: and z29.d, z29.d, #0x200 +; CHECK-SVE-NEXT: mov z3.d, z1.d +; CHECK-SVE-NEXT: and z30.d, z30.d, #0x1000 +; CHECK-SVE-NEXT: and z10.d, z10.d, #0x4000 +; CHECK-SVE-NEXT: mov z4.d, z1.d +; CHECK-SVE-NEXT: and z11.d, z11.d, #0x8000 +; CHECK-SVE-NEXT: and z12.d, z12.d, #0x10000 +; CHECK-SVE-NEXT: and z2.d, z2.d, #0x2 +; CHECK-SVE-NEXT: movprfx z24, z0 +; CHECK-SVE-NEXT: mul z24.d, p0/m, z24.d, z6.d +; CHECK-SVE-NEXT: movprfx z6, z0 +; CHECK-SVE-NEXT: mul z6.d, p0/m, z6.d, z29.d +; CHECK-SVE-NEXT: mov z29.d, z1.d +; CHECK-SVE-NEXT: movprfx z9, z0 +; CHECK-SVE-NEXT: mul z9.d, p0/m, z9.d, z30.d +; CHECK-SVE-NEXT: movprfx z30, z0 +; CHECK-SVE-NEXT: mul z30.d, p0/m, z30.d, z10.d +; CHECK-SVE-NEXT: mov z5.d, z1.d +; CHECK-SVE-NEXT: movprfx z10, z0 +; CHECK-SVE-NEXT: mul z10.d, p0/m, z10.d, z12.d +; CHECK-SVE-NEXT: mul z2.d, p0/m, z2.d, z0.d +; CHECK-SVE-NEXT: mov z26.d, z1.d +; CHECK-SVE-NEXT: and z29.d, z29.d, #0x800 +; CHECK-SVE-NEXT: mov z27.d, z1.d +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: mov z12.d, z1.d +; CHECK-SVE-NEXT: mov z15.d, z1.d +; CHECK-SVE-NEXT: mov z16.d, z1.d +; CHECK-SVE-NEXT: and z3.d, z3.d, #0x1 +; CHECK-SVE-NEXT: and z4.d, z4.d, #0x4 +; CHECK-SVE-NEXT: and z5.d, z5.d, #0x8 +; CHECK-SVE-NEXT: movprfx z8, z0 +; CHECK-SVE-NEXT: mul z8.d, p0/m, z8.d, z29.d +; CHECK-SVE-NEXT: movprfx z29, z0 +; CHECK-SVE-NEXT: mul z29.d, p0/m, z29.d, z11.d +; CHECK-SVE-NEXT: str z2, [sp, #2, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: mov z11.d, z1.d +; CHECK-SVE-NEXT: and z26.d, z26.d, #0x40 +; CHECK-SVE-NEXT: and z27.d, z27.d, #0x80 +; CHECK-SVE-NEXT: mul z3.d, p0/m, z3.d, z0.d +; CHECK-SVE-NEXT: mul z4.d, p0/m, z4.d, z0.d +; CHECK-SVE-NEXT: movprfx z7, z0 +; CHECK-SVE-NEXT: mul z7.d, p0/m, z7.d, z5.d +; CHECK-SVE-NEXT: and z28.d, z28.d, #0x100 +; CHECK-SVE-NEXT: and z12.d, z12.d, #0x40000 +; CHECK-SVE-NEXT: and z15.d, z15.d, #0x100000 +; CHECK-SVE-NEXT: movprfx z5, z0 +; CHECK-SVE-NEXT: mul z5.d, p0/m, z5.d, z26.d +; CHECK-SVE-NEXT: movprfx z26, z0 +; CHECK-SVE-NEXT: mul z26.d, p0/m, z26.d, z27.d +; CHECK-SVE-NEXT: and z11.d, z11.d, #0x20000 +; CHECK-SVE-NEXT: and z16.d, z16.d, #0x200000 +; CHECK-SVE-NEXT: mov z25.d, z1.d +; CHECK-SVE-NEXT: mov z31.d, z1.d +; CHECK-SVE-NEXT: movprfx z27, z0 +; CHECK-SVE-NEXT: mul z27.d, p0/m, z27.d, z28.d +; CHECK-SVE-NEXT: movprfx z14, z0 +; CHECK-SVE-NEXT: mul z14.d, p0/m, z14.d, z12.d +; CHECK-SVE-NEXT: movprfx z12, z0 +; CHECK-SVE-NEXT: mul z12.d, p0/m, z12.d, z15.d +; CHECK-SVE-NEXT: movprfx z19, z0 +; CHECK-SVE-NEXT: mul z19.d, p0/m, z19.d, z11.d +; CHECK-SVE-NEXT: str z3, [sp, #1, mul vl] // 16-byte Folded Spill +; CHECK-SVE-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: mov z28.d, z1.d +; CHECK-SVE-NEXT: mov z13.d, z1.d +; CHECK-SVE-NEXT: movprfx z11, z0 +; CHECK-SVE-NEXT: mul z11.d, p0/m, z11.d, z16.d +; CHECK-SVE-NEXT: mov z17.d, z1.d +; CHECK-SVE-NEXT: mov z18.d, z1.d +; CHECK-SVE-NEXT: str z4, [sp] // 16-byte Folded Spill +; CHECK-SVE-NEXT: mov z15.d, z1.d +; CHECK-SVE-NEXT: mov z16.d, z1.d +; CHECK-SVE-NEXT: ldr z4, [sp, #1, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: mov z20.d, z1.d +; CHECK-SVE-NEXT: mov z21.d, z1.d +; CHECK-SVE-NEXT: mov z22.d, z1.d +; CHECK-SVE-NEXT: mov z23.d, z1.d +; CHECK-SVE-NEXT: mov z2.d, z1.d +; CHECK-SVE-NEXT: and z25.d, z25.d, #0x20 +; CHECK-SVE-NEXT: and z28.d, z28.d, #0x400 +; CHECK-SVE-NEXT: and z31.d, z31.d, #0x2000 +; CHECK-SVE-NEXT: and z13.d, z13.d, #0x80000 +; CHECK-SVE-NEXT: and z17.d, z17.d, #0x400000 +; CHECK-SVE-NEXT: and z18.d, z18.d, #0x800000 +; CHECK-SVE-NEXT: and z15.d, z15.d, #0x1000000 +; CHECK-SVE-NEXT: mul z25.d, p0/m, z25.d, z0.d +; CHECK-SVE-NEXT: and z16.d, z16.d, #0x2000000 +; CHECK-SVE-NEXT: and z20.d, z20.d, #0x4000000 +; CHECK-SVE-NEXT: mul z28.d, p0/m, z28.d, z0.d +; CHECK-SVE-NEXT: mul z31.d, p0/m, z31.d, z0.d +; CHECK-SVE-NEXT: and z21.d, z21.d, #0x8000000 +; CHECK-SVE-NEXT: mul z13.d, p0/m, z13.d, z0.d +; CHECK-SVE-NEXT: mul z17.d, p0/m, z17.d, z0.d +; CHECK-SVE-NEXT: and z22.d, z22.d, #0x10000000 +; CHECK-SVE-NEXT: mul z18.d, p0/m, z18.d, z0.d +; CHECK-SVE-NEXT: mul z15.d, p0/m, z15.d, z0.d +; CHECK-SVE-NEXT: and z23.d, z23.d, #0x20000000 +; CHECK-SVE-NEXT: and z2.d, z2.d, #0x40000000 +; CHECK-SVE-NEXT: mul z16.d, p0/m, z16.d, z0.d +; CHECK-SVE-NEXT: mul z20.d, p0/m, z20.d, z0.d +; CHECK-SVE-NEXT: and z1.d, z1.d, #0x80000000 +; CHECK-SVE-NEXT: mul z21.d, p0/m, z21.d, z0.d +; CHECK-SVE-NEXT: mul z22.d, p0/m, z22.d, z0.d +; CHECK-SVE-NEXT: mul z23.d, p0/m, z23.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z4.d, z3.d +; CHECK-SVE-NEXT: ldr z4, [sp] // 16-byte Folded Reload +; CHECK-SVE-NEXT: mul z2.d, p0/m, z2.d, z0.d +; CHECK-SVE-NEXT: mul z1.d, p0/m, z1.d, z0.d +; CHECK-SVE-NEXT: mul z0.d, z0.d, #0 +; CHECK-SVE-NEXT: eor z4.d, z4.d, z7.d +; CHECK-SVE-NEXT: eor z7.d, z24.d, z25.d +; CHECK-SVE-NEXT: eor z24.d, z26.d, z27.d +; CHECK-SVE-NEXT: eor z25.d, z8.d, z9.d +; CHECK-SVE-NEXT: eor z26.d, z10.d, z19.d +; CHECK-SVE-NEXT: eor z27.d, z17.d, z18.d +; CHECK-SVE-NEXT: eor z2.d, z23.d, z2.d +; CHECK-SVE-NEXT: eor z8.d, z0.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z3.d, z4.d +; CHECK-SVE-NEXT: eor z4.d, z7.d, z5.d +; CHECK-SVE-NEXT: eor z5.d, z24.d, z6.d +; CHECK-SVE-NEXT: eor z6.d, z25.d, z31.d +; CHECK-SVE-NEXT: eor z7.d, z26.d, z14.d +; CHECK-SVE-NEXT: eor z24.d, z27.d, z15.d +; CHECK-SVE-NEXT: eor z1.d, z2.d, z1.d +; CHECK-SVE-NEXT: eor z2.d, z8.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z3.d, z4.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z28.d +; CHECK-SVE-NEXT: eor z5.d, z6.d, z30.d +; CHECK-SVE-NEXT: eor z6.d, z7.d, z13.d +; CHECK-SVE-NEXT: eor z7.d, z24.d, z16.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z3.d, z4.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z29.d +; CHECK-SVE-NEXT: eor z5.d, z6.d, z12.d +; CHECK-SVE-NEXT: eor z6.d, z7.d, z20.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z3.d, z4.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z11.d +; CHECK-SVE-NEXT: eor z5.d, z6.d, z21.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z3.d, z4.d +; CHECK-SVE-NEXT: eor z4.d, z5.d, z22.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z0.d +; CHECK-SVE-NEXT: eor z3.d, z3.d, z4.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z2.d, z2.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z3.d, z1.d +; CHECK-SVE-NEXT: eor z3.d, z2.d, z0.d +; CHECK-SVE-NEXT: eor z1.d, z1.d, z3.d +; CHECK-SVE-NEXT: eor z0.d, z3.d, z0.d +; CHECK-SVE-NEXT: eor z0.d, z1.d, z0.d +; CHECK-SVE-NEXT: eor z0.d, z0.d, z2.d +; CHECK-SVE-NEXT: addvl sp, sp, #3 +; CHECK-SVE-NEXT: ldr z23, [sp] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z22, [sp, #1, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z21, [sp, #2, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z20, [sp, #3, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z19, [sp, #4, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z18, [sp, #5, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z17, [sp, #6, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z16, [sp, #7, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z15, [sp, #8, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z14, [sp, #9, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z13, [sp, #10, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z12, [sp, #11, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z11, [sp, #12, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z10, [sp, #13, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z9, [sp, #14, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: ldr z8, [sp, #15, mul vl] // 16-byte Folded Reload +; CHECK-SVE-NEXT: addvl sp, sp, #16 +; CHECK-SVE-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-SVE-NEXT: ret +; +; CHECK-SVE2-LABEL: clmul_nxv2i64_zext: +; CHECK-SVE2: // %bb.0: +; CHECK-SVE2-NEXT: mov z2.d, z1.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z0.d, z0.d, #0xffffffff +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z2.d, z2.d, #0x2 +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x1 +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x8 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x4 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x20 +; CHECK-SVE2-NEXT: mul z2.d, z0.d, z2.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x10 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x80 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x40 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x200 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x100 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x800 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x400 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x2000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x1000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x8000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x4000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x20000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x10000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x80000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x40000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x200000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x100000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x800000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x400000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x2000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x1000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z4.d, z1.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z4.d, z4.d, #0x8000000 +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x4000000 +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-NEXT: mov z3.d, z1.d +; CHECK-SVE2-NEXT: mov z6.d, z1.d +; CHECK-SVE2-NEXT: and z3.d, z3.d, #0x20000000 +; CHECK-SVE2-NEXT: and z6.d, z6.d, #0x10000000 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-NEXT: mov z5.d, z1.d +; CHECK-SVE2-NEXT: and z1.d, z1.d, #0x40000000 +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-NEXT: mul z4.d, z0.d, z6.d +; CHECK-SVE2-NEXT: and z5.d, z5.d, #0x80000000 +; CHECK-SVE2-NEXT: mul z1.d, z0.d, z1.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-NEXT: mul z3.d, z0.d, z5.d +; CHECK-SVE2-NEXT: mul z0.d, z0.d, #0 +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z1.d, z3.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-NEXT: mov z0.d, z2.d +; CHECK-SVE2-NEXT: ret +; +; CHECK-SVE2-AES-LABEL: clmul_nxv2i64_zext: +; CHECK-SVE2-AES: // %bb.0: +; CHECK-SVE2-AES-NEXT: mov z2.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z0.d, z0.d, #0xffffffff +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z2.d, z2.d, #0x2 +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x1 +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x8 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x4 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x20 +; CHECK-SVE2-AES-NEXT: mul z2.d, z0.d, z2.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: eor z2.d, z3.d, z2.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x10 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x80 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x40 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z3.d, z6.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x200 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x100 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x800 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x400 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x2000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x1000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x8000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x4000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x20000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x10000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x80000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x40000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x200000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x100000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x800000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x400000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x2000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x1000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z4.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z6.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z4.d, z4.d, #0x8000000 +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x4000000 +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z4.d +; CHECK-SVE2-AES-NEXT: mul z5.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z6.d, z3.d +; CHECK-SVE2-AES-NEXT: mov z3.d, z1.d +; CHECK-SVE2-AES-NEXT: mov z6.d, z1.d +; CHECK-SVE2-AES-NEXT: and z3.d, z3.d, #0x20000000 +; CHECK-SVE2-AES-NEXT: and z6.d, z6.d, #0x10000000 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z5.d, z4.d +; CHECK-SVE2-AES-NEXT: mov z5.d, z1.d +; CHECK-SVE2-AES-NEXT: and z1.d, z1.d, #0x40000000 +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z4.d, z0.d, z6.d +; CHECK-SVE2-AES-NEXT: and z5.d, z5.d, #0x80000000 +; CHECK-SVE2-AES-NEXT: mul z1.d, z0.d, z1.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z4.d, z3.d +; CHECK-SVE2-AES-NEXT: mul z3.d, z0.d, z5.d +; CHECK-SVE2-AES-NEXT: mul z0.d, z0.d, #0 +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z1.d, z3.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: eor3 z2.d, z2.d, z0.d, z0.d +; CHECK-SVE2-AES-NEXT: mov z0.d, z2.d +; CHECK-SVE2-AES-NEXT: ret + %zextx = zext %x to + %zexty = zext %y to + %a = call @llvm.clmul.nxv2i64( %zextx, %zexty) + ret %a +} + +; TODO: fix +; define @clmul_nxv1i128_zext( %x, %y) { +; %zextx = zext %x to +; %zexty = zext %y to +; %a = call @llvm.clmul.nxv1i128( %zextx, %zexty) +; ret %a +; } diff --git a/llvm/test/CodeGen/AArch64/clmul.ll b/llvm/test/CodeGen/AArch64/clmul.ll index e0fa67607d151..75f418f5bfb42 100644 --- a/llvm/test/CodeGen/AArch64/clmul.ll +++ b/llvm/test/CodeGen/AArch64/clmul.ll @@ -1,29 +1,1223 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=aarch64-linux-unknown-gnu %s -o - -mattr=+sve2 | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-unknown-gnu %s -o - | FileCheck %s -define @clmul_nxv16i8_sve( %x, %y) { -; CHECK-LABEL: clmul_nxv16i8_sve: +define i8 @clmul_i8(i8 %x, i8 %y) { +; CHECK-LABEL: clmul_i8: ; CHECK: // %bb.0: -; CHECK-NEXT: pmul z0.b, z0.b, z1.b +; CHECK-NEXT: and w8, w1, #0x2 +; CHECK-NEXT: and w9, w1, #0x1 +; CHECK-NEXT: and w10, w1, #0x4 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: and w11, w1, #0x8 +; CHECK-NEXT: and w12, w1, #0x10 +; CHECK-NEXT: mul w9, w0, w9 +; CHECK-NEXT: and w13, w1, #0x20 +; CHECK-NEXT: and w14, w1, #0x40 +; CHECK-NEXT: mul w10, w0, w10 +; CHECK-NEXT: mul w11, w0, w11 +; CHECK-NEXT: mul w12, w0, w12 +; CHECK-NEXT: eor w8, w9, w8 +; CHECK-NEXT: and w9, w1, #0xffffff80 +; CHECK-NEXT: mul w13, w0, w13 +; CHECK-NEXT: mul w14, w0, w14 +; CHECK-NEXT: eor w10, w10, w11 +; CHECK-NEXT: mul w9, w0, w9 +; CHECK-NEXT: eor w8, w8, w10 +; CHECK-NEXT: eor w11, w12, w13 +; CHECK-NEXT: eor w10, w11, w14 +; CHECK-NEXT: eor w8, w8, w10 +; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret - %a = call @llvm.clmul.nxv16i8( %x, %y) - ret %a + %a = call i8 @llvm.clmul.i8(i8 %x, i8 %y) + ret i8 %a } -define <16 x i8> @clmul_v16i8_neon(<16 x i8> %x, <16 x i8> %y) { -; CHECK-LABEL: clmul_v16i8_neon: +define i16 @clmul_i16(i16 %x, i16 %y) { +; CHECK-LABEL: clmul_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: pmul v0.16b, v0.16b, v1.16b +; CHECK-NEXT: and w8, w1, #0x2 +; CHECK-NEXT: and w9, w1, #0x1 +; CHECK-NEXT: and w10, w1, #0x4 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: and w11, w1, #0x8 +; CHECK-NEXT: and w12, w1, #0x10 +; CHECK-NEXT: mul w9, w0, w9 +; CHECK-NEXT: and w13, w1, #0x20 +; CHECK-NEXT: and w15, w1, #0x80 +; CHECK-NEXT: mul w10, w0, w10 +; CHECK-NEXT: and w16, w1, #0x100 +; CHECK-NEXT: and w2, w1, #0x800 +; CHECK-NEXT: mul w11, w0, w11 +; CHECK-NEXT: and w14, w1, #0x40 +; CHECK-NEXT: and w17, w1, #0x200 +; CHECK-NEXT: mul w12, w0, w12 +; CHECK-NEXT: eor w8, w9, w8 +; CHECK-NEXT: and w9, w1, #0x1000 +; CHECK-NEXT: mul w13, w0, w13 +; CHECK-NEXT: and w18, w1, #0x400 +; CHECK-NEXT: mul w15, w0, w15 +; CHECK-NEXT: eor w10, w10, w11 +; CHECK-NEXT: and w11, w1, #0x2000 +; CHECK-NEXT: mul w16, w0, w16 +; CHECK-NEXT: eor w8, w8, w10 +; CHECK-NEXT: and w10, w1, #0x4000 +; CHECK-NEXT: mul w2, w0, w2 +; CHECK-NEXT: eor w12, w12, w13 +; CHECK-NEXT: and w13, w1, #0xffff8000 +; CHECK-NEXT: mul w9, w0, w9 +; CHECK-NEXT: mul w14, w0, w14 +; CHECK-NEXT: eor w15, w15, w16 +; CHECK-NEXT: mul w17, w0, w17 +; CHECK-NEXT: mul w11, w0, w11 +; CHECK-NEXT: eor w9, w2, w9 +; CHECK-NEXT: mul w18, w0, w18 +; CHECK-NEXT: eor w12, w12, w14 +; CHECK-NEXT: mul w10, w0, w10 +; CHECK-NEXT: eor w14, w15, w17 +; CHECK-NEXT: eor w8, w8, w12 +; CHECK-NEXT: mul w13, w0, w13 +; CHECK-NEXT: eor w9, w9, w11 +; CHECK-NEXT: eor w11, w14, w18 +; CHECK-NEXT: eor w9, w9, w10 +; CHECK-NEXT: eor w8, w8, w11 +; CHECK-NEXT: eor w9, w9, w13 +; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret - %a = call <16 x i8> @llvm.clmul.v16i8(<16 x i8> %x, <16 x i8> %y) - ret <16 x i8> %a + %a = call i16 @llvm.clmul.i16(i16 %x, i16 %y) + ret i16 %a } -define <8 x i8> @clmul_v8i8_neon(<8 x i8> %x, <8 x i8> %y) { -; CHECK-LABEL: clmul_v8i8_neon: +define i32 @clmul_i32(i32 %x, i32 %y) { +; CHECK-LABEL: clmul_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: pmul v0.8b, v0.8b, v1.8b +; CHECK-NEXT: and w8, w1, #0x2 +; CHECK-NEXT: and w9, w1, #0x1 +; CHECK-NEXT: and w10, w1, #0x4 +; CHECK-NEXT: mul w8, w0, w8 +; CHECK-NEXT: and w11, w1, #0x8 +; CHECK-NEXT: and w12, w1, #0x10 +; CHECK-NEXT: mul w9, w0, w9 +; CHECK-NEXT: and w13, w1, #0x20 +; CHECK-NEXT: and w14, w1, #0x40 +; CHECK-NEXT: mul w10, w0, w10 +; CHECK-NEXT: and w2, w1, #0x800 +; CHECK-NEXT: and w15, w1, #0x80 +; CHECK-NEXT: mul w11, w0, w11 +; CHECK-NEXT: and w16, w1, #0x100 +; CHECK-NEXT: and w17, w1, #0x200 +; CHECK-NEXT: mul w12, w0, w12 +; CHECK-NEXT: eor w8, w9, w8 +; CHECK-NEXT: and w9, w1, #0x1000 +; CHECK-NEXT: mul w13, w0, w13 +; CHECK-NEXT: and w18, w1, #0x400 +; CHECK-NEXT: mul w14, w0, w14 +; CHECK-NEXT: eor w10, w10, w11 +; CHECK-NEXT: and w11, w1, #0x2000 +; CHECK-NEXT: mul w2, w0, w2 +; CHECK-NEXT: eor w8, w8, w10 +; CHECK-NEXT: and w10, w1, #0x4000 +; CHECK-NEXT: mul w9, w0, w9 +; CHECK-NEXT: eor w12, w12, w13 +; CHECK-NEXT: and w13, w1, #0x8000 +; CHECK-NEXT: mul w15, w0, w15 +; CHECK-NEXT: eor w12, w12, w14 +; CHECK-NEXT: and w14, w1, #0x10000 +; CHECK-NEXT: mul w16, w0, w16 +; CHECK-NEXT: eor w8, w8, w12 +; CHECK-NEXT: and w12, w1, #0x20000 +; CHECK-NEXT: mul w11, w0, w11 +; CHECK-NEXT: eor w9, w2, w9 +; CHECK-NEXT: and w2, w1, #0x400000 +; CHECK-NEXT: mul w17, w0, w17 +; CHECK-NEXT: mul w10, w0, w10 +; CHECK-NEXT: eor w15, w15, w16 +; CHECK-NEXT: and w16, w1, #0x40000 +; CHECK-NEXT: mul w13, w0, w13 +; CHECK-NEXT: eor w9, w9, w11 +; CHECK-NEXT: and w11, w1, #0x800000 +; CHECK-NEXT: mul w18, w0, w18 +; CHECK-NEXT: eor w15, w15, w17 +; CHECK-NEXT: and w17, w1, #0x80000 +; CHECK-NEXT: mul w14, w0, w14 +; CHECK-NEXT: eor w9, w9, w10 +; CHECK-NEXT: and w10, w1, #0x1000000 +; CHECK-NEXT: mul w12, w0, w12 +; CHECK-NEXT: eor w9, w9, w13 +; CHECK-NEXT: and w13, w1, #0x2000000 +; CHECK-NEXT: mul w16, w0, w16 +; CHECK-NEXT: eor w15, w15, w18 +; CHECK-NEXT: and w18, w1, #0x100000 +; CHECK-NEXT: mul w2, w0, w2 +; CHECK-NEXT: eor w8, w8, w15 +; CHECK-NEXT: and w15, w1, #0x200000 +; CHECK-NEXT: mul w11, w0, w11 +; CHECK-NEXT: eor w12, w14, w12 +; CHECK-NEXT: and w14, w1, #0x4000000 +; CHECK-NEXT: mul w17, w0, w17 +; CHECK-NEXT: eor w12, w12, w16 +; CHECK-NEXT: and w16, w1, #0x8000000 +; CHECK-NEXT: mul w10, w0, w10 +; CHECK-NEXT: eor w8, w8, w9 +; CHECK-NEXT: mul w13, w0, w13 +; CHECK-NEXT: eor w11, w2, w11 +; CHECK-NEXT: and w2, w1, #0x20000000 +; CHECK-NEXT: mul w18, w0, w18 +; CHECK-NEXT: eor w12, w12, w17 +; CHECK-NEXT: and w17, w1, #0x10000000 +; CHECK-NEXT: mul w14, w0, w14 +; CHECK-NEXT: eor w10, w11, w10 +; CHECK-NEXT: and w11, w1, #0x40000000 +; CHECK-NEXT: mul w15, w0, w15 +; CHECK-NEXT: eor w10, w10, w13 +; CHECK-NEXT: and w13, w1, #0x80000000 +; CHECK-NEXT: mul w16, w0, w16 +; CHECK-NEXT: eor w12, w12, w18 +; CHECK-NEXT: mul w17, w0, w17 +; CHECK-NEXT: eor w10, w10, w14 +; CHECK-NEXT: mul w2, w0, w2 +; CHECK-NEXT: eor w9, w12, w15 +; CHECK-NEXT: mul w11, w0, w11 +; CHECK-NEXT: eor w10, w10, w16 +; CHECK-NEXT: eor w8, w8, w9 +; CHECK-NEXT: mul w13, w0, w13 +; CHECK-NEXT: eor w9, w10, w17 +; CHECK-NEXT: eor w8, w8, w9 +; CHECK-NEXT: eor w10, w2, w11 +; CHECK-NEXT: eor w9, w10, w13 +; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret - %a = call <8 x i8> @llvm.clmul.v8i8(<8 x i8> %x, <8 x i8> %y) - ret <8 x i8> %a + %a = call i32 @llvm.clmul.i32(i32 %x, i32 %y) + ret i32 %a +} + +define i64 @clmul_i64(i64 %x, i64 %y) { +; CHECK-LABEL: clmul_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #304 +; CHECK-NEXT: stp x29, x30, [sp, #208] // 16-byte Folded Spill +; CHECK-NEXT: stp x28, x27, [sp, #224] // 16-byte Folded Spill +; CHECK-NEXT: stp x26, x25, [sp, #240] // 16-byte Folded Spill +; CHECK-NEXT: stp x24, x23, [sp, #256] // 16-byte Folded Spill +; CHECK-NEXT: stp x22, x21, [sp, #272] // 16-byte Folded Spill +; CHECK-NEXT: stp x20, x19, [sp, #288] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 304 +; CHECK-NEXT: .cfi_offset w19, -8 +; CHECK-NEXT: .cfi_offset w20, -16 +; CHECK-NEXT: .cfi_offset w21, -24 +; CHECK-NEXT: .cfi_offset w22, -32 +; CHECK-NEXT: .cfi_offset w23, -40 +; CHECK-NEXT: .cfi_offset w24, -48 +; CHECK-NEXT: .cfi_offset w25, -56 +; CHECK-NEXT: .cfi_offset w26, -64 +; CHECK-NEXT: .cfi_offset w27, -72 +; CHECK-NEXT: .cfi_offset w28, -80 +; CHECK-NEXT: .cfi_offset w30, -88 +; CHECK-NEXT: .cfi_offset w29, -96 +; CHECK-NEXT: and x8, x1, #0x2 +; CHECK-NEXT: mul x9, x0, x8 +; CHECK-NEXT: and x8, x1, #0x1 +; CHECK-NEXT: mul x10, x0, x8 +; CHECK-NEXT: and x8, x1, #0x4 +; CHECK-NEXT: mul x11, x0, x8 +; CHECK-NEXT: and x8, x1, #0x8 +; CHECK-NEXT: mul x13, x0, x8 +; CHECK-NEXT: and x8, x1, #0x10 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: mul x12, x0, x8 +; CHECK-NEXT: and x8, x1, #0x20 +; CHECK-NEXT: mul x14, x0, x8 +; CHECK-NEXT: and x8, x1, #0x40 +; CHECK-NEXT: eor x10, x11, x13 +; CHECK-NEXT: and x11, x1, #0x10000000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #200] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x80 +; CHECK-NEXT: mul x15, x0, x8 +; CHECK-NEXT: and x8, x1, #0x100 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #160] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x200 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #152] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x400 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #184] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x800 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #192] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x1000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #144] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x2000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #136] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x4000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #176] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x8000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #168] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x10000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #120] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x20000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #80] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x40000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #72] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x80000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #104] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x100000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #96] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x200000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #128] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x400000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #112] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x800000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #64] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x1000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #40] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x2000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: ldr x30, [sp, #40] // 8-byte Reload +; CHECK-NEXT: str x8, [sp, #32] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x4000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #56] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x8000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #48] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x10000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #88] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x20000000 +; CHECK-NEXT: mul x26, x0, x8 +; CHECK-NEXT: and x8, x1, #0x40000000 +; CHECK-NEXT: mul x22, x0, x8 +; CHECK-NEXT: and x8, x1, #0x80000000 +; CHECK-NEXT: mul x23, x0, x8 +; CHECK-NEXT: and x8, x1, #0x100000000 +; CHECK-NEXT: mul x24, x0, x8 +; CHECK-NEXT: and x8, x1, #0x200000000 +; CHECK-NEXT: eor x22, x26, x22 +; CHECK-NEXT: ldr x26, [sp, #32] // 8-byte Reload +; CHECK-NEXT: mul x25, x0, x8 +; CHECK-NEXT: and x8, x1, #0x400000000 +; CHECK-NEXT: eor x22, x22, x23 +; CHECK-NEXT: and x23, x1, #0x400000000000000 +; CHECK-NEXT: mul x27, x0, x8 +; CHECK-NEXT: and x8, x1, #0x800000000 +; CHECK-NEXT: eor x22, x22, x24 +; CHECK-NEXT: ldr x24, [sp, #48] // 8-byte Reload +; CHECK-NEXT: mul x28, x0, x8 +; CHECK-NEXT: and x8, x1, #0x1000000000 +; CHECK-NEXT: eor x22, x22, x25 +; CHECK-NEXT: ldr x25, [sp, #88] // 8-byte Reload +; CHECK-NEXT: mul x29, x0, x8 +; CHECK-NEXT: and x8, x1, #0x2000000000 +; CHECK-NEXT: eor x22, x22, x27 +; CHECK-NEXT: mul x21, x0, x8 +; CHECK-NEXT: and x8, x1, #0x4000000000 +; CHECK-NEXT: mul x7, x0, x8 +; CHECK-NEXT: and x8, x1, #0x8000000000 +; CHECK-NEXT: mul x19, x0, x8 +; CHECK-NEXT: and x8, x1, #0x10000000000 +; CHECK-NEXT: mul x5, x0, x8 +; CHECK-NEXT: and x8, x1, #0x20000000000 +; CHECK-NEXT: eor x7, x21, x7 +; CHECK-NEXT: mul x6, x0, x8 +; CHECK-NEXT: and x8, x1, #0x40000000000 +; CHECK-NEXT: mul x20, x0, x8 +; CHECK-NEXT: and x8, x1, #0x80000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: mul x23, x0, x23 +; CHECK-NEXT: str x8, [sp, #24] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x100000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #16] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x200000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #8] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x400000000000 +; CHECK-NEXT: mul x4, x0, x8 +; CHECK-NEXT: and x8, x1, #0x800000000000 +; CHECK-NEXT: mul x17, x0, x8 +; CHECK-NEXT: and x8, x1, #0x1000000000000 +; CHECK-NEXT: mul x18, x0, x8 +; CHECK-NEXT: and x8, x1, #0x2000000000000 +; CHECK-NEXT: mul x3, x0, x8 +; CHECK-NEXT: and x8, x1, #0x4000000000000 +; CHECK-NEXT: eor x17, x4, x17 +; CHECK-NEXT: mul x2, x0, x8 +; CHECK-NEXT: and x8, x1, #0x8000000000000 +; CHECK-NEXT: eor x17, x17, x18 +; CHECK-NEXT: and x18, x1, #0x4000000000000000 +; CHECK-NEXT: mul x16, x0, x8 +; CHECK-NEXT: eor x8, x9, x10 +; CHECK-NEXT: ldr x9, [sp, #160] // 8-byte Reload +; CHECK-NEXT: eor x10, x12, x14 +; CHECK-NEXT: ldr x12, [sp, #80] // 8-byte Reload +; CHECK-NEXT: eor x17, x17, x3 +; CHECK-NEXT: eor x9, x15, x9 +; CHECK-NEXT: mul x15, x0, x11 +; CHECK-NEXT: ldr x11, [sp, #200] // 8-byte Reload +; CHECK-NEXT: eor x17, x17, x2 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #152] // 8-byte Reload +; CHECK-NEXT: mul x18, x0, x18 +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: ldr x10, [sp, #184] // 8-byte Reload +; CHECK-NEXT: eor x16, x17, x16 +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: and x11, x1, #0x20000000000000 +; CHECK-NEXT: ldr x17, [sp, #24] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: mul x14, x0, x11 +; CHECK-NEXT: and x10, x1, #0x40000000000000 +; CHECK-NEXT: eor x11, x8, x9 +; CHECK-NEXT: ldr x8, [sp, #192] // 8-byte Reload +; CHECK-NEXT: ldr x9, [sp, #144] // 8-byte Reload +; CHECK-NEXT: mul x13, x0, x10 +; CHECK-NEXT: ldr x10, [sp, #136] // 8-byte Reload +; CHECK-NEXT: eor x15, x16, x15 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #120] // 8-byte Reload +; CHECK-NEXT: ldr x16, [sp, #16] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: ldr x10, [sp, #72] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: ldr x12, [sp, #176] // 8-byte Reload +; CHECK-NEXT: eor x14, x15, x14 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: and x10, x1, #0x80000000000000 +; CHECK-NEXT: ldr x15, [sp, #8] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x12 +; CHECK-NEXT: ldr x12, [sp, #104] // 8-byte Reload +; CHECK-NEXT: eor x13, x14, x13 +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: mul x12, x0, x10 +; CHECK-NEXT: ldr x10, [sp, #168] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: ldr x10, [sp, #96] // 8-byte Reload +; CHECK-NEXT: eor x8, x11, x8 +; CHECK-NEXT: ldr x11, [sp, #128] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: and x10, x1, #0x100000000000000 +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: ldr x11, [sp, #64] // 8-byte Reload +; CHECK-NEXT: mul x10, x0, x10 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldr x9, [sp, #112] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: and x11, x1, #0x200000000000000 +; CHECK-NEXT: eor x9, x9, x30 +; CHECK-NEXT: mul x11, x0, x11 +; CHECK-NEXT: eor x9, x9, x26 +; CHECK-NEXT: ldr x26, [sp, #56] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x26 +; CHECK-NEXT: eor x9, x9, x24 +; CHECK-NEXT: and x24, x1, #0x800000000000000 +; CHECK-NEXT: eor x9, x9, x25 +; CHECK-NEXT: mul x24, x0, x24 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x9, x22, x28 +; CHECK-NEXT: and x22, x1, #0x1000000000000000 +; CHECK-NEXT: eor x9, x9, x29 +; CHECK-NEXT: mul x21, x0, x22 +; CHECK-NEXT: and x11, x1, #0x8000000000000000 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x9, x7, x19 +; CHECK-NEXT: and x7, x1, #0x2000000000000000 +; CHECK-NEXT: eor x9, x9, x5 +; CHECK-NEXT: mul x4, x0, x7 +; CHECK-NEXT: eor x10, x10, x23 +; CHECK-NEXT: eor x9, x9, x6 +; CHECK-NEXT: eor x10, x10, x24 +; CHECK-NEXT: eor x9, x9, x20 +; CHECK-NEXT: mul x11, x0, x11 +; CHECK-NEXT: eor x9, x9, x17 +; CHECK-NEXT: eor x10, x10, x21 +; CHECK-NEXT: eor x9, x9, x16 +; CHECK-NEXT: ldp x20, x19, [sp, #288] // 16-byte Folded Reload +; CHECK-NEXT: eor x9, x9, x15 +; CHECK-NEXT: eor x10, x10, x4 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x9, x13, x12 +; CHECK-NEXT: eor x10, x10, x18 +; CHECK-NEXT: ldp x22, x21, [sp, #272] // 16-byte Folded Reload +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: ldp x24, x23, [sp, #256] // 16-byte Folded Reload +; CHECK-NEXT: eor x9, x10, x11 +; CHECK-NEXT: ldp x26, x25, [sp, #240] // 16-byte Folded Reload +; CHECK-NEXT: eor x0, x8, x9 +; CHECK-NEXT: ldp x28, x27, [sp, #224] // 16-byte Folded Reload +; CHECK-NEXT: ldp x29, x30, [sp, #208] // 16-byte Folded Reload +; CHECK-NEXT: add sp, sp, #304 +; CHECK-NEXT: ret + %a = call i64 @llvm.clmul.i64(i64 %x, i64 %y) + ret i64 %a +} + +define i16 @clmul_i16_zext(i8 %x, i8 %y) { +; CHECK-LABEL: clmul_i16_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: and w8, w0, #0xff +; CHECK-NEXT: and w9, w1, #0x2 +; CHECK-NEXT: and w10, w1, #0x1 +; CHECK-NEXT: mul w9, w8, w9 +; CHECK-NEXT: and w11, w1, #0x4 +; CHECK-NEXT: and w12, w1, #0x8 +; CHECK-NEXT: mul w10, w8, w10 +; CHECK-NEXT: and w13, w1, #0x10 +; CHECK-NEXT: and w14, w1, #0x20 +; CHECK-NEXT: mul w11, w8, w11 +; CHECK-NEXT: and w15, w1, #0x40 +; CHECK-NEXT: mul w12, w8, w12 +; CHECK-NEXT: mul w13, w8, w13 +; CHECK-NEXT: eor w9, w10, w9 +; CHECK-NEXT: and w10, w1, #0x80 +; CHECK-NEXT: mul w14, w8, w14 +; CHECK-NEXT: mul w15, w8, w15 +; CHECK-NEXT: eor w11, w11, w12 +; CHECK-NEXT: mul w8, w8, w10 +; CHECK-NEXT: eor w9, w9, w11 +; CHECK-NEXT: eor w12, w13, w14 +; CHECK-NEXT: eor w10, w12, w15 +; CHECK-NEXT: eor w9, w9, w10 +; CHECK-NEXT: eor w0, w9, w8 +; CHECK-NEXT: ret + %zextx = zext i8 %x to i16 + %zexty = zext i8 %y to i16 + %a = call i16 @llvm.clmul.i16(i16 %zextx, i16 %zexty) + ret i16 %a +} + +define i32 @clmul_i32_zext(i16 %x, i16 %y) { +; CHECK-LABEL: clmul_i32_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: and w8, w0, #0xffff +; CHECK-NEXT: and w9, w1, #0x2 +; CHECK-NEXT: and w10, w1, #0x1 +; CHECK-NEXT: mul w9, w8, w9 +; CHECK-NEXT: and w11, w1, #0x4 +; CHECK-NEXT: and w12, w1, #0x8 +; CHECK-NEXT: mul w10, w8, w10 +; CHECK-NEXT: and w13, w1, #0x10 +; CHECK-NEXT: and w14, w1, #0x20 +; CHECK-NEXT: mul w11, w8, w11 +; CHECK-NEXT: and w16, w1, #0x80 +; CHECK-NEXT: and w17, w1, #0x100 +; CHECK-NEXT: mul w12, w8, w12 +; CHECK-NEXT: and w2, w1, #0x800 +; CHECK-NEXT: and w15, w1, #0x40 +; CHECK-NEXT: mul w13, w8, w13 +; CHECK-NEXT: eor w9, w10, w9 +; CHECK-NEXT: and w10, w1, #0x1000 +; CHECK-NEXT: mul w14, w8, w14 +; CHECK-NEXT: and w18, w1, #0x200 +; CHECK-NEXT: and w0, w1, #0x400 +; CHECK-NEXT: mul w16, w8, w16 +; CHECK-NEXT: eor w11, w11, w12 +; CHECK-NEXT: and w12, w1, #0x2000 +; CHECK-NEXT: mul w17, w8, w17 +; CHECK-NEXT: eor w9, w9, w11 +; CHECK-NEXT: and w11, w1, #0x4000 +; CHECK-NEXT: mul w2, w8, w2 +; CHECK-NEXT: eor w13, w13, w14 +; CHECK-NEXT: and w14, w1, #0x8000 +; CHECK-NEXT: mul w10, w8, w10 +; CHECK-NEXT: mul w15, w8, w15 +; CHECK-NEXT: eor w16, w16, w17 +; CHECK-NEXT: mul w18, w8, w18 +; CHECK-NEXT: mul w12, w8, w12 +; CHECK-NEXT: eor w10, w2, w10 +; CHECK-NEXT: mul w0, w8, w0 +; CHECK-NEXT: eor w13, w13, w15 +; CHECK-NEXT: mul w11, w8, w11 +; CHECK-NEXT: eor w9, w9, w13 +; CHECK-NEXT: mul w8, w8, w14 +; CHECK-NEXT: eor w14, w16, w18 +; CHECK-NEXT: eor w10, w10, w12 +; CHECK-NEXT: eor w12, w14, w0 +; CHECK-NEXT: eor w10, w10, w11 +; CHECK-NEXT: eor w9, w9, w12 +; CHECK-NEXT: eor w8, w10, w8 +; CHECK-NEXT: eor w0, w9, w8 +; CHECK-NEXT: ret + %zextx = zext i16 %x to i32 + %zexty = zext i16 %y to i32 + %a = call i32 @llvm.clmul.i32(i32 %zextx, i32 %zexty) + ret i32 %a +} + +define i64 @clmul_i64_zext(i32 %x, i32 %y) { +; CHECK-LABEL: clmul_i64_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, w1 +; CHECK-NEXT: and x9, x8, #0x2 +; CHECK-NEXT: and x10, x8, #0x1 +; CHECK-NEXT: and x11, x8, #0x4 +; CHECK-NEXT: umull x9, w9, w0 +; CHECK-NEXT: and x12, x8, #0x8 +; CHECK-NEXT: and x13, x8, #0x10 +; CHECK-NEXT: umull x10, w10, w0 +; CHECK-NEXT: and x14, x8, #0x20 +; CHECK-NEXT: and x15, x8, #0x40 +; CHECK-NEXT: umull x11, w11, w0 +; CHECK-NEXT: and x2, x8, #0x800 +; CHECK-NEXT: and x16, x8, #0x80 +; CHECK-NEXT: umull x12, w12, w0 +; CHECK-NEXT: and x17, x8, #0x100 +; CHECK-NEXT: and x18, x8, #0x200 +; CHECK-NEXT: umull x13, w13, w0 +; CHECK-NEXT: eor x9, x10, x9 +; CHECK-NEXT: and x10, x8, #0x1000 +; CHECK-NEXT: umull x14, w14, w0 +; CHECK-NEXT: and x1, x8, #0x400 +; CHECK-NEXT: umull x15, w15, w0 +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: and x12, x8, #0x2000 +; CHECK-NEXT: umull x2, w2, w0 +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: and x11, x8, #0x4000 +; CHECK-NEXT: umull x10, w10, w0 +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: and x14, x8, #0x8000 +; CHECK-NEXT: umull x16, w16, w0 +; CHECK-NEXT: eor x13, x13, x15 +; CHECK-NEXT: and x15, x8, #0x10000 +; CHECK-NEXT: umull x17, w17, w0 +; CHECK-NEXT: eor x9, x9, x13 +; CHECK-NEXT: and x13, x8, #0x20000 +; CHECK-NEXT: umull x12, w12, w0 +; CHECK-NEXT: eor x10, x2, x10 +; CHECK-NEXT: and x2, x8, #0x400000 +; CHECK-NEXT: umull x18, w18, w0 +; CHECK-NEXT: umull x11, w11, w0 +; CHECK-NEXT: eor x16, x16, x17 +; CHECK-NEXT: and x17, x8, #0x40000 +; CHECK-NEXT: umull x14, w14, w0 +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: and x12, x8, #0x800000 +; CHECK-NEXT: umull x1, w1, w0 +; CHECK-NEXT: eor x16, x16, x18 +; CHECK-NEXT: and x18, x8, #0x80000 +; CHECK-NEXT: umull x15, w15, w0 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: and x11, x8, #0x1000000 +; CHECK-NEXT: umull x13, w13, w0 +; CHECK-NEXT: eor x10, x10, x14 +; CHECK-NEXT: and x14, x8, #0x2000000 +; CHECK-NEXT: umull x17, w17, w0 +; CHECK-NEXT: eor x16, x16, x1 +; CHECK-NEXT: and x1, x8, #0x100000 +; CHECK-NEXT: umull x2, w2, w0 +; CHECK-NEXT: eor x9, x9, x16 +; CHECK-NEXT: and x16, x8, #0x200000 +; CHECK-NEXT: umull x12, w12, w0 +; CHECK-NEXT: eor x13, x15, x13 +; CHECK-NEXT: and x15, x8, #0x4000000 +; CHECK-NEXT: umull x18, w18, w0 +; CHECK-NEXT: eor x13, x13, x17 +; CHECK-NEXT: and x17, x8, #0x8000000 +; CHECK-NEXT: umull x11, w11, w0 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: umull x14, w14, w0 +; CHECK-NEXT: eor x12, x2, x12 +; CHECK-NEXT: and x2, x8, #0x20000000 +; CHECK-NEXT: umull x1, w1, w0 +; CHECK-NEXT: eor x13, x13, x18 +; CHECK-NEXT: and x18, x8, #0x10000000 +; CHECK-NEXT: umull x15, w15, w0 +; CHECK-NEXT: eor x11, x12, x11 +; CHECK-NEXT: and x12, x8, #0x40000000 +; CHECK-NEXT: umull x16, w16, w0 +; CHECK-NEXT: eor x11, x11, x14 +; CHECK-NEXT: and x8, x8, #0x80000000 +; CHECK-NEXT: umull x17, w17, w0 +; CHECK-NEXT: eor x13, x13, x1 +; CHECK-NEXT: umull x18, w18, w0 +; CHECK-NEXT: eor x11, x11, x15 +; CHECK-NEXT: umull x2, w2, w0 +; CHECK-NEXT: eor x10, x13, x16 +; CHECK-NEXT: umull x12, w12, w0 +; CHECK-NEXT: eor x11, x11, x17 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: umull x8, w8, w0 +; CHECK-NEXT: eor x10, x11, x18 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: eor x11, x2, x12 +; CHECK-NEXT: eor x8, x11, x8 +; CHECK-NEXT: eor x0, x9, x8 +; CHECK-NEXT: ret + %zextx = zext i32 %x to i64 + %zexty = zext i32 %y to i64 + %a = call i64 @llvm.clmul.i64(i64 %zextx, i64 %zexty) + ret i64 %a +} + +define i128 @clmul_i128_zext(i64 %x, i64 %y) { +; CHECK-LABEL: clmul_i128_zext: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x29, x30, [sp, #-96]! // 16-byte Folded Spill +; CHECK-NEXT: stp x28, x27, [sp, #16] // 16-byte Folded Spill +; CHECK-NEXT: stp x26, x25, [sp, #32] // 16-byte Folded Spill +; CHECK-NEXT: stp x24, x23, [sp, #48] // 16-byte Folded Spill +; CHECK-NEXT: stp x22, x21, [sp, #64] // 16-byte Folded Spill +; CHECK-NEXT: stp x20, x19, [sp, #80] // 16-byte Folded Spill +; CHECK-NEXT: sub sp, sp, #624 +; CHECK-NEXT: .cfi_def_cfa_offset 720 +; CHECK-NEXT: .cfi_offset w19, -8 +; CHECK-NEXT: .cfi_offset w20, -16 +; CHECK-NEXT: .cfi_offset w21, -24 +; CHECK-NEXT: .cfi_offset w22, -32 +; CHECK-NEXT: .cfi_offset w23, -40 +; CHECK-NEXT: .cfi_offset w24, -48 +; CHECK-NEXT: .cfi_offset w25, -56 +; CHECK-NEXT: .cfi_offset w26, -64 +; CHECK-NEXT: .cfi_offset w27, -72 +; CHECK-NEXT: .cfi_offset w28, -80 +; CHECK-NEXT: .cfi_offset w30, -88 +; CHECK-NEXT: .cfi_offset w29, -96 +; CHECK-NEXT: and x8, x1, #0x2 +; CHECK-NEXT: mul x11, x0, x8 +; CHECK-NEXT: and x8, x1, #0x1 +; CHECK-NEXT: mul x12, x0, x8 +; CHECK-NEXT: and x8, x1, #0x4 +; CHECK-NEXT: mul x13, x0, x8 +; CHECK-NEXT: and x8, x1, #0x8 +; CHECK-NEXT: mul x14, x0, x8 +; CHECK-NEXT: and x8, x1, #0x10 +; CHECK-NEXT: mul x15, x0, x8 +; CHECK-NEXT: and x8, x1, #0x20 +; CHECK-NEXT: mul x16, x0, x8 +; CHECK-NEXT: and x8, x1, #0x40 +; CHECK-NEXT: mul x17, x0, x8 +; CHECK-NEXT: and x8, x1, #0x80 +; CHECK-NEXT: mul x18, x0, x8 +; CHECK-NEXT: and x8, x1, #0x100 +; CHECK-NEXT: mul x3, x0, x8 +; CHECK-NEXT: and x8, x1, #0x200 +; CHECK-NEXT: mul x2, x0, x8 +; CHECK-NEXT: and x8, x1, #0x400 +; CHECK-NEXT: mul x4, x0, x8 +; CHECK-NEXT: and x8, x1, #0x800 +; CHECK-NEXT: mul x5, x0, x8 +; CHECK-NEXT: and x8, x1, #0x1000 +; CHECK-NEXT: mul x20, x0, x8 +; CHECK-NEXT: and x8, x1, #0x2000 +; CHECK-NEXT: mul x6, x0, x8 +; CHECK-NEXT: and x8, x1, #0x4000 +; CHECK-NEXT: mul x7, x0, x8 +; CHECK-NEXT: and x8, x1, #0x8000 +; CHECK-NEXT: mul x19, x0, x8 +; CHECK-NEXT: and x8, x1, #0x10000 +; CHECK-NEXT: mul x21, x0, x8 +; CHECK-NEXT: and x8, x1, #0x20000 +; CHECK-NEXT: mul x22, x0, x8 +; CHECK-NEXT: and x8, x1, #0x40000 +; CHECK-NEXT: mul x23, x0, x8 +; CHECK-NEXT: and x8, x1, #0x80000 +; CHECK-NEXT: mul x24, x0, x8 +; CHECK-NEXT: and x8, x1, #0x100000 +; CHECK-NEXT: mul x25, x0, x8 +; CHECK-NEXT: and x8, x1, #0x200000 +; CHECK-NEXT: mul x26, x0, x8 +; CHECK-NEXT: and x8, x1, #0x400000 +; CHECK-NEXT: mul x27, x0, x8 +; CHECK-NEXT: and x8, x1, #0x800000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #592] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x1000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #584] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x2000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #616] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x4000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #576] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x8000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #608] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x10000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #600] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x20000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #568] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x40000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #512] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x80000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #536] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x100000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #528] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x200000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #560] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x400000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #520] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x800000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #552] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x1000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #544] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x2000000000 +; CHECK-NEXT: mul x9, x0, x8 +; CHECK-NEXT: and x8, x1, #0x4000000000 +; CHECK-NEXT: mul x10, x0, x8 +; CHECK-NEXT: and x8, x1, #0x8000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #464] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x10000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #456] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x20000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: stp x8, x9, [sp, #488] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x1, #0x40000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: stp x10, x8, [sp, #440] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x1, #0x80000000000 +; CHECK-NEXT: mul x9, x0, x8 +; CHECK-NEXT: and x8, x1, #0x100000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: stp x8, x9, [sp, #472] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x1, #0x200000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #504] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x400000000000 +; CHECK-NEXT: mul x9, x0, x8 +; CHECK-NEXT: and x8, x1, #0x800000000000 +; CHECK-NEXT: mul x10, x0, x8 +; CHECK-NEXT: and x8, x1, #0x1000000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #416] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x2000000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: str x8, [sp, #408] // 8-byte Spill +; CHECK-NEXT: and x8, x1, #0x4000000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: stp x8, x9, [sp, #424] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x1, #0x8000000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: stp x10, x8, [sp, #392] // 16-byte Folded Spill +; CHECK-NEXT: and x8, x1, #0x100000000000000 +; CHECK-NEXT: mul x9, x0, x8 +; CHECK-NEXT: and x8, x1, #0x200000000000000 +; CHECK-NEXT: mul x8, x0, x8 +; CHECK-NEXT: stp x8, x9, [sp, #376] // 16-byte Folded Spill +; CHECK-NEXT: and x9, x1, #0x400000000000000 +; CHECK-NEXT: rbit x8, x1 +; CHECK-NEXT: mul x9, x0, x9 +; CHECK-NEXT: and x10, x8, #0x2 +; CHECK-NEXT: str x9, [sp, #368] // 8-byte Spill +; CHECK-NEXT: rbit x9, x0 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #360] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #352] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #344] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #336] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #328] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #320] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #312] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #304] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x100 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #296] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x200 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #288] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x400 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #280] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x800 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #272] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #256] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x2000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #248] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #264] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #240] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #232] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #200] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #224] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #192] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x100000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #216] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x200000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #208] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x400000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #184] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x800000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #136] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #168] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x2000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #160] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #176] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #152] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #144] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #128] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #120] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #112] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x100000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #104] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x200000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #96] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x400000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #88] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x800000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #80] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x1000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #72] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x2000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #64] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x4000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #56] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x8000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #48] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x10000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #40] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x20000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #32] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x40000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #24] // 8-byte Spill +; CHECK-NEXT: and x10, x8, #0x80000000000 +; CHECK-NEXT: mul x10, x9, x10 +; CHECK-NEXT: str x10, [sp, #16] // 8-byte Spill +; CHECK-NEXT: eor x10, x12, x11 +; CHECK-NEXT: and x12, x8, #0x100000000000 +; CHECK-NEXT: mul x12, x9, x12 +; CHECK-NEXT: eor x11, x13, x14 +; CHECK-NEXT: and x13, x8, #0x200000000000 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: eor x11, x15, x16 +; CHECK-NEXT: ldr x14, [sp, #608] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x17 +; CHECK-NEXT: mul x30, x9, x13 +; CHECK-NEXT: and x13, x8, #0x400000000000 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: mul x29, x9, x13 +; CHECK-NEXT: and x13, x8, #0x800000000000 +; CHECK-NEXT: str x12, [sp, #8] // 8-byte Spill +; CHECK-NEXT: eor x12, x18, x3 +; CHECK-NEXT: eor x11, x12, x2 +; CHECK-NEXT: eor x12, x5, x20 +; CHECK-NEXT: mul x28, x9, x13 +; CHECK-NEXT: eor x11, x11, x4 +; CHECK-NEXT: ldr x13, [sp, #592] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: eor x11, x12, x6 +; CHECK-NEXT: eor x12, x21, x22 +; CHECK-NEXT: eor x11, x11, x7 +; CHECK-NEXT: eor x12, x12, x23 +; CHECK-NEXT: eor x13, x27, x13 +; CHECK-NEXT: eor x11, x11, x19 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: eor x11, x12, x24 +; CHECK-NEXT: and x12, x8, #0x1000000000000 +; CHECK-NEXT: eor x11, x11, x25 +; CHECK-NEXT: mul x27, x9, x12 +; CHECK-NEXT: ldr x12, [sp, #584] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x26 +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #616] // 8-byte Reload +; CHECK-NEXT: eor x12, x13, x12 +; CHECK-NEXT: and x13, x8, #0x2000000000000 +; CHECK-NEXT: eor x11, x12, x11 +; CHECK-NEXT: ldr x12, [sp, #576] // 8-byte Reload +; CHECK-NEXT: mul x25, x9, x13 +; CHECK-NEXT: ldr x13, [sp, #512] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #568] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x14 +; CHECK-NEXT: ldr x14, [sp, #536] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: and x13, x8, #0x4000000000000 +; CHECK-NEXT: mul x24, x9, x13 +; CHECK-NEXT: ldr x13, [sp, #600] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x14 +; CHECK-NEXT: ldr x14, [sp, #552] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x13 +; CHECK-NEXT: ldr x13, [sp, #528] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #560] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: and x13, x8, #0x8000000000000 +; CHECK-NEXT: eor x11, x12, x11 +; CHECK-NEXT: ldr x12, [sp, #520] // 8-byte Reload +; CHECK-NEXT: mul x23, x9, x13 +; CHECK-NEXT: ldr x13, [sp, #440] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #496] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x14 +; CHECK-NEXT: ldr x14, [sp, #464] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: and x13, x8, #0x10000000000000 +; CHECK-NEXT: mul x21, x9, x13 +; CHECK-NEXT: ldr x13, [sp, #544] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x14 +; CHECK-NEXT: ldr x14, [sp, #256] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x13 +; CHECK-NEXT: ldr x13, [sp, #456] // 8-byte Reload +; CHECK-NEXT: eor x26, x10, x11 +; CHECK-NEXT: ldr x10, [sp, #488] // 8-byte Reload +; CHECK-NEXT: ldr x11, [sp, #448] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: and x13, x8, #0x20000000000000 +; CHECK-NEXT: eor x10, x12, x10 +; CHECK-NEXT: mul x20, x9, x13 +; CHECK-NEXT: ldr x12, [sp, #392] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #432] // 8-byte Reload +; CHECK-NEXT: ldr x13, [sp, #480] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: and x12, x8, #0x40000000000000 +; CHECK-NEXT: eor x10, x10, x13 +; CHECK-NEXT: ldr x13, [sp, #416] // 8-byte Reload +; CHECK-NEXT: mul x7, x9, x12 +; CHECK-NEXT: ldr x12, [sp, #472] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x13 +; CHECK-NEXT: ldr x13, [sp, #504] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x12 +; CHECK-NEXT: ldr x12, [sp, #408] // 8-byte Reload +; CHECK-NEXT: eor x22, x10, x13 +; CHECK-NEXT: ldr x10, [sp, #424] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: and x12, x8, #0x80000000000000 +; CHECK-NEXT: eor x10, x11, x10 +; CHECK-NEXT: ldr x11, [sp, #400] // 8-byte Reload +; CHECK-NEXT: mul x5, x9, x12 +; CHECK-NEXT: ldr x12, [sp, #368] // 8-byte Reload +; CHECK-NEXT: eor x19, x10, x11 +; CHECK-NEXT: ldp x11, x10, [sp, #376] // 16-byte Folded Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: and x11, x8, #0x100000000000000 +; CHECK-NEXT: eor x6, x10, x12 +; CHECK-NEXT: ldp x12, x10, [sp, #352] // 16-byte Folded Reload +; CHECK-NEXT: mul x4, x9, x11 +; CHECK-NEXT: eor x10, x12, x10 +; CHECK-NEXT: ldp x12, x11, [sp, #336] // 16-byte Folded Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldp x13, x12, [sp, #320] // 16-byte Folded Reload +; CHECK-NEXT: eor x10, x10, x11 +; CHECK-NEXT: ldr x11, [sp, #312] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x13 +; CHECK-NEXT: and x13, x8, #0x200000000000000 +; CHECK-NEXT: eor x11, x12, x11 +; CHECK-NEXT: mul x3, x9, x13 +; CHECK-NEXT: and x13, x8, #0x400000000000000 +; CHECK-NEXT: eor x12, x10, x11 +; CHECK-NEXT: ldp x11, x10, [sp, #296] // 16-byte Folded Reload +; CHECK-NEXT: mul x2, x9, x13 +; CHECK-NEXT: ldr x13, [sp, #280] // 8-byte Reload +; CHECK-NEXT: eor x11, x10, x11 +; CHECK-NEXT: ldr x10, [sp, #288] // 8-byte Reload +; CHECK-NEXT: eor x3, x4, x3 +; CHECK-NEXT: and x4, x1, #0x2000000000000000 +; CHECK-NEXT: eor x11, x11, x10 +; CHECK-NEXT: ldr x10, [sp, #272] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x13 +; CHECK-NEXT: ldr x13, [sp, #248] // 8-byte Reload +; CHECK-NEXT: eor x2, x3, x2 +; CHECK-NEXT: eor x10, x10, x14 +; CHECK-NEXT: eor x11, x12, x11 +; CHECK-NEXT: ldr x12, [sp, #264] // 8-byte Reload +; CHECK-NEXT: eor x10, x10, x13 +; CHECK-NEXT: and x13, x8, #0x800000000000000 +; CHECK-NEXT: mul x3, x0, x4 +; CHECK-NEXT: eor x12, x10, x12 +; CHECK-NEXT: ldr x10, [sp, #240] // 8-byte Reload +; CHECK-NEXT: mul x18, x9, x13 +; CHECK-NEXT: ldr x13, [sp, #200] // 8-byte Reload +; CHECK-NEXT: eor x12, x12, x10 +; CHECK-NEXT: ldr x10, [sp, #232] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldp x14, x12, [sp, #216] // 16-byte Folded Reload +; CHECK-NEXT: eor x13, x10, x13 +; CHECK-NEXT: and x10, x8, #0x1000000000000000 +; CHECK-NEXT: mul x17, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #192] // 8-byte Reload +; CHECK-NEXT: eor x12, x13, x12 +; CHECK-NEXT: ldr x13, [sp, #136] // 8-byte Reload +; CHECK-NEXT: eor x18, x2, x18 +; CHECK-NEXT: eor x12, x12, x10 +; CHECK-NEXT: ldr x10, [sp, #184] // 8-byte Reload +; CHECK-NEXT: and x2, x1, #0x4000000000000000 +; CHECK-NEXT: eor x12, x12, x14 +; CHECK-NEXT: ldr x14, [sp, #168] // 8-byte Reload +; CHECK-NEXT: eor x13, x10, x13 +; CHECK-NEXT: and x10, x8, #0x2000000000000000 +; CHECK-NEXT: and x8, x8, #0x4000000000000000 +; CHECK-NEXT: mul x16, x9, x10 +; CHECK-NEXT: ldr x10, [sp, #208] // 8-byte Reload +; CHECK-NEXT: eor x13, x13, x14 +; CHECK-NEXT: eor x17, x18, x17 +; CHECK-NEXT: eor x12, x12, x10 +; CHECK-NEXT: ldr x10, [sp, #160] // 8-byte Reload +; CHECK-NEXT: mul x15, x9, x8 +; CHECK-NEXT: ldr x8, [sp, #152] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: eor x13, x13, x10 +; CHECK-NEXT: ldr x10, [sp, #176] // 8-byte Reload +; CHECK-NEXT: mul x18, x0, x2 +; CHECK-NEXT: eor x16, x17, x16 +; CHECK-NEXT: and x17, x1, #0x8000000000000000 +; CHECK-NEXT: eor x12, x13, x10 +; CHECK-NEXT: and x13, x1, #0x10000000000000 +; CHECK-NEXT: eor x9, x12, x8 +; CHECK-NEXT: ldp x10, x8, [sp, #120] // 16-byte Folded Reload +; CHECK-NEXT: mul x14, x0, x13 +; CHECK-NEXT: eor x12, x8, x10 +; CHECK-NEXT: ldr x8, [sp, #144] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x8 +; CHECK-NEXT: ldp x8, x10, [sp, #104] // 16-byte Folded Reload +; CHECK-NEXT: eor x9, x11, x9 +; CHECK-NEXT: eor x14, x19, x14 +; CHECK-NEXT: eor x12, x12, x10 +; CHECK-NEXT: eor x11, x12, x8 +; CHECK-NEXT: ldr x8, [sp, #96] // 8-byte Reload +; CHECK-NEXT: and x12, x1, #0x20000000000000 +; CHECK-NEXT: mul x13, x0, x12 +; CHECK-NEXT: eor x11, x11, x8 +; CHECK-NEXT: ldp x10, x8, [sp, #56] // 16-byte Folded Reload +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: ldp x12, x10, [sp, #80] // 16-byte Folded Reload +; CHECK-NEXT: eor x11, x11, x10 +; CHECK-NEXT: ldr x10, [sp, #48] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x12 +; CHECK-NEXT: ldr x12, [sp, #40] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: and x10, x1, #0x40000000000000 +; CHECK-NEXT: eor x8, x8, x12 +; CHECK-NEXT: mul x12, x0, x10 +; CHECK-NEXT: ldr x10, [sp, #72] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x10 +; CHECK-NEXT: ldr x10, [sp, #32] // 8-byte Reload +; CHECK-NEXT: eor x9, x9, x11 +; CHECK-NEXT: ldr x11, [sp, #24] // 8-byte Reload +; CHECK-NEXT: eor x8, x8, x10 +; CHECK-NEXT: and x10, x1, #0x80000000000000 +; CHECK-NEXT: eor x8, x8, x11 +; CHECK-NEXT: ldr x11, [sp, #16] // 8-byte Reload +; CHECK-NEXT: mul x10, x0, x10 +; CHECK-NEXT: eor x8, x8, x11 +; CHECK-NEXT: eor x11, x29, x28 +; CHECK-NEXT: ldr x29, [sp, #8] // 8-byte Reload +; CHECK-NEXT: eor x11, x11, x27 +; CHECK-NEXT: and x28, x1, #0x800000000000000 +; CHECK-NEXT: eor x8, x8, x29 +; CHECK-NEXT: eor x11, x11, x25 +; CHECK-NEXT: mul x27, x0, x28 +; CHECK-NEXT: eor x8, x8, x30 +; CHECK-NEXT: and x25, x1, #0x1000000000000000 +; CHECK-NEXT: eor x8, x9, x8 +; CHECK-NEXT: eor x9, x11, x24 +; CHECK-NEXT: mul x11, x0, x25 +; CHECK-NEXT: eor x9, x9, x23 +; CHECK-NEXT: eor x9, x9, x21 +; CHECK-NEXT: eor x9, x9, x20 +; CHECK-NEXT: eor x9, x9, x7 +; CHECK-NEXT: eor x9, x9, x5 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x9, x16, x15 +; CHECK-NEXT: mul x15, x0, x17 +; CHECK-NEXT: eor x16, x6, x27 +; CHECK-NEXT: eor x8, x8, x9 +; CHECK-NEXT: eor x9, x14, x13 +; CHECK-NEXT: eor x11, x16, x11 +; CHECK-NEXT: rbit x8, x8 +; CHECK-NEXT: eor x9, x9, x12 +; CHECK-NEXT: eor x11, x11, x3 +; CHECK-NEXT: eor x13, x26, x22 +; CHECK-NEXT: eor x9, x9, x10 +; CHECK-NEXT: eor x10, x11, x18 +; CHECK-NEXT: lsr x1, x8, #1 +; CHECK-NEXT: eor x8, x13, x9 +; CHECK-NEXT: eor x9, x10, x15 +; CHECK-NEXT: eor x0, x8, x9 +; CHECK-NEXT: add sp, sp, #624 +; CHECK-NEXT: ldp x20, x19, [sp, #80] // 16-byte Folded Reload +; CHECK-NEXT: ldp x22, x21, [sp, #64] // 16-byte Folded Reload +; CHECK-NEXT: ldp x24, x23, [sp, #48] // 16-byte Folded Reload +; CHECK-NEXT: ldp x26, x25, [sp, #32] // 16-byte Folded Reload +; CHECK-NEXT: ldp x28, x27, [sp, #16] // 16-byte Folded Reload +; CHECK-NEXT: ldp x29, x30, [sp], #96 // 16-byte Folded Reload +; CHECK-NEXT: ret + %zextx = zext i64 %x to i128 + %zexty = zext i64 %y to i128 + %a = call i128 @llvm.clmul.i128(i128 %zextx, i128 %zexty) + ret i128 %a } diff --git a/llvm/test/CodeGen/AArch64/cls.ll b/llvm/test/CodeGen/AArch64/cls.ll index 61eb6894f0442..0af9adcb3695a 100644 --- a/llvm/test/CodeGen/AArch64/cls.ll +++ b/llvm/test/CodeGen/AArch64/cls.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s +; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD +; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=CHECK,CHECK-GI ; @llvm.aarch64.cls must be directly translated into the 'cls' instruction @@ -72,12 +73,22 @@ define i32 @cls_i32_knownbits_2(i16 signext %x) { ; Check that the range max in ctls cls knownbits ; is not set to 32 define i64 @cls_i64_not_32(i64 %x) { -; CHECK-LABEL: cls_i64_not_32: -; CHECK: // %bb.0: -; CHECK-NEXT: asr x8, x0, #16 -; CHECK-NEXT: cls x8, x8 -; CHECK-NEXT: orr x0, x8, #0x10 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: cls_i64_not_32: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: asr x8, x0, #16 +; CHECK-SD-NEXT: cls x8, x8 +; CHECK-SD-NEXT: orr x0, x8, #0x10 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: cls_i64_not_32: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: asr x8, x0, #63 +; CHECK-GI-NEXT: eor x8, x8, x0, asr #16 +; CHECK-GI-NEXT: lsl x8, x8, #1 +; CHECK-GI-NEXT: orr x8, x8, #0x1 +; CHECK-GI-NEXT: clz x8, x8 +; CHECK-GI-NEXT: orr x0, x8, #0x10 +; CHECK-GI-NEXT: ret %val = ashr i64 %x, 16 %a = ashr i64 %val, 63 %b = xor i64 %val, %a @@ -125,12 +136,21 @@ define i32 @cls_i32_knownbits_4(i32 signext %x) { ; Negative test. Check that the number of sign bits is not ; overestimated. If it is, the orr disappears. define i32 @cls_i32_knownbits_no_overestimate(i32 signext %x) { -; CHECK-LABEL: cls_i32_knownbits_no_overestimate: -; CHECK: // %bb.0: -; CHECK-NEXT: asr w8, w0, #15 -; CHECK-NEXT: cls w8, w8 -; CHECK-NEXT: orr w0, w8, #0x10 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: cls_i32_knownbits_no_overestimate: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: asr w8, w0, #15 +; CHECK-SD-NEXT: cls w8, w8 +; CHECK-SD-NEXT: orr w0, w8, #0x10 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: cls_i32_knownbits_no_overestimate: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: asr w8, w0, #31 +; CHECK-GI-NEXT: eor w8, w8, w0, asr #15 +; CHECK-GI-NEXT: clz w8, w8 +; CHECK-GI-NEXT: sub w8, w8, #1 +; CHECK-GI-NEXT: orr w0, w8, #0x10 +; CHECK-GI-NEXT: ret %ashr = ashr i32 %x, 15 %a = ashr i32 %ashr, 31 %b = xor i32 %ashr, %a diff --git a/llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir b/llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir index b60f4ffdd880b..1a27c6216af6b 100644 --- a/llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir +++ b/llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir @@ -86,7 +86,7 @@ body: | %8:gpr64 = COPY killed $x0 %9:gpr64 = IMPLICIT_DEF %10:gpr64 = IMPLICIT_DEF - %11:gpr64 = SUBREG_TO_REG 0, killed undef %1, %subreg.sub_32 + %11:gpr64 = SUBREG_TO_REG killed undef %1, %subreg.sub_32 ADJCALLSTACKDOWN 16, 0, implicit-def dead $sp, implicit $sp BL @_ZL9testScanfPKcjz, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp ADJCALLSTACKUP 16, 0, implicit-def dead $sp, implicit $sp diff --git a/llvm/test/CodeGen/AArch64/fcvt_combine.ll b/llvm/test/CodeGen/AArch64/fcvt_combine.ll index 06343ae5baba9..38defb602d4f4 100644 --- a/llvm/test/CodeGen/AArch64/fcvt_combine.ll +++ b/llvm/test/CodeGen/AArch64/fcvt_combine.ll @@ -5,89 +5,30 @@ ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+fullfp16 -verify-machineinstrs -global-isel -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI define <2 x i32> @test1(<2 x float> %f) { -; CHECK-NO16-SD-LABEL: test1: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.2s, v0.2s, #4 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test1: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.2s, v0.2s, #4 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test1: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test1: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test1: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.2s, v0.2s, #4 +; CHECK-NEXT: ret %mul.i = fmul <2 x float> %f, %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> ret <2 x i32> %vcvt.i } define <4 x i32> @test2(<4 x float> %f) { -; CHECK-NO16-SD-LABEL: test2: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.4s, v0.4s, #3 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test2: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s, #3 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test2: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #8.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.4s, v0.4s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test2: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #8.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.4s, v0.4s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test2: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.4s, v0.4s, #3 +; CHECK-NEXT: ret %mul.i = fmul <4 x float> %f, %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32> ret <4 x i32> %vcvt.i } define <2 x i64> @test3(<2 x double> %d) { -; CHECK-NO16-SD-LABEL: test3: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.2d, v0.2d, #5 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test3: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d, #5 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test3: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: mov x8, #4629700416936869888 // =0x4040000000000000 -; CHECK-NO16-GI-NEXT: fmov d1, x8 -; CHECK-NO16-GI-NEXT: fmul v0.2d, v0.2d, v1.d[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.2d, v0.2d -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test3: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: mov x8, #4629700416936869888 // =0x4040000000000000 -; CHECK-FP16-GI-NEXT: fmov d1, x8 -; CHECK-FP16-GI-NEXT: fmul v0.2d, v0.2d, v1.d[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test3: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.2d, v0.2d, #5 +; CHECK-NEXT: ret %mul.i = fmul <2 x double> %d, %vcvt.i = fptosi <2 x double> %mul.i to <2 x i64> ret <2 x i64> %vcvt.i @@ -95,33 +36,11 @@ define <2 x i64> @test3(<2 x double> %d) { ; Truncate double to i32 define <2 x i32> @test4(<2 x double> %d) { -; CHECK-NO16-SD-LABEL: test4: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.2d, v0.2d, #4 -; CHECK-NO16-SD-NEXT: xtn v0.2s, v0.2d -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test4: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d, #4 -; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test4: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov d1, #16.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.2d, v0.2d, v1.d[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.2d, v0.2d -; CHECK-NO16-GI-NEXT: xtn v0.2s, v0.2d -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test4: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov d1, #16.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.2d, v0.2d, v1.d[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d -; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test4: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.2d, v0.2d, #4 +; CHECK-NEXT: xtn v0.2s, v0.2d +; CHECK-NEXT: ret %mul.i = fmul <2 x double> %d, %vcvt.i = fptosi <2 x double> %mul.i to <2 x i32> ret <2 x i32> %vcvt.i @@ -129,29 +48,10 @@ define <2 x i32> @test4(<2 x double> %d) { ; Truncate float to i16 define <2 x i16> @test5(<2 x float> %f) { -; CHECK-NO16-SD-LABEL: test5: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.2s, v0.2s, #4 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test5: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.2s, v0.2s, #4 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test5: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test5: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test5: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.2s, v0.2s, #4 +; CHECK-NEXT: ret %mul.i = fmul <2 x float> %f, %vcvt.i = fptosi <2 x float> %mul.i to <2 x i16> ret <2 x i16> %vcvt.i @@ -196,29 +96,10 @@ define <2 x i64> @test6(<2 x float> %f) { } define <2 x i32> @test7(<2 x float> %f) { -; CHECK-NO16-SD-LABEL: test7: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzu v0.2s, v0.2s, #4 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test7: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzu v0.2s, v0.2s, #4 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test7: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzu v0.2s, v0.2s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test7: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzu v0.2s, v0.2s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test7: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzu v0.2s, v0.2s, #4 +; CHECK-NEXT: ret %mul.i = fmul <2 x float> %f, %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32> ret <2 x i32> %vcvt.i @@ -406,31 +287,10 @@ define <2 x i32> @test13(<2 x float> %f) { ; Test case where const is max power of 2 (i.e., 2^32). define <2 x i32> @test14(<2 x float> %f) { -; CHECK-NO16-SD-LABEL: test14: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.2s, v0.2s, #32 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test14: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.2s, v0.2s, #32 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test14: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: mov w8, #1333788672 // =0x4f800000 -; CHECK-NO16-GI-NEXT: fmov s1, w8 -; CHECK-NO16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test14: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: mov w8, #1333788672 // =0x4f800000 -; CHECK-FP16-GI-NEXT: fmov s1, w8 -; CHECK-FP16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test14: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.2s, v0.2s, #32 +; CHECK-NEXT: ret %mul.i = fmul <2 x float> %f, %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> ret <2 x i32> %vcvt.i @@ -490,10 +350,10 @@ define <8 x i16> @test_v8f16(<8 x half> %in) { ; CHECK-NO16-SD-NEXT: uzp1 v0.8h, v1.8h, v0.8h ; CHECK-NO16-SD-NEXT: ret ; -; CHECK-FP16-SD-LABEL: test_v8f16: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h, #2 -; CHECK-FP16-SD-NEXT: ret +; CHECK-FP16-LABEL: test_v8f16: +; CHECK-FP16: // %bb.0: +; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h, #2 +; CHECK-FP16-NEXT: ret ; ; CHECK-NO16-GI-LABEL: test_v8f16: ; CHECK-NO16-GI: // %bb.0: @@ -511,13 +371,6 @@ define <8 x i16> @test_v8f16(<8 x half> %in) { ; CHECK-NO16-GI-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NO16-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h ; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test_v8f16: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: movi v1.8h, #68, lsl #8 -; CHECK-FP16-GI-NEXT: fmul v0.8h, v0.8h, v1.8h -; CHECK-FP16-GI-NEXT: fcvtzs v0.8h, v0.8h -; CHECK-FP16-GI-NEXT: ret %scale = fmul <8 x half> %in, %val = fptosi <8 x half> %scale to <8 x i16> ret <8 x i16> %val @@ -535,10 +388,10 @@ define <4 x i16> @test_v4f16(<4 x half> %in) { ; CHECK-NO16-SD-NEXT: xtn v0.4h, v0.4s ; CHECK-NO16-SD-NEXT: ret ; -; CHECK-FP16-SD-LABEL: test_v4f16: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzu v0.4h, v0.4h, #2 -; CHECK-FP16-SD-NEXT: ret +; CHECK-FP16-LABEL: test_v4f16: +; CHECK-FP16: // %bb.0: +; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h, #2 +; CHECK-FP16-NEXT: ret ; ; CHECK-NO16-GI-LABEL: test_v4f16: ; CHECK-NO16-GI: // %bb.0: @@ -551,13 +404,6 @@ define <4 x i16> @test_v4f16(<4 x half> %in) { ; CHECK-NO16-GI-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NO16-GI-NEXT: xtn v0.4h, v0.4s ; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test_v4f16: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: movi v1.4h, #68, lsl #8 -; CHECK-FP16-GI-NEXT: fmul v0.4h, v0.4h, v1.4h -; CHECK-FP16-GI-NEXT: fcvtzu v0.4h, v0.4h -; CHECK-FP16-GI-NEXT: ret %scale = fmul <4 x half> %in, %val = fptoui <4 x half> %scale to <4 x i16> ret <4 x i16> %val @@ -613,89 +459,30 @@ declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f16(<4 x half>) declare <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float>) define <2 x i32> @test1_sat(<2 x float> %f) { -; CHECK-NO16-SD-LABEL: test1_sat: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.2s, v0.2s, #4 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test1_sat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.2s, v0.2s, #4 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test1_sat: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test1_sat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test1_sat: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.2s, v0.2s, #4 +; CHECK-NEXT: ret %mul.i = fmul <2 x float> %f, %vcvt.i = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f32(<2 x float> %mul.i) ret <2 x i32> %vcvt.i } define <4 x i32> @test2_sat(<4 x float> %f) { -; CHECK-NO16-SD-LABEL: test2_sat: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.4s, v0.4s, #3 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test2_sat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s, #3 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test2_sat: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #8.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.4s, v0.4s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test2_sat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #8.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.4s, v0.4s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test2_sat: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.4s, v0.4s, #3 +; CHECK-NEXT: ret %mul.i = fmul <4 x float> %f, %vcvt.i = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %mul.i) ret <4 x i32> %vcvt.i } define <2 x i64> @test3_sat(<2 x double> %d) { -; CHECK-NO16-SD-LABEL: test3_sat: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.2d, v0.2d, #5 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test3_sat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d, #5 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test3_sat: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: mov x8, #4629700416936869888 // =0x4040000000000000 -; CHECK-NO16-GI-NEXT: fmov d1, x8 -; CHECK-NO16-GI-NEXT: fmul v0.2d, v0.2d, v1.d[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.2d, v0.2d -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test3_sat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: mov x8, #4629700416936869888 // =0x4040000000000000 -; CHECK-FP16-GI-NEXT: fmov d1, x8 -; CHECK-FP16-GI-NEXT: fmul v0.2d, v0.2d, v1.d[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test3_sat: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.2d, v0.2d, #5 +; CHECK-NEXT: ret %mul.i = fmul <2 x double> %d, %vcvt.i = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double> %mul.i) ret <2 x i64> %vcvt.i @@ -729,12 +516,10 @@ define <2 x i32> @test4_sat(<2 x double> %d) { ; ; CHECK-NO16-GI-LABEL: test4_sat: ; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov d1, #16.00000000 +; CHECK-NO16-GI-NEXT: fcvtzs v0.2d, v0.2d, #4 ; CHECK-NO16-GI-NEXT: adrp x8, .LCPI21_1 -; CHECK-NO16-GI-NEXT: fmul v0.2d, v0.2d, v1.d[0] ; CHECK-NO16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI21_1] ; CHECK-NO16-GI-NEXT: adrp x8, .LCPI21_0 -; CHECK-NO16-GI-NEXT: fcvtzs v0.2d, v0.2d ; CHECK-NO16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d ; CHECK-NO16-GI-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-NO16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI21_0] @@ -745,12 +530,10 @@ define <2 x i32> @test4_sat(<2 x double> %d) { ; ; CHECK-FP16-GI-LABEL: test4_sat: ; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov d1, #16.00000000 +; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d, #4 ; CHECK-FP16-GI-NEXT: adrp x8, .LCPI21_1 -; CHECK-FP16-GI-NEXT: fmul v0.2d, v0.2d, v1.d[0] ; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI21_1] ; CHECK-FP16-GI-NEXT: adrp x8, .LCPI21_0 -; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d ; CHECK-FP16-GI-NEXT: cmgt v2.2d, v1.2d, v0.2d ; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-FP16-GI-NEXT: ldr q1, [x8, :lo12:.LCPI21_0] @@ -785,22 +568,18 @@ define <2 x i16> @test5_sat(<2 x float> %f) { ; ; CHECK-NO16-GI-LABEL: test5_sat: ; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-NO16-GI-NEXT: mvni v2.2s, #127, msl #8 -; CHECK-NO16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] ; CHECK-NO16-GI-NEXT: movi v1.2s, #127, msl #8 -; CHECK-NO16-GI-NEXT: fcvtzs v0.2s, v0.2s +; CHECK-NO16-GI-NEXT: fcvtzs v0.2s, v0.2s, #4 +; CHECK-NO16-GI-NEXT: mvni v2.2s, #127, msl #8 ; CHECK-NO16-GI-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-NO16-GI-NEXT: smax v0.2s, v0.2s, v2.2s ; CHECK-NO16-GI-NEXT: ret ; ; CHECK-FP16-GI-LABEL: test5_sat: ; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-FP16-GI-NEXT: mvni v2.2s, #127, msl #8 -; CHECK-FP16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] ; CHECK-FP16-GI-NEXT: movi v1.2s, #127, msl #8 -; CHECK-FP16-GI-NEXT: fcvtzs v0.2s, v0.2s +; CHECK-FP16-GI-NEXT: fcvtzs v0.2s, v0.2s, #4 +; CHECK-FP16-GI-NEXT: mvni v2.2s, #127, msl #8 ; CHECK-FP16-GI-NEXT: smin v0.2s, v0.2s, v1.2s ; CHECK-FP16-GI-NEXT: smax v0.2s, v0.2s, v2.2s ; CHECK-FP16-GI-NEXT: ret @@ -811,33 +590,11 @@ define <2 x i16> @test5_sat(<2 x float> %f) { ; Truncate float to i16 define <4 x i16> @test5l_sat(<4 x float> %f) { -; CHECK-NO16-SD-LABEL: test5l_sat: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.4s, v0.4s, #4 -; CHECK-NO16-SD-NEXT: sqxtn v0.4h, v0.4s -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test5l_sat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s, #4 -; CHECK-FP16-SD-NEXT: sqxtn v0.4h, v0.4s -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test5l_sat: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.4s, v0.4s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-NO16-GI-NEXT: sqxtn v0.4h, v0.4s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test5l_sat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.4s, v0.4s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-FP16-GI-NEXT: sqxtn v0.4h, v0.4s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test5l_sat: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.4s, v0.4s, #4 +; CHECK-NEXT: sqxtn v0.4h, v0.4s +; CHECK-NEXT: ret %mul.i = fmul <4 x float> %f, %vcvt.i = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f32(<4 x float> %mul.i) ret <4 x i16> %vcvt.i @@ -882,29 +639,10 @@ define <2 x i64> @test6_sat(<2 x float> %f) { } define <2 x i32> @test7_sat(<2 x float> %f) { -; CHECK-NO16-SD-LABEL: test7_sat: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzu v0.2s, v0.2s, #4 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test7_sat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzu v0.2s, v0.2s, #4 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test7_sat: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzu v0.2s, v0.2s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test7_sat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #16.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzu v0.2s, v0.2s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test7_sat: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzu v0.2s, v0.2s, #4 +; CHECK-NEXT: ret %mul.i = fmul <2 x float> %f, %vcvt.i = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f32(<2 x float> %mul.i) ret <2 x i32> %vcvt.i @@ -1092,31 +830,10 @@ define <2 x i32> @test13_sat(<2 x float> %f) { ; Test case where const is max power of 2 (i.e., 2^32). define <2 x i32> @test14_sat(<2 x float> %f) { -; CHECK-NO16-SD-LABEL: test14_sat: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: fcvtzs v0.2s, v0.2s, #32 -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test14_sat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.2s, v0.2s, #32 -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test14_sat: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: mov w8, #1333788672 // =0x4f800000 -; CHECK-NO16-GI-NEXT: fmov s1, w8 -; CHECK-NO16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-NO16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test14_sat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: mov w8, #1333788672 // =0x4f800000 -; CHECK-FP16-GI-NEXT: fmov s1, w8 -; CHECK-FP16-GI-NEXT: fmul v0.2s, v0.2s, v1.s[0] -; CHECK-FP16-GI-NEXT: fcvtzs v0.2s, v0.2s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test14_sat: +; CHECK: // %bb.0: +; CHECK-NEXT: fcvtzs v0.2s, v0.2s, #32 +; CHECK-NEXT: ret %mul.i = fmul <2 x float> %f, %vcvt.i = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f32(<2 x float> %mul.i) ret <2 x i32> %vcvt.i @@ -1177,10 +894,10 @@ define <8 x i16> @test_v8f16_sat(<8 x half> %in) { ; CHECK-NO16-SD-NEXT: sqxtn2 v0.8h, v1.4s ; CHECK-NO16-SD-NEXT: ret ; -; CHECK-FP16-SD-LABEL: test_v8f16_sat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h, #2 -; CHECK-FP16-SD-NEXT: ret +; CHECK-FP16-LABEL: test_v8f16_sat: +; CHECK-FP16: // %bb.0: +; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h, #2 +; CHECK-FP16-NEXT: ret ; ; CHECK-NO16-GI-LABEL: test_v8f16_sat: ; CHECK-NO16-GI: // %bb.0: @@ -1199,13 +916,6 @@ define <8 x i16> @test_v8f16_sat(<8 x half> %in) { ; CHECK-NO16-GI-NEXT: sqxtn v0.4h, v1.4s ; CHECK-NO16-GI-NEXT: sqxtn2 v0.8h, v2.4s ; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test_v8f16_sat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: movi v1.8h, #68, lsl #8 -; CHECK-FP16-GI-NEXT: fmul v0.8h, v0.8h, v1.8h -; CHECK-FP16-GI-NEXT: fcvtzs v0.8h, v0.8h -; CHECK-FP16-GI-NEXT: ret %mul.i = fmul <8 x half> %in, %val = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> %mul.i) ret <8 x i16> %val @@ -1223,10 +933,10 @@ define <4 x i16> @test_v4f16_sat(<4 x half> %in) { ; CHECK-NO16-SD-NEXT: uqxtn v0.4h, v0.4s ; CHECK-NO16-SD-NEXT: ret ; -; CHECK-FP16-SD-LABEL: test_v4f16_sat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: fcvtzu v0.4h, v0.4h, #2 -; CHECK-FP16-SD-NEXT: ret +; CHECK-FP16-LABEL: test_v4f16_sat: +; CHECK-FP16: // %bb.0: +; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h, #2 +; CHECK-FP16-NEXT: ret ; ; CHECK-NO16-GI-LABEL: test_v4f16_sat: ; CHECK-NO16-GI: // %bb.0: @@ -1239,13 +949,6 @@ define <4 x i16> @test_v4f16_sat(<4 x half> %in) { ; CHECK-NO16-GI-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NO16-GI-NEXT: uqxtn v0.4h, v0.4s ; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test_v4f16_sat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: movi v1.4h, #68, lsl #8 -; CHECK-FP16-GI-NEXT: fmul v0.4h, v0.4h, v1.4h -; CHECK-FP16-GI-NEXT: fcvtzu v0.4h, v0.4h -; CHECK-FP16-GI-NEXT: ret %mul.i = fmul <4 x half> %in, %val = call <4 x i16> @llvm.fptoui.sat.v4i16.v4f16(<4 x half> %mul.i) ret <4 x i16> %val @@ -1286,37 +989,12 @@ define <4 x i32> @test_v4f16_i32_sat(<4 x half> %in) { } define <4 x i32> @test_extrasat(<4 x float> %f) { -; CHECK-NO16-SD-LABEL: test_extrasat: -; CHECK-NO16-SD: // %bb.0: -; CHECK-NO16-SD-NEXT: movi v1.2d, #0xffffff00ffffff -; CHECK-NO16-SD-NEXT: fcvtzu v0.4s, v0.4s, #3 -; CHECK-NO16-SD-NEXT: umin v0.4s, v0.4s, v1.4s -; CHECK-NO16-SD-NEXT: ret -; -; CHECK-FP16-SD-LABEL: test_extrasat: -; CHECK-FP16-SD: // %bb.0: -; CHECK-FP16-SD-NEXT: movi v1.2d, #0xffffff00ffffff -; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s, #3 -; CHECK-FP16-SD-NEXT: umin v0.4s, v0.4s, v1.4s -; CHECK-FP16-SD-NEXT: ret -; -; CHECK-NO16-GI-LABEL: test_extrasat: -; CHECK-NO16-GI: // %bb.0: -; CHECK-NO16-GI-NEXT: fmov s1, #8.00000000 -; CHECK-NO16-GI-NEXT: fmul v0.4s, v0.4s, v1.s[0] -; CHECK-NO16-GI-NEXT: movi v1.2d, #0xffffff00ffffff -; CHECK-NO16-GI-NEXT: fcvtzu v0.4s, v0.4s -; CHECK-NO16-GI-NEXT: umin v0.4s, v0.4s, v1.4s -; CHECK-NO16-GI-NEXT: ret -; -; CHECK-FP16-GI-LABEL: test_extrasat: -; CHECK-FP16-GI: // %bb.0: -; CHECK-FP16-GI-NEXT: fmov s1, #8.00000000 -; CHECK-FP16-GI-NEXT: fmul v0.4s, v0.4s, v1.s[0] -; CHECK-FP16-GI-NEXT: movi v1.2d, #0xffffff00ffffff -; CHECK-FP16-GI-NEXT: fcvtzu v0.4s, v0.4s -; CHECK-FP16-GI-NEXT: umin v0.4s, v0.4s, v1.4s -; CHECK-FP16-GI-NEXT: ret +; CHECK-LABEL: test_extrasat: +; CHECK: // %bb.0: +; CHECK-NEXT: movi v1.2d, #0xffffff00ffffff +; CHECK-NEXT: fcvtzu v0.4s, v0.4s, #3 +; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s +; CHECK-NEXT: ret %mul.i = fmul <4 x float> %f, %vcvt.i = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float> %mul.i) %t = zext <4 x i24> %vcvt.i to <4 x i32> diff --git a/llvm/test/CodeGen/AArch64/funnel-shift.ll b/llvm/test/CodeGen/AArch64/funnel-shift.ll index 90fb10258dffb..e0bbfc620e2f8 100644 --- a/llvm/test/CodeGen/AArch64/funnel-shift.ll +++ b/llvm/test/CodeGen/AArch64/funnel-shift.ll @@ -256,6 +256,34 @@ define i8 @fshl_i8_const_fold() { ret i8 %f } +define i32 @fshl_scalar_undef_shift() { +; CHECK-SD-LABEL: fshl_scalar_undef_shift: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov w0, #1 // =0x1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: fshl_scalar_undef_shift: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov w0, #-1 // =0xffffffff +; CHECK-GI-NEXT: ret + %1 = call i32 @llvm.fshl.i32(i32 1, i32 2, i32 undef) + ret i32 %1 +} + +define <2 x i32> @fshl_vector_undef_shift() { +; CHECK-SD-LABEL: fshl_vector_undef_shift: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: movi v0.2s, #1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: fshl_vector_undef_shift: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: movi d0, #0xffffffffffffffff +; CHECK-GI-NEXT: ret + %1 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> , <2 x i32> , <2 x i32> undef) + ret <2 x i32> %1 +} + ; Repeat everything for funnel shift right. ; General case - all operands can be variables. @@ -448,6 +476,34 @@ define i8 @fshr_i8_const_fold() { ret i8 %f } +define i32 @fshr_scalar_undef_shift() { +; CHECK-SD-LABEL: fshr_scalar_undef_shift: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov w0, #2 // =0x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: fshr_scalar_undef_shift: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov w0, #-1 // =0xffffffff +; CHECK-GI-NEXT: ret + %1 = call i32 @llvm.fshr.i32(i32 1, i32 2, i32 undef) + ret i32 %1 +} + +define <2 x i32> @fshr_vector_undef_shift() { +; CHECK-SD-LABEL: fshr_vector_undef_shift: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: movi v0.2s, #2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: fshr_vector_undef_shift: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: movi d0, #0xffffffffffffffff +; CHECK-GI-NEXT: ret + %1 = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> , <2 x i32> , <2 x i32> undef) + ret <2 x i32> %1 +} + define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) { ; CHECK-LABEL: fshl_i32_shift_by_bitwidth: ; CHECK: // %bb.0: diff --git a/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll b/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll index fa00c75e2928b..f12fe1f8c0c0d 100644 --- a/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll +++ b/llvm/test/CodeGen/AArch64/instr-ref-ldv.ll @@ -9,7 +9,7 @@ ; Before aarch64-isel ; %11:gpr32 = ORRWrr $wzr, killed %10:gpr32, debug-location !5; :0 -; %0:gpr64all = SUBREG_TO_REG 0, killed %11:gpr32, %subreg.sub_32, debug-location !5; :0 +; %0:gpr64all = SUBREG_TO_REG killed %11:gpr32, %subreg.sub_32, debug-location !5; :0 ; DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0), %0:gpr64all, debug-location !11; :0 @[ :0 ] line no:0 ; Before livedebugvalues diff --git a/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll b/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll index 49a0086a7be54..33e7c69f041d4 100644 --- a/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll +++ b/llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll @@ -349,9 +349,8 @@ define i32 @ctz_v16i1(<16 x i1> %a) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.16b, v0.16b, #7 ; NONSTREAMING-NEXT: ptrue p0.b, vl16 -; NONSTREAMING-NEXT: ptrue p1.b -; NONSTREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: cntp x0, p0, p0.b ; NONSTREAMING-NEXT: ret ; @@ -359,10 +358,9 @@ define i32 @ctz_v16i1(<16 x i1> %a) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.b, z0.b, #7 ; STREAMING-NEXT: ptrue p0.b, vl16 -; STREAMING-NEXT: ptrue p1.b ; STREAMING-NEXT: asr z0.b, z0.b, #7 -; STREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: cntp x0, p0, p0.b ; STREAMING-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 0) @@ -374,9 +372,8 @@ define i32 @ctz_v16i1_poison(<16 x i1> %a) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.16b, v0.16b, #7 ; NONSTREAMING-NEXT: ptrue p0.b, vl16 -; NONSTREAMING-NEXT: ptrue p1.b -; NONSTREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: cntp x0, p0, p0.b ; NONSTREAMING-NEXT: ret ; @@ -384,10 +381,9 @@ define i32 @ctz_v16i1_poison(<16 x i1> %a) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.b, z0.b, #7 ; STREAMING-NEXT: ptrue p0.b, vl16 -; STREAMING-NEXT: ptrue p1.b ; STREAMING-NEXT: asr z0.b, z0.b, #7 -; STREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: cntp x0, p0, p0.b ; STREAMING-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 1) @@ -399,9 +395,8 @@ define i64 @add_i64_ctz_v16i1_poison(<16 x i1> %a, i64 %b) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.16b, v0.16b, #7 ; NONSTREAMING-NEXT: ptrue p0.b, vl16 -; NONSTREAMING-NEXT: ptrue p1.b -; NONSTREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: incp x0, p0.b ; NONSTREAMING-NEXT: ret ; @@ -409,10 +404,9 @@ define i64 @add_i64_ctz_v16i1_poison(<16 x i1> %a, i64 %b) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.b, z0.b, #7 ; STREAMING-NEXT: ptrue p0.b, vl16 -; STREAMING-NEXT: ptrue p1.b ; STREAMING-NEXT: asr z0.b, z0.b, #7 -; STREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: incp x0, p0.b ; STREAMING-NEXT: ret %res = call i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1> %a, i1 1) @@ -425,9 +419,8 @@ define i32 @ctz_v8i1(<8 x i1> %a) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.8b, v0.8b, #7 ; NONSTREAMING-NEXT: ptrue p0.b, vl8 -; NONSTREAMING-NEXT: ptrue p1.b -; NONSTREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: cntp x0, p0, p0.b ; NONSTREAMING-NEXT: ret ; @@ -435,10 +428,9 @@ define i32 @ctz_v8i1(<8 x i1> %a) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.b, z0.b, #7 ; STREAMING-NEXT: ptrue p0.b, vl8 -; STREAMING-NEXT: ptrue p1.b ; STREAMING-NEXT: asr z0.b, z0.b, #7 -; STREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: cntp x0, p0, p0.b ; STREAMING-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.v8i1(<8 x i1> %a, i1 0) @@ -450,9 +442,8 @@ define i32 @ctz_v8i1_poison(<8 x i1> %a) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.8b, v0.8b, #7 ; NONSTREAMING-NEXT: ptrue p0.b, vl8 -; NONSTREAMING-NEXT: ptrue p1.b -; NONSTREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: cntp x0, p0, p0.b ; NONSTREAMING-NEXT: ret ; @@ -460,10 +451,9 @@ define i32 @ctz_v8i1_poison(<8 x i1> %a) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.b, z0.b, #7 ; STREAMING-NEXT: ptrue p0.b, vl8 -; STREAMING-NEXT: ptrue p1.b ; STREAMING-NEXT: asr z0.b, z0.b, #7 -; STREAMING-NEXT: cmpne p0.b, p0/z, z0.b, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: cntp x0, p0, p0.b ; STREAMING-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.v8i1(<8 x i1> %a, i1 1) @@ -475,9 +465,8 @@ define i32 @ctz_v4i1(<4 x i1> %a) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.4h, v0.4h, #15 ; NONSTREAMING-NEXT: ptrue p0.h, vl4 -; NONSTREAMING-NEXT: ptrue p1.h -; NONSTREAMING-NEXT: cmpne p0.h, p0/z, z0.h, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.h, p0/z, z0.h, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: cntp x0, p0, p0.h ; NONSTREAMING-NEXT: ret ; @@ -485,10 +474,9 @@ define i32 @ctz_v4i1(<4 x i1> %a) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.h, z0.h, #15 ; STREAMING-NEXT: ptrue p0.h, vl4 -; STREAMING-NEXT: ptrue p1.h ; STREAMING-NEXT: asr z0.h, z0.h, #15 -; STREAMING-NEXT: cmpne p0.h, p0/z, z0.h, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.h, p0/z, z0.h, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: cntp x0, p0, p0.h ; STREAMING-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1> %a, i1 0) @@ -500,9 +488,8 @@ define i32 @ctz_v4i1_poison(<4 x i1> %a) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.4h, v0.4h, #15 ; NONSTREAMING-NEXT: ptrue p0.h, vl4 -; NONSTREAMING-NEXT: ptrue p1.h -; NONSTREAMING-NEXT: cmpne p0.h, p0/z, z0.h, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.h, p0/z, z0.h, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: cntp x0, p0, p0.h ; NONSTREAMING-NEXT: ret ; @@ -510,10 +497,9 @@ define i32 @ctz_v4i1_poison(<4 x i1> %a) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.h, z0.h, #15 ; STREAMING-NEXT: ptrue p0.h, vl4 -; STREAMING-NEXT: ptrue p1.h ; STREAMING-NEXT: asr z0.h, z0.h, #15 -; STREAMING-NEXT: cmpne p0.h, p0/z, z0.h, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.h, p0/z, z0.h, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: cntp x0, p0, p0.h ; STREAMING-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.v4i1(<4 x i1> %a, i1 1) @@ -525,9 +511,8 @@ define i32 @ctz_v2i1(<2 x i1> %a) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.2s, v0.2s, #31 ; NONSTREAMING-NEXT: ptrue p0.s, vl2 -; NONSTREAMING-NEXT: ptrue p1.s -; NONSTREAMING-NEXT: cmpne p0.s, p0/z, z0.s, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.s, p0/z, z0.s, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: cntp x0, p0, p0.s ; NONSTREAMING-NEXT: ret ; @@ -535,10 +520,9 @@ define i32 @ctz_v2i1(<2 x i1> %a) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.s, z0.s, #31 ; STREAMING-NEXT: ptrue p0.s, vl2 -; STREAMING-NEXT: ptrue p1.s ; STREAMING-NEXT: asr z0.s, z0.s, #31 -; STREAMING-NEXT: cmpne p0.s, p0/z, z0.s, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.s, p0/z, z0.s, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: cntp x0, p0, p0.s ; STREAMING-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> %a, i1 0) @@ -550,9 +534,8 @@ define i32 @ctz_v2i1_poison(<2 x i1> %a) { ; NONSTREAMING: // %bb.0: ; NONSTREAMING-NEXT: shl v0.2s, v0.2s, #31 ; NONSTREAMING-NEXT: ptrue p0.s, vl2 -; NONSTREAMING-NEXT: ptrue p1.s -; NONSTREAMING-NEXT: cmpne p0.s, p0/z, z0.s, #0 -; NONSTREAMING-NEXT: brkb p0.b, p1/z, p0.b +; NONSTREAMING-NEXT: cmpne p1.s, p0/z, z0.s, #0 +; NONSTREAMING-NEXT: brkb p0.b, p0/z, p1.b ; NONSTREAMING-NEXT: cntp x0, p0, p0.s ; NONSTREAMING-NEXT: ret ; @@ -560,10 +543,9 @@ define i32 @ctz_v2i1_poison(<2 x i1> %a) { ; STREAMING: // %bb.0: ; STREAMING-NEXT: lsl z0.s, z0.s, #31 ; STREAMING-NEXT: ptrue p0.s, vl2 -; STREAMING-NEXT: ptrue p1.s ; STREAMING-NEXT: asr z0.s, z0.s, #31 -; STREAMING-NEXT: cmpne p0.s, p0/z, z0.s, #0 -; STREAMING-NEXT: brkb p0.b, p1/z, p0.b +; STREAMING-NEXT: cmpne p1.s, p0/z, z0.s, #0 +; STREAMING-NEXT: brkb p0.b, p0/z, p1.b ; STREAMING-NEXT: cntp x0, p0, p0.s ; STREAMING-NEXT: ret %res = call i32 @llvm.experimental.cttz.elts.i32.v2i1(<2 x i1> %a, i1 1) diff --git a/llvm/test/CodeGen/AArch64/loop-sink.mir b/llvm/test/CodeGen/AArch64/loop-sink.mir index 7e081ecf4c6f5..fcade6c451625 100644 --- a/llvm/test/CodeGen/AArch64/loop-sink.mir +++ b/llvm/test/CodeGen/AArch64/loop-sink.mir @@ -338,7 +338,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY2]], %bb.0, %7, %bb.9 ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[PHI]], 0 :: (load (s8) from %ir.lsr.iv) - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[LDRBBui]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG killed [[LDRBBui]], %subreg.sub_32 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri killed [[COPY3]], 50, 0, implicit-def $nzcv ; CHECK-NEXT: Bcc 8, %bb.9, implicit $nzcv @@ -433,7 +433,7 @@ body: | %6:gpr64sp = PHI %5, %bb.0, %7, %bb.8 %17:gpr32 = LDRBBui %6, 0 :: (load (s8) from %ir.lsr.iv) - %16:gpr64 = SUBREG_TO_REG 0, killed %17, %subreg.sub_32 + %16:gpr64 = SUBREG_TO_REG killed %17, %subreg.sub_32 %18:gpr32sp = COPY %16.sub_32 %19:gpr32 = SUBSWri killed %18, 50, 0, implicit-def $nzcv Bcc 8, %bb.8, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/neon-abd.ll b/llvm/test/CodeGen/AArch64/neon-abd.ll index c9f3fc44ddcb1..e0406e40ff6de 100644 --- a/llvm/test/CodeGen/AArch64/neon-abd.ll +++ b/llvm/test/CodeGen/AArch64/neon-abd.ll @@ -743,6 +743,60 @@ entry: ret <8 x i32> %r } +define <4 x i32> @abs_sub(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: abs_sub: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: sabd v0.4s, v1.4s, v0.4s +; CHECK-NEXT: ret +entry: + %add = sub nsw <4 x i32> %b, %a + %cmp.i = icmp slt <4 x i32> %add, zeroinitializer + %sub.i = sub nsw <4 x i32> zeroinitializer, %add + %cond.i = select <4 x i1> %cmp.i, <4 x i32> %sub.i, <4 x i32> %add + ret <4 x i32> %cond.i +} + +; short abs_diff_add_i16_rir(short a, short c) { +; return abs(a - 0x492) + c; +; } +define <4 x i16> @abs_diff_add_v4i16(<4 x i16> %a, <4 x i16> %c) { +; CHECK-LABEL: abs_diff_add_v4i16: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov w8, #1170 // =0x492 +; CHECK-NEXT: dup v2.4h, w8 +; CHECK-NEXT: saba v1.4h, v0.4h, v2.4h +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret +entry: + %conv = sext <4 x i16> %a to <4 x i32> + %sub = add nsw <4 x i32> %conv, splat(i32 -1170) + %0 = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) + %1 = trunc <4 x i32> %0 to <4 x i16> + %conv2 = add <4 x i16> %1, %c + ret <4 x i16> %conv2 +} + +; short abs_diff_add_<4 x i16>_rii(short a) { +; return abs(a - 0x93) + 0x943; +; } +define <4 x i16> @abs_diff_add_v4i16_rii(<4 x i16> %a) { +; CHECK-LABEL: abs_diff_add_v4i16_rii: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov w8, #2371 // =0x943 +; CHECK-NEXT: movi v2.4h, #147 +; CHECK-NEXT: dup v1.4h, w8 +; CHECK-NEXT: saba v1.4h, v0.4h, v2.4h +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret +entry: + %conv = sext <4 x i16> %a to <4 x i32> + %sub = add nsw <4 x i32> %conv, splat(i32 -147) + %0 = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) + %1 = trunc <4 x i32> %0 to <4 x i16> + %conv1 = add nuw <4 x i16> %1, splat(i16 2371) + ret <4 x i16> %conv1 +} + declare <8 x i8> @llvm.abs.v8i8(<8 x i8>, i1) declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1) diff --git a/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir b/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir index 0ebdedadb2b7c..4b3d1e0af73fa 100644 --- a/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir +++ b/llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir @@ -44,7 +44,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0 ; CHECK-NEXT: [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY]], 1, 0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[SUBWri]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG killed [[SUBWri]], %subreg.sub_32 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = nuw nsw UBFMXri killed [[SUBREG_TO_REG]], 63, 31 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/peephole-movd.mir b/llvm/test/CodeGen/AArch64/peephole-movd.mir index bd7f0ab3f044e..3e4224dc29f38 100644 --- a/llvm/test/CodeGen/AArch64/peephole-movd.mir +++ b/llvm/test/CodeGen/AArch64/peephole-movd.mir @@ -13,7 +13,7 @@ body: | ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub ; CHECK-NEXT: [[UQSHLv8i8_shift:%[0-9]+]]:fpr64 = UQSHLv8i8_shift killed [[COPY]], 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, [[UQSHLv8i8_shift]], %subreg.dsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG [[UQSHLv8i8_shift]], %subreg.dsub ; CHECK-NEXT: [[TBLv8i8One:%[0-9]+]]:fpr64 = TBLv8i8One killed [[SUBREG_TO_REG]], [[UQSHLv8i8_shift]] ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UQSHLv8i8_shift]], %subreg.dsub @@ -22,7 +22,7 @@ body: | %1:fpr64 = COPY %0.dsub:fpr128 %2:fpr64 = UQSHLv8i8_shift killed %1:fpr64, 1 %3:fpr64 = FMOVDr %2:fpr64 - %4:fpr128 = SUBREG_TO_REG 0, killed %3:fpr64, %subreg.dsub + %4:fpr128 = SUBREG_TO_REG killed %3:fpr64, %subreg.dsub %5:fpr64 = TBLv8i8One killed %4:fpr128, %2:fpr64 %7:fpr128 = IMPLICIT_DEF %6:fpr128 = INSERT_SUBREG %7:fpr128, killed %2:fpr64, %subreg.dsub @@ -40,7 +40,7 @@ body: | ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub ; CHECK-NEXT: [[UQSHLv8i8_shift:%[0-9]+]]:fpr64 = UQSHLv8i8_shift killed [[COPY]], 1 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG 0, [[UQSHLv8i8_shift]], %subreg.dsub + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr128 = SUBREG_TO_REG [[UQSHLv8i8_shift]], %subreg.dsub ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UQSHLv8i8_shift]], %subreg.dsub ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF @@ -50,7 +50,7 @@ body: | %1:fpr64 = COPY %0.dsub:fpr128 %2:fpr64 = UQSHLv8i8_shift killed %1:fpr64, 1 %3:fpr64 = FMOVDr %2:fpr64 - %4:fpr128 = SUBREG_TO_REG 0, %3:fpr64, %subreg.dsub + %4:fpr128 = SUBREG_TO_REG %3:fpr64, %subreg.dsub %7:fpr128 = IMPLICIT_DEF %6:fpr128 = INSERT_SUBREG %7:fpr128, killed %2:fpr64, %subreg.dsub %9:fpr128 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AArch64/peephole-sxtw.mir b/llvm/test/CodeGen/AArch64/peephole-sxtw.mir index b57b2b71dc707..a71c6bc09eb2d 100644 --- a/llvm/test/CodeGen/AArch64/peephole-sxtw.mir +++ b/llvm/test/CodeGen/AArch64/peephole-sxtw.mir @@ -59,7 +59,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY2]], [[COPY1]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBWrr]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[SUBWrr]], %subreg.sub_32 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) @@ -83,7 +83,7 @@ body: | %8:gpr32 = COPY $wzr %9:gpr32 = SUBWrr %8, %7 %10:gpr32 = ORRWrs $wzr, %9, 0 - %1:gpr64 = SUBREG_TO_REG 0, %10, %subreg.sub_32 + %1:gpr64 = SUBREG_TO_REG %10, %subreg.sub_32 bb.1: successors: %bb.2(0x80000000) @@ -113,7 +113,7 @@ body: | %0:gpr64 = COPY $x0 %1:gpr32 = COPY %0.sub_32 %2:gpr32 = ORRWrr $wzr, %1 - %3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32 + %3:gpr64 = SUBREG_TO_REG %2, %subreg.sub_32 %4:gpr32sp = COPY %3.sub_32 %5:gpr32sp = ADDWri %4, 1, 0 $w0 = COPY %5 @@ -131,7 +131,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr $wzr, [[COPY1]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrr]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrr]], %subreg.sub_32 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY2]], 1, 0 ; CHECK-NEXT: $w0 = COPY [[ADDWri]] @@ -140,7 +140,7 @@ body: | %0:gpr64 = COPY $x0 %1:gpr32 = COPY %0.sub_32 %2:gpr32 = ORRWrr $wzr, %1 - %3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32 + %3:gpr64 = SUBREG_TO_REG %2, %subreg.sub_32 %4:gpr32sp = COPY %3.sub_32 %5:gpr32sp = ADDWri %4, 1, 0 $w0 = COPY %5 diff --git a/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-relative-load.ll b/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-relative-load.ll new file mode 100644 index 0000000000000..2baa72b9a0107 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-relative-load.ll @@ -0,0 +1,570 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple arm64e-apple-darwin -global-isel=0 -verify-machineinstrs \ +; RUN: -aarch64-ptrauth-auth-checks=none | FileCheck %s -DL="L" --check-prefix=UNCHECKED +; RUN: llc < %s -mtriple arm64e-apple-darwin -global-isel -global-isel-abort=1 -verify-machineinstrs \ +; RUN: -aarch64-ptrauth-auth-checks=none | FileCheck %s -DL="L" --check-prefix=UNCHECKED + +; RUN: llc < %s -mtriple arm64e-apple-darwin -global-isel=0 -verify-machineinstrs \ +; RUN: | FileCheck %s -DL="L" --check-prefix=CHECKED +; RUN: llc < %s -mtriple arm64e-apple-darwin -global-isel -global-isel-abort=1 -verify-machineinstrs \ +; RUN: | FileCheck %s -DL="L" --check-prefix=CHECKED + +; RUN: llc < %s -mtriple arm64e-apple-darwin -global-isel=0 -verify-machineinstrs \ +; RUN: -aarch64-ptrauth-auth-checks=trap | FileCheck %s -DL="L" --check-prefix=TRAP +; RUN: llc < %s -mtriple arm64e-apple-darwin -global-isel -global-isel-abort=1 -verify-machineinstrs \ +; RUN: -aarch64-ptrauth-auth-checks=trap | FileCheck %s -DL="L" --check-prefix=TRAP + +; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -global-isel=0 -verify-machineinstrs \ +; RUN: -aarch64-ptrauth-auth-checks=none | FileCheck %s -DL=".L" --check-prefix=UNCHECKED +; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -global-isel -global-isel-abort=1 -verify-machineinstrs \ +; RUN: -aarch64-ptrauth-auth-checks=none | FileCheck %s -DL=".L" --check-prefix=UNCHECKED + +; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -global-isel=0 -verify-machineinstrs \ +; RUN: | FileCheck %s -DL=".L" --check-prefix=CHECKED +; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -global-isel -global-isel-abort=1 -verify-machineinstrs \ +; RUN: | FileCheck %s -DL=".L" --check-prefix=CHECKED + +; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -global-isel=0 -verify-machineinstrs \ +; RUN: -aarch64-ptrauth-auth-checks=trap | FileCheck %s -DL=".L" --check-prefix=TRAP +; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -global-isel -global-isel-abort=1 -verify-machineinstrs \ +; RUN: -aarch64-ptrauth-auth-checks=trap | FileCheck %s -DL=".L" --check-prefix=TRAP + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +define i64 @test_resign_load_relative_ia_ia(i64 %arg, i64 %arg1, i64 %arg2) { +; UNCHECKED-LABEL: test_resign_load_relative_ia_ia: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autia x16, x1 +; UNCHECKED-NEXT: ldrsw x17, [x16, #-256]! +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: pacia x16, x2 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_ia_ia: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autia x16, x1 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpaci x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_0 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_0 +; CHECKED-NEXT: Lauth_success_0: +; CHECKED-NEXT: ldrsw x17, [x16, #-256]! +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: pacia x16, x2 +; CHECKED-NEXT: Lresign_end_0: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_ia_ia: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autia x16, x1 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpaci x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_0 +; TRAP-NEXT: brk #0xc470 +; TRAP-NEXT: Lauth_success_0: +; TRAP-NEXT: ldrsw x17, [x16, #-256]! +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: pacia x16, x2 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg, i32 0, i64 %arg1, i32 0, i64 %arg2, i64 -256) + ret i64 %tmp +} + +; note: offset 256 is larger tha 255 (largest simm9), is uint<24> +define i64 @test_resign_load_relative_ib_ia(i64 %arg, i64 %arg1, i64 %arg2) { +; UNCHECKED-LABEL: test_resign_load_relative_ib_ia: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autib x16, x1 +; UNCHECKED-NEXT: add x16, x16, #256 +; UNCHECKED-NEXT: ldrsw x17, [x16] +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: pacia x16, x2 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_ib_ia: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autib x16, x1 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpaci x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_1 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_1 +; CHECKED-NEXT: Lauth_success_1: +; CHECKED-NEXT: add x16, x16, #256 +; CHECKED-NEXT: ldrsw x17, [x16] +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: pacia x16, x2 +; CHECKED-NEXT: Lresign_end_1: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_ib_ia: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autib x16, x1 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpaci x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_1 +; TRAP-NEXT: brk #0xc471 +; TRAP-NEXT: Lauth_success_1: +; TRAP-NEXT: add x16, x16, #256 +; TRAP-NEXT: ldrsw x17, [x16] +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: pacia x16, x2 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg, i32 1, i64 %arg1, i32 0, i64 %arg2, i64 256) + ret i64 %tmp +} + +define i64 @test_resign_load_relative_da_ia(i64 %arg, i64 %arg1, i64 %arg2) { +; UNCHECKED-LABEL: test_resign_load_relative_da_ia: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autda x16, x1 +; UNCHECKED-NEXT: add x16, x16, #256 +; UNCHECKED-NEXT: ldrsw x17, [x16] +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: pacia x16, x2 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_da_ia: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autda x16, x1 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpacd x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_2 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_2 +; CHECKED-NEXT: Lauth_success_2: +; CHECKED-NEXT: add x16, x16, #256 +; CHECKED-NEXT: ldrsw x17, [x16] +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: pacia x16, x2 +; CHECKED-NEXT: Lresign_end_2: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_da_ia: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autda x16, x1 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpacd x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_2 +; TRAP-NEXT: brk #0xc472 +; TRAP-NEXT: Lauth_success_2: +; TRAP-NEXT: add x16, x16, #256 +; TRAP-NEXT: ldrsw x17, [x16] +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: pacia x16, x2 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg, i32 2, i64 %arg1, i32 0, i64 %arg2, i64 256) + ret i64 %tmp +} + +define i64 @test_resign_load_relative_db_da(i64 %arg, i64 %arg1, i64 %arg2) { +; UNCHECKED-LABEL: test_resign_load_relative_db_da: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autdb x16, x1 +; UNCHECKED-NEXT: add x16, x16, #256 +; UNCHECKED-NEXT: ldrsw x17, [x16] +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: pacda x16, x2 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_db_da: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autdb x16, x1 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpacd x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_3 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_3 +; CHECKED-NEXT: Lauth_success_3: +; CHECKED-NEXT: add x16, x16, #256 +; CHECKED-NEXT: ldrsw x17, [x16] +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: pacda x16, x2 +; CHECKED-NEXT: Lresign_end_3: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_db_da: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autdb x16, x1 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpacd x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_3 +; TRAP-NEXT: brk #0xc473 +; TRAP-NEXT: Lauth_success_3: +; TRAP-NEXT: add x16, x16, #256 +; TRAP-NEXT: ldrsw x17, [x16] +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: pacda x16, x2 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg, i32 3, i64 %arg1, i32 2, i64 %arg2, i64 256) + ret i64 %tmp +} + +define i64 @test_resign_load_relative_iza_db(i64 %arg, i64 %arg1, i64 %arg2) { +; UNCHECKED-LABEL: test_resign_load_relative_iza_db: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autiza x16 +; UNCHECKED-NEXT: add x16, x16, #256 +; UNCHECKED-NEXT: ldrsw x17, [x16] +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: pacdb x16, x2 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_iza_db: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autiza x16 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpaci x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_4 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_4 +; CHECKED-NEXT: Lauth_success_4: +; CHECKED-NEXT: add x16, x16, #256 +; CHECKED-NEXT: ldrsw x17, [x16] +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: pacdb x16, x2 +; CHECKED-NEXT: Lresign_end_4: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_iza_db: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autiza x16 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpaci x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_4 +; TRAP-NEXT: brk #0xc470 +; TRAP-NEXT: Lauth_success_4: +; TRAP-NEXT: add x16, x16, #256 +; TRAP-NEXT: ldrsw x17, [x16] +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: pacdb x16, x2 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg, i32 0, i64 0, i32 3, i64 %arg2, i64 256) + ret i64 %tmp +} + +define i64 @test_resign_load_relative_da_dzb(i64 %arg, i64 %arg1, i64 %arg2) { +; UNCHECKED-LABEL: test_resign_load_relative_da_dzb: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autda x16, x1 +; UNCHECKED-NEXT: add x16, x16, #256 +; UNCHECKED-NEXT: ldrsw x17, [x16] +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: pacdzb x16 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_da_dzb: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autda x16, x1 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpacd x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_5 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_5 +; CHECKED-NEXT: Lauth_success_5: +; CHECKED-NEXT: add x16, x16, #256 +; CHECKED-NEXT: ldrsw x17, [x16] +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: pacdzb x16 +; CHECKED-NEXT: Lresign_end_5: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_da_dzb: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autda x16, x1 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpacd x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_5 +; TRAP-NEXT: brk #0xc472 +; TRAP-NEXT: Lauth_success_5: +; TRAP-NEXT: add x16, x16, #256 +; TRAP-NEXT: ldrsw x17, [x16] +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: pacdzb x16 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg, i32 2, i64 %arg1, i32 3, i64 0,i64 256) + ret i64 %tmp +} + +define i64 @test_resign_load_relative_da_constdisc(i64 %arg, i64 %arg1) { +; UNCHECKED-LABEL: test_resign_load_relative_da_constdisc: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autda x16, x1 +; UNCHECKED-NEXT: add x16, x16, #256 +; UNCHECKED-NEXT: ldrsw x17, [x16] +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: mov x17, #256 +; UNCHECKED-NEXT: pacda x16, x17 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_da_constdisc: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autda x16, x1 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpacd x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_6 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_6 +; CHECKED-NEXT: Lauth_success_6: +; CHECKED-NEXT: add x16, x16, #256 +; CHECKED-NEXT: ldrsw x17, [x16] +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: mov x17, #256 +; CHECKED-NEXT: pacda x16, x17 +; CHECKED-NEXT: Lresign_end_6: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_da_constdisc: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autda x16, x1 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpacd x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_6 +; TRAP-NEXT: brk #0xc472 +; TRAP-NEXT: Lauth_success_6: +; TRAP-NEXT: add x16, x16, #256 +; TRAP-NEXT: ldrsw x17, [x16] +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: mov x17, #256 +; TRAP-NEXT: pacda x16, x17 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg, i32 2, i64 %arg1, i32 2, i64 256,i64 256) + ret i64 %tmp +} + +; note: addend is larger than 24bit integer +define i64 @test_resign_load_relative_loadNegOffset_constdisc(i64 %arg,i64 %arg1) { +; UNCHECKED-LABEL: test_resign_load_relative_loadNegOffset_constdisc: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autda x16, x1 +; UNCHECKED-NEXT: mov x17, #62980 +; UNCHECKED-NEXT: movk x17, #65535, lsl #16 +; UNCHECKED-NEXT: movk x17, #65535, lsl #32 +; UNCHECKED-NEXT: movk x17, #65535, lsl #48 +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: ldrsw x17, [x16] +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: mov x17, #256 +; UNCHECKED-NEXT: pacda x16, x17 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_loadNegOffset_constdisc: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autda x16, x1 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpacd x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_7 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_7 +; CHECKED-NEXT: Lauth_success_7: +; CHECKED-NEXT: mov x17, #62980 +; CHECKED-NEXT: movk x17, #65535, lsl #16 +; CHECKED-NEXT: movk x17, #65535, lsl #32 +; CHECKED-NEXT: movk x17, #65535, lsl #48 +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: ldrsw x17, [x16] +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: mov x17, #256 +; CHECKED-NEXT: pacda x16, x17 +; CHECKED-NEXT: Lresign_end_7: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_loadNegOffset_constdisc: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autda x16, x1 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpacd x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_7 +; TRAP-NEXT: brk #0xc472 +; TRAP-NEXT: Lauth_success_7: +; TRAP-NEXT: mov x17, #62980 +; TRAP-NEXT: movk x17, #65535, lsl #16 +; TRAP-NEXT: movk x17, #65535, lsl #32 +; TRAP-NEXT: movk x17, #65535, lsl #48 +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: ldrsw x17, [x16] +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: mov x17, #256 +; TRAP-NEXT: pacda x16, x17 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg,i32 2,i64 %arg1,i32 2,i64 256,i64 -2556) + ret i64 %tmp +} +define i64 @test_resign_load_relative_largeOffset_constdisc(i64 %arg,i64 %arg1) { +; UNCHECKED-LABEL: test_resign_load_relative_largeOffset_constdisc: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: mov x16, x0 +; UNCHECKED-NEXT: autda x16, x1 +; UNCHECKED-NEXT: add x16, x16, #3884 +; UNCHECKED-NEXT: add x16, x16, #7, lsl #12 +; UNCHECKED-NEXT: ldrsw x17, [x16] +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: mov x17, #256 +; UNCHECKED-NEXT: pacda x16, x17 +; UNCHECKED-NEXT: mov x0, x16 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_resign_load_relative_largeOffset_constdisc: +; CHECKED: %bb.0: +; CHECKED-NEXT: mov x16, x0 +; CHECKED-NEXT: autda x16, x1 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpacd x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_8 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_8 +; CHECKED-NEXT: Lauth_success_8: +; CHECKED-NEXT: add x16, x16, #3884 +; CHECKED-NEXT: add x16, x16, #7, lsl #12 +; CHECKED-NEXT: ldrsw x17, [x16] +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: mov x17, #256 +; CHECKED-NEXT: pacda x16, x17 +; CHECKED-NEXT: Lresign_end_8: +; CHECKED-NEXT: mov x0, x16 +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_resign_load_relative_largeOffset_constdisc: +; TRAP: %bb.0: +; TRAP-NEXT: mov x16, x0 +; TRAP-NEXT: autda x16, x1 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpacd x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_8 +; TRAP-NEXT: brk #0xc472 +; TRAP-NEXT: Lauth_success_8: +; TRAP-NEXT: add x16, x16, #3884 +; TRAP-NEXT: add x16, x16, #7, lsl #12 +; TRAP-NEXT: ldrsw x17, [x16] +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: mov x17, #256 +; TRAP-NEXT: pacda x16, x17 +; TRAP-NEXT: mov x0, x16 +; TRAP-NEXT: ret + %tmp = call i64 @llvm.ptrauth.resign.load.relative(i64 %arg,i32 2,i64 %arg1,i32 2,i64 256,i64 32556) + ret i64 %tmp +} +define void @test_intrinsic_glue_chain_correctly_setup(ptr %0, i64 %1, ptr %2) { +; UNCHECKED-LABEL: test_intrinsic_glue_chain_correctly_setup: +; UNCHECKED: %bb.0: +; UNCHECKED-NEXT: str x2, [x0] +; UNCHECKED-NEXT: mov x16, x1 +; UNCHECKED-NEXT: mov x17, #29199 +; UNCHECKED-NEXT: autda x16, x17 +; UNCHECKED-NEXT: ldrsw x17, [x16, #0]! +; UNCHECKED-NEXT: add x16, x16, x17 +; UNCHECKED-NEXT: mov x17, #29199 +; UNCHECKED-NEXT: pacia x16, x17 +; UNCHECKED-NEXT: ret +; +; CHECKED-LABEL: test_intrinsic_glue_chain_correctly_setup: +; CHECKED: %bb.0: +; CHECKED-NEXT: str x2, [x0] +; CHECKED-NEXT: mov x16, x1 +; CHECKED-NEXT: mov x17, #29199 +; CHECKED-NEXT: autda x16, x17 +; CHECKED-NEXT: mov x17, x16 +; CHECKED-NEXT: xpacd x17 +; CHECKED-NEXT: cmp x16, x17 +; CHECKED-NEXT: b.eq [[L]]auth_success_9 +; CHECKED-NEXT: mov x16, x17 +; CHECKED-NEXT: b [[L]]resign_end_9 +; CHECKED-NEXT: Lauth_success_9: +; CHECKED-NEXT: ldrsw x17, [x16, #0]! +; CHECKED-NEXT: add x16, x16, x17 +; CHECKED-NEXT: mov x17, #29199 +; CHECKED-NEXT: pacia x16, x17 +; CHECKED-NEXT: Lresign_end_9: +; CHECKED-NEXT: ret +; +; TRAP-LABEL: test_intrinsic_glue_chain_correctly_setup: +; TRAP: %bb.0: +; TRAP-NEXT: str x2, [x0] +; TRAP-NEXT: mov x16, x1 +; TRAP-NEXT: mov x17, #29199 +; TRAP-NEXT: autda x16, x17 +; TRAP-NEXT: mov x17, x16 +; TRAP-NEXT: xpacd x17 +; TRAP-NEXT: cmp x16, x17 +; TRAP-NEXT: b.eq [[L]]auth_success_9 +; TRAP-NEXT: brk #0xc472 +; TRAP-NEXT: Lauth_success_9: +; TRAP-NEXT: ldrsw x17, [x16, #0]! +; TRAP-NEXT: add x16, x16, x17 +; TRAP-NEXT: mov x17, #29199 +; TRAP-NEXT: pacia x16, x17 +; TRAP-NEXT: ret + store ptr %2, ptr %0, align 8 + %15 = tail call i64 @llvm.ptrauth.resign.load.relative(i64 %1, i32 2, i64 29199, i32 0, i64 29199, i64 0) + ret void +} +declare i64 @llvm.ptrauth.auth(i64, i32, i64) +declare i64 @llvm.ptrauth.resign(i64, i32, i64, i32, i64) +declare i64 @llvm.ptrauth.resign.load.relative(i64,i32,i64,i32,i64,i64) diff --git a/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll b/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll index e2aea6df78250..a56921d008712 100644 --- a/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll +++ b/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-auth-resign-with-blend.ll @@ -29,6 +29,11 @@ ; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -global-isel -global-isel-abort=1 -verify-machineinstrs \ ; RUN: -aarch64-ptrauth-auth-checks=trap | FileCheck %s -DL=".L" --check-prefixes=TRAP,TRAP-ELF +; Make sure codegen at -O0 does not crash: +; +; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -O0 -verify-machineinstrs -global-isel=0 +; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -O0 -verify-machineinstrs -global-isel=1 -global-isel-abort=1 + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" define i64 @test_auth_blend(i64 %arg, i64 %arg1) { @@ -299,6 +304,28 @@ define i64 @test_auth_too_large_discriminator(i64 %arg, i64 %arg1) { ret i64 %tmp1 } +; Without "@earlyclobber $Scratch" constraint on AUTxMxN pseudo, the following +; instruction was fed to AArch64AsmPrinter at -O0 +; +; renamable $x8, dead renamable $x9 = AUTxMxN renamable $x8(tied-def 0), 0, 1, renamable $x9, implicit-def dead $nzcv +; +; resulting in an assertion: +; +; Assertion `ScratchReg != AddrDisc && "Forbidden to clobber AddrDisc, but have to" +; +define i64 @autxmxn_scratch_is_earlyclobber(i64 %ptr, i64 %arg) { +entry: + %discr = call i64 @llvm.ptrauth.blend(i64 %arg, i64 1) + br label %some.bb + +some.bb: + %authed = call i64 @llvm.ptrauth.auth(i64 %ptr, i32 0, i64 %discr) + br label %some.other.bb + +some.other.bb: + ret i64 %authed +} + declare i64 @llvm.ptrauth.auth(i64, i32, i64) declare i64 @llvm.ptrauth.resign(i64, i32, i64, i32, i64) declare i64 @llvm.ptrauth.blend(i64, i64) diff --git a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll index 7011b946aad74..91e8be706ba38 100644 --- a/llvm/test/CodeGen/AArch64/ptrauth-isel.ll +++ b/llvm/test/CodeGen/AArch64/ptrauth-isel.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -stop-after=finalize-isel -global-isel=0 \ -; RUN: | FileCheck %s --check-prefixes=DAGISEL +; RUN: | FileCheck %s --check-prefixes=DAGISEL,DAGISEL-DARWIN ; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -stop-after=finalize-isel -global-isel=1 -global-isel-abort=1 \ -; RUN: | FileCheck %s --check-prefixes=GISEL +; RUN: | FileCheck %s --check-prefixes=GISEL,GISEL-DARWIN ; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -verify-machineinstrs -stop-after=finalize-isel -global-isel=0 \ -; RUN: | FileCheck %s --check-prefixes=DAGISEL +; RUN: | FileCheck %s --check-prefixes=DAGISEL,DAGISEL-GNU ; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+pauth -verify-machineinstrs -stop-after=finalize-isel -global-isel=1 -global-isel-abort=1 \ -; RUN: | FileCheck %s --check-prefixes=GISEL +; RUN: | FileCheck %s --check-prefixes=GISEL,GISEL-GNU ; Check MIR produced by the instruction selector to validate properties that ; cannot be reliably tested by only inspecting the final asm output. @@ -29,7 +29,7 @@ define i64 @small_imm_disc_optimized(i64 %addr) { ; DAGISEL-NEXT: {{ $}} ; DAGISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; DAGISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; DAGISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, killed $noreg, implicit-def dead $x16, implicit-def dead $x17 ; DAGISEL-NEXT: $x0 = COPY [[PAC]] ; DAGISEL-NEXT: RET_ReallyLR implicit $x0 @@ -40,7 +40,7 @@ define i64 @small_imm_disc_optimized(i64 %addr) { ; GISEL-NEXT: {{ $}} ; GISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; GISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; GISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; GISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; GISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, $noreg, implicit-def dead $x16, implicit-def dead $x17 ; GISEL-NEXT: $x0 = COPY [[PAC]] ; GISEL-NEXT: RET_ReallyLR implicit $x0 @@ -58,7 +58,7 @@ define i64 @small_imm_disc_non_optimized(i64 %addr) noinline optnone { ; DAGISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; DAGISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY killed [[COPY]] ; DAGISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; DAGISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY1]], 2, 42, killed $noreg, implicit-def dead $x16, implicit-def dead $x17 ; DAGISEL-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[PAC]] ; DAGISEL-NEXT: $x0 = COPY [[COPY2]] @@ -85,7 +85,7 @@ define i64 @large_imm_disc_wreg(i64 %addr) { ; DAGISEL-NEXT: {{ $}} ; DAGISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; DAGISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 12345678 - ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; DAGISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; DAGISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 0, killed [[SUBREG_TO_REG]], implicit-def dead $x16, implicit-def dead $x17 ; DAGISEL-NEXT: $x0 = COPY [[PAC]] ; DAGISEL-NEXT: RET_ReallyLR implicit $x0 @@ -96,7 +96,7 @@ define i64 @large_imm_disc_wreg(i64 %addr) { ; GISEL-NEXT: {{ $}} ; GISEL-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; GISEL-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 12345678 - ; GISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 + ; GISEL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG [[MOVi32imm]], %subreg.sub_32 ; GISEL-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 0, [[SUBREG_TO_REG]], implicit-def dead $x16, implicit-def dead $x17 ; GISEL-NEXT: $x0 = COPY [[PAC]] ; GISEL-NEXT: RET_ReallyLR implicit $x0 @@ -267,3 +267,56 @@ exit: %signed = call i64 @llvm.ptrauth.sign(i64 %addr, i32 2, i64 %disc) ret i64 %signed } + +; On non-Darwin platforms, AUTxMxN allows allocating arbitrary scratch registers. +; To simplify expansion of AUTxMxN in AArch64AsmPrinter, $Scratch operand +; should be marked as @earlyclobber, which is checked by this test case. +define i64 @autxmxn_earlyclobbered_scratch(i64 %addr, i64 %disc) { + ; DAGISEL-DARWIN-LABEL: name: autxmxn_earlyclobbered_scratch + ; DAGISEL-DARWIN: bb.0.entry: + ; DAGISEL-DARWIN-NEXT: liveins: $x0, $x1 + ; DAGISEL-DARWIN-NEXT: {{ $}} + ; DAGISEL-DARWIN-NEXT: [[COPY:%[0-9]+]]:gpr64noip = COPY $x1 + ; DAGISEL-DARWIN-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0 + ; DAGISEL-DARWIN-NEXT: $x16 = COPY [[COPY1]] + ; DAGISEL-DARWIN-NEXT: AUTx16x17 2, 0, [[COPY]], implicit-def $x16, implicit-def dead $x17, implicit-def dead $nzcv, implicit $x16 + ; DAGISEL-DARWIN-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x16 + ; DAGISEL-DARWIN-NEXT: $x0 = COPY [[COPY2]] + ; DAGISEL-DARWIN-NEXT: RET_ReallyLR implicit $x0 + ; + ; GISEL-DARWIN-LABEL: name: autxmxn_earlyclobbered_scratch + ; GISEL-DARWIN: bb.1.entry: + ; GISEL-DARWIN-NEXT: liveins: $x0, $x1 + ; GISEL-DARWIN-NEXT: {{ $}} + ; GISEL-DARWIN-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x0 + ; GISEL-DARWIN-NEXT: [[COPY1:%[0-9]+]]:gpr64noip = COPY $x1 + ; GISEL-DARWIN-NEXT: $x16 = COPY [[COPY]] + ; GISEL-DARWIN-NEXT: $x17 = IMPLICIT_DEF + ; GISEL-DARWIN-NEXT: AUTx16x17 2, 0, [[COPY1]], implicit-def $x16, implicit-def $x17, implicit-def dead $nzcv, implicit $x16 + ; GISEL-DARWIN-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x16 + ; GISEL-DARWIN-NEXT: $x0 = COPY [[COPY2]] + ; GISEL-DARWIN-NEXT: RET_ReallyLR implicit $x0 + ; + ; DAGISEL-GNU-LABEL: name: autxmxn_earlyclobbered_scratch + ; DAGISEL-GNU: bb.0.entry: + ; DAGISEL-GNU-NEXT: liveins: $x0, $x1 + ; DAGISEL-GNU-NEXT: {{ $}} + ; DAGISEL-GNU-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1 + ; DAGISEL-GNU-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0 + ; DAGISEL-GNU-NEXT: %2:gpr64, early-clobber %3:gpr64common = AUTxMxN [[COPY1]], 2, 0, [[COPY]], implicit-def dead $nzcv + ; DAGISEL-GNU-NEXT: $x0 = COPY %2 + ; DAGISEL-GNU-NEXT: RET_ReallyLR implicit $x0 + ; + ; GISEL-GNU-LABEL: name: autxmxn_earlyclobbered_scratch + ; GISEL-GNU: bb.1.entry: + ; GISEL-GNU-NEXT: liveins: $x0, $x1 + ; GISEL-GNU-NEXT: {{ $}} + ; GISEL-GNU-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; GISEL-GNU-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 + ; GISEL-GNU-NEXT: %2:gpr64, early-clobber %3:gpr64common = AUTxMxN [[COPY]], 2, 0, [[COPY1]], implicit-def dead $nzcv + ; GISEL-GNU-NEXT: $x0 = COPY %2 + ; GISEL-GNU-NEXT: RET_ReallyLR implicit $x0 +entry: + %auted = call i64 @llvm.ptrauth.auth(i64 %addr, i32 2, i64 %disc) + ret i64 %auted +} diff --git a/llvm/test/CodeGen/AArch64/ptrauth-isel.mir b/llvm/test/CodeGen/AArch64/ptrauth-isel.mir index 1a155887059e3..659910b27a941 100644 --- a/llvm/test/CodeGen/AArch64/ptrauth-isel.mir +++ b/llvm/test/CodeGen/AArch64/ptrauth-isel.mir @@ -169,13 +169,13 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42 - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 42, killed $noreg, implicit-def dead $x16, implicit-def dead $x17 ; CHECK-NEXT: $x0 = COPY [[PAC]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr64 = COPY $x0 %1:gpr32 = MOVi32imm 42 - %2:gpr64noip = SUBREG_TO_REG 0, killed %1, %subreg.sub_32 + %2:gpr64noip = SUBREG_TO_REG killed %1, %subreg.sub_32 %3:gpr64 = PAC %0, 2, 0, killed %2, implicit-def dead $x16, implicit-def dead $x17 $x0 = COPY %3 RET_ReallyLR implicit $x0 @@ -192,13 +192,13 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm target-flags(aarch64-pageoff, aarch64-nc) @globalvar - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG 0, killed [[MOVi32imm]], %subreg.sub_32 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64noip = SUBREG_TO_REG killed [[MOVi32imm]], %subreg.sub_32 ; CHECK-NEXT: [[PAC:%[0-9]+]]:gpr64 = PAC [[COPY]], 2, 0, killed [[SUBREG_TO_REG]], implicit-def dead $x16, implicit-def dead $x17 ; CHECK-NEXT: $x0 = COPY [[PAC]] ; CHECK-NEXT: RET_ReallyLR implicit $x0 %0:gpr64 = COPY $x0 %1:gpr32 = MOVi32imm target-flags(aarch64-pageoff, aarch64-nc) @globalvar - %2:gpr64noip = SUBREG_TO_REG 0, killed %1, %subreg.sub_32 + %2:gpr64noip = SUBREG_TO_REG killed %1, %subreg.sub_32 %3:gpr64 = PAC %0, 2, 0, killed %2, implicit-def dead $x16, implicit-def dead $x17 $x0 = COPY %3 RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/ragreedy-csr2.ll b/llvm/test/CodeGen/AArch64/ragreedy-csr2.ll new file mode 100644 index 0000000000000..2d5f5dbbf8f07 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/ragreedy-csr2.ll @@ -0,0 +1,130 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -regalloc-csr-cost-scale=80 | FileCheck %s + +target triple = "aarch64" + +; In cold basic blocks we should spill a register instead of using callee saved +; register. + +@Func = external global ptr + +define void @foo(ptr %param) #0 { +; CHECK-LABEL: foo: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: cbz x8, .LBB0_4 +; CHECK-NEXT: // %bb.1: // %if.end +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: stp x29, x30, [sp, #16] // 16-byte Folded Spill +; CHECK-NEXT: add x29, sp, #16 +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_remember_state +; CHECK-NEXT: ldr w1, [x0, #8] +; CHECK-NEXT: cbnz w1, .LBB0_5 +; CHECK-NEXT: // %bb.2: // %if.end6 +; CHECK-NEXT: ldr w8, [x0, #12] +; CHECK-NEXT: cbnz w8, .LBB0_6 +; CHECK-NEXT: .LBB0_3: // %if.end24 +; CHECK-NEXT: ldrb w8, [x0, #16] +; CHECK-NEXT: .cfi_def_cfa wsp, 32 +; CHECK-NEXT: ldp x29, x30, [sp, #16] // 16-byte Folded Reload +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 0 +; CHECK-NEXT: .cfi_restore w30 +; CHECK-NEXT: .cfi_restore w29 +; CHECK-NEXT: tbnz w8, #0, .LBB0_8 +; CHECK-NEXT: .LBB0_4: // %common.ret +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB0_5: // %cold1 +; CHECK-NEXT: .cfi_restore_state +; CHECK-NEXT: str x0, [sp, #8] // 8-byte Spill +; CHECK-NEXT: mov x0, x8 +; CHECK-NEXT: bl fuzz +; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Reload +; CHECK-NEXT: ldr w8, [x0, #12] +; CHECK-NEXT: cbz w8, .LBB0_3 +; CHECK-NEXT: .LBB0_6: // %cold2 +; CHECK-NEXT: adrp x8, :got:Func +; CHECK-NEXT: ldr x8, [x8, :got_lo12:Func] +; CHECK-NEXT: str x0, [sp, #8] // 8-byte Spill +; CHECK-NEXT: ldr x8, [x8] +; CHECK-NEXT: blr x8 +; CHECK-NEXT: mov w8, w0 +; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Reload +; CHECK-NEXT: tbz w8, #0, .LBB0_3 +; CHECK-NEXT: // %bb.7: // %cold3 +; CHECK-NEXT: ldr x8, [x0] +; CHECK-NEXT: ldr w1, [x0, #12] +; CHECK-NEXT: mov x0, x8 +; CHECK-NEXT: bl bar +; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Reload +; CHECK-NEXT: b .LBB0_3 +; CHECK-NEXT: .LBB0_8: // %if.then35 +; CHECK-NEXT: .cfi_def_cfa wsp, 0 +; CHECK-NEXT: .cfi_same_value w30 +; CHECK-NEXT: .cfi_same_value w29 +; CHECK-NEXT: ldr x0, [x0] +; CHECK-NEXT: b bob +entry: + %load0 = load ptr, ptr %param, align 8 + %cmp = icmp eq ptr %load0, null + br i1 %cmp, label %return, label %if.end + +if.end: ; preds = %entry + %b = getelementptr inbounds nuw i8, ptr %param, i64 8 + %load1 = load i32, ptr %b, align 8 + %cmp1.not = icmp eq i32 %load1, 0 + br i1 %cmp1.not, label %if.end6, label %cold1, !prof !12 + +cold1: ; preds = %if.end + %call = tail call i64 @fuzz(ptr %load0, i32 %load1) + br label %if.end6 + +if.end6: ; preds = %cold1, %if.end + %c = getelementptr inbounds nuw i8, ptr %param, i64 12 + %load2 = load i32, ptr %c, align 4 + %cmp7.not = icmp eq i32 %load2, 0 + br i1 %cmp7.not, label %if.end24, label %cold2, !prof !12 + +cold2: ; preds = %if.end6 + %func = load ptr, ptr @Func, align 8 + %call17 = tail call i1 %func() + br i1 %call17, label %cold3, label %if.end24 + +cold3: ; preds = %cold2 + %load4 = load ptr, ptr %param, align 8 + %sunkaddr = getelementptr inbounds i8, ptr %param, i64 12 + %load5 = load i32, ptr %sunkaddr, align 4 + %conv21 = trunc i32 %load5 to i16 + %call22 = tail call i64 @bar(ptr %load4, i16 %conv21) + br label %if.end24 + +if.end24: ; preds = %cold2, %cold3, %if.end6 + %d = getelementptr inbounds nuw i8, ptr %param, i64 16 + %bf.load = load i8, ptr %d, align 8 + %zext = zext i8 %bf.load to i32 + %bf.clear = and i32 %zext, 1 + %cmp26.not = icmp eq i32 %bf.clear, 0 + br i1 %cmp26.not, label %return, label %if.then35, !prof !12 + +if.then35: ; preds = %if.end24 + %load6 = load ptr, ptr %param, align 8 + tail call void @bob(ptr %load6) + ret void + +return: ; preds = %if.end24, %entry + ret void +} + +declare i64 @fuzz(ptr, i32) + +declare i64 @bar(ptr, i16) + +declare void @bob(ptr) + +attributes #0 = { uwtable "frame-pointer"="non-leaf-no-reserve" } + +!12 = !{!"branch_weights", !"expected", i32 2000, i32 1} diff --git a/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir b/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir index 37540dde048fa..2ec7ec94e2ebb 100644 --- a/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir +++ b/llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir @@ -27,7 +27,7 @@ body: | ; CHECK-NOT: %3:gpr32 = ORRWrs $wzr, %2, 0 ; The ORRWrs should be removed. %3:gpr32 = ORRWrs $wzr, %2, 0 - %4:gpr64 = SUBREG_TO_REG 0, %3, %subreg.sub_32 + %4:gpr64 = SUBREG_TO_REG %3, %subreg.sub_32 B %bb.3 bb.3: @@ -60,7 +60,7 @@ body: | ; CHECK: %2:gpr32 = ORRWrs $wzr, %1, 0 ; The ORRWrs should not be removed. %2:gpr32 = ORRWrs $wzr, %1, 0 - %3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32 + %3:gpr64 = SUBREG_TO_REG %2, %subreg.sub_32 B %bb.3 bb.3: diff --git a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir index 08fc47d9480ce..2861933350d2e 100644 --- a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir +++ b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir @@ -29,7 +29,7 @@ body: | %1:gpr64sp = ADDXri %stack.0, 0, 0 %2:gpr64common = nuw ADDXri killed %1, 64, 0 %3:gpr32 = MOVi32imm 64 - %4:gpr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32 + %4:gpr64 = SUBREG_TO_REG killed %3, %subreg.sub_32 %6:gpr64 = COPY %4 %5:gpr64common = COPY killed %2 dead %5:gpr64common, dead early-clobber %6:gpr64 = MOPSMemorySetPseudo %5, %6, %4, implicit-def dead $nzcv @@ -57,7 +57,7 @@ body: | bb.1: bb.2: - %3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %3:gpr64all = SUBREG_TO_REG %0, %subreg.sub_32 bb.3: $nzcv = IMPLICIT_DEF @@ -69,7 +69,7 @@ body: | Bcc 1, %bb.6, implicit killed $nzcv bb.5: - %5:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %5:gpr64all = SUBREG_TO_REG %0, %subreg.sub_32 %4:gpr64 = COPY killed %5 B %bb.7 @@ -103,7 +103,7 @@ body: | bb.1: bb.2: - %3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %3:gpr64all = SUBREG_TO_REG %0, %subreg.sub_32 bb.3: $nzcv = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir b/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir index 1303776230f1a..be99e5b46a10a 100644 --- a/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir +++ b/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir @@ -92,7 +92,7 @@ body: | %1:gpr64common = COPY $x0 %3:gpr32common = ADDWri %2, 1, 0 %4:gpr32 = ORRWrs $wzr, killed %3, 0 - %0:gpr64 = SUBREG_TO_REG 0, killed %4, %subreg.sub_32 + %0:gpr64 = SUBREG_TO_REG killed %4, %subreg.sub_32 bb.1.A: successors: %bb.2(0x30000000), %bb.1(0x50000000) diff --git a/llvm/test/CodeGen/AArch64/sme-agnostic-za.ll b/llvm/test/CodeGen/AArch64/sme-agnostic-za.ll index 0ee410d18bb3c..7a89879625632 100644 --- a/llvm/test/CodeGen/AArch64/sme-agnostic-za.ll +++ b/llvm/test/CodeGen/AArch64/sme-agnostic-za.ll @@ -352,61 +352,33 @@ define i64 @test_many_callee_arguments( } define void @agnostic_za_buffer_alloc_with_stack_probes() nounwind "aarch64_za_state_agnostic" "probe-stack"="inline-asm" "stack-probe-size"="65536"{ -; CHECK-SDAG-LABEL: agnostic_za_buffer_alloc_with_stack_probes: -; CHECK-SDAG: // %bb.0: -; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill -; CHECK-SDAG-NEXT: str x19, [sp, #16] // 8-byte Spill -; CHECK-SDAG-NEXT: mov x29, sp -; CHECK-SDAG-NEXT: bl __arm_sme_state_size -; CHECK-SDAG-NEXT: mov x8, sp -; CHECK-SDAG-NEXT: sub x19, x8, x0 -; CHECK-SDAG-NEXT: .LBB7_1: // =>This Inner Loop Header: Depth=1 -; CHECK-SDAG-NEXT: sub sp, sp, #16, lsl #12 // =65536 -; CHECK-SDAG-NEXT: cmp sp, x19 -; CHECK-SDAG-NEXT: b.le .LBB7_3 -; CHECK-SDAG-NEXT: // %bb.2: // in Loop: Header=BB7_1 Depth=1 -; CHECK-SDAG-NEXT: ldr xzr, [sp] -; CHECK-SDAG-NEXT: b .LBB7_1 -; CHECK-SDAG-NEXT: .LBB7_3: -; CHECK-SDAG-NEXT: mov sp, x19 -; CHECK-SDAG-NEXT: ldr xzr, [sp] -; CHECK-SDAG-NEXT: mov x0, x19 -; CHECK-SDAG-NEXT: bl __arm_sme_save -; CHECK-SDAG-NEXT: bl private_za -; CHECK-SDAG-NEXT: mov x0, x19 -; CHECK-SDAG-NEXT: bl __arm_sme_restore -; CHECK-SDAG-NEXT: mov sp, x29 -; CHECK-SDAG-NEXT: ldr x19, [sp, #16] // 8-byte Reload -; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload -; CHECK-SDAG-NEXT: ret -; -; CHECK-LABEL: agnostic_za_buffer_alloc_with_stack_probes: -; CHECK: // %bb.0: -; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill -; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill -; CHECK-NEXT: mov x29, sp -; CHECK-NEXT: bl __arm_sme_state_size -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: sub x19, x8, x0 -; CHECK-NEXT: mov x0, x19 -; CHECK-NEXT: bl __arm_sme_save -; CHECK-NEXT: .LBB7_1: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 -; CHECK-NEXT: cmp sp, x19 -; CHECK-NEXT: b.le .LBB7_3 -; CHECK-NEXT: // %bb.2: // in Loop: Header=BB7_1 Depth=1 -; CHECK-NEXT: ldr xzr, [sp] -; CHECK-NEXT: b .LBB7_1 -; CHECK-NEXT: .LBB7_3: -; CHECK-NEXT: mov sp, x19 -; CHECK-NEXT: ldr xzr, [sp] -; CHECK-NEXT: bl private_za -; CHECK-NEXT: mov x0, x19 -; CHECK-NEXT: bl __arm_sme_restore -; CHECK-NEXT: mov sp, x29 -; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload -; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload -; CHECK-NEXT: ret +; CHECK-COMMON-LABEL: agnostic_za_buffer_alloc_with_stack_probes: +; CHECK-COMMON: // %bb.0: +; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill +; CHECK-COMMON-NEXT: str x19, [sp, #16] // 8-byte Spill +; CHECK-COMMON-NEXT: mov x29, sp +; CHECK-COMMON-NEXT: bl __arm_sme_state_size +; CHECK-COMMON-NEXT: mov x8, sp +; CHECK-COMMON-NEXT: sub x19, x8, x0 +; CHECK-COMMON-NEXT: .LBB7_1: // =>This Inner Loop Header: Depth=1 +; CHECK-COMMON-NEXT: sub sp, sp, #16, lsl #12 // =65536 +; CHECK-COMMON-NEXT: cmp sp, x19 +; CHECK-COMMON-NEXT: b.le .LBB7_3 +; CHECK-COMMON-NEXT: // %bb.2: // in Loop: Header=BB7_1 Depth=1 +; CHECK-COMMON-NEXT: ldr xzr, [sp] +; CHECK-COMMON-NEXT: b .LBB7_1 +; CHECK-COMMON-NEXT: .LBB7_3: +; CHECK-COMMON-NEXT: mov sp, x19 +; CHECK-COMMON-NEXT: ldr xzr, [sp] +; CHECK-COMMON-NEXT: mov x0, x19 +; CHECK-COMMON-NEXT: bl __arm_sme_save +; CHECK-COMMON-NEXT: bl private_za +; CHECK-COMMON-NEXT: mov x0, x19 +; CHECK-COMMON-NEXT: bl __arm_sme_restore +; CHECK-COMMON-NEXT: mov sp, x29 +; CHECK-COMMON-NEXT: ldr x19, [sp, #16] // 8-byte Reload +; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload +; CHECK-COMMON-NEXT: ret call void @private_za() ret void } diff --git a/llvm/test/CodeGen/AArch64/sme-new-za-function.ll b/llvm/test/CodeGen/AArch64/sme-new-za-function.ll index d2715b58439d8..6995cfae8e459 100644 --- a/llvm/test/CodeGen/AArch64/sme-new-za-function.ll +++ b/llvm/test/CodeGen/AArch64/sme-new-za-function.ll @@ -51,7 +51,6 @@ define void @private_za() "aarch64_new_za" { } ; Note: This test must run at -O0 as otherwise the multiple exits are optimized out. -; TODO: We should be able to omit the ZA save here (as this function does not use ZA). define i32 @private_za_multiple_exit(i32 %a, i32 %b, i64 %cond) "aarch64_new_za" { ; CHECK-SDAG-LABEL: private_za_multiple_exit: ; CHECK-SDAG: // %bb.0: // %prelude @@ -99,33 +98,21 @@ define i32 @private_za_multiple_exit(i32 %a, i32 %b, i64 %cond) "aarch64_new_za" ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mrs x8, TPIDR2_EL0 -; CHECK-NEXT: cbnz x8, .LBB1_1 -; CHECK-NEXT: b .LBB1_2 -; CHECK-NEXT: .LBB1_1: // %entry -; CHECK-NEXT: bl __arm_tpidr2_save -; CHECK-NEXT: msr TPIDR2_EL0, xzr -; CHECK-NEXT: zero {za} -; CHECK-NEXT: b .LBB1_2 -; CHECK-NEXT: .LBB1_2: // %entry -; CHECK-NEXT: smstart za ; CHECK-NEXT: str w1, [sp, #8] // 4-byte Spill ; CHECK-NEXT: str w0, [sp, #12] // 4-byte Spill ; CHECK-NEXT: subs x8, x2, #1 -; CHECK-NEXT: b.ne .LBB1_4 -; CHECK-NEXT: b .LBB1_3 -; CHECK-NEXT: .LBB1_3: // %if.else +; CHECK-NEXT: b.ne .LBB1_2 +; CHECK-NEXT: b .LBB1_1 +; CHECK-NEXT: .LBB1_1: // %if.else ; CHECK-NEXT: ldr w8, [sp, #12] // 4-byte Reload ; CHECK-NEXT: ldr w9, [sp, #8] // 4-byte Reload ; CHECK-NEXT: add w0, w8, w9 -; CHECK-NEXT: smstop za ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB1_4: // %if.end +; CHECK-NEXT: .LBB1_2: // %if.end ; CHECK-NEXT: ldr w8, [sp, #12] // 4-byte Reload ; CHECK-NEXT: ldr w9, [sp, #8] // 4-byte Reload ; CHECK-NEXT: subs w0, w8, w9 -; CHECK-NEXT: smstop za ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll b/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll index 50449172ce85b..aae1d3b756f4e 100644 --- a/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll +++ b/llvm/test/CodeGen/AArch64/sme-za-control-flow.ll @@ -49,36 +49,40 @@ define void @private_za_loop(i32 %n) "aarch64_inout_za" nounwind { ; CHECK-LABEL: private_za_loop: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill -; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill +; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: mov x29, sp ; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: rdsvl x8, #1 ; CHECK-NEXT: mov x9, sp ; CHECK-NEXT: msub x9, x8, x8, x9 ; CHECK-NEXT: mov sp, x9 -; CHECK-NEXT: sub x10, x29, #16 ; CHECK-NEXT: cmp w0, #1 ; CHECK-NEXT: stp x9, x8, [x29, #-16] -; CHECK-NEXT: msr TPIDR2_EL0, x10 -; CHECK-NEXT: b.lt .LBB0_3 +; CHECK-NEXT: b.lt .LBB0_5 ; CHECK-NEXT: // %bb.1: // %loop.preheader ; CHECK-NEXT: mov w19, w0 +; CHECK-NEXT: sub x20, x29, #16 +; CHECK-NEXT: b .LBB0_3 ; CHECK-NEXT: .LBB0_2: // %loop +; CHECK-NEXT: // in Loop: Header=BB0_3 Depth=1 +; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: cbz w19, .LBB0_5 +; CHECK-NEXT: .LBB0_3: // %loop ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: msr TPIDR2_EL0, x20 ; CHECK-NEXT: bl private_za_call -; CHECK-NEXT: subs w19, w19, #1 -; CHECK-NEXT: b.ne .LBB0_2 -; CHECK-NEXT: .LBB0_3: // %exit +; CHECK-NEXT: sub w19, w19, #1 ; CHECK-NEXT: smstart za ; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: sub x0, x29, #16 -; CHECK-NEXT: cbnz x8, .LBB0_5 -; CHECK-NEXT: // %bb.4: // %exit +; CHECK-NEXT: cbnz x8, .LBB0_2 +; CHECK-NEXT: // %bb.4: // %loop +; CHECK-NEXT: // in Loop: Header=BB0_3 Depth=1 ; CHECK-NEXT: bl __arm_tpidr2_restore +; CHECK-NEXT: b .LBB0_2 ; CHECK-NEXT: .LBB0_5: // %exit -; CHECK-NEXT: msr TPIDR2_EL0, xzr ; CHECK-NEXT: mov sp, x29 -; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload +; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll b/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll index 5243b8d7203d8..19ea1e47f84ff 100644 --- a/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll +++ b/llvm/test/CodeGen/AArch64/sme-za-exceptions.ll @@ -63,17 +63,25 @@ define void @za_with_raii(i1 %fail) "aarch64_inout_za" personality ptr @__gxx_pe ; CHECK-NEXT: ldr x1, [x1, :got_lo12:typeinfo_for_char_const_ptr] ; CHECK-NEXT: bl __cxa_throw ; CHECK-NEXT: .Ltmp1: // EH_LABEL -; CHECK-NEXT: // %bb.3: // %throw_fail -; CHECK-NEXT: .LBB0_4: // %unwind_dtors +; CHECK-NEXT: smstart za +; CHECK-NEXT: mrs x8, TPIDR2_EL0 +; CHECK-NEXT: sub x0, x29, #16 +; CHECK-NEXT: cbnz x8, .LBB0_4 +; CHECK-NEXT: // %bb.3: // %throw_exception +; CHECK-NEXT: bl __arm_tpidr2_restore +; CHECK-NEXT: .LBB0_4: // %throw_exception +; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: // %bb.5: // %throw_fail +; CHECK-NEXT: .LBB0_6: // %unwind_dtors ; CHECK-NEXT: .Ltmp2: // EH_LABEL ; CHECK-NEXT: mov x19, x0 ; CHECK-NEXT: smstart za ; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: sub x0, x29, #16 -; CHECK-NEXT: cbnz x8, .LBB0_6 -; CHECK-NEXT: // %bb.5: // %unwind_dtors +; CHECK-NEXT: cbnz x8, .LBB0_8 +; CHECK-NEXT: // %bb.7: // %unwind_dtors ; CHECK-NEXT: bl __arm_tpidr2_restore -; CHECK-NEXT: .LBB0_6: // %unwind_dtors +; CHECK-NEXT: .LBB0_8: // %unwind_dtors ; CHECK-NEXT: msr TPIDR2_EL0, xzr ; CHECK-NEXT: bl shared_za_call ; CHECK-NEXT: sub x8, x29, #16 @@ -224,15 +232,15 @@ define void @try_catch() "aarch64_inout_za" personality ptr @__gxx_personality_v ; CHECK-NEXT: msr TPIDR2_EL0, x8 ; CHECK-NEXT: bl may_throw ; CHECK-NEXT: .Ltmp4: // EH_LABEL -; CHECK-NEXT: .LBB1_1: // %after_catch ; CHECK-NEXT: smstart za ; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: sub x0, x29, #16 -; CHECK-NEXT: cbnz x8, .LBB1_3 -; CHECK-NEXT: // %bb.2: // %after_catch +; CHECK-NEXT: cbnz x8, .LBB1_2 +; CHECK-NEXT: // %bb.1: ; CHECK-NEXT: bl __arm_tpidr2_restore -; CHECK-NEXT: .LBB1_3: // %after_catch +; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: .LBB1_3: // %after_catch ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: b shared_za_call @@ -251,7 +259,15 @@ define void @try_catch() "aarch64_inout_za" personality ptr @__gxx_personality_v ; CHECK-NEXT: sub x8, x29, #16 ; CHECK-NEXT: msr TPIDR2_EL0, x8 ; CHECK-NEXT: bl __cxa_end_catch -; CHECK-NEXT: b .LBB1_1 +; CHECK-NEXT: smstart za +; CHECK-NEXT: mrs x8, TPIDR2_EL0 +; CHECK-NEXT: sub x0, x29, #16 +; CHECK-NEXT: cbnz x8, .LBB1_8 +; CHECK-NEXT: // %bb.7: // %catch +; CHECK-NEXT: bl __arm_tpidr2_restore +; CHECK-NEXT: .LBB1_8: // %catch +; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: b .LBB1_3 ; ; CHECK-SDAG-LABEL: try_catch: ; CHECK-SDAG: .Lfunc_begin1: @@ -387,8 +403,8 @@ define void @try_catch_shared_za_callee() "aarch64_new_za" personality ptr @__gx ; CHECK-NEXT: .Ltmp6: // EH_LABEL ; CHECK-NEXT: bl shared_za_call ; CHECK-NEXT: .Ltmp7: // EH_LABEL -; CHECK-NEXT: .LBB2_3: // %exit ; CHECK-NEXT: smstop za +; CHECK-NEXT: .LBB2_3: // %exit ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret @@ -408,6 +424,7 @@ define void @try_catch_shared_za_callee() "aarch64_new_za" personality ptr @__gx ; CHECK-NEXT: msr TPIDR2_EL0, x8 ; CHECK-NEXT: bl __cxa_end_catch ; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: smstop za ; CHECK-NEXT: b .LBB2_3 ; ; CHECK-SDAG-LABEL: try_catch_shared_za_callee: @@ -636,9 +653,9 @@ define void @try_catch_agnostic_za() "aarch64_za_state_agnostic" personality ptr ; CHECK-NEXT: bl __arm_sme_save ; CHECK-NEXT: bl may_throw ; CHECK-NEXT: .Ltmp13: // EH_LABEL -; CHECK-NEXT: .LBB4_1: // %exit ; CHECK-NEXT: mov x0, x19 ; CHECK-NEXT: bl __arm_sme_restore +; CHECK-NEXT: .LBB4_1: // %exit ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload ; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload @@ -647,6 +664,8 @@ define void @try_catch_agnostic_za() "aarch64_za_state_agnostic" personality ptr ; CHECK-NEXT: .Ltmp14: // EH_LABEL ; CHECK-NEXT: bl __cxa_begin_catch ; CHECK-NEXT: bl __cxa_end_catch +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: bl __arm_sme_restore ; CHECK-NEXT: b .LBB4_1 ; ; CHECK-SDAG-LABEL: try_catch_agnostic_za: @@ -746,9 +765,9 @@ define void @try_catch_agnostic_za_invoke() "aarch64_za_state_agnostic" personal ; CHECK-NEXT: bl __arm_sme_save ; CHECK-NEXT: bl agnostic_za_call ; CHECK-NEXT: .Ltmp16: // EH_LABEL -; CHECK-NEXT: .LBB5_1: // %exit ; CHECK-NEXT: mov x0, x19 ; CHECK-NEXT: bl __arm_sme_restore +; CHECK-NEXT: .LBB5_1: // %exit ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload ; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload @@ -757,6 +776,8 @@ define void @try_catch_agnostic_za_invoke() "aarch64_za_state_agnostic" personal ; CHECK-NEXT: .Ltmp17: // EH_LABEL ; CHECK-NEXT: bl __cxa_begin_catch ; CHECK-NEXT: bl __cxa_end_catch +; CHECK-NEXT: mov x0, x19 +; CHECK-NEXT: bl __arm_sme_restore ; CHECK-NEXT: b .LBB5_1 ; ; CHECK-SDAG-LABEL: try_catch_agnostic_za_invoke: @@ -845,15 +866,15 @@ define void @try_catch_inout_za_agnostic_za_callee() "aarch64_inout_za" personal ; CHECK-NEXT: msr TPIDR2_EL0, x8 ; CHECK-NEXT: bl agnostic_za_call ; CHECK-NEXT: .Ltmp19: // EH_LABEL -; CHECK-NEXT: .LBB6_1: // %exit ; CHECK-NEXT: smstart za ; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: sub x0, x29, #16 -; CHECK-NEXT: cbnz x8, .LBB6_3 -; CHECK-NEXT: // %bb.2: // %exit +; CHECK-NEXT: cbnz x8, .LBB6_2 +; CHECK-NEXT: // %bb.1: // %entry ; CHECK-NEXT: bl __arm_tpidr2_restore -; CHECK-NEXT: .LBB6_3: // %exit +; CHECK-NEXT: .LBB6_2: // %entry ; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: .LBB6_3: // %exit ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret @@ -861,7 +882,15 @@ define void @try_catch_inout_za_agnostic_za_callee() "aarch64_inout_za" personal ; CHECK-NEXT: .Ltmp20: // EH_LABEL ; CHECK-NEXT: bl __cxa_begin_catch ; CHECK-NEXT: bl __cxa_end_catch -; CHECK-NEXT: b .LBB6_1 +; CHECK-NEXT: smstart za +; CHECK-NEXT: mrs x8, TPIDR2_EL0 +; CHECK-NEXT: sub x0, x29, #16 +; CHECK-NEXT: cbnz x8, .LBB6_6 +; CHECK-NEXT: // %bb.5: // %catch +; CHECK-NEXT: bl __arm_tpidr2_restore +; CHECK-NEXT: .LBB6_6: // %catch +; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: b .LBB6_3 ; ; CHECK-SDAG-LABEL: try_catch_inout_za_agnostic_za_callee: ; CHECK-SDAG: .Lfunc_begin6: @@ -967,9 +996,9 @@ define void @try_catch_inout_zt0() "aarch64_inout_zt0" personality ptr @__gxx_pe ; CHECK-NEXT: smstop za ; CHECK-NEXT: bl may_throw ; CHECK-NEXT: .Ltmp22: // EH_LABEL -; CHECK-NEXT: .LBB7_1: // %exit ; CHECK-NEXT: smstart za ; CHECK-NEXT: ldr zt0, [x19] +; CHECK-NEXT: .LBB7_1: // %exit ; CHECK-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: add sp, sp, #80 ; CHECK-NEXT: ret @@ -977,6 +1006,8 @@ define void @try_catch_inout_zt0() "aarch64_inout_zt0" personality ptr @__gxx_pe ; CHECK-NEXT: .Ltmp23: // EH_LABEL ; CHECK-NEXT: bl __cxa_begin_catch ; CHECK-NEXT: bl __cxa_end_catch +; CHECK-NEXT: smstart za +; CHECK-NEXT: ldr zt0, [x19] ; CHECK-NEXT: b .LBB7_1 ; ; CHECK-SDAG-LABEL: try_catch_inout_zt0: diff --git a/llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll b/llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll index 44f4ea2ad242b..26fc39e271090 100644 --- a/llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll +++ b/llvm/test/CodeGen/AArch64/sme-za-lazy-save-buffer.ll @@ -1,52 +1,52 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -aarch64-new-sme-abi=false < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK-SDAG -; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s --check-prefixes=CHECK-COMMON,CHECK +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -aarch64-new-sme-abi=false < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s define i32 @no_tpidr2_save_required() "aarch64_inout_za" { -; CHECK-COMMON-LABEL: no_tpidr2_save_required: -; CHECK-COMMON: // %bb.0: // %entry -; CHECK-COMMON-NEXT: mov w0, #42 // =0x2a -; CHECK-COMMON-NEXT: ret +; CHECK-LABEL: no_tpidr2_save_required: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov w0, #42 // =0x2a +; CHECK-NEXT: ret entry: ret i32 42 } define float @multi_bb_stpidr2_save_required(i32 %a, float %b, float %c) "aarch64_inout_za" { -; CHECK-COMMON-LABEL: multi_bb_stpidr2_save_required: -; CHECK-COMMON: // %bb.0: -; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill -; CHECK-COMMON-NEXT: mov x29, sp -; CHECK-COMMON-NEXT: sub sp, sp, #16 -; CHECK-COMMON-NEXT: .cfi_def_cfa w29, 16 -; CHECK-COMMON-NEXT: .cfi_offset w30, -8 -; CHECK-COMMON-NEXT: .cfi_offset w29, -16 -; CHECK-COMMON-NEXT: rdsvl x8, #1 -; CHECK-COMMON-NEXT: mov x9, sp -; CHECK-COMMON-NEXT: msub x9, x8, x8, x9 -; CHECK-COMMON-NEXT: mov sp, x9 -; CHECK-COMMON-NEXT: stp x9, x8, [x29, #-16] -; CHECK-COMMON-NEXT: cbz w0, .LBB1_2 -; CHECK-COMMON-NEXT: // %bb.1: // %use_b -; CHECK-COMMON-NEXT: fmov s1, #4.00000000 -; CHECK-COMMON-NEXT: fadd s0, s0, s1 -; CHECK-COMMON-NEXT: b .LBB1_5 -; CHECK-COMMON-NEXT: .LBB1_2: // %use_c -; CHECK-COMMON-NEXT: fmov s0, s1 -; CHECK-COMMON-NEXT: sub x8, x29, #16 -; CHECK-COMMON-NEXT: msr TPIDR2_EL0, x8 -; CHECK-COMMON-NEXT: bl cosf -; CHECK-COMMON-NEXT: smstart za -; CHECK-COMMON-NEXT: mrs x8, TPIDR2_EL0 -; CHECK-COMMON-NEXT: sub x0, x29, #16 -; CHECK-COMMON-NEXT: cbnz x8, .LBB1_4 -; CHECK-COMMON-NEXT: // %bb.3: // %use_c -; CHECK-COMMON-NEXT: bl __arm_tpidr2_restore -; CHECK-COMMON-NEXT: .LBB1_4: // %use_c -; CHECK-COMMON-NEXT: msr TPIDR2_EL0, xzr -; CHECK-COMMON-NEXT: .LBB1_5: // %exit -; CHECK-COMMON-NEXT: mov sp, x29 -; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload -; CHECK-COMMON-NEXT: ret +; CHECK-LABEL: multi_bb_stpidr2_save_required: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa w29, 16 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: rdsvl x8, #1 +; CHECK-NEXT: mov x9, sp +; CHECK-NEXT: msub x9, x8, x8, x9 +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: stp x9, x8, [x29, #-16] +; CHECK-NEXT: cbz w0, .LBB1_2 +; CHECK-NEXT: // %bb.1: // %use_b +; CHECK-NEXT: fmov s1, #4.00000000 +; CHECK-NEXT: fadd s0, s0, s1 +; CHECK-NEXT: b .LBB1_5 +; CHECK-NEXT: .LBB1_2: // %use_c +; CHECK-NEXT: fmov s0, s1 +; CHECK-NEXT: sub x8, x29, #16 +; CHECK-NEXT: msr TPIDR2_EL0, x8 +; CHECK-NEXT: bl cosf +; CHECK-NEXT: smstart za +; CHECK-NEXT: mrs x8, TPIDR2_EL0 +; CHECK-NEXT: sub x0, x29, #16 +; CHECK-NEXT: cbnz x8, .LBB1_4 +; CHECK-NEXT: // %bb.3: // %use_c +; CHECK-NEXT: bl __arm_tpidr2_restore +; CHECK-NEXT: .LBB1_4: // %use_c +; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: .LBB1_5: // %exit +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-NEXT: ret %cmp = icmp ne i32 %a, 0 br i1 %cmp, label %use_b, label %use_c @@ -64,51 +64,6 @@ exit: } define float @multi_bb_stpidr2_save_required_stackprobe(i32 %a, float %b, float %c) "aarch64_inout_za" "probe-stack"="inline-asm" "stack-probe-size"="65536" { -; CHECK-SDAG-LABEL: multi_bb_stpidr2_save_required_stackprobe: -; CHECK-SDAG: // %bb.0: -; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill -; CHECK-SDAG-NEXT: mov x29, sp -; CHECK-SDAG-NEXT: ldr xzr, [sp, #-16]! -; CHECK-SDAG-NEXT: .cfi_def_cfa w29, 16 -; CHECK-SDAG-NEXT: .cfi_offset w30, -8 -; CHECK-SDAG-NEXT: .cfi_offset w29, -16 -; CHECK-SDAG-NEXT: rdsvl x8, #1 -; CHECK-SDAG-NEXT: mov x9, sp -; CHECK-SDAG-NEXT: msub x9, x8, x8, x9 -; CHECK-SDAG-NEXT: .LBB2_1: // =>This Inner Loop Header: Depth=1 -; CHECK-SDAG-NEXT: sub sp, sp, #16, lsl #12 // =65536 -; CHECK-SDAG-NEXT: cmp sp, x9 -; CHECK-SDAG-NEXT: b.le .LBB2_3 -; CHECK-SDAG-NEXT: // %bb.2: // in Loop: Header=BB2_1 Depth=1 -; CHECK-SDAG-NEXT: ldr xzr, [sp] -; CHECK-SDAG-NEXT: b .LBB2_1 -; CHECK-SDAG-NEXT: .LBB2_3: -; CHECK-SDAG-NEXT: mov sp, x9 -; CHECK-SDAG-NEXT: ldr xzr, [sp] -; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16] -; CHECK-SDAG-NEXT: cbz w0, .LBB2_5 -; CHECK-SDAG-NEXT: // %bb.4: // %use_b -; CHECK-SDAG-NEXT: fmov s1, #4.00000000 -; CHECK-SDAG-NEXT: fadd s0, s0, s1 -; CHECK-SDAG-NEXT: b .LBB2_8 -; CHECK-SDAG-NEXT: .LBB2_5: // %use_c -; CHECK-SDAG-NEXT: fmov s0, s1 -; CHECK-SDAG-NEXT: sub x8, x29, #16 -; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x8 -; CHECK-SDAG-NEXT: bl cosf -; CHECK-SDAG-NEXT: smstart za -; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0 -; CHECK-SDAG-NEXT: sub x0, x29, #16 -; CHECK-SDAG-NEXT: cbnz x8, .LBB2_7 -; CHECK-SDAG-NEXT: // %bb.6: // %use_c -; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore -; CHECK-SDAG-NEXT: .LBB2_7: // %use_c -; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr -; CHECK-SDAG-NEXT: .LBB2_8: // %exit -; CHECK-SDAG-NEXT: mov sp, x29 -; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload -; CHECK-SDAG-NEXT: ret -; ; CHECK-LABEL: multi_bb_stpidr2_save_required_stackprobe: ; CHECK: // %bb.0: ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill @@ -119,9 +74,7 @@ define float @multi_bb_stpidr2_save_required_stackprobe(i32 %a, float %b, float ; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: rdsvl x8, #1 ; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: sub x10, x29, #16 ; CHECK-NEXT: msub x9, x8, x8, x9 -; CHECK-NEXT: msr TPIDR2_EL0, x10 ; CHECK-NEXT: .LBB2_1: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: sub sp, sp, #16, lsl #12 // =65536 ; CHECK-NEXT: cmp sp, x9 @@ -137,19 +90,21 @@ define float @multi_bb_stpidr2_save_required_stackprobe(i32 %a, float %b, float ; CHECK-NEXT: // %bb.4: // %use_b ; CHECK-NEXT: fmov s1, #4.00000000 ; CHECK-NEXT: fadd s0, s0, s1 -; CHECK-NEXT: b .LBB2_6 +; CHECK-NEXT: b .LBB2_8 ; CHECK-NEXT: .LBB2_5: // %use_c ; CHECK-NEXT: fmov s0, s1 +; CHECK-NEXT: sub x8, x29, #16 +; CHECK-NEXT: msr TPIDR2_EL0, x8 ; CHECK-NEXT: bl cosf -; CHECK-NEXT: .LBB2_6: // %exit ; CHECK-NEXT: smstart za ; CHECK-NEXT: mrs x8, TPIDR2_EL0 ; CHECK-NEXT: sub x0, x29, #16 -; CHECK-NEXT: cbnz x8, .LBB2_8 -; CHECK-NEXT: // %bb.7: // %exit +; CHECK-NEXT: cbnz x8, .LBB2_7 +; CHECK-NEXT: // %bb.6: // %use_c ; CHECK-NEXT: bl __arm_tpidr2_restore -; CHECK-NEXT: .LBB2_8: // %exit +; CHECK-NEXT: .LBB2_7: // %use_c ; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: .LBB2_8: // %exit ; CHECK-NEXT: mov sp, x29 ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/AArch64/sme-zt0-state.ll b/llvm/test/CodeGen/AArch64/sme-zt0-state.ll index 24b4565cf24b5..4cbdca7d41aac 100644 --- a/llvm/test/CodeGen/AArch64/sme-zt0-state.ll +++ b/llvm/test/CodeGen/AArch64/sme-zt0-state.ll @@ -453,3 +453,78 @@ define void @disable_tailcallopt(ptr %callee) "aarch64_inout_zt0" nounwind { tail call void %callee() ret void } + +; Expected new lowering (not CHECK-SDAG) +; - Lazy save and spill of ZT0 before first call +; - Restore of ZA before second call +; - Reload of ZT0 after second call +define void @za_zt0_private_za_to_shared_za(ptr %callee) "aarch64_inout_za" "aarch64_inout_zt0" nounwind { +; CHECK-SDAG-LABEL: za_zt0_private_za_to_shared_za: +; CHECK-SDAG: // %bb.0: +; CHECK-SDAG-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill +; CHECK-SDAG-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill +; CHECK-SDAG-NEXT: mov x29, sp +; CHECK-SDAG-NEXT: sub sp, sp, #80 +; CHECK-SDAG-NEXT: rdsvl x8, #1 +; CHECK-SDAG-NEXT: mov x9, sp +; CHECK-SDAG-NEXT: mov x19, x0 +; CHECK-SDAG-NEXT: msub x9, x8, x8, x9 +; CHECK-SDAG-NEXT: mov sp, x9 +; CHECK-SDAG-NEXT: sub x10, x29, #16 +; CHECK-SDAG-NEXT: sub x20, x29, #80 +; CHECK-SDAG-NEXT: stp x9, x8, [x29, #-16] +; CHECK-SDAG-NEXT: msr TPIDR2_EL0, x10 +; CHECK-SDAG-NEXT: str zt0, [x20] +; CHECK-SDAG-NEXT: blr x0 +; CHECK-SDAG-NEXT: smstart za +; CHECK-SDAG-NEXT: ldr zt0, [x20] +; CHECK-SDAG-NEXT: mrs x8, TPIDR2_EL0 +; CHECK-SDAG-NEXT: sub x0, x29, #16 +; CHECK-SDAG-NEXT: cbnz x8, .LBB14_2 +; CHECK-SDAG-NEXT: // %bb.1: +; CHECK-SDAG-NEXT: bl __arm_tpidr2_restore +; CHECK-SDAG-NEXT: .LBB14_2: +; CHECK-SDAG-NEXT: msr TPIDR2_EL0, xzr +; CHECK-SDAG-NEXT: str zt0, [x20] +; CHECK-SDAG-NEXT: blr x19 +; CHECK-SDAG-NEXT: ldr zt0, [x20] +; CHECK-SDAG-NEXT: mov sp, x29 +; CHECK-SDAG-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload +; CHECK-SDAG-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload +; CHECK-SDAG-NEXT: ret +; +; CHECK-LABEL: za_zt0_private_za_to_shared_za: +; CHECK: // %bb.0: +; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill +; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: sub sp, sp, #80 +; CHECK-NEXT: rdsvl x8, #1 +; CHECK-NEXT: mov x9, sp +; CHECK-NEXT: msub x9, x8, x8, x9 +; CHECK-NEXT: mov sp, x9 +; CHECK-NEXT: sub x20, x29, #64 +; CHECK-NEXT: sub x10, x29, #80 +; CHECK-NEXT: mov x19, x0 +; CHECK-NEXT: stp x9, x8, [x29, #-80] +; CHECK-NEXT: str zt0, [x20] +; CHECK-NEXT: msr TPIDR2_EL0, x10 +; CHECK-NEXT: blr x0 +; CHECK-NEXT: smstart za +; CHECK-NEXT: mrs x8, TPIDR2_EL0 +; CHECK-NEXT: sub x0, x29, #80 +; CHECK-NEXT: cbnz x8, .LBB14_2 +; CHECK-NEXT: // %bb.1: +; CHECK-NEXT: bl __arm_tpidr2_restore +; CHECK-NEXT: .LBB14_2: +; CHECK-NEXT: msr TPIDR2_EL0, xzr +; CHECK-NEXT: blr x19 +; CHECK-NEXT: ldr zt0, [x20] +; CHECK-NEXT: mov sp, x29 +; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload +; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload +; CHECK-NEXT: ret + call void %callee() + call void %callee() "aarch64_inout_za"; + ret void; +} diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir index c552da3eca0c8..7f28610a312c5 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir @@ -53,7 +53,7 @@ body: | bb.1.for.body.preheader: %11:gpr32 = ORRWrs $wzr, %9, 0 - %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32 + %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32 %14:fpr32 = FMOVSi 112 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir index 6171abc52bb93..84fe0f6b032dc 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir @@ -53,7 +53,7 @@ body: | bb.1.for.body.preheader: %11:gpr32 = ORRWrs $wzr, %9, 0 - %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32 + %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32 %14:fpr32 = FMOVSi 112 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir index 630a89364c8c9..7a88bb1363d46 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir @@ -59,7 +59,7 @@ body: | bb.1.for.body.preheader: %7:gpr32common = SUBWri %5, 1, 0 %9:gpr64all = IMPLICIT_DEF - %8:gpr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG killed %7, %subreg.sub_32 %10:gpr64 = SBFMXri killed %8, 0, 31 %0:gpr64all = COPY %10 %12:fpr32 = FMOVSi 112 diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir index cb0b1e3028753..1c0e1cc5aa41f 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir @@ -59,7 +59,7 @@ body: | bb.1.for.body.preheader: %7:gpr32common = SUBWri %5, 1, 0 %9:gpr64all = IMPLICIT_DEF - %8:gpr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG killed %7, %subreg.sub_32 %10:gpr64 = SBFMXri killed %8, 0, 31 %0:gpr64all = COPY %10 %12:fpr32 = FMOVSi 112 diff --git a/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir b/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir index c1014b296cad3..3a984f6488700 100644 --- a/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir +++ b/llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir @@ -6,9 +6,9 @@ # CHECK: {{^ *}}Try to schedule with 47 # CHECK: {{^ *}}Inst (11) %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0) # CHECK-EMPTY: -# CHECK-NEXT: {{^ *}}es: ffffffe9 ls: ffffffe9 -# CHECK-NEXT: {{^ *}}Trying to insert node between -23 and -23 II: 47 -# CHECK-NEXT: {{^ *}}failed to insert at cycle -23 %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0) +# CHECK-NEXT: {{^ *}}es: ffffffe8 ls: ffffffe9 +# CHECK-NEXT: {{^ *}}Trying to insert node between -24 and -23 II: 47 +# CHECK-NEXT: {{^ *}}insert at cycle -24 %48:fpr128 = LDRQui %35:gpr64sp, 0 :: (load (s128) from %ir.lsr.iv63, align 4, !tbaa !0) --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" @@ -178,7 +178,7 @@ body: | successors: %bb.12, %bb.2 %48:gpr32 = ORRWrs $wzr, %45, 0 - %0:gpr64 = SUBREG_TO_REG 0, killed %48, %subreg.sub_32 + %0:gpr64 = SUBREG_TO_REG killed %48, %subreg.sub_32 dead $wzr = SUBSWri %45, 8, 0, implicit-def $nzcv Bcc 2, %bb.2, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir index bcc6a3ea9b285..878f7b782a9a1 100644 --- a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir +++ b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir @@ -5,16 +5,19 @@ # floating-point exception, and there is an instruction for barrier event. In # this case the order of them must not change. # -# FIXME: Currently the following dependencies are missed. -# -# Loop carried edges from SU(7) -# Order -# SU(2) -# SU(3) -# SU(4) -# SU(5) +# SU(2): May raise FP exception +# SU(3): May raise FP exception +# SU(4): Store +# SU(5): Barrier +# SU(7): Barrier # CHECK: ===== Loop Carried Edges Begin ===== +# CHECK-NEXT: Loop carried edges from SU(7) +# CHECK-NEXT: Order +# CHECK-NEXT: SU(2) +# CHECK-NEXT: SU(3) +# CHECK-NEXT: SU(4) +# CHECK-NEXT: SU(5) # CHECK-NEXT: ===== Loop Carried Edges End ===== --- | @@ -81,7 +84,7 @@ body: | bb.1.for.body.preheader: %8:gpr32 = ORRWrs $wzr, %5, 0 - %0:gpr64 = SUBREG_TO_REG 0, killed %8, %subreg.sub_32 + %0:gpr64 = SUBREG_TO_REG killed %8, %subreg.sub_32 %9:gpr64all = COPY $xzr %7:gpr64all = COPY %9 %13:gpr64common = ADRP target-flags(aarch64-page) @x diff --git a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir index 6116f15811ec7..b7bda43a75aa1 100644 --- a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir +++ b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir @@ -71,7 +71,7 @@ body: | bb.1.for.body.preheader: %13:gpr32 = ORRWrs $wzr, %9, 0 - %1:gpr64 = SUBREG_TO_REG 0, killed %13, %subreg.sub_32 + %1:gpr64 = SUBREG_TO_REG killed %13, %subreg.sub_32 %14:gpr64all = COPY $xzr %12:gpr64all = COPY %14 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir b/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir index 61e3c73a3ee53..5eb174c433b8a 100644 --- a/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir +++ b/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir @@ -237,7 +237,7 @@ body: | %2:gpr64sp = PHI %17, %bb.0, %13, %bb.3 %4:zpr = DUP_ZR_D %2 %22:zpr = COPY %21 - %20:gpr64all = SUBREG_TO_REG 0, %23, %subreg.sub_32 + %20:gpr64all = SUBREG_TO_REG %23, %subreg.sub_32 bb.2.vector.body: successors: %bb.3(0x04000000), %bb.2(0x7c000000) diff --git a/llvm/test/CodeGen/AArch64/sms-regpress.mir b/llvm/test/CodeGen/AArch64/sms-regpress.mir index c75eba5aab888..0e126ccf87cbe 100644 --- a/llvm/test/CodeGen/AArch64/sms-regpress.mir +++ b/llvm/test/CodeGen/AArch64/sms-regpress.mir @@ -102,7 +102,7 @@ body: | %0:fpr64 = LDRDui %10, 0 :: (load (s64) from %ir.a) %1:fpr64 = LDRDui %10, 1 :: (load (s64) from %ir.arrayidx1) %16:gpr32 = ORRWrs $wzr, %12, 0 - %2:gpr64all = SUBREG_TO_REG 0, killed %16, %subreg.sub_32 + %2:gpr64all = SUBREG_TO_REG killed %16, %subreg.sub_32 %15:fpr64 = FMOVD0 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir index 42774732ecbad..8a9ccee3565af 100644 --- a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir +++ b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir @@ -53,7 +53,7 @@ body: | bb.1.for.body.preheader: %11:gpr32 = ORRWrs $wzr, %9, 0 - %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32 + %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32 %14:fpr32 = FMOVSi 112 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir index 4f5b85f05e1c2..2b7d78b1d3daf 100644 --- a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir +++ b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir @@ -56,7 +56,7 @@ body: | bb.1.for.body.preheader: %7:gpr32common = SUBWri %5, 1, 0 %9:gpr64all = IMPLICIT_DEF - %8:gpr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG killed %7, %subreg.sub_32 %10:gpr64 = SBFMXri killed %8, 0, 31 %0:gpr64all = COPY %10 %12:fpr32 = FMOVSi 112 diff --git a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir index fb28174a79a4a..769fc21266b09 100644 --- a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir +++ b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir @@ -59,7 +59,7 @@ body: | bb.1.for.body.preheader: %11:gpr32 = ORRWrs $wzr, %9, 0 - %0:gpr64all = SUBREG_TO_REG 0, killed %11, %subreg.sub_32 + %0:gpr64all = SUBREG_TO_REG killed %11, %subreg.sub_32 %14:fpr32 = FMOVSi 0 %15:fpr32 = FMOVSi 112 B %bb.3 diff --git a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir index 290f7027244f2..d40d28e0e47e6 100644 --- a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir +++ b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir @@ -60,7 +60,7 @@ body: | bb.1.for.body.preheader: %7:gpr32common = SUBWri %5, 1, 0 %9:gpr64all = IMPLICIT_DEF - %8:gpr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32 + %8:gpr64 = SUBREG_TO_REG killed %7, %subreg.sub_32 %10:gpr64 = SBFMXri killed %8, 0, 31 %0:gpr64all = COPY %10 %12:fpr32 = FMOVSi 112 diff --git a/llvm/test/CodeGen/AArch64/sqrt-fastmath.ll b/llvm/test/CodeGen/AArch64/sqrt-fastmath.ll index e29993d02935a..241621b51eba8 100644 --- a/llvm/test/CodeGen/AArch64/sqrt-fastmath.ll +++ b/llvm/test/CodeGen/AArch64/sqrt-fastmath.ll @@ -671,4 +671,4 @@ define double @sqrt_simplify_before_recip_4_uses(double %x, ptr %p1, ptr %p2, pt ret double %sqrt_fast } -attributes #0 = { "denormal-fp-math"="ieee" } +attributes #0 = { denormal_fpenv(ieee) } diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll b/llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll index 1b846cbb0a222..013040ebe9a7c 100644 --- a/llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll +++ b/llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll @@ -65,6 +65,6 @@ declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 ; Function Attrs: argmemonly nounwind willreturn declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 -attributes #0 = { sanitize_memtag "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+mte,+neon,+v8.5a" "use-soft-float"="false" } +attributes #0 = { sanitize_memtag "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+mte,+neon,+v8.5a" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind willreturn } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll b/llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll index 59b6ec7011f6b..5a05cb99c83b6 100644 --- a/llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll +++ b/llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll @@ -79,6 +79,6 @@ declare void @llvm.lifetime.start.p0(ptr nocapture) #1 declare void @llvm.lifetime.end.p0(ptr nocapture) #1 -attributes #0 = { sanitize_memtag "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+mte,+neon,+v8.5a" "use-soft-float"="false" } +attributes #0 = { sanitize_memtag "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+mte,+neon,+v8.5a" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir b/llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir index b8fa4a2fef901..7a94a9b74d54a 100644 --- a/llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir +++ b/llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir @@ -26,7 +26,7 @@ body: | %0:gpr64 = COPY killed $x1 %1:gpr32 = COPY %0.sub_32:gpr64 %2:gpr32 = ORRWrr $wzr, killed %1:gpr32 - %3:gpr64all = SUBREG_TO_REG 0, killed %2:gpr32, %subreg.sub_32 + %3:gpr64all = SUBREG_TO_REG killed %2:gpr32, %subreg.sub_32 $x0 = COPY killed %0:gpr64 $x1 = COPY killed %3:gpr64all RET_ReallyLR implicit $x1, implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll index 9c85548aee0b1..96056713857cb 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-build-vector.ll @@ -164,7 +164,7 @@ define void @build_vector_fractional_stride_v8i32(ptr %a) #0 { } ; zip1 pattern: constant <0, 1, 2, 3> is expanded to <0, 1, 2, 3, poison, poison, poison, poison> -; to match the shuffle result width. isConstantSequence recognizes this as a sequence. +; to match the shuffle result width. isArithmeticSequence recognizes this as a sequence. define <8 x i8> @zip_const_seq_with_variable(i8 %x) #0 { ; VBITS_GE_256-LABEL: zip_const_seq_with_variable: ; VBITS_GE_256: // %bb.0: diff --git a/llvm/test/CodeGen/AArch64/sve-mask-partition.ll b/llvm/test/CodeGen/AArch64/sve-mask-partition.ll new file mode 100644 index 0000000000000..8b712bd7e42a7 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-mask-partition.ll @@ -0,0 +1,560 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s + +;; Scalable +define @mask_exclude_active_nxv16( %mask.in) { +; CHECK-LABEL: mask_exclude_active_nxv16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.b +; CHECK-NEXT: brkb p0.b, p1/z, p0.b +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( %mask.in, i1 false) + %mask.out = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 %tz.elts) + ret %mask.out +} + +define @mask_exclude_active_nxv8( %mask.in) { +; CHECK-LABEL: mask_exclude_active_nxv8: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.h +; CHECK-NEXT: brkb p0.b, p1/z, p0.b +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( %mask.in, i1 false) + %mask.out = call @llvm.get.active.lane.mask.nxv8i1.i64(i64 0, i64 %tz.elts) + ret %mask.out +} + +define @mask_exclude_active_nxv4( %mask.in) { +; CHECK-LABEL: mask_exclude_active_nxv4: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.s +; CHECK-NEXT: brkb p0.b, p1/z, p0.b +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( %mask.in, i1 false) + %mask.out = call @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 %tz.elts) + ret %mask.out +} + +define @mask_exclude_active_nxv2( %mask.in) { +; CHECK-LABEL: mask_exclude_active_nxv2: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.d +; CHECK-NEXT: brkb p0.b, p1/z, p0.b +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( %mask.in, i1 false) + %mask.out = call @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 %tz.elts) + ret %mask.out +} + +define @mask_include_active_nxv16( %mask.in) { +; CHECK-LABEL: mask_include_active_nxv16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.b +; CHECK-NEXT: brka p0.b, p1/z, p0.b +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( %mask.in, i1 false) + %inc = add i64 %tz.elts, 1 + %mask.out = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 %inc) + ret %mask.out +} + +define @mask_include_active_nxv8( %mask.in) { +; CHECK-LABEL: mask_include_active_nxv8: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.h +; CHECK-NEXT: brka p0.b, p1/z, p0.b +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv8i1( %mask.in, i1 false) + %inc = add i64 %tz.elts, 1 + %mask.out = call @llvm.get.active.lane.mask.nxv8i1.i64(i64 0, i64 %inc) + ret %mask.out +} + +define @mask_include_active_nxv4( %mask.in) { +; CHECK-LABEL: mask_include_active_nxv4: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.s +; CHECK-NEXT: brka p0.b, p1/z, p0.b +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv4i1( %mask.in, i1 false) + %inc = add i64 %tz.elts, 1 + %mask.out = call @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 %inc) + ret %mask.out +} + +define @mask_include_active_nxv2( %mask.in) { +; CHECK-LABEL: mask_include_active_nxv2: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.d +; CHECK-NEXT: brka p0.b, p1/z, p0.b +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv2i1( %mask.in, i1 false) + %inc = add i64 %tz.elts, 1 + %mask.out = call @llvm.get.active.lane.mask.nxv2i1.i64(i64 0, i64 %inc) + ret %mask.out +} + +;; Fixed +define <16 x i1> @mask_exclude_active_v16(<16 x i1> %mask.in) { +; CHECK-LABEL: mask_exclude_active_v16: +; CHECK: // %bb.0: +; CHECK-NEXT: shl v0.16b, v0.16b, #7 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; CHECK-NEXT: brkb p0.b, p0/z, p1.b +; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1> %mask.in, i1 false) + %mask.out = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %tz.elts) + ret <16 x i1> %mask.out +} + +define <8 x i1> @mask_exclude_active_v8(<8 x i1> %mask.in) { +; CHECK-LABEL: mask_exclude_active_v8: +; CHECK: // %bb.0: +; CHECK-NEXT: shl v0.8b, v0.8b, #7 +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; CHECK-NEXT: brkb p0.b, p0/z, p1.b +; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> %mask.in, i1 false) + %mask.out = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 %tz.elts) + ret <8 x i1> %mask.out +} + +define <4 x i1> @mask_exclude_active_v4(<4 x i1> %mask.in) { +; CHECK-LABEL: mask_exclude_active_v4: +; CHECK: // %bb.0: +; CHECK-NEXT: shl v0.4h, v0.4h, #15 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: cmpne p1.h, p0/z, z0.h, #0 +; CHECK-NEXT: brkb p0.b, p0/z, p1.b +; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> %mask.in, i1 false) + %mask.out = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 %tz.elts) + ret <4 x i1> %mask.out +} + +define <2 x i1> @mask_exclude_active_v2(<2 x i1> %mask.in) { +; CHECK-LABEL: mask_exclude_active_v2: +; CHECK: // %bb.0: +; CHECK-NEXT: shl v0.2s, v0.2s, #31 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0 +; CHECK-NEXT: brkb p0.b, p0/z, p1.b +; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> %mask.in, i1 false) + %mask.out = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 0, i64 %tz.elts) + ret <2 x i1> %mask.out +} + +define <16 x i1> @mask_include_active_v16(<16 x i1> %mask.in) { +; CHECK-LABEL: mask_include_active_v16: +; CHECK: // %bb.0: +; CHECK-NEXT: shl v0.16b, v0.16b, #7 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; CHECK-NEXT: brka p0.b, p0/z, p1.b +; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v16i1(<16 x i1> %mask.in, i1 false) + %inc = add i64 %tz.elts, 1 + %mask.out = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %inc) + ret <16 x i1> %mask.out +} + +define <8 x i1> @mask_include_active_v8(<8 x i1> %mask.in) { +; CHECK-LABEL: mask_include_active_v8: +; CHECK: // %bb.0: +; CHECK-NEXT: shl v0.8b, v0.8b, #7 +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: cmpne p1.b, p0/z, z0.b, #0 +; CHECK-NEXT: brka p0.b, p0/z, p1.b +; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v8i1(<8 x i1> %mask.in, i1 false) + %inc = add i64 %tz.elts, 1 + %mask.out = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 %inc) + ret <8 x i1> %mask.out +} + +define <4 x i1> @mask_include_active_v4(<4 x i1> %mask.in) { +; CHECK-LABEL: mask_include_active_v4: +; CHECK: // %bb.0: +; CHECK-NEXT: shl v0.4h, v0.4h, #15 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: cmpne p1.h, p0/z, z0.h, #0 +; CHECK-NEXT: brka p0.b, p0/z, p1.b +; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> %mask.in, i1 false) + %inc = add i64 %tz.elts, 1 + %mask.out = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 %inc) + ret <4 x i1> %mask.out +} + +define <2 x i1> @mask_include_active_v2(<2 x i1> %mask.in) { +; CHECK-LABEL: mask_include_active_v2: +; CHECK: // %bb.0: +; CHECK-NEXT: shl v0.2s, v0.2s, #31 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0 +; CHECK-NEXT: brka p0.b, p0/z, p1.b +; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v2i1(<2 x i1> %mask.in, i1 false) + %inc = add i64 %tz.elts, 1 + %mask.out = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 0, i64 %inc) + ret <2 x i1> %mask.out +} + +;; Wider-than-legal tests +define @mask_exclude_active_nxv32( %mask.in) { +; CHECK-LABEL: mask_exclude_active_nxv32: +; CHECK: // %bb.0: +; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: addvl sp, sp, #-9 +; CHECK-NEXT: str p11, [sp] // 2-byte Spill +; CHECK-NEXT: str p10, [sp, #1, mul vl] // 2-byte Spill +; CHECK-NEXT: str p9, [sp, #2, mul vl] // 2-byte Spill +; CHECK-NEXT: str p8, [sp, #3, mul vl] // 2-byte Spill +; CHECK-NEXT: str p7, [sp, #4, mul vl] // 2-byte Spill +; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill +; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill +; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill +; CHECK-NEXT: str z15, [sp, #1, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z14, [sp, #2, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z13, [sp, #3, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z12, [sp, #4, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z11, [sp, #5, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z10, [sp, #6, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z9, [sp, #7, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: str z8, [sp, #8, mul vl] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0xc8, 0x00, 0x1e, 0x22 // sp + 16 + 72 * VG +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d8 @ cfa - 8 * VG - 16 +; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d9 @ cfa - 16 * VG - 16 +; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 24 * VG - 16 +; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 32 * VG - 16 +; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x40, 0x1c // $d12 @ cfa - 40 * VG - 16 +; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x40, 0x1c // $d13 @ cfa - 48 * VG - 16 +; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x40, 0x1c // $d14 @ cfa - 56 * VG - 16 +; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x40, 0x1c // $d15 @ cfa - 64 * VG - 16 +; CHECK-NEXT: index z2.d, #0, #-1 +; CHECK-NEXT: cnth x8 +; CHECK-NEXT: punpkhi p5.h, p0.b +; CHECK-NEXT: neg x8, x8 +; CHECK-NEXT: punpkhi p4.h, p1.b +; CHECK-NEXT: cntw x9 +; CHECK-NEXT: mov z0.d, x8 +; CHECK-NEXT: punpklo p3.h, p5.b +; CHECK-NEXT: rdvl x8, #-1 +; CHECK-NEXT: punpklo p2.h, p4.b +; CHECK-NEXT: mov z1.d, x8 +; CHECK-NEXT: neg x8, x9 +; CHECK-NEXT: incd z2.d, all, mul #16 +; CHECK-NEXT: punpklo p10.h, p0.b +; CHECK-NEXT: mov z5.d, x8 +; CHECK-NEXT: punpklo p9.h, p3.b +; CHECK-NEXT: cntd x8 +; CHECK-NEXT: rdvl x9, #2 +; CHECK-NEXT: punpklo p1.h, p1.b +; CHECK-NEXT: neg x8, x8 +; CHECK-NEXT: add z4.d, z2.d, z0.d +; CHECK-NEXT: punpklo p8.h, p2.b +; CHECK-NEXT: mov z7.d, p9/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: punpklo p6.h, p10.b +; CHECK-NEXT: mov z28.d, x8 +; CHECK-NEXT: add z25.d, z2.d, z5.d +; CHECK-NEXT: punpklo p7.h, p1.b +; CHECK-NEXT: mov z3.d, p8/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: add z6.d, z4.d, z1.d +; CHECK-NEXT: punpklo p8.h, p6.b +; CHECK-NEXT: and z4.d, z4.d, z7.d +; CHECK-NEXT: punpkhi p0.h, p1.b +; CHECK-NEXT: add z28.d, z2.d, z28.d +; CHECK-NEXT: add z26.d, z25.d, z0.d +; CHECK-NEXT: punpkhi p1.h, p10.b +; CHECK-NEXT: ldr p10, [sp, #1, mul vl] // 2-byte Reload +; CHECK-NEXT: mov z7.d, p8/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: punpklo p11.h, p7.b +; CHECK-NEXT: and z3.d, z6.d, z3.d +; CHECK-NEXT: add z6.d, z2.d, z1.d +; CHECK-NEXT: punpklo p9.h, p0.b +; CHECK-NEXT: add z29.d, z25.d, z1.d +; CHECK-NEXT: add z5.d, z28.d, z5.d +; CHECK-NEXT: punpklo p8.h, p1.b +; CHECK-NEXT: mov z24.d, p11/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr p11, [sp] // 2-byte Reload +; CHECK-NEXT: punpkhi p5.h, p5.b +; CHECK-NEXT: mov z27.d, p9/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: add z31.d, z26.d, z1.d +; CHECK-NEXT: punpkhi p4.h, p4.b +; CHECK-NEXT: mov z30.d, p8/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z2.d, z2.d, z7.d +; CHECK-NEXT: punpklo p9.h, p5.b +; CHECK-NEXT: and z6.d, z6.d, z24.d +; CHECK-NEXT: add z12.d, z5.d, z1.d +; CHECK-NEXT: punpklo p8.h, p4.b +; CHECK-NEXT: and z7.d, z29.d, z27.d +; CHECK-NEXT: add z29.d, z28.d, z0.d +; CHECK-NEXT: mov z24.d, p9/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr p9, [sp, #2, mul vl] // 2-byte Reload +; CHECK-NEXT: punpkhi p3.h, p3.b +; CHECK-NEXT: mov z8.d, p8/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr p8, [sp, #3, mul vl] // 2-byte Reload +; CHECK-NEXT: punpkhi p2.h, p2.b +; CHECK-NEXT: add z0.d, z5.d, z0.d +; CHECK-NEXT: punpkhi p7.h, p7.b +; CHECK-NEXT: and z25.d, z25.d, z30.d +; CHECK-NEXT: punpkhi p6.h, p6.b +; CHECK-NEXT: and z24.d, z26.d, z24.d +; CHECK-NEXT: mov z10.d, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z26.d, z31.d, z8.d +; CHECK-NEXT: punpkhi p1.h, p1.b +; CHECK-NEXT: mov z8.d, p3/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: punpkhi p0.h, p0.b +; CHECK-NEXT: add z27.d, z28.d, z1.d +; CHECK-NEXT: mov z30.d, p7/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr p7, [sp, #4, mul vl] // 2-byte Reload +; CHECK-NEXT: punpkhi p3.h, p5.b +; CHECK-NEXT: mov z31.d, p6/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload +; CHECK-NEXT: punpkhi p2.h, p4.b +; CHECK-NEXT: add z9.d, z29.d, z1.d +; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload +; CHECK-NEXT: mov z11.d, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z13.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload +; CHECK-NEXT: mov z14.d, p3/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: add z1.d, z0.d, z1.d +; CHECK-NEXT: mov z15.d, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z27.d, z27.d, z30.d +; CHECK-NEXT: and z28.d, z28.d, z31.d +; CHECK-NEXT: and z29.d, z29.d, z8.d +; CHECK-NEXT: ldr z8, [sp, #8, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: and z30.d, z9.d, z10.d +; CHECK-NEXT: ldr z10, [sp, #6, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z9, [sp, #7, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: and z5.d, z5.d, z11.d +; CHECK-NEXT: ldr z11, [sp, #5, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: and z31.d, z12.d, z13.d +; CHECK-NEXT: ldr z13, [sp, #3, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ldr z12, [sp, #4, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: and z0.d, z0.d, z14.d +; CHECK-NEXT: ldr z14, [sp, #2, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: and z1.d, z1.d, z15.d +; CHECK-NEXT: ldr z15, [sp, #1, mul vl] // 16-byte Folded Reload +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: umax z3.d, p0/m, z3.d, z4.d +; CHECK-NEXT: umax z2.d, p0/m, z2.d, z6.d +; CHECK-NEXT: umax z7.d, p0/m, z7.d, z25.d +; CHECK-NEXT: umax z24.d, p0/m, z24.d, z26.d +; CHECK-NEXT: umax z27.d, p0/m, z27.d, z28.d +; CHECK-NEXT: umax z29.d, p0/m, z29.d, z30.d +; CHECK-NEXT: umax z5.d, p0/m, z5.d, z31.d +; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: umax z2.d, p0/m, z2.d, z3.d +; CHECK-NEXT: umax z7.d, p0/m, z7.d, z24.d +; CHECK-NEXT: umax z27.d, p0/m, z27.d, z29.d +; CHECK-NEXT: umax z0.d, p0/m, z0.d, z5.d +; CHECK-NEXT: umax z2.d, p0/m, z2.d, z7.d +; CHECK-NEXT: umax z0.d, p0/m, z0.d, z27.d +; CHECK-NEXT: umax z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: umaxv d0, p0, z0.d +; CHECK-NEXT: fmov x8, d0 +; CHECK-NEXT: sub x8, x9, x8 +; CHECK-NEXT: rdvl x9, #1 +; CHECK-NEXT: whilelo p0.b, xzr, x8 +; CHECK-NEXT: whilelo p1.b, x9, x8 +; CHECK-NEXT: addvl sp, sp, #9 +; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv32i1( %mask.in, i1 false) + %mask.out = call @llvm.get.active.lane.mask.nxv32i1.i64(i64 0, i64 %tz.elts) + ret %mask.out +} + +define <32 x i1> @mask_exclude_active_v32(<32 x i1> %mask.in) { +; CHECK-LABEL: mask_exclude_active_v32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr w9, [sp, #64] +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: ldr w10, [sp, #72] +; CHECK-NEXT: index z2.b, #0, #-1 +; CHECK-NEXT: fmov s1, w9 +; CHECK-NEXT: ldr w9, [sp, #80] +; CHECK-NEXT: mov v0.b[1], w1 +; CHECK-NEXT: mov v1.b[1], w10 +; CHECK-NEXT: ldr w10, [sp, #128] +; CHECK-NEXT: mov z3.d, z2.d +; CHECK-NEXT: add z2.b, z2.b, #32 // =0x20 +; CHECK-NEXT: mov v0.b[2], w2 +; CHECK-NEXT: add z3.b, z3.b, #16 // =0x10 +; CHECK-NEXT: mov v1.b[2], w9 +; CHECK-NEXT: ldr w9, [sp, #88] +; CHECK-NEXT: mov v0.b[3], w3 +; CHECK-NEXT: mov v1.b[3], w9 +; CHECK-NEXT: ldr w9, [sp, #96] +; CHECK-NEXT: mov v0.b[4], w4 +; CHECK-NEXT: mov v1.b[4], w9 +; CHECK-NEXT: ldr w9, [sp, #104] +; CHECK-NEXT: mov v0.b[5], w5 +; CHECK-NEXT: mov v1.b[5], w9 +; CHECK-NEXT: ldr w9, [sp, #112] +; CHECK-NEXT: mov v0.b[6], w6 +; CHECK-NEXT: mov v1.b[6], w9 +; CHECK-NEXT: ldr w9, [sp, #120] +; CHECK-NEXT: mov v0.b[7], w7 +; CHECK-NEXT: mov v1.b[7], w9 +; CHECK-NEXT: ldr w9, [sp] +; CHECK-NEXT: mov v0.b[8], w9 +; CHECK-NEXT: ldr w9, [sp, #8] +; CHECK-NEXT: mov v1.b[8], w10 +; CHECK-NEXT: ldr w10, [sp, #136] +; CHECK-NEXT: mov v0.b[9], w9 +; CHECK-NEXT: ldr w9, [sp, #16] +; CHECK-NEXT: mov v1.b[9], w10 +; CHECK-NEXT: ldr w10, [sp, #144] +; CHECK-NEXT: mov v0.b[10], w9 +; CHECK-NEXT: ldr w9, [sp, #24] +; CHECK-NEXT: mov v1.b[10], w10 +; CHECK-NEXT: ldr w10, [sp, #152] +; CHECK-NEXT: mov v0.b[11], w9 +; CHECK-NEXT: ldr w9, [sp, #32] +; CHECK-NEXT: mov v1.b[11], w10 +; CHECK-NEXT: ldr w10, [sp, #160] +; CHECK-NEXT: mov v0.b[12], w9 +; CHECK-NEXT: ldr w9, [sp, #40] +; CHECK-NEXT: mov v1.b[12], w10 +; CHECK-NEXT: ldr w10, [sp, #168] +; CHECK-NEXT: mov v0.b[13], w9 +; CHECK-NEXT: ldr w9, [sp, #48] +; CHECK-NEXT: mov v1.b[13], w10 +; CHECK-NEXT: ldr w10, [sp, #176] +; CHECK-NEXT: mov v0.b[14], w9 +; CHECK-NEXT: ldr w9, [sp, #56] +; CHECK-NEXT: mov v1.b[14], w10 +; CHECK-NEXT: ldr w10, [sp, #184] +; CHECK-NEXT: mov v0.b[15], w9 +; CHECK-NEXT: mov w9, #32 // =0x20 +; CHECK-NEXT: mov v1.b[15], w10 +; CHECK-NEXT: shl v0.16b, v0.16b, #7 +; CHECK-NEXT: shl v1.16b, v1.16b, #7 +; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 +; CHECK-NEXT: cmlt v1.16b, v1.16b, #0 +; CHECK-NEXT: and v2.16b, v0.16b, v2.16b +; CHECK-NEXT: index z0.d, #0, #1 +; CHECK-NEXT: and v1.16b, v1.16b, v3.16b +; CHECK-NEXT: mov z3.d, z0.d +; CHECK-NEXT: mov z6.d, z0.d +; CHECK-NEXT: mov z4.d, z0.d +; CHECK-NEXT: umax v2.16b, v2.16b, v1.16b +; CHECK-NEXT: mov z1.d, z0.d +; CHECK-NEXT: mov z5.d, z0.d +; CHECK-NEXT: mov z7.d, z0.d +; CHECK-NEXT: mov z17.d, z0.d +; CHECK-NEXT: mov z18.d, z0.d +; CHECK-NEXT: mov z19.d, z0.d +; CHECK-NEXT: mov z20.d, z0.d +; CHECK-NEXT: mov z21.d, z0.d +; CHECK-NEXT: umaxv b16, v2.16b +; CHECK-NEXT: mov z2.d, z0.d +; CHECK-NEXT: mov z22.d, z0.d +; CHECK-NEXT: mov z23.d, z0.d +; CHECK-NEXT: add z1.d, z1.d, #14 // =0xe +; CHECK-NEXT: add z3.d, z3.d, #12 // =0xc +; CHECK-NEXT: add z6.d, z6.d, #10 // =0xa +; CHECK-NEXT: add z4.d, z4.d, #8 // =0x8 +; CHECK-NEXT: add z5.d, z5.d, #4 // =0x4 +; CHECK-NEXT: add z2.d, z2.d, #6 // =0x6 +; CHECK-NEXT: add z7.d, z7.d, #2 // =0x2 +; CHECK-NEXT: add z17.d, z17.d, #30 // =0x1e +; CHECK-NEXT: fmov w10, s16 +; CHECK-NEXT: add z18.d, z18.d, #28 // =0x1c +; CHECK-NEXT: add z19.d, z19.d, #26 // =0x1a +; CHECK-NEXT: add z20.d, z20.d, #24 // =0x18 +; CHECK-NEXT: add z21.d, z21.d, #22 // =0x16 +; CHECK-NEXT: add z22.d, z22.d, #20 // =0x14 +; CHECK-NEXT: add z23.d, z23.d, #18 // =0x12 +; CHECK-NEXT: sub w9, w9, w10 +; CHECK-NEXT: and x9, x9, #0xff +; CHECK-NEXT: dup v16.2d, x9 +; CHECK-NEXT: adrp x9, .LCPI17_0 +; CHECK-NEXT: cmhi v24.2d, v16.2d, v0.2d +; CHECK-NEXT: add z0.d, z0.d, #16 // =0x10 +; CHECK-NEXT: cmhi v1.2d, v16.2d, v1.2d +; CHECK-NEXT: cmhi v3.2d, v16.2d, v3.2d +; CHECK-NEXT: cmhi v6.2d, v16.2d, v6.2d +; CHECK-NEXT: cmhi v4.2d, v16.2d, v4.2d +; CHECK-NEXT: cmhi v17.2d, v16.2d, v17.2d +; CHECK-NEXT: cmhi v18.2d, v16.2d, v18.2d +; CHECK-NEXT: cmhi v19.2d, v16.2d, v19.2d +; CHECK-NEXT: cmhi v20.2d, v16.2d, v20.2d +; CHECK-NEXT: cmhi v21.2d, v16.2d, v21.2d +; CHECK-NEXT: cmhi v22.2d, v16.2d, v22.2d +; CHECK-NEXT: cmhi v23.2d, v16.2d, v23.2d +; CHECK-NEXT: cmhi v0.2d, v16.2d, v0.2d +; CHECK-NEXT: cmhi v2.2d, v16.2d, v2.2d +; CHECK-NEXT: cmhi v5.2d, v16.2d, v5.2d +; CHECK-NEXT: cmhi v7.2d, v16.2d, v7.2d +; CHECK-NEXT: uzp1 v1.4s, v3.4s, v1.4s +; CHECK-NEXT: uzp1 v3.4s, v18.4s, v17.4s +; CHECK-NEXT: uzp1 v16.4s, v20.4s, v19.4s +; CHECK-NEXT: uzp1 v17.4s, v22.4s, v21.4s +; CHECK-NEXT: uzp1 v0.4s, v0.4s, v23.4s +; CHECK-NEXT: uzp1 v4.4s, v4.4s, v6.4s +; CHECK-NEXT: uzp1 v2.4s, v5.4s, v2.4s +; CHECK-NEXT: uzp1 v5.4s, v24.4s, v7.4s +; CHECK-NEXT: uzp1 v3.8h, v16.8h, v3.8h +; CHECK-NEXT: uzp1 v0.8h, v0.8h, v17.8h +; CHECK-NEXT: uzp1 v1.8h, v4.8h, v1.8h +; CHECK-NEXT: uzp1 v2.8h, v5.8h, v2.8h +; CHECK-NEXT: uzp1 v0.16b, v0.16b, v3.16b +; CHECK-NEXT: uzp1 v1.16b, v2.16b, v1.16b +; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI17_0] +; CHECK-NEXT: shl v0.16b, v0.16b, #7 +; CHECK-NEXT: shl v1.16b, v1.16b, #7 +; CHECK-NEXT: cmlt v0.16b, v0.16b, #0 +; CHECK-NEXT: cmlt v1.16b, v1.16b, #0 +; CHECK-NEXT: and v0.16b, v0.16b, v2.16b +; CHECK-NEXT: and v1.16b, v1.16b, v2.16b +; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8 +; CHECK-NEXT: zip1 v0.16b, v0.16b, v2.16b +; CHECK-NEXT: zip1 v1.16b, v1.16b, v3.16b +; CHECK-NEXT: addv h0, v0.8h +; CHECK-NEXT: addv h1, v1.8h +; CHECK-NEXT: str h0, [x8, #2] +; CHECK-NEXT: str h1, [x8] +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.v32i1(<32 x i1> %mask.in, i1 false) + %mask.out = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %tz.elts) + ret <32 x i1> %mask.out +} + +;; Non-matches +define @mask_exclude_active_nxv16_nonzero_lower_bound( %mask.in) { +; CHECK-LABEL: mask_exclude_active_nxv16_nonzero_lower_bound: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p1.b +; CHECK-NEXT: mov w9, #1 // =0x1 +; CHECK-NEXT: brkb p0.b, p1/z, p0.b +; CHECK-NEXT: cntp x8, p0, p0.b +; CHECK-NEXT: whilelo p0.b, x9, x8 +; CHECK-NEXT: ret + %tz.elts = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( %mask.in, i1 false) + %mask.out = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 1, i64 %tz.elts) + ret %mask.out +} diff --git a/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir b/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir index 566753b7d4d10..3b72e760c54fb 100644 --- a/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir +++ b/llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir @@ -26,7 +26,7 @@ body: | %0:gpr32 = COPY %3.sub_32 ; CHECK: {{.*}}.sub_32:gpr64 = COPY {{.*}}.sub_32 STRBBui %1, %2, target-flags(aarch64-pageoff, aarch64-nc) @c :: (store (s8) into @c, align 4) - %8:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %8:gpr64all = SUBREG_TO_REG %0, %subreg.sub_32 $x0 = COPY %8 ; CHECK: $x0 = COPY RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll index 32f539a267e67..9adb56cb0861e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmax.ll @@ -333,6 +333,7 @@ define float @global_agent_atomic_fmax_ret_f32__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_max_f32_e32 v3, v5, v5 ; GFX942-NEXT: v_max_f32_e32 v4, v3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -478,6 +479,7 @@ define void @global_agent_atomic_fmax_noret_f32__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -630,6 +632,7 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -785,6 +788,7 @@ define void @global_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[2:3], off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -924,6 +928,7 @@ define float @flat_agent_atomic_fmax_ret_f32__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_max_f32_e32 v3, v5, v5 ; GFX942-NEXT: v_max_f32_e32 v4, v3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1065,6 +1070,7 @@ define void @flat_agent_atomic_fmax_noret_f32__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1216,6 +1222,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1369,6 +1376,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1513,6 +1521,7 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__amdgpu_no_fine_grained_m ; GFX942-NEXT: v_max_f32_e32 v4, v0, v3 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v2, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1667,6 +1676,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f32__amdgpu_no_fine_grained_ ; GFX942-NEXT: v_max_f32_e32 v0, v0, v3 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[4:5], v2, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1831,6 +1841,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1997,6 +2008,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 offen ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll index be0ef85b217de..876eacb763695 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_fmin.ll @@ -333,6 +333,7 @@ define float @global_agent_atomic_fmin_ret_f32__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_max_f32_e32 v3, v5, v5 ; GFX942-NEXT: v_min_f32_e32 v4, v3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -478,6 +479,7 @@ define void @global_agent_atomic_fmin_noret_f32__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -630,6 +632,7 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -785,6 +788,7 @@ define void @global_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[2:3], off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -924,6 +928,7 @@ define float @flat_agent_atomic_fmin_ret_f32__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_max_f32_e32 v3, v5, v5 ; GFX942-NEXT: v_min_f32_e32 v4, v3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1065,6 +1070,7 @@ define void @flat_agent_atomic_fmin_noret_f32__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1216,6 +1222,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1369,6 +1376,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1513,6 +1521,7 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__amdgpu_no_fine_grained_m ; GFX942-NEXT: v_min_f32_e32 v4, v0, v3 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v2, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1667,6 +1676,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f32__amdgpu_no_fine_grained_ ; GFX942-NEXT: v_min_f32_e32 v0, v0, v3 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[4:5], v2, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1831,6 +1841,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1997,6 +2008,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 offen ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll index 48b6dd95bdc0d..e4ab4b74e4db1 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll @@ -53,16 +53,14 @@ define amdgpu_vs float @test_f16_f32_add_ext_fma_mul(half %x, half %y, float %z, ; GFX10: ; %bb.0: ; %.entry ; GFX10-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX10-NEXT: v_fmac_f16_e32 v3, v0, v1 -; GFX10-NEXT: v_cvt_f32_f16_e32 v0, v3 -; GFX10-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX10-NEXT: v_fma_mix_f32 v0, v3, 1.0, v2 op_sel_hi:[1,1,0] ; GFX10-NEXT: ; return to shader part epilog ; ; GFX10-CONTRACT-LABEL: test_f16_f32_add_ext_fma_mul: ; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v3, v0, v1 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v0, v3 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v3, 1.0, v2 op_sel_hi:[1,1,0] ; GFX10-CONTRACT-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_f16_f32_add_ext_fma_mul: @@ -70,8 +68,7 @@ define amdgpu_vs float @test_f16_f32_add_ext_fma_mul(half %x, half %y, float %z, ; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX10-DENORM-NEXT: v_mul_f16_e32 v0, v0, v1 ; GFX10-DENORM-NEXT: v_add_f16_e32 v0, v0, v3 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: ; return to shader part epilog .entry: %a = fmul half %u, %v @@ -129,16 +126,14 @@ define amdgpu_vs float @test_f16_f32_add_ext_fma_mul_rhs(float %x, half %y, half ; GFX10: ; %bb.0: ; %.entry ; GFX10-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX10-NEXT: v_fmac_f16_e32 v3, v1, v2 -; GFX10-NEXT: v_cvt_f32_f16_e32 v1, v3 -; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX10-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0] ; GFX10-NEXT: ; return to shader part epilog ; ; GFX10-CONTRACT-LABEL: test_f16_f32_add_ext_fma_mul_rhs: ; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX10-CONTRACT-NEXT: v_fmac_f16_e32 v3, v1, v2 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v1, v3 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0] ; GFX10-CONTRACT-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_f16_f32_add_ext_fma_mul_rhs: @@ -146,8 +141,7 @@ define amdgpu_vs float @test_f16_f32_add_ext_fma_mul_rhs(float %x, half %y, half ; GFX10-DENORM-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX10-DENORM-NEXT: v_mul_f16_e32 v1, v1, v2 ; GFX10-DENORM-NEXT: v_add_f16_e32 v1, v1, v3 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v1, 1.0, v0 op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: ; return to shader part epilog .entry: %a = fmul half %u, %v @@ -230,48 +224,36 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul(<4 x half> %x, <4 ; GFX9-DENORM-NEXT: v_pk_mul_f16 v9, v9, v11 ; GFX9-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 ; GFX9-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 -; GFX9-DENORM-NEXT: v_pk_add_f16 v0, v0, v8 -; GFX9-DENORM-NEXT: v_pk_add_f16 v1, v1, v9 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_add_f32_e32 v0, v2, v4 -; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v3, v5 -; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v8, v6 -; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v9, v7 +; GFX9-DENORM-NEXT: v_pk_add_f16 v2, v0, v8 +; GFX9-DENORM-NEXT: v_pk_add_f16 v3, v1, v9 +; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v2, 1.0, v4 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v2, 1.0, v5 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v3, 1.0, v6 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v3, 1.0, v7 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX9-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: test_v4f16_v4f32_add_ext_fma_mul: ; GFX10: ; %bb.0: ; %.entry ; GFX10-NEXT: v_pk_mul_f16 v8, v8, v10 ; GFX10-NEXT: v_pk_mul_f16 v9, v9, v11 -; GFX10-NEXT: v_pk_fma_f16 v0, v0, v2, v8 -; GFX10-NEXT: v_pk_fma_f16 v1, v1, v3, v9 -; GFX10-NEXT: v_cvt_f32_f16_e32 v2, v0 -; GFX10-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-NEXT: v_cvt_f32_f16_e32 v8, v1 -; GFX10-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-NEXT: v_add_f32_e32 v0, v2, v4 -; GFX10-NEXT: v_add_f32_e32 v1, v3, v5 -; GFX10-NEXT: v_add_f32_e32 v2, v8, v6 -; GFX10-NEXT: v_add_f32_e32 v3, v9, v7 +; GFX10-NEXT: v_pk_fma_f16 v2, v0, v2, v8 +; GFX10-NEXT: v_pk_fma_f16 v3, v1, v3, v9 +; GFX10-NEXT: v_fma_mix_f32 v0, v2, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-NEXT: v_fma_mix_f32 v1, v2, 1.0, v5 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-NEXT: v_fma_mix_f32 v2, v3, 1.0, v6 op_sel_hi:[1,1,0] +; GFX10-NEXT: v_fma_mix_f32 v3, v3, 1.0, v7 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX10-NEXT: ; return to shader part epilog ; ; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul: ; GFX10-CONTRACT: ; %bb.0: ; %.entry ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v8, v8, v10 ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v9, v9, v11 -; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v0, v0, v2, v8 -; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v1, v1, v3, v9 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v2, v0 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v8, v1 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v2, v4 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v3, v5 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v8, v6 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v9, v7 +; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v2, v0, v2, v8 +; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v3, v1, v3, v9 +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v2, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v2, 1.0, v5 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v2, v3, 1.0, v6 op_sel_hi:[1,1,0] +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v3, v3, 1.0, v7 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX10-CONTRACT-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul: @@ -280,16 +262,12 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul(<4 x half> %x, <4 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v2, v9, v11 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 -; GFX10-DENORM-NEXT: v_pk_add_f16 v0, v0, v8 -; GFX10-DENORM-NEXT: v_pk_add_f16 v1, v1, v2 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v2, v4 -; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v3, v5 -; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v8, v6 -; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v9, v7 +; GFX10-DENORM-NEXT: v_pk_add_f16 v3, v0, v8 +; GFX10-DENORM-NEXT: v_pk_add_f16 v8, v1, v2 +; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v3, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, v3, 1.0, v5 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v8, 1.0, v6 op_sel_hi:[1,1,0] +; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v8, 1.0, v7 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: ; return to shader part epilog .entry: %a = fmul <4 x half> %u, %v @@ -374,14 +352,10 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul_rhs(<4 x float> % ; GFX9-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7 ; GFX9-DENORM-NEXT: v_pk_add_f16 v4, v4, v8 ; GFX9-DENORM-NEXT: v_pk_add_f16 v5, v5, v9 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_add_f32_e32 v0, v0, v6 -; GFX9-DENORM-NEXT: v_add_f32_e32 v1, v1, v4 -; GFX9-DENORM-NEXT: v_add_f32_e32 v2, v2, v7 -; GFX9-DENORM-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v4, 1.0, v0 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v4, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v5, 1.0, v2 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v5, 1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX9-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs: @@ -390,14 +364,10 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul_rhs(<4 x float> % ; GFX10-NEXT: v_pk_mul_f16 v9, v9, v11 ; GFX10-NEXT: v_pk_fma_f16 v4, v4, v6, v8 ; GFX10-NEXT: v_pk_fma_f16 v5, v5, v7, v9 -; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v4 -; GFX10-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-NEXT: v_cvt_f32_f16_e32 v7, v5 -; GFX10-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-NEXT: v_add_f32_e32 v0, v0, v6 -; GFX10-NEXT: v_add_f32_e32 v1, v1, v4 -; GFX10-NEXT: v_add_f32_e32 v2, v2, v7 -; GFX10-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX10-NEXT: v_fma_mix_f32 v0, v4, 1.0, v0 op_sel_hi:[1,1,0] +; GFX10-NEXT: v_fma_mix_f32 v1, v4, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-NEXT: v_fma_mix_f32 v2, v5, 1.0, v2 op_sel_hi:[1,1,0] +; GFX10-NEXT: v_fma_mix_f32 v3, v5, 1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX10-NEXT: ; return to shader part epilog ; ; GFX10-CONTRACT-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs: @@ -406,14 +376,10 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul_rhs(<4 x float> % ; GFX10-CONTRACT-NEXT: v_pk_mul_f16 v9, v9, v11 ; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v4, v4, v6, v8 ; GFX10-CONTRACT-NEXT: v_pk_fma_f16 v5, v5, v7, v9 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v6, v4 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_e32 v7, v5 -; GFX10-CONTRACT-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v0, v0, v6 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v1, v1, v4 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v2, v2, v7 -; GFX10-CONTRACT-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v0, v4, 1.0, v0 op_sel_hi:[1,1,0] +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v1, v4, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v2, v5, 1.0, v2 op_sel_hi:[1,1,0] +; GFX10-CONTRACT-NEXT: v_fma_mix_f32 v3, v5, 1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX10-CONTRACT-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_v4f16_v4f32_add_ext_fma_mul_rhs: @@ -424,14 +390,10 @@ define amdgpu_vs <4 x float> @test_v4f16_v4f32_add_ext_fma_mul_rhs(<4 x float> % ; GFX10-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7 ; GFX10-DENORM-NEXT: v_pk_add_f16 v4, v4, v8 ; GFX10-DENORM-NEXT: v_pk_add_f16 v5, v5, v6 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5 -; GFX10-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-DENORM-NEXT: v_add_f32_e32 v0, v0, v6 -; GFX10-DENORM-NEXT: v_add_f32_e32 v1, v1, v4 -; GFX10-DENORM-NEXT: v_add_f32_e32 v2, v2, v7 -; GFX10-DENORM-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX10-DENORM-NEXT: v_fma_mix_f32 v0, v4, 1.0, v0 op_sel_hi:[1,1,0] +; GFX10-DENORM-NEXT: v_fma_mix_f32 v1, v4, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-DENORM-NEXT: v_fma_mix_f32 v2, v5, 1.0, v2 op_sel_hi:[1,1,0] +; GFX10-DENORM-NEXT: v_fma_mix_f32 v3, v5, 1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX10-DENORM-NEXT: ; return to shader part epilog .entry: %a = fmul <4 x half> %u, %v diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll index 21997e2224735..4dd29eace7690 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll @@ -59,16 +59,16 @@ define amdgpu_vs <5 x float> @test_5xf16_5xf32_add_ext_mul(<5 x half> inreg %x, ; GFX9-FAST-DENORM-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-FAST-DENORM-NEXT: s_lshr_b32 s3, s0, 16 ; GFX9-FAST-DENORM-NEXT: s_lshr_b32 s4, s1, 16 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s3 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v2, s1 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, s4 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v4, s2 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s6, v0 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v1, s7, v1 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v2, s8, v2 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v3, s9, v3 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v4, s10, v4 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s6 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s8 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v3, s9 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v4, s10 +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v0, s0, 1.0, v0 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v1, s3, 1.0, v1 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v2, s1, 1.0, v2 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v3, s4, 1.0, v3 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v4, s2, 1.0, v4 op_sel_hi:[1,1,0] ; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-FAST-DENORM-LABEL: test_5xf16_5xf32_add_ext_mul: @@ -110,18 +110,18 @@ define amdgpu_vs <6 x float> @test_6xf16_6xf32_add_ext_mul_rhs(<6 x half> inreg ; GFX9-FAST-DENORM-NEXT: s_lshr_b32 s3, s0, 16 ; GFX9-FAST-DENORM-NEXT: s_lshr_b32 s4, s1, 16 ; GFX9-FAST-DENORM-NEXT: s_lshr_b32 s5, s2, 16 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v0, s0 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v1, s3 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v2, s1 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v3, s4 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v4, s2 -; GFX9-FAST-DENORM-NEXT: v_cvt_f32_f16_e32 v5, s5 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v0, s6, v0 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v1, s7, v1 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v2, s8, v2 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v3, s9, v3 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v4, s10, v4 -; GFX9-FAST-DENORM-NEXT: v_add_f32_e32 v5, s11, v5 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v0, s6 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s8 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v3, s9 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v4, s10 +; GFX9-FAST-DENORM-NEXT: v_mov_b32_e32 v5, s11 +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v0, s0, 1.0, v0 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v1, s3, 1.0, v1 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v2, s1, 1.0, v2 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v3, s4, 1.0, v3 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v4, s2, 1.0, v4 op_sel_hi:[1,1,0] +; GFX9-FAST-DENORM-NEXT: v_mad_mix_f32 v5, s5, 1.0, v5 op_sel_hi:[1,1,0] ; GFX9-FAST-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-FAST-DENORM-LABEL: test_6xf16_6xf32_add_ext_mul_rhs: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll index 8879f7dc2b44c..aa6ce031ff93d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll @@ -42,16 +42,12 @@ define amdgpu_vs float @test_f16_to_f32_sub_ext_mul_rhs(float %x, half %y, half define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_mul(<4 x half> %x, <4 x half> %y, <4 x float> %z) { ; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul: ; GFX9-DENORM: ; %bb.0: ; %entry -; GFX9-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 -; GFX9-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7 +; GFX9-DENORM-NEXT: v_pk_mul_f16 v2, v0, v2 +; GFX9-DENORM-NEXT: v_pk_mul_f16 v3, v1, v3 +; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v4, -1.0, v2 op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v5, -1.0, v2 op_sel:[0,0,1] op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v6, -1.0, v3 op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v7, -1.0, v3 op_sel:[0,0,1] op_sel_hi:[0,1,1] ; GFX9-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul: @@ -76,14 +72,10 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_mul_rhs(<4 x float> %x ; GFX9-DENORM: ; %bb.0: ; %.entry ; GFX9-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6 ; GFX9-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5 +; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v4, -1.0, v0 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v4, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v5, -1.0, v2 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v5, -1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX9-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_mul_rhs: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll index df6c8dffba5ef..8febf4a53589f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll @@ -83,16 +83,12 @@ entry: define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_neg_mul(<4 x half> %x, <4 x half> %y, <4 x float> %z) { ; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul: ; GFX9-DENORM: ; %bb.0: ; %entry -; GFX9-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1] -; GFX9-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1] -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7 +; GFX9-DENORM-NEXT: v_pk_mul_f16 v2, v0, v2 neg_lo:[0,1] neg_hi:[0,1] +; GFX9-DENORM-NEXT: v_pk_mul_f16 v3, v1, v3 neg_lo:[0,1] neg_hi:[0,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v4, -1.0, v2 op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v5, -1.0, v2 op_sel:[0,0,1] op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v6, -1.0, v3 op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v7, -1.0, v3 op_sel:[0,0,1] op_sel_hi:[0,1,1] ; GFX9-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul: @@ -117,16 +113,12 @@ entry: define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_neg_ext_mul(<4 x half> %x, <4 x half> %y, <4 x float> %z) { ; GFX9-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul: ; GFX9-DENORM: ; %bb.0: ; %entry -; GFX9-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1] -; GFX9-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1] -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v2, v0 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v8, v1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v2, v4 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v3, v5 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v8, v6 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v9, v7 +; GFX9-DENORM-NEXT: v_pk_mul_f16 v2, v0, v2 neg_lo:[0,1] neg_hi:[0,1] +; GFX9-DENORM-NEXT: v_pk_mul_f16 v3, v1, v3 neg_lo:[0,1] neg_hi:[0,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v4, -1.0, v2 op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v5, -1.0, v2 op_sel:[0,0,1] op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v6, -1.0, v3 op_sel_hi:[0,1,1] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v7, -1.0, v3 op_sel:[0,0,1] op_sel_hi:[0,1,1] ; GFX9-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul: @@ -154,14 +146,10 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_ext_neg_mul2(<4 x float> % ; GFX9-DENORM: ; %bb.0: ; %entry ; GFX9-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7 neg_lo:[0,1] neg_hi:[0,1] -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5 +; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v4, -1.0, v0 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v4, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v5, -1.0, v2 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v5, -1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX9-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_ext_neg_mul2: @@ -187,14 +175,10 @@ define amdgpu_vs <4 x float> @test_v4f16_to_v4f32_sub_neg_ext_mul2(<4 x float> % ; GFX9-DENORM: ; %bb.0: ; %entry ; GFX9-DENORM-NEXT: v_pk_mul_f16 v4, v4, v6 neg_lo:[0,1] neg_hi:[0,1] ; GFX9-DENORM-NEXT: v_pk_mul_f16 v5, v5, v7 neg_lo:[0,1] neg_hi:[0,1] -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v6, v4 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_e32 v7, v5 -; GFX9-DENORM-NEXT: v_cvt_f32_f16_sdwa v5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v0, v0, v6 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v1, v1, v4 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v2, v2, v7 -; GFX9-DENORM-NEXT: v_sub_f32_e32 v3, v3, v5 +; GFX9-DENORM-NEXT: v_mad_mix_f32 v0, v4, -1.0, v0 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v1, v4, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v2, v5, -1.0, v2 op_sel_hi:[1,1,0] +; GFX9-DENORM-NEXT: v_mad_mix_f32 v3, v5, -1.0, v3 op_sel:[1,0,0] op_sel_hi:[1,1,0] ; GFX9-DENORM-NEXT: ; return to shader part epilog ; ; GFX10-DENORM-LABEL: test_v4f16_to_v4f32_sub_neg_ext_mul2: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll index 91aa286886a43..bb888fe614ce8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll @@ -118,9 +118,8 @@ define half @v_fdiv_f16(half %a, half %b) { ; GFX9-FLUSH: ; %bb.0: ; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v0 ; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v2 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0] ; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1] ; GFX9-FLUSH-NEXT: v_mac_f32_e32 v3, v4, v2 ; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1] @@ -135,18 +134,17 @@ define half @v_fdiv_f16(half %a, half %b) { ; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v0 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v5 -; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v6, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v5 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v3 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, v0, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v2 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, v0, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v4, v2 ; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v5 +; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v3 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0 ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] @@ -157,7 +155,7 @@ define half @v_fdiv_f16(half %a, half %b) { ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v0 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v5, v0, v3, neg(0) op_sel_hi:[1,0,0] ; GFX10-FLUSH-NEXT: v_mad_f32 v6, -v2, v5, v4 ; GFX10-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v3 ; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v5, v4 @@ -172,10 +170,9 @@ define half @v_fdiv_f16(half %a, half %b) { ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1 -; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0 ; GFX11-NEXT: v_rcp_f32_e32 v2, v2 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-NEXT: v_mul_f32_e32 v3, v3, v2 +; GFX11-NEXT: v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0] ; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1] ; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v2 ; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1] @@ -328,9 +325,8 @@ define half @v_fdiv_f16_ulp25(half %a, half %b) { ; GFX9-FLUSH: ; %bb.0: ; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v0 ; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v2 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0] ; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1] ; GFX9-FLUSH-NEXT: v_mac_f32_e32 v3, v4, v2 ; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1] @@ -345,18 +341,17 @@ define half @v_fdiv_f16_ulp25(half %a, half %b) { ; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v1 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v0 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v2 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v5 -; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v6, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v5 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v3 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, v0, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v2 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, v0, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v4, v2 ; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v5 +; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v3 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0 ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] @@ -367,7 +362,7 @@ define half @v_fdiv_f16_ulp25(half %a, half %b) { ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v0 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v2 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v5, v0, v3, neg(0) op_sel_hi:[1,0,0] ; GFX10-FLUSH-NEXT: v_mad_f32 v6, -v2, v5, v4 ; GFX10-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v3 ; GFX10-FLUSH-NEXT: v_mad_f32 v2, -v2, v5, v4 @@ -382,10 +377,9 @@ define half @v_fdiv_f16_ulp25(half %a, half %b) { ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cvt_f32_f16_e32 v2, v1 -; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v0 ; GFX11-NEXT: v_rcp_f32_e32 v2, v2 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-NEXT: v_mul_f32_e32 v3, v3, v2 +; GFX11-NEXT: v_fma_mix_f32 v3, v0, v2, neg(0) op_sel_hi:[1,0,0] ; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1] ; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v2 ; GFX11-NEXT: v_fma_mix_f32 v4, -v1, v3, v0 op_sel_hi:[1,0,1] @@ -940,31 +934,29 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) { ; GFX9-FLUSH: ; %bb.0: ; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v0 -; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v7, v5 +; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v3 ; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2 -; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v6, v3 -; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v7, v7 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v2 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v4, v0 op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v8, v2 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v4, v0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v4, v4 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, v0, v2, neg(0) op_sel_hi:[1,0,0] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v5, v0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v2 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, v0, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v5, v0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] ; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v8, v2 ; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2 -; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v4 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v6, v7 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v4, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v6, v7 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v4, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v6, v6, v7 -; GFX9-FLUSH-NEXT: v_and_b32_e32 v6, 0xff800000, v6 -; GFX9-FLUSH-NEXT: v_add_f32_e32 v4, v6, v4 +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v7, v6, v4 +; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v5 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX9-FLUSH-NEXT: v_and_b32_e32 v4, 0xff800000, v4 +; GFX9-FLUSH-NEXT: v_add_f32_e32 v4, v4, v7 ; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2 ; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0 -; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v5, v3 +; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v3, v5 ; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31] ; @@ -973,32 +965,30 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) { ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v8, v0 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v2 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v3 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v9, v5 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v10, v8, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v9, v7 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v12, -v3, v10 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v13, -v4, v11 -; GFX10-IEEE-NEXT: v_add_f32_e32 v12, v12, v8 -; GFX10-IEEE-NEXT: v_add_f32_e32 v13, v13, v9 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v12, v12, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v13, v13, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v10, v12, v10 -; GFX10-IEEE-NEXT: v_add_f32_e32 v11, v13, v11 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v10 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v4, -v4, v11 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v8 -; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v9 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v7 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v4 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, v0, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, v0, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v8, -v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, v0, 1.0, v7 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v8, v0, 1.0, v8 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v3 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v8, v8, v4 +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v7, v5 +; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v8, v6 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v8, -v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, v0, 1.0, v7 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v8, v0, 1.0, v8 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v7, v3 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v8, v4 ; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3 ; GFX10-IEEE-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v10 -; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v11 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v6 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v3, v1, v0 @@ -1011,30 +1001,30 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) { ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v8, v0 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v2 -; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v6, v3 -; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v9, v5 -; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v7, v4 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v10, v8, v6 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v11, v9, v7 -; GFX10-FLUSH-NEXT: v_mad_f32 v12, -v3, v10, v8 -; GFX10-FLUSH-NEXT: v_mad_f32 v13, -v4, v11, v9 -; GFX10-FLUSH-NEXT: v_mac_f32_e32 v10, v12, v6 -; GFX10-FLUSH-NEXT: v_mac_f32_e32 v11, v13, v7 -; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v10, v8 -; GFX10-FLUSH-NEXT: v_mad_f32 v4, -v4, v11, v9 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v6 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v7 +; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v3 +; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v10, v7 +; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v6, v4 +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v9, v0, v5, neg(0) op_sel_hi:[1,0,0] +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v11, v0, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-FLUSH-NEXT: v_mad_f32 v12, -v3, v9, v8 +; GFX10-FLUSH-NEXT: v_mad_f32 v13, -v4, v11, v10 +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v9, v12, v5 +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v11, v13, v6 +; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v9, v8 +; GFX10-FLUSH-NEXT: v_mad_f32 v4, -v4, v11, v10 +; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5 +; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v6 ; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3 ; GFX10-FLUSH-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v10 +; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v9 ; GFX10-FLUSH-NEXT: v_add_f32_e32 v4, v4, v11 ; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v1, v0 -; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v2, v5 +; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v2, v7 ; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] ; @@ -1043,25 +1033,24 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v0 ; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v2 ; GFX11-NEXT: v_rcp_f32_e32 v3, v3 -; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v5 ; GFX11-NEXT: v_rcp_f32_e32 v4, v4 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4 -; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1] -; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] -; GFX11-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v4 -; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1] -; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] -; GFX11-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v4 -; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX11-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v4 -; GFX11-NEXT: v_add_f32_e32 v4, v4, v7 -; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX11-NEXT: v_fma_mix_f32 v5, v0, v3, neg(0) op_sel_hi:[1,0,0] +; GFX11-NEXT: v_fma_mix_f32 v6, v0, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v5, v0 op_sel_hi:[1,0,1] +; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] +; GFX11-NEXT: v_dual_fmac_f32 v5, v7, v3 :: v_dual_fmac_f32 v6, v8, v4 +; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v5, v0 op_sel_hi:[1,0,1] +; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] +; GFX11-NEXT: v_dual_mul_f32 v3, v7, v3 :: v_dual_mul_f32 v4, v8, v4 +; GFX11-NEXT: v_and_b32_e32 v4, 0xff800000, v4 +; GFX11-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_and_b32 v3, 0xff800000, v3 +; GFX11-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX11-NEXT: v_div_fixup_f16 v0, v3, v1, v0 ; GFX11-NEXT: v_div_fixup_f16 v1, v4, v2, v5 ; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 @@ -1330,31 +1319,29 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) { ; GFX9-FLUSH: ; %bb.0: ; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v1 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v0 -; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v7, v5 +; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v3 ; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v2, v2 -; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v6, v3 -; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v7, v7 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v2 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v4, v0 op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v8, v2 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v4, v0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v4, v4 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, v0, v2, neg(0) op_sel_hi:[1,0,0] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v5, v0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v5, v6, v2 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v7, v0, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v8, -v1, v5, v0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] ; GFX9-FLUSH-NEXT: v_mul_f32_e32 v2, v8, v2 ; GFX9-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2 -; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v4 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v6, v7 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v4, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v6, v7 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v6, -v1, v4, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v6, v6, v7 -; GFX9-FLUSH-NEXT: v_and_b32_e32 v6, 0xff800000, v6 -; GFX9-FLUSH-NEXT: v_add_f32_e32 v4, v6, v4 +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v7, v6, v4 +; GFX9-FLUSH-NEXT: v_add_f32_e32 v2, v2, v5 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX9-FLUSH-NEXT: v_and_b32_e32 v4, 0xff800000, v4 +; GFX9-FLUSH-NEXT: v_add_f32_e32 v4, v4, v7 ; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2 ; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GFX9-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0 -; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v5, v3 +; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v3, v5 ; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31] ; @@ -1363,32 +1350,30 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) { ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v8, v0 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v2 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v3 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v9, v5 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v7, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v10, v8, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v11, v9, v7 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v12, -v3, v10 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v13, -v4, v11 -; GFX10-IEEE-NEXT: v_add_f32_e32 v12, v12, v8 -; GFX10-IEEE-NEXT: v_add_f32_e32 v13, v13, v9 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v12, v12, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v13, v13, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v10, v12, v10 -; GFX10-IEEE-NEXT: v_add_f32_e32 v11, v13, v11 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v10 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v4, -v4, v11 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v8 -; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v9 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v7 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v4 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, v0, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, v0, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v8, -v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, v0, 1.0, v7 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v8, v0, 1.0, v8 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v3 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v8, v8, v4 +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v7, v5 +; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v8, v6 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v8, -v1, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, v0, 1.0, v7 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v8, v0, 1.0, v8 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v7, v3 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v8, v4 ; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3 ; GFX10-IEEE-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v10 -; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v11 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v6 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v3, v1, v0 @@ -1401,30 +1386,30 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) { ; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX10-FLUSH-NEXT: v_lshrrev_b32_e32 v7, 16, v0 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v8, v0 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, v2 -; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v6, v3 -; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v9, v5 -; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v7, v4 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v10, v8, v6 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v11, v9, v7 -; GFX10-FLUSH-NEXT: v_mad_f32 v12, -v3, v10, v8 -; GFX10-FLUSH-NEXT: v_mad_f32 v13, -v4, v11, v9 -; GFX10-FLUSH-NEXT: v_mac_f32_e32 v10, v12, v6 -; GFX10-FLUSH-NEXT: v_mac_f32_e32 v11, v13, v7 -; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v10, v8 -; GFX10-FLUSH-NEXT: v_mad_f32 v4, -v4, v11, v9 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v6 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v7 +; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v3 +; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v10, v7 +; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v6, v4 +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v9, v0, v5, neg(0) op_sel_hi:[1,0,0] +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v11, v0, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-FLUSH-NEXT: v_mad_f32 v12, -v3, v9, v8 +; GFX10-FLUSH-NEXT: v_mad_f32 v13, -v4, v11, v10 +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v9, v12, v5 +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v11, v13, v6 +; GFX10-FLUSH-NEXT: v_mad_f32 v3, -v3, v9, v8 +; GFX10-FLUSH-NEXT: v_mad_f32 v4, -v4, v11, v10 +; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5 +; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v6 ; GFX10-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3 ; GFX10-FLUSH-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v10 +; GFX10-FLUSH-NEXT: v_add_f32_e32 v3, v3, v9 ; GFX10-FLUSH-NEXT: v_add_f32_e32 v4, v4, v11 ; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4 ; GFX10-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v1, v0 -; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v2, v5 +; GFX10-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v2, v7 ; GFX10-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] ; @@ -1433,25 +1418,24 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX11-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 -; GFX11-NEXT: v_cvt_f32_f16_e32 v6, v0 ; GFX11-NEXT: v_cvt_f32_f16_e32 v4, v2 ; GFX11-NEXT: v_rcp_f32_e32 v3, v3 -; GFX11-NEXT: v_cvt_f32_f16_e32 v7, v5 ; GFX11-NEXT: v_rcp_f32_e32 v4, v4 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-NEXT: v_dual_mul_f32 v6, v6, v3 :: v_dual_mul_f32 v7, v7, v4 -; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1] -; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] -; GFX11-NEXT: v_dual_fmac_f32 v6, v8, v3 :: v_dual_fmac_f32 v7, v9, v4 -; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel_hi:[1,0,1] -; GFX11-NEXT: v_fma_mix_f32 v9, -v1, v7, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] -; GFX11-NEXT: v_dual_mul_f32 v3, v8, v3 :: v_dual_mul_f32 v4, v9, v4 -; GFX11-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX11-NEXT: v_dual_add_f32 v3, v3, v6 :: v_dual_and_b32 v4, 0xff800000, v4 -; GFX11-NEXT: v_add_f32_e32 v4, v4, v7 -; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX11-NEXT: v_fma_mix_f32 v5, v0, v3, neg(0) op_sel_hi:[1,0,0] +; GFX11-NEXT: v_fma_mix_f32 v6, v0, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v5, v0 op_sel_hi:[1,0,1] +; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] +; GFX11-NEXT: v_dual_fmac_f32 v5, v7, v3 :: v_dual_fmac_f32 v6, v8, v4 +; GFX11-NEXT: v_fma_mix_f32 v7, -v1, v5, v0 op_sel_hi:[1,0,1] +; GFX11-NEXT: v_fma_mix_f32 v8, -v1, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1] +; GFX11-NEXT: v_dual_mul_f32 v3, v7, v3 :: v_dual_mul_f32 v4, v8, v4 +; GFX11-NEXT: v_and_b32_e32 v4, 0xff800000, v4 +; GFX11-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_and_b32 v3, 0xff800000, v3 +; GFX11-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0 ; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX11-NEXT: v_div_fixup_f16 v0, v3, v1, v0 ; GFX11-NEXT: v_div_fixup_f16 v1, v4, v2, v5 ; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 @@ -1663,26 +1647,26 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) { ; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v5 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v0, v2, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, -v0, v3, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_add_f32_e32 v4, 1.0, v4 +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, 1.0, v5 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v2 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v5, v3 +; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v2 +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v5, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, -v0, v4, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v0, v5, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] ; GFX10-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v6 ; GFX10-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v7 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5 -; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_add_f32_e32 v7, v7, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v2 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v6, v2 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v7, v3 ; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2 ; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v7 +; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v4 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0 @@ -1950,26 +1934,26 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) { ; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v3, v5 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, v0, v2, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, v0, v3, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_add_f32_e32 v4, -1.0, v4 +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, -1.0, v5 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v2 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v5, v3 +; GFX10-IEEE-NEXT: v_sub_f32_e32 v4, v4, v2 +; GFX10-IEEE-NEXT: v_sub_f32_e32 v5, v5, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, -v0, v4, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v0, v5, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] ; GFX10-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v6 ; GFX10-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v7 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5 -; GFX10-IEEE-NEXT: v_sub_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_sub_f32_e32 v7, v7, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v2 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v6, v2 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v7, v3 ; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2 ; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v7 +; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v4 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0 @@ -2240,35 +2224,35 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) { ; GFX10-IEEE-LABEL: v_rcp_v2f16_fabs: ; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 -; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v0 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 +; GFX10-IEEE-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0 +; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v5 +; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v4 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, -v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, -|v0|, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, 1.0, v5 ; GFX10-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v7 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v5, v3 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5 +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v5, v3 ; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_add_f32_e32 v7, v7, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v2 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5 -; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v0, -|v0|, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v7 +; GFX10-IEEE-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v7, v3 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v4 ; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v7 -; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v0 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v6 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3 -; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0 +; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, 1.0 -; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v0, v2, 1.0 +; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-FLUSH-LABEL: v_rcp_v2f16_fabs: @@ -2540,35 +2524,35 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) { ; GFX10-IEEE-LABEL: v_neg_rcp_v2f16_fabs: ; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 -; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v0 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 +; GFX10-IEEE-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0 +; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v3, v5 +; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v4 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, |v0|, v4, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, -1.0, v5 ; GFX10-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v7 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v5, v3 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5 +; GFX10-IEEE-NEXT: v_sub_f32_e32 v5, v5, v3 ; GFX10-IEEE-NEXT: v_sub_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_sub_f32_e32 v7, v7, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v2 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5 -; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v1, v5, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v0, -|v0|, v6, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v7 +; GFX10-IEEE-NEXT: v_add_f32_e32 v0, -1.0, v0 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v7, v3 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v4 ; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v7 -; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v0 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v5 +; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v6 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3 -; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, -1.0 +; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v1, v3, v1, -1.0 -; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v0, v2, -1.0 +; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v1, v0 ; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-FLUSH-LABEL: v_neg_rcp_v2f16_fabs: @@ -3000,26 +2984,26 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) { ; GFX10-IEEE-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, v0 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v3, v1 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v5, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v5 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v2 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -v0, v2, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, -v0, v3, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_add_f32_e32 v4, 1.0, v4 +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, 1.0, v5 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v2 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v5, v3 +; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v2 +; GFX10-IEEE-NEXT: v_add_f32_e32 v5, v5, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v6, -v0, v4, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v7, -v0, v5, neg(0) op_sel:[1,0,0] op_sel_hi:[1,0,0] ; GFX10-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v6 ; GFX10-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v7 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5 -; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v6, v4 -; GFX10-IEEE-NEXT: v_add_f32_e32 v7, v7, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v2 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v6, v2 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v7, v3 ; GFX10-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2 ; GFX10-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v7 +; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v2, v4 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v2, v0, 1.0 @@ -3447,36 +3431,34 @@ define amdgpu_ps i16 @s_fdiv_f16(i16 inreg %a.arg, i16 inreg %b.arg) { ; GFX9-FLUSH-LABEL: s_fdiv_f16: ; GFX9-FLUSH: ; %bb.0: ; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s1 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s0 -; GFX9-FLUSH-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-FLUSH-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v0, v0 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v0 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, -v2, v1, s0 op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mac_f32_e32 v1, v3, v0 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, -v2, v1, s0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v2, s0, v0, neg(0) op_sel_hi:[1,0,0] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, -v1, v2, s0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v2, v3, v0 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, -v1, v2, s0 op_sel_hi:[1,0,1] ; GFX9-FLUSH-NEXT: v_mul_f32_e32 v0, v3, v0 ; GFX9-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v0 -; GFX9-FLUSH-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX9-FLUSH-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v2, s0 +; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v1, s0 ; GFX9-FLUSH-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-FLUSH-NEXT: ; return to shader part epilog ; ; GFX10-IEEE-LABEL: s_fdiv_f16: ; GFX10-IEEE: ; %bb.0: ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s1 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v2, s0 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v1, v0 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v2, v1 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v4, -v0, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v4, v4, v2 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v1 -; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v4, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v2 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v0, v0 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v2, -s1, v1, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v2, s0, 1.0, v2 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v2, v2, v0 +; GFX10-IEEE-NEXT: v_add_f32_e32 v1, v2, v1 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v2, -s1, v1, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v2, s0, 1.0, v2 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v2, v0 ; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v0 -; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v3 +; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v0, s1, s0 ; GFX10-IEEE-NEXT: v_readfirstlane_b32 s0, v0 @@ -3487,7 +3469,7 @@ define amdgpu_ps i16 @s_fdiv_f16(i16 inreg %a.arg, i16 inreg %b.arg) { ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s1 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v2, s0 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v1, v0 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v3, v2, v1 +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v3, s0, v1, neg(0) op_sel_hi:[1,0,0] ; GFX10-FLUSH-NEXT: v_mad_f32 v4, -v0, v3, v2 ; GFX10-FLUSH-NEXT: v_mac_f32_e32 v3, v4, v1 ; GFX10-FLUSH-NEXT: v_mad_f32 v0, -v0, v3, v2 @@ -3502,10 +3484,9 @@ define amdgpu_ps i16 @s_fdiv_f16(i16 inreg %a.arg, i16 inreg %b.arg) { ; GFX11-LABEL: s_fdiv_f16: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s1 -; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s0 ; GFX11-NEXT: v_rcp_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-NEXT: v_mul_f32_e32 v1, v1, v0 +; GFX11-NEXT: v_fma_mix_f32 v1, s0, v0, neg(0) op_sel_hi:[1,0,0] ; GFX11-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1] ; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v0 ; GFX11-NEXT: v_fma_mix_f32 v2, -s1, v1, s0 op_sel_hi:[1,0,1] @@ -3831,33 +3812,31 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) { ; GFX9-FLUSH-LABEL: s_fdiv_v2f16: ; GFX9-FLUSH: ; %bb.0: ; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v0, s1 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s0 -; GFX9-FLUSH-NEXT: s_lshr_b32 s3, s1, 16 +; GFX9-FLUSH-NEXT: s_lshr_b32 s2, s1, 16 +; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s2 ; GFX9-FLUSH-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v0, v0 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v3, s3 -; GFX9-FLUSH-NEXT: s_lshr_b32 s2, s0, 16 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v0 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v2, v1, s0 op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mac_f32_e32 v1, v4, v0 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v2, v1, s0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: s_lshr_b32 s3, s0, 16 +; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v1, v1 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v3, s0, v0, neg(0) op_sel_hi:[1,0,0] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v2, v3, s0 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v3, v4, v0 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, -v2, v3, s0 op_sel_hi:[1,0,1] ; GFX9-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0 -; GFX9-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s2 -; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v3, v3 ; GFX9-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v0 -; GFX9-FLUSH-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX9-FLUSH-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v4, v4, v3 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v1, v4, s2 op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v5, v3 -; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v1, v4, s2 op_sel_hi:[1,0,1] -; GFX9-FLUSH-NEXT: v_mul_f32_e32 v3, v5, v3 -; GFX9-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX9-FLUSH-NEXT: v_add_f32_e32 v3, v3, v4 +; GFX9-FLUSH-NEXT: v_add_f32_e32 v0, v0, v3 +; GFX9-FLUSH-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v4, s3, v1, neg(0) op_sel_hi:[1,0,0] +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v3, v4, s3 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mac_f32_e32 v4, v5, v1 +; GFX9-FLUSH-NEXT: v_mad_mix_f32 v5, -v3, v4, s3 op_sel_hi:[1,0,1] +; GFX9-FLUSH-NEXT: v_mul_f32_e32 v1, v5, v1 +; GFX9-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v1 +; GFX9-FLUSH-NEXT: v_add_f32_e32 v1, v1, v4 ; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 -; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GFX9-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 ; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v2, s0 -; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v1, s2 +; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v1, v3, s3 ; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1 ; GFX9-FLUSH-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-FLUSH-NEXT: ; return to shader part epilog @@ -3868,30 +3847,28 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) { ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v0, s1 ; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v1, s2 ; GFX10-IEEE-NEXT: s_lshr_b32 s3, s0, 16 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v4, s0 -; GFX10-IEEE-NEXT: v_cvt_f32_f16_e32 v5, s3 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v2, v0 -; GFX10-IEEE-NEXT: v_rcp_f32_e32 v3, v1 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v6, v4, v2 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v5, v3 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v8, -v0, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v9, -v1, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v8, v8, v4 -; GFX10-IEEE-NEXT: v_add_f32_e32 v9, v9, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v8, v8, v2 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v9, v9, v3 -; GFX10-IEEE-NEXT: v_add_f32_e32 v6, v8, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v7, v9, v7 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v0, -v0, v6 -; GFX10-IEEE-NEXT: v_mul_f32_e64 v1, -v1, v7 -; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v4 -; GFX10-IEEE-NEXT: v_add_f32_e32 v1, v1, v5 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v0, v2 -; GFX10-IEEE-NEXT: v_mul_f32_e32 v1, v1, v3 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v0, v0 +; GFX10-IEEE-NEXT: v_rcp_f32_e32 v1, v1 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v2, s0, v0, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v3, s3, v1, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -s1, v2, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, -s2, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, s0, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, s3, 1.0, v5 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v4, v0 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v5, v5, v1 +; GFX10-IEEE-NEXT: v_add_f32_e32 v2, v4, v2 +; GFX10-IEEE-NEXT: v_add_f32_e32 v3, v5, v3 +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, -s1, v2, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, -s2, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v4, s0, 1.0, v4 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_fma_mix_f32 v5, s3, 1.0, v5 op_sel_hi:[1,1,0] +; GFX10-IEEE-NEXT: v_mul_f32_e32 v0, v4, v0 +; GFX10-IEEE-NEXT: v_mul_f32_e32 v1, v5, v1 ; GFX10-IEEE-NEXT: v_and_b32_e32 v0, 0xff800000, v0 ; GFX10-IEEE-NEXT: v_and_b32_e32 v1, 0xff800000, v1 -; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v6 -; GFX10-IEEE-NEXT: v_add_f32_e32 v1, v1, v7 +; GFX10-IEEE-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX10-IEEE-NEXT: v_add_f32_e32 v1, v1, v3 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX10-IEEE-NEXT: v_cvt_f16_f32_e32 v1, v1 ; GFX10-IEEE-NEXT: v_div_fixup_f16 v0, v0, s1, s0 @@ -3907,22 +3884,22 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) { ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v1, s2 ; GFX10-FLUSH-NEXT: s_lshr_b32 s3, s0, 16 ; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v4, s0 -; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v5, s3 +; GFX10-FLUSH-NEXT: v_cvt_f32_f16_e32 v6, s3 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v2, v0 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v1 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v6, v4, v2 -; GFX10-FLUSH-NEXT: v_mul_f32_e32 v7, v5, v3 -; GFX10-FLUSH-NEXT: v_mad_f32 v8, -v0, v6, v4 -; GFX10-FLUSH-NEXT: v_mad_f32 v9, -v1, v7, v5 -; GFX10-FLUSH-NEXT: v_mac_f32_e32 v6, v8, v2 +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v5, s0, v2, neg(0) op_sel_hi:[1,0,0] +; GFX10-FLUSH-NEXT: v_fma_mix_f32 v7, s3, v3, neg(0) op_sel_hi:[1,0,0] +; GFX10-FLUSH-NEXT: v_mad_f32 v8, -v0, v5, v4 +; GFX10-FLUSH-NEXT: v_mad_f32 v9, -v1, v7, v6 +; GFX10-FLUSH-NEXT: v_mac_f32_e32 v5, v8, v2 ; GFX10-FLUSH-NEXT: v_mac_f32_e32 v7, v9, v3 -; GFX10-FLUSH-NEXT: v_mad_f32 v0, -v0, v6, v4 -; GFX10-FLUSH-NEXT: v_mad_f32 v1, -v1, v7, v5 +; GFX10-FLUSH-NEXT: v_mad_f32 v0, -v0, v5, v4 +; GFX10-FLUSH-NEXT: v_mad_f32 v1, -v1, v7, v6 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v0, v2 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v1, v1, v3 ; GFX10-FLUSH-NEXT: v_and_b32_e32 v0, 0xff800000, v0 ; GFX10-FLUSH-NEXT: v_and_b32_e32 v1, 0xff800000, v1 -; GFX10-FLUSH-NEXT: v_add_f32_e32 v0, v0, v6 +; GFX10-FLUSH-NEXT: v_add_f32_e32 v0, v0, v5 ; GFX10-FLUSH-NEXT: v_add_f32_e32 v1, v1, v7 ; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v0, v0 ; GFX10-FLUSH-NEXT: v_cvt_f16_f32_e32 v1, v1 @@ -3938,12 +3915,11 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) { ; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s1 ; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s2 ; GFX11-NEXT: s_lshr_b32 s3, s0, 16 -; GFX11-NEXT: v_cvt_f32_f16_e32 v2, s0 -; GFX11-NEXT: v_cvt_f32_f16_e32 v3, s3 ; GFX11-NEXT: v_rcp_f32_e32 v0, v0 ; GFX11-NEXT: v_rcp_f32_e32 v1, v1 ; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-NEXT: v_dual_mul_f32 v2, v2, v0 :: v_dual_mul_f32 v3, v3, v1 +; GFX11-NEXT: v_fma_mix_f32 v2, s0, v0, neg(0) op_sel_hi:[1,0,0] +; GFX11-NEXT: v_fma_mix_f32 v3, s3, v1, neg(0) op_sel_hi:[1,0,0] ; GFX11-NEXT: v_fma_mix_f32 v4, -s1, v2, s0 op_sel_hi:[1,0,1] ; GFX11-NEXT: v_fma_mix_f32 v5, -s2, v3, s3 op_sel_hi:[1,0,1] ; GFX11-NEXT: v_dual_fmac_f32 v2, v4, v0 :: v_dual_fmac_f32 v3, v5, v1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll index 5db0f7f601e4f..717f0e0bb5d61 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll @@ -1,23 +1,26 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s +; RUN: sed 's/DEFAULT_MODE/ieee/g' %s > %t.ieee +; RUN: sed 's/DEFAULT_MODE/preservesign/g' %s > %t.preservesign -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=pitcairn < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %t.ieee | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %t.preservesign | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math=ieee < %s | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -denormal-fp-math=preserve-sign < %s | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %t.ieee | FileCheck -check-prefixes=GFX10,GFX10-IEEE %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %t.preservesign | FileCheck -check-prefixes=GFX10,GFX10-FLUSH %s -define float @v_fdiv_f32(float %a, float %b) { +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %t.ieee | FileCheck -check-prefixes=GFX11,GFX11-IEEE %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 < %t.preservesign | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s + +define float @v_fdiv_f32(float %a, float %b) #1 { ; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32: ; GFX6-IEEE-FASTFMA: ; %bb.0: ; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -406,7 +409,7 @@ define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #0 { ret float %fdiv } -define float @v_fdiv_f32_afn(float %a, float %b) { +define float @v_fdiv_f32_afn(float %a, float %b) #1 { ; GCN-LABEL: v_fdiv_f32_afn: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -432,7 +435,7 @@ define float @v_fdiv_f32_afn(float %a, float %b) { ret float %fdiv } -define float @v_fdiv_f32_ulp25(float %a, float %b) { +define float @v_fdiv_f32_ulp25(float %a, float %b) #1 { ; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25: ; GFX6-IEEE: ; %bb.0: ; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -634,7 +637,7 @@ define float @v_fdiv_f32_dynamic_25ulp(float %x, float %y) #0 { ret float %div } -define float @v_rcp_f32(float %x) { +define float @v_rcp_f32(float %x) #1 { ; GFX6-IEEE-FASTFMA-LABEL: v_rcp_f32: ; GFX6-IEEE-FASTFMA: ; %bb.0: ; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -818,7 +821,7 @@ define float @v_rcp_f32(float %x) { ret float %fdiv } -define float @v_rcp_f32_arcp(float %x) { +define float @v_rcp_f32_arcp(float %x) #1 { ; GFX6-IEEE-FASTFMA-LABEL: v_rcp_f32_arcp: ; GFX6-IEEE-FASTFMA: ; %bb.0: ; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1002,7 +1005,7 @@ define float @v_rcp_f32_arcp(float %x) { ret float %fdiv } -define float @v_rcp_f32_arcp_afn(float %x) { +define float @v_rcp_f32_arcp_afn(float %x) #1 { ; GCN-LABEL: v_rcp_f32_arcp_afn: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1024,7 +1027,7 @@ define float @v_rcp_f32_arcp_afn(float %x) { ret float %fdiv } -define float @v_rcp_f32_ulp25(float %x) { +define float @v_rcp_f32_ulp25(float %x) #1 { ; GFX6-IEEE-LABEL: v_rcp_f32_ulp25: ; GFX6-IEEE: ; %bb.0: ; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1081,7 +1084,7 @@ define float @v_rcp_f32_ulp25(float %x) { ret float %fdiv } -define float @v_fdiv_f32_afn_ulp25(float %a, float %b) { +define float @v_fdiv_f32_afn_ulp25(float %a, float %b) #1 { ; GCN-LABEL: v_fdiv_f32_afn_ulp25: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1107,7 +1110,7 @@ define float @v_fdiv_f32_afn_ulp25(float %a, float %b) { ret float %fdiv } -define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) { +define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) #1 { ; GFX6-IEEE-LABEL: v_fdiv_f32_arcp_ulp25: ; GFX6-IEEE: ; %bb.0: ; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1172,7 +1175,7 @@ define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) { ret float %fdiv } -define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) { +define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) #1 { ; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_v2f32: ; GFX6-IEEE-FASTFMA: ; %bb.0: ; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1488,7 +1491,7 @@ define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) { ret <2 x float> %fdiv } -define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) { +define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) #1 { ; GCN-LABEL: v_fdiv_v2f32_afn: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1519,7 +1522,7 @@ define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) { ret <2 x float> %fdiv } -define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) { +define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) #1 { ; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25: ; GFX6-IEEE: ; %bb.0: ; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1651,7 +1654,7 @@ define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) { ret <2 x float> %fdiv } -define <2 x float> @v_rcp_v2f32(<2 x float> %x) { +define <2 x float> @v_rcp_v2f32(<2 x float> %x) #1 { ; GFX6-IEEE-FASTFMA-LABEL: v_rcp_v2f32: ; GFX6-IEEE-FASTFMA: ; %bb.0: ; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1967,7 +1970,7 @@ define <2 x float> @v_rcp_v2f32(<2 x float> %x) { ret <2 x float> %fdiv } -define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) { +define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) #1 { ; GFX6-IEEE-FASTFMA-LABEL: v_rcp_v2f32_arcp: ; GFX6-IEEE-FASTFMA: ; %bb.0: ; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2283,7 +2286,7 @@ define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) { ret <2 x float> %fdiv } -define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) { +define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) #1 { ; GCN-LABEL: v_rcp_v2f32_arcp_afn: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2308,7 +2311,7 @@ define <2 x float> @v_rcp_v2f32_arcp_afn(<2 x float> %x) { ret <2 x float> %fdiv } -define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) { +define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) #1 { ; GFX6-IEEE-LABEL: v_rcp_v2f32_ulp25: ; GFX6-IEEE: ; %bb.0: ; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2386,7 +2389,7 @@ define <2 x float> @v_rcp_v2f32_ulp25(<2 x float> %x) { ret <2 x float> %fdiv } -define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) { +define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) #1 { ; GCN-LABEL: v_fdiv_v2f32_afn_ulp25: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2417,7 +2420,7 @@ define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) { ret <2 x float> %fdiv } -define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) { +define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) #1 { ; GFX6-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25: ; GFX6-IEEE: ; %bb.0: ; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2507,7 +2510,7 @@ define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) { ret <2 x float> %fdiv } -define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b) { +define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b) #1 { ; GCN-LABEL: v_fdiv_v2f32_arcp_afn_ulp25: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -5229,7 +5232,8 @@ define float @v_fdiv_f32_dynamic_25ulp_nodenorm_y(float %x, float nofpclass(sub) !0 = !{float 2.500000e+00} -attributes #0 = { "denormal-fp-math-f32"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(DEFAULT_MODE, float: dynamic) } +attributes #1 = { denormal_fpenv(DEFAULT_MODE) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN-IEEE: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll index cc2a8ee11f180..3c847d79861c7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll @@ -103,4 +103,4 @@ define float @test_fmamix_constant_bus_violation_vss(i32 %val.0, i32 inreg %val. ret float %fma } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll index 7766b3ad45962..99c3765b0fd1c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll @@ -9,6 +9,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f32_noret_pat(ptr %ptr) { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -25,6 +26,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f32_noret_pat_ieee(ptr %ptr) #0 { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -39,6 +41,7 @@ define float @flat_atomic_fadd_f32_rtn_pat(ptr %ptr, float %data) { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -76,6 +79,7 @@ define <2 x half> @global_atomic_fadd_ret_v2f16_agent_offset(ptr addrspace(1) %p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -90,6 +94,7 @@ define void @global_atomic_fadd_noret_v2f16_agent_offset(ptr addrspace(1) %ptr, ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off offset:1024 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -104,6 +109,7 @@ define <2 x half> @flat_atomic_fadd_ret_v2f16_agent_offset(ptr %ptr, <2 x half> ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v0, v[0:1], v2 offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -118,6 +124,7 @@ define void @flat_atomic_fadd_noret_v2f16_agent_offset(ptr %ptr, <2 x half> %val ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v[0:1], v2 offset:1024 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -127,6 +134,6 @@ define void @flat_atomic_fadd_noret_v2f16_agent_offset(ptr %ptr, <2 x half> %val ret void } -attributes #0 = { "denormal-fp-math-f32"="ieee,ieee" } +attributes #0 = { denormal_fpenv(float: ieee|ieee) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll new file mode 100644 index 0000000000000..317778228b396 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll @@ -0,0 +1,424 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "s_wait" --filter-out "s_delay_alu" --filter-out "endpgm" --filter-out "store" --version 6 +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -new-reg-bank-select < %s | FileCheck %s --check-prefixes=GCN,FAKE16,PREGFX12,PREGFX12-FAKE16 +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -new-reg-bank-select < %s | FileCheck %s --check-prefixes=GCN,PREGFX12,TRUE16 +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -new-reg-bank-select < %s | FileCheck %s --check-prefixes=GCN,FAKE16,PREGFX12,PREGFX12-FAKE16 +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -new-reg-bank-select < %s | FileCheck %s --check-prefixes=GCN,FAKE16,GFX12 + +define amdgpu_ps void @s_fptoui_f16_to_i16(half inreg %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: s_fptoui_f16_to_i16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_u16_f16_e32 v2, s0 +; +; TRUE16-LABEL: s_fptoui_f16_to_i16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_u16_f16_e32 v2.l, s0 + %result = fptoui half %x to i16 + store i16 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_fptosi_f16_to_i16(half inreg %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: s_fptosi_f16_to_i16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_i16_f16_e32 v2, s0 +; +; TRUE16-LABEL: s_fptosi_f16_to_i16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_i16_f16_e32 v2.l, s0 + %result = fptosi half %x to i16 + store i16 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_fptoui_f16_to_i16(half %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: v_fptoui_f16_to_i16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_u16_f16_e32 v0, v0 +; +; TRUE16-LABEL: v_fptoui_f16_to_i16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_u16_f16_e32 v0.l, v0.l + %result = fptoui half %x to i16 + store i16 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_fptosi_f16_to_i16(half %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: v_fptosi_f16_to_i16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_i16_f16_e32 v0, v0 +; +; TRUE16-LABEL: v_fptosi_f16_to_i16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_i16_f16_e32 v0.l, v0.l + %result = fptosi half %x to i16 + store i16 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_fptoui_f16_to_i32(half inreg %x, ptr addrspace(1) %out) { +; PREGFX12-LABEL: s_fptoui_f16_to_i32: +; PREGFX12: ; %bb.0: +; PREGFX12: v_cvt_f32_f16_e32 v2, s0 +; PREGFX12: v_cvt_u32_f32_e32 v2, v2 +; +; GFX12-LABEL: s_fptoui_f16_to_i32: +; GFX12: ; %bb.0: +; GFX12: s_cvt_f32_f16 s0, s0 +; GFX12: s_cvt_u32_f32 s0, s0 +; GFX12: v_mov_b32_e32 v2, s0 + %result = fptoui half %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_fptosi_f16_to_i32(half inreg %x, ptr addrspace(1) %out) { +; PREGFX12-LABEL: s_fptosi_f16_to_i32: +; PREGFX12: ; %bb.0: +; PREGFX12: v_cvt_f32_f16_e32 v2, s0 +; PREGFX12: v_cvt_i32_f32_e32 v2, v2 +; +; GFX12-LABEL: s_fptosi_f16_to_i32: +; GFX12: ; %bb.0: +; GFX12: s_cvt_f32_f16 s0, s0 +; GFX12: s_cvt_i32_f32 s0, s0 +; GFX12: v_mov_b32_e32 v2, s0 + %result = fptosi half %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_fptoui_f16_to_i32(half %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: v_fptoui_f16_to_i32: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_f32_f16_e32 v0, v0 +; FAKE16: v_cvt_u32_f32_e32 v0, v0 +; +; TRUE16-LABEL: v_fptoui_f16_to_i32: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f32_f16_e32 v0, v0.l +; TRUE16: v_cvt_u32_f32_e32 v0, v0 + %result = fptoui half %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_fptosi_f16_to_i32(half %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: v_fptosi_f16_to_i32: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_f32_f16_e32 v0, v0 +; FAKE16: v_cvt_i32_f32_e32 v0, v0 +; +; TRUE16-LABEL: v_fptosi_f16_to_i32: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f32_f16_e32 v0, v0.l +; TRUE16: v_cvt_i32_f32_e32 v0, v0 + %result = fptosi half %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_fptoui_f32_to_i32(float inreg %x, ptr addrspace(1) %out) { +; PREGFX12-LABEL: s_fptoui_f32_to_i32: +; PREGFX12: ; %bb.0: +; PREGFX12: v_cvt_u32_f32_e32 v2, s0 +; +; GFX12-LABEL: s_fptoui_f32_to_i32: +; GFX12: ; %bb.0: +; GFX12: s_cvt_u32_f32 s0, s0 +; GFX12: v_mov_b32_e32 v2, s0 + %result = fptoui float %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_fptosi_f32_to_i32(float inreg %x, ptr addrspace(1) %out) { +; PREGFX12-LABEL: s_fptosi_f32_to_i32: +; PREGFX12: ; %bb.0: +; PREGFX12: v_cvt_i32_f32_e32 v2, s0 +; +; GFX12-LABEL: s_fptosi_f32_to_i32: +; GFX12: ; %bb.0: +; GFX12: s_cvt_i32_f32 s0, s0 +; GFX12: v_mov_b32_e32 v2, s0 + %result = fptosi float %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_fptoui_f32_to_i32(float %x, ptr addrspace(1) %out) { +; GCN-LABEL: v_fptoui_f32_to_i32: +; GCN: ; %bb.0: +; GCN: v_cvt_u32_f32_e32 v0, v0 + %result = fptoui float %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_fptosi_f32_to_i32(float %x, ptr addrspace(1) %out) { +; GCN-LABEL: v_fptosi_f32_to_i32: +; GCN: ; %bb.0: +; GCN: v_cvt_i32_f32_e32 v0, v0 + %result = fptosi float %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_fptoui_f64_to_i32(double inreg %x, ptr addrspace(1) %out) { +; GCN-LABEL: s_fptoui_f64_to_i32: +; GCN: ; %bb.0: +; GCN: v_cvt_u32_f64_e32 v2, s[0:1] + %result = fptoui double %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_fptosi_f64_to_i32(double inreg %x, ptr addrspace(1) %out) { +; GCN-LABEL: s_fptosi_f64_to_i32: +; GCN: ; %bb.0: +; GCN: v_cvt_i32_f64_e32 v2, s[0:1] + %result = fptosi double %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_fptoui_f64_to_i32(double %x, ptr addrspace(1) %out) { +; GCN-LABEL: v_fptoui_f64_to_i32: +; GCN: ; %bb.0: +; GCN: v_cvt_u32_f64_e32 v0, v[0:1] + %result = fptoui double %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_fptosi_f64_to_i32(double %x, ptr addrspace(1) %out) { +; GCN-LABEL: v_fptosi_f64_to_i32: +; GCN: ; %bb.0: +; GCN: v_cvt_i32_f64_e32 v0, v[0:1] + %result = fptosi double %x to i32 + store i32 %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_uitofp_i16_to_f16(i16 inreg %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: s_uitofp_i16_to_f16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_f16_u16_e32 v2, s0 +; +; TRUE16-LABEL: s_uitofp_i16_to_f16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f16_u16_e32 v2.l, s0 + %result = uitofp i16 %x to half + store half %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_sitofp_i16_to_f16(i16 inreg %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: s_sitofp_i16_to_f16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_f16_i16_e32 v2, s0 +; +; TRUE16-LABEL: s_sitofp_i16_to_f16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f16_i16_e32 v2.l, s0 + %result = sitofp i16 %x to half + store half %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_uitofp_i16_to_f16(i16 %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: v_uitofp_i16_to_f16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_f16_u16_e32 v0, v0 +; +; TRUE16-LABEL: v_uitofp_i16_to_f16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f16_u16_e32 v0.l, v0.l + %result = uitofp i16 %x to half + store half %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_sitofp_i16_to_f16(i16 %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: v_sitofp_i16_to_f16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_f16_i16_e32 v0, v0 +; +; TRUE16-LABEL: v_sitofp_i16_to_f16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f16_i16_e32 v0.l, v0.l + %result = sitofp i16 %x to half + store half %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_uitofp_i32_to_f16(i32 inreg %x, ptr addrspace(1) %out) { +; PREGFX12-FAKE16-LABEL: s_uitofp_i32_to_f16: +; PREGFX12-FAKE16: ; %bb.0: +; PREGFX12-FAKE16: v_cvt_f32_u32_e32 v2, s0 +; PREGFX12-FAKE16: v_cvt_f16_f32_e32 v2, v2 +; +; TRUE16-LABEL: s_uitofp_i32_to_f16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f32_u32_e32 v2, s0 +; TRUE16: v_cvt_f16_f32_e32 v2.l, v2 +; +; GFX12-LABEL: s_uitofp_i32_to_f16: +; GFX12: ; %bb.0: +; GFX12: s_cvt_f32_u32 s0, s0 +; GFX12: s_cvt_f16_f32 s0, s0 +; GFX12: v_mov_b32_e32 v2, s0 + %result = uitofp i32 %x to half + store half %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_sitofp_i32_to_f16(i32 inreg %x, ptr addrspace(1) %out) { +; PREGFX12-FAKE16-LABEL: s_sitofp_i32_to_f16: +; PREGFX12-FAKE16: ; %bb.0: +; PREGFX12-FAKE16: v_cvt_f32_i32_e32 v2, s0 +; PREGFX12-FAKE16: v_cvt_f16_f32_e32 v2, v2 +; +; TRUE16-LABEL: s_sitofp_i32_to_f16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f32_i32_e32 v2, s0 +; TRUE16: v_cvt_f16_f32_e32 v2.l, v2 +; +; GFX12-LABEL: s_sitofp_i32_to_f16: +; GFX12: ; %bb.0: +; GFX12: s_cvt_f32_i32 s0, s0 +; GFX12: s_cvt_f16_f32 s0, s0 +; GFX12: v_mov_b32_e32 v2, s0 + %result = sitofp i32 %x to half + store half %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_uitofp_i32_to_f16(i32 %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: v_uitofp_i32_to_f16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_f32_u32_e32 v0, v0 +; FAKE16: v_cvt_f16_f32_e32 v0, v0 +; +; TRUE16-LABEL: v_uitofp_i32_to_f16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f32_u32_e32 v0, v0 +; TRUE16: v_cvt_f16_f32_e32 v0.l, v0 + %result = uitofp i32 %x to half + store half %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_sitofp_i32_to_f16(i32 %x, ptr addrspace(1) %out) { +; FAKE16-LABEL: v_sitofp_i32_to_f16: +; FAKE16: ; %bb.0: +; FAKE16: v_cvt_f32_i32_e32 v0, v0 +; FAKE16: v_cvt_f16_f32_e32 v0, v0 +; +; TRUE16-LABEL: v_sitofp_i32_to_f16: +; TRUE16: ; %bb.0: +; TRUE16: v_cvt_f32_i32_e32 v0, v0 +; TRUE16: v_cvt_f16_f32_e32 v0.l, v0 + %result = sitofp i32 %x to half + store half %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_uitofp_i32_to_f32(i32 inreg %x, ptr addrspace(1) %out) { +; PREGFX12-LABEL: s_uitofp_i32_to_f32: +; PREGFX12: ; %bb.0: +; PREGFX12: v_cvt_f32_u32_e32 v2, s0 +; +; GFX12-LABEL: s_uitofp_i32_to_f32: +; GFX12: ; %bb.0: +; GFX12: s_cvt_f32_u32 s0, s0 +; GFX12: v_mov_b32_e32 v2, s0 + %result = uitofp i32 %x to float + store float %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_sitofp_i32_to_f32(i32 inreg %x, ptr addrspace(1) %out) { +; PREGFX12-LABEL: s_sitofp_i32_to_f32: +; PREGFX12: ; %bb.0: +; PREGFX12: v_cvt_f32_i32_e32 v2, s0 +; +; GFX12-LABEL: s_sitofp_i32_to_f32: +; GFX12: ; %bb.0: +; GFX12: s_cvt_f32_i32 s0, s0 +; GFX12: v_mov_b32_e32 v2, s0 + %result = sitofp i32 %x to float + store float %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_uitofp_i32_to_f32(i32 %x, ptr addrspace(1) %out) { +; GCN-LABEL: v_uitofp_i32_to_f32: +; GCN: ; %bb.0: +; GCN: v_cvt_f32_u32_e32 v0, v0 + %result = uitofp i32 %x to float + store float %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_sitofp_i32_to_f32(i32 %x, ptr addrspace(1) %out) { +; GCN-LABEL: v_sitofp_i32_to_f32: +; GCN: ; %bb.0: +; GCN: v_cvt_f32_i32_e32 v0, v0 + %result = sitofp i32 %x to float + store float %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_uitofp_i32_to_f64(i32 inreg %x, ptr addrspace(1) %out) { +; GCN-LABEL: s_uitofp_i32_to_f64: +; GCN: ; %bb.0: +; GCN: v_cvt_f64_u32_e32 v[2:3], s0 + %result = uitofp i32 %x to double + store double %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @s_sitofp_i32_to_f64(i32 inreg %x, ptr addrspace(1) %out) { +; GCN-LABEL: s_sitofp_i32_to_f64: +; GCN: ; %bb.0: +; GCN: v_cvt_f64_i32_e32 v[2:3], s0 + %result = sitofp i32 %x to double + store double %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_uitofp_i32_to_f64(i32 %x, ptr addrspace(1) %out) { +; GCN-LABEL: v_uitofp_i32_to_f64: +; GCN: ; %bb.0: +; GCN: v_cvt_f64_u32_e32 v[3:4], v0 + %result = uitofp i32 %x to double + store double %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @v_sitofp_i32_to_f64(i32 %x, ptr addrspace(1) %out) { +; GCN-LABEL: v_sitofp_i32_to_f64: +; GCN: ; %bb.0: +; GCN: v_cvt_f64_i32_e32 v[3:4], v0 + %result = sitofp i32 %x to double + store double %result, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps float @fpext_hif16_to_32(<2 x half> inreg %val) { +; PREGFX12-LABEL: fpext_hif16_to_32: +; PREGFX12: ; %bb.0: +; PREGFX12: s_lshr_b32 s0, s0, 16 +; PREGFX12: v_cvt_f32_f16_e32 v0, s0 +; PREGFX12: ; return to shader part epilog +; +; GFX12-LABEL: fpext_hif16_to_32: +; GFX12: ; %bb.0: +; GFX12: s_cvt_hi_f32_f16 s0, s0 +; GFX12: v_mov_b32_e32 v0, s0 +; GFX12: ; return to shader part epilog + %hielt = extractelement <2 x half> %val, i32 1 + %res = fpext half %hielt to float + ret float %res +} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll index 62ed4bbfe54e9..2bdbdb93d9141 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll @@ -1490,7 +1490,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat(ptr addrspace(1) %pt ; GFX90A-NEXT: v_mul_f64 v[0:1], v[0:1], 4.0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: buffer_wbl2 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: global_atomic_add_f64 v2, v[0:1], s[2:3] ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1513,7 +1513,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat(ptr addrspace(1) %pt ; GFX942-NEXT: v_mul_f64 v[0:1], v[0:1], 4.0 ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[2:3] sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1587,7 +1587,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent(ptr addrspace( ; GFX942-NEXT: v_mul_f64 v[0:1], v[0:1], 4.0 ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1640,7 +1640,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_system(ptr addrspace ; GFX90A-NEXT: v_mul_f64 v[0:1], v[0:1], 4.0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: buffer_wbl2 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: global_atomic_add_f64 v2, v[0:1], s[2:3] ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1663,7 +1663,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_system(ptr addrspace ; GFX942-NEXT: v_mul_f64 v[0:1], v[0:1], 4.0 ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[2:3] sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1737,7 +1737,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_flush(ptr addrspace( ; GFX942-NEXT: v_mul_f64 v[0:1], v[0:1], 4.0 ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1781,6 +1781,7 @@ define double @global_atomic_fadd_f64_rtn_pat(ptr addrspace(1) %ptr, double %dat ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1792,6 +1793,7 @@ define double @global_atomic_fadd_f64_rtn_pat(ptr addrspace(1) %ptr, double %dat ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1831,6 +1833,7 @@ define double @global_atomic_fadd_f64_rtn_pat_agent(ptr addrspace(1) %ptr, doubl ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1861,6 +1864,7 @@ define double @global_atomic_fadd_f64_rtn_pat_system(ptr addrspace(1) %ptr, doub ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1872,6 +1876,7 @@ define double @global_atomic_fadd_f64_rtn_pat_system(ptr addrspace(1) %ptr, doub ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1932,7 +1937,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent_safe(ptr addrs ; GFX942-NEXT: v_mul_f64 v[0:1], v[0:1], 4.0 ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1978,6 +1983,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat(ptr %ptr) #1 { ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_add_f64 v[0:1], v[2:3] ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1991,6 +1997,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[2:3] sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2035,6 +2042,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2068,6 +2076,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_system(ptr %ptr) #1 { ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_add_f64 v[0:1], v[2:3] ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2081,6 +2090,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_system(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[2:3] sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2112,6 +2122,7 @@ define double @flat_atomic_fadd_f64_rtn_pat(ptr %ptr) #1 { ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2123,6 +2134,7 @@ define double @flat_atomic_fadd_f64_rtn_pat(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2162,6 +2174,7 @@ define double @flat_atomic_fadd_f64_rtn_pat_agent(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2192,6 +2205,7 @@ define double @flat_atomic_fadd_f64_rtn_pat_system(ptr %ptr) #1 { ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2204,6 +2218,7 @@ define double @flat_atomic_fadd_f64_rtn_pat_system(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2248,6 +2263,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent_safe(ptr %ptr) { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2502,9 +2518,9 @@ main_body: ret double %ret } -attributes #0 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(preservesign) } attributes #1 = { nounwind } -attributes #2 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #2 = { nounwind denormal_fpenv(preservesign) } !0 = !{} !1 = !{i32 5, i32 6} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll index 990153ebce243..d73b56aab8505 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll @@ -137,34 +137,20 @@ define amdgpu_ps void @fpext_f16_to_f64_div(half %a, ptr addrspace(1) %ptr) { } define amdgpu_ps <2 x float> @fpext_v2f16_to_v2f32_uniform(<2 x half> inreg %a) { -; GFX11-FAKE16-LABEL: fpext_v2f16_to_v2f32_uniform: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16 -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, s0 -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, s1 -; GFX11-FAKE16-NEXT: ; return to shader part epilog -; -; GFX11-TRUE16-LABEL: fpext_v2f16_to_v2f32_uniform: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, s0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0 -; GFX11-TRUE16-NEXT: ; return to shader part epilog -; -; GFX12-FAKE16-LABEL: fpext_v2f16_to_v2f32_uniform: -; GFX12-FAKE16: ; %bb.0: -; GFX12-FAKE16-NEXT: s_cvt_f32_f16 s1, s0 -; GFX12-FAKE16-NEXT: s_cvt_hi_f32_f16 s0, s0 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0 -; GFX12-FAKE16-NEXT: ; return to shader part epilog +; GFX11-LABEL: fpext_v2f16_to_v2f32_uniform: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_lshr_b32 s1, s0, 16 +; GFX11-NEXT: v_cvt_f32_f16_e32 v0, s0 +; GFX11-NEXT: v_cvt_f32_f16_e32 v1, s1 +; GFX11-NEXT: ; return to shader part epilog ; -; GFX12-TRUE16-LABEL: fpext_v2f16_to_v2f32_uniform: -; GFX12-TRUE16: ; %bb.0: -; GFX12-TRUE16-NEXT: s_cvt_f32_f16 s0, s0 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s0 -; GFX12-TRUE16-NEXT: ; return to shader part epilog +; GFX12-LABEL: fpext_v2f16_to_v2f32_uniform: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_cvt_f32_f16 s1, s0 +; GFX12-NEXT: s_cvt_hi_f32_f16 s0, s0 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GFX12-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0 +; GFX12-NEXT: ; return to shader part epilog %result = fpext <2 x half> %a to <2 x float> ret <2 x float> %result } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll index 62e97279b606a..61b87d19c6b6a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll @@ -3548,5 +3548,5 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i ret void } -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll index 6ad73601859d1..4fefef5e66155 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll @@ -664,8 +664,8 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in ; GFX6-NEXT: s_lshr_b32 s1, s1, 1 ; GFX6-NEXT: s_lshl_b32 s2, s3, s2 ; GFX6-NEXT: s_lshr_b32 s1, s1, s4 -; GFX6-NEXT: s_or_b32 s1, s2, s1 -; GFX6-NEXT: s_and_b32 s1, s1, 0xff +; GFX6-NEXT: s_or_b32 s2, s2, s1 +; GFX6-NEXT: s_and_b32 s1, s2, 0xff ; GFX6-NEXT: s_and_b32 s0, s0, 0xff ; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_or_b32 s0, s0, s1 @@ -954,17 +954,17 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; GFX6-NEXT: s_and_b32 s4, s8, 7 ; GFX6-NEXT: s_andn2_b32 s6, 7, s8 ; GFX6-NEXT: s_lshr_b32 s1, s1, 25 -; GFX6-NEXT: s_and_b32 s2, s2, 0xff ; GFX6-NEXT: s_lshl_b32 s4, s5, s4 ; GFX6-NEXT: s_lshr_b32 s1, s1, s6 +; GFX6-NEXT: s_or_b32 s4, s4, s1 +; GFX6-NEXT: s_and_b32 s1, s2, 0xff ; GFX6-NEXT: s_and_b32 s0, s0, 0xff -; GFX6-NEXT: s_lshl_b32 s2, s2, 8 -; GFX6-NEXT: s_or_b32 s1, s4, s1 -; GFX6-NEXT: s_or_b32 s0, s0, s2 -; GFX6-NEXT: s_and_b32 s2, s3, 0xff -; GFX6-NEXT: s_lshl_b32 s2, s2, 16 -; GFX6-NEXT: s_and_b32 s1, s1, 0xff -; GFX6-NEXT: s_or_b32 s0, s0, s2 +; GFX6-NEXT: s_lshl_b32 s1, s1, 8 +; GFX6-NEXT: s_or_b32 s0, s0, s1 +; GFX6-NEXT: s_and_b32 s1, s3, 0xff +; GFX6-NEXT: s_lshl_b32 s1, s1, 16 +; GFX6-NEXT: s_or_b32 s0, s0, s1 +; GFX6-NEXT: s_and_b32 s1, s4, 0xff ; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog @@ -3689,8 +3689,8 @@ define amdgpu_ps i32 @s_fshl_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, < ; GFX8-NEXT: s_lshr_b32 s1, s1, 17 ; GFX8-NEXT: s_lshl_b32 s2, s3, s2 ; GFX8-NEXT: s_lshr_b32 s1, s1, s4 -; GFX8-NEXT: s_or_b32 s1, s2, s1 -; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX8-NEXT: s_or_b32 s2, s2, s1 +; GFX8-NEXT: s_and_b32 s1, 0xffff, s2 ; GFX8-NEXT: s_and_b32 s0, 0xffff, s0 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16 ; GFX8-NEXT: s_or_b32 s0, s0, s1 @@ -4268,15 +4268,15 @@ define amdgpu_ps i48 @s_fshl_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, < ; GFX8-NEXT: s_lshr_b32 s2, s2, 17 ; GFX8-NEXT: s_lshl_b32 s4, s6, s4 ; GFX8-NEXT: s_lshr_b32 s2, s2, s7 -; GFX8-NEXT: s_and_b32 s3, 0xffff, s3 -; GFX8-NEXT: s_or_b32 s2, s4, s2 -; GFX8-NEXT: s_and_b32 s4, s5, 15 +; GFX8-NEXT: s_or_b32 s4, s4, s2 +; GFX8-NEXT: s_and_b32 s2, s5, 15 +; GFX8-NEXT: s_lshl_b32 s1, s1, s2 +; GFX8-NEXT: s_and_b32 s2, 0xffff, s3 ; GFX8-NEXT: s_andn2_b32 s5, 15, s5 -; GFX8-NEXT: s_lshr_b32 s3, s3, 1 -; GFX8-NEXT: s_lshl_b32 s1, s1, s4 -; GFX8-NEXT: s_lshr_b32 s3, s3, s5 -; GFX8-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX8-NEXT: s_or_b32 s1, s1, s3 +; GFX8-NEXT: s_lshr_b32 s2, s2, 1 +; GFX8-NEXT: s_lshr_b32 s2, s2, s5 +; GFX8-NEXT: s_or_b32 s1, s1, s2 +; GFX8-NEXT: s_and_b32 s2, 0xffff, s4 ; GFX8-NEXT: s_and_b32 s0, 0xffff, s0 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16 ; GFX8-NEXT: s_or_b32 s0, s0, s2 @@ -4614,29 +4614,29 @@ define amdgpu_ps <2 x i32> @s_fshl_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX8-NEXT: s_lshr_b32 s2, s2, 17 ; GFX8-NEXT: s_lshl_b32 s4, s6, s4 ; GFX8-NEXT: s_lshr_b32 s2, s2, s8 -; GFX8-NEXT: s_or_b32 s2, s4, s2 -; GFX8-NEXT: s_and_b32 s4, s5, 15 +; GFX8-NEXT: s_or_b32 s4, s4, s2 +; GFX8-NEXT: s_and_b32 s2, s5, 15 ; GFX8-NEXT: s_lshr_b32 s7, s1, 16 -; GFX8-NEXT: s_lshl_b32 s1, s1, s4 -; GFX8-NEXT: s_and_b32 s4, 0xffff, s3 +; GFX8-NEXT: s_lshl_b32 s1, s1, s2 +; GFX8-NEXT: s_and_b32 s2, 0xffff, s3 ; GFX8-NEXT: s_lshr_b32 s9, s5, 16 ; GFX8-NEXT: s_andn2_b32 s5, 15, s5 -; GFX8-NEXT: s_lshr_b32 s4, s4, 1 -; GFX8-NEXT: s_lshr_b32 s4, s4, s5 -; GFX8-NEXT: s_or_b32 s1, s1, s4 -; GFX8-NEXT: s_and_b32 s4, s9, 15 +; GFX8-NEXT: s_lshr_b32 s2, s2, 1 +; GFX8-NEXT: s_lshr_b32 s2, s2, s5 +; GFX8-NEXT: s_or_b32 s1, s1, s2 +; GFX8-NEXT: s_and_b32 s2, s9, 15 ; GFX8-NEXT: s_andn2_b32 s5, 15, s9 ; GFX8-NEXT: s_lshr_b32 s3, s3, 17 -; GFX8-NEXT: s_lshl_b32 s4, s7, s4 +; GFX8-NEXT: s_lshl_b32 s2, s7, s2 ; GFX8-NEXT: s_lshr_b32 s3, s3, s5 +; GFX8-NEXT: s_or_b32 s2, s2, s3 +; GFX8-NEXT: s_and_b32 s3, 0xffff, s4 ; GFX8-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX8-NEXT: s_or_b32 s3, s4, s3 ; GFX8-NEXT: s_and_b32 s0, 0xffff, s0 -; GFX8-NEXT: s_lshl_b32 s2, s2, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s2 -; GFX8-NEXT: s_and_b32 s2, 0xffff, s3 +; GFX8-NEXT: s_lshl_b32 s3, s3, 16 ; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16 +; GFX8-NEXT: s_or_b32 s0, s0, s3 ; GFX8-NEXT: s_or_b32 s1, s1, s2 ; GFX8-NEXT: ; return to shader part epilog ; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll index 5afab53628c34..bc6a2e7c43256 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll @@ -665,8 +665,8 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in ; GFX6-NEXT: s_bfe_u32 s1, s1, 0x80008 ; GFX6-NEXT: s_lshl_b32 s3, s3, s4 ; GFX6-NEXT: s_lshr_b32 s1, s1, s2 -; GFX6-NEXT: s_or_b32 s1, s3, s1 -; GFX6-NEXT: s_and_b32 s1, s1, 0xff +; GFX6-NEXT: s_or_b32 s3, s3, s1 +; GFX6-NEXT: s_and_b32 s1, s3, 0xff ; GFX6-NEXT: s_and_b32 s0, s0, 0xff ; GFX6-NEXT: s_lshl_b32 s1, s1, 8 ; GFX6-NEXT: s_or_b32 s0, s0, s1 @@ -946,28 +946,28 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in ; GFX6-NEXT: s_bfe_u32 s7, s1, 0x80008 ; GFX6-NEXT: s_lshr_b32 s2, s7, s2 ; GFX6-NEXT: s_lshr_b32 s6, s1, 24 -; GFX6-NEXT: s_or_b32 s2, s3, s2 -; GFX6-NEXT: s_and_b32 s3, s8, 7 +; GFX6-NEXT: s_or_b32 s3, s3, s2 +; GFX6-NEXT: s_and_b32 s2, s8, 7 ; GFX6-NEXT: s_andn2_b32 s7, 7, s8 ; GFX6-NEXT: s_lshl_b32 s4, s4, 1 ; GFX6-NEXT: s_bfe_u32 s1, s1, 0x80010 ; GFX6-NEXT: s_lshl_b32 s4, s4, s7 -; GFX6-NEXT: s_lshr_b32 s1, s1, s3 -; GFX6-NEXT: s_or_b32 s1, s4, s1 -; GFX6-NEXT: s_and_b32 s3, s9, 7 -; GFX6-NEXT: s_andn2_b32 s4, 7, s9 +; GFX6-NEXT: s_lshr_b32 s1, s1, s2 +; GFX6-NEXT: s_or_b32 s4, s4, s1 +; GFX6-NEXT: s_and_b32 s1, s9, 7 +; GFX6-NEXT: s_andn2_b32 s2, 7, s9 ; GFX6-NEXT: s_lshl_b32 s5, s5, 1 -; GFX6-NEXT: s_and_b32 s2, s2, 0xff -; GFX6-NEXT: s_lshl_b32 s4, s5, s4 -; GFX6-NEXT: s_lshr_b32 s3, s6, s3 +; GFX6-NEXT: s_lshl_b32 s2, s5, s2 +; GFX6-NEXT: s_lshr_b32 s1, s6, s1 +; GFX6-NEXT: s_or_b32 s2, s2, s1 +; GFX6-NEXT: s_and_b32 s1, s3, 0xff ; GFX6-NEXT: s_and_b32 s0, s0, 0xff -; GFX6-NEXT: s_lshl_b32 s2, s2, 8 -; GFX6-NEXT: s_and_b32 s1, s1, 0xff -; GFX6-NEXT: s_or_b32 s3, s4, s3 -; GFX6-NEXT: s_or_b32 s0, s0, s2 +; GFX6-NEXT: s_lshl_b32 s1, s1, 8 +; GFX6-NEXT: s_or_b32 s0, s0, s1 +; GFX6-NEXT: s_and_b32 s1, s4, 0xff ; GFX6-NEXT: s_lshl_b32 s1, s1, 16 ; GFX6-NEXT: s_or_b32 s0, s0, s1 -; GFX6-NEXT: s_and_b32 s1, s3, 0xff +; GFX6-NEXT: s_and_b32 s1, s2, 0xff ; GFX6-NEXT: s_lshl_b32 s1, s1, 24 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: ; return to shader part epilog @@ -3443,8 +3443,8 @@ define amdgpu_ps i32 @s_fshr_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs, < ; GFX8-NEXT: s_lshl_b32 s3, s3, 1 ; GFX8-NEXT: s_lshl_b32 s2, s3, s2 ; GFX8-NEXT: s_lshr_b32 s1, s4, s1 -; GFX8-NEXT: s_or_b32 s1, s2, s1 -; GFX8-NEXT: s_and_b32 s1, 0xffff, s1 +; GFX8-NEXT: s_or_b32 s2, s2, s1 +; GFX8-NEXT: s_and_b32 s1, 0xffff, s2 ; GFX8-NEXT: s_and_b32 s0, 0xffff, s0 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16 ; GFX8-NEXT: s_or_b32 s0, s0, s1 @@ -4026,15 +4026,15 @@ define amdgpu_ps i48 @s_fshr_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs, < ; GFX8-NEXT: s_lshl_b32 s6, s6, 1 ; GFX8-NEXT: s_lshl_b32 s4, s6, s4 ; GFX8-NEXT: s_lshr_b32 s2, s7, s2 -; GFX8-NEXT: s_or_b32 s2, s4, s2 -; GFX8-NEXT: s_and_b32 s4, s5, 15 +; GFX8-NEXT: s_or_b32 s4, s4, s2 +; GFX8-NEXT: s_and_b32 s2, s5, 15 ; GFX8-NEXT: s_andn2_b32 s5, 15, s5 ; GFX8-NEXT: s_lshl_b32 s1, s1, 1 ; GFX8-NEXT: s_and_b32 s3, 0xffff, s3 ; GFX8-NEXT: s_lshl_b32 s1, s1, s5 -; GFX8-NEXT: s_lshr_b32 s3, s3, s4 -; GFX8-NEXT: s_and_b32 s2, 0xffff, s2 -; GFX8-NEXT: s_or_b32 s1, s1, s3 +; GFX8-NEXT: s_lshr_b32 s2, s3, s2 +; GFX8-NEXT: s_or_b32 s1, s1, s2 +; GFX8-NEXT: s_and_b32 s2, 0xffff, s4 ; GFX8-NEXT: s_and_b32 s0, 0xffff, s0 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16 ; GFX8-NEXT: s_or_b32 s0, s0, s2 @@ -4376,8 +4376,8 @@ define amdgpu_ps <2 x i32> @s_fshr_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg % ; GFX8-NEXT: s_lshl_b32 s6, s6, 1 ; GFX8-NEXT: s_lshl_b32 s4, s6, s4 ; GFX8-NEXT: s_lshr_b32 s2, s7, s2 -; GFX8-NEXT: s_or_b32 s2, s4, s2 -; GFX8-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX8-NEXT: s_or_b32 s4, s4, s2 +; GFX8-NEXT: s_and_b32 s2, 0xffff, s4 ; GFX8-NEXT: s_and_b32 s0, 0xffff, s0 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16 ; GFX8-NEXT: s_or_b32 s0, s0, s2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll index 333207a24fe7d..10cae04fe7636 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll @@ -1317,19 +1317,19 @@ define amdgpu_kernel void @pointer_in_struct_argument({ptr addrspace(3), ptr add ; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9 ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64) - ; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (s32) from constant-pool, align 16, addrspace 4) + ; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p3) from constant-pool, align 16, addrspace 4) ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64) - ; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (s64) from constant-pool, addrspace 4) + ; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (p1) from constant-pool, addrspace 4) ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; HSA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64) ; HSA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (s8) from constant-pool, align 16, addrspace 4) ; HSA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; HSA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64) - ; HSA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (s32) from constant-pool, align 8, addrspace 4) + ; HSA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (p3) from constant-pool, align 8, addrspace 4) ; HSA-VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; HSA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](s64) - ; HSA-VI-NEXT: [[LOAD4:%[0-9]+]]:_(p1234) = G_LOAD [[PTR_ADD4]](p4) :: (dereferenceable invariant load (s64) from constant-pool, addrspace 4) + ; HSA-VI-NEXT: [[LOAD4:%[0-9]+]]:_(p1234) = G_LOAD [[PTR_ADD4]](p4) :: (dereferenceable invariant load (p1234) from constant-pool, addrspace 4) ; HSA-VI-NEXT: [[C5:%[0-9]+]]:_(p1) = G_CONSTANT i64 0 ; HSA-VI-NEXT: G_STORE [[LOAD]](p3), [[C5]](p1) :: (volatile store (p3) into `ptr addrspace(1) null`, addrspace 1) ; HSA-VI-NEXT: G_STORE [[LOAD1]](p1), [[C5]](p1) :: (volatile store (p1) into `ptr addrspace(1) null`, addrspace 1) @@ -1345,19 +1345,19 @@ define amdgpu_kernel void @pointer_in_struct_argument({ptr addrspace(3), ptr add ; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36 ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64) - ; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (s32) from constant-pool, addrspace 4) + ; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (p3) from constant-pool, addrspace 4) ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 44 ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64) - ; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (s64) from constant-pool, align 4, addrspace 4) + ; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(p1) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (p1) from constant-pool, align 4, addrspace 4) ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 52 ; LEGACY-MESA-VI-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64) ; LEGACY-MESA-VI-NEXT: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[PTR_ADD2]](p4) :: (dereferenceable invariant load (s8) from constant-pool, align 4, addrspace 4) ; LEGACY-MESA-VI-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 60 ; LEGACY-MESA-VI-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C3]](s64) - ; LEGACY-MESA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (s32) from constant-pool, addrspace 4) + ; LEGACY-MESA-VI-NEXT: [[LOAD3:%[0-9]+]]:_(p3) = G_LOAD [[PTR_ADD3]](p4) :: (dereferenceable invariant load (p3) from constant-pool, addrspace 4) ; LEGACY-MESA-VI-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 68 ; LEGACY-MESA-VI-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C4]](s64) - ; LEGACY-MESA-VI-NEXT: [[LOAD4:%[0-9]+]]:_(p1234) = G_LOAD [[PTR_ADD4]](p4) :: (dereferenceable invariant load (s64) from constant-pool, align 4, addrspace 4) + ; LEGACY-MESA-VI-NEXT: [[LOAD4:%[0-9]+]]:_(p1234) = G_LOAD [[PTR_ADD4]](p4) :: (dereferenceable invariant load (p1234) from constant-pool, align 4, addrspace 4) ; LEGACY-MESA-VI-NEXT: [[C5:%[0-9]+]]:_(p1) = G_CONSTANT i64 0 ; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](p3), [[C5]](p1) :: (volatile store (p3) into `ptr addrspace(1) null`, addrspace 1) ; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD1]](p1), [[C5]](p1) :: (volatile store (p1) into `ptr addrspace(1) null`, addrspace 1) @@ -2071,10 +2071,10 @@ define amdgpu_kernel void @v2p1i8_in_struct_arg({ <2 x ptr addrspace(1)>, <2 x p ; HSA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9 ; HSA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; HSA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64) - ; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x s64>) from constant-pool, addrspace 4) + ; HSA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x p1>) from constant-pool, addrspace 4) ; HSA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; HSA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64) - ; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x s32>) from constant-pool, align 16, addrspace 4) + ; HSA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x p3>) from constant-pool, align 16, addrspace 4) ; HSA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; HSA-VI-NEXT: G_STORE [[LOAD]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) poison`, addrspace 1) ; HSA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 @@ -2089,10 +2089,10 @@ define amdgpu_kernel void @v2p1i8_in_struct_arg({ <2 x ptr addrspace(1)>, <2 x p ; LEGACY-MESA-VI-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 ; LEGACY-MESA-VI-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 36 ; LEGACY-MESA-VI-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64) - ; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x s64>) from constant-pool, align 4, addrspace 4) + ; LEGACY-MESA-VI-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (<2 x p1>) from constant-pool, align 4, addrspace 4) ; LEGACY-MESA-VI-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 52 ; LEGACY-MESA-VI-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C1]](s64) - ; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x s32>) from constant-pool, align 4, addrspace 4) + ; LEGACY-MESA-VI-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x p3>) = G_LOAD [[PTR_ADD1]](p4) :: (dereferenceable invariant load (<2 x p3>) from constant-pool, align 4, addrspace 4) ; LEGACY-MESA-VI-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; LEGACY-MESA-VI-NEXT: G_STORE [[LOAD]](<2 x p1>), [[DEF]](p1) :: (store (<2 x p1>) into `ptr addrspace(1) poison`, addrspace 1) ; LEGACY-MESA-VI-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll index 6846137272ec6..aa25294ba17b6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll @@ -820,8 +820,8 @@ define amdgpu_kernel void @test_div_fmas_f64(ptr addrspace(1) %out, double %a, d ; GFX11_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX11_W64-NEXT: s_and_b32 s8, 1, s8 ; GFX11_W64-NEXT: v_mov_b32_e32 v0, s4 -; GFX11_W64-NEXT: v_mov_b32_e32 v2, s6 ; GFX11_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8 +; GFX11_W64-NEXT: v_mov_b32_e32 v2, s6 ; GFX11_W64-NEXT: v_mov_b32_e32 v1, s5 ; GFX11_W64-NEXT: v_mov_b32_e32 v3, s7 ; GFX11_W64-NEXT: v_div_fmas_f64 v[0:1], s[2:3], v[0:1], v[2:3] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll index 34bf3c21a8c71..e1c2b797390c2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll @@ -636,4 +636,4 @@ declare float @llvm.amdgcn.fmul.legacy(float, float) #1 attributes #0 = { nounwind readnone speculatable willreturn } attributes #1 = { nounwind readnone speculatable } -attributes #2 = { "denormal-fp-math-f32"="preserve-sign" } +attributes #2 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll index 498ddfcc31dd8..c9d4fd2bdd36e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s ; Natural mapping define amdgpu_ps half @raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) { @@ -430,6 +430,197 @@ define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffs ret <4 x half> %val } +define amdgpu_ps half @raw_buffer_load_format_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) { + ; PACKED-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; PACKED-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (s16), align 1, addrspace 8) + ; PACKED-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_OFFEN]] + ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; UNPACKED-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; UNPACKED-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (s16), align 1, addrspace 8) + ; UNPACKED-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]] + ; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX12-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (s16), align 1, addrspace 8) + ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] + ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %val = call half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) + ret half %val +} + +define amdgpu_ps <2 x half> @raw_buffer_load_format_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) { + ; PACKED-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; PACKED-NEXT: [[BUFFER_LOAD_FORMAT_D16_XY_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x s16>), align 1, addrspace 8) + ; PACKED-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_OFFEN]] + ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; UNPACKED-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; UNPACKED-NEXT: [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x s16>), align 1, addrspace 8) + ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub0 + ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub1 + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; UNPACKED-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 + ; UNPACKED-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_1]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; UNPACKED-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_AND_B32_1]], [[S_MOV_B32_1]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[S_LSHL_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: $vgpr0 = COPY [[S_OR_B32_]] + ; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX12-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x s16>), align 1, addrspace 8) + ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN]] + ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %val = call <2 x half> @llvm.amdgcn.raw.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) + ret <2 x half> %val +} + +define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) { + ; PACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; PACKED-NEXT: [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s16>), align 1, addrspace 8) + ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub0 + ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub1 + ; PACKED-NEXT: $vgpr0 = COPY [[COPY7]] + ; PACKED-NEXT: $vgpr1 = COPY [[COPY8]] + ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; UNPACKED-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; UNPACKED-NEXT: [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s16>), align 1, addrspace 8) + ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub0 + ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub1 + ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub2 + ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub3 + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; UNPACKED-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 + ; UNPACKED-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_1]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; UNPACKED-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_AND_B32_1]], [[S_MOV_B32_1]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[S_LSHL_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_2]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_3]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_LSHL_B32_1:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_AND_B32_3]], [[S_MOV_B32_1]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_2]], [[S_LSHL_B32_1]], implicit-def dead $scc + ; UNPACKED-NEXT: $vgpr0 = COPY [[S_OR_B32_]] + ; UNPACKED-NEXT: $vgpr1 = COPY [[S_OR_B32_1]] + ; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX12-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s16>), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub0 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub1 + ; GFX12-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX12-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + %val = call <4 x half> @llvm.amdgcn.raw.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) + ret <4 x half> %val +} + declare half @llvm.amdgcn.raw.buffer.load.format.f16(<4 x i32>, i32, i32, i32 immarg) #0 declare <2 x half> @llvm.amdgcn.raw.buffer.load.format.v2f16(<4 x i32>, i32, i32, i32 immarg) #0 declare <3 x half> @llvm.amdgcn.raw.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32 immarg) #0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll index 4784ac5de17b0..4838c9c474b09 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX67,GFX6 -; RUN: llc -global-isel -mcpu=hawaii -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX67,GFX7 -; RUN: llc -global-isel -mcpu=fiji -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX8 -; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910 -; RUN: llc -global-isel -mcpu=gfx1010 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910 -; RUN: llc -global-isel -mcpu=gfx1100 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11 -; RUN: llc -global-isel -mcpu=gfx1200 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1200 -; RUN: llc -global-isel -mcpu=gfx1250 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1250 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=tahiti -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX67,GFX6 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=hawaii -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX67,GFX7 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=fiji -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX8 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx900 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1010 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1100 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1200 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1200 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1250 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1250 define amdgpu_ps void @raw_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %data_addr, ptr addrspace(1) %tfe_addr) { ; GFX67-LABEL: name: raw_buffer_load_i8_tfe @@ -645,13 +645,16 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX67-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub0 ; GFX67-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub1 ; GFX67-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub2 - ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX67-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] ; GFX67-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX67-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX67-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX67-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX67-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY11]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX67-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -680,8 +683,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub0 ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub1 ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub2 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX8-NEXT: FLAT_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -705,8 +711,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub0 ; GFX910-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub1 ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub2 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -730,8 +739,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub0 ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub1 ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub2 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -754,8 +766,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub0 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub1 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub2 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -778,8 +793,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub0 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub1 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub2 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <2 x i32>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v2i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0) @@ -811,13 +829,16 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX67-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub0 ; GFX67-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub1 ; GFX67-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub2 - ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX67-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] ; GFX67-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX67-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX67-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX67-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX67-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY11]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX67-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -846,8 +867,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub0 ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub1 ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub2 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX8-NEXT: FLAT_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -871,8 +895,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub0 ; GFX910-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub1 ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub2 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -896,8 +923,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub0 ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub1 ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_OFFSET]].sub2 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -920,8 +950,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub0 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub1 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub2 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -944,8 +977,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub0 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub1 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET]].sub2 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <2 x float>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v2f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0) @@ -978,26 +1014,32 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub0_sub1 - ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vreg_64 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2_sub3 + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub2_sub3 + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[COPY12]] ; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE3]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY12]], [[REG_SEQUENCE1]], [[REG_SEQUENCE4]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY14]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX6-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_1]], %subreg.sub0_sub1, [[REG_SEQUENCE5]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY10]], [[REG_SEQUENCE1]], [[REG_SEQUENCE6]], 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.data_addr + 8, align 8, basealign 16, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_1]], %subreg.sub0_sub1, [[REG_SEQUENCE6]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY10]], [[REG_SEQUENCE1]], [[REG_SEQUENCE7]], 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.data_addr + 8, align 8, basealign 16, addrspace 1) ; GFX6-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_5]], %subreg.sub0, [[S_MOV_B32_6]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_5]], %subreg.sub0, [[S_MOV_B32_6]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_2]], %subreg.sub0_sub1, [[REG_SEQUENCE7]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY11]], [[REG_SEQUENCE2]], [[REG_SEQUENCE8]], 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE9:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_2]], %subreg.sub0_sub1, [[REG_SEQUENCE8]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY11]], [[REG_SEQUENCE2]], [[REG_SEQUENCE9]], 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX7-LABEL: name: raw_buffer_load_v3i32_tfe @@ -1021,13 +1063,17 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX7-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX7-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] ; GFX7-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX7-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX7-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX7-NEXT: BUFFER_STORE_DWORDX3_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX7-NEXT: BUFFER_STORE_DWORDX3_ADDR64 [[COPY12]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX7-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX7-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX7-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -1057,8 +1103,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -1083,8 +1133,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -1109,8 +1163,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -1134,8 +1192,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub1 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub2 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub3 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -1159,8 +1221,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub1 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub2 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub3 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vreg_96_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <3 x i32>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0) @@ -1193,26 +1259,32 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub0_sub1 - ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vreg_64 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2_sub3 + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX6-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub2_sub3 + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[COPY12]] ; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE3]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY12]], [[REG_SEQUENCE1]], [[REG_SEQUENCE4]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY14]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX6-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_1]], %subreg.sub0_sub1, [[REG_SEQUENCE5]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY10]], [[REG_SEQUENCE1]], [[REG_SEQUENCE6]], 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.data_addr + 8, align 8, basealign 16, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_1]], %subreg.sub0_sub1, [[REG_SEQUENCE6]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY10]], [[REG_SEQUENCE1]], [[REG_SEQUENCE7]], 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.data_addr + 8, align 8, basealign 16, addrspace 1) ; GFX6-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_5]], %subreg.sub0, [[S_MOV_B32_6]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_5]], %subreg.sub0, [[S_MOV_B32_6]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_2]], %subreg.sub0_sub1, [[REG_SEQUENCE7]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY11]], [[REG_SEQUENCE2]], [[REG_SEQUENCE8]], 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE9:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_2]], %subreg.sub0_sub1, [[REG_SEQUENCE8]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY11]], [[REG_SEQUENCE2]], [[REG_SEQUENCE9]], 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX7-LABEL: name: raw_buffer_load_v3f32_tfe @@ -1236,13 +1308,17 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX7-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX7-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] ; GFX7-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX7-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX7-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX7-NEXT: BUFFER_STORE_DWORDX3_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX7-NEXT: BUFFER_STORE_DWORDX3_ADDR64 [[COPY12]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX7-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX7-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX7-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -1272,8 +1348,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -1298,8 +1378,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -1324,8 +1408,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub1 ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub2 ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_OFFSET]].sub3 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -1349,8 +1437,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub1 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub2 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub3 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -1374,8 +1466,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub1 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub2 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET]].sub3 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vreg_96_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <3 x float>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v3f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0) @@ -1409,13 +1505,18 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX67-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub2 ; GFX67-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub3 ; GFX67-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub4 - ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX67-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] ; GFX67-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX67-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX67-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX67-NEXT: BUFFER_STORE_DWORDX4_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX67-NEXT: BUFFER_STORE_DWORDX4_ADDR64 [[COPY13]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX67-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -1446,8 +1547,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub2 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub3 ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub4 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -1473,8 +1579,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub2 ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub3 ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub4 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX910-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -1500,8 +1611,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub2 ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub3 ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub4 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -1526,8 +1642,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub2 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub3 ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub4 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -1552,8 +1673,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub2 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub3 ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub4 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <4 x i32>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v4i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0) @@ -1587,13 +1713,18 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX67-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub2 ; GFX67-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub3 ; GFX67-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub4 - ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX67-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] ; GFX67-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX67-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX67-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX67-NEXT: BUFFER_STORE_DWORDX4_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX67-NEXT: BUFFER_STORE_DWORDX4_ADDR64 [[COPY13]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX67-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -1624,8 +1755,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub2 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub3 ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub4 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -1651,8 +1787,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub2 ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub3 ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub4 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX910-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -1678,8 +1819,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub2 ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub3 ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_OFFSET]].sub4 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -1704,8 +1850,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub2 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub3 ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub4 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -1730,8 +1881,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub2 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub3 ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET]].sub4 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1, [[COPY10]], %subreg.sub2, [[COPY11]], %subreg.sub3 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <4 x float>, i32 } @llvm.amdgcn.raw.buffer.load.sl_v4f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll index c365d5711f6ce..373b120c566a9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s ; FIXME: Test with SI when argument lowering not broken for f16 ; Natural mapping diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll index 13f9cce91e0c9..4350b4001bce8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s ; Natural mapping define amdgpu_ps half @raw_ptr_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll index a15b34dbb8c21..1c667e287f630 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s ; FIXME: Test with SI when argument lowering not broken for f16 ; Natural mapping diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll index 9d8f47ada8521..49ed57161c80e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll index 12c6029a7a367..74e7336efecf2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset @@ -74,11 +74,46 @@ define amdgpu_ps void @raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_so ret void } -; FIXME: Crashes -; define amdgpu_ps void @raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<3 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { -; call void @llvm.amdgcn.raw.ptr.tbuffer.store.v3f16(<3 x half> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) -; ret void -; } +define amdgpu_ps void @raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<3 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { + ; UNPACKED-LABEL: name: raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; UNPACKED-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; UNPACKED-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY2]], [[COPY]], implicit $exec + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY1]], %subreg.sub2 + ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 + ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact [[REG_SEQUENCE]], [[COPY7]], [[REG_SEQUENCE1]], [[COPY8]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>) into %ir.rsrc, align 1, addrspace 8) + ; UNPACKED-NEXT: S_ENDPGM 0 + ; + ; PACKED-LABEL: name: raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; PACKED-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 + ; PACKED-NEXT: TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>) into %ir.rsrc, align 1, addrspace 8) + ; PACKED-NEXT: S_ENDPGM 0 + call void @llvm.amdgcn.raw.ptr.tbuffer.store.v3f16(<3 x half> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) + ret void +} define amdgpu_ps void @raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll index 50b3387d329b3..ce04e26f6140d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset @@ -547,6 +547,197 @@ define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffs ret half %val } +define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) { + ; UNPACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; UNPACKED-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (s16), align 1, addrspace 8) + ; UNPACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN]] + ; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; PACKED-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; PACKED-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (s16), align 1, addrspace 8) + ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_OFFEN]] + ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX12-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (s16), align 1, addrspace 8) + ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] + ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %val = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) + ret half %val +} + +define amdgpu_ps <2 x half> @raw_tbuffer_load_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) { + ; UNPACKED-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; UNPACKED-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x s16>), align 1, addrspace 8) + ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub0 + ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN]].sub1 + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; UNPACKED-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 + ; UNPACKED-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_1]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; UNPACKED-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_AND_B32_1]], [[S_MOV_B32_1]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[S_LSHL_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: $vgpr0 = COPY [[S_OR_B32_]] + ; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; PACKED-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; PACKED-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XY_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x s16>), align 1, addrspace 8) + ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_OFFEN]] + ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX12-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x s16>), align 1, addrspace 8) + ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN]] + ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + %val = call <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) + ret <2 x half> %val +} + +define amdgpu_ps <4 x half> @raw_tbuffer_load_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset) { + ; UNPACKED-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; UNPACKED-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x s16>), align 1, addrspace 8) + ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub0 + ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub1 + ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub2 + ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN]].sub3 + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; UNPACKED-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; UNPACKED-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535 + ; UNPACKED-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_1]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; UNPACKED-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_AND_B32_1]], [[S_MOV_B32_1]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], [[S_LSHL_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_2]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_AND_B32_3:%[0-9]+]]:sreg_32 = S_AND_B32 [[V_READFIRSTLANE_B32_3]], [[S_MOV_B32_]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_LSHL_B32_1:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[S_AND_B32_3]], [[S_MOV_B32_1]], implicit-def dead $scc + ; UNPACKED-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_2]], [[S_LSHL_B32_1]], implicit-def dead $scc + ; UNPACKED-NEXT: $vgpr0 = COPY [[S_OR_B32_]] + ; UNPACKED-NEXT: $vgpr1 = COPY [[S_OR_B32_1]] + ; UNPACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; PACKED-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; PACKED-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x s16>), align 1, addrspace 8) + ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub0 + ; PACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN]].sub1 + ; PACKED-NEXT: $vgpr0 = COPY [[COPY7]] + ; PACKED-NEXT: $vgpr1 = COPY [[COPY8]] + ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX12-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x s16>), align 1, addrspace 8) + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub0 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub1 + ; GFX12-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX12-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + %val = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) + ret <4 x half> %val +} + declare half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0 declare <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0 declare <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32 immarg, i32 immarg) #0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll index 977d7d379d6a1..5e076b8004794 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(half %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset @@ -105,11 +105,63 @@ define amdgpu_ps void @raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_so ret void } -; FIXME: Crashes -; define amdgpu_ps void @raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) { -; call void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) -; ret void -; } +define amdgpu_ps void @raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) { + ; UNPACKED-LABEL: name: raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; UNPACKED-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; UNPACKED-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY2]], [[COPY]], implicit $exec + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 + ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY1]], %subreg.sub2 + ; UNPACKED-NEXT: TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>), align 1, addrspace 8) + ; UNPACKED-NEXT: S_ENDPGM 0 + ; + ; PACKED-LABEL: name: raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; PACKED-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: TBUFFER_STORE_FORMAT_D16_XYZ_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>), align 1, addrspace 8) + ; PACKED-NEXT: S_ENDPGM 0 + ; + ; GFX12-LABEL: name: raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>), align 1, addrspace 8) + ; GFX12-NEXT: S_ENDPGM 0 + call void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) + ret void +} define amdgpu_ps void @raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll index aea128e3bece6..6a7021c5d01d1 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps half @struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll index c1641442a01fb..c55b918912851 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s ; Note that TFE instructions don't have the result initialization to zero due to stopping before finalize-isel - which is where that's inserted define amdgpu_ps float @struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { @@ -414,8 +414,13 @@ define amdgpu_cs void @struct_buffer_load_format_v4i32_tfe(<4 x i32> inreg %rsrc ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub2 ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub3 ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub4 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.value, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.value, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.status, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -442,8 +447,13 @@ define amdgpu_cs void @struct_buffer_load_format_v4i32_tfe(<4 x i32> inreg %rsrc ; GFX12-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN]].sub2 ; GFX12-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN]].sub3 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN]].sub4 - ; GFX12-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX12-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.value, addrspace 1) + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX12-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX12-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX12-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.value, addrspace 1) ; GFX12-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.status, addrspace 1) ; GFX12-NEXT: S_ENDPGM 0 %load = call { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) @@ -480,8 +490,12 @@ define amdgpu_cs void @struct_buffer_load_format_v3i32_tfe(<4 x i32> inreg %rsrc ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub1 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub2 ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub3 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.value, align 16, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.value, align 16, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.status, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -507,8 +521,12 @@ define amdgpu_cs void @struct_buffer_load_format_v3i32_tfe(<4 x i32> inreg %rsrc ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN]].sub1 ; GFX12-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN]].sub2 ; GFX12-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN]].sub3 - ; GFX12-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX12-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.value, align 16, addrspace 1) + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX12-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX12-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX12-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.value, align 16, addrspace 1) ; GFX12-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.status, addrspace 1) ; GFX12-NEXT: S_ENDPGM 0 %load = call { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll index 39cce20cc63f7..ef56a38fca269 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX67,GFX6 -; RUN: llc -global-isel -mcpu=hawaii -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX67,GFX7 -; RUN: llc -global-isel -mcpu=fiji -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX8 -; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910 -; RUN: llc -global-isel -mcpu=gfx1010 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910 -; RUN: llc -global-isel -mcpu=gfx1100 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11 -; RUN: llc -global-isel -mcpu=gfx1200 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1200 -; RUN: llc -global-isel -mcpu=gfx1250 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1250 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=tahiti -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX67,GFX6 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=hawaii -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX67,GFX7 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=fiji -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX8 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx900 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1010 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefix=GFX910 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1100 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX11 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1200 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1200 +; RUN: llc -global-isel -new-reg-bank-select -mcpu=gfx1250 -mattr=-real-true16 -mtriple=amdgcn-- -stop-after=instruction-select < %s | FileCheck %s -check-prefixes=GFX1250 define amdgpu_ps void @raw_buffer_load_i8_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %data_addr, ptr addrspace(1) %tfe_addr) { ; GFX67-LABEL: name: raw_buffer_load_i8_tfe @@ -678,13 +678,16 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX67-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub0 ; GFX67-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub1 ; GFX67-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub2 - ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX67-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] ; GFX67-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX67-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX67-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX67-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX67-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY12]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX67-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -714,8 +717,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub0 ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub1 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub2 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX8-NEXT: FLAT_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -740,8 +746,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub0 ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub1 ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub2 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -766,8 +775,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub0 ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub1 ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub2 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -792,8 +804,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub0 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub1 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub2 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -818,8 +833,11 @@ define amdgpu_ps void @raw_buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub0 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub1 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub2 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <2 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v2i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) @@ -852,13 +870,16 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX67-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub0 ; GFX67-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub1 ; GFX67-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub2 - ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX67-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] ; GFX67-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX67-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX67-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX67-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX67-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY12]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX67-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -888,8 +909,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub0 ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub1 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub2 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX8-NEXT: FLAT_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -914,8 +938,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub0 ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub1 ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub2 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -940,8 +967,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub0 ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub1 ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_IDXEN]].sub2 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -966,8 +996,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub0 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub1 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub2 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -992,8 +1025,11 @@ define amdgpu_ps void @raw_buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub0 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub1 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN]].sub2 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 + ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX2 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY11]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <2 x float>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v2f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) @@ -1027,26 +1063,32 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vreg_64 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub0_sub1 - ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2_sub3 + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1 + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub2_sub3 + ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vreg_64 = COPY [[COPY13]] ; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE3]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY13]], [[REG_SEQUENCE1]], [[REG_SEQUENCE4]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY15]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX6-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_1]], %subreg.sub0_sub1, [[REG_SEQUENCE5]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY11]], [[REG_SEQUENCE1]], [[REG_SEQUENCE6]], 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.data_addr + 8, align 8, basealign 16, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_1]], %subreg.sub0_sub1, [[REG_SEQUENCE6]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY11]], [[REG_SEQUENCE1]], [[REG_SEQUENCE7]], 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.data_addr + 8, align 8, basealign 16, addrspace 1) ; GFX6-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_5]], %subreg.sub0, [[S_MOV_B32_6]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_5]], %subreg.sub0, [[S_MOV_B32_6]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_2]], %subreg.sub0_sub1, [[REG_SEQUENCE7]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY12]], [[REG_SEQUENCE2]], [[REG_SEQUENCE8]], 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE9:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_2]], %subreg.sub0_sub1, [[REG_SEQUENCE8]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY12]], [[REG_SEQUENCE2]], [[REG_SEQUENCE9]], 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX7-LABEL: name: raw_buffer_load_v3i32_tfe @@ -1071,13 +1113,17 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX7-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX7-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] ; GFX7-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX7-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX7-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX7-NEXT: BUFFER_STORE_DWORDX3_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX7-NEXT: BUFFER_STORE_DWORDX3_ADDR64 [[COPY13]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX7-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX7-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX7-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -1108,8 +1154,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -1135,8 +1185,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX910-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -1162,8 +1216,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -1189,8 +1247,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub1 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub2 ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub3 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -1216,8 +1278,12 @@ define amdgpu_ps void @raw_buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub1 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub2 ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub3 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vreg_96_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) @@ -1251,26 +1317,32 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX6-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX6-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX6-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX6-NEXT: [[COPY13:%[0-9]+]]:vreg_64 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub0_sub1 - ; GFX6-NEXT: [[COPY14:%[0-9]+]]:vreg_64 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2_sub3 + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX6-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX6-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub0_sub1 + ; GFX6-NEXT: [[COPY14:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE3]].sub2_sub3 + ; GFX6-NEXT: [[COPY15:%[0-9]+]]:vreg_64 = COPY [[COPY13]] ; GFX6-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE3]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY13]], [[REG_SEQUENCE1]], [[REG_SEQUENCE4]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORDX2_ADDR64 [[COPY15]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<2 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX6-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_1]], %subreg.sub0_sub1, [[REG_SEQUENCE5]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY11]], [[REG_SEQUENCE1]], [[REG_SEQUENCE6]], 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.data_addr + 8, align 8, basealign 16, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_1]], %subreg.sub0_sub1, [[REG_SEQUENCE6]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY11]], [[REG_SEQUENCE1]], [[REG_SEQUENCE7]], 0, 8, 0, 0, implicit $exec :: (store (s32) into %ir.data_addr + 8, align 8, basealign 16, addrspace 1) ; GFX6-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX6-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 - ; GFX6-NEXT: [[REG_SEQUENCE7:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_5]], %subreg.sub0, [[S_MOV_B32_6]], %subreg.sub1 + ; GFX6-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_5]], %subreg.sub0, [[S_MOV_B32_6]], %subreg.sub1 ; GFX6-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 0 - ; GFX6-NEXT: [[REG_SEQUENCE8:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_2]], %subreg.sub0_sub1, [[REG_SEQUENCE7]], %subreg.sub2_sub3 - ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY12]], [[REG_SEQUENCE2]], [[REG_SEQUENCE8]], 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) + ; GFX6-NEXT: [[REG_SEQUENCE9:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_2]], %subreg.sub0_sub1, [[REG_SEQUENCE8]], %subreg.sub2_sub3 + ; GFX6-NEXT: BUFFER_STORE_DWORD_ADDR64 [[COPY12]], [[REG_SEQUENCE2]], [[REG_SEQUENCE9]], 0, 0, 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX6-NEXT: S_ENDPGM 0 ; ; GFX7-LABEL: name: raw_buffer_load_v3f32_tfe @@ -1295,13 +1367,17 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX7-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX7-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX7-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX7-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX7-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX7-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX7-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] ; GFX7-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX7-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX7-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX7-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX7-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX7-NEXT: BUFFER_STORE_DWORDX3_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX7-NEXT: BUFFER_STORE_DWORDX3_ADDR64 [[COPY13]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX7-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX7-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX7-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -1332,8 +1408,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -1359,8 +1439,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX910-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -1386,8 +1470,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub1 ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub2 ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_IDXEN]].sub3 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -1413,8 +1501,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub1 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub2 ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub3 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -1440,8 +1532,12 @@ define amdgpu_ps void @raw_buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub1 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub2 ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN]].sub3 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vreg_96_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX3 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (<3 x s32>) into %ir.data_addr, align 16, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <3 x float>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v3f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) @@ -1476,13 +1572,18 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX67-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub2 ; GFX67-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub3 ; GFX67-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub4 - ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX67-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] ; GFX67-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX67-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX67-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX67-NEXT: BUFFER_STORE_DWORDX4_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX67-NEXT: BUFFER_STORE_DWORDX4_ADDR64 [[COPY14]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX67-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -1514,8 +1615,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub2 ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub3 ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub4 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -1542,8 +1648,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub2 ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub3 ; GFX910-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub4 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX910-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -1570,8 +1681,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub2 ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub3 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub4 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -1598,8 +1714,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub2 ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub3 ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub4 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX1200-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -1626,8 +1747,13 @@ define amdgpu_ps void @raw_buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub2 ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub3 ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub4 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v4i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) @@ -1662,13 +1788,18 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX67-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub2 ; GFX67-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub3 ; GFX67-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub4 - ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX67-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX67-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX67-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] ; GFX67-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_2]], %subreg.sub1 ; GFX67-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 ; GFX67-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B64_]], %subreg.sub0_sub1, [[REG_SEQUENCE4]], %subreg.sub2_sub3 - ; GFX67-NEXT: BUFFER_STORE_DWORDX4_ADDR64 [[REG_SEQUENCE3]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX67-NEXT: BUFFER_STORE_DWORDX4_ADDR64 [[COPY14]], [[REG_SEQUENCE1]], [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX67-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX67-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 61440 ; GFX67-NEXT: [[REG_SEQUENCE6:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_3]], %subreg.sub0, [[S_MOV_B32_4]], %subreg.sub1 @@ -1700,8 +1831,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX8-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub2 ; GFX8-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub3 ; GFX8-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub4 - ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX8-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX8-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX8-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX8-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX8-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX8-NEXT: S_ENDPGM 0 ; @@ -1728,8 +1864,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX910-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub2 ; GFX910-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub3 ; GFX910-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub4 - ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX910-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX910-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX910-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX910-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX910-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX910-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX910-NEXT: S_ENDPGM 0 ; @@ -1756,8 +1897,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub2 ; GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub3 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_IDXEN]].sub4 - ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX11-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX11-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX11-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX11-NEXT: S_ENDPGM 0 ; @@ -1784,8 +1930,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub2 ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub3 ; GFX1200-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub4 - ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX1200-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1200-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX1200-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; GFX1200-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX1200-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1200-NEXT: S_ENDPGM 0 ; @@ -1812,8 +1963,13 @@ define amdgpu_ps void @raw_buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addr ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub2 ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub3 ; GFX1250-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN]].sub4 - ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; GFX1250-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GFX1250-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX1250-NEXT: [[COPY14:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE3]] + ; GFX1250-NEXT: GLOBAL_STORE_DWORDX4 [[REG_SEQUENCE1]], [[COPY14]], 0, 0, implicit $exec :: (store (<4 x s32>) into %ir.data_addr, addrspace 1) ; GFX1250-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec :: (store (s32) into %ir.tfe_addr, addrspace 1) ; GFX1250-NEXT: S_ENDPGM 0 %res = call { <4 x float>, i32 } @llvm.amdgcn.struct.buffer.load.sl_v4f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll index 74c069052fd52..6f71d22860d9a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll @@ -117,11 +117,69 @@ define amdgpu_ps void @struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vg ret void } -; FIXME: -; define amdgpu_ps void @struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { -; call void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) -; ret void -; } +define amdgpu_ps void @struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { + ; UNPACKED-LABEL: name: struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; UNPACKED-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; UNPACKED-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY2]], [[COPY]], implicit $exec + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 + ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY1]], %subreg.sub2 + ; UNPACKED-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 + ; UNPACKED-NEXT: BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>), align 1, addrspace 8) + ; UNPACKED-NEXT: S_ENDPGM 0 + ; + ; PACKED-LABEL: name: struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; PACKED-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 + ; PACKED-NEXT: BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>), align 1, addrspace 8) + ; PACKED-NEXT: S_ENDPGM 0 + ; + ; GFX12-LABEL: name: struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX12: bb.1 (%ir-block.0): + ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 + ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>), align 1, addrspace 8) + ; GFX12-NEXT: S_ENDPGM 0 + call void @llvm.amdgcn.struct.buffer.store.format.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) + ret void +} define amdgpu_ps void @struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll index c9771b5aca0db..6fb35ad5ce1a4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1200 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1250 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1200 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1250 %s ; Natural mapping define amdgpu_ps void @struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll index 30ce3675a42a2..bcd9781ee2a4f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=PACKED %s define amdgpu_ps half @struct_ptr_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: struct_ptr_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll index 4c598126b855d..bfa4f485b057e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s ; Note that TFE instructions don't have the result initialization to zero due to stopping before finalize-isel - which is where that's inserted define amdgpu_ps float @struct_ptr_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { @@ -235,8 +235,13 @@ define amdgpu_cs void @struct_ptr_buffer_load_format_v4i32_tfe(ptr addrspace(8) ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub2 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub3 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub4 - ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 - ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.value, addrspace 1) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; CHECK-NEXT: [[COPY14:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE3]] + ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE]], [[COPY14]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.value, addrspace 1) ; CHECK-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.status, addrspace 1) ; CHECK-NEXT: S_ENDPGM 0 %load = call { <4 x i32>, i32 } @llvm.amdgcn.struct.ptr.buffer.load.format.sl_v4i32i32s(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0) @@ -273,8 +278,12 @@ define amdgpu_cs void @struct_ptr_buffer_load_format_v3i32_tfe(ptr addrspace(8) ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub1 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub2 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub3 - ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 - ; CHECK-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.value, align 16, addrspace 1) + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; CHECK-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_96 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2 + ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE3]] + ; CHECK-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.value, align 16, addrspace 1) ; CHECK-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.status, addrspace 1) ; CHECK-NEXT: S_ENDPGM 0 %load = call { <3 x i32>, i32 } @llvm.amdgcn.struct.ptr.buffer.load.format.sl_v3i32i32s(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0, i32 0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll index 50a311e6705a6..2cf7563317118 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll @@ -82,11 +82,50 @@ define amdgpu_ps void @struct_ptr_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc ret void } -; FIXME: -; define amdgpu_ps void @struct_ptr_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { -; call void @llvm.amdgcn.struct.ptr.buffer.store.format.v3f16(<3 x half> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) -; ret void -; } +define amdgpu_ps void @struct_ptr_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<3 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { + ; UNPACKED-LABEL: name: struct_ptr_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; UNPACKED: bb.1 (%ir-block.0): + ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; UNPACKED-NEXT: {{ $}} + ; UNPACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; UNPACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; UNPACKED-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; UNPACKED-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; UNPACKED-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY2]], [[COPY]], implicit $exec + ; UNPACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; UNPACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; UNPACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; UNPACKED-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; UNPACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; UNPACKED-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; UNPACKED-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; UNPACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_LSHRREV_B32_e64_]], %subreg.sub1, [[COPY1]], %subreg.sub2 + ; UNPACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 + ; UNPACKED-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 + ; UNPACKED-NEXT: BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>) into %ir.rsrc, align 1, addrspace 8) + ; UNPACKED-NEXT: S_ENDPGM 0 + ; + ; PACKED-LABEL: name: struct_ptr_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; PACKED: bb.1 (%ir-block.0): + ; PACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; PACKED-NEXT: {{ $}} + ; PACKED-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; PACKED-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; PACKED-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; PACKED-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; PACKED-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; PACKED-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; PACKED-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; PACKED-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; PACKED-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; PACKED-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; PACKED-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 + ; PACKED-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 + ; PACKED-NEXT: BUFFER_STORE_FORMAT_D16_XYZ_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x s16>) into %ir.rsrc, align 1, addrspace 8) + ; PACKED-NEXT: S_ENDPGM 0 + call void @llvm.amdgcn.struct.ptr.buffer.store.format.v3f16(<3 x half> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0) + ret void +} define amdgpu_ps void @struct_ptr_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; UNPACKED-LABEL: name: struct_ptr_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll index f331e29176740..3a8e2e6e5f6c3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck %s ; Natural mapping define amdgpu_ps void @struct_ptr_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll index 49918e68b0cee..28e6e090b6242 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=UNPACKED %s define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; PACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll index 3c22f3555af80..591df86c48a9f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=UNPACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx810 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=UNPACKED %s define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; PACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll index 04652af147f9b..4d35f3198bc0a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll @@ -1,27 +1,87 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-- -mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=LOOP %s -; RUN: llc -global-isel -mtriple=amdgcn-- -mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=UNROLL %s +; RUN: llc -global-isel -mtriple=amdgcn-- -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=35 %s -o - | FileCheck -check-prefix=LOOP %s +; RUN: llc -global-isel -mtriple=amdgcn-- -amdgpu-memcpy-loop-unroll=2 -mem-intrinsic-expand-size=37 %s -o - | FileCheck -check-prefix=UNROLL %s declare void @llvm.memset.p1.i32(ptr addrspace(1), i8, i32, i1) define amdgpu_cs void @memset_p1i8(ptr addrspace(1) %dst, i8 %val) { ; LOOP-LABEL: memset_p1i8: -; LOOP: ; %bb.0: ; %loadstoreloop.preheader +; LOOP: ; %bb.0: +; LOOP-NEXT: v_and_b32_e32 v3, 0xff, v2 ; LOOP-NEXT: s_mov_b64 s[0:1], 0 ; LOOP-NEXT: s_mov_b32 s2, 0 ; LOOP-NEXT: s_mov_b32 s3, 0xf000 +; LOOP-NEXT: v_lshlrev_b32_e32 v4, 8, v3 +; LOOP-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; LOOP-NEXT: v_lshlrev_b32_e32 v6, 24, v3 +; LOOP-NEXT: v_or_b32_e32 v3, v3, v4 +; LOOP-NEXT: v_or_b32_e32 v3, v3, v5 +; LOOP-NEXT: v_or_b32_e32 v5, v3, v6 +; LOOP-NEXT: v_lshrrev_b32_e32 v6, 16, v5 +; LOOP-NEXT: v_bfe_u32 v7, v5, 8, 8 +; LOOP-NEXT: v_lshrrev_b32_e32 v8, 24, v5 ; LOOP-NEXT: v_mov_b32_e32 v4, s1 ; LOOP-NEXT: v_mov_b32_e32 v3, s0 -; LOOP-NEXT: .LBB0_1: ; %loadstoreloop +; LOOP-NEXT: .LBB0_1: ; %static-memset-expansion-main-body ; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1 -; LOOP-NEXT: v_add_i32_e32 v5, vcc, v0, v3 -; LOOP-NEXT: v_addc_u32_e32 v6, vcc, v1, v4, vcc -; LOOP-NEXT: v_add_i32_e32 v3, vcc, 1, v3 +; LOOP-NEXT: v_add_i32_e32 v9, vcc, v0, v3 +; LOOP-NEXT: v_addc_u32_e32 v10, vcc, v1, v4, vcc +; LOOP-NEXT: v_add_i32_e32 v3, vcc, 32, v3 ; LOOP-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; LOOP-NEXT: v_cmp_gt_u32_e32 vcc, 4, v3 -; LOOP-NEXT: buffer_store_byte v2, v[5:6], s[0:3], 0 addr64 +; LOOP-NEXT: buffer_store_byte v5, v[9:10], s[0:3], 0 addr64 +; LOOP-NEXT: buffer_store_byte v7, v[9:10], s[0:3], 0 addr64 offset:1 +; LOOP-NEXT: buffer_store_byte v6, v[9:10], s[0:3], 0 addr64 offset:2 +; LOOP-NEXT: buffer_store_byte v8, v[9:10], s[0:3], 0 addr64 offset:3 +; LOOP-NEXT: buffer_store_byte v5, v[9:10], s[0:3], 0 addr64 offset:4 +; LOOP-NEXT: buffer_store_byte v7, v[9:10], s[0:3], 0 addr64 offset:5 +; LOOP-NEXT: buffer_store_byte v6, v[9:10], s[0:3], 0 addr64 offset:6 +; LOOP-NEXT: buffer_store_byte v8, v[9:10], s[0:3], 0 addr64 offset:7 +; LOOP-NEXT: buffer_store_byte v5, v[9:10], s[0:3], 0 addr64 offset:8 +; LOOP-NEXT: buffer_store_byte v7, v[9:10], s[0:3], 0 addr64 offset:9 +; LOOP-NEXT: buffer_store_byte v6, v[9:10], s[0:3], 0 addr64 offset:10 +; LOOP-NEXT: buffer_store_byte v8, v[9:10], s[0:3], 0 addr64 offset:11 +; LOOP-NEXT: buffer_store_byte v5, v[9:10], s[0:3], 0 addr64 offset:12 +; LOOP-NEXT: buffer_store_byte v7, v[9:10], s[0:3], 0 addr64 offset:13 +; LOOP-NEXT: buffer_store_byte v6, v[9:10], s[0:3], 0 addr64 offset:14 +; LOOP-NEXT: buffer_store_byte v8, v[9:10], s[0:3], 0 addr64 offset:15 +; LOOP-NEXT: buffer_store_byte v5, v[9:10], s[0:3], 0 addr64 offset:16 +; LOOP-NEXT: buffer_store_byte v7, v[9:10], s[0:3], 0 addr64 offset:17 +; LOOP-NEXT: buffer_store_byte v6, v[9:10], s[0:3], 0 addr64 offset:18 +; LOOP-NEXT: buffer_store_byte v8, v[9:10], s[0:3], 0 addr64 offset:19 +; LOOP-NEXT: buffer_store_byte v5, v[9:10], s[0:3], 0 addr64 offset:20 +; LOOP-NEXT: buffer_store_byte v7, v[9:10], s[0:3], 0 addr64 offset:21 +; LOOP-NEXT: buffer_store_byte v6, v[9:10], s[0:3], 0 addr64 offset:22 +; LOOP-NEXT: buffer_store_byte v8, v[9:10], s[0:3], 0 addr64 offset:23 +; LOOP-NEXT: buffer_store_byte v5, v[9:10], s[0:3], 0 addr64 offset:24 +; LOOP-NEXT: buffer_store_byte v7, v[9:10], s[0:3], 0 addr64 offset:25 +; LOOP-NEXT: buffer_store_byte v6, v[9:10], s[0:3], 0 addr64 offset:26 +; LOOP-NEXT: buffer_store_byte v8, v[9:10], s[0:3], 0 addr64 offset:27 +; LOOP-NEXT: buffer_store_byte v5, v[9:10], s[0:3], 0 addr64 offset:28 +; LOOP-NEXT: buffer_store_byte v7, v[9:10], s[0:3], 0 addr64 offset:29 +; LOOP-NEXT: buffer_store_byte v6, v[9:10], s[0:3], 0 addr64 offset:30 +; LOOP-NEXT: v_cmp_gt_u32_e32 vcc, 32, v3 +; LOOP-NEXT: buffer_store_byte v8, v[9:10], s[0:3], 0 addr64 offset:31 ; LOOP-NEXT: s_cbranch_vccnz .LBB0_1 -; LOOP-NEXT: ; %bb.2: ; %split +; LOOP-NEXT: ; %bb.2: ; %static-memset-post-expansion +; LOOP-NEXT: v_and_b32_e32 v2, 0xff, v2 +; LOOP-NEXT: s_mov_b32 s2, 0 +; LOOP-NEXT: s_mov_b32 s3, 0xf000 +; LOOP-NEXT: s_mov_b64 s[0:1], 0 +; LOOP-NEXT: v_lshlrev_b32_e32 v3, 8, v2 +; LOOP-NEXT: v_lshlrev_b32_e32 v4, 16, v2 +; LOOP-NEXT: s_waitcnt expcnt(3) +; LOOP-NEXT: v_lshlrev_b32_e32 v5, 24, v2 +; LOOP-NEXT: v_or_b32_e32 v2, v2, v3 +; LOOP-NEXT: v_or_b32_e32 v2, v2, v4 +; LOOP-NEXT: v_or_b32_e32 v2, v2, v5 +; LOOP-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; LOOP-NEXT: v_bfe_u32 v4, v2, 8, 8 +; LOOP-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:32 +; LOOP-NEXT: s_waitcnt expcnt(0) +; LOOP-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; LOOP-NEXT: buffer_store_byte v4, v[0:1], s[0:3], 0 addr64 offset:33 +; LOOP-NEXT: buffer_store_byte v3, v[0:1], s[0:3], 0 addr64 offset:34 +; LOOP-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:35 ; LOOP-NEXT: s_endpgm ; ; UNROLL-LABEL: memset_p1i8: @@ -33,7 +93,39 @@ define amdgpu_cs void @memset_p1i8(ptr addrspace(1) %dst, i8 %val) { ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:1 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:2 ; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:3 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:4 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:5 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:6 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:7 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:8 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:9 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:10 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:11 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:12 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:13 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:14 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:15 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:16 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:17 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:18 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:19 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:20 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:21 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:22 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:23 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:24 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:25 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:26 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:27 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:28 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:29 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:30 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:31 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:32 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:33 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:34 +; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:35 ; UNROLL-NEXT: s_endpgm - call void @llvm.memset.p1.i32(ptr addrspace(1) %dst, i8 %val, i32 4, i1 false) + call void @llvm.memset.p1.i32(ptr addrspace(1) %dst, i8 %val, i32 36, i1 false) ret void } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll index 52425323332dd..af0185915517d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll @@ -103,4 +103,4 @@ define float @test_fmamix_constant_bus_violation_vss(i32 %val.0, i32 inreg %val. ret float %fma } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir index 593b1c6a2ebfa..920eb0f9d5df3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s --- name: fceil_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir index 6b14849556faf..b743c0db5adda 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s --- name: fexp2_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir new file mode 100644 index 0000000000000..bff455e7b2a85 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir @@ -0,0 +1,35 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s + +--- +name: ffloor_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: ffloor_s + ; CHECK: liveins: $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY1]] + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_FFLOOR %0 +... + +--- +name: ffloor_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: ffloor_v + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]] + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_FFLOOR %0 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir index 65b205f66d5f9..7a28706d2ea2e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s --- name: flog2_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir index c690f8439098f..f77a686d4e5c3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s --- name: fptosi_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir index 17e656340f780..86cf60d92b6c6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s --- name: fptoui_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir new file mode 100644 index 0000000000000..a868d40df8726 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-roundeven.mir @@ -0,0 +1,35 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s + +--- +name: intrinsic_roundeven_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: intrinsic_roundeven_s + ; CHECK: liveins: $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_ROUNDEVEN [[COPY1]] + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_INTRINSIC_ROUNDEVEN %0 +... + +--- +name: intrinsic_roundeven_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: intrinsic_roundeven_v + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_ROUNDEVEN [[COPY]] + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_INTRINSIC_ROUNDEVEN %0 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir index eca10bf2effbf..6318297cc1133 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s --- name: intrinsic_trunc_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir index 524714df5b974..3b78f1e3a2157 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s --- name: sadde_s32_sss @@ -9,30 +8,17 @@ legalized: true body: | bb.0: liveins: $sgpr0, $sgpr1, $sgpr2 - ; FAST-LABEL: name: sadde_s32_sss - ; FAST: liveins: $sgpr0, $sgpr1, $sgpr2 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; FAST-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) - ; FAST-NEXT: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[ZEXT]] - ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SADDE1]](s32) - ; GREEDY-LABEL: name: sadde_s32_sss - ; GREEDY: liveins: $sgpr0, $sgpr1, $sgpr2 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) - ; GREEDY-NEXT: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[ZEXT]] - ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SADDE1]](s32) + ; CHECK-LABEL: name: sadde_s32_sss + ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[C1]] + ; CHECK-NEXT: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[AND]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $sgpr2 @@ -48,30 +34,17 @@ legalized: true body: | bb.0: liveins: $vgpr0, $sgpr0, $sgpr1 - ; FAST-LABEL: name: sadde_s32_vss - ; FAST: liveins: $vgpr0, $sgpr0, $sgpr1 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; FAST-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; FAST-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; FAST-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]] - ; GREEDY-LABEL: name: sadde_s32_vss - ; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; GREEDY-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[COPY4]] + ; CHECK-LABEL: name: sadde_s32_vss + ; CHECK: liveins: $vgpr0, $sgpr0, $sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32) + ; CHECK-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY3]], [[AMDGPU_COPY_VCC_SCC]] %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $sgpr0 %2:_(s32) = COPY $sgpr1 @@ -86,28 +59,19 @@ legalized: true body: | bb.0: liveins: $sgpr0, $sgpr1, $vgpr0 - ; FAST-LABEL: name: sadde_s32_ssv - ; FAST: liveins: $sgpr0, $sgpr1, $vgpr0 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32) - ; FAST-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; FAST-NEXT: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; FAST-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]] - ; GREEDY-LABEL: name: sadde_s32_ssv - ; GREEDY: liveins: $sgpr0, $sgpr1, $vgpr0 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; GREEDY-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[COPY5]] + ; CHECK-LABEL: name: sadde_s32_ssv + ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY3]], [[COPY4]], [[ICMP]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $vgpr0 @@ -122,24 +86,14 @@ legalized: true body: | bb.0: liveins: $vgpr0, $vgpr1, $sgpr0 - ; FAST-LABEL: name: sadde_s32_vvs - ; FAST: liveins: $vgpr0, $vgpr1, $sgpr0 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32) - ; FAST-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; FAST-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]] - ; GREEDY-LABEL: name: sadde_s32_vvs - ; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; GREEDY-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY1]], [[COPY3]] + ; CHECK-LABEL: name: sadde_s32_vvs + ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY2]](s32) + ; CHECK-NEXT: [[SADDE:%[0-9]+]]:vgpr(s32), [[SADDE1:%[0-9]+]]:vcc(s1) = G_SADDE [[COPY]], [[COPY1]], [[AMDGPU_COPY_VCC_SCC]] %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = COPY $sgpr0 @@ -154,26 +108,15 @@ legalized: true body: | bb.0: liveins: $sgpr0, $sgpr1, $sgpr2 - ; FAST-LABEL: name: sadde_s32_sss_noscc - ; FAST: liveins: $sgpr0, $sgpr1, $sgpr2 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32) - ; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) - ; FAST-NEXT: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[ZEXT]] - ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SADDE1]](s32) - ; GREEDY-LABEL: name: sadde_s32_sss_noscc - ; GREEDY: liveins: $sgpr0, $sgpr1, $sgpr2 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) - ; GREEDY-NEXT: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[ZEXT]] - ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SADDE1]](s32) + ; CHECK-LABEL: name: sadde_s32_sss_noscc + ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:sgpr(s32) = G_SADDE [[COPY]], [[COPY1]], [[AND]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $sgpr2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir index 66e0d3db24112..4252e50ac064e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s --- name: sitofp_s diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir index eae770ae18dce..e7b30219a1826 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir @@ -1,6 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' %s -o - | FileCheck %s --- name: ssube_s32_sss @@ -9,30 +8,17 @@ legalized: true body: | bb.0: liveins: $sgpr0, $sgpr1, $sgpr2 - ; FAST-LABEL: name: ssube_s32_sss - ; FAST: liveins: $sgpr0, $sgpr1, $sgpr2 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; FAST-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) - ; FAST-NEXT: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[ZEXT]] - ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SSUBE1]](s32) - ; GREEDY-LABEL: name: ssube_s32_sss - ; GREEDY: liveins: $sgpr0, $sgpr1, $sgpr2 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) - ; GREEDY-NEXT: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[ZEXT]] - ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SSUBE1]](s32) + ; CHECK-LABEL: name: ssube_s32_sss + ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[C1]] + ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[AND]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $sgpr2 @@ -48,30 +34,17 @@ legalized: true body: | bb.0: liveins: $vgpr0, $sgpr0, $sgpr1 - ; FAST-LABEL: name: ssube_s32_vss - ; FAST: liveins: $vgpr0, $sgpr0, $sgpr1 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; FAST-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; FAST-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; FAST-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; FAST-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]] - ; GREEDY-LABEL: name: ssube_s32_vss - ; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GREEDY-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; GREEDY-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[COPY4]] + ; CHECK-LABEL: name: ssube_s32_vss + ; CHECK: liveins: $vgpr0, $sgpr0, $sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32) + ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY3]], [[AMDGPU_COPY_VCC_SCC]] %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $sgpr0 %2:_(s32) = COPY $sgpr1 @@ -86,28 +59,19 @@ legalized: true body: | bb.0: liveins: $sgpr0, $sgpr1, $vgpr0 - ; FAST-LABEL: name: ssube_s32_ssv - ; FAST: liveins: $sgpr0, $sgpr1, $vgpr0 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32) - ; FAST-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; FAST-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; FAST-NEXT: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; FAST-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]] - ; GREEDY-LABEL: name: ssube_s32_ssv - ; GREEDY: liveins: $sgpr0, $sgpr1, $vgpr0 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; GREEDY-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; GREEDY-NEXT: [[COPY5:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; GREEDY-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[COPY5]] + ; CHECK-LABEL: name: ssube_s32_ssv + ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY3]], [[COPY4]], [[ICMP]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $vgpr0 @@ -122,24 +86,14 @@ legalized: true body: | bb.0: liveins: $vgpr0, $vgpr1, $sgpr0 - ; FAST-LABEL: name: ssube_s32_vvs - ; FAST: liveins: $vgpr0, $vgpr1, $sgpr0 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32) - ; FAST-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; FAST-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]] - ; GREEDY-LABEL: name: ssube_s32_vvs - ; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; GREEDY-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[COPY3]] + ; CHECK-LABEL: name: ssube_s32_vvs + ; CHECK: liveins: $vgpr0, $vgpr1, $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY2]](s32) + ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:vgpr(s32), [[SSUBE1:%[0-9]+]]:vcc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[AMDGPU_COPY_VCC_SCC]] %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = COPY $sgpr0 @@ -148,32 +102,21 @@ body: | ... --- -name: ssubee_s32_sss_noscc +name: ssube_s32_sss_noscc legalized: true body: | bb.0: liveins: $sgpr0, $sgpr1, $sgpr2 - ; FAST-LABEL: name: ssubee_s32_sss_noscc - ; FAST: liveins: $sgpr0, $sgpr1, $sgpr2 - ; FAST-NEXT: {{ $}} - ; FAST-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; FAST-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; FAST-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32) - ; FAST-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) - ; FAST-NEXT: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[ZEXT]] - ; FAST-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SSUBE1]](s32) - ; GREEDY-LABEL: name: ssubee_s32_sss_noscc - ; GREEDY: liveins: $sgpr0, $sgpr1, $sgpr2 - ; GREEDY-NEXT: {{ $}} - ; GREEDY-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 - ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 - ; GREEDY-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 - ; GREEDY-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY2]](s32) - ; GREEDY-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) - ; GREEDY-NEXT: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[ZEXT]] - ; GREEDY-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[SSUBE1]](s32) + ; CHECK-LABEL: name: ssube_s32_sss_noscc + ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[C]] + ; CHECK-NEXT: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:sgpr(s32) = G_SSUBE [[COPY]], [[COPY1]], [[AND]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $sgpr2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir index e95be13c47d3b..3e46839532917 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass='amdgpu-regbankselect,amdgpu-regbanklegalize' -o - %s | FileCheck %s --- name: uitofp_s @@ -14,6 +14,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[COPY1]](s32) + ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UITOFP]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = G_UITOFP %0 ... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll index 15740ee5476e8..34193762e4501 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll @@ -1,152 +1,967 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s - -define half @v_constained_fma_f16_fpexcept_strict(half %x, half %y, half %z) #0 { -; GCN-LABEL: v_constained_fma_f16_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f16 v0, v0, v1, v2 -; GCN-NEXT: s_setpc_b64 s[30:31] +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX942 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s + +define void @v_constained_fma_f16_fpexcept_strict_uni(half inreg %x, half inreg %y, half inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f16_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s17 +; GFX8-NEXT: v_mov_b32_e32 v3, s18 +; GFX8-NEXT: v_fma_f16 v2, s16, v2, v3 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f16_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s17 +; GFX900-NEXT: v_mov_b32_e32 v3, s18 +; GFX900-NEXT: v_fma_f16 v2, s16, v2, v3 +; GFX900-NEXT: global_store_short v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s1 +; GFX942-NEXT: v_mov_b32_e32 v3, s2 +; GFX942-NEXT: v_fma_f16 v2, s0, v2, v3 +; GFX942-NEXT: global_store_short v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f16 v2.l, s0, s1, v2.l +; GFX11-NEXT: global_store_b16 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f16_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_fmac_f16 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-NEXT: global_store_b16 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call half @llvm.experimental.constrained.fma.f16(half %x, half %y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret half %val + store half %val, ptr addrspace(1) %out + ret void } -define <2 x half> @v_constained_fma_v2f16_fpexcept_strict(<2 x half> %x, <2 x half> %y, <2 x half> %z) #0 { -; GFX9-LABEL: v_constained_fma_v2f16_fpexcept_strict: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 -; GFX9-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f16_fpexcept_strict_div(half %x, half %y, half %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f16_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2 +; GFX8-NEXT: flat_store_short v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] ; -; GFX8-LABEL: v_constained_fma_v2f16_fpexcept_strict: +; GFX900-LABEL: v_constained_fma_f16_fpexcept_strict_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f16 v0, v0, v1, v2 +; GFX900-NEXT: global_store_short v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_fma_f16 v0, v0, v1, v2 +; GFX942-NEXT: global_store_short v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f16 v0.l, v0.l, v1.l, v2.l +; GFX11-NEXT: global_store_b16 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f16_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f16 v0, v0, v1, v2 +; GFX12-NEXT: global_store_b16 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call half @llvm.experimental.constrained.fma.f16(half %x, half %y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store half %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v2f16_fpexcept_strict_uni(<2 x half> inreg %x, <2 x half> inreg %y, <2 x half> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f16_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s17 +; GFX8-NEXT: v_mov_b32_e32 v3, s18 +; GFX8-NEXT: s_lshr_b32 s5, s17, 16 +; GFX8-NEXT: s_lshr_b32 s6, s18, 16 +; GFX8-NEXT: v_fma_f16 v2, s16, v2, v3 +; GFX8-NEXT: s_lshr_b32 s4, s16, 16 +; GFX8-NEXT: v_readfirstlane_b32 s7, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_mov_b32_e32 v3, s6 +; GFX8-NEXT: v_fma_f16 v2, s4, v2, v3 +; GFX8-NEXT: v_readfirstlane_b32 s4, v2 +; GFX8-NEXT: s_and_b32 s4, 0xffff, s4 +; GFX8-NEXT: s_and_b32 s5, 0xffff, s7 +; GFX8-NEXT: s_lshl_b32 s4, s4, 16 +; GFX8-NEXT: s_or_b32 s4, s5, s4 +; GFX8-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f16_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s17 +; GFX900-NEXT: v_mov_b32_e32 v3, s18 +; GFX900-NEXT: v_pk_fma_f16 v2, s16, v2, v3 +; GFX900-NEXT: global_store_dword v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f16_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s1 +; GFX942-NEXT: v_mov_b32_e32 v3, s2 +; GFX942-NEXT: v_pk_fma_f16 v2, s0, v2, v3 +; GFX942-NEXT: global_store_dword v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f16_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v2, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_fma_f16 v2, s0, s1, v2 +; GFX11-NEXT: global_store_b32 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f16_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_lshr_b32 s3, s0, 16 +; GFX12-NEXT: s_lshr_b32 s4, s1, 16 +; GFX12-NEXT: s_lshr_b32 s5, s2, 16 +; GFX12-NEXT: s_fmac_f16 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f16 s5, s3, s4 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: s_pack_ll_b32_b16 s0, s2, s5 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <2 x half> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v2f16_fpexcept_strict_div(<2 x half> %x, <2 x half> %y, <2 x half> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f16_fpexcept_strict_div: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1 +; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2 ; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2 -; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5 +; GFX8-NEXT: v_fma_f16 v1, v5, v6, v7 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX8-NEXT: flat_store_dword v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f16_fpexcept_strict_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_pk_fma_f16 v0, v0, v1, v2 +; GFX900-NEXT: global_store_dword v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f16_fpexcept_strict_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_pk_fma_f16 v0, v0, v1, v2 +; GFX942-NEXT: global_store_dword v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f16_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_pk_fma_f16 v0, v0, v1, v2 +; GFX11-NEXT: global_store_b32 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f16_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_pk_fma_f16 v0, v0, v1, v2 +; GFX12-NEXT: global_store_b32 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <2 x half> %val + store <2 x half> %val, ptr addrspace(1) %out + ret void } -define <3 x half> @v_constained_fma_v3f16_fpexcept_strict(<3 x half> %x, <3 x half> %y, <3 x half> %z) #0 { -; GFX9-LABEL: v_constained_fma_v3f16_fpexcept_strict: +;define void @v_constained_fma_v3f16_fpexcept_strict_uni(<3 x half> inreg %x, <3 x half> inreg %y, <3 x half> inreg %z, ptr addrspace(1) %out) #0 { +; %val = call <3 x half> @llvm.experimental.constrained.fma.v3f16(<3 x half> %x, <3 x half> %y, <3 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") +; store <3 x half> %val, ptr addrspace(1) %out +; ret void +;} + +define void @v_constained_fma_v3f16_fpexcept_strict_div(<3 x half> %x, <3 x half> %y, <3 x half> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v3f16_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v4 +; GFX8-NEXT: flat_store_short v[6:7], v0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 2, v6 +; GFX8-NEXT: v_fma_f16 v2, v8, v9, v10 +; GFX8-NEXT: v_fma_f16 v3, v1, v3, v5 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v6 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v7, vcc +; GFX8-NEXT: flat_store_short v[0:1], v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_v3f16_fpexcept_strict_div: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v2, v4 ; GFX9-NEXT: v_pk_fma_f16 v1, v1, v3, v5 +; GFX9-NEXT: global_store_short v[6:7], v0, off +; GFX9-NEXT: global_store_short_d16_hi v[6:7], v0, off offset:2 +; GFX9-NEXT: global_store_short v[6:7], v1, off offset:4 +; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX8-LABEL: v_constained_fma_v3f16_fpexcept_strict: +; GFX11-LABEL: v_constained_fma_v3f16_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_pk_fma_f16 v0, v0, v2, v4 +; GFX11-NEXT: v_pk_fma_f16 v1, v1, v3, v5 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: global_store_b16 v[6:7], v0, off +; GFX11-NEXT: global_store_d16_hi_b16 v[6:7], v0, off offset:2 +; GFX11-NEXT: global_store_b16 v[6:7], v1, off offset:4 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v3f16_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_pk_fma_f16 v0, v0, v2, v4 +; GFX12-NEXT: v_pk_fma_f16 v1, v1, v3, v5 +; GFX12-NEXT: s_clause 0x2 +; GFX12-NEXT: global_store_b16 v[6:7], v0, off +; GFX12-NEXT: global_store_d16_hi_b16 v[6:7], v0, off offset:2 +; GFX12-NEXT: global_store_b16 v[6:7], v1, off offset:4 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <3 x half> @llvm.experimental.constrained.fma.v3f16(<3 x half> %x, <3 x half> %y, <3 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <3 x half> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v4f16_fpexcept_strict_uni(<4 x half> inreg %x, <4 x half> inreg %y, <4 x half> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v4f16_fpexcept_strict_uni: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v4 -; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4 -; GFX8-NEXT: v_fma_f16 v2, v6, v7, v8 -; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v3, s20 +; GFX8-NEXT: s_lshr_b32 s6, s18, 16 +; GFX8-NEXT: s_lshr_b32 s8, s20, 16 +; GFX8-NEXT: v_fma_f16 v2, s16, v2, v3 +; GFX8-NEXT: s_lshr_b32 s4, s16, 16 +; GFX8-NEXT: v_readfirstlane_b32 s10, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, s6 +; GFX8-NEXT: v_mov_b32_e32 v3, s8 +; GFX8-NEXT: v_fma_f16 v2, s4, v2, v3 +; GFX8-NEXT: v_readfirstlane_b32 s4, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, s19 +; GFX8-NEXT: v_mov_b32_e32 v3, s21 +; GFX8-NEXT: s_lshr_b32 s7, s19, 16 +; GFX8-NEXT: s_lshr_b32 s9, s21, 16 +; GFX8-NEXT: v_fma_f16 v2, s17, v2, v3 +; GFX8-NEXT: s_lshr_b32 s5, s17, 16 +; GFX8-NEXT: v_readfirstlane_b32 s6, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, s7 +; GFX8-NEXT: v_mov_b32_e32 v3, s9 +; GFX8-NEXT: v_fma_f16 v2, s5, v2, v3 +; GFX8-NEXT: v_readfirstlane_b32 s5, v2 +; GFX8-NEXT: s_and_b32 s4, 0xffff, s4 +; GFX8-NEXT: s_and_b32 s7, 0xffff, s10 +; GFX8-NEXT: s_lshl_b32 s4, s4, 16 +; GFX8-NEXT: s_and_b32 s5, 0xffff, s5 +; GFX8-NEXT: s_or_b32 s4, s7, s4 +; GFX8-NEXT: s_and_b32 s6, 0xffff, s6 +; GFX8-NEXT: s_lshl_b32 s5, s5, 16 +; GFX8-NEXT: s_or_b32 s5, s6, s5 +; GFX8-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] - %val = call <3 x half> @llvm.experimental.constrained.fma.v3f16(<3 x half> %x, <3 x half> %y, <3 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <3 x half> %val +; +; GFX900-LABEL: v_constained_fma_v4f16_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s18 +; GFX900-NEXT: v_mov_b32_e32 v3, s20 +; GFX900-NEXT: v_pk_fma_f16 v2, s16, v2, v3 +; GFX900-NEXT: v_mov_b32_e32 v3, s19 +; GFX900-NEXT: v_mov_b32_e32 v4, s21 +; GFX900-NEXT: v_pk_fma_f16 v3, s17, v3, v4 +; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v4f16_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s2 +; GFX942-NEXT: v_mov_b32_e32 v3, s16 +; GFX942-NEXT: v_pk_fma_f16 v2, s0, v2, v3 +; GFX942-NEXT: v_mov_b32_e32 v3, s3 +; GFX942-NEXT: v_mov_b32_e32 v4, s17 +; GFX942-NEXT: v_pk_fma_f16 v3, s1, v3, v4 +; GFX942-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v4f16_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_pk_fma_f16 v2, s0, s2, v2 +; GFX11-NEXT: v_pk_fma_f16 v3, s1, s3, v3 +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v4f16_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_lshr_b32 s4, s0, 16 +; GFX12-NEXT: s_lshr_b32 s5, s2, 16 +; GFX12-NEXT: s_lshr_b32 s6, s16, 16 +; GFX12-NEXT: s_fmac_f16 s16, s0, s2 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f16 s6, s4, s5 +; GFX12-NEXT: s_lshr_b32 s0, s1, 16 +; GFX12-NEXT: s_lshr_b32 s2, s3, 16 +; GFX12-NEXT: s_lshr_b32 s4, s17, 16 +; GFX12-NEXT: s_fmac_f16 s17, s1, s3 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f16 s4, s0, s2 +; GFX12-NEXT: s_pack_ll_b32_b16 s0, s16, s6 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: s_pack_ll_b32_b16 s1, s17, s4 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <4 x half> %val, ptr addrspace(1) %out + ret void } -define <4 x half> @v_constained_fma_v4f16_fpexcept_strict(<4 x half> %x, <4 x half> %y, <4 x half> %z) #0 { -; GFX9-LABEL: v_constained_fma_v4f16_fpexcept_strict: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_fma_f16 v0, v0, v2, v4 -; GFX9-NEXT: v_pk_fma_f16 v1, v1, v3, v5 -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX8-LABEL: v_constained_fma_v4f16_fpexcept_strict: +define void @v_constained_fma_v4f16_fpexcept_strict_div(<4 x half> %x, <4 x half> %y, <4 x half> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v4f16_fpexcept_strict_div: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v4 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v3 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v5 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0 +; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4 +; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1 +; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3 +; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v5 ; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4 -; GFX8-NEXT: v_fma_f16 v2, v6, v8, v10 +; GFX8-NEXT: v_fma_f16 v2, v8, v10, v12 ; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5 -; GFX8-NEXT: v_fma_f16 v3, v7, v9, v11 +; GFX8-NEXT: v_fma_f16 v3, v9, v11, v13 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_v4f16_fpexcept_strict_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_fma_f16 v0, v0, v2, v4 +; GFX9-NEXT: v_pk_fma_f16 v1, v1, v3, v5 +; GFX9-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v4f16_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_pk_fma_f16 v0, v0, v2, v4 +; GFX11-NEXT: v_pk_fma_f16 v1, v1, v3, v5 +; GFX11-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v4f16_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_pk_fma_f16 v0, v0, v2, v4 +; GFX12-NEXT: v_pk_fma_f16 v1, v1, v3, v5 +; GFX12-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <4 x half> %val + store <4 x half> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f16_fpexcept_strict_fneg_uni(half inreg %x, half inreg %y, half inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s16 +; GFX8-NEXT: v_mov_b32_e32 v3, s17 +; GFX8-NEXT: v_fma_f16 v2, v2, v3, -s18 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s16 +; GFX900-NEXT: v_mov_b32_e32 v3, s17 +; GFX900-NEXT: v_fma_f16 v2, v2, v3, -s18 +; GFX900-NEXT: global_store_short v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s0 +; GFX942-NEXT: v_mov_b32_e32 v3, s1 +; GFX942-NEXT: v_fma_f16 v2, v2, v3, -s2 +; GFX942-NEXT: global_store_short v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b16_e32 v2.l, s1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f16 v2.l, s0, v2.l, -s2 +; GFX11-NEXT: global_store_b16 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_xor_b32 s2, s2, 0x8000 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f16 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-NEXT: global_store_b16 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.z = fneg half %z + %val = call half @llvm.experimental.constrained.fma.f16(half %x, half %y, half %neg.z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store half %val, ptr addrspace(1) %out + ret void } -define half @v_constained_fma_f16_fpexcept_strict_fneg(half %x, half %y, half %z) #0 { -; GCN-LABEL: v_constained_fma_f16_fpexcept_strict_fneg: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f16 v0, v0, v1, -v2 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f16_fpexcept_strict_fneg_div(half %x, half %y, half %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f16 v0, v0, v1, -v2 +; GFX8-NEXT: flat_store_short v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f16 v0, v0, v1, -v2 +; GFX900-NEXT: global_store_short v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_fma_f16 v0, v0, v1, -v2 +; GFX942-NEXT: global_store_short v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f16 v0.l, v0.l, v1.l, -v2.l +; GFX11-NEXT: global_store_b16 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f16 v0, v0, v1, -v2 +; GFX12-NEXT: global_store_b16 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.z = fneg half %z %val = call half @llvm.experimental.constrained.fma.f16(half %x, half %y, half %neg.z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret half %val + store half %val, ptr addrspace(1) %out + ret void } -define half @v_constained_fma_f16_fpexcept_strict_fneg_fneg(half %x, half %y, half %z) #0 { -; GCN-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f16 v0, -v0, -v1, v2 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni(half inreg %x, half inreg %y, half inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s17 +; GFX8-NEXT: v_mov_b32_e32 v3, s18 +; GFX8-NEXT: v_fma_f16 v2, -s16, -v2, v3 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s17 +; GFX900-NEXT: v_mov_b32_e32 v3, s18 +; GFX900-NEXT: v_fma_f16 v2, -s16, -v2, v3 +; GFX900-NEXT: global_store_short v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s1 +; GFX942-NEXT: v_mov_b32_e32 v3, s2 +; GFX942-NEXT: v_fma_f16 v2, -s0, -v2, v3 +; GFX942-NEXT: global_store_short v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f16 v2.l, -s0, -s1, v2.l +; GFX11-NEXT: global_store_b16 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000 +; GFX12-NEXT: s_xor_b32 s1, s1, 0x8000 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f16 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-NEXT: global_store_b16 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = fneg half %x + %neg.y = fneg half %y + %val = call half @llvm.experimental.constrained.fma.f16(half %neg.x, half %neg.y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store half %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f16_fpexcept_strict_fneg_fneg_div(half %x, half %y, half %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f16 v0, -v0, -v1, v2 +; GFX8-NEXT: flat_store_short v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f16 v0, -v0, -v1, v2 +; GFX900-NEXT: global_store_short v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_fma_f16 v0, -v0, -v1, v2 +; GFX942-NEXT: global_store_short v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f16 v0.l, -v0.l, -v1.l, v2.l +; GFX11-NEXT: global_store_b16 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f16 v0, -v0, -v1, v2 +; GFX12-NEXT: global_store_b16 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = fneg half %x %neg.y = fneg half %y %val = call half @llvm.experimental.constrained.fma.f16(half %neg.x, half %neg.y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret half %val + store half %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni(half inreg %x, half inreg %y, half inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s17 +; GFX8-NEXT: v_mov_b32_e32 v3, s18 +; GFX8-NEXT: v_fma_f16 v2, |s16|, |v2|, v3 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s17 +; GFX900-NEXT: v_mov_b32_e32 v3, s18 +; GFX900-NEXT: v_fma_f16 v2, |s16|, |v2|, v3 +; GFX900-NEXT: global_store_short v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s1 +; GFX942-NEXT: v_mov_b32_e32 v3, s2 +; GFX942-NEXT: v_fma_f16 v2, |s0|, |v2|, v3 +; GFX942-NEXT: global_store_short v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b16_e32 v2.l, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f16 v2.l, |s0|, |s1|, v2.l +; GFX11-NEXT: global_store_b16 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_and_b32 s0, s0, 0x7fff +; GFX12-NEXT: s_and_b32 s1, s1, 0x7fff +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f16 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-NEXT: global_store_b16 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = call half @llvm.fabs.f16(half %x) #0 + %neg.y = call half @llvm.fabs.f16(half %y) #0 + %val = call half @llvm.experimental.constrained.fma.f16(half %neg.x, half %neg.y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store half %val, ptr addrspace(1) %out + ret void } -define half @v_constained_fma_f16_fpexcept_strict_fabs_fabs(half %x, half %y, half %z) #0 { -; GCN-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f16 v0, |v0|, |v1|, v2 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f16_fpexcept_strict_fabs_fabs_div(half %x, half %y, half %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f16 v0, |v0|, |v1|, v2 +; GFX8-NEXT: flat_store_short v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f16 v0, |v0|, |v1|, v2 +; GFX900-NEXT: global_store_short v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_fma_f16 v0, |v0|, |v1|, v2 +; GFX942-NEXT: global_store_short v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f16 v0.l, |v0.l|, |v1.l|, v2.l +; GFX11-NEXT: global_store_b16 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f16 v0, |v0|, |v1|, v2 +; GFX12-NEXT: global_store_b16 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = call half @llvm.fabs.f16(half %x) #0 %neg.y = call half @llvm.fabs.f16(half %y) #0 %val = call half @llvm.experimental.constrained.fma.f16(half %neg.x, half %neg.y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret half %val + store half %val, ptr addrspace(1) %out + ret void } -define <2 x half> @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg(<2 x half> %x, <2 x half> %y, <2 x half> %z) #0 { -; GFX9-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0] -; GFX9-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_uni(<2 x half> inreg %x, <2 x half> inreg %y, <2 x half> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s16 +; GFX8-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX8-NEXT: v_readfirstlane_b32 s4, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, s17 +; GFX8-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 +; GFX8-NEXT: v_readfirstlane_b32 s5, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_mov_b32_e32 v3, s18 +; GFX8-NEXT: s_lshr_b32 s7, s5, 16 +; GFX8-NEXT: s_lshr_b32 s8, s18, 16 +; GFX8-NEXT: v_fma_f16 v2, s4, v2, v3 +; GFX8-NEXT: s_lshr_b32 s6, s4, 16 +; GFX8-NEXT: v_readfirstlane_b32 s4, v2 +; GFX8-NEXT: v_mov_b32_e32 v2, s7 +; GFX8-NEXT: v_mov_b32_e32 v3, s8 +; GFX8-NEXT: v_fma_f16 v2, s6, v2, v3 +; GFX8-NEXT: v_readfirstlane_b32 s5, v2 +; GFX8-NEXT: s_and_b32 s5, 0xffff, s5 +; GFX8-NEXT: s_and_b32 s4, 0xffff, s4 +; GFX8-NEXT: s_lshl_b32 s5, s5, 16 +; GFX8-NEXT: s_or_b32 s4, s4, s5 +; GFX8-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] ; -; GFX8-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg: +; GFX900-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s17 +; GFX900-NEXT: v_mov_b32_e32 v3, s18 +; GFX900-NEXT: v_pk_fma_f16 v2, s16, v2, v3 neg_lo:[1,1,0] neg_hi:[1,1,0] +; GFX900-NEXT: global_store_dword v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s1 +; GFX942-NEXT: v_mov_b32_e32 v3, s2 +; GFX942-NEXT: v_pk_fma_f16 v2, s0, v2, v3 neg_lo:[1,1,0] neg_hi:[1,1,0] +; GFX942-NEXT: global_store_dword v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v2, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_pk_fma_f16 v2, s0, s1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0] +; GFX11-NEXT: global_store_b32 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_lshr_b32 s3, s0, 16 +; GFX12-NEXT: s_lshr_b32 s4, s1, 16 +; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_xor_b32 s3, s3, 0x8000 +; GFX12-NEXT: s_xor_b32 s1, s1, 0x8000 +; GFX12-NEXT: s_xor_b32 s4, s4, 0x8000 +; GFX12-NEXT: s_lshr_b32 s5, s2, 16 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f16 s2, s0, s1 +; GFX12-NEXT: s_fmac_f16 s5, s3, s4 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: s_pack_ll_b32_b16 s0, s2, s5 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = fneg <2 x half> %x + %neg.y = fneg <2 x half> %y + %val = call <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half> %neg.x, <2 x half> %neg.y, <2 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <2 x half> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_div(<2 x half> %x, <2 x half> %y, <2 x half> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_div: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 ; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1 +; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2 ; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2 -; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5 +; GFX8-NEXT: v_fma_f16 v1, v5, v6, v7 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX8-NEXT: flat_store_dword v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0] +; GFX900-NEXT: global_store_dword v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0] +; GFX942-NEXT: global_store_dword v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0] +; GFX11-NEXT: global_store_b32 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0] +; GFX12-NEXT: global_store_b32 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = fneg <2 x half> %x %neg.y = fneg <2 x half> %y %val = call <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half> %neg.x, <2 x half> %neg.y, <2 x half> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <2 x half> %val + store <2 x half> %val, ptr addrspace(1) %out + ret void } declare half @llvm.fabs.f16(half) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll index 5955c590e9d1c..07865f5b4f3c9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll @@ -1,98 +1,1020 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s - -define float @v_constained_fma_f32_fpexcept_strict(float %x, float %y, float %z) #0 { -; GCN-LABEL: v_constained_fma_f32_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f32 v0, v0, v1, v2 -; GCN-NEXT: s_setpc_b64 s[30:31] +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX900 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s + +define void @v_constained_fma_f32_fpexcept_strict_uni(float inreg %x, float inreg %y, float inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f32_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s17 +; GFX8-NEXT: v_mov_b32_e32 v3, s18 +; GFX8-NEXT: v_fma_f32 v2, s16, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f32_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s17 +; GFX900-NEXT: v_mov_b32_e32 v3, s18 +; GFX900-NEXT: v_fma_f32 v2, s16, v2, v3 +; GFX900-NEXT: global_store_dword v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f32_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s1 +; GFX942-NEXT: v_mov_b32_e32 v3, s2 +; GFX942-NEXT: v_fma_f32 v2, s0, v2, v3 +; GFX942-NEXT: global_store_dword v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f32_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v2, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f32 v2, s0, s1, v2 +; GFX11-NEXT: global_store_b32 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f32_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_fmac_f32 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret float %val + store float %val, ptr addrspace(1) %out + ret void } -define <2 x float> @v_constained_fma_v2f32_fpexcept_strict(<2 x float> %x, <2 x float> %y, <2 x float> %z) #0 { -; GCN-LABEL: v_constained_fma_v2f32_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f32 v0, v0, v2, v4 -; GCN-NEXT: v_fma_f32 v1, v1, v3, v5 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f32_fpexcept_strict_div(float %x, float %y, float %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f32_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f32 v0, v0, v1, v2 +; GFX8-NEXT: flat_store_dword v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f32_fpexcept_strict_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f32 v0, v0, v1, v2 +; GFX900-NEXT: global_store_dword v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f32_fpexcept_strict_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_fma_f32 v0, v0, v1, v2 +; GFX942-NEXT: global_store_dword v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f32_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f32 v0, v0, v1, v2 +; GFX11-NEXT: global_store_b32 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f32_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f32 v0, v0, v1, v2 +; GFX12-NEXT: global_store_b32 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store float %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v2f32_fpexcept_strict_uni(<2 x float> inreg %x, <2 x float> inreg %y, <2 x float> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f32_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v3, s20 +; GFX8-NEXT: v_fma_f32 v2, s16, v2, v3 +; GFX8-NEXT: v_mov_b32_e32 v3, s19 +; GFX8-NEXT: v_mov_b32_e32 v4, s21 +; GFX8-NEXT: v_fma_f32 v3, s17, v3, v4 +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f32_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s18 +; GFX900-NEXT: v_mov_b32_e32 v3, s20 +; GFX900-NEXT: v_fma_f32 v2, s16, v2, v3 +; GFX900-NEXT: v_mov_b32_e32 v3, s19 +; GFX900-NEXT: v_mov_b32_e32 v4, s21 +; GFX900-NEXT: v_fma_f32 v3, s17, v3, v4 +; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f32_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[16:17] +; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[0:1], v[2:3], v[4:5] +; GFX942-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f32_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_fma_f32 v2, s0, s2, v2 +; GFX11-NEXT: v_fma_f32 v3, s1, s3, v3 +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f32_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_fmac_f32 s16, s0, s2 +; GFX12-NEXT: s_fmac_f32 s17, s1, s3 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> %x, <2 x float> %y, <2 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <2 x float> %val + store <2 x float> %val, ptr addrspace(1) %out + ret void } -define <3 x float> @v_constained_fma_v3f32_fpexcept_strict(<3 x float> %x, <3 x float> %y, <3 x float> %z) #0 { -; GCN-LABEL: v_constained_fma_v3f32_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f32 v0, v0, v3, v6 -; GCN-NEXT: v_fma_f32 v1, v1, v4, v7 -; GCN-NEXT: v_fma_f32 v2, v2, v5, v8 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_v2f32_fpexcept_strict_div(<2 x float> %x, <2 x float> %y, <2 x float> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f32_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f32 v0, v0, v2, v4 +; GFX8-NEXT: v_fma_f32 v1, v1, v3, v5 +; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f32_fpexcept_strict_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f32 v0, v0, v2, v4 +; GFX900-NEXT: v_fma_f32 v1, v1, v3, v5 +; GFX900-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f32_fpexcept_strict_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[2:3], v[4:5] +; GFX942-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f32_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f32 v0, v0, v2, v4 +; GFX11-NEXT: v_fma_f32 v1, v1, v3, v5 +; GFX11-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f32_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f32 v0, v0, v2, v4 +; GFX12-NEXT: v_fma_f32 v1, v1, v3, v5 +; GFX12-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> %x, <2 x float> %y, <2 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <2 x float> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v3f32_fpexcept_strict_uni(<3 x float> inreg %x, <3 x float> inreg %y, <3 x float> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v3f32_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s19 +; GFX8-NEXT: v_mov_b32_e32 v3, s22 +; GFX8-NEXT: v_fma_f32 v2, s16, v2, v3 +; GFX8-NEXT: v_mov_b32_e32 v3, s20 +; GFX8-NEXT: v_mov_b32_e32 v4, s23 +; GFX8-NEXT: v_fma_f32 v3, s17, v3, v4 +; GFX8-NEXT: v_mov_b32_e32 v4, s21 +; GFX8-NEXT: v_mov_b32_e32 v5, s24 +; GFX8-NEXT: v_fma_f32 v4, s18, v4, v5 +; GFX8-NEXT: flat_store_dwordx3 v[0:1], v[2:4] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v3f32_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s19 +; GFX900-NEXT: v_mov_b32_e32 v3, s22 +; GFX900-NEXT: v_fma_f32 v2, s16, v2, v3 +; GFX900-NEXT: v_mov_b32_e32 v3, s20 +; GFX900-NEXT: v_mov_b32_e32 v4, s23 +; GFX900-NEXT: v_fma_f32 v3, s17, v3, v4 +; GFX900-NEXT: v_mov_b32_e32 v4, s21 +; GFX900-NEXT: v_mov_b32_e32 v5, s24 +; GFX900-NEXT: v_fma_f32 v4, s18, v4, v5 +; GFX900-NEXT: global_store_dwordx3 v[0:1], v[2:4], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v3f32_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: s_mov_b32 s4, s3 +; GFX942-NEXT: s_mov_b32 s5, s16 +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[4:5] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[18:19] +; GFX942-NEXT: s_mov_b32 s6, s17 +; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[0:1], v[2:3], v[4:5] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[20:21] +; GFX942-NEXT: v_readfirstlane_b32 s0, v2 +; GFX942-NEXT: v_readfirstlane_b32 s1, v3 +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[6:7] +; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[2:3], v[2:3], v[4:5] +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_readfirstlane_b32 s2, v2 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_mov_b32_e32 v4, s2 +; GFX942-NEXT: v_mov_b32_e32 v3, s1 +; GFX942-NEXT: v_mov_b32_e32 v2, s0 +; GFX942-NEXT: global_store_dwordx3 v[0:1], v[2:4], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v3f32_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s18 :: v_dual_mov_b32 v3, s19 +; GFX11-NEXT: v_mov_b32_e32 v4, s20 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_fma_f32 v2, s0, s3, v2 +; GFX11-NEXT: v_fma_f32 v3, s1, s16, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_fma_f32 v4, s2, s17, v4 +; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v3f32_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_mov_b32 s4, s18 +; GFX12-NEXT: s_mov_b32 s5, s19 +; GFX12-NEXT: s_mov_b32 s6, s20 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f32 s4, s0, s3 +; GFX12-NEXT: s_fmac_f32 s5, s1, s16 +; GFX12-NEXT: s_fmac_f32 s6, s2, s17 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 +; GFX12-NEXT: v_mov_b32_e32 v4, s6 +; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off +; GFX12-NEXT: s_setpc_b64 s[30:31] +; FIXME: Optimize readfirstlane %val = call <3 x float> @llvm.experimental.constrained.fma.v3f32(<3 x float> %x, <3 x float> %y, <3 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <3 x float> %val -} - -define <4 x float> @v_constained_fma_v4f32_fpexcept_strict(<4 x float> %x, <4 x float> %y, <4 x float> %z) #0 { -; GCN-LABEL: v_constained_fma_v4f32_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f32 v0, v0, v4, v8 -; GCN-NEXT: v_fma_f32 v1, v1, v5, v9 -; GCN-NEXT: v_fma_f32 v2, v2, v6, v10 -; GCN-NEXT: v_fma_f32 v3, v3, v7, v11 -; GCN-NEXT: s_setpc_b64 s[30:31] + store <3 x float> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v3f32_fpexcept_strict_div(<3 x float> %x, <3 x float> %y, <3 x float> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v3f32_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f32 v0, v0, v3, v6 +; GFX8-NEXT: v_fma_f32 v1, v1, v4, v7 +; GFX8-NEXT: v_fma_f32 v2, v2, v5, v8 +; GFX8-NEXT: flat_store_dwordx3 v[9:10], v[0:2] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v3f32_fpexcept_strict_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f32 v0, v0, v3, v6 +; GFX900-NEXT: v_fma_f32 v1, v1, v4, v7 +; GFX900-NEXT: v_fma_f32 v2, v2, v5, v8 +; GFX900-NEXT: global_store_dwordx3 v[9:10], v[0:2], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v3f32_fpexcept_strict_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v12, v3 +; GFX942-NEXT: v_mov_b32_e32 v13, v4 +; GFX942-NEXT: v_mov_b32_e32 v4, v5 +; GFX942-NEXT: v_mov_b32_e32 v14, v9 +; GFX942-NEXT: v_mov_b32_e32 v15, v10 +; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[12:13], v[6:7] +; GFX942-NEXT: v_pk_fma_f32 v[2:3], v[2:3], v[4:5], v[8:9] +; GFX942-NEXT: global_store_dwordx3 v[14:15], v[0:2], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v3f32_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f32 v0, v0, v3, v6 +; GFX11-NEXT: v_fma_f32 v1, v1, v4, v7 +; GFX11-NEXT: v_fma_f32 v2, v2, v5, v8 +; GFX11-NEXT: global_store_b96 v[9:10], v[0:2], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v3f32_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f32 v0, v0, v3, v6 +; GFX12-NEXT: v_fma_f32 v1, v1, v4, v7 +; GFX12-NEXT: v_fma_f32 v2, v2, v5, v8 +; GFX12-NEXT: global_store_b96 v[9:10], v[0:2], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <3 x float> @llvm.experimental.constrained.fma.v3f32(<3 x float> %x, <3 x float> %y, <3 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <3 x float> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v4f32_fpexcept_strict_uni(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v4f32_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s20 +; GFX8-NEXT: v_mov_b32_e32 v3, s24 +; GFX8-NEXT: v_fma_f32 v2, s16, v2, v3 +; GFX8-NEXT: v_mov_b32_e32 v3, s21 +; GFX8-NEXT: v_mov_b32_e32 v4, s25 +; GFX8-NEXT: v_fma_f32 v3, s17, v3, v4 +; GFX8-NEXT: v_mov_b32_e32 v4, s22 +; GFX8-NEXT: v_mov_b32_e32 v5, s26 +; GFX8-NEXT: v_fma_f32 v4, s18, v4, v5 +; GFX8-NEXT: v_mov_b32_e32 v5, s23 +; GFX8-NEXT: v_mov_b32_e32 v6, s27 +; GFX8-NEXT: v_fma_f32 v5, s19, v5, v6 +; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v4f32_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s20 +; GFX900-NEXT: v_mov_b32_e32 v3, s24 +; GFX900-NEXT: v_fma_f32 v2, s16, v2, v3 +; GFX900-NEXT: v_mov_b32_e32 v3, s21 +; GFX900-NEXT: v_mov_b32_e32 v4, s25 +; GFX900-NEXT: v_fma_f32 v3, s17, v3, v4 +; GFX900-NEXT: v_mov_b32_e32 v4, s22 +; GFX900-NEXT: v_mov_b32_e32 v5, s26 +; GFX900-NEXT: v_fma_f32 v4, s18, v4, v5 +; GFX900-NEXT: v_mov_b32_e32 v5, s23 +; GFX900-NEXT: v_mov_b32_e32 v6, s27 +; GFX900-NEXT: v_fma_f32 v5, s19, v5, v6 +; GFX900-NEXT: global_store_dwordx4 v[0:1], v[2:5], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v4f32_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[16:17] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[20:21] +; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[0:1], v[2:3], v[4:5] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[22:23] +; GFX942-NEXT: v_readfirstlane_b32 s0, v2 +; GFX942-NEXT: v_readfirstlane_b32 s1, v3 +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[18:19] +; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[2:3], v[2:3], v[4:5] +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_readfirstlane_b32 s2, v2 +; GFX942-NEXT: v_readfirstlane_b32 s3, v3 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v4f32_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21 +; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_fma_f32 v2, s0, s16, v2 +; GFX11-NEXT: v_fma_f32 v3, s1, s17, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_fma_f32 v4, s2, s18, v4 +; GFX11-NEXT: v_fma_f32 v5, s3, s19, v5 +; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v4f32_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_fmac_f32 s20, s0, s16 +; GFX12-NEXT: s_fmac_f32 s21, s1, s17 +; GFX12-NEXT: s_fmac_f32 s22, s2, s18 +; GFX12-NEXT: s_fmac_f32 s23, s3, s19 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23 +; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <4 x float> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v4f32_fpexcept_strict_div(<4 x float> %x, <4 x float> %y, <4 x float> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v4f32_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f32 v0, v0, v4, v8 +; GFX8-NEXT: v_fma_f32 v1, v1, v5, v9 +; GFX8-NEXT: v_fma_f32 v2, v2, v6, v10 +; GFX8-NEXT: v_fma_f32 v3, v3, v7, v11 +; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[0:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v4f32_fpexcept_strict_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f32 v0, v0, v4, v8 +; GFX900-NEXT: v_fma_f32 v1, v1, v5, v9 +; GFX900-NEXT: v_fma_f32 v2, v2, v6, v10 +; GFX900-NEXT: v_fma_f32 v3, v3, v7, v11 +; GFX900-NEXT: global_store_dwordx4 v[12:13], v[0:3], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v4f32_fpexcept_strict_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[4:5], v[8:9] +; GFX942-NEXT: v_pk_fma_f32 v[2:3], v[2:3], v[6:7], v[10:11] +; GFX942-NEXT: global_store_dwordx4 v[12:13], v[0:3], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v4f32_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f32 v0, v0, v4, v8 +; GFX11-NEXT: v_fma_f32 v1, v1, v5, v9 +; GFX11-NEXT: v_fma_f32 v2, v2, v6, v10 +; GFX11-NEXT: v_fma_f32 v3, v3, v7, v11 +; GFX11-NEXT: global_store_b128 v[12:13], v[0:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v4f32_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f32 v0, v0, v4, v8 +; GFX12-NEXT: v_fma_f32 v1, v1, v5, v9 +; GFX12-NEXT: v_fma_f32 v2, v2, v6, v10 +; GFX12-NEXT: v_fma_f32 v3, v3, v7, v11 +; GFX12-NEXT: global_store_b128 v[12:13], v[0:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <4 x float> %val + store <4 x float> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f32_fpexcept_strict_fneg_uni(float inreg %x, float inreg %y, float inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s16 +; GFX8-NEXT: v_mov_b32_e32 v3, s17 +; GFX8-NEXT: v_fma_f32 v2, v2, v3, -s18 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s16 +; GFX900-NEXT: v_mov_b32_e32 v3, s17 +; GFX900-NEXT: v_fma_f32 v2, v2, v3, -s18 +; GFX900-NEXT: global_store_dword v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s0 +; GFX942-NEXT: v_mov_b32_e32 v3, s1 +; GFX942-NEXT: v_fma_f32 v2, v2, v3, -s2 +; GFX942-NEXT: global_store_dword v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v2, s1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f32 v2, s0, v2, -s2 +; GFX11-NEXT: global_store_b32 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_xor_b32 s2, s2, 0x80000000 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f32 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.z = fneg float %z + %val = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float %neg.z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store float %val, ptr addrspace(1) %out + ret void } -define float @v_constained_fma_f32_fpexcept_strict_fneg(float %x, float %y, float %z) #0 { -; GCN-LABEL: v_constained_fma_f32_fpexcept_strict_fneg: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f32 v0, v0, v1, -v2 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f32_fpexcept_strict_fneg_div(float %x, float %y, float %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f32 v0, v0, v1, -v2 +; GFX8-NEXT: flat_store_dword v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f32 v0, v0, v1, -v2 +; GFX900-NEXT: global_store_dword v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_fma_f32 v0, v0, v1, -v2 +; GFX942-NEXT: global_store_dword v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f32 v0, v0, v1, -v2 +; GFX11-NEXT: global_store_b32 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f32 v0, v0, v1, -v2 +; GFX12-NEXT: global_store_b32 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.z = fneg float %z %val = call float @llvm.experimental.constrained.fma.f32(float %x, float %y, float %neg.z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret float %val + store float %val, ptr addrspace(1) %out + ret void } -define float @v_constained_fma_f32_fpexcept_strict_fneg_fneg(float %x, float %y, float %z) #0 { -; GCN-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f32 v0, -v0, -v1, v2 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f32_fpexcept_strict_fneg_fneg_uni(float inreg %x, float inreg %y, float inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s17 +; GFX8-NEXT: v_mov_b32_e32 v3, s18 +; GFX8-NEXT: v_fma_f32 v2, -s16, -v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s17 +; GFX900-NEXT: v_mov_b32_e32 v3, s18 +; GFX900-NEXT: v_fma_f32 v2, -s16, -v2, v3 +; GFX900-NEXT: global_store_dword v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s1 +; GFX942-NEXT: v_mov_b32_e32 v3, s2 +; GFX942-NEXT: v_fma_f32 v2, -s0, -v2, v3 +; GFX942-NEXT: global_store_dword v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v2, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f32 v2, -s0, -s1, v2 +; GFX11-NEXT: global_store_b32 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_xor_b32 s0, s0, 0x80000000 +; GFX12-NEXT: s_xor_b32 s1, s1, 0x80000000 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f32 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = fneg float %x %neg.y = fneg float %y %val = call float @llvm.experimental.constrained.fma.f32(float %neg.x, float %neg.y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret float %val + store float %val, ptr addrspace(1) %out + ret void } -define float @v_constained_fma_f32_fpexcept_strict_fabs_fabs(float %x, float %y, float %z) #0 { -; GCN-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f32 v0, |v0|, |v1|, v2 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f32_fpexcept_strict_fneg_fneg_div(float %x, float %y, float %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f32 v0, -v0, -v1, v2 +; GFX8-NEXT: flat_store_dword v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f32 v0, -v0, -v1, v2 +; GFX900-NEXT: global_store_dword v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_fma_f32 v0, -v0, -v1, v2 +; GFX942-NEXT: global_store_dword v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f32 v0, -v0, -v1, v2 +; GFX11-NEXT: global_store_b32 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f32_fpexcept_strict_fneg_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f32 v0, -v0, -v1, v2 +; GFX12-NEXT: global_store_b32 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = fneg float %x + %neg.y = fneg float %y + %val = call float @llvm.experimental.constrained.fma.f32(float %neg.x, float %neg.y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store float %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f32_fpexcept_strict_fabs_fabs_uni(float inreg %x, float inreg %y, float inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s17 +; GFX8-NEXT: v_mov_b32_e32 v3, s18 +; GFX8-NEXT: v_fma_f32 v2, |s16|, |v2|, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s17 +; GFX900-NEXT: v_mov_b32_e32 v3, s18 +; GFX900-NEXT: v_fma_f32 v2, |s16|, |v2|, v3 +; GFX900-NEXT: global_store_dword v[0:1], v2, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s1 +; GFX942-NEXT: v_mov_b32_e32 v3, s2 +; GFX942-NEXT: v_fma_f32 v2, |s0|, |v2|, v3 +; GFX942-NEXT: global_store_dword v[0:1], v2, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v2, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f32 v2, |s0|, |s1|, v2 +; GFX11-NEXT: global_store_b32 v[0:1], v2, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_bitset0_b32 s0, 31 +; GFX12-NEXT: s_bitset0_b32 s1, 31 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f32 s2, s0, s1 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_mov_b32_e32 v2, s2 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = call float @llvm.fabs.f32(float %x) #0 %neg.y = call float @llvm.fabs.f32(float %y) #0 %val = call float @llvm.experimental.constrained.fma.f32(float %neg.x, float %neg.y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret float %val + store float %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f32_fpexcept_strict_fabs_fabs_div(float %x, float %y, float %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f32 v0, |v0|, |v1|, v2 +; GFX8-NEXT: flat_store_dword v[3:4], v0 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f32 v0, |v0|, |v1|, v2 +; GFX900-NEXT: global_store_dword v[3:4], v0, off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v6, v3 +; GFX942-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-NEXT: v_fma_f32 v0, |v0|, |v1|, v2 +; GFX942-NEXT: global_store_dword v[6:7], v0, off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f32 v0, |v0|, |v1|, v2 +; GFX11-NEXT: global_store_b32 v[3:4], v0, off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f32_fpexcept_strict_fabs_fabs_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f32 v0, |v0|, |v1|, v2 +; GFX12-NEXT: global_store_b32 v[3:4], v0, off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = call float @llvm.fabs.f32(float %x) #0 + %neg.y = call float @llvm.fabs.f32(float %y) #0 + %val = call float @llvm.experimental.constrained.fma.f32(float %neg.x, float %neg.y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store float %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_uni(<2 x float> inreg %x, <2 x float> inreg %y, <2 x float> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v4, s20 +; GFX8-NEXT: v_mov_b32_e32 v3, s19 +; GFX8-NEXT: v_fma_f32 v2, -s16, -v2, v4 +; GFX8-NEXT: v_mov_b32_e32 v4, s21 +; GFX8-NEXT: v_fma_f32 v3, -s17, -v3, v4 +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s18 +; GFX900-NEXT: v_mov_b32_e32 v4, s20 +; GFX900-NEXT: v_mov_b32_e32 v3, s19 +; GFX900-NEXT: v_fma_f32 v2, -s16, -v2, v4 +; GFX900-NEXT: v_mov_b32_e32 v4, s21 +; GFX900-NEXT: v_fma_f32 v3, -s17, -v3, v4 +; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b32_e32 v2, s0 +; GFX942-NEXT: v_mov_b32_e32 v3, s1 +; GFX942-NEXT: v_mov_b32_e32 v4, s2 +; GFX942-NEXT: v_mov_b32_e32 v5, s3 +; GFX942-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX942-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX942-NEXT: v_xor_b32_e32 v4, 0x80000000, v4 +; GFX942-NEXT: v_xor_b32_e32 v5, 0x80000000, v5 +; GFX942-NEXT: v_pk_fma_f32 v[2:3], v[2:3], v[4:5], s[16:17] +; GFX942-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_fma_f32 v2, -s0, -s2, v2 +; GFX11-NEXT: v_fma_f32 v3, -s1, -s3, v3 +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_xor_b32 s0, s0, 0x80000000 +; GFX12-NEXT: s_xor_b32 s1, s1, 0x80000000 +; GFX12-NEXT: s_xor_b32 s2, s2, 0x80000000 +; GFX12-NEXT: s_xor_b32 s3, s3, 0x80000000 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_fmac_f32 s16, s0, s2 +; GFX12-NEXT: s_fmac_f32 s17, s1, s3 +; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GFX12-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = fneg <2 x float> %x + %neg.y = fneg <2 x float> %y + %val = call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> %neg.x, <2 x float> %neg.y, <2 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <2 x float> %val, ptr addrspace(1) %out + ret void } -define <2 x float> @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg(<2 x float> %x, <2 x float> %y, <2 x float> %z) #0 { -; GCN-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f32 v0, -v0, -v2, v4 -; GCN-NEXT: v_fma_f32 v1, -v1, -v3, v5 -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_div(<2 x float> %x, <2 x float> %y, <2 x float> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f32 v0, -v0, -v2, v4 +; GFX8-NEXT: v_fma_f32 v1, -v1, -v3, v5 +; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_div: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_fma_f32 v0, -v0, -v2, v4 +; GFX900-NEXT: v_fma_f32 v1, -v1, -v3, v5 +; GFX900-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_div: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX942-NEXT: v_xor_b32_e32 v1, 0x80000000, v1 +; GFX942-NEXT: v_xor_b32_e32 v2, 0x80000000, v2 +; GFX942-NEXT: v_xor_b32_e32 v3, 0x80000000, v3 +; GFX942-NEXT: v_pk_fma_f32 v[0:1], v[0:1], v[2:3], v[4:5] +; GFX942-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f32 v0, -v0, -v2, v4 +; GFX11-NEXT: v_fma_f32 v1, -v1, -v3, v5 +; GFX11-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f32_fpexcept_strict_fneg_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f32 v0, -v0, -v2, v4 +; GFX12-NEXT: v_fma_f32 v1, -v1, -v3, v5 +; GFX12-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = fneg <2 x float> %x %neg.y = fneg <2 x float> %y %val = call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> %neg.x, <2 x float> %neg.y, <2 x float> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <2 x float> %val + store <2 x float> %val, ptr addrspace(1) %out + ret void } declare float @llvm.fabs.f32(float) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll index 04a07c42c934c..0c949fb1ae763 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll @@ -1,98 +1,1081 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s - -define double @v_constained_fma_f64_fpexcept_strict(double %x, double %y, double %z) #0 { -; GCN-LABEL: v_constained_fma_f64_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5] -; GCN-NEXT: s_setpc_b64 s[30:31] +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX900 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX942 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s + +define void @v_constained_fma_f64_fpexcept_strict_uni(double inreg %x, double inreg %y, double inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f64_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v4, s20 +; GFX8-NEXT: v_mov_b32_e32 v3, s19 +; GFX8-NEXT: v_mov_b32_e32 v5, s21 +; GFX8-NEXT: v_fma_f64 v[2:3], s[16:17], v[2:3], v[4:5] +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f64_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s18 +; GFX900-NEXT: v_mov_b32_e32 v4, s20 +; GFX900-NEXT: v_mov_b32_e32 v3, s19 +; GFX900-NEXT: v_mov_b32_e32 v5, s21 +; GFX900-NEXT: v_fma_f64 v[2:3], s[16:17], v[2:3], v[4:5] +; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f64_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[16:17] +; GFX942-NEXT: v_fma_f64 v[2:3], s[0:1], v[2:3], v[4:5] +; GFX942-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f64_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f64 v[2:3], s[0:1], s[2:3], v[2:3] +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f64_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_fma_f64 v[2:3], s[0:1], s[2:3], v[2:3] +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call double @llvm.experimental.constrained.fma.f64(double %x, double %y, double %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret double %val + store double %val, ptr addrspace(1) %out + ret void } -define <2 x double> @v_constained_fma_v2f64_fpexcept_strict(<2 x double> %x, <2 x double> %y, <2 x double> %z) #0 { -; GCN-LABEL: v_constained_fma_v2f64_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[8:9] -; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11] -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f64_fpexcept_strict_div(double %x, double %y, double %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f64_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5] +; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_f64_fpexcept_strict_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5] +; GFX9-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f64_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5] +; GFX11-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f64_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5] +; GFX12-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call double @llvm.experimental.constrained.fma.f64(double %x, double %y, double %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store double %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v2f64_fpexcept_strict_uni(<2 x double> inreg %x, <2 x double> inreg %y, <2 x double> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f64_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s20 +; GFX8-NEXT: v_mov_b32_e32 v4, s24 +; GFX8-NEXT: v_mov_b32_e32 v3, s21 +; GFX8-NEXT: v_mov_b32_e32 v5, s25 +; GFX8-NEXT: v_fma_f64 v[2:3], s[16:17], v[2:3], v[4:5] +; GFX8-NEXT: v_mov_b32_e32 v4, s22 +; GFX8-NEXT: v_mov_b32_e32 v6, s26 +; GFX8-NEXT: v_mov_b32_e32 v5, s23 +; GFX8-NEXT: v_mov_b32_e32 v7, s27 +; GFX8-NEXT: v_fma_f64 v[4:5], s[18:19], v[4:5], v[6:7] +; GFX8-NEXT: v_readfirstlane_b32 s4, v2 +; GFX8-NEXT: v_readfirstlane_b32 s5, v3 +; GFX8-NEXT: v_readfirstlane_b32 s6, v4 +; GFX8-NEXT: v_readfirstlane_b32 s7, v5 +; GFX8-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 +; GFX8-NEXT: v_mov_b32_e32 v4, s6 +; GFX8-NEXT: v_mov_b32_e32 v5, s7 +; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f64_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s20 +; GFX900-NEXT: v_mov_b32_e32 v4, s24 +; GFX900-NEXT: v_mov_b32_e32 v3, s21 +; GFX900-NEXT: v_mov_b32_e32 v5, s25 +; GFX900-NEXT: v_fma_f64 v[2:3], s[16:17], v[2:3], v[4:5] +; GFX900-NEXT: v_mov_b32_e32 v4, s22 +; GFX900-NEXT: v_mov_b32_e32 v6, s26 +; GFX900-NEXT: v_mov_b32_e32 v5, s23 +; GFX900-NEXT: v_mov_b32_e32 v7, s27 +; GFX900-NEXT: v_fma_f64 v[4:5], s[18:19], v[4:5], v[6:7] +; GFX900-NEXT: v_readfirstlane_b32 s4, v2 +; GFX900-NEXT: v_readfirstlane_b32 s5, v3 +; GFX900-NEXT: v_readfirstlane_b32 s6, v4 +; GFX900-NEXT: v_readfirstlane_b32 s7, v5 +; GFX900-NEXT: v_mov_b32_e32 v2, s4 +; GFX900-NEXT: v_mov_b32_e32 v3, s5 +; GFX900-NEXT: v_mov_b32_e32 v4, s6 +; GFX900-NEXT: v_mov_b32_e32 v5, s7 +; GFX900-NEXT: global_store_dwordx4 v[0:1], v[2:5], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f64_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[16:17] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[20:21] +; GFX942-NEXT: v_fma_f64 v[2:3], s[0:1], v[2:3], v[4:5] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[22:23] +; GFX942-NEXT: v_readfirstlane_b32 s0, v2 +; GFX942-NEXT: v_readfirstlane_b32 s1, v3 +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[18:19] +; GFX942-NEXT: v_fma_f64 v[2:3], s[2:3], v[2:3], v[4:5] +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_readfirstlane_b32 s2, v2 +; GFX942-NEXT: v_readfirstlane_b32 s3, v3 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f64_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23 +; GFX11-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_fma_f64 v[4:5], s[2:3], s[18:19], v[4:5] +; GFX11-NEXT: v_fma_f64 v[2:3], s[0:1], s[16:17], v[2:3] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_readfirstlane_b32 s3, v5 +; GFX11-NEXT: v_readfirstlane_b32 s2, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_readfirstlane_b32 s0, v2 +; GFX11-NEXT: v_readfirstlane_b32 s1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f64_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23 +; GFX12-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_fma_f64 v[4:5], s[2:3], s[18:19], v[4:5] +; GFX12-NEXT: v_fma_f64 v[2:3], s[0:1], s[16:17], v[2:3] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_readfirstlane_b32 s3, v5 +; GFX12-NEXT: v_readfirstlane_b32 s2, v4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-NEXT: s_wait_alu depctr_va_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 +; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + +; FIXME: Optimize readfirstlane %val = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %x, <2 x double> %y, <2 x double> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <2 x double> %val + store <2 x double> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v2f64_fpexcept_strict_div(<2 x double> %x, <2 x double> %y, <2 x double> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f64_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[8:9] +; GFX8-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11] +; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[0:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_v2f64_fpexcept_strict_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[8:9] +; GFX9-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11] +; GFX9-NEXT: global_store_dwordx4 v[12:13], v[0:3], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f64_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[8:9] +; GFX11-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11] +; GFX11-NEXT: global_store_b128 v[12:13], v[0:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f64_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f64 v[0:1], v[0:1], v[4:5], v[8:9] +; GFX12-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[10:11] +; GFX12-NEXT: global_store_b128 v[12:13], v[0:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %x, <2 x double> %y, <2 x double> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <2 x double> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v3f64_fpexcept_strict_uni(<3 x double> inreg %x, <3 x double> inreg %y, <3 x double> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v3f64_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v6, s22 +; GFX8-NEXT: v_mov_b32_e32 v8, s28 +; GFX8-NEXT: v_mov_b32_e32 v7, s23 +; GFX8-NEXT: v_mov_b32_e32 v9, s29 +; GFX8-NEXT: v_fma_f64 v[6:7], s[16:17], v[6:7], v[8:9] +; GFX8-NEXT: v_mov_b32_e32 v8, s24 +; GFX8-NEXT: v_mov_b32_e32 v9, s25 +; GFX8-NEXT: v_fma_f64 v[8:9], s[18:19], v[8:9], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v0, s26 +; GFX8-NEXT: v_mov_b32_e32 v1, s27 +; GFX8-NEXT: v_fma_f64 v[0:1], s[20:21], v[0:1], v[2:3] +; GFX8-NEXT: v_add_u32_e32 v2, vcc, 16, v4 +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[6:9] +; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v3f64_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v6, s22 +; GFX900-NEXT: v_mov_b32_e32 v8, s28 +; GFX900-NEXT: v_mov_b32_e32 v7, s23 +; GFX900-NEXT: v_mov_b32_e32 v9, s29 +; GFX900-NEXT: v_fma_f64 v[6:7], s[16:17], v[6:7], v[8:9] +; GFX900-NEXT: v_mov_b32_e32 v8, s24 +; GFX900-NEXT: v_mov_b32_e32 v9, s25 +; GFX900-NEXT: v_fma_f64 v[8:9], s[18:19], v[8:9], v[0:1] +; GFX900-NEXT: v_mov_b32_e32 v0, s26 +; GFX900-NEXT: v_mov_b32_e32 v1, s27 +; GFX900-NEXT: v_fma_f64 v[0:1], s[20:21], v[0:1], v[2:3] +; GFX900-NEXT: global_store_dwordx4 v[4:5], v[6:9], off +; GFX900-NEXT: global_store_dwordx2 v[4:5], v[0:1], off offset:16 +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v3f64_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[18:19] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[24:25] +; GFX942-NEXT: v_fma_f64 v[2:3], s[0:1], v[2:3], v[4:5] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[26:27] +; GFX942-NEXT: v_readfirstlane_b32 s0, v2 +; GFX942-NEXT: v_readfirstlane_b32 s1, v3 +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[20:21] +; GFX942-NEXT: v_fma_f64 v[2:3], s[2:3], v[2:3], v[4:5] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[28:29] +; GFX942-NEXT: v_readfirstlane_b32 s2, v2 +; GFX942-NEXT: v_readfirstlane_b32 s3, v3 +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[22:23] +; GFX942-NEXT: v_fma_f64 v[6:7], s[16:17], v[2:3], v[4:5] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off +; GFX942-NEXT: global_store_dwordx2 v[0:1], v[6:7], off offset:16 +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v3f64_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v4, s26 :: v_dual_mov_b32 v5, s27 +; GFX11-NEXT: v_dual_mov_b32 v2, s24 :: v_dual_mov_b32 v3, s25 +; GFX11-NEXT: v_dual_mov_b32 v6, s28 :: v_dual_mov_b32 v7, s29 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_fma_f64 v[4:5], s[2:3], s[20:21], v[4:5] +; GFX11-NEXT: v_fma_f64 v[2:3], s[0:1], s[18:19], v[2:3] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_fma_f64 v[6:7], s[16:17], s[22:23], v[6:7] +; GFX11-NEXT: v_readfirstlane_b32 s3, v5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_readfirstlane_b32 s2, v4 +; GFX11-NEXT: v_readfirstlane_b32 s0, v2 +; GFX11-NEXT: v_readfirstlane_b32 s1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX11-NEXT: global_store_b64 v[0:1], v[6:7], off offset:16 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v3f64_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v4, s26 :: v_dual_mov_b32 v5, s27 +; GFX12-NEXT: v_dual_mov_b32 v2, s24 :: v_dual_mov_b32 v3, s25 +; GFX12-NEXT: v_dual_mov_b32 v6, s28 :: v_dual_mov_b32 v7, s29 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_fma_f64 v[4:5], s[2:3], s[20:21], v[4:5] +; GFX12-NEXT: v_fma_f64 v[2:3], s[0:1], s[18:19], v[2:3] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_fma_f64 v[6:7], s[16:17], s[22:23], v[6:7] +; GFX12-NEXT: v_readfirstlane_b32 s3, v5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-NEXT: v_readfirstlane_b32 s2, v4 +; GFX12-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-NEXT: s_wait_alu depctr_va_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 +; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX12-NEXT: global_store_b64 v[0:1], v[6:7], off offset:16 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <3 x double> @llvm.experimental.constrained.fma.v3f64(<3 x double> %x, <3 x double> %y, <3 x double> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <3 x double> %val, ptr addrspace(1) %out + ret void } -define <3 x double> @v_constained_fma_v3f64_fpexcept_strict(<3 x double> %x, <3 x double> %y, <3 x double> %z) #0 { -; GCN-LABEL: v_constained_fma_v3f64_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[6:7], v[12:13] -; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[8:9], v[14:15] -; GCN-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], v[16:17] -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_v3f64_fpexcept_strict_div(<3 x double> %x, <3 x double> %y, <3 x double> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v3f64_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f64 v[0:1], v[0:1], v[6:7], v[12:13] +; GFX8-NEXT: v_fma_f64 v[2:3], v[2:3], v[8:9], v[14:15] +; GFX8-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], v[16:17] +; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[0:3] +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v18 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v19, vcc +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_v3f64_fpexcept_strict_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_fma_f64 v[0:1], v[0:1], v[6:7], v[12:13] +; GFX9-NEXT: v_fma_f64 v[2:3], v[2:3], v[8:9], v[14:15] +; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], v[16:17] +; GFX9-NEXT: global_store_dwordx4 v[18:19], v[0:3], off +; GFX9-NEXT: global_store_dwordx2 v[18:19], v[4:5], off offset:16 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v3f64_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[6:7], v[12:13] +; GFX11-NEXT: v_fma_f64 v[2:3], v[2:3], v[8:9], v[14:15] +; GFX11-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], v[16:17] +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[18:19], v[0:3], off +; GFX11-NEXT: global_store_b64 v[18:19], v[4:5], off offset:16 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v3f64_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f64 v[0:1], v[0:1], v[6:7], v[12:13] +; GFX12-NEXT: v_fma_f64 v[2:3], v[2:3], v[8:9], v[14:15] +; GFX12-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], v[16:17] +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: global_store_b128 v[18:19], v[0:3], off +; GFX12-NEXT: global_store_b64 v[18:19], v[4:5], off offset:16 +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call <3 x double> @llvm.experimental.constrained.fma.v3f64(<3 x double> %x, <3 x double> %y, <3 x double> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <3 x double> %val -} - -define <4 x double> @v_constained_fma_v4f64_fpexcept_strict(<4 x double> %x, <4 x double> %y, <4 x double> %z) #0 { -; GCN-LABEL: v_constained_fma_v4f64_fpexcept_strict: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] -; GCN-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] -; GCN-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] -; GCN-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] -; GCN-NEXT: s_setpc_b64 s[30:31] + store <3 x double> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v4f64_fpexcept_strict_uni(<4 x double> inreg %x, <4 x double> inreg %y, <4 x double> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v4f64_fpexcept_strict_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v12, s24 +; GFX8-NEXT: v_mov_b32_e32 v13, s25 +; GFX8-NEXT: v_fma_f64 v[2:3], s[16:17], v[12:13], v[2:3] +; GFX8-NEXT: v_mov_b32_e32 v12, s26 +; GFX8-NEXT: v_mov_b32_e32 v13, s27 +; GFX8-NEXT: v_fma_f64 v[4:5], s[18:19], v[12:13], v[4:5] +; GFX8-NEXT: v_mov_b32_e32 v12, s28 +; GFX8-NEXT: v_mov_b32_e32 v13, s29 +; GFX8-NEXT: v_fma_f64 v[6:7], s[20:21], v[12:13], v[6:7] +; GFX8-NEXT: v_fma_f64 v[8:9], s[22:23], v[0:1], v[8:9] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v10 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v11, vcc +; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[2:5] +; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[6:9] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v4f64_fpexcept_strict_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v12, s24 +; GFX900-NEXT: v_mov_b32_e32 v13, s25 +; GFX900-NEXT: v_fma_f64 v[2:3], s[16:17], v[12:13], v[2:3] +; GFX900-NEXT: v_mov_b32_e32 v12, s26 +; GFX900-NEXT: v_mov_b32_e32 v13, s27 +; GFX900-NEXT: v_fma_f64 v[4:5], s[18:19], v[12:13], v[4:5] +; GFX900-NEXT: v_mov_b32_e32 v12, s28 +; GFX900-NEXT: v_mov_b32_e32 v13, s29 +; GFX900-NEXT: v_fma_f64 v[6:7], s[20:21], v[12:13], v[6:7] +; GFX900-NEXT: v_fma_f64 v[8:9], s[22:23], v[0:1], v[8:9] +; GFX900-NEXT: global_store_dwordx4 v[10:11], v[2:5], off +; GFX900-NEXT: global_store_dwordx4 v[10:11], v[6:9], off offset:16 +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v4f64_fpexcept_strict_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[8:9], s[20:21] +; GFX942-NEXT: v_mov_b64_e32 v[10:11], s[28:29] +; GFX942-NEXT: v_fma_f64 v[8:9], s[0:1], v[8:9], v[10:11] +; GFX942-NEXT: v_mov_b64_e32 v[10:11], s[22:23] +; GFX942-NEXT: v_fma_f64 v[10:11], s[2:3], v[10:11], v[0:1] +; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[24:25] +; GFX942-NEXT: v_fma_f64 v[0:1], s[16:17], v[0:1], v[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[26:27] +; GFX942-NEXT: v_fma_f64 v[2:3], s[18:19], v[2:3], v[4:5] +; GFX942-NEXT: global_store_dwordx4 v[6:7], v[8:11], off +; GFX942-NEXT: global_store_dwordx4 v[6:7], v[0:3], off offset:16 +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v4f64_fpexcept_strict_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v8, s28 :: v_dual_mov_b32 v9, s29 +; GFX11-NEXT: v_fma_f64 v[10:11], s[2:3], s[22:23], v[0:1] +; GFX11-NEXT: v_fma_f64 v[0:1], s[16:17], s[24:25], v[2:3] +; GFX11-NEXT: v_fma_f64 v[2:3], s[18:19], s[26:27], v[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_fma_f64 v[8:9], s[0:1], s[20:21], v[8:9] +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[6:7], v[8:11], off +; GFX11-NEXT: global_store_b128 v[6:7], v[0:3], off offset:16 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v4f64_fpexcept_strict_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v8, s28 :: v_dual_mov_b32 v9, s29 +; GFX12-NEXT: v_fma_f64 v[10:11], s[2:3], s[22:23], v[0:1] +; GFX12-NEXT: v_fma_f64 v[0:1], s[16:17], s[24:25], v[2:3] +; GFX12-NEXT: v_fma_f64 v[2:3], s[18:19], s[26:27], v[4:5] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX12-NEXT: v_fma_f64 v[8:9], s[0:1], s[20:21], v[8:9] +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: global_store_b128 v[6:7], v[8:11], off +; GFX12-NEXT: global_store_b128 v[6:7], v[0:3], off offset:16 +; GFX12-NEXT: s_setpc_b64 s[30:31] %val = call <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double> %x, <4 x double> %y, <4 x double> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <4 x double> %val + store <4 x double> %val, ptr addrspace(1) %out + ret void } -define double @v_constained_fma_f64_fpexcept_strict_fneg(double %x, double %y, double %z) #0 { -; GCN-LABEL: v_constained_fma_f64_fpexcept_strict_fneg: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[4:5] -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_v4f64_fpexcept_strict_div(<4 x double> %x, <4 x double> %y, <4 x double> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v4f64_fpexcept_strict_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] +; GFX8-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] +; GFX8-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] +; GFX8-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] +; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[0:3] +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 16, v24 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v25, vcc +; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_v4f64_fpexcept_strict_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] +; GFX9-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] +; GFX9-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] +; GFX9-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] +; GFX9-NEXT: global_store_dwordx4 v[24:25], v[0:3], off +; GFX9-NEXT: global_store_dwordx4 v[24:25], v[4:7], off offset:16 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v4f64_fpexcept_strict_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] +; GFX11-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] +; GFX11-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] +; GFX11-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: global_store_b128 v[24:25], v[0:3], off +; GFX11-NEXT: global_store_b128 v[24:25], v[4:7], off offset:16 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v4f64_fpexcept_strict_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f64 v[0:1], v[0:1], v[8:9], v[16:17] +; GFX12-NEXT: v_fma_f64 v[2:3], v[2:3], v[10:11], v[18:19] +; GFX12-NEXT: v_fma_f64 v[4:5], v[4:5], v[12:13], v[20:21] +; GFX12-NEXT: v_fma_f64 v[6:7], v[6:7], v[14:15], v[22:23] +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: global_store_b128 v[24:25], v[0:3], off +; GFX12-NEXT: global_store_b128 v[24:25], v[4:7], off offset:16 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %val = call <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double> %x, <4 x double> %y, <4 x double> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <4 x double> %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f64_fpexcept_strict_fneg_uni(double inreg %x, double inreg %y, double inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s16 +; GFX8-NEXT: v_mov_b32_e32 v4, s18 +; GFX8-NEXT: v_mov_b32_e32 v3, s17 +; GFX8-NEXT: v_mov_b32_e32 v5, s19 +; GFX8-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -s[20:21] +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s16 +; GFX900-NEXT: v_mov_b32_e32 v4, s18 +; GFX900-NEXT: v_mov_b32_e32 v3, s17 +; GFX900-NEXT: v_mov_b32_e32 v5, s19 +; GFX900-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -s[20:21] +; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX942-NEXT: v_fma_f64 v[2:3], v[2:3], v[4:5], -s[16:17] +; GFX942-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f64 v[2:3], s[0:1], v[2:3], -s[16:17] +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_fma_f64 v[2:3], s[0:1], v[2:3], -s[16:17] +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.z = fneg double %z %val = call double @llvm.experimental.constrained.fma.f64(double %x, double %y, double %neg.z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret double %val + store double %val, ptr addrspace(1) %out + ret void } -define double @v_constained_fma_f64_fpexcept_strict_fneg_fneg(double %x, double %y, double %z) #0 { -; GCN-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[2:3], v[4:5] -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f64_fpexcept_strict_fneg_div(double %x, double %y, double %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[4:5] +; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[4:5] +; GFX9-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[4:5] +; GFX11-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], -v[4:5] +; GFX12-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.z = fneg double %z + %val = call double @llvm.experimental.constrained.fma.f64(double %x, double %y, double %neg.z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store double %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f64_fpexcept_strict_fneg_fneg_uni(double inreg %x, double inreg %y, double inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v4, s20 +; GFX8-NEXT: v_mov_b32_e32 v3, s19 +; GFX8-NEXT: v_mov_b32_e32 v5, s21 +; GFX8-NEXT: v_fma_f64 v[2:3], -s[16:17], -v[2:3], v[4:5] +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s18 +; GFX900-NEXT: v_mov_b32_e32 v4, s20 +; GFX900-NEXT: v_mov_b32_e32 v3, s19 +; GFX900-NEXT: v_mov_b32_e32 v5, s21 +; GFX900-NEXT: v_fma_f64 v[2:3], -s[16:17], -v[2:3], v[4:5] +; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[16:17] +; GFX942-NEXT: v_fma_f64 v[2:3], -s[0:1], -v[2:3], v[4:5] +; GFX942-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f64 v[2:3], -s[0:1], -s[2:3], v[2:3] +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_fma_f64 v[2:3], -s[0:1], -s[2:3], v[2:3] +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = fneg double %x %neg.y = fneg double %y %val = call double @llvm.experimental.constrained.fma.f64(double %neg.x, double %neg.y, double %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret double %val + store double %val, ptr addrspace(1) %out + ret void } -define double @v_constained_fma_f64_fpexcept_strict_fabs_fabs(double %x, double %y, double %z) #0 { -; GCN-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f64 v[0:1], |v[0:1]|, |v[2:3]|, v[4:5] -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_f64_fpexcept_strict_fneg_fneg_div(double %x, double %y, double %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[2:3], v[4:5] +; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[2:3], v[4:5] +; GFX9-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[2:3], v[4:5] +; GFX11-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f64_fpexcept_strict_fneg_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[2:3], v[4:5] +; GFX12-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = fneg double %x + %neg.y = fneg double %y + %val = call double @llvm.experimental.constrained.fma.f64(double %neg.x, double %neg.y, double %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store double %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f64_fpexcept_strict_fabs_fabs_uni(double inreg %x, double inreg %y, double inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v4, s20 +; GFX8-NEXT: v_mov_b32_e32 v3, s19 +; GFX8-NEXT: v_mov_b32_e32 v5, s21 +; GFX8-NEXT: v_fma_f64 v[2:3], |s[16:17]|, |v[2:3]|, v[4:5] +; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s18 +; GFX900-NEXT: v_mov_b32_e32 v4, s20 +; GFX900-NEXT: v_mov_b32_e32 v3, s19 +; GFX900-NEXT: v_mov_b32_e32 v5, s21 +; GFX900-NEXT: v_fma_f64 v[2:3], |s[16:17]|, |v[2:3]|, v[4:5] +; GFX900-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[16:17] +; GFX942-NEXT: v_fma_f64 v[2:3], |s[0:1]|, |v[2:3]|, v[4:5] +; GFX942-NEXT: global_store_dwordx2 v[0:1], v[2:3], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_fma_f64 v[2:3], |s[0:1]|, |s[2:3]|, v[2:3] +; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v2, s16 :: v_dual_mov_b32 v3, s17 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_fma_f64 v[2:3], |s[0:1]|, |s[2:3]|, v[2:3] +; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = call double @llvm.fabs.f64(double %x) #0 %neg.y = call double @llvm.fabs.f64(double %y) #0 %val = call double @llvm.experimental.constrained.fma.f64(double %neg.x, double %neg.y, double %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret double %val + store double %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_f64_fpexcept_strict_fabs_fabs_div(double %x, double %y, double %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f64 v[0:1], |v[0:1]|, |v[2:3]|, v[4:5] +; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_fma_f64 v[0:1], |v[0:1]|, |v[2:3]|, v[4:5] +; GFX9-NEXT: global_store_dwordx2 v[6:7], v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f64 v[0:1], |v[0:1]|, |v[2:3]|, v[4:5] +; GFX11-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_f64_fpexcept_strict_fabs_fabs_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f64 v[0:1], |v[0:1]|, |v[2:3]|, v[4:5] +; GFX12-NEXT: global_store_b64 v[6:7], v[0:1], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = call double @llvm.fabs.f64(double %x) #0 + %neg.y = call double @llvm.fabs.f64(double %y) #0 + %val = call double @llvm.experimental.constrained.fma.f64(double %neg.x, double %neg.y, double %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store double %val, ptr addrspace(1) %out + ret void +} + +define void @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni(<2 x double> inreg %x, <2 x double> inreg %y, <2 x double> inreg %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s20 +; GFX8-NEXT: v_mov_b32_e32 v6, s24 +; GFX8-NEXT: v_mov_b32_e32 v3, s21 +; GFX8-NEXT: v_mov_b32_e32 v7, s25 +; GFX8-NEXT: v_mov_b32_e32 v4, s22 +; GFX8-NEXT: v_fma_f64 v[2:3], -s[16:17], -v[2:3], v[6:7] +; GFX8-NEXT: v_mov_b32_e32 v6, s26 +; GFX8-NEXT: v_mov_b32_e32 v5, s23 +; GFX8-NEXT: v_mov_b32_e32 v7, s27 +; GFX8-NEXT: v_fma_f64 v[4:5], -s[18:19], -v[4:5], v[6:7] +; GFX8-NEXT: v_readfirstlane_b32 s4, v2 +; GFX8-NEXT: v_readfirstlane_b32 s5, v3 +; GFX8-NEXT: v_readfirstlane_b32 s6, v4 +; GFX8-NEXT: v_readfirstlane_b32 s7, v5 +; GFX8-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 +; GFX8-NEXT: v_mov_b32_e32 v4, s6 +; GFX8-NEXT: v_mov_b32_e32 v5, s7 +; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mov_b32_e32 v2, s20 +; GFX900-NEXT: v_mov_b32_e32 v6, s24 +; GFX900-NEXT: v_mov_b32_e32 v3, s21 +; GFX900-NEXT: v_mov_b32_e32 v7, s25 +; GFX900-NEXT: v_mov_b32_e32 v4, s22 +; GFX900-NEXT: v_fma_f64 v[2:3], -s[16:17], -v[2:3], v[6:7] +; GFX900-NEXT: v_mov_b32_e32 v6, s26 +; GFX900-NEXT: v_mov_b32_e32 v5, s23 +; GFX900-NEXT: v_mov_b32_e32 v7, s27 +; GFX900-NEXT: v_fma_f64 v[4:5], -s[18:19], -v[4:5], v[6:7] +; GFX900-NEXT: v_readfirstlane_b32 s4, v2 +; GFX900-NEXT: v_readfirstlane_b32 s5, v3 +; GFX900-NEXT: v_readfirstlane_b32 s6, v4 +; GFX900-NEXT: v_readfirstlane_b32 s7, v5 +; GFX900-NEXT: v_mov_b32_e32 v2, s4 +; GFX900-NEXT: v_mov_b32_e32 v3, s5 +; GFX900-NEXT: v_mov_b32_e32 v4, s6 +; GFX900-NEXT: v_mov_b32_e32 v5, s7 +; GFX900-NEXT: global_store_dwordx4 v[0:1], v[2:5], off +; GFX900-NEXT: s_waitcnt vmcnt(0) +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni: +; GFX942: ; %bb.0: +; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[16:17] +; GFX942-NEXT: v_mov_b64_e32 v[6:7], s[20:21] +; GFX942-NEXT: v_fma_f64 v[2:3], -s[0:1], -v[2:3], v[6:7] +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[18:19] +; GFX942-NEXT: v_readfirstlane_b32 s0, v2 +; GFX942-NEXT: v_readfirstlane_b32 s1, v3 +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[22:23] +; GFX942-NEXT: v_fma_f64 v[2:3], -s[2:3], -v[4:5], v[2:3] +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_readfirstlane_b32 s2, v2 +; GFX942-NEXT: v_readfirstlane_b32 s3, v3 +; GFX942-NEXT: s_nop 1 +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off +; GFX942-NEXT: s_waitcnt vmcnt(0) +; GFX942-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23 +; GFX11-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_fma_f64 v[4:5], -s[2:3], -s[18:19], v[4:5] +; GFX11-NEXT: v_fma_f64 v[2:3], -s[0:1], -s[16:17], v[2:3] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_readfirstlane_b32 s3, v5 +; GFX11-NEXT: v_readfirstlane_b32 s2, v4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-NEXT: v_readfirstlane_b32 s0, v2 +; GFX11-NEXT: v_readfirstlane_b32 s1, v3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 +; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_uni: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_dual_mov_b32 v4, s22 :: v_dual_mov_b32 v5, s23 +; GFX12-NEXT: v_dual_mov_b32 v2, s20 :: v_dual_mov_b32 v3, s21 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_fma_f64 v[4:5], -s[2:3], -s[18:19], v[4:5] +; GFX12-NEXT: v_fma_f64 v[2:3], -s[0:1], -s[16:17], v[2:3] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-NEXT: v_readfirstlane_b32 s3, v5 +; GFX12-NEXT: v_readfirstlane_b32 s2, v4 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-NEXT: s_wait_alu depctr_va_sdst(0) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2 +; GFX12-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX12-NEXT: s_setpc_b64 s[30:31] + %neg.x = fneg <2 x double> %x + %neg.y = fneg <2 x double> %y + %val = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %neg.x, <2 x double> %neg.y, <2 x double> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") + store <2 x double> %val, ptr addrspace(1) %out + ret void } -define <2 x double> @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg(<2 x double> %x, <2 x double> %y, <2 x double> %z) #0 { -; GCN-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[4:5], v[8:9] -; GCN-NEXT: v_fma_f64 v[2:3], -v[2:3], -v[6:7], v[10:11] -; GCN-NEXT: s_setpc_b64 s[30:31] +define void @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_div(<2 x double> %x, <2 x double> %y, <2 x double> %z, ptr addrspace(1) %out) #0 { +; GFX8-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_div: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[4:5], v[8:9] +; GFX8-NEXT: v_fma_f64 v[2:3], -v[2:3], -v[6:7], v[10:11] +; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[0:3] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_div: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[4:5], v[8:9] +; GFX9-NEXT: v_fma_f64 v[2:3], -v[2:3], -v[6:7], v[10:11] +; GFX9-NEXT: global_store_dwordx4 v[12:13], v[0:3], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_div: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[4:5], v[8:9] +; GFX11-NEXT: v_fma_f64 v[2:3], -v[2:3], -v[6:7], v[10:11] +; GFX11-NEXT: global_store_b128 v[12:13], v[0:3], off +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_constained_fma_v2f64_fpexcept_strict_fneg_fneg_div: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_fma_f64 v[0:1], -v[0:1], -v[4:5], v[8:9] +; GFX12-NEXT: v_fma_f64 v[2:3], -v[2:3], -v[6:7], v[10:11] +; GFX12-NEXT: global_store_b128 v[12:13], v[0:3], off +; GFX12-NEXT: s_setpc_b64 s[30:31] %neg.x = fneg <2 x double> %x %neg.y = fneg <2 x double> %y %val = call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %neg.x, <2 x double> %neg.y, <2 x double> %z, metadata !"round.tonearest", metadata !"fpexcept.strict") - ret <2 x double> %val + store <2 x double> %val, ptr addrspace(1) %out + ret void } declare double @llvm.fabs.f64(double) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll index a30e3115cc463..567656635b726 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll @@ -491,7 +491,8 @@ define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) { ; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 0x80008 ; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 8 ; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s1, s0 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s0, 8 +; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8 ; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; @@ -962,19 +963,23 @@ define amdgpu_ps i32 @s_uaddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) { ; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 0x80008 ; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s0 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, 0xffff +; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, 0xffff ; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 0x80008 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 0x80008 ; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8 +; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s1 +; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s1, 16 ; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xff -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s2, s1 -; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s0, 8 +; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 8 ; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff ; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2 -; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s1, 16 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 24 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, 0xff +; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s2, 24 ; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll new file mode 100644 index 0000000000000..fb013d35d540b --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.ll @@ -0,0 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX11 %s + +define amdgpu_ps void @unmerge_sgprS16_from_V2S16(ptr addrspace(1) inreg %ptr, ptr addrspace(1) inreg %out) { +; GFX11-LABEL: unmerge_sgprS16_from_V2S16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_pack_hl_b32_b16 s0, s0, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: global_store_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_endpgm + %load = load <2 x i16>, ptr addrspace(1) %ptr + %shuffle = shufflevector <2 x i16> %load, <2 x i16> poison, <2 x i32> + store <2 x i16> %shuffle, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @unmerge_sgprS16_from_V4S16(ptr addrspace(1) inreg %ptr, ptr addrspace(1) inreg %out) { +; GFX11-LABEL: unmerge_sgprS16_from_V4S16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_pack_lh_b32_b16 s0, s0, s1 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: global_store_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_endpgm + %load = load <4 x i16>, ptr addrspace(1) %ptr + %shuffle = shufflevector <4 x i16> %load, <4 x i16> poison, <2 x i32> + store <2 x i16> %shuffle, ptr addrspace(1) %out + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir new file mode 100644 index 0000000000000..94a59eb1a92b2 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir @@ -0,0 +1,65 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbanklegalize -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: unmerge_sgprS16_from_V2S16 +legalized: true +body: | + bb.0: + liveins: $sgpr0, $sgpr2_sgpr3 + + ; CHECK-LABEL: name: unmerge_sgprS16_from_V2S16 + ; CHECK: liveins: $sgpr0, $sgpr2_sgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3 + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>) + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32) + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST]](s32) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC]](s16) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>) + ; CHECK-NEXT: G_STORE [[COPY2]](<2 x s16>), [[COPY1]](p1) :: (store (<2 x s16>), addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + %0:sgpr(<2 x s16>) = COPY $sgpr0 + %1:sgpr(p1) = COPY $sgpr2_sgpr3 + %2:sgpr(s16), %3:sgpr(s16) = G_UNMERGE_VALUES %0(<2 x s16>) + %4:sgpr(<2 x s16>) = G_BUILD_VECTOR %3(s16), %2(s16) + G_STORE %4(<2 x s16>), %1(p1) :: (store (<2 x s16>), addrspace 1) + S_ENDPGM 0 +... + +--- +name: unmerge_sgprS16_from_V4S16 +legalized: true +body: | + bb.0: + liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3 + + ; CHECK-LABEL: name: unmerge_sgprS16_from_V4S16 + ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3 + ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(<2 x s16>), [[UV1:%[0-9]+]]:sgpr(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV]](<2 x s16>) + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32) + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST]](s32) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR]](s32) + ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV1]](<2 x s16>) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C]](s32) + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST1]](s32) + ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR1]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC3]](s16) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>) + ; CHECK-NEXT: G_STORE [[COPY2]](<2 x s16>), [[COPY1]](p1) :: (store (<2 x s16>), addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1 + %1:sgpr(p1) = COPY $sgpr2_sgpr3 + %2:sgpr(s16), %3:sgpr(s16), %4:sgpr(s16), %5:sgpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>) + %6:sgpr(<2 x s16>) = G_BUILD_VECTOR %2(s16), %5(s16) + G_STORE %6(<2 x s16>), %1(p1) :: (store (<2 x s16>), addrspace 1) + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll index 1c8a26ce6126d..e17706ba6dd67 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll @@ -483,7 +483,8 @@ define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) { ; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 0x80008 ; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 8 ; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s1, s0 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s0, 8 +; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8 ; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; @@ -946,19 +947,23 @@ define amdgpu_ps i32 @s_usubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) { ; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16 ; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 0x80008 ; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s0 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, 0xffff +; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, 0xffff ; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 0x80008 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 0x80008 ; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8 +; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s1 +; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s1, 16 ; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xff -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s2, s1 -; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s0, 8 +; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 8 ; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff ; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2 -; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s1, 16 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 24 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s2 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, 0xff +; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s2, 24 ; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll index e882769f97ac1..4f40948cab0a2 100644 --- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll @@ -16,6 +16,7 @@ define void @flat_atomic_cmpxchg_i32_ret_av_av__av(ptr %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -44,6 +45,7 @@ define void @flat_atomic_cmpxchg_i32_ret_av_av__v(ptr %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -72,6 +74,7 @@ define void @flat_atomic_cmpxchg_i32_ret_av_av__a(ptr %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -103,6 +106,7 @@ define void @flat_atomic_cmpxchg_i32_ret_a_a__a(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -134,6 +138,7 @@ define void @flat_atomic_cmpxchg_i32_ret_a_a__v(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -165,6 +170,7 @@ define void @flat_atomic_cmpxchg_i32_ret_v_a__v(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -194,6 +200,7 @@ define void @flat_atomic_cmpxchg_i32_ret_a_v__v(ptr %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -222,6 +229,7 @@ define void @flat_atomic_cmpxchg_i32_ret_v_v__a(ptr %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -251,6 +259,7 @@ define void @flat_atomic_cmpxchg_i32_ret_av_v__av(ptr %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -279,6 +288,7 @@ define void @flat_atomic_cmpxchg_i32_ret_v_av__av(ptr %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -309,6 +319,7 @@ define void @flat_atomic_cmpxchg_i32_ret_av_a__av(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -339,6 +350,7 @@ define void @flat_atomic_cmpxchg_i32_ret_a_av__av(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -380,6 +392,7 @@ define void @flat_atomic_cmpxchg_i64_ret_av_av__av(ptr %ptr) #0 { ; CHECK-NEXT: s_cbranch_execz .LBB12_2 ; CHECK-NEXT: ; %bb.1: ; %atomicrmw.global ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[6:7], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -436,6 +449,7 @@ define void @flat_atomic_cmpxchg_i64_ret_av_av__v(ptr %ptr) #0 { ; CHECK-NEXT: s_cbranch_execz .LBB13_2 ; CHECK-NEXT: ; %bb.1: ; %atomicrmw.global ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[6:7], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -492,6 +506,7 @@ define void @flat_atomic_cmpxchg_i64_ret_av_av__a(ptr %ptr) #0 { ; CHECK-NEXT: s_cbranch_execz .LBB14_2 ; CHECK-NEXT: ; %bb.1: ; %atomicrmw.global ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -561,6 +576,7 @@ define void @flat_atomic_cmpxchg_i64_ret_a_a__a(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v4, a2 ; CHECK-NEXT: v_accvgpr_read_b32 v5, a3 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -631,6 +647,7 @@ define void @flat_atomic_cmpxchg_i64_ret_a_a__v(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v4, a0 ; CHECK-NEXT: v_accvgpr_read_b32 v5, a1 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -692,6 +709,7 @@ define void @flat_atomic_cmpxchg_i64_ret_v_a__v(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v0, a0 ; CHECK-NEXT: v_accvgpr_read_b32 v1, a1 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -753,6 +771,7 @@ define void @flat_atomic_cmpxchg_i64_ret_a_v__v(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[4:5], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -810,6 +829,7 @@ define void @flat_atomic_cmpxchg_i64_ret_v_v__a(ptr %ptr) #0 { ; CHECK-NEXT: s_cbranch_execz .LBB19_2 ; CHECK-NEXT: ; %bb.1: ; %atomicrmw.global ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -871,6 +891,7 @@ define void @flat_atomic_cmpxchg_i64_ret_av_v__av(ptr %ptr) #0 { ; CHECK-NEXT: s_cbranch_execz .LBB20_2 ; CHECK-NEXT: ; %bb.1: ; %atomicrmw.global ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[6:7], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -927,6 +948,7 @@ define void @flat_atomic_cmpxchg_i64_ret_v_av__av(ptr %ptr) #0 { ; CHECK-NEXT: s_cbranch_execz .LBB21_2 ; CHECK-NEXT: ; %bb.1: ; %atomicrmw.global ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[6:7], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -987,6 +1009,7 @@ define void @flat_atomic_cmpxchg_i64_ret_av_a__av(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v0, a0 ; CHECK-NEXT: v_accvgpr_read_b32 v1, a1 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -1048,6 +1071,7 @@ define void @flat_atomic_cmpxchg_i64_ret_a_av__av(ptr %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[4:5], v[0:3] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: buffer_invl2 diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll index b5f952b0bb00d..0a300674df505 100644 --- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll +++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll @@ -16,6 +16,7 @@ define void @flat_atomic_xchg_i32_ret_a_a(ptr %ptr) #0 { ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -35,6 +36,7 @@ define void @flat_atomic_xchg_i32_ret_a_a(ptr %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -60,6 +62,7 @@ define void @flat_atomic_xchg_i32_ret_a_v(ptr %ptr) #0 { ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -78,6 +81,7 @@ define void @flat_atomic_xchg_i32_ret_a_v(ptr %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -101,6 +105,7 @@ define void @flat_atomic_xchg_i32_ret_v_a(ptr %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -118,6 +123,7 @@ define void @flat_atomic_xchg_i32_ret_v_a(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -142,6 +148,7 @@ define void @flat_atomic_xchg_i32_ret_av_av(ptr %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -158,6 +165,7 @@ define void @flat_atomic_xchg_i32_ret_av_av(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -181,6 +189,7 @@ define void @flat_atomic_xchg_i32_ret_av_v(ptr %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -197,6 +206,7 @@ define void @flat_atomic_xchg_i32_ret_av_v(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -220,6 +230,7 @@ define void @flat_atomic_xchg_i32_ret_av_a(ptr %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -237,6 +248,7 @@ define void @flat_atomic_xchg_i32_ret_av_a(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -262,6 +274,7 @@ define void @flat_atomic_xchg_i32_ret_a_av(ptr %ptr) #0 { ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -280,6 +293,7 @@ define void @flat_atomic_xchg_i32_ret_a_av(ptr %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -303,6 +317,7 @@ define void @flat_atomic_xchg_i32_ret_v_av(ptr %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -319,6 +334,7 @@ define void @flat_atomic_xchg_i32_ret_v_av(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -577,6 +593,7 @@ define void @flat_atomic_xchg_i32_noret_a(ptr %ptr) #0 { ; GFX90A-NEXT: ; def a0 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v[0:1], a0 offset:40 ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -590,6 +607,7 @@ define void @flat_atomic_xchg_i32_noret_a(ptr %ptr) #0 { ; GFX950-NEXT: ; def a0 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v[0:1], a0 offset:40 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -608,6 +626,7 @@ define void @flat_atomic_xchg_i32_noret_av(ptr %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v[0:1], v2 offset:40 ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -621,6 +640,7 @@ define void @flat_atomic_xchg_i32_noret_av(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap v[0:1], v2 offset:40 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -655,6 +675,7 @@ define void @flat_atomic_xchg_i64_ret_a_a(ptr %ptr) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB11_2 ; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -701,6 +722,7 @@ define void @flat_atomic_xchg_i64_ret_a_a(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB11_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -753,6 +775,7 @@ define void @flat_atomic_xchg_i64_ret_a_v(ptr %ptr) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB12_2 ; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -797,6 +820,7 @@ define void @flat_atomic_xchg_i64_ret_a_v(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB12_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -845,6 +869,7 @@ define void @flat_atomic_xchg_i64_ret_v_a(ptr %ptr) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB13_2 ; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -889,6 +914,7 @@ define void @flat_atomic_xchg_i64_ret_v_a(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB13_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -939,6 +965,7 @@ define void @flat_atomic_xchg_i64_ret_av_av(ptr %ptr) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB14_2 ; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -981,6 +1008,7 @@ define void @flat_atomic_xchg_i64_ret_av_av(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB14_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1029,6 +1057,7 @@ define void @flat_atomic_xchg_i64_ret_av_v(ptr %ptr) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB15_2 ; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1071,6 +1100,7 @@ define void @flat_atomic_xchg_i64_ret_av_v(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB15_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1119,6 +1149,7 @@ define void @flat_atomic_xchg_i64_ret_av_a(ptr %ptr) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB16_2 ; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1163,6 +1194,7 @@ define void @flat_atomic_xchg_i64_ret_av_a(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB16_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1215,6 +1247,7 @@ define void @flat_atomic_xchg_i64_ret_a_av(ptr %ptr) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB17_2 ; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1259,6 +1292,7 @@ define void @flat_atomic_xchg_i64_ret_a_av(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB17_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1307,6 +1341,7 @@ define void @flat_atomic_xchg_i64_ret_v_av(ptr %ptr) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB18_2 ; GFX90A-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1349,6 +1384,7 @@ define void @flat_atomic_xchg_i64_ret_v_av(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB18_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1399,6 +1435,7 @@ define void @flat_atomic_xchg_i64_noret_a(ptr %ptr) #0 { ; GFX90A-NEXT: s_setpc_b64 s[30:31] ; GFX90A-NEXT: .LBB19_3: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], a[0:1] ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1435,6 +1472,7 @@ define void @flat_atomic_xchg_i64_noret_a(ptr %ptr) #0 { ; GFX950-NEXT: s_setpc_b64 s[30:31] ; GFX950-NEXT: .LBB19_3: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], a[0:1] sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1476,6 +1514,7 @@ define void @flat_atomic_xchg_i64_noret_av(ptr %ptr) #0 { ; GFX90A-NEXT: s_setpc_b64 s[30:31] ; GFX90A-NEXT: .LBB20_3: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3] ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1511,6 +1550,7 @@ define void @flat_atomic_xchg_i64_noret_av(ptr %ptr) #0 { ; GFX950-NEXT: s_setpc_b64 s[30:31] ; GFX950-NEXT: .LBB20_3: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3] sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1551,6 +1591,7 @@ define void @flat_atomic_xor_expansion_i32_ret_a_a(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1582,6 +1623,7 @@ define void @flat_atomic_xor_expansion_i32_ret_a_a(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1620,6 +1662,7 @@ define void @flat_atomic_xor_expansion_i32_ret_a_v(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1650,6 +1693,7 @@ define void @flat_atomic_xor_expansion_i32_ret_a_v(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1686,6 +1730,7 @@ define void @flat_atomic_xor_expansion_i32_ret_v_a(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1716,6 +1761,7 @@ define void @flat_atomic_xor_expansion_i32_ret_v_a(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1753,6 +1799,7 @@ define void @flat_atomic_xor_expansion_i32_ret_av_av(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1782,6 +1829,7 @@ define void @flat_atomic_xor_expansion_i32_ret_av_av(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1818,6 +1866,7 @@ define void @flat_atomic_xor_expansion_i32_ret_av_v(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1847,6 +1896,7 @@ define void @flat_atomic_xor_expansion_i32_ret_av_v(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1883,6 +1933,7 @@ define void @flat_atomic_xor_expansion_i32_ret_av_a(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1913,6 +1964,7 @@ define void @flat_atomic_xor_expansion_i32_ret_av_a(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1951,6 +2003,7 @@ define void @flat_atomic_xor_expansion_i32_ret_a_av(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1981,6 +2034,7 @@ define void @flat_atomic_xor_expansion_i32_ret_a_av(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2017,6 +2071,7 @@ define void @flat_atomic_xor_expansion_i32_ret_v_av(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2046,6 +2101,7 @@ define void @flat_atomic_xor_expansion_i32_ret_v_av(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2140,6 +2196,7 @@ define void @flat_atomic_xor_expansion_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v0, v1, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2284,6 +2341,7 @@ define void @flat_atomic_xor_expansion_i32_ret_av_av_no_agprs(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v0, v1, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v0, v[2:3], v[0:1] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2380,6 +2438,7 @@ define void @flat_atomic_xor_expansion_i32_noret_a(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2407,6 +2466,7 @@ define void @flat_atomic_xor_expansion_i32_noret_a(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2438,6 +2498,7 @@ define void @flat_atomic_xor_expansion_i32_noret_av(ptr %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2464,6 +2525,7 @@ define void @flat_atomic_xor_expansion_i32_noret_av(ptr %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2510,6 +2572,7 @@ define void @flat_atomic_xor_expansion_i64_ret_a_a(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2572,6 +2635,7 @@ define void @flat_atomic_xor_expansion_i64_ret_a_a(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2639,6 +2703,7 @@ define void @flat_atomic_xor_expansion_i64_ret_a_v(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2697,6 +2762,7 @@ define void @flat_atomic_xor_expansion_i64_ret_a_v(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2758,6 +2824,7 @@ define void @flat_atomic_xor_expansion_i64_ret_v_a(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2818,6 +2885,7 @@ define void @flat_atomic_xor_expansion_i64_ret_v_a(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2883,6 +2951,7 @@ define void @flat_atomic_xor_expansion_i64_ret_av_av(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2939,6 +3008,7 @@ define void @flat_atomic_xor_expansion_i64_ret_av_av(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -3000,6 +3070,7 @@ define void @flat_atomic_xor_expansion_i64_ret_av_v(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3056,6 +3127,7 @@ define void @flat_atomic_xor_expansion_i64_ret_av_v(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -3117,6 +3189,7 @@ define void @flat_atomic_xor_expansion_i64_ret_av_a(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3177,6 +3250,7 @@ define void @flat_atomic_xor_expansion_i64_ret_av_a(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -3244,6 +3318,7 @@ define void @flat_atomic_xor_expansion_i64_ret_a_av(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3302,6 +3377,7 @@ define void @flat_atomic_xor_expansion_i64_ret_a_av(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -3363,6 +3439,7 @@ define void @flat_atomic_xor_expansion_i64_ret_v_av(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3419,6 +3496,7 @@ define void @flat_atomic_xor_expansion_i64_ret_v_av(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -3486,6 +3564,7 @@ define void @flat_atomic_xor_expansion_i64_noret_a(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3544,6 +3623,7 @@ define void @flat_atomic_xor_expansion_i64_noret_a(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -3603,6 +3683,7 @@ define void @flat_atomic_xor_expansion_i64_noret_av(ptr %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3659,6 +3740,7 @@ define void @flat_atomic_xor_expansion_i64_noret_av(ptr %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5] sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -3722,6 +3804,7 @@ define void @flat_atomic_xor_i32_ret_a_a(ptr %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3763,6 +3846,7 @@ define void @flat_atomic_xor_i32_ret_a_v(ptr %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3801,6 +3885,7 @@ define void @flat_atomic_xor_i32_ret_v_a(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3839,6 +3924,7 @@ define void @flat_atomic_xor_i32_ret_av_av(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3876,6 +3962,7 @@ define void @flat_atomic_xor_i32_ret_av_v(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3914,6 +4001,7 @@ define void @flat_atomic_xor_i32_ret_av_a(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3955,6 +4043,7 @@ define void @flat_atomic_xor_i32_ret_a_av(ptr %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3992,6 +4081,7 @@ define void @flat_atomic_xor_i32_ret_v_av(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4259,6 +4349,7 @@ define void @flat_atomic_xor_i32_noret_a(ptr %ptr) #0 { ; GFX950-NEXT: ; def a0 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v[0:1], a0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4288,6 +4379,7 @@ define void @flat_atomic_xor_i32_noret_av(ptr %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor v[0:1], v2 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4366,6 +4458,7 @@ define void @flat_atomic_xor_i64_ret_a_a(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB53_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4461,6 +4554,7 @@ define void @flat_atomic_xor_i64_ret_a_v(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB54_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[2:3], v[0:1], v[4:5] sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4552,6 +4646,7 @@ define void @flat_atomic_xor_i64_ret_v_a(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB55_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4643,6 +4738,7 @@ define void @flat_atomic_xor_i64_ret_av_av(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB56_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[2:3], v[0:1], v[4:5] sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4730,6 +4826,7 @@ define void @flat_atomic_xor_i64_ret_av_v(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB57_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[2:3], v[0:1], v[4:5] sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4821,6 +4918,7 @@ define void @flat_atomic_xor_i64_ret_av_a(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB58_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -4916,6 +5014,7 @@ define void @flat_atomic_xor_i64_ret_a_av(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB59_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[2:3], v[0:1], v[4:5] sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -5003,6 +5102,7 @@ define void @flat_atomic_xor_i64_ret_v_av(ptr %ptr) #0 { ; GFX950-NEXT: s_cbranch_execz .LBB60_2 ; GFX950-NEXT: ; %bb.1: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[2:3], v[0:1], v[4:5] sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -5098,6 +5198,7 @@ define void @flat_atomic_xor_i64_noret_a(ptr %ptr) #0 { ; GFX950-NEXT: s_setpc_b64 s[30:31] ; GFX950-NEXT: .LBB61_3: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[0:1], a[0:1] ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -5183,6 +5284,7 @@ define void @flat_atomic_xor_i64_noret_av(ptr %ptr) #0 { ; GFX950-NEXT: s_setpc_b64 s[30:31] ; GFX950-NEXT: .LBB62_3: ; %atomicrmw.global ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3] ; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-NEXT: buffer_inv sc1 diff --git a/llvm/test/CodeGen/AMDGPU/a-v-global-atomic-cmpxchg.ll b/llvm/test/CodeGen/AMDGPU/a-v-global-atomic-cmpxchg.ll index 6f1cb79e66423..e03728da8b004 100644 --- a/llvm/test/CodeGen/AMDGPU/a-v-global-atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/AMDGPU/a-v-global-atomic-cmpxchg.ll @@ -16,6 +16,7 @@ define void @global_atomic_cmpxchg_i32_ret_av_av__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -44,6 +45,7 @@ define void @global_atomic_cmpxchg_i32_ret_av_av__v(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -72,6 +74,7 @@ define void @global_atomic_cmpxchg_i32_ret_av_av__a(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -103,6 +106,7 @@ define void @global_atomic_cmpxchg_i32_ret_a_a__a(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -134,6 +138,7 @@ define void @global_atomic_cmpxchg_i32_ret_a_a__v(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -165,6 +170,7 @@ define void @global_atomic_cmpxchg_i32_ret_v_a__v(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -194,6 +200,7 @@ define void @global_atomic_cmpxchg_i32_ret_a_v__v(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -222,6 +229,7 @@ define void @global_atomic_cmpxchg_i32_ret_v_v__a(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -251,6 +259,7 @@ define void @global_atomic_cmpxchg_i32_ret_av_v__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -279,6 +288,7 @@ define void @global_atomic_cmpxchg_i32_ret_v_av__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v2 ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -309,6 +319,7 @@ define void @global_atomic_cmpxchg_i32_ret_av_a__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -339,6 +350,7 @@ define void @global_atomic_cmpxchg_i32_ret_a_av__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v3, a1 ; CHECK-NEXT: v_accvgpr_read_b32 v2, a0 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap v0, v[0:1], v[2:3], off offset:40 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -371,6 +383,7 @@ define void @global_atomic_cmpxchg_i64_ret_av_av__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[2:3] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -399,6 +412,7 @@ define void @global_atomic_cmpxchg_i64_ret_av_av__v(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[2:3] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -427,6 +441,7 @@ define void @global_atomic_cmpxchg_i64_ret_av_av__a(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[2:3] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -461,6 +476,7 @@ define void @global_atomic_cmpxchg_i64_ret_a_a__a(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v4, a0 ; CHECK-NEXT: v_accvgpr_read_b32 v5, a1 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -495,6 +511,7 @@ define void @global_atomic_cmpxchg_i64_ret_a_a__v(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: v_accvgpr_read_b32 v4, a0 ; CHECK-NEXT: v_accvgpr_read_b32 v5, a1 ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -525,6 +542,7 @@ define void @global_atomic_cmpxchg_i64_ret_v_a__v(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[4:5] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -555,6 +573,7 @@ define void @global_atomic_cmpxchg_i64_ret_a_v__v(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[2:3] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -583,6 +602,7 @@ define void @global_atomic_cmpxchg_i64_ret_v_v__a(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[2:3] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -613,6 +633,7 @@ define void @global_atomic_cmpxchg_i64_ret_av_v__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[2:3] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -641,6 +662,7 @@ define void @global_atomic_cmpxchg_i64_ret_v_av__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[2:3] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -671,6 +693,7 @@ define void @global_atomic_cmpxchg_i64_ret_av_a__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[4:5] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 @@ -701,6 +724,7 @@ define void @global_atomic_cmpxchg_i64_ret_a_av__av(ptr addrspace(1) %ptr) #0 { ; CHECK-NEXT: ; def v[2:3] ; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: buffer_wbl2 +; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: global_atomic_cmpswap_x2 v[0:1], v[0:1], v[2:5], off offset:80 glc ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: buffer_invl2 diff --git a/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll index b6fe0c756a106..76ef16ad33462 100644 --- a/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll +++ b/llvm/test/CodeGen/AMDGPU/a-v-global-atomicrmw.ll @@ -16,6 +16,7 @@ define void @global_atomic_xchg_i32_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -35,6 +36,7 @@ define void @global_atomic_xchg_i32_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -60,6 +62,7 @@ define void @global_atomic_xchg_i32_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -78,6 +81,7 @@ define void @global_atomic_xchg_i32_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -101,6 +105,7 @@ define void @global_atomic_xchg_i32_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -118,6 +123,7 @@ define void @global_atomic_xchg_i32_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -142,6 +148,7 @@ define void @global_atomic_xchg_i32_ret_av_av(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -158,6 +165,7 @@ define void @global_atomic_xchg_i32_ret_av_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -181,6 +189,7 @@ define void @global_atomic_xchg_i32_ret_av_v(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -197,6 +206,7 @@ define void @global_atomic_xchg_i32_ret_av_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -220,6 +230,7 @@ define void @global_atomic_xchg_i32_ret_av_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -237,6 +248,7 @@ define void @global_atomic_xchg_i32_ret_av_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -262,6 +274,7 @@ define void @global_atomic_xchg_i32_ret_a_av(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -280,6 +293,7 @@ define void @global_atomic_xchg_i32_ret_a_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -303,6 +317,7 @@ define void @global_atomic_xchg_i32_ret_v_av(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -319,6 +334,7 @@ define void @global_atomic_xchg_i32_ret_v_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v0, v[0:1], v2, off offset:40 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -577,6 +593,7 @@ define void @global_atomic_xchg_i32_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def a0 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v[0:1], a0, off offset:40 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -590,6 +607,7 @@ define void @global_atomic_xchg_i32_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def a0 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v[0:1], a0, off offset:40 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -608,6 +626,7 @@ define void @global_atomic_xchg_i32_noret_av(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v2 ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap v[0:1], v2, off offset:40 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -621,6 +640,7 @@ define void @global_atomic_xchg_i32_noret_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap v[0:1], v2, off offset:40 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -646,6 +666,7 @@ define void @global_atomic_xchg_i64_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -667,6 +688,7 @@ define void @global_atomic_xchg_i64_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -694,6 +716,7 @@ define void @global_atomic_xchg_i64_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -713,6 +736,7 @@ define void @global_atomic_xchg_i64_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -736,6 +760,7 @@ define void @global_atomic_xchg_i64_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v[2:3] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -754,6 +779,7 @@ define void @global_atomic_xchg_i64_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -779,6 +805,7 @@ define void @global_atomic_xchg_i64_ret_av_av(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v[2:3] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -795,6 +822,7 @@ define void @global_atomic_xchg_i64_ret_av_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -818,6 +846,7 @@ define void @global_atomic_xchg_i64_ret_av_v(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v[2:3] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -834,6 +863,7 @@ define void @global_atomic_xchg_i64_ret_av_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -857,6 +887,7 @@ define void @global_atomic_xchg_i64_ret_av_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v[2:3] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -875,6 +906,7 @@ define void @global_atomic_xchg_i64_ret_av_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -902,6 +934,7 @@ define void @global_atomic_xchg_i64_ret_a_av(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX90A-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -921,6 +954,7 @@ define void @global_atomic_xchg_i64_ret_a_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -944,6 +978,7 @@ define void @global_atomic_xchg_i64_ret_v_av(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v[2:3] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -960,6 +995,7 @@ define void @global_atomic_xchg_i64_ret_v_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[0:1], v[2:3], off offset:80 sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -982,6 +1018,7 @@ define void @global_atomic_xchg_i64_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def a[0:1] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], a[0:1], off ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -995,6 +1032,7 @@ define void @global_atomic_xchg_i64_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def a[0:1] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], a[0:1], off sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1013,6 +1051,7 @@ define void @global_atomic_xchg_i64_noret_av(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: ; def v[2:3] ; GFX90A-NEXT: ;;#ASMEND ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_swap_x2 v[0:1], v[2:3], off ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1026,6 +1065,7 @@ define void @global_atomic_xchg_i64_noret_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_swap_x2 v[0:1], v[2:3], off sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1056,6 +1096,7 @@ define void @global_atomic_xor_expansion_i32_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1087,6 +1128,7 @@ define void @global_atomic_xor_expansion_i32_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1125,6 +1167,7 @@ define void @global_atomic_xor_expansion_i32_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1155,6 +1198,7 @@ define void @global_atomic_xor_expansion_i32_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1191,6 +1235,7 @@ define void @global_atomic_xor_expansion_i32_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1221,6 +1266,7 @@ define void @global_atomic_xor_expansion_i32_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1258,6 +1304,7 @@ define void @global_atomic_xor_expansion_i32_ret_av_av(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1287,6 +1334,7 @@ define void @global_atomic_xor_expansion_i32_ret_av_av(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1323,6 +1371,7 @@ define void @global_atomic_xor_expansion_i32_ret_av_v(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1352,6 +1401,7 @@ define void @global_atomic_xor_expansion_i32_ret_av_v(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1388,6 +1438,7 @@ define void @global_atomic_xor_expansion_i32_ret_av_a(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1418,6 +1469,7 @@ define void @global_atomic_xor_expansion_i32_ret_av_a(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1456,6 +1508,7 @@ define void @global_atomic_xor_expansion_i32_ret_a_av(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1486,6 +1539,7 @@ define void @global_atomic_xor_expansion_i32_ret_a_av(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1522,6 +1576,7 @@ define void @global_atomic_xor_expansion_i32_ret_v_av(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1551,6 +1606,7 @@ define void @global_atomic_xor_expansion_i32_ret_v_av(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1645,6 +1701,7 @@ define void @global_atomic_xor_expansion_i32_ret_av_av_no_agprs(ptr addrspace(1) ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v0, v1, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v0, v[2:3], v[0:1], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1789,6 +1846,7 @@ define void @global_atomic_xor_expansion_i32_ret_av_av_no_agprs(ptr addrspace(1) ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v0, v1, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v0, v[2:3], v[0:1], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1885,6 +1943,7 @@ define void @global_atomic_xor_expansion_i32_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1912,6 +1971,7 @@ define void @global_atomic_xor_expansion_i32_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -1943,6 +2003,7 @@ define void @global_atomic_xor_expansion_i32_noret_av(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1969,6 +2030,7 @@ define void @global_atomic_xor_expansion_i32_noret_av(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: v_xor_b32_e32 v2, v3, v4 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2008,6 +2070,7 @@ define void @global_atomic_xor_expansion_i64_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2042,6 +2105,7 @@ define void @global_atomic_xor_expansion_i64_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2083,6 +2147,7 @@ define void @global_atomic_xor_expansion_i64_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2115,6 +2180,7 @@ define void @global_atomic_xor_expansion_i64_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2152,6 +2218,7 @@ define void @global_atomic_xor_expansion_i64_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2184,6 +2251,7 @@ define void @global_atomic_xor_expansion_i64_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2223,6 +2291,7 @@ define void @global_atomic_xor_expansion_i64_ret_av_av(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2253,6 +2322,7 @@ define void @global_atomic_xor_expansion_i64_ret_av_av(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2290,6 +2360,7 @@ define void @global_atomic_xor_expansion_i64_ret_av_v(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2320,6 +2391,7 @@ define void @global_atomic_xor_expansion_i64_ret_av_v(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2357,6 +2429,7 @@ define void @global_atomic_xor_expansion_i64_ret_av_a(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2389,6 +2462,7 @@ define void @global_atomic_xor_expansion_i64_ret_av_a(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2430,6 +2504,7 @@ define void @global_atomic_xor_expansion_i64_ret_a_av(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2462,6 +2537,7 @@ define void @global_atomic_xor_expansion_i64_ret_a_av(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2499,6 +2575,7 @@ define void @global_atomic_xor_expansion_i64_ret_v_av(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2529,6 +2606,7 @@ define void @global_atomic_xor_expansion_i64_ret_v_av(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2567,6 +2645,7 @@ define void @global_atomic_xor_expansion_i64_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2596,6 +2675,7 @@ define void @global_atomic_xor_expansion_i64_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2628,6 +2708,7 @@ define void @global_atomic_xor_expansion_i64_noret_av(ptr addrspace(1) %ptr) #0 ; GFX90A-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX90A-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2655,6 +2736,7 @@ define void @global_atomic_xor_expansion_i64_noret_av(ptr addrspace(1) %ptr) #0 ; GFX950-NEXT: v_xor_b32_e32 v3, v5, v7 ; GFX950-NEXT: v_xor_b32_e32 v2, v4, v6 ; GFX950-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_cmpswap_x2 v[2:3], v[0:1], v[2:5], off sc0 sc1 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc0 sc1 @@ -2703,6 +2785,7 @@ define void @global_atomic_xor_i32_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v0, v[0:1], v2, off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -2744,6 +2827,7 @@ define void @global_atomic_xor_i32_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v0, v[0:1], v2, off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -2782,6 +2866,7 @@ define void @global_atomic_xor_i32_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v0, v[0:1], v2, off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -2820,6 +2905,7 @@ define void @global_atomic_xor_i32_ret_av_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v0, v[0:1], v2, off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -2857,6 +2943,7 @@ define void @global_atomic_xor_i32_ret_av_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v0, v[0:1], v2, off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -2895,6 +2982,7 @@ define void @global_atomic_xor_i32_ret_av_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v0, v[0:1], v2, off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -2936,6 +3024,7 @@ define void @global_atomic_xor_i32_ret_a_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: s_nop 0 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v0, v[0:1], v2, off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -2973,6 +3062,7 @@ define void @global_atomic_xor_i32_ret_v_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v0, v[0:1], v2, off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3240,6 +3330,7 @@ define void @global_atomic_xor_i32_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def a0 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v[0:1], a0, off ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3269,6 +3360,7 @@ define void @global_atomic_xor_i32_noret_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v2 ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor v[0:1], v2, off ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3313,6 +3405,7 @@ define void @global_atomic_xor_i64_ret_a_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[0:1], v[2:3], off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3357,6 +3450,7 @@ define void @global_atomic_xor_i64_ret_a_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[0:1], v[2:3], off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3396,6 +3490,7 @@ define void @global_atomic_xor_i64_ret_v_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[0:1], v[2:3], off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3435,6 +3530,7 @@ define void @global_atomic_xor_i64_ret_av_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[0:1], v[2:3], off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3472,6 +3568,7 @@ define void @global_atomic_xor_i64_ret_av_v(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[0:1], v[2:3], off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3511,6 +3608,7 @@ define void @global_atomic_xor_i64_ret_av_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[0:1], v[2:3], off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3555,6 +3653,7 @@ define void @global_atomic_xor_i64_ret_a_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: v_accvgpr_read_b32 v3, a1 ; GFX950-NEXT: v_accvgpr_read_b32 v2, a0 ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[0:1], v[2:3], off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3592,6 +3691,7 @@ define void @global_atomic_xor_i64_ret_v_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[0:1], v[2:3], off sc0 ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3625,6 +3725,7 @@ define void @global_atomic_xor_i64_noret_a(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def a[0:1] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], a[0:1], off ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 @@ -3654,6 +3755,7 @@ define void @global_atomic_xor_i64_noret_av(ptr addrspace(1) %ptr) #0 { ; GFX950-NEXT: ; def v[2:3] ; GFX950-NEXT: ;;#ASMEND ; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: global_atomic_xor_x2 v[0:1], v[2:3], off ; GFX950-NEXT: s_waitcnt vmcnt(0) ; GFX950-NEXT: buffer_inv sc1 diff --git a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir index c1617574becc3..f4b0568c8121d 100644 --- a/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir +++ b/llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir @@ -27,11 +27,11 @@ body: | ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.1: @@ -97,187 +97,187 @@ body: | ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec - ; GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) - ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-NEXT: {{ $}} ; GFX90A-NEXT: bb.1: @@ -289,182 +289,182 @@ body: | ; GFX90A-NEXT: bb.2: ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -521,12 +521,12 @@ body: | ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec - ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX908-FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: bb.1: @@ -592,188 +592,188 @@ body: | ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_ADD_U32_e32 8904, $vgpr40, implicit $exec - ; GFX90A-FLATSCR-NEXT: $agpr0 = SCRATCH_LOAD_DWORD killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr0 = SCRATCH_LOAD_DWORD killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-FLATSCR-NEXT: {{ $}} ; GFX90A-FLATSCR-NEXT: bb.1: @@ -785,182 +785,182 @@ body: | ; GFX90A-FLATSCR-NEXT: bb.2: ; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} - ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-FLATSCR-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -1045,13 +1045,13 @@ body: | ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1 - ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) + ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) ; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.1: @@ -1117,188 +1117,188 @@ body: | ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec - ; GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1 :: (load (s32) from %stack.1, addrspace 5) - ; GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) - ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) + ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-NEXT: {{ $}} ; GFX90A-NEXT: bb.1: @@ -1310,182 +1310,182 @@ body: | ; GFX90A-NEXT: bb.2: ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -1542,14 +1542,14 @@ body: | ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec - ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX908-FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1 - ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1 + 4, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) ; GFX908-FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: bb.1: @@ -1615,188 +1615,188 @@ body: | ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_ADD_U32_e32 8904, $vgpr40, implicit $exec - ; GFX90A-FLATSCR-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.1, align 4, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.1, align 4, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-FLATSCR-NEXT: {{ $}} ; GFX90A-FLATSCR-NEXT: bb.1: @@ -1808,182 +1808,182 @@ body: | ; GFX90A-FLATSCR-NEXT: bb.2: ; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} - ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-FLATSCR-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -2068,15 +2068,15 @@ body: | ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 - ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) + ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) ; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 8, addrspace 5) + ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 8, addrspace 5) ; GFX908-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.1: @@ -2142,189 +2142,189 @@ body: | ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec - ; GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 :: (load (s32) from %stack.1, addrspace 5) - ; GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) - ; GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 8, addrspace 5) - ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) + ; GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 8, addrspace 5) + ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-NEXT: {{ $}} ; GFX90A-NEXT: bb.1: @@ -2336,182 +2336,182 @@ body: | ; GFX90A-NEXT: bb.2: ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -2568,16 +2568,16 @@ body: | ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec - ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX908-FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 - ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1 + 4, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) ; GFX908-FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1 + 8, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD $vgpr1, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1 + 8, addrspace 5) ; GFX908-FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: bb.1: @@ -2643,188 +2643,188 @@ body: | ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_ADD_U32_e32 8904, $vgpr40, implicit $exec - ; GFX90A-FLATSCR-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3 killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.1, align 4, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3 killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.1, align 4, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-FLATSCR-NEXT: {{ $}} ; GFX90A-FLATSCR-NEXT: bb.1: @@ -2836,182 +2836,182 @@ body: | ; GFX90A-FLATSCR-NEXT: bb.2: ; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} - ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-FLATSCR-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -3096,11 +3096,11 @@ body: | ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0 ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.1: @@ -3166,187 +3166,187 @@ body: | ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr0, killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr0, killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-NEXT: {{ $}} ; GFX90A-NEXT: bb.1: @@ -3358,182 +3358,182 @@ body: | ; GFX90A-NEXT: bb.2: ; GFX90A-NEXT: liveins: $agpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -3590,12 +3590,12 @@ body: | ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0 ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: bb.1: @@ -3661,188 +3661,188 @@ body: | ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_ADD_U32_e32 8904, $vgpr40, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD $agpr0, killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD $agpr0, killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-FLATSCR-NEXT: {{ $}} ; GFX90A-FLATSCR-NEXT: bb.1: @@ -3854,182 +3854,182 @@ body: | ; GFX90A-FLATSCR-NEXT: bb.2: ; GFX90A-FLATSCR-NEXT: liveins: $agpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} - ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-FLATSCR-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -4113,13 +4113,13 @@ body: | ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1 ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.1, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.1 + 4, addrspace 5) - ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.1: @@ -4185,188 +4185,188 @@ body: | ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr0, $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 :: (store (s32) into %stack.1, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr1, killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.1 + 4, addrspace 5) - ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr0, $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr1, killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-NEXT: {{ $}} ; GFX90A-NEXT: bb.1: @@ -4378,182 +4378,182 @@ body: | ; GFX90A-NEXT: bb.2: ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -4610,14 +4610,14 @@ body: | ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1 ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: (store (s32) into %stack.1, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 4, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: (store (s32) into %stack.1 + 4, addrspace 5) - ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 4, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: bb.1: @@ -4683,188 +4683,188 @@ body: | ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_ADD_U32_e32 8904, $vgpr40, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $agpr0_agpr1, killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.1, align 4, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $agpr0_agpr1, killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.1, align 4, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-FLATSCR-NEXT: {{ $}} ; GFX90A-FLATSCR-NEXT: bb.1: @@ -4876,182 +4876,182 @@ body: | ; GFX90A-FLATSCR-NEXT: bb.2: ; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} - ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-FLATSCR-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -5134,15 +5134,15 @@ body: | ; GFX908-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1 ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.1, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.1 + 4, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2 - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.1 + 8, addrspace 5) - ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 8, addrspace 5) + ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.1: @@ -5208,189 +5208,189 @@ body: | ; GFX90A-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr80, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr81, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr82, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr83, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr84, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr85, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr86, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr87, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr88, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr89, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr90, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr91, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr92, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr93, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr94, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr95, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr96, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr97, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr98, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr99, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr100, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr101, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr102, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr103, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr104, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr105, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr106, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr107, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr108, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr109, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr110, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr111, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr112, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr113, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr114, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr115, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr116, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr117, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr118, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr119, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr120, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr121, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr122, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr123, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr124, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr125, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr126, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr127, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr128, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr129, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr130, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr131, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr132, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr133, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr134, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr135, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr136, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr137, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr138, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr139, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr140, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr141, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr142, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr143, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr144, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr145, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr146, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr147, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr148, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr149, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr150, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr151, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr152, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr153, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr154, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr155, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr156, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr157, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr158, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr159, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr160, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr161, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr162, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr163, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr164, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr165, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr166, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr167, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr168, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr169, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr170, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr171, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr172, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr173, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr174, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr175, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr176, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr177, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr178, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr179, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr180, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr181, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr182, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr183, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr184, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr185, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr186, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr187, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr188, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr189, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr190, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr191, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr192, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr193, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr194, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr195, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr196, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr197, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr198, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr199, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr200, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr201, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr202, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr203, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr204, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr205, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr206, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr207, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr208, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr209, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr210, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr211, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr212, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr213, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr214, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr215, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr216, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr217, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr218, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr219, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr220, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr221, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr222, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr223, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr224, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr225, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr226, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr227, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr228, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr229, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr230, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr231, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr232, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr233, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr234, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr235, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr236, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr237, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr238, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr239, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr240, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr241, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr242, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr243, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr244, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr245, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr246, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr247, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr248, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr249, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr250, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr251, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr252, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr253, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr254, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr255, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-NEXT: $vgpr40 = V_MOV_B32_e32 8904, implicit $exec - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr0, $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.1, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr1, $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.1 + 4, addrspace 5) - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr2, killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.1 + 8, addrspace 5) - ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr0, $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr1, $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFEN $agpr2, killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 8, addrspace 5) + ; GFX90A-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 704, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-NEXT: {{ $}} ; GFX90A-NEXT: bb.1: @@ -5402,182 +5402,182 @@ body: | ; GFX90A-NEXT: bb.2: ; GFX90A-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-NEXT: $agpr255 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-NEXT: $agpr254 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-NEXT: $agpr253 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-NEXT: $agpr252 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-NEXT: $agpr251 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-NEXT: $agpr250 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-NEXT: $agpr249 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-NEXT: $agpr248 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-NEXT: $agpr247 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-NEXT: $agpr246 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-NEXT: $agpr245 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-NEXT: $agpr244 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-NEXT: $agpr243 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-NEXT: $agpr242 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-NEXT: $agpr241 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-NEXT: $agpr240 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-NEXT: $agpr239 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-NEXT: $agpr238 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-NEXT: $agpr237 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-NEXT: $agpr236 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-NEXT: $agpr235 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-NEXT: $agpr234 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-NEXT: $agpr233 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-NEXT: $agpr232 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-NEXT: $agpr231 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-NEXT: $agpr230 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-NEXT: $agpr229 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-NEXT: $agpr228 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-NEXT: $agpr227 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-NEXT: $agpr226 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-NEXT: $agpr225 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-NEXT: $agpr224 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-NEXT: $agpr223 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-NEXT: $agpr222 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-NEXT: $agpr221 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 136, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-NEXT: $agpr220 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 140, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-NEXT: $agpr219 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 144, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-NEXT: $agpr218 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 148, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-NEXT: $agpr217 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 152, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-NEXT: $agpr216 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 156, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-NEXT: $agpr215 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-NEXT: $agpr214 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 164, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-NEXT: $agpr213 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 168, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-NEXT: $agpr212 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 172, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-NEXT: $agpr211 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 176, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-NEXT: $agpr210 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 180, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-NEXT: $agpr209 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 184, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-NEXT: $agpr208 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 188, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-NEXT: $agpr207 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 192, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-NEXT: $agpr206 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 196, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-NEXT: $agpr205 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 200, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-NEXT: $agpr204 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 204, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-NEXT: $agpr203 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 208, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-NEXT: $agpr202 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 212, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-NEXT: $agpr201 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 216, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-NEXT: $agpr200 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 220, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-NEXT: $agpr199 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 224, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-NEXT: $agpr198 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 228, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-NEXT: $agpr197 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 232, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-NEXT: $agpr196 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 236, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-NEXT: $agpr195 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 240, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-NEXT: $agpr194 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 244, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-NEXT: $agpr193 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 248, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-NEXT: $agpr192 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 252, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-NEXT: $agpr191 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 256, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-NEXT: $agpr190 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 260, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-NEXT: $agpr189 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 264, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-NEXT: $agpr188 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 268, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-NEXT: $agpr187 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 272, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-NEXT: $agpr186 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 276, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-NEXT: $agpr185 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 280, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-NEXT: $agpr184 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 284, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-NEXT: $agpr183 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 288, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-NEXT: $agpr182 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 292, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-NEXT: $agpr181 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 296, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-NEXT: $agpr180 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 300, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-NEXT: $agpr179 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 304, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-NEXT: $agpr178 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 308, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-NEXT: $agpr177 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 312, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-NEXT: $agpr176 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 316, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-NEXT: $agpr175 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 320, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-NEXT: $agpr174 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 324, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-NEXT: $agpr173 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 328, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-NEXT: $agpr172 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 332, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-NEXT: $agpr171 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 336, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-NEXT: $agpr170 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 340, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-NEXT: $agpr169 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 344, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-NEXT: $agpr168 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 348, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-NEXT: $agpr167 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 352, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-NEXT: $agpr166 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 356, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-NEXT: $agpr165 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 360, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-NEXT: $agpr164 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 364, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-NEXT: $agpr163 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 368, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-NEXT: $agpr162 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 372, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-NEXT: $agpr161 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 376, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-NEXT: $agpr160 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 380, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-NEXT: $agpr159 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 384, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-NEXT: $agpr158 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 388, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-NEXT: $agpr157 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 392, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-NEXT: $agpr156 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 396, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-NEXT: $agpr155 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 400, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-NEXT: $agpr154 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 404, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-NEXT: $agpr153 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 408, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-NEXT: $agpr152 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 412, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-NEXT: $agpr151 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 416, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-NEXT: $agpr150 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 420, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-NEXT: $agpr149 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 424, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-NEXT: $agpr148 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 428, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-NEXT: $agpr147 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 432, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-NEXT: $agpr146 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 436, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-NEXT: $agpr145 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 440, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-NEXT: $agpr144 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 444, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-NEXT: $agpr143 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 448, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-NEXT: $agpr142 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 452, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-NEXT: $agpr141 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 456, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-NEXT: $agpr140 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 460, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-NEXT: $agpr139 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 464, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-NEXT: $agpr138 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 468, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-NEXT: $agpr137 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 472, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-NEXT: $agpr136 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 476, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-NEXT: $agpr135 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 480, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-NEXT: $agpr134 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 484, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-NEXT: $agpr133 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 488, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-NEXT: $agpr132 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 492, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-NEXT: $agpr131 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 496, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-NEXT: $agpr130 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 500, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-NEXT: $agpr129 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 504, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-NEXT: $agpr128 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 508, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-NEXT: $agpr127 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 512, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-NEXT: $agpr126 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 516, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-NEXT: $agpr125 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 520, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-NEXT: $agpr124 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 524, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-NEXT: $agpr123 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 528, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-NEXT: $agpr122 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 532, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-NEXT: $agpr121 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 536, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-NEXT: $agpr120 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 540, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-NEXT: $agpr119 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 544, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-NEXT: $agpr118 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 548, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-NEXT: $agpr117 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 552, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-NEXT: $agpr116 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 556, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-NEXT: $agpr115 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 560, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-NEXT: $agpr114 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 564, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-NEXT: $agpr113 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 568, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-NEXT: $agpr112 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 572, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-NEXT: $agpr111 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 576, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-NEXT: $agpr110 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 580, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-NEXT: $agpr109 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 584, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-NEXT: $agpr108 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 588, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-NEXT: $agpr107 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 592, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-NEXT: $agpr106 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 596, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-NEXT: $agpr105 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 600, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-NEXT: $agpr104 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 604, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-NEXT: $agpr103 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 608, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-NEXT: $agpr102 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 612, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-NEXT: $agpr101 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 616, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-NEXT: $agpr100 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 620, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-NEXT: $agpr99 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 624, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-NEXT: $agpr98 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 628, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-NEXT: $agpr97 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 632, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-NEXT: $agpr96 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 636, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-NEXT: $agpr95 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 640, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-NEXT: $agpr94 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 644, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-NEXT: $agpr93 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 648, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-NEXT: $agpr92 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 652, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-NEXT: $agpr91 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 656, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-NEXT: $agpr90 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 660, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-NEXT: $agpr89 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 664, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-NEXT: $agpr88 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 668, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-NEXT: $agpr87 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 672, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-NEXT: $agpr86 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 676, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-NEXT: $agpr85 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 680, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-NEXT: $agpr84 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 684, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-NEXT: $agpr83 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 688, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-NEXT: $agpr82 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 692, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-NEXT: $agpr81 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 696, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-NEXT: $agpr80 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 700, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec @@ -5634,16 +5634,16 @@ body: | ; GFX908-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $agpr0_agpr1 ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec ; GFX908-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.1, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1 + 4, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) ; GFX908-FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2 - ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 8, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.1 + 8, addrspace 5) - ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX908-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, $vgpr1, 8, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 8, addrspace 5) + ; GFX908-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX908-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX908-FLATSCR-NEXT: {{ $}} ; GFX908-FLATSCR-NEXT: bb.1: @@ -5709,188 +5709,188 @@ body: | ; GFX90A-FLATSCR-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr77, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr78, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr79, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.50, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr80, $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr81, $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr82, $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr83, $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr84, $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr85, $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr86, $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr87, $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr88, $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr89, $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr90, $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr91, $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr92, $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr93, $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr94, $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr95, $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr96, $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr97, $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr98, $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr99, $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr100, $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr101, $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr102, $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr103, $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr104, $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr105, $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr106, $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr107, $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr108, $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr109, $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr110, $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr111, $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr112, $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr113, $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr114, $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr115, $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr116, $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr117, $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr118, $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr119, $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr120, $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr121, $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr122, $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr123, $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr124, $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr125, $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr126, $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr127, $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr128, $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr129, $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr130, $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr131, $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr132, $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr133, $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr134, $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr135, $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr136, $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr137, $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr138, $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr139, $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr140, $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr141, $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr142, $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr143, $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr144, $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr145, $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr146, $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr147, $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr148, $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr149, $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr150, $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr151, $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr152, $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr153, $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr154, $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr155, $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr156, $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr157, $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr158, $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr159, $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr160, $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr161, $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr162, $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr163, $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr164, $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr165, $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr166, $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr167, $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr168, $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr169, $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr170, $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr171, $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr172, $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr173, $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr174, $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr175, $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr176, $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr177, $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr178, $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr179, $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr180, $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr181, $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr182, $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr183, $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr184, $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr185, $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr186, $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr187, $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr188, $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr189, $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr190, $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr191, $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr192, $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr193, $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr194, $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr195, $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr196, $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr197, $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr198, $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr199, $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr200, $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr201, $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr202, $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr203, $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr204, $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr205, $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr206, $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr207, $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr208, $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr209, $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr210, $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr211, $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr212, $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr213, $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr214, $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr215, $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr216, $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr217, $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr218, $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr219, $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr220, $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr221, $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr222, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr223, $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr224, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr225, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr226, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr227, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr228, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr229, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr230, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr231, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr232, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr233, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr234, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr235, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr236, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr237, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr238, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr239, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr240, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr241, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr242, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr243, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr244, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr245, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr246, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr247, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr248, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr249, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr250, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr251, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr252, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr253, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr254, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr255, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.225, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX90A-FLATSCR-NEXT: $vgpr40 = V_ADD_U32_e32 8904, $vgpr40, implicit $exec - ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORDX3 $agpr0_agpr1_agpr2, killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.1, align 4, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.226, addrspace 5) + ; GFX90A-FLATSCR-NEXT: SCRATCH_STORE_DWORDX3 $agpr0_agpr1_agpr2, killed $vgpr40, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.1, align 4, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 704, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.226, addrspace 5) ; GFX90A-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX90A-FLATSCR-NEXT: {{ $}} ; GFX90A-FLATSCR-NEXT: bb.1: @@ -5902,182 +5902,182 @@ body: | ; GFX90A-FLATSCR-NEXT: bb.2: ; GFX90A-FLATSCR-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17, $vgpr18, $vgpr19, $vgpr20, $vgpr21, $vgpr22, $vgpr23, $vgpr24, $vgpr25, $vgpr26, $vgpr27, $vgpr28, $vgpr29, $vgpr30, $vgpr31, $vgpr32, $vgpr33, $vgpr34, $vgpr35, $vgpr36, $vgpr37, $vgpr38, $vgpr39, $vgpr48, $vgpr49, $vgpr50, $vgpr51, $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-FLATSCR-NEXT: {{ $}} - ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.225, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.224, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.223, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.222, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.221, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.220, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.219, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.218, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.217, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.216, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.215, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.214, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.213, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.212, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.211, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.210, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.209, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.208, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.207, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.206, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.205, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.204, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.203, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.202, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.201, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.200, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.199, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.198, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.197, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.196, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.195, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.194, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.193, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.192, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.191, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.190, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.189, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.188, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.187, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.186, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.185, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.184, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.183, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.182, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.181, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.180, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.179, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.178, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.177, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.176, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.175, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.174, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.173, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.172, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.171, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.170, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.169, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.168, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.167, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.166, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.165, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.164, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.163, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.162, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.161, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.160, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.159, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.158, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.157, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.156, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.155, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.154, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.153, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.152, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.151, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.150, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.149, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.148, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.147, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.146, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.145, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.144, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.143, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.142, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.141, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.140, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.139, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.138, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.137, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.136, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.135, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.134, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.133, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.132, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.131, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.130, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.129, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.128, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.127, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.126, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.125, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.124, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.123, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.122, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.121, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.120, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.119, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.118, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.117, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.116, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.115, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.114, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.113, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.112, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.111, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.110, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.109, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.108, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.107, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.106, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.105, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.104, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.103, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.102, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.101, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.100, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.99, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.98, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.97, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.96, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.95, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.94, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.93, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.92, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.91, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.90, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.89, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.88, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.87, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.86, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.85, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.84, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.83, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.82, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.81, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.80, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.79, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.78, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.77, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.76, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.75, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.74, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.68, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.67, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.66, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.65, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.64, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.63, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.62, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.61, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.60, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.59, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.58, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.57, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.56, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.55, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.54, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.53, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.52, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.51, addrspace 5) - ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.50, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr255 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.225, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr254 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.224, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr253 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.223, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr252 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.222, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr251 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.221, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr250 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.220, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr249 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.219, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr248 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.218, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr247 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.217, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr246 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.216, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr245 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.215, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr244 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.214, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr243 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.213, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr242 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.212, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr241 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.211, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr240 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.210, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr239 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.209, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr238 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.208, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr237 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.207, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr236 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.206, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr235 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.205, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr234 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.204, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr233 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.203, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr232 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.202, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr231 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.201, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr230 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.200, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr229 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.199, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr228 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.198, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr227 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.197, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr226 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.196, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr225 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.195, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr224 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.194, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr223 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 128, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.193, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr222 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.192, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr221 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 136, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.191, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr220 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 140, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.190, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr219 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 144, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.189, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr218 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 148, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.188, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr217 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 152, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.187, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr216 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 156, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.186, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr215 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.185, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr214 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 164, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.184, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr213 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 168, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.183, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr212 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 172, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.182, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr211 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 176, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.181, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr210 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 180, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.180, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr209 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 184, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.179, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr208 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 188, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.178, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr207 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 192, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.177, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr206 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 196, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.176, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr205 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 200, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.175, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr204 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 204, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.174, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr203 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 208, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.173, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr202 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 212, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.172, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr201 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 216, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.171, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr200 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 220, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.170, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr199 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 224, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.169, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr198 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 228, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.168, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr197 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 232, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.167, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr196 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 236, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.166, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr195 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 240, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.165, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr194 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 244, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.164, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr193 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 248, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.163, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 252, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.162, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 256, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.161, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr190 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 260, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.160, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr189 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 264, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.159, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr188 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 268, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.158, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr187 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 272, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.157, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr186 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 276, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.156, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr185 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 280, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.155, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr184 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 284, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.154, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr183 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 288, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.153, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr182 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 292, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.152, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr181 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 296, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.151, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr180 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 300, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.150, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr179 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 304, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.149, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr178 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 308, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.148, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr177 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 312, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.147, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr176 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 316, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.146, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr175 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 320, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.145, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr174 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 324, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.144, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr173 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 328, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.143, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr172 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 332, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.142, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr171 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 336, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.141, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr170 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 340, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.140, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr169 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 344, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.139, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr168 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 348, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.138, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr167 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 352, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.137, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr166 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 356, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.136, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr165 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 360, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.135, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr164 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 364, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.134, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr163 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 368, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.133, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr162 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 372, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.132, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr161 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 376, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.131, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr160 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 380, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.130, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr159 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 384, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.129, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr158 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 388, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.128, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr157 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 392, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.127, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr156 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 396, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.126, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr155 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 400, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.125, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr154 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 404, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.124, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr153 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 408, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.123, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr152 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 412, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.122, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr151 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 416, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.121, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr150 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 420, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.120, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr149 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 424, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.119, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr148 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 428, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.118, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr147 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 432, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.117, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr146 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 436, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.116, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr145 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 440, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.115, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr144 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 444, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.114, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr143 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 448, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.113, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr142 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 452, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.112, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr141 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 456, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.111, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr140 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 460, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.110, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr139 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 464, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.109, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr138 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 468, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.108, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr137 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 472, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.107, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr136 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 476, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.106, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr135 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 480, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.105, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr134 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 484, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.104, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr133 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 488, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.103, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr132 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 492, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.102, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr131 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 496, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.101, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr130 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 500, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.100, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr129 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 504, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.99, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr128 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 508, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.98, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr127 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 512, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.97, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr126 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 516, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.96, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr125 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 520, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.95, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr124 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 524, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.94, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr123 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 528, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.93, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr122 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 532, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.92, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr121 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 536, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.91, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr120 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 540, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.90, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr119 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 544, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.89, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr118 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 548, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.88, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr117 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 552, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.87, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr116 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 556, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.86, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr115 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 560, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.85, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr114 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 564, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.84, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr113 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 568, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.83, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr112 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 572, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.82, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr111 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 576, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.81, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr110 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 580, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.80, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr109 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 584, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.79, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr108 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 588, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.78, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr107 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 592, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.77, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr106 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 596, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.76, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr105 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 600, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.75, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr104 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 604, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.74, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr103 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 608, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr102 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 612, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr101 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 616, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr100 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 620, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr99 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 624, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr98 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 628, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.68, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr97 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 632, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.67, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr96 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 636, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.66, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr95 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 640, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.65, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr94 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 644, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.64, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr93 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 648, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.63, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr92 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 652, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.62, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr91 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 656, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.61, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr90 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 660, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.60, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr89 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 664, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.59, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr88 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 668, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.58, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr87 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 672, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.57, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr86 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 676, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.56, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr85 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 680, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.55, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr84 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 684, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.54, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr83 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 688, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.53, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr82 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 692, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.52, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr81 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 696, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.51, addrspace 5) + ; GFX90A-FLATSCR-NEXT: $agpr80 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 700, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.50, addrspace 5) ; GFX90A-FLATSCR-NEXT: $agpr79 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr78 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec ; GFX90A-FLATSCR-NEXT: $agpr77 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll index 1d55dcf5056f8..7a8ca5674487b 100644 --- a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll +++ b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll @@ -624,26 +624,22 @@ define amdgpu_kernel void @introduced_copy_to_sgpr(i64 %arg, i32 %arg1, i32 %arg ; GFX908-NEXT: s_cbranch_vccnz .LBB3_7 ; GFX908-NEXT: ; %bb.6: ; %bb51 ; GFX908-NEXT: ; in Loop: Header=BB3_5 Depth=2 -; GFX908-NEXT: v_cvt_f32_f16_sdwa v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX908-NEXT: v_cvt_f32_f16_e32 v21, v21 -; GFX908-NEXT: v_cvt_f32_f16_sdwa v23, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX908-NEXT: v_cvt_f32_f16_e32 v20, v20 -; GFX908-NEXT: v_add_f32_e32 v24, v18, v12 -; GFX908-NEXT: v_add_f32_e32 v25, v19, v13 -; GFX908-NEXT: v_add_f32_e32 v26, 0, v12 -; GFX908-NEXT: v_add_f32_e32 v27, 0, v13 -; GFX908-NEXT: v_add_f32_e32 v15, v22, v15 -; GFX908-NEXT: v_add_f32_e32 v14, v21, v14 -; GFX908-NEXT: v_add_f32_e32 v13, v23, v13 -; GFX908-NEXT: v_add_f32_e32 v12, v20, v12 -; GFX908-NEXT: v_add_f32_e32 v5, v5, v25 -; GFX908-NEXT: v_add_f32_e32 v4, v4, v24 -; GFX908-NEXT: v_add_f32_e32 v7, v7, v27 -; GFX908-NEXT: v_add_f32_e32 v6, v6, v26 -; GFX908-NEXT: v_add_f32_e32 v8, v8, v14 +; GFX908-NEXT: v_add_f32_e32 v22, v18, v12 +; GFX908-NEXT: v_add_f32_e32 v23, v19, v13 +; GFX908-NEXT: v_add_f32_e32 v24, 0, v12 +; GFX908-NEXT: v_add_f32_e32 v25, 0, v13 +; GFX908-NEXT: v_fma_mix_f32 v14, v21, 1.0, v14 op_sel_hi:[1,1,0] +; GFX908-NEXT: v_fma_mix_f32 v15, v21, 1.0, v15 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX908-NEXT: v_fma_mix_f32 v12, v20, 1.0, v12 op_sel_hi:[1,1,0] +; GFX908-NEXT: v_fma_mix_f32 v13, v20, 1.0, v13 op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX908-NEXT: v_add_f32_e32 v5, v5, v23 +; GFX908-NEXT: v_add_f32_e32 v4, v4, v22 +; GFX908-NEXT: v_add_f32_e32 v7, v7, v25 +; GFX908-NEXT: v_add_f32_e32 v6, v6, v24 ; GFX908-NEXT: v_add_f32_e32 v9, v9, v15 -; GFX908-NEXT: v_add_f32_e32 v10, v10, v12 +; GFX908-NEXT: v_add_f32_e32 v8, v8, v14 ; GFX908-NEXT: v_add_f32_e32 v11, v11, v13 +; GFX908-NEXT: v_add_f32_e32 v10, v10, v12 ; GFX908-NEXT: s_branch .LBB3_4 ; GFX908-NEXT: .LBB3_7: ; in Loop: Header=BB3_5 Depth=2 ; GFX908-NEXT: s_mov_b64 s[22:23], s[18:19] diff --git a/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir b/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir index 47d489b7f35ca..973702ff9479f 100644 --- a/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir @@ -21,18 +21,18 @@ body: | ; GFX942-NEXT: renamable $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27 = IMPLICIT_DEF ; GFX942-NEXT: renamable $agpr28_agpr29 = IMPLICIT_DEF ; GFX942-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; GFX942-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; GFX942-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; GFX942-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; GFX942-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; GFX942-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; GFX942-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) ; GFX942-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr15, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX942-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr14, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 - ; GFX942-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr12_vgpr13, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s64) into %stack.0 + 48, align 4, addrspace 5) - ; GFX942-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; GFX942-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; GFX942-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; GFX942-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr12_vgpr13, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s64) into %stack.0 + 48, align 4, addrspace 5) + ; GFX942-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; GFX942-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; GFX942-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) ; GFX942-NEXT: $agpr15 = COPY $agpr30, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 ; GFX942-NEXT: $agpr14 = COPY $agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; GFX942-NEXT: $agpr12_agpr13 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0 + 48, align 4, addrspace 5) + ; GFX942-NEXT: $agpr12_agpr13 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0 + 48, align 4, addrspace 5) ; GFX942-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 renamable $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27 = IMPLICIT_DEF renamable $agpr28_agpr29 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll index 6c09950689efe..5a06737d923f1 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll @@ -68693,7 +68693,6 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: v_writelane_b32 v40, s53, 13 ; SI-NEXT: v_writelane_b32 v40, s54, 14 ; SI-NEXT: v_writelane_b32 v40, s55, 15 -; SI-NEXT: s_mov_b32 s92, s16 ; SI-NEXT: v_writelane_b32 v40, s64, 16 ; SI-NEXT: v_writelane_b32 v40, s65, 17 ; SI-NEXT: v_writelane_b32 v40, s66, 18 @@ -68710,52 +68709,54 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: v_writelane_b32 v40, s85, 29 ; SI-NEXT: v_writelane_b32 v40, s86, 30 ; SI-NEXT: v_writelane_b32 v40, s87, 31 -; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane ; SI-NEXT: v_writelane_b32 v40, s96, 32 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v41, s23, 0 +; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane ; SI-NEXT: v_writelane_b32 v40, s97, 33 -; SI-NEXT: v_writelane_b32 v41, s21, 1 -; SI-NEXT: v_readfirstlane_b32 s47, v29 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_writelane_b32 v41, s28, 0 +; SI-NEXT: v_writelane_b32 v41, s26, 1 +; SI-NEXT: v_writelane_b32 v41, s23, 2 +; SI-NEXT: v_writelane_b32 v41, s22, 3 ; SI-NEXT: v_writelane_b32 v40, s98, 34 -; SI-NEXT: v_writelane_b32 v41, s47, 2 +; SI-NEXT: v_writelane_b32 v41, s21, 4 ; SI-NEXT: v_writelane_b32 v40, s99, 35 +; SI-NEXT: s_mov_b32 s88, s29 +; SI-NEXT: s_mov_b32 s30, s25 +; SI-NEXT: s_mov_b32 s29, s24 +; SI-NEXT: v_writelane_b32 v41, s20, 5 ; SI-NEXT: v_readfirstlane_b32 s82, v30 -; SI-NEXT: v_readfirstlane_b32 s83, v28 -; SI-NEXT: v_readfirstlane_b32 s44, v27 -; SI-NEXT: v_readfirstlane_b32 s96, v26 -; SI-NEXT: v_readfirstlane_b32 s70, v25 -; SI-NEXT: v_readfirstlane_b32 s68, v24 -; SI-NEXT: v_readfirstlane_b32 s84, v23 +; SI-NEXT: v_readfirstlane_b32 s57, v29 +; SI-NEXT: v_readfirstlane_b32 s34, v28 +; SI-NEXT: v_readfirstlane_b32 s83, v27 +; SI-NEXT: v_readfirstlane_b32 s46, v26 +; SI-NEXT: v_readfirstlane_b32 s68, v25 +; SI-NEXT: v_readfirstlane_b32 s52, v24 +; SI-NEXT: v_readfirstlane_b32 s81, v23 ; SI-NEXT: v_readfirstlane_b32 s65, v22 ; SI-NEXT: v_readfirstlane_b32 s86, v21 -; SI-NEXT: v_readfirstlane_b32 s66, v20 +; SI-NEXT: v_readfirstlane_b32 s84, v20 ; SI-NEXT: v_readfirstlane_b32 s87, v19 ; SI-NEXT: v_readfirstlane_b32 s80, v18 ; SI-NEXT: v_readfirstlane_b32 s36, v17 -; SI-NEXT: v_readfirstlane_b32 s31, v16 +; SI-NEXT: v_readfirstlane_b32 s97, v16 ; SI-NEXT: v_readfirstlane_b32 s64, v15 ; SI-NEXT: v_readfirstlane_b32 s38, v14 ; SI-NEXT: v_readfirstlane_b32 s67, v13 -; SI-NEXT: v_readfirstlane_b32 s34, v12 -; SI-NEXT: v_readfirstlane_b32 s71, v11 -; SI-NEXT: v_readfirstlane_b32 s81, v10 +; SI-NEXT: v_readfirstlane_b32 s48, v12 +; SI-NEXT: v_readfirstlane_b32 s70, v11 +; SI-NEXT: v_readfirstlane_b32 s71, v10 ; SI-NEXT: v_readfirstlane_b32 s37, v9 -; SI-NEXT: v_readfirstlane_b32 s35, v8 -; SI-NEXT: v_readfirstlane_b32 s49, v7 +; SI-NEXT: v_readfirstlane_b32 s28, v8 +; SI-NEXT: v_readfirstlane_b32 s93, v7 ; SI-NEXT: v_readfirstlane_b32 s94, v6 -; SI-NEXT: v_readfirstlane_b32 s51, v5 -; SI-NEXT: v_readfirstlane_b32 s88, v4 -; SI-NEXT: v_readfirstlane_b32 s53, v3 -; SI-NEXT: v_readfirstlane_b32 s54, v2 -; SI-NEXT: v_readfirstlane_b32 s89, v1 -; SI-NEXT: v_readfirstlane_b32 s90, v0 +; SI-NEXT: v_readfirstlane_b32 s49, v5 +; SI-NEXT: v_readfirstlane_b32 s95, v4 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s91, v31 ; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_readfirstlane_b32 s16, v32 +; SI-NEXT: v_readfirstlane_b32 s89, v32 ; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_readfirstlane_b32 s93, v33 +; SI-NEXT: v_readfirstlane_b32 s79, v33 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:36 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:32 @@ -68765,245 +68766,248 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:16 ; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:12 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s52, v34 +; SI-NEXT: v_readfirstlane_b32 s39, v34 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s55, v35 +; SI-NEXT: v_readfirstlane_b32 s66, v35 ; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_readfirstlane_b32 s79, v37 +; SI-NEXT: v_readfirstlane_b32 s96, v37 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:76 -; SI-NEXT: v_readfirstlane_b32 s50, v36 +; SI-NEXT: v_readfirstlane_b32 s55, v36 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s21, v38 +; SI-NEXT: v_readfirstlane_b32 s47, v38 +; SI-NEXT: v_readfirstlane_b32 s53, v3 +; SI-NEXT: v_readfirstlane_b32 s92, v2 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s54, v0 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s56, v31 +; SI-NEXT: v_readfirstlane_b32 s59, v31 ; SI-NEXT: s_waitcnt vmcnt(10) ; SI-NEXT: v_readfirstlane_b32 s85, v32 ; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_readfirstlane_b32 s58, v33 +; SI-NEXT: v_readfirstlane_b32 s21, v33 ; SI-NEXT: s_waitcnt vmcnt(8) ; SI-NEXT: v_readfirstlane_b32 s98, v39 ; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_readfirstlane_b32 s46, v48 +; SI-NEXT: v_readfirstlane_b32 s26, v48 ; SI-NEXT: s_waitcnt vmcnt(6) ; SI-NEXT: v_readfirstlane_b32 s99, v49 ; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_readfirstlane_b32 s97, v50 +; SI-NEXT: v_readfirstlane_b32 s24, v50 ; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_readfirstlane_b32 s9, v51 -; SI-NEXT: v_writelane_b32 v41, s58, 3 -; SI-NEXT: v_writelane_b32 v41, s9, 4 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v37 +; SI-NEXT: v_readfirstlane_b32 s23, v51 +; SI-NEXT: v_writelane_b32 v41, s21, 6 ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_readfirstlane_b32 s78, v34 +; SI-NEXT: v_readfirstlane_b32 s22, v34 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v37 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_readfirstlane_b32 s69, v35 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_readfirstlane_b32 s30, v36 +; SI-NEXT: v_readfirstlane_b32 s25, v36 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: s_cbranch_scc0 .LBB99_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_and_b32 s4, s92, 0xff +; SI-NEXT: s_and_b32 s4, s16, 0xff ; SI-NEXT: s_lshl_b32 s5, s17, 8 ; SI-NEXT: s_or_b32 s12, s4, s5 ; SI-NEXT: s_and_b32 s4, s18, 0xff ; SI-NEXT: s_lshl_b32 s4, s4, 16 ; SI-NEXT: s_lshl_b32 s5, s19, 24 ; SI-NEXT: s_or_b32 s4, s5, s4 -; SI-NEXT: s_and_b32 s5, s24, 0xff -; SI-NEXT: s_lshl_b32 s6, s25, 8 +; SI-NEXT: s_and_b32 s5, s29, 0xff +; SI-NEXT: s_lshl_b32 s6, s30, 8 ; SI-NEXT: s_or_b32 s13, s5, s6 -; SI-NEXT: s_and_b32 s5, s26, 0xff +; SI-NEXT: v_readlane_b32 s5, v41, 1 +; SI-NEXT: s_and_b32 s5, s5, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s6, s27, 24 ; SI-NEXT: s_or_b32 s6, s6, s5 -; SI-NEXT: s_and_b32 s5, s54, 0xff +; SI-NEXT: s_and_b32 s5, s92, 0xff ; SI-NEXT: s_lshl_b32 s7, s53, 8 ; SI-NEXT: s_or_b32 s14, s5, s7 -; SI-NEXT: s_and_b32 s5, s88, 0xff +; SI-NEXT: s_and_b32 s5, s95, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: s_lshl_b32 s7, s51, 24 +; SI-NEXT: s_lshl_b32 s7, s49, 24 ; SI-NEXT: s_or_b32 s8, s7, s5 -; SI-NEXT: s_and_b32 s5, s81, 0xff -; SI-NEXT: s_lshl_b32 s7, s71, 8 +; SI-NEXT: s_and_b32 s5, s71, 0xff +; SI-NEXT: s_lshl_b32 s7, s70, 8 ; SI-NEXT: s_or_b32 s15, s5, s7 -; SI-NEXT: s_and_b32 s5, s34, 0xff +; SI-NEXT: s_and_b32 s5, s48, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s7, s67, 24 ; SI-NEXT: s_or_b32 s10, s7, s5 ; SI-NEXT: s_and_b32 s5, s80, 0xff ; SI-NEXT: s_lshl_b32 s7, s87, 8 ; SI-NEXT: s_or_b32 s40, s5, s7 -; SI-NEXT: s_and_b32 s5, s66, 0xff +; SI-NEXT: s_and_b32 s5, s84, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s7, s86, 24 ; SI-NEXT: s_or_b32 s60, s7, s5 -; SI-NEXT: s_and_b32 s5, s96, 0xff -; SI-NEXT: s_lshl_b32 s7, s44, 8 +; SI-NEXT: s_and_b32 s5, s46, 0xff +; SI-NEXT: s_lshl_b32 s7, s83, 8 ; SI-NEXT: s_or_b32 s41, s5, s7 -; SI-NEXT: s_and_b32 s5, s9, 0xff -; SI-NEXT: s_lshl_b32 s7, s97, 8 +; SI-NEXT: s_and_b32 s5, s23, 0xff +; SI-NEXT: s_lshl_b32 s7, s24, 8 ; SI-NEXT: s_or_b32 s42, s5, s7 -; SI-NEXT: s_and_b32 s5, s21, 0xff -; SI-NEXT: s_lshl_b32 s7, s79, 8 +; SI-NEXT: s_and_b32 s5, s47, 0xff +; SI-NEXT: s_lshl_b32 s7, s96, 8 ; SI-NEXT: s_or_b32 s43, s5, s7 -; SI-NEXT: v_readlane_b32 s7, v41, 1 -; SI-NEXT: s_and_b32 s5, s20, 0xff +; SI-NEXT: v_readlane_b32 s5, v41, 5 +; SI-NEXT: v_readlane_b32 s7, v41, 4 +; SI-NEXT: s_and_b32 s5, s5, 0xff ; SI-NEXT: s_lshl_b32 s7, s7, 8 ; SI-NEXT: s_or_b32 s5, s5, s7 -; SI-NEXT: s_and_b32 s7, s22, 0xff -; SI-NEXT: v_readlane_b32 s9, v41, 0 +; SI-NEXT: v_readlane_b32 s7, v41, 3 +; SI-NEXT: s_and_b32 s7, s7, 0xff +; SI-NEXT: v_readlane_b32 s9, v41, 2 ; SI-NEXT: s_lshl_b32 s7, s7, 16 ; SI-NEXT: s_lshl_b32 s9, s9, 24 -; SI-NEXT: s_or_b32 s57, s9, s7 -; SI-NEXT: s_and_b32 s7, s28, 0xff -; SI-NEXT: s_lshl_b32 s9, s29, 8 +; SI-NEXT: v_writelane_b32 v41, s46, 9 +; SI-NEXT: s_mov_b32 s56, s30 +; SI-NEXT: s_or_b32 s30, s9, s7 +; SI-NEXT: v_readlane_b32 s7, v41, 0 +; SI-NEXT: s_and_b32 s7, s7, 0xff +; SI-NEXT: s_lshl_b32 s9, s88, 8 ; SI-NEXT: s_or_b32 s7, s7, s9 -; SI-NEXT: s_and_b32 s9, s90, 0xff +; SI-NEXT: s_and_b32 s9, s54, 0xff ; SI-NEXT: s_lshl_b32 s9, s9, 16 -; SI-NEXT: s_lshl_b32 s11, s89, 24 -; SI-NEXT: s_or_b32 s77, s11, s9 +; SI-NEXT: s_lshl_b32 s11, s20, 24 +; SI-NEXT: s_or_b32 s90, s11, s9 ; SI-NEXT: s_and_b32 s9, s94, 0xff -; SI-NEXT: s_lshl_b32 s11, s49, 8 +; SI-NEXT: s_lshl_b32 s11, s93, 8 ; SI-NEXT: s_or_b32 s9, s9, s11 -; SI-NEXT: s_and_b32 s11, s35, 0xff +; SI-NEXT: s_and_b32 s11, s28, 0xff ; SI-NEXT: s_lshl_b32 s11, s11, 16 -; SI-NEXT: v_writelane_b32 v41, s44, 11 ; SI-NEXT: s_lshl_b32 s44, s37, 24 ; SI-NEXT: s_or_b32 vcc_lo, s44, s11 ; SI-NEXT: s_and_b32 s11, s38, 0xff ; SI-NEXT: s_lshl_b32 s44, s64, 8 ; SI-NEXT: s_or_b32 s11, s11, s44 -; SI-NEXT: s_and_b32 s44, s31, 0xff +; SI-NEXT: s_and_b32 s44, s97, 0xff ; SI-NEXT: s_lshl_b32 s44, s44, 16 ; SI-NEXT: s_lshl_b32 s45, s36, 24 +; SI-NEXT: v_writelane_b32 v41, s23, 10 ; SI-NEXT: s_or_b32 vcc_hi, s45, s44 ; SI-NEXT: s_and_b32 s44, s65, 0xff -; SI-NEXT: s_lshl_b32 s45, s84, 8 +; SI-NEXT: s_lshl_b32 s45, s81, 8 ; SI-NEXT: s_or_b32 s44, s44, s45 -; SI-NEXT: s_and_b32 s45, s68, 0xff +; SI-NEXT: s_and_b32 s45, s52, 0xff +; SI-NEXT: v_writelane_b32 v41, s92, 11 ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_mov_b32 s23, s21 -; SI-NEXT: s_mov_b32 s21, s46 -; SI-NEXT: s_lshl_b32 s46, s70, 24 +; SI-NEXT: s_lshl_b32 s46, s68, 24 +; SI-NEXT: v_writelane_b32 v41, s93, 12 ; SI-NEXT: s_and_b32 s44, s44, 0xffff -; SI-NEXT: v_writelane_b32 v41, s97, 12 -; SI-NEXT: s_mov_b32 s97, s86 -; SI-NEXT: s_mov_b32 s86, s84 -; SI-NEXT: s_mov_b32 s84, s70 -; SI-NEXT: s_mov_b32 s70, s34 -; SI-NEXT: s_mov_b32 s34, s88 -; SI-NEXT: s_mov_b32 s88, s24 -; SI-NEXT: s_or_b32 s24, s46, s45 -; SI-NEXT: s_or_b32 s61, s44, s24 +; SI-NEXT: v_writelane_b32 v41, s20, 13 +; SI-NEXT: s_or_b32 s20, s46, s45 +; SI-NEXT: s_or_b32 s61, s44, s20 ; SI-NEXT: s_and_b32 s44, s82, 0xff -; SI-NEXT: s_lshl_b32 s45, s30, 8 +; SI-NEXT: s_lshl_b32 s45, s25, 8 ; SI-NEXT: s_or_b32 s44, s44, s45 ; SI-NEXT: s_and_b32 s45, s69, 0xff ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s78, 24 -; SI-NEXT: s_mov_b32 s95, s90 -; SI-NEXT: s_mov_b32 s90, s18 +; SI-NEXT: s_lshl_b32 s46, s22, 24 +; SI-NEXT: v_writelane_b32 v41, s96, 14 +; SI-NEXT: s_mov_b32 s96, s84 +; SI-NEXT: s_mov_b32 s84, s67 +; SI-NEXT: s_mov_b32 s67, s49 +; SI-NEXT: s_mov_b32 s49, s18 ; SI-NEXT: s_or_b32 s18, s46, s45 -; SI-NEXT: s_and_b32 s45, s83, 0xff +; SI-NEXT: s_and_b32 s45, s34, 0xff ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s47, 24 +; SI-NEXT: s_lshl_b32 s46, s57, 24 ; SI-NEXT: s_and_b32 s44, s44, 0xffff ; SI-NEXT: s_or_b32 s62, s46, s45 ; SI-NEXT: s_or_b32 s63, s44, s18 ; SI-NEXT: s_and_b32 s44, s98, 0xff -; SI-NEXT: s_lshl_b32 s45, s58, 8 +; SI-NEXT: s_lshl_b32 s45, s21, 8 ; SI-NEXT: s_or_b32 s44, s44, s45 ; SI-NEXT: s_and_b32 s45, s85, 0xff ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s56, 24 -; SI-NEXT: s_mov_b32 s76, s56 -; SI-NEXT: s_mov_b32 s56, s85 -; SI-NEXT: s_mov_b32 s85, s79 -; SI-NEXT: s_mov_b32 s79, s19 +; SI-NEXT: s_lshl_b32 s46, s59, 24 +; SI-NEXT: s_mov_b32 s23, s88 +; SI-NEXT: s_mov_b32 s88, s19 ; SI-NEXT: s_or_b32 s19, s46, s45 ; SI-NEXT: s_and_b32 s45, s99, 0xff ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s21, 24 +; SI-NEXT: s_lshl_b32 s46, s26, 24 ; SI-NEXT: s_and_b32 s44, s44, 0xffff ; SI-NEXT: s_or_b32 s72, s46, s45 ; SI-NEXT: s_or_b32 s73, s44, s19 -; SI-NEXT: s_and_b32 s44, s52, 0xff -; SI-NEXT: s_lshl_b32 s45, s93, 8 +; SI-NEXT: s_and_b32 s44, s39, 0xff +; SI-NEXT: s_lshl_b32 s45, s79, 8 ; SI-NEXT: s_or_b32 s44, s44, s45 -; SI-NEXT: s_and_b32 s45, s16, 0xff -; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s91, 24 +; SI-NEXT: s_and_b32 s45, s89, 0xff ; SI-NEXT: s_and_b32 s5, s5, 0xffff -; SI-NEXT: s_mov_b32 s47, s96 -; SI-NEXT: s_mov_b32 s96, s78 -; SI-NEXT: s_mov_b32 s78, s69 -; SI-NEXT: s_mov_b32 s69, s68 -; SI-NEXT: s_mov_b32 s68, s38 -; SI-NEXT: s_mov_b32 s38, s35 -; SI-NEXT: s_mov_b32 s35, s89 -; SI-NEXT: s_or_b32 s89, s46, s45 -; SI-NEXT: s_and_b32 s45, s50, 0xff -; SI-NEXT: s_or_b32 s5, s5, s57 ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s55, 24 +; SI-NEXT: s_lshl_b32 s46, s91, 24 +; SI-NEXT: s_or_b32 s5, s5, s30 +; SI-NEXT: s_mov_b32 s77, s47 +; SI-NEXT: s_mov_b32 s47, s24 +; SI-NEXT: s_mov_b32 s24, s83 +; SI-NEXT: s_mov_b32 s83, s70 +; SI-NEXT: s_mov_b32 s70, s38 +; SI-NEXT: s_mov_b32 s38, s91 +; SI-NEXT: s_mov_b32 s91, s23 +; SI-NEXT: s_mov_b32 s23, s17 +; SI-NEXT: s_or_b32 s17, s46, s45 +; SI-NEXT: s_and_b32 s45, s55, 0xff ; SI-NEXT: s_and_b32 s12, s12, 0xffff +; SI-NEXT: s_and_b32 s7, s7, 0xffff ; SI-NEXT: s_and_b32 s9, s9, 0xffff -; SI-NEXT: s_or_b32 s74, s46, s45 -; SI-NEXT: s_mov_b32 s45, s83 -; SI-NEXT: s_mov_b32 s83, s91 -; SI-NEXT: s_mov_b32 s91, s28 +; SI-NEXT: s_and_b32 s11, s11, 0xffff +; SI-NEXT: s_mov_b32 s76, s59 +; SI-NEXT: s_mov_b32 s59, s57 +; SI-NEXT: s_mov_b32 s57, s34 +; SI-NEXT: s_mov_b32 s34, s82 +; SI-NEXT: s_mov_b32 s82, s52 +; SI-NEXT: s_mov_b32 s52, s95 +; SI-NEXT: s_mov_b32 s95, s27 +; SI-NEXT: s_mov_b32 s21, s22 +; SI-NEXT: s_mov_b32 s22, s69 +; SI-NEXT: s_mov_b32 s69, s48 +; SI-NEXT: s_mov_b32 s48, s37 +; SI-NEXT: s_mov_b32 s37, s56 +; SI-NEXT: s_lshl_b32 s45, s45, 16 +; SI-NEXT: s_lshl_b32 s46, s66, 24 +; SI-NEXT: s_and_b32 s44, s44, 0xffff +; SI-NEXT: s_mov_b32 s56, s98 +; SI-NEXT: s_mov_b32 s98, s28 ; SI-NEXT: s_and_b32 s28, s42, 0xffff -; SI-NEXT: s_mov_b32 s59, s94 -; SI-NEXT: s_mov_b32 s94, s27 ; SI-NEXT: s_and_b32 s27, s43, 0xffff ; SI-NEXT: s_or_b32 s42, s12, s4 ; SI-NEXT: s_mov_b32 s43, s5 ; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16 +; SI-NEXT: s_or_b32 s7, s7, s90 ; SI-NEXT: s_or_b32 s9, s9, vcc_lo -; SI-NEXT: v_writelane_b32 v41, s4, 5 -; SI-NEXT: s_and_b32 s11, s11, 0xffff -; SI-NEXT: v_writelane_b32 v41, s5, 6 -; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 16 ; SI-NEXT: s_or_b32 s11, s11, vcc_hi -; SI-NEXT: v_writelane_b32 v41, s4, 7 -; SI-NEXT: s_and_b32 s7, s7, 0xffff -; SI-NEXT: s_and_b32 s44, s44, 0xffff -; SI-NEXT: v_writelane_b32 v41, s5, 8 -; SI-NEXT: s_lshr_b64 s[4:5], s[10:11], 16 -; SI-NEXT: s_or_b32 s7, s7, s77 -; SI-NEXT: s_or_b32 s75, s44, s89 +; SI-NEXT: s_or_b32 s74, s46, s45 +; SI-NEXT: s_or_b32 s75, s44, s17 ; SI-NEXT: s_and_b32 s13, s13, 0xffff ; SI-NEXT: s_and_b32 s14, s14, 0xffff ; SI-NEXT: s_and_b32 s58, s15, 0xffff -; SI-NEXT: s_mov_b32 s44, s82 -; SI-NEXT: s_mov_b32 s82, s81 -; SI-NEXT: s_mov_b32 s81, s55 -; SI-NEXT: s_mov_b32 s55, s54 -; SI-NEXT: s_mov_b32 s54, s51 -; SI-NEXT: s_mov_b32 s51, s37 -; SI-NEXT: s_mov_b32 s37, s16 +; SI-NEXT: s_mov_b32 s92, s16 ; SI-NEXT: s_and_b32 s16, s40, 0xffff -; SI-NEXT: s_mov_b32 s46, s98 -; SI-NEXT: s_mov_b32 s98, s93 -; SI-NEXT: s_and_b32 s93, s41, 0xffff -; SI-NEXT: v_writelane_b32 v41, s4, 9 -; SI-NEXT: s_mov_b32 s39, s49 +; SI-NEXT: s_mov_b32 s31, s29 +; SI-NEXT: s_and_b32 s29, s41, 0xffff +; SI-NEXT: v_writelane_b32 v41, s4, 7 +; SI-NEXT: s_mov_b32 s93, s39 +; SI-NEXT: s_mov_b32 s39, s79 +; SI-NEXT: v_writelane_b32 v41, s5, 8 ; SI-NEXT: s_or_b32 s40, s13, s6 ; SI-NEXT: s_mov_b32 s41, s7 -; SI-NEXT: s_lshr_b64 s[48:49], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[6:7], 16 ; SI-NEXT: s_or_b32 s14, s14, s8 ; SI-NEXT: s_mov_b32 s15, s9 +; SI-NEXT: s_lshr_b64 s[50:51], s[8:9], 16 ; SI-NEXT: s_or_b32 s12, s58, s10 ; SI-NEXT: s_mov_b32 s13, s11 -; SI-NEXT: v_writelane_b32 v41, s5, 10 +; SI-NEXT: s_lshr_b64 s[44:45], s[10:11], 16 ; SI-NEXT: s_or_b32 s10, s16, s60 ; SI-NEXT: s_mov_b32 s11, s61 ; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16 -; SI-NEXT: s_or_b32 s8, s93, s62 +; SI-NEXT: s_or_b32 s8, s29, s62 ; SI-NEXT: s_mov_b32 s9, s63 ; SI-NEXT: s_lshr_b64 s[62:63], s[62:63], 16 ; SI-NEXT: s_or_b32 s6, s28, s72 @@ -69012,68 +69016,68 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_or_b32 s4, s27, s74 ; SI-NEXT: s_mov_b32 s5, s75 ; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16 -; SI-NEXT: s_mov_b32 s16, s37 -; SI-NEXT: s_mov_b32 s37, s51 -; SI-NEXT: s_mov_b32 s51, s54 -; SI-NEXT: s_mov_b32 s54, s55 -; SI-NEXT: s_mov_b32 s55, s81 -; SI-NEXT: s_mov_b32 s81, s82 -; SI-NEXT: s_mov_b32 s82, s44 -; SI-NEXT: v_readlane_b32 s44, v41, 11 -; SI-NEXT: s_mov_b32 s93, s98 -; SI-NEXT: s_mov_b32 s98, s46 -; SI-NEXT: s_mov_b32 s46, s21 -; SI-NEXT: s_mov_b32 s21, s23 -; SI-NEXT: s_mov_b32 s28, s91 -; SI-NEXT: s_mov_b32 s91, s83 -; SI-NEXT: s_mov_b32 s83, s45 -; SI-NEXT: s_mov_b32 s27, s94 -; SI-NEXT: s_mov_b32 s94, s59 -; SI-NEXT: s_lshr_b32 s23, s57, 16 -; SI-NEXT: s_lshr_b32 s57, s77, 16 -; SI-NEXT: s_lshr_b32 s59, vcc_lo, 16 +; SI-NEXT: s_mov_b32 s16, s92 +; SI-NEXT: s_mov_b32 s79, s39 +; SI-NEXT: s_mov_b32 s39, s93 +; SI-NEXT: s_mov_b32 s29, s31 +; SI-NEXT: s_mov_b32 s28, s98 +; SI-NEXT: s_mov_b32 s98, s56 +; SI-NEXT: s_lshr_b32 s35, s30, 16 +; SI-NEXT: v_readlane_b32 s46, v41, 9 +; SI-NEXT: s_lshr_b32 s56, s90, 16 +; SI-NEXT: s_lshr_b32 s58, vcc_lo, 16 ; SI-NEXT: s_lshr_b32 s61, vcc_hi, 16 -; SI-NEXT: s_lshr_b32 s63, s24, 16 -; SI-NEXT: s_mov_b32 s24, s88 -; SI-NEXT: s_mov_b32 s88, s34 -; SI-NEXT: s_mov_b32 s34, s70 -; SI-NEXT: s_mov_b32 s70, s84 -; SI-NEXT: s_mov_b32 s84, s86 -; SI-NEXT: s_mov_b32 s86, s97 -; SI-NEXT: v_readlane_b32 s97, v41, 12 +; SI-NEXT: s_lshr_b32 s63, s20, 16 +; SI-NEXT: v_readlane_b32 s20, v41, 13 +; SI-NEXT: v_readlane_b32 s93, v41, 12 +; SI-NEXT: v_readlane_b32 s92, v41, 11 ; SI-NEXT: s_lshr_b32 s73, s18, 16 -; SI-NEXT: s_mov_b32 s18, s90 -; SI-NEXT: s_mov_b32 s90, s95 -; SI-NEXT: s_mov_b32 s49, s39 +; SI-NEXT: s_mov_b32 s18, s49 +; SI-NEXT: s_mov_b32 s49, s67 +; SI-NEXT: s_mov_b32 s67, s84 +; SI-NEXT: s_mov_b32 s84, s96 +; SI-NEXT: v_readlane_b32 s96, v41, 14 ; SI-NEXT: s_lshr_b32 s75, s19, 16 -; SI-NEXT: s_mov_b32 s19, s79 -; SI-NEXT: s_mov_b32 s79, s85 -; SI-NEXT: s_mov_b32 s85, s56 -; SI-NEXT: s_mov_b32 s56, s76 -; SI-NEXT: s_lshr_b32 s45, s89, 16 -; SI-NEXT: s_mov_b32 s89, s35 -; SI-NEXT: s_mov_b32 s35, s38 -; SI-NEXT: s_mov_b32 s38, s68 -; SI-NEXT: s_mov_b32 s68, s69 -; SI-NEXT: s_mov_b32 s69, s78 -; SI-NEXT: s_mov_b32 s78, s96 -; SI-NEXT: s_mov_b32 s96, s47 +; SI-NEXT: s_mov_b32 s19, s88 +; SI-NEXT: s_lshr_b32 s45, s17, 16 +; SI-NEXT: s_mov_b32 s17, s23 +; SI-NEXT: v_readlane_b32 s23, v41, 10 +; SI-NEXT: s_mov_b32 s30, s37 +; SI-NEXT: s_mov_b32 s37, s48 +; SI-NEXT: s_mov_b32 s48, s69 +; SI-NEXT: s_mov_b32 s69, s22 +; SI-NEXT: s_mov_b32 s22, s21 +; SI-NEXT: s_mov_b32 s27, s95 +; SI-NEXT: s_mov_b32 s95, s52 +; SI-NEXT: s_mov_b32 s52, s82 +; SI-NEXT: s_mov_b32 s82, s34 +; SI-NEXT: s_mov_b32 s88, s91 +; SI-NEXT: s_mov_b32 s91, s38 +; SI-NEXT: s_mov_b32 s38, s70 +; SI-NEXT: s_mov_b32 s70, s83 +; SI-NEXT: s_mov_b32 s83, s24 +; SI-NEXT: s_mov_b32 s24, s47 +; SI-NEXT: s_mov_b32 s47, s77 +; SI-NEXT: s_mov_b32 s34, s57 +; SI-NEXT: s_mov_b32 s57, s59 +; SI-NEXT: s_mov_b32 s59, s76 ; SI-NEXT: s_mov_b64 s[76:77], 0 ; SI-NEXT: s_branch .LBB99_3 ; SI-NEXT: .LBB99_2: ; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: s_mov_b64 s[76:77], -1 -; SI-NEXT: v_writelane_b32 v41, s4, 5 -; SI-NEXT: v_writelane_b32 v41, s5, 6 -; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v41, s4, 7 ; SI-NEXT: ; implicit-def: $sgpr42 -; SI-NEXT: ; implicit-def: $sgpr23 +; SI-NEXT: v_writelane_b32 v41, s5, 8 +; SI-NEXT: ; implicit-def: $sgpr35 ; SI-NEXT: ; implicit-def: $sgpr40 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr57 +; SI-NEXT: ; implicit-def: $sgpr78 +; SI-NEXT: ; implicit-def: $sgpr56 ; SI-NEXT: ; implicit-def: $sgpr14 -; SI-NEXT: ; implicit-def: $sgpr59 +; SI-NEXT: ; implicit-def: $sgpr50 +; SI-NEXT: ; implicit-def: $sgpr58 ; SI-NEXT: ; implicit-def: $sgpr12 +; SI-NEXT: ; implicit-def: $sgpr44 ; SI-NEXT: ; implicit-def: $sgpr61 ; SI-NEXT: ; implicit-def: $sgpr10 ; SI-NEXT: ; implicit-def: $sgpr60 @@ -69084,39 +69088,31 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: ; implicit-def: $sgpr6 ; SI-NEXT: ; implicit-def: $sgpr72 ; SI-NEXT: ; implicit-def: $sgpr75 +; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: ; implicit-def: $sgpr74 ; SI-NEXT: ; implicit-def: $sgpr45 -; SI-NEXT: v_writelane_b32 v41, s4, 7 -; SI-NEXT: v_writelane_b32 v41, s5, 8 -; SI-NEXT: ; implicit-def: $sgpr4 -; SI-NEXT: v_writelane_b32 v41, s4, 9 -; SI-NEXT: v_writelane_b32 v41, s5, 10 -; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: .LBB99_3: ; %Flow ; SI-NEXT: s_andn2_b64 vcc, exec, s[76:77] -; SI-NEXT: v_readlane_b32 s76, v41, 5 -; SI-NEXT: v_readlane_b32 s77, v41, 6 -; SI-NEXT: s_mov_b32 s58, s76 ; SI-NEXT: v_readlane_b32 s76, v41, 7 ; SI-NEXT: v_readlane_b32 s77, v41, 8 ; SI-NEXT: s_cbranch_vccnz .LBB99_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s21, s47, 3 ; SI-NEXT: s_and_b32 s4, s21, 0xff -; SI-NEXT: s_lshl_b32 s5, s79, 8 -; SI-NEXT: s_add_i32 s50, s50, 3 +; SI-NEXT: s_lshl_b32 s5, s96, 8 +; SI-NEXT: s_add_i32 s50, s55, 3 ; SI-NEXT: s_or_b32 s4, s5, s4 ; SI-NEXT: s_and_b32 s6, s50, 0xff ; SI-NEXT: s_addk_i32 s4, 0x300 -; SI-NEXT: s_lshl_b32 s5, s55, 24 +; SI-NEXT: s_lshl_b32 s5, s66, 24 ; SI-NEXT: s_lshl_b32 s6, s6, 16 ; SI-NEXT: s_and_b32 s4, s4, 0xffff ; SI-NEXT: s_or_b32 s5, s5, s6 -; SI-NEXT: s_add_i32 s39, s52, 3 +; SI-NEXT: s_add_i32 s39, s39, 3 ; SI-NEXT: s_or_b32 s4, s5, s4 ; SI-NEXT: s_and_b32 s5, s39, 0xff -; SI-NEXT: s_lshl_b32 s6, s93, 8 -; SI-NEXT: s_add_i32 s79, s16, 3 +; SI-NEXT: s_lshl_b32 s6, s79, 8 +; SI-NEXT: s_add_i32 s79, s89, 3 ; SI-NEXT: s_or_b32 s5, s6, s5 ; SI-NEXT: s_and_b32 s7, s79, 0xff ; SI-NEXT: s_addk_i32 s5, 0x300 @@ -69124,21 +69120,20 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_lshl_b32 s7, s7, 16 ; SI-NEXT: s_and_b32 s5, s5, 0xffff ; SI-NEXT: s_or_b32 s6, s6, s7 +; SI-NEXT: s_add_i32 s23, s23, 3 ; SI-NEXT: s_or_b32 s5, s6, s5 -; SI-NEXT: v_readlane_b32 s6, v41, 4 -; SI-NEXT: s_add_i32 s23, s6, 3 ; SI-NEXT: s_and_b32 s6, s23, 0xff -; SI-NEXT: s_lshl_b32 s7, s97, 8 +; SI-NEXT: s_lshl_b32 s7, s24, 8 ; SI-NEXT: s_add_i32 s99, s99, 3 ; SI-NEXT: s_or_b32 s6, s7, s6 ; SI-NEXT: s_and_b32 s8, s99, 0xff ; SI-NEXT: s_addk_i32 s6, 0x300 -; SI-NEXT: s_lshl_b32 s7, s46, 24 +; SI-NEXT: s_lshl_b32 s7, s26, 24 ; SI-NEXT: s_lshl_b32 s8, s8, 16 ; SI-NEXT: s_and_b32 s6, s6, 0xffff ; SI-NEXT: s_or_b32 s7, s7, s8 ; SI-NEXT: s_add_i32 s98, s98, 3 -; SI-NEXT: v_readlane_b32 s8, v41, 3 +; SI-NEXT: v_readlane_b32 s8, v41, 6 ; SI-NEXT: s_or_b32 s6, s7, s6 ; SI-NEXT: s_and_b32 s7, s98, 0xff ; SI-NEXT: s_lshl_b32 s8, s8, 8 @@ -69146,32 +69141,31 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_or_b32 s7, s8, s7 ; SI-NEXT: s_and_b32 s9, s85, 0xff ; SI-NEXT: s_addk_i32 s7, 0x300 -; SI-NEXT: s_lshl_b32 s8, s56, 24 +; SI-NEXT: s_lshl_b32 s8, s59, 24 ; SI-NEXT: s_lshl_b32 s9, s9, 16 ; SI-NEXT: s_and_b32 s7, s7, 0xffff ; SI-NEXT: s_or_b32 s8, s8, s9 -; SI-NEXT: s_add_i32 s96, s96, 3 +; SI-NEXT: s_add_i32 s96, s46, 3 ; SI-NEXT: s_or_b32 s7, s8, s7 ; SI-NEXT: s_and_b32 s8, s96, 0xff -; SI-NEXT: s_lshl_b32 s9, s44, 8 -; SI-NEXT: s_add_i32 s83, s83, 3 +; SI-NEXT: s_lshl_b32 s9, s83, 8 +; SI-NEXT: s_add_i32 s83, s34, 3 ; SI-NEXT: s_or_b32 s8, s9, s8 -; SI-NEXT: v_readlane_b32 s9, v41, 2 ; SI-NEXT: s_and_b32 s10, s83, 0xff ; SI-NEXT: s_addk_i32 s8, 0x300 -; SI-NEXT: s_lshl_b32 s9, s9, 24 +; SI-NEXT: s_lshl_b32 s9, s57, 24 ; SI-NEXT: s_lshl_b32 s10, s10, 16 ; SI-NEXT: s_and_b32 s8, s8, 0xffff ; SI-NEXT: s_or_b32 s9, s9, s10 ; SI-NEXT: s_add_i32 s82, s82, 3 ; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_and_b32 s9, s82, 0xff -; SI-NEXT: s_lshl_b32 s10, s30, 8 +; SI-NEXT: s_lshl_b32 s10, s25, 8 ; SI-NEXT: s_add_i32 s69, s69, 3 ; SI-NEXT: s_or_b32 s9, s10, s9 ; SI-NEXT: s_and_b32 s11, s69, 0xff ; SI-NEXT: s_addk_i32 s9, 0x300 -; SI-NEXT: s_lshl_b32 s10, s78, 24 +; SI-NEXT: s_lshl_b32 s10, s22, 24 ; SI-NEXT: s_lshl_b32 s11, s11, 16 ; SI-NEXT: s_and_b32 s9, s9, 0xffff ; SI-NEXT: s_or_b32 s10, s10, s11 @@ -69179,7 +69173,7 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_or_b32 s9, s10, s9 ; SI-NEXT: s_and_b32 s10, s80, 0xff ; SI-NEXT: s_lshl_b32 s11, s87, 8 -; SI-NEXT: s_add_i32 s66, s66, 3 +; SI-NEXT: s_add_i32 s66, s84, 3 ; SI-NEXT: s_or_b32 s10, s11, s10 ; SI-NEXT: s_and_b32 s12, s66, 0xff ; SI-NEXT: s_addk_i32 s10, 0x300 @@ -69190,20 +69184,20 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_add_i32 s65, s65, 3 ; SI-NEXT: s_or_b32 s10, s11, s10 ; SI-NEXT: s_and_b32 s11, s65, 0xff -; SI-NEXT: s_lshl_b32 s12, s84, 8 -; SI-NEXT: s_add_i32 s52, s68, 3 +; SI-NEXT: s_lshl_b32 s12, s81, 8 +; SI-NEXT: s_add_i32 s52, s52, 3 ; SI-NEXT: s_or_b32 s11, s12, s11 ; SI-NEXT: s_and_b32 s13, s52, 0xff ; SI-NEXT: s_addk_i32 s11, 0x300 -; SI-NEXT: s_lshl_b32 s12, s70, 24 +; SI-NEXT: s_lshl_b32 s12, s68, 24 ; SI-NEXT: s_lshl_b32 s13, s13, 16 ; SI-NEXT: s_and_b32 s11, s11, 0xffff ; SI-NEXT: s_or_b32 s12, s12, s13 -; SI-NEXT: s_add_i32 s55, s81, 3 +; SI-NEXT: s_add_i32 s55, s71, 3 ; SI-NEXT: s_or_b32 s11, s12, s11 ; SI-NEXT: s_and_b32 s12, s55, 0xff -; SI-NEXT: s_lshl_b32 s13, s71, 8 -; SI-NEXT: s_add_i32 s48, s34, 3 +; SI-NEXT: s_lshl_b32 s13, s70, 8 +; SI-NEXT: s_add_i32 s48, s48, 3 ; SI-NEXT: s_or_b32 s12, s13, s12 ; SI-NEXT: s_and_b32 s14, s48, 0xff ; SI-NEXT: s_addk_i32 s12, 0x300 @@ -69215,7 +69209,7 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_or_b32 s12, s13, s12 ; SI-NEXT: s_and_b32 s13, s38, 0xff ; SI-NEXT: s_lshl_b32 s14, s64, 8 -; SI-NEXT: s_add_i32 s31, s31, 3 +; SI-NEXT: s_add_i32 s31, s97, 3 ; SI-NEXT: s_or_b32 s13, s14, s13 ; SI-NEXT: s_and_b32 s15, s31, 0xff ; SI-NEXT: s_addk_i32 s13, 0x300 @@ -69223,84 +69217,85 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_lshl_b32 s15, s15, 16 ; SI-NEXT: s_and_b32 s13, s13, 0xffff ; SI-NEXT: s_or_b32 s14, s14, s15 -; SI-NEXT: s_add_i32 s36, s54, 3 +; SI-NEXT: s_add_i32 s36, s92, 3 ; SI-NEXT: s_or_b32 s13, s14, s13 ; SI-NEXT: s_and_b32 s14, s36, 0xff ; SI-NEXT: s_lshl_b32 s15, s53, 8 -; SI-NEXT: s_add_i32 s95, s88, 3 +; SI-NEXT: s_add_i32 s95, s95, 3 ; SI-NEXT: s_or_b32 s14, s15, s14 ; SI-NEXT: s_and_b32 s21, s95, 0xff ; SI-NEXT: s_addk_i32 s14, 0x300 -; SI-NEXT: s_lshl_b32 s15, s51, 24 +; SI-NEXT: s_lshl_b32 s15, s49, 24 ; SI-NEXT: s_lshl_b32 s21, s21, 16 ; SI-NEXT: s_and_b32 s14, s14, 0xffff ; SI-NEXT: s_or_b32 s15, s15, s21 ; SI-NEXT: s_add_i32 s94, s94, 3 ; SI-NEXT: s_or_b32 s14, s15, s14 ; SI-NEXT: s_and_b32 s15, s94, 0xff -; SI-NEXT: s_lshl_b32 s21, s49, 8 -; SI-NEXT: s_add_i32 s91, s35, 3 +; SI-NEXT: s_lshl_b32 s21, s93, 8 +; SI-NEXT: s_add_i32 s91, s28, 3 ; SI-NEXT: s_or_b32 s15, s21, s15 -; SI-NEXT: s_and_b32 s16, s91, 0xff +; SI-NEXT: s_and_b32 s22, s91, 0xff ; SI-NEXT: s_addk_i32 s15, 0x300 ; SI-NEXT: s_lshl_b32 s21, s37, 24 -; SI-NEXT: s_lshl_b32 s16, s16, 16 +; SI-NEXT: s_lshl_b32 s22, s22, 16 ; SI-NEXT: s_and_b32 s15, s15, 0xffff -; SI-NEXT: s_or_b32 s21, s21, s16 -; SI-NEXT: s_add_i32 s24, s24, 3 +; SI-NEXT: s_or_b32 s21, s21, s22 +; SI-NEXT: s_add_i32 s24, s29, 3 +; SI-NEXT: v_readlane_b32 s23, v41, 1 +; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_or_b32 s15, s21, s15 ; SI-NEXT: s_and_b32 s21, s24, 0xff -; SI-NEXT: s_lshl_b32 s16, s25, 8 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_or_b32 s21, s16, s21 -; SI-NEXT: s_and_b32 s23, s26, 0xff -; SI-NEXT: s_addk_i32 s21, 0x300 -; SI-NEXT: s_lshl_b32 s16, s27, 24 -; SI-NEXT: s_lshl_b32 s23, s23, 16 -; SI-NEXT: s_and_b32 s21, s21, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s23 -; SI-NEXT: s_or_b32 s21, s16, s21 -; SI-NEXT: s_add_i32 s28, s28, 3 -; SI-NEXT: s_add_i32 s40, s21, 0x3000000 -; SI-NEXT: s_and_b32 s21, s28, 0xff -; SI-NEXT: s_lshl_b32 s16, s29, 8 -; SI-NEXT: s_lshl_b32 s23, s89, 24 -; SI-NEXT: s_add_i32 s89, s90, 3 -; SI-NEXT: s_or_b32 s21, s16, s21 -; SI-NEXT: s_and_b32 s16, s89, 0xff -; SI-NEXT: s_addk_i32 s21, 0x300 -; SI-NEXT: s_lshl_b32 s16, s16, 16 -; SI-NEXT: s_and_b32 s21, s21, 0xffff -; SI-NEXT: s_or_b32 s16, s23, s16 -; SI-NEXT: s_or_b32 s16, s16, s21 -; SI-NEXT: s_add_i32 s41, s16, 0x3000000 -; SI-NEXT: s_add_i32 s16, s92, 3 +; SI-NEXT: s_lshl_b32 s22, s30, 8 +; SI-NEXT: s_add_i32 s26, s23, 3 ; SI-NEXT: s_and_b32 s16, s16, 0xff ; SI-NEXT: s_lshl_b32 s17, s17, 8 ; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_or_b32 s21, s22, s21 +; SI-NEXT: s_and_b32 s23, s26, 0xff ; SI-NEXT: s_or_b32 s16, s17, s16 ; SI-NEXT: s_and_b32 s18, s18, 0xff +; SI-NEXT: s_addk_i32 s21, 0x300 +; SI-NEXT: s_lshl_b32 s22, s27, 24 +; SI-NEXT: s_lshl_b32 s23, s23, 16 ; SI-NEXT: s_addk_i32 s16, 0x300 ; SI-NEXT: s_lshl_b32 s17, s19, 24 ; SI-NEXT: s_lshl_b32 s18, s18, 16 +; SI-NEXT: s_and_b32 s21, s21, 0xffff +; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: s_and_b32 s16, s16, 0xffff ; SI-NEXT: s_or_b32 s17, s17, s18 +; SI-NEXT: s_or_b32 s21, s22, s21 ; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_add_i32 s40, s21, 0x3000000 +; SI-NEXT: v_readlane_b32 s21, v41, 0 ; SI-NEXT: s_add_i32 s42, s16, 0x3000000 -; SI-NEXT: s_add_i32 s16, s20, 3 -; SI-NEXT: v_readlane_b32 s17, v41, 1 +; SI-NEXT: v_readlane_b32 s16, v41, 5 +; SI-NEXT: s_add_i32 s28, s21, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 +; SI-NEXT: v_readlane_b32 s17, v41, 4 +; SI-NEXT: v_readlane_b32 s18, v41, 3 +; SI-NEXT: s_and_b32 s21, s28, 0xff +; SI-NEXT: s_lshl_b32 s22, s88, 8 +; SI-NEXT: s_add_i32 s89, s54, 3 ; SI-NEXT: s_and_b32 s16, s16, 0xff ; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_add_i32 s18, s22, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_or_b32 s21, s22, s21 +; SI-NEXT: s_and_b32 s22, s89, 0xff ; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_readlane_b32 s17, v41, 0 +; SI-NEXT: v_readlane_b32 s17, v41, 2 ; SI-NEXT: s_and_b32 s18, s18, 0xff +; SI-NEXT: s_addk_i32 s21, 0x300 +; SI-NEXT: s_lshl_b32 s20, s20, 24 +; SI-NEXT: s_lshl_b32 s22, s22, 16 ; SI-NEXT: s_addk_i32 s16, 0x300 ; SI-NEXT: s_lshl_b32 s17, s17, 24 ; SI-NEXT: s_lshl_b32 s18, s18, 16 +; SI-NEXT: s_and_b32 s21, s21, 0xffff +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: s_and_b32 s16, s16, 0xffff ; SI-NEXT: s_or_b32 s17, s17, s18 -; SI-NEXT: s_or_b32 s16, s17, s16 ; SI-NEXT: s_add_i32 s4, s4, 0x3000000 ; SI-NEXT: s_add_i32 s5, s5, 0x3000000 ; SI-NEXT: s_add_i32 s6, s6, 0x3000000 @@ -69311,49 +69306,49 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_add_i32 s11, s11, 0x3000000 ; SI-NEXT: s_add_i32 s12, s12, 0x3000000 ; SI-NEXT: s_add_i32 s13, s13, 0x3000000 -; SI-NEXT: s_add_i32 s43, s16, 0x3000000 +; SI-NEXT: s_or_b32 s20, s20, s21 +; SI-NEXT: s_or_b32 s16, s17, s16 ; SI-NEXT: s_add_i32 s14, s14, 0x3000000 ; SI-NEXT: s_add_i32 s15, s15, 0x3000000 -; SI-NEXT: s_lshr_b64 s[58:59], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 16 +; SI-NEXT: s_add_i32 s41, s20, 0x3000000 +; SI-NEXT: s_add_i32 s43, s16, 0x3000000 +; SI-NEXT: s_lshr_b64 s[44:45], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[72:73], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[48:49], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[14:15], 16 -; SI-NEXT: v_writelane_b32 v41, s16, 9 -; SI-NEXT: s_lshr_b32 s23, s43, 16 -; SI-NEXT: s_lshr_b32 s57, s41, 16 -; SI-NEXT: s_lshr_b32 s59, s15, 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[50:51], s[14:15], 16 +; SI-NEXT: s_lshr_b32 s35, s43, 16 +; SI-NEXT: s_lshr_b32 s56, s41, 16 +; SI-NEXT: s_lshr_b32 s58, s15, 16 ; SI-NEXT: s_lshr_b32 s61, s13, 16 ; SI-NEXT: s_lshr_b32 s63, s11, 16 ; SI-NEXT: s_lshr_b32 s73, s9, 16 ; SI-NEXT: s_lshr_b32 s75, s7, 16 ; SI-NEXT: s_lshr_b32 s45, s5, 16 -; SI-NEXT: v_writelane_b32 v41, s17, 10 ; SI-NEXT: .LBB99_5: ; %end ; SI-NEXT: s_and_b32 s16, s42, 0xffff -; SI-NEXT: s_lshl_b32 s17, s58, 16 +; SI-NEXT: s_lshl_b32 s17, s76, 16 ; SI-NEXT: s_or_b32 s16, s16, s17 ; SI-NEXT: s_and_b32 s17, s43, 0xffff -; SI-NEXT: s_lshl_b32 s18, s23, 16 +; SI-NEXT: s_lshl_b32 s18, s35, 16 ; SI-NEXT: s_or_b32 s17, s17, s18 ; SI-NEXT: s_and_b32 s18, s40, 0xffff -; SI-NEXT: s_lshl_b32 s19, s48, 16 +; SI-NEXT: s_lshl_b32 s19, s78, 16 ; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: s_and_b32 s19, s41, 0xffff -; SI-NEXT: s_lshl_b32 s20, s57, 16 +; SI-NEXT: s_lshl_b32 s20, s56, 16 ; SI-NEXT: s_or_b32 s19, s19, s20 ; SI-NEXT: s_and_b32 s14, s14, 0xffff -; SI-NEXT: s_lshl_b32 s20, s76, 16 +; SI-NEXT: s_lshl_b32 s20, s50, 16 ; SI-NEXT: s_or_b32 s14, s14, s20 ; SI-NEXT: s_and_b32 s15, s15, 0xffff -; SI-NEXT: s_lshl_b32 s20, s59, 16 +; SI-NEXT: s_lshl_b32 s20, s58, 16 ; SI-NEXT: s_or_b32 s15, s15, s20 -; SI-NEXT: v_readlane_b32 s20, v41, 9 ; SI-NEXT: s_and_b32 s12, s12, 0xffff -; SI-NEXT: s_lshl_b32 s20, s20, 16 +; SI-NEXT: s_lshl_b32 s20, s44, 16 ; SI-NEXT: s_or_b32 s12, s12, s20 ; SI-NEXT: s_and_b32 s13, s13, 0xffff ; SI-NEXT: s_lshl_b32 s20, s61, 16 @@ -69382,7 +69377,6 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_and_b32 s5, s5, 0xffff ; SI-NEXT: s_lshl_b32 s20, s45, 16 ; SI-NEXT: s_or_b32 s5, s5, s20 -; SI-NEXT: v_readlane_b32 s21, v41, 10 ; SI-NEXT: v_mov_b32_e32 v0, s16 ; SI-NEXT: v_mov_b32_e32 v1, s17 ; SI-NEXT: v_mov_b32_e32 v2, s18 @@ -81308,7 +81302,6 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: v_writelane_b32 v40, s53, 13 ; SI-NEXT: v_writelane_b32 v40, s54, 14 ; SI-NEXT: v_writelane_b32 v40, s55, 15 -; SI-NEXT: s_mov_b32 s92, s16 ; SI-NEXT: v_writelane_b32 v40, s64, 16 ; SI-NEXT: v_writelane_b32 v40, s65, 17 ; SI-NEXT: v_writelane_b32 v40, s66, 18 @@ -81325,52 +81318,54 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: v_writelane_b32 v40, s85, 29 ; SI-NEXT: v_writelane_b32 v40, s86, 30 ; SI-NEXT: v_writelane_b32 v40, s87, 31 -; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane ; SI-NEXT: v_writelane_b32 v40, s96, 32 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v41, s23, 0 +; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane ; SI-NEXT: v_writelane_b32 v40, s97, 33 -; SI-NEXT: v_writelane_b32 v41, s21, 1 -; SI-NEXT: v_readfirstlane_b32 s47, v29 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_writelane_b32 v41, s28, 0 +; SI-NEXT: v_writelane_b32 v41, s26, 1 +; SI-NEXT: v_writelane_b32 v41, s23, 2 +; SI-NEXT: v_writelane_b32 v41, s22, 3 ; SI-NEXT: v_writelane_b32 v40, s98, 34 -; SI-NEXT: v_writelane_b32 v41, s47, 2 +; SI-NEXT: v_writelane_b32 v41, s21, 4 ; SI-NEXT: v_writelane_b32 v40, s99, 35 +; SI-NEXT: s_mov_b32 s88, s29 +; SI-NEXT: s_mov_b32 s30, s25 +; SI-NEXT: s_mov_b32 s29, s24 +; SI-NEXT: v_writelane_b32 v41, s20, 5 ; SI-NEXT: v_readfirstlane_b32 s82, v30 -; SI-NEXT: v_readfirstlane_b32 s83, v28 -; SI-NEXT: v_readfirstlane_b32 s44, v27 -; SI-NEXT: v_readfirstlane_b32 s96, v26 -; SI-NEXT: v_readfirstlane_b32 s70, v25 -; SI-NEXT: v_readfirstlane_b32 s68, v24 -; SI-NEXT: v_readfirstlane_b32 s84, v23 +; SI-NEXT: v_readfirstlane_b32 s57, v29 +; SI-NEXT: v_readfirstlane_b32 s34, v28 +; SI-NEXT: v_readfirstlane_b32 s83, v27 +; SI-NEXT: v_readfirstlane_b32 s46, v26 +; SI-NEXT: v_readfirstlane_b32 s68, v25 +; SI-NEXT: v_readfirstlane_b32 s52, v24 +; SI-NEXT: v_readfirstlane_b32 s81, v23 ; SI-NEXT: v_readfirstlane_b32 s65, v22 ; SI-NEXT: v_readfirstlane_b32 s86, v21 -; SI-NEXT: v_readfirstlane_b32 s66, v20 +; SI-NEXT: v_readfirstlane_b32 s84, v20 ; SI-NEXT: v_readfirstlane_b32 s87, v19 ; SI-NEXT: v_readfirstlane_b32 s80, v18 ; SI-NEXT: v_readfirstlane_b32 s36, v17 -; SI-NEXT: v_readfirstlane_b32 s31, v16 +; SI-NEXT: v_readfirstlane_b32 s97, v16 ; SI-NEXT: v_readfirstlane_b32 s64, v15 ; SI-NEXT: v_readfirstlane_b32 s38, v14 ; SI-NEXT: v_readfirstlane_b32 s67, v13 -; SI-NEXT: v_readfirstlane_b32 s34, v12 -; SI-NEXT: v_readfirstlane_b32 s71, v11 -; SI-NEXT: v_readfirstlane_b32 s81, v10 +; SI-NEXT: v_readfirstlane_b32 s48, v12 +; SI-NEXT: v_readfirstlane_b32 s70, v11 +; SI-NEXT: v_readfirstlane_b32 s71, v10 ; SI-NEXT: v_readfirstlane_b32 s37, v9 -; SI-NEXT: v_readfirstlane_b32 s35, v8 -; SI-NEXT: v_readfirstlane_b32 s49, v7 +; SI-NEXT: v_readfirstlane_b32 s28, v8 +; SI-NEXT: v_readfirstlane_b32 s93, v7 ; SI-NEXT: v_readfirstlane_b32 s94, v6 -; SI-NEXT: v_readfirstlane_b32 s51, v5 -; SI-NEXT: v_readfirstlane_b32 s88, v4 -; SI-NEXT: v_readfirstlane_b32 s53, v3 -; SI-NEXT: v_readfirstlane_b32 s54, v2 -; SI-NEXT: v_readfirstlane_b32 s89, v1 -; SI-NEXT: v_readfirstlane_b32 s90, v0 +; SI-NEXT: v_readfirstlane_b32 s49, v5 +; SI-NEXT: v_readfirstlane_b32 s95, v4 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s91, v31 ; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_readfirstlane_b32 s16, v32 +; SI-NEXT: v_readfirstlane_b32 s89, v32 ; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_readfirstlane_b32 s93, v33 +; SI-NEXT: v_readfirstlane_b32 s79, v33 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:36 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:32 @@ -81380,245 +81375,248 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:16 ; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:12 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s52, v34 +; SI-NEXT: v_readfirstlane_b32 s39, v34 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s55, v35 +; SI-NEXT: v_readfirstlane_b32 s66, v35 ; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_readfirstlane_b32 s79, v37 +; SI-NEXT: v_readfirstlane_b32 s96, v37 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:76 -; SI-NEXT: v_readfirstlane_b32 s50, v36 +; SI-NEXT: v_readfirstlane_b32 s55, v36 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s21, v38 +; SI-NEXT: v_readfirstlane_b32 s47, v38 +; SI-NEXT: v_readfirstlane_b32 s53, v3 +; SI-NEXT: v_readfirstlane_b32 s92, v2 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s54, v0 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s56, v31 +; SI-NEXT: v_readfirstlane_b32 s59, v31 ; SI-NEXT: s_waitcnt vmcnt(10) ; SI-NEXT: v_readfirstlane_b32 s85, v32 ; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_readfirstlane_b32 s58, v33 +; SI-NEXT: v_readfirstlane_b32 s21, v33 ; SI-NEXT: s_waitcnt vmcnt(8) ; SI-NEXT: v_readfirstlane_b32 s98, v39 ; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_readfirstlane_b32 s46, v48 +; SI-NEXT: v_readfirstlane_b32 s26, v48 ; SI-NEXT: s_waitcnt vmcnt(6) ; SI-NEXT: v_readfirstlane_b32 s99, v49 ; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_readfirstlane_b32 s97, v50 +; SI-NEXT: v_readfirstlane_b32 s24, v50 ; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_readfirstlane_b32 s9, v51 -; SI-NEXT: v_writelane_b32 v41, s58, 3 -; SI-NEXT: v_writelane_b32 v41, s9, 4 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v37 +; SI-NEXT: v_readfirstlane_b32 s23, v51 +; SI-NEXT: v_writelane_b32 v41, s21, 6 ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_readfirstlane_b32 s78, v34 +; SI-NEXT: v_readfirstlane_b32 s22, v34 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v37 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_readfirstlane_b32 s69, v35 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_readfirstlane_b32 s30, v36 +; SI-NEXT: v_readfirstlane_b32 s25, v36 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: s_cbranch_scc0 .LBB107_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_and_b32 s4, s92, 0xff +; SI-NEXT: s_and_b32 s4, s16, 0xff ; SI-NEXT: s_lshl_b32 s5, s17, 8 ; SI-NEXT: s_or_b32 s12, s4, s5 ; SI-NEXT: s_and_b32 s4, s18, 0xff ; SI-NEXT: s_lshl_b32 s4, s4, 16 ; SI-NEXT: s_lshl_b32 s5, s19, 24 ; SI-NEXT: s_or_b32 s4, s5, s4 -; SI-NEXT: s_and_b32 s5, s24, 0xff -; SI-NEXT: s_lshl_b32 s6, s25, 8 +; SI-NEXT: s_and_b32 s5, s29, 0xff +; SI-NEXT: s_lshl_b32 s6, s30, 8 ; SI-NEXT: s_or_b32 s13, s5, s6 -; SI-NEXT: s_and_b32 s5, s26, 0xff +; SI-NEXT: v_readlane_b32 s5, v41, 1 +; SI-NEXT: s_and_b32 s5, s5, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s6, s27, 24 ; SI-NEXT: s_or_b32 s6, s6, s5 -; SI-NEXT: s_and_b32 s5, s54, 0xff +; SI-NEXT: s_and_b32 s5, s92, 0xff ; SI-NEXT: s_lshl_b32 s7, s53, 8 ; SI-NEXT: s_or_b32 s14, s5, s7 -; SI-NEXT: s_and_b32 s5, s88, 0xff +; SI-NEXT: s_and_b32 s5, s95, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: s_lshl_b32 s7, s51, 24 +; SI-NEXT: s_lshl_b32 s7, s49, 24 ; SI-NEXT: s_or_b32 s8, s7, s5 -; SI-NEXT: s_and_b32 s5, s81, 0xff -; SI-NEXT: s_lshl_b32 s7, s71, 8 +; SI-NEXT: s_and_b32 s5, s71, 0xff +; SI-NEXT: s_lshl_b32 s7, s70, 8 ; SI-NEXT: s_or_b32 s15, s5, s7 -; SI-NEXT: s_and_b32 s5, s34, 0xff +; SI-NEXT: s_and_b32 s5, s48, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s7, s67, 24 ; SI-NEXT: s_or_b32 s10, s7, s5 ; SI-NEXT: s_and_b32 s5, s80, 0xff ; SI-NEXT: s_lshl_b32 s7, s87, 8 ; SI-NEXT: s_or_b32 s40, s5, s7 -; SI-NEXT: s_and_b32 s5, s66, 0xff +; SI-NEXT: s_and_b32 s5, s84, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s7, s86, 24 ; SI-NEXT: s_or_b32 s60, s7, s5 -; SI-NEXT: s_and_b32 s5, s96, 0xff -; SI-NEXT: s_lshl_b32 s7, s44, 8 +; SI-NEXT: s_and_b32 s5, s46, 0xff +; SI-NEXT: s_lshl_b32 s7, s83, 8 ; SI-NEXT: s_or_b32 s41, s5, s7 -; SI-NEXT: s_and_b32 s5, s9, 0xff -; SI-NEXT: s_lshl_b32 s7, s97, 8 +; SI-NEXT: s_and_b32 s5, s23, 0xff +; SI-NEXT: s_lshl_b32 s7, s24, 8 ; SI-NEXT: s_or_b32 s42, s5, s7 -; SI-NEXT: s_and_b32 s5, s21, 0xff -; SI-NEXT: s_lshl_b32 s7, s79, 8 +; SI-NEXT: s_and_b32 s5, s47, 0xff +; SI-NEXT: s_lshl_b32 s7, s96, 8 ; SI-NEXT: s_or_b32 s43, s5, s7 -; SI-NEXT: v_readlane_b32 s7, v41, 1 -; SI-NEXT: s_and_b32 s5, s20, 0xff +; SI-NEXT: v_readlane_b32 s5, v41, 5 +; SI-NEXT: v_readlane_b32 s7, v41, 4 +; SI-NEXT: s_and_b32 s5, s5, 0xff ; SI-NEXT: s_lshl_b32 s7, s7, 8 ; SI-NEXT: s_or_b32 s5, s5, s7 -; SI-NEXT: s_and_b32 s7, s22, 0xff -; SI-NEXT: v_readlane_b32 s9, v41, 0 +; SI-NEXT: v_readlane_b32 s7, v41, 3 +; SI-NEXT: s_and_b32 s7, s7, 0xff +; SI-NEXT: v_readlane_b32 s9, v41, 2 ; SI-NEXT: s_lshl_b32 s7, s7, 16 ; SI-NEXT: s_lshl_b32 s9, s9, 24 -; SI-NEXT: s_or_b32 s57, s9, s7 -; SI-NEXT: s_and_b32 s7, s28, 0xff -; SI-NEXT: s_lshl_b32 s9, s29, 8 +; SI-NEXT: v_writelane_b32 v41, s46, 9 +; SI-NEXT: s_mov_b32 s56, s30 +; SI-NEXT: s_or_b32 s30, s9, s7 +; SI-NEXT: v_readlane_b32 s7, v41, 0 +; SI-NEXT: s_and_b32 s7, s7, 0xff +; SI-NEXT: s_lshl_b32 s9, s88, 8 ; SI-NEXT: s_or_b32 s7, s7, s9 -; SI-NEXT: s_and_b32 s9, s90, 0xff +; SI-NEXT: s_and_b32 s9, s54, 0xff ; SI-NEXT: s_lshl_b32 s9, s9, 16 -; SI-NEXT: s_lshl_b32 s11, s89, 24 -; SI-NEXT: s_or_b32 s77, s11, s9 +; SI-NEXT: s_lshl_b32 s11, s20, 24 +; SI-NEXT: s_or_b32 s90, s11, s9 ; SI-NEXT: s_and_b32 s9, s94, 0xff -; SI-NEXT: s_lshl_b32 s11, s49, 8 +; SI-NEXT: s_lshl_b32 s11, s93, 8 ; SI-NEXT: s_or_b32 s9, s9, s11 -; SI-NEXT: s_and_b32 s11, s35, 0xff +; SI-NEXT: s_and_b32 s11, s28, 0xff ; SI-NEXT: s_lshl_b32 s11, s11, 16 -; SI-NEXT: v_writelane_b32 v41, s44, 11 ; SI-NEXT: s_lshl_b32 s44, s37, 24 ; SI-NEXT: s_or_b32 vcc_lo, s44, s11 ; SI-NEXT: s_and_b32 s11, s38, 0xff ; SI-NEXT: s_lshl_b32 s44, s64, 8 ; SI-NEXT: s_or_b32 s11, s11, s44 -; SI-NEXT: s_and_b32 s44, s31, 0xff +; SI-NEXT: s_and_b32 s44, s97, 0xff ; SI-NEXT: s_lshl_b32 s44, s44, 16 ; SI-NEXT: s_lshl_b32 s45, s36, 24 +; SI-NEXT: v_writelane_b32 v41, s23, 10 ; SI-NEXT: s_or_b32 vcc_hi, s45, s44 ; SI-NEXT: s_and_b32 s44, s65, 0xff -; SI-NEXT: s_lshl_b32 s45, s84, 8 +; SI-NEXT: s_lshl_b32 s45, s81, 8 ; SI-NEXT: s_or_b32 s44, s44, s45 -; SI-NEXT: s_and_b32 s45, s68, 0xff +; SI-NEXT: s_and_b32 s45, s52, 0xff +; SI-NEXT: v_writelane_b32 v41, s92, 11 ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_mov_b32 s23, s21 -; SI-NEXT: s_mov_b32 s21, s46 -; SI-NEXT: s_lshl_b32 s46, s70, 24 +; SI-NEXT: s_lshl_b32 s46, s68, 24 +; SI-NEXT: v_writelane_b32 v41, s93, 12 ; SI-NEXT: s_and_b32 s44, s44, 0xffff -; SI-NEXT: v_writelane_b32 v41, s97, 12 -; SI-NEXT: s_mov_b32 s97, s86 -; SI-NEXT: s_mov_b32 s86, s84 -; SI-NEXT: s_mov_b32 s84, s70 -; SI-NEXT: s_mov_b32 s70, s34 -; SI-NEXT: s_mov_b32 s34, s88 -; SI-NEXT: s_mov_b32 s88, s24 -; SI-NEXT: s_or_b32 s24, s46, s45 -; SI-NEXT: s_or_b32 s61, s44, s24 +; SI-NEXT: v_writelane_b32 v41, s20, 13 +; SI-NEXT: s_or_b32 s20, s46, s45 +; SI-NEXT: s_or_b32 s61, s44, s20 ; SI-NEXT: s_and_b32 s44, s82, 0xff -; SI-NEXT: s_lshl_b32 s45, s30, 8 +; SI-NEXT: s_lshl_b32 s45, s25, 8 ; SI-NEXT: s_or_b32 s44, s44, s45 ; SI-NEXT: s_and_b32 s45, s69, 0xff ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s78, 24 -; SI-NEXT: s_mov_b32 s95, s90 -; SI-NEXT: s_mov_b32 s90, s18 +; SI-NEXT: s_lshl_b32 s46, s22, 24 +; SI-NEXT: v_writelane_b32 v41, s96, 14 +; SI-NEXT: s_mov_b32 s96, s84 +; SI-NEXT: s_mov_b32 s84, s67 +; SI-NEXT: s_mov_b32 s67, s49 +; SI-NEXT: s_mov_b32 s49, s18 ; SI-NEXT: s_or_b32 s18, s46, s45 -; SI-NEXT: s_and_b32 s45, s83, 0xff +; SI-NEXT: s_and_b32 s45, s34, 0xff ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s47, 24 +; SI-NEXT: s_lshl_b32 s46, s57, 24 ; SI-NEXT: s_and_b32 s44, s44, 0xffff ; SI-NEXT: s_or_b32 s62, s46, s45 ; SI-NEXT: s_or_b32 s63, s44, s18 ; SI-NEXT: s_and_b32 s44, s98, 0xff -; SI-NEXT: s_lshl_b32 s45, s58, 8 +; SI-NEXT: s_lshl_b32 s45, s21, 8 ; SI-NEXT: s_or_b32 s44, s44, s45 ; SI-NEXT: s_and_b32 s45, s85, 0xff ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s56, 24 -; SI-NEXT: s_mov_b32 s76, s56 -; SI-NEXT: s_mov_b32 s56, s85 -; SI-NEXT: s_mov_b32 s85, s79 -; SI-NEXT: s_mov_b32 s79, s19 +; SI-NEXT: s_lshl_b32 s46, s59, 24 +; SI-NEXT: s_mov_b32 s23, s88 +; SI-NEXT: s_mov_b32 s88, s19 ; SI-NEXT: s_or_b32 s19, s46, s45 ; SI-NEXT: s_and_b32 s45, s99, 0xff ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s21, 24 +; SI-NEXT: s_lshl_b32 s46, s26, 24 ; SI-NEXT: s_and_b32 s44, s44, 0xffff ; SI-NEXT: s_or_b32 s72, s46, s45 ; SI-NEXT: s_or_b32 s73, s44, s19 -; SI-NEXT: s_and_b32 s44, s52, 0xff -; SI-NEXT: s_lshl_b32 s45, s93, 8 +; SI-NEXT: s_and_b32 s44, s39, 0xff +; SI-NEXT: s_lshl_b32 s45, s79, 8 ; SI-NEXT: s_or_b32 s44, s44, s45 -; SI-NEXT: s_and_b32 s45, s16, 0xff -; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s91, 24 +; SI-NEXT: s_and_b32 s45, s89, 0xff ; SI-NEXT: s_and_b32 s5, s5, 0xffff -; SI-NEXT: s_mov_b32 s47, s96 -; SI-NEXT: s_mov_b32 s96, s78 -; SI-NEXT: s_mov_b32 s78, s69 -; SI-NEXT: s_mov_b32 s69, s68 -; SI-NEXT: s_mov_b32 s68, s38 -; SI-NEXT: s_mov_b32 s38, s35 -; SI-NEXT: s_mov_b32 s35, s89 -; SI-NEXT: s_or_b32 s89, s46, s45 -; SI-NEXT: s_and_b32 s45, s50, 0xff -; SI-NEXT: s_or_b32 s5, s5, s57 ; SI-NEXT: s_lshl_b32 s45, s45, 16 -; SI-NEXT: s_lshl_b32 s46, s55, 24 +; SI-NEXT: s_lshl_b32 s46, s91, 24 +; SI-NEXT: s_or_b32 s5, s5, s30 +; SI-NEXT: s_mov_b32 s77, s47 +; SI-NEXT: s_mov_b32 s47, s24 +; SI-NEXT: s_mov_b32 s24, s83 +; SI-NEXT: s_mov_b32 s83, s70 +; SI-NEXT: s_mov_b32 s70, s38 +; SI-NEXT: s_mov_b32 s38, s91 +; SI-NEXT: s_mov_b32 s91, s23 +; SI-NEXT: s_mov_b32 s23, s17 +; SI-NEXT: s_or_b32 s17, s46, s45 +; SI-NEXT: s_and_b32 s45, s55, 0xff ; SI-NEXT: s_and_b32 s12, s12, 0xffff +; SI-NEXT: s_and_b32 s7, s7, 0xffff ; SI-NEXT: s_and_b32 s9, s9, 0xffff -; SI-NEXT: s_or_b32 s74, s46, s45 -; SI-NEXT: s_mov_b32 s45, s83 -; SI-NEXT: s_mov_b32 s83, s91 -; SI-NEXT: s_mov_b32 s91, s28 +; SI-NEXT: s_and_b32 s11, s11, 0xffff +; SI-NEXT: s_mov_b32 s76, s59 +; SI-NEXT: s_mov_b32 s59, s57 +; SI-NEXT: s_mov_b32 s57, s34 +; SI-NEXT: s_mov_b32 s34, s82 +; SI-NEXT: s_mov_b32 s82, s52 +; SI-NEXT: s_mov_b32 s52, s95 +; SI-NEXT: s_mov_b32 s95, s27 +; SI-NEXT: s_mov_b32 s21, s22 +; SI-NEXT: s_mov_b32 s22, s69 +; SI-NEXT: s_mov_b32 s69, s48 +; SI-NEXT: s_mov_b32 s48, s37 +; SI-NEXT: s_mov_b32 s37, s56 +; SI-NEXT: s_lshl_b32 s45, s45, 16 +; SI-NEXT: s_lshl_b32 s46, s66, 24 +; SI-NEXT: s_and_b32 s44, s44, 0xffff +; SI-NEXT: s_mov_b32 s56, s98 +; SI-NEXT: s_mov_b32 s98, s28 ; SI-NEXT: s_and_b32 s28, s42, 0xffff -; SI-NEXT: s_mov_b32 s59, s94 -; SI-NEXT: s_mov_b32 s94, s27 ; SI-NEXT: s_and_b32 s27, s43, 0xffff ; SI-NEXT: s_or_b32 s42, s12, s4 ; SI-NEXT: s_mov_b32 s43, s5 ; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16 +; SI-NEXT: s_or_b32 s7, s7, s90 ; SI-NEXT: s_or_b32 s9, s9, vcc_lo -; SI-NEXT: v_writelane_b32 v41, s4, 5 -; SI-NEXT: s_and_b32 s11, s11, 0xffff -; SI-NEXT: v_writelane_b32 v41, s5, 6 -; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 16 ; SI-NEXT: s_or_b32 s11, s11, vcc_hi -; SI-NEXT: v_writelane_b32 v41, s4, 7 -; SI-NEXT: s_and_b32 s7, s7, 0xffff -; SI-NEXT: s_and_b32 s44, s44, 0xffff -; SI-NEXT: v_writelane_b32 v41, s5, 8 -; SI-NEXT: s_lshr_b64 s[4:5], s[10:11], 16 -; SI-NEXT: s_or_b32 s7, s7, s77 -; SI-NEXT: s_or_b32 s75, s44, s89 +; SI-NEXT: s_or_b32 s74, s46, s45 +; SI-NEXT: s_or_b32 s75, s44, s17 ; SI-NEXT: s_and_b32 s13, s13, 0xffff ; SI-NEXT: s_and_b32 s14, s14, 0xffff ; SI-NEXT: s_and_b32 s58, s15, 0xffff -; SI-NEXT: s_mov_b32 s44, s82 -; SI-NEXT: s_mov_b32 s82, s81 -; SI-NEXT: s_mov_b32 s81, s55 -; SI-NEXT: s_mov_b32 s55, s54 -; SI-NEXT: s_mov_b32 s54, s51 -; SI-NEXT: s_mov_b32 s51, s37 -; SI-NEXT: s_mov_b32 s37, s16 +; SI-NEXT: s_mov_b32 s92, s16 ; SI-NEXT: s_and_b32 s16, s40, 0xffff -; SI-NEXT: s_mov_b32 s46, s98 -; SI-NEXT: s_mov_b32 s98, s93 -; SI-NEXT: s_and_b32 s93, s41, 0xffff -; SI-NEXT: v_writelane_b32 v41, s4, 9 -; SI-NEXT: s_mov_b32 s39, s49 +; SI-NEXT: s_mov_b32 s31, s29 +; SI-NEXT: s_and_b32 s29, s41, 0xffff +; SI-NEXT: v_writelane_b32 v41, s4, 7 +; SI-NEXT: s_mov_b32 s93, s39 +; SI-NEXT: s_mov_b32 s39, s79 +; SI-NEXT: v_writelane_b32 v41, s5, 8 ; SI-NEXT: s_or_b32 s40, s13, s6 ; SI-NEXT: s_mov_b32 s41, s7 -; SI-NEXT: s_lshr_b64 s[48:49], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[6:7], 16 ; SI-NEXT: s_or_b32 s14, s14, s8 ; SI-NEXT: s_mov_b32 s15, s9 +; SI-NEXT: s_lshr_b64 s[50:51], s[8:9], 16 ; SI-NEXT: s_or_b32 s12, s58, s10 ; SI-NEXT: s_mov_b32 s13, s11 -; SI-NEXT: v_writelane_b32 v41, s5, 10 +; SI-NEXT: s_lshr_b64 s[44:45], s[10:11], 16 ; SI-NEXT: s_or_b32 s10, s16, s60 ; SI-NEXT: s_mov_b32 s11, s61 ; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16 -; SI-NEXT: s_or_b32 s8, s93, s62 +; SI-NEXT: s_or_b32 s8, s29, s62 ; SI-NEXT: s_mov_b32 s9, s63 ; SI-NEXT: s_lshr_b64 s[62:63], s[62:63], 16 ; SI-NEXT: s_or_b32 s6, s28, s72 @@ -81627,68 +81625,68 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_or_b32 s4, s27, s74 ; SI-NEXT: s_mov_b32 s5, s75 ; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16 -; SI-NEXT: s_mov_b32 s16, s37 -; SI-NEXT: s_mov_b32 s37, s51 -; SI-NEXT: s_mov_b32 s51, s54 -; SI-NEXT: s_mov_b32 s54, s55 -; SI-NEXT: s_mov_b32 s55, s81 -; SI-NEXT: s_mov_b32 s81, s82 -; SI-NEXT: s_mov_b32 s82, s44 -; SI-NEXT: v_readlane_b32 s44, v41, 11 -; SI-NEXT: s_mov_b32 s93, s98 -; SI-NEXT: s_mov_b32 s98, s46 -; SI-NEXT: s_mov_b32 s46, s21 -; SI-NEXT: s_mov_b32 s21, s23 -; SI-NEXT: s_mov_b32 s28, s91 -; SI-NEXT: s_mov_b32 s91, s83 -; SI-NEXT: s_mov_b32 s83, s45 -; SI-NEXT: s_mov_b32 s27, s94 -; SI-NEXT: s_mov_b32 s94, s59 -; SI-NEXT: s_lshr_b32 s23, s57, 16 -; SI-NEXT: s_lshr_b32 s57, s77, 16 -; SI-NEXT: s_lshr_b32 s59, vcc_lo, 16 +; SI-NEXT: s_mov_b32 s16, s92 +; SI-NEXT: s_mov_b32 s79, s39 +; SI-NEXT: s_mov_b32 s39, s93 +; SI-NEXT: s_mov_b32 s29, s31 +; SI-NEXT: s_mov_b32 s28, s98 +; SI-NEXT: s_mov_b32 s98, s56 +; SI-NEXT: s_lshr_b32 s35, s30, 16 +; SI-NEXT: v_readlane_b32 s46, v41, 9 +; SI-NEXT: s_lshr_b32 s56, s90, 16 +; SI-NEXT: s_lshr_b32 s58, vcc_lo, 16 ; SI-NEXT: s_lshr_b32 s61, vcc_hi, 16 -; SI-NEXT: s_lshr_b32 s63, s24, 16 -; SI-NEXT: s_mov_b32 s24, s88 -; SI-NEXT: s_mov_b32 s88, s34 -; SI-NEXT: s_mov_b32 s34, s70 -; SI-NEXT: s_mov_b32 s70, s84 -; SI-NEXT: s_mov_b32 s84, s86 -; SI-NEXT: s_mov_b32 s86, s97 -; SI-NEXT: v_readlane_b32 s97, v41, 12 +; SI-NEXT: s_lshr_b32 s63, s20, 16 +; SI-NEXT: v_readlane_b32 s20, v41, 13 +; SI-NEXT: v_readlane_b32 s93, v41, 12 +; SI-NEXT: v_readlane_b32 s92, v41, 11 ; SI-NEXT: s_lshr_b32 s73, s18, 16 -; SI-NEXT: s_mov_b32 s18, s90 -; SI-NEXT: s_mov_b32 s90, s95 -; SI-NEXT: s_mov_b32 s49, s39 +; SI-NEXT: s_mov_b32 s18, s49 +; SI-NEXT: s_mov_b32 s49, s67 +; SI-NEXT: s_mov_b32 s67, s84 +; SI-NEXT: s_mov_b32 s84, s96 +; SI-NEXT: v_readlane_b32 s96, v41, 14 ; SI-NEXT: s_lshr_b32 s75, s19, 16 -; SI-NEXT: s_mov_b32 s19, s79 -; SI-NEXT: s_mov_b32 s79, s85 -; SI-NEXT: s_mov_b32 s85, s56 -; SI-NEXT: s_mov_b32 s56, s76 -; SI-NEXT: s_lshr_b32 s45, s89, 16 -; SI-NEXT: s_mov_b32 s89, s35 -; SI-NEXT: s_mov_b32 s35, s38 -; SI-NEXT: s_mov_b32 s38, s68 -; SI-NEXT: s_mov_b32 s68, s69 -; SI-NEXT: s_mov_b32 s69, s78 -; SI-NEXT: s_mov_b32 s78, s96 -; SI-NEXT: s_mov_b32 s96, s47 +; SI-NEXT: s_mov_b32 s19, s88 +; SI-NEXT: s_lshr_b32 s45, s17, 16 +; SI-NEXT: s_mov_b32 s17, s23 +; SI-NEXT: v_readlane_b32 s23, v41, 10 +; SI-NEXT: s_mov_b32 s30, s37 +; SI-NEXT: s_mov_b32 s37, s48 +; SI-NEXT: s_mov_b32 s48, s69 +; SI-NEXT: s_mov_b32 s69, s22 +; SI-NEXT: s_mov_b32 s22, s21 +; SI-NEXT: s_mov_b32 s27, s95 +; SI-NEXT: s_mov_b32 s95, s52 +; SI-NEXT: s_mov_b32 s52, s82 +; SI-NEXT: s_mov_b32 s82, s34 +; SI-NEXT: s_mov_b32 s88, s91 +; SI-NEXT: s_mov_b32 s91, s38 +; SI-NEXT: s_mov_b32 s38, s70 +; SI-NEXT: s_mov_b32 s70, s83 +; SI-NEXT: s_mov_b32 s83, s24 +; SI-NEXT: s_mov_b32 s24, s47 +; SI-NEXT: s_mov_b32 s47, s77 +; SI-NEXT: s_mov_b32 s34, s57 +; SI-NEXT: s_mov_b32 s57, s59 +; SI-NEXT: s_mov_b32 s59, s76 ; SI-NEXT: s_mov_b64 s[76:77], 0 ; SI-NEXT: s_branch .LBB107_3 ; SI-NEXT: .LBB107_2: ; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: s_mov_b64 s[76:77], -1 -; SI-NEXT: v_writelane_b32 v41, s4, 5 -; SI-NEXT: v_writelane_b32 v41, s5, 6 -; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v41, s4, 7 ; SI-NEXT: ; implicit-def: $sgpr42 -; SI-NEXT: ; implicit-def: $sgpr23 +; SI-NEXT: v_writelane_b32 v41, s5, 8 +; SI-NEXT: ; implicit-def: $sgpr35 ; SI-NEXT: ; implicit-def: $sgpr40 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr57 +; SI-NEXT: ; implicit-def: $sgpr78 +; SI-NEXT: ; implicit-def: $sgpr56 ; SI-NEXT: ; implicit-def: $sgpr14 -; SI-NEXT: ; implicit-def: $sgpr59 +; SI-NEXT: ; implicit-def: $sgpr50 +; SI-NEXT: ; implicit-def: $sgpr58 ; SI-NEXT: ; implicit-def: $sgpr12 +; SI-NEXT: ; implicit-def: $sgpr44 ; SI-NEXT: ; implicit-def: $sgpr61 ; SI-NEXT: ; implicit-def: $sgpr10 ; SI-NEXT: ; implicit-def: $sgpr60 @@ -81699,39 +81697,31 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: ; implicit-def: $sgpr6 ; SI-NEXT: ; implicit-def: $sgpr72 ; SI-NEXT: ; implicit-def: $sgpr75 +; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: ; implicit-def: $sgpr74 ; SI-NEXT: ; implicit-def: $sgpr45 -; SI-NEXT: v_writelane_b32 v41, s4, 7 -; SI-NEXT: v_writelane_b32 v41, s5, 8 -; SI-NEXT: ; implicit-def: $sgpr4 -; SI-NEXT: v_writelane_b32 v41, s4, 9 -; SI-NEXT: v_writelane_b32 v41, s5, 10 -; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: .LBB107_3: ; %Flow ; SI-NEXT: s_andn2_b64 vcc, exec, s[76:77] -; SI-NEXT: v_readlane_b32 s76, v41, 5 -; SI-NEXT: v_readlane_b32 s77, v41, 6 -; SI-NEXT: s_mov_b32 s58, s76 ; SI-NEXT: v_readlane_b32 s76, v41, 7 ; SI-NEXT: v_readlane_b32 s77, v41, 8 ; SI-NEXT: s_cbranch_vccnz .LBB107_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s21, s47, 3 ; SI-NEXT: s_and_b32 s4, s21, 0xff -; SI-NEXT: s_lshl_b32 s5, s79, 8 -; SI-NEXT: s_add_i32 s50, s50, 3 +; SI-NEXT: s_lshl_b32 s5, s96, 8 +; SI-NEXT: s_add_i32 s50, s55, 3 ; SI-NEXT: s_or_b32 s4, s5, s4 ; SI-NEXT: s_and_b32 s6, s50, 0xff ; SI-NEXT: s_addk_i32 s4, 0x300 -; SI-NEXT: s_lshl_b32 s5, s55, 24 +; SI-NEXT: s_lshl_b32 s5, s66, 24 ; SI-NEXT: s_lshl_b32 s6, s6, 16 ; SI-NEXT: s_and_b32 s4, s4, 0xffff ; SI-NEXT: s_or_b32 s5, s5, s6 -; SI-NEXT: s_add_i32 s39, s52, 3 +; SI-NEXT: s_add_i32 s39, s39, 3 ; SI-NEXT: s_or_b32 s4, s5, s4 ; SI-NEXT: s_and_b32 s5, s39, 0xff -; SI-NEXT: s_lshl_b32 s6, s93, 8 -; SI-NEXT: s_add_i32 s79, s16, 3 +; SI-NEXT: s_lshl_b32 s6, s79, 8 +; SI-NEXT: s_add_i32 s79, s89, 3 ; SI-NEXT: s_or_b32 s5, s6, s5 ; SI-NEXT: s_and_b32 s7, s79, 0xff ; SI-NEXT: s_addk_i32 s5, 0x300 @@ -81739,21 +81729,20 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_lshl_b32 s7, s7, 16 ; SI-NEXT: s_and_b32 s5, s5, 0xffff ; SI-NEXT: s_or_b32 s6, s6, s7 +; SI-NEXT: s_add_i32 s23, s23, 3 ; SI-NEXT: s_or_b32 s5, s6, s5 -; SI-NEXT: v_readlane_b32 s6, v41, 4 -; SI-NEXT: s_add_i32 s23, s6, 3 ; SI-NEXT: s_and_b32 s6, s23, 0xff -; SI-NEXT: s_lshl_b32 s7, s97, 8 +; SI-NEXT: s_lshl_b32 s7, s24, 8 ; SI-NEXT: s_add_i32 s99, s99, 3 ; SI-NEXT: s_or_b32 s6, s7, s6 ; SI-NEXT: s_and_b32 s8, s99, 0xff ; SI-NEXT: s_addk_i32 s6, 0x300 -; SI-NEXT: s_lshl_b32 s7, s46, 24 +; SI-NEXT: s_lshl_b32 s7, s26, 24 ; SI-NEXT: s_lshl_b32 s8, s8, 16 ; SI-NEXT: s_and_b32 s6, s6, 0xffff ; SI-NEXT: s_or_b32 s7, s7, s8 ; SI-NEXT: s_add_i32 s98, s98, 3 -; SI-NEXT: v_readlane_b32 s8, v41, 3 +; SI-NEXT: v_readlane_b32 s8, v41, 6 ; SI-NEXT: s_or_b32 s6, s7, s6 ; SI-NEXT: s_and_b32 s7, s98, 0xff ; SI-NEXT: s_lshl_b32 s8, s8, 8 @@ -81761,32 +81750,31 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_or_b32 s7, s8, s7 ; SI-NEXT: s_and_b32 s9, s85, 0xff ; SI-NEXT: s_addk_i32 s7, 0x300 -; SI-NEXT: s_lshl_b32 s8, s56, 24 +; SI-NEXT: s_lshl_b32 s8, s59, 24 ; SI-NEXT: s_lshl_b32 s9, s9, 16 ; SI-NEXT: s_and_b32 s7, s7, 0xffff ; SI-NEXT: s_or_b32 s8, s8, s9 -; SI-NEXT: s_add_i32 s96, s96, 3 +; SI-NEXT: s_add_i32 s96, s46, 3 ; SI-NEXT: s_or_b32 s7, s8, s7 ; SI-NEXT: s_and_b32 s8, s96, 0xff -; SI-NEXT: s_lshl_b32 s9, s44, 8 -; SI-NEXT: s_add_i32 s83, s83, 3 +; SI-NEXT: s_lshl_b32 s9, s83, 8 +; SI-NEXT: s_add_i32 s83, s34, 3 ; SI-NEXT: s_or_b32 s8, s9, s8 -; SI-NEXT: v_readlane_b32 s9, v41, 2 ; SI-NEXT: s_and_b32 s10, s83, 0xff ; SI-NEXT: s_addk_i32 s8, 0x300 -; SI-NEXT: s_lshl_b32 s9, s9, 24 +; SI-NEXT: s_lshl_b32 s9, s57, 24 ; SI-NEXT: s_lshl_b32 s10, s10, 16 ; SI-NEXT: s_and_b32 s8, s8, 0xffff ; SI-NEXT: s_or_b32 s9, s9, s10 ; SI-NEXT: s_add_i32 s82, s82, 3 ; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_and_b32 s9, s82, 0xff -; SI-NEXT: s_lshl_b32 s10, s30, 8 +; SI-NEXT: s_lshl_b32 s10, s25, 8 ; SI-NEXT: s_add_i32 s69, s69, 3 ; SI-NEXT: s_or_b32 s9, s10, s9 ; SI-NEXT: s_and_b32 s11, s69, 0xff ; SI-NEXT: s_addk_i32 s9, 0x300 -; SI-NEXT: s_lshl_b32 s10, s78, 24 +; SI-NEXT: s_lshl_b32 s10, s22, 24 ; SI-NEXT: s_lshl_b32 s11, s11, 16 ; SI-NEXT: s_and_b32 s9, s9, 0xffff ; SI-NEXT: s_or_b32 s10, s10, s11 @@ -81794,7 +81782,7 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_or_b32 s9, s10, s9 ; SI-NEXT: s_and_b32 s10, s80, 0xff ; SI-NEXT: s_lshl_b32 s11, s87, 8 -; SI-NEXT: s_add_i32 s66, s66, 3 +; SI-NEXT: s_add_i32 s66, s84, 3 ; SI-NEXT: s_or_b32 s10, s11, s10 ; SI-NEXT: s_and_b32 s12, s66, 0xff ; SI-NEXT: s_addk_i32 s10, 0x300 @@ -81805,20 +81793,20 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_add_i32 s65, s65, 3 ; SI-NEXT: s_or_b32 s10, s11, s10 ; SI-NEXT: s_and_b32 s11, s65, 0xff -; SI-NEXT: s_lshl_b32 s12, s84, 8 -; SI-NEXT: s_add_i32 s52, s68, 3 +; SI-NEXT: s_lshl_b32 s12, s81, 8 +; SI-NEXT: s_add_i32 s52, s52, 3 ; SI-NEXT: s_or_b32 s11, s12, s11 ; SI-NEXT: s_and_b32 s13, s52, 0xff ; SI-NEXT: s_addk_i32 s11, 0x300 -; SI-NEXT: s_lshl_b32 s12, s70, 24 +; SI-NEXT: s_lshl_b32 s12, s68, 24 ; SI-NEXT: s_lshl_b32 s13, s13, 16 ; SI-NEXT: s_and_b32 s11, s11, 0xffff ; SI-NEXT: s_or_b32 s12, s12, s13 -; SI-NEXT: s_add_i32 s55, s81, 3 +; SI-NEXT: s_add_i32 s55, s71, 3 ; SI-NEXT: s_or_b32 s11, s12, s11 ; SI-NEXT: s_and_b32 s12, s55, 0xff -; SI-NEXT: s_lshl_b32 s13, s71, 8 -; SI-NEXT: s_add_i32 s48, s34, 3 +; SI-NEXT: s_lshl_b32 s13, s70, 8 +; SI-NEXT: s_add_i32 s48, s48, 3 ; SI-NEXT: s_or_b32 s12, s13, s12 ; SI-NEXT: s_and_b32 s14, s48, 0xff ; SI-NEXT: s_addk_i32 s12, 0x300 @@ -81830,7 +81818,7 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_or_b32 s12, s13, s12 ; SI-NEXT: s_and_b32 s13, s38, 0xff ; SI-NEXT: s_lshl_b32 s14, s64, 8 -; SI-NEXT: s_add_i32 s31, s31, 3 +; SI-NEXT: s_add_i32 s31, s97, 3 ; SI-NEXT: s_or_b32 s13, s14, s13 ; SI-NEXT: s_and_b32 s15, s31, 0xff ; SI-NEXT: s_addk_i32 s13, 0x300 @@ -81838,84 +81826,85 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_lshl_b32 s15, s15, 16 ; SI-NEXT: s_and_b32 s13, s13, 0xffff ; SI-NEXT: s_or_b32 s14, s14, s15 -; SI-NEXT: s_add_i32 s36, s54, 3 +; SI-NEXT: s_add_i32 s36, s92, 3 ; SI-NEXT: s_or_b32 s13, s14, s13 ; SI-NEXT: s_and_b32 s14, s36, 0xff ; SI-NEXT: s_lshl_b32 s15, s53, 8 -; SI-NEXT: s_add_i32 s95, s88, 3 +; SI-NEXT: s_add_i32 s95, s95, 3 ; SI-NEXT: s_or_b32 s14, s15, s14 ; SI-NEXT: s_and_b32 s21, s95, 0xff ; SI-NEXT: s_addk_i32 s14, 0x300 -; SI-NEXT: s_lshl_b32 s15, s51, 24 +; SI-NEXT: s_lshl_b32 s15, s49, 24 ; SI-NEXT: s_lshl_b32 s21, s21, 16 ; SI-NEXT: s_and_b32 s14, s14, 0xffff ; SI-NEXT: s_or_b32 s15, s15, s21 ; SI-NEXT: s_add_i32 s94, s94, 3 ; SI-NEXT: s_or_b32 s14, s15, s14 ; SI-NEXT: s_and_b32 s15, s94, 0xff -; SI-NEXT: s_lshl_b32 s21, s49, 8 -; SI-NEXT: s_add_i32 s91, s35, 3 +; SI-NEXT: s_lshl_b32 s21, s93, 8 +; SI-NEXT: s_add_i32 s91, s28, 3 ; SI-NEXT: s_or_b32 s15, s21, s15 -; SI-NEXT: s_and_b32 s16, s91, 0xff +; SI-NEXT: s_and_b32 s22, s91, 0xff ; SI-NEXT: s_addk_i32 s15, 0x300 ; SI-NEXT: s_lshl_b32 s21, s37, 24 -; SI-NEXT: s_lshl_b32 s16, s16, 16 +; SI-NEXT: s_lshl_b32 s22, s22, 16 ; SI-NEXT: s_and_b32 s15, s15, 0xffff -; SI-NEXT: s_or_b32 s21, s21, s16 -; SI-NEXT: s_add_i32 s24, s24, 3 +; SI-NEXT: s_or_b32 s21, s21, s22 +; SI-NEXT: s_add_i32 s24, s29, 3 +; SI-NEXT: v_readlane_b32 s23, v41, 1 +; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_or_b32 s15, s21, s15 ; SI-NEXT: s_and_b32 s21, s24, 0xff -; SI-NEXT: s_lshl_b32 s16, s25, 8 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_or_b32 s21, s16, s21 -; SI-NEXT: s_and_b32 s23, s26, 0xff -; SI-NEXT: s_addk_i32 s21, 0x300 -; SI-NEXT: s_lshl_b32 s16, s27, 24 -; SI-NEXT: s_lshl_b32 s23, s23, 16 -; SI-NEXT: s_and_b32 s21, s21, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s23 -; SI-NEXT: s_or_b32 s21, s16, s21 -; SI-NEXT: s_add_i32 s28, s28, 3 -; SI-NEXT: s_add_i32 s40, s21, 0x3000000 -; SI-NEXT: s_and_b32 s21, s28, 0xff -; SI-NEXT: s_lshl_b32 s16, s29, 8 -; SI-NEXT: s_lshl_b32 s23, s89, 24 -; SI-NEXT: s_add_i32 s89, s90, 3 -; SI-NEXT: s_or_b32 s21, s16, s21 -; SI-NEXT: s_and_b32 s16, s89, 0xff -; SI-NEXT: s_addk_i32 s21, 0x300 -; SI-NEXT: s_lshl_b32 s16, s16, 16 -; SI-NEXT: s_and_b32 s21, s21, 0xffff -; SI-NEXT: s_or_b32 s16, s23, s16 -; SI-NEXT: s_or_b32 s16, s16, s21 -; SI-NEXT: s_add_i32 s41, s16, 0x3000000 -; SI-NEXT: s_add_i32 s16, s92, 3 +; SI-NEXT: s_lshl_b32 s22, s30, 8 +; SI-NEXT: s_add_i32 s26, s23, 3 ; SI-NEXT: s_and_b32 s16, s16, 0xff ; SI-NEXT: s_lshl_b32 s17, s17, 8 ; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_or_b32 s21, s22, s21 +; SI-NEXT: s_and_b32 s23, s26, 0xff ; SI-NEXT: s_or_b32 s16, s17, s16 ; SI-NEXT: s_and_b32 s18, s18, 0xff +; SI-NEXT: s_addk_i32 s21, 0x300 +; SI-NEXT: s_lshl_b32 s22, s27, 24 +; SI-NEXT: s_lshl_b32 s23, s23, 16 ; SI-NEXT: s_addk_i32 s16, 0x300 ; SI-NEXT: s_lshl_b32 s17, s19, 24 ; SI-NEXT: s_lshl_b32 s18, s18, 16 +; SI-NEXT: s_and_b32 s21, s21, 0xffff +; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: s_and_b32 s16, s16, 0xffff ; SI-NEXT: s_or_b32 s17, s17, s18 +; SI-NEXT: s_or_b32 s21, s22, s21 ; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_add_i32 s40, s21, 0x3000000 +; SI-NEXT: v_readlane_b32 s21, v41, 0 ; SI-NEXT: s_add_i32 s42, s16, 0x3000000 -; SI-NEXT: s_add_i32 s16, s20, 3 -; SI-NEXT: v_readlane_b32 s17, v41, 1 +; SI-NEXT: v_readlane_b32 s16, v41, 5 +; SI-NEXT: s_add_i32 s28, s21, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 +; SI-NEXT: v_readlane_b32 s17, v41, 4 +; SI-NEXT: v_readlane_b32 s18, v41, 3 +; SI-NEXT: s_and_b32 s21, s28, 0xff +; SI-NEXT: s_lshl_b32 s22, s88, 8 +; SI-NEXT: s_add_i32 s89, s54, 3 ; SI-NEXT: s_and_b32 s16, s16, 0xff ; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_add_i32 s18, s22, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_or_b32 s21, s22, s21 +; SI-NEXT: s_and_b32 s22, s89, 0xff ; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_readlane_b32 s17, v41, 0 +; SI-NEXT: v_readlane_b32 s17, v41, 2 ; SI-NEXT: s_and_b32 s18, s18, 0xff +; SI-NEXT: s_addk_i32 s21, 0x300 +; SI-NEXT: s_lshl_b32 s20, s20, 24 +; SI-NEXT: s_lshl_b32 s22, s22, 16 ; SI-NEXT: s_addk_i32 s16, 0x300 ; SI-NEXT: s_lshl_b32 s17, s17, 24 ; SI-NEXT: s_lshl_b32 s18, s18, 16 +; SI-NEXT: s_and_b32 s21, s21, 0xffff +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: s_and_b32 s16, s16, 0xffff ; SI-NEXT: s_or_b32 s17, s17, s18 -; SI-NEXT: s_or_b32 s16, s17, s16 ; SI-NEXT: s_add_i32 s4, s4, 0x3000000 ; SI-NEXT: s_add_i32 s5, s5, 0x3000000 ; SI-NEXT: s_add_i32 s6, s6, 0x3000000 @@ -81926,49 +81915,49 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_add_i32 s11, s11, 0x3000000 ; SI-NEXT: s_add_i32 s12, s12, 0x3000000 ; SI-NEXT: s_add_i32 s13, s13, 0x3000000 -; SI-NEXT: s_add_i32 s43, s16, 0x3000000 +; SI-NEXT: s_or_b32 s20, s20, s21 +; SI-NEXT: s_or_b32 s16, s17, s16 ; SI-NEXT: s_add_i32 s14, s14, 0x3000000 ; SI-NEXT: s_add_i32 s15, s15, 0x3000000 -; SI-NEXT: s_lshr_b64 s[58:59], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 16 +; SI-NEXT: s_add_i32 s41, s20, 0x3000000 +; SI-NEXT: s_add_i32 s43, s16, 0x3000000 +; SI-NEXT: s_lshr_b64 s[44:45], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[72:73], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[48:49], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[14:15], 16 -; SI-NEXT: v_writelane_b32 v41, s16, 9 -; SI-NEXT: s_lshr_b32 s23, s43, 16 -; SI-NEXT: s_lshr_b32 s57, s41, 16 -; SI-NEXT: s_lshr_b32 s59, s15, 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[50:51], s[14:15], 16 +; SI-NEXT: s_lshr_b32 s35, s43, 16 +; SI-NEXT: s_lshr_b32 s56, s41, 16 +; SI-NEXT: s_lshr_b32 s58, s15, 16 ; SI-NEXT: s_lshr_b32 s61, s13, 16 ; SI-NEXT: s_lshr_b32 s63, s11, 16 ; SI-NEXT: s_lshr_b32 s73, s9, 16 ; SI-NEXT: s_lshr_b32 s75, s7, 16 ; SI-NEXT: s_lshr_b32 s45, s5, 16 -; SI-NEXT: v_writelane_b32 v41, s17, 10 ; SI-NEXT: .LBB107_5: ; %end ; SI-NEXT: s_and_b32 s16, s42, 0xffff -; SI-NEXT: s_lshl_b32 s17, s58, 16 +; SI-NEXT: s_lshl_b32 s17, s76, 16 ; SI-NEXT: s_or_b32 s16, s16, s17 ; SI-NEXT: s_and_b32 s17, s43, 0xffff -; SI-NEXT: s_lshl_b32 s18, s23, 16 +; SI-NEXT: s_lshl_b32 s18, s35, 16 ; SI-NEXT: s_or_b32 s17, s17, s18 ; SI-NEXT: s_and_b32 s18, s40, 0xffff -; SI-NEXT: s_lshl_b32 s19, s48, 16 +; SI-NEXT: s_lshl_b32 s19, s78, 16 ; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: s_and_b32 s19, s41, 0xffff -; SI-NEXT: s_lshl_b32 s20, s57, 16 +; SI-NEXT: s_lshl_b32 s20, s56, 16 ; SI-NEXT: s_or_b32 s19, s19, s20 ; SI-NEXT: s_and_b32 s14, s14, 0xffff -; SI-NEXT: s_lshl_b32 s20, s76, 16 +; SI-NEXT: s_lshl_b32 s20, s50, 16 ; SI-NEXT: s_or_b32 s14, s14, s20 ; SI-NEXT: s_and_b32 s15, s15, 0xffff -; SI-NEXT: s_lshl_b32 s20, s59, 16 +; SI-NEXT: s_lshl_b32 s20, s58, 16 ; SI-NEXT: s_or_b32 s15, s15, s20 -; SI-NEXT: v_readlane_b32 s20, v41, 9 ; SI-NEXT: s_and_b32 s12, s12, 0xffff -; SI-NEXT: s_lshl_b32 s20, s20, 16 +; SI-NEXT: s_lshl_b32 s20, s44, 16 ; SI-NEXT: s_or_b32 s12, s12, s20 ; SI-NEXT: s_and_b32 s13, s13, 0xffff ; SI-NEXT: s_lshl_b32 s20, s61, 16 @@ -81997,7 +81986,6 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 ; SI-NEXT: s_and_b32 s5, s5, 0xffff ; SI-NEXT: s_lshl_b32 s20, s45, 16 ; SI-NEXT: s_or_b32 s5, s5, s20 -; SI-NEXT: v_readlane_b32 s21, v41, 10 ; SI-NEXT: v_mov_b32_e32 v0, s16 ; SI-NEXT: v_mov_b32_e32 v1, s17 ; SI-NEXT: v_mov_b32_e32 v2, s18 diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll index 1fecc2b613c4c..fa1ba6ceff58b 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.f64.ll @@ -767,8 +767,8 @@ define double @rsq_f64_assume_nonzero(double %x) { ret double %fdiv } -attributes #0 = { "denormal-fp-math"="ieee,dynamic" } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } +attributes #0 = { denormal_fpenv(ieee|dynamic) } +attributes #1 = { denormal_fpenv(ieee|preservesign) } !0 = !{float 2.500000e+00} ;. diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll index a8e5e11b37f25..65053d00f9c90 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll @@ -67,7 +67,7 @@ define half @test_pow_fast_f16__integral_y(half %x, i32 %y.i) { ; CHECK-NEXT: v_cvt_i32_f32_e32 v2, v2 ; CHECK-NEXT: v_lshlrev_b16_e32 v2, 15, v2 ; CHECK-NEXT: v_and_b32_e32 v0, v2, v0 -; CHECK-NEXT: v_or_b32_e32 v0, v0, v1 +; CHECK-NEXT: v_or_b32_e32 v0, v1, v0 ; CHECK-NEXT: s_setpc_b64 s[30:31] %y = sitofp i32 %y.i to half %pow = tail call fast half @_Z3powDhDh(half %x, half %y) @@ -176,7 +176,7 @@ define double @test_pow_fast_f64__integral_y(double %x, i32 %y.i) { ; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; CHECK-NEXT: v_or_b32_e32 v1, v2, v1 +; CHECK-NEXT: v_or_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_readlane_b32 s53, v43, 13 ; CHECK-NEXT: v_readlane_b32 s52, v43, 12 ; CHECK-NEXT: v_readlane_b32 s51, v43, 11 @@ -353,7 +353,7 @@ define half @test_pown_fast_f16(half %x, i32 %y) { ; CHECK-NEXT: v_cvt_f16_f32_e32 v2, v2 ; CHECK-NEXT: v_mul_f16_e32 v2, v3, v2 ; CHECK-NEXT: v_exp_f16_e32 v2, v2 -; CHECK-NEXT: v_or_b32_e32 v0, v0, v2 +; CHECK-NEXT: v_or_b32_e32 v0, v2, v0 ; CHECK-NEXT: s_setpc_b64 s[30:31] %call = tail call fast half @_Z4pownDhi(half %x, i32 %y) ret half %call @@ -458,7 +458,7 @@ define double @test_pown_fast_f64(double %x, i32 %y) { ; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; CHECK-NEXT: v_or_b32_e32 v1, v2, v1 +; CHECK-NEXT: v_or_b32_e32 v1, v1, v2 ; CHECK-NEXT: v_readlane_b32 s53, v43, 13 ; CHECK-NEXT: v_readlane_b32 s52, v43, 12 ; CHECK-NEXT: v_readlane_b32 s51, v43, 11 @@ -681,7 +681,7 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) { ; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1 ; CHECK-NEXT: buffer_store_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill ; CHECK-NEXT: s_mov_b64 exec, s[18:19] -; CHECK-NEXT: v_writelane_b32 v43, s16, 14 +; CHECK-NEXT: v_writelane_b32 v43, s16, 15 ; CHECK-NEXT: v_writelane_b32 v43, s30, 0 ; CHECK-NEXT: v_writelane_b32 v43, s31, 1 ; CHECK-NEXT: v_writelane_b32 v43, s34, 2 @@ -699,15 +699,16 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) { ; CHECK-NEXT: s_addc_u32 s5, s5, _Z4log2d@gotpcrel32@hi+12 ; CHECK-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0 ; CHECK-NEXT: v_writelane_b32 v43, s50, 10 +; CHECK-NEXT: v_writelane_b32 v43, s51, 11 ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; CHECK-NEXT: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill -; CHECK-NEXT: v_writelane_b32 v43, s51, 11 -; CHECK-NEXT: v_mov_b32_e32 v41, v1 ; CHECK-NEXT: v_writelane_b32 v43, s52, 12 +; CHECK-NEXT: v_mov_b32_e32 v41, v1 +; CHECK-NEXT: v_writelane_b32 v43, s53, 13 ; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v41 ; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49] -; CHECK-NEXT: v_writelane_b32 v43, s53, 13 +; CHECK-NEXT: v_writelane_b32 v43, s54, 14 ; CHECK-NEXT: v_mov_b32_e32 v40, v31 ; CHECK-NEXT: s_mov_b32 s50, s15 ; CHECK-NEXT: s_mov_b32 s51, s14 @@ -717,6 +718,7 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) { ; CHECK-NEXT: s_mov_b64 s[36:37], s[8:9] ; CHECK-NEXT: s_mov_b64 s[38:39], s[6:7] ; CHECK-NEXT: v_or_b32_e32 v42, 1, v2 +; CHECK-NEXT: s_brev_b32 s54, -2 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] ; CHECK-NEXT: v_cvt_f64_i32_e32 v[2:3], v42 @@ -736,11 +738,11 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) { ; CHECK-NEXT: v_mov_b32_e32 v31, v40 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17] -; CHECK-NEXT: v_and_b32_e32 v2, 0x80000000, v41 +; CHECK-NEXT: v_bfi_b32 v1, s54, v1, v41 ; CHECK-NEXT: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload -; CHECK-NEXT: v_or_b32_e32 v1, v2, v1 +; CHECK-NEXT: v_readlane_b32 s54, v43, 14 ; CHECK-NEXT: v_readlane_b32 s53, v43, 13 ; CHECK-NEXT: v_readlane_b32 s52, v43, 12 ; CHECK-NEXT: v_readlane_b32 s51, v43, 11 @@ -756,7 +758,7 @@ define double @test_pown_fast_f64_known_odd(double %x, i32 %y.arg) { ; CHECK-NEXT: v_readlane_b32 s31, v43, 1 ; CHECK-NEXT: v_readlane_b32 s30, v43, 0 ; CHECK-NEXT: s_mov_b32 s32, s33 -; CHECK-NEXT: v_readlane_b32 s4, v43, 14 +; CHECK-NEXT: v_readlane_b32 s4, v43, 15 ; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1 ; CHECK-NEXT: buffer_load_dword v43, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload ; CHECK-NEXT: s_mov_b64 exec, s[6:7] diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll index 113531571757c..193e3a740b92e 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll @@ -1073,7 +1073,7 @@ define float @test_pow_afn_f32_nnan_ninf_x_known_positive(float nofpclass(ninf n ; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: ret float [[__EXP2]] ; %pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y) @@ -1095,7 +1095,7 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf_x_known_positive(<2 x float> no ; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) ; CHECK-NEXT: ret <2 x float> [[__EXP2]] ; %pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y) @@ -1157,7 +1157,7 @@ define double @test_pow_afn_f64_nnan_ninf_x_known_positive(double nofpclass(ninf ; CHECK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn double @_Z4log2d(double [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn double [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn double @_Z4exp2d(double [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) double @_Z4exp2d(double [[__YLOGX]]) ; CHECK-NEXT: ret double [[__EXP2]] ; %pow = tail call afn nnan ninf double @_Z3powdd(double %x, double %y) @@ -1179,7 +1179,7 @@ define <2 x double> @test_pow_afn_v2f64_nnan_ninf_x_known_positive(<2 x double> ; CHECK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x double> @_Z4log2Dv2_d(<2 x double> [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x double> [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]]) ; CHECK-NEXT: ret <2 x double> [[__EXP2]] ; %pow = tail call afn nnan ninf <2 x double> @_Z3powDv2_dS_(<2 x double> %x, <2 x double> %y) @@ -1241,7 +1241,7 @@ define half @test_pow_afn_f16_nnan_ninf_x_known_positive(half nofpclass(ninf nno ; CHECK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn half @llvm.log2.f16(half [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn half [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn half @llvm.exp2.f16(half [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) half @llvm.exp2.f16(half [[__YLOGX]]) ; CHECK-NEXT: ret half [[__EXP2]] ; %pow = tail call afn nnan ninf half @_Z3powDhDh(half %x, half %y) @@ -1263,7 +1263,7 @@ define <2 x half> @test_pow_afn_v2f16_nnan_ninf_x_known_positive(<2 x half> nofp ; CHECK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x half> @llvm.log2.v2f16(<2 x half> [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x half> [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x half> @llvm.exp2.v2f16(<2 x half> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x half> @llvm.exp2.v2f16(<2 x half> [[__YLOGX]]) ; CHECK-NEXT: ret <2 x half> [[__EXP2]] ; %pow = tail call afn nnan ninf <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> %y) @@ -2209,14 +2209,13 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp(float %x, i32 %y) ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32 -; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float -; CHECK-NEXT: ret float [[TMP5]] +; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]]) +; CHECK-NEXT: ret float [[__POW_SIGN1]] ; %y.cast = sitofp i32 %y to float %pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast) @@ -2297,14 +2296,13 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp(float %x, i32 %y) ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32 -; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float -; CHECK-NEXT: ret float [[TMP5]] +; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]]) +; CHECK-NEXT: ret float [[__POW_SIGN1]] ; %y.cast = uitofp i32 %y to float %pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast) @@ -2346,14 +2344,13 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256(float %x, i2 ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32 -; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float -; CHECK-NEXT: ret float [[TMP5]] +; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]]) +; CHECK-NEXT: ret float [[__POW_SIGN1]] ; %y.cast = uitofp i256 %y to float %pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast) @@ -2369,14 +2366,13 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256(float %x, i2 ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32 -; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float -; CHECK-NEXT: ret float [[TMP5]] +; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]]) +; CHECK-NEXT: ret float [[__POW_SIGN1]] ; %y.cast = sitofp i256 %y to float %pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast) @@ -2392,14 +2388,13 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp(<2 x floa ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float> ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 31) ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32> ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float> -; CHECK-NEXT: ret <2 x float> [[TMP5]] +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float> +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP3]]) +; CHECK-NEXT: ret <2 x float> [[__POW_SIGN1]] ; %y.cast = sitofp <2 x i32> %y to <2 x float> %pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y.cast) @@ -2441,14 +2436,13 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp(<2 x floa ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float> ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 31) ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32> ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP4]] to <2 x float> -; CHECK-NEXT: ret <2 x float> [[TMP5]] +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float> +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP3]]) +; CHECK-NEXT: ret <2 x float> [[__POW_SIGN1]] ; %y.cast = uitofp <2 x i32> %y to <2 x float> %pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y.cast) @@ -2468,6 +2462,20 @@ define float @test_pow_f32_known_positive_x__known_integral_sitofp(float nofpcla ret float %pow } +define float @test_pow_f32__known_positive_x__known_integral_y(float nofpclass(ninf nnorm nsub nzero) %x, i32 %y.int) #0 { +; CHECK-LABEL: define float @test_pow_f32__known_positive_x__known_integral_y +; CHECK-SAME: (float nofpclass(ninf nzero nsub nnorm) [[X:%.*]], i32 [[Y_INT:%.*]]) #[[ATTR2]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[Y:%.*]] = sitofp i32 [[Y_INT]] to float +; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]]) +; CHECK-NEXT: ret float [[CALL]] +; +entry: + %y = sitofp i32 %y.int to float + %call = tail call float @_Z3powff(float %x, float %y) + ret float %call +} + define float @test_pow_afn_f32_known_positive_x__known_integral_sitofp(float nofpclass(ninf nsub nnorm) %x, i32 %y) { ; CHECK-LABEL: define float @test_pow_afn_f32_known_positive_x__known_integral_sitofp ; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) { @@ -2486,7 +2494,7 @@ define float @test_pow_afn_nnan_ninf_f32__known_positive_x__known_integral_sitof ; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: ret float [[__EXP2]] ; %y.cast = sitofp i32 %y to float @@ -2553,14 +2561,13 @@ define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc(float %x, float ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[__EXP2]] to i32 -; CHECK-NEXT: [[TMP4:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = bitcast i32 [[TMP4]] to float -; CHECK-NEXT: ret float [[TMP5]] +; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]]) +; CHECK-NEXT: ret float [[__POW_SIGN1]] ; %y = call float @llvm.trunc.f32(float %y.arg) %pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll index 27d204c1a253f..2f0db29fc763b 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll @@ -673,14 +673,13 @@ define float @test_pown_afn_nnan_ninf_f32(float %x, i32 %y) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 31 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float -; CHECK-NEXT: ret float [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[__POW_SIGN]] to float +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP1]]) +; CHECK-NEXT: ret float [[__POW_SIGN1]] ; entry: %call = tail call nnan ninf afn float @_Z4pownfi(float %x, i32 %y) @@ -695,14 +694,13 @@ define <2 x float> @test_pown_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y) ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float> ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[Y]], splat (i32 31) ; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[X]] to <2 x i32> ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[__EXP2]] to <2 x i32> -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i32> [[__POW_SIGN]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float> -; CHECK-NEXT: ret <2 x float> [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float> +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP1]]) +; CHECK-NEXT: ret <2 x float> [[__POW_SIGN1]] ; entry: %call = tail call nnan ninf afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y) @@ -717,15 +715,14 @@ define double @test_pown_afn_nnan_ninf_f64(double %x, i32 %y) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn double @_Z4log2d(double [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to double ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn double [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn double @_Z4exp2d(double [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) double @_Z4exp2d(double [[__YLOGX]]) ; CHECK-NEXT: [[__YTOU:%.*]] = zext i32 [[Y]] to i64 ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i64 [[__YTOU]], 63 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[X]] to i64 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i64 [[__YEVEN]], [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[__EXP2]] to i64 -; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[__POW_SIGN]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[TMP2]] to double -; CHECK-NEXT: ret double [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[__POW_SIGN]] to double +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn double @llvm.copysign.f64(double [[__EXP2]], double [[TMP1]]) +; CHECK-NEXT: ret double [[__POW_SIGN1]] ; entry: %call = tail call nnan ninf afn double @_Z4powndi(double %x, i32 %y) @@ -740,15 +737,14 @@ define <2 x double> @test_pown_afn_nnan_ninf_v2f64(<2 x double> %x, <2 x i32> %y ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x double> @_Z4log2Dv2_d(<2 x double> [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x double> ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x double> [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]]) ; CHECK-NEXT: [[__YTOU:%.*]] = zext <2 x i32> [[Y]] to <2 x i64> ; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i64> [[__YTOU]], splat (i64 63) ; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[X]] to <2 x i64> ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i64> [[__YEVEN]], [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[__EXP2]] to <2 x i64> -; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[__POW_SIGN]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to <2 x double> -; CHECK-NEXT: ret <2 x double> [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[__POW_SIGN]] to <2 x double> +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x double> @llvm.copysign.v2f64(<2 x double> [[__EXP2]], <2 x double> [[TMP1]]) +; CHECK-NEXT: ret <2 x double> [[__POW_SIGN1]] ; entry: %call = tail call nnan ninf afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y) @@ -763,15 +759,14 @@ define half @test_pown_afn_nnan_ninf_f16(half %x, i32 %y) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn half @llvm.log2.f16(half [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to half ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn half [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn half @llvm.exp2.f16(half [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) half @llvm.exp2.f16(half [[__YLOGX]]) ; CHECK-NEXT: [[__YTOU:%.*]] = trunc i32 [[Y]] to i16 ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i16 [[__YTOU]], 15 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i16 [[__YEVEN]], [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[__EXP2]] to i16 -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i16 [[__POW_SIGN]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast i16 [[TMP2]] to half -; CHECK-NEXT: ret half [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i16 [[__POW_SIGN]] to half +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn half @llvm.copysign.f16(half [[__EXP2]], half [[TMP1]]) +; CHECK-NEXT: ret half [[__POW_SIGN1]] ; entry: %call = tail call nnan ninf afn half @_Z4pownDhi(half %x, i32 %y) @@ -786,15 +781,14 @@ define <2 x half> @test_pown_afn_nnan_ninf_v2f16(<2 x half> %x, <2 x i32> %y) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x half> @llvm.log2.v2f16(<2 x half> [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x half> ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x half> [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x half> @llvm.exp2.v2f16(<2 x half> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x half> @llvm.exp2.v2f16(<2 x half> [[__YLOGX]]) ; CHECK-NEXT: [[__YTOU:%.*]] = trunc <2 x i32> [[Y]] to <2 x i16> ; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i16> [[__YTOU]], splat (i16 15) ; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x half> [[X]] to <2 x i16> ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i16> [[__YEVEN]], [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x half> [[__EXP2]] to <2 x i16> -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint <2 x i16> [[__POW_SIGN]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to <2 x half> -; CHECK-NEXT: ret <2 x half> [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[__POW_SIGN]] to <2 x half> +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x half> @llvm.copysign.v2f16(<2 x half> [[__EXP2]], <2 x half> [[TMP1]]) +; CHECK-NEXT: ret <2 x half> [[__POW_SIGN1]] ; entry: %call = tail call nnan ninf afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y) @@ -821,14 +815,13 @@ define float @test_pown_fast_f32_strictfp(float %x, i32 %y) #1 { ; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]]) #[[ATTR0]] ; CHECK-NEXT: [[POWNI2F:%.*]] = call fast float @llvm.experimental.constrained.sitofp.f32.i32(i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]] ; CHECK-NEXT: [[__YLOGX:%.*]] = call fast float @llvm.experimental.constrained.fmul.f32(float [[POWNI2F]], float [[__LOG2]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]] -; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]]) #[[ATTR0]] +; CHECK-NEXT: [[__EXP2:%.*]] = call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) #[[ATTR0]] ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 31 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float -; CHECK-NEXT: ret float [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[__POW_SIGN]] to float +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call fast float @llvm.copysign.f32(float [[__EXP2]], float [[TMP1]]) #[[ATTR0]] +; CHECK-NEXT: ret float [[__POW_SIGN1]] ; entry: %call = tail call fast float @_Z4pownfi(float %x, i32 %y) #1 @@ -1067,14 +1060,13 @@ define float @test_pown_afn_ninf_nnan_f32__x_known_positive(float nofpclass(ninf ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[Y]], 31 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[X]] to i32 ; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[__EXP2]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[__POW_SIGN]], [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float -; CHECK-NEXT: ret float [[TMP3]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[__POW_SIGN]] to float +; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP1]]) +; CHECK-NEXT: ret float [[__POW_SIGN1]] ; entry: %call = tail call afn ninf nnan float @_Z4pownfi(float %x, i32 %y) @@ -1128,7 +1120,7 @@ define float @test_fast_pown_f32_y_known_even(float %x, i32 %y.arg) { ; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: ret float [[__EXP2]] ; entry: @@ -1146,7 +1138,7 @@ define float @test_fast_pown_f32_known_positive_y_known_even(float nofpclass(nin ; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[__FABS]]) ; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to float ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[__LOG2]], [[POWNI2F]] -; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: ret float [[__EXP2]] ; entry: diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll index 47ad3b1bbb7b3..6c4dd9dccbd4f 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll @@ -25,7 +25,7 @@ define float @test_powr_fast_f32(float %x, float %y) { ; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call fast float @llvm.log2.f32(float [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast float [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call fast float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: ret float [[__EXP2]] ; %powr = tail call fast float @_Z4powrff(float %x, float %y) @@ -37,7 +37,7 @@ define <2 x float> @test_powr_fast_v2f32(<2 x float> %x, <2 x float> %y) { ; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call fast <2 x float> @llvm.log2.v2f32(<2 x float> [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul fast <2 x float> [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call fast <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call fast nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) ; CHECK-NEXT: ret <2 x float> [[__EXP2]] ; %powr = tail call fast <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y) @@ -1010,7 +1010,7 @@ define float @test_powr_afn_f32_nnan_ninf_x_known_positive(float nofpclass(ninf ; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: ret float [[__EXP2]] ; %powr = tail call afn nnan ninf float @_Z4powrff(float %x, float %y) @@ -1032,7 +1032,7 @@ define <2 x float> @test_powr_afn_v2f32_nnan_ninf_x_known_positive(<2 x float> n ; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) { ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[Y]], [[__LOG2]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) ; CHECK-NEXT: ret <2 x float> [[__EXP2]] ; %powr = tail call afn nnan ninf <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y) @@ -1109,7 +1109,7 @@ define float @test_powr_afn_nnan_ninf_f32_known_integral_sitofp(float %x, i32 %y ; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: ret float [[__EXP2]] ; %y.cast = sitofp i32 %y to float @@ -1147,7 +1147,7 @@ define float @test_powr_afn_nnan_ninf_f32_known_integral_uitofp(float %x, i32 %y ; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]]) ; CHECK-NEXT: ret float [[__EXP2]] ; %y.cast = uitofp i32 %y to float @@ -1161,7 +1161,7 @@ define <2 x float> @test_powr_afn_nnan_ninf_v2f32_known_integral_sitofp(<2 x flo ; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float> ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[Y_CAST]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) ; CHECK-NEXT: ret <2 x float> [[__EXP2]] ; %y.cast = sitofp <2 x i32> %y to <2 x float> @@ -1199,7 +1199,7 @@ define <2 x float> @test_powr_afn_nnan_ninf_v2f32_known_integral_uitofp(<2 x flo ; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float> ; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]]) ; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[Y_CAST]] -; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) +; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]]) ; CHECK-NEXT: ret <2 x float> [[__EXP2]] ; %y.cast = uitofp <2 x i32> %y to <2 x float> diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll index e16c94cc0c458..b77a3a4c3f504 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll @@ -66,7 +66,7 @@ define amdgpu_vs half @vs_amdpal(half %arg0) #0 { ret half %add } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } ; amdgpu.pal.metadata.msgpack represents this: ; diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll index f52a33c7c0f8d..6f9ab39462c43 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll @@ -2596,11 +2596,11 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1164_ITERATIVE-NEXT: v_add_co_u32 v0, vcc, s2, v0 +; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1 ; GFX1164_ITERATIVE-NEXT: v_add_co_ci_u32_e64 v1, null, s3, v1, vcc ; GFX1164_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1 ; GFX1164_ITERATIVE-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 ; GFX1164_ITERATIVE-NEXT: s_endpgm ; @@ -3143,15 +3143,15 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1164_DPP: ; %bb.0: ; %entry ; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0 -; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) @@ -5853,9 +5853,9 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1164-NEXT: v_subrev_co_ci_u32_e64 v6, null, 0, v8, vcc ; GFX1164-NEXT: v_mov_b32_e32 v0, v5 ; GFX1164-NEXT: v_mov_b32_e32 v2, v7 -; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX1164-NEXT: v_mov_b32_e32 v1, v6 ; GFX1164-NEXT: v_mov_b32_e32 v3, v8 +; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX1164-NEXT: v_mov_b32_e32 v1, v6 ; GFX1164-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc ; GFX1164-NEXT: s_waitcnt vmcnt(0) ; GFX1164-NEXT: buffer_gl1_inv @@ -5876,11 +5876,11 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace ; GFX1164-NEXT: v_mul_u32_u24_e32 v0, 5, v4 ; GFX1164-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1164-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v4 -; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX1164-NEXT: v_sub_co_u32 v0, vcc, s2, v0 +; GFX1164-NEXT: s_mov_b32 s2, -1 ; GFX1164-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc ; GFX1164-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1164-NEXT: s_mov_b32 s2, -1 ; GFX1164-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 ; GFX1164-NEXT: s_endpgm ; @@ -6381,9 +6381,9 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX1164-NEXT: v_subrev_co_ci_u32_e64 v6, null, s15, v8, vcc ; GFX1164-NEXT: v_mov_b32_e32 v0, v5 ; GFX1164-NEXT: v_mov_b32_e32 v2, v7 -; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX1164-NEXT: v_mov_b32_e32 v1, v6 ; GFX1164-NEXT: v_mov_b32_e32 v3, v8 +; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX1164-NEXT: v_mov_b32_e32 v1, v6 ; GFX1164-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc ; GFX1164-NEXT: s_waitcnt vmcnt(0) ; GFX1164-NEXT: buffer_gl1_inv @@ -6981,9 +6981,9 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1164_ITERATIVE-NEXT: v_subrev_co_ci_u32_e64 v7, null, s9, v9, vcc ; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v0, v6 ; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v2, v8 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7 ; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v3, v9 +; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX1164_ITERATIVE-NEXT: v_mov_b32_e32 v1, v7 ; GFX1164_ITERATIVE-NEXT: buffer_atomic_cmpswap_b64 v[0:3], off, s[4:7], 0 glc ; GFX1164_ITERATIVE-NEXT: s_waitcnt vmcnt(0) ; GFX1164_ITERATIVE-NEXT: buffer_gl1_inv @@ -7003,10 +7003,9 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1164_ITERATIVE-NEXT: v_sub_co_u32 v0, vcc, s2, v4 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1 ; GFX1164_ITERATIVE-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v5, vcc ; GFX1164_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1 ; GFX1164_ITERATIVE-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 ; GFX1164_ITERATIVE-NEXT: s_endpgm ; @@ -7665,15 +7664,15 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace( ; GFX1164_DPP: ; %bb.0: ; %entry ; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0 -; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) @@ -12765,10 +12764,10 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs ; GFX1164-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164-TRUE16-NEXT: v_add_f32_e32 v0, s10, v0 +; GFX1164-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 ; GFX1164-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1 ; GFX1164-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v0 -; GFX1164-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff ; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GFX1164-TRUE16-NEXT: v_mov_b16_e32 v2.h, 0 @@ -12823,10 +12822,10 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs ; GFX1164-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164-FAKE16-NEXT: v_add_f32_e32 v0, s10, v0 +; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 ; GFX1164-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1 ; GFX1164-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v0 -; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164-FAKE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff ; GFX1164-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -13802,22 +13801,23 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add ; GFX1164-TRUE16-NEXT: v_add_f32_e32 v0, s11, v0 ; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164-TRUE16-NEXT: v_add_f32_e32 v2, s10, v2 +; GFX1164-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 ; GFX1164-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1 -; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX1164-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1 ; GFX1164-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 -; GFX1164-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX1164-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1 ; GFX1164-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2 ; GFX1164-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff +; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164-TRUE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff -; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc ; GFX1164-TRUE16-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 ; GFX1164-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vcc(0) +; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164-TRUE16-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc -; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1164-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.h ; GFX1164-TRUE16-NEXT: v_mov_b32_e32 v3, v1 +; GFX1164-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1164-TRUE16-NEXT: v_mov_b32_e32 v2, v0 ; GFX1164-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc ; GFX1164-TRUE16-NEXT: s_waitcnt vmcnt(0) @@ -13862,22 +13862,23 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add ; GFX1164-FAKE16-NEXT: v_add_f32_e32 v0, s12, v0 ; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164-FAKE16-NEXT: v_add_f32_e32 v2, s13, v2 +; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0 +; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_sdst(0) +; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 ; GFX1164-FAKE16-NEXT: v_bfe_u32 v3, v0, 16, 1 -; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1164-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1 ; GFX1164-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0 ; GFX1164-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v2 -; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 ; GFX1164-FAKE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff +; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164-FAKE16-NEXT: v_add3_u32 v4, v4, v2, 0x7fff -; GFX1164-FAKE16-NEXT: v_cmp_u_f32_e64 s[0:1], v0, v0 -; GFX1164-FAKE16-NEXT: s_waitcnt_depctr depctr_va_sdst(0) -; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1164-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX1164-FAKE16-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[0:1] -; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX1164-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x7060302 ; GFX1164-FAKE16-NEXT: v_mov_b32_e32 v3, v1 +; GFX1164-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1164-FAKE16-NEXT: v_mov_b32_e32 v2, v0 ; GFX1164-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], 0 glc ; GFX1164-FAKE16-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll index 785aee07a990e..b71577385606a 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll @@ -2222,11 +2222,11 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) { ; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1164_ITERATIVE-NEXT: v_add_co_u32 v0, vcc, s2, v0 +; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1 ; GFX1164_ITERATIVE-NEXT: v_add_co_ci_u32_e64 v1, null, s3, v1, vcc ; GFX1164_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1 ; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164_ITERATIVE-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 ; GFX1164_ITERATIVE-NEXT: s_endpgm @@ -2629,57 +2629,56 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) { ; GFX1164_DPP: ; %bb.0: ; %entry ; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0 -; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0 ; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1 +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc ; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0 +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 31 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s2 ; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc ; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1] -; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -3285,15 +3284,15 @@ define amdgpu_kernel void @add_i64_varying_nouse() { ; GFX1164_DPP: ; %bb.0: ; %entry ; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0 -; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_xmask:1 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_xmask:1 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) @@ -5028,11 +5027,11 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out) { ; GFX1164-NEXT: v_mul_u32_u24_e32 v0, 5, v2 ; GFX1164-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1164-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2 -; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX1164-NEXT: v_sub_co_u32 v0, vcc, s2, v0 +; GFX1164-NEXT: s_mov_b32 s2, -1 ; GFX1164-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc ; GFX1164-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1164-NEXT: s_mov_b32 s2, -1 ; GFX1164-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 ; GFX1164-NEXT: s_endpgm @@ -5636,11 +5635,11 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) { ; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX1164_ITERATIVE-NEXT: v_sub_co_u32 v0, vcc, s2, v0 +; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1 ; GFX1164_ITERATIVE-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc ; GFX1164_ITERATIVE-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1164_ITERATIVE-NEXT: s_mov_b32 s2, -1 ; GFX1164_ITERATIVE-NEXT: s_waitcnt lgkmcnt(0) ; GFX1164_ITERATIVE-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0 ; GFX1164_ITERATIVE-NEXT: s_endpgm @@ -6043,57 +6042,56 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) { ; GFX1164_DPP: ; %bb.0: ; %entry ; GFX1164_DPP-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0 -; GFX1164_DPP-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1] ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0 ; GFX1164_DPP-NEXT: v_mov_b32_e32 v6, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v2, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_permlanex16_b32 v5, v2, -1, -1 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v5, 0 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_permlanex16_b32 v4, v1, -1, -1 +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc ; GFX1164_DPP-NEXT: v_mov_b32_e32 v3, 0 +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1164_DPP-NEXT: v_readlane_b32 s2, v1, 31 -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_mov_b32_e32 v4, s2 ; GFX1164_DPP-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf -; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX1164_DPP-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_va_vcc(0) +; GFX1164_DPP-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1164_DPP-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc ; GFX1164_DPP-NEXT: s_mov_b64 exec, s[0:1] -; GFX1164_DPP-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1164_DPP-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX1164_DPP-NEXT: s_or_saveexec_b64 s[0:1], -1 ; GFX1164_DPP-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) @@ -11059,11 +11057,11 @@ define amdgpu_kernel void @max_i64_constant(ptr addrspace(1) %out) { ; GFX1164-NEXT: buffer_gl0_inv ; GFX1164-NEXT: .LBB22_2: ; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1] -; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1164-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1164-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc ; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1164-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] ; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0) @@ -11423,10 +11421,9 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) { ; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv ; GFX1164_ITERATIVE-NEXT: .LBB23_4: ; GFX1164_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] ; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc ; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc @@ -12884,11 +12881,11 @@ define amdgpu_kernel void @min_i64_constant(ptr addrspace(1) %out) { ; GFX1164-NEXT: buffer_gl0_inv ; GFX1164-NEXT: .LBB25_2: ; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1] -; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1164-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1164-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc ; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1164-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] ; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0) @@ -13248,10 +13245,9 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) { ; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv ; GFX1164_ITERATIVE-NEXT: .LBB26_4: ; GFX1164_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] ; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc ; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc @@ -14705,11 +14701,11 @@ define amdgpu_kernel void @umax_i64_constant(ptr addrspace(1) %out) { ; GFX1164-NEXT: buffer_gl0_inv ; GFX1164-NEXT: .LBB28_2: ; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1] -; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1164-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1164-NEXT: v_mov_b32_e32 v1, 0 ; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1164-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] ; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0) @@ -15063,10 +15059,9 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) { ; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv ; GFX1164_ITERATIVE-NEXT: .LBB29_4: ; GFX1164_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] ; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc ; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc @@ -16516,11 +16511,11 @@ define amdgpu_kernel void @umin_i64_constant(ptr addrspace(1) %out) { ; GFX1164-NEXT: buffer_gl0_inv ; GFX1164-NEXT: .LBB31_2: ; GFX1164-NEXT: s_or_b64 exec, exec, s[0:1] -; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164-NEXT: v_readfirstlane_b32 s3, v1 ; GFX1164-NEXT: v_readfirstlane_b32 s2, v0 ; GFX1164-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc ; GFX1164-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX1164-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1164-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX1164-NEXT: s_waitcnt_depctr depctr_va_vcc(0) @@ -16874,10 +16869,9 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) { ; GFX1164_ITERATIVE-NEXT: buffer_gl0_inv ; GFX1164_ITERATIVE-NEXT: .LBB32_4: ; GFX1164_ITERATIVE-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s3, v3 ; GFX1164_ITERATIVE-NEXT: v_readfirstlane_b32 s2, v2 -; GFX1164_ITERATIVE-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1164_ITERATIVE-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 ; GFX1164_ITERATIVE-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc ; GFX1164_ITERATIVE-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc diff --git a/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll b/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll index 18e2ae2919404..ae42404fd3818 100644 --- a/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll +++ b/llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll @@ -46,6 +46,7 @@ define float @syncscope_system(ptr %addr, float %val) #0 { ; GFX90A-NEXT: s_cbranch_execz .LBB0_3 ; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v3, v[0:1], v2, off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -84,6 +85,7 @@ define float @syncscope_system(ptr %addr, float %val) #0 { ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 diff --git a/llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll index 587157b5bc3af..232103a7035f4 100644 --- a/llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll +++ b/llvm/test/CodeGen/AMDGPU/atomics-hw-remarks-gfx90a.ll @@ -91,6 +91,6 @@ main_body: ret void } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(preservesign) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir b/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir index dfe4b8a33f396..9ce869ee08324 100644 --- a/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir +++ b/llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir @@ -70,9 +70,9 @@ body: | ; GFX908-PEI-NEXT: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 = IMPLICIT_DEF ; GFX908-PEI-NEXT: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 = IMPLICIT_DEF ; GFX908-PEI-NEXT: $vgpr40 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 - ; GFX908-PEI-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) + ; GFX908-PEI-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GFX908-PEI-NEXT: $vgpr40 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec - ; GFX908-PEI-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; GFX908-PEI-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; GFX908-PEI-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2 ; GFX908-PEI-NEXT: S_ENDPGM 0 ; @@ -86,9 +86,9 @@ body: | ; GFX908-PEI-MACHINECP-NEXT: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9 = IMPLICIT_DEF ; GFX908-PEI-MACHINECP-NEXT: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 = IMPLICIT_DEF ; GFX908-PEI-MACHINECP-NEXT: $vgpr40 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 - ; GFX908-PEI-MACHINECP-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) + ; GFX908-PEI-MACHINECP-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GFX908-PEI-MACHINECP-NEXT: $vgpr40 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec - ; GFX908-PEI-MACHINECP-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; GFX908-PEI-MACHINECP-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; GFX908-PEI-MACHINECP-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2 ; GFX908-PEI-MACHINECP-NEXT: S_ENDPGM 0 renamable $agpr0 = COPY renamable $vgpr0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir index a2ec87053a8d5..f945766d69cf0 100644 --- a/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir +++ b/llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir @@ -28,20 +28,20 @@ body: | ; GCN-NEXT: liveins: $sgpr30, $sgpr31, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $sgpr30_sgpr31 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) ; GCN-NEXT: renamable $vgpr44 = COPY $vgpr13, implicit $exec ; GCN-NEXT: renamable $vgpr43 = COPY $vgpr12, implicit $exec ; GCN-NEXT: S_CBRANCH_SCC1 %bb.2, implicit undef $scc @@ -64,17 +64,17 @@ body: | ; GCN-NEXT: renamable $sgpr16_sgpr17 = IMPLICIT_DEF ; GCN-NEXT: $vgpr40 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr40, implicit-def $sgpr30_sgpr31, implicit $sgpr30_sgpr31 ; GCN-NEXT: $vgpr40 = SI_SPILL_S32_TO_VGPR $sgpr31, 1, $vgpr40, implicit $sgpr30_sgpr31 - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15, implicit $vgpr14_vgpr15 :: (store (s32) into %stack.1, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec, implicit killed $vgpr14_vgpr15 :: (store (s32) into %stack.1 + 4, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit-def $vgpr10_vgpr11, implicit $vgpr10_vgpr11 :: (store (s32) into %stack.2, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec, implicit killed $vgpr10_vgpr11 :: (store (s32) into %stack.2 + 4, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15, implicit $vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec, implicit killed $vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit-def $vgpr10_vgpr11, implicit $vgpr10_vgpr11 :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec, implicit killed $vgpr10_vgpr11 :: ("amdgpu-thread-private" store (s32) into %stack.2 + 4, addrspace 5) ; GCN-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr16_sgpr17, 0, csr_amdgpu, implicit-def dead $vgpr0 - ; GCN-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15 :: (load (s32) from %stack.1, addrspace 5) - ; GCN-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) + ; GCN-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec, implicit-def $vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; GCN-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) ; GCN-NEXT: renamable $vgpr0_vgpr1 = nofpexcept V_FMA_F64_e64 0, killed $vgpr45_vgpr46, 0, killed $vgpr41_vgpr42, 0, killed $vgpr60_vgpr61, 0, 0, implicit $mode, implicit $exec ; GCN-NEXT: FLAT_STORE_DWORDX2 killed renamable $vgpr58_vgpr59, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64)) - ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.2, addrspace 5) - ; GCN-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.2 + 4, addrspace 5) + ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) + ; GCN-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2 + 4, addrspace 5) ; GCN-NEXT: FLAT_STORE_DWORDX2 killed renamable $vgpr0_vgpr1, killed renamable $vgpr56_vgpr57, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64)) ; GCN-NEXT: {{ $}} ; GCN-NEXT: bb.2: @@ -83,20 +83,20 @@ body: | ; GCN-NEXT: renamable $vgpr0_vgpr1 = V_MOV_B64_PSEUDO 0, implicit $exec ; GCN-NEXT: FLAT_STORE_DWORDX2 undef renamable $vgpr0_vgpr1, killed renamable $vgpr43_vgpr44, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64)) ; GCN-NEXT: FLAT_STORE_DWORDX2 killed renamable $vgpr0_vgpr1, killed renamable $vgpr14_vgpr15, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64)) - ; GCN-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GCN-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GCN-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GCN-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GCN-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GCN-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GCN-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GCN-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GCN-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GCN-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GCN-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GCN-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) + ; GCN-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GCN-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GCN-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GCN-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GCN-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GCN-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GCN-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GCN-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GCN-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GCN-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GCN-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GCN-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; GCN-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; GCN-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: S_SETPC_B64_return undef $sgpr30_sgpr31 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll index a5763816e58cc..94efba4014ec5 100644 --- a/llvm/test/CodeGen/AMDGPU/bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/bf16.ll @@ -3508,7 +3508,7 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s2, s33 ; GFX1250-NEXT: s_mov_b32 s33, s32 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_store_b32 off, v4, s33 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v4, s33 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_get_pc_i64 s[0:1] @@ -3526,7 +3526,7 @@ define void @test_call(bfloat %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_load_b32 v4, off, s33 ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v4, off, s33 nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_mov_b32 s33, s2 @@ -3752,7 +3752,7 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s2, s33 ; GFX1250-NEXT: s_mov_b32 s33, s32 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_store_b32 off, v4, s33 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v4, s33 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_get_pc_i64 s[0:1] @@ -3770,7 +3770,7 @@ define void @test_call_v2bf16(<2 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_load_b32 v4, off, s33 ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v4, off, s33 nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_mov_b32 s33, s2 @@ -4016,7 +4016,7 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s2, s33 ; GFX1250-NEXT: s_mov_b32 s33, s32 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v5, s33 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_get_pc_i64 s[0:1] @@ -4038,7 +4038,7 @@ define void @test_call_v3bf16(<3 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_load_b32 v5, off, s33 ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v5, off, s33 nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_mov_b32 s33, s2 @@ -4294,7 +4294,7 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s2, s33 ; GFX1250-NEXT: s_mov_b32 s33, s32 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v5, s33 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_get_pc_i64 s[0:1] @@ -4313,7 +4313,7 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_load_b32 v5, off, s33 ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v5, off, s33 nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_mov_b32 s33, s2 @@ -4610,7 +4610,7 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s2, s33 ; GFX1250-NEXT: s_mov_b32 s33, s32 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_store_b32 off, v5, s33 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v5, s33 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_get_pc_i64 s[0:1] @@ -4628,7 +4628,7 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_load_b32 v5, off, s33 ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v5, off, s33 nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_mov_b32 s33, s2 @@ -5013,7 +5013,7 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s2, s33 ; GFX1250-NEXT: s_mov_b32 s33, s32 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_store_b32 off, v9, s33 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v9, s33 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_get_pc_i64 s[0:1] @@ -5034,7 +5034,7 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) { ; GFX1250-NEXT: s_mov_b32 s32, s33 ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-NEXT: scratch_load_b32 v9, off, s33 ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v9, off, s33 nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-NEXT: s_mov_b32 s33, s2 @@ -9585,29 +9585,14 @@ define bfloat @v_fadd_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250TRUE16-LABEL: v_fadd_bf16: -; GFX1250TRUE16: ; %bb.0: -; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l -; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v1, v2 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] -; -; GFX1250FAKE16-LABEL: v_fadd_bf16: -; GFX1250FAKE16: ; %bb.0: -; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] +; GFX1250-LABEL: v_fadd_bf16: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %op = fadd bfloat %a, %b ret bfloat %op } @@ -13747,26 +13732,15 @@ define bfloat @v_fadd_bf16_fpimm_0(bfloat %arg0) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250TRUE16-LABEL: v_fadd_bf16_fpimm_0: -; GFX1250TRUE16: ; %bb.0: -; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, 1.0, v1 -; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] -; -; GFX1250FAKE16-LABEL: v_fadd_bf16_fpimm_0: -; GFX1250FAKE16: ; %bb.0: -; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, 1.0, v0 -; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] +; GFX1250-LABEL: v_fadd_bf16_fpimm_0: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: s_mov_b32 s0, 1.0 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s0 op_sel_hi:[1,1,0] +; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %add = fadd bfloat %arg0, 1.0 ret bfloat %add } @@ -13870,26 +13844,15 @@ define bfloat @v_fadd_bf16_fpimm_1(bfloat %arg0) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250TRUE16-LABEL: v_fadd_bf16_fpimm_1: -; GFX1250TRUE16: ; %bb.0: -; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, 0x42280000, v1 -; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] -; -; GFX1250FAKE16-LABEL: v_fadd_bf16_fpimm_1: -; GFX1250FAKE16: ; %bb.0: -; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, 0x42280000, v0 -; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] +; GFX1250-LABEL: v_fadd_bf16_fpimm_1: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: s_mov_b32 s0, 0x42280000 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s0 op_sel_hi:[1,1,0] +; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %add = fadd bfloat %arg0, 42.0 ret bfloat %add } @@ -14002,29 +13965,14 @@ define bfloat @v_fsub_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250TRUE16-LABEL: v_fsub_bf16: -; GFX1250TRUE16: ; %bb.0: -; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l -; GFX1250TRUE16-NEXT: v_sub_f32_e32 v0, v1, v2 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] -; -; GFX1250FAKE16-LABEL: v_fsub_bf16: -; GFX1250FAKE16: ; %bb.0: -; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] +; GFX1250-LABEL: v_fsub_bf16: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %op = fsub bfloat %a, %b ret bfloat %op } @@ -14424,14 +14372,10 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) { ; GFX1250TRUE16: ; %bb.0: ; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v3, 16, v3 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1250TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2 -; GFX1250TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250TRUE16-NEXT: v_sub_f32_e32 v1, v1, v3 -; GFX1250TRUE16-NEXT: v_dual_sub_f32 v3, v5, v4 :: v_dual_sub_f32 v0, v0, v2 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v1, v3, -1.0, v1 op_sel_hi:[1,1,1] +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v3, v2, -1.0, v0 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v2, -1.0, v0 op_sel_hi:[1,1,1] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 ; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v3 ; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] @@ -14440,14 +14384,10 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) { ; GFX1250FAKE16: ; %bb.0: ; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX1250FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2 -; GFX1250FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_dual_sub_f32 v4, v5, v4 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1250FAKE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_sub_f32 v1, v1, v3 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v2, -1.0, v0 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v2, -1.0, v0 op_sel_hi:[1,1,1] +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v1, v3, -1.0, v1 op_sel_hi:[1,1,1] +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v4 ; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 ; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] @@ -14730,17 +14670,11 @@ define <4 x bfloat> @v_fsub_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) { ; GFX1250: ; %bb.0: ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_and_b32_e32 v4, 0xffff0000, v3 -; GFX1250-NEXT: v_and_b32_e32 v5, 0xffff0000, v1 -; GFX1250-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX1250-NEXT: v_and_b32_e32 v6, 0xffff0000, v2 -; GFX1250-NEXT: v_and_b32_e32 v7, 0xffff0000, v0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: v_dual_sub_f32 v4, v5, v4 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_sub_f32_e32 v5, v7, v6 -; GFX1250-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_sub_f32 v1, v1, v3 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250-NEXT: v_fma_mix_f32_bf16 v4, v3, -1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1250-NEXT: v_fma_mix_f32_bf16 v5, v2, -1.0, v0 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v2, -1.0, v0 op_sel_hi:[1,1,1] +; GFX1250-NEXT: v_fma_mix_f32_bf16 v1, v3, -1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v5 ; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v1, v4 ; GFX1250-NEXT: s_set_pc_i64 s[30:31] @@ -14860,12 +14794,7 @@ define bfloat @v_fmul_bf16(bfloat %a, bfloat %b) { ; GFX1250TRUE16: ; %bb.0: ; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l -; GFX1250TRUE16-NEXT: v_mul_f32_e32 v0, v1, v2 +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 ; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] @@ -30732,30 +30661,32 @@ define bfloat @v_exp_bf16(bfloat %a) { ; GFX1250TRUE16: ; %bb.0: ; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l ; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x3fb8aa3b -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250TRUE16-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v1 -; GFX1250TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1 -; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v3, v0, s0, -v2 op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v2, v1, s0, neg(0) op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v3, v1, s0, -v2 op_sel_hi:[1,0,0] ; GFX1250TRUE16-NEXT: v_rndne_f32_e32 v4, v2 ; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x32a5705f ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) -; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v3 op_sel_hi:[1,0,0] -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v1, v1, s0, v3 op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4 -; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v3.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l +; GFX1250TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_add_f32_e32 v1, v2, v1 ; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v4 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) -; GFX1250TRUE16-NEXT: v_exp_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_exp_f32_e32 v1, v1 ; GFX1250TRUE16-NEXT: v_nop -; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v0, v2 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v1, v2 ; GFX1250TRUE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo -; GFX1250TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1 +; GFX1250TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 ; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] ; @@ -30763,28 +30694,29 @@ define bfloat @v_exp_bf16(bfloat %a) { ; GFX1250FAKE16: ; %bb.0: ; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x3fb8aa3b -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v1 -; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v3, v2 -; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v0, s0, -v2 op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v1, v0, s0, neg(0) op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v2, v1 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v3, v0, s0, -v1 op_sel_hi:[1,0,0] ; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x32a5705f ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3 -; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v4 op_sel_hi:[1,0,0] -; GFX1250FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v2, v0 -; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v3 -; GFX1250FAKE16-NEXT: v_exp_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_sub_f32_e32 v1, v1, v2 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v3, v0, s0, v3 op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v1, v1, v3 +; GFX1250FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250FAKE16-NEXT: v_exp_f32_e32 v1, v1 ; GFX1250FAKE16-NEXT: v_nop -; GFX1250FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v2 -; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo -; GFX1250FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo +; GFX1250FAKE16-NEXT: v_ldexp_f32 v1, v1, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 ; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.exp.bf16(bfloat %a) @@ -31202,30 +31134,32 @@ define bfloat @v_exp10_bf16(bfloat %a) { ; GFX1250TRUE16: ; %bb.0: ; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 -; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l ; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x40549a78 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250TRUE16-NEXT: v_mul_f32_e32 v2, 0x40549a78, v1 -; GFX1250TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v1 -; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v3, v0, s0, -v2 op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v2, v1, s0, neg(0) op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v3, v1, s0, -v2 op_sel_hi:[1,0,0] ; GFX1250TRUE16-NEXT: v_rndne_f32_e32 v4, v2 ; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x33979a37 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) -; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v3 op_sel_hi:[1,0,0] -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v1, v1, s0, v3 op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4 -; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v3.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l +; GFX1250TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_add_f32_e32 v1, v2, v1 ; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v4 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) -; GFX1250TRUE16-NEXT: v_exp_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_exp_f32_e32 v1, v1 ; GFX1250TRUE16-NEXT: v_nop -; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v0, v2 -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v1, v2 ; GFX1250TRUE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo -; GFX1250TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v1 +; GFX1250TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo -; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 ; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] ; @@ -31233,28 +31167,29 @@ define bfloat @v_exp10_bf16(bfloat %a) { ; GFX1250FAKE16: ; %bb.0: ; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x40549a78 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_mul_f32_e32 v2, 0x40549a78, v1 -; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v3, v2 -; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v0, s0, -v2 op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v1, v0, s0, neg(0) op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v2, v1 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v3, v0, s0, -v1 op_sel_hi:[1,0,0] ; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x33979a37 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3 -; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v4 op_sel_hi:[1,0,0] -; GFX1250FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v1 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v2, v0 -; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v3 -; GFX1250FAKE16-NEXT: v_exp_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_sub_f32_e32 v1, v1, v2 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v3, v0, s0, v3 op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v1, v1, v3 +; GFX1250FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250FAKE16-NEXT: v_exp_f32_e32 v1, v1 ; GFX1250FAKE16-NEXT: v_nop -; GFX1250FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v2 -; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo -; GFX1250FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v1 -; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo +; GFX1250FAKE16-NEXT: v_ldexp_f32 v1, v1, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v1, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 ; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.exp10.bf16(bfloat %a) @@ -31919,14 +31854,14 @@ define bfloat @v_round_bf16(bfloat %a) { ; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 ; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_trunc_f32_e32 v0, v1 -; GFX1250TRUE16-NEXT: v_sub_f32_e32 v2, v1, v0 +; GFX1250TRUE16-NEXT: v_trunc_f32_e32 v2, v1 +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5 -; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0 +; GFX1250TRUE16-NEXT: v_cmp_ge_f32_e64 s0, |v0|, 0.5 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v2, v1 -; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX1250TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1 +; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 ; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] @@ -31935,16 +31870,16 @@ define bfloat @v_round_bf16(bfloat %a) { ; GFX1250FAKE16: ; %bb.0: ; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_trunc_f32_e32 v1, v0 -; GFX1250FAKE16-NEXT: v_sub_f32_e32 v2, v0, v1 +; GFX1250FAKE16-NEXT: v_trunc_f32_e32 v2, v1 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5 -; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0 +; GFX1250FAKE16-NEXT: v_cmp_ge_f32_e64 s0, |v0|, 0.5 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s0 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0 -; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v1, v0 +; GFX1250FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v1 +; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 ; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] diff --git a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll index 02d7b50e23b5d..f8b35e54e3bc0 100644 --- a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll @@ -71,21 +71,20 @@ define amdgpu_kernel void @br_cc_f16( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[8:11], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[8:11], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v2.l, v2.h +; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_2 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %one +; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6 +; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7 ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; GFX11-TRUE16-NEXT: .LBB0_2: ; %two +; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6 +; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7 ; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -180,22 +179,24 @@ define amdgpu_kernel void @br_cc_f16_imm_a( ; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 ; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800 ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, 0.5, v1.l ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB1_2 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %one -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0x3800 -; GFX11-TRUE16-NEXT: .LBB1_2: ; %two ; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6 ; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7 ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-TRUE16-NEXT: s_endpgm +; GFX11-TRUE16-NEXT: .LBB1_2: ; %two +; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6 +; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7 +; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: s_endpgm ; ; GFX11-FAKE16-LABEL: br_cc_f16_imm_a: ; GFX11-FAKE16: ; %bb.0: ; %entry @@ -283,18 +284,20 @@ define amdgpu_kernel void @br_cc_f16_imm_b( ; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 ; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 ; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800 ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[4:7], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, 0.5, v1.l -; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB2_2 -; GFX11-TRUE16-NEXT: ; %bb.1: ; %two -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0x3800 -; GFX11-TRUE16-NEXT: .LBB2_2: ; %one +; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB2_2 +; GFX11-TRUE16-NEXT: ; %bb.1: ; %one +; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6 +; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7 +; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: s_endpgm +; GFX11-TRUE16-NEXT: .LBB2_2: ; %two ; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6 ; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7 ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir index 34c0159dd3ddb..eacb9085e0a7a 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir +++ b/llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir @@ -35,7 +35,7 @@ body: | ; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $exec = S_NOT_B64 $exec, implicit-def dead $scc, implicit-def $vgpr2 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr0, 0, undef $vgpr2, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr1, 1, $vgpr2, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $sgpr0_sgpr1 = S_GETPC_B64 post-instr-symbol @@ -61,7 +61,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr2, 0, implicit-def $sgpr0_sgpr1 ; CHECK-NEXT: $sgpr1 = V_READLANE_B32 killed $vgpr2, 1 - ; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec = S_NOT_B64 $exec, implicit-def dead $scc, implicit killed $vgpr2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: @@ -77,7 +77,7 @@ body: | ; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $exec = S_NOT_B64 $exec, implicit-def dead $scc, implicit-def $vgpr2 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr0, 0, undef $vgpr2, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr1, 1, $vgpr2, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $sgpr0_sgpr1 = S_GETPC_B64 post-instr-symbol @@ -103,7 +103,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr2, 0, implicit-def $sgpr0_sgpr1 ; CHECK-NEXT: $sgpr1 = V_READLANE_B32 killed $vgpr2, 1 - ; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec = S_NOT_B64 $exec, implicit-def dead $scc, implicit killed $vgpr2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir b/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir index 4cf92b0127131..7aa9b4717fd60 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir +++ b/llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir @@ -36,7 +36,7 @@ body: | ; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr32, $sgpr33, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $exec = S_NOT_B64 $exec, implicit-def dead $scc, implicit-def $vgpr2 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr0, 0, undef $vgpr2, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr1, 1, $vgpr2, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $sgpr0_sgpr1 = S_GETPC_B64 post-instr-symbol @@ -62,7 +62,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr2, 0, implicit-def $sgpr0_sgpr1 ; CHECK-NEXT: $sgpr1 = V_READLANE_B32 killed $vgpr2, 1 - ; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec = S_NOT_B64 $exec, implicit-def dead $scc, implicit killed $vgpr2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: @@ -78,7 +78,7 @@ body: | ; CHECK-NEXT: liveins: $vcc_hi, $vcc_lo, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $sgpr20, $sgpr21, $sgpr22, $sgpr23, $sgpr24, $sgpr25, $sgpr26, $sgpr27, $sgpr28, $sgpr29, $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $sgpr38, $sgpr39, $sgpr40, $sgpr41, $sgpr42, $sgpr43, $sgpr44, $sgpr45, $sgpr46, $sgpr47, $sgpr48, $sgpr49, $sgpr50, $sgpr51, $sgpr52, $sgpr53, $sgpr54, $sgpr55, $sgpr56, $sgpr57, $sgpr58, $sgpr59, $sgpr60, $sgpr61, $sgpr62, $sgpr63, $sgpr64, $sgpr65, $sgpr66, $sgpr67, $sgpr68, $sgpr69, $sgpr70, $sgpr71, $sgpr72, $sgpr73, $sgpr74, $sgpr75, $sgpr76, $sgpr77, $sgpr78, $sgpr79, $sgpr80, $sgpr81, $sgpr82, $sgpr83, $sgpr84, $sgpr85, $sgpr86, $sgpr87, $sgpr88, $sgpr89, $sgpr90, $sgpr91, $sgpr92, $sgpr93, $sgpr94, $sgpr95, $sgpr96, $sgpr97, $sgpr98, $sgpr99, $sgpr100, $sgpr101, $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $exec = S_NOT_B64 $exec, implicit-def dead $scc, implicit-def $vgpr2 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr0, 0, undef $vgpr2, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $vgpr2 = V_WRITELANE_B32 $sgpr1, 1, $vgpr2, implicit $sgpr0_sgpr1 ; CHECK-NEXT: $sgpr0_sgpr1 = S_GETPC_B64 post-instr-symbol @@ -105,7 +105,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr0 = V_READLANE_B32 $vgpr2, 0, implicit-def $sgpr0_sgpr1 ; CHECK-NEXT: $sgpr1 = V_READLANE_B32 killed $vgpr2, 1 - ; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec = S_NOT_B64 $exec, implicit-def dead $scc, implicit killed $vgpr2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir new file mode 100644 index 0000000000000..ebc7253cf2027 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir @@ -0,0 +1,74 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -amdgpu-s-branch-bits=4 -run-pass branch-relaxation %s -o - | FileCheck %s + +# Test that getInstSizeInBytes correctly estimates S_MOV_B64 with 64-bit +# literal values on targets with 64-bit literal support (gfx1250). +# +# Values outside [0, 2^31-1] require 64-bit literal encoding, making the +# instruction 12 bytes (4-byte opcode + 8-byte literal) instead of 8 bytes +# (4-byte opcode + 4-byte literal). +# +# With -amdgpu-s-branch-bits=4, forward branches can reach at most +7 dwords. +# Three S_MOV_B64 with 64-bit literals = 3 * 12 = 36 bytes = 9 dwords, +# which exceeds the 7-dword limit, so the branch must be relaxed. +# +# Without the correct size estimation (8 bytes instead of 12), the total +# would be 3 * 8 = 24 bytes = 6 dwords, fitting within the limit, and +# relaxation would not occur. In a rare real-world scenario, this could lead to +# an assembler error where branch size exceeds simm16. + +# The branch is relaxed: the original S_CBRANCH_SCC0 is inverted to +# S_CBRANCH_SCC1 (skipping the long branch), and a new block (bb.3) is +# inserted with S_ADD_PC_I64 for the long branch. + +--- +name: s_mov_b64_64bit_literal_size +tracksRegLiveness: true +machineFunctionInfo: + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + stackPtrOffsetReg: '$sgpr32' +body: | + ; CHECK-LABEL: name: s_mov_b64_64bit_literal_size + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $sgpr8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: S_CMP_EQ_U32 $sgpr8, 0, implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sgpr4_sgpr5 = S_GETPC_B64 post-instr-symbol + ; CHECK-NEXT: $sgpr4 = S_ADD_U32 $sgpr4, target-flags() , implicit-def $scc + ; CHECK-NEXT: $sgpr5 = S_ADDC_U32 $sgpr5, target-flags() , implicit-def $scc, implicit $scc + ; CHECK-NEXT: S_SETPC_B64 $sgpr4_sgpr5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sgpr10_sgpr11 = S_MOV_B64 4294967295 + ; CHECK-NEXT: $sgpr12_sgpr13 = S_MOV_B64 2147483648 + ; CHECK-NEXT: $sgpr14_sgpr15 = S_MOV_B64 -17 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: S_ENDPGM 0 + bb.0: + liveins: $sgpr8 + S_CMP_EQ_U32 $sgpr8, 0, implicit-def $scc + S_CBRANCH_SCC0 %bb.2, implicit $scc + + bb.1: + ; S_MOV_B64 with values requiring 64-bit literal encoding (12 bytes each). + ; These values are outside the [0, 2^31-1] range where 32-bit literal + ; can be used, so they need 64-bit literal encoding on gfx1250. + ; 0xFFFFFFFF (4294967295) is in [2^31, 2^32-1]. + ; 0x80000000 (2147483648) is exactly 2^31. + ; -17 (0xFFFFFFFFFFFFFFEF) is a negative non-inline constant. + $sgpr10_sgpr11 = S_MOV_B64 4294967295 + $sgpr12_sgpr13 = S_MOV_B64 2147483648 + $sgpr14_sgpr15 = S_MOV_B64 -17 + + bb.2: + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll index 27308e82a3354..029512631b367 100644 --- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll +++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll @@ -35,6 +35,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_fine_g ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -219,6 +220,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f32__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], 0 offen offset:1024 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -402,6 +404,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__waterfall__amdgp ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: s_mov_b64 s[2:3], exec ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=1 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 ; GFX942-NEXT: v_readfirstlane_b32 s5, v1 @@ -790,6 +793,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_fine_g ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -990,6 +994,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f32__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], 0 offen offset:1024 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1183,6 +1188,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset(ptr addrspace(7) ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1400,6 +1406,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_remote ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1617,6 +1624,7 @@ define float @buffer_fat_ptr_agent_atomic_fadd_ret_f32__offset__amdgpu_no_remote ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1857,6 +1865,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2098,6 +2107,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2369,6 +2379,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__waterfall__amdg ; GFX942-NEXT: v_mov_b32_e32 v6, v5 ; GFX942-NEXT: s_mov_b64 s[2:3], exec ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 ; GFX942-NEXT: v_readfirstlane_b32 s5, v1 @@ -2847,6 +2858,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_remot ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3107,6 +3119,7 @@ define double @buffer_fat_ptr_agent_atomic_fadd_ret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3431,6 +3444,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr ; GFX942-NEXT: v_and_or_b32 v2, v3, s7, v2 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[4:5], v1, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3862,6 +3876,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_ ; GFX942-NEXT: v_and_or_b32 v2, v3, s7, v2 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[4:5], v1, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4371,6 +4386,7 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: v_mov_b64_e32 v[8:9], v[6:7] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB15_4: ; Parent Loop BB15_3 Depth=1 ; GFX942-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 @@ -5103,6 +5119,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__amdgpu_no_fine ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_lshrrev_b32_sdwa v0, s6, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_add_f32_e32 v0, v0, v5 ; GFX942-NEXT: v_bfe_u32 v2, v0, 16, 1 ; GFX942-NEXT: v_or_b32_e32 v3, 0x400000, v0 @@ -5620,6 +5637,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_bf16__offset__amdgpu_no_fine ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_lshrrev_b32_sdwa v0, s6, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_add_f32_e32 v0, v0, v3 ; GFX942-NEXT: v_bfe_u32 v4, v0, 16, 1 ; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v0 @@ -6220,7 +6238,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fadd_ret_bf16__offset__waterfall__amd ; GFX942-NEXT: v_or_b32_e32 v6, 0x400000, v4 ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v6, v7, v10, v4 @@ -6896,6 +6914,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__amdgpu_no ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7130,6 +7149,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2f16__offset__amdgpu_no_fin ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 offen offset:1024 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7360,6 +7380,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__waterfall ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: s_mov_b64 s[2:3], exec ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB21_1: ; =>This Inner Loop Header: Depth=1 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 ; GFX942-NEXT: v_readfirstlane_b32 s5, v1 @@ -7817,6 +7838,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset(ptr addrsp ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8067,6 +8089,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2f16__offset(ptr addrspace( ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 offen offset:1024 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8307,6 +8330,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fadd_ret_v2f16__offset__amdgpu_no ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8557,6 +8581,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2f16__offset__amdgpu_no_rem ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 offen offset:1024 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8825,6 +8850,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[4:5] ; GFX942-NEXT: v_perm_b32 v6, v1, v0, s9 @@ -9261,6 +9287,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5] ; GFX942-NEXT: v_perm_b32 v0, v5, v0, s9 @@ -9707,6 +9734,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__waterf ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc ; GFX942-NEXT: v_and_b32_e32 v7, 0xffff0000, v9 ; GFX942-NEXT: v_add_f32_e32 v7, v7, v5 @@ -10416,6 +10444,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset(ptr add ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[4:5] ; GFX942-NEXT: v_perm_b32 v6, v1, v0, s9 @@ -10852,6 +10881,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset(ptr addrspace ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5] ; GFX942-NEXT: v_perm_b32 v0, v5, v0, s9 @@ -11271,6 +11301,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fadd_ret_v2bf16__offset__amdgpu ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[4:5] ; GFX942-NEXT: v_perm_b32 v6, v1, v0, s9 @@ -11707,6 +11738,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_re ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5] ; GFX942-NEXT: v_perm_b32 v0, v5, v0, s9 @@ -12124,6 +12156,7 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_v2bf16__offset__amdgpu_no_fi ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5] ; GFX942-NEXT: v_perm_b32 v0, v5, v0, s9 @@ -12524,6 +12557,7 @@ define float @buffer_fat_ptr_system_atomic_fadd_ret_f32__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v1, s16 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_add_f32 v0, v1, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -12583,6 +12617,7 @@ define float @buffer_fat_ptr_system_atomic_fadd_ret_f32__offset__amdgpu_no_fine_ ; GFX90A-NEXT: v_add_f32_e32 v4, v5, v2 ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[4:5] op_sel:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll index 5b5fb8f3a1663..1b957444869e7 100644 --- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll +++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll @@ -47,6 +47,7 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__amdgpu_no_fine_g ; GFX942-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -216,6 +217,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f32__offset__amdgpu_no_fine_ ; GFX942-NEXT: v_max_f32_e32 v0, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[4:5], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -418,6 +420,7 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__waterfall__amdgp ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: v_mov_b64_e32 v[6:7], v[8:9] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1 ; GFX942-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 @@ -768,6 +771,7 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__amdgpu_no_remote ; GFX942-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1018,6 +1022,7 @@ define float @buffer_fat_ptr_agent_atomic_fmax_ret_f32__offset__amdgpu_no_fine_g ; GFX942-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1203,6 +1208,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1384,6 +1390,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1604,6 +1611,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__waterfall__amdg ; GFX942-NEXT: v_mov_b32_e32 v6, v5 ; GFX942-NEXT: s_mov_b64 s[2:3], exec ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 ; GFX942-NEXT: v_readfirstlane_b32 s5, v1 @@ -1984,6 +1992,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_remot ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2249,6 +2258,7 @@ define double @buffer_fat_ptr_agent_atomic_fmax_ret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2518,6 +2528,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr ; GFX942-NEXT: v_and_or_b32 v0, v1, s7, v0 ; GFX942-NEXT: v_mov_b64_e32 v[2:3], v[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[2:3], v4, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2970,6 +2981,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_ ; GFX942-NEXT: v_and_or_b32 v0, v1, s7, v0 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[4:5], v2, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3501,6 +3513,7 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[6:7] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1 ; GFX942-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 @@ -4247,6 +4260,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__amdgpu_no_fine ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_lshrrev_b32_sdwa v0, s6, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_max_f32_e32 v0, v0, v5 ; GFX942-NEXT: v_bfe_u32 v2, v0, 16, 1 ; GFX942-NEXT: v_or_b32_e32 v3, 0x400000, v0 @@ -4766,6 +4780,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_bf16__offset__amdgpu_no_fine ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_lshrrev_b32_sdwa v0, s6, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_max_f32_e32 v0, v0, v3 ; GFX942-NEXT: v_bfe_u32 v4, v0, 16, 1 ; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v0 @@ -5368,7 +5383,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmax_ret_bf16__offset__waterfall__amd ; GFX942-NEXT: v_or_b32_e32 v6, 0x400000, v4 ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v6, v7, v10, v4 @@ -6077,6 +6092,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__amdgpu_no ; GFX942-NEXT: v_mov_b32_e32 v5, v0 ; GFX942-NEXT: v_pk_max_f16 v0, v5, v5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_max_f16 v4, v0, v2 ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] @@ -6377,6 +6393,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2f16__offset__amdgpu_no_fin ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_max_f16 v0, v1, v1 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_max_f16 v0, v0, v2 ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[0:1] @@ -6720,6 +6737,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmax_ret_v2f16__offset__waterfall ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: v_pk_max_f16 v8, v6, v5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[6:7], v[8:9] ; GFX942-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1 ; GFX942-NEXT: ; => This Inner Loop Header: Depth=2 @@ -7345,6 +7363,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__amdgpu ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[4:5] ; GFX942-NEXT: v_perm_b32 v6, v1, v0, s9 @@ -7865,6 +7884,7 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_v2bf16__offset__amdgpu_no_fi ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5] ; GFX942-NEXT: v_perm_b32 v0, v5, v0, s9 @@ -8455,6 +8475,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmax_ret_v2bf16__offset__waterf ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc ; GFX942-NEXT: v_and_b32_e32 v7, 0xffff0000, v9 ; GFX942-NEXT: v_max_f32_e32 v7, v7, v5 @@ -9157,6 +9178,7 @@ define float @buffer_fat_ptr_system_atomic_fmax_ret_f32__offset__amdgpu_no_fine_ ; GFX942-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -9207,6 +9229,7 @@ define float @buffer_fat_ptr_system_atomic_fmax_ret_f32__offset__amdgpu_no_fine_ ; GFX90A-NEXT: v_max_f32_e32 v4, v0, v2 ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[4:5] op_sel:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll index c1c512b9c0a18..da140ac4bf59c 100644 --- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll +++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll @@ -47,6 +47,7 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__amdgpu_no_fine_g ; GFX942-NEXT: v_min_f32_e32 v4, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -216,6 +217,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f32__offset__amdgpu_no_fine_ ; GFX942-NEXT: v_min_f32_e32 v0, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[4:5], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -418,6 +420,7 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__waterfall__amdgp ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: v_mov_b64_e32 v[6:7], v[8:9] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB2_4: ; Parent Loop BB2_3 Depth=1 ; GFX942-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 @@ -768,6 +771,7 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__amdgpu_no_remote ; GFX942-NEXT: v_min_f32_e32 v4, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1018,6 +1022,7 @@ define float @buffer_fat_ptr_agent_atomic_fmin_ret_f32__offset__amdgpu_no_fine_g ; GFX942-NEXT: v_min_f32_e32 v4, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1203,6 +1208,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1384,6 +1390,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1604,6 +1611,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__waterfall__amdg ; GFX942-NEXT: v_mov_b32_e32 v6, v5 ; GFX942-NEXT: s_mov_b64 s[2:3], exec ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB7_1: ; =>This Inner Loop Header: Depth=1 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 ; GFX942-NEXT: v_readfirstlane_b32 s5, v1 @@ -1984,6 +1992,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_remot ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2249,6 +2258,7 @@ define double @buffer_fat_ptr_agent_atomic_fmin_ret_f64__offset__amdgpu_no_fine_ ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, s16 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 offen offset:2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2518,6 +2528,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr ; GFX942-NEXT: v_and_or_b32 v0, v1, s7, v0 ; GFX942-NEXT: v_mov_b64_e32 v[2:3], v[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[2:3], v4, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2970,6 +2981,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_ ; GFX942-NEXT: v_and_or_b32 v0, v1, s7, v0 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[4:5], v2, s[0:3], 0 offen sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3501,6 +3513,7 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[6:7] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: .LBB12_4: ; Parent Loop BB12_3 Depth=1 ; GFX942-NEXT: ; => This Inner Loop Header: Depth=2 ; GFX942-NEXT: v_readfirstlane_b32 s4, v0 @@ -4247,6 +4260,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__amdgpu_no_fine ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_lshrrev_b32_sdwa v0, s6, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_min_f32_e32 v0, v0, v5 ; GFX942-NEXT: v_bfe_u32 v2, v0, 16, 1 ; GFX942-NEXT: v_or_b32_e32 v3, 0x400000, v0 @@ -4766,6 +4780,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_bf16__offset__amdgpu_no_fine ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_lshrrev_b32_sdwa v0, s6, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_min_f32_e32 v0, v0, v3 ; GFX942-NEXT: v_bfe_u32 v4, v0, 16, 1 ; GFX942-NEXT: v_or_b32_e32 v5, 0x400000, v0 @@ -5368,7 +5383,7 @@ define bfloat @buffer_fat_ptr_agent_atomic_fmin_ret_bf16__offset__waterfall__amd ; GFX942-NEXT: v_or_b32_e32 v6, 0x400000, v4 ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v6, v7, v10, v4 @@ -6077,6 +6092,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__amdgpu_no ; GFX942-NEXT: v_mov_b32_e32 v5, v0 ; GFX942-NEXT: v_pk_max_f16 v0, v5, v5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_min_f16 v4, v0, v2 ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] @@ -6377,6 +6393,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2f16__offset__amdgpu_no_fin ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_max_f16 v0, v1, v1 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_min_f16 v0, v0, v2 ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_mov_b64_e32 v[4:5], v[0:1] @@ -6720,6 +6737,7 @@ define <2 x half> @buffer_fat_ptr_agent_atomic_fmin_ret_v2f16__offset__waterfall ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: v_pk_min_f16 v8, v6, v5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[6:7], v[8:9] ; GFX942-NEXT: .LBB18_4: ; Parent Loop BB18_3 Depth=1 ; GFX942-NEXT: ; => This Inner Loop Header: Depth=2 @@ -7345,6 +7363,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__amdgpu ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[4:5] ; GFX942-NEXT: v_perm_b32 v6, v1, v0, s9 @@ -7865,6 +7884,7 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_v2bf16__offset__amdgpu_no_fi ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 ; GFX942-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc ; GFX942-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[4:5] ; GFX942-NEXT: v_perm_b32 v0, v5, v0, s9 @@ -8455,6 +8475,7 @@ define <2 x bfloat> @buffer_fat_ptr_agent_atomic_fmin_ret_v2bf16__offset__waterf ; GFX942-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 ; GFX942-NEXT: s_mov_b64 s[8:9], exec ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc ; GFX942-NEXT: v_and_b32_e32 v7, 0xffff0000, v9 ; GFX942-NEXT: v_min_f32_e32 v7, v7, v5 @@ -9157,6 +9178,7 @@ define float @buffer_fat_ptr_system_atomic_fmin_ret_f32__offset__amdgpu_no_fine_ ; GFX942-NEXT: v_min_f32_e32 v4, v0, v2 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], v[4:5] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[0:3], 0 offen offset:1024 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -9207,6 +9229,7 @@ define float @buffer_fat_ptr_system_atomic_fmin_ret_f32__offset__amdgpu_no_fine_ ; GFX90A-NEXT: v_min_f32_e32 v4, v0, v2 ; GFX90A-NEXT: v_pk_mov_b32 v[0:1], v[4:5], v[4:5] op_sel:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_atomic_cmpswap v[0:1], v3, s[16:19], 0 offen offset:1024 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll index 867ec0488d199..5967d17c351ea 100644 --- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll +++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=SDAG %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select -global-isel-abort=2 < %s | FileCheck -check-prefix=GISEL %s ; Note: if you're adding tests here, also add them to ; lower-buffer-fat-pointers-contents-legalization.ll to verify the IR produced by @@ -173,6 +173,14 @@ define i128 @load_i128(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load i128, ptr addrspace(7) %p @@ -439,6 +447,14 @@ define <8 x i16> @load_v8i16(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <8 x i16>, ptr addrspace(7) %p @@ -477,6 +493,14 @@ define <2 x i64> @load_v2i64(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <2 x i64>, ptr addrspace(7) %p @@ -667,6 +691,14 @@ define <8 x half> @load_v8f16(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <8 x half>, ptr addrspace(7) %p @@ -1161,6 +1193,14 @@ define <2 x ptr addrspace(1)> @load_v2p1(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <2 x ptr addrspace(1)>, ptr addrspace(7) %p @@ -1199,6 +1239,10 @@ define <2 x ptr addrspace(5)> @load_v2p5(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx2 v[0:1], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <2 x ptr addrspace(5)>, ptr addrspace(7) %p @@ -1237,6 +1281,12 @@ define <3 x ptr addrspace(5)> @load_v3p5(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx3 v[0:2], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <3 x ptr addrspace(5)>, ptr addrspace(7) %p @@ -1275,6 +1325,14 @@ define <4 x ptr addrspace(5)> @load_v4p5(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <4 x ptr addrspace(5)>, ptr addrspace(7) %p @@ -1315,6 +1373,12 @@ define <6 x half> @load_v6f16(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx3 v[0:2], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <6 x half>, ptr addrspace(7) %p @@ -1612,7 +1676,24 @@ define <4 x ptr addrspace(1)> @load_v4p1(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: buffer_load_dwordx4 v[4:7], off, s[16:19], 0 offset:16 -; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: s_waitcnt vmcnt(1) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s8, v4 +; GISEL-NEXT: v_readfirstlane_b32 s9, v5 +; GISEL-NEXT: v_readfirstlane_b32 s10, v6 +; GISEL-NEXT: v_readfirstlane_b32 s11, v7 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 +; GISEL-NEXT: v_mov_b32_e32 v4, s8 +; GISEL-NEXT: v_mov_b32_e32 v5, s9 +; GISEL-NEXT: v_mov_b32_e32 v6, s10 +; GISEL-NEXT: v_mov_b32_e32 v7, s11 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <4 x ptr addrspace(1)>, ptr addrspace(7) %p @@ -1655,6 +1736,8 @@ define <1 x i16> @load_v1i16(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <1 x i16>, ptr addrspace(7) %p @@ -1692,8 +1775,11 @@ define <3 x i16> @load_v3i16(ptr addrspace(8) inreg %buf) { ; GISEL-LABEL: load_v3i16: ; GISEL: ; %bb.0: ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 ; GISEL-NEXT: buffer_load_ushort v1, off, s[16:19], 0 offset:4 +; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 +; GISEL-NEXT: s_waitcnt vmcnt(1) +; GISEL-NEXT: v_readfirstlane_b32 s4, v1 +; GISEL-NEXT: v_mov_b32_e32 v1, s4 ; GISEL-NEXT: s_waitcnt vmcnt(0) ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) @@ -1734,8 +1820,11 @@ define <5 x i16> @load_v5i16(ptr addrspace(8) inreg %buf) { ; GISEL-LABEL: load_v5i16: ; GISEL: ; %bb.0: ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: buffer_load_dwordx2 v[0:1], off, s[16:19], 0 ; GISEL-NEXT: buffer_load_ushort v2, off, s[16:19], 0 offset:8 +; GISEL-NEXT: buffer_load_dwordx2 v[0:1], off, s[16:19], 0 +; GISEL-NEXT: s_waitcnt vmcnt(1) +; GISEL-NEXT: v_readfirstlane_b32 s4, v2 +; GISEL-NEXT: v_mov_b32_e32 v2, s4 ; GISEL-NEXT: s_waitcnt vmcnt(0) ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) @@ -1777,6 +1866,12 @@ define <6 x i16> @load_v6i16(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx3 v[0:2], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <6 x i16>, ptr addrspace(7) %p @@ -1816,7 +1911,16 @@ define <7 x i16> @load_v7i16(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx3 v[0:2], off, s[16:19], 0 ; GISEL-NEXT: buffer_load_ushort v3, off, s[16:19], 0 offset:12 +; GISEL-NEXT: s_waitcnt vmcnt(1) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <7 x i16>, ptr addrspace(7) %p @@ -1858,7 +1962,18 @@ define <9 x i16> @load_v9i16(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: buffer_load_ushort v4, off, s[16:19], 0 offset:16 +; GISEL-NEXT: s_waitcnt vmcnt(1) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s8, v4 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 +; GISEL-NEXT: v_mov_b32_e32 v4, s8 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <9 x i16>, ptr addrspace(7) %p @@ -1942,7 +2057,9 @@ define <2 x i8> @load_v2i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s4, s4, 8 +; GISEL-NEXT: v_mov_b32_e32 v1, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <2 x i8>, ptr addrspace(7) %p @@ -1990,7 +2107,9 @@ define <3 x i8> @load_v3i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; GISEL-NEXT: buffer_load_ubyte v2, off, s[16:19], 0 offset:2 ; GISEL-NEXT: s_waitcnt vmcnt(1) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s4, s4, 8 +; GISEL-NEXT: v_mov_b32_e32 v1, s4 ; GISEL-NEXT: s_waitcnt vmcnt(0) ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) @@ -2040,9 +2159,13 @@ define <4 x i8> @load_v4i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s5, s4, 8 +; GISEL-NEXT: s_lshr_b32 s6, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <4 x i8>, ptr addrspace(7) %p @@ -2100,9 +2223,13 @@ define <5 x i8> @load_v5i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 ; GISEL-NEXT: buffer_load_ubyte v4, off, s[16:19], 0 offset:4 ; GISEL-NEXT: s_waitcnt vmcnt(1) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s5, s4, 8 +; GISEL-NEXT: s_lshr_b32 s6, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 ; GISEL-NEXT: s_waitcnt vmcnt(0) ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) @@ -2167,11 +2294,17 @@ define <6 x i8> @load_v6i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 ; GISEL-NEXT: buffer_load_ushort v4, off, s[16:19], 0 offset:4 ; GISEL-NEXT: s_waitcnt vmcnt(1) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v4 +; GISEL-NEXT: v_readfirstlane_b32 s5, v4 +; GISEL-NEXT: s_lshr_b32 s6, s4, 8 +; GISEL-NEXT: s_lshr_b32 s7, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: s_lshr_b32 s5, s5, 8 +; GISEL-NEXT: v_mov_b32_e32 v1, s6 +; GISEL-NEXT: v_mov_b32_e32 v2, s7 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 +; GISEL-NEXT: v_mov_b32_e32 v5, s5 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <6 x i8>, ptr addrspace(7) %p @@ -2238,11 +2371,17 @@ define <7 x i8> @load_v7i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: buffer_load_ushort v4, off, s[16:19], 0 offset:4 ; GISEL-NEXT: buffer_load_ubyte v6, off, s[16:19], 0 offset:6 ; GISEL-NEXT: s_waitcnt vmcnt(2) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 ; GISEL-NEXT: s_waitcnt vmcnt(1) -; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v4 +; GISEL-NEXT: v_readfirstlane_b32 s5, v4 +; GISEL-NEXT: s_lshr_b32 s6, s4, 8 +; GISEL-NEXT: s_lshr_b32 s7, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: s_lshr_b32 s5, s5, 8 +; GISEL-NEXT: v_mov_b32_e32 v1, s6 +; GISEL-NEXT: v_mov_b32_e32 v2, s7 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 +; GISEL-NEXT: v_mov_b32_e32 v5, s5 ; GISEL-NEXT: s_waitcnt vmcnt(0) ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) @@ -2311,14 +2450,21 @@ define <8 x i8> @load_v8i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx2 v[0:1], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v8, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v7, 24, v1 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: s_lshr_b32 s6, s4, 8 +; GISEL-NEXT: s_lshr_b32 s7, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: s_lshr_b32 s8, s5, 8 +; GISEL-NEXT: s_lshr_b32 s9, s5, 16 +; GISEL-NEXT: s_lshr_b32 s5, s5, 24 ; GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GISEL-NEXT: v_mov_b32_e32 v1, v8 +; GISEL-NEXT: v_mov_b32_e32 v1, s6 +; GISEL-NEXT: v_mov_b32_e32 v2, s7 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 +; GISEL-NEXT: v_mov_b32_e32 v5, s8 +; GISEL-NEXT: v_mov_b32_e32 v6, s9 +; GISEL-NEXT: v_mov_b32_e32 v7, s5 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <8 x i8>, ptr addrspace(7) %p @@ -2393,19 +2539,29 @@ define <12 x i8> @load_v12i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx3 v[0:2], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v13, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v12, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v7, 24, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v9, 8, v2 -; GISEL-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GISEL-NEXT: v_lshrrev_b32_e32 v11, 24, v2 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: s_lshr_b32 s7, s4, 8 +; GISEL-NEXT: s_lshr_b32 s8, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: s_lshr_b32 s9, s5, 8 +; GISEL-NEXT: s_lshr_b32 s10, s5, 16 +; GISEL-NEXT: s_lshr_b32 s5, s5, 24 +; GISEL-NEXT: s_lshr_b32 s11, s6, 8 +; GISEL-NEXT: s_lshr_b32 s12, s6, 16 +; GISEL-NEXT: s_lshr_b32 s6, s6, 24 ; GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GISEL-NEXT: v_mov_b32_e32 v8, v2 -; GISEL-NEXT: v_mov_b32_e32 v1, v13 -; GISEL-NEXT: v_mov_b32_e32 v2, v12 +; GISEL-NEXT: v_mov_b32_e32 v1, s7 +; GISEL-NEXT: v_mov_b32_e32 v2, s8 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 +; GISEL-NEXT: v_mov_b32_e32 v5, s9 +; GISEL-NEXT: v_mov_b32_e32 v6, s10 +; GISEL-NEXT: v_mov_b32_e32 v7, s5 +; GISEL-NEXT: v_mov_b32_e32 v9, s11 +; GISEL-NEXT: v_mov_b32_e32 v10, s12 +; GISEL-NEXT: v_mov_b32_e32 v11, s6 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <12 x i8>, ptr addrspace(7) %p @@ -2495,24 +2651,37 @@ define <16 x i8> @load_v16i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v16, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v17, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v18, 24, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v7, 24, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v9, 8, v2 -; GISEL-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GISEL-NEXT: v_lshrrev_b32_e32 v11, 24, v2 -; GISEL-NEXT: v_lshrrev_b32_e32 v13, 8, v3 -; GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v3 -; GISEL-NEXT: v_lshrrev_b32_e32 v15, 24, v3 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: s_lshr_b32 s8, s4, 8 +; GISEL-NEXT: s_lshr_b32 s9, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: s_lshr_b32 s10, s5, 8 +; GISEL-NEXT: s_lshr_b32 s11, s5, 16 +; GISEL-NEXT: s_lshr_b32 s5, s5, 24 +; GISEL-NEXT: s_lshr_b32 s12, s6, 8 +; GISEL-NEXT: s_lshr_b32 s13, s6, 16 +; GISEL-NEXT: s_lshr_b32 s6, s6, 24 +; GISEL-NEXT: s_lshr_b32 s14, s7, 8 +; GISEL-NEXT: s_lshr_b32 s15, s7, 16 +; GISEL-NEXT: s_lshr_b32 s7, s7, 24 ; GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GISEL-NEXT: v_mov_b32_e32 v8, v2 ; GISEL-NEXT: v_mov_b32_e32 v12, v3 -; GISEL-NEXT: v_mov_b32_e32 v1, v16 -; GISEL-NEXT: v_mov_b32_e32 v2, v17 -; GISEL-NEXT: v_mov_b32_e32 v3, v18 +; GISEL-NEXT: v_mov_b32_e32 v1, s8 +; GISEL-NEXT: v_mov_b32_e32 v2, s9 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 +; GISEL-NEXT: v_mov_b32_e32 v5, s10 +; GISEL-NEXT: v_mov_b32_e32 v6, s11 +; GISEL-NEXT: v_mov_b32_e32 v7, s5 +; GISEL-NEXT: v_mov_b32_e32 v9, s12 +; GISEL-NEXT: v_mov_b32_e32 v10, s13 +; GISEL-NEXT: v_mov_b32_e32 v11, s6 +; GISEL-NEXT: v_mov_b32_e32 v13, s14 +; GISEL-NEXT: v_mov_b32_e32 v14, s15 +; GISEL-NEXT: v_mov_b32_e32 v15, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <16 x i8>, ptr addrspace(7) %p @@ -2629,43 +2798,69 @@ define <32 x i8> @load_v32i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: buffer_load_dwordx4 v[16:19], off, s[16:19], 0 offset:16 ; GISEL-NEXT: s_waitcnt vmcnt(1) -; GISEL-NEXT: v_lshrrev_b32_e32 v35, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v36, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v37, 24, v0 -; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v32, 8, v16 -; GISEL-NEXT: v_lshrrev_b32_e32 v33, 16, v16 -; GISEL-NEXT: v_lshrrev_b32_e32 v34, 24, v16 -; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v7, 24, v1 -; GISEL-NEXT: v_lshrrev_b32_e32 v9, 8, v2 -; GISEL-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GISEL-NEXT: v_lshrrev_b32_e32 v11, 24, v2 -; GISEL-NEXT: v_lshrrev_b32_e32 v13, 8, v3 -; GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v3 -; GISEL-NEXT: v_lshrrev_b32_e32 v15, 24, v3 -; GISEL-NEXT: v_lshrrev_b32_e32 v21, 8, v17 -; GISEL-NEXT: v_lshrrev_b32_e32 v22, 16, v17 -; GISEL-NEXT: v_lshrrev_b32_e32 v23, 24, v17 -; GISEL-NEXT: v_lshrrev_b32_e32 v25, 8, v18 -; GISEL-NEXT: v_lshrrev_b32_e32 v26, 16, v18 -; GISEL-NEXT: v_lshrrev_b32_e32 v27, 24, v18 -; GISEL-NEXT: v_lshrrev_b32_e32 v29, 8, v19 -; GISEL-NEXT: v_lshrrev_b32_e32 v30, 16, v19 -; GISEL-NEXT: v_lshrrev_b32_e32 v31, 24, v19 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s8, v16 +; GISEL-NEXT: v_readfirstlane_b32 s9, v17 +; GISEL-NEXT: v_readfirstlane_b32 s10, v18 +; GISEL-NEXT: v_readfirstlane_b32 s11, v19 +; GISEL-NEXT: s_lshr_b32 s12, s4, 8 +; GISEL-NEXT: s_lshr_b32 s13, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: s_lshr_b32 s14, s5, 8 +; GISEL-NEXT: s_lshr_b32 s15, s5, 16 +; GISEL-NEXT: s_lshr_b32 s5, s5, 24 +; GISEL-NEXT: s_lshr_b32 s16, s6, 8 +; GISEL-NEXT: s_lshr_b32 s17, s6, 16 +; GISEL-NEXT: s_lshr_b32 s6, s6, 24 +; GISEL-NEXT: s_lshr_b32 s18, s7, 8 +; GISEL-NEXT: s_lshr_b32 s19, s7, 16 +; GISEL-NEXT: s_lshr_b32 s7, s7, 24 +; GISEL-NEXT: s_lshr_b32 s20, s8, 8 +; GISEL-NEXT: s_lshr_b32 s21, s8, 16 +; GISEL-NEXT: s_lshr_b32 s8, s8, 24 +; GISEL-NEXT: s_lshr_b32 s22, s9, 8 +; GISEL-NEXT: s_lshr_b32 s23, s9, 16 +; GISEL-NEXT: s_lshr_b32 s9, s9, 24 +; GISEL-NEXT: s_lshr_b32 s24, s10, 8 +; GISEL-NEXT: s_lshr_b32 s25, s10, 16 +; GISEL-NEXT: s_lshr_b32 s10, s10, 24 +; GISEL-NEXT: s_lshr_b32 s26, s11, 8 +; GISEL-NEXT: s_lshr_b32 s27, s11, 16 +; GISEL-NEXT: s_lshr_b32 s11, s11, 24 ; GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GISEL-NEXT: v_mov_b32_e32 v8, v2 ; GISEL-NEXT: v_mov_b32_e32 v12, v3 ; GISEL-NEXT: v_mov_b32_e32 v20, v17 ; GISEL-NEXT: v_mov_b32_e32 v24, v18 ; GISEL-NEXT: v_mov_b32_e32 v28, v19 -; GISEL-NEXT: v_mov_b32_e32 v1, v35 -; GISEL-NEXT: v_mov_b32_e32 v2, v36 -; GISEL-NEXT: v_mov_b32_e32 v3, v37 -; GISEL-NEXT: v_mov_b32_e32 v17, v32 -; GISEL-NEXT: v_mov_b32_e32 v18, v33 -; GISEL-NEXT: v_mov_b32_e32 v19, v34 +; GISEL-NEXT: v_mov_b32_e32 v1, s12 +; GISEL-NEXT: v_mov_b32_e32 v2, s13 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 +; GISEL-NEXT: v_mov_b32_e32 v5, s14 +; GISEL-NEXT: v_mov_b32_e32 v6, s15 +; GISEL-NEXT: v_mov_b32_e32 v7, s5 +; GISEL-NEXT: v_mov_b32_e32 v9, s16 +; GISEL-NEXT: v_mov_b32_e32 v10, s17 +; GISEL-NEXT: v_mov_b32_e32 v11, s6 +; GISEL-NEXT: v_mov_b32_e32 v13, s18 +; GISEL-NEXT: v_mov_b32_e32 v14, s19 +; GISEL-NEXT: v_mov_b32_e32 v15, s7 +; GISEL-NEXT: v_mov_b32_e32 v17, s20 +; GISEL-NEXT: v_mov_b32_e32 v18, s21 +; GISEL-NEXT: v_mov_b32_e32 v19, s8 +; GISEL-NEXT: v_mov_b32_e32 v21, s22 +; GISEL-NEXT: v_mov_b32_e32 v22, s23 +; GISEL-NEXT: v_mov_b32_e32 v23, s9 +; GISEL-NEXT: v_mov_b32_e32 v25, s24 +; GISEL-NEXT: v_mov_b32_e32 v26, s25 +; GISEL-NEXT: v_mov_b32_e32 v27, s10 +; GISEL-NEXT: v_mov_b32_e32 v29, s26 +; GISEL-NEXT: v_mov_b32_e32 v30, s27 +; GISEL-NEXT: v_mov_b32_e32 v31, s11 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <32 x i8>, ptr addrspace(7) %p @@ -2871,7 +3066,9 @@ define [2 x half] @load_a2f16(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s4, s4, 16 +; GISEL-NEXT: v_mov_b32_e32 v1, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load [2 x half], ptr addrspace(7) %p @@ -2914,6 +3111,14 @@ define [2 x ptr addrspace(1)] @load_a2p1(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_readfirstlane_b32 s7, v3 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load [2 x ptr addrspace(1)], ptr addrspace(7) %p @@ -2955,19 +3160,23 @@ define i40 @load_i40(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 ; GISEL-NEXT: buffer_load_ubyte v1, off, s[16:19], 0 offset:4 -; GISEL-NEXT: v_mov_b32_e32 v2, 0xff ; GISEL-NEXT: s_waitcnt vmcnt(1) -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v4, 24, v0 -; GISEL-NEXT: v_and_b32_e32 v3, 0xff, v3 -; GISEL-NEXT: v_and_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GISEL-NEXT: v_lshlrev_b16_e32 v4, 8, v4 -; GISEL-NEXT: v_lshlrev_b16_e32 v3, 8, v3 -; GISEL-NEXT: v_or_b32_e32 v2, v2, v4 -; GISEL-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s5, s4, 8 +; GISEL-NEXT: s_lshr_b32 s6, s4, 16 +; GISEL-NEXT: s_lshr_b32 s7, s4, 24 +; GISEL-NEXT: s_and_b32 s5, s5, 0xff +; GISEL-NEXT: s_and_b32 s6, s6, 0xff +; GISEL-NEXT: s_lshl_b32 s7, s7, 8 +; GISEL-NEXT: s_and_b32 s4, s4, 0xff +; GISEL-NEXT: s_lshl_b32 s5, s5, 8 +; GISEL-NEXT: s_or_b32 s6, s6, s7 +; GISEL-NEXT: s_or_b32 s4, s4, s5 +; GISEL-NEXT: s_and_b32 s5, 0xffff, s6 +; GISEL-NEXT: s_and_b32 s4, 0xffff, s4 +; GISEL-NEXT: s_lshl_b32 s5, s5, 16 +; GISEL-NEXT: s_or_b32 s4, s4, s5 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 ; GISEL-NEXT: s_waitcnt vmcnt(0) ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) @@ -3009,6 +3218,12 @@ define i96 @load_i96(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dwordx3 v[0:2], off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v1 +; GISEL-NEXT: v_readfirstlane_b32 s6, v2 +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load i96, ptr addrspace(7) %p @@ -3221,7 +3436,9 @@ define <2 x i4> @load_v2i4(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_ubyte v0, off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s4, s4, 4 +; GISEL-NEXT: v_mov_b32_e32 v1, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <2 x i4>, ptr addrspace(7) %p @@ -3279,9 +3496,13 @@ define <4 x i4> @load_v4i4(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 4, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 12, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s5, s4, 4 +; GISEL-NEXT: s_lshr_b32 s6, s4, 8 +; GISEL-NEXT: s_lshr_b32 s4, s4, 12 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <4 x i4>, ptr addrspace(7) %p @@ -3347,13 +3568,21 @@ define <8 x i4> @load_v8i4(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 4, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 12, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v5, 20, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v6, 24, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v7, 28, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s5, s4, 4 +; GISEL-NEXT: s_lshr_b32 s6, s4, 8 +; GISEL-NEXT: s_lshr_b32 s7, s4, 12 +; GISEL-NEXT: s_lshr_b32 s8, s4, 16 +; GISEL-NEXT: s_lshr_b32 s9, s4, 20 +; GISEL-NEXT: s_lshr_b32 s10, s4, 24 +; GISEL-NEXT: s_lshr_b32 s4, s4, 28 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 +; GISEL-NEXT: v_mov_b32_e32 v4, s8 +; GISEL-NEXT: v_mov_b32_e32 v5, s9 +; GISEL-NEXT: v_mov_b32_e32 v6, s10 +; GISEL-NEXT: v_mov_b32_e32 v7, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <8 x i4>, ptr addrspace(7) %p @@ -3429,7 +3658,10 @@ define <2 x i6> @load_v2i6(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b16_e32 v1, 6, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_and_b32 s4, 0xffff, s4 +; GISEL-NEXT: s_lshr_b32 s4, s4, 6 +; GISEL-NEXT: v_mov_b32_e32 v1, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load <2 x i6>, ptr addrspace(7) %p @@ -3528,9 +3760,13 @@ define <4 x i8> @volatile_load_v4i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 glc ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: s_lshr_b32 s5, s4, 8 +; GISEL-NEXT: s_lshr_b32 s6, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load volatile <4 x i8>, ptr addrspace(7) %p @@ -3593,10 +3829,16 @@ define <6 x i8> @volatile_load_v6i8(ptr addrspace(8) inreg %buf) { ; GISEL-NEXT: s_waitcnt vmcnt(0) ; GISEL-NEXT: buffer_load_ushort v4, off, s[16:19], 0 offset:4 glc ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0 -; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v4 +; GISEL-NEXT: v_readfirstlane_b32 s4, v0 +; GISEL-NEXT: v_readfirstlane_b32 s5, v4 +; GISEL-NEXT: s_lshr_b32 s6, s4, 8 +; GISEL-NEXT: s_lshr_b32 s7, s4, 16 +; GISEL-NEXT: s_lshr_b32 s4, s4, 24 +; GISEL-NEXT: s_lshr_b32 s5, s5, 8 +; GISEL-NEXT: v_mov_b32_e32 v1, s6 +; GISEL-NEXT: v_mov_b32_e32 v2, s7 +; GISEL-NEXT: v_mov_b32_e32 v3, s4 +; GISEL-NEXT: v_mov_b32_e32 v5, s5 ; GISEL-NEXT: s_setpc_b64 s[30:31] %p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7) %ret = load volatile <6 x i8>, ptr addrspace(7) %p diff --git a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir index 7336a54ae42db..0b043da201275 100644 --- a/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir @@ -21,9 +21,9 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: $vgpr63 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 -1 - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: renamable $vgpr62 = IMPLICIT_DEF ; GCN-NEXT: $vgpr62 = SI_SPILL_S32_TO_VGPR $sgpr15, 0, killed $vgpr62 @@ -59,10 +59,10 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: bb.4: ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GCN-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GCN-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec ; GCN-NEXT: $exec = S_MOV_B64 -1 - ; GCN-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; GCN-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: SI_RETURN bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll index d3881660bb846..293e24f2d1b9d 100644 --- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll +++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll @@ -5799,22 +5799,39 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 { ; SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5] ; SDAG-NEXT: s_endpgm ; -; GFX11-LABEL: test_call_external_void_func_struct_i8_i32: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 -; GFX11-NEXT: s_mov_b32 s7, 0x31016000 -; GFX11-NEXT: s_mov_b32 s6, -1 -; GFX11-NEXT: s_getpc_b64 s[2:3] -; GFX11-NEXT: s_add_u32 s2, s2, external_void_func_struct_i8_i32@rel32@lo+4 -; GFX11-NEXT: s_addc_u32 s3, s3, external_void_func_struct_i8_i32@rel32@hi+12 -; GFX11-NEXT: s_mov_b32 s32, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: buffer_load_u8 v0, off, s[4:7], 0 -; GFX11-NEXT: buffer_load_b32 v1, off, s[4:7], 0 offset:4 -; GFX11-NEXT: s_mov_b64 s[6:7], s[0:1] -; GFX11-NEXT: s_swappc_b64 s[30:31], s[2:3] -; GFX11-NEXT: s_endpgm +; GFX11-TRUE16-LABEL: test_call_external_void_func_struct_i8_i32: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 +; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX11-TRUE16-NEXT: s_getpc_b64 s[2:3] +; GFX11-TRUE16-NEXT: s_add_u32 s2, s2, external_void_func_struct_i8_i32@rel32@lo+4 +; GFX11-TRUE16-NEXT: s_addc_u32 s3, s3, external_void_func_struct_i8_i32@rel32@hi+12 +; GFX11-TRUE16-NEXT: s_mov_b32 s32, 0 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: buffer_load_d16_u8 v0, off, s[4:7], 0 +; GFX11-TRUE16-NEXT: buffer_load_b32 v1, off, s[4:7], 0 offset:4 +; GFX11-TRUE16-NEXT: s_mov_b64 s[6:7], s[0:1] +; GFX11-TRUE16-NEXT: s_swappc_b64 s[30:31], s[2:3] +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: test_call_external_void_func_struct_i8_i32: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[4:5], s[0:1], 0x0 +; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1 +; GFX11-FAKE16-NEXT: s_getpc_b64 s[2:3] +; GFX11-FAKE16-NEXT: s_add_u32 s2, s2, external_void_func_struct_i8_i32@rel32@lo+4 +; GFX11-FAKE16-NEXT: s_addc_u32 s3, s3, external_void_func_struct_i8_i32@rel32@hi+12 +; GFX11-FAKE16-NEXT: s_mov_b32 s32, 0 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: buffer_load_u8 v0, off, s[4:7], 0 +; GFX11-FAKE16-NEXT: buffer_load_b32 v1, off, s[4:7], 0 offset:4 +; GFX11-FAKE16-NEXT: s_mov_b64 s[6:7], s[0:1] +; GFX11-FAKE16-NEXT: s_swappc_b64 s[30:31], s[2:3] +; GFX11-FAKE16-NEXT: s_endpgm ; ; HSA-LABEL: test_call_external_void_func_struct_i8_i32: ; HSA: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll b/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll index 638e4b01488a0..3937b1cb05d3e 100644 --- a/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll +++ b/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll @@ -2382,10 +2382,10 @@ declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } -attributes #2 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } -attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #2 = { nounwind denormal_fpenv(float: ieee|ieee) } +attributes #3 = { nounwind denormal_fpenv(float: ieee|ieee) denormal_fpenv(preservesign) } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!2, !3} diff --git a/llvm/test/CodeGen/AMDGPU/clamp.ll b/llvm/test/CodeGen/AMDGPU/clamp.ll index 0d3567faaa10c..ffd52c2704409 100644 --- a/llvm/test/CodeGen/AMDGPU/clamp.ll +++ b/llvm/test/CodeGen/AMDGPU/clamp.ll @@ -4831,10 +4831,10 @@ declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #1 declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>) #1 declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } -attributes #2 = { nounwind "amdgpu-dx10-clamp"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-nans-fp-math"="false" } -attributes #3 = { nounwind "amdgpu-dx10-clamp"="true" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-nans-fp-math"="false" } -attributes #4 = { nounwind "amdgpu-dx10-clamp"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-nans-fp-math"="false" } +attributes #2 = { nounwind "amdgpu-dx10-clamp"="false" denormal_fpenv(float: preservesign) "no-nans-fp-math"="false" } +attributes #3 = { nounwind "amdgpu-dx10-clamp"="true" denormal_fpenv(float: preservesign) "no-nans-fp-math"="false" } +attributes #4 = { nounwind "amdgpu-dx10-clamp"="false" denormal_fpenv(float: preservesign) "no-nans-fp-math"="false" } attributes #5 = { nounwind readnone "amdgpu-ieee"="false" } attributes #6 = { nounwind "amdgpu-dx10-clamp"="false" } diff --git a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll index c167834470e3b..83e62cbb9b6fb 100644 --- a/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll +++ b/llvm/test/CodeGen/AMDGPU/combine-reg-or-const.ll @@ -27,7 +27,7 @@ define protected amdgpu_kernel void @_Z11test_kernelPii(ptr addrspace(1) nocaptu ; CHECK-NEXT: s_addc_u32 s1, s3, s5 ; CHECK-NEXT: s_bfe_u32 s2, s6, 0xd0003 ; CHECK-NEXT: s_add_i32 s2, s2, s7 -; CHECK-NEXT: s_or_b32 s2, s2, 0xc0 +; CHECK-NEXT: s_addk_i32 s2, 0xc0 ; CHECK-NEXT: v_mov_b32_e32 v0, s0 ; CHECK-NEXT: v_mov_b32_e32 v1, s1 ; CHECK-NEXT: v_mov_b32_e32 v2, s2 diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll index ec92edbe2bf65..42245e3d7013d 100644 --- a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll +++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11,GFX11-TRUE16 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GFX11,GFX11-FAKE16 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS,GCN-TRUE16,GFX11NONANS-TRUE16 -; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -enable-no-nans-fp-math < %s | FileCheck %s -check-prefixes=GCN,GFX11NONANS,GCN-FAKE16,GFX11NONANS-FAKE16 ; The tests check the following optimization of DAGCombiner: ; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C) @@ -855,21 +853,13 @@ define i1 @test57(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test58(double %arg1, double %arg2, double %arg3) #0 { -; GFX11-LABEL: test58: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test58: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test58: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ugt double %arg1, %arg3 %cmp2 = fcmp ugt double %arg2, %arg3 %and1 = and i1 %cmp1, %cmp2 @@ -877,21 +867,13 @@ define i1 @test58(double %arg1, double %arg2, double %arg3) #0 { } define i1 @test59(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test59: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test59: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test59: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp uge float %arg1, %arg3 %cmp2 = fcmp uge float %arg2, %arg3 %and1 = and i1 %cmp1, %cmp2 @@ -899,21 +881,13 @@ define i1 @test59(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test60(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test60: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test60: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test60: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ule float %arg1, %arg3 %cmp2 = fcmp ule float %arg2, %arg3 %and1 = and i1 %cmp1, %cmp2 @@ -921,21 +895,13 @@ define i1 @test60(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test61(double %arg1, double %arg2, double %arg3) #0 { -; GFX11-LABEL: test61: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test61: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test61: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ult double %arg1, %arg3 %cmp2 = fcmp ult double %arg2, %arg3 %and1 = and i1 %cmp1, %cmp2 @@ -1083,22 +1049,14 @@ define i1 @test69(double %arg1, double %arg2, double %arg3) { } define i1 @test70(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test70: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test70: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test70: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp olt float %var1, %arg3 @@ -1144,22 +1102,14 @@ define i1 @test72(double %arg1, double %arg2, double %arg3) { } define i1 @test73(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test73: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test73: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test73: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp oge float %var1, %arg3 @@ -1169,25 +1119,15 @@ define i1 @test73(float %arg1, float %arg2, float %arg3) { } define i1 @test74(double %arg1, double %arg2, double %arg3) { -; GFX11-LABEL: test74: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test74: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test74: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call double @llvm.canonicalize.f64(double %arg1) %var2 = call double @llvm.canonicalize.f64(double %arg2) %cmp1 = fcmp ugt double %var1, %arg3 @@ -1197,22 +1137,14 @@ define i1 @test74(double %arg1, double %arg2, double %arg3) { } define i1 @test75(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test75: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test75: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test75: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp uge float %var1, %arg3 @@ -1222,22 +1154,14 @@ define i1 @test75(float %arg1, float %arg2, float %arg3) { } define i1 @test76(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test76: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test76: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test76: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp ule float %var1, %arg3 @@ -1247,25 +1171,15 @@ define i1 @test76(float %arg1, float %arg2, float %arg3) { } define i1 @test77(double %arg1, double %arg2, double %arg3) { -; GFX11-LABEL: test77: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test77: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test77: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call double @llvm.canonicalize.f64(double %arg1) %var2 = call double @llvm.canonicalize.f64(double %arg2) %cmp1 = fcmp ult double %var1, %arg3 @@ -1289,21 +1203,13 @@ define i1 @test78(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test79(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test79: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test79: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test79: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ult float %arg1, %arg3 %cmp2 = fcmp ugt float %arg3, %arg2 %and1 = and i1 %cmp1, %cmp2 @@ -1364,22 +1270,14 @@ define i1 @test82(double %arg1, double %arg2, double %arg3) { } define i1 @test83(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test83: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test83: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test83: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp ule float %var1, %arg3 @@ -1408,7 +1306,6 @@ define i1 @test84(half %arg1, half %arg2, half %arg3) { ; GFX11-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test84: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1416,7 +1313,6 @@ define i1 @test84(half %arg1, half %arg2, half %arg3) { ; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v2.l ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test84: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1458,7 +1354,6 @@ define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { ; GFX11-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v3, v1 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test85: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1468,7 +1363,6 @@ define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { ; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.h, v2.h ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test85: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1514,7 +1408,6 @@ define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { ; GFX11-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v1 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test86: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1524,7 +1417,6 @@ define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { ; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test86: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1564,7 +1456,6 @@ define i1 @test87(half %arg1, half %arg2, half %arg3) { ; GFX11-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test87: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1572,7 +1463,6 @@ define i1 @test87(half %arg1, half %arg2, half %arg3) { ; GCN-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test87: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -1614,26 +1504,24 @@ define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { ; GFX11-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v1 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test88: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-TRUE16-NEXT: v_pk_min_f16 v1, v0, v1 -; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l +; GCN-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.l, v2.l ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h +; GCN-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v1.h, v2.h ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test88: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-FAKE16-NEXT: v_pk_min_f16 v0, v0, v1 ; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0, v2 ; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v1 +; GCN-FAKE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v3, v1 ; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1) @@ -1664,20 +1552,18 @@ define i1 @test89(half %arg1, half %arg2, half %arg3) { ; GFX11-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test89: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l -; GCN-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l +; GCN-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v2.l ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test89: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1 -; GCN-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v2 ; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] %var1 = call half @llvm.canonicalize.f16(half %arg1) @@ -1708,20 +1594,18 @@ define i1 @test90(half %arg1, half %arg2, half %arg3) { ; GFX11-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test90: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l -; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v2.l +; GCN-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v2.l ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test90: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1 -; GCN-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2 ; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] %var1 = call half @llvm.canonicalize.f16(half %arg1) @@ -1758,26 +1642,24 @@ define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { ; GFX11-FAKE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v3, v1 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test91: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v0, v1 -; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l +; GCN-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1.l, v2.l ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.h +; GCN-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v1.h, v2.h ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test91: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v1 ; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 ; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GCN-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0, v2 ; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GCN-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v3, v1 +; GCN-FAKE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v3, v1 ; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo ; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1) @@ -2175,21 +2057,13 @@ define i1 @test107(float %arg1, float %arg2, float %arg3, float %C) { } define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) { -; GFX11-LABEL: test108: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max3_f32 v0, v0, v1, v2 -; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v3 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test108: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max3_f32 v0, v0, v1, v2 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test108: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ult float %arg1, %C %cmp2 = fcmp ult float %arg2, %C %cmp3 = fcmp ult float %arg3, %C @@ -2199,27 +2073,17 @@ define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) { } define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C) { -; GFX11-LABEL: test109: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2 -; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3 -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4 -; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v1, v4 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test109: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4 -; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s0, v1, v4 -; GFX11NONANS-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test109: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; GCN-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2 +; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4 +; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v4 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp olt float %arg1, %C %cmp2 = fcmp olt float %arg2, %C %cmp3 = fcmp ogt float %arg3, %C @@ -2257,28 +2121,17 @@ define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1 } define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) { -; GFX11-LABEL: test111: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2 -; GFX11-NEXT: v_dual_min_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4 -; GFX11-NEXT: v_min3_f32 v0, v0, v1, v2 -; GFX11-NEXT: v_min_f32_e32 v0, v0, v3 -; GFX11-NEXT: v_min3_f32 v0, v5, v6, v0 -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test111: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v3 -; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v2 -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v4 -; GFX11NONANS-NEXT: v_min3_f32 v0, v5, v6, v0 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test111: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2 +; GCN-NEXT: v_dual_min_f32 v2, v2, v3 :: v_dual_max_f32 v3, v4, v4 +; GCN-NEXT: v_min3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_min_f32_e32 v0, v0, v3 +; GCN-NEXT: v_min3_f32 v0, v5, v6, v0 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp olt float %arg1, %C %cmp2 = fcmp olt float %arg2, %C %or1 = or i1 %cmp1, %cmp2 @@ -2298,30 +2151,19 @@ define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %ar } define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) { -; GFX11-LABEL: test112: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2 -; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v4, v8 -; GFX11-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_min_f32 v2, v2, v3 -; GFX11-NEXT: v_max_f32_e32 v3, v6, v6 -; GFX11-NEXT: v_min3_f32 v0, v0, v1, v2 -; GFX11-NEXT: v_min3_f32 v0, v0, v5, v3 -; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v0, v8 -; GFX11-NEXT: s_or_b32 s0, s0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test112: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v3 -; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v2 -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v4 -; GFX11NONANS-NEXT: v_min3_f32 v0, v5, v6, v0 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test112: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2 +; GCN-NEXT: v_cmp_nge_f32_e32 vcc_lo, v4, v8 +; GCN-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_min_f32 v2, v2, v3 +; GCN-NEXT: v_max_f32_e32 v3, v6, v6 +; GCN-NEXT: v_min3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_min3_f32 v0, v0, v5, v3 +; GCN-NEXT: v_cmp_lt_f32_e64 s0, v0, v8 +; GCN-NEXT: s_or_b32 s0, s0, vcc_lo +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp olt float %arg1, %C %cmp2 = fcmp olt float %arg2, %C %or1 = or i1 %cmp1, %cmp2 @@ -2341,24 +2183,16 @@ define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %ar } define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) { -; GFX11-LABEL: test113: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 -; GFX11-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_nge_f32_e64 s0, v0, v3 -; GFX11-NEXT: s_or_b32 s0, s0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test113: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_maxmin_f32 v0, v0, v1, v2 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test113: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_nge_f32_e64 s0, v0, v3 +; GCN-NEXT: s_or_b32 s0, s0, vcc_lo +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ult float %arg1, %C %cmp2 = fcmp ult float %arg2, %C %cmp3 = fcmp olt float %arg3, %C @@ -2368,26 +2202,16 @@ define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) { } define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) { -; GFX11-LABEL: test114: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v2, v3 -; GFX11-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v0, v3 -; GFX11-NEXT: s_and_b32 s0, s0, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test114: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 -; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s0, v0, v3 -; GFX11NONANS-NEXT: s_and_b32 s0, s0, vcc_lo -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test114: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; GCN-NEXT: v_cmp_nge_f32_e32 vcc_lo, v2, v3 +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_gt_f32_e64 s0, v0, v3 +; GCN-NEXT: s_and_b32 s0, s0, vcc_lo +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ogt float %arg1, %C %cmp2 = fcmp ogt float %arg2, %C %cmp3 = fcmp ult float %arg3, %C @@ -2397,26 +2221,17 @@ define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) { } define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C) { -; GFX11-LABEL: test115: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v3, v3, v3 -; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3 -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4 -; GFX11-NEXT: v_cmp_nge_f32_e64 s0, v1, v4 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test115: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v2, v2, v3 -; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v2 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test115: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v2, v2, v2 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v3, v3, v3 +; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4 +; GCN-NEXT: v_cmp_nge_f32_e64 s0, v1, v4 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp olt float %arg1, %C %cmp2 = fcmp olt float %arg2, %C %var3 = call float @llvm.canonicalize.f32(float %arg3) @@ -2430,44 +2245,27 @@ define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C) } define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %C) { -; GFX11-LABEL: test116: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v8, v8, v8 -; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2 -; GFX11-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4 -; GFX11-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v6, v6, v6 -; GFX11-NEXT: v_min_f32_e32 v8, v8, v9 -; GFX11-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5 -; GFX11-NEXT: v_max_f32_e32 v4, v6, v7 -; GFX11-NEXT: v_min3_f32 v0, v0, v1, v8 -; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v10 -; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v3, v10 -; GFX11-NEXT: v_cmp_gt_f32_e64 s1, v4, v10 -; GFX11-NEXT: v_cmp_lt_f32_e64 s2, v0, v10 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, vcc_lo -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test116: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v8, v8, v9 -; GFX11NONANS-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5 -; GFX11NONANS-NEXT: v_max_f32_e32 v4, v6, v7 -; GFX11NONANS-NEXT: v_min3_f32 v0, v0, v1, v8 -; GFX11NONANS-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v10 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s0, v3, v10 -; GFX11NONANS-NEXT: v_cmp_gt_f32_e64 s1, v4, v10 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s2, v0, v10 -; GFX11NONANS-NEXT: s_or_b32 s0, s0, s1 -; GFX11NONANS-NEXT: s_or_b32 s1, s2, vcc_lo -; GFX11NONANS-NEXT: s_or_b32 s0, s0, s1 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test116: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v9, v9, v9 :: v_dual_max_f32 v8, v8, v8 +; GCN-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; GCN-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v2, v2, v2 +; GCN-NEXT: v_dual_max_f32 v5, v5, v5 :: v_dual_max_f32 v4, v4, v4 +; GCN-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v6, v6, v6 +; GCN-NEXT: v_min_f32_e32 v8, v8, v9 +; GCN-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5 +; GCN-NEXT: v_max_f32_e32 v4, v6, v7 +; GCN-NEXT: v_min3_f32 v0, v0, v1, v8 +; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v10 +; GCN-NEXT: v_cmp_lt_f32_e64 s0, v3, v10 +; GCN-NEXT: v_cmp_gt_f32_e64 s1, v4, v10 +; GCN-NEXT: v_cmp_lt_f32_e64 s2, v0, v10 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_or_b32 s1, s2, vcc_lo +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp olt float %arg1, %C %cmp2 = fcmp olt float %arg2, %C %cmp3 = fcmp ogt float %arg3, %C @@ -2491,45 +2289,27 @@ define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %ar } define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %arg11, float %arg12, float %C1, float %C2) { -; GFX11-LABEL: test117: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v6, v6, v6 -; GFX11-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v10, v10, v10 -; GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; GFX11-NEXT: v_dual_max_f32 v11, v11, v11 :: v_dual_max_f32 v2, v2, v2 -; GFX11-NEXT: v_min_f32_e32 v6, v6, v7 -; GFX11-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11 -; GFX11-NEXT: v_min_f32_e32 v2, v2, v3 -; GFX11-NEXT: v_min3_f32 v3, v4, v5, v6 -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v12 -; GFX11-NEXT: v_min3_f32 v0, v8, v9, v1 -; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v2, v13 -; GFX11-NEXT: v_cmp_lt_f32_e64 s1, v3, v13 -; GFX11-NEXT: v_cmp_lt_f32_e64 s2, v0, v12 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s0, s2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test117: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v6, v6, v7 -; GFX11NONANS-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11 -; GFX11NONANS-NEXT: v_min_f32_e32 v2, v2, v3 -; GFX11NONANS-NEXT: v_min3_f32 v3, v4, v5, v6 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v12 -; GFX11NONANS-NEXT: v_min3_f32 v0, v8, v9, v1 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s0, v2, v13 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s1, v3, v13 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e64 s2, v0, v12 -; GFX11NONANS-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11NONANS-NEXT: s_or_b32 s0, s0, s1 -; GFX11NONANS-NEXT: s_or_b32 s0, s2, s0 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test117: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v3, v3, v3 :: v_dual_max_f32 v6, v6, v6 +; GCN-NEXT: v_dual_max_f32 v7, v7, v7 :: v_dual_max_f32 v10, v10, v10 +; GCN-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; GCN-NEXT: v_dual_max_f32 v11, v11, v11 :: v_dual_max_f32 v2, v2, v2 +; GCN-NEXT: v_min_f32_e32 v6, v6, v7 +; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11 +; GCN-NEXT: v_min_f32_e32 v2, v2, v3 +; GCN-NEXT: v_min3_f32 v3, v4, v5, v6 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v12 +; GCN-NEXT: v_min3_f32 v0, v8, v9, v1 +; GCN-NEXT: v_cmp_lt_f32_e64 s0, v2, v13 +; GCN-NEXT: v_cmp_lt_f32_e64 s1, v3, v13 +; GCN-NEXT: v_cmp_lt_f32_e64 s2, v0, v12 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_or_b32 s0, s2, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp olt float %arg1, %C1 %cmp2 = fcmp olt float %arg2, %C1 %cmp3 = fcmp olt float %arg3, %C2 @@ -2814,7 +2594,6 @@ define i1 @test131(i16 %arg1, i32 %arg2) { ; GFX11-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-TRUE16-LABEL: test131: ; GCN-TRUE16: ; %bb.0: ; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2823,7 +2602,6 @@ define i1 @test131(i16 %arg1, i32 %arg2) { ; GCN-TRUE16-NEXT: s_or_b32 s0, s0, vcc_lo ; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] -; ; GCN-FAKE16-LABEL: test131: ; GCN-FAKE16: ; %bb.0: ; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) @@ -2875,22 +2653,14 @@ define i1 @test133(i32 %arg1, i32 %arg2) { } define i1 @test134(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test134: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_gt_f32_e64 s0, v2, v1 -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test134: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test134: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_gt_f32_e64 s0, v2, v1 +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp olt float %arg1, %arg3 %cmp2 = fcmp ogt float %arg3, %arg2 %and1 = and i1 %cmp1, %cmp2 @@ -2898,22 +2668,14 @@ define i1 @test134(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test135(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test135: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_nle_f32_e64 s0, v2, v1 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test135: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test135: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_nle_f32_e64 s0, v2, v1 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ult float %arg1, %arg3 %cmp2 = fcmp ugt float %arg3, %arg2 %or1 = or i1 %cmp1, %cmp2 @@ -2921,26 +2683,16 @@ define i1 @test135(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test136(double %arg1, double %arg2, double %arg3) { -; GFX11-LABEL: test136: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_ge_f64_e64 s0, v[4:5], v[2:3] -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test136: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test136: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_ge_f64_e64 s0, v[4:5], v[2:3] +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call double @llvm.canonicalize.f64(double %arg1) %var2 = call double @llvm.canonicalize.f64(double %arg2) %cmp1 = fcmp ole double %var1, %arg3 @@ -2950,23 +2702,15 @@ define i1 @test136(double %arg1, double %arg2, double %arg3) { } define i1 @test137(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test137: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v2, v1 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test137: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test137: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_nlt_f32_e64 s0, v2, v1 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp ule float %var1, %arg3 @@ -2976,22 +2720,14 @@ define i1 @test137(float %arg1, float %arg2, float %arg3) { } define i1 @test138(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test138: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v1, v2 -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test138: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test138: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_lt_f32_e64 s0, v1, v2 +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp olt float %arg1, %arg3 %cmp2 = fcmp olt float %arg2, %arg3 %and1 = and i1 %cmp1, %cmp2 @@ -2999,22 +2735,14 @@ define i1 @test138(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test139(double %arg1, double %arg2, double %arg3) #0 { -; GFX11-LABEL: test139: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5] -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test139: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test139: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5] +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ole double %arg1, %arg3 %cmp2 = fcmp ole double %arg2, %arg3 %and1 = and i1 %cmp1, %cmp2 @@ -3022,22 +2750,14 @@ define i1 @test139(double %arg1, double %arg2, double %arg3) #0 { } define i1 @test140(double %arg1, double %arg2, double %arg3) #0 { -; GFX11-LABEL: test140: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5] -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test140: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test140: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5] +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ogt double %arg1, %arg3 %cmp2 = fcmp ogt double %arg2, %arg3 %and1 = and i1 %cmp1, %cmp2 @@ -3045,22 +2765,14 @@ define i1 @test140(double %arg1, double %arg2, double %arg3) #0 { } define i1 @test141(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test141: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_ge_f32_e64 s0, v1, v2 -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test141: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test141: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 s0, v1, v2 +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp oge float %arg1, %arg3 %cmp2 = fcmp oge float %arg2, %arg3 %and1 = and i1 %cmp1, %cmp2 @@ -3068,22 +2780,14 @@ define i1 @test141(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test142(double %arg1, double %arg2, double %arg3) #0 { -; GFX11-LABEL: test142: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5] -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test142: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test142: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5] +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ugt double %arg1, %arg3 %cmp2 = fcmp ugt double %arg2, %arg3 %or1 = or i1 %cmp1, %cmp2 @@ -3091,22 +2795,14 @@ define i1 @test142(double %arg1, double %arg2, double %arg3) #0 { } define i1 @test143(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test143: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test143: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test143: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp uge float %arg1, %arg3 %cmp2 = fcmp uge float %arg2, %arg3 %or1 = or i1 %cmp1, %cmp2 @@ -3114,22 +2810,14 @@ define i1 @test143(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test144(float %arg1, float %arg2, float %arg3) #0 { -; GFX11-LABEL: test144: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test144: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test144: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ule float %arg1, %arg3 %cmp2 = fcmp ule float %arg2, %arg3 %or1 = or i1 %cmp1, %cmp2 @@ -3137,22 +2825,14 @@ define i1 @test144(float %arg1, float %arg2, float %arg3) #0 { } define i1 @test145(double %arg1, double %arg2, double %arg3) #0 { -; GFX11-LABEL: test145: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5] -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test145: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test145: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5] +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %cmp1 = fcmp ult double %arg1, %arg3 %cmp2 = fcmp ult double %arg2, %arg3 %or1 = or i1 %cmp1, %cmp2 @@ -3160,23 +2840,15 @@ define i1 @test145(double %arg1, double %arg2, double %arg3) #0 { } define i1 @test146(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test146: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_lt_f32_e64 s0, v1, v2 -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test146: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test146: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_lt_f32_e64 s0, v1, v2 +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp olt float %var1, %arg3 @@ -3186,26 +2858,16 @@ define i1 @test146(float %arg1, float %arg2, float %arg3) { } define i1 @test147(double %arg1, double %arg2, double %arg3) { -; GFX11-LABEL: test147: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5] -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test147: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test147: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_le_f64_e64 s0, v[2:3], v[4:5] +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call double @llvm.canonicalize.f64(double %arg1) %var2 = call double @llvm.canonicalize.f64(double %arg2) %cmp1 = fcmp ole double %var1, %arg3 @@ -3215,26 +2877,16 @@ define i1 @test147(double %arg1, double %arg2, double %arg3) { } define i1 @test148(double %arg1, double %arg2, double %arg3) { -; GFX11-LABEL: test148: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5] -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test148: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test148: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_gt_f64_e64 s0, v[2:3], v[4:5] +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call double @llvm.canonicalize.f64(double %arg1) %var2 = call double @llvm.canonicalize.f64(double %arg2) %cmp1 = fcmp ogt double %var1, %arg3 @@ -3244,23 +2896,15 @@ define i1 @test148(double %arg1, double %arg2, double %arg3) { } define i1 @test149(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test149: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_ge_f32_e64 s0, v1, v2 -; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test149: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test149: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 s0, v1, v2 +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp oge float %var1, %arg3 @@ -3270,26 +2914,16 @@ define i1 @test149(float %arg1, float %arg2, float %arg3) { } define i1 @test150(double %arg1, double %arg2, double %arg3) { -; GFX11-LABEL: test150: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5] -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test150: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test150: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_cmp_nle_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_nle_f64_e64 s0, v[2:3], v[4:5] +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call double @llvm.canonicalize.f64(double %arg1) %var2 = call double @llvm.canonicalize.f64(double %arg2) %cmp1 = fcmp ugt double %var1, %arg3 @@ -3299,23 +2933,15 @@ define i1 @test150(double %arg1, double %arg2, double %arg3) { } define i1 @test151(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test151: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test151: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test151: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_nlt_f32_e64 s0, v1, v2 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp uge float %var1, %arg3 @@ -3325,23 +2951,15 @@ define i1 @test151(float %arg1, float %arg2, float %arg3) { } define i1 @test152(float %arg1, float %arg2, float %arg3) { -; GFX11-LABEL: test152: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GFX11-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 -; GFX11-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2 -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test152: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_min_f32_e32 v0, v0, v1 -; GFX11NONANS-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test152: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GCN-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cmp_ngt_f32_e64 s0, v1, v2 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call float @llvm.canonicalize.f32(float %arg1) %var2 = call float @llvm.canonicalize.f32(float %arg2) %cmp1 = fcmp ule float %var1, %arg3 @@ -3351,26 +2969,16 @@ define i1 @test152(float %arg1, float %arg2, float %arg3) { } define i1 @test153(double %arg1, double %arg2, double %arg3) { -; GFX11-LABEL: test153: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5] -; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 -; GFX11-NEXT: s_setpc_b64 s[30:31] -; -; GFX11NONANS-LABEL: test153: -; GFX11NONANS: ; %bb.0: -; GFX11NONANS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11NONANS-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] -; GFX11NONANS-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] -; GFX11NONANS-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] -; GFX11NONANS-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] -; GFX11NONANS-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX11NONANS-NEXT: s_setpc_b64 s[30:31] +; GCN-LABEL: test153: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_cmp_nge_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cmp_nge_f64_e64 s0, v[2:3], v[4:5] +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] %var1 = call double @llvm.canonicalize.f64(double %arg1) %var2 = call double @llvm.canonicalize.f64(double %arg2) %cmp1 = fcmp ult double %var1, %arg3 @@ -3387,5 +2995,4 @@ declare <2 x half> @llvm.canonicalize.v2f16(<2 x half>) attributes #0 = { nounwind "amdgpu-ieee"="false" } attributes #1 = { nounwind "no-nans-fp-math"="true" } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX11NONANS-FAKE16: {{.*}} -; GFX11NONANS-TRUE16: {{.*}} +; GFX11: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll new file mode 100644 index 0000000000000..37ef7949fe5c9 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll @@ -0,0 +1,1449 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GCN-TRUE16 +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s -check-prefixes=GCN,GCN-FAKE16 + +; The tests check the following optimization of DAGCombiner: +; CMP(A,C)||CMP(B,C) => CMP(MIN/MAX(A,B), C) +; CMP(A,C)&&CMP(B,C) => CMP(MIN/MAX(A,B), C) + +define i1 @test54(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test54: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %arg3 + %cmp2 = fcmp nnan olt float %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test55(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test55: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ole double %arg1, %arg3 + %cmp2 = fcmp nnan ole double %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test56(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test56: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ogt double %arg1, %arg3 + %cmp2 = fcmp nnan ogt double %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test57(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test57: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan oge float %arg1, %arg3 + %cmp2 = fcmp nnan oge float %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test58(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test58: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ugt double %arg1, %arg3 + %cmp2 = fcmp nnan ugt double %arg2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test59(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test59: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan uge float %arg1, %arg3 + %cmp2 = fcmp nnan uge float %arg2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test60(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test60: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ule float %arg1, %arg3 + %cmp2 = fcmp nnan ule float %arg2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test61(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test61: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ult double %arg1, %arg3 + %cmp2 = fcmp nnan ult double %arg2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test62(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test62: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1 +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, 1.0 + %add2 = fadd nnan float %arg2, 2.0 + %cmp1 = fcmp nnan olt float %add1, %arg3 + %cmp2 = fcmp nnan olt float %add2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test63(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test63: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0 +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan double %arg1, 1.0 + %add2 = fadd nnan double %arg2, 2.0 + %cmp1 = fcmp nnan ole double %add1, %arg3 + %cmp2 = fcmp nnan ole double %add2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test64(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test64: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0 +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan double %arg1, 1.0 + %add2 = fadd nnan double %arg2, 2.0 + %cmp1 = fcmp nnan ogt double %add1, %arg3 + %cmp2 = fcmp nnan ogt double %add2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test65(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test65: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1 +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, 1.0 + %add2 = fadd nnan float %arg2, 2.0 + %cmp1 = fcmp nnan oge float %add1, %arg3 + %cmp2 = fcmp nnan oge float %add2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test66(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test66: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0 +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan double %arg1, 1.0 + %add2 = fadd nnan double %arg2, 2.0 + %cmp1 = fcmp nnan ugt double %add1, %arg3 + %cmp2 = fcmp nnan ugt double %add2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test67(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test67: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1 +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, 1.0 + %add2 = fadd nnan float %arg2, 2.0 + %cmp1 = fcmp nnan uge float %add1, %arg3 + %cmp2 = fcmp nnan uge float %add2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test68(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test68: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1 +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, 1.0 + %add2 = fadd nnan float %arg2, 2.0 + %cmp1 = fcmp nnan ule float %add1, %arg3 + %cmp2 = fcmp nnan ule float %add2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test69(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test69: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0 +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan double %arg1, 1.0 + %add2 = fadd nnan double %arg2, 2.0 + %cmp1 = fcmp nnan ult double %add1, %arg3 + %cmp2 = fcmp nnan ult double %add2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test70(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test70: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan olt float %var1, %arg3 + %cmp2 = fcmp nnan olt float %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test71(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test71: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ole double %var1, %arg3 + %cmp2 = fcmp nnan ole double %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test72(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test72: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ogt double %var1, %arg3 + %cmp2 = fcmp nnan ogt double %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test73(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test73: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan oge float %var1, %arg3 + %cmp2 = fcmp nnan oge float %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test74(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test74: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ugt double %var1, %arg3 + %cmp2 = fcmp nnan ugt double %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test75(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test75: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan uge float %var1, %arg3 + %cmp2 = fcmp nnan uge float %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test76(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test76: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan ule float %var1, %arg3 + %cmp2 = fcmp nnan ule float %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test77(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test77: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ult double %var1, %arg3 + %cmp2 = fcmp nnan ult double %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test78(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test78: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %arg3 + %cmp2 = fcmp nnan ogt float %arg3, %arg2 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test79(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test79: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ult float %arg1, %arg3 + %cmp2 = fcmp nnan ugt float %arg3, %arg2 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test80(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test80: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v0, 1.0, v0 :: v_dual_add_f32 v1, 2.0, v1 +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, 1.0 + %add2 = fadd nnan float %arg2, 2.0 + %cmp1 = fcmp nnan oge float %add1, %arg3 + %cmp2 = fcmp nnan ole float %arg3, %add2 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test81(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test81: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 +; GCN-NEXT: v_add_f64 v[2:3], v[2:3], 2.0 +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan double %arg1, 1.0 + %add2 = fadd nnan double %arg2, 2.0 + %cmp1 = fcmp nnan ugt double %add1, %arg3 + %cmp2 = fcmp nnan ult double %arg3, %add2 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test82(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test82: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ole double %var1, %arg3 + %cmp2 = fcmp nnan oge double %arg3, %var2 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test83(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test83: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan ule float %var1, %arg3 + %cmp2 = fcmp nnan uge float %arg3, %var2 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test84(half %arg1, half %arg2, half %arg3) { +; GCN-TRUE16-LABEL: test84: +; GCN-TRUE16: ; %bb.0: +; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l +; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v2.l +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FAKE16-LABEL: test84: +; GCN-FAKE16: ; %bb.0: +; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1 +; GCN-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan half @llvm.canonicalize.f16(half %arg1) + %var2 = call nnan half @llvm.canonicalize.f16(half %arg2) + %cmp1 = fcmp nnan olt half %var1, %arg3 + %cmp2 = fcmp nnan olt half %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define <2 x i1> @test85(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { +; GCN-TRUE16-LABEL: test85: +; GCN-TRUE16: ; %bb.0: +; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0 +; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 +; GCN-TRUE16-NEXT: v_pk_min_f16 v1, v0, v1 +; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.l, v2.l +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v1.h, v2.h +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FAKE16-LABEL: test85: +; GCN-FAKE16: ; %bb.0: +; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v0 +; GCN-FAKE16-NEXT: v_pk_max_f16 v1, v1, v1 +; GCN-FAKE16-NEXT: v_pk_min_f16 v0, v0, v1 +; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GCN-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v3, v1 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] + %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1) + %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2) + %cmp1 = fcmp nnan ole <2 x half> %var1, %arg3 + %cmp2 = fcmp nnan ole <2 x half> %var2, %arg3 + %or1 = or <2 x i1> %cmp1, %cmp2 + ret <2 x i1> %or1 +} + +define <2 x i1> @test86(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { +; GCN-TRUE16-LABEL: test86: +; GCN-TRUE16: ; %bb.0: +; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0 +; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 +; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v0, v1 +; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FAKE16-LABEL: test86: +; GCN-FAKE16: ; %bb.0: +; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v0 +; GCN-FAKE16-NEXT: v_pk_max_f16 v1, v1, v1 +; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v1 +; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v1 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] + %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1) + %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2) + %cmp1 = fcmp nnan ogt <2 x half> %var1, %arg3 + %cmp2 = fcmp nnan ogt <2 x half> %var2, %arg3 + %or1 = or <2 x i1> %cmp1, %cmp2 + ret <2 x i1> %or1 +} + +define i1 @test87(half %arg1, half %arg2, half %arg3) { +; GCN-TRUE16-LABEL: test87: +; GCN-TRUE16: ; %bb.0: +; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l +; GCN-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FAKE16-LABEL: test87: +; GCN-FAKE16: ; %bb.0: +; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1 +; GCN-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan half @llvm.canonicalize.f16(half %arg1) + %var2 = call nnan half @llvm.canonicalize.f16(half %arg2) + %cmp1 = fcmp nnan oge half %var1, %arg3 + %cmp2 = fcmp nnan oge half %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define <2 x i1> @test88(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { +; GCN-TRUE16-LABEL: test88: +; GCN-TRUE16: ; %bb.0: +; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0 +; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 +; GCN-TRUE16-NEXT: v_pk_min_f16 v1, v0, v1 +; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.l, v2.l +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v1.h, v2.h +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FAKE16-LABEL: test88: +; GCN-FAKE16: ; %bb.0: +; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v0 +; GCN-FAKE16-NEXT: v_pk_max_f16 v1, v1, v1 +; GCN-FAKE16-NEXT: v_pk_min_f16 v0, v0, v1 +; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v3, v1 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] + %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1) + %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2) + %cmp1 = fcmp nnan ugt <2 x half> %var1, %arg3 + %cmp2 = fcmp nnan ugt <2 x half> %var2, %arg3 + %and1 = and <2 x i1> %cmp1, %cmp2 + ret <2 x i1> %and1 +} + +define i1 @test89(half %arg1, half %arg2, half %arg3) { +; GCN-TRUE16-LABEL: test89: +; GCN-TRUE16: ; %bb.0: +; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v1.l +; GCN-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v2.l +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FAKE16-LABEL: test89: +; GCN-FAKE16: ; %bb.0: +; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FAKE16-NEXT: v_min_f16_e32 v0, v0, v1 +; GCN-FAKE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan half @llvm.canonicalize.f16(half %arg1) + %var2 = call nnan half @llvm.canonicalize.f16(half %arg2) + %cmp1 = fcmp nnan uge half %var1, %arg3 + %cmp2 = fcmp nnan uge half %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test90(half %arg1, half %arg2, half %arg3) { +; GCN-TRUE16-LABEL: test90: +; GCN-TRUE16: ; %bb.0: +; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v1.l +; GCN-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v2.l +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FAKE16-LABEL: test90: +; GCN-FAKE16: ; %bb.0: +; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FAKE16-NEXT: v_max_f16_e32 v0, v0, v1 +; GCN-FAKE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan half @llvm.canonicalize.f16(half %arg1) + %var2 = call nnan half @llvm.canonicalize.f16(half %arg2) + %cmp1 = fcmp nnan ule half %var1, %arg3 + %cmp2 = fcmp nnan ule half %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define <2 x i1> @test91(<2 x half> %arg1, <2 x half> %arg2, <2 x half> %arg3) { +; GCN-TRUE16-LABEL: test91: +; GCN-TRUE16: ; %bb.0: +; GCN-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-TRUE16-NEXT: v_pk_max_f16 v0, v0, v0 +; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 +; GCN-TRUE16-NEXT: v_pk_max_f16 v1, v0, v1 +; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.l, v2.l +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v1.h, v2.h +; GCN-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GCN-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GCN-FAKE16-LABEL: test91: +; GCN-FAKE16: ; %bb.0: +; GCN-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v0 +; GCN-FAKE16-NEXT: v_pk_max_f16 v1, v1, v1 +; GCN-FAKE16-NEXT: v_pk_max_f16 v0, v0, v1 +; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GCN-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GCN-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v3, v1 +; GCN-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GCN-FAKE16-NEXT: s_setpc_b64 s[30:31] + %var1 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg1) + %var2 = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %arg2) + %cmp1 = fcmp nnan ult <2 x half> %var1, %arg3 + %cmp2 = fcmp nnan ult <2 x half> %var2, %arg3 + %and1 = and <2 x i1> %cmp1, %cmp2 + ret <2 x i1> %and1 +} + +define i1 @test107(float %arg1, float %arg2, float %arg3, float %C) { +; GCN-LABEL: test107: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %C + %cmp2 = fcmp nnan olt float %arg2, %C + %cmp3 = fcmp nnan olt float %arg3, %C + %or1 = or i1 %cmp1, %cmp2 + %or2 = or i1 %or1, %cmp3 + ret i1 %or2 +} + +define i1 @test108(float %arg1, float %arg2, float %arg3, float %C) { +; GCN-LABEL: test108: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ult float %arg1, %C + %cmp2 = fcmp nnan ult float %arg2, %C + %cmp3 = fcmp nnan ult float %arg3, %C + %and1 = and i1 %cmp1, %cmp2 + %and2 = and i1 %and1, %cmp3 + ret i1 %and2 +} + +define i1 @test109(float %arg1, float %arg2, float %arg3, float %arg4, float %C) { +; GCN-LABEL: test109: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_max_f32 v1, v2, v3 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4 +; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v4 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %C + %cmp2 = fcmp nnan olt float %arg2, %C + %cmp3 = fcmp nnan ogt float %arg3, %C + %cmp4 = fcmp nnan ogt float %arg4, %C + %or1 = or i1 %cmp1, %cmp2 + %or2 = or i1 %cmp3, %cmp4 + %or3 = or i1 %or1, %or2 + ret i1 %or3 +} + +define i1 @test110(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 { +; GCN-LABEL: test110: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5 +; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7 +; GCN-NEXT: v_dual_max_f32 v0, v0, v1 :: v_dual_min_f32 v1, v2, v3 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 +; GCN-NEXT: v_cmp_gt_f32_e64 s0, v1, v8 +; GCN-NEXT: s_and_b32 s0, vcc_lo, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, %C1 + %add2 = fadd nnan float %arg2, %C2 + %add3 = fadd nnan float %arg3, %C3 + %add4 = fadd nnan float %arg4, %C4 + %cmp1 = fcmp nnan ult float %add1, %C + %cmp2 = fcmp nnan ult float %add2, %C + %cmp3 = fcmp nnan ugt float %add3, %C + %cmp4 = fcmp nnan ugt float %add4, %C + %or1 = and i1 %cmp1, %cmp2 + %or2 = and i1 %cmp3, %cmp4 + %or3 = and i1 %or1, %or2 + ret i1 %or3 +} + +define i1 @test111(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) { +; GCN-LABEL: test111: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v2, v2, v3 +; GCN-NEXT: v_min3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_min_f32_e32 v0, v0, v4 +; GCN-NEXT: v_min3_f32 v0, v5, v6, v0 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %C + %cmp2 = fcmp nnan olt float %arg2, %C + %or1 = or i1 %cmp1, %cmp2 + %cmp3 = fcmp nnan olt float %arg3, %C + %cmp4 = fcmp nnan olt float %arg4, %C + %or2 = or i1 %cmp3, %cmp4 + %cmp5 = fcmp nnan olt float %arg5, %C + %or3 = or i1 %or1, %or2 + %or4 = or i1 %or3, %cmp5 + %cmp6 = fcmp nnan olt float %arg6, %C + %cmp7 = fcmp nnan olt float %arg7, %C + %or5 = or i1 %cmp6, %cmp7 + %cmp8 = fcmp nnan olt float %arg8, %C + %or6 = or i1 %or5, %or4 + %or7 = or i1 %or6, %cmp8 + ret i1 %or6 +} + +define i1 @test112(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %C) { +; GCN-LABEL: test112: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v2, v2, v3 +; GCN-NEXT: v_min3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_min_f32_e32 v0, v0, v4 +; GCN-NEXT: v_min3_f32 v0, v5, v6, v0 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %C + %cmp2 = fcmp nnan olt float %arg2, %C + %or1 = or i1 %cmp1, %cmp2 + %cmp3 = fcmp nnan olt float %arg3, %C + %cmp4 = fcmp nnan olt float %arg4, %C + %or2 = or i1 %cmp3, %cmp4 + %cmp5 = fcmp nnan ult float %arg5, %C + %or3 = or i1 %or1, %or2 + %or4 = or i1 %or3, %cmp5 + %cmp6 = fcmp nnan olt float %arg6, %C + %cmp7 = fcmp nnan olt float %arg7, %C + %or5 = or i1 %cmp6, %cmp7 + %cmp8 = fcmp nnan ult float %arg8, %C + %or6 = or i1 %or5, %or4 + %or7 = or i1 %or6, %cmp8 + ret i1 %or6 +} + +define i1 @test113(float %arg1, float %arg2, float %arg3, float %C) { +; GCN-LABEL: test113: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_maxmin_f32 v0, v0, v1, v2 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ult float %arg1, %C + %cmp2 = fcmp nnan ult float %arg2, %C + %cmp3 = fcmp nnan olt float %arg3, %C + %and1 = and i1 %cmp1, %cmp2 + %or1 = or i1 %and1, %cmp3 + ret i1 %or1 +} + +define i1 @test114(float %arg1, float %arg2, float %arg3, float %C) { +; GCN-LABEL: test114: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3 +; GCN-NEXT: v_cmp_gt_f32_e64 s0, v0, v3 +; GCN-NEXT: s_and_b32 s0, s0, vcc_lo +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ogt float %arg1, %C + %cmp2 = fcmp nnan ogt float %arg2, %C + %cmp3 = fcmp nnan ult float %arg3, %C + %and1 = or i1 %cmp1, %cmp2 + %or1 = and i1 %and1, %cmp3 + ret i1 %or1 +} + +define i1 @test115(float %arg1, float %arg2, float %arg3, float %arg4, float %C) { +; GCN-LABEL: test115: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v2, v2, v3 +; GCN-NEXT: v_min3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %C + %cmp2 = fcmp nnan olt float %arg2, %C + %var3 = call nnan float @llvm.canonicalize.f32(float %arg3) + %var4 = call nnan float @llvm.canonicalize.f32(float %arg4) + %cmp3 = fcmp nnan ult float %var3, %C + %cmp4 = fcmp nnan ult float %var4, %C + %or1 = or i1 %cmp1, %cmp2 + %and1 = and i1 %cmp3, %cmp4 + %or2 = or i1 %or1, %and1 + ret i1 %or2 +} + +define i1 @test116(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %C) { +; GCN-LABEL: test116: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v8, v8, v9 +; GCN-NEXT: v_dual_max_f32 v2, v2, v3 :: v_dual_min_f32 v3, v4, v5 +; GCN-NEXT: v_max_f32_e32 v4, v6, v7 +; GCN-NEXT: v_min3_f32 v0, v0, v1, v8 +; GCN-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v10 +; GCN-NEXT: v_cmp_lt_f32_e64 s0, v3, v10 +; GCN-NEXT: v_cmp_gt_f32_e64 s1, v4, v10 +; GCN-NEXT: v_cmp_lt_f32_e64 s2, v0, v10 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_or_b32 s1, s2, vcc_lo +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %C + %cmp2 = fcmp nnan olt float %arg2, %C + %cmp3 = fcmp nnan ogt float %arg3, %C + %cmp4 = fcmp nnan ogt float %arg4, %C + %cmp5 = fcmp nnan olt float %arg5, %C + %cmp6 = fcmp nnan olt float %arg6, %C + %cmp7 = fcmp nnan ogt float %arg7, %C + %cmp8 = fcmp nnan ogt float %arg8, %C + %cmp9 = fcmp nnan olt float %arg9, %C + %cmp10 = fcmp nnan olt float %arg10, %C + %or1 = or i1 %cmp1, %cmp2 + %or2 = or i1 %cmp3, %cmp4 + %or3 = or i1 %cmp5, %cmp6 + %or4 = or i1 %cmp7, %cmp8 + %or5 = or i1 %cmp9, %cmp10 + %or6 = or i1 %or1, %or2 + %or7 = or i1 %or3, %or4 + %or8 = or i1 %or5, %or6 + %or9 = or i1 %or7, %or8 + ret i1 %or9 +} + +define i1 @test117(float %arg1, float %arg2, float %arg3, float %arg4, float %arg5, float %arg6, float %arg7, float %arg8, float %arg9, float %arg10, float %arg11, float %arg12, float %C1, float %C2) { +; GCN-LABEL: test117: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v6, v6, v7 +; GCN-NEXT: v_dual_min_f32 v0, v0, v1 :: v_dual_min_f32 v1, v10, v11 +; GCN-NEXT: v_min_f32_e32 v2, v2, v3 +; GCN-NEXT: v_min3_f32 v3, v4, v5, v6 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v12 +; GCN-NEXT: v_min3_f32 v0, v8, v9, v1 +; GCN-NEXT: v_cmp_lt_f32_e64 s0, v2, v13 +; GCN-NEXT: v_cmp_lt_f32_e64 s1, v3, v13 +; GCN-NEXT: v_cmp_lt_f32_e64 s2, v0, v12 +; GCN-NEXT: s_or_b32 s0, vcc_lo, s0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_or_b32 s0, s2, s0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %C1 + %cmp2 = fcmp nnan olt float %arg2, %C1 + %cmp3 = fcmp nnan olt float %arg3, %C2 + %cmp4 = fcmp nnan olt float %arg4, %C2 + %cmp5 = fcmp nnan olt float %arg5, %C2 + %cmp6 = fcmp nnan olt float %arg6, %C2 + %cmp7 = fcmp nnan olt float %arg7, %C2 + %cmp8 = fcmp nnan olt float %arg8, %C2 + %cmp9 = fcmp nnan olt float %arg9, %C1 + %cmp10 = fcmp nnan olt float %arg10, %C1 + %cmp11 = fcmp nnan olt float %arg11, %C1 + %cmp12 = fcmp nnan olt float %arg12, %C1 + %or1 = or i1 %cmp1, %cmp2 + %or2 = or i1 %cmp3, %cmp4 + %or3 = or i1 %cmp5, %cmp6 + %or4 = or i1 %cmp7, %cmp8 + %or5 = or i1 %cmp9, %cmp10 + %or6 = or i1 %cmp11, %cmp12 + %or7 = or i1 %or1, %or2 + %or8 = or i1 %or3, %or4 + %or9 = or i1 %or5, %or6 + %or10 = or i1 %or7, %or8 + %or11 = or i1 %or9, %or10 + ret i1 %or11 +} + + +define i1 @test118(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 { +; GCN-LABEL: test118: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5 +; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7 +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_max3_f32 v0, v0, v2, v3 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, %C1 + %add2 = fadd nnan float %arg2, %C2 + %add3 = fadd nnan float %arg3, %C3 + %add4 = fadd nnan float %arg4, %C4 + %cmp1 = fcmp nnan ult float %add1, %C + %cmp2 = fcmp nnan ult float %add2, %C + %cmp3 = fcmp nnan ult float %add3, %C + %cmp4 = fcmp nnan ult float %add4, %C + %or1 = or i1 %cmp1, %cmp2 + %and1 = and i1 %cmp3, %cmp4 + %and2 = and i1 %or1, %and1 + ret i1 %and2 +} + +define i1 @test119(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 { +; GCN-LABEL: test119: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7 +; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5 +; GCN-NEXT: v_min_f32_e32 v2, v2, v3 +; GCN-NEXT: v_minmax_f32 v0, v0, v1, v2 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, %C1 + %add2 = fadd nnan float %arg2, %C2 + %add3 = fadd nnan float %arg3, %C3 + %add4 = fadd nnan float %arg4, %C4 + %cmp1 = fcmp nnan ult float %add1, %C + %cmp2 = fcmp nnan ult float %add2, %C + %cmp3 = fcmp nnan ult float %add3, %C + %cmp4 = fcmp nnan ult float %add4, %C + %or1 = or i1 %cmp1, %cmp2 + %and1 = or i1 %cmp3, %cmp4 + %and2 = and i1 %or1, %and1 + ret i1 %and2 +} + +define i1 @test120(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 { +; GCN-LABEL: test120: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7 +; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5 +; GCN-NEXT: v_max_f32_e32 v2, v2, v3 +; GCN-NEXT: v_min3_f32 v0, v0, v1, v2 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, %C1 + %add2 = fadd nnan float %arg2, %C2 + %add3 = fadd nnan float %arg3, %C3 + %add4 = fadd nnan float %arg4, %C4 + %cmp1 = fcmp nnan ult float %add1, %C + %cmp2 = fcmp nnan ult float %add2, %C + %cmp3 = fcmp nnan ult float %add3, %C + %cmp4 = fcmp nnan ult float %add4, %C + %or1 = or i1 %cmp1, %cmp2 + %and1 = and i1 %cmp3, %cmp4 + %and2 = or i1 %or1, %and1 + ret i1 %and2 +} + +define i1 @test121(float %arg1, float %arg2, float %arg3, float %arg4, float %C1, float %C2, float %C3, float %C4, float %C) #0 { +; GCN-LABEL: test121: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7 +; GCN-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v5 +; GCN-NEXT: v_max_f32_e32 v2, v2, v3 +; GCN-NEXT: v_maxmin_f32 v0, v0, v1, v2 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v8 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %add1 = fadd nnan float %arg1, %C1 + %add2 = fadd nnan float %arg2, %C2 + %add3 = fadd nnan float %arg3, %C3 + %add4 = fadd nnan float %arg4, %C4 + %cmp1 = fcmp nnan ult float %add1, %C + %cmp2 = fcmp nnan ult float %add2, %C + %cmp3 = fcmp nnan ult float %add3, %C + %cmp4 = fcmp nnan ult float %add4, %C + %or1 = and i1 %cmp1, %cmp2 + %and1 = and i1 %cmp3, %cmp4 + %and2 = or i1 %or1, %and1 + ret i1 %and2 +} + +define i1 @test122(double %arg1, double %arg2, double %arg3) #1 { +; GCN-LABEL: test122: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ult double %arg1, %arg3 + %cmp2 = fcmp nnan ult double %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test123(double %arg1, double %arg2, double %arg3) #1 { +; GCN-LABEL: test123: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ogt double %var1, %arg3 + %cmp2 = fcmp nnan ogt double %var2, %arg3 + %or1 = and i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test134(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test134: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %arg3 + %cmp2 = fcmp nnan ogt float %arg3, %arg2 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test135(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test135: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ult float %arg1, %arg3 + %cmp2 = fcmp nnan ugt float %arg3, %arg2 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test136(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test136: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ole double %var1, %arg3 + %cmp2 = fcmp nnan oge double %arg3, %var2 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test137(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test137: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan ule float %var1, %arg3 + %cmp2 = fcmp nnan uge float %arg3, %var2 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test138(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test138: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan olt float %arg1, %arg3 + %cmp2 = fcmp nnan olt float %arg2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test139(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test139: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ole double %arg1, %arg3 + %cmp2 = fcmp nnan ole double %arg2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test140(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test140: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ogt double %arg1, %arg3 + %cmp2 = fcmp nnan ogt double %arg2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test141(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test141: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan oge float %arg1, %arg3 + %cmp2 = fcmp nnan oge float %arg2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test142(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test142: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ugt double %arg1, %arg3 + %cmp2 = fcmp nnan ugt double %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test143(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test143: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan uge float %arg1, %arg3 + %cmp2 = fcmp nnan uge float %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test144(float %arg1, float %arg2, float %arg3) #0 { +; GCN-LABEL: test144: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ule float %arg1, %arg3 + %cmp2 = fcmp nnan ule float %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test145(double %arg1, double %arg2, double %arg3) #0 { +; GCN-LABEL: test145: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %cmp1 = fcmp nnan ult double %arg1, %arg3 + %cmp2 = fcmp nnan ult double %arg2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test146(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test146: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan olt float %var1, %arg3 + %cmp2 = fcmp nnan olt float %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test147(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test147: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_le_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ole double %var1, %arg3 + %cmp2 = fcmp nnan ole double %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test148(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test148: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ogt double %var1, %arg3 + %cmp2 = fcmp nnan ogt double %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test149(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test149: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan oge float %var1, %arg3 + %cmp2 = fcmp nnan oge float %var2, %arg3 + %and1 = and i1 %cmp1, %cmp2 + ret i1 %and1 +} + +define i1 @test150(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test150: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_gt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ugt double %var1, %arg3 + %cmp2 = fcmp nnan ugt double %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test151(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test151: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan uge float %var1, %arg3 + %cmp2 = fcmp nnan uge float %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test152(float %arg1, float %arg2, float %arg3) { +; GCN-LABEL: test152: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_min_f32_e32 v0, v0, v1 +; GCN-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan float @llvm.canonicalize.f32(float %arg1) + %var2 = call nnan float @llvm.canonicalize.f32(float %arg2) + %cmp1 = fcmp nnan ule float %var1, %arg3 + %cmp2 = fcmp nnan ule float %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +define i1 @test153(double %arg1, double %arg2, double %arg3) { +; GCN-LABEL: test153: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] +; GCN-NEXT: v_max_f64 v[2:3], v[2:3], v[2:3] +; GCN-NEXT: v_min_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: v_cmp_lt_f64_e32 vcc_lo, v[0:1], v[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GCN-NEXT: s_setpc_b64 s[30:31] + %var1 = call nnan double @llvm.canonicalize.f64(double %arg1) + %var2 = call nnan double @llvm.canonicalize.f64(double %arg2) + %cmp1 = fcmp nnan ult double %var1, %arg3 + %cmp2 = fcmp nnan ult double %var2, %arg3 + %or1 = or i1 %cmp1, %cmp2 + ret i1 %or1 +} + +declare double @llvm.canonicalize.f64(double) +declare float @llvm.canonicalize.f32(float) +declare half @llvm.canonicalize.f16(half) +declare <2 x half> @llvm.canonicalize.v2f16(<2 x half>) + +attributes #0 = { nounwind "amdgpu-ieee"="false" } +attributes #1 = { nounwind "no-nans-fp-math"="true" } diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll index a7a9851cc5c26..28a18ec3845e0 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll @@ -439,7 +439,7 @@ declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) #3 ; Function Attrs: nounwind readnone willreturn declare <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32>, i32, i32 immarg) #3 -attributes #0 = { "denormal-fp-math-f32"="preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } attributes #2 = { nounwind readnone speculatable willreturn } attributes #3 = { nounwind readonly willreturn } diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll index 3327ef0514fcd..65a1443f83c6e 100644 --- a/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll +++ b/llvm/test/CodeGen/AMDGPU/dagcombine-select.ll @@ -591,7 +591,7 @@ define amdgpu_kernel void @frem_constant_sel_constants(ptr addrspace(1) %p, i1 % ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v0, -4.0, s[0:1] ; GFX9-NEXT: s_mov_b32 s0, 0x40a00000 -; GFX9-NEXT: v_cmp_nlt_f32_e64 s[2:3], |v1|, s0 +; GFX9-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, s0 ; GFX9-NEXT: s_and_b64 vcc, exec, s[2:3] ; GFX9-NEXT: s_cbranch_vccz .LBB26_2 ; GFX9-NEXT: ; %bb.1: ; %frem.else @@ -665,7 +665,7 @@ define amdgpu_kernel void @frem_constant_sel_constants(ptr addrspace(1) %p, i1 % ; GFX942-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX942-NEXT: v_cndmask_b32_e64 v1, v0, -4.0, s[0:1] ; GFX942-NEXT: s_mov_b32 s0, 0x40a00000 -; GFX942-NEXT: v_cmp_nlt_f32_e64 s[2:3], |v1|, s0 +; GFX942-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, s0 ; GFX942-NEXT: s_and_b64 vcc, exec, s[2:3] ; GFX942-NEXT: s_cbranch_vccz .LBB26_2 ; GFX942-NEXT: ; %bb.1: ; %frem.else diff --git a/llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll b/llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll new file mode 100644 index 0000000000000..8c5bd2cf21913 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/debug-independence-scheduleRegion.ll @@ -0,0 +1,57 @@ +; Ensure that compiling with and without debug generates identical code. +; Test that scheduleRegion in iterative scheduler only updates LiveIntervals if non-debug +; instructions are reordered. + +; RUN: opt %s -strip-debug -o %t.no_debug.ll -S +; RUN: llc -O2 -mcpu=gfx1250 < %s -misched=gcn-iterative-ilp -filetype=obj -o %t.with_debug.o +; RUN: llc -O2 -mcpu=gfx1250 < %t.no_debug.ll -misched=gcn-iterative-ilp -filetype=obj -o %t.no_debug.o +; RUN: llvm-strip %t.with_debug.o %t.no_debug.o +; RUN: cmp %t.with_debug.o %t.no_debug.o + +target triple = "amdgcn-amd-amdhsa" + +declare void @llvm.amdgcn.s.barrier() #0 + +define amdgpu_kernel void @_test_scheduleRegion(<2 x float> %f9, <2 x float> %f15, <14 x float> %f16, <2 x float> %f14, <2 x float> %f33, i1 %cmp59.13, <2 x float> %f48, ptr addrspace(1) %arrayidx.1) { +entry: + #dbg_value(ptr addrspace(1) null, !4, !DIExpression(), !13) + tail call void @llvm.amdgcn.s.barrier() + fence acquire + store float 0.000000e+00, ptr addrspace(3) null, align 4 + %f26 = fsub <2 x float> %f14, %f33 + %f27 = shufflevector <2 x float> %f26, <2 x float> zeroinitializer, <14 x i32> + %f28 = shufflevector <14 x float> zeroinitializer, <14 x float> %f27, <14 x i32> + %f31 = shufflevector <14 x float> %f28, <14 x float> zeroinitializer, <2 x i32> + %f34 = fsub <2 x float> %f31, %f15 + store float 0.000000e+00, ptr addrspace(1) null, align 4 + store float 0.000000e+00, ptr addrspace(1) %arrayidx.1, align 4 + store float 0.000000e+00, ptr addrspace(1) null, align 4 + %f49 = fsub <2 x float> %f34, %f48 + %f61 = fsub <2 x float> %f49, %f9 + %f64 = shufflevector <2 x float> %f61, <2 x float> zeroinitializer, <14 x i32> + %f65 = shufflevector <14 x float> zeroinitializer, <14 x float> %f64, <14 x i32> + %promotealloca.13 = select i1 %cmp59.13, <14 x float> zeroinitializer, <14 x float> %f65 + %f67 = extractelement <14 x float> %promotealloca.13, i64 9 + store float %f67, ptr addrspace(1) %arrayidx.1, align 4 + ret void +} + +attributes #0 = { convergent nocallback nofree nounwind willreturn } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "AMD clang version 22.0.0git (ssh://github-emu/AMD-Lightning-Internal/llvm-project 25425 c51a87b7a53a3e8f308402aaffa3ecbc2953305a)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, imports: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "/tmp", checksumkind: CSK_MD5, checksum: "cc205700bf3536fe4ff21a07daf7e01d") +!2 = !{} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !DILocalVariable(name: "info", scope: !5, file: !6, line: 162, type: !11) +!5 = distinct !DISubprogram(name: "test_scheduleRegion", linkageName: "_test_scheduleRegion", scope: !7, file: !6, line: 142, type: !9, scopeLine: 150, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, templateParams: !2, retainedNodes: !2) +!6 = !DIFile(filename: "kernels.hpp", directory: "/tmp") +!7 = !DINamespace(name: "v33200", scope: !8, exportSymbols: true) +!8 = !DINamespace(name: "solve", scope: null) +!9 = distinct !DISubroutineType(types: !10) +!10 = !{null} +!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64) +!12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!13 = !DILocation(line: 0, scope: !5) diff --git a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll index b63fff38f34f6..e9146c0d241ba 100644 --- a/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll +++ b/llvm/test/CodeGen/AMDGPU/default-fp-mode.ll @@ -172,17 +172,18 @@ declare void @llvm.amdgcn.kill(i1) attributes #0 = { nounwind "target-cpu"="tahiti" } attributes #1 = { nounwind "target-cpu"="fiji" } -attributes #2 = { nounwind "denormal-fp-math"="ieee,ieee" } -attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } -attributes #4 = { nounwind "denormal-fp-math"="ieee,ieee" } -attributes #5 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #6 = { nounwind "denormal-fp-math"="ieee,ieee" } -attributes #7 = { nounwind "denormal-fp-math-f32"="ieee,ieee" "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #8 = { nounwind "denormal-fp-math"="ieee,ieee" } -attributes #9 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #10 = { nounwind "denormal-fp-math"="preserve-sign,ieee" } -attributes #11 = { nounwind "denormal-fp-math"="ieee,preserve-sign" } -attributes #12 = { nounwind "denormal-fp-math-f32"="ieee,preserve-sign" "denormal-fp-math"="ieee,ieee" } -attributes #13 = { nounwind "denormal-fp-math-f32"="preserve-sign,ieee" "denormal-fp-math"="ieee,ieee" } -attributes #14 = { nounwind "denormal-fp-math"="ieee,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" } -attributes #15 = { nounwind "denormal-fp-math"="preserve-sign,ieee" "denormal-fp-math-f32"="ieee,ieee" } + +attributes #2 = { nounwind denormal_fpenv(ieee) } +attributes #3 = { nounwind denormal_fpenv(float:ieee|ieee) } +attributes #4 = { nounwind denormal_fpenv(ieee) } +attributes #5 = { nounwind denormal_fpenv(preservesign) } +attributes #6 = { nounwind denormal_fpenv(ieee) } +attributes #7 = { nounwind denormal_fpenv(preservesign, float:ieee) } +attributes #8 = { nounwind denormal_fpenv(ieee) } +attributes #9 = { nounwind denormal_fpenv(float:preservesign|preservesign) } +attributes #10 = { nounwind denormal_fpenv(preservesign|ieee) } +attributes #11 = { nounwind denormal_fpenv(ieee|preservesign) } +attributes #12 = { nounwind denormal_fpenv(ieee, float:ieee|preservesign) } +attributes #13 = { nounwind denormal_fpenv(ieee, float:preservesign|ieee) } +attributes #14 = { nounwind denormal_fpenv(ieee|preservesign, float:ieee) } +attributes #15 = { nounwind denormal_fpenv(preservesign|ieee, float:ieee) } diff --git a/llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll b/llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll index 2e7247b3b924b..8105ba3cc10e1 100644 --- a/llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll +++ b/llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll @@ -104,6 +104,7 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1151 < %s | FileCheck --check-prefixes=GFX1151 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1152 < %s | FileCheck --check-prefixes=GFX1152 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1153 < %s | FileCheck --check-prefixes=GFX1153 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1170 < %s | FileCheck --check-prefixes=GFX1170 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GFX1200 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1201 < %s | FileCheck --check-prefixes=GFX1201 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250 %s @@ -204,6 +205,7 @@ ; GFX1151: .amdgcn_target "amdgcn-amd-amdhsa--gfx1151" ; GFX1152: .amdgcn_target "amdgcn-amd-amdhsa--gfx1152" ; GFX1153: .amdgcn_target "amdgcn-amd-amdhsa--gfx1153" +; GFX1170: .amdgcn_target "amdgcn-amd-amdhsa--gfx1170" ; GFX1200: .amdgcn_target "amdgcn-amd-amdhsa--gfx1200" ; GFX1201: .amdgcn_target "amdgcn-amd-amdhsa--gfx1201" ; GFX1250: .amdgcn_target "amdgcn-amd-amdhsa--gfx1250" diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll index d5b5ab6e457f9..5a4aa4effac00 100644 --- a/llvm/test/CodeGen/AMDGPU/div_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll @@ -4373,6 +4373,115 @@ define i128 @v_sdiv_i128_v_pow2k(i128 %lhs) { ret i128 %div } +define i128 @v_sdiv_exact_i128_v_pow2k(i128 %lhs) { +; GFX9-LABEL: v_sdiv_exact_i128_v_pow2k: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_ashrrev_i32_e32 v4, 31, v3 +; GFX9-NEXT: v_mov_b32_e32 v5, v4 +; GFX9-NEXT: v_lshrrev_b64 v[4:5], 31, v[4:5] +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v1, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[2:3] +; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v4 +; GFX9-NEXT: v_or_b32_e32 v0, v2, v0 +; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v3 +; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-O0-LABEL: v_sdiv_exact_i128_v_pow2k: +; GFX9-O0: ; %bb.0: +; GFX9-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v0 +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: s_waitcnt vmcnt(0) +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-O0-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v2 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v4 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v5 +; GFX9-O0-NEXT: s_mov_b32 s4, 63 +; GFX9-O0-NEXT: v_ashrrev_i64 v[4:5], s4, v[4:5] +; GFX9-O0-NEXT: s_mov_b32 s5, 31 +; GFX9-O0-NEXT: v_lshrrev_b64 v[6:7], s5, v[4:5] +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v6 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v7 +; GFX9-O0-NEXT: s_mov_b64 s[8:9], 0 +; GFX9-O0-NEXT: s_mov_b32 s6, s8 +; GFX9-O0-NEXT: s_mov_b32 s4, s9 +; GFX9-O0-NEXT: v_add_co_u32_e32 v0, vcc, v0, v5 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v4, s6 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v5, vcc, v2, v4, vcc +; GFX9-O0-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-O0-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3 +; GFX9-O0-NEXT: s_mov_b32 s4, 33 +; GFX9-O0-NEXT: v_lshrrev_b64 v[0:1], s4, v[0:1] +; GFX9-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec +; GFX9-O0-NEXT: v_lshl_or_b32 v0, v2, s5, v0 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v5 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v6 +; GFX9-O0-NEXT: v_ashrrev_i64 v[3:4], s4, v[3:4] +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v6 +; GFX9-O0-NEXT: s_mov_b32 s4, 1 +; GFX9-O0-NEXT: v_alignbit_b32 v1, v1, v2, s4 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 +; GFX9-O0-NEXT: s_mov_b32 s4, 32 +; GFX9-O0-NEXT: v_lshrrev_b64 v[3:4], s4, v[3:4] +; GFX9-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr3_vgpr4 killed $exec +; GFX9-O0-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-G-LABEL: v_sdiv_exact_i128_v_pow2k: +; GFX9-G: ; %bb.0: +; GFX9-G-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-G-NEXT: v_mov_b32_e32 v4, v1 +; GFX9-G-NEXT: v_lshlrev_b64 v[0:1], 31, v[2:3] +; GFX9-G-NEXT: v_lshrrev_b32_e32 v2, 1, v4 +; GFX9-G-NEXT: v_ashrrev_i32_e32 v4, 31, v3 +; GFX9-G-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX9-G-NEXT: v_ashrrev_i32_e32 v2, 1, v3 +; GFX9-G-NEXT: v_mov_b32_e32 v3, v4 +; GFX9-G-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-G-O0-LABEL: v_sdiv_exact_i128_v_pow2k: +; GFX9-G-O0: ; %bb.0: +; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v2 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v3 +; GFX9-G-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec +; GFX9-G-O0-NEXT: v_mov_b32_e32 v6, v4 +; GFX9-G-O0-NEXT: s_mov_b32 s4, 1 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v2, v0, v1 +; GFX9-G-O0-NEXT: s_mov_b32 s4, 31 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-G-O0-NEXT: v_lshlrev_b64 v[5:6], v0, v[5:6] +; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v5 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v6 +; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v2 +; GFX9-G-O0-NEXT: s_mov_b32 s4, 31 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v3, v2, v4 +; GFX9-G-O0-NEXT: s_mov_b32 s4, 1 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v2, v2, v4 +; GFX9-G-O0-NEXT: s_setpc_b64 s[30:31] + %div = sdiv exact i128 %lhs, 8589934592 + ret i128 %div +} + define i128 @v_udiv_i128_v_pow2k(i128 %lhs) { ; GFX9-LABEL: v_udiv_i128_v_pow2k: ; GFX9: ; %bb.0: @@ -4445,3 +4554,76 @@ define i128 @v_udiv_i128_v_pow2k(i128 %lhs) { %div = udiv i128 %lhs, 8589934592 ret i128 %div } + +define i128 @v_udiv_exact_i128_v_pow2k(i128 %lhs) { +; GFX9-LABEL: v_udiv_exact_i128_v_pow2k: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v4, v1 +; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[2:3] +; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v4 +; GFX9-NEXT: v_or_b32_e32 v0, v2, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v3 +; GFX9-NEXT: v_mov_b32_e32 v3, 0 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-O0-LABEL: v_udiv_exact_i128_v_pow2k: +; GFX9-O0: ; %bb.0: +; GFX9-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v2 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v1 +; GFX9-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v2 +; GFX9-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v5 +; GFX9-O0-NEXT: s_mov_b32 s4, 33 +; GFX9-O0-NEXT: v_lshrrev_b64 v[0:1], s4, v[0:1] +; GFX9-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 killed $vgpr0_vgpr1 killed $exec +; GFX9-O0-NEXT: s_mov_b32 s5, 31 +; GFX9-O0-NEXT: v_lshl_or_b32 v0, v4, s5, v0 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v5 +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v6 +; GFX9-O0-NEXT: v_lshrrev_b64 v[2:3], s4, v[1:2] +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v6 +; GFX9-O0-NEXT: s_mov_b32 s4, 1 +; GFX9-O0-NEXT: v_alignbit_b32 v1, v1, v4, s4 +; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v3, 0 +; GFX9-O0-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-G-LABEL: v_udiv_exact_i128_v_pow2k: +; GFX9-G: ; %bb.0: +; GFX9-G-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-G-NEXT: v_mov_b32_e32 v4, v1 +; GFX9-G-NEXT: v_lshlrev_b64 v[0:1], 31, v[2:3] +; GFX9-G-NEXT: v_lshrrev_b32_e32 v2, 1, v4 +; GFX9-G-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX9-G-NEXT: v_lshrrev_b32_e32 v2, 1, v3 +; GFX9-G-NEXT: v_mov_b32_e32 v3, 0 +; GFX9-G-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-G-O0-LABEL: v_udiv_exact_i128_v_pow2k: +; GFX9-G-O0: ; %bb.0: +; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, v2 +; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec +; GFX9-G-O0-NEXT: v_mov_b32_e32 v5, v3 +; GFX9-G-O0-NEXT: s_mov_b32 s4, 1 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v2, v0, v1 +; GFX9-G-O0-NEXT: s_mov_b32 s4, 31 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-G-O0-NEXT: v_lshlrev_b64 v[4:5], v0, v[4:5] +; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v4 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v5 +; GFX9-G-O0-NEXT: v_or_b32_e64 v0, v0, v2 +; GFX9-G-O0-NEXT: s_mov_b32 s4, 1 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-G-O0-NEXT: v_lshrrev_b32_e64 v2, v2, v3 +; GFX9-G-O0-NEXT: s_mov_b32 s4, 0 +; GFX9-G-O0-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-G-O0-NEXT: s_setpc_b64 s[30:31] + %div = udiv exact i128 %lhs, 8589934592 + ret i128 %div +} diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll index 1e96b63bcd321..2b434c54da9c2 100644 --- a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll @@ -822,6 +822,688 @@ define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ret <2 x i128> %shl } +define <2 x i128> @v_sdiv_v2i128_v_pow2k(<2 x i128> %lhs) { +; SDAG-LABEL: v_sdiv_v2i128_v_pow2k: +; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases +; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-NEXT: v_ashrrev_i32_e32 v18, 31, v3 +; SDAG-NEXT: v_sub_i32_e32 v8, vcc, 0, v0 +; SDAG-NEXT: v_mov_b32_e32 v9, 0 +; SDAG-NEXT: s_mov_b64 s[6:7], 0x7f +; SDAG-NEXT: v_mov_b32_e32 v19, v18 +; SDAG-NEXT: v_subb_u32_e32 v10, vcc, 0, v1, vcc +; SDAG-NEXT: v_subb_u32_e32 v11, vcc, 0, v2, vcc +; SDAG-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3] +; SDAG-NEXT: v_cndmask_b32_e64 v13, v1, v10, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v12, v0, v8, s[4:5] +; SDAG-NEXT: v_subb_u32_e32 v0, vcc, 0, v3, vcc +; SDAG-NEXT: v_cndmask_b32_e64 v10, v2, v11, s[4:5] +; SDAG-NEXT: v_ffbh_u32_e32 v1, v12 +; SDAG-NEXT: v_ffbh_u32_e32 v2, v13 +; SDAG-NEXT: v_cndmask_b32_e64 v11, v3, v0, s[4:5] +; SDAG-NEXT: v_or_b32_e32 v0, v12, v10 +; SDAG-NEXT: v_ffbh_u32_e32 v3, v10 +; SDAG-NEXT: v_add_i32_e32 v8, vcc, 32, v1 +; SDAG-NEXT: v_or_b32_e32 v1, v13, v11 +; SDAG-NEXT: v_add_i32_e32 v3, vcc, 32, v3 +; SDAG-NEXT: v_ffbh_u32_e32 v14, v11 +; SDAG-NEXT: v_min_u32_e32 v2, v8, v2 +; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] +; SDAG-NEXT: v_min_u32_e32 v0, v3, v14 +; SDAG-NEXT: v_add_i32_e32 v1, vcc, 64, v2 +; SDAG-NEXT: v_addc_u32_e64 v2, s[8:9], 0, 0, vcc +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; SDAG-NEXT: v_cndmask_b32_e64 v3, v2, 0, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; SDAG-NEXT: v_sub_i32_e32 v2, vcc, 0x5e, v0 +; SDAG-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc +; SDAG-NEXT: v_xor_b32_e32 v0, 0x7f, v2 +; SDAG-NEXT: v_subb_u32_e32 v8, vcc, 0, v9, vcc +; SDAG-NEXT: v_cmp_lt_u64_e64 s[6:7], s[6:7], v[2:3] +; SDAG-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7] +; SDAG-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc +; SDAG-NEXT: v_or_b32_e32 v0, v0, v8 +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; SDAG-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; SDAG-NEXT: v_or_b32_e32 v1, v3, v9 +; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] +; SDAG-NEXT: v_cndmask_b32_e32 v14, v15, v14, vcc +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; SDAG-NEXT: v_and_b32_e32 v0, 1, v14 +; SDAG-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0 +; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v1, v11, 0, s[4:5] +; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; SDAG-NEXT: v_cndmask_b32_e64 v0, v10, 0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v16, v13, 0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v17, v12, 0, s[4:5] +; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc +; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; SDAG-NEXT: s_cbranch_execz .LBB1_6 +; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 +; SDAG-NEXT: v_add_i32_e32 v20, vcc, 1, v2 +; SDAG-NEXT: v_sub_i32_e64 v0, s[4:5], 63, v2 +; SDAG-NEXT: v_addc_u32_e32 v21, vcc, 0, v3, vcc +; SDAG-NEXT: v_lshl_b64 v[0:1], v[12:13], v0 +; SDAG-NEXT: v_addc_u32_e32 v22, vcc, 0, v8, vcc +; SDAG-NEXT: v_addc_u32_e32 v23, vcc, 0, v9, vcc +; SDAG-NEXT: v_or_b32_e32 v8, v20, v22 +; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 0x7f, v2 +; SDAG-NEXT: v_or_b32_e32 v9, v21, v23 +; SDAG-NEXT: v_lshl_b64 v[2:3], v[10:11], v16 +; SDAG-NEXT: v_sub_i32_e32 v17, vcc, 64, v16 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[12:13], v16 +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; SDAG-NEXT: v_lshr_b64 v[8:9], v[12:13], v17 +; SDAG-NEXT: v_or_b32_e32 v3, v3, v9 +; SDAG-NEXT: v_or_b32_e32 v2, v2, v8 +; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v16 +; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v9, 0, v15, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v8, 0, v14, s[4:5] +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16 +; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v11, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v10, s[4:5] +; SDAG-NEXT: v_mov_b32_e32 v2, 0 +; SDAG-NEXT: v_mov_b32_e32 v3, 0 +; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc +; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] +; SDAG-NEXT: s_cbranch_execz .LBB1_5 +; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 +; SDAG-NEXT: v_lshr_b64 v[2:3], v[12:13], v20 +; SDAG-NEXT: v_sub_i32_e32 v14, vcc, 64, v20 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[10:11], v14 +; SDAG-NEXT: v_or_b32_e32 v15, v3, v15 +; SDAG-NEXT: v_or_b32_e32 v14, v2, v14 +; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v20 +; SDAG-NEXT: v_subrev_i32_e64 v2, s[4:5], 64, v20 +; SDAG-NEXT: v_lshr_b64 v[2:3], v[10:11], v2 +; SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v15, vcc +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v20 +; SDAG-NEXT: v_cndmask_b32_e64 v13, v3, v13, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v14, vcc +; SDAG-NEXT: v_cndmask_b32_e64 v12, v2, v12, s[4:5] +; SDAG-NEXT: v_lshr_b64 v[2:3], v[10:11], v20 +; SDAG-NEXT: v_cndmask_b32_e32 v15, 0, v3, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v14, 0, v2, vcc +; SDAG-NEXT: v_mov_b32_e32 v10, 0 +; SDAG-NEXT: v_mov_b32_e32 v11, 0 +; SDAG-NEXT: s_mov_b64 s[4:5], 0 +; SDAG-NEXT: v_mov_b32_e32 v3, 0 +; SDAG-NEXT: v_mov_b32_e32 v16, 0 +; SDAG-NEXT: v_mov_b32_e32 v17, 0 +; SDAG-NEXT: .LBB1_3: ; %udiv-do-while3 +; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; SDAG-NEXT: v_lshrrev_b32_e32 v2, 31, v9 +; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v24, 31, v13 +; SDAG-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v25, 31, v1 +; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; SDAG-NEXT: v_or_b32_e32 v9, v17, v9 +; SDAG-NEXT: v_or_b32_e32 v8, v16, v8 +; SDAG-NEXT: v_or_b32_e32 v14, v14, v24 +; SDAG-NEXT: v_or_b32_e32 v12, v12, v25 +; SDAG-NEXT: v_or_b32_e32 v0, v0, v2 +; SDAG-NEXT: v_sub_i32_e32 v2, vcc, -1, v12 +; SDAG-NEXT: v_subb_u32_e32 v2, vcc, 1, v13, vcc +; SDAG-NEXT: v_subb_u32_e32 v2, vcc, 0, v14, vcc +; SDAG-NEXT: v_subb_u32_e32 v2, vcc, 0, v15, vcc +; SDAG-NEXT: v_ashrrev_i32_e32 v2, 31, v2 +; SDAG-NEXT: v_subrev_i32_e32 v12, vcc, 0, v12 +; SDAG-NEXT: v_and_b32_e32 v16, 2, v2 +; SDAG-NEXT: v_and_b32_e32 v2, 1, v2 +; SDAG-NEXT: v_subb_u32_e32 v13, vcc, v13, v16, vcc +; SDAG-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v14, vcc +; SDAG-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v15, vcc +; SDAG-NEXT: v_add_i32_e32 v20, vcc, -1, v20 +; SDAG-NEXT: v_addc_u32_e32 v21, vcc, -1, v21, vcc +; SDAG-NEXT: v_addc_u32_e32 v22, vcc, -1, v22, vcc +; SDAG-NEXT: v_addc_u32_e32 v23, vcc, -1, v23, vcc +; SDAG-NEXT: v_or_b32_e32 v16, v20, v22 +; SDAG-NEXT: v_or_b32_e32 v17, v21, v23 +; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17] +; SDAG-NEXT: v_or_b32_e32 v1, v11, v1 +; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; SDAG-NEXT: v_or_b32_e32 v0, v10, v0 +; SDAG-NEXT: v_mov_b32_e32 v17, v3 +; SDAG-NEXT: v_mov_b32_e32 v16, v2 +; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] +; SDAG-NEXT: s_cbranch_execnz .LBB1_3 +; SDAG-NEXT: ; %bb.4: ; %Flow13 +; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] +; SDAG-NEXT: .LBB1_5: ; %Flow14 +; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] +; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v10, 31, v9 +; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; SDAG-NEXT: v_or_b32_e32 v0, v0, v10 +; SDAG-NEXT: v_or_b32_e32 v16, v3, v9 +; SDAG-NEXT: v_or_b32_e32 v17, v2, v8 +; SDAG-NEXT: .LBB1_6: ; %Flow16 +; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] +; SDAG-NEXT: v_ashrrev_i32_e32 v20, 31, v7 +; SDAG-NEXT: v_sub_i32_e32 v2, vcc, 0, v4 +; SDAG-NEXT: v_mov_b32_e32 v12, 0 +; SDAG-NEXT: s_mov_b64 s[6:7], 0x7f +; SDAG-NEXT: v_mov_b32_e32 v21, v20 +; SDAG-NEXT: v_subb_u32_e32 v3, vcc, 0, v5, vcc +; SDAG-NEXT: v_subb_u32_e32 v8, vcc, 0, v6, vcc +; SDAG-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v11, v5, v3, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v10, v4, v2, s[4:5] +; SDAG-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc +; SDAG-NEXT: v_cndmask_b32_e64 v8, v6, v8, s[4:5] +; SDAG-NEXT: v_ffbh_u32_e32 v3, v10 +; SDAG-NEXT: v_ffbh_u32_e32 v4, v11 +; SDAG-NEXT: v_cndmask_b32_e64 v9, v7, v2, s[4:5] +; SDAG-NEXT: v_or_b32_e32 v2, v10, v8 +; SDAG-NEXT: v_ffbh_u32_e32 v5, v8 +; SDAG-NEXT: v_add_i32_e32 v6, vcc, 32, v3 +; SDAG-NEXT: v_or_b32_e32 v3, v11, v9 +; SDAG-NEXT: v_add_i32_e32 v5, vcc, 32, v5 +; SDAG-NEXT: v_ffbh_u32_e32 v7, v9 +; SDAG-NEXT: v_min_u32_e32 v4, v6, v4 +; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[2:3] +; SDAG-NEXT: v_min_u32_e32 v2, v5, v7 +; SDAG-NEXT: v_add_i32_e32 v3, vcc, 64, v4 +; SDAG-NEXT: v_addc_u32_e64 v4, s[8:9], 0, 0, vcc +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; SDAG-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; SDAG-NEXT: v_sub_i32_e32 v2, vcc, 0x5e, v2 +; SDAG-NEXT: v_subb_u32_e32 v3, vcc, 0, v4, vcc +; SDAG-NEXT: v_xor_b32_e32 v6, 0x7f, v2 +; SDAG-NEXT: v_subb_u32_e32 v4, vcc, 0, v12, vcc +; SDAG-NEXT: v_cmp_lt_u64_e64 s[6:7], s[6:7], v[2:3] +; SDAG-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[6:7] +; SDAG-NEXT: v_subb_u32_e32 v5, vcc, 0, v12, vcc +; SDAG-NEXT: v_or_b32_e32 v6, v6, v4 +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc +; SDAG-NEXT: v_or_b32_e32 v7, v3, v5 +; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[4:5] +; SDAG-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; SDAG-NEXT: v_and_b32_e32 v6, 1, v12 +; SDAG-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v6 +; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v13, v9, 0, s[4:5] +; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; SDAG-NEXT: v_cndmask_b32_e64 v12, v8, 0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v7, v11, 0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v6, v10, 0, s[4:5] +; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc +; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; SDAG-NEXT: s_cbranch_execz .LBB1_12 +; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 +; SDAG-NEXT: v_add_i32_e32 v22, vcc, 1, v2 +; SDAG-NEXT: v_sub_i32_e64 v6, s[4:5], 63, v2 +; SDAG-NEXT: v_addc_u32_e32 v23, vcc, 0, v3, vcc +; SDAG-NEXT: v_lshl_b64 v[6:7], v[10:11], v6 +; SDAG-NEXT: v_addc_u32_e32 v24, vcc, 0, v4, vcc +; SDAG-NEXT: v_addc_u32_e32 v25, vcc, 0, v5, vcc +; SDAG-NEXT: v_or_b32_e32 v3, v22, v24 +; SDAG-NEXT: v_sub_i32_e32 v5, vcc, 0x7f, v2 +; SDAG-NEXT: v_or_b32_e32 v4, v23, v25 +; SDAG-NEXT: v_lshl_b64 v[12:13], v[8:9], v5 +; SDAG-NEXT: v_sub_i32_e32 v2, vcc, 64, v5 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[10:11], v5 +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[3:4] +; SDAG-NEXT: v_lshr_b64 v[2:3], v[10:11], v2 +; SDAG-NEXT: v_or_b32_e32 v3, v13, v3 +; SDAG-NEXT: v_or_b32_e32 v2, v12, v2 +; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v5 +; SDAG-NEXT: v_cndmask_b32_e64 v4, v7, v3, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v6, v6, v2, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v15, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, v14, s[4:5] +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 +; SDAG-NEXT: v_cndmask_b32_e64 v5, v4, v9, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v4, v6, v8, s[4:5] +; SDAG-NEXT: v_mov_b32_e32 v6, 0 +; SDAG-NEXT: v_mov_b32_e32 v7, 0 +; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc +; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] +; SDAG-NEXT: s_cbranch_execz .LBB1_11 +; SDAG-NEXT: ; %bb.8: ; %udiv-preheader +; SDAG-NEXT: v_lshr_b64 v[6:7], v[10:11], v22 +; SDAG-NEXT: v_sub_i32_e32 v12, vcc, 64, v22 +; SDAG-NEXT: v_lshl_b64 v[12:13], v[8:9], v12 +; SDAG-NEXT: v_or_b32_e32 v13, v7, v13 +; SDAG-NEXT: v_or_b32_e32 v12, v6, v12 +; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v22 +; SDAG-NEXT: v_subrev_i32_e64 v6, s[4:5], 64, v22 +; SDAG-NEXT: v_lshr_b64 v[6:7], v[8:9], v6 +; SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v22 +; SDAG-NEXT: v_cndmask_b32_e64 v11, v7, v11, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc +; SDAG-NEXT: v_cndmask_b32_e64 v10, v6, v10, s[4:5] +; SDAG-NEXT: v_lshr_b64 v[6:7], v[8:9], v22 +; SDAG-NEXT: v_cndmask_b32_e32 v13, 0, v7, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v12, 0, v6, vcc +; SDAG-NEXT: v_mov_b32_e32 v8, 0 +; SDAG-NEXT: v_mov_b32_e32 v9, 0 +; SDAG-NEXT: s_mov_b64 s[4:5], 0 +; SDAG-NEXT: v_mov_b32_e32 v7, 0 +; SDAG-NEXT: v_mov_b32_e32 v14, 0 +; SDAG-NEXT: v_mov_b32_e32 v15, 0 +; SDAG-NEXT: .LBB1_9: ; %udiv-do-while +; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; SDAG-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v6, 31, v11 +; SDAG-NEXT: v_or_b32_e32 v12, v12, v6 +; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v6, 31, v5 +; SDAG-NEXT: v_or_b32_e32 v10, v10, v6 +; SDAG-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v6, 31, v3 +; SDAG-NEXT: v_or_b32_e32 v4, v4, v6 +; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 +; SDAG-NEXT: v_or_b32_e32 v5, v9, v5 +; SDAG-NEXT: v_or_b32_e32 v4, v8, v4 +; SDAG-NEXT: v_or_b32_e32 v3, v15, v3 +; SDAG-NEXT: v_or_b32_e32 v2, v14, v2 +; SDAG-NEXT: v_sub_i32_e32 v6, vcc, -1, v10 +; SDAG-NEXT: v_subb_u32_e32 v6, vcc, 1, v11, vcc +; SDAG-NEXT: v_subb_u32_e32 v6, vcc, 0, v12, vcc +; SDAG-NEXT: v_subb_u32_e32 v6, vcc, 0, v13, vcc +; SDAG-NEXT: v_ashrrev_i32_e32 v14, 31, v6 +; SDAG-NEXT: v_and_b32_e32 v6, 1, v14 +; SDAG-NEXT: v_and_b32_e32 v14, 2, v14 +; SDAG-NEXT: v_subrev_i32_e32 v10, vcc, 0, v10 +; SDAG-NEXT: v_subb_u32_e32 v11, vcc, v11, v14, vcc +; SDAG-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v12, vcc +; SDAG-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v13, vcc +; SDAG-NEXT: v_add_i32_e32 v22, vcc, -1, v22 +; SDAG-NEXT: v_addc_u32_e32 v23, vcc, -1, v23, vcc +; SDAG-NEXT: v_addc_u32_e32 v24, vcc, -1, v24, vcc +; SDAG-NEXT: v_addc_u32_e32 v25, vcc, -1, v25, vcc +; SDAG-NEXT: v_or_b32_e32 v15, v23, v25 +; SDAG-NEXT: v_or_b32_e32 v14, v22, v24 +; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] +; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; SDAG-NEXT: v_mov_b32_e32 v15, v7 +; SDAG-NEXT: v_mov_b32_e32 v14, v6 +; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] +; SDAG-NEXT: s_cbranch_execnz .LBB1_9 +; SDAG-NEXT: ; %bb.10: ; %Flow +; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] +; SDAG-NEXT: .LBB1_11: ; %Flow11 +; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] +; SDAG-NEXT: v_lshl_b64 v[12:13], v[4:5], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v3 +; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 +; SDAG-NEXT: v_or_b32_e32 v12, v12, v4 +; SDAG-NEXT: v_or_b32_e32 v7, v7, v3 +; SDAG-NEXT: v_or_b32_e32 v6, v6, v2 +; SDAG-NEXT: .LBB1_12: ; %Flow12 +; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] +; SDAG-NEXT: v_xor_b32_e32 v3, v1, v19 +; SDAG-NEXT: v_xor_b32_e32 v2, v0, v18 +; SDAG-NEXT: v_xor_b32_e32 v1, v16, v19 +; SDAG-NEXT: v_xor_b32_e32 v0, v17, v18 +; SDAG-NEXT: v_xor_b32_e32 v8, v13, v21 +; SDAG-NEXT: v_xor_b32_e32 v9, v12, v20 +; SDAG-NEXT: v_xor_b32_e32 v5, v7, v21 +; SDAG-NEXT: v_sub_i32_e32 v0, vcc, v0, v18 +; SDAG-NEXT: v_subb_u32_e32 v1, vcc, v1, v19, vcc +; SDAG-NEXT: v_subb_u32_e32 v2, vcc, v2, v18, vcc +; SDAG-NEXT: v_subb_u32_e32 v3, vcc, v3, v19, vcc +; SDAG-NEXT: v_xor_b32_e32 v4, v6, v20 +; SDAG-NEXT: v_sub_i32_e32 v4, vcc, v4, v20 +; SDAG-NEXT: v_subb_u32_e32 v5, vcc, v5, v21, vcc +; SDAG-NEXT: v_subb_u32_e32 v6, vcc, v9, v20, vcc +; SDAG-NEXT: v_subb_u32_e32 v7, vcc, v8, v21, vcc +; SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-LABEL: v_sdiv_v2i128_v_pow2k: +; GISEL: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases +; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-NEXT: s_mov_b64 s[8:9], 0 +; GISEL-NEXT: v_ashrrev_i32_e32 v18, 31, v3 +; GISEL-NEXT: v_mov_b32_e32 v14, 0x5e +; GISEL-NEXT: v_mov_b32_e32 v8, 0x7f +; GISEL-NEXT: v_mov_b32_e32 v9, 0 +; GISEL-NEXT: v_xor_b32_e32 v0, v18, v0 +; GISEL-NEXT: v_xor_b32_e32 v1, v18, v1 +; GISEL-NEXT: v_xor_b32_e32 v2, v18, v2 +; GISEL-NEXT: v_xor_b32_e32 v3, v18, v3 +; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v0, v18 +; GISEL-NEXT: v_subb_u32_e32 v11, vcc, v1, v18, vcc +; GISEL-NEXT: v_subb_u32_e32 v12, vcc, v2, v18, vcc +; GISEL-NEXT: v_subb_u32_e32 v13, vcc, v3, v18, vcc +; GISEL-NEXT: v_ffbh_u32_e32 v2, v11 +; GISEL-NEXT: v_ffbh_u32_e32 v3, v10 +; GISEL-NEXT: v_or_b32_e32 v0, v10, v12 +; GISEL-NEXT: v_or_b32_e32 v1, v11, v13 +; GISEL-NEXT: v_add_i32_e32 v3, vcc, 32, v3 +; GISEL-NEXT: v_ffbh_u32_e32 v15, v13 +; GISEL-NEXT: v_ffbh_u32_e32 v16, v12 +; GISEL-NEXT: v_min_u32_e32 v2, v2, v3 +; GISEL-NEXT: v_add_i32_e32 v3, vcc, 32, v16 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v0, vcc, 64, v2 +; GISEL-NEXT: v_min_u32_e32 v1, v15, v3 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[12:13] +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v14, v0 +; GISEL-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, vcc +; GISEL-NEXT: v_subb_u32_e64 v0, s[4:5], 0, 0, s[4:5] +; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, s[4:5] +; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[8:9] +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc +; GISEL-NEXT: v_xor_b32_e32 v8, 0x7f, v2 +; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc +; GISEL-NEXT: v_or_b32_e32 v8, v8, v0 +; GISEL-NEXT: v_or_b32_e32 v9, v3, v1 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e32 v14, v15, v14, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GISEL-NEXT: v_or_b32_e32 v9, v16, v14 +; GISEL-NEXT: v_and_b32_e32 v14, 1, v9 +; GISEL-NEXT: v_or_b32_e32 v8, v9, v8 +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 +; GISEL-NEXT: v_cndmask_b32_e64 v16, v10, 0, vcc +; GISEL-NEXT: v_and_b32_e32 v14, 1, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v17, v11, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v8, v12, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v9, v13, 0, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 +; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; GISEL-NEXT: s_cbranch_execz .LBB1_6 +; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 +; GISEL-NEXT: v_add_i32_e32 v19, vcc, 1, v2 +; GISEL-NEXT: v_addc_u32_e64 v20, s[4:5], 0, v3, vcc +; GISEL-NEXT: v_sub_i32_e32 v23, vcc, 0x7f, v2 +; GISEL-NEXT: v_not_b32_e32 v2, 63 +; GISEL-NEXT: v_addc_u32_e64 v21, vcc, 0, v0, s[4:5] +; GISEL-NEXT: v_addc_u32_e32 v22, vcc, 0, v1, vcc +; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v23, v2 +; GISEL-NEXT: v_sub_i32_e64 v8, s[4:5], 64, v23 +; GISEL-NEXT: v_lshl_b64 v[0:1], v[10:11], v23 +; GISEL-NEXT: v_lshl_b64 v[2:3], v[12:13], v23 +; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 +; GISEL-NEXT: v_lshr_b64 v[8:9], v[10:11], v8 +; GISEL-NEXT: v_lshl_b64 v[16:17], v[10:11], v14 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v23 +; GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v1, vcc +; GISEL-NEXT: v_or_b32_e32 v0, v8, v2 +; GISEL-NEXT: v_or_b32_e32 v1, v9, v3 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v23 +; GISEL-NEXT: v_cndmask_b32_e32 v8, v0, v12, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v9, v1, v13, vcc +; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] +; GISEL-NEXT: v_mov_b32_e32 v0, s8 +; GISEL-NEXT: v_mov_b32_e32 v1, s9 +; GISEL-NEXT: v_mov_b32_e32 v2, s10 +; GISEL-NEXT: v_mov_b32_e32 v3, s11 +; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] +; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] +; GISEL-NEXT: s_cbranch_execz .LBB1_5 +; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 +; GISEL-NEXT: v_add_i32_e32 v16, vcc, 0xffffffc0, v19 +; GISEL-NEXT: v_sub_i32_e32 v17, vcc, 64, v19 +; GISEL-NEXT: v_lshr_b64 v[0:1], v[12:13], v19 +; GISEL-NEXT: v_lshr_b64 v[2:3], v[10:11], v19 +; GISEL-NEXT: s_mov_b64 s[8:9], 0 +; GISEL-NEXT: v_lshl_b64 v[23:24], v[12:13], v17 +; GISEL-NEXT: v_lshr_b64 v[12:13], v[12:13], v16 +; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v19 +; GISEL-NEXT: v_cndmask_b32_e32 v16, 0, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v1, vcc +; GISEL-NEXT: v_or_b32_e32 v0, v2, v23 +; GISEL-NEXT: v_or_b32_e32 v1, v3, v24 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v1, v13, v1, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v19 +; GISEL-NEXT: v_cndmask_b32_e32 v12, v0, v10, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v13, v1, v11, vcc +; GISEL-NEXT: v_mov_b32_e32 v11, 0 +; GISEL-NEXT: v_mov_b32_e32 v0, s8 +; GISEL-NEXT: v_mov_b32_e32 v1, s9 +; GISEL-NEXT: v_mov_b32_e32 v2, s10 +; GISEL-NEXT: v_mov_b32_e32 v3, s11 +; GISEL-NEXT: .LBB1_3: ; %udiv-do-while3 +; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GISEL-NEXT: v_lshl_b64 v[2:3], v[14:15], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v10, 31, v15 +; GISEL-NEXT: v_lshl_b64 v[23:24], v[12:13], 1 +; GISEL-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v12, 31, v13 +; GISEL-NEXT: v_lshrrev_b32_e32 v13, 31, v9 +; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; GISEL-NEXT: v_add_i32_e32 v19, vcc, -1, v19 +; GISEL-NEXT: v_addc_u32_e32 v20, vcc, -1, v20, vcc +; GISEL-NEXT: v_or_b32_e32 v14, v0, v2 +; GISEL-NEXT: v_or_b32_e32 v15, v1, v3 +; GISEL-NEXT: v_or_b32_e32 v2, v16, v12 +; GISEL-NEXT: v_or_b32_e32 v0, v23, v13 +; GISEL-NEXT: v_or_b32_e32 v8, v8, v10 +; GISEL-NEXT: v_addc_u32_e32 v21, vcc, -1, v21, vcc +; GISEL-NEXT: v_addc_u32_e32 v22, vcc, -1, v22, vcc +; GISEL-NEXT: v_sub_i32_e32 v1, vcc, 1, v24 +; GISEL-NEXT: v_subb_u32_e32 v1, vcc, 0, v2, vcc +; GISEL-NEXT: v_subrev_i32_e64 v12, s[4:5], 0, v0 +; GISEL-NEXT: v_or_b32_e32 v0, v19, v21 +; GISEL-NEXT: v_or_b32_e32 v1, v20, v22 +; GISEL-NEXT: v_subb_u32_e32 v3, vcc, 0, v17, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_ashrrev_i32_e32 v0, 31, v3 +; GISEL-NEXT: v_and_b32_e32 v10, 1, v0 +; GISEL-NEXT: v_and_b32_e32 v3, 2, v0 +; GISEL-NEXT: v_mov_b32_e32 v0, v10 +; GISEL-NEXT: v_mov_b32_e32 v1, v11 +; GISEL-NEXT: v_sub_i32_e64 v13, s[4:5], v24, v3 +; GISEL-NEXT: v_subbrev_u32_e64 v16, s[4:5], 0, v2, s[4:5] +; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GISEL-NEXT: v_subbrev_u32_e64 v17, vcc, 0, v17, s[4:5] +; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] +; GISEL-NEXT: s_cbranch_execnz .LBB1_3 +; GISEL-NEXT: ; %bb.4: ; %Flow13 +; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] +; GISEL-NEXT: .LBB1_5: ; %Flow14 +; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] +; GISEL-NEXT: v_lshl_b64 v[2:3], v[14:15], 1 +; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v10, 31, v15 +; GISEL-NEXT: v_or_b32_e32 v8, v8, v10 +; GISEL-NEXT: v_or_b32_e32 v16, v0, v2 +; GISEL-NEXT: v_or_b32_e32 v17, v1, v3 +; GISEL-NEXT: .LBB1_6: ; %Flow16 +; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-NEXT: s_mov_b64 s[8:9], 0 +; GISEL-NEXT: v_ashrrev_i32_e32 v19, 31, v7 +; GISEL-NEXT: v_mov_b32_e32 v2, 0x5e +; GISEL-NEXT: v_mov_b32_e32 v12, 0x7f +; GISEL-NEXT: v_mov_b32_e32 v13, 0 +; GISEL-NEXT: v_xor_b32_e32 v0, v19, v4 +; GISEL-NEXT: v_xor_b32_e32 v1, v19, v5 +; GISEL-NEXT: v_xor_b32_e32 v3, v19, v6 +; GISEL-NEXT: v_xor_b32_e32 v6, v19, v7 +; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v19 +; GISEL-NEXT: v_subb_u32_e32 v5, vcc, v1, v19, vcc +; GISEL-NEXT: v_subb_u32_e32 v10, vcc, v3, v19, vcc +; GISEL-NEXT: v_subb_u32_e32 v11, vcc, v6, v19, vcc +; GISEL-NEXT: v_ffbh_u32_e32 v3, v5 +; GISEL-NEXT: v_ffbh_u32_e32 v6, v4 +; GISEL-NEXT: v_or_b32_e32 v0, v4, v10 +; GISEL-NEXT: v_or_b32_e32 v1, v5, v11 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, 32, v6 +; GISEL-NEXT: v_ffbh_u32_e32 v7, v11 +; GISEL-NEXT: v_ffbh_u32_e32 v14, v10 +; GISEL-NEXT: v_min_u32_e32 v3, v3, v6 +; GISEL-NEXT: v_add_i32_e32 v6, vcc, 32, v14 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc +; GISEL-NEXT: v_add_i32_e32 v0, vcc, 64, v3 +; GISEL-NEXT: v_min_u32_e32 v1, v7, v6 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11] +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v0 +; GISEL-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, vcc +; GISEL-NEXT: v_subb_u32_e64 v0, s[4:5], 0, 0, s[4:5] +; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, s[4:5] +; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[12:13] +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc +; GISEL-NEXT: v_xor_b32_e32 v6, 0x7f, v2 +; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; GISEL-NEXT: v_or_b32_e32 v6, v6, v0 +; GISEL-NEXT: v_or_b32_e32 v7, v3, v1 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] +; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc +; GISEL-NEXT: v_or_b32_e32 v7, v14, v12 +; GISEL-NEXT: v_and_b32_e32 v12, 1, v7 +; GISEL-NEXT: v_or_b32_e32 v6, v7, v6 +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, v4, 0, vcc +; GISEL-NEXT: v_and_b32_e32 v14, 1, v6 +; GISEL-NEXT: v_cndmask_b32_e64 v13, v5, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v6, v10, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v7, v11, 0, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14 +; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; GISEL-NEXT: s_cbranch_execz .LBB1_12 +; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 +; GISEL-NEXT: v_add_i32_e32 v20, vcc, 1, v2 +; GISEL-NEXT: v_addc_u32_e64 v21, s[4:5], 0, v3, vcc +; GISEL-NEXT: v_sub_i32_e32 v24, vcc, 0x7f, v2 +; GISEL-NEXT: v_not_b32_e32 v2, 63 +; GISEL-NEXT: v_addc_u32_e64 v22, vcc, 0, v0, s[4:5] +; GISEL-NEXT: v_addc_u32_e32 v23, vcc, 0, v1, vcc +; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v24, v2 +; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], 64, v24 +; GISEL-NEXT: v_lshl_b64 v[0:1], v[4:5], v24 +; GISEL-NEXT: v_lshl_b64 v[2:3], v[10:11], v24 +; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 +; GISEL-NEXT: v_lshr_b64 v[6:7], v[4:5], v6 +; GISEL-NEXT: v_lshl_b64 v[14:15], v[4:5], v12 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v24 +; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v13, 0, v1, vcc +; GISEL-NEXT: v_or_b32_e32 v0, v6, v2 +; GISEL-NEXT: v_or_b32_e32 v1, v7, v3 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v14, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v1, v15, v1, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v24 +; GISEL-NEXT: v_cndmask_b32_e32 v6, v0, v10, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v7, v1, v11, vcc +; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] +; GISEL-NEXT: v_mov_b32_e32 v0, s8 +; GISEL-NEXT: v_mov_b32_e32 v1, s9 +; GISEL-NEXT: v_mov_b32_e32 v2, s10 +; GISEL-NEXT: v_mov_b32_e32 v3, s11 +; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] +; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] +; GISEL-NEXT: s_cbranch_execz .LBB1_11 +; GISEL-NEXT: ; %bb.8: ; %udiv-preheader +; GISEL-NEXT: v_add_i32_e32 v24, vcc, 0xffffffc0, v20 +; GISEL-NEXT: v_sub_i32_e32 v14, vcc, 64, v20 +; GISEL-NEXT: v_lshr_b64 v[0:1], v[10:11], v20 +; GISEL-NEXT: v_lshr_b64 v[2:3], v[4:5], v20 +; GISEL-NEXT: s_mov_b64 s[8:9], 0 +; GISEL-NEXT: v_lshl_b64 v[14:15], v[10:11], v14 +; GISEL-NEXT: v_lshr_b64 v[10:11], v[10:11], v24 +; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] +; GISEL-NEXT: v_or_b32_e32 v2, v2, v14 +; GISEL-NEXT: v_or_b32_e32 v3, v3, v15 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v20 +; GISEL-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v1, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v20 +; GISEL-NEXT: v_cndmask_b32_e32 v10, v2, v4, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v11, v3, v5, vcc +; GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GISEL-NEXT: v_mov_b32_e32 v0, s8 +; GISEL-NEXT: v_mov_b32_e32 v1, s9 +; GISEL-NEXT: v_mov_b32_e32 v2, s10 +; GISEL-NEXT: v_mov_b32_e32 v3, s11 +; GISEL-NEXT: .LBB1_9: ; %udiv-do-while +; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GISEL-NEXT: v_lshl_b64 v[24:25], v[10:11], 1 +; GISEL-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v5, 31, v11 +; GISEL-NEXT: v_lshrrev_b32_e32 v10, 31, v7 +; GISEL-NEXT: v_lshl_b64 v[2:3], v[12:13], 1 +; GISEL-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v11, 31, v13 +; GISEL-NEXT: v_add_i32_e32 v20, vcc, -1, v20 +; GISEL-NEXT: v_addc_u32_e32 v21, vcc, -1, v21, vcc +; GISEL-NEXT: v_or_b32_e32 v5, v14, v5 +; GISEL-NEXT: v_or_b32_e32 v10, v24, v10 +; GISEL-NEXT: v_or_b32_e32 v6, v6, v11 +; GISEL-NEXT: v_or_b32_e32 v12, v0, v2 +; GISEL-NEXT: v_or_b32_e32 v13, v1, v3 +; GISEL-NEXT: v_addc_u32_e32 v22, vcc, -1, v22, vcc +; GISEL-NEXT: v_addc_u32_e32 v23, vcc, -1, v23, vcc +; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 1, v25 +; GISEL-NEXT: v_subb_u32_e32 v0, vcc, 0, v5, vcc +; GISEL-NEXT: v_subrev_i32_e64 v10, s[4:5], 0, v10 +; GISEL-NEXT: v_or_b32_e32 v0, v20, v22 +; GISEL-NEXT: v_or_b32_e32 v1, v21, v23 +; GISEL-NEXT: v_subb_u32_e32 v2, vcc, 0, v15, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_ashrrev_i32_e32 v0, 31, v2 +; GISEL-NEXT: v_and_b32_e32 v3, 1, v0 +; GISEL-NEXT: v_and_b32_e32 v2, 2, v0 +; GISEL-NEXT: v_mov_b32_e32 v0, v3 +; GISEL-NEXT: v_mov_b32_e32 v1, v4 +; GISEL-NEXT: v_sub_i32_e64 v11, s[4:5], v25, v2 +; GISEL-NEXT: v_subbrev_u32_e64 v14, s[4:5], 0, v5, s[4:5] +; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GISEL-NEXT: v_subbrev_u32_e64 v15, vcc, 0, v15, s[4:5] +; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] +; GISEL-NEXT: s_cbranch_execnz .LBB1_9 +; GISEL-NEXT: ; %bb.10: ; %Flow +; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] +; GISEL-NEXT: .LBB1_11: ; %Flow11 +; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] +; GISEL-NEXT: v_lshl_b64 v[2:3], v[12:13], 1 +; GISEL-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v4, 31, v13 +; GISEL-NEXT: v_or_b32_e32 v6, v6, v4 +; GISEL-NEXT: v_or_b32_e32 v12, v0, v2 +; GISEL-NEXT: v_or_b32_e32 v13, v1, v3 +; GISEL-NEXT: .LBB1_12: ; %Flow12 +; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-NEXT: v_xor_b32_e32 v0, v16, v18 +; GISEL-NEXT: v_xor_b32_e32 v1, v17, v18 +; GISEL-NEXT: v_xor_b32_e32 v2, v8, v18 +; GISEL-NEXT: v_xor_b32_e32 v3, v9, v18 +; GISEL-NEXT: v_xor_b32_e32 v4, v12, v19 +; GISEL-NEXT: v_xor_b32_e32 v5, v13, v19 +; GISEL-NEXT: v_xor_b32_e32 v6, v6, v19 +; GISEL-NEXT: v_xor_b32_e32 v7, v7, v19 +; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v18 +; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v18, vcc +; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], v4, v19 +; GISEL-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v19, s[4:5] +; GISEL-NEXT: v_subb_u32_e32 v2, vcc, v2, v18, vcc +; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v18, vcc +; GISEL-NEXT: v_subb_u32_e64 v6, vcc, v6, v19, s[4:5] +; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v7, v19, vcc +; GISEL-NEXT: s_setpc_b64 s[30:31] + %shl = sdiv <2 x i128> %lhs, + ret <2 x i128> %shl +} + define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-LABEL: v_udiv_v2i128_vv: ; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases @@ -887,7 +1569,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: s_and_b64 s[8:9], s[6:7], vcc ; SDAG-NEXT: v_cndmask_b32_e64 v19, v0, 0, s[4:5] ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] -; SDAG-NEXT: s_cbranch_execz .LBB1_6 +; SDAG-NEXT: s_cbranch_execz .LBB2_6 ; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 ; SDAG-NEXT: v_add_i32_e32 v26, vcc, 1, v20 ; SDAG-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v20 @@ -917,7 +1599,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v21, 0 ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB1_5 +; SDAG-NEXT: s_cbranch_execz .LBB2_5 ; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 ; SDAG-NEXT: v_lshr_b64 v[20:21], v[0:1], v26 ; SDAG-NEXT: v_sub_i32_e32 v22, vcc, 64, v26 @@ -945,7 +1627,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v21, 0 ; SDAG-NEXT: v_mov_b32_e32 v24, 0 ; SDAG-NEXT: v_mov_b32_e32 v25, 0 -; SDAG-NEXT: .LBB1_3: ; %udiv-do-while3 +; SDAG-NEXT: .LBB2_3: ; %udiv-do-while3 ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 ; SDAG-NEXT: v_lshrrev_b32_e32 v34, 31, v19 ; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1 @@ -986,10 +1668,10 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v25, v21 ; SDAG-NEXT: v_mov_b32_e32 v24, v20 ; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] -; SDAG-NEXT: s_cbranch_execnz .LBB1_3 +; SDAG-NEXT: s_cbranch_execnz .LBB2_3 ; SDAG-NEXT: ; %bb.4: ; %Flow13 ; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] -; SDAG-NEXT: .LBB1_5: ; %Flow14 +; SDAG-NEXT: .LBB2_5: ; %Flow14 ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] ; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v8, 31, v19 @@ -997,7 +1679,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_or_b32_e32 v2, v2, v8 ; SDAG-NEXT: v_or_b32_e32 v18, v21, v1 ; SDAG-NEXT: v_or_b32_e32 v19, v20, v0 -; SDAG-NEXT: .LBB1_6: ; %Flow16 +; SDAG-NEXT: .LBB2_6: ; %Flow16 ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] ; SDAG-NEXT: v_or_b32_e32 v1, v13, v15 ; SDAG-NEXT: v_or_b32_e32 v0, v12, v14 @@ -1058,7 +1740,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_cndmask_b32_e64 v11, v4, 0, s[4:5] ; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB1_12 +; SDAG-NEXT: s_cbranch_execz .LBB2_12 ; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 ; SDAG-NEXT: v_add_i32_e32 v22, vcc, 1, v0 ; SDAG-NEXT: v_sub_i32_e64 v8, s[4:5], 63, v0 @@ -1088,7 +1770,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v17, 0 ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB1_11 +; SDAG-NEXT: s_cbranch_execz .LBB2_11 ; SDAG-NEXT: ; %bb.8: ; %udiv-preheader ; SDAG-NEXT: v_lshr_b64 v[20:21], v[4:5], v22 ; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 64, v22 @@ -1116,7 +1798,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc ; SDAG-NEXT: v_mov_b32_e32 v4, 0 ; SDAG-NEXT: v_mov_b32_e32 v5, 0 -; SDAG-NEXT: .LBB1_9: ; %udiv-do-while +; SDAG-NEXT: .LBB2_9: ; %udiv-do-while ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 ; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v16, 31, v7 @@ -1157,10 +1839,10 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v4, v16 ; SDAG-NEXT: v_mov_b32_e32 v5, v17 ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] -; SDAG-NEXT: s_cbranch_execnz .LBB1_9 +; SDAG-NEXT: s_cbranch_execnz .LBB2_9 ; SDAG-NEXT: ; %bb.10: ; %Flow ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] -; SDAG-NEXT: .LBB1_11: ; %Flow11 +; SDAG-NEXT: .LBB2_11: ; %Flow11 ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] ; SDAG-NEXT: v_lshl_b64 v[8:9], v[0:1], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v11 @@ -1168,7 +1850,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_or_b32_e32 v8, v8, v4 ; SDAG-NEXT: v_or_b32_e32 v10, v17, v1 ; SDAG-NEXT: v_or_b32_e32 v11, v16, v0 -; SDAG-NEXT: .LBB1_12: ; %Flow12 +; SDAG-NEXT: .LBB2_12: ; %Flow12 ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] ; SDAG-NEXT: v_mov_b32_e32 v0, v19 ; SDAG-NEXT: v_mov_b32_e32 v1, v18 @@ -1243,7 +1925,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GISEL-NEXT: v_cndmask_b32_e64 v19, v1, 0, vcc ; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[4:5] -; GISEL-NEXT: s_cbranch_execz .LBB1_6 +; GISEL-NEXT: s_cbranch_execz .LBB2_6 ; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 ; GISEL-NEXT: v_add_i32_e32 v26, vcc, 1, v22 ; GISEL-NEXT: v_addc_u32_e64 v27, s[4:5], 0, v23, vcc @@ -1275,7 +1957,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v18, s8 ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GISEL-NEXT: s_xor_b64 s[8:9], exec, s[6:7] -; GISEL-NEXT: s_cbranch_execz .LBB1_5 +; GISEL-NEXT: s_cbranch_execz .LBB2_5 ; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 ; GISEL-NEXT: v_add_i32_e32 v32, vcc, 0xffffffc0, v26 ; GISEL-NEXT: v_sub_i32_e32 v24, vcc, 64, v26 @@ -1304,7 +1986,7 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v20, s6 ; GISEL-NEXT: v_mov_b32_e32 v19, s5 ; GISEL-NEXT: v_mov_b32_e32 v18, s4 -; GISEL-NEXT: .LBB1_3: ; %udiv-do-while3 +; GISEL-NEXT: .LBB2_3: ; %udiv-do-while3 ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_lshrrev_b32_e32 v34, 31, v23 ; GISEL-NEXT: v_lshl_b64 v[20:21], v[22:23], 1 @@ -1343,200 +2025,826 @@ define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v19, v1 ; GISEL-NEXT: v_mov_b32_e32 v18, v0 ; GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5] -; GISEL-NEXT: s_cbranch_execnz .LBB1_3 +; GISEL-NEXT: s_cbranch_execnz .LBB2_3 +; GISEL-NEXT: ; %bb.4: ; %Flow13 +; GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GISEL-NEXT: .LBB2_5: ; %Flow14 +; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] +; GISEL-NEXT: v_lshl_b64 v[0:1], v[22:23], 1 +; GISEL-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v8, 31, v23 +; GISEL-NEXT: v_or_b32_e32 v2, v2, v8 +; GISEL-NEXT: v_or_b32_e32 v18, v18, v0 +; GISEL-NEXT: v_or_b32_e32 v19, v19, v1 +; GISEL-NEXT: .LBB2_6: ; %Flow16 +; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] +; GISEL-NEXT: s_mov_b64 s[8:9], 0 +; GISEL-NEXT: v_or_b32_e32 v0, v12, v14 +; GISEL-NEXT: v_or_b32_e32 v1, v13, v15 +; GISEL-NEXT: v_or_b32_e32 v8, v4, v6 +; GISEL-NEXT: v_or_b32_e32 v9, v5, v7 +; GISEL-NEXT: v_ffbh_u32_e32 v16, v13 +; GISEL-NEXT: v_ffbh_u32_e32 v17, v12 +; GISEL-NEXT: v_ffbh_u32_e32 v20, v15 +; GISEL-NEXT: v_ffbh_u32_e32 v21, v14 +; GISEL-NEXT: v_ffbh_u32_e32 v22, v5 +; GISEL-NEXT: v_ffbh_u32_e32 v23, v4 +; GISEL-NEXT: v_ffbh_u32_e32 v24, v7 +; GISEL-NEXT: v_ffbh_u32_e32 v25, v6 +; GISEL-NEXT: v_mov_b32_e32 v10, 0x7f +; GISEL-NEXT: v_mov_b32_e32 v11, 0 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[8:9] +; GISEL-NEXT: v_add_i32_e64 v0, s[6:7], 32, v17 +; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 32, v21 +; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], 32, v23 +; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], 32, v25 +; GISEL-NEXT: v_min_u32_e32 v0, v16, v0 +; GISEL-NEXT: v_min_u32_e32 v1, v20, v1 +; GISEL-NEXT: v_min_u32_e32 v8, v22, v8 +; GISEL-NEXT: v_min_u32_e32 v9, v24, v9 +; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, s[4:5] +; GISEL-NEXT: v_add_i32_e32 v0, vcc, 64, v0 +; GISEL-NEXT: v_add_i32_e32 v8, vcc, 64, v8 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] +; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc +; GISEL-NEXT: v_sub_i32_e32 v16, vcc, v0, v1 +; GISEL-NEXT: v_subb_u32_e64 v17, s[4:5], 0, 0, vcc +; GISEL-NEXT: v_subb_u32_e64 v0, s[4:5], 0, 0, s[4:5] +; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, s[4:5] +; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[16:17], v[10:11] +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; GISEL-NEXT: v_xor_b32_e32 v8, 0x7f, v16 +; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; GISEL-NEXT: v_or_b32_e32 v8, v8, v0 +; GISEL-NEXT: v_or_b32_e32 v9, v17, v1 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] +; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc +; GISEL-NEXT: v_or_b32_e32 v9, v20, v10 +; GISEL-NEXT: v_and_b32_e32 v10, 1, v9 +; GISEL-NEXT: v_or_b32_e32 v8, v9, v8 +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v10, v4, 0, vcc +; GISEL-NEXT: v_and_b32_e32 v20, 1, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v11, v5, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v8, v6, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v9, v7, 0, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20 +; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 +; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[4:5] +; GISEL-NEXT: s_cbranch_execz .LBB2_12 +; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 +; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v16 +; GISEL-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v17, vcc +; GISEL-NEXT: v_sub_i32_e32 v26, vcc, 0x7f, v16 +; GISEL-NEXT: v_not_b32_e32 v9, 63 +; GISEL-NEXT: v_addc_u32_e64 v24, vcc, 0, v0, s[4:5] +; GISEL-NEXT: v_addc_u32_e32 v25, vcc, 0, v1, vcc +; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v26, v9 +; GISEL-NEXT: v_sub_i32_e64 v10, s[4:5], 64, v26 +; GISEL-NEXT: v_lshl_b64 v[0:1], v[4:5], v26 +; GISEL-NEXT: v_lshl_b64 v[16:17], v[6:7], v26 +; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 +; GISEL-NEXT: v_lshr_b64 v[20:21], v[4:5], v10 +; GISEL-NEXT: v_lshl_b64 v[22:23], v[4:5], v9 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v26 +; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v1, vcc +; GISEL-NEXT: v_or_b32_e32 v0, v20, v16 +; GISEL-NEXT: v_or_b32_e32 v1, v21, v17 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v22, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v1, v23, v1, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v26 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc +; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] +; GISEL-NEXT: v_mov_b32_e32 v23, s11 +; GISEL-NEXT: v_mov_b32_e32 v22, s10 +; GISEL-NEXT: v_mov_b32_e32 v21, s9 +; GISEL-NEXT: v_mov_b32_e32 v20, s8 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; GISEL-NEXT: s_xor_b64 s[8:9], exec, s[6:7] +; GISEL-NEXT: s_cbranch_execz .LBB2_11 +; GISEL-NEXT: ; %bb.8: ; %udiv-preheader +; GISEL-NEXT: v_add_i32_e32 v28, vcc, 0xffffffc0, v8 +; GISEL-NEXT: v_sub_i32_e32 v22, vcc, 64, v8 +; GISEL-NEXT: v_lshr_b64 v[16:17], v[6:7], v8 +; GISEL-NEXT: v_lshr_b64 v[20:21], v[4:5], v8 +; GISEL-NEXT: s_mov_b64 s[4:5], 0 +; GISEL-NEXT: v_add_i32_e32 v26, vcc, -1, v12 +; GISEL-NEXT: v_addc_u32_e32 v27, vcc, -1, v13, vcc +; GISEL-NEXT: v_lshl_b64 v[22:23], v[6:7], v22 +; GISEL-NEXT: v_lshr_b64 v[6:7], v[6:7], v28 +; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v14, vcc +; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v15, vcc +; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5] +; GISEL-NEXT: v_or_b32_e32 v20, v20, v22 +; GISEL-NEXT: v_or_b32_e32 v21, v21, v23 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8 +; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v20, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v21, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8 +; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v5, vcc +; GISEL-NEXT: v_mov_b32_e32 v5, 0 +; GISEL-NEXT: v_mov_b32_e32 v23, s7 +; GISEL-NEXT: v_mov_b32_e32 v22, s6 +; GISEL-NEXT: v_mov_b32_e32 v21, s5 +; GISEL-NEXT: v_mov_b32_e32 v20, s4 +; GISEL-NEXT: .LBB2_9: ; %udiv-do-while +; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GISEL-NEXT: v_lshl_b64 v[22:23], v[6:7], 1 +; GISEL-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v4, 31, v7 +; GISEL-NEXT: v_lshrrev_b32_e32 v30, 31, v1 +; GISEL-NEXT: v_lshl_b64 v[6:7], v[9:10], 1 +; GISEL-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v9, 31, v10 +; GISEL-NEXT: v_add_i32_e32 v8, vcc, -1, v8 +; GISEL-NEXT: v_addc_u32_e32 v11, vcc, -1, v11, vcc +; GISEL-NEXT: v_or_b32_e32 v16, v16, v4 +; GISEL-NEXT: v_or_b32_e32 v22, v22, v30 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v9 +; GISEL-NEXT: v_or_b32_e32 v9, v20, v6 +; GISEL-NEXT: v_or_b32_e32 v10, v21, v7 +; GISEL-NEXT: v_addc_u32_e32 v24, vcc, -1, v24, vcc +; GISEL-NEXT: v_addc_u32_e32 v25, vcc, -1, v25, vcc +; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v26, v22 +; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v27, v23, vcc +; GISEL-NEXT: v_or_b32_e32 v6, v8, v24 +; GISEL-NEXT: v_or_b32_e32 v7, v11, v25 +; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v28, v16, vcc +; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v29, v17, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] +; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v4 +; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GISEL-NEXT: v_and_b32_e32 v4, 1, v6 +; GISEL-NEXT: v_and_b32_e32 v7, v6, v12 +; GISEL-NEXT: v_and_b32_e32 v30, v6, v13 +; GISEL-NEXT: v_and_b32_e32 v31, v6, v14 +; GISEL-NEXT: v_and_b32_e32 v32, v6, v15 +; GISEL-NEXT: v_mov_b32_e32 v21, v5 +; GISEL-NEXT: v_mov_b32_e32 v20, v4 +; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v22, v7 +; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v23, v30, vcc +; GISEL-NEXT: v_subb_u32_e32 v16, vcc, v16, v31, vcc +; GISEL-NEXT: v_subb_u32_e32 v17, vcc, v17, v32, vcc +; GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GISEL-NEXT: s_cbranch_execnz .LBB2_9 +; GISEL-NEXT: ; %bb.10: ; %Flow +; GISEL-NEXT: s_or_b64 exec, exec, s[4:5] +; GISEL-NEXT: .LBB2_11: ; %Flow11 +; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] +; GISEL-NEXT: v_lshl_b64 v[4:5], v[9:10], 1 +; GISEL-NEXT: v_lshl_b64 v[8:9], v[0:1], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v10 +; GISEL-NEXT: v_or_b32_e32 v8, v8, v0 +; GISEL-NEXT: v_or_b32_e32 v10, v20, v4 +; GISEL-NEXT: v_or_b32_e32 v11, v21, v5 +; GISEL-NEXT: .LBB2_12: ; %Flow12 +; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] +; GISEL-NEXT: v_mov_b32_e32 v0, v18 +; GISEL-NEXT: v_mov_b32_e32 v1, v19 +; GISEL-NEXT: v_mov_b32_e32 v4, v10 +; GISEL-NEXT: v_mov_b32_e32 v5, v11 +; GISEL-NEXT: v_mov_b32_e32 v6, v8 +; GISEL-NEXT: v_mov_b32_e32 v7, v9 +; GISEL-NEXT: s_setpc_b64 s[30:31] + %shl = udiv <2 x i128> %lhs, %rhs + ret <2 x i128> %shl +} + +define <2 x i128> @v_udiv_v2i128_v_pow2k(<2 x i128> %lhs) { +; SDAG-LABEL: v_udiv_v2i128_v_pow2k: +; SDAG: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases +; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v9, v3 +; SDAG-NEXT: v_mov_b32_e32 v8, v2 +; SDAG-NEXT: v_or_b32_e32 v3, v1, v9 +; SDAG-NEXT: v_or_b32_e32 v2, v0, v8 +; SDAG-NEXT: v_ffbh_u32_e32 v10, v8 +; SDAG-NEXT: v_ffbh_u32_e32 v11, v9 +; SDAG-NEXT: v_ffbh_u32_e32 v12, v0 +; SDAG-NEXT: v_ffbh_u32_e32 v13, v1 +; SDAG-NEXT: v_mov_b32_e32 v15, 0 +; SDAG-NEXT: s_mov_b64 s[6:7], 0x7f +; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[2:3] +; SDAG-NEXT: v_add_i32_e32 v2, vcc, 32, v10 +; SDAG-NEXT: v_add_i32_e32 v3, vcc, 32, v12 +; SDAG-NEXT: v_min_u32_e32 v2, v2, v11 +; SDAG-NEXT: v_min_u32_e32 v3, v3, v13 +; SDAG-NEXT: v_add_i32_e32 v3, vcc, 64, v3 +; SDAG-NEXT: v_addc_u32_e64 v10, s[8:9], 0, 0, vcc +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; SDAG-NEXT: v_cndmask_b32_e64 v10, v10, 0, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; SDAG-NEXT: v_sub_i32_e32 v12, vcc, 0x5e, v2 +; SDAG-NEXT: v_subb_u32_e32 v13, vcc, 0, v10, vcc +; SDAG-NEXT: v_xor_b32_e32 v2, 0x7f, v12 +; SDAG-NEXT: v_subb_u32_e32 v14, vcc, 0, v15, vcc +; SDAG-NEXT: v_cmp_lt_u64_e64 s[6:7], s[6:7], v[12:13] +; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[6:7] +; SDAG-NEXT: v_subb_u32_e32 v15, vcc, 0, v15, vcc +; SDAG-NEXT: v_or_b32_e32 v2, v2, v14 +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] +; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; SDAG-NEXT: v_or_b32_e32 v3, v13, v15 +; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] +; SDAG-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; SDAG-NEXT: v_and_b32_e32 v2, 1, v10 +; SDAG-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v2 +; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v3, v9, 0, s[4:5] +; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; SDAG-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v10, v1, 0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v11, v0, 0, s[4:5] +; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc +; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; SDAG-NEXT: s_cbranch_execz .LBB3_6 +; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 +; SDAG-NEXT: v_add_i32_e32 v18, vcc, 1, v12 +; SDAG-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v12 +; SDAG-NEXT: v_addc_u32_e32 v19, vcc, 0, v13, vcc +; SDAG-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 +; SDAG-NEXT: v_addc_u32_e32 v20, vcc, 0, v14, vcc +; SDAG-NEXT: v_addc_u32_e32 v21, vcc, 0, v15, vcc +; SDAG-NEXT: v_or_b32_e32 v10, v18, v20 +; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 0x7f, v12 +; SDAG-NEXT: v_or_b32_e32 v11, v19, v21 +; SDAG-NEXT: v_lshl_b64 v[12:13], v[8:9], v16 +; SDAG-NEXT: v_sub_i32_e32 v17, vcc, 64, v16 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[0:1], v16 +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; SDAG-NEXT: v_lshr_b64 v[10:11], v[0:1], v17 +; SDAG-NEXT: v_or_b32_e32 v11, v13, v11 +; SDAG-NEXT: v_or_b32_e32 v10, v12, v10 +; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v16 +; SDAG-NEXT: v_cndmask_b32_e64 v3, v3, v11, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v2, v2, v10, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v15, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, v14, s[4:5] +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16 +; SDAG-NEXT: v_cndmask_b32_e64 v3, v3, v9, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v2, v2, v8, s[4:5] +; SDAG-NEXT: v_mov_b32_e32 v12, 0 +; SDAG-NEXT: v_mov_b32_e32 v13, 0 +; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc +; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] +; SDAG-NEXT: s_cbranch_execz .LBB3_5 +; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 +; SDAG-NEXT: v_lshr_b64 v[12:13], v[0:1], v18 +; SDAG-NEXT: v_sub_i32_e32 v14, vcc, 64, v18 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[8:9], v14 +; SDAG-NEXT: v_or_b32_e32 v15, v13, v15 +; SDAG-NEXT: v_or_b32_e32 v14, v12, v14 +; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v18 +; SDAG-NEXT: v_subrev_i32_e64 v12, s[4:5], 64, v18 +; SDAG-NEXT: v_lshr_b64 v[12:13], v[8:9], v12 +; SDAG-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18 +; SDAG-NEXT: v_cndmask_b32_e64 v15, v13, v1, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e32 v1, v12, v14, vcc +; SDAG-NEXT: v_cndmask_b32_e64 v14, v1, v0, s[4:5] +; SDAG-NEXT: v_lshr_b64 v[0:1], v[8:9], v18 +; SDAG-NEXT: v_cndmask_b32_e32 v17, 0, v1, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v16, 0, v0, vcc +; SDAG-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-NEXT: v_mov_b32_e32 v1, 0 +; SDAG-NEXT: s_mov_b64 s[4:5], 0 +; SDAG-NEXT: v_mov_b32_e32 v13, 0 +; SDAG-NEXT: v_mov_b32_e32 v8, 0 +; SDAG-NEXT: v_mov_b32_e32 v9, 0 +; SDAG-NEXT: .LBB3_3: ; %udiv-do-while3 +; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v12, 31, v15 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v3 +; SDAG-NEXT: v_or_b32_e32 v16, v16, v12 +; SDAG-NEXT: v_or_b32_e32 v12, v14, v22 +; SDAG-NEXT: v_sub_i32_e32 v14, vcc, -1, v12 +; SDAG-NEXT: v_subb_u32_e32 v14, vcc, 1, v15, vcc +; SDAG-NEXT: v_subb_u32_e32 v14, vcc, 0, v16, vcc +; SDAG-NEXT: v_subb_u32_e32 v14, vcc, 0, v17, vcc +; SDAG-NEXT: v_ashrrev_i32_e32 v22, 31, v14 +; SDAG-NEXT: v_subrev_i32_e32 v14, vcc, 0, v12 +; SDAG-NEXT: v_and_b32_e32 v12, 2, v22 +; SDAG-NEXT: v_subb_u32_e32 v15, vcc, v15, v12, vcc +; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v12, 31, v11 +; SDAG-NEXT: v_or_b32_e32 v2, v2, v12 +; SDAG-NEXT: v_or_b32_e32 v3, v1, v3 +; SDAG-NEXT: v_or_b32_e32 v2, v0, v2 +; SDAG-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 +; SDAG-NEXT: v_and_b32_e32 v12, 1, v22 +; SDAG-NEXT: v_subbrev_u32_e32 v16, vcc, 0, v16, vcc +; SDAG-NEXT: v_subbrev_u32_e32 v17, vcc, 0, v17, vcc +; SDAG-NEXT: v_add_i32_e32 v18, vcc, -1, v18 +; SDAG-NEXT: v_addc_u32_e32 v19, vcc, -1, v19, vcc +; SDAG-NEXT: v_addc_u32_e32 v20, vcc, -1, v20, vcc +; SDAG-NEXT: v_addc_u32_e32 v21, vcc, -1, v21, vcc +; SDAG-NEXT: v_or_b32_e32 v22, v18, v20 +; SDAG-NEXT: v_or_b32_e32 v23, v19, v21 +; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23] +; SDAG-NEXT: v_or_b32_e32 v11, v9, v11 +; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; SDAG-NEXT: v_or_b32_e32 v10, v8, v10 +; SDAG-NEXT: v_mov_b32_e32 v8, v12 +; SDAG-NEXT: v_mov_b32_e32 v9, v13 +; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] +; SDAG-NEXT: s_cbranch_execnz .LBB3_3 +; SDAG-NEXT: ; %bb.4: ; %Flow13 +; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] +; SDAG-NEXT: .LBB3_5: ; %Flow14 +; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] +; SDAG-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v8, 31, v11 +; SDAG-NEXT: v_lshl_b64 v[0:1], v[10:11], 1 +; SDAG-NEXT: v_or_b32_e32 v2, v2, v8 +; SDAG-NEXT: v_or_b32_e32 v10, v13, v1 +; SDAG-NEXT: v_or_b32_e32 v11, v12, v0 +; SDAG-NEXT: .LBB3_6: ; %Flow16 +; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] +; SDAG-NEXT: v_or_b32_e32 v1, v5, v7 +; SDAG-NEXT: v_or_b32_e32 v0, v4, v6 +; SDAG-NEXT: v_ffbh_u32_e32 v8, v6 +; SDAG-NEXT: v_ffbh_u32_e32 v9, v7 +; SDAG-NEXT: v_ffbh_u32_e32 v12, v4 +; SDAG-NEXT: v_ffbh_u32_e32 v13, v5 +; SDAG-NEXT: v_mov_b32_e32 v15, 0 +; SDAG-NEXT: s_mov_b64 s[6:7], 0x7f +; SDAG-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] +; SDAG-NEXT: v_add_i32_e32 v0, vcc, 32, v8 +; SDAG-NEXT: v_add_i32_e32 v1, vcc, 32, v12 +; SDAG-NEXT: v_min_u32_e32 v0, v0, v9 +; SDAG-NEXT: v_min_u32_e32 v1, v1, v13 +; SDAG-NEXT: v_add_i32_e32 v1, vcc, 64, v1 +; SDAG-NEXT: v_addc_u32_e64 v8, s[8:9], 0, 0, vcc +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v8, v8, 0, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; SDAG-NEXT: v_sub_i32_e32 v0, vcc, 0x5e, v0 +; SDAG-NEXT: v_subb_u32_e32 v1, vcc, 0, v8, vcc +; SDAG-NEXT: v_xor_b32_e32 v8, 0x7f, v0 +; SDAG-NEXT: v_subb_u32_e32 v14, vcc, 0, v15, vcc +; SDAG-NEXT: v_cmp_lt_u64_e64 s[6:7], s[6:7], v[0:1] +; SDAG-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7] +; SDAG-NEXT: v_subb_u32_e32 v15, vcc, 0, v15, vcc +; SDAG-NEXT: v_or_b32_e32 v8, v8, v14 +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15] +; SDAG-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc +; SDAG-NEXT: v_or_b32_e32 v9, v1, v15 +; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] +; SDAG-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; SDAG-NEXT: v_and_b32_e32 v8, 1, v12 +; SDAG-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v8 +; SDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v9, v7, 0, s[4:5] +; SDAG-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; SDAG-NEXT: v_cndmask_b32_e64 v8, v6, 0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v12, v5, 0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v13, v4, 0, s[4:5] +; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc +; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; SDAG-NEXT: s_cbranch_execz .LBB3_12 +; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 +; SDAG-NEXT: v_add_i32_e32 v18, vcc, 1, v0 +; SDAG-NEXT: v_sub_i32_e64 v8, s[4:5], 63, v0 +; SDAG-NEXT: v_addc_u32_e32 v19, vcc, 0, v1, vcc +; SDAG-NEXT: v_lshl_b64 v[8:9], v[4:5], v8 +; SDAG-NEXT: v_addc_u32_e32 v20, vcc, 0, v14, vcc +; SDAG-NEXT: v_addc_u32_e32 v21, vcc, 0, v15, vcc +; SDAG-NEXT: v_or_b32_e32 v12, v18, v20 +; SDAG-NEXT: v_sub_i32_e32 v16, vcc, 0x7f, v0 +; SDAG-NEXT: v_or_b32_e32 v13, v19, v21 +; SDAG-NEXT: v_lshl_b64 v[0:1], v[6:7], v16 +; SDAG-NEXT: v_sub_i32_e32 v17, vcc, 64, v16 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[4:5], v16 +; SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; SDAG-NEXT: v_lshr_b64 v[12:13], v[4:5], v17 +; SDAG-NEXT: v_or_b32_e32 v1, v1, v13 +; SDAG-NEXT: v_or_b32_e32 v0, v0, v12 +; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v16 +; SDAG-NEXT: v_cndmask_b32_e64 v1, v9, v1, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v0, v8, v0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v13, 0, v15, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v12, 0, v14, s[4:5] +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v16 +; SDAG-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5] +; SDAG-NEXT: v_mov_b32_e32 v14, 0 +; SDAG-NEXT: v_mov_b32_e32 v15, 0 +; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc +; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] +; SDAG-NEXT: s_cbranch_execz .LBB3_11 +; SDAG-NEXT: ; %bb.8: ; %udiv-preheader +; SDAG-NEXT: v_lshr_b64 v[8:9], v[4:5], v18 +; SDAG-NEXT: v_sub_i32_e32 v14, vcc, 64, v18 +; SDAG-NEXT: v_lshl_b64 v[14:15], v[6:7], v14 +; SDAG-NEXT: v_or_b32_e32 v15, v9, v15 +; SDAG-NEXT: v_or_b32_e32 v14, v8, v14 +; SDAG-NEXT: v_cmp_gt_u32_e32 vcc, 64, v18 +; SDAG-NEXT: v_subrev_i32_e64 v8, s[4:5], 64, v18 +; SDAG-NEXT: v_lshr_b64 v[8:9], v[6:7], v8 +; SDAG-NEXT: v_cndmask_b32_e32 v9, v9, v15, vcc +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18 +; SDAG-NEXT: v_cndmask_b32_e64 v9, v9, v5, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e32 v5, v8, v14, vcc +; SDAG-NEXT: v_cndmask_b32_e64 v8, v5, v4, s[4:5] +; SDAG-NEXT: v_lshr_b64 v[4:5], v[6:7], v18 +; SDAG-NEXT: v_cndmask_b32_e32 v17, 0, v5, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v16, 0, v4, vcc +; SDAG-NEXT: v_mov_b32_e32 v4, 0 +; SDAG-NEXT: v_mov_b32_e32 v5, 0 +; SDAG-NEXT: s_mov_b64 s[4:5], 0 +; SDAG-NEXT: v_mov_b32_e32 v15, 0 +; SDAG-NEXT: v_mov_b32_e32 v6, 0 +; SDAG-NEXT: v_mov_b32_e32 v7, 0 +; SDAG-NEXT: .LBB3_9: ; %udiv-do-while +; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v14, 31, v9 +; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v1 +; SDAG-NEXT: v_or_b32_e32 v16, v16, v14 +; SDAG-NEXT: v_or_b32_e32 v8, v8, v22 +; SDAG-NEXT: v_sub_i32_e32 v14, vcc, -1, v8 +; SDAG-NEXT: v_subb_u32_e32 v14, vcc, 1, v9, vcc +; SDAG-NEXT: v_subb_u32_e32 v14, vcc, 0, v16, vcc +; SDAG-NEXT: v_subb_u32_e32 v14, vcc, 0, v17, vcc +; SDAG-NEXT: v_ashrrev_i32_e32 v14, 31, v14 +; SDAG-NEXT: v_subrev_i32_e32 v8, vcc, 0, v8 +; SDAG-NEXT: v_and_b32_e32 v22, 2, v14 +; SDAG-NEXT: v_subb_u32_e32 v9, vcc, v9, v22, vcc +; SDAG-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v13 +; SDAG-NEXT: v_or_b32_e32 v0, v0, v22 +; SDAG-NEXT: v_or_b32_e32 v1, v5, v1 +; SDAG-NEXT: v_or_b32_e32 v0, v4, v0 +; SDAG-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 +; SDAG-NEXT: v_and_b32_e32 v14, 1, v14 +; SDAG-NEXT: v_subbrev_u32_e32 v16, vcc, 0, v16, vcc +; SDAG-NEXT: v_subbrev_u32_e32 v17, vcc, 0, v17, vcc +; SDAG-NEXT: v_add_i32_e32 v18, vcc, -1, v18 +; SDAG-NEXT: v_addc_u32_e32 v19, vcc, -1, v19, vcc +; SDAG-NEXT: v_addc_u32_e32 v20, vcc, -1, v20, vcc +; SDAG-NEXT: v_addc_u32_e32 v21, vcc, -1, v21, vcc +; SDAG-NEXT: v_or_b32_e32 v22, v18, v20 +; SDAG-NEXT: v_or_b32_e32 v23, v19, v21 +; SDAG-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[22:23] +; SDAG-NEXT: v_or_b32_e32 v13, v7, v13 +; SDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; SDAG-NEXT: v_or_b32_e32 v12, v6, v12 +; SDAG-NEXT: v_mov_b32_e32 v6, v14 +; SDAG-NEXT: v_mov_b32_e32 v7, v15 +; SDAG-NEXT: s_andn2_b64 exec, exec, s[4:5] +; SDAG-NEXT: s_cbranch_execnz .LBB3_9 +; SDAG-NEXT: ; %bb.10: ; %Flow +; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] +; SDAG-NEXT: .LBB3_11: ; %Flow11 +; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] +; SDAG-NEXT: v_lshl_b64 v[8:9], v[0:1], 1 +; SDAG-NEXT: v_lshrrev_b32_e32 v4, 31, v13 +; SDAG-NEXT: v_lshl_b64 v[0:1], v[12:13], 1 +; SDAG-NEXT: v_or_b32_e32 v8, v8, v4 +; SDAG-NEXT: v_or_b32_e32 v12, v15, v1 +; SDAG-NEXT: v_or_b32_e32 v13, v14, v0 +; SDAG-NEXT: .LBB3_12: ; %Flow12 +; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] +; SDAG-NEXT: v_mov_b32_e32 v0, v11 +; SDAG-NEXT: v_mov_b32_e32 v1, v10 +; SDAG-NEXT: v_mov_b32_e32 v4, v13 +; SDAG-NEXT: v_mov_b32_e32 v5, v12 +; SDAG-NEXT: v_mov_b32_e32 v6, v8 +; SDAG-NEXT: v_mov_b32_e32 v7, v9 +; SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-LABEL: v_udiv_v2i128_v_pow2k: +; GISEL: ; %bb.0: ; %_udiv-special-cases_udiv-special-cases +; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-NEXT: v_mov_b32_e32 v8, v2 +; GISEL-NEXT: v_mov_b32_e32 v9, v3 +; GISEL-NEXT: s_mov_b64 s[8:9], 0 +; GISEL-NEXT: v_or_b32_e32 v2, v0, v8 +; GISEL-NEXT: v_or_b32_e32 v3, v1, v9 +; GISEL-NEXT: v_ffbh_u32_e32 v12, v1 +; GISEL-NEXT: v_ffbh_u32_e32 v13, v0 +; GISEL-NEXT: v_ffbh_u32_e32 v14, v9 +; GISEL-NEXT: v_ffbh_u32_e32 v15, v8 +; GISEL-NEXT: v_mov_b32_e32 v16, 0x5e +; GISEL-NEXT: v_mov_b32_e32 v10, 0x7f +; GISEL-NEXT: v_mov_b32_e32 v11, 0 +; GISEL-NEXT: v_add_i32_e32 v13, vcc, 32, v13 +; GISEL-NEXT: v_add_i32_e32 v15, vcc, 32, v15 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] +; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc +; GISEL-NEXT: v_min_u32_e32 v2, v12, v13 +; GISEL-NEXT: v_min_u32_e32 v3, v14, v15 +; GISEL-NEXT: v_add_i32_e32 v2, vcc, 64, v2 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] +; GISEL-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; GISEL-NEXT: v_sub_i32_e32 v14, vcc, v16, v2 +; GISEL-NEXT: v_subb_u32_e64 v15, s[4:5], 0, 0, vcc +; GISEL-NEXT: v_subb_u32_e64 v12, s[4:5], 0, 0, s[4:5] +; GISEL-NEXT: v_subb_u32_e64 v13, s[4:5], 0, 0, s[4:5] +; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[14:15], v[10:11] +; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; GISEL-NEXT: v_xor_b32_e32 v2, 0x7f, v14 +; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] +; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; GISEL-NEXT: v_or_b32_e32 v2, v2, v12 +; GISEL-NEXT: v_or_b32_e32 v3, v15, v13 +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[12:13] +; GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] +; GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc +; GISEL-NEXT: v_or_b32_e32 v3, v17, v10 +; GISEL-NEXT: v_and_b32_e32 v10, 1, v3 +; GISEL-NEXT: v_or_b32_e32 v2, v3, v2 +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 +; GISEL-NEXT: v_cndmask_b32_e64 v10, v0, 0, vcc +; GISEL-NEXT: v_and_b32_e32 v16, 1, v2 +; GISEL-NEXT: v_cndmask_b32_e64 v11, v1, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v2, v8, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, 0, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 +; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; GISEL-NEXT: s_cbranch_execz .LBB3_6 +; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 +; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v14 +; GISEL-NEXT: v_addc_u32_e64 v19, s[4:5], 0, v15, vcc +; GISEL-NEXT: v_sub_i32_e32 v22, vcc, 0x7f, v14 +; GISEL-NEXT: v_not_b32_e32 v2, 63 +; GISEL-NEXT: v_addc_u32_e64 v20, vcc, 0, v12, s[4:5] +; GISEL-NEXT: v_addc_u32_e32 v21, vcc, 0, v13, vcc +; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v22, v2 +; GISEL-NEXT: v_sub_i32_e64 v12, s[4:5], 64, v22 +; GISEL-NEXT: v_lshl_b64 v[2:3], v[0:1], v22 +; GISEL-NEXT: v_lshl_b64 v[10:11], v[8:9], v22 +; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 +; GISEL-NEXT: v_lshr_b64 v[12:13], v[0:1], v12 +; GISEL-NEXT: v_lshl_b64 v[16:17], v[0:1], v14 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v22 +; GISEL-NEXT: v_cndmask_b32_e32 v14, 0, v2, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v15, 0, v3, vcc +; GISEL-NEXT: v_or_b32_e32 v2, v12, v10 +; GISEL-NEXT: v_or_b32_e32 v3, v13, v11 +; GISEL-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v22 +; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc +; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] +; GISEL-NEXT: v_mov_b32_e32 v13, s11 +; GISEL-NEXT: v_mov_b32_e32 v12, s10 +; GISEL-NEXT: v_mov_b32_e32 v11, s9 +; GISEL-NEXT: v_mov_b32_e32 v10, s8 +; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] +; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] +; GISEL-NEXT: s_cbranch_execz .LBB3_5 +; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 +; GISEL-NEXT: v_add_i32_e32 v22, vcc, 0xffffffc0, v18 +; GISEL-NEXT: v_sub_i32_e32 v16, vcc, 64, v18 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v18 +; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18 +; GISEL-NEXT: v_lshr_b64 v[10:11], v[8:9], v18 +; GISEL-NEXT: v_lshr_b64 v[12:13], v[0:1], v18 +; GISEL-NEXT: v_lshl_b64 v[16:17], v[8:9], v16 +; GISEL-NEXT: v_or_b32_e32 v12, v12, v16 +; GISEL-NEXT: v_or_b32_e32 v13, v13, v17 +; GISEL-NEXT: s_mov_b64 s[8:9], 0 +; GISEL-NEXT: v_lshr_b64 v[8:9], v[8:9], v22 +; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v13, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v8, v8, v0, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e64 v9, v9, v1, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e32 v16, 0, v10, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v11, vcc +; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] +; GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-NEXT: v_mov_b32_e32 v13, s11 +; GISEL-NEXT: v_mov_b32_e32 v12, s10 +; GISEL-NEXT: v_mov_b32_e32 v11, s9 +; GISEL-NEXT: v_mov_b32_e32 v10, s8 +; GISEL-NEXT: .LBB3_3: ; %udiv-do-while3 +; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GISEL-NEXT: v_lshl_b64 v[12:13], v[14:15], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v15 +; GISEL-NEXT: v_or_b32_e32 v14, v10, v12 +; GISEL-NEXT: v_or_b32_e32 v15, v11, v13 +; GISEL-NEXT: v_lshl_b64 v[10:11], v[8:9], 1 +; GISEL-NEXT: v_lshl_b64 v[12:13], v[16:17], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v8, 31, v9 +; GISEL-NEXT: v_lshrrev_b32_e32 v9, 31, v3 +; GISEL-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 +; GISEL-NEXT: v_add_i32_e32 v18, vcc, -1, v18 +; GISEL-NEXT: v_addc_u32_e32 v19, vcc, -1, v19, vcc +; GISEL-NEXT: v_or_b32_e32 v12, v12, v8 +; GISEL-NEXT: v_or_b32_e32 v8, v10, v9 +; GISEL-NEXT: v_or_b32_e32 v2, v2, v0 +; GISEL-NEXT: v_addc_u32_e32 v20, vcc, -1, v20, vcc +; GISEL-NEXT: v_addc_u32_e32 v21, vcc, -1, v21, vcc +; GISEL-NEXT: v_sub_i32_e32 v0, vcc, 1, v11 +; GISEL-NEXT: v_subb_u32_e32 v0, vcc, 0, v12, vcc +; GISEL-NEXT: v_subrev_i32_e64 v8, s[4:5], 0, v8 +; GISEL-NEXT: v_or_b32_e32 v9, v18, v20 +; GISEL-NEXT: v_or_b32_e32 v10, v19, v21 +; GISEL-NEXT: v_subb_u32_e32 v0, vcc, 0, v13, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[9:10] +; GISEL-NEXT: v_ashrrev_i32_e32 v9, 31, v0 +; GISEL-NEXT: v_and_b32_e32 v0, 1, v9 +; GISEL-NEXT: v_and_b32_e32 v9, 2, v9 +; GISEL-NEXT: v_sub_i32_e64 v9, s[4:5], v11, v9 +; GISEL-NEXT: v_mov_b32_e32 v11, v1 +; GISEL-NEXT: v_mov_b32_e32 v10, v0 +; GISEL-NEXT: v_subbrev_u32_e64 v16, s[4:5], 0, v12, s[4:5] +; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GISEL-NEXT: v_subbrev_u32_e64 v17, vcc, 0, v13, s[4:5] +; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] +; GISEL-NEXT: s_cbranch_execnz .LBB3_3 ; GISEL-NEXT: ; %bb.4: ; %Flow13 -; GISEL-NEXT: s_or_b64 exec, exec, s[4:5] -; GISEL-NEXT: .LBB1_5: ; %Flow14 ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] -; GISEL-NEXT: v_lshl_b64 v[0:1], v[22:23], 1 +; GISEL-NEXT: .LBB3_5: ; %Flow14 +; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] +; GISEL-NEXT: v_lshl_b64 v[0:1], v[14:15], 1 ; GISEL-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GISEL-NEXT: v_lshrrev_b32_e32 v8, 31, v23 +; GISEL-NEXT: v_lshrrev_b32_e32 v8, 31, v15 ; GISEL-NEXT: v_or_b32_e32 v2, v2, v8 -; GISEL-NEXT: v_or_b32_e32 v18, v18, v0 -; GISEL-NEXT: v_or_b32_e32 v19, v19, v1 -; GISEL-NEXT: .LBB1_6: ; %Flow16 -; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] +; GISEL-NEXT: v_or_b32_e32 v10, v10, v0 +; GISEL-NEXT: v_or_b32_e32 v11, v11, v1 +; GISEL-NEXT: .LBB3_6: ; %Flow16 +; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] ; GISEL-NEXT: s_mov_b64 s[8:9], 0 -; GISEL-NEXT: v_or_b32_e32 v0, v12, v14 -; GISEL-NEXT: v_or_b32_e32 v1, v13, v15 -; GISEL-NEXT: v_or_b32_e32 v8, v4, v6 -; GISEL-NEXT: v_or_b32_e32 v9, v5, v7 -; GISEL-NEXT: v_ffbh_u32_e32 v16, v13 -; GISEL-NEXT: v_ffbh_u32_e32 v17, v12 -; GISEL-NEXT: v_ffbh_u32_e32 v20, v15 -; GISEL-NEXT: v_ffbh_u32_e32 v21, v14 -; GISEL-NEXT: v_ffbh_u32_e32 v22, v5 -; GISEL-NEXT: v_ffbh_u32_e32 v23, v4 -; GISEL-NEXT: v_ffbh_u32_e32 v24, v7 -; GISEL-NEXT: v_ffbh_u32_e32 v25, v6 -; GISEL-NEXT: v_mov_b32_e32 v10, 0x7f -; GISEL-NEXT: v_mov_b32_e32 v11, 0 +; GISEL-NEXT: v_or_b32_e32 v0, v4, v6 +; GISEL-NEXT: v_or_b32_e32 v1, v5, v7 +; GISEL-NEXT: v_ffbh_u32_e32 v12, v5 +; GISEL-NEXT: v_ffbh_u32_e32 v13, v4 +; GISEL-NEXT: v_ffbh_u32_e32 v14, v7 +; GISEL-NEXT: v_ffbh_u32_e32 v15, v6 +; GISEL-NEXT: v_mov_b32_e32 v16, 0x5e +; GISEL-NEXT: v_mov_b32_e32 v8, 0x7f +; GISEL-NEXT: v_mov_b32_e32 v9, 0 +; GISEL-NEXT: v_add_i32_e32 v13, vcc, 32, v13 +; GISEL-NEXT: v_add_i32_e32 v15, vcc, 32, v15 ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GISEL-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[8:9] -; GISEL-NEXT: v_add_i32_e64 v0, s[6:7], 32, v17 -; GISEL-NEXT: v_add_i32_e64 v1, s[6:7], 32, v21 -; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], 32, v23 -; GISEL-NEXT: v_add_i32_e64 v9, s[6:7], 32, v25 -; GISEL-NEXT: v_min_u32_e32 v0, v16, v0 -; GISEL-NEXT: v_min_u32_e32 v1, v20, v1 -; GISEL-NEXT: v_min_u32_e32 v8, v22, v8 -; GISEL-NEXT: v_min_u32_e32 v9, v24, v9 -; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc +; GISEL-NEXT: v_min_u32_e32 v0, v12, v13 +; GISEL-NEXT: v_min_u32_e32 v1, v14, v15 ; GISEL-NEXT: v_add_i32_e32 v0, vcc, 64, v0 -; GISEL-NEXT: v_add_i32_e32 v8, vcc, 64, v8 -; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] -; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] -; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc -; GISEL-NEXT: v_sub_i32_e32 v16, vcc, v0, v1 -; GISEL-NEXT: v_subb_u32_e64 v17, s[4:5], 0, 0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GISEL-NEXT: v_sub_i32_e32 v14, vcc, v16, v0 +; GISEL-NEXT: v_subb_u32_e64 v15, s[4:5], 0, 0, vcc ; GISEL-NEXT: v_subb_u32_e64 v0, s[4:5], 0, 0, s[4:5] ; GISEL-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, s[4:5] -; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[16:17], v[10:11] -; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc -; GISEL-NEXT: v_xor_b32_e32 v8, 0x7f, v16 +; GISEL-NEXT: v_cmp_gt_u64_e32 vcc, v[14:15], v[8:9] +; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc +; GISEL-NEXT: v_xor_b32_e32 v8, 0x7f, v14 ; GISEL-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1] -; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; GISEL-NEXT: v_or_b32_e32 v8, v8, v0 -; GISEL-NEXT: v_or_b32_e32 v9, v17, v1 +; GISEL-NEXT: v_or_b32_e32 v9, v15, v1 ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GISEL-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc ; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9] ; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc -; GISEL-NEXT: v_or_b32_e32 v9, v20, v10 -; GISEL-NEXT: v_and_b32_e32 v10, 1, v9 +; GISEL-NEXT: v_or_b32_e32 v9, v17, v12 +; GISEL-NEXT: v_and_b32_e32 v12, 1, v9 ; GISEL-NEXT: v_or_b32_e32 v8, v9, v8 -; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 -; GISEL-NEXT: v_cndmask_b32_e64 v10, v4, 0, vcc -; GISEL-NEXT: v_and_b32_e32 v20, 1, v8 -; GISEL-NEXT: v_cndmask_b32_e64 v11, v5, 0, vcc +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 +; GISEL-NEXT: v_cndmask_b32_e64 v12, v4, 0, vcc +; GISEL-NEXT: v_and_b32_e32 v16, 1, v8 +; GISEL-NEXT: v_cndmask_b32_e64 v13, v5, 0, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v8, v6, 0, vcc ; GISEL-NEXT: v_cndmask_b32_e64 v9, v7, 0, vcc -; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v20 +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 -; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[4:5] -; GISEL-NEXT: s_cbranch_execz .LBB1_12 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; GISEL-NEXT: s_cbranch_execz .LBB3_12 ; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 -; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v16 -; GISEL-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v17, vcc -; GISEL-NEXT: v_sub_i32_e32 v26, vcc, 0x7f, v16 -; GISEL-NEXT: v_not_b32_e32 v9, 63 -; GISEL-NEXT: v_addc_u32_e64 v24, vcc, 0, v0, s[4:5] -; GISEL-NEXT: v_addc_u32_e32 v25, vcc, 0, v1, vcc -; GISEL-NEXT: v_add_i32_e64 v9, s[4:5], v26, v9 -; GISEL-NEXT: v_sub_i32_e64 v10, s[4:5], 64, v26 -; GISEL-NEXT: v_lshl_b64 v[0:1], v[4:5], v26 -; GISEL-NEXT: v_lshl_b64 v[16:17], v[6:7], v26 +; GISEL-NEXT: v_add_i32_e32 v18, vcc, 1, v14 +; GISEL-NEXT: v_addc_u32_e64 v19, s[4:5], 0, v15, vcc +; GISEL-NEXT: v_sub_i32_e32 v16, vcc, 0x7f, v14 +; GISEL-NEXT: v_not_b32_e32 v8, 63 +; GISEL-NEXT: v_addc_u32_e64 v20, vcc, 0, v0, s[4:5] +; GISEL-NEXT: v_addc_u32_e32 v21, vcc, 0, v1, vcc +; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v16, v8 +; GISEL-NEXT: v_sub_i32_e64 v12, s[4:5], 64, v16 +; GISEL-NEXT: v_lshl_b64 v[0:1], v[4:5], v16 +; GISEL-NEXT: v_lshl_b64 v[8:9], v[6:7], v16 ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 -; GISEL-NEXT: v_lshr_b64 v[20:21], v[4:5], v10 -; GISEL-NEXT: v_lshl_b64 v[22:23], v[4:5], v9 -; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v26 -; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v0, vcc -; GISEL-NEXT: v_cndmask_b32_e32 v10, 0, v1, vcc -; GISEL-NEXT: v_or_b32_e32 v0, v20, v16 -; GISEL-NEXT: v_or_b32_e32 v1, v21, v17 -; GISEL-NEXT: v_cndmask_b32_e32 v0, v22, v0, vcc -; GISEL-NEXT: v_cndmask_b32_e32 v1, v23, v1, vcc -; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v26 -; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc -; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc +; GISEL-NEXT: v_lshr_b64 v[12:13], v[4:5], v12 +; GISEL-NEXT: v_lshl_b64 v[14:15], v[4:5], v14 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v16 +; GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GISEL-NEXT: v_or_b32_e32 v8, v12, v8 +; GISEL-NEXT: v_or_b32_e32 v9, v13, v9 +; GISEL-NEXT: v_cndmask_b32_e32 v8, v14, v8, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v9, v15, v9, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16 +; GISEL-NEXT: v_cndmask_b32_e32 v8, v8, v6, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v9, v9, v7, vcc ; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] -; GISEL-NEXT: v_mov_b32_e32 v23, s11 -; GISEL-NEXT: v_mov_b32_e32 v22, s10 -; GISEL-NEXT: v_mov_b32_e32 v21, s9 -; GISEL-NEXT: v_mov_b32_e32 v20, s8 -; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] -; GISEL-NEXT: s_xor_b64 s[8:9], exec, s[6:7] -; GISEL-NEXT: s_cbranch_execz .LBB1_11 +; GISEL-NEXT: v_mov_b32_e32 v15, s11 +; GISEL-NEXT: v_mov_b32_e32 v14, s10 +; GISEL-NEXT: v_mov_b32_e32 v13, s9 +; GISEL-NEXT: v_mov_b32_e32 v12, s8 +; GISEL-NEXT: s_and_saveexec_b64 s[8:9], s[4:5] +; GISEL-NEXT: s_xor_b64 s[12:13], exec, s[8:9] +; GISEL-NEXT: s_cbranch_execz .LBB3_11 ; GISEL-NEXT: ; %bb.8: ; %udiv-preheader -; GISEL-NEXT: v_add_i32_e32 v28, vcc, 0xffffffc0, v8 -; GISEL-NEXT: v_sub_i32_e32 v22, vcc, 64, v8 -; GISEL-NEXT: v_lshr_b64 v[16:17], v[6:7], v8 -; GISEL-NEXT: v_lshr_b64 v[20:21], v[4:5], v8 -; GISEL-NEXT: s_mov_b64 s[4:5], 0 -; GISEL-NEXT: v_add_i32_e32 v26, vcc, -1, v12 -; GISEL-NEXT: v_addc_u32_e32 v27, vcc, -1, v13, vcc -; GISEL-NEXT: v_lshl_b64 v[22:23], v[6:7], v22 -; GISEL-NEXT: v_lshr_b64 v[6:7], v[6:7], v28 -; GISEL-NEXT: v_addc_u32_e32 v28, vcc, -1, v14, vcc -; GISEL-NEXT: v_addc_u32_e32 v29, vcc, -1, v15, vcc -; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5] -; GISEL-NEXT: v_or_b32_e32 v20, v20, v22 -; GISEL-NEXT: v_or_b32_e32 v21, v21, v23 -; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v8 -; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v20, vcc -; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v21, vcc -; GISEL-NEXT: v_cndmask_b32_e32 v16, 0, v16, vcc -; GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v17, vcc -; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8 -; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v4, vcc -; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v5, vcc +; GISEL-NEXT: v_add_i32_e32 v22, vcc, 0xffffffc0, v18 +; GISEL-NEXT: v_sub_i32_e32 v16, vcc, 64, v18 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v18 +; GISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18 +; GISEL-NEXT: v_lshr_b64 v[12:13], v[6:7], v18 +; GISEL-NEXT: v_lshr_b64 v[14:15], v[4:5], v18 +; GISEL-NEXT: v_lshl_b64 v[16:17], v[6:7], v16 +; GISEL-NEXT: v_or_b32_e32 v14, v14, v16 +; GISEL-NEXT: v_or_b32_e32 v15, v15, v17 +; GISEL-NEXT: s_mov_b64 s[8:9], 0 +; GISEL-NEXT: v_lshr_b64 v[6:7], v[6:7], v22 +; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v14, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v7, v7, v15, vcc +; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v4, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[4:5] +; GISEL-NEXT: v_cndmask_b32_e32 v16, 0, v12, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v17, 0, v13, vcc +; GISEL-NEXT: s_mov_b64 s[10:11], s[8:9] ; GISEL-NEXT: v_mov_b32_e32 v5, 0 -; GISEL-NEXT: v_mov_b32_e32 v23, s7 -; GISEL-NEXT: v_mov_b32_e32 v22, s6 -; GISEL-NEXT: v_mov_b32_e32 v21, s5 -; GISEL-NEXT: v_mov_b32_e32 v20, s4 -; GISEL-NEXT: .LBB1_9: ; %udiv-do-while +; GISEL-NEXT: v_mov_b32_e32 v15, s11 +; GISEL-NEXT: v_mov_b32_e32 v14, s10 +; GISEL-NEXT: v_mov_b32_e32 v13, s9 +; GISEL-NEXT: v_mov_b32_e32 v12, s8 +; GISEL-NEXT: .LBB3_9: ; %udiv-do-while ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 -; GISEL-NEXT: v_lshl_b64 v[22:23], v[6:7], 1 -; GISEL-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 -; GISEL-NEXT: v_lshrrev_b32_e32 v4, 31, v7 -; GISEL-NEXT: v_lshrrev_b32_e32 v30, 31, v1 -; GISEL-NEXT: v_lshl_b64 v[6:7], v[9:10], 1 -; GISEL-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 -; GISEL-NEXT: v_lshrrev_b32_e32 v9, 31, v10 -; GISEL-NEXT: v_add_i32_e32 v8, vcc, -1, v8 -; GISEL-NEXT: v_addc_u32_e32 v11, vcc, -1, v11, vcc -; GISEL-NEXT: v_or_b32_e32 v16, v16, v4 -; GISEL-NEXT: v_or_b32_e32 v22, v22, v30 -; GISEL-NEXT: v_or_b32_e32 v0, v0, v9 -; GISEL-NEXT: v_or_b32_e32 v9, v20, v6 -; GISEL-NEXT: v_or_b32_e32 v10, v21, v7 -; GISEL-NEXT: v_addc_u32_e32 v24, vcc, -1, v24, vcc -; GISEL-NEXT: v_addc_u32_e32 v25, vcc, -1, v25, vcc -; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v26, v22 -; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v27, v23, vcc -; GISEL-NEXT: v_or_b32_e32 v6, v8, v24 -; GISEL-NEXT: v_or_b32_e32 v7, v11, v25 -; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v28, v16, vcc -; GISEL-NEXT: v_subb_u32_e32 v4, vcc, v29, v17, vcc -; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] -; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v4 -; GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GISEL-NEXT: v_and_b32_e32 v4, 1, v6 -; GISEL-NEXT: v_and_b32_e32 v7, v6, v12 -; GISEL-NEXT: v_and_b32_e32 v30, v6, v13 -; GISEL-NEXT: v_and_b32_e32 v31, v6, v14 -; GISEL-NEXT: v_and_b32_e32 v32, v6, v15 -; GISEL-NEXT: v_mov_b32_e32 v21, v5 -; GISEL-NEXT: v_mov_b32_e32 v20, v4 -; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v22, v7 -; GISEL-NEXT: v_subb_u32_e32 v7, vcc, v23, v30, vcc -; GISEL-NEXT: v_subb_u32_e32 v16, vcc, v16, v31, vcc -; GISEL-NEXT: v_subb_u32_e32 v17, vcc, v17, v32, vcc -; GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5] -; GISEL-NEXT: s_cbranch_execnz .LBB1_9 +; GISEL-NEXT: v_lshl_b64 v[14:15], v[0:1], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v4, 31, v1 +; GISEL-NEXT: v_or_b32_e32 v0, v12, v14 +; GISEL-NEXT: v_or_b32_e32 v1, v13, v15 +; GISEL-NEXT: v_lshl_b64 v[12:13], v[6:7], 1 +; GISEL-NEXT: v_lshl_b64 v[14:15], v[16:17], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v6, 31, v7 +; GISEL-NEXT: v_lshrrev_b32_e32 v7, 31, v9 +; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; GISEL-NEXT: v_add_i32_e32 v18, vcc, -1, v18 +; GISEL-NEXT: v_addc_u32_e32 v19, vcc, -1, v19, vcc +; GISEL-NEXT: v_or_b32_e32 v14, v14, v6 +; GISEL-NEXT: v_or_b32_e32 v6, v12, v7 +; GISEL-NEXT: v_or_b32_e32 v8, v8, v4 +; GISEL-NEXT: v_addc_u32_e32 v20, vcc, -1, v20, vcc +; GISEL-NEXT: v_addc_u32_e32 v21, vcc, -1, v21, vcc +; GISEL-NEXT: v_sub_i32_e32 v4, vcc, 1, v13 +; GISEL-NEXT: v_subb_u32_e32 v4, vcc, 0, v14, vcc +; GISEL-NEXT: v_subrev_i32_e64 v6, s[4:5], 0, v6 +; GISEL-NEXT: v_or_b32_e32 v16, v18, v20 +; GISEL-NEXT: v_or_b32_e32 v17, v19, v21 +; GISEL-NEXT: v_subb_u32_e32 v4, vcc, 0, v15, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[16:17] +; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v4 +; GISEL-NEXT: v_and_b32_e32 v4, 1, v7 +; GISEL-NEXT: v_and_b32_e32 v7, 2, v7 +; GISEL-NEXT: v_sub_i32_e64 v7, s[4:5], v13, v7 +; GISEL-NEXT: v_mov_b32_e32 v13, v5 +; GISEL-NEXT: v_mov_b32_e32 v12, v4 +; GISEL-NEXT: v_subbrev_u32_e64 v16, s[4:5], 0, v14, s[4:5] +; GISEL-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GISEL-NEXT: v_subbrev_u32_e64 v17, vcc, 0, v15, s[4:5] +; GISEL-NEXT: s_andn2_b64 exec, exec, s[8:9] +; GISEL-NEXT: s_cbranch_execnz .LBB3_9 ; GISEL-NEXT: ; %bb.10: ; %Flow -; GISEL-NEXT: s_or_b64 exec, exec, s[4:5] -; GISEL-NEXT: .LBB1_11: ; %Flow11 ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] -; GISEL-NEXT: v_lshl_b64 v[4:5], v[9:10], 1 -; GISEL-NEXT: v_lshl_b64 v[8:9], v[0:1], 1 -; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v10 -; GISEL-NEXT: v_or_b32_e32 v8, v8, v0 -; GISEL-NEXT: v_or_b32_e32 v10, v20, v4 -; GISEL-NEXT: v_or_b32_e32 v11, v21, v5 -; GISEL-NEXT: .LBB1_12: ; %Flow12 +; GISEL-NEXT: .LBB3_11: ; %Flow11 ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] -; GISEL-NEXT: v_mov_b32_e32 v0, v18 -; GISEL-NEXT: v_mov_b32_e32 v1, v19 -; GISEL-NEXT: v_mov_b32_e32 v4, v10 -; GISEL-NEXT: v_mov_b32_e32 v5, v11 +; GISEL-NEXT: v_lshl_b64 v[4:5], v[0:1], 1 +; GISEL-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; GISEL-NEXT: v_lshrrev_b32_e32 v0, 31, v1 +; GISEL-NEXT: v_or_b32_e32 v8, v8, v0 +; GISEL-NEXT: v_or_b32_e32 v12, v12, v4 +; GISEL-NEXT: v_or_b32_e32 v13, v13, v5 +; GISEL-NEXT: .LBB3_12: ; %Flow12 +; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-NEXT: v_mov_b32_e32 v0, v10 +; GISEL-NEXT: v_mov_b32_e32 v1, v11 +; GISEL-NEXT: v_mov_b32_e32 v4, v12 +; GISEL-NEXT: v_mov_b32_e32 v5, v13 ; GISEL-NEXT: v_mov_b32_e32 v6, v8 ; GISEL-NEXT: v_mov_b32_e32 v7, v9 ; GISEL-NEXT: s_setpc_b64 s[30:31] - %shl = udiv <2 x i128> %lhs, %rhs + %shl = udiv <2 x i128> %lhs, ret <2 x i128> %shl } @@ -1624,7 +2932,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: s_and_b64 s[8:9], s[6:7], vcc ; SDAG-NEXT: v_cndmask_b32_e64 v34, v16, 0, s[4:5] ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] -; SDAG-NEXT: s_cbranch_execz .LBB2_6 +; SDAG-NEXT: s_cbranch_execz .LBB4_6 ; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 ; SDAG-NEXT: v_add_i32_e32 v32, vcc, 1, v10 ; SDAG-NEXT: v_sub_i32_e64 v8, s[4:5], 63, v10 @@ -1654,7 +2962,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v11, 0 ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB2_5 +; SDAG-NEXT: s_cbranch_execz .LBB4_5 ; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 ; SDAG-NEXT: v_lshr_b64 v[22:23], v[16:17], v32 ; SDAG-NEXT: v_sub_i32_e32 v10, vcc, 64, v32 @@ -1682,7 +2990,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_cndmask_b32_e32 v24, v22, v16, vcc ; SDAG-NEXT: v_mov_b32_e32 v22, 0 ; SDAG-NEXT: v_mov_b32_e32 v23, 0 -; SDAG-NEXT: .LBB2_3: ; %udiv-do-while3 +; SDAG-NEXT: .LBB4_3: ; %udiv-do-while3 ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 ; SDAG-NEXT: v_lshrrev_b32_e32 v10, 31, v19 ; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1 @@ -1723,10 +3031,10 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v23, v11 ; SDAG-NEXT: v_mov_b32_e32 v22, v10 ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] -; SDAG-NEXT: s_cbranch_execnz .LBB2_3 +; SDAG-NEXT: s_cbranch_execnz .LBB4_3 ; SDAG-NEXT: ; %bb.4: ; %Flow13 ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] -; SDAG-NEXT: .LBB2_5: ; %Flow14 +; SDAG-NEXT: .LBB4_5: ; %Flow14 ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] ; SDAG-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v19 @@ -1734,7 +3042,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_or_b32_e32 v8, v8, v20 ; SDAG-NEXT: v_or_b32_e32 v33, v11, v19 ; SDAG-NEXT: v_or_b32_e32 v34, v10, v18 -; SDAG-NEXT: .LBB2_6: ; %Flow16 +; SDAG-NEXT: .LBB4_6: ; %Flow16 ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] ; SDAG-NEXT: v_ashrrev_i32_e32 v32, 31, v7 ; SDAG-NEXT: v_sub_i32_e32 v10, vcc, 0, v4 @@ -1815,7 +3123,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_cndmask_b32_e64 v21, v10, 0, s[4:5] ; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB2_12 +; SDAG-NEXT: s_cbranch_execz .LBB4_12 ; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 ; SDAG-NEXT: v_add_i32_e32 v38, vcc, 1, v12 ; SDAG-NEXT: v_sub_i32_e64 v14, s[4:5], 63, v12 @@ -1845,7 +3153,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v19, 0 ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB2_11 +; SDAG-NEXT: s_cbranch_execz .LBB4_11 ; SDAG-NEXT: ; %bb.8: ; %udiv-preheader ; SDAG-NEXT: v_lshr_b64 v[22:23], v[10:11], v38 ; SDAG-NEXT: v_sub_i32_e32 v18, vcc, 64, v38 @@ -1873,7 +3181,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_cndmask_b32_e32 v24, v22, v10, vcc ; SDAG-NEXT: v_mov_b32_e32 v22, 0 ; SDAG-NEXT: v_mov_b32_e32 v23, 0 -; SDAG-NEXT: .LBB2_9: ; %udiv-do-while +; SDAG-NEXT: .LBB4_9: ; %udiv-do-while ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 ; SDAG-NEXT: v_lshl_b64 v[26:27], v[26:27], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v25 @@ -1914,10 +3222,10 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v23, v19 ; SDAG-NEXT: v_mov_b32_e32 v22, v18 ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] -; SDAG-NEXT: s_cbranch_execnz .LBB2_9 +; SDAG-NEXT: s_cbranch_execnz .LBB4_9 ; SDAG-NEXT: ; %bb.10: ; %Flow ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] -; SDAG-NEXT: .LBB2_11: ; %Flow11 +; SDAG-NEXT: .LBB4_11: ; %Flow11 ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] ; SDAG-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v20, 31, v13 @@ -1925,7 +3233,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_or_b32_e32 v14, v14, v20 ; SDAG-NEXT: v_or_b32_e32 v20, v19, v13 ; SDAG-NEXT: v_or_b32_e32 v21, v18, v12 -; SDAG-NEXT: .LBB2_12: ; %Flow12 +; SDAG-NEXT: .LBB4_12: ; %Flow12 ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] ; SDAG-NEXT: v_mul_lo_u32 v18, v34, v3 ; SDAG-NEXT: v_mad_u64_u32 v[12:13], s[4:5], v34, v2, 0 @@ -2075,7 +3383,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GISEL-NEXT: v_cndmask_b32_e64 v32, v17, 0, vcc ; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[4:5] -; GISEL-NEXT: s_cbranch_execz .LBB2_6 +; GISEL-NEXT: s_cbranch_execz .LBB4_6 ; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 ; GISEL-NEXT: v_add_i32_e32 v31, vcc, 1, v2 ; GISEL-NEXT: v_addc_u32_e64 v32, s[4:5], 0, v3, vcc @@ -2107,7 +3415,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v3, s11 ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GISEL-NEXT: s_xor_b64 s[8:9], exec, s[6:7] -; GISEL-NEXT: s_cbranch_execz .LBB2_5 +; GISEL-NEXT: s_cbranch_execz .LBB4_5 ; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 ; GISEL-NEXT: v_add_i32_e32 v24, vcc, 0xffffffc0, v31 ; GISEL-NEXT: v_sub_i32_e32 v22, vcc, 64, v31 @@ -2136,7 +3444,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v1, s5 ; GISEL-NEXT: v_mov_b32_e32 v2, s6 ; GISEL-NEXT: v_mov_b32_e32 v3, s7 -; GISEL-NEXT: .LBB2_3: ; %udiv-do-while3 +; GISEL-NEXT: .LBB4_3: ; %udiv-do-while3 ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_lshrrev_b32_e32 v39, 31, v21 ; GISEL-NEXT: v_lshl_b64 v[2:3], v[20:21], 1 @@ -2175,10 +3483,10 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v0, v22 ; GISEL-NEXT: v_mov_b32_e32 v1, v23 ; GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5] -; GISEL-NEXT: s_cbranch_execnz .LBB2_3 +; GISEL-NEXT: s_cbranch_execnz .LBB4_3 ; GISEL-NEXT: ; %bb.4: ; %Flow13 ; GISEL-NEXT: s_or_b64 exec, exec, s[4:5] -; GISEL-NEXT: .LBB2_5: ; %Flow14 +; GISEL-NEXT: .LBB4_5: ; %Flow14 ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] ; GISEL-NEXT: v_lshl_b64 v[2:3], v[20:21], 1 ; GISEL-NEXT: v_lshl_b64 v[18:19], v[18:19], 1 @@ -2186,7 +3494,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_or_b32_e32 v18, v18, v20 ; GISEL-NEXT: v_or_b32_e32 v31, v0, v2 ; GISEL-NEXT: v_or_b32_e32 v32, v1, v3 -; GISEL-NEXT: .LBB2_6: ; %Flow16 +; GISEL-NEXT: .LBB4_6: ; %Flow16 ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] ; GISEL-NEXT: s_mov_b64 s[8:9], 0 ; GISEL-NEXT: v_ashrrev_i32_e32 v33, 31, v7 @@ -2266,7 +3574,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v22 ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 ; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[4:5] -; GISEL-NEXT: s_cbranch_execz .LBB2_12 +; GISEL-NEXT: s_cbranch_execz .LBB4_12 ; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 ; GISEL-NEXT: v_add_i32_e32 v36, vcc, 1, v14 ; GISEL-NEXT: v_addc_u32_e64 v37, s[4:5], 0, v15, vcc @@ -2298,7 +3606,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v3, s11 ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GISEL-NEXT: s_xor_b64 s[8:9], exec, s[6:7] -; GISEL-NEXT: s_cbranch_execz .LBB2_11 +; GISEL-NEXT: s_cbranch_execz .LBB4_11 ; GISEL-NEXT: ; %bb.8: ; %udiv-preheader ; GISEL-NEXT: v_add_i32_e32 v24, vcc, 0xffffffc0, v36 ; GISEL-NEXT: v_sub_i32_e32 v22, vcc, 64, v36 @@ -2327,7 +3635,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v1, s5 ; GISEL-NEXT: v_mov_b32_e32 v2, s6 ; GISEL-NEXT: v_mov_b32_e32 v3, s7 -; GISEL-NEXT: .LBB2_9: ; %udiv-do-while +; GISEL-NEXT: .LBB4_9: ; %udiv-do-while ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_lshl_b64 v[2:3], v[20:21], 1 ; GISEL-NEXT: v_lshrrev_b32_e32 v22, 31, v21 @@ -2366,10 +3674,10 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_subb_u32_e32 v26, vcc, v2, v26, vcc ; GISEL-NEXT: v_subb_u32_e32 v27, vcc, v27, v52, vcc ; GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5] -; GISEL-NEXT: s_cbranch_execnz .LBB2_9 +; GISEL-NEXT: s_cbranch_execnz .LBB4_9 ; GISEL-NEXT: ; %bb.10: ; %Flow ; GISEL-NEXT: s_or_b64 exec, exec, s[4:5] -; GISEL-NEXT: .LBB2_11: ; %Flow11 +; GISEL-NEXT: .LBB4_11: ; %Flow11 ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] ; GISEL-NEXT: v_lshl_b64 v[22:23], v[20:21], 1 ; GISEL-NEXT: v_lshl_b64 v[2:3], v[14:15], 1 @@ -2377,7 +3685,7 @@ define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_or_b32_e32 v2, v2, v14 ; GISEL-NEXT: v_or_b32_e32 v20, v0, v22 ; GISEL-NEXT: v_or_b32_e32 v21, v1, v23 -; GISEL-NEXT: .LBB2_12: ; %Flow12 +; GISEL-NEXT: .LBB4_12: ; %Flow12 ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] ; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v30, v31, 0 ; GISEL-NEXT: v_mad_u64_u32 v[14:15], s[4:5], v30, v18, 0 @@ -2495,7 +3803,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: s_and_b64 s[8:9], s[6:7], vcc ; SDAG-NEXT: v_cndmask_b32_e64 v33, v0, 0, s[4:5] ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] -; SDAG-NEXT: s_cbranch_execz .LBB3_6 +; SDAG-NEXT: s_cbranch_execz .LBB5_6 ; SDAG-NEXT: ; %bb.1: ; %udiv-bb15 ; SDAG-NEXT: v_add_i32_e32 v30, vcc, 1, v18 ; SDAG-NEXT: v_sub_i32_e64 v16, s[4:5], 63, v18 @@ -2525,7 +3833,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v19, 0 ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB3_5 +; SDAG-NEXT: s_cbranch_execz .LBB5_5 ; SDAG-NEXT: ; %bb.2: ; %udiv-preheader4 ; SDAG-NEXT: v_lshr_b64 v[24:25], v[0:1], v30 ; SDAG-NEXT: v_sub_i32_e32 v18, vcc, 64, v30 @@ -2553,7 +3861,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_cndmask_b32_e32 v26, v24, v0, vcc ; SDAG-NEXT: v_mov_b32_e32 v24, 0 ; SDAG-NEXT: v_mov_b32_e32 v25, 0 -; SDAG-NEXT: .LBB3_3: ; %udiv-do-while3 +; SDAG-NEXT: .LBB5_3: ; %udiv-do-while3 ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 ; SDAG-NEXT: v_lshrrev_b32_e32 v18, 31, v21 ; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 @@ -2594,10 +3902,10 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v25, v19 ; SDAG-NEXT: v_mov_b32_e32 v24, v18 ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] -; SDAG-NEXT: s_cbranch_execnz .LBB3_3 +; SDAG-NEXT: s_cbranch_execnz .LBB5_3 ; SDAG-NEXT: ; %bb.4: ; %Flow13 ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] -; SDAG-NEXT: .LBB3_5: ; %Flow14 +; SDAG-NEXT: .LBB5_5: ; %Flow14 ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] ; SDAG-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v21 @@ -2605,7 +3913,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 ; SDAG-NEXT: v_or_b32_e32 v32, v19, v21 ; SDAG-NEXT: v_or_b32_e32 v33, v18, v20 -; SDAG-NEXT: .LBB3_6: ; %Flow16 +; SDAG-NEXT: .LBB5_6: ; %Flow16 ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] ; SDAG-NEXT: v_or_b32_e32 v19, v13, v15 ; SDAG-NEXT: v_or_b32_e32 v18, v12, v14 @@ -2666,7 +3974,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_cndmask_b32_e64 v25, v4, 0, s[4:5] ; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB3_12 +; SDAG-NEXT: s_cbranch_execz .LBB5_12 ; SDAG-NEXT: ; %bb.7: ; %udiv-bb1 ; SDAG-NEXT: v_add_i32_e32 v34, vcc, 1, v20 ; SDAG-NEXT: v_sub_i32_e64 v18, s[4:5], 63, v20 @@ -2696,7 +4004,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v23, 0 ; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5] -; SDAG-NEXT: s_cbranch_execz .LBB3_11 +; SDAG-NEXT: s_cbranch_execz .LBB5_11 ; SDAG-NEXT: ; %bb.8: ; %udiv-preheader ; SDAG-NEXT: v_lshr_b64 v[26:27], v[4:5], v34 ; SDAG-NEXT: v_sub_i32_e32 v22, vcc, 64, v34 @@ -2724,7 +4032,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_cndmask_b32_e32 v28, v26, v4, vcc ; SDAG-NEXT: v_mov_b32_e32 v26, 0 ; SDAG-NEXT: v_mov_b32_e32 v27, 0 -; SDAG-NEXT: .LBB3_9: ; %udiv-do-while +; SDAG-NEXT: .LBB5_9: ; %udiv-do-while ; SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 ; SDAG-NEXT: v_lshl_b64 v[30:31], v[30:31], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v22, 31, v29 @@ -2765,10 +4073,10 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_mov_b32_e32 v27, v23 ; SDAG-NEXT: v_mov_b32_e32 v26, v22 ; SDAG-NEXT: s_andn2_b64 exec, exec, s[10:11] -; SDAG-NEXT: s_cbranch_execnz .LBB3_9 +; SDAG-NEXT: s_cbranch_execnz .LBB5_9 ; SDAG-NEXT: ; %bb.10: ; %Flow ; SDAG-NEXT: s_or_b64 exec, exec, s[10:11] -; SDAG-NEXT: .LBB3_11: ; %Flow11 +; SDAG-NEXT: .LBB5_11: ; %Flow11 ; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] ; SDAG-NEXT: v_lshl_b64 v[18:19], v[18:19], 1 ; SDAG-NEXT: v_lshrrev_b32_e32 v24, 31, v21 @@ -2776,7 +4084,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; SDAG-NEXT: v_or_b32_e32 v18, v18, v24 ; SDAG-NEXT: v_or_b32_e32 v24, v23, v21 ; SDAG-NEXT: v_or_b32_e32 v25, v22, v20 -; SDAG-NEXT: .LBB3_12: ; %Flow12 +; SDAG-NEXT: .LBB5_12: ; %Flow12 ; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] ; SDAG-NEXT: v_mul_lo_u32 v23, v33, v11 ; SDAG-NEXT: v_mad_u64_u32 v[26:27], s[4:5], v33, v10, 0 @@ -2890,7 +4198,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: s_xor_b64 s[4:5], s[4:5], -1 ; GISEL-NEXT: v_cndmask_b32_e64 v33, v1, 0, vcc ; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[4:5] -; GISEL-NEXT: s_cbranch_execz .LBB3_6 +; GISEL-NEXT: s_cbranch_execz .LBB5_6 ; GISEL-NEXT: ; %bb.1: ; %udiv-bb15 ; GISEL-NEXT: v_add_i32_e32 v30, vcc, 1, v18 ; GISEL-NEXT: v_addc_u32_e64 v31, s[4:5], 0, v19, vcc @@ -2922,7 +4230,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v16, s8 ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GISEL-NEXT: s_xor_b64 s[8:9], exec, s[6:7] -; GISEL-NEXT: s_cbranch_execz .LBB3_5 +; GISEL-NEXT: s_cbranch_execz .LBB5_5 ; GISEL-NEXT: ; %bb.2: ; %udiv-preheader4 ; GISEL-NEXT: v_add_i32_e32 v26, vcc, 0xffffffc0, v30 ; GISEL-NEXT: v_sub_i32_e32 v24, vcc, 64, v30 @@ -2951,7 +4259,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v18, s6 ; GISEL-NEXT: v_mov_b32_e32 v17, s5 ; GISEL-NEXT: v_mov_b32_e32 v16, s4 -; GISEL-NEXT: .LBB3_3: ; %udiv-do-while3 +; GISEL-NEXT: .LBB5_3: ; %udiv-do-while3 ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_lshrrev_b32_e32 v38, 31, v23 ; GISEL-NEXT: v_lshl_b64 v[18:19], v[22:23], 1 @@ -2990,10 +4298,10 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v16, v24 ; GISEL-NEXT: v_mov_b32_e32 v17, v25 ; GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5] -; GISEL-NEXT: s_cbranch_execnz .LBB3_3 +; GISEL-NEXT: s_cbranch_execnz .LBB5_3 ; GISEL-NEXT: ; %bb.4: ; %Flow13 ; GISEL-NEXT: s_or_b64 exec, exec, s[4:5] -; GISEL-NEXT: .LBB3_5: ; %Flow14 +; GISEL-NEXT: .LBB5_5: ; %Flow14 ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] ; GISEL-NEXT: v_lshl_b64 v[18:19], v[22:23], 1 ; GISEL-NEXT: v_lshl_b64 v[20:21], v[20:21], 1 @@ -3001,7 +4309,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_or_b32_e32 v20, v20, v22 ; GISEL-NEXT: v_or_b32_e32 v32, v16, v18 ; GISEL-NEXT: v_or_b32_e32 v33, v17, v19 -; GISEL-NEXT: .LBB3_6: ; %Flow16 +; GISEL-NEXT: .LBB5_6: ; %Flow16 ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] ; GISEL-NEXT: s_mov_b64 s[8:9], 0 ; GISEL-NEXT: v_or_b32_e32 v16, v12, v14 @@ -3063,7 +4371,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 ; GISEL-NEXT: s_xor_b64 s[4:5], vcc, -1 ; GISEL-NEXT: s_and_saveexec_b64 s[12:13], s[4:5] -; GISEL-NEXT: s_cbranch_execz .LBB3_12 +; GISEL-NEXT: s_cbranch_execz .LBB5_12 ; GISEL-NEXT: ; %bb.7: ; %udiv-bb1 ; GISEL-NEXT: v_add_i32_e32 v34, vcc, 1, v22 ; GISEL-NEXT: v_addc_u32_e64 v35, s[4:5], 0, v23, vcc @@ -3095,7 +4403,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v16, s8 ; GISEL-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GISEL-NEXT: s_xor_b64 s[8:9], exec, s[6:7] -; GISEL-NEXT: s_cbranch_execz .LBB3_11 +; GISEL-NEXT: s_cbranch_execz .LBB5_11 ; GISEL-NEXT: ; %bb.8: ; %udiv-preheader ; GISEL-NEXT: v_add_i32_e32 v28, vcc, 0xffffffc0, v34 ; GISEL-NEXT: v_sub_i32_e32 v26, vcc, 64, v34 @@ -3124,7 +4432,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_mov_b32_e32 v18, s6 ; GISEL-NEXT: v_mov_b32_e32 v17, s5 ; GISEL-NEXT: v_mov_b32_e32 v16, s4 -; GISEL-NEXT: .LBB3_9: ; %udiv-do-while +; GISEL-NEXT: .LBB5_9: ; %udiv-do-while ; GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 ; GISEL-NEXT: v_lshl_b64 v[18:19], v[24:25], 1 ; GISEL-NEXT: v_lshrrev_b32_e32 v26, 31, v25 @@ -3163,10 +4471,10 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_subb_u32_e32 v30, vcc, v18, v30, vcc ; GISEL-NEXT: v_subb_u32_e32 v31, vcc, v31, v50, vcc ; GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5] -; GISEL-NEXT: s_cbranch_execnz .LBB3_9 +; GISEL-NEXT: s_cbranch_execnz .LBB5_9 ; GISEL-NEXT: ; %bb.10: ; %Flow ; GISEL-NEXT: s_or_b64 exec, exec, s[4:5] -; GISEL-NEXT: .LBB3_11: ; %Flow11 +; GISEL-NEXT: .LBB5_11: ; %Flow11 ; GISEL-NEXT: s_or_b64 exec, exec, s[8:9] ; GISEL-NEXT: v_lshl_b64 v[26:27], v[24:25], 1 ; GISEL-NEXT: v_lshl_b64 v[18:19], v[22:23], 1 @@ -3174,7 +4482,7 @@ define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) { ; GISEL-NEXT: v_or_b32_e32 v18, v18, v22 ; GISEL-NEXT: v_or_b32_e32 v24, v16, v26 ; GISEL-NEXT: v_or_b32_e32 v25, v17, v27 -; GISEL-NEXT: .LBB3_12: ; %Flow12 +; GISEL-NEXT: .LBB5_12: ; %Flow12 ; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] ; GISEL-NEXT: v_mad_u64_u32 v[16:17], s[4:5], v8, v32, 0 ; GISEL-NEXT: v_mad_u64_u32 v[22:23], s[4:5], v8, v20, 0 diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll b/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll index 4253c593b3e7e..f411fa9be7f76 100644 --- a/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll +++ b/llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll @@ -75,6 +75,7 @@ ; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1151 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1151 %s ; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1152 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1152 %s ; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1153 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1153 %s +; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1170 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1170 %s ; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1200 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1200 %s ; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1201 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1201 %s ; RUN: llc -filetype=obj -mtriple=amdgcn -mcpu=gfx1250 < %s | llvm-readobj --file-header - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1250 %s @@ -159,6 +160,7 @@ ; GFX1151: EF_AMDGPU_MACH_AMDGCN_GFX1151 (0x4A) ; GFX1152: EF_AMDGPU_MACH_AMDGCN_GFX1152 (0x55) ; GFX1153: EF_AMDGPU_MACH_AMDGCN_GFX1153 (0x58) +; GFX1170: EF_AMDGPU_MACH_AMDGCN_GFX1170 (0x5D) ; GFX1200: EF_AMDGPU_MACH_AMDGCN_GFX1200 (0x48) ; GFX1201: EF_AMDGPU_MACH_AMDGCN_GFX1201 (0x4E) ; GFX1250: EF_AMDGPU_MACH_AMDGCN_GFX1250 (0x49) diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir index 7f370b2cca658..6550fa61c77ab 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir @@ -300,22 +300,22 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -326,12 +326,12 @@ body: | ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX8-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; GFX8-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.18, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.18, addrspace 5) ; GFX8-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: $sgpr4 = S_MOV_B32 128 ; GFX8-NEXT: $vgpr1, dead $sgpr6_sgpr7 = V_ADD_CO_U32_e64 killed $sgpr4, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec - ; GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.18, addrspace 5) + ; GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.18, addrspace 5) ; GFX8-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -340,43 +340,43 @@ body: | ; GFX8-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX8-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX8-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX8-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) - ; GFX8-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.16, addrspace 5) - ; GFX8-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GFX8-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GFX8-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GFX8-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GFX8-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GFX8-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GFX8-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GFX8-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GFX8-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GFX8-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GFX8-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GFX8-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) - ; GFX8-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; GFX8-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX8-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) + ; GFX8-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX8-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX8-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX8-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX8-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX8-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX8-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX8-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX8-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX8-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX8-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX8-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX8-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX8-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX8-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX8-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc, implicit killed $vcc ; ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX900-NEXT: {{ $}} - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -387,11 +387,11 @@ body: | ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX900-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; GFX900-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.18, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.18, addrspace 5) ; GFX900-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: $vgpr1 = V_ADD_U32_e32 128, killed $vgpr1, implicit $exec ; GFX900-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec - ; GFX900-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.18, addrspace 5) + ; GFX900-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.18, addrspace 5) ; GFX900-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -400,22 +400,22 @@ body: | ; GFX900-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX900-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX900-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX900-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) - ; GFX900-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.16, addrspace 5) - ; GFX900-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GFX900-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GFX900-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GFX900-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GFX900-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GFX900-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GFX900-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GFX900-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GFX900-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GFX900-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GFX900-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GFX900-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) - ; GFX900-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; GFX900-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX900-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) + ; GFX900-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX900-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX900-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX900-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX900-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX900-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX900-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX900-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX900-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX900-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX900-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX900-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX900-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX900-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX900-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX900-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc, implicit killed $vcc ; ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr @@ -447,11 +447,11 @@ body: | ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX90A-NEXT: V_CMP_EQ_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec ; GFX90A-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.18, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.18, addrspace 5) ; GFX90A-NEXT: $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_ADD_U32_e32 64, killed $vgpr1, implicit $exec ; GFX90A-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec - ; GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.18, addrspace 5) + ; GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.18, addrspace 5) ; GFX90A-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX90A-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX90A-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -481,22 +481,22 @@ body: | ; GFX1010-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX1010: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX1010-NEXT: {{ $}} - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) - ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) + ; GFX1010-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1010-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -518,43 +518,43 @@ body: | ; GFX1010-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX1010-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX1010-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX1010-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) - ; GFX1010-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.16, addrspace 5) - ; GFX1010-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GFX1010-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GFX1010-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GFX1010-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GFX1010-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GFX1010-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GFX1010-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GFX1010-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GFX1010-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GFX1010-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GFX1010-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GFX1010-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) - ; GFX1010-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; GFX1010-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX1010-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) + ; GFX1010-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX1010-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX1010-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX1010-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX1010-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX1010-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX1010-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX1010-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX1010-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX1010-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX1010-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX1010-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX1010-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX1010-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX1010-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX1010-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc, implicit killed $vcc_lo ; ; GFX1100-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX1100: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX1100-NEXT: {{ $}} - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr43, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr45, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr46, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.8, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr47, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr56, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.10, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr57, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.11, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr58, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.12, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr59, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.13, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr60, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.14, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr61, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.15, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr62, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.16, addrspace 5) - ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr63, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.17, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr43, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr45, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr46, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr47, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr56, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr57, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr58, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr59, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr60, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr61, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr62, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) + ; GFX1100-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr63, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1100-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -577,43 +577,43 @@ body: | ; GFX1100-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX1100-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX1100-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX1100-NEXT: $vgpr63 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.17, addrspace 5) - ; GFX1100-NEXT: $vgpr62 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.16, addrspace 5) - ; GFX1100-NEXT: $vgpr61 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.15, addrspace 5) - ; GFX1100-NEXT: $vgpr60 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.14, addrspace 5) - ; GFX1100-NEXT: $vgpr59 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.13, addrspace 5) - ; GFX1100-NEXT: $vgpr58 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.12, addrspace 5) - ; GFX1100-NEXT: $vgpr57 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.11, addrspace 5) - ; GFX1100-NEXT: $vgpr56 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.10, addrspace 5) - ; GFX1100-NEXT: $vgpr47 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) - ; GFX1100-NEXT: $vgpr46 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.8, addrspace 5) - ; GFX1100-NEXT: $vgpr45 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.7, addrspace 5) - ; GFX1100-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.6, addrspace 5) - ; GFX1100-NEXT: $vgpr43 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.5, addrspace 5) - ; GFX1100-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.4, addrspace 5) - ; GFX1100-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5) - ; GFX1100-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX1100-NEXT: $vgpr63 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) + ; GFX1100-NEXT: $vgpr62 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX1100-NEXT: $vgpr61 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX1100-NEXT: $vgpr60 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX1100-NEXT: $vgpr59 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX1100-NEXT: $vgpr58 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX1100-NEXT: $vgpr57 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX1100-NEXT: $vgpr56 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX1100-NEXT: $vgpr47 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX1100-NEXT: $vgpr46 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX1100-NEXT: $vgpr45 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX1100-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX1100-NEXT: $vgpr43 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX1100-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX1100-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX1100-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX1100-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc, implicit killed $vcc_lo ; ; GFX1200-LABEL: name: materialize_fi_s_mov_b32_offset_64_live_scc_live_vcc_no_vgpr ; GFX1200: liveins: $sgpr4, $sgpr5, $vgpr0, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr43, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr45, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr46, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.8, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr47, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr56, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.10, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr57, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.11, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr58, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.12, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr59, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.13, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr60, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.14, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr61, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.15, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr62, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.16, addrspace 5) - ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr63, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.17, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr40, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr43, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr45, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr46, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr47, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr56, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr57, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr58, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr59, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr60, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr61, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr62, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) + ; GFX1200-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr63, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX1200-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -636,22 +636,22 @@ body: | ; GFX1200-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX1200-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX1200-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX1200-NEXT: $vgpr63 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.17, addrspace 5) - ; GFX1200-NEXT: $vgpr62 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.16, addrspace 5) - ; GFX1200-NEXT: $vgpr61 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.15, addrspace 5) - ; GFX1200-NEXT: $vgpr60 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.14, addrspace 5) - ; GFX1200-NEXT: $vgpr59 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.13, addrspace 5) - ; GFX1200-NEXT: $vgpr58 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.12, addrspace 5) - ; GFX1200-NEXT: $vgpr57 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.11, addrspace 5) - ; GFX1200-NEXT: $vgpr56 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.10, addrspace 5) - ; GFX1200-NEXT: $vgpr47 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) - ; GFX1200-NEXT: $vgpr46 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.8, addrspace 5) - ; GFX1200-NEXT: $vgpr45 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.7, addrspace 5) - ; GFX1200-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.6, addrspace 5) - ; GFX1200-NEXT: $vgpr43 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.5, addrspace 5) - ; GFX1200-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.4, addrspace 5) - ; GFX1200-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5) - ; GFX1200-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX1200-NEXT: $vgpr63 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) + ; GFX1200-NEXT: $vgpr62 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX1200-NEXT: $vgpr61 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX1200-NEXT: $vgpr60 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX1200-NEXT: $vgpr59 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX1200-NEXT: $vgpr58 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX1200-NEXT: $vgpr57 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX1200-NEXT: $vgpr56 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX1200-NEXT: $vgpr47 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX1200-NEXT: $vgpr46 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX1200-NEXT: $vgpr45 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX1200-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX1200-NEXT: $vgpr43 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX1200-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX1200-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX1200-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX1200-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc, implicit killed $vcc_lo S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 @@ -1068,4 +1068,3 @@ body: | S_ENDPGM 0, implicit $sgpr4, implicit $scc, implicit killed $vcc ... - diff --git a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir index ade7b4266e9e6..79486d56c55ca 100644 --- a/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir +++ b/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir @@ -1053,71 +1053,71 @@ body: | ; GFX7-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX7: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX7-NEXT: {{ $}} - ; GFX7-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX7-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX7-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX7-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX7-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; GFX7-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $vgpr0, 0, implicit $exec - ; GFX7-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX7-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX7-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; GFX7-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX8-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX8: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX8-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; GFX8-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $vgpr0, 0, implicit $exec - ; GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX8-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; GFX8-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX900-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX900: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX900-NEXT: {{ $}} - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX900-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX900-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; GFX900-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $vgpr0, 0, implicit $exec - ; GFX900-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX900-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX900-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; GFX900-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX90A-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX90A: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX90A-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX90A-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; GFX90A-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $vgpr0, 0, implicit $exec - ; GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX90A-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; GFX90A-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX10-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX10: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX10-NEXT: {{ $}} - ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX10-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX10-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 128, killed $vgpr0, 0, implicit $exec - ; GFX10-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX10-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX10-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; GFX10-NEXT: SI_RETURN implicit $vgpr0 ; ; GFX942-LABEL: name: v_add_co_u32_e64__fi_literal_offset__sgpr__scavenge_spill_required ; GFX942: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; GFX942-NEXT: {{ $}} - ; GFX942-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX942-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX942-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 $sgpr8, killed $vgpr1, 0, implicit $exec ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 128, implicit $exec ; GFX942-NEXT: renamable $vgpr0, renamable $vcc = V_ADD_CO_U32_e64 killed $vgpr1, killed $vgpr0, 0, implicit $exec - ; GFX942-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX942-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX942-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; GFX942-NEXT: SI_RETURN implicit $vgpr0 ; @@ -1160,22 +1160,22 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__sgpr__scavenge_spill_required ; MUBUFW64: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; MUBUFW64-NEXT: {{ $}} - ; MUBUFW64-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUFW64-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr8, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec - ; MUBUFW64-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUFW64-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUFW64-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; ; FLATSCRW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__sgpr__scavenge_spill_required ; FLATSCRW64: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; FLATSCRW64-NEXT: {{ $}} - ; FLATSCRW64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; FLATSCRW64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; FLATSCRW64-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr8, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; FLATSCRW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec - ; FLATSCRW64-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; FLATSCRW64-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 132, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; FLATSCRW64-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; FLATSCRW64-NEXT: SI_RETURN implicit $vgpr0 renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr8, %stack.1, implicit-def dead $vcc, implicit $exec @@ -1202,11 +1202,11 @@ body: | ; MUBUFW64-LABEL: name: v_add_co_u32_e32__fi_literal_offset__vgpr__scavenge_spill_required ; MUBUFW64: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253, $vgpr254, $vgpr255, $sgpr8 ; MUBUFW64-NEXT: {{ $}} - ; MUBUFW64-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUFW64-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUFW64-NEXT: renamable $vgpr1 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 $vgpr8, killed $vgpr1, implicit-def dead $vcc, implicit $exec ; MUBUFW64-NEXT: renamable $vgpr0 = V_ADD_CO_U32_e32 128, killed $vgpr0, implicit-def dead $vcc, implicit $exec - ; MUBUFW64-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUFW64-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUFW64-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, implicit $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, implicit $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, implicit $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, implicit $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, implicit $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, implicit $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, implicit $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, implicit $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, implicit $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, implicit $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, implicit $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, implicit $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, implicit $vgpr248_vgpr249_vgpr250_vgpr251, implicit $vgpr252_vgpr253, implicit $vgpr254, implicit $vgpr255 ; MUBUFW64-NEXT: SI_RETURN implicit $vgpr0 ; diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll index edae2c393e5f0..a36be284a4bc3 100644 --- a/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll +++ b/llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll @@ -216,19 +216,34 @@ define amdgpu_kernel void @extract_vector_elt_v3f16(ptr addrspace(1) %out, <3 x ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:2 ; VI-NEXT: s_endpgm ; -; GFX11-LABEL: extract_vector_elt_v3f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-NEXT: s_mov_b32 s7, 0x31016000 -; GFX11-NEXT: s_mov_b32 s6, -1 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2 -; GFX11-NEXT: s_mov_b32 s4, s0 -; GFX11-NEXT: s_mov_b32 s5, s1 -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0 -; GFX11-NEXT: buffer_store_b16 v1, off, s[4:7], 0 offset:2 -; GFX11-NEXT: s_endpgm +; GFX11-TRUE16-LABEL: extract_vector_elt_v3f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 offset:2 +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: extract_vector_elt_v3f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-FAKE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX11-FAKE16-NEXT: s_mov_b32 s6, -1 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s4, s0 +; GFX11-FAKE16-NEXT: s_mov_b32 s5, s1 +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 +; GFX11-FAKE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 offset:2 +; GFX11-FAKE16-NEXT: s_endpgm %p0 = extractelement <3 x half> %foo, i32 0 %p1 = extractelement <3 x half> %foo, i32 2 %out1 = getelementptr half, ptr addrspace(1) %out, i32 1 @@ -269,20 +284,35 @@ define amdgpu_kernel void @dynamic_extract_vector_elt_v3f16(ptr addrspace(1) %ou ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 ; VI-NEXT: s_endpgm ; -; GFX11-LABEL: dynamic_extract_vector_elt_v3f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x34 -; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshl_b32 s4, s6, 4 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s4 -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: s_mov_b32 s2, -1 -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 -; GFX11-NEXT: s_endpgm +; GFX11-TRUE16-LABEL: dynamic_extract_vector_elt_v3f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x34 +; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s6, 4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-TRUE16-NEXT: s_lshr_b64 s[2:3], s[2:3], s4 +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: dynamic_extract_vector_elt_v3f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x34 +; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s6, 4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-FAKE16-NEXT: s_lshr_b64 s[2:3], s[2:3], s4 +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 +; GFX11-FAKE16-NEXT: s_endpgm %p0 = extractelement <3 x half> %foo, i32 %idx %out1 = getelementptr half, ptr addrspace(1) %out, i32 1 store half %p0, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/fabs-known-signbit-combine-fast-fdiv-lowering.ll b/llvm/test/CodeGen/AMDGPU/fabs-known-signbit-combine-fast-fdiv-lowering.ll index 750f390e79110..f6886d7499d73 100644 --- a/llvm/test/CodeGen/AMDGPU/fabs-known-signbit-combine-fast-fdiv-lowering.ll +++ b/llvm/test/CodeGen/AMDGPU/fabs-known-signbit-combine-fast-fdiv-lowering.ll @@ -314,6 +314,6 @@ declare float @llvm.maximumnum.f32(float, float) #0 declare float @llvm.minimumnum.f32(float, float) #0 attributes #0 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } -attributes #1 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { denormal_fpenv(float: preservesign) } !0 = !{float 2.500000e+00} diff --git a/llvm/test/CodeGen/AMDGPU/fadd.f16.ll b/llvm/test/CodeGen/AMDGPU/fadd.f16.ll index 0b7533e2ecced..e8c96787db66c 100644 --- a/llvm/test/CodeGen/AMDGPU/fadd.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fadd.f16.ll @@ -72,11 +72,11 @@ define amdgpu_kernel void @fadd_f16( ; GFX11-SDAG-NEXT: s_mov_b32 s1, s3 ; GFX11-SDAG-NEXT: s_mov_b32 s2, s10 ; GFX11-SDAG-NEXT: s_mov_b32 s3, s11 -; GFX11-SDAG-NEXT: buffer_load_u16 v0, off, s[0:3], 0 glc dlc +; GFX11-SDAG-NEXT: buffer_load_d16_b16 v0, off, s[0:3], 0 glc dlc ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) -; GFX11-SDAG-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-SDAG-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) -; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l +; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h ; GFX11-SDAG-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-SDAG-NEXT: s_endpgm ; @@ -92,11 +92,11 @@ define amdgpu_kernel void @fadd_f16( ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: s_mov_b64 s[8:9], s[2:3] ; GFX11-GISEL-NEXT: s_mov_b64 s[2:3], s[10:11] -; GFX11-GISEL-NEXT: buffer_load_u16 v0, off, s[8:11], 0 glc dlc +; GFX11-GISEL-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 glc dlc ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX11-GISEL-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-GISEL-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) -; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l +; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h ; GFX11-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-NEXT: s_endpgm ; @@ -232,7 +232,7 @@ define amdgpu_kernel void @fadd_f16_imm_a( ; GFX11-SDAG-NEXT: s_mov_b32 s1, s3 ; GFX11-SDAG-NEXT: s_mov_b32 s2, s6 ; GFX11-SDAG-NEXT: s_mov_b32 s3, s7 -; GFX11-SDAG-NEXT: buffer_load_u16 v0, off, s[0:3], 0 +; GFX11-SDAG-NEXT: buffer_load_d16_b16 v0, off, s[0:3], 0 ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l ; GFX11-SDAG-NEXT: buffer_store_b16 v0, off, s[4:7], 0 @@ -246,7 +246,7 @@ define amdgpu_kernel void @fadd_f16_imm_a( ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3] ; GFX11-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7] -; GFX11-GISEL-NEXT: buffer_load_u16 v0, off, s[4:7], 0 +; GFX11-GISEL-NEXT: buffer_load_d16_b16 v0, off, s[4:7], 0 ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l ; GFX11-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0 @@ -364,7 +364,7 @@ define amdgpu_kernel void @fadd_f16_imm_b( ; GFX11-SDAG-NEXT: s_mov_b32 s1, s3 ; GFX11-SDAG-NEXT: s_mov_b32 s2, s6 ; GFX11-SDAG-NEXT: s_mov_b32 s3, s7 -; GFX11-SDAG-NEXT: buffer_load_u16 v0, off, s[0:3], 0 +; GFX11-SDAG-NEXT: buffer_load_d16_b16 v0, off, s[0:3], 0 ; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX11-SDAG-NEXT: v_add_f16_e32 v0.l, 2.0, v0.l ; GFX11-SDAG-NEXT: buffer_store_b16 v0, off, s[4:7], 0 @@ -378,7 +378,7 @@ define amdgpu_kernel void @fadd_f16_imm_b( ; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3] ; GFX11-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7] -; GFX11-GISEL-NEXT: buffer_load_u16 v0, off, s[4:7], 0 +; GFX11-GISEL-NEXT: buffer_load_d16_b16 v0, off, s[4:7], 0 ; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX11-GISEL-NEXT: v_add_f16_e32 v0.l, 2.0, v0.l ; GFX11-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0 diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll index a62673679eb8e..a87570ef5d848 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll @@ -948,4 +948,4 @@ declare float @llvm.amdgcn.exp2.f32(float) #0 attributes #0 = { nounwind readnone } attributes #1 = { "no-nans-fp-math"="true" } -attributes #2 = { "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" } +attributes #2 = { denormal_fpenv(preservesign, float: ieee) } diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll index b23645839944e..933d427243d76 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll @@ -1389,6 +1389,6 @@ define <64 x bfloat> @v_test_canonicalize_var_v64bf16(<64 x bfloat> %val) #1 { } attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #2 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #3 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } +attributes #2 = { nounwind denormal_fpenv(preservesign) } +attributes #3 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll index 805b1421f94d0..06212cf96cfa6 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll @@ -4040,6 +4040,6 @@ define <64 x half> @v_test_canonicalize_var_v64f16(<64 x half> %val) #1 { } attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #2 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #3 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } +attributes #2 = { nounwind denormal_fpenv(preservesign) } +attributes #3 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll index 78ea7fde4bf28..53b6ceb45531e 100644 --- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll +++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.ll @@ -5519,13 +5519,13 @@ define <4 x double> @v_test_canonicalize_v4f64(<4 x double> %arg) #1 { } attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #2 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #3 = { nounwind "denormal-fp-math"="ieee,ieee" } -attributes #4 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #5 = { nounwind "denormal-fp-math-f32"="dynamic,dynamic" } -attributes #6 = { nounwind "denormal-fp-math-f32"="dynamic,ieee" } -attributes #7 = { nounwind "denormal-fp-math-f32"="ieee,dynamic" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } +attributes #2 = { nounwind denormal_fpenv(preservesign) } +attributes #3 = { nounwind denormal_fpenv(ieee|ieee) } +attributes #4 = { nounwind denormal_fpenv(preservesign) } +attributes #5 = { nounwind denormal_fpenv(float: dynamic|dynamic) } +attributes #6 = { nounwind denormal_fpenv(float: dynamic|ieee) } +attributes #7 = { nounwind denormal_fpenv(float: ieee|dynamic) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX11-GISEL-FAKE16: {{.*}} ; GFX11-GISEL-TRUE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll index 5d3f69c84b902..0a6619810ad0e 100644 --- a/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fcmp.f16.ll @@ -71,13 +71,13 @@ define amdgpu_kernel void @fcmp_f16_lt( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -121,13 +121,13 @@ define amdgpu_kernel void @fcmp_f16_lt( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -233,13 +233,13 @@ define amdgpu_kernel void @fcmp_f16_lt_abs( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e64 s2, |v0.l|, |v1.l| +; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e64 s2, |v0.l|, |v0.h| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, s2 ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 @@ -285,9 +285,9 @@ define amdgpu_kernel void @fcmp_f16_lt_abs( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 @@ -405,13 +405,13 @@ define amdgpu_kernel void @fcmp_f16_eq( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -455,13 +455,13 @@ define amdgpu_kernel void @fcmp_f16_eq( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_eq_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -567,13 +567,13 @@ define amdgpu_kernel void @fcmp_f16_le( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -617,13 +617,13 @@ define amdgpu_kernel void @fcmp_f16_le( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_le_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -729,13 +729,13 @@ define amdgpu_kernel void @fcmp_f16_gt( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -779,13 +779,13 @@ define amdgpu_kernel void @fcmp_f16_gt( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -891,13 +891,13 @@ define amdgpu_kernel void @fcmp_f16_lg( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -941,13 +941,13 @@ define amdgpu_kernel void @fcmp_f16_lg( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -1053,13 +1053,13 @@ define amdgpu_kernel void @fcmp_f16_ge( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -1103,13 +1103,13 @@ define amdgpu_kernel void @fcmp_f16_ge( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -1215,13 +1215,13 @@ define amdgpu_kernel void @fcmp_f16_o( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -1265,13 +1265,13 @@ define amdgpu_kernel void @fcmp_f16_o( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -1377,13 +1377,13 @@ define amdgpu_kernel void @fcmp_f16_u( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -1427,13 +1427,13 @@ define amdgpu_kernel void @fcmp_f16_u( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_u_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -1539,13 +1539,13 @@ define amdgpu_kernel void @fcmp_f16_nge( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -1589,13 +1589,13 @@ define amdgpu_kernel void @fcmp_f16_nge( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_nge_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -1701,13 +1701,13 @@ define amdgpu_kernel void @fcmp_f16_nlg( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -1751,13 +1751,13 @@ define amdgpu_kernel void @fcmp_f16_nlg( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_nlg_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -1863,13 +1863,13 @@ define amdgpu_kernel void @fcmp_f16_ngt( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -1913,13 +1913,13 @@ define amdgpu_kernel void @fcmp_f16_ngt( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -2025,13 +2025,13 @@ define amdgpu_kernel void @fcmp_f16_nle( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -2075,13 +2075,13 @@ define amdgpu_kernel void @fcmp_f16_nle( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_nle_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -2187,13 +2187,13 @@ define amdgpu_kernel void @fcmp_f16_neq( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -2237,13 +2237,13 @@ define amdgpu_kernel void @fcmp_f16_neq( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_neq_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm @@ -2349,13 +2349,13 @@ define amdgpu_kernel void @fcmp_f16_nlt( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v0.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -2399,13 +2399,13 @@ define amdgpu_kernel void @fcmp_f16_nlt( ; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l +; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v0.h ; GFX12-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo ; GFX12-TRUE16-NEXT: buffer_store_b32 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll b/llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll index 2d6ae31f8e585..5874c72df41ab 100644 --- a/llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll +++ b/llvm/test/CodeGen/AMDGPU/fdiv-nofpexcept.ll @@ -66,4 +66,4 @@ entry: ret float %fdiv } -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll index fd5c47d36a752..3f82414ac1eef 100644 --- a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll @@ -89,10 +89,9 @@ define amdgpu_kernel void @v_fdiv_f16( ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: global_load_ushort v2, v0, s[6:7] glc ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cvt_f32_f16_e32 v4, v1 ; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX9-NEXT: v_rcp_f32_e32 v3, v3 -; GFX9-NEXT: v_mul_f32_e32 v4, v4, v3 +; GFX9-NEXT: v_mad_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] ; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] ; GFX9-NEXT: v_mac_f32_e32 v4, v5, v3 ; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] @@ -115,16 +114,16 @@ define amdgpu_kernel void @v_fdiv_f16( ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cvt_f32_f16_e32 v5, v1 +; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v1 ; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX10-NEXT: v_rcp_f32_e32 v4, v3 -; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4 -; GFX10-NEXT: v_mad_f32 v7, -v3, v6, v5 -; GFX10-NEXT: v_mac_f32_e32 v6, v7, v4 -; GFX10-NEXT: v_mad_f32 v3, -v3, v6, v5 +; GFX10-NEXT: v_fma_mix_f32 v5, v1, v4, neg(0) op_sel_hi:[1,0,0] +; GFX10-NEXT: v_mad_f32 v7, -v3, v5, v6 +; GFX10-NEXT: v_mac_f32_e32 v5, v7, v4 +; GFX10-NEXT: v_mad_f32 v3, -v3, v5, v6 ; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX10-NEXT: v_add_f32_e32 v3, v3, v6 +; GFX10-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-NEXT: v_div_fixup_f16 v1, v3, v2, v1 ; GFX10-NEXT: global_store_short v0, v1, s[0:1] @@ -143,12 +142,11 @@ define amdgpu_kernel void @v_fdiv_f16( ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v2.l ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v0, v0 ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v4, v0 +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0] ; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0 @@ -177,12 +175,11 @@ define amdgpu_kernel void @v_fdiv_f16( ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] glc dlc ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v1 ; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v3, v3 ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-FAKE16-NEXT: v_mul_f32_e32 v4, v4, v3 +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] ; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3 diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.ll b/llvm/test/CodeGen/AMDGPU/fdiv.ll index c510c40c8536c..0f71cc48a57cf 100644 --- a/llvm/test/CodeGen/AMDGPU/fdiv.ll +++ b/llvm/test/CodeGen/AMDGPU/fdiv.ll @@ -8044,8 +8044,8 @@ define float @v_fdiv_f32_daz_25ulp_nodenorm_y(float %x, float nofpclass(sub) %y) ret float %div } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="ieee,ieee" } -attributes #2 = { "denormal-fp-math-f32"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(float: preservesign) } +attributes #1 = { denormal_fpenv(float: ieee|ieee) } +attributes #2 = { denormal_fpenv(float: dynamic|dynamic) } !0 = !{float 2.500000e+00} diff --git a/llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll b/llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll index 7e9f21b94bea0..a526b1ec16502 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll +++ b/llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll @@ -54,7 +54,6 @@ define amdgpu_ps void @global_load_lds_dword_saddr(ptr addrspace(1) inreg nocapt ; GFX90A-NEXT: s_mov_b32 m0, s4 ; GFX90A-NEXT: s_nop 0 ; GFX90A-NEXT: global_load_dword v0, s[2:3] offset:32 slc lds -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1] ; GFX90A-NEXT: s_endpgm main_body: diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll index 262b6c53fa2f8..91b0f2e55aade 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll @@ -32,6 +32,7 @@ define float @flat_agent_atomic_fadd_ret_f32__amdgpu_no_fine_grained_memory__amd ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -208,6 +209,7 @@ define float @flat_agent_atomic_fadd_ret_f32__offset12b_pos__amdgpu_no_fine_grai ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -397,6 +399,7 @@ define float @flat_agent_atomic_fadd_ret_f32__offset12b_neg__amdgpu_no_fine_grai ; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -590,6 +593,7 @@ define void @flat_agent_atomic_fadd_noret_f32__amdgpu_no_fine_grained_memory__am ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -796,6 +800,7 @@ define void @flat_agent_atomic_fadd_noret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1016,6 +1021,7 @@ define void @flat_agent_atomic_fadd_noret_f32__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1237,6 +1243,7 @@ define float @flat_system_atomic_fadd_ret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1304,6 +1311,7 @@ define float @flat_system_atomic_fadd_ret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX90A-NEXT: s_cbranch_execz .LBB6_5 ; GFX90A-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v0, v[4:5], v2, off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1426,6 +1434,7 @@ define void @flat_system_atomic_fadd_noret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1492,6 +1501,7 @@ define void @flat_system_atomic_fadd_noret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: s_cbranch_execz .LBB7_5 ; GFX90A-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1645,6 +1655,7 @@ define void @flat_agent_atomic_fadd_noret_f32_maybe_remote(ptr %ptr, float %val) ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1809,6 +1820,7 @@ define void @flat_agent_atomic_fadd_noret_f32___amdgpu_no_fine_grained_memory(pt ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1960,6 +1972,7 @@ define void @flat_agent_atomic_fadd_noret_f32___amdgpu_no_fine_grained_memory__a ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2177,6 +2190,7 @@ define void @flat_agent_atomic_fadd_noret_f32_amdgpu_ignore_denormal_mode(ptr %p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2345,6 +2359,7 @@ define float @flat_agent_atomic_fadd_ret_f32__ftz__amdgpu_no_fine_grained_memory ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2521,6 +2536,7 @@ define float @flat_agent_atomic_fadd_ret_f32__offset12b_pos__ftz__amdgpu_no_fine ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2710,6 +2726,7 @@ define float @flat_agent_atomic_fadd_ret_f32__offset12b_neg__ftz__amdgpu_no_fine ; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2903,6 +2920,7 @@ define void @flat_agent_atomic_fadd_noret_f32__ftz__amdgpu_no_fine_grained_memor ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3109,6 +3127,7 @@ define void @flat_agent_atomic_fadd_noret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3329,6 +3348,7 @@ define void @flat_agent_atomic_fadd_noret_f32__offset12b_neg__ftz__amdgpu_no_fin ; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3550,6 +3570,7 @@ define float @flat_system_atomic_fadd_ret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -3617,6 +3638,7 @@ define float @flat_system_atomic_fadd_ret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX90A-NEXT: s_cbranch_execz .LBB18_5 ; GFX90A-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v0, v[4:5], v2, off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3739,6 +3761,7 @@ define void @flat_system_atomic_fadd_noret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -3805,6 +3828,7 @@ define void @flat_system_atomic_fadd_noret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX90A-NEXT: s_cbranch_execz .LBB19_5 ; GFX90A-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3959,6 +3983,7 @@ define float @flat_agent_atomic_fadd_ret_f32__ieee__amdgpu_no_fine_grained_memor ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -4026,6 +4051,7 @@ define float @flat_agent_atomic_fadd_ret_f32__ieee__amdgpu_no_fine_grained_memor ; GFX90A-NEXT: s_cbranch_execz .LBB20_5 ; GFX90A-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v0, v[4:5], v2, off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -4148,6 +4174,7 @@ define void @flat_agent_atomic_fadd_noret_f32__ieee__amdgpu_no_fine_grained_memo ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -4214,6 +4241,7 @@ define void @flat_agent_atomic_fadd_noret_f32__ieee__amdgpu_no_fine_grained_memo ; GFX90A-NEXT: s_cbranch_execz .LBB21_5 ; GFX90A-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -4367,6 +4395,7 @@ define float @flat_agent_atomic_fadd_ret_f32__amdgpu_no_remote_memory__amdgpu_ig ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4531,6 +4560,7 @@ define void @flat_agent_atomic_fadd_noret_f32__amdgpu_no_remote_memory__amdgpu_i ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4688,6 +4718,7 @@ define float @flat_agent_atomic_fadd_ret_f32__amdgpu_no_remote_memory(ptr %ptr, ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4852,6 +4883,7 @@ define void @flat_agent_atomic_fadd_noret_f32__amdgpu_no_remote_memory(ptr %ptr, ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5009,6 +5041,7 @@ define float @flat_agent_atomic_fadd_ret_f32__amdgpu_no_fine_grained_memory_amdg ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5185,6 +5218,7 @@ define void @flat_agent_atomic_fadd_noret_f32__amdgpu_no_fine_grained_memory_amd ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5391,6 +5425,7 @@ define float @flat_agent_atomic_fadd_ret_f32__amdgpu_no_fine_grained_memory_amdg ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5539,6 +5574,7 @@ define void @flat_agent_atomic_fadd_noret_f32__amdgpu_no_fine_grained_memory_amd ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5752,6 +5788,7 @@ define double @flat_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: s_cbranch_execz .LBB30_5 ; GFX942-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[4:5], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6193,6 +6230,7 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: s_cbranch_execz .LBB31_5 ; GFX942-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[4:5], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6654,6 +6692,7 @@ define double @flat_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: s_cbranch_execz .LBB32_5 ; GFX942-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[4:5], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7105,6 +7144,7 @@ define void @flat_agent_atomic_fadd_noret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: s_cbranch_execz .LBB33_5 ; GFX942-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[2:3], off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7539,6 +7579,7 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: s_cbranch_execz .LBB34_5 ; GFX942-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[2:3], off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7988,6 +8029,7 @@ define void @flat_agent_atomic_fadd_noret_f64__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: s_cbranch_execz .LBB35_5 ; GFX942-NEXT: ; %bb.4: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[2:3], off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8462,6 +8504,7 @@ define half @flat_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr % ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8834,6 +8877,7 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grain ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9215,6 +9259,7 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_grain ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9588,6 +9633,7 @@ define void @flat_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9948,6 +9994,7 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10317,6 +10364,7 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10651,6 +10699,7 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b__align4_pos__amdgpu_no_ ; GFX942-NEXT: v_add_f16_e32 v3, v5, v2 ; GFX942-NEXT: v_and_or_b32 v4, v5, s2, v3 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10925,6 +10974,7 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__align4__amdgpu_no_fi ; GFX942-NEXT: v_add_f16_e32 v3, v5, v2 ; GFX942-NEXT: v_and_or_b32 v4, v5, s2, v3 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11241,6 +11291,7 @@ define half @flat_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grai ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -11390,6 +11441,7 @@ define half @flat_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grai ; GFX90A-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX90A-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -11622,6 +11674,7 @@ define void @flat_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -11766,6 +11819,7 @@ define void @flat_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX90A-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -12026,6 +12080,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12482,6 +12537,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12948,6 +13004,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -13409,6 +13466,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -13861,6 +13919,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14282,6 +14341,7 @@ define bfloat @flat_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_no ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14649,6 +14709,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_no ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15037,6 +15098,7 @@ define void @flat_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15485,6 +15547,7 @@ define bfloat @flat_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15670,6 +15733,7 @@ define bfloat @flat_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15950,6 +16014,7 @@ define void @flat_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -16129,6 +16194,7 @@ define void @flat_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -16284,6 +16350,7 @@ define <2 x half> @flat_agent_atomic_fadd_ret_v2f16__amdgpu_no_fine_grained_memo ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16466,6 +16533,7 @@ define <2 x half> @flat_agent_atomic_fadd_ret_v2f16__offset12b_pos__amdgpu_no_fi ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v0, v[0:1], v2 offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16656,6 +16724,7 @@ define <2 x half> @flat_agent_atomic_fadd_ret_v2f16__offset12b_neg__amdgpu_no_fi ; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16853,6 +16922,7 @@ define void @flat_agent_atomic_fadd_noret_v2f16__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17026,6 +17096,7 @@ define void @flat_agent_atomic_fadd_noret_v2f16__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v[0:1], v2 offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17209,6 +17280,7 @@ define void @flat_agent_atomic_fadd_noret_v2f16__offset12b_neg__amdgpu_no_fine_g ; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17403,6 +17475,7 @@ define <2 x half> @flat_system_atomic_fadd_ret_v2f16__offset12b_pos__amdgpu_no_f ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v0, v[0:1], v2 offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -17469,6 +17542,7 @@ define <2 x half> @flat_system_atomic_fadd_ret_v2f16__offset12b_pos__amdgpu_no_f ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_pk_add_f16 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -17593,6 +17667,7 @@ define void @flat_system_atomic_fadd_noret_v2f16__offset12b_pos__amdgpu_no_fine_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v[0:1], v2 offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -17657,6 +17732,7 @@ define void @flat_system_atomic_fadd_noret_v2f16__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_pk_add_f16 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -17775,6 +17851,7 @@ define <2 x half> @flat_agent_atomic_fadd_ret_v2f16__amdgpu_no_remote_memory(ptr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17957,6 +18034,7 @@ define void @flat_agent_atomic_fadd_noret_v2f16__amdgpu_no_remote_memory(ptr %pt ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18130,6 +18208,7 @@ define <2 x half> @flat_agent_atomic_fadd_ret_v2f16__amdgpu_no_fine_grained_memo ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18312,6 +18391,7 @@ define void @flat_agent_atomic_fadd_noret_v2f16__amdgpu_no_fine_grained_memory__ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_f16 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18489,6 +18569,7 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18815,6 +18896,7 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_no ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v0, v[0:1], v2 offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -19149,6 +19231,7 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_no ; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -19491,6 +19574,7 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory( ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -19805,6 +19889,7 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v[0:1], v2 offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -20129,6 +20214,7 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: s_nop 1 ; GFX942-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -20467,6 +20553,7 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v0, v[0:1], v2 offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -20637,6 +20724,7 @@ define <2 x bfloat> @flat_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_n ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -20801,6 +20889,7 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v[0:1], v2 offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -20967,6 +21056,7 @@ define void @flat_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -21124,6 +21214,7 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memory( ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -21450,6 +21541,7 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr %p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -21764,6 +21856,7 @@ define <2 x bfloat> @flat_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained_m ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v0, v[0:1], v2 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -22090,6 +22183,7 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_pk_add_bf16 v[0:1], v2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -22387,6 +22481,6 @@ define void @flat_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memory_ } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll index 3919ba4e2b1c2..ddc889f8075d5 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll @@ -40,6 +40,7 @@ define float @flat_agent_atomic_fmax_ret_f32__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -182,6 +183,7 @@ define float @flat_agent_atomic_fmax_ret_f32__offset12b_pos__amdgpu_no_fine_grai ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -336,6 +338,7 @@ define float @flat_agent_atomic_fmax_ret_f32__offset12b_neg__amdgpu_no_fine_grai ; GFX942-NEXT: v_max_f32_e32 v0, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -494,6 +497,7 @@ define void @flat_agent_atomic_fmax_noret_f32__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -634,6 +638,7 @@ define void @flat_agent_atomic_fmax_noret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -787,6 +792,7 @@ define void @flat_agent_atomic_fmax_noret_f32__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -948,6 +954,7 @@ define float @flat_system_atomic_fmax_ret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -995,6 +1002,7 @@ define float @flat_system_atomic_fmax_ret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1099,6 +1107,7 @@ define void @flat_system_atomic_fmax_noret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1147,6 +1156,7 @@ define void @flat_system_atomic_fmax_noret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1248,6 +1258,7 @@ define float @flat_agent_atomic_fmax_ret_f32__amdgpu_no_remote_memory(ptr %ptr, ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1440,6 +1451,7 @@ define float @flat_agent_atomic_fmax_ret_f32__amdgpu_no_fine_grained_memory__amd ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1586,6 +1598,7 @@ define float @flat_agent_atomic_fmax_ret_f32__ftz__amdgpu_no_fine_grained_memory ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1728,6 +1741,7 @@ define float @flat_agent_atomic_fmax_ret_f32__offset12b_pos__ftz__amdgpu_no_fine ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1882,6 +1896,7 @@ define float @flat_agent_atomic_fmax_ret_f32__offset12b_neg__ftz__amdgpu_no_fine ; GFX942-NEXT: v_max_f32_e32 v0, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v0, v1 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2040,6 +2055,7 @@ define void @flat_agent_atomic_fmax_noret_f32__ftz__amdgpu_no_fine_grained_memor ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2180,6 +2196,7 @@ define void @flat_agent_atomic_fmax_noret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2333,6 +2350,7 @@ define void @flat_agent_atomic_fmax_noret_f32__offset12b_neg__ftz__amdgpu_no_fin ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2494,6 +2512,7 @@ define float @flat_system_atomic_fmax_ret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2541,6 +2560,7 @@ define float @flat_system_atomic_fmax_ret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2645,6 +2665,7 @@ define void @flat_system_atomic_fmax_noret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2693,6 +2714,7 @@ define void @flat_system_atomic_fmax_noret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2851,6 +2873,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB18_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3247,6 +3270,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB19_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3659,6 +3683,7 @@ define double @flat_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB20_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4063,6 +4088,7 @@ define void @flat_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB21_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4453,6 +4479,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB22_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4858,6 +4885,7 @@ define void @flat_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB23_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5257,6 +5285,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr %ptr, ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB24_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5680,6 +5709,7 @@ define double @flat_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__am ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB25_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_max_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6109,6 +6139,7 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr % ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6504,6 +6535,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6910,6 +6942,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7305,6 +7338,7 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7688,6 +7722,7 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8082,6 +8117,7 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8441,6 +8477,7 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_fi ; GFX942-NEXT: v_max_f16_e32 v2, v2, v4 ; GFX942-NEXT: v_and_or_b32 v2, v3, s2, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8738,6 +8775,7 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_no_ ; GFX942-NEXT: v_max_f16_e32 v2, v2, v4 ; GFX942-NEXT: v_and_or_b32 v2, v3, s2, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9071,6 +9109,7 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -9231,6 +9270,7 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai ; GFX90A-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -9477,6 +9517,7 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -9632,6 +9673,7 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -9896,6 +9938,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10353,6 +10396,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10820,6 +10864,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11276,6 +11321,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11719,6 +11765,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12172,6 +12219,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12594,6 +12642,7 @@ define bfloat @flat_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_no ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12962,6 +13011,7 @@ define void @flat_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_no ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -13363,6 +13413,7 @@ define bfloat @flat_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13548,6 +13599,7 @@ define bfloat @flat_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13829,6 +13881,7 @@ define void @flat_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -14008,6 +14061,7 @@ define void @flat_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -14192,6 +14246,7 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__amdgpu_no_fine_grained_memo ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14422,6 +14477,7 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_fi ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14663,6 +14719,7 @@ define <2 x half> @flat_agent_atomic_fmax_ret_v2f16__offset12b_neg__amdgpu_no_fi ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v0, v1 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14906,6 +14963,7 @@ define void @flat_agent_atomic_fmax_noret_v2f16__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15126,6 +15184,7 @@ define void @flat_agent_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15359,6 +15418,7 @@ define void @flat_agent_atomic_fmax_noret_v2f16__offset12b_neg__amdgpu_no_fine_g ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15601,6 +15661,7 @@ define <2 x half> @flat_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_f ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15681,6 +15742,7 @@ define <2 x half> @flat_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_f ; GFX90A-NEXT: v_pk_max_f16 v2, v3, v3 ; GFX90A-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15838,6 +15900,7 @@ define void @flat_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15916,6 +15979,7 @@ define void @flat_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: v_pk_max_f16 v2, v3, v3 ; GFX90A-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -16159,6 +16223,7 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained_m ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16608,6 +16673,7 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_no ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17068,6 +17134,7 @@ define <2 x bfloat> @flat_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_no ; GFX942-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v2, v0, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17528,6 +17595,7 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memory( ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17960,6 +18028,7 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18405,6 +18474,7 @@ define void @flat_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18866,6 +18936,7 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19044,6 +19115,7 @@ define <2 x bfloat> @flat_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_n ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19320,6 +19392,7 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19493,6 +19566,7 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19633,6 +19707,6 @@ define void @flat_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fine } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll index 858ff79ade52f..1b3fd173ab7b5 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll @@ -40,6 +40,7 @@ define float @flat_agent_atomic_fmin_ret_f32__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -182,6 +183,7 @@ define float @flat_agent_atomic_fmin_ret_f32__offset12b_pos__amdgpu_no_fine_grai ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -336,6 +338,7 @@ define float @flat_agent_atomic_fmin_ret_f32__offset12b_neg__amdgpu_no_fine_grai ; GFX942-NEXT: v_max_f32_e32 v0, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -494,6 +497,7 @@ define void @flat_agent_atomic_fmin_noret_f32__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -634,6 +638,7 @@ define void @flat_agent_atomic_fmin_noret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -787,6 +792,7 @@ define void @flat_agent_atomic_fmin_noret_f32__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -948,6 +954,7 @@ define float @flat_system_atomic_fmin_ret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -995,6 +1002,7 @@ define float @flat_system_atomic_fmin_ret_f32__offset12b_pos__amdgpu_no_fine_gra ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1099,6 +1107,7 @@ define void @flat_system_atomic_fmin_noret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1147,6 +1156,7 @@ define void @flat_system_atomic_fmin_noret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1248,6 +1258,7 @@ define float @flat_agent_atomic_fmin_ret_f32__amdgpu_no_remote_memory(ptr %ptr, ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1440,6 +1451,7 @@ define float @flat_agent_atomic_fmin_ret_f32__amdgpu_no_fine_grained_memory__amd ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1586,6 +1598,7 @@ define float @flat_agent_atomic_fmin_ret_f32__ftz__amdgpu_no_fine_grained_memory ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1728,6 +1741,7 @@ define float @flat_agent_atomic_fmin_ret_f32__offset12b_pos__ftz__amdgpu_no_fine ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1882,6 +1896,7 @@ define float @flat_agent_atomic_fmin_ret_f32__offset12b_neg__ftz__amdgpu_no_fine ; GFX942-NEXT: v_max_f32_e32 v0, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v0, v1 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2040,6 +2055,7 @@ define void @flat_agent_atomic_fmin_noret_f32__ftz__amdgpu_no_fine_grained_memor ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2180,6 +2196,7 @@ define void @flat_agent_atomic_fmin_noret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2333,6 +2350,7 @@ define void @flat_agent_atomic_fmin_noret_f32__offset12b_neg__ftz__amdgpu_no_fin ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2494,6 +2512,7 @@ define float @flat_system_atomic_fmin_ret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2541,6 +2560,7 @@ define float @flat_system_atomic_fmin_ret_f32__offset12b_pos__ftz__amdgpu_no_fin ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2645,6 +2665,7 @@ define void @flat_system_atomic_fmin_noret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2693,6 +2714,7 @@ define void @flat_system_atomic_fmin_noret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2851,6 +2873,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB18_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3247,6 +3270,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB19_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3659,6 +3683,7 @@ define double @flat_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB20_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4063,6 +4088,7 @@ define void @flat_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB21_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4453,6 +4479,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB22_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4858,6 +4885,7 @@ define void @flat_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB23_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[2:3] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5257,6 +5285,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr %ptr, ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB24_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5680,6 +5709,7 @@ define double @flat_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__am ; GFX942-NEXT: s_setpc_b64 s[30:31] ; GFX942-NEXT: .LBB25_3: ; %atomicrmw.global ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_min_f64 v[0:1], v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6109,6 +6139,7 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr % ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6504,6 +6535,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6910,6 +6942,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7305,6 +7338,7 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7688,6 +7722,7 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8082,6 +8117,7 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8441,6 +8477,7 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_fi ; GFX942-NEXT: v_min_f16_e32 v2, v2, v4 ; GFX942-NEXT: v_and_or_b32 v2, v3, s2, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8738,6 +8775,7 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_no_ ; GFX942-NEXT: v_min_f16_e32 v2, v2, v4 ; GFX942-NEXT: v_and_or_b32 v2, v3, s2, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9071,6 +9109,7 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -9231,6 +9270,7 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai ; GFX90A-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -9477,6 +9517,7 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -9632,6 +9673,7 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -9896,6 +9938,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10353,6 +10396,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10820,6 +10864,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11276,6 +11321,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11719,6 +11765,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12172,6 +12219,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12594,6 +12642,7 @@ define bfloat @flat_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_no ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12962,6 +13011,7 @@ define void @flat_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_no ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -13363,6 +13413,7 @@ define bfloat @flat_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13548,6 +13599,7 @@ define bfloat @flat_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13829,6 +13881,7 @@ define void @flat_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -14008,6 +14061,7 @@ define void @flat_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -14192,6 +14246,7 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__amdgpu_no_fine_grained_memo ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14422,6 +14477,7 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_fi ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14663,6 +14719,7 @@ define <2 x half> @flat_agent_atomic_fmin_ret_v2f16__offset12b_neg__amdgpu_no_fi ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v0, v1 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14906,6 +14963,7 @@ define void @flat_agent_atomic_fmin_noret_v2f16__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15126,6 +15184,7 @@ define void @flat_agent_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15359,6 +15418,7 @@ define void @flat_agent_atomic_fmin_noret_v2f16__offset12b_neg__amdgpu_no_fine_g ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15601,6 +15661,7 @@ define <2 x half> @flat_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_f ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15681,6 +15742,7 @@ define <2 x half> @flat_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_f ; GFX90A-NEXT: v_pk_max_f16 v2, v3, v3 ; GFX90A-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15838,6 +15900,7 @@ define void @flat_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15916,6 +15979,7 @@ define void @flat_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: v_pk_max_f16 v2, v3, v3 ; GFX90A-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -16159,6 +16223,7 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained_m ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16608,6 +16673,7 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_no ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17068,6 +17134,7 @@ define <2 x bfloat> @flat_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_no ; GFX942-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v2, v0, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17528,6 +17595,7 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memory( ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17960,6 +18028,7 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18405,6 +18474,7 @@ define void @flat_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18866,6 +18936,7 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19044,6 +19115,7 @@ define <2 x bfloat> @flat_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_n ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19320,6 +19392,7 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19493,6 +19566,7 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19633,6 +19707,6 @@ define void @flat_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fine } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll index 0fb799ea66461..53612827cd2a3 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll @@ -55,6 +55,7 @@ define float @flat_agent_atomic_fsub_ret_f32(ptr %ptr, float %val) #0 { ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -250,6 +251,7 @@ define float @flat_agent_atomic_fsub_ret_f32__offset12b_pos(ptr %ptr, float %val ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -455,6 +457,7 @@ define float @flat_agent_atomic_fsub_ret_f32__offset12b_neg(ptr %ptr, float %val ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v6, v7, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[6:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -661,6 +664,7 @@ define void @flat_agent_atomic_fsub_noret_f32(ptr %ptr, float %val) #0 { ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -846,6 +850,7 @@ define void @flat_agent_atomic_fsub_noret_f32__offset12b_pos(ptr %ptr, float %va ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1044,6 +1049,7 @@ define void @flat_agent_atomic_fsub_noret_f32__offset12b_neg(ptr %ptr, float %va ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1252,6 +1258,7 @@ define float @flat_system_atomic_fsub_ret_f32__offset12b_pos(ptr %ptr, float %va ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1326,6 +1333,7 @@ define float @flat_system_atomic_fsub_ret_f32__offset12b_pos(ptr %ptr, float %va ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1452,6 +1460,7 @@ define void @flat_system_atomic_fsub_noret_f32__offset12b_pos(ptr %ptr, float %v ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1523,6 +1532,7 @@ define void @flat_system_atomic_fsub_noret_f32__offset12b_pos(ptr %ptr, float %v ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1652,6 +1662,7 @@ define float @flat_agent_atomic_fsub_ret_f32__ftz(ptr %ptr, float %val) #1 { ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1847,6 +1858,7 @@ define float @flat_agent_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr %ptr, float ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2052,6 +2064,7 @@ define float @flat_agent_atomic_fsub_ret_f32__offset12b_neg__ftz(ptr %ptr, float ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v6, v7, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[6:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2258,6 +2271,7 @@ define void @flat_agent_atomic_fsub_noret_f32__ftz(ptr %ptr, float %val) #1 { ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2443,6 +2457,7 @@ define void @flat_agent_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr %ptr, floa ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2641,6 +2656,7 @@ define void @flat_agent_atomic_fsub_noret_f32__offset12b_neg__ftz(ptr %ptr, floa ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2849,6 +2865,7 @@ define float @flat_system_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr %ptr, floa ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2923,6 +2940,7 @@ define float @flat_system_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr %ptr, floa ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3049,6 +3067,7 @@ define void @flat_system_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr %ptr, flo ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -3120,6 +3139,7 @@ define void @flat_system_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr %ptr, flo ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3281,6 +3301,7 @@ define double @flat_agent_atomic_fsub_ret_f64(ptr %ptr, double %val) #0 { ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3707,6 +3728,7 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_pos(ptr %ptr, double %v ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[8:9], v[4:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4153,6 +4175,7 @@ define double @flat_agent_atomic_fsub_ret_f64__offset12b_neg(ptr %ptr, double %v ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[8:9], v[4:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4590,6 +4613,7 @@ define void @flat_agent_atomic_fsub_noret_f64(ptr %ptr, double %val) #0 { ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5011,6 +5035,7 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_pos(ptr %ptr, double %v ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5447,6 +5472,7 @@ define void @flat_agent_atomic_fsub_noret_f64__offset12b_neg(ptr %ptr, double %v ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5909,6 +5935,7 @@ define half @flat_agent_atomic_fsub_ret_f16(ptr %ptr, half %val) #0 { ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6281,6 +6308,7 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val) ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6662,6 +6690,7 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_neg(ptr %ptr, half %val) ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7035,6 +7064,7 @@ define void @flat_agent_atomic_fsub_noret_f16(ptr %ptr, half %val) #0 { ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7395,6 +7425,7 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %val ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7764,6 +7795,7 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_neg(ptr %ptr, half %val ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8101,6 +8133,7 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos__align4(ptr %ptr, hal ; GFX942-NEXT: v_sub_f16_e32 v3, v5, v2 ; GFX942-NEXT: v_and_or_b32 v4, v5, s2, v3 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8378,6 +8411,7 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b__align4_pos(ptr %ptr, h ; GFX942-NEXT: v_sub_f16_e32 v3, v5, v2 ; GFX942-NEXT: v_and_or_b32 v4, v5, s2, v3 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8688,6 +8722,7 @@ define half @flat_system_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val) ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -8837,6 +8872,7 @@ define half @flat_system_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val) ; GFX90A-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX90A-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -9069,6 +9105,7 @@ define void @flat_system_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %va ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -9213,6 +9250,7 @@ define void @flat_system_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %va ; GFX90A-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX90A-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -9473,6 +9511,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16(ptr %ptr, bfloat %val) #0 { ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9929,6 +9968,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat % ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10395,6 +10435,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr %ptr, bfloat % ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10850,6 +10891,7 @@ define void @flat_agent_atomic_fsub_noret_bf16(ptr %ptr, bfloat %val) #0 { ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v4, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11292,6 +11334,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat % ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11744,6 +11787,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr %ptr, bfloat % ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12165,6 +12209,7 @@ define bfloat @flat_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr %ptr, ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12532,6 +12577,7 @@ define void @flat_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr %ptr, ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12932,6 +12978,7 @@ define bfloat @flat_system_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13117,6 +13164,7 @@ define bfloat @flat_system_atomic_fsub_ret_bf16__offset12b_pos(ptr %ptr, bfloat ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13397,6 +13445,7 @@ define void @flat_system_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13576,6 +13625,7 @@ define void @flat_system_atomic_fsub_noret_bf16__offset12b_pos(ptr %ptr, bfloat ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13754,6 +13804,7 @@ define <2 x half> @flat_agent_atomic_fsub_ret_v2f16(ptr %ptr, <2 x half> %val) # ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -13967,6 +14018,7 @@ define <2 x half> @flat_agent_atomic_fsub_ret_v2f16__offset12b_pos(ptr %ptr, <2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14191,6 +14243,7 @@ define <2 x half> @flat_agent_atomic_fsub_ret_v2f16__offset12b_neg(ptr %ptr, <2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v6, v7, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[6:7] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14416,6 +14469,7 @@ define void @flat_agent_atomic_fsub_noret_v2f16(ptr %ptr, <2 x half> %val) #0 { ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14617,6 +14671,7 @@ define void @flat_agent_atomic_fsub_noret_v2f16__offset12b_pos(ptr %ptr, <2 x ha ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14831,6 +14886,7 @@ define void @flat_agent_atomic_fsub_noret_v2f16__offset12b_neg(ptr %ptr, <2 x ha ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15055,6 +15111,7 @@ define <2 x half> @flat_system_atomic_fsub_ret_v2f16__offset12b_pos(ptr %ptr, <2 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15129,6 +15186,7 @@ define <2 x half> @flat_system_atomic_fsub_ret_v2f16__offset12b_pos(ptr %ptr, <2 ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15274,6 +15332,7 @@ define void @flat_system_atomic_fsub_noret_v2f16__offset12b_pos(ptr %ptr, <2 x h ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15345,6 +15404,7 @@ define void @flat_system_atomic_fsub_noret_v2f16__offset12b_pos(ptr %ptr, <2 x h ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15582,6 +15642,7 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16(ptr %ptr, <2 x bfloat> %v ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16031,6 +16092,7 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr, ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16491,6 +16553,7 @@ define <2 x bfloat> @flat_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr %ptr, ; GFX942-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v2, v0, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v0, v[4:5], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16951,6 +17014,7 @@ define void @flat_agent_atomic_fsub_noret_v2bf16(ptr %ptr, <2 x bfloat> %val) #0 ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17383,6 +17447,7 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x b ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17828,6 +17893,7 @@ define void @flat_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr %ptr, <2 x b ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18289,6 +18355,7 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr, ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -18467,6 +18534,7 @@ define <2 x bfloat> @flat_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr %ptr, ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -18743,6 +18811,7 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -18916,6 +18985,7 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19056,4 +19126,4 @@ define void @flat_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr %ptr, <2 x } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll index dffdeebf1220d..54fb38ba877ad 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll @@ -25,6 +25,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -37,6 +38,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -66,6 +68,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_2047(ptr inreg %sbase, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v[0:1], v2 offset:2047 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -78,6 +81,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_2047(ptr inreg %sbase, i ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v[2:3], v1 offset:2047 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -111,6 +115,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_neg2048(ptr inreg %sbase ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -126,6 +131,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_neg2048(ptr inreg %sbase ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -155,6 +161,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -167,6 +174,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -196,6 +204,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_2048(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:2048 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -208,6 +217,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_2048(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v0, v[2:3], v1 offset:2048 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -241,6 +251,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_neg2048(ptr inreg %sbase, i32 %v ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -256,6 +267,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_neg2048(ptr inreg %sbase, i32 %v ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -317,6 +329,7 @@ define amdgpu_ps float @flat_xchg_saddr_uniform_ptr_in_vgprs_rtn(i32 %voffset, i ; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[4:5], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -331,6 +344,7 @@ define amdgpu_ps float @flat_xchg_saddr_uniform_ptr_in_vgprs_rtn(i32 %voffset, i ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -386,6 +400,7 @@ define amdgpu_ps float @flat_xchg_saddr_uniform_ptr_in_vgprs_rtn_immoffset(i32 % ; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[4:5], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:42 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -400,6 +415,7 @@ define amdgpu_ps float @flat_xchg_saddr_uniform_ptr_in_vgprs_rtn_immoffset(i32 % ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v0, v[2:3], v1 offset:42 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -456,6 +472,7 @@ define amdgpu_ps void @flat_xchg_saddr_uniform_ptr_in_vgprs_nortn(i32 %voffset, ; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[4:5], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -470,6 +487,7 @@ define amdgpu_ps void @flat_xchg_saddr_uniform_ptr_in_vgprs_nortn(i32 %voffset, ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -524,6 +542,7 @@ define amdgpu_ps void @flat_xchg_saddr_uniform_ptr_in_vgprs_nortn_immoffset(i32 ; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[4:5], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v[0:1], v2 offset:42 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -538,6 +557,7 @@ define amdgpu_ps void @flat_xchg_saddr_uniform_ptr_in_vgprs_nortn_immoffset(i32 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap v[2:3], v1 offset:42 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -671,6 +691,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: s_branch .LBB10_5 ; GFX950-SDAG-NEXT: .LBB10_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -712,6 +733,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-NEXT: s_branch .LBB10_5 ; GFX950-GISEL-NEXT: .LBB10_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -859,6 +881,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX950-SDAG-NEXT: s_branch .LBB11_5 ; GFX950-SDAG-NEXT: .LBB11_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -903,6 +926,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX950-GISEL-NEXT: s_branch .LBB11_5 ; GFX950-GISEL-NEXT: .LBB11_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1023,6 +1047,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB12_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1056,6 +1081,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB12_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1177,6 +1203,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB13_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1214,6 +1241,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB13_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_swap_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1256,6 +1284,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1268,6 +1297,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_add v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1300,6 +1330,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1315,6 +1346,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_add v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1345,6 +1377,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1357,6 +1390,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_add v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1388,6 +1422,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1403,6 +1438,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_add v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1527,6 +1563,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: s_branch .LBB18_5 ; GFX950-SDAG-NEXT: .LBB18_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1569,6 +1606,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-NEXT: s_branch .LBB18_5 ; GFX950-GISEL-NEXT: .LBB18_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_add_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1719,6 +1757,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: s_branch .LBB19_5 ; GFX950-SDAG-NEXT: .LBB19_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1764,6 +1803,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-NEXT: s_branch .LBB19_5 ; GFX950-GISEL-NEXT: .LBB19_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_add_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -1893,6 +1933,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB20_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -1929,6 +1970,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB20_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_add_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2061,6 +2103,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB21_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -2101,6 +2144,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB21_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_add_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2148,6 +2192,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -2160,6 +2205,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_sub v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2192,6 +2238,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -2207,6 +2254,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_sub v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2237,6 +2285,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -2249,6 +2298,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_sub v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2280,6 +2330,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -2295,6 +2346,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_sub v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2419,6 +2471,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: s_branch .LBB26_5 ; GFX950-SDAG-NEXT: .LBB26_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -2463,6 +2516,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-NEXT: s_branch .LBB26_5 ; GFX950-GISEL-NEXT: .LBB26_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2613,6 +2667,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: s_branch .LBB27_5 ; GFX950-SDAG-NEXT: .LBB27_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -2660,6 +2715,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-NEXT: s_branch .LBB27_5 ; GFX950-GISEL-NEXT: .LBB27_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2789,6 +2845,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB28_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -2827,6 +2884,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB28_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_sub_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -2959,6 +3017,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB29_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3001,6 +3060,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB29_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_sub_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3048,6 +3108,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3060,6 +3121,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_and v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3092,6 +3154,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3107,6 +3170,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_and v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3137,6 +3201,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3149,6 +3214,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_and v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3180,6 +3246,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3195,6 +3262,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_and v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3321,6 +3389,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: s_branch .LBB34_5 ; GFX950-SDAG-NEXT: .LBB34_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3364,6 +3433,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-NEXT: s_branch .LBB34_5 ; GFX950-GISEL-NEXT: .LBB34_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_and_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3515,6 +3585,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: s_branch .LBB35_5 ; GFX950-SDAG-NEXT: .LBB35_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3561,6 +3632,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-NEXT: s_branch .LBB35_5 ; GFX950-GISEL-NEXT: .LBB35_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_and_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3691,6 +3763,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB36_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3728,6 +3801,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB36_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_and_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3861,6 +3935,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB37_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3902,6 +3977,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB37_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_and_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3948,6 +4024,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -3960,6 +4037,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i3 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_or v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -3992,6 +4070,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4007,6 +4086,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_or v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4037,6 +4117,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4049,6 +4130,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_or v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4080,6 +4162,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4095,6 +4178,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_or v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4221,6 +4305,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn(ptr inreg %sbase, i32 %voffs ; GFX950-SDAG-NEXT: s_branch .LBB42_5 ; GFX950-SDAG-NEXT: .LBB42_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4264,6 +4349,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn(ptr inreg %sbase, i32 %voffs ; GFX950-GISEL-NEXT: s_branch .LBB42_5 ; GFX950-GISEL-NEXT: .LBB42_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_or_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4415,6 +4501,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32 ; GFX950-SDAG-NEXT: s_branch .LBB43_5 ; GFX950-SDAG-NEXT: .LBB43_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4461,6 +4548,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32 ; GFX950-GISEL-NEXT: s_branch .LBB43_5 ; GFX950-GISEL-NEXT: .LBB43_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_or_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4591,6 +4679,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB44_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4628,6 +4717,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB44_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_or_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4761,6 +4851,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB45_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4802,6 +4893,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB45_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_or_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4848,6 +4940,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4860,6 +4953,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_xor v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4892,6 +4986,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4907,6 +5002,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_xor v0, v[2:3], v1 sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4937,6 +5033,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4949,6 +5046,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_xor v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -4980,6 +5078,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -4995,6 +5094,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_xor v[2:3], v1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -5121,6 +5221,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: s_branch .LBB50_5 ; GFX950-SDAG-NEXT: .LBB50_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -5164,6 +5265,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-NEXT: s_branch .LBB50_5 ; GFX950-GISEL-NEXT: .LBB50_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -5315,6 +5417,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: s_branch .LBB51_5 ; GFX950-SDAG-NEXT: .LBB51_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor_x2 v[0:1], v[4:5], v[2:3] sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -5361,6 +5464,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-NEXT: s_branch .LBB51_5 ; GFX950-GISEL-NEXT: .LBB51_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3], v[4:5] sc0 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -5491,6 +5595,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB52_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -5528,6 +5633,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB52_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_xor_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -5661,6 +5767,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB53_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor_x2 v[0:1], v[2:3] ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc1 @@ -5702,6 +5809,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB53_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_xor_x2 v[0:1], v[4:5] ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc1 @@ -9093,6 +9201,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffse ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] sc0 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc0 sc1 @@ -9106,6 +9215,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffse ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v5, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] sc0 sc1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc0 sc1 @@ -9140,6 +9250,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] sc0 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc0 sc1 @@ -9156,6 +9267,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] sc0 sc1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc0 sc1 @@ -9188,6 +9300,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffs ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc0 sc1 @@ -9201,6 +9314,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffs ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v5, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] sc1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc0 sc1 @@ -9233,6 +9347,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc0 sc1 @@ -9249,6 +9364,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-GISEL-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] sc1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc0 sc1 @@ -9379,6 +9495,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn(ptr inreg %sbase, i32 % ; GFX950-SDAG-NEXT: s_branch .LBB90_5 ; GFX950-SDAG-NEXT: .LBB90_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[4:7] sc0 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc0 sc1 @@ -9426,6 +9543,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn(ptr inreg %sbase, i32 % ; GFX950-GISEL-NEXT: s_branch .LBB90_5 ; GFX950-GISEL-NEXT: .LBB90_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] sc0 sc1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc0 sc1 @@ -9584,6 +9702,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase ; GFX950-SDAG-NEXT: s_branch .LBB91_5 ; GFX950-SDAG-NEXT: .LBB91_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[4:7] sc0 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc0 sc1 @@ -9634,6 +9753,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase ; GFX950-GISEL-NEXT: s_branch .LBB91_5 ; GFX950-GISEL-NEXT: .LBB91_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] sc0 sc1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc0 sc1 @@ -9771,6 +9891,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffs ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB92_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:7] sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc0 sc1 @@ -9812,6 +9933,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffs ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB92_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:9] sc1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc0 sc1 @@ -9951,6 +10073,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 ; GFX950-SDAG-NEXT: s_endpgm ; GFX950-SDAG-NEXT: .LBB93_3: ; %atomicrmw.global ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:7] sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: buffer_inv sc0 sc1 @@ -9996,6 +10119,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 ; GFX950-GISEL-NEXT: s_endpgm ; GFX950-GISEL-NEXT: .LBB93_3: ; %atomicrmw.global ; GFX950-GISEL-NEXT: buffer_wbl2 sc0 sc1 +; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) ; GFX950-GISEL-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[6:9] sc1 ; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-GISEL-NEXT: buffer_inv sc0 sc1 diff --git a/llvm/test/CodeGen/AMDGPU/fmax3.ll b/llvm/test/CodeGen/AMDGPU/fmax3.ll index 94f7eee4a6efb..4368f2a5de3b1 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax3.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax3.ll @@ -510,15 +510,15 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs ; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX11-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX11-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[20:23], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v1.l, v2.l +; GFX11-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v0.h, v1.l ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -570,15 +570,15 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs ; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v2.l +; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l ; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm ; @@ -631,15 +631,15 @@ define amdgpu_kernel void @test_fmax3_olt_0_f16(ptr addrspace(1) %out, ptr addrs ; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13 ; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14 ; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[4:7], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8 ; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9 -; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v2.l +; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v0.h, v1.l ; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-TRUE16-NEXT: s_endpgm ; @@ -803,15 +803,15 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs ; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX11-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX11-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_max3_f16 v0.l, v0.l, v1.l, v2.l +; GFX11-TRUE16-NEXT: v_max3_f16 v0.l, v1.l, v0.l, v0.h ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -863,15 +863,15 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs ; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v2.l +; GFX12-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v0.l, v0.h ; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm ; @@ -924,15 +924,15 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(ptr addrspace(1) %out, ptr addrs ; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13 ; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14 ; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8 ; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9 -; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v0.l, v1.l, v2.l +; GFX1250-TRUE16-NEXT: v_max3_num_f16 v0.l, v1.l, v0.l, v0.h ; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-TRUE16-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll index f3a84e6e45260..0537e8c2ed59b 100644 --- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll @@ -57,9 +57,9 @@ define amdgpu_kernel void @test_fmax_legacy_uge_f32_fast(ptr addrspace(1) %out, ; GCN-DAG: v_add_f32_e32 [[ADD_A:v[0-9]+]], 1.0, [[A]] ; GCN-DAG: v_add_f32_e32 [[ADD_B:v[0-9]+]], 2.0, [[B]] -; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]] +; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]] -; VI: v_cmp_nlt_f32_e32 vcc, [[ADD_A]], [[ADD_B]] +; VI: v_cmp_ge_f32_e32 vcc, [[ADD_A]], [[ADD_B]] ; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[ADD_B]], [[ADD_A]] diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll index be9027bdef823..f538cba5ed356 100644 --- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll +++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll @@ -218,5 +218,5 @@ declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #1 declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #1 declare double @llvm.maxnum.f64(double, double) -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/fmin3.ll b/llvm/test/CodeGen/AMDGPU/fmin3.ll index 6be2eb93ee25c..142bdd42b2c00 100644 --- a/llvm/test/CodeGen/AMDGPU/fmin3.ll +++ b/llvm/test/CodeGen/AMDGPU/fmin3.ll @@ -510,15 +510,15 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs ; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX11-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX11-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[20:23], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v1.l, v2.l +; GFX11-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v0.h, v1.l ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -570,15 +570,15 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs ; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v2.l +; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l ; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm ; @@ -631,15 +631,15 @@ define amdgpu_kernel void @test_fmin3_olt_0_f16(ptr addrspace(1) %out, ptr addrs ; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13 ; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14 ; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[4:7], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[20:23], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8 ; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9 -; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v2.l +; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v0.h, v1.l ; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-TRUE16-NEXT: s_endpgm ; @@ -803,15 +803,15 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs ; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX11-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX11-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_min3_f16 v0.l, v0.l, v1.l, v2.l +; GFX11-TRUE16-NEXT: v_min3_f16 v0.l, v1.l, v0.l, v0.h ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -863,15 +863,15 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs ; GFX12-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX12-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX12-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX12-TRUE16-NEXT: buffer_load_u16 v1, off, s[12:15], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v2.l +; GFX12-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v0.l, v0.h ; GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_endpgm ; @@ -924,15 +924,15 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(ptr addrspace(1) %out, ptr addrs ; GFX1250-TRUE16-NEXT: s_mov_b32 s17, s13 ; GFX1250-TRUE16-NEXT: s_mov_b32 s20, s14 ; GFX1250-TRUE16-NEXT: s_mov_b32 s21, s15 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: buffer_load_u16 v0, off, s[20:23], null scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], null scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: s_mov_b32 s0, s8 ; GFX1250-TRUE16-NEXT: s_mov_b32 s1, s9 -; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v0.l, v1.l, v2.l +; GFX1250-TRUE16-NEXT: v_min3_num_f16 v0.l, v1.l, v0.l, v0.h ; GFX1250-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-TRUE16-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll index 39eefa1879870..b478e9a0830eb 100644 --- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll @@ -81,9 +81,9 @@ define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_fast(ptr addrspace(1) %out ; VI-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[#LOAD + 2]], 1.0 ; VI-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[#LOAD + 3]], 2.0 -; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]] +; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]] -; VI: v_cmp_ngt_f32_e32 vcc, [[ADD_A]], [[ADD_B]] +; VI: v_cmp_le_f32_e32 vcc, [[ADD_A]], [[ADD_B]] ; VI: v_cndmask_b32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]], vcc define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_nnan_src(ptr addrspace(1) %out, float %a, float %b) #0 { %a.nnan = fadd nnan float %a, 1.0 diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.f64.ll b/llvm/test/CodeGen/AMDGPU/fminnum.f64.ll index 92597594123ee..d15a144984ddc 100644 --- a/llvm/test/CodeGen/AMDGPU/fminnum.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/fminnum.f64.ll @@ -113,5 +113,5 @@ define amdgpu_kernel void @test_fmin_v16f64(ptr addrspace(1) %out, <16 x double> } attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "denormal-fp-math"="ieee,ieee" } -attributes #2 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(ieee|ieee) } +attributes #2 = { nounwind denormal_fpenv(preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.ll b/llvm/test/CodeGen/AMDGPU/fminnum.ll index 22bd13f2379cf..95b315b8baa59 100644 --- a/llvm/test/CodeGen/AMDGPU/fminnum.ll +++ b/llvm/test/CodeGen/AMDGPU/fminnum.ll @@ -225,5 +225,5 @@ declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #1 declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/fmul.f16.ll b/llvm/test/CodeGen/AMDGPU/fmul.f16.ll index 082006898b436..3bf4f5aafbe12 100644 --- a/llvm/test/CodeGen/AMDGPU/fmul.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fmul.f16.ll @@ -69,13 +69,13 @@ define amdgpu_kernel void @fmul_f16( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -163,7 +163,7 @@ define amdgpu_kernel void @fmul_f16_imm_a( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x4200, v0.l @@ -246,7 +246,7 @@ define amdgpu_kernel void @fmul_f16_imm_b( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, 4.0, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll index fb4289144ca1f..13e4206ab7f57 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll @@ -6106,7 +6106,7 @@ declare <2 x half> @llvm.fma.v2f16(<2 x half>, <2 x half>, <2 x half>) declare half @llvm.fmuladd.f16(half, half, half) #1 declare <4 x half> @llvm.fmuladd.v4f16(<4 x half>, <4 x half>, <4 x half>) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } -attributes #4 = { nounwind "amdgpu-ieee"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #4 = { nounwind "amdgpu-ieee"="false" denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll index 69d1ee3f533a6..e50489cdeba54 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll @@ -157,11 +157,11 @@ declare half @llvm.arithmetic.fence.f16(half) #1 declare float @llvm.amdgcn.interp.p1.f16(float, i32, i32, i1, i32) #0 declare half @llvm.amdgcn.interp.p2.f16(float, float, i32, i32, i1, i32) #0 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } attributes #3 = { nounwind "no-signed-zeros-fp-math"="true" } -attributes #4 = { nounwind "amdgpu-ieee"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #4 = { nounwind "amdgpu-ieee"="false" denormal_fpenv(float: preservesign) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN-NSZ: {{.*}} ; GCN-SAFE: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll index 4a5eae770a674..cfa5247267559 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll @@ -8323,6 +8323,6 @@ declare float @llvm.amdgcn.fmul.legacy(float, float) #1 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll index 3e7d67a40b12b..e1fef9083e132 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll @@ -4657,7 +4657,7 @@ declare half @llvm.maxnum.f16(half, half) #1 declare half @llvm.amdgcn.sin.f16(half) #1 declare half @llvm.amdgcn.rcp.f16(half) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } -attributes #4 = { nounwind "amdgpu-ieee"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #4 = { nounwind "amdgpu-ieee"="false" denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/fold-fabs.ll b/llvm/test/CodeGen/AMDGPU/fold-fabs.ll index bb1f01b641aee..8e65f9a5e7f70 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-fabs.ll +++ b/llvm/test/CodeGen/AMDGPU/fold-fabs.ll @@ -9,7 +9,7 @@ define float @fold_abs_in_branch(float %arg1, float %arg2) { ; GFX10-NEXT: s_mov_b32 s4, exec_lo ; GFX10-NEXT: v_add_f32_e32 v1, v0, v1 ; GFX10-NEXT: v_add_f32_e64 v0, |v1|, |v1| -; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v0 +; GFX10-NEXT: v_cmpx_ge_f32_e32 1.0, v0 ; GFX10-NEXT: ; %bb.1: ; %if ; GFX10-NEXT: v_mul_f32_e64 v0, 0x3e4ccccd, |v1| ; GFX10-NEXT: ; %bb.2: ; %exit @@ -40,7 +40,7 @@ define float @fold_abs_in_branch_multiple_users(float %arg1, float %arg2) { ; GFX10-NEXT: s_mov_b32 s4, exec_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_f32_e64 v1, |v0|, |v0| -; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v1 +; GFX10-NEXT: v_cmpx_ge_f32_e32 1.0, v1 ; GFX10-NEXT: ; %bb.1: ; %if ; GFX10-NEXT: v_mul_f32_e64 v1, 0x3e4ccccd, |v0| ; GFX10-NEXT: ; %bb.2: ; %exit @@ -126,7 +126,7 @@ define float @fold_abs_in_branch_fabs(float %arg1, float %arg2) { ; GFX10-NEXT: s_mov_b32 s4, exec_lo ; GFX10-NEXT: v_add_f32_e32 v1, v0, v1 ; GFX10-NEXT: v_add_f32_e64 v0, |v1|, |v1| -; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v0 +; GFX10-NEXT: v_cmpx_ge_f32_e32 1.0, v0 ; GFX10-NEXT: ; %bb.1: ; %if ; GFX10-NEXT: v_mul_f32_e64 v0, 0x3e4ccccd, |v1| ; GFX10-NEXT: ; %bb.2: ; %exit @@ -158,7 +158,7 @@ define float @fold_abs_in_branch_phi(float %arg1, float %arg2) { ; GFX10-NEXT: s_mov_b32 s4, exec_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_f32_e64 v0, |v0|, |v0| -; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v0 +; GFX10-NEXT: v_cmpx_ge_f32_e32 1.0, v0 ; GFX10-NEXT: s_cbranch_execz .LBB5_3 ; GFX10-NEXT: ; %bb.1: ; %header.preheader ; GFX10-NEXT: ; implicit-def: $vgpr0 @@ -202,7 +202,7 @@ define float @fold_neg_in_branch(float %arg1, float %arg2) { ; GFX10-NEXT: s_mov_b32 s4, exec_lo ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_mov_b32_e32 v1, v0 -; GFX10-NEXT: v_cmpx_nlt_f32_e32 1.0, v0 +; GFX10-NEXT: v_cmpx_ge_f32_e32 1.0, v0 ; GFX10-NEXT: ; %bb.1: ; %if ; GFX10-NEXT: v_rcp_f32_e64 v1, -v0 ; GFX10-NEXT: v_mul_f32_e64 v1, |v0|, v1 diff --git a/llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll b/llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll index 24c6303a6306c..648ac6c2517e6 100644 --- a/llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll +++ b/llvm/test/CodeGen/AMDGPU/fp-atomics-gfx942.ll @@ -14,6 +14,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f32_noret_pat(ptr %ptr) { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -57,6 +58,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f32_noret_pat_ieee(ptr %ptr) #0 { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v[0:1], v2 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -97,6 +99,7 @@ define float @flat_atomic_fadd_f32_rtn_pat(ptr %ptr, float %data) { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f32 v0, v[0:1], v2 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -268,6 +271,6 @@ define <2 x i16> @local_atomic_fadd_v2bf16_rtn(ptr addrspace(3) %ptr, <2 x i16> ret <2 x i16> %ret } -attributes #0 = { "denormal-fp-math-f32"="ieee,ieee" } +attributes #0 = { denormal_fpenv(float: ieee|ieee) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll index 82af553f60059..e5b55140b44bd 100644 --- a/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll +++ b/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll @@ -1483,7 +1483,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat(ptr addrspace(1) %pt ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1] ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1496,7 +1496,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat(ptr addrspace(1) %pt ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1] sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1540,7 +1540,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent(ptr addrspace( ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], 4.0 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1] ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1573,7 +1573,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_system(ptr addrspace ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v1, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 -; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1] ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1586,7 +1586,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_system(ptr addrspace ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1] sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1630,7 +1630,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_flush(ptr addrspace( ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], 4.0 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1] ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1662,6 +1662,7 @@ define double @global_atomic_fadd_f64_rtn_pat(ptr addrspace(1) %ptr, double %dat ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1673,6 +1674,7 @@ define double @global_atomic_fadd_f64_rtn_pat(ptr addrspace(1) %ptr, double %dat ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1712,6 +1714,7 @@ define double @global_atomic_fadd_f64_rtn_pat_agent(ptr addrspace(1) %ptr, doubl ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1742,6 +1745,7 @@ define double @global_atomic_fadd_f64_rtn_pat_system(ptr addrspace(1) %ptr, doub ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1753,6 +1757,7 @@ define double @global_atomic_fadd_f64_rtn_pat_system(ptr addrspace(1) %ptr, doub ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1806,7 +1811,7 @@ define amdgpu_kernel void @global_atomic_fadd_f64_noret_pat_agent_safe(ptr addrs ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: v_mov_b64_e32 v[0:1], 4.0 ; GFX942-NEXT: buffer_wbl2 sc1 -; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v2, v[0:1], s[0:1] ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1840,6 +1845,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat(ptr %ptr) #1 { ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_add_f64 v[2:3], v[0:1] ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1853,6 +1859,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[2:3], v[0:1] sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1897,6 +1904,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[2:3], v[0:1] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1930,6 +1938,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_system(ptr %ptr) #1 { ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_add_f64 v[2:3], v[0:1] ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1943,6 +1952,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_system(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[2:3], v[0:1] sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1974,6 +1984,7 @@ define double @flat_atomic_fadd_f64_rtn_pat(ptr %ptr) #1 { ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1985,6 +1996,7 @@ define double @flat_atomic_fadd_f64_rtn_pat(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2024,6 +2036,7 @@ define double @flat_atomic_fadd_f64_rtn_pat_agent(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2054,6 +2067,7 @@ define double @flat_atomic_fadd_f64_rtn_pat_system(ptr %ptr) #1 { ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 ; GFX90A-NEXT: v_mov_b32_e32 v3, 0x40100000 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2066,6 +2080,7 @@ define double @flat_atomic_fadd_f64_rtn_pat_system(ptr %ptr) #1 { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], 4.0 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[0:1], v[0:1], v[2:3] sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2121,6 +2136,7 @@ define amdgpu_kernel void @flat_atomic_fadd_f64_noret_pat_agent_safe(ptr %ptr) { ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: flat_atomic_add_f64 v[2:3], v[0:1] ; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2427,11 +2443,11 @@ main_body: ret double %ret } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(preservesign) } attributes #1 = { nounwind } -attributes #2 = { "denormal-fp-math"="ieee,ieee" } -attributes #3 = { "denormal-fp-math"="ieee,ieee" } -attributes #4 = { "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #2 = { denormal_fpenv(ieee|ieee) } +attributes #3 = { denormal_fpenv(ieee|ieee) } +attributes #4 = { denormal_fpenv(preservesign) } !0 = !{} !1 = !{i32 5, i32 6} diff --git a/llvm/test/CodeGen/AMDGPU/fpext-free.ll b/llvm/test/CodeGen/AMDGPU/fpext-free.ll index b88cb210c91e8..10a925f9df687 100644 --- a/llvm/test/CodeGen/AMDGPU/fpext-free.ll +++ b/llvm/test/CodeGen/AMDGPU/fpext-free.ll @@ -5,8 +5,8 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11-FAKE16,GFX11-F32DENORM,GFX11-F32DENORM-FAKE16 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX89,GFX9-F32FLUSH %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GFX89,GFX9-F32DENORM %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX89 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GFX89 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX89,GFX8,GFX8-F32FLUSH %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -denormal-fp-math-f32=ieee < %s | FileCheck -enable-var-scope -check-prefixes=GFX89,GFX8,GFX8-F32DENORM %s ; fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) define float @fadd_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 { @@ -14,18 +14,16 @@ define float @fadd_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 { ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel_hi:[1,1,0] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fadd_fpext_fmul_f16_to_f32: ; GFX11-FAKE16: ; %bb.0: ; %entry ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel_hi:[1,1,0] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fadd_fpext_fmul_f16_to_f32: @@ -41,6 +39,14 @@ define float @fadd_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 { ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fadd_fpext_fmul_f16_to_f32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX8-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %x, %y %mul.ext = fpext half %mul to float @@ -118,18 +124,16 @@ define float @fadd_fpext_fmul_f16_to_f32_commute(half %x, half %y, float %z) #0 ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel_hi:[1,1,0] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fadd_fpext_fmul_f16_to_f32_commute: ; GFX11-FAKE16: ; %bb.0: ; %entry ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v0, 1.0, v2 op_sel_hi:[1,1,0] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fadd_fpext_fmul_f16_to_f32_commute: @@ -145,6 +149,14 @@ define float @fadd_fpext_fmul_f16_to_f32_commute(half %x, half %y, float %z) #0 ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v2, v0 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fadd_fpext_fmul_f16_to_f32_commute: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX8-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %x, %y %mul.ext = fpext half %mul to float @@ -189,6 +201,25 @@ define float @fadd_muladd_fpext_fmul_f16_to_f32(float %x, float %y, half %u, hal ; GFX9-F32DENORM-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32FLUSH-LABEL: fadd_muladd_fpext_fmul_f16_to_f32: +; GFX8-F32FLUSH: ; %bb.0: ; %entry +; GFX8-F32FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32FLUSH-NEXT: v_mul_f16_e32 v2, v2, v3 +; GFX8-F32FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX8-F32FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1 +; GFX8-F32FLUSH-NEXT: v_add_f32_e32 v0, v2, v4 +; GFX8-F32FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32DENORM-LABEL: fadd_muladd_fpext_fmul_f16_to_f32: +; GFX8-F32DENORM: ; %bb.0: ; %entry +; GFX8-F32DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32DENORM-NEXT: v_mul_f16_e32 v2, v2, v3 +; GFX8-F32DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX8-F32DENORM-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX8-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v4 +; GFX8-F32DENORM-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %u, %v %mul.ext = fpext half %mul to float @@ -234,6 +265,25 @@ define float @fadd_muladd_fpext_fmul_f16_to_f32_commute(float %x, float %y, half ; GFX9-F32DENORM-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v4, v0 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32FLUSH-LABEL: fadd_muladd_fpext_fmul_f16_to_f32_commute: +; GFX8-F32FLUSH: ; %bb.0: ; %entry +; GFX8-F32FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32FLUSH-NEXT: v_mul_f16_e32 v2, v2, v3 +; GFX8-F32FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX8-F32FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1 +; GFX8-F32FLUSH-NEXT: v_add_f32_e32 v0, v4, v2 +; GFX8-F32FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32DENORM-LABEL: fadd_muladd_fpext_fmul_f16_to_f32_commute: +; GFX8-F32DENORM: ; %bb.0: ; %entry +; GFX8-F32DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32DENORM-NEXT: v_mul_f16_e32 v2, v2, v3 +; GFX8-F32DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX8-F32DENORM-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX8-F32DENORM-NEXT: v_add_f32_e32 v0, v4, v0 +; GFX8-F32DENORM-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %u, %v %mul.ext = fpext half %mul to float @@ -277,6 +327,25 @@ define float @fadd_fmad_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half ; GFX9-F32DENORM-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32FLUSH-LABEL: fadd_fmad_fpext_fmul_f16_to_f32: +; GFX8-F32FLUSH: ; %bb.0: ; %entry +; GFX8-F32FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32FLUSH-NEXT: v_mul_f16_e32 v2, v2, v3 +; GFX8-F32FLUSH-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX8-F32FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1 +; GFX8-F32FLUSH-NEXT: v_add_f32_e32 v0, v2, v4 +; GFX8-F32FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32DENORM-LABEL: fadd_fmad_fpext_fmul_f16_to_f32: +; GFX8-F32DENORM: ; %bb.0: ; %entry +; GFX8-F32DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32DENORM-NEXT: v_mul_f16_e32 v2, v2, v3 +; GFX8-F32DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX8-F32DENORM-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX8-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v4 +; GFX8-F32DENORM-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %u, %v %mul.ext = fpext half %mul to float @@ -323,6 +392,15 @@ define float @fadd_fma_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half % ; GFX9-F32DENORM-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fadd_fma_fpext_fmul_f16_to_f32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v2, v2, v3 +; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX8-NEXT: v_fma_f32 v0, v0, v1, v2 +; GFX8-NEXT: v_add_f32_e32 v0, v0, v4 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul contract half %u, %v %mul.ext = fpext half %mul to float @@ -366,6 +444,15 @@ define float @fadd_fma_fpext_fmul_f16_to_f32_commute(float %x, float %y, half %u ; GFX9-F32DENORM-NEXT: v_fma_f32 v0, v0, v1, v2 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v4, v0 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fadd_fma_fpext_fmul_f16_to_f32_commute: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v2, v2, v3 +; GFX8-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GFX8-NEXT: v_fma_f32 v0, v0, v1, v2 +; GFX8-NEXT: v_add_f32_e32 v0, v4, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul contract half %u, %v %mul.ext = fpext half %mul to float @@ -380,12 +467,10 @@ define float @fadd_fpext_fmuladd_f16_to_f32(float %x, half %y, half %z, half %u, ; GFX11-TRUE16-LABEL: fadd_fpext_fmuladd_f16_to_f32: ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v1.h, v3.l, v4.l +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v1.h, v1.l, v2.l -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v1.l, v2.l +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fadd_fpext_fmuladd_f16_to_f32: @@ -394,9 +479,7 @@ define float @fadd_fpext_fmuladd_f16_to_f32(float %x, half %y, half %z, half %u, ; GFX11-FAKE16-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v3, v1, v2 -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fadd_fpext_fmuladd_f16_to_f32: @@ -414,6 +497,15 @@ define float @fadd_fpext_fmuladd_f16_to_f32(float %x, half %y, half %z, half %u, ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fadd_fpext_fmuladd_f16_to_f32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-NEXT: v_fma_f16 v1, v1, v2, v3 +; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul contract half %u, %v %fma = call half @llvm.fmuladd.f16(half %y, half %z, half %mul) @@ -426,12 +518,10 @@ define float @fadd_fpext_fma_f16_to_f32(float %x, half %y, half %z, half %u, hal ; GFX11-TRUE16-LABEL: fadd_fpext_fma_f16_to_f32: ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v1.h, v3.l, v4.l +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v1.h, v1.l, v2.l -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v1.l, v2.l +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fadd_fpext_fma_f16_to_f32: @@ -440,9 +530,7 @@ define float @fadd_fpext_fma_f16_to_f32(float %x, half %y, half %z, half %u, hal ; GFX11-FAKE16-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v3, v1, v2 -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fadd_fpext_fma_f16_to_f32: @@ -460,6 +548,15 @@ define float @fadd_fpext_fma_f16_to_f32(float %x, half %y, half %z, half %u, hal ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fadd_fpext_fma_f16_to_f32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-NEXT: v_fma_f16 v1, v1, v2, v3 +; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul contract half %u, %v %fma = call half @llvm.fma.f16(half %y, half %z, half %mul) @@ -472,12 +569,10 @@ define float @fadd_fpext_fma_f16_to_f32_commute(float %x, half %y, half %z, half ; GFX11-TRUE16-LABEL: fadd_fpext_fma_f16_to_f32_commute: ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v1.h, v3.l, v4.l +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v1.h, v1.l, v2.l -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v1, v0 +; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v1.l, v2.l +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fadd_fpext_fma_f16_to_f32_commute: @@ -486,9 +581,7 @@ define float @fadd_fpext_fma_f16_to_f32_commute(float %x, half %y, half %z, half ; GFX11-FAKE16-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v3, v1, v2 -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, v1, v0 +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v3, 1.0, v0 op_sel_hi:[1,1,0] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fadd_fpext_fma_f16_to_f32_commute: @@ -506,6 +599,15 @@ define float @fadd_fpext_fma_f16_to_f32_commute(float %x, half %y, half %z, half ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-F32DENORM-NEXT: v_add_f32_e32 v0, v1, v0 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fadd_fpext_fma_f16_to_f32_commute: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-NEXT: v_fma_f16 v1, v1, v2, v3 +; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX8-NEXT: v_add_f32_e32 v0, v1, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul contract half %u, %v %fma = call half @llvm.fma.f16(half %y, half %z, half %mul) @@ -521,18 +623,16 @@ define float @fsub_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 { ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l -; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fsub_fpext_fmul_f16_to_f32: ; GFX11-FAKE16: ; %bb.0: ; %entry ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX11-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fsub_fpext_fmul_f16_to_f32: @@ -548,6 +648,14 @@ define float @fsub_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 { ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fsub_fpext_fmul_f16_to_f32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %x, %y %mul.ext = fpext half %mul to float @@ -568,18 +676,16 @@ define float @fsub_fpext_fmul_f16_to_f32_commute(float %x, half %y, half %z) #0 ; GFX11-F32DENORM-TRUE16: ; %bb.0: ; %entry ; GFX11-F32DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-F32DENORM-TRUE16-NEXT: v_mul_f16_e32 v1.l, v1.l, v2.l -; GFX11-F32DENORM-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-F32DENORM-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l -; GFX11-F32DENORM-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX11-F32DENORM-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-F32DENORM-TRUE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,0] ; GFX11-F32DENORM-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-F32DENORM-FAKE16-LABEL: fsub_fpext_fmul_f16_to_f32_commute: ; GFX11-F32DENORM-FAKE16: ; %bb.0: ; %entry ; GFX11-F32DENORM-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-F32DENORM-FAKE16-NEXT: v_mul_f16_e32 v1, v1, v2 -; GFX11-F32DENORM-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-F32DENORM-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GFX11-F32DENORM-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX11-F32DENORM-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-F32DENORM-FAKE16-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,0] ; GFX11-F32DENORM-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fsub_fpext_fmul_f16_to_f32_commute: @@ -595,6 +701,14 @@ define float @fsub_fpext_fmul_f16_to_f32_commute(float %x, half %y, half %z) #0 ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1 ; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fsub_fpext_fmul_f16_to_f32_commute: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v1, v1, v2 +; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul contract half %y, %z %mul.ext = fpext half %mul to float @@ -609,18 +723,16 @@ define float @fsub_fpext_fneg_fmul_f16_to_f32(half %x, half %y, float %z) #0 { ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l -; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fsub_fpext_fneg_fmul_f16_to_f32: ; GFX11-FAKE16: ; %bb.0: ; %entry ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_mul_f16_e64 v0, v0, -v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX11-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fsub_fpext_fneg_fmul_f16_to_f32: @@ -636,6 +748,14 @@ define float @fsub_fpext_fneg_fmul_f16_to_f32(half %x, half %y, float %z) #0 { ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fsub_fpext_fneg_fmul_f16_to_f32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e64 v0, v0, -v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %x, %y %neg.mul = fsub half -0.0, %mul @@ -651,18 +771,16 @@ define float @fsub_fneg_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 { ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, v0.l, -v1.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l -; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fsub_fneg_fpext_fmul_f16_to_f32: ; GFX11-FAKE16: ; %bb.0: ; %entry ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_mul_f16_e64 v0, v0, -v1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX11-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-F32FLUSH-LABEL: fsub_fneg_fpext_fmul_f16_to_f32: @@ -678,6 +796,14 @@ define float @fsub_fneg_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 { ; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0 ; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fsub_fneg_fpext_fmul_f16_to_f32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e64 v0, v0, -v1 +; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %x, %y %mul.ext = fpext half %mul to float @@ -723,6 +849,25 @@ define float @fsub_muladd_fpext_mul_f16_to_f32(float %x, float %y, float %z, hal ; GFX9-F32DENORM-NEXT: v_fma_f32 v0, v0, v1, v3 ; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32FLUSH-LABEL: fsub_muladd_fpext_mul_f16_to_f32: +; GFX8-F32FLUSH: ; %bb.0: ; %entry +; GFX8-F32FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32FLUSH-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-F32FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX8-F32FLUSH-NEXT: v_mac_f32_e32 v3, v0, v1 +; GFX8-F32FLUSH-NEXT: v_sub_f32_e32 v0, v3, v2 +; GFX8-F32FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32DENORM-LABEL: fsub_muladd_fpext_mul_f16_to_f32: +; GFX8-F32DENORM: ; %bb.0: ; %entry +; GFX8-F32DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32DENORM-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-F32DENORM-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX8-F32DENORM-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX8-F32DENORM-NEXT: v_add_f32_e32 v0, v0, v3 +; GFX8-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX8-F32DENORM-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul reassoc half %u, %v %mul.ext = fpext half %mul to float @@ -738,12 +883,10 @@ define float @fsub_fpext_muladd_mul_f16_to_f32(half %x, half %y, float %z, half ; GFX11-TRUE16-LABEL: fsub_fpext_muladd_mul_f16_to_f32: ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.h, v3.l, v4.l +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v0.h, v0.l, v1.l -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v3 op_sel_hi:[0,1,1] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fsub_fpext_muladd_mul_f16_to_f32: @@ -752,19 +895,34 @@ define float @fsub_fpext_muladd_mul_f16_to_f32(half %x, half %y, float %z, half ; GFX11-FAKE16-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v3, v0, v1 -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v2, -1.0, v3 op_sel_hi:[0,1,1] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX89-LABEL: fsub_fpext_muladd_mul_f16_to_f32: -; GFX89: ; %bb.0: ; %entry -; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX89-NEXT: v_mul_f16_e32 v3, v3, v4 -; GFX89-NEXT: v_fma_f16 v0, v0, v1, v3 -; GFX89-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX89-NEXT: v_sub_f32_e32 v0, v0, v2 -; GFX89-NEXT: s_setpc_b64 s[30:31] +; GFX9-F32FLUSH-LABEL: fsub_fpext_muladd_mul_f16_to_f32: +; GFX9-F32FLUSH: ; %bb.0: ; %entry +; GFX9-F32FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-F32FLUSH-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX9-F32FLUSH-NEXT: v_fma_f16 v0, v0, v1, v3 +; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, v2, -1.0, v0 op_sel_hi:[0,1,1] +; GFX9-F32FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-F32DENORM-LABEL: fsub_fpext_muladd_mul_f16_to_f32: +; GFX9-F32DENORM: ; %bb.0: ; %entry +; GFX9-F32DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX9-F32DENORM-NEXT: v_fma_f16 v0, v0, v1, v3 +; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fsub_fpext_muladd_mul_f16_to_f32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-NEXT: v_fma_f16 v0, v0, v1, v3 +; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %u, %v %fma = call half @llvm.fmuladd.f16(half %x, half %y, half %mul) @@ -809,6 +967,25 @@ define float @fsub_muladd_fpext_mul_f16_to_f32_commute(float %x, float %y, float ; GFX9-F32DENORM-NEXT: v_fma_f32 v1, v1, v2, v3 ; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v1 ; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32FLUSH-LABEL: fsub_muladd_fpext_mul_f16_to_f32_commute: +; GFX8-F32FLUSH: ; %bb.0: ; %entry +; GFX8-F32FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32FLUSH-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-F32FLUSH-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX8-F32FLUSH-NEXT: v_mac_f32_e32 v3, v1, v2 +; GFX8-F32FLUSH-NEXT: v_sub_f32_e32 v0, v0, v3 +; GFX8-F32FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-F32DENORM-LABEL: fsub_muladd_fpext_mul_f16_to_f32_commute: +; GFX8-F32DENORM: ; %bb.0: ; %entry +; GFX8-F32DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-F32DENORM-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-F32DENORM-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GFX8-F32DENORM-NEXT: v_mul_f32_e32 v1, v1, v2 +; GFX8-F32DENORM-NEXT: v_add_f32_e32 v1, v1, v3 +; GFX8-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX8-F32DENORM-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul reassoc half %u, %v %mul.ext = fpext half %mul to float @@ -824,12 +1001,10 @@ define float @fsub_fpext_muladd_mul_f16_to_f32_commute(float %x, half %y, half % ; GFX11-TRUE16-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute: ; GFX11-TRUE16: ; %bb.0: ; %entry ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v1.h, v3.l, v4.l +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v3.l, v3.l, v4.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v1.h, v1.l, v2.l -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v3.l, v1.l, v2.l +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v0, v3, -1.0, v0 op_sel_hi:[1,1,0] ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-FAKE16-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute: @@ -838,19 +1013,34 @@ define float @fsub_fpext_muladd_mul_f16_to_f32_commute(float %x, half %y, half % ; GFX11-FAKE16-NEXT: v_mul_f16_e32 v3, v3, v4 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_fmac_f16_e32 v3, v1, v2 -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v0, v3, -1.0, v0 op_sel_hi:[1,1,0] ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX89-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute: -; GFX89: ; %bb.0: ; %entry -; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX89-NEXT: v_mul_f16_e32 v3, v3, v4 -; GFX89-NEXT: v_fma_f16 v1, v1, v2, v3 -; GFX89-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GFX89-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX89-NEXT: s_setpc_b64 s[30:31] +; GFX9-F32FLUSH-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute: +; GFX9-F32FLUSH: ; %bb.0: ; %entry +; GFX9-F32FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-F32FLUSH-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX9-F32FLUSH-NEXT: v_fma_f16 v1, v1, v2, v3 +; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,0] +; GFX9-F32FLUSH-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-F32DENORM-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute: +; GFX9-F32DENORM: ; %bb.0: ; %entry +; GFX9-F32DENORM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX9-F32DENORM-NEXT: v_fma_f16 v1, v1, v2, v3 +; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX9-F32DENORM-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: fsub_fpext_muladd_mul_f16_to_f32_commute: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_mul_f16_e32 v3, v3, v4 +; GFX8-NEXT: v_fma_f16 v1, v1, v2, v3 +; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX8-NEXT: s_setpc_b64 s[30:31] entry: %mul = fmul half %u, %v %fma = call half @llvm.fmuladd.f16(half %y, half %z, half %mul) diff --git a/llvm/test/CodeGen/AMDGPU/fpext.f16.ll b/llvm/test/CodeGen/AMDGPU/fpext.f16.ll index 94c2d3364a769..fc7d87e92e1b3 100644 --- a/llvm/test/CodeGen/AMDGPU/fpext.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fpext.f16.ll @@ -53,7 +53,7 @@ define amdgpu_kernel void @fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l @@ -136,7 +136,7 @@ define amdgpu_kernel void @fpext_f16_to_f64( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l @@ -465,7 +465,7 @@ define amdgpu_kernel void @fneg_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l @@ -547,7 +547,7 @@ define amdgpu_kernel void @fabs_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, |v0.l| @@ -629,7 +629,7 @@ define amdgpu_kernel void @fneg_fabs_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -|v0.l| @@ -722,16 +722,16 @@ define amdgpu_kernel void @fneg_multi_use_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l -; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x8000, v1 +; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x8000, v0 +; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v0.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l -; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l +; GFX11-TRUE16-NEXT: buffer_store_b32 v2, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -825,14 +825,14 @@ define amdgpu_kernel void @fneg_multi_foldable_use_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e64 v1.l, -v0.l, v0.l -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -v0.l -; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v0.l +; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, -v0.l, v0.l +; GFX11-TRUE16-NEXT: buffer_store_b32 v1, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -925,16 +925,16 @@ define amdgpu_kernel void @fabs_multi_use_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, |v0.l| -; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l +; GFX11-TRUE16-NEXT: buffer_store_b32 v2, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -1028,14 +1028,14 @@ define amdgpu_kernel void @fabs_multi_foldable_use_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e64 v1.l, |v0.l|, v0.l -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, |v0.l| -; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.l| +; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, |v0.l|, v0.l +; GFX11-TRUE16-NEXT: buffer_store_b32 v1, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -1128,16 +1128,16 @@ define amdgpu_kernel void @fabs_fneg_multi_use_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l -; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x8000, v1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x8000, v0 +; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -|v0.l| ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -|v0.l| -; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l +; GFX11-TRUE16-NEXT: buffer_store_b32 v2, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -1232,14 +1232,14 @@ define amdgpu_kernel void @fabs_fneg_multi_foldable_use_fpext_f16_to_f32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e64 v1.l, -|v0.l|, v0.l -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v0, -|v0.l| -; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -|v0.l| +; GFX11-TRUE16-NEXT: v_mul_f16_e64 v0.l, -|v0.l|, v0.l +; GFX11-TRUE16-NEXT: buffer_store_b32 v1, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/fptosi.f16.ll b/llvm/test/CodeGen/AMDGPU/fptosi.f16.ll index ac269ee0d5abe..db483562c46ab 100644 --- a/llvm/test/CodeGen/AMDGPU/fptosi.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fptosi.f16.ll @@ -54,7 +54,7 @@ define amdgpu_kernel void @fptosi_f16_to_i16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l @@ -137,7 +137,7 @@ define amdgpu_kernel void @fptosi_f16_to_i32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l @@ -229,7 +229,7 @@ define amdgpu_kernel void @fptosi_f16_to_i64( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/fptoui.f16.ll b/llvm/test/CodeGen/AMDGPU/fptoui.f16.ll index af1ab37e48474..5b231eabad706 100644 --- a/llvm/test/CodeGen/AMDGPU/fptoui.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fptoui.f16.ll @@ -54,7 +54,7 @@ define amdgpu_kernel void @fptoui_f16_to_i16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l @@ -137,7 +137,7 @@ define amdgpu_kernel void @fptoui_f16_to_i32( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l @@ -230,7 +230,7 @@ define amdgpu_kernel void @fptoui_f16_to_i64( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll index 77faf363ca412..9dd8d8f230217 100644 --- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll @@ -249,7 +249,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16( ; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-GISEL-TRUE16-NEXT: s_endpgm @@ -512,7 +512,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_afn(ptr addrspace(1) %r, ; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-GISEL-TRUE16-NEXT: s_endpgm @@ -1170,7 +1170,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16( ; GFX11-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000 ; GFX11-GISEL-TRUE16-NEXT: s_or_b32 s2, s3, s2 ; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 -; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 ; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX11-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-TRUE16-NEXT: s_endpgm @@ -1417,7 +1417,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16( ; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000 ; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s2, s3, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-GISEL-TRUE16-NEXT: s_endpgm @@ -4264,7 +4264,7 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16( ; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-GISEL-TRUE16-NEXT: s_endpgm @@ -4534,7 +4534,7 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16( ; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-GISEL-TRUE16-NEXT: s_endpgm @@ -4804,7 +4804,7 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16( ; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null ; GFX1250-GISEL-TRUE16-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll index 0a1e3bb0979ac..0a2c59668714d 100644 --- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll +++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll @@ -490,61 +490,173 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in) ; GFX11-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-SDAG-NEXT: s_endpgm ; -; GFX11-GISEL-LABEL: fptrunc_f64_to_f16: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-GISEL-NEXT: s_bfe_u32 s4, s3, 0xb0014 -; GFX11-GISEL-NEXT: s_lshr_b32 s5, s3, 8 -; GFX11-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff -; GFX11-GISEL-NEXT: s_addk_i32 s4, 0xfc10 -; GFX11-GISEL-NEXT: s_and_b32 s5, s5, 0xffe -; GFX11-GISEL-NEXT: s_or_b32 s2, s6, s2 -; GFX11-GISEL-NEXT: s_cselect_b32 s2, 1, 0 -; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-GISEL-NEXT: s_or_b32 s2, s5, s2 -; GFX11-GISEL-NEXT: s_cselect_b32 s5, 1, 0 -; GFX11-GISEL-NEXT: s_sub_i32 s6, 1, s4 -; GFX11-GISEL-NEXT: s_or_b32 s8, s2, 0x1000 -; GFX11-GISEL-NEXT: s_max_i32 s6, s6, 0 -; GFX11-GISEL-NEXT: s_lshl_b32 s7, s4, 12 -; GFX11-GISEL-NEXT: s_min_i32 s6, s6, 13 -; GFX11-GISEL-NEXT: s_lshl_b32 s5, s5, 9 -; GFX11-GISEL-NEXT: s_lshr_b32 s9, s8, s6 -; GFX11-GISEL-NEXT: s_or_b32 s2, s2, s7 -; GFX11-GISEL-NEXT: s_lshl_b32 s6, s9, s6 -; GFX11-GISEL-NEXT: s_or_b32 s5, s5, 0x7c00 -; GFX11-GISEL-NEXT: s_cmp_lg_u32 s6, s8 -; GFX11-GISEL-NEXT: s_cselect_b32 s6, 1, 0 -; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-GISEL-NEXT: s_or_b32 s6, s9, s6 -; GFX11-GISEL-NEXT: s_cmp_lt_i32 s4, 1 -; GFX11-GISEL-NEXT: s_cselect_b32 s2, s6, s2 -; GFX11-GISEL-NEXT: s_and_b32 s6, s2, 7 -; GFX11-GISEL-NEXT: s_lshr_b32 s2, s2, 2 -; GFX11-GISEL-NEXT: s_cmp_eq_u32 s6, 3 -; GFX11-GISEL-NEXT: s_cselect_b32 s7, 1, 0 -; GFX11-GISEL-NEXT: s_cmp_gt_i32 s6, 5 -; GFX11-GISEL-NEXT: s_cselect_b32 s6, 1, 0 -; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-GISEL-NEXT: s_or_b32 s6, s7, s6 -; GFX11-GISEL-NEXT: s_cmp_lg_u32 s6, 0 -; GFX11-GISEL-NEXT: s_cselect_b32 s6, 1, 0 -; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-GISEL-NEXT: s_add_i32 s2, s2, s6 -; GFX11-GISEL-NEXT: s_cmp_gt_i32 s4, 30 -; GFX11-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2 -; GFX11-GISEL-NEXT: s_cmpk_eq_i32 s4, 0x40f -; GFX11-GISEL-NEXT: s_cselect_b32 s2, s5, s2 -; GFX11-GISEL-NEXT: s_lshr_b32 s3, s3, 16 -; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-GISEL-NEXT: s_and_b32 s3, s3, 0x8000 -; GFX11-GISEL-NEXT: s_or_b32 s2, s3, s2 -; GFX11-GISEL-NEXT: s_mov_b32 s3, 0x31016000 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-GISEL-NEXT: s_mov_b32 s2, -1 -; GFX11-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0 -; GFX11-GISEL-NEXT: s_endpgm +; GFX11-SAFE-GISEL-LABEL: fptrunc_f64_to_f16: +; GFX11-SAFE-GISEL: ; %bb.0: +; GFX11-SAFE-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-SAFE-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SAFE-GISEL-NEXT: s_bfe_u32 s4, s3, 0xb0014 +; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s5, s3, 8 +; GFX11-SAFE-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff +; GFX11-SAFE-GISEL-NEXT: s_addk_i32 s4, 0xfc10 +; GFX11-SAFE-GISEL-NEXT: s_and_b32 s5, s5, 0xffe +; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s6, s2 +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0 +; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s5, s2 +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GFX11-SAFE-GISEL-NEXT: s_sub_i32 s6, 1, s4 +; GFX11-SAFE-GISEL-NEXT: s_or_b32 s8, s2, 0x1000 +; GFX11-SAFE-GISEL-NEXT: s_max_i32 s6, s6, 0 +; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s7, s4, 12 +; GFX11-SAFE-GISEL-NEXT: s_min_i32 s6, s6, 13 +; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s5, s5, 9 +; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s9, s8, s6 +; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s2, s7 +; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s6, s9, s6 +; GFX11-SAFE-GISEL-NEXT: s_or_b32 s5, s5, 0x7c00 +; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, s8 +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-SAFE-GISEL-NEXT: s_or_b32 s6, s9, s6 +; GFX11-SAFE-GISEL-NEXT: s_cmp_lt_i32 s4, 1 +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, s6, s2 +; GFX11-SAFE-GISEL-NEXT: s_and_b32 s6, s2, 7 +; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s2, s2, 2 +; GFX11-SAFE-GISEL-NEXT: s_cmp_eq_u32 s6, 3 +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s7, 1, 0 +; GFX11-SAFE-GISEL-NEXT: s_cmp_gt_i32 s6, 5 +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SAFE-GISEL-NEXT: s_or_b32 s6, s7, s6 +; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, 0 +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-SAFE-GISEL-NEXT: s_add_i32 s2, s2, s6 +; GFX11-SAFE-GISEL-NEXT: s_cmp_gt_i32 s4, 30 +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2 +; GFX11-SAFE-GISEL-NEXT: s_cmpk_eq_i32 s4, 0x40f +; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, s5, s2 +; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s3, s3, 16 +; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-SAFE-GISEL-NEXT: s_and_b32 s3, s3, 0x8000 +; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s3, s2 +; GFX11-SAFE-GISEL-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-SAFE-GISEL-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX11-SAFE-GISEL-NEXT: s_mov_b32 s2, -1 +; GFX11-SAFE-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0 +; GFX11-SAFE-GISEL-NEXT: s_endpgm +; +; GFX11-UNSAFE-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16: +; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0: +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_bfe_u32 s4, s3, 0xb0014 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshr_b32 s5, s3, 8 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_and_b32 s6, s3, 0x1ff +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_addk_i32 s4, 0xfc10 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_and_b32 s5, s5, 0xffe +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s2, s6, s2 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s2, 1, 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s2, s5, s2 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s5, 1, 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_sub_i32 s6, 1, s4 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s8, s2, 0x1000 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_max_i32 s6, s6, 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshl_b32 s7, s4, 12 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_min_i32 s6, s6, 13 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshl_b32 s5, s5, 9 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshr_b32 s9, s8, s6 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s2, s2, s7 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshl_b32 s6, s9, s6 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s5, s5, 0x7c00 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, s8 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s6, s9, s6 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_lt_i32 s4, 1 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s2, s6, s2 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_and_b32 s6, s2, 7 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshr_b32 s2, s2, 2 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_eq_u32 s6, 3 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s7, 1, 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s6, 5 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s6, s7, s6 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_add_i32 s2, s2, s6 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s4, 30 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s2, 0x7c00, s2 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmpk_eq_i32 s4, 0x40f +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s2, s5, s2 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshr_b32 s3, s3, 16 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s2, s3, s2 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 +; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_endpgm +; +; GFX11-UNSAFE-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16: +; GFX11-UNSAFE-GISEL-FAKE16: ; %bb.0: +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_bfe_u32 s4, s3, 0xb0014 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshr_b32 s5, s3, 8 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_and_b32 s6, s3, 0x1ff +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_addk_i32 s4, 0xfc10 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_and_b32 s5, s5, 0xffe +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s2, s6, s2 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s2, 1, 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s2, s5, s2 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s5, 1, 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_sub_i32 s6, 1, s4 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s8, s2, 0x1000 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_max_i32 s6, s6, 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshl_b32 s7, s4, 12 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_min_i32 s6, s6, 13 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshl_b32 s5, s5, 9 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshr_b32 s9, s8, s6 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s2, s2, s7 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshl_b32 s6, s9, s6 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s5, s5, 0x7c00 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s6, s8 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s6, s9, s6 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_lt_i32 s4, 1 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s2, s6, s2 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_and_b32 s6, s2, 7 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshr_b32 s2, s2, 2 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_eq_u32 s6, 3 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s7, 1, 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s6, 5 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s6, s7, s6 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s6, 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_add_i32 s2, s2, s6 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s4, 30 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s2, 0x7c00, s2 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmpk_eq_i32 s4, 0x40f +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s2, s5, s2 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshr_b32 s3, s3, 16 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_and_b32 s3, s3, 0x8000 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s2, s3, s2 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 +; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_endpgm %result = fptrunc double %in to half %result_i16 = bitcast half %result to i16 store i16 %result_i16, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/frame-index.mir b/llvm/test/CodeGen/AMDGPU/frame-index.mir index 81bd8baaa0e5d..ab544e5336754 100644 --- a/llvm/test/CodeGen/AMDGPU/frame-index.mir +++ b/llvm/test/CodeGen/AMDGPU/frame-index.mir @@ -401,22 +401,22 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_0_live_scc__no_free_vgprs ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -426,12 +426,12 @@ body: | ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX8-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: $sgpr4 = S_MOV_B32 64 ; GFX8-NEXT: $vgpr0, dead $vcc = V_ADD_CO_U32_e64 killed $sgpr4, killed $vgpr0, 0, implicit $exec ; GFX8-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec - ; GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) + ; GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) ; GFX8-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -440,43 +440,43 @@ body: | ; GFX8-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX8-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX8-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX8-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.16, addrspace 5) - ; GFX8-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GFX8-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GFX8-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GFX8-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GFX8-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GFX8-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GFX8-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GFX8-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GFX8-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GFX8-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GFX8-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GFX8-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) - ; GFX8-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; GFX8-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) - ; GFX8-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX8-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX8-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX8-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX8-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX8-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX8-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX8-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX8-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX8-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX8-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX8-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX8-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX8-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX8-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX8-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) + ; GFX8-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX8-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc ; ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_0_live_scc__no_free_vgprs ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX900-NEXT: {{ $}} - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -486,11 +486,11 @@ body: | ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX900-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX900-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: $vgpr0 = V_ADD_U32_e32 64, killed $vgpr0, implicit $exec ; GFX900-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec - ; GFX900-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) + ; GFX900-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) ; GFX900-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -499,22 +499,22 @@ body: | ; GFX900-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX900-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX900-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX900-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.16, addrspace 5) - ; GFX900-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GFX900-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GFX900-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GFX900-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GFX900-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GFX900-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GFX900-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GFX900-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GFX900-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GFX900-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GFX900-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GFX900-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) - ; GFX900-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; GFX900-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) - ; GFX900-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX900-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX900-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX900-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX900-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX900-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX900-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX900-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX900-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX900-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX900-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX900-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX900-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX900-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX900-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX900-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) + ; GFX900-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX900-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc ; ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_0_live_scc__no_free_vgprs @@ -545,10 +545,10 @@ body: | ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX90A-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX90A-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec - ; GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) + ; GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) ; GFX90A-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX90A-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX90A-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -615,22 +615,22 @@ body: | ; GFX8-LABEL: name: materialize_fi_s_mov_b32_offset_96_live_scc__no_free_vgprs ; GFX8: liveins: $sgpr4, $sgpr5, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX8-NEXT: {{ $}} - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -640,12 +640,12 @@ body: | ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX8-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX8-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.18, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.18, addrspace 5) ; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX8-NEXT: $sgpr4 = S_MOV_B32 128 ; GFX8-NEXT: $vgpr0, dead $vcc = V_ADD_CO_U32_e64 killed $sgpr4, killed $vgpr0, 0, implicit $exec ; GFX8-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec - ; GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.18, addrspace 5) + ; GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.18, addrspace 5) ; GFX8-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX8-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX8-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -654,43 +654,43 @@ body: | ; GFX8-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX8-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX8-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX8-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) - ; GFX8-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.16, addrspace 5) - ; GFX8-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GFX8-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GFX8-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GFX8-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GFX8-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GFX8-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GFX8-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GFX8-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GFX8-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GFX8-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GFX8-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GFX8-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) - ; GFX8-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; GFX8-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX8-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) + ; GFX8-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX8-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX8-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX8-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX8-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX8-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX8-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX8-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX8-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX8-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX8-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX8-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX8-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX8-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX8-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX8-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc ; ; GFX900-LABEL: name: materialize_fi_s_mov_b32_offset_96_live_scc__no_free_vgprs ; GFX900: liveins: $sgpr4, $sgpr5, $vgpr40, $vgpr41, $vgpr42, $vgpr43, $vgpr44, $vgpr45, $vgpr46, $vgpr47, $vgpr56, $vgpr57, $vgpr58, $vgpr59, $vgpr60, $vgpr61, $vgpr62, $vgpr63 ; GFX900-NEXT: {{ $}} - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr41, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr42, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr43, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr44, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr45, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr46, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr47, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr56, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr57, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr58, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr59, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr60, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr61, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr62, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -700,11 +700,11 @@ body: | ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX900-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX900-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (store (s32) into %stack.18, addrspace 5) + ; GFX900-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.18, addrspace 5) ; GFX900-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX900-NEXT: $vgpr0 = V_ADD_U32_e32 128, killed $vgpr0, implicit $exec ; GFX900-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec - ; GFX900-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: (load (s32) from %stack.18, addrspace 5) + ; GFX900-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.18, addrspace 5) ; GFX900-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX900-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX900-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 @@ -713,22 +713,22 @@ body: | ; GFX900-NEXT: S_NOP 0, implicit $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX900-NEXT: S_NOP 0, implicit $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX900-NEXT: S_NOP 0, implicit $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 - ; GFX900-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) - ; GFX900-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.16, addrspace 5) - ; GFX900-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GFX900-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GFX900-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GFX900-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GFX900-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GFX900-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GFX900-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GFX900-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GFX900-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GFX900-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GFX900-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GFX900-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) - ; GFX900-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; GFX900-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GFX900-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) + ; GFX900-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX900-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX900-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX900-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX900-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX900-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX900-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX900-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX900-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX900-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX900-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX900-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX900-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX900-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX900-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX900-NEXT: S_ENDPGM 0, implicit $sgpr4, implicit $scc ; ; GFX90A-LABEL: name: materialize_fi_s_mov_b32_offset_96_live_scc__no_free_vgprs @@ -759,11 +759,11 @@ body: | ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55 ; GFX90A-NEXT: S_NOP 0, implicit-def $vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 ; GFX90A-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc - ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.18, addrspace 5) + ; GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.18, addrspace 5) ; GFX90A-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec ; GFX90A-NEXT: $vgpr0 = V_ADD_U32_e32 64, killed $vgpr0, implicit $exec ; GFX90A-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec - ; GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.18, addrspace 5) + ; GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.18, addrspace 5) ; GFX90A-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; GFX90A-NEXT: S_NOP 0, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; GFX90A-NEXT: S_NOP 0, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 diff --git a/llvm/test/CodeGen/AMDGPU/freeze.ll b/llvm/test/CodeGen/AMDGPU/freeze.ll index 2ee95e535b04a..6ed4e6aed92d8 100644 --- a/llvm/test/CodeGen/AMDGPU/freeze.ll +++ b/llvm/test/CodeGen/AMDGPU/freeze.ll @@ -13697,6 +13697,140 @@ define void @freeze_v3i1(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) { ret void } +define void @freeze_i1_scc(i32 inreg %a, i32 inreg %b, ptr addrspace(1) %ptrb) { +; GFX6-SDAG-LABEL: freeze_i1_scc: +; GFX6-SDAG: ; %bb.0: +; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-SDAG-NEXT: s_cmp_eq_u32 s16, s17 +; GFX6-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX6-SDAG-NEXT: s_cselect_b64 s[8:9], -1, 0 +; GFX6-SDAG-NEXT: s_mov_b32 s7, 0xf000 +; GFX6-SDAG-NEXT: s_mov_b32 s4, s6 +; GFX6-SDAG-NEXT: s_mov_b32 s5, s6 +; GFX6-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[8:9] +; GFX6-SDAG-NEXT: buffer_store_byte v2, v[0:1], s[4:7], 0 addr64 +; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX6-GISEL-LABEL: freeze_i1_scc: +; GFX6-GISEL: ; %bb.0: +; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-GISEL-NEXT: s_cmp_eq_u32 s16, s17 +; GFX6-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-GISEL-NEXT: s_and_b32 s4, s4, 1 +; GFX6-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX6-GISEL-NEXT: s_mov_b32 s7, 0xf000 +; GFX6-GISEL-NEXT: s_mov_b64 s[4:5], 0 +; GFX6-GISEL-NEXT: buffer_store_byte v2, v[0:1], s[4:7], 0 addr64 +; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-SDAG-LABEL: freeze_i1_scc: +; GFX7-SDAG: ; %bb.0: +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-SDAG-NEXT: s_cmp_eq_u32 s16, s17 +; GFX7-SDAG-NEXT: s_mov_b32 s6, 0 +; GFX7-SDAG-NEXT: s_cselect_b64 s[8:9], -1, 0 +; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-SDAG-NEXT: s_mov_b32 s4, s6 +; GFX7-SDAG-NEXT: s_mov_b32 s5, s6 +; GFX7-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[8:9] +; GFX7-SDAG-NEXT: buffer_store_byte v2, v[0:1], s[4:7], 0 addr64 +; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX7-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-GISEL-LABEL: freeze_i1_scc: +; GFX7-GISEL: ; %bb.0: +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-GISEL-NEXT: s_cmp_eq_u32 s16, s17 +; GFX7-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX7-GISEL-NEXT: s_and_b32 s4, s4, 1 +; GFX7-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX7-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX7-GISEL-NEXT: s_mov_b32 s6, 0 +; GFX7-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX7-GISEL-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-GISEL-NEXT: s_mov_b64 s[4:5], 0 +; GFX7-GISEL-NEXT: buffer_store_byte v2, v[0:1], s[4:7], 0 addr64 +; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-GISEL-LABEL: freeze_i1_scc: +; GFX8-GISEL: ; %bb.0: +; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-GISEL-NEXT: s_cmp_eq_u32 s16, s17 +; GFX8-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-GISEL-NEXT: s_and_b32 s4, s4, 1 +; GFX8-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX8-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-GISEL-NEXT: flat_store_byte v[0:1], v2 +; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: freeze_i1_scc: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_cmp_eq_u32 s16, s17 +; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-GISEL-NEXT: s_and_b32 s4, s4, 1 +; GFX9-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX9-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: freeze_i1_scc: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_cmp_eq_u32 s16, s17 +; GFX10-SDAG-NEXT: s_cselect_b32 s4, -1, 0 +; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4 +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v2, off +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: freeze_i1_scc: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_cmp_eq_u32 s16, s17 +; GFX10-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-GISEL-NEXT: s_and_b32 s4, s4, 1 +; GFX10-GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GFX10-GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v2, off +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: freeze_i1_scc: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_cmp_eq_u32 s0, s1 +; GFX11-SDAG-NEXT: s_cselect_b32 s0, -1, 0 +; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0 +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v2, off +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: freeze_i1_scc: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_cmp_eq_u32 s0, s1 +; GFX11-GISEL-NEXT: s_cselect_b32 s0, 1, 0 +; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 1 +; GFX11-GISEL-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-GISEL-NEXT: s_cselect_b32 s0, 1, 0 +; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v2, off +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] + %cmp = icmp eq i32 %a, %b + %freeze = freeze i1 %cmp + store i1 %freeze, ptr addrspace(1) %ptrb + ret void +} + define void @freeze_i1_vcc(ptr addrspace(1) %ptra, ptr addrspace(1) %ptrb) { ; GFX6-SDAG-LABEL: freeze_i1_vcc: ; GFX6-SDAG: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll index 374747ada621b..5d243189d516a 100644 --- a/llvm/test/CodeGen/AMDGPU/frem.ll +++ b/llvm/test/CodeGen/AMDGPU/frem.ll @@ -1447,18 +1447,16 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] ; GFX9-NEXT: global_load_ushort v2, v0, s[6:7] offset:8 -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cvt_f32_f16_e32 v4, v2 -; GFX9-NEXT: v_rcp_f32_e32 v4, v4 -; GFX9-NEXT: v_mul_f32_e32 v3, v3, v4 -; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX9-NEXT: v_mac_f32_e32 v3, v5, v4 -; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX9-NEXT: v_mul_f32_e32 v4, v5, v4 -; GFX9-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX9-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v2 +; GFX9-NEXT: v_rcp_f32_e32 v3, v3 +; GFX9-NEXT: v_mad_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX9-NEXT: v_mac_f32_e32 v4, v5, v3 +; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX9-NEXT: v_mul_f32_e32 v3, v5, v3 +; GFX9-NEXT: v_and_b32_e32 v3, 0xff800000, v3 +; GFX9-NEXT: v_add_f32_e32 v3, v3, v4 ; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX9-NEXT: v_div_fixup_f16 v3, v3, v2, v1 ; GFX9-NEXT: v_trunc_f16_e32 v3, v3 @@ -1477,17 +1475,17 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] ; GFX10-NEXT: global_load_ushort v2, v0, s[6:7] offset:8 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 +; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v1 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v2 -; GFX10-NEXT: v_rcp_f32_e32 v5, v4 -; GFX10-NEXT: v_mul_f32_e32 v6, v3, v5 -; GFX10-NEXT: v_mad_f32 v7, -v4, v6, v3 -; GFX10-NEXT: v_mac_f32_e32 v6, v7, v5 -; GFX10-NEXT: v_mad_f32 v3, -v4, v6, v3 -; GFX10-NEXT: v_mul_f32_e32 v3, v3, v5 +; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 +; GFX10-NEXT: v_rcp_f32_e32 v4, v3 +; GFX10-NEXT: v_fma_mix_f32 v5, v1, v4, neg(0) op_sel_hi:[1,0,0] +; GFX10-NEXT: v_mad_f32 v7, -v3, v5, v6 +; GFX10-NEXT: v_mac_f32_e32 v5, v7, v4 +; GFX10-NEXT: v_mad_f32 v3, -v3, v5, v6 +; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX10-NEXT: v_add_f32_e32 v3, v3, v6 +; GFX10-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-NEXT: v_div_fixup_f16 v3, v3, v2, v1 ; GFX10-NEXT: v_trunc_f16_e32 v3, v3 @@ -1505,23 +1503,21 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3] ; GFX11-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v2.l ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v3.l +; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v4, v4 +; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v0, v0 ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4 -; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0] +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v0, v5, v4 -; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] +; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0 +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 +; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v4, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l @@ -1541,23 +1537,21 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] ; GFX11-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] offset:8 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v4, v4 +; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v3, v3 ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4 -; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v3, v5, v4 -; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] +; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3 +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_mul_f32_e32 v4, v5, v4 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 +; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4 ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1 @@ -1577,22 +1571,20 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX1150-TRUE16-NEXT: s_clause 0x1 ; GFX1150-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3] ; GFX1150-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8 -; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX1150-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v2.l ; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX1150-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v3.l +; GFX1150-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) -; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v4, v4 -; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4 +; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v0, v0 +; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0] ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] -; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v5, v4 +; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] +; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0 ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] -; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] +; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0 ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-TRUE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v4, v0 +; GFX1150-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0 +; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 ; GFX1150-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l @@ -1614,22 +1606,20 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX1150-FAKE16-NEXT: s_clause 0x1 ; GFX1150-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] ; GFX1150-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] offset:8 -; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(1) -; GFX1150-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX1150-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GFX1150-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) -; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v4, v4 -; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4 +; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v3, v3 +; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX1150-FAKE16-NEXT: v_fmac_f32_e32 v3, v5, v4 +; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX1150-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3 ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3 ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-FAKE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX1150-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX1150-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3 +; GFX1150-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4 ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX1150-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1 @@ -1651,22 +1641,20 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX1200-TRUE16-NEXT: s_clause 0x1 ; GFX1200-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3] ; GFX1200-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8 -; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x1 -; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v2.l ; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v3.l +; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) -; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v4, v4 -; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4 +; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v0, v0 +; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0] ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] -; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v5, v4 +; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] +; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0 ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] -; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] +; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0 ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-TRUE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v4, v0 +; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0 +; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 ; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l @@ -1688,22 +1676,20 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX1200-FAKE16-NEXT: s_clause 0x1 ; GFX1200-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] ; GFX1200-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] offset:8 -; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x1 -; GFX1200-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1200-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GFX1200-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) -; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v4, v4 -; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4 +; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v3, v3 +; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v3, v5, v4 +; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3 ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3 ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-FAKE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX1200-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3 +; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4 ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX1200-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1 @@ -1945,18 +1931,16 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] ; GFX9-NEXT: global_load_ushort v2, v0, s[6:7] offset:8 -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_cvt_f32_f16_e32 v4, v2 -; GFX9-NEXT: v_rcp_f32_e32 v4, v4 -; GFX9-NEXT: v_mul_f32_e32 v3, v3, v4 -; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX9-NEXT: v_mac_f32_e32 v3, v5, v4 -; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX9-NEXT: v_mul_f32_e32 v4, v5, v4 -; GFX9-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX9-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX9-NEXT: v_cvt_f32_f16_e32 v3, v2 +; GFX9-NEXT: v_rcp_f32_e32 v3, v3 +; GFX9-NEXT: v_mad_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX9-NEXT: v_mac_f32_e32 v4, v5, v3 +; GFX9-NEXT: v_mad_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX9-NEXT: v_mul_f32_e32 v3, v5, v3 +; GFX9-NEXT: v_and_b32_e32 v3, 0xff800000, v3 +; GFX9-NEXT: v_add_f32_e32 v3, v3, v4 ; GFX9-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX9-NEXT: v_div_fixup_f16 v3, v3, v2, v1 ; GFX9-NEXT: v_trunc_f16_e32 v3, v3 @@ -1975,17 +1959,17 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] ; GFX10-NEXT: global_load_ushort v2, v0, s[6:7] offset:8 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v1 +; GFX10-NEXT: v_cvt_f32_f16_e32 v6, v1 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: v_cvt_f32_f16_e32 v4, v2 -; GFX10-NEXT: v_rcp_f32_e32 v5, v4 -; GFX10-NEXT: v_mul_f32_e32 v6, v3, v5 -; GFX10-NEXT: v_mad_f32 v7, -v4, v6, v3 -; GFX10-NEXT: v_mac_f32_e32 v6, v7, v5 -; GFX10-NEXT: v_mad_f32 v3, -v4, v6, v3 -; GFX10-NEXT: v_mul_f32_e32 v3, v3, v5 +; GFX10-NEXT: v_cvt_f32_f16_e32 v3, v2 +; GFX10-NEXT: v_rcp_f32_e32 v4, v3 +; GFX10-NEXT: v_fma_mix_f32 v5, v1, v4, neg(0) op_sel_hi:[1,0,0] +; GFX10-NEXT: v_mad_f32 v7, -v3, v5, v6 +; GFX10-NEXT: v_mac_f32_e32 v5, v7, v4 +; GFX10-NEXT: v_mad_f32 v3, -v3, v5, v6 +; GFX10-NEXT: v_mul_f32_e32 v3, v3, v4 ; GFX10-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; GFX10-NEXT: v_add_f32_e32 v3, v3, v6 +; GFX10-NEXT: v_add_f32_e32 v3, v3, v5 ; GFX10-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX10-NEXT: v_div_fixup_f16 v3, v3, v2, v1 ; GFX10-NEXT: v_trunc_f16_e32 v3, v3 @@ -2003,23 +1987,21 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3] ; GFX11-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v2.l ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v3.l +; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v4, v4 +; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v0, v0 ; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4 -; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0] +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v0, v5, v4 -; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] +; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0 +; GFX11-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 +; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v4, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l @@ -2039,23 +2021,21 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX11-FAKE16-NEXT: s_clause 0x1 ; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] ; GFX11-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] offset:8 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v4, v4 +; GFX11-FAKE16-NEXT: v_rcp_f32_e32 v3, v3 ; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0) -; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4 -; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v3, v5, v4 -; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] +; GFX11-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3 +; GFX11-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_mul_f32_e32 v4, v5, v4 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 +; GFX11-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4 ; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1 @@ -2075,22 +2055,20 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX1150-TRUE16-NEXT: s_clause 0x1 ; GFX1150-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3] ; GFX1150-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8 -; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX1150-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v2.l ; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX1150-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v3.l +; GFX1150-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) -; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v4, v4 -; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4 +; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v0, v0 +; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0] ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] -; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v5, v4 +; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] +; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0 ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] -; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX1150-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] +; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0 ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-TRUE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v4, v0 +; GFX1150-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0 +; GFX1150-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 ; GFX1150-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l @@ -2112,22 +2090,20 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX1150-FAKE16-NEXT: s_clause 0x1 ; GFX1150-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] ; GFX1150-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] offset:8 -; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(1) -; GFX1150-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX1150-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GFX1150-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) -; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v4, v4 -; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4 +; GFX1150-FAKE16-NEXT: v_rcp_f32_e32 v3, v3 +; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX1150-FAKE16-NEXT: v_fmac_f32_e32 v3, v5, v4 +; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX1150-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3 ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX1150-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX1150-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3 ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1150-FAKE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX1150-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX1150-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3 +; GFX1150-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4 ; GFX1150-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1150-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX1150-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1 @@ -2149,22 +2125,20 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX1200-TRUE16-NEXT: s_clause 0x1 ; GFX1200-TRUE16-NEXT: global_load_d16_b16 v2, v1, s[2:3] ; GFX1200-TRUE16-NEXT: global_load_d16_b16 v3, v1, s[4:5] offset:8 -; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x1 -; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v2.l ; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v4, v3.l +; GFX1200-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v3.l ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) -; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v4, v4 -; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v4 +; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v0, v0 +; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v4, v2, v0, neg(0) op_sel_hi:[1,0,0] ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] -; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v5, v4 +; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] +; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v0 ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1] -; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX1200-TRUE16-NEXT: v_fma_mix_f32 v5, -v3, v4, v2 op_sel_hi:[1,0,1] +; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v0, v5, v0 ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-TRUE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v4, v0 +; GFX1200-TRUE16-NEXT: v_and_b32_e32 v0, 0xff800000, v0 +; GFX1200-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4 ; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 ; GFX1200-TRUE16-NEXT: v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l @@ -2186,22 +2160,20 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX1200-FAKE16-NEXT: s_clause 0x1 ; GFX1200-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] ; GFX1200-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5] offset:8 -; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x1 -; GFX1200-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v1 ; GFX1200-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1200-FAKE16-NEXT: v_cvt_f32_f16_e32 v4, v2 +; GFX1200-FAKE16-NEXT: v_cvt_f32_f16_e32 v3, v2 ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1) -; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v4, v4 -; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v3, v4 +; GFX1200-FAKE16-NEXT: v_rcp_f32_e32 v3, v3 +; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v4, v1, v3, neg(0) op_sel_hi:[1,0,0] ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v3, v5, v4 +; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX1200-FAKE16-NEXT: v_fmac_f32_e32 v4, v5, v3 ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1] -; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v4, v5, v4 +; GFX1200-FAKE16-NEXT: v_fma_mix_f32 v5, -v2, v4, v1 op_sel_hi:[1,0,1] +; GFX1200-FAKE16-NEXT: v_mul_f32_e32 v3, v5, v3 ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1200-FAKE16-NEXT: v_and_b32_e32 v4, 0xff800000, v4 -; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v4, v3 +; GFX1200-FAKE16-NEXT: v_and_b32_e32 v3, 0xff800000, v3 +; GFX1200-FAKE16-NEXT: v_add_f32_e32 v3, v3, v4 ; GFX1200-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1200-FAKE16-NEXT: v_cvt_f16_f32_e32 v3, v3 ; GFX1200-FAKE16-NEXT: v_div_fixup_f16 v3, v3, v2, v1 @@ -18931,4 +18903,4 @@ define amdgpu_kernel void @frem_v2f64_const(ptr addrspace(1) %out) #0 { -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll b/llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll index 2629fb3ff0a73..1004afc9a1ac1 100644 --- a/llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll +++ b/llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll @@ -1315,9 +1315,9 @@ declare i1 @llvm.amdgcn.class.f16(half, i32) declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) declare float @llvm.amdgcn.interp.p1.f16(float, i32, i32, i1, i32) -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #2 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #3 = { "denormal-fp-math"="ieee,ieee" strictfp } -attributes #4 = { "denormal-fp-math"="preserve-sign,preserve-sign" strictfp } -attributes #5 = { "denormal-fp-math"="dynamic,dynamic" strictfp } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } +attributes #2 = { denormal_fpenv(dynamic) } +attributes #3 = { denormal_fpenv(ieee|ieee) strictfp } +attributes #4 = { denormal_fpenv(preservesign) strictfp } +attributes #5 = { denormal_fpenv(dynamic) strictfp } diff --git a/llvm/test/CodeGen/AMDGPU/fsub.f16.ll b/llvm/test/CodeGen/AMDGPU/fsub.f16.ll index b8b339964cf0e..5c4bb6f91a50d 100644 --- a/llvm/test/CodeGen/AMDGPU/fsub.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fsub.f16.ll @@ -69,13 +69,13 @@ define amdgpu_kernel void @fsub_f16( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v0.h ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -163,7 +163,7 @@ define amdgpu_kernel void @fsub_f16_imm_a( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: v_sub_f16_e32 v0.l, 1.0, v0.l @@ -246,7 +246,7 @@ define amdgpu_kernel void @fsub_f16_imm_b( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, -2.0, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll index 7d2a48779bef6..3928a44595761 100644 --- a/llvm/test/CodeGen/AMDGPU/function-args.ll +++ b/llvm/test/CodeGen/AMDGPU/function-args.ll @@ -2291,13 +2291,13 @@ define void @void_func_byval_struct_i8_i32(ptr addrspace(5) byval({ i8, i32 }) % ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x1 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v0, off, s32 ; GFX11-TRUE16-NEXT: scratch_load_b32 v1, off, s32 offset:4 +; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v0, off, s32 ; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) ; GFX11-TRUE16-NEXT: buffer_store_b32 v1, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: buffer_store_b8 v0, off, s[0:3], 0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -2402,21 +2402,21 @@ define void @void_func_byval_struct_i8_i32_x2(ptr addrspace(5) byval({ i8, i32 } ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v1, off, s32 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: scratch_load_b32 v3, off, s32 offset:4 glc dlc +; GFX11-TRUE16-NEXT: scratch_load_b32 v2, off, s32 offset:4 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v2, off, s32 offset:8 glc dlc +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v1, off, s32 offset:8 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: scratch_load_b32 v4, off, s32 offset:12 glc dlc +; GFX11-TRUE16-NEXT: scratch_load_b32 v3, off, s32 offset:12 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 -; GFX11-TRUE16-NEXT: buffer_store_b32 v3, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b32 v2, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: buffer_store_b8 v1, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: buffer_store_b32 v4, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b32 v3, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: buffer_store_b8 v2, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v1, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: ds_store_b32 v0, v0 ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) @@ -2652,11 +2652,11 @@ define void @void_func_v32i32_i1_i8_i16_bf16(<32 x i32> %arg0, i1 %arg1, i8 %arg ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_clause 0x5 ; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_u8 v36, off, s32 offset:4 +; GFX11-TRUE16-NEXT: scratch_load_u8 v34, off, s32 offset:4 ; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:20 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:12 +; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:16 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:20 ; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5) @@ -2668,6 +2668,8 @@ define void @void_func_v32i32_i1_i8_i16_bf16(<32 x i32> %arg0, i1 %arg1, i8 %arg ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: buffer_store_b128 v[16:19], off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(4) +; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 1, v34 ; GFX11-TRUE16-NEXT: buffer_store_b128 v[12:15], off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: buffer_store_b128 v[8:11], off, s[0:3], 0 dlc @@ -2676,21 +2678,17 @@ define void @void_func_v32i32_i1_i8_i16_bf16(<32 x i32> %arg0, i1 %arg1, i8 %arg ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(4) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 1, v36 -; GFX11-TRUE16-NEXT: buffer_store_b8 v0, off, s[0:3], 0 dlc -; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3) -; GFX11-TRUE16-NEXT: buffer_store_b8 v32, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v16, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2) -; GFX11-TRUE16-NEXT: buffer_store_b16 v33, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v32, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-TRUE16-NEXT: buffer_store_b16 v34, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b16 v32, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_store_b16 v35, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b16 v33, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b16 v33, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -4134,21 +4132,21 @@ define void @void_func_v32i32_v16i8(<32 x i32> %arg0, <16 x i8> %arg1) #0 { ; GFX11-TRUE16-NEXT: s_clause 0x10 ; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 ; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v32, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v33, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v34, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v35, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v36, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v37, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v38, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v39, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v48, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v49, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v50, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v51, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v52, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v53, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v54, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v55, off, s32 offset:4 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v32, off, s32 offset:60 +; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v33, off, s32 offset:56 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v33, off, s32 offset:52 +; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v34, off, s32 offset:48 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v34, off, s32 offset:44 +; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v35, off, s32 offset:40 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v35, off, s32 offset:36 +; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v36, off, s32 offset:32 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v36, off, s32 offset:28 +; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v37, off, s32 offset:24 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v37, off, s32 offset:20 +; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v38, off, s32 offset:16 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v38, off, s32 offset:12 +; GFX11-TRUE16-NEXT: scratch_load_d16_u8 v39, off, s32 offset:8 +; GFX11-TRUE16-NEXT: scratch_load_d16_hi_u8 v39, off, s32 offset:4 ; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(16) @@ -4168,53 +4166,45 @@ define void @void_func_v32i32_v16i8(<32 x i32> %arg0, <16 x i8> %arg1) #0 { ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(15) -; GFX11-TRUE16-NEXT: buffer_store_b8 v32, off, s[0:3], 0 dlc -; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(14) -; GFX11-TRUE16-NEXT: buffer_store_b8 v33, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v32, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13) -; GFX11-TRUE16-NEXT: buffer_store_b8 v34, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v32, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12) -; GFX11-TRUE16-NEXT: buffer_store_b8 v35, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v33, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11) -; GFX11-TRUE16-NEXT: buffer_store_b8 v36, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v33, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10) -; GFX11-TRUE16-NEXT: buffer_store_b8 v37, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v34, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(9) -; GFX11-TRUE16-NEXT: buffer_store_b8 v38, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v34, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8) -; GFX11-TRUE16-NEXT: buffer_store_b8 v39, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v35, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7) -; GFX11-TRUE16-NEXT: buffer_store_b8 v48, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v35, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6) -; GFX11-TRUE16-NEXT: buffer_store_b8 v49, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v36, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5) -; GFX11-TRUE16-NEXT: buffer_store_b8 v50, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v36, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(4) -; GFX11-TRUE16-NEXT: buffer_store_b8 v51, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v37, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3) -; GFX11-TRUE16-NEXT: buffer_store_b8 v52, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v37, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2) -; GFX11-TRUE16-NEXT: buffer_store_b8 v53, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v38, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-TRUE16-NEXT: buffer_store_b8 v54, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v38, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_store_b8 v55, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: buffer_store_b8 v39, off, s[0:3], 0 dlc +; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v39, off, s[0:3], 0 dlc ; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; diff --git a/llvm/test/CodeGen/AMDGPU/function-returns.ll b/llvm/test/CodeGen/AMDGPU/function-returns.ll index 4add34dd7d956..a7665ee31e608 100644 --- a/llvm/test/CodeGen/AMDGPU/function-returns.ll +++ b/llvm/test/CodeGen/AMDGPU/function-returns.ll @@ -84,14 +84,23 @@ define i8 @i8_func_void() #0 { ; GFX789-NEXT: s_waitcnt vmcnt(0) ; GFX789-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-LABEL: i8_func_void: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 -; GFX11-NEXT: s_mov_b32 s2, -1 -; GFX11-NEXT: buffer_load_u8 v0, off, s[0:3], 0 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: i8_func_void: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX11-TRUE16-NEXT: buffer_load_d16_u8 v0, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: i8_func_void: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX11-FAKE16-NEXT: buffer_load_u8 v0, off, s[0:3], 0 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %val = load i8, ptr addrspace(1) poison ret i8 %val } @@ -150,14 +159,23 @@ define i16 @i16_func_void() #0 { ; GFX789-NEXT: s_waitcnt vmcnt(0) ; GFX789-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-LABEL: i16_func_void: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 -; GFX11-NEXT: s_mov_b32 s2, -1 -; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: i16_func_void: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: i16_func_void: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[0:3], 0 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %val = load i16, ptr addrspace(1) poison ret i16 %val } @@ -1164,16 +1182,27 @@ define {i8, i32} @struct_i8_i32_func_void() #0 { ; GFX789-NEXT: s_waitcnt vmcnt(0) ; GFX789-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-LABEL: struct_i8_i32_func_void: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 -; GFX11-NEXT: s_mov_b32 s2, -1 -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: buffer_load_u8 v0, off, s[0:3], 0 -; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: struct_i8_i32_func_void: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: buffer_load_d16_u8 v0, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: buffer_load_b32 v1, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: struct_i8_i32_func_void: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: buffer_load_u8 v0, off, s[0:3], 0 +; GFX11-FAKE16-NEXT: buffer_load_b32 v1, off, s[0:3], 0 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %val = load { i8, i32 }, ptr addrspace(1) poison ret { i8, i32 } %val } @@ -1193,19 +1222,33 @@ define void @void_func_sret_struct_i8_i32(ptr addrspace(5) sret({ i8, i32 }) %ar ; GFX789-NEXT: s_waitcnt vmcnt(0) ; GFX789-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-LABEL: void_func_sret_struct_i8_i32: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 -; GFX11-NEXT: s_mov_b32 s2, -1 -; GFX11-NEXT: buffer_load_u8 v1, off, s[0:3], 0 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: buffer_load_b32 v2, off, s[0:3], 0 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: scratch_store_b8 v0, v1, off -; GFX11-NEXT: scratch_store_b32 v0, v2, off offset:4 -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: void_func_sret_struct_i8_i32: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX11-TRUE16-NEXT: buffer_load_d16_u8 v1, off, s[0:3], 0 glc dlc +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: buffer_load_b32 v2, off, s[0:3], 0 glc dlc +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: s_clause 0x1 +; GFX11-TRUE16-NEXT: scratch_store_b8 v0, v1, off +; GFX11-TRUE16-NEXT: scratch_store_b32 v0, v2, off offset:4 +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: void_func_sret_struct_i8_i32: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX11-FAKE16-NEXT: buffer_load_u8 v1, off, s[0:3], 0 glc dlc +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: buffer_load_b32 v2, off, s[0:3], 0 glc dlc +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: s_clause 0x1 +; GFX11-FAKE16-NEXT: scratch_store_b8 v0, v1, off +; GFX11-FAKE16-NEXT: scratch_store_b32 v0, v2, off offset:4 +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %val0 = load volatile i8, ptr addrspace(1) poison %val1 = load volatile i32, ptr addrspace(1) poison %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %arg0, i32 0, i32 0 @@ -2268,14 +2311,23 @@ define bfloat @bf16_func_void() #0 { ; GFX789-NEXT: s_waitcnt vmcnt(0) ; GFX789-NEXT: s_setpc_b64 s[30:31] ; -; GFX11-LABEL: bf16_func_void: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 -; GFX11-NEXT: s_mov_b32 s2, -1 -; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX11-TRUE16-LABEL: bf16_func_void: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[0:3], 0 +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-FAKE16-LABEL: bf16_func_void: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 +; GFX11-FAKE16-NEXT: buffer_load_u16 v0, off, s[0:3], 0 +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] %val = load bfloat, ptr addrspace(1) poison ret bfloat %val } diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir new file mode 100644 index 0000000000000..29bfeb8fa1bd1 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir @@ -0,0 +1,170 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs -start-before machine-scheduler -stop-after amdgpu-wait-sgpr-hazards -o - %s | FileCheck -check-prefix=GFX11 %s + +# The following loop should only require a single s_waitcnt_depctr +--- +name: gemm_loop1 +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true +body: | + ; GFX11-LABEL: name: gemm_loop1 + ; GFX11: bb.0: + ; GFX11-NEXT: successors: %bb.1(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: renamable $vgpr0 = V_MOV_B32_e32 0, implicit $exec + ; GFX11-NEXT: renamable $vgpr1 = V_MOV_B32_e32 0, implicit $exec + ; GFX11-NEXT: renamable $vgpr2 = V_MOV_B32_e32 0, implicit $exec + ; GFX11-NEXT: renamable $vgpr3 = V_MOV_B32_e32 0, implicit $exec + ; GFX11-NEXT: renamable $vgpr4 = V_MOV_B32_e32 0, implicit $exec + ; GFX11-NEXT: renamable $sgpr8 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr9 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr10 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr11 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr12 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr13 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr14 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr15 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr16 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr17 = S_MOV_B32 0 + ; GFX11-NEXT: renamable $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF + ; GFX11-NEXT: renamable $sgpr4_sgpr5_sgpr6_sgpr7 = IMPLICIT_DEF + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.1: + ; GFX11-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: liveins: $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: renamable $vgpr5 = V_ADD_U32_e32 $sgpr17, $vgpr0, implicit $exec + ; GFX11-NEXT: renamable $sgpr17 = S_ADDK_I32 killed renamable $sgpr17, 128, implicit-def dead $scc + ; GFX11-NEXT: S_CMP_LT_U32 renamable $sgpr17, renamable $sgpr15, implicit-def $scc + ; GFX11-NEXT: renamable $sgpr17 = S_CSELECT_B32 killed renamable $sgpr17, 0, implicit killed $scc + ; GFX11-NEXT: renamable $vgpr7 = V_ADD_U32_e32 64, $vgpr5, implicit $exec + ; GFX11-NEXT: renamable $sgpr18_sgpr19 = V_CMP_GT_U32_e64 $sgpr15, $vgpr5, implicit $exec + ; GFX11-NEXT: S_WAITCNT_DEPCTR .VaSdst_0 + ; GFX11-NEXT: renamable $vgpr6 = V_ADD_U32_e32 $sgpr8, $vgpr5, implicit $exec + ; GFX11-NEXT: renamable $vgpr8 = V_ADD_U32_e32 $sgpr9, killed $vgpr5, implicit $exec + ; GFX11-NEXT: renamable $sgpr16 = nsw S_ADD_I32 killed renamable $sgpr16, -1, implicit-def dead $scc + ; GFX11-NEXT: renamable $sgpr20_sgpr21 = V_CMP_GT_U32_e64 $sgpr15, $vgpr7, implicit $exec + ; GFX11-NEXT: S_WAITCNT_DEPCTR .VaSdst_0 + ; GFX11-NEXT: S_CMP_LG_U32 renamable $sgpr16, 0, implicit-def $scc + ; GFX11-NEXT: renamable $vgpr5 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr6, $sgpr18_sgpr19, implicit $exec + ; GFX11-NEXT: renamable $vgpr6 = V_ADD_U32_e32 $sgpr8, $vgpr7, implicit $exec + ; GFX11-NEXT: renamable $vgpr7 = V_ADD_U32_e32 $sgpr9, killed $vgpr7, implicit $exec + ; GFX11-NEXT: renamable $vgpr8 = V_CNDMASK_B32_e64 0, $sgpr10, 0, killed $vgpr8, killed $sgpr18_sgpr19, implicit $exec + ; GFX11-NEXT: renamable $vgpr6 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr6, $sgpr20_sgpr21, implicit $exec + ; GFX11-NEXT: renamable $vgpr7 = V_CNDMASK_B32_e64 0, $sgpr10, 0, killed $vgpr7, killed $sgpr20_sgpr21, implicit $exec + ; GFX11-NEXT: renamable $vgpr9 = V_ADD_U32_e32 $sgpr11, $vgpr8, implicit $exec + ; GFX11-NEXT: renamable $vgpr10 = V_ADD_U32_e32 $sgpr12, $vgpr8, implicit $exec + ; GFX11-NEXT: renamable $vgpr11 = V_ADD_U32_e32 $sgpr13, $vgpr8, implicit $exec + ; GFX11-NEXT: renamable $vgpr8 = V_ADD_U32_e32 $sgpr14, killed $vgpr8, implicit $exec + ; GFX11-NEXT: renamable $vgpr12 = V_ADD_U32_e32 $sgpr11, $vgpr7, implicit $exec + ; GFX11-NEXT: renamable $vgpr13 = V_ADD_U32_e32 $sgpr12, $vgpr7, implicit $exec + ; GFX11-NEXT: renamable $vgpr14 = V_ADD_U32_e32 $sgpr13, $vgpr7, implicit $exec + ; GFX11-NEXT: renamable $vgpr7 = V_ADD_U32_e32 $sgpr14, killed $vgpr7, implicit $exec + ; GFX11-NEXT: BUNDLE implicit-def $vgpr5, implicit-def $vgpr6, implicit killed $vgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec, implicit killed $vgpr6 :: (dereferenceable invariant load (s16), align 1, addrspace 8) { + ; GFX11-NEXT: S_CLAUSE 1 + ; GFX11-NEXT: renamable $vgpr5 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr5, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: renamable $vgpr6 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr6, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: } + ; GFX11-NEXT: BUNDLE implicit-def $vgpr9, implicit-def $vgpr10, implicit-def $vgpr11, implicit-def $vgpr8, implicit-def $vgpr12, implicit-def $vgpr13, implicit-def $vgpr14, implicit-def $vgpr7, implicit killed $vgpr9, implicit $sgpr4_sgpr5_sgpr6_sgpr7, implicit $exec, implicit killed $vgpr10, implicit killed $vgpr11, implicit killed $vgpr8, implicit killed $vgpr12, implicit killed $vgpr13, implicit killed $vgpr14, implicit killed $vgpr7 :: (dereferenceable invariant load (s16), align 1, addrspace 8) { + ; GFX11-NEXT: S_CLAUSE 7 + ; GFX11-NEXT: renamable $vgpr9 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr9, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: renamable $vgpr10 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr10, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: renamable $vgpr11 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr11, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: renamable $vgpr8 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr8, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: renamable $vgpr12 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr12, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: renamable $vgpr13 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr13, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: renamable $vgpr14 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr14, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: renamable $vgpr7 = BUFFER_LOAD_USHORT_IDXEN killed renamable $vgpr7, renamable $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + ; GFX11-NEXT: } + ; GFX11-NEXT: S_WAITCNT 9207 + ; GFX11-NEXT: renamable $vgpr5 = V_PERM_B32_e64 killed $vgpr6, killed $vgpr5, 84148480, implicit $exec + ; GFX11-NEXT: S_WAITCNT 4087 + ; GFX11-NEXT: renamable $vgpr6 = V_PERM_B32_e64 killed $vgpr12, killed $vgpr9, 84148480, implicit $exec + ; GFX11-NEXT: S_WAITCNT 3063 + ; GFX11-NEXT: renamable $vgpr9 = V_PERM_B32_e64 killed $vgpr13, killed $vgpr10, 84148480, implicit $exec + ; GFX11-NEXT: S_WAITCNT 2039 + ; GFX11-NEXT: renamable $vgpr10 = V_PERM_B32_e64 killed $vgpr14, killed $vgpr11, 84148480, implicit $exec + ; GFX11-NEXT: S_WAITCNT 1015 + ; GFX11-NEXT: renamable $vgpr7 = V_PERM_B32_e64 killed $vgpr7, killed $vgpr8, 84148480, implicit $exec + ; GFX11-NEXT: renamable $vgpr1 = nofpexcept V_DOT2_F32_F16 8, $vgpr5, 8, killed $vgpr6, 8, killed $vgpr1, -1, 0, 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: renamable $vgpr2 = nofpexcept V_DOT2_F32_F16 8, $vgpr5, 8, killed $vgpr9, 8, killed $vgpr2, -1, 0, 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: renamable $vgpr3 = nofpexcept V_DOT2_F32_F16 8, $vgpr5, 8, killed $vgpr10, 8, killed $vgpr3, -1, 0, 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: renamable $vgpr4 = nofpexcept V_DOT2_F32_F16 8, killed $vgpr5, 8, killed $vgpr7, 8, killed $vgpr4, -1, 0, 0, 0, 0, implicit $mode, implicit $exec + ; GFX11-NEXT: S_CBRANCH_SCC1 %bb.1, implicit killed $scc + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: S_ENDPGM 0 + bb.0: + %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %1:sreg_32 = S_MOV_B32 0 + %2:sreg_32 = S_MOV_B32 0 + %3:sreg_32 = S_MOV_B32 0 + %4:sgpr_128 = IMPLICIT_DEF + %5:sreg_32 = S_MOV_B32 0 + %6:sgpr_128 = IMPLICIT_DEF + %7:sreg_32 = S_MOV_B32 0 + %8:sreg_32 = S_MOV_B32 0 + %9:sreg_32 = S_MOV_B32 0 + %10:sgpr_32 = S_MOV_B32 0 + %11:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %13:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %15:sreg_32 = S_MOV_B32 0 + %16:sreg_32 = S_MOV_B32 0 + S_BRANCH %bb.1 + + bb.1: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + + %17:vgpr_32 = V_ADD_U32_e64 %16, %0, 0, implicit $exec + %18:vgpr_32 = V_ADD_U32_e64 %1, %17, 0, implicit $exec + %19:sreg_64_xexec = V_CMP_GT_U32_e64 %10, %17, implicit $exec + %20:vgpr_32 = V_CNDMASK_B32_e64 0, -1, 0, %18, %19, implicit $exec + %21:vgpr_32 = V_ADD_U32_e64 %2, %17, 0, implicit $exec + %22:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %21, %19, implicit $exec + %23:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %20, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %24:vgpr_32 = V_ADD_U32_e64 %5, %22, 0, implicit $exec + %25:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %24, %6, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %26:vgpr_32 = V_ADD_U32_e64 %7, %22, 0, implicit $exec + %27:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %26, %6, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %28:vgpr_32 = V_ADD_U32_e64 %8, %22, 0, implicit $exec + %29:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %28, %6, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %30:vgpr_32 = V_ADD_U32_e64 %9, %22, 0, implicit $exec + %31:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %30, %6, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %32:vgpr_32 = V_ADD_U32_e64 64, %17, 0, implicit $exec + %33:vgpr_32 = V_ADD_U32_e64 %1, %32, 0, implicit $exec + %34:sreg_64_xexec = V_CMP_GT_U32_e64 %10, %32, implicit $exec + %35:vgpr_32 = V_CNDMASK_B32_e64 0, -1, 0, %33, %34, implicit $exec + %36:vgpr_32 = V_ADD_U32_e64 %2, %32, 0, implicit $exec + %37:vgpr_32 = V_CNDMASK_B32_e64 0, %3, 0, %36, %34, implicit $exec + %38:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %35, %4, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %39:vgpr_32 = V_ADD_U32_e64 %5, %37, 0, implicit $exec + %40:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %39, %6, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %41:vgpr_32 = V_ADD_U32_e64 %7, %37, 0, implicit $exec + %42:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %41, %6, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %43:vgpr_32 = V_ADD_U32_e64 %8, %37, 0, implicit $exec + %44:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %43, %6, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %45:vgpr_32 = V_ADD_U32_e64 %9, %37, 0, implicit $exec + %46:vgpr_32 = BUFFER_LOAD_USHORT_IDXEN %45, %6, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s16), align 1, addrspace 8) + %47:vgpr_32 = V_PERM_B32_e64 %38, %23, 84148480, implicit $exec + %48:vgpr_32 = V_PERM_B32_e64 %40, %25, 84148480, implicit $exec + %11:vgpr_32 = nofpexcept V_DOT2_F32_F16 8, %47, 8, %48, 8, %11, -1, 0, 0, 0, 0, implicit $mode, implicit $exec + %49:vgpr_32 = V_PERM_B32_e64 %42, %27, 84148480, implicit $exec + %12:vgpr_32 = nofpexcept V_DOT2_F32_F16 8, %47, 8, %49, 8, %12, -1, 0, 0, 0, 0, implicit $mode, implicit $exec + %50:vgpr_32 = V_PERM_B32_e64 %44, %29, 84148480, implicit $exec + %13:vgpr_32 = nofpexcept V_DOT2_F32_F16 8, %47, 8, %50, 8, %13, -1, 0, 0, 0, 0, implicit $mode, implicit $exec + %51:vgpr_32 = V_PERM_B32_e64 %46, %31, 84148480, implicit $exec + %14:vgpr_32 = nofpexcept V_DOT2_F32_F16 8, %47, 8, %51, 8, %14, -1, 0, 0, 0, 0, implicit $mode, implicit $exec + %52:sreg_32 = S_ADD_I32 %16, 128, implicit-def dead $scc + S_CMP_LT_U32 %52, %10, implicit-def $scc + %16:sreg_32 = S_CSELECT_B32 %52, 0, implicit killed $scc + %15:sreg_32 = nsw S_ADD_I32 %15, -1, implicit-def dead $scc + S_CMP_LG_U32 %15, 0, implicit-def $scc + S_CBRANCH_SCC1 %bb.1, implicit killed $scc + S_BRANCH %bb.2 + + bb.2: + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll index 6b02e6b05f1b7..ab242eba6f19b 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll @@ -74,6 +74,6 @@ define amdgpu_kernel void @global_atomic_fadd_noret_f32_wrong_subtarget(ptr addr ret void } -attributes #1 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-cpu"="gfx803" "target-features"="+atomic-fadd-no-rtn-insts" } +attributes #1 = { denormal_fpenv(float: preservesign) "target-cpu"="gfx803" "target-features"="+atomic-fadd-no-rtn-insts" } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll index 4b7e08f814b5b..864df0eda1e49 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll @@ -48,6 +48,7 @@ define float @global_agent_atomic_fadd_ret_f32__amdgpu_no_fine_grained_memory(pt ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -245,6 +246,7 @@ define float @global_agent_atomic_fadd_ret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -444,6 +446,7 @@ define float @global_agent_atomic_fadd_ret_f32__offset12b_neg__amdgpu_no_fine_gr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -653,6 +656,7 @@ define void @global_agent_atomic_fadd_noret_f32__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -844,6 +848,7 @@ define void @global_agent_atomic_fadd_noret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1038,6 +1043,7 @@ define void @global_agent_atomic_fadd_noret_f32__offset12b_neg__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:-2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1241,6 +1247,7 @@ define float @global_system_atomic_fadd_ret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1290,6 +1297,7 @@ define float @global_system_atomic_fadd_ret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_add_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1443,6 +1451,7 @@ define void @global_system_atomic_fadd_noret_f32__offset12b_pos__amdgpu_no_fine_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1491,6 +1500,7 @@ define void @global_system_atomic_fadd_noret_f32__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_add_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1639,6 +1649,7 @@ define float @global_agent_atomic_fadd_ret_f32_maybe_remote(ptr addrspace(1) %pt ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1854,6 +1865,7 @@ define float @global_agent_atomic_fadd_ret_f32_maybe_remote__amdgpu_ignore_denor ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2069,6 +2081,7 @@ define void @global_agent_atomic_fadd_noret_f32_maybe_remote__amdgpu_ignore_deno ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2277,6 +2290,7 @@ define float @global_agent_atomic_fadd_ret_f32___amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2476,6 +2490,7 @@ define float @global_agent_atomic_fadd_ret_f32___amdgpu_no_fine_grained_memory__ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2661,6 +2676,7 @@ define float @global_agent_atomic_fadd_ret_f32_amdgpu_ignore_denormal_mode(ptr a ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2876,6 +2892,7 @@ define void @global_agent_atomic_fadd_noret_f32_maybe_remote(ptr addrspace(1) %p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3084,6 +3101,7 @@ define void @global_agent_atomic_fadd_noret_f32___amdgpu_no_fine_grained_memory( ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3278,6 +3296,7 @@ define void @global_agent_atomic_fadd_noret_f32___amdgpu_no_fine_grained_memory_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3446,6 +3465,7 @@ define void @global_agent_atomic_fadd_noret_f32_amdgpu_ignore_denormal_mode(ptr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3654,6 +3674,7 @@ define float @global_agent_atomic_fadd_ret_f32__amdgpu_no_remote_memory(ptr addr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3867,6 +3888,7 @@ define void @global_agent_atomic_fadd_noret_f32__amdgpu_no_remote_memory(ptr add ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4072,6 +4094,7 @@ define float @global_agent_atomic_fadd_ret_f32__amdgpu_no_remote_memory__amdgpu_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4285,6 +4308,7 @@ define void @global_agent_atomic_fadd_noret_f32__amdgpu_no_remote_memory__amdgpu ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4490,6 +4514,7 @@ define float @global_agent_atomic_fadd_ret_f32__amdgpu_no_remote_memory__amdgpu_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4687,6 +4712,7 @@ define void @global_agent_atomic_fadd_noret_f32__amdgpu_no_remote_memory__amdgpu ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4882,6 +4908,7 @@ define float @global_agent_atomic_fadd_ret_f32__ftz__amdgpu_no_fine_grained_memo ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5065,6 +5092,7 @@ define float @global_agent_atomic_fadd_ret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5250,6 +5278,7 @@ define float @global_agent_atomic_fadd_ret_f32__offset12b_neg__ftz__amdgpu_no_fi ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5445,6 +5474,7 @@ define void @global_agent_atomic_fadd_noret_f32__ftz__amdgpu_no_fine_grained_mem ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5610,6 +5640,7 @@ define void @global_agent_atomic_fadd_noret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5778,6 +5809,7 @@ define void @global_agent_atomic_fadd_noret_f32__offset12b_neg__ftz__amdgpu_no_f ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:-2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5955,6 +5987,7 @@ define float @global_system_atomic_fadd_ret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -5998,6 +6031,7 @@ define float @global_system_atomic_fadd_ret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -6143,6 +6177,7 @@ define void @global_system_atomic_fadd_noret_f32__offset12b_pos__ftz__amdgpu_no_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -6185,6 +6220,7 @@ define void @global_system_atomic_fadd_noret_f32__offset12b_pos__ftz__amdgpu_no_ ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -6313,6 +6349,7 @@ define float @global_agent_atomic_fadd_ret_f32__offset12b_pos__ieee__amdgpu_no_f ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6498,6 +6535,7 @@ define void @global_agent_atomic_fadd_noret_f32__offset12b_pos__ieee__amdgpu_no_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6666,6 +6704,7 @@ define float @global_agent_atomic_fadd_ret_f32__ftz__amdgpu_no_remote_memory(ptr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6879,6 +6918,7 @@ define void @global_agent_atomic_fadd_noret_f32__ftz__amdgpu_no_remote_memory(pt ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7084,6 +7124,7 @@ define float @global_agent_atomic_fadd_ret_f32__ftz__amdgpu_no_fine_grained_memo ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7267,6 +7308,7 @@ define void @global_agent_atomic_fadd_noret_f32__ftz__amdgpu_no_fine_grained_mem ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f32 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7453,6 +7495,7 @@ define double @global_agent_atomic_fadd_ret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7687,6 +7730,7 @@ define double @global_agent_atomic_fadd_ret_f64__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off offset:2040 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7922,6 +7966,7 @@ define double @global_agent_atomic_fadd_ret_f64__offset12b_neg__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8159,6 +8204,7 @@ define void @global_agent_atomic_fadd_noret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[2:3], off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8375,6 +8421,7 @@ define void @global_agent_atomic_fadd_noret_f64__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[2:3], off offset:2040 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8594,6 +8641,7 @@ define void @global_agent_atomic_fadd_noret_f64__offset12b_neg__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_add_f64 v[0:1], v[2:3], off offset:-2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8975,6 +9023,7 @@ define half @global_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9483,6 +9532,7 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10003,6 +10053,7 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10510,6 +10561,7 @@ define void @global_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11002,6 +11054,7 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11506,6 +11559,7 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11957,6 +12011,7 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__align4__amdgpu_no_ ; GFX942-NEXT: v_add_f16_e32 v3, v5, v2 ; GFX942-NEXT: v_and_or_b32 v4, v5, s2, v3 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12335,6 +12390,7 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b__align4_pos__amdgpu_n ; GFX942-NEXT: v_add_f16_e32 v3, v5, v2 ; GFX942-NEXT: v_and_or_b32 v4, v5, s2, v3 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12768,6 +12824,7 @@ define half @global_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -12917,6 +12974,7 @@ define half @global_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX90A-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13283,6 +13341,7 @@ define void @global_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13427,6 +13486,7 @@ define void @global_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX90A-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13614,21 +13674,17 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory( ; GFX1250-TRUE16-NEXT: v_not_b32_e32 v4, v4 ; GFX1250-TRUE16-NEXT: .LBB54_1: ; %atomicrmw.start ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, 0 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v7, v5 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v7 -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v5, v5, v6 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v5, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v6 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_and_or_b32 v6, v7, v4, v5 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_DEV @@ -13652,7 +13708,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory( ; GFX1250-FAKE16: ; %bb.0: ; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_lshlrev_b32 v2, 16, v2 +; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v0 ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3 @@ -13668,14 +13724,12 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory( ; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v7 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v5, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2 ; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_or_b32 v6, v7, v4, v5 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_DEV @@ -13833,6 +13887,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__amdgpu_no_fine_grained_memory( ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14211,21 +14266,17 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX1250-TRUE16-NEXT: v_not_b32_e32 v4, v4 ; GFX1250-TRUE16-NEXT: .LBB55_1: ; %atomicrmw.start ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, 0 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v7, v5 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v7 -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v5, v5, v6 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v5, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v6 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_and_or_b32 v6, v7, v4, v5 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_DEV @@ -14251,13 +14302,13 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1] ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-FAKE16-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_bitop2_b32 v3, 3, v4 bitop3:0x40 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4 ; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_not_b32_e32 v4, v4 ; GFX1250-FAKE16-NEXT: .LBB55_1: ; %atomicrmw.start ; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -14265,14 +14316,12 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v7 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v5, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2 ; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_or_b32 v6, v7, v4, v5 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_DEV @@ -14436,6 +14485,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14826,21 +14876,17 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX1250-TRUE16-NEXT: v_not_b32_e32 v4, v4 ; GFX1250-TRUE16-NEXT: .LBB56_1: ; %atomicrmw.start ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, 0 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v7, v5 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v7 -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v5, v5, v6 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v5, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v6 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_and_or_b32 v6, v7, v4, v5 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_DEV @@ -14865,16 +14911,15 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-FAKE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 ; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4 ; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_not_b32_e32 v4, v4 ; GFX1250-FAKE16-NEXT: .LBB56_1: ; %atomicrmw.start ; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -14882,14 +14927,12 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v7 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v5, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2 ; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_or_b32 v6, v7, v4, v5 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_DEV @@ -15054,6 +15097,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15445,17 +15489,14 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory( ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v3, v5 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v4, v4, v7 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, 0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v4, v4, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l ; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v3, v7 +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_DEV @@ -15479,7 +15520,7 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory( ; GFX1250-FAKE16: ; %bb.0: ; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v3, v0 :: v_dual_lshlrev_b32 v2, 16, v2 +; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v0 ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, -4, v3 @@ -15494,13 +15535,12 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory( ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v3, v5 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v4, v4, v2 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v4, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 -; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v3, v4 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_DEV @@ -15654,6 +15694,7 @@ define void @global_agent_atomic_fadd_noret_bf16__amdgpu_no_fine_grained_memory( ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16011,41 +16052,39 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1] +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l ; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 -; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v4 -; GFX1250-TRUE16-NEXT: global_load_b32 v5, v[0:1], off -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff +; GFX1250-TRUE16-NEXT: v_and_b32_e32 v4, 3, v4 +; GFX1250-TRUE16-NEXT: global_load_b32 v3, v[0:1], off +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4 +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_not_b32_e32 v6, v4 +; GFX1250-TRUE16-NEXT: v_not_b32_e32 v5, v5 ; GFX1250-TRUE16-NEXT: .LBB58_1: ; %atomicrmw.start ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v3, v5 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v4, v4, v7 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l +; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, 0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v2, v2, 1.0, v6 op_sel_hi:[1,1,1] +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v3, v7 -; GFX1250-TRUE16-NEXT: v_and_or_b32 v4, v5, v6, v4 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v2, v4, v7 +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 -; GFX1250-TRUE16-NEXT: global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX1250-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v5 -; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v5, v4 +; GFX1250-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v3, v2 ; GFX1250-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 @@ -16060,37 +16099,36 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1] ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-FAKE16-NEXT: v_dual_lshlrev_b32 v6, 16, v2 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 -; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v4, 3, v4 bitop3:0x40 -; GFX1250-FAKE16-NEXT: global_load_b32 v3, v[0:1], off -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff -; GFX1250-FAKE16-NEXT: v_not_b32_e32 v5, v5 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4 +; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_not_b32_e32 v6, v4 ; GFX1250-FAKE16-NEXT: .LBB58_1: ; %atomicrmw.start ; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v2, v2, v6 +; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v3, v5 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 -; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v4, 1.0, v2 op_sel_hi:[1,1,1] +; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2 -; GFX1250-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v3, v4 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 -; GFX1250-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX1250-FAKE16-NEXT: global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v2 +; GFX1250-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v5 +; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v5, v4 ; GFX1250-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 @@ -16239,6 +16277,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16607,42 +16646,40 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-TRUE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l ; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0 +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 -; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v4 -; GFX1250-TRUE16-NEXT: global_load_b32 v5, v[0:1], off -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff -; GFX1250-TRUE16-NEXT: v_not_b32_e32 v6, v4 +; GFX1250-TRUE16-NEXT: v_and_b32_e32 v4, 3, v4 +; GFX1250-TRUE16-NEXT: global_load_b32 v3, v[0:1], off +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4 +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_not_b32_e32 v5, v5 ; GFX1250-TRUE16-NEXT: .LBB59_1: ; %atomicrmw.start ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v3, v5 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v4, v4, v7 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l +; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, 0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v2, v2, 1.0, v6 op_sel_hi:[1,1,1] +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v3, v7 -; GFX1250-TRUE16-NEXT: v_and_or_b32 v4, v5, v6, v4 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v2, v4, v7 +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 -; GFX1250-TRUE16-NEXT: global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX1250-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v5 -; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v5, v4 +; GFX1250-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v3, v2 ; GFX1250-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 @@ -16656,40 +16693,38 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-FAKE16-NEXT: s_mov_b64 s[0:1], 0xfffffffffffff800 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v2 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 -; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4 -; GFX1250-FAKE16-NEXT: global_load_b32 v3, v[0:1], off -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_not_b32_e32 v5, v5 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4 +; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff +; GFX1250-FAKE16-NEXT: v_not_b32_e32 v6, v4 ; GFX1250-FAKE16-NEXT: .LBB59_1: ; %atomicrmw.start ; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v2, v2, v6 +; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v3, v5 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 -; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v4, 1.0, v2 op_sel_hi:[1,1,1] +; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2 -; GFX1250-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v3, v4 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 -; GFX1250-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX1250-FAKE16-NEXT: global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v2 +; GFX1250-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v5 +; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v5, v4 ; GFX1250-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 @@ -16839,6 +16874,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17212,17 +17248,13 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_ ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v5, v3 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5 -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v4, v4, v3 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.h, v3.l +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.h, 0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_and_or_b32 v4, 0xffff0000, v5, v3 +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v3, v5, 1.0, v2 op_sel_hi:[1,1,1] +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l +; GFX1250-TRUE16-NEXT: v_and_or_b32 v4, 0xffff0000, v5, v4 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 @@ -17246,19 +17278,16 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_ ; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 ; GFX1250-FAKE16-NEXT: .LBB60_1: ; %atomicrmw.start ; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v5, v3 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v5 -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v3, v3, v2 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v3, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_or_b32 v4, 0xffff0000, v5, v3 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_DEV @@ -17388,6 +17417,7 @@ define bfloat @global_agent_atomic_fadd_ret_bf16__offset12b_pos__align4__amdgpu_ ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17695,31 +17725,29 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_ ; GFX1250-TRUE16: ; %bb.0: ; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250-TRUE16-NEXT: global_load_b32 v5, v[0:1], off offset:2046 +; GFX1250-TRUE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l ; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0 ; GFX1250-TRUE16-NEXT: .LBB61_1: ; %atomicrmw.start ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.h, v2.l ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v4, v4, v3 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.h, v3.l -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v2, v3, 1.0, v4 op_sel_hi:[1,1,1] +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v5.h, 0 +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v4.l -; GFX1250-TRUE16-NEXT: v_and_or_b32 v4, 0xffff0000, v5, v3 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l +; GFX1250-TRUE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v5 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 -; GFX1250-TRUE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[4:5], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX1250-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 -; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v5, v3 +; GFX1250-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v3, v2 ; GFX1250-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 @@ -17732,29 +17760,27 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_ ; GFX1250-FAKE16: ; %bb.0: ; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 -; GFX1250-FAKE16-NEXT: global_load_b32 v3, v[0:1], off offset:2046 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2 +; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off offset:2046 ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 ; GFX1250-FAKE16-NEXT: .LBB61_1: ; %atomicrmw.start ; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v3, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v2, v2, v4 -; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX1250-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v3, v2 +; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v3, v3, s0 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_and_or_b32 v4, 0xffff0000, v5, v3 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 -; GFX1250-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX1250-FAKE16-NEXT: global_atomic_cmpswap_b32 v3, v[0:1], v[4:5], off offset:2046 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v2 +; GFX1250-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v5 +; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v5, v3 ; GFX1250-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 @@ -17869,6 +17895,7 @@ define void @global_agent_atomic_fadd_noret_bf16__offset12b__align4_pos__amdgpu_ ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18178,21 +18205,17 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX1250-TRUE16-NEXT: v_not_b32_e32 v4, v4 ; GFX1250-TRUE16-NEXT: .LBB62_1: ; %atomicrmw.start ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, 0 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v7, v5 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v5, v3, v7 -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v5, v5, v6 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.h, v6.l -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v5, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 ; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v5, v3, v6 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_and_or_b32 v6, v7, v4, v5 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_SYS @@ -18218,13 +18241,13 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1] ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-FAKE16-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_bitop2_b32 v3, 3, v4 bitop3:0x40 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4 ; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_not_b32_e32 v4, v4 ; GFX1250-FAKE16-NEXT: .LBB62_1: ; %atomicrmw.start ; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -18232,14 +18255,12 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v5, v3, v7 -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v5, v5, 1.0, v2 op_sel_hi:[1,1,1] ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v5, v5, v2 ; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v5, v5, s0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v5, v3, v5 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-FAKE16-NEXT: v_and_or_b32 v6, v7, v4, v5 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_SYS @@ -18405,6 +18426,7 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -18590,6 +18612,7 @@ define bfloat @global_system_atomic_fadd_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -18786,41 +18809,39 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine ; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1] +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l ; GFX1250-TRUE16-NEXT: s_mov_b32 s0, 0 -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 -; GFX1250-TRUE16-NEXT: v_and_b32_e32 v3, 3, v4 -; GFX1250-TRUE16-NEXT: global_load_b32 v5, v[0:1], off -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff +; GFX1250-TRUE16-NEXT: v_and_b32_e32 v4, 3, v4 +; GFX1250-TRUE16-NEXT: global_load_b32 v3, v[0:1], off +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4 +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_not_b32_e32 v6, v4 +; GFX1250-TRUE16-NEXT: v_not_b32_e32 v5, v5 ; GFX1250-TRUE16-NEXT: .LBB63_1: ; %atomicrmw.start ; GFX1250-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v4, v3, v5 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, 0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, v2.l -; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX1250-TRUE16-NEXT: v_add_f32_e32 v4, v4, v7 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, v7.l +; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.h, 0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 -; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX1250-TRUE16-NEXT: v_fma_mix_f32_bf16 v2, v2, 1.0, v6 op_sel_hi:[1,1,1] +; GFX1250-TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, v3, v7 -; GFX1250-TRUE16-NEXT: v_and_or_b32 v4, v5, v6, v4 +; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l +; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v2, v4, v7 +; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-TRUE16-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 -; GFX1250-TRUE16-NEXT: global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS +; GFX1250-TRUE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: global_inv scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v5 -; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v5, v4 +; GFX1250-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v3, v2 ; GFX1250-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 @@ -18835,37 +18856,36 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine ; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 ; GFX1250-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], 0x7fe, v[0:1] ; GFX1250-FAKE16-NEXT: s_mov_b32 s0, 0 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-FAKE16-NEXT: v_dual_lshlrev_b32 v6, 16, v2 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 -; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v4, 3, v4 bitop3:0x40 -; GFX1250-FAKE16-NEXT: global_load_b32 v3, v[0:1], off -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 3, v4 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v5, v4, 0xffff -; GFX1250-FAKE16-NEXT: v_not_b32_e32 v5, v5 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_bitop2_b32 v0, -4, v4 bitop3:0x40 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v3, 3, v4 +; GFX1250-FAKE16-NEXT: global_load_b32 v5, v[0:1], off +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 3, v3 +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e64 v4, v3, 0xffff +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_not_b32_e32 v6, v4 ; GFX1250-FAKE16-NEXT: .LBB63_1: ; %atomicrmw.start ; GFX1250-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v2, v4, v3 -; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX1250-FAKE16-NEXT: v_add_f32_e32 v2, v2, v6 +; GFX1250-FAKE16-NEXT: v_lshrrev_b32_e32 v4, v3, v5 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 -; GFX1250-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX1250-FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v4, 1.0, v2 op_sel_hi:[1,1,1] +; GFX1250-FAKE16-NEXT: v_cvt_pk_bf16_f32 v4, v4, s0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v2, v4, v2 -; GFX1250-FAKE16-NEXT: v_and_or_b32 v2, v3, v5, v2 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v4, v3, v4 +; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-FAKE16-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 -; GFX1250-FAKE16-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS +; GFX1250-FAKE16-NEXT: global_atomic_cmpswap_b32 v4, v[0:1], v[4:5], off th:TH_ATOMIC_RETURN scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: global_inv scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 -; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v3, v2 +; GFX1250-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v4, v5 +; GFX1250-FAKE16-NEXT: v_mov_b32_e32 v5, v4 ; GFX1250-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0 ; GFX1250-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 @@ -19016,6 +19036,7 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19195,6 +19216,7 @@ define void @global_system_atomic_fadd_noret_bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19414,6 +19436,7 @@ define <2 x half> @global_agent_atomic_fadd_ret_v2f16__amdgpu_no_fine_grained_me ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -19646,6 +19669,7 @@ define <2 x half> @global_agent_atomic_fadd_ret_v2f16__offset12b_pos__amdgpu_no_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -19880,6 +19904,7 @@ define <2 x half> @global_agent_atomic_fadd_ret_v2f16__offset12b_neg__amdgpu_no_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -20122,6 +20147,7 @@ define void @global_agent_atomic_fadd_noret_v2f16__amdgpu_no_fine_grained_memory ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -20330,6 +20356,7 @@ define void @global_agent_atomic_fadd_noret_v2f16__offset12b_pos__amdgpu_no_fine ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -20541,6 +20568,7 @@ define void @global_agent_atomic_fadd_noret_v2f16__offset12b_neg__amdgpu_no_fine ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off offset:-2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -20761,6 +20789,7 @@ define <2 x half> @global_system_atomic_fadd_ret_v2f16__offset12b_pos__amdgpu_no ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -20820,6 +20849,7 @@ define <2 x half> @global_system_atomic_fadd_ret_v2f16__offset12b_pos__amdgpu_no ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -20998,6 +21028,7 @@ define void @global_system_atomic_fadd_noret_v2f16__offset12b_pos__amdgpu_no_fin ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -21054,6 +21085,7 @@ define void @global_system_atomic_fadd_noret_v2f16__offset12b_pos__amdgpu_no_fin ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off offset:2044 ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -21211,6 +21243,7 @@ define <2 x half> @global_agent_atomic_fadd_ret_v2f16__amdgpu_no_remote_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -21457,6 +21490,7 @@ define void @global_agent_atomic_fadd_noret_v2f16__amdgpu_no_remote_memory(ptr a ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -21691,6 +21725,7 @@ define <2 x half> @global_agent_atomic_fadd_ret_v2f16__amdgpu_no_fine_grained_me ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -21923,6 +21958,7 @@ define void @global_agent_atomic_fadd_noret_v2f16__amdgpu_no_fine_grained_memory ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -22131,6 +22167,7 @@ define <2 x half> @global_agent_atomic_fadd_ret_v2f16__maybe_remote(ptr addrspac ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -22377,6 +22414,7 @@ define void @global_agent_atomic_fadd_noret_v2f16__maybe_remote(ptr addrspace(1) ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_f16 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -22615,6 +22653,7 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -23011,6 +23050,7 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v0, v[0:1], v2, off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -23409,6 +23449,7 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__offset12b_neg__amdgpu_ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v0, v[0:1], v2, off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -23815,6 +23856,7 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -24195,6 +24237,7 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fin ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v[0:1], v2, off offset:2044 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -24578,6 +24621,7 @@ define void @global_agent_atomic_fadd_noret_v2bf16__offset12b_neg__amdgpu_no_fin ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v[0:1], v2, off offset:-2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -24970,6 +25014,7 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v0, v[0:1], v2, off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -25139,6 +25184,7 @@ define <2 x bfloat> @global_system_atomic_fadd_ret_v2bf16__offset12b_pos__amdgpu ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -25371,6 +25417,7 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v[0:1], v2, off offset:2044 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -25535,6 +25582,7 @@ define void @global_system_atomic_fadd_noret_v2bf16__offset12b_pos__amdgpu_no_fi ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -25756,6 +25804,7 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_remote_memor ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -26152,6 +26201,7 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_remote_memory(ptr ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -26532,6 +26582,7 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__amdgpu_no_fine_grained ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -26928,6 +26979,7 @@ define void @global_agent_atomic_fadd_noret_v2bf16__amdgpu_no_fine_grained_memor ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -27308,6 +27360,7 @@ define <2 x bfloat> @global_agent_atomic_fadd_ret_v2bf16__maybe_remote(ptr addrs ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -27704,6 +27757,7 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1 ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_pk_add_bf16 v[0:1], v2, off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -28054,6 +28108,6 @@ define void @global_agent_atomic_fadd_noret_v2bf16__maybe_remote(ptr addrspace(1 } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll index 041a77c960f04..21762ff4222a9 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll @@ -41,6 +41,7 @@ define float @global_agent_atomic_fmax_ret_f32__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -202,6 +203,7 @@ define float @global_agent_atomic_fmax_ret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -365,6 +367,7 @@ define float @global_agent_atomic_fmax_ret_f32__offset12b_neg__amdgpu_no_fine_gr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -528,6 +531,7 @@ define void @global_agent_atomic_fmax_noret_f32__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -683,6 +687,7 @@ define void @global_agent_atomic_fmax_noret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -841,6 +846,7 @@ define void @global_agent_atomic_fmax_noret_f32__offset12b_neg__amdgpu_no_fine_g ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1000,6 +1006,7 @@ define float @global_system_atomic_fmax_ret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1045,6 +1052,7 @@ define float @global_system_atomic_fmax_ret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1166,6 +1174,7 @@ define void @global_system_atomic_fmax_noret_f32__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1210,6 +1219,7 @@ define void @global_system_atomic_fmax_noret_f32__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1326,6 +1336,7 @@ define float @global_agent_atomic_fmax_ret_f32__amdgpu_no_remote_memory(ptr addr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1556,6 +1567,7 @@ define float @global_agent_atomic_fmax_ret_f32__amdgpu_no_fine_grained_memory__a ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1721,6 +1733,7 @@ define float @global_agent_atomic_fmax_ret_f32__ftz__amdgpu_no_fine_grained_memo ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1882,6 +1895,7 @@ define float @global_agent_atomic_fmax_ret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2045,6 +2059,7 @@ define float @global_agent_atomic_fmax_ret_f32__offset12b_neg__ftz__amdgpu_no_fi ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2208,6 +2223,7 @@ define void @global_agent_atomic_fmax_noret_f32__ftz__amdgpu_no_fine_grained_mem ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2363,6 +2379,7 @@ define void @global_agent_atomic_fmax_noret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2521,6 +2538,7 @@ define void @global_agent_atomic_fmax_noret_f32__offset12b_neg__ftz__amdgpu_no_f ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2680,6 +2698,7 @@ define float @global_system_atomic_fmax_ret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2725,6 +2744,7 @@ define float @global_system_atomic_fmax_ret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2846,6 +2866,7 @@ define void @global_system_atomic_fmax_noret_f32__offset12b_pos__ftz__amdgpu_no_ ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2890,6 +2911,7 @@ define void @global_system_atomic_fmax_noret_f32__offset12b_pos__ftz__amdgpu_no_ ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_max_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3021,6 +3043,7 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3193,6 +3216,7 @@ define double @global_agent_atomic_fmax_ret_f64__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[0:1], v[2:3], off offset:2040 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3366,6 +3390,7 @@ define double @global_agent_atomic_fmax_ret_f64__offset12b_neg__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3538,6 +3563,7 @@ define void @global_agent_atomic_fmax_noret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[2:3], off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3700,6 +3726,7 @@ define void @global_agent_atomic_fmax_noret_f64__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[2:3], off offset:2040 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3865,6 +3892,7 @@ define void @global_agent_atomic_fmax_noret_f64__offset12b_neg__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[2:3], off offset:-2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4031,6 +4059,7 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_remote_memory(ptr add ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4278,6 +4307,7 @@ define double @global_agent_atomic_fmax_ret_f64__amdgpu_no_fine_grained_memory__ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_max_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4532,6 +4562,7 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4975,6 +5006,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5431,6 +5463,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5876,6 +5909,7 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6307,6 +6341,7 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6750,6 +6785,7 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7158,6 +7194,7 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__align4__amdgpu_no_ ; GFX942-NEXT: v_max_f16_e32 v2, v2, v4 ; GFX942-NEXT: v_and_or_b32 v2, v3, s2, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7494,6 +7531,7 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b__align4_pos__amdgpu_n ; GFX942-NEXT: v_max_f16_e32 v2, v2, v4 ; GFX942-NEXT: v_and_or_b32 v2, v3, s2, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7863,6 +7901,7 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -8023,6 +8062,7 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -8319,6 +8359,7 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -8474,6 +8515,7 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -8787,6 +8829,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__amdgpu_no_fine_grained_memory( ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9295,6 +9338,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9815,6 +9859,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10324,6 +10369,7 @@ define void @global_agent_atomic_fmax_noret_bf16__amdgpu_no_fine_grained_memory( ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10818,6 +10864,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11323,6 +11370,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11797,6 +11845,7 @@ define bfloat @global_agent_atomic_fmax_ret_bf16__offset12b_pos__align4__amdgpu_ ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12207,6 +12256,7 @@ define void @global_agent_atomic_fmax_noret_bf16__offset12b__align4_pos__amdgpu_ ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12647,6 +12697,7 @@ define bfloat @global_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -12832,6 +12883,7 @@ define bfloat @global_system_atomic_fmax_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13166,6 +13218,7 @@ define void @global_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13345,6 +13398,7 @@ define void @global_system_atomic_fmax_noret_bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13581,6 +13635,7 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__amdgpu_no_fine_grained_me ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -13862,6 +13917,7 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no_ ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14145,6 +14201,7 @@ define <2 x half> @global_agent_atomic_fmax_ret_v2f16__offset12b_neg__amdgpu_no_ ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14435,6 +14492,7 @@ define void @global_agent_atomic_fmax_noret_v2f16__amdgpu_no_fine_grained_memory ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14703,6 +14761,7 @@ define void @global_agent_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14974,6 +15033,7 @@ define void @global_agent_atomic_fmax_noret_v2f16__offset12b_neg__amdgpu_no_fine ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15255,6 +15315,7 @@ define <2 x half> @global_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15334,6 +15395,7 @@ define <2 x half> @global_system_atomic_fmax_ret_v2f16__offset12b_pos__amdgpu_no ; GFX90A-NEXT: v_pk_max_f16 v2, v3, v3 ; GFX90A-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15540,6 +15602,7 @@ define void @global_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fin ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15616,6 +15679,7 @@ define void @global_system_atomic_fmax_noret_v2f16__offset12b_pos__amdgpu_no_fin ; GFX90A-NEXT: v_pk_max_f16 v2, v3, v3 ; GFX90A-NEXT: v_pk_max_f16 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15905,6 +15969,7 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__amdgpu_no_fine_grained ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16411,6 +16476,7 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu_ ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16919,6 +16985,7 @@ define <2 x bfloat> @global_agent_atomic_fmax_ret_v2bf16__offset12b_neg__amdgpu_ ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17431,6 +17498,7 @@ define void @global_agent_atomic_fmax_noret_v2bf16__amdgpu_no_fine_grained_memor ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17916,6 +17984,7 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fin ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18404,6 +18473,7 @@ define void @global_agent_atomic_fmax_noret_v2bf16__offset12b_neg__amdgpu_no_fin ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18906,6 +18976,7 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19083,6 +19154,7 @@ define <2 x bfloat> @global_system_atomic_fmax_ret_v2bf16__offset12b_pos__amdgpu ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19414,6 +19486,7 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19585,6 +19658,7 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19776,6 +19850,6 @@ define void @global_system_atomic_fmax_noret_v2bf16__offset12b_pos__amdgpu_no_fi } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll index e13a16b762d6d..ea493405612d1 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll @@ -41,6 +41,7 @@ define float @global_agent_atomic_fmin_ret_f32__amdgpu_no_fine_grained_memory(pt ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -202,6 +203,7 @@ define float @global_agent_atomic_fmin_ret_f32__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -365,6 +367,7 @@ define float @global_agent_atomic_fmin_ret_f32__offset12b_neg__amdgpu_no_fine_gr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -528,6 +531,7 @@ define void @global_agent_atomic_fmin_noret_f32__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -683,6 +687,7 @@ define void @global_agent_atomic_fmin_noret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -841,6 +846,7 @@ define void @global_agent_atomic_fmin_noret_f32__offset12b_neg__amdgpu_no_fine_g ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1000,6 +1006,7 @@ define float @global_system_atomic_fmin_ret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1045,6 +1052,7 @@ define float @global_system_atomic_fmin_ret_f32__offset12b_pos__amdgpu_no_fine_g ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1166,6 +1174,7 @@ define void @global_system_atomic_fmin_noret_f32__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1210,6 +1219,7 @@ define void @global_system_atomic_fmin_noret_f32__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1326,6 +1336,7 @@ define float @global_agent_atomic_fmin_ret_f32__amdgpu_no_remote_memory(ptr addr ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1556,6 +1567,7 @@ define float @global_agent_atomic_fmin_ret_f32__amdgpu_no_fine_grained_memory__a ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1721,6 +1733,7 @@ define float @global_agent_atomic_fmin_ret_f32__ftz__amdgpu_no_fine_grained_memo ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1882,6 +1895,7 @@ define float @global_agent_atomic_fmin_ret_f32__offset12b_pos__ftz__amdgpu_no_fi ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2045,6 +2059,7 @@ define float @global_agent_atomic_fmin_ret_f32__offset12b_neg__ftz__amdgpu_no_fi ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2208,6 +2223,7 @@ define void @global_agent_atomic_fmin_noret_f32__ftz__amdgpu_no_fine_grained_mem ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2363,6 +2379,7 @@ define void @global_agent_atomic_fmin_noret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2521,6 +2538,7 @@ define void @global_agent_atomic_fmin_noret_f32__offset12b_neg__ftz__amdgpu_no_f ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2680,6 +2698,7 @@ define float @global_system_atomic_fmin_ret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2725,6 +2744,7 @@ define float @global_system_atomic_fmin_ret_f32__offset12b_pos__ftz__amdgpu_no_f ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -2846,6 +2866,7 @@ define void @global_system_atomic_fmin_noret_f32__offset12b_pos__ftz__amdgpu_no_ ; GFX942-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX942-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -2890,6 +2911,7 @@ define void @global_system_atomic_fmin_noret_f32__offset12b_pos__ftz__amdgpu_no_ ; GFX90A-NEXT: v_max_f32_e32 v2, v3, v3 ; GFX90A-NEXT: v_min_f32_e32 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3021,6 +3043,7 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3193,6 +3216,7 @@ define double @global_agent_atomic_fmin_ret_f64__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[0:1], v[2:3], off offset:2040 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3366,6 +3390,7 @@ define double @global_agent_atomic_fmin_ret_f64__offset12b_neg__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3538,6 +3563,7 @@ define void @global_agent_atomic_fmin_noret_f64__amdgpu_no_fine_grained_memory(p ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[2:3], off ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3700,6 +3726,7 @@ define void @global_agent_atomic_fmin_noret_f64__offset12b_pos__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[2:3], off offset:2040 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3865,6 +3892,7 @@ define void @global_agent_atomic_fmin_noret_f64__offset12b_neg__amdgpu_no_fine_g ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[2:3], off offset:-2048 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4031,6 +4059,7 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_remote_memory(ptr add ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4278,6 +4307,7 @@ define double @global_agent_atomic_fmin_ret_f64__amdgpu_no_fine_grained_memory__ ; GFX942: ; %bb.0: ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_min_f64 v[0:1], v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4532,6 +4562,7 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4975,6 +5006,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5431,6 +5463,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5876,6 +5909,7 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6307,6 +6341,7 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6750,6 +6785,7 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7158,6 +7194,7 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__align4__amdgpu_no_ ; GFX942-NEXT: v_min_f16_e32 v2, v2, v4 ; GFX942-NEXT: v_and_or_b32 v2, v3, s2, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7494,6 +7531,7 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b__align4_pos__amdgpu_n ; GFX942-NEXT: v_min_f16_e32 v2, v2, v4 ; GFX942-NEXT: v_and_or_b32 v2, v3, s2, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7863,6 +7901,7 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -8023,6 +8062,7 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr ; GFX90A-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -8319,6 +8359,7 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -8474,6 +8515,7 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_ ; GFX90A-NEXT: v_lshlrev_b32_e32 v2, v4, v2 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -8787,6 +8829,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__amdgpu_no_fine_grained_memory( ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9295,6 +9338,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9815,6 +9859,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10324,6 +10369,7 @@ define void @global_agent_atomic_fmin_noret_bf16__amdgpu_no_fine_grained_memory( ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10818,6 +10864,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11323,6 +11370,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b_neg__amdgpu_no_fine_ ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11797,6 +11845,7 @@ define bfloat @global_agent_atomic_fmin_ret_bf16__offset12b_pos__align4__amdgpu_ ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12207,6 +12256,7 @@ define void @global_agent_atomic_fmin_noret_bf16__offset12b__align4_pos__amdgpu_ ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12647,6 +12697,7 @@ define bfloat @global_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -12832,6 +12883,7 @@ define bfloat @global_system_atomic_fmin_ret_bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13166,6 +13218,7 @@ define void @global_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13345,6 +13398,7 @@ define void @global_system_atomic_fmin_noret_bf16__offset12b_pos__amdgpu_no_fine ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13581,6 +13635,7 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__amdgpu_no_fine_grained_me ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -13862,6 +13917,7 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no_ ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14145,6 +14201,7 @@ define <2 x half> @global_agent_atomic_fmin_ret_v2f16__offset12b_neg__amdgpu_no_ ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14435,6 +14492,7 @@ define void @global_agent_atomic_fmin_noret_v2f16__amdgpu_no_fine_grained_memory ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14703,6 +14761,7 @@ define void @global_agent_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fine ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14974,6 +15033,7 @@ define void @global_agent_atomic_fmin_noret_v2f16__offset12b_neg__amdgpu_no_fine ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15255,6 +15315,7 @@ define <2 x half> @global_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15334,6 +15395,7 @@ define <2 x half> @global_system_atomic_fmin_ret_v2f16__offset12b_pos__amdgpu_no ; GFX90A-NEXT: v_pk_max_f16 v2, v3, v3 ; GFX90A-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15540,6 +15602,7 @@ define void @global_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fin ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15616,6 +15679,7 @@ define void @global_system_atomic_fmin_noret_v2f16__offset12b_pos__amdgpu_no_fin ; GFX90A-NEXT: v_pk_max_f16 v2, v3, v3 ; GFX90A-NEXT: v_pk_min_f16 v2, v2, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15905,6 +15969,7 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__amdgpu_no_fine_grained ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16411,6 +16476,7 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu_ ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16919,6 +16985,7 @@ define <2 x bfloat> @global_agent_atomic_fmin_ret_v2bf16__offset12b_neg__amdgpu_ ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17431,6 +17498,7 @@ define void @global_agent_atomic_fmin_noret_v2bf16__amdgpu_no_fine_grained_memor ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17916,6 +17984,7 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fin ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18404,6 +18473,7 @@ define void @global_agent_atomic_fmin_noret_v2bf16__offset12b_neg__amdgpu_no_fin ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18906,6 +18976,7 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19083,6 +19154,7 @@ define <2 x bfloat> @global_system_atomic_fmin_ret_v2bf16__offset12b_pos__amdgpu ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19414,6 +19486,7 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19585,6 +19658,7 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19776,6 +19850,6 @@ define void @global_system_atomic_fmin_noret_v2bf16__offset12b_pos__amdgpu_no_fi } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll index 0229a482ca17b..748971fa059c1 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll @@ -56,6 +56,7 @@ define float @global_agent_atomic_fsub_ret_f32(ptr addrspace(1) %ptr, float %val ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -287,6 +288,7 @@ define float @global_agent_atomic_fsub_ret_f32__offset12b_pos(ptr addrspace(1) % ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -520,6 +522,7 @@ define float @global_agent_atomic_fsub_ret_f32__offset12b_neg(ptr addrspace(1) % ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -761,6 +764,7 @@ define void @global_agent_atomic_fsub_noret_f32(ptr addrspace(1) %ptr, float %va ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -981,6 +985,7 @@ define void @global_agent_atomic_fsub_noret_f32__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1204,6 +1209,7 @@ define void @global_agent_atomic_fsub_noret_f32__offset12b_neg(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -1438,6 +1444,7 @@ define float @global_system_atomic_fsub_ret_f32__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1511,6 +1518,7 @@ define float @global_system_atomic_fsub_ret_f32__offset12b_pos(ptr addrspace(1) ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1672,6 +1680,7 @@ define void @global_system_atomic_fsub_noret_f32__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -1741,6 +1750,7 @@ define void @global_system_atomic_fsub_noret_f32__offset12b_pos(ptr addrspace(1) ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -1903,6 +1913,7 @@ define float @global_agent_atomic_fsub_ret_f32__ftz(ptr addrspace(1) %ptr, float ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2134,6 +2145,7 @@ define float @global_agent_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr addrspace ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2367,6 +2379,7 @@ define float @global_agent_atomic_fsub_ret_f32__offset12b_neg__ftz(ptr addrspace ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2608,6 +2621,7 @@ define void @global_agent_atomic_fsub_noret_f32__ftz(ptr addrspace(1) %ptr, floa ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -2828,6 +2842,7 @@ define void @global_agent_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr addrspac ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3051,6 +3066,7 @@ define void @global_agent_atomic_fsub_noret_f32__offset12b_neg__ftz(ptr addrspac ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -3285,6 +3301,7 @@ define float @global_system_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr addrspac ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -3358,6 +3375,7 @@ define float @global_system_atomic_fsub_ret_f32__offset12b_pos__ftz(ptr addrspac ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3519,6 +3537,7 @@ define void @global_system_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr addrspa ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -3588,6 +3607,7 @@ define void @global_system_atomic_fsub_noret_f32__offset12b_pos__ftz(ptr addrspa ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_sub_f32_e32 v4, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -3750,6 +3770,7 @@ define double @global_agent_atomic_fsub_ret_f64(ptr addrspace(1) %ptr, double %v ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4001,6 +4022,7 @@ define double @global_agent_atomic_fsub_ret_f64__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:2040 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4253,6 +4275,7 @@ define double @global_agent_atomic_fsub_ret_f64__offset12b_neg(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4507,6 +4530,7 @@ define void @global_agent_atomic_fsub_noret_f64(ptr addrspace(1) %ptr, double %v ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4736,6 +4760,7 @@ define void @global_agent_atomic_fsub_noret_f64__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:2040 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -4968,6 +4993,7 @@ define void @global_agent_atomic_fsub_noret_f64__offset12b_neg(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_add_f64 v[4:5], v[6:7], -v[2:3] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5281,6 +5307,7 @@ define half @global_agent_atomic_fsub_ret_f16(ptr addrspace(1) %ptr, half %val) ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -5701,6 +5728,7 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %p ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6132,6 +6160,7 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_neg(ptr addrspace(1) %p ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6555,6 +6584,7 @@ define void @global_agent_atomic_fsub_noret_f16(ptr addrspace(1) %ptr, half %val ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -6963,6 +6993,7 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7381,6 +7412,7 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_neg(ptr addrspace(1) ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -7767,6 +7799,7 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos__align4(ptr addrspa ; GFX942-NEXT: v_sub_f16_e32 v3, v5, v2 ; GFX942-NEXT: v_and_or_b32 v4, v5, s2, v3 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8083,6 +8116,7 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b__align4_pos(ptr addrs ; GFX942-NEXT: v_sub_f16_e32 v3, v5, v2 ; GFX942-NEXT: v_and_or_b32 v4, v5, s2, v3 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -8429,6 +8463,7 @@ define half @global_system_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) % ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -8578,6 +8613,7 @@ define half @global_system_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) % ; GFX90A-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX90A-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -8860,6 +8896,7 @@ define void @global_system_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -9004,6 +9041,7 @@ define void @global_system_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1) ; GFX90A-NEXT: v_lshlrev_b32_e32 v4, v3, v4 ; GFX90A-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -9313,6 +9351,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16(ptr addrspace(1) %ptr, bfloat % ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -9819,6 +9858,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10337,6 +10377,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_neg(ptr addrspace(1) ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -10844,6 +10885,7 @@ define void @global_agent_atomic_fsub_noret_bf16(ptr addrspace(1) %ptr, bfloat % ; GFX942-NEXT: v_lshlrev_b32_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v4, v5, v6, v4 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v4, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11336,6 +11378,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1) ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -11839,6 +11882,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b_neg(ptr addrspace(1) ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12311,6 +12355,7 @@ define bfloat @global_agent_atomic_fsub_ret_bf16__offset12b_pos__align4(ptr addr ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -12719,6 +12764,7 @@ define void @global_agent_atomic_fsub_noret_bf16__offset12b__align4_pos(ptr addr ; GFX942-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX942-NEXT: v_and_or_b32 v2, v3, s3, v2 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2046 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -13157,6 +13203,7 @@ define bfloat @global_system_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1 ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13342,6 +13389,7 @@ define bfloat @global_system_atomic_fsub_ret_bf16__offset12b_pos(ptr addrspace(1 ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -13674,6 +13722,7 @@ define void @global_system_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1 ; GFX942-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX942-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -13853,6 +13902,7 @@ define void @global_system_atomic_fsub_noret_bf16__offset12b_pos(ptr addrspace(1 ; GFX90A-NEXT: v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX90A-NEXT: v_and_or_b32 v2, v3, v5, v2 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -14082,6 +14132,7 @@ define <2 x half> @global_agent_atomic_fsub_ret_v2f16(ptr addrspace(1) %ptr, <2 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14346,6 +14397,7 @@ define <2 x half> @global_agent_atomic_fsub_ret_v2f16__offset12b_pos(ptr addrspa ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14612,6 +14664,7 @@ define <2 x half> @global_agent_atomic_fsub_ret_v2f16__offset12b_neg(ptr addrspa ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -14884,6 +14937,7 @@ define void @global_agent_atomic_fsub_noret_v2f16(ptr addrspace(1) %ptr, <2 x ha ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15133,6 +15187,7 @@ define void @global_agent_atomic_fsub_noret_v2f16__offset12b_pos(ptr addrspace(1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15385,6 +15440,7 @@ define void @global_agent_atomic_fsub_noret_v2f16__offset12b_neg(ptr addrspace(1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -15648,6 +15704,7 @@ define <2 x half> @global_system_atomic_fsub_ret_v2f16__offset12b_pos(ptr addrsp ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15721,6 +15778,7 @@ define <2 x half> @global_system_atomic_fsub_ret_v2f16__offset12b_pos(ptr addrsp ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -15915,6 +15973,7 @@ define void @global_system_atomic_fsub_noret_v2f16__offset12b_pos(ptr addrspace( ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -15984,6 +16043,7 @@ define void @global_system_atomic_fsub_noret_v2f16__offset12b_pos(ptr addrspace( ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: v_pk_add_f16 v4, v5, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -16267,6 +16327,7 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16(ptr addrspace(1) %ptr, ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -16773,6 +16834,7 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_pos(ptr addr ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17281,6 +17343,7 @@ define <2 x bfloat> @global_agent_atomic_fsub_ret_v2bf16__offset12b_neg(ptr addr ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -17793,6 +17856,7 @@ define void @global_agent_atomic_fsub_noret_v2bf16(ptr addrspace(1) %ptr, <2 x b ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18278,6 +18342,7 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace( ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -18766,6 +18831,7 @@ define void @global_agent_atomic_fsub_noret_v2bf16__offset12b_neg(ptr addrspace( ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:-2048 sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -19268,6 +19334,7 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19445,6 +19512,7 @@ define <2 x bfloat> @global_system_atomic_fsub_ret_v2bf16__offset12b_pos(ptr add ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -19776,6 +19844,7 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace ; GFX942-NEXT: v_cndmask_b32_e64 v2, v7, v8, s[0:1] ; GFX942-NEXT: v_perm_b32 v2, v6, v2, s5 ; GFX942-NEXT: buffer_wbl2 sc0 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc0 sc1 @@ -19947,6 +20016,7 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace ; GFX90A-NEXT: v_cndmask_b32_e32 v6, v9, v10, vcc ; GFX90A-NEXT: v_perm_b32 v2, v6, v2, s9 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off offset:2044 glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -20138,4 +20208,4 @@ define void @global_system_atomic_fsub_noret_v2bf16__offset12b_pos(ptr addrspace } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll b/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll index bd9aa0f5a454a..74f85467f8872 100644 --- a/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll +++ b/llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll @@ -33,6 +33,6 @@ define amdgpu_kernel void @global_atomic_fadd_noret_f32_wrong_subtarget(ptr addr ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-features"="+atomic-fadd-no-rtn-insts" } +attributes #0 = { denormal_fpenv(float: preservesign) "target-features"="+atomic-fadd-no-rtn-insts" } !0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll index eb1d950a90467..49de34820c4c0 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll @@ -1125,10 +1125,9 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4096(ptr addrspace ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v0, vcc, 0x1000, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1212,10 +1211,9 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg4097(ptr addrsp ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v0, vcc, 0xfffff000, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1393,10 +1391,9 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF(ptr addrs ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v0, vcc, 0x7ff000, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1441,10 +1438,9 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF(ptr addrs ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v0, vcc, 0xff800000, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll b/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll index 94d9092cda2b1..8a61b8f5eeda5 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll @@ -1946,6 +1946,6 @@ define amdgpu_ps double @global_atomic_fadd_double_div_address_div_value_system_ ret double %result } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } +attributes #1 = { strictfp denormal_fpenv(float: preservesign) } attributes #2 = { strictfp } diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll index af38d6e27f6ff..8587ab3fdb3af 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomics_optimizer_fp_no_rtn.ll @@ -1638,6 +1638,6 @@ define amdgpu_ps void @global_atomic_fadd_double_div_address_div_value_system_sc ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } +attributes #1 = { strictfp denormal_fpenv(float: preservesign) } attributes #2 = { strictfp } diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll index a6a886dc321ce..103ca48a7dc5f 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll @@ -12931,8 +12931,8 @@ define amdgpu_kernel void @global_atomic_fadd_uni_address_uni_value_system_scope ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } +attributes #1 = { strictfp denormal_fpenv(float: preservesign) } attributes #2 = { strictfp } !1 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll index e62d6c593215b..2160976599dd7 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll @@ -7413,7 +7413,7 @@ define amdgpu_kernel void @global_atomic_fmax_uni_address_uni_value_system_scope ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } !1 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll index 1c14ff65dcbb6..029fb9c118344 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll @@ -7413,6 +7413,6 @@ define amdgpu_kernel void @global_atomic_fmin_uni_address_uni_value_system_scope ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } !1 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll index b97c3cdf32d12..3250d95bb0b7d 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll @@ -12565,7 +12565,7 @@ define amdgpu_kernel void @global_atomic_fsub_double_uni_address_div_value_defau ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } +attributes #1 = { strictfp denormal_fpenv(float: preservesign) } attributes #2 = { strictfp } diff --git a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll index c24c3f8f6159b..7956670a16530 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll @@ -92,10 +92,10 @@ define amdgpu_kernel void @test_no_ieee_mode_no_dx10_clamp_vi(ptr addrspace(1) % attributes #0 = { nounwind "target-cpu"="kaveri" } attributes #1 = { nounwind "target-cpu"="fiji" } -attributes #2 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #4 = { nounwind "denormal-fp-math"="ieee,ieee" } -attributes #5 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #2 = { nounwind denormal_fpenv(float: preservesign) } +attributes #3 = { nounwind denormal_fpenv(preservesign, float: ieee) } +attributes #4 = { nounwind denormal_fpenv(ieee) } +attributes #5 = { nounwind denormal_fpenv(preservesign) } attributes #6 = { nounwind "amdgpu-dx10-clamp"="false" "target-cpu"="fiji" } attributes #7 = { nounwind "amdgpu-ieee"="false" "target-cpu"="fiji" } attributes #8 = { nounwind "amdgpu-dx10-clamp"="false" "amdgpu-ieee"="false" "target-cpu"="fiji" } diff --git a/llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll b/llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll index d45cde4ca2376..864c74d1056d2 100644 --- a/llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes='require,atomic-expand' < %s | FileCheck --check-prefix=OPT %s @@ -13,7 +13,6 @@ define i32 @global_agent_monotonic_idempotent_or(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] syncscope("agent-one-as") monotonic, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw or ptr addrspace(1) %in, i32 0 syncscope("agent-one-as") monotonic, align 4 ret i32 %val @@ -31,7 +30,6 @@ define i32 @global_agent_acquire_idempotent_or(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] syncscope("agent-one-as") acquire, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw or ptr addrspace(1) %in, i32 0 syncscope("agent-one-as") acquire, align 4 ret i32 %val @@ -43,6 +41,7 @@ define i32 @global_agent_release_idempotent_or(ptr addrspace(1) %in) { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_or v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] @@ -50,7 +49,6 @@ define i32 @global_agent_release_idempotent_or(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = atomicrmw add ptr addrspace(1) [[IN:%.*]], i32 0 syncscope("agent-one-as") release, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw or ptr addrspace(1) %in, i32 0 syncscope("agent-one-as") release, align 4 ret i32 %val @@ -62,6 +60,7 @@ define i32 @global_agent_release_idempotent_or_no_remote(ptr addrspace(1) %in) { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_or v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] @@ -80,6 +79,7 @@ define i32 @global_agent_release_idempotent_or_no_fine_grained(ptr addrspace(1) ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_or v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] @@ -98,6 +98,7 @@ define i32 @global_agent_acquire_release_idempotent_or(ptr addrspace(1) %in) { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_or v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -106,7 +107,6 @@ define i32 @global_agent_acquire_release_idempotent_or(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = atomicrmw add ptr addrspace(1) [[IN:%.*]], i32 0 syncscope("agent-one-as") acq_rel, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw or ptr addrspace(1) %in, i32 0 syncscope("agent-one-as") acq_rel, align 4 ret i32 %val @@ -118,6 +118,7 @@ define i32 @global_agent_acquire_release_idempotent_or__no_fine_grained(ptr addr ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_or v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -137,6 +138,7 @@ define i32 @global_agent_seq_cst_idempotent_or(ptr addrspace(1) %in) { ; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX942-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-NEXT: buffer_wbl2 sc1 +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: global_atomic_or v0, v[0:1], v2, off sc0 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_inv sc1 @@ -145,7 +147,6 @@ define i32 @global_agent_seq_cst_idempotent_or(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = atomicrmw add ptr addrspace(1) [[IN:%.*]], i32 0 syncscope("agent-one-as") seq_cst, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw or ptr addrspace(1) %in, i32 0 syncscope("agent-one-as") seq_cst, align 4 ret i32 %val @@ -162,7 +163,6 @@ define i32 @global_agent_monotonic_idempotent_add(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] syncscope("workgroup") monotonic, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw add ptr addrspace(1) %in, i32 0 syncscope("workgroup") monotonic, align 4 ret i32 %val @@ -179,7 +179,6 @@ define i32 @global_agent_monotonic_idempotent_add__no_fine_grained(ptr addrspace ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] syncscope("workgroup") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META0]] ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw add ptr addrspace(1) %in, i32 0 syncscope("workgroup") monotonic, align 4, !amdgpu.no.fine.grained.memory !0 ret i32 %val @@ -196,7 +195,6 @@ define i32 @global_agent_monotonic_idempotent_sub(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] syncscope("wavefront") monotonic, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw sub ptr addrspace(1) %in, i32 0 syncscope("wavefront") monotonic, align 4 ret i32 %val @@ -213,7 +211,6 @@ define i32 @global_agent_monotonic_idempotent_sub__no_fine_grained(ptr addrspace ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] syncscope("wavefront") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META0]] ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw sub ptr addrspace(1) %in, i32 0 syncscope("wavefront") monotonic, align 4, !amdgpu.no.fine.grained.memory !0 ret i32 %val @@ -230,7 +227,6 @@ define i32 @global_system_monotonic_idempotent_xor(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] monotonic, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw xor ptr addrspace(1) %in, i32 0 monotonic, align 4 ret i32 %val @@ -247,7 +243,6 @@ define i32 @global_system_monotonic_idempotent_xor__no_fine_grained(ptr addrspac ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] monotonic, align 4, !amdgpu.no.fine.grained.memory [[META0]] ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw xor ptr addrspace(1) %in, i32 0 monotonic, align 4, !amdgpu.no.fine.grained.memory !0 ret i32 %val @@ -264,7 +259,6 @@ define i32 @global_agent_monotonic_idempotent_and(ptr addrspace(1) %in) { ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] syncscope("singlethread") monotonic, align 4 ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw and ptr addrspace(1) %in, i32 -1 syncscope("singlethread") monotonic, align 4 ret i32 %val @@ -281,7 +275,6 @@ define i32 @global_agent_monotonic_idempotent_and_no_fined_grain(ptr addrspace(1 ; OPT-NEXT: entry: ; OPT-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[IN:%.*]] syncscope("singlethread") monotonic, align 4, !amdgpu.no.fine.grained.memory [[META0]] ; OPT-NEXT: ret i32 [[VAL]] -; entry: %val = atomicrmw and ptr addrspace(1) %in, i32 -1 syncscope("singlethread") monotonic, align 4, !amdgpu.no.fine.grained.memory !0 ret i32 %val diff --git a/llvm/test/CodeGen/AMDGPU/imm16.ll b/llvm/test/CodeGen/AMDGPU/imm16.ll index ff40b1db5fe2f..0b2e5d540d463 100644 --- a/llvm/test/CodeGen/AMDGPU/imm16.ll +++ b/llvm/test/CodeGen/AMDGPU/imm16.ll @@ -19,16 +19,27 @@ define amdgpu_kernel void @store_inline_imm_neg_0.0_i16(ptr addrspace(1) %out) { ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_neg_0.0_i16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 dlc ; encoding: [0x00,0x20,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0x7c,0xbc] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_neg_0.0_i16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x8000 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x80,0xff,0xff] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 dlc ; encoding: [0x00,0x20,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0x7c,0xbc] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_neg_0.0_i16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 dlc ; encoding: [0x00,0x20,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0x7c,0xbc] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_neg_0.0_i16: ; VI: ; %bb.0: @@ -66,15 +77,25 @@ define amdgpu_kernel void @store_inline_imm_0.0_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_0.0_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_0.0_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0 ; encoding: [0x80,0x38,0x00,0x7e] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_0.0_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_0.0_f16: ; VI: ; %bb.0: @@ -110,15 +131,25 @@ define amdgpu_kernel void @store_imm_neg_0.0_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_imm_neg_0.0_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_imm_neg_0.0_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x8000 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x80,0xff,0xff] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_imm_neg_0.0_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_imm_neg_0.0_f16: ; VI: ; %bb.0: @@ -154,15 +185,25 @@ define amdgpu_kernel void @store_inline_imm_0.5_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_0.5_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x3800 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x38,0x00,0x00] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_0.5_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x38,0x00,0x00] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_0.5_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3800 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x38,0x00,0x00] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_0.5_f16: ; VI: ; %bb.0: @@ -198,15 +239,25 @@ define amdgpu_kernel void @store_inline_imm_m_0.5_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_m_0.5_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0xffffb800 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xb8,0xff,0xff] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_m_0.5_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0xb800 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0xb8,0xff,0xff] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_m_0.5_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0xffffb800 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xb8,0xff,0xff] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_m_0.5_f16: ; VI: ; %bb.0: @@ -242,15 +293,25 @@ define amdgpu_kernel void @store_inline_imm_1.0_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_1.0_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x3c00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x3c,0x00,0x00] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_1.0_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3c00 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x3c,0x00,0x00] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_1.0_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3c00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x3c,0x00,0x00] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_1.0_f16: ; VI: ; %bb.0: @@ -286,15 +347,25 @@ define amdgpu_kernel void @store_inline_imm_m_1.0_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_m_1.0_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0xffffbc00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xbc,0xff,0xff] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_m_1.0_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0xbc00 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0xbc,0xff,0xff] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_m_1.0_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0xffffbc00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xbc,0xff,0xff] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_m_1.0_f16: ; VI: ; %bb.0: @@ -330,15 +401,25 @@ define amdgpu_kernel void @store_inline_imm_2.0_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_2.0_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x4000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x40,0x00,0x00] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_2.0_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x4000 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x40,0x00,0x00] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_2.0_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x4000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x40,0x00,0x00] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_2.0_f16: ; VI: ; %bb.0: @@ -374,15 +455,25 @@ define amdgpu_kernel void @store_inline_imm_m_2.0_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_m_2.0_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0xffffc000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xc0,0xff,0xff] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_m_2.0_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0xc000 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0xc0,0xff,0xff] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_m_2.0_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0xffffc000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xc0,0xff,0xff] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_m_2.0_f16: ; VI: ; %bb.0: @@ -418,15 +509,25 @@ define amdgpu_kernel void @store_inline_imm_4.0_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_4.0_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x4400 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x44,0x00,0x00] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_4.0_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x4400 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x44,0x00,0x00] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_4.0_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x4400 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x44,0x00,0x00] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_4.0_f16: ; VI: ; %bb.0: @@ -462,15 +563,25 @@ define amdgpu_kernel void @store_inline_imm_m_4.0_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_m_4.0_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0xffffc400 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xc4,0xff,0xff] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_m_4.0_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0xc400 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0xc4,0xff,0xff] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_m_4.0_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0xffffc400 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0xc4,0xff,0xff] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_m_4.0_f16: ; VI: ; %bb.0: @@ -506,15 +617,25 @@ define amdgpu_kernel void @store_inline_imm_inv_2pi_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_inv_2pi_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x3118 ; encoding: [0xff,0x02,0x00,0x7e,0x18,0x31,0x00,0x00] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_inv_2pi_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3118 ; encoding: [0xff,0x38,0x00,0x7e,0x18,0x31,0x00,0x00] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_inv_2pi_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x3118 ; encoding: [0xff,0x02,0x00,0x7e,0x18,0x31,0x00,0x00] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_inv_2pi_f16: ; VI: ; %bb.0: @@ -550,15 +671,25 @@ define amdgpu_kernel void @store_inline_imm_m_inv_2pi_f16(ptr addrspace(1) %out) ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_inline_imm_m_inv_2pi_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0xffffb118 ; encoding: [0xff,0x02,0x00,0x7e,0x18,0xb1,0xff,0xff] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_inline_imm_m_inv_2pi_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0xb118 ; encoding: [0xff,0x38,0x00,0x7e,0x18,0xb1,0xff,0xff] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_inline_imm_m_inv_2pi_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0xffffb118 ; encoding: [0xff,0x02,0x00,0x7e,0x18,0xb1,0xff,0xff] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_inline_imm_m_inv_2pi_f16: ; VI: ; %bb.0: @@ -594,15 +725,25 @@ define amdgpu_kernel void @store_literal_imm_f16(ptr addrspace(1) %out) { ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; -; GFX11-LABEL: store_literal_imm_f16: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] -; GFX11-NEXT: v_mov_b32_e32 v0, 0x6c00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x6c,0x00,0x00] -; GFX11-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] -; GFX11-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] -; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] -; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] -; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; GFX11-TRUE16-LABEL: store_literal_imm_f16: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x6c00 ; encoding: [0xff,0x38,0x00,0x7e,0x00,0x6c,0x00,0x00] +; GFX11-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-TRUE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] +; +; GFX11-FAKE16-LABEL: store_literal_imm_f16: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xf8] +; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0x6c00 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x6c,0x00,0x00] +; GFX11-FAKE16-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0x60,0x01,0x31] +; GFX11-FAKE16-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf] +; GFX11-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x64,0xe0,0x00,0x00,0x00,0x80] +; GFX11-FAKE16-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf] ; ; VI-LABEL: store_literal_imm_f16: ; VI: ; %bb.0: @@ -1251,7 +1392,7 @@ define amdgpu_kernel void @commute_add_inline_imm_0.5_f16(ptr addrspace(1) %out, ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; encoding: [0x02,0x00,0x88,0xbe] ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; encoding: [0x03,0x00,0x89,0xbe] ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 ; encoding: [0x00,0x00,0x84,0xbe] -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x00,0x02,0x80] +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x80,0xe0,0x00,0x00,0x02,0x80] ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; encoding: [0x01,0x00,0x85,0xbe] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf] ; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 0.5, v0.l ; encoding: [0xf0,0x00,0x00,0x64] @@ -1349,7 +1490,7 @@ define amdgpu_kernel void @commute_add_literal_f16(ptr addrspace(1) %out, ptr ad ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; encoding: [0x02,0x00,0x88,0xbe] ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; encoding: [0x03,0x00,0x89,0xbe] ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 ; encoding: [0x00,0x00,0x84,0xbe] -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x48,0xe0,0x00,0x00,0x02,0x80] +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x80,0xe0,0x00,0x00,0x02,0x80] ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; encoding: [0x01,0x00,0x85,0xbe] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; encoding: [0xf7,0x03,0x89,0xbf] ; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 0x6400, v0.l ; encoding: [0xff,0x00,0x00,0x64,0x00,0x64,0x00,0x00] diff --git a/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll b/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll new file mode 100644 index 0000000000000..bc2f5566b0e62 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -O1 -global-isel < %s | FileCheck %s + +; Test that V_INDIRECT_REG_READ_GPR_IDX expansion handles immediate index operands. +; The wave.reduce.umin with constant arguments folds to 0, which becomes an +; immediate index for the insertelement, triggering V_INDIRECT_REG_READ_GPR_IDX +; with an immediate operand. + +; CHECK-LABEL: indirect_reg_read_imm_idx: +; CHECK: s_set_gpr_idx_on 0, gpr_idx(SRC0) +; CHECK-NEXT: v_mov_b32_e32 +; CHECK-NEXT: s_set_gpr_idx_off +define amdgpu_kernel void @indirect_reg_read_imm_idx() { +entry: + %vec = load <32 x i16>, ptr null, align 64 + %idx = call i32 @llvm.amdgcn.wave.reduce.umin.i32(i32 0, i32 0) + %ins = insertelement <32 x i16> %vec, i16 0, i32 %idx + store <32 x i16> %ins, ptr null, align 64 + ret void +} + +declare i32 @llvm.amdgcn.wave.reduce.umin.i32(i32, i32 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir b/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir new file mode 100644 index 0000000000000..0e4fa2790ef62 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir @@ -0,0 +1,18 @@ +# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -start-before=twoaddressinstruction %s -o - | FileCheck %s + +# Test that V_INDIRECT_REG_READ_GPR_IDX expansion handles immediate index operands. + + +# CHECK-LABEL: indirect_reg_read_imm_idx: +# CHECK: s_set_gpr_idx_on 0, gpr_idx(SRC0) +# CHECK-NEXT: v_mov_b32_e32 +# CHECK-NEXT: s_set_gpr_idx_off + +name: indirect_reg_read_imm_idx +tracksRegLiveness: true +body: | + bb.0.entry: + %0:vreg_512_align2 = IMPLICIT_DEF + %1:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V16 %0, 0, 3, implicit-def $m0, implicit $m0, implicit $exec + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/inline-attr.ll b/llvm/test/CodeGen/AMDGPU/inline-attr.ll index c33b3344fd51c..6400c3860ad88 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-attr.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-attr.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -O3 %s | FileCheck --check-prefixes=GCN,UNSAFE %s ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -O3 -enable-no-nans-fp-math %s | FileCheck --check-prefixes=GCN,NONANS %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -O3 -enable-no-infs-fp-math %s | FileCheck --check-prefixes=GCN,NOINFS %s declare void @extern() #0 @@ -37,17 +36,17 @@ entry: } attributes #0 = { nounwind "uniform-work-group-size"="false"} -attributes #1 = { nounwind "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" } +attributes #1 = { nounwind "less-precise-fpmad"="true" "no-nans-fp-math"="true" } ;. ; UNSAFE: attributes #[[ATTR0]] = { nounwind "uniform-work-group-size"="false" } -; UNSAFE: attributes #[[ATTR1]] = { nounwind "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "uniform-work-group-size"="false" } +; UNSAFE: attributes #[[ATTR1]] = { nounwind "less-precise-fpmad"="false" "no-nans-fp-math"="false" "uniform-work-group-size"="false" } ;. ; NONANS: attributes #[[ATTR0]] = { nounwind "no-nans-fp-math"="true" "uniform-work-group-size"="false" } -; NONANS: attributes #[[ATTR1]] = { nounwind "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="true" "uniform-work-group-size"="false" } +; NONANS: attributes #[[ATTR1]] = { nounwind "less-precise-fpmad"="false" "no-nans-fp-math"="true" "uniform-work-group-size"="false" } ;. -; NOINFS: attributes #[[ATTR0]] = { nounwind "no-infs-fp-math"="true" "uniform-work-group-size"="false" } -; NOINFS: attributes #[[ATTR1]] = { nounwind "less-precise-fpmad"="false" "no-infs-fp-math"="true" "no-nans-fp-math"="false" "uniform-work-group-size"="false" } +; NOINFS: attributes #[[ATTR0]] = { nounwind "uniform-work-group-size"="false" } +; NOINFS: attributes #[[ATTR1]] = { nounwind "less-precise-fpmad"="false" "no-nans-fp-math"="false" "uniform-work-group-size"="false" } ;. ; UNSAFE: [[META0]] = !{} ;. diff --git a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll index 58cd2f5bc11af..9eaebfdf611e0 100644 --- a/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll @@ -13,7 +13,7 @@ define fastcc i32 @foo() { ; CHECK-NEXT: $sgpr16 = S_MOV_B32 $sgpr33 ; CHECK-NEXT: $sgpr33 = S_MOV_B32 $sgpr32 ; CHECK-NEXT: $sgpr17 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr17 ; CHECK-NEXT: $sgpr32 = frame-setup S_ADDK_I32 $sgpr32, 512, implicit-def dead $scc ; CHECK-NEXT: $vgpr40 = V_WRITELANE_B32 killed $sgpr16, 2, undef $vgpr40 @@ -44,7 +44,7 @@ define fastcc i32 @foo() { ; CHECK-NEXT: $sgpr32 = S_MOV_B32 $sgpr33 ; CHECK-NEXT: $sgpr4 = V_READLANE_B32 $vgpr40, 2 ; CHECK-NEXT: $sgpr5 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 killed $sgpr5 ; CHECK-NEXT: $sgpr33 = S_MOV_B32 killed $sgpr4 ; CHECK-NEXT: S_WAITCNT 16240 diff --git a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll index b91967bca72d8..72e95db6da440 100644 --- a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll +++ b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll @@ -168,6 +168,7 @@ define i32 @atomic_nand_i32_global(ptr addrspace(1) %ptr) nounwind { ; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX90A-NEXT: v_bfi_b32 v2, v3, -5, -1 ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_invl2 @@ -822,6 +823,7 @@ define void @flat_atomic_xchg_i32_noret(ptr %ptr, i32 %in) { ; GFX90A: ; %bb.0: ; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: flat_atomic_swap v[0:1], v2 ; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX90A-NEXT: buffer_invl2 diff --git a/llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir b/llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir index 86b6c5982b4cb..1c93dee780312 100644 --- a/llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir +++ b/llvm/test/CodeGen/AMDGPU/issue98474-virtregrewriter-live-out-undef-subregisters.mir @@ -271,7 +271,7 @@ body: | ; CHECK-NEXT: liveins: $sgpr30, $sgpr31, $sgpr34, $sgpr35, $sgpr36, $sgpr37, $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr40, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; CHECK-NEXT: $vgpr40 = SI_SPILL_S32_TO_VGPR $sgpr30, 0, $vgpr40 ; CHECK-NEXT: $vgpr40 = SI_SPILL_S32_TO_VGPR $sgpr31, 1, $vgpr40 @@ -307,7 +307,7 @@ body: | ; CHECK-NEXT: $sgpr31 = SI_RESTORE_S32_FROM_VGPR $vgpr40, 1 ; CHECK-NEXT: $sgpr30 = SI_RESTORE_S32_FROM_VGPR $vgpr40, 0 ; CHECK-NEXT: $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; CHECK-NEXT: SI_RETURN implicit $vgpr0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll index 2f9182e6e7c6a..5a15ec8ec3c8f 100644 --- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll +++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll @@ -417,8 +417,7 @@ define float @uitofp_i128_to_f32(i128 %x) { ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2 ; GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc ; GISEL-NEXT: ; implicit-def: $vgpr6 -; GISEL-NEXT: ; implicit-def: $vgpr0 -; GISEL-NEXT: ; implicit-def: $vgpr2 +; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GISEL-NEXT: ; %bb.3: ; %Flow3 ; GISEL-NEXT: s_or_saveexec_b64 s[8:9], s[4:5] ; GISEL-NEXT: v_sub_u32_e32 v7, 0x7f, v5 @@ -978,7 +977,7 @@ define double @uitofp_i128_to_f64(i128 %x) { ; GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v9, 0, v1, vcc ; GISEL-NEXT: ; implicit-def: $vgpr6 -; GISEL-NEXT: ; implicit-def: $vgpr0 +; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GISEL-NEXT: ; %bb.3: ; %Flow3 ; GISEL-NEXT: s_or_saveexec_b64 s[8:9], s[4:5] ; GISEL-NEXT: v_sub_u32_e32 v7, 0x7f, v8 @@ -1509,8 +1508,7 @@ define half @uitofp_i128_to_f16(i128 %x) { ; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2 ; GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v0, vcc ; GISEL-NEXT: ; implicit-def: $vgpr6 -; GISEL-NEXT: ; implicit-def: $vgpr0 -; GISEL-NEXT: ; implicit-def: $vgpr2 +; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 ; GISEL-NEXT: ; %bb.3: ; %Flow3 ; GISEL-NEXT: s_or_saveexec_b64 s[8:9], s[4:5] ; GISEL-NEXT: v_sub_u32_e32 v7, 0x7f, v5 diff --git a/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir b/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir index 7a913cf50ea2b..819da917db9fb 100644 --- a/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir +++ b/llvm/test/CodeGen/AMDGPU/kernel-mubuf-with-voffset.mir @@ -36,7 +36,7 @@ body: | ; CHECK-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: diff --git a/llvm/test/CodeGen/AMDGPU/known-never-snan.ll b/llvm/test/CodeGen/AMDGPU/known-never-snan.ll index 5691fc8740a6b..078f3014fdc9b 100644 --- a/llvm/test/CodeGen/AMDGPU/known-never-snan.ll +++ b/llvm/test/CodeGen/AMDGPU/known-never-snan.ll @@ -667,7 +667,7 @@ declare float @llvm.amdgcn.rsq.f32(float) #1 declare float @llvm.amdgcn.fract.f32(float) #1 declare float @llvm.amdgcn.cubeid(float, float, float) #0 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone speculatable } !0 = !{float 2.500000e+00} diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir index 21372c06d3223..0e64d0430668e 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir +++ b/llvm/test/CodeGen/AMDGPU/lds-dma-waitcnt.mir @@ -67,6 +67,45 @@ body: | ... +# Test that GLOBAL_LOAD_LDS does not increment lgkmcnt (LGKM_CNT = 0). +# GCN-LABEL: name: ds_read_global_load_lds_use_ds_data +# GCN: DS_READ_B32_gfx9 +# GCN-NEXT: GLOBAL_LOAD_LDS_DWORD +# GCN-NEXT: S_WAITCNT 49279 +# lgkmcnt(0) +# GCN-NEXT: V_ADD_U32_e32 +--- +name: ds_read_global_load_lds_use_ds_data +body: | + bb.0: + $m0 = S_MOV_B32 0 + $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `ptr addrspace(3) poison`) + GLOBAL_LOAD_LDS_DWORD $vgpr2_vgpr3, 4, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) poison` + 4), (store (s32) into `ptr addrspace(3) poison` + 4) + $vgpr4 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec + S_ENDPGM 0 + +... + +# Test that BUFFER_LOAD_DWORD_LDS does not increment lgkmcnt. +# DS_READ increments lgkmcnt. When using the DS_READ result, we wait for lgkmcnt(0). +# GCN-LABEL: name: ds_read_buffer_load_lds_use_ds_data +# GCN: DS_READ_B32_gfx9 +# GCN-NEXT: BUFFER_LOAD_DWORD_LDS_IDXEN +# GCN-NEXT: S_WAITCNT 49279 +# lgkmcnt(0) +# GCN-NEXT: V_ADD_U32_e32 +--- +name: ds_read_buffer_load_lds_use_ds_data +body: | + bb.0: + $m0 = S_MOV_B32 0 + $vgpr0 = DS_READ_B32_gfx9 $vgpr1, 0, 0, implicit $m0, implicit $exec :: (load (s32) from `ptr addrspace(3) poison`) + BUFFER_LOAD_DWORD_LDS_IDXEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec, implicit $m0 :: (load (s32) from `ptr addrspace(1) poison`), (store (s32) into `ptr addrspace(3) poison`) + $vgpr4 = V_ADD_U32_e32 $vgpr0, $vgpr0, implicit $exec + S_ENDPGM 0 + +... + # GCN-LABEL: name: scratch_load_lds_dword_ds_read # GCN: SCRATCH_LOAD_LDS_DWORD # GCN-NEXT: S_WAITCNT 3952 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll index 3372868455d65..4280d10fc2b33 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll @@ -1,8 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1170 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX1170 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX12 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1170PLUS,GFX1250 %s define amdgpu_cs float @test_cvt_f32_bf8_byte0(i32 %a) { +; GFX1170-LABEL: test_cvt_f32_bf8_byte0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_cvt_f32_bf8_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: test_cvt_f32_bf8_byte0: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_cvt_f32_bf8_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -19,6 +25,11 @@ define amdgpu_cs float @test_cvt_f32_bf8_byte0(i32 %a) { } define amdgpu_cs float @test_cvt_f32_bf8_byte1(i32 %a) { +; GFX1170-LABEL: test_cvt_f32_bf8_byte1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: test_cvt_f32_bf8_byte1: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -35,6 +46,11 @@ define amdgpu_cs float @test_cvt_f32_bf8_byte1(i32 %a) { } define amdgpu_cs float @test_cvt_f32_bf8_byte2(i32 %a) { +; GFX1170-LABEL: test_cvt_f32_bf8_byte2: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: test_cvt_f32_bf8_byte2: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_cvt_f32_bf8_e64_dpp v0, v0 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -51,6 +67,11 @@ define amdgpu_cs float @test_cvt_f32_bf8_byte2(i32 %a) { } define amdgpu_cs float @test_cvt_f32_fp8_byte3(i32 %a) { +; GFX1170-LABEL: test_cvt_f32_fp8_byte3: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_cvt_f32_fp8_e64_dpp v0, v0 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: test_cvt_f32_fp8_byte3: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_cvt_f32_fp8_e64_dpp v0, v0 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -67,6 +88,14 @@ define amdgpu_cs float @test_cvt_f32_fp8_byte3(i32 %a) { } define amdgpu_cs void @test_cvt_pk_bf8_f32_word0(i32 %a, float %y, i32 %old, ptr addrspace(1) %out) { +; GFX1170-LABEL: test_cvt_pk_bf8_f32_word0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_cvt_pk_bf8_f32 v2.l, v0, v1 +; GFX1170-NEXT: global_store_b32 v[3:4], v2, off +; GFX1170-NEXT: s_endpgm +; ; GFX12-LABEL: test_cvt_pk_bf8_f32_word0: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_cvt_pk_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -88,6 +117,14 @@ define amdgpu_cs void @test_cvt_pk_bf8_f32_word0(i32 %a, float %y, i32 %old, ptr } define amdgpu_cs void @test_cvt_pk_fp8_f32_word1(i32 %a, float %y, i32 %old, ptr addrspace(1) %out) { +; GFX1170-LABEL: test_cvt_pk_fp8_f32_word1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_cvt_pk_fp8_f32 v2.h, v0, v1 op_sel:[0,0,1] +; GFX1170-NEXT: global_store_b32 v[3:4], v2, off +; GFX1170-NEXT: s_endpgm +; ; GFX12-LABEL: test_cvt_pk_fp8_f32_word1: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -113,6 +150,12 @@ define amdgpu_cs void @test_cvt_pk_fp8_f32_word1(i32 %a, float %y, i32 %old, ptr } define amdgpu_cs void @test_cvt_sr_bf8_f32_byte0(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) { +; GFX1170-LABEL: test_cvt_sr_bf8_f32_byte0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_cvt_sr_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: global_store_b32 v[3:4], v2, off +; GFX1170-NEXT: s_endpgm +; ; GFX12-LABEL: test_cvt_sr_bf8_f32_byte0: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_cvt_sr_bf8_f32_e64_dpp v2, v0, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -134,6 +177,12 @@ define amdgpu_cs void @test_cvt_sr_bf8_f32_byte0(i32 %a, i32 %r, i32 %old, ptr a } define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) { +; GFX1170-LABEL: test_cvt_sr_fp8_f32_byte1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: global_store_b32 v[3:4], v2, off +; GFX1170-NEXT: s_endpgm +; ; GFX12-LABEL: test_cvt_sr_fp8_f32_byte1: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -155,6 +204,12 @@ define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1(i32 %a, i32 %r, i32 %old, ptr a } define amdgpu_cs void @test_cvt_sr_fp8_f32_byte2(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) { +; GFX1170-LABEL: test_cvt_sr_fp8_f32_byte2: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 +; GFX1170-NEXT: global_store_b32 v[3:4], v2, off +; GFX1170-NEXT: s_endpgm +; ; GFX12-LABEL: test_cvt_sr_fp8_f32_byte2: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 @@ -187,3 +242,5 @@ declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32) #1 attributes #0 = { nounwind convergent } attributes #1 = { nounwind readnone convergent } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX1170PLUS: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir index b1e23808e91a9..ce36dd0aa26f9 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir @@ -1,6 +1,8 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass=gcn-dpp-combine %s -o - | FileCheck -check-prefix=GFX12 %s -# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -passes=gcn-dpp-combine %s -o - | FileCheck -check-prefix=GFX12 %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1170 -verify-machineinstrs -run-pass=gcn-dpp-combine %s -o - | FileCheck -check-prefix=GFX1170PLUS %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1170 -verify-machineinstrs -passes=gcn-dpp-combine %s -o - | FileCheck -check-prefix=GFX1170PLUS %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass=gcn-dpp-combine %s -o - | FileCheck -check-prefix=GFX1170PLUS %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -passes=gcn-dpp-combine %s -o - | FileCheck -check-prefix=GFX1170PLUS %s --- name: test_cvt_f32_bf8_byte0 @@ -9,14 +11,14 @@ body: | bb.0: liveins: $vgpr0 - ; GFX12-LABEL: name: test_cvt_f32_bf8_byte0 - ; GFX12: liveins: $vgpr0 - ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; GFX12-NEXT: [[V_CVT_F32_BF8_OP_SEL_dpp:%[0-9]+]]:vgpr_32 = V_CVT_F32_BF8_OP_SEL_dpp [[DEF]], [[COPY]], 228, 15, 15, 1, implicit $mode, implicit $exec - ; GFX12-NEXT: $vgpr0 = COPY [[V_CVT_F32_BF8_OP_SEL_dpp]] - ; GFX12-NEXT: SI_RETURN_TO_EPILOG $vgpr0 + ; GFX1170PLUS-LABEL: name: test_cvt_f32_bf8_byte0 + ; GFX1170PLUS: liveins: $vgpr0 + ; GFX1170PLUS-NEXT: {{ $}} + ; GFX1170PLUS-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1170PLUS-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX1170PLUS-NEXT: [[V_CVT_F32_BF8_OP_SEL_dpp:%[0-9]+]]:vgpr_32 = V_CVT_F32_BF8_OP_SEL_dpp [[DEF]], [[COPY]], 228, 15, 15, 1, implicit $mode, implicit $exec + ; GFX1170PLUS-NEXT: $vgpr0 = COPY [[V_CVT_F32_BF8_OP_SEL_dpp]] + ; GFX1170PLUS-NEXT: SI_RETURN_TO_EPILOG $vgpr0 %0:vgpr_32 = COPY $vgpr0 %1:vgpr_32 = V_MOV_B32_dpp %0, %0, 228, 15, 15, -1, implicit $exec %2:vgpr_32 = V_CVT_F32_BF8_OP_SEL_e32 killed %1, implicit $mode, implicit $exec @@ -31,14 +33,14 @@ body: | bb.0: liveins: $vgpr0 - ; GFX12-LABEL: name: test_cvt_f32_bf8_byte2 - ; GFX12: liveins: $vgpr0 - ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; GFX12-NEXT: [[V_CVT_F32_BF8_OP_SEL_e64_dpp:%[0-9]+]]:vgpr_32 = V_CVT_F32_BF8_OP_SEL_e64_dpp [[DEF]], [[COPY]], 2, 228, 15, 15, 1, implicit $mode, implicit $exec - ; GFX12-NEXT: $vgpr0 = COPY [[V_CVT_F32_BF8_OP_SEL_e64_dpp]] - ; GFX12-NEXT: SI_RETURN_TO_EPILOG $vgpr0 + ; GFX1170PLUS-LABEL: name: test_cvt_f32_bf8_byte2 + ; GFX1170PLUS: liveins: $vgpr0 + ; GFX1170PLUS-NEXT: {{ $}} + ; GFX1170PLUS-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1170PLUS-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX1170PLUS-NEXT: [[V_CVT_F32_BF8_OP_SEL_e64_dpp:%[0-9]+]]:vgpr_32 = V_CVT_F32_BF8_OP_SEL_e64_dpp [[DEF]], [[COPY]], 2, 228, 15, 15, 1, implicit $mode, implicit $exec + ; GFX1170PLUS-NEXT: $vgpr0 = COPY [[V_CVT_F32_BF8_OP_SEL_e64_dpp]] + ; GFX1170PLUS-NEXT: SI_RETURN_TO_EPILOG $vgpr0 %0:vgpr_32 = COPY $vgpr0 %1:vgpr_32 = V_MOV_B32_dpp %0, %0, 228, 15, 15, -1, implicit $exec %2:vgpr_32 = V_CVT_F32_BF8_OP_SEL_e64 killed %1, 2, implicit $mode, implicit $exec @@ -53,14 +55,14 @@ body: | bb.0: liveins: $vgpr0 - ; GFX12-LABEL: name: test_cvt_f32_fp8_byte3 - ; GFX12: liveins: $vgpr0 - ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; GFX12-NEXT: [[V_CVT_F32_FP8_OP_SEL_e64_dpp:%[0-9]+]]:vgpr_32 = V_CVT_F32_FP8_OP_SEL_e64_dpp [[DEF]], [[COPY]], 3, 228, 15, 15, 1, implicit $mode, implicit $exec - ; GFX12-NEXT: $vgpr0 = COPY [[V_CVT_F32_FP8_OP_SEL_e64_dpp]] - ; GFX12-NEXT: SI_RETURN_TO_EPILOG $vgpr0 + ; GFX1170PLUS-LABEL: name: test_cvt_f32_fp8_byte3 + ; GFX1170PLUS: liveins: $vgpr0 + ; GFX1170PLUS-NEXT: {{ $}} + ; GFX1170PLUS-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1170PLUS-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX1170PLUS-NEXT: [[V_CVT_F32_FP8_OP_SEL_e64_dpp:%[0-9]+]]:vgpr_32 = V_CVT_F32_FP8_OP_SEL_e64_dpp [[DEF]], [[COPY]], 3, 228, 15, 15, 1, implicit $mode, implicit $exec + ; GFX1170PLUS-NEXT: $vgpr0 = COPY [[V_CVT_F32_FP8_OP_SEL_e64_dpp]] + ; GFX1170PLUS-NEXT: SI_RETURN_TO_EPILOG $vgpr0 %0:vgpr_32 = COPY $vgpr0 %1:vgpr_32 = V_MOV_B32_dpp %0, %0, 228, 15, 15, -1, implicit $exec %2:vgpr_32 = V_CVT_F32_FP8_OP_SEL_e64 killed %1, 3, implicit $mode, implicit $exec @@ -75,19 +77,19 @@ body: | bb.0: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 - ; GFX12-LABEL: name: test_cvt_pk_bf8_f32_word0 - ; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 - ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 - ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; GFX12-NEXT: [[V_CVT_PK_BF8_F32_e64_dpp:%[0-9]+]]:vgpr_32 = V_CVT_PK_BF8_F32_e64_dpp [[DEF]], 0, [[COPY4]], 0, [[COPY3]], [[COPY2]], 0, 228, 15, 15, 1, implicit $mode, implicit $exec - ; GFX12-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], killed [[V_CVT_PK_BF8_F32_e64_dpp]], 0, 0, implicit $exec - ; GFX12-NEXT: S_ENDPGM 0 + ; GFX1170PLUS-LABEL: name: test_cvt_pk_bf8_f32_word0 + ; GFX1170PLUS: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1170PLUS-NEXT: {{ $}} + ; GFX1170PLUS-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX1170PLUS-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX1170PLUS-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX1170PLUS-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX1170PLUS-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1170PLUS-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; GFX1170PLUS-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX1170PLUS-NEXT: [[V_CVT_PK_BF8_F32_e64_dpp:%[0-9]+]]:vgpr_32 = V_CVT_PK_BF8_F32_e64_dpp [[DEF]], 0, [[COPY4]], 0, [[COPY3]], [[COPY2]], 0, 228, 15, 15, 1, implicit $mode, implicit $exec + ; GFX1170PLUS-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], killed [[V_CVT_PK_BF8_F32_e64_dpp]], 0, 0, implicit $exec + ; GFX1170PLUS-NEXT: S_ENDPGM 0 %4:vgpr_32 = COPY $vgpr4 %3:vgpr_32 = COPY $vgpr3 %2:vgpr_32 = COPY $vgpr2 @@ -107,19 +109,19 @@ body: | bb.0: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 - ; GFX12-LABEL: name: test_cvt_pk_fp8_f32_word1 - ; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 - ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 - ; GFX12-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY4]], [[COPY4]], 228, 15, 15, -1, implicit $exec - ; GFX12-NEXT: [[V_CVT_PK_FP8_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_FP8_F32_e64 8, killed [[V_MOV_B32_dpp]], 0, [[COPY3]], [[COPY2]], 0, implicit $mode, implicit $exec - ; GFX12-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], killed [[V_CVT_PK_FP8_F32_e64_]], 0, 0, implicit $exec - ; GFX12-NEXT: S_ENDPGM 0 + ; GFX1170PLUS-LABEL: name: test_cvt_pk_fp8_f32_word1 + ; GFX1170PLUS: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1170PLUS-NEXT: {{ $}} + ; GFX1170PLUS-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX1170PLUS-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX1170PLUS-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX1170PLUS-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX1170PLUS-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1170PLUS-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; GFX1170PLUS-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY4]], [[COPY4]], 228, 15, 15, -1, implicit $exec + ; GFX1170PLUS-NEXT: [[V_CVT_PK_FP8_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_FP8_F32_e64 8, killed [[V_MOV_B32_dpp]], 0, [[COPY3]], [[COPY2]], 0, implicit $mode, implicit $exec + ; GFX1170PLUS-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], killed [[V_CVT_PK_FP8_F32_e64_]], 0, 0, implicit $exec + ; GFX1170PLUS-NEXT: S_ENDPGM 0 %4:vgpr_32 = COPY $vgpr4 %3:vgpr_32 = COPY $vgpr3 %2:vgpr_32 = COPY $vgpr2 @@ -139,19 +141,19 @@ body: | bb.0: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 - ; GFX12-LABEL: name: test_cvt_sr_bf8_f32_byte0 - ; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 - ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 - ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; GFX12-NEXT: [[V_CVT_SR_BF8_F32_e64_dpp:%[0-9]+]]:vgpr_32 = V_CVT_SR_BF8_F32_e64_dpp [[DEF]], 0, [[COPY4]], 0, [[COPY3]], 0, [[COPY2]], 0, 228, 15, 15, 1, implicit $mode, implicit $exec - ; GFX12-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], killed [[V_CVT_SR_BF8_F32_e64_dpp]], 0, 0, implicit $exec - ; GFX12-NEXT: S_ENDPGM 0 + ; GFX1170PLUS-LABEL: name: test_cvt_sr_bf8_f32_byte0 + ; GFX1170PLUS: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1170PLUS-NEXT: {{ $}} + ; GFX1170PLUS-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX1170PLUS-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX1170PLUS-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX1170PLUS-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX1170PLUS-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1170PLUS-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; GFX1170PLUS-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX1170PLUS-NEXT: [[V_CVT_SR_BF8_F32_e64_dpp:%[0-9]+]]:vgpr_32 = V_CVT_SR_BF8_F32_e64_dpp [[DEF]], 0, [[COPY4]], 0, [[COPY3]], 0, [[COPY2]], 0, 228, 15, 15, 1, implicit $mode, implicit $exec + ; GFX1170PLUS-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], killed [[V_CVT_SR_BF8_F32_e64_dpp]], 0, 0, implicit $exec + ; GFX1170PLUS-NEXT: S_ENDPGM 0 %4:vgpr_32 = COPY $vgpr4 %3:vgpr_32 = COPY $vgpr3 %2:vgpr_32 = COPY $vgpr2 @@ -171,19 +173,19 @@ body: | bb.0: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 - ; GFX12-LABEL: name: test_cvt_sr_fp8_f32_byte2 - ; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 - ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 - ; GFX12-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY4]], [[COPY4]], 228, 15, 15, -1, implicit $exec - ; GFX12-NEXT: [[V_CVT_SR_FP8_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_SR_FP8_F32_e64 8, killed [[V_MOV_B32_dpp]], 0, [[COPY3]], 0, [[COPY2]], 0, implicit $mode, implicit $exec - ; GFX12-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], killed [[V_CVT_SR_FP8_F32_e64_]], 0, 0, implicit $exec - ; GFX12-NEXT: S_ENDPGM 0 + ; GFX1170PLUS-LABEL: name: test_cvt_sr_fp8_f32_byte2 + ; GFX1170PLUS: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1170PLUS-NEXT: {{ $}} + ; GFX1170PLUS-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX1170PLUS-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX1170PLUS-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX1170PLUS-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX1170PLUS-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX1170PLUS-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; GFX1170PLUS-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[COPY4]], [[COPY4]], 228, 15, 15, -1, implicit $exec + ; GFX1170PLUS-NEXT: [[V_CVT_SR_FP8_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_SR_FP8_F32_e64 8, killed [[V_MOV_B32_dpp]], 0, [[COPY3]], 0, [[COPY2]], 0, implicit $mode, implicit $exec + ; GFX1170PLUS-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE]], killed [[V_CVT_SR_FP8_F32_e64_]], 0, 0, implicit $exec + ; GFX1170PLUS-NEXT: S_ENDPGM 0 %4:vgpr_32 = COPY $vgpr4 %3:vgpr_32 = COPY $vgpr3 %2:vgpr_32 = COPY $vgpr2 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll index b84fb520e0519..6f3c1abc70d76 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll @@ -3,6 +3,9 @@ ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9X,GFX942 %s ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9X,GFX950 %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX9X,GFX950 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1170,GFX1170-FAKE16 %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s @@ -32,6 +35,12 @@ define float @test_cvt_f32_bf8_byte0(i32 %a) { ; GFX950-NEXT: v_cvt_f32_bf8_e32 v0, v0 ; GFX950-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_f32_bf8_byte0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_f32_bf8_e32 v0, v0 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_f32_bf8_byte0: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -59,6 +68,12 @@ define float @test_cvt_f32_bf8_byte1(i32 %a) { ; GFX9X-NEXT: v_cvt_f32_bf8_sdwa v0, v0 src0_sel:BYTE_1 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_f32_bf8_byte1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_f32_bf8_byte1: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -86,6 +101,12 @@ define float @test_cvt_f32_bf8_byte2(i32 %a) { ; GFX9X-NEXT: v_cvt_f32_bf8_sdwa v0, v0 src0_sel:BYTE_2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_f32_bf8_byte2: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_f32_bf8_byte2: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -113,6 +134,12 @@ define float @test_cvt_f32_bf8_byte3(i32 %a) { ; GFX9X-NEXT: v_cvt_f32_bf8_sdwa v0, v0 src0_sel:BYTE_3 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_f32_bf8_byte3: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:3 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_f32_bf8_byte3: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -146,6 +173,12 @@ define float @test_cvt_f32_fp8_byte0(i32 %a) { ; GFX950-NEXT: v_cvt_f32_fp8_e32 v0, v0 ; GFX950-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_f32_fp8_byte0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_f32_fp8_e32 v0, v0 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_f32_fp8_byte0: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -173,6 +206,12 @@ define float @test_cvt_f32_fp8_byte1(i32 %a) { ; GFX9X-NEXT: v_cvt_f32_fp8_sdwa v0, v0 src0_sel:BYTE_1 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_f32_fp8_byte1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_f32_fp8_byte1: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -200,6 +239,12 @@ define float @test_cvt_f32_fp8_byte2(i32 %a) { ; GFX9X-NEXT: v_cvt_f32_fp8_sdwa v0, v0 src0_sel:BYTE_2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_f32_fp8_byte2: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_f32_fp8_byte2: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -227,6 +272,12 @@ define float @test_cvt_f32_fp8_byte3(i32 %a) { ; GFX9X-NEXT: v_cvt_f32_fp8_sdwa v0, v0 src0_sel:BYTE_3 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_f32_fp8_byte3: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:3 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_f32_fp8_byte3: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -254,6 +305,12 @@ define <2 x float> @test_cvt_pk_f32_bf8_word0(i32 %a) { ; GFX9X-NEXT: v_cvt_pk_f32_bf8_e32 v[0:1], v0 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_pk_f32_bf8_word0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_pk_f32_bf8_e32 v[0:1], v0 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_pk_f32_bf8_word0: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -281,6 +338,12 @@ define <2 x float> @test_cvt_pk_f32_bf8_word1(i32 %a) { ; GFX9X-NEXT: v_cvt_pk_f32_bf8_sdwa v[0:1], v0 src0_sel:WORD_1 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_pk_f32_bf8_word1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0] +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_pk_f32_bf8_word1: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -308,6 +371,12 @@ define <2 x float> @test_cvt_pk_f32_fp8_word0(i32 %a) { ; GFX9X-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_pk_f32_fp8_word0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_pk_f32_fp8_word0: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -335,6 +404,12 @@ define <2 x float> @test_cvt_pk_f32_fp8_word1(i32 %a) { ; GFX9X-NEXT: v_cvt_pk_f32_fp8_sdwa v[0:1], v0 src0_sel:WORD_1 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_pk_f32_fp8_word1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_pk_f32_fp8_e64 v[0:1], v0 op_sel:[1,0] +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_pk_f32_fp8_word1: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -363,6 +438,22 @@ define i32 @test_cvt_pk_bf8_f32_word0(float %x, float %y, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-TRUE16-LABEL: test_cvt_pk_bf8_f32_word0: +; GFX1170-TRUE16: ; %bb.0: +; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-TRUE16-NEXT: v_cvt_pk_bf8_f32 v2.l, v0, v1 +; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1170-FAKE16-LABEL: test_cvt_pk_bf8_f32_word0: +; GFX1170-FAKE16: ; %bb.0: +; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-FAKE16-NEXT: v_cvt_pk_bf8_f32 v2, v0, v1 +; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-FAKE16-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-TRUE16-LABEL: test_cvt_pk_bf8_f32_word0: ; GFX12-TRUE16: ; %bb.0: ; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -417,6 +508,22 @@ define i32 @test_cvt_pk_bf8_f32_word1(float %x, float %y, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-TRUE16-LABEL: test_cvt_pk_bf8_f32_word1: +; GFX1170-TRUE16: ; %bb.0: +; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-TRUE16-NEXT: v_cvt_pk_bf8_f32 v2.h, v0, v1 op_sel:[0,0,1] +; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1170-FAKE16-LABEL: test_cvt_pk_bf8_f32_word1: +; GFX1170-FAKE16: ; %bb.0: +; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-FAKE16-NEXT: v_cvt_pk_bf8_f32 v2, v0, v1 op_sel:[0,0,1] +; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-FAKE16-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-TRUE16-LABEL: test_cvt_pk_bf8_f32_word1: ; GFX12-TRUE16: ; %bb.0: ; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -470,6 +577,22 @@ define i32 @test_cvt_pk_fp8_f32_word0(float %x, float %y, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-TRUE16-LABEL: test_cvt_pk_fp8_f32_word0: +; GFX1170-TRUE16: ; %bb.0: +; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.l, v0, v1 +; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1170-FAKE16-LABEL: test_cvt_pk_fp8_f32_word0: +; GFX1170-FAKE16: ; %bb.0: +; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 +; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-FAKE16-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-TRUE16-LABEL: test_cvt_pk_fp8_f32_word0: ; GFX12-TRUE16: ; %bb.0: ; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -524,6 +647,22 @@ define i32 @test_cvt_pk_fp8_f32_word1(float %x, float %y, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1: +; GFX1170-TRUE16: ; %bb.0: +; GFX1170-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-TRUE16-NEXT: v_cvt_pk_fp8_f32 v2.h, v0, v1 op_sel:[0,0,1] +; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1170-FAKE16-LABEL: test_cvt_pk_fp8_f32_word1: +; GFX1170-FAKE16: ; %bb.0: +; GFX1170-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-FAKE16-NEXT: v_cvt_pk_fp8_f32 v2, v0, v1 op_sel:[0,0,1] +; GFX1170-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-FAKE16-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-FAKE16-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-TRUE16-LABEL: test_cvt_pk_fp8_f32_word1: ; GFX12-TRUE16: ; %bb.0: ; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -577,6 +716,14 @@ define i32 @test_cvt_sr_bf8_f32_byte0(float %x, i32 %r, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_sr_bf8_f32_byte0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_sr_bf8_f32_byte0: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -610,6 +757,14 @@ define i32 @test_cvt_sr_bf8_f32_byte1(float %x, i32 %r, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_sr_bf8_f32_byte1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 byte_sel:1 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_sr_bf8_f32_byte1: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -643,6 +798,14 @@ define i32 @test_cvt_sr_bf8_f32_byte2(float %x, i32 %r, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_sr_bf8_f32_byte2: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 byte_sel:2 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_sr_bf8_f32_byte2: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -676,6 +839,14 @@ define i32 @test_cvt_sr_bf8_f32_byte3(float %x, i32 %r, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_sr_bf8_f32_byte3: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 byte_sel:3 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_sr_bf8_f32_byte3: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -708,6 +879,14 @@ define i32 @test_cvt_sr_fp8_f32_byte0(float %x, i32 %r, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_sr_fp8_f32_byte0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_sr_fp8_f32_byte0: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -741,6 +920,14 @@ define i32 @test_cvt_sr_fp8_f32_byte1(float %x, i32 %r, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_sr_fp8_f32_byte1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:1 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_sr_fp8_f32_byte1: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -774,6 +961,14 @@ define i32 @test_cvt_sr_fp8_f32_byte2(float %x, i32 %r, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_sr_fp8_f32_byte2: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:2 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_sr_fp8_f32_byte2: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -807,6 +1002,14 @@ define i32 @test_cvt_sr_fp8_f32_byte3(float %x, i32 %r, i32 %old) { ; GFX9X-NEXT: v_mov_b32_e32 v0, v2 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_cvt_sr_fp8_f32_byte3: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:3 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_mov_b32_e32 v0, v2 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_cvt_sr_fp8_f32_byte3: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -839,6 +1042,14 @@ define float @test_sext_cvt_f32_fp8(i16 %a) { ; GFX9X-NEXT: v_cvt_f32_fp8_sdwa v0, v0 src0_sel:BYTE_1 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_sext_cvt_f32_fp8: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_sext_cvt_f32_fp8: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -872,6 +1083,14 @@ define float @test_sext_cvt_f32_bf8(i16 %a) { ; GFX9X-NEXT: v_cvt_f32_bf8_sdwa v0, v0 src0_sel:BYTE_1 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_sext_cvt_f32_bf8: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_cvt_f32_bf8_e64 v0, v0 byte_sel:1 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_sext_cvt_f32_bf8: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -905,6 +1124,14 @@ define <2 x float> @test_sext_cvt_pk_f32_bf8_word1(i16 %a) { ; GFX9X-NEXT: v_cvt_pk_f32_bf8_sdwa v[0:1], v0 src0_sel:WORD_1 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_sext_cvt_pk_f32_bf8_word1: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_cvt_pk_f32_bf8_e64 v[0:1], v0 op_sel:[1,0] +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_sext_cvt_pk_f32_bf8_word1: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -938,6 +1165,14 @@ define <2 x float> @test_sext_cvt_pk_f32_fp8_word0(i16 %a) { ; GFX9X-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0 ; GFX9X-NEXT: s_setpc_b64 s[30:31] ; +; GFX1170-LABEL: test_sext_cvt_pk_f32_fp8_word0: +; GFX1170: ; %bb.0: +; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1170-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX1170-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1170-NEXT: v_cvt_pk_f32_fp8_e32 v[0:1], v0 +; GFX1170-NEXT: s_setpc_b64 s[30:31] +; ; GFX12-LABEL: test_sext_cvt_pk_f32_fp8_word0: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll index c5daf21a43dee..d5cff22756b53 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll @@ -107,4 +107,4 @@ declare float @llvm.amdgcn.fmul.legacy(float, float) #1 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } -attributes #2 = { nounwind "denormal-fp-math"="preserve-sign" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } +attributes #2 = { nounwind denormal_fpenv(preservesign) "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir index 689d1472d6010..94de6dd31cad5 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.large.mir @@ -103,9 +103,10 @@ ; GCN-NEXT: ; implicit-def: $vgpr197 ; GCN-NEXT: ; iglp_opt mask(0x00000002) ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b128 v230, v[64:67] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b128 v230, v[68:71] offset:1024 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: buffer_load_dwordx4 v[160:163], v226, s[8:11], 0 offen offset:64 sc0 sc1 @@ -150,10 +151,11 @@ ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[80:95], v[64:65], v[152:153], 0 ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b128 v230, v[160:163] ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[80:95], v[66:67], v[154:155], v[80:95] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b128 v230, v[164:167] offset:1024 ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[64:79], v[168:169], v[152:153], 0 ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[64:79], v[170:171], v[154:155], v[64:79] @@ -199,9 +201,10 @@ ; GCN-NEXT: s_waitcnt vmcnt(8) ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b128 v230, v[152:155] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b128 v230, v[160:163] offset:1024 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: buffer_load_dwordx4 v[152:155], v226, s[8:11], 0 offen offset:192 sc0 sc1 @@ -280,9 +283,10 @@ ; GCN-NEXT: s_waitcnt vmcnt(8) ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b128 v230, v[152:155] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b128 v230, v[226:229] offset:1024 ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: s_waitcnt vmcnt(8) @@ -322,15 +326,16 @@ ; GCN-NEXT: s_waitcnt vmcnt(8) ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b64 v199, v[238:239] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v200, v[240:241] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v201, v[242:243] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v202, v[244:245] ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: buffer_load_dwordx2 v[192:193], v247, s[0:3], 0 offen sc0 sc1 @@ -649,15 +654,16 @@ ; GCN-NEXT: s_waitcnt vmcnt(8) ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b64 v199, v[188:189] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v200, v[190:191] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v201, v[192:193] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v202, v[194:195] ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[32:47], v[146:147], v[126:127], v[32:47] ; GCN-NEXT: v_exp_f32_e32 v101, v125 @@ -792,16 +798,17 @@ ; GCN-NEXT: s_waitcnt vmcnt(8) ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b64 v199, v[126:127] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v200, v[150:151] ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[0:15], v[130:131], v[144:145], v[0:15] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v201, v[152:153] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v202, v[154:155] ; GCN-NEXT: v_fma_f32 v127, s4, v84, -v128 ; GCN-NEXT: v_exp_f32_e32 v84, v129 @@ -942,18 +949,19 @@ ; GCN-NEXT: s_waitcnt vmcnt(8) ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b64 v199, v[150:151] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v200, v[152:153] ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[0:15], v[132:133], v[142:143], v[0:15] ; GCN-NEXT: v_cvt_f16_f32_e32 v132, v125 ; GCN-NEXT: v_exp_f32_e32 v130, v158 ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v201, v[154:155] ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b64 v202, v[156:157] ; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: s_waitcnt vmcnt(8) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir index 0887fdf0844b0..0a8d7acd187fc 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.exp.small.mir @@ -39,6 +39,7 @@ ; GCN-NEXT: v_add_u32_e32 v76, s20, v76 ; GCN-NEXT: v_and_b32_e32 v76, 0x1fffffff, v76 ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b128 v48, v[0:3] ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: buffer_load_dwordx4 v[32:35], v4, s[0:3], 0 offen offset:64 sc0 sc1 @@ -91,6 +92,7 @@ ; GCN-NEXT: s_waitcnt vmcnt(8) ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b128 v48, v[32:35] ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[16:31], v[36:37], v[40:41], v[16:31] ; GCN-NEXT: ;;#ASMSTART @@ -138,12 +140,13 @@ ; GCN-NEXT: v_perm_b32 v71, v74, v72, s3 ; GCN-NEXT: v_perm_b32 v72, v75, v73, s2 ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b32 v76, v70 ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b32 v77, v71 ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b32 v78, v72 ; GCN-NEXT: v_mul_f32_e32 v74, s4, v20 ; GCN-NEXT: v_mfma_f32_32x32x8_f16 v[0:15], v[68:69], v[64:65], v[0:15] @@ -197,7 +200,7 @@ ; GCN-NEXT: ds_bpermute_b32 v65, v66, v64 ; GCN-NEXT: v_perm_b32 v68, v75, v73, s3 ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b32 v79, v68 ; GCN-NEXT: ; implicit-def: $vgpr84 ; GCN-NEXT: v_max_f32_e32 v65, v65, v65 @@ -310,6 +313,7 @@ ; GCN-NEXT: s_waitcnt vmcnt(8) ; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: buffer_wbl2 sc0 sc1 + ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: ds_write_b32 v76, v31 ; GCN-NEXT: v_mul_f32_e32 v31, 0x3fb8aa3b, v67 ; GCN-NEXT: v_exp_f32_e32 v31, v31 @@ -317,13 +321,13 @@ ; GCN-NEXT: v_pack_b32_f16 v18, v19, v86 ; GCN-NEXT: v_pack_b32_f16 v19, v22, v89 ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b32 v77, v64 ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b32 v78, v90 ; GCN-NEXT: buffer_wbl2 sc0 sc1 - ; GCN-NEXT: s_waitcnt lgkmcnt(0) + ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: ds_write_b32 v79, v65 ; GCN-NEXT: v_mul_f32_e32 v64, 0x3fb8aa3b, v73 ; GCN-NEXT: v_mul_f32_e32 v65, 0x3fb8aa3b, v87 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll index 910c55a041ede..f353deab46672 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll @@ -2,77 +2,82 @@ ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s -declare i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1), i32) -declare <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1), i32) -declare <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1), i32) -declare i32 @llvm.amdgcn.flat.load.monitor.b32.i32(ptr, i32) -declare <2 x i32> @llvm.amdgcn.flat.load.monitor.b64.v2i32(ptr, i32) -declare <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr, i32) - -define amdgpu_ps void @global_load_monitor_b32_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: global_load_monitor_b32_vaddr: +declare i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1), i32, metadata) +declare <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1), i32, metadata) +declare <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1), i32, metadata) +declare i32 @llvm.amdgcn.flat.load.monitor.b32.i32(ptr, i32, metadata) +declare <2 x i32> @llvm.amdgcn.flat.load.monitor.b64.v2i32(ptr, i32, metadata) +declare <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr, i32, metadata) + + +define amdgpu_ps void @global_load_monitor_b32_vaddr_relaxed_sys(ptr addrspace(1) %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: global_load_monitor_b32_vaddr_relaxed_sys: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: global_load_monitor_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT +; GFX1250-NEXT: global_load_monitor_b32 v0, v[0:1], off offset:32 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b32 v[2:3], v0, off ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4 - %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 1) + %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 0, metadata !0) store i32 %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @global_load_monitor_b32_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: global_load_monitor_b32_saddr: +define amdgpu_ps void @global_load_monitor_b32_saddr_relaxed_sys(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: global_load_monitor_b32_saddr_relaxed_sys: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: v_mov_b32_e32 v2, 0 -; GFX1250-NEXT: global_load_monitor_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_HT scope:SCOPE_SE +; GFX1250-NEXT: global_load_monitor_b32 v2, v2, s[0:1] offset:32 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b32 v[0:1], v2, off ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4 - %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 10) + %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 0, metadata !0) store i32 %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @global_load_monitor_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: global_load_monitor_b64_vaddr: +define amdgpu_ps void @global_load_monitor_b64_vaddr_acquire_agent(ptr addrspace(1) %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: global_load_monitor_b64_vaddr_acquire_agent: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: global_load_monitor_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV +; GFX1250-NEXT: global_load_monitor_b64 v[0:1], v[0:1], off offset:32 scope:SCOPE_DEV +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4 - %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 22) + %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 2, metadata !1) store <2 x i32> %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @global_load_monitor_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: global_load_monitor_b64_saddr: +define amdgpu_ps void @global_load_monitor_b64_saddr_acquire_agent(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: global_load_monitor_b64_saddr_acquire_agent: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: v_mov_b32_e32 v2, 0 -; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS +; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v2, s[0:1] offset:32 scope:SCOPE_DEV +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4 - %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 27) + %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 2, metadata !1) store <2 x i32> %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @global_load_monitor_b128_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: global_load_monitor_b128_vaddr: +define amdgpu_ps void @global_load_monitor_b128_vaddr_seq_cst_workgroup(ptr addrspace(1) %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: global_load_monitor_b128_vaddr_seq_cst_workgroup: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: global_load_monitor_b128 v[4:7], v[0:1], off offset:32 @@ -81,122 +86,137 @@ define amdgpu_ps void @global_load_monitor_b128_vaddr(ptr addrspace(1) %addr, pt ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4 - %val = call <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1) %gep, i32 0) + %val = call <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1) %gep, i32 5, metadata !2) store <4 x i32> %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @global_load_monitor_b128_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: global_load_monitor_b128_saddr: +define amdgpu_ps void @global_load_monitor_b128_saddr_seq_cst_workgroup(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: global_load_monitor_b128_saddr_seq_cst_workgroup: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: v_mov_b32_e32 v2, 0 -; GFX1250-NEXT: global_load_monitor_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_NT +; GFX1250-NEXT: global_load_monitor_b128 v[2:5], v2, s[0:1] offset:32 ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4 - %val = call <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1) %gep, i32 1) + %val = call <4 x i32> @llvm.amdgcn.global.load.monitor.b128.v4i32(ptr addrspace(1) %gep, i32 5, metadata !2) store <4 x i32> %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @flat_load_monitor_b32(ptr %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: flat_load_monitor_b32: +define amdgpu_ps void @flat_load_monitor_b32_seq_cst_sys(ptr %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: flat_load_monitor_b32_seq_cst_sys: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: flat_load_monitor_b32 v0, v[0:1] offset:32 th:TH_LOAD_HT scope:SCOPE_SE +; GFX1250-NEXT: flat_load_monitor_b32 v0, v[0:1] offset:32 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: global_inv scope:SCOPE_SYS +; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b32 v[2:3], v0, off ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr inbounds i64, ptr addrspace(0) %addr, i32 4 - %val = call i32 @llvm.amdgcn.flat.load.monitor.b32.i32(ptr addrspace(0) %gep, i32 10) + %val = call i32 @llvm.amdgcn.flat.load.monitor.b32.i32(ptr addrspace(0) %gep, i32 5, metadata !0) store i32 %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @flat_load_monitor_b64(ptr %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: flat_load_monitor_b64: +define amdgpu_ps void @flat_load_monitor_b64_seq_cst_agent(ptr %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: flat_load_monitor_b64_seq_cst_agent: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: flat_load_monitor_b64 v[0:1], v[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV +; GFX1250-NEXT: flat_load_monitor_b64 v[0:1], v[0:1] offset:32 scope:SCOPE_DEV ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: global_inv scope:SCOPE_DEV +; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr inbounds i64, ptr addrspace(0) %addr, i32 4 - %val = call <2 x i32> @llvm.amdgcn.flat.load.monitor.b64.v2i32(ptr addrspace(0) %gep, i32 22) + %val = call <2 x i32> @llvm.amdgcn.flat.load.monitor.b64.v2i32(ptr addrspace(0) %gep, i32 5, metadata !1) store <2 x i32> %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @flat_load_monitor_b128(ptr %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: flat_load_monitor_b128: +define amdgpu_ps void @flat_load_monitor_b128_acquire_sys(ptr %addr, ptr addrspace(1) %use) { +; GFX1250-LABEL: flat_load_monitor_b128_acquire_sys: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: flat_load_monitor_b128 v[4:7], v[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS +; GFX1250-NEXT: flat_load_monitor_b128 v[4:7], v[0:1] offset:32 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: global_inv scope:SCOPE_SYS +; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off ; GFX1250-NEXT: s_endpgm entry: %gep = getelementptr inbounds i64, ptr addrspace(0) %addr, i32 4 - %val = call <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr addrspace(0) %gep, i32 27) + %val = call <4 x i32> @llvm.amdgcn.flat.load.monitor.b128.v4i32(ptr addrspace(0) %gep, i32 2, metadata !0) store <4 x i32> %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @global_load_monitor_b32_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) { -; GFX1250-LABEL: global_load_monitor_b32_saddr_scale_offset: +define amdgpu_ps void @global_load_monitor_b32_saddr_scale_offset_acquire_agent(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) { +; GFX1250-LABEL: global_load_monitor_b32_saddr_scale_offset_acquire_agent: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: global_load_monitor_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_NT +; GFX1250-NEXT: global_load_monitor_b32 v2, v2, s[0:1] scale_offset scope:SCOPE_DEV +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: global_inv scope:SCOPE_DEV ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b32 v[0:1], v2, off ; GFX1250-NEXT: s_endpgm entry: %idxprom = sext i32 %idx to i64 %gep = getelementptr i32, ptr addrspace(1) %addr, i64 %idxprom - %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 1) + %val = call i32 @llvm.amdgcn.global.load.monitor.b32.i32(ptr addrspace(1) %gep, i32 2, metadata !1) store i32 %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @global_load_monitor_b64_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) { -; GFX1250-LABEL: global_load_monitor_b64_saddr_scale_offset: +define amdgpu_ps void @global_load_monitor_b64_saddr_scale_offset_acquire_workgroup(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) { +; GFX1250-LABEL: global_load_monitor_b64_saddr_scale_offset_acquire_workgroup: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 -; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_NT +; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v2, s[0:1] scale_offset ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off ; GFX1250-NEXT: s_endpgm entry: %idxprom = sext i32 %idx to i64 %gep = getelementptr i64, ptr addrspace(1) %addr, i64 %idxprom - %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 1) + %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 2, metadata !2) store <2 x i32> %val, ptr addrspace(1) %use ret void } -define amdgpu_ps void @global_load_monitor_b64_saddr_no_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) { -; GFX1250-LABEL: global_load_monitor_b64_saddr_no_scale_offset: +define amdgpu_ps void @global_load_monitor_b64_saddr_no_scale_offset_seq_cst_sys(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %idx) { +; GFX1250-LABEL: global_load_monitor_b64_saddr_no_scale_offset_seq_cst_sys: ; GFX1250: ; %bb.0: ; %entry ; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1] -; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v[2:3], off th:TH_LOAD_NT +; GFX1250-NEXT: global_load_monitor_b64 v[2:3], v[2:3], off scope:SCOPE_SYS +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: global_inv scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off ; GFX1250-NEXT: s_endpgm entry: %idxprom = sext i32 %idx to i64 %gep = getelementptr i32, ptr addrspace(1) %addr, i64 %idxprom - %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 1) + %val = call <2 x i32> @llvm.amdgcn.global.load.monitor.b64.v2i32(ptr addrspace(1) %gep, i32 5, metadata !0) store <2 x i32> %val, ptr addrspace(1) %use ret void } + +!0 = !{ !"" } +!1 = !{ !"agent" } +!2 = !{ !"workgroup" } + ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX1250-GISEL: {{.*}} ; GFX1250-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll index 352af044b0a6d..f66ad928d261d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.to.lds.ll @@ -267,9 +267,8 @@ main_body: define amdgpu_ps void @buffer_load_lds_dword_volatile(ptr addrspace(7) nocapture inreg %gptr, i32 %off, ptr addrspace(3) inreg %lptr) { ; GFX90A-LABEL: buffer_load_lds_dword_volatile: ; GFX90A: ; %bb.0: ; %main_body -; GFX90A-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX90A-NEXT: s_mov_b32 m0, s5 -; GFX90A-NEXT: s_nop 0 +; GFX90A-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX90A-NEXT: buffer_load_dword v0, s[0:3], 0 offen glc lds ; GFX90A-NEXT: s_waitcnt vmcnt(0) ; GFX90A-NEXT: buffer_load_dword v0, s[0:3], 0 offen offset:256 lds @@ -278,9 +277,8 @@ define amdgpu_ps void @buffer_load_lds_dword_volatile(ptr addrspace(7) nocapture ; ; GFX942-LABEL: buffer_load_lds_dword_volatile: ; GFX942: ; %bb.0: ; %main_body -; GFX942-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX942-NEXT: s_mov_b32 m0, s5 -; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX942-NEXT: buffer_load_dword v0, s[0:3], 0 offen sc0 sc1 lds ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: buffer_load_dword v0, s[0:3], 0 offen offset:256 lds diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll index 6248da0c0e706..909be6000bb1c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll @@ -7,8 +7,8 @@ ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=GFX11-PACKED,GFX11-PACKED-FAKE16 %s ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-TRUE16 %s ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-FAKE16 %s -; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-TRUE16 %s -; RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-FAKE16 %s +; RUN: llc < %s -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-TRUE16 %s +; RUN: llc < %s -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-FAKE16 %s define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data) { ; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll index 9983c09538201..38f7ea12251ee 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll @@ -37,7 +37,7 @@ define amdgpu_kernel void @rcp_f16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l @@ -73,7 +73,7 @@ define amdgpu_kernel void @rcp_f16( ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: v_rcp_f16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll index 477f0a610feec..130de84a9407d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll @@ -214,9 +214,9 @@ define amdgpu_kernel void @unsafe_amdgcn_sqrt_rsq_rcp_pat_f64(ptr addrspace(1) % } attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #2 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } -attributes #4 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } +attributes #2 = { nounwind denormal_fpenv(float: preservesign) } +attributes #3 = { nounwind denormal_fpenv(float: ieee|ieee) } +attributes #4 = { nounwind denormal_fpenv(float: ieee|ieee) } !0 = !{float 2.500000e+00} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll index 9f26745d83a64..efb6b20d6e730 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll @@ -37,7 +37,7 @@ define amdgpu_kernel void @rsq_f16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l @@ -73,7 +73,7 @@ define amdgpu_kernel void @rsq_f16( ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: v_rsq_f16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll index 27a8b35467218..fbccbd5ff29af 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll @@ -3,12 +3,51 @@ ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s ; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s -; GCN-LABEL: {{^}}test_wait_event: -; GFX11: s_wait_event 0x0 -; GFX12: s_wait_event 0x2 - -define amdgpu_ps void @test_wait_event() { +; GCN-LABEL: {{^}}test_wait_event_export_ready: +; GFX11: s_wait_event 0x2 +; GFX12: s_wait_event { export_ready: 1 } +define amdgpu_ps void @test_wait_event_export_ready() { entry: call void @llvm.amdgcn.s.wait.event.export.ready() ret void } + +; GCN-LABEL: {{^}}test_wait_event_0: +; GFX11: s_wait_event { dont_wait_export_ready: 0 } +; GFX12: s_wait_event { export_ready: 0 } +define amdgpu_ps void @test_wait_event_0() { + call void @llvm.amdgcn.s.wait.event(i16 0) + ret void +} + +; GCN-LABEL: {{^}}test_wait_event_1: +; GFX11: s_wait_event { dont_wait_export_ready: 1 } +; GFX12: s_wait_event 0x1 +define amdgpu_ps void @test_wait_event_1() { + call void @llvm.amdgcn.s.wait.event(i16 1) + ret void +} + +; GCN-LABEL: {{^}}test_wait_event_2: +; GFX11: s_wait_event 0x2 +; GFX12: s_wait_event { export_ready: 1 } +define amdgpu_ps void @test_wait_event_2() { + call void @llvm.amdgcn.s.wait.event(i16 2) + ret void +} + +; GCN-LABEL: {{^}}test_wait_event_3: +; GFX11: s_wait_event 0x3 +; GFX12: s_wait_event 0x3 +define amdgpu_ps void @test_wait_event_3() { + call void @llvm.amdgcn.s.wait.event(i16 3) + ret void +} + +; GCN-LABEL: {{^}}test_wait_event_max: +; GFX11: s_wait_event 0xffff +; GFX12: s_wait_event 0xffff +define amdgpu_ps void @test_wait_event_max() { + call void @llvm.amdgcn.s.wait.event(i16 -1) + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll index 568fb127d5c6d..c4f0b57f295da 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll @@ -4,7 +4,7 @@ ;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck --check-prefixes=GFX11 %s ;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-enable-prt-strict-null | FileCheck --check-prefixes=NOPRT %s ;RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1200 | FileCheck --check-prefixes=GFX12,GFX12-SDAG %s -;RUN: llc < %s -global-isel -mtriple=amdgcn -mcpu=gfx1200 | FileCheck --check-prefixes=GFX12,GFX12-GISEL %s +;RUN: llc < %s -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 | FileCheck --check-prefixes=GFX12,GFX12-GISEL %s define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { ; GFX6-LABEL: buffer_load: @@ -183,25 +183,62 @@ define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { ; NOPRT-NEXT: v_add_f32_e32 v2, v10, v2 ; NOPRT-NEXT: ; return to shader part epilog ; -; GFX12-LABEL: buffer_load_immoffs_large: -; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: v_mov_b32_e32 v8, 0 -; GFX12-NEXT: s_mov_b32 s4, 60 -; GFX12-NEXT: s_movk_i32 s5, 0x7ffc -; GFX12-NEXT: s_clause 0x1 -; GFX12-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], s4 idxen offset:4092 -; GFX12-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], s5 idxen offset:4092 -; GFX12-NEXT: s_mov_b32 s4, 0x8ffc -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: v_add_f32_e32 v1, v1, v5 -; GFX12-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], s4 idxen offset:4 -; GFX12-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v3, v3, v7 -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v1, v9, v1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-NEXT: v_dual_add_f32 v0, v8, v0 :: v_dual_add_f32 v3, v11, v3 -; GFX12-NEXT: v_add_f32_e32 v2, v10, v2 -; GFX12-NEXT: ; return to shader part epilog +; GFX12-SDAG-LABEL: buffer_load_immoffs_large: +; GFX12-SDAG: ; %bb.0: ; %main_body +; GFX12-SDAG-NEXT: v_mov_b32_e32 v8, 0 +; GFX12-SDAG-NEXT: s_mov_b32 s4, 60 +; GFX12-SDAG-NEXT: s_movk_i32 s5, 0x7ffc +; GFX12-SDAG-NEXT: s_clause 0x1 +; GFX12-SDAG-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], s4 idxen offset:4092 +; GFX12-SDAG-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], s5 idxen offset:4092 +; GFX12-SDAG-NEXT: s_mov_b32 s4, 0x8ffc +; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX12-SDAG-NEXT: v_add_f32_e32 v1, v1, v5 +; GFX12-SDAG-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], s4 idxen offset:4 +; GFX12-SDAG-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v3, v3, v7 +; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX12-SDAG-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v1, v9, v1 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-SDAG-NEXT: v_dual_add_f32 v0, v8, v0 :: v_dual_add_f32 v3, v11, v3 +; GFX12-SDAG-NEXT: v_add_f32_e32 v2, v10, v2 +; GFX12-SDAG-NEXT: ; return to shader part epilog +; +; GFX12-GISEL-LABEL: buffer_load_immoffs_large: +; GFX12-GISEL: ; %bb.0: ; %main_body +; GFX12-GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GFX12-GISEL-NEXT: s_mov_b32 s4, 60 +; GFX12-GISEL-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], s4 idxen offset:4092 +; GFX12-GISEL-NEXT: s_movk_i32 s4, 0x7ffc +; GFX12-GISEL-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], s4 idxen offset:4092 +; GFX12-GISEL-NEXT: s_mov_b32 s4, 0x8ffc +; GFX12-GISEL-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], s4 idxen offset:4 +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x2 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v3 +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x1 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s4, v4 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s5, v5 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s6, v6 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s7, v7 +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s8, v8 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s9, v9 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s10, v10 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s11, v11 +; GFX12-GISEL-NEXT: s_add_f32 s0, s0, s4 +; GFX12-GISEL-NEXT: s_add_f32 s1, s1, s5 +; GFX12-GISEL-NEXT: s_add_f32 s2, s2, s6 +; GFX12-GISEL-NEXT: s_add_f32 s3, s3, s7 +; GFX12-GISEL-NEXT: s_add_f32 s0, s8, s0 +; GFX12-GISEL-NEXT: s_add_f32 s1, s9, s1 +; GFX12-GISEL-NEXT: s_add_f32 s2, s10, s2 +; GFX12-GISEL-NEXT: s_add_f32 s3, s11, s3 +; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_2) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-GISEL-NEXT: ; return to shader part epilog main_body: %d.0 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4092, i32 60, i32 0) %d.1 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4092, i32 32764, i32 0) @@ -837,17 +874,36 @@ define amdgpu_cs float @buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa ; NOPRT-NEXT: v_mov_b32_e32 v0, v6 ; NOPRT-NEXT: ; return to shader part epilog ; -; GFX12-LABEL: buffer_load_v4i32_tfe: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v7, 2 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 -; GFX12-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v2 -; GFX12-NEXT: buffer_load_format_xyzw v[2:6], v7, s[0:3], null idxen tfe -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off -; GFX12-NEXT: v_mov_b32_e32 v0, v6 -; GFX12-NEXT: ; return to shader part epilog +; GFX12-SDAG-LABEL: buffer_load_v4i32_tfe: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v7, 2 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-SDAG-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v2 +; GFX12-SDAG-NEXT: buffer_load_format_xyzw v[2:6], v7, s[0:3], null idxen tfe +; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX12-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v6 +; GFX12-SDAG-NEXT: ; return to shader part epilog +; +; GFX12-GISEL-LABEL: buffer_load_v4i32_tfe: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v7, 2 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v2 +; GFX12-GISEL-NEXT: buffer_load_format_xyzw v[2:6], v7, s[0:3], null idxen tfe +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v5 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v2, s0 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2 +; GFX12-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v6 +; GFX12-GISEL-NEXT: ; return to shader part epilog %load = call { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4i32i32s(<4 x i32> %rsrc, i32 2, i32 0, i32 0, i32 0) %data = extractvalue { <4 x i32>, i32 } %load, 0 store <4 x i32> %data, ptr addrspace(1) %out @@ -912,17 +968,36 @@ define amdgpu_cs float @buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa ; NOPRT-NEXT: v_mov_b32_e32 v0, v6 ; NOPRT-NEXT: ; return to shader part epilog ; -; GFX12-LABEL: buffer_load_v4f32_tfe: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 -; GFX12-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v2 -; GFX12-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], null idxen tfe -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b128 v[0:1], v[2:5], off -; GFX12-NEXT: v_mov_b32_e32 v0, v6 -; GFX12-NEXT: ; return to shader part epilog +; GFX12-SDAG-LABEL: buffer_load_v4f32_tfe: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-SDAG-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v2 +; GFX12-SDAG-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], null idxen tfe +; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX12-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v6 +; GFX12-SDAG-NEXT: ; return to shader part epilog +; +; GFX12-GISEL-LABEL: buffer_load_v4f32_tfe: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, v2 :: v_dual_mov_b32 v6, v2 +; GFX12-GISEL-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], null idxen tfe +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v5 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v2, s0 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v4, s2 +; GFX12-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off +; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v6 +; GFX12-GISEL-NEXT: ; return to shader part epilog %load = call { <4 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = extractvalue { <4 x float>, i32 } %load, 0 store <4 x float> %data, ptr addrspace(1) %out @@ -985,17 +1060,35 @@ define amdgpu_cs float @buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa ; NOPRT-NEXT: v_mov_b32_e32 v0, v5 ; NOPRT-NEXT: ; return to shader part epilog ; -; GFX12-LABEL: buffer_load_v3i32_tfe: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 -; GFX12-NEXT: v_mov_b32_e32 v5, v2 -; GFX12-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], null idxen tfe -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off -; GFX12-NEXT: v_mov_b32_e32 v0, v5 -; GFX12-NEXT: ; return to shader part epilog +; GFX12-SDAG-LABEL: buffer_load_v3i32_tfe: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX12-SDAG-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], null idxen tfe +; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX12-SDAG-NEXT: global_store_b96 v[0:1], v[2:4], off +; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v5 +; GFX12-SDAG-NEXT: ; return to shader part epilog +; +; GFX12-GISEL-LABEL: buffer_load_v3i32_tfe: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX12-GISEL-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], null idxen tfe +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s2 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX12-GISEL-NEXT: global_store_b96 v[0:1], v[2:4], off +; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v5 +; GFX12-GISEL-NEXT: ; return to shader part epilog %load = call { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = extractvalue { <3 x i32>, i32 } %load, 0 store <3 x i32> %data, ptr addrspace(1) %out @@ -1058,17 +1151,35 @@ define amdgpu_cs float @buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa ; NOPRT-NEXT: v_mov_b32_e32 v0, v5 ; NOPRT-NEXT: ; return to shader part epilog ; -; GFX12-LABEL: buffer_load_v3f32_tfe: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 -; GFX12-NEXT: v_mov_b32_e32 v5, v2 -; GFX12-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], null idxen tfe -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b96 v[0:1], v[2:4], off -; GFX12-NEXT: v_mov_b32_e32 v0, v5 -; GFX12-NEXT: ; return to shader part epilog +; GFX12-SDAG-LABEL: buffer_load_v3f32_tfe: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX12-SDAG-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], null idxen tfe +; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX12-SDAG-NEXT: global_store_b96 v[0:1], v[2:4], off +; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v5 +; GFX12-SDAG-NEXT: ; return to shader part epilog +; +; GFX12-GISEL-LABEL: buffer_load_v3f32_tfe: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX12-GISEL-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], null idxen tfe +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v4 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-GISEL-NEXT: v_mov_b32_e32 v4, s2 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 +; GFX12-GISEL-NEXT: global_store_b96 v[0:1], v[2:4], off +; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v5 +; GFX12-GISEL-NEXT: ; return to shader part epilog %load = call { <3 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = extractvalue { <3 x float>, i32 } %load, 0 store <3 x float> %data, ptr addrspace(1) %out @@ -1128,16 +1239,30 @@ define amdgpu_cs float @buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa ; NOPRT-NEXT: v_mov_b32_e32 v0, v4 ; NOPRT-NEXT: ; return to shader part epilog ; -; GFX12-LABEL: buffer_load_v2i32_tfe: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 -; GFX12-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], null idxen tfe -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off -; GFX12-NEXT: v_mov_b32_e32 v0, v4 -; GFX12-NEXT: ; return to shader part epilog +; GFX12-SDAG-LABEL: buffer_load_v2i32_tfe: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-SDAG-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], null idxen tfe +; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX12-SDAG-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v4 +; GFX12-SDAG-NEXT: ; return to shader part epilog +; +; GFX12-GISEL-LABEL: buffer_load_v2i32_tfe: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-GISEL-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], null idxen tfe +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX12-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v4 +; GFX12-GISEL-NEXT: ; return to shader part epilog %load = call { <2 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = extractvalue { <2 x i32>, i32 } %load, 0 store <2 x i32> %data, ptr addrspace(1) %out @@ -1197,16 +1322,30 @@ define amdgpu_cs float @buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa ; NOPRT-NEXT: v_mov_b32_e32 v0, v4 ; NOPRT-NEXT: ; return to shader part epilog ; -; GFX12-LABEL: buffer_load_v2f32_tfe: -; GFX12: ; %bb.0: -; GFX12-NEXT: v_mov_b32_e32 v2, 0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 -; GFX12-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], null idxen tfe -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off -; GFX12-NEXT: v_mov_b32_e32 v0, v4 -; GFX12-NEXT: ; return to shader part epilog +; GFX12-SDAG-LABEL: buffer_load_v2f32_tfe: +; GFX12-SDAG: ; %bb.0: +; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-SDAG-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], null idxen tfe +; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX12-SDAG-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v4 +; GFX12-SDAG-NEXT: ; return to shader part epilog +; +; GFX12-GISEL-LABEL: buffer_load_v2f32_tfe: +; GFX12-GISEL: ; %bb.0: +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1) +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v4, v2 +; GFX12-GISEL-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], null idxen tfe +; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v2 +; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v3 +; GFX12-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX12-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off +; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, v4 +; GFX12-GISEL-NEXT: ; return to shader part epilog %load = call { <2 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) %data = extractvalue { <2 x float>, i32 } %load, 0 store <2 x float> %data, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll index 4f970750a796e..d138a9e893af4 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll @@ -9,8 +9,8 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-FAKE16 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-TRUE16 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-SDAG,GFX12-PACKED-SDAG-FAKE16 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-TRUE16 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-FAKE16 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-TRUE16 %s +; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefixes=GFX12-PACKED,GFX12-PACKED-GISEL,GFX12-PACKED-GISEL-FAKE16 %s define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data, i32 %vindex) { ; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll index 1f259ac96be42..b11eafd4a821a 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.shuffle.ll @@ -193,16 +193,16 @@ define float @test_wave_shuffle_float(float %val, i32 %idx) { ; GFX11-W64-GISEL-NEXT: v_permlane64_b32 v2, v0 ; GFX11-W64-GISEL-NEXT: ds_bpermute_b32 v2, v1, v2 ; GFX11-W64-GISEL-NEXT: s_mov_b64 exec, s[0:1] -; GFX11-W64-GISEL-NEXT: ds_bpermute_b32 v0, v1, v0 ; GFX11-W64-GISEL-NEXT: v_mbcnt_lo_u32_b32 v3, -1, 0 -; GFX11-W64-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-W64-GISEL-NEXT: ds_bpermute_b32 v0, v1, v0 ; GFX11-W64-GISEL-NEXT: v_xor_b32_e32 v1, v3, v1 ; GFX11-W64-GISEL-NEXT: s_waitcnt lgkmcnt(1) ; GFX11-W64-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX11-W64-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-W64-GISEL-NEXT: v_and_b32_e32 v1, 32, v1 -; GFX11-W64-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-W64-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GFX11-W64-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-W64-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-W64-GISEL-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc ; GFX11-W64-GISEL-NEXT: s_xor_saveexec_b64 s[0:1], -1 ; GFX11-W64-GISEL-NEXT: scratch_load_b32 v2, off, s32 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll index 117a169069782..4769f0f62fdf7 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll @@ -57,7 +57,7 @@ define amdgpu_kernel void @ceil_f16( ; GFX11-NEXT: s_mov_b32 s8, s2 ; GFX11-NEXT: s_mov_b32 s9, s3 ; GFX11-NEXT: s_mov_b32 s4, s0 -; GFX11-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-NEXT: s_mov_b32 s5, s1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_ceil_f16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll index 1485e3f88f942..6e028f080b481 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.exp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.ll @@ -7158,6 +7158,6 @@ declare <2 x half> @llvm.exp.v2f16(<2 x half>) #2 declare <3 x half> @llvm.exp.v3f16(<3 x half>) #2 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2 -attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(float: ieee|preservesign) } +attributes #1 = { denormal_fpenv(float: dynamic|dynamic) } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll index c4204417362a4..bf8197a4cd9cb 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.ll @@ -7391,6 +7391,6 @@ declare <2 x half> @llvm.exp10.v2f16(<2 x half>) #2 declare <3 x half> @llvm.exp10.v3f16(<3 x half>) #2 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2 -attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(float: ieee|preservesign) } +attributes #1 = { denormal_fpenv(float: dynamic|dynamic) } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll index 21c7f56aa0816..caa771326d847 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll @@ -3777,8 +3777,8 @@ declare <2 x half> @llvm.exp2.v2f16(<2 x half>) #2 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2 declare <3 x half> @llvm.exp2.v3f16(<3 x half>) #2 -attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(float: ieee|preservesign) } +attributes #1 = { denormal_fpenv(float: dynamic|dynamic) } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN-GISEL: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll index 868e69dfbd352..f32d8af2ce11a 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll @@ -57,7 +57,7 @@ define amdgpu_kernel void @floor_f16( ; GFX11-NEXT: s_mov_b32 s8, s2 ; GFX11-NEXT: s_mov_b32 s9, s3 ; GFX11-NEXT: s_mov_b32 s4, s0 -; GFX11-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-NEXT: s_mov_b32 s5, s1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_floor_f16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll index a32a456c102dd..146956c5908ea 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll @@ -177,17 +177,18 @@ define amdgpu_kernel void @fmuladd_f16( ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s13, s3 ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s16, s4 ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s17, s5 -; GFX11-FLUSH-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 -; GFX11-FLUSH-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], 0 -; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s12, s6 -; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s13, s7 +; GFX11-FLUSH-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 +; GFX11-FLUSH-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 +; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s4, s6 +; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s5, s7 +; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s6, s10 +; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s7, s11 ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s8, s0 -; GFX11-FLUSH-TRUE16-NEXT: buffer_load_u16 v2, off, s[12:15], 0 +; GFX11-FLUSH-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0 ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l +; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h ; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FLUSH-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX11-FLUSH-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FLUSH-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l ; GFX11-FLUSH-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 @@ -242,14 +243,14 @@ define amdgpu_kernel void @fmuladd_f16( ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s17, s5 ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s20, s6 ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX11-DENORM-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 -; GFX11-DENORM-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], 0 -; GFX11-DENORM-TRUE16-NEXT: buffer_load_u16 v2, off, s[20:23], 0 +; GFX11-DENORM-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 +; GFX11-DENORM-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 +; GFX11-DENORM-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[20:23], 0 ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-DENORM-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l -; GFX11-DENORM-TRUE16-NEXT: buffer_store_b16 v2, off, s[8:11], 0 +; GFX11-DENORM-TRUE16-NEXT: v_fmac_f16_e32 v1.l, v0.l, v0.h +; GFX11-DENORM-TRUE16-NEXT: buffer_store_b16 v1, off, s[8:11], 0 ; GFX11-DENORM-TRUE16-NEXT: s_endpgm ; ; GFX11-DENORM-FAKE16-LABEL: fmuladd_f16: @@ -432,14 +433,14 @@ define amdgpu_kernel void @fmuladd_f16_imm_a( ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s13, s3 ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s8, s0 -; GFX11-FLUSH-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-FLUSH-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FLUSH-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-FLUSH-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x4200, v0.l ; GFX11-FLUSH-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FLUSH-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l +; GFX11-FLUSH-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h ; GFX11-FLUSH-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-FLUSH-TRUE16-NEXT: s_endpgm ; @@ -483,13 +484,13 @@ define amdgpu_kernel void @fmuladd_f16_imm_a( ; GFX11-DENORM-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-DENORM-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-DENORM-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-DENORM-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-DENORM-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-DENORM-TRUE16-NEXT: v_fmamk_f16 v0.l, v0.l, 0x4200, v1.l +; GFX11-DENORM-TRUE16-NEXT: v_fmamk_f16 v0.l, v0.l, 0x4200, v0.h ; GFX11-DENORM-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-DENORM-TRUE16-NEXT: s_endpgm ; @@ -667,14 +668,14 @@ define amdgpu_kernel void @fmuladd_f16_imm_b( ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s13, s3 ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s8, s0 -; GFX11-FLUSH-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-FLUSH-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FLUSH-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-FLUSH-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-FLUSH-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FLUSH-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-FLUSH-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0x4200, v0.l ; GFX11-FLUSH-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FLUSH-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v1.l +; GFX11-FLUSH-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h ; GFX11-FLUSH-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-FLUSH-TRUE16-NEXT: s_endpgm ; @@ -718,13 +719,13 @@ define amdgpu_kernel void @fmuladd_f16_imm_b( ; GFX11-DENORM-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-DENORM-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-DENORM-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-DENORM-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-DENORM-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-DENORM-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-DENORM-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-DENORM-TRUE16-NEXT: v_fmamk_f16 v0.l, v0.l, 0x4200, v1.l +; GFX11-DENORM-TRUE16-NEXT: v_fmamk_f16 v0.l, v0.l, 0x4200, v0.h ; GFX11-DENORM-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-DENORM-TRUE16-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll index 38a0140e36c33..d80fb6d8ea108 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll @@ -3303,10 +3303,10 @@ declare <3 x i1> @llvm.is.fpclass.v3bf16(<3 x bfloat>, i32) declare <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat>, i32) ; Assume DAZ -attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" } +attributes #0 = { denormal_fpenv(ieee|preservesign) } ; Maybe daz -attributes #1 = { "denormal-fp-math"="ieee,dynamic" } +attributes #1 = { denormal_fpenv(ieee|dynamic) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX10SELDAG: {{.*}} ; GFX11SELDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll index cc5f6f842625c..bc01298205901 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll @@ -4428,10 +4428,10 @@ declare <3 x i1> @llvm.is.fpclass.v3f16(<3 x half>, i32) declare <4 x i1> @llvm.is.fpclass.v4f16(<4 x half>, i32) ; Assume DAZ -attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" } +attributes #0 = { denormal_fpenv(ieee|preservesign) } ; Maybe daz -attributes #1 = { "denormal-fp-math"="ieee,dynamic" } +attributes #1 = { denormal_fpenv(ieee|dynamic) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX11GLISEL: {{.*}} ; GFX11SELDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll index 7903ae93d770c..e2fd0a2d2d692 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll @@ -7958,8 +7958,8 @@ declare <3 x half> @llvm.log.v3f16(<3 x half>) #2 declare <4 x half> @llvm.log.v4f16(<4 x half>) #2 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2 -attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(float: ieee|preservesign) } +attributes #1 = { denormal_fpenv(float: dynamic|dynamic) } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX689-GISEL: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll index 478580ff8ec0a..b36ea6b1a134d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll @@ -7958,8 +7958,8 @@ declare <3 x half> @llvm.log10.v3f16(<3 x half>) #2 declare <4 x half> @llvm.log10.v4f16(<4 x half>) #2 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2 -attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(float: ieee|preservesign) } +attributes #1 = { denormal_fpenv(float: dynamic|dynamic) } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX689-GISEL: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll index 8401e05b39c19..7035d143ff679 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll @@ -5072,8 +5072,8 @@ declare <3 x half> @llvm.log2.v3f16(<3 x half>) #2 declare <4 x half> @llvm.log2.v4f16(<4 x half>) #2 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2 -attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(float: ieee|preservesign) } +attributes #1 = { denormal_fpenv(float: dynamic|dynamic) } attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX689-GISEL: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll index 69f17ed072425..2da2aa182971c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll @@ -128,14 +128,14 @@ define amdgpu_kernel void @maxnum_f16( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l -; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l +; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.h ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 @@ -267,7 +267,7 @@ define amdgpu_kernel void @maxnum_f16_imm_a( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l @@ -393,7 +393,7 @@ define amdgpu_kernel void @maxnum_f16_imm_b( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l @@ -1115,4 +1115,4 @@ entry: ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll index 0e91d905d5585..6b40024d3af01 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll @@ -128,14 +128,14 @@ define amdgpu_kernel void @minnum_f16_ieee( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l -; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v1.l, v1.l +; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.h, v0.h ; GFX11-TRUE16-NEXT: v_min_f16_e32 v0.l, v0.l, v0.h ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm @@ -302,7 +302,7 @@ define amdgpu_kernel void @minnum_f16_imm_a( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l @@ -426,7 +426,7 @@ define amdgpu_kernel void @minnum_f16_imm_b( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l @@ -1177,4 +1177,4 @@ entry: ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.modf.ll b/llvm/test/CodeGen/AMDGPU/llvm.modf.ll new file mode 100644 index 0000000000000..fc4f6507f273f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.modf.ll @@ -0,0 +1,569 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s + +declare { half, half } @llvm.modf.f16(half) +declare { <2 x half>, <2 x half> } @llvm.modf.v2f16(<2 x half>) + +declare { float, float } @llvm.modf.f32(float) +declare { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float>) + +declare { double, double } @llvm.modf.f64(double) +declare { <2 x double>, <2 x double> } @llvm.modf.v2f64(<2 x double>) + +define { half, half } @test_modf_f16(half %x) { +; GFX9-SDAG-LABEL: test_modf_f16: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7c00 +; GFX9-SDAG-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-SDAG-NEXT: v_sub_f16_e32 v2, v0, v1 +; GFX9-SDAG-NEXT: v_cmp_neq_f16_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_f16: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7c00 +; GFX9-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1 +; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[4:5], |v0|, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 +; GFX9-GISEL-NEXT: v_or_b32_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { half, half } @llvm.modf.f16(half %x) + ret { half, half } %result +} + +define half @test_modf_f16_only_use_fract(half %x) { +; GFX9-SDAG-LABEL: test_modf_f16_only_use_fract: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7c00 +; GFX9-SDAG-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-SDAG-NEXT: v_sub_f16_e32 v1, v0, v1 +; GFX9-SDAG-NEXT: v_cmp_neq_f16_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7fff +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v1, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_f16_only_use_fract: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7c00 +; GFX9-GISEL-NEXT: v_sub_f16_e32 v1, v0, v1 +; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[4:5], |v0|, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0 +; GFX9-GISEL-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { half, half } @llvm.modf.f16(half %x) + %result.0 = extractvalue { half, half } %result, 0 + ret half %result.0 +} + +define half @test_modf_f16_only_use_integer(half %x) { +; GFX9-LABEL: test_modf_f16_only_use_integer: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_trunc_f16_e32 v0, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call { half, half } @llvm.modf.f16(half %x) + %result.1 = extractvalue { half, half } %result, 1 + ret half %result.1 +} + +define { <2 x half>, <2 x half> } @test_modf_v2f16(<2 x half> %x) { +; GFX9-SDAG-LABEL: test_modf_v2f16: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7c00 +; GFX9-SDAG-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-SDAG-NEXT: v_sub_f16_e32 v2, v0, v1 +; GFX9-SDAG-NEXT: v_cmp_neq_f16_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-SDAG-NEXT: s_movk_i32 s5, 0x7fff +; GFX9-SDAG-NEXT: v_bfi_b32 v2, s5, v2, v0 +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_trunc_f16_e32 v3, v0 +; GFX9-SDAG-NEXT: v_sub_f16_e32 v4, v0, v3 +; GFX9-SDAG-NEXT: v_cmp_neq_f16_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s5, v4, v0 +; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX9-SDAG-NEXT: v_pack_b32_f16 v1, v1, v3 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_v2f16: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7c00 +; GFX9-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1 +; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[4:5], |v0|, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2 +; GFX9-GISEL-NEXT: v_and_b32_e32 v5, 0xffff8000, v0 +; GFX9-GISEL-NEXT: v_or_b32_e32 v2, v2, v5 +; GFX9-GISEL-NEXT: v_trunc_f16_sdwa v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-GISEL-NEXT: v_sub_f16_sdwa v6, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-GISEL-NEXT: v_cmp_eq_f16_sdwa s[4:5], |v0|, v3 src0_sel:WORD_1 src1_sel:DWORD +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xffff8000 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v6, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0x7fff, v3 +; GFX9-GISEL-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-GISEL-NEXT: v_or_b32_e32 v0, v3, v0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2 +; GFX9-GISEL-NEXT: v_pack_b32_f16 v1, v1, v5 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x half>, <2 x half> } @llvm.modf.v2f16(<2 x half> %x) + ret { <2 x half>, <2 x half> } %result +} + +define <2 x half> @test_modf_v2f16_only_use_fract(<2 x half> %x) { +; GFX9-SDAG-LABEL: test_modf_v2f16_only_use_fract: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x7c00 +; GFX9-SDAG-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-SDAG-NEXT: v_sub_f16_e32 v1, v0, v1 +; GFX9-SDAG-NEXT: v_cmp_neq_f16_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-SDAG-NEXT: s_movk_i32 s5, 0x7fff +; GFX9-SDAG-NEXT: v_bfi_b32 v1, s5, v1, v0 +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-SDAG-NEXT: v_trunc_f16_e32 v2, v0 +; GFX9-SDAG-NEXT: v_sub_f16_e32 v2, v0, v2 +; GFX9-SDAG-NEXT: v_cmp_neq_f16_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s5, v2, v0 +; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v1, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_v2f16_only_use_fract: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7c00 +; GFX9-GISEL-NEXT: v_sub_f16_e32 v1, v0, v1 +; GFX9-GISEL-NEXT: v_cmp_eq_f16_e64 s[4:5], |v0|, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v4, 0xffff8000, v0 +; GFX9-GISEL-NEXT: v_or_b32_e32 v1, v1, v4 +; GFX9-GISEL-NEXT: v_trunc_f16_sdwa v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-GISEL-NEXT: v_sub_f16_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-GISEL-NEXT: v_cmp_eq_f16_sdwa s[4:5], |v0|, v2 src0_sel:WORD_1 src1_sel:DWORD +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2 +; GFX9-GISEL-NEXT: v_and_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-GISEL-NEXT: v_or_b32_e32 v0, v2, v0 +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x half>, <2 x half> } @llvm.modf.v2f16(<2 x half> %x) + %result.0 = extractvalue { <2 x half>, <2 x half> } %result, 0 + ret <2 x half> %result.0 +} + +define <2 x half> @test_modf_v2f16_only_use_integer(<2 x half> %x) { +; GFX9-SDAG-LABEL: test_modf_v2f16_only_use_integer: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_trunc_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-SDAG-NEXT: v_trunc_f16_e32 v0, v0 +; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_v2f16_only_use_integer: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f16_e32 v1, v0 +; GFX9-GISEL-NEXT: v_trunc_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-GISEL-NEXT: v_pack_b32_f16 v0, v1, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x half>, <2 x half> } @llvm.modf.v2f16(<2 x half> %x) + %result.1 = extractvalue { <2 x half>, <2 x half> } %result, 1 + ret <2 x half> %result.1 +} + +define { float, float } @test_modf_f32(float %x) { +; GFX9-SDAG-LABEL: test_modf_f32: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x7f800000 +; GFX9-SDAG-NEXT: v_trunc_f32_e32 v1, v0 +; GFX9-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1 +; GFX9-SDAG-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-SDAG-NEXT: s_brev_b32 s4, -2 +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_f32: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 +; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 +; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v0|, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v3, -2 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v0 +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v2, v3, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { float, float } @llvm.modf.f32(float %x) + ret { float, float } %result +} + +define float @test_modf_f32_only_use_fract(float %x) { +; GFX9-SDAG-LABEL: test_modf_f32_only_use_fract: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x7f800000 +; GFX9-SDAG-NEXT: v_trunc_f32_e32 v1, v0 +; GFX9-SDAG-NEXT: v_sub_f32_e32 v1, v0, v1 +; GFX9-SDAG-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-SDAG-NEXT: s_brev_b32 s4, -2 +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v1, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_f32_only_use_fract: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000 +; GFX9-GISEL-NEXT: v_sub_f32_e32 v1, v0, v1 +; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v0|, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v0 +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v1, v2, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { float, float } @llvm.modf.f32(float %x) + %result.0 = extractvalue { float, float } %result, 0 + ret float %result.0 +} + +define float @test_modf_f32_only_use_integer(float %x) { +; GFX9-LABEL: test_modf_f32_only_use_integer: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_trunc_f32_e32 v0, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call { float, float } @llvm.modf.f32(float %x) + %result.1 = extractvalue { float, float } %result, 1 + ret float %result.1 +} + +define { <2 x float>, <2 x float> } @test_modf_v2f32(<2 x float> %x) { +; GFX9-SDAG-LABEL: test_modf_v2f32: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x7f800000 +; GFX9-SDAG-NEXT: v_trunc_f32_e32 v2, v0 +; GFX9-SDAG-NEXT: v_sub_f32_e32 v3, v0, v2 +; GFX9-SDAG-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; GFX9-SDAG-NEXT: s_brev_b32 s5, -2 +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s5, v3, v0 +; GFX9-SDAG-NEXT: v_trunc_f32_e32 v3, v1 +; GFX9-SDAG-NEXT: v_sub_f32_e32 v4, v1, v3 +; GFX9-SDAG-NEXT: v_cmp_neq_f32_e64 vcc, |v1|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc +; GFX9-SDAG-NEXT: v_bfi_b32 v1, s5, v4, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_v2f32: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f32_e32 v2, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000 +; GFX9-GISEL-NEXT: v_sub_f32_e32 v3, v0, v2 +; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v0|, v4 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5] +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v5, -2 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v0 +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v3, v5, v0 +; GFX9-GISEL-NEXT: v_trunc_f32_e32 v3, v1 +; GFX9-GISEL-NEXT: v_sub_f32_e32 v6, v1, v3 +; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v1|, v4 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v6, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1 +; GFX9-GISEL-NEXT: v_and_or_b32 v1, v4, v5, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> %x) + ret { <2 x float>, <2 x float> } %result +} + +define <2 x float> @test_modf_v2f32_only_use_fract(<2 x float> %x) { +; GFX9-SDAG-LABEL: test_modf_v2f32_only_use_fract: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_mov_b32 s4, 0x7f800000 +; GFX9-SDAG-NEXT: v_trunc_f32_e32 v2, v0 +; GFX9-SDAG-NEXT: v_sub_f32_e32 v2, v0, v2 +; GFX9-SDAG-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-SDAG-NEXT: s_brev_b32 s5, -2 +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s5, v2, v0 +; GFX9-SDAG-NEXT: v_trunc_f32_e32 v2, v1 +; GFX9-SDAG-NEXT: v_sub_f32_e32 v2, v1, v2 +; GFX9-SDAG-NEXT: v_cmp_neq_f32_e64 vcc, |v1|, s4 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; GFX9-SDAG-NEXT: v_bfi_b32 v1, s5, v2, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_v2f32_only_use_fract: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f32_e32 v2, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000 +; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v2 +; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v0|, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v4, -2 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v0 +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v2, v4, v0 +; GFX9-GISEL-NEXT: v_trunc_f32_e32 v2, v1 +; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v1, v2 +; GFX9-GISEL-NEXT: v_cmp_eq_f32_e64 s[4:5], |v1|, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1 +; GFX9-GISEL-NEXT: v_and_or_b32 v1, v2, v4, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> %x) + %result.0 = extractvalue { <2 x float>, <2 x float> } %result, 0 + ret <2 x float> %result.0 +} + +define <2 x float> @test_modf_v2f32_only_use_integer(<2 x float> %x) { +; GFX9-LABEL: test_modf_v2f32_only_use_integer: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_trunc_f32_e32 v0, v0 +; GFX9-NEXT: v_trunc_f32_e32 v1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> %x) + %result.1 = extractvalue { <2 x float>, <2 x float> } %result, 1 + ret <2 x float> %result.1 +} + +define { double, double } @test_modf_f64(double %x) { +; GFX9-SDAG-LABEL: test_modf_f64: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1] +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x204 +; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s4 +; GFX9-SDAG-NEXT: s_brev_b32 s6, -2 +; GFX9-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v5, 0, s[4:5] +; GFX9-SDAG-NEXT: v_bfi_b32 v1, s6, v4, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_f64: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7ff00000 +; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[4:5] +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v4, -2 +; GFX9-GISEL-NEXT: v_add_f64 v[6:7], v[0:1], -v[2:3] +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v6, 0, s[4:5] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, v7, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, 0, v5 +; GFX9-GISEL-NEXT: v_and_or_b32 v1, v6, v4, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { double, double } @llvm.modf.f64(double %x) + ret { double, double } %result +} + +define double @test_modf_f64_only_use_fract(double %x) { +; GFX9-SDAG-LABEL: test_modf_f64_only_use_fract: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[2:3], v[0:1] +; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x204 +; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s4 +; GFX9-SDAG-NEXT: s_brev_b32 s6, -2 +; GFX9-SDAG-NEXT: v_add_f64 v[2:3], v[0:1], -v[2:3] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[4:5] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v3, 0, s[4:5] +; GFX9-SDAG-NEXT: v_bfi_b32 v1, s6, v2, v1 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_f64_only_use_fract: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[2:3], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7ff00000 +; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[4:5] +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v4, -2 +; GFX9-GISEL-NEXT: v_add_f64 v[2:3], v[0:1], -v[2:3] +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5] +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, 0, v2 +; GFX9-GISEL-NEXT: v_and_or_b32 v1, v3, v4, v1 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { double, double } @llvm.modf.f64(double %x) + %result.0 = extractvalue { double, double } %result, 0 + ret double %result.0 +} + +define double @test_modf_f64_only_use_integer(double %x) { +; GFX9-LABEL: test_modf_f64_only_use_integer: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_trunc_f64_e32 v[0:1], v[0:1] +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call { double, double } @llvm.modf.f64(double %x) + %result.1 = extractvalue { double, double } %result, 1 + ret double %result.1 +} + +define { <2 x double>, <2 x double> } @test_modf_v2f64(<2 x double> %x) { +; GFX9-SDAG-LABEL: test_modf_v2f64: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[4:5], v[0:1] +; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[6:7], v[2:3] +; GFX9-SDAG-NEXT: s_movk_i32 s6, 0x204 +; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s6 +; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[6:7], v[2:3], s6 +; GFX9-SDAG-NEXT: s_brev_b32 s8, -2 +; GFX9-SDAG-NEXT: v_add_f64 v[8:9], v[0:1], -v[4:5] +; GFX9-SDAG-NEXT: v_add_f64 v[10:11], v[2:3], -v[6:7] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v8, 0, s[4:5] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v8, v9, 0, s[4:5] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v9, v11, 0, s[6:7] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v10, 0, s[6:7] +; GFX9-SDAG-NEXT: v_bfi_b32 v1, s8, v8, v1 +; GFX9-SDAG-NEXT: v_bfi_b32 v3, s8, v9, v3 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_v2f64: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[4:5], v[0:1] +; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[6:7], v[2:3] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v9, 0x7ff00000 +; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[8:9] +; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[6:7], |v[2:3]|, v[8:9] +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v8, -2 +; GFX9-GISEL-NEXT: v_add_f64 v[10:11], v[0:1], -v[4:5] +; GFX9-GISEL-NEXT: v_add_f64 v[12:13], v[2:3], -v[6:7] +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0x80000000, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v9, v10, 0, s[4:5] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v10, v11, 0, s[4:5] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v11, v12, 0, s[6:7] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v12, v13, 0, s[6:7] +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, 0, v9 +; GFX9-GISEL-NEXT: v_and_or_b32 v1, v10, v8, v1 +; GFX9-GISEL-NEXT: v_and_or_b32 v2, v2, 0, v11 +; GFX9-GISEL-NEXT: v_and_or_b32 v3, v12, v8, v3 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x double>, <2 x double> } @llvm.modf.v2f64(<2 x double> %x) + ret { <2 x double>, <2 x double> } %result +} + +define <2 x double> @test_modf_v2f64_only_use_fract(<2 x double> %x) { +; GFX9-SDAG-LABEL: test_modf_v2f64_only_use_fract: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[4:5], v[0:1] +; GFX9-SDAG-NEXT: v_trunc_f64_e32 v[6:7], v[2:3] +; GFX9-SDAG-NEXT: s_movk_i32 s6, 0x204 +; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[4:5], v[0:1], s6 +; GFX9-SDAG-NEXT: v_cmp_class_f64_e64 s[6:7], v[2:3], s6 +; GFX9-SDAG-NEXT: s_brev_b32 s8, -2 +; GFX9-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[4:5] +; GFX9-SDAG-NEXT: v_add_f64 v[6:7], v[2:3], -v[6:7] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v5, 0, s[4:5] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[6:7] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[6:7] +; GFX9-SDAG-NEXT: v_bfi_b32 v1, s8, v4, v1 +; GFX9-SDAG-NEXT: v_bfi_b32 v3, s8, v5, v3 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_v2f64_only_use_fract: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[4:5], v[0:1] +; GFX9-GISEL-NEXT: v_trunc_f64_e32 v[6:7], v[2:3] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v9, 0x7ff00000 +; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[4:5], |v[0:1]|, v[8:9] +; GFX9-GISEL-NEXT: v_cmp_eq_f64_e64 s[6:7], |v[2:3]|, v[8:9] +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v8, -2 +; GFX9-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[4:5] +; GFX9-GISEL-NEXT: v_add_f64 v[6:7], v[2:3], -v[6:7] +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0x80000000, v1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v3, 0x80000000, v3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v5, 0, s[4:5] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[6:7] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[6:7] +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v0, 0, v4 +; GFX9-GISEL-NEXT: v_and_or_b32 v1, v5, v8, v1 +; GFX9-GISEL-NEXT: v_and_or_b32 v2, v2, 0, v6 +; GFX9-GISEL-NEXT: v_and_or_b32 v3, v7, v8, v3 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x double>, <2 x double> } @llvm.modf.v2f64(<2 x double> %x) + %result.0 = extractvalue { <2 x double>, <2 x double> } %result, 0 + ret <2 x double> %result.0 +} + +define <2 x double> @test_modf_v2f64_only_use_integer(<2 x double> %x) { +; GFX9-LABEL: test_modf_v2f64_only_use_integer: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_trunc_f64_e32 v[0:1], v[0:1] +; GFX9-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call { <2 x double>, <2 x double> } @llvm.modf.v2f64(<2 x double> %x) + %result.1 = extractvalue { <2 x double>, <2 x double> } %result, 1 + ret <2 x double> %result.1 +} + +define { float, float } @test_modf_ninf(float %x) { +; GFX9-SDAG-LABEL: test_modf_ninf: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_trunc_f32_e32 v1, v0 +; GFX9-SDAG-NEXT: v_sub_f32_e32 v2, v0, v1 +; GFX9-SDAG-NEXT: s_brev_b32 s4, -2 +; GFX9-SDAG-NEXT: v_bfi_b32 v0, s4, v2, v0 +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: test_modf_ninf: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: v_trunc_f32_e32 v1, v0 +; GFX9-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1 +; GFX9-GISEL-NEXT: v_bfrev_b32_e32 v3, -2 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0x80000000, v0 +; GFX9-GISEL-NEXT: v_and_or_b32 v0, v2, v3, v0 +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] + %result = call ninf { float, float } @llvm.modf.f32(float %x) + ret { float, float } %result +} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll index 57ce028b1fc4a..80a7d0127fec5 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll @@ -60,7 +60,7 @@ define amdgpu_kernel void @rint_f16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_rndne_f16_e32 v0.l, v0.l @@ -96,7 +96,7 @@ define amdgpu_kernel void @rint_f16( ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: v_rndne_f16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll new file mode 100644 index 0000000000000..3ebfdcff4309f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.sponentry.ll @@ -0,0 +1,398 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=CHECK,DAGISEL +; RUN: llc -global-isel=0 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=CHECK,DAGISEL +; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=CHECK,GISEL +; RUN: llc -global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=CHECK,GISEL + +; Test that in dynamic VGPR mode, the return of sponentry points after the area reserved for CWSR. + +define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_16(i32 %val) #0 { +; CHECK-LABEL: sponentry_cs_dvgpr_16: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; CHECK-NEXT: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; CHECK-NEXT: s_cmp_lg_u32 0, s33 +; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0 +; CHECK-NEXT: s_cmp_lg_u32 0, s0 +; CHECK-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS +; CHECK-NEXT: s_wait_storecnt 0x0 +; CHECK-NEXT: s_cmovk_i32 s0, 0x1c0 +; CHECK-NEXT: ; return to shader part epilog + %local = alloca i32, addrspace(5) + store volatile i32 %val, ptr addrspace(5) %local + %stack.base = call ptr addrspace(5) @llvm.sponentry() + ret ptr addrspace(5) %stack.base +} + +; CHECK: ScratchSize: 8 + +define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_32(i32 %val) #1 { +; CHECK-LABEL: sponentry_cs_dvgpr_32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; CHECK-NEXT: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; CHECK-NEXT: s_cmp_lg_u32 0, s33 +; CHECK-NEXT: s_cmovk_i32 s33, 0x380 +; CHECK-NEXT: s_cmp_lg_u32 0, s0 +; CHECK-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS +; CHECK-NEXT: s_wait_storecnt 0x0 +; CHECK-NEXT: s_cmovk_i32 s0, 0x380 +; CHECK-NEXT: ; return to shader part epilog + %local = alloca i32, addrspace(5) + store volatile i32 %val, ptr addrspace(5) %local + %stack.base = call ptr addrspace(5) @llvm.sponentry() + ret ptr addrspace(5) %stack.base +} + +; CHECK: ScratchSize: 8 + +; If we're not in dynamic VGPR mode, then sponentry can just return 0. + +define amdgpu_cs ptr addrspace(5) @sponentry_cs_no_dvgpr(i32 %val) #2 { +; CHECK-LABEL: sponentry_cs_no_dvgpr: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_mov_b32 s0, 0 +; CHECK-NEXT: scratch_store_b32 off, v0, off scope:SCOPE_SYS +; CHECK-NEXT: s_wait_storecnt 0x0 +; CHECK-NEXT: ; return to shader part epilog + %local = alloca i32, addrspace(5) + store volatile i32 %val, ptr addrspace(5) %local + %stack.base = call ptr addrspace(5) @llvm.sponentry() + ret ptr addrspace(5) %stack.base +} + +; CHECK: ScratchSize: 8 + +define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_control_flow(i32 %val, ptr addrspace(5) %ptr) #0 { +; CHECK-LABEL: sponentry_cs_dvgpr_control_flow: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; CHECK-NEXT: s_mov_b32 s0, exec_lo +; CHECK-NEXT: s_cmp_lg_u32 0, s33 +; CHECK-NEXT: s_cmovk_i32 s33, 0x1c0 +; CHECK-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS +; CHECK-NEXT: s_wait_storecnt 0x0 +; CHECK-NEXT: v_cmpx_gt_i32_e32 0x43, v0 +; CHECK-NEXT: ; %bb.1: ; %if.then +; CHECK-NEXT: s_getreg_b32 s1, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; CHECK-NEXT: s_cmp_lg_u32 0, s1 +; CHECK-NEXT: s_cmovk_i32 s1, 0x1c0 +; CHECK-NEXT: v_mov_b32_e32 v1, s1 +; CHECK-NEXT: ; %bb.2: ; %if.end +; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) +; CHECK-NEXT: v_readfirstlane_b32 s0, v1 +; CHECK-NEXT: s_wait_alu depctr_va_sdst(0) +; CHECK-NEXT: ; return to shader part epilog +entry: + %local = alloca i32, addrspace(5) + store volatile i32 %val, ptr addrspace(5) %local + %which = icmp slt i32 %val, 67 + br i1 %which, label %if.then, label %if.end + +if.then: + %stack.base = call ptr addrspace(5) @llvm.sponentry() + br label %if.end + +if.end: + %ret = phi ptr addrspace(5) [ %stack.base, %if.then ], [ %ptr, %entry ] + ret ptr addrspace(5) %ret +} + +; CHECK: ScratchSize: 8 + +declare amdgpu_gfx i32 @callee() + +define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_calls(i32 %val) #0 { +; DAGISEL-LABEL: sponentry_cs_dvgpr_calls: +; DAGISEL: ; %bb.0: +; DAGISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; DAGISEL-NEXT: s_mov_b32 s1, callee@abs32@hi +; DAGISEL-NEXT: s_cmp_lg_u32 0, s33 +; DAGISEL-NEXT: s_mov_b32 s0, callee@abs32@lo +; DAGISEL-NEXT: s_cmovk_i32 s33, 0x1c0 +; DAGISEL-NEXT: s_cselect_b32 s32, 0x1d0, 16 +; DAGISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] +; DAGISEL-NEXT: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; DAGISEL-NEXT: s_wait_storecnt 0x0 +; DAGISEL-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS +; DAGISEL-NEXT: s_wait_storecnt 0x0 +; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; DAGISEL-NEXT: s_cmp_lg_u32 0, s0 +; DAGISEL-NEXT: s_cmovk_i32 s0, 0x1c0 +; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; DAGISEL-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: sponentry_cs_dvgpr_calls: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; GISEL-NEXT: s_mov_b32 s0, callee@abs32@lo +; GISEL-NEXT: s_cmp_lg_u32 0, s33 +; GISEL-NEXT: s_mov_b32 s1, callee@abs32@hi +; GISEL-NEXT: s_cmovk_i32 s33, 0x1c0 +; GISEL-NEXT: s_cselect_b32 s32, 0x1d0, 16 +; GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] +; GISEL-NEXT: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; GISEL-NEXT: s_wait_storecnt 0x0 +; GISEL-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS +; GISEL-NEXT: s_wait_storecnt 0x0 +; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; GISEL-NEXT: s_cmp_lg_u32 0, s0 +; GISEL-NEXT: s_cmovk_i32 s0, 0x1c0 +; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; GISEL-NEXT: ; return to shader part epilog + %local = alloca i32, addrspace(5) + %res = call amdgpu_gfx i32 @callee() + store volatile i32 %res, ptr addrspace(5) %local + %stack.base = call ptr addrspace(5) @llvm.sponentry() + ret ptr addrspace(5) %stack.base +} + +; CHECK: ScratchSize: 16 + +define amdgpu_cs ptr addrspace(5) @sponentry_cs_dvgpr_realign(i32 %val) #0 { +; CHECK-LABEL: sponentry_cs_dvgpr_realign: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_getreg_b32 s33, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; CHECK-NEXT: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2, 8, 2) +; CHECK-NEXT: s_cmp_lg_u32 0, s33 +; CHECK-NEXT: s_cmovk_i32 s33, 0x200 +; CHECK-NEXT: s_cmp_lg_u32 0, s0 +; CHECK-NEXT: scratch_store_b32 off, v0, s33 scope:SCOPE_SYS +; CHECK-NEXT: s_wait_storecnt 0x0 +; CHECK-NEXT: s_cmovk_i32 s0, 0x200 +; CHECK-NEXT: ; return to shader part epilog + %boop = alloca i32, addrspace(5) + %local = alloca i32, align 128, addrspace(5) + store volatile i32 %val, ptr addrspace(5) %local + %stack.base = call ptr addrspace(5) @llvm.sponentry() + ret ptr addrspace(5) %stack.base +} + +; CHECK: ScratchSize: 128 + +define amdgpu_gfx ptr addrspace(5) @sponentry_gfx(i32 %val, ptr addrspace(5) %ptr) #0 { +; DAGISEL-LABEL: sponentry_gfx: +; DAGISEL: ; %bb.0: ; %entry +; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; DAGISEL-NEXT: s_wait_expcnt 0x0 +; DAGISEL-NEXT: s_wait_samplecnt 0x0 +; DAGISEL-NEXT: s_wait_bvhcnt 0x0 +; DAGISEL-NEXT: s_wait_kmcnt 0x0 +; DAGISEL-NEXT: s_mov_b32 s0, exec_lo +; DAGISEL-NEXT: s_wait_storecnt 0x0 +; DAGISEL-NEXT: scratch_store_b32 off, v0, s32 offset:4 scope:SCOPE_SYS +; DAGISEL-NEXT: s_wait_storecnt 0x0 +; DAGISEL-NEXT: v_cmpx_gt_i32_e32 0x43, v0 +; DAGISEL-NEXT: ; %bb.1: ; %if.then +; DAGISEL-NEXT: v_mov_b32_e32 v1, s32 +; DAGISEL-NEXT: ; %bb.2: ; %if.end +; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; DAGISEL-NEXT: v_mov_b32_e32 v0, v1 +; DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-LABEL: sponentry_gfx: +; GISEL: ; %bb.0: ; %entry +; GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-NEXT: s_wait_expcnt 0x0 +; GISEL-NEXT: s_wait_samplecnt 0x0 +; GISEL-NEXT: s_wait_bvhcnt 0x0 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v2, v0 +; GISEL-NEXT: v_mov_b32_e32 v0, v1 +; GISEL-NEXT: s_mov_b32 s0, exec_lo +; GISEL-NEXT: s_wait_storecnt 0x0 +; GISEL-NEXT: scratch_store_b32 off, v2, s32 offset:4 scope:SCOPE_SYS +; GISEL-NEXT: s_wait_storecnt 0x0 +; GISEL-NEXT: v_cmpx_gt_i32_e32 0x43, v2 +; GISEL-NEXT: ; %bb.1: ; %if.then +; GISEL-NEXT: s_mov_b32 s1, s32 +; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; GISEL-NEXT: v_mov_b32_e32 v0, s1 +; GISEL-NEXT: ; %bb.2: ; %if.end +; GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + %local = alloca i32, addrspace(5) + store volatile i32 %val, ptr addrspace(5) %local + %which = icmp slt i32 %val, 67 + br i1 %which, label %if.then, label %if.end + +if.then: + %stack.base = call ptr addrspace(5) @llvm.sponentry() + br label %if.end + +if.end: + %ret = phi ptr addrspace(5) [ %stack.base, %if.then ], [ %ptr, %entry ] + ret ptr addrspace(5) %ret +} + +; FIXME: Optimize away the 4 bytes for the sponentry frame index. +; CHECK: ScratchSize: 12 + +define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_dvgpr_realign(i32 %val) #0 { +; CHECK-LABEL: sponentry_gfx_dvgpr_realign: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0 +; CHECK-NEXT: s_wait_expcnt 0x0 +; CHECK-NEXT: s_wait_samplecnt 0x0 +; CHECK-NEXT: s_wait_bvhcnt 0x0 +; CHECK-NEXT: s_wait_kmcnt 0x0 +; CHECK-NEXT: s_mov_b32 s0, s33 +; CHECK-NEXT: s_add_co_i32 s33, s32, 0x7f +; CHECK-NEXT: s_mov_b32 s1, s34 +; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0) +; CHECK-NEXT: s_and_b32 s33, s33, 0xffffff80 +; CHECK-NEXT: s_mov_b32 s34, s32 +; CHECK-NEXT: s_wait_storecnt 0x0 +; CHECK-NEXT: scratch_store_b32 off, v0, s33 offset:128 scope:SCOPE_SYS +; CHECK-NEXT: s_wait_storecnt 0x0 +; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0) +; CHECK-NEXT: v_mov_b32_e32 v0, s34 +; CHECK-NEXT: s_addk_co_i32 s32, 0x180 +; CHECK-NEXT: s_mov_b32 s32, s34 +; CHECK-NEXT: s_mov_b32 s34, s1 +; CHECK-NEXT: s_mov_b32 s33, s0 +; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] + %boop = alloca i32, addrspace(5) + %local = alloca i32, align 128, addrspace(5) + store volatile i32 %val, ptr addrspace(5) %local + %stack.base = call ptr addrspace(5) @llvm.sponentry() + ret ptr addrspace(5) %stack.base +} + +; FIXME: Optimize away the sponentry fixed object. +; CHECK: ScratchSize: 384 + +define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_stack_args(<32 x i32> %fill.sgprs, i32 %val, ptr addrspace(5) %ptr) #0 { +; DAGISEL-LABEL: sponentry_gfx_stack_args: +; DAGISEL: ; %bb.0: +; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; DAGISEL-NEXT: s_wait_expcnt 0x0 +; DAGISEL-NEXT: s_wait_samplecnt 0x0 +; DAGISEL-NEXT: s_wait_bvhcnt 0x0 +; DAGISEL-NEXT: s_wait_kmcnt 0x0 +; DAGISEL-NEXT: s_clause 0x1 +; DAGISEL-NEXT: scratch_load_b32 v0, off, s32 offset:4 +; DAGISEL-NEXT: scratch_load_b32 v1, off, s32 +; DAGISEL-NEXT: s_wait_loadcnt 0x0 +; DAGISEL-NEXT: s_wait_storecnt 0x0 +; DAGISEL-NEXT: scratch_store_b32 v0, v1, off scope:SCOPE_SYS +; DAGISEL-NEXT: s_wait_storecnt 0x0 +; DAGISEL-NEXT: v_mov_b32_e32 v0, s32 +; DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-LABEL: sponentry_gfx_stack_args: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-NEXT: s_wait_expcnt 0x0 +; GISEL-NEXT: s_wait_samplecnt 0x0 +; GISEL-NEXT: s_wait_bvhcnt 0x0 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: s_clause 0x1 +; GISEL-NEXT: scratch_load_b32 v0, off, s32 +; GISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 +; GISEL-NEXT: s_wait_loadcnt 0x0 +; GISEL-NEXT: s_wait_storecnt 0x0 +; GISEL-NEXT: scratch_store_b32 v1, v0, off scope:SCOPE_SYS +; GISEL-NEXT: s_wait_storecnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v0, s32 +; GISEL-NEXT: s_setpc_b64 s[30:31] + store volatile i32 %val, ptr addrspace(5) %ptr + %stack.base = call ptr addrspace(5) @llvm.sponentry() + ret ptr addrspace(5) %stack.base +} + +; CHECK: ScratchSize: 12 + +define amdgpu_gfx ptr addrspace(5) @sponentry_gfx_dyn_alloc(i32 %val) #0 { +; DAGISEL-LABEL: sponentry_gfx_dyn_alloc: +; DAGISEL: ; %bb.0: +; DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; DAGISEL-NEXT: s_wait_expcnt 0x0 +; DAGISEL-NEXT: s_wait_samplecnt 0x0 +; DAGISEL-NEXT: s_wait_bvhcnt 0x0 +; DAGISEL-NEXT: s_wait_kmcnt 0x0 +; DAGISEL-NEXT: v_lshl_add_u32 v1, v0, 2, 15 +; DAGISEL-NEXT: s_mov_b32 s34, s33 +; DAGISEL-NEXT: s_mov_b32 s1, exec_lo +; DAGISEL-NEXT: s_mov_b32 s0, 0 +; DAGISEL-NEXT: s_mov_b32 s33, s32 +; DAGISEL-NEXT: v_and_b32_e32 v1, -16, v1 +; DAGISEL-NEXT: s_add_co_i32 s32, s32, 16 +; DAGISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 +; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; DAGISEL-NEXT: s_ctz_i32_b32 s2, s1 +; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; DAGISEL-NEXT: v_readlane_b32 s3, v1, s2 +; DAGISEL-NEXT: s_bitset0_b32 s1, s2 +; DAGISEL-NEXT: s_max_u32 s0, s0, s3 +; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; DAGISEL-NEXT: s_cmp_lg_u32 s1, 0 +; DAGISEL-NEXT: s_cbranch_scc1 .LBB9_1 +; DAGISEL-NEXT: ; %bb.2: +; DAGISEL-NEXT: s_mov_b32 s1, s32 +; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; DAGISEL-NEXT: v_lshl_add_u32 v1, s0, 5, s1 +; DAGISEL-NEXT: s_wait_storecnt 0x0 +; DAGISEL-NEXT: scratch_store_b32 off, v0, s1 scope:SCOPE_SYS +; DAGISEL-NEXT: s_wait_storecnt 0x0 +; DAGISEL-NEXT: v_mov_b32_e32 v0, s33 +; DAGISEL-NEXT: v_readfirstlane_b32 s32, v1 +; DAGISEL-NEXT: s_mov_b32 s32, s33 +; DAGISEL-NEXT: s_mov_b32 s33, s34 +; DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-LABEL: sponentry_gfx_dyn_alloc: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-NEXT: s_wait_expcnt 0x0 +; GISEL-NEXT: s_wait_samplecnt 0x0 +; GISEL-NEXT: s_wait_bvhcnt 0x0 +; GISEL-NEXT: s_wait_kmcnt 0x0 +; GISEL-NEXT: v_lshl_add_u32 v1, v0, 2, 15 +; GISEL-NEXT: s_mov_b32 s34, s33 +; GISEL-NEXT: s_mov_b32 s1, exec_lo +; GISEL-NEXT: s_mov_b32 s0, 0 +; GISEL-NEXT: s_mov_b32 s33, s32 +; GISEL-NEXT: v_and_b32_e32 v1, -16, v1 +; GISEL-NEXT: s_add_co_i32 s32, s32, 16 +; GISEL-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1 +; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; GISEL-NEXT: s_ctz_i32_b32 s2, s1 +; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; GISEL-NEXT: v_readlane_b32 s3, v1, s2 +; GISEL-NEXT: s_bitset0_b32 s1, s2 +; GISEL-NEXT: s_max_u32 s0, s0, s3 +; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; GISEL-NEXT: s_cmp_lg_u32 s1, 0 +; GISEL-NEXT: s_cbranch_scc1 .LBB9_1 +; GISEL-NEXT: ; %bb.2: +; GISEL-NEXT: s_mov_b32 s1, s32 +; GISEL-NEXT: s_lshl_b32 s0, s0, 5 +; GISEL-NEXT: s_wait_storecnt 0x0 +; GISEL-NEXT: scratch_store_b32 off, v0, s1 scope:SCOPE_SYS +; GISEL-NEXT: s_wait_storecnt 0x0 +; GISEL-NEXT: v_mov_b32_e32 v0, s33 +; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; GISEL-NEXT: s_add_co_u32 s32, s1, s0 +; GISEL-NEXT: s_mov_b32 s32, s33 +; GISEL-NEXT: s_mov_b32 s33, s34 +; GISEL-NEXT: s_wait_alu depctr_sa_sdst(0) +; GISEL-NEXT: s_setpc_b64 s[30:31] + %local = alloca i32, i32 %val, addrspace(5) + store volatile i32 %val, ptr addrspace(5) %local + %stack.base = call ptr addrspace(5) @llvm.sponentry() + ret ptr addrspace(5) %stack.base +} + +; CHECK: ScratchSize: 16 + +attributes #0 = { nounwind "amdgpu-dynamic-vgpr-block-size"="16" } +attributes #1 = { nounwind "amdgpu-dynamic-vgpr-block-size"="32" } +attributes #2 = { nounwind "amdgpu-dynamic-vgpr-block-size"="0" } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll index bbbf4b66cf55b..0965dd126a8e8 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll @@ -18,7 +18,7 @@ define amdgpu_kernel void @sqrt_bf16(ptr addrspace(1) %r, ptr addrspace(1) %a) { ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: v_sqrt_bf16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll index 6fbfcf3451430..961a881cae20e 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll @@ -59,7 +59,7 @@ define amdgpu_kernel void @sqrt_f16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l @@ -95,7 +95,7 @@ define amdgpu_kernel void @sqrt_f16( ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: v_sqrt_f16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll index 047c170ab527f..e4d82271884c1 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll @@ -59,7 +59,7 @@ define amdgpu_kernel void @trunc_f16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l @@ -95,7 +95,7 @@ define amdgpu_kernel void @trunc_f16( ; GFX12-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX12-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX12-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX12-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], null +; GFX12-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], null ; GFX12-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll index 3d02d70d2fdbb..6894d55c34fcb 100644 --- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll +++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll @@ -28,31 +28,179 @@ define amdgpu_kernel void @local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; MUBUF-NEXT: s_mov_b32 s4, 0 ; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: .LBB0_1: ; %loadstoreloop +; MUBUF-NEXT: .LBB0_1: ; %static-memset-expansion-main-body ; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1 ; MUBUF-NEXT: v_mov_b32_e32 v3, 0x3000 ; MUBUF-NEXT: v_add_u32_e32 v2, s4, v3 -; MUBUF-NEXT: s_add_i32 s4, s4, 1 -; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120 -; MUBUF-NEXT: buffer_store_byte v1, v2, s[0:3], 0 offen +; MUBUF-NEXT: s_addk_i32 s4, 0x100 +; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2100 +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:252 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:248 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:244 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:240 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:236 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:232 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:228 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:224 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:220 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:216 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:212 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:208 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:204 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:200 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:196 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:192 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:188 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:184 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:180 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:176 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:172 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:168 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:164 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:160 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:156 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:152 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:148 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:144 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:140 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:136 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:132 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:128 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:124 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:120 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:116 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:112 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:108 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:104 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:100 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:96 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:92 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:88 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:84 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:80 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:76 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:72 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:68 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:64 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:60 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:56 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:52 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:48 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:44 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:40 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:36 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:32 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:28 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:24 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:20 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:16 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:8 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_cbranch_scc1 .LBB0_1 -; MUBUF-NEXT: ; %bb.2: ; %split -; MUBUF-NEXT: v_mov_b32_e32 v1, 0x50d0 -; MUBUF-NEXT: buffer_load_dword v2, v1, s[0:3], 0 offen glc +; MUBUF-NEXT: ; %bb.2: ; %static-memset-post-expansion +; MUBUF-NEXT: v_mov_b32_e32 v1, 0x5100 +; MUBUF-NEXT: v_mov_b32_e32 v2, 0 +; MUBUF-NEXT: s_movk_i32 s4, 0x2110 +; MUBUF-NEXT: v_mov_b32_e32 v3, 0x3000 +; MUBUF-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen offset:8 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen offset:4 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: v_add_u32_e32 v1, s4, v3 +; MUBUF-NEXT: s_movk_i32 s4, 0x20d0 +; MUBUF-NEXT: v_mov_b32_e32 v3, 0x3000 +; MUBUF-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen offset:8 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen offset:4 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: v_add_u32_e32 v1, s4, v3 +; MUBUF-NEXT: buffer_load_dword v3, v1, s[0:3], 0 offen glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: buffer_load_dword v3, v1, s[0:3], 0 offen offset:4 glc +; MUBUF-NEXT: buffer_load_dword v4, v1, s[0:3], 0 offen offset:4 glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen glc +; MUBUF-NEXT: buffer_load_dword v5, v0, s[0:3], 0 offen glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: buffer_load_dword v5, v0, s[0:3], 0 offen offset:4 glc +; MUBUF-NEXT: buffer_load_dword v6, v0, s[0:3], 0 offen offset:4 glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 -; MUBUF-NEXT: v_mov_b32_e32 v6, 0 -; MUBUF-NEXT: v_add_co_u32_e32 v0, vcc, v2, v4 -; MUBUF-NEXT: v_addc_co_u32_e32 v1, vcc, v3, v5, vcc +; MUBUF-NEXT: v_add_co_u32_e32 v0, vcc, v3, v5 +; MUBUF-NEXT: v_addc_co_u32_e32 v1, vcc, v4, v6, vcc ; MUBUF-NEXT: s_waitcnt lgkmcnt(0) -; MUBUF-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5] +; MUBUF-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_endpgm ; @@ -65,20 +213,69 @@ define amdgpu_kernel void @local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s0, 0 -; FLATSCR-NEXT: .LBB0_1: ; %loadstoreloop +; FLATSCR-NEXT: s_mov_b32 s1, s0 +; FLATSCR-NEXT: s_mov_b32 s2, s0 +; FLATSCR-NEXT: s_mov_b32 s3, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v0, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v1, s1 +; FLATSCR-NEXT: v_mov_b32_e32 v2, s2 +; FLATSCR-NEXT: v_mov_b32_e32 v3, s3 +; FLATSCR-NEXT: .LBB0_1: ; %static-memset-expansion-main-body ; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLATSCR-NEXT: s_add_i32 s1, s0, 0x3000 -; FLATSCR-NEXT: s_add_i32 s0, s0, 1 -; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120 -; FLATSCR-NEXT: scratch_store_byte off, v0, s1 +; FLATSCR-NEXT: s_addk_i32 s0, 0x100 +; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2100 +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:240 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:224 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:208 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:192 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:176 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:160 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:144 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:128 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:112 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:96 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:80 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:64 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:48 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:32 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:16 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_cbranch_scc1 .LBB0_1 -; FLATSCR-NEXT: ; %bb.2: ; %split +; FLATSCR-NEXT: ; %bb.2: ; %static-memset-post-expansion ; FLATSCR-NEXT: s_movk_i32 s0, 0x2000 -; FLATSCR-NEXT: s_addk_i32 s0, 0x3000 -; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s0 offset:208 glc +; FLATSCR-NEXT: s_add_i32 s6, s0, 0x3000 +; FLATSCR-NEXT: s_mov_b32 s0, 0 +; FLATSCR-NEXT: s_mov_b32 s1, s0 +; FLATSCR-NEXT: s_mov_b32 s2, s0 +; FLATSCR-NEXT: s_mov_b32 s3, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v0, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v1, s1 +; FLATSCR-NEXT: v_mov_b32_e32 v2, s2 +; FLATSCR-NEXT: v_mov_b32_e32 v3, s3 +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s6 offset:256 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s6 offset:272 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_movk_i32 s0, 0x3000 +; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s6 offset:208 glc +; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s0 offset:64 glc ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 @@ -121,20 +318,173 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; MUBUF-NEXT: s_add_i32 s32, s32, 0x200000 ; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], s33 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: .LBB1_1: ; %loadstoreloop +; MUBUF-NEXT: .LBB1_1: ; %static-memset-expansion-main-body ; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1 ; MUBUF-NEXT: v_lshrrev_b32_e64 v5, 6, s33 ; MUBUF-NEXT: v_add_u32_e32 v4, s4, v5 ; MUBUF-NEXT: v_mov_b32_e32 v5, 0x3000 -; MUBUF-NEXT: s_add_i32 s4, s4, 1 +; MUBUF-NEXT: s_addk_i32 s4, 0x100 ; MUBUF-NEXT: v_add_u32_e32 v4, v5, v4 -; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120 -; MUBUF-NEXT: buffer_store_byte v3, v4, s[0:3], 0 offen +; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2100 +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:252 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:248 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:244 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:240 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:236 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:232 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:228 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:224 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:220 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:216 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:212 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:208 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:204 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:200 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:196 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:192 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:188 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:184 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:180 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:176 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:172 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:168 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:164 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:160 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:156 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:152 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:148 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:144 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:140 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:136 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:132 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:128 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:124 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:120 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:116 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:112 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:108 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:104 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:100 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:96 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:92 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:88 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:84 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:80 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:76 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:72 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:68 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:64 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:60 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:56 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:52 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:48 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:44 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:40 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:36 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:32 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:28 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:24 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:20 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:16 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:8 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen offset:4 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_cbranch_scc1 .LBB1_1 -; MUBUF-NEXT: ; %bb.2: ; %split +; MUBUF-NEXT: ; %bb.2: ; %static-memset-post-expansion ; MUBUF-NEXT: v_lshrrev_b32_e64 v4, 6, s33 -; MUBUF-NEXT: v_add_u32_e32 v3, 0x50d0, v4 +; MUBUF-NEXT: v_add_u32_e32 v3, 0x5100, v4 +; MUBUF-NEXT: v_mov_b32_e32 v4, 0 +; MUBUF-NEXT: s_movk_i32 s4, 0x2110 +; MUBUF-NEXT: v_lshrrev_b32_e64 v5, 6, s33 +; MUBUF-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen offset:8 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen offset:4 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: v_add_u32_e32 v3, s4, v5 +; MUBUF-NEXT: v_mov_b32_e32 v5, 0x3000 +; MUBUF-NEXT: v_add_u32_e32 v3, v5, v3 +; MUBUF-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen offset:8 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen offset:4 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: s_movk_i32 s4, 0x20d0 +; MUBUF-NEXT: v_lshrrev_b32_e64 v4, 6, s33 +; MUBUF-NEXT: v_add_u32_e32 v3, s4, v4 +; MUBUF-NEXT: v_mov_b32_e32 v4, 0x3000 +; MUBUF-NEXT: v_add_u32_e32 v3, v4, v3 ; MUBUF-NEXT: buffer_load_dword v4, v3, s[0:3], 0 offen glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: buffer_load_dword v5, v3, s[0:3], 0 offen offset:4 glc @@ -155,10 +505,10 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-LABEL: func_local_stack_offset_uses_sp: ; FLATSCR: ; %bb.0: ; %entry ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; FLATSCR-NEXT: s_mov_b32 s2, s33 +; FLATSCR-NEXT: s_mov_b32 s5, s33 ; FLATSCR-NEXT: s_add_i32 s33, s32, 0x1fff ; FLATSCR-NEXT: s_and_b32 s33, s33, 0xffffe000 -; FLATSCR-NEXT: s_mov_b32 s3, s34 +; FLATSCR-NEXT: s_mov_b32 s6, s34 ; FLATSCR-NEXT: s_mov_b32 s34, s32 ; FLATSCR-NEXT: s_add_i32 s32, s32, 0x8000 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 @@ -166,27 +516,76 @@ define void @func_local_stack_offset_uses_sp(ptr addrspace(1) %out) { ; FLATSCR-NEXT: scratch_store_dword off, v2, s0 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s0, 0 -; FLATSCR-NEXT: .LBB1_1: ; %loadstoreloop +; FLATSCR-NEXT: s_mov_b32 s3, s0 +; FLATSCR-NEXT: s_mov_b32 s1, s0 +; FLATSCR-NEXT: s_mov_b32 s2, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v5, s3 +; FLATSCR-NEXT: v_mov_b32_e32 v4, s2 +; FLATSCR-NEXT: v_mov_b32_e32 v3, s1 +; FLATSCR-NEXT: v_mov_b32_e32 v2, s0 +; FLATSCR-NEXT: .LBB1_1: ; %static-memset-expansion-main-body ; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLATSCR-NEXT: s_add_i32 s1, s33, s0 ; FLATSCR-NEXT: s_addk_i32 s1, 0x3000 -; FLATSCR-NEXT: s_add_i32 s0, s0, 1 -; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120 -; FLATSCR-NEXT: scratch_store_byte off, v2, s1 +; FLATSCR-NEXT: s_addk_i32 s0, 0x100 +; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2100 +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:240 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:224 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:208 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:192 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:176 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:160 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:144 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:128 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:112 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:96 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:80 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:64 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:48 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:32 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 offset:16 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s1 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_cbranch_scc1 .LBB1_1 -; FLATSCR-NEXT: ; %bb.2: ; %split +; FLATSCR-NEXT: ; %bb.2: ; %static-memset-post-expansion ; FLATSCR-NEXT: s_movk_i32 s0, 0x2000 -; FLATSCR-NEXT: s_add_i32 s1, s33, s0 -; FLATSCR-NEXT: s_add_i32 s0, s1, 0x3000 -; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s0 offset:208 glc +; FLATSCR-NEXT: s_add_i32 s4, s33, s0 +; FLATSCR-NEXT: s_mov_b32 s0, 0 +; FLATSCR-NEXT: s_mov_b32 s3, s0 +; FLATSCR-NEXT: s_mov_b32 s1, s0 +; FLATSCR-NEXT: s_mov_b32 s2, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v5, s3 +; FLATSCR-NEXT: s_addk_i32 s4, 0x3000 +; FLATSCR-NEXT: v_mov_b32_e32 v4, s2 +; FLATSCR-NEXT: v_mov_b32_e32 v3, s1 +; FLATSCR-NEXT: v_mov_b32_e32 v2, s0 +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s4 offset:256 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[2:5], s4 offset:272 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_add_i32 s0, s33, 0x3000 +; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s4 offset:208 glc +; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s0 offset:64 glc ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s32, s34 -; FLATSCR-NEXT: s_mov_b32 s34, s3 -; FLATSCR-NEXT: s_mov_b32 s33, s2 +; FLATSCR-NEXT: s_mov_b32 s34, s6 +; FLATSCR-NEXT: s_mov_b32 s33, s5 ; FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc ; FLATSCR-NEXT: global_store_dwordx2 v[0:1], v[2:3], off @@ -216,76 +615,222 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out ; MUBUF-NEXT: s_mov_b32 s4, 0 ; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: .LBB2_1: ; %loadstoreloop +; MUBUF-NEXT: .LBB2_1: ; %static-memset-expansion-main-body ; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1 ; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000 ; MUBUF-NEXT: v_add_u32_e32 v1, s4, v2 -; MUBUF-NEXT: s_add_i32 s4, s4, 1 -; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120 -; MUBUF-NEXT: buffer_store_byte v0, v1, s[0:3], 0 offen +; MUBUF-NEXT: s_addk_i32 s4, 0x100 +; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2100 +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:252 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:248 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:244 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:240 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:236 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:232 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:228 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:224 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:220 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:216 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:212 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:208 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:204 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:200 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:196 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:192 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:188 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:184 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:180 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:176 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:172 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:168 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:164 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:160 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:156 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:152 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:148 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:144 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:140 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:136 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:132 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:128 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:124 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:120 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:116 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:112 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:108 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:104 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:100 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:96 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:92 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:88 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:84 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:80 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:76 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:72 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:68 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:64 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:60 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:56 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:52 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:48 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:44 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:40 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:36 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:32 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:28 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:24 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:20 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:16 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:8 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen offset:4 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_cbranch_scc1 .LBB2_1 -; MUBUF-NEXT: ; %bb.2: ; %split -; MUBUF-NEXT: s_movk_i32 s5, 0x12d4 -; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000 -; MUBUF-NEXT: v_or_b32_e32 v0, s5, v1 -; MUBUF-NEXT: s_movk_i32 s5, 0x12d0 +; MUBUF-NEXT: ; %bb.2: ; %static-memset-post-expansion +; MUBUF-NEXT: v_mov_b32_e32 v0, 0x6100 +; MUBUF-NEXT: v_mov_b32_e32 v6, 0 +; MUBUF-NEXT: s_movk_i32 s4, 0x2110 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000 -; MUBUF-NEXT: s_movk_i32 s4, 0x4000 -; MUBUF-NEXT: buffer_load_dword v5, v0, s[0:3], 0 offen glc +; MUBUF-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:8 ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_or_b32_e32 v0, s5, v1 -; MUBUF-NEXT: s_movk_i32 s5, 0x12c4 +; MUBUF-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:4 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: v_add_u32_e32 v0, s4, v1 +; MUBUF-NEXT: s_movk_i32 s4, 0x12c0 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000 -; MUBUF-NEXT: s_or_b32 s4, s4, 0x12c0 -; MUBUF-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen glc +; MUBUF-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:12 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:8 +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_or_b32_e32 v0, s5, v1 -; MUBUF-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen glc +; MUBUF-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: v_or_b32_e32 v0, s4, v1 +; MUBUF-NEXT: s_movk_i32 s4, 0x12d4 +; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000 +; MUBUF-NEXT: v_or_b32_e32 v1, s4, v2 +; MUBUF-NEXT: s_movk_i32 s4, 0x12d0 +; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000 +; MUBUF-NEXT: buffer_load_dword v5, v1, s[0:3], 0 offen glc +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: v_or_b32_e32 v1, s4, v2 +; MUBUF-NEXT: s_movk_i32 s4, 0x12c4 +; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000 +; MUBUF-NEXT: buffer_load_dword v4, v1, s[0:3], 0 offen glc +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: v_or_b32_e32 v1, s4, v2 +; MUBUF-NEXT: buffer_load_dword v7, v1, s[0:3], 0 offen glc +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: buffer_load_dword v8, v0, s[0:3], 0 offen glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_mov_b32_e32 v0, s4 ; MUBUF-NEXT: s_movk_i32 s4, 0x12cc -; MUBUF-NEXT: v_mov_b32_e32 v3, 0x4000 -; MUBUF-NEXT: v_or_b32_e32 v2, s4, v3 +; MUBUF-NEXT: v_mov_b32_e32 v1, 0x4000 +; MUBUF-NEXT: v_or_b32_e32 v0, s4, v1 ; MUBUF-NEXT: s_movk_i32 s4, 0x12c8 -; MUBUF-NEXT: v_mov_b32_e32 v6, 0x4000 +; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000 +; MUBUF-NEXT: v_or_b32_e32 v1, s4, v2 +; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000 ; MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_mov_b32_e32 v7, 0x4000 -; MUBUF-NEXT: buffer_load_dword v3, v2, s[0:3], 0 offen glc -; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_or_b32_e32 v2, s4, v6 -; MUBUF-NEXT: v_mov_b32_e32 v8, 0x4000 -; MUBUF-NEXT: v_mov_b32_e32 v9, 0x4000 -; MUBUF-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen glc -; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_mov_b32_e32 v10, 0x4000 -; MUBUF-NEXT: buffer_load_dword v6, v7, s[0:3], 0 offen glc +; MUBUF-NEXT: v_mov_b32_e32 v3, 0x4000 +; MUBUF-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: v_mov_b32_e32 v11, 0x4000 -; MUBUF-NEXT: buffer_load_dword v7, v8, s[0:3], 0 offen offset:4 glc +; MUBUF-NEXT: buffer_load_dword v9, v2, s[0:3], 0 offen glc +; MUBUF-NEXT: s_waitcnt vmcnt(0) +; MUBUF-NEXT: v_mov_b32_e32 v2, 0x4000 +; MUBUF-NEXT: buffer_load_dword v10, v2, s[0:3], 0 offen offset:4 glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: v_mov_b32_e32 v12, 0x4000 -; MUBUF-NEXT: buffer_load_dword v8, v9, s[0:3], 0 offen offset:8 glc +; MUBUF-NEXT: buffer_load_dword v2, v3, s[0:3], 0 offen offset:8 glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 -; MUBUF-NEXT: buffer_load_dword v9, v10, s[0:3], 0 offen offset:12 glc +; MUBUF-NEXT: v_mov_b32_e32 v13, 0x4000 +; MUBUF-NEXT: buffer_load_dword v3, v11, s[0:3], 0 offen offset:12 glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v2, v8 -; MUBUF-NEXT: buffer_load_dword v10, v11, s[0:3], 0 offen offset:16 glc +; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0 +; MUBUF-NEXT: buffer_load_dword v11, v12, s[0:3], 0 offen offset:16 glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc -; MUBUF-NEXT: buffer_load_dword v11, v12, s[0:3], 0 offen offset:20 glc +; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v1, v2 +; MUBUF-NEXT: buffer_load_dword v12, v13, s[0:3], 0 offen offset:20 glc ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: v_add_co_u32_e32 v0, vcc, v0, v6 -; MUBUF-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc -; MUBUF-NEXT: v_mov_b32_e32 v12, 0 -; MUBUF-NEXT: v_add_co_u32_e32 v4, vcc, v4, v10 -; MUBUF-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v11, vcc +; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v0, v3, vcc +; MUBUF-NEXT: v_add_co_u32_e32 v0, vcc, v8, v9 +; MUBUF-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v10, vcc +; MUBUF-NEXT: v_add_co_u32_e32 v4, vcc, v4, v11 +; MUBUF-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v12, vcc ; MUBUF-NEXT: s_waitcnt lgkmcnt(0) -; MUBUF-NEXT: global_store_dwordx2 v12, v[4:5], s[4:5] offset:16 +; MUBUF-NEXT: global_store_dwordx2 v6, v[4:5], s[4:5] offset:16 ; MUBUF-NEXT: s_waitcnt vmcnt(0) -; MUBUF-NEXT: global_store_dwordx4 v12, v[0:3], s[4:5] +; MUBUF-NEXT: global_store_dwordx4 v6, v[0:3], s[4:5] ; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_endpgm ; @@ -298,16 +843,67 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out ; FLATSCR-NEXT: scratch_store_dword off, v0, s0 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_mov_b32 s0, 0 -; FLATSCR-NEXT: .LBB2_1: ; %loadstoreloop +; FLATSCR-NEXT: s_mov_b32 s1, s0 +; FLATSCR-NEXT: s_mov_b32 s2, s0 +; FLATSCR-NEXT: s_mov_b32 s3, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v0, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v1, s1 +; FLATSCR-NEXT: v_mov_b32_e32 v2, s2 +; FLATSCR-NEXT: v_mov_b32_e32 v3, s3 +; FLATSCR-NEXT: .LBB2_1: ; %static-memset-expansion-main-body ; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLATSCR-NEXT: s_add_i32 s1, s0, 0x4000 -; FLATSCR-NEXT: s_add_i32 s0, s0, 1 -; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120 -; FLATSCR-NEXT: scratch_store_byte off, v0, s1 +; FLATSCR-NEXT: s_addk_i32 s0, 0x100 +; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2100 +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:240 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:224 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:208 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:192 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:176 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:160 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:144 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:128 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:112 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:96 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:80 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:64 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:48 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:32 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 offset:16 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s1 ; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_cbranch_scc1 .LBB2_1 -; FLATSCR-NEXT: ; %bb.2: ; %split +; FLATSCR-NEXT: ; %bb.2: ; %static-memset-post-expansion +; FLATSCR-NEXT: s_movk_i32 s0, 0x2000 +; FLATSCR-NEXT: s_add_i32 s6, s0, 0x4000 +; FLATSCR-NEXT: s_mov_b32 s0, 0 +; FLATSCR-NEXT: s_mov_b32 s1, s0 +; FLATSCR-NEXT: s_mov_b32 s2, s0 +; FLATSCR-NEXT: s_mov_b32 s3, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v0, s0 +; FLATSCR-NEXT: v_mov_b32_e32 v1, s1 +; FLATSCR-NEXT: v_mov_b32_e32 v2, s2 +; FLATSCR-NEXT: v_mov_b32_e32 v3, s3 ; FLATSCR-NEXT: s_movk_i32 s0, 0x1000 +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s6 offset:256 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) +; FLATSCR-NEXT: scratch_store_dwordx4 off, v[0:3], s6 offset:272 +; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_addk_i32 s0, 0x4000 ; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s0 offset:720 glc ; FLATSCR-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll index 83d6f4f5882b4..a57a4a38b1cbd 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-buffer-fat-pointers-mem-transfer.ll @@ -1328,15 +1328,45 @@ define void @memset_known(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] +; CHECK-NEXT: br label %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY:.*]] +; CHECK: [[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]]: +; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]] ] ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 0), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 1), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 2), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 3)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_4:%.*]] = add nuw i32 [[TMP2]], 16 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 4), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 5), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 6), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 7)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_4]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_8:%.*]] = add nuw i32 [[TMP2]], 32 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 8), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 9), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 10), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 11)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_8]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_12:%.*]] = add nuw i32 [[TMP2]], 48 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 12), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 13), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 14), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 15)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_12]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_16:%.*]] = add nuw i32 [[TMP2]], 64 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 16), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 17), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 18), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 19)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_16]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_20:%.*]] = add nuw i32 [[TMP2]], 80 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 20), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 21), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 22), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 23)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_20]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_24:%.*]] = add nuw i32 [[TMP2]], 96 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 24), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 25), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 26), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 27)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_24]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_28:%.*]] = add nuw i32 [[TMP2]], 112 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 28), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 29), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 30), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 31)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_28]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_32:%.*]] = add nuw i32 [[TMP2]], 128 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 32), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 33), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 34), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 35)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_32]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_36:%.*]] = add nuw i32 [[TMP2]], 144 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 36), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 37), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 38), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 39)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_36]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_40:%.*]] = add nuw i32 [[TMP2]], 160 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 40), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 41), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 42), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 43)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_40]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_44:%.*]] = add nuw i32 [[TMP2]], 176 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 44), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 45), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 46), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 47)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_44]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_48:%.*]] = add nuw i32 [[TMP2]], 192 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 48), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 49), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 50), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 51)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_48]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_52:%.*]] = add nuw i32 [[TMP2]], 208 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 52), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 53), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 54), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 55)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_52]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_56:%.*]] = add nuw i32 [[TMP2]], 224 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 56), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 57), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 58), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 59)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_56]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_60:%.*]] = add nuw i32 [[TMP2]], 240 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 60), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 61), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 62), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 63)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_60]], i32 0, i32 0) +; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 256 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 8192 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: br i1 [[TMP4]], label %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]], label %[[STATIC_MEMSET_POST_LOOP_EXPANSION:.*]] +; CHECK: [[STATIC_MEMSET_POST_LOOP_EXPANSION]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.p7.i32(ptr addrspace(7) noundef nonnull align 16 %ptr, i8 1, i32 8192, i1 false) @@ -1348,15 +1378,9 @@ define void @memset_known_small(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] -; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 32 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[PTR_OFF]], i32 0, i32 0) +; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[PTR_OFF]], 16 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP1]], i32 0, i32 0) ; CHECK-NEXT: ret void ; call void @llvm.memset.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 32, i1 false) @@ -1368,15 +1392,7 @@ define void @memset_known_byte(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] -; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 1 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[PTR_OFF]], i32 0, i32 0) ; CHECK-NEXT: ret void ; call void @llvm.memset.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 1, i1 false) @@ -1388,15 +1404,13 @@ define void @memset_known_tail(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] -; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 bitcast (<8 x i8> splat (i8 1) to i64), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[PTR_OFF]], i32 0, i32 0) +; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[PTR_OFF]], 8 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 bitcast (<4 x i8> splat (i8 1) to i32), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP1]], i32 0, i32 0) +; CHECK-NEXT: [[TMP3:%.*]] = add nuw i32 [[PTR_OFF]], 12 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 bitcast (<2 x i8> splat (i8 1) to i16), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP3]], i32 0, i32 0) +; CHECK-NEXT: [[TMP2:%.*]] = add nuw i32 [[PTR_OFF]], 14 ; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 15 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 15, i1 false) @@ -1408,16 +1422,46 @@ define void @memset_known_i64(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] +; CHECK-NEXT: br label %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY:.*]] +; CHECK: [[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]]: +; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]] ] ; CHECK-NEXT: [[DOTC:%.*]] = trunc i64 [[TMP1]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[DOTC]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i64 [[TMP1]], 1 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 0), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 1), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 2), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 3)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_4:%.*]] = add nuw i32 [[TMP2]], 16 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 4), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 5), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 6), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 7)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_4]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_8:%.*]] = add nuw i32 [[TMP2]], 32 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 8), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 9), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 10), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 11)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_8]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_12:%.*]] = add nuw i32 [[TMP2]], 48 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 12), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 13), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 14), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 15)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_12]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_16:%.*]] = add nuw i32 [[TMP2]], 64 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 16), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 17), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 18), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 19)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_16]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_20:%.*]] = add nuw i32 [[TMP2]], 80 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 20), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 21), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 22), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 23)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_20]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_24:%.*]] = add nuw i32 [[TMP2]], 96 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 24), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 25), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 26), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 27)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_24]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_28:%.*]] = add nuw i32 [[TMP2]], 112 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 28), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 29), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 30), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 31)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_28]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_32:%.*]] = add nuw i32 [[TMP2]], 128 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 32), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 33), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 34), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 35)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_32]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_36:%.*]] = add nuw i32 [[TMP2]], 144 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 36), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 37), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 38), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 39)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_36]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_40:%.*]] = add nuw i32 [[TMP2]], 160 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 40), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 41), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 42), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 43)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_40]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_44:%.*]] = add nuw i32 [[TMP2]], 176 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 44), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 45), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 46), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 47)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_44]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_48:%.*]] = add nuw i32 [[TMP2]], 192 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 48), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 49), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 50), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 51)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_48]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_52:%.*]] = add nuw i32 [[TMP2]], 208 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 52), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 53), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 54), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 55)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_52]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_56:%.*]] = add nuw i32 [[TMP2]], 224 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 56), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 57), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 58), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 59)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_56]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_60:%.*]] = add nuw i32 [[TMP2]], 240 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 60), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 61), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 62), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 63)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_60]], i32 0, i32 0) +; CHECK-NEXT: [[TMP3]] = add i64 [[TMP1]], 256 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 8192 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: br i1 [[TMP4]], label %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]], label %[[STATIC_MEMSET_POST_LOOP_EXPANSION:.*]] +; CHECK: [[STATIC_MEMSET_POST_LOOP_EXPANSION]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.p7.i64(ptr addrspace(7) %ptr, i8 1, i64 8192, i1 false) @@ -1429,15 +1473,9 @@ define void @memset_known_i32_volatile(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] -; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 -2147483648) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 32 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[PTR_OFF]], i32 0, i32 -2147483648) +; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[PTR_OFF]], 16 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP1]], i32 0, i32 -2147483648) ; CHECK-NEXT: ret void ; call void @llvm.memset.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 32, i1 true) @@ -1449,16 +1487,29 @@ define void @memset_unknown(ptr addrspace(7) inreg %ptr, i32 inreg %length) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]], i32 inreg [[LENGTH:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 0, [[LENGTH]] -; CHECK-NEXT: br i1 [[TMP1]], label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP4:%.*]], %[[LOADSTORELOOP]] ] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[LENGTH]], 15 +; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[LENGTH]], [[TMP1]] +; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP4]], 0 +; CHECK-NEXT: br i1 [[TMP12]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY:.*]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_COND:.*]] +; CHECK: [[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]]: +; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]] ] ; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[PTR_OFF]], [[TMP2]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP3]], i32 0, i32 0) -; CHECK-NEXT: [[TMP4]] = add i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], [[LENGTH]] -; CHECK-NEXT: br i1 [[TMP5]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP3]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5]] = add i32 [[TMP2]], 16 +; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], [[TMP4]] +; CHECK-NEXT: br i1 [[TMP6]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_COND]] +; CHECK: [[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_COND]]: +; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[TMP7]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_BODY:.*]], label %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION:.*]] +; CHECK: [[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_BODY]]: +; CHECK-NEXT: [[RESIDUAL_LOOP_INDEX:%.*]] = phi i32 [ 0, %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_COND]] ], [ [[TMP10:%.*]], %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_BODY]] ] +; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP4]], [[RESIDUAL_LOOP_INDEX]] +; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[PTR_OFF]], [[TMP8]] +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP9]], i32 0, i32 0) +; CHECK-NEXT: [[TMP10]] = add i32 [[RESIDUAL_LOOP_INDEX]], 1 +; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i32 [[TMP10]], [[TMP1]] +; CHECK-NEXT: br i1 [[TMP11]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_BODY]], label %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION]] +; CHECK: [[DYNAMIC_MEMSET_POST_LOOP_EXPANSION]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 %length, i1 false) @@ -1475,15 +1526,45 @@ define void @memset.inline_known(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] +; CHECK-NEXT: br label %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY:.*]] +; CHECK: [[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]]: +; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]] ] ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 0), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 1), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 2), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 3)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_4:%.*]] = add nuw i32 [[TMP2]], 16 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 4), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 5), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 6), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 7)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_4]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_8:%.*]] = add nuw i32 [[TMP2]], 32 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 8), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 9), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 10), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 11)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_8]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_12:%.*]] = add nuw i32 [[TMP2]], 48 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 12), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 13), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 14), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 15)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_12]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_16:%.*]] = add nuw i32 [[TMP2]], 64 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 16), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 17), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 18), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 19)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_16]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_20:%.*]] = add nuw i32 [[TMP2]], 80 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 20), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 21), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 22), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 23)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_20]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_24:%.*]] = add nuw i32 [[TMP2]], 96 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 24), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 25), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 26), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 27)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_24]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_28:%.*]] = add nuw i32 [[TMP2]], 112 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 28), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 29), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 30), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 31)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_28]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_32:%.*]] = add nuw i32 [[TMP2]], 128 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 32), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 33), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 34), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 35)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_32]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_36:%.*]] = add nuw i32 [[TMP2]], 144 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 36), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 37), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 38), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 39)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_36]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_40:%.*]] = add nuw i32 [[TMP2]], 160 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 40), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 41), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 42), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 43)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_40]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_44:%.*]] = add nuw i32 [[TMP2]], 176 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 44), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 45), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 46), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 47)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_44]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_48:%.*]] = add nuw i32 [[TMP2]], 192 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 48), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 49), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 50), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 51)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_48]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_52:%.*]] = add nuw i32 [[TMP2]], 208 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 52), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 53), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 54), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 55)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_52]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_56:%.*]] = add nuw i32 [[TMP2]], 224 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 56), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 57), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 58), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 59)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_56]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_60:%.*]] = add nuw i32 [[TMP2]], 240 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 60), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 61), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 62), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 63)>, ptr addrspace(8) align 16 [[PTR_RSRC]], i32 [[DOTPART_60]], i32 0, i32 0) +; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 256 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 8192 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: br i1 [[TMP4]], label %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]], label %[[STATIC_MEMSET_POST_LOOP_EXPANSION:.*]] +; CHECK: [[STATIC_MEMSET_POST_LOOP_EXPANSION]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.inline.p7.i32(ptr addrspace(7) noundef nonnull align 16 %ptr, i8 1, i32 8192, i1 false) @@ -1495,15 +1576,9 @@ define void @memset.inline_known_small(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] -; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 32 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[PTR_OFF]], i32 0, i32 0) +; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[PTR_OFF]], 16 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP1]], i32 0, i32 0) ; CHECK-NEXT: ret void ; call void @llvm.memset.inline.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 32, i1 false) @@ -1515,15 +1590,7 @@ define void @memset.inline_known_byte(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] -; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 1 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[PTR_OFF]], i32 0, i32 0) ; CHECK-NEXT: ret void ; call void @llvm.memset.inline.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 1, i1 false) @@ -1535,15 +1602,13 @@ define void @memset.inline_known_tail(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] -; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i64(i64 bitcast (<8 x i8> splat (i8 1) to i64), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[PTR_OFF]], i32 0, i32 0) +; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[PTR_OFF]], 8 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 bitcast (<4 x i8> splat (i8 1) to i32), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP1]], i32 0, i32 0) +; CHECK-NEXT: [[TMP3:%.*]] = add nuw i32 [[PTR_OFF]], 12 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i16(i16 bitcast (<2 x i8> splat (i8 1) to i16), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP3]], i32 0, i32 0) +; CHECK-NEXT: [[TMP2:%.*]] = add nuw i32 [[PTR_OFF]], 14 ; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 15 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.inline.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 15, i1 false) @@ -1555,16 +1620,46 @@ define void @memset.inline_known_i64(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] +; CHECK-NEXT: br label %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY:.*]] +; CHECK: [[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]]: +; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]] ] ; CHECK-NEXT: [[DOTC:%.*]] = trunc i64 [[TMP1]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[DOTC]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) -; CHECK-NEXT: [[TMP3]] = add i64 [[TMP1]], 1 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 0), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 1), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 2), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 3)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_4:%.*]] = add nuw i32 [[TMP2]], 16 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 4), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 5), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 6), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 7)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_4]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_8:%.*]] = add nuw i32 [[TMP2]], 32 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 8), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 9), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 10), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 11)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_8]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_12:%.*]] = add nuw i32 [[TMP2]], 48 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 12), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 13), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 14), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 15)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_12]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_16:%.*]] = add nuw i32 [[TMP2]], 64 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 16), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 17), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 18), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 19)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_16]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_20:%.*]] = add nuw i32 [[TMP2]], 80 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 20), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 21), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 22), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 23)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_20]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_24:%.*]] = add nuw i32 [[TMP2]], 96 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 24), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 25), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 26), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 27)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_24]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_28:%.*]] = add nuw i32 [[TMP2]], 112 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 28), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 29), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 30), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 31)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_28]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_32:%.*]] = add nuw i32 [[TMP2]], 128 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 32), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 33), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 34), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 35)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_32]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_36:%.*]] = add nuw i32 [[TMP2]], 144 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 36), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 37), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 38), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 39)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_36]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_40:%.*]] = add nuw i32 [[TMP2]], 160 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 40), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 41), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 42), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 43)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_40]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_44:%.*]] = add nuw i32 [[TMP2]], 176 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 44), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 45), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 46), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 47)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_44]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_48:%.*]] = add nuw i32 [[TMP2]], 192 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 48), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 49), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 50), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 51)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_48]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_52:%.*]] = add nuw i32 [[TMP2]], 208 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 52), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 53), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 54), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 55)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_52]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_56:%.*]] = add nuw i32 [[TMP2]], 224 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 56), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 57), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 58), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 59)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_56]], i32 0, i32 0) +; CHECK-NEXT: [[DOTPART_60:%.*]] = add nuw i32 [[TMP2]], 240 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 60), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 61), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 62), i32 extractelement (<64 x i32> bitcast (<256 x i8> splat (i8 1) to <64 x i32>), i32 63)>, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[DOTPART_60]], i32 0, i32 0) +; CHECK-NEXT: [[TMP3]] = add i64 [[TMP1]], 256 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 8192 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: br i1 [[TMP4]], label %[[STATIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]], label %[[STATIC_MEMSET_POST_LOOP_EXPANSION:.*]] +; CHECK: [[STATIC_MEMSET_POST_LOOP_EXPANSION]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.inline.p7.i64(ptr addrspace(7) %ptr, i8 1, i64 8192, i1 false) @@ -1576,15 +1671,9 @@ define void @memset.inline_known_i32_volatile(ptr addrspace(7) inreg %ptr) { ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ] -; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[PTR_OFF]], [[TMP1]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP2]], i32 0, i32 -2147483648) -; CHECK-NEXT: [[TMP3]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 32 -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[PTR_OFF]], i32 0, i32 -2147483648) +; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[PTR_OFF]], 16 +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP1]], i32 0, i32 -2147483648) ; CHECK-NEXT: ret void ; call void @llvm.memset.inline.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 32, i1 true) @@ -1596,16 +1685,29 @@ define void @memset.inline_unknown(ptr addrspace(7) inreg %ptr, i32 inreg %lengt ; CHECK-SAME: { ptr addrspace(8), i32 } inreg [[PTR:%.*]], i32 inreg [[LENGTH:%.*]]) #[[ATTR0]] { ; CHECK-NEXT: [[PTR_RSRC:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 0 ; CHECK-NEXT: [[PTR_OFF:%.*]] = extractvalue { ptr addrspace(8), i32 } [[PTR]], 1 -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 0, [[LENGTH]] -; CHECK-NEXT: br i1 [[TMP1]], label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP4:%.*]], %[[LOADSTORELOOP]] ] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[LENGTH]], 15 +; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[LENGTH]], [[TMP1]] +; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP4]], 0 +; CHECK-NEXT: br i1 [[TMP12]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY:.*]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_COND:.*]] +; CHECK: [[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]]: +; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]] ] ; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[PTR_OFF]], [[TMP2]] -; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP3]], i32 0, i32 0) -; CHECK-NEXT: [[TMP4]] = add i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i32 [[TMP4]], [[LENGTH]] -; CHECK-NEXT: br i1 [[TMP5]], label %[[LOADSTORELOOP]], label %[[SPLIT]] -; CHECK: [[SPLIT]]: +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.v4i32(<4 x i32> bitcast (<16 x i8> splat (i8 1) to <4 x i32>), ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP3]], i32 0, i32 0) +; CHECK-NEXT: [[TMP5]] = add i32 [[TMP2]], 16 +; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i32 [[TMP5]], [[TMP4]] +; CHECK-NEXT: br i1 [[TMP6]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_COND]] +; CHECK: [[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_COND]]: +; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[TMP7]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_BODY:.*]], label %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION:.*]] +; CHECK: [[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_BODY]]: +; CHECK-NEXT: [[RESIDUAL_LOOP_INDEX:%.*]] = phi i32 [ 0, %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_COND]] ], [ [[TMP10:%.*]], %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_BODY]] ] +; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP4]], [[RESIDUAL_LOOP_INDEX]] +; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[PTR_OFF]], [[TMP8]] +; CHECK-NEXT: call void @llvm.amdgcn.raw.ptr.buffer.store.i8(i8 1, ptr addrspace(8) align 1 [[PTR_RSRC]], i32 [[TMP9]], i32 0, i32 0) +; CHECK-NEXT: [[TMP10]] = add i32 [[RESIDUAL_LOOP_INDEX]], 1 +; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i32 [[TMP10]], [[TMP1]] +; CHECK-NEXT: br i1 [[TMP11]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_RESIDUAL_BODY]], label %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION]] +; CHECK: [[DYNAMIC_MEMSET_POST_LOOP_EXPANSION]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.inline.p7.i32(ptr addrspace(7) %ptr, i8 1, i32 %length, i1 false) diff --git a/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll b/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll index cf3443ff33b72..3d73b55831cd0 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics-threshold.ll @@ -21,15 +21,6 @@ define amdgpu_kernel void @memset_size_0(ptr addrspace(1) %dst, i8 %val) { ; OPT4-NEXT: ret void ; ; OPT0-LABEL: @memset_size_0( -; OPT0-NEXT: br i1 true, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]] -; OPT0: loadstoreloop: -; OPT0-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ] -; OPT0-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 [[TMP1]] -; OPT0-NEXT: store i8 [[VAL:%.*]], ptr addrspace(1) [[TMP2]], align 1 -; OPT0-NEXT: [[TMP3]] = add i64 [[TMP1]], 1 -; OPT0-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 0 -; OPT0-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]] -; OPT0: split: ; OPT0-NEXT: ret void ; ; OPT_NEG-LABEL: @memset_size_0( @@ -50,15 +41,11 @@ define amdgpu_kernel void @memset_size_4(ptr addrspace(1) %dst, i8 %val) { ; OPT4-NEXT: ret void ; ; OPT0-LABEL: @memset_size_4( -; OPT0-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]] -; OPT0: loadstoreloop: -; OPT0-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ] -; OPT0-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 [[TMP1]] -; OPT0-NEXT: store i8 [[VAL:%.*]], ptr addrspace(1) [[TMP2]], align 1 -; OPT0-NEXT: [[TMP3]] = add i64 [[TMP1]], 1 -; OPT0-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 4 -; OPT0-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]] -; OPT0: split: +; OPT0-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[VAL:%.*]], i64 0 +; OPT0-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <4 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer +; OPT0-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <4 x i8> [[SETVALUE_SPLAT_SPLAT]] to i32 +; OPT0-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 0 +; OPT0-NEXT: store i32 [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP1]], align 1 ; OPT0-NEXT: ret void ; ; OPT_NEG-LABEL: @memset_size_4( @@ -75,27 +62,19 @@ define amdgpu_kernel void @memset_size_8(ptr addrspace(1) %dst, i8 %val) { ; OPT8-NEXT: ret void ; ; OPT4-LABEL: @memset_size_8( -; OPT4-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]] -; OPT4: loadstoreloop: -; OPT4-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ] -; OPT4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 [[TMP1]] -; OPT4-NEXT: store i8 [[VAL:%.*]], ptr addrspace(1) [[TMP2]], align 1 -; OPT4-NEXT: [[TMP3]] = add i64 [[TMP1]], 1 -; OPT4-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 8 -; OPT4-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]] -; OPT4: split: +; OPT4-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i8> poison, i8 [[VAL:%.*]], i64 0 +; OPT4-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <8 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <8 x i8> poison, <8 x i32> zeroinitializer +; OPT4-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <8 x i8> [[SETVALUE_SPLAT_SPLAT]] to i64 +; OPT4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 0 +; OPT4-NEXT: store i64 [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP1]], align 1 ; OPT4-NEXT: ret void ; ; OPT0-LABEL: @memset_size_8( -; OPT0-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]] -; OPT0: loadstoreloop: -; OPT0-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ] -; OPT0-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 [[TMP1]] -; OPT0-NEXT: store i8 [[VAL:%.*]], ptr addrspace(1) [[TMP2]], align 1 -; OPT0-NEXT: [[TMP3]] = add i64 [[TMP1]], 1 -; OPT0-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 8 -; OPT0-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]] -; OPT0: split: +; OPT0-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <8 x i8> poison, i8 [[VAL:%.*]], i64 0 +; OPT0-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <8 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <8 x i8> poison, <8 x i32> zeroinitializer +; OPT0-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <8 x i8> [[SETVALUE_SPLAT_SPLAT]] to i64 +; OPT0-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 0 +; OPT0-NEXT: store i64 [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP1]], align 1 ; OPT0-NEXT: ret void ; ; OPT_NEG-LABEL: @memset_size_8( diff --git a/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll index 20a34dc997bbc..929ef2fc3c06c 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-mem-intrinsics.ll @@ -163,15 +163,18 @@ define amdgpu_kernel void @max_size_small_static_memset_caller0(ptr addrspace(1) ; MAX1024-NEXT: ret void ; ; ALL-LABEL: @max_size_small_static_memset_caller0( -; ALL-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]] -; ALL: loadstoreloop: +; ALL-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <256 x i8> poison, i8 [[VAL:%.*]], i64 0 +; ALL-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <256 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <256 x i8> poison, <256 x i32> zeroinitializer +; ALL-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <256 x i8> [[SETVALUE_SPLAT_SPLAT]] to <64 x i32> +; ALL-NEXT: br label [[LOADSTORELOOP:%.*]] +; ALL: static-memset-expansion-main-body: ; ALL-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ] ; ALL-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 [[TMP1]] -; ALL-NEXT: store i8 [[VAL:%.*]], ptr addrspace(1) [[TMP2]], align 1 -; ALL-NEXT: [[TMP3]] = add i64 [[TMP1]], 1 +; ALL-NEXT: store <64 x i32> [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP2]], align 1 +; ALL-NEXT: [[TMP3]] = add i64 [[TMP1]], 256 ; ALL-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 1024 -; ALL-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]] -; ALL: split: +; ALL-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT:%.*]] +; ALL: static-memset-post-expansion: ; ALL-NEXT: ret void ; call void @llvm.memset.p1.i64(ptr addrspace(1) %dst, i8 %val, i64 1024, i1 false) @@ -180,21 +183,60 @@ define amdgpu_kernel void @max_size_small_static_memset_caller0(ptr addrspace(1) define amdgpu_kernel void @min_size_large_static_memset_caller0(ptr addrspace(1) %dst, i8 %val) #0 { ; OPT-LABEL: @min_size_large_static_memset_caller0( -; OPT-NEXT: br i1 false, label [[SPLIT:%.*]], label [[LOADSTORELOOP:%.*]] -; OPT: loadstoreloop: +; OPT-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <256 x i8> poison, i8 [[VAL:%.*]], i64 0 +; OPT-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <256 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <256 x i8> poison, <256 x i32> zeroinitializer +; OPT-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <256 x i8> [[SETVALUE_SPLAT_SPLAT]] to <64 x i32> +; OPT-NEXT: br label [[LOADSTORELOOP:%.*]] +; OPT: static-memset-expansion-main-body: ; OPT-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], [[LOADSTORELOOP]] ] ; OPT-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 [[TMP1]] -; OPT-NEXT: store i8 [[VAL:%.*]], ptr addrspace(1) [[TMP2]], align 1 -; OPT-NEXT: [[TMP3]] = add i64 [[TMP1]], 1 -; OPT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 1025 -; OPT-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT]] -; OPT: split: +; OPT-NEXT: store <64 x i32> [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP2]], align 1 +; OPT-NEXT: [[TMP3]] = add i64 [[TMP1]], 256 +; OPT-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 1024 +; OPT-NEXT: br i1 [[TMP4]], label [[LOADSTORELOOP]], label [[SPLIT:%.*]] +; OPT: static-memset-post-expansion: +; OPT-NEXT: [[TMP5:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 1024 +; OPT-NEXT: store i8 [[VAL]], ptr addrspace(1) [[TMP5]], align 1 ; OPT-NEXT: ret void ; call void @llvm.memset.p1.i64(ptr addrspace(1) %dst, i8 %val, i64 1025, i1 false) ret void } +define amdgpu_kernel void @variable_size_memset_caller0(ptr addrspace(1) %dst, i8 %val, i64 %n) #0 { +; OPT-LABEL: @variable_size_memset_caller0( +; OPT-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[VAL:%.*]], i64 0 +; OPT-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <16 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer +; OPT-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <16 x i8> [[SETVALUE_SPLAT_SPLAT]] to <4 x i32> +; OPT-NEXT: [[TMP1:%.*]] = and i64 [[N:%.*]], 15 +; OPT-NEXT: [[TMP2:%.*]] = sub i64 [[N]], [[TMP1]] +; OPT-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP2]], 0 +; OPT-NEXT: br i1 [[TMP3]], label [[DYNAMIC_MEMSET_EXPANSION_MAIN_BODY:%.*]], label [[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_COND:%.*]] +; OPT: dynamic-memset-expansion-main-body: +; OPT-NEXT: [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[DYNAMIC_MEMSET_EXPANSION_MAIN_BODY]] ] +; OPT-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST:%.*]], i64 [[LOOP_INDEX]] +; OPT-NEXT: store <4 x i32> [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP4]], align 1 +; OPT-NEXT: [[TMP5]] = add i64 [[LOOP_INDEX]], 16 +; OPT-NEXT: [[TMP6:%.*]] = icmp ult i64 [[TMP5]], [[TMP2]] +; OPT-NEXT: br i1 [[TMP6]], label [[DYNAMIC_MEMSET_EXPANSION_MAIN_BODY]], label [[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_COND]] +; OPT: dynamic-memset-expansion-residual-cond: +; OPT-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP1]], 0 +; OPT-NEXT: br i1 [[TMP7]], label [[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_BODY:%.*]], label [[DYNAMIC_MEMSET_POST_EXPANSION:%.*]] +; OPT: dynamic-memset-expansion-residual-body: +; OPT-NEXT: [[RESIDUAL_LOOP_INDEX:%.*]] = phi i64 [ 0, [[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_COND]] ], [ [[TMP10:%.*]], [[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_BODY]] ] +; OPT-NEXT: [[TMP8:%.*]] = add i64 [[TMP2]], [[RESIDUAL_LOOP_INDEX]] +; OPT-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 [[TMP8]] +; OPT-NEXT: store i8 [[VAL]], ptr addrspace(1) [[TMP9]], align 1 +; OPT-NEXT: [[TMP10]] = add i64 [[RESIDUAL_LOOP_INDEX]], 1 +; OPT-NEXT: [[TMP11:%.*]] = icmp ult i64 [[TMP10]], [[TMP1]] +; OPT-NEXT: br i1 [[TMP11]], label [[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_BODY]], label [[DYNAMIC_MEMSET_POST_EXPANSION]] +; OPT: dynamic-memset-post-expansion: +; OPT-NEXT: ret void +; + call void @llvm.memset.p1.i64(ptr addrspace(1) %dst, i8 %val, i64 %n, i1 false) + ret void +} + define amdgpu_kernel void @variable_memcpy_caller0(ptr addrspace(1) %dst, ptr addrspace(1) %src, i64 %n) #0 { ; OPT-LABEL: @variable_memcpy_caller0( ; OPT-NEXT: [[TMP2:%.*]] = and i64 [[N:%.*]], 15 diff --git a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll index 247a0a9a64b33..7d73439ecd381 100644 --- a/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll +++ b/llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll @@ -1,9 +1,14 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GCN,GFX942 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GISEL,GFX942-GISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GISEL,GFX1250-GISEL %s define i64 @lshl_add_u64_v1v(i64 %v, i64 %a) { ; GCN-LABEL: lshl_add_u64_v1v: ; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 1, v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_v1v: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 1, v[{{[0-9:]+}}] %shl = shl i64 %v, 1 %add = add i64 %shl, %a ret i64 %add @@ -12,6 +17,9 @@ define i64 @lshl_add_u64_v1v(i64 %v, i64 %a) { define i64 @lshl_add_u64_v4v(i64 %v, i64 %a) { ; GCN-LABEL: lshl_add_u64_v4v: ; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 4, v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_v4v: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 4, v[{{[0-9:]+}}] %shl = shl i64 %v, 4 %add = add i64 %shl, %a ret i64 %add @@ -23,6 +31,9 @@ define i64 @lshl_add_u64_v5v(i64 %v, i64 %a) { ; GFX942-NEXT: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0, v[{{[0-9:]+}}] ; GFX1250-NEXT: s_delay_alu ; GFX1250-NEXT: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_v5v: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] %shl = shl i64 %v, 5 %add = add i64 %shl, %a ret i64 %add @@ -34,6 +45,9 @@ define i64 @lshl_add_u64_vvv(i64 %v, i64 %s, i64 %a) { ; GFX942-NEXT: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0, v[{{[0-9:]+}}] ; GFX1250-NEXT: s_delay_alu ; GFX1250-NEXT: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_vvv: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] %shl = shl i64 %v, %s %add = add i64 %shl, %a ret i64 %add @@ -42,6 +56,9 @@ define i64 @lshl_add_u64_vvv(i64 %v, i64 %s, i64 %a) { define amdgpu_kernel void @lshl_add_u64_s2v(i64 %v) { ; GCN-LABEL: lshl_add_u64_s2v: ; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 2, v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_s2v: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, s{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_add_nc_u64_e32 v[{{[0-9:]+}}], s[{{[0-9:]+}}], v[{{[0-9:]+}}] %a = load i64, ptr poison %shl = shl i64 %v, 2 %add = add i64 %shl, %a @@ -52,6 +69,9 @@ define amdgpu_kernel void @lshl_add_u64_s2v(i64 %v) { define amdgpu_kernel void @lshl_add_u64_v2s(i64 %a) { ; GCN-LABEL: lshl_add_u64_v2s: ; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 2, s[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_v2s: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, s{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 2, s[{{[0-9:]+}}] %v = load i64, ptr poison %shl = shl i64 %v, 2 %add = add i64 %shl, %a @@ -65,6 +85,9 @@ define amdgpu_kernel void @lshl_add_u64_s2s(i64 %v, i64 %a) { ; GFX942: s_add_u32 ; GFX942: s_addc_u32 ; GFX1250: s_add_nc_u64 +; GISEL-LABEL: lshl_add_u64_s2s: +; GFX942-GISEL: s_addc_u32 +; GFX1250-GISEL: s_add_nc_u64 %shl = shl i64 %v, 2 %add = add i64 %shl, %a store i64 %add, ptr poison @@ -75,6 +98,9 @@ define i64 @add_u64_vv(i64 %v, i64 %a) { ; GCN-LABEL: add_u64_vv: ; GFX942: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] ; GFX1250: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3] +; GISEL-LABEL: add_u64_vv: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3] %add = add i64 %v, %a ret i64 %add } @@ -83,6 +109,9 @@ define amdgpu_kernel void @add_u64_sv(i64 %v) { ; GCN-LABEL: add_u64_sv: ; GFX942: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX1250: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] +; GISEL-LABEL: add_u64_sv: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, s{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] %a = load i64, ptr poison %add = add i64 %v, %a store i64 %add, ptr poison @@ -93,6 +122,9 @@ define amdgpu_kernel void @add_u64_vs(i64 %a) { ; GCN-LABEL: add_u64_vs: ; GFX942: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] ; GFX1250: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] +; GISEL-LABEL: add_u64_vs: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, s{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] %v = load i64, ptr poison %add = add i64 %v, %a store i64 %add, ptr poison @@ -104,6 +136,8 @@ define amdgpu_kernel void @add_u64_ss(i64 %v, i64 %a) { ; GFX942: s_add_u32 ; GFX942: s_addc_u32 s1, s1, s3 ; GFX1250: s_add_nc_u64 s[0:1], s[0:1], s[2:3] +; GISEL-LABEL: add_u64_ss: +; GFX1250-GISEL: s_add_nc_u64 s[0:1], s[0:1], s[2:3] %add = add i64 %v, %a store i64 %add, ptr poison ret void @@ -112,7 +146,136 @@ define amdgpu_kernel void @add_u64_ss(i64 %v, i64 %a) { define i32 @lshl_add_u64_gep(ptr %p, i64 %a) { ; GCN-LABEL: lshl_add_u64_gep: ; GCN: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1] +; GISEL-LABEL: lshl_add_u64_gep: +; GISEL: v_lshl_add_u64 v[0:1], v[2:3], 2, v[0:1] %gep = getelementptr inbounds i32, ptr %p, i64 %a %v = load i32, ptr %gep ret i32 %v } + +define i64 @lshl_add_u64_vvv_and_2(i64 %v, i64 %a, i64 %s) { +; GCN-LABEL: lshl_add_u64_vvv_and_2: +; GCN: v_and_b32_e32 [[AND:v[0-9:]+]], 2, v{{[0-9:]+}} +; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND]], v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_vvv_and_2: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_and_b32_e32 [[AND:v[0-9:]+]], 2, v{{[0-9:]+}} +; GFX1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND]], v[{{[0-9:]+}}] + %and = and i64 %s, 2 + %shl = shl i64 %v, %and + %add = add i64 %shl, %a + ret i64 %add +} + +define i64 @lshl_add_u64_vvv_and_4(i64 %v, i64 %a, i64 %s) { +; GCN-LABEL: lshl_add_u64_vvv_and_4: +; GCN: v_and_b32_e32 [[AND:v[0-9:]+]], 4, v{{[0-9:]+}} +; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND]], v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_vvv_and_4: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_and_b32_e32 [[AND:v[0-9:]+]], 4, v{{[0-9:]+}} +; GFX1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND]], v[{{[0-9:]+}}] + %and = and i64 %s, 4 + %shl = shl i64 %v, %and + %add = add i64 %shl, %a + ret i64 %add +} + +define i64 @lshl_add_u64_vvv_and_5(i64 %v, i64 %a, i64 %s) { +; GCN-LABEL: lshl_add_u64_vvv_and_5: +; GFX942: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0, v[{{[0-9:]+}}] +; GFX1250: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_vvv_and_5: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] + %and = and i64 %s, 5 + %shl = shl i64 %v, %and + %add = add i64 %shl, %a + ret i64 %add +} + +define i64 @lshl_add_u64_vvv_urem(i64 %v, i64 %a, i64 %s) { +; GCN-LABEL: lshl_add_u64_vvv_urem: +; GCN: v_and_b32_e32 [[AND:v[0-9:]+]], 3, v{{[0-9:]+}} +; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND]], v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_vvv_urem: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND]], v[{{[0-9:]+}}] + %urem = urem i64 %s, 4 + %shl = shl i64 %v, %urem + %add = add i64 %shl, %a + ret i64 %add +} + +define <4 x i64> @lshl_add_u64_vvv_and_2_v4(<4 x i64> %v, <4 x i64> %a, <4 x i64> %s) { +; GCN-LABEL: lshl_add_u64_vvv_and_2_v4: +; GCN-DAG: v_and_b32_e32 [[AND5:v[0-9:]+]], 5, v{{[0-9:]+}} +; GCN-DAG: v_and_b32_e32 [[AND3:v[0-9:]+]], 1, v{{[0-9:]+}} +; GCN-DAG: v_and_b32_e32 [[AND2:v[0-9:]+]], 2, v{{[0-9:]+}} +; GCN-DAG: v_and_b32_e32 [[AND1:v[0-9:]+]], 3, v{{[0-9:]+}} +; GCN-DAG: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND1]], v[{{[0-9:]+}}] +; GCN-DAG: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND2]], v[{{[0-9:]+}}] +; GCN-DAG: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND3]], v[{{[0-9:]+}}] +; GFX1250: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] +; GFX942: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], 0, v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_vvv_and_2_v4: +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX1250-GISEL-DAG: v_and_b32_e32 [[AND5:v[0-9:]+]], 5, v{{[0-9:]+}} +; GFX1250-GISEL-DAG: v_and_b32_e32 [[AND3:v[0-9:]+]], 1, v{{[0-9:]+}} +; GFX1250-GISEL-DAG: v_and_b32_e32 [[AND2:v[0-9:]+]], 2, v{{[0-9:]+}} +; GFX1250-GISEL-DAG: v_and_b32_e32 [[AND1:v[0-9:]+]], 3, v{{[0-9:]+}} +; GFX1250-GISEL-DAG: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND1]], v[{{[0-9:]+}}] +; GFX1250-GISEL-DAG v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], [[AND2]], v[{{[0-9:]+}}] +; GFX1250-GISEL: v_add_nc_u64_e32 v[{{[0-9:]+}}], v[{{[0-9:]+}}], v[{{[0-9:]+}}] + %and = and <4 x i64> %s, + %shl = shl <4 x i64> %v, %and + %add = add <4 x i64> %shl, %a + ret <4 x i64> %add +} + +define amdgpu_ps <2 x i32> @lshl_add_u64_sss_and_4(i32 inreg %v, i32 inreg %a, i32 inreg %s) { +; GCN-LABEL: lshl_add_u64_sss_and_4 +; GFX942: s_add_i32 s{{[0-9:]+}}, s{{[0-9:]+}}, s{{[0-9:]+}} +; GFX1250: s_add_co_i32 s{{[0-9:]+}}, s{{[0-9:]+}}, s{{[0-9:]+}} +; GISEL-LABEL: lshl_add_u64_sss_and_4 +; GFX942-GISEL: s_add_i32 s{{[0-9:]+}}, s{{[0-9:]+}}, s{{[0-9:]+}} +; GFX1250-GISEL: s_add_co_i32 s{{[0-9:]+}}, s{{[0-9:]+}}, s{{[0-9:]+}} + %and = and i32 %s, 4 + %zext_and = zext i32 %and to i64 + %zext_a = zext i32 %and to i64 + %zext_v = zext i32 %and to i64 + %shl = shl i64 %zext_v, %zext_and + %add = add i64 %shl, %zext_a + %bitcast = bitcast i64 %add to <2 x i32> + ret <2 x i32> %bitcast +} + +define amdgpu_ps <2 x i32> @lshl_add_u64_svs_and_4(i32 inreg %v, i64 %a, i32 inreg %s) { +; GCN-LABEL: lshl_add_u64_svs_and_4 +; GFX-1250: v_lshl_add_u64 v[{{[0-9:]+}}], s{{[0-9:]+}}, s{{[0-9:]+}}, v[{{[0-9:]+}}] +; GFX-942: v_lshl_add_u64 v[{{[0-9:]+}}], s[{{[0-9:]+}}], 0, v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_svs_and_4 +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, s{{[0-9:]+}}, v{{[0-9:]+}} +; GFX-1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], s{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}] + %and = and i32 %s, 4 + %zext_and = zext i32 %and to i64 + %zext_v = zext i32 %and to i64 + %shl = shl i64 %zext_v, %zext_and + %add = add i64 %shl, %a + %bitcast = bitcast i64 %add to <2 x i32> + ret <2 x i32> %bitcast +} + +define amdgpu_ps <2 x i32> @lshl_add_u64_vvs_and_4(i64 %v, i64 %a, i32 inreg %s) { +; GCN-LABEL: lshl_add_u64_vvs_and_4 +; GCN: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}] +; GISEL-LABEL: lshl_add_u64_vvs_and_4 +; GFX942-GISEL: v_add_co_u32_e32 v{{[0-9:]+}}, vcc, v{{[0-9:]+}}, v{{[0-9:]+}} +; GFX-1250-GISEL: v_lshl_add_u64 v[{{[0-9:]+}}], v[{{[0-9:]+}}], s{{[0-9:]+}}, v[{{[0-9:]+}}] + %and = and i32 %s, 4 + %zext_and = zext i32 %and to i64 + %shl = shl i64 %v, %zext_and + %add = add i64 %shl, %a + %bitcast = bitcast i64 %add to <2 x i32> + ret <2 x i32> %bitcast +} diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir new file mode 100644 index 0000000000000..cf186d0588afc --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-rematerialization-scoring.mir @@ -0,0 +1,523 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule -verify-machineinstrs %s -o - | FileCheck %s + +# All tests are almost identical, the only differences being that some +# VGPR-defining instructions are progressively made artificially +# unrematerializable with an implicit def to test rematerialization +# priorities. The CFG is the following for all tests in the file. +# +# +---+ +# | 0 | +# +---+ +# | +# v +# +---+ +# +------>| 1 |-----+ +# | +---+ | +# | | v +# | | +---+ +# | | | 2 | +# | | +-+-+ +# | v | +# +---+ +---+ | +# | 4 |<----| 3 |<----+ +# +---+ +---+ +# | +# v +# +---+ +# | 5 | +# +---+ + +# %32's defining and using region frequencies are identical therefore it is the +# best register to rematerialize. +name: favor_same_frequency +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true +body: | + ; CHECK-LABEL: name: favor_same_frequency + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $vgpr0, $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %mem_addr:sgpr_64 = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: %loop_if_bound:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: %mem_data:sreg_64_xexec = S_LOAD_DWORDX2_IMM %mem_addr, 52, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4) + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode + ; CHECK-NEXT: %exec_loop_mask:sreg_64 = V_CMP_GT_U32_e64 %mem_data.sub0, %loop_if_bound, implicit $exec + ; CHECK-NEXT: %loop_counter:sreg_32 = COPY %mem_data.sub1 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_3:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_4:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_5:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_6:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_12:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_13:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_14:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_15:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_17:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_18:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_24:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_25:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_26:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_27:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_28:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_30:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_31:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %exec_save_if:sreg_64 = COPY $exec, implicit-def $exec + ; CHECK-NEXT: %exec_if:sreg_64 = S_AND_B64 %exec_save_if, %exec_loop_mask, implicit-def dead $scc + ; CHECK-NEXT: $exec = S_MOV_B64_term %exec_if + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_24]], implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]], implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.5(0x04000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $exec = S_OR_B64 $exec, %exec_save_if, implicit-def $scc + ; CHECK-NEXT: %loop_counter:sreg_32 = S_ADD_I32 %loop_counter, -1, implicit-def dead $scc + ; CHECK-NEXT: S_CMP_LG_U32 %loop_counter, 0, implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.5, implicit killed $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]], implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]], implicit [[V_CVT_I32_F64_e32_7]] + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]], implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]], implicit [[V_CVT_I32_F64_e32_15]] + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]], implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]] + ; CHECK-NEXT: S_BRANCH %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_32]] + ; CHECK-NEXT: S_ENDPGM 0 + bb.0: + liveins: $vgpr0, $sgpr0_sgpr1 + + %mem_addr:sgpr_64 = COPY $sgpr0_sgpr1 + %loop_if_bound:vgpr_32 = COPY $vgpr0 + %mem_data:sreg_64_xexec = S_LOAD_DWORDX2_IMM %mem_addr, 52, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4) + %exec_loop_mask:sreg_64 = V_CMP_GT_U32_e64 %mem_data.sub0, killed %loop_if_bound, implicit $exec + %loop_counter:sreg_32 = COPY %mem_data.sub1 + + %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode + %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode + %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode + %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode + %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode + %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode + %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode + %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode + %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode + %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode + %10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + %11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode + %12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode + %13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode + %14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode + %15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode + %16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode + %17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode + %18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode + %19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode + %20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode + %21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode + %22:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode + %23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode + %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode + %25:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode + %26:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode + %27:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode + %28:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode + %29:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode + %30:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode + %31:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode + %32:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode + + bb.1: + successors: %bb.2, %bb.3 + + %exec_save_if:sreg_64 = COPY $exec, implicit-def $exec + %exec_if:sreg_64 = S_AND_B64 %exec_save_if, %exec_loop_mask, implicit-def dead $scc + $exec = S_MOV_B64_term %exec_if + S_CBRANCH_EXECZ %bb.3, implicit $exec + S_BRANCH %bb.2 + + bb.2: + successors: %bb.3 + + S_NOP 0, implicit %24, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29, implicit %30, implicit %31 + + bb.3: + successors: %bb.4(0x7c000000), %bb.5(0x04000000) + + $exec = S_OR_B64 $exec, %exec_save_if, implicit-def $scc + %loop_counter:sreg_32 = S_ADD_I32 %loop_counter, -1, implicit-def dead $scc + S_CMP_LG_U32 %loop_counter, 0, implicit-def $scc + S_CBRANCH_SCC0 %bb.5, implicit killed $scc + + bb.4: + successors: %bb.1 + + S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7 + S_NOP 0, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14, implicit %15 + S_NOP 0, implicit %16, implicit %17, implicit %18, implicit %19, implicit %20, implicit %21, implicit %22, implicit %23 + + S_BRANCH %bb.1 + + bb.5: + + S_NOP 0, implicit %32 + + S_ENDPGM 0 +... +--- +# bb.2's frequency is lesser than bb.4's therefore it is preferable to +# rematerialize registers in bb.2 instead of bb.4. +name: favor_lower_frequency +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true +body: | + ; CHECK-LABEL: name: favor_lower_frequency + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $vgpr0, $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %mem_addr:sgpr_64 = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: %loop_if_bound:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: %mem_data:sreg_64_xexec = S_LOAD_DWORDX2_IMM %mem_addr, 52, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4) + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_3:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_4:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_5:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_6:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_12:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_13:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_14:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_15:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_17:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_18:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: %exec_loop_mask:sreg_64 = V_CMP_GT_U32_e64 %mem_data.sub0, %loop_if_bound, implicit $exec + ; CHECK-NEXT: %loop_counter:sreg_32 = COPY %mem_data.sub1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %exec_save_if:sreg_64 = COPY $exec, implicit-def $exec + ; CHECK-NEXT: %exec_if:sreg_64 = S_AND_B64 %exec_save_if, %exec_loop_mask, implicit-def dead $scc + ; CHECK-NEXT: $exec = S_MOV_B64_term %exec_if + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_24:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_25:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_26:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_27:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_28:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_30:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_31:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_24]], implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]], implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.5(0x04000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $exec = S_OR_B64 $exec, %exec_save_if, implicit-def $scc + ; CHECK-NEXT: %loop_counter:sreg_32 = S_ADD_I32 %loop_counter, -1, implicit-def dead $scc + ; CHECK-NEXT: S_CMP_LG_U32 %loop_counter, 0, implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.5, implicit killed $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]], implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]] + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_7]], implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]], implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]], implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]] + ; CHECK-NEXT: S_BRANCH %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_23]] + ; CHECK-NEXT: S_ENDPGM 0 + bb.0: + liveins: $vgpr0, $sgpr0_sgpr1 + + %mem_addr:sgpr_64 = COPY $sgpr0_sgpr1 + %loop_if_bound:vgpr_32 = COPY $vgpr0 + %mem_data:sreg_64_xexec = S_LOAD_DWORDX2_IMM %mem_addr, 52, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4) + %exec_loop_mask:sreg_64 = V_CMP_GT_U32_e64 %mem_data.sub0, killed %loop_if_bound, implicit $exec + %loop_counter:sreg_32 = COPY %mem_data.sub1 + + %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode + %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode + %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode + %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode + %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode + %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode + %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode + %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode + %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode + %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode + %10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + %11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode + %12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode + %13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode + %14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode + %15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode + %16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode + %17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode + %18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode + %19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode + %20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode + %21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode + %22:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode + %23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode + %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode + %25:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode + %26:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode + %27:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode + %28:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode + %29:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode + %30:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode + %31:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode + %32:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode, implicit-def $m0 + + bb.1: + successors: %bb.2, %bb.3 + + %exec_save_if:sreg_64 = COPY $exec, implicit-def $exec + %exec_if:sreg_64 = S_AND_B64 %exec_save_if, %exec_loop_mask, implicit-def dead $scc + $exec = S_MOV_B64_term %exec_if + S_CBRANCH_EXECZ %bb.3, implicit $exec + S_BRANCH %bb.2 + + bb.2: + successors: %bb.3 + + S_NOP 0, implicit %24, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29, implicit %30, implicit %31 + + bb.3: + successors: %bb.4(0x7c000000), %bb.5(0x04000000) + + $exec = S_OR_B64 $exec, %exec_save_if, implicit-def $scc + %loop_counter:sreg_32 = S_ADD_I32 %loop_counter, -1, implicit-def dead $scc + S_CMP_LG_U32 %loop_counter, 0, implicit-def $scc + S_CBRANCH_SCC0 %bb.5, implicit killed $scc + + bb.4: + successors: %bb.1 + + S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7 + S_NOP 0, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14, implicit %15 + S_NOP 0, implicit %16, implicit %17, implicit %18, implicit %19, implicit %20, implicit %21, implicit %22, implicit %23 + + S_BRANCH %bb.1 + + bb.5: + + S_NOP 0, implicit %32 + + S_ENDPGM 0 +... +--- +# Rematerializing registers used in bb.4 is the only option. +name: remat_in_only_possible_region +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true +body: | + ; CHECK-LABEL: name: remat_in_only_possible_region + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $vgpr0, $sgpr0_sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %mem_addr:sgpr_64 = COPY $sgpr0_sgpr1 + ; CHECK-NEXT: %loop_if_bound:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: %mem_data:sreg_64_xexec = S_LOAD_DWORDX2_IMM %mem_addr, 52, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4) + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_3:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_4:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_5:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_6:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_12:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_13:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_14:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_15:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_17:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_18:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode, implicit-def $m0 + ; CHECK-NEXT: %exec_loop_mask:sreg_64 = V_CMP_GT_U32_e64 %mem_data.sub0, %loop_if_bound, implicit $exec + ; CHECK-NEXT: %loop_counter:sreg_32 = COPY %mem_data.sub1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %exec_save_if:sreg_64 = COPY $exec, implicit-def $exec + ; CHECK-NEXT: %exec_if:sreg_64 = S_AND_B64 %exec_save_if, %exec_loop_mask, implicit-def dead $scc + ; CHECK-NEXT: $exec = S_MOV_B64_term %exec_if + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]], implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.5(0x04000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $exec = S_OR_B64 $exec, %exec_save_if, implicit-def $scc + ; CHECK-NEXT: %loop_counter:sreg_32 = S_ADD_I32 %loop_counter, -1, implicit-def dead $scc + ; CHECK-NEXT: S_CMP_LG_U32 %loop_counter, 0, implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.5, implicit killed $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_24:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_25:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_26:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_27:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_28:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_30:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_31:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode + ; CHECK-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_24]], implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]], implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]] + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]], implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]] + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_7]], implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]], implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] + ; CHECK-NEXT: S_BRANCH %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_23]] + ; CHECK-NEXT: S_ENDPGM 0 + bb.0: + liveins: $vgpr0, $sgpr0_sgpr1 + + %mem_addr:sgpr_64 = COPY $sgpr0_sgpr1 + %loop_if_bound:vgpr_32 = COPY $vgpr0 + %mem_data:sreg_64_xexec = S_LOAD_DWORDX2_IMM %mem_addr, 52, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4) + %exec_loop_mask:sreg_64 = V_CMP_GT_U32_e64 %mem_data.sub0, killed %loop_if_bound, implicit $exec + %loop_counter:sreg_32 = COPY %mem_data.sub1 + + %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode + %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode + %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode + %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode + %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode + %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode + %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode + %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode + %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode + %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode + %10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + %11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode + %12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode + %13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode + %14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode + %15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode + %16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode + %17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode + %18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode + %19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode + %20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode + %21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode + %22:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode + %23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode + %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0 + %25:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode, implicit-def $m0 + %26:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode, implicit-def $m0 + %27:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode, implicit-def $m0 + %28:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode, implicit-def $m0 + %29:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode, implicit-def $m0 + %30:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode, implicit-def $m0 + %31:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode, implicit-def $m0 + %32:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode, implicit-def $m0 + + bb.1: + successors: %bb.2, %bb.3 + + %exec_save_if:sreg_64 = COPY $exec, implicit-def $exec + %exec_if:sreg_64 = S_AND_B64 %exec_save_if, %exec_loop_mask, implicit-def dead $scc + $exec = S_MOV_B64_term %exec_if + S_CBRANCH_EXECZ %bb.3, implicit $exec + S_BRANCH %bb.2 + + bb.2: + successors: %bb.3 + + S_NOP 0, implicit %24, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29, implicit %30, implicit %31 + + bb.3: + successors: %bb.4(0x7c000000), %bb.5(0x04000000) + + $exec = S_OR_B64 $exec, %exec_save_if, implicit-def $scc + %loop_counter:sreg_32 = S_ADD_I32 %loop_counter, -1, implicit-def dead $scc + S_CMP_LG_U32 %loop_counter, 0, implicit-def $scc + S_CBRANCH_SCC0 %bb.5, implicit killed $scc + + bb.4: + successors: %bb.1 + + S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7 + S_NOP 0, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14, implicit %15 + S_NOP 0, implicit %16, implicit %17, implicit %18, implicit %19, implicit %20, implicit %21, implicit %22, implicit %23 + + S_BRANCH %bb.1 + + bb.5: + + S_NOP 0, implicit %32 + + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir index 3b3ea3f37db80..1daa709ab6439 100644 --- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir +++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-attr.mir @@ -37,88 +37,89 @@ body: | ; GFX908: bb.0: ; GFX908-NEXT: successors: %bb.1(0x80000000) ; GFX908-NEXT: {{ $}} - ; GFX908-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 1 - ; GFX908-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 2 - ; GFX908-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 3 - ; GFX908-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sgpr_32 = S_MOV_B32 4 - ; GFX908-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sgpr_32 = S_MOV_B32 5 - ; GFX908-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sgpr_32 = S_MOV_B32 6 - ; GFX908-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sgpr_32 = S_MOV_B32 7 - ; GFX908-NEXT: [[S_MOV_B32_7:%[0-9]+]]:sgpr_32 = S_MOV_B32 8 - ; GFX908-NEXT: [[S_MOV_B32_8:%[0-9]+]]:sgpr_32 = S_MOV_B32 9 - ; GFX908-NEXT: [[S_MOV_B32_9:%[0-9]+]]:sgpr_32 = S_MOV_B32 10 - ; GFX908-NEXT: [[S_MOV_B32_10:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 - ; GFX908-NEXT: [[S_MOV_B32_11:%[0-9]+]]:sgpr_32 = S_MOV_B32 12 - ; GFX908-NEXT: [[S_MOV_B32_12:%[0-9]+]]:sgpr_32 = S_MOV_B32 13 - ; GFX908-NEXT: [[S_MOV_B32_13:%[0-9]+]]:sgpr_32 = S_MOV_B32 14 - ; GFX908-NEXT: [[S_MOV_B32_14:%[0-9]+]]:sgpr_32 = S_MOV_B32 15 - ; GFX908-NEXT: [[S_MOV_B32_15:%[0-9]+]]:sgpr_32 = S_MOV_B32 16 - ; GFX908-NEXT: [[S_MOV_B32_16:%[0-9]+]]:sgpr_32 = S_MOV_B32 17 - ; GFX908-NEXT: [[S_MOV_B32_17:%[0-9]+]]:sgpr_32 = S_MOV_B32 18 - ; GFX908-NEXT: [[S_MOV_B32_18:%[0-9]+]]:sgpr_32 = S_MOV_B32 19 - ; GFX908-NEXT: [[S_MOV_B32_19:%[0-9]+]]:sgpr_32 = S_MOV_B32 20 - ; GFX908-NEXT: [[S_MOV_B32_20:%[0-9]+]]:sgpr_32 = S_MOV_B32 21 - ; GFX908-NEXT: [[S_MOV_B32_21:%[0-9]+]]:sgpr_32 = S_MOV_B32 22 - ; GFX908-NEXT: [[S_MOV_B32_22:%[0-9]+]]:sgpr_32 = S_MOV_B32 23 - ; GFX908-NEXT: [[S_MOV_B32_23:%[0-9]+]]:sgpr_32 = S_MOV_B32 24 - ; GFX908-NEXT: [[S_MOV_B32_24:%[0-9]+]]:sgpr_32 = S_MOV_B32 25 - ; GFX908-NEXT: [[S_MOV_B32_25:%[0-9]+]]:sgpr_32 = S_MOV_B32 26 - ; GFX908-NEXT: [[S_MOV_B32_26:%[0-9]+]]:sgpr_32 = S_MOV_B32 27 - ; GFX908-NEXT: [[S_MOV_B32_27:%[0-9]+]]:sgpr_32 = S_MOV_B32 28 - ; GFX908-NEXT: [[S_MOV_B32_28:%[0-9]+]]:sgpr_32 = S_MOV_B32 29 - ; GFX908-NEXT: [[S_MOV_B32_29:%[0-9]+]]:sgpr_32 = S_MOV_B32 30 - ; GFX908-NEXT: [[S_MOV_B32_30:%[0-9]+]]:sgpr_32 = S_MOV_B32 31 - ; GFX908-NEXT: [[S_MOV_B32_31:%[0-9]+]]:sgpr_32 = S_MOV_B32 32 - ; GFX908-NEXT: [[S_MOV_B32_32:%[0-9]+]]:sgpr_32 = S_MOV_B32 33 - ; GFX908-NEXT: [[S_MOV_B32_33:%[0-9]+]]:sgpr_32 = S_MOV_B32 34 - ; GFX908-NEXT: [[S_MOV_B32_34:%[0-9]+]]:sgpr_32 = S_MOV_B32 35 - ; GFX908-NEXT: [[S_MOV_B32_35:%[0-9]+]]:sgpr_32 = S_MOV_B32 36 - ; GFX908-NEXT: [[S_MOV_B32_36:%[0-9]+]]:sgpr_32 = S_MOV_B32 37 - ; GFX908-NEXT: [[S_MOV_B32_37:%[0-9]+]]:sgpr_32 = S_MOV_B32 38 - ; GFX908-NEXT: [[S_MOV_B32_38:%[0-9]+]]:sgpr_32 = S_MOV_B32 39 - ; GFX908-NEXT: [[S_MOV_B32_39:%[0-9]+]]:sgpr_32 = S_MOV_B32 40 - ; GFX908-NEXT: [[S_MOV_B32_40:%[0-9]+]]:sgpr_32 = S_MOV_B32 41 - ; GFX908-NEXT: [[S_MOV_B32_41:%[0-9]+]]:sgpr_32 = S_MOV_B32 42 - ; GFX908-NEXT: [[S_MOV_B32_42:%[0-9]+]]:sgpr_32 = S_MOV_B32 43 - ; GFX908-NEXT: [[S_MOV_B32_43:%[0-9]+]]:sgpr_32 = S_MOV_B32 44 - ; GFX908-NEXT: [[S_MOV_B32_44:%[0-9]+]]:sgpr_32 = S_MOV_B32 45 - ; GFX908-NEXT: [[S_MOV_B32_45:%[0-9]+]]:sgpr_32 = S_MOV_B32 46 - ; GFX908-NEXT: [[S_MOV_B32_46:%[0-9]+]]:sgpr_32 = S_MOV_B32 47 - ; GFX908-NEXT: [[S_MOV_B32_47:%[0-9]+]]:sgpr_32 = S_MOV_B32 48 - ; GFX908-NEXT: [[S_MOV_B32_48:%[0-9]+]]:sgpr_32 = S_MOV_B32 49 - ; GFX908-NEXT: [[S_MOV_B32_49:%[0-9]+]]:sgpr_32 = S_MOV_B32 50 - ; GFX908-NEXT: [[S_MOV_B32_50:%[0-9]+]]:sgpr_32 = S_MOV_B32 51 - ; GFX908-NEXT: [[S_MOV_B32_51:%[0-9]+]]:sgpr_32 = S_MOV_B32 52 - ; GFX908-NEXT: [[S_MOV_B32_52:%[0-9]+]]:sgpr_32 = S_MOV_B32 53 - ; GFX908-NEXT: [[S_MOV_B32_53:%[0-9]+]]:sgpr_32 = S_MOV_B32 54 - ; GFX908-NEXT: [[S_MOV_B32_54:%[0-9]+]]:sgpr_32 = S_MOV_B32 55 - ; GFX908-NEXT: [[S_MOV_B32_55:%[0-9]+]]:sgpr_32 = S_MOV_B32 56 - ; GFX908-NEXT: [[S_MOV_B32_56:%[0-9]+]]:sgpr_32 = S_MOV_B32 57 - ; GFX908-NEXT: [[S_MOV_B32_57:%[0-9]+]]:sgpr_32 = S_MOV_B32 58 - ; GFX908-NEXT: [[S_MOV_B32_58:%[0-9]+]]:sgpr_32 = S_MOV_B32 59 - ; GFX908-NEXT: [[S_MOV_B32_59:%[0-9]+]]:sgpr_32 = S_MOV_B32 60 - ; GFX908-NEXT: [[S_MOV_B32_60:%[0-9]+]]:sgpr_32 = S_MOV_B32 61 - ; GFX908-NEXT: [[S_MOV_B32_61:%[0-9]+]]:sgpr_32 = S_MOV_B32 62 - ; GFX908-NEXT: [[S_MOV_B32_62:%[0-9]+]]:sgpr_32 = S_MOV_B32 63 - ; GFX908-NEXT: [[S_MOV_B32_63:%[0-9]+]]:sgpr_32 = S_MOV_B32 64 - ; GFX908-NEXT: [[S_MOV_B32_64:%[0-9]+]]:sgpr_32 = S_MOV_B32 65 - ; GFX908-NEXT: [[S_MOV_B32_65:%[0-9]+]]:sgpr_32 = S_MOV_B32 66 - ; GFX908-NEXT: [[S_MOV_B32_66:%[0-9]+]]:sgpr_32 = S_MOV_B32 67 - ; GFX908-NEXT: [[S_MOV_B32_67:%[0-9]+]]:sgpr_32 = S_MOV_B32 68 - ; GFX908-NEXT: [[S_MOV_B32_68:%[0-9]+]]:sgpr_32 = S_MOV_B32 69 - ; GFX908-NEXT: [[S_MOV_B32_69:%[0-9]+]]:sgpr_32 = S_MOV_B32 70 - ; GFX908-NEXT: [[S_MOV_B32_70:%[0-9]+]]:sgpr_32 = S_MOV_B32 71 - ; GFX908-NEXT: [[S_MOV_B32_71:%[0-9]+]]:sgpr_32 = S_MOV_B32 72 - ; GFX908-NEXT: [[S_MOV_B32_72:%[0-9]+]]:sgpr_32 = S_MOV_B32 73 - ; GFX908-NEXT: [[S_MOV_B32_73:%[0-9]+]]:sgpr_32 = S_MOV_B32 74 - ; GFX908-NEXT: [[S_MOV_B32_74:%[0-9]+]]:sgpr_32 = S_MOV_B32 75 - ; GFX908-NEXT: [[S_MOV_B32_75:%[0-9]+]]:sgpr_32 = S_MOV_B32 76 - ; GFX908-NEXT: [[S_MOV_B32_76:%[0-9]+]]:sgpr_32 = S_MOV_B32 77 - ; GFX908-NEXT: [[S_MOV_B32_77:%[0-9]+]]:sgpr_32 = S_MOV_B32 78 - ; GFX908-NEXT: [[S_MOV_B32_78:%[0-9]+]]:sgpr_32 = S_MOV_B32 79 + ; GFX908-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 6 + ; GFX908-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 7 + ; GFX908-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 8 + ; GFX908-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sgpr_32 = S_MOV_B32 9 + ; GFX908-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sgpr_32 = S_MOV_B32 10 + ; GFX908-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 + ; GFX908-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sgpr_32 = S_MOV_B32 12 + ; GFX908-NEXT: [[S_MOV_B32_7:%[0-9]+]]:sgpr_32 = S_MOV_B32 13 + ; GFX908-NEXT: [[S_MOV_B32_8:%[0-9]+]]:sgpr_32 = S_MOV_B32 14 + ; GFX908-NEXT: [[S_MOV_B32_9:%[0-9]+]]:sgpr_32 = S_MOV_B32 15 + ; GFX908-NEXT: [[S_MOV_B32_10:%[0-9]+]]:sgpr_32 = S_MOV_B32 16 + ; GFX908-NEXT: [[S_MOV_B32_11:%[0-9]+]]:sgpr_32 = S_MOV_B32 17 + ; GFX908-NEXT: [[S_MOV_B32_12:%[0-9]+]]:sgpr_32 = S_MOV_B32 18 + ; GFX908-NEXT: [[S_MOV_B32_13:%[0-9]+]]:sgpr_32 = S_MOV_B32 19 + ; GFX908-NEXT: [[S_MOV_B32_14:%[0-9]+]]:sgpr_32 = S_MOV_B32 20 + ; GFX908-NEXT: [[S_MOV_B32_15:%[0-9]+]]:sgpr_32 = S_MOV_B32 21 + ; GFX908-NEXT: [[S_MOV_B32_16:%[0-9]+]]:sgpr_32 = S_MOV_B32 22 + ; GFX908-NEXT: [[S_MOV_B32_17:%[0-9]+]]:sgpr_32 = S_MOV_B32 23 + ; GFX908-NEXT: [[S_MOV_B32_18:%[0-9]+]]:sgpr_32 = S_MOV_B32 24 + ; GFX908-NEXT: [[S_MOV_B32_19:%[0-9]+]]:sgpr_32 = S_MOV_B32 25 + ; GFX908-NEXT: [[S_MOV_B32_20:%[0-9]+]]:sgpr_32 = S_MOV_B32 26 + ; GFX908-NEXT: [[S_MOV_B32_21:%[0-9]+]]:sgpr_32 = S_MOV_B32 27 + ; GFX908-NEXT: [[S_MOV_B32_22:%[0-9]+]]:sgpr_32 = S_MOV_B32 28 + ; GFX908-NEXT: [[S_MOV_B32_23:%[0-9]+]]:sgpr_32 = S_MOV_B32 29 + ; GFX908-NEXT: [[S_MOV_B32_24:%[0-9]+]]:sgpr_32 = S_MOV_B32 30 + ; GFX908-NEXT: [[S_MOV_B32_25:%[0-9]+]]:sgpr_32 = S_MOV_B32 31 + ; GFX908-NEXT: [[S_MOV_B32_26:%[0-9]+]]:sgpr_32 = S_MOV_B32 32 + ; GFX908-NEXT: [[S_MOV_B32_27:%[0-9]+]]:sgpr_32 = S_MOV_B32 33 + ; GFX908-NEXT: [[S_MOV_B32_28:%[0-9]+]]:sgpr_32 = S_MOV_B32 34 + ; GFX908-NEXT: [[S_MOV_B32_29:%[0-9]+]]:sgpr_32 = S_MOV_B32 35 + ; GFX908-NEXT: [[S_MOV_B32_30:%[0-9]+]]:sgpr_32 = S_MOV_B32 36 + ; GFX908-NEXT: [[S_MOV_B32_31:%[0-9]+]]:sgpr_32 = S_MOV_B32 37 + ; GFX908-NEXT: [[S_MOV_B32_32:%[0-9]+]]:sgpr_32 = S_MOV_B32 38 + ; GFX908-NEXT: [[S_MOV_B32_33:%[0-9]+]]:sgpr_32 = S_MOV_B32 39 + ; GFX908-NEXT: [[S_MOV_B32_34:%[0-9]+]]:sgpr_32 = S_MOV_B32 40 + ; GFX908-NEXT: [[S_MOV_B32_35:%[0-9]+]]:sgpr_32 = S_MOV_B32 41 + ; GFX908-NEXT: [[S_MOV_B32_36:%[0-9]+]]:sgpr_32 = S_MOV_B32 42 + ; GFX908-NEXT: [[S_MOV_B32_37:%[0-9]+]]:sgpr_32 = S_MOV_B32 43 + ; GFX908-NEXT: [[S_MOV_B32_38:%[0-9]+]]:sgpr_32 = S_MOV_B32 44 + ; GFX908-NEXT: [[S_MOV_B32_39:%[0-9]+]]:sgpr_32 = S_MOV_B32 45 + ; GFX908-NEXT: [[S_MOV_B32_40:%[0-9]+]]:sgpr_32 = S_MOV_B32 46 + ; GFX908-NEXT: [[S_MOV_B32_41:%[0-9]+]]:sgpr_32 = S_MOV_B32 47 + ; GFX908-NEXT: [[S_MOV_B32_42:%[0-9]+]]:sgpr_32 = S_MOV_B32 48 + ; GFX908-NEXT: [[S_MOV_B32_43:%[0-9]+]]:sgpr_32 = S_MOV_B32 49 + ; GFX908-NEXT: [[S_MOV_B32_44:%[0-9]+]]:sgpr_32 = S_MOV_B32 50 + ; GFX908-NEXT: [[S_MOV_B32_45:%[0-9]+]]:sgpr_32 = S_MOV_B32 51 + ; GFX908-NEXT: [[S_MOV_B32_46:%[0-9]+]]:sgpr_32 = S_MOV_B32 52 + ; GFX908-NEXT: [[S_MOV_B32_47:%[0-9]+]]:sgpr_32 = S_MOV_B32 53 + ; GFX908-NEXT: [[S_MOV_B32_48:%[0-9]+]]:sgpr_32 = S_MOV_B32 54 + ; GFX908-NEXT: [[S_MOV_B32_49:%[0-9]+]]:sgpr_32 = S_MOV_B32 55 + ; GFX908-NEXT: [[S_MOV_B32_50:%[0-9]+]]:sgpr_32 = S_MOV_B32 56 + ; GFX908-NEXT: [[S_MOV_B32_51:%[0-9]+]]:sgpr_32 = S_MOV_B32 57 + ; GFX908-NEXT: [[S_MOV_B32_52:%[0-9]+]]:sgpr_32 = S_MOV_B32 58 + ; GFX908-NEXT: [[S_MOV_B32_53:%[0-9]+]]:sgpr_32 = S_MOV_B32 59 + ; GFX908-NEXT: [[S_MOV_B32_54:%[0-9]+]]:sgpr_32 = S_MOV_B32 60 + ; GFX908-NEXT: [[S_MOV_B32_55:%[0-9]+]]:sgpr_32 = S_MOV_B32 61 + ; GFX908-NEXT: [[S_MOV_B32_56:%[0-9]+]]:sgpr_32 = S_MOV_B32 62 + ; GFX908-NEXT: [[S_MOV_B32_57:%[0-9]+]]:sgpr_32 = S_MOV_B32 63 + ; GFX908-NEXT: [[S_MOV_B32_58:%[0-9]+]]:sgpr_32 = S_MOV_B32 64 + ; GFX908-NEXT: [[S_MOV_B32_59:%[0-9]+]]:sgpr_32 = S_MOV_B32 65 + ; GFX908-NEXT: [[S_MOV_B32_60:%[0-9]+]]:sgpr_32 = S_MOV_B32 66 + ; GFX908-NEXT: [[S_MOV_B32_61:%[0-9]+]]:sgpr_32 = S_MOV_B32 67 + ; GFX908-NEXT: [[S_MOV_B32_62:%[0-9]+]]:sgpr_32 = S_MOV_B32 68 + ; GFX908-NEXT: [[S_MOV_B32_63:%[0-9]+]]:sgpr_32 = S_MOV_B32 69 + ; GFX908-NEXT: [[S_MOV_B32_64:%[0-9]+]]:sgpr_32 = S_MOV_B32 70 + ; GFX908-NEXT: [[S_MOV_B32_65:%[0-9]+]]:sgpr_32 = S_MOV_B32 71 + ; GFX908-NEXT: [[S_MOV_B32_66:%[0-9]+]]:sgpr_32 = S_MOV_B32 72 + ; GFX908-NEXT: [[S_MOV_B32_67:%[0-9]+]]:sgpr_32 = S_MOV_B32 73 + ; GFX908-NEXT: [[S_MOV_B32_68:%[0-9]+]]:sgpr_32 = S_MOV_B32 74 + ; GFX908-NEXT: [[S_MOV_B32_69:%[0-9]+]]:sgpr_32 = S_MOV_B32 75 + ; GFX908-NEXT: [[S_MOV_B32_70:%[0-9]+]]:sgpr_32 = S_MOV_B32 76 + ; GFX908-NEXT: [[S_MOV_B32_71:%[0-9]+]]:sgpr_32 = S_MOV_B32 77 + ; GFX908-NEXT: [[S_MOV_B32_72:%[0-9]+]]:sgpr_32 = S_MOV_B32 78 + ; GFX908-NEXT: [[S_MOV_B32_73:%[0-9]+]]:sgpr_32 = S_MOV_B32 79 ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.1: - ; GFX908-NEXT: [[S_MOV_B32_79:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; GFX908-NEXT: [[S_MOV_B32_74:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; GFX908-NEXT: [[S_MOV_B32_75:%[0-9]+]]:sgpr_32 = S_MOV_B32 1 + ; GFX908-NEXT: [[S_MOV_B32_76:%[0-9]+]]:sgpr_32 = S_MOV_B32 2 + ; GFX908-NEXT: [[S_MOV_B32_77:%[0-9]+]]:sgpr_32 = S_MOV_B32 3 + ; GFX908-NEXT: [[S_MOV_B32_78:%[0-9]+]]:sgpr_32 = S_MOV_B32 4 + ; GFX908-NEXT: S_NOP 0, implicit [[S_MOV_B32_74]], implicit [[S_MOV_B32_75]], implicit [[S_MOV_B32_76]], implicit [[S_MOV_B32_77]], implicit [[S_MOV_B32_78]] + ; GFX908-NEXT: [[S_MOV_B32_79:%[0-9]+]]:sgpr_32 = S_MOV_B32 5 ; GFX908-NEXT: S_NOP 0, implicit [[S_MOV_B32_79]], implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]] ; GFX908-NEXT: S_NOP 0, implicit [[S_MOV_B32_4]], implicit [[S_MOV_B32_5]], implicit [[S_MOV_B32_6]], implicit [[S_MOV_B32_7]], implicit [[S_MOV_B32_8]] ; GFX908-NEXT: S_NOP 0, implicit [[S_MOV_B32_9]], implicit [[S_MOV_B32_10]], implicit [[S_MOV_B32_11]], implicit [[S_MOV_B32_12]], implicit [[S_MOV_B32_13]] @@ -134,95 +135,95 @@ body: | ; GFX908-NEXT: S_NOP 0, implicit [[S_MOV_B32_59]], implicit [[S_MOV_B32_60]], implicit [[S_MOV_B32_61]], implicit [[S_MOV_B32_62]], implicit [[S_MOV_B32_63]] ; GFX908-NEXT: S_NOP 0, implicit [[S_MOV_B32_64]], implicit [[S_MOV_B32_65]], implicit [[S_MOV_B32_66]], implicit [[S_MOV_B32_67]], implicit [[S_MOV_B32_68]] ; GFX908-NEXT: S_NOP 0, implicit [[S_MOV_B32_69]], implicit [[S_MOV_B32_70]], implicit [[S_MOV_B32_71]], implicit [[S_MOV_B32_72]], implicit [[S_MOV_B32_73]] - ; GFX908-NEXT: S_NOP 0, implicit [[S_MOV_B32_74]], implicit [[S_MOV_B32_75]], implicit [[S_MOV_B32_76]], implicit [[S_MOV_B32_77]], implicit [[S_MOV_B32_78]] ; GFX908-NEXT: S_ENDPGM 0 ; ; GFX90A-LABEL: name: small_num_sgprs_as_spill ; GFX90A: bb.0: ; GFX90A-NEXT: successors: %bb.1(0x80000000) ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 1 - ; GFX90A-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 2 - ; GFX90A-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 3 - ; GFX90A-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sgpr_32 = S_MOV_B32 4 - ; GFX90A-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sgpr_32 = S_MOV_B32 5 - ; GFX90A-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sgpr_32 = S_MOV_B32 6 - ; GFX90A-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sgpr_32 = S_MOV_B32 7 - ; GFX90A-NEXT: [[S_MOV_B32_7:%[0-9]+]]:sgpr_32 = S_MOV_B32 8 - ; GFX90A-NEXT: [[S_MOV_B32_8:%[0-9]+]]:sgpr_32 = S_MOV_B32 9 - ; GFX90A-NEXT: [[S_MOV_B32_9:%[0-9]+]]:sgpr_32 = S_MOV_B32 10 - ; GFX90A-NEXT: [[S_MOV_B32_10:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 - ; GFX90A-NEXT: [[S_MOV_B32_11:%[0-9]+]]:sgpr_32 = S_MOV_B32 12 - ; GFX90A-NEXT: [[S_MOV_B32_12:%[0-9]+]]:sgpr_32 = S_MOV_B32 13 - ; GFX90A-NEXT: [[S_MOV_B32_13:%[0-9]+]]:sgpr_32 = S_MOV_B32 14 - ; GFX90A-NEXT: [[S_MOV_B32_14:%[0-9]+]]:sgpr_32 = S_MOV_B32 15 - ; GFX90A-NEXT: [[S_MOV_B32_15:%[0-9]+]]:sgpr_32 = S_MOV_B32 16 - ; GFX90A-NEXT: [[S_MOV_B32_16:%[0-9]+]]:sgpr_32 = S_MOV_B32 17 - ; GFX90A-NEXT: [[S_MOV_B32_17:%[0-9]+]]:sgpr_32 = S_MOV_B32 18 - ; GFX90A-NEXT: [[S_MOV_B32_18:%[0-9]+]]:sgpr_32 = S_MOV_B32 19 - ; GFX90A-NEXT: [[S_MOV_B32_19:%[0-9]+]]:sgpr_32 = S_MOV_B32 20 - ; GFX90A-NEXT: [[S_MOV_B32_20:%[0-9]+]]:sgpr_32 = S_MOV_B32 21 - ; GFX90A-NEXT: [[S_MOV_B32_21:%[0-9]+]]:sgpr_32 = S_MOV_B32 22 - ; GFX90A-NEXT: [[S_MOV_B32_22:%[0-9]+]]:sgpr_32 = S_MOV_B32 23 - ; GFX90A-NEXT: [[S_MOV_B32_23:%[0-9]+]]:sgpr_32 = S_MOV_B32 24 - ; GFX90A-NEXT: [[S_MOV_B32_24:%[0-9]+]]:sgpr_32 = S_MOV_B32 25 - ; GFX90A-NEXT: [[S_MOV_B32_25:%[0-9]+]]:sgpr_32 = S_MOV_B32 26 - ; GFX90A-NEXT: [[S_MOV_B32_26:%[0-9]+]]:sgpr_32 = S_MOV_B32 27 - ; GFX90A-NEXT: [[S_MOV_B32_27:%[0-9]+]]:sgpr_32 = S_MOV_B32 28 - ; GFX90A-NEXT: [[S_MOV_B32_28:%[0-9]+]]:sgpr_32 = S_MOV_B32 29 - ; GFX90A-NEXT: [[S_MOV_B32_29:%[0-9]+]]:sgpr_32 = S_MOV_B32 30 - ; GFX90A-NEXT: [[S_MOV_B32_30:%[0-9]+]]:sgpr_32 = S_MOV_B32 31 - ; GFX90A-NEXT: [[S_MOV_B32_31:%[0-9]+]]:sgpr_32 = S_MOV_B32 32 - ; GFX90A-NEXT: [[S_MOV_B32_32:%[0-9]+]]:sgpr_32 = S_MOV_B32 33 - ; GFX90A-NEXT: [[S_MOV_B32_33:%[0-9]+]]:sgpr_32 = S_MOV_B32 34 - ; GFX90A-NEXT: [[S_MOV_B32_34:%[0-9]+]]:sgpr_32 = S_MOV_B32 35 - ; GFX90A-NEXT: [[S_MOV_B32_35:%[0-9]+]]:sgpr_32 = S_MOV_B32 36 - ; GFX90A-NEXT: [[S_MOV_B32_36:%[0-9]+]]:sgpr_32 = S_MOV_B32 37 - ; GFX90A-NEXT: [[S_MOV_B32_37:%[0-9]+]]:sgpr_32 = S_MOV_B32 38 - ; GFX90A-NEXT: [[S_MOV_B32_38:%[0-9]+]]:sgpr_32 = S_MOV_B32 39 - ; GFX90A-NEXT: [[S_MOV_B32_39:%[0-9]+]]:sgpr_32 = S_MOV_B32 40 - ; GFX90A-NEXT: [[S_MOV_B32_40:%[0-9]+]]:sgpr_32 = S_MOV_B32 41 - ; GFX90A-NEXT: [[S_MOV_B32_41:%[0-9]+]]:sgpr_32 = S_MOV_B32 42 - ; GFX90A-NEXT: [[S_MOV_B32_42:%[0-9]+]]:sgpr_32 = S_MOV_B32 43 - ; GFX90A-NEXT: [[S_MOV_B32_43:%[0-9]+]]:sgpr_32 = S_MOV_B32 44 - ; GFX90A-NEXT: [[S_MOV_B32_44:%[0-9]+]]:sgpr_32 = S_MOV_B32 45 - ; GFX90A-NEXT: [[S_MOV_B32_45:%[0-9]+]]:sgpr_32 = S_MOV_B32 46 - ; GFX90A-NEXT: [[S_MOV_B32_46:%[0-9]+]]:sgpr_32 = S_MOV_B32 47 - ; GFX90A-NEXT: [[S_MOV_B32_47:%[0-9]+]]:sgpr_32 = S_MOV_B32 48 - ; GFX90A-NEXT: [[S_MOV_B32_48:%[0-9]+]]:sgpr_32 = S_MOV_B32 49 - ; GFX90A-NEXT: [[S_MOV_B32_49:%[0-9]+]]:sgpr_32 = S_MOV_B32 50 - ; GFX90A-NEXT: [[S_MOV_B32_50:%[0-9]+]]:sgpr_32 = S_MOV_B32 51 - ; GFX90A-NEXT: [[S_MOV_B32_51:%[0-9]+]]:sgpr_32 = S_MOV_B32 52 - ; GFX90A-NEXT: [[S_MOV_B32_52:%[0-9]+]]:sgpr_32 = S_MOV_B32 53 - ; GFX90A-NEXT: [[S_MOV_B32_53:%[0-9]+]]:sgpr_32 = S_MOV_B32 54 - ; GFX90A-NEXT: [[S_MOV_B32_54:%[0-9]+]]:sgpr_32 = S_MOV_B32 55 - ; GFX90A-NEXT: [[S_MOV_B32_55:%[0-9]+]]:sgpr_32 = S_MOV_B32 56 - ; GFX90A-NEXT: [[S_MOV_B32_56:%[0-9]+]]:sgpr_32 = S_MOV_B32 57 - ; GFX90A-NEXT: [[S_MOV_B32_57:%[0-9]+]]:sgpr_32 = S_MOV_B32 58 - ; GFX90A-NEXT: [[S_MOV_B32_58:%[0-9]+]]:sgpr_32 = S_MOV_B32 59 - ; GFX90A-NEXT: [[S_MOV_B32_59:%[0-9]+]]:sgpr_32 = S_MOV_B32 60 - ; GFX90A-NEXT: [[S_MOV_B32_60:%[0-9]+]]:sgpr_32 = S_MOV_B32 61 - ; GFX90A-NEXT: [[S_MOV_B32_61:%[0-9]+]]:sgpr_32 = S_MOV_B32 62 - ; GFX90A-NEXT: [[S_MOV_B32_62:%[0-9]+]]:sgpr_32 = S_MOV_B32 63 - ; GFX90A-NEXT: [[S_MOV_B32_63:%[0-9]+]]:sgpr_32 = S_MOV_B32 64 - ; GFX90A-NEXT: [[S_MOV_B32_64:%[0-9]+]]:sgpr_32 = S_MOV_B32 65 - ; GFX90A-NEXT: [[S_MOV_B32_65:%[0-9]+]]:sgpr_32 = S_MOV_B32 66 - ; GFX90A-NEXT: [[S_MOV_B32_66:%[0-9]+]]:sgpr_32 = S_MOV_B32 67 - ; GFX90A-NEXT: [[S_MOV_B32_67:%[0-9]+]]:sgpr_32 = S_MOV_B32 68 - ; GFX90A-NEXT: [[S_MOV_B32_68:%[0-9]+]]:sgpr_32 = S_MOV_B32 69 - ; GFX90A-NEXT: [[S_MOV_B32_69:%[0-9]+]]:sgpr_32 = S_MOV_B32 70 - ; GFX90A-NEXT: [[S_MOV_B32_70:%[0-9]+]]:sgpr_32 = S_MOV_B32 71 - ; GFX90A-NEXT: [[S_MOV_B32_71:%[0-9]+]]:sgpr_32 = S_MOV_B32 72 - ; GFX90A-NEXT: [[S_MOV_B32_72:%[0-9]+]]:sgpr_32 = S_MOV_B32 73 - ; GFX90A-NEXT: [[S_MOV_B32_73:%[0-9]+]]:sgpr_32 = S_MOV_B32 74 - ; GFX90A-NEXT: [[S_MOV_B32_74:%[0-9]+]]:sgpr_32 = S_MOV_B32 75 - ; GFX90A-NEXT: [[S_MOV_B32_75:%[0-9]+]]:sgpr_32 = S_MOV_B32 76 - ; GFX90A-NEXT: [[S_MOV_B32_76:%[0-9]+]]:sgpr_32 = S_MOV_B32 77 - ; GFX90A-NEXT: [[S_MOV_B32_77:%[0-9]+]]:sgpr_32 = S_MOV_B32 78 - ; GFX90A-NEXT: [[S_MOV_B32_78:%[0-9]+]]:sgpr_32 = S_MOV_B32 79 + ; GFX90A-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 6 + ; GFX90A-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 7 + ; GFX90A-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 8 + ; GFX90A-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sgpr_32 = S_MOV_B32 9 + ; GFX90A-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sgpr_32 = S_MOV_B32 10 + ; GFX90A-NEXT: [[S_MOV_B32_5:%[0-9]+]]:sgpr_32 = S_MOV_B32 11 + ; GFX90A-NEXT: [[S_MOV_B32_6:%[0-9]+]]:sgpr_32 = S_MOV_B32 12 + ; GFX90A-NEXT: [[S_MOV_B32_7:%[0-9]+]]:sgpr_32 = S_MOV_B32 13 + ; GFX90A-NEXT: [[S_MOV_B32_8:%[0-9]+]]:sgpr_32 = S_MOV_B32 14 + ; GFX90A-NEXT: [[S_MOV_B32_9:%[0-9]+]]:sgpr_32 = S_MOV_B32 15 + ; GFX90A-NEXT: [[S_MOV_B32_10:%[0-9]+]]:sgpr_32 = S_MOV_B32 16 + ; GFX90A-NEXT: [[S_MOV_B32_11:%[0-9]+]]:sgpr_32 = S_MOV_B32 17 + ; GFX90A-NEXT: [[S_MOV_B32_12:%[0-9]+]]:sgpr_32 = S_MOV_B32 18 + ; GFX90A-NEXT: [[S_MOV_B32_13:%[0-9]+]]:sgpr_32 = S_MOV_B32 19 + ; GFX90A-NEXT: [[S_MOV_B32_14:%[0-9]+]]:sgpr_32 = S_MOV_B32 20 + ; GFX90A-NEXT: [[S_MOV_B32_15:%[0-9]+]]:sgpr_32 = S_MOV_B32 21 + ; GFX90A-NEXT: [[S_MOV_B32_16:%[0-9]+]]:sgpr_32 = S_MOV_B32 22 + ; GFX90A-NEXT: [[S_MOV_B32_17:%[0-9]+]]:sgpr_32 = S_MOV_B32 23 + ; GFX90A-NEXT: [[S_MOV_B32_18:%[0-9]+]]:sgpr_32 = S_MOV_B32 24 + ; GFX90A-NEXT: [[S_MOV_B32_19:%[0-9]+]]:sgpr_32 = S_MOV_B32 25 + ; GFX90A-NEXT: [[S_MOV_B32_20:%[0-9]+]]:sgpr_32 = S_MOV_B32 26 + ; GFX90A-NEXT: [[S_MOV_B32_21:%[0-9]+]]:sgpr_32 = S_MOV_B32 27 + ; GFX90A-NEXT: [[S_MOV_B32_22:%[0-9]+]]:sgpr_32 = S_MOV_B32 28 + ; GFX90A-NEXT: [[S_MOV_B32_23:%[0-9]+]]:sgpr_32 = S_MOV_B32 29 + ; GFX90A-NEXT: [[S_MOV_B32_24:%[0-9]+]]:sgpr_32 = S_MOV_B32 30 + ; GFX90A-NEXT: [[S_MOV_B32_25:%[0-9]+]]:sgpr_32 = S_MOV_B32 31 + ; GFX90A-NEXT: [[S_MOV_B32_26:%[0-9]+]]:sgpr_32 = S_MOV_B32 32 + ; GFX90A-NEXT: [[S_MOV_B32_27:%[0-9]+]]:sgpr_32 = S_MOV_B32 33 + ; GFX90A-NEXT: [[S_MOV_B32_28:%[0-9]+]]:sgpr_32 = S_MOV_B32 34 + ; GFX90A-NEXT: [[S_MOV_B32_29:%[0-9]+]]:sgpr_32 = S_MOV_B32 35 + ; GFX90A-NEXT: [[S_MOV_B32_30:%[0-9]+]]:sgpr_32 = S_MOV_B32 36 + ; GFX90A-NEXT: [[S_MOV_B32_31:%[0-9]+]]:sgpr_32 = S_MOV_B32 37 + ; GFX90A-NEXT: [[S_MOV_B32_32:%[0-9]+]]:sgpr_32 = S_MOV_B32 38 + ; GFX90A-NEXT: [[S_MOV_B32_33:%[0-9]+]]:sgpr_32 = S_MOV_B32 39 + ; GFX90A-NEXT: [[S_MOV_B32_34:%[0-9]+]]:sgpr_32 = S_MOV_B32 40 + ; GFX90A-NEXT: [[S_MOV_B32_35:%[0-9]+]]:sgpr_32 = S_MOV_B32 41 + ; GFX90A-NEXT: [[S_MOV_B32_36:%[0-9]+]]:sgpr_32 = S_MOV_B32 42 + ; GFX90A-NEXT: [[S_MOV_B32_37:%[0-9]+]]:sgpr_32 = S_MOV_B32 43 + ; GFX90A-NEXT: [[S_MOV_B32_38:%[0-9]+]]:sgpr_32 = S_MOV_B32 44 + ; GFX90A-NEXT: [[S_MOV_B32_39:%[0-9]+]]:sgpr_32 = S_MOV_B32 45 + ; GFX90A-NEXT: [[S_MOV_B32_40:%[0-9]+]]:sgpr_32 = S_MOV_B32 46 + ; GFX90A-NEXT: [[S_MOV_B32_41:%[0-9]+]]:sgpr_32 = S_MOV_B32 47 + ; GFX90A-NEXT: [[S_MOV_B32_42:%[0-9]+]]:sgpr_32 = S_MOV_B32 48 + ; GFX90A-NEXT: [[S_MOV_B32_43:%[0-9]+]]:sgpr_32 = S_MOV_B32 49 + ; GFX90A-NEXT: [[S_MOV_B32_44:%[0-9]+]]:sgpr_32 = S_MOV_B32 50 + ; GFX90A-NEXT: [[S_MOV_B32_45:%[0-9]+]]:sgpr_32 = S_MOV_B32 51 + ; GFX90A-NEXT: [[S_MOV_B32_46:%[0-9]+]]:sgpr_32 = S_MOV_B32 52 + ; GFX90A-NEXT: [[S_MOV_B32_47:%[0-9]+]]:sgpr_32 = S_MOV_B32 53 + ; GFX90A-NEXT: [[S_MOV_B32_48:%[0-9]+]]:sgpr_32 = S_MOV_B32 54 + ; GFX90A-NEXT: [[S_MOV_B32_49:%[0-9]+]]:sgpr_32 = S_MOV_B32 55 + ; GFX90A-NEXT: [[S_MOV_B32_50:%[0-9]+]]:sgpr_32 = S_MOV_B32 56 + ; GFX90A-NEXT: [[S_MOV_B32_51:%[0-9]+]]:sgpr_32 = S_MOV_B32 57 + ; GFX90A-NEXT: [[S_MOV_B32_52:%[0-9]+]]:sgpr_32 = S_MOV_B32 58 + ; GFX90A-NEXT: [[S_MOV_B32_53:%[0-9]+]]:sgpr_32 = S_MOV_B32 59 + ; GFX90A-NEXT: [[S_MOV_B32_54:%[0-9]+]]:sgpr_32 = S_MOV_B32 60 + ; GFX90A-NEXT: [[S_MOV_B32_55:%[0-9]+]]:sgpr_32 = S_MOV_B32 61 + ; GFX90A-NEXT: [[S_MOV_B32_56:%[0-9]+]]:sgpr_32 = S_MOV_B32 62 + ; GFX90A-NEXT: [[S_MOV_B32_57:%[0-9]+]]:sgpr_32 = S_MOV_B32 63 + ; GFX90A-NEXT: [[S_MOV_B32_58:%[0-9]+]]:sgpr_32 = S_MOV_B32 64 + ; GFX90A-NEXT: [[S_MOV_B32_59:%[0-9]+]]:sgpr_32 = S_MOV_B32 65 + ; GFX90A-NEXT: [[S_MOV_B32_60:%[0-9]+]]:sgpr_32 = S_MOV_B32 66 + ; GFX90A-NEXT: [[S_MOV_B32_61:%[0-9]+]]:sgpr_32 = S_MOV_B32 67 + ; GFX90A-NEXT: [[S_MOV_B32_62:%[0-9]+]]:sgpr_32 = S_MOV_B32 68 + ; GFX90A-NEXT: [[S_MOV_B32_63:%[0-9]+]]:sgpr_32 = S_MOV_B32 69 + ; GFX90A-NEXT: [[S_MOV_B32_64:%[0-9]+]]:sgpr_32 = S_MOV_B32 70 + ; GFX90A-NEXT: [[S_MOV_B32_65:%[0-9]+]]:sgpr_32 = S_MOV_B32 71 + ; GFX90A-NEXT: [[S_MOV_B32_66:%[0-9]+]]:sgpr_32 = S_MOV_B32 72 + ; GFX90A-NEXT: [[S_MOV_B32_67:%[0-9]+]]:sgpr_32 = S_MOV_B32 73 + ; GFX90A-NEXT: [[S_MOV_B32_68:%[0-9]+]]:sgpr_32 = S_MOV_B32 74 + ; GFX90A-NEXT: [[S_MOV_B32_69:%[0-9]+]]:sgpr_32 = S_MOV_B32 75 + ; GFX90A-NEXT: [[S_MOV_B32_70:%[0-9]+]]:sgpr_32 = S_MOV_B32 76 + ; GFX90A-NEXT: [[S_MOV_B32_71:%[0-9]+]]:sgpr_32 = S_MOV_B32 77 + ; GFX90A-NEXT: [[S_MOV_B32_72:%[0-9]+]]:sgpr_32 = S_MOV_B32 78 + ; GFX90A-NEXT: [[S_MOV_B32_73:%[0-9]+]]:sgpr_32 = S_MOV_B32 79 ; GFX90A-NEXT: {{ $}} ; GFX90A-NEXT: bb.1: - ; GFX90A-NEXT: [[S_MOV_B32_79:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; GFX90A-NEXT: [[S_MOV_B32_74:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; GFX90A-NEXT: [[S_MOV_B32_75:%[0-9]+]]:sgpr_32 = S_MOV_B32 1 + ; GFX90A-NEXT: [[S_MOV_B32_76:%[0-9]+]]:sgpr_32 = S_MOV_B32 2 + ; GFX90A-NEXT: [[S_MOV_B32_77:%[0-9]+]]:sgpr_32 = S_MOV_B32 3 + ; GFX90A-NEXT: [[S_MOV_B32_78:%[0-9]+]]:sgpr_32 = S_MOV_B32 4 + ; GFX90A-NEXT: S_NOP 0, implicit [[S_MOV_B32_74]], implicit [[S_MOV_B32_75]], implicit [[S_MOV_B32_76]], implicit [[S_MOV_B32_77]], implicit [[S_MOV_B32_78]] + ; GFX90A-NEXT: [[S_MOV_B32_79:%[0-9]+]]:sgpr_32 = S_MOV_B32 5 ; GFX90A-NEXT: S_NOP 0, implicit [[S_MOV_B32_79]], implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]] ; GFX90A-NEXT: S_NOP 0, implicit [[S_MOV_B32_4]], implicit [[S_MOV_B32_5]], implicit [[S_MOV_B32_6]], implicit [[S_MOV_B32_7]], implicit [[S_MOV_B32_8]] ; GFX90A-NEXT: S_NOP 0, implicit [[S_MOV_B32_9]], implicit [[S_MOV_B32_10]], implicit [[S_MOV_B32_11]], implicit [[S_MOV_B32_12]], implicit [[S_MOV_B32_13]] @@ -238,7 +239,6 @@ body: | ; GFX90A-NEXT: S_NOP 0, implicit [[S_MOV_B32_59]], implicit [[S_MOV_B32_60]], implicit [[S_MOV_B32_61]], implicit [[S_MOV_B32_62]], implicit [[S_MOV_B32_63]] ; GFX90A-NEXT: S_NOP 0, implicit [[S_MOV_B32_64]], implicit [[S_MOV_B32_65]], implicit [[S_MOV_B32_66]], implicit [[S_MOV_B32_67]], implicit [[S_MOV_B32_68]] ; GFX90A-NEXT: S_NOP 0, implicit [[S_MOV_B32_69]], implicit [[S_MOV_B32_70]], implicit [[S_MOV_B32_71]], implicit [[S_MOV_B32_72]], implicit [[S_MOV_B32_73]] - ; GFX90A-NEXT: S_NOP 0, implicit [[S_MOV_B32_74]], implicit [[S_MOV_B32_75]], implicit [[S_MOV_B32_76]], implicit [[S_MOV_B32_77]], implicit [[S_MOV_B32_78]] ; GFX90A-NEXT: S_ENDPGM 0 bb.0: successors: %bb.1 @@ -796,9 +796,6 @@ body: | ; GFX908-NEXT: [[DEF26:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[DEF27:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[DEF28:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX908-NEXT: [[DEF29:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX908-NEXT: [[DEF30:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX908-NEXT: [[DEF31:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_3:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0 @@ -839,15 +836,18 @@ body: | ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] ; GFX908-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]] + ; GFX908-NEXT: [[DEF29:%[0-9]+]]:agpr_32 = IMPLICIT_DEF + ; GFX908-NEXT: [[DEF30:%[0-9]+]]:agpr_32 = IMPLICIT_DEF + ; GFX908-NEXT: [[DEF31:%[0-9]+]]:agpr_32 = IMPLICIT_DEF + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_29]], implicit [[V_CVT_I32_F64_e32_30]], implicit [[DEF29]], implicit [[DEF30]], implicit [[DEF31]] ; GFX908-NEXT: [[DEF32:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_29]], implicit [[V_CVT_I32_F64_e32_30]], implicit [[DEF32]], implicit [[DEF]], implicit [[DEF1]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF2]], implicit [[DEF3]], implicit [[DEF4]], implicit [[DEF5]], implicit [[DEF6]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF7]], implicit [[DEF8]], implicit [[DEF9]], implicit [[DEF10]], implicit [[DEF11]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF12]], implicit [[DEF13]], implicit [[DEF14]], implicit [[DEF15]], implicit [[DEF16]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF17]], implicit [[DEF18]], implicit [[DEF19]], implicit [[DEF20]], implicit [[DEF21]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF22]], implicit [[DEF23]], implicit [[DEF24]], implicit [[DEF25]], implicit [[DEF26]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF27]], implicit [[DEF28]], implicit [[DEF29]], implicit [[DEF30]], implicit [[V_CVT_I32_F64_e32_31]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF31]] + ; GFX908-NEXT: S_NOP 0, implicit [[DEF32]], implicit [[DEF]], implicit [[DEF1]], implicit [[DEF2]], implicit [[DEF3]] + ; GFX908-NEXT: S_NOP 0, implicit [[DEF4]], implicit [[DEF5]], implicit [[DEF6]], implicit [[DEF7]], implicit [[DEF8]] + ; GFX908-NEXT: S_NOP 0, implicit [[DEF9]], implicit [[DEF10]], implicit [[DEF11]], implicit [[DEF12]], implicit [[DEF13]] + ; GFX908-NEXT: S_NOP 0, implicit [[DEF14]], implicit [[DEF15]], implicit [[DEF16]], implicit [[DEF17]], implicit [[DEF18]] + ; GFX908-NEXT: S_NOP 0, implicit [[DEF19]], implicit [[DEF20]], implicit [[DEF21]], implicit [[DEF22]], implicit [[DEF23]] + ; GFX908-NEXT: S_NOP 0, implicit [[DEF24]], implicit [[DEF25]], implicit [[DEF26]], implicit [[DEF27]], implicit [[V_CVT_I32_F64_e32_31]] + ; GFX908-NEXT: S_NOP 0, implicit [[DEF28]] ; GFX908-NEXT: S_ENDPGM 0 ; ; GFX90A-LABEL: name: reduce_arch_and_acc_vgrp_spill @@ -910,9 +910,6 @@ body: | ; GFX90A-NEXT: [[DEF26:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[DEF27:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[DEF28:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX90A-NEXT: [[DEF29:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX90A-NEXT: [[DEF30:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX90A-NEXT: [[DEF31:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[V_CVT_I32_F64_e32_27:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode ; GFX90A-NEXT: [[V_CVT_I32_F64_e32_28:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode ; GFX90A-NEXT: [[V_CVT_I32_F64_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode @@ -927,15 +924,18 @@ body: | ; GFX90A-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] ; GFX90A-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode ; GFX90A-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]] + ; GFX90A-NEXT: [[DEF29:%[0-9]+]]:agpr_32 = IMPLICIT_DEF + ; GFX90A-NEXT: [[DEF30:%[0-9]+]]:agpr_32 = IMPLICIT_DEF + ; GFX90A-NEXT: [[DEF31:%[0-9]+]]:agpr_32 = IMPLICIT_DEF + ; GFX90A-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_29]], implicit [[V_CVT_I32_F64_e32_30]], implicit [[DEF29]], implicit [[DEF30]], implicit [[DEF31]] ; GFX90A-NEXT: [[DEF32:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX90A-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_29]], implicit [[V_CVT_I32_F64_e32_30]], implicit [[DEF32]], implicit [[DEF]], implicit [[DEF1]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF2]], implicit [[DEF3]], implicit [[DEF4]], implicit [[DEF5]], implicit [[DEF6]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF7]], implicit [[DEF8]], implicit [[DEF9]], implicit [[DEF10]], implicit [[DEF11]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF12]], implicit [[DEF13]], implicit [[DEF14]], implicit [[DEF15]], implicit [[DEF16]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF17]], implicit [[DEF18]], implicit [[DEF19]], implicit [[DEF20]], implicit [[DEF21]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF22]], implicit [[DEF23]], implicit [[DEF24]], implicit [[DEF25]], implicit [[DEF26]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF27]], implicit [[DEF28]], implicit [[DEF29]], implicit [[DEF30]], implicit [[V_CVT_I32_F64_e32_31]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF31]] + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF32]], implicit [[DEF]], implicit [[DEF1]], implicit [[DEF2]], implicit [[DEF3]] + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF4]], implicit [[DEF5]], implicit [[DEF6]], implicit [[DEF7]], implicit [[DEF8]] + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF9]], implicit [[DEF10]], implicit [[DEF11]], implicit [[DEF12]], implicit [[DEF13]] + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF14]], implicit [[DEF15]], implicit [[DEF16]], implicit [[DEF17]], implicit [[DEF18]] + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF19]], implicit [[DEF20]], implicit [[DEF21]], implicit [[DEF22]], implicit [[DEF23]] + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF24]], implicit [[DEF25]], implicit [[DEF26]], implicit [[DEF27]], implicit [[V_CVT_I32_F64_e32_31]] + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF28]] ; GFX90A-NEXT: S_ENDPGM 0 bb.0: successors: %bb.1 @@ -2174,6 +2174,8 @@ body: | ; GFX908-NEXT: [[DEF243:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[DEF244:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[DEF245:%[0-9]+]]:agpr_32 = IMPLICIT_DEF + ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: bb.1: ; GFX908-NEXT: [[DEF246:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[DEF247:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[DEF248:%[0-9]+]]:agpr_32 = IMPLICIT_DEF @@ -2184,8 +2186,7 @@ body: | ; GFX908-NEXT: [[DEF253:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[DEF254:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: [[DEF255:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX908-NEXT: {{ $}} - ; GFX908-NEXT: bb.1: + ; GFX908-NEXT: S_NOP 0, implicit [[DEF246]], implicit [[DEF247]], implicit [[DEF248]], implicit [[DEF249]], implicit [[DEF250]], implicit [[DEF251]], implicit [[DEF252]], implicit [[DEF253]], implicit [[DEF254]], implicit [[DEF255]] ; GFX908-NEXT: [[DEF256:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX908-NEXT: S_NOP 0, implicit [[DEF256]], implicit [[DEF]], implicit [[DEF1]], implicit [[DEF2]], implicit [[DEF3]], implicit [[DEF4]], implicit [[DEF5]], implicit [[DEF6]], implicit [[DEF7]], implicit [[DEF8]] ; GFX908-NEXT: S_NOP 0, implicit [[DEF9]], implicit [[DEF10]], implicit [[DEF11]], implicit [[DEF12]], implicit [[DEF13]], implicit [[DEF14]], implicit [[DEF15]], implicit [[DEF16]], implicit [[DEF17]], implicit [[DEF18]] @@ -2211,8 +2212,7 @@ body: | ; GFX908-NEXT: S_NOP 0, implicit [[DEF209]], implicit [[DEF210]], implicit [[DEF211]], implicit [[DEF212]], implicit [[DEF213]], implicit [[DEF214]], implicit [[DEF215]], implicit [[DEF216]], implicit [[DEF217]], implicit [[DEF218]] ; GFX908-NEXT: S_NOP 0, implicit [[DEF219]], implicit [[DEF220]], implicit [[DEF221]], implicit [[DEF222]], implicit [[DEF223]], implicit [[DEF224]], implicit [[DEF225]], implicit [[DEF226]], implicit [[DEF227]], implicit [[DEF228]] ; GFX908-NEXT: S_NOP 0, implicit [[DEF229]], implicit [[DEF230]], implicit [[DEF231]], implicit [[DEF232]], implicit [[DEF233]], implicit [[DEF234]], implicit [[DEF235]], implicit [[DEF236]], implicit [[DEF237]], implicit [[DEF238]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF239]], implicit [[DEF240]], implicit [[DEF241]], implicit [[DEF242]], implicit [[DEF243]], implicit [[DEF244]], implicit [[DEF245]], implicit [[DEF246]], implicit [[DEF247]], implicit [[DEF248]] - ; GFX908-NEXT: S_NOP 0, implicit [[DEF249]], implicit [[DEF250]], implicit [[DEF251]], implicit [[DEF252]], implicit [[DEF253]], implicit [[DEF254]], implicit [[DEF255]], implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]] + ; GFX908-NEXT: S_NOP 0, implicit [[DEF239]], implicit [[DEF240]], implicit [[DEF241]], implicit [[DEF242]], implicit [[DEF243]], implicit [[DEF244]], implicit [[DEF245]], implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]] ; GFX908-NEXT: S_ENDPGM 0 ; ; GFX90A-LABEL: name: reduce_spill_agpr_above_addressable_limit @@ -2465,6 +2465,10 @@ body: | ; GFX90A-NEXT: [[DEF243:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[DEF244:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[DEF245:%[0-9]+]]:agpr_32 = IMPLICIT_DEF + ; GFX90A-NEXT: [[V_CVT_I32_F64_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 257, implicit $exec, implicit $mode + ; GFX90A-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 258, implicit $exec, implicit $mode + ; GFX90A-NEXT: {{ $}} + ; GFX90A-NEXT: bb.1: ; GFX90A-NEXT: [[DEF246:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[DEF247:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[DEF248:%[0-9]+]]:agpr_32 = IMPLICIT_DEF @@ -2475,10 +2479,7 @@ body: | ; GFX90A-NEXT: [[DEF253:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[DEF254:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: [[DEF255:%[0-9]+]]:agpr_32 = IMPLICIT_DEF - ; GFX90A-NEXT: [[V_CVT_I32_F64_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 257, implicit $exec, implicit $mode - ; GFX90A-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 258, implicit $exec, implicit $mode - ; GFX90A-NEXT: {{ $}} - ; GFX90A-NEXT: bb.1: + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF246]], implicit [[DEF247]], implicit [[DEF248]], implicit [[DEF249]], implicit [[DEF250]], implicit [[DEF251]], implicit [[DEF252]], implicit [[DEF253]], implicit [[DEF254]], implicit [[DEF255]] ; GFX90A-NEXT: [[DEF256:%[0-9]+]]:agpr_32 = IMPLICIT_DEF ; GFX90A-NEXT: S_NOP 0, implicit [[DEF256]], implicit [[DEF]], implicit [[DEF1]], implicit [[DEF2]], implicit [[DEF3]], implicit [[DEF4]], implicit [[DEF5]], implicit [[DEF6]], implicit [[DEF7]], implicit [[DEF8]] ; GFX90A-NEXT: S_NOP 0, implicit [[DEF9]], implicit [[DEF10]], implicit [[DEF11]], implicit [[DEF12]], implicit [[DEF13]], implicit [[DEF14]], implicit [[DEF15]], implicit [[DEF16]], implicit [[DEF17]], implicit [[DEF18]] @@ -2504,8 +2505,7 @@ body: | ; GFX90A-NEXT: S_NOP 0, implicit [[DEF209]], implicit [[DEF210]], implicit [[DEF211]], implicit [[DEF212]], implicit [[DEF213]], implicit [[DEF214]], implicit [[DEF215]], implicit [[DEF216]], implicit [[DEF217]], implicit [[DEF218]] ; GFX90A-NEXT: S_NOP 0, implicit [[DEF219]], implicit [[DEF220]], implicit [[DEF221]], implicit [[DEF222]], implicit [[DEF223]], implicit [[DEF224]], implicit [[DEF225]], implicit [[DEF226]], implicit [[DEF227]], implicit [[DEF228]] ; GFX90A-NEXT: S_NOP 0, implicit [[DEF229]], implicit [[DEF230]], implicit [[DEF231]], implicit [[DEF232]], implicit [[DEF233]], implicit [[DEF234]], implicit [[DEF235]], implicit [[DEF236]], implicit [[DEF237]], implicit [[DEF238]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF239]], implicit [[DEF240]], implicit [[DEF241]], implicit [[DEF242]], implicit [[DEF243]], implicit [[DEF244]], implicit [[DEF245]], implicit [[DEF246]], implicit [[DEF247]], implicit [[DEF248]] - ; GFX90A-NEXT: S_NOP 0, implicit [[DEF249]], implicit [[DEF250]], implicit [[DEF251]], implicit [[DEF252]], implicit [[DEF253]], implicit [[DEF254]], implicit [[DEF255]], implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]] + ; GFX90A-NEXT: S_NOP 0, implicit [[DEF239]], implicit [[DEF240]], implicit [[DEF241]], implicit [[DEF242]], implicit [[DEF243]], implicit [[DEF244]], implicit [[DEF245]], implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]] ; GFX90A-NEXT: S_ENDPGM 0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir index 050ff23cd1f27..b2be61b975892 100644 --- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir +++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir @@ -23,8 +23,8 @@ body: | ; DEBUG: Machine code for function sink_and_inc_idx_when_skipping_small_region_1: IsSSA, NoPHIs, TracksLiveness ; DEBUG: [PreRARemat] Retrying function scheduling with new min. occupancy of 10 from rematerializing (original was 9, target was 10) ; DEBUG-NEXT: ********** MI Scheduling ********** - ; DEBUG-NEXT: sink_and_inc_idx_when_skipping_small_region_1:%bb.2 - ; DEBUG-NEXT: From: %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0 + ; DEBUG-NEXT: sink_and_inc_idx_when_skipping_small_region_1:%bb.1 + ; DEBUG-NEXT: From: %23:vgpr_32 = nofpexcept DBG_VALUE 23, implicit $noreg, implicit $noreg ; DEBUG-NEXT: To: End RegionInstrs: 2 bb.0: successors: %bb.1 @@ -95,9 +95,9 @@ body: | ; DEBUG: Machine code for function sink_and_inc_idx_when_skipping_small_regions_2: IsSSA, NoPHIs, TracksLiveness ; DEBUG: [PreRARemat] Retrying function scheduling with new min. occupancy of 10 from rematerializing (original was 9, target was 10) ; DEBUG-NEXT: ********** MI Scheduling ********** - ; DEBUG-NEXT: sink_and_inc_idx_when_skipping_small_regions_2:%bb.2 - ; DEBUG-NEXT: From: %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0 - ; DEBUG-NEXT: To: End RegionInstrs: 4 + ; DEBUG-NEXT: sink_and_inc_idx_when_skipping_small_regions_2:%bb.1 + ; DEBUG-NEXT: From: %23:vgpr_32 = nofpexcept DBG_VALUE 23, implicit $noreg, implicit $noreg + ; DEBUG-NEXT: To: End RegionInstrs: 2 bb.0: successors: %bb.1 diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir index 1ef95deee29cc..58ae0820dc184 100644 --- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir +++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir @@ -9419,7 +9419,7 @@ body: | ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_23]] ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.2: - ; GFX908-NEXT: DBG_VALUE %23, 0, 0 + ; GFX908-NEXT: DBG_VALUE %23:vgpr_32, 0, 0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_24:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_24]] ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]] @@ -9471,7 +9471,7 @@ body: | ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_23]] ; GFX908-GCNTRACKERS-NEXT: {{ $}} ; GFX908-GCNTRACKERS-NEXT: bb.2: - ; GFX908-GCNTRACKERS-NEXT: DBG_VALUE %23, 0, 0 + ; GFX908-GCNTRACKERS-NEXT: DBG_VALUE %23:vgpr_32, 0, 0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_24:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_24]] ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]] @@ -10269,13 +10269,13 @@ body: | ; GFX908-NEXT: [[V_CVT_I32_F64_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0 - ; GFX908-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0 - ; GFX908-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode ; GFX908-NEXT: [[V_CVT_I32_F64_e32_12:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_13:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_14:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_15:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0 - ; GFX908-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode ; GFX908-NEXT: [[V_CVT_I32_F64_e32_17:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_18:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0 @@ -10291,7 +10291,9 @@ body: | ; GFX908-NEXT: [[V_CVT_I32_F64_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_30:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: [[V_CVT_I32_F64_e32_31:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode, implicit-def $m0 - ; GFX908-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_33:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 33, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_34:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 34, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.1: ; GFX908-NEXT: successors: %bb.2(0x80000000) @@ -10302,16 +10304,16 @@ body: | ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]] - ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]], implicit [[V_CVT_I32_F64_e32_32]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]], implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_33]], implicit [[V_CVT_I32_F64_e32_34]] ; GFX908-NEXT: {{ $}} ; GFX908-NEXT: bb.2: ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]] ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]], implicit [[V_CVT_I32_F64_e32_7]], implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]] - ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] - ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]] - ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]], implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_33]], implicit [[V_CVT_I32_F64_e32_34]] ; GFX908-NEXT: S_ENDPGM 0 ; ; GFX908-GCNTRACKERS-LABEL: name: test_rollback_remat_defregion_above_target @@ -10328,13 +10330,13 @@ body: | ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0 - ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0 - ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_12:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_13:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_14:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_15:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0 - ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_17:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_18:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0 @@ -10350,7 +10352,9 @@ body: | ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_30:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_31:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode, implicit-def $m0 - ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_33:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 33, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_34:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 34, implicit $exec, implicit $mode, implicit-def $m0 ; GFX908-GCNTRACKERS-NEXT: {{ $}} ; GFX908-GCNTRACKERS-NEXT: bb.1: ; GFX908-GCNTRACKERS-NEXT: successors: %bb.2(0x80000000) @@ -10361,16 +10365,16 @@ body: | ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]] - ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]], implicit [[V_CVT_I32_F64_e32_32]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]], implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_33]], implicit [[V_CVT_I32_F64_e32_34]] ; GFX908-GCNTRACKERS-NEXT: {{ $}} ; GFX908-GCNTRACKERS-NEXT: bb.2: ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]] ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]], implicit [[V_CVT_I32_F64_e32_7]], implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]] - ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] - ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]] - ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]], implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_33]], implicit [[V_CVT_I32_F64_e32_34]] ; GFX908-GCNTRACKERS-NEXT: S_ENDPGM 0 bb.0: successors: %bb.1 @@ -10385,13 +10389,13 @@ body: | %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0 %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0 %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0 - %10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0 - %11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0 + %10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode + %11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode %12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0 %13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0 %14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0 %15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0 - %16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0 + %16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode %17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0 %18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0 %19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0 @@ -10407,28 +10411,30 @@ body: | %29:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode, implicit-def $m0 %30:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode, implicit-def $m0 %31:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode, implicit-def $m0 - %32:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode + %32:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode, implicit-def $m0 + %33:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 33, implicit $exec, implicit $mode, implicit-def $m0 + %34:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 34, implicit $exec, implicit $mode, implicit-def $m0 bb.1: successors: %bb.2 - S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, + S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4 S_NOP 0, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9 S_NOP 0, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14 S_NOP 0, implicit %15, implicit %16, implicit %17, implicit %18, implicit %19 S_NOP 0, implicit %20, implicit %21, implicit %22, implicit %23, implicit %24 S_NOP 0, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29 - S_NOP 0, implicit %30, implicit %31, implicit %32 + S_NOP 0, implicit %30, implicit %31, implicit %32, implicit %33, implicit %34 bb.2: - S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, + S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4 S_NOP 0, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9 - S_NOP 0, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14 - S_NOP 0, implicit %15, implicit %16, implicit %17, implicit %18, implicit %19 + S_NOP 0, implicit %12, implicit %13, implicit %14 + S_NOP 0, implicit %15, implicit %17, implicit %18, implicit %19 S_NOP 0, implicit %20, implicit %21, implicit %22, implicit %23, implicit %24 S_NOP 0, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29 - S_NOP 0, implicit %30, implicit %31 + S_NOP 0, implicit %30, implicit %31, implicit %32, implicit %33, implicit %34 S_ENDPGM 0 ... @@ -10627,12 +10633,12 @@ body: | S_ENDPGM 0 ... --- -name: test_rollback_remats_emptydefregion +name: test_rollback_remats_emptydefregion_block tracksRegLiveness: true machineFunctionInfo: isEntryFunction: true body: | - ; GFX908-LABEL: name: test_rollback_remats_emptydefregion + ; GFX908-LABEL: name: test_rollback_remats_emptydefregion_block ; GFX908: bb.0: ; GFX908-NEXT: successors: %bb.1(0x80000000) ; GFX908-NEXT: {{ $}} @@ -10696,7 +10702,7 @@ body: | ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]] ; GFX908-NEXT: S_ENDPGM 0 ; - ; GFX908-GCNTRACKERS-LABEL: name: test_rollback_remats_emptydefregion + ; GFX908-GCNTRACKERS-LABEL: name: test_rollback_remats_emptydefregion_block ; GFX908-GCNTRACKERS: bb.0: ; GFX908-GCNTRACKERS-NEXT: successors: %bb.1(0x80000000) ; GFX908-GCNTRACKERS-NEXT: {{ $}} @@ -10825,6 +10831,207 @@ body: | S_ENDPGM 0 ... --- +name: test_rollback_remats_emptydefregion_barrier +tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true +body: | + ; GFX908-LABEL: name: test_rollback_remats_emptydefregion_barrier + ; GFX908: bb.0: + ; GFX908-NEXT: successors: %bb.1(0x80000000) + ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_3:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_4:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_5:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_6:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_12:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_13:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_14:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_15:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_17:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_18:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_24:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_25:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_26:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_27:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_28:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_30:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_31:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: bb.1: + ; GFX908-NEXT: successors: %bb.2(0x80000000) + ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode + ; GFX908-NEXT: [[V_CVT_I32_F64_e32_33:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 33, implicit $exec, implicit $mode + ; GFX908-NEXT: SCHED_BARRIER 0 + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]] + ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: bb.2: + ; GFX908-NEXT: successors: %bb.3(0x80000000) + ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]], implicit [[V_CVT_I32_F64_e32_7]], implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]], implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_33]] + ; GFX908-NEXT: {{ $}} + ; GFX908-NEXT: bb.3: + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]], implicit [[V_CVT_I32_F64_e32_7]], implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]] + ; GFX908-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]] + ; GFX908-NEXT: S_ENDPGM 0 + ; + ; GFX908-GCNTRACKERS-LABEL: name: test_rollback_remats_emptydefregion_barrier + ; GFX908-GCNTRACKERS: bb.0: + ; GFX908-GCNTRACKERS-NEXT: successors: %bb.1(0x80000000) + ; GFX908-GCNTRACKERS-NEXT: {{ $}} + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_2:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_3:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_4:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_5:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_6:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_7:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_8:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_9:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_10:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_11:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_12:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_13:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_14:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_15:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_16:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_17:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_18:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_19:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_20:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_21:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_22:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_23:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_24:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_25:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_26:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_27:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_28:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_29:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_30:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_31:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode, implicit-def $m0 + ; GFX908-GCNTRACKERS-NEXT: {{ $}} + ; GFX908-GCNTRACKERS-NEXT: bb.1: + ; GFX908-GCNTRACKERS-NEXT: successors: %bb.2(0x80000000) + ; GFX908-GCNTRACKERS-NEXT: {{ $}} + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_32:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode + ; GFX908-GCNTRACKERS-NEXT: [[V_CVT_I32_F64_e32_33:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 33, implicit $exec, implicit $mode + ; GFX908-GCNTRACKERS-NEXT: SCHED_BARRIER 0 + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]] + ; GFX908-GCNTRACKERS-NEXT: {{ $}} + ; GFX908-GCNTRACKERS-NEXT: bb.2: + ; GFX908-GCNTRACKERS-NEXT: successors: %bb.3(0x80000000) + ; GFX908-GCNTRACKERS-NEXT: {{ $}} + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]], implicit [[V_CVT_I32_F64_e32_7]], implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]], implicit [[V_CVT_I32_F64_e32_32]], implicit [[V_CVT_I32_F64_e32_33]] + ; GFX908-GCNTRACKERS-NEXT: {{ $}} + ; GFX908-GCNTRACKERS-NEXT: bb.3: + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_]], implicit [[V_CVT_I32_F64_e32_1]], implicit [[V_CVT_I32_F64_e32_2]], implicit [[V_CVT_I32_F64_e32_3]], implicit [[V_CVT_I32_F64_e32_4]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_5]], implicit [[V_CVT_I32_F64_e32_6]], implicit [[V_CVT_I32_F64_e32_7]], implicit [[V_CVT_I32_F64_e32_8]], implicit [[V_CVT_I32_F64_e32_9]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_10]], implicit [[V_CVT_I32_F64_e32_11]], implicit [[V_CVT_I32_F64_e32_12]], implicit [[V_CVT_I32_F64_e32_13]], implicit [[V_CVT_I32_F64_e32_14]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_15]], implicit [[V_CVT_I32_F64_e32_16]], implicit [[V_CVT_I32_F64_e32_17]], implicit [[V_CVT_I32_F64_e32_18]], implicit [[V_CVT_I32_F64_e32_19]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_20]], implicit [[V_CVT_I32_F64_e32_21]], implicit [[V_CVT_I32_F64_e32_22]], implicit [[V_CVT_I32_F64_e32_23]], implicit [[V_CVT_I32_F64_e32_24]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_25]], implicit [[V_CVT_I32_F64_e32_26]], implicit [[V_CVT_I32_F64_e32_27]], implicit [[V_CVT_I32_F64_e32_28]], implicit [[V_CVT_I32_F64_e32_29]] + ; GFX908-GCNTRACKERS-NEXT: S_NOP 0, implicit [[V_CVT_I32_F64_e32_30]], implicit [[V_CVT_I32_F64_e32_31]] + ; GFX908-GCNTRACKERS-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1 + + %0:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 0, implicit $exec, implicit $mode, implicit-def $m0 + %1:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 1, implicit $exec, implicit $mode, implicit-def $m0 + %2:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 2, implicit $exec, implicit $mode, implicit-def $m0 + %3:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 3, implicit $exec, implicit $mode, implicit-def $m0 + %4:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 4, implicit $exec, implicit $mode, implicit-def $m0 + %5:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 5, implicit $exec, implicit $mode, implicit-def $m0 + %6:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 6, implicit $exec, implicit $mode, implicit-def $m0 + %7:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 7, implicit $exec, implicit $mode, implicit-def $m0 + %8:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 8, implicit $exec, implicit $mode, implicit-def $m0 + %9:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 9, implicit $exec, implicit $mode, implicit-def $m0 + %10:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 10, implicit $exec, implicit $mode, implicit-def $m0 + %11:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 11, implicit $exec, implicit $mode, implicit-def $m0 + %12:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 12, implicit $exec, implicit $mode, implicit-def $m0 + %13:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 13, implicit $exec, implicit $mode, implicit-def $m0 + %14:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 14, implicit $exec, implicit $mode, implicit-def $m0 + %15:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 15, implicit $exec, implicit $mode, implicit-def $m0 + %16:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 16, implicit $exec, implicit $mode, implicit-def $m0 + %17:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 17, implicit $exec, implicit $mode, implicit-def $m0 + %18:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 18, implicit $exec, implicit $mode, implicit-def $m0 + %19:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 19, implicit $exec, implicit $mode, implicit-def $m0 + %20:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 20, implicit $exec, implicit $mode, implicit-def $m0 + %21:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 21, implicit $exec, implicit $mode, implicit-def $m0 + %22:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 22, implicit $exec, implicit $mode, implicit-def $m0 + %23:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 23, implicit $exec, implicit $mode, implicit-def $m0 + %24:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 24, implicit $exec, implicit $mode, implicit-def $m0 + %25:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 25, implicit $exec, implicit $mode, implicit-def $m0 + %26:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 26, implicit $exec, implicit $mode, implicit-def $m0 + %27:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 27, implicit $exec, implicit $mode, implicit-def $m0 + %28:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 28, implicit $exec, implicit $mode, implicit-def $m0 + %29:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 29, implicit $exec, implicit $mode, implicit-def $m0 + %30:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 30, implicit $exec, implicit $mode, implicit-def $m0 + %31:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 31, implicit $exec, implicit $mode, implicit-def $m0 + + bb.1: + successors: %bb.2 + + %32:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 32, implicit $exec, implicit $mode + %33:vgpr_32 = nofpexcept V_CVT_I32_F64_e32 33, implicit $exec, implicit $mode + SCHED_BARRIER 0 + S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4 + + bb.2: + successors: %bb.3 + + S_NOP 0, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9 + S_NOP 0, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14 + S_NOP 0, implicit %15, implicit %16, implicit %17, implicit %18, implicit %19 + S_NOP 0, implicit %20, implicit %21, implicit %22, implicit %23, implicit %24 + S_NOP 0, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29 + S_NOP 0, implicit %30, implicit %31, implicit %32, implicit %33 + + bb.3: + + S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, + S_NOP 0, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9 + S_NOP 0, implicit %10, implicit %11, implicit %12, implicit %13, implicit %14 + S_NOP 0, implicit %15, implicit %16, implicit %17, implicit %18, implicit %19 + S_NOP 0, implicit %20, implicit %21, implicit %22, implicit %23, implicit %24 + S_NOP 0, implicit %25, implicit %26, implicit %27, implicit %28, implicit %29 + S_NOP 0, implicit %30, implicit %31 + + S_ENDPGM 0 +... +--- name: test_occ_8_physreg_use tracksRegLiveness: true machineFunctionInfo: diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll index 83625a59ed69f..42eab0324ec49 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll @@ -389,10 +389,9 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_bf16lo_f32_denormals_fmulfadd(bfloat % ; GFX1250: ; %bb.0: ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_mul_f32 v0, v0, v1 -; GFX1250-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v2, 1.0, v0 op_sel_hi:[1,1,0] ; GFX1250-NEXT: s_set_pc_i64 s[30:31] %src0.ext = fpext bfloat %src0 to float %src1.ext = fpext bfloat %src1 to float @@ -407,9 +406,8 @@ define float @v_mad_mix_f32_bf16lo_bf16lo_f32_denormals_fmulfadd(bfloat %src0, b ; GFX1250: ; %bb.0: ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX1250-NEXT: s_set_pc_i64 s[30:31] %src0.ext = fpext bfloat %src0 to float @@ -617,6 +615,776 @@ entry: ret void } +define float @v_mad_mix_f32_bf16lo_add_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16hi_add_bf16hi_int(i32 %src0, i32 %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16hi_add_bf16hi_int: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.hi = lshr i32 %src0, 16 + %src1.hi = lshr i32 %src1, 16 + %src0.i16 = trunc i32 %src0.hi to i16 + %src1.i16 = trunc i32 %src1.hi to i16 + %src0.fp16 = bitcast i16 %src0.i16 to bfloat + %src1.fp16 = bitcast i16 %src1.i16 to bfloat + %src0.ext = fpext bfloat %src0.fp16 to float + %src1.ext = fpext bfloat %src1.fp16 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16hi_add_bf16hi_elt(<2 x bfloat> %src0, <2 x bfloat> %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16hi_add_bf16hi_elt: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.hi = extractelement <2 x bfloat> %src0, i32 1 + %src1.hi = extractelement <2 x bfloat> %src1, i32 1 + %src0.ext = fpext bfloat %src0.hi to float + %src1.ext = fpext bfloat %src1.hi to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define <2 x float> @v_mad_mix_v2f32_cvt_add(<2 x bfloat> %src0, <2 x bfloat> %src1) { +; GFX1250-LABEL: v_mad_mix_v2f32_cvt_add: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 +; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v0 :: v_dual_lshlrev_b32 v4, 16, v1 +; GFX1250-NEXT: v_and_b32_e32 v5, 0xffff0000, v1 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_pk_add_f32 v[0:1], v[2:3], v[4:5] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext <2 x bfloat> %src0 to <2 x float> + %src1.ext = fpext <2 x bfloat> %src1 to <2 x float> + %result = fadd <2 x float> %src0.ext, %src1.ext + ret <2 x float> %result +} + +define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x bfloat> %src0, <2 x bfloat> %src1) { +; GFX1250-LABEL: v_mad_mix_v2f32_shuffle_cvt_add: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_dual_lshlrev_b32 v3, 16, v0 :: v_dual_lshlrev_b32 v4, 16, v1 +; GFX1250-NEXT: v_and_b32_e32 v2, 0xffff0000, v0 +; GFX1250-NEXT: v_and_b32_e32 v5, 0xffff0000, v1 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_pk_add_f32 v[0:1], v[2:3], v[4:5] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.shuf = shufflevector <2 x bfloat> %src0, <2 x bfloat> poison, <2 x i32> + %src1.shuf = shufflevector <2 x bfloat> %src1, <2 x bfloat> poison, <2 x i32> + %src0.ext = fpext <2 x bfloat> %src0.shuf to <2 x float> + %src1.ext = fpext <2 x bfloat> %src1.shuf to <2 x float> + %result = fadd <2 x float> %src0.ext, %src1.ext + ret <2 x float> %result +} + +define float @v_mad_mix_f32_negbf16lo_add_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_negbf16lo_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, -1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %src0.ext.neg = fneg float %src0.ext + %result = fadd float %src0.ext.neg, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absbf16lo_add_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_absbf16lo_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %result = fadd float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_negabsbf16lo_add_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_negabsbf16lo_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src0.ext.neg.abs = fneg float %src0.ext.abs + %result = fadd float %src0.ext.neg.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_add_f32(bfloat %src0, float %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_f32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %result = fadd float %src0.ext, %src1 + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_add_negf32(bfloat %src0, float %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_negf32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel_hi:[0,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.neg = fneg float %src1 + %result = fadd float %src0.ext, %src1.neg + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_add_absf32(bfloat %src0, float %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_absf32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, |v1| op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.abs = call float @llvm.fabs.f32(float %src1) + %result = fadd float %src0.ext, %src1.abs + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_add_negabsf32(bfloat %src0, float %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_add_negabsf32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v1|, -1.0, v0 op_sel_hi:[0,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.abs = call float @llvm.fabs.f32(float %src1) + %src1.neg.abs = fneg float %src1.abs + %result = fadd float %src0.ext, %src1.neg.abs + ret float %result +} + +define float @no_mix_simple_cvt_add(float %src0, float %src1) { +; GFX1250-LABEL: no_mix_simple_cvt_add: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %result = fadd float %src0, %src1 + ret float %result +} + +define float @no_mix_simple_fabs_cvt_add(float %src0, float %src1) { +; GFX1250-LABEL: no_mix_simple_fabs_cvt_add: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.fabs = call float @llvm.fabs.f32(float %src0) + %result = fadd float %src0.fabs, %src1 + ret float %result +} + +define float @v_mad_mix_clamp_f32_bf16hi_add_bf16hi_elt(<2 x bfloat> %src0, <2 x bfloat> %src1) { +; GFX1250-LABEL: v_mad_mix_clamp_f32_bf16hi_add_bf16hi_elt: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] clamp +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.hi = extractelement <2 x bfloat> %src0, i32 1 + %src1.hi = extractelement <2 x bfloat> %src1, i32 1 + %src0.ext = fpext bfloat %src0.hi to float + %src1.ext = fpext bfloat %src1.hi to float + %result = fadd float %src0.ext, %src1.ext + %max = call float @llvm.maxnum.f32(float %result, float 0.0) + %clamp = call float @llvm.minnum.f32(float %max, float 1.0) + ret float %clamp +} + +define float @v_mad_mix_f32_negprecvtbf16lo_add_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_negprecvtbf16lo_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, -1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0 + %src0.neg = fneg bfloat %src0 + %src0.ext = fpext bfloat %src0.neg to float + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absprecvtbf16lo_add_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_absprecvtbf16lo_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0 + %src0.fabs = call bfloat @llvm.fabs.bf16(bfloat %src0) + %src0.ext = fpext bfloat %src0.fabs to float + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_negabsprecvtbf16lo_add_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_negabsprecvtbf16lo_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0 + %src0.fabs = call bfloat @llvm.fabs.bf16(bfloat %src0) + %src0.neg.abs = fneg bfloat %src0.fabs + %src0.ext = fpext bfloat %src0.neg.abs to float + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_precvtnegbf16hi_abs_add_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_precvtnegbf16hi_abs_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-NEXT: v_xor_b32_e32 v0, 0x8000, v0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1 + %src0.neg = fneg bfloat %src0 + %src0.ext = fpext bfloat %src0.neg to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_precvtabsbf16hi_add_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_precvtabsbf16hi_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1 + %src0.abs = call bfloat @llvm.fabs.bf16(bfloat %src0) + %src0.ext = fpext bfloat %src0.abs to float + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfneg_bf16hi_add_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %fneg = fneg <2 x bfloat> %src0.arg.bc + %src0 = extractelement <2 x bfloat> %fneg, i32 1 + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfabs_bf16hi_add_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc) + %src0 = extractelement <2 x bfloat> %fabs, i32 1 + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfabsfneg_bf16hi_add_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_add_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc) + %fneg.fabs = fneg <2 x bfloat> %fabs + %src0 = extractelement <2 x bfloat> %fneg.fabs, i32 1 + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16hi_mul_bf16hi_int(i32 %src0, i32 %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16hi_mul_bf16hi_int: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.hi = lshr i32 %src0, 16 + %src1.hi = lshr i32 %src1, 16 + %src0.i16 = trunc i32 %src0.hi to i16 + %src1.i16 = trunc i32 %src1.hi to i16 + %src0.fp16 = bitcast i16 %src0.i16 to bfloat + %src1.fp16 = bitcast i16 %src1.i16 to bfloat + %src0.ext = fpext bfloat %src0.fp16 to float + %src1.ext = fpext bfloat %src1.fp16 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16hi_mul_bf16hi_elt(<2 x bfloat> %src0, <2 x bfloat> %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16hi_mul_bf16hi_elt: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.hi = extractelement <2 x bfloat> %src0, i32 1 + %src1.hi = extractelement <2 x bfloat> %src1, i32 1 + %src0.ext = fpext bfloat %src0.hi to float + %src1.ext = fpext bfloat %src1.hi to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define <2 x float> @v_mad_mix_v2f32_cvt_mul(<2 x bfloat> %src0, <2 x bfloat> %src1) { +; GFX1250-LABEL: v_mad_mix_v2f32_cvt_mul: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_and_b32_e32 v3, 0xffff0000, v0 +; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v0 :: v_dual_lshlrev_b32 v4, 16, v1 +; GFX1250-NEXT: v_and_b32_e32 v5, 0xffff0000, v1 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_pk_mul_f32 v[0:1], v[2:3], v[4:5] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext <2 x bfloat> %src0 to <2 x float> + %src1.ext = fpext <2 x bfloat> %src1 to <2 x float> + %result = fmul <2 x float> %src0.ext, %src1.ext + ret <2 x float> %result +} + +define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_mul(<2 x bfloat> %src0, <2 x bfloat> %src1) { +; GFX1250-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_dual_lshlrev_b32 v3, 16, v0 :: v_dual_lshlrev_b32 v4, 16, v1 +; GFX1250-NEXT: v_and_b32_e32 v2, 0xffff0000, v0 +; GFX1250-NEXT: v_and_b32_e32 v5, 0xffff0000, v1 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-NEXT: v_pk_mul_f32 v[0:1], v[2:3], v[4:5] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.shuf = shufflevector <2 x bfloat> %src0, <2 x bfloat> poison, <2 x i32> + %src1.shuf = shufflevector <2 x bfloat> %src1, <2 x bfloat> poison, <2 x i32> + %src0.ext = fpext <2 x bfloat> %src0.shuf to <2 x float> + %src1.ext = fpext <2 x bfloat> %src1.shuf to <2 x float> + %result = fmul <2 x float> %src0.ext, %src1.ext + ret <2 x float> %result +} + +define float @v_mad_mix_f32_negbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_negbf16lo_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %src0.ext.neg = fneg float %src0.ext + %result = fmul float %src0.ext.neg, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_absbf16lo_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %result = fmul float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_negabsbf16lo_mul_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_negabsbf16lo_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src0.ext.neg.abs = fneg float %src0.ext.abs + %result = fmul float %src0.ext.neg.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_mul_f32(bfloat %src0, float %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_f32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel_hi:[1,0,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %result = fmul float %src0.ext, %src1 + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_mul_negf32(bfloat %src0, float %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_negf32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.neg = fneg float %src1 + %result = fmul float %src0.ext, %src1.neg + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_mul_absf32(bfloat %src0, float %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_absf32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.abs = call float @llvm.fabs.f32(float %src1) + %result = fmul float %src0.ext, %src1.abs + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_mul_negabsf32(bfloat %src0, float %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_mul_negabsf32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.abs = call float @llvm.fabs.f32(float %src1) + %src1.neg.abs = fneg float %src1.abs + %result = fmul float %src0.ext, %src1.neg.abs + ret float %result +} + +define float @no_mix_simple_cvt_mul(float %src0, float %src1) { +; GFX1250-LABEL: no_mix_simple_cvt_mul: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %result = fmul float %src0, %src1 + ret float %result +} + +define float @no_mix_simple_fabs_cvt_mul(float %src0, float %src1) { +; GFX1250-LABEL: no_mix_simple_fabs_cvt_mul: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.fabs = call float @llvm.fabs.f32(float %src0) + %result = fmul float %src0.fabs, %src1 + ret float %result +} + +define float @v_mad_mix_clamp_f32_bf16hi_mul_bf16hi_elt(<2 x bfloat> %src0, <2 x bfloat> %src1) { +; GFX1250-LABEL: v_mad_mix_clamp_f32_bf16hi_mul_bf16hi_elt: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] clamp +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.hi = extractelement <2 x bfloat> %src0, i32 1 + %src1.hi = extractelement <2 x bfloat> %src1, i32 1 + %src0.ext = fpext bfloat %src0.hi to float + %src1.ext = fpext bfloat %src1.hi to float + %result = fmul float %src0.ext, %src1.ext + %max = call float @llvm.maxnum.f32(float %result, float 0.0) + %clamp = call float @llvm.minnum.f32(float %max, float 1.0) + ret float %clamp +} + +define float @v_mad_mix_f32_negprecvtbf16lo_mul_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_negprecvtbf16lo_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0 + %src0.neg = fneg bfloat %src0 + %src0.ext = fpext bfloat %src0.neg to float + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absprecvtbf16lo_mul_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_absprecvtbf16lo_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0 + %src0.fabs = call bfloat @llvm.fabs.bf16(bfloat %src0) + %src0.ext = fpext bfloat %src0.fabs to float + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_negabsprecvtbf16lo_mul_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_negabsprecvtbf16lo_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 0 + %src0.fabs = call bfloat @llvm.fabs.bf16(bfloat %src0) + %src0.neg.abs = fneg bfloat %src0.fabs + %src0.ext = fpext bfloat %src0.neg.abs to float + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_precvtnegbf16hi_abs_mul_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_precvtnegbf16hi_abs_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-NEXT: v_xor_b32_e32 v0, 0x8000, v0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1 + %src0.neg = fneg bfloat %src0 + %src0.ext = fpext bfloat %src0.neg to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_precvtabsbf16hi_mul_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_precvtabsbf16hi_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %src0 = extractelement <2 x bfloat> %src0.arg.bc, i32 1 + %src0.abs = call bfloat @llvm.fabs.bf16(bfloat %src0) + %src0.ext = fpext bfloat %src0.abs to float + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfneg_bf16hi_mul_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_preextractfneg_bf16hi_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %fneg = fneg <2 x bfloat> %src0.arg.bc + %src0 = extractelement <2 x bfloat> %fneg, i32 1 + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfabs_bf16hi_mul_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_preextractfabs_bf16hi_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc) + %src0 = extractelement <2 x bfloat> %fabs, i32 1 + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfabsfneg_bf16hi_mul_bf16lo(i32 %src0.arg, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_preextractfabsfneg_bf16hi_mul_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x bfloat> + %fabs = call <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat> %src0.arg.bc) + %fneg.fabs = fneg <2 x bfloat> %fabs + %src0 = extractelement <2 x bfloat> %fneg.fabs, i32 1 + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16lo_sub_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16lo_sub_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %result = fsub float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absbf16lo_sub_bf16lo(bfloat %src0, bfloat %src1) { +; GFX1250-LABEL: v_mad_mix_f32_absbf16lo_sub_bf16lo: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, |v0| op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.ext = fpext bfloat %src0 to float + %src1.ext = fpext bfloat %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %result = fsub float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_bf16hi_fsub_bf16hi(i32 %src0, i32 %src1) { +; GFX1250-LABEL: v_mad_mix_f32_bf16hi_fsub_bf16hi: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, v0 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.hi = lshr i32 %src0, 16 + %src1.hi = lshr i32 %src1, 16 + %src0.i16 = trunc i32 %src0.hi to i16 + %src1.i16 = trunc i32 %src1.hi to i16 + %src0.fp16 = bitcast i16 %src0.i16 to bfloat + %src1.fp16 = bitcast i16 %src1.i16 to bfloat + %src0.ext = fpext bfloat %src0.fp16 to float + %src1.ext = fpext bfloat %src1.fp16 to float + %result = fsub float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absbf16hi_fsub_bf16hi(i32 %src0, i32 %src1) { +; GFX1250-LABEL: v_mad_mix_f32_absbf16hi_fsub_bf16hi: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v1, -1.0, |v0| op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1250-NEXT: s_set_pc_i64 s[30:31] + %src0.hi = lshr i32 %src0, 16 + %src1.hi = lshr i32 %src1, 16 + %src0.i16 = trunc i32 %src0.hi to i16 + %src1.i16 = trunc i32 %src1.hi to i16 + %src0.fp16 = bitcast i16 %src0.i16 to bfloat + %src1.fp16 = bitcast i16 %src1.i16 to bfloat + %src0.ext = fpext bfloat %src0.fp16 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src1.ext = fpext bfloat %src1.fp16 to float + %result = fsub float %src0.ext.abs, %src1.ext + ret float %result +} + declare bfloat @llvm.fabs.bf16(bfloat) #2 declare <2 x bfloat> @llvm.fabs.v2bf16(<2 x bfloat>) #2 declare float @llvm.fabs.f32(float) #2 @@ -625,6 +1393,6 @@ declare float @llvm.maxnum.f32(float, float) #2 declare float @llvm.fmuladd.f32(float, float, float) #2 declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #2 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } +attributes #1 = { nounwind denormal_fpenv(float: ieee|ieee) } attributes #2 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll index 393581fd148f6..4c3f61522f5ae 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll @@ -163,5 +163,5 @@ declare float @llvm.maxnum.f32(float, float) #1 declare float @llvm.fmuladd.f32(float, float, float) #1 declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll index 7044afb09e371..051470df48fdc 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll @@ -651,7 +651,7 @@ declare float @llvm.maxnum.f32(float, float) #1 declare float @llvm.fmuladd.f32(float, float, float) #1 declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone speculatable } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GISEL-GFX11-FAKE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll index 03304ae3946b3..a2f6b5f7cd073 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll @@ -496,5 +496,5 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) # declare <3 x float> @llvm.fmuladd.v3f32(<3 x float>, <3 x float>, <3 x float>) #1 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone speculatable } diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll index 154d6c7079672..689263d21f2cc 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll @@ -2758,7 +2758,7 @@ declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) # declare <3 x float> @llvm.fmuladd.v3f32(<3 x float>, <3 x float>, <3 x float>) #1 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone speculatable } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GISEL-GFX1100-FAKE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix.ll b/llvm/test/CodeGen/AMDGPU/mad-mix.ll index fcd9dae983cfb..ee5de5fb697a8 100644 --- a/llvm/test/CodeGen/AMDGPU/mad-mix.ll +++ b/llvm/test/CodeGen/AMDGPU/mad-mix.ll @@ -1854,27 +1854,13 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals(half %src0, half %src1, fl } define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half %src1, half %src2) #1 { -; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd: -; SDAG-GFX1100-TRUE16: ; %bb.0: -; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l -; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l -; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f32_f16_e32 v2, v2.l -; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; SDAG-GFX1100-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1 -; SDAG-GFX1100-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2 -; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd: -; SDAG-GFX1100-FAKE16: ; %bb.0: -; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-GFX1100-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 -; SDAG-GFX1100-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1 -; SDAG-GFX1100-FAKE16-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; SDAG-GFX1100-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1 -; SDAG-GFX1100-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2 -; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-NEXT: v_fma_mix_f32 v0, v2, 1.0, v0 op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd: ; GFX900: ; %bb.0: @@ -1889,11 +1875,8 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, ; GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd: ; GFX906: ; %bb.0: ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX906-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX906-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GFX906-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GFX906-NEXT: v_mul_f32_e32 v0, v0, v1 -; GFX906-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: v_fma_mix_f32 v0, v2, 1.0, v0 op_sel_hi:[1,1,0] ; GFX906-NEXT: s_setpc_b64 s[30:31] ; ; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd: @@ -1925,17 +1908,6 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, ; CI-NEXT: v_mul_f32_e32 v0, v0, v1 ; CI-NEXT: v_add_f32_e32 v0, v0, v2 ; CI-NEXT: s_setpc_b64 s[30:31] -; -; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd: -; GISEL-GFX1100: ; %bb.0: -; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-GFX1100-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GISEL-GFX1100-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GISEL-GFX1100-NEXT: v_cvt_f32_f16_e32 v2, v2 -; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GISEL-GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GISEL-GFX1100-NEXT: v_add_f32_e32 v0, v0, v2 -; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] %src0.ext = fpext half %src0 to float %src1.ext = fpext half %src1 to float %src2.ext = fpext half %src2 to float @@ -1945,25 +1917,13 @@ define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, } define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half %src1, float %src2) #1 { -; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd: -; SDAG-GFX1100-TRUE16: ; %bb.0: -; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l -; SDAG-GFX1100-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v1.l -; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; SDAG-GFX1100-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1 -; SDAG-GFX1100-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2 -; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd: -; SDAG-GFX1100-FAKE16: ; %bb.0: -; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-GFX1100-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0 -; SDAG-GFX1100-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1 -; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; SDAG-GFX1100-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1 -; SDAG-GFX1100-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2 -; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1100-NEXT: v_add_f32_e32 v0, v0, v2 +; GFX1100-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd: ; GFX900: ; %bb.0: @@ -1977,9 +1937,7 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half ; GFX906-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd: ; GFX906: ; %bb.0: ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX906-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GFX906-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GFX906-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] ; GFX906-NEXT: v_add_f32_e32 v0, v0, v2 ; GFX906-NEXT: s_setpc_b64 s[30:31] ; @@ -2009,16 +1967,6 @@ define float @v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd(half %src0, half ; CI-NEXT: v_mul_f32_e32 v0, v0, v1 ; CI-NEXT: v_add_f32_e32 v0, v0, v2 ; CI-NEXT: s_setpc_b64 s[30:31] -; -; GISEL-GFX1100-LABEL: v_mad_mix_f32_f16lo_f16lo_f32_denormals_fmulfadd: -; GISEL-GFX1100: ; %bb.0: -; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-GFX1100-NEXT: v_cvt_f32_f16_e32 v0, v0 -; GISEL-GFX1100-NEXT: v_cvt_f32_f16_e32 v1, v1 -; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GISEL-GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 -; GISEL-GFX1100-NEXT: v_add_f32_e32 v0, v0, v2 -; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] %src0.ext = fpext half %src0 to float %src1.ext = fpext half %src1 to float %mul = fmul float %src0.ext, %src1.ext @@ -2623,6 +2571,3325 @@ define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg, ret float %result } +define float @v_mad_mix_f32_f16lo_add_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_add_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_add_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_add_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_add_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_add_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_add_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16hi_add_f16hi(i32 %src0, i32 %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16hi_add_f16hi: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16hi_add_f16hi: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16hi_add_f16hi: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16hi_add_f16hi: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16hi_add_f16hi: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16hi_add_f16hi: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_add_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.hi = lshr i32 %src0, 16 + %src1.hi = lshr i32 %src1, 16 + %src0.i16 = trunc i32 %src0.hi to i16 + %src1.i16 = trunc i32 %src1.hi to i16 + %src0.fp16 = bitcast i16 %src0.i16 to half + %src1.fp16 = bitcast i16 %src1.i16 to half + %src0.ext = fpext half %src0.fp16 to float + %src1.ext = fpext half %src1.fp16 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16hi_add_f16hi_elt(<2 x half> %src0, <2 x half> %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16hi_add_f16hi_elt: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16hi_add_f16hi_elt: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16hi_add_f16hi_elt: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16hi_add_f16hi_elt: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16hi_add_f16hi_elt: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_f16hi_add_f16hi_elt: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_f16hi_add_f16hi_elt: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.hi = extractelement <2 x half> %src0, i32 1 + %src1.hi = extractelement <2 x half> %src1, i32 1 + %src0.ext = fpext half %src0.hi to float + %src1.ext = fpext half %src1.hi to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define <2 x float> @v_mad_mix_v2f32_cvt_add(<2 x half> %src0, <2 x half> %src1) { +; GFX1100-LABEL: v_mad_mix_v2f32_cvt_add: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1100-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1100-NEXT: v_mov_b32_e32 v0, v2 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_v2f32_cvt_add: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v4, v1 +; SDAG-GFX900-NEXT: v_add_f32_e32 v1, v2, v3 +; SDAG-GFX900-NEXT: v_add_f32_e32 v0, v0, v4 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_v2f32_cvt_add: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel_hi:[1,1,1] +; GFX906-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: v_mov_b32_e32 v0, v2 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_v2f32_cvt_add: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v4, v1 +; SDAG-GFX9GEN-NEXT: v_add_f32_e32 v1, v2, v3 +; SDAG-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v4 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_v2f32_cvt_add: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v4, v1 +; SDAG-VI-NEXT: v_add_f32_e32 v1, v2, v3 +; SDAG-VI-NEXT: v_add_f32_e32 v0, v0, v4 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_v2f32_cvt_add: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v4, v1 +; SDAG-CI-NEXT: v_add_f32_e32 v1, v3, v2 +; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v4 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_v2f32_cvt_add: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v2, v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v2, v0 +; GISEL-GFX900-NEXT: v_add_f32_e32 v1, v3, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_v2f32_cvt_add: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v2, v0 +; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v1, v3, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_v2f32_cvt_add: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v2, v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_add_f32_e32 v0, v2, v0 +; GISEL-VI-NEXT: v_add_f32_e32 v1, v3, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_v2f32_cvt_add: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v1, v2, v3 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext <2 x half> %src0 to <2 x float> + %src1.ext = fpext <2 x half> %src1 to <2 x float> + %result = fadd <2 x float> %src0.ext, %src1.ext + ret <2 x float> %result +} + +define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_add(<2 x half> %src0, <2 x half> %src1) { +; GFX1100-LABEL: v_mad_mix_v2f32_shuffle_cvt_add: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX1100-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[0,0,1] op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1100-NEXT: v_mov_b32_e32 v0, v2 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_v2f32_shuffle_cvt_add: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX900-NEXT: v_add_f32_e32 v1, v3, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_v2f32_shuffle_cvt_add: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v2, v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX906-NEXT: v_fma_mix_f32 v1, v0, 1.0, v1 op_sel:[0,0,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: v_mov_b32_e32 v0, v2 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_v2f32_shuffle_cvt_add: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX9GEN-NEXT: v_add_f32_e32 v1, v3, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_v2f32_shuffle_cvt_add: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_e32 v3, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v0, v1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_add_f32_e32 v0, v2, v0 +; VI-NEXT: v_add_f32_e32 v1, v3, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_v2f32_shuffle_cvt_add: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v4, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v2 +; SDAG-CI-NEXT: v_add_f32_e32 v0, v3, v0 +; SDAG-CI-NEXT: v_add_f32_e32 v1, v4, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_v2f32_shuffle_cvt_add: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v4, v0 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v2, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v1, v3, v4 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.shuf = shufflevector <2 x half> %src0, <2 x half> poison, <2 x i32> + %src1.shuf = shufflevector <2 x half> %src1, <2 x half> poison, <2 x i32> + %src0.ext = fpext <2 x half> %src0.shuf to <2 x float> + %src1.ext = fpext <2 x half> %src1.shuf to <2 x float> + %result = fadd <2 x float> %src0.ext, %src1.ext + ret <2 x float> %result +} + +define float @v_mad_mix_f32_negf16lo_add_f16lo(half %src0, half %src1) { +; SDAG-GFX1100-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; SDAG-GFX1100: ; %bb.0: +; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1] +; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX906-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; SDAG-GFX906: ; %bb.0: +; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1] +; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX1100-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; GISEL-GFX1100: ; %bb.0: +; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1] +; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX906-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; GISEL-GFX906: ; %bb.0: +; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1] +; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_negf16lo_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %src0.ext.neg = fneg float %src0.ext + %result = fadd float %src0.ext.neg, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absf16lo_add_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_absf16lo_add_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_absf16lo_add_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_absf16lo_add_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_absf16lo_add_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_absf16lo_add_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_add_f32_e64 v0, |v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_absf16lo_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_absf16lo_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %result = fadd float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_negabsf16lo_add_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_sub_f32_e64 v0, v1, |v0| +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_sub_f32_e64 v0, v1, |v0| +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_sub_f32_e64 v0, v1, |v0| +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_negabsf16lo_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_sub_f32_e64 v0, v1, |v0| +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src0.ext.neg.abs = fneg float %src0.ext.abs + %result = fadd float %src0.ext.neg.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16lo_add_f32(half %src0, float %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_f32: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_add_f32: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_add_f32: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_add_f32: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_add_f32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_add_f32: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_add_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %result = fadd float %src0.ext, %src1 + ret float %result +} + +define float @v_mad_mix_f32_f16lo_add_negf32(half %src0, float %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_negf32: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[0,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_add_negf32: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_add_negf32: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[0,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_add_negf32: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_add_negf32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_add_negf32: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_sub_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.neg = fneg float %src1 + %result = fadd float %src0.ext, %src1.neg + ret float %result +} + +define float @v_mad_mix_f32_f16lo_add_absf32(half %src0, float %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_absf32: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, |v1| op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_add_absf32: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_add_f32_e64 v0, v0, |v1| +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_add_absf32: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, |v1| op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_add_absf32: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_add_f32_e64 v0, v0, |v1| +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_add_absf32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_add_f32_e64 v0, v0, |v1| +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_add_absf32: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_add_f32_e64 v0, v0, |v1| +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.abs = call float @llvm.fabs.f32(float %src1) + %result = fadd float %src0.ext, %src1.abs + ret float %result +} + +define float @v_mad_mix_f32_f16lo_add_negabsf32(half %src0, float %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_add_negabsf32: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v1|, -1.0, v0 op_sel_hi:[0,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_add_negabsf32: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_sub_f32_e64 v0, v0, |v1| +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_add_negabsf32: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v1|, -1.0, v0 op_sel_hi:[0,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_add_negabsf32: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_sub_f32_e64 v0, v0, |v1| +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_add_negabsf32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_sub_f32_e64 v0, v0, |v1| +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_add_negabsf32: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_sub_f32_e64 v0, v0, |v1| +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.abs = call float @llvm.fabs.f32(float %src1) + %src1.neg.abs = fneg float %src1.abs + %result = fadd float %src0.ext, %src1.neg.abs + ret float %result +} + +define float @no_mix_simple_cvt_add(float %src0, float %src1) { +; GFX1100-LABEL: no_mix_simple_cvt_add: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: no_mix_simple_cvt_add: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: no_mix_simple_cvt_add: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: no_mix_simple_cvt_add: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: no_mix_simple_cvt_add: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: no_mix_simple_cvt_add: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_add_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %result = fadd float %src0, %src1 + ret float %result +} + +define float @no_mix_simple_fabs_cvt_add(float %src0, float %src1) { +; GFX1100-LABEL: no_mix_simple_fabs_cvt_add: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: no_mix_simple_fabs_cvt_add: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: no_mix_simple_fabs_cvt_add: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: no_mix_simple_fabs_cvt_add: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: no_mix_simple_fabs_cvt_add: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_add_f32_e64 v0, |v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: no_mix_simple_fabs_cvt_add: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_add_f32_e64 v0, |v0|, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.fabs = call float @llvm.fabs.f32(float %src0) + %result = fadd float %src0.fabs, %src1 + ret float %result +} + +define float @v_mad_mix_clamp_f32_f16hi_add_f16hi(<2 x half> %src0, <2 x half> %src1) { +; GFX1100-LABEL: v_mad_mix_clamp_f32_f16hi_add_f16hi: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] clamp +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_clamp_f32_f16hi_add_f16hi: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_add_f32_e64 v0, v0, v1 clamp +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_clamp_f32_f16hi_add_f16hi: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, 1.0, v1 op_sel:[1,0,1] op_sel_hi:[1,1,1] clamp +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_clamp_f32_f16hi_add_f16hi: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_add_f32_e64 v0, v0, v1 clamp +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_clamp_f32_f16hi_add_f16hi: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_add_f32_e64 v0, v0, v1 clamp +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_clamp_f32_f16hi_add_f16hi: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_add_f32_e64 v0, v0, v1 clamp +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_clamp_f32_f16hi_add_f16hi: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e64 v0, v0, v1 clamp +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.hi = extractelement <2 x half> %src0, i32 1 + %src1.hi = extractelement <2 x half> %src1, i32 1 + %src0.ext = fpext half %src0.hi to float + %src1.ext = fpext half %src1.hi to float + %result = fadd float %src0.ext, %src1.ext + %max = call float @llvm.maxnum.f32(float %result, float 0.0) + %clamp = call float @llvm.minnum.f32(float %max, float 1.0) + ret float %clamp +} + +define float @v_mad_mix_f32_negprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) { +; SDAG-GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; SDAG-GFX1100: ; %bb.0: +; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1] +; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX906-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; SDAG-GFX906: ; %bb.0: +; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel_hi:[1,1,1] +; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; GISEL-GFX1100: ; %bb.0: +; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1] +; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX906-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; GISEL-GFX906: ; %bb.0: +; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel_hi:[1,1,1] +; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_negprecvtf16lo_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 0 + %src0.neg = fneg half %src0 + %src0.ext = fpext half %src0.neg to float + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_absprecvtf16lo_add_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_add_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 0 + %src0.fabs = call half @llvm.fabs.f16(half %src0) + %src0.ext = fpext half %src0.fabs to float + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_negabsprecvtf16lo_add_f16lo(i32 %src0.arg, half %src1) { +; SDAG-GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; SDAG-GFX1100: ; %bb.0: +; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1] +; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX906-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; SDAG-GFX906: ; %bb.0: +; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel_hi:[1,1,1] +; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; GISEL-GFX1100: ; %bb.0: +; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX906-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; GISEL-GFX906: ; %bb.0: +; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 0 + %src0.fabs = call half @llvm.fabs.f16(half %src0) + %src0.neg.abs = fneg half %src0.fabs + %src0.ext = fpext half %src0.neg.abs to float + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo(i32 %src0.arg, half %src1) { +; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; SDAG-GFX1100-TRUE16: ; %bb.0: +; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l +; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h +; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, 1.0, v0 op_sel_hi:[1,1,1] +; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; SDAG-GFX1100-FAKE16: ; %bb.0: +; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; SDAG-GFX1100-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0 +; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: s_mov_b32 s4, 0x8000 +; GFX906-NEXT: v_xor_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_add_f32_e64 v0, |v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; GISEL-GFX1100: ; %bb.0: +; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x8000, v0 +; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel_hi:[1,1,1] +; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e64 v0, |v0|, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 1 + %src0.neg = fneg half %src0 + %src0.ext = fpext half %src0.neg to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_precvtabsf16hi_add_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_add_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_precvtabsf16hi_add_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_add_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 1 + %src0.abs = call half @llvm.fabs.f16(half %src0) + %src0.ext = fpext half %src0.abs to float + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) { +; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; SDAG-GFX1100: ; %bb.0: +; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; SDAG-GFX906: ; %bb.0: +; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, v0, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; GISEL-GFX1100: ; %bb.0: +; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; GISEL-GFX906: ; %bb.0: +; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -v0, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_preextractfneg_f16hi_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %fneg = fneg <2 x half> %src0.arg.bc + %src0 = extractelement <2 x half> %fneg, i32 1 + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfabs_f16hi_add_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc) + %src0 = extractelement <2 x half> %fabs, i32 1 + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo(i32 %src0.arg, half %src1) { +; SDAG-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; SDAG-GFX1100: ; %bb.0: +; SDAG-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; SDAG-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; SDAG-GFX906: ; %bb.0: +; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX906-NEXT: v_fma_mix_f32 v0, |v0|, -1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_sub_f32_e32 v0, v1, v0 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; GISEL-GFX1100: ; %bb.0: +; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_or_b32_e32 v0, 0x80008000, v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; GISEL-GFX906: ; %bb.0: +; GISEL-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, 1.0, v1 op_sel:[1,0,0] op_sel_hi:[1,1,1] +; GISEL-GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_or_b32_e32 v0, 0x80008000, v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_or_b32_e32 v0, 0x80008000, v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_add_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_or_b32_e32 v0, 0x80008000, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_add_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc) + %fneg.fabs = fneg <2 x half> %fabs + %src0 = extractelement <2 x half> %fneg.fabs, i32 1 + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fadd float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16lo_mul_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_mul_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_mul_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_mul_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16hi_mul_f16hi_int(i32 %src0, i32 %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_int: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_int: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_int: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_int: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_int: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_int: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.hi = lshr i32 %src0, 16 + %src1.hi = lshr i32 %src1, 16 + %src0.i16 = trunc i32 %src0.hi to i16 + %src1.i16 = trunc i32 %src1.hi to i16 + %src0.fp16 = bitcast i16 %src0.i16 to half + %src1.fp16 = bitcast i16 %src1.i16 to half + %src0.ext = fpext half %src0.fp16 to float + %src1.ext = fpext half %src1.fp16 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16hi_mul_f16hi_elt(<2 x half> %src0, <2 x half> %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_elt: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_elt: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_elt: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_elt: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_elt: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_elt: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_f16hi_mul_f16hi_elt: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.hi = extractelement <2 x half> %src0, i32 1 + %src1.hi = extractelement <2 x half> %src1, i32 1 + %src0.ext = fpext half %src0.hi to float + %src1.ext = fpext half %src1.hi to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define <2 x float> @v_mad_mix_v2f32_cvt_mul(<2 x half> %src0, <2 x half> %src1) { +; GFX1100-LABEL: v_mad_mix_v2f32_cvt_mul: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1100-NEXT: v_mov_b32_e32 v0, v2 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_v2f32_cvt_mul: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v4, v1 +; SDAG-GFX900-NEXT: v_mul_f32_e32 v1, v2, v3 +; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v4 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_v2f32_cvt_mul: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: v_mov_b32_e32 v0, v2 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_v2f32_cvt_mul: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v4, v1 +; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v1, v2, v3 +; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v4 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_v2f32_cvt_mul: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v4, v1 +; SDAG-VI-NEXT: v_mul_f32_e32 v1, v2, v3 +; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v4 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_v2f32_cvt_mul: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v4, v1 +; SDAG-CI-NEXT: v_mul_f32_e32 v1, v3, v2 +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v4 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_v2f32_cvt_mul: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v2, v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v2, v0 +; GISEL-GFX900-NEXT: v_mul_f32_e32 v1, v3, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_v2f32_cvt_mul: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v2, v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v2, v0 +; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v1, v3, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_v2f32_cvt_mul: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v2, v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_mul_f32_e32 v0, v2, v0 +; GISEL-VI-NEXT: v_mul_f32_e32 v1, v3, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_v2f32_cvt_mul: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: v_mul_f32_e32 v1, v2, v3 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext <2 x half> %src0 to <2 x float> + %src1.ext = fpext <2 x half> %src1 to <2 x float> + %result = fmul <2 x float> %src0.ext, %src1.ext + ret <2 x float> %result +} + +define <2 x float> @v_mad_mix_v2f32_shuffle_cvt_mul(<2 x half> %src0, <2 x half> %src1) { +; GFX1100-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[0,1,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1100-NEXT: v_mov_b32_e32 v0, v2 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_mul_f32_e32 v0, v2, v0 +; GFX900-NEXT: v_mul_f32_e32 v1, v3, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v2, v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: v_fma_mix_f32 v1, v0, v1, neg(0) op_sel:[0,1,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: v_mov_b32_e32 v0, v2 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v2, v0 +; GFX9GEN-NEXT: v_mul_f32_e32 v1, v3, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_e32 v3, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v0, v1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_mul_f32_e32 v0, v2, v0 +; VI-NEXT: v_mul_f32_e32 v1, v3, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v4, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v2 +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v3, v0 +; SDAG-CI-NEXT: v_mul_f32_e32 v1, v4, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_v2f32_shuffle_cvt_mul: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v3, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v4, v0 +; GISEL-CI-NEXT: v_mul_f32_e32 v0, v2, v1 +; GISEL-CI-NEXT: v_mul_f32_e32 v1, v3, v4 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.shuf = shufflevector <2 x half> %src0, <2 x half> poison, <2 x i32> + %src1.shuf = shufflevector <2 x half> %src1, <2 x half> poison, <2 x i32> + %src0.ext = fpext <2 x half> %src0.shuf to <2 x float> + %src1.ext = fpext <2 x half> %src1.shuf to <2 x float> + %result = fmul <2 x float> %src0.ext, %src1.ext + ret <2 x float> %result +} + +define float @v_mad_mix_f32_negf16lo_mul_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_negf16lo_mul_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %src0.ext.neg = fneg float %src0.ext + %result = fmul float %src0.ext.neg, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absf16lo_mul_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_absf16lo_mul_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %result = fmul float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_negabsf16lo_mul_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_negabsf16lo_mul_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e64 v0, -|v0|, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src0.ext.neg.abs = fneg float %src0.ext.abs + %result = fmul float %src0.ext.neg.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16lo_mul_f32(half %src0, float %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_f32: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,0,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_f32: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_mul_f32: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel_hi:[1,0,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_mul_f32: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_mul_f32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_mul_f32: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %result = fmul float %src0.ext, %src1 + ret float %result +} + +define float @v_mad_mix_f32_f16lo_mul_negf32(half %src0, float %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_negf32: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_negf32: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_mul_f32_e64 v0, v0, -v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_mul_negf32: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, -v1, neg(0) op_sel_hi:[1,0,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_mul_negf32: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_mul_f32_e64 v0, v0, -v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_mul_negf32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_mul_f32_e64 v0, v0, -v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_mul_negf32: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_mul_f32_e64 v0, v0, -v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.neg = fneg float %src1 + %result = fmul float %src0.ext, %src1.neg + ret float %result +} + +define float @v_mad_mix_f32_f16lo_mul_absf32(half %src0, float %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_absf32: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_absf32: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_mul_f32_e64 v0, v0, |v1| +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_mul_absf32: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, |v1|, neg(0) op_sel_hi:[1,0,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_mul_absf32: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_mul_f32_e64 v0, v0, |v1| +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_mul_absf32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_mul_f32_e64 v0, v0, |v1| +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_mul_absf32: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_mul_f32_e64 v0, v0, |v1| +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.abs = call float @llvm.fabs.f32(float %src1) + %result = fmul float %src0.ext, %src1.abs + ret float %result +} + +define float @v_mad_mix_f32_f16lo_mul_negabsf32(half %src0, float %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_mul_f32_e64 v0, v0, -|v1| +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, -|v1|, neg(0) op_sel_hi:[1,0,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_mul_f32_e64 v0, v0, -|v1| +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_mul_f32_e64 v0, v0, -|v1| +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_mul_negabsf32: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_mul_f32_e64 v0, v0, -|v1| +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.abs = call float @llvm.fabs.f32(float %src1) + %src1.neg.abs = fneg float %src1.abs + %result = fmul float %src0.ext, %src1.neg.abs + ret float %result +} + +define float @no_mix_simple_cvt_mul(float %src0, float %src1) { +; GFX1100-LABEL: no_mix_simple_cvt_mul: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: no_mix_simple_cvt_mul: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: no_mix_simple_cvt_mul: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: no_mix_simple_cvt_mul: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: no_mix_simple_cvt_mul: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: no_mix_simple_cvt_mul: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %result = fmul float %src0, %src1 + ret float %result +} + +define float @no_mix_simple_fabs_cvt_mul(float %src0, float %src1) { +; GFX1100-LABEL: no_mix_simple_fabs_cvt_mul: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: no_mix_simple_fabs_cvt_mul: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: no_mix_simple_fabs_cvt_mul: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: no_mix_simple_fabs_cvt_mul: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: no_mix_simple_fabs_cvt_mul: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: no_mix_simple_fabs_cvt_mul: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.fabs = call float @llvm.fabs.f32(float %src0) + %result = fmul float %src0.fabs, %src1 + ret float %result +} + +define float @v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt(<2 x half> %src0, <2 x half> %src1) { +; GFX1100-LABEL: v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] clamp +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_mul_f32_e64 v0, v0, v1 clamp +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v0, v1, neg(0) op_sel:[1,1,0] op_sel_hi:[1,1,0] clamp +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_mul_f32_e64 v0, v0, v1 clamp +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_mul_f32_e64 v0, v0, v1 clamp +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_mul_f32_e64 v0, v0, v1 clamp +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_clamp_f32_f16hi_mul_f16hi_elt: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e64 v0, v0, v1 clamp +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.hi = extractelement <2 x half> %src0, i32 1 + %src1.hi = extractelement <2 x half> %src1, i32 1 + %src0.ext = fpext half %src0.hi to float + %src1.ext = fpext half %src1.hi to float + %result = fmul float %src0.ext, %src1.ext + %max = call float @llvm.maxnum.f32(float %result, float 0.0) + %clamp = call float @llvm.minnum.f32(float %max, float 1.0) + ret float %clamp +} + +define float @v_mad_mix_f32_negprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_negprecvtf16lo_mul_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 0 + %src0.neg = fneg half %src0 + %src0.ext = fpext half %src0.neg to float + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_absprecvtf16lo_mul_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 0 + %src0.fabs = call half @llvm.fabs.f16(half %src0) + %src0.ext = fpext half %src0.fabs to float + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_negabsprecvtf16lo_mul_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 0 + %src0.fabs = call half @llvm.fabs.f16(half %src0) + %src0.neg.abs = fneg half %src0.fabs + %src0.ext = fpext half %src0.neg.abs to float + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo(i32 %src0.arg, half %src1) { +; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; SDAG-GFX1100-TRUE16: ; %bb.0: +; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l +; SDAG-GFX1100-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v0.h +; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX1100-TRUE16-NEXT: v_fma_mix_f32 v0, |v1|, v0, neg(0) op_sel_hi:[1,1,0] +; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; SDAG-GFX1100-FAKE16: ; %bb.0: +; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX1100-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; SDAG-GFX1100-FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0 +; SDAG-GFX1100-FAKE16-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: s_mov_b32 s4, 0x8000 +; GFX906-NEXT: v_xor_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX1100-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; GISEL-GFX1100: ; %bb.0: +; GISEL-GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX1100-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GISEL-GFX1100-NEXT: v_xor_b32_e32 v0, 0x8000, v0 +; GISEL-GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel_hi:[1,1,0] +; GISEL-GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_precvtnegf16hi_abs_mul_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e64 v0, |v0|, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 1 + %src0.neg = fneg half %src0 + %src0.ext = fpext half %src0.neg to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_precvtabsf16hi_mul_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_precvtabsf16hi_mul_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %src0 = extractelement <2 x half> %src0.arg.bc, i32 1 + %src0.abs = call half @llvm.fabs.f16(half %src0) + %src0.ext = fpext half %src0.abs to float + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, -v0, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v0, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_preextractfneg_f16hi_mul_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %fneg = fneg <2 x half> %src0.arg.bc + %src0 = extractelement <2 x half> %fneg, i32 1 + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, |v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabs_f16hi_mul_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc) + %src0 = extractelement <2 x half> %fabs, i32 1 + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo(i32 %src0.arg, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; SDAG-GFX900: ; %bb.0: +; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, -|v0|, v1, neg(0) op_sel:[1,0,0] op_sel_hi:[1,1,0] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; SDAG-GFX9GEN: ; %bb.0: +; SDAG-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-VI-NEXT: v_cvt_f32_f16_sdwa v0, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; SDAG-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, -|v0| +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX900-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; GISEL-GFX900: ; %bb.0: +; GISEL-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX900-NEXT: v_or_b32_e32 v0, 0x80008000, v0 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX900-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX9GEN-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; GISEL-GFX9GEN: ; %bb.0: +; GISEL-GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX9GEN-NEXT: v_or_b32_e32 v0, 0x80008000, v0 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-GFX9GEN-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-VI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-VI-NEXT: v_or_b32_e32 v0, 0x80008000, v0 +; GISEL-VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GISEL-VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-VI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-VI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_preextractfabsfneg_f16hi_mul_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_or_b32_e32 v0, 0x80008000, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_mul_f32_e32 v0, v0, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.arg.bc = bitcast i32 %src0.arg to <2 x half> + %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %src0.arg.bc) + %fneg.fabs = fneg <2 x half> %fabs + %src0 = extractelement <2 x half> %fneg.fabs, i32 1 + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fmul float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16lo_sub_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16lo_sub_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16lo_sub_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16lo_sub_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16lo_sub_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16lo_sub_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16lo_sub_f16lo: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_sub_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %result = fsub float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absf16lo_sub_f16lo(half %src0, half %src1) { +; GFX1100-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, |v0| op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX900-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX900-NEXT: v_sub_f32_e64 v0, |v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v1, -1.0, |v0| op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GFX9GEN-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GFX9GEN-NEXT: v_sub_f32_e64 v0, |v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; VI-NEXT: v_sub_f32_e64 v0, |v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_sub_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_absf16lo_sub_f16lo: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_sub_f32_e64 v0, |v0|, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.ext = fpext half %src0 to float + %src1.ext = fpext half %src1 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %result = fsub float %src0.ext.abs, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_f16hi_fsub_f16hi(i32 %src0, i32 %src1) { +; GFX1100-LABEL: v_mad_mix_f32_f16hi_fsub_f16hi: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_f16hi_fsub_f16hi: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_f16hi_fsub_f16hi: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v1, -1.0, v0 op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_f16hi_fsub_f16hi: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_f16hi_fsub_f16hi: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_sub_f32_e32 v0, v0, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; CI-LABEL: v_mad_mix_f32_f16hi_fsub_f16hi: +; CI: ; %bb.0: +; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; CI-NEXT: v_sub_f32_e32 v0, v0, v1 +; CI-NEXT: s_setpc_b64 s[30:31] + %src0.hi = lshr i32 %src0, 16 + %src1.hi = lshr i32 %src1, 16 + %src0.i16 = trunc i32 %src0.hi to i16 + %src1.i16 = trunc i32 %src1.hi to i16 + %src0.fp16 = bitcast i16 %src0.i16 to half + %src1.fp16 = bitcast i16 %src1.i16 to half + %src0.ext = fpext half %src0.fp16 to float + %src1.ext = fpext half %src1.fp16 to float + %result = fsub float %src0.ext, %src1.ext + ret float %result +} + +define float @v_mad_mix_f32_absf16hi_fsub_f16hi(i32 %src0, i32 %src1) { +; GFX1100-LABEL: v_mad_mix_f32_absf16hi_fsub_f16hi: +; GFX1100: ; %bb.0: +; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX1100-NEXT: v_fma_mix_f32 v0, v1, -1.0, |v0| op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX1100-NEXT: s_setpc_b64 s[30:31] +; +; GFX900-LABEL: v_mad_mix_f32_absf16hi_fsub_f16hi: +; GFX900: ; %bb.0: +; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX900-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX900-NEXT: v_sub_f32_e64 v0, |v0|, v1 +; GFX900-NEXT: s_setpc_b64 s[30:31] +; +; GFX906-LABEL: v_mad_mix_f32_absf16hi_fsub_f16hi: +; GFX906: ; %bb.0: +; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX906-NEXT: v_fma_mix_f32 v0, v1, -1.0, |v0| op_sel:[1,0,1] op_sel_hi:[1,1,1] +; GFX906-NEXT: s_setpc_b64 s[30:31] +; +; GFX9GEN-LABEL: v_mad_mix_f32_absf16hi_fsub_f16hi: +; GFX9GEN: ; %bb.0: +; GFX9GEN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9GEN-NEXT: v_sub_f32_e64 v0, |v0|, v1 +; GFX9GEN-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: v_mad_mix_f32_absf16hi_fsub_f16hi: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_cvt_f32_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; VI-NEXT: v_sub_f32_e64 v0, |v0|, v1 +; VI-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-CI-LABEL: v_mad_mix_f32_absf16hi_fsub_f16hi: +; SDAG-CI: ; %bb.0: +; SDAG-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; SDAG-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SDAG-CI-NEXT: v_cvt_f32_f16_e64 v0, |v0| +; SDAG-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SDAG-CI-NEXT: v_sub_f32_e32 v0, v0, v1 +; SDAG-CI-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-CI-LABEL: v_mad_mix_f32_absf16hi_fsub_f16hi: +; GISEL-CI: ; %bb.0: +; GISEL-CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GISEL-CI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; GISEL-CI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; GISEL-CI-NEXT: v_sub_f32_e64 v0, |v0|, v1 +; GISEL-CI-NEXT: s_setpc_b64 s[30:31] + %src0.hi = lshr i32 %src0, 16 + %src1.hi = lshr i32 %src1, 16 + %src0.i16 = trunc i32 %src0.hi to i16 + %src1.i16 = trunc i32 %src1.hi to i16 + %src0.fp16 = bitcast i16 %src0.i16 to half + %src1.fp16 = bitcast i16 %src1.i16 to half + %src0.ext = fpext half %src0.fp16 to float + %src0.ext.abs = call float @llvm.fabs.f32(float %src0.ext) + %src1.ext = fpext half %src1.fp16 to float + %result = fsub float %src0.ext.abs, %src1.ext + ret float %result +} + declare half @llvm.fabs.f16(half) #2 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2 declare float @llvm.fabs.f32(float) #2 @@ -2631,8 +5898,8 @@ declare float @llvm.maxnum.f32(float, float) #2 declare float @llvm.fmuladd.f32(float, float, float) #2 declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #2 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } +attributes #1 = { nounwind denormal_fpenv(float: ieee|ieee) } attributes #2 = { nounwind readnone speculatable } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GISEL-GFX1100-FAKE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/madak.ll b/llvm/test/CodeGen/AMDGPU/madak.ll index b2813b392d253..b16dad4316db4 100644 --- a/llvm/test/CodeGen/AMDGPU/madak.ll +++ b/llvm/test/CodeGen/AMDGPU/madak.ll @@ -1510,4 +1510,4 @@ bb4: ret void } -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/madmk.ll b/llvm/test/CodeGen/AMDGPU/madmk.ll index 4ef752b45e143..7b96296172035 100644 --- a/llvm/test/CodeGen/AMDGPU/madmk.ll +++ b/llvm/test/CodeGen/AMDGPU/madmk.ll @@ -214,5 +214,5 @@ bb6: ; preds = %bb2 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll index 4f2816538b1ff..c60642e2cc4d8 100644 --- a/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll +++ b/llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll @@ -15974,6 +15974,1616 @@ entry: ret void } +define void @memset_p0_sz2048(ptr addrspace(0) %dst) { +; CHECK-LABEL: memset_p0_sz2048: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s4, 0x41414141 +; CHECK-NEXT: s_mov_b32 s5, s4 +; CHECK-NEXT: s_mov_b32 s6, s4 +; CHECK-NEXT: s_mov_b32 s7, s4 +; CHECK-NEXT: v_mov_b32_e32 v2, s4 +; CHECK-NEXT: v_mov_b32_e32 v3, s5 +; CHECK-NEXT: v_mov_b32_e32 v4, s6 +; CHECK-NEXT: v_mov_b32_e32 v5, s7 +; CHECK-NEXT: s_mov_b64 s[4:5], 0 +; CHECK-NEXT: s_inst_prefetch 0x1 +; CHECK-NEXT: .p2align 6 +; CHECK-NEXT: .LBB10_1: ; %static-memset-expansion-main-body +; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: v_add_co_u32 v6, vcc_lo, v0, s4 +; CHECK-NEXT: s_add_u32 s4, s4, 0x100 +; CHECK-NEXT: v_add_co_ci_u32_e64 v7, null, s5, v1, vcc_lo +; CHECK-NEXT: s_addc_u32 s5, s5, 0 +; CHECK-NEXT: v_add_co_u32 v8, vcc_lo, v6, 48 +; CHECK-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5] +; CHECK-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v7, vcc_lo +; CHECK-NEXT: flat_store_dwordx4 v[6:7], v[2:5] offset:128 +; CHECK-NEXT: flat_store_dwordx4 v[6:7], v[2:5] offset:64 +; CHECK-NEXT: flat_store_dwordx4 v[6:7], v[2:5] offset:32 +; CHECK-NEXT: flat_store_dwordx4 v[6:7], v[2:5] offset:16 +; CHECK-NEXT: flat_store_dwordx4 v[6:7], v[2:5] +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:192 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:176 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:160 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:144 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:128 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:112 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:96 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:64 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:48 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] offset:32 +; CHECK-NEXT: flat_store_dwordx4 v[8:9], v[2:5] +; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; CHECK-NEXT: s_cbranch_vccnz .LBB10_1 +; CHECK-NEXT: ; %bb.2: ; %static-memset-post-expansion +; CHECK-NEXT: s_inst_prefetch 0x2 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +; +; ALIGNED-LABEL: memset_p0_sz2048: +; ALIGNED: ; %bb.0: ; %entry +; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; ALIGNED-NEXT: v_mov_b32_e32 v4, 0x41414141 +; ALIGNED-NEXT: v_mov_b32_e32 v5, 0x41 +; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 +; ALIGNED-NEXT: .LBB10_1: ; %static-memset-expansion-main-body +; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1 +; ALIGNED-NEXT: v_add_co_u32 v2, vcc_lo, v0, s4 +; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, s5, v1, vcc_lo +; ALIGNED-NEXT: s_add_u32 s4, s4, 0x100 +; ALIGNED-NEXT: s_addc_u32 s5, s5, 0 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:204 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:200 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:196 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:192 +; ALIGNED-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5] +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:128 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:12 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:8 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:4 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:64 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:108 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:104 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:100 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:32 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:60 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:56 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:52 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:48 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:16 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:76 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:68 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:64 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:8 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:4 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:2 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:1 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 +; ALIGNED-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3 +; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo +; ALIGNED-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:152 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:156 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:148 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:144 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:247 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:248 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:246 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:252 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:251 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:250 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:249 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:245 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:244 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:243 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:242 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:241 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:240 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:239 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:238 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:237 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:168 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:172 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:164 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:231 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:232 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:230 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:236 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:235 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:234 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:233 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:229 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:228 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:227 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:226 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:225 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:224 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:223 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:222 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:221 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:120 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:124 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:215 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:216 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:214 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:220 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:219 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:218 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:217 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:213 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:212 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:211 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:210 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:209 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:208 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:207 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:206 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:205 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:140 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:132 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:128 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:199 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:200 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:198 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:204 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:203 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:202 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:201 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:197 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:196 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:195 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:194 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:193 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:192 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:191 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:190 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:189 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:216 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:220 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:212 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:208 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:183 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:184 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:182 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:188 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:187 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:186 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:185 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:181 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:180 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:179 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:178 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:177 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:176 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:175 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:174 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:173 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:232 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:236 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:228 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:224 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:167 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:168 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:166 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:172 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:171 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:170 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:169 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:165 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:164 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:163 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:162 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:161 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:160 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:159 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:158 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:157 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:184 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:188 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:180 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:176 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:151 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:152 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:150 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:156 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:155 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:154 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:153 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:149 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:148 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:147 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:146 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:145 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:144 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:143 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:142 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:141 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:135 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:136 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:134 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:140 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:139 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:138 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:137 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:133 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:132 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:131 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:130 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:129 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:128 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:127 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:126 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:24 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:28 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:16 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:119 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:120 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:118 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:124 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:123 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:122 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:121 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:117 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:116 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:115 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:114 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:113 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:112 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:111 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:110 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:109 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:40 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:44 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:36 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:32 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:103 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:104 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:102 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:108 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:107 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:106 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:105 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:101 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:100 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:99 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:98 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:97 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:96 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:95 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:94 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:93 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:244 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:240 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:78 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:77 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:80 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:79 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:84 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:83 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:82 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:81 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:86 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:85 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:88 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:87 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:92 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:91 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:90 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:89 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:71 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:72 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:70 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:76 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:75 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:74 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:73 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:69 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:68 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:67 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:66 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:65 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:64 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:63 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:62 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:92 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:84 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:55 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:56 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:54 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:60 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:59 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:58 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:57 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:53 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:52 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:51 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:50 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:49 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:48 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:47 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:46 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:45 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:39 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:40 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:38 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:44 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:43 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:42 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:41 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:37 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:36 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:35 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:34 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:33 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:32 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:31 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:30 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:23 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:24 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:22 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:28 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:27 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:26 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:25 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:21 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:20 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:19 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:18 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:17 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:16 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:15 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:14 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:7 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:8 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:6 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:12 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:11 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:10 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:9 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:4 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:3 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 offset:2 +; ALIGNED-NEXT: flat_store_byte v[2:3], v5 +; ALIGNED-NEXT: s_cbranch_vccnz .LBB10_1 +; ALIGNED-NEXT: ; %bb.2: ; %static-memset-post-expansion +; ALIGNED-NEXT: s_waitcnt lgkmcnt(0) +; ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; UNROLL3-LABEL: memset_p0_sz2048: +; UNROLL3: ; %bb.0: ; %entry +; UNROLL3-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; UNROLL3-NEXT: s_mov_b32 s4, 0x41414141 +; UNROLL3-NEXT: s_mov_b32 s5, s4 +; UNROLL3-NEXT: s_mov_b32 s6, s4 +; UNROLL3-NEXT: s_mov_b32 s7, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v2, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v3, s5 +; UNROLL3-NEXT: v_mov_b32_e32 v4, s6 +; UNROLL3-NEXT: v_mov_b32_e32 v5, s7 +; UNROLL3-NEXT: s_mov_b64 s[4:5], 0 +; UNROLL3-NEXT: .p2align 6 +; UNROLL3-NEXT: .LBB10_1: ; %static-memset-expansion-main-body +; UNROLL3-NEXT: ; =>This Inner Loop Header: Depth=1 +; UNROLL3-NEXT: v_add_co_u32 v6, vcc_lo, v0, s4 +; UNROLL3-NEXT: s_add_u32 s4, s4, 48 +; UNROLL3-NEXT: v_add_co_ci_u32_e64 v7, null, s5, v1, vcc_lo +; UNROLL3-NEXT: s_addc_u32 s5, s5, 0 +; UNROLL3-NEXT: flat_store_dwordx4 v[6:7], v[2:5] offset:16 +; UNROLL3-NEXT: flat_store_dwordx4 v[6:7], v[2:5] +; UNROLL3-NEXT: v_cmp_gt_u64_e64 s6, 0x7e0, s[4:5] +; UNROLL3-NEXT: flat_store_dwordx4 v[6:7], v[2:5] offset:32 +; UNROLL3-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; UNROLL3-NEXT: s_cbranch_vccnz .LBB10_1 +; UNROLL3-NEXT: ; %bb.2: ; %static-memset-post-expansion +; UNROLL3-NEXT: s_mov_b32 s4, 0x41414141 +; UNROLL3-NEXT: s_mov_b32 s5, s4 +; UNROLL3-NEXT: s_mov_b32 s6, s4 +; UNROLL3-NEXT: s_mov_b32 s7, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v2, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v3, s5 +; UNROLL3-NEXT: v_mov_b32_e32 v4, s6 +; UNROLL3-NEXT: v_mov_b32_e32 v5, s7 +; UNROLL3-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:2016 +; UNROLL3-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:2032 +; UNROLL3-NEXT: s_waitcnt lgkmcnt(0) +; UNROLL3-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p0.i64(ptr addrspace(0) noundef nonnull %dst, i8 65, i64 2048, i1 false) + ret void +} + +define void @memset_p1_sz2048(ptr addrspace(1) %dst) { +; CHECK-LABEL: memset_p1_sz2048: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s4, 0x41414141 +; CHECK-NEXT: s_mov_b32 s5, s4 +; CHECK-NEXT: s_mov_b32 s6, s4 +; CHECK-NEXT: s_mov_b32 s7, s4 +; CHECK-NEXT: v_mov_b32_e32 v2, s4 +; CHECK-NEXT: v_mov_b32_e32 v3, s5 +; CHECK-NEXT: v_mov_b32_e32 v4, s6 +; CHECK-NEXT: v_mov_b32_e32 v5, s7 +; CHECK-NEXT: s_mov_b64 s[4:5], 0 +; CHECK-NEXT: s_inst_prefetch 0x1 +; CHECK-NEXT: .p2align 6 +; CHECK-NEXT: .LBB11_1: ; %static-memset-expansion-main-body +; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: v_add_co_u32 v6, vcc_lo, v0, s4 +; CHECK-NEXT: s_add_u32 s4, s4, 0x100 +; CHECK-NEXT: v_add_co_ci_u32_e64 v7, null, s5, v1, vcc_lo +; CHECK-NEXT: s_addc_u32 s5, s5, 0 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:240 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:224 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:208 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:192 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:176 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:160 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:144 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:128 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:112 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:96 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:80 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:64 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:48 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:32 +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:16 +; CHECK-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5] +; CHECK-NEXT: global_store_dwordx4 v[6:7], v[2:5], off +; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; CHECK-NEXT: s_cbranch_vccnz .LBB11_1 +; CHECK-NEXT: ; %bb.2: ; %static-memset-post-expansion +; CHECK-NEXT: s_inst_prefetch 0x2 +; CHECK-NEXT: s_setpc_b64 s[30:31] +; +; ALIGNED-LABEL: memset_p1_sz2048: +; ALIGNED: ; %bb.0: ; %entry +; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; ALIGNED-NEXT: v_mov_b32_e32 v4, 0x41414141 +; ALIGNED-NEXT: v_mov_b32_e32 v5, 0x41 +; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 +; ALIGNED-NEXT: .LBB11_1: ; %static-memset-expansion-main-body +; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1 +; ALIGNED-NEXT: v_add_co_u32 v2, vcc_lo, v0, s4 +; ALIGNED-NEXT: s_add_u32 s4, s4, 0x100 +; ALIGNED-NEXT: v_add_co_ci_u32_e64 v3, null, s5, v1, vcc_lo +; ALIGNED-NEXT: s_addc_u32 s5, s5, 0 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:152 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:156 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:148 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:144 +; ALIGNED-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5] +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:250 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:251 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:249 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:255 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:254 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:253 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:252 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:248 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:247 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:246 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:245 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:244 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:243 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:242 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:241 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:240 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:168 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:172 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:164 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:234 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:235 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:233 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:239 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:238 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:237 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:236 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:232 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:231 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:230 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:229 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:228 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:227 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:226 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:225 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:224 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:120 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:124 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:116 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:112 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:218 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:219 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:217 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:223 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:222 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:221 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:220 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:216 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:215 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:214 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:213 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:212 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:211 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:210 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:209 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:208 +; ALIGNED-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:140 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:132 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:128 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:202 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:203 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:201 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:207 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:206 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:205 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:204 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:200 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:199 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:198 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:197 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:196 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:195 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:194 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:193 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:192 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:216 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:220 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:212 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:208 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:186 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:187 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:185 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:191 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:190 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:189 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:188 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:184 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:183 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:182 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:181 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:180 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:179 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:178 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:177 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:176 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:232 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:236 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:228 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:224 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:170 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:171 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:169 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:175 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:174 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:173 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:172 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:168 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:167 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:166 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:165 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:164 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:163 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:162 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:161 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:160 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:184 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:188 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:180 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:176 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:154 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:155 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:153 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:159 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:158 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:157 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:156 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:152 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:151 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:150 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:149 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:148 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:147 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:146 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:145 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:144 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:200 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:204 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:196 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:192 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:138 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:139 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:137 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:143 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:142 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:141 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:140 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:136 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:135 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:134 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:133 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:132 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:131 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:130 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:129 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:128 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:24 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:28 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:16 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:122 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:123 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:121 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:127 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:126 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:125 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:124 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:120 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:119 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:118 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:117 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:116 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:115 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:114 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:113 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:112 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:40 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:44 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:36 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:32 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:106 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:107 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:105 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:111 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:110 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:109 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:108 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:104 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:103 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:102 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:101 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:100 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:99 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:98 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:97 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:96 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:244 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:240 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:81 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:80 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:83 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:82 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:87 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:86 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:85 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:84 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:89 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:88 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:91 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:90 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:95 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:94 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:93 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:92 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:8 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:12 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:4 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:74 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:75 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:73 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:79 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:78 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:77 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:76 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:72 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:71 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:70 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:69 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:68 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:67 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:66 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:65 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:64 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:92 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:84 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:58 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:59 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:57 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:63 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:62 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:61 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:60 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:56 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:55 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:54 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:53 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:52 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:51 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:50 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:49 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:48 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:104 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:108 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:100 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:42 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:43 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:41 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:47 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:46 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:45 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:44 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:40 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:39 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:38 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:37 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:36 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:35 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:34 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:33 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:32 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:56 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:60 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:52 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:48 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:26 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:27 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:25 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:31 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:30 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:29 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:28 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:24 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:23 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:22 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:21 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:20 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:19 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:18 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:17 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:16 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:76 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:68 +; ALIGNED-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:64 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:10 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:11 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:9 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:15 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:14 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:13 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:12 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:8 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:7 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:6 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:5 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:4 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:3 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:2 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off offset:1 +; ALIGNED-NEXT: global_store_byte v[2:3], v5, off +; ALIGNED-NEXT: s_cbranch_vccnz .LBB11_1 +; ALIGNED-NEXT: ; %bb.2: ; %static-memset-post-expansion +; ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; UNROLL3-LABEL: memset_p1_sz2048: +; UNROLL3: ; %bb.0: ; %entry +; UNROLL3-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; UNROLL3-NEXT: s_mov_b32 s4, 0x41414141 +; UNROLL3-NEXT: s_mov_b32 s5, s4 +; UNROLL3-NEXT: s_mov_b32 s6, s4 +; UNROLL3-NEXT: s_mov_b32 s7, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v2, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v3, s5 +; UNROLL3-NEXT: v_mov_b32_e32 v4, s6 +; UNROLL3-NEXT: v_mov_b32_e32 v5, s7 +; UNROLL3-NEXT: s_mov_b64 s[4:5], 0 +; UNROLL3-NEXT: .p2align 6 +; UNROLL3-NEXT: .LBB11_1: ; %static-memset-expansion-main-body +; UNROLL3-NEXT: ; =>This Inner Loop Header: Depth=1 +; UNROLL3-NEXT: v_add_co_u32 v6, vcc_lo, v0, s4 +; UNROLL3-NEXT: s_add_u32 s4, s4, 48 +; UNROLL3-NEXT: v_add_co_ci_u32_e64 v7, null, s5, v1, vcc_lo +; UNROLL3-NEXT: s_addc_u32 s5, s5, 0 +; UNROLL3-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:16 +; UNROLL3-NEXT: global_store_dwordx4 v[6:7], v[2:5], off +; UNROLL3-NEXT: v_cmp_gt_u64_e64 s6, 0x7e0, s[4:5] +; UNROLL3-NEXT: global_store_dwordx4 v[6:7], v[2:5], off offset:32 +; UNROLL3-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; UNROLL3-NEXT: s_cbranch_vccnz .LBB11_1 +; UNROLL3-NEXT: ; %bb.2: ; %static-memset-post-expansion +; UNROLL3-NEXT: s_mov_b32 s4, 0x41414141 +; UNROLL3-NEXT: s_mov_b32 s5, s4 +; UNROLL3-NEXT: s_mov_b32 s6, s4 +; UNROLL3-NEXT: s_mov_b32 s7, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v2, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v3, s5 +; UNROLL3-NEXT: v_mov_b32_e32 v4, s6 +; UNROLL3-NEXT: v_mov_b32_e32 v5, s7 +; UNROLL3-NEXT: global_store_dwordx4 v[0:1], v[2:5], off offset:2016 +; UNROLL3-NEXT: global_store_dwordx4 v[0:1], v[2:5], off offset:2032 +; UNROLL3-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull %dst, i8 65, i64 2048, i1 false) + ret void +} + +define void @memset_p3_sz2048(ptr addrspace(3) %dst) { +; CHECK-LABEL: memset_p3_sz2048: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s4, 0x41414141 +; CHECK-NEXT: s_mov_b32 s5, s4 +; CHECK-NEXT: s_mov_b32 s6, s4 +; CHECK-NEXT: s_mov_b32 s7, s4 +; CHECK-NEXT: v_mov_b32_e32 v1, s4 +; CHECK-NEXT: v_mov_b32_e32 v2, s5 +; CHECK-NEXT: v_mov_b32_e32 v3, s6 +; CHECK-NEXT: v_mov_b32_e32 v4, s7 +; CHECK-NEXT: s_mov_b64 s[4:5], 0 +; CHECK-NEXT: s_inst_prefetch 0x1 +; CHECK-NEXT: .p2align 6 +; CHECK-NEXT: .LBB12_1: ; %static-memset-expansion-main-body +; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: s_add_u32 s4, s4, 0x100 +; CHECK-NEXT: s_addc_u32 s5, s5, 0 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:240 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:224 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:208 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:192 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:176 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:160 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:144 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:128 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:112 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:96 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:80 +; CHECK-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5] +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:64 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:48 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:32 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] offset:16 +; CHECK-NEXT: ds_write_b128 v0, v[1:4] +; CHECK-NEXT: v_add_nc_u32_e32 v0, 0x100, v0 +; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; CHECK-NEXT: s_cbranch_vccnz .LBB12_1 +; CHECK-NEXT: ; %bb.2: ; %static-memset-post-expansion +; CHECK-NEXT: s_inst_prefetch 0x2 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +; +; ALIGNED-LABEL: memset_p3_sz2048: +; ALIGNED: ; %bb.0: ; %entry +; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; ALIGNED-NEXT: v_mov_b32_e32 v1, 0x41 +; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 +; ALIGNED-NEXT: .LBB12_1: ; %static-memset-expansion-main-body +; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1 +; ALIGNED-NEXT: s_add_u32 s4, s4, 0x100 +; ALIGNED-NEXT: s_addc_u32 s5, s5, 0 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:255 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:254 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:253 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:252 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:251 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:250 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:249 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:248 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:247 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:246 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:245 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:244 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:243 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:242 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:241 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:240 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:239 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:238 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:237 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:236 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:235 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:234 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:233 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:232 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:231 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:230 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:229 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:228 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:227 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:226 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:225 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:224 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:223 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:222 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:221 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:220 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:219 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:218 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:217 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:216 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:215 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:214 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:213 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:212 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:211 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:210 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:209 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:208 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:207 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:206 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:205 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:204 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:203 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:202 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:201 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:200 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:199 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:198 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:197 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:196 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:195 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:194 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:193 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:192 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:191 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:190 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:189 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:188 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:187 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:186 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:185 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:184 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:183 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:182 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:181 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:180 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:179 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:178 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:177 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:176 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:175 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:174 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:173 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:172 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:171 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:170 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:169 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:168 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:167 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:166 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:165 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:164 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:163 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:162 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:161 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:160 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:159 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:158 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:157 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:156 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:155 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:154 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:153 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:152 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:151 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:150 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:149 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:148 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:147 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:146 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:145 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:144 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:143 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:142 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:141 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:140 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:139 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:138 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:137 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:136 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:135 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:134 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:133 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:132 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:131 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:130 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:129 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:128 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:127 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:126 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:125 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:124 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:123 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:122 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:121 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:120 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:119 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:118 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:117 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:116 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:115 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:114 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:113 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:112 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:111 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:110 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:109 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:108 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:107 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:106 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:105 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:104 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:103 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:102 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:101 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:100 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:99 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:98 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:97 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:96 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:87 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:86 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:85 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:84 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:81 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:80 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:83 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:82 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:95 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:94 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:93 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:92 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:89 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:88 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:91 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:90 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:79 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:78 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:77 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:76 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:75 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:74 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:73 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:72 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:71 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:70 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:69 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:68 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:67 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:66 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:65 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:64 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:63 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:62 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:61 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:60 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:59 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:58 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:57 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:56 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:55 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:54 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:53 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:52 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:51 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:50 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:49 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:48 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:47 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:46 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:45 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:44 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:43 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:42 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:41 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:40 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:39 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:38 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:37 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:36 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:35 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:34 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:33 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:32 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:31 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:30 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:29 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:28 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:27 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:26 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:25 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:24 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:23 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:22 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:21 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:20 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:19 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:18 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:17 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:16 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:15 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:14 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:13 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:12 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:11 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:10 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:9 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:8 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:7 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:6 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:5 +; ALIGNED-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5] +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:4 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:3 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:2 +; ALIGNED-NEXT: ds_write_b8 v0, v1 offset:1 +; ALIGNED-NEXT: ds_write_b8 v0, v1 +; ALIGNED-NEXT: v_add_nc_u32_e32 v0, 0x100, v0 +; ALIGNED-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; ALIGNED-NEXT: s_cbranch_vccnz .LBB12_1 +; ALIGNED-NEXT: ; %bb.2: ; %static-memset-post-expansion +; ALIGNED-NEXT: s_waitcnt lgkmcnt(0) +; ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; UNROLL3-LABEL: memset_p3_sz2048: +; UNROLL3: ; %bb.0: ; %entry +; UNROLL3-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; UNROLL3-NEXT: s_mov_b32 s4, 0x41414141 +; UNROLL3-NEXT: v_mov_b32_e32 v5, v0 +; UNROLL3-NEXT: s_mov_b32 s5, s4 +; UNROLL3-NEXT: s_mov_b32 s6, s4 +; UNROLL3-NEXT: s_mov_b32 s7, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v1, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v2, s5 +; UNROLL3-NEXT: v_mov_b32_e32 v3, s6 +; UNROLL3-NEXT: v_mov_b32_e32 v4, s7 +; UNROLL3-NEXT: s_mov_b64 s[4:5], 0 +; UNROLL3-NEXT: .LBB12_1: ; %static-memset-expansion-main-body +; UNROLL3-NEXT: ; =>This Inner Loop Header: Depth=1 +; UNROLL3-NEXT: s_add_u32 s4, s4, 48 +; UNROLL3-NEXT: s_addc_u32 s5, s5, 0 +; UNROLL3-NEXT: ds_write_b128 v5, v[1:4] offset:16 +; UNROLL3-NEXT: ds_write_b128 v5, v[1:4] +; UNROLL3-NEXT: ds_write_b128 v5, v[1:4] offset:32 +; UNROLL3-NEXT: v_cmp_gt_u64_e64 s6, 0x7e0, s[4:5] +; UNROLL3-NEXT: v_add_nc_u32_e32 v5, 48, v5 +; UNROLL3-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; UNROLL3-NEXT: s_cbranch_vccnz .LBB12_1 +; UNROLL3-NEXT: ; %bb.2: ; %static-memset-post-expansion +; UNROLL3-NEXT: s_mov_b32 s4, 0x41414141 +; UNROLL3-NEXT: s_mov_b32 s5, s4 +; UNROLL3-NEXT: s_mov_b32 s6, s4 +; UNROLL3-NEXT: s_mov_b32 s7, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v1, s4 +; UNROLL3-NEXT: v_mov_b32_e32 v2, s5 +; UNROLL3-NEXT: v_mov_b32_e32 v3, s6 +; UNROLL3-NEXT: v_mov_b32_e32 v4, s7 +; UNROLL3-NEXT: ds_write_b128 v0, v[1:4] offset:2016 +; UNROLL3-NEXT: ds_write_b128 v0, v[1:4] offset:2032 +; UNROLL3-NEXT: s_waitcnt lgkmcnt(0) +; UNROLL3-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p3.i64(ptr addrspace(3) noundef nonnull %dst, i8 65, i64 2048, i1 false) + ret void +} + +define void @memset_p5_sz2048(ptr addrspace(5) %dst) { +; CHECK-LABEL: memset_p5_sz2048: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v1, 0x41414141 +; CHECK-NEXT: s_mov_b64 s[4:5], 0 +; CHECK-NEXT: .LBB13_1: ; %static-memset-expansion-main-body +; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: s_add_u32 s4, s4, 0x100 +; CHECK-NEXT: s_addc_u32 s5, s5, 0 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:252 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:248 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:244 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:240 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:236 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:232 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:228 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:224 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:220 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:216 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:212 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:208 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:204 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:200 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:196 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:192 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:188 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:184 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:180 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:176 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:172 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:168 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:164 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:160 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:156 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:152 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:148 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:144 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:140 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:136 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:132 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:128 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:108 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:104 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:100 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:96 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:92 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:88 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:84 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:80 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:76 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:72 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:68 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:64 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20 +; CHECK-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5] +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4 +; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; CHECK-NEXT: v_add_nc_u32_e32 v0, 0x100, v0 +; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; CHECK-NEXT: s_cbranch_vccnz .LBB13_1 +; CHECK-NEXT: ; %bb.2: ; %static-memset-post-expansion +; CHECK-NEXT: s_setpc_b64 s[30:31] +; +; ALIGNED-LABEL: memset_p5_sz2048: +; ALIGNED: ; %bb.0: ; %entry +; ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; ALIGNED-NEXT: v_mov_b32_e32 v1, 0x41 +; ALIGNED-NEXT: s_mov_b64 s[4:5], 0 +; ALIGNED-NEXT: .LBB13_1: ; %static-memset-expansion-main-body +; ALIGNED-NEXT: ; =>This Inner Loop Header: Depth=1 +; ALIGNED-NEXT: s_add_u32 s4, s4, 0x100 +; ALIGNED-NEXT: s_addc_u32 s5, s5, 0 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:255 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:254 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:253 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:252 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:251 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:250 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:249 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:248 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:247 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:246 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:245 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:244 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:243 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:242 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:241 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:240 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:239 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:238 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:237 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:236 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:235 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:234 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:233 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:232 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:231 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:230 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:229 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:228 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:227 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:226 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:225 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:224 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:223 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:222 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:221 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:220 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:219 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:218 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:217 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:216 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:215 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:214 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:213 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:212 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:211 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:210 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:209 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:208 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:207 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:206 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:205 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:204 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:203 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:202 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:201 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:200 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:199 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:198 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:197 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:196 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:195 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:194 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:193 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:192 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:191 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:190 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:189 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:188 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:187 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:186 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:185 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:184 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:183 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:182 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:181 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:180 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:179 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:178 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:177 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:176 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:175 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:174 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:173 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:172 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:171 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:170 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:169 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:168 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:167 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:166 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:165 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:164 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:163 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:162 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:161 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:160 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:159 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:158 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:157 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:156 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:155 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:154 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:153 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:152 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:151 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:150 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:149 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:148 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:147 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:146 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:145 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:144 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:143 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:142 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:141 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:140 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:139 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:138 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:137 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:136 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:135 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:134 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:133 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:132 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:131 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:130 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:129 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:128 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:127 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:126 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:125 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:124 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:123 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:122 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:121 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:120 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:119 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:118 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:117 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:116 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:115 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:114 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:113 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:112 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:111 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:110 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:109 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:108 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:107 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:106 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:105 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:104 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:103 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:102 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:101 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:100 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:99 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:98 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:97 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:96 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:95 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:94 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:93 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:92 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:91 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:90 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:89 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:88 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:87 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:86 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:85 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:84 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:83 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:82 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:81 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:80 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:79 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:78 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:77 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:76 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:75 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:74 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:73 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:72 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:71 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:70 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:69 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:68 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:67 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:66 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:65 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:64 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:63 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:62 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:61 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:60 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:59 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:58 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:57 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:56 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:55 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:54 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:53 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:52 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:51 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:50 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:49 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:48 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:47 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:46 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:45 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:44 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:43 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:42 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:41 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:40 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:39 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:38 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:37 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:36 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:35 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:34 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:33 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:32 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:31 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:30 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:29 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:28 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:27 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:26 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:25 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:24 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:23 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:22 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:21 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:20 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:19 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:18 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:17 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:16 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:15 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:14 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:13 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:12 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:11 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:10 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:9 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:8 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:7 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:6 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:5 +; ALIGNED-NEXT: v_cmp_gt_u64_e64 s6, 0x800, s[4:5] +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:4 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:3 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:2 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen offset:1 +; ALIGNED-NEXT: buffer_store_byte v1, v0, s[0:3], 0 offen +; ALIGNED-NEXT: v_add_nc_u32_e32 v0, 0x100, v0 +; ALIGNED-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; ALIGNED-NEXT: s_cbranch_vccnz .LBB13_1 +; ALIGNED-NEXT: ; %bb.2: ; %static-memset-post-expansion +; ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; UNROLL3-LABEL: memset_p5_sz2048: +; UNROLL3: ; %bb.0: ; %entry +; UNROLL3-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; UNROLL3-NEXT: v_mov_b32_e32 v1, 0x41414141 +; UNROLL3-NEXT: v_mov_b32_e32 v2, v0 +; UNROLL3-NEXT: s_mov_b64 s[4:5], 0 +; UNROLL3-NEXT: .p2align 6 +; UNROLL3-NEXT: .LBB13_1: ; %static-memset-expansion-main-body +; UNROLL3-NEXT: ; =>This Inner Loop Header: Depth=1 +; UNROLL3-NEXT: s_add_u32 s4, s4, 48 +; UNROLL3-NEXT: s_addc_u32 s5, s5, 0 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:44 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:40 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:36 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:32 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:28 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:24 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:20 +; UNROLL3-NEXT: v_cmp_gt_u64_e64 s6, 0x7e0, s[4:5] +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:16 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:12 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:8 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen offset:4 +; UNROLL3-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; UNROLL3-NEXT: v_add_nc_u32_e32 v2, 48, v2 +; UNROLL3-NEXT: s_and_b32 vcc_lo, exec_lo, s6 +; UNROLL3-NEXT: s_cbranch_vccnz .LBB13_1 +; UNROLL3-NEXT: ; %bb.2: ; %static-memset-post-expansion +; UNROLL3-NEXT: v_mov_b32_e32 v1, 0x41414141 +; UNROLL3-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:2028 +; UNROLL3-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:2024 +; UNROLL3-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:2020 +; UNROLL3-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:2016 +; UNROLL3-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:2044 +; UNROLL3-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:2040 +; UNROLL3-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:2036 +; UNROLL3-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:2032 +; UNROLL3-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p5.i64(ptr addrspace(5) noundef nonnull %dst, i8 65, i64 2048, i1 false) + ret void +} + declare void @llvm.memcpy.p0.p0.i64(ptr addrspace(0) noalias nocapture writeonly, ptr addrspace(0) noalias nocapture readonly, i64, i1 immarg) #2 declare void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noalias nocapture writeonly, ptr addrspace(1) noalias nocapture readonly, i64, i1 immarg) #2 @@ -15989,4 +17599,10 @@ declare void @llvm.memmove.p5.p5.i64(ptr addrspace(5) nocapture writeonly, ptr a declare void @llvm.memmove.p0.p5.i64(ptr addrspace(0) nocapture writeonly, ptr addrspace(5) nocapture readonly, i64, i1 immarg) #2 +declare void @llvm.memset.p0.i64(ptr addrspace(0) nocapture writeonly, i8, i64, i1 immarg) #3 +declare void @llvm.memset.p1.i64(ptr addrspace(1) nocapture writeonly, i8, i64, i1 immarg) #3 +declare void @llvm.memset.p3.i64(ptr addrspace(3) nocapture writeonly, i8, i64, i1 immarg) #3 +declare void @llvm.memset.p5.i64(ptr addrspace(5) nocapture writeonly, i8, i64, i1 immarg) #3 + attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) } +attributes #3 = { nocallback nofree nounwind willreturn memory(argmem: write) } diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll index b7971a024cc38..15fb5e756d058 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll @@ -104,10 +104,10 @@ define float @struct_buffer_atomic_add_v2f16_ret(<2 x half> %val, <4 x i32> inre ; GFX1250: ; %bb.0: ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: scratch_store_b32 off, v2, s32 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v2, s32 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: v_mov_b32_e32 v2, v1 -; GFX1250-NEXT: scratch_load_b32 v1, off, s32 ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v1, off, s32 nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_mov_b32 s4, s3 ; GFX1250-NEXT: s_mov_b32 s5, s2 ; GFX1250-NEXT: s_mov_b32 s6, s1 @@ -133,10 +133,10 @@ define void @struct_buffer_atomic_add_v2f16_noret(<2 x half> %val, <4 x i32> inr ; GFX1250: ; %bb.0: ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: scratch_store_b32 off, v2, s32 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v2, s32 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: v_mov_b32_e32 v2, v1 -; GFX1250-NEXT: scratch_load_b32 v1, off, s32 ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v1, off, s32 nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_mov_b32 s4, s3 ; GFX1250-NEXT: s_mov_b32 s5, s2 ; GFX1250-NEXT: s_mov_b32 s6, s1 diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll index 0b40c81af414d..14d2e4ca5f2c3 100644 --- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-lds-dma-volatile-and-nontemporal.ll @@ -340,18 +340,16 @@ define amdgpu_ps void @load_to_lds_p7_dword_volatile(ptr addrspace(7) inreg %gpt define amdgpu_ps void @load_to_lds_p7_dword_nontemporal(ptr addrspace(7) inreg %gptr, i32 %off, ptr addrspace(3) inreg %lptr) { ; GFX90A-LABEL: load_to_lds_p7_dword_nontemporal: ; GFX90A: ; %bb.0: -; GFX90A-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX90A-NEXT: s_mov_b32 m0, s5 -; GFX90A-NEXT: s_nop 0 +; GFX90A-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX90A-NEXT: buffer_load_dword v0, s[0:3], 0 offen glc slc lds ; GFX90A-NEXT: buffer_load_dword v0, s[0:3], 0 offen offset:512 lds ; GFX90A-NEXT: s_endpgm ; ; GFX942-LABEL: load_to_lds_p7_dword_nontemporal: ; GFX942: ; %bb.0: -; GFX942-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX942-NEXT: s_mov_b32 m0, s5 -; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_add_u32_e32 v0, s4, v0 ; GFX942-NEXT: buffer_load_dword v0, s[0:3], 0 offen nt lds ; GFX942-NEXT: buffer_load_dword v0, s[0:3], 0 offen offset:512 lds ; GFX942-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll new file mode 100644 index 0000000000000..ab12e3c19992d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-non-volatile.ll @@ -0,0 +1,365 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX12-CU,GFX12-CU-DAGISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+cumode < %s | FileCheck --check-prefixes=GFX12-CU,GFX12-CU-GISEL %s + +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-DAGISEL %s +; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-GISEL %s + +define void @flat_i32_nonatomic(ptr addrspace(0) %in, ptr addrspace(0) %out) { +; GFX12-CU-LABEL: flat_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: flat_load_b32 v0, v[0:1] +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: flat_store_b32 v[2:3], v0 +; GFX12-CU-NEXT: s_wait_dscnt 0x0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: flat_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: flat_load_b32 v0, v[0:1] +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: flat_store_b32 v[2:3], v0 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(0) %in + store i32 %val, ptr addrspace(0) %out + ret void +} + +define i32 @md_invariant__flat_i32_nonatomic(ptr addrspace(0) %in, ptr addrspace(0) %out) { +; GFX12-CU-LABEL: md_invariant__flat_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: flat_load_b32 v0, v[0:1] +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: md_invariant__flat_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: flat_load_b32 v0, v[0:1] nv +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(0) %in, !invariant.load !0 + ret i32 %val +} + +define void @global_i32_nonatomic(ptr addrspace(1) %in, ptr addrspace(1) %out) { +; GFX12-CU-LABEL: global_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: global_load_b32 v0, v[0:1], off +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: global_store_b32 v[2:3], v0, off +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: global_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: global_load_b32 v0, v[0:1], off +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: global_store_b32 v[2:3], v0, off +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(1) %in + store i32 %val, ptr addrspace(1) %out + ret void +} + +define i32 @md_invariant__global_i32_nonatomic(ptr addrspace(1) %in, ptr addrspace(1) %out) { +; GFX12-CU-LABEL: md_invariant__global_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: global_load_b32 v0, v[0:1], off +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: md_invariant__global_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: global_load_b32 v0, v[0:1], off nv +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(1) %in, !invariant.load !0 + ret i32 %val +} + +define i32 @scalar_i32_nonatomic(ptr addrspace(4) inreg %in) { +; GFX12-CU-LABEL: scalar_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: s_load_b32 s0, s[0:1], 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: scalar_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: s_load_b32 s0, s[0:1], 0x0 nv +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(4) %in + ret i32 %val +} + +define i32 @md_invariant__scalar_i32_nonatomic(ptr addrspace(4) inreg %in) { +; GFX12-CU-LABEL: md_invariant__scalar_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: s_load_b32 s0, s[0:1], 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: md_invariant__scalar_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: s_load_b32 s0, s[0:1], 0x0 nv +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(4) %in, !invariant.load !0 + ret i32 %val +} + +define void @scratch_i32_nonatomic(ptr addrspace(5) %in, ptr addrspace(5) %out) { +; GFX12-CU-LABEL: scratch_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: scratch_load_b32 v0, v0, off +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: scratch_store_b32 v1, v0, off +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: scratch_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: scratch_load_b32 v0, v0, off +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: scratch_store_b32 v1, v0, off +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(5) %in + store i32 %val, ptr addrspace(5) %out + ret void +} + +define i32 @md_invariant__scratch_i32_nonatomic(ptr addrspace(5) %in, ptr addrspace(5) %out) { +; GFX12-CU-LABEL: md_invariant__scratch_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: scratch_load_b32 v0, v0, off +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: md_invariant__scratch_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: scratch_load_b32 v0, v0, off nv +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(5) %in, !invariant.load !0 + ret i32 %val +} + +define i32 @scalar32_i32_nonatomic(ptr addrspace(6) inreg %in) { +; GFX12-CU-LABEL: scalar32_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: s_mov_b32 s1, 0 +; GFX12-CU-NEXT: s_load_b32 s0, s[0:1], 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: scalar32_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: s_mov_b32 s1, 0 +; GFX1250-NEXT: s_load_b32 s0, s[0:1], 0x0 nv +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(6) %in + ret i32 %val +} + +define i32 @md_invariant__scalar32_i32_nonatomic(ptr addrspace(6) inreg %in) { +; GFX12-CU-LABEL: md_invariant__scalar32_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: s_mov_b32 s1, 0 +; GFX12-CU-NEXT: s_load_b32 s0, s[0:1], 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: md_invariant__scalar32_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: s_mov_b32 s1, 0 +; GFX1250-NEXT: s_load_b32 s0, s[0:1], 0x0 nv +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_mov_b32_e32 v0, s0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(6) %in, !invariant.load !0 + ret i32 %val +} + +define void @buffer_i32_nonatomic(ptr addrspace(7) inreg %in, ptr addrspace(7) inreg %out) { +; GFX12-CU-DAGISEL-LABEL: buffer_i32_nonatomic: +; GFX12-CU-DAGISEL: ; %bb.0: ; %entry +; GFX12-CU-DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-DAGISEL-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-DAGISEL-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-DAGISEL-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-DAGISEL-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-DAGISEL-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s21 +; GFX12-CU-DAGISEL-NEXT: s_mov_b32 s7, s20 +; GFX12-CU-DAGISEL-NEXT: s_mov_b32 s6, s19 +; GFX12-CU-DAGISEL-NEXT: s_mov_b32 s5, s18 +; GFX12-CU-DAGISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen +; GFX12-CU-DAGISEL-NEXT: s_mov_b32 s4, s17 +; GFX12-CU-DAGISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-DAGISEL-NEXT: buffer_store_b32 v0, v1, s[4:7], null offen +; GFX12-CU-DAGISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-CU-GISEL-LABEL: buffer_i32_nonatomic: +; GFX12-CU-GISEL: ; %bb.0: ; %entry +; GFX12-CU-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-GISEL-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-GISEL-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-GISEL-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-GISEL-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s21 +; GFX12-CU-GISEL-NEXT: s_mov_b32 s4, s17 +; GFX12-CU-GISEL-NEXT: s_mov_b32 s5, s18 +; GFX12-CU-GISEL-NEXT: s_mov_b32 s6, s19 +; GFX12-CU-GISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen +; GFX12-CU-GISEL-NEXT: s_mov_b32 s7, s20 +; GFX12-CU-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-GISEL-NEXT: buffer_store_b32 v0, v1, s[4:7], null offen +; GFX12-CU-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-DAGISEL-LABEL: buffer_i32_nonatomic: +; GFX1250-DAGISEL: ; %bb.0: ; %entry +; GFX1250-DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s21 +; GFX1250-DAGISEL-NEXT: s_mov_b32 s7, s20 +; GFX1250-DAGISEL-NEXT: s_mov_b32 s6, s19 +; GFX1250-DAGISEL-NEXT: s_mov_b32 s5, s18 +; GFX1250-DAGISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen +; GFX1250-DAGISEL-NEXT: s_mov_b32 s4, s17 +; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1250-DAGISEL-NEXT: buffer_store_b32 v0, v1, s[4:7], null offen +; GFX1250-DAGISEL-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-GISEL-LABEL: buffer_i32_nonatomic: +; GFX1250-GISEL: ; %bb.0: ; %entry +; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s21 +; GFX1250-GISEL-NEXT: s_mov_b32 s4, s17 +; GFX1250-GISEL-NEXT: s_mov_b32 s5, s18 +; GFX1250-GISEL-NEXT: s_mov_b32 s6, s19 +; GFX1250-GISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen +; GFX1250-GISEL-NEXT: s_mov_b32 s7, s20 +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1250-GISEL-NEXT: buffer_store_b32 v0, v1, s[4:7], null offen +; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(7) %in + store i32 %val, ptr addrspace(7) %out + ret void +} + +define i32 @md_invariant__buffer_i32_nonatomic(ptr addrspace(7) inreg %in, ptr addrspace(7) inreg %out) { +; GFX12-CU-LABEL: md_invariant__buffer_i32_nonatomic: +; GFX12-CU: ; %bb.0: ; %entry +; GFX12-CU-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-CU-NEXT: s_wait_expcnt 0x0 +; GFX12-CU-NEXT: s_wait_samplecnt 0x0 +; GFX12-CU-NEXT: s_wait_bvhcnt 0x0 +; GFX12-CU-NEXT: s_wait_kmcnt 0x0 +; GFX12-CU-NEXT: v_mov_b32_e32 v0, s16 +; GFX12-CU-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen +; GFX12-CU-NEXT: s_wait_loadcnt 0x0 +; GFX12-CU-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: md_invariant__buffer_i32_nonatomic: +; GFX1250: ; %bb.0: ; %entry +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_mov_b32_e32 v0, s16 +; GFX1250-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen nv +; GFX1250-NEXT: s_wait_loadcnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] +entry: + %val = load i32, ptr addrspace(7) %in, !invariant.load !0 + ret i32 %val +} + +!0 = !{} diff --git a/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll b/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll new file mode 100644 index 0000000000000..990a986ffab75 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/memset-param-combinations.ll @@ -0,0 +1,1896 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 %s -o - | FileCheck -check-prefixes=GFX942,GFX942-SDAG %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 %s -o - | FileCheck -check-prefixes=GFX942,GFX942-GISEL %s + + +define void @memset_p0_varsize_align_4_varsetval(ptr addrspace(0) align 4 %dst, i8 %setval, i64 %size) { +; GFX942-SDAG-LABEL: memset_p0_varsize_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v3 +; GFX942-SDAG-NEXT: v_and_b32_e32 v12, -16, v10 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v4 +; GFX942-SDAG-NEXT: v_and_b32_e32 v8, 15, v10 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB0_3 +; GFX942-SDAG-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-SDAG-NEXT: s_mov_b32 s4, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v4, v2, v2, s4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB0_2: ; %dynamic-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[14:15], v[0:1], 0, s[4:5] +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 16 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[12:13] +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[14:15], v[4:7] +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB0_2 +; GFX942-SDAG-NEXT: .LBB0_3: ; %Flow4 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB0_6 +; GFX942-SDAG-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-SDAG-NEXT: v_and_b32_e32 v10, -16, v10 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[10:11] +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB0_5: ; %dynamic-memset-expansion-residual-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[4:5] +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 1 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9] +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: flat_store_byte v[4:5], v2 +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB0_5 +; GFX942-SDAG-NEXT: .LBB0_6: ; %Flow2 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p0_varsize_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_mov_b32_e32 v10, v3 +; GFX942-GISEL-NEXT: v_and_b32_e32 v8, 15, v10 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v11, v4 +; GFX942-GISEL-NEXT: v_sub_co_u32_e32 v12, vcc, v10, v8 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v9, 0 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_subbrev_co_u32_e32 v13, vcc, 0, v11, vcc +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB0_3 +; GFX942-GISEL-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v2 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v3, 8, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v3, 24, v3 +; GFX942-GISEL-NEXT: v_or3_b32 v4, v4, v5, v3 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[0:1] +; GFX942-GISEL-NEXT: .LBB0_2: ; %dynamic-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v16, vcc, v0, v14 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v17, vcc, v1, v15, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, 16, v14 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[16:17], v[4:7] +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[14:15], v[12:13] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB0_2 +; GFX942-GISEL-NEXT: .LBB0_3: ; %Flow4 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB0_6 +; GFX942-GISEL-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-GISEL-NEXT: v_lshrrev_b64 v[4:5], 4, v[10:11] +; GFX942-GISEL-NEXT: v_lshl_add_u64 v[0:1], v[4:5], 4, v[0:1] +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] +; GFX942-GISEL-NEXT: .LBB0_5: ; %dynamic-memset-expansion-residual-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, v0, v4 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v5, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v4, vcc, 1, v4 +; GFX942-GISEL-NEXT: flat_store_byte v[6:7], v2 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[8:9] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB0_5 +; GFX942-GISEL-NEXT: .LBB0_6: ; %Flow2 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p0.i64(ptr addrspace(0) noundef nonnull align 4 %dst, i8 %setval, i64 %size, i1 false) + ret void +} + +define void @memset_p1_varsize_align_4_varsetval(ptr addrspace(1) align 4 %dst, i8 %setval, i64 %size) { +; GFX942-SDAG-LABEL: memset_p1_varsize_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v3 +; GFX942-SDAG-NEXT: v_and_b32_e32 v12, -16, v10 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v4 +; GFX942-SDAG-NEXT: v_and_b32_e32 v8, 15, v10 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB1_3 +; GFX942-SDAG-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-SDAG-NEXT: s_mov_b32 s4, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v4, v2, v2, s4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB1_2: ; %dynamic-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[14:15], v[0:1], 0, s[4:5] +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 16 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[12:13] +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: global_store_dwordx4 v[14:15], v[4:7], off +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB1_2 +; GFX942-SDAG-NEXT: .LBB1_3: ; %Flow4 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB1_6 +; GFX942-SDAG-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-SDAG-NEXT: v_and_b32_e32 v10, -16, v10 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[10:11] +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB1_5: ; %dynamic-memset-expansion-residual-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[4:5] +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 1 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9] +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: global_store_byte v[4:5], v2, off +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB1_5 +; GFX942-SDAG-NEXT: .LBB1_6: ; %Flow2 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p1_varsize_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_mov_b32_e32 v10, v3 +; GFX942-GISEL-NEXT: v_and_b32_e32 v8, 15, v10 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v11, v4 +; GFX942-GISEL-NEXT: v_sub_co_u32_e32 v12, vcc, v10, v8 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v9, 0 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_subbrev_co_u32_e32 v13, vcc, 0, v11, vcc +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB1_3 +; GFX942-GISEL-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v2 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v3, 8, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v3, 24, v3 +; GFX942-GISEL-NEXT: v_or3_b32 v4, v4, v5, v3 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[0:1] +; GFX942-GISEL-NEXT: .LBB1_2: ; %dynamic-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v16, vcc, v0, v14 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v17, vcc, v1, v15, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, 16, v14 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[16:17], v[4:7], off +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[14:15], v[12:13] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB1_2 +; GFX942-GISEL-NEXT: .LBB1_3: ; %Flow4 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB1_6 +; GFX942-GISEL-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-GISEL-NEXT: v_lshrrev_b64 v[4:5], 4, v[10:11] +; GFX942-GISEL-NEXT: v_lshl_add_u64 v[0:1], v[4:5], 4, v[0:1] +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] +; GFX942-GISEL-NEXT: .LBB1_5: ; %dynamic-memset-expansion-residual-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, v0, v4 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v5, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v4, vcc, 1, v4 +; GFX942-GISEL-NEXT: global_store_byte v[6:7], v2, off +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[8:9] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB1_5 +; GFX942-GISEL-NEXT: .LBB1_6: ; %Flow2 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 4 %dst, i8 %setval, i64 %size, i1 false) + ret void +} + +define void @memset_p3_varsize_align_4_varsetval(ptr addrspace(3) align 4 %dst, i8 %setval, i64 %size) { +; GFX942-SDAG-LABEL: memset_p3_varsize_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v3 +; GFX942-SDAG-NEXT: v_and_b32_e32 v4, -16, v2 +; GFX942-SDAG-NEXT: v_and_b32_e32 v10, 15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB2_3 +; GFX942-SDAG-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-SDAG-NEXT: s_mov_b32 s4, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v6, v1, v1, s4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v6 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v6 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v6 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v0 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB2_2: ; %dynamic-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 16 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[4:5] +; GFX942-SDAG-NEXT: ds_write2_b32 v9, v8, v7 offset0:2 offset1:3 +; GFX942-SDAG-NEXT: ds_write2_b32 v9, v6, v3 offset1:1 +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: v_add_u32_e32 v9, 16, v9 +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB2_2 +; GFX942-SDAG-NEXT: .LBB2_3: ; %Flow7 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB2_6 +; GFX942-SDAG-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-SDAG-NEXT: v_and_b32_e32 v2, -16, v2 +; GFX942-SDAG-NEXT: v_add_u32_e32 v0, v0, v2 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB2_5: ; %dynamic-memset-expansion-residual-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 1 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[10:11] +; GFX942-SDAG-NEXT: ds_write_b8 v0, v1 +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 1, v0 +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB2_5 +; GFX942-SDAG-NEXT: .LBB2_6: ; %Flow5 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p3_varsize_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v4, 15, v2 +; GFX942-GISEL-NEXT: v_sub_co_u32_e32 v6, vcc, v2, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, 0 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_subbrev_co_u32_e32 v7, vcc, 0, v3, vcc +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB2_3 +; GFX942-GISEL-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-GISEL-NEXT: v_and_b32_e32 v8, 0xff, v1 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v9, v8, 8, v8 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v10, 16, v8 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v8, 24, v8 +; GFX942-GISEL-NEXT: v_or3_b32 v8, v9, v10, v8 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v9, v8 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v10, v8 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v11, v8 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v14, v0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[0:1] +; GFX942-GISEL-NEXT: .LBB2_2: ; %dynamic-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 16, v12 +; GFX942-GISEL-NEXT: ds_write2_b64 v14, v[8:9], v[10:11] offset1:1 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: v_add_u32_e32 v14, 16, v14 +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB2_2 +; GFX942-GISEL-NEXT: .LBB2_3: ; %Flow7 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB2_6 +; GFX942-GISEL-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-GISEL-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3] +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 4, v2 +; GFX942-GISEL-NEXT: v_add_u32_e32 v0, v0, v2 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-GISEL-NEXT: .LBB2_5: ; %dynamic-memset-expansion-residual-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 1, v2 +; GFX942-GISEL-NEXT: ds_write_b8 v0, v1 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[4:5] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 1, v0 +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB2_5 +; GFX942-GISEL-NEXT: .LBB2_6: ; %Flow5 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p3.i64(ptr addrspace(3) noundef nonnull align 4 %dst, i8 %setval, i64 %size, i1 false) + ret void +} + +define void @memset_p5_varsize_align_4_varsetval(ptr addrspace(5) align 4 %dst, i8 %setval, i64 %size) { +; GFX942-SDAG-LABEL: memset_p5_varsize_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v3 +; GFX942-SDAG-NEXT: v_and_b32_e32 v4, -16, v2 +; GFX942-SDAG-NEXT: v_and_b32_e32 v10, 15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB3_3 +; GFX942-SDAG-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-SDAG-NEXT: s_mov_b32 s4, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v6, v1, v1, s4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v6 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v6 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v6 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v0 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB3_2: ; %dynamic-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 16 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[4:5] +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v3, v[6:9], off +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: v_add_u32_e32 v3, 16, v3 +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB3_2 +; GFX942-SDAG-NEXT: .LBB3_3: ; %Flow7 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB3_6 +; GFX942-SDAG-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-SDAG-NEXT: v_and_b32_e32 v2, -16, v2 +; GFX942-SDAG-NEXT: v_add_u32_e32 v0, v0, v2 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB3_5: ; %dynamic-memset-expansion-residual-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 1 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[10:11] +; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 1, v0 +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB3_5 +; GFX942-SDAG-NEXT: .LBB3_6: ; %Flow5 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p5_varsize_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v8, 15, v2 +; GFX942-GISEL-NEXT: v_sub_co_u32_e32 v10, vcc, v2, v8 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v9, 0 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_subbrev_co_u32_e32 v11, vcc, 0, v3, vcc +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB3_3 +; GFX942-GISEL-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-GISEL-NEXT: v_and_b32_e32 v4, 0xff, v1 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v5, v4, 8, v4 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v4 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v4, 24, v4 +; GFX942-GISEL-NEXT: v_or3_b32 v4, v5, v6, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v14, v0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[0:1] +; GFX942-GISEL-NEXT: .LBB3_2: ; %dynamic-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 16, v12 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v14, v[4:7], off +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[10:11] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: v_add_u32_e32 v14, 16, v14 +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB3_2 +; GFX942-GISEL-NEXT: .LBB3_3: ; %Flow7 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB3_6 +; GFX942-GISEL-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-GISEL-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3] +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 4, v2 +; GFX942-GISEL-NEXT: v_add_u32_e32 v0, v0, v2 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-GISEL-NEXT: .LBB3_5: ; %dynamic-memset-expansion-residual-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 1, v2 +; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[8:9] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 1, v0 +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB3_5 +; GFX942-GISEL-NEXT: .LBB3_6: ; %Flow5 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p5.i64(ptr addrspace(5) noundef nonnull align 4 %dst, i8 %setval, i64 %size, i1 false) + ret void +} + +define void @memset_p0_sz1055_align_4_varsetval(ptr addrspace(0) align 4 %dst, i8 %setval) { +; GFX942-SDAG-LABEL: memset_p0_sz1055_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v4, v2, v2, s0 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a12, v60 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a13, v61 ; Reload Reuse +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v33, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v34, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v35, v4 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[2:3], 0x70 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0x60 +; GFX942-SDAG-NEXT: s_mov_b64 s[6:7], 0x50 +; GFX942-SDAG-NEXT: s_mov_b64 s[8:9], 0xf0 +; GFX942-SDAG-NEXT: s_mov_b64 s[10:11], 0xe0 +; GFX942-SDAG-NEXT: s_mov_b64 s[12:13], 0xd0 +; GFX942-SDAG-NEXT: s_mov_b64 s[14:15], 0xc0 +; GFX942-SDAG-NEXT: s_mov_b64 s[16:17], 0xb0 +; GFX942-SDAG-NEXT: s_mov_b64 s[18:19], 0xa0 +; GFX942-SDAG-NEXT: s_mov_b64 s[20:21], 0x90 +; GFX942-SDAG-NEXT: v_mov_b64_e32 v[36:37], 0x400 +; GFX942-SDAG-NEXT: .LBB4_1: ; %static-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[38:39], v[0:1], 0, s[0:1] +; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100 +; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[36:37] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[48:49], v[38:39], 0, s[2:3] +; GFX942-SDAG-NEXT: s_and_b64 vcc, exec, vcc +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[50:51], v[38:39], 0, s[4:5] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[52:53], v[38:39], 0, s[6:7] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[38:39], v[20:23] offset:64 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[54:55], v[38:39], 0, 48 +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[38:39], v[12:15] offset:32 +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[38:39], v[8:11] offset:16 +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[38:39], v[4:7] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[40:41], v[38:39], 0, s[8:9] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[42:43], v[38:39], 0, s[10:11] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[44:45], v[38:39], 0, s[12:13] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[46:47], v[38:39], 0, s[14:15] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[56:57], v[38:39], 0, s[16:17] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[58:59], v[38:39], 0, s[18:19] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[60:61], v[38:39], 0, s[20:21] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[38:39], v[4:7] offset:128 +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[48:49], v[32:35] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[50:51], v[28:31] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[52:53], v[24:27] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[54:55], v[16:19] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[40:41], v[32:35] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[42:43], v[28:31] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[44:45], v[24:27] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[46:47], v[20:23] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[56:57], v[16:19] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[58:59], v[12:15] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[60:61], v[8:11] +; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB4_1 +; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v4, v2, v2, s0 +; GFX942-SDAG-NEXT: v_lshlrev_b16_e32 v3, 8, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-SDAG-NEXT: v_or_b32_sdwa v3, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[0:1], v[4:7] offset:1024 +; GFX942-SDAG-NEXT: flat_store_dwordx3 v[0:1], v[4:6] offset:1040 +; GFX942-SDAG-NEXT: flat_store_short v[0:1], v3 offset:1052 +; GFX942-SDAG-NEXT: flat_store_byte v[0:1], v2 offset:1054 +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v61, a13 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v60, a12 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v59, a11 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v58, a10 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v57, a9 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v56, a8 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v47, a7 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v46, a6 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v45, a5 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v44, a4 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v43, a3 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v42, a2 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p0_sz1055_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v2 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v3, 8, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v3, 24, v3 +; GFX942-GISEL-NEXT: v_or3_b32 v4, v4, v5, v3 +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], 0x400 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1] +; GFX942-GISEL-NEXT: .LBB4_1: ; %static-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, v0, v10 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, v1, v11, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, 0x100, v10 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:16 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:32 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:48 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:64 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:80 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:96 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:112 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:128 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:144 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:160 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:176 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:192 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:208 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:224 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[12:13], v[4:7] offset:240 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc +; GFX942-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9] +; GFX942-GISEL-NEXT: s_cbranch_vccnz .LBB4_1 +; GFX942-GISEL-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v2 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v3, 8, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v3, 24, v3 +; GFX942-GISEL-NEXT: v_or3_b32 v6, v4, v5, v3 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 8 +; GFX942-GISEL-NEXT: v_lshlrev_b16_sdwa v3, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX942-GISEL-NEXT: v_or_b32_sdwa v3, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX942-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v3 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v4, 16, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v7, v6 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v8, v6 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v9, v6 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[0:1], v[6:9] offset:1024 +; GFX942-GISEL-NEXT: flat_store_dwordx3 v[0:1], v[4:6] offset:1040 +; GFX942-GISEL-NEXT: flat_store_short v[0:1], v3 offset:1052 +; GFX942-GISEL-NEXT: flat_store_byte v[0:1], v2 offset:1054 +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p0.i64(ptr addrspace(0) noundef nonnull align 4 %dst, i8 %setval, i64 1055, i1 false) + ret void +} + +define void @memset_p0_sz2048_align_4_varsetval(ptr addrspace(0) align 4 %dst, i8 %setval) { +; GFX942-SDAG-LABEL: memset_p0_sz2048_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v2, v2, v2, s0 +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a0, v40 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a1, v41 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a2, v42 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a3, v43 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a4, v44 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a5, v45 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a6, v46 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a7, v47 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a8, v56 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a9, v57 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a10, v58 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_write_b32 a11, v59 ; Reload Reuse +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v33, v2 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[2:3], 0x70 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0x60 +; GFX942-SDAG-NEXT: s_mov_b64 s[6:7], 0x50 +; GFX942-SDAG-NEXT: s_mov_b64 s[8:9], 0xf0 +; GFX942-SDAG-NEXT: s_mov_b64 s[10:11], 0xe0 +; GFX942-SDAG-NEXT: s_mov_b64 s[12:13], 0xd0 +; GFX942-SDAG-NEXT: s_mov_b64 s[14:15], 0xc0 +; GFX942-SDAG-NEXT: s_mov_b64 s[16:17], 0xb0 +; GFX942-SDAG-NEXT: s_mov_b64 s[18:19], 0xa0 +; GFX942-SDAG-NEXT: s_mov_b64 s[20:21], 0x90 +; GFX942-SDAG-NEXT: v_mov_b64_e32 v[34:35], 0x800 +; GFX942-SDAG-NEXT: .LBB5_1: ; %static-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[36:37], v[0:1], 0, s[0:1] +; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100 +; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[34:35] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[38:39], v[36:37], 0, s[2:3] +; GFX942-SDAG-NEXT: s_and_b64 vcc, exec, vcc +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[48:49], v[36:37], 0, s[4:5] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[50:51], v[36:37], 0, s[6:7] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[36:37], v[18:21] offset:64 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[52:53], v[36:37], 0, 48 +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[36:37], v[10:13] offset:32 +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[36:37], v[6:9] offset:16 +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[36:37], v[2:5] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[54:55], v[36:37], 0, s[8:9] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[40:41], v[36:37], 0, s[10:11] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[42:43], v[36:37], 0, s[12:13] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[44:45], v[36:37], 0, s[14:15] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[46:47], v[36:37], 0, s[16:17] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[56:57], v[36:37], 0, s[18:19] +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[58:59], v[36:37], 0, s[20:21] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[36:37], v[2:5] offset:128 +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[38:39], v[30:33] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[48:49], v[26:29] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[50:51], v[22:25] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[52:53], v[14:17] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[54:55], v[30:33] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[40:41], v[26:29] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[42:43], v[22:25] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[44:45], v[18:21] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[46:47], v[14:17] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[56:57], v[10:13] +; GFX942-SDAG-NEXT: flat_store_dwordx4 v[58:59], v[6:9] +; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB5_1 +; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v59, a11 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v58, a10 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v57, a9 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v56, a8 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v47, a7 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v46, a6 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v45, a5 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v44, a4 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v43, a3 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v42, a2 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v41, a1 ; Reload Reuse +; GFX942-SDAG-NEXT: v_accvgpr_read_b32 v40, a0 ; Reload Reuse +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p0_sz2048_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v3, v2, 8, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v2 +; GFX942-GISEL-NEXT: v_or3_b32 v2, v3, v4, v2 +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], 0x800 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1] +; GFX942-GISEL-NEXT: .LBB5_1: ; %static-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, v0, v8 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v11, vcc, v1, v9, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 0x100, v8 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:16 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:32 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:48 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:64 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:80 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:96 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:112 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:128 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:144 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:160 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:176 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:192 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:208 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:224 +; GFX942-GISEL-NEXT: flat_store_dwordx4 v[10:11], v[2:5] offset:240 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX942-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[6:7] +; GFX942-GISEL-NEXT: s_cbranch_vccnz .LBB5_1 +; GFX942-GISEL-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p0.i64(ptr addrspace(0) noundef nonnull align 4 %dst, i8 %setval, i64 2048, i1 false) + ret void +} + +define void @memset_p1_sz1055_align_4_varsetval(ptr addrspace(1) align 4 %dst, i8 %setval) { +; GFX942-SDAG-LABEL: memset_p1_sz1055_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v4, v2, v2, s0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v33, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v34, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v35, v4 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_mov_b64_e32 v[36:37], 0x400 +; GFX942-SDAG-NEXT: .LBB6_1: ; %static-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[38:39], v[0:1], 0, s[0:1] +; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100 +; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[36:37] +; GFX942-SDAG-NEXT: s_and_b64 vcc, exec, vcc +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[32:35], off offset:112 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[28:31], off offset:96 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[24:27], off offset:80 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[20:23], off offset:64 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[16:19], off offset:48 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[12:15], off offset:32 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[8:11], off offset:16 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[4:7], off +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[32:35], off offset:240 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[28:31], off offset:224 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[24:27], off offset:208 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[20:23], off offset:192 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[16:19], off offset:176 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[12:15], off offset:160 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[8:11], off offset:144 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[38:39], v[4:7], off offset:128 +; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB6_1 +; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v4, v2, v2, s0 +; GFX942-SDAG-NEXT: v_lshlrev_b16_e32 v3, 8, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-SDAG-NEXT: v_or_b32_sdwa v3, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX942-SDAG-NEXT: global_store_dwordx4 v[0:1], v[4:7], off offset:1024 +; GFX942-SDAG-NEXT: global_store_dwordx3 v[0:1], v[4:6], off offset:1040 +; GFX942-SDAG-NEXT: global_store_short v[0:1], v3, off offset:1052 +; GFX942-SDAG-NEXT: global_store_byte v[0:1], v2, off offset:1054 +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p1_sz1055_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v2 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v3, 8, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v3, 24, v3 +; GFX942-GISEL-NEXT: v_or3_b32 v4, v4, v5, v3 +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], 0x400 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1] +; GFX942-GISEL-NEXT: .LBB6_1: ; %static-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, v0, v10 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, v1, v11, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, 0x100, v10 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:16 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:32 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:48 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:64 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:80 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:96 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:112 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:128 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:144 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:160 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:176 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:192 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:208 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:224 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:240 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc +; GFX942-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9] +; GFX942-GISEL-NEXT: s_cbranch_vccnz .LBB6_1 +; GFX942-GISEL-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-GISEL-NEXT: v_and_b32_e32 v3, 0xff, v2 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v3, 8, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v3, 24, v3 +; GFX942-GISEL-NEXT: v_or3_b32 v6, v4, v5, v3 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 8 +; GFX942-GISEL-NEXT: v_lshlrev_b16_sdwa v3, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX942-GISEL-NEXT: v_or_b32_sdwa v3, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX942-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v3 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v4, 16, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v7, v6 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v8, v6 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v9, v6 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[0:1], v[6:9], off offset:1024 +; GFX942-GISEL-NEXT: global_store_dwordx3 v[0:1], v[4:6], off offset:1040 +; GFX942-GISEL-NEXT: global_store_short v[0:1], v3, off offset:1052 +; GFX942-GISEL-NEXT: global_store_byte v[0:1], v2, off offset:1054 +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 4 %dst, i8 %setval, i64 1055, i1 false) + ret void +} + +define void @memset_p1_sz2048_align_4_varsetval(ptr addrspace(1) align 4 %dst, i8 %setval) { +; GFX942-SDAG-LABEL: memset_p1_sz2048_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v2, v2, v2, s0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v33, v2 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_mov_b64_e32 v[34:35], 0x800 +; GFX942-SDAG-NEXT: .LBB7_1: ; %static-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[36:37], v[0:1], 0, s[0:1] +; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100 +; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[34:35] +; GFX942-SDAG-NEXT: s_and_b64 vcc, exec, vcc +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[30:33], off offset:112 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[26:29], off offset:96 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[22:25], off offset:80 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[18:21], off offset:64 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[14:17], off offset:48 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[10:13], off offset:32 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[6:9], off offset:16 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[2:5], off +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[30:33], off offset:240 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[26:29], off offset:224 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[22:25], off offset:208 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[18:21], off offset:192 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[14:17], off offset:176 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[10:13], off offset:160 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[6:9], off offset:144 +; GFX942-SDAG-NEXT: global_store_dwordx4 v[36:37], v[2:5], off offset:128 +; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB7_1 +; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p1_sz2048_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v2 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v3, v2, 8, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v2 +; GFX942-GISEL-NEXT: v_or3_b32 v2, v3, v4, v2 +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], 0x800 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1] +; GFX942-GISEL-NEXT: .LBB7_1: ; %static-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v10, vcc, v0, v8 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v11, vcc, v1, v9, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 0x100, v8 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:16 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:32 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:48 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:64 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:80 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:96 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:112 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:128 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:144 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:160 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:176 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:192 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:208 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:224 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[10:11], v[2:5], off offset:240 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX942-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[6:7] +; GFX942-GISEL-NEXT: s_cbranch_vccnz .LBB7_1 +; GFX942-GISEL-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 4 %dst, i8 %setval, i64 2048, i1 false) + ret void +} + +define void @memset_p3_sz1055_align_4_varsetval(ptr addrspace(3) align 4 %dst, i8 %setval) { +; GFX942-SDAG-LABEL: memset_p3_sz1055_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v2, v1, v1, s0 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_mov_b64_e32 v[34:35], 0x400 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v36, v0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v33, v2 +; GFX942-SDAG-NEXT: .LBB8_1: ; %static-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100 +; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[34:35] +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v32, v33 offset0:30 offset1:31 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v30, v31 offset0:28 offset1:29 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v28, v29 offset0:26 offset1:27 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v26, v27 offset0:24 offset1:25 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v24, v25 offset0:22 offset1:23 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v22, v23 offset0:20 offset1:21 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v20, v21 offset0:18 offset1:19 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v18, v19 offset0:16 offset1:17 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v16, v17 offset0:14 offset1:15 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v14, v15 offset0:12 offset1:13 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v12, v13 offset0:10 offset1:11 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v10, v11 offset0:8 offset1:9 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v8, v9 offset0:6 offset1:7 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v6, v7 offset0:4 offset1:5 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v4, v5 offset0:2 offset1:3 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v2, v3 offset1:1 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v32, v33 offset0:62 offset1:63 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v30, v31 offset0:60 offset1:61 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v28, v29 offset0:58 offset1:59 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v26, v27 offset0:56 offset1:57 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v24, v25 offset0:54 offset1:55 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v22, v23 offset0:52 offset1:53 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v20, v21 offset0:50 offset1:51 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v18, v19 offset0:48 offset1:49 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v16, v17 offset0:46 offset1:47 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v14, v15 offset0:44 offset1:45 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v12, v13 offset0:42 offset1:43 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v10, v11 offset0:40 offset1:41 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v8, v9 offset0:38 offset1:39 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v6, v7 offset0:36 offset1:37 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v4, v5 offset0:34 offset1:35 +; GFX942-SDAG-NEXT: ds_write2_b32 v36, v2, v3 offset0:32 offset1:33 +; GFX942-SDAG-NEXT: v_add_u32_e32 v36, 0x100, v36 +; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB8_1 +; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_add_u32_e32 v2, 0x400, v0 +; GFX942-SDAG-NEXT: v_add_u32_e32 v3, 0x408, v0 +; GFX942-SDAG-NEXT: v_perm_b32 v4, v1, v1, s0 +; GFX942-SDAG-NEXT: ds_write2_b32 v3, v4, v4 offset1:1 +; GFX942-SDAG-NEXT: ds_write2_b32 v2, v4, v4 offset1:1 +; GFX942-SDAG-NEXT: v_add_u32_e32 v2, 0x410, v0 +; GFX942-SDAG-NEXT: ds_write2_b32 v2, v4, v4 offset1:1 +; GFX942-SDAG-NEXT: ds_write_b32 v0, v4 offset:1048 +; GFX942-SDAG-NEXT: v_lshlrev_b16_e32 v2, 8, v1 +; GFX942-SDAG-NEXT: v_or_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX942-SDAG-NEXT: ds_write_b16 v0, v2 offset:1052 +; GFX942-SDAG-NEXT: ds_write_b8 v0, v1 offset:1054 +; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p3_sz1055_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v1 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v3, v2, 8, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v2 +; GFX942-GISEL-NEXT: v_or3_b32 v2, v3, v4, v2 +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], 0x400 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v10, v0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1] +; GFX942-GISEL-NEXT: .LBB8_1: ; %static-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 0x100, v8 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset1:1 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:2 offset1:3 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:4 offset1:5 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:6 offset1:7 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:8 offset1:9 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:10 offset1:11 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:12 offset1:13 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:14 offset1:15 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:16 offset1:17 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:18 offset1:19 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:20 offset1:21 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:22 offset1:23 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:24 offset1:25 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:26 offset1:27 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:28 offset1:29 +; GFX942-GISEL-NEXT: ds_write2_b64 v10, v[2:3], v[4:5] offset0:30 offset1:31 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX942-GISEL-NEXT: v_add_u32_e32 v10, 0x100, v10 +; GFX942-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[6:7] +; GFX942-GISEL-NEXT: s_cbranch_vccnz .LBB8_1 +; GFX942-GISEL-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v1 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v3, v2, 8, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v2 +; GFX942-GISEL-NEXT: v_or3_b32 v2, v3, v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:128 offset1:129 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 8 +; GFX942-GISEL-NEXT: v_lshlrev_b16_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX942-GISEL-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX942-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v3 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v4, 16, v4 +; GFX942-GISEL-NEXT: v_add_u32_e32 v5, 0x410, v0 +; GFX942-GISEL-NEXT: ds_write2_b32 v5, v4, v4 offset1:1 +; GFX942-GISEL-NEXT: ds_write_b32 v0, v2 offset:1048 +; GFX942-GISEL-NEXT: ds_write_b16 v0, v3 offset:1052 +; GFX942-GISEL-NEXT: ds_write_b8 v0, v1 offset:1054 +; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p3.i64(ptr addrspace(3) noundef nonnull align 4 %dst, i8 %setval, i64 1055, i1 false) + ret void +} + +define void @memset_p3_sz2048_align_4_varsetval(ptr addrspace(3) align 4 %dst, i8 %setval) { +; GFX942-SDAG-LABEL: memset_p3_sz2048_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v2, v1, v1, s0 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_mov_b64_e32 v[34:35], 0x800 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v1, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v2 +; GFX942-SDAG-NEXT: .LBB9_1: ; %static-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100 +; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[34:35] +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v32, v31 offset0:30 offset1:31 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v30, v29 offset0:28 offset1:29 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v28, v27 offset0:26 offset1:27 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v26, v25 offset0:24 offset1:25 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v24, v23 offset0:22 offset1:23 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v22, v21 offset0:20 offset1:21 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v20, v19 offset0:18 offset1:19 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v18, v17 offset0:16 offset1:17 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v16, v15 offset0:14 offset1:15 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v14, v13 offset0:12 offset1:13 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v12, v11 offset0:10 offset1:11 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v10, v9 offset0:8 offset1:9 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v8, v7 offset0:6 offset1:7 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v6, v5 offset0:4 offset1:5 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v4, v3 offset0:2 offset1:3 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v2, v1 offset1:1 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v32, v31 offset0:62 offset1:63 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v30, v29 offset0:60 offset1:61 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v28, v27 offset0:58 offset1:59 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v26, v25 offset0:56 offset1:57 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v24, v23 offset0:54 offset1:55 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v22, v21 offset0:52 offset1:53 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v20, v19 offset0:50 offset1:51 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v18, v17 offset0:48 offset1:49 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v16, v15 offset0:46 offset1:47 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v14, v13 offset0:44 offset1:45 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v12, v11 offset0:42 offset1:43 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v10, v9 offset0:40 offset1:41 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v8, v7 offset0:38 offset1:39 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v6, v5 offset0:36 offset1:37 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v4, v3 offset0:34 offset1:35 +; GFX942-SDAG-NEXT: ds_write2_b32 v0, v2, v1 offset0:32 offset1:33 +; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 0x100, v0 +; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB9_1 +; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p3_sz2048_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v2, v1, 8, v1 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v1 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1 +; GFX942-GISEL-NEXT: v_or3_b32 v2, v2, v3, v1 +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], 0x800 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1] +; GFX942-GISEL-NEXT: .LBB9_1: ; %static-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 0x100, v8 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset1:1 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:2 offset1:3 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:4 offset1:5 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:6 offset1:7 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:8 offset1:9 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:10 offset1:11 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:12 offset1:13 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:14 offset1:15 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:16 offset1:17 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:18 offset1:19 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:20 offset1:21 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:22 offset1:23 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:24 offset1:25 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:26 offset1:27 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:28 offset1:29 +; GFX942-GISEL-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset0:30 offset1:31 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 0x100, v0 +; GFX942-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[6:7] +; GFX942-GISEL-NEXT: s_cbranch_vccnz .LBB9_1 +; GFX942-GISEL-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p3.i64(ptr addrspace(3) noundef nonnull align 4 %dst, i8 %setval, i64 2048, i1 false) + ret void +} + +define void @memset_p5_sz1055_align_4_varsetval(ptr addrspace(5) align 4 %dst, i8 %setval) { +; GFX942-SDAG-LABEL: memset_p5_sz1055_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v2, v1, v1, s0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v33, v2 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_mov_b64_e32 v[34:35], 0x400 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v36, v0 +; GFX942-SDAG-NEXT: .LBB10_1: ; %static-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100 +; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[34:35] +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[30:33], off offset:112 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[26:29], off offset:96 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[22:25], off offset:80 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[18:21], off offset:64 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[14:17], off offset:48 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[10:13], off offset:32 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[6:9], off offset:16 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[2:5], off +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[30:33], off offset:240 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[26:29], off offset:224 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[22:25], off offset:208 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[18:21], off offset:192 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[14:17], off offset:176 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[10:13], off offset:160 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[6:9], off offset:144 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v36, v[2:5], off offset:128 +; GFX942-SDAG-NEXT: v_add_u32_e32 v36, 0x100, v36 +; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB10_1 +; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v2, v1, v1, s0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:1024 +; GFX942-SDAG-NEXT: scratch_store_dwordx2 v0, v[2:3], off offset:1040 +; GFX942-SDAG-NEXT: scratch_store_dword v0, v2, off offset:1048 +; GFX942-SDAG-NEXT: v_lshlrev_b16_e32 v2, 8, v1 +; GFX942-SDAG-NEXT: v_or_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX942-SDAG-NEXT: scratch_store_short v0, v2, off offset:1052 +; GFX942-SDAG-NEXT: scratch_store_byte v0, v1, off offset:1054 +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p5_sz1055_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v1 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v3, v2, 8, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v2 +; GFX942-GISEL-NEXT: v_or3_b32 v2, v3, v4, v2 +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], 0x400 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v10, v0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1] +; GFX942-GISEL-NEXT: .LBB10_1: ; %static-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 0x100, v8 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:16 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:32 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:48 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:64 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:80 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:96 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:112 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:128 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:144 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:160 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:176 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:192 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:208 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:224 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v10, v[2:5], off offset:240 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX942-GISEL-NEXT: v_add_u32_e32 v10, 0x100, v10 +; GFX942-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[6:7] +; GFX942-GISEL-NEXT: s_cbranch_vccnz .LBB10_1 +; GFX942-GISEL-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-GISEL-NEXT: v_and_b32_e32 v2, 0xff, v1 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v3, v2, 8, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 24, v2 +; GFX942-GISEL-NEXT: v_or3_b32 v2, v3, v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:1024 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, 8 +; GFX942-GISEL-NEXT: v_lshlrev_b16_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX942-GISEL-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX942-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v3 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v4, v4, 16, v4 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-GISEL-NEXT: scratch_store_dwordx2 v0, v[4:5], off offset:1040 +; GFX942-GISEL-NEXT: scratch_store_dword v0, v2, off offset:1048 +; GFX942-GISEL-NEXT: scratch_store_short v0, v3, off offset:1052 +; GFX942-GISEL-NEXT: scratch_store_byte v0, v1, off offset:1054 +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p5.i64(ptr addrspace(5) noundef nonnull align 4 %dst, i8 %setval, i64 1055, i1 false) + ret void +} + +define void @memset_p5_sz2048_align_4_varsetval(ptr addrspace(5) align 4 %dst, i8 %setval) { +; GFX942-SDAG-LABEL: memset_p5_sz2048_align_4_varsetval: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: s_mov_b32 s0, 0x4040404 +; GFX942-SDAG-NEXT: v_perm_b32 v2, v1, v1, s0 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v12, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v13, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v14, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v16, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v17, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v18, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v19, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v20, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v21, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v22, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v23, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v24, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v25, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v26, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v27, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v28, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v29, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v30, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v31, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v32, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v33, v2 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_mov_b64_e32 v[34:35], 0x800 +; GFX942-SDAG-NEXT: .LBB11_1: ; %static-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: s_add_u32 s0, s0, 0x100 +; GFX942-SDAG-NEXT: s_addc_u32 s1, s1, 0 +; GFX942-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[34:35] +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[30:33], off offset:112 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[26:29], off offset:96 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[22:25], off offset:80 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[18:21], off offset:64 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[14:17], off offset:48 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[10:13], off offset:32 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[6:9], off offset:16 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[2:5], off +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[30:33], off offset:240 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[26:29], off offset:224 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[22:25], off offset:208 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[18:21], off offset:192 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[14:17], off offset:176 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[10:13], off offset:160 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[6:9], off offset:144 +; GFX942-SDAG-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:128 +; GFX942-SDAG-NEXT: v_add_u32_e32 v0, 0x100, v0 +; GFX942-SDAG-NEXT: s_cbranch_vccnz .LBB11_1 +; GFX942-SDAG-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p5_sz2048_align_4_varsetval: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v1 +; GFX942-GISEL-NEXT: v_lshl_or_b32 v2, v1, 8, v1 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v1 +; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1 +; GFX942-GISEL-NEXT: v_or3_b32 v2, v2, v3, v1 +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, v2 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v5, v2 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], 0x800 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[0:1] +; GFX942-GISEL-NEXT: .LBB11_1: ; %static-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v8, vcc, 0x100, v8 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:16 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:32 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:48 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:64 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:80 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:96 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:112 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:128 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:144 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:160 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:176 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:192 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:208 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:224 +; GFX942-GISEL-NEXT: scratch_store_dwordx4 v0, v[2:5], off offset:240 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc +; GFX942-GISEL-NEXT: v_add_u32_e32 v0, 0x100, v0 +; GFX942-GISEL-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[6:7] +; GFX942-GISEL-NEXT: s_cbranch_vccnz .LBB11_1 +; GFX942-GISEL-NEXT: ; %bb.2: ; %static-memset-post-expansion +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p5.i64(ptr addrspace(5) noundef nonnull align 4 %dst, i8 %setval, i64 2048, i1 false) + ret void +} + +define void @memset_p1_varsz_align_4_set40(ptr addrspace(1) align 4 %dst, i64 %size) { +; GFX942-SDAG-LABEL: memset_p1_varsz_align_4_set40: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: v_and_b32_e32 v10, -16, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v3 +; GFX942-SDAG-NEXT: v_and_b32_e32 v8, 15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB12_3 +; GFX942-SDAG-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-SDAG-NEXT: v_mov_b32_e32 v4, 0x28282828 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v6, v4 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v4 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB12_2: ; %dynamic-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[12:13], v[0:1], 0, s[4:5] +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 16 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[10:11] +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: global_store_dwordx4 v[12:13], v[4:7], off +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB12_2 +; GFX942-SDAG-NEXT: .LBB12_3: ; %Flow4 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB12_6 +; GFX942-SDAG-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-SDAG-NEXT: v_and_b32_e32 v2, -16, v2 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 40 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB12_5: ; %dynamic-memset-expansion-residual-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[4:5] +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 1 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9] +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: global_store_byte v[4:5], v2, off +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB12_5 +; GFX942-SDAG-NEXT: .LBB12_6: ; %Flow2 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p1_varsz_align_4_set40: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v8, 15, v2 +; GFX942-GISEL-NEXT: v_sub_co_u32_e32 v10, vcc, v2, v8 +; GFX942-GISEL-NEXT: v_mov_b32_e32 v9, 0 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_subbrev_co_u32_e32 v11, vcc, 0, v3, vcc +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB12_3 +; GFX942-GISEL-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-GISEL-NEXT: s_mov_b32 s4, 0x28282828 +; GFX942-GISEL-NEXT: s_mov_b32 s5, s4 +; GFX942-GISEL-NEXT: s_mov_b32 s6, s4 +; GFX942-GISEL-NEXT: s_mov_b32 s7, s4 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[4:5] +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[6:7] +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[0:1] +; GFX942-GISEL-NEXT: .LBB12_2: ; %dynamic-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, v0, v12 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, v1, v13, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 16, v12 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[14:15], v[4:7], off +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[10:11] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB12_2 +; GFX942-GISEL-NEXT: .LBB12_3: ; %Flow4 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB12_6 +; GFX942-GISEL-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-GISEL-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3] +; GFX942-GISEL-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 4, v[0:1] +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 40 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-GISEL-NEXT: .LBB12_5: ; %dynamic-memset-expansion-residual-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, v0, v2 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v3, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 1, v2 +; GFX942-GISEL-NEXT: global_store_byte v[6:7], v4, off +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[8:9] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB12_5 +; GFX942-GISEL-NEXT: .LBB12_6: ; %Flow2 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 4 %dst, i8 40, i64 %size, i1 false) + ret void +} + +define void @memset_p1_varsz_align_4_set0(ptr addrspace(1) align 4 %dst, i64 %size) { +; GFX942-SDAG-LABEL: memset_p1_varsz_align_4_set0: +; GFX942-SDAG: ; %bb.0: ; %entry +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-SDAG-NEXT: v_and_b32_e32 v6, -16, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v7, v3 +; GFX942-SDAG-NEXT: v_and_b32_e32 v4, 15, v2 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v5, 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB13_3 +; GFX942-SDAG-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-SDAG-NEXT: v_mov_b32_e32 v8, v5 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v9, v5 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v10, v5 +; GFX942-SDAG-NEXT: v_mov_b32_e32 v11, v5 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB13_2: ; %dynamic-memset-expansion-main-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[12:13], v[0:1], 0, s[4:5] +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 16 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[6:7] +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: global_store_dwordx4 v[12:13], v[8:11], off +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB13_2 +; GFX942-SDAG-NEXT: .LBB13_3: ; %Flow4 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-SDAG-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GFX942-SDAG-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-SDAG-NEXT: s_cbranch_execz .LBB13_6 +; GFX942-SDAG-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-SDAG-NEXT: v_and_b32_e32 v2, -16, v2 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3] +; GFX942-SDAG-NEXT: v_mov_b32_e32 v2, 0 +; GFX942-SDAG-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-SDAG-NEXT: .LBB13_5: ; %dynamic-memset-expansion-residual-body +; GFX942-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-SDAG-NEXT: v_lshl_add_u64 v[6:7], v[0:1], 0, s[4:5] +; GFX942-SDAG-NEXT: s_add_u32 s4, s4, 1 +; GFX942-SDAG-NEXT: s_addc_u32 s5, s5, 0 +; GFX942-SDAG-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[4:5] +; GFX942-SDAG-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-SDAG-NEXT: global_store_byte v[6:7], v2, off +; GFX942-SDAG-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-SDAG-NEXT: s_cbranch_execnz .LBB13_5 +; GFX942-SDAG-NEXT: .LBB13_6: ; %Flow2 +; GFX942-SDAG-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX942-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX942-GISEL-LABEL: memset_p1_varsz_align_4_set0: +; GFX942-GISEL: ; %bb.0: ; %entry +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX942-GISEL-NEXT: v_and_b32_e32 v8, 15, v2 +; GFX942-GISEL-NEXT: v_sub_co_u32_e32 v10, vcc, v2, v8 +; GFX942-GISEL-NEXT: s_mov_b32 s0, 0 +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_subbrev_co_u32_e32 v11, vcc, 0, v3, vcc +; GFX942-GISEL-NEXT: v_mov_b32_e32 v9, 0 +; GFX942-GISEL-NEXT: s_mov_b64 s[4:5], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB13_3 +; GFX942-GISEL-NEXT: ; %bb.1: ; %dynamic-memset-expansion-main-body.preheader +; GFX942-GISEL-NEXT: s_mov_b32 s2, s0 +; GFX942-GISEL-NEXT: s_mov_b32 s3, s0 +; GFX942-GISEL-NEXT: s_mov_b32 s1, s0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[2:3] +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[4:5] +; GFX942-GISEL-NEXT: .LBB13_2: ; %dynamic-memset-expansion-main-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v14, vcc, v0, v12 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v15, vcc, v1, v13, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v12, vcc, 16, v12 +; GFX942-GISEL-NEXT: global_store_dwordx4 v[14:15], v[4:7], off +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[10:11] +; GFX942-GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB13_2 +; GFX942-GISEL-NEXT: .LBB13_3: ; %Flow4 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[6:7] +; GFX942-GISEL-NEXT: s_mov_b64 s[0:1], 0 +; GFX942-GISEL-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] +; GFX942-GISEL-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX942-GISEL-NEXT: s_cbranch_execz .LBB13_6 +; GFX942-GISEL-NEXT: ; %bb.4: ; %dynamic-memset-expansion-residual-body.preheader +; GFX942-GISEL-NEXT: v_lshrrev_b64 v[2:3], 4, v[2:3] +; GFX942-GISEL-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 4, v[0:1] +; GFX942-GISEL-NEXT: v_mov_b32_e32 v4, 0 +; GFX942-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] +; GFX942-GISEL-NEXT: .LBB13_5: ; %dynamic-memset-expansion-residual-body +; GFX942-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v6, vcc, v0, v2 +; GFX942-GISEL-NEXT: s_nop 1 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v3, vcc +; GFX942-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 1, v2 +; GFX942-GISEL-NEXT: global_store_byte v[6:7], v4, off +; GFX942-GISEL-NEXT: s_nop 0 +; GFX942-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX942-GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[2:3], v[8:9] +; GFX942-GISEL-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX942-GISEL-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX942-GISEL-NEXT: s_cbranch_execnz .LBB13_5 +; GFX942-GISEL-NEXT: .LBB13_6: ; %Flow2 +; GFX942-GISEL-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX942-GISEL-NEXT: s_setpc_b64 s[30:31] +entry: + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 4 %dst, i8 0, i64 %size, i1 false) + ret void +} + +declare void @llvm.memset.p0.i64(ptr addrspace(0) noalias nocapture writeonly, i8, i64, i1 immarg) +declare void @llvm.memset.p1.i64(ptr addrspace(1) noalias nocapture writeonly, i8, i64, i1 immarg) +declare void @llvm.memset.p3.i64(ptr addrspace(3) noalias nocapture writeonly, i8, i64, i1 immarg) +declare void @llvm.memset.p5.i64(ptr addrspace(5) noalias nocapture writeonly, i8, i64, i1 immarg) + + +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX942: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll index 26c4830dffffb..059527cea7c01 100644 --- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll @@ -2682,8 +2682,8 @@ define <32 x float> @test_mfma_loop_non_splat_ret_use() #0 { ; GFX908-NEXT: v_accvgpr_write_b32 a3, 0 ; GFX908-NEXT: v_accvgpr_write_b32 a2, 0 ; GFX908-NEXT: v_accvgpr_write_b32 a0, 0 -; GFX908-NEXT: s_mov_b32 s4, 16 ; GFX908-NEXT: v_mov_b32_e32 v0, 1.0 +; GFX908-NEXT: s_mov_b32 s4, 16 ; GFX908-NEXT: v_mov_b32_e32 v1, 2.0 ; GFX908-NEXT: .LBB11_1: ; %for.cond.preheader ; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll index eff0680fe9a31..5283233a0b461 100644 --- a/llvm/test/CodeGen/AMDGPU/min.ll +++ b/llvm/test/CodeGen/AMDGPU/min.ll @@ -3798,36 +3798,36 @@ define amdgpu_kernel void @s_test_umin_ult_v8i16(ptr addrspace(1) %out, <8 x i16 ; VI-NEXT: s_min_u32 s3, s3, s7 ; VI-NEXT: s_min_u32 s10, s11, s10 ; VI-NEXT: s_lshl_b32 s3, s3, 16 -; VI-NEXT: s_or_b32 s3, s10, s3 -; VI-NEXT: s_and_b32 s7, s6, 0xffff -; VI-NEXT: s_and_b32 s10, s2, 0xffff +; VI-NEXT: s_or_b32 s10, s10, s3 +; VI-NEXT: s_and_b32 s3, s6, 0xffff +; VI-NEXT: s_and_b32 s7, s2, 0xffff ; VI-NEXT: s_lshr_b32 s6, s6, 16 ; VI-NEXT: s_lshr_b32 s2, s2, 16 ; VI-NEXT: s_min_u32 s2, s2, s6 -; VI-NEXT: s_min_u32 s7, s10, s7 +; VI-NEXT: s_min_u32 s3, s7, s3 ; VI-NEXT: s_lshl_b32 s2, s2, 16 -; VI-NEXT: s_or_b32 s2, s7, s2 -; VI-NEXT: s_and_b32 s6, s5, 0xffff -; VI-NEXT: s_and_b32 s7, s1, 0xffff +; VI-NEXT: s_or_b32 s3, s3, s2 +; VI-NEXT: s_and_b32 s2, s5, 0xffff +; VI-NEXT: s_and_b32 s6, s1, 0xffff ; VI-NEXT: s_lshr_b32 s5, s5, 16 ; VI-NEXT: s_lshr_b32 s1, s1, 16 ; VI-NEXT: s_min_u32 s1, s1, s5 -; VI-NEXT: s_min_u32 s6, s7, s6 +; VI-NEXT: s_min_u32 s2, s6, s2 ; VI-NEXT: s_lshl_b32 s1, s1, 16 -; VI-NEXT: s_or_b32 s1, s6, s1 -; VI-NEXT: s_and_b32 s5, s4, 0xffff -; VI-NEXT: s_and_b32 s6, s0, 0xffff +; VI-NEXT: s_or_b32 s2, s2, s1 +; VI-NEXT: s_and_b32 s1, s4, 0xffff +; VI-NEXT: s_and_b32 s5, s0, 0xffff ; VI-NEXT: s_lshr_b32 s4, s4, 16 ; VI-NEXT: s_lshr_b32 s0, s0, 16 ; VI-NEXT: s_min_u32 s0, s0, s4 -; VI-NEXT: s_min_u32 s5, s6, s5 +; VI-NEXT: s_min_u32 s1, s5, s1 ; VI-NEXT: s_lshl_b32 s0, s0, 16 -; VI-NEXT: s_or_b32 s0, s5, s0 +; VI-NEXT: s_or_b32 s1, s1, s0 ; VI-NEXT: v_mov_b32_e32 v4, s8 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v0, s1 +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_mov_b32_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v3, s10 ; VI-NEXT: v_mov_b32_e32 v5, s9 ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll b/llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll new file mode 100644 index 0000000000000..a801ff73286a7 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll @@ -0,0 +1,347 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s + +declare { float, float } @llvm.modf.f32(float) +declare { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float>) +declare { <4 x float>, <4 x float> } @llvm.modf.v4f32(<4 x float>) + +define { float, float } @modf_3_25() { +; CHECK-LABEL: modf_3_25: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0x3e800000 +; CHECK-NEXT: v_mov_b32_e32 v1, 0x40400000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float 0x400A000000000000) + ret { float, float } %ret +} + +define { float, float } @modf_neg_3_25() { +; CHECK-LABEL: modf_neg_3_25: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0xbe800000 +; CHECK-NEXT: v_mov_b32_e32 v1, 0xc0400000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float 0xC00A000000000000) + ret { float, float } %ret +} + +define { float, float } @modf_integer() { +; CHECK-LABEL: modf_integer: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_bfrev_b32_e32 v0, 1 +; CHECK-NEXT: v_mov_b32_e32 v1, 0xc2280000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float -42.0) + ret { float, float } %ret +} + +define { float, float } @modf_fraction() { +; CHECK-LABEL: modf_fraction: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0.5 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float 0.5) + ret { float, float } %ret +} + +define { float, float } @modf_negfraction() { +; CHECK-LABEL: modf_negfraction: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, -0.5 +; CHECK-NEXT: v_bfrev_b32_e32 v1, 1 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float -0.5) + ret { float, float } %ret +} + +define { float, float } @modf_zero() { +; CHECK-LABEL: modf_zero: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float 0.0) + ret { float, float } %ret +} + +define { float, float } @modf_negzero() { +; CHECK-LABEL: modf_negzero: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_bfrev_b32_e32 v0, 1 +; CHECK-NEXT: v_bfrev_b32_e32 v1, 1 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float -0.0) + ret { float, float } %ret +} + +define { float, float } @modf_inf() { +; CHECK-LABEL: modf_inf: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, 0x7f800000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float 0x7FF0000000000000) + ret { float, float } %ret +} + +define { float, float } @modf_neginf() { +; CHECK-LABEL: modf_neginf: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_bfrev_b32_e32 v0, 1 +; CHECK-NEXT: v_mov_b32_e32 v1, 0xff800000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float 0xFFF0000000000000) + ret { float, float } %ret +} + +define { float, float } @modf_qnan() { +; CHECK-LABEL: modf_qnan: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0x7fc00000 +; CHECK-NEXT: v_mov_b32_e32 v1, 0x7fc00000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float 0x7FF8000000000000) + ret { float, float } %ret +} + +define { float, float } @modf_snan() { +; CHECK-LABEL: modf_snan: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_trunc_f32_e32 v1, 0x7f800001 +; CHECK-NEXT: v_sub_f32_e32 v0, 0x7f800001, v1 +; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float bitcast (i32 2139095041 to float)) + ret { float, float } %ret +} + +define { float, float } @modf_pos_denorm() { +; CHECK-LABEL: modf_pos_denorm: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0x7fffff +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float bitcast (i32 8388607 to float)) + ret { float, float } %ret +} + +define { float, float } @modf_neg_denorm() { +; CHECK-LABEL: modf_neg_denorm: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0x807fffff +; CHECK-NEXT: v_bfrev_b32_e32 v1, 1 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float bitcast (i32 -2139095041 to float)) + ret { float, float } %ret +} + +define { float, float } @modf_posion() { +; CHECK-LABEL: modf_posion: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { float, float } @llvm.modf.f32(float poison) + ret { float, float } %ret +} + +define { <2 x float>, <2 x float> } @modf_posion_vector() { +; CHECK-LABEL: modf_posion_vector: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> poison) + ret { <2 x float>, <2 x float> } %ret +} + +define { <2 x float>, <2 x float> } @modf_zero_vector() { +; CHECK-LABEL: modf_zero_vector: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, 0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> zeroinitializer) + ret { <2 x float>, <2 x float> } %ret +} + +define { <2 x float>, <2 x float> } @modf_zero_negzero_vector() { +; CHECK-LABEL: modf_zero_negzero_vector: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: v_bfrev_b32_e32 v1, 1 +; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: v_bfrev_b32_e32 v3, 1 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> ) + ret { <2 x float>, <2 x float> } %ret +} + +define { float, float } @modf_modf(float %x) { +; CHECK-LABEL: modf_modf: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s4, 0x7f800000 +; CHECK-NEXT: v_trunc_f32_e32 v1, v0 +; CHECK-NEXT: v_sub_f32_e32 v1, v0, v1 +; CHECK-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 +; CHECK-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; CHECK-NEXT: s_brev_b32 s5, -2 +; CHECK-NEXT: v_bfi_b32 v0, s5, v1, v0 +; CHECK-NEXT: v_trunc_f32_e32 v1, v0 +; CHECK-NEXT: v_sub_f32_e32 v2, v0, v1 +; CHECK-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 +; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; CHECK-NEXT: v_bfi_b32 v0, s5, v2, v0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %modf0 = call { float, float } @llvm.modf.f32(float %x) + %modf0.0 = extractvalue { float, float } %modf0, 0 + %modf1 = call { float, float } @llvm.modf.f32(float %modf0.0) + ret { float, float } %modf1 +} + +define { <2 x float>, <2 x float> } @modf_modf_vector(<2 x float> %x) { +; CHECK-LABEL: modf_modf_vector: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_mov_b32 s4, 0x7f800000 +; CHECK-NEXT: v_trunc_f32_e32 v2, v1 +; CHECK-NEXT: v_sub_f32_e32 v2, v1, v2 +; CHECK-NEXT: v_cmp_neq_f32_e64 vcc, |v1|, s4 +; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; CHECK-NEXT: s_brev_b32 s5, -2 +; CHECK-NEXT: v_bfi_b32 v1, s5, v2, v1 +; CHECK-NEXT: v_trunc_f32_e32 v2, v0 +; CHECK-NEXT: v_sub_f32_e32 v2, v0, v2 +; CHECK-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 +; CHECK-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; CHECK-NEXT: v_bfi_b32 v0, s5, v2, v0 +; CHECK-NEXT: v_trunc_f32_e32 v2, v0 +; CHECK-NEXT: v_sub_f32_e32 v3, v0, v2 +; CHECK-NEXT: v_cmp_neq_f32_e64 vcc, |v0|, s4 +; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; CHECK-NEXT: v_bfi_b32 v0, s5, v3, v0 +; CHECK-NEXT: v_trunc_f32_e32 v3, v1 +; CHECK-NEXT: v_sub_f32_e32 v4, v1, v3 +; CHECK-NEXT: v_cmp_neq_f32_e64 vcc, |v1|, s4 +; CHECK-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc +; CHECK-NEXT: v_bfi_b32 v1, s5, v4, v1 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %modf0 = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> %x) + %modf0.0 = extractvalue { <2 x float>, <2 x float> } %modf0, 0 + %modf1 = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> %modf0.0) + ret { <2 x float>, <2 x float> } %modf1 +} + +define { float, float } @modf_modf_const(float %x) { +; CHECK-LABEL: modf_modf_const: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0x3e800000 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %modf0 = call { float, float } @llvm.modf.f32(float 0x400A000000000000) + %modf0.0 = extractvalue { float, float } %modf0, 0 + %modf1 = call { float, float } @llvm.modf.f32(float %modf0.0) + ret { float, float } %modf1 +} + +define { <4 x float>, <4 x float> } @modf_nonsplat_vector() { +; CHECK-LABEL: modf_nonsplat_vector: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_and_b32 s4, 0x80000000, s4 +; CHECK-NEXT: v_trunc_f32_e32 v6, s4 +; CHECK-NEXT: v_mov_b32_e32 v0, 0x3e800000 +; CHECK-NEXT: v_bfrev_b32_e32 v1, 1 +; CHECK-NEXT: v_mov_b32_e32 v2, s4 +; CHECK-NEXT: v_mov_b32_e32 v3, 0 +; CHECK-NEXT: v_mov_b32_e32 v4, 0x40400000 +; CHECK-NEXT: v_mov_b32_e32 v5, 0xc2000000 +; CHECK-NEXT: v_mov_b32_e32 v7, 0x4479c000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <4 x float>, <4 x float> } @llvm.modf.v4f32(<4 x float> ) + ret { <4 x float>, <4 x float> } %ret +} + +define { <2 x float>, <2 x float> } @modf_splat_3_25() { +; CHECK-LABEL: modf_splat_3_25: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0x3e800000 +; CHECK-NEXT: v_mov_b32_e32 v1, 0x3e800000 +; CHECK-NEXT: v_mov_b32_e32 v2, 0x40400000 +; CHECK-NEXT: v_mov_b32_e32 v3, 0x40400000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> ) + ret { <2 x float>, <2 x float> } %ret +} + +define { <2 x float>, <2 x float> } @modf_splat_qnan() { +; CHECK-LABEL: modf_splat_qnan: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0x7fc00000 +; CHECK-NEXT: v_mov_b32_e32 v1, 0x7fc00000 +; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000 +; CHECK-NEXT: v_mov_b32_e32 v3, 0x7fc00000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> ) + ret { <2 x float>, <2 x float> } %ret +} + +define { <2 x float>, <2 x float> } @modf_splat_inf() { +; CHECK-LABEL: modf_splat_inf: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, 0x7f800000 +; CHECK-NEXT: v_mov_b32_e32 v3, 0x7f800000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> ) + ret { <2 x float>, <2 x float> } %ret +} + +define { <2 x float>, <2 x float> } @modf_splat_neginf() { +; CHECK-LABEL: modf_splat_neginf: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_bfrev_b32_e32 v0, 1 +; CHECK-NEXT: v_bfrev_b32_e32 v1, 1 +; CHECK-NEXT: v_mov_b32_e32 v2, 0xff800000 +; CHECK-NEXT: v_mov_b32_e32 v3, 0xff800000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> ) + ret { <2 x float>, <2 x float> } %ret +} + +define { <2 x float>, <2 x float> } @modf_splat_poison_inf() { +; CHECK-LABEL: modf_splat_poison_inf: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_and_b32 s4, 0x80000000, s4 +; CHECK-NEXT: v_trunc_f32_e32 v2, s4 +; CHECK-NEXT: v_mov_b32_e32 v0, s4 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, 0x7f800000 +; CHECK-NEXT: s_setpc_b64 s[30:31] + %ret = call { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float> ) + ret { <2 x float>, <2 x float> } %ret +} diff --git a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll index b13ad2d25b31d..0c0919de4aedc 100644 --- a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll +++ b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll @@ -263,8 +263,8 @@ define void @slsr1_1(i32 %b.arg, i32 %s.arg) #0 { declare void @foo(i32) #2 declare float @llvm.fmuladd.f32(float, float, float) #1 -attributes #0 = { nounwind willreturn "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind willreturn denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone speculatable } -attributes #2 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #2 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-cluster-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-cluster-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-cluster-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" denormal_fpenv(float: preservesign) } !0 = !{float 2.500000e+00} diff --git a/llvm/test/CodeGen/AMDGPU/omod.ll b/llvm/test/CodeGen/AMDGPU/omod.ll index c248de294eb81..d0d4e27a5a7f5 100644 --- a/llvm/test/CodeGen/AMDGPU/omod.ll +++ b/llvm/test/CodeGen/AMDGPU/omod.ll @@ -1319,13 +1319,13 @@ declare half @llvm.minnum.f16(half, half) #1 declare half @llvm.maxnum.f16(half, half) #1 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } -attributes #2 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } -attributes #3 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #2 = { nounwind denormal_fpenv(float: ieee) } +attributes #3 = { nounwind denormal_fpenv(preservesign) } attributes #4 = { nounwind "no-signed-zeros-fp-math"="false" } -attributes #5 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #6 = { nounwind "denormal-fp-math"="ieee,ieee" } +attributes #5 = { nounwind denormal_fpenv(preservesign) } +attributes #6 = { nounwind denormal_fpenv(ieee) } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!2, !3} diff --git a/llvm/test/CodeGen/AMDGPU/operand-folding.ll b/llvm/test/CodeGen/AMDGPU/operand-folding.ll index 1427225d25ee6..3177eef80436f 100644 --- a/llvm/test/CodeGen/AMDGPU/operand-folding.ll +++ b/llvm/test/CodeGen/AMDGPU/operand-folding.ll @@ -168,4 +168,4 @@ define i32 @issue139908(i64 %in) { declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll index cb2c8ddbaa6f2..555c49f186399 100644 --- a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll +++ b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-dvgpr.ll @@ -201,7 +201,7 @@ declare i64 @llvm.amdgcn.s.getpc() #2 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg) #3 -attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" "denormal-fp-math-f32"="preserve-sign" "target-features"="+wavefrontsize64,+cumode" "amdgpu-dynamic-vgpr-block-size"="16" } +attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" denormal_fpenv(float: preservesign) "target-features"="+wavefrontsize64,+cumode" "amdgpu-dynamic-vgpr-block-size"="16" } attributes #1 = { nounwind memory(readwrite) "InitialPSInputAddr"="36983" } diff --git a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll index 68694faf833e9..6ee48a9775629 100644 --- a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll +++ b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx1250.ll @@ -200,7 +200,7 @@ declare i64 @llvm.amdgcn.s.getpc() #2 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg) #3 -attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" "denormal-fp-math-f32"="preserve-sign" } +attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" denormal_fpenv(float: preservesign) } attributes #1 = { nounwind memory(readwrite) "InitialPSInputAddr"="36983" } diff --git a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll index b3575c68b892f..858a6a06eb029 100644 --- a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll +++ b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll @@ -207,7 +207,7 @@ declare i64 @llvm.amdgcn.s.getpc() #2 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg) #3 -attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" "denormal-fp-math-f32"="preserve-sign" } +attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" denormal_fpenv(float: preservesign) } attributes #1 = { nounwind memory(readwrite) "InitialPSInputAddr"="36983" } diff --git a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll index 1573544a3db14..33e8fb75431c2 100644 --- a/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll @@ -40,7 +40,7 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 { ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7012362 /* regdef:VReg_128 */, def renamable $vgpr0_vgpr1_vgpr2_vgpr3 ; PEI-GFX908-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = COPY killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit $exec ; PEI-GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 2818058 /* regdef:VReg_64 */, def renamable $vgpr0_vgpr1 - ; PEI-GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) + ; PEI-GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; PEI-GFX908-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1 ; PEI-GFX908-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = COPY killed renamable $agpr0_agpr1_agpr2_agpr3, implicit $exec ; PEI-GFX908-NEXT: GLOBAL_STORE_DWORDX4 undef renamable $vgpr0_vgpr1, killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, 0, 0, implicit $exec :: (volatile store (s128) into `ptr addrspace(1) poison`, addrspace 1) @@ -49,7 +49,7 @@ define amdgpu_kernel void @partial_copy(<4 x i32> %arg) #0 { ; PEI-GFX908-NEXT: renamable $vgpr0 = AV_MOV_B32_IMM_PSEUDO 1, implicit $exec ; PEI-GFX908-NEXT: renamable $vgpr1 = AV_MOV_B32_IMM_PSEUDO 2, implicit $exec ; PEI-GFX908-NEXT: renamable $agpr0_agpr1_agpr2_agpr3 = V_MFMA_I32_4X4X4I8_e64 killed $vgpr0, killed $vgpr1, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec - ; PEI-GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) + ; PEI-GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; PEI-GFX908-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr4, implicit $exec, implicit $vgpr0_vgpr1 ; PEI-GFX908-NEXT: GLOBAL_STORE_DWORDX2 undef renamable $vgpr0_vgpr1, killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec :: (volatile store (s64) into `ptr addrspace(1) poison`, addrspace 1) ; PEI-GFX908-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = COPY killed renamable $agpr0_agpr1_agpr2_agpr3, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir index bb248fe0444db..6121b447228b8 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir @@ -36,12 +36,12 @@ body: | ; GCN-LABEL: name: preserve_active_lanes_above_args ; GCN: liveins: $sgpr0, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: SCRATCH_STORE_DWORD_ST killed $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_ST killed $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: renamable $vgpr10 = V_MOV_B32_e32 10, implicit $exec ; GCN-NEXT: $vgpr8 = COPY killed renamable $vgpr10 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) - ; GCN-NEXT: $vgpr10 = SCRATCH_LOAD_DWORD_ST 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr10 = SCRATCH_LOAD_DWORD_ST 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: SI_CS_CHAIN_TC_W32 killed renamable $sgpr4_sgpr5, @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8, implicit $vgpr9 renamable $vgpr10 = V_MOV_B32_e32 10, implicit $exec $vgpr8 = COPY renamable killed $vgpr10 @@ -70,7 +70,7 @@ body: | ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr1 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr10, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $vgpr10 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr10 @@ -81,7 +81,7 @@ body: | ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) ; GCN-NEXT: $sgpr1 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr10 = SCRATCH_LOAD_DWORD_ST 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr10 = SCRATCH_LOAD_DWORD_ST 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: SI_CS_CHAIN_TC_W32 killed renamable $sgpr4_sgpr5, @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8, implicit $vgpr9 S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 @@ -144,7 +144,7 @@ body: | ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9, $vgpr10 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr1 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr9, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr9, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $vgpr8 = SI_SPILL_S32_TO_VGPR $sgpr35, 0, killed $vgpr8 @@ -154,7 +154,7 @@ body: | ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) ; GCN-NEXT: $sgpr1 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr9 = SCRATCH_LOAD_DWORD_ST 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr9(tied-def 0) :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr9 = SCRATCH_LOAD_DWORD_ST 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr9(tied-def 0) :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: SI_CS_CHAIN_TC_W32 killed renamable $sgpr4_sgpr5, @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8, implicit $vgpr9 S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 diff --git a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir index 4aea915936ffc..69d857e11ac9b 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir @@ -38,15 +38,15 @@ body: | ; GCN: liveins: $sgpr0, $sgpr35, $vgpr8, $vgpr9 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr1 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr8, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr9, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr8, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_ST $vgpr9, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc ; GCN-NEXT: renamable $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4) ; GCN-NEXT: S_NOP 0, implicit-def $vgpr0, implicit-def $vgpr1, implicit-def $vgpr2, implicit-def $vgpr3, implicit-def $vgpr4, implicit-def $vgpr5, implicit-def $vgpr6, implicit-def $vgpr7 ; GCN-NEXT: $sgpr1 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr8 = SCRATCH_LOAD_DWORD_ST 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr8(tied-def 0) :: (load (s32) from %stack.0, addrspace 5) - ; GCN-NEXT: $vgpr9 = SCRATCH_LOAD_DWORD_ST 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GCN-NEXT: $vgpr8 = SCRATCH_LOAD_DWORD_ST 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr8(tied-def 0) :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr9 = SCRATCH_LOAD_DWORD_ST 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1 ; GCN-NEXT: SI_CS_CHAIN_TC_W32 killed renamable $sgpr4_sgpr5, @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8 renamable $sgpr4_sgpr5 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @callee + 4, target-flags(amdgpu-gotprel32-hi) @callee + 12, implicit-def dead $scc diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir index 4b4e9f1d81ec6..f35a34659e6dd 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir @@ -21,8 +21,8 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v1 ; MUBUF: $vgpr0 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v1 @@ -35,8 +35,8 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v1 ; FLATSCR: $vgpr0 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v1 @@ -49,8 +49,8 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v1 ; MUBUF-GFX90A: $vgpr0 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v1 @@ -63,8 +63,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v1 ; FLATSCR-GFX90A: $vgpr0 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v1 @@ -94,10 +94,10 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v2 ; MUBUF: $vgpr0_vgpr1 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v2 @@ -112,8 +112,8 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v2 ; FLATSCR: $vgpr0_vgpr1 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v2 @@ -128,10 +128,10 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v2 ; MUBUF-GFX90A: $vgpr0_vgpr1 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v2 @@ -146,8 +146,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v2 ; FLATSCR-GFX90A: $vgpr0_vgpr1 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v2 @@ -179,12 +179,12 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v3 ; MUBUF: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v3 @@ -201,8 +201,8 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v3 ; FLATSCR: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v3 @@ -219,12 +219,12 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v3 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v3 @@ -241,8 +241,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v3 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v3 @@ -276,14 +276,14 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v4 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v4 @@ -302,8 +302,8 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v4 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v4 @@ -322,14 +322,14 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v4 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v4 @@ -348,8 +348,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v4 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v4 @@ -385,16 +385,16 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v5 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v5 @@ -415,10 +415,10 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v5 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v5 @@ -439,16 +439,16 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v5 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v5 @@ -469,10 +469,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v5 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v5 @@ -510,18 +510,18 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v6 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v6 @@ -544,10 +544,10 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v6 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s64) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v6 @@ -570,18 +570,18 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v6 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v6 @@ -604,10 +604,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v6 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s64) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v6 @@ -647,20 +647,20 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v7 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v7 @@ -685,10 +685,10 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v7 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr4_vgpr5_vgpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s96) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr4_vgpr5_vgpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" store (s96) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v7 @@ -713,20 +713,20 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v7 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v7 @@ -751,10 +751,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v7 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr4_vgpr5_vgpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (store (s96) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr4_vgpr5_vgpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" store (s96) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v7 @@ -796,22 +796,22 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v8 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v8 @@ -838,10 +838,10 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v8 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v8 @@ -868,22 +868,22 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v8 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v8 @@ -910,10 +910,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v8 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v8 @@ -957,38 +957,38 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v16 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v16 @@ -1031,14 +1031,14 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v16 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v16 @@ -1081,38 +1081,38 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v16 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v16 @@ -1155,14 +1155,14 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v16 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v16 @@ -1222,70 +1222,70 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_av_v32 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 64, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 68, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 72, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 76, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 80, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 84, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 88, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 92, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 96, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 100, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 104, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 108, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 112, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 116, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 120, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) - ; MUBUF-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 64, addrspace 5) - ; MUBUF-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 68, addrspace 5) - ; MUBUF-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 72, addrspace 5) - ; MUBUF-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 76, addrspace 5) - ; MUBUF-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 80, addrspace 5) - ; MUBUF-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 84, addrspace 5) - ; MUBUF-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 88, addrspace 5) - ; MUBUF-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 92, addrspace 5) - ; MUBUF-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 96, addrspace 5) - ; MUBUF-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 100, addrspace 5) - ; MUBUF-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 104, addrspace 5) - ; MUBUF-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 108, addrspace 5) - ; MUBUF-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 112, addrspace 5) - ; MUBUF-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 116, addrspace 5) - ; MUBUF-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 120, addrspace 5) - ; MUBUF-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 124, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) + ; MUBUF-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) + ; MUBUF-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) + ; MUBUF-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) + ; MUBUF-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) + ; MUBUF-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) + ; MUBUF-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) + ; MUBUF-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) + ; MUBUF-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) + ; MUBUF-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) + ; MUBUF-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) + ; MUBUF-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) + ; MUBUF-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) + ; MUBUF-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) + ; MUBUF-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) + ; MUBUF-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_av_v32 @@ -1360,22 +1360,22 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_av_v32 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr16_vgpr17_vgpr18_vgpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr24_vgpr25_vgpr26_vgpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr28_vgpr29_vgpr30_vgpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0 + 112, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr24_vgpr25_vgpr26_vgpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr28_vgpr29_vgpr30_vgpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr16_vgpr17_vgpr18_vgpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr24_vgpr25_vgpr26_vgpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr28_vgpr29_vgpr30_vgpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr24_vgpr25_vgpr26_vgpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr28_vgpr29_vgpr30_vgpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 112, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_av_v32 @@ -1450,70 +1450,70 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_v32 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 64, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 68, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 72, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 76, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 80, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 84, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 88, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 92, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 96, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 100, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 104, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 108, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 112, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 116, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 120, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 64, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 68, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 72, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 76, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 80, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 84, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 88, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 92, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 96, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 100, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 104, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 108, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 112, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 116, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 120, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 124, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_v32 @@ -1588,22 +1588,22 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_v32 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr16_vgpr17_vgpr18_vgpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr24_vgpr25_vgpr26_vgpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr28_vgpr29_vgpr30_vgpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0 + 112, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr24_vgpr25_vgpr26_vgpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr28_vgpr29_vgpr30_vgpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr16_vgpr17_vgpr18_vgpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr24_vgpr25_vgpr26_vgpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr28_vgpr29_vgpr30_vgpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr24_vgpr25_vgpr26_vgpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr28_vgpr29_vgpr30_vgpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 112, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_v32 @@ -1696,8 +1696,8 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a1 ; MUBUF: $agpr0 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -1712,8 +1712,8 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a1 ; FLATSCR: $agpr0 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -1727,8 +1727,8 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a1 ; MUBUF-GFX90A: $agpr0 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a1 @@ -1741,8 +1741,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a1 ; FLATSCR-GFX90A: $agpr0 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a1 @@ -1773,12 +1773,12 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a2 ; MUBUF: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -1795,12 +1795,12 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a2 ; FLATSCR: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -1816,10 +1816,10 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a2 ; MUBUF-GFX90A: $agpr0_agpr1 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a2 @@ -1834,8 +1834,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a2 ; FLATSCR-GFX90A: $agpr0_agpr1 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a2 @@ -1868,16 +1868,16 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a3 ; MUBUF: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -1896,16 +1896,16 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a3 ; FLATSCR: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -1923,12 +1923,12 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a3 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a3 @@ -1945,8 +1945,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a3 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a3 @@ -1981,20 +1981,20 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a4 ; MUBUF: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2015,20 +2015,20 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a4 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2048,14 +2048,14 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a4 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a4 @@ -2074,8 +2074,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a4 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a4 @@ -2112,24 +2112,24 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a5 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2152,24 +2152,24 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a5 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2191,16 +2191,16 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a5 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a5 @@ -2221,10 +2221,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a5 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a5 @@ -2263,28 +2263,28 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a6 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2309,28 +2309,28 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a6 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2354,18 +2354,18 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a6 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a6 @@ -2388,10 +2388,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a6 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr4_agpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr4_agpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s64) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a6 @@ -2432,32 +2432,32 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a7 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2484,32 +2484,32 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a7 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0 + 24, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2535,20 +2535,20 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a7 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a7 @@ -2573,10 +2573,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a7 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr4_agpr5_agpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (store (s96) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr4_agpr5_agpr6, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" store (s96) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a7 @@ -2619,36 +2619,36 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a8 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2677,36 +2677,36 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a8 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2734,22 +2734,22 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a8 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a8 @@ -2776,10 +2776,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a8 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a8 @@ -2824,40 +2824,40 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a9 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2888,40 +2888,40 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a9 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0 + 32, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2951,24 +2951,24 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a9 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a9 @@ -2997,12 +2997,12 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a9 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr8, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (store (s32) into %stack.0 + 32, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr8 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr8, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr8 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a9 @@ -3049,44 +3049,44 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a10 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -3119,44 +3119,44 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a10 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0 + 36, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -3188,26 +3188,26 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a10 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a10 @@ -3238,12 +3238,12 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a10 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr8_agpr9, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (store (s64) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr8_agpr9, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" store (s64) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0 + 32, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a10 @@ -3292,48 +3292,48 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a11 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -3368,48 +3368,48 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a11 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0 + 40, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -3443,28 +3443,28 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a11 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a11 @@ -3497,12 +3497,12 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a11 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr8_agpr9_agpr10, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (store (s96) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr8_agpr9_agpr10, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" store (s96) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0 + 32, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a11 @@ -3553,52 +3553,52 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a12 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -3635,52 +3635,52 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a12 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0 + 44, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -3716,30 +3716,30 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a12 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a12 @@ -3774,12 +3774,12 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a12 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a12 @@ -3832,68 +3832,68 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a16 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr12, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr14, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr15, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) ; MUBUF-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) ; MUBUF-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) ; MUBUF-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -3938,68 +3938,68 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a16 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr12, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 48, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 52, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr14, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 56, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr15, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 48, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) ; FLATSCR-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 52, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) ; FLATSCR-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 56, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) ; FLATSCR-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 60, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; FLATSCR-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -4043,38 +4043,38 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a16 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a16 @@ -4117,14 +4117,14 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a16 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr12_agpr13_agpr14_agpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr12_agpr13_agpr14_agpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr12_agpr13_agpr14_agpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr12_agpr13_agpr14_agpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a16 @@ -4185,132 +4185,132 @@ body: | ; MUBUF-LABEL: name: test_spill_av_a32 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr12, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr14, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr15, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr16, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 64, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr17, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 68, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr18, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 72, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr19, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 76, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr20, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 80, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr21, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 84, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr22, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 88, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr23, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 92, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr24, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 96, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr25, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 100, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr26, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 104, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr27, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 108, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr28, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 112, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr29, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 116, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr30, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 120, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr31, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) ; MUBUF-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) ; MUBUF-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) ; MUBUF-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 64, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) ; MUBUF-NEXT: $agpr16 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 68, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) ; MUBUF-NEXT: $agpr17 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 72, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) ; MUBUF-NEXT: $agpr18 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 76, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) ; MUBUF-NEXT: $agpr19 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 80, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) ; MUBUF-NEXT: $agpr20 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 84, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) ; MUBUF-NEXT: $agpr21 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 88, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) ; MUBUF-NEXT: $agpr22 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 92, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) ; MUBUF-NEXT: $agpr23 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 96, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) ; MUBUF-NEXT: $agpr24 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 100, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) ; MUBUF-NEXT: $agpr25 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 104, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) ; MUBUF-NEXT: $agpr26 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 108, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) ; MUBUF-NEXT: $agpr27 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 112, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) ; MUBUF-NEXT: $agpr28 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 116, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) ; MUBUF-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 120, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) ; MUBUF-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 124, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; MUBUF-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -4387,132 +4387,132 @@ body: | ; FLATSCR-LABEL: name: test_spill_av_a32 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr12, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 48, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 52, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr14, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 56, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr15, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 60, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr16, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 64, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr17, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 68, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr18, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 72, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr19, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 76, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr20, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 80, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr21, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 84, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr22, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 88, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr23, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 92, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr24, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 96, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr25, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 100, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr26, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 104, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr27, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 108, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr28, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 112, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr29, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 116, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr30, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 120, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr31, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 48, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) ; FLATSCR-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 52, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) ; FLATSCR-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 56, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) ; FLATSCR-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 60, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; FLATSCR-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 64, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) ; FLATSCR-NEXT: $agpr16 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 68, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) ; FLATSCR-NEXT: $agpr17 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 72, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) ; FLATSCR-NEXT: $agpr18 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 76, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) ; FLATSCR-NEXT: $agpr19 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 80, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) ; FLATSCR-NEXT: $agpr20 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 84, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) ; FLATSCR-NEXT: $agpr21 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 88, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) ; FLATSCR-NEXT: $agpr22 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 92, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) ; FLATSCR-NEXT: $agpr23 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 96, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) ; FLATSCR-NEXT: $agpr24 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 100, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) ; FLATSCR-NEXT: $agpr25 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 104, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) ; FLATSCR-NEXT: $agpr26 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 108, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) ; FLATSCR-NEXT: $agpr27 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 112, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) ; FLATSCR-NEXT: $agpr28 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 116, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) ; FLATSCR-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 120, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) ; FLATSCR-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 124, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; FLATSCR-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -4588,70 +4588,70 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_av_a32 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 64, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 68, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 72, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 76, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 80, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 84, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 88, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 92, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 96, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 100, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 104, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 108, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 112, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 116, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 120, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 64, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 68, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 72, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 76, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 80, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 84, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 88, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 92, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 96, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 100, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 104, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 108, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 112, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 116, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 120, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 124, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_av_a32 @@ -4726,22 +4726,22 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_av_a32 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr12_agpr13_agpr14_agpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr16_agpr17_agpr18_agpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr20_agpr21_agpr22_agpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr24_agpr25_agpr26_agpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr28_agpr29_agpr30_agpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s128) into %stack.0 + 112, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr12_agpr13_agpr14_agpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr16_agpr17_agpr18_agpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr20_agpr21_agpr22_agpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr24_agpr25_agpr26_agpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr28_agpr29_agpr30_agpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr12_agpr13_agpr14_agpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr16_agpr17_agpr18_agpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr20_agpr21_agpr22_agpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr24_agpr25_agpr26_agpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr28_agpr29_agpr30_agpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr12_agpr13_agpr14_agpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr16_agpr17_agpr18_agpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr20_agpr21_agpr22_agpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr24_agpr25_agpr26_agpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr28_agpr29_agpr30_agpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 112, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_av_a32 diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir new file mode 100644 index 0000000000000..6645af43f9b9f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir @@ -0,0 +1,32 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck %s + +# Test that the buildSpillLoadStore does correct calculations for Maxoffset in case of +# spill instructions. Must emit offset within 13 bit signed number range. + +--- +name: test_spill_v6_offset_overflow +tracksRegLiveness: true +fixedStack: + - { id: 0, type: spill-slot, offset: 4084, size: 24, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: [] +machineFunctionInfo: + hasSpilledVGPRs: true + stackPtrOffsetReg: '$sgpr32' +body: | + bb.0: + liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 + + ; CHECK-LABEL: name: test_spill_v6_offset_overflow + ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $sgpr0 = S_ADD_I32 $sgpr32, 4084, implicit-def dead $scc + ; CHECK-NEXT: SCRATCH_STORE_DWORDX4_SADDR $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s128) into %fixed-stack.0, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR $vgpr4_vgpr5, killed $sgpr0, 16, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s64) into %fixed-stack.0 + 16, align 4, addrspace 5) + ; CHECK-NEXT: S_ENDPGM 0 + SI_SPILL_AV192_SAVE $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %fixed-stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %fixed-stack.0, align 4, addrspace 5) + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir index c9208bfa15c63..4b25392aaa797 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir @@ -60,9 +60,9 @@ body: | ; MUBUF-V2A: liveins: $agpr0 ; MUBUF-V2A-NEXT: {{ $}} ; MUBUF-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit killed $vgpr0_vgpr1 - ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $vgpr0_vgpr1 ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; @@ -71,9 +71,9 @@ body: | ; FLATSCR-V2A-NEXT: {{ $}} ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1 - ; FLATSCR-V2A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-V2A-NEXT: S_ENDPGM 0 $vgpr0_vgpr1 = IMPLICIT_DEF SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, align 4, addrspace 5) @@ -97,11 +97,11 @@ body: | ; MUBUF-V2A: liveins: $agpr0 ; MUBUF-V2A-NEXT: {{ $}} ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 - ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 ; MUBUF-V2A-NEXT: S_ENDPGM 0 ; @@ -110,9 +110,9 @@ body: | ; FLATSCR-V2A-NEXT: {{ $}} ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s64) into %stack.0, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 - ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (load (s64) from %stack.0, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: S_ENDPGM 0 $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF SI_SPILL_V96_SAVE killed $vgpr0_vgpr1_vgpr2, %stack.0, $sgpr32, 0, implicit $exec :: (store (s96) into %stack.0, align 4, addrspace 5) @@ -136,11 +136,11 @@ body: | ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-V2A-NEXT: {{ $}} ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 - ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec ; MUBUF-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec ; MUBUF-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 @@ -153,11 +153,11 @@ body: | ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; FLATSCR-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; FLATSCR-V2A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-V2A-NEXT: S_ENDPGM 0 $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5) @@ -181,13 +181,13 @@ body: | ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2 ; MUBUF-V2A-NEXT: {{ $}} ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr4, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 - ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec ; MUBUF-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec ; MUBUF-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 @@ -199,11 +199,11 @@ body: | ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s64) into %stack.0, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr4, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 - ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s64) from %stack.0, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 ; FLATSCR-V2A-NEXT: S_ENDPGM 0 $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF @@ -228,13 +228,13 @@ body: | ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-V2A-NEXT: {{ $}} ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec ; MUBUF-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr4, implicit $exec ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr5, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 - ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr4, implicit $exec ; MUBUF-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec ; MUBUF-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec @@ -249,13 +249,13 @@ body: | ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr5, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr4, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr4, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 - ; FLATSCR-V2A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 ; FLATSCR-V2A-NEXT: S_ENDPGM 0 @@ -281,18 +281,18 @@ body: | ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; MUBUF-V2A-NEXT: {{ $}} ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr4, implicit $exec ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr5, implicit $exec ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr6, implicit $exec ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr7, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 - ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-V2A-NEXT: $vgpr4 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec ; MUBUF-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec ; MUBUF-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec @@ -303,12 +303,12 @@ body: | ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3 ; FLATSCR-V2A-NEXT: {{ $}} ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr7, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr6, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr5, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr4, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 - ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $vgpr7 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-V2A-NEXT: $vgpr6 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 ; FLATSCR-V2A-NEXT: $vgpr5 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 @@ -336,33 +336,33 @@ body: | ; MUBUF-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; MUBUF-V2A-NEXT: {{ $}} ; MUBUF-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-V2A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; MUBUF-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr11, implicit $exec ; MUBUF-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr12, implicit $exec ; MUBUF-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr13, implicit $exec ; MUBUF-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr14, implicit $exec ; MUBUF-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr15, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 - ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-V2A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-V2A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; MUBUF-V2A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 $agpr4, implicit $exec ; MUBUF-V2A-NEXT: $vgpr12 = V_ACCVGPR_READ_B32_e64 $agpr3, implicit $exec ; MUBUF-V2A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec @@ -374,18 +374,18 @@ body: | ; FLATSCR-V2A: liveins: $agpr0, $agpr1, $agpr2, $agpr3, $agpr4 ; FLATSCR-V2A-NEXT: {{ $}} ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr11, implicit $exec - ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr8_vgpr9_vgpr10, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr8_vgpr9_vgpr10, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.0 + 32, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr15, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-V2A-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr14, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-V2A-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr13, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-V2A-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr12, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 - ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-V2A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $vgpr11 = V_ACCVGPR_READ_B32_e64 $agpr4, implicit $exec - ; FLATSCR-V2A-NEXT: $vgpr8_vgpr9_vgpr10 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-V2A-NEXT: $vgpr8_vgpr9_vgpr10 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0 + 32, align 4, addrspace 5) ; FLATSCR-V2A-NEXT: $vgpr15 = V_ACCVGPR_READ_B32_e64 $agpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-V2A-NEXT: $vgpr14 = V_ACCVGPR_READ_B32_e64 $agpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 ; FLATSCR-V2A-NEXT: $vgpr13 = V_ACCVGPR_READ_B32_e64 $agpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 diff --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir index 2fbe08300af57..8c6283dc2dbc5 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill.mir @@ -21,8 +21,8 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v1 ; MUBUF: $vgpr0 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v1 @@ -35,8 +35,8 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v1 ; FLATSCR: $vgpr0 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v1 @@ -49,8 +49,8 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v1 ; MUBUF-GFX90A: $vgpr0 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v1 @@ -63,8 +63,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v1 ; FLATSCR-GFX90A: $vgpr0 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v1 @@ -94,10 +94,10 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v2 ; MUBUF: $vgpr0_vgpr1 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v2 @@ -112,8 +112,8 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v2 ; FLATSCR: $vgpr0_vgpr1 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v2 @@ -128,10 +128,10 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v2 ; MUBUF-GFX90A: $vgpr0_vgpr1 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v2 @@ -146,8 +146,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v2 ; FLATSCR-GFX90A: $vgpr0_vgpr1 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v2 @@ -179,12 +179,12 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v3 ; MUBUF: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v3 @@ -201,8 +201,8 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v3 ; FLATSCR: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v3 @@ -219,12 +219,12 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v3 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v3 @@ -241,8 +241,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v3 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v3 @@ -276,14 +276,14 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v4 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v4 @@ -302,8 +302,8 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v4 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v4 @@ -322,14 +322,14 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v4 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v4 @@ -348,8 +348,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v4 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v4 @@ -385,16 +385,16 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v5 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v5 @@ -415,10 +415,10 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v5 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v5 @@ -439,16 +439,16 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v5 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v5 @@ -469,10 +469,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v5 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v5 @@ -510,18 +510,18 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v6 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v6 @@ -544,10 +544,10 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v6 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s64) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v6 @@ -570,18 +570,18 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v6 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v6 @@ -604,10 +604,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v6 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr4_vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" store (s64) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v6 @@ -647,22 +647,22 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v8 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v8 @@ -689,10 +689,10 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v8 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v8 @@ -719,22 +719,22 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v8 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v8 @@ -761,10 +761,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v8 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v8 @@ -808,38 +808,38 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v16 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v16 @@ -882,14 +882,14 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v16 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v16 @@ -932,38 +932,38 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v16 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v16 @@ -1006,14 +1006,14 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v16 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v16 @@ -1073,70 +1073,70 @@ body: | bb.0.entry: ; MUBUF-LABEL: name: test_spill_v32 ; MUBUF: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 64, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 68, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 72, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 76, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 80, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 84, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 88, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 92, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 96, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 100, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 104, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 108, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 112, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 116, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 120, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) - ; MUBUF-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 64, addrspace 5) - ; MUBUF-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 68, addrspace 5) - ; MUBUF-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 72, addrspace 5) - ; MUBUF-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 76, addrspace 5) - ; MUBUF-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 80, addrspace 5) - ; MUBUF-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 84, addrspace 5) - ; MUBUF-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 88, addrspace 5) - ; MUBUF-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 92, addrspace 5) - ; MUBUF-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 96, addrspace 5) - ; MUBUF-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 100, addrspace 5) - ; MUBUF-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 104, addrspace 5) - ; MUBUF-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 108, addrspace 5) - ; MUBUF-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 112, addrspace 5) - ; MUBUF-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 116, addrspace 5) - ; MUBUF-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 120, addrspace 5) - ; MUBUF-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 124, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) + ; MUBUF-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) + ; MUBUF-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) + ; MUBUF-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) + ; MUBUF-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) + ; MUBUF-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) + ; MUBUF-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) + ; MUBUF-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) + ; MUBUF-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) + ; MUBUF-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) + ; MUBUF-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) + ; MUBUF-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) + ; MUBUF-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) + ; MUBUF-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) + ; MUBUF-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) + ; MUBUF-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; MUBUF-NEXT: S_ENDPGM 0 ; ; MUBUF-V2A-LABEL: name: test_spill_v32 @@ -1211,22 +1211,22 @@ body: | ; ; FLATSCR-LABEL: name: test_spill_v32 ; FLATSCR: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr16_vgpr17_vgpr18_vgpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr24_vgpr25_vgpr26_vgpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr28_vgpr29_vgpr30_vgpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0 + 112, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr24_vgpr25_vgpr26_vgpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr28_vgpr29_vgpr30_vgpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr16_vgpr17_vgpr18_vgpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr24_vgpr25_vgpr26_vgpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr28_vgpr29_vgpr30_vgpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr24_vgpr25_vgpr26_vgpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr28_vgpr29_vgpr30_vgpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 112, align 4, addrspace 5) ; FLATSCR-NEXT: S_ENDPGM 0 ; ; FLATSCR-V2A-LABEL: name: test_spill_v32 @@ -1301,70 +1301,70 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_v32 ; MUBUF-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 64, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 68, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 72, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 76, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 80, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 84, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 88, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 92, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 96, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 100, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 104, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 108, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 112, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 116, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 120, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 64, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 68, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 72, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 76, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 80, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 84, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 88, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 92, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 96, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 100, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 104, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 108, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 112, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 116, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 120, addrspace 5) - ; MUBUF-GFX90A-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 124, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) + ; MUBUF-GFX90A-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_v32 @@ -1439,22 +1439,22 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_v32 ; FLATSCR-GFX90A: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr16_vgpr17_vgpr18_vgpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr24_vgpr25_vgpr26_vgpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr28_vgpr29_vgpr30_vgpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (store (s128) into %stack.0 + 112, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr24_vgpr25_vgpr26_vgpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $vgpr28_vgpr29_vgpr30_vgpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr4_vgpr5_vgpr6_vgpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr8_vgpr9_vgpr10_vgpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr12_vgpr13_vgpr14_vgpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr16_vgpr17_vgpr18_vgpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr24_vgpr25_vgpr26_vgpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr28_vgpr29_vgpr30_vgpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr4_vgpr5_vgpr6_vgpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr8_vgpr9_vgpr10_vgpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr12_vgpr13_vgpr14_vgpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr16_vgpr17_vgpr18_vgpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr24_vgpr25_vgpr26_vgpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $vgpr28_vgpr29_vgpr30_vgpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 112, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_v32 @@ -1547,8 +1547,8 @@ body: | ; MUBUF-LABEL: name: test_spill_a1 ; MUBUF: $agpr0 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -1563,8 +1563,8 @@ body: | ; FLATSCR-LABEL: name: test_spill_a1 ; FLATSCR: $agpr0 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -1578,8 +1578,8 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a1 ; MUBUF-GFX90A: $agpr0 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a1 @@ -1592,8 +1592,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a1 ; FLATSCR-GFX90A: $agpr0 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a1 @@ -1624,12 +1624,12 @@ body: | ; MUBUF-LABEL: name: test_spill_a2 ; MUBUF: $agpr0_agpr1 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -1646,12 +1646,12 @@ body: | ; FLATSCR-LABEL: name: test_spill_a2 ; FLATSCR: $agpr0_agpr1 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -1667,10 +1667,10 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a2 ; MUBUF-GFX90A: $agpr0_agpr1 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a2 @@ -1685,8 +1685,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a2 ; FLATSCR-GFX90A: $agpr0_agpr1 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a2 @@ -1719,16 +1719,16 @@ body: | ; MUBUF-LABEL: name: test_spill_a3 ; MUBUF: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -1747,16 +1747,16 @@ body: | ; FLATSCR-LABEL: name: test_spill_a3 ; FLATSCR: $agpr0_agpr1_agpr2 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -1774,12 +1774,12 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a3 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2, implicit $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a3 @@ -1796,8 +1796,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a3 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a3 @@ -1832,20 +1832,20 @@ body: | ; MUBUF-LABEL: name: test_spill_a4 ; MUBUF: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -1866,20 +1866,20 @@ body: | ; FLATSCR-LABEL: name: test_spill_a4 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -1899,14 +1899,14 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a4 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a4 @@ -1925,8 +1925,8 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a4 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a4 @@ -1963,24 +1963,24 @@ body: | ; MUBUF-LABEL: name: test_spill_a5 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2003,24 +2003,24 @@ body: | ; FLATSCR-LABEL: name: test_spill_a5 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2042,16 +2042,16 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a5 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a5 @@ -2072,10 +2072,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a5 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: (store (s32) into %stack.0 + 16, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4, implicit $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr4, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a5 @@ -2114,28 +2114,28 @@ body: | ; MUBUF-LABEL: name: test_spill_a6 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2160,28 +2160,28 @@ body: | ; FLATSCR-LABEL: name: test_spill_a6 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2205,18 +2205,18 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a6 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a6 @@ -2239,10 +2239,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a6 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr4_agpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (store (s64) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr4_agpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" store (s64) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a6 @@ -2283,36 +2283,36 @@ body: | ; MUBUF-LABEL: name: test_spill_a8 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2341,36 +2341,36 @@ body: | ; FLATSCR-LABEL: name: test_spill_a8 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2398,22 +2398,22 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a8 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a8 @@ -2440,10 +2440,10 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a8 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a8 @@ -2488,68 +2488,68 @@ body: | ; MUBUF-LABEL: name: test_spill_a16 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr12, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr14, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr15, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) ; MUBUF-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) ; MUBUF-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) ; MUBUF-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -2594,68 +2594,68 @@ body: | ; FLATSCR-LABEL: name: test_spill_a16 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr12, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 48, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 52, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr14, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 56, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr15, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 48, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) ; FLATSCR-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 52, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) ; FLATSCR-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 56, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) ; FLATSCR-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 60, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; FLATSCR-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -2699,38 +2699,38 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a16 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a16 @@ -2773,14 +2773,14 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a16 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr12_agpr13_agpr14_agpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr12_agpr13_agpr14_agpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr12_agpr13_agpr14_agpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr12_agpr13_agpr14_agpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a16 @@ -2841,132 +2841,132 @@ body: | ; MUBUF-LABEL: name: test_spill_a32 ; MUBUF: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr12, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr14, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr15, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr16, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 64, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr17, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 68, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr18, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 72, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr19, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 76, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr20, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 80, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr21, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 84, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr22, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 88, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr23, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 92, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr24, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 96, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr25, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 100, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr26, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 104, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr27, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 108, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr28, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 112, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr29, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 116, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr30, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 120, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) ; MUBUF-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr31, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; MUBUF-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; MUBUF-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; MUBUF-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; MUBUF-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; MUBUF-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; MUBUF-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; MUBUF-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; MUBUF-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; MUBUF-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; MUBUF-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; MUBUF-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; MUBUF-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) ; MUBUF-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) ; MUBUF-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) ; MUBUF-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; MUBUF-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 64, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) ; MUBUF-NEXT: $agpr16 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 68, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) ; MUBUF-NEXT: $agpr17 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 72, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) ; MUBUF-NEXT: $agpr18 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 76, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) ; MUBUF-NEXT: $agpr19 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 80, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) ; MUBUF-NEXT: $agpr20 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 84, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) ; MUBUF-NEXT: $agpr21 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 88, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) ; MUBUF-NEXT: $agpr22 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 92, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) ; MUBUF-NEXT: $agpr23 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 96, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) ; MUBUF-NEXT: $agpr24 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 100, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) ; MUBUF-NEXT: $agpr25 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 104, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) ; MUBUF-NEXT: $agpr26 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 108, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) ; MUBUF-NEXT: $agpr27 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 112, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) ; MUBUF-NEXT: $agpr28 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 116, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) ; MUBUF-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 120, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) ; MUBUF-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 124, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; MUBUF-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; MUBUF-NEXT: S_ENDPGM 0 ; @@ -3043,132 +3043,132 @@ body: | ; FLATSCR-LABEL: name: test_spill_a32 ; FLATSCR: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr4, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr5, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr6, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr7, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr8, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr9, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr10, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr11, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr12, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 48, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr13, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 52, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr14, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 56, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr15, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 60, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr16, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 64, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr17, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 68, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr18, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 72, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr19, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 76, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr20, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 80, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr21, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 84, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr22, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 88, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr23, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 92, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr24, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 96, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr25, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 100, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr26, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 104, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr27, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 108, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr28, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 112, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr29, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 116, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr30, implicit $exec - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0 + 120, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) ; FLATSCR-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr31, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 124, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; FLATSCR-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 4, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) ; FLATSCR-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 8, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) ; FLATSCR-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 12, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) ; FLATSCR-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 16, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) ; FLATSCR-NEXT: $agpr4 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 20, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) ; FLATSCR-NEXT: $agpr5 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 24, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) ; FLATSCR-NEXT: $agpr6 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 28, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) ; FLATSCR-NEXT: $agpr7 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 32, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) ; FLATSCR-NEXT: $agpr8 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 36, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 36, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) ; FLATSCR-NEXT: $agpr9 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 40, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 40, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) ; FLATSCR-NEXT: $agpr10 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 44, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) ; FLATSCR-NEXT: $agpr11 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 48, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) ; FLATSCR-NEXT: $agpr12 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 52, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 52, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) ; FLATSCR-NEXT: $agpr13 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 56, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 56, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) ; FLATSCR-NEXT: $agpr14 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 60, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 60, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) ; FLATSCR-NEXT: $agpr15 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 64, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) ; FLATSCR-NEXT: $agpr16 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 68, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 68, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) ; FLATSCR-NEXT: $agpr17 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 72, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 72, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) ; FLATSCR-NEXT: $agpr18 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 76, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 76, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) ; FLATSCR-NEXT: $agpr19 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 80, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) ; FLATSCR-NEXT: $agpr20 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 84, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 84, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) ; FLATSCR-NEXT: $agpr21 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 88, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 88, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) ; FLATSCR-NEXT: $agpr22 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 92, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 92, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) ; FLATSCR-NEXT: $agpr23 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 96, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) ; FLATSCR-NEXT: $agpr24 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 100, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 100, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) ; FLATSCR-NEXT: $agpr25 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 104, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 104, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) ; FLATSCR-NEXT: $agpr26 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 108, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 108, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) ; FLATSCR-NEXT: $agpr27 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 112, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) ; FLATSCR-NEXT: $agpr28 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 116, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 116, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) ; FLATSCR-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 120, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 120, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) ; FLATSCR-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0 + 124, addrspace 5) + ; FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 124, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; FLATSCR-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec ; FLATSCR-NEXT: S_ENDPGM 0 ; @@ -3244,70 +3244,70 @@ body: | ; ; MUBUF-GFX90A-LABEL: name: test_spill_a32 ; MUBUF-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 64, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 68, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 72, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 76, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 80, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 84, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 88, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 92, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 96, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 100, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 104, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 108, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 112, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 116, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 120, addrspace 5) - ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s32) into %stack.0 + 124, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (load (s32) from %stack.0, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 4, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 8, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 12, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 16, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 20, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 24, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 28, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 32, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 36, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 40, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 44, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 48, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 52, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 56, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 60, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 64, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 68, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 72, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 76, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 80, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 84, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 88, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 92, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 96, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 100, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 104, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 108, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 112, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 116, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 120, addrspace 5) - ; MUBUF-GFX90A-NEXT: $agpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: (load (s32) from %stack.0 + 124, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr4, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr6, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr7, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr8, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr9, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr10, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr11, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr12, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr13, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr14, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr15, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr16, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 64, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr17, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 68, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr18, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 72, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr19, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 76, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr20, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 80, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr21, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 84, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr22, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 88, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr23, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 92, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr24, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 96, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr25, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 100, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr26, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 104, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr27, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 108, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr28, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 112, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr29, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 116, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr30, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 120, addrspace 5) + ; MUBUF-GFX90A-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr31, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 124, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 4, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 8, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 12, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 16, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 20, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 24, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 28, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 32, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 36, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 40, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 44, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 48, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 52, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 56, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 60, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 64, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 68, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 72, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 76, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 80, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 84, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 88, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 92, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 96, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 100, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 104, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 108, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 112, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 116, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 120, addrspace 5) + ; MUBUF-GFX90A-NEXT: $agpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0 + 124, addrspace 5) ; MUBUF-GFX90A-NEXT: S_ENDPGM 0 ; ; MUBUF-GFX90A-V2A-LABEL: name: test_spill_a32 @@ -3382,22 +3382,22 @@ body: | ; ; FLATSCR-GFX90A-LABEL: name: test_spill_a32 ; FLATSCR-GFX90A: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = IMPLICIT_DEF - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s128) into %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr12_agpr13_agpr14_agpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr16_agpr17_agpr18_agpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr20_agpr21_agpr22_agpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr24_agpr25_agpr26_agpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr28_agpr29_agpr30_agpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (store (s128) into %stack.0 + 112, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: (load (s128) from %stack.0, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 16, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 32, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr12_agpr13_agpr14_agpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 48, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr16_agpr17_agpr18_agpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 64, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr20_agpr21_agpr22_agpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 80, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr24_agpr25_agpr26_agpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 96, align 4, addrspace 5) - ; FLATSCR-GFX90A-NEXT: $agpr28_agpr29_agpr30_agpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr0_agpr1_agpr2_agpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr4_agpr5_agpr6_agpr7, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr8_agpr9_agpr10_agpr11, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr12_agpr13_agpr14_agpr15, $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr16_agpr17_agpr18_agpr19, $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr20_agpr21_agpr22_agpr23, $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr24_agpr25_agpr26_agpr27, $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $agpr28_agpr29_agpr30_agpr31, $sgpr32, 112, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" store (s128) into %stack.0 + 112, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr0_agpr1_agpr2_agpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 :: ("amdgpu-thread-private" load (s128) from %stack.0, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr4_agpr5_agpr6_agpr7 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 16, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr8_agpr9_agpr10_agpr11 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 32, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr12_agpr13_agpr14_agpr15 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 48, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 48, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr16_agpr17_agpr18_agpr19 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 64, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr20_agpr21_agpr22_agpr23 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 80, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 80, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr24_agpr25_agpr26_agpr27 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 96, align 4, addrspace 5) + ; FLATSCR-GFX90A-NEXT: $agpr28_agpr29_agpr30_agpr31 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 112, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.0 + 112, align 4, addrspace 5) ; FLATSCR-GFX90A-NEXT: S_ENDPGM 0 ; ; FLATSCR-GFX90A-V2A-LABEL: name: test_spill_a32 diff --git a/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir b/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir index aa4428f3da4eb..17b3e506f5300 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-reg-scavenger-position.mir @@ -30,14 +30,14 @@ body: | ; CHECK-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $sgpr4, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr4 = S_MOV_B32 524288 - ; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, align 8192, addrspace 5) + ; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, align 8192, addrspace 5) ; CHECK-NEXT: S_BRANCH %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: liveins: $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr4 = S_MOV_B32 524288 - ; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, align 8192, addrspace 5) + ; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr4, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, align 8192, addrspace 5) ; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr0 bb.0: $vgpr0 = SI_SPILL_V32_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir index 63a4759d8e740..1e3158001b6f6 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-scavenge-vgpr-spill.mir @@ -24,14 +24,14 @@ body: | liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX8-LABEL: name: pei_scavenge_vgpr_spill - ; GFX8: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 + ; GFX8: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr2 ; GFX8-NEXT: {{ $}} ; GFX8-NEXT: $sgpr4 = COPY $sgpr33 ; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX8-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX8-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX8-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 1048832, implicit-def dead $scc - ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX8-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, undef $vgpr2 ; GFX8-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr34, 1, undef $vgpr2 @@ -49,20 +49,20 @@ body: | ; GFX8-NEXT: $sgpr34 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 1 ; GFX8-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX8-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 1048832, implicit-def dead $scc - ; GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX8-NEXT: $sgpr33 = COPY $sgpr4 ; GFX8-NEXT: S_ENDPGM 0, amdgpu_allvgprs ; ; GFX9-LABEL: name: pei_scavenge_vgpr_spill - ; GFX9: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 + ; GFX9: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr2 ; GFX9-NEXT: {{ $}} ; GFX9-NEXT: $sgpr4 = COPY $sgpr33 ; GFX9-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc ; GFX9-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294443008, implicit-def dead $scc ; GFX9-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX9-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 1048832, implicit-def dead $scc - ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX9-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, undef $vgpr2 ; GFX9-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr34, 1, undef $vgpr2 @@ -78,20 +78,20 @@ body: | ; GFX9-NEXT: $sgpr34 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 1 ; GFX9-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX9-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 1048832, implicit-def dead $scc - ; GFX9-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; GFX9-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, killed $sgpr5, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX9-NEXT: $sgpr33 = COPY $sgpr4 ; GFX9-NEXT: S_ENDPGM 0, amdgpu_allvgprs ; ; GFX9-FLATSCR-LABEL: name: pei_scavenge_vgpr_spill - ; GFX9-FLATSCR: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 + ; GFX9-FLATSCR: liveins: $vgpr2, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr2 ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: $sgpr4 = COPY $sgpr33 ; GFX9-FLATSCR-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 8191, implicit-def $scc ; GFX9-FLATSCR-NEXT: $sgpr33 = frame-setup S_AND_B32 killed $sgpr33, 4294959104, implicit-def dead $scc ; GFX9-FLATSCR-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX9-FLATSCR-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 16388, implicit-def dead $scc - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr2, killed $sgpr5, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr2, killed $sgpr5, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; GFX9-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX9-FLATSCR-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, undef $vgpr2 ; GFX9-FLATSCR-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr34, 1, undef $vgpr2 @@ -106,7 +106,7 @@ body: | ; GFX9-FLATSCR-NEXT: $sgpr34 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 1 ; GFX9-FLATSCR-NEXT: $sgpr6_sgpr7 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec ; GFX9-FLATSCR-NEXT: $sgpr5 = S_ADD_I32 $sgpr33, 16388, implicit-def dead $scc - ; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR killed $sgpr5, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR killed $sgpr5, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; GFX9-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7 ; GFX9-FLATSCR-NEXT: $sgpr33 = COPY $sgpr4 ; GFX9-FLATSCR-NEXT: S_ENDPGM 0, amdgpu_allvgprs diff --git a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir index bfca9331a5d25..e41fc0c169b90 100644 --- a/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir +++ b/llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir @@ -27,10 +27,10 @@ body: | ; CHECK: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $m0 = S_MOV_B32 9 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 ; CHECK-NEXT: $m0 = S_MOV_B32 9 - ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 S_SETPC_B64_return $sgpr30_sgpr31 @@ -51,10 +51,10 @@ body: | ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $m0 = S_MOV_B32 16711935 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 ; CHECK-NEXT: $m0 = S_MOV_B32 16711935 - ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr42, implicit-def $vgpr43, implicit-def $vgpr44, implicit-def $vgpr45, implicit-def $vgpr46, implicit-def $vgpr47, implicit-def $vgpr48, implicit-def $vgpr49, implicit-def $vgpr50, implicit-def $vgpr51, implicit-def $vgpr52, implicit-def $vgpr53, implicit-def $vgpr54, implicit-def $vgpr55, implicit-def $vgpr56, implicit-def $vgpr57, implicit-def $vgpr58, implicit-def $vgpr59, implicit-def $vgpr60, implicit-def $vgpr61, implicit-def $vgpr62, implicit-def $vgpr63, implicit-def $vgpr64, implicit-def $vgpr65, implicit-def $vgpr66 S_SETPC_B64_return $sgpr30_sgpr31 @@ -79,18 +79,18 @@ body: | ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $m0 = S_MOV_B32 3 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5) ; CHECK-NEXT: $m0 = S_MOV_B32 65 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.1, align 4, addrspace 5) ; CHECK-NEXT: $m0 = S_MOV_B32 1 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.2, align 4, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 ; CHECK-NEXT: $m0 = S_MOV_B32 1 - ; CHECK-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: (load (s1024) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239_vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247_vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255_vgpr256_vgpr257_vgpr258_vgpr259_vgpr260_vgpr261_vgpr262_vgpr263 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr233, implicit $vgpr234, implicit $vgpr235, implicit $vgpr236, implicit $vgpr237, implicit $vgpr238, implicit $vgpr239, implicit $vgpr248, implicit $vgpr249, implicit $vgpr250, implicit $vgpr251, implicit $vgpr252, implicit $vgpr253, implicit $vgpr254, implicit $vgpr255 :: ("amdgpu-thread-private" load (s1024) from %stack.2, align 4, addrspace 5) ; CHECK-NEXT: $m0 = S_MOV_B32 65 - ; CHECK-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: (load (s1024) from %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr105, implicit $vgpr106, implicit $vgpr107, implicit $vgpr108, implicit $vgpr109, implicit $vgpr111, implicit $vgpr120, implicit $vgpr121, implicit $vgpr122, implicit $vgpr123, implicit $vgpr124, implicit $vgpr125, implicit $vgpr126, implicit $vgpr127 :: ("amdgpu-thread-private" load (s1024) from %stack.1, align 4, addrspace 5) ; CHECK-NEXT: $m0 = S_MOV_B32 3 - ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 32, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr104, implicit-def $vgpr110, implicit-def $vgpr232 S_SETPC_B64_return $sgpr30_sgpr31 @@ -113,14 +113,14 @@ body: | ; CHECK: liveins: $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $m0 = S_MOV_B32 7 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5) ; CHECK-NEXT: $m0 = S_MOV_B32 3 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.1, align 4, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 ; CHECK-NEXT: $m0 = S_MOV_B32 3 - ; CHECK-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: (load (s1024) from %stack.1, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr74, implicit $vgpr75, implicit $vgpr76, implicit $vgpr77, implicit $vgpr78, implicit $vgpr79, implicit $vgpr88, implicit $vgpr89, implicit $vgpr90, implicit $vgpr91, implicit $vgpr92, implicit $vgpr93, implicit $vgpr94, implicit $vgpr95 :: ("amdgpu-thread-private" load (s1024) from %stack.1, align 4, addrspace 5) ; CHECK-NEXT: $m0 = S_MOV_B32 7 - ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40_vgpr41_vgpr42, implicit-def $vgpr70_vgpr71_vgpr72_vgpr73 S_SETPC_B64_return $sgpr30_sgpr31 @@ -149,12 +149,12 @@ body: | ; CHECK: liveins: $vgpr48, $sgpr30_sgpr31, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $m0 = S_MOV_B32 1 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.2, align 4, addrspace 5) ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr48, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40 ; CHECK-NEXT: $m0 = S_MOV_B32 1 - ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.2, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr43, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.2, align 4, addrspace 5) ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.0, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) SCRATCH_STORE_DWORD_SADDR $vgpr48, %stack.1, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) @@ -183,22 +183,22 @@ body: | ; W32: liveins: $sgpr48, $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 ; W32-NEXT: {{ $}} ; W32-NEXT: $sgpr0 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) - ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; W32-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; W32-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 ; W32-NEXT: $m0 = S_MOV_B32 9 - ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.4, align 4, addrspace 5) + ; W32-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.4, align 4, addrspace 5) ; W32-NEXT: $vgpr44 = SI_SPILL_S32_TO_VGPR $sgpr48, 0, $vgpr44 ; W32-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec ; W32-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40 ; W32-NEXT: $sgpr48 = SI_RESTORE_S32_FROM_VGPR $vgpr44, 0 ; W32-NEXT: $m0 = S_MOV_B32 9 - ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.4, align 4, addrspace 5) + ; W32-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.4, align 4, addrspace 5) ; W32-NEXT: $sgpr0 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; W32-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) - ; W32-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) - ; W32-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5) + ; W32-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; W32-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) + ; W32-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; W32-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 ; W32-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 ; @@ -206,22 +206,22 @@ body: | ; W64: liveins: $sgpr48, $sgpr30_sgpr31, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40, $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 ; W64-NEXT: {{ $}} ; W64-NEXT: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) - ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) + ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr41, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr42, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; W64-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr44, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; W64-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1 ; W64-NEXT: $m0 = S_MOV_B32 9 - ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.4, align 4, addrspace 5) + ; W64-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.4, align 4, addrspace 5) ; W64-NEXT: $vgpr44 = SI_SPILL_S32_TO_VGPR $sgpr48, 0, $vgpr44 ; W64-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec ; W64-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit $vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40 ; W64-NEXT: $sgpr48 = SI_RESTORE_S32_FROM_VGPR $vgpr44, 0 ; W64-NEXT: $m0 = S_MOV_B32 9 - ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: (load (s1024) from %stack.4, align 4, addrspace 5) + ; W64-NEXT: $vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr41, implicit $vgpr42, implicit $vgpr44, implicit $vgpr45, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63 :: ("amdgpu-thread-private" load (s1024) from %stack.4, align 4, addrspace 5) ; W64-NEXT: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; W64-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) - ; W64-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) - ; W64-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5) + ; W64-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; W64-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) + ; W64-NEXT: $vgpr44 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; W64-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1 ; W64-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 S_NOP 0, implicit-def $vgpr40, implicit-def $vgpr41, implicit-def $vgpr43, implicit-def $sgpr22, implicit-def $sgpr48, implicit-def $m0, implicit-def $exec @@ -261,7 +261,7 @@ body: | ; CHECK-NEXT: liveins: $vgpr44, $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $m0 = S_MOV_B32 11 - ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: (store (s1024) into %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_BLOCK_SADDR $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0 :: ("amdgpu-thread-private" store (s1024) into %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr42, implicit-def $vgpr45 ; CHECK-NEXT: S_BRANCH %bb.1 ; CHECK-NEXT: {{ $}} @@ -276,7 +276,7 @@ body: | ; CHECK-NEXT: liveins: $sgpr30_sgpr31, $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $m0 = S_MOV_B32 11 - ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: (load (s1024) from %stack.0, align 4, addrspace 5) + ; CHECK-NEXT: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 = SCRATCH_LOAD_BLOCK_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $m0, implicit $vgpr44, implicit $vgpr46, implicit $vgpr47, implicit $vgpr56, implicit $vgpr57, implicit $vgpr58, implicit $vgpr59, implicit $vgpr60, implicit $vgpr61, implicit $vgpr62, implicit $vgpr63, implicit $vgpr72, implicit $vgpr73 :: ("amdgpu-thread-private" load (s1024) from %stack.0, align 4, addrspace 5) ; CHECK-NEXT: S_SETPC_B64_return $sgpr30_sgpr31 bb.0: liveins: $sgpr30_sgpr31, $vgpr44 diff --git a/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll b/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll index 6ce614bd92480..7a627733e12c2 100644 --- a/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll +++ b/llvm/test/CodeGen/AMDGPU/prevent-fmul-hoist-ir.ll @@ -398,8 +398,8 @@ if.else: ; preds = %entry ret double %sub } -attributes #0 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { nounwind "denormal-fp-math"="ieee,ieee" } +attributes #0 = { nounwind denormal_fpenv(preservesign) } +attributes #1 = { nounwind denormal_fpenv(ieee|ieee) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; FP-CONTRACT-FAST: {{.*}} ; NO-UNSAFE-FP-MATH: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll index 015ce256a80c2..598a954da0567 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll @@ -9,9 +9,9 @@ define amdgpu_kernel void @test_overwrite(i64 %val, i1 %cond) { ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <3 x i64> [[STACK]], i64 43, i32 0 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[END:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[PROMOTEALLOCA1:%.*]] = phi <3 x i64> [ [[TMP3:%.*]], [[LOOP]] ], [ [[TMP0]], [[ENTRY:%.*]] ] -; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA1]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i64> [[PROMOTEALLOCA1]], i64 68, i32 0 +; CHECK-NEXT: [[PROMOTEALLOCA2:%.*]] = phi <3 x i64> [ [[TMP3:%.*]], [[LOOP]] ], [ [[TMP0]], [[ENTRY:%.*]] ] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA2]], i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i64> [[PROMOTEALLOCA2]], i64 68, i32 0 ; CHECK-NEXT: [[TMP3]] = insertelement <3 x i64> [[TMP2]], i64 32, i32 0 ; CHECK-NEXT: [[LOOP_CC:%.*]] = icmp ne i64 [[TMP1]], 68 ; CHECK-NEXT: br i1 [[LOOP_CC]], label [[LOOP]], label [[END]] @@ -67,9 +67,9 @@ define amdgpu_kernel void @test_no_overwrite(i64 %val, i1 %cond) { ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <3 x i64> [[STACK]], i64 43, i32 0 ; CHECK-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[END:%.*]] ; CHECK: loop: -; CHECK-NEXT: [[PROMOTEALLOCA1:%.*]] = phi <3 x i64> [ [[TMP2:%.*]], [[LOOP]] ], [ [[TMP0]], [[ENTRY:%.*]] ] -; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA1]], i32 0 -; CHECK-NEXT: [[TMP2]] = insertelement <3 x i64> [[PROMOTEALLOCA1]], i64 32, i32 1 +; CHECK-NEXT: [[PROMOTEALLOCA2:%.*]] = phi <3 x i64> [ [[TMP2:%.*]], [[LOOP]] ], [ [[TMP0]], [[ENTRY:%.*]] ] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA2]], i32 0 +; CHECK-NEXT: [[TMP2]] = insertelement <3 x i64> [[PROMOTEALLOCA2]], i64 32, i32 1 ; CHECK-NEXT: [[LOOP_CC:%.*]] = icmp ne i64 [[TMP1]], 32 ; CHECK-NEXT: br i1 [[LOOP_CC]], label [[LOOP]], label [[END]] ; CHECK: end: @@ -192,6 +192,57 @@ entry: ret void } +define void @alloca_load_store_ptr_ptrvec(ptr %arg) { +; CHECK-LABEL: define void @alloca_load_store_ptr_ptrvec +; CHECK-SAME: (ptr [[ARG:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <2 x ptr addrspace(3)> poison +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr <2 x i32> [[TMP1]] to <2 x ptr addrspace(3)> +; CHECK-NEXT: ret void +; +entry: + %alloca = alloca <2 x ptr addrspace(3)>, align 8, addrspace(5) + store ptr %arg, ptr addrspace(5) %alloca, align 8 + %tmp = load ptr, ptr addrspace(5) %alloca, align 8 + ret void +} + +define <2 x ptr> @alloca_load_store_diff_size_ptrvecs1(<2 x ptr> %arg) { +; CHECK-LABEL: define <2 x ptr> @alloca_load_store_diff_size_ptrvecs1 +; CHECK-SAME: (<2 x ptr> [[ARG:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <4 x ptr addrspace(3)> poison +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <2 x ptr> [[ARG]] to <2 x i64> +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr <4 x i32> [[TMP1]] to <4 x ptr addrspace(3)> +; CHECK-NEXT: ret <2 x ptr> [[ARG]] +; +entry: + %alloca = alloca <4 x ptr addrspace(3)>, align 8, addrspace(5) + store <2 x ptr> %arg, ptr addrspace(5) %alloca, align 8 + %tmp = load <2 x ptr>, ptr addrspace(5) %alloca, align 8 + ret <2 x ptr> %tmp +} + +define <4 x ptr addrspace(3)> @alloca_load_store_diff_size_ptrvecs2(<4 x ptr addrspace(3)> %arg) { +; CHECK-LABEL: define <4 x ptr addrspace(3)> @alloca_load_store_diff_size_ptrvecs2 +; CHECK-SAME: (<4 x ptr addrspace(3)> [[ARG:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <2 x ptr> poison +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <4 x ptr addrspace(3)> [[ARG]] to <4 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <2 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr <2 x i64> [[TMP1]] to <2 x ptr> +; CHECK-NEXT: ret <4 x ptr addrspace(3)> [[ARG]] +; +entry: + %alloca = alloca <2 x ptr>, align 8, addrspace(5) + store <4 x ptr addrspace(3)> %arg, ptr addrspace(5) %alloca, align 8 + %tmp = load <4 x ptr addrspace(3)>, ptr addrspace(5) %alloca, align 8 + ret <4 x ptr addrspace(3)> %tmp +} + ; Will not vectorize because we're accessing a 64 bit vector with a 32 bits pointer. define ptr addrspace(3) @alloca_load_store_ptr_mixed_full_ivec(ptr addrspace(3) %arg) { ; CHECK-LABEL: define ptr addrspace(3) @alloca_load_store_ptr_mixed_full_ivec diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir index 9215c0e664505..8d8c791fbd9ae 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir @@ -85,7 +85,7 @@ body: | ; GFX1250-LABEL: name: promote_async_load_u64 ; GFX1250: liveins: $vgpr0, $sgpr4_sgpr5 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: early-clobber renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM_ec killed renamable $sgpr4_sgpr5, 36, 0 :: (dereferenceable invariant load (s64), align 4, addrspace 4) + ; GFX1250-NEXT: early-clobber renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM_ec killed renamable $sgpr4_sgpr5, 36, 32 :: (dereferenceable invariant load (s64), align 4, addrspace 4) ; GFX1250-NEXT: renamable $vgpr1 = V_MOV_B32_e32 0, implicit $exec ; GFX1250-NEXT: renamable $vgpr0 = V_AND_B32_e32 1023, killed $vgpr0, implicit $exec ; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128_SADDR $vgpr1, $sgpr0_sgpr1, $vgpr0, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3) diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll index 1c986a02e8bd6..fba7720b37bf6 100644 --- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll +++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll @@ -327,7 +327,7 @@ define void @global_load_lds_dword_saddr_and_vaddr(ptr addrspace(1) nocapture in ; GFX942-NEXT: s_mov_b32 m0, s2 ; GFX942-NEXT: s_nop 0 ; GFX942-NEXT: global_load_lds_dword v1, s[0:1] offset:48 sc1 -; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_setpc_b64 s[30:31] main_body: %voffset.64 = zext i32 %voffset to i64 diff --git a/llvm/test/CodeGen/AMDGPU/rcp-pattern.ll b/llvm/test/CodeGen/AMDGPU/rcp-pattern.ll index 9f0ffbcf6eff9..26f2b3d2af60d 100644 --- a/llvm/test/CodeGen/AMDGPU/rcp-pattern.ll +++ b/llvm/test/CodeGen/AMDGPU/rcp-pattern.ll @@ -1411,10 +1411,10 @@ define amdgpu_kernel void @s_div_arcp_neg_k_x_pat_f32_daz(ptr addrspace(1) %out) declare float @llvm.fabs.f32(float) #1 declare float @llvm.sqrt.f32(float) #1 -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } attributes #1 = { nounwind readnone } -attributes #2 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } -attributes #4 = { nounwind "denormal-fp-math-f32"="ieee,ieee" } +attributes #2 = { nounwind denormal_fpenv(float: preservesign) } +attributes #3 = { nounwind denormal_fpenv(float: ieee|ieee) } +attributes #4 = { nounwind denormal_fpenv(float: ieee|ieee) } !0 = !{float 2.500000e+00} diff --git a/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll b/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll index 54c3b46589a51..db3c902ec2416 100644 --- a/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll +++ b/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll @@ -42,5 +42,5 @@ define amdgpu_kernel void @rcp_sint_denorm(ptr addrspace(1) %in, ptr addrspace(1 !0 = !{float 2.500000e+00} -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="ieee,ieee" } +attributes #0 = { denormal_fpenv(float: preservesign) } +attributes #1 = { denormal_fpenv(float: ieee|ieee) } diff --git a/llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir b/llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir index e4cbae66d47fa..35f1a5f74afc1 100644 --- a/llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir @@ -39,7 +39,7 @@ body: | ; GFX908-NEXT: $sgpr0 = S_ADD_U32 $sgpr0, $sgpr7, implicit-def $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-NEXT: $sgpr1 = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908-NEXT: renamable $vgpr34 = GLOBAL_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GFX908-NEXT: renamable $vgpr34 = GLOBAL_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, implicit $exec ; GFX908-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr34, implicit $exec, implicit $exec ; GFX908-NEXT: renamable $vgpr34 = GLOBAL_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, implicit $exec @@ -148,74 +148,74 @@ body: | ; GFX908-NEXT: $vgpr35 = V_MOV_B32_e32 killed $sgpr4, implicit $exec ; GFX908-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr35, implicit $exec, implicit $exec ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr5, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr6, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr7, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr8, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr9, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 20, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr10, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 24, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr11, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 28, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr12, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 32, 0, 0, implicit $exec :: (store (s32) into %stack.8, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr13, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 36, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr14, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 40, 0, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.10, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr15, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 44, 0, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.11, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr16, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 48, 0, 0, implicit $exec :: (store (s32) into %stack.12, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.12, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr17, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 52, 0, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.13, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr18, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 56, 0, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.14, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr19, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 60, 0, 0, implicit $exec :: (store (s32) into %stack.15, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.15, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr20, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 64, 0, 0, implicit $exec :: (store (s32) into %stack.16, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.16, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr21, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 68, 0, 0, implicit $exec :: (store (s32) into %stack.17, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.17, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr22, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 72, 0, 0, implicit $exec :: (store (s32) into %stack.18, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.18, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr23, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 76, 0, 0, implicit $exec :: (store (s32) into %stack.19, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.19, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr24, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 80, 0, 0, implicit $exec :: (store (s32) into %stack.20, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.20, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr25, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 84, 0, 0, implicit $exec :: (store (s32) into %stack.21, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.21, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr26, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 88, 0, 0, implicit $exec :: (store (s32) into %stack.22, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.22, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr27, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 92, 0, 0, implicit $exec :: (store (s32) into %stack.23, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.23, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr28, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 96, 0, 0, implicit $exec :: (store (s32) into %stack.24, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.24, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr29, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 100, 0, 0, implicit $exec :: (store (s32) into %stack.25, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.25, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr30, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 104, 0, 0, implicit $exec :: (store (s32) into %stack.26, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.26, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr31, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 108, 0, 0, implicit $exec :: (store (s32) into %stack.27, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.27, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr34, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 112, 0, 0, implicit $exec :: (store (s32) into %stack.28, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.28, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr35, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 116, 0, 0, implicit $exec :: (store (s32) into %stack.29, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.29, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr36, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 120, 0, 0, implicit $exec :: (store (s32) into %stack.30, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.30, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr37, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 124, 0, 0, implicit $exec :: (store (s32) into %stack.31, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.31, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr38, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 128, 0, 0, implicit $exec :: (store (s32) into %stack.32, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.32, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr39, implicit $exec, implicit $exec - ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 132, 0, 0, implicit $exec :: (store (s32) into %stack.33, addrspace 5) + ; GFX908-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr34, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.33, addrspace 5) ; GFX908-NEXT: $vgpr34 = V_MOV_B32_e32 killed $sgpr40, implicit $exec, implicit $exec ; GFX908-NEXT: S_NOP 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19, implicit $vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27, implicit $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33, implicit $vgpr35 - ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GFX908-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GFX908-NEXT: GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, killed renamable $vgpr0, 0, 0, implicit $exec ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $exec ; GFX908-NEXT: GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, killed renamable $vgpr0, 0, 0, implicit $exec @@ -287,39 +287,39 @@ body: | ; GFX908-NEXT: GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, killed renamable $vgpr0, 0, 0, implicit $exec ; GFX908-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr35, implicit $exec, implicit $exec ; GFX908-NEXT: GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, killed renamable $vgpr0, 0, 0, implicit $exec - ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) - ; GFX908-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) - ; GFX908-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) - ; GFX908-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) - ; GFX908-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 20, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) - ; GFX908-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 24, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) - ; GFX908-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 28, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) - ; GFX908-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 32, 0, 0, implicit $exec :: (load (s32) from %stack.8, addrspace 5) - ; GFX908-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 36, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) - ; GFX908-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 40, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5) - ; GFX908-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 44, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5) - ; GFX908-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 48, 0, 0, implicit $exec :: (load (s32) from %stack.12, addrspace 5) - ; GFX908-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 52, 0, 0, implicit $exec :: (load (s32) from %stack.13, addrspace 5) - ; GFX908-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 56, 0, 0, implicit $exec :: (load (s32) from %stack.14, addrspace 5) - ; GFX908-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 60, 0, 0, implicit $exec :: (load (s32) from %stack.15, addrspace 5) - ; GFX908-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 64, 0, 0, implicit $exec :: (load (s32) from %stack.16, addrspace 5) - ; GFX908-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 68, 0, 0, implicit $exec :: (load (s32) from %stack.17, addrspace 5) - ; GFX908-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 72, 0, 0, implicit $exec :: (load (s32) from %stack.18, addrspace 5) - ; GFX908-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 76, 0, 0, implicit $exec :: (load (s32) from %stack.19, addrspace 5) - ; GFX908-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 80, 0, 0, implicit $exec :: (load (s32) from %stack.20, addrspace 5) - ; GFX908-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 84, 0, 0, implicit $exec :: (load (s32) from %stack.21, addrspace 5) - ; GFX908-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 88, 0, 0, implicit $exec :: (load (s32) from %stack.22, addrspace 5) - ; GFX908-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 92, 0, 0, implicit $exec :: (load (s32) from %stack.23, addrspace 5) - ; GFX908-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 96, 0, 0, implicit $exec :: (load (s32) from %stack.24, addrspace 5) - ; GFX908-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 100, 0, 0, implicit $exec :: (load (s32) from %stack.25, addrspace 5) - ; GFX908-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 104, 0, 0, implicit $exec :: (load (s32) from %stack.26, addrspace 5) - ; GFX908-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 108, 0, 0, implicit $exec :: (load (s32) from %stack.27, addrspace 5) - ; GFX908-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 112, 0, 0, implicit $exec :: (load (s32) from %stack.28, addrspace 5) - ; GFX908-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 116, 0, 0, implicit $exec :: (load (s32) from %stack.29, addrspace 5) - ; GFX908-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 120, 0, 0, implicit $exec :: (load (s32) from %stack.30, addrspace 5) - ; GFX908-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 124, 0, 0, implicit $exec :: (load (s32) from %stack.31, addrspace 5) - ; GFX908-NEXT: $vgpr32 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 128, 0, 0, implicit $exec :: (load (s32) from %stack.32, addrspace 5) - ; GFX908-NEXT: $vgpr33 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 132, 0, 0, implicit $exec :: (load (s32) from %stack.33, addrspace 5) + ; GFX908-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; GFX908-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) + ; GFX908-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; GFX908-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) + ; GFX908-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 20, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; GFX908-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 24, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; GFX908-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) + ; GFX908-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 32, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, addrspace 5) + ; GFX908-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 36, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) + ; GFX908-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 40, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.10, addrspace 5) + ; GFX908-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.11, addrspace 5) + ; GFX908-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 48, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.12, addrspace 5) + ; GFX908-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 52, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.13, addrspace 5) + ; GFX908-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 56, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.14, addrspace 5) + ; GFX908-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 60, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.15, addrspace 5) + ; GFX908-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.16, addrspace 5) + ; GFX908-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 68, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.17, addrspace 5) + ; GFX908-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 72, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.18, addrspace 5) + ; GFX908-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 76, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.19, addrspace 5) + ; GFX908-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 80, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.20, addrspace 5) + ; GFX908-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 84, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.21, addrspace 5) + ; GFX908-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 88, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.22, addrspace 5) + ; GFX908-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 92, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.23, addrspace 5) + ; GFX908-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.24, addrspace 5) + ; GFX908-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 100, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.25, addrspace 5) + ; GFX908-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 104, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.26, addrspace 5) + ; GFX908-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 108, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.27, addrspace 5) + ; GFX908-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 112, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.28, addrspace 5) + ; GFX908-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 116, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.29, addrspace 5) + ; GFX908-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 120, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.30, addrspace 5) + ; GFX908-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 124, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.31, addrspace 5) + ; GFX908-NEXT: $vgpr32 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 128, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.32, addrspace 5) + ; GFX908-NEXT: $vgpr33 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 132, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.33, addrspace 5) ; GFX908-NEXT: S_NOP 0, implicit renamable $agpr0, implicit killed renamable $vgpr1, implicit killed renamable $vgpr2, implicit killed renamable $vgpr3, implicit killed renamable $vgpr4, implicit killed renamable $vgpr5, implicit killed renamable $vgpr6, implicit killed renamable $vgpr7, implicit killed renamable $vgpr8, implicit killed renamable $vgpr9, implicit killed renamable $vgpr10, implicit killed renamable $vgpr11, implicit killed renamable $vgpr12, implicit killed renamable $vgpr13, implicit killed renamable $vgpr14, implicit killed renamable $vgpr15, implicit killed renamable $vgpr16, implicit killed renamable $vgpr17, implicit killed renamable $vgpr18, implicit killed renamable $vgpr19, implicit killed renamable $vgpr20, implicit killed renamable $vgpr21, implicit killed renamable $vgpr22, implicit killed renamable $vgpr23, implicit killed renamable $vgpr24, implicit killed renamable $vgpr25, implicit killed renamable $vgpr26, implicit killed renamable $vgpr27, implicit killed renamable $vgpr28, implicit killed renamable $vgpr29, implicit killed renamable $vgpr30, implicit killed renamable $vgpr31, implicit killed renamable $vgpr32, implicit killed renamable $vgpr33, implicit killed renamable $vgpr34 ; GFX908-NEXT: S_ENDPGM 0, implicit killed renamable $agpr0 %v0:vgpr_32 = GLOBAL_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll index 2d3524d711788..1196d51b89557 100644 --- a/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll +++ b/llvm/test/CodeGen/AMDGPU/repeated-divisor.ll @@ -1011,8 +1011,8 @@ define <6 x half> @v_repeat_divisor_v3f16_x2(<3 x half> %x, <3 x half> %y, <3 x ret <6 x half> %shuffle } -attributes #0 = { "denormal-fp-math-f32"="ieee,ieee" } -attributes #1 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: ieee|ieee) } +attributes #1 = { denormal_fpenv(float: preservesign) } !0 = !{float 2.5} ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: diff --git a/llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll b/llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll index d9fdfb38ef344..dbeeb9085f59a 100644 --- a/llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll +++ b/llvm/test/CodeGen/AMDGPU/rsq.f32-safe.ll @@ -923,7 +923,7 @@ define float @v_rsq_f32_known_never_posdenormal(float nofpclass(psub) %val) { !0 = !{float 2.500000e+00} !1 = !{float 1.000000e+00} -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; CI-DAZ-SAFE: {{.*}} ; GCN-DAZ-SAFE: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/rsq.f32.ll b/llvm/test/CodeGen/AMDGPU/rsq.f32.ll index f967e951b27a4..e841cb1518532 100644 --- a/llvm/test/CodeGen/AMDGPU/rsq.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/rsq.f32.ll @@ -961,7 +961,7 @@ define float @v_rsq_f32_known_never_posdenormal(float nofpclass(psub) %val) { !0 = !{float 2.500000e+00} !1 = !{float 1.000000e+00} -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; CI-DAZ-UNSAFE: {{.*}} ; CI-IEEE-UNSAFE: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll b/llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll new file mode 100644 index 0000000000000..c0ad0c0c64adc --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/s_or_b32_transformation.ll @@ -0,0 +1,31 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s +; This tests if disjoint s_or_b32 gets transformed to s_addk_i32 when we can't use s_bitset1_b32 + +define amdgpu_ps i32 @s_or_b32_i32(i32 inreg %x) { +; CHECK-LABEL: s_or_b32_i32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_or_b32 s0, s0, 0x101 +; CHECK-NEXT: ; return to shader part epilog + %or = or i32 %x, 257 + ret i32 %or +} + +define amdgpu_ps i32 @s_or_b32_disjoint_to_s_addk_i32(i32 inreg %x) { +; CHECK-LABEL: s_or_b32_disjoint_to_s_addk_i32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_addk_i32 s0, 0x101 +; CHECK-NEXT: ; return to shader part epilog + %or = or disjoint i32 %x, 257 + ret i32 %or +} + +define amdgpu_ps i32 @s_or_b32_to_s_bitset1_b32(i32 inreg %x) { +; CHECK-LABEL: s_or_b32_to_s_bitset1_b32: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_bitset1_b32 s0, 8 +; CHECK-NEXT: ; return to shader part epilog + %or = or disjoint i32 %x, 256 + ret i32 %or +} + diff --git a/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir b/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir index 592e0f0cf0c24..105da9178b109 100644 --- a/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir +++ b/llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir @@ -20,11 +20,11 @@ body: | ; CHECK-NEXT: $sgpr4_sgpr5 = IMPLICIT_DEF ; CHECK-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $exec ; CHECK-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; CHECK-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, undef $vgpr0, implicit $sgpr4_sgpr5 ; CHECK-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, $vgpr0, implicit killed $sgpr4_sgpr5 ; CHECK-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr0, implicit $exec - ; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7, implicit killed $vgpr0 ; CHECK-NEXT: S_ENDPGM 0 $vgpr0 = IMPLICIT_DEF @@ -53,11 +53,11 @@ body: | ; CHECK-NEXT: $sgpr4_sgpr5 = IMPLICIT_DEF ; CHECK-NEXT: $sgpr6_sgpr7 = S_MOV_B64 $exec ; CHECK-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; CHECK-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, undef $vgpr0, implicit $sgpr4_sgpr5 ; CHECK-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr5, 1, $vgpr0, implicit killed $sgpr4_sgpr5 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr6_sgpr7, implicit killed $vgpr0 ; CHECK-NEXT: S_ENDPGM 0 $vgpr0 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir b/llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir index 6a3707542d630..34c82cf2c73fb 100644 --- a/llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir +++ b/llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir @@ -215,37 +215,37 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -311,37 +311,37 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF13]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -408,48 +408,48 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -522,49 +522,49 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF13]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -639,40 +639,43 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF13]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF14]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) @@ -680,14 +683,11 @@ body: | ; CHECK-NEXT: KILL [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF17]], [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF16]], [[DEF12]], [[DEF13]], [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -767,40 +767,43 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[V_ADD_U32_e32_]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF13]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF14]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) @@ -808,15 +811,12 @@ body: | ; CHECK-NEXT: KILL [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF12]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec - ; CHECK-NEXT: undef [[V_ADD_U32_e32_3:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_3:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF17]], [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF16]], [[DEF12]], [[DEF13]], [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -898,36 +898,39 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -939,16 +942,16 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF13]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF14]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.6(0x80000000) @@ -956,14 +959,11 @@ body: | ; CHECK-NEXT: KILL [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF17]], [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF16]], [[DEF12]], [[DEF13]], [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -1055,36 +1055,39 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -1096,16 +1099,16 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF13]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF14]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.6(0x80000000) @@ -1113,15 +1116,12 @@ body: | ; CHECK-NEXT: KILL [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF12]].sub1, [[V_ADD_U32_e32_1]].sub0, implicit $exec - ; CHECK-NEXT: undef [[V_ADD_U32_e32_3:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_1]].sub0, implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_3:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF17]], [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF16]], [[DEF12]], [[DEF13]], [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -1215,28 +1215,30 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) @@ -1247,20 +1249,18 @@ body: | ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -1336,28 +1336,30 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) @@ -1368,24 +1370,22 @@ body: | ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF13]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -1465,40 +1465,42 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.5(0x40000000) @@ -1509,22 +1511,20 @@ body: | ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.7 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -1610,40 +1610,42 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.5(0x40000000) @@ -1654,24 +1656,22 @@ body: | ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.7 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF13]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -1756,46 +1756,50 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub1, [[DEF10]], implicit $exec + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.4, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub0, [[DEF10]], implicit $exec - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF12]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF13]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_6:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_7:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_8:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_9:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_10:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_11:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF7]], [[DEF8]], [[DEF14]], 4, 4, [[DEF9]].sub0, [[DEF10]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_6:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_7:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_8:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_9:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_10:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_11:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) @@ -1811,22 +1815,18 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF10]], implicit $exec + ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.6(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_3:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF10]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_3:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF16]], [[DEF17]], [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF15]], [[DEF11]], [[DEF12]], [[DEF13]], [[DEF14]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_3]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -1923,40 +1923,43 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.4, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[V_ADD_U32_e32_]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF13]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF14]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) @@ -1972,25 +1975,22 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.6(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub1, [[DEF11]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub1, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.6 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.6(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub0, [[DEF11]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: - ; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF12]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF17]], [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF16]], [[DEF12]], [[DEF13]], [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -2083,36 +2083,39 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -2124,16 +2127,16 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF13]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF14]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.6(0x80000000) @@ -2149,23 +2152,20 @@ body: | ; CHECK-NEXT: bb.7: ; CHECK-NEXT: successors: %bb.9(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF11]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.9 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: ; CHECK-NEXT: successors: %bb.9(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF11]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF17]], [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF16]], [[DEF12]], [[DEF13]], [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -2269,36 +2269,38 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -2310,10 +2312,10 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF14]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF15]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF16]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.6(0x40000000) @@ -2324,24 +2326,22 @@ body: | ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: - ; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF13]].sub1, [[V_ADD_U32_e32_1]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_1]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DEF16]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -2438,36 +2438,38 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY [[DS_READ_B128_gfx9_]] - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_1:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_2:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_3:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_4:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_5:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_1:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_2:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_3:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_4:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_5:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) @@ -2482,14 +2484,12 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_128_align2 = COPY [[COPY]] - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[COPY7]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[COPY7]], 0, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF13]], [[DEF14]], [[COPY7]] + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF15]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF16]], [[DEF17]], [[COPY7]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -2568,37 +2568,39 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY [[DS_READ_B128_gfx9_]] - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_1:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_2:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_3:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_4:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_5:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF10]], [[DEF11]], [[COPY]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_1:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_2:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_3:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_4:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_5:%[0-9]+]]:areg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64 [[DEF12]], [[DEF13]], [[COPY]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) @@ -2613,13 +2615,11 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vreg_128_align2 = COPY [[COPY]] - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF13]].sub1, [[COPY7]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[COPY7]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[COPY7]], [[V_ADD_U32_e32_]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[COPY7]], [[V_ADD_U32_e32_]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -2698,48 +2698,48 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 0, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 128, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 128, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF13]], [[DEF14]], [[DS_READ_B128_gfx9_]] + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF15]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -2813,49 +2813,49 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 0, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 128, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 128, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 0, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF13]], [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF15]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF16]], [[DEF17]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -2929,43 +2929,43 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 128, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 128, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF13]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF14]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF15]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF15]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF16]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF17]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]], 0, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DS_READ_B128_gfx9_1]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -3038,44 +3038,44 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 128, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 128, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF13]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF14]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF15]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF15]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF16]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF17]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]], 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]], 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]], 128, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DS_READ_B128_gfx9_1]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -3149,35 +3149,37 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 256, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 256, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 512, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 512, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -3189,20 +3191,18 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_1]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF13]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF14]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF15]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_1]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF15]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF16]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF17]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]], 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]], 128, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DS_READ_B128_gfx9_]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -3285,35 +3285,37 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 256, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 256, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 512, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 512, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -3325,21 +3327,19 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_1]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF13]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF14]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF15]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_1]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF15]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF16]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF17]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]], 128, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]], 384, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]], 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]], 384, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DS_READ_B128_gfx9_]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -3425,27 +3425,29 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) @@ -3456,21 +3458,19 @@ body: | ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 0, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 128, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF13]], [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF15]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF16]], [[DEF17]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -3545,27 +3545,29 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) @@ -3576,25 +3578,23 @@ body: | ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 256, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 256, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 256, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 256, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]], 0, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF13]], [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF15]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF16]], [[DEF17]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -3675,39 +3675,41 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 0, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 256, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 256, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.5(0x40000000) @@ -3718,23 +3720,21 @@ body: | ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 128, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.7 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 128, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF13]], [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF15]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF16]], [[DEF17]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -3821,39 +3821,41 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 0, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 256, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 256, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.5(0x40000000) @@ -3864,25 +3866,23 @@ body: | ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 128, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.7 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, 128, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF12]], [[DS_READ_B128_gfx9_]].sub0, 256, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF14]], [[DS_READ_B128_gfx9_]].sub0, 256, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF13]], [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF15]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF16]], [[DEF17]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -3969,33 +3969,35 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 256, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 256, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF13]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF14]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF15]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF15]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF16]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF17]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) @@ -4006,21 +4008,19 @@ body: | ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]], 0, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]], 256, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]], 256, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DS_READ_B128_gfx9_1]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -4103,33 +4103,35 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 256, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 256, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF13]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF14]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF15]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF15]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF16]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF17]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) @@ -4140,25 +4142,23 @@ body: | ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]].sub0, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]].sub1, 256, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]].sub0, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]].sub1, 256, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]].sub1, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]].sub0, 256, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]].sub1, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]].sub0, 256, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]], 0, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DS_READ_B128_gfx9_1]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -4245,35 +4245,37 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 256, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 256, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 512, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 512, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -4285,10 +4287,10 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_1]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF13]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF14]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF15]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_1]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF15]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF16]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF17]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.6(0x40000000) @@ -4299,23 +4301,21 @@ body: | ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]].sub0, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]].sub1, 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]].sub0, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]].sub1, 128, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]].sub1, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]].sub0, 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]].sub1, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]].sub0, 128, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DS_READ_B128_gfx9_]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -4410,35 +4410,37 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 256, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 256, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF9]], 512, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF11]], 512, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -4450,10 +4452,10 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DS_READ_B128_gfx9_1]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF13]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF14]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[DEF15]], 4, 4, [[DEF12]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DS_READ_B128_gfx9_1]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF15]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF16]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF12]], [[DEF13]], [[DEF17]], 4, 4, [[DEF14]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.6(0x40000000) @@ -4464,25 +4466,23 @@ body: | ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]].sub0, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]].sub1, 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]].sub0, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]].sub1, 128, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]].sub1, 0, 0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_]].sub0, 128, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]].sub1, 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B32_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_]].sub0, 128, 0, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF9]], [[DS_READ_B128_gfx9_1]], 256, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[DS_READ_B128_gfx9_1]], 256, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF17]], [[DEF13]], [[DEF14]], [[DEF15]], [[DS_READ_B128_gfx9_]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DS_READ_B128_gfx9_]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -4579,37 +4579,37 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 0, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -4677,36 +4677,38 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 0, 0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 0, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -4718,10 +4720,10 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF14]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF15]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF16]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.6(0x40000000) @@ -4732,23 +4734,21 @@ body: | ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF12]], [[V_ADD_U32_e32_]], 0, 0, implicit $exec - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF14]], [[V_ADD_U32_e32_]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: S_BRANCH %bb.8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[DEF17:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[DEF17:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[DEF19:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[DEF19:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_ADD_U32_e32_]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF21:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF19]], [[DEF20]], [[DEF21]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF18]], [[DEF13]], [[DEF14]], [[DEF15]], [[DEF16]], [[V_ADD_U32_e32_]], [[DEF17]] + ; CHECK-NEXT: [[DEF21:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF21]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_]], [[DEF19]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -4843,40 +4843,43 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[V_ADD_U32_e32_]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF13]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF14]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF8]], [[DEF9]], [[DEF15]], 4, 4, [[DEF10]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF16]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF18]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) @@ -4884,15 +4887,12 @@ body: | ; CHECK-NEXT: KILL [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_4]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_5]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF12]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF11]], [[V_ADD_U32_e32_1]], 0, 0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF15]].sub1, [[V_ADD_U32_e32_]].sub0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF14]], [[V_ADD_U32_e32_1]], 0, 0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF17]], [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF16]], [[DEF12]], [[DEF13]], [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF15]], [[DEF16]], [[DEF17]], [[DEF18]], [[V_ADD_U32_e32_1]], [[V_ADD_U32_e32_2]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -4975,40 +4975,42 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF12]], 0, 0, implicit $exec + ; CHECK-NEXT: [[DS_READ_B128_gfx9_:%[0-9]+]]:vreg_128_align2 = DS_READ_B128_gfx9 [[DEF14]], 0, 0, implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[DS_READ_B128_gfx9_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[DS_READ_B128_gfx9_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub1, [[DEF14]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DS_READ_B128_gfx9_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.5(0x40000000) @@ -5019,23 +5021,21 @@ body: | ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub1, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.7 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.7(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 0, 0, implicit $exec + ; CHECK-NEXT: DS_WRITE_B128_gfx9 [[DEF14]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], 0, 0, implicit $exec ; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: - ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DS_READ_B128_gfx9_]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DS_READ_B128_gfx9_]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF15]], [[DEF16]], [[DEF17]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF14]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_1]] + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF16]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF17]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_3]], [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -5121,59 +5121,59 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF14:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF12]], implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_ADD_U32_e32_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF14]], implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_ADD_U32_e32_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.4, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF15]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF15]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF15]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF11]], [[DEF12]], [[DEF17]], 4, 4, [[DEF13]].sub0, [[DEF14]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF9]], [[DEF10]], [[DEF15]], 4, 4, [[DEF11]].sub0, [[DEF12]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF15]].sub0, [[DEF12]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF17]].sub0, [[DEF14]], implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF17]], [[DEF18]], [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF16]], [[DEF13]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[DEF15]], [[V_ADD_U32_e32_1]] + ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF18]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF19]], [[DEF15]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_1]], [[V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_2]], [[DEF17]], [[V_ADD_U32_e32_1]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir b/llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir index 3666508038aa3..1cb6bdaf72666 100644 --- a/llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir +++ b/llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir @@ -45,33 +45,35 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub1, [[DEF9]], implicit $exec + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub0, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub1, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -83,10 +85,10 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF16]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF16]], [[DEF17]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF18]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.6(0x40000000) @@ -97,8 +99,8 @@ body: | ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub1, [[DEF9]], implicit $exec - ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub0, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF11]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: @@ -110,23 +112,21 @@ body: | ; CHECK-NEXT: bb.8: ; CHECK-NEXT: successors: %bb.9(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_3:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub0, [[DEF9]], implicit $exec - ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_3:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub1, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_3:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_3:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF11]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.10(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_4:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub1, [[DEF11]].sub0, implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_4:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub2, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_4:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF13]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_4:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub2, [[DEF11]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.10: - ; CHECK-NEXT: [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF10]].sub1, [[DEF11]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_5:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF13]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF17]], [[DEF10]], [[DEF11]], [[V_ADD_U32_e32_4]], [[V_ADD_U32_e32_5]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF12]], [[DEF13]], [[V_ADD_U32_e32_4]], [[V_ADD_U32_e32_5]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -229,33 +229,35 @@ body: | ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vreg_128 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %12 ; CHECK-NEXT: S_NOP 0, implicit-def %13 - ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub1, [[DEF9]], implicit $exec + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF14:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF15:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub0, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub0, [[DEF11]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub1, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF12]].sub1, [[DEF11]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -267,10 +269,10 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF14:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF15:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF16:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF14]], [[DEF15]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF16]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF16:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF17:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF16]], [[DEF17]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF18]].sub0, [[DEF11]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.6(0x40000000) @@ -281,24 +283,22 @@ body: | ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub1, [[DEF9]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub0, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF11]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF11]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub0, [[DEF9]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub1, [[DEF9]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub0, [[DEF11]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF13]].sub1, [[DEF11]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: - ; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF10]].sub1, [[V_ADD_U32_e32_1]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF12]].sub1, [[V_ADD_U32_e32_1]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF17:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF18:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF19:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF - ; CHECK-NEXT: KILL [[DEF18]], [[DEF19]], [[DEF20]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF17]], [[DEF10]], [[DEF11]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] + ; CHECK-NEXT: [[DEF20:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: KILL [[DEF19]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF5]], [[DEF6]], [[DEF7]], [[DEF8]], [[DEF9]], [[DEF10]], [[DEF20]], [[DEF12]], [[DEF13]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] ; CHECK-NEXT: S_NOP 0, implicit %12, implicit %13 ; CHECK-NEXT: S_ENDPGM 0 bb.0: @@ -388,37 +388,37 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_128 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_512 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_128 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF ; CHECK-NEXT: S_NOP 0, implicit-def %5 ; CHECK-NEXT: S_NOP 0, implicit-def %6 - ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_512 = IMPLICIT_DEF ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF6:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead [[DEF8:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead [[DEF9:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF6]].sub1, [[DEF5]], implicit $exec + ; CHECK-NEXT: [[DEF8:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF10:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead [[DEF13:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF + ; CHECK-NEXT: dead undef [[V_ADD_U32_e32_:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub1, [[DEF9]], implicit $exec ; CHECK-NEXT: $scc = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF10:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF11:%[0-9]+]]:av_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF12:%[0-9]+]]:vreg_128_align2 = IMPLICIT_DEF - ; CHECK-NEXT: [[DEF13:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF6]].sub0, [[DEF5]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub0, [[DEF9]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF6]].sub1, [[DEF5]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_1:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF10]].sub1, [[DEF9]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: @@ -430,7 +430,7 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: %bb.5(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF7:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF10]], [[DEF11]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF13]].sub0, [[DEF5]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[DEF11:%[0-9]+]]:vreg_128_align2 = contract nofpexcept V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64 [[DEF5]], [[DEF6]], [[V_ADD_U32_e32_1]], 4, 4, [[DEF8]].sub0, [[DEF9]], 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.6(0x40000000) @@ -441,20 +441,20 @@ body: | ; CHECK-NEXT: bb.6: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF7]].sub1, [[DEF5]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF7]].sub0, [[DEF5]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub1, [[DEF9]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub0, [[DEF9]], implicit $exec ; CHECK-NEXT: S_BRANCH %bb.8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7: ; CHECK-NEXT: successors: %bb.8(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF7]].sub0, [[DEF5]], implicit $exec - ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF7]].sub1, [[DEF5]], implicit $exec + ; CHECK-NEXT: undef [[V_ADD_U32_e32_2:%[0-9]+]].sub0:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub0, [[DEF9]], implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]].sub1:vreg_128_align2 = V_ADD_U32_e32 [[DEF11]].sub1, [[DEF9]], implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: - ; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF6]].sub1, [[V_ADD_U32_e32_1]].sub0, implicit $exec + ; CHECK-NEXT: [[V_ADD_U32_e32_3:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF10]].sub1, [[V_ADD_U32_e32_1]].sub0, implicit $exec ; CHECK-NEXT: SCHED_BARRIER 0 - ; CHECK-NEXT: KILL [[DEF4]], [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF12]], [[DEF6]], [[DEF7]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] + ; CHECK-NEXT: KILL [[DEF]], [[DEF1]], [[DEF2]], [[DEF3]], [[DEF4]], [[DEF7]], [[DEF10]], [[DEF11]], [[V_ADD_U32_e32_2]], [[V_ADD_U32_e32_3]] ; CHECK-NEXT: S_NOP 0, implicit %5, implicit %6 ; CHECK-NEXT: S_ENDPGM 0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir index 7be5b164cd1a1..8e98d0cc27473 100644 --- a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir +++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir @@ -16,7 +16,6 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3 - ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: global_load_ushort v14, v[0:1], off ; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX9-NEXT: global_load_ushort v15, v[4:5], off @@ -74,7 +73,6 @@ ; GFX9-TGS: ; %bb.0: ; GFX9-TGS-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX9-TGS-NEXT: ; implicit-def: $vgpr2_vgpr3 - ; GFX9-TGS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-TGS-NEXT: global_load_ushort v14, v[0:1], off ; GFX9-TGS-NEXT: ; implicit-def: $vgpr4_vgpr5 ; GFX9-TGS-NEXT: global_load_ushort v15, v[4:5], off @@ -136,6 +134,8 @@ --- name: test_workgroup tracksRegLiveness: true +machineFunctionInfo: + isEntryFunction: true body: | bb.0: %0:sgpr_256 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll index 6de85255e9c17..fa705fb455ba8 100644 --- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll +++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll @@ -2293,7 +2293,7 @@ entry: declare i32 @llvm.amdgcn.workitem.id.x() -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(preservesign) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN: {{.*}} ; GFX9_10: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/select.f16.ll b/llvm/test/CodeGen/AMDGPU/select.f16.ll index 195d222408139..36f073054031a 100644 --- a/llvm/test/CodeGen/AMDGPU/select.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/select.f16.ll @@ -99,22 +99,20 @@ define amdgpu_kernel void @select_f16( ; GFX11-TRUE16-NEXT: s_mov_b32 s17, s11 ; GFX11-TRUE16-NEXT: s_mov_b32 s20, s12 ; GFX11-TRUE16-NEXT: s_mov_b32 s21, s13 -; GFX11-TRUE16-NEXT: s_mov_b32 s24, s14 -; GFX11-TRUE16-NEXT: s_mov_b32 s25, s15 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[20:23], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[20:23], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v3, off, s[24:27], 0 glc dlc +; GFX11-TRUE16-NEXT: s_mov_b32 s24, s14 +; GFX11-TRUE16-NEXT: s_mov_b32 s25, s15 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[24:27], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[0:3], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v1, off, s[0:3], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s8 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s9 -; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.h, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -244,27 +242,25 @@ define amdgpu_kernel void @select_f16_imm_a( ; GFX11-TRUE16-NEXT: s_mov_b32 s15, s11 ; GFX11-TRUE16-NEXT: s_mov_b32 s18, s10 ; GFX11-TRUE16-NEXT: s_mov_b32 s19, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s22, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s23, s11 ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s16, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: s_mov_b32 s20, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 +; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 +; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 +; GFX11-TRUE16-NEXT: s_mov_b32 s6, s10 +; GFX11-TRUE16-NEXT: s_mov_b32 s7, s11 +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[20:23], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, 0.5, v0.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.h, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -385,27 +381,25 @@ define amdgpu_kernel void @select_f16_imm_b( ; GFX11-TRUE16-NEXT: s_mov_b32 s15, s11 ; GFX11-TRUE16-NEXT: s_mov_b32 s18, s10 ; GFX11-TRUE16-NEXT: s_mov_b32 s19, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s22, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s23, s11 ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s16, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: s_mov_b32 s20, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s21, s7 -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 +; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 +; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 +; GFX11-TRUE16-NEXT: s_mov_b32 s6, s10 +; GFX11-TRUE16-NEXT: s_mov_b32 s7, s11 +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[20:23], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0.5, v0.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.h, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -534,20 +528,20 @@ define amdgpu_kernel void @select_f16_imm_c( ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s16, s4 ; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: s_mov_b32 s12, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s13, s7 +; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 +; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 +; GFX11-TRUE16-NEXT: s_mov_b32 s6, s10 +; GFX11-TRUE16-NEXT: s_mov_b32 s7, s11 ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3800, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3800, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -676,20 +670,20 @@ define amdgpu_kernel void @select_f16_imm_d( ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s16, s4 ; GFX11-TRUE16-NEXT: s_mov_b32 s17, s5 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: s_mov_b32 s12, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s13, s7 +; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 +; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 +; GFX11-TRUE16-NEXT: s_mov_b32 s6, s10 +; GFX11-TRUE16-NEXT: s_mov_b32 s7, s11 ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[12:15], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 -; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v1.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3800, v0.l, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x3800, v1.l, vcc_lo ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir index b4f23ec00b8e2..03b88858c7318 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir @@ -6,7 +6,7 @@ ret [13 x i32] poison } - attributes #0 = { alwaysinline nounwind memory(readwrite) "amdgpu-flat-work-group-size"="32,32" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "denormal-fp-math-f32"="preserve-sign" "target-cpu"="gfx1030" "target-features"="+wavefrontsize32,+cumode,+enable-flat-scratch" "uniform-work-group-size"="false" } + attributes #0 = { alwaysinline nounwind memory(readwrite) "amdgpu-flat-work-group-size"="32,32" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" denormal_fpenv(float: preservesign) "target-cpu"="gfx1030" "target-features"="+wavefrontsize32,+cumode,+enable-flat-scratch" "uniform-work-group-size"="false" } ... --- @@ -33,11 +33,11 @@ body: | ; GCN-NEXT: $vcc_hi = frame-setup COPY $sgpr33 ; GCN-NEXT: $sgpr33 = frame-setup COPY $sgpr32 ; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.69, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.70, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.71, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5) - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr5, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.73, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.69, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.70, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.71, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.72, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr5, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.73, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 ; GCN-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr2 @@ -200,11 +200,11 @@ body: | ; GCN-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 0 ; GCN-NEXT: $sgpr32 = frame-destroy COPY $sgpr33 ; GCN-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5) - ; GCN-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5) - ; GCN-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.71, addrspace 5) - ; GCN-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.72, addrspace 5) - ; GCN-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.73, addrspace 5) + ; GCN-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.69, addrspace 5) + ; GCN-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.70, addrspace 5) + ; GCN-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.71, addrspace 5) + ; GCN-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.72, addrspace 5) + ; GCN-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.73, addrspace 5) ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0 ; GCN-NEXT: $sgpr33 = frame-destroy COPY $vcc_hi ; GCN-NEXT: S_ENDPGM 0 diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir index 59c4b715dd12e..346dadb7b15e6 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir @@ -26,11 +26,11 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr8, 0, undef $vgpr0 ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr0 ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} @@ -76,12 +76,12 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr8, 0, undef $vgpr0, implicit $sgpr8_sgpr9 ; VMEM-GFX8-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr9, 1, $vgpr0, implicit $sgpr8_sgpr9 ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr0 ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} @@ -125,11 +125,11 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; VMEM-GFX8-NEXT: $sgpr8 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr0 ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} @@ -173,12 +173,12 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; VMEM-GFX8-NEXT: $sgpr8 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr8_sgpr9 ; VMEM-GFX8-NEXT: $sgpr9 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 1 - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr0 ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} @@ -223,14 +223,14 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr8, 0, undef $vgpr0 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -276,14 +276,14 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; VMEM-GFX8-NEXT: $sgpr8 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -332,15 +332,15 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 3 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr8, 0, undef $vgpr0, implicit $sgpr8_sgpr9 ; VMEM-GFX8-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr9, 1, $vgpr0, implicit $sgpr8_sgpr9 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -386,15 +386,15 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 3 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; VMEM-GFX8-NEXT: $sgpr8 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr8_sgpr9 ; VMEM-GFX8-NEXT: $sgpr9 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 1 - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -446,24 +446,24 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr8, 0, undef $vgpr0 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr9, 0, undef $vgpr0 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN killed $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -510,24 +510,24 @@ body: | ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; VMEM-GFX8-NEXT: $sgpr8 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; VMEM-GFX8-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 1 - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 16392, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $sgpr9 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; VMEM-GFX8-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir index cac9c85130a7b..28d2ba59ebc68 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir @@ -28,17 +28,17 @@ body: | ; CHECK-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; CHECK-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; CHECK-NEXT: $vgpr1 = SI_SPILL_S32_TO_VGPR $sgpr10, 0, undef $vgpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr1 ; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 $exec ; CHECK-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR killed $vgpr1, 0 - ; CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; CHECK-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5, implicit killed $vgpr1 ; CHECK-NEXT: S_SETPC_B64 $sgpr30_sgpr31, implicit $scc S_CMP_EQ_U32 0, 0, implicit-def $scc diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir index ba2e80fdc04c8..8596e7d91f0f3 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill.mir @@ -68,74 +68,74 @@ body: | ; GCN64-MUBUF-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr12, 0, undef $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12_sgpr13 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit killed $sgpr12_sgpr13 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12_sgpr13 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 7, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 16, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 15, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr15, 3, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 28, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 31, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr15, 3, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr16, 4, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 44, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 255, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 @@ -144,13 +144,13 @@ body: | ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr17, 5, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr18, 6, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr19, 7, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 64, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 65535, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 @@ -167,13 +167,13 @@ body: | ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr25, 13, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr26, 14, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr27, 15, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 96, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 4294967295, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, undef $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 @@ -206,17 +206,17 @@ body: | ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr93, 29, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr94, 30, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr95, 31, $vgpr0, implicit killed $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 160, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr2 = S_ADD_I32 $sgpr33, 262144, implicit-def dead $scc - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, killed $sgpr2, 0, 0, 0, implicit $exec :: (store (s32) into %stack.8, align 4096, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, killed $sgpr2, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, align 4096, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; ; GCN32-MUBUF-LABEL: name: check_spill @@ -232,74 +232,74 @@ body: | ; GCN32-MUBUF-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 1, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr12, 0, undef $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 1, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12_sgpr13 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 3, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit killed $sgpr12_sgpr13 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12_sgpr13 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 3, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 7, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 16, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 15, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr15, 3, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 28, 0, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 31, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr15, 3, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr16, 4, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 44, 0, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 255, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 @@ -308,13 +308,13 @@ body: | ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr17, 5, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr18, 6, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr19, 7, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 64, 0, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 65535, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 @@ -331,13 +331,13 @@ body: | ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr25, 13, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr26, 14, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr27, 15, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 96, 0, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 4294967295, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, undef $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 @@ -370,17 +370,17 @@ body: | ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr93, 29, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr94, 30, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr95, 31, $vgpr0, implicit killed $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 160, 0, 0, implicit $exec :: (store (s32) into %stack.7, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 1, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr1 = S_ADD_I32 $sgpr33, 131072, implicit-def dead $scc - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, killed $sgpr1, 0, 0, 0, implicit $exec :: (store (s32) into %stack.8, align 4096, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, killed $sgpr1, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.8, align 4096, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; ; GCN64-FLATSCR-LABEL: name: check_spill @@ -392,74 +392,74 @@ body: | ; GCN64-FLATSCR-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr12, 0, undef $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12_sgpr13 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit killed $sgpr12_sgpr13 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12_sgpr13 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12_sgpr13_sgpr14 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 7, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 15, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr15, 3, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 31, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr15, 3, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr16, 4, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 44, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 255, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 @@ -468,13 +468,13 @@ body: | ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr17, 5, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr18, 6, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr19, 7, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 64, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 65535, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr13, 1, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr14, 2, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 @@ -491,13 +491,13 @@ body: | ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr25, 13, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr26, 14, $vgpr0, implicit $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr27, 15, $vgpr0, implicit killed $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 96, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 4294967295, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr64, 0, undef $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr65, 1, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr66, 2, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 @@ -530,17 +530,17 @@ body: | ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr93, 29, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr94, 30, $vgpr0, implicit $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr95, 31, $vgpr0, implicit killed $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 160, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: renamable $sgpr12 = IMPLICIT_DEF ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr12, 0, undef $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr2 = S_ADD_I32 $sgpr33, 4096, implicit-def dead $scc - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, killed $sgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.8, align 4096, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, killed $sgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.8, align 4096, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 renamable $sgpr12 = IMPLICIT_DEF SI_SPILL_S32_SAVE killed $sgpr12, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 @@ -626,53 +626,53 @@ body: | ; GCN64-MUBUF-NEXT: $sgpr29 = S_ADDC_U32 $sgpr29, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr28_sgpr29_sgpr30_sgpr31 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13 ; GCN64-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 1 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 7, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 16, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14 ; GCN64-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 2 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 15, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 28, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN64-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 ; GCN64-MUBUF-NEXT: $sgpr15 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 3 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 31, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 44, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 ; GCN64-MUBUF-NEXT: $sgpr15 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 3 ; GCN64-MUBUF-NEXT: $sgpr16 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 4 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 255, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 64, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -681,12 +681,12 @@ body: | ; GCN64-MUBUF-NEXT: $sgpr17 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 5 ; GCN64-MUBUF-NEXT: $sgpr18 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 6 ; GCN64-MUBUF-NEXT: $sgpr19 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 7 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 65535, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 96, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -703,12 +703,12 @@ body: | ; GCN64-MUBUF-NEXT: $sgpr25 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 13 ; GCN64-MUBUF-NEXT: $sgpr26 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 14 ; GCN64-MUBUF-NEXT: $sgpr27 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 15 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 4294967295, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 160, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr64 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-MUBUF-NEXT: $sgpr65 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-MUBUF-NEXT: $sgpr66 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -741,15 +741,15 @@ body: | ; GCN64-MUBUF-NEXT: $sgpr93 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 29 ; GCN64-MUBUF-NEXT: $sgpr94 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 30 ; GCN64-MUBUF-NEXT: $sgpr95 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 31 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-MUBUF-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr2 = S_ADD_I32 $sgpr33, 262144, implicit-def dead $scc - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, killed $sgpr2, 0, 0, 0, implicit $exec :: (load (s32) from %stack.8, align 4096, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, killed $sgpr2, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, align 4096, addrspace 5) ; GCN64-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr28_sgpr29_sgpr30_sgpr31, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-MUBUF-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; ; GCN32-MUBUF-LABEL: name: check_reload @@ -764,53 +764,53 @@ body: | ; GCN32-MUBUF-NEXT: $sgpr97 = S_ADDC_U32 $sgpr97, 0, implicit-def dead $scc, implicit $scc, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 1, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 3, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13 ; GCN32-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 1 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 7, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 16, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 16, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14 ; GCN32-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN32-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 2 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 15, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 28, 0, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 28, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN32-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN32-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 ; GCN32-MUBUF-NEXT: $sgpr15 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 3 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 31, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 44, 0, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 44, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN32-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN32-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 ; GCN32-MUBUF-NEXT: $sgpr15 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 3 ; GCN32-MUBUF-NEXT: $sgpr16 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 4 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 255, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 64, 0, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 64, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN32-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN32-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -819,12 +819,12 @@ body: | ; GCN32-MUBUF-NEXT: $sgpr17 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 5 ; GCN32-MUBUF-NEXT: $sgpr18 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 6 ; GCN32-MUBUF-NEXT: $sgpr19 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 7 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 65535, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 96, 0, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 96, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN32-MUBUF-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN32-MUBUF-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -841,12 +841,12 @@ body: | ; GCN32-MUBUF-NEXT: $sgpr25 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 13 ; GCN32-MUBUF-NEXT: $sgpr26 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 14 ; GCN32-MUBUF-NEXT: $sgpr27 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 15 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 4294967295, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 160, 0, 0, implicit $exec :: (load (s32) from %stack.7, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 160, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr64 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN32-MUBUF-NEXT: $sgpr65 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN32-MUBUF-NEXT: $sgpr66 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -879,15 +879,15 @@ body: | ; GCN32-MUBUF-NEXT: $sgpr93 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 29 ; GCN32-MUBUF-NEXT: $sgpr94 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 30 ; GCN32-MUBUF-NEXT: $sgpr95 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 31 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; GCN32-MUBUF-NEXT: $sgpr0 = S_MOV_B32 $exec_lo ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 1, implicit-def $vgpr0 - ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr1 = S_ADD_I32 $sgpr33, 131072, implicit-def dead $scc - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, killed $sgpr1, 0, 0, 0, implicit $exec :: (load (s32) from %stack.8, align 4096, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, killed $sgpr1, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.8, align 4096, addrspace 5) ; GCN32-MUBUF-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.9, addrspace 5) + ; GCN32-MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN32-MUBUF-NEXT: $exec_lo = S_MOV_B32 killed $sgpr0, implicit killed $vgpr0 ; ; GCN64-FLATSCR-LABEL: name: check_reload @@ -898,53 +898,53 @@ body: | ; GCN64-FLATSCR-NEXT: $flat_scr_hi = S_ADDC_U32 $sgpr1, 0, implicit-def dead $scc, implicit $scc ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13 ; GCN64-FLATSCR-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 1 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 7, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14 ; GCN64-FLATSCR-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-FLATSCR-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 2 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 15, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15 ; GCN64-FLATSCR-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-FLATSCR-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 ; GCN64-FLATSCR-NEXT: $sgpr15 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 3 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 31, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 44, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.4, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 44, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 ; GCN64-FLATSCR-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-FLATSCR-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 ; GCN64-FLATSCR-NEXT: $sgpr15 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 3 ; GCN64-FLATSCR-NEXT: $sgpr16 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 4 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 255, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 64, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.5, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 64, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19 ; GCN64-FLATSCR-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-FLATSCR-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -953,12 +953,12 @@ body: | ; GCN64-FLATSCR-NEXT: $sgpr17 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 5 ; GCN64-FLATSCR-NEXT: $sgpr18 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 6 ; GCN64-FLATSCR-NEXT: $sgpr19 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 7 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 65535, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 96, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.6, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 96, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27 ; GCN64-FLATSCR-NEXT: $sgpr13 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-FLATSCR-NEXT: $sgpr14 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -975,12 +975,12 @@ body: | ; GCN64-FLATSCR-NEXT: $sgpr25 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 13 ; GCN64-FLATSCR-NEXT: $sgpr26 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 14 ; GCN64-FLATSCR-NEXT: $sgpr27 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 15 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 4294967295, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 160, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.7, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 160, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr64 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95 ; GCN64-FLATSCR-NEXT: $sgpr65 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 1 ; GCN64-FLATSCR-NEXT: $sgpr66 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 2 @@ -1013,15 +1013,15 @@ body: | ; GCN64-FLATSCR-NEXT: $sgpr93 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 29 ; GCN64-FLATSCR-NEXT: $sgpr94 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 30 ; GCN64-FLATSCR-NEXT: $sgpr95 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 31 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GCN64-FLATSCR-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 1, implicit-def $vgpr0 - ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr2 = S_ADD_I32 $sgpr33, 4096, implicit-def dead $scc - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR killed $sgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.8, align 4096, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR killed $sgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.8, align 4096, addrspace 5) ; GCN64-FLATSCR-NEXT: $sgpr12 = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 0 - ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.9, addrspace 5) + ; GCN64-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.9, addrspace 5) ; GCN64-FLATSCR-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 renamable $sgpr12 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 diff --git a/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll b/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll index 6a88be6e55859..36a7ee057d24b 100644 --- a/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll +++ b/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll @@ -354,14 +354,13 @@ declare half @_Z4pownDhi(half, i32) ; GCN-NATIVE: %__log2 = tail call fast half @llvm.log2.f16(half %__fabs) ; GCN-NATIVE: %pownI2F = sitofp i32 %y to half ; GCN-NATIVE: %__ylogx = fmul fast half %__log2, %pownI2F -; GCN-NATIVE: %__exp2 = tail call fast half @llvm.exp2.f16(half %__ylogx) +; GCN-NATIVE: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) half @llvm.exp2.f16(half %__ylogx) ; GCN-NATIVE: %__ytou = trunc i32 %y to i16 ; GCN-NATIVE: %__yeven = shl i16 %__ytou, 15 ; GCN-NATIVE: %0 = bitcast half %x to i16 ; GCN-NATIVE: %__pow_sign = and i16 %__yeven, %0 -; GCN-NATIVE: %1 = bitcast half %__exp2 to i16 -; GCN-NATIVE: %2 = or disjoint i16 %__pow_sign, %1 -; GCN-NATIVE: %3 = bitcast i16 %2 to half +; GCN-NATIVE: %1 = bitcast i16 %__pow_sign to half +; GCN-NATIVE: %__pow_sign1 = tail call fast half @llvm.copysign.f16(half %__exp2, half %1) define half @test_pown_f16(half %x, i32 %y) { entry: %call = call fast half @_Z4pownDhi(half %x, i32 %y) @@ -374,8 +373,8 @@ declare float @_Z4pownfi(float, i32) ; GCN: %__fabs = tail call fast float @llvm.fabs.f32(float %tmp) ; GCN: %__log2 = tail call fast float @llvm.log2.f32(float %__fabs) ; GCN: %__ylogx = fmul fast float %__log2, 1.013000e+03 -; GCN: %__exp2 = tail call fast float @llvm.exp2.f32(float %__ylogx) -; GCN: %[[r0:.*]] = tail call float @llvm.copysign.f32(float %__exp2, float %tmp) +; GCN: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float %__ylogx) +; GCN: %[[r0:.*]] = tail call fast float @llvm.copysign.f32(float %__exp2, float %tmp) ; GCN: store float %[[r0]], ptr addrspace(1) %a, align 4 define amdgpu_kernel void @test_pow(ptr addrspace(1) nocapture %a) { entry: @@ -388,7 +387,7 @@ entry: ; GCN-LABEL: {{^}}define amdgpu_kernel void @test_powr ; GCN: %__log2 = tail call fast float @llvm.log2.f32(float %tmp) ; GCN: %__ylogx = fmul fast float %tmp1, %__log2 -; GCN: %__exp2 = tail call fast float @llvm.exp2.f32(float %__ylogx) +; GCN: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float %__ylogx) ; GCN: store float %__exp2, ptr addrspace(1) %a, align 4 define amdgpu_kernel void @test_powr(ptr addrspace(1) nocapture %a) { entry: @@ -406,13 +405,13 @@ entry: ; GCN: %__log2 = tail call fast float @llvm.log2.f32(float %__fabs) ; GCN: %pownI2F = sitofp i32 %conv to float ; GCN: %__ylogx = fmul fast float %__log2, %pownI2F -; GCN: %__exp2 = tail call fast float @llvm.exp2.f32(float %__ylogx) +; GCN: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float %__ylogx) ; GCN: %__yeven = shl i32 %conv, 31 ; GCN: %[[r0:.*]] = bitcast float %tmp to i32 ; GCN: %__pow_sign = and i32 %__yeven, %[[r0]] -; GCN: %[[r1:.*]] = bitcast float %__exp2 to i32 -; GCN: %[[r2:.*]] = or disjoint i32 %__pow_sign, %[[r1]] -; GCN: store i32 %[[r2]], ptr addrspace(1) %a, align 4 +; GCN: %[[r1:.*]] = bitcast i32 %__pow_sign to float +; GCN: %[[r2:.*]] = tail call fast float @llvm.copysign.f32(float %__exp2, float %[[r1]]) +; GCN: store float %[[r2]], ptr addrspace(1) %a, align 4 define amdgpu_kernel void @test_pown(ptr addrspace(1) nocapture %a) { entry: %tmp = load float, ptr addrspace(1) %a, align 4 @@ -431,8 +430,8 @@ declare <2 x half> @_Z3powDv2_DhS_(<2 x half>, <2 x half>) ; GCN: %__fabs = tail call fast half @llvm.fabs.f16(half %x) ; GCN: %__log2 = tail call fast half @llvm.log2.f16(half %__fabs) ; GCN: %__ylogx = fmul fast half %__log2, 0xH4A80 -; GCN: %__exp2 = tail call fast half @llvm.exp2.f16(half %__ylogx) -; GCN: %1 = tail call half @llvm.copysign.f16(half %__exp2, half %x) +; GCN: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) half @llvm.exp2.f16(half %__ylogx) +; GCN: %__pow_sign1 = tail call fast half @llvm.copysign.f16(half %__exp2, half %x) define half @test_pow_fast_f16__y_13(half %x) { %powr = tail call fast half @_Z3powDhDh(half %x, half 13.0) ret half %powr @@ -442,8 +441,8 @@ define half @test_pow_fast_f16__y_13(half %x) { ; GCN: %__fabs = tail call fast <2 x half> @llvm.fabs.v2f16(<2 x half> %x) ; GCN: %__log2 = tail call fast <2 x half> @llvm.log2.v2f16(<2 x half> %__fabs) ; GCN: %__ylogx = fmul fast <2 x half> %__log2, splat (half 0xH4A80) -; GCN: %__exp2 = tail call fast <2 x half> @llvm.exp2.v2f16(<2 x half> %__ylogx) -; GCN: %1 = tail call <2 x half> @llvm.copysign.v2f16(<2 x half> %__exp2, <2 x half> %x) +; GCN: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) <2 x half> @llvm.exp2.v2f16(<2 x half> %__ylogx) +; GCN: %__pow_sign1 = tail call fast <2 x half> @llvm.copysign.v2f16(<2 x half> %__exp2, <2 x half> %x) define <2 x half> @test_pow_fast_v2f16__y_13(<2 x half> %x) { %powr = tail call fast <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> ) ret <2 x half> %powr @@ -657,7 +656,7 @@ declare float @_Z5log10f(float) ; GCN: %tmp1 = load float, ptr addrspace(1) %arrayidx1, align 4 ; GCN: %__log2 = tail call fast float @llvm.log2.f32(float %tmp) ; GCN: %__ylogx = fmul fast float %tmp1, %__log2 -; GCN: %__exp2 = tail call fast float @llvm.exp2.f32(float %__ylogx) +; GCN: %__exp2 = tail call fast nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float %__ylogx) ; GCN: store float %__exp2, ptr addrspace(1) %a, align 4 define amdgpu_kernel void @test_use_native_powr(ptr addrspace(1) nocapture %a) { entry: diff --git a/llvm/test/CodeGen/AMDGPU/sitofp.f16.ll b/llvm/test/CodeGen/AMDGPU/sitofp.f16.ll index 792bd03ad15aa..3b61a5fa45604 100644 --- a/llvm/test/CodeGen/AMDGPU/sitofp.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/sitofp.f16.ll @@ -53,7 +53,7 @@ define amdgpu_kernel void @sitofp_i16_to_f16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir index 9d25df4738709..4b3fb5741dbed 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir @@ -18,9 +18,9 @@ body: | ; CHECK: liveins: $agpr0_agpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_A64_SAVE killed $agpr0_agpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) ... @@ -43,9 +43,9 @@ body: | ; CHECK: liveins: $agpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_A64_SAVE killed $agpr0_agpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) ... @@ -66,9 +66,9 @@ body: | ; CHECK: liveins: $agpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec, implicit-def $agpr0_agpr1, implicit $agpr0_agpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1 - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $agpr0_agpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_A64_SAVE killed $agpr0_agpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) ... diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr.mir b/llvm/test/CodeGen/AMDGPU/spill-agpr.mir index 3f6956b83ae92..d791b29ec579d 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-agpr.mir @@ -255,14 +255,14 @@ body: | ; GFX908-EXPANDED-NEXT: {{ $}} ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0 ; GFX908-EXPANDED-NEXT: $vgpr63 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec - ; GFX908-EXPANDED-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GFX908-EXPANDED-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr63, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GFX908-EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; GFX908-EXPANDED-NEXT: {{ $}} ; GFX908-EXPANDED-NEXT: bb.1: ; GFX908-EXPANDED-NEXT: successors: %bb.2(0x80000000) ; GFX908-EXPANDED-NEXT: {{ $}} ; GFX908-EXPANDED-NEXT: bb.2: - ; GFX908-EXPANDED-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GFX908-EXPANDED-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GFX908-EXPANDED-NEXT: $agpr0 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr63, implicit $exec ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit undef $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX908-EXPANDED-NEXT: S_NOP 0, implicit undef $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 @@ -320,14 +320,14 @@ body: | ; GFX90A-EXPANDED-NEXT: liveins: $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239 ; GFX90A-EXPANDED-NEXT: {{ $}} ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $agpr0 - ; GFX90A-EXPANDED-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GFX90A-EXPANDED-NEXT: BUFFER_STORE_DWORD_OFFSET killed $agpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GFX90A-EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; GFX90A-EXPANDED-NEXT: {{ $}} ; GFX90A-EXPANDED-NEXT: bb.1: ; GFX90A-EXPANDED-NEXT: successors: %bb.2(0x80000000) ; GFX90A-EXPANDED-NEXT: {{ $}} ; GFX90A-EXPANDED-NEXT: bb.2: - ; GFX90A-EXPANDED-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GFX90A-EXPANDED-NEXT: $agpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit undef $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit undef $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GFX90A-EXPANDED-NEXT: S_NOP 0, implicit undef $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 diff --git a/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir b/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir index f4edafd9443ab..fd6efd536e504 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir @@ -23,7 +23,7 @@ body: | ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr8_sgpr9 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr8_sgpr9 ; GCN-NEXT: renamable $sgpr1 = COPY $sgpr2 ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF @@ -33,7 +33,7 @@ body: | ; GCN-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr3, 3, killed $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3 ; GCN-NEXT: renamable $sgpr8 = COPY renamable $sgpr1 ; GCN-NEXT: $sgpr0_sgpr1 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1 ; GCN-NEXT: S_ENDPGM 0, implicit $sgpr8 renamable $sgpr1 = COPY $sgpr2 @@ -61,7 +61,7 @@ body: | ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr8_sgpr9 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr8_sgpr9 ; GCN-NEXT: renamable $sgpr1 = COPY $sgpr2 ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF @@ -70,7 +70,7 @@ body: | ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr2, 2, killed $vgpr0 ; GCN-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr3, 3, killed $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3 ; GCN-NEXT: $sgpr0_sgpr1 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1 ; GCN-NEXT: S_ENDPGM 0 renamable $sgpr1 = COPY $sgpr2 @@ -96,10 +96,10 @@ body: | ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GCN-NEXT: {{ $}} ; GCN-NEXT: renamable $vgpr1 = COPY $vgpr2, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 12, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 12, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; GCN-NEXT: renamable $vgpr8 = COPY $vgpr2, implicit $exec ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr8 renamable $vgpr1 = COPY $vgpr2 @@ -126,10 +126,10 @@ body: | ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GCN-NEXT: {{ $}} ; GCN-NEXT: renamable $vgpr1 = COPY $vgpr2, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 12, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr2, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr3, $sgpr100_sgpr101_sgpr102_sgpr103, $sgpr32, 12, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) ; GCN-NEXT: S_ENDPGM 0 renamable $vgpr1 = COPY $vgpr2 SI_SPILL_V128_SAVE renamable killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, align 4, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir b/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir index bb87b6e52da89..4b4266355b8ef 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir @@ -162,7 +162,7 @@ body: | ; GFX950-NEXT: $agpr25 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr16, implicit $exec, implicit killed $vgpr16_vgpr17_vgpr18_vgpr19 ; GFX950-NEXT: $agpr26 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr23, implicit $exec, implicit-def $vgpr20_vgpr21_vgpr22_vgpr23, implicit $vgpr20_vgpr21_vgpr22_vgpr23 ; GFX950-NEXT: $agpr27 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr22, implicit $exec, implicit $vgpr20_vgpr21_vgpr22_vgpr23 - ; GFX950-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr20_vgpr21, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr20_vgpr21_vgpr22_vgpr23 :: (store (s64) into %stack.5, align 4, addrspace 5) + ; GFX950-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr20_vgpr21, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr20_vgpr21_vgpr22_vgpr23 :: ("amdgpu-thread-private" store (s64) into %stack.5, align 4, addrspace 5) ; GFX950-NEXT: $vgpr0 = IMPLICIT_DEF ; GFX950-NEXT: $agpr5 = COPY $agpr6, implicit-def $agpr2_agpr3_agpr4_agpr5 ; GFX950-NEXT: $agpr4 = COPY $agpr7, implicit $agpr2_agpr3_agpr4_agpr5 @@ -191,7 +191,7 @@ body: | ; GFX950-NEXT: DS_WRITE_B128_gfx9 renamable $vgpr0, killed renamable $agpr2_agpr3_agpr4_agpr5, 4096, 0, implicit $exec ; GFX950-NEXT: $agpr5 = COPY $agpr26, implicit-def $agpr2_agpr3_agpr4_agpr5 ; GFX950-NEXT: $agpr4 = COPY $agpr27, implicit $agpr2_agpr3_agpr4_agpr5 - ; GFX950-NEXT: $agpr2_agpr3 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr2_agpr3_agpr4_agpr5, implicit $agpr2_agpr3_agpr4_agpr5 :: (load (s64) from %stack.5, align 4, addrspace 5) + ; GFX950-NEXT: $agpr2_agpr3 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr2_agpr3_agpr4_agpr5, implicit $agpr2_agpr3_agpr4_agpr5 :: ("amdgpu-thread-private" load (s64) from %stack.5, align 4, addrspace 5) ; GFX950-NEXT: DS_WRITE_B128_gfx9 renamable $vgpr0, killed renamable $agpr2_agpr3_agpr4_agpr5, 5120, 0, implicit $exec ; GFX950-NEXT: S_ENDPGM 0 renamable $agpr0_agpr1 = IMPLICIT_DEF @@ -266,7 +266,7 @@ body: | ; GFX950-NEXT: $agpr23 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr18, implicit $exec, implicit $vgpr16_vgpr17_vgpr18_vgpr19 ; GFX950-NEXT: $agpr24 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr17, implicit $exec, implicit $vgpr16_vgpr17_vgpr18_vgpr19 ; GFX950-NEXT: $agpr25 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr16, implicit $exec, implicit killed $vgpr16_vgpr17_vgpr18_vgpr19 - ; GFX950-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.5, align 4, addrspace 5) + ; GFX950-NEXT: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr20_vgpr21_vgpr22_vgpr23, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s128) into %stack.5, align 4, addrspace 5) ; GFX950-NEXT: $vgpr0 = IMPLICIT_DEF ; GFX950-NEXT: $agpr5 = COPY $agpr6, implicit-def $agpr2_agpr3_agpr4_agpr5 ; GFX950-NEXT: $agpr4 = COPY $agpr7, implicit $agpr2_agpr3_agpr4_agpr5 @@ -293,7 +293,7 @@ body: | ; GFX950-NEXT: $agpr3 = COPY $agpr24, implicit $agpr2_agpr3_agpr4_agpr5 ; GFX950-NEXT: $agpr2 = COPY $agpr25, implicit $agpr2_agpr3_agpr4_agpr5 ; GFX950-NEXT: DS_WRITE_B128_gfx9 renamable $vgpr0, killed renamable $agpr2_agpr3_agpr4_agpr5, 4096, 0, implicit $exec - ; GFX950-NEXT: $agpr2_agpr3_agpr4_agpr5 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.5, align 4, addrspace 5) + ; GFX950-NEXT: $agpr2_agpr3_agpr4_agpr5 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s128) from %stack.5, align 4, addrspace 5) ; GFX950-NEXT: DS_WRITE_B128_gfx9 renamable $vgpr0, killed renamable $agpr2_agpr3_agpr4_agpr5, 5120, 0, implicit $exec ; GFX950-NEXT: S_ENDPGM 0 renamable $agpr0_agpr1 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir b/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir index 639bf6a6d550c..7066afbcf9663 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir @@ -50,28 +50,28 @@ body: | ; GFX9-NEXT: $vcc = IMPLICIT_DEF ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX9-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX9-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_lo, 0, undef $vgpr0, implicit $vcc ; GFX9-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_hi, 1, $vgpr0, implicit $vcc - ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GFX9-NEXT: $vcc = IMPLICIT_DEF ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX9-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX9-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_lo, 0, undef $vgpr0, implicit $vcc ; GFX9-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_hi, 1, $vgpr0, implicit killed $vcc - ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GFX9-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX9-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GFX9-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GFX9-NEXT: $vcc_lo = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $vcc ; GFX9-NEXT: $vcc_hi = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 1 - ; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX9-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr12_sgpr13_sgpr14_sgpr15, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX9-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; ; GFX10-LABEL: name: check_vcc @@ -87,28 +87,28 @@ body: | ; GFX10-NEXT: $vcc = IMPLICIT_DEF ; GFX10-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX10-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX10-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_lo, 0, undef $vgpr0, implicit $vcc ; GFX10-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_hi, 1, $vgpr0, implicit $vcc - ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX10-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GFX10-NEXT: $vcc = IMPLICIT_DEF ; GFX10-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX10-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX10-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_lo, 0, undef $vgpr0, implicit $vcc ; GFX10-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_hi, 1, $vgpr0, implicit killed $vcc - ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX10-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GFX10-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX10-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GFX10-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GFX10-NEXT: $vcc_lo = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $vcc ; GFX10-NEXT: $vcc_hi = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 1 - ; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GFX10-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr33, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX10-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; ; GFX11-LABEL: name: check_vcc @@ -118,28 +118,28 @@ body: | ; GFX11-NEXT: $vcc = IMPLICIT_DEF ; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX11-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX11-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_lo, 0, undef $vgpr0, implicit $vcc ; GFX11-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_hi, 1, $vgpr0, implicit $vcc - ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX11-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GFX11-NEXT: $vcc = IMPLICIT_DEF ; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX11-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX11-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_lo, 0, undef $vgpr0, implicit $vcc ; GFX11-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR $vcc_hi, 1, $vgpr0, implicit killed $vcc - ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX11-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 ; GFX11-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec ; GFX11-NEXT: $exec = S_MOV_B64 3, implicit-def $vgpr0 - ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; GFX11-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GFX11-NEXT: $vcc_lo = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0, implicit-def $vcc ; GFX11-NEXT: $vcc_hi = SI_RESTORE_S32_FROM_VGPR killed $vgpr0, 1 - ; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GFX11-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX11-NEXT: $exec = S_MOV_B64 killed $sgpr0_sgpr1, implicit killed $vgpr0 $vcc = IMPLICIT_DEF SI_SPILL_S64_SAVE $vcc, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 diff --git a/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir b/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir index beeb9b2df8b01..90c1b9b44dd1c 100644 --- a/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir +++ b/llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir @@ -17,9 +17,9 @@ body: | ; GCN: liveins: $agpr30, $agpr31, $agpr28_agpr29, $agpr24_agpr25_agpr26_agpr27, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s96) into %stack.0, align 4, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr31, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s96) from %stack.0, align 4, addrspace 5) + ; GCN-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25_agpr26_agpr27, implicit $agpr28_agpr29, implicit $agpr30 SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -43,10 +43,10 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s64) into %stack.0, align 4, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr30, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr31, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s64) from %stack.0, align 4, addrspace 5) + ; GCN-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25_agpr26_agpr27, implicit $agpr28_agpr29 SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -71,11 +71,11 @@ body: | ; GCN-NEXT: $agpr29 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $vgpr3 = V_ACCVGPR_READ_B32_e64 $agpr29, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $vgpr2 = V_ACCVGPR_READ_B32_e64 $agpr30, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $vgpr1 = V_ACCVGPR_READ_B32_e64 $agpr31, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25_agpr26_agpr27, implicit $agpr28 SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -127,9 +127,9 @@ body: | ; GCN: liveins: $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr52_vgpr53, $vgpr48_vgpr49_vgpr50_vgpr51, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s96) into %stack.0, align 4, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: (load (s96) from %stack.0, align 4, addrspace 5) + ; GCN-NEXT: $agpr0_agpr1_agpr2 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr52_vgpr53, implicit $vgpr54 SI_SPILL_A128_SAVE killed $agpr0_agpr1_agpr2_agpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $agpr0_agpr1_agpr2_agpr3 = SI_SPILL_A128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -153,10 +153,10 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s64) into %stack.0, align 4, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: (load (s64) from %stack.0, align 4, addrspace 5) + ; GCN-NEXT: $agpr0_agpr1 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr52_vgpr53 SI_SPILL_A128_SAVE killed $agpr0_agpr1_agpr2_agpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $agpr0_agpr1_agpr2_agpr3 = SI_SPILL_A128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -181,11 +181,11 @@ body: | ; GCN-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $agpr3 = V_ACCVGPR_WRITE_B32_e64 $vgpr53, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $agpr2 = V_ACCVGPR_WRITE_B32_e64 $vgpr54, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $agpr1 = V_ACCVGPR_WRITE_B32_e64 $vgpr55, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: $agpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $agpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, implicit $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr52 SI_SPILL_A128_SAVE killed $agpr0_agpr1_agpr2_agpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $agpr0_agpr1_agpr2_agpr3 = SI_SPILL_A128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir b/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir index 69895833efccb..834e42eee9685 100644 --- a/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir +++ b/llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir @@ -18,9 +18,9 @@ body: | ; EXPANDED-NEXT: successors: %bb.1(0x80000000) ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 - ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) + ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, align 4, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 - ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, align 4, addrspace 5) + ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.0, align 4, addrspace 5) ; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: bb.1: @@ -29,8 +29,8 @@ body: | ; EXPANDED-NEXT: S_NOP 1 ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: bb.2: - ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.0, align 4, addrspace 5) - ; EXPANDED-NEXT: $vgpr0_hi16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.1, align 4, addrspace 5) + ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.0, align 4, addrspace 5) + ; EXPANDED-NEXT: $vgpr0_hi16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.1, align 4, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_lo16, implicit killed renamable $vgpr0_hi16 ; ; SRAMECC-EXPANDED-LABEL: name: spill_restore_vgpr16 @@ -38,9 +38,9 @@ body: | ; SRAMECC-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 - ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 - ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.0, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: bb.1: @@ -49,9 +49,9 @@ body: | ; SRAMECC-EXPANDED-NEXT: S_NOP 1 ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: bb.2: - ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.0, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.0, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: $vgpr0_lo16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec - ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.1, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: $vgpr0_hi16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_lo16, implicit killed renamable $vgpr0_hi16 bb.0: @@ -86,9 +86,9 @@ body: | ; EXPANDED-NEXT: successors: %bb.1(0x80000000) ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 - ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) + ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, align 4, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 - ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, align 4, addrspace 5) + ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.0, align 4, addrspace 5) ; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: bb.1: @@ -98,8 +98,8 @@ body: | ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: bb.2: ; EXPANDED-NEXT: S_NOP 1 - ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.0, align 4, addrspace 5) - ; EXPANDED-NEXT: $vgpr0_hi16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.1, align 4, addrspace 5) + ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.0, align 4, addrspace 5) + ; EXPANDED-NEXT: $vgpr0_hi16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.1, align 4, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_lo16, implicit killed renamable $vgpr0_hi16 ; ; SRAMECC-EXPANDED-LABEL: name: spill_restore_vgpr16_middle_of_block @@ -107,9 +107,9 @@ body: | ; SRAMECC-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 - ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 - ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.0, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: bb.1: @@ -119,9 +119,9 @@ body: | ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: bb.2: ; SRAMECC-EXPANDED-NEXT: S_NOP 1 - ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.0, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.0, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: $vgpr0_lo16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec - ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.1, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: $vgpr0_hi16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_lo16, implicit killed renamable $vgpr0_hi16 bb.0: @@ -157,9 +157,9 @@ body: | ; EXPANDED-NEXT: successors: %bb.1(0x80000000) ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 - ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) + ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, align 4, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 - ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, align 4, addrspace 5) + ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.0, align 4, addrspace 5) ; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: bb.1: @@ -168,17 +168,17 @@ body: | ; EXPANDED-NEXT: S_NOP 1 ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: bb.2: - ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.0, align 4, addrspace 5) - ; EXPANDED-NEXT: $vgpr0_hi16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.1, align 4, addrspace 5) + ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.0, align 4, addrspace 5) + ; EXPANDED-NEXT: $vgpr0_hi16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.1, align 4, addrspace 5) ; ; SRAMECC-EXPANDED-LABEL: name: spill_restore_vgpr16_end_of_block ; SRAMECC-EXPANDED: bb.0: ; SRAMECC-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 - ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit renamable $vgpr0_lo16 - ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.0, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: bb.1: @@ -187,9 +187,9 @@ body: | ; SRAMECC-EXPANDED-NEXT: S_NOP 1 ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: bb.2: - ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.0, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.0, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: $vgpr0_lo16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec - ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.1, align 4, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.1, align 4, addrspace 5) ; SRAMECC-EXPANDED-NEXT: $vgpr0_hi16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec bb.0: successors: %bb.1(0x80000000) diff --git a/llvm/test/CodeGen/AMDGPU/spillv16.ll b/llvm/test/CodeGen/AMDGPU/spillv16.ll index c16793675f6a2..62ea4dc7a1865 100644 --- a/llvm/test/CodeGen/AMDGPU/spillv16.ll +++ b/llvm/test/CodeGen/AMDGPU/spillv16.ll @@ -64,11 +64,11 @@ define void @spill_i16_alu() { ; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x7b, v0.l -; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 ; 2-byte Folded Spill +; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 nv ; 2-byte Folded Spill ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-TRUE16-NEXT: ;;#ASMSTART ; GFX1250-TRUE16-NEXT: ;;#ASMEND -; GFX1250-TRUE16-NEXT: scratch_load_u16 v1, off, s32 offset:2 th:TH_LOAD_LU ; 2-byte Folded Reload +; GFX1250-TRUE16-NEXT: scratch_load_u16 v1, off, s32 offset:2 th:TH_LOAD_LU nv ; 2-byte Folded Reload ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 @@ -83,11 +83,11 @@ define void @spill_i16_alu() { ; GFX1250-FAKE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: v_add_nc_u16 v0, 0x7b, v0 -; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill +; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:4 nv ; 4-byte Folded Spill ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-FAKE16-NEXT: ;;#ASMSTART ; GFX1250-FAKE16-NEXT: ;;#ASMEND -; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:4 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:4 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS @@ -207,13 +207,13 @@ define void @spill_i16_alu_two_vals() { ; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x7b, v0.l -; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:6 ; 2-byte Folded Spill +; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:6 nv ; 2-byte Folded Spill ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-TRUE16-NEXT: ;;#ASMSTART ; GFX1250-TRUE16-NEXT: ;;#ASMEND ; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 offset:4 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: scratch_load_u16 v1, off, s32 offset:6 th:TH_LOAD_LU ; 2-byte Folded Reload +; GFX1250-TRUE16-NEXT: scratch_load_u16 v1, off, s32 offset:6 th:TH_LOAD_LU nv ; 2-byte Folded Reload ; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x7b, v0.l ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l @@ -232,13 +232,13 @@ define void @spill_i16_alu_two_vals() { ; GFX1250-FAKE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: v_add_nc_u16 v0, 0x7b, v0 -; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill +; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; 4-byte Folded Spill ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-FAKE16-NEXT: ;;#ASMSTART ; GFX1250-FAKE16-NEXT: ;;#ASMEND ; GFX1250-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:4 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: scratch_load_b32 v1, off, s32 offset:8 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-FAKE16-NEXT: scratch_load_b32 v1, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-FAKE16-NEXT: v_add_nc_u16 v0, 0x7b, v0 ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 @@ -326,11 +326,11 @@ define void @spill_i16() { ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:4 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: ;;#ASMSTART ; GFX1250-NEXT: ;;#ASMEND -; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:4 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:4 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS @@ -405,11 +405,11 @@ define void @spill_half() { ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:4 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:4 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: ;;#ASMSTART ; GFX1250-NEXT: ;;#ASMEND -; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:4 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:4 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS @@ -484,11 +484,11 @@ define void @spill_i16_from_v2i16() { ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: scratch_load_u16 v0, off, s32 offset:2 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: ;;#ASMSTART ; GFX1250-NEXT: ;;#ASMEND -; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS @@ -585,19 +585,19 @@ define void @spill_2xi16_from_v2i16() { ; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 offset:2 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: s_clause 0x1 ; 4-byte Folded Spill -; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:12 +; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:12 nv ; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill +; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; 4-byte Folded Spill ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-TRUE16-NEXT: ;;#ASMSTART ; GFX1250-TRUE16-NEXT: ;;#ASMEND -; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:12 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:12 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 -; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 @@ -610,19 +610,19 @@ define void @spill_2xi16_from_v2i16() { ; GFX1250-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:2 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: s_clause 0x1 ; 4-byte Folded Spill -; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 +; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; GFX1250-FAKE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:12 ; 4-byte Folded Spill +; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:12 nv ; 4-byte Folded Spill ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-FAKE16-NEXT: ;;#ASMSTART ; GFX1250-FAKE16-NEXT: ;;#ASMEND -; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 -; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:12 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:12 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 @@ -721,14 +721,14 @@ define void @spill_2xi16_from_v2i16_one_free_reg() { ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-TRUE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill +; GFX1250-TRUE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; 4-byte Folded Spill ; GFX1250-TRUE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-TRUE16-NEXT: ;;#ASMSTART ; GFX1250-TRUE16-NEXT: ;;#ASMEND ; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v7.l ; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 offset:2 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 -; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-TRUE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-TRUE16-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS ; GFX1250-TRUE16-NEXT: s_wait_storecnt 0x0 @@ -743,13 +743,13 @@ define void @spill_2xi16_from_v2i16_one_free_reg() { ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-FAKE16-NEXT: scratch_load_u16 v0, off, s32 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill +; GFX1250-FAKE16-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; 4-byte Folded Spill ; GFX1250-FAKE16-NEXT: s_wait_xcnt 0x0 ; GFX1250-FAKE16-NEXT: ;;#ASMSTART ; GFX1250-FAKE16-NEXT: ;;#ASMEND ; GFX1250-FAKE16-NEXT: scratch_store_b16 off, v7, s32 offset:2 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 -; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX1250-FAKE16-NEXT: scratch_store_b16 off, v0, s32 scope:SCOPE_SYS ; GFX1250-FAKE16-NEXT: s_wait_storecnt 0x0 @@ -814,11 +814,11 @@ define void @spill_v2i16() { ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:4 scope:SCOPE_SYS ; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:8 ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:8 nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: ;;#ASMSTART ; GFX1250-NEXT: ;;#ASMEND -; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v0, off, s32 offset:8 th:TH_LOAD_LU nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: scratch_store_b32 off, v0, s32 offset:4 scope:SCOPE_SYS diff --git a/llvm/test/CodeGen/AMDGPU/spillv16.mir b/llvm/test/CodeGen/AMDGPU/spillv16.mir index ba2d926eb8883..73c7200cc4496 100644 --- a/llvm/test/CodeGen/AMDGPU/spillv16.mir +++ b/llvm/test/CodeGen/AMDGPU/spillv16.mir @@ -34,8 +34,8 @@ body: | ; EXPANDED-NEXT: successors: %bb.1(0x80000000) ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 - ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, addrspace 5) - ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, addrspace 5) + ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, addrspace 5) + ; EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.0, addrspace 5) ; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: bb.1: @@ -44,8 +44,8 @@ body: | ; EXPANDED-NEXT: S_NOP 1 ; EXPANDED-NEXT: {{ $}} ; EXPANDED-NEXT: bb.2: - ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.0, addrspace 5) - ; EXPANDED-NEXT: $vgpr0_hi16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.1, addrspace 5) + ; EXPANDED-NEXT: $vgpr0_lo16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.0, addrspace 5) + ; EXPANDED-NEXT: $vgpr0_hi16 = SCRATCH_LOAD_SHORT_D16_SADDR_t16 $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.1, addrspace 5) ; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_lo16, implicit killed renamable $vgpr0_hi16 ; ; SRAMECC-EXPANDED-LABEL: name: spill_restore_vgpr16 @@ -53,8 +53,8 @@ body: | ; SRAMECC-EXPANDED-NEXT: successors: %bb.1(0x80000000) ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_lo16, implicit-def renamable $vgpr0_hi16 - ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.1, addrspace 5) - ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_hi16, $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.1, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: SCRATCH_STORE_SHORT_SADDR_t16 killed $vgpr0_lo16, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s16) into %stack.0, addrspace 5) ; SRAMECC-EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: bb.1: @@ -63,9 +63,9 @@ body: | ; SRAMECC-EXPANDED-NEXT: S_NOP 1 ; SRAMECC-EXPANDED-NEXT: {{ $}} ; SRAMECC-EXPANDED-NEXT: bb.2: - ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.0, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.0, addrspace 5) ; SRAMECC-EXPANDED-NEXT: $vgpr0_lo16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec - ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: (load (s16) from %stack.1, addrspace 5) + ; SRAMECC-EXPANDED-NEXT: $vgpr1 = SCRATCH_LOAD_USHORT_SADDR $sgpr32, 2, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s16) from %stack.1, addrspace 5) ; SRAMECC-EXPANDED-NEXT: $vgpr0_hi16 = V_MOV_B16_t16_e64 0, killed $vgpr1_lo16, 0, implicit $exec ; SRAMECC-EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_lo16, implicit killed renamable $vgpr0_hi16 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir b/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir index cc261b0da4a8f..ca19f7e0a55cd 100644 --- a/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir +++ b/llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir @@ -20,13 +20,13 @@ body: | ; GCN: liveins: $sgpr20, $vgpr1 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF ; GCN-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr0 ; GCN-NEXT: $vgpr0 = COPY killed renamable $vgpr1, implicit $exec ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $vgpr0(tied-def 0) :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $vgpr0(tied-def 0) :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: SI_RETURN implicit $vgpr0 $vgpr0 = IMPLICIT_DEF @@ -53,8 +53,8 @@ body: | ; GCN: liveins: $sgpr20, $sgpr21, $vgpr1 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: $vgpr0 = IMPLICIT_DEF ; GCN-NEXT: $vgpr2 = IMPLICIT_DEF @@ -62,8 +62,8 @@ body: | ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR killed $sgpr21, 0, $vgpr2 ; GCN-NEXT: $vgpr0 = COPY $vgpr1, implicit $exec ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $vgpr0(tied-def 0) :: (load (s32) from %stack.0, addrspace 5) - ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; GCN-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit $vgpr0(tied-def 0) :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: SI_RETURN implicit $vgpr0_vgpr1 $vgpr0 = IMPLICIT_DEF @@ -92,13 +92,13 @@ body: | ; GCN: liveins: $sgpr20, $vgpr1 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: $vgpr2 = IMPLICIT_DEF ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr2 ; GCN-NEXT: $vgpr0 = COPY $vgpr1, implicit $exec ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: SI_RETURN implicit $vgpr0_vgpr1 $vgpr2 = IMPLICIT_DEF @@ -124,14 +124,14 @@ body: | ; GCN: liveins: $sgpr20, $vgpr1 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: $vgpr2 = IMPLICIT_DEF ; GCN-NEXT: $vgpr2 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr2 ; GCN-NEXT: $sgpr20 = SI_RESTORE_S32_FROM_VGPR $vgpr2, 0, implicit $exec ; GCN-NEXT: $vgpr0 = COPY killed $vgpr1, implicit $exec ; GCN-NEXT: $sgpr4_sgpr5 = S_XOR_SAVEEXEC_B64 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: $exec = S_MOV_B64 killed $sgpr4_sgpr5 ; GCN-NEXT: SI_RETURN implicit $vgpr0 $vgpr40 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll b/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll index 0cf26be3ac24f..77d62a3a9a8cd 100644 --- a/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll +++ b/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll @@ -105,7 +105,7 @@ define amdgpu_ps { <4 x float> } @test_return_to_epilog_with_optimized_kill(floa ; GCN-NEXT: {{ $}} ; GCN-NEXT: renamable $vgpr1 = nofpexcept V_RCP_F32_e32 $vgpr0, implicit $mode, implicit $exec ; GCN-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec - ; GCN-NEXT: nofpexcept V_CMP_NGT_F32_e32 0, killed $vgpr1, implicit-def $vcc, implicit $mode, implicit $exec + ; GCN-NEXT: nofpexcept V_CMP_LE_F32_e32 0, killed $vgpr1, implicit-def $vcc, implicit $mode, implicit $exec ; GCN-NEXT: $sgpr2_sgpr3 = S_AND_SAVEEXEC_B64 killed $vcc, implicit-def $exec, implicit-def $scc, implicit $exec ; GCN-NEXT: renamable $sgpr2_sgpr3 = S_XOR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def dead $scc ; GCN-NEXT: S_CBRANCH_EXECNZ %bb.3, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/udivrem24.ll b/llvm/test/CodeGen/AMDGPU/udivrem24.ll index 1e5ec59456a26..935a9bf23c9cb 100644 --- a/llvm/test/CodeGen/AMDGPU/udivrem24.ll +++ b/llvm/test/CodeGen/AMDGPU/udivrem24.ll @@ -2077,6 +2077,6 @@ define amdgpu_kernel void @test_udiv24_u23_u16_i32(ptr addrspace(1) %out, ptr ad ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="ieee,preserve-sign" } -attributes #2 = { "denormal-fp-math-f32"="preserve-sign,ieee" } +attributes #0 = { denormal_fpenv(float: preservesign) } +attributes #1 = { denormal_fpenv(float: ieee|preservesign) } +attributes #2 = { denormal_fpenv(float: preservesign|ieee) } diff --git a/llvm/test/CodeGen/AMDGPU/uitofp.f16.ll b/llvm/test/CodeGen/AMDGPU/uitofp.f16.ll index 8fe5cbeaab34d..901361ff48cee 100644 --- a/llvm/test/CodeGen/AMDGPU/uitofp.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/uitofp.f16.ll @@ -53,7 +53,7 @@ define amdgpu_kernel void @uitofp_i16_to_f16( ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s3 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[8:11], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l diff --git a/llvm/test/CodeGen/AMDGPU/v_mac.ll b/llvm/test/CodeGen/AMDGPU/v_mac.ll index d987e7c65e692..4658332ac395d 100644 --- a/llvm/test/CodeGen/AMDGPU/v_mac.ll +++ b/llvm/test/CodeGen/AMDGPU/v_mac.ll @@ -291,7 +291,7 @@ bb: ; GCN-LABEL: {{^}}v_mac_f32_dynamic: ; GCN: v_mul_f32 ; GCN: v_add_f32 -define float @v_mac_f32_dynamic(float %a, float %b, float %c) "denormal-fp-math-f32"="dynamic,dynamic" { +define float @v_mac_f32_dynamic(float %a, float %b, float %c) denormal_fpenv(float: dynamic|dynamic) { %mul = fmul float %a, %b %mad = fadd float %mul, %c ret float %mad @@ -300,7 +300,7 @@ define float @v_mac_f32_dynamic(float %a, float %b, float %c) "denormal-fp-math- ; GCN-LABEL: {{^}}v_mac_f32_dynamic_daz: ; GCN: v_mul_f32 ; GCN: v_add_f32 -define float @v_mac_f32_dynamic_daz(float %a, float %b, float %c) "denormal-fp-math-f32"="preserve-sign,dynamic" { +define float @v_mac_f32_dynamic_daz(float %a, float %b, float %c) denormal_fpenv(float: preservesign|dynamic) { %mul = fmul float %a, %b %mad = fadd float %mul, %c ret float %mad @@ -309,7 +309,7 @@ define float @v_mac_f32_dynamic_daz(float %a, float %b, float %c) "denormal-fp-m ; GCN-LABEL: {{^}}v_mac_f32_dynamic_ftz: ; GCN: v_mul_f32 ; GCN: v_add_f32 -define float @v_mac_f32_dynamic_ftz(float %a, float %b, float %c) "denormal-fp-math-f32"="dynamic,preserve-sign" { +define float @v_mac_f32_dynamic_ftz(float %a, float %b, float %c) denormal_fpenv(float: dynamic|preservesign) { %mul = fmul float %a, %b %mad = fadd float %mul, %c ret float %mad diff --git a/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll b/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll index 34cf771fae45e..8e1a4bf2a2d9f 100644 --- a/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll +++ b/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll @@ -738,6 +738,6 @@ entry: declare void @llvm.amdgcn.s.barrier() #2 -attributes #0 = { nounwind "no-signed-zeros-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind "no-signed-zeros-fp-math"="false" denormal_fpenv(preservesign) } +attributes #1 = { nounwind denormal_fpenv(preservesign) } attributes #2 = { nounwind convergent } diff --git a/llvm/test/CodeGen/AMDGPU/v_madak_f16.ll b/llvm/test/CodeGen/AMDGPU/v_madak_f16.ll index b675e0ffe9eed..2e85301edd3c1 100644 --- a/llvm/test/CodeGen/AMDGPU/v_madak_f16.ll +++ b/llvm/test/CodeGen/AMDGPU/v_madak_f16.ll @@ -70,12 +70,12 @@ define amdgpu_kernel void @madak_f16( ; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s12, s2 ; GFX11-TRUE16-NEXT: s_mov_b32 s13, s3 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[12:15], 0 -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[4:7], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[12:15], 0 +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[4:7], 0 ; GFX11-TRUE16-NEXT: s_mov_b32 s8, s0 ; GFX11-TRUE16-NEXT: s_mov_b32 s9, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v0.h ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 0x4900, v0.l ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], 0 @@ -216,22 +216,22 @@ define amdgpu_kernel void @madak_f16_use_2( ; GFX11-TRUE16-NEXT: s_mov_b32 s17, s13 ; GFX11-TRUE16-NEXT: s_mov_b32 s20, s14 ; GFX11-TRUE16-NEXT: s_mov_b32 s21, s15 -; GFX11-TRUE16-NEXT: buffer_load_u16 v0, off, s[16:19], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[16:19], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v1, off, s[20:23], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[20:23], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: buffer_load_u16 v2, off, s[0:3], 0 glc dlc +; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[0:3], 0 glc dlc ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_mov_b32 s4, s8 ; GFX11-TRUE16-NEXT: s_mov_b32 s5, s9 ; GFX11-TRUE16-NEXT: s_mov_b32 s0, s10 ; GFX11-TRUE16-NEXT: s_mov_b32 s1, s11 -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.l, v1.l -; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v2.l +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.h, v0.l, v0.h +; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, v0.l, v1.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.l, 0x4900, v0.h +; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.h, 0x4900, v0.h ; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 0x4900, v0.l -; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[4:7], 0 +; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b16 v0, off, s[4:7], 0 ; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-TRUE16-NEXT: s_endpgm ; @@ -291,6 +291,6 @@ entry: ret void } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(preservesign) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GFX11: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir b/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir index 69cf924548ed8..17730521cbedf 100644 --- a/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir +++ b/llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir @@ -20,9 +20,9 @@ body: | ; GCN: liveins: $vgpr52, $vgpr53, $vgpr54, $vgpr55, $agpr0_agpr1_agpr2_agpr3, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s96) into %stack.0, align 4, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $agpr0_agpr1_agpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $vgpr51 = COPY $vgpr55, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51 - ; GCN-NEXT: $vgpr48_vgpr49_vgpr50 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr48_vgpr49_vgpr50_vgpr51 :: (load (s96) from %stack.0, align 4, addrspace 5) + ; GCN-NEXT: $vgpr48_vgpr49_vgpr50 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr48_vgpr49_vgpr50_vgpr51 :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr52, implicit $vgpr53, implicit $vgpr54, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 SI_SPILL_A128_SAVE killed $agpr0_agpr1_agpr2_agpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $vgpr48_vgpr49_vgpr50_vgpr51 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -46,10 +46,10 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s64) into %stack.0, align 4, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $agpr0_agpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $vgpr51 = COPY $vgpr54, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51 ; GCN-NEXT: $vgpr50 = COPY $vgpr55, implicit $vgpr48_vgpr49_vgpr50_vgpr51 - ; GCN-NEXT: $vgpr48_vgpr49 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr48_vgpr49_vgpr50_vgpr51 :: (load (s64) from %stack.0, align 4, addrspace 5) + ; GCN-NEXT: $vgpr48_vgpr49 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr48_vgpr49_vgpr50_vgpr51 :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr52, implicit $vgpr53, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 SI_SPILL_A128_SAVE killed $agpr0_agpr1_agpr2_agpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $vgpr48_vgpr49_vgpr50_vgpr51 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -74,11 +74,11 @@ body: | ; GCN-NEXT: $vgpr53 = V_ACCVGPR_READ_B32_e64 killed $agpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr54 = V_ACCVGPR_READ_B32_e64 killed $agpr2, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 ; GCN-NEXT: $vgpr55 = V_ACCVGPR_READ_B32_e64 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2_agpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $agpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $agpr0_agpr1_agpr2_agpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $vgpr51 = COPY $vgpr53, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51 ; GCN-NEXT: $vgpr50 = COPY $vgpr54, implicit $vgpr48_vgpr49_vgpr50_vgpr51 ; GCN-NEXT: $vgpr49 = COPY $vgpr55, implicit $vgpr48_vgpr49_vgpr50_vgpr51 - ; GCN-NEXT: $vgpr48 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr48_vgpr49_vgpr50_vgpr51 :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $vgpr48 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr48_vgpr49_vgpr50_vgpr51, implicit $vgpr48_vgpr49_vgpr50_vgpr51 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $vgpr52, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, implicit $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 SI_SPILL_A128_SAVE killed $agpr0_agpr1_agpr2_agpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $vgpr48_vgpr49_vgpr50_vgpr51 = SI_SPILL_V128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -130,9 +130,9 @@ body: | ; GCN: liveins: $agpr30, $agpr31, $agpr24_agpr25, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: {{ $}} ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s96) into %stack.0, align 4, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORDX3_SADDR killed $vgpr0_vgpr1_vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s96) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $agpr29 = COPY $agpr30, implicit-def $agpr26_agpr27_agpr28_agpr29 - ; GCN-NEXT: $agpr26_agpr27_agpr28 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr26_agpr27_agpr28_agpr29, implicit $agpr26_agpr27_agpr28_agpr29 :: (load (s96) from %stack.0, align 4, addrspace 5) + ; GCN-NEXT: $agpr26_agpr27_agpr28 = SCRATCH_LOAD_DWORDX3_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr26_agpr27_agpr28_agpr29, implicit $agpr26_agpr27_agpr28_agpr29 :: ("amdgpu-thread-private" load (s96) from %stack.0, align 4, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $agpr31, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25 SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $agpr26_agpr27_agpr28_agpr29 = SI_SPILL_A128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -156,10 +156,10 @@ body: | ; GCN-NEXT: {{ $}} ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s64) into %stack.0, align 4, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORDX2_SADDR killed $vgpr0_vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s64) into %stack.0, align 4, addrspace 5) ; GCN-NEXT: $agpr29 = COPY $agpr30, implicit-def $agpr26_agpr27_agpr28_agpr29 ; GCN-NEXT: $agpr28 = COPY $agpr31, implicit $agpr26_agpr27_agpr28_agpr29 - ; GCN-NEXT: $agpr26_agpr27 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr26_agpr27_agpr28_agpr29, implicit $agpr26_agpr27_agpr28_agpr29 :: (load (s64) from %stack.0, align 4, addrspace 5) + ; GCN-NEXT: $agpr26_agpr27 = SCRATCH_LOAD_DWORDX2_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr26_agpr27_agpr28_agpr29, implicit $agpr26_agpr27_agpr28_agpr29 :: ("amdgpu-thread-private" load (s64) from %stack.0, align 4, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24_agpr25 SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $agpr26_agpr27_agpr28_agpr29 = SI_SPILL_A128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) @@ -184,11 +184,11 @@ body: | ; GCN-NEXT: $agpr25 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr30 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 ; GCN-NEXT: $agpr31 = V_ACCVGPR_WRITE_B32_e64 killed $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3 - ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) + ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; GCN-NEXT: $agpr29 = COPY $agpr25, implicit-def $agpr26_agpr27_agpr28_agpr29 ; GCN-NEXT: $agpr28 = COPY $agpr30, implicit $agpr26_agpr27_agpr28_agpr29 ; GCN-NEXT: $agpr27 = COPY $agpr31, implicit $agpr26_agpr27_agpr28_agpr29 - ; GCN-NEXT: $agpr26 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr26_agpr27_agpr28_agpr29, implicit $agpr26_agpr27_agpr28_agpr29 :: (load (s32) from %stack.0, addrspace 5) + ; GCN-NEXT: $agpr26 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $agpr26_agpr27_agpr28_agpr29, implicit $agpr26_agpr27_agpr28_agpr29 :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; GCN-NEXT: S_ENDPGM 0, implicit $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, implicit $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, implicit $agpr24 SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) $agpr26_agpr27_agpr28_agpr29 = SI_SPILL_A128_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.0, align 4, addrspace 5) diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir index 572a875941b22..d0a57cece191c 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir +++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir @@ -28,7 +28,7 @@ body: | ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -47,7 +47,7 @@ body: | ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -65,7 +65,7 @@ body: | ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -83,7 +83,7 @@ body: | ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -127,8 +127,8 @@ body: | ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -147,7 +147,7 @@ body: | ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e32 8200, $vgpr2, implicit $exec - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.1, align 4, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.1, align 4, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -165,7 +165,7 @@ body: | ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.1, align 4, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.1, align 4, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -183,8 +183,8 @@ body: | ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1 + 4, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -226,7 +226,7 @@ body: | ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -244,7 +244,7 @@ body: | ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec - ; GFX9-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -261,7 +261,7 @@ body: | ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -278,7 +278,7 @@ body: | ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -320,8 +320,8 @@ body: | ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; MUBUF-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.1, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -339,7 +339,7 @@ body: | ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e32 8200, $vgpr2, implicit $exec - ; GFX9-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.1, align 4, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.1, align 4, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -356,7 +356,7 @@ body: | ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.1, align 4, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.1, align 4, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -373,8 +373,8 @@ body: | ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc ; VMEM-GFX8-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -416,10 +416,10 @@ body: | ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -437,11 +437,11 @@ body: | ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec - ; GFX9-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) - ; GFX9-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -459,10 +459,10 @@ body: | ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) - ; GFX10-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -480,10 +480,10 @@ body: | ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -528,11 +528,11 @@ body: | ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.1, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -550,11 +550,11 @@ body: | ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e32 8200, $vgpr2, implicit $exec - ; GFX9-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.1, align 4, addrspace 5) - ; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.1, align 4, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -572,10 +572,10 @@ body: | ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (load (s64) from %stack.1, align 4, addrspace 5) - ; GFX10-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr0_vgpr1 = SCRATCH_LOAD_DWORDX2 killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s64) from %stack.1, align 4, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -593,11 +593,11 @@ body: | ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: (load (s32) from %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -642,12 +642,12 @@ body: | ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr3 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: (load (s32) from %stack.1, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -665,11 +665,11 @@ body: | ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr3 = V_ADD_U32_e32 8200, $vgpr3, implicit $exec - ; GFX9-FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3 killed $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.1, align 4, addrspace 5) - ; GFX9-FLATSCR-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3 killed $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.1, align 4, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -687,10 +687,10 @@ body: | ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr3 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3 killed $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: (load (s96) from %stack.1, align 4, addrspace 5) - ; GFX10-FLATSCR-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr0_vgpr1_vgpr2 = SCRATCH_LOAD_DWORDX3 killed $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s96) from %stack.1, align 4, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -708,12 +708,12 @@ body: | ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr3 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: (load (s32) from %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 4, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (load (s32) from %stack.1 + 8, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 4, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.1 + 8, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -758,10 +758,10 @@ body: | ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -779,11 +779,11 @@ body: | ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e32 8200, $vgpr1, implicit $exec - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; GFX9-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -801,10 +801,10 @@ body: | ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr1 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; GFX10-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD $vgpr0, killed $vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -822,10 +822,10 @@ body: | ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -870,11 +870,11 @@ body: | ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1 + 4, addrspace 5) - ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; MUBUF-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -892,11 +892,11 @@ body: | ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e32 8200, $vgpr2, implicit $exec - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.1, align 4, addrspace 5) - ; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.1, align 4, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -914,10 +914,10 @@ body: | ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr2, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr2 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: (store (s64) into %stack.1, align 4, addrspace 5) - ; GFX10-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORDX2 $vgpr0_vgpr1, killed $vgpr2, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s64) into %stack.1, align 4, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -935,11 +935,11 @@ body: | ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr2 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.1 + 4, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -984,12 +984,12 @@ body: | ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr3 = V_MOV_B32_e32 8200, implicit $exec - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.1, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.1 + 4, addrspace 5) - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr2, killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.1 + 8, addrspace 5) - ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr2, killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 8, addrspace 5) + ; MUBUF-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -1007,11 +1007,11 @@ body: | ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $vgpr3 = V_MOV_B32_e32 $sgpr32, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr3 = V_ADD_U32_e32 8200, $vgpr3, implicit $exec - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORDX3 $vgpr0_vgpr1_vgpr2, killed $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.1, align 4, addrspace 5) - ; GFX9-FLATSCR-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORDX3 $vgpr0_vgpr1_vgpr2, killed $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.1, align 4, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -1029,10 +1029,10 @@ body: | ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $vgpr3 = V_ADD_U32_e64 $sgpr32, 8200, 0, implicit $exec - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORDX3 $vgpr0_vgpr1_vgpr2, killed $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: (store (s96) into %stack.1, align 4, addrspace 5) - ; GFX10-FLATSCR-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORDX3 $vgpr0_vgpr1_vgpr2, killed $vgpr3, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s96) into %stack.1, align 4, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -1050,12 +1050,12 @@ body: | ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr3 = V_MOV_B32_e32 8200, implicit $exec - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.1 + 4, addrspace 5) - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr2, killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 :: (store (s32) into %stack.1 + 8, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr0, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr1, $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.1 + 4, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFEN $vgpr2, killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2 :: ("amdgpu-thread-private" store (s32) into %stack.1 + 8, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: @@ -1203,10 +1203,10 @@ body: | ; MUBUF-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; MUBUF-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; MUBUF-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; MUBUF-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) - ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; MUBUF-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; MUBUF-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; MUBUF-NEXT: {{ $}} ; MUBUF-NEXT: bb.1: @@ -1224,13 +1224,13 @@ body: | ; GFX9-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: $sgpr4 = S_ADDC_U32 $sgpr32, 8200, implicit-def $scc, implicit $scc ; GFX9-FLATSCR-NEXT: S_BITCMP1_B32 $sgpr4, 0, implicit-def $scc ; GFX9-FLATSCR-NEXT: $sgpr4 = S_BITSET0_B32 0, $sgpr4 ; GFX9-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr4, implicit $exec ; GFX9-FLATSCR-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) - ; GFX9-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX9-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX9-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX9-FLATSCR-NEXT: {{ $}} ; GFX9-FLATSCR-NEXT: bb.1: @@ -1248,13 +1248,13 @@ body: | ; GFX10-FLATSCR-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr1, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: $sgpr4 = S_ADDC_U32 $sgpr32, 8200, implicit-def $scc, implicit $scc ; GFX10-FLATSCR-NEXT: S_BITCMP1_B32 $sgpr4, 0, implicit-def $scc ; GFX10-FLATSCR-NEXT: $sgpr4 = S_BITSET0_B32 0, $sgpr4 ; GFX10-FLATSCR-NEXT: $vgpr1 = V_MOV_B32_e32 killed $sgpr4, implicit $exec ; GFX10-FLATSCR-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) - ; GFX10-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; GFX10-FLATSCR-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; GFX10-FLATSCR-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; GFX10-FLATSCR-NEXT: {{ $}} ; GFX10-FLATSCR-NEXT: bb.1: @@ -1272,10 +1272,10 @@ body: | ; VMEM-GFX8-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251, $vgpr252_vgpr253_vgpr254_vgpr255 ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: S_CMP_EQ_U32 0, 0, implicit-def $scc - ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: $vgpr1 = V_MOV_B32_e32 8200, implicit $exec ; VMEM-GFX8-NEXT: $vgpr0 = BUFFER_LOAD_DWORD_OFFEN killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5) - ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) + ; VMEM-GFX8-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; VMEM-GFX8-NEXT: S_CBRANCH_SCC1 %bb.2, implicit $scc ; VMEM-GFX8-NEXT: {{ $}} ; VMEM-GFX8-NEXT: bb.1: diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir b/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir index edea344a66a3c..93fc2857d5092 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir +++ b/llvm/test/CodeGen/AMDGPU/vgpr-spill.mir @@ -17,7 +17,7 @@ body: | ; CHECK-LABEL: name: spill_v32 ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit $vgpr0 SI_SPILL_V32_SAVE $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) S_NOP 0, implicit $vgpr0 @@ -39,7 +39,7 @@ body: | ; CHECK-LABEL: name: spill_v32_kill ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.0, addrspace 5) ... @@ -59,8 +59,8 @@ body: | ; CHECK-LABEL: name: spill_v64 ; CHECK: liveins: $vgpr0_vgpr1 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) ; CHECK-NEXT: S_NOP 0, implicit $vgpr0_vgpr1 SI_SPILL_V64_SAVE $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) S_NOP 0, implicit $vgpr0_vgpr1 @@ -82,8 +82,8 @@ body: | ; CHECK-LABEL: name: spill_v64_kill ; CHECK: liveins: $vgpr0_vgpr1 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) ... @@ -105,8 +105,8 @@ body: | ; CHECK-LABEL: name: spill_v64_undef_sub1_killed ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) ... @@ -126,8 +126,8 @@ body: | ; CHECK-LABEL: name: spill_v64_undef_sub0_killed ; CHECK: liveins: $vgpr1 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: (store (s32) into %stack.0 + 4, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, addrspace 5) ... @@ -147,10 +147,10 @@ body: | ; CHECK-LABEL: name: spill_v128_kill ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 4, addrspace 5) - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: (store (s32) into %stack.0 + 8, addrspace 5) - ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: (store (s32) into %stack.0 + 12, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 4, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 8, 0, 0, implicit $exec :: ("amdgpu-thread-private" store (s32) into %stack.0 + 8, addrspace 5) + ; CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET killed $vgpr3, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 12, 0, 0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3 :: ("amdgpu-thread-private" store (s32) into %stack.0 + 12, addrspace 5) SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.0, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.0, addrspace 5) ... diff --git a/llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll b/llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll index e3adf737d6e5c..ca43fcc4d2cd0 100644 --- a/llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll +++ b/llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll @@ -891,7 +891,7 @@ define amdgpu_kernel void @atomic_rmw_across_basic_blocks(ptr addrspace(1) %ptr, ; GFX1250-NEXT: v_writelane_b32 v2, s4, 0 ; GFX1250-NEXT: v_writelane_b32 v2, s5, 1 ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_store_b32 off, v2, off ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v2, off nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: v_mov_b32_e32 v0, 0 @@ -921,7 +921,7 @@ define amdgpu_kernel void @atomic_rmw_across_basic_blocks(ptr addrspace(1) %ptr, ; GFX1250-NEXT: s_cbranch_scc1 .LBB16_2 ; GFX1250-NEXT: ; %bb.1: ; %then ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_load_b32 v2, off, off ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v2, off, off nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_wait_loadcnt 0x0 @@ -973,13 +973,13 @@ define amdgpu_kernel void @atomic_rmw_in_loop(ptr addrspace(1) %ptr, i32 %n) { ; GFX1250-NEXT: v_writelane_b32 v2, s1, 2 ; GFX1250-NEXT: v_writelane_b32 v2, s0, 3 ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_store_b32 off, v2, off ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v2, off nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: .LBB17_1: ; %loop ; GFX1250-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_load_b32 v2, off, off ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v2, off, off nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_wait_loadcnt 0x0 @@ -1015,7 +1015,7 @@ define amdgpu_kernel void @atomic_rmw_in_loop(ptr addrspace(1) %ptr, i32 %n) { ; GFX1250-NEXT: v_writelane_b32 v2, s0, 3 ; GFX1250-NEXT: s_mov_b32 s6, exec_lo ; GFX1250-NEXT: s_mov_b32 exec_lo, -1 -; GFX1250-NEXT: scratch_store_b32 off, v2, off ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v2, off nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_cbranch_scc1 .LBB17_1 @@ -1078,13 +1078,13 @@ define amdgpu_kernel void @atomic_rmw_with_branch(ptr addrspace(1) %ptr, i32 %co ; GFX1250-NEXT: v_writelane_b32 v2, s0, 2 ; GFX1250-NEXT: s_mov_b32 s6, exec_lo ; GFX1250-NEXT: s_mov_b32 exec_lo, -1 -; GFX1250-NEXT: scratch_store_b32 off, v2, off ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v2, off nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_cbranch_scc1 .LBB18_3 ; GFX1250-NEXT: .LBB18_1: ; %Flow ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_load_b32 v2, off, off ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v2, off, off nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_wait_loadcnt 0x0 @@ -1096,7 +1096,7 @@ define amdgpu_kernel void @atomic_rmw_with_branch(ptr addrspace(1) %ptr, i32 %co ; GFX1250-NEXT: s_cbranch_vccnz .LBB18_4 ; GFX1250-NEXT: ; %bb.2: ; %bb1 ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_load_b32 v2, off, off ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v2, off, off nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_wait_loadcnt 0x0 @@ -1117,7 +1117,7 @@ define amdgpu_kernel void @atomic_rmw_with_branch(ptr addrspace(1) %ptr, i32 %co ; GFX1250-NEXT: s_branch .LBB18_4 ; GFX1250-NEXT: .LBB18_3: ; %bb2 ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_load_b32 v2, off, off ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v2, off, off nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_wait_loadcnt 0x0 @@ -1138,13 +1138,13 @@ define amdgpu_kernel void @atomic_rmw_with_branch(ptr addrspace(1) %ptr, i32 %co ; GFX1250-NEXT: s_mov_b32 s0, 0 ; GFX1250-NEXT: v_writelane_b32 v2, s0, 2 ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_store_b32 off, v2, off ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v2, off nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_branch .LBB18_1 ; GFX1250-NEXT: .LBB18_4: ; %merge ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_load_b32 v2, off, off ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v2, off, off nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_wait_loadcnt 0x0 @@ -1199,7 +1199,7 @@ define amdgpu_kernel void @atomic_rmw_fallthrough(ptr addrspace(1) %ptr) { ; GFX1250-NEXT: v_writelane_b32 v2, s2, 0 ; GFX1250-NEXT: v_writelane_b32 v2, s3, 1 ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_store_b32 off, v2, off ; 4-byte Folded Spill +; GFX1250-NEXT: scratch_store_b32 off, v2, off nv ; 4-byte Folded Spill ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: v_mov_b32_e32 v0, 0 @@ -1226,7 +1226,7 @@ define amdgpu_kernel void @atomic_rmw_fallthrough(ptr addrspace(1) %ptr) { ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: ; %bb.1: ; %next ; GFX1250-NEXT: s_or_saveexec_b32 s6, -1 -; GFX1250-NEXT: scratch_load_b32 v2, off, off ; 4-byte Folded Reload +; GFX1250-NEXT: scratch_load_b32 v2, off, off nv ; 4-byte Folded Reload ; GFX1250-NEXT: s_wait_xcnt 0x0 ; GFX1250-NEXT: s_mov_b32 exec_lo, s6 ; GFX1250-NEXT: s_wait_loadcnt 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll b/llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll index a00aca34252b1..74fddfe290818 100644 --- a/llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-unscoped.ll @@ -11,15 +11,14 @@ define amdgpu_kernel void @test_waitcnt(ptr addrspace(1) %global_buffer, ptr add ; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_load_dword s6, s[0:1], 0x0 ; CHECK-NEXT: s_add_u32 s4, s0, 64 ; CHECK-NEXT: s_addc_u32 s5, s1, 0 ; CHECK-NEXT: s_mov_b32 m0, s2 -; CHECK-NEXT: s_nop 0 -; CHECK-NEXT: global_load_lds_dword v0, s[4:5] offset:4 -; CHECK-NEXT: s_load_dword s4, s[0:1], 0x0 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: v_mov_b32_e32 v3, s4 +; CHECK-NEXT: v_mov_b32_e32 v3, s6 ; CHECK-NEXT: global_store_dword v0, v3, s[0:1] offset:64 +; CHECK-NEXT: global_load_lds_dword v0, s[4:5] offset:4 ; CHECK-NEXT: ; sched_barrier mask(0x00000000) ; CHECK-NEXT: v_mov_b32_e32 v1, s2 ; CHECK-NEXT: v_mov_b32_e32 v2, s3 diff --git a/llvm/test/CodeGen/AMDGPU/waitcnt-wbl2.ll b/llvm/test/CodeGen/AMDGPU/waitcnt-wbl2.ll new file mode 100644 index 0000000000000..912b267d6ee7f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/waitcnt-wbl2.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck -check-prefixes=GFX950 %s + +; Test that vmcnt(0) is correctly preserved between buffer_wbl2 and atomic +; when there are global memory stores that need to be written back. + +define void @global_store_different_block(ptr addrspace(1) %data_ptr, ptr addrspace(1) %atomic_ptr, i1 %cond) { +; GFX950-LABEL: global_store_different_block: +; GFX950: ; %bb.0: ; %entry +; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX950-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4 +; GFX950-NEXT: v_mov_b32_e32 v4, 42 +; GFX950-NEXT: global_store_dword v[0:1], v4, off +; GFX950-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX950-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX950-NEXT: s_cbranch_execz .LBB0_2 +; GFX950-NEXT: ; %bb.1: ; %do_atomic +; GFX950-NEXT: v_mov_b64_e32 v[0:1], 0 +; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) +; GFX950-NEXT: global_atomic_swap_x2 v[2:3], v[0:1], off +; GFX950-NEXT: .LBB0_2: ; %exit +; GFX950-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX950-NEXT: s_waitcnt vmcnt(0) +; GFX950-NEXT: s_setpc_b64 s[30:31] +entry: + ; Global store in entry block + store i32 42, ptr addrspace(1) %data_ptr, align 4 + call void @llvm.amdgcn.s.waitcnt(i32 112) + br i1 %cond, label %do_atomic, label %exit + +do_atomic: + %old = atomicrmw xchg ptr addrspace(1) %atomic_ptr, i64 0 syncscope("agent") release + br label %exit + +exit: + ret void +} + +define void @global_store_then_atomic(ptr addrspace(1) %data_ptr, ptr addrspace(1) %atomic_ptr) { +; GFX950-LABEL: global_store_then_atomic: +; GFX950: ; %bb.0: ; %entry +; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX950-NEXT: v_mov_b32_e32 v4, 42 +; GFX950-NEXT: global_store_dword v[0:1], v4, off +; GFX950-NEXT: v_mov_b64_e32 v[0:1], 0 +; GFX950-NEXT: buffer_wbl2 sc1 +; GFX950-NEXT: s_waitcnt vmcnt(0) +; GFX950-NEXT: global_atomic_swap_x2 v[2:3], v[0:1], off +; GFX950-NEXT: s_waitcnt vmcnt(0) +; GFX950-NEXT: s_setpc_b64 s[30:31] +entry: + store i32 42, ptr addrspace(1) %data_ptr, align 4 + %old = atomicrmw xchg ptr addrspace(1) %atomic_ptr, i64 0 syncscope("agent") release + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir b/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir index adba762235d8c..25bff3f693f21 100644 --- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir +++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir @@ -24,14 +24,14 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: save_inactive_lanes_non_csr_vgpr - ; CHECK: liveins: $vgpr0 + ; CHECK: liveins: $vgpr0, $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 14, implicit $exec ; CHECK-NEXT: $exec_lo = S_XOR_B32 $sgpr0, -1, implicit-def $scc - ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0(tied-def 0) :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0(tied-def 0) :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $sgpr0 ; CHECK-NEXT: SI_RETURN implicit killed $vgpr0 renamable $sgpr0 = SI_WHOLE_WAVE_FUNC_SETUP implicit-def dead $exec, implicit $exec @@ -65,9 +65,9 @@ body: | ; CHECK: liveins: $vgpr40 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr0 = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr40 = V_MOV_B32_e32 14, implicit $exec - ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $sgpr0 ; CHECK-NEXT: SI_RETURN renamable $sgpr0 = SI_WHOLE_WAVE_FUNC_SETUP implicit-def dead $exec, implicit $exec @@ -102,13 +102,13 @@ body: | ; CHECK: liveins: $sgpr20, $vgpr191, $vgpr192 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vcc_lo = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr192, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr192, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: $vgpr192 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr192 ; CHECK-NEXT: $sgpr20 = S_MOV_B32 14, implicit $exec ; CHECK-NEXT: $sgpr20 = SI_RESTORE_S32_FROM_VGPR $vgpr192, 0 ; CHECK-NEXT: $exec_lo = S_XOR_B32 $vcc_lo, -1, implicit-def $scc - ; CHECK-NEXT: $vgpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr192 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $vcc_lo ; CHECK-NEXT: SI_RETURN $vgpr192 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr192 @@ -145,11 +145,11 @@ body: | ; CHECK: liveins: $sgpr20, $vgpr191 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vcc_lo = S_OR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr191, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr191, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) ; CHECK-NEXT: $vgpr191 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr191 ; CHECK-NEXT: $sgpr20 = S_MOV_B32 14, implicit $exec ; CHECK-NEXT: $sgpr20 = SI_RESTORE_S32_FROM_VGPR $vgpr191, 0 - ; CHECK-NEXT: $vgpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr191 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $vcc_lo ; CHECK-NEXT: SI_RETURN $vgpr191 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr191 @@ -191,21 +191,21 @@ body: | liveins: $sgpr20, $vgpr0, $vgpr1, $vgpr191 ; CHECK-LABEL: name: vgpr_and_sgpr_csr - ; CHECK: liveins: $sgpr20, $vgpr0, $vgpr1, $vgpr40, $vgpr49 + ; CHECK: liveins: $sgpr20, $vgpr0, $vgpr1, $vgpr40, $vgpr49, $vgpr49 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vcc_lo = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr49, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr49, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; CHECK-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr0 ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $sgpr20 ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr49, implicit-def $sgpr40 ; CHECK-NEXT: $sgpr20 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0 - ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; CHECK-NEXT: $exec_lo = S_XOR_B32 $vcc_lo, -1, implicit-def $scc - ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) - ; CHECK-NEXT: $vgpr49 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr49 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $vcc_lo ; CHECK-NEXT: SI_RETURN $vgpr191 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr191 @@ -248,22 +248,22 @@ body: | liveins: $sgpr20, $vgpr0, $vgpr1, $vgpr191 ; CHECK-LABEL: name: split_orig_exec - ; CHECK: liveins: $sgpr20, $vgpr0, $vgpr1, $vgpr40, $vgpr49 + ; CHECK: liveins: $sgpr20, $vgpr0, $vgpr1, $vgpr40, $vgpr49, $vgpr49 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vcc_lo = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr49, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr49, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; CHECK-NEXT: $vgpr0 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr0 ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr40, implicit-def $sgpr20 ; CHECK-NEXT: $sgpr3 = COPY $vcc_lo ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr49, implicit-def $sgpr40 ; CHECK-NEXT: $sgpr20 = SI_RESTORE_S32_FROM_VGPR $vgpr0, 0 - ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; CHECK-NEXT: $exec_lo = S_XOR_B32 $sgpr3, -1, implicit-def $scc - ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.0, addrspace 5) - ; CHECK-NEXT: $vgpr49 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr49 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $sgpr3 ; CHECK-NEXT: SI_RETURN $vgpr191 = SI_SPILL_S32_TO_VGPR killed $sgpr20, 0, $vgpr191 @@ -298,29 +298,29 @@ machineFunctionInfo: body: | bb.0: ; CHECK-LABEL: name: vgpr_superregs - ; CHECK: liveins: $vgpr0, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr40, $vgpr41, $vgpr42 + ; CHECK: liveins: $vgpr0, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr40, $vgpr41, $vgpr42, $vgpr0, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $sgpr0 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr2, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr3, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.2, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr4, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.3, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.4, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr2, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr3, $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.2, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr4, $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.3, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr5, $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.4, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.5, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr41, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.6, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr42, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.7, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr40, $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.5, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr41, $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.6, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr42, $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.7, addrspace 5) ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 14, implicit $exec ; CHECK-NEXT: S_NOP 0, implicit-def $vgpr2_vgpr3_vgpr4_vgpr5, implicit-def $vgpr40_vgpr41_vgpr42 - ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.5, addrspace 5) - ; CHECK-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.6, addrspace 5) - ; CHECK-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.7, addrspace 5) + ; CHECK-NEXT: $vgpr40 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 20, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.5, addrspace 5) + ; CHECK-NEXT: $vgpr41 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 24, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.6, addrspace 5) + ; CHECK-NEXT: $vgpr42 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 28, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.7, addrspace 5) ; CHECK-NEXT: $exec_lo = S_XOR_B32 $sgpr0, -1, implicit-def $scc - ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0(tied-def 0) :: (load (s32) from %stack.0, addrspace 5) - ; CHECK-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) - ; CHECK-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.2, addrspace 5) - ; CHECK-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.3, addrspace 5) - ; CHECK-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.4, addrspace 5) + ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0(tied-def 0) :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) + ; CHECK-NEXT: $vgpr3 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 8, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.2, addrspace 5) + ; CHECK-NEXT: $vgpr4 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 12, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.3, addrspace 5) + ; CHECK-NEXT: $vgpr5 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 16, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.4, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $sgpr0 ; CHECK-NEXT: SI_RETURN implicit killed $vgpr0 renamable $sgpr0 = SI_WHOLE_WAVE_FUNC_SETUP implicit-def dead $exec, implicit $exec @@ -396,11 +396,11 @@ body: | ; CHECK-LABEL: name: multiple_blocks ; CHECK: bb.0: ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) - ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $vcc_lo = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.0, addrspace 5) - ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr1, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.1, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr0, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.0, addrspace 5) + ; CHECK-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr1, $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" store (s32) into %stack.1, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 -1 ; CHECK-NEXT: $sgpr1 = S_MOV_B32 $exec_lo ; CHECK-NEXT: V_CMPX_EQ_U32_nosdst_e64 $vgpr0, $vgpr1, implicit-def $exec, implicit $exec @@ -419,8 +419,8 @@ body: | ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, killed renamable $sgpr1, implicit-def $scc ; CHECK-NEXT: renamable $vgpr0 = V_CNDMASK_B32_e64 0, $vgpr1, 0, $vgpr0, $vcc_lo, implicit $exec ; CHECK-NEXT: $exec_lo = S_XOR_B32 $vcc_lo, -1, implicit-def $scc - ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0(tied-def 0) :: (load (s32) from %stack.0, addrspace 5) - ; CHECK-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.1, addrspace 5) + ; CHECK-NEXT: $vgpr0 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0(tied-def 0) :: ("amdgpu-thread-private" load (s32) from %stack.0, addrspace 5) + ; CHECK-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr32, 4, 0, implicit $exec, implicit $flat_scr :: ("amdgpu-thread-private" load (s32) from %stack.1, addrspace 5) ; CHECK-NEXT: $exec_lo = S_MOV_B32 $vcc_lo ; CHECK-NEXT: SI_RETURN implicit $vgpr0 bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll index c4f8e332a429c..37105efa3333c 100644 --- a/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll +++ b/llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll @@ -114,8 +114,8 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: v_dual_cndmask_b32 v0, 5, v0 :: v_dual_cndmask_b32 v1, 3, v1 @@ -123,8 +123,8 @@ define amdgpu_gfx_whole_wave i32 @basic_test(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, vcc_lo ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -239,8 +239,8 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 % ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: v_cndmask_b32_e32 v1, 17, v1, vcc_lo @@ -248,8 +248,8 @@ define amdgpu_gfx_whole_wave i32 @single_use_of_active(i1 %active, i32 %a, i32 % ; GFX1250-DAGISEL-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, vcc_lo ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -338,12 +338,12 @@ define amdgpu_gfx_whole_wave i32 @unused_active(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 ; 4-byte Folded Spill +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 nv ; 4-byte Folded Spill ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v0, 14 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 nv ; 4-byte Folded Reload ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -518,13 +518,13 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3 ; 16-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:16 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 ; 4-byte Folded Spill +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 offset:12 nv ; 4-byte Folded Spill ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: ;;#ASMSTART ; GFX1250-DAGISEL-NEXT: ; clobber CSR @@ -533,7 +533,7 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: ;;#ASMSTART ; GFX1250-DAGISEL-NEXT: ; clobber non-CSR ; GFX1250-DAGISEL-NEXT: ;;#ASMEND -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s32 offset:12 ; 4-byte Folded Reload +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s32 offset:12 nv ; 4-byte Folded Reload ; GFX1250-DAGISEL-NEXT: v_dual_cndmask_b32 v0, 5, v0 :: v_dual_cndmask_b32 v1, 3, v1 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s20, v2, 0 ; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) @@ -541,10 +541,10 @@ define amdgpu_gfx_whole_wave i32 @csr(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3 ; 16-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49, off, s32 offset:16 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49, off, s32 offset:16 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, vcc_lo ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -636,12 +636,12 @@ define amdgpu_gfx_whole_wave void @csr_vgpr_only(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_or_saveexec_b32 s0, -1 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s32 nv ; 4-byte Folded Spill ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: ;;#ASMSTART ; GFX1250-DAGISEL-NEXT: ; clobber CSR VGPR ; GFX1250-DAGISEL-NEXT: ;;#ASMEND -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s32 nv ; 4-byte Folded Reload ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -748,7 +748,7 @@ define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 ; 4-byte Folded Spill +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 nv ; 4-byte Folded Spill ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v0, s68, 0 @@ -758,7 +758,7 @@ define amdgpu_gfx_whole_wave void @sgpr_spill_only(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s68, v0, 0 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 ; 4-byte Folded Reload +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 nv ; 4-byte Folded Reload ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -1024,8 +1024,8 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) @@ -1039,8 +1039,8 @@ define amdgpu_gfx_whole_wave i32 @multiple_blocks(i1 %active, i32 %a, i32 %b) { ; GFX1250-DAGISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x1 ; 8-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, vcc_lo ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -1189,10 +1189,10 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3 ; 16-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 5, v0 @@ -1202,10 +1202,10 @@ define amdgpu_gfx_whole_wave i64 @ret_64(i1 %active, i64 %a, i64 %b) { ; GFX1250-DAGISEL-NEXT: v_mov_b32_dpp v1, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, vcc_lo, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3 ; 16-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s32 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s32 offset:12 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s32 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s32 offset:12 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, vcc_lo ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -1382,12 +1382,12 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x5 ; 24-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s9 @@ -1400,12 +1400,12 @@ define amdgpu_gfx_whole_wave void @inreg_args(i1 %active, i32 inreg %i32, <4 x i ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x5 ; 24-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s32 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s32 offset:12 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4, off, s32 offset:16 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5, off, s32 offset:20 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s32 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s32 offset:12 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4, off, s32 offset:16 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5, off, s32 offset:20 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-DAGISEL-NEXT: s_wait_loadcnt 0x0 @@ -2775,939 +2775,939 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ; GFX1250-DAGISEL-NEXT: s_mov_b32 s33, s32 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:252 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:252 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:504 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:504 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:576 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 4 ; msbs: dst=0 src0=0 src1=1 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:752 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:756 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:752 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:756 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:760 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:764 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:768 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:772 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:780 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1004 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1008 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:760 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:764 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:768 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:772 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:780 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1004 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1008 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1012 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1016 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1020 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1024 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1032 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1260 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1012 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1016 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1020 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1024 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1032 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1260 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1512 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1512 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1600 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1600 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x408 ; msbs: dst=0 src0=0 src1=2 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1752 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1756 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1760 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1764 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1752 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1756 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1760 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1764 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1768 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1772 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1780 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:1992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:1996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2004 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2008 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2012 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2016 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1768 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1772 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1780 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:1992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:1996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2004 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2008 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2012 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2016 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2020 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2024 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2032 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2268 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2020 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2024 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2032 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2268 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2520 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2520 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2624 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2624 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x80c ; msbs: dst=0 src0=0 src1=3 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2752 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2756 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2760 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2764 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2768 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2772 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2752 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2756 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2760 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2764 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2768 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2772 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2780 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:2992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:2996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3004 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3008 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3012 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3016 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3020 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3024 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2780 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:2992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:2996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3004 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3008 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3012 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3016 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3020 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3024 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3032 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3276 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3032 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3276 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3528 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3528 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; 120-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3648 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3648 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0xc00 ; msbs: dst=0 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 ; 4-byte Folded Spill +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 nv ; 4-byte Folded Spill ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v40, s0, 3 ; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v2, v0 @@ -3723,940 +3723,940 @@ define amdgpu_gfx_whole_wave <2 x half> @call_gfx_from_whole_wave(i1 %active, <2 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s30, v40, 1 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s4, v40, 0 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s0, v40, 3 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s33 ; 4-byte Folded Reload +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s33 nv ; 4-byte Folded Reload ; GFX1250-DAGISEL-NEXT: s_mov_b32 s32, s33 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, s4, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s33 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s33 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s33 offset:12 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s33 offset:16 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4, off, s33 offset:20 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5, off, s33 offset:24 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6, off, s33 offset:28 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7, off, s33 offset:32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8, off, s33 offset:36 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9, off, s33 offset:40 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10, off, s33 offset:44 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11, off, s33 offset:48 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12, off, s33 offset:52 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13, off, s33 offset:56 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14, off, s33 offset:60 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15, off, s33 offset:64 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16, off, s33 offset:68 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17, off, s33 offset:72 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18, off, s33 offset:76 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19, off, s33 offset:80 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20, off, s33 offset:84 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21, off, s33 offset:88 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22, off, s33 offset:92 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23, off, s33 offset:96 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24, off, s33 offset:100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25, off, s33 offset:104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26, off, s33 offset:108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27, off, s33 offset:112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28, off, s33 offset:116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29, off, s33 offset:120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30, off, s33 offset:124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31, off, s33 offset:128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32, off, s33 offset:132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33, off, s33 offset:136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34, off, s33 offset:140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35, off, s33 offset:144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36, off, s33 offset:148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37, off, s33 offset:152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38, off, s33 offset:156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39, off, s33 offset:160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48, off, s33 offset:164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49, off, s33 offset:168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50, off, s33 offset:172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51, off, s33 offset:176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52, off, s33 offset:180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53, off, s33 offset:184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54, off, s33 offset:188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55, off, s33 offset:192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64, off, s33 offset:196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65, off, s33 offset:200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66, off, s33 offset:204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67, off, s33 offset:208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68, off, s33 offset:212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69, off, s33 offset:216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70, off, s33 offset:220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71, off, s33 offset:224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80, off, s33 offset:228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81, off, s33 offset:232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82, off, s33 offset:236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83, off, s33 offset:240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84, off, s33 offset:244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85, off, s33 offset:248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86, off, s33 offset:252 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s33 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s33 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s33 offset:12 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s33 offset:16 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4, off, s33 offset:20 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5, off, s33 offset:24 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6, off, s33 offset:28 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7, off, s33 offset:32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8, off, s33 offset:36 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9, off, s33 offset:40 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10, off, s33 offset:44 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11, off, s33 offset:48 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12, off, s33 offset:52 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13, off, s33 offset:56 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14, off, s33 offset:60 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15, off, s33 offset:64 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16, off, s33 offset:68 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17, off, s33 offset:72 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18, off, s33 offset:76 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19, off, s33 offset:80 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20, off, s33 offset:84 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21, off, s33 offset:88 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22, off, s33 offset:92 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23, off, s33 offset:96 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24, off, s33 offset:100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25, off, s33 offset:104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26, off, s33 offset:108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27, off, s33 offset:112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28, off, s33 offset:116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29, off, s33 offset:120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30, off, s33 offset:124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31, off, s33 offset:128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32, off, s33 offset:132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33, off, s33 offset:136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34, off, s33 offset:140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35, off, s33 offset:144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36, off, s33 offset:148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37, off, s33 offset:152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38, off, s33 offset:156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39, off, s33 offset:160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48, off, s33 offset:164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49, off, s33 offset:168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50, off, s33 offset:172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51, off, s33 offset:176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52, off, s33 offset:180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53, off, s33 offset:184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54, off, s33 offset:188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55, off, s33 offset:192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64, off, s33 offset:196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65, off, s33 offset:200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66, off, s33 offset:204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67, off, s33 offset:208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68, off, s33 offset:212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69, off, s33 offset:216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70, off, s33 offset:220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71, off, s33 offset:224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80, off, s33 offset:228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81, off, s33 offset:232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82, off, s33 offset:236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83, off, s33 offset:240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84, off, s33 offset:244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85, off, s33 offset:248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86, off, s33 offset:252 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87, off, s33 offset:256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96, off, s33 offset:260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97, off, s33 offset:264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98, off, s33 offset:268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99, off, s33 offset:272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100, off, s33 offset:276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101, off, s33 offset:280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102, off, s33 offset:284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103, off, s33 offset:288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112, off, s33 offset:292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113, off, s33 offset:296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114, off, s33 offset:300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115, off, s33 offset:304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116, off, s33 offset:308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117, off, s33 offset:312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118, off, s33 offset:316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119, off, s33 offset:320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128, off, s33 offset:324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129, off, s33 offset:328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130, off, s33 offset:332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131, off, s33 offset:336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132, off, s33 offset:340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133, off, s33 offset:344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134, off, s33 offset:348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135, off, s33 offset:352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144, off, s33 offset:356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145, off, s33 offset:360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146, off, s33 offset:364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147, off, s33 offset:368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148, off, s33 offset:372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149, off, s33 offset:376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150, off, s33 offset:380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151, off, s33 offset:384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160, off, s33 offset:388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161, off, s33 offset:392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162, off, s33 offset:396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163, off, s33 offset:400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164, off, s33 offset:404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165, off, s33 offset:408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166, off, s33 offset:412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167, off, s33 offset:416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176, off, s33 offset:420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177, off, s33 offset:424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178, off, s33 offset:428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179, off, s33 offset:432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180, off, s33 offset:436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181, off, s33 offset:440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182, off, s33 offset:444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183, off, s33 offset:448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192, off, s33 offset:452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193, off, s33 offset:456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194, off, s33 offset:460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195, off, s33 offset:464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196, off, s33 offset:468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197, off, s33 offset:472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198, off, s33 offset:476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199, off, s33 offset:480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208, off, s33 offset:484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209, off, s33 offset:488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210, off, s33 offset:492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211, off, s33 offset:496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212, off, s33 offset:500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213, off, s33 offset:504 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87, off, s33 offset:256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96, off, s33 offset:260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97, off, s33 offset:264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98, off, s33 offset:268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99, off, s33 offset:272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100, off, s33 offset:276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101, off, s33 offset:280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102, off, s33 offset:284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103, off, s33 offset:288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112, off, s33 offset:292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113, off, s33 offset:296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114, off, s33 offset:300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115, off, s33 offset:304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116, off, s33 offset:308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117, off, s33 offset:312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118, off, s33 offset:316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119, off, s33 offset:320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128, off, s33 offset:324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129, off, s33 offset:328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130, off, s33 offset:332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131, off, s33 offset:336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132, off, s33 offset:340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133, off, s33 offset:344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134, off, s33 offset:348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135, off, s33 offset:352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144, off, s33 offset:356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145, off, s33 offset:360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146, off, s33 offset:364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147, off, s33 offset:368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148, off, s33 offset:372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149, off, s33 offset:376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150, off, s33 offset:380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151, off, s33 offset:384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160, off, s33 offset:388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161, off, s33 offset:392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162, off, s33 offset:396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163, off, s33 offset:400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164, off, s33 offset:404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165, off, s33 offset:408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166, off, s33 offset:412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167, off, s33 offset:416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176, off, s33 offset:420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177, off, s33 offset:424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178, off, s33 offset:428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179, off, s33 offset:432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180, off, s33 offset:436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181, off, s33 offset:440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182, off, s33 offset:444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183, off, s33 offset:448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192, off, s33 offset:452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193, off, s33 offset:456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194, off, s33 offset:460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195, off, s33 offset:464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196, off, s33 offset:468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197, off, s33 offset:472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198, off, s33 offset:476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199, off, s33 offset:480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208, off, s33 offset:484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209, off, s33 offset:488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210, off, s33 offset:492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211, off, s33 offset:496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212, off, s33 offset:500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213, off, s33 offset:504 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214, off, s33 offset:508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215, off, s33 offset:512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224, off, s33 offset:516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225, off, s33 offset:520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226, off, s33 offset:524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227, off, s33 offset:528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228, off, s33 offset:532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229, off, s33 offset:536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230, off, s33 offset:540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231, off, s33 offset:544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240, off, s33 offset:548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241, off, s33 offset:552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242, off, s33 offset:556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243, off, s33 offset:560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244, off, s33 offset:564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245, off, s33 offset:568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246, off, s33 offset:572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247, off, s33 offset:576 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214, off, s33 offset:508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215, off, s33 offset:512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224, off, s33 offset:516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225, off, s33 offset:520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226, off, s33 offset:524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227, off, s33 offset:528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228, off, s33 offset:532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229, off, s33 offset:536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230, off, s33 offset:540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231, off, s33 offset:544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240, off, s33 offset:548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241, off, s33 offset:552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242, off, s33 offset:556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243, off, s33 offset:560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244, off, s33 offset:564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245, off, s33 offset:568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246, off, s33 offset:572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247, off, s33 offset:576 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 64 ; msbs: dst=1 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v256*/, off, s33 offset:580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v257*/, off, s33 offset:584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v258*/, off, s33 offset:588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v259*/, off, s33 offset:592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v260*/, off, s33 offset:596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v261*/, off, s33 offset:600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v262*/, off, s33 offset:604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v263*/, off, s33 offset:608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v264*/, off, s33 offset:612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v265*/, off, s33 offset:616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v266*/, off, s33 offset:620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v267*/, off, s33 offset:624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v268*/, off, s33 offset:628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v269*/, off, s33 offset:632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v270*/, off, s33 offset:636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v271*/, off, s33 offset:640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v272*/, off, s33 offset:644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v273*/, off, s33 offset:648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v274*/, off, s33 offset:652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v275*/, off, s33 offset:656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v276*/, off, s33 offset:660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v277*/, off, s33 offset:664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v278*/, off, s33 offset:668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v279*/, off, s33 offset:672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v280*/, off, s33 offset:676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v281*/, off, s33 offset:680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v282*/, off, s33 offset:684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v283*/, off, s33 offset:688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v284*/, off, s33 offset:692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v285*/, off, s33 offset:696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v286*/, off, s33 offset:700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v287*/, off, s33 offset:704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v288*/, off, s33 offset:708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v289*/, off, s33 offset:712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v290*/, off, s33 offset:716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v291*/, off, s33 offset:720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v292*/, off, s33 offset:724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v293*/, off, s33 offset:728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v294*/, off, s33 offset:732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v295*/, off, s33 offset:736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v296*/, off, s33 offset:740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v297*/, off, s33 offset:744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v298*/, off, s33 offset:748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v299*/, off, s33 offset:752 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v300*/, off, s33 offset:756 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v256*/, off, s33 offset:580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v257*/, off, s33 offset:584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v258*/, off, s33 offset:588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v259*/, off, s33 offset:592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v260*/, off, s33 offset:596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v261*/, off, s33 offset:600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v262*/, off, s33 offset:604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v263*/, off, s33 offset:608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v264*/, off, s33 offset:612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v265*/, off, s33 offset:616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v266*/, off, s33 offset:620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v267*/, off, s33 offset:624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v268*/, off, s33 offset:628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v269*/, off, s33 offset:632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v270*/, off, s33 offset:636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v271*/, off, s33 offset:640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v272*/, off, s33 offset:644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v273*/, off, s33 offset:648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v274*/, off, s33 offset:652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v275*/, off, s33 offset:656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v276*/, off, s33 offset:660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v277*/, off, s33 offset:664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v278*/, off, s33 offset:668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v279*/, off, s33 offset:672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v280*/, off, s33 offset:676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v281*/, off, s33 offset:680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v282*/, off, s33 offset:684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v283*/, off, s33 offset:688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v284*/, off, s33 offset:692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v285*/, off, s33 offset:696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v286*/, off, s33 offset:700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v287*/, off, s33 offset:704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v288*/, off, s33 offset:708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v289*/, off, s33 offset:712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v290*/, off, s33 offset:716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v291*/, off, s33 offset:720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v292*/, off, s33 offset:724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v293*/, off, s33 offset:728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v294*/, off, s33 offset:732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v295*/, off, s33 offset:736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v296*/, off, s33 offset:740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v297*/, off, s33 offset:744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v298*/, off, s33 offset:748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v299*/, off, s33 offset:752 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v300*/, off, s33 offset:756 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v301*/, off, s33 offset:760 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v302*/, off, s33 offset:764 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v303*/, off, s33 offset:768 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v304*/, off, s33 offset:772 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v305*/, off, s33 offset:776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v306*/, off, s33 offset:780 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v307*/, off, s33 offset:784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v308*/, off, s33 offset:788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v309*/, off, s33 offset:792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v310*/, off, s33 offset:796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v311*/, off, s33 offset:800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v312*/, off, s33 offset:804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v313*/, off, s33 offset:808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v314*/, off, s33 offset:812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v315*/, off, s33 offset:816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v316*/, off, s33 offset:820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v317*/, off, s33 offset:824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v318*/, off, s33 offset:828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v319*/, off, s33 offset:832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v320*/, off, s33 offset:836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v321*/, off, s33 offset:840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v322*/, off, s33 offset:844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v323*/, off, s33 offset:848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v324*/, off, s33 offset:852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v325*/, off, s33 offset:856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v326*/, off, s33 offset:860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v327*/, off, s33 offset:864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v328*/, off, s33 offset:868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v329*/, off, s33 offset:872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v330*/, off, s33 offset:876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v331*/, off, s33 offset:880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v332*/, off, s33 offset:884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v333*/, off, s33 offset:888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v334*/, off, s33 offset:892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v335*/, off, s33 offset:896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v336*/, off, s33 offset:900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v337*/, off, s33 offset:904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v338*/, off, s33 offset:908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v339*/, off, s33 offset:912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v340*/, off, s33 offset:916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v341*/, off, s33 offset:920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v342*/, off, s33 offset:924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v343*/, off, s33 offset:928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v344*/, off, s33 offset:932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v345*/, off, s33 offset:936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v346*/, off, s33 offset:940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v347*/, off, s33 offset:944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v348*/, off, s33 offset:948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v349*/, off, s33 offset:952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v350*/, off, s33 offset:956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v351*/, off, s33 offset:960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v352*/, off, s33 offset:964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v353*/, off, s33 offset:968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v354*/, off, s33 offset:972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v355*/, off, s33 offset:976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v356*/, off, s33 offset:980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v357*/, off, s33 offset:984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v358*/, off, s33 offset:988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v359*/, off, s33 offset:992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v360*/, off, s33 offset:996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v361*/, off, s33 offset:1000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v362*/, off, s33 offset:1004 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v363*/, off, s33 offset:1008 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v301*/, off, s33 offset:760 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v302*/, off, s33 offset:764 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v303*/, off, s33 offset:768 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v304*/, off, s33 offset:772 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v305*/, off, s33 offset:776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v306*/, off, s33 offset:780 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v307*/, off, s33 offset:784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v308*/, off, s33 offset:788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v309*/, off, s33 offset:792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v310*/, off, s33 offset:796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v311*/, off, s33 offset:800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v312*/, off, s33 offset:804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v313*/, off, s33 offset:808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v314*/, off, s33 offset:812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v315*/, off, s33 offset:816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v316*/, off, s33 offset:820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v317*/, off, s33 offset:824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v318*/, off, s33 offset:828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v319*/, off, s33 offset:832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v320*/, off, s33 offset:836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v321*/, off, s33 offset:840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v322*/, off, s33 offset:844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v323*/, off, s33 offset:848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v324*/, off, s33 offset:852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v325*/, off, s33 offset:856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v326*/, off, s33 offset:860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v327*/, off, s33 offset:864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v328*/, off, s33 offset:868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v329*/, off, s33 offset:872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v330*/, off, s33 offset:876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v331*/, off, s33 offset:880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v332*/, off, s33 offset:884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v333*/, off, s33 offset:888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v334*/, off, s33 offset:892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v335*/, off, s33 offset:896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v336*/, off, s33 offset:900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v337*/, off, s33 offset:904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v338*/, off, s33 offset:908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v339*/, off, s33 offset:912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v340*/, off, s33 offset:916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v341*/, off, s33 offset:920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v342*/, off, s33 offset:924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v343*/, off, s33 offset:928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v344*/, off, s33 offset:932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v345*/, off, s33 offset:936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v346*/, off, s33 offset:940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v347*/, off, s33 offset:944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v348*/, off, s33 offset:948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v349*/, off, s33 offset:952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v350*/, off, s33 offset:956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v351*/, off, s33 offset:960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v352*/, off, s33 offset:964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v353*/, off, s33 offset:968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v354*/, off, s33 offset:972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v355*/, off, s33 offset:976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v356*/, off, s33 offset:980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v357*/, off, s33 offset:984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v358*/, off, s33 offset:988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v359*/, off, s33 offset:992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v360*/, off, s33 offset:996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v361*/, off, s33 offset:1000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v362*/, off, s33 offset:1004 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v363*/, off, s33 offset:1008 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v364*/, off, s33 offset:1012 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v365*/, off, s33 offset:1016 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v366*/, off, s33 offset:1020 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v367*/, off, s33 offset:1024 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v368*/, off, s33 offset:1028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v369*/, off, s33 offset:1032 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v370*/, off, s33 offset:1036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v371*/, off, s33 offset:1040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v372*/, off, s33 offset:1044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v373*/, off, s33 offset:1048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v374*/, off, s33 offset:1052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v375*/, off, s33 offset:1056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v376*/, off, s33 offset:1060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v377*/, off, s33 offset:1064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v378*/, off, s33 offset:1068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v379*/, off, s33 offset:1072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v380*/, off, s33 offset:1076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v381*/, off, s33 offset:1080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v382*/, off, s33 offset:1084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v383*/, off, s33 offset:1088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v384*/, off, s33 offset:1092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v385*/, off, s33 offset:1096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v386*/, off, s33 offset:1100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v387*/, off, s33 offset:1104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v388*/, off, s33 offset:1108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v389*/, off, s33 offset:1112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v390*/, off, s33 offset:1116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v391*/, off, s33 offset:1120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v392*/, off, s33 offset:1124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v393*/, off, s33 offset:1128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v394*/, off, s33 offset:1132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v395*/, off, s33 offset:1136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v396*/, off, s33 offset:1140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v397*/, off, s33 offset:1144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v398*/, off, s33 offset:1148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v399*/, off, s33 offset:1152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v400*/, off, s33 offset:1156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v401*/, off, s33 offset:1160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v402*/, off, s33 offset:1164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v403*/, off, s33 offset:1168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v404*/, off, s33 offset:1172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v405*/, off, s33 offset:1176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v406*/, off, s33 offset:1180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v407*/, off, s33 offset:1184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v408*/, off, s33 offset:1188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v409*/, off, s33 offset:1192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v410*/, off, s33 offset:1196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v411*/, off, s33 offset:1200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v412*/, off, s33 offset:1204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v413*/, off, s33 offset:1208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v414*/, off, s33 offset:1212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v415*/, off, s33 offset:1216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v416*/, off, s33 offset:1220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v417*/, off, s33 offset:1224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v418*/, off, s33 offset:1228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v419*/, off, s33 offset:1232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v420*/, off, s33 offset:1236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v421*/, off, s33 offset:1240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v422*/, off, s33 offset:1244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v423*/, off, s33 offset:1248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v424*/, off, s33 offset:1252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v425*/, off, s33 offset:1256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v426*/, off, s33 offset:1260 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v364*/, off, s33 offset:1012 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v365*/, off, s33 offset:1016 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v366*/, off, s33 offset:1020 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v367*/, off, s33 offset:1024 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v368*/, off, s33 offset:1028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v369*/, off, s33 offset:1032 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v370*/, off, s33 offset:1036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v371*/, off, s33 offset:1040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v372*/, off, s33 offset:1044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v373*/, off, s33 offset:1048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v374*/, off, s33 offset:1052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v375*/, off, s33 offset:1056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v376*/, off, s33 offset:1060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v377*/, off, s33 offset:1064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v378*/, off, s33 offset:1068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v379*/, off, s33 offset:1072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v380*/, off, s33 offset:1076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v381*/, off, s33 offset:1080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v382*/, off, s33 offset:1084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v383*/, off, s33 offset:1088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v384*/, off, s33 offset:1092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v385*/, off, s33 offset:1096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v386*/, off, s33 offset:1100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v387*/, off, s33 offset:1104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v388*/, off, s33 offset:1108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v389*/, off, s33 offset:1112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v390*/, off, s33 offset:1116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v391*/, off, s33 offset:1120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v392*/, off, s33 offset:1124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v393*/, off, s33 offset:1128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v394*/, off, s33 offset:1132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v395*/, off, s33 offset:1136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v396*/, off, s33 offset:1140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v397*/, off, s33 offset:1144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v398*/, off, s33 offset:1148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v399*/, off, s33 offset:1152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v400*/, off, s33 offset:1156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v401*/, off, s33 offset:1160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v402*/, off, s33 offset:1164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v403*/, off, s33 offset:1168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v404*/, off, s33 offset:1172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v405*/, off, s33 offset:1176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v406*/, off, s33 offset:1180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v407*/, off, s33 offset:1184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v408*/, off, s33 offset:1188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v409*/, off, s33 offset:1192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v410*/, off, s33 offset:1196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v411*/, off, s33 offset:1200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v412*/, off, s33 offset:1204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v413*/, off, s33 offset:1208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v414*/, off, s33 offset:1212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v415*/, off, s33 offset:1216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v416*/, off, s33 offset:1220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v417*/, off, s33 offset:1224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v418*/, off, s33 offset:1228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v419*/, off, s33 offset:1232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v420*/, off, s33 offset:1236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v421*/, off, s33 offset:1240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v422*/, off, s33 offset:1244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v423*/, off, s33 offset:1248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v424*/, off, s33 offset:1252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v425*/, off, s33 offset:1256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v426*/, off, s33 offset:1260 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v427*/, off, s33 offset:1264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v428*/, off, s33 offset:1268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v429*/, off, s33 offset:1272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v430*/, off, s33 offset:1276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v431*/, off, s33 offset:1280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v432*/, off, s33 offset:1284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v433*/, off, s33 offset:1288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v434*/, off, s33 offset:1292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v435*/, off, s33 offset:1296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v436*/, off, s33 offset:1300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v437*/, off, s33 offset:1304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v438*/, off, s33 offset:1308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v439*/, off, s33 offset:1312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v440*/, off, s33 offset:1316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v441*/, off, s33 offset:1320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v442*/, off, s33 offset:1324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v443*/, off, s33 offset:1328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v444*/, off, s33 offset:1332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v445*/, off, s33 offset:1336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v446*/, off, s33 offset:1340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v447*/, off, s33 offset:1344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v448*/, off, s33 offset:1348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v449*/, off, s33 offset:1352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v450*/, off, s33 offset:1356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v451*/, off, s33 offset:1360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v452*/, off, s33 offset:1364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v453*/, off, s33 offset:1368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v454*/, off, s33 offset:1372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v455*/, off, s33 offset:1376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v456*/, off, s33 offset:1380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v457*/, off, s33 offset:1384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v458*/, off, s33 offset:1388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v459*/, off, s33 offset:1392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v460*/, off, s33 offset:1396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v461*/, off, s33 offset:1400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v462*/, off, s33 offset:1404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v463*/, off, s33 offset:1408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v464*/, off, s33 offset:1412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v465*/, off, s33 offset:1416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v466*/, off, s33 offset:1420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v467*/, off, s33 offset:1424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v468*/, off, s33 offset:1428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v469*/, off, s33 offset:1432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v470*/, off, s33 offset:1436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v471*/, off, s33 offset:1440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v472*/, off, s33 offset:1444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v473*/, off, s33 offset:1448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v474*/, off, s33 offset:1452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v475*/, off, s33 offset:1456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v476*/, off, s33 offset:1460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v477*/, off, s33 offset:1464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v478*/, off, s33 offset:1468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v479*/, off, s33 offset:1472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v480*/, off, s33 offset:1476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v481*/, off, s33 offset:1480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v482*/, off, s33 offset:1484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v483*/, off, s33 offset:1488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v484*/, off, s33 offset:1492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v485*/, off, s33 offset:1496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v486*/, off, s33 offset:1500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v487*/, off, s33 offset:1504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v488*/, off, s33 offset:1508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v489*/, off, s33 offset:1512 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v427*/, off, s33 offset:1264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v428*/, off, s33 offset:1268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v429*/, off, s33 offset:1272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v430*/, off, s33 offset:1276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v431*/, off, s33 offset:1280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v432*/, off, s33 offset:1284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v433*/, off, s33 offset:1288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v434*/, off, s33 offset:1292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v435*/, off, s33 offset:1296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v436*/, off, s33 offset:1300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v437*/, off, s33 offset:1304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v438*/, off, s33 offset:1308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v439*/, off, s33 offset:1312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v440*/, off, s33 offset:1316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v441*/, off, s33 offset:1320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v442*/, off, s33 offset:1324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v443*/, off, s33 offset:1328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v444*/, off, s33 offset:1332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v445*/, off, s33 offset:1336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v446*/, off, s33 offset:1340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v447*/, off, s33 offset:1344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v448*/, off, s33 offset:1348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v449*/, off, s33 offset:1352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v450*/, off, s33 offset:1356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v451*/, off, s33 offset:1360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v452*/, off, s33 offset:1364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v453*/, off, s33 offset:1368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v454*/, off, s33 offset:1372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v455*/, off, s33 offset:1376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v456*/, off, s33 offset:1380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v457*/, off, s33 offset:1384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v458*/, off, s33 offset:1388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v459*/, off, s33 offset:1392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v460*/, off, s33 offset:1396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v461*/, off, s33 offset:1400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v462*/, off, s33 offset:1404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v463*/, off, s33 offset:1408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v464*/, off, s33 offset:1412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v465*/, off, s33 offset:1416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v466*/, off, s33 offset:1420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v467*/, off, s33 offset:1424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v468*/, off, s33 offset:1428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v469*/, off, s33 offset:1432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v470*/, off, s33 offset:1436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v471*/, off, s33 offset:1440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v472*/, off, s33 offset:1444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v473*/, off, s33 offset:1448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v474*/, off, s33 offset:1452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v475*/, off, s33 offset:1456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v476*/, off, s33 offset:1460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v477*/, off, s33 offset:1464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v478*/, off, s33 offset:1468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v479*/, off, s33 offset:1472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v480*/, off, s33 offset:1476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v481*/, off, s33 offset:1480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v482*/, off, s33 offset:1484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v483*/, off, s33 offset:1488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v484*/, off, s33 offset:1492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v485*/, off, s33 offset:1496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v486*/, off, s33 offset:1500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v487*/, off, s33 offset:1504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v488*/, off, s33 offset:1508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v489*/, off, s33 offset:1512 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v490*/, off, s33 offset:1516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v491*/, off, s33 offset:1520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v492*/, off, s33 offset:1524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v493*/, off, s33 offset:1528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v494*/, off, s33 offset:1532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v495*/, off, s33 offset:1536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v496*/, off, s33 offset:1540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v497*/, off, s33 offset:1544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v498*/, off, s33 offset:1548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v499*/, off, s33 offset:1552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v500*/, off, s33 offset:1556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v501*/, off, s33 offset:1560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v502*/, off, s33 offset:1564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v503*/, off, s33 offset:1568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v504*/, off, s33 offset:1572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v505*/, off, s33 offset:1576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v506*/, off, s33 offset:1580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v507*/, off, s33 offset:1584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v508*/, off, s33 offset:1588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v509*/, off, s33 offset:1592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v510*/, off, s33 offset:1596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v511*/, off, s33 offset:1600 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v490*/, off, s33 offset:1516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v491*/, off, s33 offset:1520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v492*/, off, s33 offset:1524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v493*/, off, s33 offset:1528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v494*/, off, s33 offset:1532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v495*/, off, s33 offset:1536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v496*/, off, s33 offset:1540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v497*/, off, s33 offset:1544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v498*/, off, s33 offset:1548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v499*/, off, s33 offset:1552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v500*/, off, s33 offset:1556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v501*/, off, s33 offset:1560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v502*/, off, s33 offset:1564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v503*/, off, s33 offset:1568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v504*/, off, s33 offset:1572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v505*/, off, s33 offset:1576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v506*/, off, s33 offset:1580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v507*/, off, s33 offset:1584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v508*/, off, s33 offset:1588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v509*/, off, s33 offset:1592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v510*/, off, s33 offset:1596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v511*/, off, s33 offset:1600 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x4080 ; msbs: dst=2 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v512*/, off, s33 offset:1604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v513*/, off, s33 offset:1608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v514*/, off, s33 offset:1612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v515*/, off, s33 offset:1616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v516*/, off, s33 offset:1620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v517*/, off, s33 offset:1624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v518*/, off, s33 offset:1628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v519*/, off, s33 offset:1632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v520*/, off, s33 offset:1636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v521*/, off, s33 offset:1640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v522*/, off, s33 offset:1644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v523*/, off, s33 offset:1648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v524*/, off, s33 offset:1652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v525*/, off, s33 offset:1656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v526*/, off, s33 offset:1660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v527*/, off, s33 offset:1664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v528*/, off, s33 offset:1668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v529*/, off, s33 offset:1672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v530*/, off, s33 offset:1676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v531*/, off, s33 offset:1680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v532*/, off, s33 offset:1684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v533*/, off, s33 offset:1688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v534*/, off, s33 offset:1692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v535*/, off, s33 offset:1696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v536*/, off, s33 offset:1700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v537*/, off, s33 offset:1704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v538*/, off, s33 offset:1708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v539*/, off, s33 offset:1712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v540*/, off, s33 offset:1716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v541*/, off, s33 offset:1720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v542*/, off, s33 offset:1724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v543*/, off, s33 offset:1728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v544*/, off, s33 offset:1732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v545*/, off, s33 offset:1736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v546*/, off, s33 offset:1740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v547*/, off, s33 offset:1744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v548*/, off, s33 offset:1748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v549*/, off, s33 offset:1752 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v550*/, off, s33 offset:1756 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v551*/, off, s33 offset:1760 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v552*/, off, s33 offset:1764 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v512*/, off, s33 offset:1604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v513*/, off, s33 offset:1608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v514*/, off, s33 offset:1612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v515*/, off, s33 offset:1616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v516*/, off, s33 offset:1620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v517*/, off, s33 offset:1624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v518*/, off, s33 offset:1628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v519*/, off, s33 offset:1632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v520*/, off, s33 offset:1636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v521*/, off, s33 offset:1640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v522*/, off, s33 offset:1644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v523*/, off, s33 offset:1648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v524*/, off, s33 offset:1652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v525*/, off, s33 offset:1656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v526*/, off, s33 offset:1660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v527*/, off, s33 offset:1664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v528*/, off, s33 offset:1668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v529*/, off, s33 offset:1672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v530*/, off, s33 offset:1676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v531*/, off, s33 offset:1680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v532*/, off, s33 offset:1684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v533*/, off, s33 offset:1688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v534*/, off, s33 offset:1692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v535*/, off, s33 offset:1696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v536*/, off, s33 offset:1700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v537*/, off, s33 offset:1704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v538*/, off, s33 offset:1708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v539*/, off, s33 offset:1712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v540*/, off, s33 offset:1716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v541*/, off, s33 offset:1720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v542*/, off, s33 offset:1724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v543*/, off, s33 offset:1728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v544*/, off, s33 offset:1732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v545*/, off, s33 offset:1736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v546*/, off, s33 offset:1740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v547*/, off, s33 offset:1744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v548*/, off, s33 offset:1748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v549*/, off, s33 offset:1752 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v550*/, off, s33 offset:1756 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v551*/, off, s33 offset:1760 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v552*/, off, s33 offset:1764 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v553*/, off, s33 offset:1768 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v554*/, off, s33 offset:1772 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v555*/, off, s33 offset:1776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v556*/, off, s33 offset:1780 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v557*/, off, s33 offset:1784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v558*/, off, s33 offset:1788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v559*/, off, s33 offset:1792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v560*/, off, s33 offset:1796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v561*/, off, s33 offset:1800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v562*/, off, s33 offset:1804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v563*/, off, s33 offset:1808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v564*/, off, s33 offset:1812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v565*/, off, s33 offset:1816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v566*/, off, s33 offset:1820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v567*/, off, s33 offset:1824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v568*/, off, s33 offset:1828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v569*/, off, s33 offset:1832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v570*/, off, s33 offset:1836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v571*/, off, s33 offset:1840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v572*/, off, s33 offset:1844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v573*/, off, s33 offset:1848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v574*/, off, s33 offset:1852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v575*/, off, s33 offset:1856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v576*/, off, s33 offset:1860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v577*/, off, s33 offset:1864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v578*/, off, s33 offset:1868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v579*/, off, s33 offset:1872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v580*/, off, s33 offset:1876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v581*/, off, s33 offset:1880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v582*/, off, s33 offset:1884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v583*/, off, s33 offset:1888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v584*/, off, s33 offset:1892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v585*/, off, s33 offset:1896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v586*/, off, s33 offset:1900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v587*/, off, s33 offset:1904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v588*/, off, s33 offset:1908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v589*/, off, s33 offset:1912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v590*/, off, s33 offset:1916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v591*/, off, s33 offset:1920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v592*/, off, s33 offset:1924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v593*/, off, s33 offset:1928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v594*/, off, s33 offset:1932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v595*/, off, s33 offset:1936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v596*/, off, s33 offset:1940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v597*/, off, s33 offset:1944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v598*/, off, s33 offset:1948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v599*/, off, s33 offset:1952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v600*/, off, s33 offset:1956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v601*/, off, s33 offset:1960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v602*/, off, s33 offset:1964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v603*/, off, s33 offset:1968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v604*/, off, s33 offset:1972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v605*/, off, s33 offset:1976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v606*/, off, s33 offset:1980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v607*/, off, s33 offset:1984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v608*/, off, s33 offset:1988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v609*/, off, s33 offset:1992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v610*/, off, s33 offset:1996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v611*/, off, s33 offset:2000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v612*/, off, s33 offset:2004 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v613*/, off, s33 offset:2008 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v614*/, off, s33 offset:2012 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v615*/, off, s33 offset:2016 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v553*/, off, s33 offset:1768 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v554*/, off, s33 offset:1772 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v555*/, off, s33 offset:1776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v556*/, off, s33 offset:1780 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v557*/, off, s33 offset:1784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v558*/, off, s33 offset:1788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v559*/, off, s33 offset:1792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v560*/, off, s33 offset:1796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v561*/, off, s33 offset:1800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v562*/, off, s33 offset:1804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v563*/, off, s33 offset:1808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v564*/, off, s33 offset:1812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v565*/, off, s33 offset:1816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v566*/, off, s33 offset:1820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v567*/, off, s33 offset:1824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v568*/, off, s33 offset:1828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v569*/, off, s33 offset:1832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v570*/, off, s33 offset:1836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v571*/, off, s33 offset:1840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v572*/, off, s33 offset:1844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v573*/, off, s33 offset:1848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v574*/, off, s33 offset:1852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v575*/, off, s33 offset:1856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v576*/, off, s33 offset:1860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v577*/, off, s33 offset:1864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v578*/, off, s33 offset:1868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v579*/, off, s33 offset:1872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v580*/, off, s33 offset:1876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v581*/, off, s33 offset:1880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v582*/, off, s33 offset:1884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v583*/, off, s33 offset:1888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v584*/, off, s33 offset:1892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v585*/, off, s33 offset:1896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v586*/, off, s33 offset:1900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v587*/, off, s33 offset:1904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v588*/, off, s33 offset:1908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v589*/, off, s33 offset:1912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v590*/, off, s33 offset:1916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v591*/, off, s33 offset:1920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v592*/, off, s33 offset:1924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v593*/, off, s33 offset:1928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v594*/, off, s33 offset:1932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v595*/, off, s33 offset:1936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v596*/, off, s33 offset:1940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v597*/, off, s33 offset:1944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v598*/, off, s33 offset:1948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v599*/, off, s33 offset:1952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v600*/, off, s33 offset:1956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v601*/, off, s33 offset:1960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v602*/, off, s33 offset:1964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v603*/, off, s33 offset:1968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v604*/, off, s33 offset:1972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v605*/, off, s33 offset:1976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v606*/, off, s33 offset:1980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v607*/, off, s33 offset:1984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v608*/, off, s33 offset:1988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v609*/, off, s33 offset:1992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v610*/, off, s33 offset:1996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v611*/, off, s33 offset:2000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v612*/, off, s33 offset:2004 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v613*/, off, s33 offset:2008 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v614*/, off, s33 offset:2012 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v615*/, off, s33 offset:2016 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v616*/, off, s33 offset:2020 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v617*/, off, s33 offset:2024 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v618*/, off, s33 offset:2028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v619*/, off, s33 offset:2032 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v620*/, off, s33 offset:2036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v621*/, off, s33 offset:2040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v622*/, off, s33 offset:2044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v623*/, off, s33 offset:2048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v624*/, off, s33 offset:2052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v625*/, off, s33 offset:2056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v626*/, off, s33 offset:2060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v627*/, off, s33 offset:2064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v628*/, off, s33 offset:2068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v629*/, off, s33 offset:2072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v630*/, off, s33 offset:2076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v631*/, off, s33 offset:2080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v632*/, off, s33 offset:2084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v633*/, off, s33 offset:2088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v634*/, off, s33 offset:2092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v635*/, off, s33 offset:2096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v636*/, off, s33 offset:2100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v637*/, off, s33 offset:2104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v638*/, off, s33 offset:2108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v639*/, off, s33 offset:2112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v640*/, off, s33 offset:2116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v641*/, off, s33 offset:2120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v642*/, off, s33 offset:2124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v643*/, off, s33 offset:2128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v644*/, off, s33 offset:2132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v645*/, off, s33 offset:2136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v646*/, off, s33 offset:2140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v647*/, off, s33 offset:2144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v648*/, off, s33 offset:2148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v649*/, off, s33 offset:2152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v650*/, off, s33 offset:2156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v651*/, off, s33 offset:2160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v652*/, off, s33 offset:2164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v653*/, off, s33 offset:2168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v654*/, off, s33 offset:2172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v655*/, off, s33 offset:2176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v656*/, off, s33 offset:2180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v657*/, off, s33 offset:2184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v658*/, off, s33 offset:2188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v659*/, off, s33 offset:2192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v660*/, off, s33 offset:2196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v661*/, off, s33 offset:2200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v662*/, off, s33 offset:2204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v663*/, off, s33 offset:2208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v664*/, off, s33 offset:2212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v665*/, off, s33 offset:2216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v666*/, off, s33 offset:2220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v667*/, off, s33 offset:2224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v668*/, off, s33 offset:2228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v669*/, off, s33 offset:2232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v670*/, off, s33 offset:2236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v671*/, off, s33 offset:2240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v672*/, off, s33 offset:2244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v673*/, off, s33 offset:2248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v674*/, off, s33 offset:2252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v675*/, off, s33 offset:2256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v676*/, off, s33 offset:2260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v677*/, off, s33 offset:2264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v678*/, off, s33 offset:2268 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v616*/, off, s33 offset:2020 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v617*/, off, s33 offset:2024 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v618*/, off, s33 offset:2028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v619*/, off, s33 offset:2032 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v620*/, off, s33 offset:2036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v621*/, off, s33 offset:2040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v622*/, off, s33 offset:2044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v623*/, off, s33 offset:2048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v624*/, off, s33 offset:2052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v625*/, off, s33 offset:2056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v626*/, off, s33 offset:2060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v627*/, off, s33 offset:2064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v628*/, off, s33 offset:2068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v629*/, off, s33 offset:2072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v630*/, off, s33 offset:2076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v631*/, off, s33 offset:2080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v632*/, off, s33 offset:2084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v633*/, off, s33 offset:2088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v634*/, off, s33 offset:2092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v635*/, off, s33 offset:2096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v636*/, off, s33 offset:2100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v637*/, off, s33 offset:2104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v638*/, off, s33 offset:2108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v639*/, off, s33 offset:2112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v640*/, off, s33 offset:2116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v641*/, off, s33 offset:2120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v642*/, off, s33 offset:2124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v643*/, off, s33 offset:2128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v644*/, off, s33 offset:2132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v645*/, off, s33 offset:2136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v646*/, off, s33 offset:2140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v647*/, off, s33 offset:2144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v648*/, off, s33 offset:2148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v649*/, off, s33 offset:2152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v650*/, off, s33 offset:2156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v651*/, off, s33 offset:2160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v652*/, off, s33 offset:2164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v653*/, off, s33 offset:2168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v654*/, off, s33 offset:2172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v655*/, off, s33 offset:2176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v656*/, off, s33 offset:2180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v657*/, off, s33 offset:2184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v658*/, off, s33 offset:2188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v659*/, off, s33 offset:2192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v660*/, off, s33 offset:2196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v661*/, off, s33 offset:2200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v662*/, off, s33 offset:2204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v663*/, off, s33 offset:2208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v664*/, off, s33 offset:2212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v665*/, off, s33 offset:2216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v666*/, off, s33 offset:2220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v667*/, off, s33 offset:2224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v668*/, off, s33 offset:2228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v669*/, off, s33 offset:2232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v670*/, off, s33 offset:2236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v671*/, off, s33 offset:2240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v672*/, off, s33 offset:2244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v673*/, off, s33 offset:2248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v674*/, off, s33 offset:2252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v675*/, off, s33 offset:2256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v676*/, off, s33 offset:2260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v677*/, off, s33 offset:2264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v678*/, off, s33 offset:2268 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v679*/, off, s33 offset:2272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v680*/, off, s33 offset:2276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v681*/, off, s33 offset:2280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v682*/, off, s33 offset:2284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v683*/, off, s33 offset:2288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v684*/, off, s33 offset:2292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v685*/, off, s33 offset:2296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v686*/, off, s33 offset:2300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v687*/, off, s33 offset:2304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v688*/, off, s33 offset:2308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v689*/, off, s33 offset:2312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v690*/, off, s33 offset:2316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v691*/, off, s33 offset:2320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v692*/, off, s33 offset:2324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v693*/, off, s33 offset:2328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v694*/, off, s33 offset:2332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v695*/, off, s33 offset:2336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v696*/, off, s33 offset:2340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v697*/, off, s33 offset:2344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v698*/, off, s33 offset:2348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v699*/, off, s33 offset:2352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v700*/, off, s33 offset:2356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v701*/, off, s33 offset:2360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v702*/, off, s33 offset:2364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v703*/, off, s33 offset:2368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v704*/, off, s33 offset:2372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v705*/, off, s33 offset:2376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v706*/, off, s33 offset:2380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v707*/, off, s33 offset:2384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v708*/, off, s33 offset:2388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v709*/, off, s33 offset:2392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v710*/, off, s33 offset:2396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v711*/, off, s33 offset:2400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v712*/, off, s33 offset:2404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v713*/, off, s33 offset:2408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v714*/, off, s33 offset:2412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v715*/, off, s33 offset:2416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v716*/, off, s33 offset:2420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v717*/, off, s33 offset:2424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v718*/, off, s33 offset:2428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v719*/, off, s33 offset:2432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v720*/, off, s33 offset:2436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v721*/, off, s33 offset:2440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v722*/, off, s33 offset:2444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v723*/, off, s33 offset:2448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v724*/, off, s33 offset:2452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v725*/, off, s33 offset:2456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v726*/, off, s33 offset:2460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v727*/, off, s33 offset:2464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v728*/, off, s33 offset:2468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v729*/, off, s33 offset:2472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v730*/, off, s33 offset:2476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v731*/, off, s33 offset:2480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v732*/, off, s33 offset:2484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v733*/, off, s33 offset:2488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v734*/, off, s33 offset:2492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v735*/, off, s33 offset:2496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v736*/, off, s33 offset:2500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v737*/, off, s33 offset:2504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v738*/, off, s33 offset:2508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v739*/, off, s33 offset:2512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v740*/, off, s33 offset:2516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v741*/, off, s33 offset:2520 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v679*/, off, s33 offset:2272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v680*/, off, s33 offset:2276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v681*/, off, s33 offset:2280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v682*/, off, s33 offset:2284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v683*/, off, s33 offset:2288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v684*/, off, s33 offset:2292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v685*/, off, s33 offset:2296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v686*/, off, s33 offset:2300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v687*/, off, s33 offset:2304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v688*/, off, s33 offset:2308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v689*/, off, s33 offset:2312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v690*/, off, s33 offset:2316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v691*/, off, s33 offset:2320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v692*/, off, s33 offset:2324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v693*/, off, s33 offset:2328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v694*/, off, s33 offset:2332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v695*/, off, s33 offset:2336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v696*/, off, s33 offset:2340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v697*/, off, s33 offset:2344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v698*/, off, s33 offset:2348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v699*/, off, s33 offset:2352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v700*/, off, s33 offset:2356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v701*/, off, s33 offset:2360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v702*/, off, s33 offset:2364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v703*/, off, s33 offset:2368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v704*/, off, s33 offset:2372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v705*/, off, s33 offset:2376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v706*/, off, s33 offset:2380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v707*/, off, s33 offset:2384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v708*/, off, s33 offset:2388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v709*/, off, s33 offset:2392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v710*/, off, s33 offset:2396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v711*/, off, s33 offset:2400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v712*/, off, s33 offset:2404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v713*/, off, s33 offset:2408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v714*/, off, s33 offset:2412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v715*/, off, s33 offset:2416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v716*/, off, s33 offset:2420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v717*/, off, s33 offset:2424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v718*/, off, s33 offset:2428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v719*/, off, s33 offset:2432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v720*/, off, s33 offset:2436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v721*/, off, s33 offset:2440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v722*/, off, s33 offset:2444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v723*/, off, s33 offset:2448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v724*/, off, s33 offset:2452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v725*/, off, s33 offset:2456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v726*/, off, s33 offset:2460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v727*/, off, s33 offset:2464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v728*/, off, s33 offset:2468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v729*/, off, s33 offset:2472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v730*/, off, s33 offset:2476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v731*/, off, s33 offset:2480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v732*/, off, s33 offset:2484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v733*/, off, s33 offset:2488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v734*/, off, s33 offset:2492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v735*/, off, s33 offset:2496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v736*/, off, s33 offset:2500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v737*/, off, s33 offset:2504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v738*/, off, s33 offset:2508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v739*/, off, s33 offset:2512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v740*/, off, s33 offset:2516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v741*/, off, s33 offset:2520 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v742*/, off, s33 offset:2524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v743*/, off, s33 offset:2528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v744*/, off, s33 offset:2532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v745*/, off, s33 offset:2536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v746*/, off, s33 offset:2540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v747*/, off, s33 offset:2544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v748*/, off, s33 offset:2548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v749*/, off, s33 offset:2552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v750*/, off, s33 offset:2556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v751*/, off, s33 offset:2560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v752*/, off, s33 offset:2564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v753*/, off, s33 offset:2568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v754*/, off, s33 offset:2572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v755*/, off, s33 offset:2576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v756*/, off, s33 offset:2580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v757*/, off, s33 offset:2584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v758*/, off, s33 offset:2588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v759*/, off, s33 offset:2592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v760*/, off, s33 offset:2596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v761*/, off, s33 offset:2600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v762*/, off, s33 offset:2604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v763*/, off, s33 offset:2608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v764*/, off, s33 offset:2612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v765*/, off, s33 offset:2616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v766*/, off, s33 offset:2620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v767*/, off, s33 offset:2624 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v742*/, off, s33 offset:2524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v743*/, off, s33 offset:2528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v744*/, off, s33 offset:2532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v745*/, off, s33 offset:2536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v746*/, off, s33 offset:2540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v747*/, off, s33 offset:2544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v748*/, off, s33 offset:2548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v749*/, off, s33 offset:2552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v750*/, off, s33 offset:2556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v751*/, off, s33 offset:2560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v752*/, off, s33 offset:2564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v753*/, off, s33 offset:2568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v754*/, off, s33 offset:2572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v755*/, off, s33 offset:2576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v756*/, off, s33 offset:2580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v757*/, off, s33 offset:2584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v758*/, off, s33 offset:2588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v759*/, off, s33 offset:2592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v760*/, off, s33 offset:2596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v761*/, off, s33 offset:2600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v762*/, off, s33 offset:2604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v763*/, off, s33 offset:2608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v764*/, off, s33 offset:2612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v765*/, off, s33 offset:2616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v766*/, off, s33 offset:2620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v767*/, off, s33 offset:2624 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x80c0 ; msbs: dst=3 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v768*/, off, s33 offset:2628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v769*/, off, s33 offset:2632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v770*/, off, s33 offset:2636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v771*/, off, s33 offset:2640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v772*/, off, s33 offset:2644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v773*/, off, s33 offset:2648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v774*/, off, s33 offset:2652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v775*/, off, s33 offset:2656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v776*/, off, s33 offset:2660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v777*/, off, s33 offset:2664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v778*/, off, s33 offset:2668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v779*/, off, s33 offset:2672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v780*/, off, s33 offset:2676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v781*/, off, s33 offset:2680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v782*/, off, s33 offset:2684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v783*/, off, s33 offset:2688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v784*/, off, s33 offset:2692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v785*/, off, s33 offset:2696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v786*/, off, s33 offset:2700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v787*/, off, s33 offset:2704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v788*/, off, s33 offset:2708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v789*/, off, s33 offset:2712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v790*/, off, s33 offset:2716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v791*/, off, s33 offset:2720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v792*/, off, s33 offset:2724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v793*/, off, s33 offset:2728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v794*/, off, s33 offset:2732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v795*/, off, s33 offset:2736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v796*/, off, s33 offset:2740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v797*/, off, s33 offset:2744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v798*/, off, s33 offset:2748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v799*/, off, s33 offset:2752 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v800*/, off, s33 offset:2756 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v801*/, off, s33 offset:2760 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v802*/, off, s33 offset:2764 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v803*/, off, s33 offset:2768 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v804*/, off, s33 offset:2772 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v768*/, off, s33 offset:2628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v769*/, off, s33 offset:2632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v770*/, off, s33 offset:2636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v771*/, off, s33 offset:2640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v772*/, off, s33 offset:2644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v773*/, off, s33 offset:2648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v774*/, off, s33 offset:2652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v775*/, off, s33 offset:2656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v776*/, off, s33 offset:2660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v777*/, off, s33 offset:2664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v778*/, off, s33 offset:2668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v779*/, off, s33 offset:2672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v780*/, off, s33 offset:2676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v781*/, off, s33 offset:2680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v782*/, off, s33 offset:2684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v783*/, off, s33 offset:2688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v784*/, off, s33 offset:2692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v785*/, off, s33 offset:2696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v786*/, off, s33 offset:2700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v787*/, off, s33 offset:2704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v788*/, off, s33 offset:2708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v789*/, off, s33 offset:2712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v790*/, off, s33 offset:2716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v791*/, off, s33 offset:2720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v792*/, off, s33 offset:2724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v793*/, off, s33 offset:2728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v794*/, off, s33 offset:2732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v795*/, off, s33 offset:2736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v796*/, off, s33 offset:2740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v797*/, off, s33 offset:2744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v798*/, off, s33 offset:2748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v799*/, off, s33 offset:2752 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v800*/, off, s33 offset:2756 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v801*/, off, s33 offset:2760 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v802*/, off, s33 offset:2764 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v803*/, off, s33 offset:2768 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v804*/, off, s33 offset:2772 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v805*/, off, s33 offset:2776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v806*/, off, s33 offset:2780 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v807*/, off, s33 offset:2784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v808*/, off, s33 offset:2788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v809*/, off, s33 offset:2792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v810*/, off, s33 offset:2796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v811*/, off, s33 offset:2800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v812*/, off, s33 offset:2804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v813*/, off, s33 offset:2808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v814*/, off, s33 offset:2812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v815*/, off, s33 offset:2816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v816*/, off, s33 offset:2820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v817*/, off, s33 offset:2824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v818*/, off, s33 offset:2828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v819*/, off, s33 offset:2832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v820*/, off, s33 offset:2836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v821*/, off, s33 offset:2840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v822*/, off, s33 offset:2844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v823*/, off, s33 offset:2848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v824*/, off, s33 offset:2852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v825*/, off, s33 offset:2856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v826*/, off, s33 offset:2860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v827*/, off, s33 offset:2864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v828*/, off, s33 offset:2868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v829*/, off, s33 offset:2872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v830*/, off, s33 offset:2876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v831*/, off, s33 offset:2880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v832*/, off, s33 offset:2884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v833*/, off, s33 offset:2888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v834*/, off, s33 offset:2892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v835*/, off, s33 offset:2896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v836*/, off, s33 offset:2900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v837*/, off, s33 offset:2904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v838*/, off, s33 offset:2908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v839*/, off, s33 offset:2912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v840*/, off, s33 offset:2916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v841*/, off, s33 offset:2920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v842*/, off, s33 offset:2924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v843*/, off, s33 offset:2928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v844*/, off, s33 offset:2932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v845*/, off, s33 offset:2936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v846*/, off, s33 offset:2940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v847*/, off, s33 offset:2944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v848*/, off, s33 offset:2948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v849*/, off, s33 offset:2952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v850*/, off, s33 offset:2956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v851*/, off, s33 offset:2960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v852*/, off, s33 offset:2964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v853*/, off, s33 offset:2968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v854*/, off, s33 offset:2972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v855*/, off, s33 offset:2976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v856*/, off, s33 offset:2980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v857*/, off, s33 offset:2984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v858*/, off, s33 offset:2988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v859*/, off, s33 offset:2992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v860*/, off, s33 offset:2996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v861*/, off, s33 offset:3000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v862*/, off, s33 offset:3004 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v863*/, off, s33 offset:3008 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v864*/, off, s33 offset:3012 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v865*/, off, s33 offset:3016 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v866*/, off, s33 offset:3020 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v867*/, off, s33 offset:3024 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v805*/, off, s33 offset:2776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v806*/, off, s33 offset:2780 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v807*/, off, s33 offset:2784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v808*/, off, s33 offset:2788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v809*/, off, s33 offset:2792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v810*/, off, s33 offset:2796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v811*/, off, s33 offset:2800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v812*/, off, s33 offset:2804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v813*/, off, s33 offset:2808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v814*/, off, s33 offset:2812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v815*/, off, s33 offset:2816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v816*/, off, s33 offset:2820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v817*/, off, s33 offset:2824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v818*/, off, s33 offset:2828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v819*/, off, s33 offset:2832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v820*/, off, s33 offset:2836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v821*/, off, s33 offset:2840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v822*/, off, s33 offset:2844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v823*/, off, s33 offset:2848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v824*/, off, s33 offset:2852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v825*/, off, s33 offset:2856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v826*/, off, s33 offset:2860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v827*/, off, s33 offset:2864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v828*/, off, s33 offset:2868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v829*/, off, s33 offset:2872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v830*/, off, s33 offset:2876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v831*/, off, s33 offset:2880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v832*/, off, s33 offset:2884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v833*/, off, s33 offset:2888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v834*/, off, s33 offset:2892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v835*/, off, s33 offset:2896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v836*/, off, s33 offset:2900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v837*/, off, s33 offset:2904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v838*/, off, s33 offset:2908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v839*/, off, s33 offset:2912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v840*/, off, s33 offset:2916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v841*/, off, s33 offset:2920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v842*/, off, s33 offset:2924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v843*/, off, s33 offset:2928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v844*/, off, s33 offset:2932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v845*/, off, s33 offset:2936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v846*/, off, s33 offset:2940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v847*/, off, s33 offset:2944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v848*/, off, s33 offset:2948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v849*/, off, s33 offset:2952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v850*/, off, s33 offset:2956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v851*/, off, s33 offset:2960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v852*/, off, s33 offset:2964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v853*/, off, s33 offset:2968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v854*/, off, s33 offset:2972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v855*/, off, s33 offset:2976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v856*/, off, s33 offset:2980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v857*/, off, s33 offset:2984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v858*/, off, s33 offset:2988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v859*/, off, s33 offset:2992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v860*/, off, s33 offset:2996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v861*/, off, s33 offset:3000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v862*/, off, s33 offset:3004 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v863*/, off, s33 offset:3008 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v864*/, off, s33 offset:3012 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v865*/, off, s33 offset:3016 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v866*/, off, s33 offset:3020 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v867*/, off, s33 offset:3024 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v868*/, off, s33 offset:3028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v869*/, off, s33 offset:3032 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v870*/, off, s33 offset:3036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v871*/, off, s33 offset:3040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v872*/, off, s33 offset:3044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v873*/, off, s33 offset:3048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v874*/, off, s33 offset:3052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v875*/, off, s33 offset:3056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v876*/, off, s33 offset:3060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v877*/, off, s33 offset:3064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v878*/, off, s33 offset:3068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v879*/, off, s33 offset:3072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v880*/, off, s33 offset:3076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v881*/, off, s33 offset:3080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v882*/, off, s33 offset:3084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v883*/, off, s33 offset:3088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v884*/, off, s33 offset:3092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v885*/, off, s33 offset:3096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v886*/, off, s33 offset:3100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v887*/, off, s33 offset:3104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v888*/, off, s33 offset:3108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v889*/, off, s33 offset:3112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v890*/, off, s33 offset:3116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v891*/, off, s33 offset:3120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v892*/, off, s33 offset:3124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v893*/, off, s33 offset:3128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v894*/, off, s33 offset:3132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v895*/, off, s33 offset:3136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v896*/, off, s33 offset:3140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v897*/, off, s33 offset:3144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v898*/, off, s33 offset:3148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v899*/, off, s33 offset:3152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v900*/, off, s33 offset:3156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v901*/, off, s33 offset:3160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v902*/, off, s33 offset:3164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v903*/, off, s33 offset:3168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v904*/, off, s33 offset:3172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v905*/, off, s33 offset:3176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v906*/, off, s33 offset:3180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v907*/, off, s33 offset:3184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v908*/, off, s33 offset:3188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v909*/, off, s33 offset:3192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v910*/, off, s33 offset:3196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v911*/, off, s33 offset:3200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v912*/, off, s33 offset:3204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v913*/, off, s33 offset:3208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v914*/, off, s33 offset:3212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v915*/, off, s33 offset:3216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v916*/, off, s33 offset:3220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v917*/, off, s33 offset:3224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v918*/, off, s33 offset:3228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v919*/, off, s33 offset:3232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v920*/, off, s33 offset:3236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v921*/, off, s33 offset:3240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v922*/, off, s33 offset:3244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v923*/, off, s33 offset:3248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v924*/, off, s33 offset:3252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v925*/, off, s33 offset:3256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v926*/, off, s33 offset:3260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v927*/, off, s33 offset:3264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v928*/, off, s33 offset:3268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v929*/, off, s33 offset:3272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v930*/, off, s33 offset:3276 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v868*/, off, s33 offset:3028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v869*/, off, s33 offset:3032 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v870*/, off, s33 offset:3036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v871*/, off, s33 offset:3040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v872*/, off, s33 offset:3044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v873*/, off, s33 offset:3048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v874*/, off, s33 offset:3052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v875*/, off, s33 offset:3056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v876*/, off, s33 offset:3060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v877*/, off, s33 offset:3064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v878*/, off, s33 offset:3068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v879*/, off, s33 offset:3072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v880*/, off, s33 offset:3076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v881*/, off, s33 offset:3080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v882*/, off, s33 offset:3084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v883*/, off, s33 offset:3088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v884*/, off, s33 offset:3092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v885*/, off, s33 offset:3096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v886*/, off, s33 offset:3100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v887*/, off, s33 offset:3104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v888*/, off, s33 offset:3108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v889*/, off, s33 offset:3112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v890*/, off, s33 offset:3116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v891*/, off, s33 offset:3120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v892*/, off, s33 offset:3124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v893*/, off, s33 offset:3128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v894*/, off, s33 offset:3132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v895*/, off, s33 offset:3136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v896*/, off, s33 offset:3140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v897*/, off, s33 offset:3144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v898*/, off, s33 offset:3148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v899*/, off, s33 offset:3152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v900*/, off, s33 offset:3156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v901*/, off, s33 offset:3160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v902*/, off, s33 offset:3164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v903*/, off, s33 offset:3168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v904*/, off, s33 offset:3172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v905*/, off, s33 offset:3176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v906*/, off, s33 offset:3180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v907*/, off, s33 offset:3184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v908*/, off, s33 offset:3188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v909*/, off, s33 offset:3192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v910*/, off, s33 offset:3196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v911*/, off, s33 offset:3200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v912*/, off, s33 offset:3204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v913*/, off, s33 offset:3208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v914*/, off, s33 offset:3212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v915*/, off, s33 offset:3216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v916*/, off, s33 offset:3220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v917*/, off, s33 offset:3224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v918*/, off, s33 offset:3228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v919*/, off, s33 offset:3232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v920*/, off, s33 offset:3236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v921*/, off, s33 offset:3240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v922*/, off, s33 offset:3244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v923*/, off, s33 offset:3248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v924*/, off, s33 offset:3252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v925*/, off, s33 offset:3256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v926*/, off, s33 offset:3260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v927*/, off, s33 offset:3264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v928*/, off, s33 offset:3268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v929*/, off, s33 offset:3272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v930*/, off, s33 offset:3276 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v931*/, off, s33 offset:3280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v932*/, off, s33 offset:3284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v933*/, off, s33 offset:3288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v934*/, off, s33 offset:3292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v935*/, off, s33 offset:3296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v936*/, off, s33 offset:3300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v937*/, off, s33 offset:3304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v938*/, off, s33 offset:3308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v939*/, off, s33 offset:3312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v940*/, off, s33 offset:3316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v941*/, off, s33 offset:3320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v942*/, off, s33 offset:3324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v943*/, off, s33 offset:3328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v944*/, off, s33 offset:3332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v945*/, off, s33 offset:3336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v946*/, off, s33 offset:3340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v947*/, off, s33 offset:3344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v948*/, off, s33 offset:3348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v949*/, off, s33 offset:3352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v950*/, off, s33 offset:3356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v951*/, off, s33 offset:3360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v952*/, off, s33 offset:3364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v953*/, off, s33 offset:3368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v954*/, off, s33 offset:3372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v955*/, off, s33 offset:3376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v956*/, off, s33 offset:3380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v957*/, off, s33 offset:3384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v958*/, off, s33 offset:3388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v959*/, off, s33 offset:3392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v960*/, off, s33 offset:3396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v961*/, off, s33 offset:3400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v962*/, off, s33 offset:3404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v963*/, off, s33 offset:3408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v964*/, off, s33 offset:3412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v965*/, off, s33 offset:3416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v966*/, off, s33 offset:3420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v967*/, off, s33 offset:3424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v968*/, off, s33 offset:3428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v969*/, off, s33 offset:3432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v970*/, off, s33 offset:3436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v971*/, off, s33 offset:3440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v972*/, off, s33 offset:3444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v973*/, off, s33 offset:3448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v974*/, off, s33 offset:3452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v975*/, off, s33 offset:3456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v976*/, off, s33 offset:3460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v977*/, off, s33 offset:3464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v978*/, off, s33 offset:3468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v979*/, off, s33 offset:3472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v980*/, off, s33 offset:3476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v981*/, off, s33 offset:3480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v982*/, off, s33 offset:3484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v983*/, off, s33 offset:3488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v984*/, off, s33 offset:3492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v985*/, off, s33 offset:3496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v986*/, off, s33 offset:3500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v987*/, off, s33 offset:3504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v988*/, off, s33 offset:3508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v989*/, off, s33 offset:3512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v990*/, off, s33 offset:3516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v991*/, off, s33 offset:3520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v992*/, off, s33 offset:3524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v993*/, off, s33 offset:3528 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v931*/, off, s33 offset:3280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v932*/, off, s33 offset:3284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v933*/, off, s33 offset:3288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v934*/, off, s33 offset:3292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v935*/, off, s33 offset:3296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v936*/, off, s33 offset:3300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v937*/, off, s33 offset:3304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v938*/, off, s33 offset:3308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v939*/, off, s33 offset:3312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v940*/, off, s33 offset:3316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v941*/, off, s33 offset:3320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v942*/, off, s33 offset:3324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v943*/, off, s33 offset:3328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v944*/, off, s33 offset:3332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v945*/, off, s33 offset:3336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v946*/, off, s33 offset:3340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v947*/, off, s33 offset:3344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v948*/, off, s33 offset:3348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v949*/, off, s33 offset:3352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v950*/, off, s33 offset:3356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v951*/, off, s33 offset:3360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v952*/, off, s33 offset:3364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v953*/, off, s33 offset:3368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v954*/, off, s33 offset:3372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v955*/, off, s33 offset:3376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v956*/, off, s33 offset:3380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v957*/, off, s33 offset:3384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v958*/, off, s33 offset:3388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v959*/, off, s33 offset:3392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v960*/, off, s33 offset:3396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v961*/, off, s33 offset:3400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v962*/, off, s33 offset:3404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v963*/, off, s33 offset:3408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v964*/, off, s33 offset:3412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v965*/, off, s33 offset:3416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v966*/, off, s33 offset:3420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v967*/, off, s33 offset:3424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v968*/, off, s33 offset:3428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v969*/, off, s33 offset:3432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v970*/, off, s33 offset:3436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v971*/, off, s33 offset:3440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v972*/, off, s33 offset:3444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v973*/, off, s33 offset:3448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v974*/, off, s33 offset:3452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v975*/, off, s33 offset:3456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v976*/, off, s33 offset:3460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v977*/, off, s33 offset:3464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v978*/, off, s33 offset:3468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v979*/, off, s33 offset:3472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v980*/, off, s33 offset:3476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v981*/, off, s33 offset:3480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v982*/, off, s33 offset:3484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v983*/, off, s33 offset:3488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v984*/, off, s33 offset:3492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v985*/, off, s33 offset:3496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v986*/, off, s33 offset:3500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v987*/, off, s33 offset:3504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v988*/, off, s33 offset:3508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v989*/, off, s33 offset:3512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v990*/, off, s33 offset:3516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v991*/, off, s33 offset:3520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v992*/, off, s33 offset:3524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v993*/, off, s33 offset:3528 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; 120-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v994*/, off, s33 offset:3532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v995*/, off, s33 offset:3536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v996*/, off, s33 offset:3540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v997*/, off, s33 offset:3544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v998*/, off, s33 offset:3548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v999*/, off, s33 offset:3552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v1000*/, off, s33 offset:3556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v1001*/, off, s33 offset:3560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v1002*/, off, s33 offset:3564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v1003*/, off, s33 offset:3568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v1004*/, off, s33 offset:3572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v1005*/, off, s33 offset:3576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v1006*/, off, s33 offset:3580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v1007*/, off, s33 offset:3584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v1008*/, off, s33 offset:3588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v1009*/, off, s33 offset:3592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v1010*/, off, s33 offset:3596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v1011*/, off, s33 offset:3600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v1012*/, off, s33 offset:3604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v1013*/, off, s33 offset:3608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v1014*/, off, s33 offset:3612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v1015*/, off, s33 offset:3616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v1016*/, off, s33 offset:3620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v1017*/, off, s33 offset:3624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v1018*/, off, s33 offset:3628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v1019*/, off, s33 offset:3632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v1020*/, off, s33 offset:3636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v1021*/, off, s33 offset:3640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v1022*/, off, s33 offset:3644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v1023*/, off, s33 offset:3648 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v994*/, off, s33 offset:3532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v995*/, off, s33 offset:3536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v996*/, off, s33 offset:3540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v997*/, off, s33 offset:3544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v998*/, off, s33 offset:3548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v999*/, off, s33 offset:3552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v1000*/, off, s33 offset:3556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v1001*/, off, s33 offset:3560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v1002*/, off, s33 offset:3564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v1003*/, off, s33 offset:3568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v1004*/, off, s33 offset:3572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v1005*/, off, s33 offset:3576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v1006*/, off, s33 offset:3580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v1007*/, off, s33 offset:3584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v1008*/, off, s33 offset:3588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v1009*/, off, s33 offset:3592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v1010*/, off, s33 offset:3596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v1011*/, off, s33 offset:3600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v1012*/, off, s33 offset:3604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v1013*/, off, s33 offset:3608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v1014*/, off, s33 offset:3612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v1015*/, off, s33 offset:3616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v1016*/, off, s33 offset:3620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v1017*/, off, s33 offset:3624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v1018*/, off, s33 offset:3628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v1019*/, off, s33 offset:3632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v1020*/, off, s33 offset:3636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v1021*/, off, s33 offset:3640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v1022*/, off, s33 offset:3644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v1023*/, off, s33 offset:3648 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, s4 ; GFX1250-DAGISEL-NEXT: s_mov_b32 s33, s0 @@ -5939,935 +5939,935 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ ; GFX1250-DAGISEL-NEXT: s_wait_kmcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s32 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s32 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s32 offset:12 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s32 offset:16 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s32 offset:20 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s32 offset:24 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s32 offset:28 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s32 offset:32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s32 offset:36 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s32 offset:40 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s32 offset:44 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s32 offset:48 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s32 offset:52 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s32 offset:56 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s32 offset:60 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s32 offset:64 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s32 offset:68 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s32 offset:72 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s32 offset:76 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s32 offset:80 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s32 offset:84 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s32 offset:88 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s32 offset:92 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s32 offset:96 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s32 offset:100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s32 offset:104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s32 offset:108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s32 offset:112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s32 offset:116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s32 offset:120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s32 offset:124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s32 offset:128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s32 offset:132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s32 offset:136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s32 offset:140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s32 offset:144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s32 offset:148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s32 offset:152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s32 offset:156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s32 offset:160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s32 offset:164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s32 offset:168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s32 offset:172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s32 offset:176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s32 offset:180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s32 offset:184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s32 offset:188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s32 offset:192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s32 offset:196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s32 offset:200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s32 offset:204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s32 offset:208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s32 offset:212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s32 offset:216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s32 offset:220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s32 offset:224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s32 offset:228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s32 offset:232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s32 offset:236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s32 offset:240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s32 offset:244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s32 offset:248 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s32 offset:252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s32 offset:256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s32 offset:260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s32 offset:264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s32 offset:268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s32 offset:272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s32 offset:276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s32 offset:280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s32 offset:284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s32 offset:288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s32 offset:292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s32 offset:296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s32 offset:300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s32 offset:304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s32 offset:308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s32 offset:312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s32 offset:316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s32 offset:320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s32 offset:324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s32 offset:328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s32 offset:332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s32 offset:336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s32 offset:340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s32 offset:344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s32 offset:348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s32 offset:352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s32 offset:356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s32 offset:360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s32 offset:364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s32 offset:368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s32 offset:372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s32 offset:376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s32 offset:380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s32 offset:384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s32 offset:388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s32 offset:392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s32 offset:396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s32 offset:400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s32 offset:404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s32 offset:408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s32 offset:412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s32 offset:416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s32 offset:420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s32 offset:424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s32 offset:428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s32 offset:432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s32 offset:436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s32 offset:440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s32 offset:444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s32 offset:448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s32 offset:452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s32 offset:456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s32 offset:460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s32 offset:464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s32 offset:468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s32 offset:472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s32 offset:476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s32 offset:480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s32 offset:484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s32 offset:488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s32 offset:492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s32 offset:496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s32 offset:500 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s32 offset:504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s32 offset:508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s32 offset:512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s32 offset:516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s32 offset:520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s32 offset:524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s32 offset:528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s32 offset:532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s32 offset:536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s32 offset:540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s32 offset:544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s32 offset:548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s32 offset:552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s32 offset:556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s32 offset:560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s32 offset:564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s32 offset:568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s32 offset:572 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 4 ; msbs: dst=0 src0=0 src1=1 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s32 offset:576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s32 offset:580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s32 offset:584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s32 offset:588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s32 offset:592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s32 offset:596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s32 offset:600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s32 offset:604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s32 offset:608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s32 offset:612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s32 offset:616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s32 offset:620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s32 offset:624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s32 offset:628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s32 offset:632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s32 offset:636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s32 offset:640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s32 offset:644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s32 offset:648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s32 offset:652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s32 offset:656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s32 offset:660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s32 offset:664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s32 offset:668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s32 offset:672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s32 offset:676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s32 offset:680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s32 offset:684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s32 offset:688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s32 offset:692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s32 offset:696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s32 offset:700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s32 offset:704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s32 offset:708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s32 offset:712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s32 offset:716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s32 offset:720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s32 offset:724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s32 offset:728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s32 offset:732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s32 offset:736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s32 offset:740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s32 offset:744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s32 offset:748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s32 offset:752 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s32 offset:576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s32 offset:580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s32 offset:584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s32 offset:588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s32 offset:592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s32 offset:596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s32 offset:600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s32 offset:604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s32 offset:608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s32 offset:612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s32 offset:616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s32 offset:620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s32 offset:624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s32 offset:628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s32 offset:632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s32 offset:636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s32 offset:640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s32 offset:644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s32 offset:648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s32 offset:652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s32 offset:656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s32 offset:660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s32 offset:664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s32 offset:668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s32 offset:672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s32 offset:676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s32 offset:680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s32 offset:684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s32 offset:688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s32 offset:692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s32 offset:696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s32 offset:700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s32 offset:704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s32 offset:708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s32 offset:712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s32 offset:716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s32 offset:720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s32 offset:724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s32 offset:728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s32 offset:732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s32 offset:736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s32 offset:740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s32 offset:744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s32 offset:748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s32 offset:752 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s32 offset:756 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s32 offset:760 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s32 offset:764 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s32 offset:768 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s32 offset:772 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s32 offset:776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s32 offset:780 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s32 offset:784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s32 offset:788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s32 offset:792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s32 offset:796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s32 offset:800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s32 offset:804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s32 offset:808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s32 offset:812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s32 offset:816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s32 offset:820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s32 offset:824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s32 offset:828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s32 offset:832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s32 offset:836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s32 offset:840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s32 offset:844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s32 offset:848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s32 offset:852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s32 offset:856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s32 offset:860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s32 offset:864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s32 offset:868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s32 offset:872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s32 offset:876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s32 offset:880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s32 offset:884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s32 offset:888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s32 offset:892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s32 offset:896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s32 offset:900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s32 offset:904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s32 offset:908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s32 offset:912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s32 offset:916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s32 offset:920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s32 offset:924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s32 offset:928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s32 offset:932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s32 offset:936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s32 offset:940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s32 offset:944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s32 offset:948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s32 offset:952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s32 offset:956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s32 offset:960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s32 offset:964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s32 offset:968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s32 offset:972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s32 offset:976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s32 offset:980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s32 offset:984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s32 offset:988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s32 offset:992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s32 offset:996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s32 offset:1000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s32 offset:1004 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s32 offset:756 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s32 offset:760 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s32 offset:764 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s32 offset:768 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s32 offset:772 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s32 offset:776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s32 offset:780 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s32 offset:784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s32 offset:788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s32 offset:792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s32 offset:796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s32 offset:800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s32 offset:804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s32 offset:808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s32 offset:812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s32 offset:816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s32 offset:820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s32 offset:824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s32 offset:828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s32 offset:832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s32 offset:836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s32 offset:840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s32 offset:844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s32 offset:848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s32 offset:852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s32 offset:856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s32 offset:860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s32 offset:864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s32 offset:868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s32 offset:872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s32 offset:876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s32 offset:880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s32 offset:884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s32 offset:888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s32 offset:892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s32 offset:896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s32 offset:900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s32 offset:904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s32 offset:908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s32 offset:912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s32 offset:916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s32 offset:920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s32 offset:924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s32 offset:928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s32 offset:932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s32 offset:936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s32 offset:940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s32 offset:944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s32 offset:948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s32 offset:952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s32 offset:956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s32 offset:960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s32 offset:964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s32 offset:968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s32 offset:972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s32 offset:976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s32 offset:980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s32 offset:984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s32 offset:988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s32 offset:992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s32 offset:996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s32 offset:1000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s32 offset:1004 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s32 offset:1008 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s32 offset:1012 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s32 offset:1016 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s32 offset:1020 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s32 offset:1024 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s32 offset:1028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s32 offset:1032 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s32 offset:1036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s32 offset:1040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s32 offset:1044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s32 offset:1048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s32 offset:1052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s32 offset:1056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s32 offset:1060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s32 offset:1064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s32 offset:1068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s32 offset:1072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s32 offset:1076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s32 offset:1080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s32 offset:1084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s32 offset:1088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s32 offset:1092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s32 offset:1096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s32 offset:1100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s32 offset:1104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s32 offset:1108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s32 offset:1112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s32 offset:1116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s32 offset:1120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s32 offset:1124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s32 offset:1128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s32 offset:1132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s32 offset:1136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s32 offset:1140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s32 offset:1144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s32 offset:1148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s32 offset:1152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s32 offset:1156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s32 offset:1160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s32 offset:1164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s32 offset:1168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s32 offset:1172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s32 offset:1176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s32 offset:1180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s32 offset:1184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s32 offset:1188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s32 offset:1192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s32 offset:1196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s32 offset:1200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s32 offset:1204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s32 offset:1208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s32 offset:1212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s32 offset:1216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s32 offset:1220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s32 offset:1224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s32 offset:1228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s32 offset:1232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s32 offset:1236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s32 offset:1240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s32 offset:1244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s32 offset:1248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s32 offset:1252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s32 offset:1256 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s32 offset:1008 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s32 offset:1012 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s32 offset:1016 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s32 offset:1020 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s32 offset:1024 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s32 offset:1028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s32 offset:1032 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s32 offset:1036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s32 offset:1040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s32 offset:1044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s32 offset:1048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s32 offset:1052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s32 offset:1056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s32 offset:1060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s32 offset:1064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s32 offset:1068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s32 offset:1072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s32 offset:1076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s32 offset:1080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s32 offset:1084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s32 offset:1088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s32 offset:1092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s32 offset:1096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s32 offset:1100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s32 offset:1104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s32 offset:1108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s32 offset:1112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s32 offset:1116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s32 offset:1120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s32 offset:1124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s32 offset:1128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s32 offset:1132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s32 offset:1136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s32 offset:1140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s32 offset:1144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s32 offset:1148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s32 offset:1152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s32 offset:1156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s32 offset:1160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s32 offset:1164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s32 offset:1168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s32 offset:1172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s32 offset:1176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s32 offset:1180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s32 offset:1184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s32 offset:1188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s32 offset:1192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s32 offset:1196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s32 offset:1200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s32 offset:1204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s32 offset:1208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s32 offset:1212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s32 offset:1216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s32 offset:1220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s32 offset:1224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s32 offset:1228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s32 offset:1232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s32 offset:1236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s32 offset:1240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s32 offset:1244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s32 offset:1248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s32 offset:1252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s32 offset:1256 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s32 offset:1260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s32 offset:1264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s32 offset:1268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s32 offset:1272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s32 offset:1276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s32 offset:1280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s32 offset:1284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s32 offset:1288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s32 offset:1292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s32 offset:1296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s32 offset:1300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s32 offset:1304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s32 offset:1308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s32 offset:1312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s32 offset:1316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s32 offset:1320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s32 offset:1324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s32 offset:1328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s32 offset:1332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s32 offset:1336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s32 offset:1340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s32 offset:1344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s32 offset:1348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s32 offset:1352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s32 offset:1356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s32 offset:1360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s32 offset:1364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s32 offset:1368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s32 offset:1372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s32 offset:1376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s32 offset:1380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s32 offset:1384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s32 offset:1388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s32 offset:1392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s32 offset:1396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s32 offset:1400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s32 offset:1404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s32 offset:1408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s32 offset:1412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s32 offset:1416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s32 offset:1420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s32 offset:1424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s32 offset:1428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s32 offset:1432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s32 offset:1436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s32 offset:1440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s32 offset:1444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s32 offset:1448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s32 offset:1452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s32 offset:1456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s32 offset:1460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s32 offset:1464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s32 offset:1468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s32 offset:1472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s32 offset:1476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s32 offset:1480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s32 offset:1484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s32 offset:1488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s32 offset:1492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s32 offset:1496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s32 offset:1500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s32 offset:1504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s32 offset:1508 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s32 offset:1260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s32 offset:1264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s32 offset:1268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s32 offset:1272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s32 offset:1276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s32 offset:1280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s32 offset:1284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s32 offset:1288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s32 offset:1292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s32 offset:1296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s32 offset:1300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s32 offset:1304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s32 offset:1308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s32 offset:1312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s32 offset:1316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s32 offset:1320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s32 offset:1324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s32 offset:1328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s32 offset:1332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s32 offset:1336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s32 offset:1340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s32 offset:1344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s32 offset:1348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s32 offset:1352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s32 offset:1356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s32 offset:1360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s32 offset:1364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s32 offset:1368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s32 offset:1372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s32 offset:1376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s32 offset:1380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s32 offset:1384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s32 offset:1388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s32 offset:1392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s32 offset:1396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s32 offset:1400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s32 offset:1404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s32 offset:1408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s32 offset:1412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s32 offset:1416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s32 offset:1420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s32 offset:1424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s32 offset:1428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s32 offset:1432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s32 offset:1436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s32 offset:1440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s32 offset:1444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s32 offset:1448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s32 offset:1452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s32 offset:1456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s32 offset:1460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s32 offset:1464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s32 offset:1468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s32 offset:1472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s32 offset:1476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s32 offset:1480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s32 offset:1484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s32 offset:1488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s32 offset:1492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s32 offset:1496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s32 offset:1500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s32 offset:1504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s32 offset:1508 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s32 offset:1512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s32 offset:1516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s32 offset:1520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s32 offset:1524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s32 offset:1528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s32 offset:1532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s32 offset:1536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s32 offset:1540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s32 offset:1544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s32 offset:1548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s32 offset:1552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s32 offset:1556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s32 offset:1560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s32 offset:1564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s32 offset:1568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s32 offset:1572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s32 offset:1576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s32 offset:1580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s32 offset:1584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s32 offset:1588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s32 offset:1592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s32 offset:1596 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s32 offset:1512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s32 offset:1516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s32 offset:1520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s32 offset:1524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s32 offset:1528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s32 offset:1532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s32 offset:1536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s32 offset:1540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s32 offset:1544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s32 offset:1548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s32 offset:1552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s32 offset:1556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s32 offset:1560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s32 offset:1564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s32 offset:1568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s32 offset:1572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s32 offset:1576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s32 offset:1580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s32 offset:1584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s32 offset:1588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s32 offset:1592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s32 offset:1596 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x408 ; msbs: dst=0 src0=0 src1=2 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s32 offset:1600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s32 offset:1604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s32 offset:1608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s32 offset:1612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s32 offset:1616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s32 offset:1620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s32 offset:1624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s32 offset:1628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s32 offset:1632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s32 offset:1636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s32 offset:1640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s32 offset:1644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s32 offset:1648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s32 offset:1652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s32 offset:1656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s32 offset:1660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s32 offset:1664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s32 offset:1668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s32 offset:1672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s32 offset:1676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s32 offset:1680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s32 offset:1684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s32 offset:1688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s32 offset:1692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s32 offset:1696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s32 offset:1700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s32 offset:1704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s32 offset:1708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s32 offset:1712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s32 offset:1716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s32 offset:1720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s32 offset:1724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s32 offset:1728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s32 offset:1732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s32 offset:1736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s32 offset:1740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s32 offset:1744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s32 offset:1748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s32 offset:1752 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s32 offset:1756 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s32 offset:1760 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s32 offset:1600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s32 offset:1604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s32 offset:1608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s32 offset:1612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s32 offset:1616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s32 offset:1620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s32 offset:1624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s32 offset:1628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s32 offset:1632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s32 offset:1636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s32 offset:1640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s32 offset:1644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s32 offset:1648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s32 offset:1652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s32 offset:1656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s32 offset:1660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s32 offset:1664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s32 offset:1668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s32 offset:1672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s32 offset:1676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s32 offset:1680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s32 offset:1684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s32 offset:1688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s32 offset:1692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s32 offset:1696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s32 offset:1700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s32 offset:1704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s32 offset:1708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s32 offset:1712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s32 offset:1716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s32 offset:1720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s32 offset:1724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s32 offset:1728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s32 offset:1732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s32 offset:1736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s32 offset:1740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s32 offset:1744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s32 offset:1748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s32 offset:1752 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s32 offset:1756 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s32 offset:1760 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s32 offset:1764 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s32 offset:1768 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s32 offset:1772 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s32 offset:1776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s32 offset:1780 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s32 offset:1784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s32 offset:1788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s32 offset:1792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s32 offset:1796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s32 offset:1800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s32 offset:1804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s32 offset:1808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s32 offset:1812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s32 offset:1816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s32 offset:1820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s32 offset:1824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s32 offset:1828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s32 offset:1832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s32 offset:1836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s32 offset:1840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s32 offset:1844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s32 offset:1848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s32 offset:1852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s32 offset:1856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s32 offset:1860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s32 offset:1864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s32 offset:1868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s32 offset:1872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s32 offset:1876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s32 offset:1880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s32 offset:1884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s32 offset:1888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s32 offset:1892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s32 offset:1896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s32 offset:1900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s32 offset:1904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s32 offset:1908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s32 offset:1912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s32 offset:1916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s32 offset:1920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s32 offset:1924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s32 offset:1928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s32 offset:1932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s32 offset:1936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s32 offset:1940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s32 offset:1944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s32 offset:1948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s32 offset:1952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s32 offset:1956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s32 offset:1960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s32 offset:1964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s32 offset:1968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s32 offset:1972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s32 offset:1976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s32 offset:1980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s32 offset:1984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s32 offset:1988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s32 offset:1992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s32 offset:1996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s32 offset:2000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s32 offset:2004 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s32 offset:2008 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s32 offset:2012 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s32 offset:1764 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s32 offset:1768 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s32 offset:1772 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s32 offset:1776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s32 offset:1780 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s32 offset:1784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s32 offset:1788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s32 offset:1792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s32 offset:1796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s32 offset:1800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s32 offset:1804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s32 offset:1808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s32 offset:1812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s32 offset:1816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s32 offset:1820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s32 offset:1824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s32 offset:1828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s32 offset:1832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s32 offset:1836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s32 offset:1840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s32 offset:1844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s32 offset:1848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s32 offset:1852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s32 offset:1856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s32 offset:1860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s32 offset:1864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s32 offset:1868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s32 offset:1872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s32 offset:1876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s32 offset:1880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s32 offset:1884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s32 offset:1888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s32 offset:1892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s32 offset:1896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s32 offset:1900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s32 offset:1904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s32 offset:1908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s32 offset:1912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s32 offset:1916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s32 offset:1920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s32 offset:1924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s32 offset:1928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s32 offset:1932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s32 offset:1936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s32 offset:1940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s32 offset:1944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s32 offset:1948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s32 offset:1952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s32 offset:1956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s32 offset:1960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s32 offset:1964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s32 offset:1968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s32 offset:1972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s32 offset:1976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s32 offset:1980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s32 offset:1984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s32 offset:1988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s32 offset:1992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s32 offset:1996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s32 offset:2000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s32 offset:2004 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s32 offset:2008 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s32 offset:2012 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s32 offset:2016 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s32 offset:2020 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s32 offset:2024 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s32 offset:2028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s32 offset:2032 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s32 offset:2036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s32 offset:2040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s32 offset:2044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s32 offset:2048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s32 offset:2052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s32 offset:2056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s32 offset:2060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s32 offset:2064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s32 offset:2068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s32 offset:2072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s32 offset:2076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s32 offset:2080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s32 offset:2084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s32 offset:2088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s32 offset:2092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s32 offset:2096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s32 offset:2100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s32 offset:2104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s32 offset:2108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s32 offset:2112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s32 offset:2116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s32 offset:2120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s32 offset:2124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s32 offset:2128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s32 offset:2132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s32 offset:2136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s32 offset:2140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s32 offset:2144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s32 offset:2148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s32 offset:2152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s32 offset:2156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s32 offset:2160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s32 offset:2164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s32 offset:2168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s32 offset:2172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s32 offset:2176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s32 offset:2180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s32 offset:2184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s32 offset:2188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s32 offset:2192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s32 offset:2196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s32 offset:2200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s32 offset:2204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s32 offset:2208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s32 offset:2212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s32 offset:2216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s32 offset:2220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s32 offset:2224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s32 offset:2228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s32 offset:2232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s32 offset:2236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s32 offset:2240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s32 offset:2244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s32 offset:2248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s32 offset:2252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s32 offset:2256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s32 offset:2260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s32 offset:2264 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s32 offset:2016 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s32 offset:2020 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s32 offset:2024 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s32 offset:2028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s32 offset:2032 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s32 offset:2036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s32 offset:2040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s32 offset:2044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s32 offset:2048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s32 offset:2052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s32 offset:2056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s32 offset:2060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s32 offset:2064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s32 offset:2068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s32 offset:2072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s32 offset:2076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s32 offset:2080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s32 offset:2084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s32 offset:2088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s32 offset:2092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s32 offset:2096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s32 offset:2100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s32 offset:2104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s32 offset:2108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s32 offset:2112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s32 offset:2116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s32 offset:2120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s32 offset:2124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s32 offset:2128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s32 offset:2132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s32 offset:2136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s32 offset:2140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s32 offset:2144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s32 offset:2148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s32 offset:2152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s32 offset:2156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s32 offset:2160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s32 offset:2164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s32 offset:2168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s32 offset:2172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s32 offset:2176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s32 offset:2180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s32 offset:2184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s32 offset:2188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s32 offset:2192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s32 offset:2196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s32 offset:2200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s32 offset:2204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s32 offset:2208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s32 offset:2212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s32 offset:2216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s32 offset:2220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s32 offset:2224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s32 offset:2228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s32 offset:2232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s32 offset:2236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s32 offset:2240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s32 offset:2244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s32 offset:2248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s32 offset:2252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s32 offset:2256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s32 offset:2260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s32 offset:2264 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s32 offset:2268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s32 offset:2272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s32 offset:2276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s32 offset:2280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s32 offset:2284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s32 offset:2288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s32 offset:2292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s32 offset:2296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s32 offset:2300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s32 offset:2304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s32 offset:2308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s32 offset:2312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s32 offset:2316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s32 offset:2320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s32 offset:2324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s32 offset:2328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s32 offset:2332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s32 offset:2336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s32 offset:2340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s32 offset:2344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s32 offset:2348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s32 offset:2352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s32 offset:2356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s32 offset:2360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s32 offset:2364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s32 offset:2368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s32 offset:2372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s32 offset:2376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s32 offset:2380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s32 offset:2384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s32 offset:2388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s32 offset:2392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s32 offset:2396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s32 offset:2400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s32 offset:2404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s32 offset:2408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s32 offset:2412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s32 offset:2416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s32 offset:2420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s32 offset:2424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s32 offset:2428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s32 offset:2432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s32 offset:2436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s32 offset:2440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s32 offset:2444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s32 offset:2448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s32 offset:2452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s32 offset:2456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s32 offset:2460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s32 offset:2464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s32 offset:2468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s32 offset:2472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s32 offset:2476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s32 offset:2480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s32 offset:2484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s32 offset:2488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s32 offset:2492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s32 offset:2496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s32 offset:2500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s32 offset:2504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s32 offset:2508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s32 offset:2512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s32 offset:2516 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s32 offset:2268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s32 offset:2272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s32 offset:2276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s32 offset:2280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s32 offset:2284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s32 offset:2288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s32 offset:2292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s32 offset:2296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s32 offset:2300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s32 offset:2304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s32 offset:2308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s32 offset:2312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s32 offset:2316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s32 offset:2320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s32 offset:2324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s32 offset:2328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s32 offset:2332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s32 offset:2336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s32 offset:2340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s32 offset:2344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s32 offset:2348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s32 offset:2352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s32 offset:2356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s32 offset:2360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s32 offset:2364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s32 offset:2368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s32 offset:2372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s32 offset:2376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s32 offset:2380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s32 offset:2384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s32 offset:2388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s32 offset:2392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s32 offset:2396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s32 offset:2400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s32 offset:2404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s32 offset:2408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s32 offset:2412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s32 offset:2416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s32 offset:2420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s32 offset:2424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s32 offset:2428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s32 offset:2432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s32 offset:2436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s32 offset:2440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s32 offset:2444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s32 offset:2448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s32 offset:2452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s32 offset:2456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s32 offset:2460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s32 offset:2464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s32 offset:2468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s32 offset:2472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s32 offset:2476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s32 offset:2480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s32 offset:2484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s32 offset:2488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s32 offset:2492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s32 offset:2496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s32 offset:2500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s32 offset:2504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s32 offset:2508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s32 offset:2512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s32 offset:2516 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s32 offset:2520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s32 offset:2524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s32 offset:2528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s32 offset:2532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s32 offset:2536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s32 offset:2540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s32 offset:2544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s32 offset:2548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s32 offset:2552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s32 offset:2556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s32 offset:2560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s32 offset:2564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s32 offset:2568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s32 offset:2572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s32 offset:2576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s32 offset:2580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s32 offset:2584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s32 offset:2588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s32 offset:2592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s32 offset:2596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s32 offset:2600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s32 offset:2604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s32 offset:2608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s32 offset:2612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s32 offset:2616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s32 offset:2620 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s32 offset:2520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s32 offset:2524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s32 offset:2528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s32 offset:2532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s32 offset:2536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s32 offset:2540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s32 offset:2544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s32 offset:2548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s32 offset:2552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s32 offset:2556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s32 offset:2560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s32 offset:2564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s32 offset:2568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s32 offset:2572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s32 offset:2576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s32 offset:2580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s32 offset:2584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s32 offset:2588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s32 offset:2592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s32 offset:2596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s32 offset:2600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s32 offset:2604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s32 offset:2608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s32 offset:2612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s32 offset:2616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s32 offset:2620 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x80c ; msbs: dst=0 src0=0 src1=3 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s32 offset:2624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s32 offset:2628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s32 offset:2632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s32 offset:2636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s32 offset:2640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s32 offset:2644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s32 offset:2648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s32 offset:2652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s32 offset:2656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s32 offset:2660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s32 offset:2664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s32 offset:2668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s32 offset:2672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s32 offset:2676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s32 offset:2680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s32 offset:2684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s32 offset:2688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s32 offset:2692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s32 offset:2696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s32 offset:2700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s32 offset:2704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s32 offset:2708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s32 offset:2712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s32 offset:2716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s32 offset:2720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s32 offset:2724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s32 offset:2728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s32 offset:2732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s32 offset:2736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s32 offset:2740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s32 offset:2744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s32 offset:2748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s32 offset:2752 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s32 offset:2756 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s32 offset:2760 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s32 offset:2764 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s32 offset:2768 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s32 offset:2624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s32 offset:2628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s32 offset:2632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s32 offset:2636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s32 offset:2640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s32 offset:2644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s32 offset:2648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s32 offset:2652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s32 offset:2656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s32 offset:2660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s32 offset:2664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s32 offset:2668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s32 offset:2672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s32 offset:2676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s32 offset:2680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s32 offset:2684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s32 offset:2688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s32 offset:2692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s32 offset:2696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s32 offset:2700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s32 offset:2704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s32 offset:2708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s32 offset:2712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s32 offset:2716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s32 offset:2720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s32 offset:2724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s32 offset:2728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s32 offset:2732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s32 offset:2736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s32 offset:2740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s32 offset:2744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s32 offset:2748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s32 offset:2752 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s32 offset:2756 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s32 offset:2760 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s32 offset:2764 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s32 offset:2768 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s32 offset:2772 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s32 offset:2776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s32 offset:2780 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s32 offset:2784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s32 offset:2788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s32 offset:2792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s32 offset:2796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s32 offset:2800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s32 offset:2804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s32 offset:2808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s32 offset:2812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s32 offset:2816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s32 offset:2820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s32 offset:2824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s32 offset:2828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s32 offset:2832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s32 offset:2836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s32 offset:2840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s32 offset:2844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s32 offset:2848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s32 offset:2852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s32 offset:2856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s32 offset:2860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s32 offset:2864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s32 offset:2868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s32 offset:2872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s32 offset:2876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s32 offset:2880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s32 offset:2884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s32 offset:2888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s32 offset:2892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s32 offset:2896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s32 offset:2900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s32 offset:2904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s32 offset:2908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s32 offset:2912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s32 offset:2916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s32 offset:2920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s32 offset:2924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s32 offset:2928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s32 offset:2932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s32 offset:2936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s32 offset:2940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s32 offset:2944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s32 offset:2948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s32 offset:2952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s32 offset:2956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s32 offset:2960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s32 offset:2964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s32 offset:2968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s32 offset:2972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s32 offset:2976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s32 offset:2980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s32 offset:2984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s32 offset:2988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s32 offset:2992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s32 offset:2996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s32 offset:3000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s32 offset:3004 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s32 offset:3008 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s32 offset:3012 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s32 offset:3016 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s32 offset:3020 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s32 offset:2772 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s32 offset:2776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s32 offset:2780 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s32 offset:2784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s32 offset:2788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s32 offset:2792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s32 offset:2796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s32 offset:2800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s32 offset:2804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s32 offset:2808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s32 offset:2812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s32 offset:2816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s32 offset:2820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s32 offset:2824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s32 offset:2828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s32 offset:2832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s32 offset:2836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s32 offset:2840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s32 offset:2844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s32 offset:2848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s32 offset:2852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s32 offset:2856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s32 offset:2860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s32 offset:2864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s32 offset:2868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s32 offset:2872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s32 offset:2876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s32 offset:2880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s32 offset:2884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s32 offset:2888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s32 offset:2892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s32 offset:2896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s32 offset:2900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s32 offset:2904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s32 offset:2908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s32 offset:2912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s32 offset:2916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s32 offset:2920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s32 offset:2924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s32 offset:2928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s32 offset:2932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s32 offset:2936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s32 offset:2940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s32 offset:2944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s32 offset:2948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s32 offset:2952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s32 offset:2956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s32 offset:2960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s32 offset:2964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s32 offset:2968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s32 offset:2972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s32 offset:2976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s32 offset:2980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s32 offset:2984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s32 offset:2988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s32 offset:2992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s32 offset:2996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s32 offset:3000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s32 offset:3004 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s32 offset:3008 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s32 offset:3012 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s32 offset:3016 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s32 offset:3020 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s32 offset:3024 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s32 offset:3028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s32 offset:3032 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s32 offset:3036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s32 offset:3040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s32 offset:3044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s32 offset:3048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s32 offset:3052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s32 offset:3056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s32 offset:3060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s32 offset:3064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s32 offset:3068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s32 offset:3072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s32 offset:3076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s32 offset:3080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s32 offset:3084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s32 offset:3088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s32 offset:3092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s32 offset:3096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s32 offset:3100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s32 offset:3104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s32 offset:3108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s32 offset:3112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s32 offset:3116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s32 offset:3120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s32 offset:3124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s32 offset:3128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s32 offset:3132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s32 offset:3136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s32 offset:3140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s32 offset:3144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s32 offset:3148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s32 offset:3152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s32 offset:3156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s32 offset:3160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s32 offset:3164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s32 offset:3168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s32 offset:3172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s32 offset:3176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s32 offset:3180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s32 offset:3184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s32 offset:3188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s32 offset:3192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s32 offset:3196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s32 offset:3200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s32 offset:3204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s32 offset:3208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s32 offset:3212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s32 offset:3216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s32 offset:3220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s32 offset:3224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s32 offset:3228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s32 offset:3232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s32 offset:3236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s32 offset:3240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s32 offset:3244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s32 offset:3248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s32 offset:3252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s32 offset:3256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s32 offset:3260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s32 offset:3264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s32 offset:3268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s32 offset:3272 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s32 offset:3024 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s32 offset:3028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s32 offset:3032 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s32 offset:3036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s32 offset:3040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s32 offset:3044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s32 offset:3048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s32 offset:3052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s32 offset:3056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s32 offset:3060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s32 offset:3064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s32 offset:3068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s32 offset:3072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s32 offset:3076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s32 offset:3080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s32 offset:3084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s32 offset:3088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s32 offset:3092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s32 offset:3096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s32 offset:3100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s32 offset:3104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s32 offset:3108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s32 offset:3112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s32 offset:3116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s32 offset:3120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s32 offset:3124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s32 offset:3128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s32 offset:3132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s32 offset:3136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s32 offset:3140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s32 offset:3144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s32 offset:3148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s32 offset:3152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s32 offset:3156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s32 offset:3160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s32 offset:3164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s32 offset:3168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s32 offset:3172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s32 offset:3176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s32 offset:3180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s32 offset:3184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s32 offset:3188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s32 offset:3192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s32 offset:3196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s32 offset:3200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s32 offset:3204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s32 offset:3208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s32 offset:3212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s32 offset:3216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s32 offset:3220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s32 offset:3224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s32 offset:3228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s32 offset:3232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s32 offset:3236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s32 offset:3240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s32 offset:3244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s32 offset:3248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s32 offset:3252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s32 offset:3256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s32 offset:3260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s32 offset:3264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s32 offset:3268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s32 offset:3272 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s32 offset:3276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s32 offset:3280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s32 offset:3284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s32 offset:3288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s32 offset:3292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s32 offset:3296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s32 offset:3300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s32 offset:3304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s32 offset:3308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s32 offset:3312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s32 offset:3316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s32 offset:3320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s32 offset:3324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s32 offset:3328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s32 offset:3332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s32 offset:3336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s32 offset:3340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s32 offset:3344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s32 offset:3348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s32 offset:3352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s32 offset:3356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s32 offset:3360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s32 offset:3364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s32 offset:3368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s32 offset:3372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s32 offset:3376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s32 offset:3380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s32 offset:3384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s32 offset:3388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s32 offset:3392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s32 offset:3396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s32 offset:3400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s32 offset:3404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s32 offset:3408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s32 offset:3412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s32 offset:3416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s32 offset:3420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s32 offset:3424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s32 offset:3428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s32 offset:3432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s32 offset:3436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s32 offset:3440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s32 offset:3444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s32 offset:3448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s32 offset:3452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s32 offset:3456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s32 offset:3460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s32 offset:3464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s32 offset:3468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s32 offset:3472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s32 offset:3476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s32 offset:3480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s32 offset:3484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s32 offset:3488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s32 offset:3492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s32 offset:3496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s32 offset:3500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s32 offset:3504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s32 offset:3508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s32 offset:3512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s32 offset:3516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s32 offset:3520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s32 offset:3524 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s32 offset:3276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s32 offset:3280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s32 offset:3284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s32 offset:3288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s32 offset:3292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s32 offset:3296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s32 offset:3300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s32 offset:3304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s32 offset:3308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s32 offset:3312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s32 offset:3316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s32 offset:3320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s32 offset:3324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s32 offset:3328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s32 offset:3332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s32 offset:3336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s32 offset:3340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s32 offset:3344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s32 offset:3348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s32 offset:3352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s32 offset:3356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s32 offset:3360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s32 offset:3364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s32 offset:3368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s32 offset:3372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s32 offset:3376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s32 offset:3380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s32 offset:3384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s32 offset:3388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s32 offset:3392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s32 offset:3396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s32 offset:3400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s32 offset:3404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s32 offset:3408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s32 offset:3412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s32 offset:3416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s32 offset:3420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s32 offset:3424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s32 offset:3428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s32 offset:3432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s32 offset:3436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s32 offset:3440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s32 offset:3444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s32 offset:3448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s32 offset:3452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s32 offset:3456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s32 offset:3460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s32 offset:3464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s32 offset:3468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s32 offset:3472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s32 offset:3476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s32 offset:3480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s32 offset:3484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s32 offset:3488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s32 offset:3492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s32 offset:3496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s32 offset:3500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s32 offset:3504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s32 offset:3508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s32 offset:3512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s32 offset:3516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s32 offset:3520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s32 offset:3524 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; 120-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s32 offset:3528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s32 offset:3532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s32 offset:3536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s32 offset:3540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s32 offset:3544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s32 offset:3548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s32 offset:3552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s32 offset:3556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s32 offset:3560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s32 offset:3564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s32 offset:3568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s32 offset:3572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s32 offset:3576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s32 offset:3580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s32 offset:3584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s32 offset:3588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s32 offset:3592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s32 offset:3596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s32 offset:3600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s32 offset:3604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s32 offset:3608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s32 offset:3612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s32 offset:3616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s32 offset:3620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s32 offset:3624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s32 offset:3628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s32 offset:3632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s32 offset:3636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s32 offset:3640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s32 offset:3644 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s32 offset:3528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s32 offset:3532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s32 offset:3536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s32 offset:3540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s32 offset:3544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s32 offset:3548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s32 offset:3552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s32 offset:3556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s32 offset:3560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s32 offset:3564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s32 offset:3568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s32 offset:3572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s32 offset:3576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s32 offset:3580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s32 offset:3584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s32 offset:3588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s32 offset:3592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s32 offset:3596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s32 offset:3600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s32 offset:3604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s32 offset:3608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s32 offset:3612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s32 offset:3616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s32 offset:3620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s32 offset:3624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s32 offset:3628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s32 offset:3632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s32 offset:3636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s32 offset:3640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s32 offset:3644 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: v_mov_b32_e32 v2, v0 @@ -6876,935 +6876,935 @@ define amdgpu_gfx_whole_wave <2 x half> @tail_call_gfx_from_whole_wave(i1 %activ ; GFX1250-DAGISEL-NEXT: v_swap_b32 v0, v1 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, s0, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s32 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s32 offset:12 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4, off, s32 offset:16 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5, off, s32 offset:20 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6, off, s32 offset:24 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7, off, s32 offset:28 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8, off, s32 offset:32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9, off, s32 offset:36 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10, off, s32 offset:40 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11, off, s32 offset:44 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12, off, s32 offset:48 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13, off, s32 offset:52 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14, off, s32 offset:56 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15, off, s32 offset:60 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16, off, s32 offset:64 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17, off, s32 offset:68 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18, off, s32 offset:72 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19, off, s32 offset:76 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20, off, s32 offset:80 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21, off, s32 offset:84 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22, off, s32 offset:88 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23, off, s32 offset:92 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24, off, s32 offset:96 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25, off, s32 offset:100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26, off, s32 offset:104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27, off, s32 offset:108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28, off, s32 offset:112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29, off, s32 offset:116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30, off, s32 offset:120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31, off, s32 offset:124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32, off, s32 offset:128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33, off, s32 offset:132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34, off, s32 offset:136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35, off, s32 offset:140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36, off, s32 offset:144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37, off, s32 offset:148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38, off, s32 offset:152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39, off, s32 offset:156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48, off, s32 offset:160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49, off, s32 offset:164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50, off, s32 offset:168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51, off, s32 offset:172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52, off, s32 offset:176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53, off, s32 offset:180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54, off, s32 offset:184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55, off, s32 offset:188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64, off, s32 offset:192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65, off, s32 offset:196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66, off, s32 offset:200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67, off, s32 offset:204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68, off, s32 offset:208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69, off, s32 offset:212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70, off, s32 offset:216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71, off, s32 offset:220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80, off, s32 offset:224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81, off, s32 offset:228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82, off, s32 offset:232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83, off, s32 offset:236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84, off, s32 offset:240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85, off, s32 offset:244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86, off, s32 offset:248 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s32 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s32 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s32 offset:12 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4, off, s32 offset:16 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5, off, s32 offset:20 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6, off, s32 offset:24 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7, off, s32 offset:28 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8, off, s32 offset:32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9, off, s32 offset:36 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10, off, s32 offset:40 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11, off, s32 offset:44 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12, off, s32 offset:48 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13, off, s32 offset:52 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14, off, s32 offset:56 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15, off, s32 offset:60 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16, off, s32 offset:64 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17, off, s32 offset:68 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18, off, s32 offset:72 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19, off, s32 offset:76 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20, off, s32 offset:80 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21, off, s32 offset:84 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22, off, s32 offset:88 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23, off, s32 offset:92 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24, off, s32 offset:96 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25, off, s32 offset:100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26, off, s32 offset:104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27, off, s32 offset:108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28, off, s32 offset:112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29, off, s32 offset:116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30, off, s32 offset:120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31, off, s32 offset:124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32, off, s32 offset:128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33, off, s32 offset:132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34, off, s32 offset:136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35, off, s32 offset:140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36, off, s32 offset:144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37, off, s32 offset:148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38, off, s32 offset:152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39, off, s32 offset:156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48, off, s32 offset:160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49, off, s32 offset:164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50, off, s32 offset:168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51, off, s32 offset:172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52, off, s32 offset:176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53, off, s32 offset:180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54, off, s32 offset:184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55, off, s32 offset:188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64, off, s32 offset:192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65, off, s32 offset:196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66, off, s32 offset:200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67, off, s32 offset:204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68, off, s32 offset:208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69, off, s32 offset:212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70, off, s32 offset:216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71, off, s32 offset:220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80, off, s32 offset:224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81, off, s32 offset:228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82, off, s32 offset:232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83, off, s32 offset:236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84, off, s32 offset:240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85, off, s32 offset:244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86, off, s32 offset:248 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87, off, s32 offset:252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96, off, s32 offset:256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97, off, s32 offset:260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98, off, s32 offset:264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99, off, s32 offset:268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100, off, s32 offset:272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101, off, s32 offset:276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102, off, s32 offset:280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103, off, s32 offset:284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112, off, s32 offset:288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113, off, s32 offset:292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114, off, s32 offset:296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115, off, s32 offset:300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116, off, s32 offset:304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117, off, s32 offset:308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118, off, s32 offset:312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119, off, s32 offset:316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128, off, s32 offset:320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129, off, s32 offset:324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130, off, s32 offset:328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131, off, s32 offset:332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132, off, s32 offset:336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133, off, s32 offset:340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134, off, s32 offset:344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135, off, s32 offset:348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144, off, s32 offset:352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145, off, s32 offset:356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146, off, s32 offset:360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147, off, s32 offset:364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148, off, s32 offset:368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149, off, s32 offset:372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150, off, s32 offset:376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151, off, s32 offset:380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160, off, s32 offset:384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161, off, s32 offset:388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162, off, s32 offset:392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163, off, s32 offset:396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164, off, s32 offset:400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165, off, s32 offset:404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166, off, s32 offset:408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167, off, s32 offset:412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176, off, s32 offset:416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177, off, s32 offset:420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178, off, s32 offset:424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179, off, s32 offset:428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180, off, s32 offset:432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181, off, s32 offset:436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182, off, s32 offset:440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183, off, s32 offset:444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192, off, s32 offset:448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193, off, s32 offset:452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194, off, s32 offset:456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195, off, s32 offset:460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196, off, s32 offset:464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197, off, s32 offset:468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198, off, s32 offset:472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199, off, s32 offset:476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208, off, s32 offset:480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209, off, s32 offset:484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210, off, s32 offset:488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211, off, s32 offset:492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212, off, s32 offset:496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213, off, s32 offset:500 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87, off, s32 offset:252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96, off, s32 offset:256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97, off, s32 offset:260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98, off, s32 offset:264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99, off, s32 offset:268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100, off, s32 offset:272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101, off, s32 offset:276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102, off, s32 offset:280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103, off, s32 offset:284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112, off, s32 offset:288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113, off, s32 offset:292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114, off, s32 offset:296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115, off, s32 offset:300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116, off, s32 offset:304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117, off, s32 offset:308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118, off, s32 offset:312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119, off, s32 offset:316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128, off, s32 offset:320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129, off, s32 offset:324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130, off, s32 offset:328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131, off, s32 offset:332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132, off, s32 offset:336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133, off, s32 offset:340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134, off, s32 offset:344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135, off, s32 offset:348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144, off, s32 offset:352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145, off, s32 offset:356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146, off, s32 offset:360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147, off, s32 offset:364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148, off, s32 offset:368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149, off, s32 offset:372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150, off, s32 offset:376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151, off, s32 offset:380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160, off, s32 offset:384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161, off, s32 offset:388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162, off, s32 offset:392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163, off, s32 offset:396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164, off, s32 offset:400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165, off, s32 offset:404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166, off, s32 offset:408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167, off, s32 offset:412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176, off, s32 offset:416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177, off, s32 offset:420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178, off, s32 offset:424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179, off, s32 offset:428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180, off, s32 offset:432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181, off, s32 offset:436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182, off, s32 offset:440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183, off, s32 offset:444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192, off, s32 offset:448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193, off, s32 offset:452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194, off, s32 offset:456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195, off, s32 offset:460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196, off, s32 offset:464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197, off, s32 offset:468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198, off, s32 offset:472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199, off, s32 offset:476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208, off, s32 offset:480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209, off, s32 offset:484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210, off, s32 offset:488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211, off, s32 offset:492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212, off, s32 offset:496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213, off, s32 offset:500 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214, off, s32 offset:504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215, off, s32 offset:508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224, off, s32 offset:512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225, off, s32 offset:516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226, off, s32 offset:520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227, off, s32 offset:524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228, off, s32 offset:528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229, off, s32 offset:532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230, off, s32 offset:536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231, off, s32 offset:540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240, off, s32 offset:544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241, off, s32 offset:548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242, off, s32 offset:552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243, off, s32 offset:556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244, off, s32 offset:560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245, off, s32 offset:564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246, off, s32 offset:568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247, off, s32 offset:572 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214, off, s32 offset:504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215, off, s32 offset:508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224, off, s32 offset:512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225, off, s32 offset:516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226, off, s32 offset:520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227, off, s32 offset:524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228, off, s32 offset:528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229, off, s32 offset:532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230, off, s32 offset:536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231, off, s32 offset:540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240, off, s32 offset:544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241, off, s32 offset:548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242, off, s32 offset:552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243, off, s32 offset:556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244, off, s32 offset:560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245, off, s32 offset:564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246, off, s32 offset:568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247, off, s32 offset:572 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 64 ; msbs: dst=1 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v256*/, off, s32 offset:576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v257*/, off, s32 offset:580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v258*/, off, s32 offset:584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v259*/, off, s32 offset:588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v260*/, off, s32 offset:592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v261*/, off, s32 offset:596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v262*/, off, s32 offset:600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v263*/, off, s32 offset:604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v264*/, off, s32 offset:608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v265*/, off, s32 offset:612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v266*/, off, s32 offset:616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v267*/, off, s32 offset:620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v268*/, off, s32 offset:624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v269*/, off, s32 offset:628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v270*/, off, s32 offset:632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v271*/, off, s32 offset:636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v272*/, off, s32 offset:640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v273*/, off, s32 offset:644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v274*/, off, s32 offset:648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v275*/, off, s32 offset:652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v276*/, off, s32 offset:656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v277*/, off, s32 offset:660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v278*/, off, s32 offset:664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v279*/, off, s32 offset:668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v280*/, off, s32 offset:672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v281*/, off, s32 offset:676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v282*/, off, s32 offset:680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v283*/, off, s32 offset:684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v284*/, off, s32 offset:688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v285*/, off, s32 offset:692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v286*/, off, s32 offset:696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v287*/, off, s32 offset:700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v288*/, off, s32 offset:704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v289*/, off, s32 offset:708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v290*/, off, s32 offset:712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v291*/, off, s32 offset:716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v292*/, off, s32 offset:720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v293*/, off, s32 offset:724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v294*/, off, s32 offset:728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v295*/, off, s32 offset:732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v296*/, off, s32 offset:736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v297*/, off, s32 offset:740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v298*/, off, s32 offset:744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v299*/, off, s32 offset:748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v300*/, off, s32 offset:752 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v256*/, off, s32 offset:576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v257*/, off, s32 offset:580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v258*/, off, s32 offset:584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v259*/, off, s32 offset:588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v260*/, off, s32 offset:592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v261*/, off, s32 offset:596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v262*/, off, s32 offset:600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v263*/, off, s32 offset:604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v264*/, off, s32 offset:608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v265*/, off, s32 offset:612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v266*/, off, s32 offset:616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v267*/, off, s32 offset:620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v268*/, off, s32 offset:624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v269*/, off, s32 offset:628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v270*/, off, s32 offset:632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v271*/, off, s32 offset:636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v272*/, off, s32 offset:640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v273*/, off, s32 offset:644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v274*/, off, s32 offset:648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v275*/, off, s32 offset:652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v276*/, off, s32 offset:656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v277*/, off, s32 offset:660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v278*/, off, s32 offset:664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v279*/, off, s32 offset:668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v280*/, off, s32 offset:672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v281*/, off, s32 offset:676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v282*/, off, s32 offset:680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v283*/, off, s32 offset:684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v284*/, off, s32 offset:688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v285*/, off, s32 offset:692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v286*/, off, s32 offset:696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v287*/, off, s32 offset:700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v288*/, off, s32 offset:704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v289*/, off, s32 offset:708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v290*/, off, s32 offset:712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v291*/, off, s32 offset:716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v292*/, off, s32 offset:720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v293*/, off, s32 offset:724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v294*/, off, s32 offset:728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v295*/, off, s32 offset:732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v296*/, off, s32 offset:736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v297*/, off, s32 offset:740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v298*/, off, s32 offset:744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v299*/, off, s32 offset:748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v300*/, off, s32 offset:752 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v301*/, off, s32 offset:756 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v302*/, off, s32 offset:760 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v303*/, off, s32 offset:764 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v304*/, off, s32 offset:768 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v305*/, off, s32 offset:772 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v306*/, off, s32 offset:776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v307*/, off, s32 offset:780 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v308*/, off, s32 offset:784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v309*/, off, s32 offset:788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v310*/, off, s32 offset:792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v311*/, off, s32 offset:796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v312*/, off, s32 offset:800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v313*/, off, s32 offset:804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v314*/, off, s32 offset:808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v315*/, off, s32 offset:812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v316*/, off, s32 offset:816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v317*/, off, s32 offset:820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v318*/, off, s32 offset:824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v319*/, off, s32 offset:828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v320*/, off, s32 offset:832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v321*/, off, s32 offset:836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v322*/, off, s32 offset:840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v323*/, off, s32 offset:844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v324*/, off, s32 offset:848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v325*/, off, s32 offset:852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v326*/, off, s32 offset:856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v327*/, off, s32 offset:860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v328*/, off, s32 offset:864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v329*/, off, s32 offset:868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v330*/, off, s32 offset:872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v331*/, off, s32 offset:876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v332*/, off, s32 offset:880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v333*/, off, s32 offset:884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v334*/, off, s32 offset:888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v335*/, off, s32 offset:892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v336*/, off, s32 offset:896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v337*/, off, s32 offset:900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v338*/, off, s32 offset:904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v339*/, off, s32 offset:908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v340*/, off, s32 offset:912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v341*/, off, s32 offset:916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v342*/, off, s32 offset:920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v343*/, off, s32 offset:924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v344*/, off, s32 offset:928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v345*/, off, s32 offset:932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v346*/, off, s32 offset:936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v347*/, off, s32 offset:940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v348*/, off, s32 offset:944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v349*/, off, s32 offset:948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v350*/, off, s32 offset:952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v351*/, off, s32 offset:956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v352*/, off, s32 offset:960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v353*/, off, s32 offset:964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v354*/, off, s32 offset:968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v355*/, off, s32 offset:972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v356*/, off, s32 offset:976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v357*/, off, s32 offset:980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v358*/, off, s32 offset:984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v359*/, off, s32 offset:988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v360*/, off, s32 offset:992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v361*/, off, s32 offset:996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v362*/, off, s32 offset:1000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v363*/, off, s32 offset:1004 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v301*/, off, s32 offset:756 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v302*/, off, s32 offset:760 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v303*/, off, s32 offset:764 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v304*/, off, s32 offset:768 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v305*/, off, s32 offset:772 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v306*/, off, s32 offset:776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v307*/, off, s32 offset:780 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v308*/, off, s32 offset:784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v309*/, off, s32 offset:788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v310*/, off, s32 offset:792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v311*/, off, s32 offset:796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v312*/, off, s32 offset:800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v313*/, off, s32 offset:804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v314*/, off, s32 offset:808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v315*/, off, s32 offset:812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v316*/, off, s32 offset:816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v317*/, off, s32 offset:820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v318*/, off, s32 offset:824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v319*/, off, s32 offset:828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v320*/, off, s32 offset:832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v321*/, off, s32 offset:836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v322*/, off, s32 offset:840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v323*/, off, s32 offset:844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v324*/, off, s32 offset:848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v325*/, off, s32 offset:852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v326*/, off, s32 offset:856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v327*/, off, s32 offset:860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v328*/, off, s32 offset:864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v329*/, off, s32 offset:868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v330*/, off, s32 offset:872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v331*/, off, s32 offset:876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v332*/, off, s32 offset:880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v333*/, off, s32 offset:884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v334*/, off, s32 offset:888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v335*/, off, s32 offset:892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v336*/, off, s32 offset:896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v337*/, off, s32 offset:900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v338*/, off, s32 offset:904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v339*/, off, s32 offset:908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v340*/, off, s32 offset:912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v341*/, off, s32 offset:916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v342*/, off, s32 offset:920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v343*/, off, s32 offset:924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v344*/, off, s32 offset:928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v345*/, off, s32 offset:932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v346*/, off, s32 offset:936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v347*/, off, s32 offset:940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v348*/, off, s32 offset:944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v349*/, off, s32 offset:948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v350*/, off, s32 offset:952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v351*/, off, s32 offset:956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v352*/, off, s32 offset:960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v353*/, off, s32 offset:964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v354*/, off, s32 offset:968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v355*/, off, s32 offset:972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v356*/, off, s32 offset:976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v357*/, off, s32 offset:980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v358*/, off, s32 offset:984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v359*/, off, s32 offset:988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v360*/, off, s32 offset:992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v361*/, off, s32 offset:996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v362*/, off, s32 offset:1000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v363*/, off, s32 offset:1004 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v364*/, off, s32 offset:1008 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v365*/, off, s32 offset:1012 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v366*/, off, s32 offset:1016 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v367*/, off, s32 offset:1020 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v368*/, off, s32 offset:1024 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v369*/, off, s32 offset:1028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v370*/, off, s32 offset:1032 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v371*/, off, s32 offset:1036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v372*/, off, s32 offset:1040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v373*/, off, s32 offset:1044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v374*/, off, s32 offset:1048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v375*/, off, s32 offset:1052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v376*/, off, s32 offset:1056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v377*/, off, s32 offset:1060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v378*/, off, s32 offset:1064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v379*/, off, s32 offset:1068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v380*/, off, s32 offset:1072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v381*/, off, s32 offset:1076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v382*/, off, s32 offset:1080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v383*/, off, s32 offset:1084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v384*/, off, s32 offset:1088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v385*/, off, s32 offset:1092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v386*/, off, s32 offset:1096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v387*/, off, s32 offset:1100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v388*/, off, s32 offset:1104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v389*/, off, s32 offset:1108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v390*/, off, s32 offset:1112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v391*/, off, s32 offset:1116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v392*/, off, s32 offset:1120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v393*/, off, s32 offset:1124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v394*/, off, s32 offset:1128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v395*/, off, s32 offset:1132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v396*/, off, s32 offset:1136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v397*/, off, s32 offset:1140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v398*/, off, s32 offset:1144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v399*/, off, s32 offset:1148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v400*/, off, s32 offset:1152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v401*/, off, s32 offset:1156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v402*/, off, s32 offset:1160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v403*/, off, s32 offset:1164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v404*/, off, s32 offset:1168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v405*/, off, s32 offset:1172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v406*/, off, s32 offset:1176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v407*/, off, s32 offset:1180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v408*/, off, s32 offset:1184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v409*/, off, s32 offset:1188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v410*/, off, s32 offset:1192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v411*/, off, s32 offset:1196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v412*/, off, s32 offset:1200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v413*/, off, s32 offset:1204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v414*/, off, s32 offset:1208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v415*/, off, s32 offset:1212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v416*/, off, s32 offset:1216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v417*/, off, s32 offset:1220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v418*/, off, s32 offset:1224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v419*/, off, s32 offset:1228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v420*/, off, s32 offset:1232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v421*/, off, s32 offset:1236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v422*/, off, s32 offset:1240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v423*/, off, s32 offset:1244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v424*/, off, s32 offset:1248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v425*/, off, s32 offset:1252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v426*/, off, s32 offset:1256 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v364*/, off, s32 offset:1008 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v365*/, off, s32 offset:1012 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v366*/, off, s32 offset:1016 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v367*/, off, s32 offset:1020 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v368*/, off, s32 offset:1024 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v369*/, off, s32 offset:1028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v370*/, off, s32 offset:1032 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v371*/, off, s32 offset:1036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v372*/, off, s32 offset:1040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v373*/, off, s32 offset:1044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v374*/, off, s32 offset:1048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v375*/, off, s32 offset:1052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v376*/, off, s32 offset:1056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v377*/, off, s32 offset:1060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v378*/, off, s32 offset:1064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v379*/, off, s32 offset:1068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v380*/, off, s32 offset:1072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v381*/, off, s32 offset:1076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v382*/, off, s32 offset:1080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v383*/, off, s32 offset:1084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v384*/, off, s32 offset:1088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v385*/, off, s32 offset:1092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v386*/, off, s32 offset:1096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v387*/, off, s32 offset:1100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v388*/, off, s32 offset:1104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v389*/, off, s32 offset:1108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v390*/, off, s32 offset:1112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v391*/, off, s32 offset:1116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v392*/, off, s32 offset:1120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v393*/, off, s32 offset:1124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v394*/, off, s32 offset:1128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v395*/, off, s32 offset:1132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v396*/, off, s32 offset:1136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v397*/, off, s32 offset:1140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v398*/, off, s32 offset:1144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v399*/, off, s32 offset:1148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v400*/, off, s32 offset:1152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v401*/, off, s32 offset:1156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v402*/, off, s32 offset:1160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v403*/, off, s32 offset:1164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v404*/, off, s32 offset:1168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v405*/, off, s32 offset:1172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v406*/, off, s32 offset:1176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v407*/, off, s32 offset:1180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v408*/, off, s32 offset:1184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v409*/, off, s32 offset:1188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v410*/, off, s32 offset:1192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v411*/, off, s32 offset:1196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v412*/, off, s32 offset:1200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v413*/, off, s32 offset:1204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v414*/, off, s32 offset:1208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v415*/, off, s32 offset:1212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v416*/, off, s32 offset:1216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v417*/, off, s32 offset:1220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v418*/, off, s32 offset:1224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v419*/, off, s32 offset:1228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v420*/, off, s32 offset:1232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v421*/, off, s32 offset:1236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v422*/, off, s32 offset:1240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v423*/, off, s32 offset:1244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v424*/, off, s32 offset:1248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v425*/, off, s32 offset:1252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v426*/, off, s32 offset:1256 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v427*/, off, s32 offset:1260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v428*/, off, s32 offset:1264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v429*/, off, s32 offset:1268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v430*/, off, s32 offset:1272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v431*/, off, s32 offset:1276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v432*/, off, s32 offset:1280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v433*/, off, s32 offset:1284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v434*/, off, s32 offset:1288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v435*/, off, s32 offset:1292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v436*/, off, s32 offset:1296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v437*/, off, s32 offset:1300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v438*/, off, s32 offset:1304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v439*/, off, s32 offset:1308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v440*/, off, s32 offset:1312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v441*/, off, s32 offset:1316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v442*/, off, s32 offset:1320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v443*/, off, s32 offset:1324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v444*/, off, s32 offset:1328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v445*/, off, s32 offset:1332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v446*/, off, s32 offset:1336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v447*/, off, s32 offset:1340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v448*/, off, s32 offset:1344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v449*/, off, s32 offset:1348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v450*/, off, s32 offset:1352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v451*/, off, s32 offset:1356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v452*/, off, s32 offset:1360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v453*/, off, s32 offset:1364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v454*/, off, s32 offset:1368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v455*/, off, s32 offset:1372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v456*/, off, s32 offset:1376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v457*/, off, s32 offset:1380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v458*/, off, s32 offset:1384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v459*/, off, s32 offset:1388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v460*/, off, s32 offset:1392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v461*/, off, s32 offset:1396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v462*/, off, s32 offset:1400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v463*/, off, s32 offset:1404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v464*/, off, s32 offset:1408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v465*/, off, s32 offset:1412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v466*/, off, s32 offset:1416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v467*/, off, s32 offset:1420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v468*/, off, s32 offset:1424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v469*/, off, s32 offset:1428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v470*/, off, s32 offset:1432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v471*/, off, s32 offset:1436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v472*/, off, s32 offset:1440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v473*/, off, s32 offset:1444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v474*/, off, s32 offset:1448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v475*/, off, s32 offset:1452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v476*/, off, s32 offset:1456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v477*/, off, s32 offset:1460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v478*/, off, s32 offset:1464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v479*/, off, s32 offset:1468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v480*/, off, s32 offset:1472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v481*/, off, s32 offset:1476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v482*/, off, s32 offset:1480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v483*/, off, s32 offset:1484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v484*/, off, s32 offset:1488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v485*/, off, s32 offset:1492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v486*/, off, s32 offset:1496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v487*/, off, s32 offset:1500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v488*/, off, s32 offset:1504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v489*/, off, s32 offset:1508 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v427*/, off, s32 offset:1260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v428*/, off, s32 offset:1264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v429*/, off, s32 offset:1268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v430*/, off, s32 offset:1272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v431*/, off, s32 offset:1276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v432*/, off, s32 offset:1280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v433*/, off, s32 offset:1284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v434*/, off, s32 offset:1288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v435*/, off, s32 offset:1292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v436*/, off, s32 offset:1296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v437*/, off, s32 offset:1300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v438*/, off, s32 offset:1304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v439*/, off, s32 offset:1308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v440*/, off, s32 offset:1312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v441*/, off, s32 offset:1316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v442*/, off, s32 offset:1320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v443*/, off, s32 offset:1324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v444*/, off, s32 offset:1328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v445*/, off, s32 offset:1332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v446*/, off, s32 offset:1336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v447*/, off, s32 offset:1340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v448*/, off, s32 offset:1344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v449*/, off, s32 offset:1348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v450*/, off, s32 offset:1352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v451*/, off, s32 offset:1356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v452*/, off, s32 offset:1360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v453*/, off, s32 offset:1364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v454*/, off, s32 offset:1368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v455*/, off, s32 offset:1372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v456*/, off, s32 offset:1376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v457*/, off, s32 offset:1380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v458*/, off, s32 offset:1384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v459*/, off, s32 offset:1388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v460*/, off, s32 offset:1392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v461*/, off, s32 offset:1396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v462*/, off, s32 offset:1400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v463*/, off, s32 offset:1404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v464*/, off, s32 offset:1408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v465*/, off, s32 offset:1412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v466*/, off, s32 offset:1416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v467*/, off, s32 offset:1420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v468*/, off, s32 offset:1424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v469*/, off, s32 offset:1428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v470*/, off, s32 offset:1432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v471*/, off, s32 offset:1436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v472*/, off, s32 offset:1440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v473*/, off, s32 offset:1444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v474*/, off, s32 offset:1448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v475*/, off, s32 offset:1452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v476*/, off, s32 offset:1456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v477*/, off, s32 offset:1460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v478*/, off, s32 offset:1464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v479*/, off, s32 offset:1468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v480*/, off, s32 offset:1472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v481*/, off, s32 offset:1476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v482*/, off, s32 offset:1480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v483*/, off, s32 offset:1484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v484*/, off, s32 offset:1488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v485*/, off, s32 offset:1492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v486*/, off, s32 offset:1496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v487*/, off, s32 offset:1500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v488*/, off, s32 offset:1504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v489*/, off, s32 offset:1508 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v490*/, off, s32 offset:1512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v491*/, off, s32 offset:1516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v492*/, off, s32 offset:1520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v493*/, off, s32 offset:1524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v494*/, off, s32 offset:1528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v495*/, off, s32 offset:1532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v496*/, off, s32 offset:1536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v497*/, off, s32 offset:1540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v498*/, off, s32 offset:1544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v499*/, off, s32 offset:1548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v500*/, off, s32 offset:1552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v501*/, off, s32 offset:1556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v502*/, off, s32 offset:1560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v503*/, off, s32 offset:1564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v504*/, off, s32 offset:1568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v505*/, off, s32 offset:1572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v506*/, off, s32 offset:1576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v507*/, off, s32 offset:1580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v508*/, off, s32 offset:1584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v509*/, off, s32 offset:1588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v510*/, off, s32 offset:1592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v511*/, off, s32 offset:1596 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v490*/, off, s32 offset:1512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v491*/, off, s32 offset:1516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v492*/, off, s32 offset:1520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v493*/, off, s32 offset:1524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v494*/, off, s32 offset:1528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v495*/, off, s32 offset:1532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v496*/, off, s32 offset:1536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v497*/, off, s32 offset:1540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v498*/, off, s32 offset:1544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v499*/, off, s32 offset:1548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v500*/, off, s32 offset:1552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v501*/, off, s32 offset:1556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v502*/, off, s32 offset:1560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v503*/, off, s32 offset:1564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v504*/, off, s32 offset:1568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v505*/, off, s32 offset:1572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v506*/, off, s32 offset:1576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v507*/, off, s32 offset:1580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v508*/, off, s32 offset:1584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v509*/, off, s32 offset:1588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v510*/, off, s32 offset:1592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v511*/, off, s32 offset:1596 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x4080 ; msbs: dst=2 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v512*/, off, s32 offset:1600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v513*/, off, s32 offset:1604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v514*/, off, s32 offset:1608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v515*/, off, s32 offset:1612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v516*/, off, s32 offset:1616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v517*/, off, s32 offset:1620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v518*/, off, s32 offset:1624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v519*/, off, s32 offset:1628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v520*/, off, s32 offset:1632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v521*/, off, s32 offset:1636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v522*/, off, s32 offset:1640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v523*/, off, s32 offset:1644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v524*/, off, s32 offset:1648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v525*/, off, s32 offset:1652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v526*/, off, s32 offset:1656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v527*/, off, s32 offset:1660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v528*/, off, s32 offset:1664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v529*/, off, s32 offset:1668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v530*/, off, s32 offset:1672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v531*/, off, s32 offset:1676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v532*/, off, s32 offset:1680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v533*/, off, s32 offset:1684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v534*/, off, s32 offset:1688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v535*/, off, s32 offset:1692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v536*/, off, s32 offset:1696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v537*/, off, s32 offset:1700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v538*/, off, s32 offset:1704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v539*/, off, s32 offset:1708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v540*/, off, s32 offset:1712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v541*/, off, s32 offset:1716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v542*/, off, s32 offset:1720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v543*/, off, s32 offset:1724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v544*/, off, s32 offset:1728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v545*/, off, s32 offset:1732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v546*/, off, s32 offset:1736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v547*/, off, s32 offset:1740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v548*/, off, s32 offset:1744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v549*/, off, s32 offset:1748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v550*/, off, s32 offset:1752 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v551*/, off, s32 offset:1756 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v552*/, off, s32 offset:1760 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v512*/, off, s32 offset:1600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v513*/, off, s32 offset:1604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v514*/, off, s32 offset:1608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v515*/, off, s32 offset:1612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v516*/, off, s32 offset:1616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v517*/, off, s32 offset:1620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v518*/, off, s32 offset:1624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v519*/, off, s32 offset:1628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v520*/, off, s32 offset:1632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v521*/, off, s32 offset:1636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v522*/, off, s32 offset:1640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v523*/, off, s32 offset:1644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v524*/, off, s32 offset:1648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v525*/, off, s32 offset:1652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v526*/, off, s32 offset:1656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v527*/, off, s32 offset:1660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v528*/, off, s32 offset:1664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v529*/, off, s32 offset:1668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v530*/, off, s32 offset:1672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v531*/, off, s32 offset:1676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v532*/, off, s32 offset:1680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v533*/, off, s32 offset:1684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v534*/, off, s32 offset:1688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v535*/, off, s32 offset:1692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v536*/, off, s32 offset:1696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v537*/, off, s32 offset:1700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v538*/, off, s32 offset:1704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v539*/, off, s32 offset:1708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v540*/, off, s32 offset:1712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v541*/, off, s32 offset:1716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v542*/, off, s32 offset:1720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v543*/, off, s32 offset:1724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v544*/, off, s32 offset:1728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v545*/, off, s32 offset:1732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v546*/, off, s32 offset:1736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v547*/, off, s32 offset:1740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v548*/, off, s32 offset:1744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v549*/, off, s32 offset:1748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v550*/, off, s32 offset:1752 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v551*/, off, s32 offset:1756 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v552*/, off, s32 offset:1760 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v553*/, off, s32 offset:1764 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v554*/, off, s32 offset:1768 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v555*/, off, s32 offset:1772 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v556*/, off, s32 offset:1776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v557*/, off, s32 offset:1780 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v558*/, off, s32 offset:1784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v559*/, off, s32 offset:1788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v560*/, off, s32 offset:1792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v561*/, off, s32 offset:1796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v562*/, off, s32 offset:1800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v563*/, off, s32 offset:1804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v564*/, off, s32 offset:1808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v565*/, off, s32 offset:1812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v566*/, off, s32 offset:1816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v567*/, off, s32 offset:1820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v568*/, off, s32 offset:1824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v569*/, off, s32 offset:1828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v570*/, off, s32 offset:1832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v571*/, off, s32 offset:1836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v572*/, off, s32 offset:1840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v573*/, off, s32 offset:1844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v574*/, off, s32 offset:1848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v575*/, off, s32 offset:1852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v576*/, off, s32 offset:1856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v577*/, off, s32 offset:1860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v578*/, off, s32 offset:1864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v579*/, off, s32 offset:1868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v580*/, off, s32 offset:1872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v581*/, off, s32 offset:1876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v582*/, off, s32 offset:1880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v583*/, off, s32 offset:1884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v584*/, off, s32 offset:1888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v585*/, off, s32 offset:1892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v586*/, off, s32 offset:1896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v587*/, off, s32 offset:1900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v588*/, off, s32 offset:1904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v589*/, off, s32 offset:1908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v590*/, off, s32 offset:1912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v591*/, off, s32 offset:1916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v592*/, off, s32 offset:1920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v593*/, off, s32 offset:1924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v594*/, off, s32 offset:1928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v595*/, off, s32 offset:1932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v596*/, off, s32 offset:1936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v597*/, off, s32 offset:1940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v598*/, off, s32 offset:1944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v599*/, off, s32 offset:1948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v600*/, off, s32 offset:1952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v601*/, off, s32 offset:1956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v602*/, off, s32 offset:1960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v603*/, off, s32 offset:1964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v604*/, off, s32 offset:1968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v605*/, off, s32 offset:1972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v606*/, off, s32 offset:1976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v607*/, off, s32 offset:1980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v608*/, off, s32 offset:1984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v609*/, off, s32 offset:1988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v610*/, off, s32 offset:1992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v611*/, off, s32 offset:1996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v612*/, off, s32 offset:2000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v613*/, off, s32 offset:2004 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v614*/, off, s32 offset:2008 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v615*/, off, s32 offset:2012 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v553*/, off, s32 offset:1764 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v554*/, off, s32 offset:1768 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v555*/, off, s32 offset:1772 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v556*/, off, s32 offset:1776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v557*/, off, s32 offset:1780 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v558*/, off, s32 offset:1784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v559*/, off, s32 offset:1788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v560*/, off, s32 offset:1792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v561*/, off, s32 offset:1796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v562*/, off, s32 offset:1800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v563*/, off, s32 offset:1804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v564*/, off, s32 offset:1808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v565*/, off, s32 offset:1812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v566*/, off, s32 offset:1816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v567*/, off, s32 offset:1820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v568*/, off, s32 offset:1824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v569*/, off, s32 offset:1828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v570*/, off, s32 offset:1832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v571*/, off, s32 offset:1836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v572*/, off, s32 offset:1840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v573*/, off, s32 offset:1844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v574*/, off, s32 offset:1848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v575*/, off, s32 offset:1852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v576*/, off, s32 offset:1856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v577*/, off, s32 offset:1860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v578*/, off, s32 offset:1864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v579*/, off, s32 offset:1868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v580*/, off, s32 offset:1872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v581*/, off, s32 offset:1876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v582*/, off, s32 offset:1880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v583*/, off, s32 offset:1884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v584*/, off, s32 offset:1888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v585*/, off, s32 offset:1892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v586*/, off, s32 offset:1896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v587*/, off, s32 offset:1900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v588*/, off, s32 offset:1904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v589*/, off, s32 offset:1908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v590*/, off, s32 offset:1912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v591*/, off, s32 offset:1916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v592*/, off, s32 offset:1920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v593*/, off, s32 offset:1924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v594*/, off, s32 offset:1928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v595*/, off, s32 offset:1932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v596*/, off, s32 offset:1936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v597*/, off, s32 offset:1940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v598*/, off, s32 offset:1944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v599*/, off, s32 offset:1948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v600*/, off, s32 offset:1952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v601*/, off, s32 offset:1956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v602*/, off, s32 offset:1960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v603*/, off, s32 offset:1964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v604*/, off, s32 offset:1968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v605*/, off, s32 offset:1972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v606*/, off, s32 offset:1976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v607*/, off, s32 offset:1980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v608*/, off, s32 offset:1984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v609*/, off, s32 offset:1988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v610*/, off, s32 offset:1992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v611*/, off, s32 offset:1996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v612*/, off, s32 offset:2000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v613*/, off, s32 offset:2004 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v614*/, off, s32 offset:2008 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v615*/, off, s32 offset:2012 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v616*/, off, s32 offset:2016 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v617*/, off, s32 offset:2020 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v618*/, off, s32 offset:2024 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v619*/, off, s32 offset:2028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v620*/, off, s32 offset:2032 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v621*/, off, s32 offset:2036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v622*/, off, s32 offset:2040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v623*/, off, s32 offset:2044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v624*/, off, s32 offset:2048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v625*/, off, s32 offset:2052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v626*/, off, s32 offset:2056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v627*/, off, s32 offset:2060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v628*/, off, s32 offset:2064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v629*/, off, s32 offset:2068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v630*/, off, s32 offset:2072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v631*/, off, s32 offset:2076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v632*/, off, s32 offset:2080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v633*/, off, s32 offset:2084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v634*/, off, s32 offset:2088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v635*/, off, s32 offset:2092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v636*/, off, s32 offset:2096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v637*/, off, s32 offset:2100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v638*/, off, s32 offset:2104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v639*/, off, s32 offset:2108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v640*/, off, s32 offset:2112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v641*/, off, s32 offset:2116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v642*/, off, s32 offset:2120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v643*/, off, s32 offset:2124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v644*/, off, s32 offset:2128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v645*/, off, s32 offset:2132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v646*/, off, s32 offset:2136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v647*/, off, s32 offset:2140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v648*/, off, s32 offset:2144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v649*/, off, s32 offset:2148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v650*/, off, s32 offset:2152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v651*/, off, s32 offset:2156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v652*/, off, s32 offset:2160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v653*/, off, s32 offset:2164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v654*/, off, s32 offset:2168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v655*/, off, s32 offset:2172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v656*/, off, s32 offset:2176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v657*/, off, s32 offset:2180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v658*/, off, s32 offset:2184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v659*/, off, s32 offset:2188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v660*/, off, s32 offset:2192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v661*/, off, s32 offset:2196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v662*/, off, s32 offset:2200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v663*/, off, s32 offset:2204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v664*/, off, s32 offset:2208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v665*/, off, s32 offset:2212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v666*/, off, s32 offset:2216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v667*/, off, s32 offset:2220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v668*/, off, s32 offset:2224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v669*/, off, s32 offset:2228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v670*/, off, s32 offset:2232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v671*/, off, s32 offset:2236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v672*/, off, s32 offset:2240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v673*/, off, s32 offset:2244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v674*/, off, s32 offset:2248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v675*/, off, s32 offset:2252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v676*/, off, s32 offset:2256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v677*/, off, s32 offset:2260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v678*/, off, s32 offset:2264 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v616*/, off, s32 offset:2016 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v617*/, off, s32 offset:2020 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v618*/, off, s32 offset:2024 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v619*/, off, s32 offset:2028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v620*/, off, s32 offset:2032 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v621*/, off, s32 offset:2036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v622*/, off, s32 offset:2040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v623*/, off, s32 offset:2044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v624*/, off, s32 offset:2048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v625*/, off, s32 offset:2052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v626*/, off, s32 offset:2056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v627*/, off, s32 offset:2060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v628*/, off, s32 offset:2064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v629*/, off, s32 offset:2068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v630*/, off, s32 offset:2072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v631*/, off, s32 offset:2076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v632*/, off, s32 offset:2080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v633*/, off, s32 offset:2084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v634*/, off, s32 offset:2088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v635*/, off, s32 offset:2092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v636*/, off, s32 offset:2096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v637*/, off, s32 offset:2100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v638*/, off, s32 offset:2104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v639*/, off, s32 offset:2108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v640*/, off, s32 offset:2112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v641*/, off, s32 offset:2116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v642*/, off, s32 offset:2120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v643*/, off, s32 offset:2124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v644*/, off, s32 offset:2128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v645*/, off, s32 offset:2132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v646*/, off, s32 offset:2136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v647*/, off, s32 offset:2140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v648*/, off, s32 offset:2144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v649*/, off, s32 offset:2148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v650*/, off, s32 offset:2152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v651*/, off, s32 offset:2156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v652*/, off, s32 offset:2160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v653*/, off, s32 offset:2164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v654*/, off, s32 offset:2168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v655*/, off, s32 offset:2172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v656*/, off, s32 offset:2176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v657*/, off, s32 offset:2180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v658*/, off, s32 offset:2184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v659*/, off, s32 offset:2188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v660*/, off, s32 offset:2192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v661*/, off, s32 offset:2196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v662*/, off, s32 offset:2200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v663*/, off, s32 offset:2204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v664*/, off, s32 offset:2208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v665*/, off, s32 offset:2212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v666*/, off, s32 offset:2216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v667*/, off, s32 offset:2220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v668*/, off, s32 offset:2224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v669*/, off, s32 offset:2228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v670*/, off, s32 offset:2232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v671*/, off, s32 offset:2236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v672*/, off, s32 offset:2240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v673*/, off, s32 offset:2244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v674*/, off, s32 offset:2248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v675*/, off, s32 offset:2252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v676*/, off, s32 offset:2256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v677*/, off, s32 offset:2260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v678*/, off, s32 offset:2264 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v679*/, off, s32 offset:2268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v680*/, off, s32 offset:2272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v681*/, off, s32 offset:2276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v682*/, off, s32 offset:2280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v683*/, off, s32 offset:2284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v684*/, off, s32 offset:2288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v685*/, off, s32 offset:2292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v686*/, off, s32 offset:2296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v687*/, off, s32 offset:2300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v688*/, off, s32 offset:2304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v689*/, off, s32 offset:2308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v690*/, off, s32 offset:2312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v691*/, off, s32 offset:2316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v692*/, off, s32 offset:2320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v693*/, off, s32 offset:2324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v694*/, off, s32 offset:2328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v695*/, off, s32 offset:2332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v696*/, off, s32 offset:2336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v697*/, off, s32 offset:2340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v698*/, off, s32 offset:2344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v699*/, off, s32 offset:2348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v700*/, off, s32 offset:2352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v701*/, off, s32 offset:2356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v702*/, off, s32 offset:2360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v703*/, off, s32 offset:2364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v704*/, off, s32 offset:2368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v705*/, off, s32 offset:2372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v706*/, off, s32 offset:2376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v707*/, off, s32 offset:2380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v708*/, off, s32 offset:2384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v709*/, off, s32 offset:2388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v710*/, off, s32 offset:2392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v711*/, off, s32 offset:2396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v712*/, off, s32 offset:2400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v713*/, off, s32 offset:2404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v714*/, off, s32 offset:2408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v715*/, off, s32 offset:2412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v716*/, off, s32 offset:2416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v717*/, off, s32 offset:2420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v718*/, off, s32 offset:2424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v719*/, off, s32 offset:2428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v720*/, off, s32 offset:2432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v721*/, off, s32 offset:2436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v722*/, off, s32 offset:2440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v723*/, off, s32 offset:2444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v724*/, off, s32 offset:2448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v725*/, off, s32 offset:2452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v726*/, off, s32 offset:2456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v727*/, off, s32 offset:2460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v728*/, off, s32 offset:2464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v729*/, off, s32 offset:2468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v730*/, off, s32 offset:2472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v731*/, off, s32 offset:2476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v732*/, off, s32 offset:2480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v733*/, off, s32 offset:2484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v734*/, off, s32 offset:2488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v735*/, off, s32 offset:2492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v736*/, off, s32 offset:2496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v737*/, off, s32 offset:2500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v738*/, off, s32 offset:2504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v739*/, off, s32 offset:2508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v740*/, off, s32 offset:2512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v741*/, off, s32 offset:2516 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v679*/, off, s32 offset:2268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v680*/, off, s32 offset:2272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v681*/, off, s32 offset:2276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v682*/, off, s32 offset:2280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v683*/, off, s32 offset:2284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v684*/, off, s32 offset:2288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v685*/, off, s32 offset:2292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v686*/, off, s32 offset:2296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v687*/, off, s32 offset:2300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v688*/, off, s32 offset:2304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v689*/, off, s32 offset:2308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v690*/, off, s32 offset:2312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v691*/, off, s32 offset:2316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v692*/, off, s32 offset:2320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v693*/, off, s32 offset:2324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v694*/, off, s32 offset:2328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v695*/, off, s32 offset:2332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v696*/, off, s32 offset:2336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v697*/, off, s32 offset:2340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v698*/, off, s32 offset:2344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v699*/, off, s32 offset:2348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v700*/, off, s32 offset:2352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v701*/, off, s32 offset:2356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v702*/, off, s32 offset:2360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v703*/, off, s32 offset:2364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v704*/, off, s32 offset:2368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v705*/, off, s32 offset:2372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v706*/, off, s32 offset:2376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v707*/, off, s32 offset:2380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v708*/, off, s32 offset:2384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v709*/, off, s32 offset:2388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v710*/, off, s32 offset:2392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v711*/, off, s32 offset:2396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v712*/, off, s32 offset:2400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v713*/, off, s32 offset:2404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v714*/, off, s32 offset:2408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v715*/, off, s32 offset:2412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v716*/, off, s32 offset:2416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v717*/, off, s32 offset:2420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v718*/, off, s32 offset:2424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v719*/, off, s32 offset:2428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v720*/, off, s32 offset:2432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v721*/, off, s32 offset:2436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v722*/, off, s32 offset:2440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v723*/, off, s32 offset:2444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v724*/, off, s32 offset:2448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v725*/, off, s32 offset:2452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v726*/, off, s32 offset:2456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v727*/, off, s32 offset:2460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v728*/, off, s32 offset:2464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v729*/, off, s32 offset:2468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v730*/, off, s32 offset:2472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v731*/, off, s32 offset:2476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v732*/, off, s32 offset:2480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v733*/, off, s32 offset:2484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v734*/, off, s32 offset:2488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v735*/, off, s32 offset:2492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v736*/, off, s32 offset:2496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v737*/, off, s32 offset:2500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v738*/, off, s32 offset:2504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v739*/, off, s32 offset:2508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v740*/, off, s32 offset:2512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v741*/, off, s32 offset:2516 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v742*/, off, s32 offset:2520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v743*/, off, s32 offset:2524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v744*/, off, s32 offset:2528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v745*/, off, s32 offset:2532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v746*/, off, s32 offset:2536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v747*/, off, s32 offset:2540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v748*/, off, s32 offset:2544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v749*/, off, s32 offset:2548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v750*/, off, s32 offset:2552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v751*/, off, s32 offset:2556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v752*/, off, s32 offset:2560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v753*/, off, s32 offset:2564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v754*/, off, s32 offset:2568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v755*/, off, s32 offset:2572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v756*/, off, s32 offset:2576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v757*/, off, s32 offset:2580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v758*/, off, s32 offset:2584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v759*/, off, s32 offset:2588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v760*/, off, s32 offset:2592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v761*/, off, s32 offset:2596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v762*/, off, s32 offset:2600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v763*/, off, s32 offset:2604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v764*/, off, s32 offset:2608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v765*/, off, s32 offset:2612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v766*/, off, s32 offset:2616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v767*/, off, s32 offset:2620 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v742*/, off, s32 offset:2520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v743*/, off, s32 offset:2524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v744*/, off, s32 offset:2528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v745*/, off, s32 offset:2532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v746*/, off, s32 offset:2536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v747*/, off, s32 offset:2540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v748*/, off, s32 offset:2544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v749*/, off, s32 offset:2548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v750*/, off, s32 offset:2552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v751*/, off, s32 offset:2556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v752*/, off, s32 offset:2560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v753*/, off, s32 offset:2564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v754*/, off, s32 offset:2568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v755*/, off, s32 offset:2572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v756*/, off, s32 offset:2576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v757*/, off, s32 offset:2580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v758*/, off, s32 offset:2584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v759*/, off, s32 offset:2588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v760*/, off, s32 offset:2592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v761*/, off, s32 offset:2596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v762*/, off, s32 offset:2600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v763*/, off, s32 offset:2604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v764*/, off, s32 offset:2608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v765*/, off, s32 offset:2612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v766*/, off, s32 offset:2616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v767*/, off, s32 offset:2620 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x80c0 ; msbs: dst=3 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v768*/, off, s32 offset:2624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v769*/, off, s32 offset:2628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v770*/, off, s32 offset:2632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v771*/, off, s32 offset:2636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v772*/, off, s32 offset:2640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v773*/, off, s32 offset:2644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v774*/, off, s32 offset:2648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v775*/, off, s32 offset:2652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v776*/, off, s32 offset:2656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v777*/, off, s32 offset:2660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v778*/, off, s32 offset:2664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v779*/, off, s32 offset:2668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v780*/, off, s32 offset:2672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v781*/, off, s32 offset:2676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v782*/, off, s32 offset:2680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v783*/, off, s32 offset:2684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v784*/, off, s32 offset:2688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v785*/, off, s32 offset:2692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v786*/, off, s32 offset:2696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v787*/, off, s32 offset:2700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v788*/, off, s32 offset:2704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v789*/, off, s32 offset:2708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v790*/, off, s32 offset:2712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v791*/, off, s32 offset:2716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v792*/, off, s32 offset:2720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v793*/, off, s32 offset:2724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v794*/, off, s32 offset:2728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v795*/, off, s32 offset:2732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v796*/, off, s32 offset:2736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v797*/, off, s32 offset:2740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v798*/, off, s32 offset:2744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v799*/, off, s32 offset:2748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v800*/, off, s32 offset:2752 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v801*/, off, s32 offset:2756 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v802*/, off, s32 offset:2760 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v803*/, off, s32 offset:2764 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v804*/, off, s32 offset:2768 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v768*/, off, s32 offset:2624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v769*/, off, s32 offset:2628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v770*/, off, s32 offset:2632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v771*/, off, s32 offset:2636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v772*/, off, s32 offset:2640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v773*/, off, s32 offset:2644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v774*/, off, s32 offset:2648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v775*/, off, s32 offset:2652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v776*/, off, s32 offset:2656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v777*/, off, s32 offset:2660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v778*/, off, s32 offset:2664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v779*/, off, s32 offset:2668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v780*/, off, s32 offset:2672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v781*/, off, s32 offset:2676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v782*/, off, s32 offset:2680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v783*/, off, s32 offset:2684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v784*/, off, s32 offset:2688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v785*/, off, s32 offset:2692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v786*/, off, s32 offset:2696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v787*/, off, s32 offset:2700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v788*/, off, s32 offset:2704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v789*/, off, s32 offset:2708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v790*/, off, s32 offset:2712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v791*/, off, s32 offset:2716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v792*/, off, s32 offset:2720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v793*/, off, s32 offset:2724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v794*/, off, s32 offset:2728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v795*/, off, s32 offset:2732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v796*/, off, s32 offset:2736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v797*/, off, s32 offset:2740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v798*/, off, s32 offset:2744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v799*/, off, s32 offset:2748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v800*/, off, s32 offset:2752 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v801*/, off, s32 offset:2756 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v802*/, off, s32 offset:2760 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v803*/, off, s32 offset:2764 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v804*/, off, s32 offset:2768 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v805*/, off, s32 offset:2772 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v806*/, off, s32 offset:2776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v807*/, off, s32 offset:2780 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v808*/, off, s32 offset:2784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v809*/, off, s32 offset:2788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v810*/, off, s32 offset:2792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v811*/, off, s32 offset:2796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v812*/, off, s32 offset:2800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v813*/, off, s32 offset:2804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v814*/, off, s32 offset:2808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v815*/, off, s32 offset:2812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v816*/, off, s32 offset:2816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v817*/, off, s32 offset:2820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v818*/, off, s32 offset:2824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v819*/, off, s32 offset:2828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v820*/, off, s32 offset:2832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v821*/, off, s32 offset:2836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v822*/, off, s32 offset:2840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v823*/, off, s32 offset:2844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v824*/, off, s32 offset:2848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v825*/, off, s32 offset:2852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v826*/, off, s32 offset:2856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v827*/, off, s32 offset:2860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v828*/, off, s32 offset:2864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v829*/, off, s32 offset:2868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v830*/, off, s32 offset:2872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v831*/, off, s32 offset:2876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v832*/, off, s32 offset:2880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v833*/, off, s32 offset:2884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v834*/, off, s32 offset:2888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v835*/, off, s32 offset:2892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v836*/, off, s32 offset:2896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v837*/, off, s32 offset:2900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v838*/, off, s32 offset:2904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v839*/, off, s32 offset:2908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v840*/, off, s32 offset:2912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v841*/, off, s32 offset:2916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v842*/, off, s32 offset:2920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v843*/, off, s32 offset:2924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v844*/, off, s32 offset:2928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v845*/, off, s32 offset:2932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v846*/, off, s32 offset:2936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v847*/, off, s32 offset:2940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v848*/, off, s32 offset:2944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v849*/, off, s32 offset:2948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v850*/, off, s32 offset:2952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v851*/, off, s32 offset:2956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v852*/, off, s32 offset:2960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v853*/, off, s32 offset:2964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v854*/, off, s32 offset:2968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v855*/, off, s32 offset:2972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v856*/, off, s32 offset:2976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v857*/, off, s32 offset:2980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v858*/, off, s32 offset:2984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v859*/, off, s32 offset:2988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v860*/, off, s32 offset:2992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v861*/, off, s32 offset:2996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v862*/, off, s32 offset:3000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v863*/, off, s32 offset:3004 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v864*/, off, s32 offset:3008 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v865*/, off, s32 offset:3012 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v866*/, off, s32 offset:3016 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v867*/, off, s32 offset:3020 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v805*/, off, s32 offset:2772 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v806*/, off, s32 offset:2776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v807*/, off, s32 offset:2780 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v808*/, off, s32 offset:2784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v809*/, off, s32 offset:2788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v810*/, off, s32 offset:2792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v811*/, off, s32 offset:2796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v812*/, off, s32 offset:2800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v813*/, off, s32 offset:2804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v814*/, off, s32 offset:2808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v815*/, off, s32 offset:2812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v816*/, off, s32 offset:2816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v817*/, off, s32 offset:2820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v818*/, off, s32 offset:2824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v819*/, off, s32 offset:2828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v820*/, off, s32 offset:2832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v821*/, off, s32 offset:2836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v822*/, off, s32 offset:2840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v823*/, off, s32 offset:2844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v824*/, off, s32 offset:2848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v825*/, off, s32 offset:2852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v826*/, off, s32 offset:2856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v827*/, off, s32 offset:2860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v828*/, off, s32 offset:2864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v829*/, off, s32 offset:2868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v830*/, off, s32 offset:2872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v831*/, off, s32 offset:2876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v832*/, off, s32 offset:2880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v833*/, off, s32 offset:2884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v834*/, off, s32 offset:2888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v835*/, off, s32 offset:2892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v836*/, off, s32 offset:2896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v837*/, off, s32 offset:2900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v838*/, off, s32 offset:2904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v839*/, off, s32 offset:2908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v840*/, off, s32 offset:2912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v841*/, off, s32 offset:2916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v842*/, off, s32 offset:2920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v843*/, off, s32 offset:2924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v844*/, off, s32 offset:2928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v845*/, off, s32 offset:2932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v846*/, off, s32 offset:2936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v847*/, off, s32 offset:2940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v848*/, off, s32 offset:2944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v849*/, off, s32 offset:2948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v850*/, off, s32 offset:2952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v851*/, off, s32 offset:2956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v852*/, off, s32 offset:2960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v853*/, off, s32 offset:2964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v854*/, off, s32 offset:2968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v855*/, off, s32 offset:2972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v856*/, off, s32 offset:2976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v857*/, off, s32 offset:2980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v858*/, off, s32 offset:2984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v859*/, off, s32 offset:2988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v860*/, off, s32 offset:2992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v861*/, off, s32 offset:2996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v862*/, off, s32 offset:3000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v863*/, off, s32 offset:3004 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v864*/, off, s32 offset:3008 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v865*/, off, s32 offset:3012 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v866*/, off, s32 offset:3016 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v867*/, off, s32 offset:3020 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v868*/, off, s32 offset:3024 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v869*/, off, s32 offset:3028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v870*/, off, s32 offset:3032 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v871*/, off, s32 offset:3036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v872*/, off, s32 offset:3040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v873*/, off, s32 offset:3044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v874*/, off, s32 offset:3048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v875*/, off, s32 offset:3052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v876*/, off, s32 offset:3056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v877*/, off, s32 offset:3060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v878*/, off, s32 offset:3064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v879*/, off, s32 offset:3068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v880*/, off, s32 offset:3072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v881*/, off, s32 offset:3076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v882*/, off, s32 offset:3080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v883*/, off, s32 offset:3084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v884*/, off, s32 offset:3088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v885*/, off, s32 offset:3092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v886*/, off, s32 offset:3096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v887*/, off, s32 offset:3100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v888*/, off, s32 offset:3104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v889*/, off, s32 offset:3108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v890*/, off, s32 offset:3112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v891*/, off, s32 offset:3116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v892*/, off, s32 offset:3120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v893*/, off, s32 offset:3124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v894*/, off, s32 offset:3128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v895*/, off, s32 offset:3132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v896*/, off, s32 offset:3136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v897*/, off, s32 offset:3140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v898*/, off, s32 offset:3144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v899*/, off, s32 offset:3148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v900*/, off, s32 offset:3152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v901*/, off, s32 offset:3156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v902*/, off, s32 offset:3160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v903*/, off, s32 offset:3164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v904*/, off, s32 offset:3168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v905*/, off, s32 offset:3172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v906*/, off, s32 offset:3176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v907*/, off, s32 offset:3180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v908*/, off, s32 offset:3184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v909*/, off, s32 offset:3188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v910*/, off, s32 offset:3192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v911*/, off, s32 offset:3196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v912*/, off, s32 offset:3200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v913*/, off, s32 offset:3204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v914*/, off, s32 offset:3208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v915*/, off, s32 offset:3212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v916*/, off, s32 offset:3216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v917*/, off, s32 offset:3220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v918*/, off, s32 offset:3224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v919*/, off, s32 offset:3228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v920*/, off, s32 offset:3232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v921*/, off, s32 offset:3236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v922*/, off, s32 offset:3240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v923*/, off, s32 offset:3244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v924*/, off, s32 offset:3248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v925*/, off, s32 offset:3252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v926*/, off, s32 offset:3256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v927*/, off, s32 offset:3260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v928*/, off, s32 offset:3264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v929*/, off, s32 offset:3268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v930*/, off, s32 offset:3272 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v868*/, off, s32 offset:3024 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v869*/, off, s32 offset:3028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v870*/, off, s32 offset:3032 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v871*/, off, s32 offset:3036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v872*/, off, s32 offset:3040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v873*/, off, s32 offset:3044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v874*/, off, s32 offset:3048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v875*/, off, s32 offset:3052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v876*/, off, s32 offset:3056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v877*/, off, s32 offset:3060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v878*/, off, s32 offset:3064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v879*/, off, s32 offset:3068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v880*/, off, s32 offset:3072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v881*/, off, s32 offset:3076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v882*/, off, s32 offset:3080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v883*/, off, s32 offset:3084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v884*/, off, s32 offset:3088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v885*/, off, s32 offset:3092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v886*/, off, s32 offset:3096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v887*/, off, s32 offset:3100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v888*/, off, s32 offset:3104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v889*/, off, s32 offset:3108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v890*/, off, s32 offset:3112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v891*/, off, s32 offset:3116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v892*/, off, s32 offset:3120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v893*/, off, s32 offset:3124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v894*/, off, s32 offset:3128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v895*/, off, s32 offset:3132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v896*/, off, s32 offset:3136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v897*/, off, s32 offset:3140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v898*/, off, s32 offset:3144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v899*/, off, s32 offset:3148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v900*/, off, s32 offset:3152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v901*/, off, s32 offset:3156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v902*/, off, s32 offset:3160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v903*/, off, s32 offset:3164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v904*/, off, s32 offset:3168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v905*/, off, s32 offset:3172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v906*/, off, s32 offset:3176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v907*/, off, s32 offset:3180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v908*/, off, s32 offset:3184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v909*/, off, s32 offset:3188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v910*/, off, s32 offset:3192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v911*/, off, s32 offset:3196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v912*/, off, s32 offset:3200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v913*/, off, s32 offset:3204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v914*/, off, s32 offset:3208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v915*/, off, s32 offset:3212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v916*/, off, s32 offset:3216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v917*/, off, s32 offset:3220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v918*/, off, s32 offset:3224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v919*/, off, s32 offset:3228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v920*/, off, s32 offset:3232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v921*/, off, s32 offset:3236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v922*/, off, s32 offset:3240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v923*/, off, s32 offset:3244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v924*/, off, s32 offset:3248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v925*/, off, s32 offset:3252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v926*/, off, s32 offset:3256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v927*/, off, s32 offset:3260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v928*/, off, s32 offset:3264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v929*/, off, s32 offset:3268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v930*/, off, s32 offset:3272 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v931*/, off, s32 offset:3276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v932*/, off, s32 offset:3280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v933*/, off, s32 offset:3284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v934*/, off, s32 offset:3288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v935*/, off, s32 offset:3292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v936*/, off, s32 offset:3296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v937*/, off, s32 offset:3300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v938*/, off, s32 offset:3304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v939*/, off, s32 offset:3308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v940*/, off, s32 offset:3312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v941*/, off, s32 offset:3316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v942*/, off, s32 offset:3320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v943*/, off, s32 offset:3324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v944*/, off, s32 offset:3328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v945*/, off, s32 offset:3332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v946*/, off, s32 offset:3336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v947*/, off, s32 offset:3340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v948*/, off, s32 offset:3344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v949*/, off, s32 offset:3348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v950*/, off, s32 offset:3352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v951*/, off, s32 offset:3356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v952*/, off, s32 offset:3360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v953*/, off, s32 offset:3364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v954*/, off, s32 offset:3368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v955*/, off, s32 offset:3372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v956*/, off, s32 offset:3376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v957*/, off, s32 offset:3380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v958*/, off, s32 offset:3384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v959*/, off, s32 offset:3388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v960*/, off, s32 offset:3392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v961*/, off, s32 offset:3396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v962*/, off, s32 offset:3400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v963*/, off, s32 offset:3404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v964*/, off, s32 offset:3408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v965*/, off, s32 offset:3412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v966*/, off, s32 offset:3416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v967*/, off, s32 offset:3420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v968*/, off, s32 offset:3424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v969*/, off, s32 offset:3428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v970*/, off, s32 offset:3432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v971*/, off, s32 offset:3436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v972*/, off, s32 offset:3440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v973*/, off, s32 offset:3444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v974*/, off, s32 offset:3448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v975*/, off, s32 offset:3452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v976*/, off, s32 offset:3456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v977*/, off, s32 offset:3460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v978*/, off, s32 offset:3464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v979*/, off, s32 offset:3468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v980*/, off, s32 offset:3472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v981*/, off, s32 offset:3476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v982*/, off, s32 offset:3480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v983*/, off, s32 offset:3484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v984*/, off, s32 offset:3488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v985*/, off, s32 offset:3492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v986*/, off, s32 offset:3496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v987*/, off, s32 offset:3500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v988*/, off, s32 offset:3504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v989*/, off, s32 offset:3508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v990*/, off, s32 offset:3512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v991*/, off, s32 offset:3516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v992*/, off, s32 offset:3520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v993*/, off, s32 offset:3524 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v931*/, off, s32 offset:3276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v932*/, off, s32 offset:3280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v933*/, off, s32 offset:3284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v934*/, off, s32 offset:3288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v935*/, off, s32 offset:3292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v936*/, off, s32 offset:3296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v937*/, off, s32 offset:3300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v938*/, off, s32 offset:3304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v939*/, off, s32 offset:3308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v940*/, off, s32 offset:3312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v941*/, off, s32 offset:3316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v942*/, off, s32 offset:3320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v943*/, off, s32 offset:3324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v944*/, off, s32 offset:3328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v945*/, off, s32 offset:3332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v946*/, off, s32 offset:3336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v947*/, off, s32 offset:3340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v948*/, off, s32 offset:3344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v949*/, off, s32 offset:3348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v950*/, off, s32 offset:3352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v951*/, off, s32 offset:3356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v952*/, off, s32 offset:3360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v953*/, off, s32 offset:3364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v954*/, off, s32 offset:3368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v955*/, off, s32 offset:3372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v956*/, off, s32 offset:3376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v957*/, off, s32 offset:3380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v958*/, off, s32 offset:3384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v959*/, off, s32 offset:3388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v960*/, off, s32 offset:3392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v961*/, off, s32 offset:3396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v962*/, off, s32 offset:3400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v963*/, off, s32 offset:3404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v964*/, off, s32 offset:3408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v965*/, off, s32 offset:3412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v966*/, off, s32 offset:3416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v967*/, off, s32 offset:3420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v968*/, off, s32 offset:3424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v969*/, off, s32 offset:3428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v970*/, off, s32 offset:3432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v971*/, off, s32 offset:3436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v972*/, off, s32 offset:3440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v973*/, off, s32 offset:3444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v974*/, off, s32 offset:3448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v975*/, off, s32 offset:3452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v976*/, off, s32 offset:3456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v977*/, off, s32 offset:3460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v978*/, off, s32 offset:3464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v979*/, off, s32 offset:3468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v980*/, off, s32 offset:3472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v981*/, off, s32 offset:3476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v982*/, off, s32 offset:3480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v983*/, off, s32 offset:3484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v984*/, off, s32 offset:3488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v985*/, off, s32 offset:3492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v986*/, off, s32 offset:3496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v987*/, off, s32 offset:3500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v988*/, off, s32 offset:3504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v989*/, off, s32 offset:3508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v990*/, off, s32 offset:3512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v991*/, off, s32 offset:3516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v992*/, off, s32 offset:3520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v993*/, off, s32 offset:3524 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; 120-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v994*/, off, s32 offset:3528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v995*/, off, s32 offset:3532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v996*/, off, s32 offset:3536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v997*/, off, s32 offset:3540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v998*/, off, s32 offset:3544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v999*/, off, s32 offset:3548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v1000*/, off, s32 offset:3552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v1001*/, off, s32 offset:3556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v1002*/, off, s32 offset:3560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v1003*/, off, s32 offset:3564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v1004*/, off, s32 offset:3568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v1005*/, off, s32 offset:3572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v1006*/, off, s32 offset:3576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v1007*/, off, s32 offset:3580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v1008*/, off, s32 offset:3584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v1009*/, off, s32 offset:3588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v1010*/, off, s32 offset:3592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v1011*/, off, s32 offset:3596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v1012*/, off, s32 offset:3600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v1013*/, off, s32 offset:3604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v1014*/, off, s32 offset:3608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v1015*/, off, s32 offset:3612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v1016*/, off, s32 offset:3616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v1017*/, off, s32 offset:3620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v1018*/, off, s32 offset:3624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v1019*/, off, s32 offset:3628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v1020*/, off, s32 offset:3632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v1021*/, off, s32 offset:3636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v1022*/, off, s32 offset:3640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v1023*/, off, s32 offset:3644 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v994*/, off, s32 offset:3528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v995*/, off, s32 offset:3532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v996*/, off, s32 offset:3536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v997*/, off, s32 offset:3540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v998*/, off, s32 offset:3544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v999*/, off, s32 offset:3548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v1000*/, off, s32 offset:3552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v1001*/, off, s32 offset:3556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v1002*/, off, s32 offset:3560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v1003*/, off, s32 offset:3564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v1004*/, off, s32 offset:3568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v1005*/, off, s32 offset:3572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v1006*/, off, s32 offset:3576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v1007*/, off, s32 offset:3580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v1008*/, off, s32 offset:3584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v1009*/, off, s32 offset:3588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v1010*/, off, s32 offset:3592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v1011*/, off, s32 offset:3596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v1012*/, off, s32 offset:3600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v1013*/, off, s32 offset:3604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v1014*/, off, s32 offset:3608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v1015*/, off, s32 offset:3612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v1016*/, off, s32 offset:3616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v1017*/, off, s32 offset:3620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v1018*/, off, s32 offset:3624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v1019*/, off, s32 offset:3628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v1020*/, off, s32 offset:3632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v1021*/, off, s32 offset:3636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v1022*/, off, s32 offset:3640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v1023*/, off, s32 offset:3644 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, s0 ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0xc000 ; msbs: dst=0 src0=0 src1=0 src2=0 @@ -9251,942 +9251,942 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> ; GFX1250-DAGISEL-NEXT: s_mov_b32 s33, s32 ; GFX1250-DAGISEL-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:260 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0, s33 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1, s33 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2, s33 offset:12 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3, s33 offset:16 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4, s33 offset:20 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5, s33 offset:24 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6, s33 offset:28 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7, s33 offset:32 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8, s33 offset:36 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9, s33 offset:40 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10, s33 offset:44 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11, s33 offset:48 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12, s33 offset:52 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13, s33 offset:56 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14, s33 offset:60 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15, s33 offset:64 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16, s33 offset:68 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17, s33 offset:72 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18, s33 offset:76 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19, s33 offset:80 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20, s33 offset:84 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21, s33 offset:88 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22, s33 offset:92 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23, s33 offset:96 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24, s33 offset:100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25, s33 offset:104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26, s33 offset:108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27, s33 offset:112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28, s33 offset:116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29, s33 offset:120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30, s33 offset:124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31, s33 offset:128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32, s33 offset:132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33, s33 offset:136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34, s33 offset:140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35, s33 offset:144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36, s33 offset:148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37, s33 offset:152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38, s33 offset:156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39, s33 offset:160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48, s33 offset:172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49, s33 offset:176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50, s33 offset:180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51, s33 offset:184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52, s33 offset:188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53, s33 offset:192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54, s33 offset:196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55, s33 offset:200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64, s33 offset:204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65, s33 offset:208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66, s33 offset:212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67, s33 offset:216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68, s33 offset:220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69, s33 offset:224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70, s33 offset:228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71, s33 offset:232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80, s33 offset:236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81, s33 offset:240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82, s33 offset:244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83, s33 offset:248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84, s33 offset:252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85, s33 offset:256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86, s33 offset:260 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:512 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87, s33 offset:264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96, s33 offset:268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97, s33 offset:272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98, s33 offset:276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99, s33 offset:280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100, s33 offset:284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101, s33 offset:288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102, s33 offset:292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103, s33 offset:296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112, s33 offset:300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113, s33 offset:304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114, s33 offset:308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115, s33 offset:312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116, s33 offset:316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117, s33 offset:320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118, s33 offset:324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119, s33 offset:328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128, s33 offset:332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129, s33 offset:336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130, s33 offset:340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131, s33 offset:344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132, s33 offset:348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133, s33 offset:352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134, s33 offset:356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135, s33 offset:360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144, s33 offset:364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145, s33 offset:368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146, s33 offset:372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147, s33 offset:376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148, s33 offset:380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149, s33 offset:384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150, s33 offset:388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151, s33 offset:392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160, s33 offset:396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161, s33 offset:400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162, s33 offset:404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163, s33 offset:408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164, s33 offset:412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165, s33 offset:416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166, s33 offset:420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167, s33 offset:424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176, s33 offset:428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177, s33 offset:432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178, s33 offset:436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179, s33 offset:440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180, s33 offset:444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181, s33 offset:448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182, s33 offset:452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183, s33 offset:456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192, s33 offset:460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193, s33 offset:464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194, s33 offset:468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195, s33 offset:472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196, s33 offset:476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197, s33 offset:480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198, s33 offset:484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199, s33 offset:488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208, s33 offset:492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209, s33 offset:496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210, s33 offset:500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211, s33 offset:504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212, s33 offset:508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213, s33 offset:512 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:584 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214, s33 offset:516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215, s33 offset:520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224, s33 offset:524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225, s33 offset:528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226, s33 offset:532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227, s33 offset:536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228, s33 offset:540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229, s33 offset:544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230, s33 offset:548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231, s33 offset:552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240, s33 offset:556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241, s33 offset:560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242, s33 offset:564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243, s33 offset:568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244, s33 offset:572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245, s33 offset:576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246, s33 offset:580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247, s33 offset:584 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 4 ; msbs: dst=0 src0=0 src1=1 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:752 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:756 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:760 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:764 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v256*/, s33 offset:588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v257*/, s33 offset:592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v258*/, s33 offset:596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v259*/, s33 offset:600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v260*/, s33 offset:604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v261*/, s33 offset:608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v262*/, s33 offset:612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v263*/, s33 offset:616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v264*/, s33 offset:620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v265*/, s33 offset:624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v266*/, s33 offset:628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v267*/, s33 offset:632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v268*/, s33 offset:636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v269*/, s33 offset:640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v270*/, s33 offset:644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v271*/, s33 offset:648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v272*/, s33 offset:652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v273*/, s33 offset:656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v274*/, s33 offset:660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v275*/, s33 offset:664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v276*/, s33 offset:668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v277*/, s33 offset:672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v278*/, s33 offset:676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v279*/, s33 offset:680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v280*/, s33 offset:684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v281*/, s33 offset:688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v282*/, s33 offset:692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v283*/, s33 offset:696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v284*/, s33 offset:700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v285*/, s33 offset:704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v286*/, s33 offset:708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v287*/, s33 offset:712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v288*/, s33 offset:716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v289*/, s33 offset:720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v290*/, s33 offset:724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v291*/, s33 offset:728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v292*/, s33 offset:732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v293*/, s33 offset:736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v294*/, s33 offset:740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v295*/, s33 offset:744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v296*/, s33 offset:748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v297*/, s33 offset:752 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v298*/, s33 offset:756 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v299*/, s33 offset:760 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v300*/, s33 offset:764 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:768 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:772 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:780 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:1000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:1004 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1008 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1012 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1016 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v301*/, s33 offset:768 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v302*/, s33 offset:772 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v303*/, s33 offset:776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v304*/, s33 offset:780 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v305*/, s33 offset:784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v306*/, s33 offset:788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v307*/, s33 offset:792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v308*/, s33 offset:796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v309*/, s33 offset:800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v310*/, s33 offset:804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v311*/, s33 offset:808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v312*/, s33 offset:812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v313*/, s33 offset:816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v314*/, s33 offset:820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v315*/, s33 offset:824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v316*/, s33 offset:828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v317*/, s33 offset:832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v318*/, s33 offset:836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v319*/, s33 offset:840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v320*/, s33 offset:844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v321*/, s33 offset:848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v322*/, s33 offset:852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v323*/, s33 offset:856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v324*/, s33 offset:860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v325*/, s33 offset:864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v326*/, s33 offset:868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v327*/, s33 offset:872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v328*/, s33 offset:876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v329*/, s33 offset:880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v330*/, s33 offset:884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v331*/, s33 offset:888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v332*/, s33 offset:892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v333*/, s33 offset:896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v334*/, s33 offset:900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v335*/, s33 offset:904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v336*/, s33 offset:908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v337*/, s33 offset:912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v338*/, s33 offset:916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v339*/, s33 offset:920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v340*/, s33 offset:924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v341*/, s33 offset:928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v342*/, s33 offset:932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v343*/, s33 offset:936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v344*/, s33 offset:940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v345*/, s33 offset:944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v346*/, s33 offset:948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v347*/, s33 offset:952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v348*/, s33 offset:956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v349*/, s33 offset:960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v350*/, s33 offset:964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v351*/, s33 offset:968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v352*/, s33 offset:972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v353*/, s33 offset:976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v354*/, s33 offset:980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v355*/, s33 offset:984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v356*/, s33 offset:988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v357*/, s33 offset:992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v358*/, s33 offset:996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v359*/, s33 offset:1000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v360*/, s33 offset:1004 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v361*/, s33 offset:1008 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v362*/, s33 offset:1012 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v363*/, s33 offset:1016 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1020 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1024 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1032 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1268 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v364*/, s33 offset:1020 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v365*/, s33 offset:1024 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v366*/, s33 offset:1028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v367*/, s33 offset:1032 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v368*/, s33 offset:1036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v369*/, s33 offset:1040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v370*/, s33 offset:1044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v371*/, s33 offset:1048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v372*/, s33 offset:1052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v373*/, s33 offset:1056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v374*/, s33 offset:1060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v375*/, s33 offset:1064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v376*/, s33 offset:1068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v377*/, s33 offset:1072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v378*/, s33 offset:1076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v379*/, s33 offset:1080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v380*/, s33 offset:1084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v381*/, s33 offset:1088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v382*/, s33 offset:1092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v383*/, s33 offset:1096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v384*/, s33 offset:1100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v385*/, s33 offset:1104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v386*/, s33 offset:1108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v387*/, s33 offset:1112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v388*/, s33 offset:1116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v389*/, s33 offset:1120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v390*/, s33 offset:1124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v391*/, s33 offset:1128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v392*/, s33 offset:1132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v393*/, s33 offset:1136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v394*/, s33 offset:1140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v395*/, s33 offset:1144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v396*/, s33 offset:1148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v397*/, s33 offset:1152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v398*/, s33 offset:1156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v399*/, s33 offset:1160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v400*/, s33 offset:1164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v401*/, s33 offset:1168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v402*/, s33 offset:1172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v403*/, s33 offset:1176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v404*/, s33 offset:1180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v405*/, s33 offset:1184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v406*/, s33 offset:1188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v407*/, s33 offset:1192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v408*/, s33 offset:1196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v409*/, s33 offset:1200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v410*/, s33 offset:1204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v411*/, s33 offset:1208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v412*/, s33 offset:1212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v413*/, s33 offset:1216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v414*/, s33 offset:1220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v415*/, s33 offset:1224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v416*/, s33 offset:1228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v417*/, s33 offset:1232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v418*/, s33 offset:1236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v419*/, s33 offset:1240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v420*/, s33 offset:1244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v421*/, s33 offset:1248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v422*/, s33 offset:1252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v423*/, s33 offset:1256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v424*/, s33 offset:1260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v425*/, s33 offset:1264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v426*/, s33 offset:1268 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1520 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v427*/, s33 offset:1272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v428*/, s33 offset:1276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v429*/, s33 offset:1280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v430*/, s33 offset:1284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v431*/, s33 offset:1288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v432*/, s33 offset:1292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v433*/, s33 offset:1296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v434*/, s33 offset:1300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v435*/, s33 offset:1304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v436*/, s33 offset:1308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v437*/, s33 offset:1312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v438*/, s33 offset:1316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v439*/, s33 offset:1320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v440*/, s33 offset:1324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v441*/, s33 offset:1328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v442*/, s33 offset:1332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v443*/, s33 offset:1336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v444*/, s33 offset:1340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v445*/, s33 offset:1344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v446*/, s33 offset:1348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v447*/, s33 offset:1352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v448*/, s33 offset:1356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v449*/, s33 offset:1360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v450*/, s33 offset:1364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v451*/, s33 offset:1368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v452*/, s33 offset:1372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v453*/, s33 offset:1376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v454*/, s33 offset:1380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v455*/, s33 offset:1384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v456*/, s33 offset:1388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v457*/, s33 offset:1392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v458*/, s33 offset:1396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v459*/, s33 offset:1400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v460*/, s33 offset:1404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v461*/, s33 offset:1408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v462*/, s33 offset:1412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v463*/, s33 offset:1416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v464*/, s33 offset:1420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v465*/, s33 offset:1424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v466*/, s33 offset:1428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v467*/, s33 offset:1432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v468*/, s33 offset:1436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v469*/, s33 offset:1440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v470*/, s33 offset:1444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v471*/, s33 offset:1448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v472*/, s33 offset:1452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v473*/, s33 offset:1456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v474*/, s33 offset:1460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v475*/, s33 offset:1464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v476*/, s33 offset:1468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v477*/, s33 offset:1472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v478*/, s33 offset:1476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v479*/, s33 offset:1480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v480*/, s33 offset:1484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v481*/, s33 offset:1488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v482*/, s33 offset:1492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v483*/, s33 offset:1496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v484*/, s33 offset:1500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v485*/, s33 offset:1504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v486*/, s33 offset:1508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v487*/, s33 offset:1512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v488*/, s33 offset:1516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v489*/, s33 offset:1520 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1608 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v490*/, s33 offset:1524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v491*/, s33 offset:1528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v492*/, s33 offset:1532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v493*/, s33 offset:1536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v494*/, s33 offset:1540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v495*/, s33 offset:1544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v496*/, s33 offset:1548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v497*/, s33 offset:1552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v498*/, s33 offset:1556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v499*/, s33 offset:1560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v500*/, s33 offset:1564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v501*/, s33 offset:1568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v502*/, s33 offset:1572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v503*/, s33 offset:1576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v504*/, s33 offset:1580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v505*/, s33 offset:1584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v506*/, s33 offset:1588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v507*/, s33 offset:1592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v508*/, s33 offset:1596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v509*/, s33 offset:1600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v510*/, s33 offset:1604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v511*/, s33 offset:1608 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x408 ; msbs: dst=0 src0=0 src1=2 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1752 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1756 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1760 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1764 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1768 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1772 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v512*/, s33 offset:1612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v513*/, s33 offset:1616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v514*/, s33 offset:1620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v515*/, s33 offset:1624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v516*/, s33 offset:1628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v517*/, s33 offset:1632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v518*/, s33 offset:1636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v519*/, s33 offset:1640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v520*/, s33 offset:1644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v521*/, s33 offset:1648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v522*/, s33 offset:1652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v523*/, s33 offset:1656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v524*/, s33 offset:1660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v525*/, s33 offset:1664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v526*/, s33 offset:1668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v527*/, s33 offset:1672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v528*/, s33 offset:1676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v529*/, s33 offset:1680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v530*/, s33 offset:1684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v531*/, s33 offset:1688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v532*/, s33 offset:1692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v533*/, s33 offset:1696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v534*/, s33 offset:1700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v535*/, s33 offset:1704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v536*/, s33 offset:1708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v537*/, s33 offset:1712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v538*/, s33 offset:1716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v539*/, s33 offset:1720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v540*/, s33 offset:1724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v541*/, s33 offset:1728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v542*/, s33 offset:1732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v543*/, s33 offset:1736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v544*/, s33 offset:1740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v545*/, s33 offset:1744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v546*/, s33 offset:1748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v547*/, s33 offset:1752 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v548*/, s33 offset:1756 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v549*/, s33 offset:1760 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v550*/, s33 offset:1764 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v551*/, s33 offset:1768 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v552*/, s33 offset:1772 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1780 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:2000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:2004 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2008 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2012 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2016 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2020 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2024 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v553*/, s33 offset:1776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v554*/, s33 offset:1780 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v555*/, s33 offset:1784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v556*/, s33 offset:1788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v557*/, s33 offset:1792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v558*/, s33 offset:1796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v559*/, s33 offset:1800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v560*/, s33 offset:1804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v561*/, s33 offset:1808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v562*/, s33 offset:1812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v563*/, s33 offset:1816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v564*/, s33 offset:1820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v565*/, s33 offset:1824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v566*/, s33 offset:1828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v567*/, s33 offset:1832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v568*/, s33 offset:1836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v569*/, s33 offset:1840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v570*/, s33 offset:1844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v571*/, s33 offset:1848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v572*/, s33 offset:1852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v573*/, s33 offset:1856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v574*/, s33 offset:1860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v575*/, s33 offset:1864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v576*/, s33 offset:1868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v577*/, s33 offset:1872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v578*/, s33 offset:1876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v579*/, s33 offset:1880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v580*/, s33 offset:1884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v581*/, s33 offset:1888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v582*/, s33 offset:1892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v583*/, s33 offset:1896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v584*/, s33 offset:1900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v585*/, s33 offset:1904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v586*/, s33 offset:1908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v587*/, s33 offset:1912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v588*/, s33 offset:1916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v589*/, s33 offset:1920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v590*/, s33 offset:1924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v591*/, s33 offset:1928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v592*/, s33 offset:1932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v593*/, s33 offset:1936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v594*/, s33 offset:1940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v595*/, s33 offset:1944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v596*/, s33 offset:1948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v597*/, s33 offset:1952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v598*/, s33 offset:1956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v599*/, s33 offset:1960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v600*/, s33 offset:1964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v601*/, s33 offset:1968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v602*/, s33 offset:1972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v603*/, s33 offset:1976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v604*/, s33 offset:1980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v605*/, s33 offset:1984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v606*/, s33 offset:1988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v607*/, s33 offset:1992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v608*/, s33 offset:1996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v609*/, s33 offset:2000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v610*/, s33 offset:2004 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v611*/, s33 offset:2008 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v612*/, s33 offset:2012 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v613*/, s33 offset:2016 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v614*/, s33 offset:2020 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v615*/, s33 offset:2024 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2032 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2276 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v616*/, s33 offset:2028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v617*/, s33 offset:2032 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v618*/, s33 offset:2036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v619*/, s33 offset:2040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v620*/, s33 offset:2044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v621*/, s33 offset:2048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v622*/, s33 offset:2052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v623*/, s33 offset:2056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v624*/, s33 offset:2060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v625*/, s33 offset:2064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v626*/, s33 offset:2068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v627*/, s33 offset:2072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v628*/, s33 offset:2076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v629*/, s33 offset:2080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v630*/, s33 offset:2084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v631*/, s33 offset:2088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v632*/, s33 offset:2092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v633*/, s33 offset:2096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v634*/, s33 offset:2100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v635*/, s33 offset:2104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v636*/, s33 offset:2108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v637*/, s33 offset:2112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v638*/, s33 offset:2116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v639*/, s33 offset:2120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v640*/, s33 offset:2124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v641*/, s33 offset:2128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v642*/, s33 offset:2132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v643*/, s33 offset:2136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v644*/, s33 offset:2140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v645*/, s33 offset:2144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v646*/, s33 offset:2148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v647*/, s33 offset:2152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v648*/, s33 offset:2156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v649*/, s33 offset:2160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v650*/, s33 offset:2164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v651*/, s33 offset:2168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v652*/, s33 offset:2172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v653*/, s33 offset:2176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v654*/, s33 offset:2180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v655*/, s33 offset:2184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v656*/, s33 offset:2188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v657*/, s33 offset:2192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v658*/, s33 offset:2196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v659*/, s33 offset:2200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v660*/, s33 offset:2204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v661*/, s33 offset:2208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v662*/, s33 offset:2212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v663*/, s33 offset:2216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v664*/, s33 offset:2220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v665*/, s33 offset:2224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v666*/, s33 offset:2228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v667*/, s33 offset:2232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v668*/, s33 offset:2236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v669*/, s33 offset:2240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v670*/, s33 offset:2244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v671*/, s33 offset:2248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v672*/, s33 offset:2252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v673*/, s33 offset:2256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v674*/, s33 offset:2260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v675*/, s33 offset:2264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v676*/, s33 offset:2268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v677*/, s33 offset:2272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v678*/, s33 offset:2276 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2284 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2528 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v679*/, s33 offset:2280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v680*/, s33 offset:2284 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v681*/, s33 offset:2288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v682*/, s33 offset:2292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v683*/, s33 offset:2296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v684*/, s33 offset:2300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v685*/, s33 offset:2304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v686*/, s33 offset:2308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v687*/, s33 offset:2312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v688*/, s33 offset:2316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v689*/, s33 offset:2320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v690*/, s33 offset:2324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v691*/, s33 offset:2328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v692*/, s33 offset:2332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v693*/, s33 offset:2336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v694*/, s33 offset:2340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v695*/, s33 offset:2344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v696*/, s33 offset:2348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v697*/, s33 offset:2352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v698*/, s33 offset:2356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v699*/, s33 offset:2360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v700*/, s33 offset:2364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v701*/, s33 offset:2368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v702*/, s33 offset:2372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v703*/, s33 offset:2376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v704*/, s33 offset:2380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v705*/, s33 offset:2384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v706*/, s33 offset:2388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v707*/, s33 offset:2392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v708*/, s33 offset:2396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v709*/, s33 offset:2400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v710*/, s33 offset:2404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v711*/, s33 offset:2408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v712*/, s33 offset:2412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v713*/, s33 offset:2416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v714*/, s33 offset:2420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v715*/, s33 offset:2424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v716*/, s33 offset:2428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v717*/, s33 offset:2432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v718*/, s33 offset:2436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v719*/, s33 offset:2440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v720*/, s33 offset:2444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v721*/, s33 offset:2448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v722*/, s33 offset:2452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v723*/, s33 offset:2456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v724*/, s33 offset:2460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v725*/, s33 offset:2464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v726*/, s33 offset:2468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v727*/, s33 offset:2472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v728*/, s33 offset:2476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v729*/, s33 offset:2480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v730*/, s33 offset:2484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v731*/, s33 offset:2488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v732*/, s33 offset:2492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v733*/, s33 offset:2496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v734*/, s33 offset:2500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v735*/, s33 offset:2504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v736*/, s33 offset:2508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v737*/, s33 offset:2512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v738*/, s33 offset:2516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v739*/, s33 offset:2520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v740*/, s33 offset:2524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v741*/, s33 offset:2528 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2536 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2632 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v742*/, s33 offset:2532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v743*/, s33 offset:2536 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v744*/, s33 offset:2540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v745*/, s33 offset:2544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v746*/, s33 offset:2548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v747*/, s33 offset:2552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v748*/, s33 offset:2556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v749*/, s33 offset:2560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v750*/, s33 offset:2564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v751*/, s33 offset:2568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v752*/, s33 offset:2572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v753*/, s33 offset:2576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v754*/, s33 offset:2580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v755*/, s33 offset:2584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v756*/, s33 offset:2588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v757*/, s33 offset:2592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v758*/, s33 offset:2596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v759*/, s33 offset:2600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v760*/, s33 offset:2604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v761*/, s33 offset:2608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v762*/, s33 offset:2612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v763*/, s33 offset:2616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v764*/, s33 offset:2620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v765*/, s33 offset:2624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v766*/, s33 offset:2628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v767*/, s33 offset:2632 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x80c ; msbs: dst=0 src0=0 src1=3 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2656 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2660 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2664 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2668 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2672 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2676 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2680 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2684 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2688 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2692 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2696 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2700 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2704 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2708 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2712 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2716 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2720 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2724 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2728 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2732 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2736 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2740 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2744 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2748 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2752 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2756 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2760 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2764 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2768 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2772 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2776 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2780 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v0 /*v768*/, s33 offset:2636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v1 /*v769*/, s33 offset:2640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v2 /*v770*/, s33 offset:2644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v3 /*v771*/, s33 offset:2648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v4 /*v772*/, s33 offset:2652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v5 /*v773*/, s33 offset:2656 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v6 /*v774*/, s33 offset:2660 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v7 /*v775*/, s33 offset:2664 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v8 /*v776*/, s33 offset:2668 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v9 /*v777*/, s33 offset:2672 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v10 /*v778*/, s33 offset:2676 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v11 /*v779*/, s33 offset:2680 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v12 /*v780*/, s33 offset:2684 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v13 /*v781*/, s33 offset:2688 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v14 /*v782*/, s33 offset:2692 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v15 /*v783*/, s33 offset:2696 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v16 /*v784*/, s33 offset:2700 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v17 /*v785*/, s33 offset:2704 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v18 /*v786*/, s33 offset:2708 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v19 /*v787*/, s33 offset:2712 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v20 /*v788*/, s33 offset:2716 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v21 /*v789*/, s33 offset:2720 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v22 /*v790*/, s33 offset:2724 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v23 /*v791*/, s33 offset:2728 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v24 /*v792*/, s33 offset:2732 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v25 /*v793*/, s33 offset:2736 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v26 /*v794*/, s33 offset:2740 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v27 /*v795*/, s33 offset:2744 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v28 /*v796*/, s33 offset:2748 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v29 /*v797*/, s33 offset:2752 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v30 /*v798*/, s33 offset:2756 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v31 /*v799*/, s33 offset:2760 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v32 /*v800*/, s33 offset:2764 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v33 /*v801*/, s33 offset:2768 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v34 /*v802*/, s33 offset:2772 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v35 /*v803*/, s33 offset:2776 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v36 /*v804*/, s33 offset:2780 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2784 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2788 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2792 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2796 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2800 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2804 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2808 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2812 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2816 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2820 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2824 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2828 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2832 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2836 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2840 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2844 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2848 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2852 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2856 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2860 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2864 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2868 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2872 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2876 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2880 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2884 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2888 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2892 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2896 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2900 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2904 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2908 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2912 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2916 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2920 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2924 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2928 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2932 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2936 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2940 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2944 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2948 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2952 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2956 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2960 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2964 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2968 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2972 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2976 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2980 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2984 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2988 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2992 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2996 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:3000 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:3004 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3008 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3012 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3016 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3020 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3024 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3028 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3032 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v37 /*v805*/, s33 offset:2784 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v38 /*v806*/, s33 offset:2788 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v39 /*v807*/, s33 offset:2792 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40 /*v808*/, s33 offset:2796 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41 /*v809*/, s33 offset:2800 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42 /*v810*/, s33 offset:2804 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v43 /*v811*/, s33 offset:2808 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v44 /*v812*/, s33 offset:2812 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v45 /*v813*/, s33 offset:2816 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v46 /*v814*/, s33 offset:2820 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v47 /*v815*/, s33 offset:2824 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v48 /*v816*/, s33 offset:2828 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v49 /*v817*/, s33 offset:2832 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v50 /*v818*/, s33 offset:2836 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v51 /*v819*/, s33 offset:2840 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v52 /*v820*/, s33 offset:2844 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v53 /*v821*/, s33 offset:2848 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v54 /*v822*/, s33 offset:2852 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v55 /*v823*/, s33 offset:2856 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v56 /*v824*/, s33 offset:2860 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v57 /*v825*/, s33 offset:2864 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v58 /*v826*/, s33 offset:2868 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v59 /*v827*/, s33 offset:2872 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v60 /*v828*/, s33 offset:2876 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v61 /*v829*/, s33 offset:2880 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v62 /*v830*/, s33 offset:2884 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v63 /*v831*/, s33 offset:2888 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v64 /*v832*/, s33 offset:2892 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v65 /*v833*/, s33 offset:2896 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v66 /*v834*/, s33 offset:2900 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v67 /*v835*/, s33 offset:2904 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v68 /*v836*/, s33 offset:2908 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v69 /*v837*/, s33 offset:2912 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v70 /*v838*/, s33 offset:2916 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v71 /*v839*/, s33 offset:2920 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v72 /*v840*/, s33 offset:2924 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v73 /*v841*/, s33 offset:2928 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v74 /*v842*/, s33 offset:2932 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v75 /*v843*/, s33 offset:2936 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v76 /*v844*/, s33 offset:2940 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v77 /*v845*/, s33 offset:2944 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v78 /*v846*/, s33 offset:2948 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v79 /*v847*/, s33 offset:2952 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v80 /*v848*/, s33 offset:2956 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v81 /*v849*/, s33 offset:2960 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v82 /*v850*/, s33 offset:2964 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v83 /*v851*/, s33 offset:2968 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v84 /*v852*/, s33 offset:2972 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v85 /*v853*/, s33 offset:2976 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v86 /*v854*/, s33 offset:2980 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v87 /*v855*/, s33 offset:2984 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v88 /*v856*/, s33 offset:2988 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v89 /*v857*/, s33 offset:2992 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v90 /*v858*/, s33 offset:2996 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v91 /*v859*/, s33 offset:3000 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v92 /*v860*/, s33 offset:3004 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v93 /*v861*/, s33 offset:3008 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v94 /*v862*/, s33 offset:3012 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v95 /*v863*/, s33 offset:3016 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v96 /*v864*/, s33 offset:3020 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v97 /*v865*/, s33 offset:3024 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v98 /*v866*/, s33 offset:3028 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v99 /*v867*/, s33 offset:3032 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3036 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3040 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3044 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3048 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3052 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3056 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3060 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3064 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3068 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3072 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3076 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3080 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3084 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3088 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3092 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3096 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3100 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3104 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3108 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3112 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3116 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3120 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3124 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3128 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3132 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3136 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3140 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3144 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3148 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3152 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3156 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3160 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3168 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3172 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3176 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3180 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3184 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3188 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3192 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3196 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3200 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3204 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3208 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3212 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3216 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3220 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3224 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3228 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3232 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3236 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3240 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3244 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3248 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3252 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3256 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3260 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3264 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3268 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3272 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3276 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3280 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3284 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v100 /*v868*/, s33 offset:3036 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v101 /*v869*/, s33 offset:3040 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v102 /*v870*/, s33 offset:3044 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v103 /*v871*/, s33 offset:3048 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v104 /*v872*/, s33 offset:3052 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v105 /*v873*/, s33 offset:3056 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v106 /*v874*/, s33 offset:3060 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v107 /*v875*/, s33 offset:3064 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v108 /*v876*/, s33 offset:3068 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v109 /*v877*/, s33 offset:3072 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v110 /*v878*/, s33 offset:3076 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v111 /*v879*/, s33 offset:3080 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v112 /*v880*/, s33 offset:3084 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v113 /*v881*/, s33 offset:3088 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v114 /*v882*/, s33 offset:3092 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v115 /*v883*/, s33 offset:3096 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v116 /*v884*/, s33 offset:3100 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v117 /*v885*/, s33 offset:3104 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v118 /*v886*/, s33 offset:3108 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v119 /*v887*/, s33 offset:3112 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v120 /*v888*/, s33 offset:3116 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v121 /*v889*/, s33 offset:3120 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v122 /*v890*/, s33 offset:3124 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v123 /*v891*/, s33 offset:3128 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v124 /*v892*/, s33 offset:3132 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v125 /*v893*/, s33 offset:3136 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v126 /*v894*/, s33 offset:3140 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v127 /*v895*/, s33 offset:3144 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v128 /*v896*/, s33 offset:3148 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v129 /*v897*/, s33 offset:3152 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v130 /*v898*/, s33 offset:3156 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v131 /*v899*/, s33 offset:3160 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v132 /*v900*/, s33 offset:3164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v133 /*v901*/, s33 offset:3168 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v134 /*v902*/, s33 offset:3172 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v135 /*v903*/, s33 offset:3176 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v136 /*v904*/, s33 offset:3180 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v137 /*v905*/, s33 offset:3184 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v138 /*v906*/, s33 offset:3188 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v139 /*v907*/, s33 offset:3192 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v140 /*v908*/, s33 offset:3196 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v141 /*v909*/, s33 offset:3200 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v142 /*v910*/, s33 offset:3204 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v143 /*v911*/, s33 offset:3208 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v144 /*v912*/, s33 offset:3212 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v145 /*v913*/, s33 offset:3216 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v146 /*v914*/, s33 offset:3220 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v147 /*v915*/, s33 offset:3224 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v148 /*v916*/, s33 offset:3228 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v149 /*v917*/, s33 offset:3232 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v150 /*v918*/, s33 offset:3236 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v151 /*v919*/, s33 offset:3240 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v152 /*v920*/, s33 offset:3244 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v153 /*v921*/, s33 offset:3248 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v154 /*v922*/, s33 offset:3252 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v155 /*v923*/, s33 offset:3256 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v156 /*v924*/, s33 offset:3260 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v157 /*v925*/, s33 offset:3264 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v158 /*v926*/, s33 offset:3268 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v159 /*v927*/, s33 offset:3272 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v160 /*v928*/, s33 offset:3276 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v161 /*v929*/, s33 offset:3280 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v162 /*v930*/, s33 offset:3284 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3288 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3292 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3296 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3300 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3304 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3308 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3312 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3316 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3320 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3324 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3328 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3332 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3336 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3340 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3344 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3348 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3352 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3356 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3360 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3364 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3368 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3372 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3376 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3380 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3384 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3388 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3392 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3396 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3400 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3404 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3408 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3412 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3416 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3420 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3424 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3428 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3432 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3436 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3440 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3444 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3448 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3452 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3456 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3460 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3464 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3468 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3472 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3476 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3480 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3484 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3488 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3492 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3496 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3500 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3504 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3508 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3512 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3516 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3520 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3524 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3528 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3532 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3536 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v163 /*v931*/, s33 offset:3288 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v164 /*v932*/, s33 offset:3292 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v165 /*v933*/, s33 offset:3296 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v166 /*v934*/, s33 offset:3300 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v167 /*v935*/, s33 offset:3304 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v168 /*v936*/, s33 offset:3308 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v169 /*v937*/, s33 offset:3312 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v170 /*v938*/, s33 offset:3316 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v171 /*v939*/, s33 offset:3320 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v172 /*v940*/, s33 offset:3324 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v173 /*v941*/, s33 offset:3328 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v174 /*v942*/, s33 offset:3332 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v175 /*v943*/, s33 offset:3336 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v176 /*v944*/, s33 offset:3340 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v177 /*v945*/, s33 offset:3344 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v178 /*v946*/, s33 offset:3348 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v179 /*v947*/, s33 offset:3352 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v180 /*v948*/, s33 offset:3356 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v181 /*v949*/, s33 offset:3360 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v182 /*v950*/, s33 offset:3364 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v183 /*v951*/, s33 offset:3368 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v184 /*v952*/, s33 offset:3372 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v185 /*v953*/, s33 offset:3376 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v186 /*v954*/, s33 offset:3380 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v187 /*v955*/, s33 offset:3384 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v188 /*v956*/, s33 offset:3388 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v189 /*v957*/, s33 offset:3392 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v190 /*v958*/, s33 offset:3396 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v191 /*v959*/, s33 offset:3400 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v192 /*v960*/, s33 offset:3404 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v193 /*v961*/, s33 offset:3408 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v194 /*v962*/, s33 offset:3412 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v195 /*v963*/, s33 offset:3416 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v196 /*v964*/, s33 offset:3420 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v197 /*v965*/, s33 offset:3424 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v198 /*v966*/, s33 offset:3428 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v199 /*v967*/, s33 offset:3432 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v200 /*v968*/, s33 offset:3436 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v201 /*v969*/, s33 offset:3440 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v202 /*v970*/, s33 offset:3444 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v203 /*v971*/, s33 offset:3448 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v204 /*v972*/, s33 offset:3452 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v205 /*v973*/, s33 offset:3456 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v206 /*v974*/, s33 offset:3460 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v207 /*v975*/, s33 offset:3464 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v208 /*v976*/, s33 offset:3468 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v209 /*v977*/, s33 offset:3472 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v210 /*v978*/, s33 offset:3476 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v211 /*v979*/, s33 offset:3480 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v212 /*v980*/, s33 offset:3484 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v213 /*v981*/, s33 offset:3488 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v214 /*v982*/, s33 offset:3492 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v215 /*v983*/, s33 offset:3496 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v216 /*v984*/, s33 offset:3500 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v217 /*v985*/, s33 offset:3504 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v218 /*v986*/, s33 offset:3508 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v219 /*v987*/, s33 offset:3512 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v220 /*v988*/, s33 offset:3516 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v221 /*v989*/, s33 offset:3520 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v222 /*v990*/, s33 offset:3524 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v223 /*v991*/, s33 offset:3528 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v224 /*v992*/, s33 offset:3532 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v225 /*v993*/, s33 offset:3536 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; 120-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3540 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3544 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3548 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3552 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3556 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3560 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3564 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3568 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3572 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3576 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3580 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3584 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3588 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3592 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3596 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3600 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3604 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3608 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3612 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3616 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3620 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3624 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3628 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3632 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3636 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3640 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3644 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3648 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3652 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3656 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v226 /*v994*/, s33 offset:3540 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v227 /*v995*/, s33 offset:3544 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v228 /*v996*/, s33 offset:3548 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v229 /*v997*/, s33 offset:3552 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v230 /*v998*/, s33 offset:3556 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v231 /*v999*/, s33 offset:3560 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v232 /*v1000*/, s33 offset:3564 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v233 /*v1001*/, s33 offset:3568 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v234 /*v1002*/, s33 offset:3572 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v235 /*v1003*/, s33 offset:3576 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v236 /*v1004*/, s33 offset:3580 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v237 /*v1005*/, s33 offset:3584 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v238 /*v1006*/, s33 offset:3588 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v239 /*v1007*/, s33 offset:3592 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v240 /*v1008*/, s33 offset:3596 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v241 /*v1009*/, s33 offset:3600 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v242 /*v1010*/, s33 offset:3604 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v243 /*v1011*/, s33 offset:3608 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v244 /*v1012*/, s33 offset:3612 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v245 /*v1013*/, s33 offset:3616 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v246 /*v1014*/, s33 offset:3620 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v247 /*v1015*/, s33 offset:3624 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v248 /*v1016*/, s33 offset:3628 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v249 /*v1017*/, s33 offset:3632 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v250 /*v1018*/, s33 offset:3636 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v251 /*v1019*/, s33 offset:3640 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v252 /*v1020*/, s33 offset:3644 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v253 /*v1021*/, s33 offset:3648 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v254 /*v1022*/, s33 offset:3652 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v255 /*v1023*/, s33 offset:3656 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, -1 ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0xc00 ; msbs: dst=0 src0=0 src1=0 src2=0 ; GFX1250-DAGISEL-NEXT: s_clause 0x2 ; 12-byte Folded Spill -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42, s33 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164 -; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168 +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v42, s33 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v40, s33 offset:164 nv +; GFX1250-DAGISEL-NEXT: scratch_store_b32 off, v41, s33 offset:168 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x2 ; GFX1250-DAGISEL-NEXT: v_writelane_b32 v42, s0, 3 ; GFX1250-DAGISEL-NEXT: s_mov_b64 s[0:1], callee@abs64 @@ -10203,942 +10203,942 @@ define amdgpu_gfx_whole_wave void @call_from_whole_wave(i1 %unused, <8 x float> ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s4, v42, 0 ; GFX1250-DAGISEL-NEXT: v_readlane_b32 s0, v42, 3 ; GFX1250-DAGISEL-NEXT: s_clause 0x2 ; 12-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42, off, s33 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s33 offset:164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41, off, s33 offset:168 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42, off, s33 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40, off, s33 offset:164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41, off, s33 offset:168 nv ; GFX1250-DAGISEL-NEXT: s_mov_b32 s32, s33 ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_xor_b32 exec_lo, s4, -1 ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s33 offset:4 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s33 offset:8 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s33 offset:12 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s33 offset:16 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4, off, s33 offset:20 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5, off, s33 offset:24 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6, off, s33 offset:28 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7, off, s33 offset:32 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8, off, s33 offset:36 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9, off, s33 offset:40 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10, off, s33 offset:44 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11, off, s33 offset:48 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12, off, s33 offset:52 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13, off, s33 offset:56 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14, off, s33 offset:60 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15, off, s33 offset:64 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16, off, s33 offset:68 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17, off, s33 offset:72 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18, off, s33 offset:76 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19, off, s33 offset:80 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20, off, s33 offset:84 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21, off, s33 offset:88 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22, off, s33 offset:92 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23, off, s33 offset:96 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24, off, s33 offset:100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25, off, s33 offset:104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26, off, s33 offset:108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27, off, s33 offset:112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28, off, s33 offset:116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29, off, s33 offset:120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30, off, s33 offset:124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31, off, s33 offset:128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32, off, s33 offset:132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33, off, s33 offset:136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34, off, s33 offset:140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35, off, s33 offset:144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36, off, s33 offset:148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37, off, s33 offset:152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38, off, s33 offset:156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39, off, s33 offset:160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48, off, s33 offset:172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49, off, s33 offset:176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50, off, s33 offset:180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51, off, s33 offset:184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52, off, s33 offset:188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53, off, s33 offset:192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54, off, s33 offset:196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55, off, s33 offset:200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64, off, s33 offset:204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65, off, s33 offset:208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66, off, s33 offset:212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67, off, s33 offset:216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68, off, s33 offset:220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69, off, s33 offset:224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70, off, s33 offset:228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71, off, s33 offset:232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80, off, s33 offset:236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81, off, s33 offset:240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82, off, s33 offset:244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83, off, s33 offset:248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84, off, s33 offset:252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85, off, s33 offset:256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86, off, s33 offset:260 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0, off, s33 offset:4 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1, off, s33 offset:8 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2, off, s33 offset:12 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3, off, s33 offset:16 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4, off, s33 offset:20 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5, off, s33 offset:24 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6, off, s33 offset:28 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7, off, s33 offset:32 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8, off, s33 offset:36 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9, off, s33 offset:40 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10, off, s33 offset:44 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11, off, s33 offset:48 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12, off, s33 offset:52 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13, off, s33 offset:56 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14, off, s33 offset:60 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15, off, s33 offset:64 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16, off, s33 offset:68 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17, off, s33 offset:72 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18, off, s33 offset:76 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19, off, s33 offset:80 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20, off, s33 offset:84 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21, off, s33 offset:88 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22, off, s33 offset:92 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23, off, s33 offset:96 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24, off, s33 offset:100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25, off, s33 offset:104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26, off, s33 offset:108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27, off, s33 offset:112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28, off, s33 offset:116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29, off, s33 offset:120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30, off, s33 offset:124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31, off, s33 offset:128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32, off, s33 offset:132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33, off, s33 offset:136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34, off, s33 offset:140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35, off, s33 offset:144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36, off, s33 offset:148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37, off, s33 offset:152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38, off, s33 offset:156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39, off, s33 offset:160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48, off, s33 offset:172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49, off, s33 offset:176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50, off, s33 offset:180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51, off, s33 offset:184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52, off, s33 offset:188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53, off, s33 offset:192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54, off, s33 offset:196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55, off, s33 offset:200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64, off, s33 offset:204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65, off, s33 offset:208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66, off, s33 offset:212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67, off, s33 offset:216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68, off, s33 offset:220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69, off, s33 offset:224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70, off, s33 offset:228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71, off, s33 offset:232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80, off, s33 offset:236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81, off, s33 offset:240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82, off, s33 offset:244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83, off, s33 offset:248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84, off, s33 offset:252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85, off, s33 offset:256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86, off, s33 offset:260 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87, off, s33 offset:264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96, off, s33 offset:268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97, off, s33 offset:272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98, off, s33 offset:276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99, off, s33 offset:280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100, off, s33 offset:284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101, off, s33 offset:288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102, off, s33 offset:292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103, off, s33 offset:296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112, off, s33 offset:300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113, off, s33 offset:304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114, off, s33 offset:308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115, off, s33 offset:312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116, off, s33 offset:316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117, off, s33 offset:320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118, off, s33 offset:324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119, off, s33 offset:328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128, off, s33 offset:332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129, off, s33 offset:336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130, off, s33 offset:340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131, off, s33 offset:344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132, off, s33 offset:348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133, off, s33 offset:352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134, off, s33 offset:356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135, off, s33 offset:360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144, off, s33 offset:364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145, off, s33 offset:368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146, off, s33 offset:372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147, off, s33 offset:376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148, off, s33 offset:380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149, off, s33 offset:384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150, off, s33 offset:388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151, off, s33 offset:392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160, off, s33 offset:396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161, off, s33 offset:400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162, off, s33 offset:404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163, off, s33 offset:408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164, off, s33 offset:412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165, off, s33 offset:416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166, off, s33 offset:420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167, off, s33 offset:424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176, off, s33 offset:428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177, off, s33 offset:432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178, off, s33 offset:436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179, off, s33 offset:440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180, off, s33 offset:444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181, off, s33 offset:448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182, off, s33 offset:452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183, off, s33 offset:456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192, off, s33 offset:460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193, off, s33 offset:464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194, off, s33 offset:468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195, off, s33 offset:472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196, off, s33 offset:476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197, off, s33 offset:480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198, off, s33 offset:484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199, off, s33 offset:488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208, off, s33 offset:492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209, off, s33 offset:496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210, off, s33 offset:500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211, off, s33 offset:504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212, off, s33 offset:508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213, off, s33 offset:512 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87, off, s33 offset:264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96, off, s33 offset:268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97, off, s33 offset:272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98, off, s33 offset:276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99, off, s33 offset:280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100, off, s33 offset:284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101, off, s33 offset:288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102, off, s33 offset:292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103, off, s33 offset:296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112, off, s33 offset:300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113, off, s33 offset:304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114, off, s33 offset:308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115, off, s33 offset:312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116, off, s33 offset:316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117, off, s33 offset:320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118, off, s33 offset:324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119, off, s33 offset:328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128, off, s33 offset:332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129, off, s33 offset:336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130, off, s33 offset:340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131, off, s33 offset:344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132, off, s33 offset:348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133, off, s33 offset:352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134, off, s33 offset:356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135, off, s33 offset:360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144, off, s33 offset:364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145, off, s33 offset:368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146, off, s33 offset:372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147, off, s33 offset:376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148, off, s33 offset:380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149, off, s33 offset:384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150, off, s33 offset:388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151, off, s33 offset:392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160, off, s33 offset:396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161, off, s33 offset:400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162, off, s33 offset:404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163, off, s33 offset:408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164, off, s33 offset:412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165, off, s33 offset:416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166, off, s33 offset:420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167, off, s33 offset:424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176, off, s33 offset:428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177, off, s33 offset:432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178, off, s33 offset:436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179, off, s33 offset:440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180, off, s33 offset:444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181, off, s33 offset:448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182, off, s33 offset:452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183, off, s33 offset:456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192, off, s33 offset:460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193, off, s33 offset:464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194, off, s33 offset:468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195, off, s33 offset:472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196, off, s33 offset:476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197, off, s33 offset:480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198, off, s33 offset:484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199, off, s33 offset:488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208, off, s33 offset:492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209, off, s33 offset:496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210, off, s33 offset:500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211, off, s33 offset:504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212, off, s33 offset:508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213, off, s33 offset:512 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214, off, s33 offset:516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215, off, s33 offset:520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224, off, s33 offset:524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225, off, s33 offset:528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226, off, s33 offset:532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227, off, s33 offset:536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228, off, s33 offset:540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229, off, s33 offset:544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230, off, s33 offset:548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231, off, s33 offset:552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240, off, s33 offset:556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241, off, s33 offset:560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242, off, s33 offset:564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243, off, s33 offset:568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244, off, s33 offset:572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245, off, s33 offset:576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246, off, s33 offset:580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247, off, s33 offset:584 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214, off, s33 offset:516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215, off, s33 offset:520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224, off, s33 offset:524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225, off, s33 offset:528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226, off, s33 offset:532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227, off, s33 offset:536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228, off, s33 offset:540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229, off, s33 offset:544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230, off, s33 offset:548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231, off, s33 offset:552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240, off, s33 offset:556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241, off, s33 offset:560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242, off, s33 offset:564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243, off, s33 offset:568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244, off, s33 offset:572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245, off, s33 offset:576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246, off, s33 offset:580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247, off, s33 offset:584 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 64 ; msbs: dst=1 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v256*/, off, s33 offset:588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v257*/, off, s33 offset:592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v258*/, off, s33 offset:596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v259*/, off, s33 offset:600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v260*/, off, s33 offset:604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v261*/, off, s33 offset:608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v262*/, off, s33 offset:612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v263*/, off, s33 offset:616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v264*/, off, s33 offset:620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v265*/, off, s33 offset:624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v266*/, off, s33 offset:628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v267*/, off, s33 offset:632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v268*/, off, s33 offset:636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v269*/, off, s33 offset:640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v270*/, off, s33 offset:644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v271*/, off, s33 offset:648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v272*/, off, s33 offset:652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v273*/, off, s33 offset:656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v274*/, off, s33 offset:660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v275*/, off, s33 offset:664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v276*/, off, s33 offset:668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v277*/, off, s33 offset:672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v278*/, off, s33 offset:676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v279*/, off, s33 offset:680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v280*/, off, s33 offset:684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v281*/, off, s33 offset:688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v282*/, off, s33 offset:692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v283*/, off, s33 offset:696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v284*/, off, s33 offset:700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v285*/, off, s33 offset:704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v286*/, off, s33 offset:708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v287*/, off, s33 offset:712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v288*/, off, s33 offset:716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v289*/, off, s33 offset:720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v290*/, off, s33 offset:724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v291*/, off, s33 offset:728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v292*/, off, s33 offset:732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v293*/, off, s33 offset:736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v294*/, off, s33 offset:740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v295*/, off, s33 offset:744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v296*/, off, s33 offset:748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v297*/, off, s33 offset:752 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v298*/, off, s33 offset:756 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v299*/, off, s33 offset:760 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v300*/, off, s33 offset:764 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v256*/, off, s33 offset:588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v257*/, off, s33 offset:592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v258*/, off, s33 offset:596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v259*/, off, s33 offset:600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v260*/, off, s33 offset:604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v261*/, off, s33 offset:608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v262*/, off, s33 offset:612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v263*/, off, s33 offset:616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v264*/, off, s33 offset:620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v265*/, off, s33 offset:624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v266*/, off, s33 offset:628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v267*/, off, s33 offset:632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v268*/, off, s33 offset:636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v269*/, off, s33 offset:640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v270*/, off, s33 offset:644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v271*/, off, s33 offset:648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v272*/, off, s33 offset:652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v273*/, off, s33 offset:656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v274*/, off, s33 offset:660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v275*/, off, s33 offset:664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v276*/, off, s33 offset:668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v277*/, off, s33 offset:672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v278*/, off, s33 offset:676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v279*/, off, s33 offset:680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v280*/, off, s33 offset:684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v281*/, off, s33 offset:688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v282*/, off, s33 offset:692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v283*/, off, s33 offset:696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v284*/, off, s33 offset:700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v285*/, off, s33 offset:704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v286*/, off, s33 offset:708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v287*/, off, s33 offset:712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v288*/, off, s33 offset:716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v289*/, off, s33 offset:720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v290*/, off, s33 offset:724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v291*/, off, s33 offset:728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v292*/, off, s33 offset:732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v293*/, off, s33 offset:736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v294*/, off, s33 offset:740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v295*/, off, s33 offset:744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v296*/, off, s33 offset:748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v297*/, off, s33 offset:752 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v298*/, off, s33 offset:756 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v299*/, off, s33 offset:760 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v300*/, off, s33 offset:764 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v301*/, off, s33 offset:768 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v302*/, off, s33 offset:772 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v303*/, off, s33 offset:776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v304*/, off, s33 offset:780 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v305*/, off, s33 offset:784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v306*/, off, s33 offset:788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v307*/, off, s33 offset:792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v308*/, off, s33 offset:796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v309*/, off, s33 offset:800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v310*/, off, s33 offset:804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v311*/, off, s33 offset:808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v312*/, off, s33 offset:812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v313*/, off, s33 offset:816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v314*/, off, s33 offset:820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v315*/, off, s33 offset:824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v316*/, off, s33 offset:828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v317*/, off, s33 offset:832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v318*/, off, s33 offset:836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v319*/, off, s33 offset:840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v320*/, off, s33 offset:844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v321*/, off, s33 offset:848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v322*/, off, s33 offset:852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v323*/, off, s33 offset:856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v324*/, off, s33 offset:860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v325*/, off, s33 offset:864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v326*/, off, s33 offset:868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v327*/, off, s33 offset:872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v328*/, off, s33 offset:876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v329*/, off, s33 offset:880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v330*/, off, s33 offset:884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v331*/, off, s33 offset:888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v332*/, off, s33 offset:892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v333*/, off, s33 offset:896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v334*/, off, s33 offset:900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v335*/, off, s33 offset:904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v336*/, off, s33 offset:908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v337*/, off, s33 offset:912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v338*/, off, s33 offset:916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v339*/, off, s33 offset:920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v340*/, off, s33 offset:924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v341*/, off, s33 offset:928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v342*/, off, s33 offset:932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v343*/, off, s33 offset:936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v344*/, off, s33 offset:940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v345*/, off, s33 offset:944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v346*/, off, s33 offset:948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v347*/, off, s33 offset:952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v348*/, off, s33 offset:956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v349*/, off, s33 offset:960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v350*/, off, s33 offset:964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v351*/, off, s33 offset:968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v352*/, off, s33 offset:972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v353*/, off, s33 offset:976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v354*/, off, s33 offset:980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v355*/, off, s33 offset:984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v356*/, off, s33 offset:988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v357*/, off, s33 offset:992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v358*/, off, s33 offset:996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v359*/, off, s33 offset:1000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v360*/, off, s33 offset:1004 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v361*/, off, s33 offset:1008 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v362*/, off, s33 offset:1012 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v363*/, off, s33 offset:1016 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v301*/, off, s33 offset:768 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v302*/, off, s33 offset:772 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v303*/, off, s33 offset:776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v304*/, off, s33 offset:780 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v305*/, off, s33 offset:784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v306*/, off, s33 offset:788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v307*/, off, s33 offset:792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v308*/, off, s33 offset:796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v309*/, off, s33 offset:800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v310*/, off, s33 offset:804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v311*/, off, s33 offset:808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v312*/, off, s33 offset:812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v313*/, off, s33 offset:816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v314*/, off, s33 offset:820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v315*/, off, s33 offset:824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v316*/, off, s33 offset:828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v317*/, off, s33 offset:832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v318*/, off, s33 offset:836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v319*/, off, s33 offset:840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v320*/, off, s33 offset:844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v321*/, off, s33 offset:848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v322*/, off, s33 offset:852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v323*/, off, s33 offset:856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v324*/, off, s33 offset:860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v325*/, off, s33 offset:864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v326*/, off, s33 offset:868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v327*/, off, s33 offset:872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v328*/, off, s33 offset:876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v329*/, off, s33 offset:880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v330*/, off, s33 offset:884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v331*/, off, s33 offset:888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v332*/, off, s33 offset:892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v333*/, off, s33 offset:896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v334*/, off, s33 offset:900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v335*/, off, s33 offset:904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v336*/, off, s33 offset:908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v337*/, off, s33 offset:912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v338*/, off, s33 offset:916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v339*/, off, s33 offset:920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v340*/, off, s33 offset:924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v341*/, off, s33 offset:928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v342*/, off, s33 offset:932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v343*/, off, s33 offset:936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v344*/, off, s33 offset:940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v345*/, off, s33 offset:944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v346*/, off, s33 offset:948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v347*/, off, s33 offset:952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v348*/, off, s33 offset:956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v349*/, off, s33 offset:960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v350*/, off, s33 offset:964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v351*/, off, s33 offset:968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v352*/, off, s33 offset:972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v353*/, off, s33 offset:976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v354*/, off, s33 offset:980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v355*/, off, s33 offset:984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v356*/, off, s33 offset:988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v357*/, off, s33 offset:992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v358*/, off, s33 offset:996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v359*/, off, s33 offset:1000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v360*/, off, s33 offset:1004 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v361*/, off, s33 offset:1008 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v362*/, off, s33 offset:1012 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v363*/, off, s33 offset:1016 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v364*/, off, s33 offset:1020 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v365*/, off, s33 offset:1024 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v366*/, off, s33 offset:1028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v367*/, off, s33 offset:1032 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v368*/, off, s33 offset:1036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v369*/, off, s33 offset:1040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v370*/, off, s33 offset:1044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v371*/, off, s33 offset:1048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v372*/, off, s33 offset:1052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v373*/, off, s33 offset:1056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v374*/, off, s33 offset:1060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v375*/, off, s33 offset:1064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v376*/, off, s33 offset:1068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v377*/, off, s33 offset:1072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v378*/, off, s33 offset:1076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v379*/, off, s33 offset:1080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v380*/, off, s33 offset:1084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v381*/, off, s33 offset:1088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v382*/, off, s33 offset:1092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v383*/, off, s33 offset:1096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v384*/, off, s33 offset:1100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v385*/, off, s33 offset:1104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v386*/, off, s33 offset:1108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v387*/, off, s33 offset:1112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v388*/, off, s33 offset:1116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v389*/, off, s33 offset:1120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v390*/, off, s33 offset:1124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v391*/, off, s33 offset:1128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v392*/, off, s33 offset:1132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v393*/, off, s33 offset:1136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v394*/, off, s33 offset:1140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v395*/, off, s33 offset:1144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v396*/, off, s33 offset:1148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v397*/, off, s33 offset:1152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v398*/, off, s33 offset:1156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v399*/, off, s33 offset:1160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v400*/, off, s33 offset:1164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v401*/, off, s33 offset:1168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v402*/, off, s33 offset:1172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v403*/, off, s33 offset:1176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v404*/, off, s33 offset:1180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v405*/, off, s33 offset:1184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v406*/, off, s33 offset:1188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v407*/, off, s33 offset:1192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v408*/, off, s33 offset:1196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v409*/, off, s33 offset:1200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v410*/, off, s33 offset:1204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v411*/, off, s33 offset:1208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v412*/, off, s33 offset:1212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v413*/, off, s33 offset:1216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v414*/, off, s33 offset:1220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v415*/, off, s33 offset:1224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v416*/, off, s33 offset:1228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v417*/, off, s33 offset:1232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v418*/, off, s33 offset:1236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v419*/, off, s33 offset:1240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v420*/, off, s33 offset:1244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v421*/, off, s33 offset:1248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v422*/, off, s33 offset:1252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v423*/, off, s33 offset:1256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v424*/, off, s33 offset:1260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v425*/, off, s33 offset:1264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v426*/, off, s33 offset:1268 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v364*/, off, s33 offset:1020 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v365*/, off, s33 offset:1024 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v366*/, off, s33 offset:1028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v367*/, off, s33 offset:1032 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v368*/, off, s33 offset:1036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v369*/, off, s33 offset:1040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v370*/, off, s33 offset:1044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v371*/, off, s33 offset:1048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v372*/, off, s33 offset:1052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v373*/, off, s33 offset:1056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v374*/, off, s33 offset:1060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v375*/, off, s33 offset:1064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v376*/, off, s33 offset:1068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v377*/, off, s33 offset:1072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v378*/, off, s33 offset:1076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v379*/, off, s33 offset:1080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v380*/, off, s33 offset:1084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v381*/, off, s33 offset:1088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v382*/, off, s33 offset:1092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v383*/, off, s33 offset:1096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v384*/, off, s33 offset:1100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v385*/, off, s33 offset:1104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v386*/, off, s33 offset:1108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v387*/, off, s33 offset:1112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v388*/, off, s33 offset:1116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v389*/, off, s33 offset:1120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v390*/, off, s33 offset:1124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v391*/, off, s33 offset:1128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v392*/, off, s33 offset:1132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v393*/, off, s33 offset:1136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v394*/, off, s33 offset:1140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v395*/, off, s33 offset:1144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v396*/, off, s33 offset:1148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v397*/, off, s33 offset:1152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v398*/, off, s33 offset:1156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v399*/, off, s33 offset:1160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v400*/, off, s33 offset:1164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v401*/, off, s33 offset:1168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v402*/, off, s33 offset:1172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v403*/, off, s33 offset:1176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v404*/, off, s33 offset:1180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v405*/, off, s33 offset:1184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v406*/, off, s33 offset:1188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v407*/, off, s33 offset:1192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v408*/, off, s33 offset:1196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v409*/, off, s33 offset:1200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v410*/, off, s33 offset:1204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v411*/, off, s33 offset:1208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v412*/, off, s33 offset:1212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v413*/, off, s33 offset:1216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v414*/, off, s33 offset:1220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v415*/, off, s33 offset:1224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v416*/, off, s33 offset:1228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v417*/, off, s33 offset:1232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v418*/, off, s33 offset:1236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v419*/, off, s33 offset:1240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v420*/, off, s33 offset:1244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v421*/, off, s33 offset:1248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v422*/, off, s33 offset:1252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v423*/, off, s33 offset:1256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v424*/, off, s33 offset:1260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v425*/, off, s33 offset:1264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v426*/, off, s33 offset:1268 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v427*/, off, s33 offset:1272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v428*/, off, s33 offset:1276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v429*/, off, s33 offset:1280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v430*/, off, s33 offset:1284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v431*/, off, s33 offset:1288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v432*/, off, s33 offset:1292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v433*/, off, s33 offset:1296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v434*/, off, s33 offset:1300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v435*/, off, s33 offset:1304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v436*/, off, s33 offset:1308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v437*/, off, s33 offset:1312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v438*/, off, s33 offset:1316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v439*/, off, s33 offset:1320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v440*/, off, s33 offset:1324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v441*/, off, s33 offset:1328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v442*/, off, s33 offset:1332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v443*/, off, s33 offset:1336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v444*/, off, s33 offset:1340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v445*/, off, s33 offset:1344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v446*/, off, s33 offset:1348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v447*/, off, s33 offset:1352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v448*/, off, s33 offset:1356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v449*/, off, s33 offset:1360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v450*/, off, s33 offset:1364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v451*/, off, s33 offset:1368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v452*/, off, s33 offset:1372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v453*/, off, s33 offset:1376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v454*/, off, s33 offset:1380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v455*/, off, s33 offset:1384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v456*/, off, s33 offset:1388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v457*/, off, s33 offset:1392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v458*/, off, s33 offset:1396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v459*/, off, s33 offset:1400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v460*/, off, s33 offset:1404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v461*/, off, s33 offset:1408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v462*/, off, s33 offset:1412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v463*/, off, s33 offset:1416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v464*/, off, s33 offset:1420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v465*/, off, s33 offset:1424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v466*/, off, s33 offset:1428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v467*/, off, s33 offset:1432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v468*/, off, s33 offset:1436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v469*/, off, s33 offset:1440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v470*/, off, s33 offset:1444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v471*/, off, s33 offset:1448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v472*/, off, s33 offset:1452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v473*/, off, s33 offset:1456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v474*/, off, s33 offset:1460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v475*/, off, s33 offset:1464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v476*/, off, s33 offset:1468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v477*/, off, s33 offset:1472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v478*/, off, s33 offset:1476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v479*/, off, s33 offset:1480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v480*/, off, s33 offset:1484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v481*/, off, s33 offset:1488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v482*/, off, s33 offset:1492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v483*/, off, s33 offset:1496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v484*/, off, s33 offset:1500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v485*/, off, s33 offset:1504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v486*/, off, s33 offset:1508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v487*/, off, s33 offset:1512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v488*/, off, s33 offset:1516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v489*/, off, s33 offset:1520 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v427*/, off, s33 offset:1272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v428*/, off, s33 offset:1276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v429*/, off, s33 offset:1280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v430*/, off, s33 offset:1284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v431*/, off, s33 offset:1288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v432*/, off, s33 offset:1292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v433*/, off, s33 offset:1296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v434*/, off, s33 offset:1300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v435*/, off, s33 offset:1304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v436*/, off, s33 offset:1308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v437*/, off, s33 offset:1312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v438*/, off, s33 offset:1316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v439*/, off, s33 offset:1320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v440*/, off, s33 offset:1324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v441*/, off, s33 offset:1328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v442*/, off, s33 offset:1332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v443*/, off, s33 offset:1336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v444*/, off, s33 offset:1340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v445*/, off, s33 offset:1344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v446*/, off, s33 offset:1348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v447*/, off, s33 offset:1352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v448*/, off, s33 offset:1356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v449*/, off, s33 offset:1360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v450*/, off, s33 offset:1364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v451*/, off, s33 offset:1368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v452*/, off, s33 offset:1372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v453*/, off, s33 offset:1376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v454*/, off, s33 offset:1380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v455*/, off, s33 offset:1384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v456*/, off, s33 offset:1388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v457*/, off, s33 offset:1392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v458*/, off, s33 offset:1396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v459*/, off, s33 offset:1400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v460*/, off, s33 offset:1404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v461*/, off, s33 offset:1408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v462*/, off, s33 offset:1412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v463*/, off, s33 offset:1416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v464*/, off, s33 offset:1420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v465*/, off, s33 offset:1424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v466*/, off, s33 offset:1428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v467*/, off, s33 offset:1432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v468*/, off, s33 offset:1436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v469*/, off, s33 offset:1440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v470*/, off, s33 offset:1444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v471*/, off, s33 offset:1448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v472*/, off, s33 offset:1452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v473*/, off, s33 offset:1456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v474*/, off, s33 offset:1460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v475*/, off, s33 offset:1464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v476*/, off, s33 offset:1468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v477*/, off, s33 offset:1472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v478*/, off, s33 offset:1476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v479*/, off, s33 offset:1480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v480*/, off, s33 offset:1484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v481*/, off, s33 offset:1488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v482*/, off, s33 offset:1492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v483*/, off, s33 offset:1496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v484*/, off, s33 offset:1500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v485*/, off, s33 offset:1504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v486*/, off, s33 offset:1508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v487*/, off, s33 offset:1512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v488*/, off, s33 offset:1516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v489*/, off, s33 offset:1520 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v490*/, off, s33 offset:1524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v491*/, off, s33 offset:1528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v492*/, off, s33 offset:1532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v493*/, off, s33 offset:1536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v494*/, off, s33 offset:1540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v495*/, off, s33 offset:1544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v496*/, off, s33 offset:1548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v497*/, off, s33 offset:1552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v498*/, off, s33 offset:1556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v499*/, off, s33 offset:1560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v500*/, off, s33 offset:1564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v501*/, off, s33 offset:1568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v502*/, off, s33 offset:1572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v503*/, off, s33 offset:1576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v504*/, off, s33 offset:1580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v505*/, off, s33 offset:1584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v506*/, off, s33 offset:1588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v507*/, off, s33 offset:1592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v508*/, off, s33 offset:1596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v509*/, off, s33 offset:1600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v510*/, off, s33 offset:1604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v511*/, off, s33 offset:1608 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v490*/, off, s33 offset:1524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v491*/, off, s33 offset:1528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v492*/, off, s33 offset:1532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v493*/, off, s33 offset:1536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v494*/, off, s33 offset:1540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v495*/, off, s33 offset:1544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v496*/, off, s33 offset:1548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v497*/, off, s33 offset:1552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v498*/, off, s33 offset:1556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v499*/, off, s33 offset:1560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v500*/, off, s33 offset:1564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v501*/, off, s33 offset:1568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v502*/, off, s33 offset:1572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v503*/, off, s33 offset:1576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v504*/, off, s33 offset:1580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v505*/, off, s33 offset:1584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v506*/, off, s33 offset:1588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v507*/, off, s33 offset:1592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v508*/, off, s33 offset:1596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v509*/, off, s33 offset:1600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v510*/, off, s33 offset:1604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v511*/, off, s33 offset:1608 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x4080 ; msbs: dst=2 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v512*/, off, s33 offset:1612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v513*/, off, s33 offset:1616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v514*/, off, s33 offset:1620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v515*/, off, s33 offset:1624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v516*/, off, s33 offset:1628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v517*/, off, s33 offset:1632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v518*/, off, s33 offset:1636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v519*/, off, s33 offset:1640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v520*/, off, s33 offset:1644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v521*/, off, s33 offset:1648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v522*/, off, s33 offset:1652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v523*/, off, s33 offset:1656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v524*/, off, s33 offset:1660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v525*/, off, s33 offset:1664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v526*/, off, s33 offset:1668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v527*/, off, s33 offset:1672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v528*/, off, s33 offset:1676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v529*/, off, s33 offset:1680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v530*/, off, s33 offset:1684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v531*/, off, s33 offset:1688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v532*/, off, s33 offset:1692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v533*/, off, s33 offset:1696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v534*/, off, s33 offset:1700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v535*/, off, s33 offset:1704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v536*/, off, s33 offset:1708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v537*/, off, s33 offset:1712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v538*/, off, s33 offset:1716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v539*/, off, s33 offset:1720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v540*/, off, s33 offset:1724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v541*/, off, s33 offset:1728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v542*/, off, s33 offset:1732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v543*/, off, s33 offset:1736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v544*/, off, s33 offset:1740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v545*/, off, s33 offset:1744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v546*/, off, s33 offset:1748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v547*/, off, s33 offset:1752 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v548*/, off, s33 offset:1756 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v549*/, off, s33 offset:1760 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v550*/, off, s33 offset:1764 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v551*/, off, s33 offset:1768 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v552*/, off, s33 offset:1772 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v512*/, off, s33 offset:1612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v513*/, off, s33 offset:1616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v514*/, off, s33 offset:1620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v515*/, off, s33 offset:1624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v516*/, off, s33 offset:1628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v517*/, off, s33 offset:1632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v518*/, off, s33 offset:1636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v519*/, off, s33 offset:1640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v520*/, off, s33 offset:1644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v521*/, off, s33 offset:1648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v522*/, off, s33 offset:1652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v523*/, off, s33 offset:1656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v524*/, off, s33 offset:1660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v525*/, off, s33 offset:1664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v526*/, off, s33 offset:1668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v527*/, off, s33 offset:1672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v528*/, off, s33 offset:1676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v529*/, off, s33 offset:1680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v530*/, off, s33 offset:1684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v531*/, off, s33 offset:1688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v532*/, off, s33 offset:1692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v533*/, off, s33 offset:1696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v534*/, off, s33 offset:1700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v535*/, off, s33 offset:1704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v536*/, off, s33 offset:1708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v537*/, off, s33 offset:1712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v538*/, off, s33 offset:1716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v539*/, off, s33 offset:1720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v540*/, off, s33 offset:1724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v541*/, off, s33 offset:1728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v542*/, off, s33 offset:1732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v543*/, off, s33 offset:1736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v544*/, off, s33 offset:1740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v545*/, off, s33 offset:1744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v546*/, off, s33 offset:1748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v547*/, off, s33 offset:1752 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v548*/, off, s33 offset:1756 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v549*/, off, s33 offset:1760 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v550*/, off, s33 offset:1764 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v551*/, off, s33 offset:1768 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v552*/, off, s33 offset:1772 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v553*/, off, s33 offset:1776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v554*/, off, s33 offset:1780 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v555*/, off, s33 offset:1784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v556*/, off, s33 offset:1788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v557*/, off, s33 offset:1792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v558*/, off, s33 offset:1796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v559*/, off, s33 offset:1800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v560*/, off, s33 offset:1804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v561*/, off, s33 offset:1808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v562*/, off, s33 offset:1812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v563*/, off, s33 offset:1816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v564*/, off, s33 offset:1820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v565*/, off, s33 offset:1824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v566*/, off, s33 offset:1828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v567*/, off, s33 offset:1832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v568*/, off, s33 offset:1836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v569*/, off, s33 offset:1840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v570*/, off, s33 offset:1844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v571*/, off, s33 offset:1848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v572*/, off, s33 offset:1852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v573*/, off, s33 offset:1856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v574*/, off, s33 offset:1860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v575*/, off, s33 offset:1864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v576*/, off, s33 offset:1868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v577*/, off, s33 offset:1872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v578*/, off, s33 offset:1876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v579*/, off, s33 offset:1880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v580*/, off, s33 offset:1884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v581*/, off, s33 offset:1888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v582*/, off, s33 offset:1892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v583*/, off, s33 offset:1896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v584*/, off, s33 offset:1900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v585*/, off, s33 offset:1904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v586*/, off, s33 offset:1908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v587*/, off, s33 offset:1912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v588*/, off, s33 offset:1916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v589*/, off, s33 offset:1920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v590*/, off, s33 offset:1924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v591*/, off, s33 offset:1928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v592*/, off, s33 offset:1932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v593*/, off, s33 offset:1936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v594*/, off, s33 offset:1940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v595*/, off, s33 offset:1944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v596*/, off, s33 offset:1948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v597*/, off, s33 offset:1952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v598*/, off, s33 offset:1956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v599*/, off, s33 offset:1960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v600*/, off, s33 offset:1964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v601*/, off, s33 offset:1968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v602*/, off, s33 offset:1972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v603*/, off, s33 offset:1976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v604*/, off, s33 offset:1980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v605*/, off, s33 offset:1984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v606*/, off, s33 offset:1988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v607*/, off, s33 offset:1992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v608*/, off, s33 offset:1996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v609*/, off, s33 offset:2000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v610*/, off, s33 offset:2004 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v611*/, off, s33 offset:2008 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v612*/, off, s33 offset:2012 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v613*/, off, s33 offset:2016 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v614*/, off, s33 offset:2020 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v615*/, off, s33 offset:2024 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v553*/, off, s33 offset:1776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v554*/, off, s33 offset:1780 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v555*/, off, s33 offset:1784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v556*/, off, s33 offset:1788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v557*/, off, s33 offset:1792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v558*/, off, s33 offset:1796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v559*/, off, s33 offset:1800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v560*/, off, s33 offset:1804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v561*/, off, s33 offset:1808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v562*/, off, s33 offset:1812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v563*/, off, s33 offset:1816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v564*/, off, s33 offset:1820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v565*/, off, s33 offset:1824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v566*/, off, s33 offset:1828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v567*/, off, s33 offset:1832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v568*/, off, s33 offset:1836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v569*/, off, s33 offset:1840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v570*/, off, s33 offset:1844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v571*/, off, s33 offset:1848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v572*/, off, s33 offset:1852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v573*/, off, s33 offset:1856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v574*/, off, s33 offset:1860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v575*/, off, s33 offset:1864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v576*/, off, s33 offset:1868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v577*/, off, s33 offset:1872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v578*/, off, s33 offset:1876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v579*/, off, s33 offset:1880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v580*/, off, s33 offset:1884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v581*/, off, s33 offset:1888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v582*/, off, s33 offset:1892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v583*/, off, s33 offset:1896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v584*/, off, s33 offset:1900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v585*/, off, s33 offset:1904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v586*/, off, s33 offset:1908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v587*/, off, s33 offset:1912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v588*/, off, s33 offset:1916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v589*/, off, s33 offset:1920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v590*/, off, s33 offset:1924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v591*/, off, s33 offset:1928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v592*/, off, s33 offset:1932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v593*/, off, s33 offset:1936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v594*/, off, s33 offset:1940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v595*/, off, s33 offset:1944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v596*/, off, s33 offset:1948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v597*/, off, s33 offset:1952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v598*/, off, s33 offset:1956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v599*/, off, s33 offset:1960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v600*/, off, s33 offset:1964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v601*/, off, s33 offset:1968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v602*/, off, s33 offset:1972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v603*/, off, s33 offset:1976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v604*/, off, s33 offset:1980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v605*/, off, s33 offset:1984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v606*/, off, s33 offset:1988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v607*/, off, s33 offset:1992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v608*/, off, s33 offset:1996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v609*/, off, s33 offset:2000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v610*/, off, s33 offset:2004 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v611*/, off, s33 offset:2008 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v612*/, off, s33 offset:2012 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v613*/, off, s33 offset:2016 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v614*/, off, s33 offset:2020 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v615*/, off, s33 offset:2024 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v616*/, off, s33 offset:2028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v617*/, off, s33 offset:2032 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v618*/, off, s33 offset:2036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v619*/, off, s33 offset:2040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v620*/, off, s33 offset:2044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v621*/, off, s33 offset:2048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v622*/, off, s33 offset:2052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v623*/, off, s33 offset:2056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v624*/, off, s33 offset:2060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v625*/, off, s33 offset:2064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v626*/, off, s33 offset:2068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v627*/, off, s33 offset:2072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v628*/, off, s33 offset:2076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v629*/, off, s33 offset:2080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v630*/, off, s33 offset:2084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v631*/, off, s33 offset:2088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v632*/, off, s33 offset:2092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v633*/, off, s33 offset:2096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v634*/, off, s33 offset:2100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v635*/, off, s33 offset:2104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v636*/, off, s33 offset:2108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v637*/, off, s33 offset:2112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v638*/, off, s33 offset:2116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v639*/, off, s33 offset:2120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v640*/, off, s33 offset:2124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v641*/, off, s33 offset:2128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v642*/, off, s33 offset:2132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v643*/, off, s33 offset:2136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v644*/, off, s33 offset:2140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v645*/, off, s33 offset:2144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v646*/, off, s33 offset:2148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v647*/, off, s33 offset:2152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v648*/, off, s33 offset:2156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v649*/, off, s33 offset:2160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v650*/, off, s33 offset:2164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v651*/, off, s33 offset:2168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v652*/, off, s33 offset:2172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v653*/, off, s33 offset:2176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v654*/, off, s33 offset:2180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v655*/, off, s33 offset:2184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v656*/, off, s33 offset:2188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v657*/, off, s33 offset:2192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v658*/, off, s33 offset:2196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v659*/, off, s33 offset:2200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v660*/, off, s33 offset:2204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v661*/, off, s33 offset:2208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v662*/, off, s33 offset:2212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v663*/, off, s33 offset:2216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v664*/, off, s33 offset:2220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v665*/, off, s33 offset:2224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v666*/, off, s33 offset:2228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v667*/, off, s33 offset:2232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v668*/, off, s33 offset:2236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v669*/, off, s33 offset:2240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v670*/, off, s33 offset:2244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v671*/, off, s33 offset:2248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v672*/, off, s33 offset:2252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v673*/, off, s33 offset:2256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v674*/, off, s33 offset:2260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v675*/, off, s33 offset:2264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v676*/, off, s33 offset:2268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v677*/, off, s33 offset:2272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v678*/, off, s33 offset:2276 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v616*/, off, s33 offset:2028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v617*/, off, s33 offset:2032 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v618*/, off, s33 offset:2036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v619*/, off, s33 offset:2040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v620*/, off, s33 offset:2044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v621*/, off, s33 offset:2048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v622*/, off, s33 offset:2052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v623*/, off, s33 offset:2056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v624*/, off, s33 offset:2060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v625*/, off, s33 offset:2064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v626*/, off, s33 offset:2068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v627*/, off, s33 offset:2072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v628*/, off, s33 offset:2076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v629*/, off, s33 offset:2080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v630*/, off, s33 offset:2084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v631*/, off, s33 offset:2088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v632*/, off, s33 offset:2092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v633*/, off, s33 offset:2096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v634*/, off, s33 offset:2100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v635*/, off, s33 offset:2104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v636*/, off, s33 offset:2108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v637*/, off, s33 offset:2112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v638*/, off, s33 offset:2116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v639*/, off, s33 offset:2120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v640*/, off, s33 offset:2124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v641*/, off, s33 offset:2128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v642*/, off, s33 offset:2132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v643*/, off, s33 offset:2136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v644*/, off, s33 offset:2140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v645*/, off, s33 offset:2144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v646*/, off, s33 offset:2148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v647*/, off, s33 offset:2152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v648*/, off, s33 offset:2156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v649*/, off, s33 offset:2160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v650*/, off, s33 offset:2164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v651*/, off, s33 offset:2168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v652*/, off, s33 offset:2172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v653*/, off, s33 offset:2176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v654*/, off, s33 offset:2180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v655*/, off, s33 offset:2184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v656*/, off, s33 offset:2188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v657*/, off, s33 offset:2192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v658*/, off, s33 offset:2196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v659*/, off, s33 offset:2200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v660*/, off, s33 offset:2204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v661*/, off, s33 offset:2208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v662*/, off, s33 offset:2212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v663*/, off, s33 offset:2216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v664*/, off, s33 offset:2220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v665*/, off, s33 offset:2224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v666*/, off, s33 offset:2228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v667*/, off, s33 offset:2232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v668*/, off, s33 offset:2236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v669*/, off, s33 offset:2240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v670*/, off, s33 offset:2244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v671*/, off, s33 offset:2248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v672*/, off, s33 offset:2252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v673*/, off, s33 offset:2256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v674*/, off, s33 offset:2260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v675*/, off, s33 offset:2264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v676*/, off, s33 offset:2268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v677*/, off, s33 offset:2272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v678*/, off, s33 offset:2276 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v679*/, off, s33 offset:2280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v680*/, off, s33 offset:2284 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v681*/, off, s33 offset:2288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v682*/, off, s33 offset:2292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v683*/, off, s33 offset:2296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v684*/, off, s33 offset:2300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v685*/, off, s33 offset:2304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v686*/, off, s33 offset:2308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v687*/, off, s33 offset:2312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v688*/, off, s33 offset:2316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v689*/, off, s33 offset:2320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v690*/, off, s33 offset:2324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v691*/, off, s33 offset:2328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v692*/, off, s33 offset:2332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v693*/, off, s33 offset:2336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v694*/, off, s33 offset:2340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v695*/, off, s33 offset:2344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v696*/, off, s33 offset:2348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v697*/, off, s33 offset:2352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v698*/, off, s33 offset:2356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v699*/, off, s33 offset:2360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v700*/, off, s33 offset:2364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v701*/, off, s33 offset:2368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v702*/, off, s33 offset:2372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v703*/, off, s33 offset:2376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v704*/, off, s33 offset:2380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v705*/, off, s33 offset:2384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v706*/, off, s33 offset:2388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v707*/, off, s33 offset:2392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v708*/, off, s33 offset:2396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v709*/, off, s33 offset:2400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v710*/, off, s33 offset:2404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v711*/, off, s33 offset:2408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v712*/, off, s33 offset:2412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v713*/, off, s33 offset:2416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v714*/, off, s33 offset:2420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v715*/, off, s33 offset:2424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v716*/, off, s33 offset:2428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v717*/, off, s33 offset:2432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v718*/, off, s33 offset:2436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v719*/, off, s33 offset:2440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v720*/, off, s33 offset:2444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v721*/, off, s33 offset:2448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v722*/, off, s33 offset:2452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v723*/, off, s33 offset:2456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v724*/, off, s33 offset:2460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v725*/, off, s33 offset:2464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v726*/, off, s33 offset:2468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v727*/, off, s33 offset:2472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v728*/, off, s33 offset:2476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v729*/, off, s33 offset:2480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v730*/, off, s33 offset:2484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v731*/, off, s33 offset:2488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v732*/, off, s33 offset:2492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v733*/, off, s33 offset:2496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v734*/, off, s33 offset:2500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v735*/, off, s33 offset:2504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v736*/, off, s33 offset:2508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v737*/, off, s33 offset:2512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v738*/, off, s33 offset:2516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v739*/, off, s33 offset:2520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v740*/, off, s33 offset:2524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v741*/, off, s33 offset:2528 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v679*/, off, s33 offset:2280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v680*/, off, s33 offset:2284 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v681*/, off, s33 offset:2288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v682*/, off, s33 offset:2292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v683*/, off, s33 offset:2296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v684*/, off, s33 offset:2300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v685*/, off, s33 offset:2304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v686*/, off, s33 offset:2308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v687*/, off, s33 offset:2312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v688*/, off, s33 offset:2316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v689*/, off, s33 offset:2320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v690*/, off, s33 offset:2324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v691*/, off, s33 offset:2328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v692*/, off, s33 offset:2332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v693*/, off, s33 offset:2336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v694*/, off, s33 offset:2340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v695*/, off, s33 offset:2344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v696*/, off, s33 offset:2348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v697*/, off, s33 offset:2352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v698*/, off, s33 offset:2356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v699*/, off, s33 offset:2360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v700*/, off, s33 offset:2364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v701*/, off, s33 offset:2368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v702*/, off, s33 offset:2372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v703*/, off, s33 offset:2376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v704*/, off, s33 offset:2380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v705*/, off, s33 offset:2384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v706*/, off, s33 offset:2388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v707*/, off, s33 offset:2392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v708*/, off, s33 offset:2396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v709*/, off, s33 offset:2400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v710*/, off, s33 offset:2404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v711*/, off, s33 offset:2408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v712*/, off, s33 offset:2412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v713*/, off, s33 offset:2416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v714*/, off, s33 offset:2420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v715*/, off, s33 offset:2424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v716*/, off, s33 offset:2428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v717*/, off, s33 offset:2432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v718*/, off, s33 offset:2436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v719*/, off, s33 offset:2440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v720*/, off, s33 offset:2444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v721*/, off, s33 offset:2448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v722*/, off, s33 offset:2452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v723*/, off, s33 offset:2456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v724*/, off, s33 offset:2460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v725*/, off, s33 offset:2464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v726*/, off, s33 offset:2468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v727*/, off, s33 offset:2472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v728*/, off, s33 offset:2476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v729*/, off, s33 offset:2480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v730*/, off, s33 offset:2484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v731*/, off, s33 offset:2488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v732*/, off, s33 offset:2492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v733*/, off, s33 offset:2496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v734*/, off, s33 offset:2500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v735*/, off, s33 offset:2504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v736*/, off, s33 offset:2508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v737*/, off, s33 offset:2512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v738*/, off, s33 offset:2516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v739*/, off, s33 offset:2520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v740*/, off, s33 offset:2524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v741*/, off, s33 offset:2528 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v742*/, off, s33 offset:2532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v743*/, off, s33 offset:2536 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v744*/, off, s33 offset:2540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v745*/, off, s33 offset:2544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v746*/, off, s33 offset:2548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v747*/, off, s33 offset:2552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v748*/, off, s33 offset:2556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v749*/, off, s33 offset:2560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v750*/, off, s33 offset:2564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v751*/, off, s33 offset:2568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v752*/, off, s33 offset:2572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v753*/, off, s33 offset:2576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v754*/, off, s33 offset:2580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v755*/, off, s33 offset:2584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v756*/, off, s33 offset:2588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v757*/, off, s33 offset:2592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v758*/, off, s33 offset:2596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v759*/, off, s33 offset:2600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v760*/, off, s33 offset:2604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v761*/, off, s33 offset:2608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v762*/, off, s33 offset:2612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v763*/, off, s33 offset:2616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v764*/, off, s33 offset:2620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v765*/, off, s33 offset:2624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v766*/, off, s33 offset:2628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v767*/, off, s33 offset:2632 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v742*/, off, s33 offset:2532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v743*/, off, s33 offset:2536 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v744*/, off, s33 offset:2540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v745*/, off, s33 offset:2544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v746*/, off, s33 offset:2548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v747*/, off, s33 offset:2552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v748*/, off, s33 offset:2556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v749*/, off, s33 offset:2560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v750*/, off, s33 offset:2564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v751*/, off, s33 offset:2568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v752*/, off, s33 offset:2572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v753*/, off, s33 offset:2576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v754*/, off, s33 offset:2580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v755*/, off, s33 offset:2584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v756*/, off, s33 offset:2588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v757*/, off, s33 offset:2592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v758*/, off, s33 offset:2596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v759*/, off, s33 offset:2600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v760*/, off, s33 offset:2604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v761*/, off, s33 offset:2608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v762*/, off, s33 offset:2612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v763*/, off, s33 offset:2616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v764*/, off, s33 offset:2620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v765*/, off, s33 offset:2624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v766*/, off, s33 offset:2628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v767*/, off, s33 offset:2632 nv ; GFX1250-DAGISEL-NEXT: s_set_vgpr_msb 0x80c0 ; msbs: dst=3 src0=0 src1=0 src2=0 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v768*/, off, s33 offset:2636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v769*/, off, s33 offset:2640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v770*/, off, s33 offset:2644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v771*/, off, s33 offset:2648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v772*/, off, s33 offset:2652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v773*/, off, s33 offset:2656 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v774*/, off, s33 offset:2660 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v775*/, off, s33 offset:2664 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v776*/, off, s33 offset:2668 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v777*/, off, s33 offset:2672 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v778*/, off, s33 offset:2676 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v779*/, off, s33 offset:2680 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v780*/, off, s33 offset:2684 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v781*/, off, s33 offset:2688 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v782*/, off, s33 offset:2692 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v783*/, off, s33 offset:2696 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v784*/, off, s33 offset:2700 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v785*/, off, s33 offset:2704 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v786*/, off, s33 offset:2708 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v787*/, off, s33 offset:2712 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v788*/, off, s33 offset:2716 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v789*/, off, s33 offset:2720 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v790*/, off, s33 offset:2724 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v791*/, off, s33 offset:2728 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v792*/, off, s33 offset:2732 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v793*/, off, s33 offset:2736 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v794*/, off, s33 offset:2740 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v795*/, off, s33 offset:2744 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v796*/, off, s33 offset:2748 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v797*/, off, s33 offset:2752 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v798*/, off, s33 offset:2756 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v799*/, off, s33 offset:2760 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v800*/, off, s33 offset:2764 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v801*/, off, s33 offset:2768 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v802*/, off, s33 offset:2772 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v803*/, off, s33 offset:2776 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v804*/, off, s33 offset:2780 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v0 /*v768*/, off, s33 offset:2636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v1 /*v769*/, off, s33 offset:2640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v2 /*v770*/, off, s33 offset:2644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v3 /*v771*/, off, s33 offset:2648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v4 /*v772*/, off, s33 offset:2652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v5 /*v773*/, off, s33 offset:2656 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v6 /*v774*/, off, s33 offset:2660 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v7 /*v775*/, off, s33 offset:2664 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v8 /*v776*/, off, s33 offset:2668 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v9 /*v777*/, off, s33 offset:2672 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v10 /*v778*/, off, s33 offset:2676 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v11 /*v779*/, off, s33 offset:2680 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v12 /*v780*/, off, s33 offset:2684 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v13 /*v781*/, off, s33 offset:2688 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v14 /*v782*/, off, s33 offset:2692 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v15 /*v783*/, off, s33 offset:2696 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v16 /*v784*/, off, s33 offset:2700 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v17 /*v785*/, off, s33 offset:2704 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v18 /*v786*/, off, s33 offset:2708 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v19 /*v787*/, off, s33 offset:2712 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v20 /*v788*/, off, s33 offset:2716 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v21 /*v789*/, off, s33 offset:2720 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v22 /*v790*/, off, s33 offset:2724 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v23 /*v791*/, off, s33 offset:2728 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v24 /*v792*/, off, s33 offset:2732 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v25 /*v793*/, off, s33 offset:2736 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v26 /*v794*/, off, s33 offset:2740 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v27 /*v795*/, off, s33 offset:2744 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v28 /*v796*/, off, s33 offset:2748 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v29 /*v797*/, off, s33 offset:2752 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v30 /*v798*/, off, s33 offset:2756 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v31 /*v799*/, off, s33 offset:2760 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v32 /*v800*/, off, s33 offset:2764 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v33 /*v801*/, off, s33 offset:2768 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v34 /*v802*/, off, s33 offset:2772 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v35 /*v803*/, off, s33 offset:2776 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v36 /*v804*/, off, s33 offset:2780 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v805*/, off, s33 offset:2784 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v806*/, off, s33 offset:2788 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v807*/, off, s33 offset:2792 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v808*/, off, s33 offset:2796 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v809*/, off, s33 offset:2800 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v810*/, off, s33 offset:2804 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v811*/, off, s33 offset:2808 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v812*/, off, s33 offset:2812 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v813*/, off, s33 offset:2816 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v814*/, off, s33 offset:2820 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v815*/, off, s33 offset:2824 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v816*/, off, s33 offset:2828 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v817*/, off, s33 offset:2832 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v818*/, off, s33 offset:2836 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v819*/, off, s33 offset:2840 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v820*/, off, s33 offset:2844 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v821*/, off, s33 offset:2848 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v822*/, off, s33 offset:2852 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v823*/, off, s33 offset:2856 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v824*/, off, s33 offset:2860 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v825*/, off, s33 offset:2864 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v826*/, off, s33 offset:2868 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v827*/, off, s33 offset:2872 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v828*/, off, s33 offset:2876 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v829*/, off, s33 offset:2880 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v830*/, off, s33 offset:2884 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v831*/, off, s33 offset:2888 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v832*/, off, s33 offset:2892 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v833*/, off, s33 offset:2896 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v834*/, off, s33 offset:2900 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v835*/, off, s33 offset:2904 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v836*/, off, s33 offset:2908 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v837*/, off, s33 offset:2912 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v838*/, off, s33 offset:2916 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v839*/, off, s33 offset:2920 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v840*/, off, s33 offset:2924 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v841*/, off, s33 offset:2928 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v842*/, off, s33 offset:2932 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v843*/, off, s33 offset:2936 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v844*/, off, s33 offset:2940 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v845*/, off, s33 offset:2944 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v846*/, off, s33 offset:2948 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v847*/, off, s33 offset:2952 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v848*/, off, s33 offset:2956 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v849*/, off, s33 offset:2960 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v850*/, off, s33 offset:2964 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v851*/, off, s33 offset:2968 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v852*/, off, s33 offset:2972 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v853*/, off, s33 offset:2976 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v854*/, off, s33 offset:2980 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v855*/, off, s33 offset:2984 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v856*/, off, s33 offset:2988 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v857*/, off, s33 offset:2992 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v858*/, off, s33 offset:2996 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v859*/, off, s33 offset:3000 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v860*/, off, s33 offset:3004 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v861*/, off, s33 offset:3008 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v862*/, off, s33 offset:3012 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v863*/, off, s33 offset:3016 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v864*/, off, s33 offset:3020 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v865*/, off, s33 offset:3024 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v866*/, off, s33 offset:3028 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v867*/, off, s33 offset:3032 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v37 /*v805*/, off, s33 offset:2784 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v38 /*v806*/, off, s33 offset:2788 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v39 /*v807*/, off, s33 offset:2792 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v40 /*v808*/, off, s33 offset:2796 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v41 /*v809*/, off, s33 offset:2800 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v42 /*v810*/, off, s33 offset:2804 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v43 /*v811*/, off, s33 offset:2808 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v44 /*v812*/, off, s33 offset:2812 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v45 /*v813*/, off, s33 offset:2816 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v46 /*v814*/, off, s33 offset:2820 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v47 /*v815*/, off, s33 offset:2824 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v48 /*v816*/, off, s33 offset:2828 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v49 /*v817*/, off, s33 offset:2832 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v50 /*v818*/, off, s33 offset:2836 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v51 /*v819*/, off, s33 offset:2840 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v52 /*v820*/, off, s33 offset:2844 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v53 /*v821*/, off, s33 offset:2848 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v54 /*v822*/, off, s33 offset:2852 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v55 /*v823*/, off, s33 offset:2856 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v56 /*v824*/, off, s33 offset:2860 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v57 /*v825*/, off, s33 offset:2864 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v58 /*v826*/, off, s33 offset:2868 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v59 /*v827*/, off, s33 offset:2872 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v60 /*v828*/, off, s33 offset:2876 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v61 /*v829*/, off, s33 offset:2880 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v62 /*v830*/, off, s33 offset:2884 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v63 /*v831*/, off, s33 offset:2888 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v64 /*v832*/, off, s33 offset:2892 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v65 /*v833*/, off, s33 offset:2896 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v66 /*v834*/, off, s33 offset:2900 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v67 /*v835*/, off, s33 offset:2904 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v68 /*v836*/, off, s33 offset:2908 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v69 /*v837*/, off, s33 offset:2912 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v70 /*v838*/, off, s33 offset:2916 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v71 /*v839*/, off, s33 offset:2920 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v72 /*v840*/, off, s33 offset:2924 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v73 /*v841*/, off, s33 offset:2928 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v74 /*v842*/, off, s33 offset:2932 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v75 /*v843*/, off, s33 offset:2936 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v76 /*v844*/, off, s33 offset:2940 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v77 /*v845*/, off, s33 offset:2944 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v78 /*v846*/, off, s33 offset:2948 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v79 /*v847*/, off, s33 offset:2952 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v80 /*v848*/, off, s33 offset:2956 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v81 /*v849*/, off, s33 offset:2960 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v82 /*v850*/, off, s33 offset:2964 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v83 /*v851*/, off, s33 offset:2968 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v84 /*v852*/, off, s33 offset:2972 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v85 /*v853*/, off, s33 offset:2976 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v86 /*v854*/, off, s33 offset:2980 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v87 /*v855*/, off, s33 offset:2984 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v88 /*v856*/, off, s33 offset:2988 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v89 /*v857*/, off, s33 offset:2992 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v90 /*v858*/, off, s33 offset:2996 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v91 /*v859*/, off, s33 offset:3000 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v92 /*v860*/, off, s33 offset:3004 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v93 /*v861*/, off, s33 offset:3008 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v94 /*v862*/, off, s33 offset:3012 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v95 /*v863*/, off, s33 offset:3016 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v96 /*v864*/, off, s33 offset:3020 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v97 /*v865*/, off, s33 offset:3024 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v98 /*v866*/, off, s33 offset:3028 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v99 /*v867*/, off, s33 offset:3032 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v868*/, off, s33 offset:3036 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v869*/, off, s33 offset:3040 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v870*/, off, s33 offset:3044 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v871*/, off, s33 offset:3048 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v872*/, off, s33 offset:3052 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v873*/, off, s33 offset:3056 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v874*/, off, s33 offset:3060 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v875*/, off, s33 offset:3064 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v876*/, off, s33 offset:3068 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v877*/, off, s33 offset:3072 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v878*/, off, s33 offset:3076 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v879*/, off, s33 offset:3080 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v880*/, off, s33 offset:3084 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v881*/, off, s33 offset:3088 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v882*/, off, s33 offset:3092 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v883*/, off, s33 offset:3096 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v884*/, off, s33 offset:3100 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v885*/, off, s33 offset:3104 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v886*/, off, s33 offset:3108 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v887*/, off, s33 offset:3112 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v888*/, off, s33 offset:3116 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v889*/, off, s33 offset:3120 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v890*/, off, s33 offset:3124 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v891*/, off, s33 offset:3128 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v892*/, off, s33 offset:3132 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v893*/, off, s33 offset:3136 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v894*/, off, s33 offset:3140 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v895*/, off, s33 offset:3144 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v896*/, off, s33 offset:3148 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v897*/, off, s33 offset:3152 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v898*/, off, s33 offset:3156 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v899*/, off, s33 offset:3160 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v900*/, off, s33 offset:3164 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v901*/, off, s33 offset:3168 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v902*/, off, s33 offset:3172 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v903*/, off, s33 offset:3176 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v904*/, off, s33 offset:3180 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v905*/, off, s33 offset:3184 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v906*/, off, s33 offset:3188 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v907*/, off, s33 offset:3192 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v908*/, off, s33 offset:3196 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v909*/, off, s33 offset:3200 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v910*/, off, s33 offset:3204 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v911*/, off, s33 offset:3208 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v912*/, off, s33 offset:3212 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v913*/, off, s33 offset:3216 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v914*/, off, s33 offset:3220 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v915*/, off, s33 offset:3224 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v916*/, off, s33 offset:3228 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v917*/, off, s33 offset:3232 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v918*/, off, s33 offset:3236 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v919*/, off, s33 offset:3240 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v920*/, off, s33 offset:3244 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v921*/, off, s33 offset:3248 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v922*/, off, s33 offset:3252 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v923*/, off, s33 offset:3256 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v924*/, off, s33 offset:3260 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v925*/, off, s33 offset:3264 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v926*/, off, s33 offset:3268 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v927*/, off, s33 offset:3272 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v928*/, off, s33 offset:3276 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v929*/, off, s33 offset:3280 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v930*/, off, s33 offset:3284 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v100 /*v868*/, off, s33 offset:3036 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v101 /*v869*/, off, s33 offset:3040 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v102 /*v870*/, off, s33 offset:3044 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v103 /*v871*/, off, s33 offset:3048 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v104 /*v872*/, off, s33 offset:3052 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v105 /*v873*/, off, s33 offset:3056 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v106 /*v874*/, off, s33 offset:3060 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v107 /*v875*/, off, s33 offset:3064 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v108 /*v876*/, off, s33 offset:3068 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v109 /*v877*/, off, s33 offset:3072 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v110 /*v878*/, off, s33 offset:3076 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v111 /*v879*/, off, s33 offset:3080 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v112 /*v880*/, off, s33 offset:3084 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v113 /*v881*/, off, s33 offset:3088 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v114 /*v882*/, off, s33 offset:3092 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v115 /*v883*/, off, s33 offset:3096 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v116 /*v884*/, off, s33 offset:3100 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v117 /*v885*/, off, s33 offset:3104 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v118 /*v886*/, off, s33 offset:3108 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v119 /*v887*/, off, s33 offset:3112 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v120 /*v888*/, off, s33 offset:3116 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v121 /*v889*/, off, s33 offset:3120 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v122 /*v890*/, off, s33 offset:3124 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v123 /*v891*/, off, s33 offset:3128 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v124 /*v892*/, off, s33 offset:3132 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v125 /*v893*/, off, s33 offset:3136 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v126 /*v894*/, off, s33 offset:3140 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v127 /*v895*/, off, s33 offset:3144 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v128 /*v896*/, off, s33 offset:3148 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v129 /*v897*/, off, s33 offset:3152 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v130 /*v898*/, off, s33 offset:3156 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v131 /*v899*/, off, s33 offset:3160 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v132 /*v900*/, off, s33 offset:3164 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v133 /*v901*/, off, s33 offset:3168 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v134 /*v902*/, off, s33 offset:3172 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v135 /*v903*/, off, s33 offset:3176 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v136 /*v904*/, off, s33 offset:3180 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v137 /*v905*/, off, s33 offset:3184 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v138 /*v906*/, off, s33 offset:3188 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v139 /*v907*/, off, s33 offset:3192 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v140 /*v908*/, off, s33 offset:3196 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v141 /*v909*/, off, s33 offset:3200 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v142 /*v910*/, off, s33 offset:3204 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v143 /*v911*/, off, s33 offset:3208 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v144 /*v912*/, off, s33 offset:3212 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v145 /*v913*/, off, s33 offset:3216 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v146 /*v914*/, off, s33 offset:3220 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v147 /*v915*/, off, s33 offset:3224 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v148 /*v916*/, off, s33 offset:3228 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v149 /*v917*/, off, s33 offset:3232 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v150 /*v918*/, off, s33 offset:3236 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v151 /*v919*/, off, s33 offset:3240 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v152 /*v920*/, off, s33 offset:3244 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v153 /*v921*/, off, s33 offset:3248 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v154 /*v922*/, off, s33 offset:3252 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v155 /*v923*/, off, s33 offset:3256 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v156 /*v924*/, off, s33 offset:3260 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v157 /*v925*/, off, s33 offset:3264 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v158 /*v926*/, off, s33 offset:3268 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v159 /*v927*/, off, s33 offset:3272 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v160 /*v928*/, off, s33 offset:3276 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v161 /*v929*/, off, s33 offset:3280 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v162 /*v930*/, off, s33 offset:3284 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x3e ; 252-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v931*/, off, s33 offset:3288 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v932*/, off, s33 offset:3292 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v933*/, off, s33 offset:3296 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v934*/, off, s33 offset:3300 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v935*/, off, s33 offset:3304 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v936*/, off, s33 offset:3308 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v937*/, off, s33 offset:3312 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v938*/, off, s33 offset:3316 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v939*/, off, s33 offset:3320 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v940*/, off, s33 offset:3324 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v941*/, off, s33 offset:3328 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v942*/, off, s33 offset:3332 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v943*/, off, s33 offset:3336 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v944*/, off, s33 offset:3340 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v945*/, off, s33 offset:3344 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v946*/, off, s33 offset:3348 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v947*/, off, s33 offset:3352 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v948*/, off, s33 offset:3356 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v949*/, off, s33 offset:3360 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v950*/, off, s33 offset:3364 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v951*/, off, s33 offset:3368 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v952*/, off, s33 offset:3372 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v953*/, off, s33 offset:3376 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v954*/, off, s33 offset:3380 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v955*/, off, s33 offset:3384 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v956*/, off, s33 offset:3388 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v957*/, off, s33 offset:3392 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v958*/, off, s33 offset:3396 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v959*/, off, s33 offset:3400 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v960*/, off, s33 offset:3404 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v961*/, off, s33 offset:3408 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v962*/, off, s33 offset:3412 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v963*/, off, s33 offset:3416 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v964*/, off, s33 offset:3420 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v965*/, off, s33 offset:3424 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v966*/, off, s33 offset:3428 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v967*/, off, s33 offset:3432 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v968*/, off, s33 offset:3436 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v969*/, off, s33 offset:3440 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v970*/, off, s33 offset:3444 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v971*/, off, s33 offset:3448 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v972*/, off, s33 offset:3452 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v973*/, off, s33 offset:3456 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v974*/, off, s33 offset:3460 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v975*/, off, s33 offset:3464 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v976*/, off, s33 offset:3468 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v977*/, off, s33 offset:3472 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v978*/, off, s33 offset:3476 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v979*/, off, s33 offset:3480 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v980*/, off, s33 offset:3484 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v981*/, off, s33 offset:3488 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v982*/, off, s33 offset:3492 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v983*/, off, s33 offset:3496 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v984*/, off, s33 offset:3500 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v985*/, off, s33 offset:3504 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v986*/, off, s33 offset:3508 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v987*/, off, s33 offset:3512 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v988*/, off, s33 offset:3516 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v989*/, off, s33 offset:3520 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v990*/, off, s33 offset:3524 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v991*/, off, s33 offset:3528 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v992*/, off, s33 offset:3532 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v993*/, off, s33 offset:3536 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v163 /*v931*/, off, s33 offset:3288 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v164 /*v932*/, off, s33 offset:3292 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v165 /*v933*/, off, s33 offset:3296 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v166 /*v934*/, off, s33 offset:3300 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v167 /*v935*/, off, s33 offset:3304 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v168 /*v936*/, off, s33 offset:3308 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v169 /*v937*/, off, s33 offset:3312 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v170 /*v938*/, off, s33 offset:3316 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v171 /*v939*/, off, s33 offset:3320 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v172 /*v940*/, off, s33 offset:3324 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v173 /*v941*/, off, s33 offset:3328 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v174 /*v942*/, off, s33 offset:3332 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v175 /*v943*/, off, s33 offset:3336 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v176 /*v944*/, off, s33 offset:3340 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v177 /*v945*/, off, s33 offset:3344 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v178 /*v946*/, off, s33 offset:3348 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v179 /*v947*/, off, s33 offset:3352 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v180 /*v948*/, off, s33 offset:3356 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v181 /*v949*/, off, s33 offset:3360 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v182 /*v950*/, off, s33 offset:3364 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v183 /*v951*/, off, s33 offset:3368 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v184 /*v952*/, off, s33 offset:3372 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v185 /*v953*/, off, s33 offset:3376 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v186 /*v954*/, off, s33 offset:3380 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v187 /*v955*/, off, s33 offset:3384 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v188 /*v956*/, off, s33 offset:3388 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v189 /*v957*/, off, s33 offset:3392 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v190 /*v958*/, off, s33 offset:3396 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v191 /*v959*/, off, s33 offset:3400 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v192 /*v960*/, off, s33 offset:3404 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v193 /*v961*/, off, s33 offset:3408 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v194 /*v962*/, off, s33 offset:3412 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v195 /*v963*/, off, s33 offset:3416 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v196 /*v964*/, off, s33 offset:3420 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v197 /*v965*/, off, s33 offset:3424 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v198 /*v966*/, off, s33 offset:3428 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v199 /*v967*/, off, s33 offset:3432 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v200 /*v968*/, off, s33 offset:3436 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v201 /*v969*/, off, s33 offset:3440 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v202 /*v970*/, off, s33 offset:3444 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v203 /*v971*/, off, s33 offset:3448 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v204 /*v972*/, off, s33 offset:3452 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v205 /*v973*/, off, s33 offset:3456 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v206 /*v974*/, off, s33 offset:3460 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v207 /*v975*/, off, s33 offset:3464 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v208 /*v976*/, off, s33 offset:3468 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v209 /*v977*/, off, s33 offset:3472 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v210 /*v978*/, off, s33 offset:3476 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v211 /*v979*/, off, s33 offset:3480 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v212 /*v980*/, off, s33 offset:3484 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v213 /*v981*/, off, s33 offset:3488 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v214 /*v982*/, off, s33 offset:3492 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v215 /*v983*/, off, s33 offset:3496 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v216 /*v984*/, off, s33 offset:3500 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v217 /*v985*/, off, s33 offset:3504 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v218 /*v986*/, off, s33 offset:3508 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v219 /*v987*/, off, s33 offset:3512 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v220 /*v988*/, off, s33 offset:3516 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v221 /*v989*/, off, s33 offset:3520 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v222 /*v990*/, off, s33 offset:3524 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v223 /*v991*/, off, s33 offset:3528 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v224 /*v992*/, off, s33 offset:3532 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v225 /*v993*/, off, s33 offset:3536 nv ; GFX1250-DAGISEL-NEXT: s_clause 0x1d ; 120-byte Folded Reload -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v994*/, off, s33 offset:3540 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v995*/, off, s33 offset:3544 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v996*/, off, s33 offset:3548 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v997*/, off, s33 offset:3552 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v998*/, off, s33 offset:3556 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v999*/, off, s33 offset:3560 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v1000*/, off, s33 offset:3564 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v1001*/, off, s33 offset:3568 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v1002*/, off, s33 offset:3572 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v1003*/, off, s33 offset:3576 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v1004*/, off, s33 offset:3580 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v1005*/, off, s33 offset:3584 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v1006*/, off, s33 offset:3588 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v1007*/, off, s33 offset:3592 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v1008*/, off, s33 offset:3596 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v1009*/, off, s33 offset:3600 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v1010*/, off, s33 offset:3604 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v1011*/, off, s33 offset:3608 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v1012*/, off, s33 offset:3612 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v1013*/, off, s33 offset:3616 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v1014*/, off, s33 offset:3620 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v1015*/, off, s33 offset:3624 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v1016*/, off, s33 offset:3628 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v1017*/, off, s33 offset:3632 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v1018*/, off, s33 offset:3636 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v1019*/, off, s33 offset:3640 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v1020*/, off, s33 offset:3644 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v1021*/, off, s33 offset:3648 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v1022*/, off, s33 offset:3652 -; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v1023*/, off, s33 offset:3656 +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v226 /*v994*/, off, s33 offset:3540 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v227 /*v995*/, off, s33 offset:3544 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v228 /*v996*/, off, s33 offset:3548 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v229 /*v997*/, off, s33 offset:3552 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v230 /*v998*/, off, s33 offset:3556 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v231 /*v999*/, off, s33 offset:3560 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v232 /*v1000*/, off, s33 offset:3564 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v233 /*v1001*/, off, s33 offset:3568 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v234 /*v1002*/, off, s33 offset:3572 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v235 /*v1003*/, off, s33 offset:3576 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v236 /*v1004*/, off, s33 offset:3580 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v237 /*v1005*/, off, s33 offset:3584 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v238 /*v1006*/, off, s33 offset:3588 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v239 /*v1007*/, off, s33 offset:3592 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v240 /*v1008*/, off, s33 offset:3596 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v241 /*v1009*/, off, s33 offset:3600 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v242 /*v1010*/, off, s33 offset:3604 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v243 /*v1011*/, off, s33 offset:3608 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v244 /*v1012*/, off, s33 offset:3612 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v245 /*v1013*/, off, s33 offset:3616 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v246 /*v1014*/, off, s33 offset:3620 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v247 /*v1015*/, off, s33 offset:3624 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v248 /*v1016*/, off, s33 offset:3628 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v249 /*v1017*/, off, s33 offset:3632 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v250 /*v1018*/, off, s33 offset:3636 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v251 /*v1019*/, off, s33 offset:3640 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v252 /*v1020*/, off, s33 offset:3644 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v253 /*v1021*/, off, s33 offset:3648 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v254 /*v1022*/, off, s33 offset:3652 nv +; GFX1250-DAGISEL-NEXT: scratch_load_b32 v255 /*v1023*/, off, s33 offset:3656 nv ; GFX1250-DAGISEL-NEXT: s_wait_xcnt 0x0 ; GFX1250-DAGISEL-NEXT: s_mov_b32 exec_lo, s4 ; GFX1250-DAGISEL-NEXT: s_mov_b32 s33, s0 diff --git a/llvm/test/CodeGen/ARM/build-attributes-fn-attr3.ll b/llvm/test/CodeGen/ARM/build-attributes-fn-attr3.ll index 27d1dc20bd815..e082e34ca1253 100644 --- a/llvm/test/CodeGen/ARM/build-attributes-fn-attr3.ll +++ b/llvm/test/CodeGen/ARM/build-attributes-fn-attr3.ll @@ -17,4 +17,4 @@ entry: declare float @llvm.fma.f32(float, float, float) -attributes #0 = { minsize norecurse nounwind optsize readnone "no-trapping-math"="true" "denormal-fp-math"="ieee"} +attributes #0 = { minsize norecurse nounwind optsize readnone "no-trapping-math"="true" denormal_fpenv(ieee)} diff --git a/llvm/test/CodeGen/ARM/build-attributes-fn-attr4.ll b/llvm/test/CodeGen/ARM/build-attributes-fn-attr4.ll index 9c8dd8d95c61c..10cca563adc4a 100644 --- a/llvm/test/CodeGen/ARM/build-attributes-fn-attr4.ll +++ b/llvm/test/CodeGen/ARM/build-attributes-fn-attr4.ll @@ -16,4 +16,4 @@ entry: declare float @llvm.fma.f32(float, float, float) -attributes #0 = { minsize norecurse nounwind optsize readnone "denormal-fp-math"="positive-zero,positive-zero" } +attributes #0 = { minsize norecurse nounwind optsize readnone denormal_fpenv(positivezero|positivezero) } diff --git a/llvm/test/CodeGen/ARM/build-attributes-fn-attr5.ll b/llvm/test/CodeGen/ARM/build-attributes-fn-attr5.ll index cda3ea0fc6d18..c294582f4c462 100644 --- a/llvm/test/CodeGen/ARM/build-attributes-fn-attr5.ll +++ b/llvm/test/CodeGen/ARM/build-attributes-fn-attr5.ll @@ -16,4 +16,4 @@ entry: declare float @llvm.fma.f32(float, float, float) -attributes #0 = { minsize norecurse nounwind optsize readnone "denormal-fp-math"="preserve-sign,preserve-sign"} +attributes #0 = { minsize norecurse nounwind optsize readnone denormal_fpenv(preservesign)} diff --git a/llvm/test/CodeGen/ARM/build-attributes-fn-attr6.ll b/llvm/test/CodeGen/ARM/build-attributes-fn-attr6.ll index 59d0a40198392..85e3dbf5d5bd3 100644 --- a/llvm/test/CodeGen/ARM/build-attributes-fn-attr6.ll +++ b/llvm/test/CodeGen/ARM/build-attributes-fn-attr6.ll @@ -22,5 +22,5 @@ entry: declare float @llvm.fma.f32(float, float, float) -attributes #0 = { minsize norecurse nounwind optsize readnone "denormal-fp-math"="preserve-sign,preserve-sign"} -attributes #1 = { minsize norecurse nounwind optsize readnone "denormal-fp-math"="positive-zero,positive-zero"} +attributes #0 = { minsize norecurse nounwind optsize readnone denormal_fpenv(preservesign)} +attributes #1 = { minsize norecurse nounwind optsize readnone denormal_fpenv(positivezero|positivezero)} diff --git a/llvm/test/CodeGen/ARM/build-attributes-module.ll b/llvm/test/CodeGen/ARM/build-attributes-module.ll new file mode 100644 index 0000000000000..aefcd4ef5143b --- /dev/null +++ b/llvm/test/CodeGen/ARM/build-attributes-module.ll @@ -0,0 +1,14 @@ +; RUN: llc %s -mtriple=arm-none-none-eabi -o - | FileCheck %s + +define void @f() { + ret void +} + +!llvm.module.flags = !{!0, !1, !2} + +; CHECK-NOT: .eabi_attribute 20 +!0 = !{i32 2, !"arm-eabi-fp-denormal", i32 0} +; CHECK: .eabi_attribute 21, 1 +!1 = !{i32 2, !"arm-eabi-fp-exceptions", i32 1} +; CHECK: .eabi_attribute 23, 1 +!2 = !{i32 2, !"arm-eabi-fp-number-model", i32 1} diff --git a/llvm/test/CodeGen/ARM/clang-section.ll b/llvm/test/CodeGen/ARM/clang-section.ll index 9c32ab27cd9f2..c77d9d1610c79 100644 --- a/llvm/test/CodeGen/ARM/clang-section.ll +++ b/llvm/test/CodeGen/ARM/clang-section.ll @@ -35,8 +35,8 @@ attributes #0 = { "bss-section"="my_bss.1" "data-section"="my_data.1" "rodata-se attributes #1 = { "data-section"="my_data.1" "rodata-section"="my_rodata.1" } attributes #2 = { "bss-section"="my_bss.2" "rodata-section"="my_rodata.1" } attributes #3 = { "bss-section"="my_bss.2" "data-section"="my_data.2" "rodata-section"="my_rodata.2" } -attributes #6 = { "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+dsp,+fp16,+neon,+vfp3" "use-soft-float"="false" } -attributes #7 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+dsp,+fp16,+neon,+vfp3" "use-soft-float"="false" } +attributes #6 = { "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+dsp,+fp16,+neon,+vfp3" "use-soft-float"="false" } +attributes #7 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a9" "target-features"="+dsp,+fp16,+neon,+vfp3" "use-soft-float"="false" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/llvm/test/CodeGen/ARM/cls.ll b/llvm/test/CodeGen/ARM/cls.ll index cccb38d0766f3..273460c1aa7a2 100644 --- a/llvm/test/CodeGen/ARM/cls.ll +++ b/llvm/test/CodeGen/ARM/cls.ll @@ -1,27 +1,138 @@ -; RUN: llc -mtriple=armv5 %s -o - | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=armv5 %s -o - | FileCheck %s --check-prefixes=CHECKV5 +; RUN: llc -mtriple=thumbv8.1-m.main %s -o - | FileCheck %s --check-prefix=CHECKV8 -; CHECK: eor [[T:r[0-9]+]], [[T]], [[T]], asr #31 -; CHECK-NEXT: mov [[C1:r[0-9]+]], #1 -; CHECK-NEXT: orr [[T]], [[C1]], [[T]], lsl #1 -; CHECK-NEXT: clz [[T]], [[T]] define i32 @cls(i32 %t) { +; CHECKV5-LABEL: cls: +; CHECKV5: @ %bb.0: +; CHECKV5-NEXT: eor r0, r0, r0, asr #31 +; CHECKV5-NEXT: mov r1, #1 +; CHECKV5-NEXT: orr r0, r1, r0, lsl #1 +; CHECKV5-NEXT: clz r0, r0 +; CHECKV5-NEXT: bx lr +; +; CHECKV8-LABEL: cls: +; CHECKV8: @ %bb.0: +; CHECKV8-NEXT: asrs r1, r0, #31 +; CHECKV8-NEXT: eors r1, r0 +; CHECKV8-NEXT: lsls r0, r1, #1 +; CHECKV8-NEXT: lsrs r1, r0, #1 +; CHECKV8-NEXT: orrs r1, r0 +; CHECKV8-NEXT: lsrs r0, r1, #2 +; CHECKV8-NEXT: orrs r0, r1 +; CHECKV8-NEXT: lsrs r1, r0, #4 +; CHECKV8-NEXT: orrs r1, r0 +; CHECKV8-NEXT: lsrs r0, r1, #8 +; CHECKV8-NEXT: orrs r0, r1 +; CHECKV8-NEXT: lsrs r1, r0, #16 +; CHECKV8-NEXT: orrs r1, r0 +; CHECKV8-NEXT: mvns r0, r1 +; CHECKV8-NEXT: movs r1, #1 +; CHECKV8-NEXT: lsrs r2, r0, #1 +; CHECKV8-NEXT: bics r0, r1 +; CHECKV8-NEXT: ldr r1, .LCPI0_0 +; CHECKV8-NEXT: ands r1, r2 +; CHECKV8-NEXT: subs r0, r0, r1 +; CHECKV8-NEXT: ldr r1, .LCPI0_1 +; CHECKV8-NEXT: lsrs r2, r0, #2 +; CHECKV8-NEXT: ands r0, r1 +; CHECKV8-NEXT: ands r2, r1 +; CHECKV8-NEXT: adds r0, r0, r2 +; CHECKV8-NEXT: lsrs r1, r0, #4 +; CHECKV8-NEXT: adds r0, r0, r1 +; CHECKV8-NEXT: ldr r1, .LCPI0_2 +; CHECKV8-NEXT: ands r1, r0 +; CHECKV8-NEXT: ldr r0, .LCPI0_3 +; CHECKV8-NEXT: muls r0, r1, r0 +; CHECKV8-NEXT: lsrs r0, r0, #24 +; CHECKV8-NEXT: bx lr +; CHECKV8-NEXT: .p2align 2 +; CHECKV8-NEXT: @ %bb.1: +; CHECKV8-NEXT: .LCPI0_0: +; CHECKV8-NEXT: .long 1431655765 @ 0x55555555 +; CHECKV8-NEXT: .LCPI0_1: +; CHECKV8-NEXT: .long 858993459 @ 0x33333333 +; CHECKV8-NEXT: .LCPI0_2: +; CHECKV8-NEXT: .long 252645135 @ 0xf0f0f0f +; CHECKV8-NEXT: .LCPI0_3: +; CHECKV8-NEXT: .long 16843009 @ 0x1010101 %cls.i = call i32 @llvm.arm.cls(i32 %t) ret i32 %cls.i } -; CHECK: cmp r1, #0 -; CHECK: mvnne [[ADJUSTEDLO:r[0-9]+]], r0 -; CHECK: clz [[CLZLO:r[0-9]+]], [[ADJUSTEDLO]] -; CHECK: eor [[A:r[0-9]+]], r1, r1, asr #31 -; CHECK: mov r1, #1 -; CHECK: orr [[A]], r1, [[A]], lsl #1 -; CHECK: clz [[CLSHI:r[0-9]+]], [[A]] -; CHECK: cmp [[CLSHI]], #31 -; CHECK: addeq r0, [[CLZLO]], #31 define i32 @cls64(i64 %t) { +; CHECKV5-LABEL: cls64: +; CHECKV5: @ %bb.0: +; CHECKV5-NEXT: cmp r1, #0 +; CHECKV5-NEXT: mvnne r0, r0 +; CHECKV5-NEXT: clz r2, r0 +; CHECKV5-NEXT: eor r0, r1, r1, asr #31 +; CHECKV5-NEXT: mov r1, #1 +; CHECKV5-NEXT: orr r0, r1, r0, lsl #1 +; CHECKV5-NEXT: clz r0, r0 +; CHECKV5-NEXT: cmp r0, #31 +; CHECKV5-NEXT: addeq r0, r2, #31 +; CHECKV5-NEXT: bx lr +; +; CHECKV8-LABEL: cls64: +; CHECKV8: @ %bb.0: +; CHECKV8-NEXT: push {r4, lr} +; CHECKV8-NEXT: movs r4, r0 +; CHECKV8-NEXT: cmp r1, #0 +; CHECKV8-NEXT: beq .LBB1_2 +; CHECKV8-NEXT: @ %bb.1: +; CHECKV8-NEXT: mvns r4, r4 +; CHECKV8-NEXT: .LBB1_2: +; CHECKV8-NEXT: asrs r0, r1, #31 +; CHECKV8-NEXT: eors r0, r1 +; CHECKV8-NEXT: lsls r0, r0, #1 +; CHECKV8-NEXT: adds r0, r0, #1 +; CHECKV8-NEXT: bl __clzsi2 +; CHECKV8-NEXT: cmp r0, #31 +; CHECKV8-NEXT: bne .LBB1_4 +; CHECKV8-NEXT: @ %bb.3: +; CHECKV8-NEXT: lsrs r0, r4, #1 +; CHECKV8-NEXT: orrs r0, r4 +; CHECKV8-NEXT: lsrs r1, r0, #2 +; CHECKV8-NEXT: orrs r1, r0 +; CHECKV8-NEXT: lsrs r0, r1, #4 +; CHECKV8-NEXT: orrs r0, r1 +; CHECKV8-NEXT: lsrs r1, r0, #8 +; CHECKV8-NEXT: orrs r1, r0 +; CHECKV8-NEXT: lsrs r0, r1, #16 +; CHECKV8-NEXT: orrs r0, r1 +; CHECKV8-NEXT: mvns r0, r0 +; CHECKV8-NEXT: lsrs r1, r0, #1 +; CHECKV8-NEXT: ldr r2, .LCPI1_0 +; CHECKV8-NEXT: ands r2, r1 +; CHECKV8-NEXT: subs r0, r0, r2 +; CHECKV8-NEXT: ldr r1, .LCPI1_1 +; CHECKV8-NEXT: lsrs r2, r0, #2 +; CHECKV8-NEXT: ands r0, r1 +; CHECKV8-NEXT: ands r2, r1 +; CHECKV8-NEXT: adds r0, r0, r2 +; CHECKV8-NEXT: lsrs r1, r0, #4 +; CHECKV8-NEXT: adds r0, r0, r1 +; CHECKV8-NEXT: ldr r1, .LCPI1_2 +; CHECKV8-NEXT: ands r1, r0 +; CHECKV8-NEXT: ldr r0, .LCPI1_3 +; CHECKV8-NEXT: muls r0, r1, r0 +; CHECKV8-NEXT: lsrs r0, r0, #24 +; CHECKV8-NEXT: adds r0, #31 +; CHECKV8-NEXT: .LBB1_4: +; CHECKV8-NEXT: pop {r4} +; CHECKV8-NEXT: pop {r1} +; CHECKV8-NEXT: bx r1 +; CHECKV8-NEXT: .p2align 2 +; CHECKV8-NEXT: @ %bb.5: +; CHECKV8-NEXT: .LCPI1_0: +; CHECKV8-NEXT: .long 1431655765 @ 0x55555555 +; CHECKV8-NEXT: .LCPI1_1: +; CHECKV8-NEXT: .long 858993459 @ 0x33333333 +; CHECKV8-NEXT: .LCPI1_2: +; CHECKV8-NEXT: .long 252645135 @ 0xf0f0f0f +; CHECKV8-NEXT: .LCPI1_3: +; CHECKV8-NEXT: .long 16843009 @ 0x1010101 %cls.i = call i32 @llvm.arm.cls64(i64 %t) ret i32 %cls.i } - -declare i32 @llvm.arm.cls(i32) nounwind -declare i32 @llvm.arm.cls64(i64) nounwind diff --git a/llvm/test/CodeGen/ARM/cmse-clear-float-bigend.mir b/llvm/test/CodeGen/ARM/cmse-clear-float-bigend.mir index ae36da480537f..1be25ae3d3dc1 100644 --- a/llvm/test/CodeGen/ARM/cmse-clear-float-bigend.mir +++ b/llvm/test/CodeGen/ARM/cmse-clear-float-bigend.mir @@ -16,7 +16,7 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #1 - attributes #0 = { "cmse_nonsecure_entry" nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+8msecext,+armv8-m.main,-d32,-fp64,+fp-armv8,+hwdiv,+thumb-mode,-crypto,-fullfp16,-neon" "use-soft-float"="false" } + attributes #0 = { "cmse_nonsecure_entry" nounwind "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+8msecext,+armv8-m.main,-d32,-fp64,+fp-armv8,+hwdiv,+thumb-mode,-crypto,-fullfp16,-neon" "use-soft-float"="false" } attributes #1 = { nounwind } attributes #2 = { "cmse_nonsecure_call" nounwind } diff --git a/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll b/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll index 52fe5ce1a8a5f..2185bd8a2a138 100644 --- a/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll +++ b/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll @@ -253,9 +253,9 @@ define half @fp16_vminnm_NNNu(half %b) { ; CHECK-NEXT: vmov.f16 s2, #1.200000e+01 ; CHECK-NEXT: vminnm.f16 s0, s0, s2 ; CHECK-NEXT: vldr.16 s2, .LCPI14_0 -; CHECK-NEXT: vcmp.f16 s0, s2 +; CHECK-NEXT: vcmp.f16 s2, s0 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-NEXT: vselge.f16 s0, s2, s0 +; CHECK-NEXT: vselgt.f16 s0, s0, s2 ; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: bx lr ; CHECK-NEXT: .p2align 1 @@ -277,9 +277,9 @@ define half @fp16_vminnm_NNNule(half %b) { ; CHECK-NEXT: vmov.f16 s0, r0 ; CHECK-NEXT: vminnm.f16 s0, s0, s2 ; CHECK-NEXT: vldr.16 s2, .LCPI15_1 -; CHECK-NEXT: vcmp.f16 s0, s2 +; CHECK-NEXT: vcmp.f16 s2, s0 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-NEXT: vselgt.f16 s0, s2, s0 +; CHECK-NEXT: vselge.f16 s0, s0, s2 ; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: bx lr ; CHECK-NEXT: .p2align 1 @@ -434,9 +434,9 @@ define half @fp16_vmaxnm_NNNu(half %b) { ; CHECK-NEXT: vmov.f16 s2, #1.200000e+01 ; CHECK-NEXT: vmaxnm.f16 s0, s0, s2 ; CHECK-NEXT: vldr.16 s2, .LCPI21_0 -; CHECK-NEXT: vcmp.f16 s2, s0 +; CHECK-NEXT: vcmp.f16 s0, s2 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-NEXT: vselge.f16 s0, s2, s0 +; CHECK-NEXT: vselgt.f16 s0, s0, s2 ; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: bx lr ; CHECK-NEXT: .p2align 1 @@ -458,9 +458,9 @@ define half @fp16_vmaxnm_NNNuge(half %b) { ; CHECK-NEXT: vmov.f16 s0, r0 ; CHECK-NEXT: vmaxnm.f16 s0, s0, s2 ; CHECK-NEXT: vldr.16 s2, .LCPI22_1 -; CHECK-NEXT: vcmp.f16 s2, s0 +; CHECK-NEXT: vcmp.f16 s0, s2 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-NEXT: vselgt.f16 s0, s2, s0 +; CHECK-NEXT: vselge.f16 s0, s0, s2 ; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: bx lr ; CHECK-NEXT: .p2align 1 @@ -483,9 +483,9 @@ define half @fp16_vminmaxnm_neg0(half %a) { ; CHECK-NEXT: vldr.16 s0, .LCPI23_0 ; CHECK-NEXT: vmov.f16 s2, r0 ; CHECK-NEXT: vminnm.f16 s2, s2, s0 -; CHECK-NEXT: vcmp.f16 s0, s2 +; CHECK-NEXT: vcmp.f16 s2, s0 ; CHECK-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-NEXT: vselge.f16 s0, s0, s2 +; CHECK-NEXT: vselgt.f16 s0, s2, s0 ; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: bx lr ; CHECK-NEXT: .p2align 1 diff --git a/llvm/test/CodeGen/ARM/i64_volatile_load_store.ll b/llvm/test/CodeGen/ARM/i64_volatile_load_store.ll index ca5fd2bc14f40..125326fd754fa 100644 --- a/llvm/test/CodeGen/ARM/i64_volatile_load_store.ll +++ b/llvm/test/CodeGen/ARM/i64_volatile_load_store.ll @@ -121,23 +121,22 @@ define void @test_unaligned() { ; CHECK-ARMV5TE-NEXT: push {r4, r5, r6, lr} ; CHECK-ARMV5TE-NEXT: ldr r0, .LCPI1_0 ; CHECK-ARMV5TE-NEXT: ldr r6, .LCPI1_1 -; CHECK-ARMV5TE-NEXT: mov r1, r0 -; CHECK-ARMV5TE-NEXT: ldrb lr, [r1, #4]! -; CHECK-ARMV5TE-NEXT: ldrb r3, [r1, #2] -; CHECK-ARMV5TE-NEXT: ldrb r12, [r1, #3] -; CHECK-ARMV5TE-NEXT: ldrb r1, [r0] -; CHECK-ARMV5TE-NEXT: ldrb r2, [r0, #1] -; CHECK-ARMV5TE-NEXT: ldrb r4, [r0, #2] -; CHECK-ARMV5TE-NEXT: ldrb r5, [r0, #3] -; CHECK-ARMV5TE-NEXT: ldrb r0, [r0, #5] -; CHECK-ARMV5TE-NEXT: strb r0, [r6, #5] -; CHECK-ARMV5TE-NEXT: strb r4, [r6, #2] -; CHECK-ARMV5TE-NEXT: strb r5, [r6, #3] -; CHECK-ARMV5TE-NEXT: strb r1, [r6] -; CHECK-ARMV5TE-NEXT: strb r2, [r6, #1] -; CHECK-ARMV5TE-NEXT: strb lr, [r6, #4]! +; CHECK-ARMV5TE-NEXT: ldrb r12, [r0] +; CHECK-ARMV5TE-NEXT: ldrb lr, [r0, #1] +; CHECK-ARMV5TE-NEXT: ldrb r3, [r0, #2] +; CHECK-ARMV5TE-NEXT: ldrb r1, [r0, #3] +; CHECK-ARMV5TE-NEXT: ldrb r2, [r0, #5] +; CHECK-ARMV5TE-NEXT: ldrb r4, [r0, #4] +; CHECK-ARMV5TE-NEXT: ldrb r5, [r0, #7] +; CHECK-ARMV5TE-NEXT: ldrb r0, [r0, #6] +; CHECK-ARMV5TE-NEXT: strb r0, [r6, #6] +; CHECK-ARMV5TE-NEXT: strb r5, [r6, #7] +; CHECK-ARMV5TE-NEXT: strb r4, [r6, #4] +; CHECK-ARMV5TE-NEXT: strb r2, [r6, #5] ; CHECK-ARMV5TE-NEXT: strb r3, [r6, #2] -; CHECK-ARMV5TE-NEXT: strb r12, [r6, #3] +; CHECK-ARMV5TE-NEXT: strb r1, [r6, #3] +; CHECK-ARMV5TE-NEXT: strb r12, [r6] +; CHECK-ARMV5TE-NEXT: strb lr, [r6, #1] ; CHECK-ARMV5TE-NEXT: pop {r4, r5, r6, pc} ; CHECK-ARMV5TE-NEXT: .p2align 2 ; CHECK-ARMV5TE-NEXT: @ %bb.1: @@ -164,23 +163,22 @@ define void @test_unaligned() { ; CHECK-ARMV4T-NEXT: push {r4, r5, r6, lr} ; CHECK-ARMV4T-NEXT: ldr r0, .LCPI1_0 ; CHECK-ARMV4T-NEXT: ldr r6, .LCPI1_1 -; CHECK-ARMV4T-NEXT: mov r1, r0 -; CHECK-ARMV4T-NEXT: ldrb lr, [r1, #4]! -; CHECK-ARMV4T-NEXT: ldrb r3, [r1, #2] -; CHECK-ARMV4T-NEXT: ldrb r12, [r1, #3] -; CHECK-ARMV4T-NEXT: ldrb r1, [r0] -; CHECK-ARMV4T-NEXT: ldrb r2, [r0, #1] -; CHECK-ARMV4T-NEXT: ldrb r4, [r0, #2] -; CHECK-ARMV4T-NEXT: ldrb r5, [r0, #3] -; CHECK-ARMV4T-NEXT: ldrb r0, [r0, #5] -; CHECK-ARMV4T-NEXT: strb r0, [r6, #5] -; CHECK-ARMV4T-NEXT: strb r4, [r6, #2] -; CHECK-ARMV4T-NEXT: strb r5, [r6, #3] -; CHECK-ARMV4T-NEXT: strb r1, [r6] -; CHECK-ARMV4T-NEXT: strb r2, [r6, #1] -; CHECK-ARMV4T-NEXT: strb lr, [r6, #4]! +; CHECK-ARMV4T-NEXT: ldrb r12, [r0] +; CHECK-ARMV4T-NEXT: ldrb lr, [r0, #1] +; CHECK-ARMV4T-NEXT: ldrb r3, [r0, #2] +; CHECK-ARMV4T-NEXT: ldrb r1, [r0, #3] +; CHECK-ARMV4T-NEXT: ldrb r2, [r0, #5] +; CHECK-ARMV4T-NEXT: ldrb r4, [r0, #4] +; CHECK-ARMV4T-NEXT: ldrb r5, [r0, #7] +; CHECK-ARMV4T-NEXT: ldrb r0, [r0, #6] +; CHECK-ARMV4T-NEXT: strb r0, [r6, #6] +; CHECK-ARMV4T-NEXT: strb r5, [r6, #7] +; CHECK-ARMV4T-NEXT: strb r4, [r6, #4] +; CHECK-ARMV4T-NEXT: strb r2, [r6, #5] ; CHECK-ARMV4T-NEXT: strb r3, [r6, #2] -; CHECK-ARMV4T-NEXT: strb r12, [r6, #3] +; CHECK-ARMV4T-NEXT: strb r1, [r6, #3] +; CHECK-ARMV4T-NEXT: strb r12, [r6] +; CHECK-ARMV4T-NEXT: strb lr, [r6, #1] ; CHECK-ARMV4T-NEXT: pop {r4, r5, r6, lr} ; CHECK-ARMV4T-NEXT: bx lr ; CHECK-ARMV4T-NEXT: .p2align 2 @@ -210,23 +208,22 @@ define void @test_unaligned() { ; CHECK-ARMV7-STRICT-NEXT: movw r6, :lower16:y_unaligned ; CHECK-ARMV7-STRICT-NEXT: movt r0, :upper16:x_unaligned ; CHECK-ARMV7-STRICT-NEXT: movt r6, :upper16:y_unaligned -; CHECK-ARMV7-STRICT-NEXT: mov r1, r0 -; CHECK-ARMV7-STRICT-NEXT: ldrb r12, [r1, #4]! -; CHECK-ARMV7-STRICT-NEXT: ldrb r3, [r0] +; CHECK-ARMV7-STRICT-NEXT: ldrb r12, [r0] ; CHECK-ARMV7-STRICT-NEXT: ldrb lr, [r0, #1] -; CHECK-ARMV7-STRICT-NEXT: ldrb r2, [r0, #2] -; CHECK-ARMV7-STRICT-NEXT: ldrb r4, [r0, #3] -; CHECK-ARMV7-STRICT-NEXT: ldrb r0, [r0, #5] -; CHECK-ARMV7-STRICT-NEXT: ldrb r5, [r1, #2] -; CHECK-ARMV7-STRICT-NEXT: ldrb r1, [r1, #3] -; CHECK-ARMV7-STRICT-NEXT: strb r0, [r6, #5] -; CHECK-ARMV7-STRICT-NEXT: strb r2, [r6, #2] -; CHECK-ARMV7-STRICT-NEXT: strb r4, [r6, #3] -; CHECK-ARMV7-STRICT-NEXT: strb r3, [r6] -; CHECK-ARMV7-STRICT-NEXT: strb lr, [r6, #1] -; CHECK-ARMV7-STRICT-NEXT: strb r12, [r6, #4]! -; CHECK-ARMV7-STRICT-NEXT: strb r5, [r6, #2] +; CHECK-ARMV7-STRICT-NEXT: ldrb r3, [r0, #2] +; CHECK-ARMV7-STRICT-NEXT: ldrb r1, [r0, #3] +; CHECK-ARMV7-STRICT-NEXT: ldrb r2, [r0, #5] +; CHECK-ARMV7-STRICT-NEXT: ldrb r4, [r0, #4] +; CHECK-ARMV7-STRICT-NEXT: ldrb r5, [r0, #7] +; CHECK-ARMV7-STRICT-NEXT: ldrb r0, [r0, #6] +; CHECK-ARMV7-STRICT-NEXT: strb r0, [r6, #6] +; CHECK-ARMV7-STRICT-NEXT: strb r5, [r6, #7] +; CHECK-ARMV7-STRICT-NEXT: strb r4, [r6, #4] +; CHECK-ARMV7-STRICT-NEXT: strb r2, [r6, #5] +; CHECK-ARMV7-STRICT-NEXT: strb r3, [r6, #2] ; CHECK-ARMV7-STRICT-NEXT: strb r1, [r6, #3] +; CHECK-ARMV7-STRICT-NEXT: strb r12, [r6] +; CHECK-ARMV7-STRICT-NEXT: strb lr, [r6, #1] ; CHECK-ARMV7-STRICT-NEXT: pop {r4, r5, r6, pc} ; ; CHECK-ARMV6-LABEL: test_unaligned: @@ -251,23 +248,22 @@ define void @test_unaligned() { ; CHECK-ARMV6-STRICT-NEXT: push {r4, r5, r6, lr} ; CHECK-ARMV6-STRICT-NEXT: ldr r0, .LCPI1_0 ; CHECK-ARMV6-STRICT-NEXT: ldr r6, .LCPI1_1 -; CHECK-ARMV6-STRICT-NEXT: mov r1, r0 -; CHECK-ARMV6-STRICT-NEXT: ldrb lr, [r1, #4]! -; CHECK-ARMV6-STRICT-NEXT: ldrb r3, [r1, #2] -; CHECK-ARMV6-STRICT-NEXT: ldrb r12, [r1, #3] -; CHECK-ARMV6-STRICT-NEXT: ldrb r1, [r0] -; CHECK-ARMV6-STRICT-NEXT: ldrb r2, [r0, #1] -; CHECK-ARMV6-STRICT-NEXT: ldrb r4, [r0, #2] -; CHECK-ARMV6-STRICT-NEXT: ldrb r5, [r0, #3] -; CHECK-ARMV6-STRICT-NEXT: ldrb r0, [r0, #5] -; CHECK-ARMV6-STRICT-NEXT: strb r0, [r6, #5] -; CHECK-ARMV6-STRICT-NEXT: strb r4, [r6, #2] -; CHECK-ARMV6-STRICT-NEXT: strb r5, [r6, #3] -; CHECK-ARMV6-STRICT-NEXT: strb r1, [r6] -; CHECK-ARMV6-STRICT-NEXT: strb r2, [r6, #1] -; CHECK-ARMV6-STRICT-NEXT: strb lr, [r6, #4]! +; CHECK-ARMV6-STRICT-NEXT: ldrb r12, [r0] +; CHECK-ARMV6-STRICT-NEXT: ldrb lr, [r0, #1] +; CHECK-ARMV6-STRICT-NEXT: ldrb r3, [r0, #2] +; CHECK-ARMV6-STRICT-NEXT: ldrb r1, [r0, #3] +; CHECK-ARMV6-STRICT-NEXT: ldrb r2, [r0, #5] +; CHECK-ARMV6-STRICT-NEXT: ldrb r4, [r0, #4] +; CHECK-ARMV6-STRICT-NEXT: ldrb r5, [r0, #7] +; CHECK-ARMV6-STRICT-NEXT: ldrb r0, [r0, #6] +; CHECK-ARMV6-STRICT-NEXT: strb r0, [r6, #6] +; CHECK-ARMV6-STRICT-NEXT: strb r5, [r6, #7] +; CHECK-ARMV6-STRICT-NEXT: strb r4, [r6, #4] +; CHECK-ARMV6-STRICT-NEXT: strb r2, [r6, #5] ; CHECK-ARMV6-STRICT-NEXT: strb r3, [r6, #2] -; CHECK-ARMV6-STRICT-NEXT: strb r12, [r6, #3] +; CHECK-ARMV6-STRICT-NEXT: strb r1, [r6, #3] +; CHECK-ARMV6-STRICT-NEXT: strb r12, [r6] +; CHECK-ARMV6-STRICT-NEXT: strb lr, [r6, #1] ; CHECK-ARMV6-STRICT-NEXT: pop {r4, r5, r6, pc} ; CHECK-ARMV6-STRICT-NEXT: .p2align 2 ; CHECK-ARMV6-STRICT-NEXT: @ %bb.1: diff --git a/llvm/test/CodeGen/ARM/intrinsics-crypto.ll b/llvm/test/CodeGen/ARM/intrinsics-crypto.ll index bb54f6b81b483..753d62daab96c 100644 --- a/llvm/test/CodeGen/ARM/intrinsics-crypto.ll +++ b/llvm/test/CodeGen/ARM/intrinsics-crypto.ll @@ -1,45 +1,60 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s define arm_aapcs_vfpcc <16 x i8> @test_aesde(ptr %a, ptr %b) { +; CHECK-LABEL: test_aesde: +; CHECK: @ %bb.0: +; CHECK-NEXT: vld1.64 {d16, d17}, [r1] +; CHECK-NEXT: vld1.64 {d18, d19}, [r0] +; CHECK-NEXT: aesd.8 q9, q8 +; CHECK-NEXT: aese.8 q9, q8 +; CHECK-NEXT: aesimc.8 q8, q9 +; CHECK-NEXT: aesmc.8 q0, q8 +; CHECK-NEXT: bx lr %tmp = load <16 x i8>, ptr %a %tmp2 = load <16 x i8>, ptr %b %tmp3 = call <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %tmp, <16 x i8> %tmp2) - ; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}} %tmp4 = call <16 x i8> @llvm.arm.neon.aese(<16 x i8> %tmp3, <16 x i8> %tmp2) - ; CHECK: aese.8 q{{[0-9]+}}, q{{[0-9]+}} %tmp5 = call <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %tmp4) - ; CHECK: aesimc.8 q{{[0-9]+}}, q{{[0-9]+}} %tmp6 = call <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %tmp5) - ; CHECK: aesmc.8 q{{[0-9]+}}, q{{[0-9]+}} ret <16 x i8> %tmp6 } define arm_aapcs_vfpcc <4 x i32> @test_sha(ptr %a, ptr %b, ptr %c) { +; CHECK-LABEL: test_sha: +; CHECK: @ %bb.0: +; CHECK-NEXT: ldr r0, [r0] +; CHECK-NEXT: vld1.64 {d0, d1}, [r1] +; CHECK-NEXT: vmov s4, r0 +; CHECK-NEXT: vld1.64 {d18, d19}, [r2] +; CHECK-NEXT: sha1h.32 q2, q1 +; CHECK-NEXT: vmov r0, s8 +; CHECK-NEXT: vmov.32 d16[0], r0 +; CHECK-NEXT: sha1c.32 q0, q1, q8 +; CHECK-NEXT: sha1m.32 q0, q1, q8 +; CHECK-NEXT: sha1p.32 q0, q1, q8 +; CHECK-NEXT: sha1su0.32 q0, q9, q8 +; CHECK-NEXT: sha1su1.32 q0, q8 +; CHECK-NEXT: sha256h.32 q0, q9, q8 +; CHECK-NEXT: sha256h2.32 q0, q9, q8 +; CHECK-NEXT: sha256su1.32 q0, q9, q8 +; CHECK-NEXT: sha256su0.32 q0, q9 +; CHECK-NEXT: bx lr %tmp = load <4 x i32>, ptr %a %tmp2 = load <4 x i32>, ptr %b %tmp3 = load <4 x i32>, ptr %c %scalar = extractelement <4 x i32> %tmp, i32 0 %resscalar = call i32 @llvm.arm.neon.sha1h(i32 %scalar) %res1 = insertelement <4 x i32> undef, i32 %resscalar, i32 0 - ; CHECK: sha1h.32 q{{[0-9]+}}, q{{[0-9]+}} %res2 = call <4 x i32> @llvm.arm.neon.sha1c(<4 x i32> %tmp2, i32 %scalar, <4 x i32> %res1) - ; CHECK: sha1c.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} %res3 = call <4 x i32> @llvm.arm.neon.sha1m(<4 x i32> %res2, i32 %scalar, <4 x i32> %res1) - ; CHECK: sha1m.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} %res4 = call <4 x i32> @llvm.arm.neon.sha1p(<4 x i32> %res3, i32 %scalar, <4 x i32> %res1) - ; CHECK: sha1p.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} %res5 = call <4 x i32> @llvm.arm.neon.sha1su0(<4 x i32> %res4, <4 x i32> %tmp3, <4 x i32> %res1) - ; CHECK: sha1su0.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} %res6 = call <4 x i32> @llvm.arm.neon.sha1su1(<4 x i32> %res5, <4 x i32> %res1) - ; CHECK: sha1su1.32 q{{[0-9]+}}, q{{[0-9]+}} %res7 = call <4 x i32> @llvm.arm.neon.sha256h(<4 x i32> %res6, <4 x i32> %tmp3, <4 x i32> %res1) - ; CHECK: sha256h.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} %res8 = call <4 x i32> @llvm.arm.neon.sha256h2(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1) - ; CHECK: sha256h2.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} %res9 = call <4 x i32> @llvm.arm.neon.sha256su1(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1) - ; CHECK: sha256su1.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} %res10 = call <4 x i32> @llvm.arm.neon.sha256su0(<4 x i32> %res9, <4 x i32> %tmp3) - ; CHECK: sha256su0.32 q{{[0-9]+}}, q{{[0-9]+}} ret <4 x i32> %res10 } diff --git a/llvm/test/CodeGen/ARM/select.ll b/llvm/test/CodeGen/ARM/select.ll index 48d6ee925d939..3f186f69c5aa3 100644 --- a/llvm/test/CodeGen/ARM/select.ll +++ b/llvm/test/CodeGen/ARM/select.ll @@ -440,17 +440,15 @@ define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp { define i1 @test_overflow_recombine(i32 %in1, i32 %in2) { ; CHECK-LABEL: test_overflow_recombine: ; CHECK: @ %bb.0: -; CHECK-NEXT: mul r2, r0, r1 -; CHECK-NEXT: smmul r0, r0, r1 -; CHECK-NEXT: subs r0, r0, r2, asr #31 +; CHECK-NEXT: smull r0, r1, r0, r1 +; CHECK-NEXT: subs r0, r1, r0, asr #31 ; CHECK-NEXT: movwne r0, #1 ; CHECK-NEXT: bx lr ; ; CHECK-NEON-LABEL: test_overflow_recombine: ; CHECK-NEON: @ %bb.0: -; CHECK-NEON-NEXT: mul r2, r0, r1 -; CHECK-NEON-NEXT: smmul r0, r0, r1 -; CHECK-NEON-NEXT: subs.w r0, r0, r2, asr #31 +; CHECK-NEON-NEXT: smull r0, r1, r0, r1 +; CHECK-NEON-NEXT: subs.w r0, r1, r0, asr #31 ; CHECK-NEON-NEXT: it ne ; CHECK-NEON-NEXT: movne r0, #1 ; CHECK-NEON-NEXT: bx lr diff --git a/llvm/test/CodeGen/ARM/softfp-constant-comparison.ll b/llvm/test/CodeGen/ARM/softfp-constant-comparison.ll index 2aa7611347a07..24e0a7e60e5fd 100644 --- a/llvm/test/CodeGen/ARM/softfp-constant-comparison.ll +++ b/llvm/test/CodeGen/ARM/softfp-constant-comparison.ll @@ -32,4 +32,4 @@ land.end: ; preds = %land.rhs, %entry ret void } -attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m4" "target-features"="+armv7e-m,+dsp,+fp16,+hwdiv,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp,-aes,-crc,-crypto,-dotprod,-fp16fml,-fullfp16,-hwdiv-arm,-lob,-mve,-mve.fp,-ras,-sb,-sha2" "use-soft-float"="false" } +attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m4" "target-features"="+armv7e-m,+dsp,+fp16,+hwdiv,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp,-aes,-crc,-crypto,-dotprod,-fp16fml,-fullfp16,-hwdiv-arm,-lob,-mve,-mve.fp,-ras,-sb,-sha2" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/ARM/unaligned_load_store_aeabi.ll b/llvm/test/CodeGen/ARM/unaligned_load_store_aeabi.ll new file mode 100644 index 0000000000000..5e395c49cd3b2 --- /dev/null +++ b/llvm/test/CodeGen/ARM/unaligned_load_store_aeabi.ll @@ -0,0 +1,728 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv6m-eabi -mattr=+strict-align %s -o - | FileCheck %s -check-prefix=CHECK-V6M-MINSIZE +; RUN: llc -mtriple=thumbv6m-eabi -mattr=+strict-align %s -o - | FileCheck %s -check-prefix=CHECK-V6M-OPTSIZE +; RUN: llc -mtriple=thumbv7m-eabi -mattr=+strict-align %s -o - | FileCheck %s -check-prefix=CHECK-V7M-MINSIZE +; RUN: llc -mtriple=thumbv7m-eabi -mattr=+strict-align %s -o - | FileCheck %s -check-prefix=CHECK-V7M-OPTSIZE +; RUN: llc -mtriple=thumbv7m-eabi -mattr=-strict-align %s -o - | FileCheck %s -check-prefix=CHECK-ALIGNED-MINSIZE +; RUN: llc -mtriple=thumbv7m-eabi -mattr=-strict-align %s -o - | FileCheck %s -check-prefix=CHECK-ALIGNED-OPTSIZE + +define void @loadstore4_align1_minsize(i32* %a, i32* %b) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: loadstore4_align1_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: mov r4, r1 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V6M-MINSIZE-NEXT: mov r1, r4 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uwrite4 +; CHECK-V6M-MINSIZE-NEXT: pop {r4, pc} +; +; CHECK-V7M-MINSIZE-LABEL: loadstore4_align1_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: mov r4, r1 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V7M-MINSIZE-NEXT: mov r1, r4 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uwrite4 +; CHECK-V7M-MINSIZE-NEXT: pop {r4, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: loadstore4_align1_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: str r0, [r1] +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 1 + store i32 %tmp, i32* %b, align 1 + ret void +} + +define void @loadstore4_align1_optsize(i32* %a, i32* %b) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: loadstore4_align1_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE: .save {r4, lr} +; CHECK-V6M-OPTSIZE: push {r4, lr} +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uwrite4 +; CHECK-V6M-OPTSIZE: pop {r4, pc} +; +; CHECK-V7M-OPTSIZE-LABEL: loadstore4_align1_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uwrite4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-OPTSIZE-LABEL: loadstore4_align1_optsize: +; CHECK-ALIGNED-OPTSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-OPTSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-OPTSIZE-NEXT: str r0, [r1] +; CHECK-ALIGNED-OPTSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 1 + store i32 %tmp, i32* %b, align 1 + ret void +} + +define i32 @load4_align1_minsize(i32* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load4_align1_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load4_align1_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: load4_align1_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 1 + ret i32 %tmp +} + +define i32 @load4_align1_optsize(i32* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load4_align1_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load4_align1_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-OPTSIZE-LABEL: load4_align1_optsize: +; CHECK-ALIGNED-OPTSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-OPTSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-OPTSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 1 + ret i32 %tmp +} + +define i64 @load4_align1_zext_minsize(i32* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load4_align1_zext_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V6M-MINSIZE-NEXT: movs r1, #0 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load4_align1_zext_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V7M-MINSIZE-NEXT: movs r1, #0 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: load4_align1_zext_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: movs r1, #0 +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 1 + %ext = zext i32 %tmp to i64 + ret i64 %ext +} + +define i64 @load4_align1_zext_optsize(i32* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load4_align1_zext_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load4_align1_zext_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-OPTSIZE-LABEL: load4_align1_zext_optsize: +; CHECK-ALIGNED-OPTSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-OPTSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-OPTSIZE-NEXT: movs r1, #0 +; CHECK-ALIGNED-OPTSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 1 + %ext = zext i32 %tmp to i64 + ret i64 %ext +} + +define i64 @load4_align1_sext_minsize(i32* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load4_align1_sext_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V6M-MINSIZE-NEXT: asrs r1, r0, #31 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load4_align1_sext_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V7M-MINSIZE-NEXT: asrs r1, r0, #31 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: load4_align1_sext_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: asrs r1, r0, #31 +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 1 + %ext = sext i32 %tmp to i64 + ret i64 %ext +} + +define i64 @load4_align1_sext_optsize(i32* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load4_align1_sext_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load4_align1_sext_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-OPTSIZE-LABEL: load4_align1_sext_optsize: +; CHECK-ALIGNED-OPTSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-OPTSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-OPTSIZE-NEXT: asrs r1, r0, #31 +; CHECK-ALIGNED-OPTSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 1 + %ext = sext i32 %tmp to i64 + ret i64 %ext +} + +define void @store4_align1_minsize(i32* %a, i32 %b) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: store4_align1_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: mov r2, r0 +; CHECK-V6M-MINSIZE-NEXT: mov r0, r1 +; CHECK-V6M-MINSIZE-NEXT: mov r1, r2 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uwrite4 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: store4_align1_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: mov r2, r0 +; CHECK-V7M-MINSIZE-NEXT: mov r0, r1 +; CHECK-V7M-MINSIZE-NEXT: mov r1, r2 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uwrite4 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: store4_align1_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: str r1, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + store i32 %b, i32* %a, align 1 + ret void +} + +define void @store4_align1_optsize(i32* %a, i32 %b) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: store4_align1_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uwrite4 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: store4_align1_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uwrite4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-OPTSIZE-LABEL: store4_align1_optsize: +; CHECK-ALIGNED-OPTSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-OPTSIZE-NEXT: str r1, [r0] +; CHECK-ALIGNED-OPTSIZE-NEXT: bx lr +entry: + store i32 %b, i32* %a, align 1 + ret void +} + +define i32 @load4_align2_minsize(i32* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load4_align2_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load4_align2_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: load4_align2_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 2 + ret i32 %tmp +} + +define i32 @load4_align2_optsize(i32* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load4_align2_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load4_align2_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-OPTSIZE-LABEL: load4_align2_optsize: +; CHECK-ALIGNED-OPTSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-OPTSIZE-NEXT: ldr r0, [r0] +; CHECK-ALIGNED-OPTSIZE-NEXT: bx lr +entry: + %tmp = load i32, i32* %a, align 2 + ret i32 %tmp +} + +define i64 @load6_align1_zext_minsize(i48* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load6_align1_zext_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: ldrb r1, [r0, #4] +; CHECK-V6M-MINSIZE-NEXT: ldrb r2, [r0, #5] +; CHECK-V6M-MINSIZE-NEXT: lsls r2, r2, #8 +; CHECK-V6M-MINSIZE-NEXT: adds r4, r2, r1 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V6M-MINSIZE-NEXT: mov r1, r4 +; CHECK-V6M-MINSIZE-NEXT: pop {r4, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load6_align1_zext_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: mov r4, r0 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V7M-MINSIZE-NEXT: ldrb r2, [r4, #5] +; CHECK-V7M-MINSIZE-NEXT: ldrb r1, [r4, #4] +; CHECK-V7M-MINSIZE-NEXT: orr.w r1, r1, r2, lsl #8 +; CHECK-V7M-MINSIZE-NEXT: pop {r4, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: load6_align1_zext_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: ldr r2, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: ldrh r1, [r0, #4] +; CHECK-ALIGNED-MINSIZE-NEXT: mov r0, r2 +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + %tmp = load i48, i48* %a, align 1 + %ext = zext i48 %tmp to i64 + ret i64 %ext +} + +define i64 @load6_align1_zext_optsize(i48* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load6_align1_zext_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load6_align1_zext_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-MINSIZE-LABEL: load6_align1_zext_optsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: ldr r2, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: ldrh r1, [r0, #4] +; CHECK-ALIGNED-MINSIZE-NEXT: mov r0, r2 +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + %tmp = load i48, i48* %a, align 1 + %ext = zext i48 %tmp to i64 + ret i64 %ext +} + +define i64 @load6_align1_sext_minsize(i48* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load6_align1_sext_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: movs r1, #5 +; CHECK-V6M-MINSIZE-NEXT: ldrsb r1, [r0, r1] +; CHECK-V6M-MINSIZE-NEXT: lsls r1, r1, #8 +; CHECK-V6M-MINSIZE-NEXT: ldrb r2, [r0, #4] +; CHECK-V6M-MINSIZE-NEXT: adds r4, r1, r2 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V6M-MINSIZE-NEXT: mov r1, r4 +; CHECK-V6M-MINSIZE-NEXT: pop {r4, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load6_align1_sext_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: ldrsb.w r1, [r0, #5] +; CHECK-V7M-MINSIZE-NEXT: ldrb r2, [r0, #4] +; CHECK-V7M-MINSIZE-NEXT: orr.w r4, r2, r1, lsl #8 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread4 +; CHECK-V7M-MINSIZE-NEXT: mov r1, r4 +; CHECK-V7M-MINSIZE-NEXT: pop {r4, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: load6_align1_sext_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: ldr r2, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: ldrsh.w r1, [r0, #4] +; CHECK-ALIGNED-MINSIZE-NEXT: mov r0, r2 +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + %tmp = load i48, i48* %a, align 1 + %ext = sext i48 %tmp to i64 + ret i64 %ext +} + +define i64 @load6_align1_sext_optsize(i48* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load6_align1_sext_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load6_align1_sext_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-OPTSIZE-LABEL: load6_align1_sext_optsize: +; CHECK-ALIGNED-OPTSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-OPTSIZE-NEXT: ldr r2, [r0] +; CHECK-ALIGNED-OPTSIZE-NEXT: ldrsh.w r1, [r0, #4] +; CHECK-ALIGNED-OPTSIZE-NEXT: mov r0, r2 +; CHECK-ALIGNED-OPTSIZE-NEXT: bx lr +entry: + %tmp = load i48, i48* %a, align 1 + %ext = sext i48 %tmp to i64 + ret i64 %ext +} + +define void @store6_align1_minsize(i48* %a, i48 %b) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: store6_align1_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: mov r1, r0 +; CHECK-V6M-MINSIZE-NEXT: strb r3, [r0, #4] +; CHECK-V6M-MINSIZE-NEXT: lsrs r0, r3, #8 +; CHECK-V6M-MINSIZE-NEXT: strb r0, [r1, #5] +; CHECK-V6M-MINSIZE-NEXT: mov r0, r2 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uwrite4 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: store6_align1_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: mov r1, r0 +; CHECK-V7M-MINSIZE-NEXT: strb r3, [r0, #4] +; CHECK-V7M-MINSIZE-NEXT: lsrs r0, r3, #8 +; CHECK-V7M-MINSIZE-NEXT: strb r0, [r1, #5] +; CHECK-V7M-MINSIZE-NEXT: mov r0, r2 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uwrite4 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-ALIGNED-MINSIZE-LABEL: store6_align1_minsize: +; CHECK-ALIGNED-MINSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-MINSIZE-NEXT: strh r3, [r0, #4] +; CHECK-ALIGNED-MINSIZE-NEXT: str r2, [r0] +; CHECK-ALIGNED-MINSIZE-NEXT: bx lr +entry: + store i48 %b, i48* %a, align 1 + ret void +} + +define void @store6_align1_optsize(i48* %a, i48 %b) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: store6_align1_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uwrite4 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: store6_align1_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uwrite4 +; CHECK-V7M-OPTSIZE: bx lr +; +; CHECK-ALIGNED-OPTSIZE-LABEL: store6_align1_optsize: +; CHECK-ALIGNED-OPTSIZE: @ %bb.0: @ %entry +; CHECK-ALIGNED-OPTSIZE-NEXT: strh r3, [r0, #4] +; CHECK-ALIGNED-OPTSIZE-NEXT: str r2, [r0] +; CHECK-ALIGNED-OPTSIZE-NEXT: bx lr +entry: + store i48 %b, i48* %a, align 1 + ret void +} + +define void @loadstore8_align4_minsize(double* %a, double* %b) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: loadstore8_align4_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: mov r4, r1 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread8 +; CHECK-V6M-MINSIZE-NEXT: mov r2, r4 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uwrite8 +; CHECK-V6M-MINSIZE-NEXT: pop {r4, pc} +; +; CHECK-V7M-MINSIZE-LABEL: loadstore8_align4_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: mov r4, r1 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread8 +; CHECK-V7M-MINSIZE-NEXT: mov r2, r4 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uwrite8 +; CHECK-V7M-MINSIZE-NEXT: pop {r4, pc} +; +entry: + %tmp = load double, double* %a, align 1 + store double %tmp, double* %b, align 1 + ret void +} + +define void @loadstore8_align4_optsize(double* %a, double* %b) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: loadstore8_align4_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NEXT: .save {r4, r5, r6, r7, lr} +; CHECK-V6M-OPTSIZE-NEXT: push {r4, r5, r6, r7, lr} +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread8 +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uwrite8 +; CHECK-V6M-OPTSIZE: pop {r4, r5, r6, r7, pc} +; +; CHECK-V7M-OPTSIZE-LABEL: loadstore8_align4_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NEXT: .save {r4, r5, r6, lr} +; CHECK-V7M-OPTSIZE-NEXT: push {r4, r5, r6, lr} +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread8 +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uwrite8 +; CHECK-V7M-OPTSIZE: pop {r4, r5, r6, pc} +entry: + %tmp = load double, double* %a, align 1 + store double %tmp, double* %b, align 1 + ret void +} + +define double @load8_align1_minsize(double* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load8_align1_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread8 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load8_align1_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread8 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +; +entry: + %tmp = load double, double* %a, align 1 + ret double %tmp +} + +define double @load8_align1_optsize(double* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load8_align1_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread8 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load8_align1_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread8 +; CHECK-V7M-OPTSIZE: bx lr +; +entry: + %tmp = load double, double* %a, align 1 + ret double %tmp +} + +define void @store8_align1_minsize(double* %a, double %b) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: store8_align1_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: mov r1, r3 +; CHECK-V6M-MINSIZE-NEXT: mov r3, r0 +; CHECK-V6M-MINSIZE-NEXT: mov r0, r2 +; CHECK-V6M-MINSIZE-NEXT: mov r2, r3 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uwrite8 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: store8_align1_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: mov r1, r3 +; CHECK-V7M-MINSIZE-NEXT: mov r3, r0 +; CHECK-V7M-MINSIZE-NEXT: mov r0, r2 +; CHECK-V7M-MINSIZE-NEXT: mov r2, r3 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uwrite8 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +entry: + store double %b, double* %a, align 1 + ret void +} + +define void @store8_align1_optsize(double* %a, double %b) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: store8_align1_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uwrite8 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: store8_align1_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uwrite8 +; CHECK-V7M-OPTSIZE: bx lr +entry: + store double %b, double* %a, align 1 + ret void +} + +define double @load8_align2_minsize(double* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load8_align2_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread8 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load8_align2_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread8 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +entry: + %tmp = load double, double* %a, align 2 + ret double %tmp +} + +define double @load8_align2_optsize(double* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load8_align2_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread8 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load8_align2_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uread8 +; CHECK-V7M-OPTSIZE: bx lr +entry: + %tmp = load double, double* %a, align 2 + ret double %tmp +} + +define i64 @load12_align1_trunc_minsize(i96* %a) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: load12_align1_trunc_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uread8 +; CHECK-V6M-MINSIZE-NEXT: pop {r7, pc} +; +; CHECK-V7M-MINSIZE-LABEL: load12_align1_trunc_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r7, lr} +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uread8 +; CHECK-V7M-MINSIZE-NEXT: pop {r7, pc} +entry: + %tmp = load i96, i96* %a, align 1 + %ext = trunc i96 %tmp to i64 + ret i64 %ext +} + +define i64 @load12_align1_trunc_optsize(i96* %a) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: load12_align1_trunc_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uread8 +; CHECK-V6M-OPTSIZE: bx lr +; +; CHECK-V7M-OPTSIZE-LABEL: load12_align1_trunc_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bx __aeabi_uread8 +; CHECK-V7M-OPTSIZE: bx lr +entry: + %tmp = load i96, i96* %a, align 1 + %ext = trunc i96 %tmp to i64 + ret i64 %ext +} + +define void @store12_align4_trunc_minsize(i96* %a, i96 %b) nounwind minsize { +; CHECK-V6M-MINSIZE-LABEL: store12_align4_trunc_minsize: +; CHECK-V6M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V6M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V6M-MINSIZE-NEXT: mov r1, r3 +; CHECK-V6M-MINSIZE-NEXT: mov r4, r0 +; CHECK-V6M-MINSIZE-NEXT: mov r0, r2 +; CHECK-V6M-MINSIZE-NEXT: mov r2, r4 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uwrite8 +; CHECK-V6M-MINSIZE-NEXT: adds r4, #8 +; CHECK-V6M-MINSIZE-NEXT: ldr r0, [sp, #8] +; CHECK-V6M-MINSIZE-NEXT: mov r1, r4 +; CHECK-V6M-MINSIZE-NEXT: bl __aeabi_uwrite4 +; CHECK-V6M-MINSIZE-NEXT: pop {r4, pc} +; +; CHECK-V7M-MINSIZE-LABEL: store12_align4_trunc_minsize: +; CHECK-V7M-MINSIZE: @ %bb.0: @ %entry +; CHECK-V7M-MINSIZE-NEXT: .save {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: push {r4, lr} +; CHECK-V7M-MINSIZE-NEXT: mov r4, r0 +; CHECK-V7M-MINSIZE-NEXT: mov r0, r2 +; CHECK-V7M-MINSIZE-NEXT: mov r1, r3 +; CHECK-V7M-MINSIZE-NEXT: mov r2, r4 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uwrite8 +; CHECK-V7M-MINSIZE-NEXT: ldr r0, [sp, #8] +; CHECK-V7M-MINSIZE-NEXT: add.w r1, r4, #8 +; CHECK-V7M-MINSIZE-NEXT: bl __aeabi_uwrite4 +; CHECK-V7M-MINSIZE-NEXT: pop {r4, pc} +entry: + store i96 %b, i96* %a, align 1 + ret void +} + +define void @store12_align4_trunc_optsize(i96* %a, i96 %b) nounwind optsize { +; CHECK-V6M-OPTSIZE-LABEL: store12_align4_trunc_optsize: +; CHECK-V6M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V6M-OPTSIZE-NEXT: .save {r4, lr} +; CHECK-V6M-OPTSIZE-NEXT: push {r4, lr} +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uwrite8 +; CHECK-V6M-OPTSIZE-NOT: bl __aeabi_uwrite4 +; CHECK-V6M-OPTSIZE: pop {r4, pc} +; +; CHECK-V7M-OPTSIZE-LABEL: store12_align4_trunc_optsize: +; CHECK-V7M-OPTSIZE: @ %bb.0: @ %entry +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uwrite8 +; CHECK-V7M-OPTSIZE-NOT: bl __aeabi_uwrite4 +; CHECK-V7M-OPTSIZE: bx lr +entry: + store i96 %b, i96* %a, align 1 + ret void +} diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll index c1eae0429baad..12dca7a78cc27 100644 --- a/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll @@ -111,3 +111,17 @@ entry: %0 = call i32 @llvm.dx.wave.prefix.bit.count(i1 %expr) ret void } + +define noundef i32 @wave_prefix_sum(i32 noundef %x) { +entry: + ; CHECK: Function wave_prefix_sum : [[WAVE_FLAG]] + %ret = call i32 @llvm.dx.wave.prefix.sum.i32(i32 %x) + ret i32 %ret +} + +define noundef i32 @wave_prefix_usum(i32 noundef %x) { +entry: + ; CHECK: Function wave_prefix_usum : [[WAVE_FLAG]] + %ret = call i32 @llvm.dx.wave.prefix.usum.i32(i32 %x) + ret i32 %ret +} diff --git a/llvm/test/CodeGen/DirectX/WavePrefixSum.ll b/llvm/test/CodeGen/DirectX/WavePrefixSum.ll new file mode 100644 index 0000000000000..ed8c2b2b85465 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/WavePrefixSum.ll @@ -0,0 +1,143 @@ +; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library < %s | FileCheck %s + +; Test that for scalar values, WavePrefixSum maps down to the DirectX op + +define noundef half @wave_prefix_sum_half(half noundef %expr) { +entry: +; CHECK: call half @dx.op.wavePrefixOp.f16(i32 121, half %expr, i8 0, i8 0) + %ret = call half @llvm.dx.wave.prefix.sum.f16(half %expr) + ret half %ret +} + +define noundef float @wave_prefix_sum_float(float noundef %expr) { +entry: +; CHECK: call float @dx.op.wavePrefixOp.f32(i32 121, float %expr, i8 0, i8 0) + %ret = call float @llvm.dx.wave.prefix.sum.f32(float %expr) + ret float %ret +} + +define noundef double @wave_prefix_sum_double(double noundef %expr) { +entry: +; CHECK: call double @dx.op.wavePrefixOp.f64(i32 121, double %expr, i8 0, i8 0) + %ret = call double @llvm.dx.wave.prefix.sum.f64(double %expr) + ret double %ret +} + +define noundef i16 @wave_prefix_sum_i16(i16 noundef %expr) { +entry: +; CHECK: call i16 @dx.op.wavePrefixOp.i16(i32 121, i16 %expr, i8 0, i8 0) + %ret = call i16 @llvm.dx.wave.prefix.sum.i16(i16 %expr) + ret i16 %ret +} + +define noundef i32 @wave_prefix_sum_i32(i32 noundef %expr) { +entry: +; CHECK: call i32 @dx.op.wavePrefixOp.i32(i32 121, i32 %expr, i8 0, i8 0) + %ret = call i32 @llvm.dx.wave.prefix.sum.i32(i32 %expr) + ret i32 %ret +} + +define noundef i64 @wave_prefix_sum_i64(i64 noundef %expr) { +entry: +; CHECK: call i64 @dx.op.wavePrefixOp.i64(i32 121, i64 %expr, i8 0, i8 0) + %ret = call i64 @llvm.dx.wave.prefix.sum.i64(i64 %expr) + ret i64 %ret +} + +define noundef i16 @wave_prefix_usum_i16(i16 noundef %expr) { +entry: +; CHECK: call i16 @dx.op.wavePrefixOp.i16(i32 121, i16 %expr, i8 0, i8 1) + %ret = call i16 @llvm.dx.wave.prefix.usum.i16(i16 %expr) + ret i16 %ret +} + +define noundef i32 @wave_prefix_usum_i32(i32 noundef %expr) { +entry: +; CHECK: call i32 @dx.op.wavePrefixOp.i32(i32 121, i32 %expr, i8 0, i8 1) + %ret = call i32 @llvm.dx.wave.prefix.usum.i32(i32 %expr) + ret i32 %ret +} + +define noundef i64 @wave_prefix_usum_i64(i64 noundef %expr) { +entry: +; CHECK: call i64 @dx.op.wavePrefixOp.i64(i32 121, i64 %expr, i8 0, i8 1) + %ret = call i64 @llvm.dx.wave.prefix.usum.i64(i64 %expr) + ret i64 %ret +} + +declare half @llvm.dx.wave.prefix.sum.f16(half) +declare float @llvm.dx.wave.prefix.sum.f32(float) +declare double @llvm.dx.wave.prefix.sum.f64(double) + +declare i16 @llvm.dx.wave.prefix.sum.i16(i16) +declare i32 @llvm.dx.wave.prefix.sum.i32(i32) +declare i64 @llvm.dx.wave.prefix.sum.i64(i64) + +declare i16 @llvm.dx.wave.prefix.usum.i16(i16) +declare i32 @llvm.dx.wave.prefix.usum.i32(i32) +declare i64 @llvm.dx.wave.prefix.usum.i64(i64) + +; Test that for vector values, WavePrefixSum scalarizes and maps down to the +; DirectX op + +define noundef <2 x half> @wave_prefix_sum_v2half(<2 x half> noundef %expr) { +entry: +; CHECK: call half @dx.op.wavePrefixOp.f16(i32 121, half %expr.i0, i8 0, i8 0) +; CHECK: call half @dx.op.wavePrefixOp.f16(i32 121, half %expr.i1, i8 0, i8 0) + %ret = call <2 x half> @llvm.dx.wave.prefix.sum.v2f16(<2 x half> %expr) + ret <2 x half> %ret +} + +define noundef <3 x i32> @wave_prefix_sum_v3i32(<3 x i32> noundef %expr) { +entry: +; CHECK: call i32 @dx.op.wavePrefixOp.i32(i32 121, i32 %expr.i0, i8 0, i8 0) +; CHECK: call i32 @dx.op.wavePrefixOp.i32(i32 121, i32 %expr.i1, i8 0, i8 0) +; CHECK: call i32 @dx.op.wavePrefixOp.i32(i32 121, i32 %expr.i2, i8 0, i8 0) + %ret = call <3 x i32> @llvm.dx.wave.prefix.sum.v3i32(<3 x i32> %expr) + ret <3 x i32> %ret +} + +define noundef <4 x double> @wave_prefix_sum_v4f64(<4 x double> noundef %expr) { +entry: +; CHECK: call double @dx.op.wavePrefixOp.f64(i32 121, double %expr.i0, i8 0, i8 0) +; CHECK: call double @dx.op.wavePrefixOp.f64(i32 121, double %expr.i1, i8 0, i8 0) +; CHECK: call double @dx.op.wavePrefixOp.f64(i32 121, double %expr.i2, i8 0, i8 0) +; CHECK: call double @dx.op.wavePrefixOp.f64(i32 121, double %expr.i3, i8 0, i8 0) + %ret = call <4 x double> @llvm.dx.wave.prefix.sum.v464(<4 x double> %expr) + ret <4 x double> %ret +} + +declare <2 x half> @llvm.dx.wave.prefix.sum.v2f16(<2 x half>) +declare <3 x i32> @llvm.dx.wave.prefix.sum.v3i32(<3 x i32>) +declare <4 x double> @llvm.dx.wave.prefix.sum.v4f64(<4 x double>) + +define noundef <2 x i16> @wave_prefix_usum_v2i16(<2 x i16> noundef %expr) { +entry: +; CHECK: call i16 @dx.op.wavePrefixOp.i16(i32 121, i16 %expr.i0, i8 0, i8 1) +; CHECK: call i16 @dx.op.wavePrefixOp.i16(i32 121, i16 %expr.i1, i8 0, i8 1) + %ret = call <2 x i16> @llvm.dx.wave.prefix.usum.v2f16(<2 x i16> %expr) + ret <2 x i16> %ret +} + +define noundef <3 x i32> @wave_prefix_usum_v3i32(<3 x i32> noundef %expr) { +entry: +; CHECK: call i32 @dx.op.wavePrefixOp.i32(i32 121, i32 %expr.i0, i8 0, i8 1) +; CHECK: call i32 @dx.op.wavePrefixOp.i32(i32 121, i32 %expr.i1, i8 0, i8 1) +; CHECK: call i32 @dx.op.wavePrefixOp.i32(i32 121, i32 %expr.i2, i8 0, i8 1) + %ret = call <3 x i32> @llvm.dx.wave.prefix.usum.v3i32(<3 x i32> %expr) + ret <3 x i32> %ret +} + +define noundef <4 x i64> @wave_prefix_usum_v4f64(<4 x i64> noundef %expr) { +entry: +; CHECK: call i64 @dx.op.wavePrefixOp.i64(i32 121, i64 %expr.i0, i8 0, i8 1) +; CHECK: call i64 @dx.op.wavePrefixOp.i64(i32 121, i64 %expr.i1, i8 0, i8 1) +; CHECK: call i64 @dx.op.wavePrefixOp.i64(i32 121, i64 %expr.i2, i8 0, i8 1) +; CHECK: call i64 @dx.op.wavePrefixOp.i64(i32 121, i64 %expr.i3, i8 0, i8 1) + %ret = call <4 x i64> @llvm.dx.wave.prefix.usum.v464(<4 x i64> %expr) + ret <4 x i64> %ret +} + +declare <2 x i16> @llvm.dx.wave.prefix.usum.v2f16(<2 x i16>) +declare <3 x i32> @llvm.dx.wave.prefix.usum.v3i32(<3 x i32>) +declare <4 x i64> @llvm.dx.wave.prefix.usum.v4f64(<4 x i64>) diff --git a/llvm/test/CodeGen/DirectX/scalar-bug-117273.ll b/llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll similarity index 91% rename from llvm/test/CodeGen/DirectX/scalar-bug-117273.ll rename to llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll index 43bbe9249aac0..c77a3043303e5 100644 --- a/llvm/test/CodeGen/DirectX/scalar-bug-117273.ll +++ b/llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -passes='dxil-data-scalarization,dxil-flatten-arrays,function(scalarizer),dxil-op-lower' -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s +; RUN: opt -S -passes='dxil-data-scalarization,dxil-flatten-arrays,function(scalarizer),dxil-op-lower' -mtriple=dxil-pc-shadermodel6.3-library -use-constant-fp-for-fixed-length-splat %s | FileCheck %s @StaticArr = internal constant [8 x <3 x float>] [<3 x float> zeroinitializer, <3 x float> splat (float 5.000000e-01), <3 x float> , <3 x float> , <3 x float> , <3 x float> , <3 x float> , <3 x float> ], align 16 diff --git a/llvm/test/CodeGen/Generic/denormal-fp-math-cl-opt.ll b/llvm/test/CodeGen/Generic/denormal-fp-math-cl-opt.ll index 7e0922c7d0810..026ed5ed53f0e 100644 --- a/llvm/test/CodeGen/Generic/denormal-fp-math-cl-opt.ll +++ b/llvm/test/CodeGen/Generic/denormal-fp-math-cl-opt.ll @@ -3,7 +3,7 @@ ; Check that the command line flag annotates the IR with the ; appropriate attributes. -; CHECK: attributes #0 = { "denormal-fp-math"="dynamic,dynamic" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +; CHECK: attributes #0 = { denormal_fpenv(dynamic, float: preservesign) } define float @foo(float %var) { ret float %var } diff --git a/llvm/test/CodeGen/Hexagon/dag-isel-balancetree-rauw.ll b/llvm/test/CodeGen/Hexagon/dag-isel-balancetree-rauw.ll new file mode 100644 index 0000000000000..48daa6e5d1fd6 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/dag-isel-balancetree-rauw.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; +; Test that the DAG ISel address tree balancing does not crash when nodes +; are replaced (RAUW'd) during balancing. This is a regression test for +; GitHub issue #64371 where use-after-poison occurred in balanceSubTree(). +; +; The specific pattern that triggers the issue involves nested adds used +; in address calculations with null pointers, causing nodes to be replaced +; during the balancing process. + +; CHECK-LABEL: f: +; CHECK: memb +; CHECK: memb +define void @f(i32 %LGV1, ptr %RP) { + %G6 = getelementptr i32, ptr null, i32 %LGV1 + %B1 = add i32 %LGV1, %LGV1 + store i1 false, ptr %G6, align 1 + %B2 = add i32 %LGV1, %B1 + %G1 = getelementptr float, ptr %RP, i32 %B2 + store i1 false, ptr %G1, align 1 + ret void +} diff --git a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll index 8b121c539229d..263dc04f090f1 100644 --- a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll +++ b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll @@ -1,4 +1,4 @@ -;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s +;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck --enable-var-scope %s define dso_local void @store_isnan_f32(ptr %a, ptr %b, ptr %isnan_cmp) local_unnamed_addr { entry: @@ -13,7 +13,7 @@ entry: ret void } -; CHECK: store_isnan_f32 +; CHECK-LABEL:store_isnan_f32 ; CHECK: [[RONE32:r[0-9]+]] = #1 ; CHECK: [[VOP2_F32:v[0-9]+]] = vxor([[VOP2_F32]],[[VOP2_F32]]) ; CHECK: [[VOP1_F32:v[0-9]+]] = vmemu(r0+#0) @@ -45,7 +45,7 @@ entry: ; CHECK: [[VOP3_F16:v[0-9]+]] = vmemu(r1+#0) ; CHECK: [[Q1_F16]] &= vcmp.eq([[VOP3_F16]].h,[[VOP3_F16]].h) ; CHECK: [[VOUT_F16:v[0-9]+]] = vmux([[Q1_F16]],[[VOP2_F16]],[[VONES16]]) -; CHECK: vmemu(r2+#0) = [[VOUT_F32]] +; CHECK: vmemu(r2+#0) = [[VOUT_F16]] define dso_local void @store_isordered_f32(ptr %a, ptr %b, ptr %isordered_cmp) local_unnamed_addr { entry: @@ -60,6 +60,7 @@ entry: ret void } ; CHECK-LABEL: store_isordered_f32 +; CHECK: [[RONE32:r[0-9]+]] = #1 ; CHECK: [[VOP2_ORD_F32:v[0-9]+]] = vxor([[VOP2_ORD_F32]],[[VOP2_ORD_F32]]) ; CHECK: [[VOP1_ORD_F32:v[0-9]+]] = vmemu(r0+#0) ; CHECK: [[VONES_ORD_F32:v[0-9]+]] = vsplat([[RONE32]]) @@ -83,6 +84,7 @@ entry: ret void } ; CHECK-LABEL: store_isordered_f16 +; CHECK: [[RONE16:r[0-9]+]] = #1 ; CHECK: [[VOP2_ORD_F16:v[0-9]+]] = vxor([[VOP2_ORD_F16]],[[VOP2_ORD_F16]]) ; CHECK: [[VOP1_ORD_F16:v[0-9]+]] = vmemu(r0+#0) ; CHECK: [[VONES_ORD_F16:v[0-9]+]].h = vsplat([[RONE16]]) diff --git a/llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll b/llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll index 463e34da7a5c0..34eec1faa951c 100644 --- a/llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll +++ b/llvm/test/CodeGen/Hexagon/isel/mulh-scalar.ll @@ -209,13 +209,13 @@ define <4 x i16> @f6(<4 x i16> %a0, <4 x i16> %a1) #0 { ; CHECK-NEXT: r5:4 = vmpyh(r0,r2):sat ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7:6 = vmpyh(r1,r3):sat +; CHECK-NEXT: r{{[0-9]+}}:{{[0-9]+}} = vmpyh(r1,r3):sat ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r0 = combine(r5.h,r4.h) +; CHECK-NEXT: r0 = combine(r{{[0-9]+}}.h,r{{[0-9]+}}.h) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r1 = combine(r7.h,r6.h) +; CHECK-NEXT: r1 = combine(r{{[0-9]+}}.h,r{{[0-9]+}}.h) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/live-vars/live-outs.ll b/llvm/test/CodeGen/Hexagon/live-vars/live-outs.ll new file mode 100644 index 0000000000000..08b1195928d1f --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/live-vars/live-outs.ll @@ -0,0 +1,77 @@ +; RUN: llc -O3 -verify-machineinstrs < %s -o /dev/null +; REQUIRES: asserts +; +; This is a compile-only regression test (asserts build) for Hexagon. + +define i32 @foo(ptr nocapture readnone %x, i32 %n, ptr nocapture readonly %p, + ptr nocapture readonly %q, ptr %b) { +entry: + %cmp = icmp eq i32 %n, 0 + br i1 %cmp, label %return, label %if.end + +if.end: ; preds = %entry + %div = lshr i32 %n, 3 + %cmp149 = icmp eq i32 %div, 0 + br i1 %cmp149, label %for.end, label %for.body.preheader + +for.body.preheader: ; preds = %if.end + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.inc + %arrayidx.phi = phi ptr [ %arrayidx.inc, %for.inc ], [ %p, %for.body.preheader ] + %arrayidx2.phi = phi ptr [ %arrayidx2.inc, %for.inc ], [ %q, %for.body.preheader ] + %i.050 = phi i32 [ %inc, %for.inc ], [ 0, %for.body.preheader ] + %0 = load i8, ptr %arrayidx.phi, align 1 + %1 = load i8, ptr %arrayidx2.phi, align 1 + %cmp4 = icmp eq i8 %0, %1 + br i1 %cmp4, label %for.inc, label %for.end.loopexit + +for.inc: ; preds = %for.body + %arrayidx2.inc = getelementptr i8, ptr %arrayidx2.phi, i32 1 + %arrayidx.inc = getelementptr i8, ptr %arrayidx.phi, i32 1 + %inc = add nuw nsw i32 %i.050, 1 + %cmp1 = icmp ult i32 %inc, %div + br i1 %cmp1, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body, %for.inc + %i.0.lcssa.ph = phi i32 [ %i.050, %for.body ], [ %inc, %for.inc ] + br label %for.end + +for.end: ; preds = %for.end.loopexit, %if.end + %i.0.lcssa = phi i32 [ 0, %if.end ], [ %i.0.lcssa.ph, %for.end.loopexit ] + %cmp8 = icmp eq i32 %i.0.lcssa, %div + br i1 %cmp8, label %if.end30, label %if.then10 + +if.then10: ; preds = %for.end + %rem = and i32 %n, 7 + %cmp11 = icmp eq i32 %rem, 0 + br i1 %cmp11, label %return, label %if.end14 + +if.end14: ; preds = %if.then10 + %sub = sub nsw i32 8, %rem + %shl = shl i32 1, %sub + %sub16 = add i32 %shl, 255 + %arrayidx18 = getelementptr inbounds i8, ptr %p, i32 %i.0.lcssa + %2 = load i8, ptr %arrayidx18, align 1 + %sub16.not = or i32 %sub16, -256 + %neg = xor i32 %sub16.not, 255 + %arrayidx21 = getelementptr inbounds i8, ptr %q, i32 %i.0.lcssa + %3 = load i8, ptr %arrayidx21, align 1 + %4 = xor i8 %3, %2 + %5 = zext i8 %4 to i32 + %6 = and i32 %5, %neg + %cmp26 = icmp eq i32 %6, 0 + br i1 %cmp26, label %return, label %if.end30 + +if.end30: ; preds = %for.end, %if.end14 + %cmp31 = icmp eq ptr %b, null + br i1 %cmp31, label %return, label %if.then33 + +if.then33: ; preds = %if.end30 + store i8 0, ptr %b, align 1 + br label %return + +return: ; preds = %if.end30, %if.then33, %if.end14, %if.then10, %entry + %retval.0 = phi i32 [ 0, %entry ], [ 1, %if.then10 ], [ 1, %if.end14 ], [ 0, %if.then33 ], [ 0, %if.end30 ] + ret i32 %retval.0 +} diff --git a/llvm/test/CodeGen/Hexagon/nbench1.ll b/llvm/test/CodeGen/Hexagon/nbench1.ll index 25a83db5717e3..04335ce4fa1c1 100644 --- a/llvm/test/CodeGen/Hexagon/nbench1.ll +++ b/llvm/test/CodeGen/Hexagon/nbench1.ll @@ -3,9 +3,9 @@ ; if instruction being considered for addition to packet has higher latency, ; end existing packet and start a new one. -; CHECK: .LBB0_4: ; CHECK: p{{[0-3]+}} = cmp.gtu(r{{[0-9]+}},r{{[0-9]+}}) -; CHECK-NEXT: } +; CHECK: if (p{{[0-3]+}}.new) jumpr:nt r31 +; CHECK: } @array = external dso_local local_unnamed_addr global ptr, align 4 diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll b/llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll index e3f36988f9387..a6c3b599586f6 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump-kill.ll @@ -2,7 +2,8 @@ ; ; Check that this testcase compiles successfully and that a new-value jump ; has been created. -; CHECK: if (cmp.gtu(r{{[0-9]+}}.new,r{{[0-9]+}})) jump +; CHECK: p{{[0-3]+}} = cmp.gtu(r{{[0-9]+}},r{{[0-9]+}}) +; CHECK-SAME: if (p{{[0-3]+}}.new) jump target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll b/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll new file mode 100644 index 0000000000000..6dcaebc0b83f1 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll @@ -0,0 +1,24 @@ +; REQUIRES: asserts +; RUN: llc -march=hexagon -verify-machineinstrs -o - < %s 2>&1 | FileCheck %s + +; This is a crash / fatal-error regression test: +; llc used to hit: +; LLVM ERROR: invalid node: operand #1 must have type i32, but has type i16 +; during DAG combine / ISel: +; t61: v4i16 = HexagonISD::VASR t56, Constant:i16<1> +; t56: v4i16 = mulhs ... +; +; The test ensures llc does NOT emit "LLVM ERROR" and produces assembly for the function. + +; CHECK-NOT: LLVM ERROR: +; CHECK-NOT: invalid node: +; CHECK-LABEL: sq77777777: +; CHECK: r{{[0-9]+}}:{{[0-9]+}} = vasrh(r{{[0-9]+}}:{{[0-9]+}},#1) + +target triple = "hexagon-unknown-linux-musl" + +define <8 x i16> @sq77777777(<8 x i16> %0) { +entry: + %div = sdiv <8 x i16> %0, splat (i16 7) + ret <8 x i16> %div +} diff --git a/llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep6.mir b/llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep6.mir index 4281d15377141..8fe3b3d83aa94 100644 --- a/llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep6.mir +++ b/llvm/test/CodeGen/Hexagon/swp-loop-carried-order-dep6.mir @@ -19,23 +19,33 @@ # } # ``` # -# FIXME: Currently the following dependencies are missed. -# Loop carried edges from SU(16) -# Order -# SU(6) -# SU(8) -# SU(10) -# SU(11) -# Loop carried edges from SU(17) -# Order -# SU(10) -# SU(11) -# Loop carried edges from SU(19) -# Order -# SU(10) -# SU(11) +# SU(6): Load +# SU(8): Store +# SU(10): Store +# SU(11): Barrier +# SU(16): Barrier +# SU(17): Load +# SU(19): Load +# +# As the order between load/store and barrier must be preserved, the following +# loop-carried dependnecies need to be added: +# - SU(16) -> SU(6), SU(8), SU(10) +# - SU(17), SU(19) -> SU(11) +# - SU(16) -> SU(11) (barrier to barrier) # CHECK: ===== Loop Carried Edges Begin ===== +# CHECK-NEXT: Loop carried edges from SU(16) +# CHECK-NEXT: Order +# CHECK-NEXT: SU(6) +# CHECK-NEXT: SU(8) +# CHECK-NEXT: SU(10) +# CHECK-NEXT: SU(11) +# CHECK-NEXT: Loop carried edges from SU(17) +# CHECK-NEXT: Order +# CHECK-NEXT: SU(11) +# CHECK-NEXT: Loop carried edges from SU(19) +# CHECK-NEXT: Order +# CHECK-NEXT: SU(11) # CHECK-NEXT: ===== Loop Carried Edges End ===== --- | diff --git a/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll b/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll index a0aeb80a5fa93..cfb459c6d2055 100644 --- a/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll +++ b/llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll @@ -3,7 +3,7 @@ ; From coremark. Test that we pipeline the matrix multiplication bitextract ; function. The pipelined code should have two packets. -; CHECK: loop0(.LBB0_[[LOOP:.]], +; CHECK: loop{{[01]}}(.LBB0_[[LOOP:[0-9]+]],r{{[0-9]+}}) ; CHECK: .LBB0_[[LOOP]]: ; CHECK: [[REG0:(r[0-9]+)]] = mpyi([[REG1:(r[0-9]+)]],[[REG2:(r[0-9]+)]]) ; CHECK: += mpyi @@ -11,7 +11,7 @@ ; CHECK: = extractu([[REG0:(r[0-9]+)]], ; CHECK: = extractu([[REG0]], ; CHECK: [[REG2:(r[0-9]+)]] = memh -; CHECK: endloop0 +; CHECK: endloop{{[01]}} %union_h2_sem_t = type { i32 } diff --git a/llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll b/llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll new file mode 100644 index 0000000000000..cd98ba7e4083c --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lasx/vxi1-masks.ll @@ -0,0 +1,1026 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64 + +define void @xor_zext_masks_v4i64(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: xor_zext_masks_v4i64: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 2 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; LA32-NEXT: vldi $vr0, -1777 +; LA32-NEXT: vxor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vextrins.w $vr1, $vr0, 2 +; LA32-NEXT: vextrins.w $vr1, $vr0, 35 +; LA32-NEXT: vextrins.w $vr0, $vr0, 33 +; LA32-NEXT: xvpermi.q $xr0, $xr1, 2 +; LA32-NEXT: xvrepli.d $xr1, 1 +; LA32-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: xor_zext_masks_v4i64: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 0 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 1 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 1 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 2 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 3 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; LA64-NEXT: vldi $vr0, -1777 +; LA64-NEXT: vxor.v $vr0, $vr1, $vr0 +; LA64-NEXT: vpickve2gr.w $a1, $vr0, 2 +; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 0 +; LA64-NEXT: vpickve2gr.w $a1, $vr0, 3 +; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 1 +; LA64-NEXT: vpickve2gr.w $a1, $vr0, 0 +; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 0 +; LA64-NEXT: vpickve2gr.w $a1, $vr0, 1 +; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 1 +; LA64-NEXT: xvpermi.q $xr2, $xr1, 2 +; LA64-NEXT: xvrepli.d $xr0, 1 +; LA64-NEXT: xvand.v $xr0, $xr2, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret + %v0 = load <4 x double>, ptr %a + %v1 = load <4 x double>, ptr %b + %m0 = fcmp olt <4 x double> %v0, %v1 + %mxor = xor <4 x i1> %m0, + %r = zext <4 x i1> %mxor to <4 x i64> + store <4 x i64> %r, ptr %res + ret void +} + +define void @xor_zext_masks_v8i32(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: xor_zext_masks_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 0 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 1 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 2 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 2 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 3 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 3 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 4 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 5 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 5 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 6 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 7 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 7 +; CHECK-NEXT: vldi $vr0, -2305 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a1, 1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr2, $a1, 0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.w $vr2, $a1, 1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.w $vr2, $a1, 2 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.w $vr2, $a1, 3 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 2 +; CHECK-NEXT: xvrepli.w $xr0, 1 +; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <8 x float>, ptr %a + %v1 = load <8 x float>, ptr %b + %m0 = fcmp olt <8 x float> %v0, %v1 + %mxor = xor <8 x i1> %m0, + %r = zext <8 x i1> %mxor to <8 x i32> + store <8 x i32> %r, ptr %res + ret void +} + +define void @xor_zext_masks_v16i16(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: xor_zext_masks_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvseq.h $xr0, $xr0, $xr1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 2 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 3 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 4 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 5 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 6 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 7 +; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 8 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 9 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 10 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 11 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 12 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 13 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 14 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 15 +; CHECK-NEXT: vrepli.h $vr0, 255 +; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 8 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 0 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 9 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 1 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 10 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 2 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 11 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 3 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 12 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 4 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 13 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 5 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 14 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 6 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 15 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 7 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 0 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 1 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 2 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 3 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 4 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 5 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 6 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 7 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 2 +; CHECK-NEXT: xvrepli.h $xr0, 1 +; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i16>, ptr %a + %v1 = load <16 x i16>, ptr %b + %m0 = icmp eq <16 x i16> %v0, %v1 + %mxor = xor <16 x i1> %m0, + %r = zext <16 x i1> %mxor to <16 x i16> + store <16 x i16> %r, ptr %res + ret void +} + +define void @xor_sext_masks_v4i64(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: xor_sext_masks_v4i64: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 2 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; LA32-NEXT: vldi $vr0, -1777 +; LA32-NEXT: vxor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vori.b $vr1, $vr0, 0 +; LA32-NEXT: vextrins.w $vr1, $vr1, 16 +; LA32-NEXT: vextrins.w $vr1, $vr0, 33 +; LA32-NEXT: vextrins.w $vr1, $vr0, 49 +; LA32-NEXT: vextrins.w $vr2, $vr0, 2 +; LA32-NEXT: vextrins.w $vr2, $vr0, 18 +; LA32-NEXT: vextrins.w $vr2, $vr0, 35 +; LA32-NEXT: vextrins.w $vr2, $vr0, 51 +; LA32-NEXT: xvpermi.q $xr1, $xr2, 2 +; LA32-NEXT: xvst $xr1, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: xor_sext_masks_v4i64: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 0 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 2 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 1 +; LA64-NEXT: xvpickve2gr.d $a2, $xr0, 3 +; LA64-NEXT: vrepli.b $vr0, -1 +; LA64-NEXT: vxor.v $vr0, $vr1, $vr0 +; LA64-NEXT: vpickve2gr.w $a3, $vr0, 2 +; LA64-NEXT: vinsgr2vr.d $vr1, $a3, 0 +; LA64-NEXT: vinsgr2vr.d $vr1, $a2, 1 +; LA64-NEXT: vpickve2gr.w $a2, $vr0, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 0 +; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 1 +; LA64-NEXT: xvpermi.q $xr0, $xr1, 2 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret + %v0 = load <4 x double>, ptr %a + %v1 = load <4 x double>, ptr %b + %m0 = fcmp olt <4 x double> %v0, %v1 + %mxor = xor <4 x i1> %m0, + %r = sext <4 x i1> %mxor to <4 x i64> + store <4 x i64> %r, ptr %res + ret void +} + +define void @xor_sext_masks_v8i32(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: xor_sext_masks_v8i32: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; LA32-NEXT: vinsgr2vr.h $vr1, $a1, 0 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 2 +; LA32-NEXT: vinsgr2vr.h $vr1, $a1, 2 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; LA32-NEXT: vinsgr2vr.h $vr1, $a1, 4 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; LA32-NEXT: vinsgr2vr.h $vr1, $a1, 6 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 3 +; LA32-NEXT: xvpickve2gr.w $a2, $xr0, 1 +; LA32-NEXT: xvpickve2gr.w $a3, $xr0, 7 +; LA32-NEXT: xvpickve2gr.w $a4, $xr0, 5 +; LA32-NEXT: vrepli.b $vr0, -1 +; LA32-NEXT: vxor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vpickve2gr.h $a5, $vr0, 4 +; LA32-NEXT: ext.w.h $a5, $a5 +; LA32-NEXT: vinsgr2vr.w $vr1, $a5, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a4, 1 +; LA32-NEXT: vpickve2gr.h $a4, $vr0, 6 +; LA32-NEXT: ext.w.h $a4, $a4 +; LA32-NEXT: vinsgr2vr.w $vr1, $a4, 2 +; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 3 +; LA32-NEXT: vpickve2gr.h $a3, $vr0, 0 +; LA32-NEXT: ext.w.h $a3, $a3 +; LA32-NEXT: vinsgr2vr.w $vr2, $a3, 0 +; LA32-NEXT: vinsgr2vr.w $vr2, $a2, 1 +; LA32-NEXT: vpickve2gr.h $a2, $vr0, 2 +; LA32-NEXT: ext.w.h $a2, $a2 +; LA32-NEXT: vinsgr2vr.w $vr2, $a2, 2 +; LA32-NEXT: vinsgr2vr.w $vr2, $a1, 3 +; LA32-NEXT: xvpermi.q $xr2, $xr1, 2 +; LA32-NEXT: xvst $xr2, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: xor_sext_masks_v8i32: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; LA64-NEXT: vinsgr2vr.h $vr1, $a1, 0 +; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 2 +; LA64-NEXT: vinsgr2vr.h $vr1, $a1, 2 +; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; LA64-NEXT: vinsgr2vr.h $vr1, $a1, 4 +; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; LA64-NEXT: vinsgr2vr.h $vr1, $a1, 6 +; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 3 +; LA64-NEXT: xvpickve2gr.w $a2, $xr0, 1 +; LA64-NEXT: xvpickve2gr.w $a3, $xr0, 7 +; LA64-NEXT: xvpickve2gr.w $a4, $xr0, 5 +; LA64-NEXT: vrepli.b $vr0, -1 +; LA64-NEXT: vxor.v $vr0, $vr1, $vr0 +; LA64-NEXT: vpickve2gr.h $a5, $vr0, 4 +; LA64-NEXT: ext.w.h $a5, $a5 +; LA64-NEXT: vinsgr2vr.w $vr1, $a5, 0 +; LA64-NEXT: ext.w.h $a4, $a4 +; LA64-NEXT: vinsgr2vr.w $vr1, $a4, 1 +; LA64-NEXT: vpickve2gr.h $a4, $vr0, 6 +; LA64-NEXT: ext.w.h $a4, $a4 +; LA64-NEXT: vinsgr2vr.w $vr1, $a4, 2 +; LA64-NEXT: ext.w.h $a3, $a3 +; LA64-NEXT: vinsgr2vr.w $vr1, $a3, 3 +; LA64-NEXT: vpickve2gr.h $a3, $vr0, 0 +; LA64-NEXT: ext.w.h $a3, $a3 +; LA64-NEXT: vinsgr2vr.w $vr2, $a3, 0 +; LA64-NEXT: ext.w.h $a2, $a2 +; LA64-NEXT: vinsgr2vr.w $vr2, $a2, 1 +; LA64-NEXT: vpickve2gr.h $a2, $vr0, 2 +; LA64-NEXT: ext.w.h $a2, $a2 +; LA64-NEXT: vinsgr2vr.w $vr2, $a2, 2 +; LA64-NEXT: ext.w.h $a1, $a1 +; LA64-NEXT: vinsgr2vr.w $vr2, $a1, 3 +; LA64-NEXT: xvpermi.q $xr2, $xr1, 2 +; LA64-NEXT: xvst $xr2, $a0, 0 +; LA64-NEXT: ret + %v0 = load <8 x float>, ptr %a + %v1 = load <8 x float>, ptr %b + %m0 = fcmp olt <8 x float> %v0, %v1 + %mxor = xor <8 x i1> %m0, + %r = sext <8 x i1> %mxor to <8 x i32> + store <8 x i32> %r, ptr %res + ret void +} + +define void @xor_sext_masks_v16i16(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: xor_sext_masks_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvseq.h $xr0, $xr0, $xr1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 2 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 4 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 6 +; CHECK-NEXT: xvpermi.d $xr2, $xr0, 14 +; CHECK-NEXT: vpickve2gr.h $a1, $vr2, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 8 +; CHECK-NEXT: vpickve2gr.h $a1, $vr2, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 10 +; CHECK-NEXT: vpickve2gr.h $a1, $vr2, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 12 +; CHECK-NEXT: vpickve2gr.h $a1, $vr2, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 14 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 7 +; CHECK-NEXT: vpickve2gr.h $a2, $vr0, 5 +; CHECK-NEXT: vpickve2gr.h $a3, $vr0, 3 +; CHECK-NEXT: vpickve2gr.h $a4, $vr0, 1 +; CHECK-NEXT: vpickve2gr.h $a5, $vr2, 7 +; CHECK-NEXT: vpickve2gr.h $a6, $vr2, 5 +; CHECK-NEXT: vpickve2gr.h $a7, $vr2, 3 +; CHECK-NEXT: vpickve2gr.h $t0, $vr2, 1 +; CHECK-NEXT: vxori.b $vr0, $vr1, 255 +; CHECK-NEXT: vpickve2gr.b $t1, $vr0, 8 +; CHECK-NEXT: ext.w.b $t1, $t1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $t1, 0 +; CHECK-NEXT: ext.w.b $t0, $t0 +; CHECK-NEXT: vinsgr2vr.h $vr1, $t0, 1 +; CHECK-NEXT: vpickve2gr.b $t0, $vr0, 10 +; CHECK-NEXT: ext.w.b $t0, $t0 +; CHECK-NEXT: vinsgr2vr.h $vr1, $t0, 2 +; CHECK-NEXT: ext.w.b $a7, $a7 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a7, 3 +; CHECK-NEXT: vpickve2gr.b $a7, $vr0, 12 +; CHECK-NEXT: ext.w.b $a7, $a7 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a7, 4 +; CHECK-NEXT: ext.w.b $a6, $a6 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a6, 5 +; CHECK-NEXT: vpickve2gr.b $a6, $vr0, 14 +; CHECK-NEXT: ext.w.b $a6, $a6 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a6, 6 +; CHECK-NEXT: ext.w.b $a5, $a5 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a5, 7 +; CHECK-NEXT: vpickve2gr.b $a5, $vr0, 0 +; CHECK-NEXT: ext.w.b $a5, $a5 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a5, 0 +; CHECK-NEXT: ext.w.b $a4, $a4 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a4, 1 +; CHECK-NEXT: vpickve2gr.b $a4, $vr0, 2 +; CHECK-NEXT: ext.w.b $a4, $a4 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a4, 2 +; CHECK-NEXT: ext.w.b $a3, $a3 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a3, 3 +; CHECK-NEXT: vpickve2gr.b $a3, $vr0, 4 +; CHECK-NEXT: ext.w.b $a3, $a3 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a3, 4 +; CHECK-NEXT: ext.w.b $a2, $a2 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a2, 5 +; CHECK-NEXT: vpickve2gr.b $a2, $vr0, 6 +; CHECK-NEXT: ext.w.b $a2, $a2 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a2, 6 +; CHECK-NEXT: ext.w.b $a1, $a1 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 7 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 2 +; CHECK-NEXT: xvst $xr2, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i16>, ptr %a + %v1 = load <16 x i16>, ptr %b + %m0 = icmp eq <16 x i16> %v0, %v1 + %mxor = xor <16 x i1> %m0, + %r = sext <16 x i1> %mxor to <16 x i16> + store <16 x i16> %r, ptr %res + ret void +} + +define void @or_zext_masks_v4i64(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: or_zext_masks_v4i64: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 2 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; LA32-NEXT: vldi $vr0, -1777 +; LA32-NEXT: vor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vextrins.w $vr1, $vr0, 2 +; LA32-NEXT: vextrins.w $vr1, $vr0, 35 +; LA32-NEXT: vextrins.w $vr0, $vr0, 33 +; LA32-NEXT: xvpermi.q $xr0, $xr1, 2 +; LA32-NEXT: xvrepli.d $xr1, 1 +; LA32-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: or_zext_masks_v4i64: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 0 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 1 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 1 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 2 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA64-NEXT: xvpickve2gr.d $a1, $xr0, 3 +; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; LA64-NEXT: vldi $vr0, -1777 +; LA64-NEXT: vor.v $vr0, $vr1, $vr0 +; LA64-NEXT: vpickve2gr.w $a1, $vr0, 2 +; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 0 +; LA64-NEXT: vpickve2gr.w $a1, $vr0, 3 +; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 1 +; LA64-NEXT: vpickve2gr.w $a1, $vr0, 0 +; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 0 +; LA64-NEXT: vpickve2gr.w $a1, $vr0, 1 +; LA64-NEXT: vinsgr2vr.d $vr2, $a1, 1 +; LA64-NEXT: xvpermi.q $xr2, $xr1, 2 +; LA64-NEXT: xvrepli.d $xr0, 1 +; LA64-NEXT: xvand.v $xr0, $xr2, $xr0 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret + %v0 = load <4 x double>, ptr %a + %v1 = load <4 x double>, ptr %b + %m0 = fcmp olt <4 x double> %v0, %v1 + %mor = or <4 x i1> %m0, + %r = zext <4 x i1> %mor to <4 x i64> + store <4 x i64> %r, ptr %res + ret void +} + +define void @or_zext_masks_v8i32(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: or_zext_masks_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 0 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 1 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 2 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 2 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 3 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 3 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 4 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 5 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 5 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 6 +; CHECK-NEXT: xvpickve2gr.w $a1, $xr0, 7 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 7 +; CHECK-NEXT: vldi $vr0, -2305 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a1, 1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.w $vr2, $a1, 0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.w $vr2, $a1, 1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.w $vr2, $a1, 2 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.w $vr2, $a1, 3 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 2 +; CHECK-NEXT: xvrepli.w $xr0, 1 +; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <8 x float>, ptr %a + %v1 = load <8 x float>, ptr %b + %m0 = fcmp olt <8 x float> %v0, %v1 + %mor = or <8 x i1> %m0, + %r = zext <8 x i1> %mor to <8 x i32> + store <8 x i32> %r, ptr %res + ret void +} + +define void @or_zext_masks_v16i16(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: or_zext_masks_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvseq.h $xr0, $xr0, $xr1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 0 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 1 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 2 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 3 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 4 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 5 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 6 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 7 +; CHECK-NEXT: xvpermi.d $xr0, $xr0, 14 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 8 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 9 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 10 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 11 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 12 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 13 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 14 +; CHECK-NEXT: vpickve2gr.h $a1, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.b $vr1, $a1, 15 +; CHECK-NEXT: vrepli.h $vr0, 255 +; CHECK-NEXT: vor.v $vr0, $vr1, $vr0 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 8 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 0 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 9 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 1 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 10 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 2 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 11 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 3 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 12 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 4 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 13 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 5 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 14 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 6 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 15 +; CHECK-NEXT: vinsgr2vr.h $vr1, $a1, 7 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 0 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 0 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 1 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 1 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 2 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 2 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 3 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 3 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 4 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 4 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 5 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 5 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 6 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 6 +; CHECK-NEXT: vpickve2gr.b $a1, $vr0, 7 +; CHECK-NEXT: vinsgr2vr.h $vr2, $a1, 7 +; CHECK-NEXT: xvpermi.q $xr2, $xr1, 2 +; CHECK-NEXT: xvrepli.h $xr0, 1 +; CHECK-NEXT: xvand.v $xr0, $xr2, $xr0 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i16>, ptr %a + %v1 = load <16 x i16>, ptr %b + %m0 = icmp eq <16 x i16> %v0, %v1 + %mor = or <16 x i1> %m0, + %r = zext <16 x i1> %mor to <16 x i16> + store <16 x i16> %r, ptr %res + ret void +} + +define void @or_sext_masks_v4i64(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: or_sext_masks_v4i64: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 2 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3 +; LA32-NEXT: vldi $vr0, -1777 +; LA32-NEXT: vor.v $vr0, $vr1, $vr0 +; LA32-NEXT: vori.b $vr1, $vr0, 0 +; LA32-NEXT: vextrins.w $vr1, $vr1, 16 +; LA32-NEXT: vextrins.w $vr1, $vr0, 33 +; LA32-NEXT: vextrins.w $vr1, $vr0, 49 +; LA32-NEXT: vextrins.w $vr2, $vr0, 2 +; LA32-NEXT: vextrins.w $vr2, $vr0, 18 +; LA32-NEXT: vextrins.w $vr2, $vr0, 35 +; LA32-NEXT: vextrins.w $vr2, $vr0, 51 +; LA32-NEXT: xvpermi.q $xr1, $xr2, 2 +; LA32-NEXT: xvst $xr1, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: or_sext_masks_v4i64: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA64-NEXT: xvrepli.b $xr1, -1 +; LA64-NEXT: xvextrins.d $xr1, $xr0, 17 +; LA64-NEXT: xvst $xr1, $a0, 0 +; LA64-NEXT: ret + %v0 = load <4 x double>, ptr %a + %v1 = load <4 x double>, ptr %b + %m0 = fcmp olt <4 x double> %v0, %v1 + %mor = or <4 x i1> %m0, + %r = sext <4 x i1> %mor to <4 x i64> + store <4 x i64> %r, ptr %res + ret void +} + +define void @or_sext_masks_v8i32(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: or_sext_masks_v8i32: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; LA32-NEXT: xvpickve.w $xr1, $xr0, 1 +; LA32-NEXT: xvrepli.b $xr2, -1 +; LA32-NEXT: xvinsve0.w $xr2, $xr1, 1 +; LA32-NEXT: xvpickve.w $xr1, $xr0, 3 +; LA32-NEXT: xvinsve0.w $xr2, $xr1, 3 +; LA32-NEXT: xvpickve.w $xr1, $xr0, 5 +; LA32-NEXT: xvinsve0.w $xr2, $xr1, 5 +; LA32-NEXT: xvpickve.w $xr0, $xr0, 7 +; LA32-NEXT: xvinsve0.w $xr2, $xr0, 7 +; LA32-NEXT: xvst $xr2, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: or_sext_masks_v8i32: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 7 +; LA64-NEXT: xvpickve2gr.w $a2, $xr0, 5 +; LA64-NEXT: xvpickve2gr.w $a3, $xr0, 3 +; LA64-NEXT: xvpickve2gr.w $a4, $xr0, 1 +; LA64-NEXT: ext.w.h $a4, $a4 +; LA64-NEXT: xvrepli.b $xr0, -1 +; LA64-NEXT: xvinsgr2vr.w $xr0, $a4, 1 +; LA64-NEXT: ext.w.h $a3, $a3 +; LA64-NEXT: xvinsgr2vr.w $xr0, $a3, 3 +; LA64-NEXT: ext.w.h $a2, $a2 +; LA64-NEXT: xvinsgr2vr.w $xr0, $a2, 5 +; LA64-NEXT: ext.w.h $a1, $a1 +; LA64-NEXT: xvinsgr2vr.w $xr0, $a1, 7 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret + %v0 = load <8 x float>, ptr %a + %v1 = load <8 x float>, ptr %b + %m0 = fcmp olt <8 x float> %v0, %v1 + %mor = or <8 x i1> %m0, + %r = sext <8 x i1> %mor to <8 x i32> + store <8 x i32> %r, ptr %res + ret void +} + +define void @or_sext_masks_v16i16(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: or_sext_masks_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvseq.h $xr0, $xr0, $xr1 +; CHECK-NEXT: xvpermi.d $xr1, $xr0, 14 +; CHECK-NEXT: vpickve2gr.h $a1, $vr1, 7 +; CHECK-NEXT: vpickve2gr.h $a2, $vr1, 5 +; CHECK-NEXT: vpickve2gr.h $a3, $vr1, 3 +; CHECK-NEXT: vpickve2gr.h $a4, $vr1, 1 +; CHECK-NEXT: vpickve2gr.h $a5, $vr0, 7 +; CHECK-NEXT: vpickve2gr.h $a6, $vr0, 5 +; CHECK-NEXT: vpickve2gr.h $a7, $vr0, 3 +; CHECK-NEXT: vpickve2gr.h $t0, $vr0, 1 +; CHECK-NEXT: ext.w.b $t0, $t0 +; CHECK-NEXT: xvrepli.b $xr0, -1 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $t0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 17 +; CHECK-NEXT: ext.w.b $a7, $a7 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a7 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 51 +; CHECK-NEXT: ext.w.b $a6, $a6 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a6 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 85 +; CHECK-NEXT: ext.w.b $a5, $a5 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a5 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 119 +; CHECK-NEXT: ext.w.b $a4, $a4 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a4 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 17 +; CHECK-NEXT: ext.w.b $a3, $a3 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a3 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 51 +; CHECK-NEXT: ext.w.b $a2, $a2 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a2 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 85 +; CHECK-NEXT: ext.w.b $a1, $a1 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a1 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 119 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i16>, ptr %a + %v1 = load <16 x i16>, ptr %b + %m0 = icmp eq <16 x i16> %v0, %v1 + %mor = or <16 x i1> %m0, + %r = sext <16 x i1> %mor to <16 x i16> + store <16 x i16> %r, ptr %res + ret void +} + +define void @and_zext_masks_v4i64(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: and_zext_masks_v4i64: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA32-NEXT: vldi $vr0, -1777 +; LA32-NEXT: vand.v $vr0, $vr1, $vr0 +; LA32-NEXT: vextrins.w $vr1, $vr0, 2 +; LA32-NEXT: vextrins.w $vr1, $vr0, 35 +; LA32-NEXT: vextrins.w $vr0, $vr0, 33 +; LA32-NEXT: xvpermi.q $xr0, $xr1, 2 +; LA32-NEXT: xvrepli.d $xr1, 1 +; LA32-NEXT: xvand.v $xr0, $xr0, $xr1 +; LA32-NEXT: xvst $xr0, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: and_zext_masks_v4i64: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: pcalau12i $a1, %pc_hi20(.LCPI12_0) +; LA64-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI12_0) +; LA64-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA64-NEXT: xvand.v $xr0, $xr0, $xr2 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret + %v0 = load <4 x double>, ptr %a + %v1 = load <4 x double>, ptr %b + %m0 = fcmp olt <4 x double> %v0, %v1 + %mand = and <4 x i1> %m0, + %r = zext <4 x i1> %mand to <4 x i64> + store <4 x i64> %r, ptr %res + ret void +} + +define void @and_zext_masks_v8i32(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: and_zext_masks_v8i32: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; CHECK-NEXT: xvrepli.d $xr1, 1 +; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <8 x float>, ptr %a + %v1 = load <8 x float>, ptr %b + %m0 = fcmp olt <8 x float> %v0, %v1 + %mand = and <8 x i1> %m0, + %r = zext <8 x i1> %mand to <8 x i32> + store <8 x i32> %r, ptr %res + ret void +} + +define void @and_zext_masks_v16i16(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: and_zext_masks_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvseq.h $xr0, $xr0, $xr1 +; CHECK-NEXT: xvrepli.w $xr1, 1 +; CHECK-NEXT: xvand.v $xr0, $xr0, $xr1 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i16>, ptr %a + %v1 = load <16 x i16>, ptr %b + %m0 = icmp eq <16 x i16> %v0, %v1 + %mand = and <16 x i1> %m0, + %r = zext <16 x i1> %mand to <16 x i16> + store <16 x i16> %r, ptr %res + ret void +} + +define void @and_sext_masks_v4i64(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: and_sext_masks_v4i64: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 0 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 0 +; LA32-NEXT: xvpickve2gr.w $a1, $xr0, 4 +; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 2 +; LA32-NEXT: vldi $vr0, -1777 +; LA32-NEXT: vand.v $vr0, $vr1, $vr0 +; LA32-NEXT: vori.b $vr1, $vr0, 0 +; LA32-NEXT: vextrins.w $vr1, $vr1, 16 +; LA32-NEXT: vextrins.w $vr1, $vr0, 33 +; LA32-NEXT: vextrins.w $vr1, $vr0, 49 +; LA32-NEXT: vextrins.w $vr2, $vr0, 2 +; LA32-NEXT: vextrins.w $vr2, $vr0, 18 +; LA32-NEXT: vextrins.w $vr2, $vr0, 35 +; LA32-NEXT: vextrins.w $vr2, $vr0, 51 +; LA32-NEXT: xvpermi.q $xr1, $xr2, 2 +; LA32-NEXT: xvst $xr1, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: and_sext_masks_v4i64: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: xvfcmp.clt.d $xr0, $xr0, $xr1 +; LA64-NEXT: xvrepli.b $xr1, 0 +; LA64-NEXT: xvextrins.d $xr1, $xr0, 0 +; LA64-NEXT: xvst $xr1, $a0, 0 +; LA64-NEXT: ret + %v0 = load <4 x double>, ptr %a + %v1 = load <4 x double>, ptr %b + %m0 = fcmp olt <4 x double> %v0, %v1 + %mand = and <4 x i1> %m0, + %r = sext <4 x i1> %mand to <4 x i64> + store <4 x i64> %r, ptr %res + ret void +} + +define void @and_sext_masks_v8i32(ptr %res, ptr %a, ptr %b) nounwind { +; LA32-LABEL: and_sext_masks_v8i32: +; LA32: # %bb.0: +; LA32-NEXT: xvld $xr0, $a1, 0 +; LA32-NEXT: xvld $xr1, $a2, 0 +; LA32-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; LA32-NEXT: xvrepli.b $xr1, 0 +; LA32-NEXT: xvinsve0.w $xr1, $xr0, 0 +; LA32-NEXT: xvpickve.w $xr2, $xr0, 2 +; LA32-NEXT: xvinsve0.w $xr1, $xr2, 2 +; LA32-NEXT: xvpickve.w $xr2, $xr0, 4 +; LA32-NEXT: xvinsve0.w $xr1, $xr2, 4 +; LA32-NEXT: xvpickve.w $xr0, $xr0, 6 +; LA32-NEXT: xvinsve0.w $xr1, $xr0, 6 +; LA32-NEXT: xvst $xr1, $a0, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: and_sext_masks_v8i32: +; LA64: # %bb.0: +; LA64-NEXT: xvld $xr0, $a1, 0 +; LA64-NEXT: xvld $xr1, $a2, 0 +; LA64-NEXT: xvfcmp.clt.s $xr0, $xr0, $xr1 +; LA64-NEXT: xvpickve2gr.w $a1, $xr0, 6 +; LA64-NEXT: xvpickve2gr.w $a2, $xr0, 4 +; LA64-NEXT: xvpickve2gr.w $a3, $xr0, 2 +; LA64-NEXT: xvpickve2gr.w $a4, $xr0, 0 +; LA64-NEXT: ext.w.h $a4, $a4 +; LA64-NEXT: xvrepli.b $xr0, 0 +; LA64-NEXT: xvinsgr2vr.w $xr0, $a4, 0 +; LA64-NEXT: ext.w.h $a3, $a3 +; LA64-NEXT: xvinsgr2vr.w $xr0, $a3, 2 +; LA64-NEXT: ext.w.h $a2, $a2 +; LA64-NEXT: xvinsgr2vr.w $xr0, $a2, 4 +; LA64-NEXT: ext.w.h $a1, $a1 +; LA64-NEXT: xvinsgr2vr.w $xr0, $a1, 6 +; LA64-NEXT: xvst $xr0, $a0, 0 +; LA64-NEXT: ret + %v0 = load <8 x float>, ptr %a + %v1 = load <8 x float>, ptr %b + %m0 = fcmp olt <8 x float> %v0, %v1 + %mand = and <8 x i1> %m0, + %r = sext <8 x i1> %mand to <8 x i32> + store <8 x i32> %r, ptr %res + ret void +} + +define void @and_sext_masks_v16i16(ptr %res, ptr %a, ptr %b) nounwind { +; CHECK-LABEL: and_sext_masks_v16i16: +; CHECK: # %bb.0: +; CHECK-NEXT: xvld $xr0, $a1, 0 +; CHECK-NEXT: xvld $xr1, $a2, 0 +; CHECK-NEXT: xvseq.h $xr0, $xr0, $xr1 +; CHECK-NEXT: xvpermi.d $xr1, $xr0, 14 +; CHECK-NEXT: vpickve2gr.h $a1, $vr1, 6 +; CHECK-NEXT: vpickve2gr.h $a2, $vr1, 4 +; CHECK-NEXT: vpickve2gr.h $a3, $vr1, 2 +; CHECK-NEXT: vpickve2gr.h $a4, $vr1, 0 +; CHECK-NEXT: vpickve2gr.h $a5, $vr0, 6 +; CHECK-NEXT: vpickve2gr.h $a6, $vr0, 4 +; CHECK-NEXT: vpickve2gr.h $a7, $vr0, 2 +; CHECK-NEXT: vpickve2gr.h $t0, $vr0, 0 +; CHECK-NEXT: ext.w.b $t0, $t0 +; CHECK-NEXT: xvrepli.b $xr0, 0 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $t0 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 0 +; CHECK-NEXT: ext.w.b $a7, $a7 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a7 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 34 +; CHECK-NEXT: ext.w.b $a6, $a6 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a6 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 68 +; CHECK-NEXT: ext.w.b $a5, $a5 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a5 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 102 +; CHECK-NEXT: ext.w.b $a4, $a4 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a4 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 0 +; CHECK-NEXT: ext.w.b $a3, $a3 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a3 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 34 +; CHECK-NEXT: ext.w.b $a2, $a2 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a2 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 68 +; CHECK-NEXT: ext.w.b $a1, $a1 +; CHECK-NEXT: xvreplgr2vr.h $xr1, $a1 +; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48 +; CHECK-NEXT: xvextrins.h $xr0, $xr1, 102 +; CHECK-NEXT: xvst $xr0, $a0, 0 +; CHECK-NEXT: ret + %v0 = load <16 x i16>, ptr %a + %v1 = load <16 x i16>, ptr %b + %m0 = icmp eq <16 x i16> %v0, %v1 + %mand = and <16 x i1> %m0, + %r = sext <16 x i1> %mand to <16 x i16> + store <16 x i16> %r, ptr %res + ret void +} diff --git a/llvm/test/CodeGen/LoongArch/lsx/issue177155.ll b/llvm/test/CodeGen/LoongArch/lsx/issue177155.ll new file mode 100644 index 0000000000000..b33544da2af73 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/lsx/issue177155.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s + +define i8 @test(<2 x i32> %vecinit7) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vrepli.d $vr1, 1 +; CHECK-NEXT: vand.v $vr0, $vr0, $vr1 +; CHECK-NEXT: vneg.d $vr0, $vr0 +; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4 +; CHECK-NEXT: ret +entry: + %0 = tail call <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8> splat (i8 1), <16 x i8> zeroinitializer) + %shuffle = shufflevector <16 x i8> %0, <16 x i8> zeroinitializer, <2 x i32> + %1 = and <2 x i8> %shuffle, splat (i8 1) + %and = zext <2 x i8> %1 to <2 x i32> + %and.i = and <2 x i32> %vecinit7, %and + %conv.i = zext <2 x i32> %and.i to <2 x i64> + %sub.i = sub <2 x i64> zeroinitializer, %conv.i + %2 = bitcast <2 x i64> %sub.i to <16 x i8> + %conv14 = extractelement <16 x i8> %2, i64 4 + ret i8 %conv14 +} + +declare <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8>, <16 x i8>) diff --git a/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir b/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir new file mode 100644 index 0000000000000..ba98a525c24b5 --- /dev/null +++ b/llvm/test/CodeGen/MIR/Mips/mips32r6-copyPhysReg-fcmp-f64-to-gpr.mir @@ -0,0 +1,18 @@ +# RUN: llc -mtriple=mipsisa32r6-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s + +name: f +alignment: 4 +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $d12_64, $d14_64 + + renamable $d0_64 = CMP_LT_D renamable $d14_64, renamable $d12_64 + ; CHECK: cmp.lt.d + $v1 = MFC1_D64 $d0_64 + ; CHECK: mfc1 + renamable $v0 = COPY renamable $d0_64 + ; CHECK: mfc1 + renamable $v0 = SUBu killed renamable $v1, killed renamable $v0 + RetRA implicit $v0 +... diff --git a/llvm/test/CodeGen/MIR/RISCV/skip-mir-comment-trailing-whitespace.mir b/llvm/test/CodeGen/MIR/RISCV/skip-mir-comment-trailing-whitespace.mir index 4fcdd0ec2ef8c..38e343d59beb8 100644 --- a/llvm/test/CodeGen/MIR/RISCV/skip-mir-comment-trailing-whitespace.mir +++ b/llvm/test/CodeGen/MIR/RISCV/skip-mir-comment-trailing-whitespace.mir @@ -6,7 +6,7 @@ tracksRegLiveness: true body: | bb.0: ; CHECK-LABEL: name: test_vse8{{$}} - ; CHECK: PseudoVSE8_V_MF8 %1, %2, %0, 3 /* e8 */ :: (store unknown-size, align 1) + ; CHECK: PseudoVSE8_V_MF8 %1, %2, %0 /* vl */, 3 /* e8 */ :: (store unknown-size, align 1) liveins: $x10, $v8, $x11 %0:gprnox0 = COPY $x11 diff --git a/llvm/test/CodeGen/Mips/musttail-disabled.ll b/llvm/test/CodeGen/Mips/musttail-disabled.ll new file mode 100644 index 0000000000000..f300a45879f9d --- /dev/null +++ b/llvm/test/CodeGen/Mips/musttail-disabled.ll @@ -0,0 +1,16 @@ +; RUN: not --crash llc -mtriple=mips-unknown-linux-gnu < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=mips-unknown-linux-gnu -mips-tail-calls=0 < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=mips64-unknown-linux-gnu < %s 2>&1 | FileCheck %s + +; Test that musttail fails when MIPS tail calls are disabled (default). + +; CHECK: LLVM ERROR: failed to perform tail call elimination on a call site marked musttail + +define hidden i32 @callee(i32 %a) { + ret i32 %a +} + +define i32 @caller(i32 %a) { + %ret = musttail call i32 @callee(i32 %a) + ret i32 %ret +} diff --git a/llvm/test/CodeGen/Mips/musttail-fastisel.ll b/llvm/test/CodeGen/Mips/musttail-fastisel.ll new file mode 100644 index 0000000000000..3ab742662de6f --- /dev/null +++ b/llvm/test/CodeGen/Mips/musttail-fastisel.ll @@ -0,0 +1,28 @@ +; RUN: llc -mtriple=mips-unknown-linux-gnu -mips-tail-calls=1 -O0 < %s | FileCheck %s +; RUN: llc -mtriple=mips64-unknown-linux-gnu -mips-tail-calls=1 -O0 < %s | FileCheck %s + +; Test that musttail works correctly at -O0 when Fast ISel is used. +; This is a regression test for a bug where Fast ISel incorrectly set +; IncomingArgSize to 0 for functions with no arguments, causing the +; tail call eligibility check to fail. + +@ptr = dso_local global ptr null, align 4 + +define dso_local void @callee() { +entry: + %local = alloca i32, align 4 + store volatile i32 2, ptr %local, align 4 + ret void +} + +; CHECK-LABEL: caller: +; CHECK: j callee +; CHECK-NOT: jal callee +define dso_local void @caller() { +entry: + %local = alloca i32, align 4 + store i32 1, ptr %local, align 4 + store ptr %local, ptr @ptr, align 4 + musttail call void @callee() + ret void +} diff --git a/llvm/test/CodeGen/Mips/musttail.ll b/llvm/test/CodeGen/Mips/musttail.ll index b96cb2b923984..1bd7682f16bb5 100644 --- a/llvm/test/CodeGen/Mips/musttail.ll +++ b/llvm/test/CodeGen/Mips/musttail.ll @@ -5,6 +5,15 @@ ; Test musttail support for MIPS define dso_local i32 @callee_args(i32 %a, i32 %b, i32 %c) { +; MIPS32-LABEL: callee_args: +; MIPS32: # %bb.0: +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $2, $4 +; +; MIPS64-LABEL: callee_args: +; MIPS64: # %bb.0: +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $4, 0 ret i32 %a; } @@ -25,6 +34,15 @@ define i32 @test_musttail_args(i32 %x, i32 %y, i32 %z) { ; Test musttail with many arguments that spill to stack (involves memory) ; MIPS O32 ABI: first 4 args in $a0-$a3, rest on stack define hidden i32 @many_args_callee(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) { +; MIPS32-LABEL: many_args_callee: +; MIPS32: # %bb.0: +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: move $2, $4 +; +; MIPS64-LABEL: many_args_callee: +; MIPS64: # %bb.0: +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: sll $2, $4, 0 ret i32 %a } @@ -53,6 +71,17 @@ define i32 @test_musttail_many_args(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %struct.large = type { i32, i32, i32, i32, i32, i32, i32, i32 } define hidden i32 @callee_with_struct(%struct.large %s, i32 %x) { +; MIPS32-LABEL: callee_with_struct: +; MIPS32: # %bb.0: +; MIPS32-NEXT: lw $2, 32($sp) +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +; +; MIPS64-LABEL: callee_with_struct: +; MIPS64: # %bb.0: +; MIPS64-NEXT: lw $2, 4($sp) +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: nop ret i32 %x } @@ -82,6 +111,15 @@ define i32 @test_musttail_struct(%struct.large %s, i32 %x) { ; Test musttail with mixed int and float arguments that use stack define hidden float @mixed_args_callee(i32 %a, float %b, i32 %c, float %d, i32 %e, float %f) { +; MIPS32-LABEL: mixed_args_callee: +; MIPS32: # %bb.0: +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: mtc1 $5, $f0 +; +; MIPS64-LABEL: mixed_args_callee: +; MIPS64: # %bb.0: +; MIPS64-NEXT: jr $ra +; MIPS64-NEXT: mov.s $f0, $f13 ret float %b } diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll deleted file mode 100644 index 88fae7a3f78a0..0000000000000 --- a/llvm/test/CodeGen/NVPTX/atomicrmw-expand.ll +++ /dev/null @@ -1,151 +0,0 @@ -; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_30 | FileCheck %s --check-prefixes=ALL,SM30 -; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_60 | FileCheck %s --check-prefixes=ALL,SM60 -; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_30 | %ptxas-verify %} -; RUN: %if ptxas-sm_60 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_60 | %ptxas-verify -arch=sm_60 %} - -; CHECK-LABEL: fadd_double -define void @fadd_double(ptr %0, double %1) { -entry: - ; SM30: atom.cas.b64 - ; SM60: atom.add.f64 - %2 = atomicrmw fadd ptr %0, double %1 monotonic, align 8 - ret void -} - -; CHECK-LABEL: fadd_float -define void @fadd_float(ptr %0, float %1) { -entry: - ; ALL: atom.add.f32 - %2 = atomicrmw fadd ptr %0, float %1 monotonic, align 4 - ret void -} - -; CHECK-LABEL: bitwise_i32 -define void @bitwise_i32(ptr %0, i32 %1) { -entry: - ; ALL: atom.and.b32 - %2 = atomicrmw and ptr %0, i32 %1 monotonic, align 4 - ; ALL: atom.or.b32 - %3 = atomicrmw or ptr %0, i32 %1 monotonic, align 4 - ; ALL: atom.xor.b32 - %4 = atomicrmw xor ptr %0, i32 %1 monotonic, align 4 - ; ALL: atom.exch.b32 - %5 = atomicrmw xchg ptr %0, i32 %1 monotonic, align 4 - ret void -} - -; CHECK-LABEL: bitwise_i64 -define void @bitwise_i64(ptr %0, i64 %1) { -entry: - ; SM30: atom.cas.b64 - ; SM60: atom.and.b64 - %2 = atomicrmw and ptr %0, i64 %1 monotonic, align 8 - ; SM30: atom.cas.b64 - ; SM60: atom.or.b64 - %3 = atomicrmw or ptr %0, i64 %1 monotonic, align 8 - ; SM30: atom.cas.b64 - ; SM60: atom.xor.b64 - %4 = atomicrmw xor ptr %0, i64 %1 monotonic, align 8 - ; SM30: atom.cas.b64 - ; SM60: atom.exch.b64 - %5 = atomicrmw xchg ptr %0, i64 %1 monotonic, align 8 - ret void -} - -; CHECK-LABEL: minmax_i32 -define void @minmax_i32(ptr %0, i32 %1) { -entry: - ; ALL: atom.min.s32 - %2 = atomicrmw min ptr %0, i32 %1 monotonic, align 4 - ; ALL: atom.max.s32 - %3 = atomicrmw max ptr %0, i32 %1 monotonic, align 4 - ; ALL: atom.min.u32 - %4 = atomicrmw umin ptr %0, i32 %1 monotonic, align 4 - ; ALL: atom.max.u32 - %5 = atomicrmw umax ptr %0, i32 %1 monotonic, align 4 - ret void -} - -; CHECK-LABEL: minmax_i64 -define void @minmax_i64(ptr %0, i64 %1) { -entry: - ; SM30: atom.cas.b64 - ; SM60: atom.min.s64 - %2 = atomicrmw min ptr %0, i64 %1 monotonic, align 8 - ; SM30: atom.cas.b64 - ; SM60: atom.max.s64 - %3 = atomicrmw max ptr %0, i64 %1 monotonic, align 8 - ; SM30: atom.cas.b64 - ; SM60: atom.min.u64 - %4 = atomicrmw umin ptr %0, i64 %1 monotonic, align 8 - ; SM30: atom.cas.b64 - ; SM60: atom.max.u64 - %5 = atomicrmw umax ptr %0, i64 %1 monotonic, align 8 - ret void -} - -; CHECK-LABEL: bitwise_i8 -define void @bitwise_i8(ptr %0, i8 %1) { -entry: - ; ALL: atom.and.b32 - %2 = atomicrmw and ptr %0, i8 %1 monotonic, align 1 - ; ALL: atom.or.b32 - %3 = atomicrmw or ptr %0, i8 %1 monotonic, align 1 - ; ALL: atom.xor.b32 - %4 = atomicrmw xor ptr %0, i8 %1 monotonic, align 1 - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %5 = atomicrmw xchg ptr %0, i8 %1 monotonic, align 1 - ret void -} - -; CHECK-LABEL: minmax_i8 -define void @minmax_i8(ptr %0, i8 %1) { -entry: - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %2 = atomicrmw min ptr %0, i8 %1 monotonic, align 1 - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %3 = atomicrmw max ptr %0, i8 %1 monotonic, align 1 - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %4 = atomicrmw umin ptr %0, i8 %1 monotonic, align 1 - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %5 = atomicrmw umax ptr %0, i8 %1 monotonic, align 1 - ret void -} - -; CHECK-LABEL: bitwise_i16 -define void @bitwise_i16(ptr %0, i16 %1) { -entry: - ; ALL: atom.and.b32 - %2 = atomicrmw and ptr %0, i16 %1 monotonic, align 2 - ; ALL: atom.or.b32 - %3 = atomicrmw or ptr %0, i16 %1 monotonic, align 2 - ; ALL: atom.xor.b32 - %4 = atomicrmw xor ptr %0, i16 %1 monotonic, align 2 - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %5 = atomicrmw xchg ptr %0, i16 %1 monotonic, align 2 - ret void -} - -; CHECK-LABEL: minmax_i16 -define void @minmax_i16(ptr %0, i16 %1) { -entry: - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %2 = atomicrmw min ptr %0, i16 %1 monotonic, align 2 - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %3 = atomicrmw max ptr %0, i16 %1 monotonic, align 2 - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %4 = atomicrmw umin ptr %0, i16 %1 monotonic, align 2 - ; SM30: atom.cas.b32 - ; SM60: atom.sys.cas.b32 - %5 = atomicrmw umax ptr %0, i16 %1 monotonic, align 2 - ret void -} diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll new file mode 100644 index 0000000000000..7509cb53e424c --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/atomicrmw-sm60.ll @@ -0,0 +1,3137 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 -mattr=+ptx50 | FileCheck %s --check-prefix=SM60 +; RUN: %if ptxas-sm_60 && ptxas-isa-5.0 %{ llc < %s -march=nvptx64 -mcpu=sm_60 -mattr=+ptx50 | %ptxas-verify -arch=sm_60 %} + +define i8 @xchg_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: xchg_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<14>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r5, [xchg_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r6, %rd2; +; SM60-NEXT: and.b32 %r7, %r6, 3; +; SM60-NEXT: shl.b32 %r1, %r7, 3; +; SM60-NEXT: mov.b32 %r8, 255; +; SM60-NEXT: shl.b32 %r9, %r8, %r1; +; SM60-NEXT: not.b32 %r2, %r9; +; SM60-NEXT: shl.b32 %r3, %r5, %r1; +; SM60-NEXT: ld.global.b32 %r13, [%rd1]; +; SM60-NEXT: $L__BB0_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r10, %r13, %r2; +; SM60-NEXT: or.b32 %r11, %r10, %r3; +; SM60-NEXT: atom.cta.global.cas.b32 %r4, [%rd1], %r13, %r11; +; SM60-NEXT: setp.ne.b32 %p1, %r4, %r13; +; SM60-NEXT: mov.b32 %r13, %r4; +; SM60-NEXT: @%p1 bra $L__BB0_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r12, %r4, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r12; +; SM60-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @xchg_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: xchg_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<14>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b16 %r5, [xchg_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r6, %rd2; +; SM60-NEXT: and.b32 %r7, %r6, 3; +; SM60-NEXT: shl.b32 %r1, %r7, 3; +; SM60-NEXT: mov.b32 %r8, 65535; +; SM60-NEXT: shl.b32 %r9, %r8, %r1; +; SM60-NEXT: not.b32 %r2, %r9; +; SM60-NEXT: shl.b32 %r3, %r5, %r1; +; SM60-NEXT: ld.global.b32 %r13, [%rd1]; +; SM60-NEXT: $L__BB1_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r10, %r13, %r2; +; SM60-NEXT: or.b32 %r11, %r10, %r3; +; SM60-NEXT: atom.cta.global.cas.b32 %r4, [%rd1], %r13, %r11; +; SM60-NEXT: setp.ne.b32 %p1, %r4, %r13; +; SM60-NEXT: mov.b32 %r13, %r4; +; SM60-NEXT: @%p1 bra $L__BB1_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r12, %r4, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r12; +; SM60-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @xchg_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: xchg_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [xchg_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [xchg_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.exch.b32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @xchg_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: xchg_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [xchg_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.exch.b64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @add_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: add_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [add_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r6, [add_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB4_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: add.s32 %r10, %r15, %r4; +; SM60-NEXT: and.b32 %r11, %r10, %r2; +; SM60-NEXT: and.b32 %r12, %r15, %r3; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM60-NEXT: mov.b32 %r15, %r5; +; SM60-NEXT: @%p1 bra $L__BB4_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @add_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: add_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [add_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b16 %r6, [add_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 65535; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB5_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: add.s32 %r10, %r15, %r4; +; SM60-NEXT: and.b32 %r11, %r10, %r2; +; SM60-NEXT: and.b32 %r12, %r15, %r3; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM60-NEXT: mov.b32 %r15, %r5; +; SM60-NEXT: @%p1 bra $L__BB5_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @add_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: add_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.add.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @add_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: add_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.add.u64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @sub_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: sub_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r6, [sub_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB8_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: sub.s32 %r10, %r15, %r4; +; SM60-NEXT: and.b32 %r11, %r10, %r2; +; SM60-NEXT: and.b32 %r12, %r15, %r3; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM60-NEXT: mov.b32 %r15, %r5; +; SM60-NEXT: @%p1 bra $L__BB8_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @sub_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: sub_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b16 %r6, [sub_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 65535; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB9_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: sub.s32 %r10, %r15, %r4; +; SM60-NEXT: and.b32 %r11, %r10, %r2; +; SM60-NEXT: and.b32 %r12, %r15, %r3; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM60-NEXT: mov.b32 %r15, %r5; +; SM60-NEXT: @%p1 bra $L__BB9_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @sub_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: sub_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<4>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [sub_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [sub_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: neg.s32 %r2, %r1; +; SM60-NEXT: atom.cta.global.add.u32 %r3, [%rd1], %r2; +; SM60-NEXT: st.param.b32 [func_retval0], %r3; +; SM60-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @sub_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: sub_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<5>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [sub_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: neg.s64 %rd3, %rd2; +; SM60-NEXT: atom.cta.global.add.u64 %rd4, [%rd1], %rd3; +; SM60-NEXT: st.param.b64 [func_retval0], %rd4; +; SM60-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @and_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: and_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<12>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [and_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r1, [and_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd2, %rd1, -4; +; SM60-NEXT: cvt.u32.u64 %r2, %rd1; +; SM60-NEXT: and.b32 %r3, %r2, 3; +; SM60-NEXT: shl.b32 %r4, %r3, 3; +; SM60-NEXT: mov.b32 %r5, 255; +; SM60-NEXT: shl.b32 %r6, %r5, %r4; +; SM60-NEXT: not.b32 %r7, %r6; +; SM60-NEXT: shl.b32 %r8, %r1, %r4; +; SM60-NEXT: or.b32 %r9, %r8, %r7; +; SM60-NEXT: atom.cta.global.and.b32 %r10, [%rd2], %r9; +; SM60-NEXT: shr.u32 %r11, %r10, %r4; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r11; +; SM60-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @and_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: and_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<12>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [and_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b16 %r1, [and_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd2, %rd1, -4; +; SM60-NEXT: cvt.u32.u64 %r2, %rd1; +; SM60-NEXT: and.b32 %r3, %r2, 3; +; SM60-NEXT: shl.b32 %r4, %r3, 3; +; SM60-NEXT: mov.b32 %r5, 65535; +; SM60-NEXT: shl.b32 %r6, %r5, %r4; +; SM60-NEXT: not.b32 %r7, %r6; +; SM60-NEXT: shl.b32 %r8, %r1, %r4; +; SM60-NEXT: or.b32 %r9, %r8, %r7; +; SM60-NEXT: atom.cta.global.and.b32 %r10, [%rd2], %r9; +; SM60-NEXT: shr.u32 %r11, %r10, %r4; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r11; +; SM60-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @and_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: and_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [and_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [and_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.and.b32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @and_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: and_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [and_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [and_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.and.b64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @nand_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: nand_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<17>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r6, [nand_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r16, [%rd1]; +; SM60-NEXT: $L__BB16_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r10, %r16, %r4; +; SM60-NEXT: not.b32 %r11, %r10; +; SM60-NEXT: and.b32 %r12, %r11, %r2; +; SM60-NEXT: and.b32 %r13, %r16, %r3; +; SM60-NEXT: or.b32 %r14, %r13, %r12; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM60-NEXT: mov.b32 %r16, %r5; +; SM60-NEXT: @%p1 bra $L__BB16_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r15, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r15; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @nand_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: nand_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<17>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b16 %r6, [nand_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 65535; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r16, [%rd1]; +; SM60-NEXT: $L__BB17_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r10, %r16, %r4; +; SM60-NEXT: not.b32 %r11, %r10; +; SM60-NEXT: and.b32 %r12, %r11, %r2; +; SM60-NEXT: and.b32 %r13, %r16, %r3; +; SM60-NEXT: or.b32 %r14, %r13, %r12; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM60-NEXT: mov.b32 %r16, %r5; +; SM60-NEXT: @%p1 bra $L__BB17_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r15, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r15; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @nand_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: nand_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<6>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r5, [%rd1]; +; SM60-NEXT: $L__BB18_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r3, %r5, %r2; +; SM60-NEXT: not.b32 %r4, %r3; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM60-NEXT: mov.b32 %r5, %r1; +; SM60-NEXT: @%p1 bra $L__BB18_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @nand_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: nand_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b64 %rd<7>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM60-NEXT: $L__BB19_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b64 %rd4, %rd6, %rd3; +; SM60-NEXT: not.b64 %rd5, %rd4; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM60-NEXT: setp.ne.b64 %p1, %rd1, %rd6; +; SM60-NEXT: mov.b64 %rd6, %rd1; +; SM60-NEXT: @%p1 bra $L__BB19_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @or_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: or_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<8>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [or_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r1, [or_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd2, %rd1, -4; +; SM60-NEXT: cvt.u32.u64 %r2, %rd1; +; SM60-NEXT: and.b32 %r3, %r2, 3; +; SM60-NEXT: shl.b32 %r4, %r3, 3; +; SM60-NEXT: shl.b32 %r5, %r1, %r4; +; SM60-NEXT: atom.cta.global.or.b32 %r6, [%rd2], %r5; +; SM60-NEXT: shr.u32 %r7, %r6, %r4; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r7; +; SM60-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @or_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: or_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<8>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [or_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b16 %r1, [or_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd2, %rd1, -4; +; SM60-NEXT: cvt.u32.u64 %r2, %rd1; +; SM60-NEXT: and.b32 %r3, %r2, 3; +; SM60-NEXT: shl.b32 %r4, %r3, 3; +; SM60-NEXT: shl.b32 %r5, %r1, %r4; +; SM60-NEXT: atom.cta.global.or.b32 %r6, [%rd2], %r5; +; SM60-NEXT: shr.u32 %r7, %r6, %r4; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r7; +; SM60-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @or_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: or_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [or_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [or_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.or.b32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @or_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: or_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [or_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [or_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.or.b64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @xor_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: xor_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<8>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r1, [xor_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd2, %rd1, -4; +; SM60-NEXT: cvt.u32.u64 %r2, %rd1; +; SM60-NEXT: and.b32 %r3, %r2, 3; +; SM60-NEXT: shl.b32 %r4, %r3, 3; +; SM60-NEXT: shl.b32 %r5, %r1, %r4; +; SM60-NEXT: atom.cta.global.xor.b32 %r6, [%rd2], %r5; +; SM60-NEXT: shr.u32 %r7, %r6, %r4; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r7; +; SM60-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @xor_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: xor_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<8>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b16 %r1, [xor_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd2, %rd1, -4; +; SM60-NEXT: cvt.u32.u64 %r2, %rd1; +; SM60-NEXT: and.b32 %r3, %r2, 3; +; SM60-NEXT: shl.b32 %r4, %r3, 3; +; SM60-NEXT: shl.b32 %r5, %r1, %r4; +; SM60-NEXT: atom.cta.global.xor.b32 %r6, [%rd2], %r5; +; SM60-NEXT: shr.u32 %r7, %r6, %r4; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r7; +; SM60-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @xor_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: xor_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [xor_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.xor.b32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @xor_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: xor_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [xor_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.xor.b64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @max_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: max_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<5>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b8 %rs1, [max_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [max_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 255; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: cvt.s16.s8 %rs3, %rs1; +; SM60-NEXT: $L__BB28_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r15, %r1; +; SM60-NEXT: cvt.s8.s32 %rs2, %r8; +; SM60-NEXT: max.s16 %rs4, %rs2, %rs3; +; SM60-NEXT: cvt.u32.u16 %r9, %rs4; +; SM60-NEXT: and.b32 %r10, %r9, 255; +; SM60-NEXT: shl.b32 %r11, %r10, %r1; +; SM60-NEXT: and.b32 %r12, %r15, %r2; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r15; +; SM60-NEXT: mov.b32 %r15, %r3; +; SM60-NEXT: @%p1 bra $L__BB28_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @max_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: max_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<4>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [max_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [max_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB29_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: max.s16 %rs3, %rs2, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs3; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB29_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @max_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: max_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [max_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [max_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.max.s32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @max_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: max_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [max_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [max_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.max.s64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @min_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: min_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<5>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b8 %rs1, [min_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [min_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 255; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: cvt.s16.s8 %rs3, %rs1; +; SM60-NEXT: $L__BB32_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r15, %r1; +; SM60-NEXT: cvt.s8.s32 %rs2, %r8; +; SM60-NEXT: min.s16 %rs4, %rs2, %rs3; +; SM60-NEXT: cvt.u32.u16 %r9, %rs4; +; SM60-NEXT: and.b32 %r10, %r9, 255; +; SM60-NEXT: shl.b32 %r11, %r10, %r1; +; SM60-NEXT: and.b32 %r12, %r15, %r2; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r15; +; SM60-NEXT: mov.b32 %r15, %r3; +; SM60-NEXT: @%p1 bra $L__BB32_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @min_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: min_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<4>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [min_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [min_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB33_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: min.s16 %rs3, %rs2, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs3; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB33_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @min_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: min_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.min.s32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @min_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: min_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [min_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [min_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.min.s64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @umax_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: umax_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<5>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b8 %rs1, [umax_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 255; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB36_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: and.b16 %rs3, %rs2, 255; +; SM60-NEXT: max.u16 %rs4, %rs3, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs4; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB36_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @umax_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: umax_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<4>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [umax_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB37_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: max.u16 %rs3, %rs2, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs3; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB37_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @umax_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: umax_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.max.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @umax_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: umax_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.max.u64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @umin_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: umin_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<5>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b8 %rs1, [umin_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 255; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB40_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: and.b16 %rs3, %rs2, 255; +; SM60-NEXT: min.u16 %rs4, %rs3, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs4; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB40_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @umin_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: umin_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<4>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [umin_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB41_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: min.u16 %rs3, %rs2, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs3; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB41_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @umin_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: umin_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [umin_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [umin_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.min.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @umin_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: umin_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [umin_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.min.u64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @uinc_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: uinc_wrap_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b16 %rs<6>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b8 %rs1, [uinc_wrap_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 255; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB44_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r15, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: and.b16 %rs3, %rs2, 255; +; SM60-NEXT: add.s16 %rs4, %rs2, 1; +; SM60-NEXT: setp.ge.u16 %p1, %rs3, %rs1; +; SM60-NEXT: selp.b16 %rs5, 0, %rs4, %p1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs5; +; SM60-NEXT: and.b32 %r10, %r9, 255; +; SM60-NEXT: shl.b32 %r11, %r10, %r1; +; SM60-NEXT: and.b32 %r12, %r15, %r2; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p2, %r3, %r15; +; SM60-NEXT: mov.b32 %r15, %r3; +; SM60-NEXT: @%p2 bra $L__BB44_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @uinc_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: uinc_wrap_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b16 %rs<5>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [uinc_wrap_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB45_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: add.s16 %rs3, %rs2, 1; +; SM60-NEXT: setp.ge.u16 %p1, %rs2, %rs1; +; SM60-NEXT: selp.b16 %rs4, 0, %rs3, %p1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs4; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p2, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p2 bra $L__BB45_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @uinc_wrap_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: uinc_wrap_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [uinc_wrap_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [uinc_wrap_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.inc.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @uinc_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: uinc_wrap_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b64 %rd<7>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [uinc_wrap_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM60-NEXT: $L__BB47_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: add.s64 %rd4, %rd6, 1; +; SM60-NEXT: setp.ge.u64 %p1, %rd6, %rd3; +; SM60-NEXT: selp.b64 %rd5, 0, %rd4, %p1; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM60-NEXT: setp.ne.b64 %p2, %rd1, %rd6; +; SM60-NEXT: mov.b64 %rd6, %rd1; +; SM60-NEXT: @%p2 bra $L__BB47_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @udec_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: udec_wrap_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<4>; +; SM60-NEXT: .reg .b16 %rs<7>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b8 %rs1, [udec_wrap_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 255; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB48_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r15, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: and.b16 %rs3, %rs2, 255; +; SM60-NEXT: add.s16 %rs4, %rs2, -1; +; SM60-NEXT: setp.eq.b16 %p1, %rs3, 0; +; SM60-NEXT: setp.gt.u16 %p2, %rs3, %rs1; +; SM60-NEXT: selp.b16 %rs5, %rs1, %rs4, %p2; +; SM60-NEXT: selp.b16 %rs6, %rs1, %rs5, %p1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs6; +; SM60-NEXT: and.b32 %r10, %r9, 255; +; SM60-NEXT: shl.b32 %r11, %r10, %r1; +; SM60-NEXT: and.b32 %r12, %r15, %r2; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p3, %r3, %r15; +; SM60-NEXT: mov.b32 %r15, %r3; +; SM60-NEXT: @%p3 bra $L__BB48_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @udec_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: udec_wrap_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<4>; +; SM60-NEXT: .reg .b16 %rs<6>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [udec_wrap_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB49_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: add.s16 %rs3, %rs2, -1; +; SM60-NEXT: setp.eq.b16 %p1, %rs2, 0; +; SM60-NEXT: setp.gt.u16 %p2, %rs2, %rs1; +; SM60-NEXT: selp.b16 %rs4, %rs1, %rs3, %p2; +; SM60-NEXT: selp.b16 %rs5, %rs1, %rs4, %p1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs5; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p3, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p3 bra $L__BB49_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @udec_wrap_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: udec_wrap_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [udec_wrap_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [udec_wrap_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.dec.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @udec_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: udec_wrap_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<4>; +; SM60-NEXT: .reg .b64 %rd<8>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [udec_wrap_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd7, [%rd2]; +; SM60-NEXT: $L__BB51_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: add.s64 %rd4, %rd7, -1; +; SM60-NEXT: setp.eq.b64 %p1, %rd7, 0; +; SM60-NEXT: setp.gt.u64 %p2, %rd7, %rd3; +; SM60-NEXT: selp.b64 %rd5, %rd3, %rd4, %p2; +; SM60-NEXT: selp.b64 %rd6, %rd3, %rd5, %p1; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd7, %rd6; +; SM60-NEXT: setp.ne.b64 %p3, %rd1, %rd7; +; SM60-NEXT: mov.b64 %rd7, %rd1; +; SM60-NEXT: @%p3 bra $L__BB51_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @usub_cond_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: usub_cond_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b16 %rs<6>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b8 %rs1, [usub_cond_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 255; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB52_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r15, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: and.b16 %rs3, %rs2, 255; +; SM60-NEXT: setp.ge.u16 %p1, %rs3, %rs1; +; SM60-NEXT: sub.s16 %rs4, %rs2, %rs1; +; SM60-NEXT: selp.b16 %rs5, %rs4, %rs2, %p1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs5; +; SM60-NEXT: and.b32 %r10, %r9, 255; +; SM60-NEXT: shl.b32 %r11, %r10, %r1; +; SM60-NEXT: and.b32 %r12, %r15, %r2; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p2, %r3, %r15; +; SM60-NEXT: mov.b32 %r15, %r3; +; SM60-NEXT: @%p2 bra $L__BB52_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @usub_cond_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: usub_cond_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b16 %rs<5>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [usub_cond_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB53_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: setp.ge.u16 %p1, %rs2, %rs1; +; SM60-NEXT: sub.s16 %rs3, %rs2, %rs1; +; SM60-NEXT: selp.b16 %rs4, %rs3, %rs2, %p1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs4; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p2, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p2 bra $L__BB53_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @usub_cond_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: usub_cond_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b32 %r<6>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [usub_cond_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [usub_cond_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r5, [%rd1]; +; SM60-NEXT: $L__BB54_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: setp.ge.u32 %p1, %r5, %r2; +; SM60-NEXT: sub.s32 %r3, %r5, %r2; +; SM60-NEXT: selp.b32 %r4, %r3, %r5, %p1; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM60-NEXT: setp.ne.b32 %p2, %r1, %r5; +; SM60-NEXT: mov.b32 %r5, %r1; +; SM60-NEXT: @%p2 bra $L__BB54_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @usub_cond_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: usub_cond_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b64 %rd<7>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [usub_cond_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM60-NEXT: $L__BB55_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: setp.ge.u64 %p1, %rd6, %rd3; +; SM60-NEXT: sub.s64 %rd4, %rd6, %rd3; +; SM60-NEXT: selp.b64 %rd5, %rd4, %rd6, %p1; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM60-NEXT: setp.ne.b64 %p2, %rd1, %rd6; +; SM60-NEXT: mov.b64 %rd6, %rd1; +; SM60-NEXT: @%p2 bra $L__BB55_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @usub_sat_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: usub_sat_acq_rel_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<6>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b8 %rs1, [usub_sat_acq_rel_i8_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 255; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB56_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: and.b16 %rs3, %rs2, 255; +; SM60-NEXT: max.u16 %rs4, %rs3, %rs1; +; SM60-NEXT: sub.s16 %rs5, %rs4, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs5; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB56_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @usub_sat_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM60-LABEL: usub_sat_acq_rel_i16_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<5>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [usub_sat_acq_rel_i16_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i16_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB57_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: max.u16 %rs3, %rs2, %rs1; +; SM60-NEXT: sub.s16 %rs4, %rs3, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs4; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB57_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @usub_sat_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: usub_sat_acq_rel_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<6>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [usub_sat_acq_rel_i32_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [usub_sat_acq_rel_i32_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r5, [%rd1]; +; SM60-NEXT: $L__BB58_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: max.u32 %r3, %r5, %r2; +; SM60-NEXT: sub.s32 %r4, %r3, %r2; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM60-NEXT: mov.b32 %r5, %r1; +; SM60-NEXT: @%p1 bra $L__BB58_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @usub_sat_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM60-LABEL: usub_sat_acq_rel_i64_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b64 %rd<7>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [usub_sat_acq_rel_i64_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i64_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM60-NEXT: $L__BB59_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: max.u64 %rd4, %rd6, %rd3; +; SM60-NEXT: sub.s64 %rd5, %rd4, %rd3; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM60-NEXT: setp.ne.b64 %p1, %rd1, %rd6; +; SM60-NEXT: mov.b64 %rd6, %rd1; +; SM60-NEXT: @%p1 bra $L__BB59_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define float @fadd_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM60-LABEL: fadd_acq_rel_float_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.add.f32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM60-LABEL: fsub_acq_rel_float_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<5>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [fsub_acq_rel_float_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r4, [%rd1]; +; SM60-NEXT: $L__BB61_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: sub.rn.f32 %r3, %r4, %r2; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM60-NEXT: mov.b32 %r4, %r1; +; SM60-NEXT: @%p1 bra $L__BB61_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM60-LABEL: fmin_acq_rel_float_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<5>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [fmin_acq_rel_float_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r4, [%rd1]; +; SM60-NEXT: $L__BB62_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: min.f32 %r3, %r4, %r2; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM60-NEXT: mov.b32 %r4, %r1; +; SM60-NEXT: @%p1 bra $L__BB62_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM60-LABEL: fmax_acq_rel_float_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<5>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [fmax_acq_rel_float_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r4, [%rd1]; +; SM60-NEXT: $L__BB63_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: max.f32 %r3, %r4, %r2; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM60-NEXT: mov.b32 %r4, %r1; +; SM60-NEXT: @%p1 bra $L__BB63_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM60-LABEL: fminimum_acq_rel_float_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<6>; +; SM60-NEXT: .reg .b32 %r<9>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r8, [%rd1]; +; SM60-NEXT: setp.eq.b32 %p3, %r2, -2147483648; +; SM60-NEXT: $L__BB64_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: setp.nan.f32 %p1, %r8, %r2; +; SM60-NEXT: min.f32 %r3, %r8, %r2; +; SM60-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1; +; SM60-NEXT: setp.eq.b32 %p2, %r8, -2147483648; +; SM60-NEXT: selp.f32 %r5, %r8, %r4, %p2; +; SM60-NEXT: selp.f32 %r6, %r2, %r5, %p3; +; SM60-NEXT: setp.eq.f32 %p4, %r4, 0f00000000; +; SM60-NEXT: selp.f32 %r7, %r6, %r4, %p4; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r8, %r7; +; SM60-NEXT: setp.ne.b32 %p5, %r1, %r8; +; SM60-NEXT: mov.b32 %r8, %r1; +; SM60-NEXT: @%p5 bra $L__BB64_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM60-LABEL: fmaximum_acq_rel_float_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<6>; +; SM60-NEXT: .reg .b32 %r<9>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r8, [%rd1]; +; SM60-NEXT: setp.eq.b32 %p3, %r2, 0; +; SM60-NEXT: $L__BB65_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: setp.nan.f32 %p1, %r8, %r2; +; SM60-NEXT: max.f32 %r3, %r8, %r2; +; SM60-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1; +; SM60-NEXT: setp.eq.b32 %p2, %r8, 0; +; SM60-NEXT: selp.f32 %r5, %r8, %r4, %p2; +; SM60-NEXT: selp.f32 %r6, %r2, %r5, %p3; +; SM60-NEXT: setp.eq.f32 %p4, %r4, 0f00000000; +; SM60-NEXT: selp.f32 %r7, %r6, %r4, %p4; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r8, %r7; +; SM60-NEXT: setp.ne.b32 %p5, %r1, %r8; +; SM60-NEXT: mov.b32 %r8, %r1; +; SM60-NEXT: @%p5 bra $L__BB65_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define double @fadd_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM60-LABEL: fadd_acq_rel_double_global_cta( +; SM60: { +; SM60-NEXT: .reg .b64 %rd<4>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_global_cta_param_0]; +; SM60-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.add.f64 %rd3, [%rd1], %rd2; +; SM60-NEXT: st.param.b64 [func_retval0], %rd3; +; SM60-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fsub_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM60-LABEL: fsub_acq_rel_double_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b64 %rd<6>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [fsub_acq_rel_double_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_double_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM60-NEXT: $L__BB67_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: sub.rn.f64 %rd4, %rd5, %rd3; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM60-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM60-NEXT: mov.b64 %rd5, %rd1; +; SM60-NEXT: @%p1 bra $L__BB67_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmin_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM60-LABEL: fmin_acq_rel_double_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b64 %rd<6>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [fmin_acq_rel_double_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_double_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM60-NEXT: $L__BB68_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: min.f64 %rd4, %rd5, %rd3; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM60-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM60-NEXT: mov.b64 %rd5, %rd1; +; SM60-NEXT: @%p1 bra $L__BB68_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmax_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM60-LABEL: fmax_acq_rel_double_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b64 %rd<6>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [fmax_acq_rel_double_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_double_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM60-NEXT: $L__BB69_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: max.f64 %rd4, %rd5, %rd3; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM60-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM60-NEXT: mov.b64 %rd5, %rd1; +; SM60-NEXT: @%p1 bra $L__BB69_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM60-LABEL: fminimum_acq_rel_double_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<6>; +; SM60-NEXT: .reg .b64 %rd<10>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [fminimum_acq_rel_double_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_double_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd9, [%rd2]; +; SM60-NEXT: setp.eq.b64 %p3, %rd3, -9223372036854775808; +; SM60-NEXT: $L__BB70_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: setp.nan.f64 %p1, %rd9, %rd3; +; SM60-NEXT: min.f64 %rd4, %rd9, %rd3; +; SM60-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1; +; SM60-NEXT: setp.eq.b64 %p2, %rd9, -9223372036854775808; +; SM60-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2; +; SM60-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3; +; SM60-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000; +; SM60-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8; +; SM60-NEXT: setp.ne.b64 %p5, %rd1, %rd9; +; SM60-NEXT: mov.b64 %rd9, %rd1; +; SM60-NEXT: @%p5 bra $L__BB70_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmaximum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM60-LABEL: fmaximum_acq_rel_double_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<6>; +; SM60-NEXT: .reg .b64 %rd<10>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd3, [fmaximum_acq_rel_double_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_double_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b64 %rd9, [%rd2]; +; SM60-NEXT: setp.eq.b64 %p3, %rd3, 0; +; SM60-NEXT: $L__BB71_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: setp.nan.f64 %p1, %rd9, %rd3; +; SM60-NEXT: max.f64 %rd4, %rd9, %rd3; +; SM60-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1; +; SM60-NEXT: setp.eq.b64 %p2, %rd9, 0; +; SM60-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2; +; SM60-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3; +; SM60-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000; +; SM60-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4; +; SM60-NEXT: atom.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8; +; SM60-NEXT: setp.ne.b64 %p5, %rd1, %rd9; +; SM60-NEXT: mov.b64 %rd9, %rd1; +; SM60-NEXT: @%p5 bra $L__BB71_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b64 [func_retval0], %rd1; +; SM60-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define half @fadd_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM60-LABEL: fadd_acq_rel_half_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<4>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_half_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB72_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: add.rn.f16 %rs3, %rs2, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs3; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB72_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM60-LABEL: fsub_acq_rel_half_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<4>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: $L__BB73_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: sub.rn.f16 %rs3, %rs2, %rs1; +; SM60-NEXT: cvt.u32.u16 %r9, %rs3; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p1 bra $L__BB73_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM60-LABEL: fmin_acq_rel_half_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<4>; +; SM60-NEXT: .reg .b32 %r<18>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r17, [%rd1]; +; SM60-NEXT: cvt.f32.f16 %r10, %rs1; +; SM60-NEXT: $L__BB74_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r17, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: cvt.f32.f16 %r9, %rs2; +; SM60-NEXT: min.f32 %r11, %r9, %r10; +; SM60-NEXT: cvt.rn.f16.f32 %rs3, %r11; +; SM60-NEXT: cvt.u32.u16 %r12, %rs3; +; SM60-NEXT: shl.b32 %r13, %r12, %r1; +; SM60-NEXT: and.b32 %r14, %r17, %r2; +; SM60-NEXT: or.b32 %r15, %r14, %r13; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r17, %r15; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r17; +; SM60-NEXT: mov.b32 %r17, %r3; +; SM60-NEXT: @%p1 bra $L__BB74_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r16, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r16; +; SM60-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM60-LABEL: fmax_acq_rel_half_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b16 %rs<4>; +; SM60-NEXT: .reg .b32 %r<18>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r17, [%rd1]; +; SM60-NEXT: cvt.f32.f16 %r10, %rs1; +; SM60-NEXT: $L__BB75_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r17, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: cvt.f32.f16 %r9, %rs2; +; SM60-NEXT: max.f32 %r11, %r9, %r10; +; SM60-NEXT: cvt.rn.f16.f32 %rs3, %r11; +; SM60-NEXT: cvt.u32.u16 %r12, %rs3; +; SM60-NEXT: shl.b32 %r13, %r12, %r1; +; SM60-NEXT: and.b32 %r14, %r17, %r2; +; SM60-NEXT: or.b32 %r15, %r14, %r13; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r17, %r15; +; SM60-NEXT: setp.ne.b32 %p1, %r3, %r17; +; SM60-NEXT: mov.b32 %r17, %r3; +; SM60-NEXT: @%p1 bra $L__BB75_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r16, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r16; +; SM60-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM60-LABEL: fminimum_acq_rel_half_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<7>; +; SM60-NEXT: .reg .b16 %rs<9>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: setp.eq.b16 %p4, %rs1, -32768; +; SM60-NEXT: $L__BB76_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: setp.lt.f16 %p1, %rs2, %rs1; +; SM60-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1; +; SM60-NEXT: setp.nan.f16 %p2, %rs2, %rs1; +; SM60-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2; +; SM60-NEXT: setp.eq.b16 %p3, %rs2, -32768; +; SM60-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3; +; SM60-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4; +; SM60-NEXT: mov.b16 %rs7, 0x0000; +; SM60-NEXT: setp.eq.f16 %p5, %rs4, %rs7; +; SM60-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5; +; SM60-NEXT: cvt.u32.u16 %r9, %rs8; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p6, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p6 bra $L__BB76_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM60-LABEL: fmaximum_acq_rel_half_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<7>; +; SM60-NEXT: .reg .b16 %rs<9>; +; SM60-NEXT: .reg .b32 %r<15>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r14, [%rd1]; +; SM60-NEXT: setp.eq.b16 %p4, %rs1, 0; +; SM60-NEXT: $L__BB77_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r14, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: setp.gt.f16 %p1, %rs2, %rs1; +; SM60-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1; +; SM60-NEXT: setp.nan.f16 %p2, %rs2, %rs1; +; SM60-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2; +; SM60-NEXT: setp.eq.b16 %p3, %rs2, 0; +; SM60-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3; +; SM60-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4; +; SM60-NEXT: mov.b16 %rs7, 0x0000; +; SM60-NEXT: setp.eq.f16 %p5, %rs4, %rs7; +; SM60-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5; +; SM60-NEXT: cvt.u32.u16 %r9, %rs8; +; SM60-NEXT: shl.b32 %r10, %r9, %r1; +; SM60-NEXT: and.b32 %r11, %r14, %r2; +; SM60-NEXT: or.b32 %r12, %r11, %r10; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM60-NEXT: setp.ne.b32 %p6, %r3, %r14; +; SM60-NEXT: mov.b32 %r14, %r3; +; SM60-NEXT: @%p6 bra $L__BB77_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r13, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r13; +; SM60-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define bfloat @fadd_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM60-LABEL: fadd_acq_rel_bfloat_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b16 %rs<2>; +; SM60-NEXT: .reg .b32 %r<24>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_bfloat_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_bfloat_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r23, [%rd1]; +; SM60-NEXT: cvt.u32.u16 %r10, %rs1; +; SM60-NEXT: shl.b32 %r11, %r10, 16; +; SM60-NEXT: $L__BB78_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r23, %r1; +; SM60-NEXT: shl.b32 %r9, %r8, 16; +; SM60-NEXT: add.rn.f32 %r12, %r9, %r11; +; SM60-NEXT: bfe.u32 %r13, %r12, 16, 1; +; SM60-NEXT: add.s32 %r14, %r13, %r12; +; SM60-NEXT: add.s32 %r15, %r14, 32767; +; SM60-NEXT: setp.nan.f32 %p1, %r12, %r12; +; SM60-NEXT: or.b32 %r16, %r12, 4194304; +; SM60-NEXT: selp.b32 %r17, %r16, %r15, %p1; +; SM60-NEXT: shr.u32 %r18, %r17, 16; +; SM60-NEXT: shl.b32 %r19, %r18, %r1; +; SM60-NEXT: and.b32 %r20, %r23, %r2; +; SM60-NEXT: or.b32 %r21, %r20, %r19; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r23, %r21; +; SM60-NEXT: setp.ne.b32 %p2, %r3, %r23; +; SM60-NEXT: mov.b32 %r23, %r3; +; SM60-NEXT: @%p2 bra $L__BB78_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r22, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r22; +; SM60-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fsub_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM60-LABEL: fsub_acq_rel_bfloat_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b16 %rs<2>; +; SM60-NEXT: .reg .b32 %r<24>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_bfloat_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_bfloat_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r23, [%rd1]; +; SM60-NEXT: cvt.u32.u16 %r10, %rs1; +; SM60-NEXT: shl.b32 %r11, %r10, 16; +; SM60-NEXT: $L__BB79_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r23, %r1; +; SM60-NEXT: shl.b32 %r9, %r8, 16; +; SM60-NEXT: sub.rn.f32 %r12, %r9, %r11; +; SM60-NEXT: bfe.u32 %r13, %r12, 16, 1; +; SM60-NEXT: add.s32 %r14, %r13, %r12; +; SM60-NEXT: add.s32 %r15, %r14, 32767; +; SM60-NEXT: setp.nan.f32 %p1, %r12, %r12; +; SM60-NEXT: or.b32 %r16, %r12, 4194304; +; SM60-NEXT: selp.b32 %r17, %r16, %r15, %p1; +; SM60-NEXT: shr.u32 %r18, %r17, 16; +; SM60-NEXT: shl.b32 %r19, %r18, %r1; +; SM60-NEXT: and.b32 %r20, %r23, %r2; +; SM60-NEXT: or.b32 %r21, %r20, %r19; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r23, %r21; +; SM60-NEXT: setp.ne.b32 %p2, %r3, %r23; +; SM60-NEXT: mov.b32 %r23, %r3; +; SM60-NEXT: @%p2 bra $L__BB79_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r22, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r22; +; SM60-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmin_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM60-LABEL: fmin_acq_rel_bfloat_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b16 %rs<2>; +; SM60-NEXT: .reg .b32 %r<24>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_bfloat_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_bfloat_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r23, [%rd1]; +; SM60-NEXT: cvt.u32.u16 %r10, %rs1; +; SM60-NEXT: shl.b32 %r11, %r10, 16; +; SM60-NEXT: $L__BB80_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r23, %r1; +; SM60-NEXT: shl.b32 %r9, %r8, 16; +; SM60-NEXT: min.f32 %r12, %r9, %r11; +; SM60-NEXT: bfe.u32 %r13, %r12, 16, 1; +; SM60-NEXT: add.s32 %r14, %r13, %r12; +; SM60-NEXT: add.s32 %r15, %r14, 32767; +; SM60-NEXT: setp.nan.f32 %p1, %r12, %r12; +; SM60-NEXT: or.b32 %r16, %r12, 4194304; +; SM60-NEXT: selp.b32 %r17, %r16, %r15, %p1; +; SM60-NEXT: shr.u32 %r18, %r17, 16; +; SM60-NEXT: shl.b32 %r19, %r18, %r1; +; SM60-NEXT: and.b32 %r20, %r23, %r2; +; SM60-NEXT: or.b32 %r21, %r20, %r19; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r23, %r21; +; SM60-NEXT: setp.ne.b32 %p2, %r3, %r23; +; SM60-NEXT: mov.b32 %r23, %r3; +; SM60-NEXT: @%p2 bra $L__BB80_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r22, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r22; +; SM60-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmax_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM60-LABEL: fmax_acq_rel_bfloat_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<3>; +; SM60-NEXT: .reg .b16 %rs<2>; +; SM60-NEXT: .reg .b32 %r<24>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_bfloat_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_bfloat_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r23, [%rd1]; +; SM60-NEXT: cvt.u32.u16 %r10, %rs1; +; SM60-NEXT: shl.b32 %r11, %r10, 16; +; SM60-NEXT: $L__BB81_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r23, %r1; +; SM60-NEXT: shl.b32 %r9, %r8, 16; +; SM60-NEXT: max.f32 %r12, %r9, %r11; +; SM60-NEXT: bfe.u32 %r13, %r12, 16, 1; +; SM60-NEXT: add.s32 %r14, %r13, %r12; +; SM60-NEXT: add.s32 %r15, %r14, 32767; +; SM60-NEXT: setp.nan.f32 %p1, %r12, %r12; +; SM60-NEXT: or.b32 %r16, %r12, 4194304; +; SM60-NEXT: selp.b32 %r17, %r16, %r15, %p1; +; SM60-NEXT: shr.u32 %r18, %r17, 16; +; SM60-NEXT: shl.b32 %r19, %r18, %r1; +; SM60-NEXT: and.b32 %r20, %r23, %r2; +; SM60-NEXT: or.b32 %r21, %r20, %r19; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r23, %r21; +; SM60-NEXT: setp.ne.b32 %p2, %r3, %r23; +; SM60-NEXT: mov.b32 %r23, %r3; +; SM60-NEXT: @%p2 bra $L__BB81_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r22, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r22; +; SM60-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM60-LABEL: fminimum_acq_rel_bfloat_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<7>; +; SM60-NEXT: .reg .b16 %rs<8>; +; SM60-NEXT: .reg .b32 %r<20>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_bfloat_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_bfloat_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r19, [%rd1]; +; SM60-NEXT: cvt.u32.u16 %r10, %rs1; +; SM60-NEXT: shl.b32 %r11, %r10, 16; +; SM60-NEXT: setp.eq.b16 %p4, %rs1, -32768; +; SM60-NEXT: $L__BB82_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r19, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: shl.b32 %r9, %r8, 16; +; SM60-NEXT: setp.lt.f32 %p1, %r9, %r11; +; SM60-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1; +; SM60-NEXT: setp.nan.f32 %p2, %r9, %r11; +; SM60-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2; +; SM60-NEXT: setp.eq.b16 %p3, %rs2, -32768; +; SM60-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3; +; SM60-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4; +; SM60-NEXT: cvt.u32.u16 %r12, %rs4; +; SM60-NEXT: shl.b32 %r13, %r12, 16; +; SM60-NEXT: setp.eq.f32 %p5, %r13, 0f00000000; +; SM60-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5; +; SM60-NEXT: cvt.u32.u16 %r14, %rs7; +; SM60-NEXT: shl.b32 %r15, %r14, %r1; +; SM60-NEXT: and.b32 %r16, %r19, %r2; +; SM60-NEXT: or.b32 %r17, %r16, %r15; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r19, %r17; +; SM60-NEXT: setp.ne.b32 %p6, %r3, %r19; +; SM60-NEXT: mov.b32 %r19, %r3; +; SM60-NEXT: @%p6 bra $L__BB82_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r18, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r18; +; SM60-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM60-LABEL: fmaximum_acq_rel_bfloat_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<7>; +; SM60-NEXT: .reg .b16 %rs<8>; +; SM60-NEXT: .reg .b32 %r<20>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_bfloat_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_bfloat_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r4, %rd2; +; SM60-NEXT: and.b32 %r5, %r4, 3; +; SM60-NEXT: shl.b32 %r1, %r5, 3; +; SM60-NEXT: mov.b32 %r6, 65535; +; SM60-NEXT: shl.b32 %r7, %r6, %r1; +; SM60-NEXT: not.b32 %r2, %r7; +; SM60-NEXT: ld.global.b32 %r19, [%rd1]; +; SM60-NEXT: cvt.u32.u16 %r10, %rs1; +; SM60-NEXT: shl.b32 %r11, %r10, 16; +; SM60-NEXT: setp.eq.b16 %p4, %rs1, 0; +; SM60-NEXT: $L__BB83_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: shr.u32 %r8, %r19, %r1; +; SM60-NEXT: cvt.u16.u32 %rs2, %r8; +; SM60-NEXT: shl.b32 %r9, %r8, 16; +; SM60-NEXT: setp.gt.f32 %p1, %r9, %r11; +; SM60-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1; +; SM60-NEXT: setp.nan.f32 %p2, %r9, %r11; +; SM60-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2; +; SM60-NEXT: setp.eq.b16 %p3, %rs2, 0; +; SM60-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3; +; SM60-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4; +; SM60-NEXT: cvt.u32.u16 %r12, %rs4; +; SM60-NEXT: shl.b32 %r13, %r12, 16; +; SM60-NEXT: setp.eq.f32 %p5, %r13, 0f00000000; +; SM60-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5; +; SM60-NEXT: cvt.u32.u16 %r14, %rs7; +; SM60-NEXT: shl.b32 %r15, %r14, %r1; +; SM60-NEXT: and.b32 %r16, %r19, %r2; +; SM60-NEXT: or.b32 %r17, %r16, %r15; +; SM60-NEXT: atom.cta.global.cas.b32 %r3, [%rd1], %r19, %r17; +; SM60-NEXT: setp.ne.b32 %p6, %r3, %r19; +; SM60-NEXT: mov.b32 %r19, %r3; +; SM60-NEXT: @%p6 bra $L__BB83_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r18, %r3, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b16 [func_retval0], %r18; +; SM60-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define i8 @add_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: add_monotonic_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [add_monotonic_i8_global_cta_param_0]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: ld.param.b8 %r6, [add_monotonic_i8_global_cta_param_1]; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB84_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: add.s32 %r10, %r15, %r4; +; SM60-NEXT: and.b32 %r11, %r10, %r2; +; SM60-NEXT: and.b32 %r12, %r15, %r3; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM60-NEXT: mov.b32 %r15, %r5; +; SM60-NEXT: @%p1 bra $L__BB84_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r5, %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") monotonic + ret i8 %retval +} + +define i8 @add_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: add_acquire_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [add_acquire_i8_global_cta_param_0]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: ld.param.b8 %r6, [add_acquire_i8_global_cta_param_1]; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB85_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: add.s32 %r10, %r15, %r4; +; SM60-NEXT: and.b32 %r11, %r10, %r2; +; SM60-NEXT: and.b32 %r12, %r15, %r3; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM60-NEXT: mov.b32 %r15, %r5; +; SM60-NEXT: @%p1 bra $L__BB85_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") acquire + ret i8 %retval +} + +define i8 @add_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: add_release_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [add_release_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r6, [add_release_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB86_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: add.s32 %r10, %r15, %r4; +; SM60-NEXT: and.b32 %r11, %r10, %r2; +; SM60-NEXT: and.b32 %r12, %r15, %r3; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM60-NEXT: mov.b32 %r15, %r5; +; SM60-NEXT: @%p1 bra $L__BB86_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r5, %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") release + ret i8 %retval +} + +define i8 @add_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: add_seq_cst_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<16>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [add_seq_cst_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r6, [add_seq_cst_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r15, [%rd1]; +; SM60-NEXT: $L__BB87_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: add.s32 %r10, %r15, %r4; +; SM60-NEXT: and.b32 %r11, %r10, %r2; +; SM60-NEXT: and.b32 %r12, %r15, %r3; +; SM60-NEXT: or.b32 %r13, %r12, %r11; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM60-NEXT: mov.b32 %r15, %r5; +; SM60-NEXT: @%p1 bra $L__BB87_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r14, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r14; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") seq_cst + ret i8 %retval +} + +define i32 @add_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: add_monotonic_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [add_monotonic_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [add_monotonic_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.add.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") monotonic + ret i32 %retval +} + +define i32 @add_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: add_acquire_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [add_acquire_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [add_acquire_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.add.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") acquire + ret i32 %retval +} + +define i32 @add_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: add_release_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [add_release_i32_global_cta_param_0]; +; SM60-NEXT: ld.param.b32 %r1, [add_release_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.add.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") release + ret i32 %retval +} + +define i32 @add_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: add_seq_cst_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .b32 %r<3>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd1, [add_seq_cst_i32_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b32 %r1, [add_seq_cst_i32_global_cta_param_1]; +; SM60-NEXT: atom.cta.global.add.u32 %r2, [%rd1], %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r2; +; SM60-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") seq_cst + ret i32 %retval +} + +define i8 @nand_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: nand_monotonic_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<17>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [nand_monotonic_i8_global_cta_param_0]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: ld.param.b8 %r6, [nand_monotonic_i8_global_cta_param_1]; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r16, [%rd1]; +; SM60-NEXT: $L__BB92_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r10, %r16, %r4; +; SM60-NEXT: not.b32 %r11, %r10; +; SM60-NEXT: and.b32 %r12, %r11, %r2; +; SM60-NEXT: and.b32 %r13, %r16, %r3; +; SM60-NEXT: or.b32 %r14, %r13, %r12; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM60-NEXT: mov.b32 %r16, %r5; +; SM60-NEXT: @%p1 bra $L__BB92_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r15, %r5, %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r15; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") monotonic + ret i8 %retval +} + +define i8 @nand_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: nand_acquire_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<17>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [nand_acquire_i8_global_cta_param_0]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: ld.param.b8 %r6, [nand_acquire_i8_global_cta_param_1]; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r16, [%rd1]; +; SM60-NEXT: $L__BB93_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r10, %r16, %r4; +; SM60-NEXT: not.b32 %r11, %r10; +; SM60-NEXT: and.b32 %r12, %r11, %r2; +; SM60-NEXT: and.b32 %r13, %r16, %r3; +; SM60-NEXT: or.b32 %r14, %r13, %r12; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM60-NEXT: mov.b32 %r16, %r5; +; SM60-NEXT: @%p1 bra $L__BB93_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r15, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r15; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") acquire + ret i8 %retval +} + +define i8 @nand_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: nand_release_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<17>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [nand_release_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r6, [nand_release_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r16, [%rd1]; +; SM60-NEXT: $L__BB94_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r10, %r16, %r4; +; SM60-NEXT: not.b32 %r11, %r10; +; SM60-NEXT: and.b32 %r12, %r11, %r2; +; SM60-NEXT: and.b32 %r13, %r16, %r3; +; SM60-NEXT: or.b32 %r14, %r13, %r12; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM60-NEXT: mov.b32 %r16, %r5; +; SM60-NEXT: @%p1 bra $L__BB94_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r15, %r5, %r1; +; SM60-NEXT: st.param.b32 [func_retval0], %r15; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") release + ret i8 %retval +} + +define i8 @nand_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM60-LABEL: nand_seq_cst_i8_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<17>; +; SM60-NEXT: .reg .b64 %rd<3>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b64 %rd2, [nand_seq_cst_i8_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.param.b8 %r6, [nand_seq_cst_i8_global_cta_param_1]; +; SM60-NEXT: and.b64 %rd1, %rd2, -4; +; SM60-NEXT: cvt.u32.u64 %r7, %rd2; +; SM60-NEXT: and.b32 %r8, %r7, 3; +; SM60-NEXT: shl.b32 %r1, %r8, 3; +; SM60-NEXT: mov.b32 %r9, 255; +; SM60-NEXT: shl.b32 %r2, %r9, %r1; +; SM60-NEXT: not.b32 %r3, %r2; +; SM60-NEXT: shl.b32 %r4, %r6, %r1; +; SM60-NEXT: ld.global.b32 %r16, [%rd1]; +; SM60-NEXT: $L__BB95_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r10, %r16, %r4; +; SM60-NEXT: not.b32 %r11, %r10; +; SM60-NEXT: and.b32 %r12, %r11, %r2; +; SM60-NEXT: and.b32 %r13, %r16, %r3; +; SM60-NEXT: or.b32 %r14, %r13, %r12; +; SM60-NEXT: atom.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM60-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM60-NEXT: mov.b32 %r16, %r5; +; SM60-NEXT: @%p1 bra $L__BB95_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: shr.u32 %r15, %r5, %r1; +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r15; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") seq_cst + ret i8 %retval +} + +define i32 @nand_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: nand_monotonic_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<6>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [nand_monotonic_i32_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [nand_monotonic_i32_global_cta_param_0]; +; SM60-NEXT: ld.global.b32 %r5, [%rd1]; +; SM60-NEXT: $L__BB96_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r3, %r5, %r2; +; SM60-NEXT: not.b32 %r4, %r3; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM60-NEXT: mov.b32 %r5, %r1; +; SM60-NEXT: @%p1 bra $L__BB96_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") monotonic + ret i32 %retval +} + +define i32 @nand_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: nand_acquire_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<6>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [nand_acquire_i32_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [nand_acquire_i32_global_cta_param_0]; +; SM60-NEXT: ld.global.b32 %r5, [%rd1]; +; SM60-NEXT: $L__BB97_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r3, %r5, %r2; +; SM60-NEXT: not.b32 %r4, %r3; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM60-NEXT: mov.b32 %r5, %r1; +; SM60-NEXT: @%p1 bra $L__BB97_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") acquire + ret i32 %retval +} + +define i32 @nand_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: nand_release_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<6>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [nand_release_i32_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [nand_release_i32_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r5, [%rd1]; +; SM60-NEXT: $L__BB98_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r3, %r5, %r2; +; SM60-NEXT: not.b32 %r4, %r3; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM60-NEXT: mov.b32 %r5, %r1; +; SM60-NEXT: @%p1 bra $L__BB98_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") release + ret i32 %retval +} + +define i32 @nand_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM60-LABEL: nand_seq_cst_i32_global_cta( +; SM60: { +; SM60-NEXT: .reg .pred %p<2>; +; SM60-NEXT: .reg .b32 %r<6>; +; SM60-NEXT: .reg .b64 %rd<2>; +; SM60-EMPTY: +; SM60-NEXT: // %bb.0: +; SM60-NEXT: ld.param.b32 %r2, [nand_seq_cst_i32_global_cta_param_1]; +; SM60-NEXT: ld.param.b64 %rd1, [nand_seq_cst_i32_global_cta_param_0]; +; SM60-NEXT: membar.cta; +; SM60-NEXT: ld.global.b32 %r5, [%rd1]; +; SM60-NEXT: $L__BB99_1: // %atomicrmw.start +; SM60-NEXT: // =>This Inner Loop Header: Depth=1 +; SM60-NEXT: and.b32 %r3, %r5, %r2; +; SM60-NEXT: not.b32 %r4, %r3; +; SM60-NEXT: atom.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM60-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM60-NEXT: mov.b32 %r5, %r1; +; SM60-NEXT: @%p1 bra $L__BB99_1; +; SM60-NEXT: // %bb.2: // %atomicrmw.end +; SM60-NEXT: membar.cta; +; SM60-NEXT: st.param.b32 [func_retval0], %r1; +; SM60-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") seq_cst + ret i32 %retval +} + diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll new file mode 100644 index 0000000000000..ec058567e9ec7 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/atomicrmw-sm70.ll @@ -0,0 +1,3111 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx63 | FileCheck %s --check-prefix=SM70 +; RUN: %if ptxas-sm_70 && ptxas-isa-6.3 %{ llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx63 | %ptxas-verify -arch=sm_70 %} + +define i8 @xchg_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: xchg_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<14>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r5, [xchg_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r6, %rd2; +; SM70-NEXT: and.b32 %r7, %r6, 3; +; SM70-NEXT: shl.b32 %r1, %r7, 3; +; SM70-NEXT: mov.b32 %r8, 255; +; SM70-NEXT: shl.b32 %r9, %r8, %r1; +; SM70-NEXT: not.b32 %r2, %r9; +; SM70-NEXT: shl.b32 %r3, %r5, %r1; +; SM70-NEXT: ld.global.b32 %r13, [%rd1]; +; SM70-NEXT: $L__BB0_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r10, %r13, %r2; +; SM70-NEXT: or.b32 %r11, %r10, %r3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r4, [%rd1], %r13, %r11; +; SM70-NEXT: setp.ne.b32 %p1, %r4, %r13; +; SM70-NEXT: mov.b32 %r13, %r4; +; SM70-NEXT: @%p1 bra $L__BB0_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r12, %r4, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r12; +; SM70-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @xchg_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: xchg_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<14>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b16 %r5, [xchg_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r6, %rd2; +; SM70-NEXT: and.b32 %r7, %r6, 3; +; SM70-NEXT: shl.b32 %r1, %r7, 3; +; SM70-NEXT: mov.b32 %r8, 65535; +; SM70-NEXT: shl.b32 %r9, %r8, %r1; +; SM70-NEXT: not.b32 %r2, %r9; +; SM70-NEXT: shl.b32 %r3, %r5, %r1; +; SM70-NEXT: ld.global.b32 %r13, [%rd1]; +; SM70-NEXT: $L__BB1_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r10, %r13, %r2; +; SM70-NEXT: or.b32 %r11, %r10, %r3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r4, [%rd1], %r13, %r11; +; SM70-NEXT: setp.ne.b32 %p1, %r4, %r13; +; SM70-NEXT: mov.b32 %r13, %r4; +; SM70-NEXT: @%p1 bra $L__BB1_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r12, %r4, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r12; +; SM70-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @xchg_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: xchg_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [xchg_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [xchg_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.exch.b32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @xchg_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: xchg_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [xchg_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.exch.b64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @add_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: add_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [add_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r6, [add_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB4_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: add.s32 %r10, %r15, %r4; +; SM70-NEXT: and.b32 %r11, %r10, %r2; +; SM70-NEXT: and.b32 %r12, %r15, %r3; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM70-NEXT: mov.b32 %r15, %r5; +; SM70-NEXT: @%p1 bra $L__BB4_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @add_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: add_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [add_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b16 %r6, [add_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 65535; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB5_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: add.s32 %r10, %r15, %r4; +; SM70-NEXT: and.b32 %r11, %r10, %r2; +; SM70-NEXT: and.b32 %r12, %r15, %r3; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM70-NEXT: mov.b32 %r15, %r5; +; SM70-NEXT: @%p1 bra $L__BB5_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @add_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: add_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.add.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @add_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: add_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.add.u64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @sub_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: sub_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r6, [sub_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB8_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: sub.s32 %r10, %r15, %r4; +; SM70-NEXT: and.b32 %r11, %r10, %r2; +; SM70-NEXT: and.b32 %r12, %r15, %r3; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM70-NEXT: mov.b32 %r15, %r5; +; SM70-NEXT: @%p1 bra $L__BB8_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @sub_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: sub_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b16 %r6, [sub_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 65535; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB9_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: sub.s32 %r10, %r15, %r4; +; SM70-NEXT: and.b32 %r11, %r10, %r2; +; SM70-NEXT: and.b32 %r12, %r15, %r3; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM70-NEXT: mov.b32 %r15, %r5; +; SM70-NEXT: @%p1 bra $L__BB9_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @sub_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: sub_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<4>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [sub_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [sub_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: neg.s32 %r2, %r1; +; SM70-NEXT: atom.acq_rel.cta.global.add.u32 %r3, [%rd1], %r2; +; SM70-NEXT: st.param.b32 [func_retval0], %r3; +; SM70-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @sub_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: sub_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<5>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [sub_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: neg.s64 %rd3, %rd2; +; SM70-NEXT: atom.acq_rel.cta.global.add.u64 %rd4, [%rd1], %rd3; +; SM70-NEXT: st.param.b64 [func_retval0], %rd4; +; SM70-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @and_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: and_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<12>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [and_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r1, [and_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd2, %rd1, -4; +; SM70-NEXT: cvt.u32.u64 %r2, %rd1; +; SM70-NEXT: and.b32 %r3, %r2, 3; +; SM70-NEXT: shl.b32 %r4, %r3, 3; +; SM70-NEXT: mov.b32 %r5, 255; +; SM70-NEXT: shl.b32 %r6, %r5, %r4; +; SM70-NEXT: not.b32 %r7, %r6; +; SM70-NEXT: shl.b32 %r8, %r1, %r4; +; SM70-NEXT: or.b32 %r9, %r8, %r7; +; SM70-NEXT: atom.relaxed.cta.global.and.b32 %r10, [%rd2], %r9; +; SM70-NEXT: shr.u32 %r11, %r10, %r4; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r11; +; SM70-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @and_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: and_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<12>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [and_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b16 %r1, [and_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd2, %rd1, -4; +; SM70-NEXT: cvt.u32.u64 %r2, %rd1; +; SM70-NEXT: and.b32 %r3, %r2, 3; +; SM70-NEXT: shl.b32 %r4, %r3, 3; +; SM70-NEXT: mov.b32 %r5, 65535; +; SM70-NEXT: shl.b32 %r6, %r5, %r4; +; SM70-NEXT: not.b32 %r7, %r6; +; SM70-NEXT: shl.b32 %r8, %r1, %r4; +; SM70-NEXT: or.b32 %r9, %r8, %r7; +; SM70-NEXT: atom.relaxed.cta.global.and.b32 %r10, [%rd2], %r9; +; SM70-NEXT: shr.u32 %r11, %r10, %r4; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r11; +; SM70-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @and_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: and_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [and_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [and_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.and.b32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @and_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: and_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [and_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [and_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.and.b64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @nand_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: nand_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<17>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r6, [nand_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r16, [%rd1]; +; SM70-NEXT: $L__BB16_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r10, %r16, %r4; +; SM70-NEXT: not.b32 %r11, %r10; +; SM70-NEXT: and.b32 %r12, %r11, %r2; +; SM70-NEXT: and.b32 %r13, %r16, %r3; +; SM70-NEXT: or.b32 %r14, %r13, %r12; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM70-NEXT: mov.b32 %r16, %r5; +; SM70-NEXT: @%p1 bra $L__BB16_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r15, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r15; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @nand_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: nand_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<17>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b16 %r6, [nand_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 65535; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r16, [%rd1]; +; SM70-NEXT: $L__BB17_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r10, %r16, %r4; +; SM70-NEXT: not.b32 %r11, %r10; +; SM70-NEXT: and.b32 %r12, %r11, %r2; +; SM70-NEXT: and.b32 %r13, %r16, %r3; +; SM70-NEXT: or.b32 %r14, %r13, %r12; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM70-NEXT: mov.b32 %r16, %r5; +; SM70-NEXT: @%p1 bra $L__BB17_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r15, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r15; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @nand_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: nand_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<6>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r5, [%rd1]; +; SM70-NEXT: $L__BB18_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r3, %r5, %r2; +; SM70-NEXT: not.b32 %r4, %r3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM70-NEXT: mov.b32 %r5, %r1; +; SM70-NEXT: @%p1 bra $L__BB18_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @nand_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: nand_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b64 %rd<7>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM70-NEXT: $L__BB19_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b64 %rd4, %rd6, %rd3; +; SM70-NEXT: not.b64 %rd5, %rd4; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM70-NEXT: setp.ne.b64 %p1, %rd1, %rd6; +; SM70-NEXT: mov.b64 %rd6, %rd1; +; SM70-NEXT: @%p1 bra $L__BB19_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @or_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: or_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<8>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [or_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r1, [or_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd2, %rd1, -4; +; SM70-NEXT: cvt.u32.u64 %r2, %rd1; +; SM70-NEXT: and.b32 %r3, %r2, 3; +; SM70-NEXT: shl.b32 %r4, %r3, 3; +; SM70-NEXT: shl.b32 %r5, %r1, %r4; +; SM70-NEXT: atom.relaxed.cta.global.or.b32 %r6, [%rd2], %r5; +; SM70-NEXT: shr.u32 %r7, %r6, %r4; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r7; +; SM70-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @or_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: or_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<8>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [or_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b16 %r1, [or_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd2, %rd1, -4; +; SM70-NEXT: cvt.u32.u64 %r2, %rd1; +; SM70-NEXT: and.b32 %r3, %r2, 3; +; SM70-NEXT: shl.b32 %r4, %r3, 3; +; SM70-NEXT: shl.b32 %r5, %r1, %r4; +; SM70-NEXT: atom.relaxed.cta.global.or.b32 %r6, [%rd2], %r5; +; SM70-NEXT: shr.u32 %r7, %r6, %r4; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r7; +; SM70-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @or_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: or_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [or_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [or_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.or.b32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @or_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: or_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [or_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [or_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.or.b64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @xor_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: xor_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<8>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r1, [xor_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd2, %rd1, -4; +; SM70-NEXT: cvt.u32.u64 %r2, %rd1; +; SM70-NEXT: and.b32 %r3, %r2, 3; +; SM70-NEXT: shl.b32 %r4, %r3, 3; +; SM70-NEXT: shl.b32 %r5, %r1, %r4; +; SM70-NEXT: atom.relaxed.cta.global.xor.b32 %r6, [%rd2], %r5; +; SM70-NEXT: shr.u32 %r7, %r6, %r4; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r7; +; SM70-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @xor_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: xor_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<8>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b16 %r1, [xor_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd2, %rd1, -4; +; SM70-NEXT: cvt.u32.u64 %r2, %rd1; +; SM70-NEXT: and.b32 %r3, %r2, 3; +; SM70-NEXT: shl.b32 %r4, %r3, 3; +; SM70-NEXT: shl.b32 %r5, %r1, %r4; +; SM70-NEXT: atom.relaxed.cta.global.xor.b32 %r6, [%rd2], %r5; +; SM70-NEXT: shr.u32 %r7, %r6, %r4; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r7; +; SM70-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @xor_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: xor_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [xor_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.xor.b32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @xor_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: xor_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [xor_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.xor.b64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @max_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: max_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<5>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b8 %rs1, [max_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [max_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 255; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: cvt.s16.s8 %rs3, %rs1; +; SM70-NEXT: $L__BB28_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r15, %r1; +; SM70-NEXT: cvt.s8.s32 %rs2, %r8; +; SM70-NEXT: max.s16 %rs4, %rs2, %rs3; +; SM70-NEXT: cvt.u32.u16 %r9, %rs4; +; SM70-NEXT: and.b32 %r10, %r9, 255; +; SM70-NEXT: shl.b32 %r11, %r10, %r1; +; SM70-NEXT: and.b32 %r12, %r15, %r2; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r15; +; SM70-NEXT: mov.b32 %r15, %r3; +; SM70-NEXT: @%p1 bra $L__BB28_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @max_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: max_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<4>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [max_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [max_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB29_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: max.s16 %rs3, %rs2, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs3; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB29_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @max_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: max_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [max_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [max_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.max.s32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @max_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: max_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [max_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [max_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.max.s64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @min_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: min_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<5>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b8 %rs1, [min_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [min_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 255; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: cvt.s16.s8 %rs3, %rs1; +; SM70-NEXT: $L__BB32_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r15, %r1; +; SM70-NEXT: cvt.s8.s32 %rs2, %r8; +; SM70-NEXT: min.s16 %rs4, %rs2, %rs3; +; SM70-NEXT: cvt.u32.u16 %r9, %rs4; +; SM70-NEXT: and.b32 %r10, %r9, 255; +; SM70-NEXT: shl.b32 %r11, %r10, %r1; +; SM70-NEXT: and.b32 %r12, %r15, %r2; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r15; +; SM70-NEXT: mov.b32 %r15, %r3; +; SM70-NEXT: @%p1 bra $L__BB32_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @min_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: min_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<4>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [min_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [min_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB33_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: min.s16 %rs3, %rs2, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs3; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB33_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @min_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: min_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.min.s32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @min_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: min_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [min_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [min_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.min.s64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @umax_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: umax_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<5>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b8 %rs1, [umax_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 255; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB36_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: and.b16 %rs3, %rs2, 255; +; SM70-NEXT: max.u16 %rs4, %rs3, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs4; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB36_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @umax_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: umax_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<4>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [umax_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB37_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: max.u16 %rs3, %rs2, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs3; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB37_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @umax_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: umax_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.max.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @umax_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: umax_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.max.u64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @umin_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: umin_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<5>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b8 %rs1, [umin_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 255; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB40_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: and.b16 %rs3, %rs2, 255; +; SM70-NEXT: min.u16 %rs4, %rs3, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs4; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB40_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @umin_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: umin_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<4>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [umin_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB41_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: min.u16 %rs3, %rs2, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs3; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB41_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @umin_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: umin_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [umin_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [umin_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.min.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @umin_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: umin_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [umin_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.min.u64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @uinc_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: uinc_wrap_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b16 %rs<6>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b8 %rs1, [uinc_wrap_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 255; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB44_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r15, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: and.b16 %rs3, %rs2, 255; +; SM70-NEXT: add.s16 %rs4, %rs2, 1; +; SM70-NEXT: setp.ge.u16 %p1, %rs3, %rs1; +; SM70-NEXT: selp.b16 %rs5, 0, %rs4, %p1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs5; +; SM70-NEXT: and.b32 %r10, %r9, 255; +; SM70-NEXT: shl.b32 %r11, %r10, %r1; +; SM70-NEXT: and.b32 %r12, %r15, %r2; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p2, %r3, %r15; +; SM70-NEXT: mov.b32 %r15, %r3; +; SM70-NEXT: @%p2 bra $L__BB44_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @uinc_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: uinc_wrap_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b16 %rs<5>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [uinc_wrap_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB45_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: add.s16 %rs3, %rs2, 1; +; SM70-NEXT: setp.ge.u16 %p1, %rs2, %rs1; +; SM70-NEXT: selp.b16 %rs4, 0, %rs3, %p1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs4; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p2, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p2 bra $L__BB45_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @uinc_wrap_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: uinc_wrap_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [uinc_wrap_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [uinc_wrap_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.inc.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @uinc_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: uinc_wrap_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b64 %rd<7>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [uinc_wrap_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM70-NEXT: $L__BB47_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: add.s64 %rd4, %rd6, 1; +; SM70-NEXT: setp.ge.u64 %p1, %rd6, %rd3; +; SM70-NEXT: selp.b64 %rd5, 0, %rd4, %p1; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM70-NEXT: setp.ne.b64 %p2, %rd1, %rd6; +; SM70-NEXT: mov.b64 %rd6, %rd1; +; SM70-NEXT: @%p2 bra $L__BB47_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @udec_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: udec_wrap_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<4>; +; SM70-NEXT: .reg .b16 %rs<7>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b8 %rs1, [udec_wrap_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 255; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB48_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r15, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: and.b16 %rs3, %rs2, 255; +; SM70-NEXT: add.s16 %rs4, %rs2, -1; +; SM70-NEXT: setp.eq.b16 %p1, %rs3, 0; +; SM70-NEXT: setp.gt.u16 %p2, %rs3, %rs1; +; SM70-NEXT: selp.b16 %rs5, %rs1, %rs4, %p2; +; SM70-NEXT: selp.b16 %rs6, %rs1, %rs5, %p1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs6; +; SM70-NEXT: and.b32 %r10, %r9, 255; +; SM70-NEXT: shl.b32 %r11, %r10, %r1; +; SM70-NEXT: and.b32 %r12, %r15, %r2; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p3, %r3, %r15; +; SM70-NEXT: mov.b32 %r15, %r3; +; SM70-NEXT: @%p3 bra $L__BB48_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @udec_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: udec_wrap_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<4>; +; SM70-NEXT: .reg .b16 %rs<6>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [udec_wrap_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB49_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: add.s16 %rs3, %rs2, -1; +; SM70-NEXT: setp.eq.b16 %p1, %rs2, 0; +; SM70-NEXT: setp.gt.u16 %p2, %rs2, %rs1; +; SM70-NEXT: selp.b16 %rs4, %rs1, %rs3, %p2; +; SM70-NEXT: selp.b16 %rs5, %rs1, %rs4, %p1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs5; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p3, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p3 bra $L__BB49_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @udec_wrap_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: udec_wrap_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [udec_wrap_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [udec_wrap_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.dec.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @udec_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: udec_wrap_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<4>; +; SM70-NEXT: .reg .b64 %rd<8>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [udec_wrap_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd7, [%rd2]; +; SM70-NEXT: $L__BB51_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: add.s64 %rd4, %rd7, -1; +; SM70-NEXT: setp.eq.b64 %p1, %rd7, 0; +; SM70-NEXT: setp.gt.u64 %p2, %rd7, %rd3; +; SM70-NEXT: selp.b64 %rd5, %rd3, %rd4, %p2; +; SM70-NEXT: selp.b64 %rd6, %rd3, %rd5, %p1; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd7, %rd6; +; SM70-NEXT: setp.ne.b64 %p3, %rd1, %rd7; +; SM70-NEXT: mov.b64 %rd7, %rd1; +; SM70-NEXT: @%p3 bra $L__BB51_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @usub_cond_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: usub_cond_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b16 %rs<6>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b8 %rs1, [usub_cond_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 255; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB52_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r15, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: and.b16 %rs3, %rs2, 255; +; SM70-NEXT: setp.ge.u16 %p1, %rs3, %rs1; +; SM70-NEXT: sub.s16 %rs4, %rs2, %rs1; +; SM70-NEXT: selp.b16 %rs5, %rs4, %rs2, %p1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs5; +; SM70-NEXT: and.b32 %r10, %r9, 255; +; SM70-NEXT: shl.b32 %r11, %r10, %r1; +; SM70-NEXT: and.b32 %r12, %r15, %r2; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p2, %r3, %r15; +; SM70-NEXT: mov.b32 %r15, %r3; +; SM70-NEXT: @%p2 bra $L__BB52_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @usub_cond_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: usub_cond_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b16 %rs<5>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [usub_cond_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB53_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: setp.ge.u16 %p1, %rs2, %rs1; +; SM70-NEXT: sub.s16 %rs3, %rs2, %rs1; +; SM70-NEXT: selp.b16 %rs4, %rs3, %rs2, %p1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs4; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p2, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p2 bra $L__BB53_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @usub_cond_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: usub_cond_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b32 %r<6>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [usub_cond_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [usub_cond_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r5, [%rd1]; +; SM70-NEXT: $L__BB54_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: setp.ge.u32 %p1, %r5, %r2; +; SM70-NEXT: sub.s32 %r3, %r5, %r2; +; SM70-NEXT: selp.b32 %r4, %r3, %r5, %p1; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM70-NEXT: setp.ne.b32 %p2, %r1, %r5; +; SM70-NEXT: mov.b32 %r5, %r1; +; SM70-NEXT: @%p2 bra $L__BB54_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @usub_cond_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: usub_cond_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b64 %rd<7>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [usub_cond_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM70-NEXT: $L__BB55_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: setp.ge.u64 %p1, %rd6, %rd3; +; SM70-NEXT: sub.s64 %rd4, %rd6, %rd3; +; SM70-NEXT: selp.b64 %rd5, %rd4, %rd6, %p1; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM70-NEXT: setp.ne.b64 %p2, %rd1, %rd6; +; SM70-NEXT: mov.b64 %rd6, %rd1; +; SM70-NEXT: @%p2 bra $L__BB55_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @usub_sat_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: usub_sat_acq_rel_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<6>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b8 %rs1, [usub_sat_acq_rel_i8_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 255; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB56_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: and.b16 %rs3, %rs2, 255; +; SM70-NEXT: max.u16 %rs4, %rs3, %rs1; +; SM70-NEXT: sub.s16 %rs5, %rs4, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs5; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB56_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @usub_sat_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM70-LABEL: usub_sat_acq_rel_i16_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<5>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [usub_sat_acq_rel_i16_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i16_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB57_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: max.u16 %rs3, %rs2, %rs1; +; SM70-NEXT: sub.s16 %rs4, %rs3, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs4; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB57_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @usub_sat_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: usub_sat_acq_rel_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<6>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [usub_sat_acq_rel_i32_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [usub_sat_acq_rel_i32_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r5, [%rd1]; +; SM70-NEXT: $L__BB58_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: max.u32 %r3, %r5, %r2; +; SM70-NEXT: sub.s32 %r4, %r3, %r2; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM70-NEXT: mov.b32 %r5, %r1; +; SM70-NEXT: @%p1 bra $L__BB58_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @usub_sat_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM70-LABEL: usub_sat_acq_rel_i64_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b64 %rd<7>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [usub_sat_acq_rel_i64_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i64_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM70-NEXT: $L__BB59_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: max.u64 %rd4, %rd6, %rd3; +; SM70-NEXT: sub.s64 %rd5, %rd4, %rd3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM70-NEXT: setp.ne.b64 %p1, %rd1, %rd6; +; SM70-NEXT: mov.b64 %rd6, %rd1; +; SM70-NEXT: @%p1 bra $L__BB59_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define float @fadd_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM70-LABEL: fadd_acq_rel_float_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.add.f32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM70-LABEL: fsub_acq_rel_float_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<5>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [fsub_acq_rel_float_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r4, [%rd1]; +; SM70-NEXT: $L__BB61_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: sub.rn.f32 %r3, %r4, %r2; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM70-NEXT: mov.b32 %r4, %r1; +; SM70-NEXT: @%p1 bra $L__BB61_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM70-LABEL: fmin_acq_rel_float_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<5>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [fmin_acq_rel_float_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r4, [%rd1]; +; SM70-NEXT: $L__BB62_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: min.f32 %r3, %r4, %r2; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM70-NEXT: mov.b32 %r4, %r1; +; SM70-NEXT: @%p1 bra $L__BB62_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM70-LABEL: fmax_acq_rel_float_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<5>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [fmax_acq_rel_float_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r4, [%rd1]; +; SM70-NEXT: $L__BB63_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: max.f32 %r3, %r4, %r2; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM70-NEXT: mov.b32 %r4, %r1; +; SM70-NEXT: @%p1 bra $L__BB63_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM70-LABEL: fminimum_acq_rel_float_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<6>; +; SM70-NEXT: .reg .b32 %r<9>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r8, [%rd1]; +; SM70-NEXT: setp.eq.b32 %p3, %r2, -2147483648; +; SM70-NEXT: $L__BB64_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: setp.nan.f32 %p1, %r8, %r2; +; SM70-NEXT: min.f32 %r3, %r8, %r2; +; SM70-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1; +; SM70-NEXT: setp.eq.b32 %p2, %r8, -2147483648; +; SM70-NEXT: selp.f32 %r5, %r8, %r4, %p2; +; SM70-NEXT: selp.f32 %r6, %r2, %r5, %p3; +; SM70-NEXT: setp.eq.f32 %p4, %r4, 0f00000000; +; SM70-NEXT: selp.f32 %r7, %r6, %r4, %p4; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r8, %r7; +; SM70-NEXT: setp.ne.b32 %p5, %r1, %r8; +; SM70-NEXT: mov.b32 %r8, %r1; +; SM70-NEXT: @%p5 bra $L__BB64_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM70-LABEL: fmaximum_acq_rel_float_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<6>; +; SM70-NEXT: .reg .b32 %r<9>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r8, [%rd1]; +; SM70-NEXT: setp.eq.b32 %p3, %r2, 0; +; SM70-NEXT: $L__BB65_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: setp.nan.f32 %p1, %r8, %r2; +; SM70-NEXT: max.f32 %r3, %r8, %r2; +; SM70-NEXT: selp.f32 %r4, 0f7FC00000, %r3, %p1; +; SM70-NEXT: setp.eq.b32 %p2, %r8, 0; +; SM70-NEXT: selp.f32 %r5, %r8, %r4, %p2; +; SM70-NEXT: selp.f32 %r6, %r2, %r5, %p3; +; SM70-NEXT: setp.eq.f32 %p4, %r4, 0f00000000; +; SM70-NEXT: selp.f32 %r7, %r6, %r4, %p4; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r8, %r7; +; SM70-NEXT: setp.ne.b32 %p5, %r1, %r8; +; SM70-NEXT: mov.b32 %r8, %r1; +; SM70-NEXT: @%p5 bra $L__BB65_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define double @fadd_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM70-LABEL: fadd_acq_rel_double_global_cta( +; SM70: { +; SM70-NEXT: .reg .b64 %rd<4>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_global_cta_param_0]; +; SM70-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.add.f64 %rd3, [%rd1], %rd2; +; SM70-NEXT: st.param.b64 [func_retval0], %rd3; +; SM70-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fsub_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM70-LABEL: fsub_acq_rel_double_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b64 %rd<6>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [fsub_acq_rel_double_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_double_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM70-NEXT: $L__BB67_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: sub.rn.f64 %rd4, %rd5, %rd3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM70-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM70-NEXT: mov.b64 %rd5, %rd1; +; SM70-NEXT: @%p1 bra $L__BB67_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmin_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM70-LABEL: fmin_acq_rel_double_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b64 %rd<6>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [fmin_acq_rel_double_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_double_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM70-NEXT: $L__BB68_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: min.f64 %rd4, %rd5, %rd3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM70-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM70-NEXT: mov.b64 %rd5, %rd1; +; SM70-NEXT: @%p1 bra $L__BB68_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmax_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM70-LABEL: fmax_acq_rel_double_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b64 %rd<6>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [fmax_acq_rel_double_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_double_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM70-NEXT: $L__BB69_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: max.f64 %rd4, %rd5, %rd3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM70-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM70-NEXT: mov.b64 %rd5, %rd1; +; SM70-NEXT: @%p1 bra $L__BB69_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM70-LABEL: fminimum_acq_rel_double_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<6>; +; SM70-NEXT: .reg .b64 %rd<10>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [fminimum_acq_rel_double_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_double_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd9, [%rd2]; +; SM70-NEXT: setp.eq.b64 %p3, %rd3, -9223372036854775808; +; SM70-NEXT: $L__BB70_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: setp.nan.f64 %p1, %rd9, %rd3; +; SM70-NEXT: min.f64 %rd4, %rd9, %rd3; +; SM70-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1; +; SM70-NEXT: setp.eq.b64 %p2, %rd9, -9223372036854775808; +; SM70-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2; +; SM70-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3; +; SM70-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000; +; SM70-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8; +; SM70-NEXT: setp.ne.b64 %p5, %rd1, %rd9; +; SM70-NEXT: mov.b64 %rd9, %rd1; +; SM70-NEXT: @%p5 bra $L__BB70_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmaximum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM70-LABEL: fmaximum_acq_rel_double_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<6>; +; SM70-NEXT: .reg .b64 %rd<10>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd3, [fmaximum_acq_rel_double_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_double_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b64 %rd9, [%rd2]; +; SM70-NEXT: setp.eq.b64 %p3, %rd3, 0; +; SM70-NEXT: $L__BB71_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: setp.nan.f64 %p1, %rd9, %rd3; +; SM70-NEXT: max.f64 %rd4, %rd9, %rd3; +; SM70-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1; +; SM70-NEXT: setp.eq.b64 %p2, %rd9, 0; +; SM70-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2; +; SM70-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3; +; SM70-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000; +; SM70-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4; +; SM70-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8; +; SM70-NEXT: setp.ne.b64 %p5, %rd1, %rd9; +; SM70-NEXT: mov.b64 %rd9, %rd1; +; SM70-NEXT: @%p5 bra $L__BB71_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b64 [func_retval0], %rd1; +; SM70-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define half @fadd_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM70-LABEL: fadd_acq_rel_half_global_cta( +; SM70: { +; SM70-NEXT: .reg .b16 %rs<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_half_global_cta_param_0]; +; SM70-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1]; +; SM70-NEXT: atom.acq_rel.cta.global.add.noftz.f16 %rs2, [%rd1], %rs1; +; SM70-NEXT: st.param.b16 [func_retval0], %rs2; +; SM70-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM70-LABEL: fsub_acq_rel_half_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<4>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: $L__BB73_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: sub.rn.f16 %rs3, %rs2, %rs1; +; SM70-NEXT: cvt.u32.u16 %r9, %rs3; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p1 bra $L__BB73_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM70-LABEL: fmin_acq_rel_half_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<4>; +; SM70-NEXT: .reg .b32 %r<18>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r17, [%rd1]; +; SM70-NEXT: cvt.f32.f16 %r10, %rs1; +; SM70-NEXT: $L__BB74_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r17, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: cvt.f32.f16 %r9, %rs2; +; SM70-NEXT: min.f32 %r11, %r9, %r10; +; SM70-NEXT: cvt.rn.f16.f32 %rs3, %r11; +; SM70-NEXT: cvt.u32.u16 %r12, %rs3; +; SM70-NEXT: shl.b32 %r13, %r12, %r1; +; SM70-NEXT: and.b32 %r14, %r17, %r2; +; SM70-NEXT: or.b32 %r15, %r14, %r13; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r17, %r15; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r17; +; SM70-NEXT: mov.b32 %r17, %r3; +; SM70-NEXT: @%p1 bra $L__BB74_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r16, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r16; +; SM70-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM70-LABEL: fmax_acq_rel_half_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b16 %rs<4>; +; SM70-NEXT: .reg .b32 %r<18>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r17, [%rd1]; +; SM70-NEXT: cvt.f32.f16 %r10, %rs1; +; SM70-NEXT: $L__BB75_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r17, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: cvt.f32.f16 %r9, %rs2; +; SM70-NEXT: max.f32 %r11, %r9, %r10; +; SM70-NEXT: cvt.rn.f16.f32 %rs3, %r11; +; SM70-NEXT: cvt.u32.u16 %r12, %rs3; +; SM70-NEXT: shl.b32 %r13, %r12, %r1; +; SM70-NEXT: and.b32 %r14, %r17, %r2; +; SM70-NEXT: or.b32 %r15, %r14, %r13; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r17, %r15; +; SM70-NEXT: setp.ne.b32 %p1, %r3, %r17; +; SM70-NEXT: mov.b32 %r17, %r3; +; SM70-NEXT: @%p1 bra $L__BB75_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r16, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r16; +; SM70-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM70-LABEL: fminimum_acq_rel_half_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<7>; +; SM70-NEXT: .reg .b16 %rs<9>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: setp.eq.b16 %p4, %rs1, -32768; +; SM70-NEXT: $L__BB76_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: setp.lt.f16 %p1, %rs2, %rs1; +; SM70-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1; +; SM70-NEXT: setp.nan.f16 %p2, %rs2, %rs1; +; SM70-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2; +; SM70-NEXT: setp.eq.b16 %p3, %rs2, -32768; +; SM70-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3; +; SM70-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4; +; SM70-NEXT: mov.b16 %rs7, 0x0000; +; SM70-NEXT: setp.eq.f16 %p5, %rs4, %rs7; +; SM70-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5; +; SM70-NEXT: cvt.u32.u16 %r9, %rs8; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p6, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p6 bra $L__BB76_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM70-LABEL: fmaximum_acq_rel_half_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<7>; +; SM70-NEXT: .reg .b16 %rs<9>; +; SM70-NEXT: .reg .b32 %r<15>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r14, [%rd1]; +; SM70-NEXT: setp.eq.b16 %p4, %rs1, 0; +; SM70-NEXT: $L__BB77_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r14, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: setp.gt.f16 %p1, %rs2, %rs1; +; SM70-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1; +; SM70-NEXT: setp.nan.f16 %p2, %rs2, %rs1; +; SM70-NEXT: selp.b16 %rs4, 0x7E00, %rs3, %p2; +; SM70-NEXT: setp.eq.b16 %p3, %rs2, 0; +; SM70-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3; +; SM70-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4; +; SM70-NEXT: mov.b16 %rs7, 0x0000; +; SM70-NEXT: setp.eq.f16 %p5, %rs4, %rs7; +; SM70-NEXT: selp.b16 %rs8, %rs6, %rs4, %p5; +; SM70-NEXT: cvt.u32.u16 %r9, %rs8; +; SM70-NEXT: shl.b32 %r10, %r9, %r1; +; SM70-NEXT: and.b32 %r11, %r14, %r2; +; SM70-NEXT: or.b32 %r12, %r11, %r10; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM70-NEXT: setp.ne.b32 %p6, %r3, %r14; +; SM70-NEXT: mov.b32 %r14, %r3; +; SM70-NEXT: @%p6 bra $L__BB77_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r13, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r13; +; SM70-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define bfloat @fadd_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM70-LABEL: fadd_acq_rel_bfloat_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b16 %rs<2>; +; SM70-NEXT: .reg .b32 %r<24>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_bfloat_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_bfloat_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r23, [%rd1]; +; SM70-NEXT: cvt.u32.u16 %r10, %rs1; +; SM70-NEXT: shl.b32 %r11, %r10, 16; +; SM70-NEXT: $L__BB78_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r23, %r1; +; SM70-NEXT: shl.b32 %r9, %r8, 16; +; SM70-NEXT: add.rn.f32 %r12, %r9, %r11; +; SM70-NEXT: bfe.u32 %r13, %r12, 16, 1; +; SM70-NEXT: add.s32 %r14, %r13, %r12; +; SM70-NEXT: add.s32 %r15, %r14, 32767; +; SM70-NEXT: setp.nan.f32 %p1, %r12, %r12; +; SM70-NEXT: or.b32 %r16, %r12, 4194304; +; SM70-NEXT: selp.b32 %r17, %r16, %r15, %p1; +; SM70-NEXT: shr.u32 %r18, %r17, 16; +; SM70-NEXT: shl.b32 %r19, %r18, %r1; +; SM70-NEXT: and.b32 %r20, %r23, %r2; +; SM70-NEXT: or.b32 %r21, %r20, %r19; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r23, %r21; +; SM70-NEXT: setp.ne.b32 %p2, %r3, %r23; +; SM70-NEXT: mov.b32 %r23, %r3; +; SM70-NEXT: @%p2 bra $L__BB78_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r22, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r22; +; SM70-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fsub_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM70-LABEL: fsub_acq_rel_bfloat_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b16 %rs<2>; +; SM70-NEXT: .reg .b32 %r<24>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_bfloat_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_bfloat_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r23, [%rd1]; +; SM70-NEXT: cvt.u32.u16 %r10, %rs1; +; SM70-NEXT: shl.b32 %r11, %r10, 16; +; SM70-NEXT: $L__BB79_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r23, %r1; +; SM70-NEXT: shl.b32 %r9, %r8, 16; +; SM70-NEXT: sub.rn.f32 %r12, %r9, %r11; +; SM70-NEXT: bfe.u32 %r13, %r12, 16, 1; +; SM70-NEXT: add.s32 %r14, %r13, %r12; +; SM70-NEXT: add.s32 %r15, %r14, 32767; +; SM70-NEXT: setp.nan.f32 %p1, %r12, %r12; +; SM70-NEXT: or.b32 %r16, %r12, 4194304; +; SM70-NEXT: selp.b32 %r17, %r16, %r15, %p1; +; SM70-NEXT: shr.u32 %r18, %r17, 16; +; SM70-NEXT: shl.b32 %r19, %r18, %r1; +; SM70-NEXT: and.b32 %r20, %r23, %r2; +; SM70-NEXT: or.b32 %r21, %r20, %r19; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r23, %r21; +; SM70-NEXT: setp.ne.b32 %p2, %r3, %r23; +; SM70-NEXT: mov.b32 %r23, %r3; +; SM70-NEXT: @%p2 bra $L__BB79_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r22, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r22; +; SM70-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmin_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM70-LABEL: fmin_acq_rel_bfloat_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b16 %rs<2>; +; SM70-NEXT: .reg .b32 %r<24>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_bfloat_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_bfloat_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r23, [%rd1]; +; SM70-NEXT: cvt.u32.u16 %r10, %rs1; +; SM70-NEXT: shl.b32 %r11, %r10, 16; +; SM70-NEXT: $L__BB80_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r23, %r1; +; SM70-NEXT: shl.b32 %r9, %r8, 16; +; SM70-NEXT: min.f32 %r12, %r9, %r11; +; SM70-NEXT: bfe.u32 %r13, %r12, 16, 1; +; SM70-NEXT: add.s32 %r14, %r13, %r12; +; SM70-NEXT: add.s32 %r15, %r14, 32767; +; SM70-NEXT: setp.nan.f32 %p1, %r12, %r12; +; SM70-NEXT: or.b32 %r16, %r12, 4194304; +; SM70-NEXT: selp.b32 %r17, %r16, %r15, %p1; +; SM70-NEXT: shr.u32 %r18, %r17, 16; +; SM70-NEXT: shl.b32 %r19, %r18, %r1; +; SM70-NEXT: and.b32 %r20, %r23, %r2; +; SM70-NEXT: or.b32 %r21, %r20, %r19; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r23, %r21; +; SM70-NEXT: setp.ne.b32 %p2, %r3, %r23; +; SM70-NEXT: mov.b32 %r23, %r3; +; SM70-NEXT: @%p2 bra $L__BB80_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r22, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r22; +; SM70-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmax_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM70-LABEL: fmax_acq_rel_bfloat_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<3>; +; SM70-NEXT: .reg .b16 %rs<2>; +; SM70-NEXT: .reg .b32 %r<24>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_bfloat_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_bfloat_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r23, [%rd1]; +; SM70-NEXT: cvt.u32.u16 %r10, %rs1; +; SM70-NEXT: shl.b32 %r11, %r10, 16; +; SM70-NEXT: $L__BB81_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r23, %r1; +; SM70-NEXT: shl.b32 %r9, %r8, 16; +; SM70-NEXT: max.f32 %r12, %r9, %r11; +; SM70-NEXT: bfe.u32 %r13, %r12, 16, 1; +; SM70-NEXT: add.s32 %r14, %r13, %r12; +; SM70-NEXT: add.s32 %r15, %r14, 32767; +; SM70-NEXT: setp.nan.f32 %p1, %r12, %r12; +; SM70-NEXT: or.b32 %r16, %r12, 4194304; +; SM70-NEXT: selp.b32 %r17, %r16, %r15, %p1; +; SM70-NEXT: shr.u32 %r18, %r17, 16; +; SM70-NEXT: shl.b32 %r19, %r18, %r1; +; SM70-NEXT: and.b32 %r20, %r23, %r2; +; SM70-NEXT: or.b32 %r21, %r20, %r19; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r23, %r21; +; SM70-NEXT: setp.ne.b32 %p2, %r3, %r23; +; SM70-NEXT: mov.b32 %r23, %r3; +; SM70-NEXT: @%p2 bra $L__BB81_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r22, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r22; +; SM70-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM70-LABEL: fminimum_acq_rel_bfloat_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<7>; +; SM70-NEXT: .reg .b16 %rs<8>; +; SM70-NEXT: .reg .b32 %r<20>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_bfloat_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_bfloat_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r19, [%rd1]; +; SM70-NEXT: cvt.u32.u16 %r10, %rs1; +; SM70-NEXT: shl.b32 %r11, %r10, 16; +; SM70-NEXT: setp.eq.b16 %p4, %rs1, -32768; +; SM70-NEXT: $L__BB82_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r19, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: shl.b32 %r9, %r8, 16; +; SM70-NEXT: setp.lt.f32 %p1, %r9, %r11; +; SM70-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1; +; SM70-NEXT: setp.nan.f32 %p2, %r9, %r11; +; SM70-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2; +; SM70-NEXT: setp.eq.b16 %p3, %rs2, -32768; +; SM70-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3; +; SM70-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4; +; SM70-NEXT: cvt.u32.u16 %r12, %rs4; +; SM70-NEXT: shl.b32 %r13, %r12, 16; +; SM70-NEXT: setp.eq.f32 %p5, %r13, 0f00000000; +; SM70-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5; +; SM70-NEXT: cvt.u32.u16 %r14, %rs7; +; SM70-NEXT: shl.b32 %r15, %r14, %r1; +; SM70-NEXT: and.b32 %r16, %r19, %r2; +; SM70-NEXT: or.b32 %r17, %r16, %r15; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r19, %r17; +; SM70-NEXT: setp.ne.b32 %p6, %r3, %r19; +; SM70-NEXT: mov.b32 %r19, %r3; +; SM70-NEXT: @%p6 bra $L__BB82_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r18, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r18; +; SM70-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM70-LABEL: fmaximum_acq_rel_bfloat_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<7>; +; SM70-NEXT: .reg .b16 %rs<8>; +; SM70-NEXT: .reg .b32 %r<20>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_bfloat_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_bfloat_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r4, %rd2; +; SM70-NEXT: and.b32 %r5, %r4, 3; +; SM70-NEXT: shl.b32 %r1, %r5, 3; +; SM70-NEXT: mov.b32 %r6, 65535; +; SM70-NEXT: shl.b32 %r7, %r6, %r1; +; SM70-NEXT: not.b32 %r2, %r7; +; SM70-NEXT: ld.global.b32 %r19, [%rd1]; +; SM70-NEXT: cvt.u32.u16 %r10, %rs1; +; SM70-NEXT: shl.b32 %r11, %r10, 16; +; SM70-NEXT: setp.eq.b16 %p4, %rs1, 0; +; SM70-NEXT: $L__BB83_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: shr.u32 %r8, %r19, %r1; +; SM70-NEXT: cvt.u16.u32 %rs2, %r8; +; SM70-NEXT: shl.b32 %r9, %r8, 16; +; SM70-NEXT: setp.gt.f32 %p1, %r9, %r11; +; SM70-NEXT: selp.b16 %rs3, %rs2, %rs1, %p1; +; SM70-NEXT: setp.nan.f32 %p2, %r9, %r11; +; SM70-NEXT: selp.b16 %rs4, 0x7FC0, %rs3, %p2; +; SM70-NEXT: setp.eq.b16 %p3, %rs2, 0; +; SM70-NEXT: selp.b16 %rs5, %rs2, %rs4, %p3; +; SM70-NEXT: selp.b16 %rs6, %rs1, %rs5, %p4; +; SM70-NEXT: cvt.u32.u16 %r12, %rs4; +; SM70-NEXT: shl.b32 %r13, %r12, 16; +; SM70-NEXT: setp.eq.f32 %p5, %r13, 0f00000000; +; SM70-NEXT: selp.b16 %rs7, %rs6, %rs4, %p5; +; SM70-NEXT: cvt.u32.u16 %r14, %rs7; +; SM70-NEXT: shl.b32 %r15, %r14, %r1; +; SM70-NEXT: and.b32 %r16, %r19, %r2; +; SM70-NEXT: or.b32 %r17, %r16, %r15; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r19, %r17; +; SM70-NEXT: setp.ne.b32 %p6, %r3, %r19; +; SM70-NEXT: mov.b32 %r19, %r3; +; SM70-NEXT: @%p6 bra $L__BB83_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r18, %r3, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b16 [func_retval0], %r18; +; SM70-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define i8 @add_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: add_monotonic_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [add_monotonic_i8_global_cta_param_0]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: ld.param.b8 %r6, [add_monotonic_i8_global_cta_param_1]; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB84_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: add.s32 %r10, %r15, %r4; +; SM70-NEXT: and.b32 %r11, %r10, %r2; +; SM70-NEXT: and.b32 %r12, %r15, %r3; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM70-NEXT: mov.b32 %r15, %r5; +; SM70-NEXT: @%p1 bra $L__BB84_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r5, %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") monotonic + ret i8 %retval +} + +define i8 @add_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: add_acquire_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [add_acquire_i8_global_cta_param_0]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: ld.param.b8 %r6, [add_acquire_i8_global_cta_param_1]; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB85_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: add.s32 %r10, %r15, %r4; +; SM70-NEXT: and.b32 %r11, %r10, %r2; +; SM70-NEXT: and.b32 %r12, %r15, %r3; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM70-NEXT: mov.b32 %r15, %r5; +; SM70-NEXT: @%p1 bra $L__BB85_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") acquire + ret i8 %retval +} + +define i8 @add_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: add_release_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [add_release_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r6, [add_release_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB86_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: add.s32 %r10, %r15, %r4; +; SM70-NEXT: and.b32 %r11, %r10, %r2; +; SM70-NEXT: and.b32 %r12, %r15, %r3; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM70-NEXT: mov.b32 %r15, %r5; +; SM70-NEXT: @%p1 bra $L__BB86_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r5, %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") release + ret i8 %retval +} + +define i8 @add_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: add_seq_cst_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<16>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [add_seq_cst_i8_global_cta_param_0]; +; SM70-NEXT: fence.sc.cta; +; SM70-NEXT: ld.param.b8 %r6, [add_seq_cst_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r15, [%rd1]; +; SM70-NEXT: $L__BB87_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: add.s32 %r10, %r15, %r4; +; SM70-NEXT: and.b32 %r11, %r10, %r2; +; SM70-NEXT: and.b32 %r12, %r15, %r3; +; SM70-NEXT: or.b32 %r13, %r12, %r11; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM70-NEXT: mov.b32 %r15, %r5; +; SM70-NEXT: @%p1 bra $L__BB87_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r14, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r14; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") seq_cst + ret i8 %retval +} + +define i32 @add_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: add_monotonic_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [add_monotonic_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [add_monotonic_i32_global_cta_param_1]; +; SM70-NEXT: atom.relaxed.cta.global.add.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") monotonic + ret i32 %retval +} + +define i32 @add_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: add_acquire_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [add_acquire_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [add_acquire_i32_global_cta_param_1]; +; SM70-NEXT: atom.acquire.cta.global.add.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") acquire + ret i32 %retval +} + +define i32 @add_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: add_release_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [add_release_i32_global_cta_param_0]; +; SM70-NEXT: ld.param.b32 %r1, [add_release_i32_global_cta_param_1]; +; SM70-NEXT: atom.release.cta.global.add.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") release + ret i32 %retval +} + +define i32 @add_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: add_seq_cst_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .b32 %r<3>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd1, [add_seq_cst_i32_global_cta_param_0]; +; SM70-NEXT: fence.sc.cta; +; SM70-NEXT: ld.param.b32 %r1, [add_seq_cst_i32_global_cta_param_1]; +; SM70-NEXT: atom.acquire.cta.global.add.u32 %r2, [%rd1], %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r2; +; SM70-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") seq_cst + ret i32 %retval +} + +define i8 @nand_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: nand_monotonic_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<17>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [nand_monotonic_i8_global_cta_param_0]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: ld.param.b8 %r6, [nand_monotonic_i8_global_cta_param_1]; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r16, [%rd1]; +; SM70-NEXT: $L__BB92_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r10, %r16, %r4; +; SM70-NEXT: not.b32 %r11, %r10; +; SM70-NEXT: and.b32 %r12, %r11, %r2; +; SM70-NEXT: and.b32 %r13, %r16, %r3; +; SM70-NEXT: or.b32 %r14, %r13, %r12; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM70-NEXT: mov.b32 %r16, %r5; +; SM70-NEXT: @%p1 bra $L__BB92_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r15, %r5, %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r15; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") monotonic + ret i8 %retval +} + +define i8 @nand_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: nand_acquire_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<17>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [nand_acquire_i8_global_cta_param_0]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: ld.param.b8 %r6, [nand_acquire_i8_global_cta_param_1]; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r16, [%rd1]; +; SM70-NEXT: $L__BB93_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r10, %r16, %r4; +; SM70-NEXT: not.b32 %r11, %r10; +; SM70-NEXT: and.b32 %r12, %r11, %r2; +; SM70-NEXT: and.b32 %r13, %r16, %r3; +; SM70-NEXT: or.b32 %r14, %r13, %r12; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM70-NEXT: mov.b32 %r16, %r5; +; SM70-NEXT: @%p1 bra $L__BB93_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r15, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r15; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") acquire + ret i8 %retval +} + +define i8 @nand_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: nand_release_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<17>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [nand_release_i8_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.param.b8 %r6, [nand_release_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r16, [%rd1]; +; SM70-NEXT: $L__BB94_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r10, %r16, %r4; +; SM70-NEXT: not.b32 %r11, %r10; +; SM70-NEXT: and.b32 %r12, %r11, %r2; +; SM70-NEXT: and.b32 %r13, %r16, %r3; +; SM70-NEXT: or.b32 %r14, %r13, %r12; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM70-NEXT: mov.b32 %r16, %r5; +; SM70-NEXT: @%p1 bra $L__BB94_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r15, %r5, %r1; +; SM70-NEXT: st.param.b32 [func_retval0], %r15; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") release + ret i8 %retval +} + +define i8 @nand_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM70-LABEL: nand_seq_cst_i8_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<17>; +; SM70-NEXT: .reg .b64 %rd<3>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b64 %rd2, [nand_seq_cst_i8_global_cta_param_0]; +; SM70-NEXT: fence.sc.cta; +; SM70-NEXT: ld.param.b8 %r6, [nand_seq_cst_i8_global_cta_param_1]; +; SM70-NEXT: and.b64 %rd1, %rd2, -4; +; SM70-NEXT: cvt.u32.u64 %r7, %rd2; +; SM70-NEXT: and.b32 %r8, %r7, 3; +; SM70-NEXT: shl.b32 %r1, %r8, 3; +; SM70-NEXT: mov.b32 %r9, 255; +; SM70-NEXT: shl.b32 %r2, %r9, %r1; +; SM70-NEXT: not.b32 %r3, %r2; +; SM70-NEXT: shl.b32 %r4, %r6, %r1; +; SM70-NEXT: ld.global.b32 %r16, [%rd1]; +; SM70-NEXT: $L__BB95_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r10, %r16, %r4; +; SM70-NEXT: not.b32 %r11, %r10; +; SM70-NEXT: and.b32 %r12, %r11, %r2; +; SM70-NEXT: and.b32 %r13, %r16, %r3; +; SM70-NEXT: or.b32 %r14, %r13, %r12; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM70-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM70-NEXT: mov.b32 %r16, %r5; +; SM70-NEXT: @%p1 bra $L__BB95_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: shr.u32 %r15, %r5, %r1; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r15; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") seq_cst + ret i8 %retval +} + +define i32 @nand_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: nand_monotonic_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<6>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [nand_monotonic_i32_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [nand_monotonic_i32_global_cta_param_0]; +; SM70-NEXT: ld.global.b32 %r5, [%rd1]; +; SM70-NEXT: $L__BB96_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r3, %r5, %r2; +; SM70-NEXT: not.b32 %r4, %r3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM70-NEXT: mov.b32 %r5, %r1; +; SM70-NEXT: @%p1 bra $L__BB96_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") monotonic + ret i32 %retval +} + +define i32 @nand_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: nand_acquire_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<6>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [nand_acquire_i32_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [nand_acquire_i32_global_cta_param_0]; +; SM70-NEXT: ld.global.b32 %r5, [%rd1]; +; SM70-NEXT: $L__BB97_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r3, %r5, %r2; +; SM70-NEXT: not.b32 %r4, %r3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM70-NEXT: mov.b32 %r5, %r1; +; SM70-NEXT: @%p1 bra $L__BB97_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") acquire + ret i32 %retval +} + +define i32 @nand_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: nand_release_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<6>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [nand_release_i32_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [nand_release_i32_global_cta_param_0]; +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: ld.global.b32 %r5, [%rd1]; +; SM70-NEXT: $L__BB98_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r3, %r5, %r2; +; SM70-NEXT: not.b32 %r4, %r3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM70-NEXT: mov.b32 %r5, %r1; +; SM70-NEXT: @%p1 bra $L__BB98_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") release + ret i32 %retval +} + +define i32 @nand_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM70-LABEL: nand_seq_cst_i32_global_cta( +; SM70: { +; SM70-NEXT: .reg .pred %p<2>; +; SM70-NEXT: .reg .b32 %r<6>; +; SM70-NEXT: .reg .b64 %rd<2>; +; SM70-EMPTY: +; SM70-NEXT: // %bb.0: +; SM70-NEXT: ld.param.b32 %r2, [nand_seq_cst_i32_global_cta_param_1]; +; SM70-NEXT: ld.param.b64 %rd1, [nand_seq_cst_i32_global_cta_param_0]; +; SM70-NEXT: fence.sc.cta; +; SM70-NEXT: ld.global.b32 %r5, [%rd1]; +; SM70-NEXT: $L__BB99_1: // %atomicrmw.start +; SM70-NEXT: // =>This Inner Loop Header: Depth=1 +; SM70-NEXT: and.b32 %r3, %r5, %r2; +; SM70-NEXT: not.b32 %r4, %r3; +; SM70-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM70-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM70-NEXT: mov.b32 %r5, %r1; +; SM70-NEXT: @%p1 bra $L__BB99_1; +; SM70-NEXT: // %bb.2: // %atomicrmw.end +; SM70-NEXT: fence.acq_rel.cta; +; SM70-NEXT: st.param.b32 [func_retval0], %r1; +; SM70-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") seq_cst + ret i32 %retval +} + diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll new file mode 100644 index 0000000000000..bc918023b2658 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll @@ -0,0 +1,2983 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx87 | FileCheck %s --check-prefix=SM90 +; RUN: %if ptxas-sm_90 && ptxas-isa-8.7 %{ llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx87 | %ptxas-verify -arch=sm_90 %} + +define i8 @xchg_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: xchg_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<14>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r5, [xchg_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r6, %rd2; +; SM90-NEXT: and.b32 %r7, %r6, 3; +; SM90-NEXT: shl.b32 %r1, %r7, 3; +; SM90-NEXT: mov.b32 %r8, 255; +; SM90-NEXT: shl.b32 %r9, %r8, %r1; +; SM90-NEXT: not.b32 %r2, %r9; +; SM90-NEXT: shl.b32 %r3, %r5, %r1; +; SM90-NEXT: ld.global.b32 %r13, [%rd1]; +; SM90-NEXT: $L__BB0_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r10, %r13, %r2; +; SM90-NEXT: or.b32 %r11, %r10, %r3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r4, [%rd1], %r13, %r11; +; SM90-NEXT: setp.ne.b32 %p1, %r4, %r13; +; SM90-NEXT: mov.b32 %r13, %r4; +; SM90-NEXT: @%p1 bra $L__BB0_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r12, %r4, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r12; +; SM90-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @xchg_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: xchg_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<14>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b16 %r5, [xchg_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r6, %rd2; +; SM90-NEXT: and.b32 %r7, %r6, 3; +; SM90-NEXT: shl.b32 %r1, %r7, 3; +; SM90-NEXT: mov.b32 %r8, 65535; +; SM90-NEXT: shl.b32 %r9, %r8, %r1; +; SM90-NEXT: not.b32 %r2, %r9; +; SM90-NEXT: shl.b32 %r3, %r5, %r1; +; SM90-NEXT: ld.global.b32 %r13, [%rd1]; +; SM90-NEXT: $L__BB1_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r10, %r13, %r2; +; SM90-NEXT: or.b32 %r11, %r10, %r3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r4, [%rd1], %r13, %r11; +; SM90-NEXT: setp.ne.b32 %p1, %r4, %r13; +; SM90-NEXT: mov.b32 %r13, %r4; +; SM90-NEXT: @%p1 bra $L__BB1_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r12, %r4, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r12; +; SM90-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @xchg_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: xchg_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [xchg_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [xchg_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.exch.b32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @xchg_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: xchg_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [xchg_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.exch.b64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw xchg ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @add_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: add_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r6, [add_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB4_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: add.s32 %r10, %r15, %r4; +; SM90-NEXT: and.b32 %r11, %r10, %r2; +; SM90-NEXT: and.b32 %r12, %r15, %r3; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM90-NEXT: mov.b32 %r15, %r5; +; SM90-NEXT: @%p1 bra $L__BB4_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @add_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: add_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b16 %r6, [add_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 65535; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB5_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: add.s32 %r10, %r15, %r4; +; SM90-NEXT: and.b32 %r11, %r10, %r2; +; SM90-NEXT: and.b32 %r12, %r15, %r3; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM90-NEXT: mov.b32 %r15, %r5; +; SM90-NEXT: @%p1 bra $L__BB5_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @add_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: add_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.add.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @add_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: add_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.add.u64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @sub_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: sub_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r6, [sub_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB8_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: sub.s32 %r10, %r15, %r4; +; SM90-NEXT: and.b32 %r11, %r10, %r2; +; SM90-NEXT: and.b32 %r12, %r15, %r3; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM90-NEXT: mov.b32 %r15, %r5; +; SM90-NEXT: @%p1 bra $L__BB8_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @sub_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: sub_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b16 %r6, [sub_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 65535; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB9_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: sub.s32 %r10, %r15, %r4; +; SM90-NEXT: and.b32 %r11, %r10, %r2; +; SM90-NEXT: and.b32 %r12, %r15, %r3; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM90-NEXT: mov.b32 %r15, %r5; +; SM90-NEXT: @%p1 bra $L__BB9_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @sub_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: sub_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<4>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [sub_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [sub_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: neg.s32 %r2, %r1; +; SM90-NEXT: atom.acq_rel.cta.global.add.u32 %r3, [%rd1], %r2; +; SM90-NEXT: st.param.b32 [func_retval0], %r3; +; SM90-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @sub_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: sub_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<5>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [sub_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: neg.s64 %rd3, %rd2; +; SM90-NEXT: atom.acq_rel.cta.global.add.u64 %rd4, [%rd1], %rd3; +; SM90-NEXT: st.param.b64 [func_retval0], %rd4; +; SM90-NEXT: ret; + %retval = atomicrmw sub ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @and_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: and_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<12>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [and_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r1, [and_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd2, %rd1, -4; +; SM90-NEXT: cvt.u32.u64 %r2, %rd1; +; SM90-NEXT: and.b32 %r3, %r2, 3; +; SM90-NEXT: shl.b32 %r4, %r3, 3; +; SM90-NEXT: mov.b32 %r5, 255; +; SM90-NEXT: shl.b32 %r6, %r5, %r4; +; SM90-NEXT: not.b32 %r7, %r6; +; SM90-NEXT: shl.b32 %r8, %r1, %r4; +; SM90-NEXT: or.b32 %r9, %r8, %r7; +; SM90-NEXT: atom.relaxed.cta.global.and.b32 %r10, [%rd2], %r9; +; SM90-NEXT: shr.u32 %r11, %r10, %r4; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r11; +; SM90-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @and_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: and_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<12>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [and_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b16 %r1, [and_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd2, %rd1, -4; +; SM90-NEXT: cvt.u32.u64 %r2, %rd1; +; SM90-NEXT: and.b32 %r3, %r2, 3; +; SM90-NEXT: shl.b32 %r4, %r3, 3; +; SM90-NEXT: mov.b32 %r5, 65535; +; SM90-NEXT: shl.b32 %r6, %r5, %r4; +; SM90-NEXT: not.b32 %r7, %r6; +; SM90-NEXT: shl.b32 %r8, %r1, %r4; +; SM90-NEXT: or.b32 %r9, %r8, %r7; +; SM90-NEXT: atom.relaxed.cta.global.and.b32 %r10, [%rd2], %r9; +; SM90-NEXT: shr.u32 %r11, %r10, %r4; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r11; +; SM90-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @and_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: and_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [and_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [and_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.and.b32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @and_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: and_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [and_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [and_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.and.b64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw and ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @nand_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: nand_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<17>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r6, [nand_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r16, [%rd1]; +; SM90-NEXT: $L__BB16_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r10, %r16, %r4; +; SM90-NEXT: not.b32 %r11, %r10; +; SM90-NEXT: and.b32 %r12, %r11, %r2; +; SM90-NEXT: and.b32 %r13, %r16, %r3; +; SM90-NEXT: or.b32 %r14, %r13, %r12; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM90-NEXT: mov.b32 %r16, %r5; +; SM90-NEXT: @%p1 bra $L__BB16_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r15, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r15; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @nand_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: nand_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<17>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b16 %r6, [nand_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 65535; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r16, [%rd1]; +; SM90-NEXT: $L__BB17_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r10, %r16, %r4; +; SM90-NEXT: not.b32 %r11, %r10; +; SM90-NEXT: and.b32 %r12, %r11, %r2; +; SM90-NEXT: and.b32 %r13, %r16, %r3; +; SM90-NEXT: or.b32 %r14, %r13, %r12; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM90-NEXT: mov.b32 %r16, %r5; +; SM90-NEXT: @%p1 bra $L__BB17_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r15, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r15; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @nand_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: nand_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<6>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r5, [%rd1]; +; SM90-NEXT: $L__BB18_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r3, %r5, %r2; +; SM90-NEXT: not.b32 %r4, %r3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM90-NEXT: mov.b32 %r5, %r1; +; SM90-NEXT: @%p1 bra $L__BB18_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @nand_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: nand_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b64 %rd<7>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM90-NEXT: $L__BB19_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b64 %rd4, %rd6, %rd3; +; SM90-NEXT: not.b64 %rd5, %rd4; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM90-NEXT: setp.ne.b64 %p1, %rd1, %rd6; +; SM90-NEXT: mov.b64 %rd6, %rd1; +; SM90-NEXT: @%p1 bra $L__BB19_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @or_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: or_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<8>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [or_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r1, [or_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd2, %rd1, -4; +; SM90-NEXT: cvt.u32.u64 %r2, %rd1; +; SM90-NEXT: and.b32 %r3, %r2, 3; +; SM90-NEXT: shl.b32 %r4, %r3, 3; +; SM90-NEXT: shl.b32 %r5, %r1, %r4; +; SM90-NEXT: atom.relaxed.cta.global.or.b32 %r6, [%rd2], %r5; +; SM90-NEXT: shr.u32 %r7, %r6, %r4; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r7; +; SM90-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @or_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: or_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<8>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [or_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b16 %r1, [or_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd2, %rd1, -4; +; SM90-NEXT: cvt.u32.u64 %r2, %rd1; +; SM90-NEXT: and.b32 %r3, %r2, 3; +; SM90-NEXT: shl.b32 %r4, %r3, 3; +; SM90-NEXT: shl.b32 %r5, %r1, %r4; +; SM90-NEXT: atom.relaxed.cta.global.or.b32 %r6, [%rd2], %r5; +; SM90-NEXT: shr.u32 %r7, %r6, %r4; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r7; +; SM90-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @or_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: or_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [or_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [or_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.or.b32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @or_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: or_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [or_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [or_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.or.b64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw or ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @xor_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: xor_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<8>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r1, [xor_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd2, %rd1, -4; +; SM90-NEXT: cvt.u32.u64 %r2, %rd1; +; SM90-NEXT: and.b32 %r3, %r2, 3; +; SM90-NEXT: shl.b32 %r4, %r3, 3; +; SM90-NEXT: shl.b32 %r5, %r1, %r4; +; SM90-NEXT: atom.relaxed.cta.global.xor.b32 %r6, [%rd2], %r5; +; SM90-NEXT: shr.u32 %r7, %r6, %r4; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r7; +; SM90-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @xor_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: xor_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<8>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b16 %r1, [xor_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd2, %rd1, -4; +; SM90-NEXT: cvt.u32.u64 %r2, %rd1; +; SM90-NEXT: and.b32 %r3, %r2, 3; +; SM90-NEXT: shl.b32 %r4, %r3, 3; +; SM90-NEXT: shl.b32 %r5, %r1, %r4; +; SM90-NEXT: atom.relaxed.cta.global.xor.b32 %r6, [%rd2], %r5; +; SM90-NEXT: shr.u32 %r7, %r6, %r4; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r7; +; SM90-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @xor_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: xor_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [xor_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.xor.b32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @xor_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: xor_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [xor_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.xor.b64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw xor ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @max_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: max_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<5>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b8 %rs1, [max_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [max_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 255; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: cvt.s16.s8 %rs3, %rs1; +; SM90-NEXT: $L__BB28_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r15, %r1; +; SM90-NEXT: cvt.s8.s32 %rs2, %r8; +; SM90-NEXT: max.s16 %rs4, %rs2, %rs3; +; SM90-NEXT: cvt.u32.u16 %r9, %rs4; +; SM90-NEXT: and.b32 %r10, %r9, 255; +; SM90-NEXT: shl.b32 %r11, %r10, %r1; +; SM90-NEXT: and.b32 %r12, %r15, %r2; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r15; +; SM90-NEXT: mov.b32 %r15, %r3; +; SM90-NEXT: @%p1 bra $L__BB28_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @max_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: max_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [max_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [max_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB29_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: max.s16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB29_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @max_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: max_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [max_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [max_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.max.s32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @max_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: max_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [max_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [max_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.max.s64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw max ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @min_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: min_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<5>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b8 %rs1, [min_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [min_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 255; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: cvt.s16.s8 %rs3, %rs1; +; SM90-NEXT: $L__BB32_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r15, %r1; +; SM90-NEXT: cvt.s8.s32 %rs2, %r8; +; SM90-NEXT: min.s16 %rs4, %rs2, %rs3; +; SM90-NEXT: cvt.u32.u16 %r9, %rs4; +; SM90-NEXT: and.b32 %r10, %r9, 255; +; SM90-NEXT: shl.b32 %r11, %r10, %r1; +; SM90-NEXT: and.b32 %r12, %r15, %r2; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r15; +; SM90-NEXT: mov.b32 %r15, %r3; +; SM90-NEXT: @%p1 bra $L__BB32_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @min_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: min_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [min_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [min_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB33_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: min.s16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB33_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @min_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: min_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.min.s32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @min_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: min_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [min_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.min.s64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw min ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @umax_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: umax_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<5>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b8 %rs1, [umax_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 255; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB36_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: and.b16 %rs3, %rs2, 255; +; SM90-NEXT: max.u16 %rs4, %rs3, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs4; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB36_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @umax_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: umax_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [umax_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB37_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: max.u16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB37_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @umax_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: umax_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.max.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @umax_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: umax_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.max.u64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw umax ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @umin_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: umin_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<5>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b8 %rs1, [umin_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 255; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB40_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: and.b16 %rs3, %rs2, 255; +; SM90-NEXT: min.u16 %rs4, %rs3, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs4; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB40_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @umin_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: umin_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [umin_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB41_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: min.u16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB41_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @umin_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: umin_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [umin_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [umin_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.min.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @umin_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: umin_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [umin_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.min.u64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw umin ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @uinc_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: uinc_wrap_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<3>; +; SM90-NEXT: .reg .b16 %rs<6>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b8 %rs1, [uinc_wrap_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 255; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB44_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r15, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: and.b16 %rs3, %rs2, 255; +; SM90-NEXT: add.s16 %rs4, %rs2, 1; +; SM90-NEXT: setp.ge.u16 %p1, %rs3, %rs1; +; SM90-NEXT: selp.b16 %rs5, 0, %rs4, %p1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs5; +; SM90-NEXT: and.b32 %r10, %r9, 255; +; SM90-NEXT: shl.b32 %r11, %r10, %r1; +; SM90-NEXT: and.b32 %r12, %r15, %r2; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p2, %r3, %r15; +; SM90-NEXT: mov.b32 %r15, %r3; +; SM90-NEXT: @%p2 bra $L__BB44_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @uinc_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: uinc_wrap_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<3>; +; SM90-NEXT: .reg .b16 %rs<5>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [uinc_wrap_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB45_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: add.s16 %rs3, %rs2, 1; +; SM90-NEXT: setp.ge.u16 %p1, %rs2, %rs1; +; SM90-NEXT: selp.b16 %rs4, 0, %rs3, %p1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs4; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p2, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p2 bra $L__BB45_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @uinc_wrap_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: uinc_wrap_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [uinc_wrap_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [uinc_wrap_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.inc.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @uinc_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: uinc_wrap_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<3>; +; SM90-NEXT: .reg .b64 %rd<7>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [uinc_wrap_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM90-NEXT: $L__BB47_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: add.s64 %rd4, %rd6, 1; +; SM90-NEXT: setp.ge.u64 %p1, %rd6, %rd3; +; SM90-NEXT: selp.b64 %rd5, 0, %rd4, %p1; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM90-NEXT: setp.ne.b64 %p2, %rd1, %rd6; +; SM90-NEXT: mov.b64 %rd6, %rd1; +; SM90-NEXT: @%p2 bra $L__BB47_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @udec_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: udec_wrap_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<4>; +; SM90-NEXT: .reg .b16 %rs<7>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b8 %rs1, [udec_wrap_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 255; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB48_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r15, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: and.b16 %rs3, %rs2, 255; +; SM90-NEXT: add.s16 %rs4, %rs2, -1; +; SM90-NEXT: setp.eq.b16 %p1, %rs3, 0; +; SM90-NEXT: setp.gt.u16 %p2, %rs3, %rs1; +; SM90-NEXT: selp.b16 %rs5, %rs1, %rs4, %p2; +; SM90-NEXT: selp.b16 %rs6, %rs1, %rs5, %p1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs6; +; SM90-NEXT: and.b32 %r10, %r9, 255; +; SM90-NEXT: shl.b32 %r11, %r10, %r1; +; SM90-NEXT: and.b32 %r12, %r15, %r2; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p3, %r3, %r15; +; SM90-NEXT: mov.b32 %r15, %r3; +; SM90-NEXT: @%p3 bra $L__BB48_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @udec_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: udec_wrap_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<4>; +; SM90-NEXT: .reg .b16 %rs<6>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [udec_wrap_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB49_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: add.s16 %rs3, %rs2, -1; +; SM90-NEXT: setp.eq.b16 %p1, %rs2, 0; +; SM90-NEXT: setp.gt.u16 %p2, %rs2, %rs1; +; SM90-NEXT: selp.b16 %rs4, %rs1, %rs3, %p2; +; SM90-NEXT: selp.b16 %rs5, %rs1, %rs4, %p1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs5; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p3, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p3 bra $L__BB49_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @udec_wrap_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: udec_wrap_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [udec_wrap_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [udec_wrap_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.dec.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @udec_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: udec_wrap_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<4>; +; SM90-NEXT: .reg .b64 %rd<8>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [udec_wrap_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd7, [%rd2]; +; SM90-NEXT: $L__BB51_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: add.s64 %rd4, %rd7, -1; +; SM90-NEXT: setp.eq.b64 %p1, %rd7, 0; +; SM90-NEXT: setp.gt.u64 %p2, %rd7, %rd3; +; SM90-NEXT: selp.b64 %rd5, %rd3, %rd4, %p2; +; SM90-NEXT: selp.b64 %rd6, %rd3, %rd5, %p1; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd7, %rd6; +; SM90-NEXT: setp.ne.b64 %p3, %rd1, %rd7; +; SM90-NEXT: mov.b64 %rd7, %rd1; +; SM90-NEXT: @%p3 bra $L__BB51_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @usub_cond_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: usub_cond_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<3>; +; SM90-NEXT: .reg .b16 %rs<6>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b8 %rs1, [usub_cond_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 255; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB52_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r15, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: and.b16 %rs3, %rs2, 255; +; SM90-NEXT: setp.ge.u16 %p1, %rs3, %rs1; +; SM90-NEXT: sub.s16 %rs4, %rs2, %rs1; +; SM90-NEXT: selp.b16 %rs5, %rs4, %rs2, %p1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs5; +; SM90-NEXT: and.b32 %r10, %r9, 255; +; SM90-NEXT: shl.b32 %r11, %r10, %r1; +; SM90-NEXT: and.b32 %r12, %r15, %r2; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p2, %r3, %r15; +; SM90-NEXT: mov.b32 %r15, %r3; +; SM90-NEXT: @%p2 bra $L__BB52_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @usub_cond_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: usub_cond_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<3>; +; SM90-NEXT: .reg .b16 %rs<5>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [usub_cond_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB53_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: setp.ge.u16 %p1, %rs2, %rs1; +; SM90-NEXT: sub.s16 %rs3, %rs2, %rs1; +; SM90-NEXT: selp.b16 %rs4, %rs3, %rs2, %p1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs4; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p2, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p2 bra $L__BB53_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @usub_cond_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: usub_cond_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<3>; +; SM90-NEXT: .reg .b32 %r<6>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [usub_cond_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [usub_cond_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r5, [%rd1]; +; SM90-NEXT: $L__BB54_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: setp.ge.u32 %p1, %r5, %r2; +; SM90-NEXT: sub.s32 %r3, %r5, %r2; +; SM90-NEXT: selp.b32 %r4, %r3, %r5, %p1; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM90-NEXT: setp.ne.b32 %p2, %r1, %r5; +; SM90-NEXT: mov.b32 %r5, %r1; +; SM90-NEXT: @%p2 bra $L__BB54_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @usub_cond_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: usub_cond_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<3>; +; SM90-NEXT: .reg .b64 %rd<7>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [usub_cond_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM90-NEXT: $L__BB55_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: setp.ge.u64 %p1, %rd6, %rd3; +; SM90-NEXT: sub.s64 %rd4, %rd6, %rd3; +; SM90-NEXT: selp.b64 %rd5, %rd4, %rd6, %p1; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM90-NEXT: setp.ne.b64 %p2, %rd1, %rd6; +; SM90-NEXT: mov.b64 %rd6, %rd1; +; SM90-NEXT: @%p2 bra $L__BB55_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw usub_cond ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define i8 @usub_sat_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: usub_sat_acq_rel_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<6>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b8 %rs1, [usub_sat_acq_rel_i8_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 255; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB56_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: and.b16 %rs3, %rs2, 255; +; SM90-NEXT: max.u16 %rs4, %rs3, %rs1; +; SM90-NEXT: sub.s16 %rs5, %rs4, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs5; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB56_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel + ret i8 %retval +} + +define i16 @usub_sat_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) { +; SM90-LABEL: usub_sat_acq_rel_i16_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<5>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [usub_sat_acq_rel_i16_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i16_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB57_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: max.u16 %rs3, %rs2, %rs1; +; SM90-NEXT: sub.s16 %rs4, %rs3, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs4; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB57_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel + ret i16 %retval +} + +define i32 @usub_sat_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: usub_sat_acq_rel_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<6>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [usub_sat_acq_rel_i32_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [usub_sat_acq_rel_i32_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r5, [%rd1]; +; SM90-NEXT: $L__BB58_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: max.u32 %r3, %r5, %r2; +; SM90-NEXT: sub.s32 %r4, %r3, %r2; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM90-NEXT: mov.b32 %r5, %r1; +; SM90-NEXT: @%p1 bra $L__BB58_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel + ret i32 %retval +} + +define i64 @usub_sat_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) { +; SM90-LABEL: usub_sat_acq_rel_i64_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b64 %rd<7>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [usub_sat_acq_rel_i64_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i64_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd6, [%rd2]; +; SM90-NEXT: $L__BB59_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: max.u64 %rd4, %rd6, %rd3; +; SM90-NEXT: sub.s64 %rd5, %rd4, %rd3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd6, %rd5; +; SM90-NEXT: setp.ne.b64 %p1, %rd1, %rd6; +; SM90-NEXT: mov.b64 %rd6, %rd1; +; SM90-NEXT: @%p1 bra $L__BB59_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw usub_sat ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel + ret i64 %retval +} + +define float @fadd_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM90-LABEL: fadd_acq_rel_float_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.add.f32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM90-LABEL: fsub_acq_rel_float_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<5>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [fsub_acq_rel_float_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r4, [%rd1]; +; SM90-NEXT: $L__BB61_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: sub.rn.f32 %r3, %r4, %r2; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM90-NEXT: mov.b32 %r4, %r1; +; SM90-NEXT: @%p1 bra $L__BB61_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM90-LABEL: fmin_acq_rel_float_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<5>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [fmin_acq_rel_float_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r4, [%rd1]; +; SM90-NEXT: $L__BB62_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: min.f32 %r3, %r4, %r2; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM90-NEXT: mov.b32 %r4, %r1; +; SM90-NEXT: @%p1 bra $L__BB62_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM90-LABEL: fmax_acq_rel_float_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<5>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [fmax_acq_rel_float_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r4, [%rd1]; +; SM90-NEXT: $L__BB63_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: max.f32 %r3, %r4, %r2; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM90-NEXT: mov.b32 %r4, %r1; +; SM90-NEXT: @%p1 bra $L__BB63_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM90-LABEL: fminimum_acq_rel_float_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<5>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r4, [%rd1]; +; SM90-NEXT: $L__BB64_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: min.NaN.f32 %r3, %r4, %r2; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM90-NEXT: mov.b32 %r4, %r1; +; SM90-NEXT: @%p1 bra $L__BB64_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val) { +; SM90-LABEL: fmaximum_acq_rel_float_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<5>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r4, [%rd1]; +; SM90-NEXT: $L__BB65_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: max.NaN.f32 %r3, %r4, %r2; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r4, %r3; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r4; +; SM90-NEXT: mov.b32 %r4, %r1; +; SM90-NEXT: @%p1 bra $L__BB65_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, float %val syncscope("block") acq_rel + ret float %retval +} + +define double @fadd_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM90-LABEL: fadd_acq_rel_double_global_cta( +; SM90: { +; SM90-NEXT: .reg .b64 %rd<4>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_global_cta_param_0]; +; SM90-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.add.f64 %rd3, [%rd1], %rd2; +; SM90-NEXT: st.param.b64 [func_retval0], %rd3; +; SM90-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fsub_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM90-LABEL: fsub_acq_rel_double_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b64 %rd<6>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [fsub_acq_rel_double_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_double_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM90-NEXT: $L__BB67_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: sub.rn.f64 %rd4, %rd5, %rd3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM90-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM90-NEXT: mov.b64 %rd5, %rd1; +; SM90-NEXT: @%p1 bra $L__BB67_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmin_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM90-LABEL: fmin_acq_rel_double_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b64 %rd<6>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [fmin_acq_rel_double_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_double_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM90-NEXT: $L__BB68_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: min.f64 %rd4, %rd5, %rd3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM90-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM90-NEXT: mov.b64 %rd5, %rd1; +; SM90-NEXT: @%p1 bra $L__BB68_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmax_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM90-LABEL: fmax_acq_rel_double_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b64 %rd<6>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [fmax_acq_rel_double_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_double_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd5, [%rd2]; +; SM90-NEXT: $L__BB69_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: max.f64 %rd4, %rd5, %rd3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd5, %rd4; +; SM90-NEXT: setp.ne.b64 %p1, %rd1, %rd5; +; SM90-NEXT: mov.b64 %rd5, %rd1; +; SM90-NEXT: @%p1 bra $L__BB69_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM90-LABEL: fminimum_acq_rel_double_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<6>; +; SM90-NEXT: .reg .b64 %rd<10>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [fminimum_acq_rel_double_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_double_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd9, [%rd2]; +; SM90-NEXT: setp.eq.b64 %p3, %rd3, -9223372036854775808; +; SM90-NEXT: $L__BB70_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: setp.nan.f64 %p1, %rd9, %rd3; +; SM90-NEXT: min.f64 %rd4, %rd9, %rd3; +; SM90-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1; +; SM90-NEXT: setp.eq.b64 %p2, %rd9, -9223372036854775808; +; SM90-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2; +; SM90-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3; +; SM90-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000; +; SM90-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8; +; SM90-NEXT: setp.ne.b64 %p5, %rd1, %rd9; +; SM90-NEXT: mov.b64 %rd9, %rd1; +; SM90-NEXT: @%p5 bra $L__BB70_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define double @fmaximum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %val) { +; SM90-LABEL: fmaximum_acq_rel_double_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<6>; +; SM90-NEXT: .reg .b64 %rd<10>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd3, [fmaximum_acq_rel_double_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_double_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b64 %rd9, [%rd2]; +; SM90-NEXT: setp.eq.b64 %p3, %rd3, 0; +; SM90-NEXT: $L__BB71_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: setp.nan.f64 %p1, %rd9, %rd3; +; SM90-NEXT: max.f64 %rd4, %rd9, %rd3; +; SM90-NEXT: selp.f64 %rd5, 0d7FF8000000000000, %rd4, %p1; +; SM90-NEXT: setp.eq.b64 %p2, %rd9, 0; +; SM90-NEXT: selp.f64 %rd6, %rd9, %rd5, %p2; +; SM90-NEXT: selp.f64 %rd7, %rd3, %rd6, %p3; +; SM90-NEXT: setp.eq.f64 %p4, %rd5, 0d0000000000000000; +; SM90-NEXT: selp.f64 %rd8, %rd7, %rd5, %p4; +; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd1, [%rd2], %rd9, %rd8; +; SM90-NEXT: setp.ne.b64 %p5, %rd1, %rd9; +; SM90-NEXT: mov.b64 %rd9, %rd1; +; SM90-NEXT: @%p5 bra $L__BB71_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b64 [func_retval0], %rd1; +; SM90-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, double %val syncscope("block") acq_rel + ret double %retval +} + +define half @fadd_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM90-LABEL: fadd_acq_rel_half_global_cta( +; SM90: { +; SM90-NEXT: .reg .b16 %rs<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_half_global_cta_param_0]; +; SM90-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.add.noftz.f16 %rs2, [%rd1], %rs1; +; SM90-NEXT: st.param.b16 [func_retval0], %rs2; +; SM90-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM90-LABEL: fsub_acq_rel_half_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB73_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: sub.rn.f16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB73_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM90-LABEL: fmin_acq_rel_half_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB74_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: min.f16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB74_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM90-LABEL: fmax_acq_rel_half_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB75_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: max.f16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB75_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM90-LABEL: fminimum_acq_rel_half_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB76_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: min.NaN.f16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB76_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) { +; SM90-LABEL: fmaximum_acq_rel_half_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB77_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: max.NaN.f16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB77_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, half %val syncscope("block") acq_rel + ret half %retval +} + +define bfloat @fadd_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM90-LABEL: fadd_acq_rel_bfloat_global_cta( +; SM90: { +; SM90-NEXT: .reg .b16 %rs<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_bfloat_global_cta_param_0]; +; SM90-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_bfloat_global_cta_param_1]; +; SM90-NEXT: atom.acq_rel.cta.global.add.noftz.bf16 %rs2, [%rd1], %rs1; +; SM90-NEXT: st.param.b16 [func_retval0], %rs2; +; SM90-NEXT: ret; + %retval = atomicrmw fadd ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fsub_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM90-LABEL: fsub_acq_rel_bfloat_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_bfloat_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_bfloat_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB79_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: sub.rn.bf16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB79_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fsub ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmin_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM90-LABEL: fmin_acq_rel_bfloat_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_bfloat_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_bfloat_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB80_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: min.bf16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB80_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fmin ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmax_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM90-LABEL: fmax_acq_rel_bfloat_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_bfloat_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_bfloat_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB81_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: max.bf16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB81_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fmax ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM90-LABEL: fminimum_acq_rel_bfloat_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_bfloat_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_bfloat_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB82_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: min.NaN.bf16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB82_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fminimum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %val) { +; SM90-LABEL: fmaximum_acq_rel_bfloat_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b16 %rs<4>; +; SM90-NEXT: .reg .b32 %r<15>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_bfloat_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_bfloat_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r4, %rd2; +; SM90-NEXT: and.b32 %r5, %r4, 3; +; SM90-NEXT: shl.b32 %r1, %r5, 3; +; SM90-NEXT: mov.b32 %r6, 65535; +; SM90-NEXT: shl.b32 %r7, %r6, %r1; +; SM90-NEXT: not.b32 %r2, %r7; +; SM90-NEXT: ld.global.b32 %r14, [%rd1]; +; SM90-NEXT: $L__BB83_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: shr.u32 %r8, %r14, %r1; +; SM90-NEXT: cvt.u16.u32 %rs2, %r8; +; SM90-NEXT: max.NaN.bf16 %rs3, %rs2, %rs1; +; SM90-NEXT: cvt.u32.u16 %r9, %rs3; +; SM90-NEXT: shl.b32 %r10, %r9, %r1; +; SM90-NEXT: and.b32 %r11, %r14, %r2; +; SM90-NEXT: or.b32 %r12, %r11, %r10; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r14, %r12; +; SM90-NEXT: setp.ne.b32 %p1, %r3, %r14; +; SM90-NEXT: mov.b32 %r14, %r3; +; SM90-NEXT: @%p1 bra $L__BB83_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r13, %r3, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b16 [func_retval0], %r13; +; SM90-NEXT: ret; + %retval = atomicrmw fmaximum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel + ret bfloat %retval +} + +define i8 @add_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: add_monotonic_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [add_monotonic_i8_global_cta_param_0]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: ld.param.b8 %r6, [add_monotonic_i8_global_cta_param_1]; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB84_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: add.s32 %r10, %r15, %r4; +; SM90-NEXT: and.b32 %r11, %r10, %r2; +; SM90-NEXT: and.b32 %r12, %r15, %r3; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM90-NEXT: mov.b32 %r15, %r5; +; SM90-NEXT: @%p1 bra $L__BB84_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r5, %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") monotonic + ret i8 %retval +} + +define i8 @add_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: add_acquire_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [add_acquire_i8_global_cta_param_0]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: ld.param.b8 %r6, [add_acquire_i8_global_cta_param_1]; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB85_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: add.s32 %r10, %r15, %r4; +; SM90-NEXT: and.b32 %r11, %r10, %r2; +; SM90-NEXT: and.b32 %r12, %r15, %r3; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM90-NEXT: mov.b32 %r15, %r5; +; SM90-NEXT: @%p1 bra $L__BB85_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") acquire + ret i8 %retval +} + +define i8 @add_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: add_release_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [add_release_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r6, [add_release_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB86_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: add.s32 %r10, %r15, %r4; +; SM90-NEXT: and.b32 %r11, %r10, %r2; +; SM90-NEXT: and.b32 %r12, %r15, %r3; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM90-NEXT: mov.b32 %r15, %r5; +; SM90-NEXT: @%p1 bra $L__BB86_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r5, %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") release + ret i8 %retval +} + +define i8 @add_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: add_seq_cst_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<16>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [add_seq_cst_i8_global_cta_param_0]; +; SM90-NEXT: fence.sc.cta; +; SM90-NEXT: ld.param.b8 %r6, [add_seq_cst_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r15, [%rd1]; +; SM90-NEXT: $L__BB87_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: add.s32 %r10, %r15, %r4; +; SM90-NEXT: and.b32 %r11, %r10, %r2; +; SM90-NEXT: and.b32 %r12, %r15, %r3; +; SM90-NEXT: or.b32 %r13, %r12, %r11; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r15, %r13; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r15; +; SM90-NEXT: mov.b32 %r15, %r5; +; SM90-NEXT: @%p1 bra $L__BB87_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r14, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r14; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") seq_cst + ret i8 %retval +} + +define i32 @add_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: add_monotonic_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [add_monotonic_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [add_monotonic_i32_global_cta_param_1]; +; SM90-NEXT: atom.relaxed.cta.global.add.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") monotonic + ret i32 %retval +} + +define i32 @add_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: add_acquire_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [add_acquire_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [add_acquire_i32_global_cta_param_1]; +; SM90-NEXT: atom.acquire.cta.global.add.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") acquire + ret i32 %retval +} + +define i32 @add_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: add_release_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [add_release_i32_global_cta_param_0]; +; SM90-NEXT: ld.param.b32 %r1, [add_release_i32_global_cta_param_1]; +; SM90-NEXT: atom.release.cta.global.add.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") release + ret i32 %retval +} + +define i32 @add_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: add_seq_cst_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .b32 %r<3>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd1, [add_seq_cst_i32_global_cta_param_0]; +; SM90-NEXT: fence.sc.cta; +; SM90-NEXT: ld.param.b32 %r1, [add_seq_cst_i32_global_cta_param_1]; +; SM90-NEXT: atom.acquire.cta.global.add.u32 %r2, [%rd1], %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r2; +; SM90-NEXT: ret; + %retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") seq_cst + ret i32 %retval +} + +define i8 @nand_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: nand_monotonic_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<17>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [nand_monotonic_i8_global_cta_param_0]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: ld.param.b8 %r6, [nand_monotonic_i8_global_cta_param_1]; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r16, [%rd1]; +; SM90-NEXT: $L__BB92_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r10, %r16, %r4; +; SM90-NEXT: not.b32 %r11, %r10; +; SM90-NEXT: and.b32 %r12, %r11, %r2; +; SM90-NEXT: and.b32 %r13, %r16, %r3; +; SM90-NEXT: or.b32 %r14, %r13, %r12; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM90-NEXT: mov.b32 %r16, %r5; +; SM90-NEXT: @%p1 bra $L__BB92_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r15, %r5, %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r15; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") monotonic + ret i8 %retval +} + +define i8 @nand_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: nand_acquire_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<17>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [nand_acquire_i8_global_cta_param_0]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: ld.param.b8 %r6, [nand_acquire_i8_global_cta_param_1]; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r16, [%rd1]; +; SM90-NEXT: $L__BB93_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r10, %r16, %r4; +; SM90-NEXT: not.b32 %r11, %r10; +; SM90-NEXT: and.b32 %r12, %r11, %r2; +; SM90-NEXT: and.b32 %r13, %r16, %r3; +; SM90-NEXT: or.b32 %r14, %r13, %r12; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM90-NEXT: mov.b32 %r16, %r5; +; SM90-NEXT: @%p1 bra $L__BB93_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r15, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r15; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") acquire + ret i8 %retval +} + +define i8 @nand_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: nand_release_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<17>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [nand_release_i8_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.param.b8 %r6, [nand_release_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r16, [%rd1]; +; SM90-NEXT: $L__BB94_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r10, %r16, %r4; +; SM90-NEXT: not.b32 %r11, %r10; +; SM90-NEXT: and.b32 %r12, %r11, %r2; +; SM90-NEXT: and.b32 %r13, %r16, %r3; +; SM90-NEXT: or.b32 %r14, %r13, %r12; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM90-NEXT: mov.b32 %r16, %r5; +; SM90-NEXT: @%p1 bra $L__BB94_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r15, %r5, %r1; +; SM90-NEXT: st.param.b32 [func_retval0], %r15; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") release + ret i8 %retval +} + +define i8 @nand_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) { +; SM90-LABEL: nand_seq_cst_i8_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<17>; +; SM90-NEXT: .reg .b64 %rd<3>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b64 %rd2, [nand_seq_cst_i8_global_cta_param_0]; +; SM90-NEXT: fence.sc.cta; +; SM90-NEXT: ld.param.b8 %r6, [nand_seq_cst_i8_global_cta_param_1]; +; SM90-NEXT: and.b64 %rd1, %rd2, -4; +; SM90-NEXT: cvt.u32.u64 %r7, %rd2; +; SM90-NEXT: and.b32 %r8, %r7, 3; +; SM90-NEXT: shl.b32 %r1, %r8, 3; +; SM90-NEXT: mov.b32 %r9, 255; +; SM90-NEXT: shl.b32 %r2, %r9, %r1; +; SM90-NEXT: not.b32 %r3, %r2; +; SM90-NEXT: shl.b32 %r4, %r6, %r1; +; SM90-NEXT: ld.global.b32 %r16, [%rd1]; +; SM90-NEXT: $L__BB95_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r10, %r16, %r4; +; SM90-NEXT: not.b32 %r11, %r10; +; SM90-NEXT: and.b32 %r12, %r11, %r2; +; SM90-NEXT: and.b32 %r13, %r16, %r3; +; SM90-NEXT: or.b32 %r14, %r13, %r12; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r5, [%rd1], %r16, %r14; +; SM90-NEXT: setp.ne.b32 %p1, %r5, %r16; +; SM90-NEXT: mov.b32 %r16, %r5; +; SM90-NEXT: @%p1 bra $L__BB95_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: shr.u32 %r15, %r5, %r1; +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r15; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") seq_cst + ret i8 %retval +} + +define i32 @nand_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: nand_monotonic_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<6>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [nand_monotonic_i32_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [nand_monotonic_i32_global_cta_param_0]; +; SM90-NEXT: ld.global.b32 %r5, [%rd1]; +; SM90-NEXT: $L__BB96_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r3, %r5, %r2; +; SM90-NEXT: not.b32 %r4, %r3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM90-NEXT: mov.b32 %r5, %r1; +; SM90-NEXT: @%p1 bra $L__BB96_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") monotonic + ret i32 %retval +} + +define i32 @nand_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: nand_acquire_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<6>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [nand_acquire_i32_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [nand_acquire_i32_global_cta_param_0]; +; SM90-NEXT: ld.global.b32 %r5, [%rd1]; +; SM90-NEXT: $L__BB97_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r3, %r5, %r2; +; SM90-NEXT: not.b32 %r4, %r3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM90-NEXT: mov.b32 %r5, %r1; +; SM90-NEXT: @%p1 bra $L__BB97_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") acquire + ret i32 %retval +} + +define i32 @nand_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: nand_release_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<6>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [nand_release_i32_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [nand_release_i32_global_cta_param_0]; +; SM90-NEXT: fence.release.cta; +; SM90-NEXT: ld.global.b32 %r5, [%rd1]; +; SM90-NEXT: $L__BB98_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r3, %r5, %r2; +; SM90-NEXT: not.b32 %r4, %r3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM90-NEXT: mov.b32 %r5, %r1; +; SM90-NEXT: @%p1 bra $L__BB98_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") release + ret i32 %retval +} + +define i32 @nand_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) { +; SM90-LABEL: nand_seq_cst_i32_global_cta( +; SM90: { +; SM90-NEXT: .reg .pred %p<2>; +; SM90-NEXT: .reg .b32 %r<6>; +; SM90-NEXT: .reg .b64 %rd<2>; +; SM90-EMPTY: +; SM90-NEXT: // %bb.0: +; SM90-NEXT: ld.param.b32 %r2, [nand_seq_cst_i32_global_cta_param_1]; +; SM90-NEXT: ld.param.b64 %rd1, [nand_seq_cst_i32_global_cta_param_0]; +; SM90-NEXT: fence.sc.cta; +; SM90-NEXT: ld.global.b32 %r5, [%rd1]; +; SM90-NEXT: $L__BB99_1: // %atomicrmw.start +; SM90-NEXT: // =>This Inner Loop Header: Depth=1 +; SM90-NEXT: and.b32 %r3, %r5, %r2; +; SM90-NEXT: not.b32 %r4, %r3; +; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r1, [%rd1], %r5, %r4; +; SM90-NEXT: setp.ne.b32 %p1, %r1, %r5; +; SM90-NEXT: mov.b32 %r5, %r1; +; SM90-NEXT: @%p1 bra $L__BB99_1; +; SM90-NEXT: // %bb.2: // %atomicrmw.end +; SM90-NEXT: fence.acquire.cta; +; SM90-NEXT: st.param.b32 [func_retval0], %r1; +; SM90-NEXT: ret; + %retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") seq_cst + ret i32 %retval +} + diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw.py b/llvm/test/CodeGen/NVPTX/atomicrmw.py new file mode 100644 index 0000000000000..238fe45bf45a0 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/atomicrmw.py @@ -0,0 +1,116 @@ +# For manual usage, not as a part of lit tests. Used for generating the following tests: + +from string import Template +from itertools import product + +TEST_SM_ARCH_PAIRS = [(60, 50), (70, 63), (90, 87)] + +SCOPE_LLVM_TO_PTX = {"": "sys", "block": "cta", "cluster": "cluster", "device": "gpu"} + +ORDERINGS = ["monotonic", "acquire", "release", "acq_rel", "seq_cst"] + +INTEGER_OPERATIONS = [ + "xchg", + "add", + "sub", + "and", + "nand", + "or", + "xor", + "max", + "min", + "umax", + "umin", + "uinc_wrap", + "udec_wrap", + "usub_cond", + "usub_sat", +] + +FLOATING_POINT_OPERATIONS = ["fadd", "fsub", "fmin", "fmax", "fminimum", "fmaximum"] + +ADDRSPACE_NUM_TO_ADDRSPACE = {0: "generic", 1: "global", 3: "shared"} + +atomicrmw_func = Template( + """define ${datatype} @${operation}_${ordering}_${datatype}_${addrspace}_${ptx_scope}(ptr${addrspace_cast} %addr, ${datatype} %val) { + %retval = atomicrmw ${operation} ptr ${addrspace_cast} %addr, ${datatype} %val syncscope(\"${llvm_scope}\") ${ordering} + ret $datatype %retval +} +""" +) + +run_statement = Template( + """; RUN: llc < %s -march=nvptx64 -mcpu=sm_${sm} -mattr=+ptx${ptx} | FileCheck %s --check-prefix=SM${sm} +; RUN: %if ptxas-sm_${sm} && ptxas-isa-${ptxfp} %{ llc < %s -march=nvptx64 -mcpu=sm_${sm} -mattr=+ptx${ptx} | %ptxas-verify -arch=sm_${sm} %} +""" +) + + +def get_addrspace_cast(addrspace): + if addrspace == 0: + return "" + else: + return " addrspace({})".format(str(addrspace)) + + +if __name__ == "__main__": + for sm, ptx in TEST_SM_ARCH_PAIRS: + # Slice 1: Keep addrspace, llvm_scope, ordering fixed, generate all possible operations and sizes + with open("atomicrmw-sm{}.ll".format(str(sm)), "w") as fp: + print(run_statement.substitute(sm=sm, ptx=ptx, ptxfp=ptx / 10.0), file=fp) + # Integer operations + addrspace, llvm_scope, ordering = 1, "block", "acq_rel" + for operation, datatype in product( + INTEGER_OPERATIONS, ["i8", "i16", "i32", "i64"] + ): + print( + atomicrmw_func.substitute( + operation=operation, + ordering=ordering, + datatype=datatype, + addrspace=ADDRSPACE_NUM_TO_ADDRSPACE[addrspace], + ptx_scope=SCOPE_LLVM_TO_PTX[llvm_scope], + llvm_scope=llvm_scope, + addrspace_cast=get_addrspace_cast(addrspace), + ), + file=fp, + ) + + # Floating point add + for datatype, operation in product( + ["float", "double", "half", "bfloat"], FLOATING_POINT_OPERATIONS + ): + print( + atomicrmw_func.substitute( + operation=operation, + ordering=ordering, + datatype=datatype, + addrspace=ADDRSPACE_NUM_TO_ADDRSPACE[addrspace], + ptx_scope=SCOPE_LLVM_TO_PTX[llvm_scope], + llvm_scope=llvm_scope, + addrspace_cast=get_addrspace_cast(addrspace), + ), + file=fp, + ) + + # Slice 2: Keep addrspace, llvm_scope fixed, and generate all possible orderings for operations add and nand. + # add is natively supported for larger bitwidths, while nand is emulated always + addrspace, llvm_scope = 1, "block" + for operation, datatype, ordering in product( + ["add", "nand"], ["i8", "i32"], ORDERINGS + ): + if addrspace == 1 and llvm_scope == "block" and ordering == "acq_rel": + # These are a part of Slice 1 + continue + print( + atomicrmw_func.substitute( + operation=operation, + ordering=ordering, + datatype=datatype, + addrspace=ADDRSPACE_NUM_TO_ADDRSPACE[addrspace], + addrspace_cast=get_addrspace_cast(addrspace), + ptx_scope=SCOPE_LLVM_TO_PTX[llvm_scope], + llvm_scope=llvm_scope, + ), + file=fp, + ) diff --git a/llvm/test/CodeGen/NVPTX/atomics-sm60.ll b/llvm/test/CodeGen/NVPTX/atomics-sm60.ll index ae10526ec8365..10e1ca434f271 100644 --- a/llvm/test/CodeGen/NVPTX/atomics-sm60.ll +++ b/llvm/test/CodeGen/NVPTX/atomics-sm60.ll @@ -5,26 +5,15 @@ ; CHECK-LABEL: .func test( define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, double %d) { -; CHECK: atom.add.f64 +; CHECK: atom.sys.add.f64 %r1 = call double @llvm.nvvm.atomic.load.add.f64.p0(ptr %dp0, double %d) -; CHECK: atom.global.add.f64 +; CHECK: atom.sys.global.add.f64 %r2 = call double @llvm.nvvm.atomic.load.add.f64.p1(ptr addrspace(1) %dp1, double %d) -; CHECK: atom.shared.add.f64 +; CHECK: atom.sys.shared.add.f64 %ret = call double @llvm.nvvm.atomic.load.add.f64.p3(ptr addrspace(3) %dp3, double %d) ret void } -; CHECK-LABEL: .func test2( -define void @test2(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, double %d) { -; CHECK: atom.add.f64 - %r1 = atomicrmw fadd ptr %dp0, double %d seq_cst -; CHECK: atom.global.add.f64 - %r2 = atomicrmw fadd ptr addrspace(1) %dp1, double %d seq_cst -; CHECK: atom.shared.add.f64 - %ret = atomicrmw fadd ptr addrspace(3) %dp3, double %d seq_cst - ret void -} - declare double @llvm.nvvm.atomic.load.add.f64.p0(ptr nocapture, double) #1 declare double @llvm.nvvm.atomic.load.add.f64.p1(ptr addrspace(1) nocapture, double) #1 declare double @llvm.nvvm.atomic.load.add.f64.p3(ptr addrspace(3) nocapture, double) #1 diff --git a/llvm/test/CodeGen/NVPTX/atomics-sm70.ll b/llvm/test/CodeGen/NVPTX/atomics-sm70.ll deleted file mode 100644 index e2762bac45a35..0000000000000 --- a/llvm/test/CodeGen/NVPTX/atomics-sm70.ll +++ /dev/null @@ -1,144 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc < %s -mtriple=nvptx -mcpu=sm_70 -mattr=+ptx63 | FileCheck %s --check-prefixes=CHECK -; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_70 -mattr=+ptx63 | FileCheck %s --check-prefixes=CHECK64 -; RUN: llc < %s -mtriple=nvptx -mcpu=sm_70 -mattr=+ptx62 | FileCheck %s --check-prefixes=CHECKPTX62 -; RUN: %if ptxas-sm_70 && ptxas-isa-6.3 && ptxas-ptr32 %{ llc < %s -mtriple=nvptx -mcpu=sm_70 -mattr=+ptx63 | %ptxas-verify -arch=sm_70 %} -; RUN: %if ptxas-sm_70 && ptxas-isa-6.3 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_70 -mattr=+ptx63 | %ptxas-verify -arch=sm_70 %} -; RUN: %if ptxas-sm_70 && ptxas-isa-6.2 && ptxas-ptr32 %{ llc < %s -mtriple=nvptx -mcpu=sm_70 -mattr=+ptx62 | %ptxas-verify -arch=sm_70 %} - -target triple = "nvptx64-nvidia-cuda" - -define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, half %val) { -; CHECK-LABEL: test( -; CHECK: { -; CHECK-NEXT: .reg .b16 %rs<7>; -; CHECK-NEXT: .reg .b32 %r<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b32 %r1, [test_param_0]; -; CHECK-NEXT: ld.param.b16 %rs1, [test_param_3]; -; CHECK-NEXT: atom.add.noftz.f16 %rs2, [%r1], %rs1; -; CHECK-NEXT: ld.param.b32 %r2, [test_param_1]; -; CHECK-NEXT: mov.b16 %rs3, 0x3C00; -; CHECK-NEXT: atom.add.noftz.f16 %rs4, [%r1], %rs3; -; CHECK-NEXT: ld.param.b32 %r3, [test_param_2]; -; CHECK-NEXT: atom.global.add.noftz.f16 %rs5, [%r2], %rs1; -; CHECK-NEXT: atom.shared.add.noftz.f16 %rs6, [%r3], %rs1; -; CHECK-NEXT: ret; -; -; CHECK64-LABEL: test( -; CHECK64: { -; CHECK64-NEXT: .reg .b16 %rs<7>; -; CHECK64-NEXT: .reg .b64 %rd<4>; -; CHECK64-EMPTY: -; CHECK64-NEXT: // %bb.0: -; CHECK64-NEXT: ld.param.b64 %rd1, [test_param_0]; -; CHECK64-NEXT: ld.param.b16 %rs1, [test_param_3]; -; CHECK64-NEXT: atom.add.noftz.f16 %rs2, [%rd1], %rs1; -; CHECK64-NEXT: ld.param.b64 %rd2, [test_param_1]; -; CHECK64-NEXT: mov.b16 %rs3, 0x3C00; -; CHECK64-NEXT: atom.add.noftz.f16 %rs4, [%rd1], %rs3; -; CHECK64-NEXT: ld.param.b64 %rd3, [test_param_2]; -; CHECK64-NEXT: atom.global.add.noftz.f16 %rs5, [%rd2], %rs1; -; CHECK64-NEXT: atom.shared.add.noftz.f16 %rs6, [%rd3], %rs1; -; CHECK64-NEXT: ret; -; -; CHECKPTX62-LABEL: test( -; CHECKPTX62: { -; CHECKPTX62-NEXT: .reg .pred %p<5>; -; CHECKPTX62-NEXT: .reg .b16 %rs<11>; -; CHECKPTX62-NEXT: .reg .b32 %r<50>; -; CHECKPTX62-EMPTY: -; CHECKPTX62-NEXT: // %bb.0: -; CHECKPTX62-NEXT: ld.param.b16 %rs1, [test_param_3]; -; CHECKPTX62-NEXT: ld.param.b32 %r15, [test_param_2]; -; CHECKPTX62-NEXT: ld.param.b32 %r14, [test_param_1]; -; CHECKPTX62-NEXT: ld.param.b32 %r16, [test_param_0]; -; CHECKPTX62-NEXT: and.b32 %r1, %r16, -4; -; CHECKPTX62-NEXT: and.b32 %r17, %r16, 3; -; CHECKPTX62-NEXT: shl.b32 %r2, %r17, 3; -; CHECKPTX62-NEXT: mov.b32 %r18, 65535; -; CHECKPTX62-NEXT: shl.b32 %r19, %r18, %r2; -; CHECKPTX62-NEXT: not.b32 %r3, %r19; -; CHECKPTX62-NEXT: ld.b32 %r46, [%r1]; -; CHECKPTX62-NEXT: $L__BB0_1: // %atomicrmw.start45 -; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX62-NEXT: shr.u32 %r20, %r46, %r2; -; CHECKPTX62-NEXT: cvt.u16.u32 %rs2, %r20; -; CHECKPTX62-NEXT: add.rn.f16 %rs3, %rs2, %rs1; -; CHECKPTX62-NEXT: cvt.u32.u16 %r21, %rs3; -; CHECKPTX62-NEXT: shl.b32 %r22, %r21, %r2; -; CHECKPTX62-NEXT: and.b32 %r23, %r46, %r3; -; CHECKPTX62-NEXT: or.b32 %r24, %r23, %r22; -; CHECKPTX62-NEXT: atom.relaxed.sys.cas.b32 %r4, [%r1], %r46, %r24; -; CHECKPTX62-NEXT: setp.ne.b32 %p1, %r4, %r46; -; CHECKPTX62-NEXT: mov.b32 %r46, %r4; -; CHECKPTX62-NEXT: @%p1 bra $L__BB0_1; -; CHECKPTX62-NEXT: // %bb.2: // %atomicrmw.end44 -; CHECKPTX62-NEXT: ld.b32 %r47, [%r1]; -; CHECKPTX62-NEXT: $L__BB0_3: // %atomicrmw.start27 -; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX62-NEXT: shr.u32 %r25, %r47, %r2; -; CHECKPTX62-NEXT: cvt.u16.u32 %rs4, %r25; -; CHECKPTX62-NEXT: mov.b16 %rs5, 0x3C00; -; CHECKPTX62-NEXT: add.rn.f16 %rs6, %rs4, %rs5; -; CHECKPTX62-NEXT: cvt.u32.u16 %r26, %rs6; -; CHECKPTX62-NEXT: shl.b32 %r27, %r26, %r2; -; CHECKPTX62-NEXT: and.b32 %r28, %r47, %r3; -; CHECKPTX62-NEXT: or.b32 %r29, %r28, %r27; -; CHECKPTX62-NEXT: atom.relaxed.sys.cas.b32 %r5, [%r1], %r47, %r29; -; CHECKPTX62-NEXT: setp.ne.b32 %p2, %r5, %r47; -; CHECKPTX62-NEXT: mov.b32 %r47, %r5; -; CHECKPTX62-NEXT: @%p2 bra $L__BB0_3; -; CHECKPTX62-NEXT: // %bb.4: // %atomicrmw.end26 -; CHECKPTX62-NEXT: and.b32 %r6, %r14, -4; -; CHECKPTX62-NEXT: shl.b32 %r30, %r14, 3; -; CHECKPTX62-NEXT: and.b32 %r7, %r30, 24; -; CHECKPTX62-NEXT: mov.b32 %r31, 65535; -; CHECKPTX62-NEXT: shl.b32 %r32, %r31, %r7; -; CHECKPTX62-NEXT: not.b32 %r8, %r32; -; CHECKPTX62-NEXT: ld.global.b32 %r48, [%r6]; -; CHECKPTX62-NEXT: $L__BB0_5: // %atomicrmw.start9 -; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX62-NEXT: shr.u32 %r33, %r48, %r7; -; CHECKPTX62-NEXT: cvt.u16.u32 %rs7, %r33; -; CHECKPTX62-NEXT: add.rn.f16 %rs8, %rs7, %rs1; -; CHECKPTX62-NEXT: cvt.u32.u16 %r34, %rs8; -; CHECKPTX62-NEXT: shl.b32 %r35, %r34, %r7; -; CHECKPTX62-NEXT: and.b32 %r36, %r48, %r8; -; CHECKPTX62-NEXT: or.b32 %r37, %r36, %r35; -; CHECKPTX62-NEXT: atom.relaxed.sys.global.cas.b32 %r9, [%r6], %r48, %r37; -; CHECKPTX62-NEXT: setp.ne.b32 %p3, %r9, %r48; -; CHECKPTX62-NEXT: mov.b32 %r48, %r9; -; CHECKPTX62-NEXT: @%p3 bra $L__BB0_5; -; CHECKPTX62-NEXT: // %bb.6: // %atomicrmw.end8 -; CHECKPTX62-NEXT: and.b32 %r10, %r15, -4; -; CHECKPTX62-NEXT: shl.b32 %r38, %r15, 3; -; CHECKPTX62-NEXT: and.b32 %r11, %r38, 24; -; CHECKPTX62-NEXT: mov.b32 %r39, 65535; -; CHECKPTX62-NEXT: shl.b32 %r40, %r39, %r11; -; CHECKPTX62-NEXT: not.b32 %r12, %r40; -; CHECKPTX62-NEXT: ld.shared.b32 %r49, [%r10]; -; CHECKPTX62-NEXT: $L__BB0_7: // %atomicrmw.start -; CHECKPTX62-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX62-NEXT: shr.u32 %r41, %r49, %r11; -; CHECKPTX62-NEXT: cvt.u16.u32 %rs9, %r41; -; CHECKPTX62-NEXT: add.rn.f16 %rs10, %rs9, %rs1; -; CHECKPTX62-NEXT: cvt.u32.u16 %r42, %rs10; -; CHECKPTX62-NEXT: shl.b32 %r43, %r42, %r11; -; CHECKPTX62-NEXT: and.b32 %r44, %r49, %r12; -; CHECKPTX62-NEXT: or.b32 %r45, %r44, %r43; -; CHECKPTX62-NEXT: atom.relaxed.sys.shared.cas.b32 %r13, [%r10], %r49, %r45; -; CHECKPTX62-NEXT: setp.ne.b32 %p4, %r13, %r49; -; CHECKPTX62-NEXT: mov.b32 %r49, %r13; -; CHECKPTX62-NEXT: @%p4 bra $L__BB0_7; -; CHECKPTX62-NEXT: // %bb.8: // %atomicrmw.end -; CHECKPTX62-NEXT: ret; - %r1 = atomicrmw fadd ptr %dp0, half %val monotonic - %r2 = atomicrmw fadd ptr %dp0, half 1.0 monotonic - %r3 = atomicrmw fadd ptr addrspace(1) %dp1, half %val monotonic - %r4 = atomicrmw fadd ptr addrspace(3) %dp3, half %val monotonic - ret void -} - -attributes #1 = { argmemonly nounwind } diff --git a/llvm/test/CodeGen/NVPTX/atomics-sm90.ll b/llvm/test/CodeGen/NVPTX/atomics-sm90.ll deleted file mode 100644 index e6c6a73eef14d..0000000000000 --- a/llvm/test/CodeGen/NVPTX/atomics-sm90.ll +++ /dev/null @@ -1,147 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc < %s -mtriple=nvptx -mcpu=sm_90 -mattr=+ptx78 | FileCheck %s --check-prefixes=CHECK -; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx78 | FileCheck %s --check-prefixes=CHECK64 -; RUN: llc < %s -mtriple=nvptx -mcpu=sm_86 -mattr=+ptx71 | FileCheck %s --check-prefixes=CHECKPTX71 -; RUN: %if ptxas-sm_90 && ptxas-isa-7.8 && ptxas-ptr32 %{ llc < %s -mtriple=nvptx -mcpu=sm_90 -mattr=+ptx78 | %ptxas-verify -arch=sm_90 %} -; RUN: %if ptxas-sm_90 && ptxas-isa-7.8 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx78 | %ptxas-verify -arch=sm_90 %} -; RUN: %if ptxas-sm_86 && ptxas-isa-7.1 && ptxas-ptr32 %{ llc < %s -mtriple=nvptx -mcpu=sm_86 -mattr=+ptx71 | %ptxas-verify -arch=sm_86 %} - -target triple = "nvptx64-nvidia-cuda" - -define void @test(ptr %dp0, ptr addrspace(1) %dp1, ptr addrspace(3) %dp3, bfloat %val) { -; CHECK-LABEL: test( -; CHECK: { -; CHECK-NEXT: .reg .b16 %rs<7>; -; CHECK-NEXT: .reg .b32 %r<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b32 %r1, [test_param_0]; -; CHECK-NEXT: ld.param.b16 %rs1, [test_param_3]; -; CHECK-NEXT: atom.add.noftz.bf16 %rs2, [%r1], %rs1; -; CHECK-NEXT: ld.param.b32 %r2, [test_param_1]; -; CHECK-NEXT: mov.b16 %rs3, 0x3F80; -; CHECK-NEXT: atom.add.noftz.bf16 %rs4, [%r1], %rs3; -; CHECK-NEXT: ld.param.b32 %r3, [test_param_2]; -; CHECK-NEXT: atom.global.add.noftz.bf16 %rs5, [%r2], %rs1; -; CHECK-NEXT: atom.shared.add.noftz.bf16 %rs6, [%r3], %rs1; -; CHECK-NEXT: ret; -; -; CHECK64-LABEL: test( -; CHECK64: { -; CHECK64-NEXT: .reg .b16 %rs<7>; -; CHECK64-NEXT: .reg .b64 %rd<4>; -; CHECK64-EMPTY: -; CHECK64-NEXT: // %bb.0: -; CHECK64-NEXT: ld.param.b64 %rd1, [test_param_0]; -; CHECK64-NEXT: ld.param.b16 %rs1, [test_param_3]; -; CHECK64-NEXT: atom.add.noftz.bf16 %rs2, [%rd1], %rs1; -; CHECK64-NEXT: ld.param.b64 %rd2, [test_param_1]; -; CHECK64-NEXT: mov.b16 %rs3, 0x3F80; -; CHECK64-NEXT: atom.add.noftz.bf16 %rs4, [%rd1], %rs3; -; CHECK64-NEXT: ld.param.b64 %rd3, [test_param_2]; -; CHECK64-NEXT: atom.global.add.noftz.bf16 %rs5, [%rd2], %rs1; -; CHECK64-NEXT: atom.shared.add.noftz.bf16 %rs6, [%rd3], %rs1; -; CHECK64-NEXT: ret; -; -; CHECKPTX71-LABEL: test( -; CHECKPTX71: { -; CHECKPTX71-NEXT: .reg .pred %p<5>; -; CHECKPTX71-NEXT: .reg .b16 %rs<14>; -; CHECKPTX71-NEXT: .reg .b32 %r<50>; -; CHECKPTX71-EMPTY: -; CHECKPTX71-NEXT: // %bb.0: -; CHECKPTX71-NEXT: ld.param.b16 %rs1, [test_param_3]; -; CHECKPTX71-NEXT: ld.param.b32 %r15, [test_param_2]; -; CHECKPTX71-NEXT: ld.param.b32 %r14, [test_param_1]; -; CHECKPTX71-NEXT: ld.param.b32 %r16, [test_param_0]; -; CHECKPTX71-NEXT: and.b32 %r1, %r16, -4; -; CHECKPTX71-NEXT: and.b32 %r17, %r16, 3; -; CHECKPTX71-NEXT: shl.b32 %r2, %r17, 3; -; CHECKPTX71-NEXT: mov.b32 %r18, 65535; -; CHECKPTX71-NEXT: shl.b32 %r19, %r18, %r2; -; CHECKPTX71-NEXT: not.b32 %r3, %r19; -; CHECKPTX71-NEXT: ld.b32 %r46, [%r1]; -; CHECKPTX71-NEXT: $L__BB0_1: // %atomicrmw.start45 -; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX71-NEXT: shr.u32 %r20, %r46, %r2; -; CHECKPTX71-NEXT: cvt.u16.u32 %rs2, %r20; -; CHECKPTX71-NEXT: mov.b16 %rs3, 0x3F80; -; CHECKPTX71-NEXT: fma.rn.bf16 %rs4, %rs2, %rs3, %rs1; -; CHECKPTX71-NEXT: cvt.u32.u16 %r21, %rs4; -; CHECKPTX71-NEXT: shl.b32 %r22, %r21, %r2; -; CHECKPTX71-NEXT: and.b32 %r23, %r46, %r3; -; CHECKPTX71-NEXT: or.b32 %r24, %r23, %r22; -; CHECKPTX71-NEXT: atom.relaxed.sys.cas.b32 %r4, [%r1], %r46, %r24; -; CHECKPTX71-NEXT: setp.ne.b32 %p1, %r4, %r46; -; CHECKPTX71-NEXT: mov.b32 %r46, %r4; -; CHECKPTX71-NEXT: @%p1 bra $L__BB0_1; -; CHECKPTX71-NEXT: // %bb.2: // %atomicrmw.end44 -; CHECKPTX71-NEXT: ld.b32 %r47, [%r1]; -; CHECKPTX71-NEXT: $L__BB0_3: // %atomicrmw.start27 -; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX71-NEXT: shr.u32 %r25, %r47, %r2; -; CHECKPTX71-NEXT: cvt.u16.u32 %rs5, %r25; -; CHECKPTX71-NEXT: mov.b16 %rs6, 0x3F80; -; CHECKPTX71-NEXT: fma.rn.bf16 %rs7, %rs5, %rs6, %rs6; -; CHECKPTX71-NEXT: cvt.u32.u16 %r26, %rs7; -; CHECKPTX71-NEXT: shl.b32 %r27, %r26, %r2; -; CHECKPTX71-NEXT: and.b32 %r28, %r47, %r3; -; CHECKPTX71-NEXT: or.b32 %r29, %r28, %r27; -; CHECKPTX71-NEXT: atom.relaxed.sys.cas.b32 %r5, [%r1], %r47, %r29; -; CHECKPTX71-NEXT: setp.ne.b32 %p2, %r5, %r47; -; CHECKPTX71-NEXT: mov.b32 %r47, %r5; -; CHECKPTX71-NEXT: @%p2 bra $L__BB0_3; -; CHECKPTX71-NEXT: // %bb.4: // %atomicrmw.end26 -; CHECKPTX71-NEXT: and.b32 %r6, %r14, -4; -; CHECKPTX71-NEXT: shl.b32 %r30, %r14, 3; -; CHECKPTX71-NEXT: and.b32 %r7, %r30, 24; -; CHECKPTX71-NEXT: mov.b32 %r31, 65535; -; CHECKPTX71-NEXT: shl.b32 %r32, %r31, %r7; -; CHECKPTX71-NEXT: not.b32 %r8, %r32; -; CHECKPTX71-NEXT: ld.global.b32 %r48, [%r6]; -; CHECKPTX71-NEXT: $L__BB0_5: // %atomicrmw.start9 -; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX71-NEXT: shr.u32 %r33, %r48, %r7; -; CHECKPTX71-NEXT: cvt.u16.u32 %rs8, %r33; -; CHECKPTX71-NEXT: mov.b16 %rs9, 0x3F80; -; CHECKPTX71-NEXT: fma.rn.bf16 %rs10, %rs8, %rs9, %rs1; -; CHECKPTX71-NEXT: cvt.u32.u16 %r34, %rs10; -; CHECKPTX71-NEXT: shl.b32 %r35, %r34, %r7; -; CHECKPTX71-NEXT: and.b32 %r36, %r48, %r8; -; CHECKPTX71-NEXT: or.b32 %r37, %r36, %r35; -; CHECKPTX71-NEXT: atom.relaxed.sys.global.cas.b32 %r9, [%r6], %r48, %r37; -; CHECKPTX71-NEXT: setp.ne.b32 %p3, %r9, %r48; -; CHECKPTX71-NEXT: mov.b32 %r48, %r9; -; CHECKPTX71-NEXT: @%p3 bra $L__BB0_5; -; CHECKPTX71-NEXT: // %bb.6: // %atomicrmw.end8 -; CHECKPTX71-NEXT: and.b32 %r10, %r15, -4; -; CHECKPTX71-NEXT: shl.b32 %r38, %r15, 3; -; CHECKPTX71-NEXT: and.b32 %r11, %r38, 24; -; CHECKPTX71-NEXT: mov.b32 %r39, 65535; -; CHECKPTX71-NEXT: shl.b32 %r40, %r39, %r11; -; CHECKPTX71-NEXT: not.b32 %r12, %r40; -; CHECKPTX71-NEXT: ld.shared.b32 %r49, [%r10]; -; CHECKPTX71-NEXT: $L__BB0_7: // %atomicrmw.start -; CHECKPTX71-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECKPTX71-NEXT: shr.u32 %r41, %r49, %r11; -; CHECKPTX71-NEXT: cvt.u16.u32 %rs11, %r41; -; CHECKPTX71-NEXT: mov.b16 %rs12, 0x3F80; -; CHECKPTX71-NEXT: fma.rn.bf16 %rs13, %rs11, %rs12, %rs1; -; CHECKPTX71-NEXT: cvt.u32.u16 %r42, %rs13; -; CHECKPTX71-NEXT: shl.b32 %r43, %r42, %r11; -; CHECKPTX71-NEXT: and.b32 %r44, %r49, %r12; -; CHECKPTX71-NEXT: or.b32 %r45, %r44, %r43; -; CHECKPTX71-NEXT: atom.relaxed.sys.shared.cas.b32 %r13, [%r10], %r49, %r45; -; CHECKPTX71-NEXT: setp.ne.b32 %p4, %r13, %r49; -; CHECKPTX71-NEXT: mov.b32 %r49, %r13; -; CHECKPTX71-NEXT: @%p4 bra $L__BB0_7; -; CHECKPTX71-NEXT: // %bb.8: // %atomicrmw.end -; CHECKPTX71-NEXT: ret; - %r1 = atomicrmw fadd ptr %dp0, bfloat %val monotonic - %r2 = atomicrmw fadd ptr %dp0, bfloat 1.0 monotonic - %r3 = atomicrmw fadd ptr addrspace(1) %dp1, bfloat %val monotonic - %r4 = atomicrmw fadd ptr addrspace(3) %dp3, bfloat %val monotonic - ret void -} - -attributes #1 = { argmemonly nounwind } diff --git a/llvm/test/CodeGen/NVPTX/atomics.ll b/llvm/test/CodeGen/NVPTX/atomics.ll index 6ea02f35e9626..48d38f565c3ef 100644 --- a/llvm/test/CodeGen/NVPTX/atomics.ll +++ b/llvm/test/CodeGen/NVPTX/atomics.ll @@ -2,349 +2,6 @@ ; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_32 | FileCheck %s ; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_32 | %ptxas-verify %} - -; CHECK-LABEL: atom0 -define i32 @atom0(ptr %addr, i32 %val) { -; CHECK-LABEL: atom0( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom0_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom0_param_1]; -; CHECK-NEXT: atom.add.u32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw add ptr %addr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom1 -define i64 @atom1(ptr %addr, i64 %val) { -; CHECK-LABEL: atom1( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom1_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom1_param_1]; -; CHECK-NEXT: atom.add.u64 %rd3, [%rd1], %rd2; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %ret = atomicrmw add ptr %addr, i64 %val seq_cst - ret i64 %ret -} - -; CHECK-LABEL: atom2 -define i32 @atom2(ptr %subr, i32 %val) { -; CHECK-LABEL: atom2( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<4>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom2_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom2_param_1]; -; CHECK-NEXT: neg.s32 %r2, %r1; -; CHECK-NEXT: atom.add.u32 %r3, [%rd1], %r2; -; CHECK-NEXT: st.param.b32 [func_retval0], %r3; -; CHECK-NEXT: ret; - %ret = atomicrmw sub ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom3 -define i64 @atom3(ptr %subr, i64 %val) { -; CHECK-LABEL: atom3( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<5>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom3_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom3_param_1]; -; CHECK-NEXT: neg.s64 %rd3, %rd2; -; CHECK-NEXT: atom.add.u64 %rd4, [%rd1], %rd3; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd4; -; CHECK-NEXT: ret; - %ret = atomicrmw sub ptr %subr, i64 %val seq_cst - ret i64 %ret -} - -; CHECK-LABEL: atom4 -define i32 @atom4(ptr %subr, i32 %val) { -; CHECK-LABEL: atom4( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom4_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom4_param_1]; -; CHECK-NEXT: atom.and.b32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw and ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom5 -define i64 @atom5(ptr %subr, i64 %val) { -; CHECK-LABEL: atom5( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom5_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom5_param_1]; -; CHECK-NEXT: atom.and.b64 %rd3, [%rd1], %rd2; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %ret = atomicrmw and ptr %subr, i64 %val seq_cst - ret i64 %ret -} - -;; NAND not yet supported -;define i32 @atom6(ptr %subr, i32 %val) { -; %ret = atomicrmw nand ptr %subr, i32 %val seq_cst -; ret i32 %ret -;} - -;define i64 @atom7(ptr %subr, i64 %val) { -; %ret = atomicrmw nand ptr %subr, i64 %val seq_cst -; ret i64 %ret -;} - -; CHECK-LABEL: atom8 -define i32 @atom8(ptr %subr, i32 %val) { -; CHECK-LABEL: atom8( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom8_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom8_param_1]; -; CHECK-NEXT: atom.or.b32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw or ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom9 -define i64 @atom9(ptr %subr, i64 %val) { -; CHECK-LABEL: atom9( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom9_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom9_param_1]; -; CHECK-NEXT: atom.or.b64 %rd3, [%rd1], %rd2; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %ret = atomicrmw or ptr %subr, i64 %val seq_cst - ret i64 %ret -} - -; CHECK-LABEL: atom10 -define i32 @atom10(ptr %subr, i32 %val) { -; CHECK-LABEL: atom10( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom10_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom10_param_1]; -; CHECK-NEXT: atom.xor.b32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw xor ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom11 -define i64 @atom11(ptr %subr, i64 %val) { -; CHECK-LABEL: atom11( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom11_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom11_param_1]; -; CHECK-NEXT: atom.xor.b64 %rd3, [%rd1], %rd2; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %ret = atomicrmw xor ptr %subr, i64 %val seq_cst - ret i64 %ret -} - -; CHECK-LABEL: atom12 -define i32 @atom12(ptr %subr, i32 %val) { -; CHECK-LABEL: atom12( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom12_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom12_param_1]; -; CHECK-NEXT: atom.max.s32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw max ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom13 -define i64 @atom13(ptr %subr, i64 %val) { -; CHECK-LABEL: atom13( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom13_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom13_param_1]; -; CHECK-NEXT: atom.max.s64 %rd3, [%rd1], %rd2; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %ret = atomicrmw max ptr %subr, i64 %val seq_cst - ret i64 %ret -} - -; CHECK-LABEL: atom14 -define i32 @atom14(ptr %subr, i32 %val) { -; CHECK-LABEL: atom14( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom14_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom14_param_1]; -; CHECK-NEXT: atom.min.s32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw min ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom15 -define i64 @atom15(ptr %subr, i64 %val) { -; CHECK-LABEL: atom15( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom15_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom15_param_1]; -; CHECK-NEXT: atom.min.s64 %rd3, [%rd1], %rd2; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %ret = atomicrmw min ptr %subr, i64 %val seq_cst - ret i64 %ret -} - -; CHECK-LABEL: atom16 -define i32 @atom16(ptr %subr, i32 %val) { -; CHECK-LABEL: atom16( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom16_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom16_param_1]; -; CHECK-NEXT: atom.max.u32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw umax ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom17 -define i64 @atom17(ptr %subr, i64 %val) { -; CHECK-LABEL: atom17( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom17_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom17_param_1]; -; CHECK-NEXT: atom.max.u64 %rd3, [%rd1], %rd2; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %ret = atomicrmw umax ptr %subr, i64 %val seq_cst - ret i64 %ret -} - -; CHECK-LABEL: atom18 -define i32 @atom18(ptr %subr, i32 %val) { -; CHECK-LABEL: atom18( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom18_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom18_param_1]; -; CHECK-NEXT: atom.min.u32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw umin ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -; CHECK-LABEL: atom19 -define i64 @atom19(ptr %subr, i64 %val) { -; CHECK-LABEL: atom19( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<4>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom19_param_0]; -; CHECK-NEXT: ld.param.b64 %rd2, [atom19_param_1]; -; CHECK-NEXT: atom.min.u64 %rd3, [%rd1], %rd2; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %ret = atomicrmw umin ptr %subr, i64 %val seq_cst - ret i64 %ret -} - -define i32 @atom20(ptr %subr, i32 %val) { -; CHECK-LABEL: atom20( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom20_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom20_param_1]; -; CHECK-NEXT: atom.inc.u32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw uinc_wrap ptr %subr, i32 %val seq_cst - ret i32 %ret -} - -define i32 @atom21(ptr %subr, i32 %val) { -; CHECK-LABEL: atom21( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atom21_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atom21_param_1]; -; CHECK-NEXT: atom.dec.u32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw udec_wrap ptr %subr, i32 %val seq_cst - ret i32 %ret -} - declare float @llvm.nvvm.atomic.load.add.f32.p0(ptr %addr, float %val) ; CHECK-LABEL: atomic_add_f32_generic @@ -356,6 +13,7 @@ define float @atomic_add_f32_generic(ptr %addr, float %val) { ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ld.param.b64 %rd1, [atomic_add_f32_generic_param_0]; +; CHECK-NEXT: membar.sys; ; CHECK-NEXT: ld.param.b32 %r1, [atomic_add_f32_generic_param_1]; ; CHECK-NEXT: atom.add.f32 %r2, [%rd1], %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; @@ -375,6 +33,7 @@ define float @atomic_add_f32_addrspace1(ptr addrspace(1) %addr, float %val) { ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ld.param.b64 %rd1, [atomic_add_f32_addrspace1_param_0]; +; CHECK-NEXT: membar.sys; ; CHECK-NEXT: ld.param.b32 %r1, [atomic_add_f32_addrspace1_param_1]; ; CHECK-NEXT: atom.global.add.f32 %r2, [%rd1], %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; @@ -394,6 +53,7 @@ define float @atomic_add_f32_addrspace3(ptr addrspace(3) %addr, float %val) { ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ld.param.b64 %rd1, [atomic_add_f32_addrspace3_param_0]; +; CHECK-NEXT: membar.sys; ; CHECK-NEXT: ld.param.b32 %r1, [atomic_add_f32_addrspace3_param_1]; ; CHECK-NEXT: atom.shared.add.f32 %r2, [%rd1], %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; @@ -401,136 +61,3 @@ define float @atomic_add_f32_addrspace3(ptr addrspace(3) %addr, float %val) { %ret = call float @llvm.nvvm.atomic.load.add.f32.p3(ptr addrspace(3) %addr, float %val) ret float %ret } - -; CHECK-LABEL: atomicrmw_add_f32_generic -define float @atomicrmw_add_f32_generic(ptr %addr, float %val) { -; CHECK-LABEL: atomicrmw_add_f32_generic( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atomicrmw_add_f32_generic_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atomicrmw_add_f32_generic_param_1]; -; CHECK-NEXT: atom.add.f32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw fadd ptr %addr, float %val seq_cst - ret float %ret -} - -; CHECK-LABEL: atomicrmw_add_f16_generic -define half @atomicrmw_add_f16_generic(ptr %addr, half %val) { -; CHECK-LABEL: atomicrmw_add_f16_generic( -; CHECK: { -; CHECK-NEXT: .reg .pred %p<2>; -; CHECK-NEXT: .reg .b16 %rs<4>; -; CHECK-NEXT: .reg .b32 %r<18>; -; CHECK-NEXT: .reg .b64 %rd<3>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b16 %rs1, [atomicrmw_add_f16_generic_param_1]; -; CHECK-NEXT: ld.param.b64 %rd2, [atomicrmw_add_f16_generic_param_0]; -; CHECK-NEXT: and.b64 %rd1, %rd2, -4; -; CHECK-NEXT: cvt.u32.u64 %r4, %rd2; -; CHECK-NEXT: and.b32 %r5, %r4, 3; -; CHECK-NEXT: shl.b32 %r1, %r5, 3; -; CHECK-NEXT: mov.b32 %r6, 65535; -; CHECK-NEXT: shl.b32 %r7, %r6, %r1; -; CHECK-NEXT: not.b32 %r2, %r7; -; CHECK-NEXT: ld.b32 %r17, [%rd1]; -; CHECK-NEXT: cvt.f32.f16 %r10, %rs1; -; CHECK-NEXT: $L__BB24_1: // %atomicrmw.start -; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: shr.u32 %r8, %r17, %r1; -; CHECK-NEXT: cvt.u16.u32 %rs2, %r8; -; CHECK-NEXT: cvt.f32.f16 %r9, %rs2; -; CHECK-NEXT: add.rn.f32 %r11, %r9, %r10; -; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r11; -; CHECK-NEXT: cvt.u32.u16 %r12, %rs3; -; CHECK-NEXT: shl.b32 %r13, %r12, %r1; -; CHECK-NEXT: and.b32 %r14, %r17, %r2; -; CHECK-NEXT: or.b32 %r15, %r14, %r13; -; CHECK-NEXT: membar.sys; -; CHECK-NEXT: atom.cas.b32 %r3, [%rd1], %r17, %r15; -; CHECK-NEXT: setp.ne.b32 %p1, %r3, %r17; -; CHECK-NEXT: mov.b32 %r17, %r3; -; CHECK-NEXT: @%p1 bra $L__BB24_1; -; CHECK-NEXT: // %bb.2: // %atomicrmw.end -; CHECK-NEXT: shr.u32 %r16, %r3, %r1; -; CHECK-NEXT: st.param.b16 [func_retval0], %r16; -; CHECK-NEXT: ret; - %ret = atomicrmw fadd ptr %addr, half %val seq_cst - ret half %ret -} - -; CHECK-LABEL: atomicrmw_add_f32_addrspace1 -define float @atomicrmw_add_f32_addrspace1(ptr addrspace(1) %addr, float %val) { -; CHECK-LABEL: atomicrmw_add_f32_addrspace1( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atomicrmw_add_f32_addrspace1_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atomicrmw_add_f32_addrspace1_param_1]; -; CHECK-NEXT: atom.global.add.f32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw fadd ptr addrspace(1) %addr, float %val seq_cst - ret float %ret -} - -; CHECK-LABEL: atomicrmw_add_f32_addrspace3 -define float @atomicrmw_add_f32_addrspace3(ptr addrspace(3) %addr, float %val) { -; CHECK-LABEL: atomicrmw_add_f32_addrspace3( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<3>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atomicrmw_add_f32_addrspace3_param_0]; -; CHECK-NEXT: ld.param.b32 %r1, [atomicrmw_add_f32_addrspace3_param_1]; -; CHECK-NEXT: atom.shared.add.f32 %r2, [%rd1], %r1; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %ret = atomicrmw fadd ptr addrspace(3) %addr, float %val seq_cst - ret float %ret -} - -; CHECK-LABEL: atomic_cmpxchg_i32 -define i32 @atomic_cmpxchg_i32(ptr %addr, i32 %cmp, i32 %new) { -; CHECK-LABEL: atomic_cmpxchg_i32( -; CHECK: { -; CHECK-NEXT: .reg .b32 %r<4>; -; CHECK-NEXT: .reg .b64 %rd<2>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atomic_cmpxchg_i32_param_0]; -; CHECK-NEXT: membar.sys; -; CHECK-NEXT: ld.param.b32 %r1, [atomic_cmpxchg_i32_param_1]; -; CHECK-NEXT: ld.param.b32 %r2, [atomic_cmpxchg_i32_param_2]; -; CHECK-NEXT: atom.cas.b32 %r3, [%rd1], %r1, %r2; -; CHECK-NEXT: st.param.b32 [func_retval0], %r2; -; CHECK-NEXT: ret; - %pairold = cmpxchg ptr %addr, i32 %cmp, i32 %new seq_cst seq_cst - ret i32 %new -} - -; CHECK-LABEL: atomic_cmpxchg_i64 -define i64 @atomic_cmpxchg_i64(ptr %addr, i64 %cmp, i64 %new) { -; CHECK-LABEL: atomic_cmpxchg_i64( -; CHECK: { -; CHECK-NEXT: .reg .b64 %rd<5>; -; CHECK-EMPTY: -; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.b64 %rd1, [atomic_cmpxchg_i64_param_0]; -; CHECK-NEXT: membar.sys; -; CHECK-NEXT: ld.param.b64 %rd2, [atomic_cmpxchg_i64_param_1]; -; CHECK-NEXT: ld.param.b64 %rd3, [atomic_cmpxchg_i64_param_2]; -; CHECK-NEXT: atom.cas.b64 %rd4, [%rd1], %rd2, %rd3; -; CHECK-NEXT: st.param.b64 [func_retval0], %rd3; -; CHECK-NEXT: ret; - %pairold = cmpxchg ptr %addr, i64 %cmp, i64 %new seq_cst seq_cst - ret i64 %new -} diff --git a/llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll b/llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll index d895c715ab3ce..3e462b3f94883 100644 --- a/llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll +++ b/llvm/test/CodeGen/NVPTX/cmpxchg-sm60.ll @@ -1,6 +1,7 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 -mattr=+ptx50 | FileCheck %s --check-prefix=SM60 ; RUN: %if ptxas-sm_60 && ptxas-isa-5.0 %{ llc < %s -march=nvptx64 -mcpu=sm_60 -mattr=+ptx50 | %ptxas-verify -arch=sm_60 %} +; NOTE: Please do not modify this file manually- instead modify cmpxchg.py define i8 @monotonic_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %new) { ; SM60-LABEL: monotonic_monotonic_i8_global_cta( diff --git a/llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll b/llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll index 76220ee3a3996..a286360c0f8cc 100644 --- a/llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll +++ b/llvm/test/CodeGen/NVPTX/cmpxchg-sm70.ll @@ -1,6 +1,7 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx63 | FileCheck %s --check-prefix=SM70 ; RUN: %if ptxas-sm_70 && ptxas-isa-6.3 %{ llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx63 | %ptxas-verify -arch=sm_70 %} +; NOTE: Please do not modify this file manually- instead modify cmpxchg.py define i8 @monotonic_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %new) { ; SM70-LABEL: monotonic_monotonic_i8_global_cta( diff --git a/llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll b/llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll index 4cdedb2065e23..17b32b59545d4 100644 --- a/llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll +++ b/llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll @@ -1,6 +1,7 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx87 | FileCheck %s --check-prefix=SM90 ; RUN: %if ptxas-sm_90 && ptxas-isa-8.7 %{ llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx87 | %ptxas-verify -arch=sm_90 %} +; NOTE: Please do not modify this file manually- instead modify cmpxchg.py define i8 @monotonic_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %new) { ; SM90-LABEL: monotonic_monotonic_i8_global_cta( diff --git a/llvm/test/CodeGen/NVPTX/cmpxchg.py b/llvm/test/CodeGen/NVPTX/cmpxchg.py index 75623a59ad481..4b288eabac942 100644 --- a/llvm/test/CodeGen/NVPTX/cmpxchg.py +++ b/llvm/test/CodeGen/NVPTX/cmpxchg.py @@ -22,7 +22,8 @@ run_statement = Template( """; RUN: llc < %s -march=nvptx64 -mcpu=sm_${sm} -mattr=+ptx${ptx} | FileCheck %s --check-prefix=SM${sm} -; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_${sm} -mattr=+ptx${ptx} | %ptxas-verify -arch=sm_${sm} %} +; RUN: %if ptxas-sm_${sm} && ptxas-isa-${ptxfp} %{ llc < %s -march=nvptx64 -mcpu=sm_${sm} -mattr=+ptx${ptx} | %ptxas-verify -arch=sm_${sm} %} +; NOTE: Please do not modify this file manually- instead modify cmpxchg.py """ ) @@ -54,7 +55,7 @@ def get_addrspace_cast(addrspace): if __name__ == "__main__": for sm, ptx in TESTS: with open("cmpxchg-sm{}.ll".format(str(sm)), "w") as fp: - print(run_statement.substitute(sm=sm, ptx=ptx), file=fp) + print(run_statement.substitute(sm=sm, ptx=ptx, ptxfp=ptx / 10.0), file=fp) # Our test space is: SIZES X SUCCESS_ORDERINGS X FAILURE_ORDERINGS X ADDRSPACES X LLVM_SCOPES # This is very large, so we instead test 3 slices. diff --git a/llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll b/llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll index 01cd70d1530b0..6641035a416c2 100644 --- a/llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll +++ b/llvm/test/CodeGen/NVPTX/distributed-shared-cluster.ll @@ -64,12 +64,16 @@ define void @test_distributed_shared_cluster_float_atomic(ptr addrspace(7) %dsme ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: // %entry ; CHECK-NEXT: ld.param.b64 %rd1, [test_distributed_shared_cluster_float_atomic_param_0]; +; CHECK-NEXT: fence.sc.sys; ; CHECK-NEXT: mov.b16 %rs1, 0x3C00; -; CHECK-NEXT: atom.shared::cluster.add.noftz.f16 %rs2, [%rd1], %rs1; +; CHECK-NEXT: atom.acquire.sys.shared::cluster.add.noftz.f16 %rs2, [%rd1], %rs1; +; CHECK-NEXT: fence.sc.sys; ; CHECK-NEXT: mov.b16 %rs3, 0x3F80; -; CHECK-NEXT: atom.shared::cluster.add.noftz.bf16 %rs4, [%rd1], %rs3; -; CHECK-NEXT: atom.shared::cluster.add.f32 %r1, [%rd1], 0f3F800000; -; CHECK-NEXT: atom.shared::cluster.add.f64 %rd2, [%rd1], 0d3FF0000000000000; +; CHECK-NEXT: atom.acquire.sys.shared::cluster.add.noftz.bf16 %rs4, [%rd1], %rs3; +; CHECK-NEXT: fence.sc.sys; +; CHECK-NEXT: atom.acquire.sys.shared::cluster.add.f32 %r1, [%rd1], 0f3F800000; +; CHECK-NEXT: fence.sc.sys; +; CHECK-NEXT: atom.acquire.sys.shared::cluster.add.f64 %rd2, [%rd1], 0d3FF0000000000000; ; CHECK-NEXT: ret; entry: ; Floating point atomic operations @@ -90,20 +94,20 @@ define void @test_distributed_shared_cluster_int_atomic(ptr addrspace(7) %dsmem_ ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: // %entry ; CHECK-NEXT: ld.param.b64 %rd1, [test_distributed_shared_cluster_int_atomic_param_0]; -; CHECK-NEXT: atom.shared::cluster.add.u32 %r1, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.add.u64 %rd2, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.exch.b32 %r2, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.exch.b64 %rd3, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.min.s32 %r3, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.min.s64 %rd4, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.min.u32 %r4, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.min.u64 %rd5, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.max.s32 %r5, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.max.s64 %rd6, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.max.u32 %r6, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.max.u64 %rd7, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.inc.u32 %r7, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.dec.u32 %r8, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.add.u32 %r1, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.add.u64 %rd2, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.exch.b32 %r2, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.exch.b64 %rd3, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.min.s32 %r3, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.min.s64 %rd4, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.min.u32 %r4, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.min.u64 %rd5, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.max.s32 %r5, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.max.s64 %rd6, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.max.u32 %r6, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.max.u64 %rd7, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.inc.u32 %r7, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.dec.u32 %r8, [%rd1], 1; ; CHECK-NEXT: ret; entry: ; Integer add operations @@ -142,12 +146,12 @@ define void @test_distributed_shared_cluster_bitwise_atomic(ptr addrspace(7) %ds ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: // %entry ; CHECK-NEXT: ld.param.b64 %rd1, [test_distributed_shared_cluster_bitwise_atomic_param_0]; -; CHECK-NEXT: atom.shared::cluster.and.b32 %r1, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.and.b64 %rd2, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.or.b32 %r2, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.or.b64 %rd3, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.xor.b32 %r3, [%rd1], 1; -; CHECK-NEXT: atom.shared::cluster.xor.b64 %rd4, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.and.b32 %r1, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.and.b64 %rd2, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.or.b32 %r2, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.or.b64 %rd3, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.xor.b32 %r3, [%rd1], 1; +; CHECK-NEXT: atom.relaxed.sys.shared::cluster.xor.b64 %rd4, [%rd1], 1; ; CHECK-NEXT: ret; entry: ; Bitwise operations diff --git a/llvm/test/CodeGen/NVPTX/div.ll b/llvm/test/CodeGen/NVPTX/div.ll index 00fc3d2341a5e..9f5f081731331 100644 --- a/llvm/test/CodeGen/NVPTX/div.ll +++ b/llvm/test/CodeGen/NVPTX/div.ll @@ -163,4 +163,4 @@ define float @div_fast_vec_ftz(float %a, float %b, float %c, float %d) #0 { ret float %fadd } -attributes #0 = { "denormal-fp-math-f32" = "preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll index a90cfff51e2c6..987fdf8bc6b69 100644 --- a/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll @@ -3004,4 +3004,4 @@ define void @test_trunc_to_v2f16(<2 x float> %a, ptr %p) { attributes #0 = { nounwind } -attributes #2 = { "denormal-fp-math"="preserve-sign" } +attributes #2 = { denormal_fpenv(preservesign) } diff --git a/llvm/test/CodeGen/NVPTX/fast-math.ll b/llvm/test/CodeGen/NVPTX/fast-math.ll index 7e778c40b8302..cc6301bccbdf8 100644 --- a/llvm/test/CodeGen/NVPTX/fast-math.ll +++ b/llvm/test/CodeGen/NVPTX/fast-math.ll @@ -549,4 +549,4 @@ define double @frem_f64(double %a, double %b) { ret double %rem } -attributes #1 = { "denormal-fp-math-f32" = "preserve-sign" } +attributes #1 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/NVPTX/fence-cluster.ll b/llvm/test/CodeGen/NVPTX/fence-cluster.ll index edaf8de3133ca..173ef500fe7fd 100644 --- a/llvm/test/CodeGen/NVPTX/fence-cluster.ll +++ b/llvm/test/CodeGen/NVPTX/fence-cluster.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx87 | FileCheck %s --check-prefix=SM90 ; RUN: %if ptxas-sm_90 && ptxas-isa-8.7 %{ llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx87 | %ptxas-verify -arch=sm_90 %} diff --git a/llvm/test/CodeGen/NVPTX/fence-nocluster.ll b/llvm/test/CodeGen/NVPTX/fence-nocluster.ll index 20f1df4d368e1..31786134a280f 100644 --- a/llvm/test/CodeGen/NVPTX/fence-nocluster.ll +++ b/llvm/test/CodeGen/NVPTX/fence-nocluster.ll @@ -1,10 +1,11 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 -mattr=+ptx50 | FileCheck %s --check-prefix=SM30 -; RUN: %if ptxas-sm_35 && ptxas-isa-5.0 %{ llc < %s -march=nvptx64 -mcpu=sm_35 -mattr=+ptx50 | %ptxas-verify -arch=sm_35 %} +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 -mattr=+ptx50 | FileCheck %s --check-prefix=SM30 +; RUN: %if ptxas-sm_30 && ptxas-isa-5.0 %{ llc < %s -march=nvptx64 -mcpu=sm_30 -mattr=+ptx50 | %ptxas-verify -arch=sm_30 %} ; RUN: llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx60 | FileCheck %s --check-prefix=SM70 ; RUN: %if ptxas-sm_70 && ptxas-isa-6.0 %{ llc < %s -march=nvptx64 -mcpu=sm_70 -mattr=+ptx60 | %ptxas-verify -arch=sm_70 %} ; RUN: llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx87 | FileCheck %s --check-prefix=SM90 ; RUN: %if ptxas-sm_90 && ptxas-isa-8.7 %{ llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx87 | %ptxas-verify -arch=sm_90 %} +; NOTE: Please do not modify this file manually- instead modify fence.py define void @fence_acquire_sys() { ; SM30-LABEL: fence_acquire_sys( diff --git a/llvm/test/CodeGen/NVPTX/fence.py b/llvm/test/CodeGen/NVPTX/fence.py index b9f9d294e6fe8..f968cd36a3f70 100644 --- a/llvm/test/CodeGen/NVPTX/fence.py +++ b/llvm/test/CodeGen/NVPTX/fence.py @@ -15,7 +15,7 @@ run_statement = Template( """; RUN: llc < %s -march=nvptx64 -mcpu=sm_${sm} -mattr=+ptx${ptx} | FileCheck %s --check-prefix=SM${sm} -; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_${sm} -mattr=+ptx${ptx} | %ptxas-verify %}""" +; RUN: %if ptxas-sm_${sm} && ptxas-isa-${ptxfp} %{ llc < %s -march=nvptx64 -mcpu=sm_${sm} -mattr=+ptx${ptx} | %ptxas-verify -arch=sm_${sm} %}""" ) # (sm, ptx) @@ -31,7 +31,11 @@ # non-cluster orderings are supported on SM30, SM70 and SM90 with open("fence-nocluster.ll", "w") as fp: for sm, ptx in TESTS: - print(run_statement.substitute(sm=sm, ptx=ptx), file=fp) + print(run_statement.substitute(sm=sm, ptx=ptx, ptxfp=ptx / 10.0), file=fp) + print( + "; NOTE: Please do not modify this file manually- instead modify fence.py", + file=fp, + ) for ordering, llvm_scope in product(ORDERINGS, LLVM_SCOPES_NO_CLUSTER): print( fence_func.substitute( @@ -44,7 +48,7 @@ # cluster ordering only supported on SM90 with open("fence-cluster.ll", "w") as fp: - print(run_statement.substitute(sm=90, ptx=87), file=fp) + print(run_statement.substitute(sm=90, ptx=87, ptxfp=8.7), file=fp) for ordering in ORDERINGS: print( fence_func.substitute( diff --git a/llvm/test/CodeGen/NVPTX/fexp2.ll b/llvm/test/CodeGen/NVPTX/fexp2.ll index d9e82cc372e24..fe205aca7a278 100644 --- a/llvm/test/CodeGen/NVPTX/fexp2.ll +++ b/llvm/test/CodeGen/NVPTX/fexp2.ll @@ -389,4 +389,4 @@ declare bfloat @llvm.exp2.bf16(bfloat %val) declare <2 x bfloat> @llvm.exp2.v2bf16(<2 x bfloat> %val) -attributes #0 = {"denormal-fp-math"="preserve-sign"} +attributes #0 = {denormal_fpenv(preservesign)} diff --git a/llvm/test/CodeGen/NVPTX/flog2.ll b/llvm/test/CodeGen/NVPTX/flog2.ll index 4aafc986db1d9..f5ae1b1f4bd5d 100644 --- a/llvm/test/CodeGen/NVPTX/flog2.ll +++ b/llvm/test/CodeGen/NVPTX/flog2.ll @@ -215,4 +215,4 @@ declare bfloat @llvm.log2.bf16(bfloat %val) declare <2 x bfloat> @llvm.log2.v2bf16(<2 x bfloat> %val) -attributes #0 = {"denormal-fp-math"="preserve-sign"} +attributes #0 = {denormal_fpenv(preservesign)} diff --git a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll index 92293ab171a12..6b261411d6144 100644 --- a/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll +++ b/llvm/test/CodeGen/NVPTX/fma-relu-contract.ll @@ -52,7 +52,7 @@ define half @fma_f16_expanded_no_nans(half %a, half %b, half %c) #0 { %1 = fmul half %a, %b %2 = fadd half %1, %c %3 = fcmp ogt half %2, 0.0 - %4 = select i1 %3, half %2, half 0.0 + %4 = select nsz i1 %3, half %2, half 0.0 ret half %4 } @@ -113,7 +113,7 @@ define half @fma_f16_expanded_no_nans_multiple_uses_of_fma(half %a, half %b, hal %1 = fmul half %a, %b %2 = fadd half %1, %c %3 = fcmp ogt half %2, 0.0 - %4 = select i1 %3, half %2, half 0.0 + %4 = select nsz i1 %3, half %2, half 0.0 %5 = fadd half %2, 7.0 %6 = fadd half %4, %5 ret half %6 @@ -212,7 +212,7 @@ define half @fma_f16_expanded_maxnum_no_nans(half %a, half %b, half %c) #0 { ; CHECK-SM70-NEXT: ret; %1 = fmul half %a, %b %2 = fadd half %1, %c - %3 = call half @llvm.maxnum.f16(half %2, half 0.0) + %3 = call nsz half @llvm.maxnum.f16(half %2, half 0.0) ret half %3 } @@ -332,7 +332,7 @@ define bfloat @fma_bf16_expanded_no_nans(bfloat %a, bfloat %b, bfloat %c) #0 { %1 = fmul bfloat %a, %b %2 = fadd bfloat %1, %c %3 = fcmp ogt bfloat %2, 0.0 - %4 = select i1 %3, bfloat %2, bfloat 0.0 + %4 = select nsz i1 %3, bfloat %2, bfloat 0.0 ret bfloat %4 } @@ -428,7 +428,7 @@ define bfloat @fma_bf16_expanded_no_nans_multiple_uses_of_fma(bfloat %a, bfloat %1 = fmul bfloat %a, %b %2 = fadd bfloat %1, %c %3 = fcmp ogt bfloat %2, 0.0 - %4 = select i1 %3, bfloat %2, bfloat 0.0 + %4 = select nsz i1 %3, bfloat %2, bfloat 0.0 %5 = fadd bfloat %2, 7.0 %6 = fadd bfloat %4, %5 ret bfloat %6 @@ -491,7 +491,7 @@ define bfloat @fma_bf16_expanded_maxnum_no_nans(bfloat %a, bfloat %b, bfloat %c) ; CHECK-SM70-NEXT: ret; %1 = fmul bfloat %a, %b %2 = fadd bfloat %1, %c - %3 = call bfloat @llvm.maxnum.bf16(bfloat %2, bfloat 0.0) + %3 = call nsz bfloat @llvm.maxnum.bf16(bfloat %2, bfloat 0.0) ret bfloat %3 } @@ -541,7 +541,7 @@ define <2 x half> @fma_f16x2_expanded_no_nans(<2 x half> %a, <2 x half> %b, <2 x %1 = fmul <2 x half> %a, %b %2 = fadd <2 x half> %1, %c %3 = fcmp ogt <2 x half> %2, - %4 = select <2 x i1> %3, <2 x half> %2, <2 x half> + %4 = select nsz <2 x i1> %3, <2 x half> %2, <2 x half> ret <2 x half> %4 } @@ -606,7 +606,7 @@ define <2 x half> @fma_f16x2_expanded_no_nans_multiple_uses_of_fma(<2 x half> %a %1 = fmul <2 x half> %a, %b %2 = fadd <2 x half> %1, %c %3 = fcmp ogt <2 x half> %2, - %4 = select <2 x i1> %3, <2 x half> %2, <2 x half> + %4 = select nsz <2 x i1> %3, <2 x half> %2, <2 x half> %5 = fadd <2 x half> %2, %6 = fadd <2 x half> %4, %5 ret <2 x half> %6 @@ -662,7 +662,7 @@ define <2 x half> @fma_f16x2_expanded_unsafe_with_nans(<2 x half> %a, <2 x half> %1 = fmul <2 x half> %a, %b %2 = fadd <2 x half> %1, %c %3 = fcmp ogt <2 x half> %2, - %4 = select <2 x i1> %3, <2 x half> %2, <2 x half> + %4 = select nsz <2 x i1> %3, <2 x half> %2, <2 x half> ret <2 x half> %4 } @@ -713,7 +713,7 @@ define <2 x half> @fma_f16x2_expanded_maxnum_no_nans(<2 x half> %a, <2 x half> % ; CHECK-SM70-NEXT: ret; %1 = fmul <2 x half> %a, %b %2 = fadd <2 x half> %1, %c - %3 = call <2 x half> @llvm.maxnum.f16x2(<2 x half> %2, <2 x half> ) + %3 = call nsz <2 x half> @llvm.maxnum.f16x2(<2 x half> %2, <2 x half> ) ret <2 x half> %3 } @@ -795,7 +795,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_unsafe_with_nans(<2 x bfloat> %a, <2 x %1 = fmul <2 x bfloat> %a, %b %2 = fadd <2 x bfloat> %1, %c %3 = fcmp ogt <2 x bfloat> %2, - %4 = select <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> + %4 = select nsz <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> ret <2 x bfloat> %4 } @@ -873,7 +873,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_no_nans(<2 x bfloat> %a, <2 x bfloat> % %1 = fmul <2 x bfloat> %a, %b %2 = fadd <2 x bfloat> %1, %c %3 = fcmp ogt <2 x bfloat> %2, - %4 = select <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> + %4 = select nsz <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> ret <2 x bfloat> %4 } @@ -1017,7 +1017,7 @@ define <2 x bfloat> @fma_bf16x2_expanded_no_nans_multiple_uses_of_fma(<2 x bfloa %1 = fmul <2 x bfloat> %a, %b %2 = fadd <2 x bfloat> %1, %c %3 = fcmp ogt <2 x bfloat> %2, - %4 = select <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> + %4 = select nsz <2 x i1> %3, <2 x bfloat> %2, <2 x bfloat> %5 = fadd <2 x bfloat> %2, %6 = fadd <2 x bfloat> %4, %5 ret <2 x bfloat> %6 @@ -1105,8 +1105,8 @@ define <2 x bfloat> @fma_bf16x2_expanded_maxnum_no_nans(<2 x bfloat> %a, <2 x bf ; CHECK-SM70-NEXT: ret; %1 = fmul <2 x bfloat> %a, %b %2 = fadd <2 x bfloat> %1, %c - %3 = call <2 x bfloat> @llvm.maxnum.bf16x2(<2 x bfloat> %2, <2 x bfloat> ) + %3 = call nsz <2 x bfloat> @llvm.maxnum.bf16x2(<2 x bfloat> %2, <2 x bfloat> ) ret <2 x bfloat> %3 } -attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } +attributes #0 = { "no-nans-fp-math"="true" } diff --git a/llvm/test/CodeGen/NVPTX/lit.local.cfg b/llvm/test/CodeGen/NVPTX/lit.local.cfg index 84cce669ec10b..dede5b354bb85 100644 --- a/llvm/test/CodeGen/NVPTX/lit.local.cfg +++ b/llvm/test/CodeGen/NVPTX/lit.local.cfg @@ -1,4 +1,4 @@ if not "NVPTX" in config.root.targets: config.unsupported = True config.suffixes.add(".py") -config.excludes = ["fence.py", "cmpxchg.py"] +config.excludes = ["fence.py", "cmpxchg.py", "atomicrmw.py"] diff --git a/llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll b/llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll index ad78e0fe7438b..6c96eab1439fb 100644 --- a/llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll +++ b/llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll @@ -117,9 +117,9 @@ entry: ; IR-LABEL: @memset_caller ; IR: [[VAL:%[0-9]+]] = trunc i32 %c to i8 -; IR: [[CMPREG:%[0-9]+]] = icmp eq i64 0, %n -; IR: br i1 [[CMPREG]], label %split, label %loadstoreloop -; IR: loadstoreloop: +; IR: [[CMPREG:%[0-9]+]] = icmp ne i64 %n, 0 +; IR: br i1 [[CMPREG]], label %dynamic-memset-expansion-main-body, label %dynamic-memset-post-expansion +; IR: dynamic-memset-expansion-main-body: ; IR: [[STOREPTR:%[0-9]+]] = getelementptr inbounds i8, ptr %dst, i64 ; IR-NEXT: store i8 [[VAL]], ptr [[STOREPTR]] @@ -141,7 +141,7 @@ entry: ; IR-LABEL: @volatile_memset_caller ; IR: [[VAL:%[0-9]+]] = trunc i32 %c to i8 -; IR: loadstoreloop: +; IR: dynamic-memset-expansion-main-body: ; IR: [[STOREPTR:%[0-9]+]] = getelementptr inbounds i8, ptr %dst, i64 ; IR-NEXT: store volatile i8 [[VAL]], ptr [[STOREPTR]] } diff --git a/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll b/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll index 714cac19b782c..94f1d3fff2040 100644 --- a/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll +++ b/llvm/test/CodeGen/NVPTX/math-intrins-sm80-ptx70-instcombine.ll @@ -318,5 +318,5 @@ define <2 x half> @fma_rn_ftz_f16x2_no_attr(<2 x half> %0, <2 x half> %1, <2 x h ret <2 x half> %res } -attributes #0 = { "denormal-fp-math"="preserve-sign" } -attributes #1 = { "denormal-fp-math-f32"="preserve-sign" } +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/NVPTX/math-intrins.ll b/llvm/test/CodeGen/NVPTX/math-intrins.ll index a35d6ec8f17f6..1ed296269c521 100644 --- a/llvm/test/CodeGen/NVPTX/math-intrins.ll +++ b/llvm/test/CodeGen/NVPTX/math-intrins.ll @@ -1839,4 +1839,4 @@ define double @fma_double(double %a, double %b, double %c) { } attributes #0 = { nounwind readnone } -attributes #1 = { "denormal-fp-math-f32" = "preserve-sign" } +attributes #1 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/NVPTX/nvptx-prec-divf32-flag.ll b/llvm/test/CodeGen/NVPTX/nvptx-prec-divf32-flag.ll index aaa3dfa86b1d1..9c9a3dff482e3 100644 --- a/llvm/test/CodeGen/NVPTX/nvptx-prec-divf32-flag.ll +++ b/llvm/test/CodeGen/NVPTX/nvptx-prec-divf32-flag.ll @@ -6,7 +6,7 @@ target triple = "nvptx64-nvidia-cuda" -define float @div_ftz(float %a, float %b) "denormal-fp-math-f32" = "preserve-sign" { +define float @div_ftz(float %a, float %b) denormal_fpenv(float: preservesign) { ; APPROX-LABEL: div_ftz( ; APPROX: { ; APPROX-NEXT: .reg .b32 %r<4>; diff --git a/llvm/test/CodeGen/NVPTX/pm-event.ll b/llvm/test/CodeGen/NVPTX/pm-event.ll index 871da6d414978..cb693b2639198 100644 --- a/llvm/test/CodeGen/NVPTX/pm-event.ll +++ b/llvm/test/CodeGen/NVPTX/pm-event.ll @@ -5,11 +5,27 @@ declare void @llvm.nvvm.pm.event.mask(i16 %mask) ; CHECK-LABEL: test_pm_event define void @test_pm_event() { - ; CHECK: pmevent.mask 255; + ; CHECK: pmevent.mask 0xffU; call void @llvm.nvvm.pm.event.mask(i16 u0xff) - ; CHECK: pmevent.mask 4096; + ; CHECK: pmevent.mask 0x1000U; call void @llvm.nvvm.pm.event.mask(i16 u0x1000) + ; CHECK: pmevent.mask 0x8000U; + call void @llvm.nvvm.pm.event.mask(i16 u0x8000) + + ; CHECK: pmevent.mask 0xffffU; + call void @llvm.nvvm.pm.event.mask(i16 u0xFFFF) + + ;; LLVM IR doesn't distinguish signed and unsigned integers. So, NVVM calls + ;; with negative integers are functionally correct here and processed + ;; correctly in NVPTX backend + + ; CHECK: pmevent.mask 0x8000U; + call void @llvm.nvvm.pm.event.mask(i16 -32768) + + ; CHECK: pmevent.mask 0xffffU; + call void @llvm.nvvm.pm.event.mask(i16 -1) + ret void } diff --git a/llvm/test/CodeGen/NVPTX/rsqrt-opt.ll b/llvm/test/CodeGen/NVPTX/rsqrt-opt.ll index 7a235b17f7d5a..7c06d5426583c 100644 --- a/llvm/test/CodeGen/NVPTX/rsqrt-opt.ll +++ b/llvm/test/CodeGen/NVPTX/rsqrt-opt.ll @@ -72,4 +72,4 @@ declare float @llvm.nvvm.sqrt.approx.f(float) declare float @llvm.nvvm.sqrt.approx.ftz.f(float) declare float @llvm.sqrt.f32(float) -attributes #0 = { "denormal-fp-math-f32" = "preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/CodeGen/NVPTX/sqrt-approx.ll b/llvm/test/CodeGen/NVPTX/sqrt-approx.ll index 7e4e701af4cd1..a9e35b85e1b5b 100644 --- a/llvm/test/CodeGen/NVPTX/sqrt-approx.ll +++ b/llvm/test/CodeGen/NVPTX/sqrt-approx.ll @@ -436,5 +436,5 @@ define double @test_sqrt64_refined_ftz_ninf(double %a) #1 #2 { ret double %ret } -attributes #1 = { "denormal-fp-math-f32" = "preserve-sign,preserve-sign" } +attributes #1 = { denormal_fpenv(float: preservesign) } attributes #2 = { "reciprocal-estimates" = "rsqrtf:1,rsqrtd:1,sqrtf:1,sqrtd:1" } diff --git a/llvm/test/CodeGen/PowerPC/aix-debug-aranges.ll b/llvm/test/CodeGen/PowerPC/aix-debug-aranges.ll new file mode 100644 index 0000000000000..7b850b6f2a2d0 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-debug-aranges.ll @@ -0,0 +1,28 @@ +; RUN: llc -filetype=obj -function-sections -generate-arange-section < %s | \ +; RUN: llvm-objdump -dr - | FileCheck %s + +; Make sure that enabling debug_arange does not corrupt branches. + +target triple = "powerpc64-ibm-aix" + +define i64 @fn1() { +; CHECK-LABEL: <.fn1>: +; CHECK: bl {{.*}} <.fn2> +; CHECK-NEXT: R_RBR .fn2 + %1 = call i64 @fn2() + ret i64 %1 +} + +define i64 @fn2() !dbg !4 { + ret i64 0 +} + +!llvm.module.flags = !{!0} +!llvm.dbg.cu = !{!1} + +!0 = !{i32 2, !"Debug Info Version", i32 3} +!1 = distinct !DICompileUnit(language: DW_LANG_Rust, file: !2, producer: "clang LLVM (rustc version 1.95.0-dev)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !3, globals: !3, splitDebugInlining: false, nameTableKind: None) +!2 = !DIFile(filename: "foo", directory: "") +!3 = !{} +!4 = distinct !DISubprogram(name: "fn2", file: !2, line: 277, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !1, templateParams: !3, retainedNodes: !3) +!5 = !DISubroutineType(types: !3) diff --git a/llvm/test/CodeGen/PowerPC/aix-ifunc-alias.ll b/llvm/test/CodeGen/PowerPC/aix-ifunc-alias.ll new file mode 100644 index 0000000000000..e1067e12e1954 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-ifunc-alias.ll @@ -0,0 +1,16 @@ +; XFAIL: * +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff %s -o - | FileCheck %s + +@foo_alias = alias i32 (...), ptr @my_foo +@foo = ifunc i32 (...), ptr @foo.resolver + +define hidden i32 @my_foo() { +entry: + ret i32 4 +} + +define internal ptr @foo.resolver() { +entry: + ret ptr @my_foo +} + diff --git a/llvm/test/CodeGen/PowerPC/aix-ifunc-debug.ll b/llvm/test/CodeGen/PowerPC/aix-ifunc-debug.ll new file mode 100644 index 0000000000000..2e7e1e848e914 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-ifunc-debug.ll @@ -0,0 +1,33 @@ +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs %s -o - | FileCheck %s + +; CHECK: .foo: +; CHECK: bctr +; CHECK-NEXT: L..sec_end0: + +@foo = ifunc i32 (...), ptr @foo.resolver + +define internal ptr @foo.resolver() #0 !dbg !7 { +entry: + ret ptr @my_foo2, !dbg !10 +} + +; Function Attrs: nounwind +define internal i32 @my_foo2() #1 !dbg !11 { +entry: + ret i32 5, !dbg !12 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 22.0.0git (git@github.ibm.com:compiler/llvm-project.git e963806df98c6d2e52573efbb8890ec72e5dd745)", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "t.c", directory: "/home/wyehia/Source/scripts.fmv/fmv/ifunc/proto2") +!2 = !{i32 7, !"Dwarf Version", i32 3} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!7 = distinct !DISubprogram(name: "foo_resolver", scope: !1, file: !1, line: 7, type: !8, scopeLine: 7, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !0, keyInstructions: true) +!8 = !DISubroutineType(types: !9) +!9 = !{} +!10 = !DILocation(line: 7, scope: !7, atomGroup: 1, atomRank: 1) +!11 = distinct !DISubprogram(name: "my_foo2", scope: !1, file: !1, line: 2, type: !8, scopeLine: 2, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !0, keyInstructions: true) +!12 = !DILocation(line: 2, scope: !11, atomGroup: 1, atomRank: 1) diff --git a/llvm/test/CodeGen/PowerPC/aix-ifunc-obj.ll b/llvm/test/CodeGen/PowerPC/aix-ifunc-obj.ll new file mode 100644 index 0000000000000..40733c3e504d5 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-ifunc-obj.ll @@ -0,0 +1,89 @@ +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff %s --filetype=obj -o %t.o +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck %s --check-prefixes=CHECK,CHECK-NO-FS + +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff %s --function-sections --filetype=obj -o %t.o +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck %s --check-prefixes=CHECK,CHECK-FS + +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff --function-sections --code-model=large --filetype=obj %s -o %t.o +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck %s --check-prefixes=CHECK-LARGE,CHECK-LARGE-FS + +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff --code-model=large --filetype=obj %s -o %t.o +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck %s --check-prefixes=CHECK-LARGE + +; CHECK: Disassembly of section .text: +;;;; R_REF relocations associating .foo to (1) the __init_ifuncs constructor +;;;; and (2) the __update_foo variable. +; CHECK-NO-FS: 0000000000000000: R_REF {{.*}} __ifunc_sec[RW] +; CHECK-NO-FS-NEXT: 0000000000000000: R_REF {{.*}} .__init_ifuncs[PR] + +;;;; .foo ifunc stub +; CHECK-NO-FS: .foo: +; CHECK-NO-FS-NEXT: ld 12, 8(2) +; CHECK-NO-FS-NEXT: R_TOC {{.*}} foo[TC] +; CHECK-NO-FS-NEXT: ld 11, 16(12) +; CHECK-NO-FS-NEXT: ld 12, 0(12) +; CHECK-NO-FS-NEXT: mtctr 12 +; CHECK-NO-FS-NEXT: bctr + +; CHECK-FS: .foo[PR]: +; CHECK-FS-NEXT: ld 12, 8(2) +; CHECK-FS-NEXT: R_REF {{.*}} __ifunc_sec[RW] +; CHECK-FS-NEXT: R_REF {{.*}} .__init_ifuncs[PR] +; CHECK-FS-NEXT: R_TOC {{.*}} foo[TC] +; CHECK-FS-NEXT: ld 11, 16(12) +; CHECK-FS-NEXT: ld 12, 0(12) +; CHECK-FS-NEXT: mtctr 12 +; CHECK-FS-NEXT: bctr + +; CHECK-LARGE: {{\.foo|\.foo\[PR\]}}: +; CHECK-LARGE-NEXT: addis 12, 2, 0 +; CHECK-LARGE-FS-NEXT: R_REF {{.*}} __ifunc_sec[RW] +; CHECK-LARGE-FS-NEXT: R_REF {{.*}} .__init_ifuncs[PR] +; CHECK-LARGE-NEXT: R_TOCU {{.*}} foo[TE] +; CHECK-LARGE-NEXT: ld 12, 8(12) +; CHECK-LARGE-NEXT: R_TOCL {{.*}} foo[TE] +; CHECK-LARGE-NEXT: ld 11, 16(12) +; CHECK-LARGE-NEXT: ld 12, 0(12) +; CHECK-LARGE-NEXT: mtctr 12 +; CHECK-LARGE-NEXT: bctr + +; CHECK: Disassembly of section .data: +;;;; section __ifunc_sec holding the [foo:foo_resolver] pairs +;;;; @__update_foo = private global { ptr, ptr } { ptr @foo, ptr @foo.resolver }, section "__ifunc_sec", align 8 +; CHECK: {{.*}} __ifunc_sec[RW]: +; CHECK-NEXT: 00 00 00 00 +; CHECK-NEXT: R_POS {{.*}} foo[DS] +; CHECK-NEXT: {{.*}} +; CHECK-NEXT: 00 00 00 00 +; CHECK-NEXT: R_POS {{.*}} foo.resolver[DS] + +;;;; A function descriptor for foo +; CHECK: {{.*}} foo[DS]: +; CHECK-NEXT: 00 00 00 00 +; CHECK-NEXT: R_POS {{.*}} .foo +; CHECK-NEXT: {{.*}} +; CHECK-NEXT: 00 00 00 00 +; CHECK-NEXT: R_POS {{.*}} TOC[TC0] + +;;;; foo's TOC +; CHECK: {{.*}} foo[TC]: +; CHECK-NEXT: 00 00 00 00 +; CHECK-NEXT: R_POS {{.*}} foo[DS] +; CHECK-NEXT: {{.*}} + +; CHECK-LARGE: {{.*}} foo[TE]: +; CHECK-LARGE-NEXT: +; CHECK-LARGE-NEXT: R_POS {{.*}} foo[DS] +; CHECK-LARGE-NEXT: + +@foo = ifunc i32 (...), ptr @foo.resolver + +define hidden i32 @my_foo() { +entry: + ret i32 4 +} + +define internal ptr @foo.resolver() { +entry: + ret ptr @my_foo +} diff --git a/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query-neg.ll b/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query-neg.ll new file mode 100644 index 0000000000000..54c6fe734cb2d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query-neg.ll @@ -0,0 +1,96 @@ +; REQUIRES: target=powerpc{{.*}} +; REQUIRES: asserts +; This testcase is for testing the negative return values of the +; TOCRestoreNeededForCallToImplementation query. + +; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -test-ifunc-warn-noerror -filetype=obj -o /dev/null 2>&1 | FileCheck %s + +; CHECK: TOC register save/restore needed for ifunc "foo_ext_decl_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_default_decl_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_weak_decl_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_hidden_weak_decl_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_protected_weak_decl_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_default_weak_decl_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_def_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_default_def_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_weak_def_ifunc" +; CHECK: TOC register save/restore needed for ifunc "foo_ext_default_weak_def_ifunc" + + +define void @foo_ext_def() { +entry: + ret void +} +define void @foo_ext_default_def() { +entry: + ret void +} +define weak void @foo_ext_default_weak_def() { +entry: + ret void +} +define weak void @foo_ext_weak_def() { +entry: + ret void +} +declare void @foo_ext_decl(...) +declare void @foo_ext_default_decl(...) +declare extern_weak void @foo_ext_weak_decl(...) +declare extern_weak hidden void @foo_ext_hidden_weak_decl(...) +declare extern_weak protected void @foo_ext_protected_weak_decl(...) +declare extern_weak void @foo_ext_default_weak_decl(...) + + +define internal ptr @foo_ext_decl_resolver() { +entry: + ret ptr @foo_ext_decl +} +define internal ptr @foo_ext_default_decl_resolver() { +entry: + ret ptr @foo_ext_default_decl +} +define internal ptr @foo_ext_weak_decl_resolver() { +entry: + ret ptr @foo_ext_weak_decl +} +define internal ptr @foo_ext_hidden_weak_decl_resolver() { +entry: + ret ptr @foo_ext_hidden_weak_decl +} +define internal ptr @foo_ext_protected_weak_decl_resolver() { +entry: + ret ptr @foo_ext_protected_weak_decl +} +define internal ptr @foo_ext_default_weak_decl_resolver() { +entry: + ret ptr @foo_ext_default_weak_decl +} +define internal ptr @foo_ext_def_resolver() { +entry: + ret ptr @foo_ext_def +} +define internal ptr @foo_ext_default_def_resolver() { +entry: + ret ptr @foo_ext_default_def +} +define internal ptr @foo_ext_weak_def_resolver() { +entry: + ret ptr @foo_ext_weak_def +} +define internal ptr @foo_ext_default_weak_def_resolver() { +entry: + ret ptr @foo_ext_default_weak_def +} + +@foo_ext_decl_ifunc = ifunc i32 (...), ptr @foo_ext_decl_resolver +@foo_ext_default_decl_ifunc = ifunc i32 (...), ptr @foo_ext_default_decl_resolver +@foo_ext_weak_decl_ifunc = ifunc i32 (...), ptr @foo_ext_weak_decl_resolver +@foo_ext_hidden_weak_decl_ifunc = ifunc i32 (...), ptr @foo_ext_hidden_weak_decl_resolver +@foo_ext_protected_weak_decl_ifunc = ifunc i32 (...), ptr @foo_ext_protected_weak_decl_resolver +@foo_ext_default_weak_decl_ifunc = ifunc i32 (...), ptr @foo_ext_default_weak_decl_resolver +@foo_ext_def_ifunc = ifunc i32 (...), ptr @foo_ext_def_resolver +@foo_ext_default_def_ifunc = ifunc i32 (...), ptr @foo_ext_default_def_resolver +@foo_ext_weak_def_ifunc = ifunc i32 (...), ptr @foo_ext_weak_def_resolver +@foo_ext_default_weak_def_ifunc = ifunc i32 (...), ptr @foo_ext_default_weak_def_resolver + + diff --git a/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query.ll b/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query.ll new file mode 100644 index 0000000000000..20d24d30db855 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-ifunc-toc-restore-query.ll @@ -0,0 +1,78 @@ +; This testcase is for testing the positive return values of the +; TOCRestoreNeededForCallToImplementation query, specifically the type of +; functions that are considered DSO local on AIX. + +; REQUIRES: asserts +; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff --function-sections -filetype=obj -o /dev/null -debug-only=asmprinter 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff --function-sections -filetype=obj -o /dev/null -debug-only=asmprinter 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff -ifunc-local-if-proven=1 -o /dev/null -debug-only=asmprinter 2>&1 | FileCheck %s + +; CHECK: foo_ext_hidden_decl is dso_local +; CHECK: foo_ext_hidden_def is dso_local +; CHECK: foo_ext_hidden_weak_def is dso_local +; CHECK: foo_ext_protected_decl is dso_local +; CHECK: foo_ext_protected_def is dso_local +; CHECK: foo_ext_protected_weak_def is dso_local +; CHECK: foo_static is dso_local + +; The following decls/defs are dso_local in the IR, and it matches the behaviour on AIX in practice +; (1) a hidden/protected declaration should have a matching definition in the same shared object, +; with the matching visibility. So the definition is not interposable due to hidden/protected. +; (2) a hidden/protected definition is not interposable. +; (3) attribute weak has no effect on interposition, and if a strong definition in the same shared object +; exists, then it's a user error to have that definition have conflicting visibility. +; In practice, on AIX the linker will silently pick the strong definition and keep it's visibility +; ignoring what's on the weak definition. +; On Linux, both ld and lld pick the strong definition but give it the most restrictive visibility based +; on the candidates available (so a weak hidden and a strong default will yield a hidden strong) +; +declare hidden void @foo_ext_hidden_decl(...) ; (1) + +declare protected void @foo_ext_protected_decl(...) ; (1) + +define hidden void @foo_ext_hidden_def() { ; (2) +entry: + ret void +} + +define protected void @foo_ext_protected_def() { ; (2) +entry: + ret void +} + +define weak hidden void @foo_ext_hidden_weak_def() { ; (3) +entry: + ret void +} + +define weak protected void @foo_ext_protected_weak_def() { ; (3) +entry: + ret void +} + +define internal void @foo_static() { +entry: + ret void +} + +@foo = ifunc void (...), ptr @resolve_foo + +@x = global i32 0, align 4 + +@switch.table.bar = private unnamed_addr constant [6 x ptr] [ptr @foo_ext_hidden_decl, ptr @foo_ext_hidden_def, ptr @foo_ext_hidden_weak_def, ptr @foo_ext_protected_decl, ptr @foo_ext_protected_def, ptr @foo_ext_protected_weak_def], align 4 + +define internal nonnull ptr @resolve_foo() { +entry: + %x = load i32, ptr @x, align 4 + %0 = icmp ult i32 %x, 6 + br i1 %0, label %switch.lookup, label %return + +switch.lookup: ; preds = %entry + %switch.gep = getelementptr inbounds nuw ptr, ptr @switch.table.bar, i32 %x + %switch.load = load ptr, ptr %switch.gep, align 4 + br label %return + +return: ; preds = %entry, %switch.lookup + %retval.0 = phi ptr [ %switch.load, %switch.lookup ], [ @foo_static, %entry ] + ret ptr %retval.0 +} diff --git a/llvm/test/CodeGen/PowerPC/aix-ifunc.ll b/llvm/test/CodeGen/PowerPC/aix-ifunc.ll new file mode 100644 index 0000000000000..32ba3afbfe48e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-ifunc.ll @@ -0,0 +1,75 @@ +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff %s -o - | FileCheck %s --check-prefixes=COMMON,NO-FUNCSECT -DALIGN=3 -DPTR_SIZE=8 -DLOAD=ld -DOFF=16 +; RUN: llc -mtriple=powerpc-ibm-aix-xcoff %s -o - | FileCheck %s --check-prefixes=COMMON,NO-FUNCSECT -DALIGN=2 -DPTR_SIZE=4 -DLOAD=lwz -DOFF=8 + +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff --function-sections %s -o - | FileCheck %s --check-prefixes=COMMON,FUNCSECT -DALIGN=3 -DPTR_SIZE=8 -DLOAD=ld -DOFF=16 +; RUN: llc -mtriple=powerpc-ibm-aix-xcoff --function-sections %s -o - | FileCheck %s --check-prefixes=COMMON,FUNCSECT -DALIGN=2 -DPTR_SIZE=4 -DLOAD=lwz -DOFF=8 + +; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff --function-sections --code-model=large %s -o - | FileCheck %s --check-prefixes=LARGE -DALIGN=3 -DPTR_SIZE=8 -DLOAD=ld -DOFF=16 +; RUN: llc -mtriple=powerpc-ibm-aix-xcoff --function-sections --code-model=large %s -o - | FileCheck %s --check-prefixes=LARGE -DALIGN=2 -DPTR_SIZE=4 -DLOAD=lwz -DOFF=8 + +;;;; section __ifunc_sec holding the [foo:foo_resolver] pairs +; COMMON: .csect __ifunc_sec[RW],2 +; COMMON-NEXT: .align [[ALIGN]] +; COMMON-NEXT: L..__update_foo: +; COMMON-NEXT: .vbyte [[PTR_SIZE]], foo[DS] +; COMMON-NEXT: .vbyte [[PTR_SIZE]], foo.resolver[DS] + +;;;; forward declare the __init_ifuncs constructor +; COMMON-NEXT: .extern .__init_ifuncs[PR] + +;;;; declare foo[DS] and .foo[PR] +; FUNCSECT-NEXT: .csect .foo[PR],5 +; FUNCSECT-NEXT: .ref L..__update_foo +; FUNCSECT-NEXT: .ref .__init_ifuncs[PR] +; FUNCSECT-NEXT: .globl foo[DS] +; FUNCSECT-NEXT: .globl .foo[PR] +; FUNCSECT-NEXT: .align 2 + +; NO-FUNCSECT-NEXT: .csect ..text..[PR],5 +; NO-FUNCSECT-NEXT: .ref L..__update_foo +; NO-FUNCSECT-NEXT: .ref .__init_ifuncs[PR] +; NO-FUNCSECT-NEXT: .globl foo[DS] +; NO-FUNCSECT-NEXT: .globl .foo +; NO-FUNCSECT-NEXT: .align 2 + +;;;; define foo's descriptor +; COMMON-NEXT: .csect foo[DS],[[ALIGN]] +; FUNCSECT-NEXT: .vbyte [[PTR_SIZE]], .foo[PR] +; NO-FUNCSECT-NEXT: .vbyte [[PTR_SIZE]], .foo +; COMMON-NEXT: .vbyte [[PTR_SIZE]], TOC[TC0] +; COMMON-NEXT: .vbyte [[PTR_SIZE]], 0 + +;;;; emit foo's body +; FUNCSECT-NEXT: .csect .foo[PR],5 +; NO-FUNCSECT-NEXT: .csect ..text..[PR],5 +; NO-FUNCSECT-NEXT: .foo: +; COMMON-NEXT: [[LOAD]] 12, [[FOO_TOC:.*]](2) +; COMMON-NEXT: [[LOAD]] 11, [[OFF]](12) +; COMMON-NEXT: [[LOAD]] 12, 0(12) +; COMMON-NEXT: mtctr 12 +; COMMON-NEXT: bctr + +; -mcmodel=large: +; LARGE: .csect .foo[PR],5 +; LARGE: addis 12, [[FOO_TOC:.*]]@u(2) +; LARGE-NEXT: [[LOAD]] 12, [[FOO_TOC]]@l(12) +; LARGE-NEXT: [[LOAD]] 11, [[OFF]](12) +; LARGE-NEXT: [[LOAD]] 12, 0(12) + +;;;; foo's TOC entry +; COMMON: [[FOO_TOC]]: +; COMMON-NEXT: .tc foo[TC],foo[DS] +; LARGE: [[FOO_TOC]]: +; LARGE-NEXT: .tc foo[TE],foo[DS] + +@foo = ifunc i32 (...), ptr @foo.resolver + +define hidden i32 @my_foo() { +entry: + ret i32 4 +} + +define internal ptr @foo.resolver() { +entry: + ret ptr @my_foo +} diff --git a/llvm/test/CodeGen/PowerPC/change-no-infs.ll b/llvm/test/CodeGen/PowerPC/change-no-infs.ll deleted file mode 100644 index 0cd5eb5408e3e..0000000000000 --- a/llvm/test/CodeGen/PowerPC/change-no-infs.ll +++ /dev/null @@ -1,67 +0,0 @@ -; Check that we can enable/disable NoInfsFPMath and NoNaNsInFPMath via function -; attributes. An attribute on one function should not magically apply to the -; next one. - -; RUN: llc < %s -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 -mattr=-vsx \ -; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=SAFE - -; RUN: llc < %s -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 -mattr=-vsx \ -; RUN: -enable-no-infs-fp-math -enable-no-nans-fp-math \ -; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=UNSAFE - -; The fcmp+select in these functions should be converted to a fsel instruction -; when both NoInfsFPMath and NoNaNsInFPMath are enabled. - -; CHECK-LABEL: default0: -define double @default0(double %a, double %y, double %z) { -entry: -; SAFE-NOT: fsel -; UNSAFE: fsel - %cmp = fcmp ult double %a, 0.000000e+00 - %z.y = select i1 %cmp, double %z, double %y - ret double %z.y -} - -; CHECK-LABEL: unsafe_math_off: -define double @unsafe_math_off(double %a, double %y, double %z) #0 #2 { -entry: -; SAFE-NOT: fsel -; UNSAFE-NOT: fsel - %cmp = fcmp ult double %a, 0.000000e+00 - %z.y = select i1 %cmp, double %z, double %y - ret double %z.y -} - -; CHECK-LABEL: default1: -define double @default1(double %a, double %y, double %z) { -; SAFE-NOT: fsel -; UNSAFE: fsel - %cmp = fcmp ult double %a, 0.000000e+00 - %z.y = select i1 %cmp, double %z, double %y - ret double %z.y -} - -; CHECK-LABEL: unsafe_math_on: -define double @unsafe_math_on(double %a, double %y, double %z) #1 #3 { -entry: -; SAFE-NOT: fsel -; UNSAFE-NOT: fsel - %cmp = fcmp ult double %a, 0.000000e+00 - %z.y = select i1 %cmp, double %z, double %y - ret double %z.y -} - -; CHECK-LABEL: default2: -define double @default2(double %a, double %y, double %z) { -; SAFE-NOT: fsel -; UNSAFE: fsel - %cmp = fcmp ult double %a, 0.000000e+00 - %z.y = select i1 %cmp, double %z, double %y - ret double %z.y -} - -attributes #0 = { "no-infs-fp-math"="false" } -attributes #1 = { "no-nans-fp-math"="false" } - -attributes #2 = { "no-infs-fp-math"="false" } -attributes #3 = { "no-infs-fp-math"="true" } diff --git a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll index baa127e451701..5ba9b1e28a45e 100644 --- a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll +++ b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll @@ -632,8 +632,8 @@ define float @fneg_fsub_nozeros_1(float %x, float %y, float %z) { ret float %add } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; FMFDEBUG: {{.*}} ; GLOBALDEBUG: {{.*}} diff --git a/llvm/test/CodeGen/PowerPC/fsel.ll b/llvm/test/CodeGen/PowerPC/fsel.ll index dea442d8404e1..42629e5176696 100644 --- a/llvm/test/CodeGen/PowerPC/fsel.ll +++ b/llvm/test/CodeGen/PowerPC/fsel.ll @@ -1,6 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -13,14 +12,21 @@ entry: ; CHECK: @zerocmp1 ; CHECK-NOT: fsel ; CHECK: blr +} -; CHECK-FM: @zerocmp1 -; CHECK-FM: fsel 1, 1, 2, 3 -; CHECK-FM: blr +define double @zerocmp1_finite(double %a, double %y, double %z) #0 { +entry: + %cmp = fcmp ninf nnan ult double %a, 0.000000e+00 + %z.y = select i1 %cmp, double %z, double %y + ret double %z.y -; CHECK-FM-VSX: @zerocmp1 -; CHECK-FM-VSX: fsel 1, 1, 2, 3 -; CHECK-FM-VSX: blr +; CHECK: @zerocmp1_finite +; CHECK: fsel 1, 1, 2, 3 +; CHECK: blr + +; CHECK-VSX: @zerocmp1_finite +; CHECK-VSX: fsel 1, 1, 2, 3 +; CHECK-VSX: blr } define double @zerocmp2(double %a, double %y, double %z) #0 { @@ -32,16 +38,23 @@ entry: ; CHECK: @zerocmp2 ; CHECK-NOT: fsel ; CHECK: blr +} -; CHECK-FM: @zerocmp2 -; CHECK-FM: fneg [[REG:[0-9]+]], 1 -; CHECK-FM: fsel 1, [[REG]], 3, 2 -; CHECK-FM: blr +define double @zerocmp2_finite(double %a, double %y, double %z) #0 { +entry: + %cmp = fcmp ninf nnan ogt double %a, 0.000000e+00 + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z -; CHECK-FM-VSX: @zerocmp2 -; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1 -; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2 -; CHECK-FM-VSX: blr +; CHECK: @zerocmp2_finite +; CHECK: fneg [[REG:[0-9]+]], 1 +; CHECK: fsel 1, [[REG]], 3, 2 +; CHECK: blr + +; CHECK-VSX: @zerocmp2_finite +; CHECK-VSX: xsnegdp [[REG:[0-9]+]], 1 +; CHECK-VSX: fsel 1, [[REG]], 3, 2 +; CHECK-VSX: blr } define double @zerocmp3(double %a, double %y, double %z) #0 { @@ -53,18 +66,25 @@ entry: ; CHECK: @zerocmp3 ; CHECK-NOT: fsel ; CHECK: blr +} -; CHECK-FM: @zerocmp3 -; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3 -; CHECK-FM: fneg [[REG2:[0-9]+]], 1 -; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3 -; CHECK-FM: blr +define double @zerocmp3_finite(double %a, double %y, double %z) #0 { +entry: + %cmp = fcmp ninf nnan oeq double %a, 0.000000e+00 + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z -; CHECK-FM-VSX: @zerocmp3 -; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3 -; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 1 -; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3 -; CHECK-FM-VSX: blr +; CHECK: @zerocmp3_finite +; CHECK: fsel [[REG:[0-9]+]], 1, 2, 3 +; CHECK: fneg [[REG2:[0-9]+]], 1 +; CHECK: fsel 1, [[REG2]], [[REG]], 3 +; CHECK: blr + +; CHECK-VSX: @zerocmp3_finite +; CHECK-VSX: fsel [[REG:[0-9]+]], 1, 2, 3 +; CHECK-VSX: xsnegdp [[REG2:[0-9]+]], 1 +; CHECK-VSX: fsel 1, [[REG2]], [[REG]], 3 +; CHECK-VSX: blr } define double @min1(double %a, double %b) #0 { @@ -76,16 +96,23 @@ entry: ; CHECK: @min1 ; CHECK-NOT: fsel ; CHECK: blr +} -; CHECK-FM: @min1 -; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1 -; CHECK-FM: fsel 1, [[REG]], 1, 2 -; CHECK-FM: blr +define double @min1_finite(double %a, double %b) #0 { +entry: + %cmp = fcmp ninf nnan ole double %a, %b + %cond = select i1 %cmp, double %a, double %b + ret double %cond -; CHECK-FM-VSX: @min1 -; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1 -; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2 -; CHECK-FM-VSX: blr +; CHECK: @min1_finite +; CHECK: fsub [[REG:[0-9]+]], 2, 1 +; CHECK: fsel 1, [[REG]], 1, 2 +; CHECK: blr + +; CHECK-VSX: @min1_finite +; CHECK-VSX: xssubdp [[REG:[0-9]+]], 2, 1 +; CHECK-VSX: fsel 1, [[REG]], 1, 2 +; CHECK-VSX: blr } define double @max1(double %a, double %b) #0 { @@ -97,16 +124,23 @@ entry: ; CHECK: @max1 ; CHECK-NOT: fsel ; CHECK: blr +} -; CHECK-FM: @max1 -; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2 -; CHECK-FM: fsel 1, [[REG]], 1, 2 -; CHECK-FM: blr +define double @max1_finite(double %a, double %b) #0 { +entry: + %cmp = fcmp ninf nnan oge double %a, %b + %cond = select i1 %cmp, double %a, double %b + ret double %cond -; CHECK-FM-VSX: @max1 -; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2 -; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2 -; CHECK-FM-VSX: blr +; CHECK: @max1_finite +; CHECK: fsub [[REG:[0-9]+]], 1, 2 +; CHECK: fsel 1, [[REG]], 1, 2 +; CHECK: blr + +; CHECK-VSX: @max1_finite +; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2 +; CHECK-VSX: fsel 1, [[REG]], 1, 2 +; CHECK-VSX: blr } define double @cmp1(double %a, double %b, double %y, double %z) #0 { @@ -118,16 +152,23 @@ entry: ; CHECK: @cmp1 ; CHECK-NOT: fsel ; CHECK: blr +} -; CHECK-FM: @cmp1 -; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2 -; CHECK-FM: fsel 1, [[REG]], 3, 4 -; CHECK-FM: blr +define double @cmp1_finite(double %a, double %b, double %y, double %z) #0 { +entry: + %cmp = fcmp ninf nnan ult double %a, %b + %z.y = select i1 %cmp, double %z, double %y + ret double %z.y -; CHECK-FM-VSX: @cmp1 -; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2 -; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4 -; CHECK-FM-VSX: blr +; CHECK: @cmp1_finite +; CHECK: fsub [[REG:[0-9]+]], 1, 2 +; CHECK: fsel 1, [[REG]], 3, 4 +; CHECK: blr + +; CHECK-VSX: @cmp1_finite +; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2 +; CHECK-VSX: fsel 1, [[REG]], 3, 4 +; CHECK-VSX: blr } define double @cmp2(double %a, double %b, double %y, double %z) #0 { @@ -139,16 +180,23 @@ entry: ; CHECK: @cmp2 ; CHECK-NOT: fsel ; CHECK: blr +} -; CHECK-FM: @cmp2 -; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1 -; CHECK-FM: fsel 1, [[REG]], 4, 3 -; CHECK-FM: blr +define double @cmp2_finite(double %a, double %b, double %y, double %z) #0 { +entry: + %cmp = fcmp ninf nnan ogt double %a, %b + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z -; CHECK-FM-VSX: @cmp2 -; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1 -; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3 -; CHECK-FM-VSX: blr +; CHECK: @cmp2_finite +; CHECK: fsub [[REG:[0-9]+]], 2, 1 +; CHECK: fsel 1, [[REG]], 4, 3 +; CHECK: blr + +; CHECK-VSX: @cmp2_finite +; CHECK-VSX: xssubdp [[REG:[0-9]+]], 2, 1 +; CHECK-VSX: fsel 1, [[REG]], 4, 3 +; CHECK-VSX: blr } define double @cmp3(double %a, double %b, double %y, double %z) #0 { @@ -160,21 +208,27 @@ entry: ; CHECK: @cmp3 ; CHECK-NOT: fsel ; CHECK: blr +} -; CHECK-FM: @cmp3 -; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2 -; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4 -; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]] -; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4 -; CHECK-FM: blr +define double @cmp3_finite(double %a, double %b, double %y, double %z) #0 { +entry: + %cmp = fcmp ninf nnan oeq double %a, %b + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z -; CHECK-FM-VSX: @cmp3 -; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2 -; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4 -; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]] -; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4 -; CHECK-FM-VSX: blr -} +; CHECK: @cmp3_finite +; CHECK: fsub [[REG:[0-9]+]], 1, 2 +; CHECK: fsel [[REG2:[0-9]+]], [[REG]], 3, 4 +; CHECK: fneg [[REG3:[0-9]+]], [[REG]] +; CHECK: fsel 1, [[REG3]], [[REG2]], 4 +; CHECK: blr -attributes #0 = { nounwind readnone } +; CHECK-VSX: @cmp3_finite +; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2 +; CHECK-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4 +; CHECK-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]] +; CHECK-VSX: fsel 1, [[REG3]], [[REG2]], 4 +; CHECK-VSX: blr +} +attributes #0 = { nounwind readnone } \ No newline at end of file diff --git a/llvm/test/CodeGen/PowerPC/ifunc-prepare.ll b/llvm/test/CodeGen/PowerPC/ifunc-prepare.ll new file mode 100644 index 0000000000000..8a8031e9eb7f2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/ifunc-prepare.ll @@ -0,0 +1,32 @@ +; RUN: opt -ppc-prep-ifunc-aix -mtriple=powerpc64-ibm-aix-xcoff %s -S | FileCheck %s -DALIGN=8 +; RUN: opt -ppc-prep-ifunc-aix -mtriple=powerpc-ibm-aix-xcoff %s -S | FileCheck %s -DALIGN=4 + +; CHECK: @__update_foo = private global { ptr, ptr } { ptr @foo, ptr @foo.resolver }, section "__ifunc_sec", align [[ALIGN]] +; CHECK: @__update_bar = private global { ptr, ptr } { ptr @bar, ptr @bar.resolver }, section "__ifunc_sec", align [[ALIGN]] +; CHECK: @foo = ifunc i32 (...), ptr @foo.resolver, !implicit.ref ![[#UPDATE_FOO:]], !implicit.ref ![[#INIT_IFUNC:]] +; CHECK: @bar = ifunc void (i32, i1), ptr @bar.resolver, !implicit.ref ![[#UPDATE_BAR:]], !implicit.ref ![[#INIT_IFUNC]] +; CHECK: declare void @__init_ifuncs() +; CHECK: ![[#UPDATE_FOO]] = !{ptr @__update_foo} +; CHECK: ![[#INIT_IFUNC]] = !{ptr @__init_ifuncs} +; CHECK: ![[#UPDATE_BAR]] = !{ptr @__update_bar} + +@foo = ifunc i32 (...), ptr @foo.resolver +@bar = ifunc void (i32, i1), ptr @bar.resolver + +define hidden signext i32 @my_foo() { +entry: + ret i32 4 +} + +define internal ptr @foo.resolver() { +entry: + ret ptr @my_foo +} + +declare void @my_bar(i32, i1) + +define ptr @bar.resolver() { +entry: + ret ptr @my_bar +} + diff --git a/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir b/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir index 0cfeb944a5dbc..d32fad49b37a5 100644 --- a/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir +++ b/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir @@ -14,10 +14,10 @@ body: | %2:g8rc = RLDICR %1, 2, 61 %3:f8rc, %4:g8rc_and_g8rc_nox0 = LFSUX %0, killed %2 %5:f4rc = FRSP killed %3, implicit $rm - %22:vslrc = SUBREG_TO_REG 1, %5, %subreg.sub_64 + %22:vslrc = SUBREG_TO_REG %5, %subreg.sub_64 %7:g8rc = LI8 8 %8:vssrc = XFLOADf32 %4, killed %7 - %23:vslrc = SUBREG_TO_REG 1, %8, %subreg.sub_64 + %23:vslrc = SUBREG_TO_REG %8, %subreg.sub_64 %10:vsrc = XXPERMDI %23, %22, 0 %11:vrrc = XVCVDPSP killed %10, implicit $rm $v2 = COPY %11 @@ -44,10 +44,10 @@ body: | %2:g8rc = RLDICR %1, 2, 61 %3:f8rc, %4:g8rc_and_g8rc_nox0 = LFSUX %0, killed %2 %5:vssrc = XSRSP killed %3 - %22:vslrc = SUBREG_TO_REG 1, %5, %subreg.sub_64 + %22:vslrc = SUBREG_TO_REG %5, %subreg.sub_64 %7:g8rc = LI8 8 %8:vssrc = XFLOADf32 %4, killed %7 - %23:vslrc = SUBREG_TO_REG 1, %8, %subreg.sub_64 + %23:vslrc = SUBREG_TO_REG %8, %subreg.sub_64 %10:vsrc = XXPERMDI %23, %22, 0 %11:vrrc = XVCVDPSP killed %10, implicit $rm $v2 = COPY %11 diff --git a/llvm/test/CodeGen/PowerPC/milicode32.ll b/llvm/test/CodeGen/PowerPC/milicode32.ll index f569bc4d2668e..491f32ee65053 100644 --- a/llvm/test/CodeGen/PowerPC/milicode32.ll +++ b/llvm/test/CodeGen/PowerPC/milicode32.ll @@ -342,7 +342,7 @@ define signext i32 @test_strcmp(ptr noundef %s1, ptr noundef %s2) nounwind { ; CHECK-AIX-32-P9-NEXT: mflr r0 ; CHECK-AIX-32-P9-NEXT: stwu r1, -64(r1) ; CHECK-AIX-32-P9-NEXT: stw r0, 72(r1) -; CHECK-AIX-32-P9-NEXT: bl .strcmp[PR] +; CHECK-AIX-32-P9-NEXT: bl .___strcmp[PR] ; CHECK-AIX-32-P9-NEXT: nop ; CHECK-AIX-32-P9-NEXT: addi r1, r1, 64 ; CHECK-AIX-32-P9-NEXT: lwz r0, 8(r1) diff --git a/llvm/test/CodeGen/PowerPC/milicode64.ll b/llvm/test/CodeGen/PowerPC/milicode64.ll index e78577af3c2bf..151fe2c525381 100644 --- a/llvm/test/CodeGen/PowerPC/milicode64.ll +++ b/llvm/test/CodeGen/PowerPC/milicode64.ll @@ -439,7 +439,7 @@ entry: declare ptr @memccpy(ptr noundef, ptr noundef, i32 noundef signext, i64 noundef) -define signext i32 @test_strcmp(ptr noundef %s1, ptr noundef %s2) nounwind { +define i32 @test_strcmp(ptr noundef %s1, ptr noundef %s2) nounwind { ; CHECK-LE-P9-LABEL: test_strcmp: ; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9-NEXT: mflr r0 @@ -469,14 +469,14 @@ define signext i32 @test_strcmp(ptr noundef %s1, ptr noundef %s2) nounwind { ; CHECK-AIX-64-P9-NEXT: mflr r0 ; CHECK-AIX-64-P9-NEXT: stdu r1, -112(r1) ; CHECK-AIX-64-P9-NEXT: std r0, 128(r1) -; CHECK-AIX-64-P9-NEXT: bl .strcmp[PR] +; CHECK-AIX-64-P9-NEXT: bl .___strcmp64[PR] ; CHECK-AIX-64-P9-NEXT: nop ; CHECK-AIX-64-P9-NEXT: addi r1, r1, 112 ; CHECK-AIX-64-P9-NEXT: ld r0, 16(r1) ; CHECK-AIX-64-P9-NEXT: mtlr r0 ; CHECK-AIX-64-P9-NEXT: blr entry: - %call = call signext i32 @strcmp(ptr noundef %s1, ptr noundef %s2) + %call = call i32 @strcmp(ptr noundef %s1, ptr noundef %s2) ret i32 %call } diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll index 504216921110b..b8629f7f442b7 100644 --- a/llvm/test/CodeGen/PowerPC/recipest.ll +++ b/llvm/test/CodeGen/PowerPC/recipest.ll @@ -1300,5 +1300,5 @@ define fp128 @hoo5_safe(fp128 %a) #1 { } attributes #0 = { nounwind "reciprocal-estimates"="sqrtf:0,sqrtd:0" } -attributes #1 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #1 = { nounwind denormal_fpenv(preservesign) } attributes #2 = { nounwind readnone "target-features"="-crbits" } diff --git a/llvm/test/CodeGen/PowerPC/scalar-equal.ll b/llvm/test/CodeGen/PowerPC/scalar-equal.ll index c0b11b47236a9..de829b5d54dee 100644 --- a/llvm/test/CodeGen/PowerPC/scalar-equal.ll +++ b/llvm/test/CodeGen/PowerPC/scalar-equal.ll @@ -1,57 +1,31 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names \ -; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \ -; RUN: --enable-no-nans-fp-math --enable-no-infs-fp-math \ -; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ -; RUN: --check-prefix=FAST-P8 -; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names \ -; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \ -; RUN: --enable-no-nans-fp-math --enable-no-infs-fp-math \ -; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ -; RUN: --check-prefix=FAST-P9 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ -; RUN: --check-prefix=NO-FAST-P9 +; RUN: --check-prefix=P9 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ -; RUN: --check-prefix=NO-FAST-P8 +; RUN: --check-prefix=P8 define double @testoeq(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: testoeq: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: xsnegdp f0, f0 -; FAST-P8-NEXT: fsel f1, f0, f1, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: testoeq: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: xsnegdp f0, f0 -; FAST-P9-NEXT: fsel f1, f0, f1, f4 -; FAST-P9-NEXT: blr +; P9-LABEL: testoeq: +; P9: # %bb.0: # %entry +; P9-NEXT: xscmpudp cr0, f1, f2 +; P9-NEXT: beq cr0, .LBB0_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB0_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr ; -; NO-FAST-P9-LABEL: testoeq: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f2 -; NO-FAST-P9-NEXT: beq cr0, .LBB0_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB0_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: testoeq: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2 -; NO-FAST-P8-NEXT: beq cr0, .LBB0_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB0_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr +; P8-LABEL: testoeq: +; P8: # %bb.0: # %entry +; P8-NEXT: xscmpudp cr0, f1, f2 +; P8-NEXT: beq cr0, .LBB0_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB0_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr entry: %cmp = fcmp oeq double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -59,37 +33,21 @@ entry: } define double @testoeq_fast(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: testoeq_fast: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: xsnegdp f0, f0 -; FAST-P8-NEXT: fsel f1, f0, f1, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: testoeq_fast: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: xsnegdp f0, f0 -; FAST-P9-NEXT: fsel f1, f0, f1, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P9-LABEL: testoeq_fast: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P9-NEXT: xsnegdp f0, f0 -; NO-FAST-P9-NEXT: fsel f1, f0, f1, f4 -; NO-FAST-P9-NEXT: blr +; P9-LABEL: testoeq_fast: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubdp f0, f1, f2 +; P9-NEXT: fsel f1, f0, f3, f4 +; P9-NEXT: xsnegdp f0, f0 +; P9-NEXT: fsel f1, f0, f1, f4 +; P9-NEXT: blr ; -; NO-FAST-P8-LABEL: testoeq_fast: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P8-NEXT: xsnegdp f0, f0 -; NO-FAST-P8-NEXT: fsel f1, f0, f1, f4 -; NO-FAST-P8-NEXT: blr +; P8-LABEL: testoeq_fast: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubdp f0, f1, f2 +; P8-NEXT: fsel f1, f0, f3, f4 +; P8-NEXT: xsnegdp f0, f0 +; P8-NEXT: fsel f1, f0, f1, f4 +; P8-NEXT: blr entry: %cmp = fcmp nnan ninf nsz oeq double %a, %b %cond = select nnan ninf nsz i1 %cmp, double %c, double %d diff --git a/llvm/test/CodeGen/PowerPC/scalar_cmp.ll b/llvm/test/CodeGen/PowerPC/scalar_cmp.ll index 881d1f4c4093b..46351782b5dc2 100644 --- a/llvm/test/CodeGen/PowerPC/scalar_cmp.ll +++ b/llvm/test/CodeGen/PowerPC/scalar_cmp.ll @@ -1,58 +1,36 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names \ ; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \ -; RUN: --enable-no-nans-fp-math --enable-no-infs-fp-math \ +; RUN: --enable-no-nans-fp-math \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ -; RUN: --check-prefix=FAST-P8 +; RUN: --check-prefix=P8 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names \ ; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \ -; RUN: --enable-no-nans-fp-math --enable-no-infs-fp-math \ +; RUN: --enable-no-nans-fp-math \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ -; RUN: --check-prefix=FAST-P9 -; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \ -; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ -; RUN: --check-prefix=NO-FAST-P8 -; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \ -; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ -; RUN: --check-prefix=NO-FAST-P9 +; RUN: --check-prefix=P9 ; Test oeq define float @select_oeq_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_oeq_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f1, f2 -; FAST-P8-NEXT: xsnegdp f1, f0 -; FAST-P8-NEXT: fsel f0, f0, f3, f4 -; FAST-P8-NEXT: fsel f1, f1, f0, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_oeq_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f1, f2 -; FAST-P9-NEXT: xsnegdp f1, f0 -; FAST-P9-NEXT: fsel f0, f0, f3, f4 -; FAST-P9-NEXT: fsel f1, f1, f0, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_oeq_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: beq cr0, .LBB0_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB0_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_oeq_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: beq cr0, .LBB0_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB0_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_oeq_float: +; P8: # %bb.0: # %entry +; P8-NEXT: fcmpu cr0, f1, f2 +; P8-NEXT: beq cr0, .LBB0_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB0_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_oeq_float: +; P9: # %bb.0: # %entry +; P9-NEXT: fcmpu cr0, f1, f2 +; P9-NEXT: beq cr0, .LBB0_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB0_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp oeq float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -60,41 +38,25 @@ entry: } define float @select_oeq_float_nsz(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_oeq_float_nsz: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f2, f1 -; FAST-P8-NEXT: xssubsp f1, f1, f2 -; FAST-P8-NEXT: fsel f1, f1, f3, f4 -; FAST-P8-NEXT: fsel f1, f0, f1, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_oeq_float_nsz: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f2, f1 -; FAST-P9-NEXT: xssubsp f1, f1, f2 -; FAST-P9-NEXT: fsel f1, f1, f3, f4 -; FAST-P9-NEXT: fsel f1, f0, f1, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_oeq_float_nsz: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: beq cr0, .LBB1_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB1_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_oeq_float_nsz: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: beq cr0, .LBB1_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB1_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_oeq_float_nsz: +; P8: # %bb.0: # %entry +; P8-NEXT: fcmpu cr0, f1, f2 +; P8-NEXT: beq cr0, .LBB1_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB1_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_oeq_float_nsz: +; P9: # %bb.0: # %entry +; P9-NEXT: fcmpu cr0, f1, f2 +; P9-NEXT: beq cr0, .LBB1_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB1_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp nsz oeq float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -102,41 +64,25 @@ entry: } define double @select_oeq_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_oeq_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: xsnegdp f0, f0 -; FAST-P8-NEXT: fsel f1, f0, f1, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_oeq_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: xsnegdp f0, f0 -; FAST-P9-NEXT: fsel f1, f0, f1, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_oeq_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2 -; NO-FAST-P8-NEXT: beq cr0, .LBB2_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB2_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_oeq_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f2 -; NO-FAST-P9-NEXT: beq cr0, .LBB2_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB2_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_oeq_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xscmpudp cr0, f1, f2 +; P8-NEXT: beq cr0, .LBB2_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB2_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_oeq_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xscmpudp cr0, f1, f2 +; P9-NEXT: beq cr0, .LBB2_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB2_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp oeq double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -144,37 +90,21 @@ entry: } define float @select_fast_oeq_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_fast_oeq_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f2, f1 -; FAST-P8-NEXT: xssubsp f1, f1, f2 -; FAST-P8-NEXT: fsel f1, f1, f3, f4 -; FAST-P8-NEXT: fsel f1, f0, f1, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_oeq_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f2, f1 -; FAST-P9-NEXT: xssubsp f1, f1, f2 -; FAST-P9-NEXT: fsel f1, f1, f3, f4 -; FAST-P9-NEXT: fsel f1, f0, f1, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_oeq_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubsp f0, f2, f1 -; NO-FAST-P8-NEXT: xssubsp f1, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f1, f3, f4 -; NO-FAST-P8-NEXT: fsel f1, f0, f1, f4 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_oeq_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubsp f0, f2, f1 -; NO-FAST-P9-NEXT: xssubsp f1, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f1, f3, f4 -; NO-FAST-P9-NEXT: fsel f1, f0, f1, f4 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_oeq_float: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubsp f0, f2, f1 +; P8-NEXT: xssubsp f1, f1, f2 +; P8-NEXT: fsel f1, f1, f3, f4 +; P8-NEXT: fsel f1, f0, f1, f4 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_oeq_float: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubsp f0, f2, f1 +; P9-NEXT: xssubsp f1, f1, f2 +; P9-NEXT: fsel f1, f1, f3, f4 +; P9-NEXT: fsel f1, f0, f1, f4 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz oeq float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -182,37 +112,21 @@ entry: } define double @select_fast_oeq_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_fast_oeq_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: xsnegdp f0, f0 -; FAST-P8-NEXT: fsel f1, f0, f1, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_oeq_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: xsnegdp f0, f0 -; FAST-P9-NEXT: fsel f1, f0, f1, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_oeq_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P8-NEXT: xsnegdp f0, f0 -; NO-FAST-P8-NEXT: fsel f1, f0, f1, f4 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_oeq_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P9-NEXT: xsnegdp f0, f0 -; NO-FAST-P9-NEXT: fsel f1, f0, f1, f4 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_oeq_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubdp f0, f1, f2 +; P8-NEXT: fsel f1, f0, f3, f4 +; P8-NEXT: xsnegdp f0, f0 +; P8-NEXT: fsel f1, f0, f1, f4 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_oeq_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubdp f0, f1, f2 +; P9-NEXT: fsel f1, f0, f3, f4 +; P9-NEXT: xsnegdp f0, f0 +; P9-NEXT: fsel f1, f0, f1, f4 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz oeq double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -222,43 +136,25 @@ entry: ; Test one define float @select_one_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_one_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f1, f2 -; FAST-P8-NEXT: xsnegdp f1, f0 -; FAST-P8-NEXT: fsel f0, f0, f4, f3 -; FAST-P8-NEXT: fsel f1, f1, f0, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_one_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f1, f2 -; FAST-P9-NEXT: xsnegdp f1, f0 -; FAST-P9-NEXT: fsel f0, f0, f4, f3 -; FAST-P9-NEXT: fsel f1, f1, f0, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_one_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: crnor 4*cr5+lt, un, eq -; NO-FAST-P8-NEXT: bc 12, 4*cr5+lt, .LBB5_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB5_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_one_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: crnor 4*cr5+lt, un, eq -; NO-FAST-P9-NEXT: bc 12, 4*cr5+lt, .LBB5_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB5_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_one_float: +; P8: # %bb.0: # %entry +; P8-NEXT: fcmpu cr0, f1, f2 +; P8-NEXT: bne cr0, .LBB5_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB5_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_one_float: +; P9: # %bb.0: # %entry +; P9-NEXT: fcmpu cr0, f1, f2 +; P9-NEXT: bne cr0, .LBB5_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB5_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp one float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -266,43 +162,25 @@ entry: } define float @select_one_float_nsz(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_one_float_nsz: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f2, f1 -; FAST-P8-NEXT: xssubsp f1, f1, f2 -; FAST-P8-NEXT: fsel f1, f1, f4, f3 -; FAST-P8-NEXT: fsel f1, f0, f1, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_one_float_nsz: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f2, f1 -; FAST-P9-NEXT: xssubsp f1, f1, f2 -; FAST-P9-NEXT: fsel f1, f1, f4, f3 -; FAST-P9-NEXT: fsel f1, f0, f1, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_one_float_nsz: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: crnor 4*cr5+lt, un, eq -; NO-FAST-P8-NEXT: bc 12, 4*cr5+lt, .LBB6_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB6_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_one_float_nsz: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: crnor 4*cr5+lt, un, eq -; NO-FAST-P9-NEXT: bc 12, 4*cr5+lt, .LBB6_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB6_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_one_float_nsz: +; P8: # %bb.0: # %entry +; P8-NEXT: fcmpu cr0, f1, f2 +; P8-NEXT: bne cr0, .LBB6_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB6_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_one_float_nsz: +; P9: # %bb.0: # %entry +; P9-NEXT: fcmpu cr0, f1, f2 +; P9-NEXT: bne cr0, .LBB6_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB6_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp nsz one float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -310,43 +188,25 @@ entry: } define double @select_one_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_one_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: xsnegdp f0, f0 -; FAST-P8-NEXT: fsel f1, f0, f1, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_one_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: xsnegdp f0, f0 -; FAST-P9-NEXT: fsel f1, f0, f1, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_one_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: crnor 4*cr5+lt, un, eq -; NO-FAST-P8-NEXT: bc 12, 4*cr5+lt, .LBB7_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB7_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_one_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: crnor 4*cr5+lt, un, eq -; NO-FAST-P9-NEXT: bc 12, 4*cr5+lt, .LBB7_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB7_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_one_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xscmpudp cr0, f1, f2 +; P8-NEXT: bne cr0, .LBB7_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB7_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_one_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xscmpudp cr0, f1, f2 +; P9-NEXT: bne cr0, .LBB7_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB7_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp one double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -354,37 +214,21 @@ entry: } define float @select_fast_one_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_fast_one_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f2, f1 -; FAST-P8-NEXT: xssubsp f1, f1, f2 -; FAST-P8-NEXT: fsel f1, f1, f4, f3 -; FAST-P8-NEXT: fsel f1, f0, f1, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_one_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f2, f1 -; FAST-P9-NEXT: xssubsp f1, f1, f2 -; FAST-P9-NEXT: fsel f1, f1, f4, f3 -; FAST-P9-NEXT: fsel f1, f0, f1, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_one_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubsp f0, f2, f1 -; NO-FAST-P8-NEXT: xssubsp f1, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f1, f4, f3 -; NO-FAST-P8-NEXT: fsel f1, f0, f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_one_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubsp f0, f2, f1 -; NO-FAST-P9-NEXT: xssubsp f1, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f1, f4, f3 -; NO-FAST-P9-NEXT: fsel f1, f0, f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_one_float: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubsp f0, f2, f1 +; P8-NEXT: xssubsp f1, f1, f2 +; P8-NEXT: fsel f1, f1, f4, f3 +; P8-NEXT: fsel f1, f0, f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_one_float: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubsp f0, f2, f1 +; P9-NEXT: xssubsp f1, f1, f2 +; P9-NEXT: fsel f1, f1, f4, f3 +; P9-NEXT: fsel f1, f0, f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz one float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -392,37 +236,21 @@ entry: } define double @select_fast_one_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_fast_one_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: xsnegdp f0, f0 -; FAST-P8-NEXT: fsel f1, f0, f1, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_one_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: xsnegdp f0, f0 -; FAST-P9-NEXT: fsel f1, f0, f1, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_one_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P8-NEXT: xsnegdp f0, f0 -; NO-FAST-P8-NEXT: fsel f1, f0, f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_one_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P9-NEXT: xsnegdp f0, f0 -; NO-FAST-P9-NEXT: fsel f1, f0, f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_one_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubdp f0, f1, f2 +; P8-NEXT: fsel f1, f0, f4, f3 +; P8-NEXT: xsnegdp f0, f0 +; P8-NEXT: fsel f1, f0, f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_one_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubdp f0, f1, f2 +; P9-NEXT: fsel f1, f0, f4, f3 +; P9-NEXT: xsnegdp f0, f0 +; P9-NEXT: fsel f1, f0, f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz one double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -432,39 +260,25 @@ entry: ; Test oge define float @select_oge_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_oge_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_oge_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_oge_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: crnor 4*cr5+lt, un, lt -; NO-FAST-P8-NEXT: bc 12, 4*cr5+lt, .LBB10_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB10_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_oge_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: crnor 4*cr5+lt, un, lt -; NO-FAST-P9-NEXT: bc 12, 4*cr5+lt, .LBB10_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB10_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_oge_float: +; P8: # %bb.0: # %entry +; P8-NEXT: fcmpu cr0, f1, f2 +; P8-NEXT: bge cr0, .LBB10_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB10_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_oge_float: +; P9: # %bb.0: # %entry +; P9-NEXT: fcmpu cr0, f1, f2 +; P9-NEXT: bge cr0, .LBB10_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB10_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp oge float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -472,39 +286,25 @@ entry: } define double @select_oge_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_oge_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_oge_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_oge_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: crnor 4*cr5+lt, un, lt -; NO-FAST-P8-NEXT: bc 12, 4*cr5+lt, .LBB11_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB11_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_oge_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: crnor 4*cr5+lt, un, lt -; NO-FAST-P9-NEXT: bc 12, 4*cr5+lt, .LBB11_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB11_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_oge_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xscmpudp cr0, f1, f2 +; P8-NEXT: bge cr0, .LBB11_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB11_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_oge_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xscmpudp cr0, f1, f2 +; P9-NEXT: bge cr0, .LBB11_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB11_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp oge double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -512,29 +312,17 @@ entry: } define float @select_fast_oge_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_fast_oge_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_oge_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_oge_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubsp f0, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_oge_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubsp f0, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_oge_float: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubsp f0, f1, f2 +; P8-NEXT: fsel f1, f0, f3, f4 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_oge_float: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubsp f0, f1, f2 +; P9-NEXT: fsel f1, f0, f3, f4 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz oge float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -542,29 +330,17 @@ entry: } define double @select_fast_oge_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_fast_oge_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_oge_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_oge_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_oge_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_oge_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubdp f0, f1, f2 +; P8-NEXT: fsel f1, f0, f3, f4 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_oge_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubdp f0, f1, f2 +; P9-NEXT: fsel f1, f0, f3, f4 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz oge double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -574,37 +350,25 @@ entry: ; Test olt define float @select_olt_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_olt_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_olt_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_olt_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: blt cr0, .LBB14_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB14_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_olt_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: blt cr0, .LBB14_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB14_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_olt_float: +; P8: # %bb.0: # %entry +; P8-NEXT: fcmpu cr0, f1, f2 +; P8-NEXT: blt cr0, .LBB14_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB14_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_olt_float: +; P9: # %bb.0: # %entry +; P9-NEXT: fcmpu cr0, f1, f2 +; P9-NEXT: blt cr0, .LBB14_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB14_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp olt float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -612,37 +376,25 @@ entry: } define double @select_olt_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_olt_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_olt_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_olt_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2 -; NO-FAST-P8-NEXT: blt cr0, .LBB15_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB15_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_olt_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f2 -; NO-FAST-P9-NEXT: blt cr0, .LBB15_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB15_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_olt_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xscmpudp cr0, f1, f2 +; P8-NEXT: blt cr0, .LBB15_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB15_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_olt_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xscmpudp cr0, f1, f2 +; P9-NEXT: blt cr0, .LBB15_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB15_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp olt double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -650,29 +402,17 @@ entry: } define float @select_fast_olt_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_fast_olt_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_olt_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_olt_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubsp f0, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_olt_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubsp f0, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_olt_float: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubsp f0, f1, f2 +; P8-NEXT: fsel f1, f0, f4, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_olt_float: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubsp f0, f1, f2 +; P9-NEXT: fsel f1, f0, f4, f3 +; P9-NEXT: blr entry: %cmp = fcmp ninf nnan nsz olt float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -680,29 +420,17 @@ entry: } define double @select_fast_olt_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_fast_olt_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f1, f2 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_olt_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f1, f2 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_olt_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P8-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_olt_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubdp f0, f1, f2 -; NO-FAST-P9-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_olt_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubdp f0, f1, f2 +; P8-NEXT: fsel f1, f0, f4, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_olt_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubdp f0, f1, f2 +; P9-NEXT: fsel f1, f0, f4, f3 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz olt double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -712,37 +440,25 @@ entry: ; Test ogt define float @select_ogt_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_ogt_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f2, f1 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_ogt_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f2, f1 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_ogt_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: bgt cr0, .LBB18_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB18_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_ogt_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: bgt cr0, .LBB18_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB18_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_ogt_float: +; P8: # %bb.0: # %entry +; P8-NEXT: fcmpu cr0, f1, f2 +; P8-NEXT: bgt cr0, .LBB18_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB18_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_ogt_float: +; P9: # %bb.0: # %entry +; P9-NEXT: fcmpu cr0, f1, f2 +; P9-NEXT: bgt cr0, .LBB18_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB18_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp ogt float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -750,37 +466,25 @@ entry: } define double @select_ogt_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_ogt_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f2, f1 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_ogt_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f2, f1 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_ogt_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2 -; NO-FAST-P8-NEXT: bgt cr0, .LBB19_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB19_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_ogt_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f2 -; NO-FAST-P9-NEXT: bgt cr0, .LBB19_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB19_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_ogt_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xscmpudp cr0, f1, f2 +; P8-NEXT: bgt cr0, .LBB19_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB19_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_ogt_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xscmpudp cr0, f1, f2 +; P9-NEXT: bgt cr0, .LBB19_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB19_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp ogt double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -788,29 +492,17 @@ entry: } define float @select_fast_ogt_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_fast_ogt_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f2, f1 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_ogt_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f2, f1 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_ogt_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubsp f0, f2, f1 -; NO-FAST-P8-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_ogt_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubsp f0, f2, f1 -; NO-FAST-P9-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_ogt_float: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubsp f0, f2, f1 +; P8-NEXT: fsel f1, f0, f4, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_ogt_float: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubsp f0, f2, f1 +; P9-NEXT: fsel f1, f0, f4, f3 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz ogt float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -818,29 +510,17 @@ entry: } define double @select_fast_ogt_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_fast_ogt_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f2, f1 -; FAST-P8-NEXT: fsel f1, f0, f4, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_ogt_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f2, f1 -; FAST-P9-NEXT: fsel f1, f0, f4, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_ogt_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubdp f0, f2, f1 -; NO-FAST-P8-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_ogt_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubdp f0, f2, f1 -; NO-FAST-P9-NEXT: fsel f1, f0, f4, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_ogt_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubdp f0, f2, f1 +; P8-NEXT: fsel f1, f0, f4, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_ogt_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubdp f0, f2, f1 +; P9-NEXT: fsel f1, f0, f4, f3 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz ogt double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -850,39 +530,25 @@ entry: ; Test ole define float @select_ole_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_ole_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f2, f1 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_ole_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f2, f1 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_ole_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: crnor 4*cr5+lt, un, gt -; NO-FAST-P8-NEXT: bc 12, 4*cr5+lt, .LBB22_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB22_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_ole_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: crnor 4*cr5+lt, un, gt -; NO-FAST-P9-NEXT: bc 12, 4*cr5+lt, .LBB22_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB22_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_ole_float: +; P8: # %bb.0: # %entry +; P8-NEXT: fcmpu cr0, f1, f2 +; P8-NEXT: ble cr0, .LBB22_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB22_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_ole_float: +; P9: # %bb.0: # %entry +; P9-NEXT: fcmpu cr0, f1, f2 +; P9-NEXT: ble cr0, .LBB22_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB22_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp ole float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -890,39 +556,25 @@ entry: } define double @select_ole_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_ole_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f2, f1 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_ole_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f2, f1 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_ole_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P8-NEXT: crnor 4*cr5+lt, un, gt -; NO-FAST-P8-NEXT: bc 12, 4*cr5+lt, .LBB23_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f3, f4 -; NO-FAST-P8-NEXT: .LBB23_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_ole_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f2 -; NO-FAST-P9-NEXT: crnor 4*cr5+lt, un, gt -; NO-FAST-P9-NEXT: bc 12, 4*cr5+lt, .LBB23_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f3, f4 -; NO-FAST-P9-NEXT: .LBB23_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_ole_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xscmpudp cr0, f1, f2 +; P8-NEXT: ble cr0, .LBB23_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f4 +; P8-NEXT: .LBB23_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: select_ole_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xscmpudp cr0, f1, f2 +; P9-NEXT: ble cr0, .LBB23_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f4 +; P9-NEXT: .LBB23_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp ole double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -930,29 +582,17 @@ entry: } define float @select_fast_ole_float(float %a, float %b, float %c, float %d) { -; FAST-P8-LABEL: select_fast_ole_float: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubsp f0, f2, f1 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_ole_float: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubsp f0, f2, f1 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_ole_float: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubsp f0, f2, f1 -; NO-FAST-P8-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_ole_float: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubsp f0, f2, f1 -; NO-FAST-P9-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_ole_float: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubsp f0, f2, f1 +; P8-NEXT: fsel f1, f0, f3, f4 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_ole_float: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubsp f0, f2, f1 +; P9-NEXT: fsel f1, f0, f3, f4 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz ole float %a, %b %cond = select i1 %cmp, float %c, float %d @@ -960,29 +600,17 @@ entry: } define double @select_fast_ole_double(double %a, double %b, double %c, double %d) { -; FAST-P8-LABEL: select_fast_ole_double: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: xssubdp f0, f2, f1 -; FAST-P8-NEXT: fsel f1, f0, f3, f4 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: select_fast_ole_double: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: xssubdp f0, f2, f1 -; FAST-P9-NEXT: fsel f1, f0, f3, f4 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: select_fast_ole_double: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: xssubdp f0, f2, f1 -; NO-FAST-P8-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: select_fast_ole_double: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: xssubdp f0, f2, f1 -; NO-FAST-P9-NEXT: fsel f1, f0, f3, f4 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: select_fast_ole_double: +; P8: # %bb.0: # %entry +; P8-NEXT: xssubdp f0, f2, f1 +; P8-NEXT: fsel f1, f0, f3, f4 +; P8-NEXT: blr +; +; P9-LABEL: select_fast_ole_double: +; P9: # %bb.0: # %entry +; P9-NEXT: xssubdp f0, f2, f1 +; P9-NEXT: fsel f1, f0, f3, f4 +; P9-NEXT: blr entry: %cmp = fcmp nnan ninf nsz ole double %a, %b %cond = select i1 %cmp, double %c, double %d @@ -991,149 +619,161 @@ entry: ; Test RHS is 1.000000e+00 define double @onecmp1(double %a, double %y, double %z) { -; FAST-P8-LABEL: onecmp1: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: vspltisw v2, -1 -; FAST-P8-NEXT: xvcvsxwdp vs0, vs34 -; FAST-P8-NEXT: xsadddp f0, f1, f0 -; FAST-P8-NEXT: fsel f1, f0, f2, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: onecmp1: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: vspltisw v2, -1 -; FAST-P9-NEXT: xvcvsxwdp vs0, vs34 -; FAST-P9-NEXT: xsadddp f0, f1, f0 -; FAST-P9-NEXT: fsel f1, f0, f2, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: onecmp1: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: vspltisw v2, 1 -; NO-FAST-P8-NEXT: xvcvsxwdp vs0, vs34 -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f0 -; NO-FAST-P8-NEXT: bc 12, lt, .LBB26_3 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fcmpu cr0, f1, f1 -; NO-FAST-P8-NEXT: bc 12, un, .LBB26_3 -; NO-FAST-P8-NEXT: # %bb.2: # %entry -; NO-FAST-P8-NEXT: fmr f3, f2 -; NO-FAST-P8-NEXT: .LBB26_3: # %entry -; NO-FAST-P8-NEXT: fmr f1, f3 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: onecmp1: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: vspltisw v2, 1 -; NO-FAST-P9-NEXT: xvcvsxwdp vs0, vs34 -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f0 -; NO-FAST-P9-NEXT: bc 12, lt, .LBB26_3 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fcmpu cr0, f1, f1 -; NO-FAST-P9-NEXT: bc 12, un, .LBB26_3 -; NO-FAST-P9-NEXT: # %bb.2: # %entry -; NO-FAST-P9-NEXT: fmr f3, f2 -; NO-FAST-P9-NEXT: .LBB26_3: # %entry -; NO-FAST-P9-NEXT: fmr f1, f3 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: onecmp1: +; P8: # %bb.0: # %entry +; P8-NEXT: vspltisw v2, 1 +; P8-NEXT: xvcvsxwdp vs0, vs34 +; P8-NEXT: xscmpudp cr0, f1, f0 +; P8-NEXT: blt cr0, .LBB26_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f3, f2 +; P8-NEXT: .LBB26_2: # %entry +; P8-NEXT: fmr f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: onecmp1: +; P9: # %bb.0: # %entry +; P9-NEXT: vspltisw v2, 1 +; P9-NEXT: xvcvsxwdp vs0, vs34 +; P9-NEXT: xscmpudp cr0, f1, f0 +; P9-NEXT: blt cr0, .LBB26_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f3, f2 +; P9-NEXT: .LBB26_2: # %entry +; P9-NEXT: fmr f1, f3 +; P9-NEXT: blr entry: %cmp = fcmp ult double %a, 1.000000e+00 %z.y = select i1 %cmp, double %z, double %y ret double %z.y } +define double @onecmp1_fast(double %a, double %y, double %z) { +; P8-LABEL: onecmp1_fast: +; P8: # %bb.0: # %entry +; P8-NEXT: vspltisw v2, -1 +; P8-NEXT: xvcvsxwdp vs0, vs34 +; P8-NEXT: xsadddp f0, f1, f0 +; P8-NEXT: fsel f1, f0, f2, f3 +; P8-NEXT: blr +; +; P9-LABEL: onecmp1_fast: +; P9: # %bb.0: # %entry +; P9-NEXT: vspltisw v2, -1 +; P9-NEXT: xvcvsxwdp vs0, vs34 +; P9-NEXT: xsadddp f0, f1, f0 +; P9-NEXT: fsel f1, f0, f2, f3 +; P9-NEXT: blr +entry: + %cmp = fcmp nnan ninf nsz ult double %a, 1.000000e+00 + %z.y = select i1 %cmp, double %z, double %y + ret double %z.y +} + define double @onecmp2(double %a, double %y, double %z) { -; FAST-P8-LABEL: onecmp2: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: vspltisw v2, 1 -; FAST-P8-NEXT: xvcvsxwdp vs0, vs34 -; FAST-P8-NEXT: xssubdp f0, f0, f1 -; FAST-P8-NEXT: fsel f1, f0, f3, f2 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: onecmp2: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: vspltisw v2, 1 -; FAST-P9-NEXT: xvcvsxwdp vs0, vs34 -; FAST-P9-NEXT: xssubdp f0, f0, f1 -; FAST-P9-NEXT: fsel f1, f0, f3, f2 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: onecmp2: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: vspltisw v2, 1 -; NO-FAST-P8-NEXT: xvcvsxwdp vs0, vs34 -; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f0 -; NO-FAST-P8-NEXT: bgt cr0, .LBB27_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f2, f3 -; NO-FAST-P8-NEXT: .LBB27_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f2 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: onecmp2: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: vspltisw v2, 1 -; NO-FAST-P9-NEXT: xvcvsxwdp vs0, vs34 -; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f0 -; NO-FAST-P9-NEXT: bgt cr0, .LBB27_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f2, f3 -; NO-FAST-P9-NEXT: .LBB27_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f2 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: onecmp2: +; P8: # %bb.0: # %entry +; P8-NEXT: vspltisw v2, 1 +; P8-NEXT: xvcvsxwdp vs0, vs34 +; P8-NEXT: xscmpudp cr0, f1, f0 +; P8-NEXT: bgt cr0, .LBB28_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f2, f3 +; P8-NEXT: .LBB28_2: # %entry +; P8-NEXT: fmr f1, f2 +; P8-NEXT: blr +; +; P9-LABEL: onecmp2: +; P9: # %bb.0: # %entry +; P9-NEXT: vspltisw v2, 1 +; P9-NEXT: xvcvsxwdp vs0, vs34 +; P9-NEXT: xscmpudp cr0, f1, f0 +; P9-NEXT: bgt cr0, .LBB28_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f2, f3 +; P9-NEXT: .LBB28_2: # %entry +; P9-NEXT: fmr f1, f2 +; P9-NEXT: blr entry: %cmp = fcmp ogt double %a, 1.000000e+00 %y.z = select i1 %cmp, double %y, double %z ret double %y.z } +define double @onecmp2_fast(double %a, double %y, double %z) { +; P8-LABEL: onecmp2_fast: +; P8: # %bb.0: # %entry +; P8-NEXT: vspltisw v2, 1 +; P8-NEXT: xvcvsxwdp vs0, vs34 +; P8-NEXT: xssubdp f0, f0, f1 +; P8-NEXT: fsel f1, f0, f3, f2 +; P8-NEXT: blr +; +; P9-LABEL: onecmp2_fast: +; P9: # %bb.0: # %entry +; P9-NEXT: vspltisw v2, 1 +; P9-NEXT: xvcvsxwdp vs0, vs34 +; P9-NEXT: xssubdp f0, f0, f1 +; P9-NEXT: fsel f1, f0, f3, f2 +; P9-NEXT: blr +entry: + %cmp = fcmp nnan ninf nsz ogt double %a, 1.000000e+00 + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z +} + define double @onecmp3(double %a, double %y, double %z) { -; FAST-P8-LABEL: onecmp3: -; FAST-P8: # %bb.0: # %entry -; FAST-P8-NEXT: vspltisw v2, -1 -; FAST-P8-NEXT: xvcvsxwdp vs0, vs34 -; FAST-P8-NEXT: xsadddp f0, f1, f0 -; FAST-P8-NEXT: fsel f1, f0, f2, f3 -; FAST-P8-NEXT: xsnegdp f0, f0 -; FAST-P8-NEXT: fsel f1, f0, f1, f3 -; FAST-P8-NEXT: blr -; -; FAST-P9-LABEL: onecmp3: -; FAST-P9: # %bb.0: # %entry -; FAST-P9-NEXT: vspltisw v2, -1 -; FAST-P9-NEXT: xvcvsxwdp vs0, vs34 -; FAST-P9-NEXT: xsadddp f0, f1, f0 -; FAST-P9-NEXT: fsel f1, f0, f2, f3 -; FAST-P9-NEXT: xsnegdp f0, f0 -; FAST-P9-NEXT: fsel f1, f0, f1, f3 -; FAST-P9-NEXT: blr -; -; NO-FAST-P8-LABEL: onecmp3: -; NO-FAST-P8: # %bb.0: # %entry -; NO-FAST-P8-NEXT: vspltisw v2, 1 -; NO-FAST-P8-NEXT: xvcvsxwdp vs0, vs34 -; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f0 -; NO-FAST-P8-NEXT: beq cr0, .LBB28_2 -; NO-FAST-P8-NEXT: # %bb.1: # %entry -; NO-FAST-P8-NEXT: fmr f2, f3 -; NO-FAST-P8-NEXT: .LBB28_2: # %entry -; NO-FAST-P8-NEXT: fmr f1, f2 -; NO-FAST-P8-NEXT: blr -; -; NO-FAST-P9-LABEL: onecmp3: -; NO-FAST-P9: # %bb.0: # %entry -; NO-FAST-P9-NEXT: vspltisw v2, 1 -; NO-FAST-P9-NEXT: xvcvsxwdp vs0, vs34 -; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f0 -; NO-FAST-P9-NEXT: beq cr0, .LBB28_2 -; NO-FAST-P9-NEXT: # %bb.1: # %entry -; NO-FAST-P9-NEXT: fmr f2, f3 -; NO-FAST-P9-NEXT: .LBB28_2: # %entry -; NO-FAST-P9-NEXT: fmr f1, f2 -; NO-FAST-P9-NEXT: blr +; P8-LABEL: onecmp3: +; P8: # %bb.0: # %entry +; P8-NEXT: vspltisw v2, 1 +; P8-NEXT: xvcvsxwdp vs0, vs34 +; P8-NEXT: xscmpudp cr0, f1, f0 +; P8-NEXT: beq cr0, .LBB30_2 +; P8-NEXT: # %bb.1: # %entry +; P8-NEXT: fmr f2, f3 +; P8-NEXT: .LBB30_2: # %entry +; P8-NEXT: fmr f1, f2 +; P8-NEXT: blr +; +; P9-LABEL: onecmp3: +; P9: # %bb.0: # %entry +; P9-NEXT: vspltisw v2, 1 +; P9-NEXT: xvcvsxwdp vs0, vs34 +; P9-NEXT: xscmpudp cr0, f1, f0 +; P9-NEXT: beq cr0, .LBB30_2 +; P9-NEXT: # %bb.1: # %entry +; P9-NEXT: fmr f2, f3 +; P9-NEXT: .LBB30_2: # %entry +; P9-NEXT: fmr f1, f2 +; P9-NEXT: blr entry: %cmp = fcmp oeq double %a, 1.000000e+00 %y.z = select i1 %cmp, double %y, double %z ret double %y.z } + +define double @onecmp3_fast(double %a, double %y, double %z) { +; P8-LABEL: onecmp3_fast: +; P8: # %bb.0: # %entry +; P8-NEXT: vspltisw v2, -1 +; P8-NEXT: xvcvsxwdp vs0, vs34 +; P8-NEXT: xsadddp f0, f1, f0 +; P8-NEXT: fsel f1, f0, f2, f3 +; P8-NEXT: xsnegdp f0, f0 +; P8-NEXT: fsel f1, f0, f1, f3 +; P8-NEXT: blr +; +; P9-LABEL: onecmp3_fast: +; P9: # %bb.0: # %entry +; P9-NEXT: vspltisw v2, -1 +; P9-NEXT: xvcvsxwdp vs0, vs34 +; P9-NEXT: xsadddp f0, f1, f0 +; P9-NEXT: fsel f1, f0, f2, f3 +; P9-NEXT: xsnegdp f0, f0 +; P9-NEXT: fsel f1, f0, f1, f3 +; P9-NEXT: blr +entry: + %cmp = fcmp nnan ninf nsz oeq double %a, 1.000000e+00 + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z +} diff --git a/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir b/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir index 31407e0d44cfb..df47ff9b3a19d 100644 --- a/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir +++ b/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir @@ -26,7 +26,7 @@ body: | %0:g8rc_and_g8rc_nox0 = COPY $x3 %1:f8rc, %2:g8rc_and_g8rc_nox0 = LFSUX %0, %0 %3:f4rc = FRSP killed %1, implicit $rm - %4:vslrc = SUBREG_TO_REG 1, %3, %subreg.sub_64 + %4:vslrc = SUBREG_TO_REG %3, %subreg.sub_64 %5:vrrc = XVCVDPSP killed %4, implicit $rm $v2 = COPY %5 BLR8 implicit $lr8, implicit $rm, implicit $v2 diff --git a/llvm/test/CodeGen/PowerPC/xxinsertw.ll b/llvm/test/CodeGen/PowerPC/xxinsertw.ll index f944b5a175be4..205e982be05b4 100644 --- a/llvm/test/CodeGen/PowerPC/xxinsertw.ll +++ b/llvm/test/CodeGen/PowerPC/xxinsertw.ll @@ -13,16 +13,16 @@ define <4 x i1> @foo(i1 %c1, i1 %c2, i1 %c3) { ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc = COPY $x3 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]].sub_32 ; CHECK-NEXT: [[MTVSRWZ:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY3]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ]], %subreg.sub_64 + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vrrc = SUBREG_TO_REG killed [[MTVSRWZ]], %subreg.sub_64 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]].sub_32 ; CHECK-NEXT: [[MTVSRWZ1:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY4]] - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ1]], %subreg.sub_64 + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vrrc = SUBREG_TO_REG killed [[MTVSRWZ1]], %subreg.sub_64 ; CHECK-NEXT: [[VMRGOW:%[0-9]+]]:vrrc = VMRGOW killed [[SUBREG_TO_REG1]], killed [[SUBREG_TO_REG]] ; CHECK-NEXT: [[LDtocCPT:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocCPT %const.0, $x2 :: (load (s64) from got) ; CHECK-NEXT: [[LXV:%[0-9]+]]:vsrc = LXV 0, killed [[LDtocCPT]] :: (load (s128) from constant-pool) ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32 ; CHECK-NEXT: [[MTVSRWZ2:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY5]] - ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG 1, killed [[MTVSRWZ2]], %subreg.sub_64 + ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG killed [[MTVSRWZ2]], %subreg.sub_64 ; CHECK-NEXT: [[XXPERM:%[0-9]+]]:vsrc = XXPERM killed [[VMRGOW]], [[SUBREG_TO_REG2]], killed [[LXV]] ; CHECK-NEXT: [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[XXPERM]], [[XXPERM]], 8 ; CHECK-NEXT: $v2 = COPY [[XXINSERTW]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir index 5b493f6844c01..e8af68f493770 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir @@ -16,7 +16,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_MF8_:%[0-9]+]]:vr = PseudoVADD_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_MF8_:%[0-9]+]]:vr = PseudoVADD_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF8_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -26,7 +26,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_MF8_:%[0-9]+]]:vr = PseudoVADD_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_MF8_:%[0-9]+]]:vr = PseudoVADD_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF8_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -51,7 +51,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF4_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -61,7 +61,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF4_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -86,7 +86,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -96,7 +96,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -121,7 +121,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -131,7 +131,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -156,7 +156,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -166,7 +166,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8m2 @@ -191,7 +191,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -201,7 +201,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m4 @@ -226,7 +226,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -236,7 +236,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m8 @@ -261,7 +261,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF4_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -271,7 +271,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_MF4_:%[0-9]+]]:vr = PseudoVADD_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF4_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -296,7 +296,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -306,7 +306,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -331,7 +331,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -341,7 +341,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -366,7 +366,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -376,7 +376,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8m2 @@ -401,7 +401,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -411,7 +411,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m4 @@ -436,7 +436,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -446,7 +446,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m8 @@ -471,7 +471,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -481,7 +481,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -506,7 +506,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -516,7 +516,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -541,7 +541,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -551,7 +551,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8m2 @@ -576,7 +576,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -586,7 +586,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m4 @@ -611,7 +611,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -621,7 +621,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m8 @@ -646,7 +646,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -656,7 +656,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -681,7 +681,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -691,7 +691,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVADD_VV_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8m2 @@ -716,7 +716,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -726,7 +726,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M4_:%[0-9]+]]:vrm4 = PseudoVADD_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVADD_VV_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m4 @@ -751,7 +751,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -761,7 +761,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m8 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir index 40fbd90f3aef5..c1adfecb32859 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/anyext.mir @@ -18,7 +18,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -27,7 +27,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -50,7 +50,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -59,7 +59,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -82,7 +82,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -91,7 +91,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -114,7 +114,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -123,7 +123,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -146,7 +146,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -155,7 +155,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -178,7 +178,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -187,7 +187,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -210,7 +210,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -219,7 +219,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -242,7 +242,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -251,7 +251,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -274,7 +274,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -283,7 +283,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -306,7 +306,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -315,7 +315,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -338,7 +338,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -347,7 +347,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -370,7 +370,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -379,7 +379,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8 @@ -402,7 +402,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -411,7 +411,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -434,7 +434,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -443,7 +443,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m2 @@ -466,7 +466,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -475,7 +475,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 @@ -498,7 +498,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -507,7 +507,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -530,7 +530,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -539,7 +539,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -562,7 +562,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -571,7 +571,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -594,7 +594,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -603,7 +603,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -626,7 +626,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -635,7 +635,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -658,7 +658,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -667,7 +667,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -690,7 +690,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -699,7 +699,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -722,7 +722,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -731,7 +731,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m2 @@ -754,7 +754,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -763,7 +763,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 @@ -786,7 +786,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -795,7 +795,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -818,7 +818,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -827,7 +827,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -850,7 +850,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -859,7 +859,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -882,7 +882,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -891,7 +891,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir index df0d48aac9255..b6d83613d3362 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/icmp.mir @@ -13,13 +13,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv1i8 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv1i8 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -37,13 +37,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv2i8 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv2i8 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -61,13 +61,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv4i8 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv4i8 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -85,13 +85,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv8i8 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv8i8 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -109,13 +109,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv16i8 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv16i8 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -133,13 +133,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv32i8 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv32i8 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -157,13 +157,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv64i8 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv64i8 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -181,13 +181,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv1i16 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv1i16 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -205,13 +205,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv2i16 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv2i16 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -229,13 +229,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv4i16 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv4i16 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -253,13 +253,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv8i16 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv8i16 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -277,13 +277,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv16i16 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv16i16 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -301,13 +301,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv32i16 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv32i16 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -325,13 +325,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv1i32 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv1i32 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -349,13 +349,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv2i32 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv2i32 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -373,13 +373,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv4i32 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv4i32 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -397,13 +397,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv8i32 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv8i32 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -421,13 +421,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv16i32 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv16i32 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -445,13 +445,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv1i64 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv1i64 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -469,13 +469,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv2i64 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv2i64 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -493,13 +493,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv4i64 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv4i64 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -517,13 +517,13 @@ body: | bb.0.entry: ; RV32I-LABEL: name: icmp_nxv8i64 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; ; RV64I-LABEL: name: icmp_nxv8i64 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir index 7610ebe7ed026..95c56c306c1ed 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv32.mir @@ -11,7 +11,7 @@ body: | bb.1: ; CHECK-LABEL: name: negative_vl ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2 - ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]], 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]] /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 -2 @@ -31,7 +31,7 @@ body: | ; CHECK: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 - ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]], 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]] /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = COPY $x10 @@ -48,7 +48,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: nonzero_vl - ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 1 @@ -65,7 +65,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: zero_vl - ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 0 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir index de78ceb2f5e13..78b7439df132e 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/render-vlop-rv64.mir @@ -11,7 +11,7 @@ body: | bb.1: ; CHECK-LABEL: name: negative_vl ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -2 - ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]], 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]] /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 -2 @@ -31,7 +31,7 @@ body: | ; CHECK: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 - ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]], 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]] /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = COPY $x10 @@ -48,7 +48,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: nonzero_vl - ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 1 @@ -65,7 +65,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: zero_vl - ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 0 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir index ada76a43639d7..35e89624ede27 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir @@ -13,7 +13,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -21,7 +21,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -42,7 +42,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -50,7 +50,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -71,7 +71,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -79,7 +79,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 3 /* e8 */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = G_IMPLICIT_DEF @@ -100,7 +100,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -108,7 +108,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -129,7 +129,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -137,7 +137,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -158,7 +158,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -166,7 +166,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 4 /* e16 */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = G_IMPLICIT_DEF @@ -187,7 +187,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -195,7 +195,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = G_IMPLICIT_DEF @@ -216,7 +216,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -224,7 +224,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = G_IMPLICIT_DEF @@ -245,7 +245,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -253,7 +253,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = G_IMPLICIT_DEF @@ -274,7 +274,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -282,7 +282,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = G_IMPLICIT_DEF @@ -303,7 +303,7 @@ body: | ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */ + ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -311,7 +311,7 @@ body: | ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */ + ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1 /* vl=VLMAX */, 6 /* e64 */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = G_IMPLICIT_DEF diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir index a52e7203761ab..b5b22ecdae1b0 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sext.mir @@ -16,7 +16,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -25,7 +25,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -48,7 +48,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -57,7 +57,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -80,7 +80,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -89,7 +89,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -112,7 +112,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -121,7 +121,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -144,7 +144,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -153,7 +153,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -176,7 +176,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -185,7 +185,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -208,7 +208,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -217,7 +217,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -240,7 +240,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -249,7 +249,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -272,7 +272,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -281,7 +281,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -304,7 +304,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -313,7 +313,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -336,7 +336,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -345,7 +345,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -368,7 +368,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -377,7 +377,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8 @@ -400,7 +400,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -409,7 +409,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -432,7 +432,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -441,7 +441,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m2 @@ -464,7 +464,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -473,7 +473,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 @@ -496,7 +496,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -505,7 +505,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -528,7 +528,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -537,7 +537,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -560,7 +560,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -569,7 +569,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -592,7 +592,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -601,7 +601,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -624,7 +624,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -633,7 +633,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -656,7 +656,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -665,7 +665,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -688,7 +688,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -697,7 +697,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -720,7 +720,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -729,7 +729,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m2 @@ -752,7 +752,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -761,7 +761,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 @@ -784,7 +784,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -793,7 +793,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVSEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -816,7 +816,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -825,7 +825,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVSEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -848,7 +848,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -857,7 +857,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVSEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -880,7 +880,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -889,7 +889,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVSEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir index 9f35ba9ef6c07..5aa0654bec71b 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir @@ -16,7 +16,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_MF8_:%[0-9]+]]:vr = PseudoVSUB_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_MF8_:%[0-9]+]]:vr = PseudoVSUB_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF8_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -26,7 +26,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_MF8_:%[0-9]+]]:vr = PseudoVSUB_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_MF8_:%[0-9]+]]:vr = PseudoVSUB_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF8_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -51,7 +51,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -61,7 +61,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -86,7 +86,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -96,7 +96,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -121,7 +121,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -131,7 +131,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -156,7 +156,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -166,7 +166,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8m2 @@ -191,7 +191,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -201,7 +201,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m4 @@ -226,7 +226,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -236,7 +236,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m8 @@ -261,7 +261,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -271,7 +271,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -296,7 +296,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -306,7 +306,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -331,7 +331,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -341,7 +341,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -366,7 +366,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -376,7 +376,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8m2 @@ -401,7 +401,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -411,7 +411,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m4 @@ -436,7 +436,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -446,7 +446,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m8 @@ -471,7 +471,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -481,7 +481,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -506,7 +506,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -516,7 +516,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -541,7 +541,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -551,7 +551,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8m2 @@ -576,7 +576,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -586,7 +586,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m4 @@ -611,7 +611,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -621,7 +621,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m8 @@ -646,7 +646,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -656,7 +656,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]] ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -681,7 +681,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -691,7 +691,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]] ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8m2 @@ -716,7 +716,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -726,7 +726,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]] ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m4 @@ -751,7 +751,7 @@ body: | ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -761,7 +761,7 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]] ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m8 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir index ab91b3d80bd9b..9e91d22efdc03 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv32.mir @@ -10,7 +10,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv1i1 - ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 -1 @@ -27,7 +27,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv2i1 - ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 -1 @@ -44,7 +44,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv4i1 - ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 -1 @@ -61,7 +61,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv8i1 - ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 -1 @@ -78,7 +78,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv16i1 - ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 -1 @@ -95,7 +95,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv32i1 - ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 -1 @@ -112,7 +112,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv64i1 - ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s32) = G_CONSTANT i32 -1 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir index 403a5f6a14ac9..80da9e6a655e7 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/vmclr-rv64.mir @@ -10,7 +10,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv1i1 - ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 -1 @@ -27,7 +27,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv2i1 - ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 -1 @@ -44,7 +44,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv4i1 - ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 -1 @@ -61,7 +61,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv8i1 - ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 -1 @@ -78,7 +78,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv16i1 - ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 -1 @@ -95,7 +95,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv32i1 - ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 -1 @@ -112,7 +112,7 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: splat_zero_nxv64i1 - ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1 /* vl=VLMAX */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:gprb(s64) = G_CONSTANT i64 -1 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir index ad151b4d9c7fe..5e4218df04398 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/zext.mir @@ -16,7 +16,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -25,7 +25,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -48,7 +48,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -57,7 +57,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -80,7 +80,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -89,7 +89,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -112,7 +112,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -121,7 +121,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -144,7 +144,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -153,7 +153,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -176,7 +176,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -185,7 +185,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -208,7 +208,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -217,7 +217,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -240,7 +240,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -249,7 +249,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -272,7 +272,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -281,7 +281,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -304,7 +304,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -313,7 +313,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -336,7 +336,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -345,7 +345,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -368,7 +368,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -377,7 +377,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8 @@ -400,7 +400,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -409,7 +409,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -432,7 +432,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -441,7 +441,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m2 @@ -464,7 +464,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -473,7 +473,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 4 /* e16 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 @@ -496,7 +496,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -505,7 +505,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -528,7 +528,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -537,7 +537,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -560,7 +560,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -569,7 +569,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -592,7 +592,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -601,7 +601,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -624,7 +624,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -633,7 +633,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -656,7 +656,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -665,7 +665,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8 @@ -688,7 +688,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -697,7 +697,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -720,7 +720,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -729,7 +729,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m2 @@ -752,7 +752,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -761,7 +761,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 @@ -784,7 +784,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8 ; @@ -793,7 +793,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8 %0:vrb() = COPY $v8 @@ -816,7 +816,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m2 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m2 ; @@ -825,7 +825,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m2 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m2 %0:vrb() = COPY $v8 @@ -848,7 +848,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m4 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m4 ; @@ -857,7 +857,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m4 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m4 %0:vrb() = COPY $v8m2 @@ -880,7 +880,7 @@ body: | ; RV32I-NEXT: {{ $}} ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV32I-NEXT: $v8m8 = COPY %1 ; RV32I-NEXT: PseudoRET implicit $v8m8 ; @@ -889,7 +889,7 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF - ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */ + ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; RV64I-NEXT: $v8m8 = COPY %1 ; RV64I-NEXT: PseudoRET implicit $v8m8 %0:vrb() = COPY $v8m4 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/alloca.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/alloca.ll new file mode 100644 index 0000000000000..127ba6b804864 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/alloca.ll @@ -0,0 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel %s -o - -stop-after=irtranslator | FileCheck %s + +; Test that single scalable vector alloca works and store +define void @test_single_scalable_alloca() { + ; CHECK-LABEL: name: test_single_scalable_alloca + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.local0 + ; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX]](p0) :: (volatile store (s64) into %ir.local0) + ; CHECK-NEXT: PseudoRET + %local0 = alloca + store volatile i64 1, ptr %local0 + ret void +} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll deleted file mode 100644 index 8e43e044b7ee5..0000000000000 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/fallback.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc -mtriple=riscv64 -mattr='+v' -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err -; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out -; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err - -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to translate instruction: alloca: -; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_alloca -define void @scalable_alloca() #1 { - %local0 = alloca - load volatile , ptr %local0 - ret void -} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32p.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32p.ll index 3f403fd8cb9e5..5708077fcefb1 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32p.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32p.ll @@ -139,3 +139,88 @@ define i64 @cls_i64_2(i64 %x) { %e = call i64 @llvm.ctlz.i64(i64 %d, i1 true) ret i64 %e } + +; The result is in the range [1-31], so we don't need an andi after the cls. +define i32 @cls_i32_knownbits(i32 %x) { +; CHECK-LABEL: cls_i32_knownbits: +; CHECK: # %bb.0: +; CHECK-NEXT: cls a0, a0 +; CHECK-NEXT: ret + %a = ashr i32 %x, 31 + %b = xor i32 %x, %a + %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) + %d = sub i32 %c, 1 + %e = and i32 %d, 31 + ret i32 %e +} + +; There are at least 16 redundant sign bits so we don't need an ori after the clsw. +define i32 @cls_i32_knownbits_2(i16 signext %x) { +; CHECK-LABEL: cls_i32_knownbits_2: +; CHECK: # %bb.0: +; CHECK-NEXT: cls a0, a0 +; CHECK-NEXT: ret + %sext = sext i16 %x to i32 + %a = ashr i32 %sext, 31 + %b = xor i32 %sext, %a + %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) + %d = sub i32 %c, 1 + %e = or i32 %d, 16 + ret i32 %e +} + +; There are at least 24 redundant sign bits so we don't need an ori after the clsw. +define i32 @cls_i32_knownbits_3(i8 signext %x) { +; CHECK-LABEL: cls_i32_knownbits_3: +; CHECK: # %bb.0: +; CHECK-NEXT: cls a0, a0 +; CHECK-NEXT: ret + %sext = sext i8 %x to i32 + %a = ashr i32 %sext, 31 + %b = xor i32 %sext, %a + %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) + %d = sub i32 %c, 1 + %e = or i32 %d, 24 + ret i32 %e +} + +; Negative test. We only know there is at least 1 redundant sign bit. We can't +; remove the ori. +define i32 @cls_i32_knownbits_4(i32 signext %x) { +; CHECK-LABEL: cls_i32_knownbits_4: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 1 +; CHECK-NEXT: srai a0, a0, 1 +; CHECK-NEXT: cls a0, a0 +; CHECK-NEXT: ori a0, a0, 1 +; CHECK-NEXT: ret + %shl = shl i32 %x, 1 + %ashr = ashr i32 %shl, 1 + %a = ashr i32 %ashr, 31 + %b = xor i32 %ashr, %a + %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) + %d = sub i32 %c, 1 + %e = or i32 %d, 1 + ret i32 %e + } + +; Negative test. Check that the number of sign bits is not +; overestimated. If it is, the ori disappears. +define i32 @cls_i32_knownbits_no_overestimate(i32 signext %x) { +; CHECK-LABEL: cls_i32_knownbits_no_overestimate: +; CHECK: # %bb.0: +; CHECK-NEXT: srai a1, a0, 15 +; CHECK-NEXT: srai a0, a0, 31 +; CHECK-NEXT: xor a0, a1, a0 +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: ori a0, a0, 16 +; CHECK-NEXT: ret + %ashr = ashr i32 %x, 15 + %a = ashr i32 %ashr, 31 + %b = xor i32 %ashr, %a + %c = call i32 @llvm.ctlz.i32(i32 %b, i1 false) + %d = sub i32 %c, 1 + %e = or i32 %d, 16 + ret i32 %e + } diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll index 5faf1079a7804..fa32f3ed39c92 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll @@ -112,3 +112,26 @@ define i64 @cls_i64_2(i64 %x) { %e = call i64 @llvm.ctlz.i64(i64 %d, i1 true) ret i64 %e } + +; Check that the range max in ctls cls knownbits +; is not set to 32. If it is, then ori disappears. +define i64 @cls_i64_not_32(i64 %x) { +; CHECK-LABEL: cls_i64_not_32: +; CHECK: # %bb.0: +; CHECK-NEXT: srai a1, a0, 16 +; CHECK-NEXT: srai a0, a0, 63 +; CHECK-NEXT: xor a0, a1, a0 +; CHECK-NEXT: slli a0, a0, 1 +; CHECK-NEXT: ori a0, a0, 1 +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: ori a0, a0, 16 +; CHECK-NEXT: ret + %val = ashr i64 %x, 16 + %a = ashr i64 %val, 63 + %b = xor i64 %val, %a + %c = shl i64 %b, 1 + %d = or i64 %c, 1 + %e = call i64 @llvm.ctlz.i64(i64 %d, i1 true) + %f = or i64 %e, 16 + ret i64 %f +} diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 3b63c1d86d3b1..d8dd000e1833b 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -98,6 +98,8 @@ ; CHECK-NEXT: Lazy Block Frequency Analysis ; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions +; CHECK-NEXT: MachineDominator Tree Construction +; CHECK-NEXT: RISC-V VL Optimizer ; CHECK-NEXT: RISC-V Vector Peephole Optimization ; CHECK-NEXT: RISC-V Fold Memory Offset ; CHECK-NEXT: Lazy Machine Block Frequency Analysis @@ -126,7 +128,6 @@ ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass ; CHECK-NEXT: RISC-V Merge Base Offset ; CHECK-NEXT: MachineDominator Tree Construction -; CHECK-NEXT: RISC-V VL Optimizer ; CHECK-NEXT: RISC-V pre-allocation Zilsd load/store optimization ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass ; CHECK-NEXT: RISC-V Insert Write VXRM Pass diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 522dc3579deb1..a17e199eed994 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -111,6 +111,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV32ZVQDOTQ %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s +; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV32ZVABD %s ; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s ; RUN: llc -mtriple=riscv32 -mattr=+zilsd %s -o - | FileCheck --check-prefix=RV32ZILSD %s ; RUN: llc -mtriple=riscv32 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s @@ -265,6 +266,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvqdotq %s -o - | FileCheck --check-prefix=RV64ZVQDOTQ %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s +; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvabd %s -o - | FileCheck --check-prefix=RV64ZVABD %s ; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s @@ -430,6 +432,7 @@ ; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV32ZVQDOTQ: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0" ; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" +; RV32ZVABD: .attribute 5, "rv32i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0" ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0" ; RV32ZILSD: .attribute 5, "rv32i2p1_zilsd1p0" ; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0" @@ -582,6 +585,7 @@ ; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV64ZVQDOTQ: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_zvqdotq0p0" ; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" +; RV64ZVABD: .attribute 5, "rv64i2p1_zicsr2p0_zvabd0p7_zve32x1p0_zvl32b1p0" ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0" ; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0" ; RV64ZCMOP: .attribute 5, "rv64i2p1_c2p0_zca1p0_zcmop1p0" diff --git a/llvm/test/CodeGen/RISCV/compress-opt-select.ll b/llvm/test/CodeGen/RISCV/compress-opt-select.ll index c0234f40cff56..fc1bf60d70755 100644 --- a/llvm/test/CodeGen/RISCV/compress-opt-select.ll +++ b/llvm/test/CodeGen/RISCV/compress-opt-select.ll @@ -2,6 +2,9 @@ ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d \ ; RUN: -M no-aliases < %s \ ; RUN: | FileCheck -check-prefix=RV32IFDC %s +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zca,+f,+d \ +; RUN: -M no-aliases < %s \ +; RUN: | FileCheck -check-prefix=RV32IFDC %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d \ ; RUN: -M no-aliases < %s \ ; RUN: | FileCheck -check-prefix=RV32IFD %s diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index a8d2be4ace515..c2e56061bf579 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -39,6 +39,7 @@ ; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate). ; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad). ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). +; CHECK-NEXT: experimental-zvabd - 'Zvabd' (Vector Absolute Difference). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). ; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support). ; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts). @@ -46,6 +47,12 @@ ; CHECK-NEXT: experimental-zvqdotq - 'Zvqdotq' (Vector quad widening 4D Dot Product). ; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point). ; CHECK-NEXT: forced-atomics - Assume that lock-free native-width atomics are available. +; CHECK-NEXT: fusion-add-mem - Enable ADD+LOAD/STORE macrofusion. +; CHECK-NEXT: fusion-logic-imm-reg - Enable ANDI/ORI/XORI+AND/OR/XOR macrofusion. +; CHECK-NEXT: fusion-logic-reg-imm - Enable AND/OR/XOR+ANDI/ORI/XORI macrofusion. +; CHECK-NEXT: fusion-logic-reg-reg - Enable AND/OR/XOR+AND/OR/XOR macrofusion. +; CHECK-NEXT: fusion-mul-add - Enable MUL+ADD macrofusion. +; CHECK-NEXT: fusion-shift-bit-extract - Enable SLLI+SRLI/SRAI macrofusion. ; CHECK-NEXT: h - 'H' (Hypervisor). ; CHECK-NEXT: i - 'I' (Base Integer Instruction Set). ; CHECK-NEXT: ld-add-fusion - Enable LD+ADD macrofusion. diff --git a/llvm/test/CodeGen/RISCV/macho-relocs.ll b/llvm/test/CodeGen/RISCV/macho-relocs.ll new file mode 100644 index 0000000000000..9090d1b09e4ab --- /dev/null +++ b/llvm/test/CodeGen/RISCV/macho-relocs.ll @@ -0,0 +1,96 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=riscv32-apple-none-macho < %s -verify-machineinstrs | FileCheck %s --check-prefixes=COMMON,DEFAULT +; RUN: llc -mtriple=riscv32-apple-none-macho < %s -relocation-model=static -verify-machineinstrs | FileCheck %s --check-prefixes=COMMON,STATIC + +define void @simple() nounwind { +; COMMON-LABEL: simple: +; COMMON: ; %bb.0: +; COMMON-NEXT: ret + ret void +} + +define void @call() nounwind { +; COMMON-LABEL: call: +; COMMON: ; %bb.0: +; COMMON-NEXT: addi sp, sp, -16 +; COMMON-NEXT: sw ra, 12(sp) ; 4-byte Folded Spill +; COMMON-NEXT: call _tail_call +; COMMON-NEXT: lw ra, 12(sp) ; 4-byte Folded Reload +; COMMON-NEXT: addi sp, sp, 16 +; COMMON-NEXT: ret + call void @tail_call() + ret void +} + +define void @tail_call() nounwind { +; COMMON-LABEL: tail_call: +; COMMON: ; %bb.0: +; COMMON-NEXT: tail _call + tail call void @call() + ret void +} + +@var = global i32 0 +define ptr @direct_global() nounwind { +; DEFAULT-LABEL: direct_global: +; DEFAULT: ; %bb.0: +; DEFAULT-NEXT: Lpcrel_hi0: +; DEFAULT-NEXT: auipc a0, %pcrel_hi(_var) +; DEFAULT-NEXT: addi a0, a0, %pcrel_lo(Lpcrel_hi0) +; DEFAULT-NEXT: ret +; +; STATIC-LABEL: direct_global: +; STATIC: ; %bb.0: +; STATIC-NEXT: lui a0, %hi(_var) +; STATIC-NEXT: addi a0, a0, %lo(_var) +; STATIC-NEXT: ret + ret ptr @var +} + +;; No GOTs in static CodeGen. +@var2 = external global i32 +define ptr @got_global() nounwind { +; DEFAULT-LABEL: got_global: +; DEFAULT: ; %bb.0: +; DEFAULT-NEXT: Lpcrel_hi1: +; DEFAULT-NEXT: auipc a0, %got_pcrel_hi(_var2) +; DEFAULT-NEXT: lw a0, %pcrel_lo(Lpcrel_hi1)(a0) +; DEFAULT-NEXT: ret +; +; STATIC-LABEL: got_global: +; STATIC: ; %bb.0: +; STATIC-NEXT: lui a0, %hi(_var2) +; STATIC-NEXT: addi a0, a0, %lo(_var2) +; STATIC-NEXT: ret + ret ptr @var2 +} + +@anon = private unnamed_addr constant i32 42 +define ptr @unnamed_const() nounwind { +; DEFAULT-LABEL: unnamed_const: +; DEFAULT: ; %bb.0: +; DEFAULT-NEXT: Lpcrel_hi2: +; DEFAULT-NEXT: auipc a0, %pcrel_hi(l_anon) +; DEFAULT-NEXT: addi a0, a0, %pcrel_lo(Lpcrel_hi2) +; DEFAULT-NEXT: ret +; +; STATIC-LABEL: unnamed_const: +; STATIC: ; %bb.0: +; STATIC-NEXT: lui a0, %hi(l_anon) +; STATIC-NEXT: addi a0, a0, %lo(l_anon) +; STATIC-NEXT: ret + ret ptr @anon +} + +; UTC_ARGS: --disable +; COMMON-LABEL: l_anon: +; COMMON-NEXT: .word 42 + +; COMMON-LABEL: .section __DATA,__data +; COMMON-LABEL: _addend: +; COMMON-NEXT: .word _simple+42 +@addend = global i32 add(i32 ptrtoint(ptr @simple to i32), i32 42) + +; COMMON-LABEL: _sub: +; COMMON-NEXT: .word _simple-_call +@sub = global i32 sub(i32 ptrtoint(ptr @simple to i32), i32 ptrtoint(ptr @call to i32)) diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir b/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir new file mode 100644 index 0000000000000..66029bda38e80 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/macro-fusion-add-mem.mir @@ -0,0 +1,102 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-add-mem | FileCheck %s + +# Test add-mem fusion: ADD + load/store with offset 0 +# This fusion combines an address calculation (ADD) with a memory operation +# that uses the calculated address with zero offset. + +# CHECK: add_lb +# CHECK: Macro fuse: {{.*}}ADD - LB +--- +name: add_lb +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + %5:gpr = LB %4, 0 + %6:gpr = XORI %3, 3 + $x10 = COPY %6 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_lh +# CHECK: Macro fuse: {{.*}}ADD - LH +--- +name: add_lh +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + %5:gpr = LH %4, 0 + %6:gpr = XORI %3, 3 + $x10 = COPY %6 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: add_sw +# CHECK: Macro fuse: {{.*}}ADD - SW +--- +name: add_sw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + SW %3, %4, 0 + %5:gpr = XORI %3, 3 + $x10 = COPY %5 + PseudoRET +... + +# CHECK: add_sd +# CHECK: Macro fuse: {{.*}}ADD - SD +--- +name: add_sd +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + SD %3, %4, 0 + %5:gpr = XORI %3, 3 + $x10 = COPY %5 + PseudoRET +... + +# Test that add-mem fusion does not happen with non-zero offset +# CHECK: add_lb_no_fusion +# CHECK-NOT: Macro fuse: {{.*}}ADD - LB +--- +name: add_lb_no_fusion +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = ADD %1, %2 + %5:gpr = LB %4, 8 + %6:gpr = XORI %3, 3 + $x10 = COPY %6 + $x11 = COPY %5 + PseudoRET +... diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir b/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir new file mode 100644 index 0000000000000..55261abaad531 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/macro-fusion-logic-imm-reg.mir @@ -0,0 +1,62 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-logic-imm-reg | FileCheck %s + +# Test logic immediate-register fusion: ANDI/ORI/XORI + AND/OR/XOR +# This fusion combines a logic operation with an immediate followed by +# a logic operation on registers. + +# CHECK: andi_and +# CHECK: Macro fuse: {{.*}}ANDI - AND +--- +name: andi_and +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ANDI %1, 255 + %4:gpr = XORI %2, 3 + %5:gpr = AND %3, %2 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: ori_or +# CHECK: Macro fuse: {{.*}}ORI - OR +--- +name: ori_or +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = ORI %1, 15 + %4:gpr = XORI %2, 3 + %5:gpr = OR %3, %2 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: xori_xor +# CHECK: Macro fuse: {{.*}}XORI - XOR +--- +name: xori_xor +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = XORI %1, 15 + %4:gpr = XORI %2, 3 + %5:gpr = XOR %3, %2 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir b/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir new file mode 100644 index 0000000000000..eba113b97c99c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-imm.mir @@ -0,0 +1,62 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-logic-reg-imm | FileCheck %s + +# Test logic register-immediate fusion: AND/OR/XOR + ANDI/ORI/XORI +# This fusion combines a logic operation on registers followed by +# a logic operation with an immediate. + +# CHECK: and_andi +# CHECK: Macro fuse: {{.*}}AND - ANDI +--- +name: and_andi +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = AND %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = ANDI %3, 255 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: or_ori +# CHECK: Macro fuse: {{.*}}OR - ORI +--- +name: or_ori +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = OR %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = ORI %3, 15 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... + +# CHECK: xor_xori +# CHECK: Macro fuse: {{.*}}XOR - XORI +--- +name: xor_xori +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = XOR %1, %2 + %4:gpr = XORI %2, 3 + %5:gpr = XORI %3, 7 + $x10 = COPY %4 + $x11 = COPY %5 + PseudoRET +... diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir b/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir new file mode 100644 index 0000000000000..582d7c77280e5 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/macro-fusion-logic-reg-reg.mir @@ -0,0 +1,64 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-logic-reg-reg | FileCheck %s + +# Test logic register-register fusion: AND/OR/XOR + AND/OR/XOR +# This fusion combines two consecutive logic operations on registers. + +# CHECK: and_or +# CHECK: Macro fuse: {{.*}}AND - OR +--- +name: and_or +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = AND %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = OR %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + +# CHECK: xor_and +# CHECK: Macro fuse: {{.*}}XOR - AND +--- +name: xor_and +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = XOR %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = AND %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + +# CHECK: or_xor +# CHECK: Macro fuse: {{.*}}OR - XOR +--- +name: or_xor +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = OR %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = XOR %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir b/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir new file mode 100644 index 0000000000000..08c3f24575642 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/macro-fusion-mul-add.mir @@ -0,0 +1,67 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+m,+fusion-mul-add | FileCheck %s + +# Test mul-add fusion: MUL + ADD and MULW + ADDW +# This fusion combines a multiplication followed by an addition. +# Both instructions must have the same width (W suffix or not). + +# CHECK: mul_add +# CHECK: Macro fuse: {{.*}}MUL - ADD +--- +name: mul_add +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = MUL %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = ADD %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + +# CHECK: mulw_addw +# CHECK: Macro fuse: {{.*}}MULW - ADDW +--- +name: mulw_addw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = MULW %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = ADDW %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + +# Test that fusion does not happen with different widths +# CHECK: mul_addw_no_fusion +# CHECK-NOT: Macro fuse: {{.*}}MUL - ADDW +--- +name: mul_addw_no_fusion +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11, $x12 + %1:gpr = COPY $x10 + %2:gpr = COPY $x11 + %3:gpr = COPY $x12 + %4:gpr = MUL %1, %2 + %5:gpr = XORI %3, 3 + %6:gpr = ADDW %4, %3 + $x10 = COPY %5 + $x11 = COPY %6 + PseudoRET +... + diff --git a/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir b/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir new file mode 100644 index 0000000000000..4ce6c1431081c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/macro-fusion-shift-bit-extract.mir @@ -0,0 +1,132 @@ +# REQUIRES: asserts +# RUN: llc -mtriple=riscv64-linux-gnu -x=mir < %s \ +# RUN: -debug-only=machine-scheduler -start-before=machine-scheduler 2>&1 \ +# RUN: -mattr=+fusion-shift-bit-extract | FileCheck %s + +# Test shift-bit-extract fusion: SLLI + SRLI/SRAI +# This fusion combines left shift followed by right shift with the constraint +# that the first immediate must be less than or equal to the second immediate. +# It also checks that both instructions have the same width (W suffix or not). + +# CHECK: slli_srli +# CHECK: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 8 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 16 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slli_srai +# CHECK: Macro fuse: {{.*}}SLLI - SRAI +--- +name: slli_srai +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 4 + %3:gpr = XORI %1, 3 + %4:gpr = SRAI %2, 8 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# Test with equal immediates +# CHECK: slli_srai_equal +# CHECK: Macro fuse: {{.*}}SLLI - SRAI +--- +name: slli_srai_equal +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 12 + %3:gpr = XORI %1, 3 + %4:gpr = SRAI %2, 12 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# Test W-suffix variants (32-bit operations on RV64) +# CHECK: slliw_srliw +# CHECK: Macro fuse: {{.*}}SLLIW - SRLIW +--- +name: slliw_srliw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLIW %1, 8 + %3:gpr = XORI %1, 3 + %4:gpr = SRLIW %2, 16 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# CHECK: slliw_sraiw +# CHECK: Macro fuse: {{.*}}SLLIW - SRAIW +--- +name: slliw_sraiw +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLIW %1, 4 + %3:gpr = XORI %1, 3 + %4:gpr = SRAIW %2, 8 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# Test that fusion does not happen with different widths +# CHECK: slli_srliw_no_fusion +# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLIW +--- +name: slli_srliw_no_fusion +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 8 + %3:gpr = XORI %1, 3 + %4:gpr = SRLIW %2, 16 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... + +# Test that fusion does not happen when imm1 > imm2 +# CHECK: slli_srli_no_fusion +# CHECK-NOT: Macro fuse: {{.*}}SLLI - SRLI +--- +name: slli_srli_no_fusion +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10 + %1:gpr = COPY $x10 + %2:gpr = SLLI %1, 16 + %3:gpr = XORI %1, 3 + %4:gpr = SRLI %2, 8 + $x10 = COPY %3 + $x11 = COPY %4 + PseudoRET +... diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir index b4ea9260297f7..47407c2270ead 100644 --- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir +++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir @@ -54,7 +54,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 - ; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]] /* vl */, 0 /* e8 */ ; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]] ; CHECK-NEXT: PseudoRET %0:vr = COPY $v8 @@ -77,7 +77,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10 - ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]] /* vl */, 0 /* e8 */ ; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]] ; CHECK-NEXT: PseudoRET %0:vr = COPY $v8 diff --git a/llvm/test/CodeGen/RISCV/pr176001.ll b/llvm/test/CodeGen/RISCV/pr176001.ll index 3ad4ac2e44e94..75c299a71f320 100644 --- a/llvm/test/CodeGen/RISCV/pr176001.ll +++ b/llvm/test/CodeGen/RISCV/pr176001.ll @@ -13,7 +13,7 @@ define <32 x i64> @main(i1 %tobool93.not, <32 x i64> %0, <32 x i64> %1) #0 { ; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1.BS_LABEL_5: - ; CHECK-NEXT: renamable $v8m8 = PseudoVMV_V_I_M8 undef renamable $v8m8, 0, 16, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: renamable $v8m8 = PseudoVMV_V_I_M8 undef renamable $v8m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: $v16m8 = COPY renamable $v8m8 ; CHECK-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 ; CHECK-NEXT: {{ $}} @@ -21,7 +21,7 @@ define <32 x i64> @main(i1 %tobool93.not, <32 x i64> %0, <32 x i64> %1) #0 { ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: liveins: $v8m8:0x0000000000000002, $v16m8:0x0000000000000006 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: renamable $v24m8 = PseudoVLE64_V_M8 undef renamable $v24m8, [[COPY]], 16, 6 /* e64 */, 2 /* tu, ma */ :: (load (s1024)) + ; CHECK-NEXT: renamable $v24m8 = PseudoVLE64_V_M8 undef renamable $v24m8, [[COPY]], 16 /* vl */, 6 /* e64 */, 2 /* tu, ma */ :: (load (s1024)) ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 1 ; CHECK-NEXT: BNE [[ANDI]], $x0, %bb.4 ; CHECK-NEXT: PseudoBR %bb.3 @@ -55,11 +55,11 @@ define <32 x i64> @main(i1 %tobool93.not, <32 x i64> %0, <32 x i64> %1) #0 { ; CHECK-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000) ; CHECK-NEXT: liveins: $v16m8:0x0000000000000006 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: renamable $v0m8 = PseudoVMV_V_I_M8 undef renamable $v0m8, 0, 16, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: renamable $v0m8 = PseudoVMV_V_I_M8 undef renamable $v0m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: renamable $v24m8 = COPY renamable $v0m8 - ; CHECK-NEXT: renamable $v8m2 = PseudoVSLIDEDOWN_VI_M2 undef renamable $v8m2, killed renamable $v16m2, 2, 1, 6 /* e64 */, 3 /* ta, ma */ + ; CHECK-NEXT: renamable $v8m2 = PseudoVSLIDEDOWN_VI_M2 undef renamable $v8m2, killed renamable $v16m2, 2, 1 /* vl */, 6 /* e64 */, 3 /* ta, ma */ ; CHECK-NEXT: [[PseudoVMV_X_S1:%[0-9]+]]:gpr = PseudoVMV_X_S killed renamable $v8, 6 /* e64 */ - ; CHECK-NEXT: renamable $v24m8 = PseudoVMV_V_V_M8 killed renamable $v24m8, killed renamable $v0m8, 1, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: renamable $v24m8 = PseudoVMV_V_V_M8 killed renamable $v24m8, killed renamable $v0m8, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: BNE [[PseudoVMV_X_S1]], $x0, %bb.9 ; CHECK-NEXT: PseudoBR %bb.8 ; CHECK-NEXT: {{ $}} @@ -70,22 +70,22 @@ define <32 x i64> @main(i1 %tobool93.not, <32 x i64> %0, <32 x i64> %1) #0 { ; CHECK-NEXT: bb.9.cond.end133: ; CHECK-NEXT: liveins: $v24m8 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: renamable $v0m8 = PseudoVMV_V_I_M8 undef renamable $v0m8, 0, 16, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: renamable $v0m8 = PseudoVMV_V_I_M8 undef renamable $v0m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: renamable $v16 = COPY renamable $v0 ; CHECK-NEXT: renamable $v8m8 = VL8RE8_V %stack.0 :: (load () from %stack.0, align 8) ; CHECK-NEXT: [[PseudoVMV_X_S2:%[0-9]+]]:gpr = PseudoVMV_X_S killed renamable $v8, 5 /* e32 */ ; CHECK-NEXT: renamable $v8m8 = COPY renamable $v0m8 - ; CHECK-NEXT: early-clobber renamable $v17 = PseudoVMSLEU_VV_M8 killed renamable $v0m8, killed renamable $v24m8, 16, 6 /* e64 */ - ; CHECK-NEXT: renamable $v16 = PseudoVMV_S_X killed renamable $v16, $x0, 16, 6 /* e64 */ - ; CHECK-NEXT: renamable $v16 = PseudoVMV_S_X killed renamable $v16, [[PseudoVMV_X_S2]], 16, 6 /* e64 */ - ; CHECK-NEXT: renamable $v24m8 = PseudoVMV_V_I_M8 undef renamable $v24m8, 0, 16, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber renamable $v17 = PseudoVMSLEU_VV_M8 killed renamable $v0m8, killed renamable $v24m8, 16 /* vl */, 6 /* e64 */ + ; CHECK-NEXT: renamable $v16 = PseudoVMV_S_X killed renamable $v16, $x0, 16 /* vl */, 6 /* e64 */ + ; CHECK-NEXT: renamable $v16 = PseudoVMV_S_X killed renamable $v16, [[PseudoVMV_X_S2]], 16 /* vl */, 6 /* e64 */ + ; CHECK-NEXT: renamable $v24m8 = PseudoVMV_V_I_M8 undef renamable $v24m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: renamable $v8 = COPY killed renamable $v16 ; CHECK-NEXT: $v0 = COPY killed renamable $v17 - ; CHECK-NEXT: renamable $v16m8 = PseudoVMERGE_VIM_M8 undef renamable $v16m8, killed renamable $v24m8, -1, $v0, 16, 6 /* e64 */ - ; CHECK-NEXT: renamable $v24m8 = PseudoVMV_V_I_M8 undef renamable $v24m8, 0, 16, 6 /* e64 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber renamable $v0 = PseudoVMSLEU_VV_M8 killed renamable $v24m8, killed renamable $v8m8, 16, 6 /* e64 */ - ; CHECK-NEXT: renamable $v8m8 = PseudoVMV_V_I_M8 undef renamable $v8m8, 0, 16, 6 /* e64 */, 0 /* tu, mu */ - ; CHECK-NEXT: renamable $v8m8 = PseudoVMERGE_VIM_M8 undef renamable $v8m8, killed renamable $v8m8, -1, $v0, 16, 6 /* e64 */ + ; CHECK-NEXT: renamable $v16m8 = PseudoVMERGE_VIM_M8 undef renamable $v16m8, killed renamable $v24m8, -1, $v0, 16 /* vl */, 6 /* e64 */ + ; CHECK-NEXT: renamable $v24m8 = PseudoVMV_V_I_M8 undef renamable $v24m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber renamable $v0 = PseudoVMSLEU_VV_M8 killed renamable $v24m8, killed renamable $v8m8, 16 /* vl */, 6 /* e64 */ + ; CHECK-NEXT: renamable $v8m8 = PseudoVMV_V_I_M8 undef renamable $v8m8, 0, 16 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: renamable $v8m8 = PseudoVMERGE_VIM_M8 undef renamable $v8m8, killed renamable $v8m8, -1, $v0, 16 /* vl */, 6 /* e64 */ ; CHECK-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 entry: switch i32 0, label %BS_LABEL_5 [ diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll index 67d76f69ab3dd..8c45d0dac5baf 100644 --- a/llvm/test/CodeGen/RISCV/rv32p.ll +++ b/llvm/test/CodeGen/RISCV/rv32p.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+zbb -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+zbb,+m -verify-machineinstrs \ ; RUN: < %s | FileCheck %s define i32 @abs_i32(i32 %x) { @@ -16,10 +16,7 @@ define i64 @abs_i64(i64 %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: bgez a1, .LBB1_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: snez a2, a0 -; CHECK-NEXT: neg a0, a0 -; CHECK-NEXT: neg a1, a1 -; CHECK-NEXT: sub a1, a1, a2 +; CHECK-NEXT: subd a0, zero, a0 ; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: ret %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) @@ -189,15 +186,16 @@ define i64 @cls_i64(i64 %x) { ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: xor a0, a0, a2 ; CHECK-NEXT: clz a0, a0 -; CHECK-NEXT: addi a1, a0, 32 +; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: j .LBB15_3 ; CHECK-NEXT: .LBB15_2: ; CHECK-NEXT: xor a1, a1, a2 -; CHECK-NEXT: clz a1, a1 +; CHECK-NEXT: clz a0, a1 ; CHECK-NEXT: .LBB15_3: -; CHECK-NEXT: addi a0, a1, -1 -; CHECK-NEXT: snez a1, a1 -; CHECK-NEXT: addi a1, a1, -1 +; CHECK-NEXT: li a1, 0 +; CHECK-NEXT: li a2, -1 +; CHECK-NEXT: mv a3, a2 +; CHECK-NEXT: addd a0, a0, a2 ; CHECK-NEXT: ret %a = ashr i64 %x, 63 %b = xor i64 %x, %a @@ -530,3 +528,172 @@ define i32 @usub_i32(i32 %x, i32 %y) { %a = call i32 @llvm.usub.sat.i32(i32 %x, i32 %y) ret i32 %a } + +define i64 @wmul_i32(i32 %x, i32 %y) { +; CHECK-LABEL: wmul_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: wmul a0, a0, a1 +; CHECK-NEXT: ret + %a = sext i32 %x to i64 + %b = sext i32 %y to i64 + %c = mul i64 %a, %b + ret i64 %c +} + +define i64 @wmulu_i32(i32 %x, i32 %y) { +; CHECK-LABEL: wmulu_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: wmulu a0, a0, a1 +; CHECK-NEXT: ret + %a = zext i32 %x to i64 + %b = zext i32 %y to i64 + %c = mul i64 %a, %b + ret i64 %c +} + +define i64 @wmulsu_i32(i32 %x, i32 %y) { +; CHECK-LABEL: wmulsu_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: wmulsu a0, a1, a0 +; CHECK-NEXT: ret + %a = zext i32 %x to i64 + %b = sext i32 %y to i64 + %c = mul i64 %a, %b + ret i64 %c +} + +; Test that mulh continues to be used with P. +define i32 @mulh_i32(i32 %x, i32 %y) { +; CHECK-LABEL: mulh_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: mulh a0, a0, a1 +; CHECK-NEXT: ret + %a = sext i32 %x to i64 + %b = sext i32 %y to i64 + %c = mul i64 %a, %b + %d = lshr i64 %c, 32 + %e = trunc i64 %d to i32 + ret i32 %e +} + +; Test that mulhu continues to be used with P. +define i32 @mulhu_i32(i32 %x, i32 %y) { +; CHECK-LABEL: mulhu_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: mulhu a0, a0, a1 +; CHECK-NEXT: ret + %a = zext i32 %x to i64 + %b = zext i32 %y to i64 + %c = mul i64 %a, %b + %d = lshr i64 %c, 32 + %e = trunc i64 %d to i32 + ret i32 %e +} + +; Test that mulhsu continues to be used with P. +define i32 @mulhsu_i32(i32 %x, i32 %y) { +; CHECK-LABEL: mulhsu_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: mulhsu a0, a1, a0 +; CHECK-NEXT: ret + %a = zext i32 %x to i64 + %b = sext i32 %y to i64 + %c = mul i64 %a, %b + %d = lshr i64 %c, 32 + %e = trunc i64 %d to i32 + ret i32 %e +} + +define i64 @add_i64(i64 %x, i64 %y) { +; CHECK-LABEL: add_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: addd a0, a0, a2 +; CHECK-NEXT: ret + %a = add i64 %x, %y + ret i64 %a +} + +define i64 @sub_i64(i64 %x, i64 %y) { +; CHECK-LABEL: sub_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: subd a0, a0, a2 +; CHECK-NEXT: ret + %a = sub i64 %x, %y + ret i64 %a +} + +define i64 @wmaccu(i32 %a, i32 %b, i64 %c) nounwind { +; CHECK-LABEL: wmaccu: +; CHECK: # %bb.0: +; CHECK-NEXT: wmaccu a2, a0, a1 +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: ret + %aext = zext i32 %a to i64 + %bext = zext i32 %b to i64 + %mul = mul i64 %aext, %bext + %result = add i64 %c, %mul + ret i64 %result +} + +define i64 @wmaccu_commute(i32 %a, i32 %b, i64 %c) nounwind { +; CHECK-LABEL: wmaccu_commute: +; CHECK: # %bb.0: +; CHECK-NEXT: wmaccu a2, a0, a1 +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: ret + %aext = zext i32 %a to i64 + %bext = zext i32 %b to i64 + %mul = mul i64 %aext, %bext + %result = add i64 %mul, %c + ret i64 %result +} + +define i64 @wmacc(i32 %a, i32 %b, i64 %c) nounwind { +; CHECK-LABEL: wmacc: +; CHECK: # %bb.0: +; CHECK-NEXT: wmacc a2, a0, a1 +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: ret + %aext = sext i32 %a to i64 + %bext = sext i32 %b to i64 + %mul = mul i64 %aext, %bext + %result = add i64 %c, %mul + ret i64 %result +} + +define i64 @wmacc_commute(i32 %a, i32 %b, i64 %c) nounwind { +; CHECK-LABEL: wmacc_commute: +; CHECK: # %bb.0: +; CHECK-NEXT: wmacc a2, a0, a1 +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: ret + %aext = sext i32 %a to i64 + %bext = sext i32 %b to i64 + %mul = mul i64 %aext, %bext + %result = add i64 %mul, %c + ret i64 %result +} + +; Negative test: multiply result has multiple uses, should not combine +define void @wmaccu_multiple_uses(i32 %a, i32 %b, i64 %c, ptr %out1, ptr %out2) nounwind { +; CHECK-LABEL: wmaccu_multiple_uses: +; CHECK: # %bb.0: +; CHECK-NEXT: wmulu a0, a0, a1 +; CHECK-NEXT: addd a2, a2, a0 +; CHECK-NEXT: sw a2, 0(a4) +; CHECK-NEXT: sw a3, 4(a4) +; CHECK-NEXT: sw a0, 0(a5) +; CHECK-NEXT: sw a1, 4(a5) +; CHECK-NEXT: ret + %aext = zext i32 %a to i64 + %bext = zext i32 %b to i64 + %mul = mul i64 %aext, %bext + %result = add i64 %c, %mul + store i64 %result, ptr %out1 + store i64 %mul, ptr %out2 + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll index 491c2e1ee8a0a..3193a0e48f428 100644 --- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll @@ -488,6 +488,76 @@ define i8 @test_extract_vector_8_elem1(<4 x i8> %a) { ret i8 %extracted } +define <2 x i16> @test_insert_vector_16(<2 x i16> %a, i16 %val) { +; CHECK-RV32-LABEL: test_insert_vector_16: +; CHECK-RV32: # %bb.0: +; CHECK-RV32-NEXT: srli a0, a0, 16 +; CHECK-RV32-NEXT: pack a0, a1, a0 +; CHECK-RV32-NEXT: ret +; +; CHECK-RV64-LABEL: test_insert_vector_16: +; CHECK-RV64: # %bb.0: +; CHECK-RV64-NEXT: srli a0, a0, 16 +; CHECK-RV64-NEXT: ppaire.h a0, a1, a0 +; CHECK-RV64-NEXT: ret + %res = insertelement <2 x i16> %a, i16 %val, i32 0 + ret <2 x i16> %res +} + +define <2 x i16> @test_insert_vector_16_elem1(<2 x i16> %a, i16 %val) { +; CHECK-RV32-LABEL: test_insert_vector_16_elem1: +; CHECK-RV32: # %bb.0: +; CHECK-RV32-NEXT: pack a0, a0, a1 +; CHECK-RV32-NEXT: ret +; +; CHECK-RV64-LABEL: test_insert_vector_16_elem1: +; CHECK-RV64: # %bb.0: +; CHECK-RV64-NEXT: ppaire.h a0, a0, a1 +; CHECK-RV64-NEXT: ret + %res = insertelement <2 x i16> %a, i16 %val, i32 1 + ret <2 x i16> %res +} + +define <4 x i8> @test_insert_vector_8(<4 x i8> %a, i8 %val) { +; CHECK-RV32-LABEL: test_insert_vector_8: +; CHECK-RV32: # %bb.0: +; CHECK-RV32-NEXT: li a2, 255 +; CHECK-RV32-NEXT: mvm a0, a1, a2 +; CHECK-RV32-NEXT: ret +; +; CHECK-RV64-LABEL: test_insert_vector_8: +; CHECK-RV64: # %bb.0: +; CHECK-RV64-NEXT: srli a2, a0, 8 +; CHECK-RV64-NEXT: srli a3, a0, 24 +; CHECK-RV64-NEXT: srli a0, a0, 16 +; CHECK-RV64-NEXT: ppaire.b a0, a0, a3 +; CHECK-RV64-NEXT: ppaire.b a1, a1, a2 +; CHECK-RV64-NEXT: ppaire.h a0, a1, a0 +; CHECK-RV64-NEXT: ret + %res = insertelement <4 x i8> %a, i8 %val, i32 0 + ret <4 x i8> %res +} + +define <4 x i8> @test_insert_vector_8_elem2(<4 x i8> %a, i8 %val) { +; CHECK-RV32-LABEL: test_insert_vector_8_elem2: +; CHECK-RV32: # %bb.0: +; CHECK-RV32-NEXT: slli a1, a1, 16 +; CHECK-RV32-NEXT: lui a2, 4080 +; CHECK-RV32-NEXT: mvm a0, a1, a2 +; CHECK-RV32-NEXT: ret +; +; CHECK-RV64-LABEL: test_insert_vector_8_elem2: +; CHECK-RV64: # %bb.0: +; CHECK-RV64-NEXT: srli a2, a0, 8 +; CHECK-RV64-NEXT: srli a3, a0, 24 +; CHECK-RV64-NEXT: ppaire.b a1, a1, a3 +; CHECK-RV64-NEXT: ppaire.b a0, a0, a2 +; CHECK-RV64-NEXT: ppaire.h a0, a0, a1 +; CHECK-RV64-NEXT: ret + %res = insertelement <4 x i8> %a, i8 %val, i32 2 + ret <4 x i8> %res +} + ; Test for splat define <4 x i8> @test_non_const_splat_i8(i8 %elt) { ; CHECK-LABEL: test_non_const_splat_i8: @@ -1629,10 +1699,10 @@ define <2 x i16> @test_select_v2i16(i1 %cond, <2 x i16> %a, <2 x i16> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a3, a0, 1 ; CHECK-NEXT: mv a0, a1 -; CHECK-NEXT: bnez a3, .LBB115_2 +; CHECK-NEXT: bnez a3, .LBB119_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: .LBB115_2: +; CHECK-NEXT: .LBB119_2: ; CHECK-NEXT: ret %res = select i1 %cond, <2 x i16> %a, <2 x i16> %b ret <2 x i16> %res @@ -1643,10 +1713,10 @@ define <4 x i8> @test_select_v4i8(i1 %cond, <4 x i8> %a, <4 x i8> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a3, a0, 1 ; CHECK-NEXT: mv a0, a1 -; CHECK-NEXT: bnez a3, .LBB116_2 +; CHECK-NEXT: bnez a3, .LBB120_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: .LBB116_2: +; CHECK-NEXT: .LBB120_2: ; CHECK-NEXT: ret %res = select i1 %cond, <4 x i8> %a, <4 x i8> %b ret <4 x i8> %res diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll index 5d249d580b64f..0da0bb339b0a2 100644 --- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll @@ -545,6 +545,70 @@ define i32 @test_extract_vector_32_elem1(<2 x i32> %a) { ret i32 %extracted } +define <4 x i16> @test_insert_vector_16(<4 x i16> %a, i16 %val) { +; CHECK-LABEL: test_insert_vector_16: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a2, 16 +; CHECK-NEXT: addi a2, a2, -1 +; CHECK-NEXT: mvm a0, a1, a2 +; CHECK-NEXT: ret + %res = insertelement <4 x i16> %a, i16 %val, i32 0 + ret <4 x i16> %res +} + +define <4 x i16> @test_insert_vector_16_elem2(<4 x i16> %a, i16 %val) { +; CHECK-LABEL: test_insert_vector_16_elem2: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a1, a1, 32 +; CHECK-NEXT: lui a2, 65535 +; CHECK-NEXT: slli a2, a2, 20 +; CHECK-NEXT: mvm a0, a1, a2 +; CHECK-NEXT: ret + %res = insertelement <4 x i16> %a, i16 %val, i32 2 + ret <4 x i16> %res +} + +define <8 x i8> @test_insert_vector_8(<8 x i8> %a, i8 %val) { +; CHECK-LABEL: test_insert_vector_8: +; CHECK: # %bb.0: +; CHECK-NEXT: li a2, 255 +; CHECK-NEXT: mvm a0, a1, a2 +; CHECK-NEXT: ret + %res = insertelement <8 x i8> %a, i8 %val, i32 0 + ret <8 x i8> %res +} + +define <8 x i8> @test_insert_vector_8_elem3(<8 x i8> %a, i8 %val) { +; CHECK-LABEL: test_insert_vector_8_elem3: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a1, a1, 24 +; CHECK-NEXT: li a2, 255 +; CHECK-NEXT: slli a2, a2, 24 +; CHECK-NEXT: mvm a0, a1, a2 +; CHECK-NEXT: ret + %res = insertelement <8 x i8> %a, i8 %val, i32 3 + ret <8 x i8> %res +} + +define <2 x i32> @test_insert_vector_32(<2 x i32> %a, i32 %val) { +; CHECK-LABEL: test_insert_vector_32: +; CHECK: # %bb.0: +; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: pack a0, a1, a0 +; CHECK-NEXT: ret + %res = insertelement <2 x i32> %a, i32 %val, i32 0 + ret <2 x i32> %res +} + +define <2 x i32> @test_insert_vector_32_elem1(<2 x i32> %a, i32 %val) { +; CHECK-LABEL: test_insert_vector_32_elem1: +; CHECK: # %bb.0: +; CHECK-NEXT: pack a0, a0, a1 +; CHECK-NEXT: ret + %res = insertelement <2 x i32> %a, i32 %val, i32 1 + ret <2 x i32> %res +} + ; Test basic add/sub operations for v2i32 (RV64 only) define <2 x i32> @test_padd_w(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: test_padd_w: @@ -1941,10 +2005,10 @@ define <4 x i16> @test_select_v4i16(i1 %cond, <4 x i16> %a, <4 x i16> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a3, a0, 1 ; CHECK-NEXT: mv a0, a1 -; CHECK-NEXT: bnez a3, .LBB155_2 +; CHECK-NEXT: bnez a3, .LBB161_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: .LBB155_2: +; CHECK-NEXT: .LBB161_2: ; CHECK-NEXT: ret %res = select i1 %cond, <4 x i16> %a, <4 x i16> %b ret <4 x i16> %res @@ -1955,10 +2019,10 @@ define <8 x i8> @test_select_v8i8(i1 %cond, <8 x i8> %a, <8 x i8> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a3, a0, 1 ; CHECK-NEXT: mv a0, a1 -; CHECK-NEXT: bnez a3, .LBB156_2 +; CHECK-NEXT: bnez a3, .LBB162_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: .LBB156_2: +; CHECK-NEXT: .LBB162_2: ; CHECK-NEXT: ret %res = select i1 %cond, <8 x i8> %a, <8 x i8> %b ret <8 x i8> %res @@ -1969,10 +2033,10 @@ define <2 x i32> @test_select_v2i32(i1 %cond, <2 x i32> %a, <2 x i32> %b) { ; CHECK: # %bb.0: ; CHECK-NEXT: andi a3, a0, 1 ; CHECK-NEXT: mv a0, a1 -; CHECK-NEXT: bnez a3, .LBB157_2 +; CHECK-NEXT: bnez a3, .LBB163_2 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: .LBB157_2: +; CHECK-NEXT: .LBB163_2: ; CHECK-NEXT: ret %res = select i1 %cond, <2 x i32> %a, <2 x i32> %b ret <2 x i32> %res diff --git a/llvm/test/CodeGen/RISCV/rvv/abd.ll b/llvm/test/CodeGen/RISCV/rvv/abd.ll index 949a9a3dfc470..c451559a29a69 100644 --- a/llvm/test/CodeGen/RISCV/rvv/abd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abd.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+experimental-zvabd -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD,ZVABD-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+experimental-zvabd -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD,ZVABD-RV64 ; ; SABD @@ -14,6 +16,12 @@ define @sabd_b( %a, %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -30,6 +38,14 @@ define @sabd_b_promoted_ops( %a, %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -45,6 +61,12 @@ define @sabd_h( %a, %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -63,6 +85,14 @@ define @sabd_h_promoted_ops( %a, %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -78,6 +108,14 @@ define @sabd_s( %a, %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; ZVABD-NEXT: vmin.vv v12, v8, v10 +; ZVABD-NEXT: vmax.vv v8, v8, v10 +; ZVABD-NEXT: vsub.vv v8, v8, v12 +; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -96,6 +134,14 @@ define @sabd_s_promoted_ops( %a, %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -111,6 +157,14 @@ define @sabd_d( %a, %b) ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_d: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; ZVABD-NEXT: vmin.vv v12, v8, v10 +; ZVABD-NEXT: vmax.vv v8, v8, v10 +; ZVABD-NEXT: vsub.vv v8, v8, v12 +; ZVABD-NEXT: ret %a.sext = sext %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -129,6 +183,16 @@ define @sabd_d_promoted_ops( %a, %a to %b.sext = sext %b to %sub = sub %a.sext, %b.sext @@ -148,6 +212,12 @@ define @uabd_b( %a, %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -164,6 +234,14 @@ define @uabd_b_promoted_ops( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -179,6 +257,12 @@ define @uabd_h( %a, %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -197,6 +281,14 @@ define @uabd_h_promoted_ops( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -212,6 +304,14 @@ define @uabd_s( %a, %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; ZVABD-NEXT: vminu.vv v12, v8, v10 +; ZVABD-NEXT: vmaxu.vv v8, v8, v10 +; ZVABD-NEXT: vsub.vv v8, v8, v12 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -230,6 +330,14 @@ define @uabd_s_promoted_ops( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -245,6 +353,14 @@ define @uabd_d( %a, %b) ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_d: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; ZVABD-NEXT: vminu.vv v12, v8, v10 +; ZVABD-NEXT: vmaxu.vv v8, v8, v10 +; ZVABD-NEXT: vsub.vv v8, v8, v12 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -263,6 +379,16 @@ define @uabd_d_promoted_ops( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -281,6 +407,15 @@ define @uabd_non_matching_extension( %a, %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -302,6 +437,15 @@ define @uabd_non_matching_promoted_ops( %a, ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_non_matching_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v10, v8 +; ZVABD-NEXT: vabdu.vv v10, v10, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v10 +; ZVABD-NEXT: ret %a.zext = zext %a to %b.zext = zext %b to %sub = sub %a.zext, %b.zext @@ -321,6 +465,16 @@ define @uabd_non_matching_promotion( %a, %a to %b.zext = sext %b to %sub = sub %a.zext, %b.zext @@ -331,3 +485,5 @@ define @uabd_non_matching_promotion( %a, @vabs_nxv1i16( %v) { ; CHECK-LABEL: vabs_nxv1i16: @@ -9,6 +13,12 @@ define @vabs_nxv1i16( %v) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv1i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, mf4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv1i16( %v, i1 false) ret %r } @@ -20,6 +30,12 @@ define @vabs_nxv2i16( %v) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv2i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv2i16( %v, i1 false) ret %r } @@ -31,6 +47,12 @@ define @vabs_nxv4i16( %v) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv4i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv4i16( %v, i1 false) ret %r } @@ -42,6 +64,12 @@ define @vabs_nxv8i16( %v) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv8i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv8i16( %v, i1 false) ret %r } @@ -53,6 +81,12 @@ define @vabs_nxv16i16( %v) { ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv16i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv16i16( %v, i1 false) ret %r } @@ -64,6 +98,12 @@ define @vabs_nxv32i16( %v) { ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv32i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e16, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv32i16( %v, i1 false) ret %r } @@ -75,6 +115,12 @@ define @vabs_nxv1i32( %v) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv1i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv1i32( %v, i1 false) ret %r } @@ -86,6 +132,12 @@ define @vabs_nxv2i32( %v) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv2i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv2i32( %v, i1 false) ret %r } @@ -97,6 +149,12 @@ define @vabs_nxv4i32( %v) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv4i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv4i32( %v, i1 false) ret %r } @@ -108,6 +166,12 @@ define @vabs_nxv8i32( %v) { ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv8i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv8i32( %v, i1 false) ret %r } @@ -119,6 +183,12 @@ define @vabs_nxv16i32( %v) { ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv16i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e32, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv16i32( %v, i1 false) ret %r } @@ -130,6 +200,12 @@ define @vabs_nxv1i64( %v) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv1i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv1i64( %v, i1 false) ret %r } @@ -141,6 +217,12 @@ define @vabs_nxv2i64( %v) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv2i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv2i64( %v, i1 false) ret %r } @@ -152,6 +234,12 @@ define @vabs_nxv4i64( %v) { ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv4i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e64, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv4i64( %v, i1 false) ret %r } @@ -163,6 +251,12 @@ define @vabs_nxv8i64( %v) { ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vabs_nxv8i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %r = call @llvm.abs.nxv8i64( %v, i1 false) ret %r } diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll index 5b215c5173211..684c9abb37353 100644 --- a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll @@ -3,6 +3,10 @@ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+experimental-zvabd -target-abi=ilp32d \ +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD +; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+experimental-zvabd -target-abi=lp64d \ +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD define @vp_abs_nxv1i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv1i8: @@ -11,6 +15,12 @@ define @vp_abs_nxv1i8( %va, ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv1i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv1i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -22,6 +32,12 @@ define @vp_abs_nxv1i8_unmasked( %va, i32 zero ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv1i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv1i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -33,6 +49,12 @@ define @vp_abs_nxv2i8( %va, ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv2i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv2i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -44,6 +66,12 @@ define @vp_abs_nxv2i8_unmasked( %va, i32 zero ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv2i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv2i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -55,6 +83,12 @@ define @vp_abs_nxv4i8( %va, ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv4i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv4i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -66,6 +100,12 @@ define @vp_abs_nxv4i8_unmasked( %va, i32 zero ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv4i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv4i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -77,6 +117,12 @@ define @vp_abs_nxv8i8( %va, ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv8i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv8i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -88,6 +134,12 @@ define @vp_abs_nxv8i8_unmasked( %va, i32 zero ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv8i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv8i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -99,6 +151,12 @@ define @vp_abs_nxv16i8( %va, @llvm.vp.abs.nxv16i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -110,6 +168,12 @@ define @vp_abs_nxv16i8_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv16i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv16i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -121,6 +185,12 @@ define @vp_abs_nxv32i8( %va, @llvm.vp.abs.nxv32i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -132,6 +202,12 @@ define @vp_abs_nxv32i8_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv32i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv32i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -143,6 +219,12 @@ define @vp_abs_nxv64i8( %va, @llvm.vp.abs.nxv64i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -154,6 +236,12 @@ define @vp_abs_nxv64i8_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv64i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv64i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -165,6 +253,12 @@ define @vp_abs_nxv1i16( %va, @llvm.vp.abs.nxv1i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -176,6 +270,12 @@ define @vp_abs_nxv1i16_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv1i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv1i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -187,6 +287,12 @@ define @vp_abs_nxv2i16( %va, @llvm.vp.abs.nxv2i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -198,6 +304,12 @@ define @vp_abs_nxv2i16_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv2i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv2i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -209,6 +321,12 @@ define @vp_abs_nxv4i16( %va, @llvm.vp.abs.nxv4i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -220,6 +338,12 @@ define @vp_abs_nxv4i16_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv4i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv4i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -231,6 +355,12 @@ define @vp_abs_nxv8i16( %va, @llvm.vp.abs.nxv8i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -242,6 +372,12 @@ define @vp_abs_nxv8i16_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv8i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv8i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -253,6 +389,12 @@ define @vp_abs_nxv16i16( %va, @llvm.vp.abs.nxv16i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -264,6 +406,12 @@ define @vp_abs_nxv16i16_unmasked( %va, i3 ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv16i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv16i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -275,6 +423,12 @@ define @vp_abs_nxv32i16( %va, @llvm.vp.abs.nxv32i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -286,6 +440,12 @@ define @vp_abs_nxv32i16_unmasked( %va, i3 ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv32i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv32i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -297,6 +457,12 @@ define @vp_abs_nxv1i32( %va, @llvm.vp.abs.nxv1i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -308,6 +474,12 @@ define @vp_abs_nxv1i32_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv1i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv1i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -319,6 +491,12 @@ define @vp_abs_nxv2i32( %va, @llvm.vp.abs.nxv2i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -330,6 +508,12 @@ define @vp_abs_nxv2i32_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv2i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv2i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -341,6 +525,12 @@ define @vp_abs_nxv4i32( %va, @llvm.vp.abs.nxv4i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -352,6 +542,12 @@ define @vp_abs_nxv4i32_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv4i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv4i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -363,6 +559,12 @@ define @vp_abs_nxv8i32( %va, @llvm.vp.abs.nxv8i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -374,6 +576,12 @@ define @vp_abs_nxv8i32_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv8i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv8i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -385,6 +593,12 @@ define @vp_abs_nxv16i32( %va, @llvm.vp.abs.nxv16i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -396,6 +610,12 @@ define @vp_abs_nxv16i32_unmasked( %va, i3 ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv16i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv16i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -407,6 +627,12 @@ define @vp_abs_nxv1i64( %va, @llvm.vp.abs.nxv1i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -418,6 +644,12 @@ define @vp_abs_nxv1i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv1i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv1i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -429,6 +661,12 @@ define @vp_abs_nxv2i64( %va, @llvm.vp.abs.nxv2i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -440,6 +678,12 @@ define @vp_abs_nxv2i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv2i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv2i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -451,6 +695,12 @@ define @vp_abs_nxv4i64( %va, @llvm.vp.abs.nxv4i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -462,6 +712,12 @@ define @vp_abs_nxv4i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv4i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv4i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -473,6 +729,12 @@ define @vp_abs_nxv7i64( %va, @llvm.vp.abs.nxv7i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -484,6 +746,12 @@ define @vp_abs_nxv7i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv7i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv7i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -495,6 +763,12 @@ define @vp_abs_nxv8i64( %va, @llvm.vp.abs.nxv8i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -506,6 +780,12 @@ define @vp_abs_nxv8i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv8i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv8i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -534,6 +814,28 @@ define @vp_abs_nxv16i64( %va, @llvm.vp.abs.nxv16i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -557,6 +859,23 @@ define @vp_abs_nxv16i64_unmasked( %va, i3 ; CHECK-NEXT: vrsub.vi v24, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v24 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_nxv16i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: csrr a1, vlenb +; ZVABD-NEXT: sub a2, a0, a1 +; ZVABD-NEXT: sltu a3, a0, a2 +; ZVABD-NEXT: addi a3, a3, -1 +; ZVABD-NEXT: and a2, a3, a2 +; ZVABD-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v16, v16 +; ZVABD-NEXT: bltu a0, a1, .LBB47_2 +; ZVABD-NEXT: # %bb.1: +; ZVABD-NEXT: mv a0, a1 +; ZVABD-NEXT: .LBB47_2: +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call @llvm.vp.abs.nxv16i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir index cb1aebf0f95dd..c733ddf591c4b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir +++ b/llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir @@ -40,7 +40,7 @@ body: | ; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, killed renamable $x10, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) + ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, killed renamable $x10, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) ; CHECK-NEXT: $x10 = PseudoReadVLENB ; CHECK-NEXT: $x10 = SUB $x8, killed $x10 ; CHECK-NEXT: $x10 = ADDI killed $x10, -2048 diff --git a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll index 9b7d9736d9835..59b9e0b415b0c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll +++ b/llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll @@ -23,9 +23,9 @@ define @test(ptr %addr, i64 %vl) { ; CHECK-NEXT: add a2, a0, a2 ; CHECK-NEXT: vs1r.v v8, (a0) ; CHECK-NEXT: vs1r.v v9, (a2) -; CHECK-NEXT: vl1re64.v v8, (a2) -; CHECK-NEXT: vl1re64.v v9, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma +; CHECK-NEXT: vle64.v v8, (a2) +; CHECK-NEXT: vle64.v v9, (a0) ; CHECK-NEXT: vfadd.vv v8, v9, v8 ; CHECK-NEXT: csrrs a0, vlenb, zero ; CHECK-NEXT: slli a0, a0, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir b/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir index a1e45a6740d70..408d533f77074 100644 --- a/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir +++ b/llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.mir @@ -7,9 +7,9 @@ name: vcpop.m body: | bb.0: ; CHECK-LABEL: name: vcpop.m - ; CHECK: %allones:vr = PseudoVMSET_M_B64 $noreg, 0 /* e8 */ + ; CHECK: %allones:vr = PseudoVMSET_M_B64 $noreg /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY %allones - ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 $noreg, 21, 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 $noreg, 21 /* vl */, 0 /* e8 */ %allones:vr = PseudoVMSET_M_B64 $noreg, 0 $v0 = COPY %allones %2:gpr = PseudoVCPOP_M_B64_MASK $noreg, $v0, 21, 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir b/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir index 554cf17eb79c5..0434fb9e3f930 100644 --- a/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir +++ b/llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir @@ -30,10 +30,10 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrnov0 = COPY $v1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrnov0 = COPY $v2 - ; CHECK-NEXT: [[PseudoVNMSUB_VV_M1_:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[PseudoVNMSUB_VV_M1_]], [[COPY1]], [[COPY2]], -1, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVNMSUB_VV_M1_]] - ; CHECK-NEXT: dead [[PseudoVSLL_VI_M1_:%[0-9]+]]:vr = PseudoVSLL_VI_M1 undef [[PseudoVSLL_VI_M1_]], [[PseudoVSLL_VI_M1_]], 11, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v0 = COPY [[PseudoVNMSUB_VV_M1_]] + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[COPY]], [[COPY1]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY [[COPY]] + ; CHECK-NEXT: dead [[COPY3:%[0-9]+]]:vr = PseudoVSLL_VI_M1 undef [[COPY3]], [[COPY3]], 11, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $v0 %0:vr = COPY $v0 %1:vrnov0 = COPY $v1 diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll index 20f397b694180..2ed155a491657 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll @@ -2504,7 +2504,7 @@ define @vp_ctlz_nxv1i9( %va, @vp_ctlz_nxv1i9( %va, @vp_ctpop_nxv1i9( %va, @vp_ctpop_nxv1i9( %va, @llvm.vp.ctpop.nxv1i9( %va, %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir index 6f223157094e9..d8cc861ccff8e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir +++ b/llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir @@ -88,7 +88,7 @@ body: | ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x10 ; CHECK-NEXT: $x2 = frame-setup ANDI $x2, -128 ; CHECK-NEXT: dead renamable $x15 = PseudoVSETIVLI 1, 72 /* e16, m1, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v25 = PseudoVMV_V_X_M1 undef $v25, killed renamable $x12, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v25 = PseudoVMV_V_X_M1 undef $v25, killed renamable $x12, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x10 = PseudoReadVLENB ; CHECK-NEXT: $x11 = ADDI $x0, 50 ; CHECK-NEXT: $x10 = MUL killed $x10, killed $x11 @@ -138,7 +138,7 @@ body: | ; CHECK-NEXT: $x10 = ADDI killed $x10, 161 ; CHECK-NEXT: renamable $v0 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8) ; CHECK-NEXT: $x10 = LD $x2, 8 :: (load (s64) from %stack.15) - ; CHECK-NEXT: renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg /* vl */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $x13 = PseudoVMV_X_S killed renamable $v0, 3 /* e8 */, implicit $vtype ; CHECK-NEXT: BLT killed renamable $x16, renamable $x27, %bb.2 ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll index 241f619b1133f..ba75f6e6421ad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll @@ -1462,8 +1462,8 @@ define void @store_extractelt_nxv8f64(ptr %x, ptr %p) { define void @store_vfmv_f_s_nxv8f64(ptr %x, ptr %p) { ; CHECK-LABEL: store_vfmv_f_s_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl1re64.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma +; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %a = load , ptr %x diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll index 0f26832cffdc8..6bfac12fa3b99 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+experimental-zvabd -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD,ZVABD-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+experimental-zvabd -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD,ZVABD-RV64 ; ; SABD ; @@ -14,6 +16,12 @@ define <8 x i8> @sabd_8b_as_16b(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_8b_as_16b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <8 x i8> %a to <8 x i16> %b.sext = sext <8 x i8> %b to <8 x i16> %sub = sub <8 x i16> %a.sext, %b.sext @@ -31,6 +39,12 @@ define <8 x i8> @sabd_8b_as_32b(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_8b_as_32b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <8 x i8> %a to <8 x i32> %b.sext = sext <8 x i8> %b to <8 x i32> %sub = sub <8 x i32> %a.sext, %b.sext @@ -48,6 +62,12 @@ define <16 x i8> @sabd_16b(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_16b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <16 x i8> %a to <16 x i16> %b.sext = sext <16 x i8> %b to <16 x i16> %sub = sub <16 x i16> %a.sext, %b.sext @@ -65,6 +85,12 @@ define <4 x i16> @sabd_4h(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_4h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <4 x i16> %a to <4 x i32> %b.sext = sext <4 x i16> %b to <4 x i32> %sub = sub <4 x i32> %a.sext, %b.sext @@ -84,6 +110,14 @@ define <4 x i16> @sabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_4h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <4 x i8> %a to <4 x i16> %b.sext = sext <4 x i8> %b to <4 x i16> %sub = sub <4 x i16> %a.sext, %b.sext @@ -100,6 +134,12 @@ define <8 x i16> @sabd_8h(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_8h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <8 x i16> %a to <8 x i32> %b.sext = sext <8 x i16> %b to <8 x i32> %sub = sub <8 x i32> %a.sext, %b.sext @@ -119,6 +159,14 @@ define <8 x i16> @sabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_8h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <8 x i8> %a to <8 x i16> %b.sext = sext <8 x i8> %b to <8 x i16> %sub = sub <8 x i16> %a.sext, %b.sext @@ -135,6 +183,14 @@ define <2 x i32> @sabd_2s(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_2s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <2 x i32> %a to <2 x i64> %b.sext = sext <2 x i32> %b to <2 x i64> %sub = sub <2 x i64> %a.sext, %b.sext @@ -154,6 +210,14 @@ define <2 x i32> @sabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) { ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_2s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, mf2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <2 x i16> %a to <2 x i32> %b.sext = sext <2 x i16> %b to <2 x i32> %sub = sub <2 x i32> %a.sext, %b.sext @@ -170,6 +234,14 @@ define <4 x i32> @sabd_4s(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_4s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <4 x i32> %a to <4 x i64> %b.sext = sext <4 x i32> %b to <4 x i64> %sub = sub <4 x i64> %a.sext, %b.sext @@ -189,6 +261,14 @@ define <4 x i32> @sabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_4s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vabd.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <4 x i16> %a to <4 x i32> %b.sext = sext <4 x i16> %b to <4 x i32> %sub = sub <4 x i32> %a.sext, %b.sext @@ -204,6 +284,14 @@ define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_2d: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.sext = sext <2 x i64> %a to <2 x i128> %b.sext = sext <2 x i64> %b to <2 x i128> %sub = sub <2 x i128> %a.sext, %b.sext @@ -223,6 +311,16 @@ define <2 x i64> @sabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_2d_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v9, v8, v10 +; ZVABD-NEXT: vsetvli zero, zero, e64, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.sext = sext <2 x i32> %a to <2 x i64> %b.sext = sext <2 x i32> %b to <2 x i64> %sub = sub <2 x i64> %a.sext, %b.sext @@ -243,6 +341,12 @@ define <8 x i8> @uabd_8b(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_8b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <8 x i8> %a to <8 x i16> %b.zext = zext <8 x i8> %b to <8 x i16> %sub = sub <8 x i16> %a.zext, %b.zext @@ -260,6 +364,12 @@ define <16 x i8> @uabd_16b(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_16b: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <16 x i8> %a to <16 x i16> %b.zext = zext <16 x i8> %b to <16 x i16> %sub = sub <16 x i16> %a.zext, %b.zext @@ -277,6 +387,12 @@ define <4 x i16> @uabd_4h(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_4h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <4 x i16> %a to <4 x i32> %b.zext = zext <4 x i16> %b to <4 x i32> %sub = sub <4 x i32> %a.zext, %b.zext @@ -296,6 +412,14 @@ define <4 x i16> @uabd_4h_promoted_ops(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_4h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <4 x i8> %a to <4 x i16> %b.zext = zext <4 x i8> %b to <4 x i16> %sub = sub <4 x i16> %a.zext, %b.zext @@ -312,6 +436,12 @@ define <8 x i16> @uabd_8h(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_8h: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <8 x i16> %a to <8 x i32> %b.zext = zext <8 x i16> %b to <8 x i32> %sub = sub <8 x i32> %a.zext, %b.zext @@ -331,6 +461,14 @@ define <8 x i16> @uabd_8h_promoted_ops(<8 x i8> %a, <8 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_8h_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <8 x i8> %a to <8 x i16> %b.zext = zext <8 x i8> %b to <8 x i16> %sub = sub <8 x i16> %a.zext, %b.zext @@ -347,6 +485,14 @@ define <2 x i32> @uabd_2s(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_2s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext <2 x i32> %a to <2 x i64> %b.zext = zext <2 x i32> %b to <2 x i64> %sub = sub <2 x i64> %a.zext, %b.zext @@ -366,6 +512,14 @@ define <2 x i32> @uabd_2s_promoted_ops(<2 x i16> %a, <2 x i16> %b) { ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_2s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e16, mf4, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, mf2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <2 x i16> %a to <2 x i32> %b.zext = zext <2 x i16> %b to <2 x i32> %sub = sub <2 x i32> %a.zext, %b.zext @@ -382,6 +536,14 @@ define <4 x i32> @uabd_4s(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_4s: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext <4 x i32> %a to <4 x i64> %b.zext = zext <4 x i32> %b to <4 x i64> %sub = sub <4 x i64> %a.zext, %b.zext @@ -401,6 +563,14 @@ define <4 x i32> @uabd_4s_promoted_ops(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_4s_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vabdu.vv v9, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <4 x i16> %a to <4 x i32> %b.zext = zext <4 x i16> %b to <4 x i32> %sub = sub <4 x i32> %a.zext, %b.zext @@ -416,6 +586,14 @@ define <2 x i64> @uabd_2d(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_2d: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a.zext = zext <2 x i64> %a to <2 x i128> %b.zext = zext <2 x i64> %b to <2 x i128> %sub = sub <2 x i128> %a.zext, %b.zext @@ -435,6 +613,16 @@ define <2 x i64> @uabd_2d_promoted_ops(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vzext.vf2 v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_2d_promoted_ops: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v9, v8, v10 +; ZVABD-NEXT: vsetvli zero, zero, e64, m1, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v9 +; ZVABD-NEXT: ret %a.zext = zext <2 x i32> %a to <2 x i64> %b.zext = zext <2 x i32> %b to <2 x i64> %sub = sub <2 x i64> %a.zext, %b.zext @@ -451,6 +639,13 @@ define <16 x i8> @uabd_v16i8_nuw(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_v16i8_nuw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vsub.vv v8, v8, v9 +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %sub = sub nuw <16 x i8> %a, %b %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %sub, i1 true) ret <16 x i8> %abs @@ -465,6 +660,13 @@ define <8 x i16> @uabd_v8i16_nuw(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_v8i16_nuw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vsub.vv v8, v8, v9 +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %sub = sub nuw <8 x i16> %a, %b %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true) ret <8 x i16> %abs @@ -479,6 +681,13 @@ define <4 x i32> @uabd_v4i32_nuw(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_v4i32_nuw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vsub.vv v8, v8, v9 +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %sub = sub nuw <4 x i32> %a, %b %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) ret <4 x i32> %abs @@ -493,6 +702,13 @@ define <2 x i64> @uabd_v2i64_nuw(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: uabd_v2i64_nuw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vsub.vv v8, v8, v9 +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %sub = sub nuw <2 x i64> %a, %b %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) ret <2 x i64> %abs @@ -507,6 +723,12 @@ define <16 x i8> @sabd_v16i8_nsw(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_v16i8_nsw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nsw <16 x i8> %a, %b %abs = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %sub, i1 true) ret <16 x i8> %abs @@ -521,6 +743,12 @@ define <8 x i16> @sabd_v8i16_nsw(<8 x i16> %a, <8 x i16> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_v8i16_nsw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %sub = sub nsw <8 x i16> %a, %b %abs = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %sub, i1 true) ret <8 x i16> %abs @@ -535,6 +763,14 @@ define <4 x i32> @sabd_v4i32_nsw(<4 x i32> %a, <4 x i32> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_v4i32_nsw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %sub = sub nsw <4 x i32> %a, %b %abs = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %sub, i1 true) ret <4 x i32> %abs @@ -549,6 +785,14 @@ define <2 x i64> @sabd_v2i64_nsw(<2 x i64> %a, <2 x i64> %b) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sabd_v2i64_nsw: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %sub = sub nsw <2 x i64> %a, %b %abs = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %sub, i1 true) ret <2 x i64> %abs @@ -563,6 +807,12 @@ define <16 x i8> @smaxmin_v16i8(<16 x i8> %0, <16 x i8> %1) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: smaxmin_v16i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <16 x i8> @llvm.smax.v16i8(<16 x i8> %0, <16 x i8> %1) %b = tail call <16 x i8> @llvm.smin.v16i8(<16 x i8> %0, <16 x i8> %1) %sub = sub <16 x i8> %a, %b @@ -578,6 +828,12 @@ define <8 x i16> @smaxmin_v8i16(<8 x i16> %0, <8 x i16> %1) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: smaxmin_v8i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabd.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <8 x i16> @llvm.smax.v8i16(<8 x i16> %0, <8 x i16> %1) %b = tail call <8 x i16> @llvm.smin.v8i16(<8 x i16> %0, <8 x i16> %1) %sub = sub <8 x i16> %a, %b @@ -593,6 +849,14 @@ define <4 x i32> @smaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: smaxmin_v4i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %0, <4 x i32> %1) %b = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %0, <4 x i32> %1) %sub = sub <4 x i32> %a, %b @@ -608,6 +872,14 @@ define <2 x i64> @smaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: smaxmin_v2i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vmin.vv v10, v8, v9 +; ZVABD-NEXT: vmax.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a = tail call <2 x i64> @llvm.smax.v2i64(<2 x i64> %0, <2 x i64> %1) %b = tail call <2 x i64> @llvm.smin.v2i64(<2 x i64> %0, <2 x i64> %1) %sub = sub <2 x i64> %a, %b @@ -623,6 +895,12 @@ define <16 x i8> @umaxmin_v16i8(<16 x i8> %0, <16 x i8> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v16i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %0, <16 x i8> %1) %b = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %0, <16 x i8> %1) %sub = sub <16 x i8> %a, %b @@ -638,6 +916,12 @@ define <8 x i16> @umaxmin_v8i16(<8 x i16> %0, <8 x i16> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v8i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <8 x i16> @llvm.umax.v8i16(<8 x i16> %0, <8 x i16> %1) %b = tail call <8 x i16> @llvm.umin.v8i16(<8 x i16> %0, <8 x i16> %1) %sub = sub <8 x i16> %a, %b @@ -653,6 +937,14 @@ define <4 x i32> @umaxmin_v4i32(<4 x i32> %0, <4 x i32> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v4i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %0, <4 x i32> %1) %b = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %0, <4 x i32> %1) %sub = sub <4 x i32> %a, %b @@ -668,6 +960,14 @@ define <2 x i64> @umaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v2i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vminu.vv v10, v8, v9 +; ZVABD-NEXT: vmaxu.vv v8, v8, v9 +; ZVABD-NEXT: vsub.vv v8, v8, v10 +; ZVABD-NEXT: ret %a = tail call <2 x i64> @llvm.umax.v2i64(<2 x i64> %0, <2 x i64> %1) %b = tail call <2 x i64> @llvm.umin.v2i64(<2 x i64> %0, <2 x i64> %1) %sub = sub <2 x i64> %a, %b @@ -683,6 +983,12 @@ define <16 x i8> @umaxmin_v16i8_com1(<16 x i8> %0, <16 x i8> %1) { ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: umaxmin_v16i8_com1: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: ret %a = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %0, <16 x i8> %1) %b = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %1, <16 x i8> %0) %sub = sub <16 x i8> %a, %b @@ -692,3 +998,5 @@ define <16 x i8> @umaxmin_v16i8_com1(<16 x i8> %0, <16 x i8> %1) { ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; RV32: {{.*}} ; RV64: {{.*}} +; ZVABD-RV32: {{.*}} +; ZVABD-RV64: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll index fa81e1f6f3514..3a6dc2ba9b9e5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll @@ -3,6 +3,10 @@ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+experimental-zvabd -target-abi=ilp32d \ +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD +; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+experimental-zvabd -target-abi=lp64d \ +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVABD define <2 x i8> @vp_abs_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v2i8: @@ -11,6 +15,12 @@ define <2 x i8> @vp_abs_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v2i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -22,6 +32,12 @@ define <2 x i8> @vp_abs_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v2i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -33,6 +49,12 @@ define <4 x i8> @vp_abs_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v4i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -44,6 +66,12 @@ define <4 x i8> @vp_abs_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v4i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -55,6 +83,12 @@ define <8 x i8> @vp_abs_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v8i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -66,6 +100,12 @@ define <8 x i8> @vp_abs_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v8i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -77,6 +117,12 @@ define <16 x i8> @vp_abs_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v16i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -88,6 +134,12 @@ define <16 x i8> @vp_abs_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v16i8_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e8, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -99,6 +151,12 @@ define <2 x i16> @vp_abs_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v2i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -110,6 +168,12 @@ define <2 x i16> @vp_abs_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v2i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -121,6 +185,12 @@ define <4 x i16> @vp_abs_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v4i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -132,6 +202,12 @@ define <4 x i16> @vp_abs_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v4i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -143,6 +219,12 @@ define <8 x i16> @vp_abs_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v8i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -154,6 +236,12 @@ define <8 x i16> @vp_abs_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v8i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -165,6 +253,12 @@ define <16 x i16> @vp_abs_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v16i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -176,6 +270,12 @@ define <16 x i16> @vp_abs_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v16i16_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -187,6 +287,12 @@ define <2 x i32> @vp_abs_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v2i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -198,6 +304,12 @@ define <2 x i32> @vp_abs_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v2i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -209,6 +321,12 @@ define <4 x i32> @vp_abs_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v4i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -220,6 +338,12 @@ define <4 x i32> @vp_abs_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v4i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -231,6 +355,12 @@ define <8 x i32> @vp_abs_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v8i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -242,6 +372,12 @@ define <8 x i32> @vp_abs_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v8i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -253,6 +389,12 @@ define <16 x i32> @vp_abs_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v16i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -264,6 +406,12 @@ define <16 x i32> @vp_abs_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v16i32_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -275,6 +423,12 @@ define <2 x i64> @vp_abs_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v2i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -286,6 +440,12 @@ define <2 x i64> @vp_abs_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v2i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -297,6 +457,12 @@ define <4 x i64> @vp_abs_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v4i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -308,6 +474,12 @@ define <4 x i64> @vp_abs_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v4i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m2, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -319,6 +491,12 @@ define <8 x i64> @vp_abs_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v8i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -330,6 +508,12 @@ define <8 x i64> @vp_abs_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v8i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m4, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -341,6 +525,12 @@ define <15 x i64> @vp_abs_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v15i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } @@ -352,6 +542,12 @@ define <15 x i64> @vp_abs_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v15i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -363,6 +559,12 @@ define <16 x i64> @vp_abs_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v16i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: ret %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -374,6 +576,12 @@ define <16 x i64> @vp_abs_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v16i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: ret %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -401,6 +609,27 @@ define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t ; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v32i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: li a2, 16 +; ZVABD-NEXT: vsetivli zero, 2, e8, mf4, ta, ma +; ZVABD-NEXT: vslidedown.vi v24, v0, 2 +; ZVABD-NEXT: mv a1, a0 +; ZVABD-NEXT: bltu a0, a2, .LBB34_2 +; ZVABD-NEXT: # %bb.1: +; ZVABD-NEXT: li a1, 16 +; ZVABD-NEXT: .LBB34_2: +; ZVABD-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8, v0.t +; ZVABD-NEXT: addi a1, a0, -16 +; ZVABD-NEXT: sltu a0, a0, a1 +; ZVABD-NEXT: addi a0, a0, -1 +; ZVABD-NEXT: and a0, a0, a1 +; ZVABD-NEXT: vmv1r.v v0, v24 +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v16, v16, v0.t +; ZVABD-NEXT: ret %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } @@ -425,6 +654,24 @@ define <32 x i64> @vp_abs_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v24, v16, 0 ; CHECK-NEXT: vmax.vv v16, v16, v24 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: vp_abs_v32i64_unmasked: +; ZVABD: # %bb.0: +; ZVABD-NEXT: li a2, 16 +; ZVABD-NEXT: mv a1, a0 +; ZVABD-NEXT: bltu a0, a2, .LBB35_2 +; ZVABD-NEXT: # %bb.1: +; ZVABD-NEXT: li a1, 16 +; ZVABD-NEXT: .LBB35_2: +; ZVABD-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: addi a1, a0, -16 +; ZVABD-NEXT: sltu a0, a0, a1 +; ZVABD-NEXT: addi a0, a0, -1 +; ZVABD-NEXT: and a0, a0, a1 +; ZVABD-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; ZVABD-NEXT: vabs.v v16, v16 +; ZVABD-NEXT: ret %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll index 847722ae6b8ab..05c2d101ea6bb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll @@ -1,6 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvabd -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=ZVABD +; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvabd -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=ZVABD define void @abs_v16i8(ptr %x) { ; CHECK-LABEL: abs_v16i8: @@ -11,6 +15,14 @@ define void @abs_v16i8(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v16i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vle8.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse8.v v8, (a0) +; ZVABD-NEXT: ret %a = load <16 x i8>, ptr %x %b = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 false) store <16 x i8> %b, ptr %x @@ -26,6 +38,14 @@ define void @abs_v8i16(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v8i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; ZVABD-NEXT: vle16.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse16.v v8, (a0) +; ZVABD-NEXT: ret %a = load <8 x i16>, ptr %x %b = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false) store <8 x i16> %b, ptr %x @@ -41,6 +61,14 @@ define void @abs_v6i16(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v6i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 6, e16, m1, ta, ma +; ZVABD-NEXT: vle16.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse16.v v8, (a0) +; ZVABD-NEXT: ret %a = load <6 x i16>, ptr %x %b = call <6 x i16> @llvm.abs.v6i16(<6 x i16> %a, i1 false) store <6 x i16> %b, ptr %x @@ -56,6 +84,14 @@ define void @abs_v4i32(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v4i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vle32.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse32.v v8, (a0) +; ZVABD-NEXT: ret %a = load <4 x i32>, ptr %x %b = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false) store <4 x i32> %b, ptr %x @@ -71,6 +107,14 @@ define void @abs_v2i64(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v2i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 2, e64, m1, ta, ma +; ZVABD-NEXT: vle64.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse64.v v8, (a0) +; ZVABD-NEXT: ret %a = load <2 x i64>, ptr %x %b = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %a, i1 false) store <2 x i64> %b, ptr %x @@ -87,6 +131,15 @@ define void @abs_v32i8(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v32i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: li a1, 32 +; ZVABD-NEXT: vsetvli zero, a1, e8, m2, ta, ma +; ZVABD-NEXT: vle8.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse8.v v8, (a0) +; ZVABD-NEXT: ret %a = load <32 x i8>, ptr %x %b = call <32 x i8> @llvm.abs.v32i8(<32 x i8> %a, i1 false) store <32 x i8> %b, ptr %x @@ -102,6 +155,14 @@ define void @abs_v16i16(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v16i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; ZVABD-NEXT: vle16.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse16.v v8, (a0) +; ZVABD-NEXT: ret %a = load <16 x i16>, ptr %x %b = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a, i1 false) store <16 x i16> %b, ptr %x @@ -117,6 +178,14 @@ define void @abs_v8i32(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v8i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; ZVABD-NEXT: vle32.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse32.v v8, (a0) +; ZVABD-NEXT: ret %a = load <8 x i32>, ptr %x %b = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false) store <8 x i32> %b, ptr %x @@ -132,6 +201,14 @@ define void @abs_v4i64(ptr %x) { ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v4i64: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; ZVABD-NEXT: vle64.v v8, (a0) +; ZVABD-NEXT: vabs.v v8, v8 +; ZVABD-NEXT: vse64.v v8, (a0) +; ZVABD-NEXT: ret %a = load <4 x i64>, ptr %x %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a, i1 false) store <4 x i64> %b, ptr %x @@ -149,6 +226,16 @@ define void @abs_v4i64_of_sext_v4i8(ptr %x) { ; CHECK-NEXT: vzext.vf8 v8, v10 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v4i64_of_sext_v4i8: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vle8.v v8, (a0) +; ZVABD-NEXT: vabs.v v10, v8 +; ZVABD-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; ZVABD-NEXT: vzext.vf8 v8, v10 +; ZVABD-NEXT: vse64.v v8, (a0) +; ZVABD-NEXT: ret %a = load <4 x i8>, ptr %x %a.ext = sext <4 x i8> %a to <4 x i64> %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false) @@ -167,6 +254,16 @@ define void @abs_v4i64_of_sext_v4i16(ptr %x) { ; CHECK-NEXT: vzext.vf4 v8, v10 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v4i64_of_sext_v4i16: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; ZVABD-NEXT: vle16.v v8, (a0) +; ZVABD-NEXT: vabs.v v10, v8 +; ZVABD-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; ZVABD-NEXT: vzext.vf4 v8, v10 +; ZVABD-NEXT: vse64.v v8, (a0) +; ZVABD-NEXT: ret %a = load <4 x i16>, ptr %x %a.ext = sext <4 x i16> %a to <4 x i64> %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false) @@ -185,6 +282,16 @@ define void @abs_v4i64_of_sext_v4i32(ptr %x) { ; CHECK-NEXT: vzext.vf2 v8, v10 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret +; +; ZVABD-LABEL: abs_v4i64_of_sext_v4i32: +; ZVABD: # %bb.0: +; ZVABD-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; ZVABD-NEXT: vle32.v v8, (a0) +; ZVABD-NEXT: vabs.v v10, v8 +; ZVABD-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; ZVABD-NEXT: vzext.vf2 v8, v10 +; ZVABD-NEXT: vse64.v v8, (a0) +; ZVABD-NEXT: ret %a = load <4 x i32>, ptr %x %a.ext = sext <4 x i32> %a to <4 x i64> %b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll index a4851e9838fbf..c41f2f7021d17 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll @@ -9,7 +9,7 @@ define <2 x double> @foo(<2 x double> %x, <2 x double> %y) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVFADD_VV_M1_E64_:%[0-9]+]]:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1_E64 $noreg, [[COPY1]], [[COPY]], 7, 2, 6 /* e64 */, 1 /* ta, mu */, implicit $frm + ; CHECK-NEXT: [[PseudoVFADD_VV_M1_E64_:%[0-9]+]]:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1_E64 $noreg, [[COPY1]], [[COPY]], 7 /* frm=dyn */, 2 /* vl */, 6 /* e64 */, 1 /* ta, mu */, implicit $frm ; CHECK-NEXT: $v8 = COPY [[PseudoVFADD_VV_M1_E64_]] ; CHECK-NEXT: PseudoRET implicit $v8 %1 = fadd fast <2 x double> %x, %y diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll index 9be93d5209121..ea791a155d3d6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -37,8 +37,7 @@ define <2 x i1> @fp2si_v2f32_v2i1(<2 x float> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %z = fptosi <2 x float> %x to <2 x i1> ret <2 x i1> %z @@ -71,8 +70,7 @@ define <2 x i1> @fp2ui_v2f32_v2i1(<2 x float> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %z = fptoui <2 x float> %x to <2 x i1> ret <2 x i1> %z @@ -111,8 +109,7 @@ define <3 x i1> @fp2si_v3f32_v3i1(<3 x float> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %z = fptosi <3 x float> %x to <3 x i1> ret <3 x i1> %z @@ -309,8 +306,7 @@ define <3 x i1> @fp2ui_v3f32_v3i1(<3 x float> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %z = fptoui <3 x float> %x to <3 x i1> ret <3 x i1> %z @@ -349,8 +345,7 @@ define <8 x i1> @fp2si_v8f32_v8i1(<8 x float> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 -; CHECK-NEXT: vand.vi v8, v10, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret %z = fptosi <8 x float> %x to <8 x i1> ret <8 x i1> %z @@ -361,8 +356,7 @@ define <8 x i1> @fp2ui_v8f32_v8i1(<8 x float> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 -; CHECK-NEXT: vand.vi v8, v10, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret %z = fptoui <8 x float> %x to <8 x i1> ret <8 x i1> %z @@ -462,7 +456,6 @@ define <2 x i1> @fp2si_v2bf16_v2i1(<2 x bfloat> %x) { ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %z = fptosi <2 x bfloat> %x to <2 x i1> @@ -475,7 +468,6 @@ define <2 x i1> @fp2ui_v2bf16_v2i1(<2 x bfloat> %x) { ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %z = fptoui <2 x bfloat> %x to <2 x i1> @@ -519,8 +511,7 @@ define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8 -; ZVFH-NEXT: vand.vi v8, v9, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v9, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: fp2si_v2f16_v2i1: @@ -528,7 +519,6 @@ define <2 x i1> @fp2si_v2f16_v2i1(<2 x half> %x) { ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %z = fptosi <2 x half> %x to <2 x i1> @@ -540,8 +530,7 @@ define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; ZVFH-NEXT: vand.vi v8, v9, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v9, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: fp2ui_v2f16_v2i1: @@ -549,7 +538,6 @@ define <2 x i1> @fp2ui_v2f16_v2i1(<2 x half> %x) { ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %z = fptoui <2 x half> %x to <2 x i1> @@ -597,8 +585,7 @@ define <2 x i1> @fp2si_v2f64_v2i1(<2 x double> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %z = fptosi <2 x double> %x to <2 x i1> ret <2 x i1> %z @@ -609,8 +596,7 @@ define <2 x i1> @fp2ui_v2f64_v2i1(<2 x double> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %z = fptoui <2 x double> %x to <2 x i1> ret <2 x i1> %z @@ -657,8 +643,7 @@ define <8 x i1> @fp2si_v8f64_v8i1(<8 x double> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 -; CHECK-NEXT: vand.vi v8, v12, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: ret %z = fptosi <8 x double> %x to <8 x i1> ret <8 x i1> %z @@ -669,8 +654,7 @@ define <8 x i1> @fp2ui_v8f64_v8i1(<8 x double> %x) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 -; CHECK-NEXT: vand.vi v8, v12, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: ret %z = fptoui <8 x double> %x to <8 x i1> ret <8 x i1> %z diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll index 287752759a06b..77c3c2269cbd2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll @@ -299,3 +299,28 @@ define <8 x i32> @vpselect_vpload2(<8 x i32> %passthru, ptr %p, <8 x i32> %x, <8 %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } + +define <8 x i32> @vpmerge_add(<8 x i32> %passthru, <8 x i32> %x, <8 x i32> %y, <8 x i1> %m, i32 zeroext %vl) { +; CHECK-LABEL: vpmerge_add: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: ret + %a = add <8 x i32> %x, %y + %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) + ret <8 x i32> %b +} + +; Negative test: Shouldn't fold vmerge into the load because we may increase vl. +define <8 x i32> @vpmerge_load(<8 x i32> %passthru, ptr %p, <8 x i1> %m, i32 zeroext %vl) { +; CHECK-LABEL: vpmerge_load: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, ma +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: ret + %a = load <8 x i32>, ptr %p + %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) + ret <8 x i32> %b +} diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll index 71c32f1473b7f..65010fdbdc2bb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefix=ZVABD +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+experimental-zvabd | FileCheck %s --check-prefix=ZVABD define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) { ; CHECK-LABEL: sad_4x8_as_i16: @@ -16,6 +18,18 @@ define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_4x8_as_i16: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vmv.s.x v9, zero +; ZVABD-NEXT: vsetvli zero, zero, e8, mf4, ta, ma +; ZVABD-NEXT: vwredsumu.vs v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, mf2, ta, ma +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %1 = zext <4 x i8> %a to <4 x i16> %3 = zext <4 x i8> %b to <4 x i16> @@ -38,6 +52,17 @@ define signext i32 @sad_4x8_as_i32(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vredsum.vs v8, v9, v8 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_4x8_as_i32: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 4, e8, mf4, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; ZVABD-NEXT: vzext.vf4 v9, v8 +; ZVABD-NEXT: vmv.s.x v8, zero +; ZVABD-NEXT: vredsum.vs v8, v9, v8 +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %1 = zext <4 x i8> %a to <4 x i32> %3 = zext <4 x i8> %b to <4 x i32> @@ -61,6 +86,18 @@ define signext i16 @sad_16x8_as_i16(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_16x8_as_i16: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vmv.s.x v9, zero +; ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; ZVABD-NEXT: vwredsumu.vs v8, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %1 = zext <16 x i8> %a to <16 x i16> %3 = zext <16 x i8> %b to <16 x i16> @@ -83,6 +120,17 @@ define signext i32 @sad_16x8_as_i32(<16 x i8> %a, <16 x i8> %b) { ; CHECK-NEXT: vredsum.vs v8, v8, v12 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_16x8_as_i32: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v12, v8, v9 +; ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; ZVABD-NEXT: vzext.vf4 v8, v12 +; ZVABD-NEXT: vmv.s.x v12, zero +; ZVABD-NEXT: vredsum.vs v8, v8, v12 +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %1 = zext <16 x i8> %a to <16 x i32> %3 = zext <16 x i8> %b to <16 x i32> @@ -135,6 +183,41 @@ define signext i32 @sad_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stridea ; CHECK-NEXT: vredsum.vs v8, v8, v12 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret +; +; ZVABD-LABEL: sad_2block_16xi8_as_i32: +; ZVABD: # %bb.0: # %entry +; ZVABD-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; ZVABD-NEXT: vle8.v v8, (a0) +; ZVABD-NEXT: vle8.v v9, (a1) +; ZVABD-NEXT: add a0, a0, a2 +; ZVABD-NEXT: add a1, a1, a3 +; ZVABD-NEXT: vle8.v v10, (a0) +; ZVABD-NEXT: vle8.v v11, (a1) +; ZVABD-NEXT: add a0, a0, a2 +; ZVABD-NEXT: add a1, a1, a3 +; ZVABD-NEXT: vle8.v v14, (a0) +; ZVABD-NEXT: vle8.v v15, (a1) +; ZVABD-NEXT: add a0, a0, a2 +; ZVABD-NEXT: add a1, a1, a3 +; ZVABD-NEXT: vabdu.vv v8, v8, v9 +; ZVABD-NEXT: vle8.v v9, (a0) +; ZVABD-NEXT: vabdu.vv v10, v10, v11 +; ZVABD-NEXT: vle8.v v11, (a1) +; ZVABD-NEXT: vwaddu.vv v12, v10, v8 +; ZVABD-NEXT: vabdu.vv v8, v14, v15 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vzext.vf2 v14, v8 +; ZVABD-NEXT: vsetvli zero, zero, e8, m1, ta, ma +; ZVABD-NEXT: vabdu.vv v16, v9, v11 +; ZVABD-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVABD-NEXT: vwaddu.vv v8, v14, v12 +; ZVABD-NEXT: vzext.vf2 v12, v16 +; ZVABD-NEXT: vwaddu.wv v8, v8, v12 +; ZVABD-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; ZVABD-NEXT: vmv.s.x v12, zero +; ZVABD-NEXT: vredsum.vs v8, v8, v12 +; ZVABD-NEXT: vmv.x.s a0, v8 +; ZVABD-NEXT: ret entry: %idx.ext8 = sext i32 %strideb to i64 %idx.ext = sext i32 %stridea to i64 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll index 36847c971d858..68b1338d92580 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll @@ -248,7 +248,7 @@ define <2 x i1> @icmp_sle_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 z ; CHECK-LABEL: icmp_sle_vv_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v8, v0 +; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: ret %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"sle", <2 x i1> %m, i32 %evl) ret <2 x i1> %v @@ -258,7 +258,7 @@ define <4 x i1> @icmp_sle_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 z ; CHECK-LABEL: icmp_sle_vv_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v8, v0 +; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: ret %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"sle", <4 x i1> %m, i32 %evl) ret <4 x i1> %v @@ -268,7 +268,7 @@ define <8 x i1> @icmp_sle_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 z ; CHECK-LABEL: icmp_sle_vv_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v8, v0 +; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: ret %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"sle", <8 x i1> %m, i32 %evl) ret <8 x i1> %v @@ -278,7 +278,7 @@ define <16 x i1> @icmp_sle_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, ; CHECK-LABEL: icmp_sle_vv_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v8, v0 +; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: ret %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"sle", <16 x i1> %m, i32 %evl) ret <16 x i1> %v @@ -288,7 +288,7 @@ define <2 x i1> @icmp_ule_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 z ; CHECK-LABEL: icmp_ule_vv_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: vmorn.mm v0, v8, v0 ; CHECK-NEXT: ret %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"ule", <2 x i1> %m, i32 %evl) ret <2 x i1> %v @@ -298,7 +298,7 @@ define <4 x i1> @icmp_ule_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 z ; CHECK-LABEL: icmp_ule_vv_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: vmorn.mm v0, v8, v0 ; CHECK-NEXT: ret %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"ule", <4 x i1> %m, i32 %evl) ret <4 x i1> %v @@ -308,7 +308,7 @@ define <8 x i1> @icmp_ule_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 z ; CHECK-LABEL: icmp_ule_vv_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: vmorn.mm v0, v8, v0 ; CHECK-NEXT: ret %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"ule", <8 x i1> %m, i32 %evl) ret <8 x i1> %v @@ -318,7 +318,7 @@ define <16 x i1> @icmp_ule_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, ; CHECK-LABEL: icmp_ule_vv_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: vmorn.mm v0, v8, v0 ; CHECK-NEXT: ret %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"ule", <16 x i1> %m, i32 %evl) ret <16 x i1> %v @@ -328,7 +328,7 @@ define <2 x i1> @icmp_sge_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 z ; CHECK-LABEL: icmp_sge_vv_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: vmorn.mm v0, v8, v0 ; CHECK-NEXT: ret %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"sge", <2 x i1> %m, i32 %evl) ret <2 x i1> %v @@ -338,7 +338,7 @@ define <4 x i1> @icmp_sge_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 z ; CHECK-LABEL: icmp_sge_vv_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: vmorn.mm v0, v8, v0 ; CHECK-NEXT: ret %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"sge", <4 x i1> %m, i32 %evl) ret <4 x i1> %v @@ -348,7 +348,7 @@ define <8 x i1> @icmp_sge_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 z ; CHECK-LABEL: icmp_sge_vv_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: vmorn.mm v0, v8, v0 ; CHECK-NEXT: ret %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"sge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v @@ -358,7 +358,7 @@ define <16 x i1> @icmp_sge_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, ; CHECK-LABEL: icmp_sge_vv_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: vmorn.mm v0, v8, v0 ; CHECK-NEXT: ret %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"sge", <16 x i1> %m, i32 %evl) ret <16 x i1> %v @@ -368,7 +368,7 @@ define <2 x i1> @icmp_uge_vv_v2i1(<2 x i1> %va, <2 x i1> %vb, <2 x i1> %m, i32 z ; CHECK-LABEL: icmp_uge_vv_v2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v8, v0 +; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: ret %v = call <2 x i1> @llvm.vp.icmp.v2i1(<2 x i1> %va, <2 x i1> %vb, metadata !"uge", <2 x i1> %m, i32 %evl) ret <2 x i1> %v @@ -378,7 +378,7 @@ define <4 x i1> @icmp_uge_vv_v4i1(<4 x i1> %va, <4 x i1> %vb, <4 x i1> %m, i32 z ; CHECK-LABEL: icmp_uge_vv_v4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v8, v0 +; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: ret %v = call <4 x i1> @llvm.vp.icmp.v4i1(<4 x i1> %va, <4 x i1> %vb, metadata !"uge", <4 x i1> %m, i32 %evl) ret <4 x i1> %v @@ -388,7 +388,7 @@ define <8 x i1> @icmp_uge_vv_v8i1(<8 x i1> %va, <8 x i1> %vb, <8 x i1> %m, i32 z ; CHECK-LABEL: icmp_uge_vv_v8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v8, v0 +; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: ret %v = call <8 x i1> @llvm.vp.icmp.v8i1(<8 x i1> %va, <8 x i1> %vb, metadata !"uge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v @@ -398,7 +398,7 @@ define <16 x i1> @icmp_uge_vv_v16i1(<16 x i1> %va, <16 x i1> %vb, <16 x i1> %m, ; CHECK-LABEL: icmp_uge_vv_v16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: vmxnor.mm v0, v8, v0 +; CHECK-NEXT: vmorn.mm v0, v0, v8 ; CHECK-NEXT: ret %v = call <16 x i1> @llvm.vp.icmp.v16i1(<16 x i1> %va, <16 x i1> %vb, metadata !"uge", <16 x i1> %m, i32 %evl) ret <16 x i1> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll index 6bea222ffb90e..d9ed69830e25f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll @@ -7,11 +7,12 @@ define <8 x i7> @vdiv_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vdiv_vv_v8i7: ; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vadd.vv v9, v9, v9 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t -; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t ; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.sdiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll index 1a7874b2c8c6f..1b31d07bed0cc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll @@ -8,9 +8,10 @@ define <8 x i7> @vdivu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe ; CHECK-LABEL: vdivu_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 127 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vand.vx v9, v9, a1, v0.t -; CHECK-NEXT: vand.vx v8, v8, a1, v0.t ; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.udiv.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll index f5978de080082..8fc277c8d9dbe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll @@ -7,11 +7,12 @@ define <8 x i7> @vmax_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vmax_vv_v8i7: ; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vadd.vv v9, v9, v9 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t -; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.smax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll index 7450a70df66ba..67bd8862219de 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll @@ -8,9 +8,10 @@ define <8 x i7> @vmaxu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe ; CHECK-LABEL: vmaxu_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 127 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vand.vx v9, v9, a1, v0.t -; CHECK-NEXT: vand.vx v8, v8, a1, v0.t ; CHECK-NEXT: vmaxu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.umax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll index 31d19304c2909..3eb6c17f4caad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll @@ -7,11 +7,12 @@ define <8 x i7> @vmin_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vmin_vv_v8i7: ; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vadd.vv v9, v9, v9 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t -; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.smin.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll index dda69ec8a7d2e..8ff01cd6332e7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll @@ -8,9 +8,10 @@ define <8 x i7> @vminu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe ; CHECK-LABEL: vminu_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 127 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vand.vx v9, v9, a1, v0.t -; CHECK-NEXT: vand.vx v8, v8, a1, v0.t ; CHECK-NEXT: vminu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.umin.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) @@ -986,28 +987,59 @@ define <16 x i64> @vminu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; Test that split-legalization works as expected. -define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { -; CHECK-LABEL: vminu_vx_v32i64: -; CHECK: # %bb.0: -; CHECK-NEXT: li a2, 16 -; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; CHECK-NEXT: vslidedown.vi v24, v0, 2 -; CHECK-NEXT: mv a1, a0 -; CHECK-NEXT: bltu a0, a2, .LBB74_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: li a1, 16 -; CHECK-NEXT: .LBB74_2: -; CHECK-NEXT: li a2, -1 -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma -; CHECK-NEXT: vminu.vx v8, v8, a2, v0.t -; CHECK-NEXT: addi a1, a0, -16 -; CHECK-NEXT: sltu a0, a0, a1 -; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: and a0, a0, a1 -; CHECK-NEXT: vmv1r.v v0, v24 -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: vminu.vx v16, v16, a2, v0.t -; CHECK-NEXT: ret - %v = call <32 x i64> @llvm.vp.umin.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) +define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i64 %x, i32 zeroext %evl) { +; RV32-LABEL: vminu_vx_v32i64: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: sw a1, 12(sp) +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero +; RV32-NEXT: li a1, 16 +; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma +; RV32-NEXT: vslidedown.vi v7, v0, 2 +; RV32-NEXT: mv a0, a2 +; RV32-NEXT: bltu a2, a1, .LBB74_2 +; RV32-NEXT: # %bb.1: +; RV32-NEXT: li a0, 16 +; RV32-NEXT: .LBB74_2: +; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; RV32-NEXT: vminu.vv v8, v8, v24, v0.t +; RV32-NEXT: addi a0, a2, -16 +; RV32-NEXT: sltu a1, a2, a0 +; RV32-NEXT: addi a1, a1, -1 +; RV32-NEXT: and a0, a1, a0 +; RV32-NEXT: vmv1r.v v0, v7 +; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma +; RV32-NEXT: vminu.vv v16, v16, v24, v0.t +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: .cfi_def_cfa_offset 0 +; RV32-NEXT: ret +; +; RV64-LABEL: vminu_vx_v32i64: +; RV64: # %bb.0: +; RV64-NEXT: li a3, 16 +; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma +; RV64-NEXT: vslidedown.vi v24, v0, 2 +; RV64-NEXT: mv a2, a1 +; RV64-NEXT: bltu a1, a3, .LBB74_2 +; RV64-NEXT: # %bb.1: +; RV64-NEXT: li a2, 16 +; RV64-NEXT: .LBB74_2: +; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV64-NEXT: vminu.vx v8, v8, a0, v0.t +; RV64-NEXT: addi a2, a1, -16 +; RV64-NEXT: sltu a1, a1, a2 +; RV64-NEXT: addi a1, a1, -1 +; RV64-NEXT: and a1, a1, a2 +; RV64-NEXT: vmv1r.v v0, v24 +; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; RV64-NEXT: vminu.vx v16, v16, a0, v0.t +; RV64-NEXT: ret + %elt.head = insertelement <32 x i64> poison, i64 %x, i32 0 + %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer + %v = call <32 x i64> @llvm.vp.umin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll index 78eabfec4153e..63dc750ea4df5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll @@ -7,11 +7,12 @@ define <8 x i7> @vrem_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vrem_vv_v8i7: ; CHECK: # %bb.0: +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vadd.vv v9, v9, v9 +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vsra.vi v9, v9, 1 +; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t -; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t ; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.srem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll index 7ba66d61b13f8..bd9077e27bfd6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll @@ -8,9 +8,10 @@ define <8 x i7> @vremu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroe ; CHECK-LABEL: vremu_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 127 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vand.vx v9, v9, a1, v0.t -; CHECK-NEXT: vand.vx v8, v8, a1, v0.t ; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.urem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll index f2f9f90f386c0..b3ae863b70cb1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll @@ -179,13 +179,13 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3 define <256 x i8> @select_evl_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c) { ; CHECK-LABEL: select_evl_v256i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma ; CHECK-NEXT: vmv1r.v v7, v8 ; CHECK-NEXT: vmv1r.v v6, v0 +; CHECK-NEXT: addi a2, a1, 128 +; CHECK-NEXT: vle8.v v24, (a2) ; CHECK-NEXT: li a2, 128 -; CHECK-NEXT: addi a3, a1, 128 ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma -; CHECK-NEXT: vle8.v v24, (a3) ; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vmv1r.v v0, v7 ; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll index b97fa1d3a51ec..50dba4304ebdd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll @@ -29,7 +29,7 @@ define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) { ; RV32-NEXT: vslidedown.vi v10, v10, 2 ; RV32-NEXT: vand.vi v10, v10, 1 ; RV32-NEXT: vmsne.vi v0, v10, 0 -; RV32-NEXT: vsetvli zero, zero, e32, m2, tu, mu +; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32-NEXT: vle32.v v8, (a0), v0.t ; RV32-NEXT: vse32.v v8, (a3) ; RV32-NEXT: ret @@ -60,7 +60,7 @@ define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) { ; RV64-NEXT: vslidedown.vi v10, v10, 2 ; RV64-NEXT: vand.vi v10, v10, 1 ; RV64-NEXT: vmsne.vi v0, v10, 0 -; RV64-NEXT: vsetvli zero, zero, e32, m2, tu, mu +; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vle32.v v8, (a0), v0.t ; RV64-NEXT: vse32.v v8, (a3) ; RV64-NEXT: ret @@ -240,7 +240,7 @@ define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) { ; RV32-NEXT: vslidedown.vi v10, v10, 2 ; RV32-NEXT: vand.vi v10, v10, 1 ; RV32-NEXT: vmsne.vi v0, v10, 0 -; RV32-NEXT: vsetvli zero, zero, e32, m2, tu, mu +; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV32-NEXT: vle32.v v8, (a0), v0.t ; RV32-NEXT: vse32.v v8, (a3) ; RV32-NEXT: ret @@ -271,7 +271,7 @@ define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) { ; RV64-NEXT: vslidedown.vi v10, v10, 2 ; RV64-NEXT: vand.vi v10, v10, 1 ; RV64-NEXT: vmsne.vi v0, v10, 0 -; RV64-NEXT: vsetvli zero, zero, e32, m2, tu, mu +; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; RV64-NEXT: vle32.v v8, (a0), v0.t ; RV64-NEXT: vse32.v v8, (a3) ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll index 7730d6e5e1312..8f0cae45201e9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll @@ -8,8 +8,9 @@ define <8 x i7> @vsll_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex ; CHECK-LABEL: vsll_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 127 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vand.vx v9, v9, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vand.vx v9, v9, a1, v0.t ; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.shl.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll index 1d0c3a6937b54..f4172c8eb4f92 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll @@ -8,10 +8,11 @@ define <8 x i7> @vsra_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex ; CHECK-LABEL: vsra_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 127 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vsra.vi v8, v8, 1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vand.vx v9, v9, a1, v0.t -; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t -; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t ; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.ashr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll index c8659b6d9739e..7de2e7e249434 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll @@ -8,9 +8,10 @@ define <8 x i7> @vsrl_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex ; CHECK-LABEL: vsrl_vv_v8i7: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 127 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; CHECK-NEXT: vand.vx v9, v9, a1 +; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: vand.vx v9, v9, a1, v0.t -; CHECK-NEXT: vand.vx v8, v8, a1, v0.t ; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %v = call <8 x i7> @llvm.vp.lshr.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll b/llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll index b1b8aac29b058..f448c9fd9d839 100644 --- a/llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll +++ b/llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll @@ -12,7 +12,7 @@ define i64 @test( %0) nounwind { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.a, 0 - ; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], killed [[ADDI]], 1, 6 /* e64 */ + ; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], killed [[ADDI]], 1 /* vl */, 6 /* e64 */ :: (store unknown-size into %ir.b, align 8) ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load (s64) from %ir.a) ; CHECK-NEXT: $x10 = COPY [[LD]] ; CHECK-NEXT: PseudoRET implicit $x10 diff --git a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll index 736dd1225da88..576753d1d7821 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll @@ -205,8 +205,8 @@ define @fshr_v64i8( %a, ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; CHECK-NEXT: addi a2, sp, 16 ; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vsll.vi v16, v8, 1, v0.t ; CHECK-NEXT: vnot.v v8, v24, v0.t ; CHECK-NEXT: vand.vi v8, v8, 7, v0.t @@ -238,8 +238,8 @@ define @fshl_v64i8( %a, ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; CHECK-NEXT: addi a2, sp, 16 ; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t ; CHECK-NEXT: vnot.v v8, v24, v0.t ; CHECK-NEXT: vand.vi v8, v8, 7, v0.t @@ -431,8 +431,8 @@ define @fshr_v32i16( %a, @fshl_v32i16( %a, @fshr_v16i32( %a, @fshl_v16i32( %a, @fshr_v7i64( %a, ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; CHECK-NEXT: addi a2, sp, 16 ; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: li a0, 63 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: li a0, 63 ; CHECK-NEXT: vand.vx v8, v24, a0, v0.t ; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t ; CHECK-NEXT: vnot.v v8, v24, v0.t @@ -840,7 +840,7 @@ define @fshl_v7i64( %a, ; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vmv8r.v v16, v8 -; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: li a0, 63 ; CHECK-NEXT: vand.vx v8, v24, a0, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t @@ -873,9 +873,9 @@ define @fshr_v8i64( %a, ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; CHECK-NEXT: addi a2, sp, 16 ; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: li a0, 63 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: li a0, 63 ; CHECK-NEXT: vand.vx v8, v24, a0, v0.t ; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t ; CHECK-NEXT: vnot.v v8, v24, v0.t @@ -909,7 +909,7 @@ define @fshl_v8i64( %a, ; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vmv8r.v v16, v8 -; CHECK-NEXT: vl8re64.v v24, (a0) +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: li a0, 63 ; CHECK-NEXT: vand.vx v8, v24, a0, v0.t ; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t @@ -1128,16 +1128,16 @@ define @fshr_v1i9( %a, %b, ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 511 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: vand.vx v10, v10, a1, v0.t +; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t +; CHECK-NEXT: vand.vx v10, v10, a1 ; CHECK-NEXT: li a0, 9 ; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t ; CHECK-NEXT: vadd.vi v10, v10, 7, v0.t ; CHECK-NEXT: vand.vi v11, v10, 15, v0.t -; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t ; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t +; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t ; CHECK-NEXT: vnot.v v10, v10, v0.t ; CHECK-NEXT: vand.vi v10, v10, 15, v0.t -; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t ; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret @@ -1150,16 +1150,16 @@ define @fshl_v1i9( %a, %b, ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 511 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: vand.vx v10, v10, a1, v0.t +; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t +; CHECK-NEXT: vand.vx v10, v10, a1 ; CHECK-NEXT: li a0, 9 +; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t ; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t -; CHECK-NEXT: vand.vi v11, v10, 15, v0.t -; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t -; CHECK-NEXT: vnot.v v10, v10, v0.t +; CHECK-NEXT: vnot.v v11, v10, v0.t +; CHECK-NEXT: vand.vi v11, v11, 15, v0.t +; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t ; CHECK-NEXT: vand.vi v10, v10, 15, v0.t -; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t -; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t -; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %res = call @llvm.vp.fshl.nxv1i9( %a, %b, %c, %m, i32 %evl) @@ -1170,13 +1170,13 @@ define @fshr_v1i4( %a, %b, ; CHECK-LABEL: fshr_v1i4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: vand.vi v10, v10, 15, v0.t +; CHECK-NEXT: vand.vi v10, v10, 15 ; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t ; CHECK-NEXT: vand.vi v9, v9, 15, v0.t ; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t -; CHECK-NEXT: vremu.vx v9, v10, a0, v0.t -; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret %trunca = call @llvm.vp.trunc.nxv1i4.nxv1i8( %a, %m, i32 zeroext %evl) @@ -1191,13 +1191,13 @@ define @fshl_v1i4( %a, %b, ; CHECK-LABEL: fshl_v1i4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: vand.vi v10, v10, 15, v0.t +; CHECK-NEXT: vand.vi v10, v10, 15 ; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t ; CHECK-NEXT: vand.vi v9, v9, 15, v0.t ; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t ; CHECK-NEXT: vor.vv v8, v8, v9, v0.t -; CHECK-NEXT: vremu.vx v9, v10, a0, v0.t -; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir b/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir index 8cc89ed5af104..cb39f242ba62d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir +++ b/llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir @@ -12,7 +12,7 @@ body: | ; MIR: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; MIR-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF ; MIR-NEXT: [[INIT_UNDEF:%[0-9]+]]:vr = INIT_UNDEF - ; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF1]], killed [[INIT_UNDEF]], 0, 0, 5 /* e32 */, 0 /* tu, mu */ + ; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF1]], killed [[INIT_UNDEF]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; MIR-NEXT: $v8 = COPY %1 ; MIR-NEXT: PseudoRET implicit $v8 %2:vr = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll b/llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll index c39630ae07e27..3ca9001fed24f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll +++ b/llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll @@ -12,7 +12,7 @@ define @vpload_nxv8i64(ptr %ptr, %m, i32 ze ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vmv0 = COPY [[COPY1]] - ; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK $noreg, [[COPY2]], [[COPY3]], [[COPY]], 6 /* e64 */, 1 /* ta, mu */ :: (load unknown-size from %ir.ptr, align 64) + ; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK $noreg, [[COPY2]], [[COPY3]], [[COPY]] /* vl */, 6 /* e64 */, 1 /* ta, mu */ :: (load unknown-size from %ir.ptr, align 64) ; CHECK-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_MASK]] ; CHECK-NEXT: PseudoRET implicit $v8m8 %load = call @llvm.vp.load.nxv8i64.p0(ptr %ptr, %m, i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/machine-combiner-subreg-verifier-error.mir b/llvm/test/CodeGen/RISCV/rvv/machine-combiner-subreg-verifier-error.mir index 76dfd4e746bea..507d0e3fce561 100644 --- a/llvm/test/CodeGen/RISCV/rvv/machine-combiner-subreg-verifier-error.mir +++ b/llvm/test/CodeGen/RISCV/rvv/machine-combiner-subreg-verifier-error.mir @@ -21,9 +21,9 @@ body: | ; CHECK-NEXT: [[DEF3:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[DEF4:%[0-9]+]]:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF5:%[0-9]+]]:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVSLIDEDOWN_VI_M8_:%[0-9]+]]:vrm8 = PseudoVSLIDEDOWN_VI_M8 $noreg, [[DEF2]], 26, 2, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 $noreg, [[DEF2]].sub_vrm1_0, killed [[DEF3]], 2, 5 /* e32 */, 1 /* ta, mu */ - ; CHECK-NEXT: [[PseudoVADD_VV_MF2_1:%[0-9]+]]:vr = PseudoVADD_VV_MF2 $noreg, [[PseudoVSLIDEDOWN_VI_M8_]].sub_vrm1_0, killed [[PseudoVADD_VV_MF2_]], 2, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVSLIDEDOWN_VI_M8_:%[0-9]+]]:vrm8 = PseudoVSLIDEDOWN_VI_M8 $noreg, [[DEF2]], 26, 2 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_MF2_:%[0-9]+]]:vr = PseudoVADD_VV_MF2 $noreg, [[DEF2]].sub_vrm1_0, killed [[DEF3]], 2 /* vl */, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVADD_VV_MF2_1:%[0-9]+]]:vr = PseudoVADD_VV_MF2 $noreg, [[PseudoVSLIDEDOWN_VI_M8_]].sub_vrm1_0, killed [[PseudoVADD_VV_MF2_]], 2 /* vl */, 5 /* e32 */, 1 /* ta, mu */ ; CHECK-NEXT: PseudoRET implicit $v8 %0:vrm4 = IMPLICIT_DEF %1:gprnox0 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir index ba5a05e89c506..6d595549e421d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir +++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir @@ -17,10 +17,10 @@ body: | ; CHECK: liveins: $v0, $v1, $v2, $v3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 undef renamable $v8, killed renamable $v2, 1, $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 undef renamable $v8, killed renamable $v2, 1, $v0, 1 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $v0 = COPY $v1, implicit $vtype - ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 undef renamable $v9, killed renamable $v3, 1, $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype - ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 undef renamable $v0, killed renamable $v8, killed renamable $v9, 1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 undef renamable $v9, killed renamable $v3, 1, $v0, 1 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 undef renamable $v0, killed renamable $v8, killed renamable $v9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v0 %0:vr = COPY $v0 %1:vr = COPY $v1 diff --git a/llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll index 0654fe8bd8d66..73c15a702071a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll @@ -13,7 +13,7 @@ define @foo( %x, @llvm.vp.fmul.nxv1f64( %x, %y, %m, i32 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/pr99782.ll b/llvm/test/CodeGen/RISCV/rvv/pr99782.ll index a4875c63da449..6c43155395dc0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/pr99782.ll +++ b/llvm/test/CodeGen/RISCV/rvv/pr99782.ll @@ -5,9 +5,9 @@ define void @vslidedown() { ; CHECK-LABEL: name: vslidedown ; CHECK: bb.0.entry: ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.v, 0 - ; CHECK-NEXT: [[PseudoVLE8_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE8_V_M8 $noreg, killed [[ADDI]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load () from %ir.v, align 1) + ; CHECK-NEXT: [[PseudoVLE8_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE8_V_M8 $noreg, killed [[ADDI]], -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ :: (load () from %ir.v, align 1) ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI %stack.1, 0 - ; CHECK-NEXT: PseudoVSE8_V_M8 killed [[PseudoVLE8_V_M8_]], killed [[ADDI1]], -1, 3 /* e8 */ :: (store () into %stack.1) + ; CHECK-NEXT: PseudoVSE8_V_M8 killed [[PseudoVLE8_V_M8_]], killed [[ADDI1]], -1 /* vl=VLMAX */, 3 /* e8 */ :: (store () into %stack.1) ; CHECK-NEXT: INLINEASM &"vadd.vv $0, $0, $0", 25 /* sideeffect mayload maystore attdialect */, 262166 /* mem:m */, %stack.0.v, 0, 262166 /* mem:m */, %stack.1, 0 ; CHECK-NEXT: PseudoRET entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir index 5a223580821b7..a17c88040cdf4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir @@ -7,8 +7,8 @@ body: | bb.0: ; CHECK-LABEL: name: avl_not_dominated ; CHECK: %evl:gprnox0 = ADDI $x0, 1 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %evl, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSE32_V_M1 %x, $noreg, %evl, 5 /* e32 */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %evl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSE32_V_M1 %x, $noreg, %evl /* vl */, 5 /* e32 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ %evl:gprnox0 = ADDI $x0, 1 PseudoVSE32_V_M1 %x:vr, $noreg, %evl, 5 /* e32 */ diff --git a/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir b/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir index feadfc627b5c0..f100897763bcc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir +++ b/llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir @@ -11,14 +11,14 @@ body: | ; CHECK: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: undef %1.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: undef [[PseudoVLE32_V_M2_:%[0-9]+]].sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: %pt2:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: %1.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 %pt2, $x10, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]].sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 %pt2, $x10, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: %pt3:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt3, $x10, 1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: undef early-clobber %5.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 undef %5.sub_vrm2_0, %1.sub_vrm2_0, 0, 1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: %5.sub_vrm2_1:vrn2m2 = COPY %1.sub_vrm2_1 - ; CHECK-NEXT: PseudoVSUXSEG2EI32_V_M2_M2 %5, $x10, [[PseudoVLE32_V_M2_]], 1, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE32_V_M2_1:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt3, $x10, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: undef early-clobber %5.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 undef %5.sub_vrm2_0, [[PseudoVLE32_V_M2_]].sub_vrm2_0, 0, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[COPY:%[0-9]+]].sub_vrm2_1:vrn2m2 = COPY [[PseudoVLE32_V_M2_]].sub_vrm2_1 + ; CHECK-NEXT: PseudoVSUXSEG2EI32_V_M2_M2 [[COPY]], $x10, [[PseudoVLE32_V_M2_1]], 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype %pt:vrm2 = IMPLICIT_DEF undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1, 5, 0 %pt2:vrm2 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir index aeab8f69f1602..3be74a7fce981 100644 --- a/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir +++ b/llvm/test/CodeGen/RISCV/rvv/regcoal-liveinterval-pruning-crash.mir @@ -11,7 +11,7 @@ body: | ; CHECK-NEXT: liveins: $x10, $v8, $v10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF - ; CHECK-NEXT: undef [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_2:vrn8m1 = PseudoVMV_V_I_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: undef [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_2:vrn8m1 = PseudoVMV_V_I_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]].sub_vrm1_6:vrn8m1 = COPY undef [[PseudoVMV_V_I_M1_]].sub_vrm1_2 ; CHECK-NEXT: BNE undef [[DEF]], $x0, %bb.3 ; CHECK-NEXT: PseudoBR %bb.1 @@ -27,8 +27,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: dead [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF - ; CHECK-NEXT: early-clobber [[PseudoVMV_V_I_M1_]].sub_vrm1_0:vrn8m1 = PseudoVRGATHER_VI_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_0, [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, 0, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: PseudoVSSEG6E8_V_M1_MASK [[PseudoVMV_V_I_M1_]].sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, undef [[DEF]], killed undef $v0, 0, 3 /* e8 */, implicit $vl, implicit $vtype :: (store unknown-size, align 1) + ; CHECK-NEXT: early-clobber [[PseudoVMV_V_I_M1_]].sub_vrm1_0:vrn8m1 = PseudoVRGATHER_VI_M1 undef [[PseudoVMV_V_I_M1_]].sub_vrm1_0, [[PseudoVMV_V_I_M1_]].sub_vrm1_2, 0, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSSEG6E8_V_M1_MASK [[PseudoVMV_V_I_M1_]].sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, undef [[DEF]], killed undef $v0, 0 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype :: (store unknown-size, align 1) ; CHECK-NEXT: PseudoRET bb.0: successors: %bb.3(0x40000000), %bb.1(0x40000000) diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir index c73c2004834db..4cd46a1b7d22a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir @@ -13,7 +13,7 @@ body: | ; CHECK-NEXT: %false:vrnov0 = COPY $v8 ; CHECK-NEXT: %true:vrnov0 = COPY $v9 ; CHECK-NEXT: %avl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */ + ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY %mask %false:vrnov0 = COPY $v8 %true:vrnov0 = COPY $v9 @@ -34,9 +34,9 @@ body: | ; CHECK-NEXT: %false:vrnov0 = COPY $noreg ; CHECK-NEXT: %true:vrnov0 = COPY $v9 ; CHECK-NEXT: %avl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */ + ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v0 = COPY %mask - ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ %pt:vrnov0 = COPY $v8 %false:vrnov0 = COPY $noreg %true:vrnov0 = COPY $v9 @@ -57,8 +57,8 @@ body: | ; CHECK-NEXT: %pt:vr = COPY $v8 ; CHECK-NEXT: %true:vrnov0 = COPY $v9 ; CHECK-NEXT: %avl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 0 /* e8 */ - ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ %false:vrnov0 = COPY $v8 %pt:vrnov0 = COPY $v8 %true:vrnov0 = COPY $v9 @@ -77,8 +77,8 @@ body: | ; CHECK-NEXT: %pt:vr = COPY $v8 ; CHECK-NEXT: %false:vrnov0 = COPY $v9 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, 4, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %pt, %true, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ %pt:vrnov0 = COPY $v8 %false:vrnov0 = COPY $v9 %mask:vmv0 = COPY $v0 @@ -97,8 +97,8 @@ body: | ; CHECK-NEXT: %pt:vrnov0 = COPY $v8 ; CHECK-NEXT: %false:vrnov0 = COPY $v9 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %pt, $noreg, $noreg, %mask, 4, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 8, 5 /* e32 */ + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %pt, $noreg, $noreg, %mask, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 8 /* vl */, 5 /* e32 */ %pt:vrnov0 = COPY $v8 %false:vrnov0 = COPY $v9 %mask:vmv0 = COPY $v0 @@ -117,8 +117,8 @@ body: | ; CHECK-NEXT: %pt:vrnov0 = COPY $v8 ; CHECK-NEXT: %false:vrnov0 = COPY $v9 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 8, 5 /* e32 */ + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, 8 /* vl */, 5 /* e32 */ %pt:vrnov0 = COPY $v8 %false:vrnov0 = COPY $v9 %mask:vmv0 = COPY $v0 @@ -135,7 +135,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %false:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */ %false:vrnov0 = COPY $v8 %mask:vmv0 = COPY $v0 %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, 4, 5 /* e32 */, 0 /* tu, mu */ @@ -152,10 +152,10 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %false:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, 4, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: - ; CHECK-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %true, %mask, 4, 5 /* e32 */ + ; CHECK-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %false, %true, %mask, 4 /* vl */, 5 /* e32 */ bb.0: liveins: $v8, $v0 %false:vrnov0 = COPY $v8 @@ -178,8 +178,8 @@ body: | ; CHECK-NEXT: %mask:vmv0 = COPY $v0 ; CHECK-NEXT: %avl1:gprnox0 = COPY $x8 ; CHECK-NEXT: %avl2:gprnox0 = COPY $x9 - ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, %avl1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, %avl2, 5 /* e32 */ + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %mask, %avl1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 %pt, %false, %true, %mask, %avl2 /* vl */, 5 /* e32 */ %pt:vrnov0 = COPY $v8 %false:vrnov0 = COPY $v9 %mask:vmv0 = COPY $v0 @@ -200,8 +200,8 @@ body: | ; CHECK-NEXT: %pt:vr = COPY $v8 ; CHECK-NEXT: %false:vrnov0 = COPY $v9 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVMV_V_V_M1_:%[0-9]+]]:vr = PseudoVMV_V_V_M1 %pt, %true, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %true:vrnov0 = PseudoVADD_VV_M1_MASK %false, $noreg, $noreg, %mask, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVMV_V_V_M1_:%[0-9]+]]:vr = PseudoVMV_V_V_M1 %pt, %true, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ %pt:vrnov0 = COPY $v8 %false:vrnov0 = COPY $v9 %mask:vmv0 = COPY $v0 diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll index fe074908a51a5..7fbbfb39a8253 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll @@ -82,7 +82,7 @@ define @fcmp_oeq_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_oeq_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_oeq_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_oeq_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -101,7 +101,7 @@ define @fcmp_oeq_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_oeq_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_oeq_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_oeq_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -183,7 +183,7 @@ define @fcmp_ogt_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_ogt_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_ogt_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_ogt_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -202,7 +202,7 @@ define @fcmp_ogt_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_ogt_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_ogt_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_ogt_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -284,7 +284,7 @@ define @fcmp_oge_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_oge_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_oge_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_oge_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -303,7 +303,7 @@ define @fcmp_oge_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_oge_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_oge_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_oge_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -385,7 +385,7 @@ define @fcmp_olt_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_olt_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_olt_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_olt_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -404,7 +404,7 @@ define @fcmp_olt_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_olt_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_olt_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_olt_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -486,7 +486,7 @@ define @fcmp_ole_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_ole_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_ole_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_ole_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -505,7 +505,7 @@ define @fcmp_ole_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_ole_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_ole_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_ole_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -599,7 +599,7 @@ define @fcmp_one_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_one_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_one_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_one_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -618,7 +618,7 @@ define @fcmp_one_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_one_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_one_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_one_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -720,7 +720,7 @@ define @fcmp_ord_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_ord_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_ord_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_ord_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -745,7 +745,7 @@ define @fcmp_ord_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_ord_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_ord_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_ord_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -846,7 +846,7 @@ define @fcmp_ueq_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_ueq_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_ueq_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_ueq_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -865,7 +865,7 @@ define @fcmp_ueq_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_ueq_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_ueq_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_ueq_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -953,7 +953,7 @@ define @fcmp_ugt_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_ugt_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_ugt_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_ugt_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -972,7 +972,7 @@ define @fcmp_ugt_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_ugt_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_ugt_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_ugt_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -1060,7 +1060,7 @@ define @fcmp_uge_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_uge_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_uge_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_uge_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1079,7 +1079,7 @@ define @fcmp_uge_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_uge_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_uge_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_uge_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -1167,7 +1167,7 @@ define @fcmp_ult_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_ult_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_ult_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_ult_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1186,7 +1186,7 @@ define @fcmp_ult_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_ult_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_ult_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_ult_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -1274,7 +1274,7 @@ define @fcmp_ule_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_ule_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_ule_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_ule_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1293,7 +1293,7 @@ define @fcmp_ule_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_ule_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_ule_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_ule_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -1375,7 +1375,7 @@ define @fcmp_une_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_une_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_une_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_une_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1394,7 +1394,7 @@ define @fcmp_une_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_une_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_une_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_une_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -1496,7 +1496,7 @@ define @fcmp_uno_fv_nxv8bf16( %va, bfloat ret %vc } -define @fcmp_uno_vv_nxv8bf16_nonans( %va, %vb) #0 { +define @fcmp_uno_vv_nxv8bf16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFBFMIN-LABEL: fcmp_uno_vv_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1521,7 +1521,7 @@ define @fcmp_uno_vv_nxv8bf16_nonans( %va, ret %vc } -define @fcmp_uno_vf_nxv8bf16_nonans( %va, bfloat %b) #0 { +define @fcmp_uno_vf_nxv8bf16_nonans( nofpclass(nan) %va, bfloat nofpclass(nan) %b) { ; ZVFBFMIN-LABEL: fcmp_uno_vf_nxv8bf16_nonans: ; ZVFBFMIN: # %bb.0: ; ZVFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0 @@ -1610,7 +1610,7 @@ define @fcmp_oeq_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_oeq_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_oeq_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_oeq_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1629,7 +1629,7 @@ define @fcmp_oeq_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_oeq_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_oeq_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_oeq_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1711,7 +1711,7 @@ define @fcmp_ogt_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_ogt_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_ogt_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_ogt_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1730,7 +1730,7 @@ define @fcmp_ogt_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_ogt_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_ogt_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_ogt_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1812,7 +1812,7 @@ define @fcmp_oge_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_oge_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_oge_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_oge_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1831,7 +1831,7 @@ define @fcmp_oge_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_oge_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_oge_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_oge_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1913,7 +1913,7 @@ define @fcmp_olt_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_olt_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_olt_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_olt_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -1932,7 +1932,7 @@ define @fcmp_olt_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_olt_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_olt_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_olt_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2014,7 +2014,7 @@ define @fcmp_ole_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_ole_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_ole_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_ole_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2033,7 +2033,7 @@ define @fcmp_ole_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_ole_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_ole_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_ole_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2127,7 +2127,7 @@ define @fcmp_one_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_one_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_one_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_one_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2146,7 +2146,7 @@ define @fcmp_one_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_one_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_one_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_one_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2248,7 +2248,7 @@ define @fcmp_ord_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_ord_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_ord_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_ord_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2273,7 +2273,7 @@ define @fcmp_ord_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_ord_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_ord_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_ord_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2374,7 +2374,7 @@ define @fcmp_ueq_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_ueq_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_ueq_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_ueq_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2393,7 +2393,7 @@ define @fcmp_ueq_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_ueq_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_ueq_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_ueq_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2481,7 +2481,7 @@ define @fcmp_ugt_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_ugt_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_ugt_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_ugt_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2500,7 +2500,7 @@ define @fcmp_ugt_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_ugt_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_ugt_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_ugt_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2588,7 +2588,7 @@ define @fcmp_uge_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_uge_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_uge_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_uge_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2607,7 +2607,7 @@ define @fcmp_uge_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_uge_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_uge_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_uge_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2695,7 +2695,7 @@ define @fcmp_ult_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_ult_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_ult_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_ult_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2714,7 +2714,7 @@ define @fcmp_ult_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_ult_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_ult_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_ult_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2802,7 +2802,7 @@ define @fcmp_ule_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_ule_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_ule_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_ule_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2821,7 +2821,7 @@ define @fcmp_ule_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_ule_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_ule_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_ule_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2903,7 +2903,7 @@ define @fcmp_une_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_une_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_une_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_une_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -2922,7 +2922,7 @@ define @fcmp_une_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_une_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_une_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_une_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -3024,7 +3024,7 @@ define @fcmp_uno_fv_nxv8f16( %va, half %b) ret %vc } -define @fcmp_uno_vv_nxv8f16_nonans( %va, %vb) #0 { +define @fcmp_uno_vv_nxv8f16_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; ZVFH-LABEL: fcmp_uno_vv_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -3049,7 +3049,7 @@ define @fcmp_uno_vv_nxv8f16_nonans( %va, %vc } -define @fcmp_uno_vf_nxv8f16_nonans( %va, half %b) #0 { +define @fcmp_uno_vf_nxv8f16_nonans( nofpclass(nan) %va, half nofpclass(nan) %b) { ; ZVFH-LABEL: fcmp_uno_vf_nxv8f16_nonans: ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma @@ -3111,7 +3111,7 @@ define @fcmp_oeq_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_oeq_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_oeq_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_oeq_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3121,7 +3121,7 @@ define @fcmp_oeq_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_oeq_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_oeq_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_oeq_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3167,7 +3167,7 @@ define @fcmp_ogt_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_ogt_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_ogt_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ogt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3177,7 +3177,7 @@ define @fcmp_ogt_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_ogt_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_ogt_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ogt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3223,7 +3223,7 @@ define @fcmp_oge_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_oge_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_oge_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_oge_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3233,7 +3233,7 @@ define @fcmp_oge_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_oge_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_oge_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_oge_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3279,7 +3279,7 @@ define @fcmp_olt_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_olt_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_olt_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_olt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3289,7 +3289,7 @@ define @fcmp_olt_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_olt_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_olt_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_olt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3335,7 +3335,7 @@ define @fcmp_ole_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_ole_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_ole_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ole_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3345,7 +3345,7 @@ define @fcmp_ole_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_ole_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_ole_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ole_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3397,7 +3397,7 @@ define @fcmp_one_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_one_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_one_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_one_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3407,7 +3407,7 @@ define @fcmp_one_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_one_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_one_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_one_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3461,7 +3461,7 @@ define @fcmp_ord_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_ord_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_ord_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ord_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3473,7 +3473,7 @@ define @fcmp_ord_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_ord_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_ord_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ord_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3528,7 +3528,7 @@ define @fcmp_ueq_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_ueq_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_ueq_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ueq_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3538,7 +3538,7 @@ define @fcmp_ueq_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_ueq_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_ueq_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3587,7 +3587,7 @@ define @fcmp_ugt_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_ugt_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_ugt_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ugt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3597,7 +3597,7 @@ define @fcmp_ugt_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_ugt_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_ugt_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ugt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3646,7 +3646,7 @@ define @fcmp_uge_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_uge_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_uge_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_uge_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3656,7 +3656,7 @@ define @fcmp_uge_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_uge_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_uge_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_uge_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3705,7 +3705,7 @@ define @fcmp_ult_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_ult_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_ult_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ult_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3715,7 +3715,7 @@ define @fcmp_ult_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_ult_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_ult_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ult_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3764,7 +3764,7 @@ define @fcmp_ule_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_ule_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_ule_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ule_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3774,7 +3774,7 @@ define @fcmp_ule_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_ule_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_ule_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ule_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3820,7 +3820,7 @@ define @fcmp_une_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_une_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_une_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_une_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3830,7 +3830,7 @@ define @fcmp_une_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_une_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_une_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_une_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3884,7 +3884,7 @@ define @fcmp_uno_fv_nxv8f32( %va, float %b ret %vc } -define @fcmp_uno_vv_nxv8f32_nonans( %va, %vb) #0 { +define @fcmp_uno_vv_nxv8f32_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_uno_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3896,7 +3896,7 @@ define @fcmp_uno_vv_nxv8f32_nonans( %va, < ret %vc } -define @fcmp_uno_vf_nxv8f32_nonans( %va, float %b) #0 { +define @fcmp_uno_vf_nxv8f32_nonans( nofpclass(nan) %va, float nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_uno_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma @@ -3945,7 +3945,7 @@ define @fcmp_oeq_fv_nxv8f64( %va, double ret %vc } -define @fcmp_oeq_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_oeq_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_oeq_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -3955,7 +3955,7 @@ define @fcmp_oeq_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_oeq_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_oeq_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_oeq_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4001,7 +4001,7 @@ define @fcmp_ogt_fv_nxv8f64( %va, double ret %vc } -define @fcmp_ogt_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_ogt_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ogt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4011,7 +4011,7 @@ define @fcmp_ogt_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_ogt_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_ogt_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ogt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4057,7 +4057,7 @@ define @fcmp_oge_fv_nxv8f64( %va, double ret %vc } -define @fcmp_oge_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_oge_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_oge_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4067,7 +4067,7 @@ define @fcmp_oge_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_oge_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_oge_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_oge_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4113,7 +4113,7 @@ define @fcmp_olt_fv_nxv8f64( %va, double ret %vc } -define @fcmp_olt_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_olt_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_olt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4123,7 +4123,7 @@ define @fcmp_olt_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_olt_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_olt_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_olt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4169,7 +4169,7 @@ define @fcmp_ole_fv_nxv8f64( %va, double ret %vc } -define @fcmp_ole_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_ole_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ole_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4179,7 +4179,7 @@ define @fcmp_ole_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_ole_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_ole_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ole_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4231,7 +4231,7 @@ define @fcmp_one_fv_nxv8f64( %va, double ret %vc } -define @fcmp_one_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_one_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_one_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4241,7 +4241,7 @@ define @fcmp_one_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_one_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_one_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_one_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4295,7 +4295,7 @@ define @fcmp_ord_fv_nxv8f64( %va, double ret %vc } -define @fcmp_ord_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_ord_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ord_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4307,7 +4307,7 @@ define @fcmp_ord_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_ord_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_ord_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ord_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4362,7 +4362,7 @@ define @fcmp_ueq_fv_nxv8f64( %va, double ret %vc } -define @fcmp_ueq_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_ueq_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ueq_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4372,7 +4372,7 @@ define @fcmp_ueq_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_ueq_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_ueq_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4421,7 +4421,7 @@ define @fcmp_ugt_fv_nxv8f64( %va, double ret %vc } -define @fcmp_ugt_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_ugt_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ugt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4431,7 +4431,7 @@ define @fcmp_ugt_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_ugt_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_ugt_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4480,7 +4480,7 @@ define @fcmp_uge_fv_nxv8f64( %va, double ret %vc } -define @fcmp_uge_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_uge_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_uge_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4490,7 +4490,7 @@ define @fcmp_uge_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_uge_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_uge_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_uge_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4539,7 +4539,7 @@ define @fcmp_ult_fv_nxv8f64( %va, double ret %vc } -define @fcmp_ult_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_ult_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ult_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4549,7 +4549,7 @@ define @fcmp_ult_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_ult_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_ult_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ult_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4598,7 +4598,7 @@ define @fcmp_ule_fv_nxv8f64( %va, double ret %vc } -define @fcmp_ule_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_ule_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_ule_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4608,7 +4608,7 @@ define @fcmp_ule_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_ule_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_ule_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_ule_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4654,7 +4654,7 @@ define @fcmp_une_fv_nxv8f64( %va, double ret %vc } -define @fcmp_une_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_une_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_une_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4664,7 +4664,7 @@ define @fcmp_une_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_une_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_une_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_une_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4718,7 +4718,7 @@ define @fcmp_uno_fv_nxv8f64( %va, double ret %vc } -define @fcmp_uno_vv_nxv8f64_nonans( %va, %vb) #0 { +define @fcmp_uno_vv_nxv8f64_nonans( nofpclass(nan) %va, nofpclass(nan) %vb) { ; CHECK-LABEL: fcmp_uno_vv_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4730,7 +4730,7 @@ define @fcmp_uno_vv_nxv8f64_nonans( %va, ret %vc } -define @fcmp_uno_vf_nxv8f64_nonans( %va, double %b) #0 { +define @fcmp_uno_vf_nxv8f64_nonans( nofpclass(nan) %va, double nofpclass(nan) %b) { ; CHECK-LABEL: fcmp_uno_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma @@ -4798,5 +4798,3 @@ define @fcmp_oeq_vf_nx16f64( %va) { %vc = fcmp oeq %va, zeroinitializer ret %vc } - -attributes #0 = { "no-nans-fp-math"="true" } diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll index 11e0691305e63..094c806f74856 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll @@ -428,7 +428,7 @@ define @icmp_sle_vv_nxv1i1( %va, @llvm.vp.icmp.nxv1i1( %va, %vb, metadata !"sle", %m, i32 %evl) ret %v @@ -438,7 +438,7 @@ define @icmp_sle_vv_nxv2i1( %va, @llvm.vp.icmp.nxv2i1( %va, %vb, metadata !"sle", %m, i32 %evl) ret %v @@ -448,7 +448,7 @@ define @icmp_sle_vv_nxv4i1( %va, @llvm.vp.icmp.nxv4i1( %va, %vb, metadata !"sle", %m, i32 %evl) ret %v @@ -458,7 +458,7 @@ define @icmp_sle_vv_nxv8i1( %va, @llvm.vp.icmp.nxv8i1( %va, %vb, metadata !"sle", %m, i32 %evl) ret %v @@ -468,7 +468,7 @@ define @icmp_sle_vv_nxv16i1( %va, @llvm.vp.icmp.nxv16i1( %va, %vb, metadata !"sle", %m, i32 %evl) ret %v @@ -478,7 +478,7 @@ define @icmp_sle_vv_nxv32i1( %va, @llvm.vp.icmp.nxv32i1( %va, %vb, metadata !"sle", %m, i32 %evl) ret %v @@ -488,7 +488,7 @@ define @icmp_sle_vv_nxv64i1( %va, @llvm.vp.icmp.nxv64i1( %va, %vb, metadata !"sle", %m, i32 %evl) ret %v @@ -498,7 +498,7 @@ define @icmp_ule_vv_nxv1i1( %va, @llvm.vp.icmp.nxv1i1( %va, %vb, metadata !"ule", %m, i32 %evl) ret %v @@ -508,7 +508,7 @@ define @icmp_ule_vv_nxv2i1( %va, @llvm.vp.icmp.nxv2i1( %va, %vb, metadata !"ule", %m, i32 %evl) ret %v @@ -518,7 +518,7 @@ define @icmp_ule_vv_nxv4i1( %va, @llvm.vp.icmp.nxv4i1( %va, %vb, metadata !"ule", %m, i32 %evl) ret %v @@ -528,7 +528,7 @@ define @icmp_ule_vv_nxv8i1( %va, @llvm.vp.icmp.nxv8i1( %va, %vb, metadata !"ule", %m, i32 %evl) ret %v @@ -538,7 +538,7 @@ define @icmp_ule_vv_nxv16i1( %va, @llvm.vp.icmp.nxv16i1( %va, %vb, metadata !"ule", %m, i32 %evl) ret %v @@ -548,7 +548,7 @@ define @icmp_ule_vv_nxv32i1( %va, @llvm.vp.icmp.nxv32i1( %va, %vb, metadata !"ule", %m, i32 %evl) ret %v @@ -558,7 +558,7 @@ define @icmp_ule_vv_nxv64i1( %va, @llvm.vp.icmp.nxv64i1( %va, %vb, metadata !"ule", %m, i32 %evl) ret %v @@ -568,7 +568,7 @@ define @icmp_sge_vv_nxv1i1( %va, @llvm.vp.icmp.nxv1i1( %va, %vb, metadata !"sge", %m, i32 %evl) ret %v @@ -578,7 +578,7 @@ define @icmp_sge_vv_nxv2i1( %va, @llvm.vp.icmp.nxv2i1( %va, %vb, metadata !"sge", %m, i32 %evl) ret %v @@ -588,7 +588,7 @@ define @icmp_sge_vv_nxv4i1( %va, @llvm.vp.icmp.nxv4i1( %va, %vb, metadata !"sge", %m, i32 %evl) ret %v @@ -598,7 +598,7 @@ define @icmp_sge_vv_nxv8i1( %va, @llvm.vp.icmp.nxv8i1( %va, %vb, metadata !"sge", %m, i32 %evl) ret %v @@ -608,7 +608,7 @@ define @icmp_sge_vv_nxv16i1( %va, @llvm.vp.icmp.nxv16i1( %va, %vb, metadata !"sge", %m, i32 %evl) ret %v @@ -618,7 +618,7 @@ define @icmp_sge_vv_nxv32i1( %va, @llvm.vp.icmp.nxv32i1( %va, %vb, metadata !"sge", %m, i32 %evl) ret %v @@ -628,7 +628,7 @@ define @icmp_sge_vv_nxv64i1( %va, @llvm.vp.icmp.nxv64i1( %va, %vb, metadata !"sge", %m, i32 %evl) ret %v @@ -638,7 +638,7 @@ define @icmp_uge_vv_nxv1i1( %va, @llvm.vp.icmp.nxv1i1( %va, %vb, metadata !"uge", %m, i32 %evl) ret %v @@ -648,7 +648,7 @@ define @icmp_uge_vv_nxv2i1( %va, @llvm.vp.icmp.nxv2i1( %va, %vb, metadata !"uge", %m, i32 %evl) ret %v @@ -658,7 +658,7 @@ define @icmp_uge_vv_nxv4i1( %va, @llvm.vp.icmp.nxv4i1( %va, %vb, metadata !"uge", %m, i32 %evl) ret %v @@ -668,7 +668,7 @@ define @icmp_uge_vv_nxv8i1( %va, @llvm.vp.icmp.nxv8i1( %va, %vb, metadata !"uge", %m, i32 %evl) ret %v @@ -678,7 +678,7 @@ define @icmp_uge_vv_nxv16i1( %va, @llvm.vp.icmp.nxv16i1( %va, %vb, metadata !"uge", %m, i32 %evl) ret %v @@ -688,7 +688,7 @@ define @icmp_uge_vv_nxv32i1( %va, @llvm.vp.icmp.nxv32i1( %va, %vb, metadata !"uge", %m, i32 %evl) ret %v @@ -698,7 +698,7 @@ define @icmp_uge_vv_nxv64i1( %va, @llvm.vp.icmp.nxv64i1( %va, %vb, metadata !"uge", %m, i32 %evl) ret %v diff --git a/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir b/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir index a4c638c165973..4cb3e0ee0976d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir +++ b/llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir @@ -124,10 +124,10 @@ body: | ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype - ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype - ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET %4:gprnox0 = COPY $x12 %3:gprnox0 = COPY $x11 @@ -171,11 +171,11 @@ body: | ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype - ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1544 /* e16, w4 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype - ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 4 /* w4 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 4 /* w4 */, implicit $frm, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET %4:gprnox0 = COPY $x12 %3:gprnox0 = COPY $x11 @@ -219,15 +219,15 @@ body: | ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype - ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1288 /* e16, w2 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype - ; CHECK-NEXT: PseudoSF_MM_F_F_ALT $t2, [[COPY3]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F_ALT $t2, [[COPY3]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype - ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET %4:gprnox0 = COPY $x12 %3:gprnox0 = COPY $x11 @@ -270,7 +270,7 @@ body: | ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1 /* w1 */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[PseudoSF_VTMV_V_T]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[PseudoSF_VTMV_V_T]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]], implicit $vtype @@ -314,11 +314,11 @@ body: | ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[COPY2]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[COPY2]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1 /* w1 */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M8_1:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[PseudoVADD_VV_M8_]], [[PseudoVADD_VV_M8_]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M8_1:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[PseudoVADD_VV_M8_]], [[PseudoVADD_VV_M8_]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_1]], implicit $vtype @@ -367,7 +367,7 @@ body: | ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY2]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY3]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype - ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY]], [[COPY]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY]], [[COPY]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY3]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: PseudoSF_VSTE16 [[COPY1]], [[COPY2]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll b/llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll index f087efcc5f57b..ba24f82983b82 100644 --- a/llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll +++ b/llvm/test/CodeGen/RISCV/rvv/strided-vpload-vpstore-output.ll @@ -15,7 +15,7 @@ define @strided_vpload_nxv1i8_i8(ptr %ptr, i8 signext %stride, ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vmv0 = COPY [[COPY1]] - ; CHECK-NEXT: [[PseudoVLSE8_V_MF8_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE8_V_MF8_MASK $noreg, [[COPY3]], [[COPY2]], [[COPY4]], [[COPY]], 3 /* e8 */, 1 /* ta, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: [[PseudoVLSE8_V_MF8_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE8_V_MF8_MASK $noreg, [[COPY3]], [[COPY2]], [[COPY4]], [[COPY]] /* vl */, 3 /* e8 */, 1 /* ta, mu */ :: (load unknown-size, align 1) ; CHECK-NEXT: $v8 = COPY [[PseudoVLSE8_V_MF8_MASK]] ; CHECK-NEXT: PseudoRET implicit $v8 %load = call @llvm.experimental.vp.strided.load.nxv1i8.p0.i8(ptr %ptr, i8 %stride, %m, i32 %evl) @@ -33,7 +33,7 @@ define void @strided_vpstore_nxv1i8_i8( %val, ptr %ptr, i8 sign ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vmv0 = COPY [[COPY1]] - ; CHECK-NEXT: PseudoVSSE8_V_MF8_MASK [[COPY4]], [[COPY3]], [[COPY2]], [[COPY5]], [[COPY]], 3 /* e8 */ :: (store unknown-size, align 1) + ; CHECK-NEXT: PseudoVSSE8_V_MF8_MASK [[COPY4]], [[COPY3]], [[COPY2]], [[COPY5]], [[COPY]] /* vl */, 3 /* e8 */ :: (store unknown-size, align 1) ; CHECK-NEXT: PseudoRET call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i8( %val, ptr %ptr, i8 %stride, %m, i32 %evl) ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir index 13419e3606baf..559dc12be3a3d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir +++ b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir @@ -11,7 +11,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF @@ -19,9 +19,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_1 - ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -49,7 +49,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF @@ -57,9 +57,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_0 - ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -87,7 +87,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF @@ -95,9 +95,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_3 - ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -125,7 +125,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF @@ -133,9 +133,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -163,15 +163,15 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_1 - ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG1]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -199,15 +199,15 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0 - ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG1]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -236,7 +236,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -246,9 +246,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_1 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -276,7 +276,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -286,9 +286,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_0 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -316,7 +316,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -326,9 +326,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_3 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -356,7 +356,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -366,9 +366,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -396,7 +396,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_4 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -406,9 +406,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3 ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_5 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -436,7 +436,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_5 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -446,9 +446,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3 ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_4 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -476,7 +476,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_6 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -486,9 +486,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2 ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_7 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -516,7 +516,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_7 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -526,9 +526,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2 ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_6 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -556,7 +556,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -564,9 +564,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_1 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -594,7 +594,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -602,9 +602,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -632,7 +632,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_2 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -640,9 +640,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -670,7 +670,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_3 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF @@ -678,9 +678,9 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -708,15 +708,15 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG1]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -744,15 +744,15 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm4 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 - ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG1]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 - ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $x10 diff --git a/llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir b/llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir index adfa39b71fd4a..299d6dd496788 100644 --- a/llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir +++ b/llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir @@ -50,7 +50,7 @@ body: | ; CHECK-NEXT: $v0 = COPY [[COPY]] ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8nov0 = COPY [[DEF]] - ; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK [[COPY2]], [[COPY1]], $v0, -1, 6 /* e64 */, 1 /* ta, mu */ :: (load (s512) from %ir.a, align 8) + ; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK [[COPY2]], [[COPY1]], $v0, -1 /* vl=VLMAX */, 6 /* e64 */, 1 /* ta, mu */ :: (load (s512) from %ir.a, align 8) ; CHECK-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_MASK]] ; CHECK-NEXT: PseudoRET implicit $v8m8 %1:vr = COPY $v0 diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir index d79539b819ac3..3e7f596b2dac4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir +++ b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir @@ -77,7 +77,7 @@ body: | ; CHECK: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vr = INIT_UNDEF - ; CHECK-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef [[DEF]], [[INIT_UNDEF]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef [[DEF]], [[INIT_UNDEF]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY %1 ; CHECK-NEXT: PseudoRET implicit $v8 %2:vr = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll b/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll index ab43ac7cf03a6..f2d8e82433e72 100644 --- a/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll @@ -437,8 +437,9 @@ entry: define @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e16, m4, tu, ma ; CHECK-NEXT: vfwsub.wv v8, v16, v24 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd.ll index 6942169587c48..134c1da011156 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd.ll @@ -234,9 +234,9 @@ entry: define @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -445,9 +445,9 @@ entry: define @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -621,9 +621,9 @@ entry: define @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -762,9 +762,9 @@ entry: define @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll index 7fd02f99f618a..329955df5bbe5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll @@ -234,9 +234,9 @@ entry: define @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -445,9 +445,9 @@ entry: define @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -621,9 +621,9 @@ entry: define @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -762,9 +762,9 @@ entry: define @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd.ll b/llvm/test/CodeGen/RISCV/rvv/vadd.ll index 8d0259a426d04..453e547d1fbdc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vand.ll b/llvm/test/CodeGen/RISCV/rvv/vand.ll index d1c8714a6abdc..6f7a50ed4c5ac 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vand.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn.ll b/llvm/test/CodeGen/RISCV/rvv/vandn.ll index 88a51658e4ef3..c903afe861a2a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vandn.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vandn.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vandn_mask_vv_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vandn_mask_vv_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vandn.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vandn_mask_vv_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vandn_mask_vv_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vandn.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vandn_mask_vv_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vandn_mask_vv_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vandn.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vandn_mask_vv_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vandn_mask_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vandn.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub.ll b/llvm/test/CodeGen/RISCV/rvv/vasub.ll index 2b7f8dbd34cf1..f0be7a2718887 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vasub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasub.ll @@ -234,9 +234,9 @@ entry: define @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -445,9 +445,9 @@ entry: define @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -621,9 +621,9 @@ entry: define @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -762,9 +762,9 @@ entry: define @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu.ll index c96a467bb425a..ded9c0473fbc6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vasubu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasubu.ll @@ -234,9 +234,9 @@ entry: define @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -445,9 +445,9 @@ entry: define @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -621,9 +621,9 @@ entry: define @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -762,9 +762,9 @@ entry: define @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 1 ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vclmul.ll b/llvm/test/CodeGen/RISCV/rvv/vclmul.ll index 8ea8edf218385..58ac4e7a90778 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vclmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vclmul.ll @@ -122,8 +122,8 @@ entry: define @intrinsic_vclmul_mask_vv_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vclmul_mask_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vclmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll b/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll index e5b09cc067c5b..2c9944a8d6a72 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vclmulh.ll @@ -122,8 +122,8 @@ entry: define @intrinsic_vclmulh_mask_vv_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vclmulh_mask_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vclmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll index e2b26ce9d1810..98f24a034d9ee 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll @@ -8,12 +8,9 @@ define @vdiv_vx_nxv8i7( %a, i7 signext %b, poison, i7 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv.ll index b2a7f27cb23bf..e2979011213e5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll index de278dc2e748d..060e321e16a3a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll @@ -10,8 +10,8 @@ define @vdivu_vx_nxv8i7( %a, i7 signext %b, < ; CHECK-NEXT: li a2, 127 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.x v9, a0 -; CHECK-NEXT: vand.vx v8, v8, a2, v0.t -; CHECK-NEXT: vand.vx v9, v9, a2, v0.t +; CHECK-NEXT: vand.vx v8, v8, a2 +; CHECK-NEXT: vand.vx v9, v9, a2 ; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement poison, i7 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu.ll index 847738f0dc140..60c19f090b6ed 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll b/llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll index 831912fb61fb5..6b60c0f59d2ff 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll @@ -8,7 +8,7 @@ define target("riscv.vector.tuple", , 2) @test_vlseg_nxv8i8(pt ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 - ; CHECK-NEXT: [[PseudoVLSEG2E8_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E8_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1) + ; CHECK-NEXT: [[PseudoVLSEG2E8_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E8_V_M1 $noreg, [[COPY1]], [[COPY]] /* vl */, 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY killed [[PseudoVLSEG2E8_V_M1_]] ; CHECK-NEXT: $v8_v9 = COPY [[COPY2]] ; CHECK-NEXT: PseudoRET implicit $v8_v9 @@ -24,7 +24,7 @@ define target("riscv.vector.tuple", , 2) @test_vlseg_nxv4i16(p ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 - ; CHECK-NEXT: [[PseudoVLSEG2E16_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E16_V_M1 $noreg, [[COPY1]], [[COPY]], 4 /* e16 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 2) + ; CHECK-NEXT: [[PseudoVLSEG2E16_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E16_V_M1 $noreg, [[COPY1]], [[COPY]] /* vl */, 4 /* e16 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 2) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY killed [[PseudoVLSEG2E16_V_M1_]] ; CHECK-NEXT: $v8_v9 = COPY [[COPY2]] ; CHECK-NEXT: PseudoRET implicit $v8_v9 @@ -40,7 +40,7 @@ define target("riscv.vector.tuple", , 2) @test_vlseg_nxv2i32(p ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 - ; CHECK-NEXT: [[PseudoVLSEG2E32_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E32_V_M1 $noreg, [[COPY1]], [[COPY]], 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 4) + ; CHECK-NEXT: [[PseudoVLSEG2E32_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E32_V_M1 $noreg, [[COPY1]], [[COPY]] /* vl */, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 4) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY killed [[PseudoVLSEG2E32_V_M1_]] ; CHECK-NEXT: $v8_v9 = COPY [[COPY2]] ; CHECK-NEXT: PseudoRET implicit $v8_v9 @@ -56,7 +56,7 @@ define target("riscv.vector.tuple", , 2) @test_vlseg_nxv1i64(p ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 - ; CHECK-NEXT: [[PseudoVLSEG2E64_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E64_V_M1 $noreg, [[COPY1]], [[COPY]], 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 8) + ; CHECK-NEXT: [[PseudoVLSEG2E64_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E64_V_M1 $noreg, [[COPY1]], [[COPY]] /* vl */, 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 8) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY killed [[PseudoVLSEG2E64_V_M1_]] ; CHECK-NEXT: $v8_v9 = COPY [[COPY2]] ; CHECK-NEXT: PseudoRET implicit $v8_v9 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-bf.ll index 0130af7d9e507..740d8e698eb30 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-bf.ll @@ -210,9 +210,9 @@ entry: define @intrinsic_vfadd_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd.ll index fa23dc4322880..699f520058891 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd.ll @@ -216,9 +216,9 @@ entry: define @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -402,9 +402,9 @@ entry: define @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -551,9 +551,9 @@ entry: define @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll index 71d119d9aff6b..aff5648920b43 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll @@ -210,9 +210,9 @@ entry: define @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -396,9 +396,9 @@ entry: define @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -545,9 +545,9 @@ entry: define @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll index c25a0d47c5c53..318c6bb81d68c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll @@ -2020,8 +2020,8 @@ define @vfma_vf_nxv16f16_unmasked_commute( @vfma_vv_nxv32f16( %va, %b, %c, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vfma_vv_nxv32f16: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfmadd.vv v16, v8, v24, v0.t ; ZVFH-NEXT: vmv.v.v v8, v16 ; ZVFH-NEXT: ret @@ -2144,8 +2144,8 @@ define @vfma_vv_nxv32f16( %va, @vfma_vv_nxv32f16_unmasked( %va, %b, %c, i32 zeroext %evl) { ; ZVFH-LABEL: vfma_vv_nxv32f16_unmasked: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfmadd.vv v8, v16, v24 ; ZVFH-NEXT: ret ; @@ -3027,8 +3027,8 @@ define @vfma_vf_nxv8f32_unmasked_commute( @vfma_vv_nxv16f32( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -3039,8 +3039,8 @@ define @vfma_vv_nxv16f32( %va, @vfma_vv_nxv16f32_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv16f32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %v = call @llvm.vp.fma.nxv16f32( %va, %b, %c, splat (i1 true), i32 %evl) @@ -3305,8 +3305,8 @@ define @vfma_vf_nxv4f64_unmasked_commute( @vfma_vv_nxv7f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv7f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -3317,8 +3317,8 @@ define @vfma_vv_nxv7f64( %va, @vfma_vv_nxv7f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv7f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %v = call @llvm.vp.fma.nxv7f64( %va, %b, %c, splat (i1 true), i32 %evl) @@ -3328,8 +3328,8 @@ define @vfma_vv_nxv7f64_unmasked( %va define @vfma_vv_nxv8f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -3340,8 +3340,8 @@ define @vfma_vv_nxv8f64( %va, @vfma_vv_nxv8f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv8f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %v = call @llvm.vp.fma.nxv8f64( %va, %b, %c, splat (i1 true), i32 %evl) @@ -7952,8 +7952,8 @@ define @vfnmsub_vf_nxv16f16_neg_splat_unmasked_commute( @vfmsub_vv_nxv32f16( %va, %b, %c, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vfmsub_vv_nxv32f16: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfmsub.vv v16, v8, v24, v0.t ; ZVFH-NEXT: vmv.v.v v8, v16 ; ZVFH-NEXT: ret @@ -7966,7 +7966,7 @@ define @vfmsub_vv_nxv32f16( %va, @vfmsub_vv_nxv32f16( %va, @vfmsub_vv_nxv32f16( %va, @vfmsub_vv_nxv32f16_unmasked( %va, %b, %c, i32 zeroext %evl) { ; ZVFH-LABEL: vfmsub_vv_nxv32f16_unmasked: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfmsub.vv v8, v16, v24 ; ZVFH-NEXT: ret ; @@ -8103,10 +8104,11 @@ define @vfmsub_vv_nxv32f16_unmasked( %v ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill -; ZVFHMIN-NEXT: vsetvli a2, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv8r.v v24, v8 -; ZVFHMIN-NEXT: vl8re16.v v16, (a0) +; ZVFHMIN-NEXT: vle16.v v16, (a0) ; ZVFHMIN-NEXT: lui a2, 8 +; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; ZVFHMIN-NEXT: vmset.m v8 ; ZVFHMIN-NEXT: csrr a3, vlenb ; ZVFHMIN-NEXT: slli a0, a3, 1 @@ -8722,8 +8724,8 @@ define @vfmsub_vf_nxv32f16_unmasked_commute( @vfnmadd_vv_nxv32f16( %va, %b, %c, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vfnmadd_vv_nxv32f16: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; ZVFH-NEXT: vmv.v.v v8, v16 ; ZVFH-NEXT: ret @@ -8746,7 +8748,7 @@ define @vfnmadd_vv_nxv32f16( %va, @vfnmadd_vv_nxv32f16( %va, @vfnmadd_vv_nxv32f16_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vfnmadd_vv_nxv32f16_commuted: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; ZVFH-NEXT: ret ; @@ -8886,7 +8888,7 @@ define @vfnmadd_vv_nxv32f16_commuted( % ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill -; ZVFHMIN-NEXT: vl8re16.v v8, (a0) +; ZVFHMIN-NEXT: vle16.v v8, (a0) ; ZVFHMIN-NEXT: lui a2, 8 ; ZVFHMIN-NEXT: csrr a3, vlenb ; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t @@ -8994,8 +8996,8 @@ define @vfnmadd_vv_nxv32f16_commuted( % define @vfnmadd_vv_nxv32f16_unmasked( %va, %b, %c, i32 zeroext %evl) { ; ZVFH-LABEL: vfnmadd_vv_nxv32f16_unmasked: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfnmadd.vv v8, v16, v24 ; ZVFH-NEXT: ret ; @@ -9015,7 +9017,8 @@ define @vfnmadd_vv_nxv32f16_unmasked( % ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill -; ZVFHMIN-NEXT: vl8re16.v v24, (a0) +; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFHMIN-NEXT: vle16.v v24, (a0) ; ZVFHMIN-NEXT: lui a2, 8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; ZVFHMIN-NEXT: vmset.m v8 @@ -9112,8 +9115,8 @@ define @vfnmadd_vv_nxv32f16_unmasked( % define @vfnmadd_vv_nxv32f16_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; ZVFH-LABEL: vfnmadd_vv_nxv32f16_unmasked_commuted: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfnmadd.vv v8, v16, v24 ; ZVFH-NEXT: ret ; @@ -9133,7 +9136,8 @@ define @vfnmadd_vv_nxv32f16_unmasked_commuted( @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute( @vfnmsub_vv_nxv32f16( %va, %b, %c, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vfnmsub_vv_nxv32f16: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; ZVFH-NEXT: vmv.v.v v8, v16 ; ZVFH-NEXT: ret @@ -10273,7 +10277,7 @@ define @vfnmsub_vv_nxv32f16( %va, @vfnmsub_vv_nxv32f16( %va, @vfnmsub_vv_nxv32f16_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; ZVFH-LABEL: vfnmsub_vv_nxv32f16_commuted: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; ZVFH-NEXT: ret ; @@ -10413,7 +10417,7 @@ define @vfnmsub_vv_nxv32f16_commuted( % ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill -; ZVFHMIN-NEXT: vl8re16.v v8, (a0) +; ZVFHMIN-NEXT: vle16.v v8, (a0) ; ZVFHMIN-NEXT: lui a2, 8 ; ZVFHMIN-NEXT: csrr a3, vlenb ; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t @@ -10521,8 +10525,8 @@ define @vfnmsub_vv_nxv32f16_commuted( % define @vfnmsub_vv_nxv32f16_unmasked( %va, %b, %c, i32 zeroext %evl) { ; ZVFH-LABEL: vfnmsub_vv_nxv32f16_unmasked: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfnmadd.vv v8, v16, v24 ; ZVFH-NEXT: ret ; @@ -10542,7 +10546,8 @@ define @vfnmsub_vv_nxv32f16_unmasked( % ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill -; ZVFHMIN-NEXT: vl8re16.v v24, (a0) +; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFHMIN-NEXT: vle16.v v24, (a0) ; ZVFHMIN-NEXT: lui a2, 8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; ZVFHMIN-NEXT: vmset.m v8 @@ -10639,8 +10644,8 @@ define @vfnmsub_vv_nxv32f16_unmasked( % define @vfnmsub_vv_nxv32f16_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; ZVFH-LABEL: vfnmsub_vv_nxv32f16_unmasked_commuted: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vl8re16.v v24, (a0) ; ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; ZVFH-NEXT: vle16.v v24, (a0) ; ZVFH-NEXT: vfnmadd.vv v8, v16, v24 ; ZVFH-NEXT: ret ; @@ -10660,7 +10665,8 @@ define @vfnmsub_vv_nxv32f16_unmasked_commuted( @vfnmsub_vf_nxv8f32_neg_splat_unmasked_commute( @vfmsub_vv_nxv16f32( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -13336,8 +13342,8 @@ define @vfmsub_vv_nxv16f32( %va, @vfmsub_vv_nxv16f32_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv16f32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) @@ -13400,8 +13406,8 @@ define @vfmsub_vf_nxv16f32_unmasked_commute( @vfnmadd_vv_nxv16f32( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -13414,8 +13420,8 @@ define @vfnmadd_vv_nxv16f32( %va, @vfnmadd_vv_nxv16f32_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv16f32_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) @@ -13427,8 +13433,8 @@ define @vfnmadd_vv_nxv16f32_commuted( define @vfnmadd_vv_nxv16f32_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv16f32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) @@ -13440,8 +13446,8 @@ define @vfnmadd_vv_nxv16f32_unmasked( define @vfnmadd_vv_nxv16f32_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv16f32_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) @@ -13565,8 +13571,8 @@ define @vfnmadd_vf_nxv16f32_neg_splat_unmasked_commute( @vfnmsub_vv_nxv16f32( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -13579,8 +13585,8 @@ define @vfnmsub_vv_nxv16f32( %va, @vfnmsub_vv_nxv16f32_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) @@ -13592,8 +13598,8 @@ define @vfnmsub_vv_nxv16f32_commuted( define @vfnmsub_vv_nxv16f32_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) @@ -13605,8 +13611,8 @@ define @vfnmsub_vv_nxv16f32_unmasked( define @vfnmsub_vv_nxv16f32_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) @@ -14889,8 +14895,8 @@ define @vfnmsub_vf_nxv4f64_neg_splat_unmasked_commute( @vfmsub_vv_nxv8f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -14902,8 +14908,8 @@ define @vfmsub_vv_nxv8f64( %va, @vfmsub_vv_nxv8f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv8f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) @@ -14966,8 +14972,8 @@ define @vfmsub_vf_nxv8f64_unmasked_commute( @vfnmadd_vv_nxv8f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -14980,8 +14986,8 @@ define @vfnmadd_vv_nxv8f64( %va, @vfnmadd_vv_nxv8f64_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv8f64_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) @@ -14993,8 +14999,8 @@ define @vfnmadd_vv_nxv8f64_commuted( define @vfnmadd_vv_nxv8f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv8f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) @@ -15006,8 +15012,8 @@ define @vfnmadd_vv_nxv8f64_unmasked( define @vfnmadd_vv_nxv8f64_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv8f64_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) @@ -15131,8 +15137,8 @@ define @vfnmadd_vf_nxv8f64_neg_splat_unmasked_commute( @vfnmsub_vv_nxv8f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -15145,8 +15151,8 @@ define @vfnmsub_vv_nxv8f64( %va, @vfnmsub_vv_nxv8f64_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) @@ -15158,8 +15164,8 @@ define @vfnmsub_vv_nxv8f64_commuted( define @vfnmsub_vv_nxv8f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) @@ -15171,8 +15177,8 @@ define @vfnmsub_vv_nxv8f64_unmasked( define @vfnmsub_vv_nxv8f64_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll index 28a8ef0087d85..86d767d3cf6f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll @@ -605,8 +605,8 @@ define @vfmacc_vf_nxv32f16_unmasked( %v define @vfmacc_vv_nxv32f16_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfmacc_vv_nxv32f16_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1138,8 +1138,8 @@ define @vfmacc_vf_nxv16f32_unmasked( define @vfmacc_vv_nxv16f32_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfmacc_vv_nxv16f32_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1565,8 +1565,8 @@ define @vfmacc_vf_nxv8f64_unmasked( % define @vfmacc_vv_nxv8f64_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfmacc_vv_nxv8f64_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-bf.ll index dff9309194486..a5cfd1f4786f5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-bf.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfmax_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax.ll index 166faef24271b..ca15522cee289 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-bf.ll index d40e39c3138f7..0c5d2d57e56e6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-bf.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfmin_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin.ll index d060a24e665c0..eda76725b15a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll index 72ed38b53d2ff..e63bf8e6139cf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll @@ -650,8 +650,8 @@ define @vmfsac_vf_nxv32f16_unmasked( %a define @vmfsac_vv_nxv32f16_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmfsac_vv_nxv32f16_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1223,8 +1223,8 @@ define @vmfsac_vf_nxv16f32_unmasked( define @vmfsac_vv_nxv16f32_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmfsac_vv_nxv16f32_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1682,8 +1682,8 @@ define @vmfsac_vf_nxv8f64_unmasked( % define @vmfsac_vv_nxv8f64_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmfsac_vv_nxv8f64_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-bf.ll index 609ef8fb149b0..a7653c87c309a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-bf.ll @@ -210,9 +210,9 @@ entry: define @intrinsic_vfmul_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul.ll index 8e8f2de3bb5eb..96f1e3d2f335e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul.ll @@ -210,9 +210,9 @@ entry: define @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -396,9 +396,9 @@ entry: define @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -545,9 +545,9 @@ entry: define @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll index 03de2c97e685c..42cde7d5f41bf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll @@ -352,8 +352,8 @@ define @vfma_vf_nxv16f16_unmasked_commute( @vfma_vv_nxv32f16( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -364,8 +364,8 @@ define @vfma_vv_nxv32f16( %va, @vfma_vv_nxv32f16_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv32f16_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %v = call @llvm.vp.fmuladd.nxv32f16( %va, %b, %c, splat (i1 true), i32 %evl) @@ -699,8 +699,8 @@ define @vfma_vf_nxv8f32_unmasked_commute( @vfma_vv_nxv16f32( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -711,8 +711,8 @@ define @vfma_vv_nxv16f32( %va, @vfma_vv_nxv16f32_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv16f32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %v = call @llvm.vp.fmuladd.nxv16f32( %va, %b, %c, splat (i1 true), i32 %evl) @@ -977,8 +977,8 @@ define @vfma_vf_nxv4f64_unmasked_commute( @vfma_vv_nxv7f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv7f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -989,8 +989,8 @@ define @vfma_vv_nxv7f64( %va, @vfma_vv_nxv7f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv7f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %v = call @llvm.vp.fmuladd.nxv7f64( %va, %b, %c, splat (i1 true), i32 %evl) @@ -1000,8 +1000,8 @@ define @vfma_vv_nxv7f64_unmasked( %va define @vfma_vv_nxv8f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1012,8 +1012,8 @@ define @vfma_vv_nxv8f64( %va, @vfma_vv_nxv8f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfma_vv_nxv8f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %v = call @llvm.vp.fmuladd.nxv8f64( %va, %b, %c, splat (i1 true), i32 %evl) @@ -3211,8 +3211,8 @@ define @vfnmsub_vf_nxv16f16_neg_splat_unmasked_commute( @vfmsub_vv_nxv32f16( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -3224,8 +3224,8 @@ define @vfmsub_vv_nxv32f16( %va, @vfmsub_vv_nxv32f16_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv32f16_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) @@ -3288,8 +3288,8 @@ define @vfmsub_vf_nxv32f16_unmasked_commute( @vfnmadd_vv_nxv32f16( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -3302,8 +3302,8 @@ define @vfnmadd_vv_nxv32f16( %va, @vfnmadd_vv_nxv32f16_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv32f16_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) @@ -3315,8 +3315,8 @@ define @vfnmadd_vv_nxv32f16_commuted( % define @vfnmadd_vv_nxv32f16_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv32f16_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) @@ -3328,8 +3328,8 @@ define @vfnmadd_vv_nxv32f16_unmasked( % define @vfnmadd_vv_nxv32f16_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv32f16_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) @@ -3453,8 +3453,8 @@ define @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute( @vfnmsub_vv_nxv32f16( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -3467,8 +3467,8 @@ define @vfnmsub_vv_nxv32f16( %va, @vfnmsub_vv_nxv32f16_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv32f16_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) @@ -3480,8 +3480,8 @@ define @vfnmsub_vv_nxv32f16_commuted( % define @vfnmsub_vv_nxv32f16_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv32f16_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) @@ -3493,8 +3493,8 @@ define @vfnmsub_vv_nxv32f16_unmasked( % define @vfnmsub_vv_nxv32f16_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv32f16_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) @@ -5166,8 +5166,8 @@ define @vfnmsub_vf_nxv8f32_neg_splat_unmasked_commute( @vfmsub_vv_nxv16f32( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -5179,8 +5179,8 @@ define @vfmsub_vv_nxv16f32( %va, @vfmsub_vv_nxv16f32_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv16f32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) @@ -5243,8 +5243,8 @@ define @vfmsub_vf_nxv16f32_unmasked_commute( @vfnmadd_vv_nxv16f32( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -5257,8 +5257,8 @@ define @vfnmadd_vv_nxv16f32( %va, @vfnmadd_vv_nxv16f32_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv16f32_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) @@ -5270,8 +5270,8 @@ define @vfnmadd_vv_nxv16f32_commuted( define @vfnmadd_vv_nxv16f32_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv16f32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) @@ -5283,8 +5283,8 @@ define @vfnmadd_vv_nxv16f32_unmasked( define @vfnmadd_vv_nxv16f32_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv16f32_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) @@ -5408,8 +5408,8 @@ define @vfnmadd_vf_nxv16f32_neg_splat_unmasked_commute( @vfnmsub_vv_nxv16f32( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -5422,8 +5422,8 @@ define @vfnmsub_vv_nxv16f32( %va, @vfnmsub_vv_nxv16f32_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) @@ -5435,8 +5435,8 @@ define @vfnmsub_vv_nxv16f32_commuted( define @vfnmsub_vv_nxv16f32_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) @@ -5448,8 +5448,8 @@ define @vfnmsub_vv_nxv16f32_unmasked( define @vfnmsub_vv_nxv16f32_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv16f32_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) @@ -6732,8 +6732,8 @@ define @vfnmsub_vf_nxv4f64_neg_splat_unmasked_commute( @vfmsub_vv_nxv8f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -6745,8 +6745,8 @@ define @vfmsub_vv_nxv8f64( %va, @vfmsub_vv_nxv8f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfmsub_vv_nxv8f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) @@ -6809,8 +6809,8 @@ define @vfmsub_vf_nxv8f64_unmasked_commute( @vfnmadd_vv_nxv8f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -6823,8 +6823,8 @@ define @vfnmadd_vv_nxv8f64( %va, @vfnmadd_vv_nxv8f64_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv8f64_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) @@ -6836,8 +6836,8 @@ define @vfnmadd_vv_nxv8f64_commuted( define @vfnmadd_vv_nxv8f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv8f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) @@ -6849,8 +6849,8 @@ define @vfnmadd_vv_nxv8f64_unmasked( define @vfnmadd_vv_nxv8f64_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmadd_vv_nxv8f64_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) @@ -6974,8 +6974,8 @@ define @vfnmadd_vf_nxv8f64_neg_splat_unmasked_commute( @vfnmsub_vv_nxv8f64( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -6988,8 +6988,8 @@ define @vfnmsub_vv_nxv8f64( %va, @vfnmsub_vv_nxv8f64_commuted( %va, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) @@ -7001,8 +7001,8 @@ define @vfnmsub_vv_nxv8f64_commuted( define @vfnmsub_vv_nxv8f64_unmasked( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) @@ -7014,8 +7014,8 @@ define @vfnmsub_vv_nxv8f64_unmasked( define @vfnmsub_vv_nxv8f64_unmasked_commuted( %va, %b, %c, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsub_vv_nxv8f64_unmasked_commuted: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll index 7f6fb030b13be..c7b415f49b2a0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll @@ -695,8 +695,8 @@ define @vfnmacc_vf_nxv32f16_unmasked( % define @vfnmacc_vv_nxv32f16_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmacc_vv_nxv32f16_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1308,8 +1308,8 @@ define @vfnmacc_vf_nxv16f32_unmasked( define @vfnmacc_vv_nxv16f32_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmacc_vv_nxv16f32_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1799,8 +1799,8 @@ define @vfnmacc_vf_nxv8f64_unmasked( define @vfnmacc_vv_nxv8f64_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmacc_vv_nxv8f64_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll index 37b223be1150c..735ee0b7f84c5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll @@ -650,8 +650,8 @@ define @vfnmsac_vf_nxv32f16_unmasked( % define @vfnmsac_vv_nxv32f16_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsac_vv_nxv32f16_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfnmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1223,8 +1223,8 @@ define @vfnmsac_vf_nxv16f32_unmasked( define @vfnmsac_vv_nxv16f32_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsac_vv_nxv16f32_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfnmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1682,8 +1682,8 @@ define @vfnmsac_vf_nxv8f64_unmasked( define @vfnmsac_vv_nxv8f64_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfnmsac_vv_nxv8f64_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfnmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll index 111fa368ac155..45a6a4d95be02 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll @@ -18,7 +18,6 @@ define @vfptosi_nxv1bf16_nxv1i1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to @@ -57,7 +56,6 @@ define @vfptoui_nxv1bf16_nxv1i1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to @@ -166,7 +164,6 @@ define @vfptosi_nxv2bf16_nxv2i1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to @@ -179,7 +176,6 @@ define @vfptoui_nxv2bf16_nxv2i1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to @@ -288,7 +284,6 @@ define @vfptosi_nxv4bf16_nxv4i1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to @@ -301,7 +296,6 @@ define @vfptoui_nxv4bf16_nxv4i1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to @@ -410,7 +404,6 @@ define @vfptosi_nxv8bf16_nxv8i1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to @@ -423,7 +416,6 @@ define @vfptoui_nxv8bf16_nxv8i1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to @@ -532,7 +524,6 @@ define @vfptosi_nxv16bf16_nxv16i1( %va) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8 ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptosi %va to @@ -545,7 +536,6 @@ define @vfptoui_nxv16bf16_nxv16i1( %va) ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16 -; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %evec = fptoui %va to @@ -634,8 +624,6 @@ define @vfptosi_nxv32bf16_nxv32i1( %va) ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16 ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v24 -; CHECK-NEXT: vand.vi v8, v8, 1 -; CHECK-NEXT: vand.vi v12, v12, 1 ; CHECK-NEXT: vmsne.vi v16, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma @@ -655,8 +643,6 @@ define @vfptoui_nxv32bf16_nxv32i1( %va) ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16 ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v24 -; CHECK-NEXT: vand.vi v8, v8, 1 -; CHECK-NEXT: vand.vi v12, v12, 1 ; CHECK-NEXT: vmsne.vi v16, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma @@ -733,8 +719,7 @@ define @vfptosi_nxv1f16_nxv1i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8 -; ZVFH-NEXT: vand.vi v8, v9, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v9, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptosi_nxv1f16_nxv1i1: @@ -742,7 +727,6 @@ define @vfptosi_nxv1f16_nxv1i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptosi %va to @@ -794,8 +778,7 @@ define @vfptoui_nxv1f16_nxv1i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; ZVFH-NEXT: vand.vi v8, v9, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v9, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptoui_nxv1f16_nxv1i1: @@ -803,7 +786,6 @@ define @vfptoui_nxv1f16_nxv1i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptoui %va to @@ -951,8 +933,7 @@ define @vfptosi_nxv2f16_nxv2i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8 -; ZVFH-NEXT: vand.vi v8, v9, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v9, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptosi_nxv2f16_nxv2i1: @@ -960,7 +941,6 @@ define @vfptosi_nxv2f16_nxv2i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptosi %va to @@ -972,8 +952,7 @@ define @vfptoui_nxv2f16_nxv2i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; ZVFH-NEXT: vand.vi v8, v9, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v9, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptoui_nxv2f16_nxv2i1: @@ -981,7 +960,6 @@ define @vfptoui_nxv2f16_nxv2i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptoui %va to @@ -1129,8 +1107,7 @@ define @vfptosi_nxv4f16_nxv4i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8 -; ZVFH-NEXT: vand.vi v8, v9, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v9, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptosi_nxv4f16_nxv4i1: @@ -1138,7 +1115,6 @@ define @vfptosi_nxv4f16_nxv4i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v10 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptosi %va to @@ -1150,8 +1126,7 @@ define @vfptoui_nxv4f16_nxv4i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; ZVFH-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; ZVFH-NEXT: vand.vi v8, v9, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v9, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptoui_nxv4f16_nxv4i1: @@ -1159,7 +1134,6 @@ define @vfptoui_nxv4f16_nxv4i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v10 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptoui %va to @@ -1307,8 +1281,7 @@ define @vfptosi_nxv8f16_nxv8i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; ZVFH-NEXT: vfncvt.rtz.x.f.w v10, v8 -; ZVFH-NEXT: vand.vi v8, v10, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v10, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptosi_nxv8f16_nxv8i1: @@ -1316,7 +1289,6 @@ define @vfptosi_nxv8f16_nxv8i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v12 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptosi %va to @@ -1328,8 +1300,7 @@ define @vfptoui_nxv8f16_nxv8i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; ZVFH-NEXT: vfncvt.rtz.xu.f.w v10, v8 -; ZVFH-NEXT: vand.vi v8, v10, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v10, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptoui_nxv8f16_nxv8i1: @@ -1337,7 +1308,6 @@ define @vfptoui_nxv8f16_nxv8i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v12 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptoui %va to @@ -1485,8 +1455,7 @@ define @vfptosi_nxv16f16_nxv16i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; ZVFH-NEXT: vfncvt.rtz.x.f.w v12, v8 -; ZVFH-NEXT: vand.vi v8, v12, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v12, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptosi_nxv16f16_nxv16i1: @@ -1494,7 +1463,6 @@ define @vfptosi_nxv16f16_nxv16i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v16 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptosi %va to @@ -1506,8 +1474,7 @@ define @vfptoui_nxv16f16_nxv16i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; ZVFH-NEXT: vfncvt.rtz.xu.f.w v12, v8 -; ZVFH-NEXT: vand.vi v8, v12, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v12, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptoui_nxv16f16_nxv16i1: @@ -1515,7 +1482,6 @@ define @vfptoui_nxv16f16_nxv16i1( %va) { ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret %evec = fptoui %va to @@ -1639,8 +1605,7 @@ define @vfptosi_nxv32f16_nxv32i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; ZVFH-NEXT: vfncvt.rtz.x.f.w v16, v8 -; ZVFH-NEXT: vand.vi v8, v16, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v16, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptosi_nxv32f16_nxv32i1: @@ -1652,8 +1617,6 @@ define @vfptosi_nxv32f16_nxv32i1( %va) { ; ZVFHMIN-NEXT: srli a0, a0, 2 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v16 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v12, v24 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 -; ZVFHMIN-NEXT: vand.vi v12, v12, 1 ; ZVFHMIN-NEXT: vmsne.vi v16, v8, 0 ; ZVFHMIN-NEXT: vmsne.vi v0, v12, 0 ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma @@ -1668,8 +1631,7 @@ define @vfptoui_nxv32f16_nxv32i1( %va) { ; ZVFH: # %bb.0: ; ZVFH-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; ZVFH-NEXT: vfncvt.rtz.xu.f.w v16, v8 -; ZVFH-NEXT: vand.vi v8, v16, 1 -; ZVFH-NEXT: vmsne.vi v0, v8, 0 +; ZVFH-NEXT: vmsne.vi v0, v16, 0 ; ZVFH-NEXT: ret ; ; ZVFHMIN-LABEL: vfptoui_nxv32f16_nxv32i1: @@ -1681,8 +1643,6 @@ define @vfptoui_nxv32f16_nxv32i1( %va) { ; ZVFHMIN-NEXT: srli a0, a0, 2 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v16 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v12, v24 -; ZVFHMIN-NEXT: vand.vi v8, v8, 1 -; ZVFHMIN-NEXT: vand.vi v12, v12, 1 ; ZVFHMIN-NEXT: vmsne.vi v16, v8, 0 ; ZVFHMIN-NEXT: vmsne.vi v0, v12, 0 ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma @@ -1785,8 +1745,7 @@ define @vfptosi_nxv1f32_nxv1i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1797,8 +1756,7 @@ define @vfptoui_nxv1f32_nxv1i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -1897,8 +1855,7 @@ define @vfptosi_nxv2f32_nxv2i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -1909,8 +1866,7 @@ define @vfptoui_nxv2f32_nxv2i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -2009,8 +1965,7 @@ define @vfptosi_nxv4f32_nxv4i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 -; CHECK-NEXT: vand.vi v8, v10, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -2021,8 +1976,7 @@ define @vfptoui_nxv4f32_nxv4i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 -; CHECK-NEXT: vand.vi v8, v10, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -2121,8 +2075,7 @@ define @vfptosi_nxv8f32_nxv8i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 -; CHECK-NEXT: vand.vi v8, v12, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -2133,8 +2086,7 @@ define @vfptoui_nxv8f32_nxv8i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 -; CHECK-NEXT: vand.vi v8, v12, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -2233,8 +2185,7 @@ define @vfptosi_nxv16f32_nxv16i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 -; CHECK-NEXT: vand.vi v8, v16, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -2245,8 +2196,7 @@ define @vfptoui_nxv16f32_nxv16i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 -; CHECK-NEXT: vand.vi v8, v16, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -2323,8 +2273,7 @@ define @vfptosi_nxv1f64_nxv1i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -2335,8 +2284,7 @@ define @vfptoui_nxv1f64_nxv1i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 -; CHECK-NEXT: vand.vi v8, v9, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -2441,8 +2389,7 @@ define @vfptosi_nxv2f64_nxv2i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 -; CHECK-NEXT: vand.vi v8, v10, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -2453,8 +2400,7 @@ define @vfptoui_nxv2f64_nxv2i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 -; CHECK-NEXT: vand.vi v8, v10, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -2559,8 +2505,7 @@ define @vfptosi_nxv4f64_nxv4i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8 -; CHECK-NEXT: vand.vi v8, v12, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -2571,8 +2516,7 @@ define @vfptoui_nxv4f64_nxv4i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8 -; CHECK-NEXT: vand.vi v8, v12, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec @@ -2677,8 +2621,7 @@ define @vfptosi_nxv8f64_nxv8i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8 -; CHECK-NEXT: vand.vi v8, v16, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: ret %evec = fptosi %va to ret %evec @@ -2689,8 +2632,7 @@ define @vfptoui_nxv8f64_nxv8i1( %va) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8 -; CHECK-NEXT: vand.vi v8, v16, 1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 +; CHECK-NEXT: vmsne.vi v0, v16, 0 ; CHECK-NEXT: ret %evec = fptoui %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-bf.ll index 605cb959134d1..ad4cc227f5f67 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-bf.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfsgnj_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll index 8949289ab68f8..b093cc1663967 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-bf.ll index 4d43b93e4bfd7..8865f3c5c97e2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-bf.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfsgnjn_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll index edd1bb65437cb..f973a2a2d9a24 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-bf.ll index b31a3290477ae..f1bb18bb0f506 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-bf.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfsgnjx_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll index 08a5b1f33a910..bcc5f2b4d630f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll index b568c19de0edd..45147ada335c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfsub_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub.ll index 70b6b58e28844..26a1068b63d19 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll index 2d130f9e6c2ca..a585a3f6e0a6d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-w-bf.ll @@ -173,9 +173,9 @@ entry: define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16alt, m4, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll index 7319301b82f91..11ab06bfc5296 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll @@ -173,9 +173,9 @@ entry: define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -322,9 +322,9 @@ entry: define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll index c1a295a36bcc2..50030cafa3019 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-w-bf.ll @@ -173,9 +173,9 @@ entry: define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16bf16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16bf16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16alt, m4, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll index d7af8f2a2746d..9ed0615abe098 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll @@ -173,9 +173,9 @@ entry: define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -322,9 +322,9 @@ entry: define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v24, (a0) -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir index a91584b11fa63..8fcf81697681c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir @@ -6,8 +6,8 @@ name: vop_vi body: | bb.0: ; CHECK-LABEL: name: vop_vi - ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -18,8 +18,8 @@ name: vop_vi_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vop_vi_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -30,8 +30,8 @@ name: vop_vi_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vop_vi_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VI_M1 $noreg, $noreg, 9, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -42,8 +42,8 @@ name: vop_vv body: | bb.0: ; CHECK-LABEL: name: vop_vv - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -54,8 +54,8 @@ name: vop_vv_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vop_vv_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -66,8 +66,8 @@ name: vop_vv_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vop_vv_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -78,8 +78,8 @@ name: vwop_vv_vd body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vd - ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -90,8 +90,8 @@ name: vwop_vv_vd_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vd_incompatible_eew - ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -102,8 +102,8 @@ name: vwop_vv_vd_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vd_incompatible_emul - ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 4 /* e8 */, 0 @@ -114,9 +114,9 @@ name: vwop_vv_vd_passthru_use body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vd_passthru_use - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -128,9 +128,9 @@ name: vwop_vv_vd_passthru_use_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vd_passthru_use_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 @@ -142,9 +142,9 @@ name: vwop_vv_vd_passthru_use_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vd_passthru_use_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF4 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF4 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWADD_VV_MF4 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -156,8 +156,8 @@ name: vwop_vv_vs2 body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -168,8 +168,8 @@ name: vwop_vv_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vs2_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -180,8 +180,8 @@ name: vwop_vv_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vs2_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVWADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -192,8 +192,8 @@ name: vwop_vv_vs1 body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vs1 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -204,8 +204,8 @@ name: vwop_vv_vs1_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vs1_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 @@ -216,8 +216,8 @@ name: vwop_vv_vs1_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwop_vv_vs1_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVWADD_VV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -228,8 +228,8 @@ name: vwop_wv_vd body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vd - ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -240,8 +240,8 @@ name: vwop_wv_vd_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vd_incompatible_eew - ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -252,8 +252,8 @@ name: vwop_wv_vd_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vd_incompatible_emul - ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVWADD_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 4 /* e8 */, 0 @@ -264,9 +264,9 @@ name: vwop_wv_vd_passthru_use body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vd_passthru_use - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -278,9 +278,9 @@ name: vwop_wv_vd_passthru_use_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vd_passthru_use_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 @@ -292,9 +292,9 @@ name: vwop_wv_vd_passthru_use_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vd_passthru_use_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF4 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF4 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWADD_WV_MF4 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -306,8 +306,8 @@ name: vwop_wv_vs2 body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vs2 - ; CHECK: %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -318,8 +318,8 @@ name: vwop_wv_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vs2_incompatible_eew - ; CHECK: %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_WV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -330,8 +330,8 @@ name: vwop_wv_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vs2_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWADD_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -342,8 +342,8 @@ name: vwop_wv_vs1 body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vs1 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -354,8 +354,8 @@ name: vwop_wv_vs1_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vs1_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -366,8 +366,8 @@ name: vwop_wv_vs1_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwop_wv_vs1_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -378,8 +378,8 @@ name: tied_vwop_wv_vs1 body: | bb.0: ; CHECK-LABEL: name: tied_vwop_wv_vs1 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 @@ -390,8 +390,8 @@ name: tied_vwop_wv_vs1_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: tied_vwop_wv_vs1_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 @@ -402,8 +402,8 @@ name: tied_vwop_wv_vs1_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: tied_vwop_wv_vs1_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 @@ -414,8 +414,8 @@ name: vop_vf2_vd body: | bb.0: ; CHECK-LABEL: name: vop_vf2_vd - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -426,8 +426,8 @@ name: vop_vf2_vd_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vop_vf2_vd_incompatible_eew - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF2_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -438,8 +438,8 @@ name: vop_vf2_vd_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vop_vf2_vd_incompatible_emul - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_MF2 $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF2_MF2 $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF2_MF2 $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -450,8 +450,8 @@ name: vop_vf2_vs2 body: | bb.0: ; CHECK-LABEL: name: vop_vf2_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 @@ -462,8 +462,8 @@ name: vop_vf2_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vop_vf2_vs2_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 @@ -474,8 +474,8 @@ name: vop_vf2_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vop_vf2_vs2_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVZEXT_VF2_M1 $noreg, %x, 1, 4 /* e16 */, 0 @@ -486,8 +486,8 @@ name: vop_vf4_vd body: | bb.0: ; CHECK-LABEL: name: vop_vf4_vd - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -498,8 +498,8 @@ name: vop_vf4_vd_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vop_vf4_vd_incompatible_eew - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF4_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -510,8 +510,8 @@ name: vop_vf4_vd_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vop_vf4_vd_incompatible_emul - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_MF2 $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF4_MF2 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF4_MF2 $noreg, $noreg, -1, 5 /* e32 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -522,8 +522,8 @@ name: vop_vf4_vs2 body: | bb.0: ; CHECK-LABEL: name: vop_vf4_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 @@ -534,8 +534,8 @@ name: vop_vf4_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vop_vf4_vs2_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 @@ -546,8 +546,8 @@ name: vop_vf4_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vop_vf4_vs2_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVZEXT_VF4_M1 $noreg, %x, 1, 5 /* e32 */, 0 @@ -558,8 +558,8 @@ name: vop_vf8_vd body: | bb.0: ; CHECK-LABEL: name: vop_vf8_vd - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, 1, 6 /* e64 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1, 6 /* e64 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 6 /* e64 */, 0 @@ -570,8 +570,8 @@ name: vop_vf8_vd_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vop_vf8_vd_incompatible_eew - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1, 6 /* e64 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1, 6 /* e64 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -582,8 +582,8 @@ name: vop_vf8_vd_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vop_vf8_vd_incompatible_emul - ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1, 6 /* e64 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVZEXT_VF8_M1 $noreg, $noreg, -1, 6 /* e64 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 6 /* e64 */, 0 @@ -594,8 +594,8 @@ name: vop_vf8_vs2 body: | bb.0: ; CHECK-LABEL: name: vop_vf8_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 @@ -606,8 +606,8 @@ name: vop_vf8_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vop_vf8_vs2_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF8 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 @@ -618,8 +618,8 @@ name: vop_vf8_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vop_vf8_vs2_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1 /* vl */, 6 /* e64 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVZEXT_VF8_M1 $noreg, %x, 1, 6 /* e64 */, 0 @@ -630,8 +630,8 @@ name: vnop_wv_vd body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vd - ; CHECK: early-clobber %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -642,8 +642,8 @@ name: vnop_wv_vd_unsupported_eew body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vd_unsupported_eew - ; CHECK: early-clobber %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVNSRL_WV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -654,8 +654,8 @@ name: vnop_wv_vd_unsupported_emul body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vd_unsupported_emul - ; CHECK: %x:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -666,9 +666,9 @@ name: vnop_wv_vd_passthru_use body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vd_passthru_use - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -680,9 +680,9 @@ name: vnop_wv_vd_passthru_use_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vd_passthru_use_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVNSRL_WV_M1 %x, $noreg, $noreg, 1, 4 /* e16 */, 0 @@ -694,9 +694,9 @@ name: vnop_wv_vd_passthru_use_unsupported_emul body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vd_passthru_use_unsupported_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVNSRL_WV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -708,8 +708,8 @@ name: vnop_wv_vs2 body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -720,8 +720,8 @@ name: vnop_wv_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vs2_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -732,8 +732,8 @@ name: vnop_wv_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vs2_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVNSRL_WV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -744,8 +744,8 @@ name: vnop_wv_vs1 body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vs1 - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -756,8 +756,8 @@ name: vnop_wv_vs1_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vs1_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -768,8 +768,8 @@ name: vnop_wv_vs1_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vnop_wv_vs1_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVNSRL_WV_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -780,8 +780,8 @@ name: vfnop_vs2 body: | bb.0: ; CHECK-LABEL: name: vfnop_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0 /* frm=rne */, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 @@ -792,8 +792,8 @@ name: vfnop_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vfnop_vs2_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0 /* frm=rne */, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 4 /* e16 */, 0 @@ -804,8 +804,8 @@ name: vfnop_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vfnop_vs2_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0 /* frm=rne */, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 early-clobber %y:vr = PseudoVFNCVT_X_F_W_MF2 $noreg, %x, 0, 1, 3 /* e8 */, 0 @@ -816,8 +816,8 @@ name: vseN_v body: | bb.0: ; CHECK-LABEL: name: vseN_v - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 PseudoVSE8_V_M1 %x, $noreg, 1, 3 /* e8 */ ... @@ -826,8 +826,8 @@ name: vseN_v_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vseN_v_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 PseudoVSE8_V_M1 %x, $noreg, 1, 3 /* e8 */ ... @@ -836,8 +836,8 @@ name: vseN_v_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vseN_v_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSE8_V_MF2 %x, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSE8_V_MF2 %x, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 PseudoVSE8_V_MF2 %x, $noreg, 1, 3 /* e8 */ ... @@ -846,8 +846,8 @@ name: vsm_v body: | bb.0: ; CHECK-LABEL: name: vsm_v - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ - ; CHECK-NEXT: PseudoVSM_V_B8 %x, $noreg, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: PseudoVSM_V_B8 %x, $noreg, 1 /* vl */, 0 /* e8 */ %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 PseudoVSM_V_B8 %x, $noreg, 1, 0 ... @@ -856,8 +856,8 @@ name: vsm_v_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vsm_v_incompatible_emul - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: PseudoVSM_V_B16 %x, $noreg, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: PseudoVSM_V_B16 %x, $noreg, 1 /* vl */, 0 /* e8 */ %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 PseudoVSM_V_B16 %x, $noreg, 1, 0 ... @@ -866,8 +866,8 @@ name: vleN_v body: | bb.0: ; CHECK-LABEL: name: vleN_v - ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -878,8 +878,8 @@ name: vleN_v_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vleN_v_incompatible_eew - ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -890,8 +890,8 @@ name: vleN_v_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vleN_v_incompatible_emul - ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -902,8 +902,8 @@ name: vlm_v body: | bb.0: ; CHECK-LABEL: name: vlm_v - ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, 1, 0 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 @@ -914,8 +914,8 @@ name: vlm_v_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vlm_v_incompatible_eew - ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 @@ -926,8 +926,8 @@ name: vlm_v_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vlm_v_incompatible_emul - ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 @@ -938,8 +938,8 @@ name: vsseN_v body: | bb.0: ; CHECK-LABEL: name: vsseN_v - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ ... @@ -948,8 +948,8 @@ name: vsseN_v_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vsseN_v_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 PseudoVSSE8_V_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ ... @@ -958,8 +958,8 @@ name: vsseN_v_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vsseN_v_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSSE8_V_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSSE8_V_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 PseudoVSSE8_V_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */ ... @@ -968,8 +968,8 @@ name: vsuxeiN_v_data body: | bb.0: ; CHECK-LABEL: name: vsuxeiN_v_data - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ ... @@ -978,8 +978,8 @@ name: vsuxeiN_v_data_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vsuxeiN_v_data_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 PseudoVSUXEI8_V_M1_M1 %x, $noreg, $noreg, 1, 3 /* e8 */ ... @@ -988,8 +988,8 @@ name: vsuxeiN_v_data_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vsuxeiN_v_data_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 PseudoVSUXEI8_V_MF2_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */ ... @@ -998,8 +998,8 @@ name: vsuxeiN_v_idx body: | bb.0: ; CHECK-LABEL: name: vsuxeiN_v_idx - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */ ... @@ -1008,8 +1008,8 @@ name: vsuxeiN_v_idx_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vsuxeiN_v_idx_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 PseudoVSUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */ ... @@ -1018,8 +1018,8 @@ name: vsuxeiN_v_idx_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vsuxeiN_v_idx_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: PseudoVSUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 PseudoVSUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */ ... @@ -1028,8 +1028,8 @@ name: vluxeiN_v_data body: | bb.0: ; CHECK-LABEL: name: vluxeiN_v_data - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1040,8 +1040,8 @@ name: vluxeiN_v_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vluxeiN_v_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1052,8 +1052,8 @@ name: vluxeiN_v_data_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vluxeiN_v_data_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1064,8 +1064,8 @@ name: vluxeiN_v_idx body: | bb.0: ; CHECK-LABEL: name: vluxeiN_v_idx - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 @@ -1076,8 +1076,8 @@ name: vluxeiN_v_idx_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1088,8 +1088,8 @@ name: vluxeiN_v_idx_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1100,8 +1100,8 @@ name: vluxeiN_v_vd body: | bb.0: ; CHECK-LABEL: name: vluxeiN_v_vd - ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -1112,8 +1112,8 @@ name: vluxeiN_v_vd_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vluxeiN_v_vd_incompatible_eew - ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -1124,8 +1124,8 @@ name: vluxeiN_vd_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vluxeiN_vd_incompatible_emul - ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -1136,8 +1136,8 @@ name: vmop_mm body: | bb.0: ; CHECK-LABEL: name: vmop_mm - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 @@ -1148,8 +1148,8 @@ name: vmop_mm_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmop_mm_incompatible_eew - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1160,8 +1160,8 @@ name: vmop_mm_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmop_mm_incompatible_emul - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 @@ -1172,8 +1172,8 @@ name: vmop_mm_mask body: | bb.0: ; CHECK-LABEL: name: vmop_mm_mask - ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1184,8 +1184,8 @@ name: vmop_mm_mask_larger_emul_user body: | bb.0: ; CHECK-LABEL: name: vmop_mm_mask_larger_emul_user - ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ - ; CHECK-NEXT: %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 @@ -1196,8 +1196,8 @@ name: vmop_mm_mask_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmop_mm_mask_incompatible_emul - ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vmv0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1208,8 +1208,8 @@ name: vmop_vv body: | bb.0: ; CHECK-LABEL: name: vmop_vv - ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1, 3 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 @@ -1220,8 +1220,8 @@ name: vmop_vv_maskuser body: | bb.0: ; CHECK-LABEL: name: vmop_vv_maskuser - ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1, 3 /* e8 */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1232,8 +1232,8 @@ name: vmop_vv_maskuser_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmop_vv_maskuser_incompatible_eew - ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ %y:vrnov0 = PseudoVADD_VV_M1_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 @@ -1244,8 +1244,8 @@ name: vmop_vv_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmop_vv_incompatible_emul - ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 @@ -1256,8 +1256,8 @@ name: vmop_vv_maskuser_incompaible_emul body: | bb.0: ; CHECK-LABEL: name: vmop_vv_maskuser_incompaible_emul - ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ %y:vrnov0 = PseudoVADD_VV_MF2_MASK $noreg, $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1268,8 +1268,8 @@ name: vmop_vv_maskuser_larger_emul body: | bb.0: ; CHECK-LABEL: name: vmop_vv_maskuser_larger_emul - ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1, 3 /* e8 */ - ; CHECK-NEXT: %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vmv0 = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ %y:vrm2nov0 = PseudoVADD_VV_M2_MASK $noreg, $noreg, $noreg, %x, 1, 4 /* e16 */, 0 @@ -1280,8 +1280,8 @@ name: vmop_vv_consumer_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmop_vv_consumer_incompatible_eew - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMSEQ_VV_M1 $noreg, %x, 1, 4 /* e16 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMSEQ_VV_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVMSEQ_VV_M1 $noreg, %x, 1, 4 /* e16 */ @@ -1292,8 +1292,8 @@ name: vmop_vv_consumer_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmop_vv_consumer_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMSEQ_VV_MF2 $noreg, %x, 1, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMSEQ_VV_MF2 $noreg, %x, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVMSEQ_VV_MF2 $noreg, %x, 1, 3 /* e8 */ @@ -1304,9 +1304,9 @@ name: vmop_vv_passthru_use body: | bb.0: ; CHECK-LABEL: name: vmop_vv_passthru_use - ; CHECK: %x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 /* ta, mu */ - ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 1 /* ta, mu */ + ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %z %x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e1 */ %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 @@ -1318,9 +1318,9 @@ name: vmop_vv_passthru_use_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmop_vv_passthru_use_incompatible_eew - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 /* ta, mu */ - ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 1 /* ta, mu */ + ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %z %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 @@ -1332,9 +1332,9 @@ name: vmop_vv_passthru_use_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmop_vv_passthru_use_incompatible_emul - ; CHECK: %x:vrnov0 = PseudoVMAND_MM_B16 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 /* ta, mu */ - ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVMAND_MM_B16 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 1 /* ta, mu */ + ; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %z %x:vrnov0 = PseudoVMAND_MM_B16 $noreg, $noreg, -1, 0 /* e1 */ %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */, 1 @@ -1346,8 +1346,8 @@ name: vmerge_vim body: | bb.0: ; CHECK-LABEL: name: vmerge_vim - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */ @@ -1358,8 +1358,8 @@ name: vmerge_vim_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmerge_vim_incompatible_eew - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, %x, 9, $v0, 1, 3 /* e8 */ @@ -1370,8 +1370,8 @@ name: vmerge_vim_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmerge_vim_incompatible_emul - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrnov0 = PseudoVMERGE_VIM_MF2 $noreg, %x, 9, $v0, 1, 3 /* e8 */ @@ -1382,8 +1382,8 @@ name: vmerge_vxm body: | bb.0: ; CHECK-LABEL: name: vmerge_vxm - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ @@ -1394,8 +1394,8 @@ name: vmerge_vxm_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmerge_vxm_incompatible_eew - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vrnov0 = PseudoVMERGE_VXM_M1 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ @@ -1406,8 +1406,8 @@ name: vmerge_vxm_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmerge_vxm_incompatible_emul - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, $noreg, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrnov0 = PseudoVMERGE_VXM_MF2 $noreg, %x, $noreg, $v0, 1, 3 /* e8 */ @@ -1418,8 +1418,8 @@ name: vmerge_vvm body: | bb.0: ; CHECK-LABEL: name: vmerge_vvm - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ @@ -1430,8 +1430,8 @@ name: vmerge_vvm_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmerge_vvm_incompatible_eew - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ @@ -1442,8 +1442,8 @@ name: vmerge_vvm_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmerge_vvm_incompatible_emul - ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ + ; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1 /* vl */, 3 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vrnov0 = PseudoVMERGE_VVM_MF2 $noreg, $noreg, %x, $v0, 1, 3 /* e8 */ @@ -1454,8 +1454,8 @@ name: vmv_v_i body: | bb.0: ; CHECK-LABEL: name: vmv_v_i - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 @@ -1466,8 +1466,8 @@ name: vmv_v_i_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmv_v_i_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_M1 %x, 9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVMV_V_I_M1 %x, 9, 1, 3 /* e8 */, 0 @@ -1478,8 +1478,8 @@ name: vmv_v_i_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmv_v_i_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_MF2 %x, 9, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_I_MF2 %x, 9, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVMV_V_I_MF2 %x, 9, 1, 3 /* e8 */, 0 @@ -1490,8 +1490,8 @@ name: vmv_v_x body: | bb.0: ; CHECK-LABEL: name: vmv_v_x - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0 @@ -1502,8 +1502,8 @@ name: vmv_v_x_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmv_v_x_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVMV_V_X_M1 %x, $noreg, 1, 3 /* e8 */, 0 @@ -1514,8 +1514,8 @@ name: vmv_v_x_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmv_v_x_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_MF2 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_X_MF2 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVMV_V_X_MF2 %x, $noreg, 1, 3 /* e8 */, 0 @@ -1526,8 +1526,8 @@ name: vmv_v_v body: | bb.0: ; CHECK-LABEL: name: vmv_v_v - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0 @@ -1538,8 +1538,8 @@ name: vmv_v_v_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmv_v_v_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 1, 3 /* e8 */, 0 @@ -1550,8 +1550,8 @@ name: vmv_v_v_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmv_v_v_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_MF2 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_MF2 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVMV_V_V_MF2 $noreg, %x, 1, 3 /* e8 */, 0 @@ -1562,8 +1562,8 @@ name: viota_m_dest body: | bb.0: ; CHECK-LABEL: name: viota_m_dest - ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -1574,8 +1574,8 @@ name: viota_m_dest_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: viota_m_dest_incompatible_eew - ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -1586,8 +1586,8 @@ name: viota_m_dest_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: viota_m_dest_incompatible_emul - ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVIOTA_M_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -1598,9 +1598,9 @@ name: viota_m_dest_passthru_use body: | bb.0: ; CHECK-LABEL: name: viota_m_dest_passthru_use - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1, 3 /* e8 */, 0 @@ -1612,9 +1612,9 @@ name: viota_m_dest_passthru_use_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: viota_m_dest_passthru_use_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVIOTA_M_M1 %x, $noreg, 1, 4 /* e16 */, 0 @@ -1626,9 +1626,9 @@ name: viota_m_dest_passthru_use_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: viota_m_dest_passthru_use_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_MF2 %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_MF2 %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVIOTA_M_MF2 %x, $noreg, 1, 3 /* e8 */, 0 @@ -1640,8 +1640,8 @@ name: viota_m_mask body: | bb.0: ; CHECK-LABEL: name: viota_m_mask - ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1, 3 /* e8 */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMSEQ_VV_M1 $noreg, $noreg, -1, 3 /* e8 */ %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0 @@ -1652,8 +1652,8 @@ name: viota_m_mask_scale_mask body: | bb.0: ; CHECK-LABEL: name: viota_m_mask_scale_mask - ; CHECK: early-clobber %x:vr = PseudoVMSEQ_VV_M2 $noreg, $noreg, 1, 4 /* e16 */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVMSEQ_VV_M2 $noreg, $noreg, 1 /* vl */, 4 /* e16 */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMSEQ_VV_M2 $noreg, $noreg, -1, 4 /* e16 */ %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 3 /* e8 */, 0 @@ -1664,8 +1664,8 @@ name: viota_m_mask_incompatible_emul_from_sew body: | bb.0: ; CHECK-LABEL: name: viota_m_mask_incompatible_emul_from_sew - ; CHECK: %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 %y:vr = PseudoVIOTA_M_M1 $noreg, %x, 1, 4 /* e16 */, 0 @@ -1676,8 +1676,8 @@ name: viota_m_mask_incompatible_emul_from_lmul body: | bb.0: ; CHECK-LABEL: name: viota_m_mask_incompatible_emul_from_lmul - ; CHECK: %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 %y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1, 3 /* e8 */, 0 @@ -1688,8 +1688,8 @@ name: vred_vs2 body: | bb.0: ; CHECK-LABEL: name: vred_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -1700,8 +1700,8 @@ name: vred_vs1 body: | bb.0: ; CHECK-LABEL: name: vred_vs1 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1712,8 +1712,8 @@ name: vred_vs1_vs2 body: | bb.0: ; CHECK-LABEL: name: vred_vs1_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 @@ -1724,8 +1724,8 @@ name: vred_vs1_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vred_vs1_vs2_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 4 /* e16 */, 0 @@ -1736,8 +1736,8 @@ name: vred_vs1_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vred_vs1_vs2_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 @@ -1748,9 +1748,9 @@ name: vred_other_user_is_vl0 body: | bb.0: ; CHECK-LABEL: name: vred_other_user_is_vl0 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 @@ -1764,9 +1764,9 @@ name: vred_both_vl0 body: | bb.0: ; CHECK-LABEL: name: vred_both_vl0 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 @@ -1781,9 +1781,9 @@ body: | bb.0: ; CHECK-LABEL: name: vred_vl0_and_vlreg ; CHECK: %vl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, %vl, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %vl:gprnox0 = COPY $x1 @@ -1799,9 +1799,9 @@ body: | bb.0: ; CHECK-LABEL: name: vred_vlreg_and_vl0 ; CHECK: %vl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %vl:gprnox0 = COPY $x1 @@ -1816,9 +1816,9 @@ name: vred_other_user_is_vl2 body: | bb.0: ; CHECK-LABEL: name: vred_other_user_is_vl2 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 @@ -1832,8 +1832,8 @@ name: vwred_vs2 body: | bb.0: ; CHECK-LABEL: name: vwred_vs2 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1844,8 +1844,8 @@ name: vwred_vs1 body: | bb.0: ; CHECK-LABEL: name: vwred_vs1 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -1856,8 +1856,8 @@ name: vwred_vs1_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwred_vs1_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -1868,8 +1868,8 @@ name: vwred_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwred_vs2_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVWREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -1880,8 +1880,8 @@ name: vwred_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwred_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVWREDSUM_VS_MF2_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -1892,8 +1892,8 @@ name: vfred_vs2 body: | bb.0: ; CHECK-LABEL: name: vfred_vs2 - ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -1904,8 +1904,8 @@ name: vfred_vs1 body: | bb.0: ; CHECK-LABEL: name: vfred_vs1 - ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 @@ -1916,8 +1916,8 @@ name: vfred_vs1_vs2 body: | bb.0: ; CHECK-LABEL: name: vfred_vs1_vs2 - ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 @@ -1928,8 +1928,8 @@ name: vfred_vs1_vs2_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vfred_vs1_vs2_incompatible_eew - ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 6 /* e64 */, 0 %y:vr = PseudoVFREDMAX_VS_M1_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 @@ -1940,8 +1940,8 @@ name: vfred_vs1_vs2_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vfred_vs1_vs2_incompatible_emul - ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_MF2_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVFREDMAX_VS_MF2_E32 $noreg, %x, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0 %y:vr = PseudoVFREDMAX_VS_MF2_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0 @@ -1952,9 +1952,9 @@ name: vwred_passthru_use body: | bb.0: ; CHECK-LABEL: name: vwred_passthru_use - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -1966,9 +1966,9 @@ name: vwred_passthru_use_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vwred_passthru_use_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:vr = PseudoVWREDSUM_VS_MF2_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -1980,9 +1980,9 @@ name: vwred_passthru_use_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vwred_passthru_use_incompatible_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF4_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVWREDSUM_VS_MF4_E8 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVWREDSUM_VS_MF4_E8 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 @@ -1994,8 +1994,8 @@ name: vfirst_v body: | bb.0: ; CHECK-LABEL: name: vfirst_v - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ - ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B8 %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B8 %x, 1 /* vl */, 0 /* e8 */ %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:gpr = PseudoVFIRST_M_B8 %x, 1, 0 ... @@ -2004,8 +2004,8 @@ name: vfirst_v_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vfirst_v_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B8 %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B8 %x, 1 /* vl */, 0 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:gpr = PseudoVFIRST_M_B8 %x, 1, 0 ... @@ -2014,8 +2014,8 @@ name: vfirst_v_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vfirst_v_incompatible_emul - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B16 %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B16 %x, 1 /* vl */, 0 /* e8 */ %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:gpr = PseudoVFIRST_M_B16 %x, 1, 0 ... @@ -2024,8 +2024,8 @@ name: vcpop_v body: | bb.0: ; CHECK-LABEL: name: vcpop_v - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ - ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B8 %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B8 %x, 1 /* vl */, 0 /* e8 */ %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:gpr = PseudoVCPOP_M_B8 %x, 1, 0 ... @@ -2034,8 +2034,8 @@ name: vcopop_v_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vcopop_v_incompatible_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B8 %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B8 %x, 1 /* vl */, 0 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 %y:gpr = PseudoVCPOP_M_B8 %x, 1, 0 ... @@ -2044,8 +2044,8 @@ name: vcpop_v_incompaitble_emul body: | bb.0: ; CHECK-LABEL: name: vcpop_v_incompaitble_emul - ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B16 %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B16 %x, 1 /* vl */, 0 /* e8 */ %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 %y:gpr = PseudoVCPOP_M_B16 %x, 1, 0 ... @@ -2054,8 +2054,8 @@ name: vmclr_m body: | bb.0: ; CHECK-LABEL: name: vmclr_m - ; CHECK: %x:vr = PseudoVMCLR_M_B8 1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMCLR_M_B8 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMCLR_M_B8 -1, 0 %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 @@ -2066,8 +2066,8 @@ name: vmclr_m_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmclr_m_incompatible_eew - ; CHECK: %x:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVMCLR_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMCLR_M_B8 -1, 0 %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -2078,8 +2078,8 @@ name: vmclr_m_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmclr_m_incompatible_emul - ; CHECK: %x:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMCLR_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMCLR_M_B8 -1, 0 %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 @@ -2090,8 +2090,8 @@ name: vmset_m body: | bb.0: ; CHECK-LABEL: name: vmset_m - ; CHECK: %x:vr = PseudoVMSET_M_B8 1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMSET_M_B8 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMSET_M_B8 -1, 0 %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 @@ -2102,8 +2102,8 @@ name: vmset_m_incompatible_eew body: | bb.0: ; CHECK-LABEL: name: vmset_m_incompatible_eew - ; CHECK: %x:vr = PseudoVMSET_M_B8 -1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVMSET_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMSET_M_B8 -1, 0 %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 @@ -2114,8 +2114,8 @@ name: vmset_m_incompatible_emul body: | bb.0: ; CHECK-LABEL: name: vmset_m_incompatible_emul - ; CHECK: %x:vr = PseudoVMSET_M_B8 -1, 0 /* e8 */ - ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */ + ; CHECK: %x:vr = PseudoVMSET_M_B8 -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVMSET_M_B8 -1, 0 %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 @@ -2126,8 +2126,8 @@ name: vrgatherei16_vv body: | bb.0: ; CHECK-LABEL: name: vrgatherei16_vv - ; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -2138,8 +2138,8 @@ name: vrgatherei16_vv_incompatible_data_eew body: | bb.0: ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_data_eew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -2150,8 +2150,8 @@ name: vrgatherei16_vv_incompatible_index_eew body: | bb.0: ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_index_eew - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 @@ -2162,8 +2162,8 @@ name: vrgatherei16_vv_incompatible_dest_emul body: | bb.0: ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_dest_emul - ; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -2174,8 +2174,8 @@ name: vrgatherei16_vv_incompatible_source_emul body: | bb.0: ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_source_emul - ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -2186,8 +2186,8 @@ name: vrgatherei16_vv_incompatible_index_emul body: | bb.0: ; CHECK-LABEL: name: vrgatherei16_vv_incompatible_index_emul - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 @@ -2203,13 +2203,13 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1, 5 /* e32 */ + ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1 /* vl */, 5 /* e32 */ %0:vr = COPY $v8 %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ @@ -2229,13 +2229,13 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: PseudoVSSEG3E64_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1, 6 /* e64 */ + ; CHECK-NEXT: PseudoVSSEG3E64_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1 /* vl */, 6 /* e64 */ %0:vr = COPY $v8 %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ @@ -2255,13 +2255,13 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1, 6 /* e64 */ + ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, 1 /* vl */, 6 /* e64 */ %0:vr = COPY $v8 %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ @@ -2277,10 +2277,10 @@ body: | bb.0: ; CHECK-LABEL: name: vsseg3e32_v_incompatible_insert_subreg - ; CHECK: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK: [[PseudoVADD_VV_M2_:%[0-9]+]]:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[PseudoVADD_VV_M2_]], %subreg.sub_vrm2_0 - ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG]], $noreg, 1, 5 /* e32 */ + ; CHECK-NEXT: PseudoVSSEG3E32_V_M1 killed [[INSERT_SUBREG]], $noreg, 1 /* vl */, 5 /* e32 */ %2:vrm2 = PseudoVADD_VV_M2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ %6:vrn3m1 = IMPLICIT_DEF %5:vrn3m1 = INSERT_SUBREG %6, %2, %subreg.sub_vrm2_0 @@ -2296,13 +2296,13 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: PseudoVSSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1, 5 /* e32 */ + ; CHECK-NEXT: PseudoVSSSEG3E32_V_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1 /* vl */, 5 /* e32 */ %0:vr = COPY $v8 %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ @@ -2322,13 +2322,13 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: PseudoVSUXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1, 5 /* e32 */ + ; CHECK-NEXT: PseudoVSUXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1 /* vl */, 5 /* e32 */ %0:vr = COPY $v8 %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ @@ -2348,13 +2348,13 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 6 /* e64 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 6 /* e64 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10 /* vl */, 6 /* e64 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: PseudoVSUXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1, 5 /* e32 */ + ; CHECK-NEXT: PseudoVSUXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1 /* vl */, 5 /* e32 */ %0:vr = COPY $v8 %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 6 /* e64 */, 3 /* ta, ma */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 6 /* e64 */, 3 /* ta, ma */ @@ -2370,8 +2370,8 @@ body: | bb.0: ; CHECK-LABEL: name: vsuxseg3ei32_v_index - ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1, 6 /* e64 */ + ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1 /* vl */, 6 /* e64 */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, %2, 1, 6 /* e64 */ ... @@ -2381,8 +2381,8 @@ body: | bb.0: ; CHECK-LABEL: name: vsuxseg3ei32_v_incompatible_index_eew - ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 6 /* e64 */, 3 /* ta, ma */ - ; CHECK-NEXT: PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1, 6 /* e64 */ + ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1 /* vl */, 6 /* e64 */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 6 /* e64 */, 3 /* ta, ma */ PseudoVSUXSEG3EI32_V_M1_M2 $noreg, $noreg, %2, 1, 6 /* e64 */ ... @@ -2396,13 +2396,13 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn3m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn3m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_1]], %subreg.sub_vrm1_2 - ; CHECK-NEXT: PseudoVSOXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1, 5 /* e32 */ + ; CHECK-NEXT: PseudoVSOXSEG3EI64_V_M2_M1 killed [[INSERT_SUBREG2]], $noreg, $noreg, 1 /* vl */, 5 /* e32 */ %0:vr = COPY $v8 %1:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ @@ -2418,8 +2418,8 @@ body: | bb.0: ; CHECK-LABEL: name: vsoxseg3ei32_v_index - ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 3 /* ta, ma */ - ; CHECK-NEXT: PseudoVSOXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1, 6 /* e64 */ + ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSOXSEG3EI32_V_M1_M2 $noreg, $noreg, [[PseudoVADD_VV_M1_]], 1 /* vl */, 6 /* e64 */ %2:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ PseudoVSOXSEG3EI32_V_M1_M2 $noreg, $noreg, %2, 1, 6 /* e64 */ ... diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir index eeec39ac5cfae..9600339972029 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-user-scalar-def.mir @@ -8,8 +8,8 @@ isSSA: true body: | bb.0: ; CHECK-LABEL: name: vec_instr_with_scalar_def - ; CHECK: [[PseudoVMNAND_MM_B8_:%[0-9]+]]:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ - ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 killed [[PseudoVMNAND_MM_B8_]], -1, 0 /* e8 */ + ; CHECK: [[PseudoVMNAND_MM_B8_:%[0-9]+]]:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1 /* vl=VLMAX */, 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 killed [[PseudoVMNAND_MM_B8_]], -1 /* vl=VLMAX */, 0 /* e8 */ %1:vr = PseudoVMNAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ %2:gpr = PseudoVCPOP_M_B1 killed %1, -1, 0 /* e8 */ ... diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir index 2eeddad9f8acb..a5cded718b9d0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir @@ -10,8 +10,8 @@ body: | ; CHECK: liveins: $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVNSRL_WV_MF4 $noreg, %x, $noreg, %vl /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %vl:gprnox0 = COPY $x1 %x:vr = PseudoVADD_VV_MF4 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ @@ -27,9 +27,9 @@ body: | ; CHECK: liveins: $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E64 $noreg, %x, $noreg, -1, 6 /* e64 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E64 $noreg, %x, $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %vl:gprnox0 = COPY $x1 @@ -44,9 +44,9 @@ name: use_largest_common_vl_imm_imm body: | bb.0: ; CHECK-LABEL: name: use_largest_common_vl_imm_imm - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 @@ -64,9 +64,9 @@ body: | ; CHECK: liveins: $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %vl, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %vl:gprnox0 = COPY $x1 @@ -86,9 +86,9 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vl0:gprnox0 = COPY $x1 ; CHECK-NEXT: %vl1:gprnox0 = COPY $x2 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl0, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl0 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %vl0:gprnox0 = COPY $x1 @@ -108,9 +108,9 @@ body: | ; CHECK: liveins: $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vl:gprnox0 = COPY $x1 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %vl:gprnox0 = COPY $x1 @@ -125,9 +125,9 @@ name: use_largest_common_vl_imm_vlmax body: | bb.0: ; CHECK-LABEL: name: use_largest_common_vl_imm_vlmax - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: $v9 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 @@ -141,8 +141,8 @@ name: vfcvt_x_f_v_nofpexcept body: | bb.0: ; CHECK-LABEL: name: vfcvt_x_f_v_nofpexcept - ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -153,8 +153,8 @@ name: vfcvt_x_f_v_fpexcept body: | bb.0: ; CHECK-LABEL: name: vfcvt_x_f_v_fpexcept - ; CHECK: %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0 /* frm=rne */, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0 %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 @@ -165,8 +165,8 @@ name: vfncvtbf16_f_f_w_nofpexcept body: | bb.0: ; CHECK-LABEL: name: vfncvtbf16_f_f_w_nofpexcept - ; CHECK: early-clobber %x:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, $noreg, 7, 1, 4 /* e16 */, 0 /* tu, mu */, implicit $frm - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: early-clobber %x:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, $noreg, 7 /* frm=dyn */, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $frm + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, $noreg, 7, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $frm %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 @@ -177,8 +177,8 @@ name: vfsqrt_nofpexcept body: | bb.0: ; CHECK-LABEL: name: vfsqrt_nofpexcept - ; CHECK: %x:vrm2 = nofpexcept PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 6, 5 /* e32 */, 3 /* ta, ma */, implicit $frm - ; CHECK-NEXT: early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4 /* e16 */, 3 /* ta, ma */, implicit $frm + ; CHECK: %x:vrm2 = nofpexcept PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7 /* frm=dyn */, 6 /* vl */, 5 /* e32 */, 3 /* ta, ma */, implicit $frm + ; CHECK-NEXT: early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7 /* frm=dyn */, 6 /* vl */, 4 /* e16 */, 3 /* ta, ma */, implicit $frm ; CHECK-NEXT: $v8 = COPY %y %x:vrm2 = nofpexcept PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 8, 5, 3, implicit $frm early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4, 3, implicit $frm @@ -189,8 +189,8 @@ name: vfsqrt_fpexcept body: | bb.0: ; CHECK-LABEL: name: vfsqrt_fpexcept - ; CHECK: %x:vrm2 = PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 8, 5 /* e32 */, 3 /* ta, ma */, implicit $frm - ; CHECK-NEXT: early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4 /* e16 */, 3 /* ta, ma */, implicit $frm + ; CHECK: %x:vrm2 = PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7 /* frm=dyn */, 8 /* vl */, 5 /* e32 */, 3 /* ta, ma */, implicit $frm + ; CHECK-NEXT: early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7 /* frm=dyn */, 6 /* vl */, 4 /* e16 */, 3 /* ta, ma */, implicit $frm ; CHECK-NEXT: $v8 = COPY %y %x:vrm2 = PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 8, 5, 3, implicit $frm early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4, 3, implicit $frm @@ -201,8 +201,8 @@ name: vfrsqrt7_nofpexcept body: | bb.0: ; CHECK-LABEL: name: vfrsqrt7_nofpexcept - ; CHECK: %x:vrm2 = nofpexcept PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vrm2 = nofpexcept PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vrm2 = nofpexcept PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5, 0 %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -213,8 +213,8 @@ name: vfrsqrt7_fpexcept body: | bb.0: ; CHECK-LABEL: name: vfrsqrt7_fpexcept - ; CHECK: %x:vrm2 = PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK: %x:vrm2 = PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vrm2 = PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5, 0 %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 @@ -225,8 +225,8 @@ name: vwadd_tied_vs1 body: | bb.0: ; CHECK-LABEL: name: vwadd_tied_vs1 - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8m2 = COPY %y %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ @@ -242,14 +242,14 @@ body: | ; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: - ; CHECK-NEXT: %a1:vr = PseudoVADD_VV_M1 $noreg, %c, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %a2:vr = PseudoVADD_VV_M1 $noreg, %a1, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %a1:vr = PseudoVADD_VV_M1 $noreg, %c, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %a2:vr = PseudoVADD_VV_M1 $noreg, %a1, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %a2 ; CHECK-NEXT: PseudoRET ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: %b1:vr = PseudoVADD_VV_M1 $noreg, %c, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %b2:vr = PseudoVADD_VV_M1 $noreg, %b1, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %b1:vr = PseudoVADD_VV_M1 $noreg, %c, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %b2:vr = PseudoVADD_VV_M1 $noreg, %b1, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %b2 ; CHECK-NEXT: PseudoRET ; CHECK-NEXT: {{ $}} @@ -257,7 +257,7 @@ body: | ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: liveins: $x1 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %c:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %c:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: BEQ $x1, $x0, %bb.1 ; CHECK-NEXT: PseudoBR %bb.2 bb.0: @@ -283,12 +283,12 @@ name: unreachable body: | ; CHECK-LABEL: name: unreachable ; CHECK: bb.0: - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %x ; CHECK-NEXT: PseudoRET ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y ; CHECK-NEXT: PseudoRET bb.0: @@ -306,9 +306,9 @@ name: passthru_not_demanded body: | bb.0: ; CHECK-LABEL: name: passthru_not_demanded - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ @@ -321,9 +321,9 @@ name: passthru_demanded body: | bb.0: ; CHECK-LABEL: name: passthru_demanded - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ @@ -336,11 +336,11 @@ name: passthru_not_demanded_passthru_chain body: | bb.0: ; CHECK-LABEL: name: passthru_not_demanded_passthru_chain - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 %y, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %a:vr = PseudoVADD_VV_M1 %z, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %b:vr = PseudoVADD_VV_M1 $noreg, %a, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 %y, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %a:vr = PseudoVADD_VV_M1 %z, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %b:vr = PseudoVADD_VV_M1 $noreg, %a, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %b %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ @@ -355,11 +355,11 @@ name: passthru_demanded_passthru_chain body: | bb.0: ; CHECK-LABEL: name: passthru_demanded_passthru_chain - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 %y, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %a:vr = PseudoVADD_VV_M1 %z, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %b:vr = PseudoVADD_VV_M1 $noreg, %a, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 %y, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %a:vr = PseudoVADD_VV_M1 %z, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %b:vr = PseudoVADD_VV_M1 $noreg, %a, $noreg, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %b %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ %y:vr = PseudoVADD_VV_M1 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ @@ -373,8 +373,8 @@ name: vxsat_dead body: | bb.0: ; CHECK-LABEL: name: vxsat_dead - ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ @@ -385,8 +385,8 @@ name: vxsat_not_dead body: | bb.0: ; CHECK-LABEL: name: vxsat_not_dead - ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def $vxsat - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit-def $vxsat + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def $vxsat %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ @@ -397,8 +397,8 @@ name: vxsat_instr_dead body: | bb.0: ; CHECK-LABEL: name: vxsat_instr_dead - ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %y %x:vr = PseudoVSADDU_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vxsat %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ @@ -409,9 +409,9 @@ name: copy body: | bb.0: ; CHECK-LABEL: name: copy - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: %y:vr = COPY %x - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ %y:vr = COPY %x @@ -423,10 +423,10 @@ name: copy_multiple_users body: | bb.0: ; CHECK-LABEL: name: copy_multiple_users - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: %y:vr = COPY %x - ; CHECK-NEXT: %z0:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ - ; CHECK-NEXT: %z1:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 3, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z0:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z1:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 3 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z0 ; CHECK-NEXT: $v9 = COPY %z1 %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ @@ -441,9 +441,9 @@ name: copy_user_invalid_sew body: | bb.0: ; CHECK-LABEL: name: copy_user_invalid_sew - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: %y:vr = COPY %x - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ %y:vr = COPY %x @@ -458,17 +458,17 @@ body: | ; CHECK: bb.0: ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1 - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z bb.0: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ @@ -488,17 +488,17 @@ body: | ; CHECK: bb.0: ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1 - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z bb.0: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ @@ -518,17 +518,17 @@ body: | ; CHECK: bb.0: ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: BNE $noreg, $noreg, %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1 - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z bb.0: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ @@ -548,13 +548,13 @@ body: | ; CHECK: bb.0: ; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %y:vr = PHI %x, %bb.0, %y, %bb.1 - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z ; CHECK-NEXT: PseudoBR %bb.1 bb.0: @@ -573,13 +573,13 @@ body: | ; CHECK: bb.0: ; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.1(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %y:vr = PHI %x, %bb.0, %z, %bb.1 - ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ ; CHECK-NEXT: $v8 = COPY %z ; CHECK-NEXT: PseudoBR %bb.1 bb.0: @@ -596,12 +596,12 @@ tracksRegLiveness: true body: | bb.0.entry: ; CHECK-LABEL: name: EMUL_is_unknown - ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 1, 0 /* e8 */ - ; CHECK-NEXT: [[PseudoVMOR_MM_B4_:%[0-9]+]]:vmv0 = PseudoVMOR_MM_B4 [[PseudoVMCLR_M_B4_]], [[PseudoVMCLR_M_B4_]], 1, 0 /* e8 */ + ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 1 /* vl */, 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVMOR_MM_B4_:%[0-9]+]]:vmv0 = PseudoVMOR_MM_B4 [[PseudoVMCLR_M_B4_]], [[PseudoVMCLR_M_B4_]], 1 /* vl */, 0 /* e8 */ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 - ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X $noreg, [[COPY]], 1, 5 /* e32 */ - ; CHECK-NEXT: [[PseudoVMV_V_I_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_I_M8 $noreg, 0, 1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: [[PseudoVREDMAX_VS_M8_E32_MASK:%[0-9]+]]:vrnov0 = PseudoVREDMAX_VS_M8_E32_MASK $noreg, killed [[PseudoVMV_V_I_M8_]], killed [[PseudoVMV_S_X]], [[PseudoVMOR_MM_B4_]], 1, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X $noreg, [[COPY]], 1 /* vl */, 5 /* e32 */ + ; CHECK-NEXT: [[PseudoVMV_V_I_M8_:%[0-9]+]]:vrm8 = PseudoVMV_V_I_M8 $noreg, 0, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVREDMAX_VS_M8_E32_MASK:%[0-9]+]]:vrnov0 = PseudoVREDMAX_VS_M8_E32_MASK $noreg, killed [[PseudoVMV_V_I_M8_]], killed [[PseudoVMV_S_X]], [[PseudoVMOR_MM_B4_]], 1 /* vl */, 5 /* e32 */, 1 /* ta, mu */ ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDMAX_VS_M8_E32_MASK]], 5 /* e32 */ ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -620,9 +620,9 @@ name: vleff_imm body: | bb.0: ; CHECK-LABEL: name: vleff_imm - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */ - ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */ - ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */ PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ @@ -636,9 +636,9 @@ body: | ; CHECK: liveins: $x8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */ - ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */ - ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl /* vl */, 3 /* e8 */ %avl:gprnox0 = COPY $x8 %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */ @@ -652,10 +652,10 @@ body: | ; CHECK-LABEL: name: vleff_reg_doesnt_dominate ; CHECK: liveins: $x8 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 3 /* ta, ma */ ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 - ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */ - ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ + ; CHECK-NEXT: %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ %avl:gprnox0 = COPY $x8 %y:vr, %vl:gprnox0 = PseudoVLE8FF_V_M1 $noreg, $noreg, %avl, 3 /* e8 */, 3 /* ta, ma */ @@ -666,9 +666,9 @@ name: vleff_mask_imm body: | bb.0: ; CHECK-LABEL: name: vleff_mask_imm - ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */ - ; CHECK-NEXT: %y:vrnov0, %vl:gprnox0 = PseudoVLE8FF_V_M1_MASK $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */ - ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %y:vrnov0, %vl:gprnox0 = PseudoVLE8FF_V_M1_MASK $noreg, $noreg, $noreg, 1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %x, $noreg, %vl /* vl */, 3 /* e8 */ %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 3 /* ta, ma */ %y:vrnov0, %vl:gprnox0 = PseudoVLE8FF_V_M1_MASK $noreg, $noreg, $noreg, 1, 3 /* e8 */, 3 /* ta, ma */ PseudoVSE8_V_M1 %x, $noreg, %vl, 3 /* e8 */ @@ -685,7 +685,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v10 ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrn4m1 = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrn4m1 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_vrm1_0 @@ -693,8 +693,8 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrn4m1 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoVADD_VV_M1_]], %subreg.sub_vrm1_2 ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrn4m1 = INSERT_SUBREG [[INSERT_SUBREG2]], [[COPY2]], %subreg.sub_vrm1_3 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm4 = COPY [[INSERT_SUBREG3]] - ; CHECK-NEXT: PseudoVSE32_V_M4 [[COPY3]], $noreg, 1, 5 /* e32 */ - ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, [[PseudoVADD_VV_M1_]], $noreg, 10, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: PseudoVSE32_V_M4 [[COPY3]], $noreg, 1 /* vl */, 5 /* e32 */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_1:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, [[PseudoVADD_VV_M1_]], $noreg, 10 /* vl */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: $v10 = COPY [[PseudoVADD_VV_M1_1]] ; CHECK-NEXT: PseudoRET implicit $v10 %0:vr = COPY $v8 @@ -722,18 +722,18 @@ body: | ; CHECK-NEXT: liveins: $x8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 - ; CHECK-NEXT: %start:vr = PseudoVMV_V_I_M1 $noreg, 0, %avl, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %start:vr = PseudoVMV_V_I_M1 $noreg, 0, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ ; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %phi:vr = PHI %start, %bb.0, %inc, %bb.1 - ; CHECK-NEXT: %inc:vr = PseudoVADD_VI_M1 $noreg, %phi, 1, %avl, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %inc:vr = PseudoVADD_VI_M1 $noreg, %phi, 1, %avl /* vl */, 3 /* e8 */, 3 /* ta, ma */ ; CHECK-NEXT: BNE $noreg, $noreg, %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: PseudoVSE8_V_M1 %inc, $noreg, %avl, 3 /* e8 */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %inc, $noreg, %avl /* vl */, 3 /* e8 */ bb.0: liveins: $x8 %avl:gprnox0 = COPY $x8 @@ -757,18 +757,18 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %avl1:gprnox0 = COPY $x8 ; CHECK-NEXT: %avl2:gprnox0 = COPY $x8 - ; CHECK-NEXT: %start:vr = PseudoVMV_V_I_M1 $noreg, 0, %avl1, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %start:vr = PseudoVMV_V_I_M1 $noreg, 0, %avl1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ ; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %phi:vr = PHI %start, %bb.0, %inc, %bb.1 - ; CHECK-NEXT: %inc:vr = PseudoVADD_VI_M1 $noreg, %phi, 1, %avl1, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: %inc:vr = PseudoVADD_VI_M1 $noreg, %phi, 1, %avl1 /* vl */, 3 /* e8 */, 3 /* ta, ma */ ; CHECK-NEXT: BNE $noreg, $noreg, %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: - ; CHECK-NEXT: PseudoVSE8_V_M1 %inc, $noreg, %avl2, 3 /* e8 */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %inc, $noreg, %avl2 /* vl */, 3 /* e8 */ bb.0: liveins: $x8, $x9 %avl1:gprnox0 = COPY $x8 @@ -801,8 +801,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %x:gprnox0 = COPY $x8 ; CHECK-NEXT: %y:gprnox0 = ADDI %x, -1 - ; CHECK-NEXT: %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %x, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %x /* vl */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ %x:gpr = COPY $x8 %y:gprnox0 = ADDI %x, -1 %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ @@ -819,8 +819,8 @@ body: | ; CHECK: liveins: $x8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %y:gprnox0 = ADDI $x0, -1 - ; CHECK-NEXT: %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ - ; CHECK-NEXT: %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ %y:gprnox0 = ADDI $x0, -1 %v:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */ %w:vr = PseudoVSLIDEDOWN_VX_M1 $noreg, %v, %y, 1, 5 /* e32 */, 0 /* tu, mu */ diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir b/llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir index 7525bf70e62d8..aaaf15b8feab2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-optimizer-subreg-assert.mir @@ -15,8 +15,8 @@ body: | ; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vmv0 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, killed [[DEF2]], [[DEF]], [[DEF1]], -1, 6 /* e64 */ - ; CHECK-NEXT: [[PseudoVREDMAXU_VS_M8_E64_:%[0-9]+]]:vr = PseudoVREDMAXU_VS_M8_E64 $noreg, [[PseudoVMERGE_VVM_M8_]], [[PseudoVMERGE_VVM_M8_]].sub_vrm1_0, -1, 6 /* e64 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 $noreg, killed [[DEF2]], [[DEF]], [[DEF1]], -1 /* vl=VLMAX */, 6 /* e64 */ + ; CHECK-NEXT: [[PseudoVREDMAXU_VS_M8_E64_:%[0-9]+]]:vr = PseudoVREDMAXU_VS_M8_E64 $noreg, [[PseudoVMERGE_VVM_M8_]], [[PseudoVMERGE_VVM_M8_]].sub_vrm1_0, -1 /* vl=VLMAX */, 6 /* e64 */, 1 /* ta, mu */ ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDMAXU_VS_M8_E64_]], 6 /* e64 */ ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] ; CHECK-NEXT: PseudoRET implicit $x10 diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll index 6b6276b838fba..e464be9feb6e3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll @@ -8,7 +8,7 @@ define i64 @test_vleff_nxv8i8(ptr %p, i64 %vl) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 - ; CHECK-NEXT: [[PseudoVLE8FF_V_M1_:%[0-9]+]]:vr, [[PseudoVLE8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1) + ; CHECK-NEXT: [[PseudoVLE8FF_V_M1_:%[0-9]+]]:vr, [[PseudoVLE8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1 $noreg, [[COPY1]], [[COPY]] /* vl */, 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1) ; CHECK-NEXT: $x10 = COPY [[PseudoVLE8FF_V_M1_1]] ; CHECK-NEXT: PseudoRET implicit $x10 entry: @@ -25,7 +25,7 @@ define i64 @test_vleff_nxv8i8_tu( %passthru, ptr %p, i64 %vl) { ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 - ; CHECK-NEXT: [[PseudoVLE8FF_V_M1_:%[0-9]+]]:vr, [[PseudoVLE8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1 [[COPY2]], [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1) + ; CHECK-NEXT: [[PseudoVLE8FF_V_M1_:%[0-9]+]]:vr, [[PseudoVLE8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1 [[COPY2]], [[COPY1]], [[COPY]] /* vl */, 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1) ; CHECK-NEXT: $x10 = COPY [[PseudoVLE8FF_V_M1_1]] ; CHECK-NEXT: PseudoRET implicit $x10 entry: @@ -44,7 +44,7 @@ define i64 @test_vleff_nxv8i8_mask( %maskedoff, ptr %p, )) - ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-LABEL: name: vleN_v_volatile + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */ :: (volatile load ()) + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 3 /* e8 */, 0 /* tu, mu */ %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 :: (volatile load ()) %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 ... diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll index 2ad7ac9390515..eff592aba0589 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll @@ -569,8 +569,8 @@ define @vmacc_vx_nxv64i8_unmasked( %a, i8 % define @vmacc_vv_nxv64i8_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmacc_vv_nxv64i8_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1076,8 +1076,8 @@ define @vmacc_vx_nxv32i16_unmasked( %a, i define @vmacc_vv_nxv32i16_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmacc_vv_nxv32i16_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1499,8 +1499,8 @@ define @vmacc_vx_nxv16i32_unmasked( %a, i define @vmacc_vv_nxv16i32_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmacc_vv_nxv16i32_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -2011,8 +2011,8 @@ define @vmacc_vx_nxv8i64_unmasked( %a, i64 define @vmacc_vv_nxv8i64_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmacc_vv_nxv8i64_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll index fe5b8b9bf6d52..cf94bcacf372c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll @@ -475,8 +475,9 @@ define @vmadd_vx_nxv32i8_ta( %a, i8 %b, @vmadd_vv_nxv64i8( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8r.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, mu +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e8, m8, tu, mu ; CHECK-NEXT: vmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) @@ -488,8 +489,9 @@ define @vmadd_vv_nxv64i8( %a, @vmadd_vv_nxv64i8_unmasked( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv64i8_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8r.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e8, m8, tu, ma ; CHECK-NEXT: vmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) @@ -529,8 +531,8 @@ define @vmadd_vx_nxv64i8_unmasked( %a, i8 % define @vmadd_vv_nxv64i8_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv64i8_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) @@ -946,8 +948,9 @@ define @vmadd_vx_nxv16i16_ta( %a, i16 %b, define @vmadd_vv_nxv32i16( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, mu +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, mu ; CHECK-NEXT: vmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) @@ -959,8 +962,9 @@ define @vmadd_vv_nxv32i16( %a, @vmadd_vv_nxv32i16_unmasked( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv32i16_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, ma +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, ma ; CHECK-NEXT: vmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) @@ -1000,8 +1004,8 @@ define @vmadd_vx_nxv32i16_unmasked( %a, i define @vmadd_vv_nxv32i16_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv32i16_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) @@ -1339,8 +1343,9 @@ define @vmadd_vx_nxv8i32_ta( %a, i32 %b, @vmadd_vv_nxv16i32( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, mu ; CHECK-NEXT: vmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) @@ -1352,8 +1357,9 @@ define @vmadd_vv_nxv16i32( %a, @vmadd_vv_nxv16i32_unmasked( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv16i32_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, ma ; CHECK-NEXT: vmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) @@ -1393,8 +1399,8 @@ define @vmadd_vx_nxv16i32_unmasked( %a, i define @vmadd_vv_nxv16i32_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv16i32_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) @@ -1786,8 +1792,9 @@ define @vmadd_vx_nxv4i64_ta( %a, i64 %b, @vmadd_vv_nxv8i64( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, mu +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e64, m8, tu, mu ; CHECK-NEXT: vmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) @@ -1799,8 +1806,9 @@ define @vmadd_vv_nxv8i64( %a, @vmadd_vv_nxv8i64_unmasked( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv8i64_unmasked: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli zero, zero, e64, m8, tu, ma ; CHECK-NEXT: vmadd.vv v8, v16, v24 ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) @@ -1870,8 +1878,8 @@ define @vmadd_vx_nxv8i64_unmasked( %a, i64 define @vmadd_vv_nxv8i64_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmadd_vv_nxv8i64_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll index 3cf464247250a..99f3cf9912380 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll @@ -8,12 +8,9 @@ define @vmax_vx_nxv8i7( %a, i7 signext %b, poison, i7 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax.ll b/llvm/test/CodeGen/RISCV/rvv/vmax.ll index e90ccc7f21291..25ecbf31fed0f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll index e755d099df4a8..ea9cf170dd35d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll @@ -10,8 +10,8 @@ define @vmaxu_vx_nxv8i7( %a, i7 signext %b, < ; CHECK-NEXT: li a2, 127 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.x v9, a0 -; CHECK-NEXT: vand.vx v8, v8, a2, v0.t -; CHECK-NEXT: vand.vx v9, v9, a2, v0.t +; CHECK-NEXT: vand.vx v8, v8, a2 +; CHECK-NEXT: vand.vx v9, v9, a2 ; CHECK-NEXT: vmaxu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement poison, i7 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu.ll index 96e7e3df34955..32e372c100baa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir index 9d9ef6991955f..d24b87a1d2619 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir @@ -12,7 +12,7 @@ body: | ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) %avl:gprnox0 = COPY $x8 %passthru:vrnov0 = COPY $v8 %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) @@ -30,7 +30,7 @@ body: | ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 ; CHECK-NEXT: %false:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %false, $noreg, %mask, %avl, 5 /* e32 */, 1 /* ta, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %false, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 1 /* ta, mu */ :: (load unknown-size, align 1) %avl:gprnox0 = COPY $x8 %false:vrnov0 = COPY $v8 %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) @@ -48,7 +48,7 @@ body: | ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %y:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) %avl:gprnox0 = COPY $x8 %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) %passthru:vrnov0 = COPY $v8 @@ -66,7 +66,7 @@ body: | ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %y:vrnov0 = PseudoVNCLIPU_WV_MF2_MASK %passthru, $noreg, $noreg, %mask, 0, %avl, 5 /* e32 */, 0 /* tu, mu */, implicit-def $vxsat + ; CHECK-NEXT: %y:vrnov0 = PseudoVNCLIPU_WV_MF2_MASK %passthru, $noreg, $noreg, %mask, 0 /* vxrm=rnu */, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit-def $vxsat %avl:gprnox0 = COPY $x8 %x:vrnov0 = PseudoVNCLIPU_WV_MF2 $noreg, $noreg, $noreg, 0, -1, 5, 3, implicit-def $vxsat %passthru:vrnov0 = COPY $v8 @@ -82,11 +82,11 @@ body: | ; CHECK: liveins: $x8, $v0, $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 - ; CHECK-NEXT: %x:vrnov0 = PseudoVNCLIPU_WV_MF2 $noreg, $noreg, $noreg, 0, -1, 5 /* e32 */, 3 /* ta, ma */, implicit-def $vxsat + ; CHECK-NEXT: %x:vrnov0 = PseudoVNCLIPU_WV_MF2 $noreg, $noreg, $noreg, 0 /* vxrm=rnu */, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */, implicit-def $vxsat ; CHECK-NEXT: %vxsat:gpr = COPY $vxsat ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %x, %mask, %avl, 5 /* e32 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %x, %mask, %avl /* vl */, 5 /* e32 */ %avl:gprnox0 = COPY $x8 %x:vrnov0 = PseudoVNCLIPU_WV_MF2 $noreg, $noreg, $noreg, 0, -1, 5, 3, implicit-def $vxsat %vxsat:gpr = COPY $vxsat @@ -107,7 +107,7 @@ body: | ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 ; CHECK-NEXT: %x:vr = COPY $v9 ; CHECK-NEXT: %y:vr = COPY $v10 - ; CHECK-NEXT: %vmerge:vrnov0 = nofpexcept PseudoVFMACC_VV_M1_E32_MASK %passthru, %y, %x, %mask, 7, %avl, 5 /* e32 */, 0 /* tu, mu */, implicit $frm + ; CHECK-NEXT: %vmerge:vrnov0 = nofpexcept PseudoVFMACC_VV_M1_E32_MASK %passthru, %y, %x, %mask, 7 /* frm=dyn */, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $frm %avl:gprnox0 = COPY $x8 %mask:vmv0 = COPY $v0 %passthru:vrnov0 = COPY $v8 @@ -127,7 +127,7 @@ body: | ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %z:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %z:vrnov0 = PseudoVLE32_V_M1_MASK %passthru, $noreg, %mask, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) %avl:gprnox0 = COPY $x8 %passthru:vrnov0 = COPY $v8 %x:vr = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) @@ -146,9 +146,9 @@ body: | ; CHECK-NEXT: %x:vr = COPY $v8 ; CHECK-NEXT: %y:vr = COPY $v9 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %add0:vr = PseudoVADD_VV_M1 $noreg, %x, %y, -1, 5 /* e32 */, 3 /* ta, ma */ + ; CHECK-NEXT: %add0:vr = PseudoVADD_VV_M1 $noreg, %x, %y, -1 /* vl=VLMAX */, 5 /* e32 */, 3 /* ta, ma */ ; CHECK-NEXT: %add1:vrnov0 = COPY %add:vrnov0 - ; CHECK-NEXT: %merge:vrnov0 = PseudoVOR_VV_M1_MASK %add:vrnov0, %add1, %y, %mask, -1, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: %merge:vrnov0 = PseudoVOR_VV_M1_MASK %add:vrnov0, %add1, %y, %mask, -1 /* vl=VLMAX */, 5 /* e32 */, 1 /* ta, mu */ %x:vr = COPY $v8 %y:vr = COPY $v9 %mask:vmv0 = COPY $v0 @@ -168,11 +168,11 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 - ; CHECK-NEXT: %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl /* vl */, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 1) ; CHECK-NEXT: %copy:vrnov0 = COPY %x ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: PseudoVSE8_V_M1 %copy, $noreg, %avl, 5 /* e32 */ - ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %copy, %mask, %avl, 5 /* e32 */ + ; CHECK-NEXT: PseudoVSE8_V_M1 %copy, $noreg, %avl /* vl */, 5 /* e32 */ + ; CHECK-NEXT: %y:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %copy, %mask, %avl /* vl */, 5 /* e32 */ %avl:gprnox0 = COPY $x8 %passthru:vrnov0 = COPY $v8 %x:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, %avl, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size) @@ -192,7 +192,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF - ; CHECK-NEXT: early-clobber %5:vrm8nov0 = PseudoVZEXT_VF8_M8_MASK $noreg, $noreg, [[DEF]], 16, 6 /* e64 */, 1 /* ta, mu */ + ; CHECK-NEXT: early-clobber %5:vrm8nov0 = PseudoVZEXT_VF8_M8_MASK $noreg, $noreg, [[DEF]], 16 /* vl */, 6 /* e64 */, 1 /* ta, mu */ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY %5 ; CHECK-NEXT: PseudoRET bb.0: @@ -211,3 +211,35 @@ body: | %125:vrm8 = COPY %121 PseudoRET ... +--- +name: increase_vl +body: | + bb.0: + ; CHECK-LABEL: name: increase_vl + ; CHECK: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %merge:vrnov0 = PseudoVADD_VV_M1_MASK %passthru, %x:vr, %y:vr, %mask, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */ + %passthru:vrnov0 = COPY $v8 + %avl:gprnox0 = COPY $x8 + %mask:vmv0 = COPY $v0 + %add:vrnov0 = PseudoVADD_VV_M1 $noreg, %x:vr, %y:vr, 1, 5 /* e32 */, 0 /* tu, mu */ + %merge:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %add, %mask, %avl, 5 /* e32 */ +... +--- +# Negative test: Shouldn't fold vmerge into the load because we may increase vl. +name: increase_vl_load +body: | + bb.0: + ; CHECK-LABEL: name: increase_vl_load + ; CHECK: %passthru:vrnov0 = COPY $v8 + ; CHECK-NEXT: %avl:gprnox0 = COPY $x8 + ; CHECK-NEXT: %mask:vmv0 = COPY $v0 + ; CHECK-NEXT: %load:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %merge:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %load, %mask, %avl /* vl */, 5 /* e32 */ + %passthru:vrnov0 = COPY $v8 + %avl:gprnox0 = COPY $x8 + %mask:vmv0 = COPY $v0 + %load:vrnov0 = PseudoVLE32_V_M1 $noreg, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size) + %merge:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, %load, %mask, %avl, 5 /* e32 */ +... diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll index 961f63cbfbc95..4c6995f3b6b3f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll @@ -8,12 +8,9 @@ define @vmin_vx_nxv8i7( %a, i7 signext %b, poison, i7 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin.ll b/llvm/test/CodeGen/RISCV/rvv/vmin.ll index edd643f08ee43..803482f55c920 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll index 631799d24e14c..75b5aa84fc42f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll @@ -10,8 +10,8 @@ define @vminu_vx_nxv8i7( %a, i7 signext %b, < ; CHECK-NEXT: li a2, 127 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.x v9, a0 -; CHECK-NEXT: vand.vx v8, v8, a2, v0.t -; CHECK-NEXT: vand.vx v9, v9, a2, v0.t +; CHECK-NEXT: vand.vx v8, v8, a2 +; CHECK-NEXT: vand.vx v9, v9, a2 ; CHECK-NEXT: vminu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement poison, i7 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu.ll b/llvm/test/CodeGen/RISCV/rvv/vminu.ll index 251f833d75faa..198b0d502d77e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul.ll b/llvm/test/CodeGen/RISCV/rvv/vmul.ll index 90b44c6e6800c..f8e559da9ca4a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul.ll @@ -225,8 +225,8 @@ entry: define @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -424,8 +424,8 @@ entry: define @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ entry: define @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -723,8 +723,8 @@ entry: define @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh.ll index bd2eac51207c1..c3e699d5040f4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulh.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulh.ll @@ -227,8 +227,8 @@ entry: define @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -426,8 +426,8 @@ entry: define @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -592,8 +592,8 @@ entry: define @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -725,8 +725,8 @@ entry: define @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll index 90ec0a6766e24..107e56a77d90c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll @@ -227,8 +227,8 @@ entry: define @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -426,8 +426,8 @@ entry: define @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -592,8 +592,8 @@ entry: define @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -725,8 +725,8 @@ entry: define @intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu.ll index 8c0d7ffb5084c..dd22099446bb1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulhu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu.ll @@ -227,8 +227,8 @@ entry: define @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -426,8 +426,8 @@ entry: define @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -592,8 +592,8 @@ entry: define @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -725,8 +725,8 @@ entry: define @intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir b/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir index ccabd5099071b..aba2e48b1e159 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir @@ -13,8 +13,8 @@ body: | ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2, implicit $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2, implicit $vtype, implicit $v28m2 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $v12m2 = COPY $v28m2 @@ -29,8 +29,8 @@ body: | ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $v28m4 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $v12m4 = COPY $v28m4 @@ -45,8 +45,8 @@ body: | ; CHECK: liveins: $x14 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v12m4 = PseudoVMV_V_I_M4 undef $v12m4, 0, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = PseudoVMV_V_I_M4 undef $v12m4, 0, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $v28m4 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5, 0, implicit $vl, implicit $vtype $v12m4 = COPY $v28m4 @@ -62,7 +62,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $v28m4 = VL4RE32_V $x16 - ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = VL4RE32_V $x16 $v12m4 = COPY $v28m4 @@ -77,9 +77,9 @@ body: | ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v4m4, $x0 = PseudoVLE32FF_V_M4 undef $v4m4, $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit-def $vl - ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype + ; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v4m4, $x0 = PseudoVLE32FF_V_M4 undef $v4m4, $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit-def $vl + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5, 0, implicit $vl, implicit $vtype $v4m4,$x0 = PseudoVLE32FF_V_M4 undef $v4m4, $x16, $noreg, 5, 0, implicit-def $vl @@ -95,12 +95,12 @@ body: | ; CHECK: liveins: $x14, $x16, $x17, $x18 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x15 = PseudoVSETVLI $x17, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype + ; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $x15 = PseudoVSETVLI $x17, 73, implicit-def $vl, implicit-def $vtype @@ -119,12 +119,12 @@ body: | ; CHECK: liveins: $x14, $x16, $x17, $x18 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = PseudoVMV_V_V_M4 undef $v12m4, $v28m4, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $v28m4 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $x0 = PseudoVSETVLIX0X0 $x0, 73, implicit-def $vl, implicit-def $vtype @@ -143,10 +143,10 @@ body: | ; CHECK: liveins: $x14, $x16, $x17, $x18 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype + ; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $x0 = PseudoVSETVLIX0X0 $x0, 73, implicit-def $vl, implicit-def $vtype @@ -163,10 +163,10 @@ body: | ; CHECK: liveins: $x16, $x17 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETIVLI 4, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: early-clobber $v28m4 = PseudoVWADD_VV_M2 undef $v28m4, $v26m2, $v8m2, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2, implicit $vtype + ; CHECK-NEXT: $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber $v28m4 = PseudoVWADD_VV_M2 undef $v28m4, $v26m2, $v8m2, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2, implicit $vtype, implicit $v28m2 $x15 = PseudoVSETIVLI 4, 73, implicit-def $vl, implicit-def $vtype $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4, 0, implicit $vl, implicit $vtype $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4, 0, implicit $vl, implicit $vtype @@ -184,9 +184,9 @@ body: | ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLIX0X0 $x0, 74 /* e16, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype + ; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype, implicit $v28m4 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $x0 = PseudoVSETVLIX0X0 $x0, 74, implicit-def $vl, implicit-def $vtype @@ -202,8 +202,8 @@ body: | ; CHECK: liveins: $x10, $v8, $v26, $v27 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x11 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v8 = PseudoVWREDSUM_VS_M1_E8 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v26 = VMV1R_V killed $v8, implicit $vtype + ; CHECK-NEXT: $v8 = PseudoVWREDSUM_VS_M1_E8 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1 /* vl */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v26 = VMV1R_V killed $v8, implicit $vtype, implicit $v8 ; CHECK-NEXT: $x10 = PseudoVSETVLI killed renamable $x10, 75 /* e16, m8, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $v8m8 = VL8RE8_V killed $x10 $x11 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype @@ -222,8 +222,8 @@ body: | ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v10 = VMV1R_V $v8, implicit $vtype + ; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v10 = VMV1R_V $v8, implicit $vtype, implicit $v8 $x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $v10 = COPY $v8 @@ -238,8 +238,8 @@ body: | ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v10m2 = VMV2R_V $v8m2, implicit $vtype + ; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v10m2 = VMV2R_V $v8m2, implicit $vtype, implicit $v8_v9 $x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $v10_v11 = COPY $v8_v9 @@ -254,8 +254,8 @@ body: | ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 87 /* e32, mf2, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v28 = PseudoVLE32_V_MF2 undef $v28, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v12 = VMV1R_V $v28, implicit $vtype + ; CHECK-NEXT: $v28 = PseudoVLE32_V_MF2 undef $v28, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v12 = VMV1R_V $v28, implicit $vtype, implicit $v28 $x15 = PseudoVSETVLI $x14, 87, implicit-def $vl, implicit-def $vtype $v28 = PseudoVLE32_V_MF2 undef $v28, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $v12 = COPY $v28 @@ -270,10 +270,10 @@ body: | ; CHECK: liveins: $x12, $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x0 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x0 = PseudoVSETIVLI 10, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v15 = PseudoVLE32_V_M1 undef $v15, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit killed $v8_v9_v10_v11_v12_v13_v14_v15, implicit-def $v8_v9_v10_v11_v12_v13_v14_v15 - ; CHECK-NEXT: $v24m8 = VMV8R_V killed $v8m8, implicit $vtype + ; CHECK-NEXT: $v15 = PseudoVLE32_V_M1 undef $v15, killed $x16, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit killed $v8_v9_v10_v11_v12_v13_v14_v15, implicit-def $v8_v9_v10_v11_v12_v13_v14_v15 + ; CHECK-NEXT: $v24m8 = VMV8R_V killed $v8m8, implicit $vtype, implicit $v8_v9_v10_v11_v12_v13_v14_v15 $x0 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype $v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg, 5, 0, implicit $vl, implicit $vtype $x0 = PseudoVSETIVLI 10, 80, implicit-def $vl, implicit-def $vtype @@ -290,8 +290,8 @@ body: | ; CHECK: liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m4 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 66 /* e8, m4, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: early-clobber $v4m4 = PseudoSF_VQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v16m4 = PseudoVMV_V_V_M4 undef $v16m4, $v4m4, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber $v4m4 = PseudoSF_VQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg /* vl */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v16m4 = PseudoVMV_V_V_M4 undef $v16m4, $v4m4, $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $v4m4 $x0 = PseudoVSETVLI $x10, 66, implicit-def $vl, implicit-def $vtype early-clobber $v4m4 = PseudoSF_VQMACCUS_2x8x2_M4 renamable $v4m4, killed renamable $v13, killed renamable $v16m4, $noreg, 3, 1, implicit $vl, implicit $vtype $v16m4 = COPY renamable $v4m4 @@ -306,8 +306,8 @@ body: | ; CHECK: liveins: $x2, $x10, $v8, $v13, $v4m4, $v16m2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 65 /* e8, m2, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: early-clobber $v4m4 = PseudoSF_VQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v16m4 = VMV4R_V $v4m4, implicit $vtype + ; CHECK-NEXT: early-clobber $v4m4 = PseudoSF_VQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg /* vl */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v16m4 = VMV4R_V $v4m4, implicit $vtype, implicit $v4m4 $x0 = PseudoVSETVLI $x10, 65, implicit-def $vl, implicit-def $vtype early-clobber $v4m4 = PseudoSF_VQMACCUS_4x8x4_M2 renamable $v4m4, killed renamable $v13, killed renamable $v16m2, $noreg, 3, 1, implicit $vl, implicit $vtype $v16m4 = COPY renamable $v4m4 @@ -322,10 +322,10 @@ body: | ; CHECK: liveins: $x10, $x11, $v8, $v9 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 201 /* e16, m2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v10m2 = PseudoVLE16_V_M2 undef $v10m2, killed $x11, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v10 = VMV1R_V $v8, implicit $vtype - ; CHECK-NEXT: $v11 = VMV1R_V $v9, implicit $vtype - ; CHECK-NEXT: $v12m2 = VMV2R_V $v10m2, implicit $vtype + ; CHECK-NEXT: $v10m2 = PseudoVLE16_V_M2 undef $v10m2, killed $x11, $noreg /* vl */, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v10 = VMV1R_V $v8, implicit $vtype, implicit $v8 + ; CHECK-NEXT: $v11 = VMV1R_V $v9, implicit $vtype, implicit $v9 + ; CHECK-NEXT: $v12m2 = VMV2R_V $v10m2, implicit $vtype, implicit $v10m2 $x0 = PseudoVSETVLI $x10, 201, implicit-def $vl, implicit-def $vtype $v10m2 = PseudoVLE16_V_M2 undef $v10m2, killed $x11, $noreg, 4, 0, implicit $vl, implicit $vtype $v10 = COPY $v8 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir index 68e74ff6ba05b..61dd49a42fffa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir @@ -11,7 +11,7 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %passthru:vr = COPY $v8 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: %y:gpr = ADDI $x0, 1 %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ %passthru:vr = COPY $v8 @@ -27,7 +27,7 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %passthru:vr = COPY $v8 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */ %passthru:vr = COPY $v8 %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ %y:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 1 /* ta, mu */ @@ -41,7 +41,7 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %passthru:vr = COPY $v8 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ %passthru:vr = COPY $v8 %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ %y:vr = PseudoVMV_V_V_M1 %passthru, %x, 5, 5 /* e32 */, 1 /* ta, mu */ @@ -55,7 +55,7 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %passthru:vr = COPY $v8 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */ %passthru:vr = COPY $v8 %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 0 /* tu, mu */ @@ -69,7 +69,7 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %passthru:vr = COPY $v8 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */ %passthru:vr = COPY $v8 %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */ @@ -84,8 +84,8 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %passthru:vr = COPY $v8 - ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 %passthru, $noreg, $noreg, 4, 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_MF8 %passthru, %x, 4, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF4 %passthru, $noreg, $noreg, 4 /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_MF8 %passthru, %x, 4 /* vl */, 3 /* e8 */, 0 /* tu, mu */ %passthru:vr = COPY $v8 %x:vr = PseudoVADD_VV_MF4 %passthru, $noreg, $noreg, 4, 4 /* e16 */, 0 /* tu, mu */ %y:vr = PseudoVMV_V_V_MF8 %passthru, %x, 4, 3 /* e8 */, 0 /* tu, mu */ @@ -96,7 +96,7 @@ tracksRegLiveness: true body: | bb.0: ; CHECK-LABEL: name: kill_flag - ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1 /* vl=VLMAX */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY [[PseudoVADD_VV_M1_]] ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY [[PseudoVADD_VV_M1_]] %0:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ @@ -112,9 +112,9 @@ body: | ; CHECK-LABEL: name: diff_regclass ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0 /* vl */, 5 /* e32 */, 1 /* ta, mu */ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8 - ; CHECK-NEXT: [[PseudoVADD_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVADD_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */ %1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */ %2:vmv0 = COPY $v8 @@ -128,9 +128,9 @@ body: | ; CHECK-LABEL: name: diff_regclass_passthru ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0 /* vl */, 5 /* e32 */, 1 /* ta, mu */ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8 - ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4) + ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4) %2:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */ %3:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */ %7:vmv0 = COPY $v8 @@ -145,7 +145,7 @@ body: | ; CHECK: liveins: $v8 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %passthru:vr = COPY $v8 - ; CHECK-NEXT: %x:vr, %vl:gpr = PseudoVLE32FF_V_M1 %passthru, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) + ; CHECK-NEXT: %x:vr, %vl:gpr = PseudoVLE32FF_V_M1 %passthru, $noreg, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1) ; CHECK-NEXT: %y:gpr = ADDI $x0, 1 %x:vr, %vl:gpr = PseudoVLE32FF_V_M1 $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size) %passthru:vr = COPY $v8 @@ -162,7 +162,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 ; CHECK-NEXT: %mask:vmv0 = COPY $v0 - ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, $noreg, %mask, 4, 5 /* e32 */ + ; CHECK-NEXT: %x:vrnov0 = PseudoVMERGE_VVM_M1 %passthru, %passthru, $noreg, %mask, 4 /* vl */, 5 /* e32 */ %passthru:vrnov0 = COPY $v8 %mask:vmv0 = COPY $v0 %x:vrnov0 = PseudoVMERGE_VVM_M1 $noreg, %passthru, $noreg, %mask, 4, 5 /* e32 */ @@ -180,7 +180,7 @@ body: | ; CHECK-NEXT: %passthru:vrnov0 = COPY $v8 ; CHECK-NEXT: %x:vr = COPY $v9 ; CHECK-NEXT: %y:vr = COPY $v10 - ; CHECK-NEXT: %vfmadd:vrnov0 = nofpexcept PseudoVFMACC_VV_M1_E32 %passthru, %y, %x, 7, %avl, 5 /* e32 */, 0 /* tu, mu */, implicit $frm + ; CHECK-NEXT: %vfmadd:vrnov0 = nofpexcept PseudoVFMACC_VV_M1_E32 %passthru, %y, %x, 7 /* frm=dyn */, %avl /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $frm %avl:gprnox0 = COPY $x8 %passthru:vrnov0 = COPY $v8 %x:vr = COPY $v9 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir b/llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir index 433d571080e37..5125d076bd255 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmv0-elimination.mir @@ -16,7 +16,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %x:vr = COPY $v8 ; CHECK-NEXT: $v0 = COPY %x - ; CHECK-NEXT: PseudoVSE8_V_M1_MASK $noreg, $noreg, $v0, -1, 3 /* e8 */ + ; CHECK-NEXT: PseudoVSE8_V_M1_MASK $noreg, $noreg, $v0, -1 /* vl=VLMAX */, 3 /* e8 */ %x:vr = COPY $v8 %y:vmv0 = COPY %x:vr PseudoVSE8_V_M1_MASK $noreg, $noreg, %y:vmv0, -1, 3 diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll index 1c4294990f90a..9a463a79c3385 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll @@ -569,8 +569,8 @@ define @vnmsac_vx_nxv64i8_unmasked( %a, i8 define @vnmsac_vv_nxv64i8_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vnmsac_vv_nxv64i8_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vnmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1076,8 +1076,8 @@ define @vnmsac_vx_nxv32i16_unmasked( %a, define @vnmsac_vv_nxv32i16_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vnmsac_vv_nxv32i16_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vnmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -1499,8 +1499,8 @@ define @vnmsac_vx_nxv16i32_unmasked( %a, define @vnmsac_vv_nxv16i32_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vnmsac_vv_nxv16i32_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vnmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret @@ -2011,8 +2011,8 @@ define @vnmsac_vx_nxv8i64_unmasked( %a, i64 define @vnmsac_vv_nxv8i64_ta( %a, %b, %c, %m, i32 zeroext %evl) { ; CHECK-LABEL: vnmsac_vv_nxv8i64_ta: ; CHECK: # %bb.0: -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vnmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vor.ll b/llvm/test/CodeGen/RISCV/rvv/vor.ll index f5d0f2383cce3..c8720a6b40df0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vor.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll index d7d767e600db5..20a055845ee43 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll @@ -359,27 +359,27 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract( % ; RV32: # %bb.0: ; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; RV32-NEXT: vmv1r.v v8, v0 -; RV32-NEXT: slli a2, a1, 1 ; RV32-NEXT: vmv.v.i v9, 0 -; RV32-NEXT: li a3, -1 -; RV32-NEXT: vmerge.vim v10, v9, 1, v0 -; RV32-NEXT: vwaddu.vv v11, v10, v10 -; RV32-NEXT: vwmaccu.vx v11, a3, v10 -; RV32-NEXT: csrr a3, vlenb -; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma +; RV32-NEXT: li a2, -1 +; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; RV32-NEXT: vmv.v.i v10, 0 -; RV32-NEXT: srli a3, a3, 2 +; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma -; RV32-NEXT: vmsne.vi v0, v11, 0 -; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; RV32-NEXT: vslidedown.vx v11, v11, a3 -; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma +; RV32-NEXT: vmerge.vim v11, v9, 1, v0 +; RV32-NEXT: srli a3, a3, 2 +; RV32-NEXT: vwaddu.vv v12, v11, v11 +; RV32-NEXT: vwmaccu.vx v12, a2, v11 +; RV32-NEXT: vmsne.vi v0, v12, 0 +; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma +; RV32-NEXT: vslidedown.vx v11, v12, a3 ; RV32-NEXT: vmerge.vim v10, v10, 1, v0 -; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma +; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; RV32-NEXT: vmsne.vi v0, v11, 0 +; RV32-NEXT: slli a2, a1, 1 ; RV32-NEXT: vmerge.vim v9, v9, 1, v0 -; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma +; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; RV32-NEXT: vslideup.vx v10, v9, a3 +; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma ; RV32-NEXT: vmsne.vi v0, v10, 0 ; RV32-NEXT: vle32.v v10, (a0), v0.t ; RV32-NEXT: li a2, 32 @@ -503,30 +503,30 @@ define {, } @not_same_mask( ; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; RV32-NEXT: vmv1r.v v9, v0 ; RV32-NEXT: vmv1r.v v0, v8 -; RV32-NEXT: slli a1, a1, 1 ; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: li a2, -1 -; RV32-NEXT: vmerge.vim v10, v8, 1, v0 +; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma +; RV32-NEXT: vmv.v.i v10, 0 +; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma +; RV32-NEXT: vmerge.vim v11, v8, 1, v0 ; RV32-NEXT: vmv1r.v v0, v9 ; RV32-NEXT: vmerge.vim v9, v8, 1, v0 -; RV32-NEXT: vwaddu.vv v11, v9, v10 -; RV32-NEXT: vwmaccu.vx v11, a2, v10 +; RV32-NEXT: vwaddu.vv v12, v9, v11 +; RV32-NEXT: vwmaccu.vx v12, a2, v11 ; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma -; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: srli a2, a2, 2 -; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma -; RV32-NEXT: vmsne.vi v0, v11, 0 +; RV32-NEXT: vmsne.vi v0, v12, 0 ; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma -; RV32-NEXT: vslidedown.vx v10, v11, a2 -; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma -; RV32-NEXT: vmerge.vim v9, v9, 1, v0 +; RV32-NEXT: vslidedown.vx v9, v12, a2 +; RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma -; RV32-NEXT: vmsne.vi v0, v10, 0 +; RV32-NEXT: vmsne.vi v0, v9, 0 +; RV32-NEXT: slli a1, a1, 1 ; RV32-NEXT: vmerge.vim v8, v8, 1, v0 +; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma +; RV32-NEXT: vslideup.vx v10, v8, a2 ; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma -; RV32-NEXT: vslideup.vx v9, v8, a2 -; RV32-NEXT: vmsne.vi v0, v9, 0 +; RV32-NEXT: vmsne.vi v0, v10, 0 ; RV32-NEXT: vle32.v v10, (a0), v0.t ; RV32-NEXT: li a0, 32 ; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll index b65663d30672f..56b8abc374380 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll @@ -8,12 +8,9 @@ define @vrem_vx_nxv8i7( %a, i7 signext %b, poison, i7 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem.ll b/llvm/test/CodeGen/RISCV/rvv/vrem.ll index a9b1cef3984e8..8f8b3d479489f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll index 51448f2050b6b..82137b828c7ac 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll @@ -10,8 +10,8 @@ define @vremu_vx_nxv8i7( %a, i7 signext %b, < ; CHECK-NEXT: li a2, 127 ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vmv.v.x v9, a0 -; CHECK-NEXT: vand.vx v8, v8, a2, v0.t -; CHECK-NEXT: vand.vx v9, v9, a2, v0.t +; CHECK-NEXT: vand.vx v8, v8, a2 +; CHECK-NEXT: vand.vx v9, v9, a2 ; CHECK-NEXT: vremu.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret %elt.head = insertelement poison, i7 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu.ll b/llvm/test/CodeGen/RISCV/rvv/vremu.ll index c1a49f45e5d5b..bb58cacbaf835 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vrol.ll b/llvm/test/CodeGen/RISCV/rvv/vrol.ll index 959bb96781621..af57eace297c9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrol.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrol.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vrol_mask_vv_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vrol_mask_vv_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vrol.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vrol_mask_vv_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vrol_mask_vv_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vrol.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vrol_mask_vv_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vrol_mask_vv_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vrol.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vrol_mask_vv_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vrol_mask_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vrol.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vror.ll b/llvm/test/CodeGen/RISCV/rvv/vror.ll index 1f3114ab152e1..3d5897c9ac61c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vror.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vror.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vror_mask_vv_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vror_mask_vv_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vror.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vror_mask_vv_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vror_mask_vv_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vror.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vror_mask_vv_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vror_mask_vv_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vror.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vror_mask_vv_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vror_mask_vv_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vror.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd.ll index 4d16bb467fa46..a9ba200b70b11 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu.ll index 032c9057aa0c8..288ab363dbe56 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll index d1933560f2698..c05f209a1bb0e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll @@ -342,22 +342,22 @@ define @select_nxv32i32( %a, @select_evl_nxv32i32( %a, %b, %c) { ; RV32-LABEL: select_evl_nxv32i32: ; RV32: # %bb.0: -; RV32-NEXT: vl8re32.v v24, (a0) ; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma +; RV32-NEXT: vle32.v v24, (a0) ; RV32-NEXT: vmerge.vvm v8, v24, v8, v0 ; RV32-NEXT: slli a2, a1, 3 ; RV32-NEXT: add a0, a0, a2 ; RV32-NEXT: slli a2, a1, 1 -; RV32-NEXT: sub a2, a1, a2 ; RV32-NEXT: vl8re32.v v24, (a0) -; RV32-NEXT: sltu a0, a1, a2 -; RV32-NEXT: addi a0, a0, -1 -; RV32-NEXT: srli a1, a1, 2 +; RV32-NEXT: srli a0, a1, 2 +; RV32-NEXT: sub a2, a1, a2 +; RV32-NEXT: sltu a1, a1, a2 +; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma -; RV32-NEXT: vslidedown.vx v0, v0, a1 -; RV32-NEXT: and a0, a0, a2 -; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; RV32-NEXT: vslidedown.vx v0, v0, a0 +; RV32-NEXT: and a1, a1, a2 +; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vmerge.vvm v16, v24, v16, v0 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir index 5e81b832381b6..498c44ffaef8e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir @@ -16,7 +16,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v10m2 = PseudoVMV_V_I_M2 undef renamable $v10m2, 0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v10m2 = PseudoVMV_V_I_M2 undef renamable $v10m2, 0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.2(0x7c000000) @@ -30,8 +30,8 @@ body: | ; CHECK-NEXT: liveins: $v8m2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x0 = PseudoVSETVLI [[DEF]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v10 = PseudoVMV_S_X undef renamable $v10, undef %2:gpr, $noreg, 5 /* e32 */, implicit $vl, implicit $vtype - ; CHECK-NEXT: dead renamable $v8 = PseudoVREDSUM_VS_M2_E32 undef renamable $v8, killed undef renamable $v8m2, killed undef renamable $v10, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v10 = PseudoVMV_S_X undef renamable $v10, undef %2:gpr, $noreg /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead renamable $v8 = PseudoVREDSUM_VS_M2_E32 undef renamable $v8, killed undef renamable $v8m2, killed undef renamable $v10, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: BNE undef %3:gpr, $x0, %bb.1 ; CHECK-NEXT: PseudoBR %bb.4 ; CHECK-NEXT: {{ $}} diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir index a35100654432c..84182ccf9ff32 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir @@ -178,23 +178,23 @@ body: | ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2 ; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1.if.then: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3.if.end: - ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8 bb.0.entry: successors: %bb.2(0x30000000), %bb.1(0x50000000) @@ -255,7 +255,7 @@ body: | ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY2]], $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY2]], $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2 ; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: {{ $}} @@ -263,17 +263,17 @@ body: | ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: early-clobber %9:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %9:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: early-clobber %9:vr = PseudoVSEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %9:vr = PseudoVSEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3.if.end: - ; CHECK-NEXT: PseudoVSE64_V_M1 %9, [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE64_V_M1 %9, [[COPY1]], $noreg /* vl */, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET bb.0.entry: successors: %bb.2(0x30000000), %bb.1(0x50000000) @@ -340,14 +340,14 @@ body: | ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY1]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY1]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVADD_VV_M1_]], 6 /* e64 */, implicit $vtype @@ -418,16 +418,16 @@ body: | ; CHECK-NEXT: bb.1.if.then: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3.if.end: - ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] + ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8 bb.0.entry: successors: %bb.2(0x30000000), %bb.1(0x50000000) @@ -480,19 +480,19 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 undef $noreg, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 undef $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 undef $noreg, 0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 [[PseudoVID_V_MF2_]], 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]] + ; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 [[PseudoVID_V_MF2_]], 0, -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]], implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY]], $v0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY]], $v0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSEQ_VI_MF2_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSEQ_VI_MF2_]], -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF ; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3 ; CHECK-NEXT: PseudoBR %bb.2 @@ -504,8 +504,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: [[PseudoVADD_VX_MF2_:%[0-9]+]]:vr = nsw PseudoVADD_VX_MF2 undef $noreg, [[PseudoVLE32_V_MF2_MASK]], [[DEF]], -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v0 = COPY [[PseudoVADD_VX_MF2_]] + ; CHECK-NEXT: [[PseudoVADD_VX_MF2_:%[0-9]+]]:vr = nsw PseudoVADD_VX_MF2 undef $noreg, [[PseudoVLE32_V_MF2_MASK]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = COPY [[PseudoVADD_VX_MF2_]], implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v0 bb.0: successors: %bb.1(0x80000000) @@ -565,16 +565,16 @@ body: | ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY2]], [[SRLI]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] - ; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = ADDI [[COPY2]], 1 ; CHECK-NEXT: BLTU [[COPY2]], [[COPY1]], %bb.1 ; CHECK-NEXT: PseudoBR %bb.2 @@ -632,16 +632,16 @@ body: | ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY2]], [[SRLI]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] - ; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = ADDI [[COPY2]], 1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: @@ -725,25 +725,25 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1 ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -2048 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1.vector.body: ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 undef $noreg, [[COPY1]], 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4) - ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE32_V_M1_]], [[PseudoVMV_V_I_M1_]], 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 undef $noreg, [[COPY1]], 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4) + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE32_V_M1_]], [[PseudoVMV_V_I_M1_]], 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = nsw ADDI [[ADDIW]], -4 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = ADDI [[COPY1]], 16 ; CHECK-NEXT: BNE [[ADDIW]], $x0, %bb.1 ; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.middle.block: - ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X undef $noreg, $x0, 1, 5 /* e32 */, implicit $vl, implicit $vtype - ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVMV_V_I_M1_]], [[PseudoVMV_S_X]], 4, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X undef $noreg, $x0, 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVMV_V_I_M1_]], [[PseudoVMV_S_X]], 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: PseudoVSE32_V_M1 [[PseudoVREDSUM_VS_M1_E8_]], [[COPY]], 1, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res) + ; CHECK-NEXT: PseudoVSE32_V_M1 [[PseudoVREDSUM_VS_M1_E8_]], [[COPY]], 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res) ; CHECK-NEXT: PseudoRET bb.0.entry: liveins: $x10, $x12 @@ -796,28 +796,28 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrnov0 = COPY $v3 ; CHECK-NEXT: %t5:vrnov0 = COPY $v1 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1 /* vl=VLMAX */, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: BEQ %a, $x0, %bb.3 ; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $v0 = COPY %mask + ; CHECK-NEXT: $v0 = COPY %mask, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: early-clobber [[COPY]]:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, %inaddr, %idxs, $v0, -1, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber [[COPY]]:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, %inaddr, %idxs, $v0, -1 /* vl=VLMAX */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v0 = COPY %mask - ; CHECK-NEXT: PseudoVSOXEI64_V_M1_MF8_MASK [[COPY]], %b, %idxs, $v0, -1, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = COPY %mask, implicit $vtype + ; CHECK-NEXT: PseudoVSOXEI64_V_M1_MF8_MASK [[COPY]], %b, %idxs, $v0, -1 /* vl=VLMAX */, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET bb.0: successors: %bb.1 @@ -875,7 +875,7 @@ body: | ; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB ; CHECK-NEXT: %inc:gpr = SRLI %vlenb, 3 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: {{ $}} @@ -884,9 +884,9 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[COPY3]] ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[ADD]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1, 6 /* e64 */, implicit $vl, implicit $vtype - ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[ADD]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSLTU_VX_M1_]], -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3 ; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: {{ $}} @@ -894,11 +894,11 @@ body: | ; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %src, [[COPY3]] - ; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 undef $noreg, [[ADD1]], -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 undef $noreg, [[ADD1]], -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 undef $noreg, [[PseudoVLE8_V_MF8_]], 4, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 undef $noreg, [[PseudoVLE8_V_MF8_]], 4, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %dst, [[COPY3]] - ; CHECK-NEXT: PseudoVSE8_V_MF8 [[PseudoVADD_VI_MF8_]], [[ADD2]], -1, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE8_V_MF8 [[PseudoVADD_VI_MF8_]], [[ADD2]], -1 /* vl=VLMAX */, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.3: ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000) @@ -1001,9 +1001,9 @@ body: | ; CHECK-NEXT: liveins: $v8m2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, renamable $v8m2, renamable $v8m2, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, renamable $v8m2, renamable $v8m2, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, renamable $v8m2, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, renamable $v8m2, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8m2 bb.0: liveins: $x10, $v8m2 @@ -1053,9 +1053,9 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, %v, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, %v, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8m2 bb.0: liveins: $x10, $x11, $v8m2 @@ -1095,9 +1095,9 @@ body: | ; CHECK-NEXT: bb.1: ; CHECK-NEXT: dead %avl:gprnox0 = ADDI %avl, -1 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v8 = PseudoVMV_S_X undef renamable $v8, $x0, 1, 3 /* e8 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8 = PseudoVMV_S_X undef renamable $v8, $x0, 1 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v8 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, $noreg, 3 /* e8 */, 3 /* ta, ma */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v8 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, $noreg /* vl */, 3 /* e8 */, 3 /* ta, ma */, implicit $vl, implicit $vtype bb.0: liveins: $x10 %avl:gprnox0 = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir index ba79acce3cc1f..d71be1c9bda88 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir @@ -18,12 +18,12 @@ body: | ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, [[COPY3]], 8, 5 /* e32 */, implicit $vl, implicit $vtype - ; CHECK-NEXT: renamable $v11 = PseudoVMV_S_X undef renamable $v11, [[COPY2]], 8, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, [[COPY3]], 8 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v11 = PseudoVMV_S_X undef renamable $v11, [[COPY2]], 8 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, [[COPY1]], 1, 6 /* e64 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 8) + ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, [[COPY1]], 1 /* vl */, 6 /* e64 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 8) ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, [[COPY]], 8, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4) + ; CHECK-NEXT: renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, [[COPY]], 8 /* vl */, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4) ; CHECK-NEXT: PseudoRET implicit $v8, implicit $v9, implicit $v10, implicit $v11 %3:gpr = COPY $x12 %2:gpr = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll index 5b56bfc535b75..66d057c972c92 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll @@ -821,10 +821,9 @@ define void @coalesce_vl_clobber(ptr %p) { ; CHECK-NEXT: vsetvli a3, a2, e8, mf8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: slli a1, a1, 32 -; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, mu -; CHECK-NEXT: vmv.v.i v10, 0 +; CHECK-NEXT: vmv1r.v v10, v9 ; CHECK-NEXT: srli a1, a1, 32 -; CHECK-NEXT: vmerge.vim v10, v10, 1, v0 +; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, mu ; CHECK-NEXT: vslideup.vx v10, v9, a1, v0.t ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir index 6e6b708dad694..a0bf52237417e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir @@ -136,7 +136,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8 %2:gprnox0 = COPY $x10 @@ -175,8 +175,8 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8 %2:gprnox0 = COPY $x11 @@ -213,8 +213,8 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY1]], $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY1]], $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY %3, implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8 %1:gprnox0 = COPY $x11 @@ -281,10 +281,10 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) - ; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.y) - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVLE64_V_M1_1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: PseudoVSE64_V_M1 [[PseudoVADD_VV_M1_]], [[COPY1]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x) + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY1]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) + ; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.y) + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVLE64_V_M1_1]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE64_V_M1 [[PseudoVADD_VV_M1_]], [[COPY1]], 2 /* vl */, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x) ; CHECK-NEXT: PseudoRET %1:gpr = COPY $x11 %0:gpr = COPY $x10 @@ -320,11 +320,11 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVMV_V_I_M1_]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVMV_V_I_M1_]], 2 /* vl */, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] ; CHECK-NEXT: PseudoRET implicit $x10 @@ -365,7 +365,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8 %2:gprnox0 = COPY $x10 @@ -405,10 +405,10 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8 %2:gprnox0 = COPY $x11 @@ -432,9 +432,9 @@ body: | ; CHECK: liveins: $x10, $v8, $x11 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: dead [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 undef $noreg, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 undef $noreg, 4 /* vl */, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET %0:vrm2 = PseudoVID_V_M2 undef $noreg, 4, 6, 3 %4:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4, 3, 0 @@ -453,14 +453,14 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %cond:gpr = COPY $x10 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: BEQ %cond, $x0, %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl - ; CHECK-NEXT: dead [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) @@ -475,7 +475,7 @@ body: | ; CHECK-NEXT: bb.4: ; CHECK-NEXT: $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S undef $noreg, 5 /* e32 */, implicit $vtype - ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET bb.0: liveins: $x10 @@ -506,7 +506,7 @@ body: | ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $vtype ; CHECK-NEXT: $vl = COPY $x1 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: dead [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: dead [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype %1:gpr = COPY $vtype @@ -523,7 +523,7 @@ body: | ; CHECK-LABEL: name: coalesce_dead_avl_addi ; CHECK: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype - ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET %avl:gprnox0 = ADDI $x0, 42 dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype @@ -545,7 +545,7 @@ body: | ; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (dereferenceable load (s32)) ; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype - ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET %ptr:gpr = COPY $x1 %avl:gprnox0 = LW killed %ptr, 0 :: (dereferenceable load (s32)) @@ -568,7 +568,7 @@ body: | ; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (volatile dereferenceable load (s32)) ; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype - ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3 /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET %ptr:gpr = COPY $x1 %avl:gprnox0 = LW killed %ptr, 0 :: (volatile dereferenceable load (s32)) @@ -590,7 +590,7 @@ body: | ; CHECK-NEXT: %avl2:gprnox0 = ADDI $x0, 2 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI %avl2, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: %x:gpr = COPY $x10 - ; CHECK-NEXT: renamable $v8 = PseudoVMV_S_X undef renamable $v8, %x, 1, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVMV_S_X undef renamable $v8, %x, 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoRET implicit $v8 %avl1:gprnox0 = ADDI $x0, 1 dead $x0 = PseudoVSETVLI %avl1:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype @@ -656,7 +656,7 @@ body: | ; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $noreg, $x0 = PseudoVLE16FF_V_M1 $noreg, $noreg, 0, 4 /* e16 */, 2 /* tu, ma */, implicit $vl, implicit $vtype, implicit-def $vl + ; CHECK-NEXT: $noreg, $x0 = PseudoVLE16FF_V_M1 $noreg, $noreg, 0 /* vl */, 4 /* e16 */, 2 /* tu, ma */, implicit $vl, implicit $vtype, implicit-def $vl ; CHECK-NEXT: %vl:gpr = PseudoReadVL implicit $vl ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll index b335974a7b9f8..8b4260695c456 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll @@ -10,7 +10,7 @@ define @vsll_vx_nxv8i7( %a, i7 signext %b, poison, i7 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsll.ll b/llvm/test/CodeGen/RISCV/rvv/vsll.ll index 7d899dcd0ba4a..230779e24daaa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsll.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsll.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul.ll index 0606823162521..38f96431a81f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul.ll @@ -238,9 +238,9 @@ entry: define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -449,9 +449,9 @@ entry: define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -625,9 +625,9 @@ entry: define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -766,9 +766,9 @@ entry: define @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) -; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll index 58d6759b34947..351998ce7c74a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll @@ -8,11 +8,11 @@ define @vsra_vx_nxv8i7( %a, i7 signext %b, poison, i7 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra.ll b/llvm/test/CodeGen/RISCV/rvv/vsra.ll index 601956c8de444..209925453485a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsra.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll index b57f0bee21f5a..5de7d2016d285 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll @@ -10,8 +10,8 @@ define @vsrl_vx_nxv8i7( %a, i7 signext %b, poison, i7 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl.ll index bd4a1d1280a33..aaacfeb817ab0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsrl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub.ll b/llvm/test/CodeGen/RISCV/rvv/vssub.ll index c0ae21f6e4025..a9af007aa7dad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu.ll index 699a2fd4f528a..7db8d50cf190e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssubu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub.ll b/llvm/test/CodeGen/RISCV/rvv/vsub.ll index d5b445a4aa233..1cd598de3e3a9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll index 05a3e5eac4e44..56f9c31b48f65 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w.ll @@ -192,8 +192,8 @@ entry: define @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -358,8 +358,8 @@ entry: define @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -491,8 +491,8 @@ entry: define @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll index e19a212b37ac7..d15ff21973321 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vwaddu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll index 381f57e59aa76..de657410fda87 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll @@ -243,6 +243,27 @@ define @vwsll_vi_nxv2i64( %a) { ret %z } +define @vwsll_vi_anyext_nxv2i64( %a) { +; CHECK-LABEL: vwsll_vi_anyext_nxv2i64: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: vsll.vx v8, v10, a0 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vi_anyext_nxv2i64: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vmv1r.v v10, v8 +; CHECK-ZVBB-NEXT: li a0, 32 +; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0 +; CHECK-ZVBB-NEXT: ret + %x = zext %a to + %z = shl %x, splat (i64 32) + ret %z +} + ; ============================================================================== ; i16 -> i32 ; ============================================================================== @@ -454,6 +475,25 @@ define @vwsll_vi_nxv4i32( %a) { ret %z } +define @vwsll_vi_anyext_nxv4i32( %a) { +; CHECK-LABEL: vwsll_vi_anyext_nxv4i32: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vsll.vi v8, v10, 16 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vi_anyext_nxv4i32: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma +; CHECK-ZVBB-NEXT: vmv1r.v v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 16 +; CHECK-ZVBB-NEXT: ret + %x = zext %a to + %z = shl %x, splat (i32 16) + ret %z +} + ; ============================================================================== ; i8 -> i16 ; ============================================================================== @@ -637,6 +677,25 @@ define @vwsll_vi_nxv8i16( %a) { ret %z } +define @vwsll_vi_anyext_nxv8i16( %a) { +; CHECK-LABEL: vwsll_vi_anyext_nxv8i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; CHECK-NEXT: vzext.vf2 v10, v8 +; CHECK-NEXT: vsll.vi v8, v10, 8 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vi_anyext_nxv8i16: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-ZVBB-NEXT: vmv1r.v v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 8 +; CHECK-ZVBB-NEXT: ret + %x = zext %a to + %z = shl %x, splat (i16 8) + ret %z +} + ; ============================================================================== ; i8 -> i64 ; ============================================================================== @@ -883,6 +942,25 @@ define @vwsll_vi_nxv2i64_nxv2i8( %a) { %z = shl %x, splat (i64 2) ret %z } + +define @vwsll_vi_anyext_nxv2i64_nxv2i8( %a) { +; CHECK-LABEL: vwsll_vi_anyext_nxv2i64_nxv2i8: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-NEXT: vzext.vf8 v10, v8 +; CHECK-NEXT: vsll.vi v8, v10, 8 +; CHECK-NEXT: ret +; +; CHECK-ZVBB-LABEL: vwsll_vi_anyext_nxv2i64_nxv2i8: +; CHECK-ZVBB: # %bb.0: +; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 8 +; CHECK-ZVBB-NEXT: ret + %x = zext %a to + %z = shl %x, splat (i64 8) + ret %z +} ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; RV32ZVBB: {{.*}} ; RV64ZVBB: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll index 9fdbe2edf017e..0e7601ee99768 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll index 50977a4e35b8e..f90193f1c4631 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w.ll @@ -188,8 +188,8 @@ entry: define @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -354,8 +354,8 @@ entry: define @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -487,8 +487,8 @@ entry: define @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl4re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor.ll b/llvm/test/CodeGen/RISCV/rvv/vxor.ll index da78f57df69ea..ec3341df3bede 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor.ll @@ -221,8 +221,8 @@ entry: define @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8r.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu +; CHECK-NEXT: vle8.v v24, (a0) ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -420,8 +420,8 @@ entry: define @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re16.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu +; CHECK-NEXT: vle16.v v24, (a0) ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -586,8 +586,8 @@ entry: define @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re32.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu +; CHECK-NEXT: vle32.v v24, (a0) ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ entry: define @intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu +; CHECK-NEXT: vle64.v v24, (a0) ; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir index 87787c1f25f09..7457971809fd2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir @@ -13,7 +13,7 @@ body: | ; MIR-NEXT: {{ $}} ; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm ; MIR-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype - ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 undef renamable $v8, killed renamable $v8, killed renamable $v9, 0, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vxrm, implicit $vl, implicit $vtype + ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 undef renamable $v8, killed renamable $v8, killed renamable $v9, 0 /* vxrm=rnu */, $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vxrm, implicit $vl, implicit $vtype ; MIR-NEXT: PseudoRET implicit $v8 ; ASM-LABEL: verify_vxrm: ; ASM: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir index 6e5b49d543216..d357ec644220f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir +++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir @@ -126,9 +126,9 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -80 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 80 - ; CHECK-NEXT: SD killed $x1, $x2, 56 :: (store (s64) into %stack.2) - ; CHECK-NEXT: SD killed $x8, $x2, 48 :: (store (s64) into %stack.3) - ; CHECK-NEXT: SD killed $x9, $x2, 40 :: (store (s64) into %stack.4) + ; CHECK-NEXT: frame-setup SD killed $x1, $x2, 56 :: (store (s64) into %stack.2) + ; CHECK-NEXT: frame-setup SD killed $x8, $x2, 48 :: (store (s64) into %stack.3) + ; CHECK-NEXT: frame-setup SD killed $x9, $x2, 40 :: (store (s64) into %stack.4) ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -24 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -32 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -40 @@ -144,7 +144,7 @@ body: | ; CHECK-NEXT: $x10 = ADD $x2, killed $x10 ; CHECK-NEXT: SD killed renamable $x16, killed $x10, 64 :: (store (s64) into %fixed-stack.1, align 16) ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 undef $v8, 0, 2, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 undef $v8, 0, 2 /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x10 = ADDI $x2, 32 ; CHECK-NEXT: VS1R_V killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8) ; CHECK-NEXT: {{ $}} @@ -162,7 +162,7 @@ body: | ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x10 = ADDI $x2, 32 ; CHECK-NEXT: renamable $v8 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8) - ; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3 /* e8 */, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) + ; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1) ; CHECK-NEXT: $x10 = COPY renamable $x9 ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) @fprintf, csr_ilp32d_lp64d, implicit-def dead $x1, implicit killed $x10, implicit-def $x2, implicit-def dead $x10 ; CHECK-NEXT: PseudoBR %bb.1 diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir index 9c2fa9d0009a7..8b4adac06716e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir +++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir @@ -28,7 +28,7 @@ body: | ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 undef $v0_v1_v2_v3_v4_v5_v6, renamable $x10, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 undef $v0_v1_v2_v3_v4_v5_v6, renamable $x10, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x11 = ADDI $x2, 16 ; CHECK-NEXT: VS4R_V $v0m4, $x11, implicit $v0_v1_v2_v3_v4_v5_v6 :: (store () into %stack.0, align 8) ; CHECK-NEXT: $x12 = PseudoReadVLENB @@ -81,7 +81,7 @@ body: | ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: $v1_v2_v3_v4_v5_v6_v7 = PseudoVLSEG7E64_V_M1 undef $v1_v2_v3_v4_v5_v6_v7, renamable $x10, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v1_v2_v3_v4_v5_v6_v7 = PseudoVLSEG7E64_V_M1 undef $v1_v2_v3_v4_v5_v6_v7, renamable $x10, $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x11 = ADDI $x2, 16 ; CHECK-NEXT: VS1R_V $v1, $x11, implicit $v1_v2_v3_v4_v5_v6_v7 :: (store () into %stack.0) ; CHECK-NEXT: $x12 = PseudoReadVLENB diff --git a/llvm/test/CodeGen/RISCV/spacemitx60-sched-copy.mir b/llvm/test/CodeGen/RISCV/spacemitx60-sched-copy.mir index 3c9bc0a0194f8..9aa4a87985fc5 100644 --- a/llvm/test/CodeGen/RISCV/spacemitx60-sched-copy.mir +++ b/llvm/test/CodeGen/RISCV/spacemitx60-sched-copy.mir @@ -21,18 +21,18 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 64 ; CHECK-NEXT: $v0 = COPY [[COPY2]] - ; CHECK-NEXT: [[PseudoVCPOP_M_B2_:%[0-9]+]]:gprnox0 = PseudoVCPOP_M_B2 [[COPY2]], [[ADDI]], 0 /* e8 */ - ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVIOTA_M_M8 undef %5, [[COPY2]], [[ADDI]], 4 /* e16 */, 0 /* tu, mu */ - ; CHECK-NEXT: [[PseudoVLE16_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE16_V_M8 undef [[PseudoVLE16_V_M8_]], [[COPY3]], [[PseudoVCPOP_M_B2_]], 4 /* e16 */, 2 /* tu, ma */ - ; CHECK-NEXT: early-clobber [[COPY1]]:vrm8nov0 = PseudoVRGATHER_VV_M8_E16_MASK [[COPY1]], [[PseudoVLE16_V_M8_]], %5, $v0, [[ADDI]], 4 /* e16 */, 1 /* ta, mu */ - ; CHECK-NEXT: [[PseudoVSLIDEDOWN_VI_M1_:%[0-9]+]]:vr = PseudoVSLIDEDOWN_VI_M1 undef [[PseudoVSLIDEDOWN_VI_M1_]], [[COPY2]], 8, 8, 3 /* e8 */, 3 /* ta, ma */ - ; CHECK-NEXT: [[PseudoVCPOP_M_B2_1:%[0-9]+]]:gprnox0 = PseudoVCPOP_M_B2 [[PseudoVSLIDEDOWN_VI_M1_]], [[ADDI]], 0 /* e8 */ + ; CHECK-NEXT: [[PseudoVCPOP_M_B2_:%[0-9]+]]:gprnox0 = PseudoVCPOP_M_B2 [[COPY2]], [[ADDI]] /* vl */, 0 /* e8 */ + ; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVIOTA_M_M8 undef %5, [[COPY2]], [[ADDI]] /* vl */, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE16_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE16_V_M8 undef [[PseudoVLE16_V_M8_]], [[COPY3]], [[PseudoVCPOP_M_B2_]] /* vl */, 4 /* e16 */, 2 /* tu, ma */ + ; CHECK-NEXT: early-clobber [[COPY1]]:vrm8nov0 = PseudoVRGATHER_VV_M8_E16_MASK [[COPY1]], [[PseudoVLE16_V_M8_]], %5, $v0, [[ADDI]] /* vl */, 4 /* e16 */, 1 /* ta, mu */ + ; CHECK-NEXT: [[PseudoVSLIDEDOWN_VI_M1_:%[0-9]+]]:vr = PseudoVSLIDEDOWN_VI_M1 undef [[PseudoVSLIDEDOWN_VI_M1_]], [[COPY2]], 8, 8 /* vl */, 3 /* e8 */, 3 /* ta, ma */ + ; CHECK-NEXT: [[PseudoVCPOP_M_B2_1:%[0-9]+]]:gprnox0 = PseudoVCPOP_M_B2 [[PseudoVSLIDEDOWN_VI_M1_]], [[ADDI]] /* vl */, 0 /* e8 */ ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoVCPOP_M_B2_]], 1 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY3]], [[SLLI]] - ; CHECK-NEXT: [[PseudoVLE16_V_M8_1:%[0-9]+]]:vrm8 = PseudoVLE16_V_M8 undef [[PseudoVLE16_V_M8_1]], [[ADD]], [[PseudoVCPOP_M_B2_1]], 4 /* e16 */, 2 /* tu, ma */ - ; CHECK-NEXT: early-clobber %13:vrm8 = PseudoVIOTA_M_M8 undef %13, [[PseudoVSLIDEDOWN_VI_M1_]], [[ADDI]], 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: [[PseudoVLE16_V_M8_1:%[0-9]+]]:vrm8 = PseudoVLE16_V_M8 undef [[PseudoVLE16_V_M8_1]], [[ADD]], [[PseudoVCPOP_M_B2_1]] /* vl */, 4 /* e16 */, 2 /* tu, ma */ + ; CHECK-NEXT: early-clobber %13:vrm8 = PseudoVIOTA_M_M8 undef %13, [[PseudoVSLIDEDOWN_VI_M1_]], [[ADDI]] /* vl */, 4 /* e16 */, 0 /* tu, mu */ ; CHECK-NEXT: $v0 = COPY [[PseudoVSLIDEDOWN_VI_M1_]] - ; CHECK-NEXT: early-clobber [[COPY]]:vrm8nov0 = PseudoVRGATHER_VV_M8_E16_MASK [[COPY]], [[PseudoVLE16_V_M8_1]], %13, $v0, [[ADDI]], 4 /* e16 */, 1 /* ta, mu */ + ; CHECK-NEXT: early-clobber [[COPY]]:vrm8nov0 = PseudoVRGATHER_VV_M8_E16_MASK [[COPY]], [[PseudoVLE16_V_M8_1]], %13, $v0, [[ADDI]] /* vl */, 4 /* e16 */, 1 /* ta, mu */ ; CHECK-NEXT: $v8m8 = COPY [[COPY1]] ; CHECK-NEXT: $v16m8 = COPY [[COPY]] ; CHECK-NEXT: PseudoRET implicit $v8m8, implicit $v16m8 diff --git a/llvm/test/CodeGen/RISCV/tls-models.ll b/llvm/test/CodeGen/RISCV/tls-models.ll index b99896e350191..52c2c31d8fa81 100644 --- a/llvm/test/CodeGen/RISCV/tls-models.ll +++ b/llvm/test/CodeGen/RISCV/tls-models.ll @@ -37,6 +37,16 @@ define ptr @f1() nounwind { ; RV32-PIC-NEXT: addi sp, sp, 16 ; RV32-PIC-NEXT: ret ; +; RV32-PIC-TLSDESC-LABEL: f1: +; RV32-PIC-TLSDESC: # %bb.0: # %entry +; RV32-PIC-TLSDESC-NEXT: .Ltlsdesc_hi0: +; RV32-PIC-TLSDESC-NEXT: auipc a0, %tlsdesc_hi(unspecified) +; RV32-PIC-TLSDESC-NEXT: lw a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0) +; RV32-PIC-TLSDESC-NEXT: addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0) +; RV32-PIC-TLSDESC-NEXT: jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0) +; RV32-PIC-TLSDESC-NEXT: add a0, a0, tp +; RV32-PIC-TLSDESC-NEXT: ret +; ; RV64-PIC-LABEL: f1: ; RV64-PIC: # %bb.0: # %entry ; RV64-PIC-NEXT: addi sp, sp, -16 @@ -49,32 +59,6 @@ define ptr @f1() nounwind { ; RV64-PIC-NEXT: addi sp, sp, 16 ; RV64-PIC-NEXT: ret ; -; RV32-NOPIC-LABEL: f1: -; RV32-NOPIC: # %bb.0: # %entry -; RV32-NOPIC-NEXT: .Lpcrel_hi0: -; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified) -; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0) -; RV32-NOPIC-NEXT: add a0, a0, tp -; RV32-NOPIC-NEXT: ret -; -; RV64-NOPIC-LABEL: f1: -; RV64-NOPIC: # %bb.0: # %entry -; RV64-NOPIC-NEXT: .Lpcrel_hi0: -; RV64-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified) -; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0) -; RV64-NOPIC-NEXT: add a0, a0, tp -; RV64-NOPIC-NEXT: ret -; -; RV32-PIC-TLSDESC-LABEL: f1: -; RV32-PIC-TLSDESC: # %bb.0: # %entry -; RV32-PIC-TLSDESC-NEXT: .Ltlsdesc_hi0: -; RV32-PIC-TLSDESC-NEXT: auipc a0, %tlsdesc_hi(unspecified) -; RV32-PIC-TLSDESC-NEXT: lw a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0) -; RV32-PIC-TLSDESC-NEXT: addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi0) -; RV32-PIC-TLSDESC-NEXT: jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi0) -; RV32-PIC-TLSDESC-NEXT: add a0, a0, tp -; RV32-PIC-TLSDESC-NEXT: ret -; ; RV64-PIC-TLSDESC-LABEL: f1: ; RV64-PIC-TLSDESC: # %bb.0: # %entry ; RV64-PIC-TLSDESC-NEXT: .Ltlsdesc_hi0: @@ -85,6 +69,14 @@ define ptr @f1() nounwind { ; RV64-PIC-TLSDESC-NEXT: add a0, a0, tp ; RV64-PIC-TLSDESC-NEXT: ret ; +; RV32-NOPIC-LABEL: f1: +; RV32-NOPIC: # %bb.0: # %entry +; RV32-NOPIC-NEXT: .Lpcrel_hi0: +; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified) +; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0) +; RV32-NOPIC-NEXT: add a0, a0, tp +; RV32-NOPIC-NEXT: ret +; ; RV32-NOPIC-TLSDESC-LABEL: f1: ; RV32-NOPIC-TLSDESC: # %bb.0: # %entry ; RV32-NOPIC-TLSDESC-NEXT: .Lpcrel_hi0: @@ -93,6 +85,14 @@ define ptr @f1() nounwind { ; RV32-NOPIC-TLSDESC-NEXT: add a0, a0, tp ; RV32-NOPIC-TLSDESC-NEXT: ret ; +; RV64-NOPIC-LABEL: f1: +; RV64-NOPIC: # %bb.0: # %entry +; RV64-NOPIC-NEXT: .Lpcrel_hi0: +; RV64-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(unspecified) +; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0) +; RV64-NOPIC-NEXT: add a0, a0, tp +; RV64-NOPIC-NEXT: ret +; ; RV64-NOPIC-TLSDESC-LABEL: f1: ; RV64-NOPIC-TLSDESC: # %bb.0: # %entry ; RV64-NOPIC-TLSDESC-NEXT: .Lpcrel_hi0: @@ -120,6 +120,16 @@ define ptr @f2() nounwind { ; RV32-PIC-NEXT: addi sp, sp, 16 ; RV32-PIC-NEXT: ret ; +; RV32-PIC-TLSDESC-LABEL: f2: +; RV32-PIC-TLSDESC: # %bb.0: # %entry +; RV32-PIC-TLSDESC-NEXT: .Ltlsdesc_hi1: +; RV32-PIC-TLSDESC-NEXT: auipc a0, %tlsdesc_hi(ld) +; RV32-PIC-TLSDESC-NEXT: lw a1, %tlsdesc_load_lo(.Ltlsdesc_hi1)(a0) +; RV32-PIC-TLSDESC-NEXT: addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi1) +; RV32-PIC-TLSDESC-NEXT: jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi1) +; RV32-PIC-TLSDESC-NEXT: add a0, a0, tp +; RV32-PIC-TLSDESC-NEXT: ret +; ; RV64-PIC-LABEL: f2: ; RV64-PIC: # %bb.0: # %entry ; RV64-PIC-NEXT: addi sp, sp, -16 @@ -132,6 +142,16 @@ define ptr @f2() nounwind { ; RV64-PIC-NEXT: addi sp, sp, 16 ; RV64-PIC-NEXT: ret ; +; RV64-PIC-TLSDESC-LABEL: f2: +; RV64-PIC-TLSDESC: # %bb.0: # %entry +; RV64-PIC-TLSDESC-NEXT: .Ltlsdesc_hi1: +; RV64-PIC-TLSDESC-NEXT: auipc a0, %tlsdesc_hi(ld) +; RV64-PIC-TLSDESC-NEXT: ld a1, %tlsdesc_load_lo(.Ltlsdesc_hi1)(a0) +; RV64-PIC-TLSDESC-NEXT: addi a0, a0, %tlsdesc_add_lo(.Ltlsdesc_hi1) +; RV64-PIC-TLSDESC-NEXT: jalr t0, 0(a1), %tlsdesc_call(.Ltlsdesc_hi1) +; RV64-PIC-TLSDESC-NEXT: add a0, a0, tp +; RV64-PIC-TLSDESC-NEXT: ret +; ; RV32-NOPIC-LABEL: f2: ; RV32-NOPIC: # %bb.0: # %entry ; RV32-NOPIC-NEXT: .Lpcrel_hi1: @@ -140,6 +160,14 @@ define ptr @f2() nounwind { ; RV32-NOPIC-NEXT: add a0, a0, tp ; RV32-NOPIC-NEXT: ret ; +; RV32-NOPIC-TLSDESC-LABEL: f2: +; RV32-NOPIC-TLSDESC: # %bb.0: # %entry +; RV32-NOPIC-TLSDESC-NEXT: .Lpcrel_hi1: +; RV32-NOPIC-TLSDESC-NEXT: auipc a0, %tls_ie_pcrel_hi(ld) +; RV32-NOPIC-TLSDESC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi1)(a0) +; RV32-NOPIC-TLSDESC-NEXT: add a0, a0, tp +; RV32-NOPIC-TLSDESC-NEXT: ret +; ; RV64-NOPIC-LABEL: f2: ; RV64-NOPIC: # %bb.0: # %entry ; RV64-NOPIC-NEXT: .Lpcrel_hi1: @@ -147,6 +175,14 @@ define ptr @f2() nounwind { ; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0) ; RV64-NOPIC-NEXT: add a0, a0, tp ; RV64-NOPIC-NEXT: ret +; +; RV64-NOPIC-TLSDESC-LABEL: f2: +; RV64-NOPIC-TLSDESC: # %bb.0: # %entry +; RV64-NOPIC-TLSDESC-NEXT: .Lpcrel_hi1: +; RV64-NOPIC-TLSDESC-NEXT: auipc a0, %tls_ie_pcrel_hi(ld) +; RV64-NOPIC-TLSDESC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0) +; RV64-NOPIC-TLSDESC-NEXT: add a0, a0, tp +; RV64-NOPIC-TLSDESC-NEXT: ret entry: ret ptr @ld } @@ -163,30 +199,6 @@ define ptr @f3() nounwind { ; RV32-PIC-NEXT: add a0, a0, tp ; RV32-PIC-NEXT: ret ; -; RV64-PIC-LABEL: f3: -; RV64-PIC: # %bb.0: # %entry -; RV64-PIC-NEXT: .Lpcrel_hi2: -; RV64-PIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie) -; RV64-PIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0) -; RV64-PIC-NEXT: add a0, a0, tp -; RV64-PIC-NEXT: ret -; -; RV32-NOPIC-LABEL: f3: -; RV32-NOPIC: # %bb.0: # %entry -; RV32-NOPIC-NEXT: .Lpcrel_hi2: -; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie) -; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi2)(a0) -; RV32-NOPIC-NEXT: add a0, a0, tp -; RV32-NOPIC-NEXT: ret -; -; RV64-NOPIC-LABEL: f3: -; RV64-NOPIC: # %bb.0: # %entry -; RV64-NOPIC-NEXT: .Lpcrel_hi2: -; RV64-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie) -; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0) -; RV64-NOPIC-NEXT: add a0, a0, tp -; RV64-NOPIC-NEXT: ret -; ; RV32-PIC-TLSDESC-LABEL: f3: ; RV32-PIC-TLSDESC: # %bb.0: # %entry ; RV32-PIC-TLSDESC-NEXT: .Lpcrel_hi0: @@ -195,6 +207,14 @@ define ptr @f3() nounwind { ; RV32-PIC-TLSDESC-NEXT: add a0, a0, tp ; RV32-PIC-TLSDESC-NEXT: ret ; +; RV64-PIC-LABEL: f3: +; RV64-PIC: # %bb.0: # %entry +; RV64-PIC-NEXT: .Lpcrel_hi2: +; RV64-PIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie) +; RV64-PIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0) +; RV64-PIC-NEXT: add a0, a0, tp +; RV64-PIC-NEXT: ret +; ; RV64-PIC-TLSDESC-LABEL: f3: ; RV64-PIC-TLSDESC: # %bb.0: # %entry ; RV64-PIC-TLSDESC-NEXT: .Lpcrel_hi0: @@ -203,6 +223,14 @@ define ptr @f3() nounwind { ; RV64-PIC-TLSDESC-NEXT: add a0, a0, tp ; RV64-PIC-TLSDESC-NEXT: ret ; +; RV32-NOPIC-LABEL: f3: +; RV32-NOPIC: # %bb.0: # %entry +; RV32-NOPIC-NEXT: .Lpcrel_hi2: +; RV32-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie) +; RV32-NOPIC-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi2)(a0) +; RV32-NOPIC-NEXT: add a0, a0, tp +; RV32-NOPIC-NEXT: ret +; ; RV32-NOPIC-TLSDESC-LABEL: f3: ; RV32-NOPIC-TLSDESC: # %bb.0: # %entry ; RV32-NOPIC-TLSDESC-NEXT: .Lpcrel_hi2: @@ -211,6 +239,14 @@ define ptr @f3() nounwind { ; RV32-NOPIC-TLSDESC-NEXT: add a0, a0, tp ; RV32-NOPIC-TLSDESC-NEXT: ret ; +; RV64-NOPIC-LABEL: f3: +; RV64-NOPIC: # %bb.0: # %entry +; RV64-NOPIC-NEXT: .Lpcrel_hi2: +; RV64-NOPIC-NEXT: auipc a0, %tls_ie_pcrel_hi(ie) +; RV64-NOPIC-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi2)(a0) +; RV64-NOPIC-NEXT: add a0, a0, tp +; RV64-NOPIC-NEXT: ret +; ; RV64-NOPIC-TLSDESC-LABEL: f3: ; RV64-NOPIC-TLSDESC: # %bb.0: # %entry ; RV64-NOPIC-TLSDESC-NEXT: .Lpcrel_hi2: @@ -233,27 +269,6 @@ define ptr @f4() nounwind { ; RV32-PIC-NEXT: addi a0, a0, %tprel_lo(le) ; RV32-PIC-NEXT: ret ; -; RV64-PIC-LABEL: f4: -; RV64-PIC: # %bb.0: # %entry -; RV64-PIC-NEXT: lui a0, %tprel_hi(le) -; RV64-PIC-NEXT: add a0, a0, tp, %tprel_add(le) -; RV64-PIC-NEXT: addi a0, a0, %tprel_lo(le) -; RV64-PIC-NEXT: ret -; -; RV32-NOPIC-LABEL: f4: -; RV32-NOPIC: # %bb.0: # %entry -; RV32-NOPIC-NEXT: lui a0, %tprel_hi(le) -; RV32-NOPIC-NEXT: add a0, a0, tp, %tprel_add(le) -; RV32-NOPIC-NEXT: addi a0, a0, %tprel_lo(le) -; RV32-NOPIC-NEXT: ret -; -; RV64-NOPIC-LABEL: f4: -; RV64-NOPIC: # %bb.0: # %entry -; RV64-NOPIC-NEXT: lui a0, %tprel_hi(le) -; RV64-NOPIC-NEXT: add a0, a0, tp, %tprel_add(le) -; RV64-NOPIC-NEXT: addi a0, a0, %tprel_lo(le) -; RV64-NOPIC-NEXT: ret -; ; RV32-PIC-TLSDESC-LABEL: f4: ; RV32-PIC-TLSDESC: # %bb.0: # %entry ; RV32-PIC-TLSDESC-NEXT: lui a0, %tprel_hi(le) @@ -261,6 +276,13 @@ define ptr @f4() nounwind { ; RV32-PIC-TLSDESC-NEXT: addi a0, a0, %tprel_lo(le) ; RV32-PIC-TLSDESC-NEXT: ret ; +; RV64-PIC-LABEL: f4: +; RV64-PIC: # %bb.0: # %entry +; RV64-PIC-NEXT: lui a0, %tprel_hi(le) +; RV64-PIC-NEXT: add a0, a0, tp, %tprel_add(le) +; RV64-PIC-NEXT: addi a0, a0, %tprel_lo(le) +; RV64-PIC-NEXT: ret +; ; RV64-PIC-TLSDESC-LABEL: f4: ; RV64-PIC-TLSDESC: # %bb.0: # %entry ; RV64-PIC-TLSDESC-NEXT: lui a0, %tprel_hi(le) @@ -268,6 +290,13 @@ define ptr @f4() nounwind { ; RV64-PIC-TLSDESC-NEXT: addi a0, a0, %tprel_lo(le) ; RV64-PIC-TLSDESC-NEXT: ret ; +; RV32-NOPIC-LABEL: f4: +; RV32-NOPIC: # %bb.0: # %entry +; RV32-NOPIC-NEXT: lui a0, %tprel_hi(le) +; RV32-NOPIC-NEXT: add a0, a0, tp, %tprel_add(le) +; RV32-NOPIC-NEXT: addi a0, a0, %tprel_lo(le) +; RV32-NOPIC-NEXT: ret +; ; RV32-NOPIC-TLSDESC-LABEL: f4: ; RV32-NOPIC-TLSDESC: # %bb.0: # %entry ; RV32-NOPIC-TLSDESC-NEXT: lui a0, %tprel_hi(le) @@ -275,6 +304,13 @@ define ptr @f4() nounwind { ; RV32-NOPIC-TLSDESC-NEXT: addi a0, a0, %tprel_lo(le) ; RV32-NOPIC-TLSDESC-NEXT: ret ; +; RV64-NOPIC-LABEL: f4: +; RV64-NOPIC: # %bb.0: # %entry +; RV64-NOPIC-NEXT: lui a0, %tprel_hi(le) +; RV64-NOPIC-NEXT: add a0, a0, tp, %tprel_add(le) +; RV64-NOPIC-NEXT: addi a0, a0, %tprel_lo(le) +; RV64-NOPIC-NEXT: ret +; ; RV64-NOPIC-TLSDESC-LABEL: f4: ; RV64-NOPIC-TLSDESC: # %bb.0: # %entry ; RV64-NOPIC-TLSDESC-NEXT: lui a0, %tprel_hi(le) diff --git a/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir b/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir index f4465bbaacf75..146e6e162c8ea 100644 --- a/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir +++ b/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir @@ -30,13 +30,13 @@ body: | ; CHECK-LIBCALL32-LABEL: name: popret_rvlist5 ; CHECK-LIBCALL32: liveins: $x1, $x8 ; CHECK-LIBCALL32-NEXT: {{ $}} - ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1 + ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1, implicit $x1, implicit $x8 ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 ; CHECK-LIBCALL32-NEXT: $x1 = IMPLICIT_DEF ; CHECK-LIBCALL32-NEXT: $x8 = IMPLICIT_DEF - ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2 + ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit-def $x1, implicit-def $x8 ; ; CHECK-ZCMP64-LABEL: name: popret_rvlist5 ; CHECK-ZCMP64: liveins: $x1, $x8 @@ -52,13 +52,13 @@ body: | ; CHECK-LIBCALL64-LABEL: name: popret_rvlist5 ; CHECK-LIBCALL64: liveins: $x1, $x8 ; CHECK-LIBCALL64-NEXT: {{ $}} - ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1 + ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1, implicit $x1, implicit $x8 ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 ; CHECK-LIBCALL64-NEXT: $x1 = IMPLICIT_DEF ; CHECK-LIBCALL64-NEXT: $x8 = IMPLICIT_DEF - ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2 + ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit-def $x1, implicit-def $x8 ; ; CHECK-NO-ZCMP32-LABEL: name: popret_rvlist5 ; CHECK-NO-ZCMP32: liveins: $x1, $x8 @@ -120,14 +120,14 @@ body: | ; CHECK-LIBCALL32-LABEL: name: popretz_rvlist5 ; CHECK-LIBCALL32: liveins: $x1, $x8 ; CHECK-LIBCALL32-NEXT: {{ $}} - ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1 + ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1, implicit $x1, implicit $x8 ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 ; CHECK-LIBCALL32-NEXT: $x1 = IMPLICIT_DEF ; CHECK-LIBCALL32-NEXT: $x8 = IMPLICIT_DEF ; CHECK-LIBCALL32-NEXT: $x10 = ADDI $x0, 0 - ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit $x10 + ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit-def $x1, implicit-def $x8, implicit $x10 ; ; CHECK-ZCMP64-LABEL: name: popretz_rvlist5 ; CHECK-ZCMP64: liveins: $x1, $x8 @@ -143,14 +143,14 @@ body: | ; CHECK-LIBCALL64-LABEL: name: popretz_rvlist5 ; CHECK-LIBCALL64: liveins: $x1, $x8 ; CHECK-LIBCALL64-NEXT: {{ $}} - ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1 + ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1, implicit $x1, implicit $x8 ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 ; CHECK-LIBCALL64-NEXT: $x1 = IMPLICIT_DEF ; CHECK-LIBCALL64-NEXT: $x8 = IMPLICIT_DEF ; CHECK-LIBCALL64-NEXT: $x10 = ADDI $x0, 0 - ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit $x10 + ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit-def $x1, implicit-def $x8, implicit $x10 ; ; CHECK-NO-ZCMP32-LABEL: name: popretz_rvlist5 ; CHECK-NO-ZCMP32: liveins: $x1, $x8 diff --git a/llvm/test/CodeGen/SPIRV/event-zero-const-64.ll b/llvm/test/CodeGen/SPIRV/event-zero-const-64.ll new file mode 100644 index 0000000000000..49cd2cb6bf268 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/event-zero-const-64.ll @@ -0,0 +1,27 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#LongTy:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#IntTy:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#EventTy:]] = OpTypeEvent +; CHECK-DAG: %[[#LongNull:]] = OpConstantNull %[[#LongTy]] +; CHECK-DAG: %[[#EventNull:]] = OpConstantNull %[[#EventTy]] +; CHECK-DAG: %[[#Scope:]] = OpConstant %[[#IntTy]] 2 +; CHECK-DAG: %[[#One:]] = OpConstant %[[#LongTy]] 1 +; CHECK: OpFunction +; CHECK: OpINotEqual %[[#]] %[[#]] %[[#LongNull]] +; CHECK: OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#]] %[[#]] %[[#One]] %[[#One]] %[[#EventNull]] + +@G_r1 = global i1 0 +@G_e1 = global target("spirv.Event") poison + +define weak_odr dso_local spir_kernel void @foo(i64 %_arg_i, ptr addrspace(1) %_arg_ptr, ptr addrspace(3) %_arg_local) { +entry: + %r1 = icmp ne i64 %_arg_i, 0 + store i1 %r1, ptr @G_r1 + %e1 = tail call spir_func target("spirv.Event") @__spirv_GroupAsyncCopy(i32 2, ptr addrspace(3) %_arg_local, ptr addrspace(1) %_arg_ptr, i64 1, i64 1, target("spirv.Event") zeroinitializer) + store target("spirv.Event") %e1, ptr @G_e1 + ret void +} + +declare dso_local spir_func target("spirv.Event") @__spirv_GroupAsyncCopy(i32, ptr addrspace(3), ptr addrspace(1), i64, i64, target("spirv.Event")) diff --git a/llvm/test/CodeGen/SPIRV/event-zero-const.ll b/llvm/test/CodeGen/SPIRV/event-zero-const.ll index 2bf8259e78785..df8c79519779d 100644 --- a/llvm/test/CodeGen/SPIRV/event-zero-const.ll +++ b/llvm/test/CodeGen/SPIRV/event-zero-const.ll @@ -1,16 +1,16 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} - ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#LongTy:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#IntTy:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#EventTy:]] = OpTypeEvent ; CHECK-DAG: %[[#LongNull:]] = OpConstantNull %[[#LongTy]] ; CHECK-DAG: %[[#EventNull:]] = OpConstantNull %[[#EventTy]] +; CHECK-DAG: %[[#Scope:]] = OpConstant %[[#IntTy]] 2 +; CHECK-DAG: %[[#One:]] = OpConstant %[[#IntTy]] 1 ; CHECK: OpFunction ; CHECK: OpINotEqual %[[#]] %[[#]] %[[#LongNull]] -; CHECK: OpGroupAsyncCopy %[[#EventTy]] %[[#]] %[[#]] %[[#]] %[[#]] %[[#]] %[[#EventNull]] +; CHECK: OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#]] %[[#]] %[[#One]] %[[#One]] %[[#EventNull]] @G_r1 = global i1 0 @G_e1 = global target("spirv.Event") poison @@ -19,9 +19,9 @@ define weak_odr dso_local spir_kernel void @foo(i64 %_arg_i, ptr addrspace(1) %_ entry: %r1 = icmp ne i64 %_arg_i, 0 store i1 %r1, ptr @G_r1 - %e1 = tail call spir_func target("spirv.Event") @__spirv_GroupAsyncCopy(i32 2, ptr addrspace(3) %_arg_local, ptr addrspace(1) %_arg_ptr, i64 1, i64 1, target("spirv.Event") zeroinitializer) + %e1 = tail call spir_func target("spirv.Event") @__spirv_GroupAsyncCopy(i32 2, ptr addrspace(3) %_arg_local, ptr addrspace(1) %_arg_ptr, i32 1, i32 1, target("spirv.Event") zeroinitializer) store target("spirv.Event") %e1, ptr @G_e1 ret void } -declare dso_local spir_func target("spirv.Event") @__spirv_GroupAsyncCopy(i32, ptr addrspace(3), ptr addrspace(1), i64, i64, target("spirv.Event")) +declare dso_local spir_func target("spirv.Event") @__spirv_GroupAsyncCopy(i32, ptr addrspace(3), ptr addrspace(1), i32, i32, target("spirv.Event")) diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll new file mode 100644 index 0000000000000..97facdb8e5cc0 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll @@ -0,0 +1,23 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_ALTERA_arbitrary_precision_integers %s -o - | FileCheck %s + +; Verify that wide integer constants (>64 bits) are correctly encoded as +; OpConstant with multi-word literals. + +; CHECK-DAG: %[[#INT128:]] = OpTypeInt 128 0 +; CHECK-DAG: %[[#NEG128:]] = OpConstant %[[#INT128]] 4294965247 4294967295 4294967295 4294967295 +; CHECK-DAG: %[[#ONE128:]] = OpConstant %[[#INT128]] 1 0 0 0 +; CHECK-DAG: %[[#BOUNDARY:]] = OpConstant %[[#INT128]] 4294967295 4294967295 0 0 +; CHECK-DAG: %[[#ZERO128:]] = OpConstantNull %[[#INT128]] +; CHECK: OpStore %[[#]] %[[#NEG128]] Aligned 16 +; CHECK: OpStore %[[#]] %[[#ONE128]] Aligned 16 +; CHECK: OpStore %[[#]] %[[#BOUNDARY]] Aligned 16 +; CHECK: OpStore %[[#]] %[[#ZERO128]] Aligned 16 + +define spir_func void @test_i128_const(ptr addrspace(4) %p) addrspace(4) { +entry: + store i128 -2049, ptr addrspace(4) %p, align 16 + store i128 1, ptr addrspace(4) %p, align 16 + store i128 18446744073709551615, ptr addrspace(4) %p, align 16 + store i128 0, ptr addrspace(4) %p, align 16 + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_unstructured_loop_controls/loop-unroll.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_unstructured_loop_controls/loop-unroll.ll new file mode 100644 index 0000000000000..b3aed5b4f2339 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_unstructured_loop_controls/loop-unroll.ll @@ -0,0 +1,104 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_unstructured_loop_controls %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-NO-EXT +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_unstructured_loop_controls %s -o - -filetype=obj | spirv-val %} + +; Check that extension and capability are emitted when extension is enabled. +; CHECK-SPIRV-DAG: OpCapability UnstructuredLoopControlsINTEL +; CHECK-SPIRV-DAG: OpExtension "SPV_INTEL_unstructured_loop_controls" + +; Check that OpLoopControlINTEL is NOT emitted when extension is not enabled. +; CHECK-NO-EXT-NOT: OpLoopControlINTEL + +; Test 1: llvm.loop.unroll.enable -> OpLoopControlINTEL Unroll. +; CHECK-SPIRV: test_unroll_enable +; CHECK-SPIRV: OpLoopControlINTEL Unroll +; CHECK-SPIRV-NEXT: OpBranchConditional + +define spir_kernel void @test_unroll_enable(ptr addrspace(1) %dst) { +entry: + br label %for.body + +for.body: + %i = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %ptr = getelementptr inbounds i32, ptr addrspace(1) %dst, i32 %i + store i32 %i, ptr addrspace(1) %ptr, align 4 + %inc = add nuw nsw i32 %i, 1 + %cmp = icmp ult i32 %inc, 10 + br i1 %cmp, label %for.body, label %for.end, !llvm.loop !0 + +for.end: + ret void +} + +; Test 2: llvm.loop.unroll.disable -> OpLoopControlINTEL DontUnroll. +; CHECK-SPIRV: test_unroll_disable +; CHECK-SPIRV: OpLoopControlINTEL DontUnroll +; CHECK-SPIRV-NEXT: OpBranchConditional + +define spir_kernel void @test_unroll_disable(ptr addrspace(1) %dst) { +entry: + br label %for.body + +for.body: + %i = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %ptr = getelementptr inbounds i32, ptr addrspace(1) %dst, i32 %i + store i32 %i, ptr addrspace(1) %ptr, align 4 + %inc = add nuw nsw i32 %i, 1 + %cmp = icmp ult i32 %inc, 10 + br i1 %cmp, label %for.body, label %for.end, !llvm.loop !1 + +for.end: + ret void +} + +; Test 3: llvm.loop.unroll.count N -> OpLoopControlINTEL PartialCount N. +; CHECK-SPIRV: test_unroll_count +; CHECK-SPIRV: OpLoopControlINTEL PartialCount 4 +; CHECK-SPIRV-NEXT: OpBranchConditional + +define spir_kernel void @test_unroll_count(ptr addrspace(1) %dst) { +entry: + br label %for.body + +for.body: + %i = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %ptr = getelementptr inbounds i32, ptr addrspace(1) %dst, i32 %i + store i32 %i, ptr addrspace(1) %ptr, align 4 + %inc = add nuw nsw i32 %i, 1 + %cmp = icmp ult i32 %inc, 10 + br i1 %cmp, label %for.body, label %for.end, !llvm.loop !2 + +for.end: + ret void +} + +; Test 4: llvm.loop.unroll.full -> OpLoopControlINTEL Unroll. +; CHECK-SPIRV: test_unroll_full +; CHECK-SPIRV: OpLoopControlINTEL Unroll +; CHECK-SPIRV-NEXT: OpBranchConditional + +define spir_kernel void @test_unroll_full(ptr addrspace(1) %dst) { +entry: + br label %for.body + +for.body: + %i = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %ptr = getelementptr inbounds i32, ptr addrspace(1) %dst, i32 %i + store i32 %i, ptr addrspace(1) %ptr, align 4 + %inc = add nuw nsw i32 %i, 1 + %cmp = icmp ult i32 %inc, 10 + br i1 %cmp, label %for.body, label %for.end, !llvm.loop !3 + +for.end: + ret void +} + +!0 = distinct !{!0, !4} +!1 = distinct !{!1, !5} +!2 = distinct !{!2, !6} +!3 = distinct !{!3, !7} + +!4 = !{!"llvm.loop.unroll.enable"} +!5 = !{!"llvm.loop.unroll.disable"} +!6 = !{!"llvm.loop.unroll.count", i32 4} +!7 = !{!"llvm.loop.unroll.full"} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WavePrefixSum.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WavePrefixSum.ll new file mode 100644 index 0000000000000..5fb82fd9ebf19 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WavePrefixSum.ll @@ -0,0 +1,41 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; Test lowering to spir-v backend for various types and scalar/vector + +; CHECK-DAG: %[[#f16:]] = OpTypeFloat 16 +; CHECK-DAG: %[[#f32:]] = OpTypeFloat 32 +; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#v4_half:]] = OpTypeVector %[[#f16]] 4 +; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3 + +; CHECK-LABEL: Begin function test_float +; CHECK: %[[#fexpr:]] = OpFunctionParameter %[[#f32]] +define float @test_float(float %fexpr) { +entry: +; CHECK: %[[#fret:]] = OpGroupNonUniformFAdd %[[#f32]] %[[#scope]] ExclusiveScan %[[#fexpr]] + %0 = call float @llvm.spv.wave.prefix.sum.f32(float %fexpr) + ret float %0 +} + +; CHECK-LABEL: Begin function test_int +; CHECK: %[[#iexpr:]] = OpFunctionParameter %[[#uint]] +define i32 @test_int(i32 %iexpr) { +entry: +; CHECK: %[[#iret:]] = OpGroupNonUniformIAdd %[[#uint]] %[[#scope]] ExclusiveScan %[[#iexpr]] + %0 = call i32 @llvm.spv.wave.prefix.sum.i32(i32 %iexpr) + ret i32 %0 +} + +; CHECK-LABEL: Begin function test_vhalf +; CHECK: %[[#vbexpr:]] = OpFunctionParameter %[[#v4_half]] +define <4 x half> @test_vhalf(<4 x half> %vbexpr) { +entry: +; CHECK: %[[#vhalfret:]] = OpGroupNonUniformFAdd %[[#v4_half]] %[[#scope]] ExclusiveScan %[[#vbexpr]] + %0 = call <4 x half> @llvm.spv.wave.prefix.sum.v4half(<4 x half> %vbexpr) + ret <4 x half> %0 +} + +declare float @llvm.spv.wave.prefix.sum.f32(float) +declare i32 @llvm.spv.wave.prefix.sum.i32(i32) +declare <4 x half> @llvm.spv.wave.prefix.sum.v4half(<4 x half>) diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll index 9ff4babd8a918..f756762755b51 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll @@ -25,7 +25,7 @@ entry: ; Test that we use the dot product op when capabilities allow -; CHECK-DOT: %[[#DOT:]] = OpSDot %[[#int_32]] %[[#X]] %[[#Y]] +; CHECK-DOT: %[[#DOT:]] = OpSDot %[[#int_32]] %[[#X]] %[[#Y]] PackedVectorFormat4x8Bit ; CHECK-DOT: %[[#RES:]] = OpIAdd %[[#int_32]] %[[#DOT]] %[[#ACC]] ; Test expansion is used when spirv dot product capabilities aren't available: diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll index 5e41c9dc79dd2..907cf622f609f 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll @@ -25,7 +25,7 @@ entry: ; Test that we use the dot product op when capabilities allow -; CHECK-DOT: %[[#DOT:]] = OpUDot %[[#int_32]] %[[#X]] %[[#Y]] +; CHECK-DOT: %[[#DOT:]] = OpUDot %[[#int_32]] %[[#X]] %[[#Y]] PackedVectorFormat4x8Bit ; CHECK-DOT: %[[#RES:]] = OpIAdd %[[#int_32]] %[[#DOT]] %[[#ACC]] ; Test expansion is used when spirv dot product capabilities aren't available: diff --git a/llvm/test/CodeGen/SPIRV/is-shader-env.ll b/llvm/test/CodeGen/SPIRV/is-shader-env.ll new file mode 100644 index 0000000000000..0365f93e781e6 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/is-shader-env.ll @@ -0,0 +1,34 @@ +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val --target-env vulkan1.3 %} + +; Regression test for https://github.com/llvm/llvm-project/issues/171898 +; When triple is spirv-unknown-unknown and a non-entry-point function using +; wide vectors (e.g. <8 x i32>) appears before the entry point with +; hlsl.shader attribute, the environment must be resolved early enough that +; legalization uses the correct vector size limits. + +; CHECK-DAG: OpCapability Shader +; CHECK-DAG: OpEntryPoint GLCompute %[[#entry:]] "main" +; CHECK-NOT: OpTypeVector %{{.*}} 8 + +@GVec4 = internal addrspace(10) global <4 x double> zeroinitializer +@Lows = internal addrspace(10) global <4 x i32> zeroinitializer +@Highs = internal addrspace(10) global <4 x i32> zeroinitializer + +define internal void @test_split() { +entry: + %0 = load <8 x i32>, ptr addrspace(10) @GVec4, align 32 + %1 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> + %2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> + store <4 x i32> %1, ptr addrspace(10) @Lows, align 16 + store <4 x i32> %2, ptr addrspace(10) @Highs, align 16 + ret void +} + +define void @main() local_unnamed_addr #0 { +entry: + call void @test_split() + ret void +} + +attributes #0 = { "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" } diff --git a/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca-count.ll b/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca-count.ll index 553b54746b5b6..e591bb3ea1e50 100644 --- a/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca-count.ll +++ b/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca-count.ll @@ -1,11 +1,11 @@ ; RUN: opt -S -passes=spirv-legalize-zero-size-arrays -mtriple=spirv64-unknown-unknown < %s | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown -spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} -; Test that zero-size array alloca with dynamic count allocates element type with count. +; Test that zero-size array alloca with dynamic count allocates just i8 define void @test_alloca_with_count(i32 %n) { ; CHECK-LABEL: @test_alloca_with_count( -; CHECK-NEXT: [[ARR:%.*]] = alloca ptr addrspace(4), align 4 +; CHECK-NEXT: [[ARR:%.*]] = alloca i8, align 4 ; CHECK-NEXT: ret void %arr = alloca [0 x i32], i32 %n, align 4 ret void diff --git a/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca-nested.ll b/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca-nested.ll index 8e8f75aae2d02..4949a25a61f30 100644 --- a/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca-nested.ll +++ b/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca-nested.ll @@ -1,10 +1,10 @@ ; RUN: opt -S -passes=spirv-legalize-zero-size-arrays -mtriple=spirv64-unknown-unknown < %s | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown -spirv-ext=+SPV_INTEL_variable_length_array %s -o - -filetype=obj | spirv-val %} -; Test that zero-size array alloca with nested arrays allocates element type. +; Test that zero-size array alloca with nested arrays allocates i8 define ptr @test_alloca_with_count(i32 %n) { ; CHECK-LABEL: @test_alloca_with_count( -; CHECK-NEXT: [[ARR:%.*]] = alloca ptr addrspace(4), align 4 +; CHECK-NEXT: [[ARR:%.*]] = alloca i8, align 4 ; CHECK-NEXT: ret ptr [[ARR]] %arr = alloca [0 x [0 x [0 x i32] ] ], align 4 ret ptr %arr diff --git a/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca.ll b/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca.ll index 2bf05bc249214..1b4a4db94a41d 100644 --- a/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca.ll +++ b/llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-alloca.ll @@ -1,12 +1,12 @@ ; RUN: opt -S -passes=spirv-legalize-zero-size-arrays -mtriple=spirv64-unknown-unknown < %s | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; Test that alloca of zero-size array allocates element type instead. +; Test that alloca of zero-size array allocates i8 instead define void @test_alloca_zero_array() { ; CHECK-LABEL: @test_alloca_zero_array( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[ARR:%.*]] = alloca ptr addrspace(4), align 4 +; CHECK-NEXT: [[ARR:%.*]] = alloca i8, align 4 ; CHECK-NEXT: ret void entry: %arr = alloca [0 x i32], align 4 diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll index 2d769ff6ab59c..95ea8472d4cc9 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll @@ -39,8 +39,8 @@ ; CHECK: %[[#Volatile:]] = OpFunctionParameter %[[#]] ; CHECK: %[[#Entry:]] = OpLabel -; CHECK: %[[#IsZeroLen:]] = OpIEqual %[[#]] %[[#Zero:]] %[[#Len]] -; CHECK: OpBranchConditional %[[#IsZeroLen]] %[[#End:]] %[[#WhileBody:]] +; CHECK: %[[#IsNonZeroLen:]] = OpINotEqual %[[#]] %[[#Len]] %[[#Zero:]] +; CHECK: OpBranchConditional %[[#IsNonZeroLen]] %[[#WhileBody:]] %[[#End:]] ; CHECK: %[[#WhileBody]] = OpLabel ; CHECK: %[[#Offset:]] = OpPhi %[[#]] %[[#Zero]] %[[#Entry]] %[[#OffsetInc:]] %[[#WhileBody]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sincos-glsl.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sincos-glsl.ll new file mode 100644 index 0000000000000..7d8096555d024 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sincos-glsl.ll @@ -0,0 +1,38 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-vulkan1.3-compute %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan1.3-compute %s -o - -filetype=obj | spirv-val %} + +; Test if llvm.sincos is lowered to glsl::sin and glsl::cos with results +; correctly reused by the original llvm.sincos user. + +; CHECK-DAG: %[[#ExtInstId:]] = OpExtInstImport "GLSL.std.450" +; CHECK-DAG: %[[#FloatTy:]] = OpTypeFloat 32 +; CHECK-DAG: %[[#Vec2FloatTy:]] = OpTypeVector %[[#FloatTy]] 2 + +; CHECK: %[[#XParam:]] = OpFunctionParameter %[[#FloatTy]] +; CHECK: %[[#SinRes:]] = OpExtInst %[[#FloatTy]] %[[#ExtInstId]] Sin %[[#XParam]] +; CHECK: %[[#CosRes:]] = OpExtInst %[[#FloatTy]] %[[#ExtInstId]] Cos %[[#XParam]] +; CHECK: %[[#Sum:]] = OpFAdd %[[#FloatTy]] %[[#SinRes]] %[[#CosRes]] +; CHECK: OpReturnValue %[[#Sum]] +define float @test_sincos_scalar(float %x) { + %result = call { float, float } @llvm.sincos.f32(float %x) + %sin = extractvalue { float, float } %result, 0 + %cos = extractvalue { float, float } %result, 1 + %sum = fadd float %sin, %cos + ret float %sum +} + +; CHECK: %[[#XvParam:]] = OpFunctionParameter %[[#Vec2FloatTy]] +; CHECK: %[[#SinResv:]] = OpExtInst %[[#Vec2FloatTy]] %[[#ExtInstId]] Sin %[[#XvParam]] +; CHECK: %[[#CosResv:]] = OpExtInst %[[#Vec2FloatTy]] %[[#ExtInstId]] Cos %[[#XvParam]] +; CHECK: %[[#Sumv:]] = OpFAdd %[[#Vec2FloatTy]] %[[#SinResv]] %[[#CosResv]] +; CHECK: OpReturnValue %[[#Sumv]] +define <2 x float> @test_sincos_vec2(<2 x float> %x) { + %result = call { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float> %x) + %sin = extractvalue { <2 x float>, <2 x float> } %result, 0 + %cos = extractvalue { <2 x float>, <2 x float> } %result, 1 + %sum = fadd <2 x float> %sin, %cos + ret <2 x float> %sum +} + +declare { float, float } @llvm.sincos.f32(float) +declare { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float>) diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sincos-opencl.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sincos-opencl.ll new file mode 100644 index 0000000000000..73f4df7a32e4b --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/sincos-opencl.ll @@ -0,0 +1,42 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; Test if llvm.sincos is lowered to opencl::sincos with the result +; correctly reused by the original llvm.sincos user. + +; CHECK-DAG: %[[#ExtInstId:]] = OpExtInstImport "OpenCL.std" +; CHECK-DAG: %[[#FloatTy:]] = OpTypeFloat 32 +; CHECK-DAG: %[[#FnPtrTy:]] = OpTypePointer Function %[[#FloatTy]] +; CHECK-DAG: %[[#Vec2FloatTy:]] = OpTypeVector %[[#FloatTy]] 2 +; CHECK-DAG: %[[#FnPtrVec2Ty:]] = OpTypePointer Function %[[#Vec2FloatTy]] + +; CHECK: %[[#XParam:]] = OpFunctionParameter %[[#FloatTy]] +; CHECK: %[[#Var:]] = OpVariable %[[#FnPtrTy]] Function +; CHECK: %[[#SinRes:]] = OpExtInst %[[#FloatTy]] %[[#ExtInstId]] sincos %[[#XParam]] %[[#Var]] +; CHECK: %[[#CosRes:]] = OpLoad %[[#FloatTy]] %[[#Var]] +; CHECK: %[[#Sum:]] = OpFAdd %[[#FloatTy]] %[[#SinRes]] %[[#CosRes]] +; CHECK: OpReturnValue %[[#Sum]] +define float @test_sincos_scalar(float %x) { + %result = call { float, float } @llvm.sincos.f32(float %x) + %sin = extractvalue { float, float } %result, 0 + %cos = extractvalue { float, float } %result, 1 + %sum = fadd float %sin, %cos + ret float %sum +} + +; CHECK: %[[#XvParam:]] = OpFunctionParameter %[[#Vec2FloatTy]] +; CHECK: %[[#Varv:]] = OpVariable %[[#FnPtrVec2Ty]] Function +; CHECK: %[[#SinResv:]] = OpExtInst %[[#Vec2FloatTy]] %[[#ExtInstId]] sincos %[[#XvParam]] %[[#Varv]] +; CHECK: %[[#CosResv:]] = OpLoad %[[#Vec2FloatTy]] %[[#Varv]] +; CHECK: %[[#Sumv:]] = OpFAdd %[[#Vec2FloatTy]] %[[#SinResv]] %[[#CosResv]] +; CHECK: OpReturnValue %[[#Sumv]] +define <2 x float> @test_sincos_vec2(<2 x float> %x) { + %result = call { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float> %x) + %sin = extractvalue { <2 x float>, <2 x float> } %result, 0 + %cos = extractvalue { <2 x float>, <2 x float> } %result, 1 + %sum = fadd <2 x float> %sin, %cos + ret <2 x float> %sum +} + +declare { float, float } @llvm.sincos.f32(float) +declare { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float>) diff --git a/llvm/test/CodeGen/SPIRV/llvm-used.ll b/llvm/test/CodeGen/SPIRV/llvm-used.ll new file mode 100644 index 0000000000000..58e96555462db --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/llvm-used.ll @@ -0,0 +1,19 @@ +; RUN: llc -verify-machineinstrs -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: llc -verify-machineinstrs -mtriple=spirv-unknown-vulkan %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan %s -o - -filetype=obj | spirv-val %} + +; Verify that llvm.used is not lowered. +; CHECK: OpName %{{[0-9]+}} "unused" +; CHECK-NOT: OpName %{{[0-9]+}} "llvm.used" + +; Check that the type of llvm.used is not emitted too. +; CHECK-NOT: OpTypeArray + +@unused = private addrspace(3) global i32 0 +@llvm.used = appending addrspace(2) global [1 x ptr addrspace (4)] [ptr addrspace(4) addrspacecast (ptr addrspace(3) @unused to ptr addrspace(4))] + +define spir_func void @foo() { +entry: + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/memory-inst-large-align.ll b/llvm/test/CodeGen/SPIRV/memory-inst-large-align.ll new file mode 100644 index 0000000000000..ecff638f276b0 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/memory-inst-large-align.ll @@ -0,0 +1,21 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#VEC:]] = OpTypeVector %[[#]] 4 +; CHECK-DAG: %[[#PTR:]] = OpTypePointer CrossWorkgroup %[[#VEC]] +; CHECK-DAG: %[[#NULL:]] = OpConstantNull %[[#VEC]] + +; CHECK: OpStore %[[#]] %[[#NULL]] Aligned 256 +; CHECK: OpLoad %[[#VEC]] %[[#]] Aligned 256 + +define spir_func void @test_store_align256(ptr addrspace(1) %p) addrspace(4) { +entry: + store <4 x i64> zeroinitializer, ptr addrspace(1) %p, align 256 + ret void +} + +define spir_func <4 x i64> @test_load_align256(ptr addrspace(1) %p) addrspace(4) { +entry: + %v = load <4 x i64>, ptr addrspace(1) %p, align 256 + ret <4 x i64> %v +} diff --git a/llvm/test/CodeGen/SPIRV/memset-large-size.ll b/llvm/test/CodeGen/SPIRV/memset-large-size.ll new file mode 100644 index 0000000000000..007b8df7e4628 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/memset-large-size.ll @@ -0,0 +1,22 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; A regression test that checks if memset with a size larger exceeding i8 range +; does not crash the backend. + +; CHECK-DAG: %[[#INT8:]] = OpTypeInt 8 0 +; CHECK-DAG: %[[#INT32:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#INT64:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#SIZE:]] = OpConstant %[[#INT32]] 444 +; CHECK-DAG: %[[#ARRTY:]] = OpTypeArray %[[#INT8]] %[[#SIZE]] +; CHECK-DAG: %[[#ZERO:]] = OpConstantNull %[[#ARRTY]] +; CHECK-DAG: %[[#LEN:]] = OpConstant %[[#INT64]] 444 +; CHECK: OpCopyMemorySized %[[#]] %[[#]] %[[#LEN]] Aligned 1 + +define spir_func void @test_memset_large(ptr addrspace(4) %p) addrspace(4) { +entry: + call addrspace(4) void @llvm.memset.p4.i64(ptr addrspace(4) %p, i8 0, i64 444, i1 false) + ret void +} + +declare void @llvm.memset.p4.i64(ptr addrspace(4) writeonly captures(none), i8, i64, i1 immarg) addrspace(4) diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll new file mode 100644 index 0000000000000..b567dd492d712 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided-64.ll @@ -0,0 +1,37 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#LongTy:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#IntTy:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#Int8Ty:]] = OpTypeInt 8 0 +; CHECK-DAG: %[[#EventTy:]] = OpTypeEvent +; CHECK-DAG: %[[#WGPtrTy:]] = OpTypePointer Workgroup %[[#Int8Ty]] +; CHECK-DAG: %[[#CWGPtrTy:]] = OpTypePointer CrossWorkgroup %[[#Int8Ty]] +; CHECK-DAG: %[[#Scope:]] = OpConstant %[[#IntTy]] 2 +; CHECK-DAG: %[[#NumElem:]] = OpConstant %[[#LongTy]] 123 +; CHECK-DAG: %[[#Stride:]] = OpConstant %[[#LongTy]] 1 +; CHECK-DAG: %[[#DstNull:]] = OpConstantNull %[[#WGPtrTy]] +; CHECK-DAG: %[[#SrcNull:]] = OpConstantNull %[[#CWGPtrTy]] +; CHECK-DAG: %[[#EventNull:]] = OpConstantNull %[[#EventTy]] +; CHECK-DAG: %[[#GenPtrEventTy:]] = OpTypePointer Generic %[[#EventTy]] +; CHECK-DAG: %[[#FunPtrEventTy:]] = OpTypePointer Function %[[#EventTy]] +; CHECK: OpFunction +; CHECK: %[[#Var:]] = OpVariable %[[#FunPtrEventTy]] Function +; CHECK: %[[#ResEvent:]] = OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#DstNull]] %[[#SrcNull]] %[[#NumElem]] %[[#Stride]] %[[#EventNull]] +; CHECK: OpStore %[[#Var]] %[[#ResEvent]] +; CHECK: %[[#PtrEventGen:]] = OpPtrCastToGeneric %[[#GenPtrEventTy]] %[[#Var]] +; CHECK: OpGroupWaitEvents %[[#Scope]] %[[#]] %[[#PtrEventGen]] +; CHECK: OpFunctionEnd + +define spir_kernel void @foo() { + %event = alloca target("spirv.Event"), align 8 + %call = call spir_func target("spirv.Event") @_Z29async_work_group_strided_copyPU3AS3hPU3AS1Khmm9ocl_event(ptr addrspace(3) null, ptr addrspace(1) null, i64 123, i64 1, target("spirv.Event") zeroinitializer) + store target("spirv.Event") %call, ptr %event, align 8 + %event.ascast = addrspacecast ptr %event to ptr addrspace(4) + call spir_func void @_Z17wait_group_eventsiPU3AS49ocl_event(i32 1, ptr addrspace(4) %event.ascast) + ret void +} + +declare spir_func target("spirv.Event") @_Z29async_work_group_strided_copyPU3AS3hPU3AS1Khmm9ocl_event(ptr addrspace(3), ptr addrspace(1), i64, i64, target("spirv.Event")) +declare spir_func void @_Z17wait_group_eventsiPU3AS49ocl_event(i32, ptr addrspace(4)) + diff --git a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll index efb99dc19eb99..e0d1b243a1445 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/OpGroupAsyncCopy-strided.ll @@ -1,34 +1,35 @@ -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} - -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-SPIRV-DAG: %[[#LongTy:]] = OpTypeInt 64 0 -; CHECK-SPIRV-DAG: %[[#IntTy:]] = OpTypeInt 32 0 -; CHECK-SPIRV-DAG: %[[#EventTy:]] = OpTypeEvent -; CHECK-SPIRV-DAG: %[[#Scope:]] = OpConstant %[[#IntTy]] 2 -; CHECK-SPIRV-DAG: %[[#Num:]] = OpConstant %[[#LongTy]] 123 -; CHECK-SPIRV-DAG: %[[#Null:]] = OpConstantNull -; CHECK-SPIRV-DAG: %[[#Stride:]] = OpConstant %[[#LongTy]] 1 -; CHECK-SPIRV-DAG: %[[#GenPtrEventTy:]] = OpTypePointer Generic %[[#EventTy]] -; CHECK-SPIRV-DAG: %[[#FunPtrEventTy:]] = OpTypePointer Function %[[#EventTy]] -; CHECK-SPIRV: OpFunction -; CHECK-SPIRV: %[[#Var:]] = OpVariable %[[#FunPtrEventTy]] Function -; CHECK-SPIRV: %[[#ResEvent:]] = OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#Null]] %[[#Null]] %[[#Num]] %[[#Stride]] %[[#Null]] -; CHECK-SPIRV: OpStore %[[#Var]] %[[#ResEvent]] -; CHECK-SPIRV: %[[#PtrEventGen:]] = OpPtrCastToGeneric %[[#GenPtrEventTy]] %[[#Var]] -; CHECK-SPIRV: OpGroupWaitEvents %[[#Scope]] %[[#Num]] %[[#PtrEventGen]] -; CHECK-SPIRV: OpFunctionEnd +; CHECK-DAG: %[[#IntTy:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#Int8Ty:]] = OpTypeInt 8 0 +; CHECK-DAG: %[[#EventTy:]] = OpTypeEvent +; CHECK-DAG: %[[#WGPtrTy:]] = OpTypePointer Workgroup %[[#Int8Ty]] +; CHECK-DAG: %[[#CWGPtrTy:]] = OpTypePointer CrossWorkgroup %[[#Int8Ty]] +; CHECK-DAG: %[[#Scope:]] = OpConstant %[[#IntTy]] 2 +; CHECK-DAG: %[[#NumElem:]] = OpConstant %[[#IntTy]] 123 +; CHECK-DAG: %[[#Stride:]] = OpConstant %[[#IntTy]] 1 +; CHECK-DAG: %[[#DstNull:]] = OpConstantNull %[[#WGPtrTy]] +; CHECK-DAG: %[[#SrcNull:]] = OpConstantNull %[[#CWGPtrTy]] +; CHECK-DAG: %[[#EventNull:]] = OpConstantNull %[[#EventTy]] +; CHECK-DAG: %[[#GenPtrEventTy:]] = OpTypePointer Generic %[[#EventTy]] +; CHECK-DAG: %[[#FunPtrEventTy:]] = OpTypePointer Function %[[#EventTy]] +; CHECK: OpFunction +; CHECK: %[[#Var:]] = OpVariable %[[#FunPtrEventTy]] Function +; CHECK: %[[#ResEvent:]] = OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#DstNull]] %[[#SrcNull]] %[[#NumElem]] %[[#Stride]] %[[#EventNull]] +; CHECK: OpStore %[[#Var]] %[[#ResEvent]] +; CHECK: %[[#PtrEventGen:]] = OpPtrCastToGeneric %[[#GenPtrEventTy]] %[[#Var]] +; CHECK: OpGroupWaitEvents %[[#Scope]] %[[#Stride]] %[[#PtrEventGen]] +; CHECK: OpFunctionEnd define spir_kernel void @foo() { - %event = alloca ptr, align 8 - %call = call spir_func ptr @_Z29async_work_group_strided_copyPU3AS3hPU3AS1Khmm9ocl_event(ptr null, ptr null, i64 123, i64 1, ptr null) - store ptr %call, ptr %event, align 8 + %event = alloca target("spirv.Event"), align 8 + %call = call spir_func target("spirv.Event") @_Z29async_work_group_strided_copyPU3AS3hPU3AS1Khjj9ocl_event(ptr addrspace(3) null, ptr addrspace(1) null, i32 123, i32 1, target("spirv.Event") zeroinitializer) + store target("spirv.Event") %call, ptr %event, align 8 %event.ascast = addrspacecast ptr %event to ptr addrspace(4) - call spir_func void @_Z17wait_group_eventsiPU3AS49ocl_event(i64 123, ptr addrspace(4) %event.ascast) + call spir_func void @_Z17wait_group_eventsiPU3AS49ocl_event(i32 1, ptr addrspace(4) %event.ascast) ret void } -declare spir_func ptr @_Z29async_work_group_strided_copyPU3AS3hPU3AS1Khmm9ocl_event(ptr, ptr, i64, i64, ptr) -declare spir_func void @_Z17wait_group_eventsiPU3AS49ocl_event(i64, ptr addrspace(4)) +declare spir_func target("spirv.Event") @_Z29async_work_group_strided_copyPU3AS3hPU3AS1Khjj9ocl_event(ptr addrspace(3), ptr addrspace(1), i32, i32, target("spirv.Event")) +declare spir_func void @_Z17wait_group_eventsiPU3AS49ocl_event(i32, ptr addrspace(4)) diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null-64.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null-64.ll new file mode 100644 index 0000000000000..6f4a7521cdbe9 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null-64.ll @@ -0,0 +1,101 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#IntTy:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#LongTy:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#EventTy:]] = OpTypeEvent +; CHECK-DAG: %[[#ConstEvent:]] = OpConstantNull %[[#EventTy]] +; CHECK-DAG: %[[#TyEventPtr:]] = OpTypePointer Function %[[#EventTy]] +; CHECK-DAG: %[[#TyEventPtrGen:]] = OpTypePointer Generic %[[#EventTy]] +; CHECK-DAG: %[[#TyStruct:]] = OpTypeStruct %[[#EventTy]] +; CHECK-DAG: %[[#TyStructPtr:]] = OpTypePointer Function %[[#TyStruct]] +; CHECK-DAG: %[[#TyChar:]] = OpTypeInt 8 0 +; CHECK-DAG: %[[#TyV4:]] = OpTypeVector %[[#TyChar]] 4 +; CHECK-DAG: %[[#TyStructV4:]] = OpTypeStruct %[[#TyV4]] +; CHECK-DAG: %[[#TyPtrSV4_CW:]] = OpTypePointer CrossWorkgroup %[[#TyStructV4]] +; CHECK-DAG: %[[#TyPtrV4_W:]] = OpTypePointer Workgroup %[[#TyV4]] +; CHECK-DAG: %[[#TyPtrV4_CW:]] = OpTypePointer CrossWorkgroup %[[#TyV4]] +; CHECK-DAG: %[[#TyHalf:]] = OpTypeFloat 16 +; CHECK-DAG: %[[#TyHalfV2:]] = OpTypeVector %[[#TyHalf]] 2 +; CHECK-DAG: %[[#TyHalfV2_W:]] = OpTypePointer Workgroup %[[#TyHalfV2]] +; CHECK-DAG: %[[#TyHalfV2_CW:]] = OpTypePointer CrossWorkgroup %[[#TyHalfV2]] +; CHECK-DAG: %[[#Scope:]] = OpConstant %[[#IntTy]] 2 +; CHECK-DAG: %[[#NumElem:]] = OpConstant %[[#LongTy]] 16 +; CHECK-DAG: %[[#Stride:]] = OpConstant %[[#LongTy]] 10 +; CHECK-DAG: %[[#NumEvents:]] = OpConstant %[[#IntTy]] 1 + +; Check correct translation of __spirv_GroupAsyncCopy and target("spirv.Event") zeroinitializer + +%StructEvent = type { target("spirv.Event") } + +@G_r = global target("spirv.Event") poison + +; CHECK: OpFunction +; CHECK: %[[#HalfA1:]] = OpFunctionParameter %[[#TyHalfV2_W]] +; CHECK: %[[#HalfA2:]] = OpFunctionParameter %[[#TyHalfV2_CW]] +; CHECK: OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#HalfA1]] %[[#HalfA2]] %[[#NumElem]] %[[#Stride]] %[[#ConstEvent]] +; CHECK: OpFunctionEnd + +define spir_kernel void @test_half(ptr addrspace(3) %_arg1, ptr addrspace(1) %_arg2) { +entry: + %r = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv2_DF16_PU3AS1KS_mm9ocl_event(i32 2, ptr addrspace(3) %_arg1, ptr addrspace(1) %_arg2, i64 16, i64 10, target("spirv.Event") zeroinitializer) + store target("spirv.Event") %r, ptr @G_r + ret void +} + +declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv2_DF16_PU3AS1KS_mm9ocl_event(i32 noundef, ptr addrspace(3) noundef, ptr addrspace(1) noundef, i64 noundef, i64 noundef, target("spirv.Event")) + +; CHECK: OpFunction +; CHECK: OpFunctionParameter +; CHECK: %[[#Src:]] = OpFunctionParameter +; CHECK: %[[#EventVar:]] = OpVariable %[[#TyEventPtr]] Function +; CHECK: %[[#Dest:]] = OpInBoundsPtrAccessChain +; CHECK: %[[#CopyRes:]] = OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#Dest]] %[[#Src]] %[[#NumElem]] %[[#Stride]] %[[#ConstEvent]] +; CHECK: OpStore %[[#EventVar]] %[[#CopyRes]] +; CHECK: OpFunctionEnd + +define spir_kernel void @foo(ptr addrspace(1) %_arg_out_ptr, ptr addrspace(3) %_arg_local_acc) { +entry: + %var = alloca %StructEvent + %dev_event.i.sroa.0 = alloca target("spirv.Event") + %add.ptr.i26 = getelementptr inbounds i32, ptr addrspace(1) %_arg_out_ptr, i64 0 + %call3.i = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS1iPU3AS3Kimm9ocl_event(i32 2, ptr addrspace(1) %add.ptr.i26, ptr addrspace(3) %_arg_local_acc, i64 16, i64 10, target("spirv.Event") zeroinitializer) + store target("spirv.Event") %call3.i, ptr %dev_event.i.sroa.0 + ret void +} + +declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS1iPU3AS3Kimm9ocl_event(i32, ptr addrspace(1), ptr addrspace(3), i64, i64, target("spirv.Event")) + +; Check correct type inference when calling __spirv_GroupAsyncCopy: +; we expect that the Backend is able to deduce a type of the %_arg_Local +; given facts that it's possible to deduce a type of the %_arg +; and %_arg_Local and %_arg are source/destination arguments in OpGroupAsyncCopy + +%Vec4 = type { <4 x i8> } + +; CHECK: OpFunction +; CHECK: %[[#BarArg1:]] = OpFunctionParameter %[[#TyPtrV4_W]] +; CHECK: %[[#BarArg2:]] = OpFunctionParameter %[[#TyPtrSV4_CW]] +; CHECK: %[[#EventVarBar:]] = OpVariable %[[#TyStructPtr]] Function +; CHECK: %[[#EventVarBarCasted2:]] = OpBitcast %[[#TyEventPtr]] %[[#EventVarBar]] +; CHECK: %[[#ResBar:]] = OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#BarArg1]] %[[#]] %[[#NumElem]] %[[#Stride]] %[[#ConstEvent]] +; CHECK: %[[#EventVarBarCasted:]] = OpBitcast %[[#TyEventPtr]] %[[#EventVarBar]] +; CHECK: OpStore %[[#EventVarBarCasted]] %[[#ResBar]] +; CHECK: %[[#EventVarBarGen:]] = OpPtrCastToGeneric %[[#TyEventPtrGen]] %[[#EventVarBarCasted2]] +; CHECK: OpGroupWaitEvents %[[#Scope]] %[[#NumEvents]] %[[#EventVarBarGen]] +; CHECK: OpFunctionEnd + +define spir_kernel void @bar(ptr addrspace(3) %_arg_Local, ptr addrspace(1) readonly %_arg) { +entry: + %E1 = alloca %StructEvent + %srcptr = getelementptr inbounds %Vec4, ptr addrspace(1) %_arg, i64 0 + %r1 = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv4_aPU3AS1KS_mm9ocl_event(i32 2, ptr addrspace(3) %_arg_Local, ptr addrspace(1) %srcptr, i64 16, i64 10, target("spirv.Event") zeroinitializer) + store target("spirv.Event") %r1, ptr %E1 + %E.ascast.i = addrspacecast ptr %E1 to ptr addrspace(4) + call spir_func void @_Z23__spirv_GroupWaitEventsjiP9ocl_event(i32 2, i32 1, ptr addrspace(4) %E.ascast.i) + ret void +} + +declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv4_aPU3AS1KS_mm9ocl_event(i32, ptr addrspace(3), ptr addrspace(1), i64, i64, target("spirv.Event")) +declare dso_local spir_func void @_Z23__spirv_GroupWaitEventsjiP9ocl_event(i32, i32, ptr addrspace(4)) + diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll index 7658362773218..d1f485cd4115f 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll @@ -1,14 +1,12 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} - -; CHECK-DAG: %[[#TyEvent:]] = OpTypeEvent -; CHECK-DAG: %[[#TyStruct:]] = OpTypeStruct %[[#TyEvent]] -; CHECK-DAG: %[[#ConstEvent:]] = OpConstantNull %[[#TyEvent]] -; CHECK-DAG: %[[#TyEventPtr:]] = OpTypePointer Function %[[#TyEvent]] -; CHECK-DAG: %[[#TyEventPtrGen:]] = OpTypePointer Generic %[[#TyEvent]] +; CHECK-DAG: %[[#IntTy:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#EventTy:]] = OpTypeEvent +; CHECK-DAG: %[[#ConstEvent:]] = OpConstantNull %[[#EventTy]] +; CHECK-DAG: %[[#TyEventPtr:]] = OpTypePointer Function %[[#EventTy]] +; CHECK-DAG: %[[#TyEventPtrGen:]] = OpTypePointer Generic %[[#EventTy]] +; CHECK-DAG: %[[#TyStruct:]] = OpTypeStruct %[[#EventTy]] ; CHECK-DAG: %[[#TyStructPtr:]] = OpTypePointer Function %[[#TyStruct]] ; CHECK-DAG: %[[#TyChar:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#TyV4:]] = OpTypeVector %[[#TyChar]] 4 @@ -20,34 +18,38 @@ ; CHECK-DAG: %[[#TyHalfV2:]] = OpTypeVector %[[#TyHalf]] 2 ; CHECK-DAG: %[[#TyHalfV2_W:]] = OpTypePointer Workgroup %[[#TyHalfV2]] ; CHECK-DAG: %[[#TyHalfV2_CW:]] = OpTypePointer CrossWorkgroup %[[#TyHalfV2]] +; CHECK-DAG: %[[#Scope:]] = OpConstant %[[#IntTy]] 2 +; CHECK-DAG: %[[#NumElem:]] = OpConstant %[[#IntTy]] 16 +; CHECK-DAG: %[[#Stride:]] = OpConstant %[[#IntTy]] 10 +; CHECK-DAG: %[[#NumEvents:]] = OpConstant %[[#IntTy]] 1 ; Check correct translation of __spirv_GroupAsyncCopy and target("spirv.Event") zeroinitializer -; CHECK: OpFunction -; CHECK: %[[#HalfA1:]] = OpFunctionParameter %[[#TyHalfV2_W:]] -; CHECK: %[[#HalfA2:]] = OpFunctionParameter %[[#TyHalfV2_CW:]] -; CHECK: OpGroupAsyncCopy %[[#TyEvent]] %[[#]] %[[#HalfA1]] %[[#HalfA2]] %[[#]] %[[#]] %[[#ConstEvent]] -; CHECK: OpFunctionEnd - %StructEvent = type { target("spirv.Event") } @G_r = global target("spirv.Event") poison +; CHECK: OpFunction +; CHECK: %[[#HalfA1:]] = OpFunctionParameter %[[#TyHalfV2_W]] +; CHECK: %[[#HalfA2:]] = OpFunctionParameter %[[#TyHalfV2_CW]] +; CHECK: OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#HalfA1]] %[[#HalfA2]] %[[#NumElem]] %[[#Stride]] %[[#ConstEvent]] +; CHECK: OpFunctionEnd + define spir_kernel void @test_half(ptr addrspace(3) %_arg1, ptr addrspace(1) %_arg2) { entry: - %r = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv2_DF16_PU3AS1KS_mm9ocl_event(i32 2, ptr addrspace(3) %_arg1, ptr addrspace(1) %_arg2, i64 16, i64 10, target("spirv.Event") zeroinitializer) + %r = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv2_DF16_PU3AS1KS_jj9ocl_event(i32 2, ptr addrspace(3) %_arg1, ptr addrspace(1) %_arg2, i32 16, i32 10, target("spirv.Event") zeroinitializer) store target("spirv.Event") %r, ptr @G_r ret void } -declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv2_DF16_PU3AS1KS_mm9ocl_event(i32 noundef, ptr addrspace(3) noundef, ptr addrspace(1) noundef, i64 noundef, i64 noundef, target("spirv.Event")) +declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv2_DF16_PU3AS1KS_jj9ocl_event(i32 noundef, ptr addrspace(3) noundef, ptr addrspace(1) noundef, i32 noundef, i32 noundef, target("spirv.Event")) ; CHECK: OpFunction ; CHECK: OpFunctionParameter ; CHECK: %[[#Src:]] = OpFunctionParameter ; CHECK: %[[#EventVar:]] = OpVariable %[[#TyEventPtr]] Function ; CHECK: %[[#Dest:]] = OpInBoundsPtrAccessChain -; CHECK: %[[#CopyRes:]] = OpGroupAsyncCopy %[[#TyEvent]] %[[#]] %[[#Dest]] %[[#Src]] %[[#]] %[[#]] %[[#ConstEvent]] +; CHECK: %[[#CopyRes:]] = OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#Dest]] %[[#Src]] %[[#NumElem]] %[[#Stride]] %[[#ConstEvent]] ; CHECK: OpStore %[[#EventVar]] %[[#CopyRes]] ; CHECK: OpFunctionEnd @@ -56,42 +58,43 @@ entry: %var = alloca %StructEvent %dev_event.i.sroa.0 = alloca target("spirv.Event") %add.ptr.i26 = getelementptr inbounds i32, ptr addrspace(1) %_arg_out_ptr, i64 0 - %call3.i = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS1iPU3AS3Kimm9ocl_event(i32 2, ptr addrspace(1) %add.ptr.i26, ptr addrspace(3) %_arg_local_acc, i64 16, i64 10, target("spirv.Event") zeroinitializer) + %call3.i = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS1iPU3AS3Kijj9ocl_event(i32 2, ptr addrspace(1) %add.ptr.i26, ptr addrspace(3) %_arg_local_acc, i32 16, i32 10, target("spirv.Event") zeroinitializer) store target("spirv.Event") %call3.i, ptr %dev_event.i.sroa.0 ret void } -declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS1iPU3AS3Kimm9ocl_event(i32, ptr addrspace(1), ptr addrspace(3), i64, i64, target("spirv.Event")) +declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS1iPU3AS3Kijj9ocl_event(i32, ptr addrspace(1), ptr addrspace(3), i32, i32, target("spirv.Event")) ; Check correct type inference when calling __spirv_GroupAsyncCopy: ; we expect that the Backend is able to deduce a type of the %_arg_Local ; given facts that it's possible to deduce a type of the %_arg ; and %_arg_Local and %_arg are source/destination arguments in OpGroupAsyncCopy +%Vec4 = type { <4 x i8> } + ; CHECK: OpFunction ; CHECK: %[[#BarArg1:]] = OpFunctionParameter %[[#TyPtrV4_W]] ; CHECK: %[[#BarArg2:]] = OpFunctionParameter %[[#TyPtrSV4_CW]] ; CHECK: %[[#EventVarBar:]] = OpVariable %[[#TyStructPtr]] Function ; CHECK: %[[#EventVarBarCasted2:]] = OpBitcast %[[#TyEventPtr]] %[[#EventVarBar]] -; CHECK: %[[#ResBar:]] = OpGroupAsyncCopy %[[#TyEvent]] %[[#]] %[[#BarArg1]] %[[#]] %[[#]] %[[#]] %[[#ConstEvent]] +; CHECK: %[[#ResBar:]] = OpGroupAsyncCopy %[[#EventTy]] %[[#Scope]] %[[#BarArg1]] %[[#]] %[[#NumElem]] %[[#Stride]] %[[#ConstEvent]] ; CHECK: %[[#EventVarBarCasted:]] = OpBitcast %[[#TyEventPtr]] %[[#EventVarBar]] ; CHECK: OpStore %[[#EventVarBarCasted]] %[[#ResBar]] ; CHECK: %[[#EventVarBarGen:]] = OpPtrCastToGeneric %[[#TyEventPtrGen]] %[[#EventVarBarCasted2]] -; CHECK: OpGroupWaitEvents %[[#]] %[[#]] %[[#EventVarBarGen]] +; CHECK: OpGroupWaitEvents %[[#Scope]] %[[#NumEvents]] %[[#EventVarBarGen]] ; CHECK: OpFunctionEnd -%Vec4 = type { <4 x i8> } - define spir_kernel void @bar(ptr addrspace(3) %_arg_Local, ptr addrspace(1) readonly %_arg) { entry: %E1 = alloca %StructEvent %srcptr = getelementptr inbounds %Vec4, ptr addrspace(1) %_arg, i64 0 - %r1 = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv4_aPU3AS1KS_mm9ocl_event(i32 2, ptr addrspace(3) %_arg_Local, ptr addrspace(1) %srcptr, i64 16, i64 10, target("spirv.Event") zeroinitializer) + %r1 = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv4_aPU3AS1KS_jj9ocl_event(i32 2, ptr addrspace(3) %_arg_Local, ptr addrspace(1) %srcptr, i32 16, i32 10, target("spirv.Event") zeroinitializer) store target("spirv.Event") %r1, ptr %E1 %E.ascast.i = addrspacecast ptr %E1 to ptr addrspace(4) call spir_func void @_Z23__spirv_GroupWaitEventsjiP9ocl_event(i32 2, i32 1, ptr addrspace(4) %E.ascast.i) ret void } -declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv4_aPU3AS1KS_mm9ocl_event(i32, ptr addrspace(3), ptr addrspace(1), i64, i64, target("spirv.Event")) +declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS3Dv4_aPU3AS1KS_jj9ocl_event(i32, ptr addrspace(3), ptr addrspace(1), i32, i32, target("spirv.Event")) declare dso_local spir_func void @_Z23__spirv_GroupWaitEventsjiP9ocl_event(i32, i32, ptr addrspace(4)) + diff --git a/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll b/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll new file mode 100644 index 0000000000000..1a01e91d1f8f2 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/zos-alias-unsupported.ll @@ -0,0 +1,16 @@ +; Test aliasing errors on z/OS + +; RUN: not llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 2>&1 | FileCheck %s + +; CHECK: error: Only aliases to functions is supported in GOFF. +; CHECK: error: Weak alias/reference not supported on z/OS + +@actual_variable = global i32 0 +@alias_variable = alias i32, ptr @actual_variable + +@foo1 = weak alias i32 (i32), ptr @foo +define hidden void @foo() { +entry: + ret void +} + diff --git a/llvm/test/CodeGen/SystemZ/zos-dwarf.ll b/llvm/test/CodeGen/SystemZ/zos-dwarf.ll new file mode 100644 index 0000000000000..919602c799f7a --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/zos-dwarf.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s + +@fortytwo = hidden global i32 42, align 4, !dbg !0 + +define hidden signext i32 @getFortyTwo() !dbg !8 { +entry: + %0 = load i32, ptr @fortytwo, align 4, !dbg !11 + ret i32 %0, !dbg !12 +} + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!6, !7} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "fortytwo", scope: !2, file: !3, line: 2, type: !5, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C11, file: !3, producer: "clang version 22.0.0git", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, globals: !4, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "fortytwo.c", directory: "") +!4 = !{!0} +!5 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!6 = !{i32 7, !"Dwarf Version", i32 4} +!7 = !{i32 2, !"Debug Info Version", i32 3} +!8 = distinct !DISubprogram(name: "getFortyTwo", scope: !3, file: !3, line: 4, type: !9, scopeLine: 4, spFlags: DISPFlagDefinition, unit: !2) +!9 = !DISubroutineType(types: !10) +!10 = !{!5} +!11 = !DILocation(line: 4, column: 28, scope: !8) +!12 = !DILocation(line: 4, column: 21, scope: !8) + +; Check the emitted section definition +; CHECK: D_ABREV CATTR ALIGN(3),FILL(0),NOLOAD,RMODE(64) +; CHECK: D_INFO CATTR ALIGN(3),FILL(0),NOLOAD,RMODE(64) +; CHECK: D_STR CATTR ALIGN(3),FILL(0),NOLOAD,RMODE(64) diff --git a/llvm/test/CodeGen/SystemZ/zos-func-alias.ll b/llvm/test/CodeGen/SystemZ/zos-func-alias.ll new file mode 100644 index 0000000000000..7e93570e44534 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/zos-func-alias.ll @@ -0,0 +1,17 @@ +; Test function aliasing on z/OS +; +; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s + +; CHECK: ENTRY foo +; CHECK-NEXT: foo XATTR LINKAGE(XPLINK),REFERENCE(CODE),SCOPE(LIBRARY) +; CHECK-NEXT: foo DS 0H +; CHECK-NEXT: ENTRY foo +; CHECK-NEXT: foo1 XATTR LINKAGE(XPLINK),REFERENCE(CODE),SCOPE(LIBRARY) +; CHECK-NEXT: foo1 DS 0H + +@foo1 = hidden alias i32 (i32), ptr @foo + +define hidden void @foo() { +entry: + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/zos-jumptable.ll b/llvm/test/CodeGen/SystemZ/zos-jumptable.ll new file mode 100644 index 0000000000000..4b11759874088 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/zos-jumptable.ll @@ -0,0 +1,34 @@ +; RUN: llc -mtriple s390x-zos -emit-gnuas-syntax-on-zos=0 < %s | FileCheck %s + +define void @jumptable(i32 signext %in, ptr %out) { +; CHECK-LABEL: jumptable DS 0H +; CHECK: larl 3,L#JTI0_0 +; CHECK: L#func_end1 DS 0H +; CHECK: L#JTI0_0 DS 0H +; CHECK: DC AD(L#BB0_2) +; CHECK: DC AD(L#BB0_5) +; CHECK: DC AD(L#BB0_3) +; CHECK: DC AD(L#BB0_4) + +entry: + switch i32 %in, label %exit [ + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + i32 4, label %bb4 + ] +bb1: + store i32 4, ptr %out + br label %exit +bb2: + store i32 3, ptr %out + br label %exit +bb3: + store i32 2, ptr %out + br label %exit +bb4: + store i32 1, ptr %out + br label %exit +exit: + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/zos-lower-constant.ll b/llvm/test/CodeGen/SystemZ/zos-lower-constant.ll new file mode 100644 index 0000000000000..c91b39f72de08 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/zos-lower-constant.ll @@ -0,0 +1,24 @@ +; Test lowering of constants on z/OS +; +; RUN: llc < %s -mtriple=s390x-ibm-zos -emit-gnuas-syntax-on-zos=0 | FileCheck %s + +; CHECK: func_s CSECT +; CHECK: DC AD(AD({{.*}}#S)+XL8'0') +; CHECK: func_e CSECT +; CHECK: DC VD(bar) +; CHECK: DC RD(foo) +; CHECK-NEXT: DC VD(foo) +@x = hidden global i32 4077, align 4 +@y = hidden global ptr @x, align 8 +@func_s = hidden global ptr @foo, align 8 +@func_e = hidden global ptr @bar, align 8 + +define hidden void @bar() { +entry: + ret void +} + +define internal void @foo() { +entry: + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll b/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll index bdd0660651456..458b27460763f 100644 --- a/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll +++ b/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll @@ -87,39 +87,39 @@ define void @func1(ptr %ptr) { ; CHECK-LABEL: func2 ; CHECK64: stmg 6,7,1744(4) ; CHECK64: aghi 4,-320 -; CHECK64: std 15,{{[0-9]+}}(4) * 8-byte Spill -; CHECK64: std 14,{{[0-9]+}}(4) * 8-byte Spill -; CHECK64: std 13,{{[0-9]+}}(4) * 8-byte Spill -; CHECK64: std 12,{{[0-9]+}}(4) * 8-byte Spill -; CHECK64: std 11,{{[0-9]+}}(4) * 8-byte Spill -; CHECK64: std 10,{{[0-9]+}}(4) * 8-byte Spill -; CHECK64: std 9,{{[0-9]+}}(4) * 8-byte Spill +; CHECK64: vst 16,{{[0-9]+}}(4),4 * 16-byte Spill +; CHECK64: vst 17,{{[0-9]+}}(4),4 * 16-byte Spill +; CHECK64: vst 18,{{[0-9]+}}(4),4 * 16-byte Spill +; CHECK64: vst 19,{{[0-9]+}}(4),4 * 16-byte Spill +; CHECK64: vst 20,{{[0-9]+}}(4),4 * 16-byte Spill +; CHECK64: vst 21,{{[0-9]+}}(4),4 * 16-byte Spill +; CHECK64: vst 22,{{[0-9]+}}(4),4 * 16-byte Spill +; CHECK64: vst 23,{{[0-9]+}}(4),4 * 16-byte Spill ; CHECK64: std 8,{{[0-9]+}}(4) * 8-byte Spill -; CHECK64: vst 23,{{[0-9]+}}(4),4 * 16-byte Spill -; CHECK64: vst 22,{{[0-9]+}}(4),4 * 16-byte Spill -; CHECK64: vst 21,{{[0-9]+}}(4),4 * 16-byte Spill -; CHECK64: vst 20,{{[0-9]+}}(4),4 * 16-byte Spill -; CHECK64: vst 19,{{[0-9]+}}(4),4 * 16-byte Spill -; CHECK64: vst 18,{{[0-9]+}}(4),4 * 16-byte Spill -; CHECK64: vst 17,{{[0-9]+}}(4),4 * 16-byte Spill -; CHECK64: vst 16,{{[0-9]+}}(4),4 * 16-byte Spill +; CHECK64: std 9,{{[0-9]+}}(4) * 8-byte Spill +; CHECK64: std 10,{{[0-9]+}}(4) * 8-byte Spill +; CHECK64: std 11,{{[0-9]+}}(4) * 8-byte Spill +; CHECK64: std 12,{{[0-9]+}}(4) * 8-byte Spill +; CHECK64: std 13,{{[0-9]+}}(4) * 8-byte Spill +; CHECK64: std 14,{{[0-9]+}}(4) * 8-byte Spill +; CHECK64: std 15,{{[0-9]+}}(4) * 8-byte Spill -; CHECK64: ld 15,{{[0-9]+}}(4) * 8-byte Reload -; CHECK64: ld 14,{{[0-9]+}}(4) * 8-byte Reload -; CHECK64: ld 13,{{[0-9]+}}(4) * 8-byte Reload -; CHECK64: ld 12,{{[0-9]+}}(4) * 8-byte Reload -; CHECK64: ld 11,{{[0-9]+}}(4) * 8-byte Reload -; CHECK64: ld 10,{{[0-9]+}}(4) * 8-byte Reload -; CHECK64: ld 9,{{[0-9]+}}(4) * 8-byte Reload +; CHECK64: vl 16,{{[0-9]+}}(4),4 * 16-byte Reload +; CHECK64: vl 17,{{[0-9]+}}(4),4 * 16-byte Reload +; CHECK64: vl 18,{{[0-9]+}}(4),4 * 16-byte Reload +; CHECK64: vl 19,{{[0-9]+}}(4),4 * 16-byte Reload +; CHECK64: vl 20,{{[0-9]+}}(4),4 * 16-byte Reload +; CHECK64: vl 21,{{[0-9]+}}(4),4 * 16-byte Reload +; CHECK64: vl 22,{{[0-9]+}}(4),4 * 16-byte Reload +; CHECK64: vl 23,{{[0-9]+}}(4),4 * 16-byte Reload ; CHECK64: ld 8,{{[0-9]+}}(4) * 8-byte Reload -; CHECK64: vl 23,{{[0-9]+}}(4),4 * 16-byte Reload -; CHECK64: vl 22,{{[0-9]+}}(4),4 * 16-byte Reload -; CHECK64: vl 21,{{[0-9]+}}(4),4 * 16-byte Reload -; CHECK64: vl 20,{{[0-9]+}}(4),4 * 16-byte Reload -; CHECK64: vl 19,{{[0-9]+}}(4),4 * 16-byte Reload -; CHECK64: vl 18,{{[0-9]+}}(4),4 * 16-byte Reload -; CHECK64: vl 17,{{[0-9]+}}(4),4 * 16-byte Reload -; CHECK64: vl 16,{{[0-9]+}}(4),4 * 16-byte Reload +; CHECK64: ld 9,{{[0-9]+}}(4) * 8-byte Reload +; CHECK64: ld 10,{{[0-9]+}}(4) * 8-byte Reload +; CHECK64: ld 11,{{[0-9]+}}(4) * 8-byte Reload +; CHECK64: ld 12,{{[0-9]+}}(4) * 8-byte Reload +; CHECK64: ld 13,{{[0-9]+}}(4) * 8-byte Reload +; CHECK64: ld 14,{{[0-9]+}}(4) * 8-byte Reload +; CHECK64: ld 15,{{[0-9]+}}(4) * 8-byte Reload ; CHECK64: lg 7,2072(4) ; CHECK64: aghi 4,320 ; CHECK64: b 2(7) @@ -316,6 +316,27 @@ define i64 @func5(i64 %n) { ret i64 %call } +; Require saving of r5, which is not restored. +; CHECK64: stmg 5,9,1864(4) +; CHECK64-NEXT: aghi 4,-192 +; CHECK64: lmg 7,9,2072(4) +; CHECK64-NEXT: aghi 4,192 +declare i32 @personality(...) +declare void @panic() +define void @func6() uwtable personality ptr @personality { +entry: + br label %bb1 +bb1: + invoke void @panic() + to label %bb2 unwind label %bb3 +bb2: + ret void +bb3: + %lp = landingpad { ptr, i32 } + catch ptr null + br label %bb1 +} + ; CHECK-LABEL: large_stack ; CHECK64: agfi 4,-1048800 ; CHECK64-NEXT: llgt 3,1208 @@ -336,12 +357,12 @@ define void @large_stack0() { ; CHECK64: lgr 0,3 ; CHECK64: llgt 3,1208 ; CHECK64: cg 4,64(3) -; CHECK64: jhe L#BB7_2 +; CHECK64: jhe L#BB8_2 ; CHECK64: %bb.1: ; CHECK64: lg 3,72(3) ; CHECK64: basr 3,3 ; CHECK64: bcr 0,7 -; CHECK64: L#BB7_2: +; CHECK64: L#BB8_2: ; CHECK64: stmg 6,7,2064(4) ; CHECK64: lgr 3,0 @@ -361,12 +382,12 @@ define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) { ; CHECK64: agfi 4,-1048800 ; CHECK64: llgt 3,1208 ; CHECK64: cg 4,64(3) -; CHECK64: jhe L#BB8_2 +; CHECK64: jhe L#BB9_2 ; CHECK64: %bb.1: ; CHECK64: lg 3,72(3) ; CHECK64: basr 3,3 ; CHECK64: bcr 0,7 -; CHECK64: L#BB8_2: +; CHECK64: L#BB9_2: ; CHECK64: lgr 3,0 ; CHECK64: lg 3,2192(3) ; CHECK64: stmg 4,12,2048(4) diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir index 17ef52a002163..66d01a3773035 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir @@ -64,7 +64,7 @@ declare <4 x i1> @llvm.arm.mve.vctp32(i32) #5 - attributes #0 = { nofree norecurse nounwind optsize "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-fp16fml,-hwdiv-arm,-i8mm,-sb,-sha2" } + attributes #0 = { nofree norecurse nounwind optsize denormal_fpenv(preservesign, float: ieee) "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-fp16fml,-hwdiv-arm,-i8mm,-sb,-sha2" } attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } attributes #2 = { nofree nosync nounwind readnone willreturn } attributes #3 = { argmemonly nofree nosync nounwind readonly willreturn } diff --git a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir index e48a038037a55..c9a9239b52f51 100644 --- a/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir +++ b/llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir @@ -13,7 +13,7 @@ ret <4 x float> %inactive1 } - attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" } + attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll index db779dea717da..5a154f4f4adbe 100644 --- a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll +++ b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll @@ -179,7 +179,7 @@ return: ; preds = %entry, %if.end ; CHECK-NOT: aut ; CHECK: b _Z1hii -attributes #0 = { minsize noinline optsize "sign-return-address"="non-leaf" "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m3" "target-features"="+armv7-m,+hwdiv,+thumb-mode" "use-soft-float"="false" } +attributes #0 = { minsize noinline optsize "sign-return-address"="non-leaf" denormal_fpenv(preservesign, float: ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m3" "target-features"="+armv7-m,+hwdiv,+thumb-mode" "use-soft-float"="false" } attributes #1 = { nounwind "sign-return-address"="non-leaf" } attributes #2 = { noreturn "sign-return-address"="non-leaf" } diff --git a/llvm/test/CodeGen/WebAssembly/GlobalISel/gisel-commandline-option.ll b/llvm/test/CodeGen/WebAssembly/GlobalISel/gisel-commandline-option.ll new file mode 100644 index 0000000000000..47b05c8160fd1 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/GlobalISel/gisel-commandline-option.ll @@ -0,0 +1,53 @@ +; RUN: llc -mtriple=wasm32-- -debug-pass=Structure %s -o /dev/null 2>&1 \ +; RUN: -verify-machineinstrs=0 -O0 -global-isel \ +; RUN: | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK,ENABLED-O0 + +; RUN: llc -mtriple=wasm32-- -debug-pass=Structure %s -o /dev/null 2>&1 \ +; RUN: -verify-machineinstrs=0 -global-isel \ +; RUN: | FileCheck %s --check-prefixes=ENABLED,NOFALLBACK,ENABLED-O1 + +; RUN: llc -mtriple=wasm32-- -debug-pass=Structure %s -o /dev/null 2>&1 \ +; RUN: -verify-machineinstrs=0 -global-isel -global-isel-abort=2 \ +; RUN: | FileCheck %s --check-prefixes=ENABLED,FALLBACK,ENABLED-O1 + +; RUN: llc -mtriple=wasm32-- -debug-pass=Structure %s -o /dev/null 2>&1 \ +; RUN: -verify-machineinstrs=0 \ +; RUN: | FileCheck %s --check-prefixes=DISABLED + +; ENABLED: IRTranslator +; ENABLED-O0-NEXT: Analysis containing CSE Info +; ENABLED-NEXT: Analysis for ComputingKnownBits +; ENABLED-O1-NEXT: MachineDominator Tree Construction +; ENABLED-O1-NEXT: Analysis containing CSE Info +; ENABLED-O1-NEXT: WebAssemblyPreLegalizerCombiner +; ENABLED-NEXT: Legalizer +; ENABLED-O1-NEXT: MachineDominator Tree Construction +; ENABLED-O1-NEXT: WebAssemblyPostLegalizerCombiner +; ENABLED-NEXT: RegBankSelect +; ENABLED-NEXT: Analysis for ComputingKnownBits +; ENABLED-O1-NEXT: Natural Loop Information +; ENABLED-O1-NEXT: Lazy Branch Probability Analysis +; ENABLED-O1-NEXT: Lazy Block Frequency Analysis +; ENABLED-NEXT: InstructionSelect +; NOFALLBACK-NEXT: WebAssembly Argument Move +; NOFALLBACK-NEXT: WebAssembly Set p2align Operands +; NOFALLBACK-NEXT: WebAssembly Fix br_table Defaults +; NOFALLBACK-NEXT: WebAssembly Clean Code After Trap +; ENABLED-NEXT: ResetMachineFunction + +; FALLBACK: WebAssembly Instruction Selection +; FALLBACK-NEXT: WebAssembly Argument Move +; FALLBACK-NEXT: WebAssembly Set p2align Operands +; FALLBACK-NEXT: WebAssembly Fix br_table Defaults +; FALLBACK-NEXT: WebAssembly Clean Code After Trap + +; NOFALLBACK-NOT: WebAssembly Instruction Selection + +; DISABLED-NOT: IRTranslator + +; DISABLED: WebAssembly Instruction Selection +; DISABLED: Finalize ISel and expand pseudo-instructions + +define void @empty() { + ret void +} diff --git a/llvm/test/CodeGen/WebAssembly/common-error.ll b/llvm/test/CodeGen/WebAssembly/common-error.ll new file mode 100644 index 0000000000000..8fce516fbf88e --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/common-error.ll @@ -0,0 +1,6 @@ +; RUN: not llc -mtriple=wasm32-unknown-unknown -filetype=asm %s -o - 2>&1 | FileCheck %s + +; CHECK: common symbols are not yet implemented for Wasm: x +; CHECK: common symbols are not yet implemented for Wasm: y +@x = common global i32 0, align 4 +@y = common global i32 0, align 4 diff --git a/llvm/test/CodeGen/WebAssembly/offset-fastisel.ll b/llvm/test/CodeGen/WebAssembly/offset-fastisel.ll index b896f8fde247e..c004410f18122 100644 --- a/llvm/test/CodeGen/WebAssembly/offset-fastisel.ll +++ b/llvm/test/CodeGen/WebAssembly/offset-fastisel.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s +; RUN: llc < %s -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,DEFAULT +; RUN: llc < %s -mcpu=mvp -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,MVP ; TODO: Merge this with offset.ll when fast-isel matches better. @@ -117,15 +118,22 @@ define i32 @load_i8_u_with_folded_offset(ptr %p) { ; TODO: this should be load8_s, need to fold sign-/zero-extend in fast-isel define i32 @load_i8_s_with_folded_offset(ptr %p) { -; CHECK-LABEL: load_i8_s_with_folded_offset: -; CHECK: .functype load_i8_s_with_folded_offset (i32) -> (i32) -; CHECK-NEXT: # %bb.0: -; CHECK-NEXT: i32.load8_u $push3=, 24($0) -; CHECK-NEXT: i32.const $push0=, 24 -; CHECK-NEXT: i32.shl $push1=, $pop3, $pop0 -; CHECK-NEXT: i32.const $push4=, 24 -; CHECK-NEXT: i32.shr_s $push2=, $pop1, $pop4 -; CHECK-NEXT: # fallthrough-return +; DEFAULT-LABEL: load_i8_s_with_folded_offset: +; DEFAULT: .functype load_i8_s_with_folded_offset (i32) -> (i32) +; DEFAULT-NEXT: # %bb.0: +; DEFAULT-NEXT: i32.load8_u $push1=, 24($0) +; DEFAULT-NEXT: i32.extend8_s $push0=, $pop1 +; DEFAULT-NEXT: # fallthrough-return +; +; MVP-LABEL: load_i8_s_with_folded_offset: +; MVP: .functype load_i8_s_with_folded_offset (i32) -> (i32) +; MVP-NEXT: # %bb.0: +; MVP-NEXT: i32.load8_u $push3=, 24($0) +; MVP-NEXT: i32.const $push0=, 24 +; MVP-NEXT: i32.shl $push1=, $pop3, $pop0 +; MVP-NEXT: i32.const $push4=, 24 +; MVP-NEXT: i32.shr_s $push2=, $pop1, $pop4 +; MVP-NEXT: # fallthrough-return %q = ptrtoint ptr %p to i32 %r = add nuw i32 %q, 24 %s = inttoptr i32 %r to ptr diff --git a/llvm/test/CodeGen/WebAssembly/signext-arg.ll b/llvm/test/CodeGen/WebAssembly/signext-arg.ll index fa595056c840c..b28b93fb57916 100644 --- a/llvm/test/CodeGen/WebAssembly/signext-arg.ll +++ b/llvm/test/CodeGen/WebAssembly/signext-arg.ll @@ -1,5 +1,5 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s +; RUN: llc < %s -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes=CHECK,DEFAULT +; RUN: llc < %s -mcpu=mvp -asm-verbose=false -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes=CHECK,MVP target triple = "wasm32-unknown-unknown" @@ -7,11 +7,16 @@ declare i32 @get_int(i16 %arg) define i32 @func_1(i16 %arg1 , i32 %arg2) #0 { ; CHECK-LABEL: func_1: -; CHECK: i32.const $push1=, 16 -; CHECK-NEXT: i32.shl $push2=, $0, $pop1 -; CHECK-NEXT: i32.const $push4=, 16 -; CHECK-NEXT: i32.shr_s $push3=, $pop2, $pop4 -; CHECK-NEXT: call $push0=, get_int, $pop3 +; +; DEFAULT: i32.extend16_s $push1=, $0 +; DEFAULT-NEXT: call $push0=, get_int, $pop1 +; +; MVP: i32.const $push1=, 16 +; MVP-NEXT: i32.shl $push2=, $0, $pop1 +; MVP-NEXT: i32.const $push4=, 16 +; MVP-NEXT: i32.shr_s $push3=, $pop2, $pop4 +; MVP-NEXT: call $push0=, get_int, $pop3 +; ; CHECK-NEXT: end_function entry: %retval = call i32 @get_int(i16 signext %arg1) diff --git a/llvm/test/CodeGen/WebAssembly/signext-inreg.ll b/llvm/test/CodeGen/WebAssembly/signext-inreg.ll index 5778a9418a3d4..c56ee860082c8 100644 --- a/llvm/test/CodeGen/WebAssembly/signext-inreg.ll +++ b/llvm/test/CodeGen/WebAssembly/signext-inreg.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -mattr=+sign-ext -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s -; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=NOSIGNEXT - +; RUN: llc < %s -mattr=+sign-ext -fast-isel=0 -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s +; RUN: llc < %s -mattr=-sign-ext -asm-verbose=false -fast-isel=0 -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=NOSIGNEXT +; RUN: llc < %s -mattr=+sign-ext -fast-isel=1 -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s +; RUN: llc < %s -mattr=-sign-ext -asm-verbose=false -fast-isel=1 -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefix=NOSIGNEXT target triple = "wasm32-unknown-unknown" ; CHECK-LABEL: i32_extend8_s: diff --git a/llvm/test/CodeGen/WebAssembly/simd-dot-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-dot-reductions.ll index 3654aaec18600..d9e5aba6f9b94 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-dot-reductions.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-dot-reductions.ll @@ -104,3 +104,40 @@ define <4 x i32> @dot_wrong_shuffle(<8 x i16> %a, <8 x i16> %b) { %res = add <4 x i32> %shuffle1, %shuffle2 ret <4 x i32> %res } + +define dso_local <4 x i32> @dot_with_bitcast_both(<4 x i32> %a, <4 x i32> %b) unnamed_addr { +; CHECK-LABEL: dot_with_bitcast_both: +; CHECK: .functype dot_with_bitcast_both (v128, v128) -> (v128) +; CHECK-NEXT: # %bb.0: # %start +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: i32x4.dot_i16x8_s +; CHECK-NEXT: # fallthrough-return +start: + %_4 = bitcast <4 x i32> %a to <8 x i16> + %_5 = bitcast <4 x i32> %b to <8 x i16> + %0 = sext <8 x i16> %_4 to <8 x i32> + %1 = sext <8 x i16> %_5 to <8 x i32> + %2 = mul nsw <8 x i32> %1, %0 + %3 = shufflevector <8 x i32> %2, <8 x i32> poison, <4 x i32> + %4 = shufflevector <8 x i32> %2, <8 x i32> poison, <4 x i32> + %5 = add <4 x i32> %3, %4 + ret <4 x i32> %5 +} + +define <4 x i32> @dot_with_bitcast_one(<4 x i32> %a) { +; CHECK-LABEL: dot_with_bitcast_one: +; CHECK: .functype dot_with_bitcast_one (v128) -> (v128) +; CHECK-NEXT: # %bb.0: # %start +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: i32x4.extadd_pairwise_i16x8_s +; CHECK-NEXT: # fallthrough-return +start: + %a1 = bitcast <4 x i32> %a to <8 x i16> + %0 = shufflevector <8 x i16> %a1, <8 x i16> %a1, <4 x i32> + %1 = shufflevector <8 x i16> %a1, <8 x i16> %a1, <4 x i32> + %2 = sext <4 x i16> %0 to <4 x i32> + %3 = sext <4 x i16> %1 to <4 x i32> + %4 = add nsw <4 x i32> %2, %3 + ret <4 x i32> %4 +} diff --git a/llvm/test/CodeGen/X86/2006-05-22-FPSetEQ.ll b/llvm/test/CodeGen/X86/2006-05-22-FPSetEQ.ll index 940fe8cf6ba75..9f072c6334c07 100644 --- a/llvm/test/CodeGen/X86/2006-05-22-FPSetEQ.ll +++ b/llvm/test/CodeGen/X86/2006-05-22-FPSetEQ.ll @@ -1,13 +1,17 @@ -; RUN: llc < %s -mtriple=i686-- -mattr=-sse | FileCheck %s -check-prefix=WITHNANS -; RUN: llc < %s -mtriple=i686-- -mattr=-sse -enable-no-nans-fp-math | FileCheck %s -check-prefix=NONANS +; RUN: llc < %s -mtriple=i686-- -mattr=-sse | FileCheck %s -; WITHNANS-LABEL: test: -; WITHNANS: setnp -; NONANS-LABEL: test: -; NONANS-NOT: setnp define i32 @test(float %f) { +; CHECK-LABEL: test: +; CHECK: setnp %tmp = fcmp oeq float %f, 0.000000e+00 ; [#uses=1] %tmp.upgrd.1 = zext i1 %tmp to i32 ; [#uses=1] ret i32 %tmp.upgrd.1 } +define i32 @test_nnan(float %f) { +; CHECK-LABEL: test_nnan: +; CHECK-NOT: setnp + %tmp = fcmp nnan oeq float %f, 0.000000e+00 ; [#uses=1] + %tmp.upgrd.1 = zext i1 %tmp to i32 ; [#uses=1] + ret i32 %tmp.upgrd.1 +} diff --git a/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll b/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll index fb4b98ac38957..8146252235b00 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll @@ -162,17 +162,15 @@ define void @PR20134(ptr %a, i32 %i) { ; CHECK-NEXT: shlq $2, %rax ; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: leal 2(%rsi), %ecx -; CHECK-NEXT: movslq %ecx, %rdx -; CHECK-NEXT: movb $2, %cl -; CHECK-NEXT: shlq %cl, %rdx -; CHECK-NEXT: leaq (%rdi,%rdx), %rcx -; CHECK-NEXT: movl (%rcx), %edx -; CHECK-NEXT: addl (%rax), %edx +; CHECK-NEXT: movslq %ecx, %rcx +; CHECK-NEXT: shlq $2, %rcx +; CHECK-NEXT: addq %rdi, %rcx +; CHECK-NEXT: movl (%rcx), %ecx +; CHECK-NEXT: addl (%rax), %ecx ; CHECK-NEXT: movslq %esi, %rax -; CHECK-NEXT: movb $2, %cl -; CHECK-NEXT: shlq %cl, %rax +; CHECK-NEXT: shlq $2, %rax ; CHECK-NEXT: addq %rdi, %rax -; CHECK-NEXT: movl %edx, (%rax) +; CHECK-NEXT: movl %ecx, (%rax) ; CHECK-NEXT: retq %add1 = add nsw i32 %i, 1 @@ -202,17 +200,15 @@ define void @PR20134_zext(ptr %a, i32 %i) { ; CHECK-NEXT: shlq $2, %rax ; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: leal 2(%rsi), %ecx -; CHECK-NEXT: movl %ecx, %edx -; CHECK-NEXT: movb $2, %cl -; CHECK-NEXT: shlq %cl, %rdx -; CHECK-NEXT: leaq (%rdi,%rdx), %rcx -; CHECK-NEXT: movl (%rcx), %edx -; CHECK-NEXT: addl (%rax), %edx +; CHECK-NEXT: movl %ecx, %ecx +; CHECK-NEXT: shlq $2, %rcx +; CHECK-NEXT: addq %rdi, %rcx +; CHECK-NEXT: movl (%rcx), %ecx +; CHECK-NEXT: addl (%rax), %ecx ; CHECK-NEXT: movl %esi, %eax -; CHECK-NEXT: movb $2, %cl -; CHECK-NEXT: shlq %cl, %rax +; CHECK-NEXT: shlq $2, %rax ; CHECK-NEXT: addq %rdi, %rax -; CHECK-NEXT: movl %edx, (%rax) +; CHECK-NEXT: movl %ecx, (%rax) ; CHECK-NEXT: retq %add1 = add nuw i32 %i, 1 diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll index 83c319b073c4a..6c06d505e8231 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-x87.ll @@ -165,18 +165,17 @@ define void @f5(ptr %a, ptr %b) { ; X86-NEXT: [[LOAD2:%[0-9]+]]:gpr(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.a, align 8) ; X86-NEXT: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 4 ; X86-NEXT: [[PTR_ADD:%[0-9]+]]:gpr(p0) = nuw inbounds G_PTR_ADD [[LOAD]], [[C]](s32) - ; X86-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY [[PTR_ADD]](p0) - ; X86-NEXT: [[LOAD3:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.a + 4, basealign 8) + ; X86-NEXT: [[LOAD3:%[0-9]+]]:gpr(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s32) from %ir.a + 4, basealign 8) ; X86-NEXT: [[MV:%[0-9]+]]:gpr(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32) ; X86-NEXT: [[LOAD4:%[0-9]+]]:gpr(s32) = G_LOAD [[LOAD1]](p0) :: (load (s32) from %ir.b, align 8) ; X86-NEXT: [[PTR_ADD1:%[0-9]+]]:gpr(p0) = nuw inbounds G_PTR_ADD [[LOAD1]], [[C]](s32) ; X86-NEXT: [[LOAD5:%[0-9]+]]:gpr(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s32) from %ir.b + 4, basealign 8) ; X86-NEXT: [[MV1:%[0-9]+]]:gpr(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32) - ; X86-NEXT: [[COPY1:%[0-9]+]]:psr(s64) = COPY [[MV]](s64) - ; X86-NEXT: [[COPY2:%[0-9]+]]:psr(s64) = COPY [[MV1]](s64) - ; X86-NEXT: [[FADD:%[0-9]+]]:psr(s64) = G_FADD [[COPY1]], [[COPY2]] - ; X86-NEXT: [[COPY3:%[0-9]+]]:gpr(s64) = COPY [[FADD]](s64) - ; X86-NEXT: [[UV:%[0-9]+]]:gpr(s32), [[UV1:%[0-9]+]]:gpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64) + ; X86-NEXT: [[COPY:%[0-9]+]]:psr(s64) = COPY [[MV]](s64) + ; X86-NEXT: [[COPY1:%[0-9]+]]:psr(s64) = COPY [[MV1]](s64) + ; X86-NEXT: [[FADD:%[0-9]+]]:psr(s64) = G_FADD [[COPY]], [[COPY1]] + ; X86-NEXT: [[COPY2:%[0-9]+]]:gpr(s64) = COPY [[FADD]](s64) + ; X86-NEXT: [[UV:%[0-9]+]]:gpr(s32), [[UV1:%[0-9]+]]:gpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64) ; X86-NEXT: G_STORE [[UV]](s32), [[LOAD]](p0) :: (store (s32) into %ir.a, align 8) ; X86-NEXT: G_STORE [[UV1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.a + 4, basealign 8) ; X86-NEXT: RET 0 diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir index 60171e5bee1f6..d204e09dd9ef1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -112,7 +112,7 @@ body: | ; ALL-LABEL: name: anyext_s64_from_s1 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit $rax %0(s64) = COPY $rdi @@ -138,7 +138,7 @@ body: | ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit ; ALL: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr8_]], %subreg.sub_32bit + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOVZX32rr8_]], %subreg.sub_32bit ; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit $rax %0(s64) = COPY $rdi @@ -164,7 +164,7 @@ body: | ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit ; ALL: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]] - ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOVZX32rr16_]], %subreg.sub_32bit + ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOVZX32rr16_]], %subreg.sub_32bit ; ALL: $rax = COPY [[SUBREG_TO_REG]] ; ALL: RET 0, implicit $rax %0(s64) = COPY $rdi diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir index 44daf22b00a3c..0805a486a76a8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -316,13 +316,13 @@ body: | ; X86-LABEL: name: test_anyext_i1toi16 ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; X86-NEXT: $ax = COPY [[SUBREG_TO_REG]] ; X86-NEXT: RET 0, implicit $ax ; X64-LABEL: name: test_anyext_i1toi16 ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; X64-NEXT: $ax = COPY [[SUBREG_TO_REG]] ; X64-NEXT: RET 0, implicit $ax %0(s32) = COPY $edi @@ -348,13 +348,13 @@ body: | ; X86-LABEL: name: test_anyext_i1toi32 ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; X86-NEXT: $eax = COPY [[SUBREG_TO_REG]] ; X86-NEXT: RET 0, implicit $eax ; X64-LABEL: name: test_anyext_i1toi32 ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit - ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit + ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG [[COPY1]], %subreg.sub_8bit ; X64-NEXT: $eax = COPY [[SUBREG_TO_REG]] ; X64-NEXT: RET 0, implicit $eax %0(s32) = COPY $edi diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir index 2657482cd9e3c..a685b417a9b52 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir @@ -364,7 +364,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; CHECK-NEXT: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32rr]], %subreg.sub_32bit ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET 0, implicit $rax %0:gpr(s32) = COPY $edi diff --git a/llvm/test/CodeGen/X86/add-i512.ll b/llvm/test/CodeGen/X86/add-i512.ll index 16ba701072031..b7ed76da4922b 100644 --- a/llvm/test/CodeGen/X86/add-i512.ll +++ b/llvm/test/CodeGen/X86/add-i512.ll @@ -383,39 +383,150 @@ define i512 @test_inc_i512_mem(ptr %p0) nounwind { ; AVX2-NEXT: movq %rcx, 56(%rax) ; AVX2-NEXT: retq ; -; AVX512-LABEL: test_inc_i512_mem: -; AVX512: # %bb.0: -; AVX512-NEXT: movq %rdi, %rax -; AVX512-NEXT: movq 56(%rsi), %rcx -; AVX512-NEXT: movq 48(%rsi), %rdx -; AVX512-NEXT: movq 40(%rsi), %rdi -; AVX512-NEXT: movq 32(%rsi), %r8 -; AVX512-NEXT: movq 24(%rsi), %r9 -; AVX512-NEXT: movq 16(%rsi), %r10 -; AVX512-NEXT: movq (%rsi), %r11 -; AVX512-NEXT: movq 8(%rsi), %rsi -; AVX512-NEXT: addq $1, %r11 -; AVX512-NEXT: adcq $0, %rsi -; AVX512-NEXT: adcq $0, %r10 -; AVX512-NEXT: adcq $0, %r9 -; AVX512-NEXT: adcq $0, %r8 -; AVX512-NEXT: adcq $0, %rdi -; AVX512-NEXT: adcq $0, %rdx -; AVX512-NEXT: adcq $0, %rcx -; AVX512-NEXT: movq %r11, (%rax) -; AVX512-NEXT: movq %rsi, 8(%rax) -; AVX512-NEXT: movq %r10, 16(%rax) -; AVX512-NEXT: movq %r9, 24(%rax) -; AVX512-NEXT: movq %r8, 32(%rax) -; AVX512-NEXT: movq %rdi, 40(%rax) -; AVX512-NEXT: movq %rdx, 48(%rax) -; AVX512-NEXT: movq %rcx, 56(%rax) -; AVX512-NEXT: retq +; AVX512F-LABEL: test_inc_i512_mem: +; AVX512F: # %bb.0: +; AVX512F-NEXT: movq %rdi, %rax +; AVX512F-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm1 = -1 +; AVX512F-NEXT: vpsubq %zmm1, %zmm0, %zmm1 +; AVX512F-NEXT: vpcmpnleuq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %ecx +; AVX512F-NEXT: vptestnmq %zmm1, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %edx +; AVX512F-NEXT: movzbl %dl, %edx +; AVX512F-NEXT: leal (%rdx,%rcx,2), %ecx +; AVX512F-NEXT: xorl %edx, %ecx +; AVX512F-NEXT: kmovw %ecx, %k1 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_inc_i512_mem: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: movq %rdi, %rax +; AVX512VL-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm1 = -1 +; AVX512VL-NEXT: vpsubq %zmm1, %zmm0, %zmm1 +; AVX512VL-NEXT: vpcmpnleuq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovd %k0, %ecx +; AVX512VL-NEXT: vptestnmq %zmm1, %zmm1, %k0 +; AVX512VL-NEXT: kmovb %k0, %edx +; AVX512VL-NEXT: leal (%rdx,%rcx,2), %ecx +; AVX512VL-NEXT: xorl %edx, %ecx +; AVX512VL-NEXT: kmovd %ecx, %k1 +; AVX512VL-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq %a0 = load i512, ptr %p0 %r = add i512 %a0, 1 ret i512 %r } +define i512 @test_add_i512_mem_mem(ptr %p0, ptr %p1) nounwind { +; SSE-LABEL: test_add_i512_mem_mem: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: movq 56(%rsi), %rcx +; SSE-NEXT: movq (%rsi), %rdi +; SSE-NEXT: addq (%rdx), %rdi +; SSE-NEXT: movq 8(%rsi), %r8 +; SSE-NEXT: adcq 8(%rdx), %r8 +; SSE-NEXT: movq 16(%rsi), %r9 +; SSE-NEXT: adcq 16(%rdx), %r9 +; SSE-NEXT: movq 24(%rsi), %r10 +; SSE-NEXT: adcq 24(%rdx), %r10 +; SSE-NEXT: movq 32(%rsi), %r11 +; SSE-NEXT: adcq 32(%rdx), %r11 +; SSE-NEXT: movq 40(%rsi), %rbx +; SSE-NEXT: adcq 40(%rdx), %rbx +; SSE-NEXT: movq 48(%rsi), %rsi +; SSE-NEXT: adcq 48(%rdx), %rsi +; SSE-NEXT: adcq 56(%rdx), %rcx +; SSE-NEXT: movq %rdi, (%rax) +; SSE-NEXT: movq %r8, 8(%rax) +; SSE-NEXT: movq %r9, 16(%rax) +; SSE-NEXT: movq %r10, 24(%rax) +; SSE-NEXT: movq %r11, 32(%rax) +; SSE-NEXT: movq %rbx, 40(%rax) +; SSE-NEXT: movq %rsi, 48(%rax) +; SSE-NEXT: movq %rcx, 56(%rax) +; SSE-NEXT: popq %rbx +; SSE-NEXT: retq +; +; AVX2-LABEL: test_add_i512_mem_mem: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq %rdi, %rax +; AVX2-NEXT: movq (%rsi), %rcx +; AVX2-NEXT: addq (%rdx), %rcx +; AVX2-NEXT: movq 8(%rsi), %rdi +; AVX2-NEXT: adcq 8(%rdx), %rdi +; AVX2-NEXT: movq 16(%rsi), %r8 +; AVX2-NEXT: adcq 16(%rdx), %r8 +; AVX2-NEXT: movq 24(%rsi), %r9 +; AVX2-NEXT: adcq 24(%rdx), %r9 +; AVX2-NEXT: movq 32(%rsi), %r10 +; AVX2-NEXT: adcq 32(%rdx), %r10 +; AVX2-NEXT: movq 40(%rsi), %r11 +; AVX2-NEXT: adcq 40(%rdx), %r11 +; AVX2-NEXT: movq 48(%rsi), %rbx +; AVX2-NEXT: adcq 48(%rdx), %rbx +; AVX2-NEXT: movq 56(%rsi), %rsi +; AVX2-NEXT: adcq 56(%rdx), %rsi +; AVX2-NEXT: movq %rcx, (%rax) +; AVX2-NEXT: movq %rdi, 8(%rax) +; AVX2-NEXT: movq %r8, 16(%rax) +; AVX2-NEXT: movq %r9, 24(%rax) +; AVX2-NEXT: movq %r10, 32(%rax) +; AVX2-NEXT: movq %r11, 40(%rax) +; AVX2-NEXT: movq %rbx, 48(%rax) +; AVX2-NEXT: movq %rsi, 56(%rax) +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: retq +; +; AVX512F-LABEL: test_add_i512_mem_mem: +; AVX512F: # %bb.0: +; AVX512F-NEXT: movq %rdi, %rax +; AVX512F-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512F-NEXT: vpaddq (%rdx), %zmm0, %zmm1 +; AVX512F-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %ecx +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm0 = -1 +; AVX512F-NEXT: vpcmpeqq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %edx +; AVX512F-NEXT: movzbl %dl, %edx +; AVX512F-NEXT: leal (%rdx,%rcx,2), %ecx +; AVX512F-NEXT: xorl %edx, %ecx +; AVX512F-NEXT: kmovw %ecx, %k1 +; AVX512F-NEXT: vpsubq %zmm0, %zmm1, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_add_i512_mem_mem: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512VL-NEXT: movq %rdi, %rax +; AVX512VL-NEXT: vpaddq (%rdx), %zmm0, %zmm1 +; AVX512VL-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovd %k0, %ecx +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm0 = -1 +; AVX512VL-NEXT: vpcmpeqq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovb %k0, %edx +; AVX512VL-NEXT: leal (%rdx,%rcx,2), %ecx +; AVX512VL-NEXT: xorl %edx, %ecx +; AVX512VL-NEXT: kmovd %ecx, %k1 +; AVX512VL-NEXT: vpsubq %zmm0, %zmm1, %zmm1 {%k1} +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq + %a0 = load i512, ptr %p0 + %a1 = load i512, ptr %p1 + %r = add i512 %a0, %a1 + ret i512 %r +} + define void @test_inc_i512_rmw(ptr %p0) nounwind { ; CHECK-LABEL: test_inc_i512_rmw: ; CHECK: # %bb.0: @@ -429,19 +540,97 @@ define void @test_inc_i512_rmw(ptr %p0) nounwind { ; CHECK-NEXT: adcq $0, 56(%rdi) ; CHECK-NEXT: retq ; -; AVX512-LABEL: test_inc_i512_rmw: -; AVX512: # %bb.0: -; AVX512-NEXT: addq $1, (%rdi) -; AVX512-NEXT: adcq $0, 8(%rdi) -; AVX512-NEXT: adcq $0, 16(%rdi) -; AVX512-NEXT: adcq $0, 24(%rdi) -; AVX512-NEXT: adcq $0, 32(%rdi) -; AVX512-NEXT: adcq $0, 40(%rdi) -; AVX512-NEXT: adcq $0, 48(%rdi) -; AVX512-NEXT: adcq $0, 56(%rdi) -; AVX512-NEXT: retq +; AVX512F-LABEL: test_inc_i512_rmw: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0 +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm1 = -1 +; AVX512F-NEXT: vpsubq %zmm1, %zmm0, %zmm1 +; AVX512F-NEXT: vpcmpnleuq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: vptestnmq %zmm1, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %ecx +; AVX512F-NEXT: movzbl %cl, %ecx +; AVX512F-NEXT: leal (%rcx,%rax,2), %eax +; AVX512F-NEXT: xorl %ecx, %eax +; AVX512F-NEXT: kmovw %eax, %k0 +; AVX512F-NEXT: knotw %k0, %k1 +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) {%k1} +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_inc_i512_rmw: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqu64 (%rdi), %zmm0 +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm1 = -1 +; AVX512VL-NEXT: vpsubq %zmm1, %zmm0, %zmm1 +; AVX512VL-NEXT: vpcmpnleuq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovd %k0, %eax +; AVX512VL-NEXT: vptestnmq %zmm1, %zmm1, %k0 +; AVX512VL-NEXT: kmovb %k0, %ecx +; AVX512VL-NEXT: leal (%rcx,%rax,2), %eax +; AVX512VL-NEXT: xorl %ecx, %eax +; AVX512VL-NEXT: kmovd %eax, %k0 +; AVX512VL-NEXT: knotb %k0, %k1 +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rdi) {%k1} +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq %a0 = load i512, ptr %p0 %r = add i512 %a0, 1 store i512 %r, ptr %p0 ret void } + +define void @test_add_i512_rmw(ptr %p0) nounwind { +; CHECK-LABEL: test_add_i512_rmw: +; CHECK: # %bb.0: +; CHECK-NEXT: addq $9, (%rdi) +; CHECK-NEXT: adcq $0, 8(%rdi) +; CHECK-NEXT: adcq $0, 16(%rdi) +; CHECK-NEXT: adcq $0, 24(%rdi) +; CHECK-NEXT: adcq $0, 32(%rdi) +; CHECK-NEXT: adcq $0, 40(%rdi) +; CHECK-NEXT: adcq $0, 48(%rdi) +; CHECK-NEXT: adcq $0, 56(%rdi) +; CHECK-NEXT: retq +; +; AVX512F-LABEL: test_add_i512_rmw: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0 +; AVX512F-NEXT: vmovd {{.*#+}} xmm1 = [9,0,0,0] +; AVX512F-NEXT: vpaddq %zmm1, %zmm0, %zmm1 +; AVX512F-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm2 = -1 +; AVX512F-NEXT: vpcmpeqq %zmm2, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %ecx +; AVX512F-NEXT: movzbl %cl, %ecx +; AVX512F-NEXT: leal (%rcx,%rax,2), %eax +; AVX512F-NEXT: xorl %ecx, %eax +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_add_i512_rmw: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqu64 (%rdi), %zmm0 +; AVX512VL-NEXT: vmovd {{.*#+}} xmm1 = [9,0,0,0] +; AVX512VL-NEXT: vpaddq %zmm1, %zmm0, %zmm1 +; AVX512VL-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovd %k0, %eax +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm2 = -1 +; AVX512VL-NEXT: vpcmpeqq %zmm2, %zmm1, %k0 +; AVX512VL-NEXT: kmovb %k0, %ecx +; AVX512VL-NEXT: leal (%rcx,%rax,2), %eax +; AVX512VL-NEXT: xorl %ecx, %eax +; AVX512VL-NEXT: kmovd %eax, %k1 +; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 {%k1} +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq + %a0 = load i512, ptr %p0 + %r = add i512 %a0, 9 + store i512 %r, ptr %p0 + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX512: {{.*}} diff --git a/llvm/test/CodeGen/X86/apx/foldimmediate.mir b/llvm/test/CodeGen/X86/apx/foldimmediate.mir index 310fc64841f7a..ffe544d2a1a00 100644 --- a/llvm/test/CodeGen/X86/apx/foldimmediate.mir +++ b/llvm/test/CodeGen/X86/apx/foldimmediate.mir @@ -40,7 +40,7 @@ body: | ; CHECK-NEXT: NOOP implicit $eflags ; CHECK-NEXT: CCMP32ri [[COPY]], 81, 2, 10, implicit-def $eflags, implicit $eflags ; CHECK-NEXT: NOOP implicit $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32ri]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32ri]], %subreg.sub_32bit ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi ; CHECK-NEXT: CTEST64ri32 [[COPY1]], 81, 2, 10, implicit-def $eflags, implicit $eflags ; CHECK-NEXT: NOOP implicit $eflags @@ -57,7 +57,7 @@ body: | CCMP32rr %1, %0, 2, 10, implicit-def $eflags, implicit $eflags NOOP implicit $eflags - %7 = SUBREG_TO_REG 0, killed %0:gr32, %subreg.sub_32bit + %7 = SUBREG_TO_REG killed %0:gr32, %subreg.sub_32bit %8 = COPY $rsi CTEST64rr %8, %7, 2, 10, implicit-def $eflags, implicit $eflags diff --git a/llvm/test/CodeGen/X86/avx-minmax.ll b/llvm/test/CodeGen/X86/avx-minmax.ll index 8e4b6c6af4cb1..27864a9eefa8e 100644 --- a/llvm/test/CodeGen/X86/avx-minmax.ll +++ b/llvm/test/CodeGen/X86/avx-minmax.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx -enable-no-nans-fp-math | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) { ; CHECK-LABEL: maxpd: ; CHECK: # %bb.0: ; CHECK-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq - %max_is_x = fcmp oge <2 x double> %x, %y + %max_is_x = fcmp nnan oge <2 x double> %x, %y %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y ret <2 x double> %max } @@ -16,7 +16,7 @@ define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vminpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq - %min_is_x = fcmp ole <2 x double> %x, %y + %min_is_x = fcmp nnan ole <2 x double> %x, %y %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y ret <2 x double> %min } @@ -26,7 +26,7 @@ define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vmaxps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq - %max_is_x = fcmp oge <4 x float> %x, %y + %max_is_x = fcmp nnan oge <4 x float> %x, %y %max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y ret <4 x float> %max } @@ -36,7 +36,7 @@ define <4 x float> @minps(<4 x float> %x, <4 x float> %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vminps %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq - %min_is_x = fcmp ole <4 x float> %x, %y + %min_is_x = fcmp nnan ole <4 x float> %x, %y %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y ret <4 x float> %min } @@ -46,7 +46,7 @@ define <4 x double> @vmaxpd(<4 x double> %x, <4 x double> %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retq - %max_is_x = fcmp oge <4 x double> %x, %y + %max_is_x = fcmp nnan oge <4 x double> %x, %y %max = select <4 x i1> %max_is_x, <4 x double> %x, <4 x double> %y ret <4 x double> %max } @@ -56,7 +56,7 @@ define <4 x double> @vminpd(<4 x double> %x, <4 x double> %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vminpd %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retq - %min_is_x = fcmp ole <4 x double> %x, %y + %min_is_x = fcmp nnan ole <4 x double> %x, %y %min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y ret <4 x double> %min } @@ -66,7 +66,7 @@ define <8 x float> @vmaxps(<8 x float> %x, <8 x float> %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vmaxps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retq - %max_is_x = fcmp oge <8 x float> %x, %y + %max_is_x = fcmp nnan oge <8 x float> %x, %y %max = select <8 x i1> %max_is_x, <8 x float> %x, <8 x float> %y ret <8 x float> %max } @@ -76,7 +76,7 @@ define <8 x float> @vminps(<8 x float> %x, <8 x float> %y) { ; CHECK: # %bb.0: ; CHECK-NEXT: vminps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: retq - %min_is_x = fcmp ole <8 x float> %x, %y + %min_is_x = fcmp nnan ole <8 x float> %x, %y %min = select <8 x i1> %min_is_x, <8 x float> %x, <8 x float> %y ret <8 x float> %min } diff --git a/llvm/test/CodeGen/X86/avx10_2-cmp.ll b/llvm/test/CodeGen/X86/avx10_2-cmp.ll index 566ce533683f7..8117345d9de04 100644 --- a/llvm/test/CodeGen/X86/avx10_2-cmp.ll +++ b/llvm/test/CodeGen/X86/avx10_2-cmp.ll @@ -281,14 +281,14 @@ define i1 @constrained_fcmp() { ; X64-LABEL: constrained_fcmp: ; X64: # %bb.0: # %entry ; X64-NEXT: vxorpd %xmm0, %xmm0, %xmm0 -; X64-NEXT: vucomxsd %xmm0, %xmm0 +; X64-NEXT: vcomisd %xmm0, %xmm0 ; X64-NEXT: setne %al ; X64-NEXT: retq ; ; X86-LABEL: constrained_fcmp: ; X86: # %bb.0: # %entry ; X86-NEXT: vxorpd %xmm0, %xmm0, %xmm0 -; X86-NEXT: vucomxsd %xmm0, %xmm0 +; X86-NEXT: vcomisd %xmm0, %xmm0 ; X86-NEXT: setne %al ; X86-NEXT: retl entry: diff --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll index 97ca0d88b7d4d..decab7b485c4d 100644 --- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll +++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll @@ -239,15 +239,12 @@ define i16 @PR90356(<16 x i1> %a) { ; CHECK-LABEL: PR90356: ; CHECK: # %bb.0: ; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0 -; CHECK-NEXT: vpmovb2m %xmm0, %k1 -; CHECK-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 -; CHECK-NEXT: movb $63, %al +; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; CHECK-NEXT: movw $4095, %ax # imm = 0xFFF ; CHECK-NEXT: kmovd %eax, %k1 -; CHECK-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} -; CHECK-NEXT: vptestmd %zmm0, %zmm0, %k0 +; CHECK-NEXT: vpcmpgtb %xmm0, %xmm1, %k0 {%k1} ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax -; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq %1 = shufflevector <16 x i1> %a, <16 x i1> zeroinitializer, <16 x i32> %2 = bitcast <16 x i1> %1 to i16 diff --git a/llvm/test/CodeGen/X86/bitcast-vector-bool.ll b/llvm/test/CodeGen/X86/bitcast-vector-bool.ll index fae1ff90dd8d5..7f899e372caed 100644 --- a/llvm/test/CodeGen/X86/bitcast-vector-bool.ll +++ b/llvm/test/CodeGen/X86/bitcast-vector-bool.ll @@ -1193,162 +1193,60 @@ define i64 @bitcast_v128i8_to_v2i64(<128 x i8> %a0) nounwind { define i1 @trunc_v128i8_cmp(<128 x i8> %a0) nounwind { ; SSE2-SSSE3-LABEL: trunc_v128i8_cmp: ; SSE2-SSSE3: # %bb.0: +; SSE2-SSSE3-NEXT: pand %xmm7, %xmm3 +; SSE2-SSSE3-NEXT: pand %xmm5, %xmm1 +; SSE2-SSSE3-NEXT: pand %xmm3, %xmm1 +; SSE2-SSSE3-NEXT: pand %xmm6, %xmm2 +; SSE2-SSSE3-NEXT: pand %xmm4, %xmm0 +; SSE2-SSSE3-NEXT: pand %xmm2, %xmm0 +; SSE2-SSSE3-NEXT: pand %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: psllw $7, %xmm0 ; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: psllw $7, %xmm1 -; SSE2-SSSE3-NEXT: pmovmskb %xmm1, %ecx -; SSE2-SSSE3-NEXT: shll $16, %ecx -; SSE2-SSSE3-NEXT: orl %eax, %ecx -; SSE2-SSSE3-NEXT: psllw $7, %xmm2 -; SSE2-SSSE3-NEXT: pmovmskb %xmm2, %edx -; SSE2-SSSE3-NEXT: psllw $7, %xmm3 -; SSE2-SSSE3-NEXT: pmovmskb %xmm3, %eax -; SSE2-SSSE3-NEXT: shll $16, %eax -; SSE2-SSSE3-NEXT: orl %edx, %eax -; SSE2-SSSE3-NEXT: shlq $32, %rax -; SSE2-SSSE3-NEXT: orq %rcx, %rax -; SSE2-SSSE3-NEXT: psllw $7, %xmm4 -; SSE2-SSSE3-NEXT: pmovmskb %xmm4, %ecx -; SSE2-SSSE3-NEXT: psllw $7, %xmm5 -; SSE2-SSSE3-NEXT: pmovmskb %xmm5, %edx -; SSE2-SSSE3-NEXT: shll $16, %edx -; SSE2-SSSE3-NEXT: orl %ecx, %edx -; SSE2-SSSE3-NEXT: psllw $7, %xmm6 -; SSE2-SSSE3-NEXT: pmovmskb %xmm6, %ecx -; SSE2-SSSE3-NEXT: psllw $7, %xmm7 -; SSE2-SSSE3-NEXT: pmovmskb %xmm7, %esi -; SSE2-SSSE3-NEXT: shll $16, %esi -; SSE2-SSSE3-NEXT: orl %ecx, %esi -; SSE2-SSSE3-NEXT: shlq $32, %rsi -; SSE2-SSSE3-NEXT: orq %rdx, %rsi -; SSE2-SSSE3-NEXT: movq %rsi, %xmm0 -; SSE2-SSSE3-NEXT: movq %rax, %xmm1 -; SSE2-SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] -; SSE2-SSSE3-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE2-SSSE3-NEXT: pcmpeqb %xmm1, %xmm0 -; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: cmpl $65535, %eax # imm = 0xFFFF +; SSE2-SSSE3-NEXT: xorl $65535, %eax # imm = 0xFFFF ; SSE2-SSSE3-NEXT: setne %al ; SSE2-SSSE3-NEXT: retq ; ; SSE41-LABEL: trunc_v128i8_cmp: ; SSE41: # %bb.0: -; SSE41-NEXT: psllw $7, %xmm0 -; SSE41-NEXT: pmovmskb %xmm0, %eax -; SSE41-NEXT: psllw $7, %xmm1 -; SSE41-NEXT: pmovmskb %xmm1, %ecx -; SSE41-NEXT: shll $16, %ecx -; SSE41-NEXT: orl %eax, %ecx -; SSE41-NEXT: psllw $7, %xmm2 -; SSE41-NEXT: pmovmskb %xmm2, %edx -; SSE41-NEXT: psllw $7, %xmm3 -; SSE41-NEXT: pmovmskb %xmm3, %eax -; SSE41-NEXT: shll $16, %eax -; SSE41-NEXT: orl %edx, %eax -; SSE41-NEXT: shlq $32, %rax -; SSE41-NEXT: orq %rcx, %rax -; SSE41-NEXT: psllw $7, %xmm4 -; SSE41-NEXT: pmovmskb %xmm4, %ecx -; SSE41-NEXT: psllw $7, %xmm5 -; SSE41-NEXT: pmovmskb %xmm5, %edx -; SSE41-NEXT: shll $16, %edx -; SSE41-NEXT: orl %ecx, %edx -; SSE41-NEXT: psllw $7, %xmm6 -; SSE41-NEXT: pmovmskb %xmm6, %ecx -; SSE41-NEXT: psllw $7, %xmm7 -; SSE41-NEXT: pmovmskb %xmm7, %esi -; SSE41-NEXT: shll $16, %esi -; SSE41-NEXT: orl %ecx, %esi -; SSE41-NEXT: shlq $32, %rsi -; SSE41-NEXT: orq %rdx, %rsi -; SSE41-NEXT: movq %rsi, %xmm0 -; SSE41-NEXT: movq %rax, %xmm1 -; SSE41-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] -; SSE41-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE41-NEXT: ptest %xmm0, %xmm1 +; SSE41-NEXT: pand %xmm7, %xmm3 +; SSE41-NEXT: pand %xmm5, %xmm1 +; SSE41-NEXT: pand %xmm3, %xmm1 +; SSE41-NEXT: pand %xmm6, %xmm2 +; SSE41-NEXT: pand %xmm4, %xmm0 +; SSE41-NEXT: pand %xmm2, %xmm0 +; SSE41-NEXT: pand %xmm1, %xmm0 +; SSE41-NEXT: ptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; SSE41-NEXT: setae %al ; SSE41-NEXT: retq ; ; AVX1-LABEL: trunc_v128i8_cmp: ; AVX1: # %bb.0: -; AVX1-NEXT: vpsllw $7, %xmm0, %xmm4 -; AVX1-NEXT: vpmovmskb %xmm4, %eax -; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 -; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0 -; AVX1-NEXT: vpmovmskb %xmm0, %ecx -; AVX1-NEXT: shll $16, %ecx -; AVX1-NEXT: orl %eax, %ecx -; AVX1-NEXT: vpsllw $7, %xmm1, %xmm0 -; AVX1-NEXT: vpmovmskb %xmm0, %edx -; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 -; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0 -; AVX1-NEXT: vpmovmskb %xmm0, %eax -; AVX1-NEXT: shll $16, %eax -; AVX1-NEXT: orl %edx, %eax -; AVX1-NEXT: shlq $32, %rax -; AVX1-NEXT: orq %rcx, %rax -; AVX1-NEXT: vpsllw $7, %xmm2, %xmm0 -; AVX1-NEXT: vpmovmskb %xmm0, %ecx -; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm0 -; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0 -; AVX1-NEXT: vpmovmskb %xmm0, %edx -; AVX1-NEXT: shll $16, %edx -; AVX1-NEXT: orl %ecx, %edx -; AVX1-NEXT: vpsllw $7, %xmm3, %xmm0 -; AVX1-NEXT: vpmovmskb %xmm0, %ecx -; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm0 -; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0 -; AVX1-NEXT: vpmovmskb %xmm0, %esi -; AVX1-NEXT: shll $16, %esi -; AVX1-NEXT: orl %ecx, %esi -; AVX1-NEXT: shlq $32, %rsi -; AVX1-NEXT: orq %rdx, %rsi -; AVX1-NEXT: vmovq %rsi, %xmm0 -; AVX1-NEXT: vmovq %rax, %xmm1 -; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] -; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; AVX1-NEXT: vptest %xmm1, %xmm0 +; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm1 +; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 +; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 +; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0 ; AVX1-NEXT: setae %al ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc_v128i8_cmp: ; AVX2: # %bb.0: -; AVX2-NEXT: vpsllw $7, %ymm1, %ymm1 -; AVX2-NEXT: vpmovmskb %ymm1, %eax -; AVX2-NEXT: shlq $32, %rax -; AVX2-NEXT: vpsllw $7, %ymm0, %ymm0 -; AVX2-NEXT: vpmovmskb %ymm0, %ecx -; AVX2-NEXT: orq %rax, %rcx -; AVX2-NEXT: vpsllw $7, %ymm3, %ymm0 -; AVX2-NEXT: vpmovmskb %ymm0, %eax -; AVX2-NEXT: shlq $32, %rax -; AVX2-NEXT: vpsllw $7, %ymm2, %ymm0 -; AVX2-NEXT: vpmovmskb %ymm0, %edx -; AVX2-NEXT: orq %rax, %rdx -; AVX2-NEXT: vmovq %rdx, %xmm0 -; AVX2-NEXT: vmovq %rcx, %xmm1 -; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] -; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vptest %xmm1, %xmm0 +; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [72340172838076673,72340172838076673,72340172838076673,72340172838076673] +; AVX2-NEXT: vptest %ymm1, %ymm0 ; AVX2-NEXT: setae %al ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; ; AVX512-LABEL: trunc_v128i8_cmp: ; AVX512: # %bb.0: -; AVX512-NEXT: vpsllw $7, %zmm0, %zmm0 -; AVX512-NEXT: vpmovb2m %zmm0, %k0 -; AVX512-NEXT: kmovq %k0, %rax -; AVX512-NEXT: vpsllw $7, %zmm1, %zmm0 -; AVX512-NEXT: vpmovb2m %zmm0, %k0 -; AVX512-NEXT: kmovq %k0, %rcx -; AVX512-NEXT: vmovq %rcx, %xmm0 -; AVX512-NEXT: vmovq %rax, %xmm1 -; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] -; AVX512-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; AVX512-NEXT: vptest %xmm1, %xmm0 -; AVX512-NEXT: setae %al +; AVX512-NEXT: vpbroadcastb {{.*#+}} zmm2 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1] +; AVX512-NEXT: vpternlogq {{.*#+}} zmm0 = zmm0 & zmm2 & zmm1 +; AVX512-NEXT: vpcmpneqd %zmm2, %zmm0, %k0 +; AVX512-NEXT: kortestw %k0, %k0 +; AVX512-NEXT: setne %al ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %1 = trunc <128 x i8> %a0 to <128 x i1> diff --git a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll index b0ca0069a526b..821b7b8e4144f 100644 --- a/llvm/test/CodeGen/X86/bypass-slow-division-64.ll +++ b/llvm/test/CodeGen/X86/bypass-slow-division-64.ll @@ -24,6 +24,7 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ ; Additional tests for 64-bit divide bypass diff --git a/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir b/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir index eec92f059082f..a56237e160c31 100644 --- a/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir +++ b/llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir @@ -35,7 +35,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY killed $edi ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY killed [[COPY]].sub_8bit ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY killed [[SUBREG_TO_REG]] ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1.loop (inlineasm-br-indirect-target): @@ -65,7 +65,7 @@ body: | %2:gr32 = COPY killed $edi %3:gr8 = COPY killed %2.sub_8bit %5:gr32 = MOV32r0 implicit-def dead $eflags - %4:gr64 = SUBREG_TO_REG 0, killed %5, %subreg.sub_32bit + %4:gr64 = SUBREG_TO_REG killed %5, %subreg.sub_32bit bb.1.loop (inlineasm-br-indirect-target): successors: %bb.2(0x40000000), %bb.1(0x40000000) diff --git a/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll b/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll index 433bd254317e6..77f4138788197 100644 --- a/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll +++ b/llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll @@ -341,7 +341,7 @@ define i64 @condition_code() { ; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.2 ; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOVZX32rr8_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOVZX32rr8_]], %subreg.sub_32bit ; CHECK-NEXT: JMP_1 %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1.b: @@ -351,7 +351,7 @@ define i64 @condition_code() { ; CHECK-NEXT: bb.2.c (inlineasm-br-indirect-target): ; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags ; CHECK-NEXT: [[MOVZX32rr8_1:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr1]] - ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOVZX32rr8_1]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOVZX32rr8_1]], %subreg.sub_32bit ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG1]] ; CHECK-NEXT: RET 0, $rax %a = callbr i64 asm "", "={@ccz},!i"() diff --git a/llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir b/llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir index 4f80f4f87dd0d..43b394721b5c9 100644 --- a/llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir +++ b/llvm/test/CodeGen/X86/cfi-epilogue-with-return.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -o - %s -mtriple=x86_64-- -run-pass=prologepilog 2>&1 | FileCheck %s --- | define i64 @_Z3foob(i1 zeroext %cond) #0 { @@ -8,11 +9,6 @@ --- # If the epilogue bb.1 is a return block, no .cfi_restore is # needed in it. -# CHECK: bb.1: -# CHECK-NOT: CFI_INSTRUCTION restore -# CHECK: RET 0 -# CHECK: bb.2: -# CHECK: RET 0 name: _Z3foob alignment: 16 tracksRegLiveness: true @@ -27,13 +23,60 @@ frameInfo: - point: '%bb.1' machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: _Z3foob + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $edi, $rbx, $r12, $r13, $r14, $r15 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: TEST8rr renamable $dil, renamable $dil, implicit-def $eflags, implicit killed $edi + ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags + ; CHECK-NEXT: JMP_1 %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: liveins: $r15, $r14, $r13, $r12, $rbx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $rbp, -16 + ; CHECK-NEXT: $rbp = frame-setup MOV64rr $rsp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $rbp + ; CHECK-NEXT: frame-setup PUSH64r killed $r15, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup PUSH64r killed $r14, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup PUSH64r killed $r13, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup PUSH64r killed $r12, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: CFI_INSTRUCTION offset $rbx, -56 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r12, -48 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r13, -40 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r14, -32 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r15, -24 + ; CHECK-NEXT: renamable $rbx = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r14 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r15 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r12 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r13 = IMPLICIT_DEF + ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax + ; CHECK-NEXT: $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r12 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $rsp, 8 + ; CHECK-NEXT: RET 0, killed $rax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $rbx, $r12, $r13, $r14, $r15 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax + ; CHECK-NEXT: RET 0, killed $rax bb.0: liveins: $edi - + TEST8rr renamable $dil, renamable $dil, implicit-def $eflags, implicit killed $edi JCC_1 %bb.2, 4, implicit killed $eflags JMP_1 %bb.1 - + bb.1: renamable $rbx = IMPLICIT_DEF renamable $r14 = IMPLICIT_DEF @@ -42,7 +85,7 @@ body: | renamable $r13 = IMPLICIT_DEF dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax RET 0, killed $rax - + bb.2: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax RET 0, killed $rax diff --git a/llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir b/llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir index 38c081c94ab91..243d800200c29 100644 --- a/llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir +++ b/llvm/test/CodeGen/X86/cfi-epilogue-without-return.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -o - %s -mtriple=x86_64-- -run-pass=prologepilog 2>&1 | FileCheck %s --- | declare dso_local void @_Z3goov() @@ -10,16 +11,6 @@ # If the epilogue bb.1.if.then is not a return block, .cfi_restore is # needed in it, otherwise bb.2.return will see different outgoing CFI # information from its predecessors. -# CHECK: bb.1: -# CHECK: CFI_INSTRUCTION restore $rbx -# CHECK-NEXT: CFI_INSTRUCTION restore $r12 -# CHECK-NEXT: CFI_INSTRUCTION restore $r13 -# CHECK-NEXT: CFI_INSTRUCTION restore $r14 -# CHECK-NEXT: CFI_INSTRUCTION restore $r15 -# CHECK-NEXT: CFI_INSTRUCTION restore $rbp -# CHECK-NOT: RET 0 -# CHECK: bb.2: -# CHECK: RET 0 name: _Z3foob alignment: 16 tracksRegLiveness: true @@ -34,20 +25,72 @@ frameInfo: - point: '%bb.1' machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: _Z3foob + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $edi, $rbx, $r12, $r13, $r14, $r15 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: TEST8rr renamable $dil, renamable $dil, implicit-def $eflags, implicit killed $edi + ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags + ; CHECK-NEXT: JMP_1 %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: liveins: $r15, $r14, $r13, $r12, $rbx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $rbp, -16 + ; CHECK-NEXT: $rbp = frame-setup MOV64rr $rsp + ; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $rbp + ; CHECK-NEXT: frame-setup PUSH64r killed $r15, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup PUSH64r killed $r14, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup PUSH64r killed $r13, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup PUSH64r killed $r12, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: CFI_INSTRUCTION offset $rbx, -56 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r12, -48 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r13, -40 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r14, -32 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r15, -24 + ; CHECK-NEXT: renamable $rbx = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r14 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r15 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r12 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r13 = IMPLICIT_DEF + ; CHECK-NEXT: $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r12 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r13 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r15 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $rsp, 8 + ; CHECK-NEXT: CFI_INSTRUCTION restore $rbx + ; CHECK-NEXT: CFI_INSTRUCTION restore $r12 + ; CHECK-NEXT: CFI_INSTRUCTION restore $r13 + ; CHECK-NEXT: CFI_INSTRUCTION restore $r14 + ; CHECK-NEXT: CFI_INSTRUCTION restore $r15 + ; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $rbp + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $rbx, $r12, $r13, $r14, $r15 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax + ; CHECK-NEXT: RET 0, killed $rax bb.0: liveins: $edi - + TEST8rr renamable $dil, renamable $dil, implicit-def $eflags, implicit killed $edi JCC_1 %bb.2, 4, implicit killed $eflags JMP_1 %bb.1 - + bb.1: renamable $rbx = IMPLICIT_DEF renamable $r14 = IMPLICIT_DEF renamable $r15 = IMPLICIT_DEF renamable $r12 = IMPLICIT_DEF renamable $r13 = IMPLICIT_DEF - + bb.2: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax RET 0, killed $rax diff --git a/llvm/test/CodeGen/X86/cfi-inserter-callee-save-register-2.mir b/llvm/test/CodeGen/X86/cfi-inserter-callee-save-register-2.mir index e85126d649be4..a08a3166a1285 100644 --- a/llvm/test/CodeGen/X86/cfi-inserter-callee-save-register-2.mir +++ b/llvm/test/CodeGen/X86/cfi-inserter-callee-save-register-2.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ # RUN: -run-pass=cfi-instr-inserter 2>&1 | FileCheck %s # Test that CFI inserter inserts .cfi_offset/.cfi_register/.cfi_rel_offset @@ -8,11 +9,6 @@ } ... --- -# CHECK: bb.3: -# CHECK: CFI_INSTRUCTION offset $rbp, -16 -# CHECK-NEXT: CFI_INSTRUCTION offset $r12, -24 -# CHECK-NEXT: CFI_INSTRUCTION register $r13, $rcx -# CHECK-NEXT: CFI_INSTRUCTION offset $r14, -40 name: foo alignment: 16 tracksRegLiveness: true @@ -33,10 +29,78 @@ fixedStack: - { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8 } machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: foo + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $edi, $r12, $r13, $r14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: CFI_INSTRUCTION offset $rbp, -16 + ; CHECK-NEXT: $rbp = frame-setup MOV64rr $rsp + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa_register $rbp + ; CHECK-NEXT: frame-setup PUSH64r killed $r12, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $rcx = frame-setup COPY $r13 + ; CHECK-NEXT: frame-setup PUSH64r killed $r14, implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: CFI_INSTRUCTION offset $r12, -24 + ; CHECK-NEXT: CFI_INSTRUCTION register $r13, $rcx + ; CHECK-NEXT: CFI_INSTRUCTION rel_offset $r14, -24 + ; CHECK-NEXT: TEST8rr renamable $dil, renamable $dil, implicit-def $eflags, implicit killed $edi + ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags + ; CHECK-NEXT: JMP_1 %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $r12 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r13 = IMPLICIT_DEF + ; CHECK-NEXT: renamable $r14 = IMPLICIT_DEF + ; CHECK-NEXT: JMP_1 %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: liveins: $rcx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax + ; CHECK-NEXT: $r12 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r13 = frame-destroy COPY $rcx + ; CHECK-NEXT: $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: CFI_INSTRUCTION restore $rbp + ; CHECK-NEXT: CFI_INSTRUCTION restore $r12 + ; CHECK-NEXT: CFI_INSTRUCTION restore $r13 + ; CHECK-NEXT: CFI_INSTRUCTION restore $r14 + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa $rsp, 8 + ; CHECK-NEXT: RET 0, killed $rax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa $rbp, 16 + ; CHECK-NEXT: CFI_INSTRUCTION offset $rbp, -16 + ; CHECK-NEXT: CFI_INSTRUCTION offset $r12, -24 + ; CHECK-NEXT: CFI_INSTRUCTION register $r13, $rcx + ; CHECK-NEXT: CFI_INSTRUCTION offset $r14, -40 + ; CHECK-NEXT: renamable $rdi = IMPLICIT_DEF + ; CHECK-NEXT: renamable $rsi = IMPLICIT_DEF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: liveins: $rcx + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax + ; CHECK-NEXT: $r12 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $r13 = frame-destroy COPY $rcx + ; CHECK-NEXT: $r14 = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp + ; CHECK-NEXT: CFI_INSTRUCTION restore $rbp + ; CHECK-NEXT: CFI_INSTRUCTION restore $r12 + ; CHECK-NEXT: CFI_INSTRUCTION restore $r13 + ; CHECK-NEXT: CFI_INSTRUCTION restore $r14 + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa $rsp, 8 + ; CHECK-NEXT: RET 0, killed $rax bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $edi, $r12, $r13, $r14 - + frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp CFI_INSTRUCTION def_cfa_offset 16 CFI_INSTRUCTION offset $rbp, -16 @@ -51,15 +115,15 @@ body: | TEST8rr renamable $dil, renamable $dil, implicit-def $eflags, implicit killed $edi JCC_1 %bb.2, 4, implicit killed $eflags JMP_1 %bb.1 - + bb.1: successors: %bb.3(0x80000000) - + renamable $r12 = IMPLICIT_DEF renamable $r13 = IMPLICIT_DEF renamable $r14 = IMPLICIT_DEF JMP_1 %bb.3 - + bb.2: liveins: $rcx dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax @@ -73,13 +137,13 @@ body: | CFI_INSTRUCTION restore $r14 CFI_INSTRUCTION def_cfa $rsp, 8 RET 0, killed $rax - + bb.3: successors: %bb.4(0x80000000) - + renamable $rdi = IMPLICIT_DEF renamable $rsi = IMPLICIT_DEF - + bb.4: liveins: $rcx dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $rax diff --git a/llvm/test/CodeGen/X86/cfi-inserter-callee-save-register.mir b/llvm/test/CodeGen/X86/cfi-inserter-callee-save-register.mir index b17c9a67abb18..abcb0743aa21b 100644 --- a/llvm/test/CodeGen/X86/cfi-inserter-callee-save-register.mir +++ b/llvm/test/CodeGen/X86/cfi-inserter-callee-save-register.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ # RUN: -run-pass=cfi-instr-inserter 2>&1 | FileCheck %s # Test that CFI inserter inserts .cfi_restore properly for @@ -8,11 +9,32 @@ } ... --- -# CHECK: bb.3: -# CHECK: CFI_INSTRUCTION restore $rbx -# CHECK-NEXT: CFI_INSTRUCTION restore $rbp name: foo body: | + ; CHECK-LABEL: name: foo + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: TEST8rr renamable $dil, renamable $dil, implicit-def $eflags, implicit killed $edi + ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: JMP_1 %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NEXT: CFI_INSTRUCTION offset $rbp, -16 + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa_register $rbp + ; CHECK-NEXT: CFI_INSTRUCTION offset $rbx, -24 + ; CHECK-NEXT: CFI_INSTRUCTION def_cfa $rsp, 8 + ; CHECK-NEXT: RET 0, $rax + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: CFI_INSTRUCTION restore $rbx + ; CHECK-NEXT: CFI_INSTRUCTION restore $rbp + ; CHECK-NEXT: RET 0, $rax bb.0: TEST8rr renamable $dil, renamable $dil, implicit-def $eflags, implicit killed $edi JCC_1 %bb.2, 5, implicit killed $eflags diff --git a/llvm/test/CodeGen/X86/cfi-xmm-asm.ll b/llvm/test/CodeGen/X86/cfi-xmm-asm.ll new file mode 100644 index 0000000000000..530c522a318bc --- /dev/null +++ b/llvm/test/CodeGen/X86/cfi-xmm-asm.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple x86_64-w64-windows-gnu -filetype=asm -exception-model=dwarf -o - %s | FileCheck %s + +define void @_Z1fv() { +; CHECK-LABEL: _Z1fv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: subq $40, %rsp +; CHECK-NEXT: movaps %xmm15, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; CHECK-NEXT: movaps %xmm10, (%rsp) # 16-byte Spill +; CHECK-NEXT: .cfi_def_cfa_offset 48 +; CHECK-NEXT: .cfi_offset %xmm10, -48 +; CHECK-NEXT: .cfi_offset %xmm15, -32 +; CHECK-NEXT: #APP +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: movaps (%rsp), %xmm10 # 16-byte Reload +; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm15 # 16-byte Reload +; CHECK-NEXT: addq $40, %rsp +; CHECK-NEXT: retq +entry: + tail call void asm sideeffect "", "~{xmm10},~{xmm15},~{dirflag},~{fpsr},~{flags}"() + ret void +} diff --git a/llvm/test/CodeGen/X86/cfi-xmm.ll b/llvm/test/CodeGen/X86/cfi-xmm.ll index 76c59ffdf9422..fa972d04f5cef 100644 --- a/llvm/test/CodeGen/X86/cfi-xmm.ll +++ b/llvm/test/CodeGen/X86/cfi-xmm.ll @@ -1,35 +1,23 @@ -; RUN: llc -mtriple x86_64-w64-windows-gnu -filetype=asm -exception-model=dwarf -o - %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -mtriple x86_64-w64-windows-gnu -exception-model=dwarf -stop-after=prologepilog | FileCheck %s --check-prefix=PEI define void @_Z1fv() { + ; PEI-LABEL: name: _Z1fv + ; PEI: bb.0.entry: + ; PEI-NEXT: liveins: $xmm15, $xmm10 + ; PEI-NEXT: {{ $}} + ; PEI-NEXT: $rsp = frame-setup SUB64ri32 $rsp, 40, implicit-def dead $eflags + ; PEI-NEXT: frame-setup MOVAPSmr $rsp, 1, $noreg, 16, $noreg, killed $xmm15 :: (store (s128) into %fixed-stack.1) + ; PEI-NEXT: frame-setup MOVAPSmr $rsp, 1, $noreg, 0, $noreg, killed $xmm10 :: (store (s128) into %fixed-stack.0) + ; PEI-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 48 + ; PEI-NEXT: CFI_INSTRUCTION offset $xmm10, -48 + ; PEI-NEXT: CFI_INSTRUCTION offset $xmm15, -32 + ; PEI-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $xmm10, 12 /* clobber */, implicit-def dead early-clobber $xmm15, 12 /* clobber */, implicit-def dead early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def dead early-clobber $eflags + ; PEI-NEXT: $xmm10 = MOVAPSrm $rsp, 1, $noreg, 0, $noreg :: (load (s128) from %fixed-stack.0) + ; PEI-NEXT: $xmm15 = MOVAPSrm $rsp, 1, $noreg, 16, $noreg :: (load (s128) from %fixed-stack.1) + ; PEI-NEXT: $rsp = frame-destroy ADD64ri32 $rsp, 40, implicit-def dead $eflags + ; PEI-NEXT: RET 0 entry: tail call void asm sideeffect "", "~{xmm10},~{xmm15},~{dirflag},~{fpsr},~{flags}"() ret void } - -; CHECK-LABEL: _Z1fv: -; CHECK: .cfi_startproc -; CHECK: subq $40, %rsp -; CHECK: movaps %xmm15, 16(%rsp) -; CHECK: movaps %xmm10, (%rsp) -; CHECK: .cfi_def_cfa_offset 48 -; CHECK: .cfi_offset %xmm10, -48 -; CHECK: .cfi_offset %xmm15, -32 -; CHECK: movaps (%rsp), %xmm10 -; CHECK: movaps 16(%rsp), %xmm15 -; CHECK: addq $40, %rsp -; CHECK: retq -; CHECK: .cfi_endproc - -; PEI-LABEL: name: _Z1fv -; PEI: $rsp = frame-setup SUB64ri32 $rsp, 40, implicit-def dead $eflags -; PEI-NEXT: frame-setup MOVAPSmr $rsp, 1, $noreg, 16, $noreg, killed $xmm15 :: (store (s128) into %fixed-stack.1) -; PEI-NEXT: frame-setup MOVAPSmr $rsp, 1, $noreg, 0, $noreg, killed $xmm10 :: (store (s128) into %fixed-stack.0) -; PEI-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 48 -; PEI-NEXT: {{^ +}}CFI_INSTRUCTION offset $xmm10, -48 -; PEI-NEXT: {{^ +}}CFI_INSTRUCTION offset $xmm15, -32 -; PEI-NEXT: INLINEASM {{.*}} -; PEI-NEXT: $xmm10 = MOVAPSrm $rsp, 1, $noreg, 0, $noreg :: (load (s128) from %fixed-stack.0) -; PEI-NEXT: $xmm15 = MOVAPSrm $rsp, 1, $noreg, 16, $noreg :: (load (s128) from %fixed-stack.1) -; PEI-NEXT: $rsp = frame-destroy ADD64ri32 $rsp, 40, implicit-def dead $eflags -; PEI-NEXT: RET 0 diff --git a/llvm/test/CodeGen/X86/clang-section-coff.ll b/llvm/test/CodeGen/X86/clang-section-coff.ll index 6b76bb6d222e3..1630f2d006b59 100644 --- a/llvm/test/CodeGen/X86/clang-section-coff.ll +++ b/llvm/test/CodeGen/X86/clang-section-coff.ll @@ -37,8 +37,8 @@ attributes #0 = { "bss-section"="my_bss.1" "data-section"="my_data.1" "rodata-se attributes #1 = { "data-section"="my_data.1" "rodata-section"="my_rodata.1" } attributes #2 = { "bss-section"="my_bss.2" "rodata-section"="my_rodata.1" } attributes #3 = { "bss-section"="my_bss.2" "data-section"="my_data.2" "rodata-section"="my_rodata.2" } -attributes #6 = { "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "use-soft-float"="false" } -attributes #7 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #6 = { "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #7 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign) "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "use-soft-float"="false" } !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/llvm/test/CodeGen/X86/cmp16.ll b/llvm/test/CodeGen/X86/cmp16.ll index 8c14a78d9e113..ff6ee68074088 100644 --- a/llvm/test/CodeGen/X86/cmp16.ll +++ b/llvm/test/CodeGen/X86/cmp16.ll @@ -14,6 +14,7 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=X64,X64-FAST ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=X64,X64-FAST ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=X64,X64-FAST +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=X64,X64-FAST define i1 @cmp16_reg_eq_reg(i16 %a0, i16 %a1) { ; X86-GENERIC-LABEL: cmp16_reg_eq_reg: diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir index 8241a1757af52..a5f1f3d6d6268 100644 --- a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir +++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir @@ -40,7 +40,7 @@ body: | %0:gr32 = MOV32r0 implicit-def dead $eflags %1:gr8 = COPY %0.sub_8bit - %2:gr64 = SUBREG_TO_REG 0, killed %0, %subreg.sub_32bit + %2:gr64 = SUBREG_TO_REG killed %0, %subreg.sub_32bit JCC_1 %bb.2, 5, implicit killed undef $eflags bb.1: diff --git a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir index 722d9b60841a2..e49a449926124 100644 --- a/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir +++ b/llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir @@ -11,7 +11,7 @@ body: | %0:gr32 = MOV32r0 implicit-def dead $eflags %1:gr8 = COPY %0.sub_8bit - %2:gr64 = SUBREG_TO_REG 0, killed %0, %subreg.sub_32bit + %2:gr64 = SUBREG_TO_REG killed %0, %subreg.sub_32bit JCC_1 %bb.2, 5, implicit killed undef $eflags bb.1: diff --git a/llvm/test/CodeGen/X86/combine-adc.ll b/llvm/test/CodeGen/X86/combine-adc.ll index a2aaea31aa6ff..cb934c8664e45 100644 --- a/llvm/test/CodeGen/X86/combine-adc.ll +++ b/llvm/test/CodeGen/X86/combine-adc.ll @@ -136,5 +136,118 @@ define i32 @adc_merge_sub(i32 %a0) nounwind { ret i32 %result } +; Basic positive test +define i32 @adc_add(i32 %0, i32 %1, i32 %2, i32 %3) nounwind { +; X86-LABEL: adc_add: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: cmpl %ecx, %eax +; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx +; X86-NEXT: js .LBB4_2 +; X86-NEXT: # %bb.1: +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: .LBB4_2: +; X86-NEXT: retl +; +; X64-LABEL: adc_add: +; X64: # %bb.0: +; X64-NEXT: movl %esi, %eax +; X64-NEXT: cmpl %esi, %edi +; X64-NEXT: adcl %ecx, %edx +; X64-NEXT: cmovsl %edi, %eax +; X64-NEXT: retq + %5 = icmp ult i32 %0, %1 + %6 = add i32 %3, %2 + %7 = zext i1 %5 to i32 + %8 = add i32 %6, %7 + %9 = icmp slt i32 %8, 0 + %10 = select i1 %9, i32 %0, i32 %1 + ret i32 %10 +} + +; Negative test: Carry or overflow flag is used +define i32 @adc_add_wrong_flags(i32 %0, i32 %1, i32 %2, i32 %3) nounwind { +; X86-LABEL: adc_add_wrong_flags: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: addl {{[0-9]+}}(%esp), %edx +; X86-NEXT: cmpl %ecx, %eax +; X86-NEXT: adcl $0, %edx +; X86-NEXT: jb .LBB5_2 +; X86-NEXT: # %bb.1: +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: .LBB5_2: +; X86-NEXT: retl +; +; X64-LABEL: adc_add_wrong_flags: +; X64: # %bb.0: +; X64-NEXT: movl %esi, %eax +; X64-NEXT: addl %ecx, %edx +; X64-NEXT: cmpl %esi, %edi +; X64-NEXT: adcl $0, %edx +; X64-NEXT: cmovbl %edi, %eax +; X64-NEXT: retq + %5 = icmp ult i32 %0, %1 + %6 = add i32 %3, %2 + %7 = zext i1 %5 to i32 + %8 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %6, i32 %7) + %9 = extractvalue { i32, i1 } %8, 1 + %10 = select i1 %9, i32 %0, i32 %1 + ret i32 %10 +} + +; Negative test: Multi-use +define i32 @adc_add_multi_use(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, ptr %5) nounwind { +; X86-LABEL: adc_add_multi_use: +; X86: # %bb.0: +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: leal (%edi,%esi), %ebx +; X86-NEXT: cmpl %ecx, %eax +; X86-NEXT: movl %ebx, (%edx) +; X86-NEXT: adcl %esi, %edi +; X86-NEXT: addl {{[0-9]+}}(%esp), %edi +; X86-NEXT: js .LBB6_2 +; X86-NEXT: # %bb.1: +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: .LBB6_2: +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: retl +; +; X64-LABEL: adc_add_multi_use: +; X64: # %bb.0: +; X64-NEXT: # kill: def $ecx killed $ecx def $rcx +; X64-NEXT: # kill: def $edx killed $edx def $rdx +; X64-NEXT: movl %esi, %eax +; X64-NEXT: leal (%rcx,%rdx), %esi +; X64-NEXT: cmpl %eax, %edi +; X64-NEXT: movl %esi, (%r9) +; X64-NEXT: adcl %edx, %ecx +; X64-NEXT: addl %r8d, %ecx +; X64-NEXT: cmovsl %edi, %eax +; X64-NEXT: retq + %7 = icmp ult i32 %0, %1 + %8 = add i32 %3, %2 + store i32 %8, ptr %5, align 4 + %9 = zext i1 %7 to i32 + %10 = add i32 %8, %9 + %11 = add i32 %10, %4 + %12 = icmp slt i32 %11, 0 + %13 = select i1 %12, i32 %0, i32 %1 + ret i32 %13 +} + declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32) declare void @use(i8) diff --git a/llvm/test/CodeGen/X86/combine-bzhi.ll b/llvm/test/CodeGen/X86/combine-bzhi.ll index 54e76469dbb82..37b0c78347373 100644 --- a/llvm/test/CodeGen/X86/combine-bzhi.ll +++ b/llvm/test/CodeGen/X86/combine-bzhi.ll @@ -40,3 +40,44 @@ define i64 @test_bzhi64_constfold() nounwind readnone { ret i64 %1 } +define i32 @test_bzhi32_minvaluefold(i32 %arg) nounwind readnone { +; CHECK-LABEL: test_bzhi32_minvaluefold: +; CHECK: # %bb.0: +; CHECK-NEXT: movl $5, %eax +; CHECK-NEXT: retq + %2 = or i32 %arg, 32 + %3 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 5, i32 %2) + ret i32 %3 +} + +define i64 @test_bzhi64_minvaluefold(i64 %arg) nounwind readnone { +; CHECK-LABEL: test_bzhi64_minvaluefold: +; CHECK: # %bb.0: +; CHECK-NEXT: movabsq $30064771072, %rax # imm = 0x700000000 +; CHECK-NEXT: retq + %2 = or i64 %arg, 64 + %3 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 30064771072, i64 %2) + ret i64 %3 +} + +define i32 @test_bzhi32_range(i32 %arg) nounwind readnone { +; CHECK-LABEL: test_bzhi32_range: +; CHECK: # %bb.0: +; CHECK-NEXT: movl $42, %eax +; CHECK-NEXT: retq + %2 = or i32 %arg, 6 + %3 = and i32 %2, 7 + %4 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 699050, i32 %3) + ret i32 %4 +} + +define i64 @test_bzhi64_range(i64 %arg) nounwind readnone { +; CHECK-LABEL: test_bzhi64_range: +; CHECK: # %bb.0: +; CHECK-NEXT: movl $40, %eax +; CHECK-NEXT: retq + %2 = or i64 %arg, 6 + %3 = and i64 %2, 7 + %4 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 30064771240, i64 %3) + ret i64 %4 +} diff --git a/llvm/test/CodeGen/X86/cond-loop.ll b/llvm/test/CodeGen/X86/cond-loop.ll new file mode 100644 index 0000000000000..e6d6618855077 --- /dev/null +++ b/llvm/test/CodeGen/X86/cond-loop.ll @@ -0,0 +1,50 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=x86_64 | FileCheck %s + +define void @f1(i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK: # %bb.0: +; CHECK-NEXT: cmpq %rsi, %rdi +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: jb .Ltmp0 +; CHECK-NEXT: retq + %cmp = icmp ult i64 %a, %b + call void @llvm.cond.loop(i1 %cmp) + ret void +} + +define void @f2() { +; CHECK-LABEL: f2: +; CHECK: # %bb.0: +; CHECK-NEXT: movb $1, %al +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: .Ltmp1: +; CHECK-NEXT: jne .Ltmp1 +; CHECK-NEXT: retq + call void @llvm.cond.loop(i1 true) + ret void +} + +define void @f3(i1 %p) { +; CHECK-LABEL: f3: +; CHECK: # %bb.0: +; CHECK-NEXT: testb $1, %dil +; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: jne .Ltmp2 +; CHECK-NEXT: retq + call void @llvm.cond.loop(i1 %p) + ret void +} + +define void @f4(i32 %a, i32 %b) { +; CHECK-LABEL: f4: +; CHECK: # %bb.0: +; CHECK-NEXT: addl %esi, %edi +; CHECK-NEXT: .Ltmp3: +; CHECK-NEXT: jo .Ltmp3 +; CHECK-NEXT: retq + %add = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) + %overflow = extractvalue { i32, i1 } %add, 1 + tail call void @llvm.cond.loop(i1 %overflow) + ret void +} diff --git a/llvm/test/CodeGen/X86/cpus-amd.ll b/llvm/test/CodeGen/X86/cpus-amd.ll index 33b2cf3731478..33cbc71b41ecd 100644 --- a/llvm/test/CodeGen/X86/cpus-amd.ll +++ b/llvm/test/CodeGen/X86/cpus-amd.ll @@ -30,6 +30,7 @@ ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver5 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty +; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver6 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty define void @foo() { ret void diff --git a/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll b/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll new file mode 100644 index 0000000000000..4d6d795e3beb8 --- /dev/null +++ b/llvm/test/CodeGen/X86/div_i129_v_pow2k.ll @@ -0,0 +1,405 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-- -O0 | FileCheck %s --check-prefix=X64-O0 +; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=i686-- -O0 | FileCheck %s --check-prefix=X86-O0 + +define i129 @v_sdiv_i129_v_pow2k(i129 %lhs) nounwind { +; X64-LABEL: v_sdiv_i129_v_pow2k: +; X64: # %bb.0: +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: andl $1, %edx +; X64-NEXT: negq %rdx +; X64-NEXT: movl %edx, %eax +; X64-NEXT: andl $1, %eax +; X64-NEXT: shldq $32, %rdx, %rax +; X64-NEXT: addq %rdi, %rax +; X64-NEXT: adcq $0, %rsi +; X64-NEXT: adcq $0, %rcx +; X64-NEXT: shrdq $33, %rsi, %rax +; X64-NEXT: andl $1, %ecx +; X64-NEXT: movq %rcx, %rdx +; X64-NEXT: negq %rdx +; X64-NEXT: shldq $31, %rsi, %rdx +; X64-NEXT: retq +; +; X64-O0-LABEL: v_sdiv_i129_v_pow2k: +; X64-O0: # %bb.0: +; X64-O0-NEXT: movl %edx, %eax +; X64-O0-NEXT: andl $1, %eax +; X64-O0-NEXT: movl %eax, %ecx +; X64-O0-NEXT: negq %rcx +; X64-O0-NEXT: movl %ecx, %r8d +; X64-O0-NEXT: andl $1, %r8d +; X64-O0-NEXT: # implicit-def: $rax +; X64-O0-NEXT: movl %r8d, %eax +; X64-O0-NEXT: shldq $32, %rcx, %rax +; X64-O0-NEXT: addq %rax, %rdi +; X64-O0-NEXT: adcq $0, %rsi +; X64-O0-NEXT: adcq $0, %rdx +; X64-O0-NEXT: movq %rsi, %rax +; X64-O0-NEXT: shldq $31, %rdi, %rax +; X64-O0-NEXT: movl %edx, %ecx +; X64-O0-NEXT: andl $1, %ecx +; X64-O0-NEXT: # kill: def $rcx killed $ecx +; X64-O0-NEXT: movq %rcx, %rdx +; X64-O0-NEXT: negq %rdx +; X64-O0-NEXT: shldq $31, %rsi, %rdx +; X64-O0-NEXT: retq +; +; X86-LABEL: v_sdiv_i129_v_pow2k: +; X86: # %bb.0: +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %ecx, %ebx +; X86-NEXT: andl $1, %ebx +; X86-NEXT: negl %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: andl $1, %edi +; X86-NEXT: addl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: adcl {{[0-9]+}}(%esp), %edi +; X86-NEXT: adcl $0, %esi +; X86-NEXT: adcl $0, %edx +; X86-NEXT: adcl $0, %ecx +; X86-NEXT: movl %ecx, %ebx +; X86-NEXT: shldl $31, %edx, %ebx +; X86-NEXT: shldl $31, %esi, %edx +; X86-NEXT: shldl $31, %edi, %esi +; X86-NEXT: andl $1, %ecx +; X86-NEXT: movl %ecx, %edi +; X86-NEXT: negl %edi +; X86-NEXT: movl %esi, (%eax) +; X86-NEXT: movl %edx, 4(%eax) +; X86-NEXT: movl %ebx, 8(%eax) +; X86-NEXT: movl %edi, 12(%eax) +; X86-NEXT: movb %cl, 16(%eax) +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: retl $4 +; +; X86-O0-LABEL: v_sdiv_i129_v_pow2k: +; X86-O0: # %bb.0: +; X86-O0-NEXT: pushl %ebp +; X86-O0-NEXT: pushl %ebx +; X86-O0-NEXT: pushl %edi +; X86-O0-NEXT: pushl %esi +; X86-O0-NEXT: subl $8, %esp +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-O0-NEXT: movl %eax, (%esp) # 4-byte Spill +; X86-O0-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-O0-NEXT: movl %edx, %ecx +; X86-O0-NEXT: andl $1, %ecx +; X86-O0-NEXT: negl %ecx +; X86-O0-NEXT: movl %ecx, %edi +; X86-O0-NEXT: andl $1, %edi +; X86-O0-NEXT: addl %ecx, %eax +; X86-O0-NEXT: movl (%esp), %ecx # 4-byte Reload +; X86-O0-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-O0-NEXT: adcl %edi, %esi +; X86-O0-NEXT: adcl $0, %ebp +; X86-O0-NEXT: adcl $0, %ebx +; X86-O0-NEXT: adcl $0, %edx +; X86-O0-NEXT: movl %edx, %edi +; X86-O0-NEXT: shldl $31, %ebx, %edi +; X86-O0-NEXT: shldl $31, %ebp, %ebx +; X86-O0-NEXT: shldl $31, %esi, %ebp +; X86-O0-NEXT: andl $1, %edx +; X86-O0-NEXT: movl %edx, %esi +; X86-O0-NEXT: negl %esi +; X86-O0-NEXT: movl %ebp, (%ecx) +; X86-O0-NEXT: movl %ebx, 4(%ecx) +; X86-O0-NEXT: movl %edi, 8(%ecx) +; X86-O0-NEXT: movl %esi, 12(%ecx) +; X86-O0-NEXT: # kill: def $dl killed $dl killed $edx +; X86-O0-NEXT: movb %dl, 16(%ecx) +; X86-O0-NEXT: addl $8, %esp +; X86-O0-NEXT: popl %esi +; X86-O0-NEXT: popl %edi +; X86-O0-NEXT: popl %ebx +; X86-O0-NEXT: popl %ebp +; X86-O0-NEXT: retl $4 + %div = sdiv i129 %lhs, 8589934592 + ret i129 %div +} + +define i129 @v_sdiv_exact_i129_v_pow2k(i129 %lhs) nounwind { +; X64-LABEL: v_sdiv_exact_i129_v_pow2k: +; X64: # %bb.0: +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: andl $1, %edx +; X64-NEXT: negq %rdx +; X64-NEXT: movl %edx, %eax +; X64-NEXT: andl $1, %eax +; X64-NEXT: shldq $32, %rdx, %rax +; X64-NEXT: addq %rdi, %rax +; X64-NEXT: adcq $0, %rsi +; X64-NEXT: adcq $0, %rcx +; X64-NEXT: shrdq $33, %rsi, %rax +; X64-NEXT: andl $1, %ecx +; X64-NEXT: movq %rcx, %rdx +; X64-NEXT: negq %rdx +; X64-NEXT: shldq $31, %rsi, %rdx +; X64-NEXT: retq +; +; X64-O0-LABEL: v_sdiv_exact_i129_v_pow2k: +; X64-O0: # %bb.0: +; X64-O0-NEXT: movl %edx, %eax +; X64-O0-NEXT: andl $1, %eax +; X64-O0-NEXT: movl %eax, %ecx +; X64-O0-NEXT: negq %rcx +; X64-O0-NEXT: movl %ecx, %r8d +; X64-O0-NEXT: andl $1, %r8d +; X64-O0-NEXT: # implicit-def: $rax +; X64-O0-NEXT: movl %r8d, %eax +; X64-O0-NEXT: shldq $32, %rcx, %rax +; X64-O0-NEXT: addq %rax, %rdi +; X64-O0-NEXT: adcq $0, %rsi +; X64-O0-NEXT: adcq $0, %rdx +; X64-O0-NEXT: movq %rsi, %rax +; X64-O0-NEXT: shldq $31, %rdi, %rax +; X64-O0-NEXT: movl %edx, %ecx +; X64-O0-NEXT: andl $1, %ecx +; X64-O0-NEXT: # kill: def $rcx killed $ecx +; X64-O0-NEXT: movq %rcx, %rdx +; X64-O0-NEXT: negq %rdx +; X64-O0-NEXT: shldq $31, %rsi, %rdx +; X64-O0-NEXT: retq +; +; X86-LABEL: v_sdiv_exact_i129_v_pow2k: +; X86: # %bb.0: +; X86-NEXT: pushl %ebx +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %ecx, %ebx +; X86-NEXT: andl $1, %ebx +; X86-NEXT: negl %ebx +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: andl $1, %edi +; X86-NEXT: addl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: adcl {{[0-9]+}}(%esp), %edi +; X86-NEXT: adcl $0, %esi +; X86-NEXT: adcl $0, %edx +; X86-NEXT: adcl $0, %ecx +; X86-NEXT: movl %ecx, %ebx +; X86-NEXT: shldl $31, %edx, %ebx +; X86-NEXT: shldl $31, %esi, %edx +; X86-NEXT: shldl $31, %edi, %esi +; X86-NEXT: andl $1, %ecx +; X86-NEXT: movl %ecx, %edi +; X86-NEXT: negl %edi +; X86-NEXT: movl %esi, (%eax) +; X86-NEXT: movl %edx, 4(%eax) +; X86-NEXT: movl %ebx, 8(%eax) +; X86-NEXT: movl %edi, 12(%eax) +; X86-NEXT: movb %cl, 16(%eax) +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebx +; X86-NEXT: retl $4 +; +; X86-O0-LABEL: v_sdiv_exact_i129_v_pow2k: +; X86-O0: # %bb.0: +; X86-O0-NEXT: pushl %ebp +; X86-O0-NEXT: pushl %ebx +; X86-O0-NEXT: pushl %edi +; X86-O0-NEXT: pushl %esi +; X86-O0-NEXT: subl $8, %esp +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-O0-NEXT: movl %eax, (%esp) # 4-byte Spill +; X86-O0-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-O0-NEXT: movl %edx, %ecx +; X86-O0-NEXT: andl $1, %ecx +; X86-O0-NEXT: negl %ecx +; X86-O0-NEXT: movl %ecx, %edi +; X86-O0-NEXT: andl $1, %edi +; X86-O0-NEXT: addl %ecx, %eax +; X86-O0-NEXT: movl (%esp), %ecx # 4-byte Reload +; X86-O0-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-O0-NEXT: adcl %edi, %esi +; X86-O0-NEXT: adcl $0, %ebp +; X86-O0-NEXT: adcl $0, %ebx +; X86-O0-NEXT: adcl $0, %edx +; X86-O0-NEXT: movl %edx, %edi +; X86-O0-NEXT: shldl $31, %ebx, %edi +; X86-O0-NEXT: shldl $31, %ebp, %ebx +; X86-O0-NEXT: shldl $31, %esi, %ebp +; X86-O0-NEXT: andl $1, %edx +; X86-O0-NEXT: movl %edx, %esi +; X86-O0-NEXT: negl %esi +; X86-O0-NEXT: movl %ebp, (%ecx) +; X86-O0-NEXT: movl %ebx, 4(%ecx) +; X86-O0-NEXT: movl %edi, 8(%ecx) +; X86-O0-NEXT: movl %esi, 12(%ecx) +; X86-O0-NEXT: # kill: def $dl killed $dl killed $edx +; X86-O0-NEXT: movb %dl, 16(%ecx) +; X86-O0-NEXT: addl $8, %esp +; X86-O0-NEXT: popl %esi +; X86-O0-NEXT: popl %edi +; X86-O0-NEXT: popl %ebx +; X86-O0-NEXT: popl %ebp +; X86-O0-NEXT: retl $4 + %div = sdiv exact i129 %lhs, 8589934592 + ret i129 %div +} + +define i129 @v_udiv_i129_v_pow2k(i129 %lhs) nounwind { +; X64-LABEL: v_udiv_i129_v_pow2k: +; X64: # %bb.0: +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: andl $1, %edx +; X64-NEXT: shrdq $33, %rsi, %rax +; X64-NEXT: shldq $31, %rsi, %rdx +; X64-NEXT: xorl %ecx, %ecx +; X64-NEXT: retq +; +; X64-O0-LABEL: v_udiv_i129_v_pow2k: +; X64-O0: # %bb.0: +; X64-O0-NEXT: movq %rsi, %rax +; X64-O0-NEXT: shldq $31, %rdi, %rax +; X64-O0-NEXT: movl %edx, %ecx +; X64-O0-NEXT: andl $1, %ecx +; X64-O0-NEXT: movl %ecx, %edx +; X64-O0-NEXT: shldq $31, %rsi, %rdx +; X64-O0-NEXT: xorl %ecx, %ecx +; X64-O0-NEXT: # kill: def $rcx killed $ecx +; X64-O0-NEXT: retq +; +; X86-LABEL: v_udiv_i129_v_pow2k: +; X86: # %bb.0: +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: shrdl $1, %esi, %edx +; X86-NEXT: shldl $31, %edi, %ecx +; X86-NEXT: shldl $31, %esi, %edi +; X86-NEXT: movl %ecx, 8(%eax) +; X86-NEXT: movl %edi, 4(%eax) +; X86-NEXT: movl %edx, (%eax) +; X86-NEXT: movl $0, 12(%eax) +; X86-NEXT: movb $0, 16(%eax) +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 +; +; X86-O0-LABEL: v_udiv_i129_v_pow2k: +; X86-O0: # %bb.0: +; X86-O0-NEXT: pushl %ebx +; X86-O0-NEXT: pushl %edi +; X86-O0-NEXT: pushl %esi +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-O0-NEXT: movl %ecx, %eax +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-O0-NEXT: shldl $31, %esi, %edx +; X86-O0-NEXT: shldl $31, %edi, %esi +; X86-O0-NEXT: shldl $31, %ebx, %edi +; X86-O0-NEXT: movl %edi, (%ecx) +; X86-O0-NEXT: movl %esi, 4(%ecx) +; X86-O0-NEXT: movl %edx, 8(%ecx) +; X86-O0-NEXT: movl $0, 12(%ecx) +; X86-O0-NEXT: movb $0, 16(%ecx) +; X86-O0-NEXT: popl %esi +; X86-O0-NEXT: popl %edi +; X86-O0-NEXT: popl %ebx +; X86-O0-NEXT: retl $4 + %div = udiv i129 %lhs, 8589934592 + ret i129 %div +} + +define i129 @v_udiv_exact_i129_v_pow2k(i129 %lhs) nounwind { +; X64-LABEL: v_udiv_exact_i129_v_pow2k: +; X64: # %bb.0: +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: andl $1, %edx +; X64-NEXT: shrdq $33, %rsi, %rax +; X64-NEXT: shldq $31, %rsi, %rdx +; X64-NEXT: xorl %ecx, %ecx +; X64-NEXT: retq +; +; X64-O0-LABEL: v_udiv_exact_i129_v_pow2k: +; X64-O0: # %bb.0: +; X64-O0-NEXT: movq %rsi, %rax +; X64-O0-NEXT: shldq $31, %rdi, %rax +; X64-O0-NEXT: movl %edx, %ecx +; X64-O0-NEXT: andl $1, %ecx +; X64-O0-NEXT: movl %ecx, %edx +; X64-O0-NEXT: shldq $31, %rsi, %rdx +; X64-O0-NEXT: xorl %ecx, %ecx +; X64-O0-NEXT: # kill: def $rcx killed $ecx +; X64-O0-NEXT: retq +; +; X86-LABEL: v_udiv_exact_i129_v_pow2k: +; X86: # %bb.0: +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: shrdl $1, %esi, %edx +; X86-NEXT: shldl $31, %edi, %ecx +; X86-NEXT: shldl $31, %esi, %edi +; X86-NEXT: movl %ecx, 8(%eax) +; X86-NEXT: movl %edi, 4(%eax) +; X86-NEXT: movl %edx, (%eax) +; X86-NEXT: movl $0, 12(%eax) +; X86-NEXT: movb $0, 16(%eax) +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 +; +; X86-O0-LABEL: v_udiv_exact_i129_v_pow2k: +; X86-O0: # %bb.0: +; X86-O0-NEXT: pushl %ebx +; X86-O0-NEXT: pushl %edi +; X86-O0-NEXT: pushl %esi +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-O0-NEXT: movl %ecx, %eax +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-O0-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X86-O0-NEXT: shldl $31, %esi, %edx +; X86-O0-NEXT: shldl $31, %edi, %esi +; X86-O0-NEXT: shldl $31, %ebx, %edi +; X86-O0-NEXT: movl %edi, (%ecx) +; X86-O0-NEXT: movl %esi, 4(%ecx) +; X86-O0-NEXT: movl %edx, 8(%ecx) +; X86-O0-NEXT: movl $0, 12(%ecx) +; X86-O0-NEXT: movb $0, 16(%ecx) +; X86-O0-NEXT: popl %esi +; X86-O0-NEXT: popl %edi +; X86-O0-NEXT: popl %ebx +; X86-O0-NEXT: retl $4 + %div = udiv exact i129 %lhs, 8589934592 + ret i129 %div +} diff --git a/llvm/test/CodeGen/X86/exp10-libcall-names.ll b/llvm/test/CodeGen/X86/exp10-libcall-names.ll index 2688474b2ce5c..614658b2be4c6 100644 --- a/llvm/test/CodeGen/X86/exp10-libcall-names.ll +++ b/llvm/test/CodeGen/X86/exp10-libcall-names.ll @@ -58,10 +58,8 @@ define double @test_exp10_f64(double %x) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll exp10 ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/expand-large-fp-optnone.ll b/llvm/test/CodeGen/X86/expand-large-fp-optnone.ll index cf155b3c3f1ac..a635d55d2033d 100644 --- a/llvm/test/CodeGen/X86/expand-large-fp-optnone.ll +++ b/llvm/test/CodeGen/X86/expand-large-fp-optnone.ll @@ -27,13 +27,13 @@ define double @main(i224 %0) #0 { ; CHECK-NEXT: .cfi_offset %r14, -32 ; CHECK-NEXT: .cfi_offset %r15, -24 ; CHECK-NEXT: .cfi_offset %rbp, -16 -; CHECK-NEXT: movq %rdi, %rax -; CHECK-NEXT: orq %rdx, %rax -; CHECK-NEXT: movl %ecx, %r8d +; CHECK-NEXT: movl %ecx, %eax +; CHECK-NEXT: movq %rdi, %r8 +; CHECK-NEXT: orq %rdx, %r8 ; CHECK-NEXT: movq %rsi, %r9 -; CHECK-NEXT: orq %r8, %r9 +; CHECK-NEXT: orq %rax, %r9 ; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: orq %r9, %rax +; CHECK-NEXT: orq %r9, %r8 ; CHECK-NEXT: je .LBB0_10 ; CHECK-NEXT: jmp .LBB0_1 ; CHECK-NEXT: .LBB0_1: # %itofp-if-end diff --git a/llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir b/llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir index ffc3fd6ce0d89..d3db88a6c29f4 100644 --- a/llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir +++ b/llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir @@ -7,5 +7,5 @@ body: | liveins: $eax ; CHECK-NOT: dead $rax = KILL {{[0-9]+}} ; CHECK: dead $rax = KILL killed $eax - dead $rax = SUBREG_TO_REG 0, killed $eax, %subreg.sub_32bit + dead $rax = SUBREG_TO_REG killed $eax, %subreg.sub_32bit ... diff --git a/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir b/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir index 37a90a2f16d67..b26dd5a959967 100644 --- a/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir +++ b/llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir @@ -188,7 +188,7 @@ body: | %0:gr32 = COPY $edi %1:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg, debug-location !13 :: (dereferenceable load (s32) from %ir.a.addr) - %2:gr64_nosp = SUBREG_TO_REG 0, killed %1, %subreg.sub_32bit, debug-location !13 + %2:gr64_nosp = SUBREG_TO_REG killed %1, %subreg.sub_32bit, debug-location !13 ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !14 %3:gr64 = COPY $rsp, debug-location !14 $rsp = COPY %3, debug-location !14 diff --git a/llvm/test/CodeGen/X86/finite-libcalls.ll b/llvm/test/CodeGen/X86/finite-libcalls.ll index ea2695dc96997..acc7ddeb9a886 100644 --- a/llvm/test/CodeGen/X86/finite-libcalls.ll +++ b/llvm/test/CodeGen/X86/finite-libcalls.ll @@ -59,10 +59,8 @@ define double @exp_f64(double %x) #0 { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll exp ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl @@ -185,10 +183,8 @@ define double @exp2_f64(double %x) #0 { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll exp2 ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl @@ -311,10 +307,8 @@ define double @log_f64(double %x) #0 { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll log ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl @@ -437,10 +431,8 @@ define double @log2_f64(double %x) #0 { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll log2 ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl @@ -563,10 +555,8 @@ define double @log10_f64(double %x) #0 { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll log10 ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl @@ -697,10 +687,8 @@ define double @pow_f64(double %x) #0 { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: movl $8, %edx ; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) diff --git a/llvm/test/CodeGen/X86/fold-add-16.ll b/llvm/test/CodeGen/X86/fold-add-16.ll new file mode 100644 index 0000000000000..5c038381eccd5 --- /dev/null +++ b/llvm/test/CodeGen/X86/fold-add-16.ll @@ -0,0 +1,45 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=i386-unknown-code16 < %s | FileCheck %s + +;; In 16-bit mode, displacements are limited to [-65535,65535] (R_386_16). +;; Test boundary conditions for offset folding. + +@X = external global i32, align 4 + +;; -65535 is within range, should fold +define i32 @neg_65535() { +; CHECK-LABEL: neg_65535: +; CHECK: # %bb.0: +; CHECK-NEXT: leal X+65535, %eax +; CHECK-NEXT: retl + ret i32 add (i32 ptrtoint (ptr @X to i32), i32 65535) +} + +;; 65535 is within range, should fold +define i32 @pos_65535() { +; CHECK-LABEL: pos_65535: +; CHECK: # %bb.0: +; CHECK-NEXT: leal X-65535, %eax +; CHECK-NEXT: retl + ret i32 sub (i32 ptrtoint (ptr @X to i32), i32 65535) +} + +;; -65536 is outside range, should NOT fold +define i32 @neg_65536() { +; CHECK-LABEL: neg_65536: +; CHECK: # %bb.0: +; CHECK-NEXT: movl $65536, %eax # imm = 0x10000 +; CHECK-NEXT: leal X(%eax), %eax +; CHECK-NEXT: retl + ret i32 add (i32 ptrtoint (ptr @X to i32), i32 65536) +} + +;; 65536 is outside range, should NOT fold +define i32 @pos_65536() { +; CHECK-LABEL: pos_65536: +; CHECK: # %bb.0: +; CHECK-NEXT: movl $-65536, %eax # imm = 0xFFFF0000 +; CHECK-NEXT: leal X(%eax), %eax +; CHECK-NEXT: retl + ret i32 sub (i32 ptrtoint (ptr @X to i32), i32 65536) +} diff --git a/llvm/test/CodeGen/X86/dag-large-offset.ll b/llvm/test/CodeGen/X86/fold-add-32.ll similarity index 100% rename from llvm/test/CodeGen/X86/dag-large-offset.ll rename to llvm/test/CodeGen/X86/fold-add-32.ll diff --git a/llvm/test/CodeGen/X86/foldimmediate.mir b/llvm/test/CodeGen/X86/foldimmediate.mir index 5fd5ae9c1ca9f..82f99655264de 100644 --- a/llvm/test/CodeGen/X86/foldimmediate.mir +++ b/llvm/test/CodeGen/X86/foldimmediate.mir @@ -54,7 +54,7 @@ body: | ; CHECK-NEXT: NOOP implicit [[ADC32ri]] ; CHECK-NEXT: [[SBB32ri:%[0-9]+]]:gr32 = SBB32ri [[COPY]], 81, implicit-def $eflags, implicit $eflags ; CHECK-NEXT: NOOP implicit [[SBB32ri]] - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32ri]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32ri]], %subreg.sub_32bit ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi ; CHECK-NEXT: [[ADD64ri32_:%[0-9]+]]:gr64 = ADD64ri32 [[COPY1]], 81, implicit-def $eflags ; CHECK-NEXT: NOOP implicit [[ADD64ri32_]] @@ -107,7 +107,7 @@ body: | %18 = SBB32rr %1, %0, implicit-def $eflags, implicit $eflags NOOP implicit %18 - %7 = SUBREG_TO_REG 0, killed %0:gr32, %subreg.sub_32bit + %7 = SUBREG_TO_REG killed %0:gr32, %subreg.sub_32bit %8 = COPY $rsi %9 = ADD64rr %7, %8, implicit-def $eflags NOOP implicit %9 diff --git a/llvm/test/CodeGen/X86/gfni-lzcnt.ll b/llvm/test/CodeGen/X86/gfni-lzcnt.ll index 6e93f218f1c15..5e7894d821d48 100644 --- a/llvm/test/CodeGen/X86/gfni-lzcnt.ll +++ b/llvm/test/CodeGen/X86/gfni-lzcnt.ll @@ -76,7 +76,7 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; GFNISSE-NEXT: pxor %xmm4, %xmm4 ; GFNISSE-NEXT: psubb %xmm0, %xmm4 ; GFNISSE-NEXT: pand %xmm4, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [12307476859704049664,12307476859704049664] +; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] ; GFNISSE-NEXT: gf2p8affineqb $8, %xmm4, %xmm0 ; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm1 ; GFNISSE-NEXT: psubb %xmm1, %xmm3 @@ -106,8 +106,7 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; GFNIAVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; GFNIAVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; GFNIAVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [12307476859704049664,12307476859704049664,12307476859704049664,12307476859704049664] -; GFNIAVX2-NEXT: vgf2p8affineqb $8, %ymm1, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; GFNIAVX2-NEXT: retq ; ; GFNIAVX512-LABEL: testv32i8: @@ -131,7 +130,7 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; GFNISSE-NEXT: pxor %xmm4, %xmm4 ; GFNISSE-NEXT: psubb %xmm0, %xmm4 ; GFNISSE-NEXT: pand %xmm4, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [12307476859704049664,12307476859704049664] +; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] ; GFNISSE-NEXT: gf2p8affineqb $8, %xmm4, %xmm0 ; GFNISSE-NEXT: gf2p8affineqb $0, %xmm2, %xmm1 ; GFNISSE-NEXT: psubb %xmm1, %xmm3 @@ -161,8 +160,7 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; GFNIAVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; GFNIAVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm1 ; GFNIAVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [12307476859704049664,12307476859704049664,12307476859704049664,12307476859704049664] -; GFNIAVX2-NEXT: vgf2p8affineqb $8, %ymm1, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; GFNIAVX2-NEXT: retq ; ; GFNIAVX512-LABEL: testv32i8u: @@ -186,7 +184,7 @@ define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { ; GFNISSE-NEXT: pxor %xmm6, %xmm6 ; GFNISSE-NEXT: psubb %xmm0, %xmm6 ; GFNISSE-NEXT: pand %xmm6, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [12307476859704049664,12307476859704049664] +; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] ; GFNISSE-NEXT: gf2p8affineqb $8, %xmm6, %xmm0 ; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm1 ; GFNISSE-NEXT: pxor %xmm7, %xmm7 @@ -217,7 +215,7 @@ define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { ; GFNIAVX1-NEXT: vpsubb %xmm0, %xmm5, %xmm0 ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; GFNIAVX1-NEXT: vandps %ymm0, %ymm4, %ymm0 -; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [12307476859704049664,12307476859704049664,12307476859704049664,12307476859704049664] +; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] ; GFNIAVX1-NEXT: vgf2p8affineqb $8, %ymm2, %ymm0, %ymm0 ; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 ; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm4, %xmm4 @@ -237,7 +235,7 @@ define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { ; GFNIAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; GFNIAVX2-NEXT: vpsubb %ymm0, %ymm3, %ymm4 ; GFNIAVX2-NEXT: vpand %ymm4, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [12307476859704049664,12307476859704049664,12307476859704049664,12307476859704049664] +; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] ; GFNIAVX2-NEXT: vgf2p8affineqb $8, %ymm4, %ymm0, %ymm0 ; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1 ; GFNIAVX2-NEXT: vpsubb %ymm1, %ymm3, %ymm2 @@ -281,7 +279,7 @@ define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind { ; GFNISSE-NEXT: pxor %xmm6, %xmm6 ; GFNISSE-NEXT: psubb %xmm0, %xmm6 ; GFNISSE-NEXT: pand %xmm6, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [12307476859704049664,12307476859704049664] +; GFNISSE-NEXT: movdqa {{.*#+}} xmm6 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] ; GFNISSE-NEXT: gf2p8affineqb $8, %xmm6, %xmm0 ; GFNISSE-NEXT: gf2p8affineqb $0, %xmm4, %xmm1 ; GFNISSE-NEXT: pxor %xmm7, %xmm7 @@ -312,7 +310,7 @@ define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind { ; GFNIAVX1-NEXT: vpsubb %xmm0, %xmm5, %xmm0 ; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; GFNIAVX1-NEXT: vandps %ymm0, %ymm4, %ymm0 -; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [12307476859704049664,12307476859704049664,12307476859704049664,12307476859704049664] +; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] ; GFNIAVX1-NEXT: vgf2p8affineqb $8, %ymm2, %ymm0, %ymm0 ; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 ; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm3, %xmm4, %xmm4 @@ -332,7 +330,7 @@ define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind { ; GFNIAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; GFNIAVX2-NEXT: vpsubb %ymm0, %ymm3, %ymm4 ; GFNIAVX2-NEXT: vpand %ymm4, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [12307476859704049664,12307476859704049664,12307476859704049664,12307476859704049664] +; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] ; GFNIAVX2-NEXT: vgf2p8affineqb $8, %ymm4, %ymm0, %ymm0 ; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm2, %ymm1, %ymm1 ; GFNIAVX2-NEXT: vpsubb %ymm1, %ymm3, %ymm2 diff --git a/llvm/test/CodeGen/X86/gfni-tzcnt.ll b/llvm/test/CodeGen/X86/gfni-tzcnt.ll index f424483c53e2c..533243f49250d 100644 --- a/llvm/test/CodeGen/X86/gfni-tzcnt.ll +++ b/llvm/test/CodeGen/X86/gfni-tzcnt.ll @@ -8,44 +8,26 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind { ; GFNISSE-LABEL: testv16i8: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: pcmpeqd %xmm1, %xmm1 -; GFNISSE-NEXT: paddb %xmm0, %xmm1 -; GFNISSE-NEXT: pandn %xmm1, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNISSE-NEXT: pand %xmm0, %xmm2 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNISSE-NEXT: movdqa %xmm1, %xmm3 -; GFNISSE-NEXT: pshufb %xmm2, %xmm3 -; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; GFNISSE-NEXT: pshufb %xmm0, %xmm1 -; GFNISSE-NEXT: paddb %xmm3, %xmm1 -; GFNISSE-NEXT: movdqa %xmm1, %xmm0 +; GFNISSE-NEXT: pxor %xmm1, %xmm1 +; GFNISSE-NEXT: psubb %xmm0, %xmm1 +; GFNISSE-NEXT: pand %xmm1, %xmm0 +; GFNISSE-NEXT: gf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; GFNISSE-NEXT: retq ; ; GFNIAVX1OR2-LABEL: testv16i8: ; GFNIAVX1OR2: # %bb.0: -; GFNIAVX1OR2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm0, %xmm1 -; GFNIAVX1OR2-NEXT: vpandn %xmm1, %xmm0, %xmm0 -; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 -; GFNIAVX1OR2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX1OR2-NEXT: vpshufb %xmm1, %xmm2, %xmm1 -; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; GFNIAVX1OR2-NEXT: vpshufb %xmm0, %xmm2, %xmm0 -; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX1OR2-NEXT: vpsubb %xmm0, %xmm1, %xmm1 +; GFNIAVX1OR2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: retq ; ; GFNIAVX512-LABEL: testv16i8: ; GFNIAVX512: # %bb.0: -; GFNIAVX512-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; GFNIAVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm1 -; GFNIAVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 -; GFNIAVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1 -; GFNIAVX512-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX512-NEXT: vpshufb %xmm1, %xmm2, %xmm1 -; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 -; GFNIAVX512-NEXT: vpshufb %xmm0, %xmm2, %xmm0 -; GFNIAVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; GFNIAVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX512-NEXT: vpsubb %xmm0, %xmm1, %xmm1 +; GFNIAVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 +; GFNIAVX512-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 ; GFNIAVX512-NEXT: retq %out = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %in, i1 0) ret <16 x i8> %out @@ -54,44 +36,26 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind { define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind { ; GFNISSE-LABEL: testv16i8u: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: pcmpeqd %xmm1, %xmm1 -; GFNISSE-NEXT: paddb %xmm0, %xmm1 -; GFNISSE-NEXT: pandn %xmm1, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNISSE-NEXT: pand %xmm0, %xmm2 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNISSE-NEXT: movdqa %xmm1, %xmm3 -; GFNISSE-NEXT: pshufb %xmm2, %xmm3 -; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; GFNISSE-NEXT: pshufb %xmm0, %xmm1 -; GFNISSE-NEXT: paddb %xmm3, %xmm1 -; GFNISSE-NEXT: movdqa %xmm1, %xmm0 +; GFNISSE-NEXT: pxor %xmm1, %xmm1 +; GFNISSE-NEXT: psubb %xmm0, %xmm1 +; GFNISSE-NEXT: pand %xmm1, %xmm0 +; GFNISSE-NEXT: gf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; GFNISSE-NEXT: retq ; ; GFNIAVX1OR2-LABEL: testv16i8u: ; GFNIAVX1OR2: # %bb.0: -; GFNIAVX1OR2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm0, %xmm1 -; GFNIAVX1OR2-NEXT: vpandn %xmm1, %xmm0, %xmm0 -; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 -; GFNIAVX1OR2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX1OR2-NEXT: vpshufb %xmm1, %xmm2, %xmm1 -; GFNIAVX1OR2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; GFNIAVX1OR2-NEXT: vpshufb %xmm0, %xmm2, %xmm0 -; GFNIAVX1OR2-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX1OR2-NEXT: vpsubb %xmm0, %xmm1, %xmm1 +; GFNIAVX1OR2-NEXT: vpand %xmm1, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: retq ; ; GFNIAVX512-LABEL: testv16i8u: ; GFNIAVX512: # %bb.0: -; GFNIAVX512-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 -; GFNIAVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm1 -; GFNIAVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 -; GFNIAVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm1 -; GFNIAVX512-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX512-NEXT: vpshufb %xmm1, %xmm2, %xmm1 -; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 -; GFNIAVX512-NEXT: vpshufb %xmm0, %xmm2, %xmm0 -; GFNIAVX512-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; GFNIAVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX512-NEXT: vpsubb %xmm0, %xmm1, %xmm1 +; GFNIAVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 +; GFNIAVX512-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 ; GFNIAVX512-NEXT: retq %out = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %in, i1 -1) ret <16 x i8> %out @@ -100,84 +64,42 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind { define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { ; GFNISSE-LABEL: testv32i8: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: pcmpeqd %xmm4, %xmm4 -; GFNISSE-NEXT: movdqa %xmm0, %xmm2 -; GFNISSE-NEXT: paddb %xmm4, %xmm2 -; GFNISSE-NEXT: pandn %xmm2, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNISSE-NEXT: movdqa %xmm0, %xmm3 -; GFNISSE-NEXT: pand %xmm5, %xmm3 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNISSE-NEXT: movdqa %xmm2, %xmm6 -; GFNISSE-NEXT: pshufb %xmm3, %xmm6 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm0 -; GFNISSE-NEXT: movdqa %xmm2, %xmm3 -; GFNISSE-NEXT: pshufb %xmm0, %xmm3 -; GFNISSE-NEXT: paddb %xmm6, %xmm3 -; GFNISSE-NEXT: paddb %xmm1, %xmm4 -; GFNISSE-NEXT: pandn %xmm4, %xmm1 -; GFNISSE-NEXT: pand %xmm1, %xmm5 -; GFNISSE-NEXT: movdqa %xmm2, %xmm0 -; GFNISSE-NEXT: pshufb %xmm5, %xmm0 -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm1 -; GFNISSE-NEXT: pshufb %xmm1, %xmm2 -; GFNISSE-NEXT: paddb %xmm0, %xmm2 -; GFNISSE-NEXT: movdqa %xmm3, %xmm0 -; GFNISSE-NEXT: movdqa %xmm2, %xmm1 +; GFNISSE-NEXT: pxor %xmm2, %xmm2 +; GFNISSE-NEXT: pxor %xmm3, %xmm3 +; GFNISSE-NEXT: psubb %xmm0, %xmm3 +; GFNISSE-NEXT: pand %xmm3, %xmm0 +; GFNISSE-NEXT: movdqa {{.*#+}} xmm3 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm3, %xmm0 +; GFNISSE-NEXT: psubb %xmm1, %xmm2 +; GFNISSE-NEXT: pand %xmm2, %xmm1 +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm3, %xmm1 ; GFNISSE-NEXT: retq ; ; GFNIAVX1-LABEL: testv32i8: ; GFNIAVX1: # %bb.0: ; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; GFNIAVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm1, %xmm3 -; GFNIAVX1-NEXT: vpandn %xmm3, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm4 -; GFNIAVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4 -; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm6 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNIAVX1-NEXT: # xmm6 = mem[0,0] -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1 -; GFNIAVX1-NEXT: vpaddb %xmm4, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm2 -; GFNIAVX1-NEXT: vpandn %xmm2, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm2 -; GFNIAVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2 -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0 -; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; GFNIAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; GFNIAVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1 +; GFNIAVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2 +; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 +; GFNIAVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 +; GFNIAVX1-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; GFNIAVX1-NEXT: retq ; ; GFNIAVX2-LABEL: testv32i8: ; GFNIAVX2: # %bb.0: -; GFNIAVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm1 -; GFNIAVX2-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 -; GFNIAVX2-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX2-NEXT: # ymm2 = mem[0,1,0,1] -; GFNIAVX2-NEXT: vpshufb %ymm1, %ymm2, %ymm1 -; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpshufb %ymm0, %ymm2, %ymm0 -; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm1 +; GFNIAVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; GFNIAVX2-NEXT: retq ; ; GFNIAVX512-LABEL: testv32i8: ; GFNIAVX512: # %bb.0: -; GFNIAVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; GFNIAVX512-NEXT: vpaddb %ymm1, %ymm0, %ymm1 -; GFNIAVX512-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; GFNIAVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm1 -; GFNIAVX512-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX512-NEXT: # ymm2 = mem[0,1,0,1] -; GFNIAVX512-NEXT: vpshufb %ymm1, %ymm2, %ymm1 -; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0 -; GFNIAVX512-NEXT: vpshufb %ymm0, %ymm2, %ymm0 -; GFNIAVX512-NEXT: vpaddb %ymm1, %ymm0, %ymm0 +; GFNIAVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX512-NEXT: vpsubb %ymm0, %ymm1, %ymm1 +; GFNIAVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 +; GFNIAVX512-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0 ; GFNIAVX512-NEXT: retq %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %in, i1 0) ret <32 x i8> %out @@ -186,84 +108,42 @@ define <32 x i8> @testv32i8(<32 x i8> %in) nounwind { define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { ; GFNISSE-LABEL: testv32i8u: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: pcmpeqd %xmm4, %xmm4 -; GFNISSE-NEXT: movdqa %xmm0, %xmm2 -; GFNISSE-NEXT: paddb %xmm4, %xmm2 -; GFNISSE-NEXT: pandn %xmm2, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNISSE-NEXT: movdqa %xmm0, %xmm3 -; GFNISSE-NEXT: pand %xmm5, %xmm3 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNISSE-NEXT: movdqa %xmm2, %xmm6 -; GFNISSE-NEXT: pshufb %xmm3, %xmm6 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm0 -; GFNISSE-NEXT: movdqa %xmm2, %xmm3 -; GFNISSE-NEXT: pshufb %xmm0, %xmm3 -; GFNISSE-NEXT: paddb %xmm6, %xmm3 -; GFNISSE-NEXT: paddb %xmm1, %xmm4 -; GFNISSE-NEXT: pandn %xmm4, %xmm1 -; GFNISSE-NEXT: pand %xmm1, %xmm5 -; GFNISSE-NEXT: movdqa %xmm2, %xmm0 -; GFNISSE-NEXT: pshufb %xmm5, %xmm0 -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm7, %xmm1 -; GFNISSE-NEXT: pshufb %xmm1, %xmm2 -; GFNISSE-NEXT: paddb %xmm0, %xmm2 -; GFNISSE-NEXT: movdqa %xmm3, %xmm0 -; GFNISSE-NEXT: movdqa %xmm2, %xmm1 +; GFNISSE-NEXT: pxor %xmm2, %xmm2 +; GFNISSE-NEXT: pxor %xmm3, %xmm3 +; GFNISSE-NEXT: psubb %xmm0, %xmm3 +; GFNISSE-NEXT: pand %xmm3, %xmm0 +; GFNISSE-NEXT: movdqa {{.*#+}} xmm3 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm3, %xmm0 +; GFNISSE-NEXT: psubb %xmm1, %xmm2 +; GFNISSE-NEXT: pand %xmm2, %xmm1 +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm3, %xmm1 ; GFNISSE-NEXT: retq ; ; GFNIAVX1-LABEL: testv32i8u: ; GFNIAVX1: # %bb.0: ; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; GFNIAVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm1, %xmm3 -; GFNIAVX1-NEXT: vpandn %xmm3, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNIAVX1-NEXT: vpand %xmm3, %xmm1, %xmm4 -; GFNIAVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX1-NEXT: vpshufb %xmm4, %xmm5, %xmm4 -; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm6 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNIAVX1-NEXT: # xmm6 = mem[0,0] -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vpshufb %xmm1, %xmm5, %xmm1 -; GFNIAVX1-NEXT: vpaddb %xmm4, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm2 -; GFNIAVX1-NEXT: vpandn %xmm2, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vpand %xmm3, %xmm0, %xmm2 -; GFNIAVX1-NEXT: vpshufb %xmm2, %xmm5, %xmm2 -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm6, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vpshufb %xmm0, %xmm5, %xmm0 -; GFNIAVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; GFNIAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; GFNIAVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1 +; GFNIAVX1-NEXT: vpsubb %xmm0, %xmm2, %xmm2 +; GFNIAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 +; GFNIAVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 +; GFNIAVX1-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; GFNIAVX1-NEXT: retq ; ; GFNIAVX2-LABEL: testv32i8u: ; GFNIAVX2: # %bb.0: -; GFNIAVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm1 -; GFNIAVX2-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 -; GFNIAVX2-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX2-NEXT: # ymm2 = mem[0,1,0,1] -; GFNIAVX2-NEXT: vpshufb %ymm1, %ymm2, %ymm1 -; GFNIAVX2-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpshufb %ymm0, %ymm2, %ymm0 -; GFNIAVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX2-NEXT: vpsubb %ymm0, %ymm1, %ymm1 +; GFNIAVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 ; GFNIAVX2-NEXT: retq ; ; GFNIAVX512-LABEL: testv32i8u: ; GFNIAVX512: # %bb.0: -; GFNIAVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; GFNIAVX512-NEXT: vpaddb %ymm1, %ymm0, %ymm1 -; GFNIAVX512-NEXT: vpandn %ymm1, %ymm0, %ymm0 -; GFNIAVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm1 -; GFNIAVX512-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX512-NEXT: # ymm2 = mem[0,1,0,1] -; GFNIAVX512-NEXT: vpshufb %ymm1, %ymm2, %ymm1 -; GFNIAVX512-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0 -; GFNIAVX512-NEXT: vpshufb %ymm0, %ymm2, %ymm0 -; GFNIAVX512-NEXT: vpaddb %ymm1, %ymm0, %ymm0 +; GFNIAVX512-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX512-NEXT: vpsubb %ymm0, %ymm1, %ymm1 +; GFNIAVX512-NEXT: vpand %ymm1, %ymm0, %ymm0 +; GFNIAVX512-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0 ; GFNIAVX512-NEXT: retq %out = call <32 x i8> @llvm.cttz.v32i8(<32 x i8> %in, i1 -1) ret <32 x i8> %out @@ -272,157 +152,72 @@ define <32 x i8> @testv32i8u(<32 x i8> %in) nounwind { define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { ; GFNISSE-LABEL: testv64i8: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: movdqa %xmm1, %xmm5 -; GFNISSE-NEXT: movdqa %xmm0, %xmm1 -; GFNISSE-NEXT: pcmpeqd %xmm6, %xmm6 -; GFNISSE-NEXT: paddb %xmm6, %xmm0 -; GFNISSE-NEXT: pandn %xmm0, %xmm1 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNISSE-NEXT: movdqa %xmm1, %xmm0 -; GFNISSE-NEXT: pand %xmm7, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNISSE-NEXT: movdqa %xmm4, %xmm9 -; GFNISSE-NEXT: pshufb %xmm0, %xmm9 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm1 -; GFNISSE-NEXT: movdqa %xmm4, %xmm0 -; GFNISSE-NEXT: pshufb %xmm1, %xmm0 -; GFNISSE-NEXT: paddb %xmm9, %xmm0 -; GFNISSE-NEXT: movdqa %xmm5, %xmm1 -; GFNISSE-NEXT: paddb %xmm6, %xmm1 -; GFNISSE-NEXT: pandn %xmm1, %xmm5 -; GFNISSE-NEXT: movdqa %xmm5, %xmm1 -; GFNISSE-NEXT: pand %xmm7, %xmm1 -; GFNISSE-NEXT: movdqa %xmm4, %xmm9 -; GFNISSE-NEXT: pshufb %xmm1, %xmm9 -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm5 -; GFNISSE-NEXT: movdqa %xmm4, %xmm1 -; GFNISSE-NEXT: pshufb %xmm5, %xmm1 -; GFNISSE-NEXT: paddb %xmm9, %xmm1 -; GFNISSE-NEXT: movdqa %xmm2, %xmm5 -; GFNISSE-NEXT: paddb %xmm6, %xmm5 -; GFNISSE-NEXT: pandn %xmm5, %xmm2 -; GFNISSE-NEXT: movdqa %xmm2, %xmm5 -; GFNISSE-NEXT: pand %xmm7, %xmm5 -; GFNISSE-NEXT: movdqa %xmm4, %xmm9 -; GFNISSE-NEXT: pshufb %xmm5, %xmm9 -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm2 -; GFNISSE-NEXT: movdqa %xmm4, %xmm5 -; GFNISSE-NEXT: pshufb %xmm2, %xmm5 -; GFNISSE-NEXT: paddb %xmm9, %xmm5 -; GFNISSE-NEXT: paddb %xmm3, %xmm6 -; GFNISSE-NEXT: pandn %xmm6, %xmm3 -; GFNISSE-NEXT: pand %xmm3, %xmm7 -; GFNISSE-NEXT: movdqa %xmm4, %xmm2 -; GFNISSE-NEXT: pshufb %xmm7, %xmm2 -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm3 -; GFNISSE-NEXT: pshufb %xmm3, %xmm4 -; GFNISSE-NEXT: paddb %xmm2, %xmm4 -; GFNISSE-NEXT: movdqa %xmm5, %xmm2 -; GFNISSE-NEXT: movdqa %xmm4, %xmm3 +; GFNISSE-NEXT: pxor %xmm4, %xmm4 +; GFNISSE-NEXT: pxor %xmm5, %xmm5 +; GFNISSE-NEXT: psubb %xmm0, %xmm5 +; GFNISSE-NEXT: pand %xmm5, %xmm0 +; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm5, %xmm0 +; GFNISSE-NEXT: pxor %xmm6, %xmm6 +; GFNISSE-NEXT: psubb %xmm1, %xmm6 +; GFNISSE-NEXT: pand %xmm6, %xmm1 +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm5, %xmm1 +; GFNISSE-NEXT: pxor %xmm6, %xmm6 +; GFNISSE-NEXT: psubb %xmm2, %xmm6 +; GFNISSE-NEXT: pand %xmm6, %xmm2 +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm5, %xmm2 +; GFNISSE-NEXT: psubb %xmm3, %xmm4 +; GFNISSE-NEXT: pand %xmm4, %xmm3 +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm5, %xmm3 ; GFNISSE-NEXT: retq ; ; GFNIAVX1-LABEL: testv64i8: ; GFNIAVX1: # %bb.0: ; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; GFNIAVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm4 -; GFNIAVX1-NEXT: vpandn %xmm4, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNIAVX1-NEXT: vpand %xmm4, %xmm2, %xmm5 -; GFNIAVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 -; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm7 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNIAVX1-NEXT: # xmm7 = mem[0,0] -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm5 -; GFNIAVX1-NEXT: vpandn %xmm5, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vpand %xmm4, %xmm0, %xmm5 -; GFNIAVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 -; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 -; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm5 -; GFNIAVX1-NEXT: vpandn %xmm5, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpand %xmm4, %xmm2, %xmm5 -; GFNIAVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm3 -; GFNIAVX1-NEXT: vpandn %xmm3, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vpand %xmm4, %xmm1, %xmm3 -; GFNIAVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3 -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 +; GFNIAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; GFNIAVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm2 +; GFNIAVX1-NEXT: vpsubb %xmm0, %xmm3, %xmm4 +; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm4, %ymm2 +; GFNIAVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 +; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] +; GFNIAVX1-NEXT: vgf2p8affineqb $8, %ymm2, %ymm0, %ymm0 +; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 +; GFNIAVX1-NEXT: vpsubb %xmm4, %xmm3, %xmm4 +; GFNIAVX1-NEXT: vpsubb %xmm1, %xmm3, %xmm3 +; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3 +; GFNIAVX1-NEXT: vandps %ymm3, %ymm1, %ymm1 +; GFNIAVX1-NEXT: vgf2p8affineqb $8, %ymm2, %ymm1, %ymm1 ; GFNIAVX1-NEXT: retq ; ; GFNIAVX2-LABEL: testv64i8: ; GFNIAVX2: # %bb.0: -; GFNIAVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 -; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm3 -; GFNIAVX2-NEXT: vpandn %ymm3, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNIAVX2-NEXT: vpand %ymm3, %ymm0, %ymm4 -; GFNIAVX2-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX2-NEXT: # ymm5 = mem[0,1,0,1] -; GFNIAVX2-NEXT: vpshufb %ymm4, %ymm5, %ymm4 -; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm6 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpshufb %ymm0, %ymm5, %ymm0 -; GFNIAVX2-NEXT: vpaddb %ymm4, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm1, %ymm2 -; GFNIAVX2-NEXT: vpandn %ymm2, %ymm1, %ymm1 -; GFNIAVX2-NEXT: vpand %ymm3, %ymm1, %ymm2 -; GFNIAVX2-NEXT: vpshufb %ymm2, %ymm5, %ymm2 -; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm1, %ymm1 -; GFNIAVX2-NEXT: vpshufb %ymm1, %ymm5, %ymm1 -; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm1, %ymm1 +; GFNIAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; GFNIAVX2-NEXT: vpsubb %ymm0, %ymm2, %ymm3 +; GFNIAVX2-NEXT: vpand %ymm3, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] +; GFNIAVX2-NEXT: vgf2p8affineqb $8, %ymm3, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vpsubb %ymm1, %ymm2, %ymm2 +; GFNIAVX2-NEXT: vpand %ymm2, %ymm1, %ymm1 +; GFNIAVX2-NEXT: vgf2p8affineqb $8, %ymm3, %ymm1, %ymm1 ; GFNIAVX2-NEXT: retq ; ; GFNIAVX512VL-LABEL: testv64i8: ; GFNIAVX512VL: # %bb.0: ; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 -; GFNIAVX512VL-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 -; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm1, %ymm3 -; GFNIAVX512VL-NEXT: vpandn %ymm3, %ymm1, %ymm1 -; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNIAVX512VL-NEXT: vpand %ymm3, %ymm1, %ymm4 -; GFNIAVX512VL-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX512VL-NEXT: # ymm5 = mem[0,1,0,1] -; GFNIAVX512VL-NEXT: vpshufb %ymm4, %ymm5, %ymm4 -; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm6 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm6, %ymm1, %ymm1 -; GFNIAVX512VL-NEXT: vpshufb %ymm1, %ymm5, %ymm1 -; GFNIAVX512VL-NEXT: vpaddb %ymm4, %ymm1, %ymm1 -; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm0, %ymm2 -; GFNIAVX512VL-NEXT: vpandn %ymm2, %ymm0, %ymm0 -; GFNIAVX512VL-NEXT: vpand %ymm3, %ymm0, %ymm2 -; GFNIAVX512VL-NEXT: vpshufb %ymm2, %ymm5, %ymm2 -; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm6, %ymm0, %ymm0 -; GFNIAVX512VL-NEXT: vpshufb %ymm0, %ymm5, %ymm0 -; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 +; GFNIAVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; GFNIAVX512VL-NEXT: vpsubb %ymm1, %ymm2, %ymm1 +; GFNIAVX512VL-NEXT: vpsubb %ymm0, %ymm2, %ymm2 +; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1 +; GFNIAVX512VL-NEXT: vpandq %zmm1, %zmm0, %zmm0 +; GFNIAVX512VL-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 ; GFNIAVX512VL-NEXT: retq ; ; GFNIAVX512BW-LABEL: testv64i8: ; GFNIAVX512BW: # %bb.0: -; GFNIAVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = -1 -; GFNIAVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm1 -; GFNIAVX512BW-NEXT: vpandnq %zmm1, %zmm0, %zmm0 -; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm1 -; GFNIAVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; GFNIAVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm1 -; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; GFNIAVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm0 -; GFNIAVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm0 +; GFNIAVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX512BW-NEXT: vpsubb %zmm0, %zmm1, %zmm1 +; GFNIAVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0 +; GFNIAVX512BW-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 ; GFNIAVX512BW-NEXT: retq %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 0) ret <64 x i8> %out @@ -431,157 +226,72 @@ define <64 x i8> @testv64i8(<64 x i8> %in) nounwind { define <64 x i8> @testv64i8u(<64 x i8> %in) nounwind { ; GFNISSE-LABEL: testv64i8u: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: movdqa %xmm1, %xmm5 -; GFNISSE-NEXT: movdqa %xmm0, %xmm1 -; GFNISSE-NEXT: pcmpeqd %xmm6, %xmm6 -; GFNISSE-NEXT: paddb %xmm6, %xmm0 -; GFNISSE-NEXT: pandn %xmm0, %xmm1 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm7 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNISSE-NEXT: movdqa %xmm1, %xmm0 -; GFNISSE-NEXT: pand %xmm7, %xmm0 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNISSE-NEXT: movdqa %xmm4, %xmm9 -; GFNISSE-NEXT: pshufb %xmm0, %xmm9 -; GFNISSE-NEXT: movdqa {{.*#+}} xmm8 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm1 -; GFNISSE-NEXT: movdqa %xmm4, %xmm0 -; GFNISSE-NEXT: pshufb %xmm1, %xmm0 -; GFNISSE-NEXT: paddb %xmm9, %xmm0 -; GFNISSE-NEXT: movdqa %xmm5, %xmm1 -; GFNISSE-NEXT: paddb %xmm6, %xmm1 -; GFNISSE-NEXT: pandn %xmm1, %xmm5 -; GFNISSE-NEXT: movdqa %xmm5, %xmm1 -; GFNISSE-NEXT: pand %xmm7, %xmm1 -; GFNISSE-NEXT: movdqa %xmm4, %xmm9 -; GFNISSE-NEXT: pshufb %xmm1, %xmm9 -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm5 -; GFNISSE-NEXT: movdqa %xmm4, %xmm1 -; GFNISSE-NEXT: pshufb %xmm5, %xmm1 -; GFNISSE-NEXT: paddb %xmm9, %xmm1 -; GFNISSE-NEXT: movdqa %xmm2, %xmm5 -; GFNISSE-NEXT: paddb %xmm6, %xmm5 -; GFNISSE-NEXT: pandn %xmm5, %xmm2 -; GFNISSE-NEXT: movdqa %xmm2, %xmm5 -; GFNISSE-NEXT: pand %xmm7, %xmm5 -; GFNISSE-NEXT: movdqa %xmm4, %xmm9 -; GFNISSE-NEXT: pshufb %xmm5, %xmm9 -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm2 -; GFNISSE-NEXT: movdqa %xmm4, %xmm5 -; GFNISSE-NEXT: pshufb %xmm2, %xmm5 -; GFNISSE-NEXT: paddb %xmm9, %xmm5 -; GFNISSE-NEXT: paddb %xmm3, %xmm6 -; GFNISSE-NEXT: pandn %xmm6, %xmm3 -; GFNISSE-NEXT: pand %xmm3, %xmm7 -; GFNISSE-NEXT: movdqa %xmm4, %xmm2 -; GFNISSE-NEXT: pshufb %xmm7, %xmm2 -; GFNISSE-NEXT: gf2p8affineqb $0, %xmm8, %xmm3 -; GFNISSE-NEXT: pshufb %xmm3, %xmm4 -; GFNISSE-NEXT: paddb %xmm2, %xmm4 -; GFNISSE-NEXT: movdqa %xmm5, %xmm2 -; GFNISSE-NEXT: movdqa %xmm4, %xmm3 +; GFNISSE-NEXT: pxor %xmm4, %xmm4 +; GFNISSE-NEXT: pxor %xmm5, %xmm5 +; GFNISSE-NEXT: psubb %xmm0, %xmm5 +; GFNISSE-NEXT: pand %xmm5, %xmm0 +; GFNISSE-NEXT: movdqa {{.*#+}} xmm5 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm5, %xmm0 +; GFNISSE-NEXT: pxor %xmm6, %xmm6 +; GFNISSE-NEXT: psubb %xmm1, %xmm6 +; GFNISSE-NEXT: pand %xmm6, %xmm1 +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm5, %xmm1 +; GFNISSE-NEXT: pxor %xmm6, %xmm6 +; GFNISSE-NEXT: psubb %xmm2, %xmm6 +; GFNISSE-NEXT: pand %xmm6, %xmm2 +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm5, %xmm2 +; GFNISSE-NEXT: psubb %xmm3, %xmm4 +; GFNISSE-NEXT: pand %xmm4, %xmm3 +; GFNISSE-NEXT: gf2p8affineqb $8, %xmm5, %xmm3 ; GFNISSE-NEXT: retq ; ; GFNIAVX1-LABEL: testv64i8u: ; GFNIAVX1: # %bb.0: ; GFNIAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 -; GFNIAVX1-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm4 -; GFNIAVX1-NEXT: vpandn %xmm4, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vbroadcastss {{.*#+}} xmm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNIAVX1-NEXT: vpand %xmm4, %xmm2, %xmm5 -; GFNIAVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 -; GFNIAVX1-NEXT: vmovddup {{.*#+}} xmm7 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNIAVX1-NEXT: # xmm7 = mem[0,0] -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm0, %xmm5 -; GFNIAVX1-NEXT: vpandn %xmm5, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vpand %xmm4, %xmm0, %xmm5 -; GFNIAVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vpshufb %xmm0, %xmm6, %xmm0 -; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm0, %xmm0 -; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 -; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm5 -; GFNIAVX1-NEXT: vpandn %xmm5, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpand %xmm4, %xmm2, %xmm5 -; GFNIAVX1-NEXT: vpshufb %xmm5, %xmm6, %xmm5 -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpshufb %xmm2, %xmm6, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm5, %xmm2, %xmm2 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm3 -; GFNIAVX1-NEXT: vpandn %xmm3, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vpand %xmm4, %xmm1, %xmm3 -; GFNIAVX1-NEXT: vpshufb %xmm3, %xmm6, %xmm3 -; GFNIAVX1-NEXT: vgf2p8affineqb $0, %xmm7, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vpshufb %xmm1, %xmm6, %xmm1 -; GFNIAVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1 -; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 +; GFNIAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; GFNIAVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm2 +; GFNIAVX1-NEXT: vpsubb %xmm0, %xmm3, %xmm4 +; GFNIAVX1-NEXT: vinsertf128 $1, %xmm2, %ymm4, %ymm2 +; GFNIAVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 +; GFNIAVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] +; GFNIAVX1-NEXT: vgf2p8affineqb $8, %ymm2, %ymm0, %ymm0 +; GFNIAVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 +; GFNIAVX1-NEXT: vpsubb %xmm4, %xmm3, %xmm4 +; GFNIAVX1-NEXT: vpsubb %xmm1, %xmm3, %xmm3 +; GFNIAVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3 +; GFNIAVX1-NEXT: vandps %ymm3, %ymm1, %ymm1 +; GFNIAVX1-NEXT: vgf2p8affineqb $8, %ymm2, %ymm1, %ymm1 ; GFNIAVX1-NEXT: retq ; ; GFNIAVX2-LABEL: testv64i8u: ; GFNIAVX2: # %bb.0: -; GFNIAVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 -; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm3 -; GFNIAVX2-NEXT: vpandn %ymm3, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpbroadcastb {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNIAVX2-NEXT: vpand %ymm3, %ymm0, %ymm4 -; GFNIAVX2-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX2-NEXT: # ymm5 = mem[0,1,0,1] -; GFNIAVX2-NEXT: vpshufb %ymm4, %ymm5, %ymm4 -; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm6 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpshufb %ymm0, %ymm5, %ymm0 -; GFNIAVX2-NEXT: vpaddb %ymm4, %ymm0, %ymm0 -; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm1, %ymm2 -; GFNIAVX2-NEXT: vpandn %ymm2, %ymm1, %ymm1 -; GFNIAVX2-NEXT: vpand %ymm3, %ymm1, %ymm2 -; GFNIAVX2-NEXT: vpshufb %ymm2, %ymm5, %ymm2 -; GFNIAVX2-NEXT: vgf2p8affineqb $0, %ymm6, %ymm1, %ymm1 -; GFNIAVX2-NEXT: vpshufb %ymm1, %ymm5, %ymm1 -; GFNIAVX2-NEXT: vpaddb %ymm2, %ymm1, %ymm1 +; GFNIAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; GFNIAVX2-NEXT: vpsubb %ymm0, %ymm2, %ymm3 +; GFNIAVX2-NEXT: vpand %ymm3, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170,0,0,0,0,255,240,204,170] +; GFNIAVX2-NEXT: vgf2p8affineqb $8, %ymm3, %ymm0, %ymm0 +; GFNIAVX2-NEXT: vpsubb %ymm1, %ymm2, %ymm2 +; GFNIAVX2-NEXT: vpand %ymm2, %ymm1, %ymm1 +; GFNIAVX2-NEXT: vgf2p8affineqb $8, %ymm3, %ymm1, %ymm1 ; GFNIAVX2-NEXT: retq ; ; GFNIAVX512VL-LABEL: testv64i8u: ; GFNIAVX512VL: # %bb.0: ; GFNIAVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 -; GFNIAVX512VL-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2 -; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm1, %ymm3 -; GFNIAVX512VL-NEXT: vpandn %ymm3, %ymm1, %ymm1 -; GFNIAVX512VL-NEXT: vpbroadcastd {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; GFNIAVX512VL-NEXT: vpand %ymm3, %ymm1, %ymm4 -; GFNIAVX512VL-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX512VL-NEXT: # ymm5 = mem[0,1,0,1] -; GFNIAVX512VL-NEXT: vpshufb %ymm4, %ymm5, %ymm4 -; GFNIAVX512VL-NEXT: vpbroadcastq {{.*#+}} ymm6 = [0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16,0,0,0,0,128,64,32,16] -; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm6, %ymm1, %ymm1 -; GFNIAVX512VL-NEXT: vpshufb %ymm1, %ymm5, %ymm1 -; GFNIAVX512VL-NEXT: vpaddb %ymm4, %ymm1, %ymm1 -; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm0, %ymm2 -; GFNIAVX512VL-NEXT: vpandn %ymm2, %ymm0, %ymm0 -; GFNIAVX512VL-NEXT: vpand %ymm3, %ymm0, %ymm2 -; GFNIAVX512VL-NEXT: vpshufb %ymm2, %ymm5, %ymm2 -; GFNIAVX512VL-NEXT: vgf2p8affineqb $0, %ymm6, %ymm0, %ymm0 -; GFNIAVX512VL-NEXT: vpshufb %ymm0, %ymm5, %ymm0 -; GFNIAVX512VL-NEXT: vpaddb %ymm2, %ymm0, %ymm0 -; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0 +; GFNIAVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; GFNIAVX512VL-NEXT: vpsubb %ymm1, %ymm2, %ymm1 +; GFNIAVX512VL-NEXT: vpsubb %ymm0, %ymm2, %ymm2 +; GFNIAVX512VL-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1 +; GFNIAVX512VL-NEXT: vpandq %zmm1, %zmm0, %zmm0 +; GFNIAVX512VL-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 ; GFNIAVX512VL-NEXT: retq ; ; GFNIAVX512BW-LABEL: testv64i8u: ; GFNIAVX512BW: # %bb.0: -; GFNIAVX512BW-NEXT: vpternlogd {{.*#+}} zmm1 = -1 -; GFNIAVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm1 -; GFNIAVX512BW-NEXT: vpandnq %zmm1, %zmm0, %zmm0 -; GFNIAVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm1 -; GFNIAVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} zmm2 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4,0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4] -; GFNIAVX512BW-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3] -; GFNIAVX512BW-NEXT: vpshufb %zmm1, %zmm2, %zmm1 -; GFNIAVX512BW-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; GFNIAVX512BW-NEXT: vpshufb %zmm0, %zmm2, %zmm0 -; GFNIAVX512BW-NEXT: vpaddb %zmm1, %zmm0, %zmm0 +; GFNIAVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; GFNIAVX512BW-NEXT: vpsubb %zmm0, %zmm1, %zmm1 +; GFNIAVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0 +; GFNIAVX512BW-NEXT: vgf2p8affineqb $8, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 ; GFNIAVX512BW-NEXT: retq %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 -1) ret <64 x i8> %out diff --git a/llvm/test/CodeGen/X86/gfni-xor-fold-avx512.ll b/llvm/test/CodeGen/X86/gfni-xor-fold-avx512.ll new file mode 100644 index 0000000000000..bf5dd46579813 --- /dev/null +++ b/llvm/test/CodeGen/X86/gfni-xor-fold-avx512.ll @@ -0,0 +1,63 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512bw,+gfni | FileCheck %s + +declare <64 x i8> @llvm.x86.vgf2p8affineqb.512(<64 x i8>, <64 x i8>, i8) + +define <64 x i8> @test_affine_xor_fold_512(<64 x i8> %src1, <64 x i8> %src2) nounwind { +; +; CHECK-LABEL: test_affine_xor_fold_512: +; CHECK: # %bb.0: +; CHECK-NEXT: vgf2p8affineqb $255, %zmm1, %zmm0, %zmm0 +; CHECK-NEXT: retq + %gfni = call <64 x i8> @llvm.x86.vgf2p8affineqb.512(<64 x i8> %src1, <64 x i8> %src2, i8 0) + %xor = xor <64 x i8> %gfni, splat(i8 -1) + ret <64 x i8> %xor +} + +define <64 x i8> @test_affine_xor_fold_512_nonzero_imm(<64 x i8> %src1, <64 x i8> %src2) nounwind { +; +; CHECK-LABEL: test_affine_xor_fold_512_nonzero_imm: +; CHECK: # %bb.0: +; CHECK-NEXT: vgf2p8affineqb $175, %zmm1, %zmm0, %zmm0 +; CHECK-NEXT: retq + %gfni = call <64 x i8> @llvm.x86.vgf2p8affineqb.512(<64 x i8> %src1, <64 x i8> %src2, i8 5) + %xor = xor <64 x i8> %gfni, splat(i8 -86) + ret <64 x i8> %xor +} + +define <64 x i8> @test_affine_xor_fold_512_commutative(<64 x i8> %src1, <64 x i8> %src2) nounwind { +; +; CHECK-LABEL: test_affine_xor_fold_512_commutative: +; CHECK: # %bb.0: +; CHECK-NEXT: vgf2p8affineqb $255, %zmm1, %zmm0, %zmm0 +; CHECK-NEXT: retq + %gfni = call <64 x i8> @llvm.x86.vgf2p8affineqb.512(<64 x i8> %src1, <64 x i8> %src2, i8 0) + %xor = xor <64 x i8> splat(i8 -1), %gfni + ret <64 x i8> %xor +} + +define <64 x i8> @test_affine_xor_no_fold_512_multi_use(<64 x i8> %src1, <64 x i8> %src2, ptr %out) nounwind { +; +; CHECK-LABEL: test_affine_xor_no_fold_512_multi_use: +; CHECK: # %bb.0: +; CHECK-NEXT: vgf2p8affineqb $0, %zmm1, %zmm0, %zmm0 +; CHECK-NEXT: vmovdqa64 %zmm0, (%rdi) +; CHECK-NEXT: vpternlogq {{.*#+}} zmm0 = ~zmm0 +; CHECK-NEXT: retq + %gfni = call <64 x i8> @llvm.x86.vgf2p8affineqb.512(<64 x i8> %src1, <64 x i8> %src2, i8 0) + store <64 x i8> %gfni, ptr %out + %xor = xor <64 x i8> %gfni, splat(i8 -1) + ret <64 x i8> %xor +} + +define <64 x i8> @test_affine_xor_no_fold_512_variable(<64 x i8> %src1, <64 x i8> %src2, <64 x i8> %var) nounwind { +; +; CHECK-LABEL: test_affine_xor_no_fold_512_variable: +; CHECK: # %bb.0: +; CHECK-NEXT: vgf2p8affineqb $0, %zmm1, %zmm0, %zmm0 +; CHECK-NEXT: vpxorq %zmm2, %zmm0, %zmm0 +; CHECK-NEXT: retq + %gfni = call <64 x i8> @llvm.x86.vgf2p8affineqb.512(<64 x i8> %src1, <64 x i8> %src2, i8 0) + %xor = xor <64 x i8> %gfni, %var + ret <64 x i8> %xor +} diff --git a/llvm/test/CodeGen/X86/gfni-xor-fold.ll b/llvm/test/CodeGen/X86/gfni-xor-fold.ll new file mode 100644 index 0000000000000..510f4cefa4e57 --- /dev/null +++ b/llvm/test/CodeGen/X86/gfni-xor-fold.ll @@ -0,0 +1,144 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-- -mattr=+gfni,+avx | FileCheck %s --check-prefixes=AVX +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+gfni,+avx512bw | FileCheck %s --check-prefixes=AVX512 + +declare <16 x i8> @llvm.x86.vgf2p8affineqb.128(<16 x i8>, <16 x i8>, i8) +declare <32 x i8> @llvm.x86.vgf2p8affineqb.256(<32 x i8>, <32 x i8>, i8) + +define <16 x i8> @test_affine_xor_fold_128(<16 x i8> %src1, <16 x i8> %src2) nounwind { +; +; AVX-LABEL: test_affine_xor_fold_128: +; AVX: # %bb.0: +; AVX-NEXT: vgf2p8affineqb $255, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX512-LABEL: test_affine_xor_fold_128: +; AVX512: # %bb.0: +; AVX512-NEXT: vgf2p8affineqb $255, %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq + %gfni = call <16 x i8> @llvm.x86.vgf2p8affineqb.128(<16 x i8> %src1, <16 x i8> %src2, i8 0) + %xor = xor <16 x i8> %gfni, splat(i8 -1) + ret <16 x i8> %xor +} + +define <16 x i8> @test_affine_xor_fold_nonzero_imm(<16 x i8> %src1, <16 x i8> %src2) nounwind { +; +; AVX-LABEL: test_affine_xor_fold_nonzero_imm: +; AVX: # %bb.0: +; AVX-NEXT: vgf2p8affineqb $175, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX512-LABEL: test_affine_xor_fold_nonzero_imm: +; AVX512: # %bb.0: +; AVX512-NEXT: vgf2p8affineqb $175, %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq + %gfni = call <16 x i8> @llvm.x86.vgf2p8affineqb.128(<16 x i8> %src1, <16 x i8> %src2, i8 5) + %xor = xor <16 x i8> %gfni, splat(i8 -86) + ret <16 x i8> %xor +} + +define <16 x i8> @test_affine_xor_fold_hex(<16 x i8> %src1, <16 x i8> %src2) nounwind { +; +; AVX-LABEL: test_affine_xor_fold_hex: +; AVX: # %bb.0: +; AVX-NEXT: vgf2p8affineqb $83, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX512-LABEL: test_affine_xor_fold_hex: +; AVX512: # %bb.0: +; AVX512-NEXT: vgf2p8affineqb $83, %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq + %gfni = call <16 x i8> @llvm.x86.vgf2p8affineqb.128(<16 x i8> %src1, <16 x i8> %src2, i8 17) + %xor = xor <16 x i8> %gfni, splat(i8 66) + ret <16 x i8> %xor +} + +define <32 x i8> @test_affine_xor_fold_256(<32 x i8> %src1, <32 x i8> %src2) nounwind { +; +; AVX-LABEL: test_affine_xor_fold_256: +; AVX: # %bb.0: +; AVX-NEXT: vgf2p8affineqb $255, %ymm1, %ymm0, %ymm0 +; AVX-NEXT: retq +; +; AVX512-LABEL: test_affine_xor_fold_256: +; AVX512: # %bb.0: +; AVX512-NEXT: vgf2p8affineqb $255, %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: retq + %gfni = call <32 x i8> @llvm.x86.vgf2p8affineqb.256(<32 x i8> %src1, <32 x i8> %src2, i8 0) + %xor = xor <32 x i8> %gfni, splat(i8 -1) + ret <32 x i8> %xor +} + +define <16 x i8> @test_affine_xor_fold_commutative(<16 x i8> %src1, <16 x i8> %src2) nounwind { +; +; AVX-LABEL: test_affine_xor_fold_commutative: +; AVX: # %bb.0: +; AVX-NEXT: vgf2p8affineqb $255, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX512-LABEL: test_affine_xor_fold_commutative: +; AVX512: # %bb.0: +; AVX512-NEXT: vgf2p8affineqb $255, %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq + %gfni = call <16 x i8> @llvm.x86.vgf2p8affineqb.128(<16 x i8> %src1, <16 x i8> %src2, i8 0) + %xor = xor <16 x i8> splat(i8 -1), %gfni + ret <16 x i8> %xor +} + +define <16 x i8> @test_affine_xor_no_fold_multi_use(<16 x i8> %src1, <16 x i8> %src2, ptr %out) nounwind { +; +; AVX-LABEL: test_affine_xor_no_fold_multi_use: +; AVX: # %bb.0: +; AVX-NEXT: vgf2p8affineqb $0, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vmovdqa %xmm0, (%rdi) +; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX512-LABEL: test_affine_xor_no_fold_multi_use: +; AVX512: # %bb.0: +; AVX512-NEXT: vgf2p8affineqb $0, %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa %xmm0, (%rdi) +; AVX512-NEXT: vpternlogq {{.*#+}} xmm0 = ~xmm0 +; AVX512-NEXT: retq + %gfni = call <16 x i8> @llvm.x86.vgf2p8affineqb.128(<16 x i8> %src1, <16 x i8> %src2, i8 0) + store <16 x i8> %gfni, ptr %out + %xor = xor <16 x i8> %gfni, splat(i8 -1) + ret <16 x i8> %xor +} + +define <16 x i8> @test_affine_xor_no_fold_non_splat(<16 x i8> %src1, <16 x i8> %src2) nounwind { +; +; AVX-LABEL: test_affine_xor_no_fold_non_splat: +; AVX: # %bb.0: +; AVX-NEXT: vgf2p8affineqb $0, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX512-LABEL: test_affine_xor_no_fold_non_splat: +; AVX512: # %bb.0: +; AVX512-NEXT: vgf2p8affineqb $0, %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX512-NEXT: retq + %gfni = call <16 x i8> @llvm.x86.vgf2p8affineqb.128(<16 x i8> %src1, <16 x i8> %src2, i8 0) + %xor = xor <16 x i8> %gfni, + ret <16 x i8> %xor +} + +define <16 x i8> @test_affine_xor_no_fold_variable(<16 x i8> %src1, <16 x i8> %src2, <16 x i8> %var) nounwind { +; +; AVX-LABEL: test_affine_xor_no_fold_variable: +; AVX: # %bb.0: +; AVX-NEXT: vgf2p8affineqb $0, %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX-NEXT: retq +; +; AVX512-LABEL: test_affine_xor_no_fold_variable: +; AVX512: # %bb.0: +; AVX512-NEXT: vgf2p8affineqb $0, %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vpxor %xmm2, %xmm0, %xmm0 +; AVX512-NEXT: retq + %gfni = call <16 x i8> @llvm.x86.vgf2p8affineqb.128(<16 x i8> %src1, <16 x i8> %src2, i8 0) + %xor = xor <16 x i8> %gfni, %var + ret <16 x i8> %xor +} diff --git a/llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll b/llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll index b2b0a6dab843f..05b3a639a30e5 100644 --- a/llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll +++ b/llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll @@ -10,7 +10,16 @@ target triple = "x86_64-unknown-linux-gnu" ; RUN: -partition-static-data-sections=true \ ; RUN: -debug-only=static-data-profile-info \ ; RUN: -data-sections=true -unique-section-names=false \ -; RUN: input-with-data-access-prof-on.ll -o - 2>&1 | FileCheck %s --check-prefixes=LOG,IR +; RUN: input-with-data-access-prof-on.ll -o - 2>&1 | FileCheck %s --check-prefixes=LOGCOMMON,IRCOMMON,IR + +;; Repeat command above, but with string literals handled in the codegen pass, +;; with -memprof-annotate-string-literal-section-prefix=true. +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -relocation-model=pic \ +; RUN: -partition-static-data-sections=true \ +; RUN: -debug-only=static-data-profile-info \ +; RUN: -data-sections=true -unique-section-names=false \ +; RUN: -memprof-annotate-string-literal-section-prefix=true \ +; RUN: input-with-data-access-prof-on.ll -o - 2>&1 | FileCheck %s --check-prefixes=LOGCOMMON,LOGSTR,IRCOMMON,IRSTR ; RUN: llc -mtriple=x86_64-unknown-linux-gnu -relocation-model=pic \ ; RUN: -partition-static-data-sections=true \ @@ -18,17 +27,44 @@ target triple = "x86_64-unknown-linux-gnu" ; RUN: -data-sections=true -unique-section-names=false \ ; RUN: input-with-data-access-prof-off.ll -o - 2>&1 | FileCheck %s --check-prefixes=OFF -; LOG: hot_bss has section prefix hot, the max from data access profiles as hot and PGO counters as hot -; LOG: data_unknown_hotness has section prefix , the max from data access profiles as and PGO counters as unlikely -; LOG: external_relro_array has section prefix unlikely, solely from data access profiles +; LOGCOMMON: hot_bss has section prefix hot, the max from data access profiles as hot and PGO counters as hot +; LOGCOMMON: data_unknown_hotness has section prefix , the max from data access profiles as and PGO counters as unlikely + +; LOGSTR: .str has section prefix , the max from data access profiles as and PGO counters as unlikely +; LOGSTR: .str.1 has section prefix hot, the max from data access profiles as unlikely and PGO counters as hot + +; LOGCOMMON: external_relro_array has section prefix unlikely, solely from data access profiles + +; LOGSTR: .str.llvm.98765 has section prefix , solely from data access profiles +; LOGSTR: .str.2 has section prefix hot, solely from data access profiles -; IR: .type hot_bss,@object -; IR-NEXT: .section .bss.hot.,"aw" -; IR: .type data_unknown_hotness,@object -; IR-NEXT: .section .data,"aw" -; IR: .type external_relro_array,@object -; IR-NEXT: .section .data.rel.ro.unlikely.,"aw" +; IRCOMMON: .type hot_bss,@object +; IRCOMMON-NEXT: .section .bss.hot.,"aw" +; IRCOMMON: .type data_unknown_hotness,@object +; IRCOMMON-NEXT: .section .data,"aw" +; IRSTR: .section .rodata,"a",@progbits +; IR: .section .rodata.unlikely.,"a",@progbits +; IRCOMMON-NEXT: .L.str: +; IRCOMMON-NEXT: .ascii "abcde" + +; IRCOMMON: .section .rodata.hot.,"a" +; IRCOMMON-NEXT: .str.1: +; IRCOMMON-NEXT: .ascii "obj.a" + +; IRCOMMON: .type external_relro_array,@object +; IRCOMMON-NEXT: .section .data.rel.ro.unlikely.,"aw" + +; IRCOMMON: .section .rodata,"a",@progbits +; IRCOMMON-NEXT: .globl .str.llvm.98765 +; IRCOMMON-NEXT: .str.llvm.98765: +; IRCOMMON-NEXT: .ascii "Joins" + +; IRSTR: .section .rodata.hot.,"a",@progbits +; IR: .section .rodata,"a",@progbits +; IRSTR-NEXT: .globl .str.2 +; IRSTR-NEXT: .str.2: +; IRSTR-NEXT: .ascii "*ptr != nullptr" ; OFF: .type hot_bss,@object ; OFF-NEXT: .section .bss.hot.,"aw" @@ -36,7 +72,7 @@ target triple = "x86_64-unknown-linux-gnu" ; OFF-NEXT: .section .data.unlikely.,"aw" ;; Global variable section prefix metadata is not used when ;; module flag `EnableDataAccessProf` is 0, and @external_relro_array has -;; external linkage, so analysis based on PGO counters doesn't apply. +;; external linkage, so analysis based on PGO counters doesn't apply. ; OFF: .type external_relro_array,@object # @external_relro_array ; OFF-NEXT: .section .data.rel.ro,"aw" @@ -44,18 +80,25 @@ target triple = "x86_64-unknown-linux-gnu" ; Internal vars @hot_bss = internal global i32 0, !section_prefix !17 @data_unknown_hotness = internal global i32 1 +@.str = private constant [5 x i8] c"abcde" +@.str.1 = internal constant [5 x i8] c"obj.a", !section_prefix !18 ; External vars @external_relro_array = constant [2 x ptr] [ptr @hot_bss, ptr @data_unknown_hotness], !section_prefix !18 +;; -> +@.str.llvm.98765 = constant [5 x i8] c"Joins" + +@.str.2 = constant [15 x i8] c"*ptr != nullptr", !section_prefix !17 + define void @cold_func() !prof !15 { %9 = load i32, ptr @data_unknown_hotness - %11 = call i32 (...) @func_taking_arbitrary_param(i32 %9) + %11 = call i32 (...) @func_taking_arbitrary_param(i32 %9, ptr @.str) ret void } define void @hot_func() !prof !14 { %9 = load i32, ptr @hot_bss - %11 = call i32 (...) @func_taking_arbitrary_param(i32 %9) + %11 = call i32 (...) @func_taking_arbitrary_param(i32 %9, ptr @.str.1) ret void } diff --git a/llvm/test/CodeGen/X86/is_fpclass.ll b/llvm/test/CodeGen/X86/is_fpclass.ll index 97136dafa6c2c..70062b245f36d 100644 --- a/llvm/test/CodeGen/X86/is_fpclass.ll +++ b/llvm/test/CodeGen/X86/is_fpclass.ll @@ -2908,7 +2908,7 @@ declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32) declare <4 x i1> @llvm.is.fpclass.v4f32(<4 x float>, i32) ; Assume DAZ -attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" } +attributes #0 = { denormal_fpenv(ieee|preservesign) } ; Maybe daz -attributes #1 = { "denormal-fp-math"="ieee,dynamic" } +attributes #1 = { denormal_fpenv(ieee|dynamic) } diff --git a/llvm/test/CodeGen/X86/isel-ceil.ll b/llvm/test/CodeGen/X86/isel-ceil.ll index 21df3f1160003..5721752331b5e 100644 --- a/llvm/test/CodeGen/X86/isel-ceil.ll +++ b/llvm/test/CodeGen/X86/isel-ceil.ll @@ -80,10 +80,8 @@ define double @ceil_f64(double %a) nounwind readnone { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll ceil ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-floor.ll b/llvm/test/CodeGen/X86/isel-floor.ll index 66eeee89169ba..acae9b12ce7fc 100644 --- a/llvm/test/CodeGen/X86/isel-floor.ll +++ b/llvm/test/CodeGen/X86/isel-floor.ll @@ -80,10 +80,8 @@ define double @floor_f64(double %a) nounwind readnone { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll floor ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-fpclass.ll b/llvm/test/CodeGen/X86/isel-fpclass.ll index 3a3939fef0f09..0393ae602fd10 100644 --- a/llvm/test/CodeGen/X86/isel-fpclass.ll +++ b/llvm/test/CodeGen/X86/isel-fpclass.ll @@ -102,13 +102,11 @@ define i1 @issignaling_f(float %x) nounwind { ; X64-GISEL: # %bb.0: ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF -; X64-GISEL-NEXT: xorl %ecx, %ecx ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 -; X64-GISEL-NEXT: seta %dl +; X64-GISEL-NEXT: seta %cl ; X64-GISEL-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000 ; X64-GISEL-NEXT: setb %al -; X64-GISEL-NEXT: andb %dl, %al -; X64-GISEL-NEXT: orb %cl, %al +; X64-GISEL-NEXT: andb %cl, %al ; X64-GISEL-NEXT: retq %a0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1) ; "snan" ret i1 %a0 @@ -147,10 +145,8 @@ define i1 @issignaling_f(float %x) nounwind { ; X64-GISEL: # %bb.0: # %entry ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF -; X64-GISEL-NEXT: xorl %ecx, %ecx ; X64-GISEL-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000 ; X64-GISEL-NEXT: setae %al -; X64-GISEL-NEXT: orb %cl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 2) ; "qnan" @@ -190,19 +186,16 @@ define i1 @not_isquiet_f(float %x) nounwind { ; X64-GISEL: # %bb.0: # %entry ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF -; X64-GISEL-NEXT: xorl %ecx, %ecx ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 -; X64-GISEL-NEXT: setb %dl +; X64-GISEL-NEXT: setb %cl +; X64-GISEL-NEXT: sete %dl ; X64-GISEL-NEXT: orb %cl, %dl ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 -; X64-GISEL-NEXT: sete %cl -; X64-GISEL-NEXT: orb %dl, %cl -; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 -; X64-GISEL-NEXT: seta %dl +; X64-GISEL-NEXT: seta %cl ; X64-GISEL-NEXT: cmpl $2143289344, %eax # imm = 0x7FC00000 ; X64-GISEL-NEXT: setb %al -; X64-GISEL-NEXT: andb %dl, %al -; X64-GISEL-NEXT: orb %cl, %al +; X64-GISEL-NEXT: andb %cl, %al +; X64-GISEL-NEXT: orb %dl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 1021) ; ~"qnan" @@ -242,10 +235,8 @@ define i1 @isinf_f(float %x) nounwind { ; X64-GISEL: # %bb.0: # %entry ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF -; X64-GISEL-NEXT: xorl %ecx, %ecx ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 ; X64-GISEL-NEXT: sete %al -; X64-GISEL-NEXT: orb %cl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf" @@ -285,13 +276,10 @@ define i1 @not_isinf_f(float %x) nounwind { ; X64-GISEL: # %bb.0: # %entry ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF -; X64-GISEL-NEXT: xorl %ecx, %ecx -; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 -; X64-GISEL-NEXT: setb %dl -; X64-GISEL-NEXT: orb %cl, %dl ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 +; X64-GISEL-NEXT: setb %cl ; X64-GISEL-NEXT: seta %al -; X64-GISEL-NEXT: orb %dl, %al +; X64-GISEL-NEXT: orb %cl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 507) ; ~0x204 = "~inf" @@ -324,11 +312,9 @@ define i1 @is_plus_inf_f(float %x) nounwind { ; ; X64-GISEL-LABEL: is_plus_inf_f: ; X64-GISEL: # %bb.0: # %entry -; X64-GISEL-NEXT: xorl %ecx, %ecx ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 ; X64-GISEL-NEXT: sete %al -; X64-GISEL-NEXT: orb %cl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 512) ; 0x200 = "+inf" @@ -361,11 +347,9 @@ define i1 @is_minus_inf_f(float %x) nounwind { ; ; X64-GISEL-LABEL: is_minus_inf_f: ; X64-GISEL: # %bb.0: # %entry -; X64-GISEL-NEXT: xorl %ecx, %ecx ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: cmpl $-8388608, %eax # imm = 0xFF800000 ; X64-GISEL-NEXT: sete %al -; X64-GISEL-NEXT: orb %cl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 4) ; "-inf" @@ -401,15 +385,13 @@ define i1 @not_is_minus_inf_f(float %x) nounwind { ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: movl %eax, %ecx ; X64-GISEL-NEXT: andl $2147483647, %ecx # imm = 0x7FFFFFFF -; X64-GISEL-NEXT: xorl %edx, %edx ; X64-GISEL-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000 -; X64-GISEL-NEXT: setb %sil -; X64-GISEL-NEXT: orb %dl, %sil +; X64-GISEL-NEXT: setb %dl ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 -; X64-GISEL-NEXT: sete %dl +; X64-GISEL-NEXT: sete %sil +; X64-GISEL-NEXT: orb %dl, %sil ; X64-GISEL-NEXT: cmpl $2139095040, %ecx # imm = 0x7F800000 ; X64-GISEL-NEXT: seta %al -; X64-GISEL-NEXT: orb %dl, %al ; X64-GISEL-NEXT: orb %sil, %al ; X64-GISEL-NEXT: retq entry: @@ -450,10 +432,8 @@ define i1 @isfinite_f(float %x) nounwind { ; X64-GISEL: # %bb.0: # %entry ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF -; X64-GISEL-NEXT: xorl %ecx, %ecx ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 ; X64-GISEL-NEXT: setb %al -; X64-GISEL-NEXT: orb %cl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite" @@ -493,13 +473,10 @@ define i1 @not_isfinite_f(float %x) nounwind { ; X64-GISEL: # %bb.0: # %entry ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF -; X64-GISEL-NEXT: xorl %ecx, %ecx -; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 -; X64-GISEL-NEXT: sete %dl -; X64-GISEL-NEXT: orb %cl, %dl ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 +; X64-GISEL-NEXT: sete %cl ; X64-GISEL-NEXT: seta %al -; X64-GISEL-NEXT: orb %dl, %al +; X64-GISEL-NEXT: orb %cl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 519) ; ~0x1f8 = "~finite" @@ -532,11 +509,9 @@ define i1 @is_plus_finite_f(float %x) nounwind { ; ; X64-GISEL-LABEL: is_plus_finite_f: ; X64-GISEL: # %bb.0: # %entry -; X64-GISEL-NEXT: xorl %ecx, %ecx ; X64-GISEL-NEXT: movd %xmm0, %eax ; X64-GISEL-NEXT: cmpl $2139095040, %eax # imm = 0x7F800000 ; X64-GISEL-NEXT: setb %al -; X64-GISEL-NEXT: orb %cl, %al ; X64-GISEL-NEXT: retq entry: %0 = tail call i1 @llvm.is.fpclass.f32(float %x, i32 448) ; 0x1c0 = "+finite" diff --git a/llvm/test/CodeGen/X86/isel-ftrunc.ll b/llvm/test/CodeGen/X86/isel-ftrunc.ll index dcdb016d29aca..c2be47ca04567 100644 --- a/llvm/test/CodeGen/X86/isel-ftrunc.ll +++ b/llvm/test/CodeGen/X86/isel-ftrunc.ll @@ -80,10 +80,8 @@ define double @trunc_f64(double %a) nounwind readnone { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll trunc ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-icmp.ll b/llvm/test/CodeGen/X86/isel-icmp.ll index 065d701bab1fd..ce4aba5d14e4d 100644 --- a/llvm/test/CodeGen/X86/isel-icmp.ll +++ b/llvm/test/CodeGen/X86/isel-icmp.ll @@ -747,38 +747,36 @@ define i32 @test_icmp_sge_i96(i96 %a, i96 %b) nounwind { ; ; GISEL-X64-LABEL: test_icmp_sge_i96: ; GISEL-X64: ## %bb.0: -; GISEL-X64-NEXT: movq %rcx, %rax -; GISEL-X64-NEXT: movq %rdi, %r8 -; GISEL-X64-NEXT: movb $32, %cl -; GISEL-X64-NEXT: shlq %cl, %r8 -; GISEL-X64-NEXT: shlq %cl, %rsi -; GISEL-X64-NEXT: shrq %cl, %rdi +; GISEL-X64-NEXT: movq %rdi, %rax +; GISEL-X64-NEXT: shlq $32, %rax +; GISEL-X64-NEXT: shlq $32, %rsi +; GISEL-X64-NEXT: shrq $32, %rdi ; GISEL-X64-NEXT: orq %rsi, %rdi -; GISEL-X64-NEXT: shrq %cl, %r8 +; GISEL-X64-NEXT: shrq $32, %rax ; GISEL-X64-NEXT: movq %rdi, %rsi -; GISEL-X64-NEXT: shlq %cl, %rsi -; GISEL-X64-NEXT: orq %r8, %rsi -; GISEL-X64-NEXT: sarq %cl, %rdi -; GISEL-X64-NEXT: movq %rdx, %rcx -; GISEL-X64-NEXT: shlq $32, %rcx -; GISEL-X64-NEXT: shlq $32, %rax -; GISEL-X64-NEXT: shrq $32, %rdx -; GISEL-X64-NEXT: orq %rax, %rdx -; GISEL-X64-NEXT: shrq $32, %rcx +; GISEL-X64-NEXT: shlq $32, %rsi +; GISEL-X64-NEXT: orq %rax, %rsi +; GISEL-X64-NEXT: sarq $32, %rdi ; GISEL-X64-NEXT: movq %rdx, %rax ; GISEL-X64-NEXT: shlq $32, %rax -; GISEL-X64-NEXT: orq %rcx, %rax +; GISEL-X64-NEXT: shlq $32, %rcx +; GISEL-X64-NEXT: shrq $32, %rdx +; GISEL-X64-NEXT: orq %rcx, %rdx +; GISEL-X64-NEXT: shrq $32, %rax +; GISEL-X64-NEXT: movq %rdx, %rcx +; GISEL-X64-NEXT: shlq $32, %rcx +; GISEL-X64-NEXT: orq %rax, %rcx ; GISEL-X64-NEXT: sarq $32, %rdx -; GISEL-X64-NEXT: xorl %ecx, %ecx -; GISEL-X64-NEXT: cmpq %rax, %rsi -; GISEL-X64-NEXT: setae %cl +; GISEL-X64-NEXT: xorl %r8d, %r8d +; GISEL-X64-NEXT: cmpq %rcx, %rsi +; GISEL-X64-NEXT: setae %r8b ; GISEL-X64-NEXT: xorl %eax, %eax -; GISEL-X64-NEXT: xorl %esi, %esi +; GISEL-X64-NEXT: xorl %ecx, %ecx ; GISEL-X64-NEXT: cmpq %rdx, %rdi ; GISEL-X64-NEXT: setge %al -; GISEL-X64-NEXT: sete %sil -; GISEL-X64-NEXT: testl %esi, %esi -; GISEL-X64-NEXT: cmovnew %cx, %ax +; GISEL-X64-NEXT: sete %cl +; GISEL-X64-NEXT: testl %ecx, %ecx +; GISEL-X64-NEXT: cmovnew %r8w, %ax ; GISEL-X64-NEXT: andl $1, %eax ; GISEL-X64-NEXT: retq ; @@ -833,21 +831,17 @@ define i32 @test_icmp_sge_i96(i96 %a, i96 %b) nounwind { ; ; GISEL-X86-LABEL: test_icmp_sge_i96: ; GISEL-X86: ## %bb.0: -; GISEL-X86-NEXT: pushl %ebp ; GISEL-X86-NEXT: pushl %ebx ; GISEL-X86-NEXT: pushl %edi ; GISEL-X86-NEXT: pushl %esi -; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edi -; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %esi -; GISEL-X86-NEXT: movl %edx, %eax -; GISEL-X86-NEXT: movb $31, %cl -; GISEL-X86-NEXT: sarl %cl, %eax -; GISEL-X86-NEXT: cmpl %edi, {{[0-9]+}}(%esp) +; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; GISEL-X86-NEXT: cmpl %ecx, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setae %ch ; GISEL-X86-NEXT: xorl %ebx, %ebx -; GISEL-X86-NEXT: cmpl %ebp, {{[0-9]+}}(%esp) +; GISEL-X86-NEXT: cmpl %esi, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: setae %cl ; GISEL-X86-NEXT: sete %bl ; GISEL-X86-NEXT: testl %ebx, %ebx @@ -855,32 +849,33 @@ define i32 @test_icmp_sge_i96(i96 %a, i96 %b) nounwind { ; GISEL-X86-NEXT: ## %bb.1: ; GISEL-X86-NEXT: movb %ch, %cl ; GISEL-X86-NEXT: LBB13_2: -; GISEL-X86-NEXT: movl %esi, %edi +; GISEL-X86-NEXT: movl %eax, %esi +; GISEL-X86-NEXT: sarl $31, %esi +; GISEL-X86-NEXT: movl %edx, %edi ; GISEL-X86-NEXT: sarl $31, %edi ; GISEL-X86-NEXT: xorl %ebx, %ebx -; GISEL-X86-NEXT: cmpl %esi, %edx -; GISEL-X86-NEXT: setae %dl +; GISEL-X86-NEXT: cmpl %edx, %eax +; GISEL-X86-NEXT: setae %al ; GISEL-X86-NEXT: sete %bl ; GISEL-X86-NEXT: testl %ebx, %ebx ; GISEL-X86-NEXT: je LBB13_4 ; GISEL-X86-NEXT: ## %bb.3: -; GISEL-X86-NEXT: movl %ecx, %edx +; GISEL-X86-NEXT: movl %ecx, %eax ; GISEL-X86-NEXT: LBB13_4: -; GISEL-X86-NEXT: xorl %ecx, %ecx -; GISEL-X86-NEXT: cmpl %edi, %eax -; GISEL-X86-NEXT: setge %al -; GISEL-X86-NEXT: sete %cl -; GISEL-X86-NEXT: testl %ecx, %ecx +; GISEL-X86-NEXT: xorl %edx, %edx +; GISEL-X86-NEXT: cmpl %edi, %esi +; GISEL-X86-NEXT: setge %cl +; GISEL-X86-NEXT: sete %dl +; GISEL-X86-NEXT: testl %edx, %edx ; GISEL-X86-NEXT: je LBB13_6 ; GISEL-X86-NEXT: ## %bb.5: -; GISEL-X86-NEXT: movl %edx, %eax +; GISEL-X86-NEXT: movl %eax, %ecx ; GISEL-X86-NEXT: LBB13_6: -; GISEL-X86-NEXT: movzbl %al, %eax +; GISEL-X86-NEXT: movzbl %cl, %eax ; GISEL-X86-NEXT: andl $1, %eax ; GISEL-X86-NEXT: popl %esi ; GISEL-X86-NEXT: popl %edi ; GISEL-X86-NEXT: popl %ebx -; GISEL-X86-NEXT: popl %ebp ; GISEL-X86-NEXT: retl %r = icmp sge i96 %a, %b %res = zext i1 %r to i32 diff --git a/llvm/test/CodeGen/X86/isel-llvm.acos.ll b/llvm/test/CodeGen/X86/isel-llvm.acos.ll index 9176cf47bda78..9fc63ffeed8d5 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.acos.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.acos.ll @@ -57,10 +57,8 @@ define double @use_acosf64(double %a) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll acos ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-llvm.asin.ll b/llvm/test/CodeGen/X86/isel-llvm.asin.ll index 87ffcc9c963c2..111303b0e9058 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.asin.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.asin.ll @@ -57,10 +57,8 @@ define double @use_asinf64(double %a) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll asin ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-llvm.atan.ll b/llvm/test/CodeGen/X86/isel-llvm.atan.ll index c03361d18c1d2..910b58393e186 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.atan.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.atan.ll @@ -57,10 +57,8 @@ define double @use_atanf64(double %a) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll atan ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-llvm.atan2.ll b/llvm/test/CodeGen/X86/isel-llvm.atan2.ll index aa56068e17780..2f43cd001b122 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.atan2.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.atan2.ll @@ -59,27 +59,23 @@ define double @use_atan2f64(double %a, double %b) nounwind { ; ; GISEL-X86-LABEL: use_atan2f64: ; GISEL-X86: # %bb.0: -; GISEL-X86-NEXT: pushl %edi ; GISEL-X86-NEXT: pushl %esi -; GISEL-X86-NEXT: subl $20, %esp +; GISEL-X86-NEXT: subl $24, %esp ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %edx ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; GISEL-X86-NEXT: movl 4(%edx), %edx -; GISEL-X86-NEXT: xorl %edi, %edi -; GISEL-X86-NEXT: addl %esp, %edi ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edi) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: movl $8, %eax ; GISEL-X86-NEXT: addl %esp, %eax ; GISEL-X86-NEXT: movl %esi, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: movl %edx, 4(%eax) ; GISEL-X86-NEXT: calll atan2 -; GISEL-X86-NEXT: addl $20, %esp +; GISEL-X86-NEXT: addl $24, %esp ; GISEL-X86-NEXT: popl %esi -; GISEL-X86-NEXT: popl %edi ; GISEL-X86-NEXT: retl ; ; GISEL-X64-LABEL: use_atan2f64: diff --git a/llvm/test/CodeGen/X86/isel-llvm.cos.ll b/llvm/test/CodeGen/X86/isel-llvm.cos.ll index af039854d3491..0abaaec87699f 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.cos.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.cos.ll @@ -57,10 +57,8 @@ define double @test_cos_f64(double %Val) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll cos ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-llvm.cosh.ll b/llvm/test/CodeGen/X86/isel-llvm.cosh.ll index a61867c11fd41..c665f84bf1377 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.cosh.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.cosh.ll @@ -57,10 +57,8 @@ define double @use_coshf64(double %a) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll cosh ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll b/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll index d271e97d8832a..859c6d1965b68 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll @@ -117,10 +117,7 @@ define void @func_02() nounwind { ; GISEL-X86-NOSSE: # %bb.0: ; GISEL-X86-NOSSE-NEXT: pushl %eax ; GISEL-X86-NOSSE-NEXT: fnstcw (%esp) -; GISEL-X86-NOSSE-NEXT: movw $-3073, %ax # imm = 0xF3FF -; GISEL-X86-NOSSE-NEXT: andw (%esp), %ax -; GISEL-X86-NOSSE-NEXT: orw $0, %ax -; GISEL-X86-NOSSE-NEXT: movw %ax, (%esp) +; GISEL-X86-NOSSE-NEXT: andw $-3073, (%esp) # imm = 0xF3FF ; GISEL-X86-NOSSE-NEXT: fldcw (%esp) ; GISEL-X86-NOSSE-NEXT: popl %eax ; GISEL-X86-NOSSE-NEXT: retl @@ -135,10 +132,7 @@ define void @func_02() nounwind { ; GISEL-X64-NOSSE-LABEL: func_02: ; GISEL-X64-NOSSE: # %bb.0: ; GISEL-X64-NOSSE-NEXT: fnstcw -{{[0-9]+}}(%rsp) -; GISEL-X64-NOSSE-NEXT: movw $-3073, %ax # imm = 0xF3FF -; GISEL-X64-NOSSE-NEXT: andw -{{[0-9]+}}(%rsp), %ax -; GISEL-X64-NOSSE-NEXT: orw $0, %ax -; GISEL-X64-NOSSE-NEXT: movw %ax, -{{[0-9]+}}(%rsp) +; GISEL-X64-NOSSE-NEXT: andw $-3073, -{{[0-9]+}}(%rsp) # imm = 0xF3FF ; GISEL-X64-NOSSE-NEXT: fldcw -{{[0-9]+}}(%rsp) ; GISEL-X64-NOSSE-NEXT: retq ; @@ -155,10 +149,7 @@ define void @func_02() nounwind { ; GISEL-X86: # %bb.0: ; GISEL-X86-NEXT: pushl %eax ; GISEL-X86-NEXT: fnstcw (%esp) -; GISEL-X86-NEXT: movw $-3073, %ax # imm = 0xF3FF -; GISEL-X86-NEXT: andw (%esp), %ax -; GISEL-X86-NEXT: orw $0, %ax -; GISEL-X86-NEXT: movw %ax, (%esp) +; GISEL-X86-NEXT: andw $-3073, (%esp) # imm = 0xF3FF ; GISEL-X86-NEXT: fldcw (%esp) ; GISEL-X86-NEXT: popl %eax ; GISEL-X86-NEXT: retl @@ -176,16 +167,10 @@ define void @func_02() nounwind { ; GISEL-X64-LABEL: func_02: ; GISEL-X64: # %bb.0: ; GISEL-X64-NEXT: fnstcw -{{[0-9]+}}(%rsp) -; GISEL-X64-NEXT: movw $-3073, %ax # imm = 0xF3FF -; GISEL-X64-NEXT: andw -{{[0-9]+}}(%rsp), %ax -; GISEL-X64-NEXT: orw $0, %ax -; GISEL-X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp) +; GISEL-X64-NEXT: andw $-3073, -{{[0-9]+}}(%rsp) # imm = 0xF3FF ; GISEL-X64-NEXT: fldcw -{{[0-9]+}}(%rsp) ; GISEL-X64-NEXT: stmxcsr -{{[0-9]+}}(%rsp) -; GISEL-X64-NEXT: movl $-24577, %eax # imm = 0x9FFF -; GISEL-X64-NEXT: andl -{{[0-9]+}}(%rsp), %eax -; GISEL-X64-NEXT: orl $0, %eax -; GISEL-X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; GISEL-X64-NEXT: andl $-24577, -{{[0-9]+}}(%rsp) # imm = 0x9FFF ; GISEL-X64-NEXT: ldmxcsr -{{[0-9]+}}(%rsp) ; GISEL-X64-NEXT: retq call void @llvm.set.rounding(i32 1) ; ToNearestTiesToEven (CW[11-10] = 00) diff --git a/llvm/test/CodeGen/X86/isel-llvm.sin.ll b/llvm/test/CodeGen/X86/isel-llvm.sin.ll index 0f17f83d01023..559a104863928 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.sin.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.sin.ll @@ -57,10 +57,8 @@ define double @test_sin_f64(double %Val) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll sin ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-llvm.sinh.ll b/llvm/test/CodeGen/X86/isel-llvm.sinh.ll index ef30f8de06953..6bd7cfbb301cb 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.sinh.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.sinh.ll @@ -57,10 +57,8 @@ define double @use_sinhf64(double %a) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll sinh ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-llvm.tan.ll b/llvm/test/CodeGen/X86/isel-llvm.tan.ll index 4e76653cd1299..4b51d208bfadd 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.tan.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.tan.ll @@ -57,10 +57,8 @@ define double @use_tanf64(double %a) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll tan ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-llvm.tanh.ll b/llvm/test/CodeGen/X86/isel-llvm.tanh.ll index c4f6e2f179cf9..29a7cbfb99af5 100644 --- a/llvm/test/CodeGen/X86/isel-llvm.tanh.ll +++ b/llvm/test/CodeGen/X86/isel-llvm.tanh.ll @@ -57,10 +57,8 @@ define double @use_tanhf64(double %a) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll tanh ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/isel-or.ll b/llvm/test/CodeGen/X86/isel-or.ll index 449f29a027743..8b191c007675c 100644 --- a/llvm/test/CodeGen/X86/isel-or.ll +++ b/llvm/test/CodeGen/X86/isel-or.ll @@ -335,10 +335,9 @@ define i64 @or_imm8_i64(i64 %a) { ; ; GISEL-X86-LABEL: or_imm8_i64: ; GISEL-X86: # %bb.0: +; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; GISEL-X86-NEXT: movl $1, %eax -; GISEL-X86-NEXT: xorl %edx, %edx ; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax -; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx ; GISEL-X86-NEXT: retl ; ; X64-LABEL: or_imm8_i64: @@ -441,9 +440,8 @@ define i64 @or_imm16_i64(i64 %a) { ; GISEL-X86-LABEL: or_imm16_i64: ; GISEL-X86: # %bb.0: ; GISEL-X86-NEXT: movl $-5022, %eax # imm = 0xEC62 -; GISEL-X86-NEXT: movl $-1, %edx ; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax -; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx +; GISEL-X86-NEXT: movl $-1, %edx ; GISEL-X86-NEXT: retl ; ; X64-LABEL: or_imm16_i64: @@ -501,9 +499,8 @@ define i64 @or_imm32_i64(i64 %a) { ; GISEL-X86-LABEL: or_imm32_i64: ; GISEL-X86: # %bb.0: ; GISEL-X86-NEXT: movl $-125778, %eax # imm = 0xFFFE14AE -; GISEL-X86-NEXT: movl $-1, %edx ; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %eax -; GISEL-X86-NEXT: orl {{[0-9]+}}(%esp), %edx +; GISEL-X86-NEXT: movl $-1, %edx ; GISEL-X86-NEXT: retl ; ; X64-LABEL: or_imm32_i64: diff --git a/llvm/test/CodeGen/X86/isel-xor.ll b/llvm/test/CodeGen/X86/isel-xor.ll index a31ad78524ee1..0549a6436a1a4 100644 --- a/llvm/test/CodeGen/X86/isel-xor.ll +++ b/llvm/test/CodeGen/X86/isel-xor.ll @@ -335,10 +335,9 @@ define i64 @xor_imm8_i64(i64 %a) { ; ; GISEL-X86-LABEL: xor_imm8_i64: ; GISEL-X86: # %bb.0: +; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; GISEL-X86-NEXT: movl $1, %eax -; GISEL-X86-NEXT: xorl %edx, %edx ; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %eax -; GISEL-X86-NEXT: xorl {{[0-9]+}}(%esp), %edx ; GISEL-X86-NEXT: retl ; ; X64-LABEL: xor_imm8_i64: diff --git a/llvm/test/CodeGen/X86/known-bits.ll b/llvm/test/CodeGen/X86/known-bits.ll index dbcc8eceeb037..58a0595e4322a 100644 --- a/llvm/test/CodeGen/X86/known-bits.ll +++ b/llvm/test/CodeGen/X86/known-bits.ll @@ -7,8 +7,7 @@ define void @knownbits_zext_in_reg(ptr) nounwind { ; X86: # %bb.0: # %BB ; X86-NEXT: pushl %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: movzbl (%eax), %eax -; X86-NEXT: movzwl %ax, %ecx +; X86-NEXT: movzbl (%eax), %ecx ; X86-NEXT: imull $101, %ecx, %eax ; X86-NEXT: shrl $14, %eax ; X86-NEXT: imull $177, %ecx, %edx @@ -32,7 +31,6 @@ define void @knownbits_zext_in_reg(ptr) nounwind { ; X64-LABEL: knownbits_zext_in_reg: ; X64: # %bb.0: # %BB ; X64-NEXT: movzbl (%rdi), %eax -; X64-NEXT: movzwl %ax, %eax ; X64-NEXT: imull $101, %eax, %ecx ; X64-NEXT: shrl $14, %ecx ; X64-NEXT: imull $177, %eax, %edx diff --git a/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll b/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll index 2cf37c68b8b40..1799dd3832aad 100644 --- a/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll +++ b/llvm/test/CodeGen/X86/legalize-vec-assertzext.ll @@ -23,7 +23,7 @@ define i64 @widen_assertzext(ptr %x) nounwind { ; CHECK-NEXT: callq test2@PLT ; CHECK-NEXT: movb $127, %al ; CHECK-NEXT: kmovw %eax, %k1 -; CHECK-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} +; CHECK-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm0 ; CHECK-NEXT: vmovq %xmm0, %rax ; CHECK-NEXT: popq %rcx @@ -41,7 +41,7 @@ define i64 @widen_assertzext_range_attr(ptr %x) nounwind { ; CHECK-NEXT: callq test2@PLT ; CHECK-NEXT: movb $127, %al ; CHECK-NEXT: kmovw %eax, %k1 -; CHECK-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} +; CHECK-NEXT: vmovdqa64 %zmm0, %zmm0 {%k1} {z} ; CHECK-NEXT: vextracti32x4 $3, %zmm0, %xmm0 ; CHECK-NEXT: vmovq %xmm0, %rax ; CHECK-NEXT: popq %rcx diff --git a/llvm/test/CodeGen/X86/llc-pipeline-npm.ll b/llvm/test/CodeGen/X86/llc-pipeline-npm.ll index 8425af01b0330..3b1992388ff63 100644 --- a/llvm/test/CodeGen/X86/llc-pipeline-npm.ll +++ b/llvm/test/CodeGen/X86/llc-pipeline-npm.ll @@ -55,6 +55,7 @@ ; O0-NEXT: fentry-insert ; O0-NEXT: xray-instrumentation ; O0-NEXT: patchable-function +; O0-NEXT: x86-indirect-branch-tracking ; O0-NEXT: x86-compress-evex ; O0-NEXT: FuncletLayoutPass ; O0-NEXT: remove-loads-into-fake-uses @@ -64,6 +65,7 @@ ; O0-NEXT: stack-frame-layout ; O0-NEXT: x86-seses ; O0-NEXT: x86-return-thunks +; O0-NEXT: x86-lvi-ret ; O0-NEXT: verify) ; O0-NEXT: free-machine-function) @@ -102,6 +104,7 @@ ; O2-NEXT: stack-protector ; O2-NEXT: verify) ; O2-NEXT: function(machine-function(x86-isel +; O2-NEXT: x86-cleanup-local-dynamic-tls ; O2-NEXT: x86-argument-stack-slot ; O2-NEXT: finalize-isel ; O2-NEXT: early-tailduplication @@ -144,7 +147,7 @@ ; O2-NEXT: machinelicm ; O2-NEXT: x86-lower-tile-copy ; O2-NEXT: x86-fp-stackifier -; O2-NEXT: x86-lvi-ret +; O2-NEXT: x86-lvi-load ; O2-NEXT: remove-redundant-debug-values ; O2-NEXT: fixup-statepoint-caller-saved ; O2-NEXT: postra-machine-sink @@ -162,6 +165,7 @@ ; O2-NEXT: xray-instrumentation ; O2-NEXT: patchable-function ; O2-NEXT: BreakFalseDepsPass +; O2-NEXT: x86-indirect-branch-tracking ; O2-NEXT: x86-fixup-bw-insts ; O2-NEXT: x86-fixup-leas ; O2-NEXT: x86-fixup-inst-tuning @@ -175,6 +179,7 @@ ; O2-NEXT: stack-frame-layout ; O2-NEXT: x86-seses ; O2-NEXT: x86-return-thunks +; O2-NEXT: x86-lvi-ret ; O2-NEXT: verify) ; O2-NEXT: free-machine-function) @@ -225,6 +230,7 @@ ; O0-WINDOWS-NEXT: fentry-insert ; O0-WINDOWS-NEXT: xray-instrumentation ; O0-WINDOWS-NEXT: patchable-function +; O0-WINDOWS-NEXT: x86-indirect-branch-tracking ; O0-WINDOWS-NEXT: x86-compress-evex ; O0-WINDOWS-NEXT: FuncletLayoutPass ; O0-WINDOWS-NEXT: remove-loads-into-fake-uses @@ -235,6 +241,8 @@ ; O0-WINDOWS-NEXT: x86-seses ; O0-WINDOWS-NEXT: x86-return-thunks ; O0-WINDOWS-NEXT: x86-avoid-trailing-call +; O0-WINDOWS-NEXT: x86-lvi-ret +; O0-WINDOWS-NEXT: x86-wineh-unwindv2 ; O0-WINDOWS-NEXT: verify) ; O0-WINDOWS-NEXT: free-machine-function) @@ -317,7 +325,7 @@ ; O3-WINDOWS-NEXT: machinelicm ; O3-WINDOWS-NEXT: x86-lower-tile-copy ; O3-WINDOWS-NEXT: x86-fp-stackifier -; O3-WINDOWS-NEXT: x86-lvi-ret +; O3-WINDOWS-NEXT: x86-lvi-load ; O3-WINDOWS-NEXT: remove-redundant-debug-values ; O3-WINDOWS-NEXT: fixup-statepoint-caller-saved ; O3-WINDOWS-NEXT: postra-machine-sink @@ -335,6 +343,7 @@ ; O3-WINDOWS-NEXT: xray-instrumentation ; O3-WINDOWS-NEXT: patchable-function ; O3-WINDOWS-NEXT: BreakFalseDepsPass +; O3-WINDOWS-NEXT: x86-indirect-branch-tracking ; O3-WINDOWS-NEXT: x86-fixup-bw-insts ; O3-WINDOWS-NEXT: x86-fixup-leas ; O3-WINDOWS-NEXT: x86-fixup-inst-tuning @@ -349,5 +358,7 @@ ; O3-WINDOWS-NEXT: x86-seses ; O3-WINDOWS-NEXT: x86-return-thunks ; O3-WINDOWS-NEXT: x86-avoid-trailing-call +; O3-WINDOWS-NEXT: x86-lvi-ret +; O3-WINDOWS-NEXT: x86-wineh-unwindv2 ; O3-WINDOWS-NEXT: verify) ; O3-WINDOWS-NEXT: free-machine-function) diff --git a/llvm/test/CodeGen/X86/llround-conv.ll b/llvm/test/CodeGen/X86/llround-conv.ll index 83151ebf9af07..93fec71b6eccc 100644 --- a/llvm/test/CodeGen/X86/llround-conv.ll +++ b/llvm/test/CodeGen/X86/llround-conv.ll @@ -133,10 +133,8 @@ define i64 @test_llround_f64(double %x) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll llround ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl @@ -363,10 +361,8 @@ define i64 @test_llround_i64_f64(double %x) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll llround ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/lround-conv-i32.ll b/llvm/test/CodeGen/X86/lround-conv-i32.ll index 73abbee86880f..4e95da14b45a1 100644 --- a/llvm/test/CodeGen/X86/lround-conv-i32.ll +++ b/llvm/test/CodeGen/X86/lround-conv-i32.ll @@ -112,10 +112,8 @@ define i32 @test_lround_i32_f64(double %x) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll lround ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/lround-conv-i64.ll b/llvm/test/CodeGen/X86/lround-conv-i64.ll index 81f01cc27eb14..0002bb8936d5d 100644 --- a/llvm/test/CodeGen/X86/lround-conv-i64.ll +++ b/llvm/test/CodeGen/X86/lround-conv-i64.ll @@ -135,10 +135,8 @@ define i64 @test_lround_i64_f64(double %x) nounwind { ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax -; GISEL-X86-NEXT: xorl %edx, %edx -; GISEL-X86-NEXT: addl %esp, %edx ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%edx) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll lround ; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll index 57b0577ac7cc9..f56dabc99f595 100644 --- a/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll +++ b/llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll @@ -340,15 +340,15 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; -; AVX512-LABEL: truncstore_v8i64_v8i32: -; AVX512: # %bb.0: -; AVX512-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 -; AVX512-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512-NEXT: vpmovqd %zmm0, (%rdi) {%k1} -; AVX512-NEXT: vzeroupper -; AVX512-NEXT: retq +; AVX512F-LABEL: truncstore_v8i64_v8i32: +; AVX512F: # %bb.0: +; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 +; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k1 +; AVX512F-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 +; AVX512F-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 +; AVX512F-NEXT: vpmovqd %zmm0, (%rdi) {%k1} +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq ; ; AVX512FVL-LABEL: truncstore_v8i64_v8i32: ; AVX512FVL: # %bb.0: @@ -359,6 +359,14 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq ; +; AVX512BW-LABEL: truncstore_v8i64_v8i32: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 +; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 +; AVX512BW-NEXT: vpmovsqd %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq +; ; AVX512BWVL-LABEL: truncstore_v8i64_v8i32: ; AVX512BWVL: # %bb.0: ; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1 @@ -962,9 +970,7 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovqw %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovsqw %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1568,9 +1574,7 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovqb %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovsqb %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -3815,9 +3819,7 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512BW-LABEL: truncstore_v16i32_v16i16: ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovdw %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovsdw %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -4591,9 +4593,7 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512BW-LABEL: truncstore_v16i32_v16i8: ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovdb %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovsdb %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -7319,9 +7319,7 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512BW-NEXT: vptestmb %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 -; AVX512BW-NEXT: vpmaxsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovwb %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovswb %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll index 0386d9531723d..d214fb694252f 100644 --- a/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll +++ b/llvm/test/CodeGen/X86/masked_store_trunc_usat.ll @@ -272,14 +272,14 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq ; -; AVX512-LABEL: truncstore_v8i64_v8i32: -; AVX512: # %bb.0: -; AVX512-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 -; AVX512-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512-NEXT: vpmovqd %zmm0, (%rdi) {%k1} -; AVX512-NEXT: vzeroupper -; AVX512-NEXT: retq +; AVX512F-LABEL: truncstore_v8i64_v8i32: +; AVX512F: # %bb.0: +; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 +; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k1 +; AVX512F-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 +; AVX512F-NEXT: vpmovqd %zmm0, (%rdi) {%k1} +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq ; ; AVX512FVL-LABEL: truncstore_v8i64_v8i32: ; AVX512FVL: # %bb.0: @@ -289,6 +289,14 @@ define void @truncstore_v8i64_v8i32(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512FVL-NEXT: vzeroupper ; AVX512FVL-NEXT: retq ; +; AVX512BW-LABEL: truncstore_v8i64_v8i32: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 +; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 +; AVX512BW-NEXT: vpmovusqd %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq +; ; AVX512BWVL-LABEL: truncstore_v8i64_v8i32: ; AVX512BWVL: # %bb.0: ; AVX512BWVL-NEXT: vptestmd %ymm1, %ymm1, %k1 @@ -828,8 +836,7 @@ define void @truncstore_v8i64_v8i16(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovqw %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovusqw %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1365,8 +1372,7 @@ define void @truncstore_v8i64_v8i8(<8 x i64> %x, ptr %p, <8 x i32> %mask) { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovqb %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovusqb %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -3463,8 +3469,7 @@ define void @truncstore_v16i32_v16i16(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512BW-LABEL: truncstore_v16i32_v16i16: ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovdw %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovusdw %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -4278,8 +4283,7 @@ define void @truncstore_v16i32_v16i8(<16 x i32> %x, ptr %p, <16 x i32> %mask) { ; AVX512BW-LABEL: truncstore_v16i32_v16i8: ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: vptestmd %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovdb %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovusdb %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -7171,8 +7175,7 @@ define void @truncstore_v32i16_v32i8(<32 x i16> %x, ptr %p, <32 x i8> %mask) { ; AVX512BW: # %bb.0: ; AVX512BW-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512BW-NEXT: vptestmb %zmm1, %zmm1, %k1 -; AVX512BW-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 -; AVX512BW-NEXT: vpmovwb %zmm0, (%rdi) {%k1} +; AVX512BW-NEXT: vpmovuswb %zmm0, (%rdi) {%k1} ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/opt_phis2.mir b/llvm/test/CodeGen/X86/opt_phis2.mir index 421a986d2601b..dedeb741e053c 100644 --- a/llvm/test/CodeGen/X86/opt_phis2.mir +++ b/llvm/test/CodeGen/X86/opt_phis2.mir @@ -29,7 +29,7 @@ body: | %13:gr32 = ADD32rr %7, killed %12, implicit-def dead $eflags %14:gr32 = AND32ri8 %13, -4, implicit-def dead $eflags %15:gr32 = SUB32rr %7, %14, implicit-def dead $eflags - %10:gr64_nosp = SUBREG_TO_REG 0, %15, %subreg.sub_32bit + %10:gr64_nosp = SUBREG_TO_REG %15, %subreg.sub_32bit %16:gr32 = SUB32ri8 %15, 3, implicit-def $eflags JCC_1 %bb.8, 7, implicit $eflags diff --git a/llvm/test/CodeGen/X86/peephole-test-after-add.mir b/llvm/test/CodeGen/X86/peephole-test-after-add.mir index 675c8f4720bc9..0490bf8e508b6 100644 --- a/llvm/test/CodeGen/X86/peephole-test-after-add.mir +++ b/llvm/test/CodeGen/X86/peephole-test-after-add.mir @@ -116,7 +116,7 @@ body: | ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY2]], 3, implicit-def $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[AND32ri8_]], %subreg.sub_32bit ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY]], 4, implicit $eflags ; CHECK-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0) ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] @@ -126,7 +126,7 @@ body: | %3:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) %4:gr32 = COPY %3.sub_32bit %5:gr32 = AND32ri8 %4, 3, implicit-def dead $eflags - %6:gr64 = SUBREG_TO_REG 0, killed %5, %subreg.sub_32bit + %6:gr64 = SUBREG_TO_REG killed %5, %subreg.sub_32bit TEST64rr %6, %6, implicit-def $eflags %7:gr64 = CMOV64rr %6, %1, 4, implicit $eflags MOV64mr %0, 1, $noreg, 0, $noreg, killed %7 :: (store (s64) into %ir.0) @@ -164,7 +164,7 @@ body: | ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY2]], 3, implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[AND32ri8_]], %subreg.sub_32bit ; CHECK-NEXT: TEST64rr [[SUBREG_TO_REG]], [[SUBREG_TO_REG]], implicit-def $eflags ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY]], 8, implicit $eflags ; CHECK-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0) @@ -175,7 +175,7 @@ body: | %4:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) %5:gr32 = COPY %4.sub_32bit %6:gr32 = AND32ri8 %5, 3, implicit-def dead $eflags - %7:gr64 = SUBREG_TO_REG 0, killed %6, %subreg.sub_32bit + %7:gr64 = SUBREG_TO_REG killed %6, %subreg.sub_32bit TEST64rr %7, %7, implicit-def $eflags %8:gr64 = CMOV64rr %7, %1, 8, implicit $eflags MOV64mr %0, 1, $noreg, 0, $noreg, killed %8 :: (store (s64) into %ir.0) @@ -219,7 +219,7 @@ body: | ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY3]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit ; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY4]], 3, implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[AND32ri8_]], %subreg.sub_32bit ; CHECK-NEXT: [[XOR64ri8_:%[0-9]+]]:gr64 = XOR64ri8 [[COPY1]], 5, implicit-def dead $eflags ; CHECK-NEXT: TEST64rr [[SUBREG_TO_REG]], [[SUBREG_TO_REG]], implicit-def $eflags ; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY2]], 4, implicit $eflags @@ -233,7 +233,7 @@ body: | %5:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0) %6:gr32 = COPY %5.sub_32bit %7:gr32 = AND32ri8 %6, 3, implicit-def dead $eflags - %8:gr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32bit + %8:gr64 = SUBREG_TO_REG killed %7, %subreg.sub_32bit %9:gr64 = XOR64ri8 %3, 5, implicit-def dead $eflags TEST64rr %8, %8, implicit-def $eflags %10:gr64 = CMOV64rr %8, %1, 4, implicit $eflags diff --git a/llvm/test/CodeGen/X86/peephole.mir b/llvm/test/CodeGen/X86/peephole.mir index 28ce9f1f0e827..efcb1582e19cc 100644 --- a/llvm/test/CodeGen/X86/peephole.mir +++ b/llvm/test/CodeGen/X86/peephole.mir @@ -30,11 +30,11 @@ body: | ; CHECK: %4:fr32 = VMOVDI2SSrr %3 ; CHECK-NOT: COPY ; CHECK: %5:gr32 = MOVSS2DIrr %4 - ; CHECK: %6:gr64 = SUBREG_TO_REG %5, 0 + ; CHECK: %6:gr64 = SUBREG_TO_REG %5, %subreg.sub_32bit ; CHECK: NOOP implicit %6 %3 = MOV32ri 42 %4 = VMOVDI2SSrr %3 %5 = MOVSS2DIrr %4 - %6 = SUBREG_TO_REG %5, 0, %subreg.sub_32bit + %6 = SUBREG_TO_REG %5, %subreg.sub_32bit NOOP implicit %6 ... diff --git a/llvm/test/CodeGen/X86/pow.ll b/llvm/test/CodeGen/X86/pow.ll index b3a5268460aa3..c2f7eb66ab01c 100644 --- a/llvm/test/CodeGen/X86/pow.ll +++ b/llvm/test/CodeGen/X86/pow.ll @@ -222,4 +222,4 @@ define double @pow_f64_not_enough_fmf(double %x) nounwind { ret double %r } -attributes #0 = { nounwind "denormal-fp-math"="ieee,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(ieee|preservesign) } diff --git a/llvm/test/CodeGen/X86/powi.ll b/llvm/test/CodeGen/X86/powi.ll index 4420d0499a5d0..9446cc071c1fc 100644 --- a/llvm/test/CodeGen/X86/powi.ll +++ b/llvm/test/CodeGen/X86/powi.ll @@ -86,20 +86,16 @@ define double @test_powi_f64_i32(double %Val, i32 %x) nounwind { ; ; GISEL-X86-LABEL: test_powi_f64_i32: ; GISEL-X86: # %bb.0: -; GISEL-X86-NEXT: pushl %esi -; GISEL-X86-NEXT: subl $24, %esp +; GISEL-X86-NEXT: subl $12, %esp ; GISEL-X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; GISEL-X86-NEXT: movl 4(%eax), %eax ; GISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; GISEL-X86-NEXT: xorl %esi, %esi -; GISEL-X86-NEXT: addl %esp, %esi ; GISEL-X86-NEXT: movl %ecx, (%esp) -; GISEL-X86-NEXT: movl %eax, 4(%esi) +; GISEL-X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: movl %edx, {{[0-9]+}}(%esp) ; GISEL-X86-NEXT: calll __powidf2 -; GISEL-X86-NEXT: addl $24, %esp -; GISEL-X86-NEXT: popl %esi +; GISEL-X86-NEXT: addl $12, %esp ; GISEL-X86-NEXT: retl ; ; FAST-X64-LABEL: test_powi_f64_i32: diff --git a/llvm/test/CodeGen/X86/pr142937.ll b/llvm/test/CodeGen/X86/pr142937.ll index 8be99e102ff5b..675bb9ea52189 100644 --- a/llvm/test/CodeGen/X86/pr142937.ll +++ b/llvm/test/CodeGen/X86/pr142937.ll @@ -1,19 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc < %s -mtriple=i686-- -O0 | FileCheck %s --check-prefix=X86 -; RUN: llc < %s -mtriple=x86_64-- -O0 | FileCheck %s --check-prefix=X64 +; RUN: not llc %s -mtriple=i686-- -O0 -filetype=null 2>&1 | FileCheck %s +; RUN: not llc %s -mtriple=x86_64-- -O0 -filetype=null 2>&1 | FileCheck %s + +; CHECK: must be lowered by the LowerTypeTests pass define void @public_type_test() { -; X86-LABEL: public_type_test: -; X86: # %bb.0: # %bb -; X86-NEXT: movb $1, %al -; X86-NEXT: # %bb.1: # %bb1 -; X86-NEXT: retl -; -; X64-LABEL: public_type_test: -; X64: # %bb.0: # %bb -; X64-NEXT: movb $1, %al -; X64-NEXT: # %bb.1: # %bb1 -; X64-NEXT: retq bb: %call = call i1 @llvm.public.type.test(ptr null, metadata !"typeinfo") br label %bb1 @@ -24,25 +15,6 @@ bb1: } define void @type_test() { -; X86-LABEL: type_test: -; X86: # %bb.0: # %bb -; X86-NEXT: movb $1, %al -; X86-NEXT: testb $1, %al -; X86-NEXT: jne .LBB1_2 -; X86-NEXT: # %bb.1: # %bb1 -; X86-NEXT: ud1l 2(%eax), %eax -; X86-NEXT: .LBB1_2: # %bb2 -; X86-NEXT: retl -; -; X64-LABEL: type_test: -; X64: # %bb.0: # %bb -; X64-NEXT: movb $1, %al -; X64-NEXT: testb $1, %al -; X64-NEXT: jne .LBB1_2 -; X64-NEXT: # %bb.1: # %bb1 -; X64-NEXT: ud1l 2(%eax), %eax -; X64-NEXT: .LBB1_2: # %bb2 -; X64-NEXT: retq bb: %call = tail call i1 @llvm.type.test(ptr null, metadata !"typeinfo") br i1 %call, label %bb2, label %bb1 @@ -56,9 +28,6 @@ bb2: } declare i1 @llvm.public.type.test(ptr, metadata) - declare void @llvm.assume(i1 noundef) - declare i1 @llvm.type.test(ptr, metadata) - declare void @llvm.ubsantrap(i8 immarg) diff --git a/llvm/test/CodeGen/X86/pr179489.ll b/llvm/test/CodeGen/X86/pr179489.ll new file mode 100644 index 0000000000000..e59261e00719f --- /dev/null +++ b/llvm/test/CodeGen/X86/pr179489.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx10.2 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx10.2 | FileCheck %s --check-prefix=X64 + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write) +declare void @llvm.masked.store.v8i8.p1(<8 x i8>, ptr addrspace(1) captures(none), <8 x i1>) #0 + +define void @foo(<8 x i16> %arg, ptr addrspace(1) %add.ptr) { +; X86-LABEL: foo: +; X86: # %bb.0: # %entry +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vmovw %xmm0, %ecx +; X86-NEXT: movb %ch, (%eax) +; X86-NEXT: retl +; +; X64-LABEL: foo: +; X64: # %bb.0: # %entry +; X64-NEXT: vmovw %xmm0, %eax +; X64-NEXT: movb %ah, (%rdi) +; X64-NEXT: retq +entry: + %i3 = shufflevector <8 x i16> %arg, <8 x i16> , <8 x i32> + %i4 = lshr <8 x i16> %i3, splat (i16 8) + %i5 = trunc <8 x i16> %i4 to <8 x i8> + call void @llvm.masked.store.v8i8.p1(<8 x i8> %i5, ptr addrspace(1) %add.ptr, <8 x i1> ) + ret void +} + +define void @bar(<8 x i64> %arg, ptr addrspace(1) %add.ptr) { +; X86-LABEL: bar: +; X86: # %bb.0: # %entry +; X86-NEXT: vpbroadcastd {{.*#+}} zmm1 = [257,257,257,257,257,257,257,257,257,257,257,257,257,257,257,257] +; X86-NEXT: movb $2, %al +; X86-NEXT: kmovd %eax, %k1 +; X86-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: vpsrlq $16, %zmm1, %zmm0 +; X86-NEXT: vpmovqb %zmm0, (%eax) {%k1} +; X86-NEXT: vzeroupper +; X86-NEXT: retl +; +; X64-LABEL: bar: +; X64: # %bb.0: # %entry +; X64-NEXT: vpextrq $1, %xmm0, %rax +; X64-NEXT: shrl $16, %eax +; X64-NEXT: movb %al, 1(%rdi) +; X64-NEXT: vzeroupper +; X64-NEXT: retq +entry: + %i3 = shufflevector <8 x i64> %arg, <8 x i64> , <8 x i32> + %i4 = lshr <8 x i64> %i3, splat (i64 16) + %i5 = trunc <8 x i64> %i4 to <8 x i8> + call void @llvm.masked.store.v8i8.p1(<8 x i8> %i5, ptr addrspace(1) %add.ptr, <8 x i1> ) + ret void +} + +attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) } diff --git a/llvm/test/CodeGen/X86/pr57673.ll b/llvm/test/CodeGen/X86/pr57673.ll index 24862539ca637..4cb8450e85c25 100644 --- a/llvm/test/CodeGen/X86/pr57673.ll +++ b/llvm/test/CodeGen/X86/pr57673.ll @@ -46,7 +46,7 @@ define void @foo() { ; NORMAL-NEXT: successors: %bb.1(0x80000000) ; NORMAL-NEXT: {{ $}} ; NORMAL-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp - ; NORMAL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32r0_1]], %subreg.sub_32bit + ; NORMAL-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32r0_1]], %subreg.sub_32bit ; NORMAL-NEXT: $rdi = COPY [[SUBREG_TO_REG]] ; NORMAL-NEXT: $rsi = COPY [[SUBREG_TO_REG]] ; NORMAL-NEXT: $rdx = COPY [[SUBREG_TO_REG]] @@ -86,7 +86,7 @@ define void @foo() { ; INSTRREF-NEXT: successors: %bb.1(0x80000000) ; INSTRREF-NEXT: {{ $}} ; INSTRREF-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp - ; INSTRREF-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32r0_1]], %subreg.sub_32bit + ; INSTRREF-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG [[MOV32r0_1]], %subreg.sub_32bit ; INSTRREF-NEXT: $rdi = COPY [[SUBREG_TO_REG]] ; INSTRREF-NEXT: $rsi = COPY [[SUBREG_TO_REG]] ; INSTRREF-NEXT: $rdx = COPY [[SUBREG_TO_REG]] diff --git a/llvm/test/CodeGen/X86/rdpru.ll b/llvm/test/CodeGen/X86/rdpru.ll index be79a4499a338..067ae31142c39 100644 --- a/llvm/test/CodeGen/X86/rdpru.ll +++ b/llvm/test/CodeGen/X86/rdpru.ll @@ -7,6 +7,7 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 -fast-isel | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 -fast-isel | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 -fast-isel | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 -fast-isel | FileCheck %s --check-prefix=X64 define void @rdpru_asm() { ; X86-LABEL: rdpru_asm: diff --git a/llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir b/llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir index 143b6864b1191..1325af8a46b3b 100644 --- a/llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir +++ b/llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir @@ -24,14 +24,14 @@ body: | ; CHECK: successors: %bb.3(0x80000000) ; CHECK: $rcx = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %stack.1) ; CHECK: renamable $eax = MOV32r0 implicit-def dead $eflags - ; CHECK: renamable $rax = SUBREG_TO_REG 0, killed renamable $eax, %subreg.sub_32bit + ; CHECK: renamable $rax = SUBREG_TO_REG killed renamable $eax, %subreg.sub_32bit ; CHECK: MOV64mi32 killed renamable $rcx, 1, $noreg, 0, $noreg, 0 :: (volatile store (s64)) ; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed $rax :: (store (s64) into %stack.0) ; CHECK: bb.3: ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: $rax = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %stack.0) ; CHECK: renamable $ecx = MOV32r0 implicit-def dead $eflags - ; CHECK: renamable $rcx = SUBREG_TO_REG 0, killed renamable $ecx, %subreg.sub_32bit + ; CHECK: renamable $rcx = SUBREG_TO_REG killed renamable $ecx, %subreg.sub_32bit ; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, killed $rcx :: (store (s64) into %stack.1) ; CHECK: JMP64r killed renamable $rax bb.0: @@ -50,7 +50,7 @@ body: | bb.2: %0:gr64 = COPY %12 %10:gr32 = MOV32r0 implicit-def $eflags - %11:gr64 = SUBREG_TO_REG 0, %10, %subreg.sub_32bit + %11:gr64 = SUBREG_TO_REG %10, %subreg.sub_32bit MOV64mi32 %0, 1, $noreg, 0, $noreg, 0 :: (volatile store (s64)) %13:gr64 = COPY %11 @@ -59,7 +59,7 @@ body: | %1:gr64 = COPY %13 %9:gr32 = MOV32r0 implicit-def dead $eflags - %8:gr64 = SUBREG_TO_REG 0, killed %9, %subreg.sub_32bit + %8:gr64 = SUBREG_TO_REG killed %9, %subreg.sub_32bit %12:gr64 = COPY %8 JMP64r %1 diff --git a/llvm/test/CodeGen/X86/select-big-integer.ll b/llvm/test/CodeGen/X86/select-big-integer.ll new file mode 100644 index 0000000000000..b7f4a57b01338 --- /dev/null +++ b/llvm/test/CodeGen/X86/select-big-integer.ll @@ -0,0 +1,459 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE,SSE4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=knl | FileCheck %s --check-prefixes=AVX512F +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512VL + +; +; LOGIC +; + +define void @test_not_i128(ptr %p0, ptr %p1, i1 zeroext %a2, ptr %p3) nounwind { +; SSE2-LABEL: test_not_i128: +; SSE2: # %bb.0: +; SSE2-NEXT: negl %edx +; SSE2-NEXT: movd %edx, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] +; SSE2-NEXT: movdqa (%rdi), %xmm1 +; SSE2-NEXT: pand %xmm0, %xmm1 +; SSE2-NEXT: por (%rsi), %xmm0 +; SSE2-NEXT: pcmpeqd %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm0, %xmm2 +; SSE2-NEXT: por %xmm1, %xmm2 +; SSE2-NEXT: movdqa %xmm2, (%rcx) +; SSE2-NEXT: retq +; +; SSE4-LABEL: test_not_i128: +; SSE4: # %bb.0: +; SSE4-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE4-NEXT: pxor (%rsi), %xmm1 +; SSE4-NEXT: negl %edx +; SSE4-NEXT: movd %edx, %xmm0 +; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] +; SSE4-NEXT: blendvps %xmm0, (%rdi), %xmm1 +; SSE4-NEXT: movaps %xmm1, (%rcx) +; SSE4-NEXT: retq +; +; AVX1-LABEL: test_not_i128: +; AVX1: # %bb.0: +; AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX1-NEXT: vpxor (%rsi), %xmm0, %xmm0 +; AVX1-NEXT: negl %edx +; AVX1-NEXT: vmovd %edx, %xmm1 +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0] +; AVX1-NEXT: vblendvps %xmm1, (%rdi), %xmm0, %xmm0 +; AVX1-NEXT: vmovaps %xmm0, (%rcx) +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_not_i128: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX2-NEXT: vpxor (%rsi), %xmm0, %xmm0 +; AVX2-NEXT: negl %edx +; AVX2-NEXT: vmovd %edx, %xmm1 +; AVX2-NEXT: vpbroadcastd %xmm1, %xmm1 +; AVX2-NEXT: vblendvps %xmm1, (%rdi), %xmm0, %xmm0 +; AVX2-NEXT: vmovaps %xmm0, (%rcx) +; AVX2-NEXT: retq +; +; AVX512F-LABEL: test_not_i128: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 +; AVX512F-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpxor (%rsi), %xmm1, %xmm1 +; AVX512F-NEXT: negb %dl +; AVX512F-NEXT: kmovw %edx, %k1 +; AVX512F-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqa %xmm1, (%rcx) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_not_i128: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512VL-NEXT: vpxor (%rsi), %xmm0, %xmm0 +; AVX512VL-NEXT: negb %dl +; AVX512VL-NEXT: kmovd %edx, %k1 +; AVX512VL-NEXT: vmovdqa32 (%rdi), %xmm0 {%k1} +; AVX512VL-NEXT: vmovdqa %xmm0, (%rcx) +; AVX512VL-NEXT: retq + %ld0 = load i128, ptr %p0 + %ld1 = load i128, ptr %p1 + %neg1 = xor i128 %ld1, -1 + %sel = select i1 %a2, i128 %ld0, i128 %neg1 + store i128 %sel, ptr %p3 + ret void +} + +define void @test_not_i256(ptr %p0, ptr %p1, i1 zeroext %a2, ptr %p3) nounwind { +; SSE2-LABEL: test_not_i256: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa (%rsi), %xmm0 +; SSE2-NEXT: movdqa 16(%rsi), %xmm1 +; SSE2-NEXT: negl %edx +; SSE2-NEXT: movd %edx, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0] +; SSE2-NEXT: movdqa (%rdi), %xmm3 +; SSE2-NEXT: pand %xmm2, %xmm3 +; SSE2-NEXT: pcmpeqd %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm2, %xmm4 +; SSE2-NEXT: pandn %xmm4, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 +; SSE2-NEXT: pand 16(%rdi), %xmm2 +; SSE2-NEXT: pandn %xmm4, %xmm1 +; SSE2-NEXT: por %xmm2, %xmm1 +; SSE2-NEXT: movdqa %xmm1, 16(%rcx) +; SSE2-NEXT: movdqa %xmm0, (%rcx) +; SSE2-NEXT: retq +; +; SSE4-LABEL: test_not_i256: +; SSE4: # %bb.0: +; SSE4-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE4-NEXT: movdqa 16(%rsi), %xmm2 +; SSE4-NEXT: pxor %xmm1, %xmm2 +; SSE4-NEXT: pxor (%rsi), %xmm1 +; SSE4-NEXT: negl %edx +; SSE4-NEXT: movd %edx, %xmm0 +; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] +; SSE4-NEXT: blendvps %xmm0, (%rdi), %xmm1 +; SSE4-NEXT: blendvps %xmm0, 16(%rdi), %xmm2 +; SSE4-NEXT: movaps %xmm2, 16(%rcx) +; SSE4-NEXT: movaps %xmm1, (%rcx) +; SSE4-NEXT: retq +; +; AVX1-LABEL: test_not_i256: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovaps (%rdi), %xmm0 +; AVX1-NEXT: vmovaps (%rsi), %xmm1 +; AVX1-NEXT: vinsertf128 $1, 16(%rsi), %ymm1, %ymm1 +; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2 +; AVX1-NEXT: vxorps %ymm2, %ymm1, %ymm1 +; AVX1-NEXT: negl %edx +; AVX1-NEXT: vmovd %edx, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,0,0] +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 +; AVX1-NEXT: vblendvps %xmm2, 16(%rdi), %xmm3, %xmm3 +; AVX1-NEXT: vmovaps %xmm3, 16(%rcx) +; AVX1-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vmovaps %xmm0, (%rcx) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_not_i256: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vpxor (%rsi), %ymm0, %ymm0 +; AVX2-NEXT: negl %edx +; AVX2-NEXT: vmovd %edx, %xmm1 +; AVX2-NEXT: vpbroadcastd %xmm1, %ymm1 +; AVX2-NEXT: vblendvps %ymm1, (%rdi), %ymm0, %ymm0 +; AVX2-NEXT: vmovups %ymm0, (%rcx) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512F-LABEL: test_not_i256: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqu (%rdi), %ymm0 +; AVX512F-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; AVX512F-NEXT: vpxor (%rsi), %ymm1, %ymm1 +; AVX512F-NEXT: negb %dl +; AVX512F-NEXT: kmovw %edx, %k1 +; AVX512F-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu %ymm1, (%rcx) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_not_i256: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 +; AVX512VL-NEXT: vpxor (%rsi), %ymm0, %ymm0 +; AVX512VL-NEXT: negb %dl +; AVX512VL-NEXT: kmovd %edx, %k1 +; AVX512VL-NEXT: vmovdqu32 (%rdi), %ymm0 {%k1} +; AVX512VL-NEXT: vmovdqu %ymm0, (%rcx) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq + %ld0 = load i256, ptr %p0 + %ld1 = load i256, ptr %p1 + %neg1 = xor i256 %ld1, -1 + %sel = select i1 %a2, i256 %ld0, i256 %neg1 + store i256 %sel, ptr %p3 + ret void +} + +define void @test_not_i512(ptr %p0, ptr %p1, i1 zeroext %a2, ptr %p3) nounwind { +; SSE2-LABEL: test_not_i512: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa (%rsi), %xmm3 +; SSE2-NEXT: movdqa 16(%rsi), %xmm2 +; SSE2-NEXT: movdqa 32(%rsi), %xmm1 +; SSE2-NEXT: movdqa 48(%rsi), %xmm0 +; SSE2-NEXT: negl %edx +; SSE2-NEXT: movd %edx, %xmm4 +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,0,0] +; SSE2-NEXT: movdqa 48(%rdi), %xmm5 +; SSE2-NEXT: pand %xmm4, %xmm5 +; SSE2-NEXT: pcmpeqd %xmm6, %xmm6 +; SSE2-NEXT: pxor %xmm4, %xmm6 +; SSE2-NEXT: pandn %xmm6, %xmm0 +; SSE2-NEXT: por %xmm5, %xmm0 +; SSE2-NEXT: movdqa 32(%rdi), %xmm5 +; SSE2-NEXT: pand %xmm4, %xmm5 +; SSE2-NEXT: pandn %xmm6, %xmm1 +; SSE2-NEXT: por %xmm5, %xmm1 +; SSE2-NEXT: movdqa 16(%rdi), %xmm5 +; SSE2-NEXT: pand %xmm4, %xmm5 +; SSE2-NEXT: pandn %xmm6, %xmm2 +; SSE2-NEXT: por %xmm5, %xmm2 +; SSE2-NEXT: pand (%rdi), %xmm4 +; SSE2-NEXT: pandn %xmm6, %xmm3 +; SSE2-NEXT: por %xmm4, %xmm3 +; SSE2-NEXT: movdqa %xmm3, (%rcx) +; SSE2-NEXT: movdqa %xmm2, 16(%rcx) +; SSE2-NEXT: movdqa %xmm1, 32(%rcx) +; SSE2-NEXT: movdqa %xmm0, 48(%rcx) +; SSE2-NEXT: retq +; +; SSE4-LABEL: test_not_i512: +; SSE4: # %bb.0: +; SSE4-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE4-NEXT: movdqa (%rsi), %xmm2 +; SSE4-NEXT: pxor %xmm1, %xmm2 +; SSE4-NEXT: movdqa 16(%rsi), %xmm3 +; SSE4-NEXT: pxor %xmm1, %xmm3 +; SSE4-NEXT: movdqa 32(%rsi), %xmm4 +; SSE4-NEXT: pxor %xmm1, %xmm4 +; SSE4-NEXT: pxor 48(%rsi), %xmm1 +; SSE4-NEXT: negl %edx +; SSE4-NEXT: movd %edx, %xmm0 +; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] +; SSE4-NEXT: blendvps %xmm0, 48(%rdi), %xmm1 +; SSE4-NEXT: blendvps %xmm0, 32(%rdi), %xmm4 +; SSE4-NEXT: blendvps %xmm0, 16(%rdi), %xmm3 +; SSE4-NEXT: blendvps %xmm0, (%rdi), %xmm2 +; SSE4-NEXT: movaps %xmm2, (%rcx) +; SSE4-NEXT: movaps %xmm3, 16(%rcx) +; SSE4-NEXT: movaps %xmm4, 32(%rcx) +; SSE4-NEXT: movaps %xmm1, 48(%rcx) +; SSE4-NEXT: retq +; +; AVX1-LABEL: test_not_i512: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovaps (%rdi), %xmm0 +; AVX1-NEXT: vmovaps (%rsi), %xmm1 +; AVX1-NEXT: vmovaps 32(%rsi), %xmm2 +; AVX1-NEXT: vinsertf128 $1, 48(%rsi), %ymm2, %ymm2 +; AVX1-NEXT: vinsertf128 $1, 16(%rsi), %ymm1, %ymm1 +; AVX1-NEXT: vmovaps 16(%rdi), %xmm3 +; AVX1-NEXT: vxorps %xmm4, %xmm4, %xmm4 +; AVX1-NEXT: vcmptrueps %ymm4, %ymm4, %ymm4 +; AVX1-NEXT: vxorps %ymm4, %ymm1, %ymm1 +; AVX1-NEXT: vxorps %ymm4, %ymm2, %ymm2 +; AVX1-NEXT: negl %edx +; AVX1-NEXT: vmovd %edx, %xmm4 +; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,0,0,0] +; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm5 +; AVX1-NEXT: vblendvps %xmm4, 48(%rdi), %xmm5, %xmm5 +; AVX1-NEXT: vmovaps 32(%rdi), %xmm6 +; AVX1-NEXT: vmovaps %xmm5, 48(%rcx) +; AVX1-NEXT: vblendvps %xmm4, %xmm6, %xmm2, %xmm2 +; AVX1-NEXT: vmovaps %xmm2, 32(%rcx) +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vblendvps %xmm4, %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vmovaps %xmm2, 16(%rcx) +; AVX1-NEXT: vblendvps %xmm4, %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vmovaps %xmm0, (%rcx) +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_not_i512: +; AVX2: # %bb.0: +; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vpxor 32(%rsi), %ymm0, %ymm1 +; AVX2-NEXT: vpxor (%rsi), %ymm0, %ymm0 +; AVX2-NEXT: negl %edx +; AVX2-NEXT: vmovd %edx, %xmm2 +; AVX2-NEXT: vpbroadcastd %xmm2, %ymm2 +; AVX2-NEXT: vblendvps %ymm2, (%rdi), %ymm0, %ymm0 +; AVX2-NEXT: vblendvps %ymm2, 32(%rdi), %ymm1, %ymm1 +; AVX2-NEXT: vmovups %ymm1, 32(%rcx) +; AVX2-NEXT: vmovups %ymm0, (%rcx) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512F-LABEL: test_not_i512: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm0 = -1 +; AVX512F-NEXT: vpxord (%rsi), %zmm0, %zmm0 +; AVX512F-NEXT: negl %edx +; AVX512F-NEXT: kmovw %edx, %k1 +; AVX512F-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm0, (%rcx) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_not_i512: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm0 = -1 +; AVX512VL-NEXT: vpxord (%rsi), %zmm0, %zmm0 +; AVX512VL-NEXT: negl %edx +; AVX512VL-NEXT: kmovd %edx, %k1 +; AVX512VL-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1} +; AVX512VL-NEXT: vmovdqu64 %zmm0, (%rcx) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq + %ld0 = load i512, ptr %p0 + %ld1 = load i512, ptr %p1 + %neg1 = xor i512 %ld1, -1 + %sel = select i1 %a2, i512 %ld0, i512 %neg1 + store i512 %sel, ptr %p3 + ret void +} + +; +; ADD/SUB +; + +define void @test_neg_i512(ptr %p0, ptr %p1, i1 zeroext %a2, ptr %p3) nounwind { +; SSE-LABEL: test_neg_i512: +; SSE: # %bb.0: +; SSE-NEXT: pushq %r15 +; SSE-NEXT: pushq %r14 +; SSE-NEXT: pushq %rbx +; SSE-NEXT: xorl %r8d, %r8d +; SSE-NEXT: xorl %r10d, %r10d +; SSE-NEXT: subq (%rsi), %r10 +; SSE-NEXT: movl $0, %eax +; SSE-NEXT: sbbq 8(%rsi), %rax +; SSE-NEXT: movl $0, %ebx +; SSE-NEXT: sbbq 16(%rsi), %rbx +; SSE-NEXT: movl $0, %r9d +; SSE-NEXT: sbbq 24(%rsi), %r9 +; SSE-NEXT: movl $0, %r14d +; SSE-NEXT: sbbq 32(%rsi), %r14 +; SSE-NEXT: movl $0, %r11d +; SSE-NEXT: sbbq 40(%rsi), %r11 +; SSE-NEXT: movl $0, %r15d +; SSE-NEXT: sbbq 48(%rsi), %r15 +; SSE-NEXT: sbbq 56(%rsi), %r8 +; SSE-NEXT: testl %edx, %edx +; SSE-NEXT: je .LBB3_2 +; SSE-NEXT: # %bb.1: +; SSE-NEXT: movq 8(%rdi), %rax +; SSE-NEXT: movq 24(%rdi), %r9 +; SSE-NEXT: movq 40(%rdi), %r11 +; SSE-NEXT: movq 56(%rdi), %r8 +; SSE-NEXT: movq (%rdi), %r10 +; SSE-NEXT: movq 16(%rdi), %rbx +; SSE-NEXT: movq 32(%rdi), %r14 +; SSE-NEXT: movq 48(%rdi), %r15 +; SSE-NEXT: .LBB3_2: +; SSE-NEXT: movq %r15, 48(%rcx) +; SSE-NEXT: movq %r14, 32(%rcx) +; SSE-NEXT: movq %rbx, 16(%rcx) +; SSE-NEXT: movq %r10, (%rcx) +; SSE-NEXT: movq %r8, 56(%rcx) +; SSE-NEXT: movq %r11, 40(%rcx) +; SSE-NEXT: movq %r9, 24(%rcx) +; SSE-NEXT: movq %rax, 8(%rcx) +; SSE-NEXT: popq %rbx +; SSE-NEXT: popq %r14 +; SSE-NEXT: popq %r15 +; SSE-NEXT: retq +; +; AVX-LABEL: test_neg_i512: +; AVX: # %bb.0: +; AVX-NEXT: pushq %r15 +; AVX-NEXT: pushq %r14 +; AVX-NEXT: pushq %rbx +; AVX-NEXT: xorl %r8d, %r8d +; AVX-NEXT: xorl %r10d, %r10d +; AVX-NEXT: subq (%rsi), %r10 +; AVX-NEXT: movl $0, %eax +; AVX-NEXT: sbbq 8(%rsi), %rax +; AVX-NEXT: movl $0, %ebx +; AVX-NEXT: sbbq 16(%rsi), %rbx +; AVX-NEXT: movl $0, %r9d +; AVX-NEXT: sbbq 24(%rsi), %r9 +; AVX-NEXT: movl $0, %r14d +; AVX-NEXT: sbbq 32(%rsi), %r14 +; AVX-NEXT: movl $0, %r11d +; AVX-NEXT: sbbq 40(%rsi), %r11 +; AVX-NEXT: movl $0, %r15d +; AVX-NEXT: sbbq 48(%rsi), %r15 +; AVX-NEXT: sbbq 56(%rsi), %r8 +; AVX-NEXT: testl %edx, %edx +; AVX-NEXT: je .LBB3_2 +; AVX-NEXT: # %bb.1: +; AVX-NEXT: movq 8(%rdi), %rax +; AVX-NEXT: movq 24(%rdi), %r9 +; AVX-NEXT: movq 40(%rdi), %r11 +; AVX-NEXT: movq 56(%rdi), %r8 +; AVX-NEXT: movq (%rdi), %r10 +; AVX-NEXT: movq 16(%rdi), %rbx +; AVX-NEXT: movq 32(%rdi), %r14 +; AVX-NEXT: movq 48(%rdi), %r15 +; AVX-NEXT: .LBB3_2: +; AVX-NEXT: movq %r15, 48(%rcx) +; AVX-NEXT: movq %r14, 32(%rcx) +; AVX-NEXT: movq %rbx, 16(%rcx) +; AVX-NEXT: movq %r10, (%rcx) +; AVX-NEXT: movq %r8, 56(%rcx) +; AVX-NEXT: movq %r11, 40(%rcx) +; AVX-NEXT: movq %r9, 24(%rcx) +; AVX-NEXT: movq %rax, 8(%rcx) +; AVX-NEXT: popq %rbx +; AVX-NEXT: popq %r14 +; AVX-NEXT: popq %r15 +; AVX-NEXT: retq +; +; AVX512F-LABEL: test_neg_i512: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: vptestnmq %zmm0, %zmm0, %k0 +; AVX512F-NEXT: kmovw %k0, %esi +; AVX512F-NEXT: movzbl %sil, %esi +; AVX512F-NEXT: leal (%rsi,%rax,2), %eax +; AVX512F-NEXT: xorl %esi, %eax +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512F-NEXT: vpsubq %zmm0, %zmm1, %zmm1 +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm2 = -1 +; AVX512F-NEXT: vpxorq %zmm2, %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: negl %edx +; AVX512F-NEXT: kmovw %edx, %k1 +; AVX512F-NEXT: vmovdqu32 (%rdi), %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rcx) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_neg_i512: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512VL-NEXT: vptestmq %zmm0, %zmm0, %k0 +; AVX512VL-NEXT: kmovd %k0, %eax +; AVX512VL-NEXT: vptestnmq %zmm0, %zmm0, %k0 +; AVX512VL-NEXT: kmovb %k0, %esi +; AVX512VL-NEXT: leal (%rsi,%rax,2), %eax +; AVX512VL-NEXT: xorl %esi, %eax +; AVX512VL-NEXT: kmovd %eax, %k1 +; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VL-NEXT: vpsubq %zmm0, %zmm1, %zmm1 +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm2 = -1 +; AVX512VL-NEXT: vpxorq %zmm2, %zmm0, %zmm1 {%k1} +; AVX512VL-NEXT: negl %edx +; AVX512VL-NEXT: kmovd %edx, %k1 +; AVX512VL-NEXT: vmovdqu32 (%rdi), %zmm1 {%k1} +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rcx) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq + %ld0 = load i512, ptr %p0 + %ld1 = load i512, ptr %p1 + %neg1 = sub i512 0, %ld1 + %sel = select i1 %a2, i512 %ld0, i512 %neg1 + store i512 %sel, ptr %p3 + ret void +} + + diff --git a/llvm/test/CodeGen/X86/shuffle-as-shifts.ll b/llvm/test/CodeGen/X86/shuffle-as-shifts.ll index 4b8f78d36c3f5..021f8d6fb971d 100644 --- a/llvm/test/CodeGen/X86/shuffle-as-shifts.ll +++ b/llvm/test/CodeGen/X86/shuffle-as-shifts.ll @@ -4,6 +4,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,CHECK-V4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 define <4 x i32> @shuf_rot_v4i32_1032(<4 x i32> %x) { diff --git a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll index ceef3fb4bb188..a215b60055dd5 100644 --- a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll +++ b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll @@ -51,6 +51,7 @@ ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver5 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver6 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX512 ; Other chips with slow unaligned memory accesses diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll index fade0f7d1d130..5ac82c715dd04 100644 --- a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll +++ b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll @@ -144,6 +144,6 @@ define float @rsqrt_daz(float %f) #1 { ret float %div } -attributes #0 = { "reciprocal-estimates"="sqrt:2" "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "reciprocal-estimates"="sqrt:2" "denormal-fp-math"="ieee,preserve-sign" } +attributes #0 = { "reciprocal-estimates"="sqrt:2" denormal_fpenv(ieee|ieee) } +attributes #1 = { "reciprocal-estimates"="sqrt:2" denormal_fpenv(ieee|preservesign) } attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll index 74b51ac21dc1f..416ff1d41af72 100644 --- a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll +++ b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll @@ -7,6 +7,7 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=X86-64 define float @f32_no_daz(float %f) #0 { @@ -403,6 +404,6 @@ declare float @llvm.sqrt.f32(float) #2 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #2 declare <8 x float> @llvm.sqrt.v8f32(<8 x float>) #2 -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(ieee|preservesign) } attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath.ll b/llvm/test/CodeGen/X86/sqrt-fastmath.ll index 83bfcd7f04d9c..143edacb5390d 100644 --- a/llvm/test/CodeGen/X86/sqrt-fastmath.ll +++ b/llvm/test/CodeGen/X86/sqrt-fastmath.ll @@ -1015,12 +1015,12 @@ define double @sqrt_simplify_before_recip_order(double %x, ptr %p) nounwind { attributes #0 = { "reciprocal-estimates"="!sqrtf,!vec-sqrtf,!divf,!vec-divf" } attributes #1 = { "reciprocal-estimates"="sqrt,vec-sqrt" } attributes #2 = { nounwind readnone } -attributes #3 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,ieee" } -attributes #4 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="ieee,preserve-sign" } +attributes #3 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(preservesign|ieee) } +attributes #4 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(ieee|preservesign) } attributes #5 = { "reciprocal-estimates"="all:0" } -attributes #6 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,dynamic" } +attributes #6 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(preservesign|dynamic) } ; Attributes without ; TODO: Merge with previous attributes when this attribute can be deleted. -attributes #7 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,ieee" } ; #3 -attributes #8 = { "reciprocal-estimates"="sqrt,vec-sqrt" "denormal-fp-math"="preserve-sign,dynamic" } ; #6 +attributes #7 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(preservesign|ieee) } ; #3 +attributes #8 = { "reciprocal-estimates"="sqrt,vec-sqrt" denormal_fpenv(preservesign|dynamic) } ; #6 diff --git a/llvm/test/CodeGen/X86/sse-minmax-finite.ll b/llvm/test/CodeGen/X86/sse-minmax-finite.ll new file mode 100644 index 0000000000000..469637964d849 --- /dev/null +++ b/llvm/test/CodeGen/X86/sse-minmax-finite.ll @@ -0,0 +1,787 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 | FileCheck %s + +; Some of these patterns can be matched as SSE min or max. Some of +; them can be matched provided that the operands are swapped. +; Some of them can't be matched at all and require a comparison +; and a conditional branch. + +; The naming convention is {,x_,y_}{o,u}{gt,lt,ge,le}{,_inverse} +; _x: use 0.0 instead of %y +; _y: use -0.0 instead of %y +; _inverse : swap the arms of the select. + +define double @ogt(double %x, double %y) { +; CHECK-LABEL: ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ogt double %x, %y + %d = select i1 %c, double %x, double %y + ret double %d +} + +define double @olt(double %x, double %y) { +; CHECK-LABEL: olt: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan olt double %x, %y + %d = select i1 %c, double %x, double %y + ret double %d +} + +define double @ogt_inverse(double %x, double %y) { +; CHECK-LABEL: ogt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ogt double %x, %y + %d = select i1 %c, double %y, double %x + ret double %d +} + +define double @olt_inverse(double %x, double %y) { +; CHECK-LABEL: olt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan olt double %x, %y + %d = select i1 %c, double %y, double %x + ret double %d +} + +define double @oge(double %x, double %y) { +; CHECK-LABEL: oge: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan oge double %x, %y + %d = select i1 %c, double %x, double %y + ret double %d +} + +define double @ole(double %x, double %y) { +; CHECK-LABEL: ole: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ole double %x, %y + %d = select i1 %c, double %x, double %y + ret double %d +} + +define double @oge_inverse(double %x, double %y) { +; RELAX-LABEL: oge_inverse: +; RELAX: # %bb.0: +; RELAX-NEXT: minsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: oge_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan oge double %x, %y + %d = select i1 %c, double %y, double %x + ret double %d +} + +define double @ole_inverse(double %x, double %y) { +; RELAX-LABEL: ole_inverse: +; RELAX: # %bb.0: +; RELAX-NEXT: maxsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ole_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ole double %x, %y + %d = select i1 %c, double %y, double %x + ret double %d +} + +define double @ogt_x(double %x) { +; CHECK-LABEL: ogt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ogt double %x, 0.000000e+00 + %d = select i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @olt_x(double %x) { +; CHECK-LABEL: olt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan olt double %x, 0.000000e+00 + %d = select i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ogt_inverse_x(double %x) { +; CHECK-LABEL: ogt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ogt double %x, 0.000000e+00 + %d = select i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @olt_inverse_x(double %x) { +; CHECK-LABEL: olt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan olt double %x, 0.000000e+00 + %d = select i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @oge_x(double %x) { +; CHECK-LABEL: oge_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan oge double %x, 0.000000e+00 + %d = select i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ole_x(double %x) { +; CHECK-LABEL: ole_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ole double %x, 0.000000e+00 + %d = select i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @oge_inverse_x(double %x) { +; RELAX-LABEL: oge_inverse_x: +; RELAX: # %bb.0: +; RELAX-NEXT: xorpd %xmm1, %xmm1 +; RELAX-NEXT: minsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: oge_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan oge double %x, 0.000000e+00 + %d = select i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ole_inverse_x(double %x) { +; RELAX-LABEL: ole_inverse_x: +; RELAX: # %bb.0: +; RELAX-NEXT: xorpd %xmm1, %xmm1 +; RELAX-NEXT: maxsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ole_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ole double %x, 0.000000e+00 + %d = select i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ugt(double %x, double %y) { +; RELAX-LABEL: ugt: +; RELAX: # %bb.0: +; RELAX-NEXT: maxsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ugt double %x, %y + %d = select i1 %c, double %x, double %y + ret double %d +} + +define double @ult(double %x, double %y) { +; RELAX-LABEL: ult: +; RELAX: # %bb.0: +; RELAX-NEXT: minsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ult: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ult double %x, %y + %d = select i1 %c, double %x, double %y + ret double %d +} + +define double @ugt_inverse(double %x, double %y) { +; CHECK-LABEL: ugt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ugt double %x, %y + %d = select i1 %c, double %y, double %x + ret double %d +} + +define double @ult_inverse(double %x, double %y) { +; CHECK-LABEL: ult_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ult double %x, %y + %d = select i1 %c, double %y, double %x + ret double %d +} + +define double @uge(double %x, double %y) { +; CHECK-LABEL: uge: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan uge double %x, %y + %d = select i1 %c, double %x, double %y + ret double %d +} + +define double @ule(double %x, double %y) { +; CHECK-LABEL: ule: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ule double %x, %y + %d = select i1 %c, double %x, double %y + ret double %d +} + +define double @uge_inverse(double %x, double %y) { +; CHECK-LABEL: uge_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan uge double %x, %y + %d = select i1 %c, double %y, double %x + ret double %d +} + +define double @ule_inverse(double %x, double %y) { +; CHECK-LABEL: ule_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ule double %x, %y + %d = select i1 %c, double %y, double %x + ret double %d +} + +define double @ugt_x(double %x) { +; RELAX-LABEL: ugt_x: +; RELAX: # %bb.0: +; RELAX-NEXT: xorpd %xmm1, %xmm1 +; RELAX-NEXT: maxsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ugt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ugt double %x, 0.000000e+00 + %d = select i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ult_x(double %x) { +; RELAX-LABEL: ult_x: +; RELAX: # %bb.0: +; RELAX-NEXT: xorpd %xmm1, %xmm1 +; RELAX-NEXT: minsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ult_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ult double %x, 0.000000e+00 + %d = select i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ugt_inverse_x(double %x) { +; CHECK-LABEL: ugt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ugt double %x, 0.000000e+00 + %d = select i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ult_inverse_x(double %x) { +; CHECK-LABEL: ult_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ult double %x, 0.000000e+00 + %d = select i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @uge_x(double %x) { +; CHECK-LABEL: uge_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan uge double %x, 0.000000e+00 + %d = select i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ule_x(double %x) { +; CHECK-LABEL: ule_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ule double %x, 0.000000e+00 + %d = select i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @uge_inverse_x(double %x) { +; CHECK-LABEL: uge_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan uge double %x, 0.000000e+00 + %d = select i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ule_inverse_x(double %x) { +; CHECK-LABEL: ule_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ule double %x, 0.000000e+00 + %d = select i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ogt_y(double %x) { +; CHECK-LABEL: ogt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ogt double %x, -0.000000e+00 + %d = select i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @olt_y(double %x) { +; CHECK-LABEL: olt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan olt double %x, -0.000000e+00 + %d = select i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ogt_inverse_y(double %x) { +; CHECK-LABEL: ogt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ogt double %x, -0.000000e+00 + %d = select i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @olt_inverse_y(double %x) { +; CHECK-LABEL: olt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan olt double %x, -0.000000e+00 + %d = select i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @oge_y(double %x) { +; CHECK-LABEL: oge_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan oge double %x, -0.000000e+00 + %d = select i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ole_y(double %x) { +; CHECK-LABEL: ole_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ole double %x, -0.000000e+00 + %d = select i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @oge_inverse_y(double %x) { +; RELAX-LABEL: oge_inverse_y: +; RELAX: # %bb.0: +; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: oge_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan oge double %x, -0.000000e+00 + %d = select i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @ole_inverse_y(double %x) { +; RELAX-LABEL: ole_inverse_y: +; RELAX: # %bb.0: +; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ole_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ole double %x, -0.000000e+00 + %d = select i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @ugt_y(double %x) { +; RELAX-LABEL: ugt_y: +; RELAX: # %bb.0: +; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ugt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ugt double %x, -0.000000e+00 + %d = select i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ult_y(double %x) { +; RELAX-LABEL: ult_y: +; RELAX: # %bb.0: +; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ult_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ult double %x, -0.000000e+00 + %d = select i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ugt_inverse_y(double %x) { +; CHECK-LABEL: ugt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ugt double %x, -0.000000e+00 + %d = select i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @ult_inverse_y(double %x) { +; CHECK-LABEL: ult_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ult double %x, -0.000000e+00 + %d = select i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @uge_y(double %x) { +; CHECK-LABEL: uge_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan uge double %x, -0.000000e+00 + %d = select i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ule_y(double %x) { +; CHECK-LABEL: ule_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ule double %x, -0.000000e+00 + %d = select i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @uge_inverse_y(double %x) { +; CHECK-LABEL: uge_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan uge double %x, -0.000000e+00 + %d = select i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @ule_inverse_y(double %x) { +; CHECK-LABEL: ule_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nnan ule double %x, -0.000000e+00 + %d = select i1 %c, double -0.000000e+00, double %x + ret double %d +} + +; Test a few more misc. cases. + +define double @clampTo3k_a(double %x) { +; CHECK-LABEL: clampTo3k_a: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nnan ogt double %x, 3.000000e+03 + %y = select i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_b(double %x) { +; CHECK-LABEL: clampTo3k_b: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nnan uge double %x, 3.000000e+03 + %y = select i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_c(double %x) { +; CHECK-LABEL: clampTo3k_c: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nnan olt double %x, 3.000000e+03 + %y = select i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_d(double %x) { +; CHECK-LABEL: clampTo3k_d: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nnan ule double %x, 3.000000e+03 + %y = select i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_e(double %x) { +; CHECK-LABEL: clampTo3k_e: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nnan olt double %x, 3.000000e+03 + %y = select i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_f(double %x) { +; CHECK-LABEL: clampTo3k_f: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nnan ule double %x, 3.000000e+03 + %y = select i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_g(double %x) { +; CHECK-LABEL: clampTo3k_g: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nnan ogt double %x, 3.000000e+03 + %y = select i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_h(double %x) { +; CHECK-LABEL: clampTo3k_h: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nnan uge double %x, 3.000000e+03 + %y = select i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define <2 x double> @test_maxpd(<2 x double> %x, <2 x double> %y) { +; CHECK-LABEL: test_maxpd: +; CHECK: # %bb.0: +; CHECK-NEXT: maxpd %xmm1, %xmm0 +; CHECK-NEXT: retq + %max_is_x = fcmp nnan oge <2 x double> %x, %y + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y + ret <2 x double> %max +} + +define <2 x double> @test_minpd(<2 x double> %x, <2 x double> %y) { +; CHECK-LABEL: test_minpd: +; CHECK: # %bb.0: +; CHECK-NEXT: minpd %xmm1, %xmm0 +; CHECK-NEXT: retq + %min_is_x = fcmp nnan ole <2 x double> %x, %y + %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y + ret <2 x double> %min +} + +define <4 x float> @test_maxps(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: test_maxps: +; CHECK: # %bb.0: +; CHECK-NEXT: maxps %xmm1, %xmm0 +; CHECK-NEXT: retq + %max_is_x = fcmp nnan oge <4 x float> %x, %y + %max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y + ret <4 x float> %max +} + +define <4 x float> @test_minps(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: test_minps: +; CHECK: # %bb.0: +; CHECK-NEXT: minps %xmm1, %xmm0 +; CHECK-NEXT: retq + %min_is_x = fcmp nnan ole <4 x float> %x, %y + %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y + ret <4 x float> %min +} + +define <2 x float> @test_maxps_illegal_v2f32(<2 x float> %x, <2 x float> %y) { +; CHECK-LABEL: test_maxps_illegal_v2f32: +; CHECK: # %bb.0: +; CHECK-NEXT: maxps %xmm1, %xmm0 +; CHECK-NEXT: retq + %max_is_x = fcmp nnan oge <2 x float> %x, %y + %max = select <2 x i1> %max_is_x, <2 x float> %x, <2 x float> %y + ret <2 x float> %max +} + +define <2 x float> @test_minps_illegal_v2f32(<2 x float> %x, <2 x float> %y) { +; CHECK-LABEL: test_minps_illegal_v2f32: +; CHECK: # %bb.0: +; CHECK-NEXT: minps %xmm1, %xmm0 +; CHECK-NEXT: retq + %min_is_x = fcmp nnan ole <2 x float> %x, %y + %min = select <2 x i1> %min_is_x, <2 x float> %x, <2 x float> %y + ret <2 x float> %min +} + +define <3 x float> @test_maxps_illegal_v3f32(<3 x float> %x, <3 x float> %y) { +; CHECK-LABEL: test_maxps_illegal_v3f32: +; CHECK: # %bb.0: +; CHECK-NEXT: maxps %xmm1, %xmm0 +; CHECK-NEXT: retq + %max_is_x = fcmp nnan oge <3 x float> %x, %y + %max = select <3 x i1> %max_is_x, <3 x float> %x, <3 x float> %y + ret <3 x float> %max +} + +define <3 x float> @test_minps_illegal_v3f32(<3 x float> %x, <3 x float> %y) { +; CHECK-LABEL: test_minps_illegal_v3f32: +; CHECK: # %bb.0: +; CHECK-NEXT: minps %xmm1, %xmm0 +; CHECK-NEXT: retq + %min_is_x = fcmp nnan ole <3 x float> %x, %y + %min = select <3 x i1> %min_is_x, <3 x float> %x, <3 x float> %y + ret <3 x float> %min +} + +; OSS-Fuzz #13838 +; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13838 +define float @ossfuzz13838(float %x) { +; CHECK-LABEL: ossfuzz13838: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: movss {{.*#+}} xmm0 = [2.55E+2,0.0E+0,0.0E+0,0.0E+0] +; CHECK-NEXT: retq +bb: + %cmp2 = fcmp nnan fast olt float %x, 2.550000e+02 + %B1 = urem i1 %cmp2, %cmp2 + %min = select i1 %B1, float %x, float 2.550000e+02 + %B = frem float %min, 0x47EFFFFFE0000000 + %cmp1 = fcmp nnan fast olt float %B, 1.000000e+00 + %r = select i1 %cmp1, float 1.000000e+00, float %min + ret float %r +} diff --git a/llvm/test/CodeGen/X86/sse-minmax-unsafe.ll b/llvm/test/CodeGen/X86/sse-minmax-unsafe.ll new file mode 100644 index 0000000000000..88167250a5314 --- /dev/null +++ b/llvm/test/CodeGen/X86/sse-minmax-unsafe.ll @@ -0,0 +1,687 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 | FileCheck %s + +; Some of these patterns can be matched as SSE min or max. Some of +; them can be matched provided that the operands are swapped. +; Some of them can't be matched at all and require a comparison +; and a conditional branch. + +; The naming convention is {,x_,y_}{o,u}{gt,lt,ge,le}{,_inverse} +; _x: use 0.0 instead of %y +; _y: use -0.0 instead of %y +; _inverse : swap the arms of the select. + +define double @ogt(double %x, double %y) { +; CHECK-LABEL: ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ogt double %x, %y + %d = select nsz nnan i1 %c, double %x, double %y + ret double %d +} + +define double @olt(double %x, double %y) { +; CHECK-LABEL: olt: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan olt double %x, %y + %d = select nsz nnan i1 %c, double %x, double %y + ret double %d +} + +define double @ogt_inverse(double %x, double %y) { +; CHECK-LABEL: ogt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ogt double %x, %y + %d = select nsz nnan i1 %c, double %y, double %x + ret double %d +} + +define double @olt_inverse(double %x, double %y) { +; CHECK-LABEL: olt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan olt double %x, %y + %d = select nsz nnan i1 %c, double %y, double %x + ret double %d +} + +define double @oge(double %x, double %y) { +; CHECK-LABEL: oge: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan oge double %x, %y + %d = select nsz nnan i1 %c, double %x, double %y + ret double %d +} + +define double @ole(double %x, double %y) { +; CHECK-LABEL: ole: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ole double %x, %y + %d = select nsz nnan i1 %c, double %x, double %y + ret double %d +} + +define double @oge_inverse(double %x, double %y) { +; CHECK-LABEL: oge_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan oge double %x, %y + %d = select nsz nnan i1 %c, double %y, double %x + ret double %d +} + +define double @ole_inverse(double %x, double %y) { +; CHECK-LABEL: ole_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ole double %x, %y + %d = select nsz nnan i1 %c, double %y, double %x + ret double %d +} + +define double @ogt_x(double %x) { +; CHECK-LABEL: ogt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ogt double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @olt_x(double %x) { +; CHECK-LABEL: olt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan olt double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ogt_inverse_x(double %x) { +; CHECK-LABEL: ogt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ogt double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @olt_inverse_x(double %x) { +; CHECK-LABEL: olt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan olt double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @oge_x(double %x) { +; CHECK-LABEL: oge_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan oge double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ole_x(double %x) { +; CHECK-LABEL: ole_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ole double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @oge_inverse_x(double %x) { +; CHECK-LABEL: oge_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan oge double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ole_inverse_x(double %x) { +; CHECK-LABEL: ole_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ole double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ugt(double %x, double %y) { +; CHECK-LABEL: ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ugt double %x, %y + %d = select nsz nnan i1 %c, double %x, double %y + ret double %d +} + +define double @ult(double %x, double %y) { +; CHECK-LABEL: ult: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ult double %x, %y + %d = select nsz nnan i1 %c, double %x, double %y + ret double %d +} + +define double @ugt_inverse(double %x, double %y) { +; CHECK-LABEL: ugt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ugt double %x, %y + %d = select nsz nnan i1 %c, double %y, double %x + ret double %d +} + +define double @ult_inverse(double %x, double %y) { +; CHECK-LABEL: ult_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ult double %x, %y + %d = select nsz nnan i1 %c, double %y, double %x + ret double %d +} + +define double @uge(double %x, double %y) { +; CHECK-LABEL: uge: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan uge double %x, %y + %d = select nsz nnan i1 %c, double %x, double %y + ret double %d +} + +define double @ule(double %x, double %y) { +; CHECK-LABEL: ule: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ule double %x, %y + %d = select nsz nnan i1 %c, double %x, double %y + ret double %d +} + +define double @uge_inverse(double %x, double %y) { +; CHECK-LABEL: uge_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan uge double %x, %y + %d = select nsz nnan i1 %c, double %y, double %x + ret double %d +} + +define double @ule_inverse(double %x, double %y) { +; CHECK-LABEL: ule_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ule double %x, %y + %d = select nsz nnan i1 %c, double %y, double %x + ret double %d +} + +define double @ugt_x(double %x) { +; CHECK-LABEL: ugt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ugt double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ult_x(double %x) { +; CHECK-LABEL: ult_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ult double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ugt_inverse_x(double %x) { +; CHECK-LABEL: ugt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ugt double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ult_inverse_x(double %x) { +; CHECK-LABEL: ult_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ult double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @uge_x(double %x) { +; CHECK-LABEL: uge_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan uge double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @ule_x(double %x) { +; CHECK-LABEL: ule_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ule double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double 0.000000e+00 + ret double %d +} + +define double @uge_inverse_x(double %x) { +; CHECK-LABEL: uge_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan uge double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ule_inverse_x(double %x) { +; CHECK-LABEL: ule_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ule double %x, 0.000000e+00 + %d = select nsz nnan i1 %c, double 0.000000e+00, double %x + ret double %d +} + +define double @ogt_y(double %x) { +; CHECK-LABEL: ogt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ogt double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @olt_y(double %x) { +; CHECK-LABEL: olt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan olt double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ogt_inverse_y(double %x) { +; CHECK-LABEL: ogt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ogt double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @olt_inverse_y(double %x) { +; CHECK-LABEL: olt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan olt double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @oge_y(double %x) { +; CHECK-LABEL: oge_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan oge double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ole_y(double %x) { +; CHECK-LABEL: ole_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ole double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @oge_inverse_y(double %x) { +; CHECK-LABEL: oge_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan oge double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @ole_inverse_y(double %x) { +; CHECK-LABEL: ole_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ole double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @ugt_y(double %x) { +; CHECK-LABEL: ugt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ugt double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ult_y(double %x) { +; CHECK-LABEL: ult_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ult double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ugt_inverse_y(double %x) { +; CHECK-LABEL: ugt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ugt double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @ult_inverse_y(double %x) { +; CHECK-LABEL: ult_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ult double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @uge_y(double %x) { +; CHECK-LABEL: uge_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan uge double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @ule_y(double %x) { +; CHECK-LABEL: ule_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ule double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double %x, double -0.000000e+00 + ret double %d +} + +define double @uge_inverse_y(double %x) { +; CHECK-LABEL: uge_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan uge double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double -0.000000e+00, double %x + ret double %d +} + +define double @ule_inverse_y(double %x) { +; CHECK-LABEL: ule_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = fcmp nsz nnan ule double %x, -0.000000e+00 + %d = select nsz nnan i1 %c, double -0.000000e+00, double %x + ret double %d +} + +; Test a few more misc. cases. + +define double @clampTo3k_a(double %x) { +; CHECK-LABEL: clampTo3k_a: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nsz nnan ogt double %x, 3.000000e+03 + %y = select nsz nnan i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_b(double %x) { +; CHECK-LABEL: clampTo3k_b: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nsz nnan uge double %x, 3.000000e+03 + %y = select nsz nnan i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_c(double %x) { +; CHECK-LABEL: clampTo3k_c: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nsz nnan olt double %x, 3.000000e+03 + %y = select nsz nnan i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_d(double %x) { +; CHECK-LABEL: clampTo3k_d: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nsz nnan ule double %x, 3.000000e+03 + %y = select nsz nnan i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_e(double %x) { +; CHECK-LABEL: clampTo3k_e: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nsz nnan olt double %x, 3.000000e+03 + %y = select nsz nnan i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_f(double %x) { +; CHECK-LABEL: clampTo3k_f: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nsz nnan ule double %x, 3.000000e+03 + %y = select nsz nnan i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_g(double %x) { +; CHECK-LABEL: clampTo3k_g: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nsz nnan ogt double %x, 3.000000e+03 + %y = select nsz nnan i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define double @clampTo3k_h(double %x) { +; CHECK-LABEL: clampTo3k_h: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq + %t0 = fcmp nsz nnan uge double %x, 3.000000e+03 + %y = select nsz nnan i1 %t0, double 3.000000e+03, double %x + ret double %y +} + +define <2 x double> @test_maxpd(<2 x double> %x, <2 x double> %y) { +; CHECK-LABEL: test_maxpd: +; CHECK: # %bb.0: +; CHECK-NEXT: maxpd %xmm1, %xmm0 +; CHECK-NEXT: retq + %max_is_x = fcmp nsz nnan oge <2 x double> %x, %y + %max = select nsz nnan <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y + ret <2 x double> %max +} + +define <2 x double> @test_minpd(<2 x double> %x, <2 x double> %y) { +; CHECK-LABEL: test_minpd: +; CHECK: # %bb.0: +; CHECK-NEXT: minpd %xmm1, %xmm0 +; CHECK-NEXT: retq + %min_is_x = fcmp nsz nnan ole <2 x double> %x, %y + %min = select nsz nnan <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y + ret <2 x double> %min +} + +define <4 x float> @test_maxps(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: test_maxps: +; CHECK: # %bb.0: +; CHECK-NEXT: maxps %xmm1, %xmm0 +; CHECK-NEXT: retq + %max_is_x = fcmp nsz nnan oge <4 x float> %x, %y + %max = select nsz nnan <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y + ret <4 x float> %max +} + +define <4 x float> @test_minps(<4 x float> %x, <4 x float> %y) { +; CHECK-LABEL: test_minps: +; CHECK: # %bb.0: +; CHECK-NEXT: minps %xmm1, %xmm0 +; CHECK-NEXT: retq + %min_is_x = fcmp nsz nnan ole <4 x float> %x, %y + %min = select nsz nnan <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y + ret <4 x float> %min +} + +define <2 x float> @test_maxps_illegal_v2f32(<2 x float> %x, <2 x float> %y) { +; CHECK-LABEL: test_maxps_illegal_v2f32: +; CHECK: # %bb.0: +; CHECK-NEXT: maxps %xmm1, %xmm0 +; CHECK-NEXT: retq + %max_is_x = fcmp nsz nnan oge <2 x float> %x, %y + %max = select nsz nnan <2 x i1> %max_is_x, <2 x float> %x, <2 x float> %y + ret <2 x float> %max +} + +define <2 x float> @test_minps_illegal_v2f32(<2 x float> %x, <2 x float> %y) { +; CHECK-LABEL: test_minps_illegal_v2f32: +; CHECK: # %bb.0: +; CHECK-NEXT: minps %xmm1, %xmm0 +; CHECK-NEXT: retq + %min_is_x = fcmp nsz nnan ole <2 x float> %x, %y + %min = select nsz nnan <2 x i1> %min_is_x, <2 x float> %x, <2 x float> %y + ret <2 x float> %min +} + +define <3 x float> @test_maxps_illegal_v3f32(<3 x float> %x, <3 x float> %y) { +; CHECK-LABEL: test_maxps_illegal_v3f32: +; CHECK: # %bb.0: +; CHECK-NEXT: maxps %xmm1, %xmm0 +; CHECK-NEXT: retq + %max_is_x = fcmp nsz nnan oge <3 x float> %x, %y + %max = select nsz nnan <3 x i1> %max_is_x, <3 x float> %x, <3 x float> %y + ret <3 x float> %max +} + +define <3 x float> @test_minps_illegal_v3f32(<3 x float> %x, <3 x float> %y) { +; CHECK-LABEL: test_minps_illegal_v3f32: +; CHECK: # %bb.0: +; CHECK-NEXT: minps %xmm1, %xmm0 +; CHECK-NEXT: retq + %min_is_x = fcmp nsz nnan ole <3 x float> %x, %y + %min = select nsz nnan <3 x i1> %min_is_x, <3 x float> %x, <3 x float> %y + ret <3 x float> %min +} + +; OSS-Fuzz #13838 +; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13838 +define float @ossfuzz13838(float %x) { +; CHECK-LABEL: ossfuzz13838: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: movss {{.*#+}} xmm0 = [2.55E+2,0.0E+0,0.0E+0,0.0E+0] +; CHECK-NEXT: retq +bb: + %cmp2 = fcmp nsz nnan fast olt float %x, 2.550000e+02 + %B1 = urem i1 %cmp2, %cmp2 + %min = select nsz nnan i1 %B1, float %x, float 2.550000e+02 + %B = frem float %min, 0x47EFFFFFE0000000 + %cmp1 = fcmp nsz nnan fast olt float %B, 1.000000e+00 + %r = select nsz nnan i1 %cmp1, float 1.000000e+00, float %min + ret float %r +} diff --git a/llvm/test/CodeGen/X86/sse-minmax.ll b/llvm/test/CodeGen/X86/sse-minmax.ll index 7904b21a3b1fa..2b97f98450973 100644 --- a/llvm/test/CodeGen/X86/sse-minmax.ll +++ b/llvm/test/CodeGen/X86/sse-minmax.ll @@ -1,7 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 | FileCheck %s --check-prefix=ALL --check-prefix=STRICT -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 -enable-no-signed-zeros-fp-math -enable-no-nans-fp-math | FileCheck %s --check-prefix=ALL --check-prefix=RELAX --check-prefix=UNSAFE -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 -enable-no-nans-fp-math | FileCheck %s --check-prefix=ALL --check-prefix=RELAX --check-prefix=FINITE +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 | FileCheck %s ; Some of these patterns can be matched as SSE min or max. Some of ; them can be matched provided that the operands are swapped. @@ -14,972 +12,640 @@ ; _inverse : swap the arms of the select. define double @ogt(double %x, double %y) { -; ALL-LABEL: ogt: -; ALL: # %bb.0: -; ALL-NEXT: maxsd %xmm1, %xmm0 -; ALL-NEXT: retq +; CHECK-LABEL: ogt: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ogt double %x, %y %d = select i1 %c, double %x, double %y ret double %d } define double @olt(double %x, double %y) { -; ALL-LABEL: olt: -; ALL: # %bb.0: -; ALL-NEXT: minsd %xmm1, %xmm0 -; ALL-NEXT: retq +; CHECK-LABEL: olt: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp olt double %x, %y %d = select i1 %c, double %x, double %y ret double %d } define double @ogt_inverse(double %x, double %y) { -; STRICT-LABEL: ogt_inverse: -; STRICT: # %bb.0: -; STRICT-NEXT: minsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ogt_inverse: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ogt_inverse: -; FINITE: # %bb.0: -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ogt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ogt double %x, %y %d = select i1 %c, double %y, double %x ret double %d } define double @olt_inverse(double %x, double %y) { -; STRICT-LABEL: olt_inverse: -; STRICT: # %bb.0: -; STRICT-NEXT: maxsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: olt_inverse: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: olt_inverse: -; FINITE: # %bb.0: -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: olt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp olt double %x, %y %d = select i1 %c, double %y, double %x ret double %d } define double @oge(double %x, double %y) { -; STRICT-LABEL: oge: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: cmplesd %xmm2, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: oge: -; RELAX: # %bb.0: -; RELAX-NEXT: maxsd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: oge: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: cmplesd %xmm2, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp oge double %x, %y %d = select i1 %c, double %x, double %y ret double %d } define double @ole(double %x, double %y) { -; STRICT-LABEL: ole: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: cmplesd %xmm1, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: ole: -; RELAX: # %bb.0: -; RELAX-NEXT: minsd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: ole: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: cmplesd %xmm1, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ole double %x, %y %d = select i1 %c, double %x, double %y ret double %d } define double @oge_inverse(double %x, double %y) { -; STRICT-LABEL: oge_inverse: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: cmplesd %xmm2, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; STRICT-NEXT: movapd %xmm2, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: oge_inverse: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: oge_inverse: -; FINITE: # %bb.0: -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; RELAX-LABEL: oge_inverse: +; RELAX: # %bb.0: +; RELAX-NEXT: minsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: oge_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: cmplesd %xmm2, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: movapd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp oge double %x, %y %d = select i1 %c, double %y, double %x ret double %d } define double @ole_inverse(double %x, double %y) { -; STRICT-LABEL: ole_inverse: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: cmplesd %xmm1, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; STRICT-NEXT: movapd %xmm2, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ole_inverse: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ole_inverse: -; FINITE: # %bb.0: -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; RELAX-LABEL: ole_inverse: +; RELAX: # %bb.0: +; RELAX-NEXT: maxsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ole_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: cmplesd %xmm1, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: movapd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp ole double %x, %y %d = select i1 %c, double %y, double %x ret double %d } define double @ogt_x(double %x) { -; ALL-LABEL: ogt_x: -; ALL: # %bb.0: -; ALL-NEXT: xorpd %xmm1, %xmm1 -; ALL-NEXT: maxsd %xmm1, %xmm0 -; ALL-NEXT: retq +; CHECK-LABEL: ogt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ogt double %x, 0.000000e+00 %d = select i1 %c, double %x, double 0.000000e+00 ret double %d } define double @olt_x(double %x) { -; ALL-LABEL: olt_x: -; ALL: # %bb.0: -; ALL-NEXT: xorpd %xmm1, %xmm1 -; ALL-NEXT: minsd %xmm1, %xmm0 -; ALL-NEXT: retq +; CHECK-LABEL: olt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp olt double %x, 0.000000e+00 %d = select i1 %c, double %x, double 0.000000e+00 ret double %d } define double @ogt_inverse_x(double %x) { -; STRICT-LABEL: ogt_inverse_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: minsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ogt_inverse_x: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: xorpd %xmm1, %xmm1 -; UNSAFE-NEXT: minsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ogt_inverse_x: -; FINITE: # %bb.0: -; FINITE-NEXT: xorpd %xmm1, %xmm1 -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ogt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ogt double %x, 0.000000e+00 %d = select i1 %c, double 0.000000e+00, double %x ret double %d } define double @olt_inverse_x(double %x) { -; STRICT-LABEL: olt_inverse_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: maxsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: olt_inverse_x: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: xorpd %xmm1, %xmm1 -; UNSAFE-NEXT: maxsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: olt_inverse_x: -; FINITE: # %bb.0: -; FINITE-NEXT: xorpd %xmm1, %xmm1 -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: olt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp olt double %x, 0.000000e+00 %d = select i1 %c, double 0.000000e+00, double %x ret double %d } define double @oge_x(double %x) { -; STRICT-LABEL: oge_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: cmplesd %xmm0, %xmm1 -; STRICT-NEXT: andpd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: oge_x: -; RELAX: # %bb.0: -; RELAX-NEXT: xorpd %xmm1, %xmm1 -; RELAX-NEXT: maxsd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: oge_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: cmplesd %xmm0, %xmm1 +; CHECK-NEXT: andpd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp oge double %x, 0.000000e+00 %d = select i1 %c, double %x, double 0.000000e+00 ret double %d } define double @ole_x(double %x) { -; STRICT-LABEL: ole_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: cmplesd %xmm1, %xmm2 -; STRICT-NEXT: andpd %xmm2, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: ole_x: -; RELAX: # %bb.0: -; RELAX-NEXT: xorpd %xmm1, %xmm1 -; RELAX-NEXT: minsd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: ole_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: cmplesd %xmm1, %xmm2 +; CHECK-NEXT: andpd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp ole double %x, 0.000000e+00 %d = select i1 %c, double %x, double 0.000000e+00 ret double %d } define double @oge_inverse_x(double %x) { -; STRICT-LABEL: oge_inverse_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: cmplesd %xmm0, %xmm1 -; STRICT-NEXT: andnpd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: oge_inverse_x: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: xorpd %xmm1, %xmm1 -; UNSAFE-NEXT: minsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: oge_inverse_x: -; FINITE: # %bb.0: -; FINITE-NEXT: xorpd %xmm1, %xmm1 -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; RELAX-LABEL: oge_inverse_x: +; RELAX: # %bb.0: +; RELAX-NEXT: xorpd %xmm1, %xmm1 +; RELAX-NEXT: minsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: oge_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: cmplesd %xmm0, %xmm1 +; CHECK-NEXT: andnpd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp oge double %x, 0.000000e+00 %d = select i1 %c, double 0.000000e+00, double %x ret double %d } define double @ole_inverse_x(double %x) { -; STRICT-LABEL: ole_inverse_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm2, %xmm2 -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: cmplesd %xmm2, %xmm1 -; STRICT-NEXT: andnpd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ole_inverse_x: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: xorpd %xmm1, %xmm1 -; UNSAFE-NEXT: maxsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ole_inverse_x: -; FINITE: # %bb.0: -; FINITE-NEXT: xorpd %xmm1, %xmm1 -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; RELAX-LABEL: ole_inverse_x: +; RELAX: # %bb.0: +; RELAX-NEXT: xorpd %xmm1, %xmm1 +; RELAX-NEXT: maxsd %xmm1, %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ole_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm2, %xmm2 +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: cmplesd %xmm2, %xmm1 +; CHECK-NEXT: andnpd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ole double %x, 0.000000e+00 %d = select i1 %c, double 0.000000e+00, double %x ret double %d } define double @ugt(double %x, double %y) { -; STRICT-LABEL: ugt: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: cmpnlesd %xmm1, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; ; RELAX-LABEL: ugt: ; RELAX: # %bb.0: ; RELAX-NEXT: maxsd %xmm1, %xmm0 ; RELAX-NEXT: retq +; CHECK-LABEL: ugt: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: cmpnlesd %xmm1, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ugt double %x, %y %d = select i1 %c, double %x, double %y ret double %d } define double @ult(double %x, double %y) { -; STRICT-LABEL: ult: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: cmpnlesd %xmm2, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; ; RELAX-LABEL: ult: ; RELAX: # %bb.0: ; RELAX-NEXT: minsd %xmm1, %xmm0 ; RELAX-NEXT: retq +; CHECK-LABEL: ult: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: cmpnlesd %xmm2, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ult double %x, %y %d = select i1 %c, double %x, double %y ret double %d } define double @ugt_inverse(double %x, double %y) { -; STRICT-LABEL: ugt_inverse: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: cmpnlesd %xmm1, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; STRICT-NEXT: movapd %xmm2, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ugt_inverse: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ugt_inverse: -; FINITE: # %bb.0: -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ugt_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: cmpnlesd %xmm1, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: movapd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp ugt double %x, %y %d = select i1 %c, double %y, double %x ret double %d } define double @ult_inverse(double %x, double %y) { -; STRICT-LABEL: ult_inverse: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: cmpnlesd %xmm2, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; STRICT-NEXT: movapd %xmm2, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ult_inverse: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ult_inverse: -; FINITE: # %bb.0: -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ult_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: cmpnlesd %xmm2, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: movapd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp ult double %x, %y %d = select i1 %c, double %y, double %x ret double %d } define double @uge(double %x, double %y) { -; STRICT-LABEL: uge: -; STRICT: # %bb.0: -; STRICT-NEXT: maxsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: uge: -; RELAX: # %bb.0: -; RELAX-NEXT: maxsd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: uge: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp uge double %x, %y %d = select i1 %c, double %x, double %y ret double %d } define double @ule(double %x, double %y) { -; STRICT-LABEL: ule: -; STRICT: # %bb.0: -; STRICT-NEXT: minsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: ule: -; RELAX: # %bb.0: -; RELAX-NEXT: minsd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: ule: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ule double %x, %y %d = select i1 %c, double %x, double %y ret double %d } define double @uge_inverse(double %x, double %y) { -; STRICT-LABEL: uge_inverse: -; STRICT: # %bb.0: -; STRICT-NEXT: minsd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: uge_inverse: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: uge_inverse: -; FINITE: # %bb.0: -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: uge_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp uge double %x, %y %d = select i1 %c, double %y, double %x ret double %d } define double @ule_inverse(double %x, double %y) { -; STRICT-LABEL: ule_inverse: -; STRICT: # %bb.0: -; STRICT-NEXT: maxsd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ule_inverse: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ule_inverse: -; FINITE: # %bb.0: -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ule_inverse: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ule double %x, %y %d = select i1 %c, double %y, double %x ret double %d } define double @ugt_x(double %x) { -; STRICT-LABEL: ugt_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: cmpnlesd %xmm1, %xmm2 -; STRICT-NEXT: andpd %xmm2, %xmm0 -; STRICT-NEXT: retq -; ; RELAX-LABEL: ugt_x: ; RELAX: # %bb.0: ; RELAX-NEXT: xorpd %xmm1, %xmm1 ; RELAX-NEXT: maxsd %xmm1, %xmm0 ; RELAX-NEXT: retq +; CHECK-LABEL: ugt_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: cmpnlesd %xmm1, %xmm2 +; CHECK-NEXT: andpd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp ugt double %x, 0.000000e+00 %d = select i1 %c, double %x, double 0.000000e+00 ret double %d } define double @ult_x(double %x) { -; STRICT-LABEL: ult_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: cmpnlesd %xmm0, %xmm1 -; STRICT-NEXT: andpd %xmm1, %xmm0 -; STRICT-NEXT: retq -; ; RELAX-LABEL: ult_x: ; RELAX: # %bb.0: ; RELAX-NEXT: xorpd %xmm1, %xmm1 ; RELAX-NEXT: minsd %xmm1, %xmm0 ; RELAX-NEXT: retq +; CHECK-LABEL: ult_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: cmpnlesd %xmm0, %xmm1 +; CHECK-NEXT: andpd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ult double %x, 0.000000e+00 %d = select i1 %c, double %x, double 0.000000e+00 ret double %d } define double @ugt_inverse_x(double %x) { -; STRICT-LABEL: ugt_inverse_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm2, %xmm2 -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: cmpnlesd %xmm2, %xmm1 -; STRICT-NEXT: andnpd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ugt_inverse_x: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: xorpd %xmm1, %xmm1 -; UNSAFE-NEXT: minsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ugt_inverse_x: -; FINITE: # %bb.0: -; FINITE-NEXT: xorpd %xmm1, %xmm1 -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ugt_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm2, %xmm2 +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: cmpnlesd %xmm2, %xmm1 +; CHECK-NEXT: andnpd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ugt double %x, 0.000000e+00 %d = select i1 %c, double 0.000000e+00, double %x ret double %d } define double @ult_inverse_x(double %x) { -; STRICT-LABEL: ult_inverse_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: cmpnlesd %xmm0, %xmm1 -; STRICT-NEXT: andnpd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ult_inverse_x: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: xorpd %xmm1, %xmm1 -; UNSAFE-NEXT: maxsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ult_inverse_x: -; FINITE: # %bb.0: -; FINITE-NEXT: xorpd %xmm1, %xmm1 -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ult_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: cmpnlesd %xmm0, %xmm1 +; CHECK-NEXT: andnpd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ult double %x, 0.000000e+00 %d = select i1 %c, double 0.000000e+00, double %x ret double %d } define double @uge_x(double %x) { -; STRICT-LABEL: uge_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: maxsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: uge_x: -; RELAX: # %bb.0: -; RELAX-NEXT: xorpd %xmm1, %xmm1 -; RELAX-NEXT: maxsd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: uge_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp uge double %x, 0.000000e+00 %d = select i1 %c, double %x, double 0.000000e+00 ret double %d } define double @ule_x(double %x) { -; STRICT-LABEL: ule_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: minsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: ule_x: -; RELAX: # %bb.0: -; RELAX-NEXT: xorpd %xmm1, %xmm1 -; RELAX-NEXT: minsd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: ule_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ule double %x, 0.000000e+00 %d = select i1 %c, double %x, double 0.000000e+00 ret double %d } define double @uge_inverse_x(double %x) { -; STRICT-LABEL: uge_inverse_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: minsd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: uge_inverse_x: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: xorpd %xmm1, %xmm1 -; UNSAFE-NEXT: minsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: uge_inverse_x: -; FINITE: # %bb.0: -; FINITE-NEXT: xorpd %xmm1, %xmm1 -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: uge_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: minsd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp uge double %x, 0.000000e+00 %d = select i1 %c, double 0.000000e+00, double %x ret double %d } define double @ule_inverse_x(double %x) { -; STRICT-LABEL: ule_inverse_x: -; STRICT: # %bb.0: -; STRICT-NEXT: xorpd %xmm1, %xmm1 -; STRICT-NEXT: maxsd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ule_inverse_x: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: xorpd %xmm1, %xmm1 -; UNSAFE-NEXT: maxsd %xmm1, %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ule_inverse_x: -; FINITE: # %bb.0: -; FINITE-NEXT: xorpd %xmm1, %xmm1 -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ule_inverse_x: +; CHECK: # %bb.0: +; CHECK-NEXT: xorpd %xmm1, %xmm1 +; CHECK-NEXT: maxsd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ule double %x, 0.000000e+00 %d = select i1 %c, double 0.000000e+00, double %x ret double %d } define double @ogt_y(double %x) { -; ALL-LABEL: ogt_y: -; ALL: # %bb.0: -; ALL-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; ALL-NEXT: retq +; CHECK-LABEL: ogt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq %c = fcmp ogt double %x, -0.000000e+00 %d = select i1 %c, double %x, double -0.000000e+00 ret double %d } define double @olt_y(double %x) { -; ALL-LABEL: olt_y: -; ALL: # %bb.0: -; ALL-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; ALL-NEXT: retq +; CHECK-LABEL: olt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq %c = fcmp olt double %x, -0.000000e+00 %d = select i1 %c, double %x, double -0.000000e+00 ret double %d } define double @ogt_inverse_y(double %x) { -; STRICT-LABEL: ogt_inverse_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; STRICT-NEXT: minsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ogt_inverse_y: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ogt_inverse_y: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ogt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ogt double %x, -0.000000e+00 %d = select i1 %c, double -0.000000e+00, double %x ret double %d } define double @olt_inverse_y(double %x) { -; STRICT-LABEL: olt_inverse_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; STRICT-NEXT: maxsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: olt_inverse_y: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: olt_inverse_y: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: olt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp olt double %x, -0.000000e+00 %d = select i1 %c, double -0.000000e+00, double %x ret double %d } define double @oge_y(double %x) { -; STRICT-LABEL: oge_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] -; STRICT-NEXT: cmplesd %xmm1, %xmm0 -; STRICT-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] -; STRICT-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; STRICT-NEXT: movapd %xmm2, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: oge_y: -; RELAX: # %bb.0: -; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: oge_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: cmplesd %xmm1, %xmm0 +; CHECK-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] +; CHECK-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: movapd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp oge double %x, -0.000000e+00 %d = select i1 %c, double %x, double -0.000000e+00 ret double %d } define double @ole_y(double %x) { -; STRICT-LABEL: ole_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: cmplesd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] -; STRICT-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; STRICT-NEXT: movapd %xmm2, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: ole_y: -; RELAX: # %bb.0: -; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: ole_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: cmplesd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] +; CHECK-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: movapd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp ole double %x, -0.000000e+00 %d = select i1 %c, double %x, double -0.000000e+00 ret double %d } define double @oge_inverse_y(double %x) { -; STRICT-LABEL: oge_inverse_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] -; STRICT-NEXT: cmplesd %xmm1, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: oge_inverse_y: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: oge_inverse_y: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; RELAX-LABEL: oge_inverse_y: +; RELAX: # %bb.0: +; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: oge_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: cmplesd %xmm1, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp oge double %x, -0.000000e+00 %d = select i1 %c, double -0.000000e+00, double %x ret double %d } define double @ole_inverse_y(double %x) { -; STRICT-LABEL: ole_inverse_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: cmplesd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ole_inverse_y: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ole_inverse_y: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; RELAX-LABEL: ole_inverse_y: +; RELAX: # %bb.0: +; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; RELAX-NEXT: retq +; CHECK-LABEL: ole_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: cmplesd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ole double %x, -0.000000e+00 %d = select i1 %c, double -0.000000e+00, double %x ret double %d } define double @ugt_y(double %x) { -; STRICT-LABEL: ugt_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: cmpnlesd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] -; STRICT-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; STRICT-NEXT: movapd %xmm2, %xmm0 -; STRICT-NEXT: retq -; ; RELAX-LABEL: ugt_y: ; RELAX: # %bb.0: ; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; RELAX-NEXT: retq +; CHECK-LABEL: ugt_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: cmpnlesd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] +; CHECK-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: movapd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp ugt double %x, -0.000000e+00 %d = select i1 %c, double %x, double -0.000000e+00 ret double %d } define double @ult_y(double %x) { -; STRICT-LABEL: ult_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] -; STRICT-NEXT: cmpnlesd %xmm1, %xmm0 -; STRICT-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] -; STRICT-NEXT: blendvpd %xmm0, %xmm1, %xmm2 -; STRICT-NEXT: movapd %xmm2, %xmm0 -; STRICT-NEXT: retq -; ; RELAX-LABEL: ult_y: ; RELAX: # %bb.0: ; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; RELAX-NEXT: retq +; CHECK-LABEL: ult_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: cmpnlesd %xmm1, %xmm0 +; CHECK-NEXT: movapd {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0] +; CHECK-NEXT: blendvpd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: movapd %xmm2, %xmm0 +; CHECK-NEXT: retq %c = fcmp ult double %x, -0.000000e+00 %d = select i1 %c, double %x, double -0.000000e+00 ret double %d } define double @ugt_inverse_y(double %x) { -; STRICT-LABEL: ugt_inverse_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: cmpnlesd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ugt_inverse_y: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ugt_inverse_y: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ugt_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: cmpnlesd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ugt double %x, -0.000000e+00 %d = select i1 %c, double -0.000000e+00, double %x ret double %d } define double @ult_inverse_y(double %x) { -; STRICT-LABEL: ult_inverse_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm1 -; STRICT-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] -; STRICT-NEXT: cmpnlesd %xmm1, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ult_inverse_y: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ult_inverse_y: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ult_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm1 +; CHECK-NEXT: movsd {{.*#+}} xmm0 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: cmpnlesd %xmm1, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ult double %x, -0.000000e+00 %d = select i1 %c, double -0.000000e+00, double %x ret double %d } define double @uge_y(double %x) { -; STRICT-LABEL: uge_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; STRICT-NEXT: maxsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: uge_y: -; RELAX: # %bb.0: -; RELAX-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: uge_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp uge double %x, -0.000000e+00 %d = select i1 %c, double %x, double -0.000000e+00 ret double %d } define double @ule_y(double %x) { -; STRICT-LABEL: ule_y: -; STRICT: # %bb.0: -; STRICT-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; STRICT-NEXT: minsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: ule_y: -; RELAX: # %bb.0: -; RELAX-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: ule_y: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %c = fcmp ule double %x, -0.000000e+00 %d = select i1 %c, double %x, double -0.000000e+00 ret double %d } define double @uge_inverse_y(double %x) { -; STRICT-LABEL: uge_inverse_y: -; STRICT: # %bb.0: -; STRICT-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: uge_inverse_y: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: uge_inverse_y: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: uge_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq %c = fcmp uge double %x, -0.000000e+00 %d = select i1 %c, double -0.000000e+00, double %x ret double %d } define double @ule_inverse_y(double %x) { -; STRICT-LABEL: ule_inverse_y: -; STRICT: # %bb.0: -; STRICT-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: ule_inverse_y: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: ule_inverse_y: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [-0.0E+0,0.0E+0] -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: ule_inverse_y: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq %c = fcmp ule double %x, -0.000000e+00 %d = select i1 %c, double -0.000000e+00, double %x ret double %d @@ -988,332 +654,196 @@ define double @ule_inverse_y(double %x) { ; Test a few more misc. cases. define double @clampTo3k_a(double %x) { -; STRICT-LABEL: clampTo3k_a: -; STRICT: # %bb.0: -; STRICT-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; STRICT-NEXT: minsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: clampTo3k_a: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: clampTo3k_a: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: clampTo3k_a: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %t0 = fcmp ogt double %x, 3.000000e+03 %y = select i1 %t0, double 3.000000e+03, double %x ret double %y } define double @clampTo3k_b(double %x) { -; STRICT-LABEL: clampTo3k_b: -; STRICT: # %bb.0: -; STRICT-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: clampTo3k_b: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: clampTo3k_b: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: clampTo3k_b: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq %t0 = fcmp uge double %x, 3.000000e+03 %y = select i1 %t0, double 3.000000e+03, double %x ret double %y } define double @clampTo3k_c(double %x) { -; STRICT-LABEL: clampTo3k_c: -; STRICT: # %bb.0: -; STRICT-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; STRICT-NEXT: maxsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: clampTo3k_c: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: clampTo3k_c: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: clampTo3k_c: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %t0 = fcmp olt double %x, 3.000000e+03 %y = select i1 %t0, double 3.000000e+03, double %x ret double %y } define double @clampTo3k_d(double %x) { -; STRICT-LABEL: clampTo3k_d: -; STRICT: # %bb.0: -; STRICT-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: clampTo3k_d: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: clampTo3k_d: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: clampTo3k_d: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq %t0 = fcmp ule double %x, 3.000000e+03 %y = select i1 %t0, double 3.000000e+03, double %x ret double %y } define double @clampTo3k_e(double %x) { -; STRICT-LABEL: clampTo3k_e: -; STRICT: # %bb.0: -; STRICT-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; STRICT-NEXT: maxsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: clampTo3k_e: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: clampTo3k_e: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: clampTo3k_e: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: maxsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %t0 = fcmp olt double %x, 3.000000e+03 %y = select i1 %t0, double 3.000000e+03, double %x ret double %y } define double @clampTo3k_f(double %x) { -; STRICT-LABEL: clampTo3k_f: -; STRICT: # %bb.0: -; STRICT-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: clampTo3k_f: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: clampTo3k_f: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; FINITE-NEXT: maxsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: clampTo3k_f: +; CHECK: # %bb.0: +; CHECK-NEXT: maxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq %t0 = fcmp ule double %x, 3.000000e+03 %y = select i1 %t0, double 3.000000e+03, double %x ret double %y } define double @clampTo3k_g(double %x) { -; STRICT-LABEL: clampTo3k_g: -; STRICT: # %bb.0: -; STRICT-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; STRICT-NEXT: minsd %xmm0, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: clampTo3k_g: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: clampTo3k_g: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: clampTo3k_g: +; CHECK: # %bb.0: +; CHECK-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] +; CHECK-NEXT: minsd %xmm0, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %t0 = fcmp ogt double %x, 3.000000e+03 %y = select i1 %t0, double 3.000000e+03, double %x ret double %y } define double @clampTo3k_h(double %x) { -; STRICT-LABEL: clampTo3k_h: -; STRICT: # %bb.0: -; STRICT-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; STRICT-NEXT: retq -; -; UNSAFE-LABEL: clampTo3k_h: -; UNSAFE: # %bb.0: -; UNSAFE-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; UNSAFE-NEXT: retq -; -; FINITE-LABEL: clampTo3k_h: -; FINITE: # %bb.0: -; FINITE-NEXT: movsd {{.*#+}} xmm1 = [3.0E+3,0.0E+0] -; FINITE-NEXT: minsd %xmm0, %xmm1 -; FINITE-NEXT: movapd %xmm1, %xmm0 -; FINITE-NEXT: retq +; CHECK-LABEL: clampTo3k_h: +; CHECK: # %bb.0: +; CHECK-NEXT: minsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; CHECK-NEXT: retq %t0 = fcmp uge double %x, 3.000000e+03 %y = select i1 %t0, double 3.000000e+03, double %x ret double %y } define <2 x double> @test_maxpd(<2 x double> %x, <2 x double> %y) { -; STRICT-LABEL: test_maxpd: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: cmplepd %xmm2, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: test_maxpd: -; RELAX: # %bb.0: -; RELAX-NEXT: maxpd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: test_maxpd: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: cmplepd %xmm2, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %max_is_x = fcmp oge <2 x double> %x, %y %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y ret <2 x double> %max } define <2 x double> @test_minpd(<2 x double> %x, <2 x double> %y) { -; STRICT-LABEL: test_minpd: -; STRICT: # %bb.0: -; STRICT-NEXT: movapd %xmm0, %xmm2 -; STRICT-NEXT: cmplepd %xmm1, %xmm0 -; STRICT-NEXT: blendvpd %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movapd %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: test_minpd: -; RELAX: # %bb.0: -; RELAX-NEXT: minpd %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: test_minpd: +; CHECK: # %bb.0: +; CHECK-NEXT: movapd %xmm0, %xmm2 +; CHECK-NEXT: cmplepd %xmm1, %xmm0 +; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movapd %xmm1, %xmm0 +; CHECK-NEXT: retq %min_is_x = fcmp ole <2 x double> %x, %y %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y ret <2 x double> %min } define <4 x float> @test_maxps(<4 x float> %x, <4 x float> %y) { -; STRICT-LABEL: test_maxps: -; STRICT: # %bb.0: -; STRICT-NEXT: movaps %xmm0, %xmm2 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: cmpleps %xmm2, %xmm0 -; STRICT-NEXT: blendvps %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: test_maxps: -; RELAX: # %bb.0: -; RELAX-NEXT: maxps %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: test_maxps: +; CHECK: # %bb.0: +; CHECK-NEXT: movaps %xmm0, %xmm2 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: cmpleps %xmm2, %xmm0 +; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: retq %max_is_x = fcmp oge <4 x float> %x, %y %max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y ret <4 x float> %max } define <4 x float> @test_minps(<4 x float> %x, <4 x float> %y) { -; STRICT-LABEL: test_minps: -; STRICT: # %bb.0: -; STRICT-NEXT: movaps %xmm0, %xmm2 -; STRICT-NEXT: cmpleps %xmm1, %xmm0 -; STRICT-NEXT: blendvps %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: test_minps: -; RELAX: # %bb.0: -; RELAX-NEXT: minps %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: test_minps: +; CHECK: # %bb.0: +; CHECK-NEXT: movaps %xmm0, %xmm2 +; CHECK-NEXT: cmpleps %xmm1, %xmm0 +; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: retq %min_is_x = fcmp ole <4 x float> %x, %y %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y ret <4 x float> %min } define <2 x float> @test_maxps_illegal_v2f32(<2 x float> %x, <2 x float> %y) { -; STRICT-LABEL: test_maxps_illegal_v2f32: -; STRICT: # %bb.0: -; STRICT-NEXT: movaps %xmm0, %xmm2 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: cmpleps %xmm2, %xmm0 -; STRICT-NEXT: blendvps %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: test_maxps_illegal_v2f32: -; RELAX: # %bb.0: -; RELAX-NEXT: maxps %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: test_maxps_illegal_v2f32: +; CHECK: # %bb.0: +; CHECK-NEXT: movaps %xmm0, %xmm2 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: cmpleps %xmm2, %xmm0 +; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: retq %max_is_x = fcmp oge <2 x float> %x, %y %max = select <2 x i1> %max_is_x, <2 x float> %x, <2 x float> %y ret <2 x float> %max } define <2 x float> @test_minps_illegal_v2f32(<2 x float> %x, <2 x float> %y) { -; STRICT-LABEL: test_minps_illegal_v2f32: -; STRICT: # %bb.0: -; STRICT-NEXT: movaps %xmm0, %xmm2 -; STRICT-NEXT: cmpleps %xmm1, %xmm0 -; STRICT-NEXT: blendvps %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: test_minps_illegal_v2f32: -; RELAX: # %bb.0: -; RELAX-NEXT: minps %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: test_minps_illegal_v2f32: +; CHECK: # %bb.0: +; CHECK-NEXT: movaps %xmm0, %xmm2 +; CHECK-NEXT: cmpleps %xmm1, %xmm0 +; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: retq %min_is_x = fcmp ole <2 x float> %x, %y %min = select <2 x i1> %min_is_x, <2 x float> %x, <2 x float> %y ret <2 x float> %min } define <3 x float> @test_maxps_illegal_v3f32(<3 x float> %x, <3 x float> %y) { -; STRICT-LABEL: test_maxps_illegal_v3f32: -; STRICT: # %bb.0: -; STRICT-NEXT: movaps %xmm0, %xmm2 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: cmpleps %xmm2, %xmm0 -; STRICT-NEXT: blendvps %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: test_maxps_illegal_v3f32: -; RELAX: # %bb.0: -; RELAX-NEXT: maxps %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: test_maxps_illegal_v3f32: +; CHECK: # %bb.0: +; CHECK-NEXT: movaps %xmm0, %xmm2 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: cmpleps %xmm2, %xmm0 +; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: retq %max_is_x = fcmp oge <3 x float> %x, %y %max = select <3 x i1> %max_is_x, <3 x float> %x, <3 x float> %y ret <3 x float> %max } define <3 x float> @test_minps_illegal_v3f32(<3 x float> %x, <3 x float> %y) { -; STRICT-LABEL: test_minps_illegal_v3f32: -; STRICT: # %bb.0: -; STRICT-NEXT: movaps %xmm0, %xmm2 -; STRICT-NEXT: cmpleps %xmm1, %xmm0 -; STRICT-NEXT: blendvps %xmm0, %xmm2, %xmm1 -; STRICT-NEXT: movaps %xmm1, %xmm0 -; STRICT-NEXT: retq -; -; RELAX-LABEL: test_minps_illegal_v3f32: -; RELAX: # %bb.0: -; RELAX-NEXT: minps %xmm1, %xmm0 -; RELAX-NEXT: retq +; CHECK-LABEL: test_minps_illegal_v3f32: +; CHECK: # %bb.0: +; CHECK-NEXT: movaps %xmm0, %xmm2 +; CHECK-NEXT: cmpleps %xmm1, %xmm0 +; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1 +; CHECK-NEXT: movaps %xmm1, %xmm0 +; CHECK-NEXT: retq %min_is_x = fcmp ole <3 x float> %x, %y %min = select <3 x i1> %min_is_x, <3 x float> %x, <3 x float> %y ret <3 x float> %min @@ -1322,10 +852,10 @@ define <3 x float> @test_minps_illegal_v3f32(<3 x float> %x, <3 x float> %y) { ; OSS-Fuzz #13838 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=13838 define float @ossfuzz13838(float %x) { -; ALL-LABEL: ossfuzz13838: -; ALL: # %bb.0: # %bb -; ALL-NEXT: movss {{.*#+}} xmm0 = [2.55E+2,0.0E+0,0.0E+0,0.0E+0] -; ALL-NEXT: retq +; CHECK-LABEL: ossfuzz13838: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: movss {{.*#+}} xmm0 = [2.55E+2,0.0E+0,0.0E+0,0.0E+0] +; CHECK-NEXT: retq bb: %cmp2 = fcmp fast olt float %x, 2.550000e+02 %B1 = urem i1 %cmp2, %cmp2 diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir index 0c5c3669268c0..62f7ee096a3ff 100644 --- a/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir +++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir @@ -285,7 +285,7 @@ body: | ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp %22:gr32 = MOV32r0 implicit-def dead $eflags - %21:gr64 = SUBREG_TO_REG 0, %22, %subreg.sub_32bit + %21:gr64 = SUBREG_TO_REG %22, %subreg.sub_32bit $rdi = COPY %21 STATEPOINT 2, 5, 2, undef %24:gr64, killed $rdi, undef $rsi, 2, 0, 2, 0, 2, 37, 2, 0, 2, 2, 2, 0, 2, 43, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 10, 2, 1, 2, 6, 2, 0, 2, 4, 2, 1, 2, 0, 2, 0, 2, 7, 2, 0, 2, 0, 2, 0, 2, 7, 2, 0, 2, 0, 2, 0, 2, 2, 2, 4, 2, 5, 2, 0, 2, 2, 2, 0, 2, 7, 2, 0, 2, 7, 2, 0, 2, 1, 2, 0, 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp diff --git a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir index 5ce76a3e46f66..ae0a1e03e78e3 100644 --- a/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir +++ b/llvm/test/CodeGen/X86/statepoint-invoke-ra.mir @@ -235,7 +235,7 @@ body: | EH_LABEL ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp %20:gr32 = MOV32r0 implicit-def dead $eflags - %21:gr64 = SUBREG_TO_REG 0, %20, %subreg.sub_32bit + %21:gr64 = SUBREG_TO_REG %20, %subreg.sub_32bit $edi = COPY %20 $rsi = COPY killed %21 $ecx = COPY %7 diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll index a33993444d023..2a0710e3249a6 100644 --- a/llvm/test/CodeGen/X86/statepoint-vreg-details.ll +++ b/llvm/test/CodeGen/X86/statepoint-vreg-details.ll @@ -50,7 +50,7 @@ define void @test_mixed(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace( ; CHECK-VREG: %0:gr64 = COPY $rdi ; CHECK-VREG: %3:gr64, %4:gr64, %5:gr64 = STATEPOINT 0, 0, 0, @func, 2, 0, 2, 0, 2, 0, 2, 4, %2(tied-def 0), 2, 0, %1(tied-def 1), %0(tied-def 2), 2, 0, 2, 4, 0, 0, 1, 1, 2, 2, 3, 3, csr_64, implicit-def $rsp, implicit-def $ssp ; CHECK-VREG: %6:gr32 = MOV32r0 implicit-def dead $eflags -; CHECK-VREG: %7:gr64 = SUBREG_TO_REG 0, killed %6, %subreg.sub_32bit +; CHECK-VREG: %7:gr64 = SUBREG_TO_REG killed %6, %subreg.sub_32bit ; CHECK-VREG: $rdi = COPY %5 ; CHECK-VREG: $rsi = COPY %7 ; CHECK-VREG: $rdx = COPY %4 @@ -361,7 +361,7 @@ define ptr addrspace(1) @test_isel_sched(ptr addrspace(1) %0, ptr addrspace(1) % ;CHECK-VREG: TEST32rr %2, %2, implicit-def $eflags ;CHECK-VREG: %3:gr64 = CMOV64rr %1, %0, 4, implicit $eflags ;CHECK-VREG: %4:gr32 = MOV32r0 implicit-def dead $eflags -;CHECK-VREG: %5:gr64 = SUBREG_TO_REG 0, killed %4, %subreg.sub_32bit +;CHECK-VREG: %5:gr64 = SUBREG_TO_REG killed %4, %subreg.sub_32bit ;CHECK-VREG: $rdi = COPY %5 ;CHECK-VREG: $rsi = COPY %3 ;CHECK-VREG: %6:gr64, %7:gr64 = STATEPOINT 10, 0, 2, @bar, $rdi, $rsi, 2, 0, 2, 0, 2, 0, 2, 2, %1(tied-def 0), %0(tied-def 1), 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp diff --git a/llvm/test/CodeGen/X86/sub-i512.ll b/llvm/test/CodeGen/X86/sub-i512.ll index b2b57fe923adc..e968e5e27e2ce 100644 --- a/llvm/test/CodeGen/X86/sub-i512.ll +++ b/llvm/test/CodeGen/X86/sub-i512.ll @@ -413,39 +413,150 @@ define i512 @test_dec_i512_mem(ptr %p0) nounwind { ; AVX2-NEXT: movq %rcx, 56(%rax) ; AVX2-NEXT: retq ; -; AVX512-LABEL: test_dec_i512_mem: -; AVX512: # %bb.0: -; AVX512-NEXT: movq %rdi, %rax -; AVX512-NEXT: movq 56(%rsi), %rcx -; AVX512-NEXT: movq 48(%rsi), %rdx -; AVX512-NEXT: movq 40(%rsi), %rdi -; AVX512-NEXT: movq 32(%rsi), %r8 -; AVX512-NEXT: movq 24(%rsi), %r9 -; AVX512-NEXT: movq 16(%rsi), %r10 -; AVX512-NEXT: movq (%rsi), %r11 -; AVX512-NEXT: movq 8(%rsi), %rsi -; AVX512-NEXT: addq $-1, %r11 -; AVX512-NEXT: adcq $-1, %rsi -; AVX512-NEXT: adcq $-1, %r10 -; AVX512-NEXT: adcq $-1, %r9 -; AVX512-NEXT: adcq $-1, %r8 -; AVX512-NEXT: adcq $-1, %rdi -; AVX512-NEXT: adcq $-1, %rdx -; AVX512-NEXT: adcq $-1, %rcx -; AVX512-NEXT: movq %r11, (%rax) -; AVX512-NEXT: movq %rsi, 8(%rax) -; AVX512-NEXT: movq %r10, 16(%rax) -; AVX512-NEXT: movq %r9, 24(%rax) -; AVX512-NEXT: movq %r8, 32(%rax) -; AVX512-NEXT: movq %rdi, 40(%rax) -; AVX512-NEXT: movq %rdx, 48(%rax) -; AVX512-NEXT: movq %rcx, 56(%rax) -; AVX512-NEXT: retq +; AVX512F-LABEL: test_dec_i512_mem: +; AVX512F: # %bb.0: +; AVX512F-NEXT: movq %rdi, %rax +; AVX512F-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm1 = -1 +; AVX512F-NEXT: vpaddq %zmm1, %zmm0, %zmm1 +; AVX512F-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %ecx +; AVX512F-NEXT: vptestnmq %zmm0, %zmm0, %k0 +; AVX512F-NEXT: kmovw %k0, %edx +; AVX512F-NEXT: movzbl %dl, %edx +; AVX512F-NEXT: leal (%rdx,%rcx,2), %ecx +; AVX512F-NEXT: xorl %edx, %ecx +; AVX512F-NEXT: kmovw %ecx, %k1 +; AVX512F-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_dec_i512_mem: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: movq %rdi, %rax +; AVX512VL-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512VL-NEXT: vptestnmq %zmm0, %zmm0, %k0 +; AVX512VL-NEXT: kmovb %k0, %ecx +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm1 = -1 +; AVX512VL-NEXT: vpaddq %zmm1, %zmm0, %zmm1 +; AVX512VL-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovd %k0, %edx +; AVX512VL-NEXT: leal (%rcx,%rdx,2), %edx +; AVX512VL-NEXT: xorl %ecx, %edx +; AVX512VL-NEXT: kmovd %edx, %k1 +; AVX512VL-NEXT: vmovdqa64 %zmm0, %zmm1 {%k1} +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq %a0 = load i512, ptr %p0 %r = sub i512 %a0, 1 ret i512 %r } +define i512 @test_sub_i512_mem_mem(ptr %p0, ptr %p1) nounwind { +; SSE-LABEL: test_sub_i512_mem_mem: +; SSE: # %bb.0: +; SSE-NEXT: pushq %rbx +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: movq 56(%rsi), %rcx +; SSE-NEXT: movq (%rsi), %rdi +; SSE-NEXT: subq (%rdx), %rdi +; SSE-NEXT: movq 8(%rsi), %r8 +; SSE-NEXT: sbbq 8(%rdx), %r8 +; SSE-NEXT: movq 16(%rsi), %r9 +; SSE-NEXT: sbbq 16(%rdx), %r9 +; SSE-NEXT: movq 24(%rsi), %r10 +; SSE-NEXT: sbbq 24(%rdx), %r10 +; SSE-NEXT: movq 32(%rsi), %r11 +; SSE-NEXT: sbbq 32(%rdx), %r11 +; SSE-NEXT: movq 40(%rsi), %rbx +; SSE-NEXT: sbbq 40(%rdx), %rbx +; SSE-NEXT: movq 48(%rsi), %rsi +; SSE-NEXT: sbbq 48(%rdx), %rsi +; SSE-NEXT: sbbq 56(%rdx), %rcx +; SSE-NEXT: movq %rdi, (%rax) +; SSE-NEXT: movq %r8, 8(%rax) +; SSE-NEXT: movq %r9, 16(%rax) +; SSE-NEXT: movq %r10, 24(%rax) +; SSE-NEXT: movq %r11, 32(%rax) +; SSE-NEXT: movq %rbx, 40(%rax) +; SSE-NEXT: movq %rsi, 48(%rax) +; SSE-NEXT: movq %rcx, 56(%rax) +; SSE-NEXT: popq %rbx +; SSE-NEXT: retq +; +; AVX2-LABEL: test_sub_i512_mem_mem: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: movq %rdi, %rax +; AVX2-NEXT: movq (%rsi), %rcx +; AVX2-NEXT: subq (%rdx), %rcx +; AVX2-NEXT: movq 8(%rsi), %rdi +; AVX2-NEXT: sbbq 8(%rdx), %rdi +; AVX2-NEXT: movq 16(%rsi), %r8 +; AVX2-NEXT: sbbq 16(%rdx), %r8 +; AVX2-NEXT: movq 24(%rsi), %r9 +; AVX2-NEXT: sbbq 24(%rdx), %r9 +; AVX2-NEXT: movq 32(%rsi), %r10 +; AVX2-NEXT: sbbq 32(%rdx), %r10 +; AVX2-NEXT: movq 40(%rsi), %r11 +; AVX2-NEXT: sbbq 40(%rdx), %r11 +; AVX2-NEXT: movq 48(%rsi), %rbx +; AVX2-NEXT: sbbq 48(%rdx), %rbx +; AVX2-NEXT: movq 56(%rsi), %rsi +; AVX2-NEXT: sbbq 56(%rdx), %rsi +; AVX2-NEXT: movq %rcx, (%rax) +; AVX2-NEXT: movq %rdi, 8(%rax) +; AVX2-NEXT: movq %r8, 16(%rax) +; AVX2-NEXT: movq %r9, 24(%rax) +; AVX2-NEXT: movq %r10, 32(%rax) +; AVX2-NEXT: movq %r11, 40(%rax) +; AVX2-NEXT: movq %rbx, 48(%rax) +; AVX2-NEXT: movq %rsi, 56(%rax) +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: retq +; +; AVX512F-LABEL: test_sub_i512_mem_mem: +; AVX512F: # %bb.0: +; AVX512F-NEXT: movq %rdi, %rax +; AVX512F-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512F-NEXT: vpsubq (%rdx), %zmm0, %zmm1 +; AVX512F-NEXT: vpcmpnleuq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %ecx +; AVX512F-NEXT: vptestnmq %zmm1, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %edx +; AVX512F-NEXT: movzbl %dl, %edx +; AVX512F-NEXT: leal (%rdx,%rcx,2), %ecx +; AVX512F-NEXT: xorl %edx, %ecx +; AVX512F-NEXT: kmovw %ecx, %k1 +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm0 = -1 +; AVX512F-NEXT: vpaddq %zmm0, %zmm1, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_sub_i512_mem_mem: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqu64 (%rsi), %zmm0 +; AVX512VL-NEXT: movq %rdi, %rax +; AVX512VL-NEXT: vpsubq (%rdx), %zmm0, %zmm1 +; AVX512VL-NEXT: vpcmpnleuq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovd %k0, %ecx +; AVX512VL-NEXT: vptestnmq %zmm1, %zmm1, %k0 +; AVX512VL-NEXT: kmovb %k0, %edx +; AVX512VL-NEXT: leal (%rdx,%rcx,2), %ecx +; AVX512VL-NEXT: xorl %edx, %ecx +; AVX512VL-NEXT: kmovd %ecx, %k1 +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm0 = -1 +; AVX512VL-NEXT: vpaddq %zmm0, %zmm1, %zmm1 {%k1} +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq + %a0 = load i512, ptr %p0 + %a1 = load i512, ptr %p1 + %r = sub i512 %a0, %a1 + ret i512 %r +} + define void @test_dec_i512_rmw(ptr %p0) nounwind { ; CHECK-LABEL: test_dec_i512_rmw: ; CHECK: # %bb.0: @@ -459,19 +570,97 @@ define void @test_dec_i512_rmw(ptr %p0) nounwind { ; CHECK-NEXT: adcq $-1, 56(%rdi) ; CHECK-NEXT: retq ; -; AVX512-LABEL: test_dec_i512_rmw: -; AVX512: # %bb.0: -; AVX512-NEXT: addq $-1, (%rdi) -; AVX512-NEXT: adcq $-1, 8(%rdi) -; AVX512-NEXT: adcq $-1, 16(%rdi) -; AVX512-NEXT: adcq $-1, 24(%rdi) -; AVX512-NEXT: adcq $-1, 32(%rdi) -; AVX512-NEXT: adcq $-1, 40(%rdi) -; AVX512-NEXT: adcq $-1, 48(%rdi) -; AVX512-NEXT: adcq $-1, 56(%rdi) -; AVX512-NEXT: retq +; AVX512F-LABEL: test_dec_i512_rmw: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0 +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm1 = -1 +; AVX512F-NEXT: vpaddq %zmm1, %zmm0, %zmm1 +; AVX512F-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: vptestnmq %zmm0, %zmm0, %k0 +; AVX512F-NEXT: kmovw %k0, %ecx +; AVX512F-NEXT: movzbl %cl, %ecx +; AVX512F-NEXT: leal (%rcx,%rax,2), %eax +; AVX512F-NEXT: xorl %ecx, %eax +; AVX512F-NEXT: kmovw %eax, %k0 +; AVX512F-NEXT: knotw %k0, %k1 +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) {%k1} +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_dec_i512_rmw: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqu64 (%rdi), %zmm0 +; AVX512VL-NEXT: vptestnmq %zmm0, %zmm0, %k0 +; AVX512VL-NEXT: kmovb %k0, %eax +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm1 = -1 +; AVX512VL-NEXT: vpaddq %zmm1, %zmm0, %zmm1 +; AVX512VL-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovd %k0, %ecx +; AVX512VL-NEXT: leal (%rax,%rcx,2), %ecx +; AVX512VL-NEXT: xorl %eax, %ecx +; AVX512VL-NEXT: kmovd %ecx, %k0 +; AVX512VL-NEXT: knotb %k0, %k1 +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rdi) {%k1} +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq %a0 = load i512, ptr %p0 %r = sub i512 %a0, 1 store i512 %r, ptr %p0 ret void } + +define void @test_sub_i512_rmw(ptr %p0) nounwind { +; CHECK-LABEL: test_sub_i512_rmw: +; CHECK: # %bb.0: +; CHECK-NEXT: addq $-9, (%rdi) +; CHECK-NEXT: adcq $-1, 8(%rdi) +; CHECK-NEXT: adcq $-1, 16(%rdi) +; CHECK-NEXT: adcq $-1, 24(%rdi) +; CHECK-NEXT: adcq $-1, 32(%rdi) +; CHECK-NEXT: adcq $-1, 40(%rdi) +; CHECK-NEXT: adcq $-1, 48(%rdi) +; CHECK-NEXT: adcq $-1, 56(%rdi) +; CHECK-NEXT: retq +; +; AVX512F-LABEL: test_sub_i512_rmw: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0 +; AVX512F-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 +; AVX512F-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %eax +; AVX512F-NEXT: vpternlogd {{.*#+}} zmm2 = -1 +; AVX512F-NEXT: vpcmpeqq %zmm2, %zmm1, %k0 +; AVX512F-NEXT: kmovw %k0, %ecx +; AVX512F-NEXT: movzbl %cl, %ecx +; AVX512F-NEXT: leal (%rcx,%rax,2), %eax +; AVX512F-NEXT: xorl %ecx, %eax +; AVX512F-NEXT: kmovw %eax, %k1 +; AVX512F-NEXT: vmovq {{.*#+}} xmm2 = [18446744073709551608,0] +; AVX512F-NEXT: vpaddq %zmm2, %zmm0, %zmm1 {%k1} +; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: test_sub_i512_rmw: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vmovdqu64 (%rdi), %zmm0 +; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 +; AVX512VL-NEXT: vpcmpltuq %zmm0, %zmm1, %k0 +; AVX512VL-NEXT: kmovd %k0, %eax +; AVX512VL-NEXT: vpternlogd {{.*#+}} zmm2 = -1 +; AVX512VL-NEXT: vpcmpeqq %zmm2, %zmm1, %k0 +; AVX512VL-NEXT: kmovb %k0, %ecx +; AVX512VL-NEXT: leal (%rcx,%rax,2), %eax +; AVX512VL-NEXT: xorl %ecx, %eax +; AVX512VL-NEXT: kmovd %eax, %k1 +; AVX512VL-NEXT: vmovq {{.*#+}} xmm2 = [18446744073709551608,0] +; AVX512VL-NEXT: vpaddq %zmm2, %zmm0, %zmm1 {%k1} +; AVX512VL-NEXT: vmovdqu64 %zmm1, (%rdi) +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq + %a0 = load i512, ptr %p0 + %r = sub i512 %a0, 9 + store i512 %r, ptr %p0 + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX512: {{.*}} diff --git a/llvm/test/CodeGen/X86/subreg-fail.mir b/llvm/test/CodeGen/X86/subreg-fail.mir index c8146f099b814..888afa8aa4915 100644 --- a/llvm/test/CodeGen/X86/subreg-fail.mir +++ b/llvm/test/CodeGen/X86/subreg-fail.mir @@ -22,9 +22,9 @@ body: | ; CHECK-NEXT: MOV32mr undef %10:gr64, 1, $noreg, 0, $noreg, [[LEA64r]].sub_32bit :: (volatile store (s32) into `ptr undef`) ; CHECK-NEXT: RET 0, undef $eax %0:gr32 = MOV32rm undef %1:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`) - %2:gr64_nosp = SUBREG_TO_REG 0, killed %0, %subreg.sub_32bit + %2:gr64_nosp = SUBREG_TO_REG killed %0, %subreg.sub_32bit %3:gr32 = MOV32rm undef %4:gr64, 1, $noreg, 0, $noreg :: (volatile load (s32) from `ptr undef`) - %5:gr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32bit + %5:gr64 = SUBREG_TO_REG killed %3, %subreg.sub_32bit %6:gr64 = COPY killed %5 %6:gr64 = SHL64ri %6, 32, implicit-def dead $eflags %7:gr64 = LEA64r killed %6, 1, killed %2, 256, $noreg diff --git a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll index 7ce983869ce7d..acfa5d59fcb2f 100644 --- a/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll +++ b/llvm/test/CodeGen/X86/tail-dup-asm-goto.ll @@ -96,7 +96,7 @@ define void @ceph_con_v2_try_read(i32 %__trans_tmp_3.sroa.0.0.copyload, i1 %tobo ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit ; CHECK-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.0.skip.i.i, 1, $noreg, 0, $noreg ; CHECK-NEXT: $rdi = COPY [[LEA64r]] ; CHECK-NEXT: CALL64r killed [[SUBREG_TO_REG]], csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax diff --git a/llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir b/llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir index 2f1ff76fda76c..e90d56e2d2793 100644 --- a/llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir +++ b/llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir @@ -22,7 +22,7 @@ body: | ; LIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; LIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.2: @@ -61,7 +61,7 @@ body: | ; LIMIT-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[SHR32ri3]], %bb.5, [[SHR32ri2]], %bb.4, [[SHR32ri1]], %bb.3, [[MOV32rm]], %bb.2 ; LIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri4]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri1]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri1]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.9: @@ -105,7 +105,7 @@ body: | ; NOLIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; NOLIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.2: @@ -114,7 +114,7 @@ body: | ; NOLIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg ; NOLIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.3: @@ -124,7 +124,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri2]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.4: @@ -134,7 +134,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri3]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.5: @@ -144,7 +144,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri4]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.6: @@ -193,7 +193,7 @@ body: | %10:gr64 = COPY $rdi %13:gr32 = SHR32ri %11, 1, implicit-def dead $eflags %14:gr32 = AND32ri %13, 7, implicit-def dead $eflags - %12:gr64_nosp = SUBREG_TO_REG 0, killed %14, %subreg.sub_32bit + %12:gr64_nosp = SUBREG_TO_REG killed %14, %subreg.sub_32bit bb.1: successors: %bb.2, %bb.3, %bb.4, %bb.5 @@ -226,7 +226,7 @@ body: | %4:gr32 = PHI %3, %bb.5, %2, %bb.4, %1, %bb.3, %0, %bb.2 %19:gr32 = SHR32ri %11, 2, implicit-def dead $eflags %20:gr32 = AND32ri %19, 7, implicit-def dead $eflags - %18:gr64_nosp = SUBREG_TO_REG 0, killed %20, %subreg.sub_32bit + %18:gr64_nosp = SUBREG_TO_REG killed %20, %subreg.sub_32bit bb.8: successors: %bb.9, %bb.10, %bb.11, %bb.12 @@ -279,7 +279,7 @@ body: | ; LIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; LIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.2: @@ -317,7 +317,7 @@ body: | ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri4]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.9: @@ -362,7 +362,7 @@ body: | ; NOLIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; NOLIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.2: @@ -371,7 +371,7 @@ body: | ; NOLIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg ; NOLIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.3: @@ -381,7 +381,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri2]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.4: @@ -391,7 +391,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri3]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.5: @@ -401,7 +401,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri4]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.6: @@ -446,7 +446,7 @@ body: | %10:gr64 = COPY $rdi %13:gr32 = SHR32ri %11, 1, implicit-def dead $eflags %14:gr32 = AND32ri %13, 7, implicit-def dead $eflags - %12:gr64_nosp = SUBREG_TO_REG 0, %14, %subreg.sub_32bit + %12:gr64_nosp = SUBREG_TO_REG %14, %subreg.sub_32bit bb.1: successors: %bb.2, %bb.3, %bb.4, %bb.5, %bb.9 @@ -478,7 +478,7 @@ body: | bb.7: %19:gr32 = SHR32ri %11, 2, implicit-def dead $eflags %20:gr32 = AND32ri %19, 7, implicit-def dead $eflags - %18:gr64_nosp = SUBREG_TO_REG 0, %20, %subreg.sub_32bit + %18:gr64_nosp = SUBREG_TO_REG %20, %subreg.sub_32bit bb.8: successors: %bb.9, %bb.10, %bb.11, %bb.12 @@ -534,7 +534,7 @@ body: | ; LIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; LIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.2: @@ -543,7 +543,7 @@ body: | ; LIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg ; LIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.3: @@ -553,7 +553,7 @@ body: | ; LIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags ; LIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri2]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.4: @@ -563,7 +563,7 @@ body: | ; LIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri3]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.5: @@ -573,7 +573,7 @@ body: | ; LIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags ; LIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; LIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags - ; LIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit + ; LIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri4]], %subreg.sub_32bit ; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg ; LIMIT-NEXT: {{ $}} ; LIMIT-NEXT: bb.6: @@ -615,7 +615,7 @@ body: | ; NOLIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi ; NOLIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG killed [[AND32ri]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.2: @@ -624,7 +624,7 @@ body: | ; NOLIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg ; NOLIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri1]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.3: @@ -634,7 +634,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri2]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.4: @@ -644,7 +644,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri3]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.5: @@ -654,7 +654,7 @@ body: | ; NOLIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags ; NOLIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags ; NOLIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags - ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit + ; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG [[AND32ri4]], %subreg.sub_32bit ; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg ; NOLIMIT-NEXT: {{ $}} ; NOLIMIT-NEXT: bb.6: @@ -693,7 +693,7 @@ body: | %10:gr64 = COPY $rdi %13:gr32 = SHR32ri %11, 1, implicit-def dead $eflags %14:gr32 = AND32ri %13, 7, implicit-def dead $eflags - %12:gr64_nosp = SUBREG_TO_REG 0, killed %14, %subreg.sub_32bit + %12:gr64_nosp = SUBREG_TO_REG killed %14, %subreg.sub_32bit bb.1: successors: %bb.2, %bb.3, %bb.4, %bb.5 @@ -725,7 +725,7 @@ body: | bb.7: %19:gr32 = SHR32ri %11, 2, implicit-def dead $eflags %20:gr32 = AND32ri %19, 7, implicit-def dead $eflags - %18:gr64_nosp = SUBREG_TO_REG 0, killed %20, %subreg.sub_32bit + %18:gr64_nosp = SUBREG_TO_REG killed %20, %subreg.sub_32bit bb.8: successors: %bb.9, %bb.10, %bb.11, %bb.12 diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-permilpd-avx512.ll b/llvm/test/CodeGen/X86/tuning-shuffle-permilpd-avx512.ll index 162ab71fc00d4..e2c8b6df6e744 100644 --- a/llvm/test/CodeGen/X86/tuning-shuffle-permilpd-avx512.ll +++ b/llvm/test/CodeGen/X86/tuning-shuffle-permilpd-avx512.ll @@ -5,6 +5,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 define <8 x double> @transform_VPERMILPSZrr(<8 x double> %a) nounwind { ; CHECK-LABEL: transform_VPERMILPSZrr: diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll b/llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll index cd97946da248f..53bad74552f8a 100644 --- a/llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll +++ b/llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll @@ -5,6 +5,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 define <16 x float> @transform_VPERMILPSZrr(<16 x float> %a) nounwind { ; CHECK-LABEL: transform_VPERMILPSZrr: diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll b/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll index 5ea991f85523e..39a072eeeea4c 100644 --- a/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll +++ b/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll @@ -6,6 +6,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 define <16 x float> @transform_VUNPCKLPDZrr(<16 x float> %a, <16 x float> %b) nounwind { diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll b/llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll index 96155f0300d2d..f8b9dac4c7ba8 100644 --- a/llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll +++ b/llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll @@ -6,6 +6,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 define <16 x float> @transform_VUNPCKLPSZrr(<16 x float> %a, <16 x float> %b) nounwind { ; CHECK-LABEL: transform_VUNPCKLPSZrr: diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll index b79d9e8ce47e9..2eae92b7117e9 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll @@ -1035,6 +1035,36 @@ define <8 x double> @concat_vpermilvar_v8f64_v4f64(<4 x double> %a0, <4 x double ret <8 x double> %res } +define <16 x float> @combine_vexpandd_of_broadcast(float %x, <16 x float> %y, i16 %m) { +; X86-LABEL: combine_vexpandd_of_broadcast: +; X86: # %bb.0: +; X86-NEXT: vpbroadcastd {{[0-9]+}}(%esp), %zmm1 +; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 +; X86-NEXT: vexpandps %zmm1, %zmm0 {%k1} +; X86-NEXT: retl +; +; X64-AVX512F-LABEL: combine_vexpandd_of_broadcast: +; X64-AVX512F: # %bb.0: +; X64-AVX512F-NEXT: vpbroadcastd %xmm0, %zmm0 +; X64-AVX512F-NEXT: kmovw %edi, %k1 +; X64-AVX512F-NEXT: vexpandps %zmm0, %zmm1 {%k1} +; X64-AVX512F-NEXT: vmovdqa64 %zmm1, %zmm0 +; X64-AVX512F-NEXT: retq +; +; X64-AVX512BW-LABEL: combine_vexpandd_of_broadcast: +; X64-AVX512BW: # %bb.0: +; X64-AVX512BW-NEXT: vpbroadcastd %xmm0, %zmm0 +; X64-AVX512BW-NEXT: kmovd %edi, %k1 +; X64-AVX512BW-NEXT: vexpandps %zmm0, %zmm1 {%k1} +; X64-AVX512BW-NEXT: vmovdqa64 %zmm1, %zmm0 +; X64-AVX512BW-NEXT: retq + %xx = insertelement <16 x float> poison, float %x, i32 0 + %vx = shufflevector <16 x float> %xx, <16 x float> poison, <16 x i32> zeroinitializer + %vm = bitcast i16 %m to <16 x i1> + %res = call <16 x float> @llvm.x86.avx512.mask.expand.v16f32(<16 x float> %vx, <16 x float> %y, <16 x i1> %vm) + ret <16 x float> %res +} + ; shift elements up by one define <16 x i32> @combine_vexpandd_as_valignd(<16 x i32> %x) { ; CHECK-LABEL: combine_vexpandd_as_valignd: @@ -1055,3 +1085,38 @@ define <16 x i32> @combine_vcompressd_as_vmov(<16 x i32> %x) { %res = call <16 x i32> @llvm.x86.avx512.mask.compress.v16i32(<16 x i32> %x, <16 x i32> zeroinitializer, <16 x i1> ) ret <16 x i32> %res } + +define <8 x i64> @PR179008(ptr %p0) { +; X86-AVX512F-LABEL: PR179008: +; X86-AVX512F: # %bb.0: +; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-AVX512F-NEXT: movb $31, %cl +; X86-AVX512F-NEXT: kmovw %ecx, %k1 +; X86-AVX512F-NEXT: vmovdqu64 (%eax), %zmm0 {%k1} {z} +; X86-AVX512F-NEXT: retl +; +; X86-AVX512BW-LABEL: PR179008: +; X86-AVX512BW: # %bb.0: +; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-AVX512BW-NEXT: movb $31, %cl +; X86-AVX512BW-NEXT: kmovd %ecx, %k1 +; X86-AVX512BW-NEXT: vmovdqu64 (%eax), %zmm0 {%k1} {z} +; X86-AVX512BW-NEXT: retl +; +; X64-AVX512F-LABEL: PR179008: +; X64-AVX512F: # %bb.0: +; X64-AVX512F-NEXT: movb $31, %al +; X64-AVX512F-NEXT: kmovw %eax, %k1 +; X64-AVX512F-NEXT: vmovdqu64 (%rdi), %zmm0 {%k1} {z} +; X64-AVX512F-NEXT: retq +; +; X64-AVX512BW-LABEL: PR179008: +; X64-AVX512BW: # %bb.0: +; X64-AVX512BW-NEXT: movb $31, %al +; X64-AVX512BW-NEXT: kmovd %eax, %k1 +; X64-AVX512BW-NEXT: vmovdqu64 (%rdi), %zmm0 {%k1} {z} +; X64-AVX512BW-NEXT: retq + %load = load <8 x i64>, ptr %p0, align 1 + %shuf = shufflevector <8 x i64> %load, <8 x i64> , <8 x i32> + ret <8 x i64> %shuf +} diff --git a/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll b/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll index 4021b1bf292bb..5bf936c6e5cec 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll @@ -9,6 +9,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver3 | FileCheck %s --check-prefixes=FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=FAST +; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=haswell | FileCheck %s --check-prefixes=FAST ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s --check-prefixes=FAST diff --git a/llvm/test/CodeGen/X86/vpdpwssd.ll b/llvm/test/CodeGen/X86/vpdpwssd.ll index 2ac2b48af4ce7..ea97800505bc2 100644 --- a/llvm/test/CodeGen/X86/vpdpwssd.ll +++ b/llvm/test/CodeGen/X86/vpdpwssd.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,AVX512VL-VNNI ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,AVX-VNNI +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver6 | FileCheck %s --check-prefixes=CHECK,AVX-VNNI ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+fast-dpwssd | FileCheck %s --check-prefixes=CHECK,AVX512-VNNI ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+avx512vl,+fast-dpwssd | FileCheck %s --check-prefixes=CHECK,AVX512VL-VNNI diff --git a/llvm/test/CodeGen/X86/win64-eh-unwindv2-errors.mir b/llvm/test/CodeGen/X86/win64-eh-unwindv2-errors.mir index 474b776658671..c8eee80bd7265 100644 --- a/llvm/test/CodeGen/X86/win64-eh-unwindv2-errors.mir +++ b/llvm/test/CodeGen/X86/win64-eh-unwindv2-errors.mir @@ -9,9 +9,15 @@ # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/alloc_no_dealloc.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=ALLOC-NO-DEALLOC +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/alloc_no_dealloc.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=ALLOC-NO-DEALLOC # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/alloc_no_dealloc.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/alloc_no_dealloc.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # ALLOC-NO-DEALLOC: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'alloc_no_dealloc': # ALLOC-NO-DEALLOC-SAME: The prolog made a stack allocation, but the epilog did not deallocate it @@ -39,9 +45,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - %t/missed_push.mir \ # RUN: -run-pass=x86-wineh-unwindv2 2>&1 | FileCheck %s \ # RUN: --check-prefix=MISSED-PUSH +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - %t/missed_push.mir \ +# RUN: -passes=x86-wineh-unwindv2 2>&1 | FileCheck %s \ +# RUN: --check-prefix=MISSED-PUSH # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/missed_push.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/missed_push.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # MISSED-PUSH: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'missed_push': # MISSED-PUSH-SAME: The prolog pushed more registers than the epilog popped @@ -72,9 +84,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/dealloc_no_alloc.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=DEALLOC-NO-ALLOC +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/dealloc_no_alloc.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=DEALLOC-NO-ALLOC # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/dealloc_no_alloc.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/dealloc_no_alloc.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # DEALLOC-NO-ALLOC: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'dealloc_no_alloc': # DEALLOC-NO-ALLOC-SAME: The epilog is deallocating a stack allocation, but the prolog did not allocate one @@ -101,10 +119,17 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/dealloc_after_epilog.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=DEALLOC-AFTER-EPILOG +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/dealloc_after_epilog.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=DEALLOC-AFTER-EPILOG # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/dealloc_after_epilog.mir -run-pass=x86-wineh-unwindv2 \ # RUN: -x86-wineh-unwindv2-force-mode=1 | FileCheck %s \ # RUN: --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/dealloc_after_epilog.mir -passes=x86-wineh-unwindv2 \ +# RUN: -x86-wineh-unwindv2-force-mode=1 | FileCheck %s \ +# RUN: --check-prefix=BESTEFFORT # DEALLOC-AFTER-EPILOG: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'dealloc_after_epilog': # DEALLOC-AFTER-EPILOG-SAME: Unexpected lea or add instruction after the epilog @@ -131,9 +156,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/pop_before_dealloc.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=POP-BEFORE-DEALLOC +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/pop_before_dealloc.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=POP-BEFORE-DEALLOC # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/pop_before_dealloc.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/pop_before_dealloc.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # POP-BEFORE-DEALLOC: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'pop_before_dealloc': # POP-BEFORE-DEALLOC-SAME: Cannot pop registers before the stack allocation has been deallocated @@ -165,9 +196,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/mov_no_setframe.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=MOV-NO-SETFRAME +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/mov_no_setframe.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=MOV-NO-SETFRAME # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/mov_no_setframe.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/mov_no_setframe.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # MOV-NO-SETFRAME: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'mov_no_setframe': # MOV-NO-SETFRAME-SAME: The epilog is setting frame back, but prolog did not set it @@ -194,10 +231,17 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/mov_after_epilog.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=MOV-AFTER-EPILOG +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/mov_after_epilog.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=MOV-AFTER-EPILOG # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/mov_after_epilog.mir -run-pass=x86-wineh-unwindv2 \ # RUN: -x86-wineh-unwindv2-force-mode=1 | FileCheck %s \ # RUN: --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/mov_after_epilog.mir -passes=x86-wineh-unwindv2 \ +# RUN: -x86-wineh-unwindv2-force-mode=1 | FileCheck %s \ +# RUN: --check-prefix=BESTEFFORT # MOV-AFTER-EPILOG: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'mov_after_epilog': # MOV-AFTER-EPILOG-SAME: Unexpected mov instruction after the epilog @@ -226,9 +270,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/pop_before_mov.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=POP-BEFORE-MOV +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/pop_before_mov.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=POP-BEFORE-MOV # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/pop_before_mov.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/pop_before_mov.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # POP-BEFORE-MOV: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'pop_before_mov': # POP-BEFORE-MOV-SAME: The epilog is setting the frame back after popping registers @@ -260,9 +310,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/mov_after_dealloc.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=MOV-AFTER-DEALLOC +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/mov_after_dealloc.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=MOV-AFTER-DEALLOC # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/mov_after_dealloc.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/mov_after_dealloc.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # MOV-AFTER-DEALLOC: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'mov_after_dealloc': # MOV-AFTER-DEALLOC-SAME: Cannot set the frame back after the stack allocation has been deallocated @@ -294,9 +350,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - %t/too_many_pops.mir \ # RUN: -run-pass=x86-wineh-unwindv2 2>&1 | FileCheck %s \ # RUN: --check-prefix=TOO-MANY-POPS +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - %t/too_many_pops.mir \ +# RUN: -passes=x86-wineh-unwindv2 2>&1 | FileCheck %s \ +# RUN: --check-prefix=TOO-MANY-POPS # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/too_many_pops.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/too_many_pops.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # TOO-MANY-POPS: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'too_many_pops': # TOO-MANY-POPS-SAME: The epilog is popping more registers than the prolog pushed @@ -326,9 +388,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/pop_in_wrong_order.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=POP-WRONG-ORDER +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/pop_in_wrong_order.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=POP-WRONG-ORDER # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/pop_in_wrong_order.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/pop_in_wrong_order.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # POP-WRONG-ORDER: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'pop_in_wrong_order': # POP-WRONG-ORDER-SAME: The epilog is popping a registers in a different order than the prolog pushed them @@ -360,9 +428,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/pop_after_epilog.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=POP-AFTER-EPILOG +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/pop_after_epilog.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=POP-AFTER-EPILOG # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/pop_after_epilog.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/pop_after_epilog.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # POP-AFTER-EPILOG: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'pop_after_epilog': # POP-AFTER-EPILOG-SAME: Registers are being popped after the epilog @@ -389,9 +463,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/instr_after_epilog.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=INSTR-AFTER-END +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/instr_after_epilog.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=INSTR-AFTER-END # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/instr_after_epilog.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/instr_after_epilog.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # INSTR-AFTER-END: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'instr_after_epilog': # INSTR-AFTER-END-SAME: Unexpected instruction in or after the epilog @@ -418,9 +498,15 @@ body: | # RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ # RUN: %t/dealloc_pop_dealloc.mir -run-pass=x86-wineh-unwindv2 2>&1 | \ # RUN: FileCheck %s --check-prefix=DEALLOC-POP-DEALLOC +# RUN: not --crash llc -mtriple=x86_64-pc-windows-msvc -o - \ +# RUN: %t/dealloc_pop_dealloc.mir -passes=x86-wineh-unwindv2 2>&1 | \ +# RUN: FileCheck %s --check-prefix=DEALLOC-POP-DEALLOC # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/dealloc_pop_dealloc.mir \ # RUN: -run-pass=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ # RUN: FileCheck %s --check-prefix=BESTEFFORT +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %t/dealloc_pop_dealloc.mir \ +# RUN: -passes=x86-wineh-unwindv2 -x86-wineh-unwindv2-force-mode=1 | \ +# RUN: FileCheck %s --check-prefix=BESTEFFORT # DEALLOC-POP-DEALLOC: LLVM ERROR: Windows x64 Unwind v2 is required, but LLVM has generated incompatible code in function 'dealloc_pop_dealloc': # DEALLOC-POP-DEALLOC-SAME: The epilog is deallocating a stack allocation after popping registers diff --git a/llvm/test/CodeGen/X86/win64-eh-unwindv2-push-pop-stack-alloc.mir b/llvm/test/CodeGen/X86/win64-eh-unwindv2-push-pop-stack-alloc.mir index 09a839f00814a..8207ba3d97bd6 100644 --- a/llvm/test/CodeGen/X86/win64-eh-unwindv2-push-pop-stack-alloc.mir +++ b/llvm/test/CodeGen/X86/win64-eh-unwindv2-push-pop-stack-alloc.mir @@ -1,5 +1,7 @@ # RUN: llc -o - %s -mtriple=x86_64-unknown-windows-msvc \ # RUN: -run-pass=x86-wineh-unwindv2 | FileCheck %s +# RUN: llc -o - %s -mtriple=x86_64-unknown-windows-msvc \ +# RUN: -passes=x86-wineh-unwindv2 | FileCheck %s # Regression test for Win x64 unwind v2: in some cases it is better to use # push+pop to adjust the stack, rather than sub+add. This is permitted with diff --git a/llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-epilogs.mir b/llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-epilogs.mir index 7c8e7097ad955..8edc43c83f195 100644 --- a/llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-epilogs.mir +++ b/llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-epilogs.mir @@ -3,11 +3,18 @@ # RUN: -x86-wineh-unwindv2-unwind-codes-threshold=8 \ # RUN: -run-pass=x86-wineh-unwindv2 | FileCheck %s \ # RUN: -check-prefixes=ALLOWLESS,CHECK +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %s \ +# RUN: -x86-wineh-unwindv2-unwind-codes-threshold=8 \ +# RUN: -passes=x86-wineh-unwindv2 | FileCheck %s \ +# RUN: -check-prefixes=ALLOWLESS,CHECK # Allow the default number of unwind codes (255) # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %s \ # RUN: -run-pass=x86-wineh-unwindv2 | FileCheck %s \ # RUN: -check-prefixes=ALLOWMORE,CHECK +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %s \ +# RUN: -passes=x86-wineh-unwindv2 | FileCheck %s \ +# RUN: -check-prefixes=ALLOWMORE,CHECK # CHECK-LABEL: too_many_epilogs # CHECK: SEH_UnwindVersion 2 diff --git a/llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-instr.mir b/llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-instr.mir index c6611a8d25595..44d89356ecae7 100644 --- a/llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-instr.mir +++ b/llvm/test/CodeGen/X86/win64-eh-unwindv2-too-many-instr.mir @@ -3,11 +3,18 @@ # RUN: -x86-wineh-unwindv2-instruction-count-threshold=4 \ # RUN: -run-pass=x86-wineh-unwindv2 | FileCheck %s \ # RUN: -check-prefixes=ALLOWLESS,CHECK +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %s \ +# RUN: -x86-wineh-unwindv2-instruction-count-threshold=4 \ +# RUN: -passes=x86-wineh-unwindv2 | FileCheck %s \ +# RUN: -check-prefixes=ALLOWLESS,CHECK # Allow the default number of instructions per info # RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %s \ # RUN: -run-pass=x86-wineh-unwindv2 | FileCheck %s \ # RUN: -check-prefixes=ALLOWMORE,CHECK +# RUN: llc -mtriple=x86_64-pc-windows-msvc -o - %s \ +# RUN: -passes=x86-wineh-unwindv2 | FileCheck %s \ +# RUN: -check-prefixes=ALLOWMORE,CHECK --- | define dso_local void @too_many_instr() local_unnamed_addr !dbg !9 { diff --git a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll index c5e879c0135f4..bb1a4e5fcb75b 100644 --- a/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll +++ b/llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll @@ -18,6 +18,7 @@ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=BMI2-FAST ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=BMI2-FAST ; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=BMI2-FAST +; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver6 | FileCheck %s --check-prefixes=BMI2-FAST ; Verify that for the X86_64 processors that are known to have poor latency ; double precision shift instructions we do not generate 'shld' or 'shrd' diff --git a/llvm/test/DebugInfo/COFF/fortran-contained-proc.ll b/llvm/test/DebugInfo/COFF/fortran-contained-proc.ll index 82b39d4fa34cb..9d79d913ba57b 100644 --- a/llvm/test/DebugInfo/COFF/fortran-contained-proc.ll +++ b/llvm/test/DebugInfo/COFF/fortran-contained-proc.ll @@ -74,8 +74,8 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #3 ; Function Attrs: mustprogress nofree nosync nounwind readnone speculatable willreturn declare void @llvm.dbg.value(metadata, metadata, metadata) #3 -attributes #0 = { nounwind uwtable "denormal-fp-math"="preserve-sign,preserve-sign" "frame-pointer"="none" "intel-lang"="fortran" "min-legal-vector-width"="0" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" } -attributes #1 = { mustprogress nofree norecurse nosync nounwind uwtable willreturn writeonly "denormal-fp-math"="preserve-sign,preserve-sign" "frame-pointer"="none" "intel-lang"="fortran" "min-legal-vector-width"="0" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" } +attributes #0 = { nounwind uwtable denormal_fpenv(preservesign) "frame-pointer"="none" "intel-lang"="fortran" "min-legal-vector-width"="0" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" } +attributes #1 = { mustprogress nofree norecurse nosync nounwind uwtable willreturn writeonly denormal_fpenv(preservesign) "frame-pointer"="none" "intel-lang"="fortran" "min-legal-vector-width"="0" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" } attributes #2 = { nofree "intel-lang"="fortran" } attributes #3 = { mustprogress nofree nosync nounwind readnone speculatable willreturn } attributes #4 = { nounwind } diff --git a/llvm/test/DebugInfo/Generic/debuginfofinder-macros.ll b/llvm/test/DebugInfo/Generic/debuginfofinder-macros.ll new file mode 100644 index 0000000000000..25d7e8a204926 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/debuginfofinder-macros.ll @@ -0,0 +1,31 @@ +; RUN: opt -passes='print' -disable-output 2>&1 < %s \ +; RUN: | FileCheck %s + +; Macro hierarchy graph: +; CompileUnit +; ├── MacroFile: ./def.c (!2) +; │ ├── Define Macro: 'SIZE' = '5' (!6) +; │ ├── Undef Macro: 'SIZE' (!7) +; │ └── MacroFile: ./def.nested.c (!4) +; │ └── Undef Macro: 'BAZ' (!9) +; └── Define Macro: 'BAZ' (!8) + +; CHECK: Macro: DW_MACINFO_define 'SIZE' = '5' from ./def.c +; CHECK: Macro: DW_MACINFO_undef 'SIZE' from ./def.c +; CHECK: Macro: DW_MACINFO_undef 'BAZ' from ./def.nested.c +; CHECK: Macro: DW_MACINFO_define 'BAZ' at line 1 + +!llvm.module.flags = !{!0, !10} +!llvm.dbg.cu = !{!1} + +!0 = !{i32 7, !"Dwarf Version", i32 0} +!1 = distinct !DICompileUnit(language: DW_LANG_OpenCL, file: !3, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, macros: !{!2, !8}) +!2 = !DIMacroFile(file: !3, nodes: !{!6, !7, !4}) +!3 = !DIFile(filename: "def.c", directory: ".") +!4 = !DIMacroFile(file: !5, nodes: !{!9}) +!5 = !DIFile(filename: "def.nested.c", directory: ".") +!6 = !DIMacro(type: DW_MACINFO_define, line: 1, name: "SIZE", value: "5") +!7 = !DIMacro(type: DW_MACINFO_undef, line: 1, name: "SIZE") +!8 = !DIMacro(type: DW_MACINFO_define, line: 1, name: "BAZ") +!9 = !DIMacro(type: DW_MACINFO_undef, line: 1, name: "BAZ") +!10 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/llvm/test/DebugInfo/Generic/inlined-local-type.ll b/llvm/test/DebugInfo/Generic/inlined-local-type.ll new file mode 100644 index 0000000000000..67e2c4664aff4 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/inlined-local-type.ll @@ -0,0 +1,127 @@ +; RUN: %llc_dwarf -O0 -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck --implicit-check-not "{{DW_TAG|NULL}}" %s + +; inline __attribute__((always_inline)) +; int removed() { struct A {int i;}; struct A a; return a.i++; } +; +; __attribute__((always_inline)) +; int not_removed() { struct B {int i;}; struct B b; return b.i++; } +; +; int foo() { return removed() + not_removed(); }} + +; Ensure that function-local types have the abstract subprogram parent even +; if those subprograms are inlined. + +; CHECK: DW_TAG_compile_unit +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_abstract_origin ({{0x.*}} "not_removed") +; CHECK: DW_TAG_variable +; CHECK: NULL +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_name ("removed") +; CHECK: [[A:0x.*]]: DW_TAG_structure_type +; CHECK: DW_AT_name ("A") +; CHECK: DW_TAG_member +; CHECK: NULL +; CHECK: DW_TAG_variable +; CHECK: DW_AT_type ([[A]] "A") +; CHECK: NULL +; CHECK: DW_TAG_base_type +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_name ("not_removed") +; CHECK: [[B:0x.*]]: DW_TAG_structure_type +; CHECK: DW_AT_name ("B") +; CHECK: DW_TAG_member +; CHECK: NULL +; CHECK: DW_TAG_variable +; CHECK: DW_AT_type ([[B]] "B") +; CHECK: NULL +; CHECK: DW_TAG_subprogram +; CHECK: DW_TAG_inlined_subroutine +; CHECK: DW_TAG_variable +; CHECK: NULL +; CHECK: DW_TAG_inlined_subroutine +; CHECK: DW_TAG_variable +; CHECK: NULL +; CHECK: NULL +; CHECK: NULL + +%struct.B = type { i32 } +%struct.A = type { i32 } + +define dso_local i32 @not_removed() !dbg !12 { + %1 = alloca %struct.B, align 4 + call void @llvm.dbg.declare(metadata %struct.B* %1, metadata !18, metadata !DIExpression()), !dbg !22 + %2 = getelementptr inbounds %struct.B, %struct.B* %1, i32 0, i32 0, !dbg !23 + %3 = load i32, i32* %2, align 4, !dbg !24 + %4 = add nsw i32 %3, 1, !dbg !24 + store i32 %4, i32* %2, align 4, !dbg !24 + ret i32 %3, !dbg !25 +} + +declare void @llvm.dbg.declare(metadata, metadata, metadata) + +define dso_local i32 @foo() !dbg !26 { + %1 = alloca %struct.A, align 4 + %2 = alloca %struct.B, align 4 + call void @llvm.dbg.declare(metadata %struct.A* %1, metadata !27, metadata !DIExpression()), !dbg !32 + %3 = getelementptr inbounds %struct.A, %struct.A* %1, i32 0, i32 0, !dbg !34 + %4 = load i32, i32* %3, align 4, !dbg !35 + %5 = add nsw i32 %4, 1, !dbg !35 + store i32 %5, i32* %3, align 4, !dbg !35 + call void @llvm.dbg.declare(metadata %struct.B* %2, metadata !18, metadata !DIExpression()), !dbg !36 + %6 = getelementptr inbounds %struct.B, %struct.B* %2, i32 0, i32 0, !dbg !38 + %7 = load i32, i32* %6, align 4, !dbg !39 + %8 = add nsw i32 %7, 1, !dbg !39 + store i32 %8, i32* %6, align 4, !dbg !39 + %9 = add nsw i32 %4, %7, !dbg !40 + ret i32 %9, !dbg !41 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8, !9, !10} +!llvm.ident = !{!11} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 14.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "inlined-local-type.cpp", directory: "") +!2 = !{i32 7, !"Dwarf Version", i32 4} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 1, !"branch-target-enforcement", i32 0} +!6 = !{i32 1, !"sign-return-address", i32 0} +!7 = !{i32 1, !"sign-return-address-all", i32 0} +!8 = !{i32 1, !"sign-return-address-with-bkey", i32 0} +!9 = !{i32 7, !"uwtable", i32 1} +!10 = !{i32 7, !"frame-pointer", i32 1} +!11 = !{!"clang version 14.0.0"} +!12 = distinct !DISubprogram(name: "not_removed", scope: !13, file: !13, line: 5, type: !14, scopeLine: 5, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !43) +!13 = !DIFile(filename: "inlined-local-type.cpp", directory: "") +!14 = !DISubroutineType(types: !15) +!15 = !{!16} +!16 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!17 = !{} +!18 = !DILocalVariable(name: "b", scope: !12, file: !13, line: 5, type: !19) +!19 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "B", scope: !12, file: !13, line: 5, size: 32, elements: !20) +!20 = !{!21} +!21 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !19, file: !13, line: 5, baseType: !16, size: 32) +!22 = !DILocation(line: 5, column: 49, scope: !12) +!23 = !DILocation(line: 5, column: 61, scope: !12) +!24 = !DILocation(line: 5, column: 62, scope: !12) +!25 = !DILocation(line: 5, column: 52, scope: !12) +!26 = distinct !DISubprogram(name: "foo", scope: !13, file: !13, line: 7, type: !14, scopeLine: 7, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !17) +!27 = !DILocalVariable(name: "a", scope: !28, file: !13, line: 2, type: !29) +!28 = distinct !DISubprogram(name: "removed", scope: !13, file: !13, line: 2, type: !14, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !42) +!29 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "A", scope: !28, file: !13, line: 2, size: 32, elements: !30) +!30 = !{!31} +!31 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !29, file: !13, line: 2, baseType: !16, size: 32) +!32 = !DILocation(line: 2, column: 45, scope: !28, inlinedAt: !33) +!33 = distinct !DILocation(line: 7, column: 20, scope: !26) +!34 = !DILocation(line: 2, column: 57, scope: !28, inlinedAt: !33) +!35 = !DILocation(line: 2, column: 58, scope: !28, inlinedAt: !33) +!36 = !DILocation(line: 5, column: 49, scope: !12, inlinedAt: !37) +!37 = distinct !DILocation(line: 7, column: 32, scope: !26) +!38 = !DILocation(line: 5, column: 61, scope: !12, inlinedAt: !37) +!39 = !DILocation(line: 5, column: 62, scope: !12, inlinedAt: !37) +!40 = !DILocation(line: 7, column: 30, scope: !26) +!41 = !DILocation(line: 7, column: 13, scope: !26) +!42 = !{!29} +!43 = !{!19} diff --git a/llvm/test/DebugInfo/Generic/lexical-block-retained-types.ll b/llvm/test/DebugInfo/Generic/lexical-block-retained-types.ll new file mode 100644 index 0000000000000..091c9d92b13b7 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/lexical-block-retained-types.ll @@ -0,0 +1,72 @@ +; RUN: %llc_dwarf -O0 -filetype=obj < %s | llvm-dwarfdump - | FileCheck --implicit-check-not "{{DW_TAG|NULL}}" %s + +; Test that retained unused (unreferenced) types emission. + +; Compiled from +; $ clang -cc1 -debug-info-kind=unused-types test.cpp -emit-llvm + +; void test_unused() { +; struct Y {}; +; { +; struct X {}; +; } +; { +; struct Z {}; +; test_external(); +; } +; } + +; CHECK: DW_TAG_compile_unit +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_name ("test_unused") +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("Y") + +; FIXME: here should be DW_TAG_lexical_block as a parent of structure 'X'. +; But it's not possible to reliably emit a lexical block for which a LexicalScope +; wasn't created, so we just fallback to the most close parent DIE +; (see DwarfCompileUnit::getOrCreateLexicalBlockDIE() for details). + +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("X") +; The LexicalScope for parent scope of structure 'Z' is created (thanks to test_external +; call), therefore, DW_TAG_structure_type for structure 'Z' is placed inside +; the DW_TAG_lexical_block. +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("Z") +; CHECK: NULL +; CHECK: NULL +; CHECK: NULL + +declare void @_Z13test_externalv() + +define dso_local void @_Z11test_unusedv() !dbg !5 { +entry: + call void @_Z13test_externalv(), !dbg !19 + ret void, !dbg !16 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!13, !14} +!llvm.ident = !{!15} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 15.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "", directory: "/") +!2 = !{!3, !10} +!3 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Y", scope: !5, file: !4, line: 2, size: 8, flags: DIFlagTypePassByValue, elements: !8) +!4 = !DIFile(filename: "test.cpp", directory: "/") +!5 = distinct !DISubprogram(name: "test_unused", linkageName: "_Z11test_unusedv", scope: !4, file: !4, line: 1, type: !6, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !9) +!6 = !DISubroutineType(types: !7) +!7 = !{null} +!8 = !{} +!9 = !{!3, !10, !18} +!10 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "X", scope: !11, file: !4, line: 4, size: 8, flags: DIFlagTypePassByValue, elements: !8) +!11 = distinct !DILexicalBlock(scope: !5, file: !4, line: 3, column: 3) +!13 = !{i32 2, !"Debug Info Version", i32 3} +!14 = !{i32 1, !"wchar_size", i32 4} +!15 = !{!"clang version 15.0.0"} +!16 = !DILocation(line: 10, column: 1, scope: !5) +!17 = distinct !DILexicalBlock(scope: !5, file: !4, line: 6, column: 3) +!18 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Z", scope: !17, file: !4, line: 7, size: 8, flags: DIFlagTypePassByValue, elements: !8) +!19 = !DILocation(line: 8, column: 1, scope: !17) diff --git a/llvm/test/DebugInfo/Generic/lexical-block-types.ll b/llvm/test/DebugInfo/Generic/lexical-block-types.ll new file mode 100644 index 0000000000000..bb8371aeee492 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/lexical-block-types.ll @@ -0,0 +1,424 @@ +; RUN: %llc_dwarf -O0 -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck --implicit-check-not "{{DW_TAG|NULL}}" %s + +; inline __attribute__((always_inline)) +; void removed() { +; struct A1 { int i; }; +; typedef int Int1; +; { +; struct I1 { Int1 j; }; +; struct C1 { typedef char Char1; Char1 c; }; +; A1 a1; a1.i++; +; { +; I1 i1; i1.j++; +; C1 c1; c1.c++; +; } +; } +; } +; +; __attribute__((always_inline)) +; void not_removed() { +; struct A2 { int i; }; +; typedef int Int2; +; { +; struct I2 { Int2 j; }; +; struct C2 { typedef char Char2; Char2 c; }; +; A2 a2; a2.i++; +; { +; I2 i2; i2.j++; +; C2 c2; c2.c++; +; } +; } +; } +; +; void foo() { +; struct A3 { int i; }; +; typedef int Int3; +; { +; struct I3 { Int3 j; }; +; { +; struct C3 { typedef char Char3; Char3 c; }; +; A3 a3; a3.i++; +; { +; I3 i3; i3.j++; +; C3 c3; c3.c++; +; } +; } +; } +; removed(); +; not_removed(); +; } +; +; CHECK: DW_TAG_compile_unit + +; Out-of-line definition of `not_removed()` shouldn't contain any debug info for types. +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_abstract_origin {{.*}} "_Z11not_removedv" +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_AT_abstract_origin {{.*}} "a2" +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_AT_abstract_origin {{.*}} "i2" +; CHECK: DW_TAG_variable +; CHECK: DW_AT_abstract_origin {{.*}} "c2" +; CHECK: NULL +; CHECK: NULL +; CHECK: NULL + +; Abstract definition of `removed()`. +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_name ("removed") +; CHECK: DW_AT_inline (DW_INL_inlined) + +; I1 and C1 defined in the first lexical block, typedef Char1 is a child of C1. +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("a1") +; CHECK: DW_AT_type {{.*}} "A1" +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_AT_type {{.*}} "I1" +; CHECK: DW_TAG_variable +; CHECK: DW_AT_type {{.*}} "C1" +; CHECK: NULL +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("I1") +; CHECK: DW_TAG_member +; CHECK: DW_AT_type {{.*}} "Int1" +; CHECK: NULL +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("C1") +; CHECK: DW_TAG_member +; CHECK: DW_AT_type {{.*}} "C1::Char1" +; CHECK: DW_TAG_typedef +; CHECK: DW_AT_name ("Char1") +; CHECK: NULL +; CHECK: NULL + +; A1 and typedef Int1 defined in the subprogram scope. +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("A1") +; CHECK: DW_TAG_member +; CHECK: NULL +; CHECK: DW_TAG_typedef +; CHECK: DW_AT_name ("Int1") +; CHECK: NULL + +; CHECK: DW_TAG_base_type +; CHECK: DW_TAG_base_type + +; Abstract definition of `not_removed()`. +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_name ("not_removed") +; CHECK: DW_AT_inline (DW_INL_inlined) + +; I2 and C2 defined in the first lexical block, typedef Char2 is a child of C2. +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("a2") +; CHECK: DW_AT_type {{.*}} "A2" +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("i2") +; CHECK: DW_AT_type {{.*}} "I2" +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("c2") +; CHECK: DW_AT_type {{.*}} "C2" +; CHECK: NULL +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("I2") +; CHECK: DW_TAG_member +; CHECK: DW_AT_type {{.*}} "Int2" +; CHECK: NULL +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("C2") +; CHECK: DW_TAG_member +; CHECK: DW_AT_type {{.*}} "C2::Char2" +; CHECK: DW_TAG_typedef +; CHECK: DW_AT_name ("Char2") +; CHECK: NULL +; CHECK: NULL + +; A2 and typedef Int2 defined in subprogram scope. +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("A2") +; CHECK: DW_TAG_member +; CHECK: NULL +; CHECK: DW_TAG_typedef +; CHECK: DW_AT_name ("Int2") +; CHECK: NULL + +; Definition of `foo()`. +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_name ("foo") + +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("a3") +; CHECK: DW_AT_type {{.*}} "A3" +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("i3") +; CHECK: DW_AT_type {{.*}} "I3" +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("c3") +; CHECK: DW_AT_type {{.*}} "C3" +; CHECK: NULL + +; C3 has the inner lexical block scope, typedef Char3 is a child of C3. +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("C3") +; CHECK: DW_TAG_member +; CHECK: DW_AT_type {{.*}} "C3::Char3" +; CHECK: DW_TAG_typedef +; CHECK: DW_AT_name ("Char3") +; CHECK: NULL +; CHECK: NULL + +; I3 has the outer lexical block scope. +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("I3") +; CHECK: DW_TAG_member +; CHECK: DW_AT_type {{.*}} "Int3" +; CHECK: NULL +; CHECK: NULL + +; CHECK: DW_TAG_inlined_subroutine +; CHECK: DW_AT_abstract_origin {{.*}} "_Z7removedv" +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_TAG_variable +; CHECK: NULL +; CHECK: NULL +; CHECK: NULL + +; CHECK: DW_TAG_inlined_subroutine +; CHECK: DW_AT_abstract_origin {{.*}} "_Z11not_removedv" +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_TAG_lexical_block +; CHECK: DW_TAG_variable +; CHECK: DW_TAG_variable +; CHECK: NULL +; CHECK: NULL +; CHECK: NULL + +; A3 and Int3 defined within the subprogam scope. +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("A3") +; CHECK: DW_TAG_member +; CHECK: NULL +; CHECK: DW_TAG_typedef +; CHECK: DW_AT_name ("Int3") +; CHECK: NULL +; CHECK: NULL + +%struct.A2 = type { i32 } +%struct.I2 = type { i32 } +%struct.C2 = type { i8 } +%struct.A1 = type { i32 } +%struct.I1 = type { i32 } +%struct.C1 = type { i8 } +%struct.A3 = type { i32 } +%struct.I3 = type { i32 } +%struct.C3 = type { i8 } + +define dso_local void @_Z11not_removedv() !dbg !8 { +entry: + %a2 = alloca %struct.A2, align 4 + %i2 = alloca %struct.I2, align 4 + %c2 = alloca %struct.C2, align 1 + call void @llvm.dbg.declare(metadata %struct.A2* %a2, metadata !12, metadata !DIExpression()), !dbg !18 + %i = getelementptr inbounds %struct.A2, %struct.A2* %a2, i32 0, i32 0, !dbg !19 + %0 = load i32, i32* %i, align 4, !dbg !20 + %inc = add nsw i32 %0, 1, !dbg !20 + store i32 %inc, i32* %i, align 4, !dbg !20 + call void @llvm.dbg.declare(metadata %struct.I2* %i2, metadata !21, metadata !DIExpression()), !dbg !27 + %j = getelementptr inbounds %struct.I2, %struct.I2* %i2, i32 0, i32 0, !dbg !28 + %1 = load i32, i32* %j, align 4, !dbg !29 + %inc1 = add nsw i32 %1, 1, !dbg !29 + store i32 %inc1, i32* %j, align 4, !dbg !29 + call void @llvm.dbg.declare(metadata %struct.C2* %c2, metadata !30, metadata !DIExpression()), !dbg !36 + %c = getelementptr inbounds %struct.C2, %struct.C2* %c2, i32 0, i32 0, !dbg !37 + %2 = load i8, i8* %c, align 1, !dbg !38 + %inc2 = add i8 %2, 1, !dbg !38 + store i8 %inc2, i8* %c, align 1, !dbg !38 + ret void, !dbg !39 +} + +declare void @llvm.dbg.declare(metadata, metadata, metadata) + +define dso_local void @_Z3foov() !dbg !40 { +entry: + %a1.i = alloca %struct.A1, align 4 + %i1.i = alloca %struct.I1, align 4 + %c1.i = alloca %struct.C1, align 1 + %a2.i = alloca %struct.A2, align 4 + %i2.i = alloca %struct.I2, align 4 + %c2.i = alloca %struct.C2, align 1 + %a3 = alloca %struct.A3, align 4 + %i3 = alloca %struct.I3, align 4 + %c3 = alloca %struct.C3, align 1 + call void @llvm.dbg.declare(metadata %struct.A3* %a3, metadata !41, metadata !DIExpression()), !dbg !47 + %i = getelementptr inbounds %struct.A3, %struct.A3* %a3, i32 0, i32 0, !dbg !48 + %0 = load i32, i32* %i, align 4, !dbg !49 + %inc = add nsw i32 %0, 1, !dbg !49 + store i32 %inc, i32* %i, align 4, !dbg !49 + call void @llvm.dbg.declare(metadata %struct.I3* %i3, metadata !50, metadata !DIExpression()), !dbg !56 + %j = getelementptr inbounds %struct.I3, %struct.I3* %i3, i32 0, i32 0, !dbg !57 + %1 = load i32, i32* %j, align 4, !dbg !58 + %inc1 = add nsw i32 %1, 1, !dbg !58 + store i32 %inc1, i32* %j, align 4, !dbg !58 + call void @llvm.dbg.declare(metadata %struct.C3* %c3, metadata !59, metadata !DIExpression()), !dbg !64 + %c = getelementptr inbounds %struct.C3, %struct.C3* %c3, i32 0, i32 0, !dbg !65 + %2 = load i8, i8* %c, align 1, !dbg !66 + %inc2 = add i8 %2, 1, !dbg !66 + store i8 %inc2, i8* %c, align 1, !dbg !66 + call void @llvm.dbg.declare(metadata %struct.A1* %a1.i, metadata !67, metadata !DIExpression()), !dbg !73 + %i.i3 = getelementptr inbounds %struct.A1, %struct.A1* %a1.i, i32 0, i32 0, !dbg !75 + %3 = load i32, i32* %i.i3, align 4, !dbg !76 + %inc.i4 = add nsw i32 %3, 1, !dbg !76 + store i32 %inc.i4, i32* %i.i3, align 4, !dbg !76 + call void @llvm.dbg.declare(metadata %struct.I1* %i1.i, metadata !77, metadata !DIExpression()), !dbg !83 + %j.i5 = getelementptr inbounds %struct.I1, %struct.I1* %i1.i, i32 0, i32 0, !dbg !84 + %4 = load i32, i32* %j.i5, align 4, !dbg !85 + %inc1.i6 = add nsw i32 %4, 1, !dbg !85 + store i32 %inc1.i6, i32* %j.i5, align 4, !dbg !85 + call void @llvm.dbg.declare(metadata %struct.C1* %c1.i, metadata !86, metadata !DIExpression()), !dbg !91 + %c.i7 = getelementptr inbounds %struct.C1, %struct.C1* %c1.i, i32 0, i32 0, !dbg !92 + %5 = load i8, i8* %c.i7, align 1, !dbg !93 + %inc2.i8 = add i8 %5, 1, !dbg !93 + store i8 %inc2.i8, i8* %c.i7, align 1, !dbg !93 + call void @llvm.dbg.declare(metadata %struct.A2* %a2.i, metadata !12, metadata !DIExpression()), !dbg !94 + %i.i = getelementptr inbounds %struct.A2, %struct.A2* %a2.i, i32 0, i32 0, !dbg !96 + %6 = load i32, i32* %i.i, align 4, !dbg !97 + %inc.i = add nsw i32 %6, 1, !dbg !97 + store i32 %inc.i, i32* %i.i, align 4, !dbg !97 + call void @llvm.dbg.declare(metadata %struct.I2* %i2.i, metadata !21, metadata !DIExpression()), !dbg !98 + %j.i = getelementptr inbounds %struct.I2, %struct.I2* %i2.i, i32 0, i32 0, !dbg !99 + %7 = load i32, i32* %j.i, align 4, !dbg !100 + %inc1.i = add nsw i32 %7, 1, !dbg !100 + store i32 %inc1.i, i32* %j.i, align 4, !dbg !100 + call void @llvm.dbg.declare(metadata %struct.C2* %c2.i, metadata !30, metadata !DIExpression()), !dbg !101 + %c.i = getelementptr inbounds %struct.C2, %struct.C2* %c2.i, i32 0, i32 0, !dbg !102 + %8 = load i8, i8* %c.i, align 1, !dbg !103 + %inc2.i = add i8 %8, 1, !dbg !103 + store i8 %inc2.i, i8* %c.i, align 1, !dbg !103 + ret void, !dbg !104 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6} +!llvm.ident = !{!7} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 14.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 4} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 7, !"uwtable", i32 1} +!6 = !{i32 7, !"frame-pointer", i32 2} +!7 = !{!"clang version 14.0.0"} +!8 = distinct !DISubprogram(name: "not_removed", linkageName: "_Z11not_removedv", scope: !1, file: !1, line: 17, type: !9, scopeLine: 17, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !105) +!9 = !DISubroutineType(types: !10) +!10 = !{null} +!11 = !{} +!12 = !DILocalVariable(name: "a2", scope: !13, file: !1, line: 23, type: !14) +!13 = distinct !DILexicalBlock(scope: !8, file: !1, line: 20, column: 3) +!14 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "A2", scope: !8, file: !1, line: 18, size: 32, flags: DIFlagTypePassByValue, elements: !15) +!15 = !{!16} +!16 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !14, file: !1, line: 18, baseType: !17, size: 32) +!17 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!18 = !DILocation(line: 23, column: 8, scope: !13) +!19 = !DILocation(line: 23, column: 15, scope: !13) +!20 = !DILocation(line: 23, column: 16, scope: !13) +!21 = !DILocalVariable(name: "i2", scope: !22, file: !1, line: 25, type: !23) +!22 = distinct !DILexicalBlock(scope: !13, file: !1, line: 24, column: 5) +!23 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "I2", scope: !13, file: !1, line: 21, size: 32, flags: DIFlagTypePassByValue, elements: !24) +!24 = !{!25} +!25 = !DIDerivedType(tag: DW_TAG_member, name: "j", scope: !23, file: !1, line: 21, baseType: !26, size: 32) +!26 = !DIDerivedType(tag: DW_TAG_typedef, name: "Int2", scope: !8, file: !1, line: 19, baseType: !17) +!27 = !DILocation(line: 25, column: 10, scope: !22) +!28 = !DILocation(line: 25, column: 17, scope: !22) +!29 = !DILocation(line: 25, column: 18, scope: !22) +!30 = !DILocalVariable(name: "c2", scope: !22, file: !1, line: 26, type: !31) +!31 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "C2", scope: !13, file: !1, line: 22, size: 8, flags: DIFlagTypePassByValue, elements: !32) +!32 = !{!33} +!33 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !31, file: !1, line: 22, baseType: !34, size: 8) +!34 = !DIDerivedType(tag: DW_TAG_typedef, name: "Char2", scope: !31, file: !1, line: 22, baseType: !35) +!35 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +!36 = !DILocation(line: 26, column: 10, scope: !22) +!37 = !DILocation(line: 26, column: 17, scope: !22) +!38 = !DILocation(line: 26, column: 18, scope: !22) +!39 = !DILocation(line: 29, column: 1, scope: !8) +!40 = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov", scope: !1, file: !1, line: 31, type: !9, scopeLine: 31, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !107) +!41 = !DILocalVariable(name: "a3", scope: !42, file: !1, line: 38, type: !44) +!42 = distinct !DILexicalBlock(scope: !43, file: !1, line: 36, column: 5) +!43 = distinct !DILexicalBlock(scope: !40, file: !1, line: 34, column: 3) +!44 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "A3", scope: !40, file: !1, line: 32, size: 32, flags: DIFlagTypePassByValue, elements: !45) +!45 = !{!46} +!46 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !44, file: !1, line: 32, baseType: !17, size: 32) +!47 = !DILocation(line: 38, column: 10, scope: !42) +!48 = !DILocation(line: 38, column: 17, scope: !42) +!49 = !DILocation(line: 38, column: 18, scope: !42) +!50 = !DILocalVariable(name: "i3", scope: !51, file: !1, line: 40, type: !52) +!51 = distinct !DILexicalBlock(scope: !42, file: !1, line: 39, column: 7) +!52 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "I3", scope: !43, file: !1, line: 35, size: 32, flags: DIFlagTypePassByValue, elements: !53) +!53 = !{!54} +!54 = !DIDerivedType(tag: DW_TAG_member, name: "j", scope: !52, file: !1, line: 35, baseType: !55, size: 32) +!55 = !DIDerivedType(tag: DW_TAG_typedef, name: "Int3", scope: !40, file: !1, line: 33, baseType: !17) +!56 = !DILocation(line: 40, column: 12, scope: !51) +!57 = !DILocation(line: 40, column: 19, scope: !51) +!58 = !DILocation(line: 40, column: 20, scope: !51) +!59 = !DILocalVariable(name: "c3", scope: !51, file: !1, line: 41, type: !60) +!60 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "C3", scope: !42, file: !1, line: 37, size: 8, flags: DIFlagTypePassByValue, elements: !61) +!61 = !{!62} +!62 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !60, file: !1, line: 37, baseType: !63, size: 8) +!63 = !DIDerivedType(tag: DW_TAG_typedef, name: "Char3", scope: !60, file: !1, line: 37, baseType: !35) +!64 = !DILocation(line: 41, column: 12, scope: !51) +!65 = !DILocation(line: 41, column: 19, scope: !51) +!66 = !DILocation(line: 41, column: 20, scope: !51) +!67 = !DILocalVariable(name: "a1", scope: !68, file: !1, line: 8, type: !70) +!68 = distinct !DILexicalBlock(scope: !69, file: !1, line: 5, column: 3) +!69 = distinct !DISubprogram(name: "removed", linkageName: "_Z7removedv", scope: !1, file: !1, line: 2, type: !9, scopeLine: 2, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !110) +!70 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "A1", scope: !69, file: !1, line: 3, size: 32, flags: DIFlagTypePassByValue, elements: !71, identifier: "_ZTSZ7removedvE2A1") +!71 = !{!72} +!72 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !70, file: !1, line: 3, baseType: !17, size: 32) +!73 = !DILocation(line: 8, column: 8, scope: !68, inlinedAt: !74) +!74 = distinct !DILocation(line: 45, column: 3, scope: !40) +!75 = !DILocation(line: 8, column: 15, scope: !68, inlinedAt: !74) +!76 = !DILocation(line: 8, column: 16, scope: !68, inlinedAt: !74) +!77 = !DILocalVariable(name: "i1", scope: !78, file: !1, line: 10, type: !79) +!78 = distinct !DILexicalBlock(scope: !68, file: !1, line: 9, column: 5) +!79 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "I1", scope: !68, file: !1, line: 6, size: 32, flags: DIFlagTypePassByValue, elements: !80, identifier: "_ZTSZ7removedvE2I1") +!80 = !{!81} +!81 = !DIDerivedType(tag: DW_TAG_member, name: "j", scope: !79, file: !1, line: 6, baseType: !82, size: 32) +!82 = !DIDerivedType(tag: DW_TAG_typedef, name: "Int1", scope: !69, file: !1, line: 4, baseType: !17) +!83 = !DILocation(line: 10, column: 10, scope: !78, inlinedAt: !74) +!84 = !DILocation(line: 10, column: 17, scope: !78, inlinedAt: !74) +!85 = !DILocation(line: 10, column: 18, scope: !78, inlinedAt: !74) +!86 = !DILocalVariable(name: "c1", scope: !78, file: !1, line: 11, type: !87) +!87 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "C1", scope: !68, file: !1, line: 7, size: 8, flags: DIFlagTypePassByValue, elements: !88, identifier: "_ZTSZ7removedvE2C1") +!88 = !{!89} +!89 = !DIDerivedType(tag: DW_TAG_member, name: "c", scope: !87, file: !1, line: 7, baseType: !90, size: 8) +!90 = !DIDerivedType(tag: DW_TAG_typedef, name: "Char1", scope: !87, file: !1, line: 7, baseType: !35) +!91 = !DILocation(line: 11, column: 10, scope: !78, inlinedAt: !74) +!92 = !DILocation(line: 11, column: 17, scope: !78, inlinedAt: !74) +!93 = !DILocation(line: 11, column: 18, scope: !78, inlinedAt: !74) +!94 = !DILocation(line: 23, column: 8, scope: !13, inlinedAt: !95) +!95 = distinct !DILocation(line: 46, column: 3, scope: !40) +!96 = !DILocation(line: 23, column: 15, scope: !13, inlinedAt: !95) +!97 = !DILocation(line: 23, column: 16, scope: !13, inlinedAt: !95) +!98 = !DILocation(line: 25, column: 10, scope: !22, inlinedAt: !95) +!99 = !DILocation(line: 25, column: 17, scope: !22, inlinedAt: !95) +!100 = !DILocation(line: 25, column: 18, scope: !22, inlinedAt: !95) +!101 = !DILocation(line: 26, column: 10, scope: !22, inlinedAt: !95) +!102 = !DILocation(line: 26, column: 17, scope: !22, inlinedAt: !95) +!103 = !DILocation(line: 26, column: 18, scope: !22, inlinedAt: !95) +!104 = !DILocation(line: 47, column: 1, scope: !40) +!105 = !{!14, !23, !26, !31} +!107 = !{!44, !52, !55, !60} +!110 = !{!70, !79, !82, !87} diff --git a/llvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll b/llvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll index 6d4d0e93d38f9..54ce1c56c6b30 100644 --- a/llvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll +++ b/llvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll @@ -38,7 +38,7 @@ define void @invalid_subprogram_declaration() !dbg !9 { ret void } define void @invalid_retained_nodes_list() !dbg !10 { ret void } !10 = distinct !DISubprogram(retainedNodes: !0) -; CHECK: invalid retained nodes, expected DILocalVariable, DILabel or DIImportedEntity +; CHECK: invalid retained nodes, expected DILocalVariable, DILabel, DIImportedEntity or DIType define void @invalid_retained_nodes_expected() !dbg !11 { ret void } !11 = distinct !DISubprogram(retainedNodes: !{!0}) diff --git a/llvm/test/DebugInfo/Inputs/cleanup-retained-nodes.ll b/llvm/test/DebugInfo/Inputs/cleanup-retained-nodes.ll new file mode 100644 index 0000000000000..d2cca1bc4f8a2 --- /dev/null +++ b/llvm/test/DebugInfo/Inputs/cleanup-retained-nodes.ll @@ -0,0 +1,17 @@ +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@var = global i8 0, align 4, !dbg !7 + +!llvm.module.flags = !{!0, !1, !2} +!llvm.dbg.cu = !{!3} + +!0 = !{i32 7, !"Dwarf Version", i32 2} +!1 = !{i32 2, !"Debug Info Version", i32 3} +!2 = !{i32 1, !"wchar_size", i32 4} +!3 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !5, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!4 = !{} +!5 = !DIFile(filename: "tmp2.cpp", directory: "/tmp/") +!6 = !DICompositeType(tag: DW_TAG_class_type, scope: !3, file: !5, line: 212, size: 8, flags: DIFlagTypePassByValue, elements: !4, identifier: "type_global_in_another_module") +!7 = !DIGlobalVariableExpression(var: !8, expr: !DIExpression()) +!8 = distinct !DIGlobalVariable(name: "var", scope: !3, file: !5, line: 1, type: !6, isLocal: false, isDefinition: true) diff --git a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir index e80ed2e3e8eb3..ca5dede206cd7 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir @@ -194,7 +194,7 @@ body: | JMP_1 %bb.11, debug-location !9 bb.11: - %36:gr64 = SUBREG_TO_REG 0, %27, %subreg.sub_32bit + %36:gr64 = SUBREG_TO_REG %27, %subreg.sub_32bit JMP_1 %bb.13, debug-location !9 bb.12: @@ -247,7 +247,7 @@ body: | bb.20: %43:gr32 = nsw DEC32r %5, implicit-def dead $eflags, debug-location !9 - %44:gr64_nosp = SUBREG_TO_REG 0, killed %43, %subreg.sub_32bit + %44:gr64_nosp = SUBREG_TO_REG killed %43, %subreg.sub_32bit ; Fiddled with to morph into llvm test, %8:gr64 = LEA64r $noreg, 4, killed %44, @amd64_push_arguments, $noreg, debug-location !9 %42:gr32 = MOV32ri 8 diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir index 684b6207e4891..59270c6ef30d3 100644 --- a/llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir +++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir @@ -127,7 +127,7 @@ body: | successors: %bb.3(0x80000000) %10:gr32 = MOV32rr %5, debug-location !13 - %0:gr64 = SUBREG_TO_REG 0, killed %10, %subreg.sub_32bit, debug-location !13 + %0:gr64 = SUBREG_TO_REG killed %10, %subreg.sub_32bit, debug-location !13 JMP_1 %bb.3 bb.2.for.cond.cleanup: diff --git a/llvm/test/DebugInfo/MIR/X86/machine-cse.mir b/llvm/test/DebugInfo/MIR/X86/machine-cse.mir index 63dc44fb705fe..19dcddd1d4fee 100644 --- a/llvm/test/DebugInfo/MIR/X86/machine-cse.mir +++ b/llvm/test/DebugInfo/MIR/X86/machine-cse.mir @@ -107,7 +107,7 @@ body: | %2:gr32 = COPY $edi %3:gr32 = MOV32rr %2 - %0:gr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32bit + %0:gr64 = SUBREG_TO_REG killed %3, %subreg.sub_32bit %4:gr64_nosp = SHL64ri %0, 9, implicit-def dead $eflags %1:gr64 = LEA64r %4, 4, %4, 0, $noreg %5:gr32 = MOV32r0 implicit-def dead $eflags @@ -171,7 +171,7 @@ body: | %2:gr32 = COPY $edi %3:gr32 = MOV32rr %2 - %0:gr64 = SUBREG_TO_REG 0, killed %3, %subreg.sub_32bit + %0:gr64 = SUBREG_TO_REG killed %3, %subreg.sub_32bit %4:gr64_nosp = SHL64ri %0, 9, implicit-def dead $eflags %1:gr64 = LEA64r %4, 4, %4, 0, $noreg %5:gr32 = MOV32r0 implicit-def dead $eflags diff --git a/llvm/test/DebugInfo/X86/cleanup-retained-nodes.ll b/llvm/test/DebugInfo/X86/cleanup-retained-nodes.ll new file mode 100644 index 0000000000000..86c5ca92d7680 --- /dev/null +++ b/llvm/test/DebugInfo/X86/cleanup-retained-nodes.ll @@ -0,0 +1,45 @@ +; RUN: llvm-as %s -o %t.bc +; RUN: llvm-as %p/../Inputs/cleanup-retained-nodes.ll -o %t.global.bc +; RUN: llvm-link %t.global.bc %t.bc %t.bc -o - | llvm-dis - -o - \ +; RUN: | FileCheck %s --implicit-check-not=DICompositeType + +; During module loading, if a local type appears in retainedNodes +; field of multiple DISubprograms due to ODR-uniquing, +; retainedNodes should be cleaned up, so that only one DISubprogram +; will have this type in its retainedNodes. + +; CHECK: distinct !DICompositeType(tag: DW_TAG_class_type, {{.*}}, identifier: "type_global_in_another_module") +; CHECK: [[EMPTY:![0-9]+]] = !{} +; CHECK: [[BAR1:![0-9]+]] = distinct !DISubprogram(name: "bar", {{.*}}, retainedNodes: [[RN_BAR1:![0-9]+]]) +; CHECK: [[RN_BAR1]] = !{[[T1:![0-9]+]], [[T1]], [[T1]], [[T2:![0-9]+]]} +; CHECK: [[T1]] = distinct !DICompositeType(tag: DW_TAG_class_type, scope: [[BAR1]], {{.*}}, identifier: "local_type") +; CHECK: [[T2]] = distinct !DICompositeType(tag: DW_TAG_class_type, scope: [[LB:![0-9]+]], {{.*}}, identifier: "local_type_in_block") +; CHECK: [[LB]] = !DILexicalBlock(scope: [[BAR1]] +; CHECK: {{![0-9]+}} = distinct !DISubprogram(name: "bar", {{.*}}, retainedNodes: [[EMPTY]]) + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@llvm.used = appending global [1 x ptr] [ptr @bar] + +define internal void @bar(ptr %this) !dbg !10 { + ret void +} + +!llvm.module.flags = !{!0, !1, !2} +!llvm.dbg.cu = !{!8} + +!0 = !{i32 7, !"Dwarf Version", i32 2} +!1 = !{i32 2, !"Debug Info Version", i32 3} +!2 = !{i32 1, !"wchar_size", i32 4} +!3 = !DICompositeType(tag: DW_TAG_class_type, scope: !10, file: !9, line: 212, size: 8, flags: DIFlagTypePassByValue, elements: !7, identifier: "type_global_in_another_module") +!4 = !DICompositeType(tag: DW_TAG_class_type, scope: !5, file: !9, line: 211, size: 8, flags: DIFlagTypePassByValue, elements: !7, identifier: "local_type_in_block") +!5 = !DILexicalBlock(scope: !10) +; All repeating occurences of a uniqued type in retainedNodes must be checked. +!6 = !{!12, !12, !12, !4, !3} +!7 = !{} +!8 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !9, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!9 = !DIFile(filename: "tmp.cpp", directory: "/tmp/") +!10 = distinct !DISubprogram(name: "bar", scope: !9, file: !9, line: 68, type: !11, scopeLine: 68, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !8, retainedNodes: !6) +!11 = !DISubroutineType(types: !7) +!12 = !DICompositeType(tag: DW_TAG_class_type, scope: !10, file: !9, line: 210, size: 8, flags: DIFlagTypePassByValue, elements: !7, identifier: "local_type") diff --git a/llvm/test/DebugInfo/X86/llparser-cleanup-retained-nodes.ll b/llvm/test/DebugInfo/X86/llparser-cleanup-retained-nodes.ll new file mode 100644 index 0000000000000..ee529adbff132 --- /dev/null +++ b/llvm/test/DebugInfo/X86/llparser-cleanup-retained-nodes.ll @@ -0,0 +1,35 @@ +; RUN: llvm-link %s %s -S -o - | FileCheck %s --implicit-check-not=DICompositeType + +; During module loading, if a local type appears in retainedNodes +; field of multiple DISubprograms due to ODR-uniquing, +; LLParser should clean up retainedNodes, so that only one DISubprogram +; will have this type in its retainedNodes. + +; CHECK: [[BAR1:![0-9]+]] = distinct !DISubprogram(name: "bar", {{.*}}, retainedNodes: [[RN_BAR1:![0-9]+]]) +; CHECK: [[EMPTY:![0-9]+]] = !{} +; CHECK: [[RN_BAR1]] = !{[[T1:![0-9]+]]} +; CHECK: [[T1]] = distinct !DICompositeType(tag: DW_TAG_class_type, scope: [[BAR1]], {{.*}}, identifier: "local_type") +; CHECK: {{![0-9]+}} = distinct !DISubprogram(name: "bar", {{.*}}, retainedNodes: [[EMPTY]]) + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@llvm.used = appending global [1 x ptr] [ptr @bar] + +define internal void @bar(ptr %this) !dbg !5 { + ret void +} + +!llvm.module.flags = !{!0, !1, !2} +!llvm.dbg.cu = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"Dwarf Version", i32 2} +!2 = !{i32 2, !"Debug Info Version", i32 3} +!3 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !4, producer: "clang version 14.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!4 = !DIFile(filename: "tmp.cpp", directory: "/tmp/") +!5 = distinct !DISubprogram(name: "bar", scope: !4, file: !4, line: 68, type: !6, scopeLine: 68, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !3, retainedNodes: !9) +!6 = !DISubroutineType(types: !8) +!7 = !DICompositeType(tag: DW_TAG_class_type, scope: !5, file: !4, line: 210, size: 8, flags: DIFlagTypePassByValue, elements: !8, identifier: "local_type") +!8 = !{} +!9 = !{!7} diff --git a/llvm/test/DebugInfo/X86/local-type-as-template-parameter.ll b/llvm/test/DebugInfo/X86/local-type-as-template-parameter.ll new file mode 100644 index 0000000000000..7963efd81374c --- /dev/null +++ b/llvm/test/DebugInfo/X86/local-type-as-template-parameter.ll @@ -0,0 +1,161 @@ +; REQUIRES: system-linux +; RUN: %llc_dwarf -mtriple=x86_64-linux -O0 -filetype=obj < %s \ +; RUN: | llvm-dwarfdump --show-children --name=foo - \ +; RUN: | FileCheck --implicit-check-not "{{DW_TAG|NULL}}" %s + +; The test ensures that AsmPrinter doesn't crashed compiling this. +; It also demonstrates misplacement for a local type (see https://github.com/llvm/llvm-project/issues/55680 for details). + +; The test compiled from: + +; template +; struct A { +; A(T &in) : a(in) {} +; T a; +; }; +; +; __attribute__((always_inline)) +; void foo() { +; struct B { int i; }; +; B objB; +; A objA(objB); +; } +; +; int main() { +; foo(); +; } + +; Concrete out-of-line tree of foo(). +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_abstract_origin {{.*}} "_Z3foov" + +;;; FIXME: 'struct B' should be in the abstract tree below, not here. +; CHECK: DW_TAG_structure_type +; CHECK: DW_AT_name ("B") +; CHECK: DW_TAG_member +; CHECK: NULL +; +; CHECK: DW_TAG_variable +; CHECK: DW_AT_abstract_origin {{.*}} "objB" +; CHECK: DW_TAG_variable +; CHECK: DW_AT_abstract_origin {{.*}} "objA" + +; CHECK: NULL + +; Abstract tree of foo(). +; CHECK: DW_TAG_subprogram +; CHECK: DW_AT_name ("foo") +; CHECK: DW_AT_inline (DW_INL_inlined) + +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("objB") +; CHECK: DW_TAG_variable +; CHECK: DW_AT_name ("objA") + +; CHECK: NULL + +; CHECK: DW_TAG_inlined_subroutine +; CHECK: DW_AT_abstract_origin {{.*}} "_Z3foov" +; CHECK: DW_TAG_variable +; CHECK: DW_AT_abstract_origin {{.*}} "objB" +; CHECK: DW_TAG_variable +; CHECK: DW_AT_abstract_origin {{.*}} "objA" +; CHECK: NULL + +%struct.B = type { i32 } +%struct.A = type { %struct.B } + +define dso_local void @_Z3foov() !dbg !7 { +entry: + %objB = alloca %struct.B, align 4 + %objA = alloca %struct.A, align 4 + call void @llvm.dbg.declare(metadata ptr %objB, metadata !30, metadata !DIExpression()), !dbg !31 + call void @llvm.dbg.declare(metadata ptr %objA, metadata !32, metadata !DIExpression()), !dbg !33 + call void @_ZN1AIZ3foovE1BEC2ERS0_(ptr noundef nonnull align 4 dereferenceable(4) %objA, ptr noundef nonnull align 4 dereferenceable(4) %objB), !dbg !33 + ret void, !dbg !34 +} + +declare void @llvm.dbg.declare(metadata, metadata, metadata) + +define internal void @_ZN1AIZ3foovE1BEC2ERS0_(ptr noundef nonnull align 4 dereferenceable(4) %this, ptr noundef nonnull align 4 dereferenceable(4) %in) unnamed_addr align 2 !dbg !35 { +entry: + %this.addr = alloca ptr, align 8 + %in.addr = alloca ptr, align 8 + store ptr %this, ptr %this.addr, align 8 + call void @llvm.dbg.declare(metadata ptr %this.addr, metadata !36, metadata !DIExpression()), !dbg !38 + store ptr %in, ptr %in.addr, align 8 + call void @llvm.dbg.declare(metadata ptr %in.addr, metadata !39, metadata !DIExpression()), !dbg !40 + %this1 = load ptr, ptr %this.addr, align 8 + %a = getelementptr inbounds %struct.A, ptr %this1, i32 0, i32 0, !dbg !41 + %0 = load ptr, ptr %in.addr, align 8, !dbg !42 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %a, ptr align 4 %0, i64 4, i1 false), !dbg !41 + ret void, !dbg !43 +} + +define dso_local noundef i32 @main() !dbg !44 { +entry: + %objB.i = alloca %struct.B, align 4 + %objA.i = alloca %struct.A, align 4 + call void @llvm.dbg.declare(metadata ptr %objB.i, metadata !30, metadata !DIExpression()), !dbg !47 + call void @llvm.dbg.declare(metadata ptr %objA.i, metadata !32, metadata !DIExpression()), !dbg !49 + call void @_ZN1AIZ3foovE1BEC2ERS0_(ptr noundef nonnull align 4 dereferenceable(4) %objA.i, ptr noundef nonnull align 4 dereferenceable(4) %objB.i), !dbg !49 + ret i32 0, !dbg !50 +} + +declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!22, !23, !24, !25, !26, !27, !28} +!llvm.ident = !{!29} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 15.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "/", checksumkind: CSK_MD5, checksum: "aec7fd397e86f8655ef7f4bb4233b849") +!2 = !{!3} +!3 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "A", file: !1, line: 2, size: 32, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !4, templateParams: !20) +!4 = !{!5, !15} +!5 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !3, file: !1, line: 4, baseType: !6, size: 32) +!6 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "B", scope: !7, file: !1, line: 9, size: 32, flags: DIFlagTypePassByValue, elements: !12) +!7 = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov", scope: !1, file: !1, line: 8, type: !8, scopeLine: 8, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !11) +!8 = !DISubroutineType(types: !9) +!9 = !{null} +!10 = !{} +!11 = !{!6} +!12 = !{!13} +!13 = !DIDerivedType(tag: DW_TAG_member, name: "i", scope: !6, file: !1, line: 9, baseType: !14, size: 32) +!14 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!15 = !DISubprogram(name: "A", scope: !3, file: !1, line: 3, type: !16, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit) +!16 = !DISubroutineType(types: !17) +!17 = !{null, !18, !19} +!18 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !3, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!19 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !6, size: 64) +!20 = !{!21} +!21 = !DITemplateTypeParameter(name: "T", type: !6) +!22 = !{i32 7, !"Dwarf Version", i32 5} +!23 = !{i32 2, !"Debug Info Version", i32 3} +!24 = !{i32 1, !"wchar_size", i32 4} +!25 = !{i32 7, !"PIC Level", i32 2} +!26 = !{i32 7, !"PIE Level", i32 2} +!27 = !{i32 7, !"uwtable", i32 2} +!28 = !{i32 7, !"frame-pointer", i32 2} +!29 = !{!"clang version 15.0.0"} +!30 = !DILocalVariable(name: "objB", scope: !7, file: !1, line: 10, type: !6) +!31 = !DILocation(line: 10, column: 5, scope: !7) +!32 = !DILocalVariable(name: "objA", scope: !7, file: !1, line: 11, type: !3) +!33 = !DILocation(line: 11, column: 8, scope: !7) +!34 = !DILocation(line: 12, column: 1, scope: !7) +!35 = distinct !DISubprogram(name: "A", linkageName: "_ZN1AIZ3foovE1BEC2ERS0_", scope: !3, file: !1, line: 3, type: !16, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !0, declaration: !15, retainedNodes: !10) +!36 = !DILocalVariable(name: "this", arg: 1, scope: !35, type: !37, flags: DIFlagArtificial | DIFlagObjectPointer) +!37 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !3, size: 64) +!38 = !DILocation(line: 0, scope: !35) +!39 = !DILocalVariable(name: "in", arg: 2, scope: !35, file: !1, line: 3, type: !19) +!40 = !DILocation(line: 3, column: 8, scope: !35) +!41 = !DILocation(line: 3, column: 14, scope: !35) +!42 = !DILocation(line: 3, column: 16, scope: !35) +!43 = !DILocation(line: 3, column: 21, scope: !35) +!44 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 14, type: !45, scopeLine: 14, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !10) +!45 = !DISubroutineType(types: !46) +!46 = !{!14} +!47 = !DILocation(line: 10, column: 5, scope: !7, inlinedAt: !48) +!48 = distinct !DILocation(line: 15, column: 3, scope: !44) +!49 = !DILocation(line: 11, column: 8, scope: !7, inlinedAt: !48) +!50 = !DILocation(line: 16, column: 1, scope: !44) diff --git a/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll b/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll index cae8a479a5ad9..1a49b03d1af9a 100644 --- a/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll +++ b/llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll @@ -30,7 +30,7 @@ define i64 @test_constant(ptr %rdata) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.land.lhs.true.i: ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET 0, $rax entry: @@ -67,7 +67,7 @@ define i64 @test_non_constant(ptr %rdata, i64 %i.194) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2.land.lhs.true.i: ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags - ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32r0_]], %subreg.sub_32bit + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOV32r0_]], %subreg.sub_32bit ; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]] ; CHECK-NEXT: RET 0, $rax entry: diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll index c24947a16c8b7..08c675899d997 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-bf16-dotprod-intrinsics.ll @@ -1,12 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 ; RUN: opt -mattr=+bf16 < %s -passes=msan -S | FileCheck %s ; -; Forked from llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll +; Forked from llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll, +; simplified to only have the cases that directly pass the function parameters +; to the intrinsic. ; -; Strictly handled: -; - llvm.aarch64.neon.bfmmla -; - llvm.aarch64.neon.bfmlalb -; - llvm.aarch64.neon.bfmlalt +; Strictly handled: (none) ; ; Heuristically handled: (none) @@ -63,142 +62,6 @@ entry: ret <4 x float> %vbfdot3.i } -define <2 x float> @test_vbfdot_lane_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) sanitize_memory { -; CHECK-LABEL: define <2 x float> @test_vbfdot_lane_f32( -; CHECK-SAME: <2 x float> [[R:%.*]], <4 x bfloat> [[A:%.*]], <4 x bfloat> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 -; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP0]] to <2 x i32> -; CHECK-NEXT: [[DOTCAST:%.*]] = bitcast <4 x bfloat> [[B]] to <2 x float> -; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> splat (i32 -1), <2 x i32> zeroinitializer -; CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[DOTCAST]], <2 x float> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[_MSPROP]] to <4 x i16> -; CHECK-NEXT: [[DOTCAST1:%.*]] = bitcast <2 x float> [[LANE]] to <4 x bfloat> -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i16> [[TMP2]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i16> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i1> [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i1> [[TMP7]] to <4 x i16> -; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[TMP8]] to <2 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <2 x i32> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = sext <2 x i1> [[TMP10]] to <2 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = or <2 x i32> [[TMP11]], [[TMP13]] -; CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> [[R]], <4 x bfloat> [[A]], <4 x bfloat> [[DOTCAST1]]) -; CHECK-NEXT: store <2 x i32> [[TMP12]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <2 x float> [[VBFDOT3_I]] -; -entry: - %.cast = bitcast <4 x bfloat> %b to <2 x float> - %lane = shufflevector <2 x float> %.cast, <2 x float> poison, <2 x i32> zeroinitializer - %.cast1 = bitcast <2 x float> %lane to <4 x bfloat> - %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %.cast1) - ret <2 x float> %vbfdot3.i -} - -define <4 x float> @test_vbfdotq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) sanitize_memory { -; CHECK-LABEL: define <4 x float> @test_vbfdotq_laneq_f32( -; CHECK-SAME: <4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 -; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP0]] to <4 x i32> -; CHECK-NEXT: [[DOTCAST:%.*]] = bitcast <8 x bfloat> [[B]] to <4 x float> -; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> splat (i32 -1), <4 x i32> -; CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[DOTCAST]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[_MSPROP]] to <8 x i16> -; CHECK-NEXT: [[DOTCAST1:%.*]] = bitcast <4 x float> [[LANE]] to <8 x bfloat> -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <8 x i16> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i1> [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = sext <8 x i1> [[TMP7]] to <8 x i16> -; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP8]] to <4 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP11]], [[TMP13]] -; CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> [[R]], <8 x bfloat> [[A]], <8 x bfloat> [[DOTCAST1]]) -; CHECK-NEXT: store <4 x i32> [[TMP12]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <4 x float> [[VBFDOT3_I]] -; -entry: - %.cast = bitcast <8 x bfloat> %b to <4 x float> - %lane = shufflevector <4 x float> %.cast, <4 x float> poison, <4 x i32> - %.cast1 = bitcast <4 x float> %lane to <8 x bfloat> - %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %.cast1) - ret <4 x float> %vbfdot3.i -} - -define <2 x float> @test_vbfdot_laneq_f32(<2 x float> %r, <4 x bfloat> %a, <8 x bfloat> %b) sanitize_memory { -; CHECK-LABEL: define <2 x float> @test_vbfdot_laneq_f32( -; CHECK-SAME: <2 x float> [[R:%.*]], <4 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 -; CHECK-NEXT: [[TMP13:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP0]] to <4 x i32> -; CHECK-NEXT: [[DOTCAST:%.*]] = bitcast <8 x bfloat> [[B]] to <4 x float> -; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> splat (i32 -1), <2 x i32> -; CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[DOTCAST]], <4 x float> poison, <2 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[_MSPROP]] to <4 x i16> -; CHECK-NEXT: [[DOTCAST1:%.*]] = bitcast <2 x float> [[LANE]] to <4 x bfloat> -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i16> [[TMP2]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <4 x i16> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <4 x i1> [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i1> [[TMP7]] to <4 x i16> -; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[TMP8]] to <2 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <2 x i32> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = sext <2 x i1> [[TMP10]] to <2 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = or <2 x i32> [[TMP11]], [[TMP13]] -; CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> [[R]], <4 x bfloat> [[A]], <4 x bfloat> [[DOTCAST1]]) -; CHECK-NEXT: store <2 x i32> [[TMP12]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <2 x float> [[VBFDOT3_I]] -; -entry: - %.cast = bitcast <8 x bfloat> %b to <4 x float> - %lane = shufflevector <4 x float> %.cast, <4 x float> poison, <2 x i32> - %.cast1 = bitcast <2 x float> %lane to <4 x bfloat> - %vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %.cast1) - ret <2 x float> %vbfdot3.i -} - -define <4 x float> @test_vbfdotq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) sanitize_memory { -; CHECK-LABEL: define <4 x float> @test_vbfdotq_lane_f32( -; CHECK-SAME: <4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <4 x bfloat> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 -; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP0]] to <2 x i32> -; CHECK-NEXT: [[DOTCAST:%.*]] = bitcast <4 x bfloat> [[B]] to <2 x float> -; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> splat (i32 -1), <4 x i32> zeroinitializer -; CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[DOTCAST]], <2 x float> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[_MSPROP]] to <8 x i16> -; CHECK-NEXT: [[DOTCAST1:%.*]] = bitcast <4 x float> [[LANE]] to <8 x bfloat> -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP2]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <8 x i16> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i1> [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = sext <8 x i1> [[TMP7]] to <8 x i16> -; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP8]] to <4 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP11]], [[TMP13]] -; CHECK-NEXT: [[VBFDOT3_I:%.*]] = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> [[R]], <8 x bfloat> [[A]], <8 x bfloat> [[DOTCAST1]]) -; CHECK-NEXT: store <4 x i32> [[TMP12]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <4 x float> [[VBFDOT3_I]] -; -entry: - %.cast = bitcast <4 x bfloat> %b to <2 x float> - %lane = shufflevector <2 x float> %.cast, <2 x float> poison, <4 x i32> zeroinitializer - %.cast1 = bitcast <4 x float> %lane to <8 x bfloat> - %vbfdot3.i = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %.cast1) - ret <4 x float> %vbfdot3.i -} - define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) sanitize_memory { ; CHECK-LABEL: define <4 x float> @test_vbfmmlaq_f32( ; CHECK-SAME: <4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) #[[ATTR0]] { @@ -207,21 +70,20 @@ define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bflo ; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP0]] to i128 -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP1]] to i128 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to i128 -; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP5]], 0 -; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] -; CHECK-NEXT: br i1 [[_MSOR3]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1:![0-9]+]] -; CHECK: [[BB6]]: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]] -; CHECK-NEXT: unreachable -; CHECK: [[BB7]]: +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to <16 x i8> +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP2]] to <16 x i8> +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <16 x i8> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP6:%.*]] = zext <16 x i1> [[TMP5]] to <16 x i8> +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <16 x i8> [[TMP4]], zeroinitializer +; CHECK-NEXT: [[TMP8:%.*]] = zext <16 x i1> [[TMP7]] to <16 x i8> +; CHECK-NEXT: [[TMP9:%.*]] = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> [[TMP6]], <16 x i8> [[TMP8]]) +; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP9]], splat (i32 8) +; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i32> +; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <4 x i32> [[TMP0]], zeroinitializer +; CHECK-NEXT: [[TMP13:%.*]] = sext <4 x i1> [[TMP12]] to <4 x i32> +; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP11]], [[TMP13]] ; CHECK-NEXT: [[VBFMMLAQ_V3_I:%.*]] = call <4 x float> @llvm.aarch64.neon.bfmmla(<4 x float> [[R]], <8 x bfloat> [[A]], <8 x bfloat> [[B]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store <4 x i32> [[TMP14]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[VBFMMLAQ_V3_I]] ; entry: @@ -283,171 +145,8 @@ entry: ret <4 x float> %vbfmlaltq_v3.i } -define <4 x float> @test_vbfmlalbq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) sanitize_memory { -; CHECK-LABEL: define <4 x float> @test_vbfmlalbq_lane_f32( -; CHECK-SAME: <4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <4 x bfloat> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 -; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> splat (i16 -1), <8 x i32> zeroinitializer -; CHECK-NEXT: [[VECINIT35:%.*]] = shufflevector <4 x bfloat> [[B]], <4 x bfloat> poison, <8 x i32> zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> poison, <8 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i16> [[_MSPROP]], <8 x i16> poison, <8 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP3]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <8 x i16> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i1> [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = sext <8 x i1> [[TMP7]] to <8 x i16> -; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP8]] to <4 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP11]], [[TMP13]] -; CHECK-NEXT: [[VBFMLALBQ_V3_I:%.*]] = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> [[R]], <8 x bfloat> [[A]], <8 x bfloat> [[VECINIT35]]) -; CHECK-NEXT: store <4 x i32> [[TMP12]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <4 x float> [[VBFMLALBQ_V3_I]] -; -entry: - %vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> poison, <8 x i32> zeroinitializer - %vbfmlalbq_v3.i = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) - ret <4 x float> %vbfmlalbq_v3.i -} - -define <4 x float> @test_vbfmlalbq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) sanitize_memory { -; CHECK-LABEL: define <4 x float> @test_vbfmlalbq_laneq_f32( -; CHECK-SAME: <4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 -; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> splat (i16 -1), <8 x i32> -; CHECK-NEXT: [[VECINIT35:%.*]] = shufflevector <8 x bfloat> [[B]], <8 x bfloat> poison, <8 x i32> -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> poison, <8 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i16> [[_MSPROP]], <8 x i16> poison, <8 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP3]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <8 x i16> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i1> [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = sext <8 x i1> [[TMP7]] to <8 x i16> -; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP8]] to <4 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP11]], [[TMP13]] -; CHECK-NEXT: [[VBFMLALBQ_V3_I:%.*]] = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> [[R]], <8 x bfloat> [[A]], <8 x bfloat> [[VECINIT35]]) -; CHECK-NEXT: store <4 x i32> [[TMP12]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <4 x float> [[VBFMLALBQ_V3_I]] -; -entry: - %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> - %vbfmlalbq_v3.i = call <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) - ret <4 x float> %vbfmlalbq_v3.i -} - -define <4 x float> @test_vbfmlaltq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) sanitize_memory { -; CHECK-LABEL: define <4 x float> @test_vbfmlaltq_lane_f32( -; CHECK-SAME: <4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <4 x bfloat> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 -; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> splat (i16 -1), <8 x i32> zeroinitializer -; CHECK-NEXT: [[VECINIT35:%.*]] = shufflevector <4 x bfloat> [[B]], <4 x bfloat> poison, <8 x i32> zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> poison, <8 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i16> [[_MSPROP]], <8 x i16> poison, <8 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP3]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <8 x i16> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i1> [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = sext <8 x i1> [[TMP7]] to <8 x i16> -; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP8]] to <4 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP11]], [[TMP13]] -; CHECK-NEXT: [[VBFMLALTQ_V3_I:%.*]] = call <4 x float> @llvm.aarch64.neon.bfmlalt(<4 x float> [[R]], <8 x bfloat> [[A]], <8 x bfloat> [[VECINIT35]]) -; CHECK-NEXT: store <4 x i32> [[TMP12]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <4 x float> [[VBFMLALTQ_V3_I]] -; -entry: - %vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> poison, <8 x i32> zeroinitializer - %vbfmlaltq_v3.i = call <4 x float> @llvm.aarch64.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) - ret <4 x float> %vbfmlaltq_v3.i -} - -define <4 x float> @test_vbfmlaltq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) sanitize_memory { -; CHECK-LABEL: define <4 x float> @test_vbfmlaltq_laneq_f32( -; CHECK-SAME: <4 x float> [[R:%.*]], <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 -; CHECK-NEXT: [[TMP13:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> splat (i16 -1), <8 x i32> -; CHECK-NEXT: [[VECINIT35:%.*]] = shufflevector <8 x bfloat> [[B]], <8 x bfloat> poison, <8 x i32> -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> poison, <8 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i16> [[_MSPROP]], <8 x i16> poison, <8 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i16> [[TMP3]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = icmp ne <8 x i16> [[TMP4]], zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = or <8 x i1> [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = sext <8 x i1> [[TMP7]] to <8 x i16> -; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i16> [[TMP8]] to <4 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP9]], zeroinitializer -; CHECK-NEXT: [[TMP11:%.*]] = sext <4 x i1> [[TMP10]] to <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = or <4 x i32> [[TMP11]], [[TMP13]] -; CHECK-NEXT: [[VBFMLALTQ_V3_I:%.*]] = call <4 x float> @llvm.aarch64.neon.bfmlalt(<4 x float> [[R]], <8 x bfloat> [[A]], <8 x bfloat> [[VECINIT35]]) -; CHECK-NEXT: store <4 x i32> [[TMP12]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <4 x float> [[VBFMLALTQ_V3_I]] -; -entry: - %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> poison, <8 x i32> - %vbfmlaltq_v3.i = call <4 x float> @llvm.aarch64.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) - ret <4 x float> %vbfmlaltq_v3.i -} - -define <4 x float> @test_vbfdotq_laneq_f32_v4i32_shufflevector(<8 x bfloat> %a, <8 x bfloat> %b) { -; CHECK-LABEL: define <4 x float> @test_vbfdotq_laneq_f32_v4i32_shufflevector( -; CHECK-SAME: <8 x bfloat> [[A:%.*]], <8 x bfloat> [[B:%.*]]) #[[ATTR1:[0-9]+]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x bfloat> [[B]] to <4 x i32> -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to <8 x bfloat> -; CHECK-NEXT: [[VBFDOTQ:%.*]] = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> zeroinitializer, <8 x bfloat> [[A]], <8 x bfloat> [[TMP2]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <4 x float> [[VBFDOTQ]] -; -entry: - %0 = bitcast <8 x bfloat> %b to <4 x i32> - %1 = shufflevector <4 x i32> %0, <4 x i32> poison, <4 x i32> zeroinitializer - %2 = bitcast <4 x i32> %1 to <8 x bfloat> - %vbfdotq = call <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float> zeroinitializer, <8 x bfloat> %a, <8 x bfloat> %2) - ret <4 x float> %vbfdotq -} - -define <2 x float> @test_vbfdotq_laneq_f32_v2i32_shufflevector(<4 x bfloat> %a, <4 x bfloat> %b) { -; CHECK-LABEL: define <2 x float> @test_vbfdotq_laneq_f32_v2i32_shufflevector( -; CHECK-SAME: <4 x bfloat> [[A:%.*]], <4 x bfloat> [[B:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x bfloat> [[B]] to <2 x i32> -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to <4 x bfloat> -; CHECK-NEXT: [[VBFDOTQ:%.*]] = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> zeroinitializer, <4 x bfloat> [[A]], <4 x bfloat> [[TMP2]]) -; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <2 x float> [[VBFDOTQ]] -; -entry: - %0 = bitcast <4 x bfloat> %b to <2 x i32> - %1 = shufflevector <2 x i32> %0, <2 x i32> poison, <2 x i32> zeroinitializer - %2 = bitcast <2 x i32> %1 to <4 x bfloat> - %vbfdotq = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> zeroinitializer, <4 x bfloat> %a, <4 x bfloat> %2) - ret <2 x float> %vbfdotq -} - declare <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bfloat>) declare <4 x float> @llvm.aarch64.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bfloat>) declare <4 x float> @llvm.aarch64.neon.bfmmla(<4 x float>, <8 x bfloat>, <8 x bfloat>) declare <4 x float> @llvm.aarch64.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>) declare <4 x float> @llvm.aarch64.neon.bfmlalt(<4 x float>, <8 x bfloat>, <8 x bfloat>) -;. -; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575} -;. diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-matmul.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-matmul.ll index 5112a65d5ff30..71bd3fc26eb8e 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-matmul.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/aarch64-matmul.ll @@ -22,7 +22,7 @@ define <4 x i32> @smmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) sa ; CHECK-NEXT: [[TMP4:%.*]] = zext <16 x i1> [[TMP3]] to <16 x i8> ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <16 x i8> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = zext <16 x i1> [[TMP5]] to <16 x i8> -; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.smmla.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> [[TMP4]], <16 x i8> [[TMP6]]) +; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> [[TMP4]], <16 x i8> [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = icmp ne <4 x i32> [[TMP7]], splat (i32 8) ; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i1> [[TMP8]] to <4 x i32> ; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP0]], zeroinitializer @@ -76,7 +76,7 @@ define <4 x i32> @usmmla.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 x i8> %b) s ; CHECK-NEXT: [[TMP4:%.*]] = zext <16 x i1> [[TMP3]] to <16 x i8> ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq <16 x i8> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = zext <16 x i1> [[TMP5]] to <16 x i8> -; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.usmmla.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> [[TMP4]], <16 x i8> [[TMP6]]) +; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.ummla.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> [[TMP4]], <16 x i8> [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = icmp ne <4 x i32> [[TMP7]], splat (i32 8) ; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i1> [[TMP8]] to <4 x i32> ; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <4 x i32> [[TMP0]], zeroinitializer diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcmp.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcmp.ll new file mode 100644 index 0000000000000..b7bbae7680801 --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vcmp.ll @@ -0,0 +1,731 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -passes=msan -S | FileCheck %s +; +; Handled strictly (suboptimal): (none) +; +; Handled heuristically: (none) +; +; Forked from llvm/test/CodeGen/AArch64/arm64-vcmp.ll + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android9001" + +define void @fcmltz_4s(<4 x float> %a, ptr %p) nounwind sanitize_memory { +; CHECK-LABEL: define void @fcmltz_4s( +; CHECK-SAME: <4 x float> [[A:%.*]], ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i1> +; CHECK-NEXT: [[TEMP:%.*]] = fcmp olt <4 x float> [[A]], zeroinitializer +; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i16> +; CHECK-NEXT: [[TEMP2:%.*]] = sext <4 x i1> [[TEMP]] to <4 x i16> +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1:![0-9]+]] +; CHECK: [[BB4]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]] +; CHECK-NEXT: unreachable +; CHECK: [[BB5]]: +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[P]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 193514046488576 +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; CHECK-NEXT: store <4 x i16> [[_MSPROP1]], ptr [[TMP8]], align 8 +; CHECK-NEXT: store <4 x i16> [[TEMP2]], ptr [[P]], align 8 +; CHECK-NEXT: ret void +; + %temp = fcmp olt <4 x float> %a, zeroinitializer + %temp2 = sext <4 x i1> %temp to <4 x i16> + store <4 x i16> %temp2, ptr %p, align 8 + ret void +} + +define <2 x i32> @facge_2s(<2 x float> %A, <2 x float> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <2 x i32> @facge_2s( +; CHECK-SAME: <2 x float> [[A:%.*]], <2 x float> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i32> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i32> +; CHECK-NEXT: [[TEMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float> [[A]], <2 x float> [[B]]) +; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <2 x i32> [[TEMP3]] +; + %temp3 = call <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float> %A, <2 x float> %B) + ret <2 x i32> %temp3 +} + +define <4 x i32> @facge_4s(<4 x float> %A, <4 x float> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <4 x i32> @facge_4s( +; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i32> +; CHECK-NEXT: [[TEMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float> [[A]], <4 x float> [[B]]) +; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <4 x i32> [[TEMP3]] +; + %temp3 = call <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float> %A, <4 x float> %B) + ret <4 x i32> %temp3 +} + +define <2 x i64> @facge_2d(<2 x double> %A, <2 x double> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <2 x i64> @facge_2d( +; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i64> +; CHECK-NEXT: [[TEMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double> [[A]], <2 x double> [[B]]) +; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <2 x i64> [[TEMP3]] +; + %temp3 = call <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double> %A, <2 x double> %B) + ret <2 x i64> %temp3 +} + +declare <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone +declare <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone +declare <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone + +define <2 x i32> @facgt_2s(<2 x float> %A, <2 x float> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <2 x i32> @facgt_2s( +; CHECK-SAME: <2 x float> [[A:%.*]], <2 x float> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i32> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i32> +; CHECK-NEXT: [[TEMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32(<2 x float> [[A]], <2 x float> [[B]]) +; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <2 x i32> [[TEMP3]] +; + %temp3 = call <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32(<2 x float> %A, <2 x float> %B) + ret <2 x i32> %temp3 +} + +define <4 x i32> @facgt_4s(<4 x float> %A, <4 x float> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <4 x i32> @facgt_4s( +; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i32> +; CHECK-NEXT: [[TEMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.facgt.v4i32.v4f32(<4 x float> [[A]], <4 x float> [[B]]) +; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <4 x i32> [[TEMP3]] +; + %temp3 = call <4 x i32> @llvm.aarch64.neon.facgt.v4i32.v4f32(<4 x float> %A, <4 x float> %B) + ret <4 x i32> %temp3 +} + +define <2 x i64> @facgt_2d(<2 x double> %A, <2 x double> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <2 x i64> @facgt_2d( +; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i64> +; CHECK-NEXT: [[TEMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double> [[A]], <2 x double> [[B]]) +; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <2 x i64> [[TEMP3]] +; + %temp3 = call <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double> %A, <2 x double> %B) + ret <2 x i64> %temp3 +} + +declare <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32(<2 x float>, <2 x float>) nounwind readnone +declare <4 x i32> @llvm.aarch64.neon.facgt.v4i32.v4f32(<4 x float>, <4 x float>) nounwind readnone +declare <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone + +define i32 @facge_s(float %A, float %B) nounwind sanitize_memory { +; CHECK-LABEL: define i32 @facge_s( +; CHECK-SAME: float [[A:%.*]], float [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP4]] to i32 +; CHECK-NEXT: [[MASK:%.*]] = call i32 @llvm.aarch64.neon.facge.i32.f32(float [[A]], float [[B]]) +; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i32 [[MASK]] +; + %mask = call i32 @llvm.aarch64.neon.facge.i32.f32(float %A, float %B) + ret i32 %mask +} + +define i64 @facge_d(double %A, double %B) nounwind sanitize_memory { +; CHECK-LABEL: define i64 @facge_d( +; CHECK-SAME: double [[A:%.*]], double [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP4]] to i64 +; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.aarch64.neon.facge.i64.f64(double [[A]], double [[B]]) +; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[MASK]] +; + %mask = call i64 @llvm.aarch64.neon.facge.i64.f64(double %A, double %B) + ret i64 %mask +} + +declare i64 @llvm.aarch64.neon.facge.i64.f64(double, double) +declare i32 @llvm.aarch64.neon.facge.i32.f32(float, float) + +define i32 @facgt_s(float %A, float %B) nounwind sanitize_memory { +; CHECK-LABEL: define i32 @facgt_s( +; CHECK-SAME: float [[A:%.*]], float [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP4]] to i32 +; CHECK-NEXT: [[MASK:%.*]] = call i32 @llvm.aarch64.neon.facgt.i32.f32(float [[A]], float [[B]]) +; CHECK-NEXT: store i32 [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i32 [[MASK]] +; + %mask = call i32 @llvm.aarch64.neon.facgt.i32.f32(float %A, float %B) + ret i32 %mask +} + +define i64 @facgt_d(double %A, double %B) nounwind sanitize_memory { +; CHECK-LABEL: define i64 @facgt_d( +; CHECK-SAME: double [[A:%.*]], double [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = sext i1 [[TMP4]] to i64 +; CHECK-NEXT: [[MASK:%.*]] = call i64 @llvm.aarch64.neon.facgt.i64.f64(double [[A]], double [[B]]) +; CHECK-NEXT: store i64 [[TMP5]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[MASK]] +; + %mask = call i64 @llvm.aarch64.neon.facgt.i64.f64(double %A, double %B) + ret i64 %mask +} + +declare i64 @llvm.aarch64.neon.facgt.i64.f64(double, double) +declare i32 @llvm.aarch64.neon.facgt.i32.f32(float, float) + +define <8 x i8> @cmtst_8b(ptr %A, ptr %B) nounwind sanitize_memory { +; CHECK-LABEL: define <8 x i8> @cmtst_8b( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] +; CHECK: [[BB3]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB4]]: +; CHECK-NEXT: [[TEMP1:%.*]] = load <8 x i8>, ptr [[A]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8 +; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] +; CHECK: [[BB8]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB9]]: +; CHECK-NEXT: [[TEMP2:%.*]] = load <8 x i8>, ptr [[B]], align 8 +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8 +; CHECK-NEXT: [[TMP13:%.*]] = and <8 x i8> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP14:%.*]] = and <8 x i8> [[TEMP1]], [[_MSLD1]] +; CHECK-NEXT: [[TMP15:%.*]] = and <8 x i8> [[_MSLD]], [[TEMP2]] +; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i8> [[TMP13]], [[TMP14]] +; CHECK-NEXT: [[TMP17:%.*]] = or <8 x i8> [[TMP16]], [[TMP15]] +; CHECK-NEXT: [[COMMONBITS:%.*]] = and <8 x i8> [[TEMP1]], [[TEMP2]] +; CHECK-NEXT: [[TMP18:%.*]] = xor <8 x i8> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[TMP19:%.*]] = or <8 x i8> [[TMP17]], zeroinitializer +; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <8 x i8> [[TMP19]], zeroinitializer +; CHECK-NEXT: [[TMP21:%.*]] = xor <8 x i8> [[TMP19]], splat (i8 -1) +; CHECK-NEXT: [[TMP22:%.*]] = and <8 x i8> [[TMP21]], [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq <8 x i8> [[TMP22]], zeroinitializer +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and <8 x i1> [[TMP20]], [[TMP23]] +; CHECK-NEXT: [[MASK:%.*]] = icmp ne <8 x i8> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[_MSPROP:%.*]] = sext <8 x i1> [[_MSPROP_ICMP]] to <8 x i8> +; CHECK-NEXT: [[RES:%.*]] = sext <8 x i1> [[MASK]] to <8 x i8> +; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <8 x i8> [[RES]] +; + %temp1 = load <8 x i8>, ptr %A + %temp2 = load <8 x i8>, ptr %B + %commonbits = and <8 x i8> %temp1, %temp2 + %mask = icmp ne <8 x i8> %commonbits, zeroinitializer + %res = sext <8 x i1> %mask to <8 x i8> + ret <8 x i8> %res +} + +define <16 x i8> @cmtst_16b(ptr %A, ptr %B) nounwind sanitize_memory { +; CHECK-LABEL: define <16 x i8> @cmtst_16b( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] +; CHECK: [[BB3]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB4]]: +; CHECK-NEXT: [[TEMP1:%.*]] = load <16 x i8>, ptr [[A]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 16 +; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] +; CHECK: [[BB8]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB9]]: +; CHECK-NEXT: [[TEMP2:%.*]] = load <16 x i8>, ptr [[B]], align 16 +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16 +; CHECK-NEXT: [[TMP13:%.*]] = and <16 x i8> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP14:%.*]] = and <16 x i8> [[TEMP1]], [[_MSLD1]] +; CHECK-NEXT: [[TMP15:%.*]] = and <16 x i8> [[_MSLD]], [[TEMP2]] +; CHECK-NEXT: [[TMP16:%.*]] = or <16 x i8> [[TMP13]], [[TMP14]] +; CHECK-NEXT: [[TMP17:%.*]] = or <16 x i8> [[TMP16]], [[TMP15]] +; CHECK-NEXT: [[COMMONBITS:%.*]] = and <16 x i8> [[TEMP1]], [[TEMP2]] +; CHECK-NEXT: [[TMP18:%.*]] = xor <16 x i8> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[TMP19:%.*]] = or <16 x i8> [[TMP17]], zeroinitializer +; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <16 x i8> [[TMP19]], zeroinitializer +; CHECK-NEXT: [[TMP21:%.*]] = xor <16 x i8> [[TMP19]], splat (i8 -1) +; CHECK-NEXT: [[TMP22:%.*]] = and <16 x i8> [[TMP21]], [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq <16 x i8> [[TMP22]], zeroinitializer +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and <16 x i1> [[TMP20]], [[TMP23]] +; CHECK-NEXT: [[MASK:%.*]] = icmp ne <16 x i8> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[_MSPROP:%.*]] = sext <16 x i1> [[_MSPROP_ICMP]] to <16 x i8> +; CHECK-NEXT: [[RES:%.*]] = sext <16 x i1> [[MASK]] to <16 x i8> +; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <16 x i8> [[RES]] +; + %temp1 = load <16 x i8>, ptr %A + %temp2 = load <16 x i8>, ptr %B + %commonbits = and <16 x i8> %temp1, %temp2 + %mask = icmp ne <16 x i8> %commonbits, zeroinitializer + %res = sext <16 x i1> %mask to <16 x i8> + ret <16 x i8> %res +} + +define <4 x i16> @cmtst_4h(ptr %A, ptr %B) nounwind sanitize_memory { +; CHECK-LABEL: define <4 x i16> @cmtst_4h( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] +; CHECK: [[BB3]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB4]]: +; CHECK-NEXT: [[TEMP1:%.*]] = load <4 x i16>, ptr [[A]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8 +; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] +; CHECK: [[BB8]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB9]]: +; CHECK-NEXT: [[TEMP2:%.*]] = load <4 x i16>, ptr [[B]], align 8 +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8 +; CHECK-NEXT: [[TMP13:%.*]] = and <4 x i16> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP14:%.*]] = and <4 x i16> [[TEMP1]], [[_MSLD1]] +; CHECK-NEXT: [[TMP15:%.*]] = and <4 x i16> [[_MSLD]], [[TEMP2]] +; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i16> [[TMP13]], [[TMP14]] +; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i16> [[TMP16]], [[TMP15]] +; CHECK-NEXT: [[COMMONBITS:%.*]] = and <4 x i16> [[TEMP1]], [[TEMP2]] +; CHECK-NEXT: [[TMP18:%.*]] = xor <4 x i16> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[TMP19:%.*]] = or <4 x i16> [[TMP17]], zeroinitializer +; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <4 x i16> [[TMP19]], zeroinitializer +; CHECK-NEXT: [[TMP21:%.*]] = xor <4 x i16> [[TMP19]], splat (i16 -1) +; CHECK-NEXT: [[TMP22:%.*]] = and <4 x i16> [[TMP21]], [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq <4 x i16> [[TMP22]], zeroinitializer +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and <4 x i1> [[TMP20]], [[TMP23]] +; CHECK-NEXT: [[MASK:%.*]] = icmp ne <4 x i16> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[_MSPROP:%.*]] = sext <4 x i1> [[_MSPROP_ICMP]] to <4 x i16> +; CHECK-NEXT: [[RES:%.*]] = sext <4 x i1> [[MASK]] to <4 x i16> +; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <4 x i16> [[RES]] +; + %temp1 = load <4 x i16>, ptr %A + %temp2 = load <4 x i16>, ptr %B + %commonbits = and <4 x i16> %temp1, %temp2 + %mask = icmp ne <4 x i16> %commonbits, zeroinitializer + %res = sext <4 x i1> %mask to <4 x i16> + ret <4 x i16> %res +} + +define <8 x i16> @cmtst_8h(ptr %A, ptr %B) nounwind sanitize_memory { +; CHECK-LABEL: define <8 x i16> @cmtst_8h( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] +; CHECK: [[BB3]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB4]]: +; CHECK-NEXT: [[TEMP1:%.*]] = load <8 x i16>, ptr [[A]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16 +; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] +; CHECK: [[BB8]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB9]]: +; CHECK-NEXT: [[TEMP2:%.*]] = load <8 x i16>, ptr [[B]], align 16 +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16 +; CHECK-NEXT: [[TMP13:%.*]] = and <8 x i16> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP14:%.*]] = and <8 x i16> [[TEMP1]], [[_MSLD1]] +; CHECK-NEXT: [[TMP15:%.*]] = and <8 x i16> [[_MSLD]], [[TEMP2]] +; CHECK-NEXT: [[TMP16:%.*]] = or <8 x i16> [[TMP13]], [[TMP14]] +; CHECK-NEXT: [[TMP17:%.*]] = or <8 x i16> [[TMP16]], [[TMP15]] +; CHECK-NEXT: [[COMMONBITS:%.*]] = and <8 x i16> [[TEMP1]], [[TEMP2]] +; CHECK-NEXT: [[TMP18:%.*]] = xor <8 x i16> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[TMP19:%.*]] = or <8 x i16> [[TMP17]], zeroinitializer +; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <8 x i16> [[TMP19]], zeroinitializer +; CHECK-NEXT: [[TMP21:%.*]] = xor <8 x i16> [[TMP19]], splat (i16 -1) +; CHECK-NEXT: [[TMP22:%.*]] = and <8 x i16> [[TMP21]], [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq <8 x i16> [[TMP22]], zeroinitializer +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and <8 x i1> [[TMP20]], [[TMP23]] +; CHECK-NEXT: [[MASK:%.*]] = icmp ne <8 x i16> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[_MSPROP:%.*]] = sext <8 x i1> [[_MSPROP_ICMP]] to <8 x i16> +; CHECK-NEXT: [[RES:%.*]] = sext <8 x i1> [[MASK]] to <8 x i16> +; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <8 x i16> [[RES]] +; + %temp1 = load <8 x i16>, ptr %A + %temp2 = load <8 x i16>, ptr %B + %commonbits = and <8 x i16> %temp1, %temp2 + %mask = icmp ne <8 x i16> %commonbits, zeroinitializer + %res = sext <8 x i1> %mask to <8 x i16> + ret <8 x i16> %res +} + +define <2 x i32> @cmtst_2s(ptr %A, ptr %B) nounwind sanitize_memory { +; CHECK-LABEL: define <2 x i32> @cmtst_2s( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] +; CHECK: [[BB3]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB4]]: +; CHECK-NEXT: [[TEMP1:%.*]] = load <2 x i32>, ptr [[A]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8 +; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] +; CHECK: [[BB8]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB9]]: +; CHECK-NEXT: [[TEMP2:%.*]] = load <2 x i32>, ptr [[B]], align 8 +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8 +; CHECK-NEXT: [[TMP13:%.*]] = and <2 x i32> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i32> [[TEMP1]], [[_MSLD1]] +; CHECK-NEXT: [[TMP15:%.*]] = and <2 x i32> [[_MSLD]], [[TEMP2]] +; CHECK-NEXT: [[TMP16:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]] +; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i32> [[TMP16]], [[TMP15]] +; CHECK-NEXT: [[COMMONBITS:%.*]] = and <2 x i32> [[TEMP1]], [[TEMP2]] +; CHECK-NEXT: [[TMP18:%.*]] = xor <2 x i32> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[TMP19:%.*]] = or <2 x i32> [[TMP17]], zeroinitializer +; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <2 x i32> [[TMP19]], zeroinitializer +; CHECK-NEXT: [[TMP21:%.*]] = xor <2 x i32> [[TMP19]], splat (i32 -1) +; CHECK-NEXT: [[TMP22:%.*]] = and <2 x i32> [[TMP21]], [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq <2 x i32> [[TMP22]], zeroinitializer +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and <2 x i1> [[TMP20]], [[TMP23]] +; CHECK-NEXT: [[MASK:%.*]] = icmp ne <2 x i32> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[_MSPROP:%.*]] = sext <2 x i1> [[_MSPROP_ICMP]] to <2 x i32> +; CHECK-NEXT: [[RES:%.*]] = sext <2 x i1> [[MASK]] to <2 x i32> +; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <2 x i32> [[RES]] +; + %temp1 = load <2 x i32>, ptr %A + %temp2 = load <2 x i32>, ptr %B + %commonbits = and <2 x i32> %temp1, %temp2 + %mask = icmp ne <2 x i32> %commonbits, zeroinitializer + %res = sext <2 x i1> %mask to <2 x i32> + ret <2 x i32> %res +} + +define <4 x i32> @cmtst_4s(ptr %A, ptr %B) nounwind sanitize_memory { +; CHECK-LABEL: define <4 x i32> @cmtst_4s( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] +; CHECK: [[BB3]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB4]]: +; CHECK-NEXT: [[TEMP1:%.*]] = load <4 x i32>, ptr [[A]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16 +; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] +; CHECK: [[BB8]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB9]]: +; CHECK-NEXT: [[TEMP2:%.*]] = load <4 x i32>, ptr [[B]], align 16 +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16 +; CHECK-NEXT: [[TMP13:%.*]] = and <4 x i32> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP14:%.*]] = and <4 x i32> [[TEMP1]], [[_MSLD1]] +; CHECK-NEXT: [[TMP15:%.*]] = and <4 x i32> [[_MSLD]], [[TEMP2]] +; CHECK-NEXT: [[TMP16:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]] +; CHECK-NEXT: [[TMP17:%.*]] = or <4 x i32> [[TMP16]], [[TMP15]] +; CHECK-NEXT: [[COMMONBITS:%.*]] = and <4 x i32> [[TEMP1]], [[TEMP2]] +; CHECK-NEXT: [[TMP18:%.*]] = xor <4 x i32> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[TMP19:%.*]] = or <4 x i32> [[TMP17]], zeroinitializer +; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <4 x i32> [[TMP19]], zeroinitializer +; CHECK-NEXT: [[TMP21:%.*]] = xor <4 x i32> [[TMP19]], splat (i32 -1) +; CHECK-NEXT: [[TMP22:%.*]] = and <4 x i32> [[TMP21]], [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq <4 x i32> [[TMP22]], zeroinitializer +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and <4 x i1> [[TMP20]], [[TMP23]] +; CHECK-NEXT: [[MASK:%.*]] = icmp ne <4 x i32> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[_MSPROP:%.*]] = sext <4 x i1> [[_MSPROP_ICMP]] to <4 x i32> +; CHECK-NEXT: [[RES:%.*]] = sext <4 x i1> [[MASK]] to <4 x i32> +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %temp1 = load <4 x i32>, ptr %A + %temp2 = load <4 x i32>, ptr %B + %commonbits = and <4 x i32> %temp1, %temp2 + %mask = icmp ne <4 x i32> %commonbits, zeroinitializer + %res = sext <4 x i1> %mask to <4 x i32> + ret <4 x i32> %res +} + +define <2 x i64> @cmtst_2d(ptr %A, ptr %B) nounwind sanitize_memory { +; CHECK-LABEL: define <2 x i64> @cmtst_2d( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]] +; CHECK: [[BB3]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB4]]: +; CHECK-NEXT: [[TEMP1:%.*]] = load <2 x i64>, ptr [[A]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16 +; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] +; CHECK: [[BB8]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB9]]: +; CHECK-NEXT: [[TEMP2:%.*]] = load <2 x i64>, ptr [[B]], align 16 +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 16 +; CHECK-NEXT: [[TMP13:%.*]] = and <2 x i64> [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i64> [[TEMP1]], [[_MSLD1]] +; CHECK-NEXT: [[TMP15:%.*]] = and <2 x i64> [[_MSLD]], [[TEMP2]] +; CHECK-NEXT: [[TMP16:%.*]] = or <2 x i64> [[TMP13]], [[TMP14]] +; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i64> [[TMP16]], [[TMP15]] +; CHECK-NEXT: [[COMMONBITS:%.*]] = and <2 x i64> [[TEMP1]], [[TEMP2]] +; CHECK-NEXT: [[TMP18:%.*]] = xor <2 x i64> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[TMP19:%.*]] = or <2 x i64> [[TMP17]], zeroinitializer +; CHECK-NEXT: [[TMP20:%.*]] = icmp ne <2 x i64> [[TMP19]], zeroinitializer +; CHECK-NEXT: [[TMP21:%.*]] = xor <2 x i64> [[TMP19]], splat (i64 -1) +; CHECK-NEXT: [[TMP22:%.*]] = and <2 x i64> [[TMP21]], [[TMP18]] +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq <2 x i64> [[TMP22]], zeroinitializer +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and <2 x i1> [[TMP20]], [[TMP23]] +; CHECK-NEXT: [[MASK:%.*]] = icmp ne <2 x i64> [[COMMONBITS]], zeroinitializer +; CHECK-NEXT: [[_MSPROP:%.*]] = sext <2 x i1> [[_MSPROP_ICMP]] to <2 x i64> +; CHECK-NEXT: [[RES:%.*]] = sext <2 x i1> [[MASK]] to <2 x i64> +; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <2 x i64> [[RES]] +; + %temp1 = load <2 x i64>, ptr %A + %temp2 = load <2 x i64>, ptr %B + %commonbits = and <2 x i64> %temp1, %temp2 + %mask = icmp ne <2 x i64> %commonbits, zeroinitializer + %res = sext <2 x i1> %mask to <2 x i64> + ret <2 x i64> %res +} + +define <1 x i64> @fcmeq_d(<1 x double> %A, <1 x double> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <1 x i64> @fcmeq_d( +; CHECK-SAME: <1 x double> [[A:%.*]], <1 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <1 x i64> [[_MSPROP]], zeroinitializer +; CHECK-NEXT: [[TST:%.*]] = fcmp oeq <1 x double> [[A]], [[B]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <1 x i1> [[TMP3]] to <1 x i64> +; CHECK-NEXT: [[MASK:%.*]] = sext <1 x i1> [[TST]] to <1 x i64> +; CHECK-NEXT: store <1 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <1 x i64> [[MASK]] +; + %tst = fcmp oeq <1 x double> %A, %B + %mask = sext <1 x i1> %tst to <1 x i64> + ret <1 x i64> %mask +} + +define <1 x i64> @fcmge_d(<1 x double> %A, <1 x double> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <1 x i64> @fcmge_d( +; CHECK-SAME: <1 x double> [[A:%.*]], <1 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <1 x i64> [[_MSPROP]], zeroinitializer +; CHECK-NEXT: [[TST:%.*]] = fcmp oge <1 x double> [[A]], [[B]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <1 x i1> [[TMP3]] to <1 x i64> +; CHECK-NEXT: [[MASK:%.*]] = sext <1 x i1> [[TST]] to <1 x i64> +; CHECK-NEXT: store <1 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <1 x i64> [[MASK]] +; + %tst = fcmp oge <1 x double> %A, %B + %mask = sext <1 x i1> %tst to <1 x i64> + ret <1 x i64> %mask +} + +define <1 x i64> @fcmle_d(<1 x double> %A, <1 x double> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <1 x i64> @fcmle_d( +; CHECK-SAME: <1 x double> [[A:%.*]], <1 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <1 x i64> [[_MSPROP]], zeroinitializer +; CHECK-NEXT: [[TST:%.*]] = fcmp ole <1 x double> [[A]], [[B]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <1 x i1> [[TMP3]] to <1 x i64> +; CHECK-NEXT: [[MASK:%.*]] = sext <1 x i1> [[TST]] to <1 x i64> +; CHECK-NEXT: store <1 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <1 x i64> [[MASK]] +; + %tst = fcmp ole <1 x double> %A, %B + %mask = sext <1 x i1> %tst to <1 x i64> + ret <1 x i64> %mask +} + +define <1 x i64> @fcmgt_d(<1 x double> %A, <1 x double> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <1 x i64> @fcmgt_d( +; CHECK-SAME: <1 x double> [[A:%.*]], <1 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <1 x i64> [[_MSPROP]], zeroinitializer +; CHECK-NEXT: [[TST:%.*]] = fcmp ogt <1 x double> [[A]], [[B]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <1 x i1> [[TMP3]] to <1 x i64> +; CHECK-NEXT: [[MASK:%.*]] = sext <1 x i1> [[TST]] to <1 x i64> +; CHECK-NEXT: store <1 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <1 x i64> [[MASK]] +; + %tst = fcmp ogt <1 x double> %A, %B + %mask = sext <1 x i1> %tst to <1 x i64> + ret <1 x i64> %mask +} + +define <1 x i64> @fcmlt_d(<1 x double> %A, <1 x double> %B) nounwind sanitize_memory { +; CHECK-LABEL: define <1 x i64> @fcmlt_d( +; CHECK-SAME: <1 x double> [[A:%.*]], <1 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <1 x i64> [[_MSPROP]], zeroinitializer +; CHECK-NEXT: [[TST:%.*]] = fcmp olt <1 x double> [[A]], [[B]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <1 x i1> [[TMP3]] to <1 x i64> +; CHECK-NEXT: [[MASK:%.*]] = sext <1 x i1> [[TST]] to <1 x i64> +; CHECK-NEXT: store <1 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <1 x i64> [[MASK]] +; + %tst = fcmp olt <1 x double> %A, %B + %mask = sext <1 x i1> %tst to <1 x i64> + ret <1 x i64> %mask +} + +define <1 x i64> @cmnez_d(<1 x i64> %A) nounwind sanitize_memory { +; CHECK-LABEL: define <1 x i64> @cmnez_d( +; CHECK-SAME: <1 x i64> [[A:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP2:%.*]] = xor <1 x i64> [[A]], zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = or <1 x i64> [[TMP1]], zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <1 x i64> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = xor <1 x i64> [[TMP3]], splat (i64 -1) +; CHECK-NEXT: [[TMP6:%.*]] = and <1 x i64> [[TMP5]], [[TMP2]] +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <1 x i64> [[TMP6]], zeroinitializer +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and <1 x i1> [[TMP4]], [[TMP7]] +; CHECK-NEXT: [[TST:%.*]] = icmp ne <1 x i64> [[A]], zeroinitializer +; CHECK-NEXT: [[_MSPROP:%.*]] = sext <1 x i1> [[_MSPROP_ICMP]] to <1 x i64> +; CHECK-NEXT: [[MASK:%.*]] = sext <1 x i1> [[TST]] to <1 x i64> +; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <1 x i64> [[MASK]] +; + %tst = icmp ne <1 x i64> %A, zeroinitializer + %mask = sext <1 x i1> %tst to <1 x i64> + ret <1 x i64> %mask +} +;. +; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575} +;. diff --git a/llvm/test/Instrumentation/MemorySanitizer/switch-icmp.ll b/llvm/test/Instrumentation/MemorySanitizer/switch-icmp.ll new file mode 100644 index 0000000000000..08e56516ff5b5 --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/switch-icmp.ll @@ -0,0 +1,135 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -S -passes=msan 2>&1 | FileCheck %s + +; This test compares the instrumentation for two loosely-equivalent patterns: +; (icmp eq + br) vs. switch. +; +; (icmp eq) can have an initialized output even if the inputs are partly +; uninitialized, if a bit is initialized in both inputs but has a different +; value. +; +; If switch has a partly uninitialized input, but it is possible to rule out +; matching any of the cases, it will use the default case instead of reporting +; use-of-uninitialized memory. This is equivalent to if the switch was replaced +; by a series of (icmp eq + br). + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i64 @switch_test(i32 %wii) sanitize_memory { +; CHECK-LABEL: define i64 @switch_test( +; CHECK-SAME: i32 [[WII:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[WII]], 42 +; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], -1 +; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], [[TMP3]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP5]], [[TMP8]] +; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[WII]], 43 +; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0 +; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1 +; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], [[TMP9]] +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0 +; CHECK-NEXT: [[_MSPROP_ICMP1:%.*]] = and i1 [[TMP11]], [[TMP14]] +; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[_MSPROP_ICMP]], [[_MSPROP_ICMP1]] +; CHECK-NEXT: br i1 [[TMP15]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1:![0-9]+]] +; CHECK: [[BB2]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]] +; CHECK-NEXT: unreachable +; CHECK: [[BB3]]: +; CHECK-NEXT: switch i32 [[WII]], label %[[U:.*]] [ +; CHECK-NEXT: i32 42, label %[[SNES:.*]] +; CHECK-NEXT: i32 43, label %[[NES:.*]] +; CHECK-NEXT: ] +; CHECK: [[SNES]]: +; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 420 +; CHECK: [[NES]]: +; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 430 +; CHECK: [[U]]: +; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 0 +; + switch i32 %wii, label %u [ + i32 42, label %snes + i32 43, label %nes + ] + +snes: + ret i64 420 + +nes: + ret i64 430 + +u: + ret i64 0 +} + +define i64 @icmp_test(i32 %wii) sanitize_memory { +; CHECK-LABEL: define i64 @icmp_test( +; CHECK-SAME: i32 [[WII:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[WII]], 42 +; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], -1 +; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], [[TMP2]] +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 +; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP4]], [[TMP7]] +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[WII]], 42 +; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]] +; CHECK: [[BB8]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB9]]: +; CHECK-NEXT: br i1 [[CMP1]], label %[[SNES:.*]], label %[[ELSE:.*]] +; CHECK: [[SNES]]: +; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 420 +; CHECK: [[ELSE]]: +; CHECK-NEXT: [[TMP10:%.*]] = xor i32 [[WII]], 43 +; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 +; CHECK-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], -1 +; CHECK-NEXT: [[TMP14:%.*]] = and i32 [[TMP13]], [[TMP10]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0 +; CHECK-NEXT: [[_MSPROP_ICMP1:%.*]] = and i1 [[TMP12]], [[TMP15]] +; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[WII]], 43 +; CHECK-NEXT: br i1 [[_MSPROP_ICMP1]], label %[[BB16:.*]], label %[[BB17:.*]], !prof [[PROF1]] +; CHECK: [[BB16]]: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]] +; CHECK-NEXT: unreachable +; CHECK: [[BB17]]: +; CHECK-NEXT: br i1 [[CMP2]], label %[[NES:.*]], label %[[U:.*]] +; CHECK: [[NES]]: +; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 430 +; CHECK: [[U]]: +; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 0 +; + %cmp1 = icmp eq i32 %wii, 42 + br i1 %cmp1, label %snes, label %else + +snes: + ret i64 420 + +else: + %cmp2 = icmp eq i32 %wii, 43 + br i1 %cmp2, label %nes, label %u + +nes: + ret i64 430 + +u: + ret i64 0 +} +;. +; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575} +;. diff --git a/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll b/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll index 0f3287b07697b..304508d9f86c4 100644 --- a/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll +++ b/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll @@ -914,4 +914,4 @@ entry: } -attributes #0 = { nounwind readonly uwtable sanitize_numerical_stability "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #0 = { nounwind readonly uwtable sanitize_numerical_stability "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign, float: ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } diff --git a/llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll b/llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll index ce2daedf94b0b..aa1df9566d4f4 100644 --- a/llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll +++ b/llvm/test/Instrumentation/NumericalStabilitySanitizer/non_float_store.ll @@ -16,4 +16,4 @@ entry: ret void } -attributes #0 = { nounwind readonly uwtable sanitize_numerical_stability "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="true" "use-soft-float"="false" } +attributes #0 = { nounwind readonly uwtable sanitize_numerical_stability "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign, float: ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="true" "use-soft-float"="false" } diff --git a/llvm/test/Instrumentation/NumericalStabilitySanitizer/scalable_vector.ll b/llvm/test/Instrumentation/NumericalStabilitySanitizer/scalable_vector.ll index 3263b8b5fe749..c071ce70d25c3 100644 --- a/llvm/test/Instrumentation/NumericalStabilitySanitizer/scalable_vector.ll +++ b/llvm/test/Instrumentation/NumericalStabilitySanitizer/scalable_vector.ll @@ -12,4 +12,4 @@ define void @add_scalable_vector( %a) sanitize_numerical_st ret void } -attributes #0 = { nounwind readonly uwtable sanitize_numerical_stability "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="true" "use-soft-float"="false" } +attributes #0 = { nounwind readonly uwtable sanitize_numerical_stability "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(preservesign, float: ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="true" "use-soft-float"="false" } diff --git a/llvm/test/LTO/PowerPC/ifunc-aix.ll b/llvm/test/LTO/PowerPC/ifunc-aix.ll new file mode 100644 index 0000000000000..f120eaabe4a39 --- /dev/null +++ b/llvm/test/LTO/PowerPC/ifunc-aix.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s > %t +; RUN: llvm-lto -list-symbols-only %t | FileCheck %s + +; CHECK: foo { function defined default } + +target triple = "powerpc-ibm-aix7.2.0.0" + +@foo = ifunc i32 (...), ptr @foo.resolver + +define internal ptr @foo.resolver() { +entry: + ret ptr @my_foo2 +} + +define internal i32 @my_foo2() { +entry: + ret i32 5 +} diff --git a/llvm/test/MC/AMDGPU/exp-gfx11.s b/llvm/test/MC/AMDGPU/exp-gfx11.s new file mode 100644 index 0000000000000..57aaa5e6f5e76 --- /dev/null +++ b/llvm/test/MC/AMDGPU/exp-gfx11.s @@ -0,0 +1,20 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --sort --version 6 +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s -filetype=null 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s -filetype=null 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 --implicit-check-not=error: %s + +exp dual_src_blend0 v4, v3, v2, v1 +// GFX11: exp dual_src_blend0 v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] +// PREGFX11: :[[@LINE-2]]:5: error: exp target is not supported on this GPU + +exp dual_src_blend1 v2, v3, off, off +// GFX11: exp dual_src_blend1 v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] +// PREGFX11: :[[@LINE-2]]:5: error: exp target is not supported on this GPU + +exp mrtz v4, v3, off, off done row_en +// GFX11: exp mrtz v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] +// PREGFX11: :[[@LINE-2]]:32: error: invalid operand for instruction + +exp mrtz v4, v3, v2, v1 row_en +// GFX11: exp mrtz v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] +// PREGFX11: :[[@LINE-2]]:25: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_exp.s b/llvm/test/MC/AMDGPU/gfx10_asm_exp.s new file mode 100644 index 0000000000000..b7e45d18e7058 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx10_asm_exp.s @@ -0,0 +1,145 @@ +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s + +exp mrt0 v0, v0, v0, v0 +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] + + +exp mrt0 v0, v0, v0, v0 done +// CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 done +// CHECK: exp mrtz v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 done +// CHECK: exp null v0, v0, v0, v0 done ; encoding: [0x9f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 done +// CHECK: exp pos0 v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 done +// CHECK: exp param0 v0, v0, v0, v0 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 done +// CHECK: exp prim v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 nodone +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nodone +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 nodone +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nodone +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 nodone +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 nodone +// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + + +exp mrt0 v0, v0, v0, v0 compr +// CHECK: exp mrt0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 compr +// CHECK: exp mrtz v0, v0, v0, v0 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 compr +// CHECK: exp null v0, v0, v0, v0 compr ; encoding: [0x9f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 compr +// CHECK: exp pos0 v0, v0, v0, v0 compr ; encoding: [0xcf,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 compr +// CHECK: exp param0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x06,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 compr +// CHECK: exp prim v0, v0, v0, v0 compr ; encoding: [0x4f,0x05,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 nocompr +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nocompr +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 nocompr +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nocompr +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 nocompr +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 nocompr +// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + + +exp mrt0 v0, v0, v0, v0 vm +// CHECK: exp mrt0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 vm +// CHECK: exp mrtz v0, v0, v0, v0 vm ; encoding: [0x8f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 vm +// CHECK: exp null v0, v0, v0, v0 vm ; encoding: [0x9f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 vm +// CHECK: exp pos0 v0, v0, v0, v0 vm ; encoding: [0xcf,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 vm +// CHECK: exp param0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x12,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 vm +// CHECK: exp prim v0, v0, v0, v0 vm ; encoding: [0x4f,0x11,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 novm +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 novm +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 novm +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 novm +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 novm +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 novm +// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx1150_unsupported.s b/llvm/test/MC/AMDGPU/gfx1150_unsupported.s new file mode 100644 index 0000000000000..8ee4131975d32 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1150_unsupported.s @@ -0,0 +1,56 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1150 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1150 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s + +v_cvt_f32_bf8 v1, 3 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_f32_bf8_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_f32_bf8_e64 v5, v1 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_f32_bf8_sdwa v5, v1 src0_sel:BYTE_0 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_f32_fp8 v1, 3 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_f32_fp8_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_f32_fp8_e64 v5, v1 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_f32_fp8_sdwa v5, v1 src0_sel:BYTE_0 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_pk_bf8_f32 v1, -v2, |v3| +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_pk_f32_bf8 v[0:1], v3 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_pk_f32_bf8_dpp v[10:11], v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_pk_f32_bf8_sdwa v[10:11], v1 src0_sel:WORD_0 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_pk_f32_fp8 v[0:1], v3 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_pk_f32_fp8_dpp v[10:11], v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_pk_f32_fp8_sdwa v[10:11], v1 src0_sel:WORD_0 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_pk_fp8_f32 v1, -v2, |v3| +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_sr_bf8_f32 v1, -|s2|, v3 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +v_cvt_sr_fp8_f32 v1, -|s2|, v3 +// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop1-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1-fake16.s new file mode 100644 index 0000000000000..575a819aadd83 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1-fake16.s @@ -0,0 +1,47 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --strict-whitespace --check-prefixes=GFX1170 %s + +v_cvt_f32_bf8_e32 v1, s3 +// GFX1170: v_cvt_f32_bf8_e32 v1, s3 ; encoding: [0x03,0xda,0x02,0x7e] + +v_cvt_f32_bf8_e32 v1, 3 +// GFX1170: v_cvt_f32_bf8_e32 v1, 3 ; encoding: [0x83,0xda,0x02,0x7e] + +v_cvt_f32_bf8_e32 v1, v3 +// GFX1170: v_cvt_f32_bf8_e32 v1, v3 ; encoding: [0x03,0xdb,0x02,0x7e] + +v_cvt_f32_fp8_e32 v1, s3 +// GFX1170: v_cvt_f32_fp8_e32 v1, s3 ; encoding: [0x03,0xd8,0x02,0x7e] + +v_cvt_f32_fp8_e32 v1, 3 +// GFX1170: v_cvt_f32_fp8_e32 v1, 3 ; encoding: [0x83,0xd8,0x02,0x7e] + +v_cvt_f32_fp8_e32 v1, v3 +// GFX1170: v_cvt_f32_fp8_e32 v1, v3 ; encoding: [0x03,0xd9,0x02,0x7e] + +v_cvt_pk_f32_bf8_e32 v[2:3], s3 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[2:3], s3 ; encoding: [0x03,0xde,0x04,0x7e] + +v_cvt_pk_f32_bf8_e32 v[3:4], s5 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[3:4], s5 ; encoding: [0x05,0xde,0x06,0x7e] + +v_cvt_pk_f32_bf8_e32 v[2:3], 3 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[2:3], 3 ; encoding: [0x83,0xde,0x04,0x7e] + +v_cvt_pk_f32_bf8_e32 v[3:4], 3 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[3:4], 3 ; encoding: [0x83,0xde,0x06,0x7e] + +v_cvt_pk_f32_bf8_e32 v[2:3], v3 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[2:3], v3 ; encoding: [0x03,0xdf,0x04,0x7e] + +v_cvt_pk_f32_bf8_e32 v[3:4], v3 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[3:4], v3 ; encoding: [0x03,0xdf,0x06,0x7e] + +v_cvt_pk_f32_fp8_e32 v[2:3], s3 +// GFX1170: v_cvt_pk_f32_fp8_e32 v[2:3], s3 ; encoding: [0x03,0xdc,0x04,0x7e] + +v_cvt_pk_f32_fp8_e32 v[2:3], 3 +// GFX1170: v_cvt_pk_f32_fp8_e32 v[2:3], 3 ; encoding: [0x83,0xdc,0x04,0x7e] + +v_cvt_pk_f32_fp8_e32 v[2:3], v3 +// GFX1170: v_cvt_pk_f32_fp8_e32 v[2:3], v3 ; encoding: [0x03,0xdd,0x04,0x7e] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1.s new file mode 100644 index 0000000000000..38a0095d6a7e3 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1.s @@ -0,0 +1,54 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding -comment-column=0 %s | FileCheck --strict-whitespace --check-prefixes=GFX1170 %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | sed -n 's#.*\(\[0x[0-9a-fx,]\{1,\}\]\)#\1#p' | llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+wavefrontsize32,+real-true16 -disassemble -show-encoding -comment-column=0 | FileCheck --strict-whitespace --check-prefixes=GFX1170 %s + +v_cvt_f32_bf8_e32 v1, s3 +// GFX1170: v_cvt_f32_bf8_e32 v1, s3 ; encoding: [0x03,0xda,0x02,0x7e] + +v_cvt_f32_bf8_e32 v1, 3 +// GFX1170: v_cvt_f32_bf8_e32 v1, 3 ; encoding: [0x83,0xda,0x02,0x7e] + +v_cvt_f32_bf8_e32 v1, v3 +// GFX1170: v_cvt_f32_bf8_e32 v1, v3 ; encoding: [0x03,0xdb,0x02,0x7e] + +v_cvt_f32_fp8_e32 v1, s3 +// GFX1170: v_cvt_f32_fp8_e32 v1, s3 ; encoding: [0x03,0xd8,0x02,0x7e] + +v_cvt_f32_fp8_e32 v1, 3 +// GFX1170: v_cvt_f32_fp8_e32 v1, 3 ; encoding: [0x83,0xd8,0x02,0x7e] + +v_cvt_f32_fp8_e32 v1, v3 +// GFX1170: v_cvt_f32_fp8_e32 v1, v3 ; encoding: [0x03,0xd9,0x02,0x7e] + +v_cvt_pk_f32_bf8_e32 v[2:3], s3 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[2:3], s3 ; encoding: [0x03,0xde,0x04,0x7e] + +v_cvt_pk_f32_bf8_e32 v[3:4], s5 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[3:4], s5 ; encoding: [0x05,0xde,0x06,0x7e] + +v_cvt_pk_f32_bf8_e32 v[2:3], 3 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[2:3], 3 ; encoding: [0x83,0xde,0x04,0x7e] + +v_cvt_pk_f32_bf8_e32 v[3:4], 3 +// GFX1170: v_cvt_pk_f32_bf8_e32 v[3:4], 3 ; encoding: [0x83,0xde,0x06,0x7e] + +v_cvt_pk_f32_bf8_e32 v[2:3], v3.l +// GFX1170: v_cvt_pk_f32_bf8_e32 v[2:3], v3.l ; encoding: [0x03,0xdf,0x04,0x7e] + +v_cvt_pk_f32_bf8_e32 v[3:4], v3.l +// GFX1170: v_cvt_pk_f32_bf8_e32 v[3:4], v3.l ; encoding: [0x03,0xdf,0x06,0x7e] + +v_cvt_pk_f32_bf8_e32 v[3:4], v3.h +// GFX1170: v_cvt_pk_f32_bf8_e32 v[3:4], v3.h ; encoding: [0x83,0xdf,0x06,0x7e] + +v_cvt_pk_f32_fp8_e32 v[2:3], s3 +// GFX1170: v_cvt_pk_f32_fp8_e32 v[2:3], s3 ; encoding: [0x03,0xdc,0x04,0x7e] + +v_cvt_pk_f32_fp8_e32 v[2:3], 3 +// GFX1170: v_cvt_pk_f32_fp8_e32 v[2:3], 3 ; encoding: [0x83,0xdc,0x04,0x7e] + +v_cvt_pk_f32_fp8_e32 v[2:3], v3.l +// GFX1170: v_cvt_pk_f32_fp8_e32 v[2:3], v3.l ; encoding: [0x03,0xdd,0x04,0x7e] + +v_cvt_pk_f32_fp8_e32 v[2:3], v3.h +// GFX1170: v_cvt_pk_f32_fp8_e32 v[2:3], v3.h ; encoding: [0x83,0xdd,0x04,0x7e] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16-fake16.s new file mode 100644 index 0000000000000..7ac418ca7d60a --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16-fake16.s @@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +v_cvt_f32_fp8 v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc +// GFX1170: v_cvt_f32_fp8_dpp v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc ; encoding: [0xfa,0xd8,0x02,0x7e,0x03,0xe4,0x00,0xac] + +v_cvt_f32_fp8 v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe +// GFX1170: v_cvt_f32_fp8_dpp v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe ; encoding: [0xfa,0xd8,0x02,0x7e,0x03,0x1b,0x00,0x2e] + +v_cvt_f32_bf8 v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc +// GFX1170: v_cvt_f32_bf8_dpp v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc ; encoding: [0xfa,0xda,0x02,0x7e,0x03,0xe4,0x00,0xac] + +v_cvt_f32_bf8 v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe +// GFX1170: v_cvt_f32_bf8_dpp v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe ; encoding: [0xfa,0xda,0x02,0x7e,0x03,0x1b,0x00,0x2e] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16.s new file mode 100644 index 0000000000000..9e5d75569e232 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16.s @@ -0,0 +1,16 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +// this file will be converted to true16 format when more true16 instructions are supported + +v_cvt_f32_fp8 v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc +// GFX1170: v_cvt_f32_fp8_dpp v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc ; encoding: [0xfa,0xd8,0x02,0x7e,0x03,0xe4,0x00,0xac] + +v_cvt_f32_fp8 v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe +// GFX1170: v_cvt_f32_fp8_dpp v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe ; encoding: [0xfa,0xd8,0x02,0x7e,0x03,0x1b,0x00,0x2e] + +v_cvt_f32_bf8 v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc +// GFX1170: v_cvt_f32_bf8_dpp v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc ; encoding: [0xfa,0xda,0x02,0x7e,0x03,0xe4,0x00,0xac] + +v_cvt_f32_bf8 v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe +// GFX1170: v_cvt_f32_bf8_dpp v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe ; encoding: [0xfa,0xda,0x02,0x7e,0x03,0x1b,0x00,0x2e] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8-fake16.s new file mode 100644 index 0000000000000..3acbfb5cfe4b3 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8-fake16.s @@ -0,0 +1,14 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +v_cvt_f32_fp8 v5, v1 dpp8:[0,1,2,3,4,5,6,7] +// GFX1170: v_cvt_f32_fp8_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0xd8,0x0a,0x7e,0x01,0x88,0xc6,0xfa] + +v_cvt_f32_fp8 v1, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd8,0x02,0x7e,0x03,0x77,0x39,0x05] + +v_cvt_f32_bf8 v5, v1 dpp8:[0,1,2,3,4,5,6,7] +// GFX1170: v_cvt_f32_bf8_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0xda,0x0a,0x7e,0x01,0x88,0xc6,0xfa] + +v_cvt_f32_bf8 v1, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xda,0x02,0x7e,0x03,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8.s new file mode 100644 index 0000000000000..cde5db3f1eea5 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8.s @@ -0,0 +1,16 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +// this file will be converted to true16 format when more true16 instructions are supported + +v_cvt_f32_fp8 v5, v1 dpp8:[0,1,2,3,4,5,6,7] +// GFX1170: v_cvt_f32_fp8_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0xd8,0x0a,0x7e,0x01,0x88,0xc6,0xfa] + +v_cvt_f32_fp8 v1, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd8,0x02,0x7e,0x03,0x77,0x39,0x05] + +v_cvt_f32_bf8 v5, v1 dpp8:[0,1,2,3,4,5,6,7] +// GFX1170: v_cvt_f32_bf8_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0xda,0x0a,0x7e,0x01,0x88,0xc6,0xfa] + +v_cvt_f32_bf8 v1, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xda,0x02,0x7e,0x03,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3-fake16.s new file mode 100644 index 0000000000000..7ede1695705df --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3-fake16.s @@ -0,0 +1,62 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +v_cvt_pk_fp8_f32 v1, v2, v3 +// GFX1170: v_cvt_pk_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x69,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_pk_fp8_f32 v1, -v2, |v3| +// GFX1170: v_cvt_pk_fp8_f32 v1, -v2, |v3| ; encoding: [0x01,0x02,0x69,0xd7,0x02,0x07,0x02,0x22] + +v_cvt_pk_fp8_f32 v1, s2, 3 +// GFX1170: v_cvt_pk_fp8_f32 v1, s2, 3 ; encoding: [0x01,0x00,0x69,0xd7,0x02,0x06,0x01,0x02] + +v_cvt_pk_bf8_f32 v1, v2, v3 +// GFX1170: v_cvt_pk_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6a,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_pk_bf8_f32 v1, -v2, |v3| +// GFX1170: v_cvt_pk_bf8_f32 v1, -v2, |v3| ; encoding: [0x01,0x02,0x6a,0xd7,0x02,0x07,0x02,0x22] + +v_cvt_pk_bf8_f32 v1, s2, 3 +// GFX1170: v_cvt_pk_bf8_f32 v1, s2, 3 ; encoding: [0x01,0x00,0x6a,0xd7,0x02,0x06,0x01,0x02] + +v_cvt_sr_fp8_f32 v1, v2, v3 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_fp8_f32 v10, s2, v5 +// GFX1170: v_cvt_sr_fp8_f32 v10, s2, v5 ; encoding: [0x0a,0x00,0x6b,0xd7,0x02,0x0a,0x02,0x02] + +v_cvt_sr_fp8_f32 v5, -|v255|, v4 +// GFX1170: v_cvt_sr_fp8_f32 v5, -|v255|, v4 ; encoding: [0x05,0x01,0x6b,0xd7,0xff,0x09,0x02,0x22] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v1, v2, v3 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v10, s2, v5 +// GFX1170: v_cvt_sr_bf8_f32 v10, s2, v5 ; encoding: [0x0a,0x00,0x6c,0xd7,0x02,0x0a,0x02,0x02] + +v_cvt_sr_bf8_f32 v5, -|v255|, v4 +// GFX1170: v_cvt_sr_bf8_f32 v5, -|v255|, v4 ; encoding: [0x05,0x01,0x6c,0xd7,0xff,0x09,0x02,0x22] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6c,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6c,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6c,0xd7,0x02,0x07,0x02,0x02] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3.s new file mode 100644 index 0000000000000..2ebbc7779abce --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3.s @@ -0,0 +1,62 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +v_cvt_pk_fp8_f32 v1, v2, v3 +// GFX1170: v_cvt_pk_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x69,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_pk_fp8_f32 v1, -v2, |v3| +// GFX1170: v_cvt_pk_fp8_f32 v1, -v2, |v3| ; encoding: [0x01,0x02,0x69,0xd7,0x02,0x07,0x02,0x22] + +v_cvt_pk_fp8_f32 v1, s2, 3 +// GFX1170: v_cvt_pk_fp8_f32 v1, s2, 3 ; encoding: [0x01,0x00,0x69,0xd7,0x02,0x06,0x01,0x02] + +v_cvt_pk_bf8_f32 v1, v2, v3 +// GFX1170: v_cvt_pk_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6a,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_pk_bf8_f32 v1, -v2, |v3| +// GFX1170: v_cvt_pk_bf8_f32 v1, -v2, |v3| ; encoding: [0x01,0x02,0x6a,0xd7,0x02,0x07,0x02,0x22] + +v_cvt_pk_bf8_f32 v1, s2, 3 +// GFX1170: v_cvt_pk_bf8_f32 v1, s2, 3 ; encoding: [0x01,0x00,0x6a,0xd7,0x02,0x06,0x01,0x02] + +v_cvt_sr_fp8_f32 v1, v2, v3 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_fp8_f32 v10, s2, v5 +// GFX1170: v_cvt_sr_fp8_f32 v10, s2, v5 ; encoding: [0x0a,0x00,0x6b,0xd7,0x02,0x0a,0x02,0x02] + +v_cvt_sr_fp8_f32 v5, -|v255|, v4 +// GFX1170: v_cvt_sr_fp8_f32 v5, -|v255|, v4 ; encoding: [0x05,0x01,0x6b,0xd7,0xff,0x09,0x02,0x22] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 +// GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6b,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v1, v2, v3 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v10, s2, v5 +// GFX1170: v_cvt_sr_bf8_f32 v10, s2, v5 ; encoding: [0x0a,0x00,0x6c,0xd7,0x02,0x0a,0x02,0x02] + +v_cvt_sr_bf8_f32 v5, -|v255|, v4 +// GFX1170: v_cvt_sr_bf8_f32 v5, -|v255|, v4 ; encoding: [0x05,0x01,0x6c,0xd7,0xff,0x09,0x02,0x22] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6c,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6c,0xd7,0x02,0x07,0x02,0x02] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 +// GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6c,0xd7,0x02,0x07,0x02,0x02] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16-fake16.s new file mode 100644 index 0000000000000..bd8a99c2b6042 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16-fake16.s @@ -0,0 +1,134 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +v_cvt_pk_bf8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +v_cvt_pk_fp8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +v_cvt_sr_bf8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +v_cvt_sr_fp8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16.s new file mode 100644 index 0000000000000..f34a89f16ca6f --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16.s @@ -0,0 +1,134 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +v_cvt_pk_bf8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +v_cvt_pk_fp8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +v_cvt_sr_bf8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +v_cvt_sr_fp8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8-fake16.s new file mode 100644 index 0000000000000..1de4fa6bdc903 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8-fake16.s @@ -0,0 +1,74 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +v_cvt_pk_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,2,3,0,1] +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,2,3,0,1] ; encoding: [0x05,0x00,0x69,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0xa9,0x21] + +v_cvt_pk_fp8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x69,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +v_cvt_pk_fp8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x69,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_cvt_pk_fp8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x69,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_cvt_pk_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_pk_bf8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6a,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +v_cvt_pk_bf8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x6a,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_cvt_pk_bf8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x6a,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_cvt_sr_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x01,0x6b,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x01,0x6c,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8.s new file mode 100644 index 0000000000000..178c35807dc59 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8.s @@ -0,0 +1,74 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX1170 %s + +v_cvt_pk_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,2,3,0,1] +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,2,3,0,1] ; encoding: [0x05,0x00,0x69,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0xa9,0x21] + +v_cvt_pk_fp8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x69,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +v_cvt_pk_fp8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x69,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_cvt_pk_fp8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] +// GFX1170: v_cvt_pk_fp8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x69,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_cvt_pk_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_pk_bf8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6a,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +v_cvt_pk_bf8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x6a,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_cvt_pk_bf8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] +// GFX1170: v_cvt_pk_bf8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x6a,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_cvt_sr_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x01,0x6b,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x01,0x6c,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_err.s new file mode 100644 index 0000000000000..ca20962331397 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_err.s @@ -0,0 +1,5 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1170 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX1170 --strict-whitespace --implicit-check-not=error %s + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4 +// GFX1170: :[[@LINE-1]]:29: error: invalid byte_sel value. diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1-fake16.s new file mode 100644 index 0000000000000..4d07beec2b597 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1-fake16.s @@ -0,0 +1,140 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --check-prefix=GFX1170 %s + +v_cvt_f32_bf8_e64 v1, s3 +// GFX1170: v_cvt_f32_bf8_e64 v1, s3 ; encoding: [0x01,0x00,0xed,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, s3 byte_sel:1 +// GFX1170: v_cvt_f32_bf8_e64 v1, s3 byte_sel:1 ; encoding: [0x01,0x10,0xed,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, s3 byte_sel:2 +// GFX1170: v_cvt_f32_bf8_e64 v1, s3 byte_sel:2 ; encoding: [0x01,0x08,0xed,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, s3 byte_sel:3 +// GFX1170: v_cvt_f32_bf8_e64 v1, s3 byte_sel:3 ; encoding: [0x01,0x18,0xed,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, 3 +// GFX1170: v_cvt_f32_bf8_e64 v1, 3 ; encoding: [0x01,0x00,0xed,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, 3 byte_sel:1 +// GFX1170: v_cvt_f32_bf8_e64 v1, 3 byte_sel:1 ; encoding: [0x01,0x10,0xed,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, 3 byte_sel:2 +// GFX1170: v_cvt_f32_bf8_e64 v1, 3 byte_sel:2 ; encoding: [0x01,0x08,0xed,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, 3 byte_sel:3 +// GFX1170: v_cvt_f32_bf8_e64 v1, 3 byte_sel:3 ; encoding: [0x01,0x18,0xed,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, v3 +// GFX1170: v_cvt_f32_bf8_e64 v1, v3 ; encoding: [0x01,0x00,0xed,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, v3 byte_sel:1 +// GFX1170: v_cvt_f32_bf8_e64 v1, v3 byte_sel:1 ; encoding: [0x01,0x10,0xed,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, v3 byte_sel:2 +// GFX1170: v_cvt_f32_bf8_e64 v1, v3 byte_sel:2 ; encoding: [0x01,0x08,0xed,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, v3 byte_sel:3 +// GFX1170: v_cvt_f32_bf8_e64 v1, v3 byte_sel:3 ; encoding: [0x01,0x18,0xed,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, s3 +// GFX1170: v_cvt_f32_fp8_e64 v1, s3 ; encoding: [0x01,0x00,0xec,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, s3 byte_sel:1 +// GFX1170: v_cvt_f32_fp8_e64 v1, s3 byte_sel:1 ; encoding: [0x01,0x10,0xec,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, s3 byte_sel:2 +// GFX1170: v_cvt_f32_fp8_e64 v1, s3 byte_sel:2 ; encoding: [0x01,0x08,0xec,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, s3 byte_sel:3 +// GFX1170: v_cvt_f32_fp8_e64 v1, s3 byte_sel:3 ; encoding: [0x01,0x18,0xec,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, 3 +// GFX1170: v_cvt_f32_fp8_e64 v1, 3 ; encoding: [0x01,0x00,0xec,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, 3 byte_sel:1 +// GFX1170: v_cvt_f32_fp8_e64 v1, 3 byte_sel:1 ; encoding: [0x01,0x10,0xec,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, 3 byte_sel:2 +// GFX1170: v_cvt_f32_fp8_e64 v1, 3 byte_sel:2 ; encoding: [0x01,0x08,0xec,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, 3 byte_sel:3 +// GFX1170: v_cvt_f32_fp8_e64 v1, 3 byte_sel:3 ; encoding: [0x01,0x18,0xec,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, v3 +// GFX1170: v_cvt_f32_fp8_e64 v1, v3 ; encoding: [0x01,0x00,0xec,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, v3 byte_sel:1 +// GFX1170: v_cvt_f32_fp8_e64 v1, v3 byte_sel:1 ; encoding: [0x01,0x10,0xec,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, v3 byte_sel:2 +// GFX1170: v_cvt_f32_fp8_e64 v1, v3 byte_sel:2 ; encoding: [0x01,0x08,0xec,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, v3 byte_sel:3 +// GFX1170: v_cvt_f32_fp8_e64 v1, v3 byte_sel:3 ; encoding: [0x01,0x18,0xec,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], s3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], s3 ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], s3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], s3 op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], 3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], 3 ; encoding: [0x02,0x00,0xef,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], 3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], 3 op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], v3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], v3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], v3 op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], s3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], s3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], s3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], s3 op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], 3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], 3 ; encoding: [0x02,0x00,0xee,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], 3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], 3 op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], v3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], v3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], v3 op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], s3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], s3 ; encoding: [0x03,0x00,0xef,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], s3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], s3 op_sel:[1,0] ; encoding: [0x03,0x08,0xef,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], 3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], 3 op_sel:[1,0] ; encoding: [0x03,0x08,0xef,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], v3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], v3 ; encoding: [0x03,0x00,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], v3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], v3 op_sel:[1,0] ; encoding: [0x03,0x08,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], s3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], s3 ; encoding: [0x03,0x00,0xee,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], 3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], 3 ; encoding: [0x03,0x00,0xee,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], 3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], 3 op_sel:[1,0] ; encoding: [0x03,0x08,0xee,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], v3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], v3 ; encoding: [0x03,0x00,0xee,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], v3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], v3 op_sel:[1,0] ; encoding: [0x03,0x08,0xee,0xd5,0x03,0x01,0x01,0x02] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1.s new file mode 100644 index 0000000000000..14b2a17c06c8c --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1.s @@ -0,0 +1,152 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX1170 %s + +v_cvt_f32_bf8_e64 v1, s3 +// GFX1170: v_cvt_f32_bf8_e64 v1, s3 ; encoding: [0x01,0x00,0xed,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, s3 byte_sel:1 +// GFX1170: v_cvt_f32_bf8_e64 v1, s3 byte_sel:1 ; encoding: [0x01,0x10,0xed,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, s3 byte_sel:2 +// GFX1170: v_cvt_f32_bf8_e64 v1, s3 byte_sel:2 ; encoding: [0x01,0x08,0xed,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, s3 byte_sel:3 +// GFX1170: v_cvt_f32_bf8_e64 v1, s3 byte_sel:3 ; encoding: [0x01,0x18,0xed,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, 3 +// GFX1170: v_cvt_f32_bf8_e64 v1, 3 ; encoding: [0x01,0x00,0xed,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, 3 byte_sel:1 +// GFX1170: v_cvt_f32_bf8_e64 v1, 3 byte_sel:1 ; encoding: [0x01,0x10,0xed,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, 3 byte_sel:2 +// GFX1170: v_cvt_f32_bf8_e64 v1, 3 byte_sel:2 ; encoding: [0x01,0x08,0xed,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, 3 byte_sel:3 +// GFX1170: v_cvt_f32_bf8_e64 v1, 3 byte_sel:3 ; encoding: [0x01,0x18,0xed,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, v3 +// GFX1170: v_cvt_f32_bf8_e64 v1, v3 ; encoding: [0x01,0x00,0xed,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, v3 byte_sel:1 +// GFX1170: v_cvt_f32_bf8_e64 v1, v3 byte_sel:1 ; encoding: [0x01,0x10,0xed,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, v3 byte_sel:2 +// GFX1170: v_cvt_f32_bf8_e64 v1, v3 byte_sel:2 ; encoding: [0x01,0x08,0xed,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_bf8_e64 v1, v3 byte_sel:3 +// GFX1170: v_cvt_f32_bf8_e64 v1, v3 byte_sel:3 ; encoding: [0x01,0x18,0xed,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, s3 +// GFX1170: v_cvt_f32_fp8_e64 v1, s3 ; encoding: [0x01,0x00,0xec,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, s3 byte_sel:1 +// GFX1170: v_cvt_f32_fp8_e64 v1, s3 byte_sel:1 ; encoding: [0x01,0x10,0xec,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, s3 byte_sel:2 +// GFX1170: v_cvt_f32_fp8_e64 v1, s3 byte_sel:2 ; encoding: [0x01,0x08,0xec,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, s3 byte_sel:3 +// GFX1170: v_cvt_f32_fp8_e64 v1, s3 byte_sel:3 ; encoding: [0x01,0x18,0xec,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, 3 +// GFX1170: v_cvt_f32_fp8_e64 v1, 3 ; encoding: [0x01,0x00,0xec,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, 3 byte_sel:1 +// GFX1170: v_cvt_f32_fp8_e64 v1, 3 byte_sel:1 ; encoding: [0x01,0x10,0xec,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, 3 byte_sel:2 +// GFX1170: v_cvt_f32_fp8_e64 v1, 3 byte_sel:2 ; encoding: [0x01,0x08,0xec,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, 3 byte_sel:3 +// GFX1170: v_cvt_f32_fp8_e64 v1, 3 byte_sel:3 ; encoding: [0x01,0x18,0xec,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, v3 +// GFX1170: v_cvt_f32_fp8_e64 v1, v3 ; encoding: [0x01,0x00,0xec,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, v3 byte_sel:1 +// GFX1170: v_cvt_f32_fp8_e64 v1, v3 byte_sel:1 ; encoding: [0x01,0x10,0xec,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, v3 byte_sel:2 +// GFX1170: v_cvt_f32_fp8_e64 v1, v3 byte_sel:2 ; encoding: [0x01,0x08,0xec,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_f32_fp8_e64 v1, v3 byte_sel:3 +// GFX1170: v_cvt_f32_fp8_e64 v1, v3 byte_sel:3 ; encoding: [0x01,0x18,0xec,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], s3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], s3 ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], s3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], s3 op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], 3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], 3 ; encoding: [0x02,0x00,0xef,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], 3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], 3 op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], v3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], v3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], v3 op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], v3.h +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], v3.h op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[2:3], v255.h +// GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], v255.h op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0xff,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], s3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], s3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], s3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], s3 op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], 3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], 3 ; encoding: [0x02,0x00,0xee,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], 3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], 3 op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], v3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[2:3], v3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], v3 op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], s3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], s3 ; encoding: [0x03,0x00,0xef,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], s3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], s3 op_sel:[1,0] ; encoding: [0x03,0x08,0xef,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], 3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], 3 op_sel:[1,0] ; encoding: [0x03,0x08,0xef,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], v3 +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], v3 ; encoding: [0x03,0x00,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_bf8_e64 v[3:4], v3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_bf8_e64 v[3:4], v3 op_sel:[1,0] ; encoding: [0x03,0x08,0xef,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], s3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], s3 ; encoding: [0x03,0x00,0xee,0xd5,0x03,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], 3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], 3 ; encoding: [0x03,0x00,0xee,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], 3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], 3 op_sel:[1,0] ; encoding: [0x03,0x08,0xee,0xd5,0x83,0x00,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], v3 +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], v3 ; encoding: [0x03,0x00,0xee,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], v3 op_sel:[1,0] +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], v3 op_sel:[1,0] ; encoding: [0x03,0x08,0xee,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], v3.h +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], v3.h op_sel:[1,0] ; encoding: [0x03,0x08,0xee,0xd5,0x03,0x01,0x01,0x02] + +v_cvt_pk_f32_fp8_e64 v[3:4], v255.h +// GFX1170: v_cvt_pk_f32_fp8_e64 v[3:4], v255.h op_sel:[1,0] ; encoding: [0x03,0x08,0xee,0xd5,0xff,0x01,0x01,0x02] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16-fake16.s new file mode 100644 index 0000000000000..e93453a2dfdc8 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16-fake16.s @@ -0,0 +1,44 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --check-prefix=GFX1170 %s + +v_cvt_f32_fp8_e64_dpp v5, v1 quad_perm:[3,1,2,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_f32_fp8_e64_dpp v5, v1 quad_perm:[3,1,2,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x05,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x01,0x27,0x00,0x2d] + +v_cvt_f32_fp8_e64_dpp v1, v3 quad_perm:[2,1,0,3] row_mask:0x5 bank_mask:0xe +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v3 quad_perm:[2,1,0,3] row_mask:0x5 bank_mask:0xe ; encoding: [0x01,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x03,0xc6,0x00,0x5e] + +v_cvt_f32_bf8_e64_dpp v5, v1 quad_perm:[0,3,2,1] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_f32_bf8_e64_dpp v5, v1 quad_perm:[0,3,2,1] row_mask:0x2 bank_mask:0xd ; encoding: [0x05,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x01,0x6c,0x00,0x2d] + +v_cvt_f32_bf8_e64_dpp v1, v3 quad_perm:[0,1,3,2] row_mask:0x5 bank_mask:0xe +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v3 quad_perm:[0,1,3,2] row_mask:0x5 bank_mask:0xe ; encoding: [0x01,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x03,0xb4,0x00,0x5e] + +v_cvt_f32_fp8 v1, v2 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd8,0x02,0x7e,0x02,0xe4,0x00,0xff] + +v_cvt_f32_fp8 v1, v2 byte_sel:0 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_fp8 v1, v2 byte_sel:1 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x10,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_fp8 v1, v2 byte_sel:2 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x08,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_fp8 v1, v2 byte_sel:3 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x18,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xda,0x02,0x7e,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 byte_sel:0 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 byte_sel:1 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x10,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 byte_sel:2 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x08,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 byte_sel:3 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x18,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16.s new file mode 100644 index 0000000000000..c24c550381e91 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16.s @@ -0,0 +1,44 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX1170 %s + +v_cvt_f32_fp8_e64_dpp v5, v1 quad_perm:[3,1,2,0] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_f32_fp8_e64_dpp v5, v1 quad_perm:[3,1,2,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x05,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x01,0x27,0x00,0x2d] + +v_cvt_f32_fp8_e64_dpp v1, v3 quad_perm:[2,1,0,3] row_mask:0x5 bank_mask:0xe +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v3 quad_perm:[2,1,0,3] row_mask:0x5 bank_mask:0xe ; encoding: [0x01,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x03,0xc6,0x00,0x5e] + +v_cvt_f32_bf8_e64_dpp v5, v1 quad_perm:[0,3,2,1] row_mask:0x2 bank_mask:0xd +// GFX1170: v_cvt_f32_bf8_e64_dpp v5, v1 quad_perm:[0,3,2,1] row_mask:0x2 bank_mask:0xd ; encoding: [0x05,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x01,0x6c,0x00,0x2d] + +v_cvt_f32_bf8_e64_dpp v1, v3 quad_perm:[0,1,3,2] row_mask:0x5 bank_mask:0xe +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v3 quad_perm:[0,1,3,2] row_mask:0x5 bank_mask:0xe ; encoding: [0x01,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x03,0xb4,0x00,0x5e] + +v_cvt_f32_fp8 v1, v2 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd8,0x02,0x7e,0x02,0xe4,0x00,0xff] + +v_cvt_f32_fp8 v1, v2 byte_sel:0 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_fp8 v1, v2 byte_sel:1 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x10,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_fp8 v1, v2 byte_sel:2 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x08,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_fp8 v1, v2 byte_sel:3 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x18,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xda,0x02,0x7e,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 byte_sel:0 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 byte_sel:1 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x10,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 byte_sel:2 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x08,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +v_cvt_f32_bf8 v1, v2 byte_sel:3 quad_perm:[0,1,2,3] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x18,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8-fake16.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8-fake16.s new file mode 100644 index 0000000000000..b34cfd70efad3 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8-fake16.s @@ -0,0 +1,44 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -show-encoding %s | FileCheck --check-prefix=GFX1170 %s + +v_cvt_f32_fp8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] +// GFX1170: v_cvt_f32_fp8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x05,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x01,0x88,0xc6,0xfa] + +v_cvt_f32_fp8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05] + +v_cvt_f32_bf8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] +// GFX1170: v_cvt_f32_bf8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x05,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x01,0x88,0xc6,0xfa] + +v_cvt_f32_bf8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd8,0x02,0x7e,0x02,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x10,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x08,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x18,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xda,0x02,0x7e,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x10,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x08,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x18,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8.s b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8.s new file mode 100644 index 0000000000000..60c058e4040e6 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8.s @@ -0,0 +1,44 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -show-encoding %s | FileCheck --check-prefix=GFX1170 %s + +v_cvt_f32_fp8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] +// GFX1170: v_cvt_f32_fp8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x05,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x01,0x88,0xc6,0xfa] + +v_cvt_f32_fp8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05] + +v_cvt_f32_bf8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] +// GFX1170: v_cvt_f32_bf8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x05,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x01,0x88,0xc6,0xfa] + +v_cvt_f32_bf8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd8,0x02,0x7e,0x02,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x10,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x08,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_fp8 v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x18,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xda,0x02,0x7e,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x10,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x08,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +v_cvt_f32_bf8 v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x18,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_err.s index f6a6b21bb880f..fe438481dd7b2 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_err.s @@ -155,3 +155,21 @@ s_load_b96 s[20:22], s[2:3], s0 s_buffer_load_b96 s[20:22], s[4:7], s0 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU + +s_wait_event -1 +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid immediate: only 16-bit values are legal + +s_wait_event 65537 +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid immediate: only 16-bit values are legal + +s_wait_event NOT_EVENT +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: expected structured immediate or an absolute expression + +s_wait_event { export_ready: 0 } +// GFX11: :[[@LINE-1]]:16: error: unknown field + +s_wait_event { export_ready: 1 } +// GFX11: :[[@LINE-1]]:16: error: unknown field + +s_wait_event { dont_wait_export_ready: 2 } +// GFX11: :[[@LINE-1]]:40: error: invalid bit value: only 1-bit values are legal diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_exp.s b/llvm/test/MC/AMDGPU/gfx11_asm_exp.s index 57aaa5e6f5e76..fcdac8aed13ab 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_exp.s @@ -1,20 +1,79 @@ -// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --sort --version 6 -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx900 %s -filetype=null 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 %s -filetype=null 2>&1 | FileCheck -check-prefix=PREGFX11 --implicit-check-not=error: %s -// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 --implicit-check-not=error: %s - -exp dual_src_blend0 v4, v3, v2, v1 -// GFX11: exp dual_src_blend0 v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] -// PREGFX11: :[[@LINE-2]]:5: error: exp target is not supported on this GPU - -exp dual_src_blend1 v2, v3, off, off -// GFX11: exp dual_src_blend1 v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] -// PREGFX11: :[[@LINE-2]]:5: error: exp target is not supported on this GPU - -exp mrtz v4, v3, off, off done row_en -// GFX11: exp mrtz v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] -// PREGFX11: :[[@LINE-2]]:32: error: invalid operand for instruction - -exp mrtz v4, v3, v2, v1 row_en -// GFX11: exp mrtz v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] -// PREGFX11: :[[@LINE-2]]:25: error: invalid operand for instruction +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s + +exp mrt0 v0, v0, v0, v0 done +// CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 done +// CHECK: exp mrtz v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 done +// CHECK: exp prim v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 done +// CHECK: exp pos0 v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp dual_src_blend0 v0, v0, v0, v0 done +// CHECK: exp dual_src_blend0 v0, v0, v0, v0 done ; encoding: [0x5f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] + + +exp mrt0 v0, v0, v0, v0 nodone +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nodone +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 nodone +// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nodone +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp dual_src_blend0 v0, v0, v0, v0 nodone +// CHECK: exp dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + + +exp mrt0 v0, v0, v0, v0 row_en +// CHECK: exp mrt0 v0, v0, v0, v0 row_en ; encoding: [0x0f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 row_en +// CHECK: exp mrtz v0, v0, v0, v0 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 row_en +// CHECK: exp prim v0, v0, v0, v0 row_en ; encoding: [0x4f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 row_en +// CHECK: exp pos0 v0, v0, v0, v0 row_en ; encoding: [0xcf,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp dual_src_blend0 v0, v0, v0, v0 row_en +// CHECK: exp dual_src_blend0 v0, v0, v0, v0 row_en ; encoding: [0x5f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 norow_en +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 norow_en +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 norow_en +// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 norow_en +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp dual_src_blend0 v0, v0, v0, v0 norow_en +// CHECK: exp dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + + +exp mrt0 v0, v0, v0, v0 nodone norow_en +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nodone norow_en +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp prim v0, v0, v0, v0 nodone norow_en +// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nodone norow_en +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +exp dual_src_blend0 v0, v0, v0, v0 nodone norow_en +// CHECK: exp dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s index c3b97e8de6c45..051ac2efca464 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_sopp.s @@ -425,11 +425,29 @@ s_ttracedata_imm 0xc1d1 s_set_inst_prefetch_distance 0xc1d1 // GFX11: s_set_inst_prefetch_distance 0xc1d1 ; encoding: [0xd1,0xc1,0x84,0xbf] +s_wait_event 0 +// GFX11: s_wait_event { dont_wait_export_ready: 0 } ; encoding: [0x00,0x00,0x8b,0xbf] + +s_wait_event { dont_wait_export_ready: 0 } ; encoding: [0x00,0x00,0x8b,0xbf]a +// GFX11: s_wait_event { dont_wait_export_ready: 0 } ; encoding: [0x00,0x00,0x8b,0xbf] + +s_wait_event 1 +// GFX11: s_wait_event { dont_wait_export_ready: 1 } ; encoding: [0x01,0x00,0x8b,0xbf] + +s_wait_event { dont_wait_export_ready: 1 } +// GFX11: s_wait_event { dont_wait_export_ready: 1 } ; encoding: [0x01,0x00,0x8b,0xbf] + +s_wait_event 2 +// GFX11: s_wait_event 0x2 ; encoding: [0x02,0x00,0x8b,0xbf] + s_wait_event 0x3141 // GFX11: s_wait_event 0x3141 ; encoding: [0x41,0x31,0x8b,0xbf] s_wait_event 0xc1d1 // GFX11: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf] +s_wait_event 0xffff +// GFX11: s_wait_event 0xffff ; encoding: [0xff,0xff,0x8b,0xbf] + s_endpgm_ordered_ps_done // GFX11: s_endpgm_ordered_ps_done ; encoding: [0x00,0x00,0xb2,0xbf] diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s index 8a98f5b549f6e..78bb59af75c1d 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s @@ -61,8 +61,12 @@ s_monitor_sleep 0 // GFX1250: s_monitor_sleep 0 ; encoding: [0x00,0x00,0x84,0xbf] // GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU -s_sendmsg sendmsg(MSG_SAVEWAVE_HAS_TDM) -// GFX1250: s_sendmsg sendmsg(MSG_SAVEWAVE_HAS_TDM) ; encoding: [0x0a,0x00,0xb6,0xbf] +s_sendmsg_rtn_b32 s1, sendmsg(MSG_RTN_SAVE_WAVE_HAS_TDM) ; encoding: [0x0a,0x00,0xb6,0xbf] +// GFX12: s_sendmsg_rtn_b32 s1, sendmsg(MSG_RTN_SAVE_WAVE_HAS_TDM) ; encoding: [0x98,0x4c,0x81,0xbe] +// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU + +s_sendmsg sendmsg(MSG_RTN_SAVE_WAVE_HAS_TDM) ; encoding: [0x0a,0x00,0xb6,0xbf] +// GFX1250: s_sendmsg sendmsg(MSG_RTN_SAVE_WAVE_HAS_TDM) ; encoding: [0x98,0x00,0xb6,0xbf] // GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: specified message id is not supported on this GPU s_barrier_wait -3 diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_exp.s b/llvm/test/MC/AMDGPU/gfx12_asm_exp.s index e93696f5ad082..7f3a78ecbef15 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_exp.s @@ -60,3 +60,83 @@ export pos3 v4, v3, v2, v1 export pos3 v4, v3, v2, v1 done // GFX12: export pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] + +// Optional operands: done and row_en + +export mrt0 v0, v0, v0, v0 done +// GFX12: export mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrtz v0, v0, v0, v0 done +// GFX12: export mrtz v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +export prim v0, v0, v0, v0 done +// GFX12: export prim v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] + +export pos0 v0, v0, v0, v0 done +// GFX12: export pos0 v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 done +// GFX12: export dual_src_blend0 v0, v0, v0, v0 done ; encoding: [0x5f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] + + +export mrt0 v0, v0, v0, v0 nodone +// GFX12: export mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrtz v0, v0, v0, v0 nodone +// GFX12: export mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export prim v0, v0, v0, v0 nodone +// GFX12: export prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +export pos0 v0, v0, v0, v0 nodone +// GFX12: export pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 nodone +// GFX12: export dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + + +export mrt0 v0, v0, v0, v0 row_en +// GFX12: export mrt0 v0, v0, v0, v0 row_en ; encoding: [0x0f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrtz v0, v0, v0, v0 row_en +// GFX12: export mrtz v0, v0, v0, v0 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +export prim v0, v0, v0, v0 row_en +// GFX12: export prim v0, v0, v0, v0 row_en ; encoding: [0x4f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] + +export pos0 v0, v0, v0, v0 row_en +// GFX12: export pos0 v0, v0, v0, v0 row_en ; encoding: [0xcf,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 row_en +// GFX12: export dual_src_blend0 v0, v0, v0, v0 row_en ; encoding: [0x5f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrt0 v0, v0, v0, v0 norow_en +// GFX12: export mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrtz v0, v0, v0, v0 norow_en +// GFX12: export mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export prim v0, v0, v0, v0 norow_en +// GFX12: export prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +export pos0 v0, v0, v0, v0 norow_en +// GFX12: export pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 norow_en +// GFX12: export dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + + +export mrt0 v0, v0, v0, v0 nodone norow_en +// GFX12: export mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrtz v0, v0, v0, v0 nodone norow_en +// GFX12: export mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export prim v0, v0, v0, v0 nodone norow_en +// GFX12: export prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +export pos0 v0, v0, v0, v0 nodone norow_en +// GFX12: export pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 nodone norow_en +// GFX12: export dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s index a1c2e1334af66..b314b8ce8ad48 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s @@ -388,3 +388,30 @@ s_waitcnt vmcnt(9) s_wakeup // GFX12: s_wakeup ; encoding: [0x00,0x00,0xb4,0xbf] + +s_wait_event 0 +// GFX1200: s_wait_event { export_ready: 0 } ; encoding: [0x00,0x00,0x8b,0xbf] + +s_wait_event 1 +// GFX1200: s_wait_event 0x1 ; encoding: [0x01,0x00,0x8b,0xbf] + +s_wait_event 2 +// GFX1200: s_wait_event { export_ready: 1 } ; encoding: [0x02,0x00,0x8b,0xbf] + +s_wait_event 0x3141 +// GFX1200: s_wait_event 0x3141 ; encoding: [0x41,0x31,0x8b,0xbf] + +s_wait_event 0xc1d1 +// GFX1200: s_wait_event 0xc1d1 ; encoding: [0xd1,0xc1,0x8b,0xbf] + +s_wait_event 0xffff +// GFX1200: s_wait_event 0xffff ; encoding: [0xff,0xff,0x8b,0xbf] + +s_wait_event { export_ready: 0 } +// GFX1200: s_wait_event { export_ready: 0 } ; encoding: [0x00,0x00,0x8b,0xbf] + +s_wait_event { export_ready: 1 } +// GFX1200: s_wait_event 0x1 ; encoding: [0x01,0x00,0x8b,0xbf] + +s_wait_event { } +// GFX1200: s_wait_event { export_ready: 0 } ; encoding: [0x00,0x00,0x8b,0xbf] diff --git a/llvm/test/MC/AMDGPU/gfx12_err.s b/llvm/test/MC/AMDGPU/gfx12_err.s index 8cd081e0273f3..036f212f7e09a 100644 --- a/llvm/test/MC/AMDGPU/gfx12_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_err.s @@ -642,3 +642,33 @@ s_buffer_load_u16 s5, s[4:7], s0 offset:-1 s_buffer_prefetch_data s[20:23], -1, s10, 7 // GFX12-ERR: [[@LINE-1]]:{{[0-9]+}}: error: expected a 23-bit unsigned offset for buffer ops + +s_wait_event NOT_EVENT +// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: expected structured immediate or an absolute expression + +s_wait_event DONT_WAIT_EXPORT_READY +// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: expected structured immediate or an absolute expression + +s_wait_event { export_ready: 2 } +// GFX12-ERR: :[[@LINE-1]]:30: error: invalid bit value: only 1-bit values are legal + +s_wait_event { export_ready: -1 } +// GFX12-ERR: :[[@LINE-1]]:30: error: invalid bit value: only 1-bit values are legal + +s_wait_event { export_ready 1 } +// GFX12-ERR: :[[@LINE-1]]:29: error: colon expected + +s_wait_event { export_ready=1 } +// GFX12-ERR: :[[@LINE-1]]:28: error: colon expected + +s_wait_event {0} +// GFX12-ERR: :[[@LINE-1]]:15: error: field name expected + +s_wait_event {1} +// GFX12-ERR: :[[@LINE-1]]:15: error: field name expected + +s_wait_event { dont_wait_export_ready: 1 } +// GFX12-ERR: :[[@LINE-1]]:16: error: unknown field + +s_wait_event { dont_wait_export_ready: 0 } +// GFX12-ERR: :[[@LINE-1]]:16: error: unknown field diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx13_asm_sopc.s new file mode 100644 index 0000000000000..45c683964d90c --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx13_asm_sopc.s @@ -0,0 +1,2360 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | FileCheck -check-prefixes=GFX13,GFX13-ASM %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1310 -disassemble -show-encoding | FileCheck -check-prefixes=GFX13,GFX13-DIS %s + +s_cmp_eq_i32 s0, s0 +// GFX13: s_cmp_eq_i32 s0, s0 ; encoding: [0x00,0x00,0x00,0xbf] + +s_cmp_eq_i32 s105, s0 +// GFX13: s_cmp_eq_i32 s105, s0 ; encoding: [0x69,0x00,0x00,0xbf] + +s_cmp_eq_i32 vcc_lo, s0 +// GFX13: s_cmp_eq_i32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x00,0xbf] + +s_cmp_eq_i32 exec_lo, s0 +// GFX13: s_cmp_eq_i32 exec_lo, s0 ; encoding: [0x7e,0x00,0x00,0xbf] + +s_cmp_eq_i32 m0, s0 +// GFX13: s_cmp_eq_i32 m0, s0 ; encoding: [0x7d,0x00,0x00,0xbf] + +s_cmp_eq_i32 null, s0 +// GFX13: s_cmp_eq_i32 null, s0 ; encoding: [0x7c,0x00,0x00,0xbf] + +s_cmp_eq_i32 0, s0 +// GFX13: s_cmp_eq_i32 0, s0 ; encoding: [0x80,0x00,0x00,0xbf] + +s_cmp_eq_i32 0.5, s0 +// GFX13: s_cmp_eq_i32 0.5, s0 ; encoding: [0xf0,0x00,0x00,0xbf] + +s_cmp_eq_i32 0x12345678, s0 +// GFX13: s_cmp_eq_i32 0x12345678, s0 ; encoding: [0xff,0x00,0x00,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_eq_i32 s0, s105 +// GFX13: s_cmp_eq_i32 s0, s105 ; encoding: [0x00,0x69,0x00,0xbf] + +s_cmp_eq_i32 s0, vcc_lo +// GFX13: s_cmp_eq_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x00,0xbf] + +s_cmp_eq_i32 s0, exec_lo +// GFX13: s_cmp_eq_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x00,0xbf] + +s_cmp_eq_i32 s0, m0 +// GFX13: s_cmp_eq_i32 s0, m0 ; encoding: [0x00,0x7d,0x00,0xbf] + +s_cmp_eq_i32 s0, null +// GFX13: s_cmp_eq_i32 s0, null ; encoding: [0x00,0x7c,0x00,0xbf] + +s_cmp_eq_i32 s0, 0 +// GFX13: s_cmp_eq_i32 s0, 0 ; encoding: [0x00,0x80,0x00,0xbf] + +s_cmp_eq_i32 s0, 0.5 +// GFX13: s_cmp_eq_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x00,0xbf] + +s_cmp_eq_i32 s0, 0x12345678 +// GFX13: s_cmp_eq_i32 s0, 0x12345678 ; encoding: [0x00,0xff,0x00,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lg_i32 s0, s0 +// GFX13: s_cmp_lg_i32 s0, s0 ; encoding: [0x00,0x00,0x01,0xbf] + +s_cmp_lg_i32 s105, s0 +// GFX13: s_cmp_lg_i32 s105, s0 ; encoding: [0x69,0x00,0x01,0xbf] + +s_cmp_lg_i32 vcc_lo, s0 +// GFX13: s_cmp_lg_i32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x01,0xbf] + +s_cmp_lg_i32 exec_lo, s0 +// GFX13: s_cmp_lg_i32 exec_lo, s0 ; encoding: [0x7e,0x00,0x01,0xbf] + +s_cmp_lg_i32 m0, s0 +// GFX13: s_cmp_lg_i32 m0, s0 ; encoding: [0x7d,0x00,0x01,0xbf] + +s_cmp_lg_i32 null, s0 +// GFX13: s_cmp_lg_i32 null, s0 ; encoding: [0x7c,0x00,0x01,0xbf] + +s_cmp_lg_i32 0, s0 +// GFX13: s_cmp_lg_i32 0, s0 ; encoding: [0x80,0x00,0x01,0xbf] + +s_cmp_lg_i32 0.5, s0 +// GFX13: s_cmp_lg_i32 0.5, s0 ; encoding: [0xf0,0x00,0x01,0xbf] + +s_cmp_lg_i32 0x12345678, s0 +// GFX13: s_cmp_lg_i32 0x12345678, s0 ; encoding: [0xff,0x00,0x01,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lg_i32 s0, s105 +// GFX13: s_cmp_lg_i32 s0, s105 ; encoding: [0x00,0x69,0x01,0xbf] + +s_cmp_lg_i32 s0, vcc_lo +// GFX13: s_cmp_lg_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x01,0xbf] + +s_cmp_lg_i32 s0, exec_lo +// GFX13: s_cmp_lg_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x01,0xbf] + +s_cmp_lg_i32 s0, m0 +// GFX13: s_cmp_lg_i32 s0, m0 ; encoding: [0x00,0x7d,0x01,0xbf] + +s_cmp_lg_i32 s0, null +// GFX13: s_cmp_lg_i32 s0, null ; encoding: [0x00,0x7c,0x01,0xbf] + +s_cmp_lg_i32 s0, 0 +// GFX13: s_cmp_lg_i32 s0, 0 ; encoding: [0x00,0x80,0x01,0xbf] + +s_cmp_lg_i32 s0, 0.5 +// GFX13: s_cmp_lg_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x01,0xbf] + +s_cmp_lg_i32 s0, 0x12345678 +// GFX13: s_cmp_lg_i32 s0, 0x12345678 ; encoding: [0x00,0xff,0x01,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_gt_i32 s0, s0 +// GFX13: s_cmp_gt_i32 s0, s0 ; encoding: [0x00,0x00,0x02,0xbf] + +s_cmp_gt_i32 s105, s0 +// GFX13: s_cmp_gt_i32 s105, s0 ; encoding: [0x69,0x00,0x02,0xbf] + +s_cmp_gt_i32 vcc_lo, s0 +// GFX13: s_cmp_gt_i32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x02,0xbf] + +s_cmp_gt_i32 exec_lo, s0 +// GFX13: s_cmp_gt_i32 exec_lo, s0 ; encoding: [0x7e,0x00,0x02,0xbf] + +s_cmp_gt_i32 m0, s0 +// GFX13: s_cmp_gt_i32 m0, s0 ; encoding: [0x7d,0x00,0x02,0xbf] + +s_cmp_gt_i32 null, s0 +// GFX13: s_cmp_gt_i32 null, s0 ; encoding: [0x7c,0x00,0x02,0xbf] + +s_cmp_gt_i32 0, s0 +// GFX13: s_cmp_gt_i32 0, s0 ; encoding: [0x80,0x00,0x02,0xbf] + +s_cmp_gt_i32 0.5, s0 +// GFX13: s_cmp_gt_i32 0.5, s0 ; encoding: [0xf0,0x00,0x02,0xbf] + +s_cmp_gt_i32 0x12345678, s0 +// GFX13: s_cmp_gt_i32 0x12345678, s0 ; encoding: [0xff,0x00,0x02,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_gt_i32 s0, s105 +// GFX13: s_cmp_gt_i32 s0, s105 ; encoding: [0x00,0x69,0x02,0xbf] + +s_cmp_gt_i32 s0, vcc_lo +// GFX13: s_cmp_gt_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x02,0xbf] + +s_cmp_gt_i32 s0, exec_lo +// GFX13: s_cmp_gt_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x02,0xbf] + +s_cmp_gt_i32 s0, m0 +// GFX13: s_cmp_gt_i32 s0, m0 ; encoding: [0x00,0x7d,0x02,0xbf] + +s_cmp_gt_i32 s0, null +// GFX13: s_cmp_gt_i32 s0, null ; encoding: [0x00,0x7c,0x02,0xbf] + +s_cmp_gt_i32 s0, 0 +// GFX13: s_cmp_gt_i32 s0, 0 ; encoding: [0x00,0x80,0x02,0xbf] + +s_cmp_gt_i32 s0, 0.5 +// GFX13: s_cmp_gt_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x02,0xbf] + +s_cmp_gt_i32 s0, 0x12345678 +// GFX13: s_cmp_gt_i32 s0, 0x12345678 ; encoding: [0x00,0xff,0x02,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_ge_i32 s0, s0 +// GFX13: s_cmp_ge_i32 s0, s0 ; encoding: [0x00,0x00,0x03,0xbf] + +s_cmp_ge_i32 s105, s0 +// GFX13: s_cmp_ge_i32 s105, s0 ; encoding: [0x69,0x00,0x03,0xbf] + +s_cmp_ge_i32 vcc_lo, s0 +// GFX13: s_cmp_ge_i32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x03,0xbf] + +s_cmp_ge_i32 exec_lo, s0 +// GFX13: s_cmp_ge_i32 exec_lo, s0 ; encoding: [0x7e,0x00,0x03,0xbf] + +s_cmp_ge_i32 m0, s0 +// GFX13: s_cmp_ge_i32 m0, s0 ; encoding: [0x7d,0x00,0x03,0xbf] + +s_cmp_ge_i32 null, s0 +// GFX13: s_cmp_ge_i32 null, s0 ; encoding: [0x7c,0x00,0x03,0xbf] + +s_cmp_ge_i32 0, s0 +// GFX13: s_cmp_ge_i32 0, s0 ; encoding: [0x80,0x00,0x03,0xbf] + +s_cmp_ge_i32 0.5, s0 +// GFX13: s_cmp_ge_i32 0.5, s0 ; encoding: [0xf0,0x00,0x03,0xbf] + +s_cmp_ge_i32 0x12345678, s0 +// GFX13: s_cmp_ge_i32 0x12345678, s0 ; encoding: [0xff,0x00,0x03,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_ge_i32 s0, s105 +// GFX13: s_cmp_ge_i32 s0, s105 ; encoding: [0x00,0x69,0x03,0xbf] + +s_cmp_ge_i32 s0, vcc_lo +// GFX13: s_cmp_ge_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x03,0xbf] + +s_cmp_ge_i32 s0, exec_lo +// GFX13: s_cmp_ge_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x03,0xbf] + +s_cmp_ge_i32 s0, m0 +// GFX13: s_cmp_ge_i32 s0, m0 ; encoding: [0x00,0x7d,0x03,0xbf] + +s_cmp_ge_i32 s0, null +// GFX13: s_cmp_ge_i32 s0, null ; encoding: [0x00,0x7c,0x03,0xbf] + +s_cmp_ge_i32 s0, 0 +// GFX13: s_cmp_ge_i32 s0, 0 ; encoding: [0x00,0x80,0x03,0xbf] + +s_cmp_ge_i32 s0, 0.5 +// GFX13: s_cmp_ge_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x03,0xbf] + +s_cmp_ge_i32 s0, 0x12345678 +// GFX13: s_cmp_ge_i32 s0, 0x12345678 ; encoding: [0x00,0xff,0x03,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lt_i32 s0, s0 +// GFX13: s_cmp_lt_i32 s0, s0 ; encoding: [0x00,0x00,0x04,0xbf] + +s_cmp_lt_i32 s105, s0 +// GFX13: s_cmp_lt_i32 s105, s0 ; encoding: [0x69,0x00,0x04,0xbf] + +s_cmp_lt_i32 vcc_lo, s0 +// GFX13: s_cmp_lt_i32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x04,0xbf] + +s_cmp_lt_i32 exec_lo, s0 +// GFX13: s_cmp_lt_i32 exec_lo, s0 ; encoding: [0x7e,0x00,0x04,0xbf] + +s_cmp_lt_i32 m0, s0 +// GFX13: s_cmp_lt_i32 m0, s0 ; encoding: [0x7d,0x00,0x04,0xbf] + +s_cmp_lt_i32 null, s0 +// GFX13: s_cmp_lt_i32 null, s0 ; encoding: [0x7c,0x00,0x04,0xbf] + +s_cmp_lt_i32 0, s0 +// GFX13: s_cmp_lt_i32 0, s0 ; encoding: [0x80,0x00,0x04,0xbf] + +s_cmp_lt_i32 0.5, s0 +// GFX13: s_cmp_lt_i32 0.5, s0 ; encoding: [0xf0,0x00,0x04,0xbf] + +s_cmp_lt_i32 0x12345678, s0 +// GFX13: s_cmp_lt_i32 0x12345678, s0 ; encoding: [0xff,0x00,0x04,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lt_i32 s0, s105 +// GFX13: s_cmp_lt_i32 s0, s105 ; encoding: [0x00,0x69,0x04,0xbf] + +s_cmp_lt_i32 s0, vcc_lo +// GFX13: s_cmp_lt_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x04,0xbf] + +s_cmp_lt_i32 s0, exec_lo +// GFX13: s_cmp_lt_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x04,0xbf] + +s_cmp_lt_i32 s0, m0 +// GFX13: s_cmp_lt_i32 s0, m0 ; encoding: [0x00,0x7d,0x04,0xbf] + +s_cmp_lt_i32 s0, null +// GFX13: s_cmp_lt_i32 s0, null ; encoding: [0x00,0x7c,0x04,0xbf] + +s_cmp_lt_i32 s0, 0 +// GFX13: s_cmp_lt_i32 s0, 0 ; encoding: [0x00,0x80,0x04,0xbf] + +s_cmp_lt_i32 s0, 0.5 +// GFX13: s_cmp_lt_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x04,0xbf] + +s_cmp_lt_i32 s0, 0x12345678 +// GFX13: s_cmp_lt_i32 s0, 0x12345678 ; encoding: [0x00,0xff,0x04,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_le_i32 s0, s0 +// GFX13: s_cmp_le_i32 s0, s0 ; encoding: [0x00,0x00,0x05,0xbf] + +s_cmp_le_i32 s105, s0 +// GFX13: s_cmp_le_i32 s105, s0 ; encoding: [0x69,0x00,0x05,0xbf] + +s_cmp_le_i32 vcc_lo, s0 +// GFX13: s_cmp_le_i32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x05,0xbf] + +s_cmp_le_i32 exec_lo, s0 +// GFX13: s_cmp_le_i32 exec_lo, s0 ; encoding: [0x7e,0x00,0x05,0xbf] + +s_cmp_le_i32 m0, s0 +// GFX13: s_cmp_le_i32 m0, s0 ; encoding: [0x7d,0x00,0x05,0xbf] + +s_cmp_le_i32 null, s0 +// GFX13: s_cmp_le_i32 null, s0 ; encoding: [0x7c,0x00,0x05,0xbf] + +s_cmp_le_i32 0, s0 +// GFX13: s_cmp_le_i32 0, s0 ; encoding: [0x80,0x00,0x05,0xbf] + +s_cmp_le_i32 0.5, s0 +// GFX13: s_cmp_le_i32 0.5, s0 ; encoding: [0xf0,0x00,0x05,0xbf] + +s_cmp_le_i32 0x12345678, s0 +// GFX13: s_cmp_le_i32 0x12345678, s0 ; encoding: [0xff,0x00,0x05,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_le_i32 s0, s105 +// GFX13: s_cmp_le_i32 s0, s105 ; encoding: [0x00,0x69,0x05,0xbf] + +s_cmp_le_i32 s0, vcc_lo +// GFX13: s_cmp_le_i32 s0, vcc_lo ; encoding: [0x00,0x6a,0x05,0xbf] + +s_cmp_le_i32 s0, exec_lo +// GFX13: s_cmp_le_i32 s0, exec_lo ; encoding: [0x00,0x7e,0x05,0xbf] + +s_cmp_le_i32 s0, m0 +// GFX13: s_cmp_le_i32 s0, m0 ; encoding: [0x00,0x7d,0x05,0xbf] + +s_cmp_le_i32 s0, null +// GFX13: s_cmp_le_i32 s0, null ; encoding: [0x00,0x7c,0x05,0xbf] + +s_cmp_le_i32 s0, 0 +// GFX13: s_cmp_le_i32 s0, 0 ; encoding: [0x00,0x80,0x05,0xbf] + +s_cmp_le_i32 s0, 0.5 +// GFX13: s_cmp_le_i32 s0, 0.5 ; encoding: [0x00,0xf0,0x05,0xbf] + +s_cmp_le_i32 s0, 0x12345678 +// GFX13: s_cmp_le_i32 s0, 0x12345678 ; encoding: [0x00,0xff,0x05,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_eq_u32 s0, s0 +// GFX13: s_cmp_eq_u32 s0, s0 ; encoding: [0x00,0x00,0x06,0xbf] + +s_cmp_eq_u32 s105, s0 +// GFX13: s_cmp_eq_u32 s105, s0 ; encoding: [0x69,0x00,0x06,0xbf] + +s_cmp_eq_u32 vcc_lo, s0 +// GFX13: s_cmp_eq_u32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x06,0xbf] + +s_cmp_eq_u32 exec_lo, s0 +// GFX13: s_cmp_eq_u32 exec_lo, s0 ; encoding: [0x7e,0x00,0x06,0xbf] + +s_cmp_eq_u32 m0, s0 +// GFX13: s_cmp_eq_u32 m0, s0 ; encoding: [0x7d,0x00,0x06,0xbf] + +s_cmp_eq_u32 null, s0 +// GFX13: s_cmp_eq_u32 null, s0 ; encoding: [0x7c,0x00,0x06,0xbf] + +s_cmp_eq_u32 0, s0 +// GFX13: s_cmp_eq_u32 0, s0 ; encoding: [0x80,0x00,0x06,0xbf] + +s_cmp_eq_u32 0.5, s0 +// GFX13: s_cmp_eq_u32 0.5, s0 ; encoding: [0xf0,0x00,0x06,0xbf] + +s_cmp_eq_u32 0x12345678, s0 +// GFX13: s_cmp_eq_u32 0x12345678, s0 ; encoding: [0xff,0x00,0x06,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_eq_u32 s0, s105 +// GFX13: s_cmp_eq_u32 s0, s105 ; encoding: [0x00,0x69,0x06,0xbf] + +s_cmp_eq_u32 s0, vcc_lo +// GFX13: s_cmp_eq_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x06,0xbf] + +s_cmp_eq_u32 s0, exec_lo +// GFX13: s_cmp_eq_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x06,0xbf] + +s_cmp_eq_u32 s0, m0 +// GFX13: s_cmp_eq_u32 s0, m0 ; encoding: [0x00,0x7d,0x06,0xbf] + +s_cmp_eq_u32 s0, null +// GFX13: s_cmp_eq_u32 s0, null ; encoding: [0x00,0x7c,0x06,0xbf] + +s_cmp_eq_u32 s0, 0 +// GFX13: s_cmp_eq_u32 s0, 0 ; encoding: [0x00,0x80,0x06,0xbf] + +s_cmp_eq_u32 s0, 0.5 +// GFX13: s_cmp_eq_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x06,0xbf] + +s_cmp_eq_u32 s0, 0x12345678 +// GFX13: s_cmp_eq_u32 s0, 0x12345678 ; encoding: [0x00,0xff,0x06,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lg_u32 s0, s0 +// GFX13: s_cmp_lg_u32 s0, s0 ; encoding: [0x00,0x00,0x07,0xbf] + +s_cmp_lg_u32 s105, s0 +// GFX13: s_cmp_lg_u32 s105, s0 ; encoding: [0x69,0x00,0x07,0xbf] + +s_cmp_lg_u32 vcc_lo, s0 +// GFX13: s_cmp_lg_u32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x07,0xbf] + +s_cmp_lg_u32 exec_lo, s0 +// GFX13: s_cmp_lg_u32 exec_lo, s0 ; encoding: [0x7e,0x00,0x07,0xbf] + +s_cmp_lg_u32 m0, s0 +// GFX13: s_cmp_lg_u32 m0, s0 ; encoding: [0x7d,0x00,0x07,0xbf] + +s_cmp_lg_u32 null, s0 +// GFX13: s_cmp_lg_u32 null, s0 ; encoding: [0x7c,0x00,0x07,0xbf] + +s_cmp_lg_u32 0, s0 +// GFX13: s_cmp_lg_u32 0, s0 ; encoding: [0x80,0x00,0x07,0xbf] + +s_cmp_lg_u32 0.5, s0 +// GFX13: s_cmp_lg_u32 0.5, s0 ; encoding: [0xf0,0x00,0x07,0xbf] + +s_cmp_lg_u32 0x12345678, s0 +// GFX13: s_cmp_lg_u32 0x12345678, s0 ; encoding: [0xff,0x00,0x07,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lg_u32 s0, s105 +// GFX13: s_cmp_lg_u32 s0, s105 ; encoding: [0x00,0x69,0x07,0xbf] + +s_cmp_lg_u32 s0, vcc_lo +// GFX13: s_cmp_lg_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x07,0xbf] + +s_cmp_lg_u32 s0, exec_lo +// GFX13: s_cmp_lg_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x07,0xbf] + +s_cmp_lg_u32 s0, m0 +// GFX13: s_cmp_lg_u32 s0, m0 ; encoding: [0x00,0x7d,0x07,0xbf] + +s_cmp_lg_u32 s0, null +// GFX13: s_cmp_lg_u32 s0, null ; encoding: [0x00,0x7c,0x07,0xbf] + +s_cmp_lg_u32 s0, 0 +// GFX13: s_cmp_lg_u32 s0, 0 ; encoding: [0x00,0x80,0x07,0xbf] + +s_cmp_lg_u32 s0, 0.5 +// GFX13: s_cmp_lg_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x07,0xbf] + +s_cmp_lg_u32 s0, 0x12345678 +// GFX13: s_cmp_lg_u32 s0, 0x12345678 ; encoding: [0x00,0xff,0x07,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_gt_u32 s0, s0 +// GFX13: s_cmp_gt_u32 s0, s0 ; encoding: [0x00,0x00,0x08,0xbf] + +s_cmp_gt_u32 s105, s0 +// GFX13: s_cmp_gt_u32 s105, s0 ; encoding: [0x69,0x00,0x08,0xbf] + +s_cmp_gt_u32 vcc_lo, s0 +// GFX13: s_cmp_gt_u32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x08,0xbf] + +s_cmp_gt_u32 exec_lo, s0 +// GFX13: s_cmp_gt_u32 exec_lo, s0 ; encoding: [0x7e,0x00,0x08,0xbf] + +s_cmp_gt_u32 m0, s0 +// GFX13: s_cmp_gt_u32 m0, s0 ; encoding: [0x7d,0x00,0x08,0xbf] + +s_cmp_gt_u32 null, s0 +// GFX13: s_cmp_gt_u32 null, s0 ; encoding: [0x7c,0x00,0x08,0xbf] + +s_cmp_gt_u32 0, s0 +// GFX13: s_cmp_gt_u32 0, s0 ; encoding: [0x80,0x00,0x08,0xbf] + +s_cmp_gt_u32 0.5, s0 +// GFX13: s_cmp_gt_u32 0.5, s0 ; encoding: [0xf0,0x00,0x08,0xbf] + +s_cmp_gt_u32 0x12345678, s0 +// GFX13: s_cmp_gt_u32 0x12345678, s0 ; encoding: [0xff,0x00,0x08,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_gt_u32 s0, s105 +// GFX13: s_cmp_gt_u32 s0, s105 ; encoding: [0x00,0x69,0x08,0xbf] + +s_cmp_gt_u32 s0, vcc_lo +// GFX13: s_cmp_gt_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x08,0xbf] + +s_cmp_gt_u32 s0, exec_lo +// GFX13: s_cmp_gt_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x08,0xbf] + +s_cmp_gt_u32 s0, m0 +// GFX13: s_cmp_gt_u32 s0, m0 ; encoding: [0x00,0x7d,0x08,0xbf] + +s_cmp_gt_u32 s0, null +// GFX13: s_cmp_gt_u32 s0, null ; encoding: [0x00,0x7c,0x08,0xbf] + +s_cmp_gt_u32 s0, 0 +// GFX13: s_cmp_gt_u32 s0, 0 ; encoding: [0x00,0x80,0x08,0xbf] + +s_cmp_gt_u32 s0, 0.5 +// GFX13: s_cmp_gt_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x08,0xbf] + +s_cmp_gt_u32 s0, 0x12345678 +// GFX13: s_cmp_gt_u32 s0, 0x12345678 ; encoding: [0x00,0xff,0x08,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_ge_u32 s0, s0 +// GFX13: s_cmp_ge_u32 s0, s0 ; encoding: [0x00,0x00,0x09,0xbf] + +s_cmp_ge_u32 s105, s0 +// GFX13: s_cmp_ge_u32 s105, s0 ; encoding: [0x69,0x00,0x09,0xbf] + +s_cmp_ge_u32 vcc_lo, s0 +// GFX13: s_cmp_ge_u32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x09,0xbf] + +s_cmp_ge_u32 exec_lo, s0 +// GFX13: s_cmp_ge_u32 exec_lo, s0 ; encoding: [0x7e,0x00,0x09,0xbf] + +s_cmp_ge_u32 m0, s0 +// GFX13: s_cmp_ge_u32 m0, s0 ; encoding: [0x7d,0x00,0x09,0xbf] + +s_cmp_ge_u32 null, s0 +// GFX13: s_cmp_ge_u32 null, s0 ; encoding: [0x7c,0x00,0x09,0xbf] + +s_cmp_ge_u32 0, s0 +// GFX13: s_cmp_ge_u32 0, s0 ; encoding: [0x80,0x00,0x09,0xbf] + +s_cmp_ge_u32 0.5, s0 +// GFX13: s_cmp_ge_u32 0.5, s0 ; encoding: [0xf0,0x00,0x09,0xbf] + +s_cmp_ge_u32 0x12345678, s0 +// GFX13: s_cmp_ge_u32 0x12345678, s0 ; encoding: [0xff,0x00,0x09,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_ge_u32 s0, s105 +// GFX13: s_cmp_ge_u32 s0, s105 ; encoding: [0x00,0x69,0x09,0xbf] + +s_cmp_ge_u32 s0, vcc_lo +// GFX13: s_cmp_ge_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x09,0xbf] + +s_cmp_ge_u32 s0, exec_lo +// GFX13: s_cmp_ge_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x09,0xbf] + +s_cmp_ge_u32 s0, m0 +// GFX13: s_cmp_ge_u32 s0, m0 ; encoding: [0x00,0x7d,0x09,0xbf] + +s_cmp_ge_u32 s0, null +// GFX13: s_cmp_ge_u32 s0, null ; encoding: [0x00,0x7c,0x09,0xbf] + +s_cmp_ge_u32 s0, 0 +// GFX13: s_cmp_ge_u32 s0, 0 ; encoding: [0x00,0x80,0x09,0xbf] + +s_cmp_ge_u32 s0, 0.5 +// GFX13: s_cmp_ge_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x09,0xbf] + +s_cmp_ge_u32 s0, 0x12345678 +// GFX13: s_cmp_ge_u32 s0, 0x12345678 ; encoding: [0x00,0xff,0x09,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lt_u32 s0, s0 +// GFX13: s_cmp_lt_u32 s0, s0 ; encoding: [0x00,0x00,0x0a,0xbf] + +s_cmp_lt_u32 s105, s0 +// GFX13: s_cmp_lt_u32 s105, s0 ; encoding: [0x69,0x00,0x0a,0xbf] + +s_cmp_lt_u32 vcc_lo, s0 +// GFX13: s_cmp_lt_u32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x0a,0xbf] + +s_cmp_lt_u32 exec_lo, s0 +// GFX13: s_cmp_lt_u32 exec_lo, s0 ; encoding: [0x7e,0x00,0x0a,0xbf] + +s_cmp_lt_u32 m0, s0 +// GFX13: s_cmp_lt_u32 m0, s0 ; encoding: [0x7d,0x00,0x0a,0xbf] + +s_cmp_lt_u32 null, s0 +// GFX13: s_cmp_lt_u32 null, s0 ; encoding: [0x7c,0x00,0x0a,0xbf] + +s_cmp_lt_u32 0, s0 +// GFX13: s_cmp_lt_u32 0, s0 ; encoding: [0x80,0x00,0x0a,0xbf] + +s_cmp_lt_u32 0.5, s0 +// GFX13: s_cmp_lt_u32 0.5, s0 ; encoding: [0xf0,0x00,0x0a,0xbf] + +s_cmp_lt_u32 0x12345678, s0 +// GFX13: s_cmp_lt_u32 0x12345678, s0 ; encoding: [0xff,0x00,0x0a,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lt_u32 s0, s105 +// GFX13: s_cmp_lt_u32 s0, s105 ; encoding: [0x00,0x69,0x0a,0xbf] + +s_cmp_lt_u32 s0, vcc_lo +// GFX13: s_cmp_lt_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x0a,0xbf] + +s_cmp_lt_u32 s0, exec_lo +// GFX13: s_cmp_lt_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x0a,0xbf] + +s_cmp_lt_u32 s0, m0 +// GFX13: s_cmp_lt_u32 s0, m0 ; encoding: [0x00,0x7d,0x0a,0xbf] + +s_cmp_lt_u32 s0, null +// GFX13: s_cmp_lt_u32 s0, null ; encoding: [0x00,0x7c,0x0a,0xbf] + +s_cmp_lt_u32 s0, 0 +// GFX13: s_cmp_lt_u32 s0, 0 ; encoding: [0x00,0x80,0x0a,0xbf] + +s_cmp_lt_u32 s0, 0.5 +// GFX13: s_cmp_lt_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x0a,0xbf] + +s_cmp_lt_u32 s0, 0x12345678 +// GFX13: s_cmp_lt_u32 s0, 0x12345678 ; encoding: [0x00,0xff,0x0a,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_le_u32 s0, s0 +// GFX13: s_cmp_le_u32 s0, s0 ; encoding: [0x00,0x00,0x0b,0xbf] + +s_cmp_le_u32 s105, s0 +// GFX13: s_cmp_le_u32 s105, s0 ; encoding: [0x69,0x00,0x0b,0xbf] + +s_cmp_le_u32 vcc_lo, s0 +// GFX13: s_cmp_le_u32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x0b,0xbf] + +s_cmp_le_u32 exec_lo, s0 +// GFX13: s_cmp_le_u32 exec_lo, s0 ; encoding: [0x7e,0x00,0x0b,0xbf] + +s_cmp_le_u32 m0, s0 +// GFX13: s_cmp_le_u32 m0, s0 ; encoding: [0x7d,0x00,0x0b,0xbf] + +s_cmp_le_u32 null, s0 +// GFX13: s_cmp_le_u32 null, s0 ; encoding: [0x7c,0x00,0x0b,0xbf] + +s_cmp_le_u32 0, s0 +// GFX13: s_cmp_le_u32 0, s0 ; encoding: [0x80,0x00,0x0b,0xbf] + +s_cmp_le_u32 0.5, s0 +// GFX13: s_cmp_le_u32 0.5, s0 ; encoding: [0xf0,0x00,0x0b,0xbf] + +s_cmp_le_u32 0x12345678, s0 +// GFX13: s_cmp_le_u32 0x12345678, s0 ; encoding: [0xff,0x00,0x0b,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_le_u32 s0, s105 +// GFX13: s_cmp_le_u32 s0, s105 ; encoding: [0x00,0x69,0x0b,0xbf] + +s_cmp_le_u32 s0, vcc_lo +// GFX13: s_cmp_le_u32 s0, vcc_lo ; encoding: [0x00,0x6a,0x0b,0xbf] + +s_cmp_le_u32 s0, exec_lo +// GFX13: s_cmp_le_u32 s0, exec_lo ; encoding: [0x00,0x7e,0x0b,0xbf] + +s_cmp_le_u32 s0, m0 +// GFX13: s_cmp_le_u32 s0, m0 ; encoding: [0x00,0x7d,0x0b,0xbf] + +s_cmp_le_u32 s0, null +// GFX13: s_cmp_le_u32 s0, null ; encoding: [0x00,0x7c,0x0b,0xbf] + +s_cmp_le_u32 s0, 0 +// GFX13: s_cmp_le_u32 s0, 0 ; encoding: [0x00,0x80,0x0b,0xbf] + +s_cmp_le_u32 s0, 0.5 +// GFX13: s_cmp_le_u32 s0, 0.5 ; encoding: [0x00,0xf0,0x0b,0xbf] + +s_cmp_le_u32 s0, 0x12345678 +// GFX13: s_cmp_le_u32 s0, 0x12345678 ; encoding: [0x00,0xff,0x0b,0xbf,0x78,0x56,0x34,0x12] + +s_bitcmp0_b32 s0, s0 +// GFX13: s_bitcmp0_b32 s0, s0 ; encoding: [0x00,0x00,0x0c,0xbf] + +s_bitcmp0_b32 s105, s0 +// GFX13: s_bitcmp0_b32 s105, s0 ; encoding: [0x69,0x00,0x0c,0xbf] + +s_bitcmp0_b32 vcc_lo, s0 +// GFX13: s_bitcmp0_b32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x0c,0xbf] + +s_bitcmp0_b32 exec_lo, s0 +// GFX13: s_bitcmp0_b32 exec_lo, s0 ; encoding: [0x7e,0x00,0x0c,0xbf] + +s_bitcmp0_b32 m0, s0 +// GFX13: s_bitcmp0_b32 m0, s0 ; encoding: [0x7d,0x00,0x0c,0xbf] + +s_bitcmp0_b32 null, s0 +// GFX13: s_bitcmp0_b32 null, s0 ; encoding: [0x7c,0x00,0x0c,0xbf] + +s_bitcmp0_b32 0, s0 +// GFX13: s_bitcmp0_b32 0, s0 ; encoding: [0x80,0x00,0x0c,0xbf] + +s_bitcmp0_b32 0.5, s0 +// GFX13: s_bitcmp0_b32 0.5, s0 ; encoding: [0xf0,0x00,0x0c,0xbf] + +s_bitcmp0_b32 0x12345678, s0 +// GFX13: s_bitcmp0_b32 0x12345678, s0 ; encoding: [0xff,0x00,0x0c,0xbf,0x78,0x56,0x34,0x12] + +s_bitcmp0_b32 s0, s105 +// GFX13: s_bitcmp0_b32 s0, s105 ; encoding: [0x00,0x69,0x0c,0xbf] + +s_bitcmp0_b32 s0, vcc_lo +// GFX13: s_bitcmp0_b32 s0, vcc_lo ; encoding: [0x00,0x6a,0x0c,0xbf] + +s_bitcmp0_b32 s0, exec_lo +// GFX13: s_bitcmp0_b32 s0, exec_lo ; encoding: [0x00,0x7e,0x0c,0xbf] + +s_bitcmp0_b32 s0, m0 +// GFX13: s_bitcmp0_b32 s0, m0 ; encoding: [0x00,0x7d,0x0c,0xbf] + +s_bitcmp0_b32 s0, null +// GFX13: s_bitcmp0_b32 s0, null ; encoding: [0x00,0x7c,0x0c,0xbf] + +s_bitcmp0_b32 s0, 0 +// GFX13: s_bitcmp0_b32 s0, 0 ; encoding: [0x00,0x80,0x0c,0xbf] + +s_bitcmp0_b32 s0, 0.5 +// GFX13: s_bitcmp0_b32 s0, 0.5 ; encoding: [0x00,0xf0,0x0c,0xbf] + +s_bitcmp0_b32 s0, 0x12345678 +// GFX13: s_bitcmp0_b32 s0, 0x12345678 ; encoding: [0x00,0xff,0x0c,0xbf,0x78,0x56,0x34,0x12] + +s_bitcmp1_b32 s0, s0 +// GFX13: s_bitcmp1_b32 s0, s0 ; encoding: [0x00,0x00,0x0d,0xbf] + +s_bitcmp1_b32 s105, s0 +// GFX13: s_bitcmp1_b32 s105, s0 ; encoding: [0x69,0x00,0x0d,0xbf] + +s_bitcmp1_b32 vcc_lo, s0 +// GFX13: s_bitcmp1_b32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x0d,0xbf] + +s_bitcmp1_b32 exec_lo, s0 +// GFX13: s_bitcmp1_b32 exec_lo, s0 ; encoding: [0x7e,0x00,0x0d,0xbf] + +s_bitcmp1_b32 m0, s0 +// GFX13: s_bitcmp1_b32 m0, s0 ; encoding: [0x7d,0x00,0x0d,0xbf] + +s_bitcmp1_b32 null, s0 +// GFX13: s_bitcmp1_b32 null, s0 ; encoding: [0x7c,0x00,0x0d,0xbf] + +s_bitcmp1_b32 0, s0 +// GFX13: s_bitcmp1_b32 0, s0 ; encoding: [0x80,0x00,0x0d,0xbf] + +s_bitcmp1_b32 0.5, s0 +// GFX13: s_bitcmp1_b32 0.5, s0 ; encoding: [0xf0,0x00,0x0d,0xbf] + +s_bitcmp1_b32 0x12345678, s0 +// GFX13: s_bitcmp1_b32 0x12345678, s0 ; encoding: [0xff,0x00,0x0d,0xbf,0x78,0x56,0x34,0x12] + +s_bitcmp1_b32 s0, s105 +// GFX13: s_bitcmp1_b32 s0, s105 ; encoding: [0x00,0x69,0x0d,0xbf] + +s_bitcmp1_b32 s0, vcc_lo +// GFX13: s_bitcmp1_b32 s0, vcc_lo ; encoding: [0x00,0x6a,0x0d,0xbf] + +s_bitcmp1_b32 s0, exec_lo +// GFX13: s_bitcmp1_b32 s0, exec_lo ; encoding: [0x00,0x7e,0x0d,0xbf] + +s_bitcmp1_b32 s0, m0 +// GFX13: s_bitcmp1_b32 s0, m0 ; encoding: [0x00,0x7d,0x0d,0xbf] + +s_bitcmp1_b32 s0, null +// GFX13: s_bitcmp1_b32 s0, null ; encoding: [0x00,0x7c,0x0d,0xbf] + +s_bitcmp1_b32 s0, 0 +// GFX13: s_bitcmp1_b32 s0, 0 ; encoding: [0x00,0x80,0x0d,0xbf] + +s_bitcmp1_b32 s0, 0.5 +// GFX13: s_bitcmp1_b32 s0, 0.5 ; encoding: [0x00,0xf0,0x0d,0xbf] + +s_bitcmp1_b32 s0, 0x12345678 +// GFX13: s_bitcmp1_b32 s0, 0x12345678 ; encoding: [0x00,0xff,0x0d,0xbf,0x78,0x56,0x34,0x12] + +s_bitcmp0_b64 s[0:1], s0 +// GFX13: s_bitcmp0_b64 s[0:1], s0 ; encoding: [0x00,0x00,0x0e,0xbf] + +s_bitcmp0_b64 s[104:105], s0 +// GFX13: s_bitcmp0_b64 s[104:105], s0 ; encoding: [0x68,0x00,0x0e,0xbf] + +s_bitcmp0_b64 vcc, s0 +// GFX13: s_bitcmp0_b64 vcc, s0 ; encoding: [0x6a,0x00,0x0e,0xbf] + +s_bitcmp0_b64 exec, s0 +// GFX13: s_bitcmp0_b64 exec, s0 ; encoding: [0x7e,0x00,0x0e,0xbf] + +s_bitcmp0_b64 null, s0 +// GFX13: s_bitcmp0_b64 null, s0 ; encoding: [0x7c,0x00,0x0e,0xbf] + +s_bitcmp0_b64 0, s0 +// GFX13: s_bitcmp0_b64 0, s0 ; encoding: [0x80,0x00,0x0e,0xbf] + +s_bitcmp0_b64 0.5, s0 +// GFX13: s_bitcmp0_b64 0.5, s0 ; encoding: [0xf0,0x00,0x0e,0xbf] + +s_bitcmp0_b64 0x123456789abcdef0, s0 +// GFX13: s_bitcmp0_b64 0x123456789abcdef0, s0 ; encoding: [0xfe,0x00,0x0e,0xbf,0xf0,0xde,0xbc,0x9a,0x78,0x56,0x34,0x12] + +s_bitcmp0_b64 s[0:1], s105 +// GFX13: s_bitcmp0_b64 s[0:1], s105 ; encoding: [0x00,0x69,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], vcc_lo +// GFX13: s_bitcmp0_b64 s[0:1], vcc_lo ; encoding: [0x00,0x6a,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], exec_lo +// GFX13: s_bitcmp0_b64 s[0:1], exec_lo ; encoding: [0x00,0x7e,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], m0 +// GFX13: s_bitcmp0_b64 s[0:1], m0 ; encoding: [0x00,0x7d,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], null +// GFX13: s_bitcmp0_b64 s[0:1], null ; encoding: [0x00,0x7c,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], 0 +// GFX13: s_bitcmp0_b64 s[0:1], 0 ; encoding: [0x00,0x80,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], 0.5 +// GFX13: s_bitcmp0_b64 s[0:1], 0.5 ; encoding: [0x00,0xf0,0x0e,0xbf] + +s_bitcmp0_b64 s[0:1], 0x12345678 +// GFX13: s_bitcmp0_b64 s[0:1], 0x12345678 ; encoding: [0x00,0xff,0x0e,0xbf,0x78,0x56,0x34,0x12] + +s_bitcmp1_b64 s[0:1], s0 +// GFX13: s_bitcmp1_b64 s[0:1], s0 ; encoding: [0x00,0x00,0x0f,0xbf] + +s_bitcmp1_b64 s[104:105], s0 +// GFX13: s_bitcmp1_b64 s[104:105], s0 ; encoding: [0x68,0x00,0x0f,0xbf] + +s_bitcmp1_b64 vcc, s0 +// GFX13: s_bitcmp1_b64 vcc, s0 ; encoding: [0x6a,0x00,0x0f,0xbf] + +s_bitcmp1_b64 exec, s0 +// GFX13: s_bitcmp1_b64 exec, s0 ; encoding: [0x7e,0x00,0x0f,0xbf] + +s_bitcmp1_b64 null, s0 +// GFX13: s_bitcmp1_b64 null, s0 ; encoding: [0x7c,0x00,0x0f,0xbf] + +s_bitcmp1_b64 0, s0 +// GFX13: s_bitcmp1_b64 0, s0 ; encoding: [0x80,0x00,0x0f,0xbf] + +s_bitcmp1_b64 0.5, s0 +// GFX13: s_bitcmp1_b64 0.5, s0 ; encoding: [0xf0,0x00,0x0f,0xbf] + +s_bitcmp1_b64 0x123456789abcdef0, s0 +// GFX13: s_bitcmp1_b64 0x123456789abcdef0, s0 ; encoding: [0xfe,0x00,0x0f,0xbf,0xf0,0xde,0xbc,0x9a,0x78,0x56,0x34,0x12] + +s_bitcmp1_b64 s[0:1], s105 +// GFX13: s_bitcmp1_b64 s[0:1], s105 ; encoding: [0x00,0x69,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], vcc_lo +// GFX13: s_bitcmp1_b64 s[0:1], vcc_lo ; encoding: [0x00,0x6a,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], exec_lo +// GFX13: s_bitcmp1_b64 s[0:1], exec_lo ; encoding: [0x00,0x7e,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], m0 +// GFX13: s_bitcmp1_b64 s[0:1], m0 ; encoding: [0x00,0x7d,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], null +// GFX13: s_bitcmp1_b64 s[0:1], null ; encoding: [0x00,0x7c,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], 0 +// GFX13: s_bitcmp1_b64 s[0:1], 0 ; encoding: [0x00,0x80,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], 0.5 +// GFX13: s_bitcmp1_b64 s[0:1], 0.5 ; encoding: [0x00,0xf0,0x0f,0xbf] + +s_bitcmp1_b64 s[0:1], 0x12345678 +// GFX13: s_bitcmp1_b64 s[0:1], 0x12345678 ; encoding: [0x00,0xff,0x0f,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_eq_u64 s[0:1], s[0:1] +// GFX13: s_cmp_eq_u64 s[0:1], s[0:1] ; encoding: [0x00,0x00,0x12,0xbf] + +s_cmp_eq_u64 s[104:105], s[0:1] +// GFX13: s_cmp_eq_u64 s[104:105], s[0:1] ; encoding: [0x68,0x00,0x12,0xbf] + +s_cmp_eq_u64 vcc, s[0:1] +// GFX13: s_cmp_eq_u64 vcc, s[0:1] ; encoding: [0x6a,0x00,0x12,0xbf] + +s_cmp_eq_u64 exec, s[0:1] +// GFX13: s_cmp_eq_u64 exec, s[0:1] ; encoding: [0x7e,0x00,0x12,0xbf] + +s_cmp_eq_u64 null, s[0:1] +// GFX13: s_cmp_eq_u64 null, s[0:1] ; encoding: [0x7c,0x00,0x12,0xbf] + +s_cmp_eq_u64 0, s[0:1] +// GFX13: s_cmp_eq_u64 0, s[0:1] ; encoding: [0x80,0x00,0x12,0xbf] + +s_cmp_eq_u64 0.5, s[0:1] +// GFX13: s_cmp_eq_u64 0.5, s[0:1] ; encoding: [0xf0,0x00,0x12,0xbf] + +s_cmp_eq_u64 0x123456789abcdef0, s[0:1] +// GFX13: s_cmp_eq_u64 0x123456789abcdef0, s[0:1] ; encoding: [0xfe,0x00,0x12,0xbf,0xf0,0xde,0xbc,0x9a,0x78,0x56,0x34,0x12] + +s_cmp_eq_u64 s[0:1], s[104:105] +// GFX13: s_cmp_eq_u64 s[0:1], s[104:105] ; encoding: [0x00,0x68,0x12,0xbf] + +s_cmp_eq_u64 s[0:1], vcc +// GFX13: s_cmp_eq_u64 s[0:1], vcc ; encoding: [0x00,0x6a,0x12,0xbf] + +s_cmp_eq_u64 s[0:1], exec +// GFX13: s_cmp_eq_u64 s[0:1], exec ; encoding: [0x00,0x7e,0x12,0xbf] + +s_cmp_eq_u64 s[0:1], null +// GFX13: s_cmp_eq_u64 s[0:1], null ; encoding: [0x00,0x7c,0x12,0xbf] + +s_cmp_eq_u64 s[0:1], 0 +// GFX13: s_cmp_eq_u64 s[0:1], 0 ; encoding: [0x00,0x80,0x12,0xbf] + +s_cmp_eq_u64 s[0:1], 0.5 +// GFX13: s_cmp_eq_u64 s[0:1], 0.5 ; encoding: [0x00,0xf0,0x12,0xbf] + +s_cmp_eq_u64 s[0:1], 0x123456789abcdef0 +// GFX13: s_cmp_eq_u64 s[0:1], 0x123456789abcdef0 ; encoding: [0x00,0xfe,0x12,0xbf,0xf0,0xde,0xbc,0x9a,0x78,0x56,0x34,0x12] + +s_cmp_lg_u64 s[0:1], s[0:1] +// GFX13: s_cmp_lg_u64 s[0:1], s[0:1] ; encoding: [0x00,0x00,0x13,0xbf] + +s_cmp_lg_u64 s[104:105], s[0:1] +// GFX13: s_cmp_lg_u64 s[104:105], s[0:1] ; encoding: [0x68,0x00,0x13,0xbf] + +s_cmp_lg_u64 vcc, s[0:1] +// GFX13: s_cmp_lg_u64 vcc, s[0:1] ; encoding: [0x6a,0x00,0x13,0xbf] + +s_cmp_lg_u64 exec, s[0:1] +// GFX13: s_cmp_lg_u64 exec, s[0:1] ; encoding: [0x7e,0x00,0x13,0xbf] + +s_cmp_lg_u64 null, s[0:1] +// GFX13: s_cmp_lg_u64 null, s[0:1] ; encoding: [0x7c,0x00,0x13,0xbf] + +s_cmp_lg_u64 0, s[0:1] +// GFX13: s_cmp_lg_u64 0, s[0:1] ; encoding: [0x80,0x00,0x13,0xbf] + +s_cmp_lg_u64 0.5, s[0:1] +// GFX13: s_cmp_lg_u64 0.5, s[0:1] ; encoding: [0xf0,0x00,0x13,0xbf] + +s_cmp_lg_u64 0x123456789abcdef0, s[0:1] +// GFX13: s_cmp_lg_u64 0x123456789abcdef0, s[0:1] ; encoding: [0xfe,0x00,0x13,0xbf,0xf0,0xde,0xbc,0x9a,0x78,0x56,0x34,0x12] + +s_cmp_lg_u64 s[0:1], s[104:105] +// GFX13: s_cmp_lg_u64 s[0:1], s[104:105] ; encoding: [0x00,0x68,0x13,0xbf] + +s_cmp_lg_u64 s[0:1], vcc +// GFX13: s_cmp_lg_u64 s[0:1], vcc ; encoding: [0x00,0x6a,0x13,0xbf] + +s_cmp_lg_u64 s[0:1], exec +// GFX13: s_cmp_lg_u64 s[0:1], exec ; encoding: [0x00,0x7e,0x13,0xbf] + +s_cmp_lg_u64 s[0:1], null +// GFX13: s_cmp_lg_u64 s[0:1], null ; encoding: [0x00,0x7c,0x13,0xbf] + +s_cmp_lg_u64 s[0:1], 0 +// GFX13: s_cmp_lg_u64 s[0:1], 0 ; encoding: [0x00,0x80,0x13,0xbf] + +s_cmp_lg_u64 s[0:1], 0.5 +// GFX13: s_cmp_lg_u64 s[0:1], 0.5 ; encoding: [0x00,0xf0,0x13,0xbf] + +s_cmp_lg_u64 s[0:1], 0x123456789abcdef0 +// GFX13: s_cmp_lg_u64 s[0:1], 0x123456789abcdef0 ; encoding: [0x00,0xfe,0x13,0xbf,0xf0,0xde,0xbc,0x9a,0x78,0x56,0x34,0x12] + +s_cmp_lt_f32 s0, s0 +// GFX13: s_cmp_lt_f32 s0, s0 ; encoding: [0x00,0x00,0x41,0xbf] + +s_cmp_lt_f32 s105, s0 +// GFX13: s_cmp_lt_f32 s105, s0 ; encoding: [0x69,0x00,0x41,0xbf] + +s_cmp_lt_f32 vcc_lo, s0 +// GFX13: s_cmp_lt_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x41,0xbf] + +s_cmp_lt_f32 exec_lo, s0 +// GFX13: s_cmp_lt_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x41,0xbf] + +s_cmp_lt_f32 m0, s0 +// GFX13: s_cmp_lt_f32 m0, s0 ; encoding: [0x7d,0x00,0x41,0xbf] + +s_cmp_lt_f32 null, s0 +// GFX13: s_cmp_lt_f32 null, s0 ; encoding: [0x7c,0x00,0x41,0xbf] + +s_cmp_lt_f32 0, s0 +// GFX13: s_cmp_lt_f32 0, s0 ; encoding: [0x80,0x00,0x41,0xbf] + +s_cmp_lt_f32 0.5, s0 +// GFX13: s_cmp_lt_f32 0.5, s0 ; encoding: [0xf0,0x00,0x41,0xbf] + +s_cmp_lt_f32 0x12345678, s0 +// GFX13: s_cmp_lt_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x41,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lt_f32 s0, s105 +// GFX13: s_cmp_lt_f32 s0, s105 ; encoding: [0x00,0x69,0x41,0xbf] + +s_cmp_lt_f32 s0, vcc_lo +// GFX13: s_cmp_lt_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x41,0xbf] + +s_cmp_lt_f32 s0, exec_lo +// GFX13: s_cmp_lt_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x41,0xbf] + +s_cmp_lt_f32 s0, m0 +// GFX13: s_cmp_lt_f32 s0, m0 ; encoding: [0x00,0x7d,0x41,0xbf] + +s_cmp_lt_f32 s0, null +// GFX13: s_cmp_lt_f32 s0, null ; encoding: [0x00,0x7c,0x41,0xbf] + +s_cmp_lt_f32 s0, 0 +// GFX13: s_cmp_lt_f32 s0, 0 ; encoding: [0x00,0x80,0x41,0xbf] + +s_cmp_lt_f32 s0, 0.5 +// GFX13: s_cmp_lt_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x41,0xbf] + +s_cmp_lt_f32 s0, 0x12345678 +// GFX13: s_cmp_lt_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x41,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_eq_f32 s0, s0 +// GFX13: s_cmp_eq_f32 s0, s0 ; encoding: [0x00,0x00,0x42,0xbf] + +s_cmp_eq_f32 s105, s0 +// GFX13: s_cmp_eq_f32 s105, s0 ; encoding: [0x69,0x00,0x42,0xbf] + +s_cmp_eq_f32 vcc_lo, s0 +// GFX13: s_cmp_eq_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x42,0xbf] + +s_cmp_eq_f32 exec_lo, s0 +// GFX13: s_cmp_eq_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x42,0xbf] + +s_cmp_eq_f32 m0, s0 +// GFX13: s_cmp_eq_f32 m0, s0 ; encoding: [0x7d,0x00,0x42,0xbf] + +s_cmp_eq_f32 null, s0 +// GFX13: s_cmp_eq_f32 null, s0 ; encoding: [0x7c,0x00,0x42,0xbf] + +s_cmp_eq_f32 0, s0 +// GFX13: s_cmp_eq_f32 0, s0 ; encoding: [0x80,0x00,0x42,0xbf] + +s_cmp_eq_f32 0.5, s0 +// GFX13: s_cmp_eq_f32 0.5, s0 ; encoding: [0xf0,0x00,0x42,0xbf] + +s_cmp_eq_f32 0x12345678, s0 +// GFX13: s_cmp_eq_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x42,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_eq_f32 s0, s105 +// GFX13: s_cmp_eq_f32 s0, s105 ; encoding: [0x00,0x69,0x42,0xbf] + +s_cmp_eq_f32 s0, vcc_lo +// GFX13: s_cmp_eq_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x42,0xbf] + +s_cmp_eq_f32 s0, exec_lo +// GFX13: s_cmp_eq_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x42,0xbf] + +s_cmp_eq_f32 s0, m0 +// GFX13: s_cmp_eq_f32 s0, m0 ; encoding: [0x00,0x7d,0x42,0xbf] + +s_cmp_eq_f32 s0, null +// GFX13: s_cmp_eq_f32 s0, null ; encoding: [0x00,0x7c,0x42,0xbf] + +s_cmp_eq_f32 s0, 0 +// GFX13: s_cmp_eq_f32 s0, 0 ; encoding: [0x00,0x80,0x42,0xbf] + +s_cmp_eq_f32 s0, 0.5 +// GFX13: s_cmp_eq_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x42,0xbf] + +s_cmp_eq_f32 s0, 0x12345678 +// GFX13: s_cmp_eq_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x42,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_le_f32 s0, s0 +// GFX13: s_cmp_le_f32 s0, s0 ; encoding: [0x00,0x00,0x43,0xbf] + +s_cmp_le_f32 s105, s0 +// GFX13: s_cmp_le_f32 s105, s0 ; encoding: [0x69,0x00,0x43,0xbf] + +s_cmp_le_f32 vcc_lo, s0 +// GFX13: s_cmp_le_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x43,0xbf] + +s_cmp_le_f32 exec_lo, s0 +// GFX13: s_cmp_le_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x43,0xbf] + +s_cmp_le_f32 m0, s0 +// GFX13: s_cmp_le_f32 m0, s0 ; encoding: [0x7d,0x00,0x43,0xbf] + +s_cmp_le_f32 null, s0 +// GFX13: s_cmp_le_f32 null, s0 ; encoding: [0x7c,0x00,0x43,0xbf] + +s_cmp_le_f32 0, s0 +// GFX13: s_cmp_le_f32 0, s0 ; encoding: [0x80,0x00,0x43,0xbf] + +s_cmp_le_f32 0.5, s0 +// GFX13: s_cmp_le_f32 0.5, s0 ; encoding: [0xf0,0x00,0x43,0xbf] + +s_cmp_le_f32 0x12345678, s0 +// GFX13: s_cmp_le_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x43,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_le_f32 s0, s105 +// GFX13: s_cmp_le_f32 s0, s105 ; encoding: [0x00,0x69,0x43,0xbf] + +s_cmp_le_f32 s0, vcc_lo +// GFX13: s_cmp_le_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x43,0xbf] + +s_cmp_le_f32 s0, exec_lo +// GFX13: s_cmp_le_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x43,0xbf] + +s_cmp_le_f32 s0, m0 +// GFX13: s_cmp_le_f32 s0, m0 ; encoding: [0x00,0x7d,0x43,0xbf] + +s_cmp_le_f32 s0, null +// GFX13: s_cmp_le_f32 s0, null ; encoding: [0x00,0x7c,0x43,0xbf] + +s_cmp_le_f32 s0, 0 +// GFX13: s_cmp_le_f32 s0, 0 ; encoding: [0x00,0x80,0x43,0xbf] + +s_cmp_le_f32 s0, 0.5 +// GFX13: s_cmp_le_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x43,0xbf] + +s_cmp_le_f32 s0, 0x12345678 +// GFX13: s_cmp_le_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x43,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_gt_f32 s0, s0 +// GFX13: s_cmp_gt_f32 s0, s0 ; encoding: [0x00,0x00,0x44,0xbf] + +s_cmp_gt_f32 s105, s0 +// GFX13: s_cmp_gt_f32 s105, s0 ; encoding: [0x69,0x00,0x44,0xbf] + +s_cmp_gt_f32 vcc_lo, s0 +// GFX13: s_cmp_gt_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x44,0xbf] + +s_cmp_gt_f32 exec_lo, s0 +// GFX13: s_cmp_gt_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x44,0xbf] + +s_cmp_gt_f32 m0, s0 +// GFX13: s_cmp_gt_f32 m0, s0 ; encoding: [0x7d,0x00,0x44,0xbf] + +s_cmp_gt_f32 null, s0 +// GFX13: s_cmp_gt_f32 null, s0 ; encoding: [0x7c,0x00,0x44,0xbf] + +s_cmp_gt_f32 0, s0 +// GFX13: s_cmp_gt_f32 0, s0 ; encoding: [0x80,0x00,0x44,0xbf] + +s_cmp_gt_f32 0.5, s0 +// GFX13: s_cmp_gt_f32 0.5, s0 ; encoding: [0xf0,0x00,0x44,0xbf] + +s_cmp_gt_f32 0x12345678, s0 +// GFX13: s_cmp_gt_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x44,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_gt_f32 s0, s105 +// GFX13: s_cmp_gt_f32 s0, s105 ; encoding: [0x00,0x69,0x44,0xbf] + +s_cmp_gt_f32 s0, vcc_lo +// GFX13: s_cmp_gt_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x44,0xbf] + +s_cmp_gt_f32 s0, exec_lo +// GFX13: s_cmp_gt_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x44,0xbf] + +s_cmp_gt_f32 s0, m0 +// GFX13: s_cmp_gt_f32 s0, m0 ; encoding: [0x00,0x7d,0x44,0xbf] + +s_cmp_gt_f32 s0, null +// GFX13: s_cmp_gt_f32 s0, null ; encoding: [0x00,0x7c,0x44,0xbf] + +s_cmp_gt_f32 s0, 0 +// GFX13: s_cmp_gt_f32 s0, 0 ; encoding: [0x00,0x80,0x44,0xbf] + +s_cmp_gt_f32 s0, 0.5 +// GFX13: s_cmp_gt_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x44,0xbf] + +s_cmp_gt_f32 s0, 0x12345678 +// GFX13: s_cmp_gt_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x44,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lg_f32 s0, s0 +// GFX13: s_cmp_lg_f32 s0, s0 ; encoding: [0x00,0x00,0x45,0xbf] + +s_cmp_lg_f32 s105, s0 +// GFX13: s_cmp_lg_f32 s105, s0 ; encoding: [0x69,0x00,0x45,0xbf] + +s_cmp_lg_f32 vcc_lo, s0 +// GFX13: s_cmp_lg_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x45,0xbf] + +s_cmp_lg_f32 exec_lo, s0 +// GFX13: s_cmp_lg_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x45,0xbf] + +s_cmp_lg_f32 m0, s0 +// GFX13: s_cmp_lg_f32 m0, s0 ; encoding: [0x7d,0x00,0x45,0xbf] + +s_cmp_lg_f32 null, s0 +// GFX13: s_cmp_lg_f32 null, s0 ; encoding: [0x7c,0x00,0x45,0xbf] + +s_cmp_lg_f32 0, s0 +// GFX13: s_cmp_lg_f32 0, s0 ; encoding: [0x80,0x00,0x45,0xbf] + +s_cmp_lg_f32 0.5, s0 +// GFX13: s_cmp_lg_f32 0.5, s0 ; encoding: [0xf0,0x00,0x45,0xbf] + +s_cmp_lg_f32 0x12345678, s0 +// GFX13: s_cmp_lg_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x45,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lg_f32 s0, s105 +// GFX13: s_cmp_lg_f32 s0, s105 ; encoding: [0x00,0x69,0x45,0xbf] + +s_cmp_lg_f32 s0, vcc_lo +// GFX13: s_cmp_lg_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x45,0xbf] + +s_cmp_lg_f32 s0, exec_lo +// GFX13: s_cmp_lg_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x45,0xbf] + +s_cmp_lg_f32 s0, m0 +// GFX13: s_cmp_lg_f32 s0, m0 ; encoding: [0x00,0x7d,0x45,0xbf] + +s_cmp_lg_f32 s0, null +// GFX13: s_cmp_lg_f32 s0, null ; encoding: [0x00,0x7c,0x45,0xbf] + +s_cmp_lg_f32 s0, 0 +// GFX13: s_cmp_lg_f32 s0, 0 ; encoding: [0x00,0x80,0x45,0xbf] + +s_cmp_lg_f32 s0, 0.5 +// GFX13: s_cmp_lg_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x45,0xbf] + +s_cmp_lg_f32 s0, 0x12345678 +// GFX13: s_cmp_lg_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x45,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_ge_f32 s0, s0 +// GFX13: s_cmp_ge_f32 s0, s0 ; encoding: [0x00,0x00,0x46,0xbf] + +s_cmp_ge_f32 s105, s0 +// GFX13: s_cmp_ge_f32 s105, s0 ; encoding: [0x69,0x00,0x46,0xbf] + +s_cmp_ge_f32 vcc_lo, s0 +// GFX13: s_cmp_ge_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x46,0xbf] + +s_cmp_ge_f32 exec_lo, s0 +// GFX13: s_cmp_ge_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x46,0xbf] + +s_cmp_ge_f32 m0, s0 +// GFX13: s_cmp_ge_f32 m0, s0 ; encoding: [0x7d,0x00,0x46,0xbf] + +s_cmp_ge_f32 null, s0 +// GFX13: s_cmp_ge_f32 null, s0 ; encoding: [0x7c,0x00,0x46,0xbf] + +s_cmp_ge_f32 0, s0 +// GFX13: s_cmp_ge_f32 0, s0 ; encoding: [0x80,0x00,0x46,0xbf] + +s_cmp_ge_f32 0.5, s0 +// GFX13: s_cmp_ge_f32 0.5, s0 ; encoding: [0xf0,0x00,0x46,0xbf] + +s_cmp_ge_f32 0x12345678, s0 +// GFX13: s_cmp_ge_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x46,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_ge_f32 s0, s105 +// GFX13: s_cmp_ge_f32 s0, s105 ; encoding: [0x00,0x69,0x46,0xbf] + +s_cmp_ge_f32 s0, vcc_lo +// GFX13: s_cmp_ge_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x46,0xbf] + +s_cmp_ge_f32 s0, exec_lo +// GFX13: s_cmp_ge_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x46,0xbf] + +s_cmp_ge_f32 s0, m0 +// GFX13: s_cmp_ge_f32 s0, m0 ; encoding: [0x00,0x7d,0x46,0xbf] + +s_cmp_ge_f32 s0, null +// GFX13: s_cmp_ge_f32 s0, null ; encoding: [0x00,0x7c,0x46,0xbf] + +s_cmp_ge_f32 s0, 0 +// GFX13: s_cmp_ge_f32 s0, 0 ; encoding: [0x00,0x80,0x46,0xbf] + +s_cmp_ge_f32 s0, 0.5 +// GFX13: s_cmp_ge_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x46,0xbf] + +s_cmp_ge_f32 s0, 0x12345678 +// GFX13: s_cmp_ge_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x46,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_o_f32 s0, s0 +// GFX13: s_cmp_o_f32 s0, s0 ; encoding: [0x00,0x00,0x47,0xbf] + +s_cmp_o_f32 s105, s0 +// GFX13: s_cmp_o_f32 s105, s0 ; encoding: [0x69,0x00,0x47,0xbf] + +s_cmp_o_f32 vcc_lo, s0 +// GFX13: s_cmp_o_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x47,0xbf] + +s_cmp_o_f32 exec_lo, s0 +// GFX13: s_cmp_o_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x47,0xbf] + +s_cmp_o_f32 m0, s0 +// GFX13: s_cmp_o_f32 m0, s0 ; encoding: [0x7d,0x00,0x47,0xbf] + +s_cmp_o_f32 null, s0 +// GFX13: s_cmp_o_f32 null, s0 ; encoding: [0x7c,0x00,0x47,0xbf] + +s_cmp_o_f32 0, s0 +// GFX13: s_cmp_o_f32 0, s0 ; encoding: [0x80,0x00,0x47,0xbf] + +s_cmp_o_f32 0.5, s0 +// GFX13: s_cmp_o_f32 0.5, s0 ; encoding: [0xf0,0x00,0x47,0xbf] + +s_cmp_o_f32 0x12345678, s0 +// GFX13: s_cmp_o_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x47,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_o_f32 s0, s105 +// GFX13: s_cmp_o_f32 s0, s105 ; encoding: [0x00,0x69,0x47,0xbf] + +s_cmp_o_f32 s0, vcc_lo +// GFX13: s_cmp_o_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x47,0xbf] + +s_cmp_o_f32 s0, exec_lo +// GFX13: s_cmp_o_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x47,0xbf] + +s_cmp_o_f32 s0, m0 +// GFX13: s_cmp_o_f32 s0, m0 ; encoding: [0x00,0x7d,0x47,0xbf] + +s_cmp_o_f32 s0, null +// GFX13: s_cmp_o_f32 s0, null ; encoding: [0x00,0x7c,0x47,0xbf] + +s_cmp_o_f32 s0, 0 +// GFX13: s_cmp_o_f32 s0, 0 ; encoding: [0x00,0x80,0x47,0xbf] + +s_cmp_o_f32 s0, 0.5 +// GFX13: s_cmp_o_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x47,0xbf] + +s_cmp_o_f32 s0, 0x12345678 +// GFX13: s_cmp_o_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x47,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_u_f32 s0, s0 +// GFX13: s_cmp_u_f32 s0, s0 ; encoding: [0x00,0x00,0x48,0xbf] + +s_cmp_u_f32 s105, s0 +// GFX13: s_cmp_u_f32 s105, s0 ; encoding: [0x69,0x00,0x48,0xbf] + +s_cmp_u_f32 vcc_lo, s0 +// GFX13: s_cmp_u_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x48,0xbf] + +s_cmp_u_f32 exec_lo, s0 +// GFX13: s_cmp_u_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x48,0xbf] + +s_cmp_u_f32 m0, s0 +// GFX13: s_cmp_u_f32 m0, s0 ; encoding: [0x7d,0x00,0x48,0xbf] + +s_cmp_u_f32 null, s0 +// GFX13: s_cmp_u_f32 null, s0 ; encoding: [0x7c,0x00,0x48,0xbf] + +s_cmp_u_f32 0, s0 +// GFX13: s_cmp_u_f32 0, s0 ; encoding: [0x80,0x00,0x48,0xbf] + +s_cmp_u_f32 0.5, s0 +// GFX13: s_cmp_u_f32 0.5, s0 ; encoding: [0xf0,0x00,0x48,0xbf] + +s_cmp_u_f32 0x12345678, s0 +// GFX13: s_cmp_u_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x48,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_u_f32 s0, s105 +// GFX13: s_cmp_u_f32 s0, s105 ; encoding: [0x00,0x69,0x48,0xbf] + +s_cmp_u_f32 s0, vcc_lo +// GFX13: s_cmp_u_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x48,0xbf] + +s_cmp_u_f32 s0, exec_lo +// GFX13: s_cmp_u_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x48,0xbf] + +s_cmp_u_f32 s0, m0 +// GFX13: s_cmp_u_f32 s0, m0 ; encoding: [0x00,0x7d,0x48,0xbf] + +s_cmp_u_f32 s0, null +// GFX13: s_cmp_u_f32 s0, null ; encoding: [0x00,0x7c,0x48,0xbf] + +s_cmp_u_f32 s0, 0 +// GFX13: s_cmp_u_f32 s0, 0 ; encoding: [0x00,0x80,0x48,0xbf] + +s_cmp_u_f32 s0, 0.5 +// GFX13: s_cmp_u_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x48,0xbf] + +s_cmp_u_f32 s0, 0x12345678 +// GFX13: s_cmp_u_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x48,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_nge_f32 s0, s0 +// GFX13: s_cmp_nge_f32 s0, s0 ; encoding: [0x00,0x00,0x49,0xbf] + +s_cmp_nge_f32 s105, s0 +// GFX13: s_cmp_nge_f32 s105, s0 ; encoding: [0x69,0x00,0x49,0xbf] + +s_cmp_nge_f32 vcc_lo, s0 +// GFX13: s_cmp_nge_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x49,0xbf] + +s_cmp_nge_f32 exec_lo, s0 +// GFX13: s_cmp_nge_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x49,0xbf] + +s_cmp_nge_f32 m0, s0 +// GFX13: s_cmp_nge_f32 m0, s0 ; encoding: [0x7d,0x00,0x49,0xbf] + +s_cmp_nge_f32 null, s0 +// GFX13: s_cmp_nge_f32 null, s0 ; encoding: [0x7c,0x00,0x49,0xbf] + +s_cmp_nge_f32 0, s0 +// GFX13: s_cmp_nge_f32 0, s0 ; encoding: [0x80,0x00,0x49,0xbf] + +s_cmp_nge_f32 0.5, s0 +// GFX13: s_cmp_nge_f32 0.5, s0 ; encoding: [0xf0,0x00,0x49,0xbf] + +s_cmp_nge_f32 0x12345678, s0 +// GFX13: s_cmp_nge_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x49,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_nge_f32 s0, s105 +// GFX13: s_cmp_nge_f32 s0, s105 ; encoding: [0x00,0x69,0x49,0xbf] + +s_cmp_nge_f32 s0, vcc_lo +// GFX13: s_cmp_nge_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x49,0xbf] + +s_cmp_nge_f32 s0, exec_lo +// GFX13: s_cmp_nge_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x49,0xbf] + +s_cmp_nge_f32 s0, m0 +// GFX13: s_cmp_nge_f32 s0, m0 ; encoding: [0x00,0x7d,0x49,0xbf] + +s_cmp_nge_f32 s0, null +// GFX13: s_cmp_nge_f32 s0, null ; encoding: [0x00,0x7c,0x49,0xbf] + +s_cmp_nge_f32 s0, 0 +// GFX13: s_cmp_nge_f32 s0, 0 ; encoding: [0x00,0x80,0x49,0xbf] + +s_cmp_nge_f32 s0, 0.5 +// GFX13: s_cmp_nge_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x49,0xbf] + +s_cmp_nge_f32 s0, 0x12345678 +// GFX13: s_cmp_nge_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x49,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_nlg_f32 s0, s0 +// GFX13: s_cmp_nlg_f32 s0, s0 ; encoding: [0x00,0x00,0x4a,0xbf] + +s_cmp_nlg_f32 s105, s0 +// GFX13: s_cmp_nlg_f32 s105, s0 ; encoding: [0x69,0x00,0x4a,0xbf] + +s_cmp_nlg_f32 vcc_lo, s0 +// GFX13: s_cmp_nlg_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x4a,0xbf] + +s_cmp_nlg_f32 exec_lo, s0 +// GFX13: s_cmp_nlg_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x4a,0xbf] + +s_cmp_nlg_f32 m0, s0 +// GFX13: s_cmp_nlg_f32 m0, s0 ; encoding: [0x7d,0x00,0x4a,0xbf] + +s_cmp_nlg_f32 null, s0 +// GFX13: s_cmp_nlg_f32 null, s0 ; encoding: [0x7c,0x00,0x4a,0xbf] + +s_cmp_nlg_f32 0, s0 +// GFX13: s_cmp_nlg_f32 0, s0 ; encoding: [0x80,0x00,0x4a,0xbf] + +s_cmp_nlg_f32 0.5, s0 +// GFX13: s_cmp_nlg_f32 0.5, s0 ; encoding: [0xf0,0x00,0x4a,0xbf] + +s_cmp_nlg_f32 0x12345678, s0 +// GFX13: s_cmp_nlg_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x4a,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_nlg_f32 s0, s105 +// GFX13: s_cmp_nlg_f32 s0, s105 ; encoding: [0x00,0x69,0x4a,0xbf] + +s_cmp_nlg_f32 s0, vcc_lo +// GFX13: s_cmp_nlg_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x4a,0xbf] + +s_cmp_nlg_f32 s0, exec_lo +// GFX13: s_cmp_nlg_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x4a,0xbf] + +s_cmp_nlg_f32 s0, m0 +// GFX13: s_cmp_nlg_f32 s0, m0 ; encoding: [0x00,0x7d,0x4a,0xbf] + +s_cmp_nlg_f32 s0, null +// GFX13: s_cmp_nlg_f32 s0, null ; encoding: [0x00,0x7c,0x4a,0xbf] + +s_cmp_nlg_f32 s0, 0 +// GFX13: s_cmp_nlg_f32 s0, 0 ; encoding: [0x00,0x80,0x4a,0xbf] + +s_cmp_nlg_f32 s0, 0.5 +// GFX13: s_cmp_nlg_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x4a,0xbf] + +s_cmp_nlg_f32 s0, 0x12345678 +// GFX13: s_cmp_nlg_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x4a,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_ngt_f32 s0, s0 +// GFX13: s_cmp_ngt_f32 s0, s0 ; encoding: [0x00,0x00,0x4b,0xbf] + +s_cmp_ngt_f32 s105, s0 +// GFX13: s_cmp_ngt_f32 s105, s0 ; encoding: [0x69,0x00,0x4b,0xbf] + +s_cmp_ngt_f32 vcc_lo, s0 +// GFX13: s_cmp_ngt_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x4b,0xbf] + +s_cmp_ngt_f32 exec_lo, s0 +// GFX13: s_cmp_ngt_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x4b,0xbf] + +s_cmp_ngt_f32 m0, s0 +// GFX13: s_cmp_ngt_f32 m0, s0 ; encoding: [0x7d,0x00,0x4b,0xbf] + +s_cmp_ngt_f32 null, s0 +// GFX13: s_cmp_ngt_f32 null, s0 ; encoding: [0x7c,0x00,0x4b,0xbf] + +s_cmp_ngt_f32 0, s0 +// GFX13: s_cmp_ngt_f32 0, s0 ; encoding: [0x80,0x00,0x4b,0xbf] + +s_cmp_ngt_f32 0.5, s0 +// GFX13: s_cmp_ngt_f32 0.5, s0 ; encoding: [0xf0,0x00,0x4b,0xbf] + +s_cmp_ngt_f32 0x12345678, s0 +// GFX13: s_cmp_ngt_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x4b,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_ngt_f32 s0, s105 +// GFX13: s_cmp_ngt_f32 s0, s105 ; encoding: [0x00,0x69,0x4b,0xbf] + +s_cmp_ngt_f32 s0, vcc_lo +// GFX13: s_cmp_ngt_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x4b,0xbf] + +s_cmp_ngt_f32 s0, exec_lo +// GFX13: s_cmp_ngt_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x4b,0xbf] + +s_cmp_ngt_f32 s0, m0 +// GFX13: s_cmp_ngt_f32 s0, m0 ; encoding: [0x00,0x7d,0x4b,0xbf] + +s_cmp_ngt_f32 s0, null +// GFX13: s_cmp_ngt_f32 s0, null ; encoding: [0x00,0x7c,0x4b,0xbf] + +s_cmp_ngt_f32 s0, 0 +// GFX13: s_cmp_ngt_f32 s0, 0 ; encoding: [0x00,0x80,0x4b,0xbf] + +s_cmp_ngt_f32 s0, 0.5 +// GFX13: s_cmp_ngt_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x4b,0xbf] + +s_cmp_ngt_f32 s0, 0x12345678 +// GFX13: s_cmp_ngt_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x4b,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_nle_f32 s0, s0 +// GFX13: s_cmp_nle_f32 s0, s0 ; encoding: [0x00,0x00,0x4c,0xbf] + +s_cmp_nle_f32 s105, s0 +// GFX13: s_cmp_nle_f32 s105, s0 ; encoding: [0x69,0x00,0x4c,0xbf] + +s_cmp_nle_f32 vcc_lo, s0 +// GFX13: s_cmp_nle_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x4c,0xbf] + +s_cmp_nle_f32 exec_lo, s0 +// GFX13: s_cmp_nle_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x4c,0xbf] + +s_cmp_nle_f32 m0, s0 +// GFX13: s_cmp_nle_f32 m0, s0 ; encoding: [0x7d,0x00,0x4c,0xbf] + +s_cmp_nle_f32 null, s0 +// GFX13: s_cmp_nle_f32 null, s0 ; encoding: [0x7c,0x00,0x4c,0xbf] + +s_cmp_nle_f32 0, s0 +// GFX13: s_cmp_nle_f32 0, s0 ; encoding: [0x80,0x00,0x4c,0xbf] + +s_cmp_nle_f32 0.5, s0 +// GFX13: s_cmp_nle_f32 0.5, s0 ; encoding: [0xf0,0x00,0x4c,0xbf] + +s_cmp_nle_f32 0x12345678, s0 +// GFX13: s_cmp_nle_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x4c,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_nle_f32 s0, s105 +// GFX13: s_cmp_nle_f32 s0, s105 ; encoding: [0x00,0x69,0x4c,0xbf] + +s_cmp_nle_f32 s0, vcc_lo +// GFX13: s_cmp_nle_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x4c,0xbf] + +s_cmp_nle_f32 s0, exec_lo +// GFX13: s_cmp_nle_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x4c,0xbf] + +s_cmp_nle_f32 s0, m0 +// GFX13: s_cmp_nle_f32 s0, m0 ; encoding: [0x00,0x7d,0x4c,0xbf] + +s_cmp_nle_f32 s0, null +// GFX13: s_cmp_nle_f32 s0, null ; encoding: [0x00,0x7c,0x4c,0xbf] + +s_cmp_nle_f32 s0, 0 +// GFX13: s_cmp_nle_f32 s0, 0 ; encoding: [0x00,0x80,0x4c,0xbf] + +s_cmp_nle_f32 s0, 0.5 +// GFX13: s_cmp_nle_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x4c,0xbf] + +s_cmp_nle_f32 s0, 0x12345678 +// GFX13: s_cmp_nle_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x4c,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_neq_f32 s0, s0 +// GFX13: s_cmp_neq_f32 s0, s0 ; encoding: [0x00,0x00,0x4d,0xbf] + +s_cmp_neq_f32 s105, s0 +// GFX13: s_cmp_neq_f32 s105, s0 ; encoding: [0x69,0x00,0x4d,0xbf] + +s_cmp_neq_f32 vcc_lo, s0 +// GFX13: s_cmp_neq_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x4d,0xbf] + +s_cmp_neq_f32 exec_lo, s0 +// GFX13: s_cmp_neq_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x4d,0xbf] + +s_cmp_neq_f32 m0, s0 +// GFX13: s_cmp_neq_f32 m0, s0 ; encoding: [0x7d,0x00,0x4d,0xbf] + +s_cmp_neq_f32 null, s0 +// GFX13: s_cmp_neq_f32 null, s0 ; encoding: [0x7c,0x00,0x4d,0xbf] + +s_cmp_neq_f32 0, s0 +// GFX13: s_cmp_neq_f32 0, s0 ; encoding: [0x80,0x00,0x4d,0xbf] + +s_cmp_neq_f32 0.5, s0 +// GFX13: s_cmp_neq_f32 0.5, s0 ; encoding: [0xf0,0x00,0x4d,0xbf] + +s_cmp_neq_f32 0x12345678, s0 +// GFX13: s_cmp_neq_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x4d,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_neq_f32 s0, s105 +// GFX13: s_cmp_neq_f32 s0, s105 ; encoding: [0x00,0x69,0x4d,0xbf] + +s_cmp_neq_f32 s0, vcc_lo +// GFX13: s_cmp_neq_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x4d,0xbf] + +s_cmp_neq_f32 s0, exec_lo +// GFX13: s_cmp_neq_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x4d,0xbf] + +s_cmp_neq_f32 s0, m0 +// GFX13: s_cmp_neq_f32 s0, m0 ; encoding: [0x00,0x7d,0x4d,0xbf] + +s_cmp_neq_f32 s0, null +// GFX13: s_cmp_neq_f32 s0, null ; encoding: [0x00,0x7c,0x4d,0xbf] + +s_cmp_neq_f32 s0, 0 +// GFX13: s_cmp_neq_f32 s0, 0 ; encoding: [0x00,0x80,0x4d,0xbf] + +s_cmp_neq_f32 s0, 0.5 +// GFX13: s_cmp_neq_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x4d,0xbf] + +s_cmp_neq_f32 s0, 0x12345678 +// GFX13: s_cmp_neq_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x4d,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_nlt_f32 s0, s0 +// GFX13: s_cmp_nlt_f32 s0, s0 ; encoding: [0x00,0x00,0x4e,0xbf] + +s_cmp_nlt_f32 s105, s0 +// GFX13: s_cmp_nlt_f32 s105, s0 ; encoding: [0x69,0x00,0x4e,0xbf] + +s_cmp_nlt_f32 vcc_lo, s0 +// GFX13: s_cmp_nlt_f32 vcc_lo, s0 ; encoding: [0x6a,0x00,0x4e,0xbf] + +s_cmp_nlt_f32 exec_lo, s0 +// GFX13: s_cmp_nlt_f32 exec_lo, s0 ; encoding: [0x7e,0x00,0x4e,0xbf] + +s_cmp_nlt_f32 m0, s0 +// GFX13: s_cmp_nlt_f32 m0, s0 ; encoding: [0x7d,0x00,0x4e,0xbf] + +s_cmp_nlt_f32 null, s0 +// GFX13: s_cmp_nlt_f32 null, s0 ; encoding: [0x7c,0x00,0x4e,0xbf] + +s_cmp_nlt_f32 0, s0 +// GFX13: s_cmp_nlt_f32 0, s0 ; encoding: [0x80,0x00,0x4e,0xbf] + +s_cmp_nlt_f32 0.5, s0 +// GFX13: s_cmp_nlt_f32 0.5, s0 ; encoding: [0xf0,0x00,0x4e,0xbf] + +s_cmp_nlt_f32 0x12345678, s0 +// GFX13: s_cmp_nlt_f32 0x12345678, s0 ; encoding: [0xff,0x00,0x4e,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_nlt_f32 s0, s105 +// GFX13: s_cmp_nlt_f32 s0, s105 ; encoding: [0x00,0x69,0x4e,0xbf] + +s_cmp_nlt_f32 s0, vcc_lo +// GFX13: s_cmp_nlt_f32 s0, vcc_lo ; encoding: [0x00,0x6a,0x4e,0xbf] + +s_cmp_nlt_f32 s0, exec_lo +// GFX13: s_cmp_nlt_f32 s0, exec_lo ; encoding: [0x00,0x7e,0x4e,0xbf] + +s_cmp_nlt_f32 s0, m0 +// GFX13: s_cmp_nlt_f32 s0, m0 ; encoding: [0x00,0x7d,0x4e,0xbf] + +s_cmp_nlt_f32 s0, null +// GFX13: s_cmp_nlt_f32 s0, null ; encoding: [0x00,0x7c,0x4e,0xbf] + +s_cmp_nlt_f32 s0, 0 +// GFX13: s_cmp_nlt_f32 s0, 0 ; encoding: [0x00,0x80,0x4e,0xbf] + +s_cmp_nlt_f32 s0, 0.5 +// GFX13: s_cmp_nlt_f32 s0, 0.5 ; encoding: [0x00,0xf0,0x4e,0xbf] + +s_cmp_nlt_f32 s0, 0x12345678 +// GFX13: s_cmp_nlt_f32 s0, 0x12345678 ; encoding: [0x00,0xff,0x4e,0xbf,0x78,0x56,0x34,0x12] + +s_cmp_lt_f16 s0, s0 +// GFX13: s_cmp_lt_f16 s0, s0 ; encoding: [0x00,0x00,0x51,0xbf] + +s_cmp_lt_f16 s105, s0 +// GFX13: s_cmp_lt_f16 s105, s0 ; encoding: [0x69,0x00,0x51,0xbf] + +s_cmp_lt_f16 vcc_lo, s0 +// GFX13: s_cmp_lt_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x51,0xbf] + +s_cmp_lt_f16 exec_lo, s0 +// GFX13: s_cmp_lt_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x51,0xbf] + +s_cmp_lt_f16 m0, s0 +// GFX13: s_cmp_lt_f16 m0, s0 ; encoding: [0x7d,0x00,0x51,0xbf] + +s_cmp_lt_f16 null, s0 +// GFX13: s_cmp_lt_f16 null, s0 ; encoding: [0x7c,0x00,0x51,0xbf] + +s_cmp_lt_f16 0, s0 +// GFX13: s_cmp_lt_f16 0, s0 ; encoding: [0x80,0x00,0x51,0xbf] + +s_cmp_lt_f16 0.5, s0 +// GFX13-ASM: s_cmp_lt_f16 0.5, s0 ; encoding: [0xf0,0x00,0x51,0xbf] +// GFX13-DIS: s_cmp_lt_f16 0x3800, s0 ; encoding: [0xff,0x00,0x51,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_lt_f16 0x1234, s0 +// GFX13: s_cmp_lt_f16 0x1234, s0 ; encoding: [0xff,0x00,0x51,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_lt_f16 s0, s105 +// GFX13: s_cmp_lt_f16 s0, s105 ; encoding: [0x00,0x69,0x51,0xbf] + +s_cmp_lt_f16 s0, vcc_lo +// GFX13: s_cmp_lt_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x51,0xbf] + +s_cmp_lt_f16 s0, exec_lo +// GFX13: s_cmp_lt_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x51,0xbf] + +s_cmp_lt_f16 s0, m0 +// GFX13: s_cmp_lt_f16 s0, m0 ; encoding: [0x00,0x7d,0x51,0xbf] + +s_cmp_lt_f16 s0, null +// GFX13: s_cmp_lt_f16 s0, null ; encoding: [0x00,0x7c,0x51,0xbf] + +s_cmp_lt_f16 s0, 0 +// GFX13: s_cmp_lt_f16 s0, 0 ; encoding: [0x00,0x80,0x51,0xbf] + +s_cmp_lt_f16 s0, 0.5 +// GFX13-ASM: s_cmp_lt_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x51,0xbf] +// GFX13-DIS: s_cmp_lt_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x51,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_lt_f16 s0, 0x1234 +// GFX13: s_cmp_lt_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x51,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_eq_f16 s0, s0 +// GFX13: s_cmp_eq_f16 s0, s0 ; encoding: [0x00,0x00,0x52,0xbf] + +s_cmp_eq_f16 s105, s0 +// GFX13: s_cmp_eq_f16 s105, s0 ; encoding: [0x69,0x00,0x52,0xbf] + +s_cmp_eq_f16 vcc_lo, s0 +// GFX13: s_cmp_eq_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x52,0xbf] + +s_cmp_eq_f16 exec_lo, s0 +// GFX13: s_cmp_eq_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x52,0xbf] + +s_cmp_eq_f16 m0, s0 +// GFX13: s_cmp_eq_f16 m0, s0 ; encoding: [0x7d,0x00,0x52,0xbf] + +s_cmp_eq_f16 null, s0 +// GFX13: s_cmp_eq_f16 null, s0 ; encoding: [0x7c,0x00,0x52,0xbf] + +s_cmp_eq_f16 0, s0 +// GFX13: s_cmp_eq_f16 0, s0 ; encoding: [0x80,0x00,0x52,0xbf] + +s_cmp_eq_f16 0.5, s0 +// GFX13-ASM: s_cmp_eq_f16 0.5, s0 ; encoding: [0xf0,0x00,0x52,0xbf] +// GFX13-DIS: s_cmp_eq_f16 0x3800, s0 ; encoding: [0xff,0x00,0x52,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_eq_f16 0x1234, s0 +// GFX13: s_cmp_eq_f16 0x1234, s0 ; encoding: [0xff,0x00,0x52,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_eq_f16 s0, s105 +// GFX13: s_cmp_eq_f16 s0, s105 ; encoding: [0x00,0x69,0x52,0xbf] + +s_cmp_eq_f16 s0, vcc_lo +// GFX13: s_cmp_eq_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x52,0xbf] + +s_cmp_eq_f16 s0, exec_lo +// GFX13: s_cmp_eq_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x52,0xbf] + +s_cmp_eq_f16 s0, m0 +// GFX13: s_cmp_eq_f16 s0, m0 ; encoding: [0x00,0x7d,0x52,0xbf] + +s_cmp_eq_f16 s0, null +// GFX13: s_cmp_eq_f16 s0, null ; encoding: [0x00,0x7c,0x52,0xbf] + +s_cmp_eq_f16 s0, 0 +// GFX13: s_cmp_eq_f16 s0, 0 ; encoding: [0x00,0x80,0x52,0xbf] + +s_cmp_eq_f16 s0, 0.5 +// GFX13-ASM: s_cmp_eq_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x52,0xbf] +// GFX13-DIS: s_cmp_eq_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x52,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_eq_f16 s0, 0x1234 +// GFX13: s_cmp_eq_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x52,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_le_f16 s0, s0 +// GFX13: s_cmp_le_f16 s0, s0 ; encoding: [0x00,0x00,0x53,0xbf] + +s_cmp_le_f16 s105, s0 +// GFX13: s_cmp_le_f16 s105, s0 ; encoding: [0x69,0x00,0x53,0xbf] + +s_cmp_le_f16 vcc_lo, s0 +// GFX13: s_cmp_le_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x53,0xbf] + +s_cmp_le_f16 exec_lo, s0 +// GFX13: s_cmp_le_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x53,0xbf] + +s_cmp_le_f16 m0, s0 +// GFX13: s_cmp_le_f16 m0, s0 ; encoding: [0x7d,0x00,0x53,0xbf] + +s_cmp_le_f16 null, s0 +// GFX13: s_cmp_le_f16 null, s0 ; encoding: [0x7c,0x00,0x53,0xbf] + +s_cmp_le_f16 0, s0 +// GFX13: s_cmp_le_f16 0, s0 ; encoding: [0x80,0x00,0x53,0xbf] + +s_cmp_le_f16 0.5, s0 +// GFX13-ASM: s_cmp_le_f16 0.5, s0 ; encoding: [0xf0,0x00,0x53,0xbf] +// GFX13-DIS: s_cmp_le_f16 0x3800, s0 ; encoding: [0xff,0x00,0x53,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_le_f16 0x1234, s0 +// GFX13: s_cmp_le_f16 0x1234, s0 ; encoding: [0xff,0x00,0x53,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_le_f16 s0, s105 +// GFX13: s_cmp_le_f16 s0, s105 ; encoding: [0x00,0x69,0x53,0xbf] + +s_cmp_le_f16 s0, vcc_lo +// GFX13: s_cmp_le_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x53,0xbf] + +s_cmp_le_f16 s0, exec_lo +// GFX13: s_cmp_le_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x53,0xbf] + +s_cmp_le_f16 s0, m0 +// GFX13: s_cmp_le_f16 s0, m0 ; encoding: [0x00,0x7d,0x53,0xbf] + +s_cmp_le_f16 s0, null +// GFX13: s_cmp_le_f16 s0, null ; encoding: [0x00,0x7c,0x53,0xbf] + +s_cmp_le_f16 s0, 0 +// GFX13: s_cmp_le_f16 s0, 0 ; encoding: [0x00,0x80,0x53,0xbf] + +s_cmp_le_f16 s0, 0.5 +// GFX13-ASM: s_cmp_le_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x53,0xbf] +// GFX13-DIS: s_cmp_le_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x53,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_le_f16 s0, 0x1234 +// GFX13: s_cmp_le_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x53,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_gt_f16 s0, s0 +// GFX13: s_cmp_gt_f16 s0, s0 ; encoding: [0x00,0x00,0x54,0xbf] + +s_cmp_gt_f16 s105, s0 +// GFX13: s_cmp_gt_f16 s105, s0 ; encoding: [0x69,0x00,0x54,0xbf] + +s_cmp_gt_f16 vcc_lo, s0 +// GFX13: s_cmp_gt_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x54,0xbf] + +s_cmp_gt_f16 exec_lo, s0 +// GFX13: s_cmp_gt_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x54,0xbf] + +s_cmp_gt_f16 m0, s0 +// GFX13: s_cmp_gt_f16 m0, s0 ; encoding: [0x7d,0x00,0x54,0xbf] + +s_cmp_gt_f16 null, s0 +// GFX13: s_cmp_gt_f16 null, s0 ; encoding: [0x7c,0x00,0x54,0xbf] + +s_cmp_gt_f16 0, s0 +// GFX13: s_cmp_gt_f16 0, s0 ; encoding: [0x80,0x00,0x54,0xbf] + +s_cmp_gt_f16 0.5, s0 +// GFX13-ASM: s_cmp_gt_f16 0.5, s0 ; encoding: [0xf0,0x00,0x54,0xbf] +// GFX13-DIS: s_cmp_gt_f16 0x3800, s0 ; encoding: [0xff,0x00,0x54,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_gt_f16 0x1234, s0 +// GFX13: s_cmp_gt_f16 0x1234, s0 ; encoding: [0xff,0x00,0x54,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_gt_f16 s0, s105 +// GFX13: s_cmp_gt_f16 s0, s105 ; encoding: [0x00,0x69,0x54,0xbf] + +s_cmp_gt_f16 s0, vcc_lo +// GFX13: s_cmp_gt_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x54,0xbf] + +s_cmp_gt_f16 s0, exec_lo +// GFX13: s_cmp_gt_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x54,0xbf] + +s_cmp_gt_f16 s0, m0 +// GFX13: s_cmp_gt_f16 s0, m0 ; encoding: [0x00,0x7d,0x54,0xbf] + +s_cmp_gt_f16 s0, null +// GFX13: s_cmp_gt_f16 s0, null ; encoding: [0x00,0x7c,0x54,0xbf] + +s_cmp_gt_f16 s0, 0 +// GFX13: s_cmp_gt_f16 s0, 0 ; encoding: [0x00,0x80,0x54,0xbf] + +s_cmp_gt_f16 s0, 0.5 +// GFX13-ASM: s_cmp_gt_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x54,0xbf] +// GFX13-DIS: s_cmp_gt_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x54,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_gt_f16 s0, 0x1234 +// GFX13: s_cmp_gt_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x54,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_lg_f16 s0, s0 +// GFX13: s_cmp_lg_f16 s0, s0 ; encoding: [0x00,0x00,0x55,0xbf] + +s_cmp_lg_f16 s105, s0 +// GFX13: s_cmp_lg_f16 s105, s0 ; encoding: [0x69,0x00,0x55,0xbf] + +s_cmp_lg_f16 vcc_lo, s0 +// GFX13: s_cmp_lg_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x55,0xbf] + +s_cmp_lg_f16 exec_lo, s0 +// GFX13: s_cmp_lg_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x55,0xbf] + +s_cmp_lg_f16 m0, s0 +// GFX13: s_cmp_lg_f16 m0, s0 ; encoding: [0x7d,0x00,0x55,0xbf] + +s_cmp_lg_f16 null, s0 +// GFX13: s_cmp_lg_f16 null, s0 ; encoding: [0x7c,0x00,0x55,0xbf] + +s_cmp_lg_f16 0, s0 +// GFX13: s_cmp_lg_f16 0, s0 ; encoding: [0x80,0x00,0x55,0xbf] + +s_cmp_lg_f16 0.5, s0 +// GFX13-ASM: s_cmp_lg_f16 0.5, s0 ; encoding: [0xf0,0x00,0x55,0xbf] +// GFX13-DIS: s_cmp_lg_f16 0x3800, s0 ; encoding: [0xff,0x00,0x55,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_lg_f16 0x1234, s0 +// GFX13: s_cmp_lg_f16 0x1234, s0 ; encoding: [0xff,0x00,0x55,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_lg_f16 s0, s105 +// GFX13: s_cmp_lg_f16 s0, s105 ; encoding: [0x00,0x69,0x55,0xbf] + +s_cmp_lg_f16 s0, vcc_lo +// GFX13: s_cmp_lg_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x55,0xbf] + +s_cmp_lg_f16 s0, exec_lo +// GFX13: s_cmp_lg_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x55,0xbf] + +s_cmp_lg_f16 s0, m0 +// GFX13: s_cmp_lg_f16 s0, m0 ; encoding: [0x00,0x7d,0x55,0xbf] + +s_cmp_lg_f16 s0, null +// GFX13: s_cmp_lg_f16 s0, null ; encoding: [0x00,0x7c,0x55,0xbf] + +s_cmp_lg_f16 s0, 0 +// GFX13: s_cmp_lg_f16 s0, 0 ; encoding: [0x00,0x80,0x55,0xbf] + +s_cmp_lg_f16 s0, 0.5 +// GFX13-ASM: s_cmp_lg_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x55,0xbf] +// GFX13-DIS: s_cmp_lg_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x55,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_lg_f16 s0, 0x1234 +// GFX13: s_cmp_lg_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x55,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_ge_f16 s0, s0 +// GFX13: s_cmp_ge_f16 s0, s0 ; encoding: [0x00,0x00,0x56,0xbf] + +s_cmp_ge_f16 s105, s0 +// GFX13: s_cmp_ge_f16 s105, s0 ; encoding: [0x69,0x00,0x56,0xbf] + +s_cmp_ge_f16 vcc_lo, s0 +// GFX13: s_cmp_ge_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x56,0xbf] + +s_cmp_ge_f16 exec_lo, s0 +// GFX13: s_cmp_ge_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x56,0xbf] + +s_cmp_ge_f16 m0, s0 +// GFX13: s_cmp_ge_f16 m0, s0 ; encoding: [0x7d,0x00,0x56,0xbf] + +s_cmp_ge_f16 null, s0 +// GFX13: s_cmp_ge_f16 null, s0 ; encoding: [0x7c,0x00,0x56,0xbf] + +s_cmp_ge_f16 0, s0 +// GFX13: s_cmp_ge_f16 0, s0 ; encoding: [0x80,0x00,0x56,0xbf] + +s_cmp_ge_f16 0.5, s0 +// GFX13-ASM: s_cmp_ge_f16 0.5, s0 ; encoding: [0xf0,0x00,0x56,0xbf] +// GFX13-DIS: s_cmp_ge_f16 0x3800, s0 ; encoding: [0xff,0x00,0x56,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_ge_f16 0x1234, s0 +// GFX13: s_cmp_ge_f16 0x1234, s0 ; encoding: [0xff,0x00,0x56,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_ge_f16 s0, s105 +// GFX13: s_cmp_ge_f16 s0, s105 ; encoding: [0x00,0x69,0x56,0xbf] + +s_cmp_ge_f16 s0, vcc_lo +// GFX13: s_cmp_ge_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x56,0xbf] + +s_cmp_ge_f16 s0, exec_lo +// GFX13: s_cmp_ge_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x56,0xbf] + +s_cmp_ge_f16 s0, m0 +// GFX13: s_cmp_ge_f16 s0, m0 ; encoding: [0x00,0x7d,0x56,0xbf] + +s_cmp_ge_f16 s0, null +// GFX13: s_cmp_ge_f16 s0, null ; encoding: [0x00,0x7c,0x56,0xbf] + +s_cmp_ge_f16 s0, 0 +// GFX13: s_cmp_ge_f16 s0, 0 ; encoding: [0x00,0x80,0x56,0xbf] + +s_cmp_ge_f16 s0, 0.5 +// GFX13-ASM: s_cmp_ge_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x56,0xbf] +// GFX13-DIS: s_cmp_ge_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x56,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_ge_f16 s0, 0x1234 +// GFX13: s_cmp_ge_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x56,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_o_f16 s0, s0 +// GFX13: s_cmp_o_f16 s0, s0 ; encoding: [0x00,0x00,0x57,0xbf] + +s_cmp_o_f16 s105, s0 +// GFX13: s_cmp_o_f16 s105, s0 ; encoding: [0x69,0x00,0x57,0xbf] + +s_cmp_o_f16 vcc_lo, s0 +// GFX13: s_cmp_o_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x57,0xbf] + +s_cmp_o_f16 exec_lo, s0 +// GFX13: s_cmp_o_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x57,0xbf] + +s_cmp_o_f16 m0, s0 +// GFX13: s_cmp_o_f16 m0, s0 ; encoding: [0x7d,0x00,0x57,0xbf] + +s_cmp_o_f16 null, s0 +// GFX13: s_cmp_o_f16 null, s0 ; encoding: [0x7c,0x00,0x57,0xbf] + +s_cmp_o_f16 0, s0 +// GFX13: s_cmp_o_f16 0, s0 ; encoding: [0x80,0x00,0x57,0xbf] + +s_cmp_o_f16 0.5, s0 +// GFX13-ASM: s_cmp_o_f16 0.5, s0 ; encoding: [0xf0,0x00,0x57,0xbf] +// GFX13-DIS: s_cmp_o_f16 0x3800, s0 ; encoding: [0xff,0x00,0x57,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_o_f16 0x1234, s0 +// GFX13: s_cmp_o_f16 0x1234, s0 ; encoding: [0xff,0x00,0x57,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_o_f16 s0, s105 +// GFX13: s_cmp_o_f16 s0, s105 ; encoding: [0x00,0x69,0x57,0xbf] + +s_cmp_o_f16 s0, vcc_lo +// GFX13: s_cmp_o_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x57,0xbf] + +s_cmp_o_f16 s0, exec_lo +// GFX13: s_cmp_o_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x57,0xbf] + +s_cmp_o_f16 s0, m0 +// GFX13: s_cmp_o_f16 s0, m0 ; encoding: [0x00,0x7d,0x57,0xbf] + +s_cmp_o_f16 s0, null +// GFX13: s_cmp_o_f16 s0, null ; encoding: [0x00,0x7c,0x57,0xbf] + +s_cmp_o_f16 s0, 0 +// GFX13: s_cmp_o_f16 s0, 0 ; encoding: [0x00,0x80,0x57,0xbf] + +s_cmp_o_f16 s0, 0.5 +// GFX13-ASM: s_cmp_o_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x57,0xbf] +// GFX13-DIS: s_cmp_o_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x57,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_o_f16 s0, 0x1234 +// GFX13: s_cmp_o_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x57,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_u_f16 s0, s0 +// GFX13: s_cmp_u_f16 s0, s0 ; encoding: [0x00,0x00,0x58,0xbf] + +s_cmp_u_f16 s105, s0 +// GFX13: s_cmp_u_f16 s105, s0 ; encoding: [0x69,0x00,0x58,0xbf] + +s_cmp_u_f16 vcc_lo, s0 +// GFX13: s_cmp_u_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x58,0xbf] + +s_cmp_u_f16 exec_lo, s0 +// GFX13: s_cmp_u_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x58,0xbf] + +s_cmp_u_f16 m0, s0 +// GFX13: s_cmp_u_f16 m0, s0 ; encoding: [0x7d,0x00,0x58,0xbf] + +s_cmp_u_f16 null, s0 +// GFX13: s_cmp_u_f16 null, s0 ; encoding: [0x7c,0x00,0x58,0xbf] + +s_cmp_u_f16 0, s0 +// GFX13: s_cmp_u_f16 0, s0 ; encoding: [0x80,0x00,0x58,0xbf] + +s_cmp_u_f16 0.5, s0 +// GFX13-ASM: s_cmp_u_f16 0.5, s0 ; encoding: [0xf0,0x00,0x58,0xbf] +// GFX13-DIS: s_cmp_u_f16 0x3800, s0 ; encoding: [0xff,0x00,0x58,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_u_f16 0x1234, s0 +// GFX13: s_cmp_u_f16 0x1234, s0 ; encoding: [0xff,0x00,0x58,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_u_f16 s0, s105 +// GFX13: s_cmp_u_f16 s0, s105 ; encoding: [0x00,0x69,0x58,0xbf] + +s_cmp_u_f16 s0, vcc_lo +// GFX13: s_cmp_u_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x58,0xbf] + +s_cmp_u_f16 s0, exec_lo +// GFX13: s_cmp_u_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x58,0xbf] + +s_cmp_u_f16 s0, m0 +// GFX13: s_cmp_u_f16 s0, m0 ; encoding: [0x00,0x7d,0x58,0xbf] + +s_cmp_u_f16 s0, null +// GFX13: s_cmp_u_f16 s0, null ; encoding: [0x00,0x7c,0x58,0xbf] + +s_cmp_u_f16 s0, 0 +// GFX13: s_cmp_u_f16 s0, 0 ; encoding: [0x00,0x80,0x58,0xbf] + +s_cmp_u_f16 s0, 0.5 +// GFX13-ASM: s_cmp_u_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x58,0xbf] +// GFX13-DIS: s_cmp_u_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x58,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_u_f16 s0, 0x1234 +// GFX13: s_cmp_u_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x58,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_nge_f16 s0, s0 +// GFX13: s_cmp_nge_f16 s0, s0 ; encoding: [0x00,0x00,0x59,0xbf] + +s_cmp_nge_f16 s105, s0 +// GFX13: s_cmp_nge_f16 s105, s0 ; encoding: [0x69,0x00,0x59,0xbf] + +s_cmp_nge_f16 vcc_lo, s0 +// GFX13: s_cmp_nge_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x59,0xbf] + +s_cmp_nge_f16 exec_lo, s0 +// GFX13: s_cmp_nge_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x59,0xbf] + +s_cmp_nge_f16 m0, s0 +// GFX13: s_cmp_nge_f16 m0, s0 ; encoding: [0x7d,0x00,0x59,0xbf] + +s_cmp_nge_f16 null, s0 +// GFX13: s_cmp_nge_f16 null, s0 ; encoding: [0x7c,0x00,0x59,0xbf] + +s_cmp_nge_f16 0, s0 +// GFX13: s_cmp_nge_f16 0, s0 ; encoding: [0x80,0x00,0x59,0xbf] + +s_cmp_nge_f16 0.5, s0 +// GFX13-ASM: s_cmp_nge_f16 0.5, s0 ; encoding: [0xf0,0x00,0x59,0xbf] +// GFX13-DIS: s_cmp_nge_f16 0x3800, s0 ; encoding: [0xff,0x00,0x59,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nge_f16 0x1234, s0 +// GFX13: s_cmp_nge_f16 0x1234, s0 ; encoding: [0xff,0x00,0x59,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_nge_f16 s0, s105 +// GFX13: s_cmp_nge_f16 s0, s105 ; encoding: [0x00,0x69,0x59,0xbf] + +s_cmp_nge_f16 s0, vcc_lo +// GFX13: s_cmp_nge_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x59,0xbf] + +s_cmp_nge_f16 s0, exec_lo +// GFX13: s_cmp_nge_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x59,0xbf] + +s_cmp_nge_f16 s0, m0 +// GFX13: s_cmp_nge_f16 s0, m0 ; encoding: [0x00,0x7d,0x59,0xbf] + +s_cmp_nge_f16 s0, null +// GFX13: s_cmp_nge_f16 s0, null ; encoding: [0x00,0x7c,0x59,0xbf] + +s_cmp_nge_f16 s0, 0 +// GFX13: s_cmp_nge_f16 s0, 0 ; encoding: [0x00,0x80,0x59,0xbf] + +s_cmp_nge_f16 s0, 0.5 +// GFX13-ASM: s_cmp_nge_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x59,0xbf] +// GFX13-DIS: s_cmp_nge_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x59,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nge_f16 s0, 0x1234 +// GFX13: s_cmp_nge_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x59,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_nlg_f16 s0, s0 +// GFX13: s_cmp_nlg_f16 s0, s0 ; encoding: [0x00,0x00,0x5a,0xbf] + +s_cmp_nlg_f16 s105, s0 +// GFX13: s_cmp_nlg_f16 s105, s0 ; encoding: [0x69,0x00,0x5a,0xbf] + +s_cmp_nlg_f16 vcc_lo, s0 +// GFX13: s_cmp_nlg_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x5a,0xbf] + +s_cmp_nlg_f16 exec_lo, s0 +// GFX13: s_cmp_nlg_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x5a,0xbf] + +s_cmp_nlg_f16 m0, s0 +// GFX13: s_cmp_nlg_f16 m0, s0 ; encoding: [0x7d,0x00,0x5a,0xbf] + +s_cmp_nlg_f16 null, s0 +// GFX13: s_cmp_nlg_f16 null, s0 ; encoding: [0x7c,0x00,0x5a,0xbf] + +s_cmp_nlg_f16 0, s0 +// GFX13: s_cmp_nlg_f16 0, s0 ; encoding: [0x80,0x00,0x5a,0xbf] + +s_cmp_nlg_f16 0.5, s0 +// GFX13-ASM: s_cmp_nlg_f16 0.5, s0 ; encoding: [0xf0,0x00,0x5a,0xbf] +// GFX13-DIS: s_cmp_nlg_f16 0x3800, s0 ; encoding: [0xff,0x00,0x5a,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nlg_f16 0x1234, s0 +// GFX13: s_cmp_nlg_f16 0x1234, s0 ; encoding: [0xff,0x00,0x5a,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_nlg_f16 s0, s105 +// GFX13: s_cmp_nlg_f16 s0, s105 ; encoding: [0x00,0x69,0x5a,0xbf] + +s_cmp_nlg_f16 s0, vcc_lo +// GFX13: s_cmp_nlg_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x5a,0xbf] + +s_cmp_nlg_f16 s0, exec_lo +// GFX13: s_cmp_nlg_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x5a,0xbf] + +s_cmp_nlg_f16 s0, m0 +// GFX13: s_cmp_nlg_f16 s0, m0 ; encoding: [0x00,0x7d,0x5a,0xbf] + +s_cmp_nlg_f16 s0, null +// GFX13: s_cmp_nlg_f16 s0, null ; encoding: [0x00,0x7c,0x5a,0xbf] + +s_cmp_nlg_f16 s0, 0 +// GFX13: s_cmp_nlg_f16 s0, 0 ; encoding: [0x00,0x80,0x5a,0xbf] + +s_cmp_nlg_f16 s0, 0.5 +// GFX13-ASM: s_cmp_nlg_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x5a,0xbf] +// GFX13-DIS: s_cmp_nlg_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x5a,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nlg_f16 s0, 0x1234 +// GFX13: s_cmp_nlg_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x5a,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_ngt_f16 s0, s0 +// GFX13: s_cmp_ngt_f16 s0, s0 ; encoding: [0x00,0x00,0x5b,0xbf] + +s_cmp_ngt_f16 s105, s0 +// GFX13: s_cmp_ngt_f16 s105, s0 ; encoding: [0x69,0x00,0x5b,0xbf] + +s_cmp_ngt_f16 vcc_lo, s0 +// GFX13: s_cmp_ngt_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x5b,0xbf] + +s_cmp_ngt_f16 exec_lo, s0 +// GFX13: s_cmp_ngt_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x5b,0xbf] + +s_cmp_ngt_f16 m0, s0 +// GFX13: s_cmp_ngt_f16 m0, s0 ; encoding: [0x7d,0x00,0x5b,0xbf] + +s_cmp_ngt_f16 null, s0 +// GFX13: s_cmp_ngt_f16 null, s0 ; encoding: [0x7c,0x00,0x5b,0xbf] + +s_cmp_ngt_f16 0, s0 +// GFX13: s_cmp_ngt_f16 0, s0 ; encoding: [0x80,0x00,0x5b,0xbf] + +s_cmp_ngt_f16 0.5, s0 +// GFX13-ASM: s_cmp_ngt_f16 0.5, s0 ; encoding: [0xf0,0x00,0x5b,0xbf] +// GFX13-DIS: s_cmp_ngt_f16 0x3800, s0 ; encoding: [0xff,0x00,0x5b,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_ngt_f16 0x1234, s0 +// GFX13: s_cmp_ngt_f16 0x1234, s0 ; encoding: [0xff,0x00,0x5b,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_ngt_f16 s0, s105 +// GFX13: s_cmp_ngt_f16 s0, s105 ; encoding: [0x00,0x69,0x5b,0xbf] + +s_cmp_ngt_f16 s0, vcc_lo +// GFX13: s_cmp_ngt_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x5b,0xbf] + +s_cmp_ngt_f16 s0, exec_lo +// GFX13: s_cmp_ngt_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x5b,0xbf] + +s_cmp_ngt_f16 s0, m0 +// GFX13: s_cmp_ngt_f16 s0, m0 ; encoding: [0x00,0x7d,0x5b,0xbf] + +s_cmp_ngt_f16 s0, null +// GFX13: s_cmp_ngt_f16 s0, null ; encoding: [0x00,0x7c,0x5b,0xbf] + +s_cmp_ngt_f16 s0, 0 +// GFX13: s_cmp_ngt_f16 s0, 0 ; encoding: [0x00,0x80,0x5b,0xbf] + +s_cmp_ngt_f16 s0, 0.5 +// GFX13-ASM: s_cmp_ngt_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x5b,0xbf] +// GFX13-DIS: s_cmp_ngt_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x5b,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_ngt_f16 s0, 0x1234 +// GFX13: s_cmp_ngt_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x5b,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_nle_f16 s0, s0 +// GFX13: s_cmp_nle_f16 s0, s0 ; encoding: [0x00,0x00,0x5c,0xbf] + +s_cmp_nle_f16 s105, s0 +// GFX13: s_cmp_nle_f16 s105, s0 ; encoding: [0x69,0x00,0x5c,0xbf] + +s_cmp_nle_f16 vcc_lo, s0 +// GFX13: s_cmp_nle_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x5c,0xbf] + +s_cmp_nle_f16 exec_lo, s0 +// GFX13: s_cmp_nle_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x5c,0xbf] + +s_cmp_nle_f16 m0, s0 +// GFX13: s_cmp_nle_f16 m0, s0 ; encoding: [0x7d,0x00,0x5c,0xbf] + +s_cmp_nle_f16 null, s0 +// GFX13: s_cmp_nle_f16 null, s0 ; encoding: [0x7c,0x00,0x5c,0xbf] + +s_cmp_nle_f16 0, s0 +// GFX13: s_cmp_nle_f16 0, s0 ; encoding: [0x80,0x00,0x5c,0xbf] + +s_cmp_nle_f16 0.5, s0 +// GFX13-ASM: s_cmp_nle_f16 0.5, s0 ; encoding: [0xf0,0x00,0x5c,0xbf] +// GFX13-DIS: s_cmp_nle_f16 0x3800, s0 ; encoding: [0xff,0x00,0x5c,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nle_f16 0x1234, s0 +// GFX13: s_cmp_nle_f16 0x1234, s0 ; encoding: [0xff,0x00,0x5c,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_nle_f16 s0, s105 +// GFX13: s_cmp_nle_f16 s0, s105 ; encoding: [0x00,0x69,0x5c,0xbf] + +s_cmp_nle_f16 s0, vcc_lo +// GFX13: s_cmp_nle_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x5c,0xbf] + +s_cmp_nle_f16 s0, exec_lo +// GFX13: s_cmp_nle_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x5c,0xbf] + +s_cmp_nle_f16 s0, m0 +// GFX13: s_cmp_nle_f16 s0, m0 ; encoding: [0x00,0x7d,0x5c,0xbf] + +s_cmp_nle_f16 s0, null +// GFX13: s_cmp_nle_f16 s0, null ; encoding: [0x00,0x7c,0x5c,0xbf] + +s_cmp_nle_f16 s0, 0 +// GFX13: s_cmp_nle_f16 s0, 0 ; encoding: [0x00,0x80,0x5c,0xbf] + +s_cmp_nle_f16 s0, 0.5 +// GFX13-ASM: s_cmp_nle_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x5c,0xbf] +// GFX13-DIS: s_cmp_nle_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x5c,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nle_f16 s0, 0x1234 +// GFX13: s_cmp_nle_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x5c,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_neq_f16 s0, s0 +// GFX13: s_cmp_neq_f16 s0, s0 ; encoding: [0x00,0x00,0x5d,0xbf] + +s_cmp_neq_f16 s105, s0 +// GFX13: s_cmp_neq_f16 s105, s0 ; encoding: [0x69,0x00,0x5d,0xbf] + +s_cmp_neq_f16 vcc_lo, s0 +// GFX13: s_cmp_neq_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x5d,0xbf] + +s_cmp_neq_f16 exec_lo, s0 +// GFX13: s_cmp_neq_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x5d,0xbf] + +s_cmp_neq_f16 m0, s0 +// GFX13: s_cmp_neq_f16 m0, s0 ; encoding: [0x7d,0x00,0x5d,0xbf] + +s_cmp_neq_f16 null, s0 +// GFX13: s_cmp_neq_f16 null, s0 ; encoding: [0x7c,0x00,0x5d,0xbf] + +s_cmp_neq_f16 0, s0 +// GFX13: s_cmp_neq_f16 0, s0 ; encoding: [0x80,0x00,0x5d,0xbf] + +s_cmp_neq_f16 0.5, s0 +// GFX13-ASM: s_cmp_neq_f16 0.5, s0 ; encoding: [0xf0,0x00,0x5d,0xbf] +// GFX13-DIS: s_cmp_neq_f16 0x3800, s0 ; encoding: [0xff,0x00,0x5d,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_neq_f16 0x1234, s0 +// GFX13: s_cmp_neq_f16 0x1234, s0 ; encoding: [0xff,0x00,0x5d,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_neq_f16 s0, s105 +// GFX13: s_cmp_neq_f16 s0, s105 ; encoding: [0x00,0x69,0x5d,0xbf] + +s_cmp_neq_f16 s0, vcc_lo +// GFX13: s_cmp_neq_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x5d,0xbf] + +s_cmp_neq_f16 s0, exec_lo +// GFX13: s_cmp_neq_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x5d,0xbf] + +s_cmp_neq_f16 s0, m0 +// GFX13: s_cmp_neq_f16 s0, m0 ; encoding: [0x00,0x7d,0x5d,0xbf] + +s_cmp_neq_f16 s0, null +// GFX13: s_cmp_neq_f16 s0, null ; encoding: [0x00,0x7c,0x5d,0xbf] + +s_cmp_neq_f16 s0, 0 +// GFX13: s_cmp_neq_f16 s0, 0 ; encoding: [0x00,0x80,0x5d,0xbf] + +s_cmp_neq_f16 s0, 0.5 +// GFX13-ASM: s_cmp_neq_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x5d,0xbf] +// GFX13-DIS: s_cmp_neq_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x5d,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_neq_f16 s0, 0x1234 +// GFX13: s_cmp_neq_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x5d,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_nlt_f16 s0, s0 +// GFX13: s_cmp_nlt_f16 s0, s0 ; encoding: [0x00,0x00,0x5e,0xbf] + +s_cmp_nlt_f16 s105, s0 +// GFX13: s_cmp_nlt_f16 s105, s0 ; encoding: [0x69,0x00,0x5e,0xbf] + +s_cmp_nlt_f16 vcc_lo, s0 +// GFX13: s_cmp_nlt_f16 vcc_lo, s0 ; encoding: [0x6a,0x00,0x5e,0xbf] + +s_cmp_nlt_f16 exec_lo, s0 +// GFX13: s_cmp_nlt_f16 exec_lo, s0 ; encoding: [0x7e,0x00,0x5e,0xbf] + +s_cmp_nlt_f16 m0, s0 +// GFX13: s_cmp_nlt_f16 m0, s0 ; encoding: [0x7d,0x00,0x5e,0xbf] + +s_cmp_nlt_f16 null, s0 +// GFX13: s_cmp_nlt_f16 null, s0 ; encoding: [0x7c,0x00,0x5e,0xbf] + +s_cmp_nlt_f16 0, s0 +// GFX13: s_cmp_nlt_f16 0, s0 ; encoding: [0x80,0x00,0x5e,0xbf] + +s_cmp_nlt_f16 0.5, s0 +// GFX13-ASM: s_cmp_nlt_f16 0.5, s0 ; encoding: [0xf0,0x00,0x5e,0xbf] +// GFX13-DIS: s_cmp_nlt_f16 0x3800, s0 ; encoding: [0xff,0x00,0x5e,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nlt_f16 0x1234, s0 +// GFX13: s_cmp_nlt_f16 0x1234, s0 ; encoding: [0xff,0x00,0x5e,0xbf,0x34,0x12,0x00,0x00] + +s_cmp_nlt_f16 s0, s105 +// GFX13: s_cmp_nlt_f16 s0, s105 ; encoding: [0x00,0x69,0x5e,0xbf] + +s_cmp_nlt_f16 s0, vcc_lo +// GFX13: s_cmp_nlt_f16 s0, vcc_lo ; encoding: [0x00,0x6a,0x5e,0xbf] + +s_cmp_nlt_f16 s0, exec_lo +// GFX13: s_cmp_nlt_f16 s0, exec_lo ; encoding: [0x00,0x7e,0x5e,0xbf] + +s_cmp_nlt_f16 s0, m0 +// GFX13: s_cmp_nlt_f16 s0, m0 ; encoding: [0x00,0x7d,0x5e,0xbf] + +s_cmp_nlt_f16 s0, null +// GFX13: s_cmp_nlt_f16 s0, null ; encoding: [0x00,0x7c,0x5e,0xbf] + +s_cmp_nlt_f16 s0, 0 +// GFX13: s_cmp_nlt_f16 s0, 0 ; encoding: [0x00,0x80,0x5e,0xbf] + +s_cmp_nlt_f16 s0, 0.5 +// GFX13-ASM: s_cmp_nlt_f16 s0, 0.5 ; encoding: [0x00,0xf0,0x5e,0xbf] +// GFX13-DIS: s_cmp_nlt_f16 s0, 0x3800 ; encoding: [0x00,0xff,0x5e,0xbf,0x00,0x38,0x00,0x00] + +s_cmp_nlt_f16 s0, 0x1234 +// GFX13: s_cmp_nlt_f16 s0, 0x1234 ; encoding: [0x00,0xff,0x5e,0xbf,0x34,0x12,0x00,0x00] + diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx13_asm_sopk.s new file mode 100644 index 0000000000000..816ec1d09ca02 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx13_asm_sopk.s @@ -0,0 +1,215 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | FileCheck -check-prefixes=GFX13,GFX13-ASM %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1310 -disassemble -show-encoding | FileCheck -check-prefixes=GFX13,GFX13-DIS %s + +s_movk_i32 s0, 0 +// GFX13: s_movk_i32 s0, 0x0 ; encoding: [0x00,0x00,0x00,0xb0] + +s_movk_i32 s105, 0 +// GFX13: s_movk_i32 s105, 0x0 ; encoding: [0x00,0x00,0x69,0xb0] + +s_movk_i32 vcc_lo, 0 +// GFX13: s_movk_i32 vcc_lo, 0x0 ; encoding: [0x00,0x00,0x6a,0xb0] + +s_movk_i32 exec_lo, 0 +// GFX13: s_movk_i32 exec_lo, 0x0 ; encoding: [0x00,0x00,0x7e,0xb0] + +s_movk_i32 m0, 0 +// GFX13: s_movk_i32 m0, 0x0 ; encoding: [0x00,0x00,0x7d,0xb0] + +s_movk_i32 null, 0 +// GFX13: s_movk_i32 null, 0x0 ; encoding: [0x00,0x00,0x7c,0xb0] + +s_movk_i32 s0, 0x1234 +// GFX13: s_movk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb0] + +s_version 0 +// GFX13-ASM: s_version 0x0 ; encoding: [0x00,0x00,0x80,0xb0] +// GFX13-DIS: s_version UC_VERSION_GFX7 ; encoding: [0x00,0x00,0x80,0xb0] + +s_version 0x1234 +// GFX13: s_version 0x1234 ; encoding: [0x34,0x12,0x80,0xb0] + +s_cmovk_i32 s0, 0 +// GFX13: s_cmovk_i32 s0, 0x0 ; encoding: [0x00,0x00,0x00,0xb1] + +s_cmovk_i32 s105, 0 +// GFX13: s_cmovk_i32 s105, 0x0 ; encoding: [0x00,0x00,0x69,0xb1] + +s_cmovk_i32 vcc_lo, 0 +// GFX13: s_cmovk_i32 vcc_lo, 0x0 ; encoding: [0x00,0x00,0x6a,0xb1] + +s_cmovk_i32 exec_lo, 0 +// GFX13: s_cmovk_i32 exec_lo, 0x0 ; encoding: [0x00,0x00,0x7e,0xb1] + +s_cmovk_i32 m0, 0 +// GFX13: s_cmovk_i32 m0, 0x0 ; encoding: [0x00,0x00,0x7d,0xb1] + +s_cmovk_i32 null, 0 +// GFX13: s_cmovk_i32 null, 0x0 ; encoding: [0x00,0x00,0x7c,0xb1] + +s_cmovk_i32 s0, 0x1234 +// GFX13: s_cmovk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb1] + +s_addk_co_i32 s0, 0 +// GFX13: s_addk_co_i32 s0, 0x0 ; encoding: [0x00,0x00,0x80,0xb7] + +s_addk_co_i32 s105, 0 +// GFX13: s_addk_co_i32 s105, 0x0 ; encoding: [0x00,0x00,0xe9,0xb7] + +s_addk_co_i32 vcc_lo, 0 +// GFX13: s_addk_co_i32 vcc_lo, 0x0 ; encoding: [0x00,0x00,0xea,0xb7] + +s_addk_co_i32 exec_lo, 0 +// GFX13: s_addk_co_i32 exec_lo, 0x0 ; encoding: [0x00,0x00,0xfe,0xb7] + +s_addk_co_i32 m0, 0 +// GFX13: s_addk_co_i32 m0, 0x0 ; encoding: [0x00,0x00,0xfd,0xb7] + +s_addk_co_i32 null, 0 +// GFX13: s_addk_co_i32 null, 0x0 ; encoding: [0x00,0x00,0xfc,0xb7] + +s_addk_co_i32 s0, 0x1234 +// GFX13: s_addk_co_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x80,0xb7] + +s_mulk_i32 s0, 0 +// GFX13: s_mulk_i32 s0, 0x0 ; encoding: [0x00,0x00,0x00,0xb8] + +s_mulk_i32 s105, 0 +// GFX13: s_mulk_i32 s105, 0x0 ; encoding: [0x00,0x00,0x69,0xb8] + +s_mulk_i32 vcc_lo, 0 +// GFX13: s_mulk_i32 vcc_lo, 0x0 ; encoding: [0x00,0x00,0x6a,0xb8] + +s_mulk_i32 exec_lo, 0 +// GFX13: s_mulk_i32 exec_lo, 0x0 ; encoding: [0x00,0x00,0x7e,0xb8] + +s_mulk_i32 m0, 0 +// GFX13: s_mulk_i32 m0, 0x0 ; encoding: [0x00,0x00,0x7d,0xb8] + +s_mulk_i32 null, 0 +// GFX13: s_mulk_i32 null, 0x0 ; encoding: [0x00,0x00,0x7c,0xb8] + +s_mulk_i32 s0, 0x1234 +// GFX13: s_mulk_i32 s0, 0x1234 ; encoding: [0x34,0x12,0x00,0xb8] + +s_getreg_b32 s0, 0 +// GFX13: s_getreg_b32 s0, hwreg(0, 0, 1) ; encoding: [0x00,0x00,0x00,0xb9] + +s_getreg_b32 s105, 0 +// GFX13: s_getreg_b32 s105, hwreg(0, 0, 1) ; encoding: [0x00,0x00,0x69,0xb9] + +s_getreg_b32 vcc_lo, 0 +// GFX13: s_getreg_b32 vcc_lo, hwreg(0, 0, 1) ; encoding: [0x00,0x00,0x6a,0xb9] + +s_getreg_b32 exec_lo, 0 +// GFX13: s_getreg_b32 exec_lo, hwreg(0, 0, 1) ; encoding: [0x00,0x00,0x7e,0xb9] + +s_getreg_b32 m0, 0 +// GFX13: s_getreg_b32 m0, hwreg(0, 0, 1) ; encoding: [0x00,0x00,0x7d,0xb9] + +s_getreg_b32 null, 0 +// GFX13: s_getreg_b32 null, hwreg(0, 0, 1) ; encoding: [0x00,0x00,0x7c,0xb9] + +s_getreg_b32 s0, 0x1234 +// GFX13: s_getreg_b32 s0, hwreg(52, 8, 3) ; encoding: [0x34,0x12,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_MODE) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_MODE) ; encoding: [0x01,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_STATUS) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_STATUS) ; encoding: [0x02,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_STATE_PRIV) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_STATE_PRIV) ; encoding: [0x04,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_GPR_ALLOC) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_GPR_ALLOC) ; encoding: [0x05,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_LDS_ALLOC) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_LDS_ALLOC) ; encoding: [0x06,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA) ; encoding: [0x0a,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_LO) ; encoding: [0x0b,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_PC_HI) ; encoding: [0x0c,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA1) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA1) ; encoding: [0x0f,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA2) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_PERF_SNAPSHOT_DATA2) ; encoding: [0x10,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_PRIV) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) ; encoding: [0x11,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_EXCP_FLAG_USER) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) ; encoding: [0x12,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_TRAP_CTRL) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_TRAP_CTRL) ; encoding: [0x13,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_LO) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO) ; encoding: [0x14,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_SCRATCH_BASE_HI) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI) ; encoding: [0x15,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_HW_ID1) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID1) ; encoding: [0x17,0xf8,0x00,0xb9] + +s_getreg_b32 s0, hwreg(HW_REG_HW_ID2) +// GFX13: s_getreg_b32 s0, hwreg(HW_REG_WAVE_HW_ID2) ; encoding: [0x18,0xf8,0x00,0xb9] + +s_setreg_b32 0, s0 +// GFX13: s_setreg_b32 hwreg(0, 0, 1), s0 ; encoding: [0x00,0x00,0x80,0xb9] + +s_setreg_b32 0x1234, s0 +// GFX13: s_setreg_b32 hwreg(52, 8, 3), s0 ; encoding: [0x34,0x12,0x80,0xb9] + +s_setreg_b32 0, s105 +// GFX13: s_setreg_b32 hwreg(0, 0, 1), s105 ; encoding: [0x00,0x00,0xe9,0xb9] + +s_setreg_b32 0, vcc_lo +// GFX13: s_setreg_b32 hwreg(0, 0, 1), vcc_lo ; encoding: [0x00,0x00,0xea,0xb9] + +s_setreg_b32 0, exec_lo +// GFX13: s_setreg_b32 hwreg(0, 0, 1), exec_lo ; encoding: [0x00,0x00,0xfe,0xb9] + +s_setreg_b32 0, m0 +// GFX13: s_setreg_b32 hwreg(0, 0, 1), m0 ; encoding: [0x00,0x00,0xfd,0xb9] + +s_setreg_b32 0, null +// GFX13: s_setreg_b32 hwreg(0, 0, 1), null ; encoding: [0x00,0x00,0xfc,0xb9] + +s_setreg_imm32_b32 0, 0 +// GFX13: s_setreg_imm32_b32 hwreg(0, 0, 1), 0 ; encoding: [0x00,0x00,0x80,0xba,0x00,0x00,0x00,0x00] + +s_setreg_imm32_b32 0x1234, 0 +// GFX13: s_setreg_imm32_b32 hwreg(52, 8, 3), 0 ; encoding: [0x34,0x12,0x80,0xba,0x00,0x00,0x00,0x00] + +s_setreg_imm32_b32 0, 0x12345678 +// GFX13: s_setreg_imm32_b32 hwreg(0, 0, 1), 0x12345678 ; encoding: [0x00,0x00,0x80,0xba,0x78,0x56,0x34,0x12] + +s_call_i64 s[0:1], 0 +// GFX13: s_call_i64 s[0:1], 0 ; encoding: [0x00,0x00,0x00,0xbb] + +s_call_i64 s[104:105], 0 +// GFX13: s_call_i64 s[104:105], 0 ; encoding: [0x00,0x00,0x68,0xbb] + +s_call_i64 vcc, 0 +// GFX13: s_call_i64 vcc, 0 ; encoding: [0x00,0x00,0x6a,0xbb] + +s_call_i64 exec, 0 +// GFX13: s_call_i64 exec, 0 ; encoding: [0x00,0x00,0x7e,0xbb] + +s_call_i64 null, 0 +// GFX13: s_call_i64 null, 0 ; encoding: [0x00,0x00,0x7c,0xbb] + +s_call_i64 s[0:1], 0x1234 +// GFX13: s_call_i64 s[0:1], 4660 ; encoding: [0x34,0x12,0x00,0xbb] + diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_sopk_alias.s b/llvm/test/MC/AMDGPU/gfx13_asm_sopk_alias.s new file mode 100644 index 0000000000000..20d0b67c2ab17 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx13_asm_sopk_alias.s @@ -0,0 +1,9 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | FileCheck -check-prefixes=GFX13 %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1310 -disassemble -show-encoding | FileCheck -check-prefixes=GFX13 %s + +s_addk_i32 s0, 0x0 +// GFX13: s_addk_co_i32 s0, 0x0 ; encoding: [0x00,0x00,0x80,0xb7] + +s_call_b64 s[0:1], 0 +// GFX13: s_call_i64 s[0:1], 0 ; encoding: [0x00,0x00,0x00,0xbb] diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx13_asm_sopp.s new file mode 100644 index 0000000000000..512f70b3be0a4 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx13_asm_sopp.s @@ -0,0 +1,282 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | FileCheck -check-prefixes=GFX13 %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1310 -disassemble -show-encoding | FileCheck -check-prefixes=GFX13 %s + +s_nop 0 +// GFX13: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf] + +s_nop 0x1234 +// GFX13: s_nop 0x1234 ; encoding: [0x34,0x12,0x80,0xbf] + +s_endpgm 0 +// GFX13: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] + +s_endpgm 0x1234 +// GFX13: s_endpgm 4660 ; encoding: [0x34,0x12,0x81,0xbf] + +s_branch 0 +// GFX13: s_branch 0 ; encoding: [0x00,0x00,0x82,0xbf] + +s_branch 0x1234 +// GFX13: s_branch 4660 ; encoding: [0x34,0x12,0x82,0xbf] + +s_wakeup 0 +// GFX13: s_wakeup 0 ; encoding: [0x00,0x00,0x83,0xbf] + +s_wakeup 32 +// GFX13: s_wakeup 32 ; encoding: [0x20,0x00,0x83,0xbf] + +s_cbranch_scc0 0 +// GFX13: s_cbranch_scc0 0 ; encoding: [0x00,0x00,0x84,0xbf] + +s_cbranch_scc0 0x1234 +// GFX13: s_cbranch_scc0 4660 ; encoding: [0x34,0x12,0x84,0xbf] + +s_cbranch_scc1 0 +// GFX13: s_cbranch_scc1 0 ; encoding: [0x00,0x00,0x85,0xbf] + +s_cbranch_scc1 0x1234 +// GFX13: s_cbranch_scc1 4660 ; encoding: [0x34,0x12,0x85,0xbf] + +s_cbranch_vccz 0 +// GFX13: s_cbranch_vccz 0 ; encoding: [0x00,0x00,0x86,0xbf] + +s_cbranch_vccz 0x1234 +// GFX13: s_cbranch_vccz 4660 ; encoding: [0x34,0x12,0x86,0xbf] + +s_cbranch_vccnz 0 +// GFX13: s_cbranch_vccnz 0 ; encoding: [0x00,0x00,0x87,0xbf] + +s_cbranch_vccnz 0x1234 +// GFX13: s_cbranch_vccnz 4660 ; encoding: [0x34,0x12,0x87,0xbf] + +s_cbranch_execz 0 +// GFX13: s_cbranch_execz 0 ; encoding: [0x00,0x00,0x88,0xbf] + +s_cbranch_execz 0x1234 +// GFX13: s_cbranch_execz 4660 ; encoding: [0x34,0x12,0x88,0xbf] + +s_cbranch_execnz 0 +// GFX13: s_cbranch_execnz 0 ; encoding: [0x00,0x00,0x89,0xbf] + +s_cbranch_execnz 0x1234 +// GFX13: s_cbranch_execnz 4660 ; encoding: [0x34,0x12,0x89,0xbf] + +s_sethalt 0 +// GFX13: s_sethalt 0 ; encoding: [0x00,0x00,0x8d,0xbf] + +s_sethalt 0x1234 +// GFX13: s_sethalt 0x1234 ; encoding: [0x34,0x12,0x8d,0xbf] + +s_sleep 0 +// GFX13: s_sleep 0 ; encoding: [0x00,0x00,0x8e,0xbf] + +s_sleep 0x1234 +// GFX13: s_sleep 0x1234 ; encoding: [0x34,0x12,0x8e,0xbf] + +s_setprio 0 +// GFX13: s_setprio 0 ; encoding: [0x00,0x00,0x8f,0xbf] + +s_setprio 0x1234 +// GFX13: s_setprio 0x1234 ; encoding: [0x34,0x12,0x8f,0xbf] + +s_sendmsg 0 +// GFX13: s_sendmsg sendmsg(0, 0, 0) ; encoding: [0x00,0x00,0x90,0xbf] + +s_sendmsg 0x1234 +// GFX13: s_sendmsg 4660 ; encoding: [0x34,0x12,0x90,0xbf] + +s_sendmsg sendmsg(MSG_HS_TESSFACTOR) +// GFX13: s_sendmsg sendmsg(MSG_HS_TESSFACTOR) ; encoding: [0x02,0x00,0x90,0xbf] + +s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +// GFX13: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; encoding: [0x03,0x00,0x90,0xbf] + +s_sendmsghalt 0 +// GFX13: s_sendmsghalt sendmsg(0, 0, 0) ; encoding: [0x00,0x00,0x91,0xbf] + +s_sendmsghalt 0x1234 +// GFX13: s_sendmsghalt 4660 ; encoding: [0x34,0x12,0x91,0xbf] + +s_sendmsghalt sendmsg(MSG_HS_TESSFACTOR) +// GFX13: s_sendmsghalt sendmsg(MSG_HS_TESSFACTOR) ; encoding: [0x02,0x00,0x91,0xbf] + +s_sendmsghalt sendmsg(MSG_DEALLOC_VGPRS) +// GFX13: s_sendmsghalt sendmsg(MSG_DEALLOC_VGPRS) ; encoding: [0x03,0x00,0x91,0xbf] + +s_trap 0 +// GFX13: s_trap 0 ; encoding: [0x00,0x00,0x92,0xbf] + +s_trap 0x1234 +// GFX13: s_trap 0x1234 ; encoding: [0x34,0x12,0x92,0xbf] + +s_icache_inv +// GFX13: s_icache_inv ; encoding: [0x00,0x00,0x93,0xbf] + +s_incperflevel 0 +// GFX13: s_incperflevel 0 ; encoding: [0x00,0x00,0x94,0xbf] + +s_incperflevel 0x1234 +// GFX13: s_incperflevel 0x1234 ; encoding: [0x34,0x12,0x94,0xbf] + +s_decperflevel 0 +// GFX13: s_decperflevel 0 ; encoding: [0x00,0x00,0x95,0xbf] + +s_decperflevel 0x1234 +// GFX13: s_decperflevel 0x1234 ; encoding: [0x34,0x12,0x95,0xbf] + +s_ttracedata +// GFX13: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf] + +s_endpgm_saved +// GFX13: s_endpgm_saved ; encoding: [0x00,0x00,0x9b,0xbf] + +s_code_end +// GFX13: s_code_end ; encoding: [0x00,0x00,0x9f,0xbf] + +s_clause 0 +// GFX13: s_clause 0x0 ; encoding: [0x00,0x00,0xa1,0xbf] + +s_clause 0x1234 +// GFX13: s_clause 0x1234 ; encoding: [0x34,0x12,0xa1,0xbf] + +s_wait_idle +// GFX13: s_wait_idle ; encoding: [0x00,0x00,0xa2,0xbf] + +s_wait_alu 0 +// GFX13: s_wait_alu depctr_hold_cnt(0) depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0xa3,0xbf] + +s_wait_alu 0x1234 +// GFX13: s_wait_alu 0x1234 ; encoding: [0x34,0x12,0xa3,0xbf] + +s_wait_alu depctr_va_vdst(14) +// GFX13: s_wait_alu depctr_va_vdst(14) ; encoding: [0x9f,0xef,0xa3,0xbf] + +s_wait_alu depctr_va_sdst(6) +// GFX13: s_wait_alu depctr_va_sdst(6) ; encoding: [0x9f,0xfd,0xa3,0xbf] + +s_wait_alu depctr_vm_vsrc(6) +// GFX13: s_wait_alu depctr_vm_vsrc(6) ; encoding: [0x9b,0xff,0xa3,0xbf] + +s_round_mode 0 +// GFX13: s_round_mode 0x0 ; encoding: [0x00,0x00,0xa4,0xbf] + +s_round_mode 0x1234 +// GFX13: s_round_mode 0x1234 ; encoding: [0x34,0x12,0xa4,0xbf] + +s_denorm_mode 0 +// GFX13: s_denorm_mode 0 ; encoding: [0x00,0x00,0xa5,0xbf] + +s_denorm_mode 0x1234 +// GFX13: s_denorm_mode 0x1234 ; encoding: [0x34,0x12,0xa5,0xbf] + +s_ttracedata_imm 0 +// GFX13: s_ttracedata_imm 0x0 ; encoding: [0x00,0x00,0xa8,0xbf] + +s_ttracedata_imm 0x1234 +// GFX13: s_ttracedata_imm 0x1234 ; encoding: [0x34,0x12,0xa8,0xbf] + +s_barrier_wait 0 +// GFX13: s_barrier_wait 0 ; encoding: [0x00,0x00,0xab,0xbf] + +s_barrier_wait 0x1234 +// GFX13: s_barrier_wait 0x1234 ; encoding: [0x34,0x12,0xab,0xbf] + +s_monitor_sleep 0 +// GFX13: s_monitor_sleep 0 ; encoding: [0x00,0x00,0xac,0xbf] + +s_monitor_sleep 0x1234 +// GFX13: s_monitor_sleep 0x1234 ; encoding: [0x34,0x12,0xac,0xbf] + +s_delay_alu 0 +// GFX13: s_delay_alu 0 ; encoding: [0x00,0x00,0xae,0xbf] + +s_delay_alu 0x1234 +// GFX13: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; encoding: [0x34,0x12,0xae,0xbf] + +s_delay_alu instid0(VALU_DEP_4) +// GFX13: s_delay_alu instid0(VALU_DEP_4) ; encoding: [0x04,0x00,0xae,0xbf] + +s_delay_alu instid1(SALU_CYCLE_3) +// GFX13: s_delay_alu instid1(SALU_CYCLE_3) ; encoding: [0x80,0x05,0xae,0xbf] + +s_wait_event 0 +// GFX13: s_wait_event { export_ready: 0 } ; encoding: [0x00,0x00,0xaf,0xbf] + +s_wait_event 1 +// GFX13: s_wait_event 0x1 ; encoding: [0x01,0x00,0xaf,0xbf] + +s_wait_event 2 +// GFX13: s_wait_event { export_ready: 1 } ; encoding: [0x02,0x00,0xaf,0xbf] + +s_wait_event 0x1234 +// GFX13: s_wait_event 0x1234 ; encoding: [0x34,0x12,0xaf,0xbf] + +s_barrier_leave 0 +// GFX13: s_barrier_leave 0 ; encoding: [0x00,0x00,0xb1,0xbf] + +s_barrier_leave 32 +// GFX13: s_barrier_leave 32 ; encoding: [0x20,0x00,0xb1,0xbf] + +s_wait_loadcnt 0 +// GFX13: s_wait_loadcnt 0x0 ; encoding: [0x00,0x00,0xc0,0xbf] + +s_wait_loadcnt 0x1234 +// GFX13: s_wait_loadcnt 0x1234 ; encoding: [0x34,0x12,0xc0,0xbf] + +s_wait_storecnt 0 +// GFX13: s_wait_storecnt 0x0 ; encoding: [0x00,0x00,0xc1,0xbf] + +s_wait_storecnt 0x1234 +// GFX13: s_wait_storecnt 0x1234 ; encoding: [0x34,0x12,0xc1,0xbf] + +s_wait_samplecnt 0 +// GFX13: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf] + +s_wait_samplecnt 0x1234 +// GFX13: s_wait_samplecnt 0x1234 ; encoding: [0x34,0x12,0xc2,0xbf] + +s_wait_expcnt 0 +// GFX13: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf] + +s_wait_expcnt 0x1234 +// GFX13: s_wait_expcnt 0x1234 ; encoding: [0x34,0x12,0xc4,0xbf] + +s_wait_dscnt 0 +// GFX13: s_wait_dscnt 0x0 ; encoding: [0x00,0x00,0xc6,0xbf] + +s_wait_dscnt 0x1234 +// GFX13: s_wait_dscnt 0x1234 ; encoding: [0x34,0x12,0xc6,0xbf] + +s_wait_kmcnt 0 +// GFX13: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf] + +s_wait_kmcnt 0x1234 +// GFX13: s_wait_kmcnt 0x1234 ; encoding: [0x34,0x12,0xc7,0xbf] + +s_wait_loadcnt_dscnt 0 +// GFX13: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf] + +s_wait_loadcnt_dscnt 0x1234 +// GFX13: s_wait_loadcnt_dscnt 0x1234 ; encoding: [0x34,0x12,0xc8,0xbf] + +s_wait_storecnt_dscnt 0 +// GFX13: s_wait_storecnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc9,0xbf] + +s_wait_storecnt_dscnt 0x1234 +// GFX13: s_wait_storecnt_dscnt 0x1234 ; encoding: [0x34,0x12,0xc9,0xbf] + +s_wait_asynccnt 0 +// GFX13: s_wait_asynccnt 0x0 ; encoding: [0x00,0x00,0xca,0xbf] + +s_wait_asynccnt 0x1234 +// GFX13: s_wait_asynccnt 0x1234 ; encoding: [0x34,0x12,0xca,0xbf] + +s_wait_tensorcnt 0x0 +// GFX13: s_wait_tensorcnt 0x0 ; encoding: [0x00,0x00,0xcb,0xbf] + +s_wait_tensorcnt 0x1 +// GFX13: s_wait_tensorcnt 0x1 ; encoding: [0x01,0x00,0xcb,0xbf] + +s_wait_tensorcnt 0x3 +// GFX13: s_wait_tensorcnt 0x3 ; encoding: [0x03,0x00,0xcb,0xbf] diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_sopp_alias.s b/llvm/test/MC/AMDGPU/gfx13_asm_sopp_alias.s new file mode 100644 index 0000000000000..18a3d27030d01 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx13_asm_sopp_alias.s @@ -0,0 +1,18 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6 +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | FileCheck -check-prefixes=GFX13 %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1310 -disassemble -show-encoding | FileCheck -check-prefixes=GFX13 %s + +s_waitcnt_depctr 0 +// GFX13: s_wait_alu depctr_hold_cnt(0) depctr_sa_sdst(0) depctr_va_vdst(0) depctr_va_sdst(0) depctr_va_ssrc(0) depctr_va_vcc(0) depctr_vm_vsrc(0) ; encoding: [0x00,0x00,0xa3,0xbf] + +s_waitcnt_depctr 0x1234 +// GFX13: s_wait_alu 0x1234 ; encoding: [0x34,0x12,0xa3,0xbf] + +s_waitcnt_depctr depctr_va_vdst(14) +// GFX13: s_wait_alu depctr_va_vdst(14) ; encoding: [0x9f,0xef,0xa3,0xbf] + +s_waitcnt_depctr depctr_va_sdst(6) +// GFX13: s_wait_alu depctr_va_sdst(6) ; encoding: [0x9f,0xfd,0xa3,0xbf] + +s_waitcnt_depctr depctr_vm_vsrc(6) +// GFX13: s_wait_alu depctr_vm_vsrc(6) ; encoding: [0x9b,0xff,0xa3,0xbf] diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_exp.s b/llvm/test/MC/AMDGPU/gfx9_asm_exp.s index 514413201c02f..a8a961bd7fae6 100644 --- a/llvm/test/MC/AMDGPU/gfx9_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx9_asm_exp.s @@ -81,3 +81,105 @@ exp param0 v0, v0, v0, v0 exp pos0 v0, v0, v0, v0 // CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp mrt0 v0, v0, v0, v0 nodone +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 nocompr +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 novm +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp mrtz v0, v0, v0, v0 done +// CHECK: exp mrtz v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nodone +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 compr +// CHECK: exp mrtz v0, v0, v0, v0 compr ; encoding: [0x8f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nocompr +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 vm +// CHECK: exp mrtz v0, v0, v0, v0 vm ; encoding: [0x8f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 novm +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp null v0, v0, v0, v0 done +// CHECK: exp null v0, v0, v0, v0 done ; encoding: [0x9f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 nodone +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 compr +// CHECK: exp null v0, v0, v0, v0 compr ; encoding: [0x9f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 nocompr +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 vm +// CHECK: exp null v0, v0, v0, v0 vm ; encoding: [0x9f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 novm +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp pos0 v0, v0, v0, v0 done +// CHECK: exp pos0 v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nodone +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 compr +// CHECK: exp pos0 v0, v0, v0, v0 compr ; encoding: [0xcf,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nocompr +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 vm +// CHECK: exp pos0 v0, v0, v0, v0 vm ; encoding: [0xcf,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 novm +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp param0 v0, v0, v0, v0 done +// CHECK: exp param0 v0, v0, v0, v0 done ; encoding: [0x0f,0x0a,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 nodone +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 compr +// CHECK: exp param0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x06,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 nocompr +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 vm +// CHECK: exp param0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x12,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 novm +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp mrt0 v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp16.txt new file mode 100644 index 0000000000000..1aaea00103169 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp16.txt @@ -0,0 +1,15 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -disassemble -show-encoding %s | FileCheck -check-prefixes=GFX1170 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -disassemble -show-encoding %s | FileCheck -check-prefixes=GFX1170 %s + +0xfa,0xd8,0x02,0x7e,0x03,0xe4,0x00,0xac +# GFX1170: v_cvt_f32_fp8_dpp v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc ; encoding: [0xfa,0xd8,0x02,0x7e,0x03,0xe4,0x00,0xac] + +0xfa,0xd8,0x02,0x7e,0x03,0x1b,0x00,0x2e +# GFX1170: v_cvt_f32_fp8_dpp v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe ; encoding: [0xfa,0xd8,0x02,0x7e,0x03,0x1b,0x00,0x2e] + +0xfa,0xda,0x02,0x7e,0x03,0xe4,0x00,0xac +# GFX1170: v_cvt_f32_bf8_dpp v1, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xc ; encoding: [0xfa,0xda,0x02,0x7e,0x03,0xe4,0x00,0xac] + +0xfa,0xda,0x02,0x7e,0x03,0x1b,0x00,0x2e +# GFX1170: v_cvt_f32_bf8_dpp v1, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xe ; encoding: [0xfa,0xda,0x02,0x7e,0x03,0x1b,0x00,0x2e] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp8.txt new file mode 100644 index 0000000000000..e5cb60e0e72b2 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp8.txt @@ -0,0 +1,15 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1170 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefix=GFX1170 %s + +0xe9,0xd8,0x0a,0x7e,0x01,0x88,0xc6,0xfa +# GFX1170: v_cvt_f32_fp8_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0xd8,0x0a,0x7e,0x01,0x88,0xc6,0xfa] + +0xe9,0xd8,0x02,0x7e,0x03,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_fp8_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd8,0x02,0x7e,0x03,0x77,0x39,0x05] + +0xe9,0xda,0x0a,0x7e,0x01,0x88,0xc6,0xfa +# GFX1170: v_cvt_f32_bf8_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0xda,0x0a,0x7e,0x01,0x88,0xc6,0xfa] + +0xe9,0xda,0x02,0x7e,0x03,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_bf8_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xda,0x02,0x7e,0x03,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3.txt new file mode 100644 index 0000000000000..14f8274e96529 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3.txt @@ -0,0 +1,63 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1170,GFX1170-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1170,GFX1170-FAKE16 %s + +0x01,0x00,0x69,0xd7,0x02,0x07,0x02,0x00 +# GFX1170-FAKE16: v_cvt_pk_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x69,0xd7,0x02,0x07,0x02,0x02] +# GFX1170-REAL16: v_cvt_pk_fp8_f32 v1.l, v2, v3 ; encoding: [0x01,0x00,0x69,0xd7,0x02,0x07,0x02,0x02] + +0x01,0x02,0x69,0xd7,0x02,0x07,0x02,0x20 +# GFX1170-FAKE16: v_cvt_pk_fp8_f32 v1, -v2, |v3| ; encoding: [0x01,0x02,0x69,0xd7,0x02,0x07,0x02,0x22] +# GFX1170-REAL16: v_cvt_pk_fp8_f32 v1.l, -v2, |v3| ; encoding: [0x01,0x02,0x69,0xd7,0x02,0x07,0x02,0x22] + +0x01,0x00,0x69,0xd7,0x02,0x06,0x01,0x00 +# GFX1170-FAKE16: v_cvt_pk_fp8_f32 v1, s2, 3 ; encoding: [0x01,0x00,0x69,0xd7,0x02,0x06,0x01,0x02] +# GFX1170-REAL16: v_cvt_pk_fp8_f32 v1.l, s2, 3 ; encoding: [0x01,0x00,0x69,0xd7,0x02,0x06,0x01,0x02] + +0x01,0x00,0x6a,0xd7,0x02,0x07,0x02,0x00 +# GFX1170-FAKE16: v_cvt_pk_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6a,0xd7,0x02,0x07,0x02,0x02] +# GFX1170-REAL16: v_cvt_pk_bf8_f32 v1.l, v2, v3 ; encoding: [0x01,0x00,0x6a,0xd7,0x02,0x07,0x02,0x02] + +0x01,0x02,0x6a,0xd7,0x02,0x07,0x02,0x20 +# GFX1170-FAKE16: v_cvt_pk_bf8_f32 v1, -v2, |v3| ; encoding: [0x01,0x02,0x6a,0xd7,0x02,0x07,0x02,0x22] +# GFX1170-REAL16: v_cvt_pk_bf8_f32 v1.l, -v2, |v3| ; encoding: [0x01,0x02,0x6a,0xd7,0x02,0x07,0x02,0x22] + +0x01,0x00,0x6a,0xd7,0x02,0x06,0x01,0x00 +# GFX1170-FAKE16: v_cvt_pk_bf8_f32 v1, s2, 3 ; encoding: [0x01,0x00,0x6a,0xd7,0x02,0x06,0x01,0x02] +# GFX1170-REAL16: v_cvt_pk_bf8_f32 v1.l, s2, 3 ; encoding: [0x01,0x00,0x6a,0xd7,0x02,0x06,0x01,0x02] + +0x01,0x00,0x6b,0xd7,0x02,0x07,0x02,0x00 +# GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6b,0xd7,0x02,0x07,0x02,0x02] + +0x0a,0x00,0x6b,0xd7,0x02,0x0a,0x02,0x00 +# GFX1170: v_cvt_sr_fp8_f32 v10, s2, v5 ; encoding: [0x0a,0x00,0x6b,0xd7,0x02,0x0a,0x02,0x02] + +0x05,0x01,0x6b,0xd7,0xff,0x09,0x02,0x20 +# GFX1170: v_cvt_sr_fp8_f32 v5, -|v255|, v4 ; encoding: [0x05,0x01,0x6b,0xd7,0xff,0x09,0x02,0x22] + +0x01,0x20,0x6b,0xd7,0x02,0x07,0x02,0x00 +# GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6b,0xd7,0x02,0x07,0x02,0x02] + +0x01,0x40,0x6b,0xd7,0x02,0x07,0x02,0x00 +# GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6b,0xd7,0x02,0x07,0x02,0x02] + +0x01,0x60,0x6b,0xd7,0x02,0x07,0x02,0x00 +# GFX1170: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6b,0xd7,0x02,0x07,0x02,0x02] + +0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x00 +# GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x02] + +0x0a,0x00,0x6c,0xd7,0x02,0x0a,0x02,0x00 +# GFX1170: v_cvt_sr_bf8_f32 v10, s2, v5 ; encoding: [0x0a,0x00,0x6c,0xd7,0x02,0x0a,0x02,0x02] + +0x05,0x01,0x6c,0xd7,0xff,0x09,0x02,0x20 +# GFX1170: v_cvt_sr_bf8_f32 v5, -|v255|, v4 ; encoding: [0x05,0x01,0x6c,0xd7,0xff,0x09,0x02,0x22] + +0x01,0x20,0x6c,0xd7,0x02,0x07,0x02,0x00 +# GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6c,0xd7,0x02,0x07,0x02,0x02] + +0x01,0x40,0x6c,0xd7,0x02,0x07,0x02,0x00 +# GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6c,0xd7,0x02,0x07,0x02,0x02] + +0x01,0x60,0x6c,0xd7,0x02,0x07,0x02,0x00 +# GFX1170: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6c,0xd7,0x02,0x07,0x02,0x02] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp16.txt new file mode 100644 index 0000000000000..240c01d55f507 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp16.txt @@ -0,0 +1,147 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck --check-prefixes=GFX1170,GFX1170-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck --check-prefixes=GFX1170,GFX1170-FAKE16 %s + +0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x02,0x6a,0xd7,0x02,0x07,0x02,0x20 +# GFX1170-FAKE16: v_cvt_pk_bf8_f32 v1, -v2, |v3| ; encoding: [0x01,0x02,0x6a,0xd7,0x02,0x07,0x02,0x22] +# GFX1170-REAL16: v_cvt_pk_bf8_f32 v1.l, -v2, |v3| ; encoding: [0x01,0x02,0x6a,0xd7,0x02,0x07,0x02,0x22] + +0x06,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v6.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v1.l, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +0x01,0x02,0x6a,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v1.l, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5 +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x02,0x6a,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x02,0x69,0xd7,0x02,0x07,0x02,0x20 +# GFX1170-FAKE16: v_cvt_pk_fp8_f32 v1, -v2, |v3| ; encoding: [0x01,0x02,0x69,0xd7,0x02,0x07,0x02,0x22] +# GFX1170-REAL16: v_cvt_pk_fp8_f32 v1.l, -v2, |v3| ; encoding: [0x01,0x02,0x69,0xd7,0x02,0x07,0x02,0x22] + +0x06,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v6, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v6.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v1, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v1.l, -v6, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +0x01,0x02,0x69,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v1.l, -v2, |v255| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5 +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v1, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v1.l, -v2, |v3| quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x02,0x69,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +0x06,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +0x01,0x00,0x6c,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5 +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +0x01,0x20,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +0x01,0x40,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +0x01,0x60,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xe4,0x00,0xff] + +0x06,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v6, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x06,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v6, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x06,0x1b,0x00,0xed] + +0x01,0x00,0x6b,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v255 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0xfe,0x03,0x20,0x02,0x1b,0x00,0xed] + +0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[0,2,1,3] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0xd8,0x00,0xed] + +0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0x2 bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0x2d] + +0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5 +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0x5 ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xe5] + +0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] + +0x01,0x20,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +0x01,0x40,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +0x01,0x60,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp8.txt new file mode 100644 index 0000000000000..d143e0b0dbcb7 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp8.txt @@ -0,0 +1,77 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck --check-prefixes=GFX1170,GFX1170-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck --check-prefixes=GFX1170,GFX1170-FAKE16 %s + +0x05,0x00,0x69,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0xa9,0x21 +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v5.l, v1, v2 dpp8:[7,6,5,4,2,3,0,1] ; encoding: [0x05,0x00,0x69,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0xa9,0x21] +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,2,3,0,1] ; encoding: [0x05,0x00,0x69,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0xa9,0x21] + +0x05,0x01,0x69,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05 +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v5.l, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x69,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x69,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +0x05,0x02,0x69,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05 +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v5.l, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x69,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x69,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +0xff,0x03,0x69,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 +# GFX1170-REAL16: v_cvt_pk_fp8_f32_e64_dpp v255.l, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x69,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# GFX1170-FAKE16: v_cvt_pk_fp8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x69,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +0x05,0x00,0x6a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v5.l, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6a,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +0x05,0x01,0x6a,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05 +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v5.l, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6a,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6a,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +0x05,0x02,0x6a,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05 +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v5.l, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x6a,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x6a,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +0xff,0x03,0x6a,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 +# GFX1170-REAL16: v_cvt_pk_bf8_f32_e64_dpp v255.l, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x6a,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +# GFX1170-FAKE16: v_cvt_pk_bf8_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x6a,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +0x05,0x00,0x6b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +0x05,0x01,0x6b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6b,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +0x05,0x00,0x6b,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6b,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +0xff,0x01,0x6b,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00 +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x01,0x6b,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +0x01,0x20,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +0x01,0x40,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +0x01,0x60,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +0x05,0x01,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, |v1|, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +0xff,0x01,0x6c,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00 +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x01,0x6c,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] + +0x01,0x20,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +0x01,0x40,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +0x01,0x60,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1.txt new file mode 100644 index 0000000000000..cf3fdcc9d33e1 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1.txt @@ -0,0 +1,57 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1170,GFX1170-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1170,GFX1170-FAKE16 %s + +0x01,0x00,0xed,0xd5,0x03,0x00,0x00,0x00 +# GFX1170: v_cvt_f32_bf8_e64 v1, s3 ; encoding: [0x01,0x00,0xed,0xd5,0x03,0x00,0x01,0x02] + +0x01,0x00,0xed,0xd5,0x83,0x00,0x00,0x00 +# GFX1170: v_cvt_f32_bf8_e64 v1, 3 ; encoding: [0x01,0x00,0xed,0xd5,0x83,0x00,0x01,0x02] + +0x01,0x00,0xed,0xd5,0x03,0x01,0x00,0x00 +# GFX1170: v_cvt_f32_bf8_e64 v1, v3 ; encoding: [0x01,0x00,0xed,0xd5,0x03,0x01,0x01,0x02] + +0x01,0x00,0xec,0xd5,0x03,0x00,0x00,0x00 +# GFX1170: v_cvt_f32_fp8_e64 v1, s3 ; encoding: [0x01,0x00,0xec,0xd5,0x03,0x00,0x01,0x02] + +0x01,0x00,0xec,0xd5,0x83,0x00,0x00,0x00 +# GFX1170: v_cvt_f32_fp8_e64 v1, 3 ; encoding: [0x01,0x00,0xec,0xd5,0x83,0x00,0x01,0x02] + +0x01,0x00,0xec,0xd5,0x03,0x01,0x00,0x00 +# GFX1170: v_cvt_f32_fp8_e64 v1, v3 ; encoding: [0x01,0x00,0xec,0xd5,0x03,0x01,0x01,0x02] + +0x02,0x00,0xef,0xd5,0x03,0x00,0x00,0x00 +# GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], s3 ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x00,0x01,0x02] + +0x02,0x00,0xef,0xd5,0x83,0x00,0x00,0x00 +# GFX1170: v_cvt_pk_f32_bf8_e64 v[2:3], 3 ; encoding: [0x02,0x00,0xef,0xd5,0x83,0x00,0x01,0x02] + +0x02,0x00,0xef,0xd5,0x03,0x01,0x00,0x00 +# GFX1170-FAKE16: v_cvt_pk_f32_bf8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x01,0x01,0x02] +# GFX1170-REAL16: v_cvt_pk_f32_bf8_e64 v[2:3], v3.l ; encoding: [0x02,0x00,0xef,0xd5,0x03,0x01,0x01,0x02] + +0x02,0x08,0xef,0xd5,0x03,0x01,0x00,0x00 +# GFX1170-FAKE16: v_cvt_pk_f32_bf8_e64 v[2:3], v3 op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x03,0x01,0x01,0x02] +# GFX1170-REAL16: v_cvt_pk_f32_bf8_e64 v[2:3], v3.h op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0x03,0x01,0x01,0x02] + +0x02,0x08,0xef,0xd5,0xff,0x01,0x00,0x00 +# GFX1170-FAKE16: v_cvt_pk_f32_bf8_e64 v[2:3], v255 op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0xff,0x01,0x01,0x02] +# GFX1170-REAL16: v_cvt_pk_f32_bf8_e64 v[2:3], v255.h op_sel:[1,0] ; encoding: [0x02,0x08,0xef,0xd5,0xff,0x01,0x01,0x02] + +0x02,0x00,0xee,0xd5,0x03,0x00,0x00,0x00 +# GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], s3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x00,0x01,0x02] + +0x02,0x00,0xee,0xd5,0x83,0x00,0x00,0x00 +# GFX1170: v_cvt_pk_f32_fp8_e64 v[2:3], 3 ; encoding: [0x02,0x00,0xee,0xd5,0x83,0x00,0x01,0x02] + +0x02,0x00,0xee,0xd5,0x03,0x01,0x00,0x00 +# GFX1170-FAKE16: v_cvt_pk_f32_fp8_e64 v[2:3], v3 ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x01,0x01,0x02] +# GFX1170-REAL16: v_cvt_pk_f32_fp8_e64 v[2:3], v3.l ; encoding: [0x02,0x00,0xee,0xd5,0x03,0x01,0x01,0x02] + +0x02,0x08,0xee,0xd5,0x03,0x01,0x00,0x00 +# GFX1170-FAKE16: v_cvt_pk_f32_fp8_e64 v[2:3], v3 op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x03,0x01,0x01,0x02] +# GFX1170-REAL16: v_cvt_pk_f32_fp8_e64 v[2:3], v3.h op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0x03,0x01,0x01,0x02] + +0x02,0x08,0xee,0xd5,0xff,0x01,0x00,0x00 +# GFX1170-FAKE16: v_cvt_pk_f32_fp8_e64 v[2:3], v255 op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0xff,0x01,0x01,0x02] +# GFX1170-REAL16: v_cvt_pk_f32_fp8_e64 v[2:3], v255.h op_sel:[1,0] ; encoding: [0x02,0x08,0xee,0xd5,0xff,0x01,0x01,0x02] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp16.txt new file mode 100644 index 0000000000000..d0bb4f32270c6 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp16.txt @@ -0,0 +1,45 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1170 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1170 %s + +0x05,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0x2d +# GFX1170: v_cvt_f32_fp8_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x2 bank_mask:0xd ; encoding: [0x05,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0x2d] + +0x01,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x03,0x58,0x00,0x5e +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v3 quad_perm:[0,2,1,1] row_mask:0x5 bank_mask:0xe ; encoding: [0x01,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x03,0x58,0x00,0x5e] + +0xfa,0xd8,0x02,0x7e,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_fp8_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xd8,0x02,0x7e,0x02,0xe4,0x00,0xff] + +0x01,0x10,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x10,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +0x01,0x08,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x08,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +0x01,0x18,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x18,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +0x01,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0xec,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +0x05,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0x2d +# GFX1170: v_cvt_f32_bf8_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x2 bank_mask:0xd ; encoding: [0x05,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0x2d] + +0x01,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x03,0x58,0x00,0x5e +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v3 quad_perm:[0,2,1,1] row_mask:0x5 bank_mask:0xe ; encoding: [0x01,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x03,0x58,0x00,0x5e] + +0xfa,0xda,0x02,0x7e,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_bf8_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xda,0x02,0x7e,0x02,0xe4,0x00,0xff] + +0x01,0x10,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x10,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +0x01,0x08,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x08,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +0x01,0x18,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x18,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] + +0x01,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0xed,0xd5,0xfa,0x00,0x00,0x00,0x02,0xe4,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp8.txt new file mode 100644 index 0000000000000..35afe0f838b78 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp8.txt @@ -0,0 +1,45 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1170 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1170 %s + +0x05,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x01,0x88,0xc6,0xfa +# GFX1170: v_cvt_f32_fp8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x05,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x01,0x88,0xc6,0xfa] + +0x01,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05] + +0xe9,0xd8,0x02,0x7e,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_fp8_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xd8,0x02,0x7e,0x02,0x77,0x39,0x05] + +0x01,0x10,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x10,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +0x01,0x08,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x08,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +0x01,0x18,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x18,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +0x01,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_fp8_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xec,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +0x05,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x01,0x88,0xc6,0xfa +# GFX1170: v_cvt_f32_bf8_e64_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x05,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x01,0x88,0xc6,0xfa] + +0x01,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x03,0x77,0x39,0x05] + +0xe9,0xda,0x02,0x7e,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_bf8_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xda,0x02,0x7e,0x02,0x77,0x39,0x05] + +0x01,0x10,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x10,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +0x01,0x08,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x08,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +0x01,0x18,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x18,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] + +0x01,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05 +# GFX1170: v_cvt_f32_bf8_e64_dpp v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0xed,0xd5,0xe9,0x00,0x00,0x00,0x02,0x77,0x39,0x05] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt index 3fac24abc809e..cbcc17cd5e68c 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt @@ -14,7 +14,10 @@ # GFX1250: s_monitor_sleep 1 ; encoding: [0x01,0x00,0x84,0xbf] 0x0a,0x00,0xb6,0xbf -# GFX1250: s_sendmsg sendmsg(MSG_SAVEWAVE_HAS_TDM) ; encoding: [0x0a,0x00,0xb6,0xbf] +# GFX1250: s_sendmsg sendmsg(10, 0, 0) ; encoding: [0x0a,0x00,0xb6,0xbf] + +0x98,0x4c,0x81,0xbe +# GFX1250: s_sendmsg_rtn_b32 s1, sendmsg(MSG_RTN_SAVE_WAVE_HAS_TDM) ; encoding: [0x98,0x4c,0x81,0xbe] 0xff,0x00,0x86,0xbf # GFX1250: s_set_vgpr_msb 0xff ; encoding: [0xff,0x00,0x86,0xbf] diff --git a/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt b/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt index 0a83a200c9317..beaaad8bf9adf 100644 --- a/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt +++ b/llvm/test/MC/Disassembler/RISCV/c_lui_disasm.txt @@ -204,7 +204,7 @@ 0x7D 0x70 # BAD: invalid instruction encoding -# MOP: c.mop.1 +# MOP: c.sspush ra 0x81 0x60 # GOOD: c.lui ra, 1 @@ -782,7 +782,7 @@ 0x7D 0x72 # BAD: invalid instruction encoding -# MOP: c.mop.5 +# MOP: c.sspopchk t0 0x81 0x62 # GOOD: c.lui t0, 1 diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s index 7d387b257b7b4..bd4bf1858b6dc 100644 --- a/llvm/test/MC/RISCV/compressed-zicfiss.s +++ b/llvm/test/MC/RISCV/compressed-zicfiss.s @@ -9,45 +9,59 @@ # RUN: | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # +# Compressed Zicfiss instructions only require Zcmop (and Zimop for +# uncompressed forms), not Zicfiss (riscv-non-isa/riscv-elf-psabi-doc#474). +# +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcmop,+zimop -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcmop,+zimop < %s \ +# RUN: | llvm-objdump --mattr=+zcmop,+zimop -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zcmop,+zimop -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcmop,+zimop < %s \ +# RUN: | llvm-objdump --mattr=+zcmop,+zimop -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# # RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # CHECK-ASM-AND-OBJ: c.sspopchk t0 # CHECK-ASM: encoding: [0x81,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspopchk x5 # CHECK-ASM-AND-OBJ: c.sspopchk t0 # CHECK-ASM: encoding: [0x81,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspopchk t0 # CHECK-ASM-AND-OBJ: c.sspush ra # CHECK-ASM: encoding: [0x81,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspush x1 # CHECK-ASM-AND-OBJ: c.sspush ra # CHECK-ASM: encoding: [0x81,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspush ra # CHECK-ASM-AND-OBJ: c.sspush ra # CHECK-ASM: encoding: [0x81,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations) c.sspush x1 # CHECK-ASM-AND-OBJ: c.sspush ra # CHECK-ASM: encoding: [0x81,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations) c.sspush ra # CHECK-ASM-AND-OBJ: c.sspopchk t0 # CHECK-ASM: encoding: [0x81,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations) c.sspopchk x5 # CHECK-ASM-AND-OBJ: c.sspopchk t0 # CHECK-ASM: encoding: [0x81,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations), 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zcmop' (Compressed May-Be-Operations) c.sspopchk t0 diff --git a/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s b/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s index 8e8c42e033b8a..477ccdf6a28de 100644 --- a/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s +++ b/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s @@ -11,8 +11,8 @@ # which are valid for the current set of features ad x1, x1, x1 -# CHECK-RV32: did you mean: add, addi, and, andi, la -# CHECK-RV64: did you mean: add, addi, addw, and, andi, la, ld, sd +# CHECK-RV32: did you mean: add, addi, and, andi, la, lpad +# CHECK-RV64: did you mean: add, addi, addw, and, andi, la, ld, lpad, sd # CHECK-NEXT: ad x1, x1, x1 fl ft0, 0(sp) diff --git a/llvm/test/MC/RISCV/rv32dc-valid.s b/llvm/test/MC/RISCV/rv32dc-valid.s index 495c88448a183..01e63fd747683 100644 --- a/llvm/test/MC/RISCV/rv32dc-valid.s +++ b/llvm/test/MC/RISCV/rv32dc-valid.s @@ -11,28 +11,24 @@ # # RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: -M no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM: encoding: [0x7e,0x34] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions) c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM: encoding: [0xc6,0xbf] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions) c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM: encoding: [0xf4,0x3f] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions) c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM: encoding: [0xf0,0xbd] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions) c.fsd fa2, 248(a1) diff --git a/llvm/test/MC/RISCV/rv32fc-valid.s b/llvm/test/MC/RISCV/rv32fc-valid.s index af38a636cf804..21fbc084050b0 100644 --- a/llvm/test/MC/RISCV/rv32fc-valid.s +++ b/llvm/test/MC/RISCV/rv32fc-valid.s @@ -11,10 +11,10 @@ # # RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: -M no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-F %s +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: not llvm-mc -triple riscv32 \ # RUN: -M no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-FC %s +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: not llvm-mc -triple riscv64 -mattr=+c,+f \ # RUN: -M no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-RV32 %s @@ -23,26 +23,22 @@ # CHECK-ASM-AND-OBJ: c.flwsp fs0, 252(sp) # CHECK-ASM: encoding: [0x7e,0x74] -# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} -# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}} -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions){{$}} +# CHECK-NO-RV32: error: instruction requires the following: 'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), RV32I Base Instruction Set{{$}} c.flwsp fs0, 252(sp) # CHECK-ASM-AND-OBJ: c.fswsp fa7, 252(sp) # CHECK-ASM: encoding: [0xc6,0xff] -# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} -# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}} -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions){{$}} +# CHECK-NO-RV32: error: instruction requires the following: 'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), RV32I Base Instruction Set{{$}} c.fswsp fa7, 252(sp) # CHECK-ASM-AND-OBJ: c.flw fa3, 124(a5) # CHECK-ASM: encoding: [0xf4,0x7f] -# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} -# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}} -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions){{$}} +# CHECK-NO-RV32: error: instruction requires the following: 'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), RV32I Base Instruction Set{{$}} c.flw fa3, 124(a5) # CHECK-ASM-AND-OBJ: c.fsw fa2, 124(a1) # CHECK-ASM: encoding: [0xf0,0xfd] -# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} -# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}} -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions){{$}} +# CHECK-NO-RV32: error: instruction requires the following: 'C' (Compressed Instructions) and 'F' (Single-Precision Floating-Point) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), RV32I Base Instruction Set{{$}} c.fsw fa2, 124(a1) diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s index 7f57345c3223c..29daf365d3f1f 100644 --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -196,7 +196,6 @@ sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the followi clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation){{$}} clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography){{$}} bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions){{$}} -pause # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zihintpause' (Pause Hint){{$}} # Using floating point registers when integer registers are expected addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32p-invalid.s b/llvm/test/MC/RISCV/rv32p-invalid.s index 617499859f853..105444cf6b300 100644 --- a/llvm/test/MC/RISCV/rv32p-invalid.s +++ b/llvm/test/MC/RISCV/rv32p-invalid.s @@ -102,8 +102,7 @@ maccsu.w00 a4, s2, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the fol pmaccsu.w.h11 a0, a2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set maccsu.w11 t5, a4, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -ppaire.h t5, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set - +ppaire.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set ppaireo.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set ppairoe.w t5, t1, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set ppairo.w t3, a0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s index c601786cccc64..fc56ec675ea90 100644 --- a/llvm/test/MC/RISCV/rv32p-valid.s +++ b/llvm/test/MC/RISCV/rv32p-valid.s @@ -337,6 +337,9 @@ maccsu.h11 s0, a2, s6 # CHECK-ASM-AND-OBJ: ppaire.b t1, a2, t5 # CHECK-ASM: encoding: [0x3b,0x43,0xe6,0x81] ppaire.b t1, a2, t5 +# CHECK-ASM-AND-OBJ: pack s0, s1, s2 +# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09] +ppaire.h s0, s1, s2 # CHECK-ASM-AND-OBJ: ppaireo.b t5, t3, s2 # CHECK-ASM: encoding: [0x3b,0x4f,0x2e,0x91] ppaireo.b t5, t3, s2 @@ -906,15 +909,15 @@ pnsrai.h s0, a0, 2 # CHECK-ASM-AND-OBJ: nsrai a4, t3 # CHECK-ASM: encoding: [0x1b,0xc7,0x4e,0x44] nsrai a4, t3, 4 -# CHECK-ASM-AND-OBJ: pnsari.b t5, t5 +# CHECK-ASM-AND-OBJ: pnsrari.b t5, t5 # CHECK-ASM: encoding: [0x1b,0xcf,0x0f,0x51] -pnsari.b t5, t5, 0 -# CHECK-ASM-AND-OBJ: pnsari.h t1, a4 +pnsrari.b t5, t5, 0 +# CHECK-ASM-AND-OBJ: pnsrari.h t1, a4 # CHECK-ASM: encoding: [0x1b,0xc3,0x37,0x52] -pnsari.h t1, a4, 3 -# CHECK-ASM-AND-OBJ: nsari s0, t1 +pnsrari.h t1, a4, 3 +# CHECK-ASM-AND-OBJ: nsrari s0, t1 # CHECK-ASM: encoding: [0x1b,0xc4,0x53,0x54] -nsari s0, t1, 5 +nsrari s0, t1, 5 # CHECK-ASM-AND-OBJ: pnclipi.b t1, a4 # CHECK-ASM: encoding: [0x1b,0xc3,0x77,0x61] pnclipi.b t1, a4, 7 @@ -1266,9 +1269,9 @@ psas.dhx a2, a2, s0 # CHECK-ASM-AND-OBJ: pssa.dhx t3, t3, t3 # CHECK-ASM: encoding: [0x1b,0xee,0xde,0x95] pssa.dhx t3, t3, t3 -# CHECK-ASM-AND-OBJ: paax.dhx t3, t3, a4 +# CHECK-ASM-AND-OBJ: paas.dhx t3, t3, a4 # CHECK-ASM: encoding: [0x1b,0xee,0xfe,0x98] -paax.dhx t3, t3, a4 +paas.dhx t3, t3, a4 # CHECK-ASM-AND-OBJ: pasa.dhx a0, t1, t1 # CHECK-ASM: encoding: [0x1b,0xe5,0x73,0x9c] pasa.dhx a0, t1, t1 diff --git a/llvm/test/MC/RISCV/rv64dc-valid.s b/llvm/test/MC/RISCV/rv64dc-valid.s index 7f2b8c46b7bb6..955b69ab8acc1 100644 --- a/llvm/test/MC/RISCV/rv64dc-valid.s +++ b/llvm/test/MC/RISCV/rv64dc-valid.s @@ -11,28 +11,28 @@ # # RUN: not llvm-mc -triple riscv64 -mattr=+c \ # RUN: -M no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: not llvm-mc -triple riscv64 -M no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM: encoding: [0x7e,0x34] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}} # CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM: encoding: [0xc6,0xbf] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}} # CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM: encoding: [0xf4,0x3f] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}} # CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM: encoding: [0xf0,0xbd] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) and 'D' (Double-Precision Floating-Point) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}} # CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsd fa2, 248(a1) diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s index 628b878c93b1b..4586bb7e657d6 100644 --- a/llvm/test/MC/RISCV/rv64p-valid.s +++ b/llvm/test/MC/RISCV/rv64p-valid.s @@ -472,6 +472,9 @@ ppaire.b s0, s0, s2 # CHECK-ASM-AND-OBJ: ppaire.h t5, a2, a4 # CHECK-ASM: encoding: [0x3b,0x4f,0xe6,0x82] ppaire.h t5, a2, a4 +# CHECK-ASM-AND-OBJ: pack s0, s1, s2 +# CHECK-ASM: encoding: [0x33,0xc4,0x24,0x09] +ppaire.w s0, s1, s2 # CHECK-ASM-AND-OBJ: ppaireo.b a4, s2, t3 # CHECK-ASM: encoding: [0x3b,0x47,0xc9,0x91] ppaireo.b a4, s2, t3 diff --git a/llvm/test/MC/RISCV/rvv/zvabd-invalid.s b/llvm/test/MC/RISCV/rvv/zvabd-invalid.s new file mode 100644 index 0000000000000..ec4529b9289cb --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvabd-invalid.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple=riscv64 --mattr=+zve64x --mattr=+experimental-zvabd %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vwabda.vv v9, v9, v8 +# CHECK-ERROR: [[@LINE-1]]:11: error: the destination vector register group cannot overlap the source vector register group +# CHECK-ERROR-LABEL: vwabda.vv v9, v9, v8 + +vwabdau.vv v9, v9, v8 +# CHECK-ERROR: [[@LINE-1]]:12: error: the destination vector register group cannot overlap the source vector register group +# CHECK-ERROR-LABEL: vwabdau.vv v9, v9, v8 diff --git a/llvm/test/MC/RISCV/rvv/zvabd.s b/llvm/test/MC/RISCV/rvv/zvabd.s new file mode 100644 index 0000000000000..2b994ebf94ba6 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvabd.s @@ -0,0 +1,63 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | llvm-objdump -d --mattr=+v --mattr=+experimental-zvabd --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+v --mattr=+experimental-zvabd %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vabs.v v9, v8 +# CHECK-INST: vabs.v v9, v8 +# CHECK-ENCODING: [0xd7,0x24,0x88,0x4a] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4a8824d7 + +vabd.vv v10, v9, v8 +# CHECK-INST: vabd.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x46] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 46942557 + +vabd.vv v10, v9, v8, v0.t +# CHECK-INST: vabd.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x44] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 44942557 + +vabdu.vv v10, v9, v8 +# CHECK-INST: vabdu.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x4e] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4e942557 + +vabdu.vv v10, v9, v8, v0.t +# CHECK-INST: vabdu.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x4c] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 4c942557 + +vwabda.vv v10, v9, v8 +# CHECK-INST: vwabda.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x56] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 56942557 + +vwabda.vv v10, v9, v8, v0.t +# CHECK-INST: vwabda.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 54942557 + +vwabdau.vv v10, v9, v8 +# CHECK-INST: vwabdau.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x5a] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 5a942557 + +vwabdau.vv v10, v9, v8, v0.t +# CHECK-INST: vwabdau.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x58] +# CHECK-ERROR: instruction requires the following: 'Zvabd' (Vector Absolute Difference){{$}} +# CHECK-UNKNOWN: 58942557 diff --git a/llvm/test/MC/RISCV/rvzcmop-valid.s b/llvm/test/MC/RISCV/rvzcmop-valid.s index dd5d26ac5dd0c..8d8ba76e7e93b 100644 --- a/llvm/test/MC/RISCV/rvzcmop-valid.s +++ b/llvm/test/MC/RISCV/rvzcmop-valid.s @@ -9,7 +9,8 @@ # RUN: | llvm-objdump --mattr=+zcmop -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# CHECK-ASM-AND-OBJ: c.mop.1 +# c.mop.1 is an alias for c.sspush ra. +# CHECK-ASM-AND-OBJ: c.sspush ra # CHECK-ASM: encoding: [0x81,0x60] c.mop.1 @@ -17,7 +18,8 @@ c.mop.1 # CHECK-ASM: encoding: [0x81,0x61] c.mop.3 -# CHECK-ASM-AND-OBJ: c.mop.5 +# c.mop.5 is an alias for c.sspopchk t0. +# CHECK-ASM-AND-OBJ: c.sspopchk t0 # CHECK-ASM: encoding: [0x81,0x62] c.mop.5 diff --git a/llvm/test/MC/RISCV/rvzihintntl-invalid.s b/llvm/test/MC/RISCV/rvzihintntl-invalid.s index af8c4075c3552..9fc647100fcf4 100644 --- a/llvm/test/MC/RISCV/rvzihintntl-invalid.s +++ b/llvm/test/MC/RISCV/rvzihintntl-invalid.s @@ -1,5 +1,11 @@ # RUN: not llvm-mc -triple riscv32 -mattr=+zihintntl < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+zihintntl < %s 2>&1 | FileCheck %s +# +# ntl.* hints are always available even without Zihintntl +# (riscv-non-isa/riscv-elf-psabi-doc#474). +# +# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s ntl.p1 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction ntl.pall 2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction @@ -10,4 +16,3 @@ ntl.p1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction ntl.pall t0, t1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction ntl.s1 t0, t1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction ntl.all t0, t1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction - diff --git a/llvm/test/MC/RISCV/rvzihintntl-valid.s b/llvm/test/MC/RISCV/rvzihintntl-valid.s index 415070a3eee29..1971b0b7a18d8 100644 --- a/llvm/test/MC/RISCV/rvzihintntl-valid.s +++ b/llvm/test/MC/RISCV/rvzihintntl-valid.s @@ -8,6 +8,20 @@ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl < %s \ # RUN: | llvm-objdump --mattr=+zihintntl -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# ntl.* hints are always available even without Zihintntl +# (riscv-non-isa/riscv-elf-psabi-doc#474). +# +# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \ +# RUN: | llvm-objdump -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \ +# RUN: | llvm-objdump -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: add zero, zero, sp # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00] diff --git a/llvm/test/MC/RISCV/rvzihintntlc-valid.s b/llvm/test/MC/RISCV/rvzihintntlc-valid.s index 53ffd7fbc879c..c8fb3c27cde18 100644 --- a/llvm/test/MC/RISCV/rvzihintntlc-valid.s +++ b/llvm/test/MC/RISCV/rvzihintntlc-valid.s @@ -8,8 +8,25 @@ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zihintntl,+c < %s \ # RUN: | llvm-objdump --mattr=+zihintntl,+c -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: not llvm-mc %s -triple=riscv32 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s -# RUN: not llvm-mc %s -triple=riscv64 -mattr=+zihintntl 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s +# +# c.ntl.* hints are available when C extension is present, even without +# enabling Zihintntl (riscv-non-isa/riscv-elf-psabi-doc#474). +# +# RUN: llvm-mc %s -triple=riscv32 -mattr=+c -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+c -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c < %s \ +# RUN: | llvm-objdump --mattr=+c -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c < %s \ +# RUN: | llvm-objdump --mattr=+c -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# +# c.ntl.* still require the C extension. +# +# RUN: not llvm-mc %s -triple=riscv32 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s +# RUN: not llvm-mc %s -triple=riscv64 2>&1 | FileCheck -check-prefix=CHECK-NO-C %s # CHECK-ASM-AND-OBJ: ntl.p1 # CHECK-ASM: encoding: [0x33,0x00,0x20,0x00] diff --git a/llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s b/llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s index d505029ae4637..0c57a12dff18f 100644 --- a/llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvzihintpause-aliases-valid.s @@ -18,6 +18,20 @@ # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zihintpause < %s \ # RUN: | llvm-objdump --mattr=+zihintpause -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# +# pause is always available even without Zihintpause +# (riscv-non-isa/riscv-elf-psabi-doc#474). +# +# RUN: llvm-mc %s -triple=riscv32 -M no-aliases \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc %s -triple=riscv32 \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d -r -M no-aliases - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s # CHECK-S-OBJ-NOALIAS: fence w, 0 # CHECK-S-OBJ: pause diff --git a/llvm/test/MC/RISCV/zicfilp-invalid.s b/llvm/test/MC/RISCV/zicfilp-invalid.s index bff989fa204a3..30d8be2f534a3 100644 --- a/llvm/test/MC/RISCV/zicfilp-invalid.s +++ b/llvm/test/MC/RISCV/zicfilp-invalid.s @@ -2,6 +2,13 @@ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicfilp -M no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# +# lpad is always available even without Zicfilp (riscv-non-isa/riscv-elf-psabi-doc#474). +# +# RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# RUN: not llvm-mc -triple riscv64 -M no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # CHECK-NO-EXT: immediate must be an integer in the range [0, 1048575] lpad 1048576 diff --git a/llvm/test/MC/RISCV/zicfilp-valid.s b/llvm/test/MC/RISCV/zicfilp-valid.s index f61cad8d85d53..c2ccefa544ba9 100644 --- a/llvm/test/MC/RISCV/zicfilp-valid.s +++ b/llvm/test/MC/RISCV/zicfilp-valid.s @@ -9,13 +9,21 @@ # RUN: | llvm-objdump --mattr=+experimental-zicfilp --no-print-imm-hex -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # -# RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s -# RUN: not llvm-mc -triple riscv64 -M no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s +# lpad is always available in the assembler and disassembler, even without +# enabling Zicfilp (riscv-non-isa/riscv-elf-psabi-doc#474). +# +# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM %s +# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \ +# RUN: | llvm-objdump --no-print-imm-hex -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: lpad 22 # CHECK-ASM: auipc zero, 22 # CHECK-ASM: encoding: [0x17,0x60,0x01,0x00] -# CHECK-NO-EXT: instruction requires the following: 'Zicfilp' (Landing pad) lpad 22 diff --git a/llvm/test/MC/RISCV/zicfiss-valid.s b/llvm/test/MC/RISCV/zicfiss-valid.s index 5b2ab8d326651..5f6d70dedcf25 100644 --- a/llvm/test/MC/RISCV/zicfiss-valid.s +++ b/llvm/test/MC/RISCV/zicfiss-valid.s @@ -9,6 +9,10 @@ # RUN: | llvm-objdump --mattr=+a,+experimental-zicfiss -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ-RV64,CHECK-ASM-AND-OBJ %s # +# Zicfiss MOP-based instructions (sspopchk, ssrdp, sspush) only require Zimop, +# not Zicfiss. SSAMOSWAP still requires Zicfiss. +# (riscv-non-isa/riscv-elf-psabi-doc#474) +# # RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: not llvm-mc -triple riscv64 -defsym=RV64=1 -M no-aliases -show-encoding < %s 2>&1 \ @@ -16,47 +20,47 @@ # CHECK-ASM-AND-OBJ: sspopchk ra # CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspopchk x1 # CHECK-ASM-AND-OBJ: sspopchk ra # CHECK-ASM: encoding: [0x73,0xc0,0xc0,0xcd] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspopchk ra # CHECK-ASM-AND-OBJ: sspopchk t0 # CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspopchk x5 # CHECK-ASM-AND-OBJ: sspopchk t0 # CHECK-ASM: encoding: [0x73,0xc0,0xc2,0xcd] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspopchk t0 # CHECK-ASM-AND-OBJ: sspush ra # CHECK-ASM: encoding: [0x73,0x40,0x10,0xce] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspush x1 # CHECK-ASM-AND-OBJ: sspush ra # CHECK-ASM: encoding: [0x73,0x40,0x10,0xce] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspush ra -# check-asm-and-obj: sspush t0 -# check-asm: encoding: [0x73,0x40,0x50,0xce] -# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-ASM-AND-OBJ: sspush t0 +# CHECK-ASM: encoding: [0x73,0x40,0x50,0xce] +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspush x5 -# check-asm-and-obj: sspush t0 -# check-asm: encoding: [0x73,0x40,0x50,0xce] -# check-no-ext: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-ASM-AND-OBJ: sspush t0 +# CHECK-ASM: encoding: [0x73,0x40,0x50,0xce] +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) sspush t0 # CHECK-ASM-AND-OBJ: ssrdp ra # CHECK-ASM: encoding: [0xf3,0x40,0xc0,0xcd] -# CHECK-NO-EXT: error: instruction requires the following: 'Zicfiss' (Shadow stack) +# CHECK-NO-EXT: error: instruction requires the following: 'Zimop' (May-Be-Operations) ssrdp ra # CHECK-ASM-AND-OBJ: ssamoswap.w a4, ra, (s0) diff --git a/llvm/test/MC/WebAssembly/common-error.s b/llvm/test/MC/WebAssembly/common-error.s new file mode 100644 index 0000000000000..38c8fbca352b2 --- /dev/null +++ b/llvm/test/MC/WebAssembly/common-error.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple=wasm32-unknown-unknown -filetype=obj %s 2>&1 | FileCheck %s + +# CHECK:common-error.s:5:9: error: common symbols are not yet implemented for Wasm: x +# CHECK:common-error.s:6:9: error: common symbols are not yet implemented for Wasm: y + .comm x,4,4 + .comm y,4,4 diff --git a/llvm/test/MC/X86/x86_long_nop.s b/llvm/test/MC/X86/x86_long_nop.s index b79403bb5f1ec..2c5fe3acde26c 100644 --- a/llvm/test/MC/X86/x86_long_nop.s +++ b/llvm/test/MC/X86/x86_long_nop.s @@ -21,6 +21,8 @@ # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver4 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver5 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver5 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15 +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver6 %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15 +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver6 | llvm-objdump -d --no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15 # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=nehalem %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=westmere %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP10 %s # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=sandybridge %s | llvm-objdump -d --no-show-raw-insn - | FileCheck --check-prefix=LNOP15 %s diff --git a/llvm/test/MachineVerifier/RISCV/subreg-liveness.mir b/llvm/test/MachineVerifier/RISCV/subreg-liveness.mir index 3c7b70efe7199..c4ff437e5d4ad 100644 --- a/llvm/test/MachineVerifier/RISCV/subreg-liveness.mir +++ b/llvm/test/MachineVerifier/RISCV/subreg-liveness.mir @@ -18,7 +18,7 @@ body: | ; CHECK-LABEL: name: func ; CHECK: liveins: $v0, $v8, $v9, $v10, $v11 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype diff --git a/llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml b/llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml index fbbedd4acfc99..ac2b98e336486 100644 --- a/llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml +++ b/llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml @@ -234,6 +234,10 @@ # RUN: llvm-readobj -S --file-headers %t.o.AMDGCN_GFX1153 | FileCheck --check-prefixes=ELF-AMDGCN-ALL,ELF-AMDGCN-GFX1153 %s # RUN: obj2yaml %t.o.AMDGCN_GFX1153 | FileCheck --check-prefixes=YAML-AMDGCN-ALL,YAML-AMDGCN-GFX1153 %s +# RUN: sed -e 's//64/' -e 's//AMDGCN_GFX1170/' %s | yaml2obj -o %t.o.AMDGCN_GFX1170 +# RUN: llvm-readobj -S --file-headers %t.o.AMDGCN_GFX1170 | FileCheck --check-prefixes=ELF-AMDGCN-ALL,ELF-AMDGCN-GFX1170 %s +# RUN: obj2yaml %t.o.AMDGCN_GFX1170 | FileCheck --check-prefixes=YAML-AMDGCN-ALL,YAML-AMDGCN-GFX1170 %s + # RUN: sed -e 's//64/' -e 's//AMDGCN_GFX1200/' %s | yaml2obj -o %t.o.AMDGCN_GFX1200 # RUN: llvm-readobj -S --file-headers %t.o.AMDGCN_GFX1200 | FileCheck --check-prefixes=ELF-AMDGCN-ALL,ELF-AMDGCN-GFX1200 %s # RUN: obj2yaml %t.o.AMDGCN_GFX1200 | FileCheck --check-prefixes=YAML-AMDGCN-ALL,YAML-AMDGCN-GFX1200 %s @@ -473,6 +477,9 @@ # ELF-AMDGCN-GFX1153: EF_AMDGPU_MACH_AMDGCN_GFX1153 (0x58) # YAML-AMDGCN-GFX1153: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX1153 ] +# ELF-AMDGCN-GFX1170: EF_AMDGPU_MACH_AMDGCN_GFX1170 (0x5D) +# YAML-AMDGCN-GFX1170: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX1170 ] + # ELF-AMDGCN-GFX1200: EF_AMDGPU_MACH_AMDGCN_GFX1200 (0x48) # YAML-AMDGCN-GFX1200: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX1200 ] diff --git a/llvm/test/ObjectYAML/Offload/malformed-entry-size.yaml b/llvm/test/ObjectYAML/Offload/malformed-entries-count.yaml similarity index 94% rename from llvm/test/ObjectYAML/Offload/malformed-entry-size.yaml rename to llvm/test/ObjectYAML/Offload/malformed-entries-count.yaml index 3194607ae39a5..bb2a34277963f 100644 --- a/llvm/test/ObjectYAML/Offload/malformed-entry-size.yaml +++ b/llvm/test/ObjectYAML/Offload/malformed-entries-count.yaml @@ -1,6 +1,6 @@ # RUN: yaml2obj %s | not obj2yaml 2>&1 | FileCheck %s !Offload -EntrySize: 999999999 +EntriesCount: 999999999 Members: - ImageKind: IMG_Cubin OffloadKind: OFK_OpenMP diff --git a/llvm/test/ObjectYAML/Offload/malformed-offset.yaml b/llvm/test/ObjectYAML/Offload/malformed-offset.yaml index 03c0431053cce..5aecfffd937bf 100644 --- a/llvm/test/ObjectYAML/Offload/malformed-offset.yaml +++ b/llvm/test/ObjectYAML/Offload/malformed-offset.yaml @@ -1,6 +1,6 @@ # RUN: yaml2obj %s | not obj2yaml 2>&1 | FileCheck %s !Offload -EntryOffset: 999999999 +EntriesOffset: 999999999 Members: - ImageKind: IMG_Cubin OffloadKind: OFK_OpenMP diff --git a/llvm/test/ObjectYAML/Offload/malformed-version.yaml b/llvm/test/ObjectYAML/Offload/malformed-version.yaml index f9279a52e2764..99383491acce0 100644 --- a/llvm/test/ObjectYAML/Offload/malformed-version.yaml +++ b/llvm/test/ObjectYAML/Offload/malformed-version.yaml @@ -1,6 +1,6 @@ # RUN: yaml2obj %s | not obj2yaml 2>&1 | FileCheck %s !Offload -Version: 2 +Version: 3 Members: - ImageKind: IMG_Cubin OffloadKind: OFK_OpenMP diff --git a/llvm/test/ObjectYAML/Offload/multiple_members.yaml b/llvm/test/ObjectYAML/Offload/multiple_members.yaml index ac73d16e429a9..b07f7acd1f782 100644 --- a/llvm/test/ObjectYAML/Offload/multiple_members.yaml +++ b/llvm/test/ObjectYAML/Offload/multiple_members.yaml @@ -18,7 +18,14 @@ Members: Value: "amdgcn-amd-amdhsa" - Key: "arch" Value: "gfx908" - Content: "cafefeed" + Content: "cafefeed" + - ImageKind: IMG_Object + OffloadKind: OFK_SYCL + # OIF_Metadata + Flags: 1 + String: + - Key: "device" + Value: "gpu" # CHECK: --- !Offload # CHECK-NEXT: Members: @@ -40,4 +47,10 @@ Members: # CHECK-NEXT: - Key: arch # CHECK-NEXT: Value: gfx908 # CHECK-NEXT: Content: CAFEFEED +# CHECK-NEXT: - ImageKind: IMG_Object +# CHECK-NEXT: OffloadKind: OFK_SYCL +# CHECK-NEXT: Flags: 1 +# CHECK-NEXT: String: +# CHECK-NEXT: - Key: device +# CHECK-NEXT: Value: gpu # CHECK-NEXT: ... diff --git a/llvm/test/Other/opt-bisect-new-pass-manager.ll b/llvm/test/Other/opt-bisect-new-pass-manager.ll index 8f8078d4d8409..8e7915bd0db75 100644 --- a/llvm/test/Other/opt-bisect-new-pass-manager.ll +++ b/llvm/test/Other/opt-bisect-new-pass-manager.ll @@ -90,6 +90,18 @@ ; CHECK-LIMIT-MULTI-PASS: BISECT: NOT running pass (8) function-attrs on (f4) ; CHECK-LIMIT-MULTI-PASS: BISECT: NOT running pass (9) early-cse on f4 +; RUN: opt -disable-output -debug-pass-manager \ +; RUN: -passes=lowertypetests -opt-bisect-limit=-1 %s 2>&1 \ +; RUN: | FileCheck %s --check-prefix=LTT-ALL +; LTT-ALL-NOT: BISECT: {{.*}}LowerTypeTestsPass +; LTT-ALL: Running pass: LowerTypeTestsPass + +; RUN: opt -disable-output -debug-pass-manager \ +; RUN: -passes=lowertypetests -opt-bisect-limit=0 %s 2>&1 \ +; RUN: | FileCheck %s --check-prefix=LTT-REQUIRED +; LTT-REQUIRED-NOT: BISECT: {{.*}}LowerTypeTestsPass +; LTT-REQUIRED: Running pass: LowerTypeTestsPass + ; Make sure we don't skip writing the output to stdout. ; RUN: opt %s -opt-bisect-limit=0 -passes=early-cse | opt -S | FileCheck %s -check-prefix=CHECK-OUTPUT ; RUN: opt %s -opt-bisect-limit=0 -passes=early-cse -S | FileCheck %s -check-prefix=CHECK-OUTPUT diff --git a/llvm/test/Other/opt-override-denormal-fp-math-f32.ll b/llvm/test/Other/opt-override-denormal-fp-math-f32.ll index d7ee5b8cd1d2b..845fca9e1b568 100644 --- a/llvm/test/Other/opt-override-denormal-fp-math-f32.ll +++ b/llvm/test/Other/opt-override-denormal-fp-math-f32.ll @@ -14,10 +14,10 @@ entry: ret i32 0 } -; ALL-DAG: attributes [[ATTR]] = { nounwind "denormal-fp-math-f32"="preserve-sign,ieee" } -; IEEE-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math-f32"="ieee,ieee" } -; PRESERVESIGN-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -; POSITIVEZERO-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math-f32"="positive-zero,positive-zero" } +; ALL-DAG: attributes [[ATTR]] = { nounwind denormal_fpenv(float: preservesign|ieee) } +; IEEE-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(ieee) } +; PRESERVESIGN-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(float: preservesign) } +; POSITIVEZERO-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(float: positivezero) } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,ieee" } +attributes #1 = { nounwind denormal_fpenv(float: preservesign|ieee) } diff --git a/llvm/test/Other/opt-override-denormal-fp-math-mixed.ll b/llvm/test/Other/opt-override-denormal-fp-math-mixed.ll index 306fc78a2183a..59e0b32035b0a 100644 --- a/llvm/test/Other/opt-override-denormal-fp-math-mixed.ll +++ b/llvm/test/Other/opt-override-denormal-fp-math-mixed.ll @@ -24,19 +24,19 @@ entry: ret i32 0 } -; ALL-DAG: attributes [[ATTR]] = { nounwind "denormal-fp-math"="preserve-sign,ieee" "denormal-fp-math-f32"="preserve-sign,ieee" } +; ALL-DAG: attributes [[ATTR]] = { nounwind denormal_fpenv(preservesign|ieee) } -; IEEE-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="ieee,ieee" } -; PRESERVESIGN-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -; POSITIVEZERO-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="positive-zero,positive-zero" } +; IEEE-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(ieee) } +; PRESERVESIGN-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(preservesign) } +; POSITIVEZERO-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(positivezero) } -; IEEEF32-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math-f32"="ieee,ieee" } -; PRESERVESIGNF32-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -; POSITIVEZEROF32-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math-f32"="positive-zero,positive-zero" } +; IEEEF32-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(ieee) } +; PRESERVESIGNF32-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(float: preservesign) } +; POSITIVEZEROF32-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(float: positivezero) } -; IEEE-BOTH-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" } -; PRESERVESIGN-BOTH-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -; POSITIVEZERO-BOTH-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="positive-zero,positive-zero" "denormal-fp-math-f32"="positive-zero,positive-zero" } +; IEEE-BOTH-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(ieee) } +; PRESERVESIGN-BOTH-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(preservesign) } +; POSITIVEZERO-BOTH-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(positivezero) } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math"="preserve-sign,ieee" "denormal-fp-math-f32"="preserve-sign,ieee" } +attributes #1 = { nounwind denormal_fpenv(preservesign|ieee, float: preservesign|ieee) } diff --git a/llvm/test/Other/opt-override-denormal-fp-math.ll b/llvm/test/Other/opt-override-denormal-fp-math.ll index f108ac64045e2..6618abd86aeb6 100644 --- a/llvm/test/Other/opt-override-denormal-fp-math.ll +++ b/llvm/test/Other/opt-override-denormal-fp-math.ll @@ -14,10 +14,10 @@ entry: ret i32 0 } -; ALL-DAG: attributes [[ATTR]] = { nounwind "denormal-fp-math"="preserve-sign,ieee" } -; IEEE-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="ieee,ieee" } -; PRESERVESIGN-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -; POSITIVEZERO-DAG: attributes [[NOATTR]] = { nounwind "denormal-fp-math"="positive-zero,positive-zero" } +; ALL-DAG: attributes [[ATTR]] = { nounwind denormal_fpenv(preservesign|ieee) } +; IEEE-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(ieee) } +; PRESERVESIGN-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(preservesign) } +; POSITIVEZERO-DAG: attributes [[NOATTR]] = { nounwind denormal_fpenv(positivezero) } attributes #0 = { nounwind } -attributes #1 = { nounwind "denormal-fp-math"="preserve-sign,ieee" } +attributes #1 = { nounwind denormal_fpenv(preservesign|ieee) } diff --git a/llvm/test/Other/opt-pipeline-attributor-enable.ll b/llvm/test/Other/opt-pipeline-attributor-enable.ll new file mode 100644 index 0000000000000..5e79f8b68ceb3 --- /dev/null +++ b/llvm/test/Other/opt-pipeline-attributor-enable.ll @@ -0,0 +1,24 @@ +; RUN: opt -S -passes='default' -attributor-enable=cgscc-light -print-pipeline-passes %s 2>&1 | FileCheck -check-prefix=CGSCCLIGHT %s +; RUN: opt -S -passes='default' -attributor-enable=module-light -print-pipeline-passes %s 2>&1 | FileCheck -check-prefix=MODULELIGHT %s +; RUN: opt -S -passes='default' -attributor-enable=light -print-pipeline-passes %s 2>&1 | FileCheck -check-prefix=LIGHT %s + +; RUN: opt -S -passes='default' -attributor-enable=cgscc -print-pipeline-passes %s 2>&1 | FileCheck -check-prefix=CGSCC %s +; RUN: opt -S -passes='default' -attributor-enable=module -print-pipeline-passes %s 2>&1 | FileCheck -check-prefix=MODULE %s +; RUN: opt -S -passes='default' -attributor-enable=full -print-pipeline-passes %s 2>&1 | FileCheck -check-prefix=FULL %s + +; CGSCCLIGHT: attributor-light-cgscc,function-attrs +; MODULELIGHT: openmp-opt,attributor-light,ipsccp + +; LIGHT: openmp-opt,attributor-light, +; LIGHT-SAME: attributor-light-cgscc,function-attrs + + +; MODULE: ,openmp-opt,attributor,ipsccp + +; CGSCC: inline,attributor-cgscc,function-attrs + +; FULL: openmp-opt,attributor, +; FULL-SAME: attributor-cgscc,function-attrs +define ptr @return_arg(ptr %arg) { + ret ptr %arg +} diff --git a/llvm/test/TableGen/CPtrWildcard.td b/llvm/test/TableGen/CPtrWildcard.td index a8b73dd28c185..6e09fce70d83d 100644 --- a/llvm/test/TableGen/CPtrWildcard.td +++ b/llvm/test/TableGen/CPtrWildcard.td @@ -10,18 +10,22 @@ // CHECK-NEXT:/* 6*/ OPC_Scope /*2 children */, 9, // ->17 // CHECK-NEXT:/* 8*/ OPC_CheckChild1Type, /*MVT::c64*/4|128,2/*260*/, // CHECK-NEXT:/* 11*/ OPC_MorphNodeTo1None, TARGET_VAL(MyTarget::C64_TO_I64), -// CHECK-NEXT: MVT::i64, 1/*#Ops*/, 0, +// CHECK-NEXT: MVT::i64, 1/*#Ops*/, /*OperandList*/0, // Ops = #0 // CHECK-NEXT: // Src: (intrinsic_wo_chain:{ *:[i64] } [[#]]:{ *:[iPTR] }, c64:{ *:[c64] }:$src) - Complexity = 8 // CHECK-NEXT: // Dst: (C64_TO_I64:{ *:[i64] } ?:{ *:[c64] }:$src) // CHECK-NEXT:/* 17*/ /*Scope*/ 9, // ->27 // CHECK-NEXT:/* 18*/ OPC_CheckChild1Type, /*MVT::c128*/5|128,2/*261*/, // CHECK-NEXT:/* 21*/ OPC_MorphNodeTo1None, TARGET_VAL(MyTarget::C128_TO_I64), -// CHECK-NEXT: MVT::i64, 1/*#Ops*/, 0, +// CHECK-NEXT: MVT::i64, 1/*#Ops*/, /*OperandList*/0, // Ops = #0 // CHECK-NEXT: // Src: (intrinsic_wo_chain:{ *:[i64] } [[#]]:{ *:[iPTR] }, c128:{ *:[c128] }:$src) - Complexity = 8 // CHECK-NEXT: // Dst: (C128_TO_I64:{ *:[i64] } ?:{ *:[c128] }:$src) // CHECK-NEXT:/* 27*/ 0, // End of Scope // CHECK-NEXT: }; // Total Array size is 28 bytes +// CHECK: static const uint8_t OperandLists[] = { +// CHECK-NEXT: /* 0 */ 0, +// CHECK-NEXT: } + include "llvm/Target/Target.td" def my_cap_ty : LLVMQualPointerType<200> { diff --git a/llvm/test/TableGen/DecoderEmitter/large-islands.td b/llvm/test/TableGen/DecoderEmitter/large-islands.td new file mode 100644 index 0000000000000..541cba495dc3b --- /dev/null +++ b/llvm/test/TableGen/DecoderEmitter/large-islands.td @@ -0,0 +1,38 @@ +// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s + +include "llvm/Target/Target.td" + +class I opcode> : Instruction { + let InOperandList = ins; + let OutOperandList = outs; + + bits<5> dst; + bits<5> src0; + bits<5> src1; + + int Size = 16; + bits<128> Inst; + + let Inst{4...0} = opcode; + let Inst{9...5} = dst; + let Inst{14...10} = src0; + let Inst{19...15} = src1; + + let Inst{127...20} = 0xdeadbeef; +} + +def Reg : Register<"reg">; + +def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>; + +def IAdd : I<(outs Regs:$dst), (ins Regs:$src0, Regs:$src1), 0b10101>; + +// CHECK-LABEL: static const uint8_t DecoderTable128[20] = { +// CHECK-NEXT: OPC_CheckField, 84, 44, 0, // 0: check Inst[127:84] == 0x0 +// CHECK-NEXT: OPC_CheckField, 20, 64, 239, 253, 182, 245, 13, + +def II : InstrInfo; + +def MyTarget : Target { + let InstructionSet = II; +} diff --git a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td index 4427c0d4bc663..777fabb8fdefb 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/Subreg.td +++ b/llvm/test/TableGen/GlobalISelEmitter/Subreg.td @@ -234,8 +234,8 @@ def : Pat<(i16 (trunc DOP:$src)), // Test that we can import SUBREG_TO_REG def : Pat<(i32 (zext SOP:$src)), - (SUBREG_TO_REG (i64 0), (SUBSOME_INSN SOP:$src), sub0)>; -// CHECK-LABEL: (zext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i32] } 0:{ *:[i64] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }) + (SUBREG_TO_REG (SUBSOME_INSN SOP:$src), sub0)>; +// CHECK-LABEL: (zext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i32] } (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast(RegState::Define)), @@ -243,10 +243,9 @@ def : Pat<(i32 (zext SOP:$src)), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, // CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), // CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: // GIR_Coverage, 11, // CHECK-NEXT: GIR_EraseRootFromParent_Done, diff --git a/llvm/test/TableGen/MacroFusion.td b/llvm/test/TableGen/MacroFusion.td index e4034bfa108cc..ca795efd141ea 100644 --- a/llvm/test/TableGen/MacroFusion.td +++ b/llvm/test/TableGen/MacroFusion.td @@ -72,19 +72,22 @@ def TestFirstSameRegFusion: Fusion<"test-first-same-reg-fusion", "HasTestFirstSa // CHECK-PREDICATOR-NEXT: #undef GET_Test_MACRO_FUSION_PRED_DECL // CHECK-PREDICATOR-EMPTY: // CHECK-PREDICATOR-NEXT: namespace llvm { +// CHECK-PREDICATOR-EMPTY: // CHECK-PREDICATOR-NEXT: bool isTestBothFusionPredicate(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); // CHECK-PREDICATOR-NEXT: bool isTestCommutableFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); // CHECK-PREDICATOR-NEXT: bool isTestFirstSameRegFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); // CHECK-PREDICATOR-NEXT: bool isTestFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); // CHECK-PREDICATOR-NEXT: bool isTestSingleFusion(const TargetInstrInfo &, const TargetSubtargetInfo &, const MachineInstr *, const MachineInstr &); -// CHECK-PREDICATOR-NEXT: } // end namespace llvm // CHECK-PREDICATOR-EMPTY: -// CHECK-PREDICATOR-NEXT: #endif +// CHECK-PREDICATOR-NEXT: } // namespace llvm +// CHECK-PREDICATOR-EMPTY: +// CHECK-PREDICATOR-NEXT: #endif // GET_Test_MACRO_FUSION_PRED_DECL // CHECK-PREDICATOR: #ifdef GET_Test_MACRO_FUSION_PRED_IMPL // CHECK-PREDICATOR-NEXT: #undef GET_Test_MACRO_FUSION_PRED_IMPL // CHECK-PREDICATOR-EMPTY: // CHECK-PREDICATOR-NEXT: namespace llvm { +// CHECK-PREDICATOR-EMPTY: // CHECK-PREDICATOR-NEXT: bool isTestBothFusionPredicate( // CHECK-PREDICATOR-NEXT: const TargetInstrInfo &TII, // CHECK-PREDICATOR-NEXT: const TargetSubtargetInfo &STI, @@ -256,9 +259,10 @@ def TestFirstSameRegFusion: Fusion<"test-first-same-reg-fusion", "HasTestFirstSa // CHECK-PREDICATOR-NEXT: } // CHECK-PREDICATOR-NEXT: return true; // CHECK-PREDICATOR-NEXT: } -// CHECK-PREDICATOR-NEXT: } // end namespace llvm // CHECK-PREDICATOR-EMPTY: -// CHECK-PREDICATOR-NEXT: #endif +// CHECK-PREDICATOR-NEXT: } // namespace llvm +// CHECK-PREDICATOR-EMPTY: +// CHECK-PREDICATOR-NEXT: #endif // GET_Test_MACRO_FUSION_PRED_IMPL // Check that we have generated target subfeature. // CHECK-SUBTARGET: { "test-both-fusion-predicate", "Test BothFusionPredicate", Test::TestBothFusionPredicate diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td index 508b098c9f44e..83531b9248f92 100644 --- a/llvm/test/TableGen/RegClassByHwMode.td +++ b/llvm/test/TableGen/RegClassByHwMode.td @@ -212,6 +212,7 @@ include "Common/RegClassByHwModeCommon.td" // ISEL-SDAG-NEXT: OPC_CheckPredicate1, // Predicate_store // ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0, // ISEL-SDAG-NEXT: OPC_MorphNodeTo0, TARGET_VAL(MyTarget::MY_STORE), 0|OPFL_Chain|OPFL_MemRefs, +// ISEL-SDAG-NEXT: 2/*#Ops*/, /*OperandList*/1, // Ops = #1 #2 // ISEL-SDAG: /*SwitchOpcode*/ {{[0-9]+}}, TARGET_VAL(ISD::LOAD), // ISEL-SDAG-NEXT: OPC_RecordMemRef, @@ -223,6 +224,12 @@ include "Common/RegClassByHwModeCommon.td" // ISEL-SDAG-NEXT: OPC_CheckTypeI64, // ISEL-SDAG-NEXT: OPC_EmitMergeInputChains1_0, // ISEL-SDAG-NEXT: OPC_MorphNodeToByHwMode, TARGET_VAL(MyTarget::MY_LOAD), 0|OPFL_Chain|OPFL_MemRefs, +// ISEL-SDAG-NEXT: 1/*#VTs*/, /*{(*:i64),(m1:i64),(m2:i64)}*/0, 1/*#Ops*/, /*OperandList*/0, // Ops = #1 + +// ISEL-SDAG: static const uint8_t OperandLists[] = { +// ISEL-SDAG-NEXT: /* 0 */ 1, +// ISEL-SDAG-NEXT: /* 1 */ 1, 2, +// ISEL-SDAG-NEXT: } diff --git a/llvm/test/TableGen/TargetLibraryInfo.td b/llvm/test/TableGen/TargetLibraryInfo.td index ca6d16e236bda..d88e1b6d58d5a 100644 --- a/llvm/test/TableGen/TargetLibraryInfo.td +++ b/llvm/test/TableGen/TargetLibraryInfo.td @@ -13,7 +13,7 @@ def cabs : TargetLibCall< "cabs", ? /* Checked manually. */>; // CHECK: #ifdef GET_TARGET_LIBRARY_INFO_ENUM // CHECK-NEXT: #undef GET_TARGET_LIBRARY_INFO_ENUM -// CHECK-NEXT: enum LibFunc : unsigned { +// CHECK: enum LibFunc : unsigned { // CHECK-NEXT: NotLibFunc = 0, // CHECK-NEXT: LibFunc_cosf, // CHECK-NEXT: LibFunc_sinf, @@ -24,7 +24,7 @@ def cabs : TargetLibCall< "cabs", ? /* Checked manually. */>; // CHECK-NEXT: End_LibFunc = NumLibFuncs, // CHECK-NEXT: Begin_LibFunc = LibFunc_cosf, // CHECK-NEXT: }; -// CHECK-NEXT: #endif +// CHECK: #endif // GET_TARGET_LIBRARY_INFO_ENUM // CHECK: #ifdef GET_TARGET_LIBRARY_INFO_STRING_TABLE // CHECK-NEXT: #undef GET_TARGET_LIBRARY_INFO_STRING_TABLE @@ -64,18 +64,18 @@ def cabs : TargetLibCall< "cabs", ? /* Checked manually. */>; // CHECK-NEXT: 6, // CHECK-NEXT: 4, // CHECK-NEXT: }; -// CHECK-NEXT: #endif +// CHECK: #endif // GET_TARGET_LIBRARY_INFO_STRING_TABLE // CHECK: #ifdef GET_TARGET_LIBRARY_INFO_IMPL_DECL // CHECK-NEXT: #undef GET_TARGET_LIBRARY_INFO_IMPL_DECL -// CHECK-NEXT: LLVM_ABI static const llvm::StringTable StandardNamesStrTable; +// CHECK: LLVM_ABI static const llvm::StringTable StandardNamesStrTable; // CHECK-NEXT: LLVM_ABI static const llvm::StringTable::Offset StandardNamesOffsets[6]; // CHECK-NEXT: LLVM_ABI static const uint8_t StandardNamesSizeTable[6]; -// CHECK-NEXT: #endif +// CHECK: #endif // GET_TARGET_LIBRARY_INFO_IMPL_DECL // CHECK: #ifdef GET_TARGET_LIBRARY_INFO_SIGNATURE_TABLE // CHECK-NEXT: #undef GET_TARGET_LIBRARY_INFO_SIGNATURE_TABLE -// CHECK-NEXT: enum FuncArgTypeID : char { +// CHECK: enum FuncArgTypeID : char { // CHECK-NEXT: NoFuncArgType = 0, // CHECK-NEXT: Void, // CHECK-NEXT: Bool, @@ -112,4 +112,4 @@ def cabs : TargetLibCall< "cabs", ? /* Checked manually. */>; // CHECK-NEXT: 0, // printf // CHECK-NEXT: 3, // cabs // CHECK-NEXT: }; -// CHECK-NEXT: #endif +// CHECK: #endif // GET_TARGET_LIBRARY_INFO_SIGNATURE_TABLE diff --git a/llvm/test/TableGen/bare-minimum-psets.td b/llvm/test/TableGen/bare-minimum-psets.td index 25e0bd2a83d1d..f0cc2b045e396 100644 --- a/llvm/test/TableGen/bare-minimum-psets.td +++ b/llvm/test/TableGen/bare-minimum-psets.td @@ -42,10 +42,10 @@ def MyTarget : Target; // CHECK-LABEL: // Register pressure sets enum. // CHECK-NEXT: namespace MyTarget { -// CHECK-NEXT: enum RegisterPressureSets { +// CHECK: enum RegisterPressureSets { // CHECK-NEXT: D_32 = 0, -// CHECK-NEXT: }; -// NAMESPACE-NEXT: } // end namespace TestNamespace +// CHECK-NEXT: }; +// CHECK: } // namespace MyTarget // CHECK-LABEL: getRegPressureSetName(unsigned Idx) const { // CHECK-NEXT: static const char *PressureNameTable[] = { diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td index 2fb04638fd1e1..5a3b4a47953ca 100644 --- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td +++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td @@ -23,17 +23,17 @@ def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32, // CHECK: OPC_CheckOpcode, TARGET_VAL(ISD::ADD), // CHECK-NEXT: OPC_RecordChild0, // #0 = $src -// CHECK-NEXT: OPC_Scope /*2 children */, 12, // ->18 +// CHECK-NEXT: OPC_Scope /*2 children */, 11, // ->17 // CHECK-NEXT: OPC_CheckChild1Integer, 0, // CHECK-NEXT: OPC_EmitIntegerI32, 0|128,1/*128*/, // #1 = TestNamespace::GPRAbove127RegClassID // CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), -// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0, +// CHECK-NEXT: MVT::i32, 2/*#Ops*/, /*OperandList*/0, // Ops = #1 #0 def : Pat<(i32 (add i32:$src, (i32 0))), (COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>; // CHECK: OPC_CheckChild1Integer, 1, // CHECK-NEXT: OPC_EmitIntegerI32, TestNamespace::GPR127RegClassID, // CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), -// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0, +// CHECK-NEXT: MVT::i32, 2/*#Ops*/, /*OperandList*/0, // Ops = #1 #0 def : Pat<(i32 (add i32:$src, (i32 1))), (COPY_TO_REGCLASS GPR127, GPR0:$src)>; diff --git a/llvm/test/TableGen/generic-tables-instruction.td b/llvm/test/TableGen/generic-tables-instruction.td index 7b99784f2d73a..3d98333b32922 100644 --- a/llvm/test/TableGen/generic-tables-instruction.td +++ b/llvm/test/TableGen/generic-tables-instruction.td @@ -18,7 +18,7 @@ def Arch : Target { let InstructionSet = ArchInstrInfo; } // A contiguous primary (Instruction) key should get a direct lookup instead of // binary search. // CHECK: const MyInstr *getCustomEncodingHelper(unsigned Opcode) { -// CHECK: if ((unsigned)Opcode != std::clamp((unsigned)Opcode, (unsigned)B, (unsigned)D)) +// CHECK: if ((unsigned)Opcode != std::clamp(Opcode, B, D)) // CHECK: return nullptr; // CHECK: auto Table = ArrayRef(InstrTable); // CHECK: size_t Idx = Opcode - B; @@ -54,7 +54,7 @@ def InstrTable : GenericTable { // // Verify contiguous check for SearchIndex. // const MyInfoEntry *getTable2ByValue(uint8_t Value) { -// CHECK: if ((uint8_t)Value != std::clamp((uint8_t)Value, (uint8_t)0xB, (uint8_t)0xD)) +// CHECK: if ((uint8_t)Value != std::clamp(Value, 0xB, 0xD)) // CHECK: return nullptr; // CHECK: auto Table = ArrayRef(Index); // CHECK: size_t Idx = Value - 0xB; diff --git a/llvm/test/TableGen/generic-tables.td b/llvm/test/TableGen/generic-tables.td index 8638740a8e565..6b72a3e807e7d 100644 --- a/llvm/test/TableGen/generic-tables.td +++ b/llvm/test/TableGen/generic-tables.td @@ -113,7 +113,7 @@ def lookupBTableByNameAndFlag : SearchIndex { // CHECK: const CEntry *lookupCEntry(StringRef Name, unsigned Kind); // CHECK-LABEL: GET_CTable_IMPL // CHECK: const CEntry *lookupCEntryByEncoding(uint16_t Encoding) { -// CHECK: if ((uint16_t)Encoding != std::clamp((uint16_t)Encoding, (uint16_t)0xA, (uint16_t)0xF)) +// CHECK: if ((uint16_t)Encoding != std::clamp(Encoding, 0xA, 0xF)) // CHECK: return nullptr; // CHECK: const CEntry *lookupCEntry(StringRef Name, unsigned Kind) { diff --git a/llvm/test/TableGen/intrinsic-arginfo.td b/llvm/test/TableGen/intrinsic-arginfo.td index eab1f5e032bc3..795fec0145e99 100644 --- a/llvm/test/TableGen/intrinsic-arginfo.td +++ b/llvm/test/TableGen/intrinsic-arginfo.td @@ -30,15 +30,16 @@ def int_my_fadd_f32 : DefaultAttrsIntrinsic< ArgInfo, [ArgName<"rounding_mode">, ImmArgPrinter<"printRoundingMode">]>, ArgInfo, [ArgName<"saturation_mode">]>]>; -// CHECK: #ifdef GET_INTRINSIC_PRETTY_PRINT_TABLE -// CHECK-NEXT: static constexpr uint8_t PPTable[] = { +// CHECK: #ifdef GET_INTRINSIC_PRETTY_PRINT_TABLE +// CHECK-NEXT: #undef GET_INTRINSIC_PRETTY_PRINT_TABLE +// CHECK: static constexpr uint8_t PPTable[] = { +// CHECK: #endif // GET_INTRINSIC_PRETTY_PRINT_TABLE -// CHECK: #endif // GET_INTRINSIC_PRETTY_PRINT_TABLE +// CHECK: #ifdef GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS +// CHECK-NEXT: #undef GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS +// CHECK: void Intrinsic::printImmArg(ID IID, unsigned ArgIdx, raw_ostream &OS, const Constant *ImmArgVal) { -// CHECK: #ifdef GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS -// CHECK: void Intrinsic::printImmArg(ID IID, unsigned ArgIdx, raw_ostream &OS, const Constant *ImmArgVal) { - -// CHECK: case dummy_foo_bar: +// CHECK: case dummy_foo_bar: // CHECK-NEXT: switch (ArgIdx) { // CHECK-NEXT: case 1: @@ -53,7 +54,7 @@ def int_my_fadd_f32 : DefaultAttrsIntrinsic< // CHECK-NEXT: } // CHECK-NEXT: break; -// CHECK: case my_fadd_f32: +// CHECK: case my_fadd_f32: // CHECK-NEXT: switch (ArgIdx) { // CHECK-NEXT: case 2: @@ -68,4 +69,4 @@ def int_my_fadd_f32 : DefaultAttrsIntrinsic< // CHECK-NEXT: } // CHECK-NEXT: break; -// CHECK: #endif // GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS +// CHECK: #endif // GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS diff --git a/llvm/test/TableGen/pset-enum.td b/llvm/test/TableGen/pset-enum.td index c4c58c2ce6409..8010c3438f118 100644 --- a/llvm/test/TableGen/pset-enum.td +++ b/llvm/test/TableGen/pset-enum.td @@ -5,7 +5,7 @@ include "reg-with-subregs-common.td" // CHECK-LABEL: // Register pressure sets enum. // NAMESPACE-NEXT: namespace TestNamespace { -// CHECK-NEXT: enum RegisterPressureSets { +// CHECK: enum RegisterPressureSets { // CHECK-NEXT: GPR32 = 0, // CHECK-NEXT: }; -// NAMESPACE-NEXT: } // end namespace TestNamespace +// NAMESPACE: } // namespace TestNamespace diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td index 79178731f12a7..7e97a7926a2d4 100644 --- a/llvm/test/TableGen/riscv-target-def.td +++ b/llvm/test/TableGen/riscv-target-def.td @@ -1,4 +1,5 @@ // RUN: llvm-tblgen -gen-riscv-target-def -I %p/../../include %s | FileCheck %s +// RUN: not llvm-tblgen -gen-riscv-target-def -DDUPLICATE -I %p/../../include %s 2>&1 | FileCheck %s --check-prefix=DUPLICATE include "llvm/Target/Target.td" @@ -26,6 +27,21 @@ class RISCVExperimentalExtension implied_features = []> + : SubtargetFeature { + let Implies = implied_features; + + string PositiveDirectiveName = pos_directive; + string NegativeDirectiveName = neg_directive; +} +class RISCVSimpleTuneFeature implied_features = []> + : RISCVTuneFeature; + def FeatureStdExtI : RISCVExtension<"i", 2, 1, "'I' (Base Integer Instruction Set)">, @@ -84,13 +100,17 @@ class RISCVProcessorModel ConfigurableTuneFeatures = []; } class RISCVTuneProcessorModel tunef = [], list f = []> - : ProcessorModel; + : ProcessorModel { + list ConfigurableTuneFeatures = []; +} def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32", NoSchedModel, @@ -188,3 +208,14 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", // CHECK-NEXT: {"i", 0, 8ULL}, // CHECK-NEXT: }; // CHECK-NEXT: #endif + +#ifdef DUPLICATE +def TuneFeatureBar : RISCVTuneFeature<"bar", "abc", "def", "HasBar", "true", "TBA">; + +def TuneFeatureFoo : RISCVTuneFeature<"foo", "xyz", "abc", "HasFoo", "true", "TBA">; + +// DUPLICATE: error: RISC-V tune feature negative directive 'abc' was already defined +// DUPLICATE-NEXT: def TuneFeatureFoo +// DUPLICATE: note: Previously defined here +// DUPLICATE-NEXT: def TuneFeatureBar +#endif diff --git a/llvm/test/Transforms/ArgumentPromotion/dbg.ll b/llvm/test/Transforms/ArgumentPromotion/dbg.ll index 6a14facfb36a2..4f680f030b8be 100644 --- a/llvm/test/Transforms/ArgumentPromotion/dbg.ll +++ b/llvm/test/Transforms/ArgumentPromotion/dbg.ll @@ -53,7 +53,22 @@ define void @caller(ptr %Y, ptr %P) { !0 = !{i32 2, !"Debug Info Version", i32 3} !1 = !DILocation(line: 8, scope: !2) -!2 = distinct !DISubprogram(name: "test", file: !5, line: 3, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !3, scopeLine: 3, scope: null) +!2 = distinct !DISubprogram(name: "test", file: !5, line: 3, type: !7, isLocal: true, isDefinition: true, flags: DIFlagPrototyped, isOptimized: false, unit: !3, scopeLine: 3, scope: null) !3 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: LineTablesOnly, file: !5) !5 = !DIFile(filename: "test.c", directory: "") !6 = !DILocation(line: 9, scope: !2) +!7 = !DISubroutineType(types: !8) +!8 = !{null, !9} +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10) +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) + +; CHECK: !0 = !{i32 2, !"Debug Info Version", i32 3} +; CHECK-NEXT: !1 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !2, producer: "clang version 3.5.0 ", isOptimized: false, runtimeVersion: 0, emissionKind: LineTablesOnly) +; CHECK-NEXT: !2 = !DIFile(filename: "test.c", directory: "") +; CHECK-NEXT: !3 = distinct !DISubprogram(name: "test", scope: null, file: !2, line: 3, type: !4, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition, unit: !1) +; CHECK-NEXT: !4 = !DISubroutineType(cc: DW_CC_nocall, types: !5) +; CHECK-NEXT: !5 = !{null, !6} +; CHECK-NEXT: !6 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7) +; CHECK-NEXT: !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +; CHECK-NEXT: !8 = !DILocation(line: 8, scope: !3) +; CHECK-NEXT: !9 = !DILocation(line: 9, scope: !3) diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll index 8a02562bea642..223ba631b354d 100644 --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll @@ -5219,12 +5219,12 @@ define void @test_atomicrmw_fadd_v2bf16_global_agent_noret__unsafe(ptr addrspace ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #1 = { strictfp "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } +attributes #1 = { strictfp denormal_fpenv(float: preservesign) } attributes #2 = { strictfp } -attributes #3 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #4 = { "denormal-fp-math-f32"="dynamic,dynamic" } -attributes #5 = { "denormal-fp-math"="dynamic,dynamic" } +attributes #3 = { denormal_fpenv(float: preservesign) } +attributes #4 = { denormal_fpenv(float: dynamic) } +attributes #5 = { denormal_fpenv(dynamic) } !0 = !{} !1 = !{i32 5, i32 6} diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-simplify-cfg-CAS-block.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-simplify-cfg-CAS-block.ll index 13c65ec5abb8c..ae414ae83b9a4 100644 --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-simplify-cfg-CAS-block.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-simplify-cfg-CAS-block.ll @@ -63,4 +63,4 @@ endif: ret void } -attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(float: preservesign) } diff --git a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll new file mode 100644 index 0000000000000..fc27e4144545f --- /dev/null +++ b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-fract.ll @@ -0,0 +1,66 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -passes=attributor -attributor-manifest-internal < %s | FileCheck %s + +declare double @llvm.amdgcn.fract.f64(double) #0 + +define double @ret_fract(double %x) { +; CHECK-LABEL: define nofpclass(inf) double @ret_fract( +; CHECK-SAME: double [[X:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: [[FRACT:%.*]] = call nofpclass(inf) double @llvm.amdgcn.fract.f64(double [[X]]) #[[ATTR2:[0-9]+]] +; CHECK-NEXT: ret double [[FRACT]] +; + %fract = call double @llvm.amdgcn.fract.f64(double %x) + ret double %fract +} + +define double @ret_fract_no_qnan(double nofpclass(qnan) %x) { +; CHECK-LABEL: define nofpclass(inf) double @ret_fract_no_qnan( +; CHECK-SAME: double nofpclass(qnan) [[X:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[FRACT:%.*]] = call nofpclass(inf) double @llvm.amdgcn.fract.f64(double nofpclass(qnan) [[X]]) #[[ATTR2]] +; CHECK-NEXT: ret double [[FRACT]] +; + %fract = call double @llvm.amdgcn.fract.f64(double %x) + ret double %fract +} + +define double @ret_fract_no_snan(double nofpclass(snan) %x) { +; CHECK-LABEL: define nofpclass(snan inf) double @ret_fract_no_snan( +; CHECK-SAME: double nofpclass(snan) [[X:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[FRACT:%.*]] = call nofpclass(snan inf) double @llvm.amdgcn.fract.f64(double nofpclass(snan) [[X]]) #[[ATTR2]] +; CHECK-NEXT: ret double [[FRACT]] +; + %fract = call double @llvm.amdgcn.fract.f64(double %x) + ret double %fract +} + +define double @ret_fract_no_inf(double nofpclass(inf) %x) { +; CHECK-LABEL: define nofpclass(inf) double @ret_fract_no_inf( +; CHECK-SAME: double nofpclass(inf) [[X:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[FRACT:%.*]] = call nofpclass(inf) double @llvm.amdgcn.fract.f64(double nofpclass(inf) [[X]]) #[[ATTR2]] +; CHECK-NEXT: ret double [[FRACT]] +; + %fract = call double @llvm.amdgcn.fract.f64(double %x) + ret double %fract +} + +define double @ret_fract_no_nan(double nofpclass(nan) %x) { +; CHECK-LABEL: define nofpclass(snan inf) double @ret_fract_no_nan( +; CHECK-SAME: double nofpclass(nan) [[X:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[FRACT:%.*]] = call nofpclass(snan inf) double @llvm.amdgcn.fract.f64(double nofpclass(nan) [[X]]) #[[ATTR2]] +; CHECK-NEXT: ret double [[FRACT]] +; + %fract = call double @llvm.amdgcn.fract.f64(double %x) + ret double %fract +} + +define double @ret_fract_no_nan_no_inf(double nofpclass(inf nan) %x) { +; CHECK-LABEL: define nofpclass(nan inf) double @ret_fract_no_nan_no_inf( +; CHECK-SAME: double nofpclass(nan inf) [[X:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[FRACT:%.*]] = call nofpclass(nan inf) double @llvm.amdgcn.fract.f64(double nofpclass(nan inf) [[X]]) #[[ATTR2]] +; CHECK-NEXT: ret double [[FRACT]] +; + %fract = call double @llvm.amdgcn.fract.f64(double %x) + ret double %fract +} + +attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } diff --git a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll index 53bd642c55b97..c7186d1cb12af 100644 --- a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll +++ b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-log.ll @@ -269,8 +269,8 @@ declare half @llvm.amdgcn.log.f16(half) #0 declare float @llvm.amdgcn.log.f32(float) #0 attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #1 = { "denormal-fp-math"="ieee,ieee" } -attributes #2 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #3 = { "denormal-fp-math"="ieee,dynamic" } -attributes #4 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #5 = { "denormal-fp-math"="dynamic,ieee" } +attributes #1 = { denormal_fpenv(ieee) } +attributes #2 = { denormal_fpenv(ieee|preservesign) } +attributes #3 = { denormal_fpenv(ieee|dynamic) } +attributes #4 = { denormal_fpenv(preservesign|ieee) } +attributes #5 = { denormal_fpenv(dynamic|ieee) } diff --git a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rcp.ll b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rcp.ll index 0dc179b1a9d6a..1c1d014d54906 100644 --- a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rcp.ll +++ b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rcp.ll @@ -426,5 +426,5 @@ define float @ret_rcp_f32_known_negative_not_nan(float nofpclass(nan pinf pzero } attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #1 = { "denormal-fp-math-f32"="ieee,dynamic" } -attributes #2 = { "denormal-fp-math"="ieee,dynamic" } +attributes #1 = { denormal_fpenv(float: ieee|dynamic) } +attributes #2 = { denormal_fpenv(ieee|dynamic) } diff --git a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rsq.ll b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rsq.ll index 2e5bcf2bfff2e..9f1e7fb49c73d 100644 --- a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rsq.ll +++ b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-rsq.ll @@ -286,5 +286,5 @@ define double @ret_rsq_f64_known_not_inf(double nofpclass(inf) %arg) { ret double %call } -attributes #0 = { "denormal-fp-math-f32"="ieee,dynamic" } -attributes #1 = { "denormal-fp-math"="ieee,dynamic" } +attributes #0 = { denormal_fpenv(float: ieee|dynamic) } +attributes #1 = { denormal_fpenv(ieee|dynamic) } diff --git a/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-trig-preop.ll b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-trig-preop.ll new file mode 100644 index 0000000000000..170da3010cceb --- /dev/null +++ b/llvm/test/Transforms/Attributor/AMDGPU/nofpclass-amdgcn-trig-preop.ll @@ -0,0 +1,12 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -passes=attributor -attributor-manifest-internal < %s | FileCheck %s + +define double @ret_trig_preop_f64(double %x, i32 %n) { +; CHECK-LABEL: define nofpclass(nan inf) double @ret_trig_preop_f64( +; CHECK-SAME: double [[X:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[RET:%.*]] = call nofpclass(nan inf) double @llvm.amdgcn.trig.preop.f64(double [[X]], i32 [[N]]) #[[ATTR2:[0-9]+]] +; CHECK-NEXT: ret double [[RET]] +; + %ret = call double @llvm.amdgcn.trig.preop.f64(double %x, i32 %n) + ret double %ret +} diff --git a/llvm/test/Transforms/Attributor/denormal-fp-math.ll b/llvm/test/Transforms/Attributor/denormal-fp-math.ll index 558d2bb074ff2..824f05cd973e3 100644 --- a/llvm/test/Transforms/Attributor/denormal-fp-math.ll +++ b/llvm/test/Transforms/Attributor/denormal-fp-math.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals --version 2 ; RUN: opt -S -passes=attributor < %s | FileCheck %s +; RUN: opt -S -passes=attributor-light < %s | FileCheck %s ; Keep the attribute checks clean by disabling inference of anything else. declare void @call_of_mystery() @@ -38,6 +39,7 @@ define internal void @leaf_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic__dynamic_d ; Should infer to preserve-sign,preserve-sign define internal void @leaf_dynamic_dynamic_from_daz_daz() #0 { +; CHECK: Function Attrs: denormal_fpenv(preservesign) ; CHECK-LABEL: define internal void @leaf_dynamic_dynamic_from_daz_daz ; CHECK-SAME: () #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -50,6 +52,7 @@ define internal void @leaf_dynamic_dynamic_from_daz_daz() #0 { ; This goes to invalid because of the mismatch in the main mode. We ; could theoretically refine to denormal-fp-math-f32=preserve-sign,preserve-sign define internal void @leaf_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic__dynamic_dynamic_from_daz_daz() #1 { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) ; CHECK-LABEL: define internal void @leaf_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic__dynamic_dynamic_from_daz_daz ; CHECK-SAME: () #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -61,6 +64,7 @@ define internal void @leaf_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic__dynamic_d ; Leave this alone, must stay dynamic,dynamic define internal void @leaf_dynamic_dynamic_from_daz_daz_and_ieee_ieee() #0 { +; CHECK: Function Attrs: denormal_fpenv(dynamic) ; CHECK-LABEL: define internal void @leaf_dynamic_dynamic_from_daz_daz_and_ieee_ieee ; CHECK-SAME: () #[[ATTR2:[0-9]+]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -72,6 +76,7 @@ define internal void @leaf_dynamic_dynamic_from_daz_daz_and_ieee_ieee() #0 { ; Leave this alone, should only have denormal-fp-math-f32=ieee,ieee define internal void @leaf_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic__dynamic_dynamic_from_daz_daz_and_ieee_ieee() #1 { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) ; CHECK-LABEL: define internal void @leaf_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic__dynamic_dynamic_from_daz_daz_and_ieee_ieee ; CHECK-SAME: () #[[ATTR1]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -83,6 +88,7 @@ define internal void @leaf_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic__dynamic_d ; Leave as dynamic,dynamic define void @externally_visible_dynamic_dynamic_from_ieee_ieee() #0 { +; CHECK: Function Attrs: denormal_fpenv(dynamic) ; CHECK-LABEL: define void @externally_visible_dynamic_dynamic_from_ieee_ieee ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -94,6 +100,7 @@ define void @externally_visible_dynamic_dynamic_from_ieee_ieee() #0 { ; Should infer to positive-zero,positive-zero define internal void @leaf_dynamic_dynamic_from_dapz_dapz() #0 { +; CHECK: Function Attrs: denormal_fpenv(positivezero) ; CHECK-LABEL: define internal void @leaf_dynamic_dynamic_from_dapz_dapz ; CHECK-SAME: () #[[ATTR3:[0-9]+]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -153,6 +160,7 @@ define void @func_default_is_ieee_ieee() { ; preserve-sign,preserve-sign entry point define void @func_daz_daz() #3 { +; CHECK: Function Attrs: denormal_fpenv(preservesign) ; CHECK-LABEL: define void @func_daz_daz ; CHECK-SAME: () #[[ATTR0]] { ; CHECK-NEXT: call void @leaf_dynamic_dynamic_from_daz_daz() @@ -172,6 +180,7 @@ define void @func_daz_daz() #3 { ; positive-zero,positive-zero entry point define void @func_dapz_dapz() #4 { +; CHECK: Function Attrs: denormal_fpenv(positivezero) ; CHECK-LABEL: define void @func_dapz_dapz ; CHECK-SAME: () #[[ATTR3]] { ; CHECK-NEXT: call void @leaf_dynamic_dynamic_from_dapz_dapz() @@ -184,6 +193,7 @@ define void @func_dapz_dapz() #4 { ; Could be fully preserve-sign,preserve-sign, but this isn't a ; realistic case and we don't bother trying to handle it. define internal void @leaf_f64_dynamic_f64_dynamic__f32_daz_f32_daz_from__daz_daz() #5 { +; CHECK: Function Attrs: denormal_fpenv(dynamic, float: preservesign) ; CHECK-LABEL: define internal void @leaf_f64_dynamic_f64_dynamic__f32_daz_f32_daz_from__daz_daz ; CHECK-SAME: () #[[ATTR4:[0-9]+]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -215,6 +225,7 @@ define internal void @leaf_ieee_dynamic_from_ieee_ieee() #7 { ; Specialize the f64 mode to ieee,ieee but leave f32 as dynamic,dynamic define internal void @leaf_dynamic_dynamic_from_f64_ieee_f32_dynamic() #0 { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) ; CHECK-LABEL: define internal void @leaf_dynamic_dynamic_from_f64_ieee_f32_dynamic ; CHECK-SAME: () #[[ATTR1]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -225,6 +236,7 @@ define internal void @leaf_dynamic_dynamic_from_f64_ieee_f32_dynamic() #0 { } define void @func_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic() #1 { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) ; CHECK-LABEL: define void @func_f64_ieee_f64_ieee__f32_dynamic_f32_dynamic ; CHECK-SAME: () #[[ATTR1]] { ; CHECK-NEXT: call void @leaf_dynamic_dynamic_from_f64_ieee_f32_dynamic() @@ -277,6 +289,7 @@ define internal void @leaf_dynamic_from_dynamic() { ; Leave unchanged as preserve-sign,preserve-sign define internal void @leaf_daz_daz_from_dynamic() #3 { +; CHECK: Function Attrs: denormal_fpenv(preservesign) ; CHECK-LABEL: define internal void @leaf_daz_daz_from_dynamic ; CHECK-SAME: () #[[ATTR0]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -287,6 +300,7 @@ define internal void @leaf_daz_daz_from_dynamic() #3 { } define void @dynamic_dynamic() #0 { +; CHECK: Function Attrs: denormal_fpenv(dynamic) ; CHECK-LABEL: define void @dynamic_dynamic ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: call void @leaf_ieee_ieee_from_dynamic() @@ -301,6 +315,7 @@ define void @dynamic_dynamic() #0 { } define internal void @leaf_ieee_f64_daz_f32() #9 { +; CHECK: Function Attrs: denormal_fpenv(float: preservesign) ; CHECK-LABEL: define internal void @leaf_ieee_f64_daz_f32 ; CHECK-SAME: () #[[ATTR7:[0-9]+]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -311,6 +326,7 @@ define internal void @leaf_ieee_f64_daz_f32() #9 { } define internal void @leaf_ieee_f64_daz_f32_from_ieee_f64_dynamic_f32() #10 { +; CHECK: Function Attrs: denormal_fpenv(preservesign, float: ieee) ; CHECK-LABEL: define internal void @leaf_ieee_f64_daz_f32_from_ieee_f64_dynamic_f32 ; CHECK-SAME: () #[[ATTR8:[0-9]+]] { ; CHECK-NEXT: call void @call_of_mystery() @@ -321,6 +337,7 @@ define internal void @leaf_ieee_f64_daz_f32_from_ieee_f64_dynamic_f32() #10 { } define void @ieee_f64_dynamic_f32() #1 { +; CHECK: Function Attrs: denormal_fpenv(float: dynamic) ; CHECK-LABEL: define void @ieee_f64_dynamic_f32 ; CHECK-SAME: () #[[ATTR1]] { ; CHECK-NEXT: call void @leaf_ieee_f64_daz_f32() @@ -332,7 +349,7 @@ define void @ieee_f64_dynamic_f32() #1 { ret void } -; => "preserve-sign,positive-zero" + "denormal-fp-math-f32"="ieee,positive-zero" +; => "preserve-sign,positive-zero" + denormal_fpenv(float: ieee|positivezero) define internal void @leaf_daz_dynamic_dynamic_dapz_from_daz_dapz_ieee_dapz() #11 { ; CHECK-LABEL: define internal void @leaf_daz_dynamic_dynamic_dapz_from_daz_dapz_ieee_dapz ; CHECK-SAME: () #[[ATTR9:[0-9]+]] { @@ -353,28 +370,28 @@ define void @daz_dapz_ieee_dapz() #12 { ret void } -attributes #0 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" } -attributes #2 = { "denormal-fp-math"="ieee,ieee" } -attributes #3 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #4 = { "denormal-fp-math"="positive-zero,positive-zero" } -attributes #5 = { "denormal-fp-math"="dynamic,dynamic" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #6 = { "denormal-fp-math"="dynamic,ieee" } -attributes #7 = { "denormal-fp-math"="ieee,dynamic" } -attributes #8 = { "denormal-fp-math"="preserve-sign,dynamic" } -attributes #9 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #10 = { "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" } -attributes #11 = { "denormal-fp-math"="preserve-sign,dynamic" "denormal-fp-math-f32"="dynamic,positive-zero" } -attributes #12 = { "denormal-fp-math"="preserve-sign,positive-zero" "denormal-fp-math-f32"="ieee,positive-zero" } +attributes #0 = { denormal_fpenv(dynamic) } +attributes #1 = { denormal_fpenv(float: dynamic) } +attributes #2 = { denormal_fpenv(ieee|ieee) } +attributes #3 = { denormal_fpenv(preservesign) } +attributes #4 = { denormal_fpenv(positivezero|positivezero) } +attributes #5 = { denormal_fpenv(dynamic, float: preservesign) } +attributes #6 = { denormal_fpenv(dynamic|ieee) } +attributes #7 = { denormal_fpenv(ieee|dynamic) } +attributes #8 = { denormal_fpenv(preservesign|dynamic) } +attributes #9 = { denormal_fpenv(float: preservesign) } +attributes #10 = { denormal_fpenv(preservesign|preservesign, float: ieee) } +attributes #11 = { denormal_fpenv(preservesign|dynamic, float: dynamic|positivezero) } +attributes #12 = { denormal_fpenv(preservesign|positivezero, float: ieee|positivezero) } ;. -; CHECK: attributes #[[ATTR0]] = { "denormal-fp-math"="preserve-sign,preserve-sign" } -; CHECK: attributes #[[ATTR1]] = { "denormal-fp-math-f32"="dynamic,dynamic" } -; CHECK: attributes #[[ATTR2]] = { "denormal-fp-math"="dynamic,dynamic" } -; CHECK: attributes #[[ATTR3]] = { "denormal-fp-math"="positive-zero,positive-zero" } -; CHECK: attributes #[[ATTR4]] = { "denormal-fp-math"="dynamic,dynamic" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -; CHECK: attributes #[[ATTR5]] = { "denormal-fp-math"="preserve-sign,ieee" } -; CHECK: attributes #[[ATTR6]] = { "denormal-fp-math"="dynamic,ieee" } -; CHECK: attributes #[[ATTR7]] = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -; CHECK: attributes #[[ATTR8]] = { "denormal-fp-math"="preserve-sign,preserve-sign" "denormal-fp-math-f32"="ieee,ieee" } -; CHECK: attributes #[[ATTR9]] = { "denormal-fp-math"="preserve-sign,positive-zero" "denormal-fp-math-f32"="ieee,positive-zero" } +; CHECK: attributes #[[ATTR0]] = { denormal_fpenv(preservesign) } +; CHECK: attributes #[[ATTR1]] = { denormal_fpenv(float: dynamic) } +; CHECK: attributes #[[ATTR2]] = { denormal_fpenv(dynamic) } +; CHECK: attributes #[[ATTR3]] = { denormal_fpenv(positivezero) } +; CHECK: attributes #[[ATTR4]] = { denormal_fpenv(dynamic, float: preservesign) } +; CHECK: attributes #[[ATTR5]] = { denormal_fpenv(preservesign|ieee) } +; CHECK: attributes #[[ATTR6]] = { denormal_fpenv(dynamic|ieee) } +; CHECK: attributes #[[ATTR7]] = { denormal_fpenv(float: preservesign) } +; CHECK: attributes #[[ATTR8]] = { denormal_fpenv(preservesign, float: ieee) } +; CHECK: attributes #[[ATTR9]] = { denormal_fpenv(preservesign|positivezero, float: ieee|positivezero) } ;. diff --git a/llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll b/llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll index d1879cbb9add9..443771da59ff9 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-canonicalize.ll @@ -23,7 +23,7 @@ define float @ret_canonicalize_noinf(float nofpclass(inf) %arg0) { ret float %call } -define float @ret_canonicalize_dynamic_denormal(float nofpclass(inf) %arg0) "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_denormal(float nofpclass(inf) %arg0) denormal_fpenv(dynamic) { ; CHECK-LABEL: define nofpclass(snan inf) float @ret_canonicalize_dynamic_denormal ; CHECK-SAME: (float nofpclass(inf) [[ARG0:%.*]]) #[[ATTR2:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan inf) float @llvm.canonicalize.f32(float nofpclass(inf) [[ARG0]]) #[[ATTR12]] @@ -33,7 +33,7 @@ define float @ret_canonicalize_dynamic_denormal(float nofpclass(inf) %arg0) "den ret float %call } -define float @ret_canonicalize_daz_denormal(float nofpclass(inf) %arg0) "denormal-fp-math"="dynamic,preserve-sign" { +define float @ret_canonicalize_daz_denormal(float nofpclass(inf) %arg0) denormal_fpenv(dynamic|preservesign) { ; CHECK-LABEL: define nofpclass(snan inf sub) float @ret_canonicalize_daz_denormal ; CHECK-SAME: (float nofpclass(inf) [[ARG0:%.*]]) #[[ATTR3:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan inf sub) float @llvm.canonicalize.f32(float nofpclass(inf) [[ARG0]]) #[[ATTR12]] @@ -43,7 +43,7 @@ define float @ret_canonicalize_daz_denormal(float nofpclass(inf) %arg0) "denorma ret float %call } -define float @ret_canonicalize_dapz_denormal(float nofpclass(inf) %arg0) "denormal-fp-math"="dynamic,positive-zero" { +define float @ret_canonicalize_dapz_denormal(float nofpclass(inf) %arg0) denormal_fpenv(dynamic|positivezero) { ; CHECK-LABEL: define nofpclass(snan inf nzero sub) float @ret_canonicalize_dapz_denormal ; CHECK-SAME: (float nofpclass(inf) [[ARG0:%.*]]) #[[ATTR4:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan inf nzero sub) float @llvm.canonicalize.f32(float nofpclass(inf) [[ARG0]]) #[[ATTR12]] @@ -53,7 +53,7 @@ define float @ret_canonicalize_dapz_denormal(float nofpclass(inf) %arg0) "denorm ret float %call } -define float @ret_canonicalize_ftpz_dapz_denormal(float nofpclass(inf) %arg0) "denormal-fp-math"="positive-zero,preserve-sign" { +define float @ret_canonicalize_ftpz_dapz_denormal(float nofpclass(inf) %arg0) denormal_fpenv(positivezero|preservesign) { ; CHECK-LABEL: define nofpclass(snan inf sub) float @ret_canonicalize_ftpz_dapz_denormal ; CHECK-SAME: (float nofpclass(inf) [[ARG0:%.*]]) #[[ATTR5:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan inf sub) float @llvm.canonicalize.f32(float nofpclass(inf) [[ARG0]]) #[[ATTR12]] @@ -63,7 +63,7 @@ define float @ret_canonicalize_ftpz_dapz_denormal(float nofpclass(inf) %arg0) "d ret float %call } -define float @ret_canonicalize_ftpz_ieee_denormal(float nofpclass(inf) %arg0) "denormal-fp-math"="positive-zero,ieee" { +define float @ret_canonicalize_ftpz_ieee_denormal(float nofpclass(inf) %arg0) denormal_fpenv(positivezero|ieee) { ; CHECK-LABEL: define nofpclass(snan inf nzero sub) float @ret_canonicalize_ftpz_ieee_denormal ; CHECK-SAME: (float nofpclass(inf) [[ARG0:%.*]]) #[[ATTR6:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan inf nzero sub) float @llvm.canonicalize.f32(float nofpclass(inf) [[ARG0]]) #[[ATTR12]] @@ -73,7 +73,7 @@ define float @ret_canonicalize_ftpz_ieee_denormal(float nofpclass(inf) %arg0) "d ret float %call } -define float @ret_canonicalize_ftpz_dynamic_denormal(float nofpclass(inf) %arg0) "denormal-fp-math"="positive-zero,dynamic" { +define float @ret_canonicalize_ftpz_dynamic_denormal(float nofpclass(inf) %arg0) denormal_fpenv(positivezero|dynamic) { ; CHECK-LABEL: define nofpclass(snan inf sub) float @ret_canonicalize_ftpz_dynamic_denormal ; CHECK-SAME: (float nofpclass(inf) [[ARG0:%.*]]) #[[ATTR7:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan inf sub) float @llvm.canonicalize.f32(float nofpclass(inf) [[ARG0]]) #[[ATTR12]] @@ -83,7 +83,7 @@ define float @ret_canonicalize_ftpz_dynamic_denormal(float nofpclass(inf) %arg0) ret float %call } -define float @ret_canonicalize_ftz_denormal(float nofpclass(inf) %arg0) "denormal-fp-math"="preserve-sign,dynamic" { +define float @ret_canonicalize_ftz_denormal(float nofpclass(inf) %arg0) denormal_fpenv(preservesign|dynamic) { ; CHECK-LABEL: define nofpclass(snan inf sub) float @ret_canonicalize_ftz_denormal ; CHECK-SAME: (float nofpclass(inf) [[ARG0:%.*]]) #[[ATTR8:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan inf sub) float @llvm.canonicalize.f32(float nofpclass(inf) [[ARG0]]) #[[ATTR12]] @@ -93,7 +93,7 @@ define float @ret_canonicalize_ftz_denormal(float nofpclass(inf) %arg0) "denorma ret float %call } -define float @ret_canonicalize_ieee_denormal(float nofpclass(inf) %arg0) "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_denormal(float nofpclass(inf) %arg0) denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define nofpclass(snan inf) float @ret_canonicalize_ieee_denormal ; CHECK-SAME: (float nofpclass(inf) [[ARG0:%.*]]) #[[ATTR9:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan inf) float @llvm.canonicalize.f32(float nofpclass(inf) [[ARG0]]) #[[ATTR12]] @@ -103,7 +103,7 @@ define float @ret_canonicalize_ieee_denormal(float nofpclass(inf) %arg0) "denorm ret float %call } -define float @ret_canonicalize_ieee_constant_pos_denormal() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_pos_denormal() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero nsub norm) float @ret_canonicalize_ieee_constant_pos_denormal ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero nsub norm) float @llvm.canonicalize.f32(float noundef 0x36A0000000000000) #[[ATTR12]] @@ -113,7 +113,7 @@ define float @ret_canonicalize_ieee_constant_pos_denormal() "denormal-fp-math"=" ret float %call } -define float @ret_canonicalize_ieee_constant_neg_denormal() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_neg_denormal() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero psub norm) float @ret_canonicalize_ieee_constant_neg_denormal ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero psub norm) float @llvm.canonicalize.f32(float noundef 0xB6A0000000000000) #[[ATTR12]] @@ -123,7 +123,7 @@ define float @ret_canonicalize_ieee_constant_neg_denormal() "denormal-fp-math"=" ret float %call } -define float @ret_canonicalize_ieee_constant_pos_zero() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_pos_zero() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_ieee_constant_pos_zero ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0.000000e+00) #[[ATTR12]] @@ -133,7 +133,7 @@ define float @ret_canonicalize_ieee_constant_pos_zero() "denormal-fp-math"="ieee ret float %call } -define float @ret_canonicalize_ieee_constant_neg_zero() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_neg_zero() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(nan inf pzero sub norm) float @ret_canonicalize_ieee_constant_neg_zero ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf pzero sub norm) float @llvm.canonicalize.f32(float noundef -0.000000e+00) #[[ATTR12]] @@ -143,7 +143,7 @@ define float @ret_canonicalize_ieee_constant_neg_zero() "denormal-fp-math"="ieee ret float %call } -define float @ret_canonicalize_ieee_constant_pos_normal() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_pos_normal() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero sub nnorm) float @ret_canonicalize_ieee_constant_pos_normal ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero sub nnorm) float @llvm.canonicalize.f32(float noundef 8.000000e+00) #[[ATTR12]] @@ -153,7 +153,7 @@ define float @ret_canonicalize_ieee_constant_pos_normal() "denormal-fp-math"="ie ret float %call } -define float @ret_canonicalize_ieee_constant_neg_normal() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_neg_normal() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero sub pnorm) float @ret_canonicalize_ieee_constant_neg_normal ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero sub pnorm) float @llvm.canonicalize.f32(float noundef -8.000000e+00) #[[ATTR12]] @@ -163,7 +163,7 @@ define float @ret_canonicalize_ieee_constant_neg_normal() "denormal-fp-math"="ie ret float %call } -define float @ret_canonicalize_ieee_constant_pos_inf() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_pos_inf() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(nan ninf zero sub norm) float @ret_canonicalize_ieee_constant_pos_inf ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF0000000000000) #[[ATTR12]] @@ -173,7 +173,7 @@ define float @ret_canonicalize_ieee_constant_pos_inf() "denormal-fp-math"="ieee, ret float %call } -define float @ret_canonicalize_ieee_constant_neg_inf() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_neg_inf() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(nan pinf zero sub norm) float @ret_canonicalize_ieee_constant_neg_inf ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf zero sub norm) float @llvm.canonicalize.f32(float noundef 0xFFF0000000000000) #[[ATTR12]] @@ -183,7 +183,7 @@ define float @ret_canonicalize_ieee_constant_neg_inf() "denormal-fp-math"="ieee, ret float %call } -define float @ret_canonicalize_ieee_constant_qnan() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_qnan() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) float @ret_canonicalize_ieee_constant_qnan ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF8000000000000) #[[ATTR12]] @@ -193,7 +193,7 @@ define float @ret_canonicalize_ieee_constant_qnan() "denormal-fp-math"="ieee,iee ret float %call } -define float @ret_canonicalize_ieee_constant_snan() "denormal-fp-math"="ieee,ieee" { +define float @ret_canonicalize_ieee_constant_snan() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) float @ret_canonicalize_ieee_constant_snan ; CHECK-SAME: () #[[ATTR9]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF1000000000000) #[[ATTR12]] @@ -203,7 +203,7 @@ define float @ret_canonicalize_ieee_constant_snan() "denormal-fp-math"="ieee,iee ret float %call } -define float @ret_canonicalize_daz_constant_pos_denormal() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_pos_denormal() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_daz_constant_pos_denormal ; CHECK-SAME: () #[[ATTR10:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x36A0000000000000) #[[ATTR12]] @@ -213,7 +213,7 @@ define float @ret_canonicalize_daz_constant_pos_denormal() "denormal-fp-math"="p ret float %call } -define float @ret_canonicalize_daz_constant_neg_denormal() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_neg_denormal() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(nan inf pzero sub norm) float @ret_canonicalize_daz_constant_neg_denormal ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf pzero sub norm) float @llvm.canonicalize.f32(float noundef 0xB6A0000000000000) #[[ATTR12]] @@ -223,7 +223,7 @@ define float @ret_canonicalize_daz_constant_neg_denormal() "denormal-fp-math"="p ret float %call } -define float @ret_canonicalize_daz_constant_pos_zero() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_pos_zero() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_daz_constant_pos_zero ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0.000000e+00) #[[ATTR12]] @@ -233,7 +233,7 @@ define float @ret_canonicalize_daz_constant_pos_zero() "denormal-fp-math"="prese ret float %call } -define float @ret_canonicalize_daz_constant_neg_zero() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_neg_zero() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(nan inf pzero sub norm) float @ret_canonicalize_daz_constant_neg_zero ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf pzero sub norm) float @llvm.canonicalize.f32(float noundef -0.000000e+00) #[[ATTR12]] @@ -243,7 +243,7 @@ define float @ret_canonicalize_daz_constant_neg_zero() "denormal-fp-math"="prese ret float %call } -define float @ret_canonicalize_daz_constant_pos_normal() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_pos_normal() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero sub nnorm) float @ret_canonicalize_daz_constant_pos_normal ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero sub nnorm) float @llvm.canonicalize.f32(float noundef 8.000000e+00) #[[ATTR12]] @@ -253,7 +253,7 @@ define float @ret_canonicalize_daz_constant_pos_normal() "denormal-fp-math"="pre ret float %call } -define float @ret_canonicalize_daz_constant_neg_normal() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_neg_normal() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(nan inf zero sub pnorm) float @ret_canonicalize_daz_constant_neg_normal ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf zero sub pnorm) float @llvm.canonicalize.f32(float noundef -8.000000e+00) #[[ATTR12]] @@ -263,7 +263,7 @@ define float @ret_canonicalize_daz_constant_neg_normal() "denormal-fp-math"="pre ret float %call } -define float @ret_canonicalize_daz_constant_pos_inf() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_pos_inf() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(nan ninf zero sub norm) float @ret_canonicalize_daz_constant_pos_inf ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF0000000000000) #[[ATTR12]] @@ -273,7 +273,7 @@ define float @ret_canonicalize_daz_constant_pos_inf() "denormal-fp-math"="preser ret float %call } -define float @ret_canonicalize_daz_constant_neg_inf() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_neg_inf() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(nan pinf zero sub norm) float @ret_canonicalize_daz_constant_neg_inf ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf zero sub norm) float @llvm.canonicalize.f32(float noundef 0xFFF0000000000000) #[[ATTR12]] @@ -283,7 +283,7 @@ define float @ret_canonicalize_daz_constant_neg_inf() "denormal-fp-math"="preser ret float %call } -define float @ret_canonicalize_daz_constant_qnan() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_qnan() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) float @ret_canonicalize_daz_constant_qnan ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF8000000000000) #[[ATTR12]] @@ -293,7 +293,7 @@ define float @ret_canonicalize_daz_constant_qnan() "denormal-fp-math"="preserve- ret float %call } -define float @ret_canonicalize_daz_constant_snan() "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_constant_snan() denormal_fpenv(preservesign) { ; CHECK-LABEL: define noundef nofpclass(snan inf zero sub norm) float @ret_canonicalize_daz_constant_snan ; CHECK-SAME: () #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf zero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF1000000000000) #[[ATTR12]] @@ -303,7 +303,7 @@ define float @ret_canonicalize_daz_constant_snan() "denormal-fp-math"="preserve- ret float %call } -define float @ret_canonicalize_dapz_constant_pos_denormal() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_pos_denormal() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_dapz_constant_pos_denormal ; CHECK-SAME: () #[[ATTR11:[0-9]+]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x36A0000000000000) #[[ATTR12]] @@ -313,7 +313,7 @@ define float @ret_canonicalize_dapz_constant_pos_denormal() "denormal-fp-math"=" ret float %call } -define float @ret_canonicalize_dapz_constant_neg_denormal() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_neg_denormal() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_dapz_constant_neg_denormal ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0xB6A0000000000000) #[[ATTR12]] @@ -323,7 +323,7 @@ define float @ret_canonicalize_dapz_constant_neg_denormal() "denormal-fp-math"=" ret float %call } -define float @ret_canonicalize_dapz_constant_pos_zero() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_pos_zero() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_dapz_constant_pos_zero ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0.000000e+00) #[[ATTR12]] @@ -333,7 +333,7 @@ define float @ret_canonicalize_dapz_constant_pos_zero() "denormal-fp-math"="posi ret float %call } -define float @ret_canonicalize_dapz_constant_neg_zero() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_neg_zero() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) float @ret_canonicalize_dapz_constant_neg_zero ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef -0.000000e+00) #[[ATTR12]] @@ -343,7 +343,7 @@ define float @ret_canonicalize_dapz_constant_neg_zero() "denormal-fp-math"="posi ret float %call } -define float @ret_canonicalize_dapz_constant_pos_normal() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_pos_normal() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub nnorm) float @ret_canonicalize_dapz_constant_pos_normal ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub nnorm) float @llvm.canonicalize.f32(float noundef 8.000000e+00) #[[ATTR12]] @@ -353,7 +353,7 @@ define float @ret_canonicalize_dapz_constant_pos_normal() "denormal-fp-math"="po ret float %call } -define float @ret_canonicalize_dapz_constant_neg_normal() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_neg_normal() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub pnorm) float @ret_canonicalize_dapz_constant_neg_normal ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nzero sub pnorm) float @llvm.canonicalize.f32(float noundef -8.000000e+00) #[[ATTR12]] @@ -363,7 +363,7 @@ define float @ret_canonicalize_dapz_constant_neg_normal() "denormal-fp-math"="po ret float %call } -define float @ret_canonicalize_dapz_constant_pos_inf() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_pos_inf() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(nan ninf nzero sub norm) float @ret_canonicalize_dapz_constant_pos_inf ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF0000000000000) #[[ATTR12]] @@ -373,7 +373,7 @@ define float @ret_canonicalize_dapz_constant_pos_inf() "denormal-fp-math"="posit ret float %call } -define float @ret_canonicalize_dapz_constant_neg_inf() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_neg_inf() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(nan pinf nzero sub norm) float @ret_canonicalize_dapz_constant_neg_inf ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0xFFF0000000000000) #[[ATTR12]] @@ -383,7 +383,7 @@ define float @ret_canonicalize_dapz_constant_neg_inf() "denormal-fp-math"="posit ret float %call } -define float @ret_canonicalize_dapz_constant_qnan() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_qnan() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(snan inf nzero sub norm) float @ret_canonicalize_dapz_constant_qnan ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF8000000000000) #[[ATTR12]] @@ -393,7 +393,7 @@ define float @ret_canonicalize_dapz_constant_qnan() "denormal-fp-math"="positive ret float %call } -define float @ret_canonicalize_dapz_constant_snan() "denormal-fp-math"="positive-zero,positive-zero" { +define float @ret_canonicalize_dapz_constant_snan() denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: define noundef nofpclass(snan inf nzero sub norm) float @ret_canonicalize_dapz_constant_snan ; CHECK-SAME: () #[[ATTR11]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf nzero sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF1000000000000) #[[ATTR12]] @@ -403,7 +403,7 @@ define float @ret_canonicalize_dapz_constant_snan() "denormal-fp-math"="positive ret float %call } -define float @ret_canonicalize_dynamic_constant_pos_denormal() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_pos_denormal() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(nan inf nsub norm) float @ret_canonicalize_dynamic_constant_pos_denormal ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf nsub norm) float @llvm.canonicalize.f32(float noundef 0x36A0000000000000) #[[ATTR12]] @@ -413,7 +413,7 @@ define float @ret_canonicalize_dynamic_constant_pos_denormal() "denormal-fp-math ret float %call } -define float @ret_canonicalize_dynamic_constant_neg_denormal() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_neg_denormal() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(nan inf psub norm) float @ret_canonicalize_dynamic_constant_neg_denormal ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf psub norm) float @llvm.canonicalize.f32(float noundef 0xB6A0000000000000) #[[ATTR12]] @@ -423,7 +423,7 @@ define float @ret_canonicalize_dynamic_constant_neg_denormal() "denormal-fp-math ret float %call } -define float @ret_canonicalize_dynamic_constant_pos_zero() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_pos_zero() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(nan inf sub norm) float @ret_canonicalize_dynamic_constant_pos_zero ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf sub norm) float @llvm.canonicalize.f32(float noundef 0.000000e+00) #[[ATTR12]] @@ -433,7 +433,7 @@ define float @ret_canonicalize_dynamic_constant_pos_zero() "denormal-fp-math"="d ret float %call } -define float @ret_canonicalize_dynamic_constant_neg_zero() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_neg_zero() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(nan inf sub norm) float @ret_canonicalize_dynamic_constant_neg_zero ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf sub norm) float @llvm.canonicalize.f32(float noundef -0.000000e+00) #[[ATTR12]] @@ -443,7 +443,7 @@ define float @ret_canonicalize_dynamic_constant_neg_zero() "denormal-fp-math"="d ret float %call } -define float @ret_canonicalize_dynamic_constant_pos_normal() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_pos_normal() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(nan inf sub nnorm) float @ret_canonicalize_dynamic_constant_pos_normal ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf sub nnorm) float @llvm.canonicalize.f32(float noundef 8.000000e+00) #[[ATTR12]] @@ -453,7 +453,7 @@ define float @ret_canonicalize_dynamic_constant_pos_normal() "denormal-fp-math"= ret float %call } -define float @ret_canonicalize_dynamic_constant_neg_normal() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_neg_normal() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(nan inf sub pnorm) float @ret_canonicalize_dynamic_constant_neg_normal ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan inf sub pnorm) float @llvm.canonicalize.f32(float noundef -8.000000e+00) #[[ATTR12]] @@ -463,7 +463,7 @@ define float @ret_canonicalize_dynamic_constant_neg_normal() "denormal-fp-math"= ret float %call } -define float @ret_canonicalize_dynamic_constant_pos_inf() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_pos_inf() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(nan ninf sub norm) float @ret_canonicalize_dynamic_constant_pos_inf ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan ninf sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF0000000000000) #[[ATTR12]] @@ -473,7 +473,7 @@ define float @ret_canonicalize_dynamic_constant_pos_inf() "denormal-fp-math"="dy ret float %call } -define float @ret_canonicalize_dynamic_constant_neg_inf() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_neg_inf() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(nan pinf sub norm) float @ret_canonicalize_dynamic_constant_neg_inf ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(nan pinf sub norm) float @llvm.canonicalize.f32(float noundef 0xFFF0000000000000) #[[ATTR12]] @@ -483,7 +483,7 @@ define float @ret_canonicalize_dynamic_constant_neg_inf() "denormal-fp-math"="dy ret float %call } -define float @ret_canonicalize_dynamic_constant_qnan() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_qnan() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(snan inf sub norm) float @ret_canonicalize_dynamic_constant_qnan ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF8000000000000) #[[ATTR12]] @@ -493,7 +493,7 @@ define float @ret_canonicalize_dynamic_constant_qnan() "denormal-fp-math"="dynam ret float %call } -define float @ret_canonicalize_dynamic_constant_snan() "denormal-fp-math"="dynamic,dynamic" { +define float @ret_canonicalize_dynamic_constant_snan() denormal_fpenv(dynamic) { ; CHECK-LABEL: define noundef nofpclass(snan inf sub norm) float @ret_canonicalize_dynamic_constant_snan ; CHECK-SAME: () #[[ATTR2]] { ; CHECK-NEXT: [[CALL:%.*]] = call noundef nofpclass(snan inf sub norm) float @llvm.canonicalize.f32(float noundef 0x7FF1000000000000) #[[ATTR12]] @@ -503,7 +503,7 @@ define float @ret_canonicalize_dynamic_constant_snan() "denormal-fp-math"="dynam ret float %call } -define float @ret_canonicalize_daz_not_nzero_not_nsub(float nofpclass(nzero nsub) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_nzero_not_nsub(float nofpclass(nzero nsub) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan nzero sub) float @ret_canonicalize_daz_not_nzero_not_nsub ; CHECK-SAME: (float nofpclass(nzero nsub) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan nzero sub) float @llvm.canonicalize.f32(float nofpclass(nzero nsub) [[X]]) #[[ATTR12]] @@ -513,7 +513,7 @@ define float @ret_canonicalize_daz_not_nzero_not_nsub(float nofpclass(nzero nsub ret float %call } -define float @ret_canonicalize_daz_not_nsub(float nofpclass(nsub) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_nsub(float nofpclass(nsub) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan sub) float @ret_canonicalize_daz_not_nsub ; CHECK-SAME: (float nofpclass(nsub) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan sub) float @llvm.canonicalize.f32(float nofpclass(nsub) [[X]]) #[[ATTR12]] @@ -523,7 +523,7 @@ define float @ret_canonicalize_daz_not_nsub(float nofpclass(nsub) %x) "denormal- ret float %call } -define float @ret_canonicalize_daz_not_nzero(float nofpclass(nzero) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_nzero(float nofpclass(nzero) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan sub) float @ret_canonicalize_daz_not_nzero ; CHECK-SAME: (float nofpclass(nzero) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan sub) float @llvm.canonicalize.f32(float nofpclass(nzero) [[X]]) #[[ATTR12]] @@ -533,7 +533,7 @@ define float @ret_canonicalize_daz_not_nzero(float nofpclass(nzero) %x) "denorma ret float %call } -define float @ret_canonicalize_daz_not_pzero_not_psub(float nofpclass(pzero psub) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_pzero_not_psub(float nofpclass(pzero psub) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan pzero sub) float @ret_canonicalize_daz_not_pzero_not_psub ; CHECK-SAME: (float nofpclass(pzero psub) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan pzero sub) float @llvm.canonicalize.f32(float nofpclass(pzero psub) [[X]]) #[[ATTR12]] @@ -543,7 +543,7 @@ define float @ret_canonicalize_daz_not_pzero_not_psub(float nofpclass(pzero psub ret float %call } -define float @ret_canonicalize_daz_not_psub(float nofpclass(psub) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_psub(float nofpclass(psub) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan sub) float @ret_canonicalize_daz_not_psub ; CHECK-SAME: (float nofpclass(psub) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan sub) float @llvm.canonicalize.f32(float nofpclass(psub) [[X]]) #[[ATTR12]] @@ -553,7 +553,7 @@ define float @ret_canonicalize_daz_not_psub(float nofpclass(psub) %x) "denormal- ret float %call } -define float @ret_canonicalize_daz_not_pzero(float nofpclass(pzero) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_pzero(float nofpclass(pzero) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan sub) float @ret_canonicalize_daz_not_pzero ; CHECK-SAME: (float nofpclass(pzero) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan sub) float @llvm.canonicalize.f32(float nofpclass(pzero) [[X]]) #[[ATTR12]] @@ -563,7 +563,7 @@ define float @ret_canonicalize_daz_not_pzero(float nofpclass(pzero) %x) "denorma ret float %call } -define float @ret_canonicalize_daz_not_zero(float nofpclass(zero) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_zero(float nofpclass(zero) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan sub) float @ret_canonicalize_daz_not_zero ; CHECK-SAME: (float nofpclass(zero) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan sub) float @llvm.canonicalize.f32(float nofpclass(zero) [[X]]) #[[ATTR12]] @@ -573,7 +573,7 @@ define float @ret_canonicalize_daz_not_zero(float nofpclass(zero) %x) "denormal- ret float %call } -define float @ret_canonicalize_daz_not_sub(float nofpclass(sub) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_sub(float nofpclass(sub) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan sub) float @ret_canonicalize_daz_not_sub ; CHECK-SAME: (float nofpclass(sub) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan sub) float @llvm.canonicalize.f32(float nofpclass(sub) [[X]]) #[[ATTR12]] @@ -583,7 +583,7 @@ define float @ret_canonicalize_daz_not_sub(float nofpclass(sub) %x) "denormal-fp ret float %call } -define float @ret_canonicalize_daz_not_sub_not_nzero(float nofpclass(sub nzero) %x) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @ret_canonicalize_daz_not_sub_not_nzero(float nofpclass(sub nzero) %x) denormal_fpenv(preservesign) { ; CHECK-LABEL: define nofpclass(snan nzero sub) float @ret_canonicalize_daz_not_sub_not_nzero ; CHECK-SAME: (float nofpclass(nzero sub) [[X:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(snan nzero sub) float @llvm.canonicalize.f32(float nofpclass(nzero sub) [[X]]) #[[ATTR12]] diff --git a/llvm/test/Transforms/Attributor/nofpclass-fdiv.ll b/llvm/test/Transforms/Attributor/nofpclass-fdiv.ll index 7ae52a4d02ad9..fef871a1e85f7 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-fdiv.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-fdiv.ll @@ -1056,9 +1056,9 @@ define float @ret_known_inf_or_nan_fdiv_known_inf_or_nan(float nofpclass(norm su ret float %fdiv } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #2 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #3 = { "denormal-fp-math"="ieee,dynamic" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(ieee|preservesign) } +attributes #2 = { denormal_fpenv(ieee|positivezero) } +attributes #3 = { denormal_fpenv(ieee|dynamic) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-frem.ll b/llvm/test/Transforms/Attributor/nofpclass-frem.ll index 2c442c10289f5..42d9ac7da1cc9 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-frem.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-frem.ll @@ -1064,9 +1064,9 @@ define float @ret_known_inf_or_nan_frem_known_inf_or_nan(float nofpclass(norm su ret float %frem } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #2 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #3 = { "denormal-fp-math"="ieee,dynamic" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(ieee|preservesign) } +attributes #2 = { denormal_fpenv(ieee|positivezero) } +attributes #3 = { denormal_fpenv(ieee|dynamic) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-frexp.ll b/llvm/test/Transforms/Attributor/nofpclass-frexp.ll index 21fe6ce5676ce..085647bb2b6f0 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-frexp.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-frexp.ll @@ -460,12 +460,12 @@ define float @ret_frexp_f32_0_nopzero_daz_ieee(float nofpclass(pzero) %arg0) #5 } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #2 = { "denormal-fp-math"="positive-zero,positive-zero" } -attributes #3 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #4 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #5 = { "denormal-fp-math"="preserve-sign,ieee" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } +attributes #2 = { denormal_fpenv(positivezero|positivezero) } +attributes #3 = { denormal_fpenv(dynamic) } +attributes #4 = { denormal_fpenv(ieee|preservesign) } +attributes #5 = { denormal_fpenv(preservesign|ieee) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: diff --git a/llvm/test/Transforms/Attributor/nofpclass-ldexp.ll b/llvm/test/Transforms/Attributor/nofpclass-ldexp.ll index b9156319b0a91..1d8c7af63c4fe 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-ldexp.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-ldexp.ll @@ -702,10 +702,10 @@ define <2 x float> @ret_ldexp_v2f32_known_pos_exp_noinf(<2 x float> nofpclass(in } define <2 x float> @ret_ldexp_v2f32_known_neg_exp_noinf(<2 x float> nofpclass(inf) %arg0, <2 x i32> %arg1) #0 { -; CHECK-LABEL: define <2 x float> @ret_ldexp_v2f32_known_neg_exp_noinf +; CHECK-LABEL: define nofpclass(inf) <2 x float> @ret_ldexp_v2f32_known_neg_exp_noinf ; CHECK-SAME: (<2 x float> nofpclass(inf) [[ARG0:%.*]], <2 x i32> [[ARG1:%.*]]) #[[ATTR1]] { ; CHECK-NEXT: [[OR_ARG1:%.*]] = or <2 x i32> [[ARG1]], -; CHECK-NEXT: [[CALL:%.*]] = call <2 x float> @llvm.ldexp.v2f32.v2i32(<2 x float> nofpclass(inf) [[ARG0]], <2 x i32> [[OR_ARG1]]) #[[ATTR10]] +; CHECK-NEXT: [[CALL:%.*]] = call nofpclass(inf) <2 x float> @llvm.ldexp.v2f32.v2i32(<2 x float> nofpclass(inf) [[ARG0]], <2 x i32> [[OR_ARG1]]) #[[ATTR10]] ; CHECK-NEXT: ret <2 x float> [[CALL]] ; %or.arg1 = or <2 x i32> %arg1, @@ -1035,15 +1035,15 @@ define float @ret_ldexp_f32_neg127(float %arg0) #0 { ret float %call } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #2 = { "denormal-fp-math"="positive-zero,positive-zero" } -attributes #3 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #4 = { "denormal-fp-math"="ieee,dynamic" } -attributes #5 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #6 = { "denormal-fp-math"="dynamic,preserve-sign" } -attributes #7 = { "denormal-fp-math"="dynamic,positive-zero" } -attributes #8 = { "denormal-fp-math"="positive-zero,dynamic" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } +attributes #2 = { denormal_fpenv(positivezero|positivezero) } +attributes #3 = { denormal_fpenv(preservesign|ieee) } +attributes #4 = { denormal_fpenv(ieee|dynamic) } +attributes #5 = { denormal_fpenv(ieee|preservesign) } +attributes #6 = { denormal_fpenv(dynamic|preservesign) } +attributes #7 = { denormal_fpenv(dynamic|positivezero) } +attributes #8 = { denormal_fpenv(positivezero|dynamic) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-log.ll b/llvm/test/Transforms/Attributor/nofpclass-log.ll index cb9ebec4a6c58..4bd62d8e903ba 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-log.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-log.ll @@ -385,13 +385,13 @@ define float @ret_constrained_log10_noinf_noneg(float nofpclass(inf nsub nnorm) ret float %call } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #2 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #3 = { "denormal-fp-math"="ieee,dynamic" } -attributes #4 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #5 = { "denormal-fp-math"="positive-zero,ieee" } -attributes #6 = { "denormal-fp-math"="dynamic,ieee" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(ieee|preservesign) } +attributes #2 = { denormal_fpenv(ieee|positivezero) } +attributes #3 = { denormal_fpenv(ieee|dynamic) } +attributes #4 = { denormal_fpenv(preservesign|ieee) } +attributes #5 = { denormal_fpenv(positivezero|ieee) } +attributes #6 = { denormal_fpenv(dynamic|ieee) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-minimum-maximum.ll b/llvm/test/Transforms/Attributor/nofpclass-minimum-maximum.ll index d9b1375d3c633..7059620febe74 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-minimum-maximum.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-minimum-maximum.ll @@ -504,13 +504,13 @@ define float @ret_maximum_any__nopos(float %arg0, float nofpclass(pinf psub pnor ret float %call } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #2 = { "denormal-fp-math"="positive-zero,positive-zero" } -attributes #3 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #4 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #5 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #6 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #7 = { "denormal-fp-math"="positive-zero,ieee" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } +attributes #2 = { denormal_fpenv(positivezero|positivezero) } +attributes #3 = { denormal_fpenv(dynamic) } +attributes #4 = { denormal_fpenv(ieee|preservesign) } +attributes #5 = { denormal_fpenv(preservesign|ieee) } +attributes #6 = { denormal_fpenv(ieee|positivezero) } +attributes #7 = { denormal_fpenv(positivezero|ieee) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-minimumnum-maximumnum.ll b/llvm/test/Transforms/Attributor/nofpclass-minimumnum-maximumnum.ll index f21e9afe9e3ba..d5a289b51c107 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-minimumnum-maximumnum.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-minimumnum-maximumnum.ll @@ -784,13 +784,13 @@ define float @ret_maximumnum_noqnan__nosnan(float nofpclass(qnan) %arg0, float n ret float %call } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #2 = { "denormal-fp-math"="positive-zero,positive-zero" } -attributes #3 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #4 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #5 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #6 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #7 = { "denormal-fp-math"="positive-zero,ieee" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } +attributes #2 = { denormal_fpenv(positivezero|positivezero) } +attributes #3 = { denormal_fpenv(dynamic) } +attributes #4 = { denormal_fpenv(ieee|preservesign) } +attributes #5 = { denormal_fpenv(preservesign|ieee) } +attributes #6 = { denormal_fpenv(ieee|positivezero) } +attributes #7 = { denormal_fpenv(positivezero|ieee) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-minnum-maxnum.ll b/llvm/test/Transforms/Attributor/nofpclass-minnum-maxnum.ll index ddfddbc22a517..308f58b7dd2fc 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-minnum-maxnum.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-minnum-maxnum.ll @@ -504,13 +504,13 @@ define float @ret_maxnum_any__nopos(float %arg0, float nofpclass(pinf psub pnorm ret float %call } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #2 = { "denormal-fp-math"="positive-zero,positive-zero" } -attributes #3 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #4 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #5 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #6 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #7 = { "denormal-fp-math"="positive-zero,ieee" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } +attributes #2 = { denormal_fpenv(positivezero|positivezero) } +attributes #3 = { denormal_fpenv(dynamic) } +attributes #4 = { denormal_fpenv(ieee|preservesign) } +attributes #5 = { denormal_fpenv(preservesign|ieee) } +attributes #6 = { denormal_fpenv(ieee|positivezero) } +attributes #7 = { denormal_fpenv(positivezero|ieee) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll b/llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll index 1312f06cde0a4..6b09ba7223cae 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-nan-fmul.ll @@ -364,9 +364,9 @@ define float @ret_fmul_ieee_nonan__nozero_nonan_noinf(float nofpclass(nan) %arg0 ret float %fmul } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #2 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #3 = { "denormal-fp-math"="ieee,dynamic" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(ieee|preservesign) } +attributes #2 = { denormal_fpenv(ieee|positivezero) } +attributes #3 = { denormal_fpenv(ieee|dynamic) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-powi.ll b/llvm/test/Transforms/Attributor/nofpclass-powi.ll index 1d59907a34f19..a3f5c5d3e08dc 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-powi.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-powi.ll @@ -285,10 +285,10 @@ define <4 x float> @powi_v4f32_i32_regression(<4 x float> %arg) { ret <4 x float> %user } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #2 = { "denormal-fp-math"="positive-zero,positive-zero" } -attributes #3 = { "denormal-fp-math"="preserve-sign,ieee" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } +attributes #2 = { denormal_fpenv(positivezero|positivezero) } +attributes #3 = { denormal_fpenv(preservesign|ieee) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass-sqrt.ll b/llvm/test/Transforms/Attributor/nofpclass-sqrt.ll index 91831cd4621c9..aa62e807cddb9 100644 --- a/llvm/test/Transforms/Attributor/nofpclass-sqrt.ll +++ b/llvm/test/Transforms/Attributor/nofpclass-sqrt.ll @@ -270,13 +270,13 @@ define float @constrained_sqrt_nozero(float nofpclass(zero) %arg) strictfp { ret float %val } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #2 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #3 = { "denormal-fp-math"="ieee,dynamic" } -attributes #4 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #5 = { "denormal-fp-math"="positive-zero,ieee" } -attributes #6 = { "denormal-fp-math"="dynamic,ieee" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(ieee|preservesign) } +attributes #2 = { denormal_fpenv(ieee|positivezero) } +attributes #3 = { denormal_fpenv(ieee|dynamic) } +attributes #4 = { denormal_fpenv(preservesign|ieee) } +attributes #5 = { denormal_fpenv(positivezero|ieee) } +attributes #6 = { denormal_fpenv(dynamic|ieee) } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; TUNIT: {{.*}} diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll index c3ee163d19dc8..18adaf437f938 100644 --- a/llvm/test/Transforms/Attributor/nofpclass.ll +++ b/llvm/test/Transforms/Attributor/nofpclass.ll @@ -2025,7 +2025,7 @@ define float @fsub_n0_commute(float %arg0) { } define float @fadd_p0_ftz_daz(float %arg0) #3 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(positivezero) memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_p0_ftz_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR9:[0-9]+]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], 0.000000e+00 @@ -2036,7 +2036,7 @@ define float @fadd_p0_ftz_daz(float %arg0) #3 { } define float @fadd_n0_ftz_daz(float %arg0) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fadd_n0_ftz_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR10:[0-9]+]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], -0.000000e+00 @@ -2047,7 +2047,7 @@ define float @fadd_n0_ftz_daz(float %arg0) #0 { } define float @fsub_p0_ftz_daz(float %arg0) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fsub_p0_ftz_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[SUB:%.*]] = fsub float [[ARG0]], 0.000000e+00 @@ -2058,7 +2058,7 @@ define float @fsub_p0_ftz_daz(float %arg0) #0 { } define float @fsub_n0_ftz_daz(float %arg0) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fsub_n0_ftz_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[SUB:%.*]] = fsub float [[ARG0]], -0.000000e+00 @@ -2069,7 +2069,7 @@ define float @fsub_n0_ftz_daz(float %arg0) #0 { } define float @fsub_p0_commute_ftz_daz(float %arg0) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fsub_p0_commute_ftz_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[SUB:%.*]] = fsub float 0.000000e+00, [[ARG0]] @@ -2080,7 +2080,7 @@ define float @fsub_p0_commute_ftz_daz(float %arg0) #0 { } define float @fsub_n0_commute_ftz_daz(float %arg0) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fsub_n0_commute_ftz_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[SUB:%.*]] = fsub float -0.000000e+00, [[ARG0]] @@ -2091,7 +2091,6 @@ define float @fsub_n0_commute_ftz_daz(float %arg0) #0 { } define float @fadd_p0_ieee_daz(float %arg0) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_p0_ieee_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR11:[0-9]+]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], 0.000000e+00 @@ -2102,7 +2101,6 @@ define float @fadd_p0_ieee_daz(float %arg0) #2 { } define float @fadd_p0_dapz_ieee(float %arg0) #4 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_p0_dapz_ieee ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR12:[0-9]+]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], 0.000000e+00 @@ -2113,7 +2111,6 @@ define float @fadd_p0_dapz_ieee(float %arg0) #4 { } define float @fadd_n0_ieee_daz(float %arg0) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define float @fadd_n0_ieee_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], -0.000000e+00 @@ -2124,7 +2121,6 @@ define float @fadd_n0_ieee_daz(float %arg0) #2 { } define float @fsub_p0_ieee_daz(float %arg0) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define float @fsub_p0_ieee_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[SUB:%.*]] = fsub float [[ARG0]], 0.000000e+00 @@ -2135,7 +2131,6 @@ define float @fsub_p0_ieee_daz(float %arg0) #2 { } define float @fsub_n0_ieee_daz(float %arg0) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fsub_n0_ieee_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[SUB:%.*]] = fsub float [[ARG0]], -0.000000e+00 @@ -2146,7 +2141,6 @@ define float @fsub_n0_ieee_daz(float %arg0) #2 { } define float @fsub_p0_commute_ieee_daz(float %arg0) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fsub_p0_commute_ieee_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[SUB:%.*]] = fsub float 0.000000e+00, [[ARG0]] @@ -2157,7 +2151,6 @@ define float @fsub_p0_commute_ieee_daz(float %arg0) #2 { } define float @fsub_n0_commute_ieee_daz(float %arg0) #1 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define float @fsub_n0_commute_ieee_daz ; CHECK-SAME: (float [[ARG0:%.*]]) #[[ATTR13:[0-9]+]] { ; CHECK-NEXT: [[SUB:%.*]] = fsub float -0.000000e+00, [[ARG0]] @@ -2179,7 +2172,7 @@ define float @fadd_never_negzero_or_negsub(float nofpclass(nzero nsub) %a, float } define float @fadd_never_negzero_or_ftz_daz(float nofpclass(nzero nsub) %a, float nofpclass(nzero nsub) %b) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fadd_never_negzero_or_ftz_daz ; CHECK-SAME: (float nofpclass(nzero nsub) [[A:%.*]], float nofpclass(nzero nsub) [[B:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A]], [[B]] @@ -2190,7 +2183,6 @@ define float @fadd_never_negzero_or_ftz_daz(float nofpclass(nzero nsub) %a, floa } define float @fadd_never_negzero_or_negsub_daz(float nofpclass(nzero nsub) %a, float nofpclass(nzero nsub) %b) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_never_negzero_or_negsub_daz ; CHECK-SAME: (float nofpclass(nzero nsub) [[A:%.*]], float nofpclass(nzero nsub) [[B:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A]], [[B]] @@ -2201,7 +2193,6 @@ define float @fadd_never_negzero_or_negsub_daz(float nofpclass(nzero nsub) %a, f } define float @fadd_never_negzero_or_negsub_dapz(float nofpclass(nzero nsub) %a, float nofpclass(nzero nsub) %b) #5 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_never_negzero_or_negsub_dapz ; CHECK-SAME: (float nofpclass(nzero nsub) [[A:%.*]], float nofpclass(nzero nsub) [[B:%.*]]) #[[ATTR14:[0-9]+]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A]], [[B]] @@ -2223,7 +2214,6 @@ define float @fadd_never_negzero_or_possub(float nofpclass(nzero psub) %a, float } define float @fadd_never_negzero_or_possub_daz(float nofpclass(nzero psub) %a, float nofpclass(nzero psub) %b) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define float @fadd_never_negzero_or_possub_daz ; CHECK-SAME: (float nofpclass(nzero psub) [[A:%.*]], float nofpclass(nzero psub) [[B:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A]], [[B]] @@ -2234,7 +2224,6 @@ define float @fadd_never_negzero_or_possub_daz(float nofpclass(nzero psub) %a, f } define float @fadd_never_negzero_or_possub_dapz(float nofpclass(nzero psub) %a, float nofpclass(nzero psub) %b) #5 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_never_negzero_or_possub_dapz ; CHECK-SAME: (float nofpclass(nzero psub) [[A:%.*]], float nofpclass(nzero psub) [[B:%.*]]) #[[ATTR14]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A]], [[B]] @@ -2245,7 +2234,6 @@ define float @fadd_never_negzero_or_possub_dapz(float nofpclass(nzero psub) %a, } define float @fadd_never_negzero_or_sub_daz(float nofpclass(nzero sub) %a, float nofpclass(nzero sub) %b) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_never_negzero_or_sub_daz ; CHECK-SAME: (float nofpclass(nzero sub) [[A:%.*]], float nofpclass(nzero sub) [[B:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A]], [[B]] @@ -2256,7 +2244,6 @@ define float @fadd_never_negzero_or_sub_daz(float nofpclass(nzero sub) %a, float } define float @fadd_never_negzero_or_sub_dapz(float nofpclass(nzero sub) %a, float nofpclass(nzero sub) %b) #5 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_never_negzero_or_sub_dapz ; CHECK-SAME: (float nofpclass(nzero sub) [[A:%.*]], float nofpclass(nzero sub) [[B:%.*]]) #[[ATTR14]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[A]], [[B]] @@ -2300,7 +2287,7 @@ define float @fadd_known_positive(float nofpclass(ninf nsub nnorm) %arg0, float } define float @fadd_known_positive_daz(float nofpclass(ninf nsub nnorm) %arg0, float nofpclass(ninf nsub nnorm) %arg1) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define nofpclass(ninf nsub nnorm) float @fadd_known_positive_daz ; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[ARG0:%.*]], float nofpclass(ninf nsub nnorm) [[ARG1:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -2344,7 +2331,7 @@ define float @fadd_known_positive_nzero(float nofpclass(ninf nsub nnorm nzero) % } define float @fadd_known_positive_nzero_ftz_daz(float nofpclass(ninf nsub nnorm nzero) %arg0, float nofpclass(ninf nsub nnorm nzero) %arg1) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define nofpclass(ninf nsub nnorm) float @fadd_known_positive_nzero_ftz_daz ; CHECK-SAME: (float nofpclass(ninf nzero nsub nnorm) [[ARG0:%.*]], float nofpclass(ninf nzero nsub nnorm) [[ARG1:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -2355,7 +2342,6 @@ define float @fadd_known_positive_nzero_ftz_daz(float nofpclass(ninf nsub nnorm } define float @fadd_known_positive_nzero_ftz(float nofpclass(ninf nsub nnorm nzero) %arg0, float nofpclass(ninf nsub nnorm nzero) %arg1) #1 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(ninf nsub nnorm) float @fadd_known_positive_nzero_ftz ; CHECK-SAME: (float nofpclass(ninf nzero nsub nnorm) [[ARG0:%.*]], float nofpclass(ninf nzero nsub nnorm) [[ARG1:%.*]]) #[[ATTR13]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -2366,7 +2352,6 @@ define float @fadd_known_positive_nzero_ftz(float nofpclass(ninf nsub nnorm nzer } define float @fadd_known_positive_nzero_daz(float nofpclass(ninf nsub nnorm nzero) %arg0, float nofpclass(ninf nsub nnorm nzero) %arg1) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @fadd_known_positive_nzero_daz ; CHECK-SAME: (float nofpclass(ninf nzero nsub nnorm) [[ARG0:%.*]], float nofpclass(ninf nzero nsub nnorm) [[ARG1:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -2388,7 +2373,7 @@ define float @fadd_known_positive_normal(float nofpclass(ninf nnorm nzero) %arg0 } define float @fadd_known_positive_normal_daz(float nofpclass(ninf nnorm nzero) %arg0, float nofpclass(ninf nnorm nzero) %arg1) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fadd_known_positive_normal_daz ; CHECK-SAME: (float nofpclass(ninf nzero nnorm) [[ARG0:%.*]], float nofpclass(ninf nzero nnorm) [[ARG1:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -2399,7 +2384,7 @@ define float @fadd_known_positive_normal_daz(float nofpclass(ninf nnorm nzero) % } define float @fadd_known_positive_normal_except0_daz(float nofpclass(ninf nnorm) %arg0, float nofpclass(ninf nnorm) %arg1) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fadd_known_positive_normal_except0_daz ; CHECK-SAME: (float nofpclass(ninf nnorm) [[ARG0:%.*]], float nofpclass(ninf nnorm) [[ARG1:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -2410,7 +2395,7 @@ define float @fadd_known_positive_normal_except0_daz(float nofpclass(ninf nnorm) } define float @fadd_known_positive_normal_dapz(float nofpclass(ninf nnorm nzero) %arg0, float nofpclass(ninf nnorm nzero) %arg1) #3 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(positivezero) memory(none) ; CHECK-LABEL: define nofpclass(nzero) float @fadd_known_positive_normal_dapz ; CHECK-SAME: (float nofpclass(ninf nzero nnorm) [[ARG0:%.*]], float nofpclass(ninf nzero nnorm) [[ARG1:%.*]]) #[[ATTR9]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -3196,7 +3181,6 @@ define float @fadd_double_no_nonsub_nzero(float noundef nofpclass(nsub nzero) %a } define float @fadd_double_no_nopsub_pzero__ieee_daz(float noundef nofpclass(psub pzero) %arg) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(pzero) float @fadd_double_no_nopsub_pzero__ieee_daz ; CHECK-SAME: (float noundef nofpclass(pzero psub) [[ARG:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3207,7 +3191,7 @@ define float @fadd_double_no_nopsub_pzero__ieee_daz(float noundef nofpclass(psub } define float @fadd_double_no_nopsub_pzero__ftz_daz(float noundef nofpclass(psub pzero) %arg) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define noundef nofpclass(pzero) float @fadd_double_no_nopsub_pzero__ftz_daz ; CHECK-SAME: (float noundef nofpclass(pzero psub) [[ARG:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3218,7 +3202,6 @@ define float @fadd_double_no_nopsub_pzero__ftz_daz(float noundef nofpclass(psub } define float @fadd_double_no_nonsub_nzero__ieee_daz(float noundef nofpclass(nsub nzero) %arg) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(nzero) float @fadd_double_no_nonsub_nzero__ieee_daz ; CHECK-SAME: (float noundef nofpclass(nzero nsub) [[ARG:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3229,7 +3212,7 @@ define float @fadd_double_no_nonsub_nzero__ieee_daz(float noundef nofpclass(nsub } define float @fadd_double_no_nonsub_nzero__ftz_daz(float noundef nofpclass(nsub nzero) %arg) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define noundef float @fadd_double_no_nonsub_nzero__ftz_daz ; CHECK-SAME: (float noundef nofpclass(nzero nsub) [[ARG:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3240,7 +3223,6 @@ define float @fadd_double_no_nonsub_nzero__ftz_daz(float noundef nofpclass(nsub } define float @fadd_double_no_nopsub_pzero__ieee_dynamic(float noundef nofpclass(psub pzero) %arg) #9 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef float @fadd_double_no_nopsub_pzero__ieee_dynamic ; CHECK-SAME: (float noundef nofpclass(pzero psub) [[ARG:%.*]]) #[[ATTR17:[0-9]+]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3251,7 +3233,6 @@ define float @fadd_double_no_nopsub_pzero__ieee_dynamic(float noundef nofpclass( } define float @fadd_double_no_nonsub_nzero__ieee_dynamic(float noundef nofpclass(nsub nzero) %arg) #9 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(nzero) float @fadd_double_no_nonsub_nzero__ieee_dynamic ; CHECK-SAME: (float noundef nofpclass(nzero nsub) [[ARG:%.*]]) #[[ATTR17]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3273,7 +3254,6 @@ define float @fadd_double_known_positive_nonsub_ieee(float noundef nofpclass(nin } define float @fadd_double_known_positive_nonsub__ieee_daz(float noundef nofpclass(ninf nnorm sub zero) %arg) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(ninf zero nsub nnorm) float @fadd_double_known_positive_nonsub__ieee_daz ; CHECK-SAME: (float noundef nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3284,7 +3264,7 @@ define float @fadd_double_known_positive_nonsub__ieee_daz(float noundef nofpclas } define float @fadd_double_known_positive_nonsub__ftz_daz(float noundef nofpclass(ninf nnorm sub zero) %arg) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define noundef nofpclass(ninf zero nsub nnorm) float @fadd_double_known_positive_nonsub__ftz_daz ; CHECK-SAME: (float noundef nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3295,7 +3275,6 @@ define float @fadd_double_known_positive_nonsub__ftz_daz(float noundef nofpclass } define float @fadd_double_known_positive_nonsub__ieee_dynamic(float noundef nofpclass(ninf nnorm sub zero) %arg) #9 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(ninf zero nsub nnorm) float @fadd_double_known_positive_nonsub__ieee_dynamic ; CHECK-SAME: (float noundef nofpclass(ninf zero sub nnorm) [[ARG:%.*]]) #[[ATTR17]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3317,7 +3296,6 @@ define float @fadd_double_known_negative_nonsub_ieee(float noundef nofpclass(pin } define float @fadd_double_known_negative_nonsub__ieee_daz(float noundef nofpclass(pinf pnorm sub zero) %arg) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(pinf zero psub pnorm) float @fadd_double_known_negative_nonsub__ieee_daz ; CHECK-SAME: (float noundef nofpclass(pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3328,7 +3306,7 @@ define float @fadd_double_known_negative_nonsub__ieee_daz(float noundef nofpclas } define float @fadd_double_known_negative_nonsub__ftz_daz(float noundef nofpclass(pinf pnorm sub zero) %arg) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define noundef nofpclass(pinf zero psub pnorm) float @fadd_double_known_negative_nonsub__ftz_daz ; CHECK-SAME: (float noundef nofpclass(pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3339,7 +3317,6 @@ define float @fadd_double_known_negative_nonsub__ftz_daz(float noundef nofpclass } define float @fadd_double_known_negative_nonsub_dynamic(float noundef nofpclass(pinf pnorm sub zero) %arg) #9 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(pinf zero psub pnorm) float @fadd_double_known_negative_nonsub_dynamic ; CHECK-SAME: (float noundef nofpclass(pinf zero sub pnorm) [[ARG:%.*]]) #[[ATTR17]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3416,7 +3393,6 @@ define float @fadd_known_negative(float nofpclass(pinf psub pnorm) %arg0, float } define float @fadd_known_negative_daz(float nofpclass(pinf psub pnorm) %arg0, float nofpclass(pinf psub pnorm) %arg1) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(pinf psub pnorm) float @fadd_known_negative_daz ; CHECK-SAME: (float nofpclass(pinf psub pnorm) [[ARG0:%.*]], float nofpclass(pinf psub pnorm) [[ARG1:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -3460,7 +3436,7 @@ define float @fadd_known_negative_pzero(float nofpclass(pinf psub pnorm pzero) % } define float @fadd_known_negative_pzero_ftz_daz(float nofpclass(pinf psub pnorm pzero) %arg0, float nofpclass(pinf psub pnorm pzero) %arg1) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define nofpclass(pinf psub pnorm) float @fadd_known_negative_pzero_ftz_daz ; CHECK-SAME: (float nofpclass(pinf pzero psub pnorm) [[ARG0:%.*]], float nofpclass(pinf pzero psub pnorm) [[ARG1:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -3471,7 +3447,6 @@ define float @fadd_known_negative_pzero_ftz_daz(float nofpclass(pinf psub pnorm } define float @fadd_known_negative_pzero_ftz(float nofpclass(pinf psub pnorm pzero) %arg0, float nofpclass(pinf psub pnorm pzero) %arg1) #1 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(pinf psub pnorm) float @fadd_known_negative_pzero_ftz ; CHECK-SAME: (float nofpclass(pinf pzero psub pnorm) [[ARG0:%.*]], float nofpclass(pinf pzero psub pnorm) [[ARG1:%.*]]) #[[ATTR13]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -3482,7 +3457,6 @@ define float @fadd_known_negative_pzero_ftz(float nofpclass(pinf psub pnorm pzer } define float @fadd_known_negative_pzero_daz(float nofpclass(pinf psub pnorm pzero) %arg0, float nofpclass(pinf psub pnorm pzero) %arg1) #2 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define nofpclass(pinf psub pnorm) float @fadd_known_negative_pzero_daz ; CHECK-SAME: (float nofpclass(pinf pzero psub pnorm) [[ARG0:%.*]], float nofpclass(pinf pzero psub pnorm) [[ARG1:%.*]]) #[[ATTR11]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -3504,7 +3478,7 @@ define float @fadd_known_negative_normal(float nofpclass(pinf pnorm pzero) %arg0 } define float @fadd_known_negative_normal_daz(float nofpclass(pinf pnorm pzero) %arg0, float nofpclass(pinf pnorm pzero) %arg1) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fadd_known_negative_normal_daz ; CHECK-SAME: (float nofpclass(pinf pzero pnorm) [[ARG0:%.*]], float nofpclass(pinf pzero pnorm) [[ARG1:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -3515,7 +3489,7 @@ define float @fadd_known_negative_normal_daz(float nofpclass(pinf pnorm pzero) % } define float @fadd_known_negative_normal_except0_daz(float nofpclass(pinf pnorm) %arg0, float nofpclass(pinf pnorm) %arg1) #0 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(preservesign) memory(none) ; CHECK-LABEL: define float @fadd_known_negative_normal_except0_daz ; CHECK-SAME: (float nofpclass(pinf pnorm) [[ARG0:%.*]], float nofpclass(pinf pnorm) [[ARG1:%.*]]) #[[ATTR10]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -3526,7 +3500,7 @@ define float @fadd_known_negative_normal_except0_daz(float nofpclass(pinf pnorm) } define float @fadd_known_negative_normal_dapz(float nofpclass(pinf pnorm pzero) %arg0, float nofpclass(pinf pnorm pzero) %arg1) #3 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn denormal_fpenv(positivezero) memory(none) ; CHECK-LABEL: define float @fadd_known_negative_normal_dapz ; CHECK-SAME: (float nofpclass(pinf pzero pnorm) [[ARG0:%.*]], float nofpclass(pinf pzero pnorm) [[ARG1:%.*]]) #[[ATTR9]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG0]], [[ARG1]] @@ -3571,7 +3545,6 @@ define float @fadd_double_no_nzero_dapz_dapz(float noundef nofpclass(nzero) %arg } define float @fadd_double_no_nzero_dapz_ieee(float noundef nofpclass(nzero) %arg) #4 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(nzero) float @fadd_double_no_nzero_dapz_ieee ; CHECK-SAME: (float noundef nofpclass(nzero) [[ARG:%.*]]) #[[ATTR12]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3606,7 +3579,6 @@ define float @fadd_double_no_pzero_maybe_undef(float nofpclass(pzero) %arg) { ; The input is not logical 0 since it's IEEE, but the output could ; still be flushed. define float @fadd_double_no_zero__output_only_is_ftz(float noundef nofpclass(zero) %arg) #7 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef float @fadd_double_no_zero__output_only_is_ftz ; CHECK-SAME: (float noundef nofpclass(zero) [[ARG:%.*]]) #[[ATTR13]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3619,7 +3591,6 @@ define float @fadd_double_no_zero__output_only_is_ftz(float noundef nofpclass(ze ; The input is not logical 0 since it's IEEE, but the output could ; still be flushed. define float @fadd_double_no_zero__output_only_is_dynamic(float noundef nofpclass(zero) %arg) #8 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef float @fadd_double_no_zero__output_only_is_dynamic ; CHECK-SAME: (float noundef nofpclass(zero) [[ARG:%.*]]) #[[ATTR18:[0-9]+]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3733,7 +3704,6 @@ entry: } define float @fadd_double_no_zero__output_only_is_ftpz(float noundef nofpclass(zero) %arg) #4 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(nzero) float @fadd_double_no_zero__output_only_is_ftpz ; CHECK-SAME: (float noundef nofpclass(zero) [[ARG:%.*]]) #[[ATTR12]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3744,7 +3714,6 @@ define float @fadd_double_no_zero__output_only_is_ftpz(float noundef nofpclass(z } define float @fadd_double_no_zero_or_nsub__output_only_is_ftpz(float noundef nofpclass(zero nsub) %arg) #4 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(nzero) float @fadd_double_no_zero_or_nsub__output_only_is_ftpz ; CHECK-SAME: (float noundef nofpclass(zero nsub) [[ARG:%.*]]) #[[ATTR12]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3755,7 +3724,6 @@ define float @fadd_double_no_zero_or_nsub__output_only_is_ftpz(float noundef nof } define float @fadd_double_no_zero_or_psub__output_only_is_ftpz(float noundef nofpclass(zero psub) %arg) #4 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(nzero) float @fadd_double_no_zero_or_psub__output_only_is_ftpz ; CHECK-SAME: (float noundef nofpclass(zero psub) [[ARG:%.*]]) #[[ATTR12]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3766,7 +3734,6 @@ define float @fadd_double_no_zero_or_psub__output_only_is_ftpz(float noundef nof } define float @fadd_double_no_zero_or_sub__output_only_is_ftpz(float noundef nofpclass(zero sub) %arg) #4 { -; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define noundef nofpclass(zero) float @fadd_double_no_zero_or_sub__output_only_is_ftpz ; CHECK-SAME: (float noundef nofpclass(zero sub) [[ARG:%.*]]) #[[ATTR12]] { ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[ARG]], [[ARG]] @@ -3882,16 +3849,16 @@ define [4 x float] @infer_return_from_load_nofpclass_md_array(ptr %ptr) { declare i64 @_Z13get_global_idj(i32 noundef) -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #2 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #3 = { "denormal-fp-math"="positive-zero,positive-zero" } -attributes #4 = { "denormal-fp-math"="positive-zero,ieee" } -attributes #5 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #6 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #7 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #8 = { "denormal-fp-math"="dynamic,ieee" } -attributes #9 = { "denormal-fp-math"="ieee,dynamic" } +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(preservesign|ieee) } +attributes #2 = { denormal_fpenv(ieee|preservesign) } +attributes #3 = { denormal_fpenv(positivezero|positivezero) } +attributes #4 = { denormal_fpenv(positivezero|ieee) } +attributes #5 = { denormal_fpenv(ieee|positivezero) } +attributes #6 = { denormal_fpenv(dynamic) } +attributes #7 = { denormal_fpenv(preservesign|ieee) } +attributes #8 = { denormal_fpenv(dynamic|ieee) } +attributes #9 = { denormal_fpenv(ieee|dynamic) } !0 = !{} !1 = !{i32 3} diff --git a/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll b/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll index 470423874441b..7462fee057500 100644 --- a/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll +++ b/llvm/test/Transforms/Attributor/reduced/register_benchmark_test.ll @@ -1557,24 +1557,24 @@ declare dso_local void @_GLOBAL__sub_I_register_benchmark_test.cc() #0 section " ; Function Attrs: cold noreturn nounwind declare void @llvm.trap() #20 -attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #2 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #2 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #3 = { nounwind } -attributes #4 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #4 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #5 = { argmemonly nounwind willreturn } -attributes #6 = { alwaysinline uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #7 = { alwaysinline nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #8 = { nobuiltin "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #9 = { nobuiltin nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #10 = { inlinehint uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #11 = { inlinehint nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #12 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #13 = { norecurse uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #6 = { alwaysinline uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #7 = { alwaysinline nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #8 = { nobuiltin "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #9 = { nobuiltin nounwind "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee, float: ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #10 = { inlinehint uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #11 = { inlinehint nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #12 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #13 = { norecurse uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #14 = { nounwind readnone willreturn } -attributes #15 = { noreturn "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #15 = { noreturn "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #16 = { noinline noreturn nounwind } attributes #17 = { argmemonly nounwind willreturn writeonly } -attributes #18 = { noreturn uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } -attributes #19 = { inlinehint noreturn uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #18 = { noreturn uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } +attributes #19 = { inlinehint noreturn uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-jump-tables"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "use-soft-float"="false" } attributes #20 = { cold noreturn nounwind } diff --git a/llvm/test/Transforms/Coroutines/coro-cleanup-noop-elide.ll b/llvm/test/Transforms/Coroutines/coro-cleanup-noop-elide.ll new file mode 100644 index 0000000000000..6d9dd654b914a --- /dev/null +++ b/llvm/test/Transforms/Coroutines/coro-cleanup-noop-elide.ll @@ -0,0 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -S -passes='coro-cleanup' | FileCheck %s + +; Tests that resume or destroy a no-op coroutine can be erased; Finally, erase coro.noop if it has no users. +define void @erase() personality i32 0 { +; CHECK-LABEL: define void @erase() personality i32 0 { +; CHECK-NEXT: [[DONE:.*:]] +; CHECK-NEXT: ret void +; + %frame = call noundef ptr @llvm.coro.noop() + %resume = call ptr @llvm.coro.subfn.addr(ptr %frame, i8 0) + call fastcc void %resume(ptr %frame) + %destroy = call ptr @llvm.coro.subfn.addr(ptr %frame, i8 1) + invoke fastcc void %destroy(ptr %frame) + to label %done unwind label %unwind + +done: + ret void + +unwind: + %pad = landingpad { ptr, i32 } + catch ptr null + call void @terminate() + unreachable +} + +; Tests the load-and-call pattern despite mismatched calling conventions. Prevent instcombine from breaking code. +define void @load() personality i32 0 { +; CHECK-LABEL: define void @load() personality i32 0 { +; CHECK-NEXT: [[DONE:.*:]] +; CHECK-NEXT: ret void +; + %frame = call noundef ptr @llvm.coro.noop() + %resume = load ptr, ptr %frame, align 8 + call void %resume(ptr %frame) + %destroy.addr = getelementptr inbounds nuw i8, ptr %frame, i64 8 + %destroy = load ptr, ptr %destroy.addr, align 8 + invoke void %destroy(ptr %frame) + to label %done unwind label %unwind + +done: + ret void + +unwind: + %pad = landingpad { ptr, i32 } + catch ptr null + call void @terminate() + unreachable +} + +declare void @terminate() noreturn diff --git a/llvm/test/Transforms/Coroutines/coro-cleanup-noop-erase.ll b/llvm/test/Transforms/Coroutines/coro-cleanup-noop-erase.ll deleted file mode 100644 index 7fd9dc900ddb2..0000000000000 --- a/llvm/test/Transforms/Coroutines/coro-cleanup-noop-erase.ll +++ /dev/null @@ -1,24 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 -; Tests that resume or destroy a no-op coroutine can be erased; Finally, erase coro.noop if it has no users. -; RUN: opt < %s -S -passes='coro-cleanup' | FileCheck %s - -define void @fn() personality i32 0 { -; CHECK-LABEL: define void @fn() personality i32 0 { -; CHECK-NEXT: [[DONE:.*:]] -; CHECK-NEXT: ret void -; - %frame = call noundef ptr @llvm.coro.noop() - %resume = call ptr @llvm.coro.subfn.addr(ptr %frame, i8 0) - call fastcc void %resume(ptr %frame) - %destroy = call ptr @llvm.coro.subfn.addr(ptr %frame, i8 1) - invoke fastcc void %destroy(ptr %frame) - to label %done unwind label %unwind - -done: - ret void - -unwind: - %pad = landingpad { ptr, i32 } - catch ptr null - unreachable -} diff --git a/llvm/test/Transforms/DeadStoreElimination/simple.ll b/llvm/test/Transforms/DeadStoreElimination/simple.ll index 4467afb43f3b6..60a6602f030f7 100644 --- a/llvm/test/Transforms/DeadStoreElimination/simple.ll +++ b/llvm/test/Transforms/DeadStoreElimination/simple.ll @@ -955,5 +955,16 @@ define void @test_dead_on_return_variable_memset(ptr dead_on_return(8) %p, i64 % ret void } +define void @test_dead_on_return_variable_offset(ptr dead_on_return(4) %p, i64 %offset) { +; CHECK-LABEL: @test_dead_on_return_variable_offset( +; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 [[OFFSET:%.*]] +; CHECK-NEXT: store i32 0, ptr [[P1]], align 4 +; CHECK-NEXT: ret void +; + %p1 = getelementptr i8, ptr %p, i64 %offset + store i32 0, ptr %p1 + ret void +} + declare void @opaque(ptr) declare void @maythrow() memory(none) diff --git a/llvm/test/Transforms/EarlyCSE/cannot-be-negative-zero-assert.ll b/llvm/test/Transforms/EarlyCSE/cannot-be-negative-zero-assert.ll index 1a24c47337757..d86b09afa50aa 100644 --- a/llvm/test/Transforms/EarlyCSE/cannot-be-negative-zero-assert.ll +++ b/llvm/test/Transforms/EarlyCSE/cannot-be-negative-zero-assert.ll @@ -38,4 +38,4 @@ entry: ret double %add.i } -attributes #0 = { "denormal-fp-math"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-fp-convert-small.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-fp-convert-small.ll index 467bf76e7320b..9a3a4860b506b 100644 --- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-fp-convert-small.ll +++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-fp-convert-small.ll @@ -7,6 +7,48 @@ define i16 @fptosi_f16_i16(half %x) { ; CHECK-LABEL: define i16 @fptosi_f16_i16( ; CHECK-SAME: half [[X:%.*]]) { ; CHECK-NEXT: [[FP_TO_I_ENTRY:.*]]: +; CHECK-NEXT: [[TMP13:%.*]] = freeze half [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[TMP13]] to i16 +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 [[TMP0]], -1 +; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP1]], i16 1, i16 -1 +; CHECK-NEXT: [[TMP2:%.*]] = lshr i16 [[TMP0]], 10 +; CHECK-NEXT: [[BIASED_EXP:%.*]] = and i16 [[TMP2]], 31 +; CHECK-NEXT: [[TMP3:%.*]] = and i16 [[TMP0]], 1023 +; CHECK-NEXT: [[SIGNIFICAND:%.*]] = or i16 [[TMP3]], 1024 +; CHECK-NEXT: [[EXP_IS_NEGATIVE:%.*]] = icmp ult i16 [[BIASED_EXP]], 15 +; CHECK-NEXT: br i1 [[EXP_IS_NEGATIVE]], label %[[FP_TO_I_CLEANUP:.*]], label %[[FP_TO_I_IF_CHECK_SATURATE:.*]] +; CHECK: [[FP_TO_I_IF_CHECK_SATURATE]]: +; CHECK-NEXT: [[TMP4:%.*]] = add i16 [[BIASED_EXP]], -31 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i16 [[TMP4]], -16 +; CHECK-NEXT: br i1 [[TMP5]], label %[[FP_TO_I_IF_SATURATE:.*]], label %[[FP_TO_I_IF_CHECK_EXP_SIZE:.*]] +; CHECK: [[FP_TO_I_IF_SATURATE]]: +; CHECK-NEXT: [[SATURATED:%.*]] = select i1 [[TMP1]], i16 32767, i16 -32768 +; CHECK-NEXT: br label %[[FP_TO_I_CLEANUP]] +; CHECK: [[FP_TO_I_IF_CHECK_EXP_SIZE]]: +; CHECK-NEXT: [[EXP_SMALLER_MANTISSA_WIDTH:%.*]] = icmp ult i16 [[BIASED_EXP]], 25 +; CHECK-NEXT: br i1 [[EXP_SMALLER_MANTISSA_WIDTH]], label %[[FP_TO_I_IF_EXP_SMALL:.*]], label %[[FP_TO_I_IF_EXP_LARGE:.*]] +; CHECK: [[FP_TO_I_IF_EXP_SMALL]]: +; CHECK-NEXT: [[TMP6:%.*]] = sub i16 25, [[BIASED_EXP]] +; CHECK-NEXT: [[TMP7:%.*]] = lshr i16 [[SIGNIFICAND]], [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = mul i16 [[TMP7]], [[SIGN]] +; CHECK-NEXT: br label %[[FP_TO_I_CLEANUP]] +; CHECK: [[FP_TO_I_IF_EXP_LARGE]]: +; CHECK-NEXT: [[TMP9:%.*]] = add i16 [[BIASED_EXP]], -25 +; CHECK-NEXT: [[TMP10:%.*]] = shl i16 [[SIGNIFICAND]], [[TMP9]] +; CHECK-NEXT: [[TMP11:%.*]] = mul i16 [[TMP10]], [[SIGN]] +; CHECK-NEXT: br label %[[FP_TO_I_CLEANUP]] +; CHECK: [[FP_TO_I_CLEANUP]]: +; CHECK-NEXT: [[TMP12:%.*]] = phi i16 [ [[SATURATED]], %[[FP_TO_I_IF_SATURATE]] ], [ [[TMP8]], %[[FP_TO_I_IF_EXP_SMALL]] ], [ [[TMP11]], %[[FP_TO_I_IF_EXP_LARGE]] ], [ 0, %[[FP_TO_I_ENTRY]] ] +; CHECK-NEXT: ret i16 [[TMP12]] +; + %res = fptosi half %x to i16 + ret i16 %res +} + +define i16 @fptosi_f16_i16_noundef(half noundef %x) { +; CHECK-LABEL: define i16 @fptosi_f16_i16_noundef( +; CHECK-SAME: half noundef [[X:%.*]]) { +; CHECK-NEXT: [[FP_TO_I_ENTRY:.*]]: ; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP1]], i16 1, i16 -1 @@ -48,7 +90,8 @@ define i24 @fptosi_f16_i24(half %x) { ; CHECK-LABEL: define i24 @fptosi_f16_i24( ; CHECK-SAME: half [[X:%.*]]) { ; CHECK-NEXT: [[FP_TO_I_ENTRY:.*]]: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16 +; CHECK-NEXT: [[TMP1:%.*]] = freeze half [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[TMP1]] to i16 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i16 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP2]], i24 1, i24 -1 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i16 [[TMP0]], 10 @@ -92,7 +135,8 @@ define i8 @fptosi_f16_i8(half %x) { ; CHECK-LABEL: define i8 @fptosi_f16_i8( ; CHECK-SAME: half [[X:%.*]]) { ; CHECK-NEXT: [[FP_TO_I_ENTRY:.*]]: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16 +; CHECK-NEXT: [[TMP16:%.*]] = freeze half [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[TMP16]] to i16 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP1]], i8 1, i8 -1 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i16 [[TMP0]], 10 @@ -136,7 +180,8 @@ define i16 @fptoui_f16_i16(half %x) { ; CHECK-LABEL: define i16 @fptoui_f16_i16( ; CHECK-SAME: half [[X:%.*]]) { ; CHECK-NEXT: [[FP_TO_I_ENTRY:.*]]: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16 +; CHECK-NEXT: [[TMP13:%.*]] = freeze half [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[TMP13]] to i16 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP1]], i16 1, i16 -1 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i16 [[TMP0]], 10 @@ -177,7 +222,8 @@ define i24 @fptoui_f16_i24(half %x) { ; CHECK-LABEL: define i24 @fptoui_f16_i24( ; CHECK-SAME: half [[X:%.*]]) { ; CHECK-NEXT: [[FP_TO_I_ENTRY:.*]]: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16 +; CHECK-NEXT: [[TMP1:%.*]] = freeze half [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[TMP1]] to i16 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i16 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP2]], i24 1, i24 -1 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i16 [[TMP0]], 10 @@ -221,7 +267,8 @@ define i8 @fptoui_f16_i8(half %x) { ; CHECK-LABEL: define i8 @fptoui_f16_i8( ; CHECK-SAME: half [[X:%.*]]) { ; CHECK-NEXT: [[FP_TO_I_ENTRY:.*]]: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[X]] to i16 +; CHECK-NEXT: [[TMP16:%.*]] = freeze half [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast half [[TMP16]] to i16 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP1]], i8 1, i8 -1 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i16 [[TMP0]], 10 diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll new file mode 100644 index 0000000000000..8077f5af1d8df --- /dev/null +++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll @@ -0,0 +1,375 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -mtriple=x86_64-- -passes='require,expand-ir-insts' -expand-fp-convert-bits=0 < %s | FileCheck %s + +; Test small bit widths that can be verified by alive2. + +define half @uitofp_i32_f16(i32 %x) { +; CHECK-LABEL: define half @uitofp_i32_f16( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[ITOFP_ENTRY:.*]]: +; CHECK-NEXT: [[TMP8:%.*]] = freeze i32 [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[TMP8]], 0 +; CHECK-NEXT: br i1 [[TMP0]], label %[[ITOFP_RETURN:.*]], label %[[ITOFP_IF_END:.*]] +; CHECK: [[ITOFP_IF_END]]: +; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[TMP8]], 31 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], [[TMP8]] +; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP8]], i1 true) +; CHECK-NEXT: [[TMP5:%.*]] = sub i32 32, [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = sub i32 31, [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP5]], 24 +; CHECK-NEXT: br i1 [[TMP7]], label %[[ITOFP_IF_THEN4:.*]], label %[[ITOFP_IF_ELSE:.*]] +; CHECK: [[ITOFP_IF_THEN4]]: +; CHECK-NEXT: switch i32 [[TMP5]], label %[[ITOFP_SW_DEFAULT:.*]] [ +; CHECK-NEXT: i32 25, label %[[ITOFP_SW_BB:.*]] +; CHECK-NEXT: i32 26, label %[[ITOFP_SW_EPILOG:.*]] +; CHECK-NEXT: ] +; CHECK: [[ITOFP_SW_BB]]: +; CHECK-NEXT: [[TMP41:%.*]] = shl i32 [[TMP8]], 1 +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_DEFAULT]]: +; CHECK-NEXT: [[TMP9:%.*]] = sub i32 6, [[TMP4]] +; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP8]], [[TMP9]] +; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP4]], 26 +; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 -1, [[TMP11]] +; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], [[TMP8]] +; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +; CHECK-NEXT: [[TMP15:%.*]] = zext i1 [[TMP14]] to i32 +; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP10]], [[TMP15]] +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_EPILOG]]: +; CHECK-NEXT: [[TMP17:%.*]] = phi i32 [ [[TMP16]], %[[ITOFP_SW_DEFAULT]] ], [ [[TMP8]], %[[ITOFP_IF_THEN4]] ], [ [[TMP41]], %[[ITOFP_SW_BB]] ] +; CHECK-NEXT: [[TMP18:%.*]] = lshr i32 [[TMP17]], 2 +; CHECK-NEXT: [[TMP19:%.*]] = and i32 [[TMP18]], 1 +; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP17]], [[TMP19]] +; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], 1 +; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP21]], 2 +; CHECK-NEXT: [[A3:%.*]] = and i32 [[TMP21]], 67108864 +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[A3]], 0 +; CHECK-NEXT: [[TMP24:%.*]] = lshr i32 [[TMP22]], 32 +; CHECK-NEXT: br i1 [[TMP23]], label %[[ITOFP_IF_END26:.*]], label %[[ITOFP_IF_THEN20:.*]] +; CHECK: [[ITOFP_IF_THEN20]]: +; CHECK-NEXT: [[TMP25:%.*]] = lshr i32 [[TMP21]], 3 +; CHECK-NEXT: [[TMP26:%.*]] = lshr i32 [[TMP25]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_ELSE]]: +; CHECK-NEXT: [[TMP27:%.*]] = add i32 [[TMP4]], -8 +; CHECK-NEXT: [[TMP28:%.*]] = shl i32 [[TMP8]], [[TMP27]] +; CHECK-NEXT: [[TMP29:%.*]] = lshr i32 [[TMP28]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_END26]]: +; CHECK-NEXT: [[TMP30:%.*]] = phi i32 [ [[TMP25]], %[[ITOFP_IF_THEN20]] ], [ [[TMP22]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP28]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP31:%.*]] = phi i32 [ [[TMP5]], %[[ITOFP_IF_THEN20]] ], [ [[TMP6]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP6]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP32:%.*]] = and i32 [[TMP1]], -2147483648 +; CHECK-NEXT: [[TMP33:%.*]] = shl i32 [[TMP31]], 23 +; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP33]], 1065353216 +; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP30]], 8388607 +; CHECK-NEXT: [[TMP36:%.*]] = or i32 [[TMP35]], [[TMP32]] +; CHECK-NEXT: [[TMP37:%.*]] = or i32 [[TMP35]], [[TMP34]] +; CHECK-NEXT: [[TMP38:%.*]] = bitcast i32 [[TMP37]] to float +; CHECK-NEXT: [[TMP39:%.*]] = fptrunc float [[TMP38]] to half +; CHECK-NEXT: br label %[[ITOFP_RETURN]] +; CHECK: [[ITOFP_RETURN]]: +; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ] +; CHECK-NEXT: ret half [[TMP40]] +; + %res = uitofp i32 %x to half + ret half %res +} + +define half @uitofp_i32_f16_noundef(i32 noundef %x) { +; CHECK-LABEL: define half @uitofp_i32_f16_noundef( +; CHECK-SAME: i32 noundef [[X:%.*]]) { +; CHECK-NEXT: [[ITOFP_ENTRY:.*]]: +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[X]], 0 +; CHECK-NEXT: br i1 [[TMP0]], label %[[ITOFP_RETURN:.*]], label %[[ITOFP_IF_END:.*]] +; CHECK: [[ITOFP_IF_END]]: +; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X]], 31 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], [[X]] +; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X]], i1 true) +; CHECK-NEXT: [[TMP5:%.*]] = sub i32 32, [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = sub i32 31, [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP5]], 24 +; CHECK-NEXT: br i1 [[TMP7]], label %[[ITOFP_IF_THEN4:.*]], label %[[ITOFP_IF_ELSE:.*]] +; CHECK: [[ITOFP_IF_THEN4]]: +; CHECK-NEXT: switch i32 [[TMP5]], label %[[ITOFP_SW_DEFAULT:.*]] [ +; CHECK-NEXT: i32 25, label %[[ITOFP_SW_BB:.*]] +; CHECK-NEXT: i32 26, label %[[ITOFP_SW_EPILOG:.*]] +; CHECK-NEXT: ] +; CHECK: [[ITOFP_SW_BB]]: +; CHECK-NEXT: [[TMP8:%.*]] = shl i32 [[X]], 1 +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_DEFAULT]]: +; CHECK-NEXT: [[TMP9:%.*]] = sub i32 6, [[TMP4]] +; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[X]], [[TMP9]] +; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP4]], 26 +; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 -1, [[TMP11]] +; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], [[X]] +; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +; CHECK-NEXT: [[TMP15:%.*]] = zext i1 [[TMP14]] to i32 +; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP10]], [[TMP15]] +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_EPILOG]]: +; CHECK-NEXT: [[TMP17:%.*]] = phi i32 [ [[TMP16]], %[[ITOFP_SW_DEFAULT]] ], [ [[X]], %[[ITOFP_IF_THEN4]] ], [ [[TMP8]], %[[ITOFP_SW_BB]] ] +; CHECK-NEXT: [[TMP18:%.*]] = lshr i32 [[TMP17]], 2 +; CHECK-NEXT: [[TMP19:%.*]] = and i32 [[TMP18]], 1 +; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP17]], [[TMP19]] +; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], 1 +; CHECK-NEXT: [[TMP22:%.*]] = lshr i32 [[TMP21]], 2 +; CHECK-NEXT: [[A3:%.*]] = and i32 [[TMP21]], 67108864 +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[A3]], 0 +; CHECK-NEXT: [[TMP24:%.*]] = lshr i32 [[TMP22]], 32 +; CHECK-NEXT: br i1 [[TMP23]], label %[[ITOFP_IF_END26:.*]], label %[[ITOFP_IF_THEN20:.*]] +; CHECK: [[ITOFP_IF_THEN20]]: +; CHECK-NEXT: [[TMP25:%.*]] = lshr i32 [[TMP21]], 3 +; CHECK-NEXT: [[TMP26:%.*]] = lshr i32 [[TMP25]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_ELSE]]: +; CHECK-NEXT: [[TMP27:%.*]] = add i32 [[TMP4]], -8 +; CHECK-NEXT: [[TMP28:%.*]] = shl i32 [[X]], [[TMP27]] +; CHECK-NEXT: [[TMP29:%.*]] = lshr i32 [[TMP28]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_END26]]: +; CHECK-NEXT: [[TMP30:%.*]] = phi i32 [ [[TMP25]], %[[ITOFP_IF_THEN20]] ], [ [[TMP22]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP28]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP31:%.*]] = phi i32 [ [[TMP5]], %[[ITOFP_IF_THEN20]] ], [ [[TMP6]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP6]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP32:%.*]] = and i32 [[TMP1]], -2147483648 +; CHECK-NEXT: [[TMP33:%.*]] = shl i32 [[TMP31]], 23 +; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP33]], 1065353216 +; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP30]], 8388607 +; CHECK-NEXT: [[TMP36:%.*]] = or i32 [[TMP35]], [[TMP32]] +; CHECK-NEXT: [[TMP37:%.*]] = or i32 [[TMP35]], [[TMP34]] +; CHECK-NEXT: [[TMP38:%.*]] = bitcast i32 [[TMP37]] to float +; CHECK-NEXT: [[TMP39:%.*]] = fptrunc float [[TMP38]] to half +; CHECK-NEXT: br label %[[ITOFP_RETURN]] +; CHECK: [[ITOFP_RETURN]]: +; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ] +; CHECK-NEXT: ret half [[TMP40]] +; + %res = uitofp i32 %x to half + ret half %res +} + +define half @uitofp_i16_f16(i16 %x) { +; CHECK-LABEL: define half @uitofp_i16_f16( +; CHECK-SAME: i16 [[X:%.*]]) { +; CHECK-NEXT: [[ITOFP_ENTRY:.*]]: +; CHECK-NEXT: [[TMP42:%.*]] = freeze i16 [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[TMP42]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0 +; CHECK-NEXT: br i1 [[TMP1]], label %[[ITOFP_RETURN:.*]], label %[[ITOFP_IF_END:.*]] +; CHECK: [[ITOFP_IF_END]]: +; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP0]], 31 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], [[TMP0]] +; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 true) +; CHECK-NEXT: [[TMP6:%.*]] = sub i32 32, [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = sub i32 31, [[TMP5]] +; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i32 [[TMP6]], 24 +; CHECK-NEXT: br i1 [[TMP8]], label %[[ITOFP_IF_THEN4:.*]], label %[[ITOFP_IF_ELSE:.*]] +; CHECK: [[ITOFP_IF_THEN4]]: +; CHECK-NEXT: switch i32 [[TMP6]], label %[[ITOFP_SW_DEFAULT:.*]] [ +; CHECK-NEXT: i32 25, label %[[ITOFP_SW_BB:.*]] +; CHECK-NEXT: i32 26, label %[[ITOFP_SW_EPILOG:.*]] +; CHECK-NEXT: ] +; CHECK: [[ITOFP_SW_BB]]: +; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP0]], 1 +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_DEFAULT]]: +; CHECK-NEXT: [[TMP10:%.*]] = sub i32 6, [[TMP5]] +; CHECK-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP0]], [[TMP10]] +; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP5]], 26 +; CHECK-NEXT: [[TMP13:%.*]] = lshr i32 -1, [[TMP12]] +; CHECK-NEXT: [[TMP14:%.*]] = and i32 [[TMP13]], [[TMP0]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +; CHECK-NEXT: [[TMP16:%.*]] = zext i1 [[TMP15]] to i32 +; CHECK-NEXT: [[TMP17:%.*]] = or i32 [[TMP11]], [[TMP16]] +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_EPILOG]]: +; CHECK-NEXT: [[TMP18:%.*]] = phi i32 [ [[TMP17]], %[[ITOFP_SW_DEFAULT]] ], [ [[TMP0]], %[[ITOFP_IF_THEN4]] ], [ [[TMP9]], %[[ITOFP_SW_BB]] ] +; CHECK-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP18]], 2 +; CHECK-NEXT: [[TMP20:%.*]] = and i32 [[TMP19]], 1 +; CHECK-NEXT: [[TMP21:%.*]] = or i32 [[TMP18]], [[TMP20]] +; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], 1 +; CHECK-NEXT: [[TMP23:%.*]] = lshr i32 [[TMP22]], 2 +; CHECK-NEXT: [[A3:%.*]] = and i32 [[TMP22]], 67108864 +; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i32 [[A3]], 0 +; CHECK-NEXT: [[TMP25:%.*]] = lshr i32 [[TMP23]], 32 +; CHECK-NEXT: br i1 [[TMP24]], label %[[ITOFP_IF_END26:.*]], label %[[ITOFP_IF_THEN20:.*]] +; CHECK: [[ITOFP_IF_THEN20]]: +; CHECK-NEXT: [[TMP26:%.*]] = lshr i32 [[TMP22]], 3 +; CHECK-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP26]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_ELSE]]: +; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[TMP5]], -8 +; CHECK-NEXT: [[TMP29:%.*]] = shl i32 [[TMP0]], [[TMP28]] +; CHECK-NEXT: [[TMP30:%.*]] = lshr i32 [[TMP29]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_END26]]: +; CHECK-NEXT: [[TMP31:%.*]] = phi i32 [ [[TMP26]], %[[ITOFP_IF_THEN20]] ], [ [[TMP23]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP29]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP32:%.*]] = phi i32 [ [[TMP6]], %[[ITOFP_IF_THEN20]] ], [ [[TMP7]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP7]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP33:%.*]] = and i32 [[TMP2]], -2147483648 +; CHECK-NEXT: [[TMP34:%.*]] = shl i32 [[TMP32]], 23 +; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[TMP34]], 1065353216 +; CHECK-NEXT: [[TMP36:%.*]] = and i32 [[TMP31]], 8388607 +; CHECK-NEXT: [[TMP37:%.*]] = or i32 [[TMP36]], [[TMP33]] +; CHECK-NEXT: [[TMP38:%.*]] = or i32 [[TMP36]], [[TMP35]] +; CHECK-NEXT: [[TMP39:%.*]] = bitcast i32 [[TMP38]] to float +; CHECK-NEXT: [[TMP40:%.*]] = fptrunc float [[TMP39]] to half +; CHECK-NEXT: br label %[[ITOFP_RETURN]] +; CHECK: [[ITOFP_RETURN]]: +; CHECK-NEXT: [[TMP41:%.*]] = phi half [ [[TMP40]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ] +; CHECK-NEXT: ret half [[TMP41]] +; + %res = uitofp i16 %x to half + ret half %res +} + +define half @sitofp_i32_f16(i32 %x) { +; CHECK-LABEL: define half @sitofp_i32_f16( +; CHECK-SAME: i32 [[X:%.*]]) { +; CHECK-NEXT: [[ITOFP_ENTRY:.*]]: +; CHECK-NEXT: [[TMP41:%.*]] = freeze i32 [[X]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[TMP41]], 0 +; CHECK-NEXT: br i1 [[TMP0]], label %[[ITOFP_RETURN:.*]], label %[[ITOFP_IF_END:.*]] +; CHECK: [[ITOFP_IF_END]]: +; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[TMP41]], 31 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], [[TMP41]] +; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP3]], i1 true) +; CHECK-NEXT: [[TMP5:%.*]] = sub i32 32, [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = sub i32 31, [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP5]], 24 +; CHECK-NEXT: br i1 [[TMP7]], label %[[ITOFP_IF_THEN4:.*]], label %[[ITOFP_IF_ELSE:.*]] +; CHECK: [[ITOFP_IF_THEN4]]: +; CHECK-NEXT: switch i32 [[TMP5]], label %[[ITOFP_SW_DEFAULT:.*]] [ +; CHECK-NEXT: i32 25, label %[[ITOFP_SW_BB:.*]] +; CHECK-NEXT: i32 26, label %[[ITOFP_SW_EPILOG:.*]] +; CHECK-NEXT: ] +; CHECK: [[ITOFP_SW_BB]]: +; CHECK-NEXT: [[TMP8:%.*]] = shl i32 [[TMP3]], 1 +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_DEFAULT]]: +; CHECK-NEXT: [[TMP9:%.*]] = sub i32 6, [[TMP4]] +; CHECK-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP3]], [[TMP9]] +; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[TMP4]], 26 +; CHECK-NEXT: [[TMP12:%.*]] = lshr i32 -1, [[TMP11]] +; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], [[TMP3]] +; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +; CHECK-NEXT: [[TMP15:%.*]] = zext i1 [[TMP14]] to i32 +; CHECK-NEXT: [[TMP16:%.*]] = or i32 [[TMP10]], [[TMP15]] +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_EPILOG]]: +; CHECK-NEXT: [[TMP17:%.*]] = phi i32 [ [[TMP16]], %[[ITOFP_SW_DEFAULT]] ], [ [[TMP3]], %[[ITOFP_IF_THEN4]] ], [ [[TMP8]], %[[ITOFP_SW_BB]] ] +; CHECK-NEXT: [[TMP18:%.*]] = lshr i32 [[TMP17]], 2 +; CHECK-NEXT: [[TMP19:%.*]] = and i32 [[TMP18]], 1 +; CHECK-NEXT: [[TMP20:%.*]] = or i32 [[TMP17]], [[TMP19]] +; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], 1 +; CHECK-NEXT: [[TMP22:%.*]] = ashr i32 [[TMP21]], 2 +; CHECK-NEXT: [[A3:%.*]] = and i32 [[TMP21]], 67108864 +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[A3]], 0 +; CHECK-NEXT: [[TMP24:%.*]] = lshr i32 [[TMP22]], 32 +; CHECK-NEXT: br i1 [[TMP23]], label %[[ITOFP_IF_END26:.*]], label %[[ITOFP_IF_THEN20:.*]] +; CHECK: [[ITOFP_IF_THEN20]]: +; CHECK-NEXT: [[TMP25:%.*]] = ashr i32 [[TMP21]], 3 +; CHECK-NEXT: [[TMP26:%.*]] = lshr i32 [[TMP25]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_ELSE]]: +; CHECK-NEXT: [[TMP27:%.*]] = add i32 [[TMP4]], -8 +; CHECK-NEXT: [[TMP28:%.*]] = shl i32 [[TMP3]], [[TMP27]] +; CHECK-NEXT: [[TMP29:%.*]] = lshr i32 [[TMP28]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_END26]]: +; CHECK-NEXT: [[TMP30:%.*]] = phi i32 [ [[TMP25]], %[[ITOFP_IF_THEN20]] ], [ [[TMP22]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP28]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP31:%.*]] = phi i32 [ [[TMP5]], %[[ITOFP_IF_THEN20]] ], [ [[TMP6]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP6]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP32:%.*]] = and i32 [[TMP1]], -2147483648 +; CHECK-NEXT: [[TMP33:%.*]] = shl i32 [[TMP31]], 23 +; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP33]], 1065353216 +; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP30]], 8388607 +; CHECK-NEXT: [[TMP36:%.*]] = or i32 [[TMP35]], [[TMP32]] +; CHECK-NEXT: [[TMP37:%.*]] = or i32 [[TMP36]], [[TMP34]] +; CHECK-NEXT: [[TMP38:%.*]] = bitcast i32 [[TMP37]] to float +; CHECK-NEXT: [[TMP39:%.*]] = fptrunc float [[TMP38]] to half +; CHECK-NEXT: br label %[[ITOFP_RETURN]] +; CHECK: [[ITOFP_RETURN]]: +; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ] +; CHECK-NEXT: ret half [[TMP40]] +; + %res = sitofp i32 %x to half + ret half %res +} + +define half @sitofp_i16_f16(i16 %x) { +; CHECK-LABEL: define half @sitofp_i16_f16( +; CHECK-SAME: i16 [[X:%.*]]) { +; CHECK-NEXT: [[ITOFP_ENTRY:.*]]: +; CHECK-NEXT: [[TMP42:%.*]] = freeze i16 [[X]] +; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TMP42]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[TMP0]], label %[[ITOFP_RETURN:.*]], label %[[ITOFP_IF_END:.*]] +; CHECK: [[ITOFP_IF_END]]: +; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP1]], 31 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP4]], i1 true) +; CHECK-NEXT: [[TMP6:%.*]] = sub i32 32, [[TMP5]] +; CHECK-NEXT: [[TMP8:%.*]] = sub i32 31, [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP6]], 24 +; CHECK-NEXT: br i1 [[TMP7]], label %[[ITOFP_IF_THEN4:.*]], label %[[ITOFP_IF_ELSE:.*]] +; CHECK: [[ITOFP_IF_THEN4]]: +; CHECK-NEXT: switch i32 [[TMP6]], label %[[ITOFP_SW_DEFAULT:.*]] [ +; CHECK-NEXT: i32 25, label %[[ITOFP_SW_BB:.*]] +; CHECK-NEXT: i32 26, label %[[ITOFP_SW_EPILOG:.*]] +; CHECK-NEXT: ] +; CHECK: [[ITOFP_SW_BB]]: +; CHECK-NEXT: [[TMP9:%.*]] = shl i32 [[TMP4]], 1 +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_DEFAULT]]: +; CHECK-NEXT: [[TMP10:%.*]] = sub i32 6, [[TMP5]] +; CHECK-NEXT: [[TMP11:%.*]] = lshr i32 [[TMP4]], [[TMP10]] +; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP5]], 26 +; CHECK-NEXT: [[TMP13:%.*]] = lshr i32 -1, [[TMP12]] +; CHECK-NEXT: [[TMP14:%.*]] = and i32 [[TMP13]], [[TMP4]] +; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 +; CHECK-NEXT: [[TMP16:%.*]] = zext i1 [[TMP15]] to i32 +; CHECK-NEXT: [[TMP17:%.*]] = or i32 [[TMP11]], [[TMP16]] +; CHECK-NEXT: br label %[[ITOFP_SW_EPILOG]] +; CHECK: [[ITOFP_SW_EPILOG]]: +; CHECK-NEXT: [[TMP18:%.*]] = phi i32 [ [[TMP17]], %[[ITOFP_SW_DEFAULT]] ], [ [[TMP4]], %[[ITOFP_IF_THEN4]] ], [ [[TMP9]], %[[ITOFP_SW_BB]] ] +; CHECK-NEXT: [[TMP19:%.*]] = lshr i32 [[TMP18]], 2 +; CHECK-NEXT: [[TMP20:%.*]] = and i32 [[TMP19]], 1 +; CHECK-NEXT: [[TMP21:%.*]] = or i32 [[TMP18]], [[TMP20]] +; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], 1 +; CHECK-NEXT: [[TMP24:%.*]] = ashr i32 [[TMP22]], 2 +; CHECK-NEXT: [[A3:%.*]] = and i32 [[TMP22]], 67108864 +; CHECK-NEXT: [[TMP23:%.*]] = icmp eq i32 [[A3]], 0 +; CHECK-NEXT: [[TMP25:%.*]] = lshr i32 [[TMP24]], 32 +; CHECK-NEXT: br i1 [[TMP23]], label %[[ITOFP_IF_END26:.*]], label %[[ITOFP_IF_THEN20:.*]] +; CHECK: [[ITOFP_IF_THEN20]]: +; CHECK-NEXT: [[TMP26:%.*]] = ashr i32 [[TMP22]], 3 +; CHECK-NEXT: [[TMP27:%.*]] = lshr i32 [[TMP26]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_ELSE]]: +; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[TMP5]], -8 +; CHECK-NEXT: [[TMP29:%.*]] = shl i32 [[TMP4]], [[TMP28]] +; CHECK-NEXT: [[TMP30:%.*]] = lshr i32 [[TMP29]], 32 +; CHECK-NEXT: br label %[[ITOFP_IF_END26]] +; CHECK: [[ITOFP_IF_END26]]: +; CHECK-NEXT: [[TMP31:%.*]] = phi i32 [ [[TMP26]], %[[ITOFP_IF_THEN20]] ], [ [[TMP24]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP29]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP32:%.*]] = phi i32 [ [[TMP6]], %[[ITOFP_IF_THEN20]] ], [ [[TMP8]], %[[ITOFP_SW_EPILOG]] ], [ [[TMP8]], %[[ITOFP_IF_ELSE]] ] +; CHECK-NEXT: [[TMP33:%.*]] = and i32 [[TMP2]], -2147483648 +; CHECK-NEXT: [[TMP34:%.*]] = shl i32 [[TMP32]], 23 +; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[TMP34]], 1065353216 +; CHECK-NEXT: [[TMP36:%.*]] = and i32 [[TMP31]], 8388607 +; CHECK-NEXT: [[TMP37:%.*]] = or i32 [[TMP36]], [[TMP33]] +; CHECK-NEXT: [[TMP41:%.*]] = or i32 [[TMP37]], [[TMP35]] +; CHECK-NEXT: [[TMP38:%.*]] = bitcast i32 [[TMP41]] to float +; CHECK-NEXT: [[TMP39:%.*]] = fptrunc float [[TMP38]] to half +; CHECK-NEXT: br label %[[ITOFP_RETURN]] +; CHECK: [[ITOFP_RETURN]]: +; CHECK-NEXT: [[TMP40:%.*]] = phi half [ [[TMP39]], %[[ITOFP_IF_END26]] ], [ 0xH0000, %[[ITOFP_ENTRY]] ] +; CHECK-NEXT: ret half [[TMP40]] +; + %res = sitofp i16 %x to half + ret half %res +} diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptosi129.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptosi129.ll index 24c1476fdb512..97268e5d6917b 100644 --- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptosi129.ll +++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptosi129.ll @@ -15,7 +15,8 @@ define i129 @halftosi129(half %a) { define i129 @floattosi129(float %a) { ; CHECK-LABEL: @floattosi129( ; CHECK-NEXT: fp-to-i-entry: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[A:%.*]] to i32 +; CHECK-NEXT: [[A:%.*]] = freeze float [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[A]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP2]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP0]], 23 @@ -58,7 +59,8 @@ define i129 @floattosi129(float %a) { define i129 @doubletosi129(double %a) { ; CHECK-LABEL: @doubletosi129( ; CHECK-NEXT: fp-to-i-entry: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[A:%.*]] to i64 +; CHECK-NEXT: [[A:%.*]] = freeze double [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[A]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i64 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP2]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP0]], 52 @@ -101,7 +103,8 @@ define i129 @doubletosi129(double %a) { define i129 @x86_fp80tosi129(x86_fp80 %a) { ; CHECK-LABEL: @x86_fp80tosi129( ; CHECK-NEXT: fp-to-i-entry: -; CHECK-NEXT: [[TMP0:%.*]] = fpext x86_fp80 [[A:%.*]] to fp128 +; CHECK-NEXT: [[A:%.*]] = freeze x86_fp80 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = fpext x86_fp80 [[A]] to fp128 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast fp128 [[TMP0]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i128 [[TMP1]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP3]], i129 1, i129 -1 @@ -145,7 +148,8 @@ define i129 @x86_fp80tosi129(x86_fp80 %a) { define i129 @fp128tosi129(fp128 %a) { ; CHECK-LABEL: @fp128tosi129( ; CHECK-NEXT: fp-to-i-entry: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast fp128 [[A:%.*]] to i128 +; CHECK-NEXT: [[A:%.*]] = freeze fp128 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast fp128 [[A]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i128 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP2]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i128 [[TMP0]], 112 @@ -189,7 +193,8 @@ define <2 x i129> @floattosi129v2(<2 x float> %a) { ; CHECK-LABEL: @floattosi129v2( ; CHECK-NEXT: fp-to-i-entryfp-to-i-entry: ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x float> [[A:%.*]], i64 0 -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[TMP0]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = freeze float [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[TMP2]] to i32 ; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP1]], -1 ; CHECK-NEXT: [[SIGN7:%.*]] = select i1 [[TMP3]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP1]], 23 @@ -225,7 +230,8 @@ define <2 x i129> @floattosi129v2(<2 x float> %a) { ; CHECK-NEXT: [[TMP14:%.*]] = phi i129 [ [[SATURATED11]], [[FP_TO_I_IF_SATURATE3]] ], [ [[TMP10]], [[FP_TO_I_IF_EXP_SMALL5]] ], [ [[TMP13]], [[FP_TO_I_IF_EXP_LARGE6]] ], [ 0, [[FP_TO_I_ENTRYFP_TO_I_ENTRY:%.*]] ] ; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i129> poison, i129 [[TMP14]], i64 0 ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[A]], i64 1 -; CHECK-NEXT: [[TMP17:%.*]] = bitcast float [[TMP16]] to i32 +; CHECK-NEXT: [[TMP35:%.*]] = freeze float [[TMP16]] +; CHECK-NEXT: [[TMP17:%.*]] = bitcast float [[TMP35]] to i32 ; CHECK-NEXT: [[TMP19:%.*]] = icmp sgt i32 [[TMP17]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP19]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP21:%.*]] = lshr i32 [[TMP17]], 23 diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptoui129.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptoui129.ll index fd29c01ef580d..5afff792c1508 100644 --- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptoui129.ll +++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptoui129.ll @@ -15,7 +15,8 @@ define i129 @halftoui129(half %a) { define i129 @floattoui129(float %a) { ; CHECK-LABEL: @floattoui129( ; CHECK-NEXT: fp-to-i-entry: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[A:%.*]] to i32 +; CHECK-NEXT: [[A:%.*]] = freeze float [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[A]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP2]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP0]], 23 @@ -58,7 +59,8 @@ define i129 @floattoui129(float %a) { define i129 @doubletoui129(double %a) { ; CHECK-LABEL: @doubletoui129( ; CHECK-NEXT: fp-to-i-entry: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[A:%.*]] to i64 +; CHECK-NEXT: [[A:%.*]] = freeze double [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[A]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i64 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP2]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP0]], 52 @@ -101,7 +103,8 @@ define i129 @doubletoui129(double %a) { define i129 @x86_fp80toui129(x86_fp80 %a) { ; CHECK-LABEL: @x86_fp80toui129( ; CHECK-NEXT: fp-to-i-entry: -; CHECK-NEXT: [[TMP0:%.*]] = fpext x86_fp80 [[A:%.*]] to fp128 +; CHECK-NEXT: [[A:%.*]] = freeze x86_fp80 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = fpext x86_fp80 [[A]] to fp128 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast fp128 [[TMP0]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i128 [[TMP1]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP3]], i129 1, i129 -1 @@ -145,7 +148,8 @@ define i129 @x86_fp80toui129(x86_fp80 %a) { define i129 @fp128toui129(fp128 %a) { ; CHECK-LABEL: @fp128toui129( ; CHECK-NEXT: fp-to-i-entry: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast fp128 [[A:%.*]] to i128 +; CHECK-NEXT: [[A:%.*]] = freeze fp128 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = bitcast fp128 [[A]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt i128 [[TMP0]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP2]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP5:%.*]] = lshr i128 [[TMP0]], 112 @@ -189,7 +193,8 @@ define <2 x i129> @floattoui129v2(<2 x float> %a) { ; CHECK-LABEL: @floattoui129v2( ; CHECK-NEXT: fp-to-i-entryfp-to-i-entry: ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x float> [[A:%.*]], i64 0 -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[TMP0]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = freeze float [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[TMP2]] to i32 ; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP1]], -1 ; CHECK-NEXT: [[SIGN7:%.*]] = select i1 [[TMP3]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP6:%.*]] = lshr i32 [[TMP1]], 23 @@ -225,7 +230,8 @@ define <2 x i129> @floattoui129v2(<2 x float> %a) { ; CHECK-NEXT: [[TMP14:%.*]] = phi i129 [ [[SATURATED11]], [[FP_TO_I_IF_SATURATE3]] ], [ [[TMP10]], [[FP_TO_I_IF_EXP_SMALL5]] ], [ [[TMP13]], [[FP_TO_I_IF_EXP_LARGE6]] ], [ 0, [[FP_TO_I_ENTRYFP_TO_I_ENTRY:%.*]] ] ; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i129> poison, i129 [[TMP14]], i64 0 ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[A]], i64 1 -; CHECK-NEXT: [[TMP17:%.*]] = bitcast float [[TMP16]] to i32 +; CHECK-NEXT: [[TMP35:%.*]] = freeze float [[TMP16]] +; CHECK-NEXT: [[TMP17:%.*]] = bitcast float [[TMP35]] to i32 ; CHECK-NEXT: [[TMP19:%.*]] = icmp sgt i32 [[TMP17]], -1 ; CHECK-NEXT: [[SIGN:%.*]] = select i1 [[TMP19]], i129 1, i129 -1 ; CHECK-NEXT: [[TMP21:%.*]] = lshr i32 [[TMP17]], 23 diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll index fab6e431872e7..a3677bafb4449 100644 --- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll +++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll @@ -5,7 +5,8 @@ define half @si129tohalf(i129 %a) { ; CHECK-LABEL: @si129tohalf( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -90,7 +91,8 @@ define half @si129tohalf(i129 %a) { define float @si129tofloat(i129 %a) { ; CHECK-LABEL: @si129tofloat( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -174,7 +176,8 @@ define float @si129tofloat(i129 %a) { define double @si129todouble(i129 %a) { ; CHECK-LABEL: @si129todouble( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -263,7 +266,8 @@ define double @si129todouble(i129 %a) { define x86_fp80 @si129tox86_fp80(i129 %a) { ; CHECK-LABEL: @si129tox86_fp80( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -347,7 +351,8 @@ define x86_fp80 @si129tox86_fp80(i129 %a) { define fp128 @si129tofp128(i129 %a) { ; CHECK-LABEL: @si129tofp128( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -431,11 +436,12 @@ define <2 x float> @si129tofloatv2(<2 x i129> %a) { ; CHECK-LABEL: @si129tofloatv2( ; CHECK-NEXT: itofp-entryitofp-entry: ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i129> [[A:%.*]], i64 0 -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i129 [[TMP0]], 0 +; CHECK-NEXT: [[TMP110:%.*]] = freeze i129 [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i129 [[TMP110]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[ITOFP_RETURN1:%.*]], label [[ITOFP_IF_END2:%.*]] ; CHECK: itofp-if-end2: -; CHECK-NEXT: [[TMP2:%.*]] = ashr i129 [[TMP0]], 128 -; CHECK-NEXT: [[TMP3:%.*]] = xor i129 [[TMP2]], [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = ashr i129 [[TMP110]], 128 +; CHECK-NEXT: [[TMP3:%.*]] = xor i129 [[TMP2]], [[TMP110]] ; CHECK-NEXT: [[TMP4:%.*]] = sub i129 [[TMP3]], [[TMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = call i129 @llvm.ctlz.i129(i129 [[TMP4]], i1 true) ; CHECK-NEXT: [[TMP6:%.*]] = trunc i129 [[TMP5]] to i32 @@ -508,11 +514,12 @@ define <2 x float> @si129tofloatv2(<2 x i129> %a) { ; CHECK-NEXT: [[TMP53:%.*]] = phi float [ [[TMP52]], [[ITOFP_IF_END269]] ], [ 0.000000e+00, [[ITOFP_ENTRYITOFP_ENTRY:%.*]] ] ; CHECK-NEXT: [[TMP54:%.*]] = insertelement <2 x float> poison, float [[TMP53]], i64 0 ; CHECK-NEXT: [[TMP55:%.*]] = extractelement <2 x i129> [[A]], i64 1 -; CHECK-NEXT: [[TMP56:%.*]] = icmp eq i129 [[TMP55]], 0 +; CHECK-NEXT: [[TMP111:%.*]] = freeze i129 [[TMP55]] +; CHECK-NEXT: [[TMP56:%.*]] = icmp eq i129 [[TMP111]], 0 ; CHECK-NEXT: br i1 [[TMP56]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: -; CHECK-NEXT: [[TMP57:%.*]] = ashr i129 [[TMP55]], 128 -; CHECK-NEXT: [[TMP58:%.*]] = xor i129 [[TMP57]], [[TMP55]] +; CHECK-NEXT: [[TMP57:%.*]] = ashr i129 [[TMP111]], 128 +; CHECK-NEXT: [[TMP58:%.*]] = xor i129 [[TMP57]], [[TMP111]] ; CHECK-NEXT: [[TMP59:%.*]] = sub i129 [[TMP58]], [[TMP57]] ; CHECK-NEXT: [[TMP60:%.*]] = call i129 @llvm.ctlz.i129(i129 [[TMP59]], i1 true) ; CHECK-NEXT: [[TMP61:%.*]] = trunc i129 [[TMP60]] to i32 diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll index 3a3a8e40ea8d1..eed61b7c53989 100644 --- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll +++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-convert-ui129tofp.ll @@ -5,7 +5,8 @@ define half @ui129tohalf(i129 %a) { ; CHECK-LABEL: @ui129tohalf( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -90,7 +91,8 @@ define half @ui129tohalf(i129 %a) { define float @ui129tofloat(i129 %a) { ; CHECK-LABEL: @ui129tofloat( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -174,7 +176,8 @@ define float @ui129tofloat(i129 %a) { define double @ui129todouble(i129 %a) { ; CHECK-LABEL: @ui129todouble( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -263,7 +266,8 @@ define double @ui129todouble(i129 %a) { define x86_fp80 @ui129tox86_fp80(i129 %a) { ; CHECK-LABEL: @ui129tox86_fp80( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -347,7 +351,8 @@ define x86_fp80 @ui129tox86_fp80(i129 %a) { define fp128 @ui129tofp128(i129 %a) { ; CHECK-LABEL: @ui129tofp128( ; CHECK-NEXT: itofp-entry: -; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A:%.*]], 0 +; CHECK-NEXT: [[A:%.*]] = freeze i129 [[A1:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i129 [[A]], 0 ; CHECK-NEXT: br i1 [[TMP0]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: ; CHECK-NEXT: [[TMP1:%.*]] = ashr i129 [[A]], 128 @@ -431,13 +436,14 @@ define <2 x float> @ui129tofloatv2(<2 x i129> %a) { ; CHECK-LABEL: @ui129tofloatv2( ; CHECK-NEXT: itofp-entryitofp-entry: ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i129> [[A:%.*]], i64 0 -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i129 [[TMP0]], 0 +; CHECK-NEXT: [[TMP10:%.*]] = freeze i129 [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i129 [[TMP10]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label [[ITOFP_RETURN1:%.*]], label [[ITOFP_IF_END2:%.*]] ; CHECK: itofp-if-end2: -; CHECK-NEXT: [[TMP2:%.*]] = ashr i129 [[TMP0]], 128 -; CHECK-NEXT: [[TMP3:%.*]] = xor i129 [[TMP2]], [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = ashr i129 [[TMP10]], 128 +; CHECK-NEXT: [[TMP3:%.*]] = xor i129 [[TMP2]], [[TMP10]] ; CHECK-NEXT: [[TMP4:%.*]] = sub i129 [[TMP3]], [[TMP2]] -; CHECK-NEXT: [[TMP5:%.*]] = call i129 @llvm.ctlz.i129(i129 [[TMP0]], i1 true) +; CHECK-NEXT: [[TMP5:%.*]] = call i129 @llvm.ctlz.i129(i129 [[TMP10]], i1 true) ; CHECK-NEXT: [[TMP6:%.*]] = trunc i129 [[TMP5]] to i32 ; CHECK-NEXT: [[TMP7:%.*]] = sub i32 129, [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = sub i32 128, [[TMP6]] @@ -449,22 +455,22 @@ define <2 x float> @ui129tofloatv2(<2 x i129> %a) { ; CHECK-NEXT: i32 26, label [[ITOFP_SW_EPILOG6:%.*]] ; CHECK-NEXT: ] ; CHECK: itofp-sw-bb4: -; CHECK-NEXT: [[TMP10:%.*]] = shl i129 [[TMP0]], 1 +; CHECK-NEXT: [[TMP65:%.*]] = shl i129 [[TMP10]], 1 ; CHECK-NEXT: br label [[ITOFP_SW_EPILOG6]] ; CHECK: itofp-sw-default5: ; CHECK-NEXT: [[TMP11:%.*]] = sub i32 103, [[TMP6]] ; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i129 -; CHECK-NEXT: [[TMP13:%.*]] = lshr i129 [[TMP0]], [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = lshr i129 [[TMP10]], [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP6]], 26 ; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i129 ; CHECK-NEXT: [[TMP16:%.*]] = lshr i129 -1, [[TMP15]] -; CHECK-NEXT: [[TMP17:%.*]] = and i129 [[TMP16]], [[TMP0]] +; CHECK-NEXT: [[TMP17:%.*]] = and i129 [[TMP16]], [[TMP10]] ; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i129 [[TMP17]], 0 ; CHECK-NEXT: [[TMP19:%.*]] = zext i1 [[TMP18]] to i129 ; CHECK-NEXT: [[TMP20:%.*]] = or i129 [[TMP13]], [[TMP19]] ; CHECK-NEXT: br label [[ITOFP_SW_EPILOG6]] ; CHECK: itofp-sw-epilog6: -; CHECK-NEXT: [[TMP21:%.*]] = phi i129 [ [[TMP20]], [[ITOFP_SW_DEFAULT5]] ], [ [[TMP0]], [[ITOFP_IF_THEN43]] ], [ [[TMP10]], [[ITOFP_SW_BB4]] ] +; CHECK-NEXT: [[TMP21:%.*]] = phi i129 [ [[TMP20]], [[ITOFP_SW_DEFAULT5]] ], [ [[TMP10]], [[ITOFP_IF_THEN43]] ], [ [[TMP65]], [[ITOFP_SW_BB4]] ] ; CHECK-NEXT: [[TMP22:%.*]] = trunc i129 [[TMP21]] to i32 ; CHECK-NEXT: [[TMP23:%.*]] = lshr i32 [[TMP22]], 2 ; CHECK-NEXT: [[TMP24:%.*]] = and i32 [[TMP23]], 1 @@ -487,7 +493,7 @@ define <2 x float> @ui129tofloatv2(<2 x i129> %a) { ; CHECK: itofp-if-else8: ; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP6]], -105 ; CHECK-NEXT: [[TMP38:%.*]] = zext i32 [[TMP37]] to i129 -; CHECK-NEXT: [[TMP39:%.*]] = shl i129 [[TMP0]], [[TMP38]] +; CHECK-NEXT: [[TMP39:%.*]] = shl i129 [[TMP10]], [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = trunc i129 [[TMP39]] to i32 ; CHECK-NEXT: [[TMP41:%.*]] = lshr i129 [[TMP39]], 32 ; CHECK-NEXT: [[TMP42:%.*]] = trunc i129 [[TMP41]] to i32 @@ -508,13 +514,14 @@ define <2 x float> @ui129tofloatv2(<2 x i129> %a) { ; CHECK-NEXT: [[TMP53:%.*]] = phi float [ [[TMP52]], [[ITOFP_IF_END269]] ], [ 0.000000e+00, [[ITOFP_ENTRYITOFP_ENTRY:%.*]] ] ; CHECK-NEXT: [[TMP54:%.*]] = insertelement <2 x float> poison, float [[TMP53]], i64 0 ; CHECK-NEXT: [[TMP55:%.*]] = extractelement <2 x i129> [[A]], i64 1 -; CHECK-NEXT: [[TMP56:%.*]] = icmp eq i129 [[TMP55]], 0 +; CHECK-NEXT: [[TMP110:%.*]] = freeze i129 [[TMP55]] +; CHECK-NEXT: [[TMP56:%.*]] = icmp eq i129 [[TMP110]], 0 ; CHECK-NEXT: br i1 [[TMP56]], label [[ITOFP_RETURN:%.*]], label [[ITOFP_IF_END:%.*]] ; CHECK: itofp-if-end: -; CHECK-NEXT: [[TMP57:%.*]] = ashr i129 [[TMP55]], 128 -; CHECK-NEXT: [[TMP58:%.*]] = xor i129 [[TMP57]], [[TMP55]] +; CHECK-NEXT: [[TMP57:%.*]] = ashr i129 [[TMP110]], 128 +; CHECK-NEXT: [[TMP58:%.*]] = xor i129 [[TMP57]], [[TMP110]] ; CHECK-NEXT: [[TMP59:%.*]] = sub i129 [[TMP58]], [[TMP57]] -; CHECK-NEXT: [[TMP60:%.*]] = call i129 @llvm.ctlz.i129(i129 [[TMP55]], i1 true) +; CHECK-NEXT: [[TMP60:%.*]] = call i129 @llvm.ctlz.i129(i129 [[TMP110]], i1 true) ; CHECK-NEXT: [[TMP61:%.*]] = trunc i129 [[TMP60]] to i32 ; CHECK-NEXT: [[TMP62:%.*]] = sub i32 129, [[TMP61]] ; CHECK-NEXT: [[TMP63:%.*]] = sub i32 128, [[TMP61]] @@ -526,22 +533,22 @@ define <2 x float> @ui129tofloatv2(<2 x i129> %a) { ; CHECK-NEXT: i32 26, label [[ITOFP_SW_EPILOG:%.*]] ; CHECK-NEXT: ] ; CHECK: itofp-sw-bb: -; CHECK-NEXT: [[TMP65:%.*]] = shl i129 [[TMP55]], 1 +; CHECK-NEXT: [[TMP111:%.*]] = shl i129 [[TMP110]], 1 ; CHECK-NEXT: br label [[ITOFP_SW_EPILOG]] ; CHECK: itofp-sw-default: ; CHECK-NEXT: [[TMP66:%.*]] = sub i32 103, [[TMP61]] ; CHECK-NEXT: [[TMP67:%.*]] = zext i32 [[TMP66]] to i129 -; CHECK-NEXT: [[TMP68:%.*]] = lshr i129 [[TMP55]], [[TMP67]] +; CHECK-NEXT: [[TMP68:%.*]] = lshr i129 [[TMP110]], [[TMP67]] ; CHECK-NEXT: [[TMP69:%.*]] = add i32 [[TMP61]], 26 ; CHECK-NEXT: [[TMP70:%.*]] = zext i32 [[TMP69]] to i129 ; CHECK-NEXT: [[TMP71:%.*]] = lshr i129 -1, [[TMP70]] -; CHECK-NEXT: [[TMP72:%.*]] = and i129 [[TMP71]], [[TMP55]] +; CHECK-NEXT: [[TMP72:%.*]] = and i129 [[TMP71]], [[TMP110]] ; CHECK-NEXT: [[TMP73:%.*]] = icmp ne i129 [[TMP72]], 0 ; CHECK-NEXT: [[TMP74:%.*]] = zext i1 [[TMP73]] to i129 ; CHECK-NEXT: [[TMP75:%.*]] = or i129 [[TMP68]], [[TMP74]] ; CHECK-NEXT: br label [[ITOFP_SW_EPILOG]] ; CHECK: itofp-sw-epilog: -; CHECK-NEXT: [[TMP76:%.*]] = phi i129 [ [[TMP75]], [[ITOFP_SW_DEFAULT]] ], [ [[TMP55]], [[ITOFP_IF_THEN4]] ], [ [[TMP65]], [[ITOFP_SW_BB]] ] +; CHECK-NEXT: [[TMP76:%.*]] = phi i129 [ [[TMP75]], [[ITOFP_SW_DEFAULT]] ], [ [[TMP110]], [[ITOFP_IF_THEN4]] ], [ [[TMP111]], [[ITOFP_SW_BB]] ] ; CHECK-NEXT: [[TMP77:%.*]] = trunc i129 [[TMP76]] to i32 ; CHECK-NEXT: [[TMP78:%.*]] = lshr i32 [[TMP77]], 2 ; CHECK-NEXT: [[TMP79:%.*]] = and i32 [[TMP78]], 1 @@ -564,7 +571,7 @@ define <2 x float> @ui129tofloatv2(<2 x i129> %a) { ; CHECK: itofp-if-else: ; CHECK-NEXT: [[TMP92:%.*]] = add i32 [[TMP61]], -105 ; CHECK-NEXT: [[TMP93:%.*]] = zext i32 [[TMP92]] to i129 -; CHECK-NEXT: [[TMP94:%.*]] = shl i129 [[TMP55]], [[TMP93]] +; CHECK-NEXT: [[TMP94:%.*]] = shl i129 [[TMP110]], [[TMP93]] ; CHECK-NEXT: [[TMP95:%.*]] = trunc i129 [[TMP94]] to i32 ; CHECK-NEXT: [[TMP96:%.*]] = lshr i129 [[TMP94]], 32 ; CHECK-NEXT: [[TMP97:%.*]] = trunc i129 [[TMP96]] to i32 diff --git a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-optnone.ll b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-optnone.ll index 5b622c1ad77eb..a0e00be2a94ff 100644 --- a/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-optnone.ll +++ b/llvm/test/Transforms/ExpandIRInsts/X86/expand-large-fp-optnone.ll @@ -9,11 +9,12 @@ define double @main(i224 %0) #0 { ; CHECK-LABEL: define double @main( ; CHECK-SAME: i224 [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[ENTRYITOFP_ENTRY:.*]]: -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i224 [[TMP0]], 0 +; CHECK-NEXT: [[TMP59:%.*]] = freeze i224 [[TMP0]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i224 [[TMP59]], 0 ; CHECK-NEXT: br i1 [[TMP1]], label %[[ITOFP_RETURN:.*]], label %[[ITOFP_IF_END:.*]] ; CHECK: [[ITOFP_IF_END]]: -; CHECK-NEXT: [[TMP2:%.*]] = ashr i224 [[TMP0]], 223 -; CHECK-NEXT: [[TMP3:%.*]] = xor i224 [[TMP2]], [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = ashr i224 [[TMP59]], 223 +; CHECK-NEXT: [[TMP3:%.*]] = xor i224 [[TMP2]], [[TMP59]] ; CHECK-NEXT: [[TMP4:%.*]] = sub i224 [[TMP3]], [[TMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = call i224 @llvm.ctlz.i224(i224 [[TMP4]], i1 true) ; CHECK-NEXT: [[TMP6:%.*]] = trunc i224 [[TMP5]] to i32 diff --git a/llvm/test/Transforms/FunctionImport/Inputs/funcimport-debug-retained-nodes.ll b/llvm/test/Transforms/FunctionImport/Inputs/funcimport-debug-retained-nodes.ll new file mode 100644 index 0000000000000..6e3a9c710e93b --- /dev/null +++ b/llvm/test/Transforms/FunctionImport/Inputs/funcimport-debug-retained-nodes.ll @@ -0,0 +1,32 @@ +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @func() { +entry: + ret void, !dbg !8 +} + +define i32 @foo() !dbg !13 { +entry: + ret i32 0, !dbg !14 +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "funcimport_debug2.c", directory: ".") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = distinct !DISubprogram(name: "func", scope: !1, file: !1, line: 2, type: !6, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2) +!6 = !DISubroutineType(types: !7) +!7 = !{null} +!8 = !DILocation(line: 2, column: 1, scope: !9, inlinedAt: !12) +!9 = distinct !DISubprogram(name: "inlined_out_clone", scope: !1, file: !1, line: 20, type: !6, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !10) +!10 = !{!11} +!11 = !DICompositeType(tag: DW_TAG_class_type, scope: !9, file: !1, line: 210, size: 8, flags: DIFlagTypePassByValue, elements: !2, identifier: "local_type") +!12 = !DILocation(line: 11, scope: !5) +!13 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2) +!14 = !DILocation(line: 3, column: 1, scope: !9, inlinedAt: !15) +!15 = !DILocation(line: 3, column: 1, scope: !13) diff --git a/llvm/test/Transforms/FunctionImport/funcimport-debug-retained-nodes.ll b/llvm/test/Transforms/FunctionImport/funcimport-debug-retained-nodes.ll new file mode 100644 index 0000000000000..3908c22d42ab7 --- /dev/null +++ b/llvm/test/Transforms/FunctionImport/funcimport-debug-retained-nodes.ll @@ -0,0 +1,118 @@ +; REQUIRES: asserts,x86-registered-target +; RUN: opt --bitcode-mdindex-threshold=0 -module-summary %s -o %t.bc +; RUN: opt --bitcode-mdindex-threshold=0 -module-summary %p/Inputs/funcimport-debug-retained-nodes.ll -o %t2.bc + +; RUN: llvm-lto2 run %t2.bc %t.bc --save-temps -o %t3 \ +; RUN: -r=%t.bc,main,px -r=%t.bc,func,px -r=%t2.bc,func,x -r=%t2.bc,foo,rx \ +; RUN: --debug-only=bitcode-reader --thinlto-threads=1 2>&1 \ +; RUN: | FileCheck --allow-empty --check-prefix=LTO %s \ +; RUN: --implicit-check-not='ignoring invalid debug info' \ +; RUN: --implicit-check-not='warning' + +; RUN: llvm-dis %t3.2.3.import.bc -o - | FileCheck %s \ +; RUN: --implicit-check-not='DISubprogram(name: "inlined_out_clone"' \ +; RUN: --implicit-check-not='DICompositeType({{.*}}, identifier: "local_type"' + +; Check that retained nodes of lazy-loaded DISubprograms are cleaned up +; from incorrectly-scoped local types. + +; When DebugTypeODRUniquing feature is enabled (e.g. with ThinLTO), +; local DITypes with the same `identifier` values are uniqued in scope +; of LLVM context during metadata loading. +; DISubprograms may reference their local types via `retainedNodes` attribute. +; Thus, during ThinLTO, the final module may end up having multiple +; DISubprograms referencing the same uniqued local type. +; MetadataLoader should clean up retainedNodes lists of DISubprograms from +; such references after loading subprograms and their local types. +; This test checks that such cleanup is done when metadata nodes are loaded +; in lazy fashion without relying on cleanup performed during +; eager function-level or module-level METADATA_BLOCK loading. + +; In order to trigger lazy-loading of DISubprogram "inlined_out_clone" +; from module-level METADATA_BLOCK in %p/Inputs/funcimport-debug-retained-nodes.ll: +; 1. The emission of metadata index is forced by setting +; --bitcode-md-index-threshold. If no MD index is emitted in BC file, +; MetadataLoader loads all metadata from a module-level METADATA_BLOCK eagerly. +; 2. The DISubprogram is referenced by locations inlined in two different +; IR functions, thus, it is emitted in module-level METADATA_BLOCK. +; 3. The DISubprogram is not referenced by any local variable of a function, +; so that it is not loaded eagerly when reading function-level METADATA_BLOCK. +; Otherwise, cleanup would be performed on it during function-level +; METADATA_BLOCK loading. +; 4. No other METADATA_BLOCK should be loaded after lazy-loading the target +; DISubprogram, to avoid cleanup being performed later. We want to observe +; the behavior of MetadataLoader when loading the target DISubprogram lazily +; without interference from metadata blocks loaded later. Therefore, @foo from +; %p/Inputs/funcimport-debug-retained-nodes.ll, that follows @func referencing +; the target DISubprogram, is marked as dso_preemptable => unsafe for LTO +; function import. + +; This test should pass if, after ThinLTO function import, the final module +; contains two DISubprograms "inlined_out_clone", and none of them reference +; the local type that doesn't belong to them via `retainedNodes`. +; It should fail if `retainedNodes` field of DISubprogram "inlined_out_clone" +; loaded from %p/Inputs/funcimport-debug-retained-nodes.ll references +; DICompositeType from the scope of DISubprogram "inlined_out_clone" from +; %p/funcimport-debug-retained-nodes.ll (the type that is uniqued +; due to DebugTypeODRUniquing on). + +; Check that lazy loading codepath is triggered, the subprogram is cleaned up, +; and MetadataLoaderImpl::resolveLoadedMetadata() is not called after that. +; LTO: Lazy metadata loading: Resolved loaded metadata. Cleaned up 1 subprogram(s). +; LTO-NOT: Resolved loaded metadata + +; The module %p/funcimport-debug-retained-nodes.ll contains: +; - DICompositeType "local_type", and +; - DISubprogram "inlined_out_clone" with empty retainedNodes list. +; The module %p/Inputs/funcimport-debug-retained-nodes.ll contains: +; - DICompositeType "local_type", and +; - DISubprogram "inlined_out_clone" with "local_type" in its retainedNodes. +; After function import into module %p/funcimport-debug-retained-nodes.ll, +; the output module contains: +; - a single DICompositeType "local_type" that comes from %p/funcimport-debug-retained-nodes.ll +; (due to ODR-uniquing, "local_type" from %p/Inputs/funcimport-debug-retained-nodes.ll +; is not imported during function import), +; - DISubprogram "inlined_out_clone" from %p/funcimport-debug-retained-nodes.ll +; with empty retainedNodes list, and +; - DISubprogram "inlined_out_clone" from %p/Inputs/funcimport-debug-retained-nodes.ll. +; This test expects its retaiendNodes to be empty, cleaned up from reference +; to "local_type" from %p/funcimport-debug-retained-nodes.ll (that, without proper +; cleanup, would occur because of ODR-uniquing). The following check lines ensure that. + +; CHECK: ![[ORIGINAL_FILE:[0-9]+]] = !DIFile(filename: "funcimport_debug.c", +; CHECK: ![[EMPTY:[0-9]+]] = !{} +; CHECK: ![[IMPORTED_FILE:[0-9]+]] = !DIFile(filename: "funcimport_debug2.c", +; CHECK: ![[ORIGINAL_SP:[0-9]+]] = distinct !DISubprogram(name: "inlined_out_clone", {{.*}}, file: ![[ORIGINAL_FILE]], {{.*}}, retainedNodes: ![[EMPTY]] +; CHECK: !DICompositeType(tag: DW_TAG_class_type, scope: ![[ORIGINAL_SP]], {{.*}}, identifier: "local_type" +; CHECK: !DISubprogram(name: "inlined_out_clone", {{.*}}, file: ![[IMPORTED_FILE]], {{.*}}, retainedNodes: ![[EMPTY]] + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @main() !dbg !5 { +entry: + %a = alloca i8, align 4 + #dbg_declare(ptr %a, !9, !DIExpression(), !12) + call void (...) @func() + ret i32 0 +} + +declare void @func(...) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "funcimport_debug.c", directory: ".") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 2, type: !6, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2) +!6 = !DISubroutineType(types: !7) +!7 = !{!8} +!8 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!9 = !DILocalVariable(name: "foo_ptr", scope: !10, file: !1, line: 4, type: !11) +!10 = distinct !DISubprogram(name: "inlined_out_clone", scope: !1, file: !1, line: 20, type: !6, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2) +!11 = !DICompositeType(tag: DW_TAG_class_type, scope: !10, file: !1, line: 210, size: 8, flags: DIFlagTypePassByValue, elements: !2, identifier: "local_type") +!12 = !DILocation(line: 3, column: 1, scope: !10, inlinedAt: !13) +!13 = !DILocation(line: 3, column: 3, scope: !5) diff --git a/llvm/test/Transforms/IROutliner/outlining-compatible-and-attribute-transfer.ll b/llvm/test/Transforms/IROutliner/outlining-compatible-and-attribute-transfer.ll index 15ce3e3c440fe..68a640ef8d3df 100644 --- a/llvm/test/Transforms/IROutliner/outlining-compatible-and-attribute-transfer.ll +++ b/llvm/test/Transforms/IROutliner/outlining-compatible-and-attribute-transfer.ll @@ -100,8 +100,7 @@ entry: ret void } -attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "less-precise-fpmad"="true" -"no-infs-fp-math"="true"} +attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "less-precise-fpmad"="true" } ; CHECK: define internal void @outlined_ir_func_0(ptr [[ARG0:%.*]], ptr [[ARG1:%.*]], ptr [[ARG2:%.*]]) [[ATTR1:#[0-9]+]] { ; CHECK: entry_to_outline: @@ -122,5 +121,5 @@ attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "les ; CHECK-NEXT: [[CL:%.*]] = load i32, ptr [[ARG2]], align 4 -; CHECK: attributes [[ATTR1]] = { minsize optsize "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" } -; CHECK: attributes [[ATTR]] = { minsize optsize "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } +; CHECK: attributes [[ATTR1]] = { minsize optsize "less-precise-fpmad"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" } +; CHECK: attributes [[ATTR]] = { minsize optsize "less-precise-fpmad"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } diff --git a/llvm/test/Transforms/IndVarSimplify/addrec_no_exec_on_every_iteration.ll b/llvm/test/Transforms/IndVarSimplify/addrec_no_exec_on_every_iteration.ll index 9524fcd998aff..d8bf1567d00ed 100644 --- a/llvm/test/Transforms/IndVarSimplify/addrec_no_exec_on_every_iteration.ll +++ b/llvm/test/Transforms/IndVarSimplify/addrec_no_exec_on_every_iteration.ll @@ -334,7 +334,7 @@ bb201: ; preds = %bb194 ret void } -attributes #0 = { nofree norecurse nounwind uwtable "denormal-fp-math"="preserve-sign" "no-frame-pointer-elim"="false" } +attributes #0 = { nofree norecurse nounwind uwtable denormal_fpenv(preservesign) "no-frame-pointer-elim"="false" } !0 = !{} !1 = !{i64 800} diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/global-atomicrmw-fadd.ll index 1bb4f0ede1f09..fd698196ffb77 100644 --- a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/global-atomicrmw-fadd.ll +++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/global-atomicrmw-fadd.ll @@ -14,7 +14,7 @@ define amdgpu_kernel void @infer_as_before_atomic(ptr addrspace(4) %arg) #0 { ret void } -attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(float: preservesign) } !0 = !{} diff --git a/llvm/test/Transforms/InferAddressSpaces/NVPTX/nullptr.ll b/llvm/test/Transforms/InferAddressSpaces/NVPTX/nullptr.ll new file mode 100644 index 0000000000000..4d029cef383b8 --- /dev/null +++ b/llvm/test/Transforms/InferAddressSpaces/NVPTX/nullptr.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -S -passes=infer-address-spaces %s | FileCheck %s + +target triple = "nvptx64--" + +define ptr @pr171890(i1 %c) { +; CHECK-LABEL: define ptr @pr171890( +; CHECK-SAME: i1 [[C:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[STACK:%.*]] = alloca i16, align 2 +; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[STACK]] to ptr addrspace(5) +; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(5) [[TMP0]] to ptr +; CHECK-NEXT: [[CONST:%.*]] = getelementptr i8, ptr null, i64 1 +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], ptr [[TMP1]], ptr [[CONST]] +; CHECK-NEXT: ret ptr [[SEL]] +; +entry: + %stack = alloca i16, align 2 + %const = getelementptr i8, ptr null, i64 1 + %sel = select i1 %c, ptr %stack, ptr %const + ret ptr %sel +} diff --git a/llvm/test/Transforms/Inline/2007-04-15-InlineEH.ll b/llvm/test/Transforms/Inline/2007-04-15-InlineEH.ll index bc5fe13e7f1d6..a891098c44d7d 100644 --- a/llvm/test/Transforms/Inline/2007-04-15-InlineEH.ll +++ b/llvm/test/Transforms/Inline/2007-04-15-InlineEH.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; PR1335 target triple = "i686-pc-linux-gnu" diff --git a/llvm/test/Transforms/Inline/2007-06-25-WeakInline.ll b/llvm/test/Transforms/Inline/2007-06-25-WeakInline.ll index a1519db7e445e..952f8b7b1b0dd 100644 --- a/llvm/test/Transforms/Inline/2007-06-25-WeakInline.ll +++ b/llvm/test/Transforms/Inline/2007-06-25-WeakInline.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; 'bar' can be overridden at link-time, don't inline it. define weak void @bar() { diff --git a/llvm/test/Transforms/Inline/2007-12-19-InlineNoUnwind.ll b/llvm/test/Transforms/Inline/2007-12-19-InlineNoUnwind.ll index 70ff6e744b5e3..b03c4ed21d68a 100644 --- a/llvm/test/Transforms/Inline/2007-12-19-InlineNoUnwind.ll +++ b/llvm/test/Transforms/Inline/2007-12-19-InlineNoUnwind.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s declare i1 @extern() diff --git a/llvm/test/Transforms/Inline/2008-09-02-NoInline.ll b/llvm/test/Transforms/Inline/2008-09-02-NoInline.ll index c34e9a530fe5e..e6c068a845cd5 100644 --- a/llvm/test/Transforms/Inline/2008-09-02-NoInline.ll +++ b/llvm/test/Transforms/Inline/2008-09-02-NoInline.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s define i32 @fn2() noinline { ; CHECK-LABEL: define i32 @fn2() diff --git a/llvm/test/Transforms/Inline/2009-01-08-NoInlineDynamicAlloca.ll b/llvm/test/Transforms/Inline/2009-01-08-NoInlineDynamicAlloca.ll index 12e1f112573f4..b418912a93044 100644 --- a/llvm/test/Transforms/Inline/2009-01-08-NoInlineDynamicAlloca.ll +++ b/llvm/test/Transforms/Inline/2009-01-08-NoInlineDynamicAlloca.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; Do not inline calls with variable-sized alloca. @q = common global ptr null diff --git a/llvm/test/Transforms/Inline/AArch64/inline-target-attr.ll b/llvm/test/Transforms/Inline/AArch64/inline-target-attr.ll index 433a9c7bdd23b..355efbb61eae8 100644 --- a/llvm/test/Transforms/Inline/AArch64/inline-target-attr.ll +++ b/llvm/test/Transforms/Inline/AArch64/inline-target-attr.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -mtriple=aarch64-unknown-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=aarch64-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s ; Check that we only inline when we have compatible target attributes. define i32 @foo() #0 { diff --git a/llvm/test/Transforms/Inline/AArch64/switch.ll b/llvm/test/Transforms/Inline/AArch64/switch.ll index 682f5ecc0bc08..bcb67c8114b4d 100644 --- a/llvm/test/Transforms/Inline/AArch64/switch.ll +++ b/llvm/test/Transforms/Inline/AArch64/switch.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -inline-threshold=20 -S -mtriple=aarch64-none-linux | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=20 -S -mtriple=aarch64-none-linux | FileCheck %s define i32 @callee_range(i32 %a, ptr %P) { switch i32 %a, label %sw.default [ diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll index 88fc2a32afd8f..a6b481ea94b75 100644 --- a/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll +++ b/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll @@ -1,5 +1,4 @@ ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=inline < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes='cgscc(inline)' < %s | FileCheck %s define i32 @func_default() #0 { ret i32 0 diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll index 64ab45d55c69d..45b17b012fcb8 100644 --- a/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll +++ b/llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll @@ -1,5 +1,4 @@ ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=inline < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes='cgscc(inline)' < %s | FileCheck %s define i32 @func_default() #0 { ret i32 0 diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-atomicrmw-md-preserve.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-atomicrmw-md-preserve.ll index 569cc91a867c3..6cf09118ba429 100644 --- a/llvm/test/Transforms/Inline/AMDGPU/inline-atomicrmw-md-preserve.ll +++ b/llvm/test/Transforms/Inline/AMDGPU/inline-atomicrmw-md-preserve.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=inline < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes='cgscc(inline)' < %s | FileCheck %s ; Ensure that custom metadata survives inlining diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-denormal-fp-math.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-denormal-fp-math.ll index e58f09e5edc34..28ecfea397aea 100644 --- a/llvm/test/Transforms/Inline/AMDGPU/inline-denormal-fp-math.ll +++ b/llvm/test/Transforms/Inline/AMDGPU/inline-denormal-fp-math.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=inline < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes='cgscc(inline)' < %s | FileCheck %s define i32 @func_default() { ; CHECK-LABEL: @func_default( @@ -861,16 +860,16 @@ define i32 @call_dynamic_dynamic_psz_psz_f32_from_psz_psz() #1 { ret i32 %result } -attributes #0 = { "denormal-fp-math"="ieee,ieee" } -attributes #1 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #2 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #3 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #4 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #5 = { "denormal-fp-math"="dynamic,ieee" } -attributes #6 = { "denormal-fp-math"="ieee,dynamic" } -attributes #7 = { "denormal-fp-math"="preserve-sign,dynamic" } -attributes #8 = { "denormal-fp-math"="dynamic,preserve-sign" } -attributes #9 = { "denormal-fp-math-f32"="dynamic,dynamic" } -attributes #10 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } -attributes #11 = { "denormal-fp-math-f32"="ieee,ieee" "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #12 = { "denormal-fp-math"="dynamic,dynamic" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(ieee|ieee) } +attributes #1 = { denormal_fpenv(preservesign) } +attributes #2 = { denormal_fpenv(preservesign|ieee) } +attributes #3 = { denormal_fpenv(ieee|preservesign) } +attributes #4 = { denormal_fpenv(dynamic) } +attributes #5 = { denormal_fpenv(dynamic|ieee) } +attributes #6 = { denormal_fpenv(ieee|dynamic) } +attributes #7 = { denormal_fpenv(preservesign|dynamic) } +attributes #8 = { denormal_fpenv(dynamic|preservesign) } +attributes #9 = { denormal_fpenv(float: dynamic) } +attributes #10 = { denormal_fpenv(float: preservesign) } +attributes #11 = { denormal_fpenv(float: ieee|ieee) denormal_fpenv(preservesign) } +attributes #12 = { denormal_fpenv(dynamic, float: preservesign) } diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-target-cpu.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-target-cpu.ll index f860b039ac119..a4c2069633cd0 100644 --- a/llvm/test/Transforms/Inline/AMDGPU/inline-target-cpu.ll +++ b/llvm/test/Transforms/Inline/AMDGPU/inline-target-cpu.ll @@ -1,5 +1,4 @@ ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=inline < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes='cgscc(inline)' < %s | FileCheck %s ; CHECK-LABEL: @func_no_target_cpu( define i32 @func_no_target_cpu() #0 { diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-sram-ecc.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-sram-ecc.ll index 825053e9f09cc..69a20d8b0077e 100644 --- a/llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-sram-ecc.ll +++ b/llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-sram-ecc.ll @@ -1,5 +1,4 @@ ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=inline < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes='cgscc(inline)' < %s | FileCheck %s ; sram-ecc can be safely ignored when inlining, since no intrinisics ; or other directly exposed operations depend on it. diff --git a/llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-xnack.ll b/llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-xnack.ll index 36fbab07ac974..99b69758c0ea8 100644 --- a/llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-xnack.ll +++ b/llvm/test/Transforms/Inline/AMDGPU/inline-target-feature-xnack.ll @@ -1,5 +1,4 @@ ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=inline < %s | FileCheck %s -; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes='cgscc(inline)' < %s | FileCheck %s define i32 @func_default() #0 { ret i32 0 diff --git a/llvm/test/Transforms/Inline/ARM/inline-dotprod.ll b/llvm/test/Transforms/Inline/ARM/inline-dotprod.ll index 2f8dbb7f01822..b94e4df8baf83 100644 --- a/llvm/test/Transforms/Inline/ARM/inline-dotprod.ll +++ b/llvm/test/Transforms/Inline/ARM/inline-dotprod.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -mtriple=arm-unknown-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=arm-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s declare i32 @foo(...) #0 diff --git a/llvm/test/Transforms/Inline/ARM/inline-target-attr.ll b/llvm/test/Transforms/Inline/ARM/inline-target-attr.ll index 444b736fa03f5..2d6408e30fd2f 100644 --- a/llvm/test/Transforms/Inline/ARM/inline-target-attr.ll +++ b/llvm/test/Transforms/Inline/ARM/inline-target-attr.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -mtriple=arm-unknown-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=arm-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s ; Check that we only inline when we have compatible target attributes. ; ARM has implemented a target attribute that will verify that the attribute ; sets are compatible. diff --git a/llvm/test/Transforms/Inline/LoongArch/inline-target-features.ll b/llvm/test/Transforms/Inline/LoongArch/inline-target-features.ll index f7a37015e07fc..5853894282c76 100644 --- a/llvm/test/Transforms/Inline/LoongArch/inline-target-features.ll +++ b/llvm/test/Transforms/Inline/LoongArch/inline-target-features.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -mtriple=loongarch64-unknown-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=loongarch64-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s ; Check that we only inline when we have compatible target attributes. target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll index b7086199e6f7d..5cdf36a09be1c 100644 --- a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll +++ b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -mtriple=powerpc64le-ibm-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=powerpc64le-ibm-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64le-ibm-linux-gnu" diff --git a/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll b/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll index b626a229a737d..deda6ad7c85ce 100644 --- a/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll +++ b/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -mtriple=riscv64-unknown-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=riscv64-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s ; Check that we only inline when we have compatible target attributes. target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" diff --git a/llvm/test/Transforms/Inline/SystemZ/inline-target-attr.ll b/llvm/test/Transforms/Inline/SystemZ/inline-target-attr.ll index 71b463b2d2b00..e0ca419fc5754 100644 --- a/llvm/test/Transforms/Inline/SystemZ/inline-target-attr.ll +++ b/llvm/test/Transforms/Inline/SystemZ/inline-target-attr.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -mtriple=s390x-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=s390x-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s ; Check that we only inline when we have equal target attributes. define i32 @foo() #0 { diff --git a/llvm/test/Transforms/Inline/X86/extractvalue.ll b/llvm/test/Transforms/Inline/X86/extractvalue.ll index ccd58c8701281..7c0f8d7b90cb5 100644 --- a/llvm/test/Transforms/Inline/X86/extractvalue.ll +++ b/llvm/test/Transforms/Inline/X86/extractvalue.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -inline-threshold=0 -debug-only=inline-cost -print-instruction-comments -S -mtriple=x86_64-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=0 -debug-only=inline-cost -print-instruction-comments -S -mtriple=x86_64-unknown-linux-gnu 2>&1 | FileCheck %s ; REQUIRES: asserts target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Inline/X86/inline-target-attr.ll b/llvm/test/Transforms/Inline/X86/inline-target-attr.ll index 528e8a5cb2e60..3b4b945bdf036 100644 --- a/llvm/test/Transforms/Inline/X86/inline-target-attr.ll +++ b/llvm/test/Transforms/Inline/X86/inline-target-attr.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s ; Check that we only inline when we have compatible target attributes. ; X86 has implemented a target attribute that will verify that the attribute ; sets are compatible. diff --git a/llvm/test/Transforms/Inline/X86/insertvalue.ll b/llvm/test/Transforms/Inline/X86/insertvalue.ll index 529f9475678c3..aa85817cdfbdc 100644 --- a/llvm/test/Transforms/Inline/X86/insertvalue.ll +++ b/llvm/test/Transforms/Inline/X86/insertvalue.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -inline-threshold=0 -debug-only=inline-cost -print-instruction-comments -S -mtriple=x86_64-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=0 -debug-only=inline-cost -print-instruction-comments -S -mtriple=x86_64-unknown-linux-gnu 2>&1 | FileCheck %s ; REQUIRES: asserts target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Inline/X86/switch.ll b/llvm/test/Transforms/Inline/X86/switch.ll index 99c7b25928b22..b4cc95b4822f9 100644 --- a/llvm/test/Transforms/Inline/X86/switch.ll +++ b/llvm/test/Transforms/Inline/X86/switch.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -inline-threshold=1 -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=1 -S -mtriple=x86_64-unknown-linux-gnu | FileCheck %s define i32 @callee_range(i32 %a, ptr %P) { switch i32 %a, label %sw.default [ diff --git a/llvm/test/Transforms/Inline/access-attributes-prop.ll b/llvm/test/Transforms/Inline/access-attributes-prop.ll index fed2590d36669..a5c52ecdfd8c2 100644 --- a/llvm/test/Transforms/Inline/access-attributes-prop.ll +++ b/llvm/test/Transforms/Inline/access-attributes-prop.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes ; RUN: opt -S -passes=inline %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' %s | FileCheck %s ; RUN: opt -S -passes='module-inline' %s | FileCheck %s declare void @bar1(ptr %p) diff --git a/llvm/test/Transforms/Inline/alloca-bonus.ll b/llvm/test/Transforms/Inline/alloca-bonus.ll index 45ff5273bbe23..4cc9dee6c268c 100644 --- a/llvm/test/Transforms/Inline/alloca-bonus.ll +++ b/llvm/test/Transforms/Inline/alloca-bonus.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline < %s -S -o - -inline-threshold=8 | FileCheck %s -; RUN: opt -passes='cgscc(inline)' < %s -S -o - -inline-threshold=8 | FileCheck %s target datalayout = "p:32:32" diff --git a/llvm/test/Transforms/Inline/alloca-dbgdeclare.ll b/llvm/test/Transforms/Inline/alloca-dbgdeclare.ll index e34cb1a9dc5ea..65458f6443a80 100644 --- a/llvm/test/Transforms/Inline/alloca-dbgdeclare.ll +++ b/llvm/test/Transforms/Inline/alloca-dbgdeclare.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s ; struct A { ; int arg0; diff --git a/llvm/test/Transforms/Inline/alloca_test.ll b/llvm/test/Transforms/Inline/alloca_test.ll index e4a90799fa326..85c539909ea20 100644 --- a/llvm/test/Transforms/Inline/alloca_test.ll +++ b/llvm/test/Transforms/Inline/alloca_test.ll @@ -3,7 +3,6 @@ ; function are moved to the top of the function they are inlined into. ; ; RUN: opt -S -passes=inline < %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' < %s | FileCheck %s define i32 @func(i32 %i) { %X = alloca i32 diff --git a/llvm/test/Transforms/Inline/array-alloca.ll b/llvm/test/Transforms/Inline/array-alloca.ll index 8abcde0dea7ff..2e3baf9ffa43b 100644 --- a/llvm/test/Transforms/Inline/array-alloca.ll +++ b/llvm/test/Transforms/Inline/array-alloca.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s %struct.A = type { i32 } define void @callee1(i32 %M) { diff --git a/llvm/test/Transforms/Inline/assumptions-from-callsite-attrs.ll b/llvm/test/Transforms/Inline/assumptions-from-callsite-attrs.ll index c0943f4aefb8f..e8a64da786c64 100644 --- a/llvm/test/Transforms/Inline/assumptions-from-callsite-attrs.ll +++ b/llvm/test/Transforms/Inline/assumptions-from-callsite-attrs.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; RUN: opt -S -passes=inline %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' %s | FileCheck %s ; RUN: opt -S -passes='module-inline' %s | FileCheck %s declare void @h(ptr %p, ptr %q, ptr %z) diff --git a/llvm/test/Transforms/Inline/attributes.ll b/llvm/test/Transforms/Inline/attributes.ll index da7eeda543c79..762e3bc9a34a4 100644 --- a/llvm/test/Transforms/Inline/attributes.ll +++ b/llvm/test/Transforms/Inline/attributes.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" define i32 @noattr_callee(i32 %i) { @@ -481,46 +480,6 @@ define i32 @test_null-pointer-is-valid2(i32 %i) null_pointer_is_valid { ; CHECK-NEXT: ret i32 } -define i32 @no-infs-fp-math_callee0(i32 %i) "no-infs-fp-math"="false" { - ret i32 %i -; CHECK: @no-infs-fp-math_callee0(i32 %i) [[NO_INFS_FPMATH_FALSE:#[0-9]+]] { -; CHECK-NEXT: ret i32 -} - -define i32 @no-infs-fp-math_callee1(i32 %i) "no-infs-fp-math"="true" { - ret i32 %i -; CHECK: @no-infs-fp-math_callee1(i32 %i) [[NO_INFS_FPMATH_TRUE:#[0-9]+]] { -; CHECK-NEXT: ret i32 -} - -define i32 @test_no-infs-fp-math0(i32 %i) "no-infs-fp-math"="false" { - %1 = call i32 @no-infs-fp-math_callee0(i32 %i) - ret i32 %1 -; CHECK: @test_no-infs-fp-math0(i32 %i) [[NO_INFS_FPMATH_FALSE]] { -; CHECK-NEXT: ret i32 -} - -define i32 @test_no-infs-fp-math1(i32 %i) "no-infs-fp-math"="false" { - %1 = call i32 @no-infs-fp-math_callee1(i32 %i) - ret i32 %1 -; CHECK: @test_no-infs-fp-math1(i32 %i) [[NO_INFS_FPMATH_FALSE]] { -; CHECK-NEXT: ret i32 -} - -define i32 @test_no-infs-fp-math2(i32 %i) "no-infs-fp-math"="true" { - %1 = call i32 @no-infs-fp-math_callee0(i32 %i) - ret i32 %1 -; CHECK: @test_no-infs-fp-math2(i32 %i) [[NO_INFS_FPMATH_FALSE]] { -; CHECK-NEXT: ret i32 -} - -define i32 @test_no-infs-fp-math3(i32 %i) "no-infs-fp-math"="true" { - %1 = call i32 @no-infs-fp-math_callee1(i32 %i) - ret i32 %1 -; CHECK: @test_no-infs-fp-math3(i32 %i) [[NO_INFS_FPMATH_TRUE]] { -; CHECK-NEXT: ret i32 -} - define i32 @no-nans-fp-math_callee0(i32 %i) "no-nans-fp-math"="false" { ret i32 %i ; CHECK: @no-nans-fp-math_callee0(i32 %i) [[NO_NANS_FPMATH_FALSE:#[0-9]+]] { @@ -647,8 +606,6 @@ define i32 @loader_replaceable_caller() { ; CHECK: attributes [[NOIMPLICITFLOAT]] = { noimplicitfloat } ; CHECK: attributes [[NOUSEJUMPTABLES]] = { "no-jump-tables"="true" } ; CHECK: attributes [[NULLPOINTERISVALID]] = { null_pointer_is_valid } -; CHECK: attributes [[NO_INFS_FPMATH_FALSE]] = { "no-infs-fp-math"="false" } -; CHECK: attributes [[NO_INFS_FPMATH_TRUE]] = { "no-infs-fp-math"="true" } ; CHECK: attributes [[NO_NANS_FPMATH_FALSE]] = { "no-nans-fp-math"="false" } ; CHECK: attributes [[NO_NANS_FPMATH_TRUE]] = { "no-nans-fp-math"="true" } ; CHECK: attributes [[NO_SIGNED_ZEROS_FPMATH_FALSE]] = { "no-signed-zeros-fp-math"="false" } diff --git a/llvm/test/Transforms/Inline/blockaddress.ll b/llvm/test/Transforms/Inline/blockaddress.ll index aded280c1ed6c..8a3861ac74928 100644 --- a/llvm/test/Transforms/Inline/blockaddress.ll +++ b/llvm/test/Transforms/Inline/blockaddress.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s ; PR10162 ; Make sure doit is not inlined since the blockaddress is taken diff --git a/llvm/test/Transforms/Inline/byval.ll b/llvm/test/Transforms/Inline/byval.ll index c945d7fe1a01a..d435ddfa73fd0 100644 --- a/llvm/test/Transforms/Inline/byval.ll +++ b/llvm/test/Transforms/Inline/byval.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; The verifier does catch problems with inlining of byval arguments that has a ; different address space compared to the alloca. But running instcombine diff --git a/llvm/test/Transforms/Inline/byval_lifetime.ll b/llvm/test/Transforms/Inline/byval_lifetime.ll index 9f68cd49c4b4c..b29d6a6a4adce 100644 --- a/llvm/test/Transforms/Inline/byval_lifetime.ll +++ b/llvm/test/Transforms/Inline/byval_lifetime.ll @@ -1,5 +1,4 @@ ; RUN: opt -S -passes=inline < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s ; By inlining foo, an alloca is created in main to hold the byval argument, so ; a lifetime marker should be generated as well by default. diff --git a/llvm/test/Transforms/Inline/call-site-attrs.ll b/llvm/test/Transforms/Inline/call-site-attrs.ll index 19b062e2b770d..fec052b1a5d84 100644 --- a/llvm/test/Transforms/Inline/call-site-attrs.ll +++ b/llvm/test/Transforms/Inline/call-site-attrs.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; Always prefer call site attribute over function attribute diff --git a/llvm/test/Transforms/Inline/callbr.ll b/llvm/test/Transforms/Inline/callbr.ll index 57e92bb2a6774..996618381ba68 100644 --- a/llvm/test/Transforms/Inline/callbr.ll +++ b/llvm/test/Transforms/Inline/callbr.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s ; RUN: opt -passes='module-inline' -S < %s | FileCheck %s define dso_local i32 @main() { diff --git a/llvm/test/Transforms/Inline/casts.ll b/llvm/test/Transforms/Inline/casts.ll index b4e015040ca41..2f07c4125bc19 100644 --- a/llvm/test/Transforms/Inline/casts.ll +++ b/llvm/test/Transforms/Inline/casts.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; RUN: opt < %s -passes='module-inline' -S | FileCheck %s define i32 @testByte(i8 %X) { diff --git a/llvm/test/Transforms/Inline/comdat-ipo.ll b/llvm/test/Transforms/Inline/comdat-ipo.ll index 0551068bb9b93..a3c4210e430e3 100644 --- a/llvm/test/Transforms/Inline/comdat-ipo.ll +++ b/llvm/test/Transforms/Inline/comdat-ipo.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s ; RUN: opt -passes='module-inline' -S < %s | FileCheck %s define i32 @caller() { diff --git a/llvm/test/Transforms/Inline/crash-lifetime-marker.ll b/llvm/test/Transforms/Inline/crash-lifetime-marker.ll index 1c79b10d413bd..27450046cfa58 100644 --- a/llvm/test/Transforms/Inline/crash-lifetime-marker.ll +++ b/llvm/test/Transforms/Inline/crash-lifetime-marker.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; RUN: opt < %s -passes='module-inline' -S | FileCheck %s ; InlineFunction would assert inside the loop that leaves lifetime markers if diff --git a/llvm/test/Transforms/Inline/frameescape.ll b/llvm/test/Transforms/Inline/frameescape.ll index 8566a7524c38d..fd5f7a0127764 100644 --- a/llvm/test/Transforms/Inline/frameescape.ll +++ b/llvm/test/Transforms/Inline/frameescape.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s ; RUN: opt -passes='module-inline' -S < %s | FileCheck %s ; PR23216: We can't inline functions using llvm.localescape. diff --git a/llvm/test/Transforms/Inline/ignore-debug-info.ll b/llvm/test/Transforms/Inline/ignore-debug-info.ll index 7ccf7e86bac2a..2187520a475da 100644 --- a/llvm/test/Transforms/Inline/ignore-debug-info.ll +++ b/llvm/test/Transforms/Inline/ignore-debug-info.ll @@ -1,7 +1,5 @@ ; RUN: opt < %s -S -passes=inline -inline-threshold=2 | FileCheck %s ; RUN: opt < %s -S -strip-debug -passes=inline -inline-threshold=2 | FileCheck %s -; RUN: opt < %s -S -passes='cgscc(inline)' -inline-threshold=2 | FileCheck %s -; RUN: opt < %s -S -strip-debug -passes='cgscc(inline)' -inline-threshold=2 | FileCheck %s ; ; The purpose of this test is to check that debug info doesn't influence ; inlining decisions. diff --git a/llvm/test/Transforms/Inline/inline-assume.ll b/llvm/test/Transforms/Inline/inline-assume.ll index b1e3e72a37034..5ade25ec00329 100644 --- a/llvm/test/Transforms/Inline/inline-assume.ll +++ b/llvm/test/Transforms/Inline/inline-assume.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S -o - < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s ; RUN: opt -passes='module-inline' -S < %s | FileCheck %s %0 = type opaque diff --git a/llvm/test/Transforms/Inline/inline-byval-bonus.ll b/llvm/test/Transforms/Inline/inline-byval-bonus.ll index 1418fff9395e2..ff1e682ff921f 100644 --- a/llvm/test/Transforms/Inline/inline-byval-bonus.ll +++ b/llvm/test/Transforms/Inline/inline-byval-bonus.ll @@ -1,5 +1,4 @@ ; RUN: opt -S -passes=inline -inline-threshold=275 < %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' -inline-threshold=275 < %s | FileCheck %s ; PR13095 ; The performance of the c-ray benchmark largely depends on the inlining of a diff --git a/llvm/test/Transforms/Inline/inline-call-with-asm-call.ll b/llvm/test/Transforms/Inline/inline-call-with-asm-call.ll index 7d8121d04996e..845c65ed99611 100644 --- a/llvm/test/Transforms/Inline/inline-call-with-asm-call.ll +++ b/llvm/test/Transforms/Inline/inline-call-with-asm-call.ll @@ -1,17 +1,14 @@ ;; Test to verify that when callee has inline assembly, bumping up `-inline-asm-instr-cost` would block inlining. ; RUN: opt < %s -passes=inline -S | FileCheck %s --check-prefixes=CHECK,INLINE -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s --check-prefixes=CHECK,INLINE ;; Verify that a low assembly instruction cost of 150 does not block inlining. ;; This test also verifies that the outlined section's instructions (in "other" ;; section) do not contribute to the cost. ; RUN: opt < %s -passes=inline -inline-asm-instr-cost=150 -S | FileCheck %s --check-prefixes=CHECK,INLINE -; RUN: opt < %s -passes='cgscc(inline)' -inline-asm-instr-cost=150 -S | FileCheck %s --check-prefixes=CHECK,INLINE ;; Verify that an assembly instruction cost of 300 blocks inlining. ; RUN: opt < %s -passes=inline -inline-asm-instr-cost=300 -S | FileCheck %s --check-prefixes=CHECK,NOINLINE -; RUN: opt < %s -passes='cgscc(inline)' -inline-asm-instr-cost=300 -S | FileCheck %s --check-prefixes=CHECK,NOINLINE define void @caller(i32 %a, i1 %b) #0 { call void @callee(i32 %a, i1 %b) diff --git a/llvm/test/Transforms/Inline/inline-constexpr-addrspacecast-argument.ll b/llvm/test/Transforms/Inline/inline-constexpr-addrspacecast-argument.ll index 82fb54130f625..b71e1765a71e3 100644 --- a/llvm/test/Transforms/Inline/inline-constexpr-addrspacecast-argument.ll +++ b/llvm/test/Transforms/Inline/inline-constexpr-addrspacecast-argument.ll @@ -1,5 +1,4 @@ ; RUN: opt -S -passes=inline < %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' < %s | FileCheck %s ; RUN: opt -S -passes='module-inline' < %s | FileCheck %s target datalayout = "e-p3:32:32-p4:64:64-n32" diff --git a/llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll b/llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll index 02f5774d05076..8c0cc971f64b0 100644 --- a/llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll +++ b/llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s %struct.a = type { i32, i32, i32, i32, i32 } diff --git a/llvm/test/Transforms/Inline/inline-drop-attributes.ll b/llvm/test/Transforms/Inline/inline-drop-attributes.ll index 9a451f4b8699a..8fdb043c6b8c3 100644 --- a/llvm/test/Transforms/Inline/inline-drop-attributes.ll +++ b/llvm/test/Transforms/Inline/inline-drop-attributes.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s define void @callee() { ; CHECK-LABEL: define void @callee() { diff --git a/llvm/test/Transforms/Inline/inline-fast-math-flags.ll b/llvm/test/Transforms/Inline/inline-fast-math-flags.ll index 11c4d2b934391..a742c52850e54 100644 --- a/llvm/test/Transforms/Inline/inline-fast-math-flags.ll +++ b/llvm/test/Transforms/Inline/inline-fast-math-flags.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -S -passes=inline -inline-threshold=20 | FileCheck %s -; RUN: opt < %s -S -passes='cgscc(inline)' -inline-threshold=20 | FileCheck %s ; RUN: opt < %s -S -passes='module-inline' -inline-threshold=20 | FileCheck %s ; Check that we don't drop FastMathFlag when estimating inlining profitability. ; diff --git a/llvm/test/Transforms/Inline/inline-funclets.ll b/llvm/test/Transforms/Inline/inline-funclets.ll index fb4a94e7b07f2..dcddb1d2d78ce 100644 --- a/llvm/test/Transforms/Inline/inline-funclets.ll +++ b/llvm/test/Transforms/Inline/inline-funclets.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S %s | FileCheck %s declare void @g() diff --git a/llvm/test/Transforms/Inline/inline-invoke-with-asm-call.ll b/llvm/test/Transforms/Inline/inline-invoke-with-asm-call.ll index 97f0ed11d3b32..7b7715a80b6af 100644 --- a/llvm/test/Transforms/Inline/inline-invoke-with-asm-call.ll +++ b/llvm/test/Transforms/Inline/inline-invoke-with-asm-call.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s target triple = "x86_64-apple-darwin" ; In inliner, we assume that inline asm does not throw. This testing case makes diff --git a/llvm/test/Transforms/Inline/inline-no-builtin-compatible.ll b/llvm/test/Transforms/Inline/inline-no-builtin-compatible.ll index b9c0bc98c8499..212c992ae04e4 100644 --- a/llvm/test/Transforms/Inline/inline-no-builtin-compatible.ll +++ b/llvm/test/Transforms/Inline/inline-no-builtin-compatible.ll @@ -1,6 +1,5 @@ ; Test to ensure no inlining is allowed into a caller with fewer nobuiltin attributes. ; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -S -passes=inline | FileCheck %s -; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s ; Make sure we don't inline callees into a caller with a superset of the ; no builtin attributes when -inline-caller-superset-nobuiltin=false. diff --git a/llvm/test/Transforms/Inline/inline-vla.ll b/llvm/test/Transforms/Inline/inline-vla.ll index 1e3c2351e6ed3..d6bfea2d1762c 100644 --- a/llvm/test/Transforms/Inline/inline-vla.ll +++ b/llvm/test/Transforms/Inline/inline-vla.ll @@ -1,5 +1,4 @@ ; RUN: opt -S -passes=inline %s -o - | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' %s -o - | FileCheck %s ; RUN: opt -S -passes='module-inline' %s -o - | FileCheck %s ; Check that memcpy2 is completely inlined away. diff --git a/llvm/test/Transforms/Inline/inline_cleanup.ll b/llvm/test/Transforms/Inline/inline_cleanup.ll index c88fec9489c90..16bf46da36c70 100644 --- a/llvm/test/Transforms/Inline/inline_cleanup.ll +++ b/llvm/test/Transforms/Inline/inline_cleanup.ll @@ -2,7 +2,6 @@ ; uncond branches away after it is done specializing. ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s @A = weak global i32 0 ; [#uses=1] @B = weak global i32 0 ; [#uses=1] diff --git a/llvm/test/Transforms/Inline/inline_constprop.ll b/llvm/test/Transforms/Inline/inline_constprop.ll index 66aa1e7b477f8..ee8551df03fed 100644 --- a/llvm/test/Transforms/Inline/inline_constprop.ll +++ b/llvm/test/Transforms/Inline/inline_constprop.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -inline-threshold=20 -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=20 -S | FileCheck %s define internal i32 @callee1(i32 %A, i32 %B) { %C = sdiv i32 %A, %B diff --git a/llvm/test/Transforms/Inline/inline_dbg_declare.ll b/llvm/test/Transforms/Inline/inline_dbg_declare.ll index b7063b840e1cf..60f1c2e733b93 100644 --- a/llvm/test/Transforms/Inline/inline_dbg_declare.ll +++ b/llvm/test/Transforms/Inline/inline_dbg_declare.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -S -passes=inline | FileCheck %s -; RUN: opt < %s -S -passes='cgscc(inline)' | FileCheck %s ; ; The purpose of this test is to check that inline pass preserves debug info ; for variable using the dbg.declare intrinsic. diff --git a/llvm/test/Transforms/Inline/inline_invoke.ll b/llvm/test/Transforms/Inline/inline_invoke.ll index b8ff5c82b33a3..a5a17ea7f57bc 100644 --- a/llvm/test/Transforms/Inline/inline_invoke.ll +++ b/llvm/test/Transforms/Inline/inline_invoke.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; Test that the inliner correctly handles inlining into invoke sites ; by appending selectors and forwarding _Unwind_Resume directly to the diff --git a/llvm/test/Transforms/Inline/inline_prune.ll b/llvm/test/Transforms/Inline/inline_prune.ll index 6be268a584def..77bfef1bc77ea 100644 --- a/llvm/test/Transforms/Inline/inline_prune.ll +++ b/llvm/test/Transforms/Inline/inline_prune.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s define internal i32 @callee1(i32 %A, i32 %B) { ; CHECK-NOT: @callee1 diff --git a/llvm/test/Transforms/Inline/inline_returns_twice.ll b/llvm/test/Transforms/Inline/inline_returns_twice.ll index cacedc0e0bcf0..c04e2a54396e1 100644 --- a/llvm/test/Transforms/Inline/inline_returns_twice.ll +++ b/llvm/test/Transforms/Inline/inline_returns_twice.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; Check that functions with "returns_twice" calls are only inlined, ; if they are themselves marked as such. diff --git a/llvm/test/Transforms/Inline/inline_ssp.ll b/llvm/test/Transforms/Inline/inline_ssp.ll index ab6f8d5158007..8d76388a6defe 100644 --- a/llvm/test/Transforms/Inline/inline_ssp.ll +++ b/llvm/test/Transforms/Inline/inline_ssp.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline %s -S | FileCheck %s -; RUN: opt -passes='cgscc(inline)' %s -S | FileCheck %s ; Ensure SSP attributes are propagated correctly when inlining. @.str = private unnamed_addr constant [11 x i8] c"fun_nossp\0A\00", align 1 diff --git a/llvm/test/Transforms/Inline/inline_unreachable-2.ll b/llvm/test/Transforms/Inline/inline_unreachable-2.ll index 703cd430adae3..c9cad2993bbe4 100644 --- a/llvm/test/Transforms/Inline/inline_unreachable-2.ll +++ b/llvm/test/Transforms/Inline/inline_unreachable-2.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; CHECK-LABEL: caller ; CHECK: call void @callee diff --git a/llvm/test/Transforms/Inline/inline_unreachable.ll b/llvm/test/Transforms/Inline/inline_unreachable.ll index e5c8bfd37a334..176cd5cbeceac 100644 --- a/llvm/test/Transforms/Inline/inline_unreachable.ll +++ b/llvm/test/Transforms/Inline/inline_unreachable.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s @a = global i32 4 @_ZTIi = external global ptr diff --git a/llvm/test/Transforms/Inline/invoke-cleanup.ll b/llvm/test/Transforms/Inline/invoke-cleanup.ll index 9e0344b5b08a4..797bb3265b3d3 100644 --- a/llvm/test/Transforms/Inline/invoke-cleanup.ll +++ b/llvm/test/Transforms/Inline/invoke-cleanup.ll @@ -1,5 +1,4 @@ ; RUN: opt %s -passes=inline -S | FileCheck %s -; RUN: opt %s -passes='cgscc(inline)' -S | FileCheck %s ; RUN: opt %s -passes='module-inline' -S | FileCheck %s declare void @external_func() diff --git a/llvm/test/Transforms/Inline/invoke-cost.ll b/llvm/test/Transforms/Inline/invoke-cost.ll index 1159603c62f32..9535441ff918b 100644 --- a/llvm/test/Transforms/Inline/invoke-cost.ll +++ b/llvm/test/Transforms/Inline/invoke-cost.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline < %s -S -o - -inline-threshold=100 | FileCheck %s -; RUN: opt -passes='cgscc(inline)' < %s -S -o - -inline-threshold=100 | FileCheck %s target datalayout = "p:32:32" diff --git a/llvm/test/Transforms/Inline/invoke_test-1.ll b/llvm/test/Transforms/Inline/invoke_test-1.ll index c09e7aa0fe0a4..056ab595f57cd 100644 --- a/llvm/test/Transforms/Inline/invoke_test-1.ll +++ b/llvm/test/Transforms/Inline/invoke_test-1.ll @@ -2,7 +2,6 @@ ; instructions ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; RUN: opt < %s -passes='module-inline' -S | FileCheck %s declare void @might_throw() diff --git a/llvm/test/Transforms/Inline/invoke_test-3.ll b/llvm/test/Transforms/Inline/invoke_test-3.ll index 3bf8bea82660f..79d6ef73f0582 100644 --- a/llvm/test/Transforms/Inline/invoke_test-3.ll +++ b/llvm/test/Transforms/Inline/invoke_test-3.ll @@ -2,7 +2,6 @@ ; turned into branches to the invoke destination. ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; RUN: opt < %s -passes='module-inline' -S | FileCheck %s declare void @might_throw() diff --git a/llvm/test/Transforms/Inline/local-as-metadata-undominated-use.ll b/llvm/test/Transforms/Inline/local-as-metadata-undominated-use.ll index d08c2430d5ce2..bd2c911be6002 100644 --- a/llvm/test/Transforms/Inline/local-as-metadata-undominated-use.ll +++ b/llvm/test/Transforms/Inline/local-as-metadata-undominated-use.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s ; ; Make sure the inliner doesn't crash when a metadata-bridged SSA operand is an diff --git a/llvm/test/Transforms/Inline/nested-inline.ll b/llvm/test/Transforms/Inline/nested-inline.ll index 703a8cbcb9724..628bbb97beaac 100644 --- a/llvm/test/Transforms/Inline/nested-inline.ll +++ b/llvm/test/Transforms/Inline/nested-inline.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; RUN: opt < %s -passes='module-inline' -S | FileCheck %s ; Test that bar and bar2 are both inlined throughout and removed. @A = weak global i32 0 ; [#uses=1] diff --git a/llvm/test/Transforms/Inline/noinline-recursive-fn.ll b/llvm/test/Transforms/Inline/noinline-recursive-fn.ll index ecfeae8e5cdb7..9386632a70a85 100644 --- a/llvm/test/Transforms/Inline/noinline-recursive-fn.ll +++ b/llvm/test/Transforms/Inline/noinline-recursive-fn.ll @@ -3,7 +3,6 @@ ; inliner heuristics are not set up for this. ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.3" diff --git a/llvm/test/Transforms/Inline/nonnull.ll b/llvm/test/Transforms/Inline/nonnull.ll index 9c0a225c57646..93aabfb6f10ab 100644 --- a/llvm/test/Transforms/Inline/nonnull.ll +++ b/llvm/test/Transforms/Inline/nonnull.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; RUN: opt -S -passes=inline %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' %s | FileCheck %s ; RUN: opt -S -passes='module-inline' %s | FileCheck %s declare void @foo() diff --git a/llvm/test/Transforms/Inline/parallel-loop-md.ll b/llvm/test/Transforms/Inline/parallel-loop-md.ll index d1991975e2a8e..b7640a6e69b87 100644 --- a/llvm/test/Transforms/Inline/parallel-loop-md.ll +++ b/llvm/test/Transforms/Inline/parallel-loop-md.ll @@ -1,5 +1,4 @@ ; RUN: opt -S -passes=inline < %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' < %s | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/Inline/pr21206.ll b/llvm/test/Transforms/Inline/pr21206.ll index 0123f929c5189..d945fac2d0b31 100644 --- a/llvm/test/Transforms/Inline/pr21206.ll +++ b/llvm/test/Transforms/Inline/pr21206.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s ; RUN: opt < %s -passes='module-inline' -S | FileCheck %s $c = comdat any diff --git a/llvm/test/Transforms/Inline/pr26698.ll b/llvm/test/Transforms/Inline/pr26698.ll index 265491fbe45be..fff5227b78e58 100644 --- a/llvm/test/Transforms/Inline/pr26698.ll +++ b/llvm/test/Transforms/Inline/pr26698.ll @@ -1,5 +1,4 @@ ; RUN: opt -S -passes=inline -inline-threshold=100 -inline-cold-callsite-threshold=100 < %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' -inline-threshold=100 -inline-cold-callsite-threshold=100 < %s | FileCheck %s target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i686-pc-windows-msvc18.0.0" diff --git a/llvm/test/Transforms/Inline/profile-meta.ll b/llvm/test/Transforms/Inline/profile-meta.ll index 79434cdc9d54a..31e4fa4481984 100644 --- a/llvm/test/Transforms/Inline/profile-meta.ll +++ b/llvm/test/Transforms/Inline/profile-meta.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -S -passes=inline | FileCheck %s -; RUN: opt < %s -S -passes='cgscc(inline)' | FileCheck %s ; Make sure that profile and unpredictable metadata is preserved when cloning a select. diff --git a/llvm/test/Transforms/Inline/recursive.ll b/llvm/test/Transforms/Inline/recursive.ll index d63076dc7ff30..1666a75938bfc 100644 --- a/llvm/test/Transforms/Inline/recursive.ll +++ b/llvm/test/Transforms/Inline/recursive.ll @@ -2,7 +2,6 @@ ; test here. ; ; RUN: opt -passes=inline -S < %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S < %s | FileCheck %s define i32 @large_stack_callee(i32 %param) { ; CHECK-LABEL: define i32 @large_stack_callee( diff --git a/llvm/test/Transforms/Inline/ret_attr_align_and_noundef.ll b/llvm/test/Transforms/Inline/ret_attr_align_and_noundef.ll index 930bef43df1db..c99d979be472b 100644 --- a/llvm/test/Transforms/Inline/ret_attr_align_and_noundef.ll +++ b/llvm/test/Transforms/Inline/ret_attr_align_and_noundef.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; RUN: opt -S -passes=inline %s | FileCheck %s -; RUN: opt -S -passes='cgscc(inline)' %s | FileCheck %s ; RUN: opt -S -passes='module-inline' %s | FileCheck %s declare ptr @foo() diff --git a/llvm/test/Transforms/Inline/ret_attr_nofpclass.ll b/llvm/test/Transforms/Inline/ret_attr_nofpclass.ll new file mode 100644 index 0000000000000..16ad718d60349 --- /dev/null +++ b/llvm/test/Transforms/Inline/ret_attr_nofpclass.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -passes=inline %s | FileCheck %s + +declare float @val_f32() +declare float @use.val(float) willreturn nounwind + +define float @callee() { +; CHECK-LABEL: define float @callee() { +; CHECK-NEXT: [[R:%.*]] = call float @val_f32() +; CHECK-NEXT: ret float [[R]] +; + %r = call float @val_f32() + ret float %r +} + +define float @caller_okay_use_after_poison_anyways() { +; CHECK-LABEL: define float @caller_okay_use_after_poison_anyways() { +; CHECK-NEXT: [[R_I:%.*]] = call nofpclass(nan) float @val_f32() +; CHECK-NEXT: call void @use.val(float [[R_I]]) +; CHECK-NEXT: ret float [[R_I]] +; + %r = call nofpclass(nan) float @callee() + call void @use.val(float %r) + ret float %r +} + +define float @callee_nofpclass_inf_nan() { +; CHECK-LABEL: define float @callee_nofpclass_inf_nan() { +; CHECK-NEXT: [[R:%.*]] = call nofpclass(nan inf) float @val_f32() +; CHECK-NEXT: ret float [[R]] +; + %r = call nofpclass(nan inf) float @val_f32() + ret float %r +} + +define float @caller_okay_intersect_nofpclass() { +; CHECK-LABEL: define float @caller_okay_intersect_nofpclass() { +; CHECK-NEXT: [[R_I:%.*]] = call nofpclass(nan inf) float @val_f32() +; CHECK-NEXT: call void @use.val(float [[R_I]]) +; CHECK-NEXT: ret float [[R_I]] +; + %r = call nofpclass(nan) float @callee_nofpclass_inf_nan() + call void @use.val(float %r) + ret float %r +} + +define float @caller_not_intersecting_nofpclass() { +; CHECK-LABEL: define float @caller_not_intersecting_nofpclass() { +; CHECK-NEXT: [[R_I:%.*]] = call nofpclass(nan inf zero) float @val_f32() +; CHECK-NEXT: call void @use.val(float [[R_I]]) +; CHECK-NEXT: ret float [[R_I]] +; + %r = call nofpclass(zero) float @callee_nofpclass_inf_nan() + call void @use.val(float %r) + ret float %r +} + diff --git a/llvm/test/Transforms/Inline/simplify-instruction-computeKnownFPClass-context.ll b/llvm/test/Transforms/Inline/simplify-instruction-computeKnownFPClass-context.ll index fe6884c926be4..fcb4f3f7b20ed 100644 --- a/llvm/test/Transforms/Inline/simplify-instruction-computeKnownFPClass-context.ll +++ b/llvm/test/Transforms/Inline/simplify-instruction-computeKnownFPClass-context.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; RUN: opt < %s -passes=inline -inline-threshold=20 -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=20 -S | FileCheck %s ; Make sure there are no crashes when calling computeKnownFPClass with ; un-inserted cloned instructions. diff --git a/llvm/test/Transforms/Inline/switch.ll b/llvm/test/Transforms/Inline/switch.ll index 8d3a2e38aef83..43e774e8717a2 100644 --- a/llvm/test/Transforms/Inline/switch.ll +++ b/llvm/test/Transforms/Inline/switch.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -inline-threshold=20 -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=20 -S | FileCheck %s define i32 @callee(i32 %a) { switch i32 %a, label %sw.default [ diff --git a/llvm/test/Transforms/Inline/vector-bonus.ll b/llvm/test/Transforms/Inline/vector-bonus.ll index e406a5c711356..5fabcb16f7703 100644 --- a/llvm/test/Transforms/Inline/vector-bonus.ll +++ b/llvm/test/Transforms/Inline/vector-bonus.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -passes=inline -inline-threshold=35 -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=35 -S | FileCheck %s define i32 @bar(<4 x i32> %v, i32 %i) #0 { entry: diff --git a/llvm/test/Transforms/Inline/vector-no-bonus.ll b/llvm/test/Transforms/Inline/vector-no-bonus.ll index 61340bf63bc4a..4dbbbc69843b4 100644 --- a/llvm/test/Transforms/Inline/vector-no-bonus.ll +++ b/llvm/test/Transforms/Inline/vector-no-bonus.ll @@ -2,7 +2,6 @@ ; the fact that the call to bar is cold thereby preventing the application of ; the vector bonus. ; RUN: opt < %s -passes=inline -inline-threshold=35 -S | FileCheck %s -; RUN: opt < %s -passes='cgscc(inline)' -inline-threshold=35 -S | FileCheck %s define i32 @bar(<4 x i32> %v, i32 %i) #0 { entry: diff --git a/llvm/test/Transforms/Inline/zero-cost.ll b/llvm/test/Transforms/Inline/zero-cost.ll index 7e2d33d6e357d..faf78426bb4db 100644 --- a/llvm/test/Transforms/Inline/zero-cost.ll +++ b/llvm/test/Transforms/Inline/zero-cost.ll @@ -1,5 +1,4 @@ ; RUN: opt -passes=inline -S %s | FileCheck %s -; RUN: opt -passes='cgscc(inline)' -S %s | FileCheck %s define void @f() { entry: diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll index 3ff9439040438..45e7896aaa7b7 100644 --- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll +++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll @@ -74,7 +74,7 @@ define double @test_constant_fold_rcp_f64_43() nounwind { define float @test_constant_fold_rcp_f32_43_strictfp() nounwind strictfp { ; CHECK-LABEL: @test_constant_fold_rcp_f32_43_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) #[[ATTR17:[0-9]+]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) #[[ATTR18:[0-9]+]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) strictfp nounwind readnone @@ -139,7 +139,7 @@ define half @test_constant_fold_sqrt_f16_0() nounwind { define float @test_constant_fold_sqrt_f32_0() nounwind { ; CHECK-LABEL: @test_constant_fold_sqrt_f32_0( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float 0.000000e+00) #[[ATTR18:[0-9]+]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float 0.000000e+00) #[[ATTR19:[0-9]+]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.sqrt.f32(float 0.0) nounwind readnone @@ -148,7 +148,7 @@ define float @test_constant_fold_sqrt_f32_0() nounwind { define double @test_constant_fold_sqrt_f64_0() nounwind { ; CHECK-LABEL: @test_constant_fold_sqrt_f64_0( -; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0.000000e+00) #[[ATTR18]] +; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double 0.000000e+00) #[[ATTR19]] ; CHECK-NEXT: ret double [[VAL]] ; %val = call double @llvm.amdgcn.sqrt.f64(double 0.0) nounwind readnone @@ -165,7 +165,7 @@ define half @test_constant_fold_sqrt_f16_neg0() nounwind { define float @test_constant_fold_sqrt_f32_neg0() nounwind { ; CHECK-LABEL: @test_constant_fold_sqrt_f32_neg0( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float -0.000000e+00) #[[ATTR18]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.sqrt.f32(float -0.000000e+00) #[[ATTR19]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.sqrt.f32(float -0.0) nounwind readnone @@ -174,7 +174,7 @@ define float @test_constant_fold_sqrt_f32_neg0() nounwind { define double @test_constant_fold_sqrt_f64_neg0() nounwind { ; CHECK-LABEL: @test_constant_fold_sqrt_f64_neg0( -; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double -0.000000e+00) #[[ATTR18]] +; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.sqrt.f64(double -0.000000e+00) #[[ATTR19]] ; CHECK-NEXT: ret double [[VAL]] ; %val = call double @llvm.amdgcn.sqrt.f64(double -0.0) nounwind readnone @@ -766,7 +766,7 @@ define i1 @test_class_isnan_f32(float %x) nounwind { define i1 @test_class_isnan_f32_strict(float %x) nounwind strictfp { ; CHECK-LABEL: @test_class_isnan_f32_strict( -; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR19:[0-9]+]] +; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR20:[0-9]+]] ; CHECK-NEXT: ret i1 [[VAL]] ; %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 3) strictfp @@ -784,7 +784,7 @@ define i1 @test_class_is_p0_n0_f32(float %x) nounwind { define i1 @test_class_is_p0_n0_f32_strict(float %x) nounwind strictfp { ; CHECK-LABEL: @test_class_is_p0_n0_f32_strict( -; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) #[[ATTR20]] ; CHECK-NEXT: ret i1 [[VAL]] ; %val = call i1 @llvm.amdgcn.class.f32(float %x, i32 96) strictfp @@ -1882,7 +1882,7 @@ define i64 @icmp_constant_inputs_false() { define i64 @icmp_constant_inputs_true() { ; CHECK-LABEL: @icmp_constant_inputs_true( -; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR20:[0-9]+]] +; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0:![0-9]+]]) #[[ATTR21:[0-9]+]] ; CHECK-NEXT: ret i64 [[RESULT]] ; %result = call i64 @llvm.amdgcn.icmp.i64.i32(i32 9, i32 8, i32 34) @@ -2589,7 +2589,7 @@ define i64 @fcmp_constant_inputs_false() { define i64 @fcmp_constant_inputs_true() { ; CHECK-LABEL: @fcmp_constant_inputs_true( -; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR20]] +; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.read_register.i64(metadata [[META0]]) #[[ATTR21]] ; CHECK-NEXT: ret i64 [[RESULT]] ; %result = call i64 @llvm.amdgcn.fcmp.i64.f32(float 2.0, float 4.0, i32 4) @@ -5614,7 +5614,7 @@ declare float @llvm.amdgcn.trig.preop.f32(float, i32) define double @trig_preop_constfold_variable_undef_arg(i32 %arg) { ; CHECK-LABEL: @trig_preop_constfold_variable_undef_arg( -; CHECK-NEXT: ret double 0x7FF8000000000000 +; CHECK-NEXT: ret double 0.000000e+00 ; %val = call double @llvm.amdgcn.trig.preop.f64(double undef, i32 %arg) ret double %val @@ -5630,8 +5630,7 @@ define double @trig_preop_constfold_variable_poison_arg(i32 %arg) { define double @trig_preop_constfold_variable_arg_undef(double %arg) { ; CHECK-LABEL: @trig_preop_constfold_variable_arg_undef( -; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double [[ARG:%.*]], i32 undef) -; CHECK-NEXT: ret double [[VAL]] +; CHECK-NEXT: ret double 0.000000e+00 ; %val = call double @llvm.amdgcn.trig.preop.f64(double %arg, i32 undef) ret double %val @@ -5656,7 +5655,8 @@ define double @trig_preop_constfold_variable_int(i32 %arg) { define double @trig_preop_qnan(i32 %arg) { ; CHECK-LABEL: @trig_preop_qnan( -; CHECK-NEXT: ret double 0x7FF8000000000000 +; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF8000000000000, i32 [[ARG:%.*]]) +; CHECK-NEXT: ret double [[VAL]] ; %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF8000000000000, i32 %arg) ret double %val @@ -5664,7 +5664,8 @@ define double @trig_preop_qnan(i32 %arg) { define double @trig_preop_snan(i32 %arg) { ; CHECK-LABEL: @trig_preop_snan( -; CHECK-NEXT: ret double 0x7FF8000000000001 +; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000001, i32 [[ARG:%.*]]) +; CHECK-NEXT: ret double [[VAL]] ; %val = call double @llvm.amdgcn.trig.preop.f64(double 0x7FF0000000000001, i32 %arg) ret double %val @@ -5741,7 +5742,7 @@ define double @trig_preop_constfold_neg32_segment() { define double @trig_preop_constfold_strictfp() strictfp { ; CHECK-LABEL: @trig_preop_constfold_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5) #[[ATTR20]] ; CHECK-NEXT: ret double [[VAL]] ; %val = call double @llvm.amdgcn.trig.preop.f64(double 3.454350e+02, i32 5) strictfp @@ -6110,7 +6111,7 @@ define half @test_constant_fold_log_f16_neg10() { define float @test_constant_fold_log_f32_qnan_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_log_f32_qnan_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.log.f32(float 0x7FF8000000000000) strictfp @@ -6119,7 +6120,7 @@ define float @test_constant_fold_log_f32_qnan_strictfp() strictfp { define float @test_constant_fold_log_f32_0_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_log_f32_0_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0.000000e+00) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0.000000e+00) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.log.f32(float 0.0) strictfp @@ -6128,7 +6129,7 @@ define float @test_constant_fold_log_f32_0_strictfp() strictfp { define float @test_constant_fold_log_f32_neg0_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_log_f32_neg0_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float -0.000000e+00) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float -0.000000e+00) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.log.f32(float -0.0) strictfp @@ -6137,7 +6138,7 @@ define float @test_constant_fold_log_f32_neg0_strictfp() strictfp { define float @test_constant_fold_log_f32_neg_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_log_f32_neg_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float -1.000000e+01) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float -1.000000e+01) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.log.f32(float -10.0) strictfp @@ -6154,7 +6155,7 @@ define float @test_constant_fold_log_f32_pinf_strictfp() strictfp { define float @test_constant_fold_log_f32_ninf_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_log_f32_ninf_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.log.f32(float 0xFFF0000000000000) strictfp @@ -6356,7 +6357,7 @@ define half @test_constant_fold_exp2_f16_neg10() { define float @test_constant_fold_exp2_f32_qnan_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_exp2_f32_qnan_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.exp2.f32(float 0x7FF8000000000000) strictfp @@ -6365,7 +6366,7 @@ define float @test_constant_fold_exp2_f32_qnan_strictfp() strictfp { define float @test_constant_fold_exp2_f32_0_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_exp2_f32_0_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 0.000000e+00) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 0.000000e+00) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.exp2.f32(float 0.0) strictfp @@ -6374,7 +6375,7 @@ define float @test_constant_fold_exp2_f32_0_strictfp() strictfp { define float @test_constant_fold_exp2_f32_neg0_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_exp2_f32_neg0_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -0.000000e+00) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -0.000000e+00) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.exp2.f32(float -0.0) strictfp @@ -6383,7 +6384,7 @@ define float @test_constant_fold_exp2_f32_neg0_strictfp() strictfp { define float @test_constant_fold_exp2_f32_1_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_exp2_f32_1_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 1.000000e+00) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 1.000000e+00) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.exp2.f32(float 1.0) strictfp @@ -6392,7 +6393,7 @@ define float @test_constant_fold_exp2_f32_1_strictfp() strictfp { define float @test_constant_fold_exp2_f32_neg1_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_exp2_f32_neg1_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -1.000000e+00) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -1.000000e+00) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.exp2.f32(float -1.0) strictfp @@ -6401,7 +6402,7 @@ define float @test_constant_fold_exp2_f32_neg1_strictfp() strictfp { define float @test_constant_fold_exp2_f32_2_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_exp2_f32_2_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 2.000000e+00) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float 2.000000e+00) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.exp2.f32(float 2.0) strictfp @@ -6410,7 +6411,7 @@ define float @test_constant_fold_exp2_f32_2_strictfp() strictfp { define float @test_constant_fold_exp2_f32_neg2_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_exp2_f32_neg2_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -2.000000e+00) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -2.000000e+00) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.exp2.f32(float -2.0) strictfp @@ -6419,7 +6420,7 @@ define float @test_constant_fold_exp2_f32_neg2_strictfp() strictfp { define float @test_constant_fold_exp2_f32_neg_strictfp() strictfp { ; CHECK-LABEL: @test_constant_fold_exp2_f32_neg_strictfp( -; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -1.000000e+01) #[[ATTR19]] +; CHECK-NEXT: [[VAL:%.*]] = call float @llvm.amdgcn.exp2.f32(float -1.000000e+01) #[[ATTR20]] ; CHECK-NEXT: ret float [[VAL]] ; %val = call float @llvm.amdgcn.exp2.f32(float -10.0) strictfp diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wave.shuffle.ll b/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wave.shuffle.ll new file mode 100644 index 0000000000000..4617592c70f7a --- /dev/null +++ b/llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.wave.shuffle.ll @@ -0,0 +1,250 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -passes=instcombine -S < %s | FileCheck -check-prefixes=CHECK-W32 %s +; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+wavefrontsize64 -passes=instcombine -S < %s | FileCheck -check-prefixes=CHECK-W64 %s + +; DPP16 Row Share optimization depends on knowing the wavefront size, this run should skip the optimization +; RUN: opt -mtriple=amdgcn-- -mattr=+dpp -passes=instcombine -S < %s | FileCheck -check-prefixes=CHECK-NO-WAVE-SIZE %s + +define i32 @test_wave_shuffle_self_select(i32 %val) { +; CHECK-W32-LABEL: define i32 @test_wave_shuffle_self_select( +; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-W32-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-W32-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[TID]]) +; CHECK-W32-NEXT: ret i32 [[RES]] +; +; CHECK-W64-LABEL: define i32 @test_wave_shuffle_self_select( +; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-W64-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-W64-NEXT: [[TID1:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[TID]]) +; CHECK-W64-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[TID1]]) +; CHECK-W64-NEXT: ret i32 [[RES]] +; +; CHECK-NO-WAVE-SIZE-LABEL: define i32 @test_wave_shuffle_self_select( +; CHECK-NO-WAVE-SIZE-SAME: i32 [[VAL:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NO-WAVE-SIZE-NEXT: [[LO:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-NO-WAVE-SIZE-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[LO]]) +; CHECK-NO-WAVE-SIZE-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[TID]]) +; CHECK-NO-WAVE-SIZE-NEXT: ret i32 [[RES]] +; + %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) + %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %tid) + ret i32 %res +} + +; In the Row Share 0 case, the logic is the same with and without the or. +; In fact, the or will likely be optimized out before reaching the DPP +; optimization step anyway. So this case should work with or without the or +define i32 @test_wave_shuffle_dpp_row_share_0(i32 %val) { +; CHECK-W32-LABEL: define i32 @test_wave_shuffle_dpp_row_share_0( +; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[VAL]], i32 336, i32 15, i32 15, i1 false) +; CHECK-W32-NEXT: ret i32 [[RES]] +; +; CHECK-W64-LABEL: define i32 @test_wave_shuffle_dpp_row_share_0( +; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[VAL]], i32 336, i32 15, i32 15, i1 false) +; CHECK-W64-NEXT: ret i32 [[RES]] +; +; CHECK-NO-WAVE-SIZE-LABEL: define i32 @test_wave_shuffle_dpp_row_share_0( +; CHECK-NO-WAVE-SIZE-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-NO-WAVE-SIZE-NEXT: [[LO:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-NO-WAVE-SIZE-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[LO]]) +; CHECK-NO-WAVE-SIZE-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 65520 +; CHECK-NO-WAVE-SIZE-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[MASKED]]) +; CHECK-NO-WAVE-SIZE-NEXT: ret i32 [[RES]] +; + %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) + %masked = and i32 %tid, 65520 ; 0xFFF0 + %share_0 = or i32 %masked, 0 + %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %share_0) + ret i32 %res +} + +define i32 @test_wave_shuffle_dpp_row_share_0_no_or(i32 %val) { +; CHECK-W32-LABEL: define i32 @test_wave_shuffle_dpp_row_share_0_no_or( +; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[VAL]], i32 336, i32 15, i32 15, i1 false) +; CHECK-W32-NEXT: ret i32 [[RES]] +; +; CHECK-W64-LABEL: define i32 @test_wave_shuffle_dpp_row_share_0_no_or( +; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[VAL]], i32 336, i32 15, i32 15, i1 false) +; CHECK-W64-NEXT: ret i32 [[RES]] +; +; CHECK-NO-WAVE-SIZE-LABEL: define i32 @test_wave_shuffle_dpp_row_share_0_no_or( +; CHECK-NO-WAVE-SIZE-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-NO-WAVE-SIZE-NEXT: [[LO:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-NO-WAVE-SIZE-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[LO]]) +; CHECK-NO-WAVE-SIZE-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 65520 +; CHECK-NO-WAVE-SIZE-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[MASKED]]) +; CHECK-NO-WAVE-SIZE-NEXT: ret i32 [[RES]] +; + %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) + %masked = and i32 %tid, 65520 ; 0xFFF0 + %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %masked) + ret i32 %res +} + +define i32 @test_wave_shuffle_dpp_row_share_7(i32 %val) { +; CHECK-W32-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7( +; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[VAL]], i32 343, i32 15, i32 15, i1 false) +; CHECK-W32-NEXT: ret i32 [[RES]] +; +; CHECK-W64-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7( +; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W64-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[VAL]], i32 343, i32 15, i32 15, i1 false) +; CHECK-W64-NEXT: ret i32 [[RES]] +; +; CHECK-NO-WAVE-SIZE-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7( +; CHECK-NO-WAVE-SIZE-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-NO-WAVE-SIZE-NEXT: [[LO:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-NO-WAVE-SIZE-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[LO]]) +; CHECK-NO-WAVE-SIZE-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 48 +; CHECK-NO-WAVE-SIZE-NEXT: [[SHARE_7:%.*]] = or disjoint i32 [[MASKED]], 7 +; CHECK-NO-WAVE-SIZE-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[SHARE_7]]) +; CHECK-NO-WAVE-SIZE-NEXT: ret i32 [[RES]] +; + %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) + %masked = and i32 %tid, 48 ; 0x30 + %share_7 = or i32 %masked, 7 + %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %share_7) + ret i32 %res +} + +define i32 @test_wave_shuffle_dpp_row_share_7_no_mask(i32 %val) { +; CHECK-W32-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7_no_mask( +; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W32-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-W32-NEXT: [[SHARE_7:%.*]] = or i32 [[TID]], 7 +; CHECK-W32-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[SHARE_7]]) +; CHECK-W32-NEXT: ret i32 [[RES]] +; +; CHECK-W64-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7_no_mask( +; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W64-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-W64-NEXT: [[TID1:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[TID]]) +; CHECK-W64-NEXT: [[SHARE_7:%.*]] = or i32 [[TID1]], 7 +; CHECK-W64-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[SHARE_7]]) +; CHECK-W64-NEXT: ret i32 [[RES]] +; +; CHECK-NO-WAVE-SIZE-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7_no_mask( +; CHECK-NO-WAVE-SIZE-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-NO-WAVE-SIZE-NEXT: [[LO:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-NO-WAVE-SIZE-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[LO]]) +; CHECK-NO-WAVE-SIZE-NEXT: [[SHARE_7:%.*]] = or i32 [[TID]], 7 +; CHECK-NO-WAVE-SIZE-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[SHARE_7]]) +; CHECK-NO-WAVE-SIZE-NEXT: ret i32 [[RES]] +; + %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) + %share_7 = or i32 %tid, 7 + %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %share_7) + ret i32 %res +} + +; Doing both mbcnt.lo and mbcnt.hi works for both wave32 and wave64 because the +; mbcnt.hi is optimized away for wave32. However, ommitting mbcnt.hi should prevent +; wave64 from optimizing to dpp. +define i32 @test_wave_shuffle_dpp_row_share_7_lo_only(i32 %val) { +; CHECK-W32-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7_lo_only( +; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[VAL]], i32 343, i32 15, i32 15, i1 false) +; CHECK-W32-NEXT: ret i32 [[RES]] +; +; CHECK-W64-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7_lo_only( +; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W64-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-W64-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 65520 +; CHECK-W64-NEXT: [[SHARE_7:%.*]] = or disjoint i32 [[MASKED]], 7 +; CHECK-W64-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[SHARE_7]]) +; CHECK-W64-NEXT: ret i32 [[RES]] +; +; CHECK-NO-WAVE-SIZE-LABEL: define i32 @test_wave_shuffle_dpp_row_share_7_lo_only( +; CHECK-NO-WAVE-SIZE-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-NO-WAVE-SIZE-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-NO-WAVE-SIZE-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 65520 +; CHECK-NO-WAVE-SIZE-NEXT: [[SHARE_7:%.*]] = or disjoint i32 [[MASKED]], 7 +; CHECK-NO-WAVE-SIZE-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[SHARE_7]]) +; CHECK-NO-WAVE-SIZE-NEXT: ret i32 [[RES]] +; + %tid = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %masked = and i32 %tid, 65520 ; 0xFFF0 + %share_7 = or i32 %masked, 7 + %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %share_7) + ret i32 %res +} + +; The mask requirements for wave32 and wave64 are slightly different since wave64 +; has 4 rows. This test has a mask that should only be valid for wave32 to be +; optimized to dpp. +define i32 @test_wave_shuffle_dpp_row_share_w32_mask(i32 %val) { +; CHECK-W32-LABEL: define i32 @test_wave_shuffle_dpp_row_share_w32_mask( +; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W32-NEXT: [[RES:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32 [[VAL]], i32 343, i32 15, i32 15, i1 false) +; CHECK-W32-NEXT: ret i32 [[RES]] +; +; CHECK-W64-LABEL: define i32 @test_wave_shuffle_dpp_row_share_w32_mask( +; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W64-NEXT: [[LO:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-W64-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[LO]]) +; CHECK-W64-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 16 +; CHECK-W64-NEXT: [[SHARE_7:%.*]] = or disjoint i32 [[MASKED]], 7 +; CHECK-W64-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[SHARE_7]]) +; CHECK-W64-NEXT: ret i32 [[RES]] +; +; CHECK-NO-WAVE-SIZE-LABEL: define i32 @test_wave_shuffle_dpp_row_share_w32_mask( +; CHECK-NO-WAVE-SIZE-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-NO-WAVE-SIZE-NEXT: [[LO:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-NO-WAVE-SIZE-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[LO]]) +; CHECK-NO-WAVE-SIZE-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 16 +; CHECK-NO-WAVE-SIZE-NEXT: [[SHARE_7:%.*]] = or disjoint i32 [[MASKED]], 7 +; CHECK-NO-WAVE-SIZE-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[SHARE_7]]) +; CHECK-NO-WAVE-SIZE-NEXT: ret i32 [[RES]] +; + %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) + %masked = and i32 %tid, 16 ; 0x10 + %share_7 = or i32 %masked, 7 + %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %share_7) + ret i32 %res +} + +define i32 @test_wave_shuffle_not_quite_row_share(i32 %val) { +; CHECK-W32-LABEL: define i32 @test_wave_shuffle_not_quite_row_share( +; CHECK-W32-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W32-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-W32-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 65280 +; CHECK-W32-NEXT: [[OR_RES:%.*]] = or disjoint i32 [[MASKED]], 55 +; CHECK-W32-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[OR_RES]]) +; CHECK-W32-NEXT: ret i32 [[RES]] +; +; CHECK-W64-LABEL: define i32 @test_wave_shuffle_not_quite_row_share( +; CHECK-W64-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-W64-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-W64-NEXT: [[TID1:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[TID]]) +; CHECK-W64-NEXT: [[MASKED:%.*]] = and i32 [[TID1]], 65280 +; CHECK-W64-NEXT: [[OR_RES:%.*]] = or disjoint i32 [[MASKED]], 55 +; CHECK-W64-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[OR_RES]]) +; CHECK-W64-NEXT: ret i32 [[RES]] +; +; CHECK-NO-WAVE-SIZE-LABEL: define i32 @test_wave_shuffle_not_quite_row_share( +; CHECK-NO-WAVE-SIZE-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] { +; CHECK-NO-WAVE-SIZE-NEXT: [[LO:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) +; CHECK-NO-WAVE-SIZE-NEXT: [[TID:%.*]] = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 [[LO]]) +; CHECK-NO-WAVE-SIZE-NEXT: [[MASKED:%.*]] = and i32 [[TID]], 65280 +; CHECK-NO-WAVE-SIZE-NEXT: [[OR_RES:%.*]] = or disjoint i32 [[MASKED]], 55 +; CHECK-NO-WAVE-SIZE-NEXT: [[RES:%.*]] = tail call i32 @llvm.amdgcn.wave.shuffle.i32(i32 [[VAL]], i32 [[OR_RES]]) +; CHECK-NO-WAVE-SIZE-NEXT: ret i32 [[RES]] +; + %lo = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = tail call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) + %masked = and i32 %tid, 65280 ; 0xFF00 + %or_res = or i32 %masked, 55 ; 0x37 + %res = tail call i32 @llvm.amdgcn.wave.shuffle(i32 %val, i32 %or_res) + ret i32 %res +} diff --git a/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll b/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll index 4d856699b2d24..856c103cd1f58 100644 --- a/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll +++ b/llvm/test/Transforms/InstCombine/NVPTX/nvvm-intrins.ll @@ -5,11 +5,11 @@ ; hackery: ; RUN: cat %s > %t.ftz -; RUN: echo 'attributes #0 = { "denormal-fp-math-f32" = "preserve-sign" }' >> %t.ftz +; RUN: echo 'attributes #0 = { denormal_fpenv(float: preservesign) }' >> %t.ftz ; RUN: opt < %t.ftz -passes=instcombine -mtriple=nvptx64-nvidia-cuda -S | FileCheck %s --check-prefix=CHECK --check-prefix=FTZ ; RUN: cat %s > %t.noftz -; RUN: echo 'attributes #0 = { "denormal-fp-math-f32" = "ieee" }' >> %t.noftz +; RUN: echo 'attributes #0 = { denormal_fpenv(float: ieee) }' >> %t.noftz ; RUN: opt < %t.noftz -passes=instcombine -mtriple=nvptx64-nvidia-cuda -S | FileCheck %s --check-prefix=CHECK --check-prefix=NOFTZ ; We handle nvvm intrinsics with ftz variants as follows: diff --git a/llvm/test/Transforms/InstCombine/add-shl-mul-umax.ll b/llvm/test/Transforms/InstCombine/add-shl-mul-umax.ll index a219503456432..385bab52a8f32 100644 --- a/llvm/test/Transforms/InstCombine/add-shl-mul-umax.ll +++ b/llvm/test/Transforms/InstCombine/add-shl-mul-umax.ll @@ -11,12 +11,12 @@ ; Positive Test Cases for `shl` -define i64 @test_shl_by_2(i64 %x) { +define i64 @test_shl_by_2(i64 %x) !prof !0 { ; CHECK-LABEL: define i64 @test_shl_by_2( -; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-SAME: i64 [[X:%.*]]) !prof [[PROF0:![0-9]+]] { ; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i64 [[X]], 2 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[X]], 0 -; CHECK-NEXT: [[MAX:%.*]] = select i1 [[TMP1]], i64 1, i64 [[TMP2]] +; CHECK-NEXT: [[MAX:%.*]] = select i1 [[TMP1]], i64 1, i64 [[TMP2]], !prof [[PROF1:![0-9]+]] ; CHECK-NEXT: ret i64 [[MAX]] ; %x1 = add i64 %x, 1 @@ -351,3 +351,9 @@ define i64 @test_mul_multi_use_mul(i64 %x) { %max = call i64 @llvm.umax.i64(i64 %mul, i64 %x1) ret i64 %max } + +!0 = !{!"function_entry_count", i64 1} +;. +; CHECK: [[PROF0]] = !{!"function_entry_count", i64 1} +; CHECK: [[PROF1]] = !{!"unknown", !"instcombine"} +;. diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll index a16e30bb49452..aa68dfb540064 100644 --- a/llvm/test/Transforms/InstCombine/add.ll +++ b/llvm/test/Transforms/InstCombine/add.ll @@ -1609,7 +1609,7 @@ define i8 @fold_add_constant_preserve_nuw(i8 %x) { define i32 @sdiv_to_udiv(i32 %arg0, i32 %arg1) { ; CHECK-LABEL: @sdiv_to_udiv( ; CHECK-NEXT: [[T0:%.*]] = shl nuw nsw i32 [[ARG0:%.*]], 8 -; CHECK-NEXT: [[T2:%.*]] = add nuw nsw i32 [[T0]], 6242049 +; CHECK-NEXT: [[T2:%.*]] = add nuw nsw i32 [[T0]], 6242048 ; CHECK-NEXT: [[T3:%.*]] = udiv i32 [[T2]], 192 ; CHECK-NEXT: ret i32 [[T3]] ; @@ -4455,7 +4455,7 @@ define i32 @ceil_div_multi_use(i32 range(i32 0, 100) %x) { ret i32 %r } -; Commuted test: add operands are swapped +; Commuted test: add operands are swapped define i32 @ceil_div_commuted(i32 range(i32 0, 100) %x) { ; CHECK-LABEL: @ceil_div_commuted( ; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[X:%.*]], 7 diff --git a/llvm/test/Transforms/InstCombine/add2.ll b/llvm/test/Transforms/InstCombine/add2.ll index 375f2616a3028..2b4ad85bfd995 100644 --- a/llvm/test/Transforms/InstCombine/add2.ll +++ b/llvm/test/Transforms/InstCombine/add2.ll @@ -510,3 +510,78 @@ define i32 @sub_undemanded_low_bits(i32 %x) { %shr = lshr i32 %sub, 4 ret i32 %shr } + +define i32 @rhs_undemanded_low_bits_exact_boundary(i32 %x) { +; CHECK-LABEL: @rhs_undemanded_low_bits_exact_boundary( +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 4 +; CHECK-NEXT: [[AND:%.*]] = add i32 [[SHL]], 32 +; CHECK-NEXT: ret i32 [[AND]] +; + %shl = shl i32 %x, 4 + %add = add i32 %shl, 47 ; 47 = 32 + 15 + %and = and i32 %add, -16 ; 0xFFFFFFF0 (Low 4bits masked out) + ret i32 %and +} + +define i32 @rhs_undemanded_low_bits_overshift_collision(i32 %x) { +; CHECK-LABEL: @rhs_undemanded_low_bits_overshift_collision( +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 8 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], 288 +; CHECK-NEXT: ret i32 [[ADD]] +; + %shl = shl i32 %x, 8 + %add = add i32 %shl, 303 ; 303 = 256 + 32 + 15 + %and = and i32 %add, -16 ; 0xFFFFFFF0 + ret i32 %and +} + +define i32 @rhs_undemanded_low_bits_undershift(i32 %x) { +; CHECK-LABEL: @rhs_undemanded_low_bits_undershift( +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 2 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], 44 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], -16 +; CHECK-NEXT: ret i32 [[AND]] +; + %shl = shl i32 %x, 2 + %add = add i32 %shl, 47 + %and = and i32 %add, -16 ; 0xFFFFFFF0 + ret i32 %and +} + +define <2 x i32> @rhs_undemanded_low_bits_vector(<2 x i32> %x) { +; CHECK-LABEL: @rhs_undemanded_low_bits_vector( +; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> [[X:%.*]], splat (i32 4) +; CHECK-NEXT: [[AND:%.*]] = add <2 x i32> [[SHL]], splat (i32 32) +; CHECK-NEXT: ret <2 x i32> [[AND]] +; + %shl = shl <2 x i32> %x, + %add = add <2 x i32> %shl, + %and = and <2 x i32> %add, + ret <2 x i32> %and +} + +; Negative tests +define i32 @rhs_undemanded_low_bits_negative_lsb_demanded(i32 %x) { +; CHECK-LABEL: @rhs_undemanded_low_bits_negative_lsb_demanded( +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], 4 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], 47 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], -15 +; CHECK-NEXT: ret i32 [[AND]] +; + %shl = shl i32 %x, 4 + %add = add i32 %shl, 47 ; 47 = 0010 1111 + %and = and i32 %add, -15 ; Mask = ...1111 0001 (Bit 0 is kept!) + ret i32 %and +} + +define i32 @rhs_undemanded_low_bits_negative_unknown_lhs(i32 %x) { +; CHECK-LABEL: @rhs_undemanded_low_bits_negative_unknown_lhs( +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 47 +; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], -16 +; CHECK-NEXT: ret i32 [[AND]] +; + ; No shift here + %add = add i32 %x, 47 + %and = and i32 %add, -16 + ret i32 %and +} diff --git a/llvm/test/Transforms/InstCombine/and-compare.ll b/llvm/test/Transforms/InstCombine/and-compare.ll index 3a59aca0fa8e1..ae5be9dc47ec6 100644 --- a/llvm/test/Transforms/InstCombine/and-compare.ll +++ b/llvm/test/Transforms/InstCombine/and-compare.ll @@ -280,3 +280,20 @@ entry: %cmp = icmp ne i8 %and, 16 ret i1 %cmp } + +define i1 @test_ne_11_and_15_add_10_multiuse(i8 %a) { +; CHECK-LABEL: @test_ne_11_and_15_add_10_multiuse( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = add i8 [[A:%.*]], 10 +; CHECK-NEXT: [[AND:%.*]] = and i8 [[ADD]], 15 +; CHECK-NEXT: call void @use.i8(i8 [[AND]]) +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[AND]], 11 +; CHECK-NEXT: ret i1 [[CMP]] +; +entry: + %add = add i8 %a, 10 + %and = and i8 %add, 15 + call void @use.i8(i8 %and) + %cmp = icmp ne i8 %and, 11 + ret i1 %cmp +} diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll index 975d3a072bcd3..4cd089ca524c2 100644 --- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll +++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll @@ -1418,7 +1418,7 @@ define i1 @bitwise_and_bitwise_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[X:%.*]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] -; CHECK-NEXT: [[AND2:%.*]] = and i1 [[TMP3]], [[C1]] +; CHECK-NEXT: [[AND2:%.*]] = and i1 [[C1]], [[TMP3]] ; CHECK-NEXT: ret i1 [[AND2]] ; %c1 = icmp eq i8 %y, 42 @@ -1439,7 +1439,7 @@ define i1 @bitwise_and_bitwise_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[X:%.*]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] -; CHECK-NEXT: [[AND2:%.*]] = and i1 [[TMP3]], [[C1]] +; CHECK-NEXT: [[AND2:%.*]] = and i1 [[C1]], [[TMP3]] ; CHECK-NEXT: ret i1 [[AND2]] ; %c1 = icmp eq i8 %y, 42 @@ -1540,10 +1540,9 @@ define i1 @bitwise_and_logical_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { define i1 @logical_and_bitwise_and_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_bitwise_and_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 ; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] -; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X]], [[Z_SHIFT]] -; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 +; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X:%.*]], [[Z_SHIFT]] +; CHECK-NEXT: [[C2:%.*]] = trunc i8 [[X]] to i1 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 ; CHECK-NEXT: [[AND1:%.*]] = and i1 [[C1]], [[C2]] ; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[C3]], i1 false @@ -1563,10 +1562,9 @@ define i1 @logical_and_bitwise_and_icmps(i8 %x, i8 %y, i8 %z) { define i1 @logical_and_bitwise_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_bitwise_and_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 ; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] -; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X]], [[Z_SHIFT]] -; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 +; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X:%.*]], [[Z_SHIFT]] +; CHECK-NEXT: [[C2:%.*]] = trunc i8 [[X]] to i1 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 ; CHECK-NEXT: [[AND1:%.*]] = and i1 [[C1]], [[C2]] ; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C3]], i1 [[AND1]], i1 false @@ -1586,12 +1584,11 @@ define i1 @logical_and_bitwise_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { define i1 @logical_and_bitwise_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_bitwise_and_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 ; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] -; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X]], [[Z_SHIFT]] -; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 +; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X:%.*]], [[Z_SHIFT]] +; CHECK-NEXT: [[C2:%.*]] = trunc i8 [[X]] to i1 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 -; CHECK-NEXT: [[AND1:%.*]] = and i1 [[C2]], [[C1]] +; CHECK-NEXT: [[AND1:%.*]] = and i1 [[C1]], [[C2]] ; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[C3]], i1 false ; CHECK-NEXT: ret i1 [[AND2]] ; @@ -1609,12 +1606,11 @@ define i1 @logical_and_bitwise_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { define i1 @logical_and_bitwise_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_bitwise_and_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 ; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] -; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X]], [[Z_SHIFT]] -; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 +; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X:%.*]], [[Z_SHIFT]] +; CHECK-NEXT: [[C2:%.*]] = trunc i8 [[X]] to i1 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 -; CHECK-NEXT: [[AND1:%.*]] = and i1 [[C2]], [[C1]] +; CHECK-NEXT: [[AND1:%.*]] = and i1 [[C1]], [[C2]] ; CHECK-NEXT: [[AND2:%.*]] = select i1 [[C3]], i1 [[AND1]], i1 false ; CHECK-NEXT: ret i1 [[AND2]] ; @@ -1632,10 +1628,9 @@ define i1 @logical_and_bitwise_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { define i1 @logical_and_logical_and_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_logical_and_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 ; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] -; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X]], [[Z_SHIFT]] -; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 +; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X:%.*]], [[Z_SHIFT]] +; CHECK-NEXT: [[C2:%.*]] = trunc i8 [[X]] to i1 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 ; CHECK-NEXT: [[AND1:%.*]] = select i1 [[C1]], i1 [[C2]], i1 false ; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[C3]], i1 false @@ -1655,10 +1650,9 @@ define i1 @logical_and_logical_and_icmps(i8 %x, i8 %y, i8 %z) { define i1 @logical_and_logical_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_logical_and_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 ; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] -; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X]], [[Z_SHIFT]] -; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 +; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X:%.*]], [[Z_SHIFT]] +; CHECK-NEXT: [[C2:%.*]] = trunc i8 [[X]] to i1 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[C3]], i1 [[C1]], i1 false ; CHECK-NEXT: [[AND2:%.*]] = select i1 [[TMP1]], i1 [[C2]], i1 false @@ -1678,10 +1672,9 @@ define i1 @logical_and_logical_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { define i1 @logical_and_logical_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_logical_and_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 ; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] -; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X]], [[Z_SHIFT]] -; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 +; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[X:%.*]], [[Z_SHIFT]] +; CHECK-NEXT: [[C2:%.*]] = trunc i8 [[X]] to i1 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 ; CHECK-NEXT: [[AND1:%.*]] = select i1 [[C2]], i1 [[C1]], i1 false ; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[C3]], i1 false diff --git a/llvm/test/Transforms/InstCombine/assume-loop-align.ll b/llvm/test/Transforms/InstCombine/assume-loop-align.ll index 24fd343d1448e..7669d5bae5b08 100644 --- a/llvm/test/Transforms/InstCombine/assume-loop-align.ll +++ b/llvm/test/Transforms/InstCombine/assume-loop-align.ll @@ -10,14 +10,8 @@ target triple = "x86_64-unknown-linux-gnu" define void @foo(ptr %a, ptr %b) #0 { ; CHECK-LABEL: @foo( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint ptr [[A:%.*]] to i64 -; CHECK-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 63 -; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0 -; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) -; CHECK-NEXT: [[PTRINT1:%.*]] = ptrtoint ptr [[B:%.*]] to i64 -; CHECK-NEXT: [[MASKEDPTR2:%.*]] = and i64 [[PTRINT1]], 63 -; CHECK-NEXT: [[MASKCOND3:%.*]] = icmp eq i64 [[MASKEDPTR2]], 0 -; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND3]]) +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A:%.*]], i64 64) ] +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[B:%.*]], i64 64) ] ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.body: ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] diff --git a/llvm/test/Transforms/InstCombine/assume.ll b/llvm/test/Transforms/InstCombine/assume.ll index cc87d6542fa12..c3a193b9fc6c4 100644 --- a/llvm/test/Transforms/InstCombine/assume.ll +++ b/llvm/test/Transforms/InstCombine/assume.ll @@ -11,18 +11,10 @@ declare void @llvm.assume(i1) #1 ; Check that the assume has not been removed: define i32 @align_to_bundle(ptr %a) #0 { -; DEFAULT-LABEL: @align_to_bundle( -; DEFAULT-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 -; DEFAULT-NEXT: [[PTRINT:%.*]] = ptrtoint ptr [[A]] to i64 -; DEFAULT-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 31 -; DEFAULT-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0 -; DEFAULT-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) -; DEFAULT-NEXT: ret i32 [[T0]] -; -; BUNDLES-LABEL: @align_to_bundle( -; BUNDLES-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 -; BUNDLES-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 32) ] -; BUNDLES-NEXT: ret i32 [[T0]] +; CHECK-LABEL: @align_to_bundle( +; CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 32) ] +; CHECK-NEXT: ret i32 [[T0]] ; %t0 = load i32, ptr %a, align 4 %ptrint = ptrtoint ptr %a to i64 @@ -33,18 +25,10 @@ define i32 @align_to_bundle(ptr %a) #0 { } define i32 @align_to_bundle_ptrtoaddr(ptr %a) #0 { -; DEFAULT-LABEL: @align_to_bundle_ptrtoaddr( -; DEFAULT-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 -; DEFAULT-NEXT: [[PTRINT:%.*]] = ptrtoaddr ptr [[A]] to i64 -; DEFAULT-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 31 -; DEFAULT-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0 -; DEFAULT-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) -; DEFAULT-NEXT: ret i32 [[T0]] -; -; BUNDLES-LABEL: @align_to_bundle_ptrtoaddr( -; BUNDLES-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 -; BUNDLES-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 32) ] -; BUNDLES-NEXT: ret i32 [[T0]] +; CHECK-LABEL: @align_to_bundle_ptrtoaddr( +; CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 32) ] +; CHECK-NEXT: ret i32 [[T0]] ; %t0 = load i32, ptr %a, align 4 %ptrint = ptrtoaddr ptr %a to i64 @@ -55,18 +39,10 @@ define i32 @align_to_bundle_ptrtoaddr(ptr %a) #0 { } define i32 @align_assume_trunc_cond(ptr %a) #0 { -; DEFAULT-LABEL: @align_assume_trunc_cond( -; DEFAULT-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 -; DEFAULT-NEXT: [[PTRINT:%.*]] = ptrtoint ptr [[A]] to i64 -; DEFAULT-NEXT: [[TRUNC:%.*]] = trunc i64 [[PTRINT]] to i1 -; DEFAULT-NEXT: [[MASKCOND:%.*]] = xor i1 [[TRUNC]], true -; DEFAULT-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) -; DEFAULT-NEXT: ret i32 [[T0]] -; -; BUNDLES-LABEL: @align_assume_trunc_cond( -; BUNDLES-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 -; BUNDLES-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 2) ] -; BUNDLES-NEXT: ret i32 [[T0]] +; CHECK-LABEL: @align_assume_trunc_cond( +; CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[A:%.*]], align 4 +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 2) ] +; CHECK-NEXT: ret i32 [[T0]] ; %t0 = load i32, ptr %a, align 4 %ptrint = ptrtoint ptr %a to i64 @@ -76,21 +52,41 @@ define i32 @align_assume_trunc_cond(ptr %a) #0 { ret i32 %t0 } +define void @align_32bit(ptr %ptr) { +; CHECK-LABEL: @align_32bit( +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[PTR:%.*]], i64 4294967296) ] +; CHECK-NEXT: ret void +; +entry: + %0 = ptrtoint ptr %ptr to i64 + %trunc = trunc i64 %0 to i32 + %cmp = icmp eq i32 0, %trunc + call void @llvm.assume(i1 %cmp) + ret void +} + +define void @align_63bit(ptr %ptr) { +; CHECK-LABEL: @align_63bit( +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[PTR:%.*]], i64 -9223372036854775808) ] +; CHECK-NEXT: ret void +; +entry: + %0 = ptrtoint ptr %ptr to i64 + %trunc = trunc i64 %0 to i63 + %cmp = icmp eq i63 0, %trunc + call void @llvm.assume(i1 %cmp) + ret void +} + ; Same check as in @foo1, but make sure it works if the assume is first too. define i32 @foo2(ptr %a) #0 { -; DEFAULT-LABEL: @foo2( -; DEFAULT-NEXT: [[PTRINT:%.*]] = ptrtoint ptr [[A:%.*]] to i64 -; DEFAULT-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 31 -; DEFAULT-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0 -; DEFAULT-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) -; DEFAULT-NEXT: [[T0:%.*]] = load i32, ptr [[A]], align 4 -; DEFAULT-NEXT: ret i32 [[T0]] -; -; BUNDLES-LABEL: @foo2( -; BUNDLES-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A:%.*]], i64 32) ] -; BUNDLES-NEXT: [[T0:%.*]] = load i32, ptr [[A]], align 4 -; BUNDLES-NEXT: ret i32 [[T0]] +; CHECK-LABEL: @foo2( +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A:%.*]], i64 32) ] +; CHECK-NEXT: [[T0:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: ret i32 [[T0]] ; %ptrint = ptrtoint ptr %a to i64 %maskedptr = and i64 %ptrint, 31 @@ -423,6 +419,43 @@ define i1 @nonnull5(ptr %a) { ret i1 %rval } +define void @redundant_nonnull1(ptr nonnull %ptr) { +; CHECK-LABEL: @redundant_nonnull1( +; CHECK-NEXT: ret void +; + call void @llvm.assume(i1 true) [ "nonnull"(ptr %ptr) ] + ret void +} + +define void @redundant_nonnull2(ptr %ptr) { +; CHECK-LABEL: @redundant_nonnull2( +; CHECK-NEXT: [[NULL_CMP_NOT:%.*]] = icmp eq ptr [[PTR:%.*]], null +; CHECK-NEXT: br i1 [[NULL_CMP_NOT]], label [[FALSE:%.*]], label [[TRUE:%.*]] +; CHECK: true: +; CHECK-NEXT: ret void +; CHECK: false: +; CHECK-NEXT: ret void +; + %cmp = icmp ne ptr %ptr, null + br i1 %cmp, label %true, label %false +true: + call void @llvm.assume(i1 true) [ "nonnull"(ptr %ptr) ] + ret void + +false: + ret void +} + +define void @redundant_nonnull3(ptr %ptr) { +; CHECK-LABEL: @redundant_nonnull3( +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "nonnull"(ptr [[PTR:%.*]]) ] +; CHECK-NEXT: ret void +; + call void @llvm.assume(i1 true) [ "nonnull"(ptr %ptr) ] + call void @llvm.assume(i1 true) [ "nonnull"(ptr %ptr) ] + ret void +} + ; PR35846 - https://bugs.llvm.org/show_bug.cgi?id=35846 define i32 @assumption_conflicts_with_known_bits(i32 %a, i32 %b) { @@ -1075,4 +1108,3 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) attributes #0 = { nounwind uwtable } attributes #1 = { nounwind } - diff --git a/llvm/test/Transforms/InstCombine/assume_inevitable.ll b/llvm/test/Transforms/InstCombine/assume_inevitable.ll index 5f27ff1e609ba..f899be41e0584 100644 --- a/llvm/test/Transforms/InstCombine/assume_inevitable.ll +++ b/llvm/test/Transforms/InstCombine/assume_inevitable.ll @@ -16,10 +16,7 @@ define i32 @assume_inevitable(ptr %a, ptr %b, ptr %c) { ; CHECK-NEXT: [[M_A:%.*]] = call ptr @llvm.ptr.annotation.p0.p0(ptr nonnull [[M]], ptr nonnull @.str, ptr nonnull @.str1, i32 2, ptr null) ; CHECK-NEXT: [[OBJSZ:%.*]] = call i64 @llvm.objectsize.i64.p0(ptr [[C:%.*]], i1 false, i1 false, i1 false) ; CHECK-NEXT: store i64 [[OBJSZ]], ptr [[M_A]], align 4 -; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint ptr [[A]] to i64 -; CHECK-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 31 -; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0 -; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[A]], i64 32) ] ; CHECK-NEXT: ret i32 [[TMP0]] ; entry: diff --git a/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll b/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll index 5883c089119c4..f8db9e3b7f0d1 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-selects-icmp-condition-bittest.ll @@ -7,24 +7,24 @@ declare void @use1(i1) ; Basic case - all good. define i8 @p0(i8 %x, i8 %v0, i8 %v1) { ; CHECK-LABEL: @p0( -; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1 +; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 2 ; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK-NEXT: ret i8 [[R]] ; - %t0 = and i8 %x, 1 - %t1 = icmp eq i8 %t0, 1 + %t0 = and i8 %x, 2 + %t1 = icmp eq i8 %t0, 2 %r = select i1 %t1, i8 %v0, i8 %v1, !prof !0 ret i8 %r } define i8 @p1(i8 %x, i8 %v0, i8 %v1) { ; CHECK-LABEL: @p1( -; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1 +; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 2 ; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]] ; CHECK-NEXT: ret i8 [[R]] ; - %t0 = and i8 %x, 1 + %t0 = and i8 %x, 2 %t1 = icmp ne i8 %t0, 0 %r = select i1 %t1, i8 %v0, i8 %v1 ret i8 %r @@ -33,14 +33,14 @@ define i8 @p1(i8 %x, i8 %v0, i8 %v1) { ; Can't invert all users of original condition define i8 @n2(i8 %x, i8 %v0, i8 %v1) { ; CHECK-LABEL: @n2( -; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1 +; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 2 ; CHECK-NEXT: [[T1:%.*]] = icmp ne i8 [[T0]], 0 ; CHECK-NEXT: call void @use1(i1 [[T1]]) ; CHECK-NEXT: [[R:%.*]] = select i1 [[T1]], i8 [[V0:%.*]], i8 [[V1:%.*]] ; CHECK-NEXT: ret i8 [[R]] ; - %t0 = and i8 %x, 1 - %t1 = icmp eq i8 %t0, 1 + %t0 = and i8 %x, 2 + %t1 = icmp eq i8 %t0, 2 call void @use1(i1 %t1) ; condition has un-invertable use %r = select i1 %t1, i8 %v0, i8 %v1 ret i8 %r @@ -50,7 +50,7 @@ define i8 @n2(i8 %x, i8 %v0, i8 %v1) { define i8 @t3(i8 %x, i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %out, i1 %c) { ; CHECK-LABEL: @t3( ; CHECK-NEXT: bb0: -; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1 +; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 2 ; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0 ; CHECK-NEXT: br i1 [[C:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK: bb1: @@ -62,8 +62,8 @@ define i8 @t3(i8 %x, i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %out, i1 %c) { ; CHECK-NEXT: ret i8 [[R1]] ; bb0: - %t0 = and i8 %x, 1 - %t1 = icmp eq i8 %t0, 1 + %t0 = and i8 %x, 2 + %t1 = icmp eq i8 %t0, 2 br i1 %c, label %bb1, label %bb2 bb1: %r0 = select i1 %t1, i8 %v0, i8 %v1 @@ -75,14 +75,14 @@ bb2: } define i8 @t4(i8 %x, i8 %v0, i8 %v1, i8 %v2, i8 %v3, ptr %out) { ; CHECK-LABEL: @t4( -; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1 +; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 2 ; CHECK-NEXT: [[T1_NOT:%.*]] = icmp eq i8 [[T0]], 0 ; CHECK-NEXT: [[R0:%.*]] = select i1 [[T1_NOT]], i8 [[V1:%.*]], i8 [[V0:%.*]] ; CHECK-NEXT: store i8 [[R0]], ptr [[OUT:%.*]], align 1 ; CHECK-NEXT: [[R1:%.*]] = select i1 [[T1_NOT]], i8 [[V3:%.*]], i8 [[V2:%.*]] ; CHECK-NEXT: ret i8 [[R1]] ; - %t0 = and i8 %x, 1 + %t0 = and i8 %x, 2 %t1 = icmp ne i8 %t0, 0 %r0 = select i1 %t1, i8 %v0, i8 %v1 store i8 %r0, ptr %out @@ -111,13 +111,13 @@ define i8 @n6(i8 %x, i8 %v0, i8 %v1) { } define i8 @n7(i8 %x, i8 %v0, i8 %v1) { ; CHECK-LABEL: @n7( -; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 1 +; CHECK-NEXT: [[T0:%.*]] = and i8 [[X:%.*]], 2 ; CHECK-NEXT: [[T1_NOT_NOT:%.*]] = icmp eq i8 [[T0]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[T1_NOT_NOT]], i8 [[V0:%.*]], i8 [[V1:%.*]] ; CHECK-NEXT: ret i8 [[R]] ; - %t0 = and i8 %x, 1 - %t1 = icmp ne i8 %t0, 1 ; not checking that it's zero + %t0 = and i8 %x, 2 + %t1 = icmp ne i8 %t0, 2 ; not checking that it's zero %r = select i1 %t1, i8 %v0, i8 %v1 ret i8 %r } diff --git a/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll b/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll index 19c4cc979d4ba..12c18e2ec0302 100644 --- a/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll +++ b/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll @@ -274,8 +274,7 @@ define <2 x i1> @cttz_eq_bitwidth_v2i32(<2 x i32> %a) { define i1 @cttz_eq_zero_i33(i33 %x) { ; CHECK-LABEL: @cttz_eq_zero_i33( -; CHECK-NEXT: [[TMP1:%.*]] = and i33 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i33 [[TMP1]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i33 [[X:%.*]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %tz = tail call i33 @llvm.cttz.i33(i33 %x, i1 false) diff --git a/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll b/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll index dcd79f5839002..9fb3f685a0b9c 100644 --- a/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll +++ b/llvm/test/Transforms/InstCombine/combine-is.fpclass-and-fcmp.ll @@ -435,5 +435,5 @@ declare i1 @llvm.is.fpclass.f16(half, i32 immarg) #0 declare <2 x i1> @llvm.is.fpclass.v2f16(<2 x half>, i32 immarg) #0 attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #2 = { "denormal-fp-math"="ieee,dynamic" } +attributes #1 = { denormal_fpenv(ieee|preservesign) } +attributes #2 = { denormal_fpenv(ieee|dynamic) } diff --git a/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll b/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll index 9a723e8bc89ff..3ac245cb0bec6 100644 --- a/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll +++ b/llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll @@ -2221,5 +2221,5 @@ declare half @llvm.canonicalize.f16(half) #0 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #0 attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #2 = { "denormal-fp-math"="ieee,dynamic" } +attributes #1 = { denormal_fpenv(ieee|preservesign) } +attributes #2 = { denormal_fpenv(ieee|dynamic) } diff --git a/llvm/test/Transforms/InstCombine/cttz.ll b/llvm/test/Transforms/InstCombine/cttz.ll index 829213b24e93e..b3291e7058896 100644 --- a/llvm/test/Transforms/InstCombine/cttz.ll +++ b/llvm/test/Transforms/InstCombine/cttz.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals smart ; RUN: opt < %s -S -passes=instcombine | FileCheck %s declare i32 @llvm.cttz.i32(i32, i1) @@ -341,16 +341,18 @@ define i8 @fold_ctz_log2_maybe_z_okay(i8 %x, i8 %y, i1 %c) { ; CHECK-LABEL: @fold_ctz_log2_maybe_z_okay( ; CHECK-NEXT: [[X:%.*]] = add i8 [[X1:%.*]], 1 ; CHECK-NEXT: [[Y:%.*]] = add i8 [[Y1:%.*]], 2 -; CHECK-NEXT: [[V_V:%.*]] = select i1 [[C:%.*]], i8 [[X]], i8 [[Y]] +; CHECK-NEXT: [[V_V:%.*]] = select i1 [[C:%.*]], i8 [[X]], i8 [[Y]], !prof [[PROF0:![0-9]+]] ; CHECK-NEXT: ret i8 [[V_V]] ; %p2 = shl i8 2, %x %p2_2 = shl i8 4, %y - %v = select i1 %c, i8 %p2, i8 %p2_2 + %v = select i1 %c, i8 %p2, i8 %p2_2, !prof !0 %r = call i8 @llvm.cttz(i8 %v, i1 true) ret i8 %r } +!0 = !{!"branch_weights", i32 1, i32 2} + define i8 @fold_clz_log2(i8 %x) { ; CHECK-LABEL: @fold_clz_log2( ; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.umin.i8(i8 [[X:%.*]], i8 5) @@ -390,3 +392,6 @@ define i9 @fold_clz_log2_i9(i9 %x) { %r = call i9 @llvm.ctlz(i9 %v, i1 true) ret i9 %r } +;. +; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 2} +;. diff --git a/llvm/test/Transforms/InstCombine/double-float-shrink-1.ll b/llvm/test/Transforms/InstCombine/double-float-shrink-1.ll index c13a01bb9d489..3b1d1ad016a4f 100644 --- a/llvm/test/Transforms/InstCombine/double-float-shrink-1.ll +++ b/llvm/test/Transforms/InstCombine/double-float-shrink-1.ll @@ -546,33 +546,59 @@ define float @fake_fmin(float %a, float %b) { ret float %f } -declare fp128 @fmin(fp128, fp128) +; The combine from sqrt->sqrtf should only propagate the existing +; callsite attributes. It should not propgate the callee's function +; attributes to the callsite; it's invalid to set denormal_fpenv on the callsiten +define void @sqrt_to_sqrtf_only_preserve_callsite_attrs() #0 { +; LINUX-LABEL: define void @sqrt_to_sqrtf_only_preserve_callsite_attrs( +; LINUX-SAME: ) #[[ATTR0:[0-9]+]] { +; LINUX-NEXT: [[ENTRY:.*:]] +; LINUX-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float noundef -1.000000e+00) #[[CALLSITE_ATTR:[0-9]+]] +; LINUX-NEXT: ret void +entry: + %call = call double @sqrt(double noundef -1.000000e+00) #2, !tbaa !0 + ret void +} + +declare fp128 @fmin(fp128, fp128) #0 -declare double @fmax(double, double) +declare double @fmax(double, double) #0 -declare double @tanh(double) -declare double @tan(double) +declare double @tanh(double) #0 +declare double @tan(double) #0 ; sqrt is a special case: the shrinking optimization ; is valid even without unsafe-fp-math. -declare double @sqrt(double) +declare double @sqrt(double) #0 declare double @llvm.sqrt.f64(double) -declare double @sin(double) -declare double @pow(double, double) -declare double @log2(double) -declare double @log1p(double) -declare double @log10(double) -declare double @log(double) -declare double @logb(double) -declare double @exp10(double) -declare double @expm1(double) -declare double @exp(double) -declare double @cbrt(double) -declare double @atanh(double) -declare double @atan(double) -declare double @acos(double) -declare double @acosh(double) -declare double @asin(double) -declare double @asinh(double) - +declare double @sin(double) #0 +declare double @pow(double, double) #0 +declare double @log2(double) #0 +declare double @log1p(double) #0 +declare double @log10(double) #0 +declare double @log(double) #0 +declare double @logb(double) #0 +declare double @exp10(double) #0 +declare double @expm1(double) #0 +declare double @exp(double) #0 +declare double @cbrt(double) #0 +declare double @atanh(double) #0 +declare double @atan(double) #0 +declare double @acos(double) #0 +declare double @acosh(double) #0 +declare double @asin(double) #0 +declare double @asinh(double) #0 + +; LINUX: #[[CALLSITE_ATTR]] = { "custom-callsite-attr" } + +attributes #0 = { denormal_fpenv(float: dynamic) } +attributes #1 = { mustprogress nocallback nofree nounwind willreturn denormal_fpenv(float: preservesign) memory(errnomem: write) } +attributes #2 = { "custom-callsite-attr" } + +!llvm.errno.tbaa = !{!0} + +!0 = !{!1, !1, i64 0} +!1 = !{!"int", !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/Transforms/InstCombine/exact.ll b/llvm/test/Transforms/InstCombine/exact.ll index 819e8fbb89b5f..d8bbcaa949660 100644 --- a/llvm/test/Transforms/InstCombine/exact.ll +++ b/llvm/test/Transforms/InstCombine/exact.ll @@ -150,8 +150,7 @@ define <2 x i1> @ashr_icmp2_vec(<2 x i64> %X) { ; Make sure we don't transform the ashr here into an sdiv define i1 @pr9998(i32 %V) { ; CHECK-LABEL: @pr9998( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[V:%.*]], 1 -; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: [[Z:%.*]] = trunc i32 [[V:%.*]] to i1 ; CHECK-NEXT: ret i1 [[Z]] ; %W = shl i32 %V, 31 diff --git a/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll b/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll index eea1dda6230a9..7affd9215d0b7 100644 --- a/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll +++ b/llvm/test/Transforms/InstCombine/fcmp-denormals-are-zero.ll @@ -348,7 +348,7 @@ declare <2 x half> @llvm.fabs.v2f16(<2 x half>) declare double @llvm.fabs.f64(double) declare <2 x double> @llvm.fabs.v2f64(<2 x double>) -attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #1 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #2 = { "denormal-fp-math"="ieee,ieee" } -attributes #3 = { "denormal-fp-math-f32"="ieee,preserve-sign" } +attributes #0 = { denormal_fpenv(ieee|preservesign) } +attributes #1 = { denormal_fpenv(ieee|positivezero) } +attributes #2 = { denormal_fpenv(ieee|ieee) } +attributes #3 = { denormal_fpenv(float: ieee|preservesign) } diff --git a/llvm/test/Transforms/InstCombine/fcmp.ll b/llvm/test/Transforms/InstCombine/fcmp.ll index d94e78c55a375..61490d120c81c 100644 --- a/llvm/test/Transforms/InstCombine/fcmp.ll +++ b/llvm/test/Transforms/InstCombine/fcmp.ll @@ -2125,7 +2125,7 @@ define <8 x i1> @fcmp_une_fsub_const_nnan_vec(<8 x float> %x, <8 x float> %y) { ret <8 x i1> %cmp } -define <8 x i1> @fcmp_ugt_fsub_const_vec_denormal_positive-zero(<8 x float> %x, <8 x float> %y) "denormal-fp-math"="positive-zero,positive-zero" { +define <8 x i1> @fcmp_ugt_fsub_const_vec_denormal_positive-zero(<8 x float> %x, <8 x float> %y) denormal_fpenv(positivezero|positivezero) { ; CHECK-LABEL: @fcmp_ugt_fsub_const_vec_denormal_positive-zero( ; CHECK-NEXT: [[FS:%.*]] = fsub <8 x float> [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <8 x float> [[FS]], zeroinitializer @@ -2136,7 +2136,7 @@ define <8 x i1> @fcmp_ugt_fsub_const_vec_denormal_positive-zero(<8 x float> %x, ret <8 x i1> %cmp } -define <8 x i1> @fcmp_ogt_fsub_const_vec_denormal_dynamic(<8 x float> %x, <8 x float> %y) "denormal-fp-math"="dynamic,dynamic" { +define <8 x i1> @fcmp_ogt_fsub_const_vec_denormal_dynamic(<8 x float> %x, <8 x float> %y) denormal_fpenv(dynamic) { ; CHECK-LABEL: @fcmp_ogt_fsub_const_vec_denormal_dynamic( ; CHECK-NEXT: [[FS:%.*]] = fsub <8 x float> [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <8 x float> [[FS]], zeroinitializer @@ -2147,7 +2147,7 @@ define <8 x i1> @fcmp_ogt_fsub_const_vec_denormal_dynamic(<8 x float> %x, <8 x f ret <8 x i1> %cmp } -define <8 x i1> @fcmp_ogt_fsub_const_vec_denormal_preserve-sign(<8 x float> %x, <8 x float> %y) "denormal-fp-math"="preserve-sign,preserve-sign" { +define <8 x i1> @fcmp_ogt_fsub_const_vec_denormal_preserve-sign(<8 x float> %x, <8 x float> %y) denormal_fpenv(preservesign) { ; CHECK-LABEL: @fcmp_ogt_fsub_const_vec_denormal_preserve-sign( ; CHECK-NEXT: [[FS:%.*]] = fsub <8 x float> [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt <8 x float> [[FS]], zeroinitializer diff --git a/llvm/test/Transforms/InstCombine/fmod.ll b/llvm/test/Transforms/InstCombine/fmod.ll index 10cff189b8dfc..8e970c1b49532 100644 --- a/llvm/test/Transforms/InstCombine/fmod.ll +++ b/llvm/test/Transforms/InstCombine/fmod.ll @@ -99,7 +99,7 @@ entry: ret fp128 %call } -define float @test_noinf_nozero_dazpreservesign(float nofpclass(inf) %f, float nofpclass(zero) %g) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @test_noinf_nozero_dazpreservesign(float nofpclass(inf) %f, float nofpclass(zero) %g) denormal_fpenv(preservesign) { ; CHECK-LABEL: define float @test_noinf_nozero_dazpreservesign( ; CHECK-SAME: float nofpclass(inf) [[F:%.*]], float nofpclass(zero) [[G:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: @@ -111,7 +111,7 @@ entry: ret float %call } -define float @test_noinf_nozero_dazdynamic(float nofpclass(inf) %f, float nofpclass(zero) %g) "denormal-fp-math"="dynamic,dynamic" { +define float @test_noinf_nozero_dazdynamic(float nofpclass(inf) %f, float nofpclass(zero) %g) denormal_fpenv(dynamic) { ; CHECK-LABEL: define float @test_noinf_nozero_dazdynamic( ; CHECK-SAME: float nofpclass(inf) [[F:%.*]], float nofpclass(zero) [[G:%.*]]) #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: entry: diff --git a/llvm/test/Transforms/InstCombine/fneg.ll b/llvm/test/Transforms/InstCombine/fneg.ll index 4e6477f804314..ed4d43eaea235 100644 --- a/llvm/test/Transforms/InstCombine/fneg.ll +++ b/llvm/test/Transforms/InstCombine/fneg.ll @@ -110,6 +110,19 @@ define <4 x double> @fmul_fneg_vec(<4 x double> %x) { ret <4 x double> %r } +; -(X / Y) --> (-X) / Y + +define float @fdiv_fneg_fpmath(float %x, float %y) { +; CHECK-LABEL: @fdiv_fneg_fpmath( +; CHECK-NEXT: [[NEG:%.*]] = fneg float [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = fdiv float [[NEG]], [[Y:%.*]], !fpmath +; CHECK-NEXT: ret float [[R]] +; + %z = fdiv arcp float %x, %y, !fpmath !{float 2.5} + %w = fneg float %z + ret float %w +} + ; -(X / C) --> X / (-C) define float @fdiv_op1_constant_fsub(float %x) { @@ -204,6 +217,16 @@ define <4 x double> @fdiv_op1_constant_fneg_vec(<4 x double> %x) { ret <4 x double> %r } +define float @fdiv_op1_constant_fneg_fpmath(float %x) { +; CHECK-LABEL: @fdiv_op1_constant_fneg_fpmath( +; CHECK-NEXT: [[R:%.*]] = fdiv float [[X:%.*]], 4.200000e+01, !fpmath +; CHECK-NEXT: ret float [[R]] +; + %d = fdiv float %x, -42.0, !fpmath !{float 2.5} + %r = fneg float %d + ret float %r +} + ; -(C / X) --> (-C) / X define float @fdiv_op0_constant_fsub(float %x) { @@ -308,6 +331,16 @@ define float @fdiv_op0_constant_fneg_nnan(float %x) { ret float %r } +define float @fdiv_op0_constant_fneg_fpmath(float %x) { +; CHECK-LABEL: @fdiv_op0_constant_fneg_fpmath( +; CHECK-NEXT: [[R:%.*]] = fdiv float -1.000000e+00, [[X:%.*]], !fpmath +; CHECK-NEXT: ret float [[R]] +; + %d = fdiv float 1.0, %x, !fpmath !{float 2.5} + %r = fneg float %d + ret float %r +} + ; Extra use prevents the fold. We don't want to replace the fneg with an fdiv. define float @fdiv_op0_constant_fsub_extra_use(float %x) { diff --git a/llvm/test/Transforms/InstCombine/gep-sext.ll b/llvm/test/Transforms/InstCombine/gep-sext.ll index e1742e1c66178..c1998776bde2a 100644 --- a/llvm/test/Transforms/InstCombine/gep-sext.ll +++ b/llvm/test/Transforms/InstCombine/gep-sext.ll @@ -1,14 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-pc-win32" declare void @use(i32) readonly ; We prefer to canonicalize the machine width gep indices early define void @test(ptr %p, i32 %index) { -; CHECK-LABEL: @test -; CHECK-NEXT: %1 = sext i32 %index to i64 -; CHECK-NEXT: %addr = getelementptr i32, ptr %p, i64 %1 +; CHECK-LABEL: define void @test( +; CHECK-SAME: ptr [[P:%.*]], i32 [[INDEX:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[INDEX]] to i64 +; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i32, ptr [[P]], i64 [[TMP1]] +; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 +; CHECK-NEXT: call void @use(i32 [[VAL]]) +; CHECK-NEXT: ret void +; %addr = getelementptr i32, ptr %p, i32 %index %val = load i32, ptr %addr call void @use(i32 %val) @@ -16,9 +20,14 @@ define void @test(ptr %p, i32 %index) { } ; If they've already been canonicalized via zext, that's fine define void @test2(ptr %p, i32 %index) { -; CHECK-LABEL: @test2 -; CHECK-NEXT: %i = zext i32 %index to i64 -; CHECK-NEXT: %addr = getelementptr i32, ptr %p, i64 %i +; CHECK-LABEL: define void @test2( +; CHECK-SAME: ptr [[P:%.*]], i32 [[INDEX:%.*]]) { +; CHECK-NEXT: [[I:%.*]] = zext i32 [[INDEX]] to i64 +; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i32, ptr [[P]], i64 [[I]] +; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 +; CHECK-NEXT: call void @use(i32 [[VAL]]) +; CHECK-NEXT: ret void +; %i = zext i32 %index to i64 %addr = getelementptr i32, ptr %p, i64 %i %val = load i32, ptr %addr @@ -28,9 +37,17 @@ define void @test2(ptr %p, i32 %index) { ; If we can use a zext, we prefer that. This requires ; knowing that the index is positive. define void @test3(ptr %p, i32 %index) { -; CHECK-LABEL: @test3 -; CHECK: zext -; CHECK-NOT: sext +; CHECK-LABEL: define void @test3( +; CHECK-SAME: ptr [[P:%.*]], i32 [[INDEX:%.*]]) { +; CHECK-NEXT: [[ADDR_BEGIN:%.*]] = getelementptr i8, ptr [[P]], i64 160 +; CHECK-NEXT: [[ADDR_FIXED:%.*]] = getelementptr i8, ptr [[P]], i64 352 +; CHECK-NEXT: [[VAL_FIXED:%.*]] = load i32, ptr [[ADDR_FIXED]], align 4, !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[VAL_FIXED]] to i64 +; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i32, ptr [[ADDR_BEGIN]], i64 [[TMP1]] +; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 +; CHECK-NEXT: call void @use(i32 [[VAL]]) +; CHECK-NEXT: ret void +; %addr_begin = getelementptr i32, ptr %p, i64 40 %addr_fixed = getelementptr i32, ptr %addr_begin, i64 48 %val_fixed = load i32, ptr %addr_fixed, !range !0 @@ -41,9 +58,17 @@ define void @test3(ptr %p, i32 %index) { } ; Replace sext with zext where possible define void @test4(ptr %p, i32 %index) { -; CHECK-LABEL: @test4 -; CHECK: zext -; CHECK-NOT: sext +; CHECK-LABEL: define void @test4( +; CHECK-SAME: ptr [[P:%.*]], i32 [[INDEX:%.*]]) { +; CHECK-NEXT: [[ADDR_BEGIN:%.*]] = getelementptr i8, ptr [[P]], i64 160 +; CHECK-NEXT: [[ADDR_FIXED:%.*]] = getelementptr i8, ptr [[P]], i64 352 +; CHECK-NEXT: [[VAL_FIXED:%.*]] = load i32, ptr [[ADDR_FIXED]], align 4, !range [[RNG0]] +; CHECK-NEXT: [[I:%.*]] = zext nneg i32 [[VAL_FIXED]] to i64 +; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i32, ptr [[ADDR_BEGIN]], i64 [[I]] +; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[ADDR]], align 4 +; CHECK-NEXT: call void @use(i32 [[VAL]]) +; CHECK-NEXT: ret void +; %addr_begin = getelementptr i32, ptr %p, i64 40 %addr_fixed = getelementptr i32, ptr %addr_begin, i64 48 %val_fixed = load i32, ptr %addr_fixed, !range !0 @@ -57,5 +82,6 @@ define void @test4(ptr %p, i32 %index) { ;; !range !0 !0 = !{i32 0, i32 2147483647} - - +;. +; CHECK: [[RNG0]] = !{i32 0, i32 2147483647} +;. diff --git a/llvm/test/Transforms/InstCombine/gep-srem-to-and-deref.ll b/llvm/test/Transforms/InstCombine/gep-srem-to-and-deref.ll new file mode 100644 index 0000000000000..9f529dad5d3d1 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/gep-srem-to-and-deref.ll @@ -0,0 +1,128 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -passes=instcombine %s -S | FileCheck %s + +define ptr @pos_pow2_2(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @pos_pow2_2( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[IDX_MASK:%.*]] = and i64 [[X]], 1 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds nuw i8, ptr [[FOO]], i64 [[IDX_MASK]] +; CHECK-NEXT: ret ptr [[P1]] +; + %idx = srem i64 %x, 2 + %p = getelementptr inbounds nuw i8, ptr %foo, i64 %idx + ret ptr %p +} + +define ptr @pos_pow2_4(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @pos_pow2_4( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[IDX_MASK:%.*]] = and i64 [[X]], 3 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds nuw i8, ptr [[FOO]], i64 [[IDX_MASK]] +; CHECK-NEXT: ret ptr [[P1]] +; + %idx = srem i64 %x, 4 + %p = getelementptr inbounds nuw i8, ptr %foo, i64 %idx + ret ptr %p +} + +define ptr @pos_pow2_8(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @pos_pow2_8( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[IDX_MASK:%.*]] = and i64 [[X]], 7 +; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds nuw i8, ptr [[FOO]], i64 [[IDX_MASK]] +; CHECK-NEXT: ret ptr [[P1]] +; + %idx = srem i64 %x, 8 + %p = getelementptr inbounds nuw i8, ptr %foo, i64 %idx + ret ptr %p +} + +define ptr @pos_not_i8(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @pos_not_i8( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[IDX1:%.*]] = and i64 [[X]], 3 +; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds nuw i32, ptr [[FOO]], i64 [[IDX1]] +; CHECK-NEXT: ret ptr [[P2]] +; + %idx = srem i64 %x, 4 + %p = getelementptr inbounds nuw i32, ptr %foo, i64 %idx + ret ptr %p +} + +; srem x, 1 is always 0, and mask is 0. GEP should be folded to %foo. +define ptr @pos_pow2_1(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @pos_pow2_1( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: ret ptr [[FOO]] +; + %idx = srem i64 %x, 1 + %p = getelementptr inbounds nuw i8, ptr %foo, i64 %idx + ret ptr %p +} + +; Non-power-of-two constant divisor +define ptr @neg_non_pow2_6(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @neg_non_pow2_6( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[IDX:%.*]] = srem i64 [[X]], 6 +; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds nuw i8, ptr [[FOO]], i64 [[IDX]] +; CHECK-NEXT: ret ptr [[P]] +; + %idx = srem i64 %x, 6 + %p = getelementptr inbounds nuw i8, ptr %foo, i64 %idx + ret ptr %p +} + +; Missing 'no unsigned wrap' +define ptr @neg_missing_nuw(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @neg_missing_nuw( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[IDX:%.*]] = srem i64 [[X]], 4 +; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds i8, ptr [[FOO]], i64 [[IDX]] +; CHECK-NEXT: ret ptr [[P]] +; + %idx = srem i64 %x, 4 + %p = getelementptr inbounds i8, ptr %foo, i64 %idx + ret ptr %p +} + +; Missing 'inbounds' +define ptr @neg_missing_inbounds(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @neg_missing_inbounds( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[IDX:%.*]] = srem i64 [[X]], 4 +; CHECK-NEXT: [[P:%.*]] = getelementptr nuw i8, ptr [[FOO]], i64 [[IDX]] +; CHECK-NEXT: ret ptr [[P]] +; + %idx = srem i64 %x, 4 + %p = getelementptr nuw i8, ptr %foo, i64 %idx + ret ptr %p +} + +define ptr @neg_nonconst_divisor(ptr %foo, i64 %x, i64 %d) { +; CHECK-LABEL: define ptr @neg_nonconst_divisor( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]], i64 [[D:%.*]]) { +; CHECK-NEXT: [[IDX:%.*]] = srem i64 [[X]], [[D]] +; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds nuw i8, ptr [[FOO]], i64 [[IDX]] +; CHECK-NEXT: ret ptr [[P]] +; + %idx = srem i64 %x, %d + %p = getelementptr inbounds nuw i8, ptr %foo, i64 %idx + ret ptr %p +} + +declare void @use(i8) + +define ptr @neg_multi_use(ptr %foo, i64 %x) { +; CHECK-LABEL: define ptr @neg_multi_use( +; CHECK-SAME: ptr [[FOO:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[IDX:%.*]] = srem i64 [[X]], 4 +; CHECK-NEXT: call void @use(i64 [[IDX]]) +; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds nuw i8, ptr [[FOO]], i64 [[IDX]] +; CHECK-NEXT: ret ptr [[P]] +; + %idx = srem i64 %x, 4 + call void @use(i64 %idx) + %p = getelementptr inbounds nuw i8, ptr %foo, i64 %idx + ret ptr %p +} diff --git a/llvm/test/Transforms/InstCombine/icmp-and-shift.ll b/llvm/test/Transforms/InstCombine/icmp-and-shift.ll index 78f1bc7d7379d..2973bb979181d 100644 --- a/llvm/test/Transforms/InstCombine/icmp-and-shift.ll +++ b/llvm/test/Transforms/InstCombine/icmp-and-shift.ll @@ -608,9 +608,8 @@ define i1 @fold_ne_rhs_fail_shift_not_1s(i8 %x, i8 %yy) { define i1 @test_shr_and_1_ne_0(i32 %a, i32 %b) { ; CHECK-LABEL: @test_shr_and_1_ne_0( -; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 1, [[B:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[A:%.*]], [[TMP1]] -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[SHR]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %shr = lshr i32 %a, %b @@ -621,9 +620,8 @@ define i1 @test_shr_and_1_ne_0(i32 %a, i32 %b) { define i1 @test_shr_and_1_ne_0_samesign(i32 %a, i32 %b) { ; CHECK-LABEL: @test_shr_and_1_ne_0_samesign( -; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 1, [[B:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[A:%.*]], [[TMP1]] -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[SHR]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %shr = lshr i32 %a, %b @@ -634,9 +632,8 @@ define i1 @test_shr_and_1_ne_0_samesign(i32 %a, i32 %b) { define i1 @test_const_shr_and_1_ne_0(i32 %b) { ; CHECK-LABEL: @test_const_shr_and_1_ne_0( -; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 1, [[B:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 42 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[SHR:%.*]] = lshr i32 42, [[B:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[SHR]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %shr = lshr i32 42, %b @@ -660,9 +657,8 @@ define i1 @test_not_const_shr_and_1_ne_0(i32 %b) { define i1 @test_const_shr_exact_and_1_ne_0(i32 %b) { ; CHECK-LABEL: @test_const_shr_exact_and_1_ne_0( -; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 1, [[B:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 42 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[SHR:%.*]] = lshr exact i32 42, [[B:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[SHR]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %shr = lshr exact i32 42, %b @@ -721,10 +717,9 @@ define i1 @test_const_shr_and_1_ne_0_i1_negative(i1 %b) { define i1 @test_const_shr_and_1_ne_0_multi_use_lshr_negative(i32 %b) { ; CHECK-LABEL: @test_const_shr_and_1_ne_0_multi_use_lshr_negative( ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 42, [[B:%.*]] -; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 1 -; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: [[CMP1:%.*]] = trunc i32 [[SHR]] to i1 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[B]], [[SHR]] -; CHECK-NEXT: [[RET:%.*]] = and i1 [[CMP1]], [[CMP2]] +; CHECK-NEXT: [[RET:%.*]] = and i1 [[CMP2]], [[CMP1]] ; CHECK-NEXT: ret i1 [[RET]] ; %shr = lshr i32 42, %b @@ -739,9 +734,9 @@ define i1 @test_const_shr_and_1_ne_0_multi_use_and_negative(i32 %b) { ; CHECK-LABEL: @test_const_shr_and_1_ne_0_multi_use_and_negative( ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 42, [[B:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 1 -; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: [[CMP1:%.*]] = trunc i32 [[SHR]] to i1 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[B]], [[AND]] -; CHECK-NEXT: [[RET:%.*]] = and i1 [[CMP1]], [[CMP2]] +; CHECK-NEXT: [[RET:%.*]] = and i1 [[CMP2]], [[CMP1]] ; CHECK-NEXT: ret i1 [[RET]] ; %shr = lshr i32 42, %b diff --git a/llvm/test/Transforms/InstCombine/icmp-binop.ll b/llvm/test/Transforms/InstCombine/icmp-binop.ll index 3b4eca3ba69b3..4c7eccbde9f2f 100644 --- a/llvm/test/Transforms/InstCombine/icmp-binop.ll +++ b/llvm/test/Transforms/InstCombine/icmp-binop.ll @@ -36,11 +36,9 @@ define <2 x i1> @mul_unkV_oddC_ne_vec(<2 x i64> %v) { define i1 @mul_assumeoddV_asumeoddV_eq(i16 %v, i16 %v2) { ; CHECK-LABEL: @mul_assumeoddV_asumeoddV_eq( -; CHECK-NEXT: [[LB:%.*]] = and i16 [[V:%.*]], 1 -; CHECK-NEXT: [[ODD:%.*]] = icmp ne i16 [[LB]], 0 +; CHECK-NEXT: [[ODD:%.*]] = trunc i16 [[V:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[ODD]]) -; CHECK-NEXT: [[LB2:%.*]] = and i16 [[V2:%.*]], 1 -; CHECK-NEXT: [[ODD2:%.*]] = icmp ne i16 [[LB2]], 0 +; CHECK-NEXT: [[ODD2:%.*]] = trunc i16 [[V2:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[ODD2]]) ; CHECK-NEXT: ret i1 true ; @@ -81,8 +79,7 @@ define i1 @mul_reused_unkV_oddC_ne(i64 %v) { define i1 @mul_assumeoddV_unkV_eq(i16 %v, i16 %v2) { ; CHECK-LABEL: @mul_assumeoddV_unkV_eq( -; CHECK-NEXT: [[LB:%.*]] = and i16 [[V2:%.*]], 1 -; CHECK-NEXT: [[ODD:%.*]] = icmp ne i16 [[LB]], 0 +; CHECK-NEXT: [[ODD:%.*]] = trunc i16 [[V2:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[ODD]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[V:%.*]], 0 ; CHECK-NEXT: ret i1 [[CMP]] @@ -97,8 +94,7 @@ define i1 @mul_assumeoddV_unkV_eq(i16 %v, i16 %v2) { define i1 @mul_reusedassumeoddV_unkV_ne(i64 %v, i64 %v2) { ; CHECK-LABEL: @mul_reusedassumeoddV_unkV_ne( -; CHECK-NEXT: [[LB:%.*]] = and i64 [[V:%.*]], 1 -; CHECK-NEXT: [[ODD:%.*]] = icmp ne i64 [[LB]], 0 +; CHECK-NEXT: [[ODD:%.*]] = trunc i64 [[V:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[ODD]]) ; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[V]], [[V2:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[V2]], 0 diff --git a/llvm/test/Transforms/InstCombine/icmp-mul-and.ll b/llvm/test/Transforms/InstCombine/icmp-mul-and.ll index 7fa75184c1cf3..62d139c81ea0f 100644 --- a/llvm/test/Transforms/InstCombine/icmp-mul-and.ll +++ b/llvm/test/Transforms/InstCombine/icmp-mul-and.ll @@ -54,8 +54,7 @@ define i1 @mul_mask_pow2_ne0_use2(i8 %x) { define i1 @mul_mask_pow2_sgt0(i8 %x) { ; CHECK-LABEL: @mul_mask_pow2_sgt0( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i8 [[X:%.*]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul i8 %x, 44 @@ -68,8 +67,7 @@ define i1 @mul_mask_pow2_sgt0(i8 %x) { define i1 @mul_mask_fakepow2_ne0(i8 %x) { ; CHECK-LABEL: @mul_mask_fakepow2_ne0( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i8 [[X:%.*]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul i8 %x, 44 @@ -82,8 +80,7 @@ define i1 @mul_mask_fakepow2_ne0(i8 %x) { define i1 @mul_mask_pow2_eq4(i8 %x) { ; CHECK-LABEL: @mul_mask_pow2_eq4( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i8 [[X:%.*]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %mul = mul i8 %x, 44 diff --git a/llvm/test/Transforms/InstCombine/icmp-mul.ll b/llvm/test/Transforms/InstCombine/icmp-mul.ll index 49e1e11fe6c36..1e4876d5cd569 100644 --- a/llvm/test/Transforms/InstCombine/icmp-mul.ll +++ b/llvm/test/Transforms/InstCombine/icmp-mul.ll @@ -1093,8 +1093,7 @@ define i1 @mul_xy_z_assumenozero_ne(i8 %x, i8 %y, i8 %z) { define i1 @mul_xy_z_assumeodd_eq(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @mul_xy_z_assumeodd_eq( -; CHECK-NEXT: [[LB:%.*]] = and i8 [[Z:%.*]], 1 -; CHECK-NEXT: [[NZ:%.*]] = icmp ne i8 [[LB]], 0 +; CHECK-NEXT: [[NZ:%.*]] = trunc i8 [[Z:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[NZ]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: ret i1 [[CMP]] diff --git a/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll b/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll index b19909a234481..4be85be543760 100644 --- a/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll +++ b/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll @@ -35,10 +35,9 @@ define i32 @not_pow2_32_assume(i32 %x) { define i64 @pow2_64_assume(i64 %x) { ; CHECK-LABEL: @pow2_64_assume( -; CHECK-NEXT: [[AND:%.*]] = and i64 [[X:%.*]], 1 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[AND]], 0 +; CHECK-NEXT: [[CMP:%.*]] = trunc i64 [[X1:%.*]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) -; CHECK-NEXT: ret i64 [[X]] +; CHECK-NEXT: ret i64 [[X1]] ; %and = and i64 %x, 1 %cmp = icmp ne i64 %and, 0 diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll index 696208b903798..42a09420769f4 100644 --- a/llvm/test/Transforms/InstCombine/icmp.ll +++ b/llvm/test/Transforms/InstCombine/icmp.ll @@ -3665,10 +3665,9 @@ define i1 @icmp_neg_cst_slt(i32 %a) { define i1 @icmp_and_or_lshr(i32 %x, i32 %y) { ; CHECK-LABEL: define i1 @icmp_and_or_lshr( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { -; CHECK-NEXT: [[SHF1:%.*]] = shl nuw i32 1, [[Y]] -; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHF1]], 1 -; CHECK-NEXT: [[AND3:%.*]] = and i32 [[X]], [[OR2]] -; CHECK-NEXT: [[RET:%.*]] = icmp ne i32 [[AND3]], 0 +; CHECK-NEXT: [[SHF:%.*]] = lshr i32 [[X]], [[Y]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHF]], [[X]] +; CHECK-NEXT: [[RET:%.*]] = trunc i32 [[OR]] to i1 ; CHECK-NEXT: ret i1 [[RET]] ; %shf = lshr i32 %x, %y @@ -3681,10 +3680,9 @@ define i1 @icmp_and_or_lshr(i32 %x, i32 %y) { define i1 @icmp_and_or_lshr_samesign(i32 %x, i32 %y) { ; CHECK-LABEL: define i1 @icmp_and_or_lshr_samesign( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { -; CHECK-NEXT: [[SHF1:%.*]] = shl nuw i32 1, [[Y]] -; CHECK-NEXT: [[OR2:%.*]] = or i32 [[SHF1]], 1 -; CHECK-NEXT: [[AND3:%.*]] = and i32 [[X]], [[OR2]] -; CHECK-NEXT: [[RET:%.*]] = icmp ne i32 [[AND3]], 0 +; CHECK-NEXT: [[SHF:%.*]] = lshr i32 [[X]], [[Y]] +; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHF]], [[X]] +; CHECK-NEXT: [[RET:%.*]] = trunc i32 [[OR]] to i1 ; CHECK-NEXT: ret i1 [[RET]] ; %shf = lshr i32 %x, %y @@ -5217,8 +5215,7 @@ define <2 x i1> @zext_bool_and_eq0_commute(<2 x i1> %x, <2 x i8> %p) { define i1 @zext_bool_and_ne0(i1 %x, i8 %y) { ; CHECK-LABEL: define i1 @zext_bool_and_ne0( ; CHECK-SAME: i1 [[X:%.*]], i8 [[Y:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y]], 1 -; CHECK-NEXT: [[R1:%.*]] = icmp ne i8 [[TMP1]], 0 +; CHECK-NEXT: [[R1:%.*]] = trunc i8 [[Y]] to i1 ; CHECK-NEXT: [[R:%.*]] = select i1 [[X]], i1 [[R1]], i1 false ; CHECK-NEXT: ret i1 [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/intrinsic-select.ll b/llvm/test/Transforms/InstCombine/intrinsic-select.ll index c8f5a216ed534..aa4168918d939 100644 --- a/llvm/test/Transforms/InstCombine/intrinsic-select.ll +++ b/llvm/test/Transforms/InstCombine/intrinsic-select.ll @@ -532,3 +532,156 @@ define <2 x i8> @test_select_rotate_right_non_splat(i1 %0) { %ret = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %s, <2 x i8> %s, <2 x i8> ) ret <2 x i8> %ret } + +define i32 @select_of_ctpop(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_ctpop( +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[TMP1]]) +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctpop1 = call i32 @llvm.ctpop.i32(i32 %x) + %ctpop2 = call i32 @llvm.ctpop.i32(i32 %y) + %sel = select i1 %cond, i32 %ctpop1, i32 %ctpop2 + ret i32 %sel +} + +; Negative test: TV is not ctpop, should not transform +define i32 @select_of_ctpop_negative_tv(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_ctpop_negative_tv( +; CHECK-NEXT: [[CTPOP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 [[CTPOP2]] +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctpop1 = add i32 %x, 0 + %ctpop2 = call i32 @llvm.ctpop.i32(i32 %y) + %sel = select i1 %cond, i32 %ctpop1, i32 %ctpop2 + ret i32 %sel +} + +; Negative test: FV is not ctpop, should not transform +define i32 @select_of_ctpop_negative_fv(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_ctpop_negative_fv( +; CHECK-NEXT: [[CTPOP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 [[CTPOP1]], i32 [[X:%.*]] +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctpop1 = call i32 @llvm.ctpop.i32(i32 %y) + %ctpop2 = add i32 %x, 0 + %sel = select i1 %cond, i32 %ctpop1, i32 %ctpop2 + ret i32 %sel +} + +; Negative test: ctpop1 has multiple uses, don't transform +define i32 @select_of_ctpop_negative_multi_use(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_ctpop_negative_multi_use( +; CHECK-NEXT: [[CTPOP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) +; CHECK-NEXT: call void @use(i32 [[CTPOP1]]) +; CHECK-NEXT: [[CTPOP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 [[CTPOP1]], i32 [[CTPOP2]] +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctpop1 = call i32 @llvm.ctpop.i32(i32 %x) + call void @use(i32 %ctpop1) + %ctpop2 = call i32 @llvm.ctpop.i32(i32 %y) + %sel = select i1 %cond, i32 %ctpop1, i32 %ctpop2 + ret i32 %sel +} + +define <4 x i32> @select_of_ctpop_vec(<4 x i1> %cond, <4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @select_of_ctpop_vec( +; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[COND:%.*]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = call range(i32 0, 33) <4 x i32> @llvm.ctpop.v4i32(<4 x i32> [[TMP1]]) +; CHECK-NEXT: ret <4 x i32> [[SEL]] +; + %ctpop1 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %x) + %ctpop2 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %y) + %sel = select <4 x i1> %cond, <4 x i32> %ctpop1, <4 x i32> %ctpop2 + ret <4 x i32> %sel +} + +define i32 @select_of_ctlz(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_ctlz( +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false) +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctlz1 = call i32 @llvm.ctlz.i32(i32 %x, i1 false) + %ctlz2 = call i32 @llvm.ctlz.i32(i32 %y, i1 false) + %sel = select i1 %cond, i32 %ctlz1, i32 %ctlz2 + ret i32 %sel +} + +define i32 @select_of_ctlz_zero_poison_false(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_ctlz_zero_poison_false( +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false) +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctlz1 = call i32 @llvm.ctlz.i32(i32 %x, i1 false) + %ctlz2 = call i32 @llvm.ctlz.i32(i32 %y, i1 true) + %sel = select i1 %cond, i32 %ctlz1, i32 %ctlz2 + ret i32 %sel +} + +define i32 @select_of_ctlz_zero_poison_true(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_ctlz_zero_poison_true( +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 true) +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctlz1 = call i32 @llvm.ctlz.i32(i32 %x, i1 true) + %ctlz2 = call i32 @llvm.ctlz.i32(i32 %y, i1 true) + %sel = select i1 %cond, i32 %ctlz1, i32 %ctlz2 + ret i32 %sel +} + +; Negative test: ctlz1 has multiple uses, don't transform +define i32 @select_of_ctlz_negative_multi_use(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_ctlz_negative_multi_use( +; CHECK-NEXT: [[CTLZ1:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) +; CHECK-NEXT: call void @use(i32 [[CTLZ1]]) +; CHECK-NEXT: [[CTLZ2:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[Y:%.*]], i1 false) +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[COND:%.*]], i32 [[CTLZ1]], i32 [[CTLZ2]] +; CHECK-NEXT: ret i32 [[SEL]] +; + %ctlz1 = call i32 @llvm.ctlz.i32(i32 %x, i1 false) + call void @use(i32 %ctlz1) + %ctlz2 = call i32 @llvm.ctlz.i32(i32 %y, i1 false) + %sel = select i1 %cond, i32 %ctlz1, i32 %ctlz2 + ret i32 %sel +} + +define <4 x i32> @select_of_ctlz_vec(<4 x i1> %cond, <4 x i32> %x, <4 x i32> %y) { +; CHECK-LABEL: @select_of_ctlz_vec( +; CHECK-NEXT: [[CTLZ2:%.*]] = call range(i32 0, 33) <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[Y:%.*]], i1 false) +; CHECK-NEXT: ret <4 x i32> [[CTLZ2]] +; + %ctlz1 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x, i1 false) + %ctlz2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %y, i1 false) + %sel = select <4 x i1> %cond, <4 x i32> %ctlz2, <4 x i32> %ctlz2 + ret <4 x i32> %sel +} + +define i32 @select_of_cttz(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_cttz( +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP1]], i1 false) +; CHECK-NEXT: ret i32 [[SEL]] +; + %cttz1 = call i32 @llvm.cttz.i32(i32 %x, i1 false) + %cttz2 = call i32 @llvm.cttz.i32(i32 %y, i1 false) + %sel = select i1 %cond, i32 %cttz1, i32 %cttz2 + ret i32 %sel +} + +define i32 @select_of_abs(i1 %cond, i32 %x, i32 %y) { +; CHECK-LABEL: @select_of_abs( +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]] +; CHECK-NEXT: [[SEL:%.*]] = call i32 @llvm.abs.i32(i32 [[TMP1]], i1 false) +; CHECK-NEXT: ret i32 [[SEL]] +; + %abs1 = call i32 @llvm.abs.i32(i32 %x, i1 false) + %abs2 = call i32 @llvm.abs.i32(i32 %y, i1 false) + %sel = select i1 %cond, i32 %abs1, i32 %abs2 + ret i32 %sel +} diff --git a/llvm/test/Transforms/InstCombine/is_fpclass.ll b/llvm/test/Transforms/InstCombine/is_fpclass.ll index b86b307e4c7fd..70a7663e5768a 100644 --- a/llvm/test/Transforms/InstCombine/is_fpclass.ll +++ b/llvm/test/Transforms/InstCombine/is_fpclass.ll @@ -132,7 +132,7 @@ define <2 x i1> @test_class_is_p0_n0_v2f32(<2 x float> %x) { ret <2 x i1> %val } -define <2 x i1> @test_class_is_p0_n0_v2f32_daz(<2 x float> %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define <2 x i1> @test_class_is_p0_n0_v2f32_daz(<2 x float> %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_v2f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 96) ; CHECK-NEXT: ret <2 x i1> [[VAL]] @@ -141,7 +141,7 @@ define <2 x i1> @test_class_is_p0_n0_v2f32_daz(<2 x float> %x) "denormal-fp-math ret <2 x i1> %val } -define <2 x i1> @test_class_is_p0_n0_v2f32_dynamic(<2 x float> %x) "denormal-fp-math-f32"="ieee,dynamic" { +define <2 x i1> @test_class_is_p0_n0_v2f32_dynamic(<2 x float> %x) denormal_fpenv(float: ieee|dynamic) { ; CHECK-LABEL: @test_class_is_p0_n0_v2f32_dynamic( ; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 96) ; CHECK-NEXT: ret <2 x i1> [[VAL]] @@ -168,7 +168,7 @@ define <2 x i1> @test_class_is_p0_n0_or_nan_v2f32(<2 x float> %x) { ret <2 x i1> %val } -define i1 @test_class_is_p0_n0_or_nan_f32_daz(float %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define i1 @test_class_is_p0_n0_or_nan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_or_nan_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 99) ; CHECK-NEXT: ret i1 [[VAL]] @@ -177,7 +177,7 @@ define i1 @test_class_is_p0_n0_or_nan_f32_daz(float %x) "denormal-fp-math-f32"=" ret i1 %val } -define <2 x i1> @test_class_is_p0_n0_or_nan_v2f32_daz(<2 x float> %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define <2 x i1> @test_class_is_p0_n0_or_nan_v2f32_daz(<2 x float> %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_or_nan_v2f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 99) ; CHECK-NEXT: ret <2 x i1> [[VAL]] @@ -205,7 +205,7 @@ define <2 x i1> @test_class_is_p0_n0_or_sub_or_nan_v2f32(<2 x float> %x) { ret <2 x i1> %val } -define i1 @test_class_is_p0_n0_or_sub_or_nan_f32_daz(float %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define i1 @test_class_is_p0_n0_or_sub_or_nan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_or_sub_or_nan_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp ueq float [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: ret i1 [[VAL]] @@ -214,7 +214,7 @@ define i1 @test_class_is_p0_n0_or_sub_or_nan_f32_daz(float %x) "denormal-fp-math ret i1 %val } -define <2 x i1> @test_class_is_p0_n0_or_sub_or_nan_v2f32_daz(<2 x float> %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define <2 x i1> @test_class_is_p0_n0_or_sub_or_nan_v2f32_daz(<2 x float> %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_or_sub_or_nan_v2f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp ueq <2 x float> [[X:%.*]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[VAL]] @@ -223,7 +223,7 @@ define <2 x i1> @test_class_is_p0_n0_or_sub_or_nan_v2f32_daz(<2 x float> %x) "de ret <2 x i1> %val } -define i1 @test_class_is_p0_n0_or_sub_or_snan_f32_daz(float %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define i1 @test_class_is_p0_n0_or_sub_or_snan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_or_sub_or_snan_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 241) ; CHECK-NEXT: ret i1 [[VAL]] @@ -232,7 +232,7 @@ define i1 @test_class_is_p0_n0_or_sub_or_snan_f32_daz(float %x) "denormal-fp-mat ret i1 %val } -define i1 @test_class_is_p0_n0_or_sub_or_qnan_f32_daz(float %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define i1 @test_class_is_p0_n0_or_sub_or_qnan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_or_sub_or_qnan_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 242) ; CHECK-NEXT: ret i1 [[VAL]] @@ -268,7 +268,7 @@ define i1 @test_class_is_not_p0_n0_or_snan_f32(float %x) { ret i1 %val } -define i1 @test_class_is_not_p0_n0_or_nan_f32_daz(float %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define i1 @test_class_is_not_p0_n0_or_nan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_not_p0_n0_or_nan_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 924) ; CHECK-NEXT: ret i1 [[VAL]] @@ -286,7 +286,7 @@ define i1 @test_class_is_not_p0_n0_or_sub_or_nan_f32(float %x) { ret i1 %val } -define i1 @test_class_is_not_p0_n0_or_sub_or_nan_f32_daz(float %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define i1 @test_class_is_not_p0_n0_or_sub_or_nan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_not_p0_n0_or_sub_or_nan_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: ret i1 [[VAL]] @@ -304,7 +304,7 @@ define i1 @test_class_is_not_p0_n0_or_sub_and_not_nan_f32(float %x) { ret i1 %val } -define i1 @test_class_is_not_p0_n0_or_sub_and_not_nan_f32_daz(float %x) "denormal-fp-math-f32"="ieee,preserve-sign" { +define i1 @test_class_is_not_p0_n0_or_sub_and_not_nan_f32_daz(float %x) denormal_fpenv(float: ieee|preservesign) { ; CHECK-LABEL: @test_class_is_not_p0_n0_or_sub_and_not_nan_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp one float [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: ret i1 [[VAL]] @@ -340,7 +340,7 @@ define i1 @test_class_is_not_p0_n0_f32_strict(float %x) strictfp { ret i1 %val } -define i1 @test_class_is_not_p0_n0_f32_daz(float %x) "denormal-fp-math"="ieee,preserve-sign" { +define i1 @test_class_is_not_p0_n0_f32_daz(float %x) denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @test_class_is_not_p0_n0_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 927) ; CHECK-NEXT: ret i1 [[VAL]] @@ -349,7 +349,7 @@ define i1 @test_class_is_not_p0_n0_f32_daz(float %x) "denormal-fp-math"="ieee,pr ret i1 %val } -define i1 @test_class_is_not_p0_n0_f32_dynamic(float %x) "denormal-fp-math"="ieee,dynamic" { +define i1 @test_class_is_not_p0_n0_f32_dynamic(float %x) denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @test_class_is_not_p0_n0_f32_dynamic( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 927) ; CHECK-NEXT: ret i1 [[VAL]] @@ -358,7 +358,7 @@ define i1 @test_class_is_not_p0_n0_f32_dynamic(float %x) "denormal-fp-math"="iee ret i1 %val } -define i1 @test_class_is_not_p0_n0_psub_nsub_f32_daz(float %x) "denormal-fp-math"="ieee,preserve-sign" { +define i1 @test_class_is_not_p0_n0_psub_nsub_f32_daz(float %x) denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @test_class_is_not_p0_n0_psub_nsub_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: ret i1 [[VAL]] @@ -367,7 +367,7 @@ define i1 @test_class_is_not_p0_n0_psub_nsub_f32_daz(float %x) "denormal-fp-math ret i1 %val } -define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dapz(float %x) "denormal-fp-math"="ieee,positive-zero" { +define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dapz(float %x) denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @test_class_is_not_p0_n0_psub_nsub_f32_dapz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp une float [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: ret i1 [[VAL]] @@ -376,7 +376,7 @@ define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dapz(float %x) "denormal-fp-mat ret i1 %val } -define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dynamic(float %x) "denormal-fp-math"="ieee,dynamic" { +define i1 @test_class_is_not_p0_n0_psub_nsub_f32_dynamic(float %x) denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @test_class_is_not_p0_n0_psub_nsub_f32_dynamic( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 783) ; CHECK-NEXT: ret i1 [[VAL]] @@ -394,7 +394,7 @@ define i1 @test_class_is_p0_n0_f32_strict(float %x) strictfp { ret i1 %val } -define i1 @test_class_is_p0_n0_f32_daz(float %x) "denormal-fp-math"="ieee,preserve-sign" { +define i1 @test_class_is_p0_n0_f32_daz(float %x) denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) ; CHECK-NEXT: ret i1 [[VAL]] @@ -403,7 +403,7 @@ define i1 @test_class_is_p0_n0_f32_daz(float %x) "denormal-fp-math"="ieee,preser ret i1 %val } -define i1 @test_class_is_p0_n0_f32_dapz(float %x) "denormal-fp-math"="ieee,positive-zero" { +define i1 @test_class_is_p0_n0_f32_dapz(float %x) denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @test_class_is_p0_n0_f32_dapz( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) ; CHECK-NEXT: ret i1 [[VAL]] @@ -421,7 +421,7 @@ define i1 @test_class_is_p0_n0_psub_nsub_f32(float %x) { ret i1 %val } -define i1 @test_class_is_p0_n0_psub_nsub_f32_daz(float %x) "denormal-fp-math"="ieee,preserve-sign" { +define i1 @test_class_is_p0_n0_psub_nsub_f32_daz(float %x) denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: ret i1 [[VAL]] @@ -430,7 +430,7 @@ define i1 @test_class_is_p0_n0_psub_nsub_f32_daz(float %x) "denormal-fp-math"="i ret i1 %val } -define i1 @test_class_is_p0_n0_psub_nsub_f32_dapz(float %x) "denormal-fp-math"="ieee,positive-zero" { +define i1 @test_class_is_p0_n0_psub_nsub_f32_dapz(float %x) denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_f32_dapz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq float [[X:%.*]], 0.000000e+00 ; CHECK-NEXT: ret i1 [[VAL]] @@ -439,7 +439,7 @@ define i1 @test_class_is_p0_n0_psub_nsub_f32_dapz(float %x) "denormal-fp-math"=" ret i1 %val } -define i1 @test_class_is_p0_n0_psub_nsub_f32_dynamic(float %x) "denormal-fp-math"="ieee,dynamic" { +define i1 @test_class_is_p0_n0_psub_nsub_f32_dynamic(float %x) denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_f32_dynamic( ; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 240) ; CHECK-NEXT: ret i1 [[VAL]] @@ -457,7 +457,7 @@ define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32(<2 x float> %x) { ret <2 x i1> %val } -define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_daz(<2 x float> %x) "denormal-fp-math"="ieee,preserve-sign" { +define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_daz(<2 x float> %x) denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_v2f32_daz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq <2 x float> [[X:%.*]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[VAL]] @@ -466,7 +466,7 @@ define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_daz(<2 x float> %x) "denorm ret <2 x i1> %val } -define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_dapz(<2 x float> %x) "denormal-fp-math"="ieee,positive-zero" { +define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_dapz(<2 x float> %x) denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_v2f32_dapz( ; CHECK-NEXT: [[VAL:%.*]] = fcmp oeq <2 x float> [[X:%.*]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[VAL]] @@ -475,7 +475,7 @@ define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_dapz(<2 x float> %x) "denor ret <2 x i1> %val } -define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_dynamic(<2 x float> %x) "denormal-fp-math"="ieee,dynamic" { +define <2 x i1> @test_class_is_p0_n0_psub_nsub_v2f32_dynamic(<2 x float> %x) denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @test_class_is_p0_n0_psub_nsub_v2f32_dynamic( ; CHECK-NEXT: [[VAL:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> [[X:%.*]], i32 240) ; CHECK-NEXT: ret <2 x i1> [[VAL]] @@ -3961,7 +3961,7 @@ declare float @llvm.fabs.f32(float) declare <2 x float> @llvm.fabs.v2f32(<2 x float>) declare void @llvm.assume(i1 noundef) -attributes #0 = { "denormal-fp-math"="dynamic,ieee" } -attributes #1 = { "denormal-fp-math"="dynamic,preserve-sign" } -attributes #2 = { "denormal-fp-math"="dynamic,positive-zero" } -attributes #3 = { "denormal-fp-math"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(dynamic|ieee) } +attributes #1 = { denormal_fpenv(dynamic|preservesign) } +attributes #2 = { denormal_fpenv(dynamic|positivezero) } +attributes #3 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/load-cmp.ll b/llvm/test/Transforms/InstCombine/load-cmp.ll index 10fe07295eed6..a5a0681ac3af3 100644 --- a/llvm/test/Transforms/InstCombine/load-cmp.ll +++ b/llvm/test/Transforms/InstCombine/load-cmp.ll @@ -128,9 +128,8 @@ define i1 @test3_noarrayty(i32 %X) { define i1 @test4(i32 %X) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 1, [[X:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 933 -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 933, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = trunc i32 [[TMP1]] to i1 ; CHECK-NEXT: ret i1 [[R]] ; %P = getelementptr inbounds [10 x i16], ptr @G16, i32 0, i32 %X @@ -142,9 +141,8 @@ define i1 @test4(i32 %X) { define i1 @test4_i16(i16 %X) { ; CHECK-LABEL: @test4_i16( ; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i16 [[X:%.*]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 1, [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 933 -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP3]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 933, [[TMP1]] +; CHECK-NEXT: [[R:%.*]] = trunc i32 [[TMP2]] to i1 ; CHECK-NEXT: ret i1 [[R]] ; %P = getelementptr inbounds [10 x i16], ptr @G16, i32 0, i16 %X @@ -377,9 +375,8 @@ define i1 @pr93017(i64 %idx) { ; Mask is 0b10101010 define i1 @load_vs_array_type_mismatch1(i32 %idx) { ; CHECK-LABEL: @load_vs_array_type_mismatch1( -; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 1, [[TMP1:%.*]] -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 170 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP3]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 170, [[IDX:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[TMP1]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %gep = getelementptr inbounds i16, ptr @g_i32_lo, i32 %idx @@ -393,9 +390,8 @@ define i1 @load_vs_array_type_mismatch1(i32 %idx) { ; Mask is 0b01010101 define i1 @load_vs_array_type_mismatch2(i32 %idx) { ; CHECK-LABEL: @load_vs_array_type_mismatch2( -; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 1, [[TMP1:%.*]] -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 85 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP3]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 85, [[IDX:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = trunc i32 [[TMP1]] to i1 ; CHECK-NEXT: ret i1 [[CMP]] ; %gep = getelementptr inbounds i16, ptr @g_i32_hi, i32 %idx @@ -492,9 +488,8 @@ define i1 @cmp_load_constant_array_messy(i32 %x){ ; CHECK-LABEL: @cmp_load_constant_array_messy( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0:%.*]], 1073741823 -; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 1, [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 373 -; CHECK-NEXT: [[COND:%.*]] = icmp ne i32 [[TMP3]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 373, [[TMP1]] +; CHECK-NEXT: [[COND:%.*]] = trunc i32 [[TMP2]] to i1 ; CHECK-NEXT: ret i1 [[COND]] ; @@ -508,9 +503,8 @@ entry: define i1 @cmp_diff_load_constant_array_messy0(i32 %x){ ; CHECK-LABEL: @cmp_diff_load_constant_array_messy0( ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1:%.*]], 1073741823 -; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 1, [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], 373 -; CHECK-NEXT: [[COND:%.*]] = icmp ne i32 [[TMP4]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = lshr i32 373, [[TMP2]] +; CHECK-NEXT: [[COND:%.*]] = trunc i32 [[TMP3]] to i1 ; CHECK-NEXT: ret i1 [[COND]] ; %isOK_ptr = getelementptr i32, ptr @CG_MESSY, i32 %x diff --git a/llvm/test/Transforms/InstCombine/log-to-intrinsic.ll b/llvm/test/Transforms/InstCombine/log-to-intrinsic.ll index 273d44c091919..527dc6e138440 100644 --- a/llvm/test/Transforms/InstCombine/log-to-intrinsic.ll +++ b/llvm/test/Transforms/InstCombine/log-to-intrinsic.ll @@ -291,7 +291,7 @@ return: } !0 = !{ float 2.5 } -define float @test_logf_pos_denormalpreserve(float %f) "denormal-fp-math"="preserve-sign,preserve-sign" { +define float @test_logf_pos_denormalpreserve(float %f) denormal_fpenv(preservesign) { ; CHECK-LABEL: define float @test_logf_pos_denormalpreserve( ; CHECK-SAME: float [[F:%.*]]) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[ENTRY:.*:]] @@ -315,7 +315,7 @@ return: ret float 0.0 } -define float @test_logf_pos_denormaldynamic(float %f) "denormal-fp-math"="dynamic,dynamic" { +define float @test_logf_pos_denormaldynamic(float %f) denormal_fpenv(dynamic) { ; CHECK-LABEL: define float @test_logf_pos_denormaldynamic( ; CHECK-SAME: float [[F:%.*]]) #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: [[ENTRY:.*:]] diff --git a/llvm/test/Transforms/InstCombine/maxnum.ll b/llvm/test/Transforms/InstCombine/maxnum.ll index 67fb7a90b3d49..5e275627414cb 100644 --- a/llvm/test/Transforms/InstCombine/maxnum.ll +++ b/llvm/test/Transforms/InstCombine/maxnum.ll @@ -402,11 +402,9 @@ define float @reduce_precision_fmf(float %x, float %y) { define float @reduce_precision_multi_use_0(float %x, float %y, ptr %p) { ; CHECK-LABEL: @reduce_precision_multi_use_0( -; CHECK-NEXT: [[X_EXT:%.*]] = fpext float [[X:%.*]] to double ; CHECK-NEXT: [[Y_EXT:%.*]] = fpext float [[Y:%.*]] to double -; CHECK-NEXT: store double [[X_EXT]], ptr [[P:%.*]], align 8 -; CHECK-NEXT: [[MAXNUM:%.*]] = call double @llvm.maxnum.f64(double [[X_EXT]], double [[Y_EXT]]) -; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[MAXNUM]] to float +; CHECK-NEXT: store double [[Y_EXT]], ptr [[P:%.*]], align 8 +; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.maxnum.f32(float [[Y]], float [[Y1:%.*]]) ; CHECK-NEXT: ret float [[TRUNC]] ; %x.ext = fpext float %x to double @@ -419,11 +417,9 @@ define float @reduce_precision_multi_use_0(float %x, float %y, ptr %p) { define float @reduce_precision_multi_use_1(float %x, float %y, ptr %p) { ; CHECK-LABEL: @reduce_precision_multi_use_1( -; CHECK-NEXT: [[X_EXT:%.*]] = fpext float [[X:%.*]] to double ; CHECK-NEXT: [[Y_EXT:%.*]] = fpext float [[Y:%.*]] to double ; CHECK-NEXT: store double [[Y_EXT]], ptr [[P:%.*]], align 8 -; CHECK-NEXT: [[MAXNUM:%.*]] = call double @llvm.maxnum.f64(double [[X_EXT]], double [[Y_EXT]]) -; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[MAXNUM]] to float +; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.maxnum.f32(float [[X:%.*]], float [[Y]]) ; CHECK-NEXT: ret float [[TRUNC]] ; %x.ext = fpext float %x to double @@ -434,6 +430,25 @@ define float @reduce_precision_multi_use_1(float %x, float %y, ptr %p) { ret float %trunc } +define float @reduce_precision_multi_use_2(float %x, float %y, ptr %p, ptr %p2) { +; CHECK-LABEL: @reduce_precision_multi_use_2( +; CHECK-NEXT: [[X_EXT:%.*]] = fpext float [[X:%.*]] to double +; CHECK-NEXT: [[Y_EXT:%.*]] = fpext float [[Y:%.*]] to double +; CHECK-NEXT: store double [[X_EXT]], ptr [[P:%.*]], align 8 +; CHECK-NEXT: store double [[Y_EXT]], ptr [[P2:%.*]], align 8 +; CHECK-NEXT: [[MAXNUM:%.*]] = call double @llvm.maxnum.f64(double [[X_EXT]], double [[Y_EXT]]) +; CHECK-NEXT: [[MAXNUM1:%.*]] = fptrunc double [[MAXNUM]] to float +; CHECK-NEXT: ret float [[MAXNUM1]] +; + %x.ext = fpext float %x to double + %y.ext = fpext float %y to double + store double %x.ext, ptr %p + store double %y.ext, ptr %p2 + %maxnum = call double @llvm.maxnum.f64(double %x.ext, double %y.ext) + %trunc = fptrunc double %maxnum to float + ret float %trunc +} + define float @negated_op(float %x) { ; CHECK-LABEL: @negated_op( ; CHECK-NEXT: [[R:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]]) diff --git a/llvm/test/Transforms/InstCombine/minnum.ll b/llvm/test/Transforms/InstCombine/minnum.ll index cc6171b9d8e6c..7ac83bf91163e 100644 --- a/llvm/test/Transforms/InstCombine/minnum.ll +++ b/llvm/test/Transforms/InstCombine/minnum.ll @@ -439,11 +439,9 @@ define float @reduce_precision_fmf(float %x, float %y) { define float @reduce_precision_multi_use_0(float %x, float %y, ptr %p) { ; CHECK-LABEL: @reduce_precision_multi_use_0( -; CHECK-NEXT: [[X_EXT:%.*]] = fpext float [[X:%.*]] to double ; CHECK-NEXT: [[Y_EXT:%.*]] = fpext float [[Y:%.*]] to double -; CHECK-NEXT: store double [[X_EXT]], ptr [[P:%.*]], align 8 -; CHECK-NEXT: [[MINNUM:%.*]] = call double @llvm.minnum.f64(double [[X_EXT]], double [[Y_EXT]]) -; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[MINNUM]] to float +; CHECK-NEXT: store double [[Y_EXT]], ptr [[P:%.*]], align 8 +; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.minnum.f32(float [[Y]], float [[Y1:%.*]]) ; CHECK-NEXT: ret float [[TRUNC]] ; %x.ext = fpext float %x to double @@ -456,11 +454,9 @@ define float @reduce_precision_multi_use_0(float %x, float %y, ptr %p) { define float @reduce_precision_multi_use_1(float %x, float %y, ptr %p) { ; CHECK-LABEL: @reduce_precision_multi_use_1( -; CHECK-NEXT: [[X_EXT:%.*]] = fpext float [[X:%.*]] to double ; CHECK-NEXT: [[Y_EXT:%.*]] = fpext float [[Y:%.*]] to double ; CHECK-NEXT: store double [[Y_EXT]], ptr [[P:%.*]], align 8 -; CHECK-NEXT: [[MINNUM:%.*]] = call double @llvm.minnum.f64(double [[X_EXT]], double [[Y_EXT]]) -; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[MINNUM]] to float +; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float [[Y]]) ; CHECK-NEXT: ret float [[TRUNC]] ; %x.ext = fpext float %x to double @@ -471,6 +467,64 @@ define float @reduce_precision_multi_use_1(float %x, float %y, ptr %p) { ret float %trunc } +define float @reduce_precision_multi_use_2(float %x, float %y, ptr %p, ptr %p2) { +; CHECK-LABEL: @reduce_precision_multi_use_2( +; CHECK-NEXT: [[X_EXT:%.*]] = fpext float [[X:%.*]] to double +; CHECK-NEXT: [[Y_EXT:%.*]] = fpext float [[Y:%.*]] to double +; CHECK-NEXT: store double [[X_EXT]], ptr [[P:%.*]], align 8 +; CHECK-NEXT: store double [[Y_EXT]], ptr [[P2:%.*]], align 8 +; CHECK-NEXT: [[MINNUM:%.*]] = call double @llvm.minnum.f64(double [[X_EXT]], double [[Y_EXT]]) +; CHECK-NEXT: [[MINNUM1:%.*]] = fptrunc double [[MINNUM]] to float +; CHECK-NEXT: ret float [[MINNUM1]] +; + %x.ext = fpext float %x to double + %y.ext = fpext float %y to double + store double %x.ext, ptr %p + store double %y.ext, ptr %p2 + %minnum = call double @llvm.minnum.f64(double %x.ext, double %y.ext) + %trunc = fptrunc double %minnum to float + ret float %trunc +} + +define float @reduce_precision_const(float %x) { +; CHECK-LABEL: @reduce_precision_const( +; CHECK-NEXT: [[TRUNC:%.*]] = call float @llvm.minnum.f32(float [[X:%.*]], float 1.000000e+00) +; CHECK-NEXT: ret float [[TRUNC]] +; + %x.ext = fpext float %x to double + %minnum = call double @llvm.minnum.f64(double %x.ext, double 1.0) + %trunc = fptrunc double %minnum to float + ret float %trunc +} + +define float @reduce_precision_const_not_lossless(float %x) { +; CHECK-LABEL: @reduce_precision_const_not_lossless( +; CHECK-NEXT: [[X_EXT:%.*]] = fpext float [[X:%.*]] to double +; CHECK-NEXT: [[MINNUM:%.*]] = call double @llvm.minnum.f64(double [[X_EXT]], double 1.000000e-01) +; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[MINNUM]] to float +; CHECK-NEXT: ret float [[TRUNC]] +; + %x.ext = fpext float %x to double + %minnum = call double @llvm.minnum.f64(double %x.ext, double 0.1) + %trunc = fptrunc double %minnum to float + ret float %trunc +} + +define float @reduce_precision_const_multi_use(float %x) { +; CHECK-LABEL: @reduce_precision_const_multi_use( +; CHECK-NEXT: [[X_EXT:%.*]] = fpext float [[X:%.*]] to double +; CHECK-NEXT: call void @use(double [[X_EXT]]) +; CHECK-NEXT: [[MINNUM:%.*]] = call double @llvm.minnum.f64(double [[X_EXT]], double 1.000000e+00) +; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[MINNUM]] to float +; CHECK-NEXT: ret float [[TRUNC]] +; + %x.ext = fpext float %x to double + call void @use(double %x.ext) + %minnum = call double @llvm.minnum.f64(double %x.ext, double 1.0) + %trunc = fptrunc double %minnum to float + ret float %trunc +} + define float @negated_op(float %x) { ; CHECK-LABEL: @negated_op( ; CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]]) diff --git a/llvm/test/Transforms/InstCombine/or.ll b/llvm/test/Transforms/InstCombine/or.ll index f61a1970d3aa4..64797d4d111a1 100644 --- a/llvm/test/Transforms/InstCombine/or.ll +++ b/llvm/test/Transforms/InstCombine/or.ll @@ -2038,8 +2038,7 @@ define i32 @or_xor_and_commuted3(i32 %x, i32 %y, i32 %z) { define i1 @or_truncs(i8 %x) { ; CHECK-LABEL: @or_truncs( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[OR1:%.*]] = icmp ne i8 [[TMP1]], 0 +; CHECK-NEXT: [[OR1:%.*]] = trunc i8 [[X:%.*]] to i1 ; CHECK-NEXT: ret i1 [[OR1]] ; %trunc1 = trunc i8 %x to i1 diff --git a/llvm/test/Transforms/InstCombine/rem-mul-shl.ll b/llvm/test/Transforms/InstCombine/rem-mul-shl.ll index 920497c07e380..6bb46cbf2022e 100644 --- a/llvm/test/Transforms/InstCombine/rem-mul-shl.ll +++ b/llvm/test/Transforms/InstCombine/rem-mul-shl.ll @@ -903,8 +903,8 @@ define i64 @urem_shl_vscale_overlap() vscale_range(1,16) { ; CHECK-LABEL: @urem_shl_vscale_overlap( ; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 10 -; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[SHIFT]], 2047 -; CHECK-NEXT: [[REM:%.*]] = and i64 [[TMP1]], 1024 +; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[SHIFT]], 1024 +; CHECK-NEXT: [[REM:%.*]] = xor i64 [[TMP1]], 1024 ; CHECK-NEXT: ret i64 [[REM]] ; %vscale = call i64 @llvm.vscale.i64() @@ -930,7 +930,7 @@ define i64 @and_add_shl_vscale_not_power2() vscale_range(1,16) { ; CHECK-LABEL: @and_add_shl_vscale_not_power2( ; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64() ; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 6 -; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[SHIFT]], 4095 +; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[SHIFT]], 4032 ; CHECK-NEXT: [[REM:%.*]] = and i64 [[ADD]], 3072 ; CHECK-NEXT: ret i64 [[REM]] ; diff --git a/llvm/test/Transforms/InstCombine/saturating-add-sub.ll b/llvm/test/Transforms/InstCombine/saturating-add-sub.ll index 80676de47f193..efa89db4af61a 100644 --- a/llvm/test/Transforms/InstCombine/saturating-add-sub.ll +++ b/llvm/test/Transforms/InstCombine/saturating-add-sub.ll @@ -2708,6 +2708,141 @@ define i8 @neg_neg_constant(i8 %x, i8 %y) { ret i8 %s } +; +; Negative constant signed saturated add - saturates to INT_MIN +; + +; Basic pattern: (x <= threshold) ? INT_MIN : (x + C) where C < 0 +; threshold should be INT_MIN - C or INT_MIN - C + 1 + +; (x <= -119) ? -128 : (x + -10) --> sadd.sat(x, -10) +define i8 @sadd_sat_neg_constant(i8 %x) { +; CHECK-LABEL: @sadd_sat_neg_constant( +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[X:%.*]], i8 -10) +; CHECK-NEXT: ret i8 [[R]] +; + %cmp = icmp sle i8 %x, -119 + %add = add i8 %x, -10 + %r = select i1 %cmp, i8 -128, i8 %add + ret i8 %r +} + +; (x < -118) ? -128 : (x + -10) --> sadd.sat(x, -10) +define i8 @sadd_sat_neg_constant_slt(i8 %x) { +; CHECK-LABEL: @sadd_sat_neg_constant_slt( +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[X:%.*]], i8 -10) +; CHECK-NEXT: ret i8 [[R]] +; + %cmp = icmp slt i8 %x, -118 + %add = add i8 %x, -10 + %r = select i1 %cmp, i8 -128, i8 %add + ret i8 %r +} + +; Commuted select: (x >= threshold) ? (x + C) : INT_MIN --> sadd.sat(x, C) +define i8 @sadd_sat_neg_constant_commuted_select(i8 %x) { +; CHECK-LABEL: @sadd_sat_neg_constant_commuted_select( +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[X:%.*]], i8 -10) +; CHECK-NEXT: ret i8 [[R]] +; + %cmp = icmp sge i8 %x, -118 + %add = add i8 %x, -10 + %r = select i1 %cmp, i8 %add, i8 -128 + ret i8 %r +} + +; sle minimum signed value is canonicalized to eq and requires special handling +; (x == INT_MIN) ? INT_MIN : x + -1 --> sadd.sat(x, -1) +define i8 @sadd_sat_eq_int_min(i8 %x) { +; CHECK-LABEL: @sadd_sat_eq_int_min( +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[X:%.*]], i8 -1) +; CHECK-NEXT: ret i8 [[R]] +; + %cmp = icmp eq i8 %x, -128 + %add = add i8 %x, -1 + %r = select i1 %cmp, i8 -128, i8 %add + ret i8 %r +} + +; Vector version of negative constant pattern +define <2 x i8> @sadd_sat_neg_constant_vector(<2 x i8> %x) { +; CHECK-LABEL: @sadd_sat_neg_constant_vector( +; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[X:%.*]], <2 x i8> splat (i8 -10)) +; CHECK-NEXT: ret <2 x i8> [[R]] +; + %cmp = icmp sle <2 x i8> %x, + %add = add <2 x i8> %x, + %r = select <2 x i1> %cmp, <2 x i8> , <2 x i8> %add + ret <2 x i8> %r +} + +; Pattern with variable: (INT_MIN - X > Y) ? INT_MIN : (X + Y) with nsw sub +define i8 @sadd_sat_int_min_minus_x_nsw(i8 %x, i8 %y) { +; CHECK-LABEL: @sadd_sat_int_min_minus_x_nsw( +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[X:%.*]], i8 [[Y:%.*]]) +; CHECK-NEXT: ret i8 [[R]] +; + %sub = sub nsw i8 -128, %x + %cmp = icmp sgt i8 %sub, %y + %add = add i8 %x, %y + %r = select i1 %cmp, i8 -128, i8 %add + ret i8 %r +} + +; Negative test: wrong saturation value +define i8 @sadd_sat_neg_constant_wrong_sat_value(i8 %x) { +; CHECK-LABEL: @sadd_sat_neg_constant_wrong_sat_value( +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], -118 +; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X]], -10 +; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i8 -127, i8 [[ADD]] +; CHECK-NEXT: ret i8 [[R]] +; + %cmp = icmp sle i8 %x, -119 + %add = add i8 %x, -10 + %r = select i1 %cmp, i8 -127, i8 %add + ret i8 %r +} + +; Boundary case: threshold allows exact match at the saturation limit +define i8 @sadd_sat_neg_constant_boundary(i8 %x) { +; CHECK-LABEL: @sadd_sat_neg_constant_boundary( +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[X:%.*]], i8 -10) +; CHECK-NEXT: ret i8 [[R]] +; + %cmp = icmp sle i8 %x, -118 + %add = add i8 %x, -10 + %r = select i1 %cmp, i8 -128, i8 %add + ret i8 %r +} + +; Negative test: threshold too high +define i8 @sadd_sat_neg_constant_wrong_threshold(i8 %x) { +; CHECK-LABEL: @sadd_sat_neg_constant_wrong_threshold( +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], -116 +; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X]], -10 +; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i8 -128, i8 [[ADD]] +; CHECK-NEXT: ret i8 [[R]] +; + %cmp = icmp sle i8 %x, -117 + %add = add i8 %x, -10 + %r = select i1 %cmp, i8 -128, i8 %add + ret i8 %r +} + +; Negative test: positive constant (should use INT_MAX saturation, not INT_MIN) +define i8 @sadd_sat_neg_pattern_positive_constant(i8 %x) { +; CHECK-LABEL: @sadd_sat_neg_pattern_positive_constant( +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], -118 +; CHECK-NEXT: [[ADD:%.*]] = add i8 [[X]], 10 +; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP]], i8 -128, i8 [[ADD]] +; CHECK-NEXT: ret i8 [[R]] +; + %cmp = icmp sle i8 %x, -119 + %add = add i8 %x, 10 + %r = select i1 %cmp, i8 -128, i8 %add + ret i8 %r +} + ; Make sure we don't crash in this case. define i32 @pr153053_strict_pred_with_nonconstant_rhs(i32 %x, i32 %y) { ; CHECK-LABEL: @pr153053_strict_pred_with_nonconstant_rhs( diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll index c134833630338..006b06cfc7669 100644 --- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll +++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll @@ -100,8 +100,7 @@ define i1 @n2(i64 %y, i32 %len) { ; New shift amount would be 16, %y has 47 leading zeros - can fold. define i1 @t3(i32 %x, i32 %len) { ; CHECK-LABEL: @t3( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1 -; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[X:%.*]] to i1 ; CHECK-NEXT: ret i1 [[T5]] ; %t0 = sub i32 32, %len @@ -117,8 +116,7 @@ define i1 @t3(i32 %x, i32 %len) { ; Note that we indeed look at leading zeros! define i1 @t3_singlebit(i32 %x, i32 %len) { ; CHECK-LABEL: @t3_singlebit( -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1 -; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[X:%.*]] to i1 ; CHECK-NEXT: ret i1 [[T5]] ; %t0 = sub i32 32, %len diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll index 6f4e78e9f91a0..2c508c0c47472 100644 --- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll +++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-shl.ll @@ -278,8 +278,7 @@ define i1 @t8_oneuse5(i32 %x, i64 %y, i32 %len) { ; CHECK-NEXT: call void @use64(i64 [[T3]]) ; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32 ; CHECK-NEXT: call void @use32(i32 [[T3_TRUNC]]) -; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[Y]], 1 -; CHECK-NEXT: [[T5:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[T5:%.*]] = trunc i64 [[Y]] to i1 ; CHECK-NEXT: ret i1 [[T5]] ; %t0 = sub i32 32, %len diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll index e95955da1b872..64ef1936fc2c1 100644 --- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll +++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest.ll @@ -534,8 +534,7 @@ define i1 @t32_shift_of_const_oneuse0(i32 %x, i32 %y, i32 %len) { ; CHECK-NEXT: call void @use32(i32 [[T2]]) ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[Y:%.*]], [[T2]] ; CHECK-NEXT: call void @use32(i32 [[T3]]) -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[Y]], 1 -; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[Y]] to i1 ; CHECK-NEXT: ret i1 [[T5]] ; %t0 = sub i32 32, %len @@ -674,12 +673,11 @@ define i1 @constantexpr() { ; CHECK-LABEL: @constantexpr( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @f.a, align 2 -; CHECK-NEXT: [[SHR:%.*]] = lshr i16 [[TMP0]], 1 +; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[TMP0]], 1 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i16 ptrtoint (ptr @f.a to i16), 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i16 -; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i16 1, [[ZEXT]] -; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[SHR]], [[TMP1]] -; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i16 [[TMP2]], 0 +; CHECK-NEXT: [[SHR11:%.*]] = lshr i16 [[SHR]], [[ZEXT]] +; CHECK-NEXT: [[TOBOOL:%.*]] = trunc i16 [[SHR11]] to i1 ; CHECK-NEXT: ret i1 [[TOBOOL]] ; entry: diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll index 4cd51c8b36f46..ce5bdfb2a4973 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-canonicalize.ll @@ -586,6 +586,20 @@ define nofpclass(nan) float @ret_nofpclass_nan__canonicalize_drop_noundef(float ret float %canon } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #2 = { "denormal-fp-math"="positive-zero,positive-zero" } +define nofpclass(snan) float @qnan_result_demands_snan_src(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.canonicalize.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.canonicalize.f32(float %select) + ret float %result +} + +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } +attributes #2 = { denormal_fpenv(positivezero|positivezero) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll index f3c8abddda115..311c8ce7a1a26 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-exp.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 6 ; RUN: opt -S -passes=instcombine < %s | FileCheck %s +declare nofpclass(qnan inf norm sub zero) float @returns_snan() + define nofpclass(pinf) float @ret_nofpclass_pinf__exp2_select_maybe_inf_or_not_pinf(i1 %cond, float %maybe.inf, float nofpclass(pinf) %not.pinf) { ; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__exp2_select_maybe_inf_or_not_pinf( ; CHECK-SAME: i1 [[COND:%.*]], float [[MAYBE_INF:%.*]], float nofpclass(pinf) [[NOT_PINF:%.*]]) { @@ -603,6 +605,20 @@ define nofpclass(nan inf) float @ret_no_inf_no_nan__exp__no_inf(float nofpclass( ret float %exp } +define nofpclass(snan) float @qnan_result_demands_snan_src(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.exp.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.exp.f32(float %select) + ret float %result +} + !0 = !{!"function_entry_count", i64 1000} ;. ; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll index ea75dcd33c9c4..eee3405e9b8cf 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fadd.ll @@ -20,6 +20,7 @@ declare nofpclass(nan ninf nzero nsub nnorm) half @returns_positive() declare nofpclass(nan pinf pzero psub pnorm) half @returns_negative() declare nofpclass(inf zero sub norm) half @returns_nan() +declare nofpclass(qnan inf zero sub norm) half @returns_snan() declare nofpclass(nan inf zero sub) half @returns_norm() declare nofpclass(nan inf zero sub pnorm) half @returns_nnorm() @@ -2043,9 +2044,51 @@ define nofpclass(snan) half @inf_or_nan__fadd__not_nan(half nofpclass(nan) %not. ret half %result } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #2 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #3 = { "denormal-fp-math"="preserve-sign,ieee" } -attributes #4 = { "denormal-fp-math"="ieee,positive-zero" } -attributes #5 = { "denormal-fp-math"="positive-zero,ieee" } +define nofpclass(snan) half @qnan_result_self_demands_snan(i1 noundef %cond, half noundef %unknown) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_self_demands_snan( +; CHECK-SAME: i1 noundef [[COND:%.*]], half noundef [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call noundef half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = fadd half [[SELECT]], [[SELECT]] +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call noundef half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown + %result = fadd half %select, %select + ret half %result +} + +define nofpclass(snan) half @qnan_result_demands_snan_lhs(i1 %cond, half %unknown0, half %unknown1) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = fadd half [[SELECT]], [[UNKNOWN1]] +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = fadd half %select, %unknown1 + ret half %result +} + +define nofpclass(snan) half @qnan_result_demands_snan_rhs(i1 %cond, half %unknown0, half %unknown1) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = fadd half [[UNKNOWN1]], [[SELECT]] +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = fadd half %unknown1, %select + ret half %result +} + +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } +attributes #2 = { denormal_fpenv(ieee|preservesign) } +attributes #3 = { denormal_fpenv(preservesign|ieee) } +attributes #4 = { denormal_fpenv(ieee|positivezero) } +attributes #5 = { denormal_fpenv(positivezero|ieee) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll index ea06ccb4a3fb7..dc31cd9a37922 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fdiv.ll @@ -11,6 +11,7 @@ declare nofpclass(nan inf norm nsub zero) half @returns_psub() declare nofpclass(nan inf norm psub zero) half @returns_nsub() declare nofpclass(nan inf sub zero) half @returns_norm() declare nofpclass(nan norm sub zero) half @returns_inf() +declare nofpclass(qnan inf norm sub zero) half @returns_snan() declare void @use(half) define nofpclass(pinf) half @ret_nofpclass_pinf__fdiv_unknown_or_pinf(i1 %cond, half %x, half %y) { @@ -2295,17 +2296,45 @@ define nofpclass(inf norm sub zero) half @nan_result_demands_subnorm_rhs__dynami ret half %div } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } -attributes #2 = { "denormal-fp-math"="ieee,preserve-sign" } -attributes #3 = { "denormal-fp-math"="ieee,dynamic" } +define nofpclass(snan) half @qnan_result_demands_snan_src_lhs(i1 %cond, half %unknown0, half %unknown1) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_src_lhs( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[MUL:%.*]] = fdiv half [[SELECT]], [[UNKNOWN1]] +; CHECK-NEXT: ret half [[MUL]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %div = fdiv half %select, %unknown1 + ret half %div +} + +define nofpclass(snan) half @qnan_result_demands_snan_src_rhs(i1 %cond, half %unknown0, half %unknown1) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_src_rhs( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[MUL:%.*]] = fdiv half [[UNKNOWN1]], [[SELECT]] +; CHECK-NEXT: ret half [[MUL]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %div = fdiv half %unknown1, %select + ret half %div +} + +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } +attributes #2 = { denormal_fpenv(ieee|preservesign) } +attributes #3 = { denormal_fpenv(ieee|dynamic) } !0 = !{!"function_entry_count", i64 1000} ;. -; CHECK: attributes #[[ATTR0]] = { "denormal-fp-math"="ieee,preserve-sign" } -; CHECK: attributes #[[ATTR1]] = { "denormal-fp-math"="preserve-sign,preserve-sign" } -; CHECK: attributes #[[ATTR2]] = { "denormal-fp-math"="dynamic,dynamic" } -; CHECK: attributes #[[ATTR3]] = { "denormal-fp-math"="ieee,dynamic" } +; CHECK: attributes #[[ATTR0]] = { denormal_fpenv(ieee|preservesign) } +; CHECK: attributes #[[ATTR1]] = { denormal_fpenv(preservesign) } +; CHECK: attributes #[[ATTR2]] = { denormal_fpenv(dynamic) } +; CHECK: attributes #[[ATTR3]] = { denormal_fpenv(ieee|dynamic) } ; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) } ;. ; CHECK: [[PROF0]] = !{!"function_entry_count", i64 1000} diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll index 4837856cfb18b..6f914c98c16ec 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fma.ll @@ -2,6 +2,7 @@ ; RUN: opt -S -passes=instcombine < %s | FileCheck %s declare nofpclass(inf norm sub zero) half @returns_nan() +declare nofpclass(qnan inf norm sub zero) half @returns_snan() define nofpclass(inf norm sub zero) half @ret_only_nan(half %x, half %y, half %z) { ; CHECK-LABEL: define nofpclass(inf zero sub norm) half @ret_only_nan( @@ -292,9 +293,74 @@ define nofpclass(nan inf) half @ret_nonan_noinf__fma_square__no_nan_no_inf_all_s ret half %result } +define nofpclass(snan) half @qnan_result_demands_snan_square_src0(i1 noundef %cond, half noundef %unknown0, half noundef %unknown1) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_square_src0( +; CHECK-SAME: i1 noundef [[COND:%.*]], half noundef [[UNKNOWN0:%.*]], half noundef [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call half @llvm.fma.f16(half [[SELECT]], half [[SELECT]], half [[UNKNOWN1]]) +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = call half @llvm.fma.f16(half %select, half %select, half %unknown1) + ret half %result +} -!0 = !{} +define nofpclass(snan) half @qnan_result_demands_snan_square_src1(i1 noundef %cond, half noundef %unknown0, half noundef %unknown1) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_square_src1( +; CHECK-SAME: i1 noundef [[COND:%.*]], half noundef [[UNKNOWN0:%.*]], half noundef [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call half @llvm.fma.f16(half [[UNKNOWN1]], half [[UNKNOWN1]], half [[SELECT]]) +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = call half @llvm.fma.f16(half %unknown1, half %unknown1, half %select) + ret half %result +} +define nofpclass(snan) half @qnan_result_demands_snan_src0(i1 %cond, half %unknown0, half %unknown1, half %unknown2) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_src0( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]], half [[UNKNOWN2:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call half @llvm.fma.f16(half [[SELECT]], half [[UNKNOWN1]], half [[UNKNOWN2]]) +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = call half @llvm.fma.f16(half %select, half %unknown1, half %unknown2) + ret half %result +} +define nofpclass(snan) half @qnan_result_demands_snan_src1(i1 %cond, half %unknown0, half %unknown1, half %unknown2) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_src1( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]], half [[UNKNOWN2:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call half @llvm.fma.f16(half [[UNKNOWN1]], half [[SELECT]], half [[UNKNOWN2]]) +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = call half @llvm.fma.f16(half %unknown1, half %select, half %unknown2) + ret half %result +} +define nofpclass(snan) half @qnan_result_demands_snan_src2(i1 %cond, half %unknown0, half %unknown1, half %unknown2) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_src2( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]], half [[UNKNOWN2:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call half @llvm.fma.f16(half [[UNKNOWN1]], half [[UNKNOWN2]], half [[SELECT]]) +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = call half @llvm.fma.f16(half %unknown1, half %unknown2, half %select) + ret half %result +} +!0 = !{} diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll index c40200f819e7d..80c0d20a4ca95 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fmul.ll @@ -7,6 +7,7 @@ declare nofpclass(nan inf pzero sub norm) float @returns_nzero() declare nofpclass(nan inf zero sub nnorm) float @returns_pnorm() declare nofpclass(nan inf norm zero) float @returns_sub() declare nofpclass(nan inf sub zero) float @returns_norm() +declare nofpclass(qnan inf norm sub zero) float @returns_snan() declare void @use(float) ; No inf result implies no inf inputs. @@ -1402,5 +1403,47 @@ define nofpclass(nan inf sub zero) float @norm_result_demands_sub_source_rhs(i1 ret float %mul } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } +define nofpclass(snan) float @qnan_result_square_demands_snan(i1 noundef %cond, float noundef %unknown0) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_square_demands_snan( +; CHECK-SAME: i1 noundef [[COND:%.*]], float noundef [[UNKNOWN0:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call noundef float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[MUL:%.*]] = fmul float [[SELECT]], [[SELECT]] +; CHECK-NEXT: ret float [[MUL]] +; + %snan = call noundef float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %mul = fmul float %select, %select + ret float %mul +} + +define nofpclass(snan) float @qnan_result_demands_snan_lhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[MUL:%.*]] = fmul float [[SELECT]], [[UNKNOWN1]] +; CHECK-NEXT: ret float [[MUL]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %mul = fmul float %select, %unknown1 + ret float %mul +} + +define nofpclass(snan) float @qnan_result_demands_snan_rhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[MUL:%.*]] = fmul float [[UNKNOWN1]], [[SELECT]] +; CHECK-NEXT: ret float [[MUL]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %mul = fmul float %unknown1, %select + ret float %mul +} + +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll index d138885efd0e6..7ff6e6f179673 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fpext.ll @@ -2,6 +2,7 @@ ; RUN: opt -S -passes=instcombine < %s | FileCheck %s declare nofpclass(inf norm sub zero) half @returns_nan_f16() +declare nofpclass(qnan inf norm sub zero) half @returns_snan_f16() declare nofpclass(nan ninf norm sub zero) half @returns_pinf_f16() declare nofpclass(nan pinf norm sub zero) half @returns_ninf_f16() declare nofpclass(nan norm sub zero) half @returns_inf_f16() @@ -470,3 +471,17 @@ define nofpclass(zero) float @ret_no_zero__fpext__select_zero_or_unknown(i1 %con %result = fpext half %select to float ret float %result } + +define nofpclass(snan) float @qnan_result_demands_snan_src(i1 %cond, half %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan_f16() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = fpext half [[SELECT]] to float +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call half @returns_snan_f16() + %select = select i1 %cond, half %snan, half %unknown + %result = fpext half %select to float + ret float %result +} diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll index 7ec16b0d9dc96..d4f84348530e6 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc-round.ll @@ -2,6 +2,7 @@ ; RUN: opt -S -passes=instcombine < %s | FileCheck %s declare nofpclass(inf norm sub zero) float @returns_nan_f32() +declare nofpclass(qnan inf norm sub zero) float @returns_snan_f32() declare nofpclass(nan ninf norm sub zero) float @returns_pinf_f32() declare nofpclass(nan pinf norm sub zero) float @returns_ninf_f32() declare nofpclass(nan norm sub zero) float @returns_inf_f32() @@ -617,3 +618,17 @@ define nofpclass(nan) half @ret_no_nan__fptrunc_drop_noundef(float %x) { %result = call noundef half @llvm.fptrunc.round.f16.f32(float %x, metadata !"round.downward"), !unknown.md !{} ret half %result } + +define nofpclass(snan) half @qnan_result_demands_snan_src2(i1 %cond, float %unknown0) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_src2( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan_f32() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call half @llvm.fptrunc.round.f16.f32(float [[SELECT]], metadata !"round.downward") +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call float @returns_snan_f32() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call half @llvm.fptrunc.round.f16.f32(float %select, metadata !"round.downward") + ret half %result +} diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll index c06e190728a3f..a291b3b06d6ed 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fptrunc.ll @@ -2,6 +2,7 @@ ; RUN: opt -S -passes=instcombine < %s | FileCheck %s declare nofpclass(inf norm sub zero) float @returns_nan_f32() +declare nofpclass(qnan inf norm sub zero) float @returns_snan_f32() declare nofpclass(nan ninf norm sub zero) float @returns_pinf_f32() declare nofpclass(nan pinf norm sub zero) float @returns_ninf_f32() declare nofpclass(nan norm sub zero) float @returns_inf_f32() @@ -605,3 +606,17 @@ define nofpclass(inf norm sub) half @zero_demands_norm_source(i1 %cond, float %u %result = fptrunc float %select to half ret half %result } + +define nofpclass(snan) half @qnan_result_demands_snan_src2(i1 %cond, float %unknown0) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_src2( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan_f32() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = fptrunc float [[SELECT]] to half +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call float @returns_snan_f32() + %select = select i1 %cond, float %snan, float %unknown0 + %result = fptrunc float %select to half + ret half %result +} diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-frexp.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-frexp.ll index 5cebd6ccd2c10..ee431d216b41f 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-frexp.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-frexp.ll @@ -610,3 +610,17 @@ define nofpclass(inf) half @multiple_extract_uses(i1 %cond, half %unknown, ptr n store half %frexp.mant2, ptr %ptr ret half %frexp.mant } + +define nofpclass(snan) half @qnan_result_demands_snan_src(i1 %cond, half %unknown, half nofpclass(qnan inf norm sub zero) %only.snan) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_src( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN:%.*]], half nofpclass(qnan inf zero sub norm) [[ONLY_SNAN:%.*]]) { +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[UNKNOWN]], half [[ONLY_SNAN]] +; CHECK-NEXT: [[FREXP:%.*]] = call { half, i32 } @llvm.frexp.f16.i32(half [[SELECT]]) +; CHECK-NEXT: [[FREXP_MANT:%.*]] = extractvalue { half, i32 } [[FREXP]], 0 +; CHECK-NEXT: ret half [[FREXP_MANT]] +; + %select = select i1 %cond, half %unknown, half %only.snan + %frexp = call { half, i32 } @llvm.frexp.f16.i32(half %select) + %frexp.mant = extractvalue { half, i32 } %frexp, 0 + ret half %frexp.mant +} diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll index c5ed839b08aaa..88cbb7d86c1e7 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-fsub.ll @@ -20,6 +20,7 @@ declare nofpclass(nan ninf nzero nsub nnorm) half @returns_positive() declare nofpclass(nan pinf pzero psub pnorm) half @returns_negative() declare nofpclass(inf zero sub norm) half @returns_nan() +declare nofpclass(qnan inf zero sub norm) half @returns_snan() declare nofpclass(nan inf zero sub) half @returns_norm() declare nofpclass(nan inf zero sub pnorm) half @returns_nnorm() @@ -1204,5 +1205,33 @@ define nofpclass(snan) half @ret_no_snan__known_negative__fsub__known_positive() ret half %result } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } +define nofpclass(snan) half @qnan_result_demands_snan_lhs(i1 %cond, half %unknown0, half %unknown1) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = fsub half [[SELECT]], [[UNKNOWN1]] +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = fsub half %select, %unknown1 + ret half %result +} + +define nofpclass(snan) half @qnan_result_demands_snan_rhs(i1 %cond, half %unknown0, half %unknown1) { +; CHECK-LABEL: define nofpclass(snan) half @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], half [[UNKNOWN0:%.*]], half [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call half @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], half [[SNAN]], half [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = fsub half [[UNKNOWN1]], [[SELECT]] +; CHECK-NEXT: ret half [[RESULT]] +; + %snan = call half @returns_snan() + %select = select i1 %cond, half %snan, half %unknown0 + %result = fsub half %unknown1, %select + ret half %result +} + +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll index e3bbab6d2d53c..6f9f20f12a007 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-log.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 ; RUN: opt -S -passes=instcombine < %s | FileCheck %s +declare nofpclass(qnan inf norm sub zero) float @returns_snan() + ; -> qnan, canonicalizing define nofpclass(inf norm sub zero) float @ret_nofpclass_only_nan__log(float %unknown) { ; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_nofpclass_only_nan__log( @@ -351,7 +353,23 @@ define nofpclass(inf nan) float @add_flags_log__drop_noundef(float nofpclass(inf ret float %result } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } +define nofpclass(snan) float @qnan_result_demands_snan_src(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.log.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.log.f32(float %select) + ret float %result +} + +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } !0 = !{} + + diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll index b6a6e63af8acb..420588bce238a 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximum.ll @@ -20,6 +20,7 @@ declare nofpclass(inf sub norm pzero) float @returns_nzero_or_nan() declare nofpclass(inf sub norm nan nzero) float @returns_pzero() declare nofpclass(inf sub norm nzero) float @returns_pzero_or_nan() declare nofpclass(inf norm sub zero) float @returns_nan() +declare nofpclass(qnan inf norm sub zero) float @returns_snan() declare nofpclass(ninf norm sub zero nan) float @returns_pinf() declare nofpclass(ninf norm sub zero) float @returns_pinf_or_nan() @@ -2102,7 +2103,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_0__mul ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) ; CHECK-NEXT: store float [[RESULT]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MUST_BE_POSITIVE_OR_ZERO]] +; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_negative_or_zero() %must.be.positive.or.zero = call float @returns_positive_or_zero() @@ -2118,7 +2119,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1__mul ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() ; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_NEGATIVE_OR_ZERO]]) ; CHECK-NEXT: store float [[RESULT]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MUST_BE_POSITIVE_OR_ZERO]] +; CHECK-NEXT: ret float [[RESULT]] ; %must.be.positive.or.zero = call float @returns_positive_or_zero() %must.be.negative.or.zero = call float @returns_negative_or_zero() @@ -2159,7 +2160,35 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1__ ret float %result } +define nofpclass(snan) float @qnan_result_demands_snan_lhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maximum.f32(float [[SELECT]], float [[UNKNOWN1]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.maximum.f32(float %select, float %unknown1) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_rhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maximum.f32(float [[UNKNOWN1]], float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.maximum.f32(float %unknown1, float %select) + ret float %result +} + !0 = !{} -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll index 2589d80a256d6..7c36c3eb871a6 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maximumnum.ll @@ -20,6 +20,7 @@ declare nofpclass(inf sub norm pzero) float @returns_nzero_or_nan() declare nofpclass(inf sub norm nan nzero) float @returns_pzero() declare nofpclass(inf sub norm nzero) float @returns_pzero_or_nan() declare nofpclass(inf norm sub zero) float @returns_nan() +declare nofpclass(qnan inf norm sub zero) float @returns_snan() declare nofpclass(ninf norm sub zero nan) float @returns_pinf() declare nofpclass(ninf norm sub zero) float @returns_pinf_or_nan() @@ -2107,7 +2108,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_0__mul ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) ; CHECK-NEXT: store float [[RESULT]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MUST_BE_POSITIVE_OR_ZERO]] +; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_negative_or_zero() %must.be.positive.or.zero = call float @returns_positive_or_zero() @@ -2123,7 +2124,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1__mul ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maximumnum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_NEGATIVE_OR_ZERO]]) ; CHECK-NEXT: store float [[RESULT]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MUST_BE_POSITIVE_OR_ZERO]] +; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_negative_or_zero() %must.be.positive.or.zero = call float @returns_positive_or_zero() @@ -2164,7 +2165,35 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1__ ret float %result } +define nofpclass(snan) float @qnan_result_demands_snan_lhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maximumnum.f32(float [[SELECT]], float [[UNKNOWN1]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.maximumnum.f32(float %select, float %unknown1) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_rhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maximumnum.f32(float [[UNKNOWN1]], float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.maximumnum.f32(float %unknown1, float %select) + ret float %result +} + !0 = !{} -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll index 62fb47646365f..ddd316baa1fd5 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-maxnum.ll @@ -20,6 +20,7 @@ declare nofpclass(inf sub norm pzero) float @returns_nzero_or_nan() declare nofpclass(inf sub norm nan nzero) float @returns_pzero() declare nofpclass(inf sub norm nzero) float @returns_pzero_or_nan() declare nofpclass(inf norm sub zero) float @returns_nan() +declare nofpclass(qnan inf norm sub zero) float @returns_snan() declare nofpclass(ninf norm sub zero nan) float @returns_pinf() declare nofpclass(ninf norm sub zero) float @returns_pinf_or_nan() @@ -49,8 +50,7 @@ declare nofpclass(ninf nnorm nsub zero) float @returns_positive_nonzero_or_nan() define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) { ; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan( ; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[X]], float [[Y]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF8000000000000 ; %result = call float @llvm.maxnum.f32(float %x, float %y) ret float %result @@ -59,7 +59,7 @@ define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) { define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y) { ; CHECK-LABEL: define nofpclass(qnan inf zero sub norm) float @ret_only_snan( ; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[X]], float [[Y]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[X]], float [[Y]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %x, float %y) @@ -69,8 +69,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y) { ; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan( ; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[X]], float [[Y]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF8000000000000 ; %result = call float @llvm.maxnum.f32(float %x, float %y) ret float %result @@ -79,7 +78,7 @@ define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y define nofpclass(nan norm sub zero) float @ret_only_inf(float %x, float %y) { ; CHECK-LABEL: define nofpclass(nan zero sub norm) float @ret_only_inf( ; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[X]], float [[Y]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[X]], float [[Y]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %x, float %y) @@ -167,8 +166,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_known_positive_or_nan__maxnum ; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_known_positive_or_nan__maxnum__negative_or_nan___negative_or_nan() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN0:%.*]] = call float @returns_negative_or_nan() ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN1:%.*]] = call float @returns_negative_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_NEGATIVE_OR_NAN0]], float [[MUST_BE_NEGATIVE_OR_NAN1]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF8000000000000 ; %must.be.negative.or.nan0 = call float @returns_negative_or_nan() %must.be.negative.or.nan1 = call float @returns_negative_or_nan() @@ -181,8 +179,7 @@ define nofpclass(pinf pnorm psub pzero) float @ret_known_negative_or_nan__maxnum ; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_known_negative_or_nan__maxnum__positive_or_nan___positive_or_nan() { ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN0:%.*]] = call float @returns_positive_or_nan() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN1:%.*]] = call float @returns_positive_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_POSITIVE_OR_NAN0]], float [[MUST_BE_POSITIVE_OR_NAN1]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF8000000000000 ; %must.be.positive.or.nan0 = call float @returns_positive_or_nan() %must.be.positive.or.nan1 = call float @returns_positive_or_nan() @@ -367,7 +364,7 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_0() ; CHECK-LABEL: define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_0() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.maxnum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_positive_or_zero() @@ -381,7 +378,7 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1() ; CHECK-LABEL: define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_NEGATIVE_OR_ZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.maxnum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_NEGATIVE_OR_ZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_positive_or_zero() @@ -394,8 +391,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_0() { ; CHECK-LABEL: define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_0() { ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO1:%.*]] = call float @returns_positive_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO1]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[MUST_BE_POSITIVE_OR_ZERO1]] ; %must.be.negative.or.zero = call float @returns_negative_or_zero() %must.be.positive.or.zero = call float @returns_positive_or_zero() @@ -407,8 +403,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1() { ; CHECK-LABEL: define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[MUST_BE_NEGATIVE_OR_ZERO]] ; %must.be.positive.or.zero = call float @returns_positive_or_zero() %must.be.negative.or.zero = call float @returns_negative_or_zero() @@ -419,7 +414,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1() { define nofpclass(nsub) float @lhs_must_be_pinf_or_nan(float %unknown, float nofpclass(ninf norm zero sub) %must.be.pinf.or.nan) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(ninf zero sub norm) [[MUST_BE_PINF_OR_NAN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_PINF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[MUST_BE_PINF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %must.be.pinf.or.nan, float %unknown) @@ -429,7 +424,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf_or_nan(float %unknown, float nofp define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm zero sub) %must.be.pinf.or.nan, float %unknown) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf_or_nan( ; CHECK-SAME: float nofpclass(ninf zero sub norm) [[MUST_BE_PINF_OR_NAN:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[MUST_BE_PINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float [[MUST_BE_PINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %unknown, float %must.be.pinf.or.nan) @@ -439,8 +434,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(nan ninf norm zero sub) %must.be.pinf) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_PINF]], float [[UNKNOWN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %result = call float @llvm.maxnum.f32(float %must.be.pinf, float %unknown) ret float %result @@ -449,8 +443,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(n define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float %unknown) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf( ; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[MUST_BE_PINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %result = call float @llvm.maxnum.f32(float %unknown, float %must.be.pinf) ret float %result @@ -460,8 +453,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zer define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan ninf norm zero sub) %must.be.pinf) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_PINF]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %result = call float @llvm.maxnum.f32(float %must.be.pinf, float %not.nan) ret float %result @@ -471,8 +463,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan) define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float nofpclass(nan) %not.nan) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan( ; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN]], float [[MUST_BE_PINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %result = call float @llvm.maxnum.f32(float %not.nan, float %must.be.pinf) ret float %result @@ -481,7 +472,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(float nofpclass(nan n define nofpclass(nsub) float @lhs_must_be_ninf_or_nan(float %unknown, float nofpclass(pinf norm zero sub) %must.be.ninf.or.nan) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(pinf zero sub norm) [[MUST_BE_NINF_OR_NAN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_NINF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[MUST_BE_NINF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %must.be.ninf.or.nan, float %unknown) @@ -491,7 +482,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf_or_nan(float %unknown, float nofp define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm zero sub) %must.be.ninf.or.nan, float %unknown) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf_or_nan( ; CHECK-SAME: float nofpclass(pinf zero sub norm) [[MUST_BE_NINF_OR_NAN:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[MUST_BE_NINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float [[MUST_BE_NINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %unknown, float %must.be.ninf.or.nan) @@ -501,7 +492,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(nan pinf norm zero sub) %must.be.ninf) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_NINF]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %must.be.ninf, float %unknown) @@ -511,7 +502,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(n define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float %unknown) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf( ; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[MUST_BE_NINF]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %unknown, float %must.be.ninf) @@ -523,8 +514,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zer define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan pinf norm zero sub) %must.be.ninf) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[MUST_BE_NINF]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %result = call float @llvm.maxnum.f32(float %must.be.ninf, float %not.nan) ret float %result @@ -534,8 +524,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan) define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float nofpclass(nan) %not.nan) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan( ; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN]], float [[MUST_BE_NINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %result = call float @llvm.maxnum.f32(float %not.nan, float %must.be.ninf) ret float %result @@ -564,7 +553,7 @@ define nofpclass(pzero) float @result_not_pzero(float %unknown0, float %unknown1 define nofpclass(zero) float @result_not_zero(float %unknown0, float %unknown1) { ; CHECK-LABEL: define nofpclass(zero) float @result_not_zero( ; CHECK-SAME: float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %unknown0, float %unknown1) @@ -594,7 +583,7 @@ define nofpclass(zero) float @result_not_zero__dynamic(float %unknown0, float %u define nofpclass(zero) float @result_not_zero_or_sub(float %unknown0, float %unknown1) { ; CHECK-LABEL: define nofpclass(zero) float @result_not_zero_or_sub( ; CHECK-SAME: float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %unknown0, float %unknown1) @@ -604,7 +593,7 @@ define nofpclass(zero) float @result_not_zero_or_sub(float %unknown0, float %unk define nofpclass(zero sub) float @result_not_zero_or_sub__daz(float %unknown0, float %unknown1) #0 { ; CHECK-LABEL: define nofpclass(zero sub) float @result_not_zero_or_sub__daz( ; CHECK-SAME: float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %unknown0, float %unknown1) @@ -614,7 +603,7 @@ define nofpclass(zero sub) float @result_not_zero_or_sub__daz(float %unknown0, f define nofpclass(zero sub) float @result_not_zero_or_sub__dynamic(float %unknown0, float %unknown1) #1 { ; CHECK-LABEL: define nofpclass(zero sub) float @result_not_zero_or_sub__dynamic( ; CHECK-SAME: float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %unknown0, float %unknown1) @@ -624,7 +613,7 @@ define nofpclass(zero sub) float @result_not_zero_or_sub__dynamic(float %unknown define nofpclass(snan) float @lhs_not_zero(float nofpclass(zero) %not.zero, float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @lhs_not_zero( ; CHECK-SAME: float nofpclass(zero) [[NOT_ZERO:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_ZERO]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_ZERO]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.zero, float %unknown) @@ -634,7 +623,7 @@ define nofpclass(snan) float @lhs_not_zero(float nofpclass(zero) %not.zero, floa define nofpclass(snan) float @rhs_not_zero(float %unknown, float nofpclass(zero) %not.zero) { ; CHECK-LABEL: define nofpclass(snan) float @rhs_not_zero( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[NOT_ZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float [[NOT_ZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %unknown, float %not.zero) @@ -644,7 +633,7 @@ define nofpclass(snan) float @rhs_not_zero(float %unknown, float nofpclass(zero) define nofpclass(snan) float @sources_not_zero(float nofpclass(zero) %not.zero0, float nofpclass(zero) %not.zero1) { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_zero( ; CHECK-SAME: float nofpclass(zero) [[NOT_ZERO0:%.*]], float nofpclass(zero) [[NOT_ZERO1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_ZERO0]], float [[NOT_ZERO1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_ZERO0]], float [[NOT_ZERO1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.zero0, float %not.zero1) @@ -674,7 +663,7 @@ define nofpclass(snan) float @sources_not_zero__dynamic(float nofpclass(zero) %n define nofpclass(snan) float @sources_not_zero_or_sub(float nofpclass(zero sub) %not.zero.sub.0, float nofpclass(zero sub) %not.zero.sub.1) { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_zero_or_sub( ; CHECK-SAME: float nofpclass(zero sub) [[NOT_ZERO_SUB_0:%.*]], float nofpclass(zero sub) [[NOT_ZERO_SUB_1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.zero.sub.0, float %not.zero.sub.1) @@ -684,7 +673,7 @@ define nofpclass(snan) float @sources_not_zero_or_sub(float nofpclass(zero sub) define nofpclass(snan) float @sources_not_zero_or_sub__daz(float nofpclass(zero sub) %not.zero.sub.0, float nofpclass(zero sub) %not.zero.sub.1) #1 { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_zero_or_sub__daz( ; CHECK-SAME: float nofpclass(zero sub) [[NOT_ZERO_SUB_0:%.*]], float nofpclass(zero sub) [[NOT_ZERO_SUB_1:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.zero.sub.0, float %not.zero.sub.1) @@ -694,7 +683,7 @@ define nofpclass(snan) float @sources_not_zero_or_sub__daz(float nofpclass(zero define nofpclass(snan) float @sources_not_zero_or_sub__dynamic(float nofpclass(zero sub) %not.zero.sub.0, float nofpclass(zero sub) %not.zero.sub.1) #1 { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_zero_or_sub__dynamic( ; CHECK-SAME: float nofpclass(zero sub) [[NOT_ZERO_SUB_0:%.*]], float nofpclass(zero sub) [[NOT_ZERO_SUB_1:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.zero.sub.0, float %not.zero.sub.1) @@ -704,7 +693,7 @@ define nofpclass(snan) float @sources_not_zero_or_sub__dynamic(float nofpclass(z define nofpclass(snan) float @sources_not_nzero(float nofpclass(nzero) %not.nzero0, float nofpclass(nzero) %not.nzero1) { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_nzero( ; CHECK-SAME: float nofpclass(nzero) [[NOT_NZERO0:%.*]], float nofpclass(nzero) [[NOT_NZERO1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NZERO0]], float [[NOT_NZERO1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_NZERO0]], float [[NOT_NZERO1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.nzero0, float %not.nzero1) @@ -714,7 +703,7 @@ define nofpclass(snan) float @sources_not_nzero(float nofpclass(nzero) %not.nzer define nofpclass(snan) float @sources_not_pzero(float nofpclass(pzero) %not.pzero0, float nofpclass(pzero) %not.pzero1) { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_pzero( ; CHECK-SAME: float nofpclass(pzero) [[NOT_PZERO0:%.*]], float nofpclass(pzero) [[NOT_PZERO1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_PZERO0]], float [[NOT_PZERO1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_PZERO0]], float [[NOT_PZERO1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.pzero0, float %not.pzero1) @@ -784,7 +773,7 @@ define nofpclass(snan) float @rhs_not_nzero_lhs_not_pzero__dynamic(float nofpcla define nofpclass(snan) float @sources_not_nzero_nsub__dynamic(float nofpclass(nzero nsub) %not.nzero0, float nofpclass(nzero nsub) %not.nzero1) #1 { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_nzero_nsub__dynamic( ; CHECK-SAME: float nofpclass(nzero nsub) [[NOT_NZERO0:%.*]], float nofpclass(nzero nsub) [[NOT_NZERO1:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NZERO0]], float [[NOT_NZERO1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_NZERO0]], float [[NOT_NZERO1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.nzero0, float %not.nzero1) @@ -844,7 +833,7 @@ define nofpclass(snan) float @unknown__maxnum__not_nan(float %x, float nofpclass define nofpclass(snan) float @not_nan__maxnum__not_nan(float nofpclass(nan) %x, float nofpclass(nan) %y) { ; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[X:%.*]], float nofpclass(nan) [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[X]], float [[Y]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.maxnum.f32(float [[X]], float [[Y]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %x, float %y) @@ -875,8 +864,7 @@ define nofpclass(snan) float @known_positive__maxnum__only_zero() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive__maxnum__only_zero() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_ZERO:%.*]] = call float @returns_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_ZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.positive = call float @returns_positive() %known.zero = call float @returns_zero() @@ -888,8 +876,7 @@ define nofpclass(snan) float @only_zero__maxnum__known_positive() { ; CHECK-LABEL: define nofpclass(snan) float @only_zero__maxnum__known_positive() { ; CHECK-NEXT: [[KNOWN_ZERO:%.*]] = call float @returns_zero() ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_ZERO]], float [[KNOWN_POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.zero = call float @returns_zero() %known.positive = call float @returns_positive() @@ -901,8 +888,7 @@ define nofpclass(snan) float @known_positive__maxnum__only_zero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive__maxnum__only_zero_or_nan() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_ZERO_OR_NAN:%.*]] = call float @returns_zero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_ZERO_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.positive = call float @returns_positive() %known.zero.or.nan = call float @returns_zero_or_nan() @@ -914,8 +900,7 @@ define nofpclass(snan) float @only_zero_or_nan__maxnum__known_positive() { ; CHECK-LABEL: define nofpclass(snan) float @only_zero_or_nan__maxnum__known_positive() { ; CHECK-NEXT: [[KNOWN_ZERO_OR_NAN:%.*]] = call float @returns_zero_or_nan() ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_ZERO_OR_NAN]], float [[KNOWN_POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.zero.or.nan = call float @returns_zero_or_nan() %known.positive = call float @returns_positive() @@ -953,8 +938,7 @@ define nofpclass(snan) float @known_positive__maxnum__only_nzero() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive__maxnum__only_nzero() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_NZERO:%.*]] = call float @returns_nzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_NZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.positive = call float @returns_positive() %known.nzero = call float @returns_nzero() @@ -966,8 +950,7 @@ define nofpclass(snan) float @only_nzero__maxnum__known_positive() { ; CHECK-LABEL: define nofpclass(snan) float @only_nzero__maxnum__known_positive() { ; CHECK-NEXT: [[KNOWN_NZERO:%.*]] = call float @returns_nzero() ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_NZERO]], float [[KNOWN_POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.nzero = call float @returns_nzero() %known.positive = call float @returns_positive() @@ -979,8 +962,7 @@ define nofpclass(snan) float @known_positive__maxnum__only_pzero() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive__maxnum__only_pzero() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_PZERO:%.*]] = call float @returns_pzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_PZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.positive = call float @returns_positive() %known.pzero = call float @returns_pzero() @@ -992,8 +974,7 @@ define nofpclass(snan) float @only_pzero__maxnum__known_positive() { ; CHECK-LABEL: define nofpclass(snan) float @only_pzero__maxnum__known_positive() { ; CHECK-NEXT: [[KNOWN_PZERO:%.*]] = call float @returns_pzero() ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_PZERO]], float [[KNOWN_POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.pzero = call float @returns_pzero() %known.positive = call float @returns_positive() @@ -1031,8 +1012,7 @@ define nofpclass(snan) float @known_negative_or_nan__maxnum__only_zero() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative_or_nan__maxnum__only_zero() { ; CHECK-NEXT: [[KNOWN_NEGATIVE_OR_NAN:%.*]] = call float @returns_negative_or_nan() ; CHECK-NEXT: [[KNOWN_ZERO:%.*]] = call float @returns_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_NEGATIVE_OR_NAN]], float [[KNOWN_ZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_ZERO]] ; %known.negative.or.nan = call float @returns_negative_or_nan() %known.zero = call float @returns_zero() @@ -1044,8 +1024,7 @@ define nofpclass(snan) float @only_zero__maxnum__known_negative_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @only_zero__maxnum__known_negative_or_nan() { ; CHECK-NEXT: [[KNOWN_ZERO:%.*]] = call float @returns_zero() ; CHECK-NEXT: [[KNOWN_NEGATIVE_OR_NAN:%.*]] = call float @returns_negative_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_ZERO]], float [[KNOWN_NEGATIVE_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_ZERO]] ; %known.zero = call float @returns_zero() %known.negative.or.nan = call float @returns_negative_or_nan() @@ -1081,7 +1060,7 @@ define nofpclass(snan) float @known_negative__maxnum__only_nzero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative__maxnum__only_nzero_or_nan() { ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[KNOWN_NZERO_OR_NAN:%.*]] = call float @returns_nzero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_NEGATIVE]], float [[KNOWN_NZERO_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[KNOWN_NEGATIVE]], float [[KNOWN_NZERO_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %known.negative = call float @returns_negative() @@ -1094,7 +1073,7 @@ define nofpclass(snan) float @only_nzero_or_nan__maxnum__known_negative() { ; CHECK-LABEL: define nofpclass(snan) float @only_nzero_or_nan__maxnum__known_negative() { ; CHECK-NEXT: [[KNOWN_NZERO_OR_NAN:%.*]] = call float @returns_nzero_or_nan() ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_NZERO_OR_NAN]], float [[KNOWN_NEGATIVE]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[KNOWN_NZERO_OR_NAN]], float [[KNOWN_NEGATIVE]]) ; CHECK-NEXT: ret float [[RESULT]] ; %known.nzero.or.nan = call float @returns_nzero_or_nan() @@ -1107,8 +1086,7 @@ define nofpclass(snan) float @known_negative__maxnum__only_pzero() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative__maxnum__only_pzero() { ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[KNOWN_PZERO:%.*]] = call float @returns_pzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_NEGATIVE]], float [[KNOWN_PZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0.000000e+00 ; %known.negative = call float @returns_negative() %known.pzero = call float @returns_pzero() @@ -1120,8 +1098,7 @@ define nofpclass(snan) float @only_pzero__maxnum__known_negative() { ; CHECK-LABEL: define nofpclass(snan) float @only_pzero__maxnum__known_negative() { ; CHECK-NEXT: [[KNOWN_PZERO:%.*]] = call float @returns_pzero() ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_PZERO]], float [[KNOWN_NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0.000000e+00 ; %known.pzero = call float @returns_pzero() %known.negative = call float @returns_negative() @@ -1188,7 +1165,7 @@ define nofpclass(pinf pnorm psub) float @ret_always_positive_nonzero__maxnum__no ; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) { ; CHECK-NEXT: [[ALWAYS_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[SELECT_RHS:%.*]] = select i1 [[COND]], float [[ALWAYS_POSITIVE]], float [[UNKNOWN]] -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_ZERO]], float [[SELECT_RHS]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_ZERO]], float [[SELECT_RHS]]) ; CHECK-NEXT: ret float [[RESULT]] ; %always.positive = call float @returns_positive() @@ -1202,7 +1179,7 @@ define nofpclass(pinf pnorm psub) float @ret_always_positive_nonzero__maxnum__no ; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) { ; CHECK-NEXT: [[ALWAYS_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[SELECT_RHS:%.*]] = select i1 [[COND]], float [[ALWAYS_NEGATIVE]], float [[UNKNOWN]] -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_ZERO]], float [[SELECT_RHS]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_ZERO]], float [[SELECT_RHS]]) ; CHECK-NEXT: ret float [[RESULT]] ; %always.negative = call float @returns_negative() @@ -1215,8 +1192,7 @@ define nofpclass(snan) float @known_positive__maxnum__only_pzero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive__maxnum__only_pzero_or_nan() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_PZERO_OR_NAN:%.*]] = call float @returns_pzero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_PZERO_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.positive = call float @returns_positive() %known.pzero.or.nan = call float @returns_pzero_or_nan() @@ -1302,8 +1278,7 @@ define nofpclass(snan) float @known_always_positive__maxnum__known_always_negati ; CHECK-LABEL: define nofpclass(snan) float @known_always_positive__maxnum__known_always_negative_or_nan() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_NEGATIVE_OR_NAN:%.*]] = call float @returns_negative_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_NEGATIVE_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.positive = call float @returns_positive() %known.negative.or.nan = call float @returns_negative_or_nan() @@ -1315,8 +1290,7 @@ define nofpclass(snan) float @known_always_negative_or_nan__maxnum__known_always ; CHECK-LABEL: define nofpclass(snan) float @known_always_negative_or_nan__maxnum__known_always_positive() { ; CHECK-NEXT: [[KNOWN_NEGATIVE_OR_NAN:%.*]] = call float @returns_negative_or_nan() ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[KNOWN_NEGATIVE_OR_NAN]], float [[KNOWN_POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_POSITIVE]] ; %known.negative.or.nan = call float @returns_negative_or_nan() %known.positive = call float @returns_positive() @@ -1380,8 +1354,7 @@ define nofpclass(snan) float @pinf__maxnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @pinf__maxnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[PINF]], float [[UNKNOWN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %pinf = call float @returns_pinf() %result = call float @llvm.maxnum.f32(float %pinf, float %unknown) @@ -1392,8 +1365,7 @@ define nofpclass(snan) float @unknown__maxnum__pinf(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__maxnum__pinf( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[PINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %pinf = call float @returns_pinf() %result = call float @llvm.maxnum.f32(float %unknown, float %pinf) @@ -1404,7 +1376,7 @@ define nofpclass(snan) float @pinf_or_nan__maxnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @pinf_or_nan__maxnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[PINF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[PINF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %pinf.or.nan = call float @returns_pinf_or_nan() @@ -1416,7 +1388,7 @@ define nofpclass(snan) float @unknown__maxnum__pinf_or_nan(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__maxnum__pinf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[PINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float [[PINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %pinf.or.nan = call float @returns_pinf_or_nan() @@ -1428,7 +1400,7 @@ define nofpclass(snan) float @ninf__maxnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @ninf__maxnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NINF]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000) ; CHECK-NEXT: ret float [[RESULT]] ; %ninf = call float @returns_ninf() @@ -1440,7 +1412,7 @@ define nofpclass(snan) float @unknown__maxnum__ninf(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__maxnum__ninf( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[NINF]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float 0xFFF0000000000000) ; CHECK-NEXT: ret float [[RESULT]] ; %ninf = call float @returns_ninf() @@ -1452,7 +1424,7 @@ define nofpclass(snan) float @ninf_or_nan__maxnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @ninf_or_nan__maxnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NINF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NINF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %ninf.or.nan = call float @returns_ninf_or_nan() @@ -1464,7 +1436,7 @@ define nofpclass(snan) float @unknown__maxnum__ninf_or_nan(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__maxnum__ninf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[NINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float [[NINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %ninf.or.nan = call float @returns_ninf_or_nan() @@ -1476,7 +1448,7 @@ define nofpclass(snan) float @inf__maxnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @inf__maxnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[INF:%.*]] = call float @returns_inf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[INF]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[INF]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf = call float @returns_inf() @@ -1488,7 +1460,7 @@ define nofpclass(snan) float @unknown__maxnum__inf(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__maxnum__inf( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[INF:%.*]] = call float @returns_inf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[INF]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float [[INF]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf = call float @returns_inf() @@ -1500,7 +1472,7 @@ define nofpclass(snan) float @inf_or_nan__maxnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @inf_or_nan__maxnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[INF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[INF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf_or_nan() @@ -1512,7 +1484,7 @@ define nofpclass(snan) float @unknown__maxnum__inf_or_nan(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__maxnum__inf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN]], float [[INF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[UNKNOWN]], float [[INF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf_or_nan() @@ -1524,8 +1496,7 @@ define nofpclass(snan) float @ninf_or_nan__maxnum__not_nan(float nofpclass(nan) ; CHECK-LABEL: define nofpclass(snan) float @ninf_or_nan__maxnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NINF_OR_NAN]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %ninf.or.nan = call float @returns_ninf_or_nan() %result = call float @llvm.maxnum.f32(float %ninf.or.nan, float %not.nan) @@ -1536,8 +1507,7 @@ define nofpclass(snan) float @not_nan__maxnum__ninf_or_nan(float nofpclass(nan) ; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum__ninf_or_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN]], float [[NINF_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %ninf.or.nan = call float @returns_ninf_or_nan() %result = call float @llvm.maxnum.f32(float %not.nan, float %ninf.or.nan) @@ -1548,7 +1518,7 @@ define nofpclass(snan) float @pinf_or_nan__maxnum__not_nan(float nofpclass(nan) ; CHECK-LABEL: define nofpclass(snan) float @pinf_or_nan__maxnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[PINF_OR_NAN]], float [[NOT_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[PINF_OR_NAN]], float [[NOT_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %pinf.or.nan = call float @returns_pinf_or_nan() @@ -1560,7 +1530,7 @@ define nofpclass(snan) float @not_nan__maxnum__pinf_or_nan(float nofpclass(nan) ; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum__pinf_or_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN]], float [[PINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_NAN]], float [[PINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %pinf.or.nan = call float @returns_pinf_or_nan() @@ -1572,7 +1542,7 @@ define nofpclass(snan) float @inf_or_nan__maxnum__not_nan(float nofpclass(nan) % ; CHECK-LABEL: define nofpclass(snan) float @inf_or_nan__maxnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[INF_OR_NAN]], float [[NOT_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[INF_OR_NAN]], float [[NOT_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf_or_nan() @@ -1584,7 +1554,7 @@ define nofpclass(snan) float @not_nan__maxnum__inf_or_nan(float nofpclass(nan) % ; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum__inf_or_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN]], float [[INF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NOT_NAN]], float [[INF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf_or_nan() @@ -1596,8 +1566,7 @@ define nofpclass(snan) float @ninf__maxnum__not_nan(float nofpclass(nan) %not.na ; CHECK-LABEL: define nofpclass(snan) float @ninf__maxnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NINF_OR_NAN]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %ninf.or.nan = call float @returns_ninf() %result = call float @llvm.maxnum.f32(float %ninf.or.nan, float %not.nan) @@ -1608,8 +1577,7 @@ define nofpclass(snan) float @not_nan__maxnum__ninf(float nofpclass(nan) %not.na ; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum__ninf( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN]], float [[NINF_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %ninf.or.nan = call float @returns_ninf() %result = call float @llvm.maxnum.f32(float %not.nan, float %ninf.or.nan) @@ -1620,8 +1588,7 @@ define nofpclass(snan) float @pinf__maxnum__not_nan(float nofpclass(nan) %not.na ; CHECK-LABEL: define nofpclass(snan) float @pinf__maxnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[PINF_OR_NAN]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %pinf.or.nan = call float @returns_pinf() %result = call float @llvm.maxnum.f32(float %pinf.or.nan, float %not.nan) @@ -1632,8 +1599,7 @@ define nofpclass(snan) float @not_nan__maxnum__pinf(float nofpclass(nan) %not.na ; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum__pinf( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN]], float [[PINF_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %pinf.or.nan = call float @returns_pinf() %result = call float @llvm.maxnum.f32(float %not.nan, float %pinf.or.nan) @@ -1644,7 +1610,7 @@ define nofpclass(snan) float @inf__maxnum__not_nan(float nofpclass(nan) %not.nan ; CHECK-LABEL: define nofpclass(snan) float @inf__maxnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[INF_OR_NAN]], float [[NOT_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan nsz float @llvm.maxnum.f32(float [[INF_OR_NAN]], float [[NOT_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf() @@ -1656,7 +1622,7 @@ define nofpclass(snan) float @not_nan__maxnum__inf(float nofpclass(nan) %not.nan ; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum__inf( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN]], float [[INF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan nsz float @llvm.maxnum.f32(float [[NOT_NAN]], float [[INF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf() @@ -1697,7 +1663,7 @@ define nofpclass(snan) float @unknown__noundef_maxnum__not_nan(float %unknown, f define nofpclass(snan) float @not_nan__noundef_maxnum__not_nan(float nofpclass(nan) %not.nan0, float nofpclass(nan) %not.nan1) { ; CHECK-LABEL: define nofpclass(snan) float @not_nan__noundef_maxnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN0:%.*]], float nofpclass(nan) [[NOT_NAN1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call noundef float @llvm.maxnum.f32(float [[NOT_NAN0]], float [[NOT_NAN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.maxnum.f32(float [[NOT_NAN0]], float [[NOT_NAN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call noundef float @llvm.maxnum.f32(float %not.nan0, float %not.nan1) @@ -1757,7 +1723,7 @@ define nofpclass(inf) float @not_inf__noundef_maxnum__not_inf(float nofpclass(in define nofpclass(snan) float @not_nan__maxnum_noundef_md__not_nan(float nofpclass(nan) %not.nan0, float nofpclass(nan) %not.nan1) { ; CHECK-LABEL: define nofpclass(snan) float @not_nan__maxnum_noundef_md__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN0:%.*]], float nofpclass(nan) [[NOT_NAN1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NOT_NAN0]], float [[NOT_NAN1]]), !noundef [[META0:![0-9]+]], !unknown.md [[META0]] +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.maxnum.f32(float [[NOT_NAN0]], float [[NOT_NAN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.maxnum.f32(float %not.nan0, float %not.nan1), !noundef !0, !unknown.md !0 @@ -1771,8 +1737,7 @@ define nofpclass(snan) float @select_is_positive_or_0__maxnum__nnorm_0(float nou ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: [[NNORM:%.*]] = call float @returns_nnorm() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[SELECT]], float [[NNORM]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[SELECT]] ; %is.pos.or.zero = fcmp oge float %arg, 0.0 %select = select i1 %is.pos.or.zero, float %arg, float 0.0 @@ -1787,8 +1752,7 @@ define nofpclass(snan) float @select_is_positive_or_0__maxnum__nnorm_1(float nou ; CHECK-NEXT: [[NNORM:%.*]] = call float @returns_nnorm() ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NNORM]], float [[SELECT]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[SELECT]] ; %nnorm = call float @returns_nnorm() %is.pos.or.zero = fcmp oge float %arg, 0.0 @@ -1803,8 +1767,7 @@ define nofpclass(snan) float @select_is_positive_or_0__maxnum__nnorm_or_nan_0(fl ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: [[NNORM_OR_NAN:%.*]] = call float @returns_nnorm_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[SELECT]], float [[NNORM_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[SELECT]] ; %is.pos.or.zero = fcmp oge float %arg, 0.0 %select = select i1 %is.pos.or.zero, float %arg, float 0.0 @@ -1819,8 +1782,7 @@ define nofpclass(snan) float @select_is_positive_or_0__maxnum__nnorm_or_nan_1(fl ; CHECK-NEXT: [[NNORM_OR_NAN:%.*]] = call float @returns_nnorm_or_nan() ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NNORM_OR_NAN]], float [[SELECT]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[SELECT]] ; %nnorm.or.nan = call float @returns_nnorm_or_nan() %is.pos.or.zero = fcmp oge float %arg, 0.0 @@ -1835,8 +1797,7 @@ define nofpclass(snan) float @select_is_positive_or_0__maxnum__negative(float no ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[SELECT]], float [[NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[SELECT]] ; %is.pos.or.zero = fcmp oge float %arg, 0.0 %select = select i1 %is.pos.or.zero, float %arg, float 0.0 @@ -1851,8 +1812,7 @@ define nofpclass(snan) float @negative__maxnum__select_is_positive_or_0(float no ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NEGATIVE]], float [[SELECT]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[SELECT]] ; %negative = call float @returns_negative() %is.pos.or.zero = fcmp oge float %arg, 0.0 @@ -1867,7 +1827,7 @@ define nofpclass(snan) float @select_is_positive_or_0__maxnum__negative_or_zero( ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: [[NEGATIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[SELECT]], float [[NEGATIVE_OR_ZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.maxnum.f32(float [[SELECT]], float [[NEGATIVE_OR_ZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %is.pos.or.zero = fcmp oge float %arg, 0.0 @@ -1883,7 +1843,7 @@ define nofpclass(snan) float @negative_or_zero__maxnum__select_is_positive_or_0( ; CHECK-NEXT: [[NEGATIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NEGATIVE_OR_ZERO]], float [[SELECT]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.maxnum.f32(float [[NEGATIVE_OR_ZERO]], float [[SELECT]]) ; CHECK-NEXT: ret float [[RESULT]] ; %negative.or.zero = call float @returns_negative_or_zero() @@ -1897,8 +1857,7 @@ define nofpclass(snan) float @negative_or_zero__maxnum__positive() { ; CHECK-LABEL: define nofpclass(snan) float @negative_or_zero__maxnum__positive() { ; CHECK-NEXT: [[NEG_NONZERO:%.*]] = call float @returns_negative_nonzero() ; CHECK-NEXT: [[POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NEG_NONZERO]], float [[POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[POSITIVE]] ; %neg.nonzero = call float @returns_negative_nonzero() %positive = call float @returns_positive() @@ -1910,8 +1869,7 @@ define nofpclass(snan) float @positive__maxnum__negative_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @positive__maxnum__negative_or_zero() { ; CHECK-NEXT: [[POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[NEG_NONZERO:%.*]] = call float @returns_negative_nonzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[POSITIVE]], float [[NEG_NONZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[POSITIVE]] ; %positive = call float @returns_positive() %neg.nonzero = call float @returns_negative_nonzero() @@ -1923,8 +1881,7 @@ define nofpclass(snan) float @negative_or_zero__maxnum__positive_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @negative_or_zero__maxnum__positive_or_zero() { ; CHECK-NEXT: [[NEG_NONZERO:%.*]] = call float @returns_negative_nonzero() ; CHECK-NEXT: [[POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NEG_NONZERO]], float [[POSITIVE_OR_ZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[POSITIVE_OR_ZERO]] ; %neg.nonzero = call float @returns_negative_nonzero() %positive.or.zero = call float @returns_positive_or_zero() @@ -1936,8 +1893,7 @@ define nofpclass(snan) float @positive_or_zero__maxnum__negative_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @positive_or_zero__maxnum__negative_or_zero() { ; CHECK-NEXT: [[POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[NEG_NONZERO:%.*]] = call float @returns_negative_nonzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[POSITIVE_OR_ZERO]], float [[NEG_NONZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[POSITIVE_OR_ZERO]] ; %positive.or.zero = call float @returns_positive_or_zero() %neg.nonzero = call float @returns_negative_nonzero() @@ -1949,8 +1905,7 @@ define nofpclass(snan) float @positive_or_zero__maxnum__negative() { ; CHECK-LABEL: define nofpclass(snan) float @positive_or_zero__maxnum__negative() { ; CHECK-NEXT: [[POS_NONZERO:%.*]] = call float @returns_positive_nonzero() ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[POS_NONZERO]], float [[NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[POS_NONZERO]] ; %pos.nonzero = call float @returns_positive_nonzero() %negative = call float @returns_negative() @@ -1962,8 +1917,7 @@ define nofpclass(snan) float @negative__maxnum__positive_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @negative__maxnum__positive_or_zero() { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[POS_NONZERO:%.*]] = call float @returns_positive_nonzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NEGATIVE]], float [[POS_NONZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[POS_NONZERO]] ; %negative = call float @returns_negative() %pos.nonzero = call float @returns_positive_nonzero() @@ -1975,8 +1929,7 @@ define nofpclass(snan) float @positive_or_zero__maxnum__negative_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @positive_or_zero__maxnum__negative_or_nan() { ; CHECK-NEXT: [[POS_NONZERO:%.*]] = call float @returns_positive_nonzero() ; CHECK-NEXT: [[NEGATIVE_OR_NAN:%.*]] = call float @returns_negative_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[POS_NONZERO]], float [[NEGATIVE_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[POS_NONZERO]] ; %pos.nonzero = call float @returns_positive_nonzero() %negative.or.nan = call float @returns_negative_or_nan() @@ -1988,8 +1941,7 @@ define nofpclass(snan) float @negative_or_nan__maxnum__positive_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @negative_or_nan__maxnum__positive_or_zero() { ; CHECK-NEXT: [[NEGATIVE_OR_NAN:%.*]] = call float @returns_negative_or_nan() ; CHECK-NEXT: [[POS_NONZERO:%.*]] = call float @returns_positive_nonzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NEGATIVE_OR_NAN]], float [[POS_NONZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[POS_NONZERO]] ; %negative.or.nan = call float @returns_negative_or_nan() %pos.nonzero = call float @returns_positive_nonzero() @@ -2001,7 +1953,7 @@ define nofpclass(snan) float @positive_or_zero_or_nan__maxnum__negative() { ; CHECK-LABEL: define nofpclass(snan) float @positive_or_zero_or_nan__maxnum__negative() { ; CHECK-NEXT: [[POS_NONZERO_OR_NAN:%.*]] = call float @returns_positive_nonzero_or_nan() ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[POS_NONZERO_OR_NAN]], float [[NEGATIVE]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[POS_NONZERO_OR_NAN]], float [[NEGATIVE]]) ; CHECK-NEXT: ret float [[RESULT]] ; %pos.nonzero.or.nan = call float @returns_positive_nonzero_or_nan() @@ -2014,7 +1966,7 @@ define nofpclass(snan) float @negative__maxnum__positive_or_zero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @negative__maxnum__positive_or_zero_or_nan() { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[POS_NONZERO_OR_NAN:%.*]] = call float @returns_positive_nonzero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NEGATIVE]], float [[POS_NONZERO_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.maxnum.f32(float [[NEGATIVE]], float [[POS_NONZERO_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %negative = call float @returns_negative() @@ -2027,8 +1979,7 @@ define nofpclass(snan) float @known_pnorm__maxnum__known_psub() { ; CHECK-LABEL: define nofpclass(snan) float @known_pnorm__maxnum__known_psub() { ; CHECK-NEXT: [[PNORM:%.*]] = call float @returns_pnorm() ; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[PNORM]], float [[PSUB]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[PNORM]] ; %pnorm = call float @returns_pnorm() %psub = call float @returns_psub() @@ -2040,8 +1991,7 @@ define nofpclass(snan) float @known_psub__maxnum__known_pnorm() { ; CHECK-LABEL: define nofpclass(snan) float @known_psub__maxnum__known_pnorm() { ; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub() ; CHECK-NEXT: [[PNORM:%.*]] = call float @returns_pnorm() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[PSUB]], float [[PNORM]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[PNORM]] ; %psub = call float @returns_psub() %pnorm = call float @returns_pnorm() @@ -2053,8 +2003,7 @@ define nofpclass(snan) float @known_pinf__maxnum__known_psub() { ; CHECK-LABEL: define nofpclass(snan) float @known_pinf__maxnum__known_psub() { ; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf() ; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[PINF]], float [[PSUB]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %pinf = call float @returns_pinf() %psub = call float @returns_psub() @@ -2066,8 +2015,7 @@ define nofpclass(snan) float @known_psub__maxnum__known_pinf() { ; CHECK-LABEL: define nofpclass(snan) float @known_psub__maxnum__known_pinf() { ; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub() ; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[PSUB]], float [[PINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF0000000000000 ; %psub = call float @returns_psub() %pinf = call float @returns_pinf() @@ -2079,8 +2027,7 @@ define nofpclass(snan) float @known_nnorm__maxnum__known_nsub() { ; CHECK-LABEL: define nofpclass(snan) float @known_nnorm__maxnum__known_nsub() { ; CHECK-NEXT: [[NNORM:%.*]] = call float @returns_nnorm() ; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NNORM]], float [[NSUB]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NSUB]] ; %nnorm = call float @returns_nnorm() %nsub = call float @returns_nsub() @@ -2092,8 +2039,7 @@ define nofpclass(snan) float @known_nsub__maxnum__known_nnorm() { ; CHECK-LABEL: define nofpclass(snan) float @known_nsub__maxnum__known_nnorm() { ; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub() ; CHECK-NEXT: [[NNORM:%.*]] = call float @returns_nnorm() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NSUB]], float [[NNORM]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NSUB]] ; %nsub = call float @returns_nsub() %nnorm = call float @returns_nnorm() @@ -2105,8 +2051,7 @@ define nofpclass(snan) float @known_ninf__maxnum__known_nsub() { ; CHECK-LABEL: define nofpclass(snan) float @known_ninf__maxnum__known_nsub() { ; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf() ; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NINF]], float [[NSUB]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NSUB]] ; %ninf = call float @returns_ninf() %nsub = call float @returns_nsub() @@ -2118,8 +2063,7 @@ define nofpclass(snan) float @known_nsub__maxnum__known_ninf() { ; CHECK-LABEL: define nofpclass(snan) float @known_nsub__maxnum__known_ninf() { ; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub() ; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[NSUB]], float [[NINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NSUB]] ; %nsub = call float @returns_nsub() %ninf = call float @returns_ninf() @@ -2134,7 +2078,7 @@ define nofpclass(snan) float @simplify_multiple_use_maxnum(ptr %ptr) { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[MAX:%.*]] = call float @llvm.maxnum.f32(float [[POSITIVE]], float [[NEGATIVE]]) ; CHECK-NEXT: store float [[MAX]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MAX]] +; CHECK-NEXT: ret float [[POSITIVE]] ; %positive = call float @returns_positive() %negative = call float @returns_negative() @@ -2150,7 +2094,7 @@ define nofpclass(snan) float @simplify_multiple_use_maxnum_commute(ptr %ptr) { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[MAX:%.*]] = call float @llvm.maxnum.f32(float [[NEGATIVE]], float [[POSITIVE]]) ; CHECK-NEXT: store float [[MAX]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MAX]] +; CHECK-NEXT: ret float [[POSITIVE]] ; %positive = call float @returns_positive() %negative = call float @returns_negative() @@ -2223,10 +2167,35 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1__ ret float %result } +define nofpclass(snan) float @qnan_result_demands_snan_lhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[SELECT]], float [[UNKNOWN1]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.maxnum.f32(float %select, float %unknown1) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_rhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.maxnum.f32(float [[UNKNOWN1]], float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.maxnum.f32(float %unknown1, float %select) + ret float %result +} + !0 = !{} -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } -;. -; CHECK: [[META0]] = !{} -;. +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll index fba6e9c45da4d..ab1f64209c8d1 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimum.ll @@ -20,6 +20,7 @@ declare nofpclass(inf sub norm pzero) float @returns_nzero_or_nan() declare nofpclass(inf sub norm nan nzero) float @returns_pzero() declare nofpclass(inf sub norm nzero) float @returns_pzero_or_nan() declare nofpclass(inf norm sub zero) float @returns_nan() +declare nofpclass(qnan inf norm sub zero) float @returns_snan() declare nofpclass(ninf norm sub zero nan) float @returns_pinf() declare nofpclass(ninf norm sub zero) float @returns_pinf_or_nan() @@ -2090,7 +2091,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_0__mul ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) ; CHECK-NEXT: store float [[RESULT]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MUST_BE_NEGATIVE_OR_ZERO]] +; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_negative_or_zero() %must.be.positive.or.zero = call float @returns_positive_or_zero() @@ -2106,7 +2107,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1__mul ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() ; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_NEGATIVE_OR_ZERO]]) ; CHECK-NEXT: store float [[RESULT]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MUST_BE_NEGATIVE_OR_ZERO]] +; CHECK-NEXT: ret float [[RESULT]] ; %must.be.positive.or.zero = call float @returns_positive_or_zero() %must.be.negative.or.zero = call float @returns_negative_or_zero() @@ -2147,7 +2148,36 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1__ ret float %result } + +define nofpclass(snan) float @qnan_result_demands_snan_lhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minimum.f32(float [[SELECT]], float [[UNKNOWN1]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.minimum.f32(float %select, float %unknown1) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_rhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minimum.f32(float [[UNKNOWN1]], float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.minimum.f32(float %unknown1, float %select) + ret float %result +} + !0 = !{} -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll index b67077cb7dbd9..4eb1286685b7a 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minimumnum.ll @@ -20,6 +20,7 @@ declare nofpclass(inf sub norm pzero) float @returns_nzero_or_nan() declare nofpclass(inf sub norm nan nzero) float @returns_pzero() declare nofpclass(inf sub norm nzero) float @returns_pzero_or_nan() declare nofpclass(inf norm sub zero) float @returns_nan() +declare nofpclass(qnan inf norm sub zero) float @returns_snan() declare nofpclass(ninf norm sub zero nan) float @returns_pinf() declare nofpclass(ninf norm sub zero) float @returns_pinf_or_nan() @@ -2098,7 +2099,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_0__mul ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) ; CHECK-NEXT: store float [[RESULT]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MUST_BE_NEGATIVE_OR_ZERO]] +; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_negative_or_zero() %must.be.positive.or.zero = call float @returns_positive_or_zero() @@ -2114,7 +2115,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1__mul ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() ; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minimumnum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_NEGATIVE_OR_ZERO]]) ; CHECK-NEXT: store float [[RESULT]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MUST_BE_NEGATIVE_OR_ZERO]] +; CHECK-NEXT: ret float [[RESULT]] ; %must.be.positive.or.zero = call float @returns_positive_or_zero() %must.be.negative.or.zero = call float @returns_negative_or_zero() @@ -2155,7 +2156,35 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1__ ret float %result } +define nofpclass(snan) float @qnan_result_demands_snan_lhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minimumnum.f32(float [[SELECT]], float [[UNKNOWN1]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.minimumnum.f32(float %select, float %unknown1) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_rhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minimumnum.f32(float [[UNKNOWN1]], float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.minimumnum.f32(float %unknown1, float %select) + ret float %result +} + !0 = !{} -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll index bf16957ea8d44..adcb9f067a998 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-minnum.ll @@ -20,6 +20,7 @@ declare nofpclass(inf sub norm pzero) float @returns_nzero_or_nan() declare nofpclass(inf sub norm nan nzero) float @returns_pzero() declare nofpclass(inf sub norm nzero) float @returns_pzero_or_nan() declare nofpclass(inf norm sub zero) float @returns_nan() +declare nofpclass(qnan inf norm sub zero) float @returns_snan() declare nofpclass(ninf norm sub zero nan) float @returns_pinf() declare nofpclass(ninf norm sub zero) float @returns_pinf_or_nan() @@ -48,8 +49,7 @@ declare nofpclass(ninf nnorm nsub zero) float @returns_positive_nonzero_or_nan() define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) { ; CHECK-LABEL: define nofpclass(inf zero sub norm) float @ret_only_nan( ; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[X]], float [[Y]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF8000000000000 ; %result = call float @llvm.minnum.f32(float %x, float %y) ret float %result @@ -58,7 +58,7 @@ define nofpclass(inf norm sub zero) float @ret_only_nan(float %x, float %y) { define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y) { ; CHECK-LABEL: define nofpclass(qnan inf zero sub norm) float @ret_only_snan( ; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[X]], float [[Y]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[X]], float [[Y]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %x, float %y) @@ -68,8 +68,7 @@ define nofpclass(inf norm sub zero qnan) float @ret_only_snan(float %x, float %y define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y) { ; CHECK-LABEL: define nofpclass(snan inf zero sub norm) float @ret_only_qnan( ; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[X]], float [[Y]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF8000000000000 ; %result = call float @llvm.minnum.f32(float %x, float %y) ret float %result @@ -78,7 +77,7 @@ define nofpclass(inf norm sub zero snan) float @ret_only_qnan(float %x, float %y define nofpclass(nan norm sub zero) float @ret_only_inf(float %x, float %y) { ; CHECK-LABEL: define nofpclass(nan zero sub norm) float @ret_only_inf( ; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[X]], float [[Y]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[X]], float [[Y]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %x, float %y) @@ -166,8 +165,7 @@ define nofpclass(ninf nnorm nsub nzero) float @ret_known_positive_or_nan__minnum ; CHECK-LABEL: define nofpclass(ninf nzero nsub nnorm) float @ret_known_positive_or_nan__minnum__negative_or_nan___negative_or_nan() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN0:%.*]] = call float @returns_negative_or_nan() ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_NAN1:%.*]] = call float @returns_negative_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_NEGATIVE_OR_NAN0]], float [[MUST_BE_NEGATIVE_OR_NAN1]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF8000000000000 ; %must.be.negative.or.nan0 = call float @returns_negative_or_nan() %must.be.negative.or.nan1 = call float @returns_negative_or_nan() @@ -180,8 +178,7 @@ define nofpclass(pinf pnorm psub pzero) float @ret_known_negative_or_nan__minnum ; CHECK-LABEL: define nofpclass(pinf pzero psub pnorm) float @ret_known_negative_or_nan__minnum__positive_or_nan___positive_or_nan() { ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN0:%.*]] = call float @returns_positive_or_nan() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN1:%.*]] = call float @returns_positive_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_POSITIVE_OR_NAN0]], float [[MUST_BE_POSITIVE_OR_NAN1]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0x7FF8000000000000 ; %must.be.positive.or.nan0 = call float @returns_positive_or_nan() %must.be.positive.or.nan1 = call float @returns_positive_or_nan() @@ -219,8 +216,7 @@ define nofpclass(snan) float @known_positive_or_nan__minnum__known_negative() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive_or_nan__minnum__known_negative() { ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN:%.*]] = call float @returns_positive_or_nan() ; CHECK-NEXT: [[MUST_BE_NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_POSITIVE_OR_NAN]], float [[MUST_BE_NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[MUST_BE_NEGATIVE]] ; %must.be.positive.or.nan = call float @returns_positive_or_nan() %must.be.negative = call float @returns_negative() @@ -232,8 +228,7 @@ define nofpclass(snan) float @known_negative__minnum__known_positive_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative__minnum__known_positive_or_nan() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_NAN:%.*]] = call float @returns_positive_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_NEGATIVE]], float [[MUST_BE_POSITIVE_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[MUST_BE_NEGATIVE]] ; %must.be.negative = call float @returns_negative() %must.be.positive.or.nan = call float @returns_positive_or_nan() @@ -366,7 +361,7 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_0() ; CHECK-LABEL: define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_0() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.minnum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_positive_or_zero() @@ -380,7 +375,7 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1() ; CHECK-LABEL: define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_NEGATIVE_OR_ZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.minnum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_NEGATIVE_OR_ZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %must.be.negative.or.zero = call float @returns_positive_or_zero() @@ -393,8 +388,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_0() { ; CHECK-LABEL: define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_0() { ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO1:%.*]] = call float @returns_positive_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[MUST_BE_POSITIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO1]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[MUST_BE_POSITIVE_OR_ZERO]] ; %must.be.negative.or.zero = call float @returns_negative_or_zero() %must.be.positive.or.zero = call float @returns_positive_or_zero() @@ -406,8 +400,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1() { ; CHECK-LABEL: define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1() { ; CHECK-NEXT: [[MUST_BE_NEGATIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[MUST_BE_POSITIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[MUST_BE_NEGATIVE_OR_ZERO]], float [[MUST_BE_POSITIVE_OR_ZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[MUST_BE_POSITIVE_OR_ZERO]] ; %must.be.positive.or.zero = call float @returns_positive_or_zero() %must.be.negative.or.zero = call float @returns_negative_or_zero() @@ -418,7 +411,7 @@ define nofpclass(snan) float @nsz_fold_negative_or_zero__positive_or_zero_1() { define nofpclass(nsub) float @lhs_must_be_pinf_or_nan(float %unknown, float nofpclass(ninf norm zero sub) %must.be.pinf.or.nan) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(ninf zero sub norm) [[MUST_BE_PINF_OR_NAN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_PINF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[MUST_BE_PINF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %must.be.pinf.or.nan, float %unknown) @@ -428,7 +421,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf_or_nan(float %unknown, float nofp define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm zero sub) %must.be.pinf.or.nan, float %unknown) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf_or_nan( ; CHECK-SAME: float nofpclass(ninf zero sub norm) [[MUST_BE_PINF_OR_NAN:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[MUST_BE_PINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float [[MUST_BE_PINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %unknown, float %must.be.pinf.or.nan) @@ -438,7 +431,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_or_nan(float nofpclass(ninf norm define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(nan ninf norm zero sub) %must.be.pinf) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_PINF]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %must.be.pinf, float %unknown) @@ -448,7 +441,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf(float %unknown, float nofpclass(n define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float %unknown) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf( ; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[MUST_BE_PINF]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %unknown, float %must.be.pinf) @@ -459,8 +452,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf(float nofpclass(nan ninf norm zer define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan ninf norm zero sub) %must.be.pinf) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_PINF]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %result = call float @llvm.minnum.f32(float %must.be.pinf, float %not.nan) ret float %result @@ -470,8 +462,7 @@ define nofpclass(nsub) float @lhs_must_be_pinf_rhs_non_nan(float nofpclass(nan) define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(float nofpclass(nan ninf norm zero sub) %must.be.pinf, float nofpclass(nan) %not.nan) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan( ; CHECK-SAME: float nofpclass(nan ninf zero sub norm) [[MUST_BE_PINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN]], float [[MUST_BE_PINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %result = call float @llvm.minnum.f32(float %not.nan, float %must.be.pinf) ret float %result @@ -480,7 +471,7 @@ define nofpclass(nsub) float @rhs_must_be_pinf_lhs_non_nan(float nofpclass(nan n define nofpclass(nsub) float @lhs_must_be_ninf_or_nan(float %unknown, float nofpclass(pinf norm zero sub) %must.be.ninf.or.nan) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(pinf zero sub norm) [[MUST_BE_NINF_OR_NAN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_NINF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[MUST_BE_NINF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %must.be.ninf.or.nan, float %unknown) @@ -490,7 +481,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf_or_nan(float %unknown, float nofp define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm zero sub) %must.be.ninf.or.nan, float %unknown) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf_or_nan( ; CHECK-SAME: float nofpclass(pinf zero sub norm) [[MUST_BE_NINF_OR_NAN:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[MUST_BE_NINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float [[MUST_BE_NINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %unknown, float %must.be.ninf.or.nan) @@ -500,8 +491,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf_or_nan(float nofpclass(pinf norm define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(nan pinf norm zero sub) %must.be.ninf) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_NINF]], float [[UNKNOWN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %result = call float @llvm.minnum.f32(float %must.be.ninf, float %unknown) ret float %result @@ -510,8 +500,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf(float %unknown, float nofpclass(n define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float %unknown) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf( ; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[MUST_BE_NINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %result = call float @llvm.minnum.f32(float %unknown, float %must.be.ninf) ret float %result @@ -522,8 +511,7 @@ define nofpclass(nsub) float @rhs_must_be_ninf(float nofpclass(nan pinf norm zer define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan) %not.nan, float nofpclass(nan pinf norm zero sub) %must.be.ninf) { ; CHECK-LABEL: define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]], float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[MUST_BE_NINF]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %result = call float @llvm.minnum.f32(float %must.be.ninf, float %not.nan) ret float %result @@ -533,8 +521,7 @@ define nofpclass(nsub) float @lhs_must_be_ninf_rhs_non_nan(float nofpclass(nan) define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan(float nofpclass(nan pinf norm zero sub) %must.be.ninf, float nofpclass(nan) %not.nan) { ; CHECK-LABEL: define nofpclass(nsub) float @rhs_must_be_ninf_lhs_non_nan( ; CHECK-SAME: float nofpclass(nan pinf zero sub norm) [[MUST_BE_NINF:%.*]], float nofpclass(nan) [[NOT_NAN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN]], float [[MUST_BE_NINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %result = call float @llvm.minnum.f32(float %not.nan, float %must.be.ninf) ret float %result @@ -563,7 +550,7 @@ define nofpclass(pzero) float @result_not_pzero(float %unknown0, float %unknown1 define nofpclass(zero) float @result_not_zero(float %unknown0, float %unknown1) { ; CHECK-LABEL: define nofpclass(zero) float @result_not_zero( ; CHECK-SAME: float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %unknown0, float %unknown1) @@ -593,7 +580,7 @@ define nofpclass(zero) float @result_not_zero__dynamic(float %unknown0, float %u define nofpclass(zero) float @result_not_zero_or_sub(float %unknown0, float %unknown1) { ; CHECK-LABEL: define nofpclass(zero) float @result_not_zero_or_sub( ; CHECK-SAME: float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %unknown0, float %unknown1) @@ -603,7 +590,7 @@ define nofpclass(zero) float @result_not_zero_or_sub(float %unknown0, float %unk define nofpclass(zero sub) float @result_not_zero_or_sub__daz(float %unknown0, float %unknown1) #0 { ; CHECK-LABEL: define nofpclass(zero sub) float @result_not_zero_or_sub__daz( ; CHECK-SAME: float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %unknown0, float %unknown1) @@ -613,7 +600,7 @@ define nofpclass(zero sub) float @result_not_zero_or_sub__daz(float %unknown0, f define nofpclass(zero sub) float @result_not_zero_or_sub__dynamic(float %unknown0, float %unknown1) #1 { ; CHECK-LABEL: define nofpclass(zero sub) float @result_not_zero_or_sub__dynamic( ; CHECK-SAME: float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN0]], float [[UNKNOWN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %unknown0, float %unknown1) @@ -623,7 +610,7 @@ define nofpclass(zero sub) float @result_not_zero_or_sub__dynamic(float %unknown define nofpclass(snan) float @lhs_not_zero(float nofpclass(zero) %not.zero, float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @lhs_not_zero( ; CHECK-SAME: float nofpclass(zero) [[NOT_ZERO:%.*]], float [[UNKNOWN:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_ZERO]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_ZERO]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.zero, float %unknown) @@ -633,7 +620,7 @@ define nofpclass(snan) float @lhs_not_zero(float nofpclass(zero) %not.zero, floa define nofpclass(snan) float @rhs_not_zero(float %unknown, float nofpclass(zero) %not.zero) { ; CHECK-LABEL: define nofpclass(snan) float @rhs_not_zero( ; CHECK-SAME: float [[UNKNOWN:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[NOT_ZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float [[NOT_ZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %unknown, float %not.zero) @@ -643,7 +630,7 @@ define nofpclass(snan) float @rhs_not_zero(float %unknown, float nofpclass(zero) define nofpclass(snan) float @sources_not_zero(float nofpclass(zero) %not.zero0, float nofpclass(zero) %not.zero1) { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_zero( ; CHECK-SAME: float nofpclass(zero) [[NOT_ZERO0:%.*]], float nofpclass(zero) [[NOT_ZERO1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_ZERO0]], float [[NOT_ZERO1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_ZERO0]], float [[NOT_ZERO1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.zero0, float %not.zero1) @@ -673,7 +660,7 @@ define nofpclass(snan) float @sources_not_zero__dynamic(float nofpclass(zero) %n define nofpclass(snan) float @sources_not_zero_or_sub(float nofpclass(zero sub) %not.zero.sub.0, float nofpclass(zero sub) %not.zero.sub.1) { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_zero_or_sub( ; CHECK-SAME: float nofpclass(zero sub) [[NOT_ZERO_SUB_0:%.*]], float nofpclass(zero sub) [[NOT_ZERO_SUB_1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.zero.sub.0, float %not.zero.sub.1) @@ -683,7 +670,7 @@ define nofpclass(snan) float @sources_not_zero_or_sub(float nofpclass(zero sub) define nofpclass(snan) float @sources_not_zero_or_sub__daz(float nofpclass(zero sub) %not.zero.sub.0, float nofpclass(zero sub) %not.zero.sub.1) #1 { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_zero_or_sub__daz( ; CHECK-SAME: float nofpclass(zero sub) [[NOT_ZERO_SUB_0:%.*]], float nofpclass(zero sub) [[NOT_ZERO_SUB_1:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.zero.sub.0, float %not.zero.sub.1) @@ -693,7 +680,7 @@ define nofpclass(snan) float @sources_not_zero_or_sub__daz(float nofpclass(zero define nofpclass(snan) float @sources_not_zero_or_sub__dynamic(float nofpclass(zero sub) %not.zero.sub.0, float nofpclass(zero sub) %not.zero.sub.1) #1 { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_zero_or_sub__dynamic( ; CHECK-SAME: float nofpclass(zero sub) [[NOT_ZERO_SUB_0:%.*]], float nofpclass(zero sub) [[NOT_ZERO_SUB_1:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_ZERO_SUB_0]], float [[NOT_ZERO_SUB_1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.zero.sub.0, float %not.zero.sub.1) @@ -703,7 +690,7 @@ define nofpclass(snan) float @sources_not_zero_or_sub__dynamic(float nofpclass(z define nofpclass(snan) float @sources_not_nzero(float nofpclass(nzero) %not.nzero0, float nofpclass(nzero) %not.nzero1) { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_nzero( ; CHECK-SAME: float nofpclass(nzero) [[NOT_NZERO0:%.*]], float nofpclass(nzero) [[NOT_NZERO1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NZERO0]], float [[NOT_NZERO1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_NZERO0]], float [[NOT_NZERO1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.nzero0, float %not.nzero1) @@ -713,7 +700,7 @@ define nofpclass(snan) float @sources_not_nzero(float nofpclass(nzero) %not.nzer define nofpclass(snan) float @sources_not_pzero(float nofpclass(pzero) %not.pzero0, float nofpclass(pzero) %not.pzero1) { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_pzero( ; CHECK-SAME: float nofpclass(pzero) [[NOT_PZERO0:%.*]], float nofpclass(pzero) [[NOT_PZERO1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_PZERO0]], float [[NOT_PZERO1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_PZERO0]], float [[NOT_PZERO1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.pzero0, float %not.pzero1) @@ -783,7 +770,7 @@ define nofpclass(snan) float @rhs_not_nzero_lhs_not_pzero__dynamic(float nofpcla define nofpclass(snan) float @sources_not_nzero_nsub__dynamic(float nofpclass(nzero nsub) %not.nzero0, float nofpclass(nzero nsub) %not.nzero1) #1 { ; CHECK-LABEL: define nofpclass(snan) float @sources_not_nzero_nsub__dynamic( ; CHECK-SAME: float nofpclass(nzero nsub) [[NOT_NZERO0:%.*]], float nofpclass(nzero nsub) [[NOT_NZERO1:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NZERO0]], float [[NOT_NZERO1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_NZERO0]], float [[NOT_NZERO1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.nzero0, float %not.nzero1) @@ -843,7 +830,7 @@ define nofpclass(snan) float @unknown__minnum__not_nan(float %x, float nofpclass define nofpclass(snan) float @not_nan__minnum__not_nan(float nofpclass(nan) %x, float nofpclass(nan) %y) { ; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[X:%.*]], float nofpclass(nan) [[Y:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[X]], float [[Y]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.minnum.f32(float [[X]], float [[Y]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %x, float %y) @@ -874,8 +861,7 @@ define nofpclass(snan) float @known_positive__minnum__only_zero() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive__minnum__only_zero() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_ZERO:%.*]] = call float @returns_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_ZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_ZERO]] ; %known.positive = call float @returns_positive() %known.zero = call float @returns_zero() @@ -887,8 +873,7 @@ define nofpclass(snan) float @only_zero__minnum__known_positive() { ; CHECK-LABEL: define nofpclass(snan) float @only_zero__minnum__known_positive() { ; CHECK-NEXT: [[KNOWN_ZERO:%.*]] = call float @returns_zero() ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_ZERO]], float [[KNOWN_POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_ZERO]] ; %known.zero = call float @returns_zero() %known.positive = call float @returns_positive() @@ -926,8 +911,7 @@ define nofpclass(snan) float @known_positive_or_nan__minnum__only_zero() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive_or_nan__minnum__only_zero() { ; CHECK-NEXT: [[KNOWN_POSITIVE_OR_NAN:%.*]] = call float @returns_positive_or_nan() ; CHECK-NEXT: [[KNOWN_ZERO:%.*]] = call float @returns_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_POSITIVE_OR_NAN]], float [[KNOWN_ZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_ZERO]] ; %known.positive.or.nan = call float @returns_positive_or_nan() %known.zero = call float @returns_zero() @@ -939,8 +923,7 @@ define nofpclass(snan) float @only_zero__minnum__known_positive_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @only_zero__minnum__known_positive_or_nan() { ; CHECK-NEXT: [[KNOWN_ZERO:%.*]] = call float @returns_zero() ; CHECK-NEXT: [[KNOWN_POSITIVE_OR_NAN:%.*]] = call float @returns_positive_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_ZERO]], float [[KNOWN_POSITIVE_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_ZERO]] ; %known.zero = call float @returns_zero() %known.positive.or.nan = call float @returns_positive_or_nan() @@ -952,8 +935,7 @@ define nofpclass(snan) float @known_positive__minnum__only_nzero() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive__minnum__only_nzero() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_NZERO:%.*]] = call float @returns_nzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_NZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float -0.000000e+00 ; %known.positive = call float @returns_positive() %known.nzero = call float @returns_nzero() @@ -965,8 +947,7 @@ define nofpclass(snan) float @only_nzero__minnum__known_positive() { ; CHECK-LABEL: define nofpclass(snan) float @only_nzero__minnum__known_positive() { ; CHECK-NEXT: [[KNOWN_NZERO:%.*]] = call float @returns_nzero() ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_NZERO]], float [[KNOWN_POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float -0.000000e+00 ; %known.nzero = call float @returns_nzero() %known.positive = call float @returns_positive() @@ -1002,8 +983,7 @@ define nofpclass(snan) float @known_negative__minnum__only_zero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative__minnum__only_zero_or_nan() { ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[KNOWN_ZERO_OR_NAN:%.*]] = call float @returns_zero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_NEGATIVE]], float [[KNOWN_ZERO_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.negative = call float @returns_negative() %known.zero.or.nan = call float @returns_zero_or_nan() @@ -1015,8 +995,7 @@ define nofpclass(snan) float @only_zero_or_nan__minnum__known_negative() { ; CHECK-LABEL: define nofpclass(snan) float @only_zero_or_nan__minnum__known_negative() { ; CHECK-NEXT: [[KNOWN_ZERO_OR_NAN:%.*]] = call float @returns_zero_or_nan() ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_ZERO_OR_NAN]], float [[KNOWN_NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.zero.or.nan = call float @returns_zero_or_nan() %known.negative = call float @returns_negative() @@ -1054,8 +1033,7 @@ define nofpclass(snan) float @known_negative__minnum__only_nzero() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative__minnum__only_nzero() { ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[KNOWN_NZERO:%.*]] = call float @returns_nzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_NEGATIVE]], float [[KNOWN_NZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.negative = call float @returns_negative() %known.nzero = call float @returns_nzero() @@ -1067,8 +1045,7 @@ define nofpclass(snan) float @only_nzero__minnum__known_negative() { ; CHECK-LABEL: define nofpclass(snan) float @only_nzero__minnum__known_negative() { ; CHECK-NEXT: [[KNOWN_NZERO:%.*]] = call float @returns_nzero() ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_NZERO]], float [[KNOWN_NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.nzero = call float @returns_nzero() %known.negative = call float @returns_negative() @@ -1080,8 +1057,7 @@ define nofpclass(snan) float @known_negative__minnum__only_nzero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative__minnum__only_nzero_or_nan() { ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[KNOWN_NZERO_OR_NAN:%.*]] = call float @returns_nzero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_NEGATIVE]], float [[KNOWN_NZERO_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.negative = call float @returns_negative() %known.nzero.or.nan = call float @returns_nzero_or_nan() @@ -1093,8 +1069,7 @@ define nofpclass(snan) float @only_nzero_or_nan__minnum__known_negative() { ; CHECK-LABEL: define nofpclass(snan) float @only_nzero_or_nan__minnum__known_negative() { ; CHECK-NEXT: [[KNOWN_NZERO_OR_NAN:%.*]] = call float @returns_nzero_or_nan() ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_NZERO_OR_NAN]], float [[KNOWN_NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.nzero.or.nan = call float @returns_nzero_or_nan() %known.negative = call float @returns_negative() @@ -1106,8 +1081,7 @@ define nofpclass(snan) float @known_negative__minnum__only_pzero() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative__minnum__only_pzero() { ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[KNOWN_PZERO:%.*]] = call float @returns_pzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_NEGATIVE]], float [[KNOWN_PZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.negative = call float @returns_negative() %known.pzero = call float @returns_pzero() @@ -1119,8 +1093,7 @@ define nofpclass(snan) float @only_pzero__minnum__known_negative() { ; CHECK-LABEL: define nofpclass(snan) float @only_pzero__minnum__known_negative() { ; CHECK-NEXT: [[KNOWN_PZERO:%.*]] = call float @returns_pzero() ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_PZERO]], float [[KNOWN_NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.pzero = call float @returns_pzero() %known.negative = call float @returns_negative() @@ -1132,8 +1105,7 @@ define nofpclass(snan) float @known_negative__minnum__only_pzero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @known_negative__minnum__only_pzero_or_nan() { ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[KNOWN_PZERO_OR_NAN:%.*]] = call float @returns_pzero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_NEGATIVE]], float [[KNOWN_PZERO_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.negative = call float @returns_negative() %known.pzero.or.nan = call float @returns_pzero_or_nan() @@ -1145,8 +1117,7 @@ define nofpclass(snan) float @only_pzero_or_nan__minnum__known_negative() { ; CHECK-LABEL: define nofpclass(snan) float @only_pzero_or_nan__minnum__known_negative() { ; CHECK-NEXT: [[KNOWN_PZERO_OR_NAN:%.*]] = call float @returns_pzero_or_nan() ; CHECK-NEXT: [[KNOWN_NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_PZERO_OR_NAN]], float [[KNOWN_NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[KNOWN_NEGATIVE]] ; %known.pzero.or.nan = call float @returns_pzero_or_nan() %known.negative = call float @returns_negative() @@ -1187,7 +1158,7 @@ define nofpclass(pinf pnorm psub) float @ret_always_positive_nonzero__minnum__no ; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) { ; CHECK-NEXT: [[ALWAYS_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[SELECT_RHS:%.*]] = select i1 [[COND]], float [[ALWAYS_POSITIVE]], float [[UNKNOWN]] -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_ZERO]], float [[SELECT_RHS]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_ZERO]], float [[SELECT_RHS]]) ; CHECK-NEXT: ret float [[RESULT]] ; %always.positive = call float @returns_positive() @@ -1201,7 +1172,7 @@ define nofpclass(pinf pnorm psub) float @ret_always_positive_nonzero__minnum__no ; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]], float nofpclass(zero) [[NOT_ZERO:%.*]]) { ; CHECK-NEXT: [[ALWAYS_NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[SELECT_RHS:%.*]] = select i1 [[COND]], float [[ALWAYS_NEGATIVE]], float [[UNKNOWN]] -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_ZERO]], float [[SELECT_RHS]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_ZERO]], float [[SELECT_RHS]]) ; CHECK-NEXT: ret float [[RESULT]] ; %always.negative = call float @returns_negative() @@ -1214,7 +1185,7 @@ define nofpclass(snan) float @known_positive__minnum__only_pzero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @known_positive__minnum__only_pzero_or_nan() { ; CHECK-NEXT: [[KNOWN_POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[KNOWN_PZERO_OR_NAN:%.*]] = call float @returns_pzero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_PZERO_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[KNOWN_POSITIVE]], float [[KNOWN_PZERO_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %known.positive = call float @returns_positive() @@ -1379,7 +1350,7 @@ define nofpclass(snan) float @pinf__minnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @pinf__minnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[PINF]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000) ; CHECK-NEXT: ret float [[RESULT]] ; %pinf = call float @returns_pinf() @@ -1391,7 +1362,7 @@ define nofpclass(snan) float @unknown__minnum__pinf(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__minnum__pinf( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[PINF]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float 0x7FF0000000000000) ; CHECK-NEXT: ret float [[RESULT]] ; %pinf = call float @returns_pinf() @@ -1403,7 +1374,7 @@ define nofpclass(snan) float @pinf_or_nan__minnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @pinf_or_nan__minnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[PINF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[PINF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %pinf.or.nan = call float @returns_pinf_or_nan() @@ -1415,7 +1386,7 @@ define nofpclass(snan) float @unknown__minnum__pinf_or_nan(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__minnum__pinf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[PINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float [[PINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %pinf.or.nan = call float @returns_pinf_or_nan() @@ -1427,8 +1398,7 @@ define nofpclass(snan) float @ninf__minnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @ninf__minnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NINF]], float [[UNKNOWN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %ninf = call float @returns_ninf() %result = call float @llvm.minnum.f32(float %ninf, float %unknown) @@ -1439,8 +1409,7 @@ define nofpclass(snan) float @unknown__minnum__ninf(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__minnum__ninf( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[NINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %ninf = call float @returns_ninf() %result = call float @llvm.minnum.f32(float %unknown, float %ninf) @@ -1451,7 +1420,7 @@ define nofpclass(snan) float @ninf_or_nan__minnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @ninf_or_nan__minnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NINF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NINF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %ninf.or.nan = call float @returns_ninf_or_nan() @@ -1463,7 +1432,7 @@ define nofpclass(snan) float @unknown__minnum__ninf_or_nan(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__minnum__ninf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[NINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float [[NINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %ninf.or.nan = call float @returns_ninf_or_nan() @@ -1475,7 +1444,7 @@ define nofpclass(snan) float @inf__minnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @inf__minnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[INF:%.*]] = call float @returns_inf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[INF]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[INF]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf = call float @returns_inf() @@ -1487,7 +1456,7 @@ define nofpclass(snan) float @unknown__minnum__inf(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__minnum__inf( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[INF:%.*]] = call float @returns_inf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[INF]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float [[INF]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf = call float @returns_inf() @@ -1499,7 +1468,7 @@ define nofpclass(snan) float @inf_or_nan__minnum__unknown(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @inf_or_nan__minnum__unknown( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[INF_OR_NAN]], float [[UNKNOWN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[INF_OR_NAN]], float [[UNKNOWN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf_or_nan() @@ -1511,7 +1480,7 @@ define nofpclass(snan) float @unknown__minnum__inf_or_nan(float %unknown) { ; CHECK-LABEL: define nofpclass(snan) float @unknown__minnum__inf_or_nan( ; CHECK-SAME: float [[UNKNOWN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN]], float [[INF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[UNKNOWN]], float [[INF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf_or_nan() @@ -1523,7 +1492,7 @@ define nofpclass(snan) float @ninf_or_nan__minnum__not_nan(float nofpclass(nan) ; CHECK-LABEL: define nofpclass(snan) float @ninf_or_nan__minnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NINF_OR_NAN]], float [[NOT_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NINF_OR_NAN]], float [[NOT_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %ninf.or.nan = call float @returns_ninf_or_nan() @@ -1535,7 +1504,7 @@ define nofpclass(snan) float @not_nan__minnum__ninf_or_nan(float nofpclass(nan) ; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum__ninf_or_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN]], float [[NINF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_NAN]], float [[NINF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %ninf.or.nan = call float @returns_ninf_or_nan() @@ -1547,8 +1516,7 @@ define nofpclass(snan) float @pinf_or_nan__minnum__not_nan(float nofpclass(nan) ; CHECK-LABEL: define nofpclass(snan) float @pinf_or_nan__minnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[PINF_OR_NAN]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %pinf.or.nan = call float @returns_pinf_or_nan() %result = call float @llvm.minnum.f32(float %pinf.or.nan, float %not.nan) @@ -1559,8 +1527,7 @@ define nofpclass(snan) float @not_nan__minnum__pinf_or_nan(float nofpclass(nan) ; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum__pinf_or_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN]], float [[PINF_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %pinf.or.nan = call float @returns_pinf_or_nan() %result = call float @llvm.minnum.f32(float %not.nan, float %pinf.or.nan) @@ -1571,7 +1538,7 @@ define nofpclass(snan) float @inf_or_nan__minnum__not_nan(float nofpclass(nan) % ; CHECK-LABEL: define nofpclass(snan) float @inf_or_nan__minnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[INF_OR_NAN]], float [[NOT_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[INF_OR_NAN]], float [[NOT_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf_or_nan() @@ -1583,7 +1550,7 @@ define nofpclass(snan) float @not_nan__minnum__inf_or_nan(float nofpclass(nan) % ; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum__inf_or_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN]], float [[INF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NOT_NAN]], float [[INF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf_or_nan() @@ -1595,8 +1562,7 @@ define nofpclass(snan) float @ninf__minnum__not_nan(float nofpclass(nan) %not.na ; CHECK-LABEL: define nofpclass(snan) float @ninf__minnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NINF_OR_NAN]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %ninf.or.nan = call float @returns_ninf() %result = call float @llvm.minnum.f32(float %ninf.or.nan, float %not.nan) @@ -1607,8 +1573,7 @@ define nofpclass(snan) float @not_nan__minnum__ninf(float nofpclass(nan) %not.na ; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum__ninf( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[NINF_OR_NAN:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN]], float [[NINF_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %ninf.or.nan = call float @returns_ninf() %result = call float @llvm.minnum.f32(float %not.nan, float %ninf.or.nan) @@ -1619,8 +1584,7 @@ define nofpclass(snan) float @pinf__minnum__not_nan(float nofpclass(nan) %not.na ; CHECK-LABEL: define nofpclass(snan) float @pinf__minnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[PINF_OR_NAN]], float [[NOT_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %pinf.or.nan = call float @returns_pinf() %result = call float @llvm.minnum.f32(float %pinf.or.nan, float %not.nan) @@ -1631,8 +1595,7 @@ define nofpclass(snan) float @not_nan__minnum__pinf(float nofpclass(nan) %not.na ; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum__pinf( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[PINF_OR_NAN:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN]], float [[PINF_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NOT_NAN]] ; %pinf.or.nan = call float @returns_pinf() %result = call float @llvm.minnum.f32(float %not.nan, float %pinf.or.nan) @@ -1643,7 +1606,7 @@ define nofpclass(snan) float @inf__minnum__not_nan(float nofpclass(nan) %not.nan ; CHECK-LABEL: define nofpclass(snan) float @inf__minnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[INF_OR_NAN]], float [[NOT_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan nsz float @llvm.minnum.f32(float [[INF_OR_NAN]], float [[NOT_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf() @@ -1655,7 +1618,7 @@ define nofpclass(snan) float @not_nan__minnum__inf(float nofpclass(nan) %not.nan ; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum__inf( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN:%.*]]) { ; CHECK-NEXT: [[INF_OR_NAN:%.*]] = call float @returns_inf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN]], float [[INF_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan nsz float @llvm.minnum.f32(float [[NOT_NAN]], float [[INF_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %inf.or.nan = call float @returns_inf() @@ -1696,7 +1659,7 @@ define nofpclass(snan) float @unknown__noundef_minnum__not_nan(float %unknown, f define nofpclass(snan) float @not_nan__noundef_minnum__not_nan(float nofpclass(nan) %not.nan0, float nofpclass(nan) %not.nan1) { ; CHECK-LABEL: define nofpclass(snan) float @not_nan__noundef_minnum__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN0:%.*]], float nofpclass(nan) [[NOT_NAN1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call noundef float @llvm.minnum.f32(float [[NOT_NAN0]], float [[NOT_NAN1]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.minnum.f32(float [[NOT_NAN0]], float [[NOT_NAN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call noundef float @llvm.minnum.f32(float %not.nan0, float %not.nan1) @@ -1756,7 +1719,7 @@ define nofpclass(inf) float @not_inf__noundef_minnum__not_inf(float nofpclass(in define nofpclass(snan) float @not_nan__minnum_noundef_md__not_nan(float nofpclass(nan) %not.nan0, float nofpclass(nan) %not.nan1) { ; CHECK-LABEL: define nofpclass(snan) float @not_nan__minnum_noundef_md__not_nan( ; CHECK-SAME: float nofpclass(nan) [[NOT_NAN0:%.*]], float nofpclass(nan) [[NOT_NAN1:%.*]]) { -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NOT_NAN0]], float [[NOT_NAN1]]), !noundef [[META0:![0-9]+]], !unknown.md [[META0]] +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.minnum.f32(float [[NOT_NAN0]], float [[NOT_NAN1]]) ; CHECK-NEXT: ret float [[RESULT]] ; %result = call float @llvm.minnum.f32(float %not.nan0, float %not.nan1), !noundef !0, !unknown.md !0 @@ -1767,11 +1730,8 @@ define nofpclass(snan) float @not_nan__minnum_noundef_md__not_nan(float nofpclas define nofpclass(snan) float @select_is_positive_or_0__minnum__nnorm_0(float noundef %arg) { ; CHECK-LABEL: define nofpclass(snan) float @select_is_positive_or_0__minnum__nnorm_0( ; CHECK-SAME: float noundef [[ARG:%.*]]) { -; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: [[NNORM:%.*]] = call float @returns_nnorm() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[SELECT]], float [[NNORM]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NNORM]] ; %is.pos.or.zero = fcmp oge float %arg, 0.0 %select = select i1 %is.pos.or.zero, float %arg, float 0.0 @@ -1784,10 +1744,7 @@ define nofpclass(snan) float @select_is_positive_or_0__minnum__nnorm_1(float nou ; CHECK-LABEL: define nofpclass(snan) float @select_is_positive_or_0__minnum__nnorm_1( ; CHECK-SAME: float noundef [[ARG:%.*]]) { ; CHECK-NEXT: [[NNORM:%.*]] = call float @returns_nnorm() -; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NNORM]], float [[SELECT]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NNORM]] ; %nnorm = call float @returns_nnorm() %is.pos.or.zero = fcmp oge float %arg, 0.0 @@ -1802,7 +1759,7 @@ define nofpclass(snan) float @select_is_positive_or_0__minnum__nnorm_or_nan_0(fl ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: [[NNORM_OR_NAN:%.*]] = call float @returns_nnorm_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[SELECT]], float [[NNORM_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[SELECT]], float [[NNORM_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %is.pos.or.zero = fcmp oge float %arg, 0.0 @@ -1818,7 +1775,7 @@ define nofpclass(snan) float @select_is_positive_or_0__minnum__nnorm_or_nan_1(fl ; CHECK-NEXT: [[NNORM_OR_NAN:%.*]] = call float @returns_nnorm_or_nan() ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NNORM_OR_NAN]], float [[SELECT]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NNORM_OR_NAN]], float [[SELECT]]) ; CHECK-NEXT: ret float [[RESULT]] ; %nnorm.or.nan = call float @returns_nnorm_or_nan() @@ -1831,11 +1788,8 @@ define nofpclass(snan) float @select_is_positive_or_0__minnum__nnorm_or_nan_1(fl define nofpclass(snan) float @select_is_positive_or_0__minnum__negative(float noundef %arg) { ; CHECK-LABEL: define nofpclass(snan) float @select_is_positive_or_0__minnum__negative( ; CHECK-SAME: float noundef [[ARG:%.*]]) { -; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[SELECT]], float [[NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEGATIVE]] ; %is.pos.or.zero = fcmp oge float %arg, 0.0 %select = select i1 %is.pos.or.zero, float %arg, float 0.0 @@ -1848,10 +1802,7 @@ define nofpclass(snan) float @negative__minnum__select_is_positive_or_0(float no ; CHECK-LABEL: define nofpclass(snan) float @negative__minnum__select_is_positive_or_0( ; CHECK-SAME: float noundef [[ARG:%.*]]) { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 -; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NEGATIVE]], float [[SELECT]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEGATIVE]] ; %negative = call float @returns_negative() %is.pos.or.zero = fcmp oge float %arg, 0.0 @@ -1866,7 +1817,7 @@ define nofpclass(snan) float @select_is_positive_or_0__minnum__negative_or_zero( ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 ; CHECK-NEXT: [[NEGATIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[SELECT]], float [[NEGATIVE_OR_ZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.minnum.f32(float [[SELECT]], float [[NEGATIVE_OR_ZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %is.pos.or.zero = fcmp oge float %arg, 0.0 @@ -1882,7 +1833,7 @@ define nofpclass(snan) float @negative_or_zero__minnum__select_is_positive_or_0( ; CHECK-NEXT: [[NEGATIVE_OR_ZERO:%.*]] = call float @returns_negative_or_zero() ; CHECK-NEXT: [[IS_POS_OR_ZERO:%.*]] = fcmp oge float [[ARG]], 0.000000e+00 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[IS_POS_OR_ZERO]], float [[ARG]], float 0.000000e+00 -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NEGATIVE_OR_ZERO]], float [[SELECT]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nnan float @llvm.minnum.f32(float [[NEGATIVE_OR_ZERO]], float [[SELECT]]) ; CHECK-NEXT: ret float [[RESULT]] ; %negative.or.zero = call float @returns_negative_or_zero() @@ -1896,8 +1847,7 @@ define nofpclass(snan) float @negative_or_zero__minnum__positive() { ; CHECK-LABEL: define nofpclass(snan) float @negative_or_zero__minnum__positive() { ; CHECK-NEXT: [[NEG_NONZERO:%.*]] = call float @returns_negative_nonzero() ; CHECK-NEXT: [[POSITIVE:%.*]] = call float @returns_positive() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NEG_NONZERO]], float [[POSITIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEG_NONZERO]] ; %neg.nonzero = call float @returns_negative_nonzero() %positive = call float @returns_positive() @@ -1909,8 +1859,7 @@ define nofpclass(snan) float @positive__minnum__negative_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @positive__minnum__negative_or_zero() { ; CHECK-NEXT: [[POSITIVE:%.*]] = call float @returns_positive() ; CHECK-NEXT: [[NEG_NONZERO:%.*]] = call float @returns_negative_nonzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[POSITIVE]], float [[NEG_NONZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEG_NONZERO]] ; %positive = call float @returns_positive() %neg.nonzero = call float @returns_negative_nonzero() @@ -1922,8 +1871,7 @@ define nofpclass(snan) float @negative_or_zero__minnum__positive_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @negative_or_zero__minnum__positive_or_zero() { ; CHECK-NEXT: [[NEG_NONZERO:%.*]] = call float @returns_negative_nonzero() ; CHECK-NEXT: [[POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NEG_NONZERO]], float [[POSITIVE_OR_ZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEG_NONZERO]] ; %neg.nonzero = call float @returns_negative_nonzero() %positive.or.zero = call float @returns_positive_or_zero() @@ -1935,8 +1883,7 @@ define nofpclass(snan) float @positive_or_zero__minnum__negative_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @positive_or_zero__minnum__negative_or_zero() { ; CHECK-NEXT: [[POSITIVE_OR_ZERO:%.*]] = call float @returns_positive_or_zero() ; CHECK-NEXT: [[NEG_NONZERO:%.*]] = call float @returns_negative_nonzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[POSITIVE_OR_ZERO]], float [[NEG_NONZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEG_NONZERO]] ; %positive.or.zero = call float @returns_positive_or_zero() %neg.nonzero = call float @returns_negative_nonzero() @@ -1948,8 +1895,7 @@ define nofpclass(snan) float @positive_or_zero__minnum__negative() { ; CHECK-LABEL: define nofpclass(snan) float @positive_or_zero__minnum__negative() { ; CHECK-NEXT: [[POS_NONZERO:%.*]] = call float @returns_positive_nonzero() ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[POS_NONZERO]], float [[NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEGATIVE]] ; %pos.nonzero = call float @returns_positive_nonzero() %negative = call float @returns_negative() @@ -1961,8 +1907,7 @@ define nofpclass(snan) float @negative__minnum__positive_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @negative__minnum__positive_or_zero() { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[POS_NONZERO:%.*]] = call float @returns_positive_nonzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NEGATIVE]], float [[POS_NONZERO]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEGATIVE]] ; %negative = call float @returns_negative() %pos.nonzero = call float @returns_positive_nonzero() @@ -1974,7 +1919,7 @@ define nofpclass(snan) float @positive_or_zero__minnum__negative_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @positive_or_zero__minnum__negative_or_nan() { ; CHECK-NEXT: [[POS_NONZERO:%.*]] = call float @returns_positive_nonzero() ; CHECK-NEXT: [[NEGATIVE_OR_NAN:%.*]] = call float @returns_negative_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[POS_NONZERO]], float [[NEGATIVE_OR_NAN]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[POS_NONZERO]], float [[NEGATIVE_OR_NAN]]) ; CHECK-NEXT: ret float [[RESULT]] ; %pos.nonzero = call float @returns_positive_nonzero() @@ -1987,7 +1932,7 @@ define nofpclass(snan) float @negative_or_nan__minnum__positive_or_zero() { ; CHECK-LABEL: define nofpclass(snan) float @negative_or_nan__minnum__positive_or_zero() { ; CHECK-NEXT: [[NEGATIVE_OR_NAN:%.*]] = call float @returns_negative_or_nan() ; CHECK-NEXT: [[POS_NONZERO:%.*]] = call float @returns_positive_nonzero() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NEGATIVE_OR_NAN]], float [[POS_NONZERO]]) +; CHECK-NEXT: [[RESULT:%.*]] = call nsz float @llvm.minnum.f32(float [[NEGATIVE_OR_NAN]], float [[POS_NONZERO]]) ; CHECK-NEXT: ret float [[RESULT]] ; %negative.or.nan = call float @returns_negative_or_nan() @@ -2000,8 +1945,7 @@ define nofpclass(snan) float @positive_or_zero_or_nan__minnum__negative() { ; CHECK-LABEL: define nofpclass(snan) float @positive_or_zero_or_nan__minnum__negative() { ; CHECK-NEXT: [[POS_NONZERO_OR_NAN:%.*]] = call float @returns_positive_nonzero_or_nan() ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[POS_NONZERO_OR_NAN]], float [[NEGATIVE]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEGATIVE]] ; %pos.nonzero.or.nan = call float @returns_positive_nonzero_or_nan() %negative = call float @returns_negative() @@ -2013,8 +1957,7 @@ define nofpclass(snan) float @negative__minnum__positive_or_zero_or_nan() { ; CHECK-LABEL: define nofpclass(snan) float @negative__minnum__positive_or_zero_or_nan() { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[POS_NONZERO_OR_NAN:%.*]] = call float @returns_positive_nonzero_or_nan() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NEGATIVE]], float [[POS_NONZERO_OR_NAN]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NEGATIVE]] ; %negative = call float @returns_negative() %pos.nonzero.or.nan = call float @returns_positive_nonzero_or_nan() @@ -2026,8 +1969,7 @@ define nofpclass(snan) float @known_pnorm__minnum__known_psub() { ; CHECK-LABEL: define nofpclass(snan) float @known_pnorm__minnum__known_psub() { ; CHECK-NEXT: [[PNORM:%.*]] = call float @returns_pnorm() ; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[PNORM]], float [[PSUB]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[PSUB]] ; %pnorm = call float @returns_pnorm() %psub = call float @returns_psub() @@ -2039,8 +1981,7 @@ define nofpclass(snan) float @known_psub__minnum__known_pnorm() { ; CHECK-LABEL: define nofpclass(snan) float @known_psub__minnum__known_pnorm() { ; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub() ; CHECK-NEXT: [[PNORM:%.*]] = call float @returns_pnorm() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[PSUB]], float [[PNORM]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[PSUB]] ; %psub = call float @returns_psub() %pnorm = call float @returns_pnorm() @@ -2052,8 +1993,7 @@ define nofpclass(snan) float @known_pinf__minnum__known_psub() { ; CHECK-LABEL: define nofpclass(snan) float @known_pinf__minnum__known_psub() { ; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf() ; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[PINF]], float [[PSUB]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[PSUB]] ; %pinf = call float @returns_pinf() %psub = call float @returns_psub() @@ -2065,8 +2005,7 @@ define nofpclass(snan) float @known_psub__minnum__known_pinf() { ; CHECK-LABEL: define nofpclass(snan) float @known_psub__minnum__known_pinf() { ; CHECK-NEXT: [[PSUB:%.*]] = call float @returns_psub() ; CHECK-NEXT: [[PINF:%.*]] = call float @returns_pinf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[PSUB]], float [[PINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[PSUB]] ; %psub = call float @returns_psub() %pinf = call float @returns_pinf() @@ -2078,8 +2017,7 @@ define nofpclass(snan) float @known_nnorm__minnum__known_nsub() { ; CHECK-LABEL: define nofpclass(snan) float @known_nnorm__minnum__known_nsub() { ; CHECK-NEXT: [[NNORM:%.*]] = call float @returns_nnorm() ; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NNORM]], float [[NSUB]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NNORM]] ; %nnorm = call float @returns_nnorm() %nsub = call float @returns_nsub() @@ -2091,8 +2029,7 @@ define nofpclass(snan) float @known_nsub__minnum__known_nnorm() { ; CHECK-LABEL: define nofpclass(snan) float @known_nsub__minnum__known_nnorm() { ; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub() ; CHECK-NEXT: [[NNORM:%.*]] = call float @returns_nnorm() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NSUB]], float [[NNORM]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float [[NNORM]] ; %nsub = call float @returns_nsub() %nnorm = call float @returns_nnorm() @@ -2104,8 +2041,7 @@ define nofpclass(snan) float @known_ninf__minnum__known_nsub() { ; CHECK-LABEL: define nofpclass(snan) float @known_ninf__minnum__known_nsub() { ; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf() ; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NINF]], float [[NSUB]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %ninf = call float @returns_ninf() %nsub = call float @returns_nsub() @@ -2117,8 +2053,7 @@ define nofpclass(snan) float @known_nsub__minnum__known_ninf() { ; CHECK-LABEL: define nofpclass(snan) float @known_nsub__minnum__known_ninf() { ; CHECK-NEXT: [[NSUB:%.*]] = call float @returns_nsub() ; CHECK-NEXT: [[NINF:%.*]] = call float @returns_ninf() -; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[NSUB]], float [[NINF]]) -; CHECK-NEXT: ret float [[RESULT]] +; CHECK-NEXT: ret float 0xFFF0000000000000 ; %nsub = call float @returns_nsub() %ninf = call float @returns_ninf() @@ -2133,7 +2068,7 @@ define nofpclass(snan) float @simplify_multiple_use_minnum(ptr %ptr) { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[POSITIVE]], float [[NEGATIVE]]) ; CHECK-NEXT: store float [[MIN]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MIN]] +; CHECK-NEXT: ret float [[NEGATIVE]] ; %positive = call float @returns_positive() %negative = call float @returns_negative() @@ -2149,7 +2084,7 @@ define nofpclass(snan) float @simplify_multiple_use_minnum_commute(ptr %ptr) { ; CHECK-NEXT: [[NEGATIVE:%.*]] = call float @returns_negative() ; CHECK-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[NEGATIVE]], float [[POSITIVE]]) ; CHECK-NEXT: store float [[MIN]], ptr [[PTR]], align 4 -; CHECK-NEXT: ret float [[MIN]] +; CHECK-NEXT: ret float [[NEGATIVE]] ; %positive = call float @returns_positive() %negative = call float @returns_negative() @@ -2222,10 +2157,35 @@ define nofpclass(snan) float @cannot_fold_negative_or_zero__positive_or_zero_1__ ret float %result } +define nofpclass(snan) float @qnan_result_demands_snan_lhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_lhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[SELECT]], float [[UNKNOWN1]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.minnum.f32(float %select, float %unknown1) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_rhs(i1 %cond, float %unknown0, float %unknown1) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_rhs( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN0:%.*]], float [[UNKNOWN1:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN0]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.minnum.f32(float [[UNKNOWN1]], float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown0 + %result = call float @llvm.minnum.f32(float %unknown1, float %select) + ret float %result +} + !0 = !{} -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } -;. -; CHECK: [[META0]] = !{} -;. +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll index fda9300c3bd1c..e487b400d87b9 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-rounding-intrinsics.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 ; RUN: opt -S -passes=instcombine < %s | FileCheck %s +declare nofpclass(qnan inf norm sub zero) float @returns_snan() + define nofpclass(snan) float @ret_no_snan__floor_no_snan(float nofpclass(nan) %x) { ; CHECK-LABEL: define nofpclass(snan) float @ret_no_snan__floor_no_snan( ; CHECK-SAME: float nofpclass(nan) [[X:%.*]]) { @@ -1241,3 +1243,101 @@ define nofpclass(nan) float @ret_non_nan__floor__drop_noundef(float %x) { %result = call noundef float @llvm.floor.f32(float %x), !unknown.md !{} ret float %result } + +define nofpclass(snan) float @qnan_result_demands_snan_src__trunc(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src__trunc( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.trunc.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.trunc.f32(float %select) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_src__floor(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src__floor( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.floor.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.floor.f32(float %select) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_src__ceil(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src__ceil( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.ceil.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.ceil.f32(float %select) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_src__rint(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src__rint( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.rint.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.rint.f32(float %select) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_src__nearbyint(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src__nearbyint( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.nearbyint.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.nearbyint.f32(float %select) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_src__round(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src__round( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.round.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.round.f32(float %select) + ret float %result +} + +define nofpclass(snan) float @qnan_result_demands_snan_src__roundeven(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src__roundeven( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.roundeven.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.roundeven.f32(float %select) + ret float %result +} diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll index 7a05e27d88184..dc24630c43231 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-sqrt.ll @@ -12,7 +12,7 @@ declare nofpclass(pinf pnorm psub pzero) float @returns_negative_or_nan() declare nofpclass(pinf pnorm psub zero nan) float @returns_negative_nonzero() declare nofpclass(pinf pnorm psub zero nan) <2 x float> @returns_negative_nonzero_vec() declare nofpclass(pinf pnorm psub zero) float @returns_negative_nonzero_or_nan() - +declare nofpclass(qnan inf norm sub zero) float @returns_snan() ; -> qnan define nofpclass(inf norm sub zero) float @ret_only_nan_sqrt(float %x) { @@ -345,5 +345,19 @@ define nofpclass(nan) float @ret_no_nan__sqrt__no_inf_inputs(float nofpclass(inf ret float %result } -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #1 = { "denormal-fp-math"="dynamic,dynamic" } +define nofpclass(snan) float @qnan_result_demands_snan_src(i1 %cond, float %unknown) { +; CHECK-LABEL: define nofpclass(snan) float @qnan_result_demands_snan_src( +; CHECK-SAME: i1 [[COND:%.*]], float [[UNKNOWN:%.*]]) { +; CHECK-NEXT: [[SNAN:%.*]] = call float @returns_snan() +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], float [[SNAN]], float [[UNKNOWN]] +; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.sqrt.f32(float [[SELECT]]) +; CHECK-NEXT: ret float [[RESULT]] +; + %snan = call float @returns_snan() + %select = select i1 %cond, float %snan, float %unknown + %result = call float @llvm.sqrt.f32(float %select) + ret float %result +} + +attributes #0 = { denormal_fpenv(preservesign) } +attributes #1 = { denormal_fpenv(dynamic) } diff --git a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll index 1c3ccf734b6a3..23b7cbc246d2a 100644 --- a/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll +++ b/llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll @@ -1879,7 +1879,7 @@ define nofpclass(snan) float @arithmetic_fence__noinf_callsite_param_attr_select define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_pinf(i1 %cond, float %x) { ; CHECK-LABEL: define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_pinf ; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) { -; CHECK-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[X]], float 0x7FF0000000000000) +; CHECK-NEXT: [[MIN:%.*]] = call nsz float @llvm.minnum.f32(float [[X]], float 0x7FF0000000000000) ; CHECK-NEXT: ret float [[MIN]] ; %min = call float @llvm.minnum.f32(float %x, float 0x7FF0000000000000) @@ -1900,7 +1900,7 @@ define nofpclass(pinf) float @ret_nofpclass_pinf__minnum_ninf(i1 %cond, float %x define nofpclass(ninf) float @ret_nofpclass_ninf__maxnum_ninf(i1 %cond, float %x) { ; CHECK-LABEL: define nofpclass(ninf) float @ret_nofpclass_ninf__maxnum_ninf ; CHECK-SAME: (i1 [[COND:%.*]], float [[X:%.*]]) { -; CHECK-NEXT: [[MAX:%.*]] = call float @llvm.maxnum.f32(float [[X]], float 0xFFF0000000000000) +; CHECK-NEXT: [[MAX:%.*]] = call nsz float @llvm.maxnum.f32(float [[X]], float 0xFFF0000000000000) ; CHECK-NEXT: ret float [[MAX]] ; %max = call float @llvm.maxnum.f32(float %x, float 0xFFF0000000000000) diff --git a/llvm/test/Transforms/InstCombine/sqrt.ll b/llvm/test/Transforms/InstCombine/sqrt.ll index 2fda5bc37d023..0a1aa21c04696 100644 --- a/llvm/test/Transforms/InstCombine/sqrt.ll +++ b/llvm/test/Transforms/InstCombine/sqrt.ll @@ -16,7 +16,7 @@ define float @test1(float %x) nounwind readnone ssp { define float @test2(float %x) nounwind readnone ssp { ; CHECK-LABEL: @test2( -; CHECK-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[X:%.*]]) #[[ATTR4]] +; CHECK-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[X:%.*]]) #[[ATTR5:[0-9]+]] ; CHECK-NEXT: ret float [[SQRTF]] ; %conv = fpext float %x to double @@ -32,7 +32,7 @@ define float @test2(float %x) nounwind readnone ssp { define float @test3(ptr %v) nounwind uwtable ssp { ; CHECK-LABEL: @test3( ; CHECK-NEXT: [[CALL34:%.*]] = call double @sqrt(double 0x7FF8000000000000) #[[ATTR4]] -; CHECK-NEXT: [[CALL36:%.*]] = call i32 @foo(double [[CALL34]]) #[[ATTR5:[0-9]+]] +; CHECK-NEXT: [[CALL36:%.*]] = call i32 @foo(double [[CALL34]]) #[[ATTR5]] ; CHECK-NEXT: [[CONV38:%.*]] = fptrunc double [[CALL34]] to float ; CHECK-NEXT: ret float [[CONV38]] ; @@ -51,7 +51,7 @@ define float @test3(ptr %v) nounwind uwtable ssp { define void @0(float %f) { ; CHECK-LABEL: @0( -; CHECK-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[F:%.*]]) #[[ATTR2:[0-9]+]] +; CHECK-NEXT: [[SQRTF:%.*]] = call float @sqrtf(float [[F:%.*]]) ; CHECK-NEXT: ret void ; %d = fpext float %f to double diff --git a/llvm/test/Transforms/InstCombine/trunc-extractelement.ll b/llvm/test/Transforms/InstCombine/trunc-extractelement.ll index ba2d07009d9c7..074b5b35d7f2d 100644 --- a/llvm/test/Transforms/InstCombine/trunc-extractelement.ll +++ b/llvm/test/Transforms/InstCombine/trunc-extractelement.ll @@ -296,3 +296,37 @@ define <4 x i64> @PR45314(<4 x i64> %x) { %b = bitcast <8 x i32> %s to <4 x i64> ret <4 x i64> %b } + +; Make sure we don't overflow when computing the new index. +define i16 @test_overflow_idx1( %vec) { +; ANY-LABEL: @test_overflow_idx1( +; ANY-NEXT: entry: +; ANY-NEXT: [[EXT:%.*]] = extractelement [[VEC:%.*]], i64 -1 +; ANY-NEXT: [[TRUNC:%.*]] = trunc i32 [[EXT]] to i16 +; ANY-NEXT: ret i16 [[TRUNC]] +; +entry: + %ext = extractelement %vec, i64 -1 + %trunc = trunc i32 %ext to i16 + ret i16 %trunc +} + +; Make sure we don't overflow when computing the new index. +define i16 @test_overflow_idx2( %vec) { +; LE-LABEL: @test_overflow_idx2( +; LE-NEXT: entry: +; LE-NEXT: [[TMP0:%.*]] = bitcast [[VEC:%.*]] to +; LE-NEXT: [[TRUNC:%.*]] = extractelement [[TMP0]], i64 4294967296 +; LE-NEXT: ret i16 [[TRUNC]] +; +; BE-LABEL: @test_overflow_idx2( +; BE-NEXT: entry: +; BE-NEXT: [[TMP0:%.*]] = bitcast [[VEC:%.*]] to +; BE-NEXT: [[TRUNC:%.*]] = extractelement [[TMP0]], i64 4294967297 +; BE-NEXT: ret i16 [[TRUNC]] +; +entry: + %ext = extractelement %vec, i32 2147483648 + %trunc = trunc i32 %ext to i16 + ret i16 %trunc +} diff --git a/llvm/test/Transforms/InstCombine/vector-splice.ll b/llvm/test/Transforms/InstCombine/vector-splice.ll new file mode 100644 index 0000000000000..902ae96181a71 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/vector-splice.ll @@ -0,0 +1,123 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -p instcombine -S | FileCheck %s + +define <4 x i32> @binop_splice_left(<4 x i32> %v1, <4 x i32> %v2, i32 %offset) { +; CHECK-LABEL: define <4 x i32> @binop_splice_left( +; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET:%.*]]) { +; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[V2]] +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]]) +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %splice1 = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset) + %splice2 = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v2, <4 x i32> poison, i32 %offset) + %res = add <4 x i32> %splice1, %splice2 + ret <4 x i32> %res +} + +define <4 x i32> @binop_splice_left_rhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) { +; CHECK-LABEL: define <4 x i32> @binop_splice_left_rhs_splat( +; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) { +; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0 +; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[SPLAT]] +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]]) +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %splice = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset) + %head = insertelement <4 x i32> poison, i32 %x, i32 0 + %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer + %res = add <4 x i32> %splice, %splat + ret <4 x i32> %res +} + +define <4 x i32> @binop_splice_left_lhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) { +; CHECK-LABEL: define <4 x i32> @binop_splice_left_lhs_splat( +; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) { +; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0 +; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[SPLAT]], [[V1]] +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]]) +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %splice = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset) + %head = insertelement <4 x i32> poison, i32 %x, i32 0 + %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer + %res = add <4 x i32> %splat, %splice + ret <4 x i32> %res +} + +define <4 x i32> @binop_splice_right(<4 x i32> %v1, <4 x i32> %v2, i32 %offset) { +; CHECK-LABEL: define <4 x i32> @binop_splice_right( +; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET:%.*]]) { +; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[V2]] +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]]) +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset) + %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> poison, i32 %offset) + %res = add <4 x i32> %splice1, %splice2 + ret <4 x i32> %res +} + +define <4 x i32> @binop_splice_right_rhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) { +; CHECK-LABEL: define <4 x i32> @binop_splice_right_rhs_splat( +; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) { +; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0 +; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[SPLAT]] +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]]) +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %splice = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset) + %head = insertelement <4 x i32> poison, i32 %x, i32 0 + %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer + %res = add <4 x i32> %splice, %splat + ret <4 x i32> %res +} + +define <4 x i32> @binop_splice_right_lhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) { +; CHECK-LABEL: define <4 x i32> @binop_splice_right_lhs_splat( +; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) { +; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0 +; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[SPLAT]], [[V1]] +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]]) +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %splice = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset) + %head = insertelement <4 x i32> poison, i32 %x, i32 0 + %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer + %res = add <4 x i32> %splat, %splice + ret <4 x i32> %res +} + +; Negative test, mismatched offset +define <4 x i32> @binop_splice_mismatched_offset(<4 x i32> %v1, <4 x i32> %v2, i32 %offset1, i32 %offset2) { +; CHECK-LABEL: define <4 x i32> @binop_splice_mismatched_offset( +; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET1:%.*]], i32 [[OFFSET2:%.*]]) { +; CHECK-NEXT: [[SPLICE1:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V1]], <4 x i32> poison, i32 [[OFFSET1]]) +; CHECK-NEXT: [[SPLICE2:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V2]], <4 x i32> poison, i32 [[OFFSET2]]) +; CHECK-NEXT: [[RES:%.*]] = add <4 x i32> [[SPLICE1]], [[SPLICE2]] +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset1) + %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> poison, i32 %offset2) + %res = add <4 x i32> %splice1, %splice2 + ret <4 x i32> %res +} + +; Negative test, non poison vector operand +define <4 x i32> @binop_splice_mismatched_vector(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, i32 %offset) { +; CHECK-LABEL: define <4 x i32> @binop_splice_mismatched_vector( +; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], <4 x i32> [[V3:%.*]], i32 [[OFFSET:%.*]]) { +; CHECK-NEXT: [[SPLICE1:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V1]], <4 x i32> [[V3]], i32 [[OFFSET]]) +; CHECK-NEXT: [[SPLICE2:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V2]], <4 x i32> [[V3]], i32 [[OFFSET]]) +; CHECK-NEXT: [[RES:%.*]] = add <4 x i32> [[SPLICE1]], [[SPLICE2]] +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> %v3, i32 %offset) + %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> %v3, i32 %offset) + %res = add <4 x i32> %splice1, %splice2 + ret <4 x i32> %res +} + diff --git a/llvm/test/Transforms/InstSimplify/canonicalize.ll b/llvm/test/Transforms/InstSimplify/canonicalize.ll index 9d2bdd1b853e6..15c45b34826ca 100644 --- a/llvm/test/Transforms/InstSimplify/canonicalize.ll +++ b/llvm/test/Transforms/InstSimplify/canonicalize.ll @@ -81,7 +81,7 @@ define float @canonicalize_denorm() { ret float %ret } -define float @canonicalize_pos_denorm_preserve_sign_output() "denormal-fp-math"="preserve-sign,ieee" { +define float @canonicalize_pos_denorm_preserve_sign_output() denormal_fpenv(preservesign|ieee) { ; CHECK-LABEL: @canonicalize_pos_denorm_preserve_sign_output( ; CHECK-NEXT: ret float 0.000000e+00 ; @@ -89,7 +89,7 @@ define float @canonicalize_pos_denorm_preserve_sign_output() "denormal-fp-math"= ret float %ret } -define float @canonicalize_pos_denorm_preserve_sign_input() "denormal-fp-math"="ieee,preserve-sign" { +define float @canonicalize_pos_denorm_preserve_sign_input() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @canonicalize_pos_denorm_preserve_sign_input( ; CHECK-NEXT: ret float 0.000000e+00 ; @@ -97,7 +97,7 @@ define float @canonicalize_pos_denorm_preserve_sign_input() "denormal-fp-math"=" ret float %ret } -define float @canonicalize_neg_denorm_preserve_sign_output() "denormal-fp-math"="preserve-sign,ieee" { +define float @canonicalize_neg_denorm_preserve_sign_output() denormal_fpenv(preservesign|ieee) { ; CHECK-LABEL: @canonicalize_neg_denorm_preserve_sign_output( ; CHECK-NEXT: ret float -0.000000e+00 ; @@ -105,7 +105,7 @@ define float @canonicalize_neg_denorm_preserve_sign_output() "denormal-fp-math"= ret float %ret } -define float @canonicalize_neg_denorm_preserve_sign_input() "denormal-fp-math"="ieee,preserve-sign" { +define float @canonicalize_neg_denorm_preserve_sign_input() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @canonicalize_neg_denorm_preserve_sign_input( ; CHECK-NEXT: ret float -0.000000e+00 ; @@ -113,7 +113,7 @@ define float @canonicalize_neg_denorm_preserve_sign_input() "denormal-fp-math"=" ret float %ret } -define float @canonicalize_pos_denorm_positive_zero_output() "denormal-fp-math"="positive-zero,ieee" { +define float @canonicalize_pos_denorm_positive_zero_output() denormal_fpenv(positivezero|ieee) { ; CHECK-LABEL: @canonicalize_pos_denorm_positive_zero_output( ; CHECK-NEXT: ret float 0.000000e+00 ; @@ -121,7 +121,7 @@ define float @canonicalize_pos_denorm_positive_zero_output() "denormal-fp-math"= ret float %ret } -define float @canonicalize_pos_denorm_positive_zero_input() "denormal-fp-math"="ieee,positive-zero" { +define float @canonicalize_pos_denorm_positive_zero_input() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @canonicalize_pos_denorm_positive_zero_input( ; CHECK-NEXT: ret float 0.000000e+00 ; @@ -129,7 +129,7 @@ define float @canonicalize_pos_denorm_positive_zero_input() "denormal-fp-math"=" ret float %ret } -define float @canonicalize_neg_denorm_positive_zero_output() "denormal-fp-math"="positive-zero,ieee" { +define float @canonicalize_neg_denorm_positive_zero_output() denormal_fpenv(positivezero|ieee) { ; CHECK-LABEL: @canonicalize_neg_denorm_positive_zero_output( ; CHECK-NEXT: ret float 0.000000e+00 ; @@ -137,7 +137,7 @@ define float @canonicalize_neg_denorm_positive_zero_output() "denormal-fp-math"= ret float %ret } -define float @canonicalize_neg_denorm_positive_zero_input() "denormal-fp-math"="ieee,positive-zero" { +define float @canonicalize_neg_denorm_positive_zero_input() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @canonicalize_neg_denorm_positive_zero_input( ; CHECK-NEXT: ret float 0.000000e+00 ; @@ -145,7 +145,7 @@ define float @canonicalize_neg_denorm_positive_zero_input() "denormal-fp-math"=" ret float %ret } -define float @canonicalize_pos_denorm_dynamic_dynamic() "denormal-fp-math"="dynamic,dynamic" { +define float @canonicalize_pos_denorm_dynamic_dynamic() denormal_fpenv(dynamic) { ; CHECK-LABEL: @canonicalize_pos_denorm_dynamic_dynamic( ; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x380FFFFFC0000000) ; CHECK-NEXT: ret float [[RET]] @@ -154,7 +154,7 @@ define float @canonicalize_pos_denorm_dynamic_dynamic() "denormal-fp-math"="dyna ret float %ret } -define float @canonicalize_neg_denorm_dynamic_dynamic() "denormal-fp-math"="dynamic,dynamic" { +define float @canonicalize_neg_denorm_dynamic_dynamic() denormal_fpenv(dynamic) { ; CHECK-LABEL: @canonicalize_neg_denorm_dynamic_dynamic( ; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0xB80FFFFFC0000000) ; CHECK-NEXT: ret float [[RET]] @@ -164,7 +164,7 @@ define float @canonicalize_neg_denorm_dynamic_dynamic() "denormal-fp-math"="dyna } ; Dynamic output - cannot flush -define float @canonicalize_pos_denorm_dynamic_output() "denormal-fp-math"="dynamic,ieee" { +define float @canonicalize_pos_denorm_dynamic_output() denormal_fpenv(dynamic|ieee) { ; CHECK-LABEL: @canonicalize_pos_denorm_dynamic_output( ; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x380FFFFFC0000000) ; CHECK-NEXT: ret float [[RET]] @@ -174,7 +174,7 @@ define float @canonicalize_pos_denorm_dynamic_output() "denormal-fp-math"="dynam } ; Dynamic output - cannot flush -define float @canonicalize_neg_denorm_dynamic_output() "denormal-fp-math"="dynamic,ieee" { +define float @canonicalize_neg_denorm_dynamic_output() denormal_fpenv(dynamic|ieee) { ; CHECK-LABEL: @canonicalize_neg_denorm_dynamic_output( ; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0xB80FFFFFC0000000) ; CHECK-NEXT: ret float [[RET]] @@ -184,7 +184,7 @@ define float @canonicalize_neg_denorm_dynamic_output() "denormal-fp-math"="dynam } ; Dynamic input - cannot flush -define float @canonicalize_pos_denorm_dynamic_input() "denormal-fp-math"="ieee,dynamic" { +define float @canonicalize_pos_denorm_dynamic_input() denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @canonicalize_pos_denorm_dynamic_input( ; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x380FFFFFC0000000) ; CHECK-NEXT: ret float [[RET]] @@ -194,7 +194,7 @@ define float @canonicalize_pos_denorm_dynamic_input() "denormal-fp-math"="ieee,d } ; Dynamic input - cannot flush -define float @canonicalize_neg_denorm_dynamic_input() "denormal-fp-math"="ieee,dynamic" { +define float @canonicalize_neg_denorm_dynamic_input() denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @canonicalize_neg_denorm_dynamic_input( ; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0xB80FFFFFC0000000) ; CHECK-NEXT: ret float [[RET]] @@ -204,7 +204,7 @@ define float @canonicalize_neg_denorm_dynamic_input() "denormal-fp-math"="ieee,d } ; Input is flushed, can fold -define float @canonicalize_pos_denorm_dynamic_output_preserve_sign_input() "denormal-fp-math"="dynamic,preserve-sign" { +define float @canonicalize_pos_denorm_dynamic_output_preserve_sign_input() denormal_fpenv(dynamic|preservesign) { ; CHECK-LABEL: @canonicalize_pos_denorm_dynamic_output_preserve_sign_input( ; CHECK-NEXT: ret float 0.000000e+00 ; @@ -213,7 +213,7 @@ define float @canonicalize_pos_denorm_dynamic_output_preserve_sign_input() "deno } ; Input is flushed, can fold -define float @canonicalize_neg_denorm_dynamic_output_preserve_sign_input() "denormal-fp-math"="dynamic,preserve-sign" { +define float @canonicalize_neg_denorm_dynamic_output_preserve_sign_input() denormal_fpenv(dynamic|preservesign) { ; CHECK-LABEL: @canonicalize_neg_denorm_dynamic_output_preserve_sign_input( ; CHECK-NEXT: ret float -0.000000e+00 ; @@ -222,7 +222,7 @@ define float @canonicalize_neg_denorm_dynamic_output_preserve_sign_input() "deno } ; Output is known flushed, can fold -define float @canonicalize_pos_preserve_sign_output_denorm_dynamic_input() "denormal-fp-math"="preserve-sign,dynamic" { +define float @canonicalize_pos_preserve_sign_output_denorm_dynamic_input() denormal_fpenv(preservesign|dynamic) { ; CHECK-LABEL: @canonicalize_pos_preserve_sign_output_denorm_dynamic_input( ; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0x380FFFFFC0000000) ; CHECK-NEXT: ret float [[RET]] @@ -232,7 +232,7 @@ define float @canonicalize_pos_preserve_sign_output_denorm_dynamic_input() "deno } ; Output is known flushed, can fold -define float @canonicalize_neg_denorm_preserve_sign_output_dynamic_input() "denormal-fp-math"="preserve-sign,dynamic" { +define float @canonicalize_neg_denorm_preserve_sign_output_dynamic_input() denormal_fpenv(preservesign|dynamic) { ; CHECK-LABEL: @canonicalize_neg_denorm_preserve_sign_output_dynamic_input( ; CHECK-NEXT: [[RET:%.*]] = call float @llvm.canonicalize.f32(float 0xB80FFFFFC0000000) ; CHECK-NEXT: ret float [[RET]] @@ -291,7 +291,7 @@ define float @canonicalize_neg_normal() { ret float %ret } -define <2 x float> @canonicalize_pos_denorm_preserve_sign_output_mixed_vector() "denormal-fp-math"="preserve-sign,ieee" { +define <2 x float> @canonicalize_pos_denorm_preserve_sign_output_mixed_vector() denormal_fpenv(preservesign|ieee) { ; CHECK-LABEL: @canonicalize_pos_denorm_preserve_sign_output_mixed_vector( ; CHECK-NEXT: ret <2 x float> ; @@ -299,7 +299,7 @@ define <2 x float> @canonicalize_pos_denorm_preserve_sign_output_mixed_vector() ret <2 x float> %ret } -define <2 x float> @canonicalize_pos_denorm_preserve_sign_input_mixed_vector() "denormal-fp-math"="ieee,preserve-sign" { +define <2 x float> @canonicalize_pos_denorm_preserve_sign_input_mixed_vector() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @canonicalize_pos_denorm_preserve_sign_input_mixed_vector( ; CHECK-NEXT: ret <2 x float> ; @@ -307,7 +307,7 @@ define <2 x float> @canonicalize_pos_denorm_preserve_sign_input_mixed_vector() " ret <2 x float> %ret } -define <2 x float> @canonicalize_pos_denorm_positive_zero_output_mixed_vector() "denormal-fp-math"="positive-zero,ieee" { +define <2 x float> @canonicalize_pos_denorm_positive_zero_output_mixed_vector() denormal_fpenv(positivezero|ieee) { ; CHECK-LABEL: @canonicalize_pos_denorm_positive_zero_output_mixed_vector( ; CHECK-NEXT: ret <2 x float> zeroinitializer ; @@ -315,7 +315,7 @@ define <2 x float> @canonicalize_pos_denorm_positive_zero_output_mixed_vector() ret <2 x float> %ret } -define <2 x float> @canonicalize_pos_denorm_positive_zero_input_mixed_vector() "denormal-fp-math"="ieee,positive-zero" { +define <2 x float> @canonicalize_pos_denorm_positive_zero_input_mixed_vector() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @canonicalize_pos_denorm_positive_zero_input_mixed_vector( ; CHECK-NEXT: ret <2 x float> zeroinitializer ; @@ -323,7 +323,7 @@ define <2 x float> @canonicalize_pos_denorm_positive_zero_input_mixed_vector() " ret <2 x float> %ret } -define float @canonicalize_neg_denorm_preserve_sign_output_positive_zero_input() "denormal-fp-math"="preserve-sign,positive-zero" { +define float @canonicalize_neg_denorm_preserve_sign_output_positive_zero_input() denormal_fpenv(preservesign|positivezero) { ; CHECK-LABEL: @canonicalize_neg_denorm_preserve_sign_output_positive_zero_input( ; CHECK-NEXT: ret float 0.000000e+00 ; @@ -331,7 +331,7 @@ define float @canonicalize_neg_denorm_preserve_sign_output_positive_zero_input() ret float %ret } -define float @canonicalize_neg_denorm_positive_zero_output_preserve_sign_input() "denormal-fp-math"="positive-zero,preserve-sign" { +define float @canonicalize_neg_denorm_positive_zero_output_preserve_sign_input() denormal_fpenv(positivezero|preservesign) { ; CHECK-LABEL: @canonicalize_neg_denorm_positive_zero_output_preserve_sign_input( ; CHECK-NEXT: ret float -0.000000e+00 ; @@ -766,7 +766,7 @@ define ppc_fp128 @canonicalize_neg1.0_ppcf128() { ; Test folds of using canonicalize + is.fpclass to inspect the denormal mode. ; -------------------------------------------------------------------- -define i1 @is_poszero_daz_enabled_check_dynamic() "denormal-fp-math"="ieee,dynamic" { +define i1 @is_poszero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @is_poszero_daz_enabled_check_dynamic( ; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0x36A0000000000000) ; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 64) @@ -777,7 +777,7 @@ define i1 @is_poszero_daz_enabled_check_dynamic() "denormal-fp-math"="ieee,dynam ret i1 %is.pos.zero } -define i1 @is_preserve_sign_daz_enabled_check_dynamic() "denormal-fp-math"="ieee,dynamic" { +define i1 @is_preserve_sign_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @is_preserve_sign_daz_enabled_check_dynamic( ; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0xB6A0000000000000) ; CHECK-NEXT: [[IS_NEG_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 32) @@ -788,7 +788,7 @@ define i1 @is_preserve_sign_daz_enabled_check_dynamic() "denormal-fp-math"="ieee ret i1 %is.neg.zero } -define i1 @is_positive_zero_daz_enabled_check_dynamic() "denormal-fp-math"="ieee,dynamic" { +define i1 @is_positive_zero_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @is_positive_zero_daz_enabled_check_dynamic( ; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0xB6A0000000000000) ; CHECK-NEXT: [[IS_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 64) @@ -799,7 +799,7 @@ define i1 @is_positive_zero_daz_enabled_check_dynamic() "denormal-fp-math"="ieee ret i1 %is.pos.zero } -define i1 @is_any_daz_enabled_check_dynamic() "denormal-fp-math"="ieee,dynamic" { +define i1 @is_any_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @is_any_daz_enabled_check_dynamic( ; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0xB6A0000000000000) ; CHECK-NEXT: [[IS_ANY_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 96) @@ -810,7 +810,7 @@ define i1 @is_any_daz_enabled_check_dynamic() "denormal-fp-math"="ieee,dynamic" ret i1 %is.any.zero } -define i1 @is_not_daz_enabled_check_dynamic() "denormal-fp-math"="ieee,dynamic" { +define i1 @is_not_daz_enabled_check_dynamic() denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @is_not_daz_enabled_check_dynamic( ; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0x36A0000000000000) ; CHECK-NEXT: [[IS_NOT_POS_ZERO:%.*]] = call i1 @llvm.is.fpclass.f32(float [[CANONICAL]], i32 959) @@ -821,7 +821,7 @@ define i1 @is_not_daz_enabled_check_dynamic() "denormal-fp-math"="ieee,dynamic" ret i1 %is.not.pos.zero } -define i1 @is_poszero_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ieee" { +define i1 @is_poszero_daz_enabled_check_ieee() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: @is_poszero_daz_enabled_check_ieee( ; CHECK-NEXT: ret i1 false ; @@ -830,7 +830,7 @@ define i1 @is_poszero_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ieee" { ret i1 %is.pos.zero } -define i1 @is_preserve_sign_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ieee" { +define i1 @is_preserve_sign_daz_enabled_check_ieee() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: @is_preserve_sign_daz_enabled_check_ieee( ; CHECK-NEXT: ret i1 false ; @@ -839,7 +839,7 @@ define i1 @is_preserve_sign_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ie ret i1 %is.neg.zero } -define i1 @is_positive_zero_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ieee" { +define i1 @is_positive_zero_daz_enabled_check_ieee() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: @is_positive_zero_daz_enabled_check_ieee( ; CHECK-NEXT: ret i1 false ; @@ -848,7 +848,7 @@ define i1 @is_positive_zero_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ie ret i1 %is.pos.zero } -define i1 @is_any_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ieee" { +define i1 @is_any_daz_enabled_check_ieee() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: @is_any_daz_enabled_check_ieee( ; CHECK-NEXT: ret i1 false ; @@ -857,7 +857,7 @@ define i1 @is_any_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ieee" { ret i1 %is.any.zero } -define i1 @is_not_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ieee" { +define i1 @is_not_daz_enabled_check_ieee() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: @is_not_daz_enabled_check_ieee( ; CHECK-NEXT: ret i1 true ; @@ -866,7 +866,7 @@ define i1 @is_not_daz_enabled_check_ieee() "denormal-fp-math"="ieee,ieee" { ret i1 %is.not.pos.zero } -define i1 @is_poszero_daz_enabled_check_preserve_sign() "denormal-fp-math"="ieee,preserve-sign" { +define i1 @is_poszero_daz_enabled_check_preserve_sign() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @is_poszero_daz_enabled_check_preserve_sign( ; CHECK-NEXT: ret i1 true ; @@ -875,7 +875,7 @@ define i1 @is_poszero_daz_enabled_check_preserve_sign() "denormal-fp-math"="ieee ret i1 %is.pos.zero } -define i1 @is_preserve_sign_daz_enabled_check_preserve_sign() "denormal-fp-math"="ieee,preserve-sign" { +define i1 @is_preserve_sign_daz_enabled_check_preserve_sign() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @is_preserve_sign_daz_enabled_check_preserve_sign( ; CHECK-NEXT: ret i1 true ; @@ -884,7 +884,7 @@ define i1 @is_preserve_sign_daz_enabled_check_preserve_sign() "denormal-fp-math" ret i1 %is.neg.zero } -define i1 @is_positive_zero_daz_enabled_check_preserve_sign() "denormal-fp-math"="ieee,preserve-sign" { +define i1 @is_positive_zero_daz_enabled_check_preserve_sign() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @is_positive_zero_daz_enabled_check_preserve_sign( ; CHECK-NEXT: ret i1 false ; @@ -893,7 +893,7 @@ define i1 @is_positive_zero_daz_enabled_check_preserve_sign() "denormal-fp-math" ret i1 %is.pos.zero } -define i1 @is_any_daz_enabled_check_preserve_sign() "denormal-fp-math"="ieee,preserve-sign" { +define i1 @is_any_daz_enabled_check_preserve_sign() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @is_any_daz_enabled_check_preserve_sign( ; CHECK-NEXT: ret i1 true ; @@ -902,7 +902,7 @@ define i1 @is_any_daz_enabled_check_preserve_sign() "denormal-fp-math"="ieee,pre ret i1 %is.any.zero } -define i1 @is_not_daz_enabled_check_preserve_sign() "denormal-fp-math"="ieee,preserve-sign" { +define i1 @is_not_daz_enabled_check_preserve_sign() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @is_not_daz_enabled_check_preserve_sign( ; CHECK-NEXT: ret i1 false ; @@ -911,7 +911,7 @@ define i1 @is_not_daz_enabled_check_preserve_sign() "denormal-fp-math"="ieee,pre ret i1 %is.not.pos.zero } -define i1 @is_poszero_daz_enabled_check_positive_zero() "denormal-fp-math"="ieee,positive-zero" { +define i1 @is_poszero_daz_enabled_check_positive_zero() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @is_poszero_daz_enabled_check_positive_zero( ; CHECK-NEXT: ret i1 true ; @@ -920,7 +920,7 @@ define i1 @is_poszero_daz_enabled_check_positive_zero() "denormal-fp-math"="ieee ret i1 %is.pos.zero } -define i1 @is_preserve_sign_daz_enabled_check_positive_zero() "denormal-fp-math"="ieee,positive-zero" { +define i1 @is_preserve_sign_daz_enabled_check_positive_zero() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @is_preserve_sign_daz_enabled_check_positive_zero( ; CHECK-NEXT: ret i1 false ; @@ -929,7 +929,7 @@ define i1 @is_preserve_sign_daz_enabled_check_positive_zero() "denormal-fp-math" ret i1 %is.neg.zero } -define i1 @is_positive_zero_daz_enabled_check_positive_zero() "denormal-fp-math"="ieee,positive-zero" { +define i1 @is_positive_zero_daz_enabled_check_positive_zero() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @is_positive_zero_daz_enabled_check_positive_zero( ; CHECK-NEXT: ret i1 true ; @@ -938,7 +938,7 @@ define i1 @is_positive_zero_daz_enabled_check_positive_zero() "denormal-fp-math" ret i1 %is.pos.zero } -define i1 @is_any_daz_enabled_check_positive_zero() "denormal-fp-math"="ieee,positive-zero" { +define i1 @is_any_daz_enabled_check_positive_zero() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @is_any_daz_enabled_check_positive_zero( ; CHECK-NEXT: ret i1 true ; @@ -947,7 +947,7 @@ define i1 @is_any_daz_enabled_check_positive_zero() "denormal-fp-math"="ieee,pos ret i1 %is.any.zero } -define i1 @is_not_daz_enabled_check_positive_zero() "denormal-fp-math"="ieee,positive-zero" { +define i1 @is_not_daz_enabled_check_positive_zero() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @is_not_daz_enabled_check_positive_zero( ; CHECK-NEXT: ret i1 false ; @@ -956,7 +956,7 @@ define i1 @is_not_daz_enabled_check_positive_zero() "denormal-fp-math"="ieee,pos ret i1 %is.not.pos.zero } -define i1 @is_poszero_daz_enabled_check_dynamic_bitcast() "denormal-fp-math"="ieee,dynamic" { +define i1 @is_poszero_daz_enabled_check_dynamic_bitcast() denormal_fpenv(ieee|dynamic) { ; CHECK-LABEL: @is_poszero_daz_enabled_check_dynamic_bitcast( ; CHECK-NEXT: [[CANONICAL:%.*]] = call float @llvm.canonicalize.f32(float 0x36A0000000000000) ; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[CANONICAL]] to i32 @@ -969,7 +969,7 @@ define i1 @is_poszero_daz_enabled_check_dynamic_bitcast() "denormal-fp-math"="ie ret i1 %is.pos.zero } -define i1 @is_poszero_daz_enabled_check_preserve_sign_bitcast() "denormal-fp-math"="ieee,preserve-sign" { +define i1 @is_poszero_daz_enabled_check_preserve_sign_bitcast() denormal_fpenv(ieee|preservesign) { ; CHECK-LABEL: @is_poszero_daz_enabled_check_preserve_sign_bitcast( ; CHECK-NEXT: ret i1 true ; @@ -979,7 +979,7 @@ define i1 @is_poszero_daz_enabled_check_preserve_sign_bitcast() "denormal-fp-mat ret i1 %is.pos.zero } -define i1 @is_poszero_daz_enabled_check_positive_zero_bitcast() "denormal-fp-math"="ieee,positive-zero" { +define i1 @is_poszero_daz_enabled_check_positive_zero_bitcast() denormal_fpenv(ieee|positivezero) { ; CHECK-LABEL: @is_poszero_daz_enabled_check_positive_zero_bitcast( ; CHECK-NEXT: ret i1 true ; @@ -989,7 +989,7 @@ define i1 @is_poszero_daz_enabled_check_positive_zero_bitcast() "denormal-fp-mat ret i1 %is.pos.zero } -define i1 @is_poszero_daz_enabled_check_ieee_bitcast() "denormal-fp-math"="ieee,ieee" { +define i1 @is_poszero_daz_enabled_check_ieee_bitcast() denormal_fpenv(ieee|ieee) { ; CHECK-LABEL: @is_poszero_daz_enabled_check_ieee_bitcast( ; CHECK-NEXT: ret i1 false ; diff --git a/llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll b/llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll index bcd75898a4ffd..16d5f0d2871b1 100644 --- a/llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll +++ b/llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll @@ -1203,16 +1203,16 @@ define i1 @fcmp_double_dynamic_dynamic_normals() #11 { ret i1 %cmp } -attributes #0 = { nounwind "denormal-fp-math"="ieee,ieee" } -attributes #1 = { nounwind "denormal-fp-math"="positive-zero,ieee" } -attributes #2 = { nounwind "denormal-fp-math"="preserve-sign,ieee" } -attributes #3 = { nounwind "denormal-fp-math"="ieee,positive-zero" } -attributes #4 = { nounwind "denormal-fp-math"="ieee,preserve-sign" } -attributes #5 = { nounwind "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="positive-zero,ieee" } -attributes #6 = { nounwind "denormal-fp-math"="positive-zero,positive-zero" } -attributes #7 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" } -attributes #8 = { nounwind "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="positive-zero,positive-zero" } -attributes #9 = { nounwind "denormal-fp-math"="dynamic,ieee" } -attributes #10 = { nounwind "denormal-fp-math"="ieee,dynamic" } -attributes #11 = { nounwind "denormal-fp-math"="dynamic,dynamic" } -attributes #12 = { nounwind "denormal-fp-math"="dynamic,preserve-sign" } +attributes #0 = { nounwind denormal_fpenv(ieee) } +attributes #1 = { nounwind denormal_fpenv(positivezero|ieee) } +attributes #2 = { nounwind denormal_fpenv(preservesign|ieee) } +attributes #3 = { nounwind denormal_fpenv(ieee|positivezero) } +attributes #4 = { nounwind denormal_fpenv(ieee|preservesign) } +attributes #5 = { nounwind denormal_fpenv(ieee, float: positivezero|ieee) } +attributes #6 = { nounwind denormal_fpenv(positivezero|positivezero) } +attributes #7 = { nounwind denormal_fpenv(preservesign) } +attributes #8 = { nounwind denormal_fpenv(ieee, float: positivezero) } +attributes #9 = { nounwind denormal_fpenv(dynamic|ieee) } +attributes #10 = { nounwind denormal_fpenv(ieee|dynamic) } +attributes #11 = { nounwind denormal_fpenv(dynamic) } +attributes #12 = { nounwind denormal_fpenv(dynamic|preservesign) } diff --git a/llvm/test/Transforms/InstSimplify/floating-point-compare.ll b/llvm/test/Transforms/InstSimplify/floating-point-compare.ll index 4286d978555e1..259d98acb1a2d 100644 --- a/llvm/test/Transforms/InstSimplify/floating-point-compare.ll +++ b/llvm/test/Transforms/InstSimplify/floating-point-compare.ll @@ -1720,7 +1720,7 @@ bb: ret float %i5 } -define i1 @is_olt_smallest_normal_dynamic(float %x) "denormal-fp-math"="dynamic,dynamic" { +define i1 @is_olt_smallest_normal_dynamic(float %x) denormal_fpenv(dynamic) { ; CHECK-LABEL: @is_olt_smallest_normal_dynamic( ; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], 0x3810000000000000 ; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]] @@ -1729,7 +1729,7 @@ define i1 @is_olt_smallest_normal_dynamic(float %x) "denormal-fp-math"="dynamic, ret i1 %is.denorm.or.zero } -define i1 @is_olt_smallest_normal_ieee(float %x) "denormal-fp-math"="dynamic,ieee" { +define i1 @is_olt_smallest_normal_ieee(float %x) denormal_fpenv(dynamic|ieee) { ; CHECK-LABEL: @is_olt_smallest_normal_ieee( ; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], 0x3810000000000000 ; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]] @@ -1738,7 +1738,7 @@ define i1 @is_olt_smallest_normal_ieee(float %x) "denormal-fp-math"="dynamic,iee ret i1 %is.denorm.or.zero } -define i1 @is_olt_smallest_normal_preserve_sign(float %x) "denormal-fp-math"="dynamic,preserve-sign" { +define i1 @is_olt_smallest_normal_preserve_sign(float %x) denormal_fpenv(dynamic|preservesign) { ; CHECK-LABEL: @is_olt_smallest_normal_preserve_sign( ; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], 0x3810000000000000 ; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]] @@ -1747,7 +1747,7 @@ define i1 @is_olt_smallest_normal_preserve_sign(float %x) "denormal-fp-math"="dy ret i1 %is.denorm.or.zero } -define i1 @is_olt_smallest_normal_positive_zero(float %x) "denormal-fp-math"="dynamic,positive-zero" { +define i1 @is_olt_smallest_normal_positive_zero(float %x) denormal_fpenv(dynamic|positivezero) { ; CHECK-LABEL: @is_olt_smallest_normal_positive_zero( ; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[X:%.*]], 0x3810000000000000 ; CHECK-NEXT: ret i1 [[IS_DENORM_OR_ZERO]] @@ -1756,7 +1756,7 @@ define i1 @is_olt_smallest_normal_positive_zero(float %x) "denormal-fp-math"="dy ret i1 %is.denorm.or.zero } -define i1 @is_fabs_olt_smallest_normal_dynamic(float %x) "denormal-fp-math"="dynamic,dynamic" { +define i1 @is_fabs_olt_smallest_normal_dynamic(float %x) denormal_fpenv(dynamic) { ; CHECK-LABEL: @is_fabs_olt_smallest_normal_dynamic( ; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]]) ; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], 0x3810000000000000 @@ -1767,7 +1767,7 @@ define i1 @is_fabs_olt_smallest_normal_dynamic(float %x) "denormal-fp-math"="dyn ret i1 %is.denorm.or.zero } -define i1 @is_fabs_olt_smallest_normal_ieee(float %x) "denormal-fp-math"="dynamic,ieee" { +define i1 @is_fabs_olt_smallest_normal_ieee(float %x) denormal_fpenv(dynamic|ieee) { ; CHECK-LABEL: @is_fabs_olt_smallest_normal_ieee( ; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]]) ; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], 0x3810000000000000 @@ -1778,7 +1778,7 @@ define i1 @is_fabs_olt_smallest_normal_ieee(float %x) "denormal-fp-math"="dynami ret i1 %is.denorm.or.zero } -define i1 @is_fabs_olt_smallest_normal_preserve_sign(float %x) "denormal-fp-math"="dynamic,preserve-sign" { +define i1 @is_fabs_olt_smallest_normal_preserve_sign(float %x) denormal_fpenv(dynamic|preservesign) { ; CHECK-LABEL: @is_fabs_olt_smallest_normal_preserve_sign( ; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]]) ; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], 0x3810000000000000 @@ -1789,7 +1789,7 @@ define i1 @is_fabs_olt_smallest_normal_preserve_sign(float %x) "denormal-fp-math ret i1 %is.denorm.or.zero } -define i1 @is_fabs_olt_smallest_normal_positive_zero(float %x) "denormal-fp-math"="dynamic,positive-zero" { +define i1 @is_fabs_olt_smallest_normal_positive_zero(float %x) denormal_fpenv(dynamic|positivezero) { ; CHECK-LABEL: @is_fabs_olt_smallest_normal_positive_zero( ; CHECK-NEXT: [[FABS_X:%.*]] = call float @llvm.fabs.f32(float [[X:%.*]]) ; CHECK-NEXT: [[IS_DENORM_OR_ZERO:%.*]] = fcmp olt float [[FABS_X]], 0x3810000000000000 @@ -1821,4 +1821,4 @@ declare double @llvm.copysign.f64(double, double) declare half @llvm.fabs.f16(half) declare void @llvm.assume(i1 noundef) -attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } +attributes #0 = { denormal_fpenv(preservesign) } diff --git a/llvm/test/Transforms/LoopDistribute/doubly-nested.ll b/llvm/test/Transforms/LoopDistribute/doubly-nested.ll new file mode 100644 index 0000000000000..23a26afa640ec --- /dev/null +++ b/llvm/test/Transforms/LoopDistribute/doubly-nested.ll @@ -0,0 +1,129 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -aa-pipeline=basic-aa -passes=loop-distribute -enable-loop-distribute -verify-loop-info -verify-dom-info -S \ +; RUN: < %s | FileCheck %s + +; Doubly nested loop with two statements in the innermost loop. +; Statement S2 can be put into a separate loop because there is no dependence between S1 and S2. +; +; for (int i = 0; i < N; i++) { +; for (int j = 0; j < M; j++) { +; S1: A[i][j+1] = A[i][j] + B[i][j] + C[i][j] // Statement S1 +; ================================ +; S2: D[i][j] = E[i][j] * F[i][j]; // Statement 2 +; } +; } + +define void @doubly_nested_distributable(ptr noalias %A, ptr noalias %B, ptr noalias %C, + ptr noalias %D, ptr noalias %E, ptr noalias %F, + i64 %N, i64 %M) { +; CHECK-LABEL: define void @doubly_nested_distributable( +; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]], ptr noalias [[D:%.*]], ptr noalias [[E:%.*]], ptr noalias [[F:%.*]], i64 [[N:%.*]], i64 [[M:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br label %[[FOR_I_HEADER:.*]] +; CHECK: [[FOR_I_HEADER]]: +; CHECK-NEXT: [[I:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[I_NEXT:%.*]], %[[FOR_I_INC:.*]] ] +; CHECK-NEXT: [[I_CMP:%.*]] = icmp slt i64 [[I]], [[N]] +; CHECK-NEXT: br i1 [[I_CMP]], label %[[FOR_J_PREHEADER_LDIST1:.*]], label %[[FOR_END:.*]] +; CHECK: [[FOR_J_PREHEADER_LDIST1]]: +; CHECK-NEXT: br label %[[FOR_J_BODY_LDIST1:.*]] +; CHECK: [[FOR_J_BODY_LDIST1]]: +; CHECK-NEXT: [[J_LDIST1:%.*]] = phi i64 [ 0, %[[FOR_J_PREHEADER_LDIST1]] ], [ [[J_NEXT_LDIST1:%.*]], %[[FOR_J_BODY_LDIST1]] ] +; CHECK-NEXT: [[IDX_I_LDIST1:%.*]] = mul i64 [[I]], [[M]] +; CHECK-NEXT: [[IDX_LDIST1:%.*]] = add i64 [[IDX_I_LDIST1]], [[J_LDIST1]] +; CHECK-NEXT: [[ARRAYIDXA_LDIST1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDX_LDIST1]] +; CHECK-NEXT: [[LOADA_LDIST1:%.*]] = load i32, ptr [[ARRAYIDXA_LDIST1]], align 4 +; CHECK-NEXT: [[ARRAYIDXB_LDIST1:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IDX_LDIST1]] +; CHECK-NEXT: [[LOADB_LDIST1:%.*]] = load i32, ptr [[ARRAYIDXB_LDIST1]], align 4 +; CHECK-NEXT: [[ARRAYIDXC_LDIST1:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IDX_LDIST1]] +; CHECK-NEXT: [[LOADC_LDIST1:%.*]] = load i32, ptr [[ARRAYIDXC_LDIST1]], align 4 +; CHECK-NEXT: [[ADDS1_LDIST1:%.*]] = add i32 [[LOADB_LDIST1]], [[LOADC_LDIST1]] +; CHECK-NEXT: [[ADDWITHDEP_LDIST1:%.*]] = add i32 [[ADDS1_LDIST1]], [[LOADA_LDIST1]] +; CHECK-NEXT: [[J_NEXT_LDIST1]] = add nuw nsw i64 [[J_LDIST1]], 1 +; CHECK-NEXT: [[IDX_NEXT_LDIST1:%.*]] = add i64 [[IDX_LDIST1]], 1 +; CHECK-NEXT: [[ARRAYIDXA_NEXT_LDIST1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IDX_NEXT_LDIST1]] +; CHECK-NEXT: store i32 [[ADDWITHDEP_LDIST1]], ptr [[ARRAYIDXA_NEXT_LDIST1]], align 4 +; CHECK-NEXT: [[EXITCOND_J_LDIST1:%.*]] = icmp eq i64 [[J_NEXT_LDIST1]], [[M]] +; CHECK-NEXT: br i1 [[EXITCOND_J_LDIST1]], label %[[FOR_J_PREHEADER:.*]], label %[[FOR_J_BODY_LDIST1]] +; CHECK: [[FOR_J_PREHEADER]]: +; CHECK-NEXT: br label %[[FOR_J_BODY:.*]] +; CHECK: [[FOR_J_BODY]]: +; CHECK-NEXT: [[J:%.*]] = phi i64 [ 0, %[[FOR_J_PREHEADER]] ], [ [[J_NEXT:%.*]], %[[FOR_J_BODY]] ] +; CHECK-NEXT: [[IDX_I:%.*]] = mul i64 [[I]], [[M]] +; CHECK-NEXT: [[IDX:%.*]] = add i64 [[IDX_I]], [[J]] +; CHECK-NEXT: [[J_NEXT]] = add nuw nsw i64 [[J]], 1 +; CHECK-NEXT: [[ARRAYIDXD:%.*]] = getelementptr inbounds i32, ptr [[D]], i64 [[IDX]] +; CHECK-NEXT: [[ARRAYIDXE:%.*]] = getelementptr inbounds i32, ptr [[E]], i64 [[IDX]] +; CHECK-NEXT: [[LOADE:%.*]] = load i32, ptr [[ARRAYIDXE]], align 4 +; CHECK-NEXT: [[ARRAYIDXF:%.*]] = getelementptr inbounds i32, ptr [[F]], i64 [[IDX]] +; CHECK-NEXT: [[LOADF:%.*]] = load i32, ptr [[ARRAYIDXF]], align 4 +; CHECK-NEXT: [[MULS2:%.*]] = mul i32 [[LOADE]], [[LOADF]] +; CHECK-NEXT: store i32 [[MULS2]], ptr [[ARRAYIDXD]], align 4 +; CHECK-NEXT: [[EXITCOND_J:%.*]] = icmp eq i64 [[J_NEXT]], [[M]] +; CHECK-NEXT: br i1 [[EXITCOND_J]], label %[[FOR_J_END:.*]], label %[[FOR_J_BODY]] +; CHECK: [[FOR_J_END]]: +; CHECK-NEXT: br label %[[FOR_I_INC]] +; CHECK: [[FOR_I_INC]]: +; CHECK-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1 +; CHECK-NEXT: br label %[[FOR_I_HEADER]] +; CHECK: [[FOR_END]]: +; CHECK-NEXT: ret void +; +entry: + br label %for.i.header + +for.i.header: ; preds = %for.i.inc, %entry + %i = phi i64 [ 0, %entry ], [ %i.next, %for.i.inc ] + %i.cmp = icmp slt i64 %i, %N + br i1 %i.cmp, label %for.j.preheader, label %for.end + +for.j.preheader: ; preds = %for.i.header + br label %for.j.body + +for.j.body: ; preds = %for.j.body, %for.j.preheader + %j = phi i64 [ 0, %for.j.preheader ], [ %j.next, %for.j.body ] + + %idx.i = mul i64 %i, %M + %idx = add i64 %idx.i, %j + + ; Statement 1: A[i][j+1] = A[i][j] + B[i][j] + C[i][j] + %arrayidxA = getelementptr inbounds i32, ptr %A, i64 %idx + %loadA = load i32, ptr %arrayidxA, align 4 + + %arrayidxB = getelementptr inbounds i32, ptr %B, i64 %idx + %loadB = load i32, ptr %arrayidxB, align 4 + + %arrayidxC = getelementptr inbounds i32, ptr %C, i64 %idx + %loadC = load i32, ptr %arrayidxC, align 4 + + %addS1 = add i32 %loadB, %loadC + %addWithDep = add i32 %addS1, %loadA + + %j.next = add nuw nsw i64 %j, 1 + %idx.next = add i64 %idx, 1 + %arrayidxA_next = getelementptr inbounds i32, ptr %A, i64 %idx.next + store i32 %addWithDep, ptr %arrayidxA_next, align 4 + + ; Statement 2: D[i][j] = E[i][j] * F[i][j] + %arrayidxD = getelementptr inbounds i32, ptr %D, i64 %idx + %arrayidxE = getelementptr inbounds i32, ptr %E, i64 %idx + %loadE = load i32, ptr %arrayidxE, align 4 + + %arrayidxF = getelementptr inbounds i32, ptr %F, i64 %idx + %loadF = load i32, ptr %arrayidxF, align 4 + + %mulS2 = mul i32 %loadE, %loadF + store i32 %mulS2, ptr %arrayidxD, align 4 + + %exitcond.j = icmp eq i64 %j.next, %M + br i1 %exitcond.j, label %for.j.end, label %for.j.body + +for.j.end: ; preds = %for.j.body + br label %for.i.inc + +for.i.inc: ; preds = %for.j.end + %i.next = add nuw nsw i64 %i, 1 + br label %for.i.header + +for.end: ; preds = %for.i.header + ret void +} diff --git a/llvm/test/Transforms/LoopIdiom/reuse-lcssa-phi-scev-expansion.ll b/llvm/test/Transforms/LoopIdiom/reuse-lcssa-phi-scev-expansion.ll index a15db620e0082..d0e70c21c7bc6 100644 --- a/llvm/test/Transforms/LoopIdiom/reuse-lcssa-phi-scev-expansion.ll +++ b/llvm/test/Transforms/LoopIdiom/reuse-lcssa-phi-scev-expansion.ll @@ -10,7 +10,7 @@ define void @scev_expand_ptrtoint(i8 %x, ptr %start) { ; CHECK-LABEL: define void @scev_expand_ptrtoint( ; CHECK-SAME: i8 [[X:%.*]], ptr [[START:%.*]]) { ; CHECK-NEXT: [[ENTRY:.*]]: -; CHECK-NEXT: [[START1:%.*]] = ptrtoint ptr [[START]] to i64 +; CHECK-NEXT: [[START1:%.*]] = ptrtoaddr ptr [[START]] to i64 ; CHECK-NEXT: br label %[[LOOP_1_HEADER:.*]] ; CHECK: [[LOOP_1_HEADER]]: ; CHECK-NEXT: [[PTR_IV_1:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_1_NEXT:%.*]], %[[LOOP_1_LATCH:.*]] ] @@ -36,7 +36,7 @@ define void @scev_expand_ptrtoint(i8 %x, ptr %start) { ; CHECK-NEXT: [[INDVAR_LCSSA:%.*]] = phi i64 [ [[INDVAR]], %[[LOOP_2_HEADER]] ], [ [[INDVAR]], %[[LOOP_2_HEADER]] ] ; CHECK-NEXT: [[PTR_IV_2_LCSSA:%.*]] = phi ptr [ [[PTR_IV_2]], %[[LOOP_2_HEADER]] ], [ [[PTR_IV_2]], %[[LOOP_2_HEADER]] ] ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 1, [[START1]] -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR_IV_1_LCSSA]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoaddr ptr [[PTR_IV_1_LCSSA]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[TMP0]] ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[CMP_EXT]], [[TMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDVAR_LCSSA]], [[TMP4]] @@ -222,3 +222,68 @@ loop.2.latch: exit: ret void } + +define void @expand_truncated_ptrtoint(ptr %A, ptr %B) { +; CHECK-LABEL: define void @expand_truncated_ptrtoint( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: br label %[[LOOP_1:.*]] +; CHECK: [[LOOP_1]]: +; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], %[[LOOP_1]] ], [ 0, %[[ENTRY]] ] +; CHECK-NEXT: [[P_0:%.*]] = phi ptr [ [[A]], %[[ENTRY]] ], [ [[P_0_NEXT:%.*]], %[[LOOP_1]] ] +; CHECK-NEXT: [[P_0_NEXT]] = getelementptr i8, ptr [[P_0]], i64 -1 +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1 +; CHECK-NEXT: br i1 false, label %[[MIDDLE:.*]], label %[[LOOP_1]] +; CHECK: [[MIDDLE]]: +; CHECK-NEXT: [[INDVAR_LCSSA:%.*]] = phi i32 [ [[INDVAR]], %[[LOOP_1]] ] +; CHECK-NEXT: [[P_0_LCSSA:%.*]] = phi ptr [ [[P_0]], %[[LOOP_1]] ] +; CHECK-NEXT: [[P_0_TO_INT:%.*]] = ptrtoint ptr [[P_0_LCSSA]] to i64 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[P_0_TO_INT]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[TRUNC]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i64 [[TMP0]], -1 +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[A1]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP2]], 1 +; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[INDVAR_LCSSA]], -1 +; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP6]], [[TMP3]] +; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP5]] to i64 +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[SCEVGEP]], i8 0, i64 [[TMP4]], i1 false) +; CHECK-NEXT: br label %[[LOOP_2:.*]] +; CHECK: [[LOOP_2]]: +; CHECK-NEXT: [[P_1:%.*]] = phi ptr [ [[B]], %[[MIDDLE]] ], [ [[P_1_NEXT:%.*]], %[[LOOP_2]] ] +; CHECK-NEXT: [[P_2:%.*]] = phi i32 [ [[TRUNC]], %[[MIDDLE]] ], [ [[P_2_NEXT:%.*]], %[[LOOP_2]] ] +; CHECK-NEXT: [[P_1_NEXT]] = getelementptr i8, ptr [[P_1]], i64 -1 +; CHECK-NEXT: [[P_2_NEXT]] = add i32 [[P_2]], -1 +; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[P_2]], 0 +; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_2]], label %[[EXIT:.*]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop.1 + +loop.1: + %p.0 = phi ptr [ %A, %entry ], [ %p.0.next, %loop.1 ] + %p.0.next = getelementptr i8, ptr %p.0, i64 -1 + call void @foo() + br i1 false, label %middle, label %loop.1 + +middle: + %p.0.to.int = ptrtoint ptr %p.0 to i64 + %trunc = trunc i64 %p.0.to.int to i32 + br label %loop.2 + +loop.2: + %p.1 = phi ptr [ %B, %middle ], [ %p.1.next, %loop.2 ] + %p.2 = phi i32 [ %trunc, %middle ], [ %p.2.next, %loop.2 ] + %p.1.next = getelementptr i8, ptr %p.1, i64 -1 + store i8 0, ptr %p.1, align 1 + %p.2.next = add i32 %p.2, -1 + %ec = icmp sgt i32 %p.2, 0 + br i1 %ec, label %loop.2, label %exit + +exit: + ret void +} diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/debuginfo-scev-salvage-ptrtoaddr.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/debuginfo-scev-salvage-ptrtoaddr.ll new file mode 100644 index 0000000000000..3cbe40ad0f2ef --- /dev/null +++ b/llvm/test/Transforms/LoopStrengthReduce/X86/debuginfo-scev-salvage-ptrtoaddr.ll @@ -0,0 +1,61 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S -loop-reduce %s -o - | FileCheck %s + +;; Ensure that debug value salvaging does not crash when encountering +;; SCEVPtrToAddrExpr in the SCEV expression tree. + + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i64 @test(ptr %p) { +; CHECK-LABEL: define i64 @test( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: [[P1:%.*]] = ptrtoaddr ptr [[P]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[P1]], -1 +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ [[TMP0]], %[[ENTRY]] ] +; CHECK-NEXT: #dbg_value(i64 [[LSR_IV]], [[META4:![0-9]+]], !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), [[META8:![0-9]+]]) +; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], 1 +; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[LOOP]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret i64 [[LSR_IV_NEXT]] +; +entry: + br label %loop + +loop: + %iv = phi ptr [ %p, %entry ], [ %iv.next, %loop ] + %addr = ptrtoaddr ptr %iv to i64 + #dbg_value(i64 %addr, !4, !DIExpression(), !9) + %iv.next = getelementptr i8, ptr %iv, i64 1 + br i1 false, label %exit, label %loop + +exit: + ret i64 %addr +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.c", directory: "/tmp") +!2 = !{} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !DILocalVariable(name: "addr", scope: !5, file: !1, line: 2, type: !7) +!5 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !6, scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2) +!6 = !DISubroutineType(types: !2) +!7 = !DIBasicType(name: "long", size: 64, encoding: DW_ATE_signed) +!9 = !DILocation(line: 2, scope: !5) +;. +; CHECK: [[META0:![0-9]+]] = distinct !DICompileUnit(language: DW_LANG_C11, file: [[META1:![0-9]+]], producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: [[META2:![0-9]+]], splitDebugInlining: false, nameTableKind: None) +; CHECK: [[META1]] = !DIFile(filename: "{{.*}}test.c", directory: {{.*}}) +; CHECK: [[META2]] = !{} +; CHECK: [[META4]] = !DILocalVariable(name: "addr", scope: [[META5:![0-9]+]], file: [[META1]], line: 2, type: [[META7:![0-9]+]]) +; CHECK: [[META5]] = distinct !DISubprogram(name: "test", scope: [[META1]], file: [[META1]], line: 1, type: [[META6:![0-9]+]], scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: [[META0]], retainedNodes: [[META2]]) +; CHECK: [[META6]] = !DISubroutineType(types: [[META2]]) +; CHECK: [[META7]] = !DIBasicType(name: "long", size: 64, encoding: DW_ATE_signed) +; CHECK: [[META8]] = !DILocation(line: 2, scope: [[META5]]) +;. diff --git a/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll b/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll index b456ad8224638..5e0fc75a6bbb2 100644 --- a/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll +++ b/llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll @@ -133,7 +133,7 @@ define hidden void @runtime(ptr nocapture %a, ptr nocapture readonly %b, ptr noc ; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_EPIL_PREHEADER]] ; CHECK: for.body.epil.preheader: ; CHECK-NEXT: [[I_09_UNR:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INC_1:%.*]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:%.*]] ] -; CHECK-NEXT: [[LCMP_MOD1:%.*]] = icmp ne i32 [[XTRAITER]], 0 +; CHECK-NEXT: [[LCMP_MOD1:%.*]] = trunc i32 [[N]] to i1 ; CHECK-NEXT: call void @llvm.assume(i1 [[LCMP_MOD1]]) ; CHECK-NEXT: [[ARRAYIDX_EPIL:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i32 [[I_09_UNR]] ; CHECK-NEXT: [[I_EPIL:%.*]] = load i32, ptr [[ARRAYIDX_EPIL]], align 4 diff --git a/llvm/test/Transforms/LoopUnroll/peel-loop-phi-analysis-iv.ll b/llvm/test/Transforms/LoopUnroll/peel-loop-phi-analysis-iv.ll index 4e16bafc65f03..a721534ddc5c1 100644 --- a/llvm/test/Transforms/LoopUnroll/peel-loop-phi-analysis-iv.ll +++ b/llvm/test/Transforms/LoopUnroll/peel-loop-phi-analysis-iv.ll @@ -48,7 +48,7 @@ declare void @g(i32) ; CHECK-NEXT: Name: Peeled ; CHECK-NEXT: Function: binary_induction ; CHECK-NEXT: Args: -; CHECK-NEXT: - String: ' peeled loop by ' +; CHECK-NEXT: - String: 'peeled loop by ' ; CHECK-NEXT: - PeelCount: '3' ; CHECK-NEXT: - String: ' iterations' ; CHECK-NEXT: ... @@ -94,7 +94,7 @@ for.body: ; CHECK-NEXT: Name: Peeled ; CHECK-NEXT: Function: tsvc_s291 ; CHECK-NEXT: Args: -; CHECK-NEXT: - String: ' peeled loop by ' +; CHECK-NEXT: - String: 'peeled loop by ' ; CHECK-NEXT: - PeelCount: '1' ; CHECK-NEXT: - String: ' iterations' ; CHECK-NEXT: ... @@ -132,7 +132,7 @@ exit: ; CHECK-NEXT: Name: Peeled ; CHECK-NEXT: Function: induction_undesirable_peel1 ; CHECK-NEXT: Args: -; CHECK-NEXT: - String: ' peeled loop by ' +; CHECK-NEXT: - String: 'peeled loop by ' ; CHECK-NEXT: - PeelCount: '1' ; CHECK-NEXT: - String: ' iterations' ; CHECK-NEXT: ... @@ -169,7 +169,7 @@ exit: ; CHECK-NEXT: Name: Peeled ; CHECK-NEXT: Function: induction_undesirable_peel2 ; CHECK-NEXT: Args: -; CHECK-NEXT: - String: ' peeled loop by ' +; CHECK-NEXT: - String: 'peeled loop by ' ; CHECK-NEXT: - PeelCount: '1' ; CHECK-NEXT: - String: ' iterations' ; CHECK-NEXT: ... @@ -224,7 +224,7 @@ exit: ; CHECK-NEXT: Name: Peeled ; CHECK-NEXT: Function: induction_undesirable_peel3 ; CHECK-NEXT: Args: -; CHECK-NEXT: - String: ' peeled loop by ' +; CHECK-NEXT: - String: 'peeled loop by ' ; CHECK-NEXT: - PeelCount: '1' ; CHECK-NEXT: - String: ' iterations' ; CHECK-NEXT: ... diff --git a/llvm/test/Transforms/LoopUnroll/unroll-multi-exit-loop-heuristics.ll b/llvm/test/Transforms/LoopUnroll/unroll-multi-exit-loop-heuristics.ll index 34ef92c507afa..82acc932fec63 100644 --- a/llvm/test/Transforms/LoopUnroll/unroll-multi-exit-loop-heuristics.ll +++ b/llvm/test/Transforms/LoopUnroll/unroll-multi-exit-loop-heuristics.ll @@ -1,5 +1,5 @@ -; RUN: opt < %s -passes=loop-unroll -unroll-runtime=true -verify-dom-info -verify-loop-info -S | FileCheck %s -; RUN: opt < %s -passes=loop-unroll -unroll-runtime=true -verify-dom-info -verify-loop-info -unroll-runtime-multi-exit=false -S | FileCheck %s -check-prefix=NOUNROLL +; RUN: opt < %s -passes=loop-unroll -unroll-runtime=true -verify-dom-info -verify-loop-info -unroll-runtime-other-exit-predictable=false -S | FileCheck %s +; RUN: opt < %s -passes=loop-unroll -unroll-runtime=true -verify-dom-info -verify-loop-info -unroll-runtime-multi-exit=false -unroll-runtime-other-exit-predictable=false -S | FileCheck %s -check-prefix=NOUNROLL ; Multi exit loop with predictable exit -- unroll ; Exit before loop body. diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll index 91c65ba8f6267..6ea9809dc8ff8 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll @@ -590,6 +590,81 @@ exit: ret void } +define void @forced_scalar_instr(ptr %gep.dst) { +; COMMON-LABEL: define void @forced_scalar_instr( +; COMMON-SAME: ptr [[GEP_DST:%.*]]) { +; COMMON-NEXT: [[ENTRY:.*:]] +; COMMON-NEXT: br label %[[VECTOR_PH:.*]] +; COMMON: [[VECTOR_PH]]: +; COMMON-NEXT: br label %[[VECTOR_BODY:.*]] +; COMMON: [[VECTOR_BODY]]: +; COMMON-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ] +; COMMON-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ] +; COMMON-NEXT: [[TMP0:%.*]] = trunc i64 [[INDEX]] to i32 +; COMMON-NEXT: [[TMP1:%.*]] = icmp ule <4 x i8> [[VEC_IND]], splat (i8 4) +; COMMON-NEXT: [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i32 0 +; COMMON-NEXT: br i1 [[TMP2]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]] +; COMMON: [[PRED_STORE_IF]]: +; COMMON-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 0 +; COMMON-NEXT: [[TMP4:%.*]] = add i32 [[TMP0]], 0 +; COMMON-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[GEP_DST]], i64 [[TMP3]] +; COMMON-NEXT: [[TMP6:%.*]] = or i32 [[TMP4]], 1 +; COMMON-NEXT: store i32 [[TMP6]], ptr [[TMP5]], align 4 +; COMMON-NEXT: br label %[[PRED_STORE_CONTINUE]] +; COMMON: [[PRED_STORE_CONTINUE]]: +; COMMON-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP1]], i32 1 +; COMMON-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]] +; COMMON: [[PRED_STORE_IF1]]: +; COMMON-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1 +; COMMON-NEXT: [[TMP9:%.*]] = add i32 [[TMP0]], 1 +; COMMON-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[GEP_DST]], i64 [[TMP8]] +; COMMON-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], 1 +; COMMON-NEXT: store i32 [[TMP11]], ptr [[TMP10]], align 4 +; COMMON-NEXT: br label %[[PRED_STORE_CONTINUE2]] +; COMMON: [[PRED_STORE_CONTINUE2]]: +; COMMON-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[TMP1]], i32 2 +; COMMON-NEXT: br i1 [[TMP12]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]] +; COMMON: [[PRED_STORE_IF3]]: +; COMMON-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 2 +; COMMON-NEXT: [[TMP14:%.*]] = add i32 [[TMP0]], 2 +; COMMON-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[GEP_DST]], i64 [[TMP13]] +; COMMON-NEXT: [[TMP16:%.*]] = or i32 [[TMP14]], 1 +; COMMON-NEXT: store i32 [[TMP16]], ptr [[TMP15]], align 4 +; COMMON-NEXT: br label %[[PRED_STORE_CONTINUE4]] +; COMMON: [[PRED_STORE_CONTINUE4]]: +; COMMON-NEXT: [[TMP17:%.*]] = extractelement <4 x i1> [[TMP1]], i32 3 +; COMMON-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]] +; COMMON: [[PRED_STORE_IF5]]: +; COMMON-NEXT: [[TMP18:%.*]] = add i64 [[INDEX]], 3 +; COMMON-NEXT: [[TMP19:%.*]] = add i32 [[TMP0]], 3 +; COMMON-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[GEP_DST]], i64 [[TMP18]] +; COMMON-NEXT: [[TMP21:%.*]] = or i32 [[TMP19]], 1 +; COMMON-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4 +; COMMON-NEXT: br label %[[PRED_STORE_CONTINUE6]] +; COMMON: [[PRED_STORE_CONTINUE6]]: +; COMMON-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; COMMON-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4) +; COMMON-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], 8 +; COMMON-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] +; COMMON: [[MIDDLE_BLOCK]]: +; COMMON-NEXT: br label %[[EXIT:.*]] +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr i32, ptr %gep.dst, i64 %iv + %t = trunc i64 %iv to i32 + %o = or i32 %t, 1 + store i32 %o, ptr %gep, align 4 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, 4 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + attributes #0 = { "target-features"="+neon,+sve" vscale_range(1,16) } attributes #1 = { "target-cpu"="neoverse-512tvb" } diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll index 0f51c21176dc9..9be5953051e44 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll @@ -94,10 +94,10 @@ define i64 @pointer_induction_only(ptr %start, ptr %end) { ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]] ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 -; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: -; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4 +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 8 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[N_VEC]], 4 ; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]] @@ -106,15 +106,15 @@ define i64 @pointer_induction_only(ptr %start, ptr %end) { ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]] -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 2 -; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <2 x i32>, ptr [[TMP7]], align 1 -; CHECK-NEXT: [[TMP9:%.*]] = zext <2 x i32> [[WIDE_LOAD4]] to <2 x i64> -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP5]], align 1 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: -; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <2 x i64> [[TMP9]], i32 1 -; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <2 x i64> [[TMP9]], i32 0 +; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64> +; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP7]], i32 3 +; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP7]], i32 2 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] ; CHECK: [[SCALAR_PH]]: @@ -163,11 +163,11 @@ define i64 @int_and_pointer_iv(ptr %start, i32 %N) { ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]] ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4 ; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4 -; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i32> [[WIDE_LOAD3]] to <4 x i64> ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000 ; CHECK-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i32> [[WIDE_LOAD3]] to <4 x i64> ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP5]], i32 2 ; CHECK-NEXT: br label %[[EXIT:.*]] ; CHECK: [[EXIT]]: @@ -289,15 +289,15 @@ define i64 @test_ptr_ivs_and_widened_ivs(ptr %src, i32 %N) { ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]] ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4 -; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i32> [[WIDE_LOAD]], splat (i32 1) -; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i32> [[TMP7]] to <4 x i64> -; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i32> [[STEP_ADD]] to <4 x i64> -; CHECK-NEXT: [[TMP10:%.*]] = shl <4 x i64> [[TMP8]], [[TMP9]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP9:%.*]] = xor <4 x i32> [[WIDE_LOAD]], splat (i32 1) +; CHECK-NEXT: [[TMP12:%.*]] = zext <4 x i32> [[TMP9]] to <4 x i64> +; CHECK-NEXT: [[TMP13:%.*]] = zext <4 x i32> [[STEP_ADD]] to <4 x i64> +; CHECK-NEXT: [[TMP10:%.*]] = shl <4 x i64> [[TMP12]], [[TMP13]] ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP10]], i32 3 ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP10]], i32 2 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] @@ -875,11 +875,11 @@ define i64 @live_out_extract_from_ptr_iv_increment(i64 %count, ptr %start, ptr n ; CHECK-NEXT: [[TMP81:%.*]] = insertelement <16 x ptr> [[TMP80]], ptr [[TMP65]], i32 13 ; CHECK-NEXT: [[TMP82:%.*]] = insertelement <16 x ptr> [[TMP81]], ptr [[TMP66]], i32 14 ; CHECK-NEXT: [[TMP83:%.*]] = insertelement <16 x ptr> [[TMP82]], ptr [[TMP67]], i32 15 -; CHECK-NEXT: [[TMP84:%.*]] = ptrtoint <16 x ptr> [[TMP83]] to <16 x i64> ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-NEXT: [[TMP85:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP85]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP84:%.*]] = ptrtoint <16 x ptr> [[TMP83]] to <16 x i64> ; CHECK-NEXT: [[TMP86:%.*]] = extractelement <16 x i64> [[TMP84]], i32 15 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] @@ -949,11 +949,11 @@ define i64 @live_out_extract_from_ptr_iv_increment(i64 %count, ptr %start, ptr n ; CHECK-NEXT: [[TMP129:%.*]] = insertelement <8 x ptr> [[TMP128]], ptr [[TMP121]], i32 5 ; CHECK-NEXT: [[TMP130:%.*]] = insertelement <8 x ptr> [[TMP129]], ptr [[TMP122]], i32 6 ; CHECK-NEXT: [[TMP131:%.*]] = insertelement <8 x ptr> [[TMP130]], ptr [[TMP123]], i32 7 -; CHECK-NEXT: [[TMP132:%.*]] = ptrtoint <8 x ptr> [[TMP131]] to <8 x i64> ; CHECK-NEXT: [[INDEX_NEXT28]] = add nuw i64 [[INDEX19]], 8 ; CHECK-NEXT: [[TMP133:%.*]] = icmp eq i64 [[INDEX_NEXT28]], [[N_VEC18]] ; CHECK-NEXT: br i1 [[TMP133]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP27:![0-9]+]] ; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP132:%.*]] = ptrtoint <8 x ptr> [[TMP131]] to <8 x i64> ; CHECK-NEXT: [[TMP134:%.*]] = extractelement <8 x i64> [[TMP132]], i32 7 ; CHECK-NEXT: [[CMP_N29:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC18]] ; CHECK-NEXT: br i1 [[CMP_N29]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll index bdc36ee44559e..e55172f3a3b37 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll @@ -10,8 +10,8 @@ ; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a17 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s ; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a18 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s ; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v2 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s -; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3 -S %s | FileCheck --check-prefix=INTERLEAVE-4-VLA %s -; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3ae -S %s | FileCheck --check-prefix=INTERLEAVE-4-VLA %s +; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s +; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3ae -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s ; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=exynos-m5 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s ; Tests for selecting interleave counts for loops with loads and stores. @@ -207,118 +207,6 @@ define void @interleave_single_load_store(ptr %src, ptr %dst, i64 %N, i8 %a, i8 ; INTERLEAVE-4: exit: ; INTERLEAVE-4-NEXT: ret void ; -; INTERLEAVE-4-VLA-LABEL: @interleave_single_load_store( -; INTERLEAVE-4-VLA-NEXT: iter.check: -; INTERLEAVE-4-VLA-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC:%.*]] to i64 -; INTERLEAVE-4-VLA-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST:%.*]] to i64 -; INTERLEAVE-4-VLA-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], 8 -; INTERLEAVE-4-VLA-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] -; INTERLEAVE-4-VLA: vector.memcheck: -; INTERLEAVE-4-VLA-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() -; INTERLEAVE-4-VLA-NEXT: [[TMP1:%.*]] = mul nuw i64 [[TMP0]], 16 -; INTERLEAVE-4-VLA-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 4 -; INTERLEAVE-4-VLA-NEXT: [[TMP3:%.*]] = sub i64 [[DST1]], [[SRC2]] -; INTERLEAVE-4-VLA-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP3]], [[TMP2]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[DIFF_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] -; INTERLEAVE-4-VLA: vector.main.loop.iter.check: -; INTERLEAVE-4-VLA-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() -; INTERLEAVE-4-VLA-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP4]], 6 -; INTERLEAVE-4-VLA-NEXT: [[MIN_ITERS_CHECK3:%.*]] = icmp ult i64 [[N]], [[TMP5]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[MIN_ITERS_CHECK3]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] -; INTERLEAVE-4-VLA: vector.ph: -; INTERLEAVE-4-VLA-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64() -; INTERLEAVE-4-VLA-NEXT: [[TMP10:%.*]] = shl nuw i64 [[TMP6]], 4 -; INTERLEAVE-4-VLA-NEXT: [[TMP7:%.*]] = shl nuw i64 [[TMP10]], 2 -; INTERLEAVE-4-VLA-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP7]] -; INTERLEAVE-4-VLA-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] -; INTERLEAVE-4-VLA-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i8 [[B:%.*]], i64 0 -; INTERLEAVE-4-VLA-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer -; INTERLEAVE-4-VLA-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement poison, i8 [[A:%.*]], i64 0 -; INTERLEAVE-4-VLA-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector [[BROADCAST_SPLATINSERT4]], poison, zeroinitializer -; INTERLEAVE-4-VLA-NEXT: br label [[VECTOR_BODY:%.*]] -; INTERLEAVE-4-VLA: vector.body: -; INTERLEAVE-4-VLA-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX]] -; INTERLEAVE-4-VLA-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP10]], 1 -; INTERLEAVE-4-VLA-NEXT: [[TMP16:%.*]] = mul nuw nsw i64 [[TMP10]], 3 -; INTERLEAVE-4-VLA-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[TMP10]] -; INTERLEAVE-4-VLA-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[TMP13]] -; INTERLEAVE-4-VLA-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 [[TMP16]] -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP8]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD6:%.*]] = load , ptr [[TMP11]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD7:%.*]] = load , ptr [[TMP14]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD8:%.*]] = load , ptr [[TMP17]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[TMP18:%.*]] = icmp sgt [[WIDE_LOAD]], [[BROADCAST_SPLAT]] -; INTERLEAVE-4-VLA-NEXT: [[TMP19:%.*]] = icmp sgt [[WIDE_LOAD6]], [[BROADCAST_SPLAT]] -; INTERLEAVE-4-VLA-NEXT: [[TMP20:%.*]] = icmp sgt [[WIDE_LOAD7]], [[BROADCAST_SPLAT]] -; INTERLEAVE-4-VLA-NEXT: [[TMP21:%.*]] = icmp sgt [[WIDE_LOAD8]], [[BROADCAST_SPLAT]] -; INTERLEAVE-4-VLA-NEXT: [[TMP22:%.*]] = call @llvm.smax.nxv16i8( [[WIDE_LOAD]], [[BROADCAST_SPLAT5]]) -; INTERLEAVE-4-VLA-NEXT: [[TMP23:%.*]] = call @llvm.smax.nxv16i8( [[WIDE_LOAD6]], [[BROADCAST_SPLAT5]]) -; INTERLEAVE-4-VLA-NEXT: [[TMP24:%.*]] = call @llvm.smax.nxv16i8( [[WIDE_LOAD7]], [[BROADCAST_SPLAT5]]) -; INTERLEAVE-4-VLA-NEXT: [[TMP25:%.*]] = call @llvm.smax.nxv16i8( [[WIDE_LOAD8]], [[BROADCAST_SPLAT5]]) -; INTERLEAVE-4-VLA-NEXT: [[TMP26:%.*]] = select [[TMP18]], [[BROADCAST_SPLAT]], [[TMP22]] -; INTERLEAVE-4-VLA-NEXT: [[TMP27:%.*]] = select [[TMP19]], [[BROADCAST_SPLAT]], [[TMP23]] -; INTERLEAVE-4-VLA-NEXT: [[TMP28:%.*]] = select [[TMP20]], [[BROADCAST_SPLAT]], [[TMP24]] -; INTERLEAVE-4-VLA-NEXT: [[TMP29:%.*]] = select [[TMP21]], [[BROADCAST_SPLAT]], [[TMP25]] -; INTERLEAVE-4-VLA-NEXT: [[TMP30:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX]] -; INTERLEAVE-4-VLA-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr [[TMP30]], i64 [[TMP10]] -; INTERLEAVE-4-VLA-NEXT: [[TMP36:%.*]] = getelementptr inbounds i8, ptr [[TMP30]], i64 [[TMP13]] -; INTERLEAVE-4-VLA-NEXT: [[TMP39:%.*]] = getelementptr inbounds i8, ptr [[TMP30]], i64 [[TMP16]] -; INTERLEAVE-4-VLA-NEXT: store [[TMP26]], ptr [[TMP30]], align 1 -; INTERLEAVE-4-VLA-NEXT: store [[TMP27]], ptr [[TMP33]], align 1 -; INTERLEAVE-4-VLA-NEXT: store [[TMP28]], ptr [[TMP36]], align 1 -; INTERLEAVE-4-VLA-NEXT: store [[TMP29]], ptr [[TMP39]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP7]] -; INTERLEAVE-4-VLA-NEXT: [[TMP40:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[TMP40]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] -; INTERLEAVE-4-VLA: middle.block: -; INTERLEAVE-4-VLA-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] -; INTERLEAVE-4-VLA: vec.epilog.iter.check: -; INTERLEAVE-4-VLA-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 8 -; INTERLEAVE-4-VLA-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] -; INTERLEAVE-4-VLA: vec.epilog.ph: -; INTERLEAVE-4-VLA-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] -; INTERLEAVE-4-VLA-NEXT: [[N_MOD_VF9:%.*]] = urem i64 [[N]], 8 -; INTERLEAVE-4-VLA-NEXT: [[N_VEC10:%.*]] = sub i64 [[N]], [[N_MOD_VF9]] -; INTERLEAVE-4-VLA-NEXT: [[BROADCAST_SPLATINSERT11:%.*]] = insertelement <8 x i8> poison, i8 [[B]], i64 0 -; INTERLEAVE-4-VLA-NEXT: [[BROADCAST_SPLAT12:%.*]] = shufflevector <8 x i8> [[BROADCAST_SPLATINSERT11]], <8 x i8> poison, <8 x i32> zeroinitializer -; INTERLEAVE-4-VLA-NEXT: [[BROADCAST_SPLATINSERT13:%.*]] = insertelement <8 x i8> poison, i8 [[A]], i64 0 -; INTERLEAVE-4-VLA-NEXT: [[BROADCAST_SPLAT14:%.*]] = shufflevector <8 x i8> [[BROADCAST_SPLATINSERT13]], <8 x i8> poison, <8 x i32> zeroinitializer -; INTERLEAVE-4-VLA-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] -; INTERLEAVE-4-VLA: vec.epilog.vector.body: -; INTERLEAVE-4-VLA-NEXT: [[INDEX15:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT17:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[TMP41:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[INDEX15]] -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD16:%.*]] = load <8 x i8>, ptr [[TMP41]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[TMP42:%.*]] = icmp sgt <8 x i8> [[WIDE_LOAD16]], [[BROADCAST_SPLAT12]] -; INTERLEAVE-4-VLA-NEXT: [[TMP43:%.*]] = call <8 x i8> @llvm.smax.v8i8(<8 x i8> [[WIDE_LOAD16]], <8 x i8> [[BROADCAST_SPLAT14]]) -; INTERLEAVE-4-VLA-NEXT: [[TMP44:%.*]] = select <8 x i1> [[TMP42]], <8 x i8> [[BROADCAST_SPLAT12]], <8 x i8> [[TMP43]] -; INTERLEAVE-4-VLA-NEXT: [[TMP45:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX15]] -; INTERLEAVE-4-VLA-NEXT: store <8 x i8> [[TMP44]], ptr [[TMP45]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[INDEX_NEXT17]] = add nuw i64 [[INDEX15]], 8 -; INTERLEAVE-4-VLA-NEXT: [[TMP46:%.*]] = icmp eq i64 [[INDEX_NEXT17]], [[N_VEC10]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[TMP46]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] -; INTERLEAVE-4-VLA: vec.epilog.middle.block: -; INTERLEAVE-4-VLA-NEXT: [[CMP_N18:%.*]] = icmp eq i64 [[N]], [[N_VEC10]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[CMP_N18]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] -; INTERLEAVE-4-VLA: vec.epilog.scalar.ph: -; INTERLEAVE-4-VLA-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC10]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] -; INTERLEAVE-4-VLA-NEXT: br label [[LOOP:%.*]] -; INTERLEAVE-4-VLA: loop: -; INTERLEAVE-4-VLA-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] -; INTERLEAVE-4-VLA-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 [[IV]] -; INTERLEAVE-4-VLA-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[CMP:%.*]] = icmp sgt i8 [[L]], [[B]] -; INTERLEAVE-4-VLA-NEXT: [[MAX:%.*]] = tail call i8 @llvm.smax.i8(i8 [[L]], i8 [[A]]) -; INTERLEAVE-4-VLA-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i8 [[B]], i8 [[MAX]] -; INTERLEAVE-4-VLA-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[IV]] -; INTERLEAVE-4-VLA-NEXT: store i8 [[SEL]], ptr [[GEP_DST]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 -; INTERLEAVE-4-VLA-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] -; INTERLEAVE-4-VLA: exit: -; INTERLEAVE-4-VLA-NEXT: ret void -; entry: br label %loop diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll b/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll index fff9365baccb4..3f7688ee373a6 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll @@ -6,7 +6,7 @@ ; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a15 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s ; RUN: opt -passes=loop-vectorize -mtriple=arm64-apple-macos -mcpu=apple-a16 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s ; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v2 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s -; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3 -S %s | FileCheck --check-prefix=INTERLEAVE-4-VLA %s +; RUN: opt -passes=loop-vectorize -mtriple=arm64 -mcpu=neoverse-v3 -S %s | FileCheck --check-prefix=INTERLEAVE-4 %s ; Tests for selecting the interleave count for loops with reductions. @@ -133,92 +133,6 @@ define i32 @interleave_integer_reduction(ptr %src, i64 %N) { ; INTERLEAVE-2-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i32 [ [[RED_NEXT]], [[LOOP]] ], [ [[TMP5]], [[MIDDLE_BLOCK]] ] ; INTERLEAVE-2-NEXT: ret i32 [[RED_NEXT_LCSSA]] ; -; INTERLEAVE-4-VLA-LABEL: @interleave_integer_reduction( -; INTERLEAVE-4-VLA-NEXT: iter.check: -; INTERLEAVE-4-VLA-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], 2 -; INTERLEAVE-4-VLA-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] -; INTERLEAVE-4-VLA: vector.main.loop.iter.check: -; INTERLEAVE-4-VLA-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() -; INTERLEAVE-4-VLA-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4 -; INTERLEAVE-4-VLA-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], [[TMP1]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] -; INTERLEAVE-4-VLA: vector.ph: -; INTERLEAVE-4-VLA-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() -; INTERLEAVE-4-VLA-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP2]], 2 -; INTERLEAVE-4-VLA-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP5]], 2 -; INTERLEAVE-4-VLA-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]] -; INTERLEAVE-4-VLA-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] -; INTERLEAVE-4-VLA-NEXT: br label [[VECTOR_BODY:%.*]] -; INTERLEAVE-4-VLA: vector.body: -; INTERLEAVE-4-VLA-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[VEC_PHI:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP14:%.*]], [[VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[VEC_PHI2:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP15:%.*]], [[VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[VEC_PHI3:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP16:%.*]], [[VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[VEC_PHI4:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP17:%.*]], [[VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i64 [[INDEX]] -; INTERLEAVE-4-VLA-NEXT: [[TMP9:%.*]] = shl nuw nsw i64 [[TMP5]], 1 -; INTERLEAVE-4-VLA-NEXT: [[TMP12:%.*]] = mul nuw nsw i64 [[TMP5]], 3 -; INTERLEAVE-4-VLA-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP5]] -; INTERLEAVE-4-VLA-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP9]] -; INTERLEAVE-4-VLA-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP12]] -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP4]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD5:%.*]] = load , ptr [[TMP7]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD6:%.*]] = load , ptr [[TMP10]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD7:%.*]] = load , ptr [[TMP13]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[TMP14]] = add [[VEC_PHI]], [[WIDE_LOAD]] -; INTERLEAVE-4-VLA-NEXT: [[TMP15]] = add [[VEC_PHI2]], [[WIDE_LOAD5]] -; INTERLEAVE-4-VLA-NEXT: [[TMP16]] = add [[VEC_PHI3]], [[WIDE_LOAD6]] -; INTERLEAVE-4-VLA-NEXT: [[TMP17]] = add [[VEC_PHI4]], [[WIDE_LOAD7]] -; INTERLEAVE-4-VLA-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]] -; INTERLEAVE-4-VLA-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] -; INTERLEAVE-4-VLA: middle.block: -; INTERLEAVE-4-VLA-NEXT: [[BIN_RDX:%.*]] = add [[TMP15]], [[TMP14]] -; INTERLEAVE-4-VLA-NEXT: [[BIN_RDX8:%.*]] = add [[TMP16]], [[BIN_RDX]] -; INTERLEAVE-4-VLA-NEXT: [[BIN_RDX9:%.*]] = add [[TMP17]], [[BIN_RDX8]] -; INTERLEAVE-4-VLA-NEXT: [[TMP19:%.*]] = call i32 @llvm.vector.reduce.add.nxv4i32( [[BIN_RDX9]]) -; INTERLEAVE-4-VLA-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] -; INTERLEAVE-4-VLA: vec.epilog.iter.check: -; INTERLEAVE-4-VLA-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 2 -; INTERLEAVE-4-VLA-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] -; INTERLEAVE-4-VLA: vec.epilog.ph: -; INTERLEAVE-4-VLA-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] -; INTERLEAVE-4-VLA-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP19]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] -; INTERLEAVE-4-VLA-NEXT: [[N_MOD_VF10:%.*]] = urem i64 [[N]], 2 -; INTERLEAVE-4-VLA-NEXT: [[N_VEC11:%.*]] = sub i64 [[N]], [[N_MOD_VF10]] -; INTERLEAVE-4-VLA-NEXT: [[TMP20:%.*]] = insertelement <2 x i32> zeroinitializer, i32 [[BC_MERGE_RDX]], i32 0 -; INTERLEAVE-4-VLA-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] -; INTERLEAVE-4-VLA: vec.epilog.vector.body: -; INTERLEAVE-4-VLA-NEXT: [[INDEX12:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT15:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[VEC_PHI13:%.*]] = phi <2 x i32> [ [[TMP20]], [[VEC_EPILOG_PH]] ], [ [[TMP22:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] -; INTERLEAVE-4-VLA-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX12]] -; INTERLEAVE-4-VLA-NEXT: [[WIDE_LOAD14:%.*]] = load <2 x i32>, ptr [[TMP21]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[TMP22]] = add <2 x i32> [[VEC_PHI13]], [[WIDE_LOAD14]] -; INTERLEAVE-4-VLA-NEXT: [[INDEX_NEXT15]] = add nuw i64 [[INDEX12]], 2 -; INTERLEAVE-4-VLA-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT15]], [[N_VEC11]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[TMP23]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] -; INTERLEAVE-4-VLA: vec.epilog.middle.block: -; INTERLEAVE-4-VLA-NEXT: [[TMP24:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[TMP22]]) -; INTERLEAVE-4-VLA-NEXT: [[CMP_N16:%.*]] = icmp eq i64 [[N]], [[N_VEC11]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[CMP_N16]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] -; INTERLEAVE-4-VLA: vec.epilog.scalar.ph: -; INTERLEAVE-4-VLA-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC11]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] -; INTERLEAVE-4-VLA-NEXT: [[BC_MERGE_RDX17:%.*]] = phi i32 [ [[TMP24]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP19]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK]] ] -; INTERLEAVE-4-VLA-NEXT: br label [[LOOP:%.*]] -; INTERLEAVE-4-VLA: loop: -; INTERLEAVE-4-VLA-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] -; INTERLEAVE-4-VLA-NEXT: [[RED:%.*]] = phi i32 [ [[BC_MERGE_RDX17]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ] -; INTERLEAVE-4-VLA-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]] -; INTERLEAVE-4-VLA-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 1 -; INTERLEAVE-4-VLA-NEXT: [[RED_NEXT]] = add i32 [[RED]], [[L]] -; INTERLEAVE-4-VLA-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 -; INTERLEAVE-4-VLA-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] -; INTERLEAVE-4-VLA-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] -; INTERLEAVE-4-VLA: exit: -; INTERLEAVE-4-VLA-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i32 [ [[RED_NEXT]], [[LOOP]] ], [ [[TMP19]], [[MIDDLE_BLOCK]] ], [ [[TMP24]], [[VEC_EPILOG_MIDDLE_BLOCK]] ] -; INTERLEAVE-4-VLA-NEXT: ret i32 [[RED_NEXT_LCSSA]] -; entry: br label %loop diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll index 9dfb987bd24a6..3951b88e41d55 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/invariant-replicate-region.ll @@ -42,11 +42,11 @@ define i32 @test_invariant_replicate_region(i32 %x, i1 %c) { ; CHECK-NEXT: br label %[[PRED_UREM_CONTINUE6]] ; CHECK: [[PRED_UREM_CONTINUE6]]: ; CHECK-NEXT: [[TMP12:%.*]] = phi <4 x i32> [ [[TMP11]], %[[PRED_UREM_CONTINUE4]] ], [ [[TMP14]], %[[PRED_UREM_IF5]] ] -; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], <4 x i32> [[TMP12]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100 ; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], <4 x i32> [[TMP12]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3 ; CHECK-NEXT: br label %[[EXIT:.*]] ; CHECK: [[EXIT]]: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll index 55994ad9a98f8..66247a4f8100e 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "(:|sincos|modf|extractvalue|store|with\.overflow)" --version 5 +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "(:|sincos|modf|extractvalue|store)" --version 5 ; RUN: opt -passes=loop-vectorize -mtriple=aarch64-gnu-linux -mcpu=neoverse-v1 -mattr=+sve < %s -S -o - -debug-only=loop-vectorize 2>%t.1 | FileCheck %s --check-prefix=CHECK ; RUN: opt -passes=loop-vectorize -mtriple=aarch64-gnu-linux -mcpu=neoverse-v1 -mattr=+sve -vector-library=ArmPL < %s -S -o - -debug-only=loop-vectorize 2>%t.2 | FileCheck %s --check-prefix=CHECK-ARMPL ; RUN: FileCheck --input-file=%t.1 --check-prefix=CHECK-COST %s @@ -526,75 +526,3 @@ for.body: exit: ret void } - -; CHECK-COST-LABEL: sadd_with_overflow_i32 -; CHECK-COST: LV: Found an estimated cost of 1 for VF 1 For instruction: %call = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %val_a, i32 %val_b) -; CHECK-COST: Cost of 4 for VF 2: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST: Cost of 4 for VF 4: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST: Cost of 7 for VF 8: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST: Cost of 13 for VF 16: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST: Cost of Invalid for VF vscale x 1: REPLICATE ir<%call> = call @llvm.sadd.with.overflow.i32(ir<%val_a>, ir<%val_b>) -; CHECK-COST: Cost of 4 for VF vscale x 2: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST: Cost of 4 for VF vscale x 4: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) - -; CHECK-COST-ARMPL-LABEL: sadd_with_overflow_i32 -; CHECK-COST-ARMPL: LV: Found an estimated cost of 1 for VF 1 For instruction: %call = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %val_a, i32 %val_b) -; CHECK-COST-ARMPL: Cost of 4 for VF 2: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST-ARMPL: Cost of 4 for VF 4: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST-ARMPL: Cost of 7 for VF 8: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST-ARMPL: Cost of 13 for VF 16: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST-ARMPL: Cost of Invalid for VF vscale x 1: REPLICATE ir<%call> = call @llvm.sadd.with.overflow.i32(ir<%val_a>, ir<%val_b>) -; CHECK-COST-ARMPL: Cost of 4 for VF vscale x 2: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) -; CHECK-COST-ARMPL: Cost of 4 for VF vscale x 4: WIDEN-INTRINSIC ir<%call> = call llvm.sadd.with.overflow(ir<%val_a>, ir<%val_b>) - -define void @sadd_with_overflow_i32(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @sadd_with_overflow_i32( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) #[[ATTR0]] { -; CHECK: [[ENTRY:.*:]] -; CHECK: [[VECTOR_PH:.*:]] -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[TMP9:%.*]] = call { , } @llvm.sadd.with.overflow.nxv4i32( [[WIDE_MASKED_LOAD:%.*]], [[WIDE_MASKED_LOAD1:%.*]]) -; CHECK: [[TMP10:%.*]] = extractvalue { , } [[TMP9]], 0 -; CHECK: [[TMP11:%.*]] = extractvalue { , } [[TMP9]], 1 -; CHECK: call void @llvm.masked.store.nxv4i32.p0( [[TMP10]], ptr align 4 [[TMP13:%.*]], [[ACTIVE_LANE_MASK:%.*]]) -; CHECK: call void @llvm.masked.store.nxv4i8.p0( [[TMP12:%.*]], ptr align 1 [[TMP14:%.*]], [[ACTIVE_LANE_MASK]]) -; CHECK: [[MIDDLE_BLOCK:.*:]] -; CHECK: [[EXIT:.*:]] -; -; CHECK-ARMPL-LABEL: define void @sadd_with_overflow_i32( -; CHECK-ARMPL-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) #[[ATTR0]] { -; CHECK-ARMPL: [[ENTRY:.*:]] -; CHECK-ARMPL: [[VECTOR_PH:.*:]] -; CHECK-ARMPL: [[VECTOR_BODY:.*:]] -; CHECK-ARMPL: [[TMP9:%.*]] = call { , } @llvm.sadd.with.overflow.nxv4i32( [[WIDE_MASKED_LOAD:%.*]], [[WIDE_MASKED_LOAD1:%.*]]) -; CHECK-ARMPL: [[TMP10:%.*]] = extractvalue { , } [[TMP9]], 0 -; CHECK-ARMPL: [[TMP11:%.*]] = extractvalue { , } [[TMP9]], 1 -; CHECK-ARMPL: call void @llvm.masked.store.nxv4i32.p0( [[TMP10]], ptr align 4 [[TMP13:%.*]], [[ACTIVE_LANE_MASK:%.*]]) -; CHECK-ARMPL: call void @llvm.masked.store.nxv4i8.p0( [[TMP12:%.*]], ptr align 1 [[TMP14:%.*]], [[ACTIVE_LANE_MASK]]) -; CHECK-ARMPL: [[MIDDLE_BLOCK:.*:]] -; CHECK-ARMPL: [[EXIT:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i32, ptr %in_a, i64 %iv - %val_a = load i32, ptr %arrayidx_a, align 4 - %arrayidx_b = getelementptr inbounds i32, ptr %in_b, i64 %iv - %val_b = load i32, ptr %arrayidx_b, align 4 - %call = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %val_a, i32 %val_b) - %result = extractvalue { i32, i1 } %call, 0 - %overflow = extractvalue { i32, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i32, ptr %out_result, i64 %iv - store i32 %result, ptr %arrayidx_result, align 4 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/neoverse-epilogue-vect.ll b/llvm/test/Transforms/LoopVectorize/AArch64/neoverse-epilogue-vect.ll index 9e42c3c5dcab7..7d02faa3d2c2d 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/neoverse-epilogue-vect.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/neoverse-epilogue-vect.ll @@ -72,17 +72,13 @@ entry: br i1 %17, label %7, label %9 } -; TODO: The V3 will generate a scalable vector body, so doesn't need a -; epilogue loop, but will need to be checked that is really the best thing to -; for the V3. -; define noundef i32 @V3(ptr noalias nocapture noundef %0, ptr noalias nocapture noundef readonly %1, i32 noundef %2) #2 { ; ; CHECK-LABEL: @V3( -; CHECK-NOT: vec.epilog.ph: -; CHECK-NOT: vec.epilog.vector.body: -; CHECK-NOT: vec.epilog.middle.block: -; CHECK-NOT: vec.epilog.scalar.ph: +; CHECK: vec.epilog.ph: +; CHECK: vec.epilog.vector.body: +; CHECK: vec.epilog.middle.block: +; CHECK: vec.epilog.scalar.ph: ; entry: %4 = icmp sgt i32 %2, 0 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll index b2be0e1d7a442..ad92b56218bb5 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll @@ -493,12 +493,12 @@ define i32 @not_dotp_not_loop_carried(ptr %a, ptr %b) { ; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <16 x i8>, ptr [[TMP4]], align 1 ; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = zext <16 x i8> [[WIDE_LOAD1]] to <16 x i32> ; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = mul <16 x i32> [[TMP6]], [[TMP3]] -; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = shufflevector <16 x i32> [[VECTOR_RECUR]], <16 x i32> [[TMP7]], <16 x i32> -; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = add <16 x i32> [[TMP7]], [[TMP8]] ; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK-INTERLEAVE1: middle.block: +; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = shufflevector <16 x i32> [[VECTOR_RECUR]], <16 x i32> [[TMP7]], <16 x i32> +; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = add <16 x i32> [[TMP7]], [[TMP8]] ; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = extractelement <16 x i32> [[TMP9]], i32 15 ; CHECK-INTERLEAVE1-NEXT: br label [[FOR_EXIT:%.*]] ; CHECK-INTERLEAVE1: for.exit: @@ -526,12 +526,12 @@ define i32 @not_dotp_not_loop_carried(ptr %a, ptr %b) { ; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = zext <16 x i8> [[WIDE_LOAD3]] to <16 x i32> ; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = mul <16 x i32> [[TMP6]], [[TMP3]] ; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = mul <16 x i32> [[TMP12]], [[TMP8]] -; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = shufflevector <16 x i32> [[TMP7]], <16 x i32> [[TMP13]], <16 x i32> -; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = add <16 x i32> [[TMP13]], [[TMP14]] ; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 ; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK-INTERLEAVED: middle.block: +; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = shufflevector <16 x i32> [[TMP7]], <16 x i32> [[TMP13]], <16 x i32> +; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = add <16 x i32> [[TMP13]], [[TMP14]] ; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = extractelement <16 x i32> [[TMP9]], i32 15 ; CHECK-INTERLEAVED-NEXT: br label [[FOR_EXIT:%.*]] ; CHECK-INTERLEAVED: for.exit: @@ -553,12 +553,12 @@ define i32 @not_dotp_not_loop_carried(ptr %a, ptr %b) { ; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <16 x i8>, ptr [[TMP4]], align 1 ; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = zext <16 x i8> [[WIDE_LOAD1]] to <16 x i32> ; CHECK-MAXBW-NEXT: [[TMP7]] = mul <16 x i32> [[TMP6]], [[TMP3]] -; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = shufflevector <16 x i32> [[VECTOR_RECUR]], <16 x i32> [[TMP7]], <16 x i32> -; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = add <16 x i32> [[TMP7]], [[TMP8]] ; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK-MAXBW: middle.block: +; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = shufflevector <16 x i32> [[VECTOR_RECUR]], <16 x i32> [[TMP7]], <16 x i32> +; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = add <16 x i32> [[TMP7]], [[TMP8]] ; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = extractelement <16 x i32> [[TMP9]], i32 15 ; CHECK-MAXBW-NEXT: br label [[FOR_EXIT:%.*]] ; CHECK-MAXBW: for.exit: @@ -1911,12 +1911,12 @@ define i32 @dotp_ext_mul(i64 %n, ptr %a, i8 %b) { ; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[BROADCAST_SPLAT]] to <8 x i32> ; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul <8 x i32> [[TMP2]], [[TMP2]] ; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP3]]) -; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> -; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = sext <8 x i32> [[TMP4]] to <8 x i64> ; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; CHECK-INTERLEAVE1: middle.block: +; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> +; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = sext <8 x i32> [[TMP8]] to <8 x i64> ; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[PARTIAL_REDUCE]]) ; CHECK-INTERLEAVE1-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP5]], i32 7 ; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] @@ -1946,12 +1946,12 @@ define i32 @dotp_ext_mul(i64 %n, ptr %a, i8 %b) { ; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul <8 x i32> [[TMP2]], [[TMP2]] ; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP3]]) ; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE2]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI1]], <8 x i32> [[TMP3]]) -; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT4]] to <8 x i32> -; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = sext <8 x i32> [[TMP4]] to <8 x i64> ; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVED-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; CHECK-INTERLEAVED: middle.block: +; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT4]] to <8 x i32> +; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = sext <8 x i32> [[TMP8]] to <8 x i64> ; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[PARTIAL_REDUCE2]], [[PARTIAL_REDUCE]] ; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]]) ; CHECK-INTERLEAVED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP5]], i32 7 @@ -1980,12 +1980,12 @@ define i32 @dotp_ext_mul(i64 %n, ptr %a, i8 %b) { ; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[BROADCAST_SPLAT]] to <8 x i32> ; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul <8 x i32> [[TMP2]], [[TMP2]] ; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call <2 x i32> @llvm.vector.partial.reduce.add.v2i32.v8i32(<2 x i32> [[VEC_PHI]], <8 x i32> [[TMP3]]) -; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> -; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = sext <8 x i32> [[TMP4]] to <8 x i64> ; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-MAXBW-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; CHECK-MAXBW: middle.block: +; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> +; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = sext <8 x i32> [[TMP8]] to <8 x i64> ; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[PARTIAL_REDUCE]]) ; CHECK-MAXBW-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP5]], i32 7 ; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] @@ -2037,12 +2037,12 @@ define i64 @not_dotp_ext_mul_8to64(i64 %n, ptr %a, i8 %b) { ; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i64 0 ; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT1]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-INTERLEAVE1-NEXT: [[TMP5]] = add <8 x i64> [[VEC_PHI]], [[TMP3]] -; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> -; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP6]] to <8 x i64> ; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] ; CHECK-INTERLEAVE1: middle.block: +; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> +; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP10]] to <8 x i64> ; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> [[TMP5]]) ; CHECK-INTERLEAVE1-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP7]], i32 7 ; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] @@ -2073,12 +2073,12 @@ define i64 @not_dotp_ext_mul_8to64(i64 %n, ptr %a, i8 %b) { ; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT2]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-INTERLEAVED-NEXT: [[TMP5]] = add <8 x i64> [[VEC_PHI]], [[TMP3]] ; CHECK-INTERLEAVED-NEXT: [[TMP6]] = add <8 x i64> [[VEC_PHI1]], [[TMP3]] -; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT3]] to <8 x i32> -; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = sext <8 x i32> [[TMP7]] to <8 x i64> ; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVED-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] ; CHECK-INTERLEAVED: middle.block: +; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT3]] to <8 x i32> +; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = sext <8 x i32> [[TMP11]] to <8 x i64> ; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = add <8 x i64> [[TMP6]], [[TMP5]] ; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> [[BIN_RDX]]) ; CHECK-INTERLEAVED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP8]], i32 7 @@ -2108,12 +2108,12 @@ define i64 @not_dotp_ext_mul_8to64(i64 %n, ptr %a, i8 %b) { ; CHECK-MAXBW-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i64 0 ; CHECK-MAXBW-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT1]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-MAXBW-NEXT: [[TMP5]] = add <8 x i64> [[VEC_PHI]], [[TMP3]] -; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> -; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP6]] to <8 x i64> ; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] ; CHECK-MAXBW: middle.block: +; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> +; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP10]] to <8 x i64> ; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> [[TMP5]]) ; CHECK-MAXBW-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP7]], i32 7 ; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] @@ -2165,12 +2165,12 @@ define i32 @not_dotp_sext_mul_zext(i64 %n, ptr %a, i8 %b) { ; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i64 0 ; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT1]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-INTERLEAVE1-NEXT: [[TMP5]] = add <8 x i32> [[VEC_PHI]], [[TMP3]] -; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> -; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP6]] to <8 x i64> ; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] ; CHECK-INTERLEAVE1: middle.block: +; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> +; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP10]] to <8 x i64> ; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP5]]) ; CHECK-INTERLEAVE1-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP7]], i32 7 ; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] @@ -2201,12 +2201,12 @@ define i32 @not_dotp_sext_mul_zext(i64 %n, ptr %a, i8 %b) { ; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT2]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-INTERLEAVED-NEXT: [[TMP5]] = add <8 x i32> [[VEC_PHI]], [[TMP3]] ; CHECK-INTERLEAVED-NEXT: [[TMP6]] = add <8 x i32> [[VEC_PHI1]], [[TMP3]] -; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT3]] to <8 x i32> -; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = sext <8 x i32> [[TMP7]] to <8 x i64> ; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVED-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] ; CHECK-INTERLEAVED: middle.block: +; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT3]] to <8 x i32> +; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = sext <8 x i32> [[TMP11]] to <8 x i64> ; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = add <8 x i32> [[TMP6]], [[TMP5]] ; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[BIN_RDX]]) ; CHECK-INTERLEAVED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP8]], i32 7 @@ -2236,12 +2236,12 @@ define i32 @not_dotp_sext_mul_zext(i64 %n, ptr %a, i8 %b) { ; CHECK-MAXBW-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i64 0 ; CHECK-MAXBW-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT1]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-MAXBW-NEXT: [[TMP5]] = add <8 x i32> [[VEC_PHI]], [[TMP3]] -; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> -; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP6]] to <8 x i64> ; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] ; CHECK-MAXBW: middle.block: +; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> +; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP10]] to <8 x i64> ; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP5]]) ; CHECK-MAXBW-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP7]], i32 7 ; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] @@ -2293,12 +2293,12 @@ define i32 @not_dotp_zext_mul_sext(i64 %n, ptr %a, i8 %b) { ; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i64 0 ; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT1]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-INTERLEAVE1-NEXT: [[TMP5]] = add <8 x i32> [[VEC_PHI]], [[TMP3]] -; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> -; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP6]] to <8 x i64> ; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] ; CHECK-INTERLEAVE1: middle.block: +; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> +; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP10]] to <8 x i64> ; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP5]]) ; CHECK-INTERLEAVE1-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP7]], i32 7 ; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] @@ -2329,12 +2329,12 @@ define i32 @not_dotp_zext_mul_sext(i64 %n, ptr %a, i8 %b) { ; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT2]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-INTERLEAVED-NEXT: [[TMP5]] = add <8 x i32> [[VEC_PHI]], [[TMP3]] ; CHECK-INTERLEAVED-NEXT: [[TMP6]] = add <8 x i32> [[VEC_PHI1]], [[TMP3]] -; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT3]] to <8 x i32> -; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = sext <8 x i32> [[TMP7]] to <8 x i64> ; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVED-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] ; CHECK-INTERLEAVED: middle.block: +; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT3]] to <8 x i32> +; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = sext <8 x i32> [[TMP11]] to <8 x i64> ; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = add <8 x i32> [[TMP6]], [[TMP5]] ; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[BIN_RDX]]) ; CHECK-INTERLEAVED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP8]], i32 7 @@ -2364,12 +2364,12 @@ define i32 @not_dotp_zext_mul_sext(i64 %n, ptr %a, i8 %b) { ; CHECK-MAXBW-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i64 0 ; CHECK-MAXBW-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT1]], <8 x i16> poison, <8 x i32> zeroinitializer ; CHECK-MAXBW-NEXT: [[TMP5]] = add <8 x i32> [[VEC_PHI]], [[TMP3]] -; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> -; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP6]] to <8 x i64> ; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] ; CHECK-MAXBW: middle.block: +; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = sext <8 x i16> [[BROADCAST_SPLAT2]] to <8 x i32> +; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = sext <8 x i32> [[TMP10]] to <8 x i64> ; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP5]]) ; CHECK-MAXBW-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <8 x i64> [[TMP7]], i32 7 ; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll index 7db519ffceb98..abd1aba6a615b 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll @@ -778,12 +778,12 @@ define i32 @not_dotp_not_loop_carried(ptr %a, ptr %b) #0 { ; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <16 x i8>, ptr [[TMP13]], align 1 ; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = zext <16 x i8> [[WIDE_LOAD1]] to <16 x i32> ; CHECK-INTERLEAVE1-NEXT: [[TMP4]] = mul <16 x i32> [[TMP3]], [[TMP1]] -; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = shufflevector <16 x i32> [[VECTOR_RECUR]], <16 x i32> [[TMP4]], <16 x i32> -; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = add <16 x i32> [[TMP4]], [[TMP5]] ; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; CHECK-INTERLEAVE1: middle.block: +; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = shufflevector <16 x i32> [[VECTOR_RECUR]], <16 x i32> [[TMP4]], <16 x i32> +; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = add <16 x i32> [[TMP4]], [[TMP9]] ; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = extractelement <16 x i32> [[TMP6]], i32 15 ; CHECK-INTERLEAVE1-NEXT: br label [[FOR_EXIT:%.*]] ; CHECK-INTERLEAVE1: for.exit: @@ -811,12 +811,12 @@ define i32 @not_dotp_not_loop_carried(ptr %a, ptr %b) #0 { ; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = zext <16 x i8> [[WIDE_LOAD3]] to <16 x i32> ; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = mul <16 x i32> [[TMP6]], [[TMP2]] ; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = mul <16 x i32> [[TMP7]], [[TMP3]] -; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = shufflevector <16 x i32> [[TMP8]], <16 x i32> [[TMP9]], <16 x i32> -; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = add <16 x i32> [[TMP9]], [[TMP14]] ; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 ; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-INTERLEAVED-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; CHECK-INTERLEAVED: middle.block: +; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = shufflevector <16 x i32> [[TMP8]], <16 x i32> [[TMP9]], <16 x i32> +; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = add <16 x i32> [[TMP9]], [[TMP14]] ; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = extractelement <16 x i32> [[TMP11]], i32 15 ; CHECK-INTERLEAVED-NEXT: br label [[FOR_EXIT:%.*]] ; CHECK-INTERLEAVED: for.exit: @@ -838,12 +838,12 @@ define i32 @not_dotp_not_loop_carried(ptr %a, ptr %b) #0 { ; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <16 x i8>, ptr [[TMP17]], align 1 ; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = zext <16 x i8> [[WIDE_LOAD1]] to <16 x i32> ; CHECK-MAXBW-NEXT: [[TMP4]] = mul <16 x i32> [[TMP3]], [[TMP1]] -; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = shufflevector <16 x i32> [[VECTOR_RECUR]], <16 x i32> [[TMP4]], <16 x i32> -; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = add <16 x i32> [[TMP4]], [[TMP5]] ; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-MAXBW-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; CHECK-MAXBW: middle.block: +; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = shufflevector <16 x i32> [[VECTOR_RECUR]], <16 x i32> [[TMP4]], <16 x i32> +; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = add <16 x i32> [[TMP4]], [[TMP9]] ; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = extractelement <16 x i32> [[TMP6]], i32 15 ; CHECK-MAXBW-NEXT: br label [[FOR_EXIT:%.*]] ; CHECK-MAXBW: for.exit: @@ -878,28 +878,28 @@ define i32 @not_dotp_not_phi(ptr %a, ptr %b) #0 { ; CHECK-INTERLEAVE1-NEXT: br label [[VECTOR_PH:%.*]] ; CHECK-INTERLEAVE1: vector.ph: ; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 3 +; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 4 ; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]] ; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] ; CHECK-INTERLEAVE1-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-INTERLEAVE1: vector.body: ; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]] -; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP10]], align 1 -; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = zext [[WIDE_LOAD]] to +; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP10]], align 1 ; CHECK-INTERLEAVE1-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]] -; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load , ptr [[TMP13]], align 1 -; CHECK-INTERLEAVE1-NEXT: [[TMP15:%.*]] = zext [[WIDE_LOAD1]] to -; CHECK-INTERLEAVE1-NEXT: [[TMP16:%.*]] = mul [[TMP15]], [[TMP12]] -; CHECK-INTERLEAVE1-NEXT: [[TMP17:%.*]] = add [[TMP16]], [[TMP15]] +; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load , ptr [[TMP13]], align 1 ; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]] ; CHECK-INTERLEAVE1-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK-INTERLEAVE1: middle.block: +; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = zext [[WIDE_LOAD]] to +; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = zext [[WIDE_LOAD1]] to +; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = mul [[TMP6]], [[TMP5]] +; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = add [[TMP7]], [[TMP6]] ; CHECK-INTERLEAVE1-NEXT: [[TMP23:%.*]] = call i32 @llvm.vscale.i32() -; CHECK-INTERLEAVE1-NEXT: [[TMP24:%.*]] = mul nuw i32 [[TMP23]], 8 +; CHECK-INTERLEAVE1-NEXT: [[TMP24:%.*]] = mul nuw i32 [[TMP23]], 16 ; CHECK-INTERLEAVE1-NEXT: [[TMP25:%.*]] = sub i32 [[TMP24]], 1 -; CHECK-INTERLEAVE1-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[TMP17]], i32 [[TMP25]] +; CHECK-INTERLEAVE1-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[TMP8]], i32 [[TMP25]] ; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] ; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH:%.*]] ; CHECK-INTERLEAVE1: scalar.ph: @@ -910,7 +910,7 @@ define i32 @not_dotp_not_phi(ptr %a, ptr %b) #0 { ; CHECK-INTERLEAVED-NEXT: br label [[VECTOR_PH:%.*]] ; CHECK-INTERLEAVED: vector.ph: ; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP2]], 3 +; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP2]], 4 ; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 1 ; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]] ; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] @@ -918,23 +918,23 @@ define i32 @not_dotp_not_phi(ptr %a, ptr %b) #0 { ; CHECK-INTERLEAVED: vector.body: ; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]] -; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP10]], i64 [[TMP1]] -; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP14]], align 1 -; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = zext [[WIDE_LOAD]] to -; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]] -; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP16]], i64 [[TMP1]] -; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD1:%.*]] = load , ptr [[TMP20]], align 1 -; CHECK-INTERLEAVED-NEXT: [[TMP22:%.*]] = zext [[WIDE_LOAD1]] to -; CHECK-INTERLEAVED-NEXT: [[TMP30:%.*]] = mul [[TMP22]], [[TMP15]] -; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = add [[TMP30]], [[TMP22]] +; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP10]], i64 [[TMP1]] +; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP4]], align 1 +; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]] +; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i64 [[TMP1]] +; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD1:%.*]] = load , ptr [[TMP6]], align 1 ; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]] ; CHECK-INTERLEAVED-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-INTERLEAVED-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK-INTERLEAVED: middle.block: +; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = zext [[WIDE_LOAD]] to +; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = zext [[WIDE_LOAD1]] to +; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = mul [[TMP15]], [[TMP11]] +; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = add [[TMP17]], [[TMP15]] ; CHECK-INTERLEAVED-NEXT: [[TMP27:%.*]] = call i32 @llvm.vscale.i32() -; CHECK-INTERLEAVED-NEXT: [[TMP28:%.*]] = mul nuw i32 [[TMP27]], 8 +; CHECK-INTERLEAVED-NEXT: [[TMP28:%.*]] = mul nuw i32 [[TMP27]], 16 ; CHECK-INTERLEAVED-NEXT: [[TMP29:%.*]] = sub i32 [[TMP28]], 1 -; CHECK-INTERLEAVED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[TMP21]], i32 [[TMP29]] +; CHECK-INTERLEAVED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[TMP21]], i32 [[TMP29]] ; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] ; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH:%.*]] ; CHECK-INTERLEAVED: scalar.ph: @@ -945,28 +945,28 @@ define i32 @not_dotp_not_phi(ptr %a, ptr %b) #0 { ; CHECK-MAXBW-NEXT: br label [[VECTOR_PH:%.*]] ; CHECK-MAXBW: vector.ph: ; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() -; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 3 +; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 4 ; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]] ; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]] ; CHECK-MAXBW-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-MAXBW: vector.body: ; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]] -; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP10]], align 1 -; CHECK-MAXBW-NEXT: [[TMP14:%.*]] = zext [[WIDE_LOAD]] to +; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP10]], align 1 ; CHECK-MAXBW-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]] -; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load , ptr [[TMP15]], align 1 -; CHECK-MAXBW-NEXT: [[TMP19:%.*]] = zext [[WIDE_LOAD1]] to -; CHECK-MAXBW-NEXT: [[TMP20:%.*]] = mul [[TMP19]], [[TMP14]] -; CHECK-MAXBW-NEXT: [[TMP21:%.*]] = add [[TMP20]], [[TMP19]] +; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load , ptr [[TMP15]], align 1 ; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]] ; CHECK-MAXBW-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-MAXBW-NEXT: br i1 [[TMP22]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK-MAXBW: middle.block: +; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = zext [[WIDE_LOAD]] to +; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = zext [[WIDE_LOAD1]] to +; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = mul [[TMP6]], [[TMP5]] +; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = add [[TMP7]], [[TMP6]] ; CHECK-MAXBW-NEXT: [[TMP23:%.*]] = call i32 @llvm.vscale.i32() -; CHECK-MAXBW-NEXT: [[TMP24:%.*]] = mul nuw i32 [[TMP23]], 8 +; CHECK-MAXBW-NEXT: [[TMP24:%.*]] = mul nuw i32 [[TMP23]], 16 ; CHECK-MAXBW-NEXT: [[TMP25:%.*]] = sub i32 [[TMP24]], 1 -; CHECK-MAXBW-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[TMP21]], i32 [[TMP25]] +; CHECK-MAXBW-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[TMP8]], i32 [[TMP25]] ; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] ; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH:%.*]] ; CHECK-MAXBW: scalar.ph: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll index 314a4cc2b778d..c94b8996718e1 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll @@ -891,7 +891,61 @@ for.exit: ; preds = %for.body ret float %add } + +define double @chained_fp_reduction_no_partial_reduce(ptr %p) #1 { +; CHECK-LABEL: define double @chained_fp_reduction_no_partial_reduce( +; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: [[LOOP:.*]]: +; CHECK-NEXT: br label %[[EXIT:.*]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[LOOP]] ], [ [[IV_NEXT:%.*]], %[[EXIT]] ] +; CHECK-NEXT: [[ACCUM:%.*]] = phi double [ 0.000000e+00, %[[LOOP]] ], [ [[ADD3:%.*]], %[[EXIT]] ] +; CHECK-NEXT: [[GEP1:%.*]] = getelementptr [11 x float], ptr [[P]], i64 [[IV]] +; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i8, ptr [[GEP1]], i64 12 +; CHECK-NEXT: [[LD1:%.*]] = load float, ptr [[GEP1]], align 4 +; CHECK-NEXT: [[EXT1:%.*]] = fpext float [[LD1]] to double +; CHECK-NEXT: [[ADD1:%.*]] = fadd reassoc contract double [[ACCUM]], [[EXT1]] +; CHECK-NEXT: [[LD2:%.*]] = load float, ptr [[GEP2]], align 4 +; CHECK-NEXT: [[EXT2:%.*]] = fpext float [[LD2]] to double +; CHECK-NEXT: [[ADD2:%.*]] = fadd reassoc contract double [[ADD1]], [[EXT2]] +; CHECK-NEXT: [[LD3:%.*]] = load float, ptr [[GEP1]], align 4 +; CHECK-NEXT: [[EXT3:%.*]] = fpext float [[LD3]] to double +; CHECK-NEXT: [[ADD3]] = fadd reassoc contract double [[ADD2]], [[EXT3]] +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV]], 11 +; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT1:.*]], label %[[EXIT]] +; CHECK: [[EXIT1]]: +; CHECK-NEXT: [[ADD3_LCSSA:%.*]] = phi double [ [[ADD3]], %[[EXIT]] ] +; CHECK-NEXT: ret double [[ADD3_LCSSA]] +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %accum = phi double [ 0.000000e+00, %entry ], [ %add3, %loop ] + %gep1 = getelementptr [11 x float], ptr %p, i64 %iv + %gep2 = getelementptr i8, ptr %gep1, i64 12 + %ld1 = load float, ptr %gep1, align 4 + %ext1 = fpext float %ld1 to double + %add1 = fadd reassoc contract double %accum, %ext1 + %ld2 = load float, ptr %gep2, align 4 + %ext2 = fpext float %ld2 to double + %add2 = fadd reassoc contract double %add1, %ext2 + %ld3 = load float, ptr %gep1, align 4 + %ext3 = fpext float %ld3 to double + %add3 = fadd reassoc contract double %add2, %ext3 + %iv.next = add i64 %iv, 1 + %cmp = icmp eq i64 %iv, 11 + br i1 %cmp, label %exit, label %loop + +exit: + ret double %add3 +} + attributes #0 = { "target-features"="+sve2p1,+dotprod" } +attributes #1 = { "target-features"="+sve" } + !0 = distinct !{!0, !1} !1 = !{!"llvm.loop.interleave.count", i32 1} !2 = distinct !{!2, !3} diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll index 73ccad2731833..9c9956bb76689 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll @@ -10,22 +10,35 @@ define i64 @reduction(i64 %arg) #0 { ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1 -; CHECK-NEXT: [[TMP1]] = or i32 [[VEC_PHI]], 1 +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) +; CHECK-NEXT: [[TMP5]] = or <4 x i32> [[VEC_PHI]], splat (i32 1) +; CHECK-NEXT: [[TMP1]] = or <4 x i32> [[VEC_PHI2]], splat (i32 1) +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i64> [[STEP_ADD]], splat (i64 4) +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 +; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[BIN_RDX1:%.*]] = or <4 x i32> [[TMP1]], [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[BIN_RDX1]]) +; CHECK-NEXT: br label %[[SCALAR_PH:.*]] +; CHECK: [[SCALAR_PH]]: +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 96, %[[SCALAR_PH]] ], [ [[TMP3:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ [[TMP7]], %[[SCALAR_PH]] ], [ [[TMP2:%.*]], %[[LOOP]] ] ; CHECK-NEXT: [[TMP2]] = or i32 [[VEC_PHI1]], 1 -; CHECK-NEXT: [[TMP3:%.*]] = add nsw i64 [[TMP0]], 1 +; CHECK-NEXT: [[TMP3]] = add nsw i64 [[TMP0]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = mul nsw i64 [[TMP3]], [[ARG]] -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 -; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 -; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] -; CHECK: [[MIDDLE_BLOCK]]: -; CHECK-NEXT: [[BIN_RDX:%.*]] = or i32 [[TMP2]], [[TMP1]] -; CHECK-NEXT: br label %[[EXIT:.*]] +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i64 [[TMP3]], 100 +; CHECK-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK: [[EXIT]]: +; CHECK-NEXT: [[MUL_LCSSA:%.*]] = phi i64 [ [[TMP4]], %[[LOOP]] ] +; CHECK-NEXT: [[BIN_RDX:%.*]] = phi i32 [ [[TMP2]], %[[LOOP]] ] ; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[BIN_RDX]] to i64 -; CHECK-NEXT: [[RES:%.*]] = add i64 [[EXT]], [[TMP4]] +; CHECK-NEXT: [[RES:%.*]] = add i64 [[EXT]], [[MUL_LCSSA]] ; CHECK-NEXT: ret i64 [[RES]] ; entry: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll index e084307c0c2ae..70e771ff0f890 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll @@ -502,9 +502,9 @@ define float @fadd_predicated(ptr noalias nocapture %a, i64 %n) { ; CHECK-UNORDERED: %[[ICMP:.*]] = icmp ule <2 x i64> %vec.ind, %[[SPLAT]] ; CHECK-UNORDERED: pred.load.continue2 ; CHECK-UNORDERED: %[[FADD]] = fadd <2 x float> %[[RDX_PHI]], {{.*}} -; CHECK-UNORDERED: %[[MASK:.*]] = select <2 x i1> %[[ICMP]], <2 x float> %[[FADD]], <2 x float> %[[RDX_PHI]] ; CHECK-UNORDERED-NOT: call float @llvm.vector.reduce.fadd ; CHECK-UNORDERED: middle.block +; CHECK-UNORDERED: %[[MASK:.*]] = select <2 x i1> %[[ICMP]], <2 x float> %[[FADD]], <2 x float> %[[RDX_PHI]] ; CHECK-UNORDERED: %[[RDX:.*]] = call float @llvm.vector.reduce.fadd.v2f32(float -0.000000e+00, <2 x float> %[[MASK]]) ; CHECK-UNORDERED: for.end ; CHECK-UNORDERED: ret float %[[RDX]] diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll b/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll index fe910a668577a..9feaa4edad29c 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll @@ -638,46 +638,46 @@ for.end: ; Test for https://github.com/llvm/llvm-project/issues/159402. For invariant divisors, ; selects can be introduced outside the vector loop and their cost should not be ; considered for each loop iteration. -define i32 @udiv_sdiv_with_invariant_divisors(i8 %x, i16 %y, i1 %c) { +define void @udiv_sdiv_with_invariant_divisors(i8 %x, i16 %y, i1 %c, ptr %p) { ; CHECK-LABEL: @udiv_sdiv_with_invariant_divisors( ; CHECK-NEXT: entry: -; CHECK-NEXT: br label [[VECTOR_PH:%.*]] -; CHECK: vector.ph: -; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i1 [[C:%.*]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer -; CHECK-NEXT: [[TMP0:%.*]] = xor [[BROADCAST_SPLAT]], splat (i1 true) -; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement poison, i8 [[X:%.*]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector [[BROADCAST_SPLATINSERT1]], poison, zeroinitializer -; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement poison, i16 [[Y:%.*]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector [[BROADCAST_SPLATINSERT3]], poison, zeroinitializer -; CHECK-NEXT: [[TMP1:%.*]] = call @llvm.stepvector.nxv8i8() -; CHECK-NEXT: [[INDUCTION:%.*]] = add splat (i8 -12), [[TMP1]] ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i1 [[C:%.*]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; CHECK-NEXT: [[TMP0:%.*]] = xor [[BROADCAST_SPLAT]], splat (i1 true) +; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement poison, i8 [[X:%.*]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector [[BROADCAST_SPLATINSERT1]], poison, zeroinitializer +; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement poison, i16 [[Y:%.*]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector [[BROADCAST_SPLATINSERT3]], poison, zeroinitializer +; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement poison, ptr [[P:%.*]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector [[BROADCAST_SPLATINSERT5]], poison, zeroinitializer +; CHECK-NEXT: [[TMP1:%.*]] = call @llvm.stepvector.nxv4i8() +; CHECK-NEXT: [[INDUCTION:%.*]] = add splat (i8 -12), [[TMP1]] +; CHECK-NEXT: br label [[LOOP_LATCH:%.*]] ; CHECK: vector.body: -; CHECK-NEXT: [[VEC_IND:%.*]] = phi [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ 12, [[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 8, i1 true) -; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8 -; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement poison, i8 [[TMP4]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector [[BROADCAST_SPLATINSERT5]], poison, zeroinitializer -; CHECK-NEXT: [[TMP8:%.*]] = call @llvm.vp.merge.nxv8i8( [[TMP0]], [[BROADCAST_SPLAT2]], splat (i8 1), i32 [[TMP3]]) -; CHECK-NEXT: [[TMP9:%.*]] = udiv [[VEC_IND]], [[TMP8]] -; CHECK-NEXT: [[TMP10:%.*]] = zext [[TMP9]] to -; CHECK-NEXT: [[TMP11:%.*]] = call @llvm.vp.merge.nxv8i16( [[TMP0]], [[BROADCAST_SPLAT4]], splat (i16 1), i32 [[TMP3]]) -; CHECK-NEXT: [[TMP12:%.*]] = sdiv [[TMP10]], [[TMP11]] -; CHECK-NEXT: [[TMP13:%.*]] = sext [[TMP12]] to -; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], zeroinitializer, [[TMP13]] -; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP3]] -; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], [[BROADCAST_SPLAT6]] -; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[AVL_NEXT]], 0 -; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi [ [[INDUCTION]], [[VECTOR_BODY]] ], [ [[VEC_IND_NEXT:%.*]], [[LOOP_LATCH]] ] +; CHECK-NEXT: [[AVL:%.*]] = phi i32 [ 12, [[VECTOR_BODY]] ], [ [[AVL_NEXT:%.*]], [[LOOP_LATCH]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.experimental.get.vector.length.i32(i32 [[AVL]], i32 4, i1 true) +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i8 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement poison, i8 [[TMP3]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector [[BROADCAST_SPLATINSERT7]], poison, zeroinitializer +; CHECK-NEXT: [[TMP10:%.*]] = call @llvm.vp.merge.nxv4i8( [[TMP0]], [[BROADCAST_SPLAT2]], splat (i8 1), i32 [[TMP2]]) +; CHECK-NEXT: [[TMP5:%.*]] = udiv [[VEC_IND]], [[TMP10]] +; CHECK-NEXT: [[TMP6:%.*]] = zext [[TMP5]] to +; CHECK-NEXT: [[TMP7:%.*]] = call @llvm.vp.merge.nxv4i16( [[TMP0]], [[BROADCAST_SPLAT4]], splat (i16 1), i32 [[TMP2]]) +; CHECK-NEXT: [[TMP8:%.*]] = sdiv [[TMP6]], [[TMP7]] +; CHECK-NEXT: [[TMP9:%.*]] = sext [[TMP8]] to +; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], zeroinitializer, [[TMP9]] +; CHECK-NEXT: call void @llvm.vp.scatter.nxv4i32.nxv4p0( [[PREDPHI]], align 4 [[BROADCAST_SPLAT6]], splat (i1 true), i32 [[TMP2]]) +; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i32 [[AVL]], [[TMP2]] +; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], [[BROADCAST_SPLAT8]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[AVL_NEXT]], 0 +; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP_LATCH]], !llvm.loop [[LOOP11:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP3]] to i64 -; CHECK-NEXT: [[TMP17:%.*]] = sub i64 [[TMP16]], 1 -; CHECK-NEXT: [[MERGE_LCSSA:%.*]] = extractelement [[PREDPHI]], i64 [[TMP17]] -; CHECK-NEXT: br label [[LOOP_LATCH:%.*]] +; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: -; CHECK-NEXT: ret i32 [[MERGE_LCSSA]] +; CHECK-NEXT: ret void ; ; FIXED-LABEL: @udiv_sdiv_with_invariant_divisors( ; FIXED-NEXT: entry: @@ -693,20 +693,21 @@ define i32 @udiv_sdiv_with_invariant_divisors(i8 %x, i16 %y, i1 %c) { ; FIXED: vector.body: ; FIXED-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; FIXED-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] -; FIXED-NEXT: [[TMP2:%.*]] = udiv <4 x i8> [[VEC_IND]], [[TMP0]] -; FIXED-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16> -; FIXED-NEXT: [[TMP4:%.*]] = sdiv <4 x i16> [[TMP3]], [[TMP1]] -; FIXED-NEXT: [[TMP5:%.*]] = sext <4 x i16> [[TMP4]] to <4 x i32> -; FIXED-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], <4 x i32> zeroinitializer, <4 x i32> [[TMP5]] +; FIXED-NEXT: [[TMP3:%.*]] = udiv <4 x i8> [[VEC_IND]], [[TMP0]] +; FIXED-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[TMP3]] to <4 x i16> +; FIXED-NEXT: [[TMP5:%.*]] = sdiv <4 x i16> [[TMP4]], [[TMP1]] +; FIXED-NEXT: [[TMP6:%.*]] = sext <4 x i16> [[TMP5]] to <4 x i32> +; FIXED-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], <4 x i32> zeroinitializer, <4 x i32> [[TMP6]] +; FIXED-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3 +; FIXED-NEXT: store i32 [[TMP7]], ptr [[P:%.*]], align 4 ; FIXED-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; FIXED-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4) -; FIXED-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12 -; FIXED-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] +; FIXED-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 12 +; FIXED-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] ; FIXED: middle.block: -; FIXED-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3 -; FIXED-NEXT: br label [[LOOP_LATCH:%.*]] +; FIXED-NEXT: br label [[EXIT:%.*]] ; FIXED: exit: -; FIXED-NEXT: ret i32 [[TMP7]] +; FIXED-NEXT: ret void ; entry: br label %loop.header @@ -725,11 +726,12 @@ then: loop.latch: %merge = phi i32 [ 0, %loop.header ], [ %sd.ext, %then ] + store i32 %merge, ptr %p, align 4 %iv.next = add nsw i16 %iv, 1 %ec = icmp eq i16 %iv.next, 0 %iv.next.trunc = trunc i16 %iv.next to i8 br i1 %ec, label %exit, label %loop.header exit: - ret i32 %merge + ret void } diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll index 028f6a45fbaf4..786ef735fc7ad 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll @@ -103,8 +103,6 @@ define i1 @scalarize_ptr_induction(ptr %start, ptr %end, ptr noalias %dst, i1 %c ; CHECK-NEXT: [[TMP20:%.*]] = mul [[TMP19]], splat (i64 -7070675565921424023) ; CHECK-NEXT: [[TMP21:%.*]] = add [[TMP20]], splat (i64 -4) ; CHECK-NEXT: call void @llvm.vp.scatter.nxv2i64.nxv2p0( [[TMP21]], align 1 [[BROADCAST_SPLAT]], splat (i1 true), i32 [[TMP11]]), !alias.scope [[META6:![0-9]+]], !noalias [[META3]] -; CHECK-NEXT: [[TMP16:%.*]] = getelementptr nusw i8, [[VECTOR_GEP]], i64 12 -; CHECK-NEXT: [[TMP17:%.*]] = icmp eq [[TMP16]], [[BROADCAST_SPLAT7]] ; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP11]] to i64 ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP26]] ; CHECK-NEXT: [[TMP27:%.*]] = mul i64 12, [[TMP26]] @@ -112,6 +110,8 @@ define i1 @scalarize_ptr_induction(ptr %start, ptr %end, ptr noalias %dst, i1 %c ; CHECK-NEXT: [[TMP28:%.*]] = icmp eq i64 [[AVL_NEXT]], 0 ; CHECK-NEXT: br i1 [[TMP28]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP30:%.*]] = getelementptr nusw i8, [[VECTOR_GEP]], i64 12 +; CHECK-NEXT: [[TMP17:%.*]] = icmp eq [[TMP30]], [[BROADCAST_SPLAT7]] ; CHECK-NEXT: [[TMP29:%.*]] = sub i64 [[TMP26]], 1 ; CHECK-NEXT: [[TMP25:%.*]] = extractelement [[TMP17]], i64 [[TMP29]] ; CHECK-NEXT: br label %[[EXIT:.*]] diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll b/llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll index 7495a215d020a..19a2424a9ee7f 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/pr87378-vpinstruction-or-drop-poison-generating-flags.ll @@ -37,9 +37,7 @@ define void @pr87378_vpinstruction_or_drop_poison_generating_flags(ptr %arg, i64 ; CHECK-NEXT: [[TMP20:%.*]] = xor [[TMP14]], splat (i1 true) ; CHECK-NEXT: [[TMP21:%.*]] = select [[TMP13]], [[TMP20]], zeroinitializer ; CHECK-NEXT: [[TMP22:%.*]] = or [[TMP19]], [[TMP21]] -; CHECK-NEXT: [[TMP23:%.*]] = extractelement [[TMP21]], i32 0 -; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP23]], i64 poison, i64 [[INDEX]] -; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i16, ptr [[ARG]], i64 [[PREDPHI]] +; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i16, ptr [[ARG]], i64 [[INDEX]] ; CHECK-NEXT: call void @llvm.vp.store.nxv8i16.p0( zeroinitializer, ptr align 2 [[TMP24]], [[TMP22]], i32 [[TMP25]]) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP8]], [[INDEX]] ; CHECK-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP8]] @@ -71,7 +69,7 @@ then.2: br label %merge merge: - %idx = phi i64 [ poison, %then.1 ], [ %iv, %then.2 ] + %idx = phi i64 [ %iv, %then.1 ], [ %iv, %then.2 ] %getelementptr = getelementptr i16, ptr %arg, i64 %idx store i16 0, ptr %getelementptr, align 2 br label %loop.latch diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/sink-to-early-exit.ll b/llvm/test/Transforms/LoopVectorize/RISCV/sink-to-early-exit.ll index 3b413ac60c73a..986c907153c98 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/sink-to-early-exit.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/sink-to-early-exit.ll @@ -35,7 +35,6 @@ define i64 @sink_to_early_exit(i64 %offset) { ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP5]], align 1 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX4]] ; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load , ptr [[TMP6]], align 1 -; CHECK-NEXT: [[TMP7:%.*]] = add [[VEC_IND]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP8:%.*]] = icmp ne [[WIDE_LOAD]], [[WIDE_LOAD5]] ; CHECK-NEXT: [[INDEX_NEXT6]] = add nuw i64 [[INDEX4]], [[TMP3]] ; CHECK-NEXT: [[TMP9:%.*]] = freeze [[TMP8]] @@ -49,6 +48,7 @@ define i64 @sink_to_early_exit(i64 %offset) { ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[LOOP_END:.*]], label %[[SCALAR_PH]] ; CHECK: [[VECTOR_EARLY_EXIT]]: +; CHECK-NEXT: [[TMP7:%.*]] = add [[VEC_IND]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[FIRST_ACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.nxv16i1( [[TMP8]], i1 false) ; CHECK-NEXT: [[TMP12:%.*]] = extractelement [[TMP7]], i64 [[FIRST_ACTIVE_LANE]] ; CHECK-NEXT: br label %[[LOOP_EARLY_EXIT:.*]] diff --git a/llvm/test/Transforms/LoopVectorize/SystemZ/load-store-scalarization-cost.ll b/llvm/test/Transforms/LoopVectorize/SystemZ/load-store-scalarization-cost.ll index e24c5a1a2bf2d..0dfc6f5436b29 100644 --- a/llvm/test/Transforms/LoopVectorize/SystemZ/load-store-scalarization-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/SystemZ/load-store-scalarization-cost.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts ; RUN: opt -mtriple=s390x-unknown-linux -mcpu=z13 -passes=loop-vectorize \ -; RUN: -force-vector-width=4 -debug-only=loop-vectorize \ +; RUN: -debug-only=loop-vectorize \ ; RUN: -disable-output -enable-interleaved-mem-accesses=false < %s 2>&1 | \ ; RUN: FileCheck %s ; @@ -8,6 +8,12 @@ ; extracts, since z13 supports element load/store. define void @fun(ptr %data, i64 %n) { +; CHECK-LABEL: LV: Checking a loop in 'fun' +; CHECK: LV: Scalarizing: %tmp1 = load i32, ptr %tmp0, align 4 +; CHECK: LV: Scalarizing: store i32 %tmp2, ptr %tmp0, align 4 + +; CHECK: Cost of 4 for VF 4: REPLICATE ir<%tmp1> = load ir<%tmp0> +; CHECK: Cost of 4 for VF 4: REPLICATE store ir<%tmp2>, ir<%tmp0> entry: br label %for.body @@ -23,10 +29,44 @@ for.body: for.end: ret void +} -; CHECK: LV: Scalarizing: %tmp1 = load i32, ptr %tmp0, align 4 -; CHECK: LV: Scalarizing: store i32 %tmp2, ptr %tmp0, align 4 +define void @predicated_store(ptr noalias %dst, ptr %src.float, ptr %src.i32.0, ptr %src.i32.1, i64 %n) #0 { +; CHECK-LABEL: LV: Checking a loop in 'predicated_store' +; CHECK: Cost of 0 for VF 2: REPLICATE ir<%load.0> = load ir<%gep.0> +; CHECK: Cost of 0 for VF 2: REPLICATE store ir<0>, ir<%dst> +; CHECK: Cost of 0 for VF 4: REPLICATE ir<%load.0> = load ir<%gep.0> +; CHECK: Cost of 0 for VF 4: REPLICATE store ir<0>, ir<%dst> +; +entry: + br label %loop -; CHECK: Cost of 4 for VF 4: REPLICATE ir<%tmp1> = load ir<%tmp0> -; CHECK: Cost of 4 for VF 4: REPLICATE store ir<%tmp2>, ir<%tmp0> +loop: + %iv = phi i64 [ %iv.next, %loop.latch ], [ 0, %entry ] + %gep.0 = getelementptr i32, ptr %src.i32.0, i64 %iv + %load.0 = load i32, ptr %gep.0, align 4 + %gep.1 = getelementptr i32, ptr %src.i32.1, i64 %iv + %ext = sext i32 %load.0 to i64 + %mul = mul i64 %n, %ext + %gep.float = getelementptr float, ptr %src.float, i64 %mul + %load.float = load float, ptr %gep.float, align 4 + %fcmp = fcmp ogt float %load.float, 0.000000e+00 + %load.1 = load i32, ptr %gep.1, align 4 + %icmp = icmp sgt i32 %load.1, 0 + %cond = and i1 %fcmp, %icmp + br i1 %cond, label %if.then, label %loop.latch + +if.then: + store i32 0, ptr %dst, align 4 + br label %loop.latch + +loop.latch: + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond = icmp eq i64 %iv.next, %n + br i1 %exitcond, label %exit, label %loop + +exit: + ret void } + +attributes #0 = { "target-cpu" = "z16" } diff --git a/llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll b/llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll index 651e2ad5e74da..2f78e72e106d6 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll @@ -325,13 +325,13 @@ define i64 @avx512_cond_load_cost(ptr %src, i32 %a, i64 %b, i32 %c, i32 %d) #1 { ; CHECK-NEXT: [[TMP68:%.*]] = sext <8 x i32> [[TMP67]] to <8 x i64> ; CHECK-NEXT: [[TMP69:%.*]] = getelementptr { i64, i64, i64 }, ptr [[SRC:%.*]], <8 x i64> [[TMP68]], i32 2 ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> align 8 [[TMP69]], <8 x i1> [[TMP1]], <8 x i64> poison) -; CHECK-NEXT: [[TMP70:%.*]] = or <8 x i64> [[WIDE_MASKED_GATHER]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP1]], <8 x i64> [[TMP70]], <8 x i64> zeroinitializer ; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 8 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i32> [[VEC_IND]], splat (i32 8) ; CHECK-NEXT: [[TMP71:%.*]] = icmp eq i32 [[IV_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP71]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP73:%.*]] = or <8 x i64> [[WIDE_MASKED_GATHER]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP1]], <8 x i64> [[TMP73]], <8 x i64> zeroinitializer ; CHECK-NEXT: [[TMP72:%.*]] = extractelement <8 x i64> [[PREDPHI]], i32 7 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP63]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] @@ -697,7 +697,7 @@ define i32 @cost_ashr_with_op_known_invariant_via_scev(i8 %a) { ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <32 x i1> poison, i1 [[CMP_I]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <32 x i1> [[BROADCAST_SPLATINSERT]], <32 x i1> poison, <32 x i32> zeroinitializer ; CHECK-NEXT: [[TMP60:%.*]] = xor <32 x i1> [[BROADCAST_SPLAT]], splat (i1 true) -; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] +; CHECK-NEXT: br label [[LOOP_HEADER1:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_UREM_CONTINUE62:%.*]] ] ; CHECK-NEXT: [[TMP61:%.*]] = extractelement <32 x i1> [[TMP60]], i32 0 @@ -860,23 +860,23 @@ define i32 @cost_ashr_with_op_known_invariant_via_scev(i8 %a) { ; CHECK: pred.urem.if61: ; CHECK-NEXT: br label [[PRED_UREM_CONTINUE62]] ; CHECK: pred.urem.continue62: -; CHECK-NEXT: [[TMP33:%.*]] = select <32 x i1> [[TMP60]], <32 x i1> poison, <32 x i1> zeroinitializer -; CHECK-NEXT: [[TMP34:%.*]] = or <32 x i1> [[TMP33]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[CMP_I]], <32 x i32> zeroinitializer, <32 x i32> poison -; CHECK-NEXT: [[TMP35:%.*]] = extractelement <32 x i32> [[PREDPHI]], i32 0 -; CHECK-NEXT: [[TMP36:%.*]] = ashr i32 [[CONV5_I]], [[TMP35]] -; CHECK-NEXT: [[BROADCAST_SPLATINSERT63:%.*]] = insertelement <32 x i32> poison, i32 [[TMP36]], i64 0 +; CHECK-NEXT: [[TMP33:%.*]] = extractelement <32 x i32> [[PREDPHI]], i32 0 +; CHECK-NEXT: [[TMP34:%.*]] = ashr i32 [[CONV5_I]], [[TMP33]] +; CHECK-NEXT: [[BROADCAST_SPLATINSERT63:%.*]] = insertelement <32 x i32> poison, i32 [[TMP34]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT64:%.*]] = shufflevector <32 x i32> [[BROADCAST_SPLATINSERT63]], <32 x i32> poison, <32 x i32> zeroinitializer -; CHECK-NEXT: [[TMP37:%.*]] = icmp eq <32 x i32> [[BROADCAST_SPLAT64]], zeroinitializer -; CHECK-NEXT: [[TMP38:%.*]] = shl <32 x i32> [[PREDPHI]], splat (i32 24) -; CHECK-NEXT: [[TMP39:%.*]] = ashr exact <32 x i32> [[TMP38]], splat (i32 24) -; CHECK-NEXT: [[TMP40:%.*]] = extractelement <32 x i1> [[TMP37]], i32 0 -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], <32 x i32> [[TMP39]], <32 x i32> zeroinitializer -; CHECK-NEXT: [[PREDPHI65:%.*]] = select <32 x i1> [[TMP34]], <32 x i32> [[TMP41]], <32 x i32> zeroinitializer ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 32 -; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i32 [[INDEX_NEXT]], 96 -; CHECK-NEXT: br i1 [[TMP42]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP10:![0-9]+]] +; CHECK-NEXT: [[TMP35:%.*]] = icmp eq i32 [[INDEX_NEXT]], 96 +; CHECK-NEXT: br i1 [[TMP35]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP_HEADER1]], !llvm.loop [[LOOP10:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP36:%.*]] = select <32 x i1> [[TMP60]], <32 x i1> poison, <32 x i1> zeroinitializer +; CHECK-NEXT: [[TMP37:%.*]] = or <32 x i1> [[TMP36]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP38:%.*]] = icmp eq <32 x i32> [[BROADCAST_SPLAT64]], zeroinitializer +; CHECK-NEXT: [[TMP39:%.*]] = shl <32 x i32> [[PREDPHI]], splat (i32 24) +; CHECK-NEXT: [[TMP40:%.*]] = ashr exact <32 x i32> [[TMP39]], splat (i32 24) +; CHECK-NEXT: [[TMP41:%.*]] = extractelement <32 x i1> [[TMP38]], i32 0 +; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], <32 x i32> [[TMP40]], <32 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI65:%.*]] = select <32 x i1> [[TMP37]], <32 x i32> [[TMP42]], <32 x i32> zeroinitializer ; CHECK-NEXT: [[TMP43:%.*]] = extractelement <32 x i32> [[PREDPHI65]], i32 31 ; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] ; CHECK: vec.epilog.iter.check: @@ -888,7 +888,7 @@ define i32 @cost_ashr_with_op_known_invariant_via_scev(i8 %a) { ; CHECK-NEXT: [[TMP44:%.*]] = xor <4 x i1> [[BROADCAST_SPLAT67]], splat (i1 true) ; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] ; CHECK: vec.epilog.vector.body: -; CHECK-NEXT: [[INDEX68:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT81:%.*]], [[PRED_UREM_CONTINUE76:%.*]] ] +; CHECK-NEXT: [[INDEX68:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT78:%.*]], [[PRED_UREM_CONTINUE76:%.*]] ] ; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i1> [[TMP44]], i32 0 ; CHECK-NEXT: br i1 [[TMP45]], label [[PRED_UREM_IF69:%.*]], label [[PRED_UREM_CONTINUE70:%.*]] ; CHECK: pred.urem.if69: @@ -909,33 +909,33 @@ define i32 @cost_ashr_with_op_known_invariant_via_scev(i8 %a) { ; CHECK: pred.urem.if75: ; CHECK-NEXT: br label [[PRED_UREM_CONTINUE76]] ; CHECK: pred.urem.continue76: -; CHECK-NEXT: [[TMP49:%.*]] = select <4 x i1> [[TMP44]], <4 x i1> poison, <4 x i1> zeroinitializer -; CHECK-NEXT: [[TMP50:%.*]] = or <4 x i1> [[TMP49]], [[BROADCAST_SPLAT67]] ; CHECK-NEXT: [[PREDPHI77:%.*]] = select i1 [[CMP_I]], <4 x i32> zeroinitializer, <4 x i32> poison -; CHECK-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[PREDPHI77]], i32 0 -; CHECK-NEXT: [[TMP52:%.*]] = ashr i32 [[CONV5_I]], [[TMP51]] -; CHECK-NEXT: [[BROADCAST_SPLATINSERT78:%.*]] = insertelement <4 x i32> poison, i32 [[TMP52]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT79:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT78]], <4 x i32> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP53:%.*]] = icmp eq <4 x i32> [[BROADCAST_SPLAT79]], zeroinitializer -; CHECK-NEXT: [[TMP54:%.*]] = shl <4 x i32> [[PREDPHI77]], splat (i32 24) -; CHECK-NEXT: [[TMP55:%.*]] = ashr exact <4 x i32> [[TMP54]], splat (i32 24) -; CHECK-NEXT: [[TMP56:%.*]] = extractelement <4 x i1> [[TMP53]], i32 0 -; CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], <4 x i32> [[TMP55]], <4 x i32> zeroinitializer -; CHECK-NEXT: [[PREDPHI80:%.*]] = select <4 x i1> [[TMP50]], <4 x i32> [[TMP57]], <4 x i32> zeroinitializer -; CHECK-NEXT: [[INDEX_NEXT81]] = add nuw i32 [[INDEX68]], 4 -; CHECK-NEXT: [[TMP58:%.*]] = icmp eq i32 [[INDEX_NEXT81]], 100 -; CHECK-NEXT: br i1 [[TMP58]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] +; CHECK-NEXT: [[TMP49:%.*]] = extractelement <4 x i32> [[PREDPHI77]], i32 0 +; CHECK-NEXT: [[TMP50:%.*]] = ashr i32 [[CONV5_I]], [[TMP49]] +; CHECK-NEXT: [[BROADCAST_SPLATINSERT79:%.*]] = insertelement <4 x i32> poison, i32 [[TMP50]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT80:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT79]], <4 x i32> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[INDEX_NEXT78]] = add nuw i32 [[INDEX68]], 4 +; CHECK-NEXT: [[TMP51:%.*]] = icmp eq i32 [[INDEX_NEXT78]], 100 +; CHECK-NEXT: br i1 [[TMP51]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] ; CHECK: vec.epilog.middle.block: -; CHECK-NEXT: [[TMP59:%.*]] = extractelement <4 x i32> [[PREDPHI80]], i32 3 +; CHECK-NEXT: [[TMP52:%.*]] = select <4 x i1> [[TMP44]], <4 x i1> poison, <4 x i1> zeroinitializer +; CHECK-NEXT: [[TMP53:%.*]] = or <4 x i1> [[TMP52]], [[BROADCAST_SPLAT67]] +; CHECK-NEXT: [[TMP54:%.*]] = icmp eq <4 x i32> [[BROADCAST_SPLAT80]], zeroinitializer +; CHECK-NEXT: [[TMP55:%.*]] = shl <4 x i32> [[PREDPHI77]], splat (i32 24) +; CHECK-NEXT: [[TMP56:%.*]] = ashr exact <4 x i32> [[TMP55]], splat (i32 24) +; CHECK-NEXT: [[TMP57:%.*]] = extractelement <4 x i1> [[TMP54]], i32 0 +; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], <4 x i32> [[TMP56]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[PREDPHI81:%.*]] = select <4 x i1> [[TMP53]], <4 x i32> [[TMP58]], <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP59:%.*]] = extractelement <4 x i32> [[PREDPHI81]], i32 3 ; CHECK-NEXT: br i1 true, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] ; CHECK: vec.epilog.scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ 0, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 4, [[VEC_EPILOG_ITER_CHECK]] ], [ 100, [[ITER_CHECK:%.*]] ] -; CHECK-NEXT: br label [[LOOP_HEADER1:%.*]] +; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] ; CHECK: loop.header: ; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] ; CHECK-NEXT: br i1 [[CMP_I]], label [[THEN:%.*]], label [[ELSE:%.*]] ; CHECK: then: -; CHECK-NEXT: [[P_1:%.*]] = phi i32 [ [[REM_I:%.*]], [[ELSE]] ], [ 0, [[LOOP_HEADER1]] ] +; CHECK-NEXT: [[P_1:%.*]] = phi i32 [ [[REM_I:%.*]], [[ELSE]] ], [ 0, [[LOOP_HEADER]] ] ; CHECK-NEXT: [[SHR_I:%.*]] = ashr i32 [[CONV5_I]], [[P_1]] ; CHECK-NEXT: [[TOBOOL6_NOT_I:%.*]] = icmp eq i32 [[SHR_I]], 0 ; CHECK-NEXT: [[SEXT_I:%.*]] = shl i32 [[P_1]], 24 @@ -950,7 +950,7 @@ define i32 @cost_ashr_with_op_known_invariant_via_scev(i8 %a) { ; CHECK-NEXT: [[P_2:%.*]] = phi i32 [ 0, [[ELSE]] ], [ [[TMP1]], [[THEN]] ] ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], -1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i8 [[IV_NEXT]], 0 -; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER1]], !llvm.loop [[LOOP13:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP13:![0-9]+]] ; CHECK: exit: ; CHECK-NEXT: [[P_2_LCSSA:%.*]] = phi i32 [ [[P_2]], [[LOOP_LATCH]] ], [ [[TMP43]], [[MIDDLE_BLOCK]] ], [ [[TMP59]], [[VEC_EPILOG_MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i32 [[P_2_LCSSA]] @@ -1432,13 +1432,13 @@ define i64 @test_predicated_udiv(i32 %d, i1 %c) #2 { ; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE62]] ; CHECK: pred.udiv.continue62: ; CHECK-NEXT: [[TMP161:%.*]] = phi <32 x i32> [ [[TMP156]], [[PRED_UDIV_CONTINUE60]] ], [ [[TMP160]], [[PRED_UDIV_IF61]] ] -; CHECK-NEXT: [[TMP162:%.*]] = zext <32 x i32> [[TMP161]] to <32 x i64> -; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], <32 x i64> zeroinitializer, <32 x i64> [[TMP162]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 32 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <32 x i32> [[VEC_IND]], splat (i32 32) ; CHECK-NEXT: [[TMP163:%.*]] = icmp eq i32 [[INDEX_NEXT]], 992 ; CHECK-NEXT: br i1 [[TMP163]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP207:%.*]] = zext <32 x i32> [[TMP161]] to <32 x i64> +; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], <32 x i64> zeroinitializer, <32 x i64> [[TMP207]] ; CHECK-NEXT: [[TMP164:%.*]] = extractelement <32 x i64> [[PREDPHI]], i32 31 ; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] ; CHECK: vec.epilog.iter.check: @@ -1528,13 +1528,13 @@ define i64 @test_predicated_udiv(i32 %d, i1 %c) #2 { ; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE84]] ; CHECK: pred.udiv.continue84: ; CHECK-NEXT: [[TMP206:%.*]] = phi <8 x i32> [ [[TMP201]], [[PRED_UDIV_CONTINUE82]] ], [ [[TMP205]], [[PRED_UDIV_IF83]] ] -; CHECK-NEXT: [[TMP207:%.*]] = zext <8 x i32> [[TMP206]] to <8 x i64> -; CHECK-NEXT: [[PREDPHI85:%.*]] = select i1 [[C]], <8 x i64> zeroinitializer, <8 x i64> [[TMP207]] ; CHECK-NEXT: [[INDEX_NEXT86]] = add nuw i32 [[INDEX67]], 8 ; CHECK-NEXT: [[VEC_IND_NEXT87]] = add <8 x i32> [[VEC_IND68]], splat (i32 8) ; CHECK-NEXT: [[TMP208:%.*]] = icmp eq i32 [[INDEX_NEXT86]], 1000 ; CHECK-NEXT: br i1 [[TMP208]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]] ; CHECK: vec.epilog.middle.block: +; CHECK-NEXT: [[TMP210:%.*]] = zext <8 x i32> [[TMP206]] to <8 x i64> +; CHECK-NEXT: [[PREDPHI85:%.*]] = select i1 [[C]], <8 x i64> zeroinitializer, <8 x i64> [[TMP210]] ; CHECK-NEXT: [[TMP209:%.*]] = extractelement <8 x i64> [[PREDPHI85]], i32 7 ; CHECK-NEXT: br i1 false, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] ; CHECK: vec.epilog.scalar.ph: diff --git a/llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll b/llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll index d19ae728cc913..1f33d63d2073c 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll @@ -32,12 +32,12 @@ define i1 @fn(ptr %nno) #0 { ; CHECK-NEXT: [[TMP8:%.*]] = urem <4 x i32> [[TMP7]], splat (i32 10) ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP8]], <4 x i32> [[REVERSE1]] ; CHECK-NEXT: [[TMP11]] = or <4 x i32> [[PREDPHI]], [[VEC_PHI]] -; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP11]], <4 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i64> [[VEC_IND]], splat (i64 -4) ; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12 ; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP12:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP11]], <4 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP12]]) ; CHECK-NEXT: br label [[FOR_INC35:%.*]] ; CHECK: exit: diff --git a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll index 009d386f52c77..1272cdd7eb71c 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll @@ -402,16 +402,16 @@ define i16 @iv_and_step_trunc() { ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <16 x i64> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <16 x i16> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = add <16 x i64> [[VEC_IND]], splat (i64 1) -; CHECK-NEXT: [[TMP1:%.*]] = trunc <16 x i64> [[TMP0]] to <16 x i16> -; CHECK-NEXT: [[TMP2:%.*]] = mul <16 x i16> [[VEC_IND1]], [[TMP1]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <16 x i64> [[VEC_IND]], splat (i64 16) ; CHECK-NEXT: [[VEC_IND_NEXT2]] = add <16 x i16> [[VEC_IND1]], splat (i16 16) -; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 -; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 +; CHECK-NEXT: br i1 [[TMP0]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <16 x i16> [[TMP2]], i32 15 +; CHECK-NEXT: [[TMP1:%.*]] = add <16 x i64> [[VEC_IND]], splat (i64 1) +; CHECK-NEXT: [[TMP2:%.*]] = trunc <16 x i64> [[TMP1]] to <16 x i16> +; CHECK-NEXT: [[TMP3:%.*]] = mul <16 x i16> [[VEC_IND1]], [[TMP2]] +; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <16 x i16> [[TMP3]], i32 15 ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: scalar.ph: ; CHECK-NEXT: br label [[LOOP1:%.*]] diff --git a/llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll b/llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll index 7e5964ac30cba..faf90a79c8354 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll @@ -37,12 +37,12 @@ define i32 @inv_load_conditional(ptr %a, i64 %n, ptr %b, i32 %k) { ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] ; CHECK-NEXT: store <16 x i32> [[BROADCAST_SPLAT5]], ptr [[TMP2]], align 4, !alias.scope [[META0:![0-9]+]], !noalias [[META3:![0-9]+]] ; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> align 4 [[BROADCAST_SPLAT]], <16 x i1> [[TMP1]], <16 x i32> poison), !alias.scope [[META3]] -; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x i1> [[TMP1]], i32 0 -; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP9]], <16 x i32> [[WIDE_MASKED_GATHER]], <16 x i32> splat (i32 1) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x i1> [[TMP1]], i32 0 +; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP10]], <16 x i32> [[WIDE_MASKED_GATHER]], <16 x i32> splat (i32 1) ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <16 x i32> [[PREDPHI]], i32 15 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX2]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] @@ -64,12 +64,12 @@ define i32 @inv_load_conditional(ptr %a, i64 %n, ptr %b, i32 %k) { ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX10]] ; CHECK-NEXT: store <8 x i32> [[BROADCAST_SPLAT12]], ptr [[TMP6]], align 4, !alias.scope [[META0]], !noalias [[META3]] ; CHECK-NEXT: [[WIDE_MASKED_GATHER13:%.*]] = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> align 4 [[BROADCAST_SPLAT9]], <8 x i1> [[TMP5]], <8 x i32> poison), !alias.scope [[META3]] -; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i1> [[TMP5]], i32 0 -; CHECK-NEXT: [[PREDPHI14:%.*]] = select i1 [[TMP10]], <8 x i32> [[WIDE_MASKED_GATHER13]], <8 x i32> splat (i32 1) ; CHECK-NEXT: [[INDEX_NEXT15]] = add nuw i64 [[INDEX10]], 8 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT15]], [[N_VEC7]] ; CHECK-NEXT: br i1 [[TMP7]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] ; CHECK: vec.epilog.middle.block: +; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x i1> [[TMP5]], i32 0 +; CHECK-NEXT: [[PREDPHI14:%.*]] = select i1 [[TMP9]], <8 x i32> [[WIDE_MASKED_GATHER13]], <8 x i32> splat (i32 1) ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i32> [[PREDPHI14]], i32 7 ; CHECK-NEXT: [[CMP_N16:%.*]] = icmp eq i64 [[SMAX2]], [[N_VEC7]] ; CHECK-NEXT: br i1 [[CMP_N16]], label [[FOR_END]], label [[VEC_EPILOG_SCALAR_PH]] diff --git a/llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll index fb28de674110d..1026177370912 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll @@ -119,12 +119,12 @@ define i1 @test_exit_compare_other_users() #0 { ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i64 -24 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP2]], i64 -7 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP3]], align 1 -; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <8 x i8> [[WIDE_LOAD]], <8 x i8> poison, <8 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <8 x i8> [[REVERSE]], splat (i8 32) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64 ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <8 x i8> [[WIDE_LOAD]], <8 x i8> poison, <8 x i32> +; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <8 x i8> [[REVERSE]], splat (i8 32) ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i1> [[TMP4]], i32 7 ; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] ; CHECK: [[VEC_EPILOG_ITER_CHECK]]: @@ -139,12 +139,12 @@ define i1 @test_exit_compare_other_users() #0 { ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP7]], i64 0 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP8]], i64 -3 ; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i8>, ptr [[TMP9]], align 1 -; CHECK-NEXT: [[REVERSE3:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD2]], <4 x i8> poison, <4 x i32> -; CHECK-NEXT: [[TMP10:%.*]] = icmp eq <4 x i8> [[REVERSE3]], splat (i8 32) ; CHECK-NEXT: [[INDEX_NEXT4]] = add nuw i64 [[INDEX1]], 4 ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT4]], 76 ; CHECK-NEXT: br i1 [[TMP11]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] ; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: +; CHECK-NEXT: [[REVERSE4:%.*]] = shufflevector <4 x i8> [[WIDE_LOAD2]], <4 x i8> poison, <4 x i32> +; CHECK-NEXT: [[TMP10:%.*]] = icmp eq <4 x i8> [[REVERSE4]], splat (i8 32) ; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[TMP10]], i32 3 ; CHECK-NEXT: br i1 false, label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] ; CHECK: [[VEC_EPILOG_SCALAR_PH]]: diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll b/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll index 57cbe7f4c241b..2e56ef4975761 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/pr141968-instsimplifyfolder.ll @@ -3,28 +3,28 @@ target triple = "x86_64" -define i8 @pr141968(i1 %cond, i8 %v) { -; CHECK-LABEL: define i8 @pr141968( -; CHECK-SAME: i1 [[COND:%.*]], i8 [[V:%.*]]) { +define void @pr141968(i1 %cond, i8 %v, ptr %p) { +; CHECK-LABEL: define void @pr141968( +; CHECK-SAME: i1 [[COND:%.*]], i8 [[V:%.*]], ptr [[P:%.*]]) { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: [[ZEXT_TRUE:%.*]] = zext i1 true to i16 ; CHECK-NEXT: [[SEXT:%.*]] = sext i8 [[V]] to i16 -; CHECK-NEXT: br label %[[VECTOR_PH:.*]] -; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] +; CHECK: [[LOOP_HEADER]]: ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i1> poison, i1 [[COND]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i1> [[BROADCAST_SPLATINSERT]], <16 x i1> poison, <16 x i32> zeroinitializer ; CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i1> [[BROADCAST_SPLAT]], splat (i1 true) -; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] -; CHECK: [[VECTOR_BODY]]: -; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE30:.*]] ] +; CHECK-NEXT: br label %[[COND_FALSE:.*]] +; CHECK: [[COND_FALSE]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[LOOP_HEADER]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE30:.*]] ] ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <16 x i1> [[TMP0]], i32 0 -; CHECK-NEXT: br i1 [[TMP1]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]] +; CHECK-NEXT: br i1 [[TMP1]], label %[[PRED_SDIV_IF:.*]], label %[[LOOP_LATCH:.*]] ; CHECK: [[PRED_SDIV_IF]]: -; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE]] -; CHECK: [[PRED_SDIV_CONTINUE]]: +; CHECK-NEXT: br label %[[LOOP_LATCH]] +; CHECK: [[LOOP_LATCH]]: ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i1> [[TMP0]], i32 1 -; CHECK-NEXT: br i1 [[TMP2]], label %[[PRED_SDIV_IF1:.*]], label %[[PRED_SDIV_CONTINUE2:.*]] -; CHECK: [[PRED_SDIV_IF1]]: +; CHECK-NEXT: br i1 [[TMP2]], label %[[EXIT:.*]], label %[[PRED_SDIV_CONTINUE2:.*]] +; CHECK: [[EXIT]]: ; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE2]] ; CHECK: [[PRED_SDIV_CONTINUE2]]: ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <16 x i1> [[TMP0]], i32 2 @@ -98,13 +98,14 @@ define i8 @pr141968(i1 %cond, i8 %v) { ; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE30]] ; CHECK: [[PRED_SDIV_CONTINUE30]]: ; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[COND]], i8 0, i8 [[V]] +; CHECK-NEXT: store i8 [[PREDPHI]], ptr [[P]], align 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16 ; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], 256 -; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[COND_FALSE]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: -; CHECK-NEXT: br label %[[EXIT:.*]] -; CHECK: [[EXIT]]: -; CHECK-NEXT: ret i8 [[PREDPHI]] +; CHECK-NEXT: br label %[[EXIT1:.*]] +; CHECK: [[EXIT1]]: +; CHECK-NEXT: ret void ; entry: %zext.true = zext i1 true to i16 @@ -122,10 +123,11 @@ cond.false: ; preds = %loop.header loop.latch: ; preds = %cond.false, %loop.header %ret = phi i8 [ %sdiv.trunc, %cond.false ], [ 0, %loop.header ] + store i8 %ret, ptr %p, align 1 %iv.next = add i8 %iv, 1 %exitcond = icmp eq i8 %iv.next, 0 br i1 %exitcond, label %exit, label %loop.header exit: ; preds = %loop.latch - ret i8 %ret + ret void } diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll b/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll index 3ce94c88be657..e91a0b6b5ccab 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll @@ -90,13 +90,13 @@ define void @test(ptr %p) { ; VEC-NEXT: store i64 0, ptr [[TMP36]], align 8 ; VEC-NEXT: store i64 0, ptr [[TMP37]], align 8 ; VEC-NEXT: store i64 0, ptr [[TMP38]], align 8 -; VEC-NEXT: [[TMP27:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) -; VEC-NEXT: [[TMP28:%.*]] = zext <4 x i16> [[TMP27]] to <4 x i64> ; VEC-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; VEC-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[STEP_ADD]], splat (i16 4) ; VEC-NEXT: [[TMP30:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; VEC-NEXT: br i1 [[TMP30]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; VEC: middle.block: +; VEC-NEXT: [[TMP42:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) +; VEC-NEXT: [[TMP28:%.*]] = zext <4 x i16> [[TMP42]] to <4 x i64> ; VEC-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP28]], i32 3 ; VEC-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP4]], [[N_VEC]] ; VEC-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] diff --git a/llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll index 7ae20a07290c3..41fb58c50ae00 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll @@ -101,3 +101,57 @@ loop.latch: exit: ret void } + +define i32 @predicated_load_non_affine_address(i32 %x, ptr %src) { +; CHECK-LABEL: define i32 @predicated_load_non_affine_address( +; CHECK-SAME: i32 [[X:%.*]], ptr [[SRC:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] +; CHECK-NEXT: [[REM:%.*]] = mul i32 [[IV]], [[X]] +; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[REM]], 0 +; CHECK-NEXT: br i1 [[C]], label %[[IF_THEN:.*]], label %[[LOOP_LATCH]] +; CHECK: [[IF_THEN]]: +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[IV]], [[X]] +; CHECK-NEXT: [[DIV_EXT:%.*]] = zext nneg i32 [[DIV]] to i64 +; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[DIV_EXT]] +; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1 +; CHECK-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i32 +; CHECK-NEXT: br label %[[LOOP_LATCH]] +; CHECK: [[LOOP_LATCH]]: +; CHECK-NEXT: [[T_0:%.*]] = phi i32 [ 0, %[[LOOP]] ], [ [[L_EXT]], %[[IF_THEN]] ] +; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 28 +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: [[T_0_LCSSA:%.*]] = phi i32 [ [[T_0]], %[[LOOP_LATCH]] ] +; CHECK-NEXT: ret i32 [[T_0_LCSSA]] +; +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ] + %rem = mul i32 %iv, %x + %c = icmp eq i32 %rem, 0 + br i1 %c, label %if.then, label %loop.latch + +if.then: + %div = udiv i32 %iv, %x + %div.ext = zext nneg i32 %div to i64 + %gep.src = getelementptr i8, ptr %src, i64 %div.ext + %l = load i8, ptr %gep.src, align 1 + %l.ext = zext i8 %l to i32 + br label %loop.latch + +loop.latch: + %t.0 = phi i32 [ 0, %loop ], [ %l.ext, %if.then ] + %iv.next = add nuw nsw i32 %iv, 1 + %ec = icmp eq i32 %iv.next, 28 + br i1 %ec, label %exit, label %loop + +exit: + %t.0.lcssa = phi i32 [ %t.0, %loop.latch ] + ret i32 %t.0.lcssa +} diff --git a/llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll b/llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll index 9fc591e2f4a1b..ceade1bdbc0bf 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll @@ -21,14 +21,14 @@ define void @simplify_udiv_1_in_replicate_region(i8 %arg, ptr %src) { ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i32 [[INDEX]] ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 4 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP3]], align 1 -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i8> [[WIDE_LOAD]], zeroinitializer -; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP4]], <4 x i8> zeroinitializer, <4 x i8> [[TMP1]] -; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i8> [[PREDPHI]], zeroinitializer -; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP5]] to <4 x i32> ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 ; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i8> [[WIDE_LOAD]], zeroinitializer +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP4]], <4 x i8> zeroinitializer, <4 x i8> [[TMP1]] +; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i8> [[PREDPHI]], zeroinitializer +; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP5]] to <4 x i32> ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i32> [[TMP6]], i32 3 ; CHECK-NEXT: br label %[[LATCH:.*]] ; CHECK: [[LATCH]]: @@ -222,13 +222,13 @@ define void @simplify_udiv_4_in_replicate_region2(i8 %arg, ptr noalias %src, ptr ; CHECK-NEXT: store i8 [[TMP77]], ptr [[TMP23]], align 1 ; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE29]] ; CHECK: [[PRED_STORE_CONTINUE29]]: -; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP11]], <4 x i8> [[TMP61]], <4 x i8> zeroinitializer -; CHECK-NEXT: [[TMP78:%.*]] = icmp ne <4 x i8> [[PREDPHI]], zeroinitializer -; CHECK-NEXT: [[TMP79:%.*]] = zext <4 x i1> [[TMP78]] to <4 x i32> ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 ; CHECK-NEXT: [[TMP80:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 ; CHECK-NEXT: br i1 [[TMP80]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP11]], <4 x i8> [[TMP61]], <4 x i8> zeroinitializer +; CHECK-NEXT: [[TMP78:%.*]] = icmp ne <4 x i8> [[PREDPHI]], zeroinitializer +; CHECK-NEXT: [[TMP79:%.*]] = zext <4 x i1> [[TMP78]] to <4 x i32> ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i32> [[TMP79]], i32 3 ; CHECK-NEXT: br label %[[LATCH:.*]] ; CHECK: [[LATCH]]: diff --git a/llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll b/llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll index 715d6db50488f..cb8ee2513284f 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/replicate-recipe-with-only-first-lane-used.ll @@ -207,7 +207,6 @@ define float @uniform_load_replicating_select(ptr %A, ptr %B, i64 %1) { ; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP10]], ptr [[A]], ptr [[TMP16]] ; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP10]], ptr [[A]], ptr [[TMP17]] ; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP10]], ptr [[A]], ptr [[TMP18]] -; CHECK-NEXT: [[TMP23:%.*]] = select i1 [[TMP10]], <4 x float> splat (float 1.000000e+01), <4 x float> splat (float 1.000000e+00) ; CHECK-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP19]], align 4 ; CHECK-NEXT: [[TMP25:%.*]] = load float, ptr [[TMP20]], align 4 ; CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[TMP21]], align 4 @@ -216,12 +215,13 @@ define float @uniform_load_replicating_select(ptr %A, ptr %B, i64 %1) { ; CHECK-NEXT: [[TMP29:%.*]] = insertelement <4 x float> [[TMP28]], float [[TMP25]], i32 1 ; CHECK-NEXT: [[TMP30:%.*]] = insertelement <4 x float> [[TMP29]], float [[TMP26]], i32 2 ; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x float> [[TMP30]], float [[TMP27]], i32 3 -; CHECK-NEXT: [[TMP32:%.*]] = fdiv <4 x float> splat (float 4.000000e+00), [[TMP31]] -; CHECK-NEXT: [[TMP33:%.*]] = call <4 x float> @llvm.pow.v4f32(<4 x float> [[TMP23]], <4 x float> [[TMP32]]) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP34]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP10]], <4 x float> splat (float 1.000000e+01), <4 x float> splat (float 1.000000e+00) +; CHECK-NEXT: [[TMP36:%.*]] = fdiv <4 x float> splat (float 4.000000e+00), [[TMP31]] +; CHECK-NEXT: [[TMP33:%.*]] = call <4 x float> @llvm.pow.v4f32(<4 x float> [[TMP32]], <4 x float> [[TMP36]]) ; CHECK-NEXT: [[TMP35:%.*]] = extractelement <4 x float> [[TMP33]], i32 3 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] ; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] diff --git a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll index 51be3699719e9..5902d588c2f41 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll @@ -462,38 +462,30 @@ define double @test_load_used_by_other_load_scev(ptr %ptr.a, ptr %ptr.b, ptr %pt ; I64-NEXT: [[ENTRY:.*]]: ; I64-NEXT: br label %[[OUTER_LOOP:.*]] ; I64: [[OUTER_LOOP_LOOPEXIT:.*]]: -; I64-NEXT: [[RESULT_LCSSA:%.*]] = phi double [ [[RESULT:%.*]], %[[INNER_LOOP:.*]] ] +; I64-NEXT: [[RESULT_LCSSA:%.*]] = phi double [ [[RESULT:%.*]], [[INNER_LOOP:%.*]] ] ; I64-NEXT: br label %[[OUTER_LOOP]] ; I64: [[OUTER_LOOP]]: ; I64-NEXT: [[ACCUM:%.*]] = phi double [ 0.000000e+00, %[[ENTRY]] ], [ [[RESULT_LCSSA]], %[[OUTER_LOOP_LOOPEXIT]] ] ; I64-NEXT: [[COND:%.*]] = call i1 @cond() -; I64-NEXT: br i1 [[COND]], label %[[INNER_LOOP_PREHEADER:.*]], label %[[EXIT:.*]] +; I64-NEXT: br i1 [[COND]], label %[[INNER_LOOP_PREHEADER:.*]], [[EXIT:label %.*]] ; I64: [[INNER_LOOP_PREHEADER]]: -; I64-NEXT: br label %[[INNER_LOOP]] -; I64: [[INNER_LOOP]]: -; I64-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[INNER_LOOP]] ], [ 0, %[[INNER_LOOP_PREHEADER]] ] -; I64-NEXT: [[ACCUM_INNER:%.*]] = phi double [ [[MUL1:%.*]], %[[INNER_LOOP]] ], [ [[ACCUM]], %[[INNER_LOOP_PREHEADER]] ] -; I64-NEXT: [[TMP1:%.*]] = add i64 [[IV]], 1 -; I64-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[PTR_C]], i64 [[TMP1]] -; I64-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[PTR_A]], i64 [[TMP1]] -; I64-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP5]], align 8 -; I64-NEXT: [[TMP9:%.*]] = getelementptr double, ptr [[PTR_B]], i64 [[TMP7]] +; I64-NEXT: br label %[[VECTOR_PH:.*]] +; I64: [[VECTOR_PH]]: +; I64-NEXT: br label %[[VECTOR_BODY:.*]] +; I64: [[VECTOR_BODY]]: +; I64-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV:%.*]], %[[VECTOR_BODY]] ] ; I64-NEXT: [[TMP10:%.*]] = load double, ptr [[PTR_A]], align 8 -; I64-NEXT: [[ADD1:%.*]] = fadd double [[TMP10]], 0.000000e+00 -; I64-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP3]], i64 8 -; I64-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP13]], align 8 -; I64-NEXT: [[MUL1]] = fmul double [[ADD1]], 0.000000e+00 -; I64-NEXT: [[MUL2:%.*]] = fmul double [[TMP15]], 0.000000e+00 -; I64-NEXT: [[ADD2:%.*]] = fadd double [[MUL2]], 0.000000e+00 -; I64-NEXT: [[ADD3:%.*]] = fadd double [[ADD2]], 1.000000e+00 -; I64-NEXT: [[TMP24:%.*]] = load double, ptr [[TMP9]], align 8 -; I64-NEXT: [[DIV:%.*]] = fdiv double [[TMP24]], [[ADD3]] -; I64-NEXT: [[RESULT]] = fsub double [[ACCUM_INNER]], [[DIV]] -; I64-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; I64-NEXT: [[TMP1:%.*]] = fadd double [[TMP10]], 0.000000e+00 +; I64-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x double> poison, double [[TMP1]], i64 0 +; I64-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x double> [[BROADCAST_SPLATINSERT]], <2 x double> poison, <2 x i32> zeroinitializer +; I64-NEXT: [[TMP2:%.*]] = fmul <2 x double> [[BROADCAST_SPLAT]], zeroinitializer +; I64-NEXT: [[IV]] = add nuw i64 [[INDEX]], 2 ; I64-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 100 -; I64-NEXT: br i1 [[EXITCOND]], label %[[OUTER_LOOP_LOOPEXIT]], label %[[INNER_LOOP]] -; I64: [[EXIT]]: -; I64-NEXT: ret double [[ACCUM]] +; I64-NEXT: br i1 [[EXITCOND]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; I64: [[MIDDLE_BLOCK]]: +; I64-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <2 x double> [[TMP2]], i32 1 +; I64-NEXT: br label %[[SCALAR_PH:.*]] +; I64: [[SCALAR_PH]]: ; ; I32-LABEL: define double @test_load_used_by_other_load_scev( ; I32-SAME: ptr [[PTR_A:%.*]], ptr [[PTR_B:%.*]], ptr [[PTR_C:%.*]]) { @@ -587,10 +579,10 @@ define double @test_load_used_by_other_load_scev_low_trip_count(ptr %ptr.a, ptr ; I64-NEXT: [[TMP9:%.*]] = getelementptr double, ptr [[PTR_B]], i64 [[TMP7]] ; I64-NEXT: [[TMP10:%.*]] = load double, ptr [[PTR_A]], align 8 ; I64-NEXT: [[ADD1:%.*]] = fadd double [[TMP10]], 0.000000e+00 -; I64-NEXT: [[GEP_C_OFFSET:%.*]] = getelementptr i8, ptr [[TMP3]], i64 8 -; I64-NEXT: [[LOAD_C:%.*]] = load double, ptr [[GEP_C_OFFSET]], align 8 +; I64-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP3]], i64 8 +; I64-NEXT: [[TMP15:%.*]] = load double, ptr [[TMP13]], align 8 ; I64-NEXT: [[MUL1]] = fmul double [[ADD1]], 0.000000e+00 -; I64-NEXT: [[MUL2:%.*]] = fmul double [[LOAD_C]], 0.000000e+00 +; I64-NEXT: [[MUL2:%.*]] = fmul double [[TMP15]], 0.000000e+00 ; I64-NEXT: [[ADD2:%.*]] = fadd double [[MUL2]], 0.000000e+00 ; I64-NEXT: [[ADD3:%.*]] = fadd double [[ADD2]], 1.000000e+00 ; I64-NEXT: [[TMP24:%.*]] = load double, ptr [[TMP9]], align 8 @@ -966,7 +958,7 @@ define void @address_use_in_different_block(ptr noalias %dst, ptr %src.0, ptr %s ; I64-NEXT: store double [[TMP91]], ptr [[TMP83]], align 8 ; I64-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; I64-NEXT: [[TMP92:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 -; I64-NEXT: br i1 [[TMP92]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; I64-NEXT: br i1 [[TMP92]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] ; I64: [[MIDDLE_BLOCK]]: ; I64-NEXT: br label %[[SCALAR_PH:.*]] ; I64: [[SCALAR_PH]]: diff --git a/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll b/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll index 4c3fd29a56021..a3d9039073779 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll @@ -139,11 +139,11 @@ define i32 @reduction_i32(ptr nocapture readonly %A, ptr nocapture readonly %B, ; CHECK-NEXT: [[WIDE_MASKED_LOAD3:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0(ptr align 4 [[TMP7]], <8 x i1> [[TMP4]], <8 x i32> poison) ; CHECK-NEXT: [[TMP9:%.*]] = add nsw <8 x i32> [[WIDE_MASKED_LOAD3]], [[WIDE_MASKED_LOAD]] ; CHECK-NEXT: [[TMP10]] = add <8 x i32> [[TMP9]], [[VEC_PHI]] -; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[TMP10]], <8 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP11:%.*]] = select <8 x i1> [[TMP4]], <8 x i32> [[TMP10]], <8 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> [[TMP11]]) ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: for.cond.cleanup: diff --git a/llvm/test/Transforms/LoopVectorize/cse-casts.ll b/llvm/test/Transforms/LoopVectorize/cse-casts.ll index b6d7a9f81ec9d..3c73eafa1b22a 100644 --- a/llvm/test/Transforms/LoopVectorize/cse-casts.ll +++ b/llvm/test/Transforms/LoopVectorize/cse-casts.ll @@ -259,12 +259,10 @@ define void @preserve_flags_narrowing_extends_and_truncs(ptr noalias %A, ptr noa ; CHECK-NEXT: [[TMP89:%.*]] = phi <4 x i8> [ [[TMP86]], %[[PRED_LOAD_CONTINUE42]] ], [ [[TMP88]], %[[PRED_LOAD_IF43]] ] ; CHECK-NEXT: [[TMP90:%.*]] = trunc <4 x i8> [[TMP77]] to <4 x i1> ; CHECK-NEXT: [[TMP91:%.*]] = trunc <4 x i8> [[TMP89]] to <4 x i1> -; CHECK-NEXT: [[TMP92:%.*]] = and <4 x i1> [[TMP90]], splat (i1 true) -; CHECK-NEXT: [[TMP93:%.*]] = and <4 x i1> [[TMP91]], splat (i1 true) ; CHECK-NEXT: [[TMP94:%.*]] = select <4 x i1> [[TMP90]], <4 x float> splat (float 1.000000e+00), <4 x float> zeroinitializer ; CHECK-NEXT: [[TMP95:%.*]] = select <4 x i1> [[TMP91]], <4 x float> splat (float 1.000000e+00), <4 x float> zeroinitializer -; CHECK-NEXT: [[TMP96:%.*]] = select <4 x i1> [[TMP92]], <4 x float> splat (float 3.000000e+00), <4 x float> [[TMP94]] -; CHECK-NEXT: [[TMP97:%.*]] = select <4 x i1> [[TMP93]], <4 x float> splat (float 3.000000e+00), <4 x float> [[TMP95]] +; CHECK-NEXT: [[TMP96:%.*]] = select <4 x i1> [[TMP90]], <4 x float> splat (float 3.000000e+00), <4 x float> [[TMP94]] +; CHECK-NEXT: [[TMP97:%.*]] = select <4 x i1> [[TMP91]], <4 x float> splat (float 3.000000e+00), <4 x float> [[TMP95]] ; CHECK-NEXT: [[TMP98:%.*]] = bitcast <4 x float> [[TMP96]] to <4 x i32> ; CHECK-NEXT: [[TMP99:%.*]] = bitcast <4 x float> [[TMP97]] to <4 x i32> ; CHECK-NEXT: [[TMP100:%.*]] = trunc <4 x i32> [[TMP98]] to <4 x i8> diff --git a/llvm/test/Transforms/LoopVectorize/early_exit_legality.ll b/llvm/test/Transforms/LoopVectorize/early_exit_legality.ll index 6c35417bd4492..c6abc932b653a 100644 --- a/llvm/test/Transforms/LoopVectorize/early_exit_legality.ll +++ b/llvm/test/Transforms/LoopVectorize/early_exit_legality.ll @@ -634,6 +634,37 @@ loop.end: } +; Parallel uncountable exits with loop-invariant conditions. +define void @uncountable_exits_invariant_conditions(ptr %p, i1 %cond1, i1 %cond2, i1 %cond3) { +; CHECK-LABEL: LV: Checking a loop in 'uncountable_exits_invariant_conditions' +; CHECK: LV: Not vectorizing: Uncountable early exits do not form a dominance chain. +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] + br i1 %cond1, label %then.1, label %else.1 + +else.1: + br i1 %cond2, label %then.2, label %exit + +then.2: + %getelementptr.i = getelementptr i16, ptr %p, i64 %iv + %l = load i16, ptr %getelementptr.i, align 2 + %ec = icmp ugt i16 %l, -25 + br i1 %ec, label %exit, label %loop.latch + +then.1: + br i1 %cond3, label %exit, label %loop.latch + +loop.latch: + %iv.next = add i64 %iv, 1 + br label %loop.header + +exit: + ret void +} + declare i32 @foo(i32) readonly declare @foo_vec() diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll index 39af9cf382c1d..9ab2557387877 100644 --- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll +++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll @@ -1,66 +1,72 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 ; REQUIRES: asserts ; RUN: opt -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -debug-only=loop-vectorize -disable-output -S %s 2>&1 | FileCheck %s define void @test_chained_first_order_recurrences_1(ptr %ptr) { ; CHECK-LABEL: 'test_chained_first_order_recurrences_1' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<1000> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<1000> = original trip-count ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.1> = phi ir<22>, ir<%for.1.next> -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.2> = phi ir<33>, vp<[[FOR1_SPLICE:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep.ptr> = getelementptr inbounds ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.ptr> -; CHECK-NEXT: WIDEN ir<%for.1.next> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: EMIT vp<[[FOR1_SPLICE]]> = first-order splice ir<%for.1>, ir<%for.1.next> -; CHECK-NEXT: EMIT vp<[[FOR2_SPLICE:%.+]]> = first-order splice ir<%for.2>, vp<[[FOR1_SPLICE]]> -; CHECK-NEXT: WIDEN ir<%add> = add vp<[[FOR1_SPLICE]]>, vp<[[FOR2_SPLICE]]> -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%gep.ptr> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%add> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.1> = phi ir<22>, ir<%for.1.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.2> = phi ir<33>, vp<[[VP6:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.ptr> = getelementptr inbounds ir<%ptr>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.ptr> +; CHECK-NEXT: WIDEN ir<%for.1.next> = load vp<[[VP5]]> +; CHECK-NEXT: EMIT vp<[[VP6]]> = first-order splice ir<%for.1>, ir<%for.1.next> +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = first-order splice ir<%for.2>, vp<[[VP6]]> +; CHECK-NEXT: WIDEN ir<%add> = add vp<[[VP6]]>, vp<[[VP7]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer inbounds ir<%gep.ptr> +; CHECK-NEXT: WIDEN store vp<[[VP8]]>, ir<%add> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RESUME_1_PART:%.+]]> = extract-last-part ir<%for.1.next> -; CHECK-NEXT: EMIT vp<[[RESUME_1:%.+]]> = extract-last-lane vp<[[RESUME_1_PART]]> -; CHECK-NEXT: EMIT vp<[[RESUME_2_PART:%.+]]> = extract-last-part vp<[[FOR1_SPLICE]]> -; CHECK-NEXT: EMIT vp<[[RESUME_2:%.+]]>.1 = extract-last-lane vp<[[RESUME_2_PART]]> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<1000>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = extract-last-part ir<%for.1.next> +; CHECK-NEXT: EMIT vp<%vector.recur.extract> = extract-last-lane vp<[[VP10]]> +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = extract-last-part vp<[[VP6]]> +; CHECK-NEXT: EMIT vp<%vector.recur.extract>.1 = extract-last-lane vp<[[VP11]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> ; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb +; CHECK-NEXT: ir-bb: ; CHECK-NEXT: No successors ; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_1_P:%.*]]> = phi [ vp<[[RESUME_1]]>, middle.block ], [ ir<22>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_2_P:%.*]]>.1 = phi [ vp<[[RESUME_2]]>.1, middle.block ], [ ir<33>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.*]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<%vector.recur.extract>, middle.block ], [ ir<22>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init>.1 = phi [ vp<%vector.recur.extract>.1, middle.block ], [ ir<33>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %for.1 = phi i16 [ 22, %entry ], [ %for.1.next, %loop ] (extra operand: vp<[[RESUME_1_P]]> from scalar.ph) -; CHECK-NEXT: IR %for.2 = phi i16 [ 33, %entry ], [ %for.1, %loop ] (extra operand: vp<[[RESUME_2_P]]>.1 from scalar.ph) -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %exitcond.not = icmp eq i64 %iv.next, 1000 +; CHECK-NEXT: IR %for.1 = phi i16 [ 22, %entry ], [ %for.1.next, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %for.2 = phi i16 [ 33, %entry ], [ %for.1, %loop ] (extra operand: vp<%scalar.recur.init>.1 from scalar.ph) +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 1 +; CHECK-NEXT: IR %gep.ptr = getelementptr inbounds i16, ptr %ptr, i64 %iv +; CHECK-NEXT: IR %for.1.next = load i16, ptr %gep.ptr, align 2 +; CHECK-NEXT: IR %add = add i16 %for.1, %for.2 +; CHECK-NEXT: IR store i16 %add, ptr %gep.ptr, align 2 +; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1000 ; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: } ; entry: br label %loop @@ -83,70 +89,76 @@ exit: define void @test_chained_first_order_recurrences_3(ptr %ptr) { ; CHECK-LABEL: 'test_chained_first_order_recurrences_3' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<1000> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<1000> = original trip-count ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.1> = phi ir<22>, ir<%for.1.next> -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.2> = phi ir<33>, vp<[[FOR1_SPLICE:%.+]]> -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.3> = phi ir<33>, vp<[[FOR2_SPLICE:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep.ptr> = getelementptr inbounds ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.ptr> -; CHECK-NEXT: WIDEN ir<%for.1.next> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: EMIT vp<[[FOR1_SPLICE]]> = first-order splice ir<%for.1>, ir<%for.1.next> -; CHECK-NEXT: EMIT vp<[[FOR2_SPLICE]]> = first-order splice ir<%for.2>, vp<[[FOR1_SPLICE]]> -; CHECK-NEXT: EMIT vp<[[FOR3_SPLICE:%.+]]> = first-order splice ir<%for.3>, vp<[[FOR2_SPLICE]]> -; CHECK-NEXT: WIDEN ir<%add.1> = add vp<[[FOR1_SPLICE]]>, vp<[[FOR2_SPLICE]]> -; CHECK-NEXT: WIDEN ir<%add.2> = add ir<%add.1>, vp<[[FOR3_SPLICE]]> -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%gep.ptr> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%add.2> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.1> = phi ir<22>, ir<%for.1.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.2> = phi ir<33>, vp<[[VP6:%[0-9]+]]> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.3> = phi ir<33>, vp<[[VP7:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.ptr> = getelementptr inbounds ir<%ptr>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.ptr> +; CHECK-NEXT: WIDEN ir<%for.1.next> = load vp<[[VP5]]> +; CHECK-NEXT: EMIT vp<[[VP6]]> = first-order splice ir<%for.1>, ir<%for.1.next> +; CHECK-NEXT: EMIT vp<[[VP7]]> = first-order splice ir<%for.2>, vp<[[VP6]]> +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = first-order splice ir<%for.3>, vp<[[VP7]]> +; CHECK-NEXT: WIDEN ir<%add.1> = add vp<[[VP6]]>, vp<[[VP7]]> +; CHECK-NEXT: WIDEN ir<%add.2> = add ir<%add.1>, vp<[[VP8]]> +; CHECK-NEXT: vp<[[VP9:%[0-9]+]]> = vector-pointer inbounds ir<%gep.ptr> +; CHECK-NEXT: WIDEN store vp<[[VP9]]>, ir<%add.2> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RESUME_1_PART:%.+]]> = extract-last-part ir<%for.1.next> -; CHECK-NEXT: EMIT vp<[[RESUME_1:%.+]]> = extract-last-lane vp<[[RESUME_1_PART]]> -; CHECK-NEXT: EMIT vp<[[RESUME_2_PART:%.+]]> = extract-last-part vp<[[FOR1_SPLICE]]> -; CHECK-NEXT: EMIT vp<[[RESUME_2:%.+]]>.1 = extract-last-lane vp<[[RESUME_2_PART]]> -; CHECK-NEXT: EMIT vp<[[RESUME_3_PART:%.+]]> = extract-last-part vp<[[FOR2_SPLICE]]> -; CHECK-NEXT: EMIT vp<[[RESUME_3:%.+]]>.2 = extract-last-lane vp<[[RESUME_3_PART]]> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<1000>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = extract-last-part ir<%for.1.next> +; CHECK-NEXT: EMIT vp<%vector.recur.extract> = extract-last-lane vp<[[VP11]]> +; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = extract-last-part vp<[[VP6]]> +; CHECK-NEXT: EMIT vp<%vector.recur.extract>.1 = extract-last-lane vp<[[VP12]]> +; CHECK-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = extract-last-part vp<[[VP7]]> +; CHECK-NEXT: EMIT vp<%vector.recur.extract>.2 = extract-last-lane vp<[[VP13]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> ; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb +; CHECK-NEXT: ir-bb: ; CHECK-NEXT: No successors ; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_1_P:%.*]]> = phi [ vp<[[RESUME_1]]>, middle.block ], [ ir<22>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_2_P:%.*]]>.1 = phi [ vp<[[RESUME_2]]>.1, middle.block ], [ ir<33>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_3_P:%.*]]>.2 = phi [ vp<[[RESUME_3]]>.2, middle.block ], [ ir<33>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.*]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<%vector.recur.extract>, middle.block ], [ ir<22>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init>.1 = phi [ vp<%vector.recur.extract>.1, middle.block ], [ ir<33>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init>.2 = phi [ vp<%vector.recur.extract>.2, middle.block ], [ ir<33>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %for.1 = phi i16 [ 22, %entry ], [ %for.1.next, %loop ] (extra operand: vp<[[RESUME_1_P]]> from scalar.ph) -; CHECK-NEXT: IR %for.2 = phi i16 [ 33, %entry ], [ %for.1, %loop ] (extra operand: vp<[[RESUME_2_P]]>.1 from scalar.ph) -; CHECK-NEXT: IR %for.3 = phi i16 [ 33, %entry ], [ %for.2, %loop ] (extra operand: vp<[[RESUME_3_P]]>.2 from scalar.ph) -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %exitcond.not = icmp eq i64 %iv.next, 1000 -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %for.1 = phi i16 [ 22, %entry ], [ %for.1.next, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %for.2 = phi i16 [ 33, %entry ], [ %for.1, %loop ] (extra operand: vp<%scalar.recur.init>.1 from scalar.ph) +; CHECK-NEXT: IR %for.3 = phi i16 [ 33, %entry ], [ %for.2, %loop ] (extra operand: vp<%scalar.recur.init>.2 from scalar.ph) +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 1 +; CHECK-NEXT: IR %gep.ptr = getelementptr inbounds i16, ptr %ptr, i64 %iv +; CHECK-NEXT: IR %for.1.next = load i16, ptr %gep.ptr, align 2 +; CHECK-NEXT: IR %add.1 = add i16 %for.1, %for.2 +; CHECK-NEXT: IR %add.2 = add i16 %add.1, %for.3 +; CHECK-NEXT: IR store i16 %add.2, ptr %gep.ptr, align 2 +; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1000 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -175,62 +187,69 @@ exit: ; for.x.next can be hoisted. define i32 @test_chained_first_order_recurrences_4(ptr %base, i64 %x) { ; CHECK-LABEL: 'test_chained_first_order_recurrences_4' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<4098> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<4098> = original trip-count ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: EMIT vp<[[SHL:%.+]]> = shl ir<%x>, ir<1> -; CHECK-NEXT: Successor(s): vector loop +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = shl ir<%x>, ir<1> +; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.x> = phi ir<0>, vp<[[SHL]]> -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.y> = phi ir<0>, ir<%for.x.prev> -; CHECK-NEXT: vp<[[SCALAR_STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep> = getelementptr ir<%base>, vp<[[SCALAR_STEPS]]> -; CHECK-NEXT: EMIT vp<[[SPLICE_X:%.]]> = first-order splice ir<%for.x>, vp<[[SHL]]> -; CHECK-NEXT: WIDEN-CAST ir<%for.x.prev> = trunc vp<[[SPLICE_X]]> to i32 -; CHECK-NEXT: EMIT vp<[[SPLICE_Y:%.+]]> = first-order splice ir<%for.y>, ir<%for.x.prev> -; CHECK-NEXT: WIDEN-CAST ir<%for.y.i64> = sext vp<[[SPLICE_Y]]> to i64 -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%gep> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%for.y.i64> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.x> = phi ir<0>, vp<[[VP3]]> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.y> = phi ir<0>, ir<%for.x.prev> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep> = getelementptr ir<%base>, vp<[[VP5]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = first-order splice ir<%for.x>, vp<[[VP3]]> +; CHECK-NEXT: WIDEN-CAST ir<%for.x.prev> = trunc vp<[[VP6]]> to i32 +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = first-order splice ir<%for.y>, ir<%for.x.prev> +; CHECK-NEXT: WIDEN-CAST ir<%for.y.i64> = sext vp<[[VP7]]> to i64 +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer ir<%gep> +; CHECK-NEXT: WIDEN store vp<[[VP8]]>, ir<%for.y.i64> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[EXT_X_PART:%.+]]> = extract-last-part vp<[[SHL]]> -; CHECK-NEXT: EMIT vp<[[EXT_X:%.+]]> = extract-last-lane vp<[[EXT_X_PART]]> -; CHECK-NEXT: EMIT vp<[[EXT_Y_PART:%.+]]> = extract-last-part ir<%for.x.prev> -; CHECK-NEXT: EMIT vp<[[EXT_Y:%.+]]>.1 = extract-last-lane vp<[[EXT_Y_PART]]> -; CHECK-NEXT: EMIT vp<[[MIDDLE_C:%.+]]> = icmp eq ir<4098>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[MIDDLE_C]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = extract-last-part vp<[[VP3]]> +; CHECK-NEXT: EMIT vp<%vector.recur.extract> = extract-last-lane vp<[[VP10]]> +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = extract-last-part ir<%for.x.prev> +; CHECK-NEXT: EMIT vp<%vector.recur.extract>.1 = extract-last-lane vp<[[VP11]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<4098>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: No successors +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors ; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph: -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.*]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_X:%.+]]> = phi [ vp<[[EXT_X]]>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_Y:%.+]]>.1 = phi [ vp<[[EXT_Y]]>.1, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: Successor(s): ir-bb +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<%vector.recur.extract>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init>.1 = phi [ vp<%vector.recur.extract>.1, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK-NEXT: IR %for.x = phi i64 [ %for.x.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_X]]> from scalar.ph) -; CHECK-NEXT: IR %for.y = phi i32 [ %for.x.prev, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_Y]]>.1 from scalar.ph) -; CHECK: No successors -; CHECK-NEXT: } +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %for.x = phi i64 [ %for.x.next, %loop ], [ 0, %entry ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %for.y = phi i32 [ %for.x.prev, %loop ], [ 0, %entry ] (extra operand: vp<%scalar.recur.init>.1 from scalar.ph) +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %gep = getelementptr i64, ptr %base, i64 %iv +; CHECK-NEXT: IR %for.x.prev = trunc i64 %for.x to i32 +; CHECK-NEXT: IR %for.y.i64 = sext i32 %for.y to i64 +; CHECK-NEXT: IR store i64 %for.y.i64, ptr %gep, align 4 +; CHECK-NEXT: IR %for.x.next = mul i64 %x, 2 +; CHECK-NEXT: IR %icmp = icmp ugt i64 %iv, 4096 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -254,64 +273,72 @@ ret: define i32 @test_chained_first_order_recurrences_5_hoist_to_load(ptr %base) { ; CHECK-LABEL: 'test_chained_first_order_recurrences_5_hoist_to_load' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<4098> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<4098> = original trip-count ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.x> = phi ir<0>, vp<%6> -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.y> = phi ir<0>, ir<%for.x.prev> -; CHECK-NEXT: vp<[[SCALAR_STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep> = getelementptr ir<%base>, vp<[[SCALAR_STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%gep> -; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: EMIT vp<%6> = shl ir<%l>, ir<1> -; CHECK-NEXT: EMIT vp<[[SPLICE_X:%.]]> = first-order splice ir<%for.x>, vp<%6> -; CHECK-NEXT: WIDEN-CAST ir<%for.x.prev> = trunc vp<[[SPLICE_X]]> to i32 -; CHECK-NEXT: EMIT vp<[[SPLICE_Y:%.+]]> = first-order splice ir<%for.y>, ir<%for.x.prev> -; CHECK-NEXT: WIDEN-CAST ir<%for.y.i64> = sext vp<[[SPLICE_Y]]> to i64 -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%gep> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%for.y.i64> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.x> = phi ir<0>, vp<[[VP6:%[0-9]+]]> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.y> = phi ir<0>, ir<%for.x.prev> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep> = getelementptr ir<%base>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer ir<%gep> +; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP5]]> +; CHECK-NEXT: EMIT vp<[[VP6]]> = shl ir<%l>, ir<1> +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = first-order splice ir<%for.x>, vp<[[VP6]]> +; CHECK-NEXT: WIDEN-CAST ir<%for.x.prev> = trunc vp<[[VP7]]> to i32 +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = first-order splice ir<%for.y>, ir<%for.x.prev> +; CHECK-NEXT: WIDEN-CAST ir<%for.y.i64> = sext vp<[[VP8]]> to i64 +; CHECK-NEXT: vp<[[VP9:%[0-9]+]]> = vector-pointer ir<%gep> +; CHECK-NEXT: WIDEN store vp<[[VP9]]>, ir<%for.y.i64> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[EXT_X_PART:%.+]]> = extract-last-part vp<%6> -; CHECK-NEXT: EMIT vp<[[EXT_X:%.+]]> = extract-last-lane vp<[[EXT_X_PART]]> -; CHECK-NEXT: EMIT vp<[[EXT_Y_PART:%.+]]> = extract-last-part ir<%for.x.prev> -; CHECK-NEXT: EMIT vp<[[EXT_Y:%.+]]>.1 = extract-last-lane vp<[[EXT_Y_PART]]> -; CHECK-NEXT: EMIT vp<[[MIDDLE_C:%.+]]> = icmp eq ir<4098>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[MIDDLE_C]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = extract-last-part vp<[[VP6]]> +; CHECK-NEXT: EMIT vp<%vector.recur.extract> = extract-last-lane vp<[[VP11]]> +; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = extract-last-part ir<%for.x.prev> +; CHECK-NEXT: EMIT vp<%vector.recur.extract>.1 = extract-last-lane vp<[[VP12]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<4098>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: No successors +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors ; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph: -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.*]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_X:%.+]]> = phi [ vp<[[EXT_X]]>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_Y:%.+]]>.1 = phi [ vp<[[EXT_Y]]>.1, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: Successor(s): ir-bb +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<%vector.recur.extract>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init>.1 = phi [ vp<%vector.recur.extract>.1, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK-NEXT: IR %for.x = phi i64 [ %for.x.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_X]]> from scalar.ph) -; CHECK-NEXT: IR %for.y = phi i32 [ %for.x.prev, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_Y]]>.1 from scalar.ph) -; CHECK: No successors -; CHECK-NEXT: } +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %for.x = phi i64 [ %for.x.next, %loop ], [ 0, %entry ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %for.y = phi i32 [ %for.x.prev, %loop ], [ 0, %entry ] (extra operand: vp<%scalar.recur.init>.1 from scalar.ph) +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %gep = getelementptr i64, ptr %base, i64 %iv +; CHECK-NEXT: IR %l = load i64, ptr %gep, align 4 +; CHECK-NEXT: IR %for.x.prev = trunc i64 %for.x to i32 +; CHECK-NEXT: IR %for.y.i64 = sext i32 %for.y to i64 +; CHECK-NEXT: IR store i64 %for.y.i64, ptr %gep, align 4 +; CHECK-NEXT: IR %for.x.next = mul i64 %l, 2 +; CHECK-NEXT: IR %icmp = icmp ugt i64 %iv, 4096 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll index cf2e7ccd1b2f0..15622f9eb961c 100644 --- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll +++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll @@ -94,9 +94,6 @@ define i32 @sink_after_dead_inst(ptr %A.ptr) { ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 4) ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16 -; CHECK-NEXT: [[TMP0:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) -; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i16> [[TMP0]], [[TMP0]] -; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32> ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[A_PTR]], i16 [[OFFSET_IDX]] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP3]], i64 4 ; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP3]], align 4 @@ -106,6 +103,9 @@ define i32 @sink_after_dead_inst(ptr %A.ptr) { ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 ; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) +; CHECK-NEXT: [[TMP4:%.*]] = or <4 x i16> [[TMP7]], [[TMP7]] +; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP4]] to <4 x i32> ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i32> [[TMP2]], i32 2 ; CHECK-NEXT: br label %[[FOR_END:.*]] ; CHECK: [[FOR_END]]: @@ -152,7 +152,6 @@ define void @sink_dead_inst(ptr %a) { ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i16 -27, [[DOTCAST]] ; CHECK-NEXT: [[TMP0:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 1) ; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) -; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32> ; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i16> [[TMP0]], splat (i16 5) ; CHECK-NEXT: [[TMP4]] = add <4 x i16> [[TMP1]], splat (i16 5) ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i16> [[VECTOR_RECUR]], <4 x i16> [[TMP3]], <4 x i32> @@ -168,6 +167,7 @@ define void @sink_dead_inst(ptr %a) { ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 40 ; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32> ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i16> [[TMP4]], i32 3 ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT1:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3 ; CHECK-NEXT: br label %[[SCALAR_PH:.*]] @@ -221,13 +221,13 @@ define void @unused_recurrence(ptr %a) { ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 4) -; CHECK-NEXT: [[TMP0:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) -; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i16> [[TMP0]], splat (i16 5) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[STEP_ADD]], splat (i16 4) ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1024 ; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) +; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i16> [[TMP3]], splat (i16 5) ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3 ; CHECK-NEXT: br label %[[SCALAR_PH:.*]] ; CHECK: [[SCALAR_PH]]: diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll index 3ae58cfb0fb01..9a449897033ef 100644 --- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll +++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll @@ -24,11 +24,11 @@ define i64 @pr97452_scalable_vf1_for_live_out(ptr %src) { ; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi [ [[VECTOR_RECUR_INIT]], %[[VECTOR_PH]] ], [ [[WIDE_LOAD:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD]] = load , ptr [[TMP5]], align 8 -; CHECK-NEXT: [[TMP7:%.*]] = call @llvm.vector.splice.right.nxv1i64( [[VECTOR_RECUR]], [[WIDE_LOAD]], i32 1) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP7:%.*]] = call @llvm.vector.splice.right.nxv1i64( [[VECTOR_RECUR]], [[WIDE_LOAD]], i32 1) ; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vscale.i32() ; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP9]], 1 ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[WIDE_LOAD]], i32 [[TMP10]] diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll index 3f9e530f1a097..6992a441f9444 100644 --- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll +++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 ; REQUIRES: asserts ; RUN: opt < %s -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -force-widen-divrem-via-safe-divisor=0 -disable-output -debug-only=loop-vectorize 2>&1 | FileCheck %s @@ -7,79 +8,99 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" ; first-order recurrence. define void @sink_replicate_region_1(i32 %x, ptr %ptr, ptr noalias %dst) optsize { -; CHECK-LABEL: sink_replicate_region_1 -; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count -; CHECK-NEXT: Live-in ir<20001> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv> -; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: vp<[[STEPS:%.]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]> -; CHECK-NEXT: Successor(s): pred.load -; CHECK-EMPTY: -; CHECK-NEXT: pred.load: { -; CHECK-NEXT: pred.load.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> -; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.load.if: -; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: REPLICATE ir<%lv> = load ir<%gep> (S->V) -; CHECK-NEXT: Successor(s): pred.load.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.load.continue: -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED1:%.+]]> = ir<%lv> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.0 -; CHECK-EMPTY: -; CHECK-NEXT: loop.0: -; CHECK-NEXT: WIDEN-CAST ir<%conv> = sext vp<[[PRED1]]> to i32 -; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%0>, ir<%conv> -; CHECK-NEXT: Successor(s): pred.store -; CHECK-EMPTY: -; CHECK-NEXT: pred.store: { -; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> -; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.if: -; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> -; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr ir<%dst>, vp<[[STEPS]]> -; CHECK-NEXT: REPLICATE ir<%add> = add ir<%conv>, ir<%rem> -; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep.dst> -; CHECK-NEXT: Successor(s): pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.continue: -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.2 -; CHECK-EMPTY: -; CHECK-NEXT: loop.2: -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors +; CHECK-LABEL: 'sink_replicate_region_1' +; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in vp<[[VP3:%[0-9]+]]> = backedge-taken count +; CHECK-NEXT: Live-in ir<20001> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv> +; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = icmp ule ir<%iv>, vp<[[VP3]]> +; CHECK-NEXT: Successor(s): pred.load +; CHECK-EMPTY: +; CHECK-NEXT: pred.load: { +; CHECK-NEXT: pred.load.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP6]]> +; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.load.if: +; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[VP5]]> +; CHECK-NEXT: REPLICATE ir<%lv> = load ir<%gep> (S->V) +; CHECK-NEXT: Successor(s): pred.load.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.load.continue: +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP7:%[0-9]+]]> = ir<%lv> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): loop.0 +; CHECK-EMPTY: +; CHECK-NEXT: loop.0: +; CHECK-NEXT: WIDEN-CAST ir<%conv> = sext vp<[[VP7]]> to i32 +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = first-order splice ir<%0>, ir<%conv> +; CHECK-NEXT: Successor(s): pred.store +; CHECK-EMPTY: +; CHECK-NEXT: pred.store: { +; CHECK-NEXT: pred.store.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP6]]> +; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.if: +; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[VP8]]>, ir<%x> +; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr ir<%dst>, vp<[[VP5]]> +; CHECK-NEXT: REPLICATE ir<%add> = add ir<%conv>, ir<%rem> +; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep.dst> +; CHECK-NEXT: Successor(s): pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.continue: +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): loop.2 +; CHECK-EMPTY: +; CHECK-NEXT: loop.2: +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %0 = phi i32 [ 0, %entry ], [ %conv, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rem = srem i32 %0, %x +; CHECK-NEXT: IR %gep = getelementptr i8, ptr %ptr, i32 %iv +; CHECK-NEXT: IR %lv = load i8, ptr %gep, align 1 +; CHECK-NEXT: IR %conv = sext i8 %lv to i32 +; CHECK-NEXT: IR %add = add i32 %conv, %rem +; CHECK-NEXT: IR %gep.dst = getelementptr i32, ptr %dst, i32 %iv +; CHECK-NEXT: IR store i32 %add, ptr %gep.dst, align 4 +; CHECK-NEXT: IR %iv.next = add nsw i32 %iv, 1 +; CHECK-NEXT: IR %ec = icmp eq i32 %iv.next, 20001 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -103,62 +124,75 @@ exit: } define void @sink_replicate_region_2(i32 %x, i8 %y, ptr %ptr, i32 %z) optsize { -; CHECK-LABEL: sink_replicate_region_2 -; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count -; CHECK-NEXT: Live-in ir<20001> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: WIDEN-CAST ir<%recur.next> = sext ir<%y> to i32 -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> -; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]> -; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur>, ir<%recur.next> -; CHECK-NEXT: WIDEN ir<%cond> = icmp eq ir<%iv>, ir<%z> -; CHECK-NEXT: EMIT vp<[[AND:%.+]]> = logical-and vp<[[MASK]]>, ir<%cond> -; CHECK-NEXT: Successor(s): pred.store -; CHECK-EMPTY: -; CHECK-NEXT: pred.store: { -; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[AND]]> -; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.if: -; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: REPLICATE ir<%add> = add ir<%rem>, ir<%recur.next> -; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep> -; CHECK-NEXT: Successor(s): pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.continue: -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): if.1 -; CHECK-EMPTY: -; CHECK-NEXT: if.1: -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors +; CHECK-LABEL: 'sink_replicate_region_2' +; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in vp<[[VP3:%[0-9]+]]> = backedge-taken count +; CHECK-NEXT: Live-in ir<20001> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: WIDEN-CAST ir<%recur.next> = sext ir<%y> to i32 +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> +; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = icmp ule ir<%iv>, vp<[[VP3]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = first-order splice ir<%recur>, ir<%recur.next> +; CHECK-NEXT: WIDEN ir<%cond> = icmp eq ir<%iv>, ir<%z> +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = logical-and vp<[[VP5]]>, ir<%cond> +; CHECK-NEXT: Successor(s): pred.store +; CHECK-EMPTY: +; CHECK-NEXT: pred.store: { +; CHECK-NEXT: pred.store.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP7]]> +; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.if: +; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[VP6]]>, ir<%x> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[VP8]]> +; CHECK-NEXT: REPLICATE ir<%add> = add ir<%rem>, ir<%recur.next> +; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep> +; CHECK-NEXT: Successor(s): pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.continue: +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): if.1 +; CHECK-EMPTY: +; CHECK-NEXT: if.1: +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %recur = phi i32 [ 0, %entry ], [ %recur.next, %latch ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %iv = phi i32 [ 0, %entry ], [ %iv.next, %latch ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %recur.next = sext i8 %y to i32 +; CHECK-NEXT: IR %cond = icmp eq i32 %iv, %z +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -187,63 +221,82 @@ exit: } define i32 @sink_replicate_region_3_reduction(i32 %x, i8 %y, ptr %ptr) optsize { -; CHECK-LABEL: sink_replicate_region_3_reduction -; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count -; CHECK-NEXT: Live-in ir<20001> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<1234>, ir<-1>, ir<1> -; CHECK-NEXT: WIDEN-CAST ir<%recur.next> = sext ir<%y> to i32 -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%and.red> = phi vp<[[RDX_START]]>, ir<%and.red.next> -; CHECK-NEXT: EMIT vp<[[WIDEN_CAN:%.+]]> = WIDEN-CANONICAL-INDUCTION vp<[[CAN_IV]]> -; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule vp<[[WIDEN_CAN]]>, vp<[[BTC]]> -; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur>, ir<%recur.next> -; CHECK-NEXT: Successor(s): pred.srem -; CHECK-EMPTY: -; CHECK-NEXT: pred.srem: { -; CHECK-NEXT: pred.srem.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> -; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.srem.if: -; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> -; CHECK-NEXT: Successor(s): pred.srem.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.srem.continue: -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%8> = ir<%rem> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.0 -; CHECK-EMPTY: -; CHECK-NEXT: loop.0: -; CHECK-NEXT: WIDEN ir<%add> = add vp<%8>, ir<%recur.next> -; CHECK-NEXT: WIDEN ir<%and.red.next> = and ir<%and.red>, ir<%add> -; CHECK-NEXT: EMIT vp<[[SEL:%.+]]> = select vp<%6>, ir<%and.red.next>, ir<%and.red> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RED_RES:%.+]]> = compute-reduction-result (and) vp<[[SEL]]> -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: IR %res = phi i32 [ %and.red.next, %loop ] (extra operand: vp<[[RED_RES]]> from middle.block) -; CHECK-NEXT: No successors +; CHECK-LABEL: 'sink_replicate_region_3_reduction' +; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = backedge-taken count +; CHECK-NEXT: Live-in ir<20001> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<1234>, ir<-1>, ir<1> +; CHECK-NEXT: WIDEN-CAST ir<%recur.next> = sext ir<%y> to i32 +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%and.red> = phi vp<[[VP3]]>, ir<%and.red.next> +; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = WIDEN-CANONICAL-INDUCTION vp<[[VP4]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = icmp ule vp<[[VP5]]>, vp<[[VP2]]> +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = first-order splice ir<%recur>, ir<%recur.next> +; CHECK-NEXT: Successor(s): pred.srem +; CHECK-EMPTY: +; CHECK-NEXT: pred.srem: { +; CHECK-NEXT: pred.srem.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP6]]> +; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.srem.if: +; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[VP7]]>, ir<%x> (S->V) +; CHECK-NEXT: Successor(s): pred.srem.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.srem.continue: +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP8:%[0-9]+]]> = ir<%rem> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): loop.0 +; CHECK-EMPTY: +; CHECK-NEXT: loop.0: +; CHECK-NEXT: WIDEN ir<%add> = add vp<[[VP8]]>, ir<%recur.next> +; CHECK-NEXT: WIDEN ir<%and.red.next> = and ir<%and.red>, ir<%add> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP0]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP1]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = select vp<[[VP6]]>, ir<%and.red.next>, ir<%and.red> +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = compute-reduction-result (and) vp<[[VP10]]> +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %res = phi i32 [ %and.red.next, %loop ] (extra operand: vp<[[VP11]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ ir<1234>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %and.red = phi i32 [ 1234, %entry ], [ %and.red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %rem = srem i32 %recur, %x +; CHECK-NEXT: IR %recur.next = sext i8 %y to i32 +; CHECK-NEXT: IR %add = add i32 %rem, %recur.next +; CHECK-NEXT: IR %and.red.next = and i32 %and.red, %add +; CHECK-NEXT: IR %iv.next = add nsw i32 %iv, 1 +; CHECK-NEXT: IR %ec = icmp eq i32 %iv.next, 20001 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -268,100 +321,123 @@ exit: ; To sink the replicate region containing %rem, we need to split the block ; containing %conv at the end, because %conv is the last recipe in the block. define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, ptr %ptr, ptr noalias %dst) optsize { -; CHECK-LABEL: sink_replicate_region_4_requires_split_at_end_of_block -; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count -; CHECK-NEXT: Live-in ir<20001> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv> -; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]> -; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: Successor(s): pred.load -; CHECK-EMPTY: -; CHECK-NEXT: pred.load: { -; CHECK-NEXT: pred.load.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> -; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.load.if: -; CHECK-NEXT: REPLICATE ir<%lv> = load ir<%gep> (S->V) -; CHECK-NEXT: Successor(s): pred.load.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.load.continue: -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%lv> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.0 -; CHECK-EMPTY: -; CHECK-NEXT: loop.0: -; CHECK-NEXT: WIDEN-CAST ir<%conv> = sext vp<[[PRED]]> to i32 -; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%0>, ir<%conv> -; CHECK-NEXT: Successor(s): pred.load -; CHECK-EMPTY: -; CHECK: pred.load: { -; CHECK-NEXT: pred.load.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> -; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue -; CHECK-EMPTY: -; CHECK: pred.load.if: -; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> -; CHECK-NEXT: REPLICATE ir<%lv.2> = load ir<%gep> (S->V) -; CHECK-NEXT: Successor(s): pred.load.continue -; CHECK-EMPTY: -; CHECK: pred.load.continue: -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[REMPHI:%.+]]> = ir<%rem> -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%10> = ir<%lv.2> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.2 -; CHECK-EMPTY: -; CHECK-NEXT: loop.2: -; CHECK-NEXT: WIDEN ir<%add.1> = add ir<%conv>, vp<[[REMPHI]]> -; CHECK-NEXT: WIDEN-CAST ir<%conv.lv.2> = sext vp<%10> to i32 -; CHECK-NEXT: WIDEN ir<%add> = add ir<%add.1>, ir<%conv.lv.2> -; CHECK-NEXT: Successor(s): pred.store -; CHECK-EMPTY: -; CHECK-NEXT: pred.store: { -; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> -; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.if: -; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr ir<%dst>, vp<[[STEPS]]> -; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep.dst> -; CHECK-NEXT: Successor(s): pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.continue: +; CHECK-LABEL: 'sink_replicate_region_4_requires_split_at_end_of_block' +; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in vp<[[VP3:%[0-9]+]]> = backedge-taken count +; CHECK-NEXT: Live-in ir<20001> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%0> = phi ir<0>, ir<%conv> +; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = icmp ule ir<%iv>, vp<[[VP3]]> +; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[VP5]]> +; CHECK-NEXT: Successor(s): pred.load +; CHECK-EMPTY: +; CHECK-NEXT: pred.load: { +; CHECK-NEXT: pred.load.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP6]]> +; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.load.if: +; CHECK-NEXT: REPLICATE ir<%lv> = load ir<%gep> (S->V) +; CHECK-NEXT: Successor(s): pred.load.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.load.continue: +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP7:%[0-9]+]]> = ir<%lv> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): loop.0 +; CHECK-EMPTY: +; CHECK-NEXT: loop.0: +; CHECK-NEXT: WIDEN-CAST ir<%conv> = sext vp<[[VP7]]> to i32 +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = first-order splice ir<%0>, ir<%conv> +; CHECK-NEXT: Successor(s): pred.load +; CHECK-EMPTY: +; CHECK-NEXT: pred.load: { +; CHECK-NEXT: pred.load.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP6]]> +; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.load.if: +; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[VP8]]>, ir<%x> (S->V) +; CHECK-NEXT: REPLICATE ir<%lv.2> = load ir<%gep> (S->V) +; CHECK-NEXT: Successor(s): pred.load.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.load.continue: +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP9:%[0-9]+]]> = ir<%rem> +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP10:%[0-9]+]]> = ir<%lv.2> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): loop.2 +; CHECK-EMPTY: +; CHECK-NEXT: loop.2: +; CHECK-NEXT: WIDEN ir<%add.1> = add ir<%conv>, vp<[[VP9]]> +; CHECK-NEXT: WIDEN-CAST ir<%conv.lv.2> = sext vp<[[VP10]]> to i32 +; CHECK-NEXT: WIDEN ir<%add> = add ir<%add.1>, ir<%conv.lv.2> +; CHECK-NEXT: Successor(s): pred.store +; CHECK-EMPTY: +; CHECK-NEXT: pred.store: { +; CHECK-NEXT: pred.store.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP6]]> +; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.if: +; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr ir<%dst>, vp<[[VP5]]> +; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep.dst> +; CHECK-NEXT: Successor(s): pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.continue: +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): loop.3 +; CHECK-EMPTY: +; CHECK-NEXT: loop.3: +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.3 -; CHECK-EMPTY: -; CHECK: loop.3: -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %0 = phi i32 [ 0, %entry ], [ %conv, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep = getelementptr i8, ptr %ptr, i32 %iv +; CHECK-NEXT: IR %rem = srem i32 %0, %x +; CHECK-NEXT: IR %lv = load i8, ptr %gep, align 1 +; CHECK-NEXT: IR %conv = sext i8 %lv to i32 +; CHECK-NEXT: IR %lv.2 = load i8, ptr %gep, align 1 +; CHECK-NEXT: IR %add.1 = add i32 %conv, %rem +; CHECK-NEXT: IR %conv.lv.2 = sext i8 %lv.2 to i32 +; CHECK-NEXT: IR %add = add i32 %add.1, %conv.lv.2 +; CHECK-NEXT: IR %gep.dst = getelementptr i32, ptr %dst, i32 %iv +; CHECK-NEXT: IR store i32 %add, ptr %gep.dst, align 4 +; CHECK-NEXT: IR %iv.next = add nsw i32 %iv, 1 +; CHECK-NEXT: IR %ec = icmp eq i32 %iv.next, 20001 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -389,63 +465,83 @@ exit: ; Test case that requires sinking a recipe in a replicate region after another replicate region. define void @sink_replicate_region_after_replicate_region(ptr %ptr, ptr noalias %dst.2, i32 %x, i8 %y) optsize { -; CHECK-LABEL: sink_replicate_region_after_replicate_region -; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count -; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (1 smax (1 + (sext i8 %y to i32))) -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: WIDEN-CAST ir<%recur.next> = sext ir<%y> to i32 -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> -; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]> -; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur>, ir<%recur.next> -; CHECK-NEXT: Successor(s): pred.store -; CHECK-EMPTY: -; CHECK-NEXT: pred.store: { -; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]> -; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.if: -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x> -; CHECK-NEXT: REPLICATE ir<%rem.div> = sdiv ir<20>, ir<%rem> -; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: REPLICATE store ir<%rem.div>, ir<%gep> -; CHECK-NEXT: REPLICATE ir<%gep.2> = getelementptr ir<%dst.2>, vp<[[STEPS]]> -; CHECK-NEXT: REPLICATE store ir<%rem.div>, ir<%gep.2> -; CHECK-NEXT: Successor(s): pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.continue: -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.3 -; CHECK-EMPTY: -; CHECK-NEXT: loop.3: -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors +; CHECK-LABEL: 'sink_replicate_region_after_replicate_region' +; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in vp<[[VP3:%[0-9]+]]> = backedge-taken count +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: EMIT vp<[[VP4]]> = EXPAND SCEV (1 smax (1 + (sext i8 %y to i32))) +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: WIDEN-CAST ir<%recur.next> = sext ir<%y> to i32 +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%recur> = phi ir<0>, ir<%recur.next> +; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = icmp ule ir<%iv>, vp<[[VP3]]> +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = first-order splice ir<%recur>, ir<%recur.next> +; CHECK-NEXT: Successor(s): pred.store +; CHECK-EMPTY: +; CHECK-NEXT: pred.store: { +; CHECK-NEXT: pred.store.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP6]]> +; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.if: +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = SCALAR-STEPS vp<[[VP5]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[VP7]]>, ir<%x> +; CHECK-NEXT: REPLICATE ir<%rem.div> = sdiv ir<20>, ir<%rem> +; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[VP8]]> +; CHECK-NEXT: REPLICATE store ir<%rem.div>, ir<%gep> +; CHECK-NEXT: REPLICATE ir<%gep.2> = getelementptr ir<%dst.2>, vp<[[VP8]]> +; CHECK-NEXT: REPLICATE store ir<%rem.div>, ir<%gep.2> +; CHECK-NEXT: Successor(s): pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.continue: +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): loop.3 +; CHECK-EMPTY: +; CHECK-NEXT: loop.3: +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %recur = phi i32 [ 0, %entry ], [ %recur.next, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rem = srem i32 %recur, %x +; CHECK-NEXT: IR %rem.div = sdiv i32 20, %rem +; CHECK-NEXT: IR %recur.next = sext i8 %y to i32 +; CHECK-NEXT: IR %gep = getelementptr i32, ptr %ptr, i32 %iv +; CHECK-NEXT: IR store i32 %rem.div, ptr %gep, align 4 +; CHECK-NEXT: IR %gep.2 = getelementptr i32, ptr %dst.2, i32 %iv +; CHECK-NEXT: IR store i32 %rem.div, ptr %gep.2, align 4 +; CHECK-NEXT: IR %iv.next = add nsw i32 %iv, 1 +; CHECK-NEXT: IR %C = icmp sgt i32 %iv.next, %recur.next +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -469,60 +565,77 @@ exit: ; preds = %loop } define void @need_new_block_after_sinking_pr56146(i32 %x, ptr %src, ptr noalias %dst) { -; CHECK-LABEL: need_new_block_after_sinking_pr56146 -; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in vp<[[BTC:%.+]]> = backedge-taken count -; CHECK-NEXT: Live-in ir<3> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%.pn> = phi ir<0>, ir<[[L:%.+]]> -; CHECK-NEXT: vp<[[DERIVED_IV:%.+]]> = DERIVED-IV ir<2> + vp<[[CAN_IV]]> * ir<1> -; CHECK-NEXT: EMIT vp<[[WIDE_IV:%.+]]> = WIDEN-CANONICAL-INDUCTION vp<[[CAN_IV]]> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp ule vp<[[WIDE_IV]]>, vp<[[BTC]]> -; CHECK-NEXT: CLONE ir<[[L]]> = load ir<%src> -; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%.pn>, ir<[[L]]> -; CHECK-NEXT: Successor(s): pred.store -; CHECK-EMPTY: -; CHECK-NEXT: pred.store: { -; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[CMP]]> -; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.if: -; CHECK-NEXT: REPLICATE ir<%val> = sdiv vp<[[SPLICE]]>, ir<%x> -; CHECK-NEXT: vp<[[SCALAR_STEPS:%.+]]> = SCALAR-STEPS vp<[[DERIVED_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr ir<%dst>, vp<[[SCALAR_STEPS]]> -; CHECK-NEXT: REPLICATE store ir<%val>, ir<%gep.dst> -; CHECK-NEXT: Successor(s): pred.store.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.store.continue: -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): loop.1 -; CHECK-EMPTY: -; CHECK-NEXT: loop.1: -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors +; CHECK-LABEL: 'need_new_block_after_sinking_pr56146' +; CHECK: VPlan 'Initial VPlan for VF={2},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in vp<[[VP3:%[0-9]+]]> = backedge-taken count +; CHECK-NEXT: Live-in ir<3> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%.pn> = phi ir<0>, ir<%l> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = DERIVED-IV ir<2> + vp<[[VP4]]> * ir<1> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = WIDEN-CANONICAL-INDUCTION vp<[[VP4]]> +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = icmp ule vp<[[VP6]]>, vp<[[VP3]]> +; CHECK-NEXT: CLONE ir<%l> = load ir<%src> +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = first-order splice ir<%.pn>, ir<%l> +; CHECK-NEXT: Successor(s): pred.store +; CHECK-EMPTY: +; CHECK-NEXT: pred.store: { +; CHECK-NEXT: pred.store.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP7]]> +; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.if: +; CHECK-NEXT: REPLICATE ir<%val> = sdiv vp<[[VP8]]>, ir<%x> +; CHECK-NEXT: vp<[[VP9:%[0-9]+]]> = SCALAR-STEPS vp<[[VP5]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr ir<%dst>, vp<[[VP9]]> +; CHECK-NEXT: REPLICATE store ir<%val>, ir<%gep.dst> +; CHECK-NEXT: Successor(s): pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.continue: +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): loop.1 +; CHECK-EMPTY: +; CHECK-NEXT: loop.1: +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ ir<2>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ 2, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %.pn = phi i32 [ 0, %entry ], [ %l, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %val = sdiv i32 %.pn, %x +; CHECK-NEXT: IR %l = load i32, ptr %src, align 4 +; CHECK-NEXT: IR %gep.dst = getelementptr i32, ptr %dst, i64 %iv +; CHECK-NEXT: IR store i32 %val, ptr %gep.dst, align 4 +; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 1 +; CHECK-NEXT: IR %ec = icmp ugt i64 %iv, 3 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll index 063f47ce2b32d..c98ee8b6765ae 100644 --- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll +++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll @@ -924,12 +924,11 @@ define i32 @PR27246() { ; UNROLL-NO-VF-NEXT: br label [[VECTOR_BODY:%.*]] ; UNROLL-NO-VF: vector.body: ; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; UNROLL-NO-VF-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[I_016]], [[INDEX]] -; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = add i32 [[OFFSET_IDX]], -1 ; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-VF-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; UNROLL-NO-VF: middle.block: +; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = sub i32 [[I_016]], [[INDEX]] ; UNROLL-NO-VF-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[I_016]], [[N_VEC]] ; UNROLL-NO-VF-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP3]], label [[SCALAR_PH]] ; UNROLL-NO-VF: scalar.ph: @@ -946,7 +945,7 @@ define i32 @PR27246() { ; UNROLL-NO-VF-NEXT: [[DEC]] = add nsw i32 [[K_0]], -1 ; UNROLL-NO-VF-NEXT: br i1 [[CMP2]], label [[FOR_COND1]], label [[FOR_COND_CLEANUP3]], !llvm.loop [[LOOP9:![0-9]+]] ; UNROLL-NO-VF: for.cond.cleanup3: -; UNROLL-NO-VF-NEXT: [[E_1_LCSSA]] = phi i32 [ [[E_1]], [[FOR_COND1]] ], [ [[OFFSET_IDX]], [[MIDDLE_BLOCK]] ] +; UNROLL-NO-VF-NEXT: [[E_1_LCSSA]] = phi i32 [ [[E_1]], [[FOR_COND1]] ], [ [[TMP1]], [[MIDDLE_BLOCK]] ] ; UNROLL-NO-VF-NEXT: [[INC]] = add nuw nsw i32 [[I_016]], 1 ; UNROLL-NO-VF-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INC]], 49 ; UNROLL-NO-VF-NEXT: br i1 [[EXITCOND]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]] @@ -1264,12 +1263,12 @@ define i32 @extract_second_last_iteration(ptr %cval, i32 %x, i32 %n) { ; UNROLL-NO-IC-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; UNROLL-NO-IC-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; UNROLL-NO-IC-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) -; UNROLL-NO-IC-NEXT: [[TMP0:%.*]] = add <4 x i32> [[STEP_ADD]], [[BROADCAST_SPLAT]] ; UNROLL-NO-IC-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 ; UNROLL-NO-IC-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) ; UNROLL-NO-IC-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-IC-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] ; UNROLL-NO-IC: middle.block: +; UNROLL-NO-IC-NEXT: [[TMP0:%.*]] = add <4 x i32> [[STEP_ADD]], [[BROADCAST_SPLAT]] ; UNROLL-NO-IC-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 ; UNROLL-NO-IC-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2 ; UNROLL-NO-IC-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]] @@ -1340,12 +1339,12 @@ define i32 @extract_second_last_iteration(ptr %cval, i32 %x, i32 %n) { ; SINK-AFTER: vector.body: ; SINK-AFTER-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; SINK-AFTER-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] -; SINK-AFTER-NEXT: [[TMP0:%.*]] = add <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; SINK-AFTER-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; SINK-AFTER-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) ; SINK-AFTER-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; SINK-AFTER-NEXT: br i1 [[TMP2]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] ; SINK-AFTER: middle.block: +; SINK-AFTER-NEXT: [[TMP0:%.*]] = add <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; SINK-AFTER-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 ; SINK-AFTER-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2 ; SINK-AFTER-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]] @@ -2441,7 +2440,6 @@ define void @sink_dead_inst(ptr %a) { ; UNROLL-NO-IC-NEXT: [[OFFSET_IDX:%.*]] = add i16 -27, [[DOTCAST]] ; UNROLL-NO-IC-NEXT: [[TMP1:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 1) ; UNROLL-NO-IC-NEXT: [[TMP2:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) -; UNROLL-NO-IC-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i32> ; UNROLL-NO-IC-NEXT: [[TMP4:%.*]] = add <4 x i16> [[TMP1]], splat (i16 5) ; UNROLL-NO-IC-NEXT: [[TMP5]] = add <4 x i16> [[TMP2]], splat (i16 5) ; UNROLL-NO-IC-NEXT: [[TMP6:%.*]] = shufflevector <4 x i16> [[VECTOR_RECUR]], <4 x i16> [[TMP4]], <4 x i32> @@ -2457,6 +2455,7 @@ define void @sink_dead_inst(ptr %a) { ; UNROLL-NO-IC-NEXT: [[TMP13:%.*]] = icmp eq i32 [[INDEX_NEXT]], 40 ; UNROLL-NO-IC-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]] ; UNROLL-NO-IC: middle.block: +; UNROLL-NO-IC-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i32> ; UNROLL-NO-IC-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i16> [[TMP5]], i32 3 ; UNROLL-NO-IC-NEXT: [[VECTOR_RECUR_EXTRACT2:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3 ; UNROLL-NO-IC-NEXT: br label [[SCALAR_PH:%.*]] @@ -2533,7 +2532,6 @@ define void @sink_dead_inst(ptr %a) { ; SINK-AFTER-NEXT: [[DOTCAST:%.*]] = trunc i32 [[INDEX]] to i16 ; SINK-AFTER-NEXT: [[OFFSET_IDX:%.*]] = add i16 -27, [[DOTCAST]] ; SINK-AFTER-NEXT: [[TMP1:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 1) -; SINK-AFTER-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32> ; SINK-AFTER-NEXT: [[TMP3]] = add <4 x i16> [[TMP1]], splat (i16 5) ; SINK-AFTER-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[VECTOR_RECUR]], <4 x i16> [[TMP3]], <4 x i32> ; SINK-AFTER-NEXT: [[TMP5:%.*]] = sub <4 x i16> [[TMP4]], splat (i16 10) @@ -2544,6 +2542,7 @@ define void @sink_dead_inst(ptr %a) { ; SINK-AFTER-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 40 ; SINK-AFTER-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]] ; SINK-AFTER: middle.block: +; SINK-AFTER-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32> ; SINK-AFTER-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i16> [[TMP3]], i32 3 ; SINK-AFTER-NEXT: [[VECTOR_RECUR_EXTRACT2:%.*]] = extractelement <4 x i32> [[TMP2]], i32 3 ; SINK-AFTER-NEXT: br label [[SCALAR_PH:%.*]] @@ -2687,12 +2686,12 @@ define i32 @sink_into_replication_region(i32 %y) { ; UNROLL-NO-IC-NEXT: [[TMP45:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> [[TMP43]], <4 x i32> ; UNROLL-NO-IC-NEXT: [[TMP46]] = add <4 x i32> [[VEC_PHI]], [[TMP44]] ; UNROLL-NO-IC-NEXT: [[TMP47]] = add <4 x i32> [[VEC_PHI1]], [[TMP45]] -; UNROLL-NO-IC-NEXT: [[TMP48:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[TMP46]], <4 x i32> [[VEC_PHI]] -; UNROLL-NO-IC-NEXT: [[TMP49:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP47]], <4 x i32> [[VEC_PHI1]] ; UNROLL-NO-IC-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 ; UNROLL-NO-IC-NEXT: [[TMP50:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-IC-NEXT: br i1 [[TMP50]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !prof [[PROF25:![0-9]+]], !llvm.loop [[LOOP26:![0-9]+]] ; UNROLL-NO-IC: middle.block: +; UNROLL-NO-IC-NEXT: [[TMP48:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[TMP46]], <4 x i32> [[VEC_PHI]] +; UNROLL-NO-IC-NEXT: [[TMP49:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP47]], <4 x i32> [[VEC_PHI1]] ; UNROLL-NO-IC-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP49]], [[TMP48]] ; UNROLL-NO-IC-NEXT: [[TMP51:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]]) ; UNROLL-NO-IC-NEXT: br label [[BB2:%.*]] @@ -2736,12 +2735,12 @@ define i32 @sink_into_replication_region(i32 %y) { ; UNROLL-NO-VF-NEXT: [[TMP9]] = phi i32 [ poison, [[PRED_UDIV_CONTINUE]] ], [ [[TMP8]], [[PRED_UDIV_IF3]] ] ; UNROLL-NO-VF-NEXT: [[TMP10]] = add i32 [[VEC_PHI]], [[VECTOR_RECUR]] ; UNROLL-NO-VF-NEXT: [[TMP11]] = add i32 [[VEC_PHI1]], [[TMP6]] -; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = select i1 [[TMP2]], i32 [[TMP10]], i32 [[VEC_PHI]] -; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = select i1 [[TMP3]], i32 [[TMP11]], i32 [[VEC_PHI1]] ; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; UNROLL-NO-VF-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-VF-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !prof [[PROF25:![0-9]+]], !llvm.loop [[LOOP26:![0-9]+]] ; UNROLL-NO-VF: middle.block: +; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = select i1 [[TMP2]], i32 [[TMP10]], i32 [[VEC_PHI]] +; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = select i1 [[TMP3]], i32 [[TMP11]], i32 [[VEC_PHI1]] ; UNROLL-NO-VF-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP13]], [[TMP12]] ; UNROLL-NO-VF-NEXT: br label [[BB2:%.*]] ; UNROLL-NO-VF: bb1: @@ -2808,11 +2807,11 @@ define i32 @sink_into_replication_region(i32 %y) { ; SINK-AFTER-NEXT: [[TMP22]] = phi <4 x i32> [ [[TMP17]], [[PRED_UDIV_CONTINUE6]] ], [ [[TMP21]], [[PRED_UDIV_IF7]] ] ; SINK-AFTER-NEXT: [[TMP23:%.*]] = shufflevector <4 x i32> [[VECTOR_RECUR]], <4 x i32> [[TMP22]], <4 x i32> ; SINK-AFTER-NEXT: [[TMP24]] = add <4 x i32> [[VEC_PHI]], [[TMP23]] -; SINK-AFTER-NEXT: [[TMP25:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[TMP24]], <4 x i32> [[VEC_PHI]] ; SINK-AFTER-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; SINK-AFTER-NEXT: [[TMP26:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; SINK-AFTER-NEXT: br i1 [[TMP26]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !prof [[PROF25:![0-9]+]], !llvm.loop [[LOOP26:![0-9]+]] ; SINK-AFTER: middle.block: +; SINK-AFTER-NEXT: [[TMP25:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[TMP24]], <4 x i32> [[VEC_PHI]] ; SINK-AFTER-NEXT: [[TMP27:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP25]]) ; SINK-AFTER-NEXT: br label [[BB2:%.*]] ; SINK-AFTER: bb1: @@ -3003,13 +3002,13 @@ define i32 @sink_into_replication_region_multiple(ptr %x, i32 %y) { ; UNROLL-NO-IC-NEXT: store i32 [[TMP9]], ptr [[TMP71]], align 4 ; UNROLL-NO-IC-NEXT: br label [[PRED_STORE_CONTINUE29]] ; UNROLL-NO-IC: pred.store.continue29: -; UNROLL-NO-IC-NEXT: [[TMP72:%.*]] = select <4 x i1> [[TMP10]], <4 x i32> [[TMP46]], <4 x i32> [[VEC_PHI]] -; UNROLL-NO-IC-NEXT: [[TMP73:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP47]], <4 x i32> [[VEC_PHI1]] ; UNROLL-NO-IC-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 ; UNROLL-NO-IC-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) ; UNROLL-NO-IC-NEXT: [[TMP74:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-IC-NEXT: br i1 [[TMP74]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !prof [[PROF25]], !llvm.loop [[LOOP28:![0-9]+]] ; UNROLL-NO-IC: middle.block: +; UNROLL-NO-IC-NEXT: [[TMP72:%.*]] = select <4 x i1> [[TMP10]], <4 x i32> [[TMP46]], <4 x i32> [[VEC_PHI]] +; UNROLL-NO-IC-NEXT: [[TMP73:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP47]], <4 x i32> [[VEC_PHI1]] ; UNROLL-NO-IC-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP73]], [[TMP72]] ; UNROLL-NO-IC-NEXT: [[TMP75:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]]) ; UNROLL-NO-IC-NEXT: br label [[BB2:%.*]] @@ -3066,12 +3065,12 @@ define i32 @sink_into_replication_region_multiple(ptr %x, i32 %y) { ; UNROLL-NO-VF-NEXT: store i32 [[TMP3]], ptr [[TMP15]], align 4 ; UNROLL-NO-VF-NEXT: br label [[PRED_STORE_CONTINUE6]] ; UNROLL-NO-VF: pred.store.continue6: -; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = select i1 [[TMP4]], i32 [[TMP10]], i32 [[VEC_PHI]] -; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = select i1 [[TMP5]], i32 [[TMP11]], i32 [[VEC_PHI1]] ; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; UNROLL-NO-VF-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-VF-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !prof [[PROF25]], !llvm.loop [[LOOP28:![0-9]+]] ; UNROLL-NO-VF: middle.block: +; UNROLL-NO-VF-NEXT: [[TMP16:%.*]] = select i1 [[TMP4]], i32 [[TMP10]], i32 [[VEC_PHI]] +; UNROLL-NO-VF-NEXT: [[TMP17:%.*]] = select i1 [[TMP5]], i32 [[TMP11]], i32 [[VEC_PHI1]] ; UNROLL-NO-VF-NEXT: [[BIN_RDX:%.*]] = add i32 [[TMP17]], [[TMP16]] ; UNROLL-NO-VF-NEXT: br label [[BB2:%.*]] ; UNROLL-NO-VF: bb1: @@ -3168,12 +3167,12 @@ define i32 @sink_into_replication_region_multiple(ptr %x, i32 %y) { ; SINK-AFTER-NEXT: store i32 [[TMP5]], ptr [[TMP36]], align 4 ; SINK-AFTER-NEXT: br label [[PRED_STORE_CONTINUE12]] ; SINK-AFTER: pred.store.continue12: -; SINK-AFTER-NEXT: [[TMP37:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP24]], <4 x i32> [[VEC_PHI]] ; SINK-AFTER-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; SINK-AFTER-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) ; SINK-AFTER-NEXT: [[TMP38:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; SINK-AFTER-NEXT: br i1 [[TMP38]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !prof [[PROF25]], !llvm.loop [[LOOP28:![0-9]+]] ; SINK-AFTER: middle.block: +; SINK-AFTER-NEXT: [[TMP37:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP24]], <4 x i32> [[VEC_PHI]] ; SINK-AFTER-NEXT: [[TMP39:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP37]]) ; SINK-AFTER-NEXT: br label [[BB2:%.*]] ; SINK-AFTER: bb1: @@ -3214,9 +3213,6 @@ define i32 @sink_after_dead_inst(ptr %A.ptr, i32 %n) { ; UNROLL-NO-IC-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; UNROLL-NO-IC-NEXT: [[STEP_ADD:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 4) ; UNROLL-NO-IC-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16 -; UNROLL-NO-IC-NEXT: [[TMP1:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) -; UNROLL-NO-IC-NEXT: [[TMP2:%.*]] = or <4 x i16> [[TMP1]], [[TMP1]] -; UNROLL-NO-IC-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i32> ; UNROLL-NO-IC-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[A_PTR:%.*]], i16 [[OFFSET_IDX]] ; UNROLL-NO-IC-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP4]], i64 4 ; UNROLL-NO-IC-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP4]], align 4 @@ -3226,6 +3222,9 @@ define i32 @sink_after_dead_inst(ptr %A.ptr, i32 %n) { ; UNROLL-NO-IC-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 ; UNROLL-NO-IC-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP29:![0-9]+]] ; UNROLL-NO-IC: middle.block: +; UNROLL-NO-IC-NEXT: [[TMP5:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) +; UNROLL-NO-IC-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP5]], [[TMP5]] +; UNROLL-NO-IC-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP8]] to <4 x i32> ; UNROLL-NO-IC-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2 ; UNROLL-NO-IC-NEXT: br label [[LOOP:%.*]] ; UNROLL-NO-IC: for.end: @@ -3239,12 +3238,12 @@ define i32 @sink_after_dead_inst(ptr %A.ptr, i32 %n) { ; UNROLL-NO-VF: vector.body: ; UNROLL-NO-VF-NEXT: [[VECTOR_RECUR:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP7:%.*]], [[VECTOR_BODY]] ] ; UNROLL-NO-VF-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[VECTOR_RECUR]] to i16 -; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = add i16 [[OFFSET_IDX]], 1 ; UNROLL-NO-VF-NEXT: [[TMP3:%.*]] = add i16 [[OFFSET_IDX]], 1 -; UNROLL-NO-VF-NEXT: [[TMP5:%.*]] = or i16 [[TMP3]], [[TMP3]] -; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = zext i16 [[TMP5]] to i32 +; UNROLL-NO-VF-NEXT: [[TMP1:%.*]] = add i16 [[OFFSET_IDX]], 1 +; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = or i16 [[TMP1]], [[TMP1]] +; UNROLL-NO-VF-NEXT: [[TMP10:%.*]] = zext i16 [[TMP2]] to i32 ; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[A_PTR:%.*]], i16 [[OFFSET_IDX]] -; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[A_PTR]], i16 [[TMP2]] +; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[A_PTR]], i16 [[TMP3]] ; UNROLL-NO-VF-NEXT: store i32 0, ptr [[TMP8]], align 4 ; UNROLL-NO-VF-NEXT: store i32 0, ptr [[TMP9]], align 4 ; UNROLL-NO-VF-NEXT: [[TMP7]] = add nuw i32 [[VECTOR_RECUR]], 2 @@ -3264,9 +3263,6 @@ define i32 @sink_after_dead_inst(ptr %A.ptr, i32 %n) { ; SINK-AFTER-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; SINK-AFTER-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; SINK-AFTER-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16 -; SINK-AFTER-NEXT: [[TMP1:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 1) -; SINK-AFTER-NEXT: [[TMP2:%.*]] = or <4 x i16> [[TMP1]], [[TMP1]] -; SINK-AFTER-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i32> ; SINK-AFTER-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[A_PTR:%.*]], i16 [[OFFSET_IDX]] ; SINK-AFTER-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP4]], align 4 ; SINK-AFTER-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 @@ -3274,6 +3270,9 @@ define i32 @sink_after_dead_inst(ptr %A.ptr, i32 %n) { ; SINK-AFTER-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16 ; SINK-AFTER-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP29:![0-9]+]] ; SINK-AFTER: middle.block: +; SINK-AFTER-NEXT: [[TMP2:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 1) +; SINK-AFTER-NEXT: [[TMP5:%.*]] = or <4 x i16> [[TMP2]], [[TMP2]] +; SINK-AFTER-NEXT: [[TMP3:%.*]] = zext <4 x i16> [[TMP5]] to <4 x i32> ; SINK-AFTER-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2 ; SINK-AFTER-NEXT: br label [[LOOP:%.*]] ; SINK-AFTER: for.end: @@ -3322,13 +3321,13 @@ define void @unused_recurrence(ptr %a, i16 %n) { ; UNROLL-NO-IC-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; UNROLL-NO-IC-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; UNROLL-NO-IC-NEXT: [[STEP_ADD:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 4) -; UNROLL-NO-IC-NEXT: [[TMP0:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) -; UNROLL-NO-IC-NEXT: [[TMP1:%.*]] = add <4 x i16> [[TMP0]], splat (i16 5) ; UNROLL-NO-IC-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8 ; UNROLL-NO-IC-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[STEP_ADD]], splat (i16 4) ; UNROLL-NO-IC-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-IC-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]] ; UNROLL-NO-IC: middle.block: +; UNROLL-NO-IC-NEXT: [[TMP7:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1) +; UNROLL-NO-IC-NEXT: [[TMP1:%.*]] = add <4 x i16> [[TMP7]], splat (i16 5) ; UNROLL-NO-IC-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3 ; UNROLL-NO-IC-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]] ; UNROLL-NO-IC-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]] @@ -3364,9 +3363,9 @@ define void @unused_recurrence(ptr %a, i16 %n) { ; UNROLL-NO-VF-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; UNROLL-NO-VF-NEXT: [[DOTCAST2:%.*]] = trunc i32 [[INDEX]] to i16 ; UNROLL-NO-VF-NEXT: [[OFFSET_IDX:%.*]] = add i16 -27, [[DOTCAST2]] -; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = add i16 [[OFFSET_IDX]], 1 -; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = add i16 [[TMP8]], 1 -; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = add i16 [[TMP9]], 5 +; UNROLL-NO-VF-NEXT: [[TMP9:%.*]] = add i16 [[OFFSET_IDX]], 1 +; UNROLL-NO-VF-NEXT: [[TMP8:%.*]] = add i16 [[TMP9]], 1 +; UNROLL-NO-VF-NEXT: [[TMP2:%.*]] = add i16 [[TMP8]], 5 ; UNROLL-NO-VF-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; UNROLL-NO-VF-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; UNROLL-NO-VF-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]] @@ -3404,13 +3403,13 @@ define void @unused_recurrence(ptr %a, i16 %n) { ; SINK-AFTER: vector.body: ; SINK-AFTER-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; SINK-AFTER-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] -; SINK-AFTER-NEXT: [[TMP7:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 1) -; SINK-AFTER-NEXT: [[TMP1:%.*]] = add <4 x i16> [[TMP7]], splat (i16 5) ; SINK-AFTER-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; SINK-AFTER-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[VEC_IND]], splat (i16 4) ; SINK-AFTER-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; SINK-AFTER-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]] ; SINK-AFTER: middle.block: +; SINK-AFTER-NEXT: [[TMP7:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 1) +; SINK-AFTER-NEXT: [[TMP1:%.*]] = add <4 x i16> [[TMP7]], splat (i16 5) ; SINK-AFTER-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i16> [[TMP1]], i32 3 ; SINK-AFTER-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]] ; SINK-AFTER-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[SCALAR_PH]] diff --git a/llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll b/llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll index aa7ee71b70fe6..bf03cfc2e8437 100644 --- a/llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll +++ b/llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll @@ -312,8 +312,6 @@ define float @fmaxnum_tailfold(ptr %src, i64 %n) #0 { ; CHECK-NEXT: [[TMP50:%.*]] = phi <4 x float> [ [[TMP44]], %[[PRED_LOAD_CONTINUE13]] ], [ [[TMP49]], %[[PRED_LOAD_IF14]] ] ; CHECK-NEXT: [[TMP51]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI]], <4 x float> [[TMP26]]) ; CHECK-NEXT: [[TMP52]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI1]], <4 x float> [[TMP50]]) -; CHECK-NEXT: [[TMP53:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[TMP51]], <4 x float> [[VEC_PHI]] -; CHECK-NEXT: [[TMP54:%.*]] = select <4 x i1> [[TMP2]], <4 x float> [[TMP52]], <4 x float> [[VEC_PHI1]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP55:%.*]] = fcmp uno <4 x float> [[TMP26]], [[TMP50]] ; CHECK-NEXT: [[TMP56:%.*]] = freeze <4 x i1> [[TMP55]] @@ -323,14 +321,15 @@ define float @fmaxnum_tailfold(ptr %src, i64 %n) #0 { ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) ; CHECK-NEXT: br i1 [[TMP59]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP53:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[TMP51]], <4 x float> [[VEC_PHI]] +; CHECK-NEXT: [[TMP54:%.*]] = select <4 x i1> [[TMP2]], <4 x float> [[TMP52]], <4 x float> [[VEC_PHI1]] ; CHECK-NEXT: [[TMP60:%.*]] = select i1 [[TMP57]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP53]] ; CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP57]], <4 x float> [[VEC_PHI1]], <4 x float> [[TMP54]] ; CHECK-NEXT: [[TMP62:%.*]] = select i1 [[TMP57]], i64 [[INDEX]], i64 [[N_VEC]] ; CHECK-NEXT: [[RDX_MINMAX:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP60]], <4 x float> [[TMP61]]) ; CHECK-NEXT: [[TMP63:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[RDX_MINMAX]]) ; CHECK-NEXT: [[TMP64:%.*]] = xor i1 [[TMP57]], true -; CHECK-NEXT: [[TMP65:%.*]] = and i1 true, [[TMP64]] -; CHECK-NEXT: br i1 [[TMP65]], label %[[EXIT:.*]], label %[[SCALAR_PH:.*]] +; CHECK-NEXT: br i1 [[TMP64]], label %[[EXIT:.*]], label %[[SCALAR_PH:.*]] ; CHECK: [[SCALAR_PH]]: ; CHECK-NEXT: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: diff --git a/llvm/test/Transforms/LoopVectorize/instruction-only-used-outside-of-loop.ll b/llvm/test/Transforms/LoopVectorize/instruction-only-used-outside-of-loop.ll index 6d56b72e370c0..01c9be50de708 100644 --- a/llvm/test/Transforms/LoopVectorize/instruction-only-used-outside-of-loop.ll +++ b/llvm/test/Transforms/LoopVectorize/instruction-only-used-outside-of-loop.ll @@ -12,11 +12,11 @@ define i32 @one_direct_branch(ptr %src) { ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i32> splat (i32 25500), [[WIDE_LOAD]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000 ; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i32> splat (i32 25500), [[WIDE_LOAD]] ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3 ; CHECK-NEXT: br label [[LOOP_LATCH:%.*]] ; CHECK: exit: @@ -53,11 +53,11 @@ define i32 @two_direct_branch(ptr %src) { ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i32> splat (i32 25500), [[WIDE_LOAD]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000 ; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i32> splat (i32 25500), [[WIDE_LOAD]] ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3 ; CHECK-NEXT: br label [[LOOP_LATCH:%.*]] ; CHECK: exit: @@ -101,14 +101,14 @@ define i32 @cond_branch(i32 %a, ptr %src) { ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC:%.*]], i32 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 -; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i32> splat (i32 25500), [[WIDE_LOAD]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[TMP3]], <4 x i32> splat (i32 10) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i32> [[VEC_IND]], splat (i32 4) ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000 ; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i32> splat (i32 25500), [[WIDE_LOAD]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP2]], <4 x i32> splat (i32 10) ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[PREDPHI]], i32 3 ; CHECK-NEXT: br label [[LOOP_LATCH:%.*]] ; CHECK: exit: diff --git a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll b/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll index c77afa870e2c1..82470d3db0a2f 100644 --- a/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll +++ b/llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll @@ -380,3 +380,55 @@ exit: ret void } +define void @pr179671(ptr align 8 dereferenceable(120) %p, ptr %a, i32 %b) { +; CHECK-LABEL: define void @pr179671( +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %vector.ph ], [ [[INDEX_NEXT:%.*]], %vector.body ] +; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi ptr [ %a, %vector.ph ], [ [[NEXT_GEP3:%.*]], %vector.body ] +; CHECK-NEXT: [[DOTCAST1:%.*]] = trunc i64 [[INDEX]] to i32 +; CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[DOTCAST1]], 3 +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 %b, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[OFFSET_IDX]], 3 +; CHECK-NEXT: [[OFFSET_IDX2:%.*]] = mul i64 [[INDEX]], 128 +; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX2]], 0 +; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX2]], 128 +; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr null, i64 [[TMP15]] +; CHECK-NEXT: [[NEXT_GEP3]] = getelementptr i8, ptr null, i64 [[TMP12]] +; CHECK-NEXT: store ptr [[VECTOR_RECUR]], ptr [[NEXT_GEP]], align 8 +; CHECK-NEXT: store ptr [[NEXT_GEP]], ptr [[NEXT_GEP3]], align 8 +; CHECK-NEXT: store ptr [[NEXT_GEP3]], ptr [[INV_PTR:%.*]], align 8 +; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[TMP11]], 3 +; CHECK-NEXT: store i32 [[TMP13]], ptr [[INV_PTR2:%.*]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC:%.*]] +; CHECK-NEXT: br i1 [[TMP14]], label %[[LOOP_1:.*]], label %vector.body +entry: + %inv_ptr = getelementptr inbounds nuw i8, ptr %p, i64 24 + %inv_ptr2 = getelementptr inbounds nuw i8, ptr %p, i64 40 + br label %loop.header + +loop.header: + %load23 = phi i32 [ %b, %entry ], [ %sadd_val, %loop.5 ] + %load12 = phi ptr [ %a, %entry ], [ %phi_ptr1, %loop.5 ] + %phi_ptr1 = phi ptr [ null, %entry ], [ %phi_ptr_next, %loop.5 ] + %phi_ptr_next = getelementptr i8, ptr %phi_ptr1, i64 128 + store ptr %load12, ptr %phi_ptr1, align 8 + br label %loop.3 + +loop.3: + store ptr %phi_ptr1, ptr %inv_ptr, align 8 + %sadd_val = add i32 %load23, 3 + %sadd_ov = icmp eq i32 %sadd_val, 8 + br i1 %sadd_ov, label %exit.0, label %loop.5 + +loop.5: + store i32 %sadd_val, ptr %inv_ptr2, align 8 + br label %loop.header + +exit.0: + store i32 0, ptr %p, align 4 + ret void + +exit: + ret void +} diff --git a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll index 6059b0244eba8..2a19ebdd77219 100644 --- a/llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll +++ b/llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll @@ -393,14 +393,14 @@ define i16 @select_decreasing_induction_icmp_table_i16(i16 noundef %val) { ; IC4VF4-NEXT: [[TMP109]] = select <4 x i1> [[TMP101]], <4 x i16> [[TMP105]], <4 x i16> [[VEC_PHI1]] ; IC4VF4-NEXT: [[TMP110]] = select <4 x i1> [[TMP102]], <4 x i16> [[TMP106]], <4 x i16> [[VEC_PHI2]] ; IC4VF4-NEXT: [[TMP111]] = select <4 x i1> [[TMP103]], <4 x i16> [[TMP107]], <4 x i16> [[VEC_PHI3]] -; IC4VF4-NEXT: [[TMP112:%.*]] = select <4 x i1> [[TMP0]], <4 x i16> [[TMP108]], <4 x i16> [[VEC_PHI]] -; IC4VF4-NEXT: [[TMP113:%.*]] = select <4 x i1> [[TMP1]], <4 x i16> [[TMP109]], <4 x i16> [[VEC_PHI1]] -; IC4VF4-NEXT: [[TMP114:%.*]] = select <4 x i1> [[TMP2]], <4 x i16> [[TMP110]], <4 x i16> [[VEC_PHI2]] -; IC4VF4-NEXT: [[TMP115:%.*]] = select <4 x i1> [[TMP3]], <4 x i16> [[TMP111]], <4 x i16> [[VEC_PHI3]] ; IC4VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16 ; IC4VF4-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i16> [[STEP_ADD_3]], splat (i16 -4) ; IC4VF4-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; IC4VF4: [[MIDDLE_BLOCK]]: +; IC4VF4-NEXT: [[TMP112:%.*]] = select <4 x i1> [[TMP0]], <4 x i16> [[TMP108]], <4 x i16> [[VEC_PHI]] +; IC4VF4-NEXT: [[TMP113:%.*]] = select <4 x i1> [[TMP1]], <4 x i16> [[TMP109]], <4 x i16> [[VEC_PHI1]] +; IC4VF4-NEXT: [[TMP114:%.*]] = select <4 x i1> [[TMP2]], <4 x i16> [[TMP110]], <4 x i16> [[VEC_PHI2]] +; IC4VF4-NEXT: [[TMP115:%.*]] = select <4 x i1> [[TMP3]], <4 x i16> [[TMP111]], <4 x i16> [[VEC_PHI3]] ; IC4VF4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP112]], <4 x i16> [[TMP113]]) ; IC4VF4-NEXT: [[RDX_MINMAX45:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[RDX_MINMAX]], <4 x i16> [[TMP114]]) ; IC4VF4-NEXT: [[RDX_MINMAX46:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[RDX_MINMAX45]], <4 x i16> [[TMP115]]) @@ -719,14 +719,14 @@ define i16 @select_decreasing_induction_icmp_table_half(half noundef %val) { ; IC4VF4-NEXT: [[TMP109]] = select <4 x i1> [[TMP101]], <4 x i16> [[TMP105]], <4 x i16> [[VEC_PHI1]] ; IC4VF4-NEXT: [[TMP110]] = select <4 x i1> [[TMP102]], <4 x i16> [[TMP106]], <4 x i16> [[VEC_PHI2]] ; IC4VF4-NEXT: [[TMP111]] = select <4 x i1> [[TMP103]], <4 x i16> [[TMP107]], <4 x i16> [[VEC_PHI3]] -; IC4VF4-NEXT: [[TMP112:%.*]] = select <4 x i1> [[TMP0]], <4 x i16> [[TMP108]], <4 x i16> [[VEC_PHI]] -; IC4VF4-NEXT: [[TMP113:%.*]] = select <4 x i1> [[TMP1]], <4 x i16> [[TMP109]], <4 x i16> [[VEC_PHI1]] -; IC4VF4-NEXT: [[TMP114:%.*]] = select <4 x i1> [[TMP2]], <4 x i16> [[TMP110]], <4 x i16> [[VEC_PHI2]] -; IC4VF4-NEXT: [[TMP115:%.*]] = select <4 x i1> [[TMP3]], <4 x i16> [[TMP111]], <4 x i16> [[VEC_PHI3]] ; IC4VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16 ; IC4VF4-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i16> [[STEP_ADD_3]], splat (i16 -4) ; IC4VF4-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; IC4VF4: [[MIDDLE_BLOCK]]: +; IC4VF4-NEXT: [[TMP112:%.*]] = select <4 x i1> [[TMP0]], <4 x i16> [[TMP108]], <4 x i16> [[VEC_PHI]] +; IC4VF4-NEXT: [[TMP113:%.*]] = select <4 x i1> [[TMP1]], <4 x i16> [[TMP109]], <4 x i16> [[VEC_PHI1]] +; IC4VF4-NEXT: [[TMP114:%.*]] = select <4 x i1> [[TMP2]], <4 x i16> [[TMP110]], <4 x i16> [[VEC_PHI2]] +; IC4VF4-NEXT: [[TMP115:%.*]] = select <4 x i1> [[TMP3]], <4 x i16> [[TMP111]], <4 x i16> [[VEC_PHI3]] ; IC4VF4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP112]], <4 x i16> [[TMP113]]) ; IC4VF4-NEXT: [[RDX_MINMAX45:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[RDX_MINMAX]], <4 x i16> [[TMP114]]) ; IC4VF4-NEXT: [[RDX_MINMAX46:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[RDX_MINMAX45]], <4 x i16> [[TMP115]]) diff --git a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll index 8bf98f043580b..10d045edd3fd2 100644 --- a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll +++ b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll @@ -212,25 +212,24 @@ define ptr @both(ptr %p, i32 %k) { ; INTERLEAVE-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 2 ; INTERLEAVE-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] ; INTERLEAVE-NEXT: [[TMP3:%.*]] = trunc i64 [[N_VEC]] to i32 -; INTERLEAVE-NEXT: [[TMP6:%.*]] = mul i64 [[N_VEC]], 4 -; INTERLEAVE-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP6]] +; INTERLEAVE-NEXT: [[TMP8:%.*]] = mul i64 [[N_VEC]], 4 +; INTERLEAVE-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP8]] ; INTERLEAVE-NEXT: br label %[[VECTOR_BODY:.*]] ; INTERLEAVE: [[VECTOR_BODY]]: ; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; INTERLEAVE-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 -; INTERLEAVE-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 4 -; INTERLEAVE-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP8]] ; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; INTERLEAVE-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; INTERLEAVE-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} ; INTERLEAVE: [[MIDDLE_BLOCK]]: +; INTERLEAVE-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 +; INTERLEAVE-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[OFFSET_IDX]] ; INTERLEAVE-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] -; INTERLEAVE-NEXT: [[IND_ESCAPE:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 -4 +; INTERLEAVE-NEXT: [[IND_ESCAPE:%.*]] = getelementptr i8, ptr [[NEXT_GEP1]], i64 -4 ; INTERLEAVE-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]] ; INTERLEAVE: [[SCALAR_PH]]: ; INTERLEAVE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] -; INTERLEAVE-NEXT: [[BC_RESUME_VAL1:%.*]] = phi ptr [ [[NEXT_GEP]], %[[MIDDLE_BLOCK]] ], [ [[BASE]], %[[ENTRY]] ] -; INTERLEAVE-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi ptr [ [[NEXT_GEP1]], %[[MIDDLE_BLOCK]] ], [ [[BASE]], %[[ENTRY]] ] +; INTERLEAVE-NEXT: [[BC_RESUME_VAL1:%.*]] = phi ptr [ [[NEXT_GEP1]], %[[MIDDLE_BLOCK]] ], [ [[BASE]], %[[ENTRY]] ] +; INTERLEAVE-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi ptr [ [[NEXT_GEP]], %[[MIDDLE_BLOCK]] ], [ [[BASE]], %[[ENTRY]] ] ; INTERLEAVE-NEXT: br label %[[FOR_BODY:.*]] ; INTERLEAVE: [[FOR_BODY]]: ; INTERLEAVE-NEXT: [[INC_PHI:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] @@ -643,12 +642,12 @@ define i32 @postinc_not_iv_backedge_value(i32 %k) { ; VEC: [[VECTOR_BODY]]: ; VEC-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; VEC-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; VEC-NEXT: [[TMP0:%.*]] = add <2 x i32> [[VEC_IND]], splat (i32 2) ; VEC-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; VEC-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i32> [[VEC_IND]], splat (i32 2) ; VEC-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; VEC-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} ; VEC: [[MIDDLE_BLOCK]]: +; VEC-NEXT: [[TMP0:%.*]] = add <2 x i32> [[VEC_IND]], splat (i32 2) ; VEC-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP0]], i32 1 ; VEC-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[K]], [[N_VEC]] ; VEC-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]] @@ -1130,7 +1129,6 @@ define i32 @test_iv_uniform_with_outside_use_scev_simplification_2(ptr %dst) { ; VEC-NEXT: br label %[[VECTOR_BODY:.*]] ; VEC: [[VECTOR_BODY]]: ; VEC-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; VEC-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; VEC-NEXT: [[OFFSET_IDX:%.*]] = mul i32 [[INDEX]], 2 ; VEC-NEXT: [[TMP0:%.*]] = add i32 [[OFFSET_IDX]], 0 ; VEC-NEXT: [[TMP1:%.*]] = add i32 [[OFFSET_IDX]], 2 @@ -1138,17 +1136,13 @@ define i32 @test_iv_uniform_with_outside_use_scev_simplification_2(ptr %dst) { ; VEC-NEXT: [[TMP3:%.*]] = getelementptr inbounds i16, ptr [[DST]], i32 [[TMP1]] ; VEC-NEXT: store i16 0, ptr [[TMP2]], align 2 ; VEC-NEXT: store i16 0, ptr [[TMP3]], align 2 -; VEC-NEXT: [[TMP4:%.*]] = add <2 x i32> [[VEC_IND]], splat (i32 1) -; VEC-NEXT: [[TMP5:%.*]] = add <2 x i32> splat (i32 1), [[TMP4]] ; VEC-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 -; VEC-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], splat (i32 4) ; VEC-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4 ; VEC-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} ; VEC: [[MIDDLE_BLOCK]]: -; VEC-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1 ; VEC-NEXT: br label %[[E_EXIT:.*]] ; VEC: [[E_EXIT]]: -; VEC-NEXT: ret i32 [[TMP7]] +; VEC-NEXT: ret i32 8 ; ; INTERLEAVE-LABEL: define i32 @test_iv_uniform_with_outside_use_scev_simplification_2( ; INTERLEAVE-SAME: ptr [[DST:%.*]]) { @@ -1166,15 +1160,13 @@ define i32 @test_iv_uniform_with_outside_use_scev_simplification_2(ptr %dst) { ; INTERLEAVE-NEXT: [[TMP3:%.*]] = getelementptr inbounds i16, ptr [[DST]], i32 [[TMP1]] ; INTERLEAVE-NEXT: store i16 0, ptr [[TMP2]], align 2 ; INTERLEAVE-NEXT: store i16 0, ptr [[TMP3]], align 2 -; INTERLEAVE-NEXT: [[TMP4:%.*]] = add i32 [[TMP1]], 1 -; INTERLEAVE-NEXT: [[TMP5:%.*]] = add i32 1, [[TMP4]] ; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; INTERLEAVE-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4 ; INTERLEAVE-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}} ; INTERLEAVE: [[MIDDLE_BLOCK]]: ; INTERLEAVE-NEXT: br label %[[E_EXIT:.*]] ; INTERLEAVE: [[E_EXIT]]: -; INTERLEAVE-NEXT: ret i32 [[TMP5]] +; INTERLEAVE-NEXT: ret i32 8 ; entry: %step.1 = sext i8 0 to i32 @@ -1293,13 +1285,11 @@ define i64 @test_iv_increment_incremented(ptr %dst) { ; VEC-NEXT: [[TMP1:%.*]] = getelementptr i16, ptr [[TMP0]], i64 0 ; VEC-NEXT: [[TMP2:%.*]] = getelementptr i16, ptr [[TMP1]], i64 -1 ; VEC-NEXT: store <2 x i16> splat (i16 1), ptr [[TMP2]], align 2 -; VEC-NEXT: [[TMP5:%.*]] = add i64 1, -1 -; VEC-NEXT: [[IV_1_NEXT_LCSSA1:%.*]] = add i64 [[TMP5]], 1 ; VEC-NEXT: br label %[[MIDDLE_BLOCK:.*]] ; VEC: [[MIDDLE_BLOCK]]: ; VEC-NEXT: br label %[[EXIT:.*]] ; VEC: [[EXIT]]: -; VEC-NEXT: ret i64 [[IV_1_NEXT_LCSSA1]] +; VEC-NEXT: ret i64 1 ; ; INTERLEAVE-LABEL: define i64 @test_iv_increment_incremented( ; INTERLEAVE-SAME: ptr [[DST:%.*]]) { @@ -1312,13 +1302,11 @@ define i64 @test_iv_increment_incremented(ptr %dst) { ; INTERLEAVE-NEXT: [[TMP1:%.*]] = getelementptr i16, ptr [[DST]], i64 2 ; INTERLEAVE-NEXT: store i16 1, ptr [[TMP0]], align 2 ; INTERLEAVE-NEXT: store i16 1, ptr [[TMP1]], align 2 -; INTERLEAVE-NEXT: [[TMP2:%.*]] = add i64 1, -1 -; INTERLEAVE-NEXT: [[IV_1_NEXT_LCSSA1:%.*]] = add i64 [[TMP2]], 1 ; INTERLEAVE-NEXT: br label %[[MIDDLE_BLOCK:.*]] ; INTERLEAVE: [[MIDDLE_BLOCK]]: ; INTERLEAVE-NEXT: br label %[[EXIT:.*]] ; INTERLEAVE: [[EXIT]]: -; INTERLEAVE-NEXT: ret i64 [[IV_1_NEXT_LCSSA1]] +; INTERLEAVE-NEXT: ret i64 1 ; entry: br label %loop diff --git a/llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll b/llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll index 5c6bccfb32d8a..1e63271cf26d5 100644 --- a/llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll +++ b/llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll @@ -89,14 +89,14 @@ define void @test3(ptr %p) { ; CHECK: vector.ph: ; CHECK-NEXT: br label [[VECTOR_BODY1:%.*]] ; CHECK: vector.body: -; CHECK-NEXT: [[INC46:%.*]] = add i32 6, 1 -; CHECK-NEXT: [[TMP5:%.*]] = add i32 7, 1 -; CHECK-NEXT: [[TMP6:%.*]] = add i32 8, 1 -; CHECK-NEXT: [[TMP7:%.*]] = add i32 9, 1 -; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> poison, i32 [[INC46]], i32 0 -; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[TMP5]], i32 1 -; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP6]], i32 2 -; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP7]], i32 3 +; CHECK-NEXT: [[TMP0:%.*]] = add i32 6, 1 +; CHECK-NEXT: [[TMP1:%.*]] = add i32 7, 1 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 8, 1 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 9, 1 +; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i32> [[TMP4]], i32 [[TMP1]], i32 1 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[TMP2]], i32 2 +; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP6]], i32 [[TMP3]], i32 3 ; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] ; CHECK: pred.store.if: ; CHECK-NEXT: [[ARRAYIDX48:%.*]] = getelementptr inbounds [1024 x i8], ptr [[P:%.*]], i64 0, i64 6 @@ -199,3 +199,60 @@ bb: %local.use = add i32 %local, 1 ret i32 %local.use } + +; Test that exit phi extracts are inserted after the definition of the value +; being extracted. This used to crash due to dominance violation when the sunk +; select was generated after the extractelement for the exit phi. +define i32 @exit_phi_sunk_def(ptr noalias %src, ptr noalias %dst) { +; CHECK-LABEL: @exit_phi_sunk_def( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[SRC:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0 +; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; CHECK: pred.store.if: +; CHECK-NEXT: store i32 1, ptr [[DST:%.*]], align 4 +; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]] +; CHECK: pred.store.continue: +; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]] +; CHECK: pred.store.if1: +; CHECK-NEXT: store i32 2, ptr [[DST]], align 4 +; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]] +; CHECK: pred.store.continue2: +; CHECK-NEXT: br i1 true, label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] +; CHECK: pred.store.if3: +; CHECK-NEXT: store i32 3, ptr [[DST]], align 4 +; CHECK-NEXT: br label [[PRED_STORE_CONTINUE4]] +; CHECK: pred.store.continue4: +; CHECK-NEXT: br i1 false, label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]] +; CHECK: pred.store.if5: +; CHECK-NEXT: store i32 4, ptr [[DST]], align 4 +; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]] +; CHECK: pred.store.continue6: +; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]] +; CHECK: middle.block: +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[TMP1]], <4 x i32> zeroinitializer, <4 x i32> splat (i32 2) +; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x i32> [[SEL]], i32 0 +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret i32 [[EXT]] +; +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] + %ld = load i32, ptr %src, align 4 + %cmp = icmp eq i32 %ld, 0 + %sel = select i1 %cmp, i32 0, i32 2 + %iv.next = add nuw nsw i32 %iv, 1 + store i32 %iv.next, ptr %dst, align 4 + %exit.cond = icmp ult i32 %iv, 2 + br i1 %exit.cond, label %loop, label %exit + +exit: + ret i32 %sel +} diff --git a/llvm/test/Transforms/LoopVectorize/multiple-result-intrinsics.ll b/llvm/test/Transforms/LoopVectorize/multiple-result-intrinsics.ll index f64d43adecfb8..c6fcbed983d3c 100644 --- a/llvm/test/Transforms/LoopVectorize/multiple-result-intrinsics.ll +++ b/llvm/test/Transforms/LoopVectorize/multiple-result-intrinsics.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "(:|sincos|frexp|modf|extract|store|with\.overflow)" --version 5 +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "(:|sincos|frexp|modf|extract|store)" --version 5 ; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=2 < %s -S -o - | FileCheck %s define void @sincos_f32(ptr noalias %in, ptr noalias writeonly %out_a, ptr noalias writeonly %out_b) { @@ -348,471 +348,3 @@ for.body: exit: ret void } - -define void @uadd_with_overflow_i32(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @uadd_with_overflow_i32( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.uadd.with.overflow.v2i32(<2 x i32> [[WIDE_LOAD:%.*]], <2 x i32> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i32> [[TMP5]], ptr [[TMP9:%.*]], align 4 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i32, ptr %in_a, i64 %iv - %val_a = load i32, ptr %arrayidx_a, align 4 - %arrayidx_b = getelementptr inbounds i32, ptr %in_b, i64 %iv - %val_b = load i32, ptr %arrayidx_b, align 4 - %call = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %val_a, i32 %val_b) - %result = extractvalue { i32, i1 } %call, 0 - %overflow = extractvalue { i32, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i32, ptr %out_result, i64 %iv - store i32 %result, ptr %arrayidx_result, align 4 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @uadd_with_overflow_i64(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @uadd_with_overflow_i64( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i64>, <2 x i1> } @llvm.uadd.with.overflow.v2i64(<2 x i64> [[WIDE_LOAD:%.*]], <2 x i64> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i64> [[TMP5]], ptr [[TMP9:%.*]], align 8 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i64, ptr %in_a, i64 %iv - %val_a = load i64, ptr %arrayidx_a, align 8 - %arrayidx_b = getelementptr inbounds i64, ptr %in_b, i64 %iv - %val_b = load i64, ptr %arrayidx_b, align 8 - %call = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %val_a, i64 %val_b) - %result = extractvalue { i64, i1 } %call, 0 - %overflow = extractvalue { i64, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i64, ptr %out_result, i64 %iv - store i64 %result, ptr %arrayidx_result, align 8 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @sadd_with_overflow_i32(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @sadd_with_overflow_i32( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[WIDE_LOAD:%.*]], <2 x i32> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i32> [[TMP5]], ptr [[TMP9:%.*]], align 4 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i32, ptr %in_a, i64 %iv - %val_a = load i32, ptr %arrayidx_a, align 4 - %arrayidx_b = getelementptr inbounds i32, ptr %in_b, i64 %iv - %val_b = load i32, ptr %arrayidx_b, align 4 - %call = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %val_a, i32 %val_b) - %result = extractvalue { i32, i1 } %call, 0 - %overflow = extractvalue { i32, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i32, ptr %out_result, i64 %iv - store i32 %result, ptr %arrayidx_result, align 4 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @sadd_with_overflow_i64(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @sadd_with_overflow_i64( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i64>, <2 x i1> } @llvm.sadd.with.overflow.v2i64(<2 x i64> [[WIDE_LOAD:%.*]], <2 x i64> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i64> [[TMP5]], ptr [[TMP9:%.*]], align 8 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i64, ptr %in_a, i64 %iv - %val_a = load i64, ptr %arrayidx_a, align 8 - %arrayidx_b = getelementptr inbounds i64, ptr %in_b, i64 %iv - %val_b = load i64, ptr %arrayidx_b, align 8 - %call = tail call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %val_a, i64 %val_b) - %result = extractvalue { i64, i1 } %call, 0 - %overflow = extractvalue { i64, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i64, ptr %out_result, i64 %iv - store i64 %result, ptr %arrayidx_result, align 8 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @usub_with_overflow_i32(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @usub_with_overflow_i32( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.usub.with.overflow.v2i32(<2 x i32> [[WIDE_LOAD:%.*]], <2 x i32> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i32> [[TMP5]], ptr [[TMP9:%.*]], align 4 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i32, ptr %in_a, i64 %iv - %val_a = load i32, ptr %arrayidx_a, align 4 - %arrayidx_b = getelementptr inbounds i32, ptr %in_b, i64 %iv - %val_b = load i32, ptr %arrayidx_b, align 4 - %call = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %val_a, i32 %val_b) - %result = extractvalue { i32, i1 } %call, 0 - %overflow = extractvalue { i32, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i32, ptr %out_result, i64 %iv - store i32 %result, ptr %arrayidx_result, align 4 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @usub_with_overflow_i64(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @usub_with_overflow_i64( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i64>, <2 x i1> } @llvm.usub.with.overflow.v2i64(<2 x i64> [[WIDE_LOAD:%.*]], <2 x i64> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i64> [[TMP5]], ptr [[TMP9:%.*]], align 8 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i64, ptr %in_a, i64 %iv - %val_a = load i64, ptr %arrayidx_a, align 8 - %arrayidx_b = getelementptr inbounds i64, ptr %in_b, i64 %iv - %val_b = load i64, ptr %arrayidx_b, align 8 - %call = tail call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %val_a, i64 %val_b) - %result = extractvalue { i64, i1 } %call, 0 - %overflow = extractvalue { i64, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i64, ptr %out_result, i64 %iv - store i64 %result, ptr %arrayidx_result, align 8 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @ssub_with_overflow_i32(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @ssub_with_overflow_i32( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.ssub.with.overflow.v2i32(<2 x i32> [[WIDE_LOAD:%.*]], <2 x i32> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i32> [[TMP5]], ptr [[TMP9:%.*]], align 4 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i32, ptr %in_a, i64 %iv - %val_a = load i32, ptr %arrayidx_a, align 4 - %arrayidx_b = getelementptr inbounds i32, ptr %in_b, i64 %iv - %val_b = load i32, ptr %arrayidx_b, align 4 - %call = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %val_a, i32 %val_b) - %result = extractvalue { i32, i1 } %call, 0 - %overflow = extractvalue { i32, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i32, ptr %out_result, i64 %iv - store i32 %result, ptr %arrayidx_result, align 4 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @ssub_with_overflow_i64(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @ssub_with_overflow_i64( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i64>, <2 x i1> } @llvm.ssub.with.overflow.v2i64(<2 x i64> [[WIDE_LOAD:%.*]], <2 x i64> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i64> [[TMP5]], ptr [[TMP9:%.*]], align 8 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i64, ptr %in_a, i64 %iv - %val_a = load i64, ptr %arrayidx_a, align 8 - %arrayidx_b = getelementptr inbounds i64, ptr %in_b, i64 %iv - %val_b = load i64, ptr %arrayidx_b, align 8 - %call = tail call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %val_a, i64 %val_b) - %result = extractvalue { i64, i1 } %call, 0 - %overflow = extractvalue { i64, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i64, ptr %out_result, i64 %iv - store i64 %result, ptr %arrayidx_result, align 8 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @umul_with_overflow_i32(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @umul_with_overflow_i32( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.umul.with.overflow.v2i32(<2 x i32> [[WIDE_LOAD:%.*]], <2 x i32> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i32> [[TMP5]], ptr [[TMP9:%.*]], align 4 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i32, ptr %in_a, i64 %iv - %val_a = load i32, ptr %arrayidx_a, align 4 - %arrayidx_b = getelementptr inbounds i32, ptr %in_b, i64 %iv - %val_b = load i32, ptr %arrayidx_b, align 4 - %call = tail call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %val_a, i32 %val_b) - %result = extractvalue { i32, i1 } %call, 0 - %overflow = extractvalue { i32, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i32, ptr %out_result, i64 %iv - store i32 %result, ptr %arrayidx_result, align 4 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @umul_with_overflow_i64(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @umul_with_overflow_i64( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i64>, <2 x i1> } @llvm.umul.with.overflow.v2i64(<2 x i64> [[WIDE_LOAD:%.*]], <2 x i64> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i64> [[TMP5]], ptr [[TMP9:%.*]], align 8 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i64, ptr %in_a, i64 %iv - %val_a = load i64, ptr %arrayidx_a, align 8 - %arrayidx_b = getelementptr inbounds i64, ptr %in_b, i64 %iv - %val_b = load i64, ptr %arrayidx_b, align 8 - %call = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %val_a, i64 %val_b) - %result = extractvalue { i64, i1 } %call, 0 - %overflow = extractvalue { i64, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i64, ptr %out_result, i64 %iv - store i64 %result, ptr %arrayidx_result, align 8 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @smul_with_overflow_i32(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @smul_with_overflow_i32( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.smul.with.overflow.v2i32(<2 x i32> [[WIDE_LOAD:%.*]], <2 x i32> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i32> [[TMP5]], ptr [[TMP9:%.*]], align 4 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i32, ptr %in_a, i64 %iv - %val_a = load i32, ptr %arrayidx_a, align 4 - %arrayidx_b = getelementptr inbounds i32, ptr %in_b, i64 %iv - %val_b = load i32, ptr %arrayidx_b, align 4 - %call = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %val_a, i32 %val_b) - %result = extractvalue { i32, i1 } %call, 0 - %overflow = extractvalue { i32, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i32, ptr %out_result, i64 %iv - store i32 %result, ptr %arrayidx_result, align 4 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} - -define void @smul_with_overflow_i64(ptr noalias %in_a, ptr noalias %in_b, ptr noalias writeonly %out_result, ptr noalias writeonly %out_overflow) { -; CHECK-LABEL: define void @smul_with_overflow_i64( -; CHECK-SAME: ptr noalias [[IN_A:%.*]], ptr noalias [[IN_B:%.*]], ptr noalias writeonly [[OUT_RESULT:%.*]], ptr noalias writeonly [[OUT_OVERFLOW:%.*]]) { -; CHECK: [[VECTOR_BODY:.*:]] -; CHECK: [[FOR_BODY:.*:]] -; CHECK: [[VECTOR_BODY1:.*:]] -; CHECK: [[TMP4:%.*]] = call { <2 x i64>, <2 x i1> } @llvm.smul.with.overflow.v2i64(<2 x i64> [[WIDE_LOAD:%.*]], <2 x i64> [[WIDE_LOAD1:%.*]]) -; CHECK: [[TMP5:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 0 -; CHECK: [[TMP6:%.*]] = extractvalue { <2 x i64>, <2 x i1> } [[TMP4]], 1 -; CHECK: store <2 x i64> [[TMP5]], ptr [[TMP9:%.*]], align 8 -; CHECK: store <2 x i8> [[TMP8:%.*]], ptr [[TMP7:%.*]], align 1 -; CHECK: [[EXIT:.*:]] -; CHECK: [[EXIT1:.*:]] -; -entry: - br label %for.body - -for.body: - %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] - %arrayidx_a = getelementptr inbounds i64, ptr %in_a, i64 %iv - %val_a = load i64, ptr %arrayidx_a, align 8 - %arrayidx_b = getelementptr inbounds i64, ptr %in_b, i64 %iv - %val_b = load i64, ptr %arrayidx_b, align 8 - %call = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %val_a, i64 %val_b) - %result = extractvalue { i64, i1 } %call, 0 - %overflow = extractvalue { i64, i1 } %call, 1 - %zext_overflow = zext i1 %overflow to i8 - %arrayidx_result = getelementptr inbounds i64, ptr %out_result, i64 %iv - store i64 %result, ptr %arrayidx_result, align 8 - %arrayidx_overflow = getelementptr inbounds i8, ptr %out_overflow, i64 %iv - store i8 %zext_overflow, ptr %arrayidx_overflow, align 1 - %iv.next = add nuw nsw i64 %iv, 1 - %exitcond.not = icmp eq i64 %iv.next, 1024 - br i1 %exitcond.not, label %exit, label %for.body - -exit: - ret void -} diff --git a/llvm/test/Transforms/LoopVectorize/no_outside_user.ll b/llvm/test/Transforms/LoopVectorize/no_outside_user.ll index 9c73d85bd58ff..5e2fb0c514d8d 100644 --- a/llvm/test/Transforms/LoopVectorize/no_outside_user.ll +++ b/llvm/test/Transforms/LoopVectorize/no_outside_user.ll @@ -23,7 +23,7 @@ define i32 @test1() { ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[SMAX]], [[B_PROMOTED]] ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2 -; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I1:.*]], label %[[VECTOR_PH:.*]] +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]] @@ -35,21 +35,21 @@ define i32 @test1() { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <2 x i32> [[VEC_IND]], splat (i32 10) -; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> splat (i32 1), <2 x i32> zeroinitializer ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i32> [[VEC_IND]], splat (i32 2) ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt <2 x i32> [[VEC_IND]], splat (i32 10) +; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP6]], <2 x i32> splat (i32 1), <2 x i32> zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[PREDPHI]], i32 1 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]] -; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I1]] -; CHECK: [[_LR_PH_I1]]: +; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I]] +; CHECK: [[_LR_PH_I]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[B_PROMOTED]], %[[BB]] ] ; CHECK-NEXT: br label %[[DOTLR_PH_I:.*]] -; CHECK: [[_LR_PH_I:.*:]] -; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I1]] ] +; CHECK: [[_LR_PH_I1:.*:]] +; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I]] ] ; CHECK-NEXT: [[UNNAMEDTMP2:%.*]] = icmp sgt i32 [[UNNAMEDTMP8]], 10 ; CHECK-NEXT: br i1 [[UNNAMEDTMP2]], label %[[BB16]], label %[[UNNAMEDBB10:.*]] ; CHECK: [[UNNAMEDBB10]]: @@ -96,7 +96,7 @@ define i32 @test2() { ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[SMAX]], [[B_PROMOTED]] ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2 -; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I1:.*]], label %[[VECTOR_PH:.*]] +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]] @@ -108,21 +108,21 @@ define i32 @test2() { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <2 x i32> [[VEC_IND]], splat (i32 10) -; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> splat (i32 1), <2 x i32> [[VEC_IND]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i32> [[VEC_IND]], splat (i32 2) ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt <2 x i32> [[VEC_IND]], splat (i32 10) +; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP6]], <2 x i32> splat (i32 1), <2 x i32> [[VEC_IND]] ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[PREDPHI]], i32 1 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]] -; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I1]] -; CHECK: [[_LR_PH_I1]]: +; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I]] +; CHECK: [[_LR_PH_I]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[B_PROMOTED]], %[[BB]] ] ; CHECK-NEXT: br label %[[DOTLR_PH_I:.*]] -; CHECK: [[_LR_PH_I:.*:]] -; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I1]] ] +; CHECK: [[_LR_PH_I1:.*:]] +; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I]] ] ; CHECK-NEXT: [[UNNAMEDTMP2:%.*]] = icmp sgt i32 [[UNNAMEDTMP8]], 10 ; CHECK-NEXT: br i1 [[UNNAMEDTMP2]], label %[[BB16]], label %[[UNNAMEDBB10:.*]] ; CHECK: [[UNNAMEDBB10]]: @@ -169,7 +169,7 @@ define i32 @test3(i32 %N) { ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[SMAX]], [[B_PROMOTED]] ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2 -; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I:.*]], label %[[VECTOR_PH:.*]] +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I1:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]] @@ -183,24 +183,24 @@ define i32 @test3(i32 %N) { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i32> [[VEC_IND]], splat (i32 2) +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[TMP4:%.*]] = icmp sle <2 x i32> [[VEC_IND]], splat (i32 10) ; CHECK-NEXT: [[TMP5:%.*]] = icmp sle <2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP6:%.*]] = select <2 x i1> [[TMP4]], <2 x i1> [[TMP5]], <2 x i1> zeroinitializer ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP6]], <2 x i32> zeroinitializer, <2 x i32> splat (i32 2) ; CHECK-NEXT: [[PREDPHI1:%.*]] = select <2 x i1> [[TMP4]], <2 x i32> [[PREDPHI]], <2 x i32> splat (i32 1) -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 -; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i32> [[VEC_IND]], splat (i32 2) -; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] -; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[PREDPHI1]], i32 1 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]] -; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I]] -; CHECK: [[_LR_PH_I]]: +; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I1]] +; CHECK: [[_LR_PH_I1]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[B_PROMOTED]], %[[BB]] ] ; CHECK-NEXT: br label %[[DOTLR_PH_I:.*]] -; CHECK: [[_LR_PH_I1:.*:]] -; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I]] ] +; CHECK: [[_LR_PH_I:.*:]] +; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I1]] ] ; CHECK-NEXT: [[UNNAMEDTMP2:%.*]] = icmp sgt i32 [[UNNAMEDTMP8]], 10 ; CHECK-NEXT: br i1 [[UNNAMEDTMP2]], label %[[BB16]], label %[[UNNAMEDBB10:.*]] ; CHECK: [[UNNAMEDBB10]]: @@ -257,7 +257,7 @@ define i32 @test4(i32 %N) { ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[SMAX]], [[B_PROMOTED]] ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2 -; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I1:.*]], label %[[VECTOR_PH:.*]] +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]] @@ -269,21 +269,21 @@ define i32 @test4(i32 %N) { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <2 x i32> [[VEC_IND]], splat (i32 10) -; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> splat (i32 1), <2 x i32> zeroinitializer ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i32> [[VEC_IND]], splat (i32 2) ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP6:%.*]] = icmp sgt <2 x i32> [[VEC_IND]], splat (i32 10) +; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP6]], <2 x i32> splat (i32 1), <2 x i32> zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[PREDPHI]], i32 1 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]] -; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT_LOOPEXIT:.*]], label %[[_LR_PH_I1]] -; CHECK: [[_LR_PH_I1]]: +; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT_LOOPEXIT:.*]], label %[[_LR_PH_I]] +; CHECK: [[_LR_PH_I]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[B_PROMOTED]], %[[DOTLR_PH_I_PREHEADER]] ] ; CHECK-NEXT: br label %[[DOTLR_PH_I:.*]] -; CHECK: [[_LR_PH_I:.*:]] -; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I1]] ] +; CHECK: [[_LR_PH_I1:.*:]] +; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I]] ] ; CHECK-NEXT: [[UNNAMEDTMP2:%.*]] = icmp sgt i32 [[UNNAMEDTMP8]], 10 ; CHECK-NEXT: br i1 [[UNNAMEDTMP2]], label %[[BB16]], label %[[UNNAMEDBB10:.*]] ; CHECK: [[UNNAMEDBB10]]: @@ -519,7 +519,7 @@ define i8 @outside_user_non_phi() { ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP0]], i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[SMAX]], [[B_PROMOTED]] ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2 -; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I1:.*]], label %[[VECTOR_PH:.*]] +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]] @@ -531,22 +531,22 @@ define i8 @outside_user_non_phi() { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <2 x i32> [[VEC_IND]], splat (i32 10) -; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> splat (i32 1), <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i32> [[PREDPHI]] to <2 x i8> ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i32> [[VEC_IND]], splat (i32 2) ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt <2 x i32> [[VEC_IND]], splat (i32 10) +; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP7]], <2 x i32> splat (i32 1), <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i32> [[PREDPHI]] to <2 x i8> ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP4]], i32 1 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]] -; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I1]] -; CHECK: [[_LR_PH_I1]]: +; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I]] +; CHECK: [[_LR_PH_I]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[B_PROMOTED]], %[[BB]] ] ; CHECK-NEXT: br label %[[DOTLR_PH_I:.*]] -; CHECK: [[_LR_PH_I:.*:]] -; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I1]] ] +; CHECK: [[_LR_PH_I1:.*:]] +; CHECK-NEXT: [[UNNAMEDTMP8:%.*]] = phi i32 [ [[UNNAMEDTMP18:%.*]], %[[BB16:.*]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I]] ] ; CHECK-NEXT: [[UNNAMEDTMP2:%.*]] = icmp sgt i32 [[UNNAMEDTMP8]], 10 ; CHECK-NEXT: br i1 [[UNNAMEDTMP2]], label %[[BB16]], label %[[UNNAMEDBB10:.*]] ; CHECK: [[UNNAMEDBB10]]: @@ -650,14 +650,14 @@ define i32 @sum_arrays_outside_use(ptr %B, ptr %A, ptr %C, i32 %N) { ; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[N]], i32 [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[SMAX]], [[B_PROMOTED]] ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 2 -; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I1:.*]], label %[[VECTOR_MEMCHECK:.*]] +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[_LR_PH_I:.*]], label %[[VECTOR_MEMCHECK:.*]] ; CHECK: [[VECTOR_MEMCHECK]]: ; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[C1]], [[B2]] ; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i32 [[TMP2]], 8 ; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[C1]], [[A3]] ; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i32 [[TMP3]], 8 ; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]] -; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[_LR_PH_I1]], label %[[VECTOR_PH:.*]] +; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[_LR_PH_I]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 2 ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP1]], [[N_MOD_VF]] @@ -680,12 +680,12 @@ define i32 @sum_arrays_outside_use(ptr %B, ptr %A, ptr %C, i32 %N) { ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[TMP11]], i32 1 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]] -; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I1]] -; CHECK: [[_LR_PH_I1]]: +; CHECK-NEXT: br i1 [[CMP_N]], label %[[F1_EXIT_LOOPEXIT:.*]], label %[[_LR_PH_I]] +; CHECK: [[_LR_PH_I]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[B_PROMOTED]], %[[BB]] ], [ [[B_PROMOTED]], %[[VECTOR_MEMCHECK]] ] ; CHECK-NEXT: br label %[[DOTLR_PH_I:.*]] -; CHECK: [[_LR_PH_I:.*:]] -; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IVNEXT:%.*]], %[[DOTLR_PH_I]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I1]] ] +; CHECK: [[_LR_PH_I1:.*:]] +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IVNEXT:%.*]], %[[DOTLR_PH_I]] ], [ [[BC_RESUME_VAL]], %[[_LR_PH_I]] ] ; CHECK-NEXT: [[INDVARS_IV:%.*]] = sext i32 [[IV]] to i64 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[BLOAD:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4 diff --git a/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll b/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll index 18803e71f1041..d4d21c6b6e243 100644 --- a/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll +++ b/llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-liveout.ll @@ -32,11 +32,11 @@ define signext i32 @f1(ptr noalias %A, ptr noalias %B, i32 signext %n) { ; VF-TWO-CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4 ; VF-TWO-CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i64 [[INDEX]] ; VF-TWO-CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i32>, ptr [[TMP3]], align 4 -; VF-TWO-CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], [[WIDE_LOAD2]] ; VF-TWO-CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 ; VF-TWO-CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; VF-TWO-CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; VF-TWO-CHECK: middle.block: +; VF-TWO-CHECK-NEXT: [[TMP5:%.*]] = add nsw <2 x i32> [[WIDE_LOAD]], [[WIDE_LOAD2]] ; VF-TWO-CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1 ; VF-TWO-CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] ; VF-TWO-CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] @@ -54,11 +54,11 @@ define signext i32 @f1(ptr noalias %A, ptr noalias %B, i32 signext %n) { ; VF-TWO-CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i32>, ptr [[TMP9]], align 4 ; VF-TWO-CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX6]] ; VF-TWO-CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <2 x i32>, ptr [[TMP11]], align 4 -; VF-TWO-CHECK-NEXT: [[TMP13:%.*]] = add nsw <2 x i32> [[WIDE_LOAD7]], [[WIDE_LOAD8]] ; VF-TWO-CHECK-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX6]], 2 ; VF-TWO-CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT9]], [[N_VEC4]] ; VF-TWO-CHECK-NEXT: br i1 [[TMP14]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; VF-TWO-CHECK: vec.epilog.middle.block: +; VF-TWO-CHECK-NEXT: [[TMP13:%.*]] = add nsw <2 x i32> [[WIDE_LOAD7]], [[WIDE_LOAD8]] ; VF-TWO-CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i32> [[TMP13]], i32 1 ; VF-TWO-CHECK-NEXT: [[CMP_N5:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC4]] ; VF-TWO-CHECK-NEXT: br i1 [[CMP_N5]], label [[FOR_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]] diff --git a/llvm/test/Transforms/LoopVectorize/optsize.ll b/llvm/test/Transforms/LoopVectorize/optsize.ll index 08903351aa2f0..9651e1cd2dd04 100644 --- a/llvm/test/Transforms/LoopVectorize/optsize.ll +++ b/llvm/test/Transforms/LoopVectorize/optsize.ll @@ -484,13 +484,13 @@ define i32 @pr45526() optsize { ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; CHECK-NEXT: [[TMP1]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 1) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 512 ; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP0]], i1 false) ; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[TMP5]], 1 @@ -512,13 +512,13 @@ define i32 @pr45526() optsize { ; PGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; PGSO-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; PGSO-NEXT: [[TMP2:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ] -; PGSO-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; PGSO-NEXT: [[TMP1]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 1) ; PGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; PGSO-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) ; PGSO-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 512 ; PGSO-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]] ; PGSO: [[MIDDLE_BLOCK]]: +; PGSO-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; PGSO-NEXT: [[TMP4:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP0]], i1 false) ; PGSO-NEXT: [[TMP5:%.*]] = sub i64 [[TMP4]], 1 ; PGSO-NEXT: [[TMP6:%.*]] = sub i64 [[TMP5]], 1 @@ -540,13 +540,13 @@ define i32 @pr45526() optsize { ; NPGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; NPGSO-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; NPGSO-NEXT: [[TMP2:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ] -; NPGSO-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; NPGSO-NEXT: [[TMP1]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 1) ; NPGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; NPGSO-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) ; NPGSO-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 512 ; NPGSO-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] ; NPGSO: [[MIDDLE_BLOCK]]: +; NPGSO-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; NPGSO-NEXT: [[TMP4:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP0]], i1 false) ; NPGSO-NEXT: [[TMP5:%.*]] = sub i64 [[TMP4]], 1 ; NPGSO-NEXT: [[TMP6:%.*]] = sub i64 [[TMP5]], 1 @@ -584,13 +584,13 @@ define i32 @pr45526_pgso() !prof !14 { ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; CHECK-NEXT: [[TMP1]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 1) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 512 ; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP0]], i1 false) ; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[TMP5]], 1 @@ -612,13 +612,13 @@ define i32 @pr45526_pgso() !prof !14 { ; PGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; PGSO-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; PGSO-NEXT: [[TMP2:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ] -; PGSO-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; PGSO-NEXT: [[TMP1]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 1) ; PGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; PGSO-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) ; PGSO-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 512 ; PGSO-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] ; PGSO: [[MIDDLE_BLOCK]]: +; PGSO-NEXT: [[TMP0:%.*]] = icmp ugt <4 x i32> [[VEC_IND]], splat (i32 510) ; PGSO-NEXT: [[TMP4:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP0]], i1 false) ; PGSO-NEXT: [[TMP5:%.*]] = sub i64 [[TMP4]], 1 ; PGSO-NEXT: [[TMP6:%.*]] = sub i64 [[TMP5]], 1 @@ -639,12 +639,12 @@ define i32 @pr45526_pgso() !prof !14 { ; NPGSO: [[VECTOR_BODY]]: ; NPGSO-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; NPGSO-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; NPGSO-NEXT: [[TMP0:%.*]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 1) ; NPGSO-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; NPGSO-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 4) ; NPGSO-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 508 ; NPGSO-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]] ; NPGSO: [[MIDDLE_BLOCK]]: +; NPGSO-NEXT: [[TMP0:%.*]] = add nuw nsw <4 x i32> [[VEC_IND]], splat (i32 1) ; NPGSO-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 ; NPGSO-NEXT: br label %[[SCALAR_PH:.*]] ; NPGSO: [[SCALAR_PH]]: diff --git a/llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll b/llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll new file mode 100644 index 0000000000000..e451f94715610 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll @@ -0,0 +1,75 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 +; REQUIRES: asserts +; RUN: opt -p loop-vectorize -force-vector-width=4 -debug-only=loop-vectorize -disable-output -S %s 2>&1 | FileCheck %s + +define void @f(ptr noalias %p, i1 %c) { +; CHECK-LABEL: 'f' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<1024> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep> = getelementptr ir<%p>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer ir<%gep> +; CHECK-NEXT: WIDEN ir<%x> = load vp<[[VP5]]> +; CHECK-NEXT: BLEND ir<%phi> = fast ir<%x> ir<0.000000e+00>/ir<%c> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%gep> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%phi> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i32 [ 0, %entry ], [ %iv.next, %latch ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep = getelementptr float, ptr %p, i32 %iv +; CHECK-NEXT: IR %x = load float, ptr %gep, align 4 +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %latch ] + %gep = getelementptr float, ptr %p, i32 %iv + %x = load float, ptr %gep + br i1 %c, label %then, label %latch + +then: + br label %latch + +latch: + %phi = phi fast float [ %x, %loop ], [ 0.0, %then ] + store float %phi, ptr %gep + %iv.next = add i32 %iv, 1 + %done = icmp eq i32 %iv.next, 1024 + br i1 %done, label %exit, label %loop + +exit: + ret void +} diff --git a/llvm/test/Transforms/LoopVectorize/phi-with-fastflags.ll b/llvm/test/Transforms/LoopVectorize/phi-with-fastflags.ll new file mode 100644 index 0000000000000..2ce2c932de2cb --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/phi-with-fastflags.ll @@ -0,0 +1,46 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 +; RUN: opt -p loop-vectorize -force-vector-width=4 -S < %s | FileCheck %s + +define void @f(ptr noalias %p, i1 %c) { +; CHECK-LABEL: define void @f( +; CHECK-SAME: ptr noalias [[P:%.*]], i1 [[C:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: br label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[P]], i32 [[INDEX]] +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4 +; CHECK-NEXT: [[PREDPHI:%.*]] = select fast i1 [[C]], <4 x float> zeroinitializer, <4 x float> [[WIDE_LOAD]] +; CHECK-NEXT: store <4 x float> [[PREDPHI]], ptr [[TMP0]], align 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1024 +; CHECK-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br label %[[EXIT:.*]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %latch ] + %gep = getelementptr float, ptr %p, i32 %iv + %x = load float, ptr %gep + br i1 %c, label %then, label %latch + +then: + br label %latch + +latch: + %phi = phi fast float [ %x, %loop ], [ 0.0, %then ] + store float %phi, ptr %gep + %iv.next = add i32 %iv, 1 + %done = icmp eq i32 %iv.next, 1024 + br i1 %done, label %exit, label %loop + +exit: + ret void +} diff --git a/llvm/test/Transforms/LoopVectorize/pr36983-multiple-lcssa.ll b/llvm/test/Transforms/LoopVectorize/pr36983-multiple-lcssa.ll index 310c7729a6b63..23f1927185883 100644 --- a/llvm/test/Transforms/LoopVectorize/pr36983-multiple-lcssa.ll +++ b/llvm/test/Transforms/LoopVectorize/pr36983-multiple-lcssa.ll @@ -12,12 +12,12 @@ define i16 @duplicate_lcssa(i16 %val) { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = sub nsw <4 x i16> [[VEC_IND]], splat (i16 1) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <4 x i16> [[VEC_IND]], splat (i16 -4) ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 65536 ; CHECK-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP0:%.*]] = sub nsw <4 x i16> [[VEC_IND]], splat (i16 1) ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI1:%.*]] = extractelement <4 x i16> [[TMP0]], i32 2 ; CHECK-NEXT: br label %[[EXIT:.*]] ; CHECK: [[EXIT]]: diff --git a/llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll b/llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll index e2ed2abcc81f8..1e5235ec5d93f 100644 --- a/llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll +++ b/llvm/test/Transforms/LoopVectorize/pr43166-fold-tail-by-masking.ll @@ -128,9 +128,9 @@ define i32 @test3(i64 %y) { ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[Y:%.*]], 0 ; CHECK-NEXT: br label [[FOR_BODY:%.*]] ; CHECK: vector.body: -; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP1]], <4 x i32> , <4 x i32> splat (i32 55) ; CHECK-NEXT: br label [[MIDDLE_BLOCK:%.*]] ; CHECK: middle.block: +; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP1]], <4 x i32> , <4 x i32> splat (i32 55) ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> , i1 false) ; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[PREDPHI]], i64 [[TMP3]] diff --git a/llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll b/llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll index 615ea062afd53..ab2965abc2a0d 100644 --- a/llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll +++ b/llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll @@ -55,11 +55,11 @@ define dso_local i16 @reverse_interleave_load_fold_mask() optsize { ; CHECK-NEXT: [[TMP23:%.*]] = phi <2 x i16> [ [[TMP12]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP21]], [[PRED_LOAD_IF3]] ] ; CHECK-NEXT: [[TMP24:%.*]] = add nsw <2 x i16> [[TMP22]], [[TMP23]] ; CHECK-NEXT: [[TMP25]] = add <2 x i16> [[VEC_PHI]], [[TMP24]] -; CHECK-NEXT: [[TMP26:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[TMP25]], <2 x i16> [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 ; CHECK-NEXT: [[TMP27:%.*]] = icmp eq i32 [[INDEX_NEXT]], 42 ; CHECK-NEXT: br i1 [[TMP27]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP26:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[TMP25]], <2 x i16> [[VEC_PHI]] ; CHECK-NEXT: [[TMP28:%.*]] = call i16 @llvm.vector.reduce.add.v2i16(<2 x i16> [[TMP26]]) ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: exit: diff --git a/llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll b/llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll index 8d14299a02878..07623a1b0d19d 100644 --- a/llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll +++ b/llvm/test/Transforms/LoopVectorize/pr55167-fold-tail-live-out.ll @@ -23,7 +23,6 @@ define i32 @test(i32 %a, i1 %c.1, i1 %c.2 ) #0 { ; CHECK-NEXT: [[TMP0:%.*]] = add <2 x i32> [[VEC_PHI]], splat (i32 10) ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[TMP0]], splat (i32 20) ; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[PREDPHI5:%.*]] = select i1 [[C_2]], <2 x i32> [[VEC_IND]], <2 x i32> splat (i32 9) ; CHECK-NEXT: [[PREDPHI6:%.*]] = select <2 x i1> [[TMP5]], <2 x i32> [[TMP0]], <2 x i32> [[TMP3]] ; CHECK-NEXT: [[PREDPHI7]] = select i1 [[C_2]], <2 x i32> [[VEC_PHI]], <2 x i32> [[PREDPHI6]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2 @@ -31,6 +30,7 @@ define i32 @test(i32 %a, i1 %c.1, i1 %c.2 ) #0 { ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 176 ; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[PREDPHI5:%.*]] = select i1 [[C_2]], <2 x i32> [[VEC_IND]], <2 x i32> splat (i32 9) ; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[PREDPHI7]]) ; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i32> [[PREDPHI5]], i32 1 ; CHECK-NEXT: br label [[LOOP_LATCH:%.*]] diff --git a/llvm/test/Transforms/LoopVectorize/predicate-switch.ll b/llvm/test/Transforms/LoopVectorize/predicate-switch.ll index 3276528e54225..acddbfd6aab81 100644 --- a/llvm/test/Transforms/LoopVectorize/predicate-switch.ll +++ b/llvm/test/Transforms/LoopVectorize/predicate-switch.ll @@ -508,6 +508,150 @@ define void @switch_unconditional(ptr %start) { ; IC2: [[EXIT]]: ; IC2-NEXT: ret void ; +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] + %gep = getelementptr i32, ptr %start, i64 %iv + %x = load i32, ptr %gep + switch i32 %x, label %foo [] + +foo: + br label %loop.latch + +loop.latch: + store i32 0, ptr %gep + %iv.next = add i64 %iv, 1 + %cmp = icmp eq i64 %iv.next, 100 + br i1 %cmp, label %exit, label %loop.header + +exit: + ret void +} + +define void @switch_unconditional_duplicate_target(ptr %start, ptr %dest) { +; IC1-LABEL: define void @switch_unconditional_duplicate_target( +; IC1-SAME: ptr [[START:%.*]], ptr [[DEST:%.*]]) { +; IC1-NEXT: [[ENTRY:.*:]] +; IC1-NEXT: br label %[[VECTOR_MEMCHECK:.*]] +; IC1: [[VECTOR_MEMCHECK]]: +; IC1-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DEST]], i64 4 +; IC1-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[START]], i64 400 +; IC1-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DEST]], [[SCEVGEP1]] +; IC1-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[START]], [[SCEVGEP]] +; IC1-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; IC1-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; IC1: [[VECTOR_PH]]: +; IC1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x ptr> poison, ptr [[DEST]], i64 0 +; IC1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x ptr> [[BROADCAST_SPLATINSERT]], <2 x ptr> poison, <2 x i32> zeroinitializer +; IC1-NEXT: br label %[[VECTOR_BODY:.*]] +; IC1: [[VECTOR_BODY]]: +; IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; IC1-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] +; IC1-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[START]], <2 x i64> [[VEC_IND]] +; IC1-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[TMP0]], i32 0 +; IC1-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP4]], align 4, !alias.scope [[META6:![0-9]+]] +; IC1-NEXT: [[TMP5:%.*]] = icmp ult <2 x i32> [[WIDE_LOAD]], splat (i32 10) +; IC1-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP5]], <2 x ptr> [[BROADCAST_SPLAT]], <2 x ptr> [[TMP0]] +; IC1-NEXT: [[PREDPHI2:%.*]] = select <2 x i1> [[TMP5]], <2 x ptr> [[BROADCAST_SPLAT]], <2 x ptr> [[PREDPHI]] +; IC1-NEXT: [[TMP1:%.*]] = extractelement <2 x ptr> [[PREDPHI2]], i32 0 +; IC1-NEXT: [[TMP2:%.*]] = extractelement <2 x ptr> [[PREDPHI2]], i32 1 +; IC1-NEXT: store i32 0, ptr [[TMP1]], align 4 +; IC1-NEXT: store i32 0, ptr [[TMP2]], align 4 +; IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; IC1-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 2) +; IC1-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; IC1-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; IC1: [[MIDDLE_BLOCK]]: +; IC1-NEXT: br label %[[EXIT:.*]] +; IC1: [[SCALAR_PH]]: +; IC1-NEXT: br label %[[LOOP:.*]] +; IC1: [[LOOP]]: +; IC1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ] +; IC1-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[START]], i64 [[IV]] +; IC1-NEXT: [[X:%.*]] = load i32, ptr [[GEP]], align 4 +; IC1-NEXT: [[COND:%.*]] = icmp ult i32 [[X]], 10 +; IC1-NEXT: br i1 [[COND]], label %[[FORWARD:.*]], label %[[LATCH]] +; IC1: [[FORWARD]]: +; IC1-NEXT: switch i32 [[X]], label %[[LATCH]] [ +; IC1-NEXT: i32 0, label %[[LATCH]] +; IC1-NEXT: ] +; IC1: [[LATCH]]: +; IC1-NEXT: [[GEP_1:%.*]] = phi ptr [ [[GEP]], %[[LOOP]] ], [ [[DEST]], %[[FORWARD]] ], [ [[DEST]], %[[FORWARD]] ] +; IC1-NEXT: store i32 0, ptr [[GEP_1]], align 4 +; IC1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; IC1-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 100 +; IC1-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]] +; IC1: [[EXIT]]: +; IC1-NEXT: ret void +; +; IC2-LABEL: define void @switch_unconditional_duplicate_target( +; IC2-SAME: ptr [[START:%.*]], ptr [[DEST:%.*]]) { +; IC2-NEXT: [[ENTRY:.*:]] +; IC2-NEXT: br label %[[VECTOR_MEMCHECK:.*]] +; IC2: [[VECTOR_MEMCHECK]]: +; IC2-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DEST]], i64 4 +; IC2-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[START]], i64 400 +; IC2-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DEST]], [[SCEVGEP1]] +; IC2-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[START]], [[SCEVGEP]] +; IC2-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; IC2-NEXT: br i1 [[FOUND_CONFLICT]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] +; IC2: [[VECTOR_PH]]: +; IC2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x ptr> poison, ptr [[DEST]], i64 0 +; IC2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x ptr> [[BROADCAST_SPLATINSERT]], <2 x ptr> poison, <2 x i32> zeroinitializer +; IC2-NEXT: br label %[[VECTOR_BODY:.*]] +; IC2: [[VECTOR_BODY]]: +; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; IC2-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] +; IC2-NEXT: [[STEP_ADD:%.*]] = add <2 x i64> [[VEC_IND]], splat (i64 2) +; IC2-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[START]], <2 x i64> [[VEC_IND]] +; IC2-NEXT: [[TMP7:%.*]] = extractelement <2 x ptr> [[TMP0]], i32 0 +; IC2-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[START]], <2 x i64> [[STEP_ADD]] +; IC2-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 2 +; IC2-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 4, !alias.scope [[META6:![0-9]+]] +; IC2-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x i32>, ptr [[TMP8]], align 4, !alias.scope [[META6]] +; IC2-NEXT: [[TMP9:%.*]] = icmp ult <2 x i32> [[WIDE_LOAD]], splat (i32 10) +; IC2-NEXT: [[TMP10:%.*]] = icmp ult <2 x i32> [[WIDE_LOAD2]], splat (i32 10) +; IC2-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP9]], <2 x ptr> [[BROADCAST_SPLAT]], <2 x ptr> [[TMP0]] +; IC2-NEXT: [[PREDPHI2:%.*]] = select <2 x i1> [[TMP9]], <2 x ptr> [[BROADCAST_SPLAT]], <2 x ptr> [[PREDPHI]] +; IC2-NEXT: [[TMP2:%.*]] = extractelement <2 x ptr> [[PREDPHI2]], i32 0 +; IC2-NEXT: [[TMP3:%.*]] = extractelement <2 x ptr> [[PREDPHI2]], i32 1 +; IC2-NEXT: [[PREDPHI5:%.*]] = select <2 x i1> [[TMP10]], <2 x ptr> [[BROADCAST_SPLAT]], <2 x ptr> [[TMP1]] +; IC2-NEXT: [[PREDPHI4:%.*]] = select <2 x i1> [[TMP10]], <2 x ptr> [[BROADCAST_SPLAT]], <2 x ptr> [[PREDPHI5]] +; IC2-NEXT: [[TMP4:%.*]] = extractelement <2 x ptr> [[PREDPHI4]], i32 0 +; IC2-NEXT: [[TMP5:%.*]] = extractelement <2 x ptr> [[PREDPHI4]], i32 1 +; IC2-NEXT: store i32 0, ptr [[TMP2]], align 4 +; IC2-NEXT: store i32 0, ptr [[TMP3]], align 4 +; IC2-NEXT: store i32 0, ptr [[TMP4]], align 4 +; IC2-NEXT: store i32 0, ptr [[TMP5]], align 4 +; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; IC2-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[STEP_ADD]], splat (i64 2) +; IC2-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; IC2-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; IC2: [[MIDDLE_BLOCK]]: +; IC2-NEXT: br label %[[EXIT:.*]] +; IC2: [[SCALAR_PH]]: +; IC2-NEXT: br label %[[LOOP:.*]] +; IC2: [[LOOP]]: +; IC2-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ] +; IC2-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[START]], i64 [[IV]] +; IC2-NEXT: [[X:%.*]] = load i32, ptr [[GEP]], align 4 +; IC2-NEXT: [[COND:%.*]] = icmp ult i32 [[X]], 10 +; IC2-NEXT: br i1 [[COND]], label %[[FORWARD:.*]], label %[[LATCH]] +; IC2: [[FORWARD]]: +; IC2-NEXT: switch i32 [[X]], label %[[LATCH]] [ +; IC2-NEXT: i32 0, label %[[LATCH]] +; IC2-NEXT: ] +; IC2: [[LATCH]]: +; IC2-NEXT: [[GEP_1:%.*]] = phi ptr [ [[GEP]], %[[LOOP]] ], [ [[DEST]], %[[FORWARD]] ], [ [[DEST]], %[[FORWARD]] ] +; IC2-NEXT: store i32 0, ptr [[GEP_1]], align 4 +; IC2-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; IC2-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV_NEXT]], 100 +; IC2-NEXT: br i1 [[CMP]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP10:![0-9]+]] +; IC2: [[EXIT]]: +; IC2-NEXT: ret void +; entry: br label %loop @@ -515,13 +659,15 @@ loop: %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] %gep = getelementptr i32, ptr %start, i64 %iv %x = load i32, ptr %gep - switch i32 %x, label %foo [] + %cond = icmp ult i32 %x, 10 + br i1 %cond, label %forward, label %latch -foo: - br label %latch +forward: + switch i32 %x, label %latch [ i32 0, label %latch ] latch: - store i32 0, ptr %gep + %gep.1 = phi ptr [ %gep, %loop ], [ %dest, %forward ], [ %dest, %forward ] + store i32 0, ptr %gep.1 %iv.next = add i64 %iv, 1 %cmp = icmp eq i64 %iv.next, 100 br i1 %cmp, label %exit, label %loop @@ -537,6 +683,11 @@ exit: ; IC1: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} ; IC1: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} ; IC1: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]} +; IC1: [[META6]] = !{[[META7:![0-9]+]]} +; IC1: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]]} +; IC1: [[META8]] = distinct !{[[META8]], !"LVerDomain"} +; IC1: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]} +; IC1: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]]} ;. ; IC2: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} ; IC2: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} @@ -544,4 +695,9 @@ exit: ; IC2: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} ; IC2: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} ; IC2: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]} +; IC2: [[META6]] = !{[[META7:![0-9]+]]} +; IC2: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]]} +; IC2: [[META8]] = distinct !{[[META8]], !"LVerDomain"} +; IC2: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]} +; IC2: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]]} ;. diff --git a/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll b/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll index e4322cfcc00ac..c9cc8060ff498 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll @@ -94,11 +94,11 @@ define i32 @chained_smax(i32 %x, ptr %src) { ; CHECK: [[PRED_LOAD_CONTINUE6]]: ; CHECK-NEXT: [[TMP25:%.*]] = phi <4 x i32> [ [[TMP19]], %[[PRED_LOAD_CONTINUE4]] ], [ [[TMP24]], %[[PRED_LOAD_IF5]] ] ; CHECK-NEXT: [[TMP26]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP25]], <4 x i32> [[TMP1]]) -; CHECK-NEXT: [[TMP27:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[TMP26]], <4 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 4) ; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP27:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[TMP26]], <4 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP27]]) ; CHECK-NEXT: br label %[[EXIT:.*]] ; CHECK: [[EXIT]]: diff --git a/llvm/test/Transforms/LoopVectorize/reduction-order.ll b/llvm/test/Transforms/LoopVectorize/reduction-order.ll index b51db48c1c6ed..186c64c924233 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction-order.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-order.ll @@ -16,18 +16,18 @@ define i32 @foo() !prof !1 { ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_PHI_1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[ADD_5:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_PHI_2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[ADD_3:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[ADD_3]] = add <4 x i32> splat (i32 3), [[VEC_PHI_2]] +; CHECK-NEXT: [[ADD_5]] = add <4 x i32> [[VEC_PHI_1]], splat (i32 5) +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12 +; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !prof [[PROF1:![0-9]+]], !llvm.loop [[LOOP2:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], ; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i64> [[VEC_IV]], splat (i64 9) -; CHECK-NEXT: [[ADD_3]] = add <4 x i32> splat (i32 3), [[VEC_PHI_2]] -; CHECK-NEXT: [[ADD_5]] = add <4 x i32> [[VEC_PHI_1]], splat (i32 5) ; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[ADD_5]], <4 x i32> [[VEC_PHI_1]] ; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[ADD_3]], <4 x i32> [[VEC_PHI_2]] -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12 -; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !prof [[PROF1:![0-9]+]], !llvm.loop [[LOOP2:![0-9]+]] -; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]]) ; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]]) ; CHECK-NEXT: br label %[[EXIT:.*]] diff --git a/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll b/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll index caf1a934ed70a..1c016d08a3c7f 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll @@ -13,7 +13,7 @@ define i8 @PR34687(i1 %c, i32 %x, i32 %n, i32 %divisor) { ; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[N_MOD_VF]] ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP0:%.*]] = select i1 [[C:%.*]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> splat (i32 1) +; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[C:%.*]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> splat (i32 1) ; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <4 x i32> poison, i32 [[X1:%.*]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT3]], <4 x i32> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] @@ -21,8 +21,6 @@ define i8 @PR34687(i1 %c, i32 %x, i32 %n, i32 %divisor) { ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP6:%.*]] = sdiv <4 x i32> [[VEC_IND]], [[TMP0]] -; CHECK-NEXT: [[PREDPHI1:%.*]] = select i1 [[C]], <4 x i32> [[TMP6]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[VEC_PHI]], splat (i32 255) ; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[TMP1]], [[BROADCAST_SPLAT4]] ; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i8> @@ -32,6 +30,8 @@ define i8 @PR34687(i1 %c, i32 %x, i32 %n, i32 %divisor) { ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP6:%.*]] = sdiv <4 x i32> [[VEC_IND]], [[TMP9]] +; CHECK-NEXT: [[PREDPHI1:%.*]] = select i1 [[C]], <4 x i32> [[TMP6]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP7:%.*]] = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> [[TMP3]]) ; CHECK-NEXT: [[TMP8:%.*]] = zext i8 [[TMP7]] to i32 ; CHECK-NEXT: [[PREDPHI:%.*]] = extractelement <4 x i32> [[PREDPHI1]], i32 3 diff --git a/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll index 557c7e570766c..0b1c3165fe13a 100644 --- a/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll +++ b/llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll @@ -118,7 +118,7 @@ define void @runtime_checks_ptr_inductions(ptr %dst.1, ptr %dst.2, i1 %c) { ; CHECK-NEXT: [[SEL_DST_LCSSA:%.*]] = phi ptr [ [[SEL_DST]], %[[LOOP_1]] ] ; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; CHECK: [[VECTOR_MEMCHECK]]: -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[PTR_IV_1_LCSSA]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoaddr ptr [[PTR_IV_1_LCSSA]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[SEL_DST_LCSSA12]] ; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2 ; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] @@ -308,7 +308,7 @@ define void @expand_diff_neg_ptrtoint_expr(ptr %src, ptr %start) { ; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; CHECK: [[VECTOR_MEMCHECK]]: ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 0, [[SRC2]] -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoaddr ptr [[TMP1]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP5]], [[TMP0]] ; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP2]], 16 ; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] @@ -403,7 +403,7 @@ define void @scev_exp_reuse_const_add(ptr %dst, ptr %src) { ; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]] ; CHECK: [[VECTOR_MEMCHECK]]: ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 -2, [[SRC2]] -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR_IV_1_NEXT_LCSSA]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoaddr ptr [[PTR_IV_1_NEXT_LCSSA]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[TMP0]] ; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4 ; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] diff --git a/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll index 2bd87d95a8a80..68327a0e5e60b 100644 --- a/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll +++ b/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll @@ -630,12 +630,12 @@ define i32 @extract_second_last_iteration(ptr %cval, i32 %x) { ; CHECK-VF4UF1: [[VECTOR_BODY]]: ; CHECK-VF4UF1-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-VF4UF1-NEXT: [[VEC_IND:%.*]] = phi [ [[TMP6]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-VF4UF1-NEXT: [[TMP9:%.*]] = add [[VEC_IND]], [[BROADCAST_SPLAT]] ; CHECK-VF4UF1-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP3]] ; CHECK-VF4UF1-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], [[DOTSPLAT]] ; CHECK-VF4UF1-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-VF4UF1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] ; CHECK-VF4UF1: [[MIDDLE_BLOCK]]: +; CHECK-VF4UF1-NEXT: [[TMP9:%.*]] = add [[VEC_IND]], [[BROADCAST_SPLAT]] ; CHECK-VF4UF1-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32() ; CHECK-VF4UF1-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 4 ; CHECK-VF4UF1-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], 1 @@ -675,12 +675,12 @@ define i32 @extract_second_last_iteration(ptr %cval, i32 %x) { ; CHECK-VF4UF2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-VF4UF2-NEXT: [[STEP_ADD:%.*]] = phi [ [[TMP7]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT1:%.*]], %[[VECTOR_BODY]] ] ; CHECK-VF4UF2-NEXT: [[VEC_IND_NEXT:%.*]] = add [[STEP_ADD]], [[BROADCAST_SPLAT2]] -; CHECK-VF4UF2-NEXT: [[TMP9:%.*]] = add [[VEC_IND_NEXT]], [[BROADCAST_SPLAT]] ; CHECK-VF4UF2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP6]] ; CHECK-VF4UF2-NEXT: [[VEC_IND_NEXT1]] = add [[VEC_IND_NEXT]], [[BROADCAST_SPLAT2]] ; CHECK-VF4UF2-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-VF4UF2-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] ; CHECK-VF4UF2: [[MIDDLE_BLOCK]]: +; CHECK-VF4UF2-NEXT: [[TMP9:%.*]] = add [[VEC_IND_NEXT]], [[BROADCAST_SPLAT]] ; CHECK-VF4UF2-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32() ; CHECK-VF4UF2-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 4 ; CHECK-VF4UF2-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], 1 diff --git a/llvm/test/Transforms/LoopVectorize/select-folds.ll b/llvm/test/Transforms/LoopVectorize/select-folds.ll index 6e46f2d4670fd..44adf95a3f737 100644 --- a/llvm/test/Transforms/LoopVectorize/select-folds.ll +++ b/llvm/test/Transforms/LoopVectorize/select-folds.ll @@ -19,12 +19,12 @@ define i32 @select_not_cond_true_false(ptr %src, i64 %n) { ; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i8> [[WIDE_LOAD]] to <4 x i1> ; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i1> [[TMP2]], splat (i1 true) ; CHECK-NEXT: [[TMP5]] = zext <4 x i1> [[TMP3]] to <4 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[VECTOR_RECUR]], <4 x i32> [[TMP5]], <4 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP4]], splat (i32 1) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[VECTOR_RECUR]], <4 x i32> [[TMP5]], <4 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP9]], splat (i32 1) ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i32> [[TMP5]], i32 3 ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP6]], i32 3 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] diff --git a/llvm/test/Transforms/LoopVectorize/select-reduction.ll b/llvm/test/Transforms/LoopVectorize/select-reduction.ll index 1f5646d2a3090..bdbfcf842d507 100644 --- a/llvm/test/Transforms/LoopVectorize/select-reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/select-reduction.ll @@ -24,17 +24,17 @@ define i32 @test(i64 %N, i32 %x) { ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP2:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT2]], -; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[VEC_PHI]], splat (i32 10) ; CHECK-NEXT: [[TMP2]] = select <4 x i1> [[TMP1]], <4 x i32> [[VEC_PHI]], <4 x i32> splat (i32 10) -; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[TMP2]], <4 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT2]], +; CHECK-NEXT: [[TMP6:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[TMP2]], <4 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP3]]) ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: exit.loopexit: diff --git a/llvm/test/Transforms/LoopVectorize/sink-to-early-exit.ll b/llvm/test/Transforms/LoopVectorize/sink-to-early-exit.ll index 3d18e5a00280f..d40aac7f3b138 100644 --- a/llvm/test/Transforms/LoopVectorize/sink-to-early-exit.ll +++ b/llvm/test/Transforms/LoopVectorize/sink-to-early-exit.ll @@ -25,7 +25,6 @@ define i64 @sink_to_early_exit(i64 %offset) { ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP0]], align 1 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P2]], i64 [[INDEX2]] ; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1 -; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i8> [[WIDE_LOAD]], [[WIDE_LOAD3]] ; CHECK-NEXT: [[INDEX_NEXT4]] = add nuw i64 [[INDEX2]], 4 ; CHECK-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]] @@ -38,6 +37,7 @@ define i64 @sink_to_early_exit(i64 %offset) { ; CHECK: [[MIDDLE_BLOCK]]: ; CHECK-NEXT: br label %[[LOOP_END:.*]] ; CHECK: [[VECTOR_EARLY_EXIT]]: +; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[FIRST_ACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP3]], i1 false) ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[TMP2]], i64 [[FIRST_ACTIVE_LANE]] ; CHECK-NEXT: br label %[[LOOP_EARLY_EXIT:.*]] diff --git a/llvm/test/Transforms/LoopVectorize/step-vector-i1-wrapping.ll b/llvm/test/Transforms/LoopVectorize/step-vector-i1-wrapping.ll index bd7eae069cbd7..da8bc60a6b68e 100644 --- a/llvm/test/Transforms/LoopVectorize/step-vector-i1-wrapping.ll +++ b/llvm/test/Transforms/LoopVectorize/step-vector-i1-wrapping.ll @@ -10,11 +10,11 @@ define void @test() { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i1> [ , %[[VECTOR_PH]] ], [ [[VEC_IND]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = select <4 x i1> [[VEC_IND]], <4 x i32> splat (i32 1), <4 x i32> zeroinitializer ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], -4 ; CHECK-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[TMP0:%.*]] = select <4 x i1> [[VEC_IND]], <4 x i32> splat (i32 1), <4 x i32> zeroinitializer ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3 ; CHECK-NEXT: br label %[[SCALAR_PH:.*]] ; CHECK: [[SCALAR_PH]]: diff --git a/llvm/test/Transforms/LoopVectorize/store-reduction-results-in-tail-folded-loop.ll b/llvm/test/Transforms/LoopVectorize/store-reduction-results-in-tail-folded-loop.ll index 19ab96dd822b6..7aafd6dfc5937 100644 --- a/llvm/test/Transforms/LoopVectorize/store-reduction-results-in-tail-folded-loop.ll +++ b/llvm/test/Transforms/LoopVectorize/store-reduction-results-in-tail-folded-loop.ll @@ -26,19 +26,19 @@ define void @pr75298_store_reduction_value_in_folded_loop(i64 %iv.start) optsize ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP3:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT2]], -; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @c, align 4 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT3]], <4 x i32> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP3]] = xor <4 x i32> [[VEC_PHI]], [[BROADCAST_SPLAT4]] -; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT4]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT5]], +; CHECK-NEXT: [[TMP7:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP7]], <4 x i32> [[TMP3]], <4 x i32> [[VEC_PHI]] ; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP4]]) ; CHECK-NEXT: store i32 [[TMP6]], ptr @a, align 4 ; CHECK-NEXT: br label [[LOOP:%.*]] diff --git a/llvm/test/Transforms/LoopVectorize/struct-return.ll b/llvm/test/Transforms/LoopVectorize/struct-return.ll index 2f8acd641b571..83c87f1e15e8f 100644 --- a/llvm/test/Transforms/LoopVectorize/struct-return.ll +++ b/llvm/test/Transforms/LoopVectorize/struct-return.ll @@ -166,31 +166,28 @@ exit: ret void } -; CHECK-REMARKS: remark: {{.*}} vectorized loop +; TODO: Allow mixed-struct type vectorization and mark overflow intrinsics as trivially vectorizable. +; CHECK-REMARKS: remark: {{.*}} loop not vectorized: call instruction cannot be vectorized define void @test_overflow_intrinsic(ptr noalias readonly %in, ptr noalias writeonly %out_a, ptr noalias writeonly %out_b) { ; CHECK-LABEL: define void @test_overflow_intrinsic( ; CHECK-SAME: ptr noalias readonly [[IN:%.*]], ptr noalias writeonly [[OUT_A:%.*]], ptr noalias writeonly [[OUT_B:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: br label %[[VECTOR_PH:.*]] -; CHECK: [[VECTOR_PH]]: -; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] -; CHECK: [[VECTOR_BODY]]: -; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br label %[[FOR_BODY:.*]] +; CHECK: [[FOR_BODY]]: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[IN]], i64 [[IV]] -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[ARRAYIDX]], align 4 -; CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i32>, <2 x i1> } @llvm.sadd.with.overflow.v2i32(<2 x i32> [[WIDE_LOAD]], <2 x i32> [[WIDE_LOAD]]) -; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP1]], 0 -; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i32>, <2 x i1> } [[TMP1]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = zext <2 x i1> [[TMP3]] to <2 x i8> +; CHECK-NEXT: [[IN_VAL:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[CALL:%.*]] = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[IN_VAL]], i32 [[IN_VAL]]) +; CHECK-NEXT: [[EXTRACT_RET:%.*]] = extractvalue { i32, i1 } [[CALL]], 0 +; CHECK-NEXT: [[EXTRACT_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[CALL]], 1 +; CHECK-NEXT: [[ZEXT_OVERFLOW:%.*]] = zext i1 [[EXTRACT_OVERFLOW]] to i8 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[OUT_A]], i64 [[IV]] -; CHECK-NEXT: store <2 x i32> [[TMP2]], ptr [[ARRAYIDX2]], align 4 +; CHECK-NEXT: store i32 [[EXTRACT_RET]], ptr [[ARRAYIDX2]], align 4 ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[OUT_B]], i64 [[IV]] -; CHECK-NEXT: store <2 x i8> [[TMP4]], ptr [[ARRAYIDX4]], align 4 -; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 2 +; CHECK-NEXT: store i8 [[ZEXT_OVERFLOW]], ptr [[ARRAYIDX4]], align 4 +; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 ; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024 -; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] -; CHECK: [[MIDDLE_BLOCK]]: -; CHECK-NEXT: br label %[[EXIT:.*]] +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; diff --git a/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll b/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll index 541ee96ac760b..fc0582b752341 100644 --- a/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll +++ b/llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll @@ -162,15 +162,15 @@ define i64 @live_out_scalar_vf(i64 %n) { ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) ; CHECK-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) ; CHECK-NEXT: [[STEP_ADD_3]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) -; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt <4 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i64> [[STEP_ADD_2]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt <4 x i64> [[STEP_ADD_3]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 16 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: middle.block: +; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt <4 x i64> [[STEP_ADD]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i64> [[STEP_ADD_2]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt <4 x i64> [[STEP_ADD_3]], [[BROADCAST_SPLAT]] ; CHECK-NEXT: [[FIRST_INACTIVE_LANE:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP4]], i1 false) ; CHECK-NEXT: [[TMP6:%.*]] = add i64 12, [[FIRST_INACTIVE_LANE]] ; CHECK-NEXT: [[FIRST_INACTIVE_LANE1:%.*]] = call i64 @llvm.experimental.cttz.elts.i64.v4i1(<4 x i1> [[TMP3]], i1 false) diff --git a/llvm/test/Transforms/LoopVectorize/uniform-blend.ll b/llvm/test/Transforms/LoopVectorize/uniform-blend.ll index 24dc182fe24a1..38bdd782257a5 100644 --- a/llvm/test/Transforms/LoopVectorize/uniform-blend.ll +++ b/llvm/test/Transforms/LoopVectorize/uniform-blend.ll @@ -13,8 +13,7 @@ define void @blend_uniform_iv_trunc(i1 %c) { ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDEX]] to i16 -; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[C]], i16 [[TMP0]], i16 poison -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i16 [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i16 [[TMP0]] ; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr [[TMP7]], align 2 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 32 @@ -36,7 +35,7 @@ loop.next: ; preds = %loop.header br label %loop.latch loop.latch: ; preds = %loop.next, %loop.header - %blend = phi i16 [ poison, %loop.header ], [ %iv.trunc.2, %loop.next ] + %blend = phi i16 [ %iv.trunc.2, %loop.header ], [ %iv.trunc.2, %loop.next ] %dst.ptr = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i16 %blend store i16 0, ptr %dst.ptr %iv.next = add nuw nsw i64 %iv, 1 @@ -55,11 +54,10 @@ define void @blend_uniform_iv(i1 %c) { ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: -; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[C]], i64 [[INDEX]], i64 poison +; CHECK-NEXT: [[TMP6:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP6]] ; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr [[TMP7]], align 2 -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP6]], 4 ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 32 ; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: @@ -79,7 +77,7 @@ loop.next: ; preds = %loop.header br label %loop.latch loop.latch: ; preds = %loop.next, %loop.header - %blend = phi i64 [ poison, %loop.header ], [ %iv, %loop.next ] + %blend = phi i64 [ %iv, %loop.header ], [ %iv, %loop.next ] %dst.ptr = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 %blend store i16 0, ptr %dst.ptr %iv.next = add nuw nsw i64 %iv, 1 @@ -99,12 +97,10 @@ define void @blend_chain_iv(i1 %c) { ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[PREDPHI1:%.*]] = phi <4 x i64> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[PREDPHI2:%.*]] = select i1 [[C]], <4 x i64> [[PREDPHI1]], <4 x i64> poison -; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 0 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 1 -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 2 -; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[PREDPHI2]], i32 3 +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP1]] ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP3]] ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP5]] @@ -114,7 +110,6 @@ define void @blend_chain_iv(i1 %c) { ; CHECK-NEXT: store i16 0, ptr [[TMP6]], align 2 ; CHECK-NEXT: store i16 0, ptr [[TMP8]], align 2 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[PREDPHI1]], splat (i64 4) ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 32 ; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: @@ -137,11 +132,11 @@ loop.next.2: br label %loop.next.3 loop.next.3: - %blend.1 = phi i64 [ poison, %loop.next ], [ %iv, %loop.next.2 ] + %blend.1 = phi i64 [ %iv, %loop.next ], [ %iv, %loop.next.2 ] br label %loop.latch loop.latch: ; preds = %loop.next, %loop.header - %blend = phi i64 [ poison, %loop.header ], [ %blend.1, %loop.next.3 ] + %blend = phi i64 [ %iv, %loop.header ], [ %blend.1, %loop.next.3 ] %dst.ptr = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 %blend store i16 0, ptr %dst.ptr %iv.next = add nuw nsw i64 %iv, 1 @@ -251,10 +246,57 @@ exit: ret void } +; Test that blend is optimized away when other incoming values are poison. + +define void @blend_poison(ptr %p, i1 %c) { +; CHECK-LABEL: define void @blend_poison( +; CHECK-SAME: ptr [[P:%.*]], i1 [[C:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: br label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[P]], i64 [[INDEX]] +; CHECK-NEXT: store <4 x i64> [[VEC_IND]], ptr [[TMP0]], align 4 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4) +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], 32 +; CHECK-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: br label %[[EXIT:.*]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ] + br i1 %c, label %if, label %latch + +if: + br label %latch + +latch: + %blend = phi i64 [ poison, %loop ], [ %iv, %if ] + %gep = getelementptr i64, ptr %p, i64 %iv + store i64 %blend, ptr %gep + %iv.next = add nuw nsw i64 %iv, 1 + %ec = icmp ult i64 %iv, 31 + br i1 %ec, label %loop, label %exit + +exit: + ret void +} + + ;. ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} ; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} ; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]} ; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]} ;. diff --git a/llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll b/llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll index 0f191b2d8a278..63be2fd7bd8a8 100644 --- a/llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll +++ b/llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll @@ -13,15 +13,14 @@ define void @ld_and_neg1_step1_start0_ind1(ptr noalias %A, ptr noalias %B) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[INDEX]], -1 -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP1]], align 8 -; CHECK-NEXT: [[TMP2:%.*]] = add nsw <2 x i64> [[WIDE_LOAD]], splat (i64 42) -; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[INDEX]] -; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr [[TMP3]], align 8 +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP0]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = add nsw <2 x i64> [[WIDE_LOAD]], splat (i64 42) +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[INDEX]] +; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr [[TMP2]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000 -; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000 +; CHECK-NEXT: br i1 [[TMP3]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: @@ -147,30 +146,25 @@ define void @ld_and_neg1_step2_start0_ind1(ptr noalias %A, ptr noalias %B) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[VEC_IND]], splat (i64 -1) -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP2]], i32 0 -; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP2]], i32 1 -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP4]] -; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP5]], align 8 -; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP6]], align 8 -; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> poison, i64 [[TMP7]], i32 0 -; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i64> [[TMP9]], i64 [[TMP8]], i32 1 -; CHECK-NEXT: [[TMP11:%.*]] = add nsw <2 x i64> [[TMP10]], splat (i64 42) -; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i64> [[TMP11]], i32 0 -; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i64> [[TMP11]], i32 1 -; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP1]] -; CHECK-NEXT: store i64 [[TMP12]], ptr [[TMP14]], align 8 -; CHECK-NEXT: store i64 [[TMP13]], ptr [[TMP15]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP3]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> [[TMP6]], i64 [[TMP5]], i32 1 +; CHECK-NEXT: [[TMP8:%.*]] = add nsw <2 x i64> [[TMP7]], splat (i64 42) +; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP8]], i32 0 +; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP8]], i32 1 +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP11]], align 8 +; CHECK-NEXT: store i64 [[TMP10]], ptr [[TMP12]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 -; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i64> [[VEC_IND]], splat (i64 4) -; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 500 -; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 500 +; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: @@ -249,30 +243,25 @@ define void @ld_and_neg1_step3_start0_ind1(ptr noalias %A, ptr noalias %B) { ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 3 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 3 -; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i64> [[VEC_IND]], splat (i64 -1) -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP2]], i32 0 -; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP2]], i32 1 -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP4]] -; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP5]], align 8 -; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP6]], align 8 -; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> poison, i64 [[TMP7]], i32 0 -; CHECK-NEXT: [[TMP10:%.*]] = insertelement <2 x i64> [[TMP9]], i64 [[TMP8]], i32 1 -; CHECK-NEXT: [[TMP11:%.*]] = add nsw <2 x i64> [[TMP10]], splat (i64 42) -; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i64> [[TMP11]], i32 0 -; CHECK-NEXT: [[TMP13:%.*]] = extractelement <2 x i64> [[TMP11]], i32 1 -; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] -; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP1]] -; CHECK-NEXT: store i64 [[TMP12]], ptr [[TMP14]], align 8 -; CHECK-NEXT: store i64 [[TMP13]], ptr [[TMP15]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP3]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0 +; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> [[TMP6]], i64 [[TMP5]], i32 1 +; CHECK-NEXT: [[TMP8:%.*]] = add nsw <2 x i64> [[TMP7]], splat (i64 42) +; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP8]], i32 0 +; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i64> [[TMP8]], i32 1 +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP11]], align 8 +; CHECK-NEXT: store i64 [[TMP10]], ptr [[TMP12]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 -; CHECK-NEXT: [[VEC_IND_NEXT]] = add nsw <2 x i64> [[VEC_IND]], splat (i64 6) -; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 332 -; CHECK-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 332 +; CHECK-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: br label [[SCALAR_PH:%.*]] ; CHECK: scalar.ph: diff --git a/llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll b/llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll index 5d07341263bc2..feab77583a594 100644 --- a/llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll +++ b/llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll @@ -4,9 +4,9 @@ target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" ; Test cases for https://github.com/llvm/llvm-project/issues/87410. -define void @test_not_first_lane_only_constant(ptr %A, ptr noalias %B) { +define void @test_not_first_lane_only_constant(ptr %A, ptr noalias %B, ptr noalias %C) { ; CHECK-LABEL: define void @test_not_first_lane_only_constant( -; CHECK-SAME: ptr [[A:%.*]], ptr noalias [[B:%.*]]) { +; CHECK-SAME: ptr [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) { ; CHECK-NEXT: entry: ; CHECK-NEXT: br label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: @@ -45,7 +45,7 @@ else.2: br label %loop.latch loop.latch: - %merge = phi ptr [ %B, %else.2 ], [ poison, %loop.header ] + %merge = phi ptr [ %B, %else.2 ], [ %C, %loop.header ] %l = load i16, ptr %merge, align 2 %iv.next = add i16 %iv, 1 store i16 %l, ptr %gep.A @@ -67,11 +67,7 @@ define void @test_not_first_lane_only_wide_compare(ptr %A, ptr noalias %B, i16 % ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[A]], i16 [[OFFSET_IDX]] -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP1]], align 2 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i16> [[WIDE_LOAD]], i32 0 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i16 [[TMP3]], [[X]] -; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP4]], ptr poison, ptr [[B]] -; CHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[TMP12]], align 2 +; CHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[B]], align 2 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <4 x i16> poison, i16 [[TMP13]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT5]], <4 x i16> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: store <4 x i16> [[BROADCAST_SPLAT6]], ptr [[TMP1]], align 2 @@ -104,7 +100,7 @@ else.2: br label %loop.latch loop.latch: - %merge = phi ptr [ %B, %else.2 ], [ poison, %loop.header ] + %merge = phi ptr [ %B, %else.2 ], [ %B, %loop.header ] %l = load i16, ptr %merge, align 2 %iv.next = add i16 %iv, 1 store i16 %l, ptr %gep.A @@ -126,11 +122,7 @@ define void @test_not_first_lane_only_wide_compare_incoming_order_swapped(ptr %A ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16 ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[A]], i16 [[OFFSET_IDX]] -; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP1]], align 2 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i16> [[WIDE_LOAD]], i32 0 -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i16 [[TMP3]], [[X]] -; CHECK-NEXT: [[PREDPHI:%.*]] = select i1 [[TMP4]], ptr poison, ptr [[B]] -; CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[PREDPHI]], align 2 +; CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[B]], align 2 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <4 x i16> poison, i16 [[TMP12]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT3]], <4 x i16> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: store <4 x i16> [[BROADCAST_SPLAT4]], ptr [[TMP1]], align 2 diff --git a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll index 277adfabb7c5c..b93215035cebf 100644 --- a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll +++ b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination-early-exit.ll @@ -341,8 +341,6 @@ define i1 @test_early_exit_max_tc_less_than_16_non_canonical_iv(ptr dereferencea ; VF8UF1-NEXT: [[OFFSET_IDX:%.*]] = add i64 2, [[INDEX]] ; VF8UF1-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[OFFSET_IDX]] ; VF8UF1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1 -; VF8UF1-NEXT: [[TMP1:%.*]] = zext <8 x i8> [[WIDE_LOAD]] to <8 x i64> -; VF8UF1-NEXT: [[TMP2:%.*]] = icmp eq <8 x i64> [[TMP1]], [[VEC_IND]] ; VF8UF1-NEXT: [[TMP3:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer ; VF8UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; VF8UF1-NEXT: [[TMP4:%.*]] = freeze <8 x i1> [[TMP3]] @@ -353,6 +351,8 @@ define i1 @test_early_exit_max_tc_less_than_16_non_canonical_iv(ptr dereferencea ; VF8UF1: [[VECTOR_BODY_INTERIM]]: ; VF8UF1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] ; VF8UF1: [[MIDDLE_BLOCK]]: +; VF8UF1-NEXT: [[TMP9:%.*]] = zext <8 x i8> [[WIDE_LOAD]] to <8 x i64> +; VF8UF1-NEXT: [[TMP2:%.*]] = icmp eq <8 x i64> [[TMP9]], [[VEC_IND]] ; VF8UF1-NEXT: [[TMP8:%.*]] = extractelement <8 x i1> [[TMP2]], i32 7 ; VF8UF1-NEXT: br label %[[EXIT:.*]] ; VF8UF1: [[VECTOR_EARLY_EXIT]]: @@ -376,8 +376,6 @@ define i1 @test_early_exit_max_tc_less_than_16_non_canonical_iv(ptr dereferencea ; VF8UF2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8 ; VF8UF2-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i8>, ptr [[TMP0]], align 1 ; VF8UF2-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i8>, ptr [[TMP1]], align 1 -; VF8UF2-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[WIDE_LOAD1]] to <8 x i64> -; VF8UF2-NEXT: [[TMP3:%.*]] = icmp eq <8 x i64> [[TMP2]], [[STEP_ADD]] ; VF8UF2-NEXT: [[TMP4:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer ; VF8UF2-NEXT: [[TMP5:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD1]], zeroinitializer ; VF8UF2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 @@ -390,6 +388,8 @@ define i1 @test_early_exit_max_tc_less_than_16_non_canonical_iv(ptr dereferencea ; VF8UF2: [[VECTOR_BODY_INTERIM]]: ; VF8UF2-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; VF8UF2: [[MIDDLE_BLOCK]]: +; VF8UF2-NEXT: [[TMP10:%.*]] = zext <8 x i8> [[WIDE_LOAD1]] to <8 x i64> +; VF8UF2-NEXT: [[TMP3:%.*]] = icmp eq <8 x i64> [[TMP10]], [[STEP_ADD]] ; VF8UF2-NEXT: [[TMP12:%.*]] = extractelement <8 x i1> [[TMP3]], i32 7 ; VF8UF2-NEXT: br label %[[EXIT:.*]] ; VF8UF2: [[VECTOR_EARLY_EXIT]]: @@ -410,8 +410,6 @@ define i1 @test_early_exit_max_tc_less_than_16_non_canonical_iv(ptr dereferencea ; VF16UF1-NEXT: [[OFFSET_IDX:%.*]] = add i64 2, [[INDEX]] ; VF16UF1-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[OFFSET_IDX]] ; VF16UF1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP0]], align 1 -; VF16UF1-NEXT: [[TMP1:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i64> -; VF16UF1-NEXT: [[TMP2:%.*]] = icmp eq <16 x i64> [[TMP1]], [[VEC_IND]] ; VF16UF1-NEXT: [[TMP3:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], zeroinitializer ; VF16UF1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; VF16UF1-NEXT: [[TMP4:%.*]] = freeze <16 x i1> [[TMP3]] @@ -421,6 +419,8 @@ define i1 @test_early_exit_max_tc_less_than_16_non_canonical_iv(ptr dereferencea ; VF16UF1: [[VECTOR_BODY_INTERIM]]: ; VF16UF1-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] ; VF16UF1: [[MIDDLE_BLOCK]]: +; VF16UF1-NEXT: [[TMP6:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i64> +; VF16UF1-NEXT: [[TMP2:%.*]] = icmp eq <16 x i64> [[TMP6]], [[VEC_IND]] ; VF16UF1-NEXT: [[TMP8:%.*]] = extractelement <16 x i1> [[TMP2]], i32 15 ; VF16UF1-NEXT: br label %[[EXIT:.*]] ; VF16UF1: [[VECTOR_EARLY_EXIT]]: diff --git a/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll b/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll index 9f0a528bfa889..5b68887f0f7da 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-print-after-all.ll @@ -6,6 +6,7 @@ ; CHECK: VPlan after printAfterInitialConstruction ; CHECK: VPlan after VPlanTransforms::clearReductionWrapFlags +; CHECK: VPlan after VPlanTransforms::optimizeFindIVReductions ; CHECK: VPlan after VPlanTransforms::handleMultiUseReductions ; CHECK: VPlan after VPlanTransforms::handleMaxMinNumReductions ; CHECK: VPlan after VPlanTransforms::handleFindLastReductions @@ -45,7 +46,7 @@ ; CHECK-DUMP: VPlan after printAfterInitialConstruction ; CHECK-DUMP-NEXT: VPlan ' for UF>=1' { ; -; CHECK-DUMP: VPlan after VPlanTransforms::optimize +; CHECK-DUMP: VPlan after VPlanTransforms::optimize{{$}} ; CHECK-DUMP-NEXT: VPlan 'Initial VPlan for VF={4},UF>=1' { ; ; CHECK-DUMP: VPlan after printFinalVPlan diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll index 5fbc12448400d..027bfe859c828 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing-metadata.ll @@ -1,22 +1,66 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 ; REQUIRES: asserts ; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s define void @test_widen_metadata(ptr noalias %A, ptr noalias %B, i32 %n) { -; CHECK-LABEL: Checking a loop in 'test_widen_metadata' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK: vector loop: { -; CHECK: vector.body: -; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> (!tbaa ![[TBAA:[0-9]+]]) -; CHECK: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float (!fpmath ![[FPMATH:[0-9]+]]) -; CHECK: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00> (!fpmath ![[FPMATH]]) -; CHECK: WIDEN-CAST ir<%conv.back> = fptosi ir<%mul> to i32 -; CHECK: WIDEN store vp<{{.*}}>, ir<%conv.back> (!tbaa ![[TBAA]]) -; CHECK: ir-bb: -; CHECK: IR %lv = load i32, ptr %gep.A, align 4, !tbaa ![[TBAA]] -; CHECK: IR %conv = sitofp i32 %lv to float, !fpmath ![[FPMATH]] -; CHECK: IR %mul = fmul float %conv, 2.000000e+00, !fpmath ![[FPMATH]] -; CHECK: IR store i32 %conv.back, ptr %gep.B, align 4, !tbaa ![[TBAA]] +; CHECK-LABEL: 'test_widen_metadata' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.A> = getelementptr inbounds ir<%A>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.A> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> (!tbaa !0) +; CHECK-NEXT: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float (!fpmath !4) +; CHECK-NEXT: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00> (!fpmath !4) +; CHECK-NEXT: WIDEN-CAST ir<%conv.back> = fptosi ir<%mul> to i32 +; CHECK-NEXT: CLONE ir<%gep.B> = getelementptr inbounds ir<%B>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%gep.B> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%conv.back> (!tbaa !0) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep.A = getelementptr inbounds i32, ptr %A, i32 %i +; CHECK-NEXT: IR %lv = load i32, ptr %gep.A, align 4, !tbaa !0, !range !3 +; CHECK-NEXT: IR %conv = sitofp i32 %lv to float, !fpmath !4 +; CHECK-NEXT: IR %mul = fmul float %conv, 2.000000e+00, !fpmath !4 +; CHECK-NEXT: IR %conv.back = fptosi float %mul to i32 +; CHECK-NEXT: IR %gep.B = getelementptr inbounds i32, ptr %B, i32 %i +; CHECK-NEXT: IR store i32 %conv.back, ptr %gep.B, align 4, !tbaa !0 +; CHECK-NEXT: IR %i.next = add i32 %i, 1 +; CHECK-NEXT: IR %cond = icmp eq i32 %i.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -41,17 +85,59 @@ exit: declare float @llvm.sqrt.f32(float) define void @test_intrinsic_with_metadata(ptr noalias %A, ptr noalias %B, i32 %n) { -; CHECK-LABEL: Checking a loop in 'test_intrinsic_with_metadata' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK: vector loop: { -; CHECK: vector.body: -; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> (!tbaa ![[TBAA2:[0-9]+]]) -; CHECK: WIDEN-INTRINSIC ir<%sqrt> = call llvm.sqrt(ir<%lv>) (!fpmath ![[FPMATH2:[0-9]+]]) -; CHECK: WIDEN store vp<{{.*}}>, ir<%sqrt> (!tbaa ![[TBAA2]]) -; CHECK: ir-bb: -; CHECK: IR %lv = load float, ptr %gep.A, align 4, !tbaa ![[TBAA2]] -; CHECK: IR %sqrt = call float @llvm.sqrt.f32(float %lv), !fpmath ![[FPMATH2]] -; CHECK: IR store float %sqrt, ptr %gep.B, align 4, !tbaa ![[TBAA2]] +; CHECK-LABEL: 'test_intrinsic_with_metadata' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.A> = getelementptr inbounds ir<%A>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.A> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> (!tbaa !0) +; CHECK-NEXT: WIDEN-INTRINSIC ir<%sqrt> = call llvm.sqrt(ir<%lv>) (!fpmath !3) +; CHECK-NEXT: CLONE ir<%gep.B> = getelementptr inbounds ir<%B>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%gep.B> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%sqrt> (!tbaa !0) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep.A = getelementptr inbounds float, ptr %A, i32 %i +; CHECK-NEXT: IR %lv = load float, ptr %gep.A, align 4, !tbaa !0 +; CHECK-NEXT: IR %sqrt = call float @llvm.sqrt.f32(float %lv), !fpmath !3 +; CHECK-NEXT: IR %gep.B = getelementptr inbounds float, ptr %B, i32 %i +; CHECK-NEXT: IR store float %sqrt, ptr %gep.B, align 4, !tbaa !0 +; CHECK-NEXT: IR %i.next = add i32 %i, 1 +; CHECK-NEXT: IR %cond = icmp eq i32 %i.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -72,18 +158,63 @@ exit: } define void @test_widen_with_multiple_metadata(ptr noalias %A, ptr noalias %B, i32 %n) { -; CHECK-LABEL: Checking a loop in 'test_widen_with_multiple_metadata' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK: vector loop: { -; CHECK: vector.body: -; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> (!tbaa ![[TBAA3:[0-9]+]]) -; CHECK: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float -; CHECK: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00> -; CHECK: WIDEN-CAST ir<%conv.back> = fptosi ir<%mul> to i32 -; CHECK: WIDEN store vp<{{.*}}>, ir<%conv.back> (!tbaa ![[TBAA3]]) -; CHECK: ir-bb: -; CHECK: IR %lv = load i32, ptr %gep.A, align 4, !tbaa ![[TBAA3]] -; CHECK: IR store i32 %conv.back, ptr %gep.B, align 4, !tbaa ![[TBAA3]] +; CHECK-LABEL: 'test_widen_with_multiple_metadata' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.A> = getelementptr inbounds ir<%A>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.A> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> (!tbaa !0) +; CHECK-NEXT: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float +; CHECK-NEXT: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00> +; CHECK-NEXT: WIDEN-CAST ir<%conv.back> = fptosi ir<%mul> to i32 +; CHECK-NEXT: CLONE ir<%gep.B> = getelementptr inbounds ir<%B>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%gep.B> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%conv.back> (!tbaa !0) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep.A = getelementptr inbounds i32, ptr %A, i32 %i +; CHECK-NEXT: IR %lv = load i32, ptr %gep.A, align 4, !tbaa !0, !range !3 +; CHECK-NEXT: IR %conv = sitofp i32 %lv to float +; CHECK-NEXT: IR %mul = fmul float %conv, 2.000000e+00 +; CHECK-NEXT: IR %conv.back = fptosi float %mul to i32 +; CHECK-NEXT: IR %gep.B = getelementptr inbounds i32, ptr %B, i32 %i +; CHECK-NEXT: IR store i32 %conv.back, ptr %gep.B, align 4, !tbaa !0 +; CHECK-NEXT: IR %i.next = add i32 %i, 1 +; CHECK-NEXT: IR %cond = icmp eq i32 %i.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll index 4d026daca115c..b282a9079c996 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing-reductions.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 ; REQUIRES: asserts ; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -prefer-inloop-reductions -disable-output %s 2>&1 | FileCheck %s @@ -5,55 +6,60 @@ ; Tests for printing VPlans with reductions. define float @print_reduction(i64 %n, ptr noalias %y) { -; CHECK-LABEL: Checking a loop in 'print_reduction' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector fast ir<0.000000e+00>, ir<0.000000e+00>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[RDX_START]]>, ir<%red.next> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%arrayidx> -; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>) -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RED_RES:%.+]]> = compute-reduction-result (fadd, in-loop) fast ir<%red.next> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: IR %red.next.lcssa = phi float [ %red.next, %loop ] (extra operand: vp<[[RED_RES]]> from middle.block) -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RED_RESUME:%.+]]> = phi [ vp<[[RED_RES]]>, middle.block ], [ ir<0.000000e+00>, ir-bb ] +; CHECK-LABEL: 'print_reduction' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector fast ir<0.000000e+00>, ir<0.000000e+00>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[VP3]]>, ir<%red.next> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP6]]> +; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = compute-reduction-result (fadd, in-loop) fast ir<%red.next> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %red.next.lcssa = phi float [ %red.next, %loop ] (extra operand: vp<[[VP8]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP8]]>, middle.block ], [ ir<0.000000e+00>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %red = phi float [ %red.next, %loop ], [ 0.000000e+00, %entry ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds float, ptr %y, i64 %iv +; CHECK-NEXT: IR %lv = load float, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %red.next = fadd fast float %lv, %red +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i64 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -73,56 +79,61 @@ exit: ; preds = %loop, %entry } define void @print_reduction_with_invariant_store(i64 %n, ptr noalias %y, ptr noalias %dst) { -; CHECK-LABEL: Checking a loop in 'print_reduction_with_invariant_store' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector fast ir<0.000000e+00>, ir<0.000000e+00>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[RDX_START]]>, ir<%red.next> -; CHECK-NEXT: vp<[[IV:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[IV]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%arrayidx> -; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>) -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RED_RES:.+]]> = compute-reduction-result (fadd, in-loop) fast ir<%red.next> -; CHECK-NEXT: CLONE store vp<[[RED_RES]]>, ir<%dst> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RED_RESUME:%.+]]> = phi [ vp<[[RED_RES]]>, middle.block ], [ ir<0.000000e+00>, ir-bb ] +; CHECK-LABEL: 'print_reduction_with_invariant_store' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector fast ir<0.000000e+00>, ir<0.000000e+00>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[VP3]]>, ir<%red.next> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP6]]> +; CHECK-NEXT: REDUCE ir<%red.next> = ir<%red> + fast reduce.fadd (ir<%lv>) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = compute-reduction-result (fadd, in-loop) fast ir<%red.next> +; CHECK-NEXT: CLONE store vp<[[VP8]]>, ir<%dst> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP8]]>, middle.block ], [ ir<0.000000e+00>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK-NEXT: IR %red = phi float [ %red.next, %loop ], [ 0.000000e+00, %entry ] -; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %red = phi float [ %red.next, %loop ], [ 0.000000e+00, %entry ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds float, ptr %y, i64 %iv +; CHECK-NEXT: IR %lv = load float, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %red.next = fadd fast float %lv, %red +; CHECK-NEXT: IR store float %red.next, ptr %dst, align 4 +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i64 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -143,60 +154,67 @@ exit: ; preds = %loop, %entry } define float @print_fmuladd_strict(ptr %a, ptr %b, i64 %n) { -; CHECK-LABEL: Checking a loop in 'print_fmuladd_strict' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector nnan ninf nsz ir<0.000000e+00>, ir<0.000000e+00>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%sum.07> = phi vp<[[RDX_START]]>, ir<%muladd> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%arrayidx> -; CHECK-NEXT: WIDEN ir<%l.a> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%b>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%arrayidx2> -; CHECK-NEXT: WIDEN ir<%l.b> = load vp<[[VEC_PTR2]]> -; CHECK-NEXT: EMIT vp<[[FMUL:%.+]]> = fmul nnan ninf nsz ir<%l.a>, ir<%l.b> -; CHECK-NEXT: REDUCE ir<[[MULADD:%.+]]> = ir<%sum.07> + nnan ninf nsz reduce.fadd (vp<[[FMUL]]>) -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RED_RES:%.+]]> = compute-reduction-result (fadd, in-loop) nnan ninf nsz ir<[[MULADD]]> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: IR %muladd.lcssa = phi float [ %muladd, %loop ] (extra operand: vp<[[RED_RES]]> from middle.block) -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RED_RESUME:%.+]]> = phi [ vp<[[RED_RES]]>, middle.block ], [ ir<0.000000e+00>, ir-bb ] +; CHECK-LABEL: 'print_fmuladd_strict' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector nnan ninf nsz ir<0.000000e+00>, ir<0.000000e+00>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%sum.07> = phi vp<[[VP3]]>, ir<%muladd> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%l.a> = load vp<[[VP6]]> +; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%b>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx2> +; CHECK-NEXT: WIDEN ir<%l.b> = load vp<[[VP7]]> +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = fmul nnan ninf nsz ir<%l.a>, ir<%l.b> +; CHECK-NEXT: REDUCE ir<%muladd> = ir<%sum.07> + nnan ninf nsz reduce.fadd (vp<[[VP8]]>) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = compute-reduction-result (fadd, in-loop) nnan ninf nsz ir<%muladd> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %muladd.lcssa = phi float [ %muladd, %loop ] (extra operand: vp<[[VP10]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP10]]>, middle.block ], [ ir<0.000000e+00>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK-NEXT: IR %sum.07 = phi float [ 0.000000e+00, %entry ], [ %muladd, %loop ] (extra operand: vp<[[RED_RESUME]]> from scalar.ph) -; CHECK: IR %exitcond.not = icmp eq i64 %iv.next, %n -; CHECK-NEXT: No successors -; CHECK-NEXT:} +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %sum.07 = phi float [ 0.000000e+00, %entry ], [ %muladd, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv +; CHECK-NEXT: IR %l.a = load float, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %arrayidx2 = getelementptr inbounds float, ptr %b, i64 %iv +; CHECK-NEXT: IR %l.b = load float, ptr %arrayidx2, align 4 +; CHECK-NEXT: IR %muladd = tail call nnan ninf nsz float @llvm.fmuladd.f32(float %l.a, float %l.b, float %sum.07) +; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 1 +; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %loop @@ -218,40 +236,64 @@ exit: } define i64 @find_last_iv(ptr %a, i64 %n, i64 %start) { -; CHECK-LABEL: Checking a loop in 'find_last_iv' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> -; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<{{.+}}> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi ir<-9223372036854775808>, ir<%cond> -; CHECK-NEXT: vp<[[SCALAR_STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr inbounds ir<%a>, vp<[[SCALAR_STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.a> -; CHECK-NEXT: WIDEN ir<%l.a> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN ir<%cmp2> = icmp eq ir<%l.a>, ir<%start> -; CHECK-NEXT: WIDEN ir<%cond> = select ir<%cmp2>, ir<%iv>, ir<%rdx> -; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[CAN_IV]]>, vp<{{.+}}> -; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<{{.+}}> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RDX_VAL:%.+]]> = compute-reduction-result (smax) ir<%cond> -; CHECK-NEXT: EMIT vp<[[RDX_CMP:%.+]]> = icmp ne vp<[[RDX_VAL]]>, ir<-9223372036854775808> -; CHECK-NEXT: EMIT vp<[[RDX_RES:%.+]]> = select vp<[[RDX_CMP]]>, vp<[[RDX_VAL]]>, ir<%start> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<{{.+}}> -; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK: ir-bb: -; CHECK-NEXT: IR %cond.lcssa = phi i64 [ %cond, %loop ] (extra operand: vp<[[RDX_RES]]> from middle.block) -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph: -; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<{{.+}}>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[RDX_RES]]>, middle.block ], [ ir<%start>, ir-bb ] +; CHECK-LABEL: 'find_last_iv' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi ir<-9223372036854775808>, ir<%cond> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr inbounds ir<%a>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.a> +; CHECK-NEXT: WIDEN ir<%l.a> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN ir<%cmp2> = icmp eq ir<%l.a>, ir<%start> +; CHECK-NEXT: WIDEN ir<%cond> = select ir<%cmp2>, ir<%iv>, ir<%rdx> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (smax) ir<%cond> +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = icmp ne vp<[[VP7]]>, ir<-9223372036854775808> +; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = select vp<[[VP8]]>, vp<[[VP7]]>, ir<%start> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %cond.lcssa = phi i64 [ %cond, %loop ] (extra operand: vp<[[VP9]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP9]]>, middle.block ], [ ir<%start>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %inc, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rdx = phi i64 [ %start, %entry ], [ %cond, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %gep.a = getelementptr inbounds i64, ptr %a, i64 %iv +; CHECK-NEXT: IR %l.a = load i64, ptr %gep.a, align 8 +; CHECK-NEXT: IR %cmp2 = icmp eq i64 %l.a, %start +; CHECK-NEXT: IR %cond = select i1 %cmp2, i64 %iv, i64 %rdx +; CHECK-NEXT: IR %inc = add nuw nsw i64 %iv, 1 +; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %inc, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -273,29 +315,60 @@ exit: define i64 @print_extended_reduction(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) { ; CHECK-LABEL: 'print_extended_reduction' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1> -; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR:%.+]]> = vector-pointer inbounds ir<%arrayidx> -; CHECK-NEXT: WIDEN ir<[[LOAD:%.+]]> = load vp<[[ADDR]]> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (ir<[[LOAD]]> zext to i64) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi vp<[[VP3]]>, vp<[[VP7:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]> +; CHECK-NEXT: EXPRESSION vp<[[VP7]]> = ir<%rdx> + reduce.add (ir<%load0> zext to i64) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP7]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %r.0.lcssa = phi i64 [ %rdx.next, %loop ] (extra operand: vp<[[VP9]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP9]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds i32, ptr %x, i32 %iv +; CHECK-NEXT: IR %load0 = load i32, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %conv0 = zext i32 %load0 to i64 +; CHECK-NEXT: IR %rdx.next = add nsw i64 %rdx, %conv0 +; CHECK-NEXT: IR %iv.next = add nuw nsw i32 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i32 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -318,32 +391,65 @@ exit: define i64 @print_mulacc(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) { ; CHECK-LABEL: 'print_mulacc' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1> -; CHECK-NEXT: CLONE ir<[[ARRAYIDX0:%.+]]> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR0:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX0]]> -; CHECK-NEXT: WIDEN ir<[[LOAD0:%.+]]> = load vp<[[ADDR0]]> -; CHECK-NEXT: CLONE ir<[[ARRAYIDX1:%.+]]> = getelementptr inbounds ir<%y>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR1:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX1]]> -; CHECK-NEXT: WIDEN ir<[[LOAD1:%.+]]> = load vp<[[ADDR1]]> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul nsw ir<[[LOAD0]]>, ir<[[LOAD1]]>) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]> +; CHECK-NEXT: CLONE ir<%arrayidx1> = getelementptr inbounds ir<%y>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1> +; CHECK-NEXT: WIDEN ir<%load1> = load vp<[[VP7]]> +; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%rdx> + reduce.add (mul nsw ir<%load0>, ir<%load1>) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP8]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %r.0.lcssa = phi i64 [ %rdx.next, %loop ] (extra operand: vp<[[VP10]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP10]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds i64, ptr %x, i32 %iv +; CHECK-NEXT: IR %load0 = load i64, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %arrayidx1 = getelementptr inbounds i64, ptr %y, i32 %iv +; CHECK-NEXT: IR %load1 = load i64, ptr %arrayidx1, align 4 +; CHECK-NEXT: IR %mul = mul nsw i64 %load0, %load1 +; CHECK-NEXT: IR %rdx.next = add nsw i64 %rdx, %mul +; CHECK-NEXT: IR %iv.next = add nuw nsw i32 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i32 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -368,32 +474,68 @@ exit: define i64 @print_mulacc_extended(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) { ; CHECK-LABEL: 'print_mulacc_extended' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1> -; CHECK-NEXT: CLONE ir<[[ARRAYIDX0:%.+]]> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR0:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX0]]> -; CHECK-NEXT: WIDEN ir<[[LOAD0:%.+]]> = load vp<[[ADDR0]]> -; CHECK-NEXT: CLONE ir<[[ARRAYIDX1:%.+]]> = getelementptr inbounds ir<%y>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR1:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX1]]> -; CHECK-NEXT: WIDEN ir<[[LOAD1:%.+]]> = load vp<[[ADDR1]]> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT:%.+]]> = ir<[[RDX]]> + reduce.add (mul nsw (ir<[[LOAD0]]> sext to i64), (ir<[[LOAD1]]> sext to i64)) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]> +; CHECK-NEXT: CLONE ir<%arrayidx1> = getelementptr inbounds ir<%y>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1> +; CHECK-NEXT: WIDEN ir<%load1> = load vp<[[VP7]]> +; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%rdx> + reduce.add (mul nsw (ir<%load0> sext to i64), (ir<%load1> sext to i64)) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP8]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %r.0.lcssa = phi i64 [ %rdx.next, %loop ] (extra operand: vp<[[VP10]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP10]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds i16, ptr %x, i32 %iv +; CHECK-NEXT: IR %load0 = load i16, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %arrayidx1 = getelementptr inbounds i16, ptr %y, i32 %iv +; CHECK-NEXT: IR %load1 = load i16, ptr %arrayidx1, align 4 +; CHECK-NEXT: IR %conv0 = sext i16 %load0 to i32 +; CHECK-NEXT: IR %conv1 = sext i16 %load1 to i32 +; CHECK-NEXT: IR %mul = mul nsw i32 %conv0, %conv1 +; CHECK-NEXT: IR %conv = sext i32 %mul to i64 +; CHECK-NEXT: IR %rdx.next = add nsw i64 %rdx, %conv +; CHECK-NEXT: IR %iv.next = add nuw nsw i32 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i32 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -421,29 +563,60 @@ exit: define i64 @print_extended_sub_reduction(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) { ; CHECK-LABEL: 'print_extended_sub_reduction' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1> -; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR:%.+]]> = vector-pointer inbounds ir<%arrayidx> -; CHECK-NEXT: WIDEN ir<[[LOAD:%.+]]> = load vp<[[ADDR]]> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.sub (ir<[[LOAD]]> zext to i64) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi vp<[[VP3]]>, vp<[[VP7:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]> +; CHECK-NEXT: EXPRESSION vp<[[VP7]]> = ir<%rdx> + reduce.sub (ir<%load0> zext to i64) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = compute-reduction-result (sub, in-loop) vp<[[VP7]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %r.0.lcssa = phi i64 [ %rdx.next, %loop ] (extra operand: vp<[[VP9]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP9]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds i32, ptr %x, i32 %iv +; CHECK-NEXT: IR %load0 = load i32, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %conv0 = zext i32 %load0 to i64 +; CHECK-NEXT: IR %rdx.next = sub nsw i64 %rdx, %conv0 +; CHECK-NEXT: IR %iv.next = add nuw nsw i32 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i32 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -466,101 +639,68 @@ exit: define i32 @print_mulacc_sub(ptr %a, ptr %b) { ; CHECK-LABEL: 'print_mulacc_sub' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<%0> = VF -; CHECK-NEXT: Live-in vp<%1> = VF * UF -; CHECK-NEXT: Live-in vp<%2> = vector-trip-count -; CHECK-NEXT: Live-in ir<1024> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: EMIT vp<%3> = reduction-start-vector ir<0>, ir<0>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION ir<0>, vp<%index.next> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi vp<%3>, vp<%8> -; CHECK-NEXT: vp<%5> = SCALAR-STEPS vp<%4>, ir<1>, vp<%0> -; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<%5> -; CHECK-NEXT: vp<%6> = vector-pointer ir<%gep.a> -; CHECK-NEXT: WIDEN ir<%load.a> = load vp<%6> -; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<%5> -; CHECK-NEXT: vp<%7> = vector-pointer ir<%gep.b> -; CHECK-NEXT: WIDEN ir<%load.b> = load vp<%7> -; CHECK-NEXT: EXPRESSION vp<%8> = ir<%accum> + reduce.sub (mul (ir<%load.b> zext to i32), (ir<%load.a> zext to i32)) -; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%4>, vp<%1> -; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<%2> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<%10> = compute-reduction-result (sub, in-loop) vp<%8> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<%2> -; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<%10> from middle.block) -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph: -; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<%2>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<%10>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) -; CHECK-NEXT: IR %accum = phi i32 [ 0, %entry ], [ %add, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) -; CHECK-NEXT: IR %gep.a = getelementptr i8, ptr %a, i64 %iv -; CHECK-NEXT: IR %load.a = load i8, ptr %gep.a, align 1 -; CHECK-NEXT: IR %ext.a = zext i8 %load.a to i32 -; CHECK-NEXT: IR %gep.b = getelementptr i8, ptr %b, i64 %iv -; CHECK-NEXT: IR %load.b = load i8, ptr %gep.b, align 1 -; CHECK-NEXT: IR %ext.b = zext i8 %load.b to i32 -; CHECK-NEXT: IR %mul = mul i32 %ext.b, %ext.a -; CHECK-NEXT: IR %add = sub i32 %accum, %mul -; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 -; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1024 -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' { -; CHECK-NEXT: Live-in ir<1024> = vector-trip-count -; CHECK-NEXT: Live-in ir<1024> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector.body -; CHECK-EMPTY: -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT-SCALAR vp<%index> = phi [ ir<0>, vector.ph ], [ vp<%index.next>, vector.body ] -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi ir<0>, ir<%add> -; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<%index> -; CHECK-NEXT: WIDEN ir<%load.a> = load ir<%gep.a> -; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<%index> -; CHECK-NEXT: WIDEN ir<%load.b> = load ir<%gep.b> -; CHECK-NEXT: WIDEN-CAST ir<%ext.b> = zext ir<%load.b> to i32 -; CHECK-NEXT: WIDEN-CAST ir<%ext.a> = zext ir<%load.a> to i32 -; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%ext.b>, ir<%ext.a> -; CHECK-NEXT: REDUCE ir<%add> = ir<%accum> + reduce.sub (ir<%mul>) -; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%index>, ir<4> -; CHECK-NEXT: EMIT vp<{{%.+}}> = icmp eq vp<%index.next>, ir<1024> -; CHECK-NEXT: EMIT branch-on-cond vp<{{%.+}}> -; CHECK-NEXT: Successor(s): middle.block, vector.body -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RED_RESULT:%.+]]> = compute-reduction-result (sub, in-loop) ir<%add> -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[RED_RESULT]]> from middle.block) -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<1024> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%gep.a> +; CHECK-NEXT: WIDEN ir<%load.a> = load vp<[[VP6]]> +; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer ir<%gep.b> +; CHECK-NEXT: WIDEN ir<%load.b> = load vp<[[VP7]]> +; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%accum> + reduce.sub (mul (ir<%load.b> zext to i32), (ir<%load.a> zext to i32)) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = compute-reduction-result (sub, in-loop) vp<[[VP8]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[VP10]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP10]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %accum = phi i32 [ 0, %entry ], [ %add, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %gep.a = getelementptr i8, ptr %a, i64 %iv +; CHECK-NEXT: IR %load.a = load i8, ptr %gep.a, align 1 +; CHECK-NEXT: IR %ext.a = zext i8 %load.a to i32 +; CHECK-NEXT: IR %gep.b = getelementptr i8, ptr %b, i64 %iv +; CHECK-NEXT: IR %load.b = load i8, ptr %gep.b, align 1 +; CHECK-NEXT: IR %ext.b = zext i8 %load.b to i32 +; CHECK-NEXT: IR %mul = mul i32 %ext.b, %ext.a +; CHECK-NEXT: IR %add = sub i32 %accum, %mul +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1024 +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %loop @@ -585,103 +725,69 @@ exit: define i32 @print_mulacc_negated(ptr %a, ptr %b) { ; CHECK-LABEL: 'print_mulacc_negated' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<%0> = VF -; CHECK-NEXT: Live-in vp<%1> = VF * UF -; CHECK-NEXT: Live-in vp<%2> = vector-trip-count -; CHECK-NEXT: Live-in ir<1024> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: EMIT vp<%3> = reduction-start-vector ir<0>, ir<0>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION ir<0>, vp<%index.next> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi vp<%3>, vp<%8> -; CHECK-NEXT: vp<%5> = SCALAR-STEPS vp<%4>, ir<1>, vp<%0> -; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<%5> -; CHECK-NEXT: vp<%6> = vector-pointer ir<%gep.a> -; CHECK-NEXT: WIDEN ir<%load.a> = load vp<%6> -; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<%5> -; CHECK-NEXT: vp<%7> = vector-pointer ir<%gep.b> -; CHECK-NEXT: WIDEN ir<%load.b> = load vp<%7> -; CHECK-NEXT: EXPRESSION vp<%8> = ir<%accum> + reduce.add (sub (0, mul (ir<%load.b> zext to i32), (ir<%load.a> zext to i32))) -; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%4>, vp<%1> -; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<%2> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<%10> = compute-reduction-result (add, in-loop) vp<%8> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<%2> -; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<%10> from middle.block) -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph: -; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<%2>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<%10>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) -; CHECK-NEXT: IR %accum = phi i32 [ 0, %entry ], [ %add, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) -; CHECK-NEXT: IR %gep.a = getelementptr i8, ptr %a, i64 %iv -; CHECK-NEXT: IR %load.a = load i8, ptr %gep.a, align 1 -; CHECK-NEXT: IR %ext.a = zext i8 %load.a to i32 -; CHECK-NEXT: IR %gep.b = getelementptr i8, ptr %b, i64 %iv -; CHECK-NEXT: IR %load.b = load i8, ptr %gep.b, align 1 -; CHECK-NEXT: IR %ext.b = zext i8 %load.b to i32 -; CHECK-NEXT: IR %mul = mul i32 %ext.b, %ext.a -; CHECK-NEXT: IR %sub = sub i32 0, %mul -; CHECK-NEXT: IR %add = add i32 %accum, %sub -; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 -; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1024 -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' { -; CHECK-NEXT: Live-in ir<1024> = vector-trip-count -; CHECK-NEXT: Live-in ir<1024> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector.body -; CHECK-EMPTY: -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT-SCALAR vp<%index> = phi [ ir<0>, vector.ph ], [ vp<%index.next>, vector.body ] -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi ir<0>, ir<%add> -; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<%index> -; CHECK-NEXT: WIDEN ir<%load.a> = load ir<%gep.a> -; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<%index> -; CHECK-NEXT: WIDEN ir<%load.b> = load ir<%gep.b> -; CHECK-NEXT: WIDEN-CAST ir<%ext.b> = zext ir<%load.b> to i32 -; CHECK-NEXT: WIDEN-CAST ir<%ext.a> = zext ir<%load.a> to i32 -; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%ext.b>, ir<%ext.a> -; CHECK-NEXT: WIDEN ir<%sub> = sub ir<0>, ir<%mul> -; CHECK-NEXT: REDUCE ir<%add> = ir<%accum> + reduce.add (ir<%sub>) -; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%index>, ir<4> -; CHECK-NEXT: EMIT vp<{{%.+}}> = icmp eq vp<%index.next>, ir<1024> -; CHECK-NEXT: EMIT branch-on-cond vp<{{%.+}}> -; CHECK-NEXT: Successor(s): middle.block, vector.body -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RED_RESULT:%.+]]> = compute-reduction-result (add, in-loop) ir<%add> -; CHECK-NEXT: Successor(s): ir-bb -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[RED_RESULT]]> from middle.block) -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<1024> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%accum> = phi vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.a> = getelementptr ir<%a>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%gep.a> +; CHECK-NEXT: WIDEN ir<%load.a> = load vp<[[VP6]]> +; CHECK-NEXT: CLONE ir<%gep.b> = getelementptr ir<%b>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer ir<%gep.b> +; CHECK-NEXT: WIDEN ir<%load.b> = load vp<[[VP7]]> +; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%accum> + reduce.add (sub (0, mul (ir<%load.b> zext to i32), (ir<%load.a> zext to i32))) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP8]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %add.lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[VP10]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP10]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %accum = phi i32 [ 0, %entry ], [ %add, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %gep.a = getelementptr i8, ptr %a, i64 %iv +; CHECK-NEXT: IR %load.a = load i8, ptr %gep.a, align 1 +; CHECK-NEXT: IR %ext.a = zext i8 %load.a to i32 +; CHECK-NEXT: IR %gep.b = getelementptr i8, ptr %b, i64 %iv +; CHECK-NEXT: IR %load.b = load i8, ptr %gep.b, align 1 +; CHECK-NEXT: IR %ext.b = zext i8 %load.b to i32 +; CHECK-NEXT: IR %mul = mul i32 %ext.b, %ext.a +; CHECK-NEXT: IR %sub = sub i32 0, %mul +; CHECK-NEXT: IR %add = add i32 %accum, %sub +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1024 +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %loop @@ -707,32 +813,68 @@ exit: define i64 @print_mulacc_sub_extended(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) { ; CHECK-LABEL: 'print_mulacc_sub_extended' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1> -; CHECK-NEXT: CLONE ir<[[ARRAYIDX0:%.+]]> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR0:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX0]]> -; CHECK-NEXT: WIDEN ir<[[LOAD0:%.+]]> = load vp<[[ADDR0]]> -; CHECK-NEXT: CLONE ir<[[ARRAYIDX1:%.+]]> = getelementptr inbounds ir<%y>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR1:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX1]]> -; CHECK-NEXT: WIDEN ir<[[LOAD1:%.+]]> = load vp<[[ADDR1]]> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT:%.+]]> = ir<[[RDX]]> + reduce.sub (mul nsw (ir<[[LOAD0]]> sext to i64), (ir<[[LOAD1]]> sext to i64)) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi vp<[[VP3]]>, vp<[[VP8:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]> +; CHECK-NEXT: CLONE ir<%arrayidx1> = getelementptr inbounds ir<%y>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx1> +; CHECK-NEXT: WIDEN ir<%load1> = load vp<[[VP7]]> +; CHECK-NEXT: EXPRESSION vp<[[VP8]]> = ir<%rdx> + reduce.sub (mul nsw (ir<%load0> sext to i64), (ir<%load1> sext to i64)) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = compute-reduction-result (sub, in-loop) vp<[[VP8]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %r.0.lcssa = phi i64 [ %rdx.next, %loop ] (extra operand: vp<[[VP10]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP10]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds i16, ptr %x, i32 %iv +; CHECK-NEXT: IR %load0 = load i16, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %arrayidx1 = getelementptr inbounds i16, ptr %y, i32 %iv +; CHECK-NEXT: IR %load1 = load i16, ptr %arrayidx1, align 4 +; CHECK-NEXT: IR %conv0 = sext i16 %load0 to i32 +; CHECK-NEXT: IR %conv1 = sext i16 %load1 to i32 +; CHECK-NEXT: IR %mul = mul nsw i32 %conv0, %conv1 +; CHECK-NEXT: IR %conv = sext i32 %mul to i64 +; CHECK-NEXT: IR %rdx.next = sub nsw i64 %rdx, %conv +; CHECK-NEXT: IR %iv.next = add nuw nsw i32 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i32 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -760,29 +902,62 @@ exit: define i64 @print_mulacc_duplicate_extends(ptr nocapture readonly %x, ptr nocapture readonly %y, i32 %n) { ; CHECK-LABEL: 'print_mulacc_duplicate_extends' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK: vector.ph: -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1> -; CHECK-NEXT: CLONE ir<[[ARRAYIDX0:%.+]]> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[ADDR0:%.+]]> = vector-pointer inbounds ir<[[ARRAYIDX0]]> -; CHECK-NEXT: WIDEN ir<[[LOAD0:%.+]]> = load vp<[[ADDR0]]> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT:%.+]]> = ir<[[RDX]]> + reduce.sub (mul nsw (ir<[[LOAD0]]> sext to i64), (ir<[[LOAD0]]> sext to i64)) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%rdx> = phi vp<[[VP3]]>, vp<[[VP7:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%x>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%load0> = load vp<[[VP6]]> +; CHECK-NEXT: EXPRESSION vp<[[VP7]]> = ir<%rdx> + reduce.sub (mul nsw (ir<%load0> sext to i64), (ir<%load0> sext to i64)) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = compute-reduction-result (sub, in-loop) vp<[[VP7]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %r.0.lcssa = phi i64 [ %rdx.next, %loop ] (extra operand: vp<[[VP9]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP9]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i32 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %rdx = phi i64 [ %rdx.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds i16, ptr %x, i32 %iv +; CHECK-NEXT: IR %load0 = load i16, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %conv0 = sext i16 %load0 to i32 +; CHECK-NEXT: IR %mul = mul nsw i32 %conv0, %conv0 +; CHECK-NEXT: IR %conv = sext i32 %mul to i64 +; CHECK-NEXT: IR %rdx.next = sub nsw i64 %rdx, %conv +; CHECK-NEXT: IR %iv.next = add nuw nsw i32 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i32 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -807,40 +982,63 @@ exit: define i32 @print_mulacc_extended_const(ptr %start, ptr %end) { ; CHECK-LABEL: 'print_mulacc_extended_const' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: vp<%3> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) +; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) ; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: ; CHECK-NEXT: vector.ph: -; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1> -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%start> + vp<[[VP2]]> * ir<1> +; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> ; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { ; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep> -; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul (ir<%l> zext to i32), (ir<63> zext to i32)) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[VP5]]>, vp<[[VP9:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep> +; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]> +; CHECK-NEXT: EXPRESSION vp<[[VP9]]> = ir<%red> + reduce.add (mul (ir<%l> zext to i32), (ir<63> zext to i32)) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: ; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result (add, in-loop) vp<[[RDX_NEXT]]> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]> +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP9]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]> ; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %red.next.lcssa = phi i32 [ %red.next, %loop ] (extra operand: vp<[[VP11]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%start>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP11]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %red = phi i32 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %l = load i8, ptr %ptr.iv, align 1 +; CHECK-NEXT: IR %l.ext = zext i8 %l to i32 +; CHECK-NEXT: IR %mul = mul i32 %l.ext, 63 +; CHECK-NEXT: IR %red.next = add i32 %red, %mul +; CHECK-NEXT: IR %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1 +; CHECK-NEXT: IR %ec = icmp eq ptr %ptr.iv, %end +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %loop @@ -861,41 +1059,64 @@ exit: define i32 @print_mulacc_extended_const_lhs(ptr %start, ptr %end) { ; CHECK-LABEL: 'print_mulacc_extended_const_lhs' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: vp<%3> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) +; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) ; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: ; CHECK-NEXT: vector.ph: -; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1> -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%start> + vp<[[VP2]]> * ir<1> +; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> ; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { ; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep> -; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[VP5]]>, vp<[[VP9:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep> +; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]> ; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = zext ir<%l> to i32 -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul ir<63>, ir<%l.ext>) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> +; CHECK-NEXT: EXPRESSION vp<[[VP9]]> = ir<%red> + reduce.add (mul ir<63>, ir<%l.ext>) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: ; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result (add, in-loop) vp<[[RDX_NEXT]]> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]> +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP9]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]> ; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %red.next.lcssa = phi i32 [ %red.next, %loop ] (extra operand: vp<[[VP11]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%start>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP11]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %red = phi i32 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %l = load i8, ptr %ptr.iv, align 1 +; CHECK-NEXT: IR %l.ext = zext i8 %l to i32 +; CHECK-NEXT: IR %mul = mul i32 63, %l.ext +; CHECK-NEXT: IR %red.next = add i32 %red, %mul +; CHECK-NEXT: IR %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1 +; CHECK-NEXT: IR %ec = icmp eq ptr %ptr.iv, %end +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %loop @@ -917,41 +1138,64 @@ exit: ; Constants >= 128 cannot be treated as sign-extended, so the expression shouldn't extend 128 define i32 @print_mulacc_not_extended_const(ptr %start, ptr %end) { ; CHECK-LABEL: 'print_mulacc_not_extended_const' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: vp<%3> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) +; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) ; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: ; CHECK-NEXT: vector.ph: -; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1> -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%start> + vp<[[VP2]]> * ir<1> +; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> ; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { ; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep> -; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[VP5]]>, vp<[[VP9:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep> +; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]> ; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = sext ir<%l> to i32 -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul ir<%l.ext>, ir<128>) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> +; CHECK-NEXT: EXPRESSION vp<[[VP9]]> = ir<%red> + reduce.add (mul ir<%l.ext>, ir<128>) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: ; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result (add, in-loop) vp<[[RDX_NEXT]]> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]> +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP9]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]> ; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %red.next.lcssa = phi i32 [ %red.next, %loop ] (extra operand: vp<[[VP11]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%start>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP11]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %red = phi i32 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %l = load i8, ptr %ptr.iv, align 1 +; CHECK-NEXT: IR %l.ext = sext i8 %l to i32 +; CHECK-NEXT: IR %mul = mul i32 %l.ext, 128 +; CHECK-NEXT: IR %red.next = add i32 %red, %mul +; CHECK-NEXT: IR %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1 +; CHECK-NEXT: IR %ec = icmp eq ptr %ptr.iv, %end +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %loop @@ -973,40 +1217,64 @@ exit: define i64 @print_ext_mulacc_extended_const(ptr %start, ptr %end) { ; CHECK-LABEL: 'print_ext_mulacc_extended_const' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: vp<%3> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) +; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) ; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: ; CHECK-NEXT: vector.ph: -; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1> -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%start> + vp<[[VP2]]> * ir<1> +; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> ; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { ; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep> -; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (mul (ir<%l> zext to i64), (ir<63> zext to i64)) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[VP5]]>, vp<[[VP9:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep> +; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]> +; CHECK-NEXT: EXPRESSION vp<[[VP9]]> = ir<%red> + reduce.add (mul (ir<%l> zext to i64), (ir<63> zext to i64)) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: ; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<%11> = compute-reduction-result (add, in-loop) vp<[[RDX_NEXT]]> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]> +; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP9]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]> ; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %red.next.lcssa = phi i64 [ %red.next, %loop ] (extra operand: vp<[[VP11]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%start>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP11]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %red = phi i64 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %l = load i8, ptr %ptr.iv, align 1 +; CHECK-NEXT: IR %l.ext = zext i8 %l to i32 +; CHECK-NEXT: IR %mul = mul i32 %l.ext, 63 +; CHECK-NEXT: IR %mul.ext = zext i32 %mul to i64 +; CHECK-NEXT: IR %red.next = add i64 %red, %mul.ext +; CHECK-NEXT: IR %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1 +; CHECK-NEXT: IR %ec = icmp eq ptr %ptr.iv, %end +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %loop @@ -1029,42 +1297,66 @@ exit: ; Constants >= 128 cannot be treated as sign-extended, so the expression shouldn't extend 128 define i64 @print_ext_mulacc_not_extended_const(ptr %start, ptr %end) { ; CHECK-LABEL: 'print_ext_mulacc_not_extended_const' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: vp<%3> = original trip-count +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: EMIT vp<%3> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) +; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1 + (-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64)) ; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: ; CHECK-NEXT: vector.ph: -; CHECK-NEXT: vp<[[DER_IV:%.+]]> = DERIVED-IV ir<%start> + vp<[[VTC]]> * ir<1> -; CHECK-NEXT: EMIT vp<[[RDX_START:%.+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%start> + vp<[[VP2]]> * ir<1> +; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> ; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { ; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<[[RDX:%.+]]> = phi vp<[[RDX_START]]>, vp<[[RDX_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer vp<%next.gep> -; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi vp<[[VP5]]>, vp<[[VP10:%[0-9]+]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<[[VP7]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer vp<%next.gep> +; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP8]]> ; CHECK-NEXT: WIDEN-CAST ir<%l.ext> = sext ir<%l> to i32 -; CHECK-NEXT: EMIT vp<[[SHL:%.+]]> = shl ir<%l.ext>, ir<7> -; CHECK-NEXT: EXPRESSION vp<[[RDX_NEXT]]> = ir<[[RDX]]> + reduce.add (vp<[[SHL]]> sext to i64) -; CHECK-NEXT: EMIT vp<[[IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT]]>, vp<[[VTC]]> +; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = shl ir<%l.ext>, ir<7> +; CHECK-NEXT: EXPRESSION vp<[[VP10]]> = ir<%red> + reduce.add (vp<[[VP9]]> sext to i64) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: ; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RES:%.+]]> = compute-reduction-result (add, in-loop) vp<[[RDX_NEXT]]> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%3>, vp<[[VTC]]> +; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP10]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]> ; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %red.next.lcssa = phi i64 [ %red.next, %loop ] (extra operand: vp<[[VP12]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP4]]>, middle.block ], [ ir<%start>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP12]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %ptr.iv = phi ptr [ %start, %entry ], [ %gep.iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %red = phi i64 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %l = load i8, ptr %ptr.iv, align 1 +; CHECK-NEXT: IR %l.ext = sext i8 %l to i32 +; CHECK-NEXT: IR %mul = mul i32 %l.ext, 128 +; CHECK-NEXT: IR %mul.ext = sext i32 %mul to i64 +; CHECK-NEXT: IR %red.next = add i64 %red, %mul.ext +; CHECK-NEXT: IR %gep.iv.next = getelementptr i8, ptr %ptr.iv, i64 1 +; CHECK-NEXT: IR %ec = icmp eq ptr %ptr.iv, %end +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %loop @@ -1090,51 +1382,52 @@ exit: ; It can however be turned into an ExtendedReduction since that one doesn't ; modify the mul's operands. define i64 @print_ext_mul_two_uses(i64 %n, ptr %a, i16 %b, i32 %c) { -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<%0> = VF * UF -; CHECK-NEXT: Live-in vp<%1> = vector-trip-count -; CHECK-NEXT: vp<%2> = original trip-count +; CHECK-LABEL: 'print_ext_mul_two_uses' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP2:%[0-9]+]]> = original trip-count ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: EMIT vp<%2> = EXPAND SCEV (1 + %n) +; CHECK-NEXT: EMIT vp<[[VP2]]> = EXPAND SCEV (1 + %n) ; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: ; CHECK-NEXT: vector.ph: -; CHECK-NEXT: EMIT vp<%3> = reduction-start-vector ir<0>, ir<0>, ir<1> +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = reduction-start-vector ir<0>, ir<0>, ir<1> ; CHECK-NEXT: WIDEN-CAST ir<%conv> = sext ir<%b> to i32 ; CHECK-NEXT: WIDEN ir<%mul> = mul ir<%conv>, ir<%conv> ; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { ; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION ir<0>, vp<%index.next> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%res2> = phi vp<%3>, vp<%5> +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%res2> = phi vp<[[VP3]]>, vp<[[VP5:%[0-9]+]]> ; CHECK-NEXT: CLONE ir<%load> = load ir<%a> -; CHECK-NEXT: WIDEN-CAST ir<%load.ext> = sext ir<%load> to i32 -; CHECK-NEXT: WIDEN-CAST ir<%load.ext.ext> = sext ir<%load.ext> to i64 -; CHECK-NEXT: EXPRESSION vp<%5> = ir<%res2> + reduce.add (ir<%mul> zext to i64) -; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%4>, vp<%0> -; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<%1> +; CHECK-NEXT: EXPRESSION vp<[[VP5]]> = ir<%res2> + reduce.add (ir<%mul> zext to i64) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP0]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP1]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: ; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<%7> = compute-reduction-result (add, in-loop) vp<%5> -; CHECK-NEXT: EMIT vp<[[EXT_PART:%.+]]> = extract-last-part ir<%load.ext.ext> -; CHECK-NEXT: EMIT vp<%vector.recur.extract> = extract-last-lane vp<[[EXT_PART]]> -; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<%2>, vp<%1> +; CHECK-NEXT: WIDEN-CAST ir<%load.ext> = sext ir<%load> to i32 +; CHECK-NEXT: WIDEN-CAST ir<%load.ext.ext> = sext ir<%load.ext> to i64 +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (add, in-loop) vp<[[VP5]]> +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = extract-last-part ir<%load.ext.ext> +; CHECK-NEXT: EMIT vp<%vector.recur.extract> = extract-last-lane vp<[[VP8]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP2]]>, vp<[[VP1]]> ; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> ; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %add.lcssa = phi i64 [ %add, %loop ] (extra operand: vp<%7> from middle.block) +; CHECK-NEXT: IR %add.lcssa = phi i64 [ %add, %loop ] (extra operand: vp<[[VP7]]> from middle.block) ; CHECK-NEXT: No successors ; CHECK-EMPTY: ; CHECK-NEXT: scalar.ph: -; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<%1>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP1]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<%vector.recur.extract>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<%7>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP7]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: @@ -1153,6 +1446,7 @@ define i64 @print_ext_mul_two_uses(i64 %n, ptr %a, i16 %b, i32 %c) { ; CHECK-NEXT: IR %exitcond740.not = icmp eq i64 %iv, %n ; CHECK-NEXT: No successors ; CHECK-NEXT: } +; entry: br label %loop @@ -1177,39 +1471,59 @@ exit: } define i32 @print_umax_reduction(ptr %y) { -; CHECK-LABEL: Checking a loop in 'print_umax_reduction' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<100> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi ir<0>, ir<%red.next> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep> -; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.umax(ir<%lv>, ir<%red>) -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RED_RES:%.+]]> = compute-reduction-result (umax) ir<%red.next> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<100>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-LABEL: 'print_umax_reduction' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<100> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: WIDEN-REDUCTION-PHI ir<%red> = phi ir<0>, ir<%red.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%y>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN-INTRINSIC ir<%red.next> = call llvm.umax(ir<%lv>, ir<%red>) +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = compute-reduction-result (umax) ir<%red.next> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<100>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %red.next.lcssa = phi i32 [ %red.next, %loop ] (extra operand: vp<[[VP7]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.merge.rdx> = phi [ vp<[[VP7]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %red = phi i32 [ 0, %entry ], [ %red.next, %loop ] (extra operand: vp<%bc.merge.rdx> from scalar.ph) +; CHECK-NEXT: IR %gep = getelementptr inbounds i32, ptr %y, i64 %iv +; CHECK-NEXT: IR %lv = load i32, ptr %gep, align 4 +; CHECK-NEXT: IR %red.next = call i32 @llvm.umax.i32(i32 %lv, i32 %red) +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %ec = icmp eq i64 %iv.next, 100 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll index be7e0686fd595..1d5d71b0a64c0 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 ; REQUIRES: asserts ; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -enable-interleaved-mem-accesses=true -enable-masked-interleaved-mem-accesses -force-widen-divrem-via-safe-divisor=0 -disable-output %s 2>&1 | FileCheck --strict-whitespace %s @@ -7,53 +8,59 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ; Tests for printing VPlans. define void @print_call_and_memory(i64 %n, ptr noalias %y, ptr noalias %x) nounwind uwtable { -; CHECK-LABEL: Checking a loop in 'print_call_and_memory' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%arrayidx> -; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN-INTRINSIC ir<%call> = call llvm.sqrt(ir<%lv>) -; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%arrayidx2> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%call> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> +; CHECK-LABEL: 'print_call_and_memory' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%y>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN-INTRINSIC ir<%call> = call llvm.sqrt(ir<%lv>) +; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%x>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx2> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%call> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> ; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb +; CHECK-NEXT: ir-bb: ; CHECK-NEXT: No successors ; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %for.body ], [ 0, %for.body.preheader ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n +; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %for.body ], [ 0, %for.body.preheader ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds float, ptr %y, i64 %iv +; CHECK-NEXT: IR %lv = load float, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %call = tail call float @llvm.sqrt.f32(float %lv) #3 +; CHECK-NEXT: IR %arrayidx2 = getelementptr inbounds float, ptr %x, i64 %iv +; CHECK-NEXT: IR store float %call, ptr %arrayidx2, align 4 +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i64 %iv.next, %n ; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: } ; entry: %cmp6 = icmp sgt i64 %n, 0 @@ -75,56 +82,64 @@ for.end: ; preds = %for.body, %entry } define void @print_widen_gep_and_select(i64 %n, ptr noalias %y, ptr noalias %x, ptr %z) nounwind uwtable { -; CHECK-LABEL: Checking a loop in 'print_widen_gep_and_select' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr inbounds ir<%y>, ir<%iv> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%arrayidx> -; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN ir<%cmp> = icmp eq ir<%arrayidx>, ir<%z> -; CHECK-NEXT: WIDEN ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01> -; CHECK-NEXT: WIDEN ir<%add> = fadd ir<%lv>, ir<%sel> -; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%arrayidx2> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%add> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> +; CHECK-LABEL: 'print_widen_gep_and_select' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: WIDEN-GEP Inv[Var] ir<%arrayidx> = getelementptr inbounds ir<%y>, ir<%iv> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN ir<%cmp> = icmp eq ir<%arrayidx>, ir<%z> +; CHECK-NEXT: WIDEN ir<%sel> = select ir<%cmp>, ir<1.000000e+01>, ir<2.000000e+01> +; CHECK-NEXT: WIDEN ir<%add> = fadd ir<%lv>, ir<%sel> +; CHECK-NEXT: CLONE ir<%arrayidx2> = getelementptr inbounds ir<%x>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%arrayidx2> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%add> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> ; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb +; CHECK-NEXT: ir-bb: ; CHECK-NEXT: No successors ; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %for.body ], [ 0, %for.body.preheader ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n +; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %for.body ], [ 0, %for.body.preheader ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %arrayidx = getelementptr inbounds float, ptr %y, i64 %iv +; CHECK-NEXT: IR %lv = load float, ptr %arrayidx, align 4 +; CHECK-NEXT: IR %cmp = icmp eq ptr %arrayidx, %z +; CHECK-NEXT: IR %sel = select i1 %cmp, float 1.000000e+01, float 2.000000e+01 +; CHECK-NEXT: IR %add = fadd float %lv, %sel +; CHECK-NEXT: IR %arrayidx2 = getelementptr inbounds float, ptr %x, i64 %iv +; CHECK-NEXT: IR store float %add, ptr %arrayidx2, align 4 +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i64 %iv.next, %n ; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: } ; entry: %cmp6 = icmp sgt i64 %n, 0 @@ -148,72 +163,72 @@ for.end: ; preds = %for.body, %entry } define void @print_replicate_predicated_phi(i64 %n, ptr %x) { -; CHECK-LABEL: Checking a loop in 'print_replicate_predicated_phi' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (1 smax %n) -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: ir<%i> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: WIDEN ir<%cmp> = icmp ult ir<%i>, ir<5> -; CHECK-NEXT: Successor(s): pred.udiv -; CHECK-EMPTY: -; CHECK-NEXT: pred.udiv: { -; CHECK-NEXT: pred.udiv.entry: -; CHECK-NEXT: BRANCH-ON-MASK ir<%cmp> -; CHECK-NEXT: Successor(s): pred.udiv.if, pred.udiv.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.udiv.if: -; CHECK-NEXT: vp<[[STEPS2:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: REPLICATE ir<%tmp4> = udiv ir<%n>, vp<[[STEPS2]]> (S->V) -; CHECK-NEXT: Successor(s): pred.udiv.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.udiv.continue: -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PRED:%.+]]> = ir<%tmp4> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): if.then.0 -; CHECK-EMPTY: -; CHECK-NEXT: if.then.0: -; CHECK-NEXT: BLEND ir<%d> = ir<0> vp<[[PRED]]>/ir<%cmp> -; CHECK-NEXT: CLONE ir<%idx> = getelementptr ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%idx> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%d> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-LABEL: 'print_replicate_predicated_phi' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1 smax %n) +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: ir<%i> = WIDEN-INDUCTION nuw nsw ir<0>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: WIDEN ir<%cmp> = icmp ult ir<%i>, ir<5> +; CHECK-NEXT: Successor(s): pred.udiv +; CHECK-EMPTY: +; CHECK-NEXT: pred.udiv: { +; CHECK-NEXT: pred.udiv.entry: +; CHECK-NEXT: BRANCH-ON-MASK ir<%cmp> +; CHECK-NEXT: Successor(s): pred.udiv.if, pred.udiv.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.udiv.if: +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: REPLICATE ir<%tmp4> = udiv ir<%n>, vp<[[VP6]]> (S->V) +; CHECK-NEXT: Successor(s): pred.udiv.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.udiv.continue: +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP7:%[0-9]+]]> = ir<%tmp4> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): if.then.0 +; CHECK-EMPTY: +; CHECK-NEXT: if.then.0: +; CHECK-NEXT: BLEND ir<%d> = ir<0> vp<%7>/ir<%cmp> +; CHECK-NEXT: CLONE ir<%idx> = getelementptr ir<%x>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer ir<%idx> +; CHECK-NEXT: WIDEN store vp<[[VP8]]>, ir<%d> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) +; CHECK-NEXT: IR %i = phi i64 [ 0, %entry ], [ %i.next, %for.inc ] (extra operand: vp<%bc.resume.val> from scalar.ph) ; CHECK-NEXT: IR %cmp = icmp ult i64 %i, 5 -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %for.body @@ -243,60 +258,79 @@ for.end: ; preds = %for.inc @CD = common global [1024 x i32] zeroinitializer, align 4 define void @print_interleave_groups(i32 %C, i32 %D) { -; CHECK-LABEL: Checking a loop in 'print_interleave_groups' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<256> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: vp<[[IV_END:%.+]]> = DERIVED-IV ir<0> + vp<[[VTC]]> * ir<4> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: vp<[[DERIVED_IV:%.+]]> = DERIVED-IV ir<0> + vp<[[CAN_IV]]> * ir<4> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DERIVED_IV]]>, ir<4>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep.AB.0> = getelementptr inbounds ir<@AB>, ir<0>, vp<[[STEPS]]> -; CHECK-NEXT: INTERLEAVE-GROUP with factor 4 at %AB.0, ir<%gep.AB.0> -; CHECK-NEXT: ir<%AB.0> = load from index 0 -; CHECK-NEXT: ir<%AB.1> = load from index 1 -; CHECK-NEXT: ir<%AB.3> = load from index 3 -; CHECK-NEXT: WIDEN ir<%add> = add nsw ir<%AB.0>, ir<%AB.1> -; CHECK-NEXT: CLONE ir<%gep.CD.0> = getelementptr inbounds ir<@CD>, ir<0>, vp<[[STEPS]]> -; CHECK-NEXT: INTERLEAVE-GROUP with factor 4 at , ir<%gep.CD.0> -; CHECK-NEXT: store ir<%add> to index 0 -; CHECK-NEXT: store ir<1> to index 1 -; CHECK-NEXT: store ir<2> to index 2 -; CHECK-NEXT: store ir<%AB.3> to index 3 -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<256>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[IV_END]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-LABEL: 'print_interleave_groups' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<256> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP2]]> * ir<4> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP4]]> * ir<4> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = SCALAR-STEPS vp<[[VP5]]>, ir<4>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.AB.0> = getelementptr inbounds ir<@AB>, ir<0>, vp<[[VP6]]> +; CHECK-NEXT: INTERLEAVE-GROUP with factor 4 at %AB.0, ir<%gep.AB.0> +; CHECK-NEXT: ir<%AB.0> = load from index 0 +; CHECK-NEXT: ir<%AB.1> = load from index 1 +; CHECK-NEXT: ir<%AB.3> = load from index 3 +; CHECK-NEXT: WIDEN ir<%add> = add nsw ir<%AB.0>, ir<%AB.1> +; CHECK-NEXT: CLONE ir<%gep.CD.0> = getelementptr inbounds ir<@CD>, ir<0>, vp<[[VP6]]> +; CHECK-NEXT: INTERLEAVE-GROUP with factor 4 at , ir<%gep.CD.0> +; CHECK-NEXT: store ir<%add> to index 0 +; CHECK-NEXT: store ir<1> to index 1 +; CHECK-NEXT: store ir<2> to index 2 +; CHECK-NEXT: store ir<%AB.3> to index 3 +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<256>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP3]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %cmp = icmp slt i64 %iv.next, 1024 -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep.AB.0 = getelementptr inbounds [1024 x i32], ptr @AB, i64 0, i64 %iv +; CHECK-NEXT: IR %AB.0 = load i32, ptr %gep.AB.0, align 4 +; CHECK-NEXT: IR %iv.plus.1 = add i64 %iv, 1 +; CHECK-NEXT: IR %gep.AB.1 = getelementptr inbounds [1024 x i32], ptr @AB, i64 0, i64 %iv.plus.1 +; CHECK-NEXT: IR %AB.1 = load i32, ptr %gep.AB.1, align 4 +; CHECK-NEXT: IR %iv.plus.2 = add i64 %iv, 2 +; CHECK-NEXT: IR %iv.plus.3 = add i64 %iv, 3 +; CHECK-NEXT: IR %gep.AB.3 = getelementptr inbounds [1024 x i32], ptr @AB, i64 0, i64 %iv.plus.3 +; CHECK-NEXT: IR %AB.3 = load i32, ptr %gep.AB.3, align 4 +; CHECK-NEXT: IR %add = add nsw i32 %AB.0, %AB.1 +; CHECK-NEXT: IR %gep.CD.0 = getelementptr inbounds [1024 x i32], ptr @CD, i64 0, i64 %iv +; CHECK-NEXT: IR store i32 %add, ptr %gep.CD.0, align 4 +; CHECK-NEXT: IR %gep.CD.1 = getelementptr inbounds [1024 x i32], ptr @CD, i64 0, i64 %iv.plus.1 +; CHECK-NEXT: IR store i32 1, ptr %gep.CD.1, align 4 +; CHECK-NEXT: IR %gep.CD.2 = getelementptr inbounds [1024 x i32], ptr @CD, i64 0, i64 %iv.plus.2 +; CHECK-NEXT: IR store i32 2, ptr %gep.CD.2, align 4 +; CHECK-NEXT: IR %gep.CD.3 = getelementptr inbounds [1024 x i32], ptr @CD, i64 0, i64 %iv.plus.3 +; CHECK-NEXT: IR store i32 %AB.3, ptr %gep.CD.3, align 4 +; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 4 +; CHECK-NEXT: IR %cmp = icmp slt i64 %iv.next, 1024 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %for.body @@ -330,76 +364,79 @@ for.end: } define void @recipe_debug_loc_location(ptr nocapture %src) !dbg !5 { -; CHECK-LABEL: Checking a loop in 'recipe_debug_loc_location' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<128> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%isd> = getelementptr inbounds ir<%src>, vp<[[STEPS]]>, !dbg /tmp/s.c:5:3 -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%isd>, !dbg /tmp/s.c:6:3 -; CHECK-NEXT: WIDEN ir<%lsd> = load vp<[[VEC_PTR]]>, !dbg /tmp/s.c:6:3 -; CHECK-NEXT: WIDEN ir<%psd> = add nuw nsw ir<%lsd>, ir<23>, !dbg /tmp/s.c:7:3 -; CHECK-NEXT: WIDEN ir<%cmp1> = icmp slt ir<%lsd>, ir<100>, !dbg /tmp/s.c:8:3 -; CHECK-NEXT: EMIT vp<[[NOT1:%.+]]> = not ir<%cmp1>, !dbg /tmp/s.c:9:3 -; CHECK-NEXT: WIDEN ir<%cmp2> = icmp sge ir<%lsd>, ir<200>, !dbg /tmp/s.c:10:3 -; CHECK-NEXT: EMIT vp<[[SEL1:%.+]]> = logical-and vp<[[NOT1]]>, ir<%cmp2>, !dbg /tmp/s.c:11:3 -; CHECK-NEXT: EMIT vp<[[OR1:%.+]]> = or vp<[[SEL1]]>, ir<%cmp1> -; CHECK-NEXT: Successor(s): pred.sdiv -; CHECK-EMPTY: -; CHECK-NEXT: pred.sdiv: { -; CHECK-NEXT: pred.sdiv.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<[[OR1]]> -; CHECK-NEXT: Successor(s): pred.sdiv.if, pred.sdiv.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.sdiv.if: -; CHECK-NEXT: REPLICATE ir<%sd1> = sdiv ir<%psd>, ir<%lsd> (S->V), !dbg /tmp/s.c:12:3 -; CHECK-NEXT: Successor(s): pred.sdiv.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.sdiv.continue: -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PHI:%.+]]> = ir<%sd1>, !dbg /tmp/s.c:12:3 +; CHECK-LABEL: 'recipe_debug_loc_location' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<128> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%isd> = getelementptr inbounds ir<%src>, vp<[[VP4]]>, !dbg /tmp/s.c:5:3 +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%isd>, !dbg /tmp/s.c:6:3 +; CHECK-NEXT: WIDEN ir<%lsd> = load vp<[[VP5]]>, !dbg /tmp/s.c:6:3 +; CHECK-NEXT: WIDEN ir<%psd> = add nuw nsw ir<%lsd>, ir<23>, !dbg /tmp/s.c:7:3 +; CHECK-NEXT: WIDEN ir<%cmp1> = icmp slt ir<%lsd>, ir<100>, !dbg /tmp/s.c:8:3 +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = not ir<%cmp1>, !dbg /tmp/s.c:9:3 +; CHECK-NEXT: WIDEN ir<%cmp2> = icmp sge ir<%lsd>, ir<200>, !dbg /tmp/s.c:10:3 +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = logical-and vp<[[VP6]]>, ir<%cmp2>, !dbg /tmp/s.c:11:3 +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = or vp<[[VP7]]>, ir<%cmp1> +; CHECK-NEXT: Successor(s): pred.sdiv +; CHECK-EMPTY: +; CHECK-NEXT: pred.sdiv: { +; CHECK-NEXT: pred.sdiv.entry: +; CHECK-NEXT: BRANCH-ON-MASK vp<[[VP8]]> +; CHECK-NEXT: Successor(s): pred.sdiv.if, pred.sdiv.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.sdiv.if: +; CHECK-NEXT: REPLICATE ir<%sd1> = sdiv ir<%psd>, ir<%lsd> (S->V), !dbg /tmp/s.c:12:3 +; CHECK-NEXT: Successor(s): pred.sdiv.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.sdiv.continue: +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP9:%[0-9]+]]> = ir<%sd1>, !dbg /tmp/s.c:12:3 +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): if.then.0 +; CHECK-EMPTY: +; CHECK-NEXT: if.then.0: +; CHECK-NEXT: BLEND ir<%ysd.0> = ir<%psd> vp<%9>/vp<[[VP8]]>, !dbg /tmp/s.c:14:3 +; CHECK-NEXT: vp<[[VP10:%[0-9]+]]> = vector-pointer inbounds ir<%isd>, !dbg /tmp/s.c:15:3 +; CHECK-NEXT: WIDEN store vp<[[VP10]]>, ir<%ysd.0>, !dbg /tmp/s.c:15:3 +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): if.then.0 -; CHECK-EMPTY: -; CHECK-NEXT: if.then.0: -; CHECK-NEXT: BLEND ir<%ysd.0> = ir<%psd> vp<[[PHI]]>/vp<[[OR1]]>, !dbg /tmp/s.c:14:3 -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%isd>, !dbg /tmp/s.c:15:3 -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%ysd.0>, !dbg /tmp/s.c:15:3 -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT:} -; CHECK-NEXT: Successor(s): middle.block +; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<128>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<128>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors ; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph: -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %if.end ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %cmp1 = icmp slt i32 %lsd, 100 -; CHECK-NEXT: No successors -; CHECK-NEXT:} +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %if.end ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %isd = getelementptr inbounds i32, ptr %src, i64 %iv, !dbg !7 +; CHECK-NEXT: IR %lsd = load i32, ptr %isd, align 4, !dbg !8 +; CHECK-NEXT: IR %psd = add nuw nsw i32 %lsd, 23, !dbg !9 +; CHECK-NEXT: IR %cmp1 = icmp slt i32 %lsd, 100, !dbg !10 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -435,56 +472,61 @@ declare float @llvm.sqrt.f32(float) nounwind readnone declare float @llvm.fmuladd.f32(float, float, float) define void @print_expand_scev(i64 %y, ptr %ptr) { -; CHECK-LABEL: Checking a loop in 'print_expand_scev' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.*]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %div = udiv i64 %y, 492802768830814060 -; CHECK-NEXT: IR %inc = add i64 %div, 1 -; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (1 + ((15 + (%y /u 492802768830814060)) /u (1 + (%y /u 492802768830814060)))) -; CHECK-NEXT: EMIT vp<[[EXP_SCEV:%.+]]> = EXPAND SCEV (1 + (%y /u 492802768830814060)) -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: vp<[[IV_END:%.+]]> = DERIVED-IV ir<0> + vp<[[VTC]]> * vp<[[EXP_SCEV]]> -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, vp<[[EXP_SCEV]]>, vp<[[VF]]> (truncated to i8) -; CHECK-NEXT: vp<[[DERIVED_IV:%.+]]> = DERIVED-IV ir<0> + vp<[[CAN_IV]]> * vp<[[EXP_SCEV]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DERIVED_IV]]>, vp<[[EXP_SCEV]]> -; CHECK-NEXT: WIDEN ir<%v3> = add nuw ir<%iv>, ir<1> -; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr inbounds ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: REPLICATE store ir<%v3>, ir<%gep> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[IV_END]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-LABEL: 'print_expand_scev' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %div = udiv i64 %y, 492802768830814060 +; CHECK-NEXT: IR %inc = add i64 %div, 1 +; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1 + ((15 + (%y /u 492802768830814060)) /u (1 + (%y /u 492802768830814060)))) +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = EXPAND SCEV (1 + (%y /u 492802768830814060)) +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP2]]> * vp<[[VP4]]> +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, vp<[[VP4]]>, vp<[[VP0]]> (truncated to i8) +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP6]]> * vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = SCALAR-STEPS vp<[[VP7]]>, vp<[[VP4]]>, vp<[[VP0]]> +; CHECK-NEXT: WIDEN ir<%v3> = add nuw ir<%iv>, ir<1> +; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr inbounds ir<%ptr>, vp<[[VP8]]> +; CHECK-NEXT: REPLICATE store ir<%v3>, ir<%gep> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP6]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP5]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %iv.next = add i64 %iv, %inc -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %loop ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %v2 = trunc i64 %iv to i8 +; CHECK-NEXT: IR %v3 = add nuw i8 %v2, 1 +; CHECK-NEXT: IR %gep = getelementptr inbounds i8, ptr %ptr, i64 %iv +; CHECK-NEXT: IR store i8 %v3, ptr %gep, align 1 +; CHECK-NEXT: IR %cmp15 = icmp slt i8 %v3, 16 +; CHECK-NEXT: IR %iv.next = add i64 %iv, %inc +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: %div = udiv i64 %y, 492802768830814060 @@ -507,54 +549,58 @@ loop.exit: } define i32 @print_exit_value(ptr %ptr, i32 %off) { -; CHECK-LABEL: Checking a loop in 'print_exit_value' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<1000> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1> -; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: WIDEN ir<%add> = add ir<%iv>, ir<%off> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<0> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[EXIT_PART:%.+]]> = extract-last-part ir<%add> -; CHECK-NEXT: EMIT vp<[[EXIT:%.+]]> = extract-last-lane vp<[[EXIT_PART]]> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<1000>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: IR %lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[EXIT]]> from middle.block) -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-LABEL: 'print_exit_value' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<1000> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds ir<%ptr>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep> +; CHECK-NEXT: WIDEN store vp<[[VP5]]>, ir<0> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: WIDEN ir<%add> = add ir<%iv>, ir<%off> +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = extract-last-part ir<%add> +; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = extract-last-lane vp<[[VP7]]> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %lcssa = phi i32 [ %add, %loop ] (extra operand: vp<[[VP8]]> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %ec = icmp eq i32 %iv.next, 1000 -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep = getelementptr inbounds i8, ptr %ptr, i32 %iv +; CHECK-NEXT: IR %add = add i32 %iv, %off +; CHECK-NEXT: IR store i8 0, ptr %gep, align 1 +; CHECK-NEXT: IR %iv.next = add nsw i32 %iv, 1 +; CHECK-NEXT: IR %ec = icmp eq i32 %iv.next, 1000 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -574,55 +620,63 @@ exit: } define void @print_fast_math_flags(i64 %n, ptr noalias %y, ptr noalias %x, ptr %z) { -; CHECK-LABEL: Checking a loop in 'print_fast_math_flags' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep.y> = getelementptr inbounds ir<%y>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.y> -; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN ir<%add> = fadd nnan ir<%lv>, ir<1.000000e+00> -; CHECK-NEXT: WIDEN ir<%mul> = fmul fast ir<%add>, ir<2.000000e+00> -; CHECK-NEXT: WIDEN ir<%div> = fdiv reassoc nsz contract ir<%mul>, ir<2.000000e+00> -; CHECK-NEXT: CLONE ir<%gep.x> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.x> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%div> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-LABEL: 'print_fast_math_flags' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.y> = getelementptr inbounds ir<%y>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.y> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN ir<%add> = fadd nnan ir<%lv>, ir<1.000000e+00> +; CHECK-NEXT: WIDEN ir<%mul> = fmul fast ir<%add>, ir<2.000000e+00> +; CHECK-NEXT: WIDEN ir<%div> = fdiv reassoc nsz contract ir<%mul>, ir<2.000000e+00> +; CHECK-NEXT: CLONE ir<%gep.x> = getelementptr inbounds ir<%x>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%gep.x> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%div> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] -; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep.y = getelementptr inbounds float, ptr %y, i64 %iv +; CHECK-NEXT: IR %lv = load float, ptr %gep.y, align 4 +; CHECK-NEXT: IR %add = fadd nnan float %lv, 1.000000e+00 +; CHECK-NEXT: IR %mul = fmul fast float %add, 2.000000e+00 +; CHECK-NEXT: IR %div = fdiv reassoc nsz contract float %mul, 2.000000e+00 +; CHECK-NEXT: IR %gep.x = getelementptr inbounds float, ptr %x, i64 %iv +; CHECK-NEXT: IR store float %div, ptr %gep.x, align 4 +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i64 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -645,54 +699,61 @@ exit: } define void @print_exact_flags(i64 %n, ptr noalias %x) { -; CHECK-LABEL: Checking a loop in 'print_exact_flags' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep.x> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.x> -; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN ir<%div.1> = udiv exact ir<%lv>, ir<20> -; CHECK-NEXT: WIDEN ir<%div.2> = udiv ir<%lv>, ir<60> -; CHECK-NEXT: WIDEN ir<%add> = add nuw nsw ir<%div.1>, ir<%div.2> -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%gep.x> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%add> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-LABEL: 'print_exact_flags' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.x> = getelementptr inbounds ir<%x>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.x> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN ir<%div.1> = udiv exact ir<%lv>, ir<20> +; CHECK-NEXT: WIDEN ir<%div.2> = udiv ir<%lv>, ir<60> +; CHECK-NEXT: WIDEN ir<%add> = add nuw nsw ir<%div.1>, ir<%div.2> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%gep.x> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%add> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n -; CHECK-NEXT: No successors -; ; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep.x = getelementptr inbounds i32, ptr %x, i64 %iv +; CHECK-NEXT: IR %lv = load i32, ptr %gep.x, align 4 +; CHECK-NEXT: IR %div.1 = udiv exact i32 %lv, 20 +; CHECK-NEXT: IR %div.2 = udiv i32 %lv, 60 +; CHECK-NEXT: IR %add = add nuw nsw i32 %div.1, %div.2 +; CHECK-NEXT: IR store i32 %add, ptr %gep.x, align 4 +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i64 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -714,75 +775,77 @@ exit: } define void @print_call_flags(ptr readonly %src, ptr noalias %dest, i64 %n) { -; CHECK-LABEL: Checking a loop in 'print_call_flags' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%ld.addr> = getelementptr inbounds ir<%src>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%ld.addr> -; CHECK-NEXT: WIDEN ir<%ld.value> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN ir<%ifcond> = fcmp oeq ir<%ld.value>, ir<5.000000e+00> -; CHECK-NEXT: Successor(s): pred.call -; CHECK-EMPTY: -; CHECK-NEXT: pred.call: { -; CHECK-NEXT: pred.call.entry: -; CHECK-NEXT: BRANCH-ON-MASK ir<%ifcond> -; CHECK-NEXT: Successor(s): pred.call.if, pred.call.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.call.if: -; CHECK-NEXT: REPLICATE ir<%foo.ret.1> = call nnan ninf nsz @foo(ir<%ld.value>) (S->V) -; CHECK-NEXT: REPLICATE ir<%foo.ret.2> = call @foo(ir<%ld.value>) (S->V) -; CHECK-NEXT: Successor(s): pred.call.continue -; CHECK-EMPTY: -; CHECK-NEXT: pred.call.continue: -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PHI1:%.+]]> = ir<%foo.ret.1> -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[PHI2:%.+]]> = ir<%foo.ret.2> +; CHECK-LABEL: 'print_call_flags' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%ld.addr> = getelementptr inbounds ir<%src>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%ld.addr> +; CHECK-NEXT: WIDEN ir<%ld.value> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN ir<%ifcond> = fcmp oeq ir<%ld.value>, ir<5.000000e+00> +; CHECK-NEXT: Successor(s): pred.call +; CHECK-EMPTY: +; CHECK-NEXT: pred.call: { +; CHECK-NEXT: pred.call.entry: +; CHECK-NEXT: BRANCH-ON-MASK ir<%ifcond> +; CHECK-NEXT: Successor(s): pred.call.if, pred.call.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.call.if: +; CHECK-NEXT: REPLICATE ir<%foo.ret.1> = call nnan ninf nsz @foo(ir<%ld.value>) (S->V) +; CHECK-NEXT: REPLICATE ir<%foo.ret.2> = call @foo(ir<%ld.value>) (S->V) +; CHECK-NEXT: Successor(s): pred.call.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.call.continue: +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP6:%[0-9]+]]> = ir<%foo.ret.1> +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[VP7:%[0-9]+]]> = ir<%foo.ret.2> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): if.then.1 +; CHECK-EMPTY: +; CHECK-NEXT: if.then.1: +; CHECK-NEXT: WIDEN ir<%fadd> = fadd vp<[[VP6]]>, vp<[[VP7]]> +; CHECK-NEXT: BLEND ir<%st.value> = ir<%ld.value> ir<%fadd>/ir<%ifcond> +; CHECK-NEXT: CLONE ir<%st.addr> = getelementptr inbounds ir<%dest>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP8:%[0-9]+]]> = vector-pointer inbounds ir<%st.addr> +; CHECK-NEXT: WIDEN store vp<[[VP8]]>, ir<%st.value> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> ; CHECK-NEXT: No successors ; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): if.then.1 -; CHECK-EMPTY: -; CHECK-NEXT: if.then.1: -; CHECK-NEXT: WIDEN ir<%fadd> = fadd vp<[[PHI1]]>, vp<[[PHI2]]> -; CHECK-NEXT: BLEND ir<%st.value> = ir<%ld.value> ir<%fadd>/ir<%ifcond> -; CHECK-NEXT: CLONE ir<%st.addr> = getelementptr inbounds ir<%dest>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%st.addr> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%st.value> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %ifcond = fcmp oeq float %ld.value, 5.0 -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %ld.addr = getelementptr inbounds float, ptr %src, i64 %iv +; CHECK-NEXT: IR %ld.value = load float, ptr %ld.addr, align 8 +; CHECK-NEXT: IR %ifcond = fcmp oeq float %ld.value, 5.000000e+00 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %for.body @@ -814,54 +877,61 @@ end: ; FIXME: Preserve disjoint flag on OR recipe. define void @print_disjoint_flags(i64 %n, ptr noalias %x) { -; CHECK-LABEL: Checking a loop in 'print_disjoint_flags' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%n> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep.x> = getelementptr inbounds ir<%x>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.x> -; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN ir<%or.1> = or disjoint ir<%lv>, ir<1> -; CHECK-NEXT: WIDEN ir<%or.2> = or ir<%lv>, ir<3> -; CHECK-NEXT: WIDEN ir<%add> = add nuw nsw ir<%or.1>, ir<%or.2> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.x> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%add> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<%n>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-LABEL: 'print_disjoint_flags' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%n> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.x> = getelementptr inbounds ir<%x>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.x> +; CHECK-NEXT: WIDEN ir<%lv> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN ir<%or.1> = or disjoint ir<%lv>, ir<1> +; CHECK-NEXT: WIDEN ir<%or.2> = or ir<%lv>, ir<3> +; CHECK-NEXT: WIDEN ir<%add> = add nuw nsw ir<%or.1>, ir<%or.2> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%gep.x> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<%add> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%n>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %exitcond = icmp eq i64 %iv.next, %n -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep.x = getelementptr inbounds i32, ptr %x, i64 %iv +; CHECK-NEXT: IR %lv = load i32, ptr %gep.x, align 4 +; CHECK-NEXT: IR %or.1 = or disjoint i32 %lv, 1 +; CHECK-NEXT: IR %or.2 = or i32 %lv, 3 +; CHECK-NEXT: IR %add = add nuw nsw i32 %or.1, %or.2 +; CHECK-NEXT: IR store i32 %add, ptr %gep.x, align 4 +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %exitcond = icmp eq i64 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -883,34 +953,58 @@ exit: } define void @zext_nneg(ptr noalias %p, ptr noalias %p1) { -; CHECK-LABEL: LV: Checking a loop in 'zext_nneg' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count +; CHECK-LABEL: 'zext_nneg' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count ; CHECK-NEXT: Live-in ir<1000> = original trip-count ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: ; CHECK-NEXT: vector.ph: ; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%idx> = getelementptr ir<%p>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%idx> -; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: WIDEN-CAST ir<%zext> = zext nneg ir<%l> -; CHECK-NEXT: EMIT vp<[[EXT_PART:%.+]]> = extract-last-part ir<%zext> -; CHECK-NEXT: EMIT vp<[[EXT:%.+]]> = extract-last-lane vp<[[EXT_PART]]> -; CHECK-NEXT: CLONE store vp<[[EXT]]>, ir<%p1> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%idx> = getelementptr ir<%p>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer ir<%idx> +; CHECK-NEXT: WIDEN ir<%l> = load vp<[[VP5]]> +; CHECK-NEXT: WIDEN-CAST ir<%zext> = zext nneg ir<%l> to i64 +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = extract-last-part ir<%zext> +; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = extract-last-lane vp<[[VP6]]> +; CHECK-NEXT: CLONE store vp<[[VP7]]>, ir<%p1> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ %next, %body ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %idx = getelementptr i32, ptr %p, i64 %iv +; CHECK-NEXT: IR %l = load i32, ptr %idx, align 8 +; CHECK-NEXT: IR %zext = zext nneg i32 %l to i64 +; CHECK-NEXT: IR store i64 %zext, ptr %p1, align 8 +; CHECK-NEXT: IR %next = add i64 %iv, 1 +; CHECK-NEXT: IR %cmp = icmp eq i64 %next, 1000 ; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: } ; entry: br label %body @@ -931,59 +1025,64 @@ exit: define i16 @print_first_order_recurrence_and_result(ptr %ptr) { ; CHECK-LABEL: 'print_first_order_recurrence_and_result' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<1000> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.1> = phi ir<22>, ir<%for.1.next> -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%gep.ptr> = getelementptr inbounds ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer inbounds ir<%gep.ptr> -; CHECK-NEXT: WIDEN ir<%for.1.next> = load vp<[[VEC_PTR]]> -; CHECK-NEXT: EMIT vp<[[FOR1_SPLICE:%.+]]> = first-order splice ir<%for.1>, ir<%for.1.next> -; CHECK-NEXT: WIDEN ir<%add> = add vp<[[FOR1_SPLICE]]>, ir<1> -; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer inbounds ir<%gep.ptr> -; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%add> -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block -; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[RESUME_1_PART:%.+]]> = extract-last-part ir<%for.1.next> -; CHECK-NEXT: EMIT vp<[[RESUME_1:%.+]]> = extract-last-lane vp<[[RESUME_1_PART]]> -; CHECK-NEXT: EMIT vp<[[FOR_RESULT:%.+]]> = extract-penultimate-element ir<%for.1.next> -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<1000>, vp<[[VTC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> -; CHECK-NEXT: Successor(s): ir-bb, scalar.ph -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb -; CHECK-NEXT: IR %for.1.lcssa = phi i16 [ %for.1, %loop ] (extra operand: vp<[[FOR_RESULT]]> from middle.block) -; CHECK-NEXT: No successors -; CHECK-EMPTY: -; CHECK-NEXT: scalar.ph -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_P:%.*]]> = phi [ vp<[[RESUME_1]]>, middle.block ], [ ir<22>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME_IV:%.+]]> = phi [ vp<[[VTC]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<1000> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: FIRST-ORDER-RECURRENCE-PHI ir<%for.1> = phi ir<22>, ir<%for.1.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep.ptr> = getelementptr inbounds ir<%ptr>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds ir<%gep.ptr> +; CHECK-NEXT: WIDEN ir<%for.1.next> = load vp<[[VP5]]> +; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = first-order splice ir<%for.1>, ir<%for.1.next> +; CHECK-NEXT: WIDEN ir<%add> = add vp<[[VP6]]>, ir<1> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%gep.ptr> +; CHECK-NEXT: WIDEN store vp<[[VP7]]>, ir<%add> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = extract-last-part ir<%for.1.next> +; CHECK-NEXT: EMIT vp<%vector.recur.extract> = extract-last-lane vp<[[VP9]]> +; CHECK-NEXT: EMIT vp<%vector.recur.extract.for.phi> = extract-penultimate-element ir<%for.1.next> +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1000>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %for.1.lcssa = phi i16 [ %for.1, %loop ] (extra operand: vp<%vector.recur.extract.for.phi> from middle.block) +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%scalar.recur.init> = phi [ vp<%vector.recur.extract>, middle.block ], [ ir<22>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %for.1 = phi i16 [ 22, %entry ], [ %for.1.next, %loop ] (extra operand: vp<[[RESUME_P]]> from scalar.ph) -; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME_IV]]> from scalar.ph) -; CHECK: IR %exitcond.not = icmp eq i64 %iv.next, 1000 -; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: IR %for.1 = phi i16 [ 22, %entry ], [ %for.1.next, %loop ] (extra operand: vp<%scalar.recur.init> from scalar.ph) +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 1 +; CHECK-NEXT: IR %gep.ptr = getelementptr inbounds i16, ptr %ptr, i64 %iv +; CHECK-NEXT: IR %for.1.next = load i16, ptr %gep.ptr, align 2 +; CHECK-NEXT: IR %add = add i16 %for.1, 1 +; CHECK-NEXT: IR store i16 %add, ptr %gep.ptr, align 2 +; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, 1000 +; CHECK-NEXT: No successors +; CHECK-NEXT: } ; entry: br label %loop @@ -1005,39 +1104,68 @@ exit: define void @print_select_with_fastmath_flags(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) { ; CHECK-LABEL: 'print_select_with_fastmath_flags' -; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count -; CHECK-NEXT: Live-in ir<%N> = original trip-count -; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph -; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: Successor(s): vector loop -; CHECK-EMPTY: -; CHECK: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[IV_NEXT_EXIT:%.+]]> -; CHECK-NEXT: vp<[[ST:%.+]]> = SCALAR-STEPS vp<[[IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds nuw ir<%b>, vp<[[ST]]> -; CHECK-NEXT: vp<[[PTR1:%.+]]> = vector-pointer inbounds nuw ir<[[GEP1]]> -; CHECK-NEXT: WIDEN ir<[[LD1:%.+]]> = load vp<[[PTR1]]> -; CHECK-NEXT: CLONE ir<[[GEP2:%.+]]> = getelementptr inbounds nuw ir<%c>, vp<[[ST]]> -; CHECK-NEXT: vp<[[PTR2:%.+]]> = vector-pointer inbounds nuw ir<[[GEP2]]> -; CHECK-NEXT: WIDEN ir<[[LD2:%.+]]> = load vp<[[PTR2]]> -; CHECK-NEXT: WIDEN ir<[[FCMP:%.+]]> = fcmp ogt fast ir<[[LD1]]>, ir<[[LD2]]> -; CHECK-NEXT: WIDEN ir<[[FADD:%.+]]> = fadd fast ir<[[LD1]]>, ir<1.000000e+01> -; CHECK-NEXT: WIDEN ir<[[SELECT:%.+]]> = select fast ir<[[FCMP]]>, ir<[[FADD]]>, ir<[[LD2]]> -; CHECK-NEXT: CLONE ir<[[GEP3:%.+]]> = getelementptr inbounds nuw ir<%a>, vp<[[ST]]> -; CHECK-NEXT: vp<[[PTR3:%.+]]> = vector-pointer inbounds nuw ir<[[GEP3]]> -; CHECK-NEXT: WIDEN store vp<[[PTR3]]>, ir<[[SELECT]]> -; CHECK-NEXT: EMIT vp<[[IV_NEXT_EXIT]]> = add nuw vp<[[IV]]>, vp<[[VFUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, vp<[[VTC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } - +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<%N> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<[[VP3]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep> = getelementptr inbounds nuw ir<%b>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = vector-pointer inbounds nuw ir<%gep> +; CHECK-NEXT: WIDEN ir<%0> = load vp<[[VP5]]> +; CHECK-NEXT: CLONE ir<%gep3> = getelementptr inbounds nuw ir<%c>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds nuw ir<%gep3> +; CHECK-NEXT: WIDEN ir<%1> = load vp<[[VP6]]> +; CHECK-NEXT: WIDEN ir<%cmp4> = fcmp ogt fast ir<%0>, ir<%1> +; CHECK-NEXT: WIDEN ir<%add> = fadd fast ir<%0>, ir<1.000000e+01> +; CHECK-NEXT: WIDEN ir<%cond> = select fast ir<%cmp4>, ir<%add>, ir<%1> +; CHECK-NEXT: CLONE ir<%gep11> = getelementptr inbounds nuw ir<%a>, vp<[[VP4]]> +; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds nuw ir<%gep11> +; CHECK-NEXT: WIDEN store vp<[[VP7]]>, ir<%cond> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%N>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ %iv.next, %for.body ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep = getelementptr inbounds nuw float, ptr %b, i64 %iv +; CHECK-NEXT: IR %0 = load float, ptr %gep, align 4 +; CHECK-NEXT: IR %gep3 = getelementptr inbounds nuw float, ptr %c, i64 %iv +; CHECK-NEXT: IR %1 = load float, ptr %gep3, align 4 +; CHECK-NEXT: IR %cmp4 = fcmp fast ogt float %0, %1 +; CHECK-NEXT: IR %add = fadd fast float %0, 1.000000e+01 +; CHECK-NEXT: IR %cond = select fast i1 %cmp4, float %add, float %1 +; CHECK-NEXT: IR %gep11 = getelementptr inbounds nuw float, ptr %a, i64 %iv +; CHECK-NEXT: IR store float %cond, ptr %gep11, align 4 +; CHECK-NEXT: IR %iv.next = add nuw nsw i64 %iv, 1 +; CHECK-NEXT: IR %exitcond.not = icmp eq i64 %iv.next, %N +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; entry: br label %for.body diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll index 9550454b1a3c2..3896e67c81b1b 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge-vf1.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 6 ; REQUIRES: asserts ; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -debug -disable-output %s 2>&1 | FileCheck %s @@ -6,68 +7,73 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ; Make sure recipes with side-effects are not sunk. define void @sink_with_sideeffects(i1 %c, ptr %ptr) { -; CHECK-LABEL: sink_with_sideeffects -; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' { -; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF -; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF -; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count -; CHECK-NEXT: ir<1024> = original trip-count +; CHECK-LABEL: 'sink_with_sideeffects' +; CHECK: VPlan 'Initial VPlan for VF={1},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: Live-in ir<1024> = original trip-count ; CHECK-EMPTY: -; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph ; CHECK-EMPTY: -; CHECK-NEXT: vector.ph: -; CHECK-NEXT: vp<[[END:%.+]]> = DERIVED-IV ir<1024> + vp<[[VEC_TC]]> * ir<-1> -; CHECK-NEXT: Successor(s): vector loop +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = DERIVED-IV ir<1024> + vp<[[VP2]]> * ir<-1> +; CHECK-NEXT: Successor(s): vector loop ; CHECK-EMPTY: -; CHECK-NEXT: vector loop: { -; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION -; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>, vp<[[VF]]> -; CHECK-NEXT: CLONE ir<%tmp2> = getelementptr ir<%ptr>, vp<[[STEPS]]> -; CHECK-NEXT: CLONE ir<%tmp3> = load ir<%tmp2> -; CHECK-NEXT: CLONE store ir<0>, ir<%tmp2> -; CHECK-NEXT: Successor(s): pred.store - -; CHECK: pred.store: { -; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK ir<%c> -; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue - -; CHECK: pred.store.if: -; CHECK-NEXT: CLONE store ir<%tmp3>, ir<%tmp2> -; CHECK-NEXT: Successor(s): pred.store.continue - -; CHECK: pred.store.continue: -; CHECK-NEXT: No successors -; CHECK-NEXT: } - -; CHECK: if.then.0: -; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> -; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]> -; CHECK-NEXT: No successors -; CHECK-NEXT: } -; CHECK-NEXT: Successor(s): middle.block +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%tmp2> = getelementptr ir<%ptr>, vp<[[VP5]]> +; CHECK-NEXT: CLONE ir<%tmp3> = load ir<%tmp2> +; CHECK-NEXT: CLONE store ir<0>, ir<%tmp2> +; CHECK-NEXT: Successor(s): pred.store +; CHECK-EMPTY: +; CHECK-NEXT: pred.store: { +; CHECK-NEXT: pred.store.entry: +; CHECK-NEXT: BRANCH-ON-MASK ir<%c> +; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.if: +; CHECK-NEXT: CLONE store ir<%tmp3>, ir<%tmp2> +; CHECK-NEXT: Successor(s): pred.store.continue +; CHECK-EMPTY: +; CHECK-NEXT: pred.store.continue: +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): if.then.0 +; CHECK-EMPTY: +; CHECK-NEXT: if.then.0: +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block ; CHECK-EMPTY: -; CHECK-NEXT: middle.block: -; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq ir<1024>, vp<[[VEC_TC]]> -; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]> +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<1024>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> ; CHECK-NEXT: Successor(s): ir-bb, scalar.ph ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: ; CHECK-NEXT: No successors ; CHECK-EMPTY: ; CHECK-NEXT: scalar.ph: -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME1:%.+]]> = phi [ vp<[[VEC_TC]]>, middle.block ], [ ir<0>, ir-bb ] -; CHECK-NEXT: EMIT-SCALAR vp<[[RESUME2:%.+]]>.1 = phi [ vp<[[END]]>, middle.block ], [ ir<1024>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val>.1 = phi [ vp<[[VP3]]>, middle.block ], [ ir<1024>, ir-bb ] ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: IR %tmp0 = phi i64 [ %tmp6, %for.inc ], [ 0, %entry ] (extra operand: vp<[[RESUME1]]> from scalar.ph) -; CHECK-NEXT: IR %tmp1 = phi i64 [ %tmp7, %for.inc ], [ 1024, %entry ] (extra operand: vp<[[RESUME2]]>.1 from scalar.ph) -; CHECK: IR %tmp5 = trunc i32 %tmp4 to i8 +; CHECK-NEXT: IR %tmp0 = phi i64 [ %tmp6, %for.inc ], [ 0, %entry ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %tmp1 = phi i64 [ %tmp7, %for.inc ], [ 1024, %entry ] (extra operand: vp<%bc.resume.val>.1 from scalar.ph) +; CHECK-NEXT: IR %tmp2 = getelementptr i8, ptr %ptr, i64 %tmp0 +; CHECK-NEXT: IR %tmp3 = load i8, ptr %tmp2, align 1 +; CHECK-NEXT: IR store i8 0, ptr %tmp2, align 1 +; CHECK-NEXT: IR %tmp4 = zext i8 %tmp3 to i32 +; CHECK-NEXT: IR %tmp5 = trunc i32 %tmp4 to i8 ; CHECK-NEXT: No successors -; CHECK-NEXT: } +; CHECK-NEXT: } ; entry: br label %for.body diff --git a/llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-dominance.ll b/llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-dominance.ll index 2af9909ee396b..a6308c5a97333 100644 --- a/llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-dominance.ll +++ b/llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-dominance.ll @@ -369,5 +369,54 @@ entry: declare ptr @get_address() +define void @multiply_phi_dominates_matmul(ptr noalias %A, ptr noalias %B, ptr noalias %C, i64 %n) { +; CHECK-LABEL: @multiply_phi_dominates_matmul( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8 +; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr i8, ptr [[A]], i64 16 +; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 +; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8 +; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr i8, ptr [[B]], i64 16 +; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8 +; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] +; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]]) +; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]] +; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]]) +; CHECK-NEXT: [[OFFSET:%.*]] = shl i64 [[IV]], 5 +; CHECK-NEXT: [[DST:%.*]] = getelementptr i8, ptr [[C:%.*]], i64 [[OFFSET]] +; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[DST]], align 8 +; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr i8, ptr [[DST]], i64 16 +; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[VEC_GEP14]], align 8 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[COND:%.*]] = icmp ult i64 [[IV_NEXT]], [[N:%.*]] +; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %a = load <4 x double>, ptr %A, align 8 + %b = load <4 x double>, ptr %B, align 8 + %c = call <4 x double> @llvm.matrix.multiply(<4 x double> %a, <4 x double> %b, i32 2, i32 2, i32 2) + %offset = mul i64 %iv, 32 + %dst = getelementptr i8, ptr %C, i64 %offset + store <4 x double> %c, ptr %dst, align 8 + %iv.next = add i64 %iv, 1 + %cond = icmp ult i64 %iv.next, %n + br i1 %cond, label %loop, label %exit + +exit: + ret void +} declare <4 x double> @llvm.matrix.multiply(<4 x double>, <4 x double>, i32, i32, i32) diff --git a/llvm/test/Transforms/PGOProfile/chr.ll b/llvm/test/Transforms/PGOProfile/chr.ll index 258af5c488997..b7f35ba025657 100644 --- a/llvm/test/Transforms/PGOProfile/chr.ll +++ b/llvm/test/Transforms/PGOProfile/chr.ll @@ -35,16 +35,15 @@ define void @test_chr_1(ptr %i) !prof !14 { ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16:![0-9]+]] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: br i1 [[TMP3]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16:![0-9]+]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF17:![0-9]+]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3]] @@ -109,23 +108,22 @@ define void @test_chr_1_1(ptr %i) !prof !14 { ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB5:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: br i1 [[TMP3]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB3_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB3_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: call void @bar() ; CHECK-NEXT: br label [[BB3_NONCHR]] ; CHECK: bb3.nonchr: ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[DOTFR1]], 4 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 -; CHECK-NEXT: br i1 [[TMP7]], label [[BB5]], label [[BB4_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP7]], label [[BB5]], label [[BB4_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb4.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB5]] @@ -198,15 +196,15 @@ define void @test_chr_2(ptr %i) !prof !14 { ; CHECK: entry.split.nonchr: ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR1]], 255 ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB4]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB4]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 1 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 -; CHECK-NEXT: br i1 [[TMP7]], label [[BB4]], label [[BB3_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP7]], label [[BB4]], label [[BB3_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb3.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB4]] @@ -290,16 +288,15 @@ define void @test_chr_3(ptr %i) !prof !14 { ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: br i1 [[TMP3]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3]] @@ -316,14 +313,14 @@ define void @test_chr_3(ptr %i) !prof !14 { ; CHECK: bb3.split.nonchr: ; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[DOTFR2]], 4 ; CHECK-NEXT: [[DOTNOT3:%.*]] = icmp eq i32 [[TMP9]], 0 -; CHECK-NEXT: br i1 [[DOTNOT3]], label [[BB5_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[DOTNOT3]], label [[BB5_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb4.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB5_NONCHR]] ; CHECK: bb5.nonchr: ; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[DOTFR2]], 8 ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0 -; CHECK-NEXT: br i1 [[TMP11]], label [[BB7]], label [[BB6_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP11]], label [[BB7]], label [[BB6_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb6.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB7]] @@ -403,13 +400,12 @@ define i32 @test_chr_4(ptr %i, i32 %sum0) !prof !14 { ; CHECK-NEXT: br label [[COMMON_RET:%.*]] ; CHECK: entry.split.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[SUM0]], 42 -; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0 -; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[DOTNOT]], i32 [[SUM0]], i32 [[TMP4]], !prof [[PROF16]] +; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP5]], i32 [[TMP4]], i32 [[SUM0]], !prof [[PROF16]] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 ; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM1_NONCHR]], 43 -; CHECK-NEXT: [[SUM2_NONCHR]] = select i1 [[TMP7]], i32 [[SUM1_NONCHR]], i32 [[TMP8]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2_NONCHR]] = select i1 [[TMP7]], i32 [[SUM1_NONCHR]], i32 [[TMP8]], !prof [[PROF17]] ; CHECK-NEXT: br label [[COMMON_RET]] ; entry: @@ -464,23 +460,23 @@ define i32 @test_chr_5(ptr %i, i32 %sum0) !prof !14 { ; CHECK: entry.split.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 255 ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[DOTFR1]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0 ; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[SUM0]], 42 -; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM0]], i32 [[TMP7]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM0]], i32 [[TMP7]], !prof [[PROF17]] ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0 ; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[SUM1_NONCHR]], 43 -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP9]], i32 [[SUM1_NONCHR]], i32 [[TMP10]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP9]], i32 [[SUM1_NONCHR]], i32 [[TMP10]], !prof [[PROF17]] ; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[DOTFR1]], 4 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP11]], 0 ; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[DOTFR1]], 8 ; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0 -; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP14]], i32 44, i32 88 +; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP14]], i32 44, i32 88, !prof [[PROF17]] ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]] -; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP12]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP12]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF17]] ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb3: ; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ], [ [[TMP3]], [[BB1]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ] @@ -557,7 +553,7 @@ define i32 @test_chr_5_1(ptr %i, i32 %sum0) !prof !14 { ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR1]], 11 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 11 -; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]] ; CHECK-NEXT: br i1 [[TMP5]], label [[BB1:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]] ; CHECK: bb1: ; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[SUM0_FR]], 173 @@ -565,23 +561,23 @@ define i32 @test_chr_5_1(ptr %i, i32 %sum0) !prof !14 { ; CHECK: entry.split.nonchr: ; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[DOTFR1]], 255 ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP7]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[DOTFR1]], 1 ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0 ; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[SUM0_FR]], 42 -; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP9]], i32 [[SUM0_FR]], i32 [[TMP10]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[TMP9]], i32 [[SUM0_FR]], i32 [[TMP10]], !prof [[PROF17]] ; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP11]], 0 ; CHECK-NEXT: [[TMP13:%.*]] = add i32 [[SUM1_NONCHR]], 43 -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP12]], i32 [[SUM1_NONCHR]], i32 [[TMP13]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP12]], i32 [[SUM1_NONCHR]], i32 [[TMP13]], !prof [[PROF17]] ; CHECK-NEXT: [[TMP14:%.*]] = and i32 [[SUM0_FR]], 4 ; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0 ; CHECK-NEXT: [[TMP16:%.*]] = and i32 [[DOTFR1]], 8 ; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[TMP16]], 0 -; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP17]], i32 44, i32 88 +; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP17]], i32 44, i32 88, !prof [[PROF17]] ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]] -; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP15]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP15]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF17]] ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb3: ; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ], [ [[TMP6]], [[BB1]] ], [ [[SUM0_FR]], [[ENTRY_SPLIT_NONCHR]] ] @@ -667,19 +663,19 @@ define i32 @test_chr_6(ptr %i, ptr %j, i32 %sum0) !prof !14 { ; CHECK: entry.split.nonchr: ; CHECK-NEXT: [[V1:%.*]] = and i32 [[I0_FR]], 255 ; CHECK-NEXT: [[V2_NOT:%.*]] = icmp eq i32 [[V1]], 0 -; CHECK-NEXT: br i1 [[V2_NOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[V2_NOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: [[V3_NONCHR:%.*]] = and i32 [[I0_FR]], 2 ; CHECK-NEXT: [[V4_NONCHR:%.*]] = icmp eq i32 [[V3_NONCHR]], 0 ; CHECK-NEXT: [[V8_NONCHR:%.*]] = add i32 [[SUM0]], 43 -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[V4_NONCHR]], i32 [[SUM0]], i32 [[V8_NONCHR]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[V4_NONCHR]], i32 [[SUM0]], i32 [[V8_NONCHR]], !prof [[PROF17]] ; CHECK-NEXT: [[V9_NONCHR:%.*]] = and i32 [[J0_FR]], 4 ; CHECK-NEXT: [[V10_NONCHR:%.*]] = icmp eq i32 [[V9_NONCHR]], 0 ; CHECK-NEXT: [[V11_NONCHR:%.*]] = and i32 [[I0_FR]], 8 ; CHECK-NEXT: [[V12_NONCHR:%.*]] = icmp eq i32 [[V11_NONCHR]], 0 -; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[V12_NONCHR]], i32 44, i32 88 +; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[V12_NONCHR]], i32 44, i32 88, !prof [[PROF17]] ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]] -; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[V10_NONCHR]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[V10_NONCHR]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF17]] ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb3: ; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ], [ [[V13]], [[BB1]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ] @@ -739,12 +735,12 @@ define i32 @test_chr_7(ptr %i, ptr %j, i32 %sum0) !prof !14 { ; CHECK-NEXT: [[V3:%.*]] = and i32 [[I0]], 2 ; CHECK-NEXT: [[V4:%.*]] = icmp eq i32 [[V3]], 0 ; CHECK-NEXT: [[V8:%.*]] = add i32 [[SUM0:%.*]], 43 -; CHECK-NEXT: [[SUM2:%.*]] = select i1 [[V4]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2:%.*]] = select i1 [[V4]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF17]] ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: [[J0:%.*]] = load i32, ptr [[J:%.*]], align 4 ; CHECK-NEXT: [[V9:%.*]] = and i32 [[J0]], 4 ; CHECK-NEXT: [[V10:%.*]] = icmp eq i32 [[V9]], 0 -; CHECK-NEXT: br i1 [[V10]], label [[BB2:%.*]], label [[BB1:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[V10]], label [[BB2:%.*]], label [[BB1:%.*]], !prof [[PROF17]] ; CHECK: bb1: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: [[SUM4:%.*]] = add i32 [[SUM2]], 44 @@ -819,14 +815,14 @@ define i32 @test_chr_7_1(ptr %i, ptr %j, i32 %sum0) !prof !14 { ; CHECK: entry.split.nonchr: ; CHECK-NEXT: [[V9:%.*]] = and i32 [[J0_FR]], 4 ; CHECK-NEXT: [[V10_NOT:%.*]] = icmp eq i32 [[V9]], 0 -; CHECK-NEXT: br i1 [[V10_NOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[V10_NOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[V11_NONCHR:%.*]] = and i32 [[J0_FR]], 8 ; CHECK-NEXT: [[V12_NONCHR:%.*]] = icmp eq i32 [[V11_NONCHR]], 0 -; CHECK-NEXT: br i1 [[V12_NONCHR]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[V12_NONCHR]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3]] @@ -834,7 +830,7 @@ define i32 @test_chr_7_1(ptr %i, ptr %j, i32 %sum0) !prof !14 { ; CHECK-NEXT: [[V3:%.*]] = and i32 [[I0]], 2 ; CHECK-NEXT: [[V4:%.*]] = icmp eq i32 [[V3]], 0 ; CHECK-NEXT: [[V8:%.*]] = add i32 [[SUM0:%.*]], 43 -; CHECK-NEXT: [[SUM2:%.*]] = select i1 [[V4]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2:%.*]] = select i1 [[V4]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF17]] ; CHECK-NEXT: ret i32 [[SUM2]] ; entry: @@ -881,14 +877,14 @@ define void @test_chr_8(ptr %i) !prof !14 { ; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 -; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF17:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF18:![0-9]+]] ; CHECK: bb0: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1]] ; CHECK: bb1: ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 2 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[TMP4]], label [[BB3:%.*]], label [[BB2:%.*]], !prof [[PROF17]] +; CHECK-NEXT: br i1 [[TMP4]], label [[BB3:%.*]], label [[BB2:%.*]], !prof [[PROF18]] ; CHECK: bb2: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3]] @@ -959,16 +955,15 @@ define i32 @test_chr_9(ptr %i, ptr %j) !prof !14 { ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: br i1 [[TMP4]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0 -; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP6]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4 ; CHECK-NEXT: call void @foo() @@ -1041,9 +1036,8 @@ define i32 @test_chr_10(ptr %i, ptr %j) !prof !14 { ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: br i1 [[TMP4]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] @@ -1051,7 +1045,7 @@ define i32 @test_chr_10(ptr %i, ptr %j) !prof !14 { ; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[J]], align 4 ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 -; CHECK-NEXT: br i1 [[TMP7]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP7]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3]] @@ -1123,22 +1117,21 @@ define void @test_chr_11(ptr %i, i32 %x) !prof !14 { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4 ; CHECK-NEXT: [[DOTFR1:%.*]] = freeze i32 [[TMP0]] -; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[DOTFR1]] to i1 ; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[DOTFR1]] to double ; CHECK-NEXT: [[DIV:%.*]] = fdiv double 1.000000e+00, [[CONV]] ; CHECK-NEXT: [[MUL16:%.*]] = fmul double [[DIV]], [[CONV]] ; CHECK-NEXT: [[CONV717:%.*]] = fptosi double [[MUL16]] to i32 ; CHECK-NEXT: [[CONV717_FR:%.*]] = freeze i32 [[CONV717]] ; CHECK-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[CONV717_FR]], 0 -; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP2]], [[CMP18]] -; CHECK-NEXT: br i1 [[TMP3]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]] +; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[CMP18]], [[TMP1]] +; CHECK-NEXT: br i1 [[TMP2]], label [[BB0:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]] ; CHECK: bb0: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: br i1 [[TMP2]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF18:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP1]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] @@ -1148,7 +1141,7 @@ define void @test_chr_11(ptr %i, i32 %x) !prof !14 { ; CHECK-NEXT: [[MUL16_NONCHR:%.*]] = fmul double [[DIV_NONCHR]], [[CONV_NONCHR]] ; CHECK-NEXT: [[CONV717_NONCHR:%.*]] = fptosi double [[MUL16_NONCHR]] to i32 ; CHECK-NEXT: [[CMP18_NONCHR:%.*]] = icmp slt i32 [[CONV717_NONCHR]], 1 -; CHECK-NEXT: br i1 [[CMP18_NONCHR]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[CMP18_NONCHR]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3]] @@ -1189,16 +1182,16 @@ define i32 @test_chr_12(ptr %i, i32 %sum0) !prof !14 { ; CHECK-NEXT: [[DOTFR2:%.*]] = freeze i32 [[TMP0]] ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[DOTFR2]], 255 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 -; CHECK-NEXT: br i1 [[TMP2]], label [[BB3:%.*]], label [[BB0:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP2]], label [[BB3:%.*]], label [[BB0:%.*]], !prof [[PROF17]] ; CHECK: bb0: ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0 ; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[SUM0:%.*]], 42 -; CHECK-NEXT: [[SUM1:%.*]] = select i1 [[TMP4]], i32 [[SUM0]], i32 [[TMP5]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM1:%.*]] = select i1 [[TMP4]], i32 [[SUM0]], i32 [[TMP5]], !prof [[PROF17]] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[DOTFR2]], 2 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 ; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM1]], 43 -; CHECK-NEXT: [[SUM2:%.*]] = select i1 [[TMP7]], i32 [[SUM1]], i32 [[TMP8]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2:%.*]] = select i1 [[TMP7]], i32 [[SUM1]], i32 [[TMP8]], !prof [[PROF17]] ; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 ; CHECK-NEXT: [[DOTFR:%.*]] = freeze i32 [[TMP9]] ; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i32 [[DOTFR]], 0 @@ -1210,11 +1203,11 @@ define i32 @test_chr_12(ptr %i, i32 %sum0) !prof !14 { ; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[SUM2]], 88 ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb0.split.nonchr: -; CHECK-NEXT: br i1 [[TMP10]], label [[BB1_NONCHR:%.*]], label [[BB3]], !prof [[PROF18]] +; CHECK-NEXT: br i1 [[TMP10]], label [[BB1_NONCHR:%.*]], label [[BB3]], !prof [[PROF16]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[TMP15:%.*]] = and i32 [[DOTFR2]], 8 ; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[TMP15]], 0 -; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP16]], i32 44, i32 88, !prof [[PROF16]] +; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP16]], i32 44, i32 88, !prof [[PROF17]] ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2]], [[SUM4_NONCHR_V]] ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb3: @@ -1302,7 +1295,7 @@ define i32 @test_chr_14(ptr %i, ptr %j, i32 %sum0, i1 %pred, i32 %z) !prof !14 { ; CHECK-NEXT: [[PRED_FR:%.*]] = freeze i1 [[PRED:%.*]] ; CHECK-NEXT: [[V0:%.*]] = icmp eq i32 [[Z_FR]], 0 ; CHECK-NEXT: [[V3_NONCHR:%.*]] = and i1 [[V0]], [[PRED_FR]] -; CHECK-NEXT: br i1 [[V3_NONCHR]], label [[BB0_NONCHR:%.*]], label [[BB1]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[V3_NONCHR]], label [[BB0_NONCHR:%.*]], label [[BB1]], !prof [[PROF17]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1]] @@ -1325,7 +1318,7 @@ define i32 @test_chr_14(ptr %i, ptr %j, i32 %sum0, i1 %pred, i32 %z) !prof !14 { ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb1.split.nonchr: ; CHECK-NEXT: [[V5_NONCHR:%.*]] = icmp eq i32 [[I0_FR]], [[J0_FR]] -; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = select i1 [[V5_NONCHR]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = select i1 [[V5_NONCHR]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF17]] ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: [[V9_NONCHR:%.*]] = and i32 [[I0_FR]], 4 ; CHECK-NEXT: [[V10_NONCHR:%.*]] = icmp eq i32 [[V9_NONCHR]], 0 @@ -1392,8 +1385,8 @@ define i32 @test_chr_15(ptr %i, ptr %j, i32 %sum0, i1 %pred, i32 %z) !prof !14 { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[I0:%.*]] = load i32, ptr [[I:%.*]], align 4 ; CHECK-NEXT: [[V0:%.*]] = icmp eq i32 [[Z:%.*]], 0 -; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i1 [[PRED:%.*]], i1 false -; CHECK-NEXT: br i1 [[V3]], label [[BB0:%.*]], label [[BB1:%.*]], !prof [[PROF16]] +; CHECK-NEXT: [[V3:%.*]] = select i1 [[V0]], i1 [[PRED:%.*]], i1 false, !prof [[PROF19:![0-9]+]] +; CHECK-NEXT: br i1 [[V3]], label [[BB0:%.*]], label [[BB1:%.*]], !prof [[PROF17]] ; CHECK: bb0: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1]] @@ -1410,9 +1403,9 @@ define i32 @test_chr_15(ptr %i, ptr %j, i32 %sum0, i1 %pred, i32 %z) !prof !14 { ; CHECK-NEXT: [[V6:%.*]] = and i32 [[I0]], 2 ; CHECK-NEXT: [[V4:%.*]] = icmp eq i32 [[V6]], [[J0]] ; CHECK-NEXT: [[V8:%.*]] = add i32 [[SUM0:%.*]], 43 -; CHECK-NEXT: [[SUM2:%.*]] = select i1 [[V4]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2:%.*]] = select i1 [[V4]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF17]] ; CHECK-NEXT: [[V5:%.*]] = icmp eq i32 [[I0]], [[SUM2]] -; CHECK-NEXT: [[SUM3:%.*]] = select i1 [[V5]], i32 [[SUM2]], i32 [[V8]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM3:%.*]] = select i1 [[V5]], i32 [[SUM2]], i32 [[V8]], !prof [[PROF17]] ; CHECK-NEXT: [[V11:%.*]] = add i32 [[I0]], [[SUM3]] ; CHECK-NEXT: ret i32 [[V11]] ; @@ -1498,9 +1491,8 @@ define i32 @test_chr_16(ptr %i) !prof !14 { ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: br i1 [[TMP3]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] @@ -1508,7 +1500,7 @@ define i32 @test_chr_16(ptr %i) !prof !14 { ; CHECK-NEXT: [[V40_NONCHR:%.*]] = add i32 [[DOTFR1]], 44 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP5]], label [[BB3]], label [[BB2_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: [[V41_NONCHR:%.*]] = add i32 [[DOTFR1]], 99 ; CHECK-NEXT: call void @foo() @@ -1578,7 +1570,7 @@ define i32 @test_chr_17(i32 %i, i1 %j) !prof !14 { ; CHECK: bbe: ; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[I]], 1 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0 -; CHECK-NEXT: br i1 [[TMP1]], label [[BB1]], label [[BB0:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP1]], label [[BB1]], label [[BB0:%.*]], !prof [[PROF17]] ; CHECK: bb0: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: [[S:%.*]] = add nuw nsw i32 [[TMP0]], [[I]] @@ -1587,7 +1579,7 @@ define i32 @test_chr_17(i32 %i, i1 %j) !prof !14 { ; CHECK-NEXT: [[P:%.*]] = phi i32 [ [[I]], [[BBQ]] ], [ [[TMP0]], [[BBE]] ], [ [[S]], [[BB0]] ] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[I]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], 0 -; CHECK-NEXT: br i1 [[TMP3]], label [[BB3]], label [[BB2:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP3]], label [[BB3]], label [[BB2:%.*]], !prof [[PROF17]] ; CHECK: bb2: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: [[Q:%.*]] = add i32 [[P]], [[TMP2]] @@ -1682,18 +1674,17 @@ define i32 @test_chr_18(ptr %i, i32 %sum0) !prof !14 { ; CHECK-NEXT: [[A4_NONCHR:%.*]] = and i32 [[LI_FR]], 4 ; CHECK-NEXT: [[CMP4_NONCHR:%.*]] = icmp eq i32 [[A4_NONCHR]], 0 ; CHECK-NEXT: [[INC2_NONCHR:%.*]] = add i32 [[INC1]], 1 -; CHECK-NEXT: br i1 [[CMP4_NONCHR]], label [[BB2]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[CMP4_NONCHR]], label [[BB2]], label [[BB1_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb1.nonchr: -; CHECK-NEXT: [[A1:%.*]] = and i32 [[LI_FR]], 1 -; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i32 [[A1]], 0 -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[CMP1_NOT]], i32 [[SUM0]], i32 [[SUM1]], !prof [[PROF16]] +; CHECK-NEXT: [[CMP1:%.*]] = trunc i32 [[LI_FR]] to i1 +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[CMP1]], i32 [[SUM1]], i32 [[SUM0]], !prof [[PROF16]] ; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], 44 ; CHECK-NEXT: br label [[BB2]] ; CHECK: bb2: ; CHECK-NEXT: [[TMP2]] = phi i32 [ [[INC2]], [[BB1]] ], [ [[INC2_NONCHR]], [[BB0_SPLIT_NONCHR]] ], [ [[INC2_NONCHR]], [[BB1_NONCHR]] ] ; CHECK-NEXT: [[SUM4:%.*]] = phi i32 [ [[SUM3]], [[BB1]] ], [ [[SUM1]], [[BB0_SPLIT_NONCHR]] ], [ [[SUM3_NONCHR]], [[BB1_NONCHR]] ] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP2]], 100 -; CHECK-NEXT: br i1 [[CMP]], label [[BB3:%.*]], label [[BB0]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[CMP]], label [[BB3:%.*]], label [[BB0]], !prof [[PROF17]] ; CHECK: bb3: ; CHECK-NEXT: ret i32 [[SUM4]] ; @@ -1769,17 +1760,17 @@ define i32 @test_chr_19(ptr %i, i32 %sum0) !prof !14 { ; CHECK: entry.split.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 255 ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB3]], label [[BB0_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[DOTFR1]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP5]], 0 ; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[SUM0]], 85 -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM0]], i32 [[TMP7]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM0]], i32 [[TMP7]], !prof [[PROF17]] ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[DOTFR1]], 8 ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 0 -; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP9]], i32 44, i32 88 +; CHECK-NEXT: [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP9]], i32 44, i32 88, !prof [[PROF17]] ; CHECK-NEXT: [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]] -; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM5_NONCHR:%.*]] = select i1 [[TMP6]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof [[PROF17]] ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb3: ; CHECK-NEXT: [[SUM6:%.*]] = phi i32 [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ], [ [[TMP3]], [[BB1]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ] @@ -1868,11 +1859,11 @@ define i32 @test_chr_20(ptr %i, i32 %sum0, i1 %j) !prof !14 { ; CHECK-NEXT: [[V8:%.*]] = add i32 [[SUM0]], 43 ; CHECK-NEXT: [[V3:%.*]] = and i32 [[I0_FR]], 2 ; CHECK-NEXT: [[V4_NOT:%.*]] = icmp eq i32 [[V3]], 0 -; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[V4_NOT]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[V4_NOT]], i32 [[SUM0]], i32 [[V8]], !prof [[PROF17]] ; CHECK-NEXT: [[V6_NONCHR:%.*]] = and i32 [[I0_FR]], 4 ; CHECK-NEXT: [[V5_NONCHR:%.*]] = icmp eq i32 [[V6_NONCHR]], 0 ; CHECK-NEXT: [[V9_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], 44 -; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = select i1 [[V5_NONCHR]], i32 [[SUM2_NONCHR]], i32 [[V9_NONCHR]], !prof [[PROF16]] +; CHECK-NEXT: [[SUM3_NONCHR:%.*]] = select i1 [[V5_NONCHR]], i32 [[SUM2_NONCHR]], i32 [[V9_NONCHR]], !prof [[PROF17]] ; CHECK-NEXT: br i1 [[J]], label [[BB1_NONCHR:%.*]], label [[BB4]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: call void @foo() @@ -1881,7 +1872,7 @@ define i32 @test_chr_20(ptr %i, i32 %sum0, i1 %j) !prof !14 { ; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[V9]], [[BB1]] ], [ [[V9]], [[ENTRY_SPLIT]] ], [ [[SUM3_NONCHR]], [[BB1_NONCHR]] ], [ [[SUM3_NONCHR]], [[ENTRY_SPLIT_NONCHR]] ] ; CHECK-NEXT: [[I5:%.*]] = load i32, ptr [[I]], align 4 ; CHECK-NEXT: [[V12:%.*]] = icmp eq i32 [[I5]], 44 -; CHECK-NEXT: [[V13:%.*]] = select i1 [[V12]], i32 44, i32 [[TMP2]], !prof [[PROF16]] +; CHECK-NEXT: [[V13:%.*]] = select i1 [[V12]], i32 44, i32 [[TMP2]], !prof [[PROF17]] ; CHECK-NEXT: ret i32 [[V13]] ; entry: @@ -1945,7 +1936,7 @@ define i32 @test_chr_21(i64 %i, i64 %k, i64 %j) "instcombine-no-verify-fixpoint" ; CHECK-NEXT: switch i64 [[I_FR]], label [[BB2:%.*]] [ ; CHECK-NEXT: i64 2, label [[BB3_NONCHR2:%.*]] ; CHECK-NEXT: i64 86, label [[BB2_NONCHR1:%.*]] -; CHECK-NEXT: ], !prof [[PROF19:![0-9]+]] +; CHECK-NEXT: ], !prof [[PROF20:![0-9]+]] ; CHECK: bb2: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: call void @foo() @@ -1954,7 +1945,7 @@ define i32 @test_chr_21(i64 %i, i64 %k, i64 %j) "instcombine-no-verify-fixpoint" ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3_NONCHR2]] ; CHECK: bb3.nonchr2: -; CHECK-NEXT: br i1 [[CMP_I]], label [[BB4_NONCHR3:%.*]], label [[BB7]], !prof [[PROF18]] +; CHECK-NEXT: br i1 [[CMP_I]], label [[BB4_NONCHR3:%.*]], label [[BB7]], !prof [[PROF16]] ; CHECK: bb4.nonchr3: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB7]] @@ -1963,18 +1954,18 @@ define i32 @test_chr_21(i64 %i, i64 %k, i64 %j) "instcombine-no-verify-fixpoint" ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB10:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: br i1 [[CMP0]], label [[BB1_NONCHR:%.*]], label [[BB10]], !prof [[PROF18]] +; CHECK-NEXT: br i1 [[CMP0]], label [[BB1_NONCHR:%.*]], label [[BB10]], !prof [[PROF16]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[CMP2_NONCHR:%.*]] = icmp eq i64 [[I_FR]], 2 -; CHECK-NEXT: br i1 [[CMP2_NONCHR]], label [[BB3_NONCHR:%.*]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[CMP2_NONCHR]], label [[BB3_NONCHR:%.*]], label [[BB2_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb3.nonchr: ; CHECK-NEXT: [[CMP_I_NONCHR:%.*]] = icmp eq i64 [[I_FR]], 86 -; CHECK-NEXT: br i1 [[CMP_I_NONCHR]], label [[BB6_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[CMP_I_NONCHR]], label [[BB6_NONCHR:%.*]], label [[BB4_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb6.nonchr: ; CHECK-NEXT: [[CMP3_NONCHR:%.*]] = icmp eq i64 [[J]], [[I_FR]] -; CHECK-NEXT: br i1 [[CMP3_NONCHR]], label [[BB8_NONCHR:%.*]], label [[BB7_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[CMP3_NONCHR]], label [[BB8_NONCHR:%.*]], label [[BB7_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb8.nonchr: -; CHECK-NEXT: br i1 [[CMP_I_NONCHR]], label [[BB10]], label [[BB9_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[CMP_I_NONCHR]], label [[BB10]], label [[BB9_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb9.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB10]] @@ -2527,14 +2518,14 @@ define void @test_chr_24(ptr %i) !prof !14 { ; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 -; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF20:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF21:![0-9]+]] ; CHECK: bb0: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1]] ; CHECK: bb1: ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 2 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[TMP4]], label [[BB3:%.*]], label [[BB2:%.*]], !prof [[PROF20]] +; CHECK-NEXT: br i1 [[TMP4]], label [[BB3:%.*]], label [[BB2:%.*]], !prof [[PROF21]] ; CHECK: bb2: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB3]] @@ -2572,14 +2563,14 @@ define void @test_chr_with_bbs_address_taken1(ptr %i) !prof !14 { ; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 -; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP2]], label [[BB1:%.*]], label [[BB0:%.*]], !prof [[PROF17]] ; CHECK: bb0: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1]] ; CHECK: bb1: ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP0]], 2 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[TMP4]], label [[BB4:%.*]], label [[BB2:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP4]], label [[BB4:%.*]], label [[BB2:%.*]], !prof [[PROF17]] ; CHECK: bb2: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB4]] @@ -2628,16 +2619,15 @@ define void @test_chr_with_bbs_address_taken2(ptr %i) !prof !14 { ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB6:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: br i1 [[TMP3]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[BB6]], label [[BB2_NONCHR:%.*]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP5]], label [[BB6]], label [[BB2_NONCHR:%.*]], !prof [[PROF17]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB6]] @@ -2700,6 +2690,9 @@ bb6: !16 = !{!"branch_weights", i32 1, i32 1} !17 = !{!"branch_weights", i32 0, i32 0} ; CHECK: !15 = !{!"branch_weights", i32 1000, i32 0} -; CHECK: !16 = !{!"branch_weights", i32 0, i32 1} -; CHECK: !17 = !{!"branch_weights", i32 1, i32 1} -; CHECK: !18 = !{!"branch_weights", i32 1, i32 0} +; CHECK: !16 = !{!"branch_weights", i32 1, i32 0} +; CHECK: !17 = !{!"branch_weights", i32 0, i32 1} +; CHECK: !18 = !{!"branch_weights", i32 1, i32 1} +; CHECK: !19 = !{!"unknown", !"instcombine"} +; CHECK: !20 = !{!"branch_weights", i32 1000, i32 0, i32 0} +; CHECK: !21 = !{!"branch_weights", i32 0, i32 0} diff --git a/llvm/test/Transforms/PGOProfile/chr_coro.ll b/llvm/test/Transforms/PGOProfile/chr_coro.ll index 12654eccd5689..501713da17491 100644 --- a/llvm/test/Transforms/PGOProfile/chr_coro.ll +++ b/llvm/test/Transforms/PGOProfile/chr_coro.ll @@ -13,20 +13,32 @@ declare noalias ptr @malloc(i32) ; resume part of the coroutine define fastcc void @f.resume(ptr noalias nonnull align 8 dereferenceable(24) %FramePtr) { - tail call void @bar() - ret void +; CHECK-LABEL: @f.resume( +; CHECK-NEXT: tail call void @bar() +; CHECK-NEXT: ret void +; + tail call void @bar() + ret void } ; destroy part of the coroutine define fastcc void @f.destroy(ptr noalias nonnull align 8 dereferenceable(24) %FramePtr) { - tail call void @bar() - ret void +; CHECK-LABEL: @f.destroy( +; CHECK-NEXT: tail call void @bar() +; CHECK-NEXT: ret void +; + tail call void @bar() + ret void } ; cleanup part of the coroutine define fastcc void @f.cleanup(ptr noalias nonnull align 8 dereferenceable(24) %FramePtr) { - tail call void @bar() - ret void +; CHECK-LABEL: @f.cleanup( +; CHECK-NEXT: tail call void @bar() +; CHECK-NEXT: ret void +; + tail call void @bar() + ret void } @f.resumers = private constant [3 x ptr] [ptr @f.resume, ptr @f.destroy, ptr @f.cleanup] @@ -44,16 +56,15 @@ define ptr @test_chr_with_coro_id(ptr %i) !prof !14 { ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB_CORO_ID:%.*]] ; CHECK: entry.split.nonchr: -; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[DOTFR1]], 1 -; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP3]], 0 -; CHECK-NEXT: br i1 [[DOTNOT]], label [[BB1_NONCHR:%.*]], label [[BB0_NONCHR:%.*]], !prof [[PROF16:![0-9]+]] +; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[DOTFR1]] to i1 +; CHECK-NEXT: br i1 [[TMP3]], label [[BB0_NONCHR:%.*]], label [[BB1_NONCHR:%.*]], !prof [[PROF16:![0-9]+]] ; CHECK: bb0.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB1_NONCHR]] ; CHECK: bb1.nonchr: ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[DOTFR1]], 2 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0 -; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB_CORO_ID]], !prof [[PROF16]] +; CHECK-NEXT: br i1 [[TMP5]], label [[BB2_NONCHR:%.*]], label [[BB_CORO_ID]], !prof [[PROF17:![0-9]+]] ; CHECK: bb2.nonchr: ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[BB_CORO_ID]] @@ -124,4 +135,5 @@ bb.coro.begin: !16 = !{!"branch_weights", i32 1, i32 1} !17 = !{!"branch_weights", i32 0, i32 0} ; CHECK: !15 = !{!"branch_weights", i32 1000, i32 0} -; CHECK: !16 = !{!"branch_weights", i32 0, i32 1} +; CHECK: !16 = !{!"branch_weights", i32 1, i32 0} +; CHECK: !17 = !{!"branch_weights", i32 0, i32 1} diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll index 57dacd455482e..5e1066ee626fa 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll @@ -41,7 +41,7 @@ define void @partial_unroll_forced(i32 %N, ptr %src, ptr noalias %dst) { ; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL_PREHEADER]] ; CHECK: loop.latch.epil.preheader: ; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[EXIT_LOOPEXIT_UNR_LCSSA]] ] -; CHECK-NEXT: [[LCMP_MOD4:%.*]] = icmp ne i64 [[XTRAITER]], 0 +; CHECK-NEXT: [[LCMP_MOD4:%.*]] = trunc i32 [[N]] to i1 ; CHECK-NEXT: tail call void @llvm.assume(i1 [[LCMP_MOD4]]) ; CHECK-NEXT: [[SRC_IDX_EPIL:%.*]] = getelementptr <8 x half>, ptr [[SRC]], i64 [[INDVARS_IV_UNR]] ; CHECK-NEXT: [[L_EPIL:%.*]] = load <8 x half>, ptr [[SRC_IDX_EPIL]], align 16 @@ -115,7 +115,7 @@ define void @cse_matching_load_from_previous_unrolled_iteration(i32 %N, ptr %src ; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL_PREHEADER]] ; CHECK: loop.latch.epil.preheader: ; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[EXIT_LOOPEXIT_UNR_LCSSA]] ] -; CHECK-NEXT: [[LCMP_MOD4:%.*]] = icmp ne i64 [[XTRAITER]], 0 +; CHECK-NEXT: [[LCMP_MOD4:%.*]] = trunc i32 [[N]] to i1 ; CHECK-NEXT: tail call void @llvm.assume(i1 [[LCMP_MOD4]]) ; CHECK-NEXT: [[GEP_SRC_12_EPIL:%.*]] = getelementptr <2 x i32>, ptr [[SRC_12]], i64 [[INDVARS_IV_UNR]] ; CHECK-NEXT: [[L_12_EPIL:%.*]] = load <2 x i32>, ptr [[GEP_SRC_12_EPIL]], align 8 diff --git a/llvm/test/Transforms/PhaseOrdering/X86/loadcombine.ll b/llvm/test/Transforms/PhaseOrdering/X86/loadcombine.ll index fe49ba9d61d98..ab15f8663ffcd 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/loadcombine.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/loadcombine.ll @@ -70,23 +70,7 @@ define i32 @loadCombine_4consecutive_1243(ptr %p) { define i32 @loadCombine_4consecutive_1324(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_1324( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -114,23 +98,7 @@ define i32 @loadCombine_4consecutive_1324(ptr %p) { define i32 @loadCombine_4consecutive_1342(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_1342( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -158,23 +126,7 @@ define i32 @loadCombine_4consecutive_1342(ptr %p) { define i32 @loadCombine_4consecutive_1423(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_1423( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -202,23 +154,7 @@ define i32 @loadCombine_4consecutive_1423(ptr %p) { define i32 @loadCombine_4consecutive_1432(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_1432( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -369,23 +305,7 @@ define i32 @loadCombine_4consecutive_2341(ptr %p) { define i32 @loadCombine_4consecutive_2413(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_2413( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -413,23 +333,7 @@ define i32 @loadCombine_4consecutive_2413(ptr %p) { define i32 @loadCombine_4consecutive_2431(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_2431( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -457,23 +361,7 @@ define i32 @loadCombine_4consecutive_2431(ptr %p) { define i32 @loadCombine_4consecutive_3124(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_3124( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -501,23 +389,7 @@ define i32 @loadCombine_4consecutive_3124(ptr %p) { define i32 @loadCombine_4consecutive_3142(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_3142( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -668,23 +540,7 @@ define i32 @loadCombine_4consecutive_3421(ptr %p) { define i32 @loadCombine_4consecutive_4123(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_4123( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -712,23 +568,7 @@ define i32 @loadCombine_4consecutive_4123(ptr %p) { define i32 @loadCombine_4consecutive_4132(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_4132( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -756,23 +596,7 @@ define i32 @loadCombine_4consecutive_4132(ptr %p) { define i32 @loadCombine_4consecutive_4213(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_4213( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 @@ -800,23 +624,7 @@ define i32 @loadCombine_4consecutive_4213(ptr %p) { define i32 @loadCombine_4consecutive_4231(ptr %p) { ; CHECK-LABEL: @loadCombine_4consecutive_4231( -; CHECK-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i64 1 -; CHECK-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i64 3 -; CHECK-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1 -; CHECK-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1 -; CHECK-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1 -; CHECK-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32 -; CHECK-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32 -; CHECK-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32 -; CHECK-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i32 [[E2]], 8 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i32 [[E3]], 16 -; CHECK-NEXT: [[S4:%.*]] = shl nuw i32 [[E4]], 24 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i32 [[S2]], [[E1]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i32 [[O1]], [[S3]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i32 [[O2]], [[S4]] +; CHECK-NEXT: [[O3:%.*]] = load i32, ptr [[P:%.*]], align 1 ; CHECK-NEXT: ret i32 [[O3]] ; %p1 = getelementptr i8, ptr %p, i32 1 diff --git a/llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll b/llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll index ac9ab8934049a..61380d5a78c90 100644 --- a/llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll +++ b/llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll @@ -1,35 +1,40 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 ; RUN: opt -passes='loop(loop-rotate),instcombine' -enable-knowledge-retention -S < %s | FileCheck %s %0 = type { ptr } -define ptr @f1(ptr %i0) local_unnamed_addr { -; CHECK-LABEL: @f1( -; CHECK-NEXT: bb: -; CHECK: br label [[BB3:%.*]] -; CHECK: bb3: -; CHECK-NEXT: [[I1:%.*]] = phi ptr [ %i0, [[BB:%.*]] ], [ [[I5:%.*]], [[BB3]] ] -; CHECK-NEXT: call void @llvm.assume(i1 true) [ "nonnull"(ptr [[I1]]) ] -; CHECK-NEXT: [[I5]] = load ptr, ptr [[I1]], align 8 +define ptr @f1(ptr %i0) { +; CHECK-LABEL: define ptr @f1( +; CHECK-SAME: ptr [[I0:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[I21:%.*]] = icmp eq ptr [[I0]], null +; CHECK-NEXT: br i1 [[I21]], label %[[EXIT:.*]], label %[[LOOP_LATCH_LR_PH:.*]] +; CHECK: [[LOOP_LATCH_LR_PH]]: +; CHECK-NEXT: br label %[[LOOP_LATCH:.*]] +; CHECK: [[LOOP_LATCH]]: +; CHECK-NEXT: [[I3:%.*]] = phi ptr [ [[I0]], %[[LOOP_LATCH_LR_PH]] ], [ [[I5:%.*]], %[[LOOP_LATCH]] ] +; CHECK-NEXT: [[I5]] = load ptr, ptr [[I3]], align 8 ; CHECK-NEXT: [[I2:%.*]] = icmp eq ptr [[I5]], null -; CHECK-NEXT: br i1 [[I2]], label [[BB6:%.*]], label [[BB3]] -; CHECK: bb6: +; CHECK-NEXT: br i1 [[I2]], label %[[LOOP_EXIT_CRIT_EDGE:.*]], label %[[LOOP_LATCH]] +; CHECK: [[LOOP_EXIT_CRIT_EDGE]]: +; CHECK-NEXT: br label %[[EXIT]] +; CHECK: [[EXIT]]: ; CHECK-NEXT: ret ptr undef ; -bb: - br label %bb1 +entry: + br label %loop -bb1: - %i = phi ptr [ %i0, %bb ], [ %i5, %bb3 ] +loop: + %i = phi ptr [ %i0, %entry ], [ %i5, %loop.latch ] %i2 = icmp eq ptr %i, null - br i1 %i2, label %bb6, label %bb3 + br i1 %i2, label %exit, label %loop.latch -bb3: +loop.latch: call void @llvm.assume(i1 true) [ "nonnull"(ptr %i) ] %i5 = load ptr, ptr %i, align 8 - br label %bb1 + br label %loop -bb6: +exit: ret ptr undef } diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll index 0da7b1494ef9f..3d2a86f50027b 100644 --- a/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll +++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AMDGPU/expand-mem-intrinsics.ll @@ -222,16 +222,32 @@ define protected amdgpu_kernel void @memmove_2048_bytes(ptr addrspace(1) %dst, p define protected amdgpu_kernel void @memset(ptr addrspace(1) %dst, i8 %value, i64 noundef %n) { ; CHECK-LABEL: define protected amdgpu_kernel void @memset( ; CHECK-SAME: ptr addrspace(1) [[DST:%.*]], i8 [[VALUE:%.*]], i64 noundef [[N:%.*]]) !dbg [[DBG38:![0-9]+]] { -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 0, [[N]], !dbg [[DBG41:![0-9]+]] -; CHECK-NEXT: br i1 [[TMP1]], label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]], !dbg [[DBG41]] +; CHECK-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[VALUE]], i64 0, !dbg [[DBG41:![0-9]+]] +; CHECK-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <16 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer, !dbg [[DBG41]] +; CHECK-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <16 x i8> [[SETVALUE_SPLAT_SPLAT]] to <4 x i32>, !dbg [[DBG41]] +; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[N]], 15, !dbg [[DBG41]] +; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[N]], [[TMP1]], !dbg [[DBG41]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP2]], 0, !dbg [[DBG41]] +; CHECK-NEXT: br i1 [[TMP3]], label %[[LOADSTORELOOP:.*]], label %[[SPLIT:.*]], !dbg [[DBG41]] ; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP4:%.*]], %[[LOADSTORELOOP]] ], !dbg [[DBG41]] -; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 [[TMP2]], !dbg [[DBG41]] -; CHECK-NEXT: store i8 [[VALUE]], ptr addrspace(1) [[TMP3]], align 1, !dbg [[DBG41]] -; CHECK-NEXT: [[TMP4]] = add i64 [[TMP2]], 1, !dbg [[DBG41]] -; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i64 [[TMP4]], [[N]], !dbg [[DBG41]] -; CHECK-NEXT: br i1 [[TMP5]], label %[[LOADSTORELOOP]], label %[[SPLIT]], !dbg [[DBG41]] +; CHECK-NEXT: [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP5:%.*]], %[[LOADSTORELOOP]] ], !dbg [[DBG41]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 [[LOOP_INDEX]], !dbg [[DBG41]] +; CHECK-NEXT: store <4 x i32> [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP4]], align 1, !dbg [[DBG41]] +; CHECK-NEXT: [[TMP5]] = add i64 [[LOOP_INDEX]], 16, !dbg [[DBG41]] +; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i64 [[TMP5]], [[TMP2]], !dbg [[DBG41]] +; CHECK-NEXT: br i1 [[TMP6]], label %[[LOADSTORELOOP]], label %[[SPLIT]], !dbg [[DBG41]] ; CHECK: [[SPLIT]]: +; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP1]], 0, !dbg [[DBG41]] +; CHECK-NEXT: br i1 [[TMP7]], label %[[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_BODY:.*]], label %[[DYNAMIC_MEMSET_POST_EXPANSION:.*]], !dbg [[DBG41]] +; CHECK: [[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_BODY]]: +; CHECK-NEXT: [[RESIDUAL_LOOP_INDEX:%.*]] = phi i64 [ 0, %[[SPLIT]] ], [ [[TMP10:%.*]], %[[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_BODY]] ], !dbg [[DBG41]] +; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP2]], [[RESIDUAL_LOOP_INDEX]], !dbg [[DBG41]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 [[TMP8]], !dbg [[DBG41]] +; CHECK-NEXT: store i8 [[VALUE]], ptr addrspace(1) [[TMP9]], align 1, !dbg [[DBG41]] +; CHECK-NEXT: [[TMP10]] = add i64 [[RESIDUAL_LOOP_INDEX]], 1, !dbg [[DBG41]] +; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i64 [[TMP10]], [[TMP1]], !dbg [[DBG41]] +; CHECK-NEXT: br i1 [[TMP11]], label %[[DYNAMIC_MEMSET_EXPANSION_RESIDUAL_BODY]], label %[[DYNAMIC_MEMSET_POST_EXPANSION]], !dbg [[DBG41]] +; CHECK: [[DYNAMIC_MEMSET_POST_EXPANSION]]: ; CHECK-NEXT: #dbg_value(i32 0, [[META40:![0-9]+]], !DIExpression(), [[META42:![0-9]+]]) ; CHECK-NEXT: ret void, !dbg [[META42]] ; @@ -242,15 +258,20 @@ define protected amdgpu_kernel void @memset(ptr addrspace(1) %dst, i8 %value, i6 define protected amdgpu_kernel void @memset_1025_bytes(ptr addrspace(1) %dst, i8 %value) { ; CHECK-LABEL: define protected amdgpu_kernel void @memset_1025_bytes( ; CHECK-SAME: ptr addrspace(1) [[DST:%.*]], i8 [[VALUE:%.*]]) !dbg [[DBG43:![0-9]+]] { -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]], !dbg [[DBG46:![0-9]+]] +; CHECK-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <256 x i8> poison, i8 [[VALUE]], i64 0, !dbg [[DBG46:![0-9]+]] +; CHECK-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <256 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <256 x i8> poison, <256 x i32> zeroinitializer, !dbg [[DBG46]] +; CHECK-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <256 x i8> [[SETVALUE_SPLAT_SPLAT]] to <64 x i32>, !dbg [[DBG46]] +; CHECK-NEXT: br label %[[LOADSTORELOOP:.*]], !dbg [[DBG46]] ; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ], !dbg [[DBG46]] -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 [[TMP1]], !dbg [[DBG46]] -; CHECK-NEXT: store i8 [[VALUE]], ptr addrspace(1) [[TMP2]], align 1, !dbg [[DBG46]] -; CHECK-NEXT: [[TMP3]] = add i64 [[TMP1]], 1, !dbg [[DBG46]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 1025, !dbg [[DBG46]] -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]], !dbg [[DBG46]] +; CHECK-NEXT: [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP2:%.*]], %[[LOADSTORELOOP]] ], !dbg [[DBG46]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 [[LOOP_INDEX]], !dbg [[DBG46]] +; CHECK-NEXT: store <64 x i32> [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP1]], align 1, !dbg [[DBG46]] +; CHECK-NEXT: [[TMP2]] = add i64 [[LOOP_INDEX]], 256, !dbg [[DBG46]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 1024, !dbg [[DBG46]] +; CHECK-NEXT: br i1 [[TMP3]], label %[[LOADSTORELOOP]], label %[[SPLIT:.*]], !dbg [[DBG46]] ; CHECK: [[SPLIT]]: +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 1024, !dbg [[DBG46]] +; CHECK-NEXT: store i8 [[VALUE]], ptr addrspace(1) [[TMP4]], align 1, !dbg [[DBG46]] ; CHECK-NEXT: #dbg_value(i32 0, [[META45:![0-9]+]], !DIExpression(), [[META47:![0-9]+]]) ; CHECK-NEXT: ret void, !dbg [[META47]] ; @@ -261,14 +282,17 @@ define protected amdgpu_kernel void @memset_1025_bytes(ptr addrspace(1) %dst, i8 define protected amdgpu_kernel void @memset_2048_bytes(ptr addrspace(1) %dst, i8 %value) { ; CHECK-LABEL: define protected amdgpu_kernel void @memset_2048_bytes( ; CHECK-SAME: ptr addrspace(1) [[DST:%.*]], i8 [[VALUE:%.*]]) !dbg [[DBG48:![0-9]+]] { -; CHECK-NEXT: br i1 false, label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]], !dbg [[DBG51:![0-9]+]] +; CHECK-NEXT: [[SETVALUE_SPLAT_SPLATINSERT:%.*]] = insertelement <256 x i8> poison, i8 [[VALUE]], i64 0, !dbg [[DBG51:![0-9]+]] +; CHECK-NEXT: [[SETVALUE_SPLAT_SPLAT:%.*]] = shufflevector <256 x i8> [[SETVALUE_SPLAT_SPLATINSERT]], <256 x i8> poison, <256 x i32> zeroinitializer, !dbg [[DBG51]] +; CHECK-NEXT: [[SETVALUE_SPLAT_CAST:%.*]] = bitcast <256 x i8> [[SETVALUE_SPLAT_SPLAT]] to <64 x i32>, !dbg [[DBG51]] +; CHECK-NEXT: br label %[[LOADSTORELOOP:.*]], !dbg [[DBG51]] ; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP3:%.*]], %[[LOADSTORELOOP]] ], !dbg [[DBG51]] -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 [[TMP1]], !dbg [[DBG51]] -; CHECK-NEXT: store i8 [[VALUE]], ptr addrspace(1) [[TMP2]], align 1, !dbg [[DBG51]] -; CHECK-NEXT: [[TMP3]] = add i64 [[TMP1]], 1, !dbg [[DBG51]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP3]], 2048, !dbg [[DBG51]] -; CHECK-NEXT: br i1 [[TMP4]], label %[[LOADSTORELOOP]], label %[[SPLIT]], !dbg [[DBG51]] +; CHECK-NEXT: [[LOOP_INDEX:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP2:%.*]], %[[LOADSTORELOOP]] ], !dbg [[DBG51]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[DST]], i64 [[LOOP_INDEX]], !dbg [[DBG51]] +; CHECK-NEXT: store <64 x i32> [[SETVALUE_SPLAT_CAST]], ptr addrspace(1) [[TMP1]], align 1, !dbg [[DBG51]] +; CHECK-NEXT: [[TMP2]] = add i64 [[LOOP_INDEX]], 256, !dbg [[DBG51]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP2]], 2048, !dbg [[DBG51]] +; CHECK-NEXT: br i1 [[TMP3]], label %[[LOADSTORELOOP]], label %[[SPLIT:.*]], !dbg [[DBG51]] ; CHECK: [[SPLIT]]: ; CHECK-NEXT: #dbg_value(i32 0, [[META50:![0-9]+]], !DIExpression(), [[META52:![0-9]+]]) ; CHECK-NEXT: ret void, !dbg [[META52]] diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-inline-non-constant-len.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-inline-non-constant-len.ll index b376e27fdaf1c..ff9f662aaee9a 100644 --- a/llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-inline-non-constant-len.ll +++ b/llvm/test/Transforms/PreISelIntrinsicLowering/X86/memset-inline-non-constant-len.ll @@ -17,26 +17,26 @@ define void @memset_32(ptr %a, i8 %value) nounwind { define void @memset_x(ptr %a, i8 %value, i64 %x) nounwind !prof !0 { ; CHECK-LABEL: define void @memset_x( ; CHECK-SAME: ptr [[A:%.*]], i8 [[VALUE:%.*]], i64 [[X:%.*]]) #[[ATTR0]] !prof [[PROF0:![0-9]+]] { -; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 0, [[X]] -; CHECK-NEXT: br i1 [[TMP1]], label %[[SPLIT:.*]], label %[[LOADSTORELOOP:.*]], !prof [[PROF1:![0-9]+]] -; CHECK: [[LOADSTORELOOP]]: -; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP4:%.*]], %[[LOADSTORELOOP]] ] +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[X]], 0 +; CHECK-NEXT: br i1 [[TMP1]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY:.*]], label %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION:.*]], !prof [[PROF1:![0-9]+]] +; CHECK: [[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]]: +; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP4:%.*]], %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]] ] ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP2]] ; CHECK-NEXT: store i8 [[VALUE]], ptr [[TMP3]], align 1 ; CHECK-NEXT: [[TMP4]] = add i64 [[TMP2]], 1 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i64 [[TMP4]], [[X]] -; CHECK-NEXT: br i1 [[TMP5]], label %[[LOADSTORELOOP]], label %[[SPLIT]], !prof [[PROF2:![0-9]+]] -; CHECK: [[SPLIT]]: -; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 0, [[X]] -; CHECK-NEXT: br i1 [[TMP6]], label %[[SPLIT1:.*]], label %[[LOADSTORELOOP2:.*]], !prof [[PROF3:![0-9]+]] -; CHECK: [[LOADSTORELOOP2]]: -; CHECK-NEXT: [[TMP7:%.*]] = phi i64 [ 0, %[[SPLIT]] ], [ [[TMP9:%.*]], %[[LOADSTORELOOP2]] ] +; CHECK-NEXT: br i1 [[TMP5]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY]], label %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION]], !prof [[PROF2:![0-9]+]] +; CHECK: [[DYNAMIC_MEMSET_POST_LOOP_EXPANSION]]: +; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[X]], 0 +; CHECK-NEXT: br i1 [[TMP6]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY2:.*]], label %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION1:.*]], !prof [[PROF1]] +; CHECK: [[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY2]]: +; CHECK-NEXT: [[TMP7:%.*]] = phi i64 [ 0, %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION]] ], [ [[TMP9:%.*]], %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY2]] ] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[TMP7]] ; CHECK-NEXT: store volatile i8 [[VALUE]], ptr [[TMP8]], align 1 ; CHECK-NEXT: [[TMP9]] = add i64 [[TMP7]], 1 ; CHECK-NEXT: [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[X]] -; CHECK-NEXT: br i1 [[TMP10]], label %[[LOADSTORELOOP2]], label %[[SPLIT1]], !prof [[PROF3]] -; CHECK: [[SPLIT1]]: +; CHECK-NEXT: br i1 [[TMP10]], label %[[DYNAMIC_MEMSET_LOOP_EXPANSION_MAIN_BODY2]], label %[[DYNAMIC_MEMSET_POST_LOOP_EXPANSION1]], !prof [[PROF3:![0-9]+]] +; CHECK: [[DYNAMIC_MEMSET_POST_LOOP_EXPANSION1]]: ; CHECK-NEXT: ret void ; call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 %x, i1 0), !prof !1 diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/cond-loop.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/cond-loop.ll new file mode 100644 index 0000000000000..6d7fdd2a9f38e --- /dev/null +++ b/llvm/test/Transforms/PreISelIntrinsicLowering/cond-loop.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; REQUIRES: x86-registered-target, mips-registered-target +; RUN: opt -mtriple=x86_64 -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck --check-prefix=X86 %s +; RUN: opt -mtriple=mips64 -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck --check-prefix=MIPS %s + +define void @f1(i64 %a, i64 %b) !prof !0 { +; X86-LABEL: define void @f1( +; X86-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) !prof [[PROF0:![0-9]+]] { +; X86-NEXT: [[CMP:%.*]] = icmp ult i64 [[A]], [[B]] +; X86-NEXT: call void @llvm.cond.loop(i1 [[CMP]]) +; X86-NEXT: ret void +; +; MIPS-LABEL: define void @f1( +; MIPS-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) !prof [[PROF0:![0-9]+]] { +; MIPS-NEXT: [[CMP:%.*]] = icmp ult i64 [[A]], [[B]] +; MIPS-NEXT: br i1 [[CMP]], label %[[BB1:.*]], label %[[BB2:.*]], !prof [[PROF1:![0-9]+]] +; MIPS: [[BB1]]: +; MIPS-NEXT: br label %[[BB1]] +; MIPS: [[BB2]]: +; MIPS-NEXT: ret void +; + %cmp = icmp ult i64 %a, %b + call void @llvm.cond.loop(i1 %cmp) + ret void +} + +!0 = !{!"function_entry_count", i64 1000} +;. +; X86: [[PROF0]] = !{!"function_entry_count", i64 1000} +;. +; MIPS: [[PROF0]] = !{!"function_entry_count", i64 1000} +; MIPS: [[PROF1]] = !{!"unknown", !"pre-isel-intrinsic-lowering"} +;. diff --git a/llvm/test/Transforms/SCCP/assume-operand-bundles.ll b/llvm/test/Transforms/SCCP/assume-operand-bundles.ll index 6f86fc331422d..7485b9e289393 100644 --- a/llvm/test/Transforms/SCCP/assume-operand-bundles.ll +++ b/llvm/test/Transforms/SCCP/assume-operand-bundles.ll @@ -124,5 +124,13 @@ false1: %cf4 = icmp ne ptr null, %v call void @use(i1 %cf4) ret void +} + +define void @check_for_constant() { +; CHECK-LABEL: define void @check_for_constant() { +; CHECK-NEXT: call void @llvm.assume(i1 true) [ "nonnull"(ptr null) ] +; CHECK-NEXT: ret void +; + call void @llvm.assume(i1 true) [ "nonnull"(ptr null) ] ret void } diff --git a/llvm/test/Transforms/SCCP/float-denormal-simplification.ll b/llvm/test/Transforms/SCCP/float-denormal-simplification.ll index fec9883aabddd..b99c4025490ac 100644 --- a/llvm/test/Transforms/SCCP/float-denormal-simplification.ll +++ b/llvm/test/Transforms/SCCP/float-denormal-simplification.ll @@ -17,5 +17,5 @@ define float @test_preserve_sign() #1 { ret float %1 } -attributes #0 = {"denormal-fp-math"="ieee,ieee"} -attributes #1 = {"denormal-fp-math"="preserve-sign,preserve-sign"} +attributes #0 = {denormal_fpenv(ieee|ieee)} +attributes #1 = {denormal_fpenv(preservesign)} diff --git a/llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll b/llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll index 285122d104c7e..78609ec8b0e51 100644 --- a/llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll +++ b/llvm/test/Transforms/SCCP/no-fold-fcmp-dynamic-denormal-mode-issue114947.ll @@ -116,4 +116,4 @@ define @no_fold_fcmp_denormal_double_ieee_dynamic_scalable_vec ret %cmp } -attributes #0 = { "denormal-fp-math"="ieee,dynamic" } +attributes #0 = { denormal_fpenv(ieee|dynamic) } diff --git a/llvm/test/Transforms/SLPVectorizer/PowerPC/disjoint-or-reductions.ll b/llvm/test/Transforms/SLPVectorizer/PowerPC/disjoint-or-reductions.ll new file mode 100644 index 0000000000000..3b6b54d10281c --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/PowerPC/disjoint-or-reductions.ll @@ -0,0 +1,261 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=powerpc64-linux-gnu -mcpu=pwr9 -mattr=+vsx | FileCheck %s + +define i64 @bswap(ptr noalias %p, ptr noalias %p1) { +; CHECK-LABEL: @bswap( +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[P:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[P1:%.*]], align 1 +; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i8> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i8> [[TMP3]] to <8 x i64> +; CHECK-NEXT: [[TMP5:%.*]] = shl nuw <8 x i64> [[TMP4]], +; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP5]]) +; CHECK-NEXT: ret i64 [[TMP6]] +; + %g1 = getelementptr i8, ptr %p, i32 1 + %g2 = getelementptr i8, ptr %p, i32 2 + %g3 = getelementptr i8, ptr %p, i32 3 + %g4 = getelementptr i8, ptr %p, i32 4 + %g5 = getelementptr i8, ptr %p, i32 5 + %g6 = getelementptr i8, ptr %p, i32 6 + %g7 = getelementptr i8, ptr %p, i32 7 + + %t0 = load i8, ptr %p + %t1 = load i8, ptr %g1 + %t2 = load i8, ptr %g2 + %t3 = load i8, ptr %g3 + %t4 = load i8, ptr %g4 + %t5 = load i8, ptr %g5 + %t6 = load i8, ptr %g6 + %t7 = load i8, ptr %g7 + + %g11 = getelementptr i8, ptr %p1, i32 1 + %g12 = getelementptr i8, ptr %p1, i32 2 + %g13 = getelementptr i8, ptr %p1, i32 3 + %g14 = getelementptr i8, ptr %p1, i32 4 + %g15 = getelementptr i8, ptr %p1, i32 5 + %g16 = getelementptr i8, ptr %p1, i32 6 + %g17 = getelementptr i8, ptr %p1, i32 7 + + %t10 = load i8, ptr %p1 + %t11 = load i8, ptr %g11 + %t12 = load i8, ptr %g12 + %t13 = load i8, ptr %g13 + %t14 = load i8, ptr %g14 + %t15 = load i8, ptr %g15 + %t16 = load i8, ptr %g16 + %t17 = load i8, ptr %g17 + + %a0 = add i8 %t0, %t10 + %a1 = add i8 %t1, %t11 + %a2 = add i8 %t2, %t12 + %a3 = add i8 %t3, %t13 + %a4 = add i8 %t4, %t14 + %a5 = add i8 %t5, %t15 + %a6 = add i8 %t6, %t16 + %a7 = add i8 %t7, %t17 + + %z0 = zext i8 %a0 to i64 + %z1 = zext i8 %a1 to i64 + %z2 = zext i8 %a2 to i64 + %z3 = zext i8 %a3 to i64 + %z4 = zext i8 %a4 to i64 + %z5 = zext i8 %a5 to i64 + %z6 = zext i8 %a6 to i64 + %z7 = zext i8 %a7 to i64 + + %sh0 = shl nuw i64 %z0, 56 + %sh1 = shl nuw nsw i64 %z1, 48 + %sh2 = shl nuw nsw i64 %z2, 40 + %sh3 = shl nuw nsw i64 %z3, 32 + %sh4 = shl nuw nsw i64 %z4, 24 + %sh5 = shl nuw nsw i64 %z5, 16 + %sh6 = shl nuw nsw i64 %z6, 8 +; %sh7 = shl nuw nsw i64 %z7, 0 <-- missing phantom shift + + %or01 = or disjoint i64 %sh0, %sh1 + %or012 = or disjoint i64 %or01, %sh2 + %or0123 = or disjoint i64 %or012, %sh3 + %or01234 = or disjoint i64 %or0123, %sh4 + %or012345 = or disjoint i64 %or01234, %sh5 + %or0123456 = or disjoint i64 %or012345, %sh6 + %or01234567 = or disjoint i64 %or0123456, %z7 + ret i64 %or01234567 +} + +define i64 @reorder(ptr noalias %p, ptr noalias %p1) { +; CHECK-LABEL: @reorder( +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[P:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[P1:%.*]], align 1 +; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i8> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i8> [[TMP3]] to <8 x i64> +; CHECK-NEXT: [[TMP5:%.*]] = shl nuw <8 x i64> [[TMP4]], +; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP5]]) +; CHECK-NEXT: ret i64 [[TMP6]] +; + %g1 = getelementptr i8, ptr %p, i32 1 + %g2 = getelementptr i8, ptr %p, i32 2 + %g3 = getelementptr i8, ptr %p, i32 3 + %g4 = getelementptr i8, ptr %p, i32 4 + %g5 = getelementptr i8, ptr %p, i32 5 + %g6 = getelementptr i8, ptr %p, i32 6 + %g7 = getelementptr i8, ptr %p, i32 7 + + %t0 = load i8, ptr %p + %t1 = load i8, ptr %g1 + %t2 = load i8, ptr %g2 + %t3 = load i8, ptr %g3 + %t4 = load i8, ptr %g4 + %t5 = load i8, ptr %g5 + %t6 = load i8, ptr %g6 + %t7 = load i8, ptr %g7 + + %g11 = getelementptr i8, ptr %p1, i32 1 + %g12 = getelementptr i8, ptr %p1, i32 2 + %g13 = getelementptr i8, ptr %p1, i32 3 + %g14 = getelementptr i8, ptr %p1, i32 4 + %g15 = getelementptr i8, ptr %p1, i32 5 + %g16 = getelementptr i8, ptr %p1, i32 6 + %g17 = getelementptr i8, ptr %p1, i32 7 + + %t10 = load i8, ptr %p1 + %t11 = load i8, ptr %g11 + %t12 = load i8, ptr %g12 + %t13 = load i8, ptr %g13 + %t14 = load i8, ptr %g14 + %t15 = load i8, ptr %g15 + %t16 = load i8, ptr %g16 + %t17 = load i8, ptr %g17 + + %a0 = add i8 %t0, %t10 + %a1 = add i8 %t1, %t11 + %a2 = add i8 %t2, %t12 + %a3 = add i8 %t3, %t13 + %a4 = add i8 %t4, %t14 + %a5 = add i8 %t5, %t15 + %a6 = add i8 %t6, %t16 + %a7 = add i8 %t7, %t17 + + %z0 = zext i8 %a0 to i64 + %z1 = zext i8 %a1 to i64 + %z2 = zext i8 %a2 to i64 + %z3 = zext i8 %a3 to i64 + %z4 = zext i8 %a4 to i64 + %z5 = zext i8 %a5 to i64 + %z6 = zext i8 %a6 to i64 + %z7 = zext i8 %a7 to i64 + + %sh0 = shl nuw i64 %z0, 56 + %sh1 = shl nuw nsw i64 %z1, 16 + %sh2 = shl nuw nsw i64 %z2, 40 + %sh3 = shl nuw nsw i64 %z3, 32 + %sh4 = shl nuw nsw i64 %z4, 24 + %sh5 = shl nuw nsw i64 %z5, 48 + %sh6 = shl nuw nsw i64 %z6, 8 +; %sh7 = shl nuw nsw i64 %z7, 0 <-- missing phantom shift + + %or01 = or disjoint i64 %sh0, %sh1 + %or012 = or disjoint i64 %or01, %sh2 + %or0123 = or disjoint i64 %or012, %sh3 + %or01234 = or disjoint i64 %or0123, %sh4 + %or012345 = or disjoint i64 %or01234, %sh5 + %or0123456 = or disjoint i64 %or012345, %sh6 + %or01234567 = or disjoint i64 %or0123456, %z7 + ret i64 %or01234567 +} + +define i64 @swap_i16(ptr noalias %p, ptr noalias %p1) { +; CHECK-LABEL: @swap_i16( +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[P:%.*]], align 2 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[P1:%.*]], align 2 +; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i16> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i16> [[TMP3]] to <4 x i64> +; CHECK-NEXT: [[TMP5:%.*]] = shl nuw <4 x i64> [[TMP4]], +; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> [[TMP5]]) +; CHECK-NEXT: ret i64 [[TMP6]] +; + %g1 = getelementptr i16, ptr %p, i32 1 + %g2 = getelementptr i16, ptr %p, i32 2 + %g3 = getelementptr i16, ptr %p, i32 3 + + %t0 = load i16, ptr %p + %t1 = load i16, ptr %g1 + %t2 = load i16, ptr %g2 + %t3 = load i16, ptr %g3 + + %g11 = getelementptr i16, ptr %p1, i32 1 + %g12 = getelementptr i16, ptr %p1, i32 2 + %g13 = getelementptr i16, ptr %p1, i32 3 + + %t10 = load i16, ptr %p1 + %t11 = load i16, ptr %g11 + %t12 = load i16, ptr %g12 + %t13 = load i16, ptr %g13 + + %a0 = add i16 %t0, %t10 + %a1 = add i16 %t1, %t11 + %a2 = add i16 %t2, %t12 + %a3 = add i16 %t3, %t13 + + %z0 = zext i16 %a0 to i64 + %z1 = zext i16 %a1 to i64 + %z2 = zext i16 %a2 to i64 + %z3 = zext i16 %a3 to i64 + + %sh0 = shl nuw i64 %z0, 48 + %sh1 = shl nuw nsw i64 %z1, 32 + %sh2 = shl nuw nsw i64 %z2, 16 + + %or01 = or disjoint i64 %sh0, %sh1 + %or012 = or disjoint i64 %or01, %sh2 + %or0123 = or disjoint i64 %or012, %z3 + ret i64 %or0123 +} + +define i64 @reorder_i16(ptr noalias %p, ptr noalias %p1) { +; CHECK-LABEL: @reorder_i16( +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[P:%.*]], align 2 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[P1:%.*]], align 2 +; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i16> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i16> [[TMP3]] to <4 x i64> +; CHECK-NEXT: [[TMP5:%.*]] = shl nuw <4 x i64> [[TMP4]], +; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> [[TMP5]]) +; CHECK-NEXT: ret i64 [[TMP6]] +; + %g1 = getelementptr i16, ptr %p, i32 1 + %g2 = getelementptr i16, ptr %p, i32 2 + %g3 = getelementptr i16, ptr %p, i32 3 + + %t0 = load i16, ptr %p + %t1 = load i16, ptr %g1 + %t2 = load i16, ptr %g2 + %t3 = load i16, ptr %g3 + + %g11 = getelementptr i16, ptr %p1, i32 1 + %g12 = getelementptr i16, ptr %p1, i32 2 + %g13 = getelementptr i16, ptr %p1, i32 3 + + %t10 = load i16, ptr %p1 + %t11 = load i16, ptr %g11 + %t12 = load i16, ptr %g12 + %t13 = load i16, ptr %g13 + + %a0 = add i16 %t0, %t10 + %a1 = add i16 %t1, %t11 + %a2 = add i16 %t2, %t12 + %a3 = add i16 %t3, %t13 + + %z0 = zext i16 %a0 to i64 + %z1 = zext i16 %a1 to i64 + %z2 = zext i16 %a2 to i64 + %z3 = zext i16 %a3 to i64 + + %sh0 = shl nuw i64 %z0, 16 + %sh1 = shl nuw nsw i64 %z1, 32 + %sh2 = shl nuw nsw i64 %z2, 48 + + %or01 = or disjoint i64 %sh0, %sh1 + %or012 = or disjoint i64 %or01, %sh2 + %or0123 = or disjoint i64 %or012, %z3 + ret i64 %or0123 +} + diff --git a/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll index dc370bd3055d0..70ef8fdf21d5a 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll @@ -7,43 +7,10 @@ define i64 @load_bswap(ptr %p) { ; CHECK-LABEL: @load_bswap( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [[V8I8:%.*]], ptr [[P:%.*]], i64 0, i32 1 -; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 2 -; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 3 -; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 4 -; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 5 -; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 6 -; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 7 -; CHECK-NEXT: [[T0:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[T1:%.*]] = load i8, ptr [[G1]], align 1 -; CHECK-NEXT: [[T2:%.*]] = load i8, ptr [[G2]], align 1 -; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[G3]], align 1 -; CHECK-NEXT: [[T4:%.*]] = load i8, ptr [[G4]], align 1 -; CHECK-NEXT: [[T5:%.*]] = load i8, ptr [[G5]], align 1 -; CHECK-NEXT: [[T6:%.*]] = load i8, ptr [[G6]], align 1 -; CHECK-NEXT: [[T7:%.*]] = load i8, ptr [[G7]], align 1 -; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[T0]] to i64 -; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[T1]] to i64 -; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64 -; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[T3]] to i64 -; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i64 -; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64 -; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i64 -; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i64 -; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 56 -; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48 -; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40 -; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32 -; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24 -; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16 -; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8 -; CHECK-NEXT: [[OR01:%.*]] = or i64 [[SH0]], [[SH1]] -; CHECK-NEXT: [[OR012:%.*]] = or i64 [[OR01]], [[SH2]] -; CHECK-NEXT: [[OR0123:%.*]] = or i64 [[OR012]], [[SH3]] -; CHECK-NEXT: [[OR01234:%.*]] = or i64 [[OR0123]], [[SH4]] -; CHECK-NEXT: [[OR012345:%.*]] = or i64 [[OR01234]], [[SH5]] -; CHECK-NEXT: [[OR0123456:%.*]] = or i64 [[OR012345]], [[SH6]] -; CHECK-NEXT: [[OR01234567:%.*]] = or i64 [[OR0123456]], [[Z7]] +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[P:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <8 x i64> [[TMP2]], +; CHECK-NEXT: [[OR01234567:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP3]]) ; CHECK-NEXT: ret i64 [[OR01234567]] ; %g1 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 1 @@ -93,44 +60,10 @@ define i64 @load_bswap(ptr %p) { define i64 @load_bswap_nop_shift(ptr %p) { ; CHECK-LABEL: @load_bswap_nop_shift( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [[V8I8:%.*]], ptr [[P:%.*]], i64 0, i32 1 -; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 2 -; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 3 -; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 4 -; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 5 -; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 6 -; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 7 -; CHECK-NEXT: [[T0:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[T1:%.*]] = load i8, ptr [[G1]], align 1 -; CHECK-NEXT: [[T2:%.*]] = load i8, ptr [[G2]], align 1 -; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[G3]], align 1 -; CHECK-NEXT: [[T4:%.*]] = load i8, ptr [[G4]], align 1 -; CHECK-NEXT: [[T5:%.*]] = load i8, ptr [[G5]], align 1 -; CHECK-NEXT: [[T6:%.*]] = load i8, ptr [[G6]], align 1 -; CHECK-NEXT: [[T7:%.*]] = load i8, ptr [[G7]], align 1 -; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[T0]] to i64 -; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[T1]] to i64 -; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64 -; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[T3]] to i64 -; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i64 -; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64 -; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i64 -; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i64 -; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 56 -; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48 -; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40 -; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32 -; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24 -; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16 -; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8 -; CHECK-NEXT: [[SH7:%.*]] = shl nuw nsw i64 [[Z7]], 0 -; CHECK-NEXT: [[OR01:%.*]] = or i64 [[SH0]], [[SH1]] -; CHECK-NEXT: [[OR012:%.*]] = or i64 [[OR01]], [[SH2]] -; CHECK-NEXT: [[OR0123:%.*]] = or i64 [[OR012]], [[SH3]] -; CHECK-NEXT: [[OR01234:%.*]] = or i64 [[OR0123]], [[SH4]] -; CHECK-NEXT: [[OR012345:%.*]] = or i64 [[OR01234]], [[SH5]] -; CHECK-NEXT: [[OR0123456:%.*]] = or i64 [[OR012345]], [[SH6]] -; CHECK-NEXT: [[OR01234567:%.*]] = or i64 [[OR0123456]], [[SH7]] +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[P:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <8 x i64> [[TMP2]], +; CHECK-NEXT: [[OR01234567:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP3]]) ; CHECK-NEXT: ret i64 [[OR01234567]] ; %g1 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 1 @@ -182,43 +115,10 @@ define i64 @load_bswap_nop_shift(ptr %p) { define i64 @load64le(ptr %arg) { ; CHECK-LABEL: @load64le( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1 -; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2 -; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 3 -; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 4 -; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 5 -; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 6 -; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 7 -; CHECK-NEXT: [[LD0:%.*]] = load i8, ptr [[ARG]], align 1 -; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[G1]], align 1 -; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[G2]], align 1 -; CHECK-NEXT: [[LD3:%.*]] = load i8, ptr [[G3]], align 1 -; CHECK-NEXT: [[LD4:%.*]] = load i8, ptr [[G4]], align 1 -; CHECK-NEXT: [[LD5:%.*]] = load i8, ptr [[G5]], align 1 -; CHECK-NEXT: [[LD6:%.*]] = load i8, ptr [[G6]], align 1 -; CHECK-NEXT: [[LD7:%.*]] = load i8, ptr [[G7]], align 1 -; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64 -; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64 -; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64 -; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[LD3]] to i64 -; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[LD4]] to i64 -; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64 -; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64 -; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64 -; CHECK-NEXT: [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i64 [[Z3]], 24 -; CHECK-NEXT: [[S4:%.*]] = shl nuw nsw i64 [[Z4]], 32 -; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40 -; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48 -; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56 -; CHECK-NEXT: [[O1:%.*]] = or i64 [[S1]], [[Z0]] -; CHECK-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S2]] -; CHECK-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S3]] -; CHECK-NEXT: [[O4:%.*]] = or i64 [[O3]], [[S4]] -; CHECK-NEXT: [[O5:%.*]] = or i64 [[O4]], [[S5]] -; CHECK-NEXT: [[O6:%.*]] = or i64 [[O5]], [[S6]] -; CHECK-NEXT: [[O7:%.*]] = or i64 [[O6]], [[S7]] +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[ARG:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl <8 x i64> [[TMP2]], +; CHECK-NEXT: [[O7:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP3]]) ; CHECK-NEXT: ret i64 [[O7]] ; %g1 = getelementptr inbounds i8, ptr %arg, i64 1 @@ -268,44 +168,10 @@ define i64 @load64le(ptr %arg) { define i64 @load64le_nop_shift(ptr %arg) { ; CHECK-LABEL: @load64le_nop_shift( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1 -; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2 -; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 3 -; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 4 -; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 5 -; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 6 -; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 7 -; CHECK-NEXT: [[LD0:%.*]] = load i8, ptr [[ARG]], align 1 -; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[G1]], align 1 -; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[G2]], align 1 -; CHECK-NEXT: [[LD3:%.*]] = load i8, ptr [[G3]], align 1 -; CHECK-NEXT: [[LD4:%.*]] = load i8, ptr [[G4]], align 1 -; CHECK-NEXT: [[LD5:%.*]] = load i8, ptr [[G5]], align 1 -; CHECK-NEXT: [[LD6:%.*]] = load i8, ptr [[G6]], align 1 -; CHECK-NEXT: [[LD7:%.*]] = load i8, ptr [[G7]], align 1 -; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64 -; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64 -; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64 -; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[LD3]] to i64 -; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[LD4]] to i64 -; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64 -; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64 -; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64 -; CHECK-NEXT: [[S0:%.*]] = shl nuw nsw i64 [[Z0]], 0 -; CHECK-NEXT: [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i64 [[Z3]], 24 -; CHECK-NEXT: [[S4:%.*]] = shl nuw nsw i64 [[Z4]], 32 -; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40 -; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48 -; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56 -; CHECK-NEXT: [[O1:%.*]] = or i64 [[S1]], [[S0]] -; CHECK-NEXT: [[O2:%.*]] = or i64 [[O1]], [[S2]] -; CHECK-NEXT: [[O3:%.*]] = or i64 [[O2]], [[S3]] -; CHECK-NEXT: [[O4:%.*]] = or i64 [[O3]], [[S4]] -; CHECK-NEXT: [[O5:%.*]] = or i64 [[O4]], [[S5]] -; CHECK-NEXT: [[O6:%.*]] = or i64 [[O5]], [[S6]] -; CHECK-NEXT: [[O7:%.*]] = or i64 [[O6]], [[S7]] +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[ARG:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i64> +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <8 x i64> [[TMP2]], +; CHECK-NEXT: [[O7:%.*]] = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> [[TMP3]]) ; CHECK-NEXT: ret i64 [[O7]] ; %g1 = getelementptr inbounds i8, ptr %arg, i64 1 @@ -355,43 +221,8 @@ define i64 @load64le_nop_shift(ptr %arg) { define i64 @load_bswap_disjoint(ptr %p) { ; CHECK-LABEL: @load_bswap_disjoint( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [[V8I8:%.*]], ptr [[P:%.*]], i64 0, i32 1 -; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 2 -; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 3 -; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 4 -; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 5 -; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 6 -; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 7 -; CHECK-NEXT: [[T0:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[T1:%.*]] = load i8, ptr [[G1]], align 1 -; CHECK-NEXT: [[T2:%.*]] = load i8, ptr [[G2]], align 1 -; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[G3]], align 1 -; CHECK-NEXT: [[T4:%.*]] = load i8, ptr [[G4]], align 1 -; CHECK-NEXT: [[T5:%.*]] = load i8, ptr [[G5]], align 1 -; CHECK-NEXT: [[T6:%.*]] = load i8, ptr [[G6]], align 1 -; CHECK-NEXT: [[T7:%.*]] = load i8, ptr [[G7]], align 1 -; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[T0]] to i64 -; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[T1]] to i64 -; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64 -; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[T3]] to i64 -; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i64 -; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64 -; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i64 -; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i64 -; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 56 -; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48 -; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40 -; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32 -; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24 -; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16 -; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8 -; CHECK-NEXT: [[OR01:%.*]] = or disjoint i64 [[SH0]], [[SH1]] -; CHECK-NEXT: [[OR012:%.*]] = or disjoint i64 [[OR01]], [[SH2]] -; CHECK-NEXT: [[OR0123:%.*]] = or disjoint i64 [[OR012]], [[SH3]] -; CHECK-NEXT: [[OR01234:%.*]] = or disjoint i64 [[OR0123]], [[SH4]] -; CHECK-NEXT: [[OR012345:%.*]] = or disjoint i64 [[OR01234]], [[SH5]] -; CHECK-NEXT: [[OR0123456:%.*]] = or disjoint i64 [[OR012345]], [[SH6]] -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i64 [[OR0123456]], [[Z7]] +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[P:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]]) ; CHECK-NEXT: ret i64 [[TMP2]] ; %g1 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 1 @@ -441,44 +272,8 @@ define i64 @load_bswap_disjoint(ptr %p) { define i64 @load_bswap_nop_shift_disjoint(ptr %p) { ; CHECK-LABEL: @load_bswap_nop_shift_disjoint( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [[V8I8:%.*]], ptr [[P:%.*]], i64 0, i32 1 -; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 2 -; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 3 -; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 4 -; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 5 -; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 6 -; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], ptr [[P]], i64 0, i32 7 -; CHECK-NEXT: [[T0:%.*]] = load i8, ptr [[P]], align 1 -; CHECK-NEXT: [[T1:%.*]] = load i8, ptr [[G1]], align 1 -; CHECK-NEXT: [[T2:%.*]] = load i8, ptr [[G2]], align 1 -; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[G3]], align 1 -; CHECK-NEXT: [[T4:%.*]] = load i8, ptr [[G4]], align 1 -; CHECK-NEXT: [[T5:%.*]] = load i8, ptr [[G5]], align 1 -; CHECK-NEXT: [[T6:%.*]] = load i8, ptr [[G6]], align 1 -; CHECK-NEXT: [[T7:%.*]] = load i8, ptr [[G7]], align 1 -; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[T0]] to i64 -; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[T1]] to i64 -; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[T2]] to i64 -; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[T3]] to i64 -; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i64 -; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64 -; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i64 -; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i64 -; CHECK-NEXT: [[SH0:%.*]] = shl nuw i64 [[Z0]], 56 -; CHECK-NEXT: [[SH1:%.*]] = shl nuw nsw i64 [[Z1]], 48 -; CHECK-NEXT: [[SH2:%.*]] = shl nuw nsw i64 [[Z2]], 40 -; CHECK-NEXT: [[SH3:%.*]] = shl nuw nsw i64 [[Z3]], 32 -; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24 -; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16 -; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8 -; CHECK-NEXT: [[SH7:%.*]] = shl nuw nsw i64 [[Z7]], 0 -; CHECK-NEXT: [[OR01:%.*]] = or disjoint i64 [[SH0]], [[SH1]] -; CHECK-NEXT: [[OR012:%.*]] = or disjoint i64 [[OR01]], [[SH2]] -; CHECK-NEXT: [[OR0123:%.*]] = or disjoint i64 [[OR012]], [[SH3]] -; CHECK-NEXT: [[OR01234:%.*]] = or disjoint i64 [[OR0123]], [[SH4]] -; CHECK-NEXT: [[OR012345:%.*]] = or disjoint i64 [[OR01234]], [[SH5]] -; CHECK-NEXT: [[OR0123456:%.*]] = or disjoint i64 [[OR012345]], [[SH6]] -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i64 [[OR0123456]], [[SH7]] +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[P:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.bswap.i64(i64 [[TMP1]]) ; CHECK-NEXT: ret i64 [[TMP2]] ; %g1 = getelementptr inbounds %v8i8, ptr %p, i64 0, i32 1 @@ -528,43 +323,7 @@ define i64 @load_bswap_nop_shift_disjoint(ptr %p) { define i64 @load64le_disjoint(ptr %arg) { ; CHECK-LABEL: @load64le_disjoint( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1 -; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2 -; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 3 -; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 4 -; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 5 -; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 6 -; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 7 -; CHECK-NEXT: [[LD0:%.*]] = load i8, ptr [[ARG]], align 1 -; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[G1]], align 1 -; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[G2]], align 1 -; CHECK-NEXT: [[LD3:%.*]] = load i8, ptr [[G3]], align 1 -; CHECK-NEXT: [[LD4:%.*]] = load i8, ptr [[G4]], align 1 -; CHECK-NEXT: [[LD5:%.*]] = load i8, ptr [[G5]], align 1 -; CHECK-NEXT: [[LD6:%.*]] = load i8, ptr [[G6]], align 1 -; CHECK-NEXT: [[LD7:%.*]] = load i8, ptr [[G7]], align 1 -; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64 -; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64 -; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64 -; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[LD3]] to i64 -; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[LD4]] to i64 -; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64 -; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64 -; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64 -; CHECK-NEXT: [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i64 [[Z3]], 24 -; CHECK-NEXT: [[S4:%.*]] = shl nuw nsw i64 [[Z4]], 32 -; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40 -; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48 -; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i64 [[S1]], [[Z0]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i64 [[O1]], [[S2]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i64 [[O2]], [[S3]] -; CHECK-NEXT: [[O4:%.*]] = or disjoint i64 [[O3]], [[S4]] -; CHECK-NEXT: [[O5:%.*]] = or disjoint i64 [[O4]], [[S5]] -; CHECK-NEXT: [[O6:%.*]] = or disjoint i64 [[O5]], [[S6]] -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i64 [[O6]], [[S7]] +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ARG:%.*]], align 1 ; CHECK-NEXT: ret i64 [[TMP2]] ; %g1 = getelementptr inbounds i8, ptr %arg, i64 1 @@ -614,44 +373,7 @@ define i64 @load64le_disjoint(ptr %arg) { define i64 @load64le_nop_shift_disjoint(ptr %arg) { ; CHECK-LABEL: @load64le_nop_shift_disjoint( -; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, ptr [[ARG:%.*]], i64 1 -; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 2 -; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 3 -; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 4 -; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 5 -; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 6 -; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, ptr [[ARG]], i64 7 -; CHECK-NEXT: [[LD0:%.*]] = load i8, ptr [[ARG]], align 1 -; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[G1]], align 1 -; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[G2]], align 1 -; CHECK-NEXT: [[LD3:%.*]] = load i8, ptr [[G3]], align 1 -; CHECK-NEXT: [[LD4:%.*]] = load i8, ptr [[G4]], align 1 -; CHECK-NEXT: [[LD5:%.*]] = load i8, ptr [[G5]], align 1 -; CHECK-NEXT: [[LD6:%.*]] = load i8, ptr [[G6]], align 1 -; CHECK-NEXT: [[LD7:%.*]] = load i8, ptr [[G7]], align 1 -; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64 -; CHECK-NEXT: [[Z1:%.*]] = zext i8 [[LD1]] to i64 -; CHECK-NEXT: [[Z2:%.*]] = zext i8 [[LD2]] to i64 -; CHECK-NEXT: [[Z3:%.*]] = zext i8 [[LD3]] to i64 -; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[LD4]] to i64 -; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64 -; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64 -; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64 -; CHECK-NEXT: [[S0:%.*]] = shl nuw nsw i64 [[Z0]], 0 -; CHECK-NEXT: [[S1:%.*]] = shl nuw nsw i64 [[Z1]], 8 -; CHECK-NEXT: [[S2:%.*]] = shl nuw nsw i64 [[Z2]], 16 -; CHECK-NEXT: [[S3:%.*]] = shl nuw nsw i64 [[Z3]], 24 -; CHECK-NEXT: [[S4:%.*]] = shl nuw nsw i64 [[Z4]], 32 -; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40 -; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48 -; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56 -; CHECK-NEXT: [[O1:%.*]] = or disjoint i64 [[S1]], [[S0]] -; CHECK-NEXT: [[O2:%.*]] = or disjoint i64 [[O1]], [[S2]] -; CHECK-NEXT: [[O3:%.*]] = or disjoint i64 [[O2]], [[S3]] -; CHECK-NEXT: [[O4:%.*]] = or disjoint i64 [[O3]], [[S4]] -; CHECK-NEXT: [[O5:%.*]] = or disjoint i64 [[O4]], [[S5]] -; CHECK-NEXT: [[O6:%.*]] = or disjoint i64 [[O5]], [[S6]] -; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i64 [[O6]], [[S7]] +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ARG:%.*]], align 1 ; CHECK-NEXT: ret i64 [[TMP2]] ; %g1 = getelementptr inbounds i8, ptr %arg, i64 1 @@ -701,84 +423,22 @@ define i64 @load64le_nop_shift_disjoint(ptr %arg) { define void @PR39538(ptr %t0, ptr %t1) { ; CHECK-LABEL: @PR39538( -; CHECK-NEXT: [[T6:%.*]] = getelementptr inbounds i8, ptr [[T0:%.*]], i64 1 -; CHECK-NEXT: [[T11:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 2 -; CHECK-NEXT: [[T16:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 3 -; CHECK-NEXT: [[T20:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 4 -; CHECK-NEXT: [[T24:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 5 -; CHECK-NEXT: [[T29:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 6 -; CHECK-NEXT: [[T34:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 7 -; CHECK-NEXT: [[T39:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 8 -; CHECK-NEXT: [[T43:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 9 -; CHECK-NEXT: [[T48:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 10 -; CHECK-NEXT: [[T53:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 11 -; CHECK-NEXT: [[T58:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 12 -; CHECK-NEXT: [[T62:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 13 -; CHECK-NEXT: [[T67:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 14 -; CHECK-NEXT: [[T72:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 15 -; CHECK-NEXT: [[T38:%.*]] = getelementptr inbounds i32, ptr [[T1:%.*]], i64 1 -; CHECK-NEXT: [[T57:%.*]] = getelementptr inbounds i32, ptr [[T1]], i64 2 -; CHECK-NEXT: [[T76:%.*]] = getelementptr inbounds i32, ptr [[T1]], i64 3 -; CHECK-NEXT: [[T3:%.*]] = load i8, ptr [[T0]], align 1 -; CHECK-NEXT: [[T7:%.*]] = load i8, ptr [[T6]], align 1 -; CHECK-NEXT: [[T12:%.*]] = load i8, ptr [[T11]], align 1 -; CHECK-NEXT: [[T17:%.*]] = load i8, ptr [[T16]], align 1 -; CHECK-NEXT: [[T21:%.*]] = load i8, ptr [[T20]], align 1 -; CHECK-NEXT: [[T25:%.*]] = load i8, ptr [[T24]], align 1 -; CHECK-NEXT: [[T30:%.*]] = load i8, ptr [[T29]], align 1 -; CHECK-NEXT: [[T35:%.*]] = load i8, ptr [[T34]], align 1 -; CHECK-NEXT: [[T40:%.*]] = load i8, ptr [[T39]], align 1 -; CHECK-NEXT: [[T44:%.*]] = load i8, ptr [[T43]], align 1 -; CHECK-NEXT: [[T49:%.*]] = load i8, ptr [[T48]], align 1 -; CHECK-NEXT: [[T54:%.*]] = load i8, ptr [[T53]], align 1 -; CHECK-NEXT: [[T59:%.*]] = load i8, ptr [[T58]], align 1 -; CHECK-NEXT: [[T63:%.*]] = load i8, ptr [[T62]], align 1 -; CHECK-NEXT: [[T68:%.*]] = load i8, ptr [[T67]], align 1 -; CHECK-NEXT: [[T73:%.*]] = load i8, ptr [[T72]], align 1 -; CHECK-NEXT: [[T4:%.*]] = zext i8 [[T3]] to i32 -; CHECK-NEXT: [[T8:%.*]] = zext i8 [[T7]] to i32 -; CHECK-NEXT: [[T13:%.*]] = zext i8 [[T12]] to i32 -; CHECK-NEXT: [[T18:%.*]] = zext i8 [[T17]] to i32 -; CHECK-NEXT: [[T22:%.*]] = zext i8 [[T21]] to i32 -; CHECK-NEXT: [[T26:%.*]] = zext i8 [[T25]] to i32 -; CHECK-NEXT: [[T31:%.*]] = zext i8 [[T30]] to i32 -; CHECK-NEXT: [[T36:%.*]] = zext i8 [[T35]] to i32 -; CHECK-NEXT: [[T41:%.*]] = zext i8 [[T40]] to i32 -; CHECK-NEXT: [[T45:%.*]] = zext i8 [[T44]] to i32 -; CHECK-NEXT: [[T50:%.*]] = zext i8 [[T49]] to i32 -; CHECK-NEXT: [[T55:%.*]] = zext i8 [[T54]] to i32 -; CHECK-NEXT: [[T60:%.*]] = zext i8 [[T59]] to i32 -; CHECK-NEXT: [[T64:%.*]] = zext i8 [[T63]] to i32 -; CHECK-NEXT: [[T69:%.*]] = zext i8 [[T68]] to i32 -; CHECK-NEXT: [[T74:%.*]] = zext i8 [[T73]] to i32 -; CHECK-NEXT: [[T5:%.*]] = shl nuw i32 [[T4]], 24 -; CHECK-NEXT: [[T23:%.*]] = shl nuw i32 [[T22]], 24 -; CHECK-NEXT: [[T42:%.*]] = shl nuw i32 [[T41]], 24 -; CHECK-NEXT: [[T61:%.*]] = shl nuw i32 [[T60]], 24 -; CHECK-NEXT: [[T9:%.*]] = shl nuw nsw i32 [[T8]], 16 -; CHECK-NEXT: [[T27:%.*]] = shl nuw nsw i32 [[T26]], 16 -; CHECK-NEXT: [[T46:%.*]] = shl nuw nsw i32 [[T45]], 16 -; CHECK-NEXT: [[T65:%.*]] = shl nuw nsw i32 [[T64]], 16 -; CHECK-NEXT: [[T14:%.*]] = shl nuw nsw i32 [[T13]], 8 -; CHECK-NEXT: [[T32:%.*]] = shl nuw nsw i32 [[T31]], 8 -; CHECK-NEXT: [[T51:%.*]] = shl nuw nsw i32 [[T50]], 8 -; CHECK-NEXT: [[T70:%.*]] = shl nuw nsw i32 [[T69]], 8 -; CHECK-NEXT: [[T10:%.*]] = or i32 [[T9]], [[T5]] -; CHECK-NEXT: [[T15:%.*]] = or i32 [[T10]], [[T14]] -; CHECK-NEXT: [[T19:%.*]] = or i32 [[T15]], [[T18]] -; CHECK-NEXT: [[T28:%.*]] = or i32 [[T27]], [[T23]] -; CHECK-NEXT: [[T33:%.*]] = or i32 [[T28]], [[T32]] -; CHECK-NEXT: [[T37:%.*]] = or i32 [[T33]], [[T36]] -; CHECK-NEXT: [[T47:%.*]] = or i32 [[T46]], [[T42]] -; CHECK-NEXT: [[T52:%.*]] = or i32 [[T47]], [[T51]] -; CHECK-NEXT: [[T56:%.*]] = or i32 [[T52]], [[T55]] -; CHECK-NEXT: [[T66:%.*]] = or i32 [[T65]], [[T61]] -; CHECK-NEXT: [[T71:%.*]] = or i32 [[T66]], [[T70]] -; CHECK-NEXT: [[T75:%.*]] = or i32 [[T71]], [[T74]] -; CHECK-NEXT: store i32 [[T19]], ptr [[T1]], align 4 -; CHECK-NEXT: store i32 [[T37]], ptr [[T38]], align 4 -; CHECK-NEXT: store i32 [[T56]], ptr [[T57]], align 4 -; CHECK-NEXT: store i32 [[T75]], ptr [[T76]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[T0:%.*]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <4 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32> +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <4 x i32> +; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <4 x i32> +; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i8> [[TMP6]] to <4 x i32> +; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <4 x i32> +; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i8> [[TMP8]] to <4 x i32> +; CHECK-NEXT: [[TMP10:%.*]] = shl nuw <4 x i32> [[TMP3]], +; CHECK-NEXT: [[TMP11:%.*]] = shl nuw <4 x i32> [[TMP5]], +; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw <4 x i32> [[TMP7]], splat (i32 8) +; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i32> [[TMP11]], [[TMP10]] +; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], [[TMP12]] +; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP14]], [[TMP9]] +; CHECK-NEXT: store <4 x i32> [[TMP15]], ptr [[T1:%.*]], align 4 ; CHECK-NEXT: ret void ; %t6 = getelementptr inbounds i8, ptr %t0, i64 1 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/bswap-reduction-aliased.ll b/llvm/test/Transforms/SLPVectorizer/X86/bswap-reduction-aliased.ll new file mode 100644 index 0000000000000..5f15269469df1 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/bswap-reduction-aliased.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + +define i32 @test(ptr %x, ptr %y) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: ptr [[X:%.*]], ptr [[Y:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X]], align 1 +; CHECK-NEXT: [[OR10:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP0]]) +; CHECK-NEXT: store i8 1, ptr [[Y]], align 1 +; CHECK-NEXT: ret i32 [[OR10]] +; +entry: + %0 = load i8, ptr %x, align 1 + %arrayidx1 = getelementptr inbounds nuw i8, ptr %x, i64 1 + %1 = load i8, ptr %arrayidx1, align 1 + %arrayidx2 = getelementptr inbounds nuw i8, ptr %x, i64 2 + %2 = load i8, ptr %arrayidx2, align 1 + %arrayidx3 = getelementptr inbounds nuw i8, ptr %x, i64 3 + %3 = load i8, ptr %arrayidx3, align 1 + store i8 1, ptr %y, align 1 + %conv = zext i8 %3 to i32 + %conv4 = zext i8 %2 to i32 + %shl = shl nuw nsw i32 %conv4, 8 + %conv5 = zext i8 %1 to i32 + %shl6 = shl nuw nsw i32 %conv5, 16 + %conv8 = zext i8 %0 to i32 + %shl9 = shl nuw i32 %conv8, 24 + %or = or disjoint i32 %shl6, %shl9 + %or7 = or disjoint i32 %or, %conv + %or10 = or disjoint i32 %or7, %shl + ret i32 %or10 +} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll index c02ef8388b066..7936d1e77c702 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll @@ -10,23 +10,10 @@ define i32 @_Z9load_le32Ph(ptr nocapture readonly %data) { ; CHECK-LABEL: @_Z9load_le32Ph( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 1 -; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 1 -; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1 -; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i32 -; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 8 -; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL3]], [[CONV]] -; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 2 -; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1 -; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i32 -; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 16 -; CHECK-NEXT: [[OR7:%.*]] = or i32 [[OR]], [[SHL6]] -; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 3 -; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1 -; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i32 -; CHECK-NEXT: [[SHL10:%.*]] = shl nuw i32 [[CONV9]], 24 -; CHECK-NEXT: [[OR11:%.*]] = or i32 [[OR7]], [[SHL10]] +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[DATA:%.*]], align 1 +; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[TMP1]], +; CHECK-NEXT: [[OR11:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP2]]) ; CHECK-NEXT: ret i32 [[OR11]] ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll b/llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll index 0545e5403f594..5f8f7ac9ed36c 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/load-merge.ll @@ -10,23 +10,10 @@ define i32 @_Z9load_le32Ph(ptr nocapture readonly %data) { ; CHECK-LABEL: @_Z9load_le32Ph( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[DATA:%.*]], align 1 -; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 1 -; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX1]], align 1 -; CHECK-NEXT: [[CONV2:%.*]] = zext i8 [[TMP1]] to i32 -; CHECK-NEXT: [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 8 -; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL3]], [[CONV]] -; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 2 -; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[ARRAYIDX4]], align 1 -; CHECK-NEXT: [[CONV5:%.*]] = zext i8 [[TMP2]] to i32 -; CHECK-NEXT: [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 16 -; CHECK-NEXT: [[OR7:%.*]] = or i32 [[OR]], [[SHL6]] -; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[DATA]], i64 3 -; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1 -; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP3]] to i32 -; CHECK-NEXT: [[SHL10:%.*]] = shl nuw i32 [[CONV9]], 24 -; CHECK-NEXT: [[OR11:%.*]] = or i32 [[OR7]], [[SHL10]] +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[DATA:%.*]], align 1 +; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[TMP1]], +; CHECK-NEXT: [[OR11:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP2]]) ; CHECK-NEXT: ret i32 [[OR11]] ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll new file mode 100644 index 0000000000000..1cba1bb586e36 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation.ll @@ -0,0 +1,76 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=icelake-server < %s | FileCheck %s + +define void @test(ptr %src, i8 %0, i32 %conv2) { +; CHECK-LABEL: define void @test( +; CHECK-SAME: ptr [[SRC:%.*]], i8 [[TMP0:%.*]], i32 [[CONV2:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[CONV65:%.*]] = zext i8 [[TMP0]] to i32 +; CHECK-NEXT: [[ADD36:%.*]] = add i32 [[CONV65]], 1 +; CHECK-NEXT: [[ADD37:%.*]] = or i32 [[ADD36]], [[CONV2]] +; CHECK-NEXT: [[CONV4:%.*]] = zext i8 [[TMP0]] to i32 +; CHECK-NEXT: [[ADD38:%.*]] = or i32 [[ADD37]], [[CONV4]] +; CHECK-NEXT: [[SHR39:%.*]] = lshr i32 [[ADD38]], 1 +; CHECK-NEXT: [[CONV40:%.*]] = trunc i32 [[SHR39]] to i8 +; CHECK-NEXT: [[ARRAYIDX41:%.*]] = getelementptr i8, ptr [[SRC]], i64 1 +; CHECK-NEXT: store i8 [[CONV40]], ptr [[ARRAYIDX41]], align 1 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[CONV4]], 1 +; CHECK-NEXT: [[ADD45:%.*]] = or i32 [[ADD]], [[CONV2]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[SRC]], align 1 +; CHECK-NEXT: [[CONV8:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: [[ADD46:%.*]] = or i32 [[ADD45]], [[CONV8]] +; CHECK-NEXT: [[SHR47:%.*]] = lshr i32 [[ADD46]], 1 +; CHECK-NEXT: [[CONV48:%.*]] = trunc i32 [[SHR47]] to i8 +; CHECK-NEXT: [[ARRAYIDX49:%.*]] = getelementptr i8, ptr [[SRC]], i64 2 +; CHECK-NEXT: store i8 [[CONV48]], ptr [[ARRAYIDX49]], align 1 +; CHECK-NEXT: [[MUL52:%.*]] = shl i32 [[CONV8]], 1 +; CHECK-NEXT: [[ADD54:%.*]] = or i32 [[MUL52]], 1 +; CHECK-NEXT: [[CONV10:%.*]] = zext i8 [[TMP0]] to i32 +; CHECK-NEXT: [[ADD55:%.*]] = add i32 [[ADD54]], [[CONV10]] +; CHECK-NEXT: [[SHR56:%.*]] = lshr i32 [[ADD55]], 1 +; CHECK-NEXT: [[CONV57:%.*]] = trunc i32 [[SHR56]] to i8 +; CHECK-NEXT: [[ARRAYIDX58:%.*]] = getelementptr i8, ptr [[SRC]], i64 3 +; CHECK-NEXT: store i8 [[CONV57]], ptr [[ARRAYIDX58]], align 1 +; CHECK-NEXT: [[ADD63:%.*]] = add i32 [[CONV8]], 1 +; CHECK-NEXT: [[ADD64:%.*]] = or i32 [[ADD63]], [[CONV10]] +; CHECK-NEXT: [[SHR66:%.*]] = lshr i32 [[ADD64]], 1 +; CHECK-NEXT: [[CONV67:%.*]] = trunc i32 [[SHR66]] to i8 +; CHECK-NEXT: [[ARRAYIDX68:%.*]] = getelementptr i8, ptr [[SRC]], i64 4 +; CHECK-NEXT: store i8 [[CONV67]], ptr [[ARRAYIDX68]], align 1 +; CHECK-NEXT: ret void +; +entry: + %conv65 = zext i8 %0 to i32 + %add36 = add i32 %conv65, 1 + %add37 = or i32 %add36, %conv2 + %conv4 = zext i8 %0 to i32 + %add38 = or i32 %add37, %conv4 + %shr39 = lshr i32 %add38, 1 + %conv40 = trunc i32 %shr39 to i8 + %arrayidx41 = getelementptr i8, ptr %src, i64 1 + store i8 %conv40, ptr %arrayidx41, align 1 + %add = add i32 %conv4, 1 + %add45 = or i32 %add, %conv2 + %1 = load i8, ptr %src, align 1 + %conv8 = zext i8 %1 to i32 + %add46 = or i32 %add45, %conv8 + %shr47 = lshr i32 %add46, 1 + %conv48 = trunc i32 %shr47 to i8 + %arrayidx49 = getelementptr i8, ptr %src, i64 2 + store i8 %conv48, ptr %arrayidx49, align 1 + %mul52 = shl i32 %conv8, 1 + %add54 = or i32 %mul52, 1 + %conv10 = zext i8 %0 to i32 + %add55 = add i32 %add54, %conv10 + %shr56 = lshr i32 %add55, 1 + %conv57 = trunc i32 %shr56 to i8 + %arrayidx58 = getelementptr i8, ptr %src, i64 3 + store i8 %conv57, ptr %arrayidx58, align 1 + %add63 = add i32 %conv8, 1 + %add64 = or i32 %add63, %conv10 + %shr66 = lshr i32 %add64, 1 + %conv67 = trunc i32 %shr66 to i8 + %arrayidx68 = getelementptr i8, ptr %src, i64 4 + store i8 %conv67, ptr %arrayidx68, align 1 + ret void +} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation2.ll b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation2.ll new file mode 100644 index 0000000000000..c311ccc4a06f1 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation2.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + +define i32 @test(ptr %img, i32 %0) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: ptr [[IMG:%.*]], i32 [[TMP0:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[ADD65:%.*]] = add i32 [[TMP0]], 1 +; CHECK-NEXT: [[ADD47_1_1:%.*]] = or i32 [[TMP0]], 1 +; CHECK-NEXT: [[ADD65_1:%.*]] = add i32 [[ADD47_1_1]], 2 +; CHECK-NEXT: [[SUB146:%.*]] = sub i32 [[ADD65]], [[ADD65_1]] +; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[IMG]], align 8 +; CHECK-NEXT: [[ARRAYIDX150:%.*]] = getelementptr i8, ptr [[TMP1]], i64 13120 +; CHECK-NEXT: store i32 [[SUB146]], ptr [[ARRAYIDX150]], align 8 +; CHECK-NEXT: [[MUL152:%.*]] = shl i32 [[ADD65]], 1 +; CHECK-NEXT: [[ADD154:%.*]] = or i32 [[MUL152]], [[ADD65_1]] +; CHECK-NEXT: [[INVARIANT_GEP_16:%.*]] = getelementptr i8, ptr [[TMP1]], i64 13116 +; CHECK-NEXT: store i32 [[ADD154]], ptr [[INVARIANT_GEP_16]], align 4 +; CHECK-NEXT: ret i32 0 +; +entry: + %add65 = add i32 %0, 1 + %add47.1.1 = or i32 %0, 1 + %add65.1 = add i32 %add47.1.1, 2 + %sub146 = sub i32 %add65, %add65.1 + %1 = load ptr, ptr %img, align 8 + %arrayidx150 = getelementptr i8, ptr %1, i64 13120 + store i32 %sub146, ptr %arrayidx150, align 8 + %mul152 = shl i32 %add65, 1 + %add154 = or i32 %mul152, %add65.1 + %invariant.gep.16 = getelementptr i8, ptr %1, i64 13116 + store i32 %add154, ptr %invariant.gep.16, align 4 + ret i32 0 +} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation3.ll b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation3.ll new file mode 100644 index 0000000000000..1134c0133d6af --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation3.ll @@ -0,0 +1,56 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + +define i32 @test(ptr %img, i32 %0, i32 %1) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: ptr [[IMG:%.*]], i32 [[TMP0:%.*]], i32 [[TMP1:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[IMG]], align 8 +; CHECK-NEXT: [[GEP1053_2:%.*]] = getelementptr i8, ptr [[TMP2]], i64 13312 +; CHECK-NEXT: [[GEP1053_3:%.*]] = getelementptr i8, ptr [[TMP2]], i64 13316 +; CHECK-NEXT: [[ADD118_1:%.*]] = add i32 [[TMP1]], 1 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[GEP1053_3]], align 4 +; CHECK-NEXT: [[ADD118:%.*]] = add i32 [[TMP3]], [[TMP0]] +; CHECK-NEXT: [[ADD139:%.*]] = add i32 [[ADD118_1]], [[ADD118]] +; CHECK-NEXT: [[M71:%.*]] = getelementptr i8, ptr [[TMP2]], i64 13112 +; CHECK-NEXT: store i32 [[ADD139]], ptr [[M71]], align 8 +; CHECK-NEXT: [[SUB146:%.*]] = sub i32 [[ADD118]], [[ADD118_1]] +; CHECK-NEXT: [[ARRAYIDX150:%.*]] = getelementptr i8, ptr [[TMP2]], i64 13120 +; CHECK-NEXT: store i32 [[SUB146]], ptr [[ARRAYIDX150]], align 8 +; CHECK-NEXT: [[SUB131:%.*]] = sub i32 0, [[TMP0]] +; CHECK-NEXT: [[MUL152:%.*]] = shl i32 [[SUB131]], 1 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[GEP1053_2]], align 4 +; CHECK-NEXT: [[SUB131_1:%.*]] = sub i32 1, [[TMP4]] +; CHECK-NEXT: [[ADD154:%.*]] = add i32 [[MUL152]], [[SUB131_1]] +; CHECK-NEXT: [[ARRAYIDX158:%.*]] = getelementptr i8, ptr [[TMP2]], i64 13116 +; CHECK-NEXT: store i32 [[ADD154]], ptr [[ARRAYIDX158]], align 4 +; CHECK-NEXT: [[SUB162:%.*]] = sub i32 [[SUB131]], [[SUB131_1]] +; CHECK-NEXT: [[ARRAYIDX166:%.*]] = getelementptr i8, ptr [[TMP2]], i64 13124 +; CHECK-NEXT: store i32 [[SUB162]], ptr [[ARRAYIDX166]], align 4 +; CHECK-NEXT: ret i32 0 +; +entry: + %2 = load ptr, ptr %img, align 8 + %gep1053.2 = getelementptr i8, ptr %2, i64 13312 + %gep1053.3 = getelementptr i8, ptr %2, i64 13316 + %add118.1 = add i32 %1, 1 + %3 = load i32, ptr %gep1053.3, align 4 + %add118 = add i32 %3, %0 + %add139 = add i32 %add118.1, %add118 + %m71 = getelementptr i8, ptr %2, i64 13112 + store i32 %add139, ptr %m71, align 8 + %sub146 = sub i32 %add118, %add118.1 + %arrayidx150 = getelementptr i8, ptr %2, i64 13120 + store i32 %sub146, ptr %arrayidx150, align 8 + %sub131 = sub i32 0, %0 + %mul152 = shl i32 %sub131, 1 + %4 = load i32, ptr %gep1053.2, align 4 + %sub131.1 = sub i32 1, %4 + %add154 = add i32 %mul152, %sub131.1 + %arrayidx158 = getelementptr i8, ptr %2, i64 13116 + store i32 %add154, ptr %arrayidx158, align 4 + %sub162 = sub i32 %sub131, %sub131.1 + %arrayidx166 = getelementptr i8, ptr %2, i64 13124 + store i32 %sub162, ptr %arrayidx166, align 4 + ret i32 0 +} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation4.ll b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation4.ll new file mode 100644 index 0000000000000..68a2138aa88db --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation4.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=icelake-server < %s | FileCheck %s + +@dequant_coef = external constant [6 x [4 x [4 x i32]]] + +define fastcc i32 @test(ptr %0, i16 %1, i32 %2) { +; CHECK-LABEL: define fastcc i32 @test( +; CHECK-SAME: ptr [[TMP0:%.*]], i16 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[CONV_2:%.*]] = zext i16 [[TMP1]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP0]], align 2 +; CHECK-NEXT: [[ADD68:%.*]] = add i32 [[TMP2]], 1 +; CHECK-NEXT: [[CONV_3_1:%.*]] = zext i16 [[TMP3]] to i32 +; CHECK-NEXT: [[ADD68_1:%.*]] = add i32 [[CONV_3_1]], -1 +; CHECK-NEXT: [[ADD118_1:%.*]] = or i32 [[ADD68]], [[ADD68_1]] +; CHECK-NEXT: [[CMP16_I:%.*]] = icmp slt i32 [[ADD118_1]], 0 +; CHECK-NEXT: [[SUB2_I2:%.*]] = sub i32 0, [[TMP2]] +; CHECK-NEXT: [[ADD56_1:%.*]] = or i32 [[TMP2]], [[CONV_3_1]] +; CHECK-NEXT: [[ADD37_1:%.*]] = add i32 [[CONV_2]], 1 +; CHECK-NEXT: [[MUL137:%.*]] = shl i32 [[ADD56_1]], 1 +; CHECK-NEXT: [[SUB138:%.*]] = sub i32 [[ADD37_1]], [[MUL137]] +; CHECK-NEXT: [[CMP16_I45:%.*]] = icmp slt i32 [[SUB138]], 0 +; CHECK-NEXT: [[SUB2_I44:%.*]] = sub i32 0, [[ADD56_1]] +; CHECK-NEXT: [[RETVAL_0_I46:%.*]] = select i1 [[CMP16_I45]], i32 [[SUB2_I44]], i32 0 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @dequant_coef, i64 12), align 4 +; CHECK-NEXT: [[MUL175_3635:%.*]] = mul i32 [[RETVAL_0_I46]], [[TMP4]] +; CHECK-NEXT: [[RETVAL_0_I:%.*]] = select i1 [[CMP16_I]], i32 [[SUB2_I2]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @dequant_coef, i64 16), align 16 +; CHECK-NEXT: [[MUL175_1:%.*]] = mul i32 [[RETVAL_0_I]], [[TMP5]] +; CHECK-NEXT: [[ADD300:%.*]] = or i32 [[MUL175_3635]], [[MUL175_1]] +; CHECK-NEXT: ret i32 [[ADD300]] +; +entry: + %conv.2 = zext i16 %1 to i32 + %3 = load i16, ptr %0, align 2 + %add68 = add i32 %2, 1 + %conv.3.1 = zext i16 %3 to i32 + %add68.1 = add i32 %conv.3.1, -1 + %add118.1 = or i32 %add68, %add68.1 + %cmp16.i = icmp slt i32 %add118.1, 0 + %sub2.i2 = sub i32 0, %2 + %add56.1 = or i32 %2, %conv.3.1 + %add37.1 = add i32 %conv.2, 1 + %mul137 = shl i32 %add56.1, 1 + %sub138 = sub i32 %add37.1, %mul137 + %cmp16.i45 = icmp slt i32 %sub138, 0 + %sub2.i44 = sub i32 0, %add56.1 + %retval.0.i46 = select i1 %cmp16.i45, i32 %sub2.i44, i32 0 + %4 = load i32, ptr getelementptr inbounds nuw (i8, ptr @dequant_coef, i64 12), align 4 + %mul175.3635 = mul i32 %retval.0.i46, %4 + %retval.0.i = select i1 %cmp16.i, i32 %sub2.i2, i32 0 + %5 = load i32, ptr getelementptr inbounds nuw (i8, ptr @dequant_coef, i64 16), align 16 + %mul175.1 = mul i32 %retval.0.i, %5 + %add300 = or i32 %mul175.3635, %mul175.1 + ret i32 %add300 +} + diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll new file mode 100644 index 0000000000000..6fea312b99b25 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/shl-to-add-transformation5.ll @@ -0,0 +1,166 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=icelake-server -slp-threshold=-5 < %s | FileCheck %s + +@st = external global [4 x [4 x i32]] + +define i32 @test(i32 %0, i32 %1) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: i32 [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[ADD110:%.*]] = add i32 [[TMP0]], [[TMP1]] +; CHECK-NEXT: [[DOTNEG_NEG:%.*]] = shl i32 [[TMP0]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = shl <2 x i32> [[TMP3]], +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr @st, i64 12), align 4 +; CHECK-NEXT: [[TMP6:%.*]] = load <2 x i32>, ptr getelementptr inbounds nuw (i8, ptr @st, i64 8), align 8 +; CHECK-NEXT: [[TMP7:%.*]] = sub <2 x i32> [[TMP6]], [[TMP4]] +; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i32> [[TMP6]], [[TMP4]] +; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> [[TMP8]], <2 x i32> +; CHECK-NEXT: store <2 x i32> [[TMP9]], ptr getelementptr inbounds nuw (i8, ptr @st, i64 8), align 8 +; CHECK-NEXT: [[SUB120_3:%.*]] = or i32 [[TMP5]], [[DOTNEG_NEG]] +; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> , i32 [[TMP0]], i32 1 +; CHECK-NEXT: [[TMP11:%.*]] = shl <4 x i32> [[TMP10]], +; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i32> poison, i32 [[ADD110]], i32 0 +; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i32> [[TMP12]], i32 [[DOTNEG_NEG]], i32 1 +; CHECK-NEXT: [[TMP14:%.*]] = sub <2 x i32> zeroinitializer, [[TMP13]] +; CHECK-NEXT: store <2 x i32> [[TMP14]], ptr getelementptr inbounds nuw (i8, ptr @st, i64 32), align 16 +; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> , <4 x i32> +; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i32> [[TMP15]], i32 [[SUB120_3]], i32 3 +; CHECK-NEXT: [[TMP17:%.*]] = shl <4 x i32> [[TMP16]], [[TMP11]] +; CHECK-NEXT: [[TMP18:%.*]] = sub <4 x i32> [[TMP16]], [[TMP11]] +; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> [[TMP18]], <4 x i32> +; CHECK-NEXT: store <4 x i32> [[TMP19]], ptr getelementptr inbounds nuw (i8, ptr @st, i64 16), align 16 +; CHECK-NEXT: ret i32 0 +; +entry: + %add110 = add i32 %0, %1 + %sub124 = sub i32 0, %add110 + store i32 %sub124, ptr getelementptr inbounds nuw (i8, ptr @st, i64 32), align 16 + %shl127 = shl i32 %0, 1 + store i32 %shl127, ptr getelementptr inbounds nuw (i8, ptr @st, i64 16), align 16 + %shl.2 = shl i32 %0, 1 + %sub124.1 = sub i32 0, %shl.2 + store i32 %sub124.1, ptr getelementptr inbounds nuw (i8, ptr @st, i64 36), align 4 + %sub115.1 = sub i32 0, %shl.2 + store i32 %sub115.1, ptr getelementptr inbounds nuw (i8, ptr @st, i64 20), align 4 + %2 = load i32, ptr getelementptr inbounds nuw (i8, ptr @st, i64 8), align 8 + %add105.2 = sub i32 %2, %0 + store i32 %add105.2, ptr getelementptr inbounds nuw (i8, ptr @st, i64 8), align 8 + %shl127.2 = shl i32 %0, 1 + store i32 %shl127.2, ptr getelementptr inbounds nuw (i8, ptr @st, i64 24), align 8 + %.neg.neg = shl i32 %0, 1 + %3 = load i32, ptr getelementptr inbounds nuw (i8, ptr @st, i64 12), align 4 + %add105.3 = add i32 %.neg.neg, %3 + store i32 %add105.3, ptr getelementptr inbounds nuw (i8, ptr @st, i64 12), align 4 + %sub120.3 = or i32 %3, %.neg.neg + %shl127.3 = shl i32 %sub120.3, 1 + store i32 %shl127.3, ptr getelementptr inbounds nuw (i8, ptr @st, i64 28), align 4 + ret i32 0 +} + +define i32 @test1(ptr %0, ptr %1, i32 %2) { +; CHECK-LABEL: define i32 @test1( +; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: [[ADD53_1:%.*]] = add i32 [[TMP4]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> , i32 [[ADD53_1]], i32 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i32 1 +; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> [[TMP6]], i32 [[TMP3]], i32 0 +; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i32> [[TMP7]], splat (i32 1) +; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> [[TMP8]], <2 x i32> +; CHECK-NEXT: [[TMP10:%.*]] = sub <2 x i32> [[TMP5]], [[TMP9]] +; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP10]], i32 1 +; CHECK-NEXT: [[SHL_1:%.*]] = shl i32 [[TMP11]], 1 +; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i32> poison, i32 [[ADD53_1]], i32 0 +; CHECK-NEXT: [[TMP13:%.*]] = insertelement <2 x i32> [[TMP12]], i32 [[SHL_1]], i32 1 +; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP8]], [[TMP13]] +; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> , <2 x i32> +; CHECK-NEXT: [[TMP16:%.*]] = add <2 x i32> [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP17:%.*]] = or <2 x i32> [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <2 x i32> [[TMP16]], <2 x i32> [[TMP17]], <2 x i32> +; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i32> [[TMP10]], i32 0 +; CHECK-NEXT: store i32 [[TMP19]], ptr @st, align 8 +; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <2 x i32> [[TMP18]], <2 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP22:%.*]] = shufflevector <4 x i32> [[TMP20]], <4 x i32> [[TMP21]], <4 x i32> +; CHECK-NEXT: [[TMP23:%.*]] = or <4 x i32> [[TMP22]], splat (i32 1) +; CHECK-NEXT: store <4 x i32> [[TMP23]], ptr getelementptr inbounds nuw (i8, ptr @st, i64 16), align 16 +; CHECK-NEXT: ret i32 0 +; +entry: + %3 = load i32, ptr %0, align 8 + %4 = load i32, ptr %1, align 4 + %sub80.1 = sub i32 0, %2 + %add62.1 = add i32 %3, 1 + %add53.1 = add i32 %4, %2 + %add81.1 = or i32 %add62.1, %add53.1 + %sub115 = add i32 %add81.1, 1 + %add128 = or i32 %sub115, 1 + store i32 %add128, ptr getelementptr inbounds nuw (i8, ptr @st, i64 16), align 16 + %sub71.11 = add i32 %2, 1 + %shl.1 = shl i32 %sub80.1, 1 + %add89.1 = or i32 %sub71.11, %shl.1 + %sub115.1 = or i32 %add89.1, %2 + %add128.1 = or i32 %sub115.1, 1 + store i32 %add128.1, ptr getelementptr inbounds nuw (i8, ptr @st, i64 20), align 4 + %sub85.1 = sub i32 %add53.1, %add62.1 + store i32 %sub85.1, ptr @st, align 8 + %add128.2 = or i32 %sub85.1, 1 + store i32 %add128.2, ptr getelementptr inbounds nuw (i8, ptr @st, i64 24), align 8 + %sub94.1 = or i32 %sub80.1, 1 + store i32 %sub94.1, ptr getelementptr inbounds nuw (i8, ptr @st, i64 28), align 4 + ret i32 0 +} + +define i32 @test2(i32 %0) { +; CHECK-LABEL: define i32 @test2( +; CHECK-SAME: i32 [[TMP0:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[ENTRY:.*:]] +; CHECK-NEXT: [[ADD110_3:%.*]] = add i32 [[TMP0]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> , i32 [[TMP0]], i32 1 +; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> splat (i32 1), [[TMP1]] +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> +; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> [[TMP5]], <2 x i32> +; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i32> [[TMP8]], +; CHECK-NEXT: [[TMP10:%.*]] = shl <2 x i32> [[TMP9]], splat (i32 1) +; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x i32> [[TMP10]], i32 1 +; CHECK-NEXT: store i32 [[TMP11]], ptr getelementptr inbounds nuw (i8, ptr @st, i64 20), align 4 +; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> , i32 [[TMP0]], i32 2 +; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[TMP10]], <2 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP12]], <4 x i32> [[TMP13]], <4 x i32> +; CHECK-NEXT: [[TMP15:%.*]] = insertelement <4 x i32> [[TMP14]], i32 [[ADD110_3]], i32 3 +; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> [[TMP16]], <4 x i32> +; CHECK-NEXT: [[TMP18:%.*]] = sub <4 x i32> [[TMP15]], [[TMP17]] +; CHECK-NEXT: [[TMP19:%.*]] = add <4 x i32> [[TMP15]], [[TMP17]] +; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <4 x i32> [[TMP18]], <4 x i32> [[TMP19]], <4 x i32> +; CHECK-NEXT: store <4 x i32> [[TMP20]], ptr @st, align 4 +; CHECK-NEXT: ret i32 0 +; +entry: + %sub80.3 = or i32 %0, 1 + %add110.3 = add i32 %0, 1 + %add110.2 = or i32 %0, 1 + %shl.1 = shl i32 %0, 1 + store i32 %shl.1, ptr getelementptr inbounds nuw (i8, ptr @st, i64 20), align 4 + %add105.3 = add i32 %sub80.3, %0 + %shl.3 = shl i32 %sub80.3, 1 + %add121.3 = add i32 %add110.3, %add105.3 + %add121.2 = add i32 %add110.2, %0 + %add121.1 = add i32 %shl.1, %shl.3 + %sub120.1 = sub i32 0, %shl.3 + %1 = insertelement <4 x i32> poison, i32 %sub120.1, i32 0 + %2 = insertelement <4 x i32> %1, i32 %add121.1, i32 1 + %3 = insertelement <4 x i32> %2, i32 %add121.2, i32 2 + %4 = insertelement <4 x i32> %3, i32 %add121.3, i32 3 + store <4 x i32> %4, ptr @st, align 4 + ret i32 0 +} + diff --git a/llvm/test/Transforms/SROA/basictest.ll b/llvm/test/Transforms/SROA/basictest.ll index 15803f7b5a25b..1d2a00e7f2380 100644 --- a/llvm/test/Transforms/SROA/basictest.ll +++ b/llvm/test/Transforms/SROA/basictest.ll @@ -529,7 +529,6 @@ entry: define ptr @test10() { ; CHECK-LABEL: @test10( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr null to i64 ; CHECK-NEXT: ret ptr null ; entry: @@ -1083,20 +1082,19 @@ define void @PR14059.1(ptr %d) { ; CHECK-NEXT: [[X_SROA_0_I_2_INSERT_MASK:%.*]] = and i64 [[TMP2]], -281474976645121 ; CHECK-NEXT: [[X_SROA_0_I_2_INSERT_INSERT:%.*]] = or i64 [[X_SROA_0_I_2_INSERT_MASK]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast i64 [[X_SROA_0_I_2_INSERT_INSERT]] to double -; CHECK-NEXT: [[TMP4:%.*]] = bitcast double [[TMP3]] to i64 ; CHECK-NEXT: [[X_SROA_0_I_4_COPYLOAD:%.*]] = load i32, ptr [[D:%.*]], align 1 -; CHECK-NEXT: [[TMP5:%.*]] = bitcast double 0.000000e+00 to i64 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast double 0.000000e+00 to i64 ; CHECK-NEXT: [[X_SROA_0_I_4_INSERT_EXT:%.*]] = zext i32 [[X_SROA_0_I_4_COPYLOAD]] to i64 ; CHECK-NEXT: [[X_SROA_0_I_4_INSERT_SHIFT:%.*]] = shl i64 [[X_SROA_0_I_4_INSERT_EXT]], 32 -; CHECK-NEXT: [[X_SROA_0_I_4_INSERT_MASK3:%.*]] = and i64 [[TMP5]], 4294967295 +; CHECK-NEXT: [[X_SROA_0_I_4_INSERT_MASK3:%.*]] = and i64 [[TMP4]], 4294967295 ; CHECK-NEXT: [[X_SROA_0_I_4_INSERT_INSERT4:%.*]] = or i64 [[X_SROA_0_I_4_INSERT_MASK3]], [[X_SROA_0_I_4_INSERT_SHIFT]] -; CHECK-NEXT: [[TMP6:%.*]] = bitcast i64 [[X_SROA_0_I_4_INSERT_INSERT4]] to double -; CHECK-NEXT: [[TMP7:%.*]] = bitcast double [[TMP6]] to i64 -; CHECK-NEXT: [[X_SROA_0_I_4_INSERT_MASK:%.*]] = and i64 [[TMP7]], 4294967295 +; CHECK-NEXT: [[TMP5:%.*]] = bitcast i64 [[X_SROA_0_I_4_INSERT_INSERT4]] to double +; CHECK-NEXT: [[TMP6:%.*]] = bitcast double [[TMP5]] to i64 +; CHECK-NEXT: [[X_SROA_0_I_4_INSERT_MASK:%.*]] = and i64 [[TMP6]], 4294967295 ; CHECK-NEXT: [[X_SROA_0_I_4_INSERT_INSERT:%.*]] = or i64 [[X_SROA_0_I_4_INSERT_MASK]], 4607182418800017408 -; CHECK-NEXT: [[TMP8:%.*]] = bitcast i64 [[X_SROA_0_I_4_INSERT_INSERT]] to double +; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64 [[X_SROA_0_I_4_INSERT_INSERT]] to double ; CHECK-NEXT: [[ACCUM_REAL_I:%.*]] = load double, ptr [[D]], align 8 -; CHECK-NEXT: [[ADD_R_I:%.*]] = fadd double [[ACCUM_REAL_I]], [[TMP8]] +; CHECK-NEXT: [[ADD_R_I:%.*]] = fadd double [[ACCUM_REAL_I]], [[TMP7]] ; CHECK-NEXT: store double [[ADD_R_I]], ptr [[D]], align 8 ; CHECK-NEXT: ret void ; diff --git a/llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll b/llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll index 72014912edd20..197c8e6908ae3 100644 --- a/llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll +++ b/llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll @@ -249,8 +249,6 @@ define amdgpu_kernel void @test_half_array() #0 { ; CHECK-NEXT: [[B_BLOCKWISE_COPY_SROA_4:%.*]] = alloca float, align 4 ; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 16 [[B_BLOCKWISE_COPY_SROA_0]], i8 0, i32 4, i1 false) ; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[B_BLOCKWISE_COPY_SROA_4]], i8 0, i32 4, i1 false) -; CHECK-NEXT: [[TMP0:%.*]] = bitcast float undef to i32 -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float undef to i32 ; CHECK-NEXT: [[DATA:%.*]] = load [4 x float], ptr undef, align 4 ; CHECK-NEXT: [[DATA_FCA_0_EXTRACT:%.*]] = extractvalue [4 x float] [[DATA]], 0 ; CHECK-NEXT: store float [[DATA_FCA_0_EXTRACT]], ptr [[B_BLOCKWISE_COPY_SROA_0]], align 16 diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll deleted file mode 100644 index 056f33e5ee367..0000000000000 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/xor-decompose.ll +++ /dev/null @@ -1,435 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; Test the xor with constant operand is decomposed in to gep. -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep \ -; RUN: -S < %s | FileCheck %s -; Test the gvn pass eliminates the redundant xor instructions from decomposition. -; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=separate-const-offset-from-gep,gvn \ -; RUN: -S < %s | FileCheck --check-prefix=GVN %s - -; Check that disjoint constants are properly extracted and folded into GEP -; addressing modes and GVN to eliminate redundant computations -define amdgpu_kernel void @test1(i1 %0, ptr addrspace(3) %1) { -; CHECK-LABEL: define amdgpu_kernel void @test1( -; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 8192 -; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP9:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP8]] -; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP9]], i32 16384 -; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP12:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP11]] -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP12]], i32 24576 -; CHECK-NEXT: [[TMP14:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 -; CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 -; CHECK-NEXT: [[TMP16:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP10]], align 16 -; CHECK-NEXT: [[TMP17:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP13]], align 16 -; CHECK-NEXT: [[TMP18:%.*]] = fadd <8 x half> [[TMP14]], [[TMP15]] -; CHECK-NEXT: [[TMP19:%.*]] = fadd <8 x half> [[TMP16]], [[TMP17]] -; CHECK-NEXT: [[TMP20:%.*]] = fadd <8 x half> [[TMP18]], [[TMP19]] -; CHECK-NEXT: store <8 x half> [[TMP20]], ptr addrspace(3) [[TMP1]], align 16 -; CHECK-NEXT: ret void -; -; GVN-LABEL: define amdgpu_kernel void @test1( -; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; GVN-NEXT: [[ENTRY:.*:]] -; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; GVN-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192 -; GVN-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 16384 -; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 24576 -; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 -; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 -; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 -; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] -; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP10]], [[TMP11]] -; GVN-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP12]], [[TMP13]] -; GVN-NEXT: store <8 x half> [[TMP14]], ptr addrspace(3) [[TMP1]], align 16 -; GVN-NEXT: ret void -; -entry: - %2 = select i1 %0, i32 0, i32 288 - %3 = xor i32 %2, 32 - %4 = xor i32 %2, 4128 - %5 = xor i32 %2, 8224 - %6 = xor i32 %2, 12320 - %7 = getelementptr half, ptr addrspace(3) %1, i32 %3 - %8 = getelementptr half, ptr addrspace(3) %1, i32 %4 - %9 = getelementptr half, ptr addrspace(3) %1, i32 %5 - %10 = getelementptr half, ptr addrspace(3) %1, i32 %6 - %11 = load <8 x half>, ptr addrspace(3) %7, align 16 - %12 = load <8 x half>, ptr addrspace(3) %8, align 16 - %13 = load <8 x half>, ptr addrspace(3) %9, align 16 - %14 = load <8 x half>, ptr addrspace(3) %10, align 16 - %15 = fadd <8 x half> %11, %12 - %16 = fadd <8 x half> %13, %14 - %17 = fadd <8 x half> %15, %16 - store <8 x half> %17, ptr addrspace(3) %1, align 16 - ret void -} - -; Check that disjoint constants are properly extracted and folded into GEP -; addressing modes and GVN to eliminate redundant computations -define amdgpu_kernel void @test2(i1 %0, ptr addrspace(3) %1) { -; CHECK-LABEL: define amdgpu_kernel void @test2( -; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP5]], i32 24576 -; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP8:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP8]], i32 16384 -; CHECK-NEXT: [[TMP10:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP11:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP11]], i32 8192 -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; CHECK-NEXT: [[TMP14:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; CHECK-NEXT: [[TMP15:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP9]], align 16 -; CHECK-NEXT: [[TMP16:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP12]], align 16 -; CHECK-NEXT: [[TMP17:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP13]], align 16 -; CHECK-NEXT: [[TMP18:%.*]] = fadd <8 x half> [[TMP14]], [[TMP15]] -; CHECK-NEXT: [[TMP19:%.*]] = fadd <8 x half> [[TMP16]], [[TMP17]] -; CHECK-NEXT: [[TMP20:%.*]] = fadd <8 x half> [[TMP18]], [[TMP19]] -; CHECK-NEXT: store <8 x half> [[TMP20]], ptr addrspace(3) [[TMP1]], align 16 -; CHECK-NEXT: ret void -; -; GVN-LABEL: define amdgpu_kernel void @test2( -; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; GVN-NEXT: [[ENTRY:.*:]] -; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; GVN-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 24576 -; GVN-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 16384 -; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192 -; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 -; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 -; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 -; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] -; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP10]], [[TMP11]] -; GVN-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP12]], [[TMP13]] -; GVN-NEXT: store <8 x half> [[TMP14]], ptr addrspace(3) [[TMP1]], align 16 -; GVN-NEXT: ret void -; -entry: - %2 = select i1 %0, i32 0, i32 288 - %3 = xor i32 %2, 12320 - %4 = xor i32 %2, 8224 - %5 = xor i32 %2, 4128 - %6 = xor i32 %2, 32 - %7 = getelementptr half, ptr addrspace(3) %1, i32 %3 - %8 = getelementptr half, ptr addrspace(3) %1, i32 %4 - %9 = getelementptr half, ptr addrspace(3) %1, i32 %5 - %10 = getelementptr half, ptr addrspace(3) %1, i32 %6 - %11 = load <8 x half>, ptr addrspace(3) %7, align 16 - %12 = load <8 x half>, ptr addrspace(3) %8, align 16 - %13 = load <8 x half>, ptr addrspace(3) %9, align 16 - %14 = load <8 x half>, ptr addrspace(3) %10, align 16 - %15 = fadd <8 x half> %11, %12 - %16 = fadd <8 x half> %13, %14 - %17 = fadd <8 x half> %15, %16 - store <8 x half> %17, ptr addrspace(3) %1, align 16 - ret void -} - -; Verify that xor instructions with different non-disjoint constants are optimized -define amdgpu_kernel void @test3(i1 %0, ptr addrspace(3) %1) { -; CHECK-LABEL: define amdgpu_kernel void @test3( -; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 288 -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 4096 -; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP9:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP8]] -; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP9]], i32 8192 -; CHECK-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 -; CHECK-NEXT: [[TMP12:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 -; CHECK-NEXT: [[TMP13:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP10]], align 16 -; CHECK-NEXT: [[TMP14:%.*]] = fadd <8 x half> [[TMP11]], [[TMP12]] -; CHECK-NEXT: [[TMP15:%.*]] = fadd <8 x half> [[TMP13]], [[TMP14]] -; CHECK-NEXT: store <8 x half> [[TMP15]], ptr addrspace(3) [[TMP1]], align 16 -; CHECK-NEXT: ret void -; -; GVN-LABEL: define amdgpu_kernel void @test3( -; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; GVN-NEXT: [[ENTRY:.*:]] -; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; GVN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 288 -; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] -; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 4096 -; GVN-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP4]], i32 8192 -; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 -; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 -; GVN-NEXT: [[TMP11:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16 -; GVN-NEXT: [[TMP12:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]] -; GVN-NEXT: [[TMP13:%.*]] = fadd <8 x half> [[TMP11]], [[TMP12]] -; GVN-NEXT: store <8 x half> [[TMP13]], ptr addrspace(3) [[TMP1]], align 16 -; GVN-NEXT: ret void -; -entry: - %2 = select i1 %0, i32 0, i32 288 - %3 = xor i32 %2, 32 - %4 = xor i32 %2, 2336 - %5 = xor i32 %2, 4128 - %6 = getelementptr half, ptr addrspace(3) %1, i32 %3 - %7 = getelementptr half, ptr addrspace(3) %1, i32 %4 - %8 = getelementptr half, ptr addrspace(3) %1, i32 %5 - %9 = load <8 x half>, ptr addrspace(3) %6, align 16 - %10 = load <8 x half>, ptr addrspace(3) %7, align 16 - %11 = load <8 x half>, ptr addrspace(3) %8, align 16 - %12 = fadd <8 x half> %9, %10 - %13 = fadd <8 x half> %11, %12 - store <8 x half> %13, ptr addrspace(3) %1, align 16 - ret void -} - -; Verify that no optimization occurs when disjoint constants are absent -define amdgpu_kernel void @test4(i1 %0, ptr addrspace(3) %1) { -; CHECK-LABEL: define amdgpu_kernel void @test4( -; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 288 -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] -; CHECK-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 -; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]] -; CHECK-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16 -; CHECK-NEXT: ret void -; -; GVN-LABEL: define amdgpu_kernel void @test4( -; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; GVN-NEXT: [[ENTRY:.*:]] -; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; GVN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 288 -; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] -; GVN-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 -; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; GVN-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]] -; GVN-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16 -; GVN-NEXT: ret void -; -entry: - %2 = select i1 %0, i32 0, i32 288 - %3 = xor i32 %2, 32 - %4 = xor i32 %2, 288 - %5 = getelementptr half, ptr addrspace(3) %1, i32 %3 - %6 = getelementptr half, ptr addrspace(3) %1, i32 %4 - %7 = load <8 x half>, ptr addrspace(3) %5, align 16 - %8 = load <8 x half>, ptr addrspace(3) %6, align 16 - %9 = fadd <8 x half> %7, %8 - store <8 x half> %9, ptr addrspace(3) %1, align 16 - ret void -} - - -; Verify that XOR-BinOp-GEP usage chains are properly optimized -define amdgpu_kernel void @test5(i1 %0, ptr addrspace(3) %1) { -; CHECK-LABEL: define amdgpu_kernel void @test5( -; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 256 -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192 -; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 -; CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16 -; CHECK-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]] -; CHECK-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16 -; CHECK-NEXT: ret void -; -; GVN-LABEL: define amdgpu_kernel void @test5( -; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; GVN-NEXT: [[ENTRY:.*:]] -; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; GVN-NEXT: [[TMP4:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; GVN-NEXT: [[TMP5:%.*]] = add i32 [[TMP3]], 256 -; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] -; GVN-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP6]], i32 8192 -; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP4]], align 16 -; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 -; GVN-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] -; GVN-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16 -; GVN-NEXT: ret void -; -entry: - %2 = select i1 %0, i32 0, i32 288 - %3 = xor i32 %2, 32 - %4 = xor i32 %2, 4128 - %5 = add i32 %4, 256 - %6 = getelementptr half, ptr addrspace(3) %1, i32 %3 - %7 = getelementptr half, ptr addrspace(3) %1, i32 %5 - %8 = load <8 x half>, ptr addrspace(3) %6, align 16 - %9 = load <8 x half>, ptr addrspace(3) %7, align 16 - %10 = fadd <8 x half> %8, %9 - store <8 x half> %10, ptr addrspace(3) %1, align 16 - ret void -} - -; Verify that BinOp-XOR-GEP usage chains are properly optimized. -; In the below test, make sure we stop processing the chain at xor -; and not fold the constant from add instruction in to gep. The -; constant from add can be folded and the future work will cover -; these cases. -define amdgpu_kernel void @test6(i1 %0, ptr addrspace(3) %1) { -; CHECK-LABEL: define amdgpu_kernel void @test6( -; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256 -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], 32 -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192 -; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 -; CHECK-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16 -; CHECK-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]] -; CHECK-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16 -; CHECK-NEXT: ret void -; -; GVN-LABEL: define amdgpu_kernel void @test6( -; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; GVN-NEXT: [[ENTRY:.*:]] -; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; GVN-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256 -; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; GVN-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], 32 -; GVN-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP6]] -; GVN-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr addrspace(3) [[TMP7]], i32 8192 -; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 -; GVN-NEXT: [[TMP10:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP8]], align 16 -; GVN-NEXT: [[TMP11:%.*]] = fadd <8 x half> [[TMP9]], [[TMP10]] -; GVN-NEXT: store <8 x half> [[TMP11]], ptr addrspace(3) [[TMP1]], align 16 -; GVN-NEXT: ret void -; -entry: - %2 = select i1 %0, i32 0, i32 288 - %3 = xor i32 %2, 32 - %4 = add i32 %2, 256 - %5 = xor i32 %4, 4128 - %6 = getelementptr half, ptr addrspace(3) %1, i32 %3 - %7 = getelementptr half, ptr addrspace(3) %1, i32 %5 - %8 = load <8 x half>, ptr addrspace(3) %6, align 16 - %9 = load <8 x half>, ptr addrspace(3) %7, align 16 - %10 = fadd <8 x half> %8, %9 - store <8 x half> %10, ptr addrspace(3) %1, align 16 - ret void -} - -; Verify that BinOp-XOR-GEP usage chains with non disjoint xor works as -; intended. -define amdgpu_kernel void @test6a(i1 %0, ptr addrspace(3) %1) { -; CHECK-LABEL: define amdgpu_kernel void @test6a( -; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256 -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 288 -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; CHECK-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 -; CHECK-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] -; CHECK-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16 -; CHECK-NEXT: ret void -; -; GVN-LABEL: define amdgpu_kernel void @test6a( -; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; GVN-NEXT: [[ENTRY:.*:]] -; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; GVN-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], 256 -; GVN-NEXT: [[TMP5:%.*]] = xor i32 [[TMP4]], 288 -; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; GVN-NEXT: [[TMP7:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP5]] -; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; GVN-NEXT: [[TMP9:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP7]], align 16 -; GVN-NEXT: [[TMP10:%.*]] = fadd <8 x half> [[TMP8]], [[TMP9]] -; GVN-NEXT: store <8 x half> [[TMP10]], ptr addrspace(3) [[TMP1]], align 16 -; GVN-NEXT: ret void -; -entry: - %2 = select i1 %0, i32 0, i32 288 - %3 = xor i32 %2, 32 - %4 = add i32 %2, 256 - %5 = xor i32 %4, 288 - %6 = getelementptr half, ptr addrspace(3) %1, i32 %3 - %7 = getelementptr half, ptr addrspace(3) %1, i32 %5 - %8 = load <8 x half>, ptr addrspace(3) %6, align 16 - %9 = load <8 x half>, ptr addrspace(3) %7, align 16 - %10 = fadd <8 x half> %8, %9 - store <8 x half> %10, ptr addrspace(3) %1, align 16 - ret void -} - -; Ensure disjoint constants exceeding addressing mode limits (e.g., 32768) are -; not extracted -define amdgpu_kernel void @test7(i1 %0, ptr addrspace(3) %1) { -; CHECK-LABEL: define amdgpu_kernel void @test7( -; CHECK-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32800 -; CHECK-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] -; CHECK-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 -; CHECK-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; CHECK-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]] -; CHECK-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16 -; CHECK-NEXT: ret void -; -; GVN-LABEL: define amdgpu_kernel void @test7( -; GVN-SAME: i1 [[TMP0:%.*]], ptr addrspace(3) [[TMP1:%.*]]) { -; GVN-NEXT: [[ENTRY:.*:]] -; GVN-NEXT: [[TMP2:%.*]] = select i1 [[TMP0]], i32 0, i32 288 -; GVN-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], 32 -; GVN-NEXT: [[TMP4:%.*]] = xor i32 [[TMP2]], 32800 -; GVN-NEXT: [[TMP5:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP3]] -; GVN-NEXT: [[TMP6:%.*]] = getelementptr half, ptr addrspace(3) [[TMP1]], i32 [[TMP4]] -; GVN-NEXT: [[TMP7:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP5]], align 16 -; GVN-NEXT: [[TMP8:%.*]] = load <8 x half>, ptr addrspace(3) [[TMP6]], align 16 -; GVN-NEXT: [[TMP9:%.*]] = fadd <8 x half> [[TMP7]], [[TMP8]] -; GVN-NEXT: store <8 x half> [[TMP9]], ptr addrspace(3) [[TMP1]], align 16 -; GVN-NEXT: ret void -; -entry: - %2 = select i1 %0, i32 0, i32 288 - %3 = xor i32 %2, 32 - %4 = xor i32 %2, 32800 - %5 = getelementptr half, ptr addrspace(3) %1, i32 %3 - %6 = getelementptr half, ptr addrspace(3) %1, i32 %4 - %7 = load <8 x half>, ptr addrspace(3) %5, align 16 - %8 = load <8 x half>, ptr addrspace(3) %6, align 16 - %9 = fadd <8 x half> %7, %8 - store <8 x half> %9, ptr addrspace(3) %1, align 16 - ret void -} - diff --git a/llvm/test/Transforms/SeparateConstOffsetFromGEP/negative-i32-offset.ll b/llvm/test/Transforms/SeparateConstOffsetFromGEP/negative-i32-offset.ll index 77a99516ceb2a..4ba033d2f5440 100644 --- a/llvm/test/Transforms/SeparateConstOffsetFromGEP/negative-i32-offset.ll +++ b/llvm/test/Transforms/SeparateConstOffsetFromGEP/negative-i32-offset.ll @@ -32,9 +32,8 @@ define ptr @test_overflow(ptr %p, i32 %a) { define ptr @test_xor_overflow(ptr %p, i32 range(i32 0, -2147483648) %a) { ; CHECK-LABEL: define ptr @test_xor_overflow( ; CHECK-SAME: ptr [[P:%.*]], i32 range(i32 0, -2147483648) [[A:%.*]]) { -; CHECK-NEXT: [[XOR1:%.*]] = xor i32 [[A]], 2147483647 -; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[XOR1]], 2 -; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[P]], i32 [[TMP1]] +; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], -1 +; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr inbounds i32, ptr [[P]], i32 [[XOR]] ; CHECK-NEXT: ret ptr [[UGLYGEP]] ; %xor = xor i32 %a, -1 diff --git a/llvm/test/Transforms/VectorCombine/AArch64/fold-equivalent-reduction-cmp.ll b/llvm/test/Transforms/VectorCombine/AArch64/fold-equivalent-reduction-cmp.ll index 9ebc2c0c892a8..26d7647e5afde 100644 --- a/llvm/test/Transforms/VectorCombine/AArch64/fold-equivalent-reduction-cmp.ll +++ b/llvm/test/Transforms/VectorCombine/AArch64/fold-equivalent-reduction-cmp.ll @@ -339,4 +339,78 @@ define i1 @or_eq_0_scalable_negative( %x) { ret i1 %cmp } +; i1 vector tests - for i1, or===umax and and===umin + +define i1 @or_eq_0_v4i1(<4 x i1> %x) { +; CHECK-LABEL: define i1 @or_eq_0_v4i1( +; CHECK-SAME: <4 x i1> [[X:%.*]]) { +; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[X]]) +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i1 [[RED]], false +; CHECK-NEXT: ret i1 [[CMP]] +; + %red = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x) + %cmp = icmp eq i1 %red, 0 + ret i1 %cmp +} + +define i1 @or_ne_0_v4i1(<4 x i1> %x) { +; CHECK-LABEL: define i1 @or_ne_0_v4i1( +; CHECK-SAME: <4 x i1> [[X:%.*]]) { +; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[X]]) +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i1 [[RED]], false +; CHECK-NEXT: ret i1 [[CMP]] +; + %red = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x) + %cmp = icmp ne i1 %red, 0 + ret i1 %cmp +} + +define i1 @and_eq_allones_v4i1(<4 x i1> %x) { +; CHECK-LABEL: define i1 @and_eq_allones_v4i1( +; CHECK-SAME: <4 x i1> [[X:%.*]]) { +; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[X]]) +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i1 [[RED]], true +; CHECK-NEXT: ret i1 [[CMP]] +; + %red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x) + %cmp = icmp eq i1 %red, -1 + ret i1 %cmp +} + +define i1 @and_ne_allones_v4i1(<4 x i1> %x) { +; CHECK-LABEL: define i1 @and_ne_allones_v4i1( +; CHECK-SAME: <4 x i1> [[X:%.*]]) { +; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[X]]) +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i1 [[RED]], true +; CHECK-NEXT: ret i1 [[CMP]] +; + %red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x) + %cmp = icmp ne i1 %red, -1 + ret i1 %cmp +} + +define i1 @umax_eq_0_v4i1(<4 x i1> %x) { +; CHECK-LABEL: define i1 @umax_eq_0_v4i1( +; CHECK-SAME: <4 x i1> [[X:%.*]]) { +; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> [[X]]) +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i1 [[RED]], false +; CHECK-NEXT: ret i1 [[CMP]] +; + %red = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %x) + %cmp = icmp eq i1 %red, 0 + ret i1 %cmp +} + +define i1 @umin_eq_allones_v4i1(<4 x i1> %x) { +; CHECK-LABEL: define i1 @umin_eq_allones_v4i1( +; CHECK-SAME: <4 x i1> [[X:%.*]]) { +; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> [[X]]) +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i1 [[RED]], true +; CHECK-NEXT: ret i1 [[CMP]] +; + %red = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> %x) + %cmp = icmp eq i1 %red, -1 + ret i1 %cmp +} + declare void @use(i32) diff --git a/llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll b/llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll index 3a3ba74663b93..5328975f3b00d 100644 --- a/llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll +++ b/llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll @@ -380,10 +380,9 @@ define <4 x i32> @test_recurse(<4 x i32> %l0, <4 x i32> %l1, <4 x i32> %l3) { ; CHECK-LABEL: @test_recurse( ; CHECK-NEXT: [[S0:%.*]] = shufflevector <4 x i32> [[L3:%.*]], <4 x i32> [[L1:%.*]], <4 x i32> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x i32> [[L1]], <4 x i32> [[L3]], <4 x i32> -; CHECK-NEXT: [[S2:%.*]] = shufflevector <4 x i32> [[L0:%.*]], <4 x i32> [[L1]], <4 x i32> -; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[S2]], [[S2]] ; CHECK-NEXT: [[SUB:%.*]] = sub <4 x i32> [[S1]], [[S0]] -; CHECK-NEXT: [[T0:%.*]] = shufflevector <4 x i32> [[ADD]], <4 x i32> [[ADD]], <4 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[L1]], <4 x i32> [[L0:%.*]], <4 x i32> +; CHECK-NEXT: [[T0:%.*]] = add <4 x i32> [[TMP1]], [[TMP1]] ; CHECK-NEXT: ret <4 x i32> [[T0]] ; %s0 = shufflevector <4 x i32> %l3, <4 x i32> %l1, <4 x i32> diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll index 0cceab506bb75..e1e9501968043 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll @@ -197,6 +197,58 @@ define <4 x i32> @shuf_mul_v4i32_yy_use2(<4 x i32> %x, <4 x i32> %y, <4 x i32> % ret <4 x i32> %r } +; Multi-use tests + +define <4 x i32> @shuf_sdiv_v4i32_multiuse_lhs(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { +; CHECK-LABEL: define <4 x i32> @shuf_sdiv_v4i32_multiuse_lhs( +; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[B0:%.*]] = sdiv <4 x i32> [[X]], [[Y]] +; CHECK-NEXT: call void @use(<4 x i32> [[B0]]) +; CHECK-NEXT: [[B1:%.*]] = sdiv <4 x i32> [[Z]], [[Y]] +; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[R]] +; + %b0 = sdiv <4 x i32> %x, %y + call void @use(<4 x i32> %b0) + %b1 = sdiv <4 x i32> %z, %y + %r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> + ret <4 x i32> %r +} + +define <4 x i32> @shuf_sdiv_v4i32_multiuse_rhs(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { +; CHECK-LABEL: define <4 x i32> @shuf_sdiv_v4i32_multiuse_rhs( +; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[B0:%.*]] = sdiv <4 x i32> [[X]], [[Y]] +; CHECK-NEXT: [[B1:%.*]] = sdiv <4 x i32> [[Z]], [[Y]] +; CHECK-NEXT: call void @use(<4 x i32> [[B1]]) +; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[R]] +; + %b0 = sdiv <4 x i32> %x, %y + %b1 = sdiv <4 x i32> %z, %y + call void @use(<4 x i32> %b1) + %r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> + ret <4 x i32> %r +} + +define <4 x i32> @shuf_sdiv_v4i32_multiuse_both(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { +; CHECK-LABEL: define <4 x i32> @shuf_sdiv_v4i32_multiuse_both( +; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[B0:%.*]] = sdiv <4 x i32> [[X]], [[Y]] +; CHECK-NEXT: [[B1:%.*]] = sdiv <4 x i32> [[Z]], [[Y]] +; CHECK-NEXT: call void @use(<4 x i32> [[B0]]) +; CHECK-NEXT: call void @use(<4 x i32> [[B1]]) +; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[R]] +; + %b0 = sdiv <4 x i32> %x, %y + %b1 = sdiv <4 x i32> %z, %y + call void @use(<4 x i32> %b0) + call void @use(<4 x i32> %b1) + %r = shufflevector <4 x i32> %b0, <4 x i32> %b1, <4 x i32> + ret <4 x i32> %r +} + ; non-matching operands (not commutable) define <4 x float> @shuf_fdiv_v4f32_no_common_op(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) { diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll index f9108efa7ee79..30ba7bd6d03d1 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-cmps.ll @@ -248,17 +248,36 @@ define <4 x i32> @shuf_icmp_eq_v4i64_v4i32_mismatch_type(<4 x i64> %x, <4 x i64> ret <4 x i32> %r } -; negative test - uses +; Multi-use test - folding depends on enabled extensions define <4 x i32> @shuf_icmp_ugt_v4i32_use(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) { -; CHECK-LABEL: define <4 x i32> @shuf_icmp_ugt_v4i32_use( -; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]], <4 x i32> [[W:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[C0:%.*]] = icmp ugt <4 x i32> [[X]], [[Y]] -; CHECK-NEXT: [[C1:%.*]] = icmp ugt <4 x i32> [[Z]], [[W]] -; CHECK-NEXT: call void @use(<4 x i1> [[C0]]) -; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i1> [[C0]], <4 x i1> [[C1]], <4 x i32> -; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[S]] to <4 x i32> -; CHECK-NEXT: ret <4 x i32> [[R]] +; SSE-LABEL: define <4 x i32> @shuf_icmp_ugt_v4i32_use( +; SSE-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]], <4 x i32> [[W:%.*]]) #[[ATTR0]] { +; SSE-NEXT: [[C0:%.*]] = icmp ugt <4 x i32> [[X]], [[Y]] +; SSE-NEXT: [[C1:%.*]] = icmp ugt <4 x i32> [[Z]], [[W]] +; SSE-NEXT: call void @use(<4 x i1> [[C0]]) +; SSE-NEXT: [[S:%.*]] = shufflevector <4 x i1> [[C0]], <4 x i1> [[C1]], <4 x i32> +; SSE-NEXT: [[R:%.*]] = sext <4 x i1> [[S]] to <4 x i32> +; SSE-NEXT: ret <4 x i32> [[R]] +; +; AVX2-LABEL: define <4 x i32> @shuf_icmp_ugt_v4i32_use( +; AVX2-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]], <4 x i32> [[W:%.*]]) #[[ATTR0]] { +; AVX2-NEXT: [[C0:%.*]] = icmp ugt <4 x i32> [[X]], [[Y]] +; AVX2-NEXT: [[C1:%.*]] = icmp ugt <4 x i32> [[Z]], [[W]] +; AVX2-NEXT: call void @use(<4 x i1> [[C0]]) +; AVX2-NEXT: [[S:%.*]] = shufflevector <4 x i1> [[C0]], <4 x i1> [[C1]], <4 x i32> +; AVX2-NEXT: [[R:%.*]] = sext <4 x i1> [[S]] to <4 x i32> +; AVX2-NEXT: ret <4 x i32> [[R]] +; +; AVX512-LABEL: define <4 x i32> @shuf_icmp_ugt_v4i32_use( +; AVX512-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]], <4 x i32> [[W:%.*]]) #[[ATTR0]] { +; AVX512-NEXT: [[C0:%.*]] = icmp ugt <4 x i32> [[X]], [[Y]] +; AVX512-NEXT: call void @use(<4 x i1> [[C0]]) +; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> [[Z]], <4 x i32> +; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[Y]], <4 x i32> [[W]], <4 x i32> +; AVX512-NEXT: [[S:%.*]] = icmp ugt <4 x i32> [[TMP1]], [[TMP2]] +; AVX512-NEXT: [[R:%.*]] = sext <4 x i1> [[S]] to <4 x i32> +; AVX512-NEXT: ret <4 x i32> [[R]] ; %c0 = icmp ugt <4 x i32> %x, %y %c1 = icmp ugt <4 x i32> %z, %w diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll index eddfc57a7d256..627b1e341f86c 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll @@ -72,6 +72,39 @@ define <2 x float> @PR86068(<2 x float> %a0, <2 x float> %a1) { %s2 = shufflevector <2 x float> %s1, <2 x float> %a0, <2 x i32> ret <2 x float> %s2 } + +; ensure we don't combine cheap PSHUFB+UNPCK sequence to a costly v32i8 SK_PermuteTwoSrc shuffle. + +define void @PR161980(<4 x i64> %a, <4 x i64> %b, ptr %dst) { +; CHECK-LABEL: define void @PR161980( +; CHECK-SAME: <4 x i64> [[A:%.*]], <4 x i64> [[B:%.*]], ptr [[DST:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[I:%.*]] = bitcast <4 x i64> [[A]] to <32 x i8> +; CHECK-NEXT: [[I1:%.*]] = shufflevector <32 x i8> [[I]], <32 x i8> poison, <32 x i32> +; CHECK-NEXT: [[I2:%.*]] = bitcast <32 x i8> [[I1]] to <4 x i64> +; CHECK-NEXT: [[I3:%.*]] = bitcast <4 x i64> [[B]] to <32 x i8> +; CHECK-NEXT: [[I4:%.*]] = shufflevector <32 x i8> [[I3]], <32 x i8> poison, <32 x i32> +; CHECK-NEXT: [[I5:%.*]] = bitcast <32 x i8> [[I4]] to <4 x i64> +; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i64> [[I2]], <4 x i64> [[I5]], <4 x i32> +; CHECK-NEXT: [[SHUFFLE_I9:%.*]] = shufflevector <4 x i64> [[I2]], <4 x i64> [[I5]], <4 x i32> +; CHECK-NEXT: store <4 x i64> [[SHUFFLE_I]], ptr [[DST]], align 1 +; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds nuw i8, ptr [[DST]], i64 32 +; CHECK-NEXT: store <4 x i64> [[SHUFFLE_I9]], ptr [[ADD_PTR]], align 1 +; CHECK-NEXT: ret void +; + %i = bitcast <4 x i64> %a to <32 x i8> + %i1 = shufflevector <32 x i8> %i, <32 x i8> poison, <32 x i32> + %i2 = bitcast <32 x i8> %i1 to <4 x i64> + %i3 = bitcast <4 x i64> %b to <32 x i8> + %i4 = shufflevector <32 x i8> %i3, <32 x i8> poison, <32 x i32> + %i5 = bitcast <32 x i8> %i4 to <4 x i64> + %shuffle.i = shufflevector <4 x i64> %i2, <4 x i64> %i5, <4 x i32> + %shuffle.i9 = shufflevector <4 x i64> %i2, <4 x i64> %i5, <4 x i32> + store <4 x i64> %shuffle.i, ptr %dst, align 1 + %add.ptr = getelementptr inbounds nuw i8, ptr %dst, i64 32 + store <4 x i64> %shuffle.i9, ptr %add.ptr, align 1 + ret void +} + ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; AVX: {{.*}} ; SSE: {{.*}} diff --git a/llvm/test/Transforms/VectorCombine/load-shufflevector.ll b/llvm/test/Transforms/VectorCombine/load-shufflevector.ll index 55a20d4489723..e7a564d688a2a 100644 --- a/llvm/test/Transforms/VectorCombine/load-shufflevector.ll +++ b/llvm/test/Transforms/VectorCombine/load-shufflevector.ll @@ -47,9 +47,8 @@ define <4 x half> @shuffle_v4_v4f16_r1_2(ptr addrspace(1) nocapture readonly %ar ; CHECK-LABEL: define <4 x half> @shuffle_v4_v4f16_r1_2( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 2 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr addrspace(1) [[TMP0]], align 32 -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x half> [[TMP2]], <2 x half> poison, <4 x i32> +; CHECK-NEXT: [[TMP0:%.*]] = load <3 x half>, ptr addrspace(1) [[ARG0]], align 32 +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x half> [[TMP0]], <3 x half> poison, <4 x i32> ; CHECK-NEXT: ret <4 x half> [[TMP1]] ; entry: @@ -62,9 +61,8 @@ define <8 x half> @shuffle_v4_v8f16_r1_2(ptr addrspace(1) nocapture readonly %ar ; CHECK-LABEL: define <8 x half> @shuffle_v4_v8f16_r1_2( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 2 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x half>, ptr addrspace(1) [[TMP0]], align 32 -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x half> [[TMP2]], <2 x half> poison, <8 x i32> +; CHECK-NEXT: [[TMP0:%.*]] = load <3 x half>, ptr addrspace(1) [[ARG0]], align 32 +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x half> [[TMP0]], <3 x half> poison, <8 x i32> ; CHECK-NEXT: ret <8 x half> [[TMP1]] ; entry: @@ -110,14 +108,13 @@ define <4 x half> @shuffle_v4_v4f16_cond_r1_2(ptr addrspace(1) nocapture readonl ; CHECK-LABEL: define <4 x half> @shuffle_v4_v4f16_cond_r1_2( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]], i1 [[COND:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 2 -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(1) [[TMP0]], align 32 +; CHECK-NEXT: [[TMP0:%.*]] = load <3 x half>, ptr addrspace(1) [[ARG0]], align 32 ; CHECK-NEXT: br i1 [[COND]], label %[[THEN:.*]], label %[[ELSE:.*]] ; CHECK: [[THEN]]: -; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <3 x half> [[TMP0]], <3 x half> poison, <4 x i32> ; CHECK-NEXT: br label %[[FINALLY:.*]] ; CHECK: [[ELSE]]: -; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <4 x i32> +; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <3 x half> [[TMP0]], <3 x half> poison, <4 x i32> ; CHECK-NEXT: br label %[[FINALLY]] ; CHECK: [[FINALLY]]: ; CHECK-NEXT: [[VAL3:%.*]] = phi <4 x half> [ [[VAL1]], %[[THEN]] ], [ [[VAL2]], %[[ELSE]] ] @@ -144,14 +141,13 @@ define <8 x half> @shuffle_v4_v8f16_cond_r1_2(ptr addrspace(1) nocapture readonl ; CHECK-LABEL: define <8 x half> @shuffle_v4_v8f16_cond_r1_2( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]], i1 [[COND:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 2 -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(1) [[TMP0]], align 32 +; CHECK-NEXT: [[TMP0:%.*]] = load <3 x half>, ptr addrspace(1) [[ARG0]], align 32 ; CHECK-NEXT: br i1 [[COND]], label %[[THEN:.*]], label %[[ELSE:.*]] ; CHECK: [[THEN]]: -; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <8 x i32> zeroinitializer +; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <3 x half> [[TMP0]], <3 x half> poison, <8 x i32> ; CHECK-NEXT: br label %[[FINALLY:.*]] ; CHECK: [[ELSE]]: -; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <2 x half> [[TMP1]], <2 x half> poison, <8 x i32> +; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <3 x half> [[TMP0]], <3 x half> poison, <8 x i32> ; CHECK-NEXT: br label %[[FINALLY]] ; CHECK: [[FINALLY]]: ; CHECK-NEXT: [[VAL3:%.*]] = phi <8 x half> [ [[VAL1]], %[[THEN]] ], [ [[VAL2]], %[[ELSE]] ] @@ -206,9 +202,8 @@ define <4 x i32> @shuffle_v4_v4i32_r1_2(ptr addrspace(1) nocapture readonly %arg ; CHECK-LABEL: define <4 x i32> @shuffle_v4_v4i32_r1_2( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 4 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(1) [[TMP0]], align 32 -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr addrspace(1) [[ARG0]], align 32 +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[TMP0]], <3 x i32> poison, <4 x i32> ; CHECK-NEXT: ret <4 x i32> [[TMP1]] ; entry: @@ -221,9 +216,8 @@ define <8 x i32> @shuffle_v4_v8i32_r1_2(ptr addrspace(1) nocapture readonly %arg ; CHECK-LABEL: define <8 x i32> @shuffle_v4_v8i32_r1_2( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 4 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr addrspace(1) [[TMP0]], align 32 -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> +; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr addrspace(1) [[ARG0]], align 32 +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <3 x i32> [[TMP0]], <3 x i32> poison, <8 x i32> ; CHECK-NEXT: ret <8 x i32> [[TMP1]] ; entry: @@ -302,14 +296,13 @@ define <4 x i32> @shuffle_v4_v4i32_cond_r1_2(ptr addrspace(1) nocapture readonly ; CHECK-LABEL: define <4 x i32> @shuffle_v4_v4i32_cond_r1_2( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]], i1 [[COND:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 4 -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[TMP0]], align 32 +; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr addrspace(1) [[ARG0]], align 32 ; CHECK-NEXT: br i1 [[COND]], label %[[THEN:.*]], label %[[ELSE:.*]] ; CHECK: [[THEN]]: -; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <3 x i32> [[TMP0]], <3 x i32> poison, <4 x i32> ; CHECK-NEXT: br label %[[FINALLY:.*]] ; CHECK: [[ELSE]]: -; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <4 x i32> +; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <3 x i32> [[TMP0]], <3 x i32> poison, <4 x i32> ; CHECK-NEXT: br label %[[FINALLY]] ; CHECK: [[FINALLY]]: ; CHECK-NEXT: [[VAL3:%.*]] = phi <4 x i32> [ [[VAL1]], %[[THEN]] ], [ [[VAL2]], %[[ELSE]] ] @@ -336,14 +329,13 @@ define <8 x i32> @shuffle_v4_v8i32_cond_r1_2(ptr addrspace(1) nocapture readonly ; CHECK-LABEL: define <8 x i32> @shuffle_v4_v8i32_cond_r1_2( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]], i1 [[COND:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 4 -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr addrspace(1) [[TMP0]], align 32 +; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr addrspace(1) [[ARG0]], align 32 ; CHECK-NEXT: br i1 [[COND]], label %[[THEN:.*]], label %[[ELSE:.*]] ; CHECK: [[THEN]]: -; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <8 x i32> zeroinitializer +; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <3 x i32> [[TMP0]], <3 x i32> poison, <8 x i32> ; CHECK-NEXT: br label %[[FINALLY:.*]] ; CHECK: [[ELSE]]: -; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <8 x i32> +; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <3 x i32> [[TMP0]], <3 x i32> poison, <8 x i32> ; CHECK-NEXT: br label %[[FINALLY]] ; CHECK: [[FINALLY]]: ; CHECK-NEXT: [[VAL3:%.*]] = phi <8 x i32> [ [[VAL1]], %[[THEN]] ], [ [[VAL2]], %[[ELSE]] ] @@ -370,14 +362,13 @@ define <8 x i32> @shuffle_v4_v8i32_cond_r1_4(ptr addrspace(1) nocapture readonly ; CHECK-LABEL: define <8 x i32> @shuffle_v4_v8i32_cond_r1_4( ; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG0:%.*]], i1 [[COND:%.*]]) local_unnamed_addr { ; CHECK-NEXT: [[ENTRY:.*:]] -; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[ARG0]], i64 4 -; CHECK-NEXT: [[TMP1:%.*]] = load <3 x i32>, ptr addrspace(1) [[TMP0]], align 32 +; CHECK-NEXT: [[VAL0:%.*]] = load <4 x i32>, ptr addrspace(1) [[ARG0]], align 32 ; CHECK-NEXT: br i1 [[COND]], label %[[THEN:.*]], label %[[ELSE:.*]] ; CHECK: [[THEN]]: -; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> poison, <8 x i32> +; CHECK-NEXT: [[VAL1:%.*]] = shufflevector <4 x i32> [[VAL0]], <4 x i32> poison, <8 x i32> ; CHECK-NEXT: br label %[[FINALLY:.*]] ; CHECK: [[ELSE]]: -; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> poison, <8 x i32> +; CHECK-NEXT: [[VAL2:%.*]] = shufflevector <4 x i32> [[VAL0]], <4 x i32> poison, <8 x i32> ; CHECK-NEXT: br label %[[FINALLY]] ; CHECK: [[FINALLY]]: ; CHECK-NEXT: [[VAL3:%.*]] = phi <8 x i32> [ [[VAL1]], %[[THEN]] ], [ [[VAL2]], %[[ELSE]] ] @@ -412,16 +403,18 @@ define <16 x i8> @shuffle_v16_v16i8_r0_31(ptr %arg) { ret <16 x i8> %shuf } -; PR178917: Verify poison mask elements are preserved when trimming loads. -define <8 x i16> @shuffle_with_poison_mask(ptr %p) { -; CHECK-LABEL: define <8 x i16> @shuffle_with_poison_mask( +; Verify that dead shuffle uses (with indices outside the range of used +; shuffles) are properly skipped when shrinking loads. +define <2 x double> @shuffle_with_dead_use(ptr %p) { +; CHECK-LABEL: define <2 x double> @shuffle_with_dead_use( ; CHECK-SAME: ptr [[P:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 2 -; CHECK-NEXT: [[TMP2:%.*]] = load <7 x i16>, ptr [[TMP1]], align 1 -; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <7 x i16> [[TMP2]], <7 x i16> poison, <8 x i32> -; CHECK-NEXT: ret <8 x i16> [[SHUF]] +; CHECK-NEXT: [[LOAD:%.*]] = load <3 x double>, ptr [[P]], align 8 +; CHECK-NEXT: [[SHUF1:%.*]] = shufflevector <3 x double> [[LOAD]], <3 x double> poison, <2 x i32> +; CHECK-NEXT: [[SHUF2:%.*]] = shufflevector <3 x double> [[LOAD]], <3 x double> poison, <2 x i32> +; CHECK-NEXT: ret <2 x double> [[SHUF2]] ; - %pre = load <8 x i16>, ptr %p, align 1 - %shuf = shufflevector <8 x i16> %pre, <8 x i16> poison, <8 x i32> - ret <8 x i16> %shuf + %load = load <3 x double>, ptr %p, align 8 + %shuf1 = shufflevector <3 x double> %load, <3 x double> poison, <2 x i32> + %shuf2 = shufflevector <3 x double> %load, <3 x double> poison, <2 x i32> + ret <2 x double> %shuf2 } diff --git a/llvm/test/Verifier/AMDGPU/intrinsic-sponentry.ll b/llvm/test/Verifier/AMDGPU/intrinsic-sponentry.ll new file mode 100644 index 0000000000000..5986d5f1b7ad4 --- /dev/null +++ b/llvm/test/Verifier/AMDGPU/intrinsic-sponentry.ll @@ -0,0 +1,64 @@ +; RUN: not llvm-as --data-layout="A5" -disable-output %s 2>&1 | FileCheck %s + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr addrspace(0) @p0() { +entry: + %res = tail call ptr addrspace(0) @llvm.sponentry() + ret ptr addrspace(0) %res +} + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr addrspace(1) @p1() { +entry: + %res = tail call ptr addrspace(1) @llvm.sponentry() + ret ptr addrspace(1) %res +} + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr addrspace(2) @p2() { +entry: + %res = tail call ptr addrspace(2) @llvm.sponentry() + ret ptr addrspace(2) %res +} + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr addrspace(3) @p3() { +entry: + %res = tail call ptr addrspace(3) @llvm.sponentry() + ret ptr addrspace(3) %res +} + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr addrspace(4) @p4() { +entry: + %res = tail call ptr addrspace(4) @llvm.sponentry() + ret ptr addrspace(4) %res +} + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr addrspace(6) @p6() { +entry: + %res = tail call ptr addrspace(6) @llvm.sponentry() + ret ptr addrspace(6) %res +} + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr addrspace(7) @p7() { +entry: + %res = tail call ptr addrspace(7) @llvm.sponentry() + ret ptr addrspace(7) %res +} + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr addrspace(8) @p8() { +entry: + %res = tail call ptr addrspace(8) @llvm.sponentry() + ret ptr addrspace(8) %res +} + +; CHECK: llvm.sponentry must return a pointer to the stack +define ptr @no_as() { +entry: + %res = tail call ptr @llvm.sponentry() + ret ptr %res +} diff --git a/llvm/test/Verifier/denormal-fp-math.ll b/llvm/test/Verifier/denormal-fp-math.ll deleted file mode 100644 index f79f28a366944..0000000000000 --- a/llvm/test/Verifier/denormal-fp-math.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck --implicit-check-not="invalid value" %s - -define float @test_denormal_fp_math_valid() "denormal-fp-math"="ieee,ieee" { - ret float 1.0 -} - -; CHECK: invalid value for 'denormal-fp-math' attribute: foo,ieee -define float @test_denormal_fp_math_invalid1() "denormal-fp-math"="foo,ieee" { - ret float 1.0 -} - -; CHECK: invalid value for 'denormal-fp-math' attribute: ieee,ieee,ieee -define float @test_denormal_fp_math_invalid2() "denormal-fp-math"="ieee,ieee,ieee" { - ret float 1.0 -} - -; CHECK: invalid value for 'denormal-fp-math-f32' attribute: foo,ieee -define float @test_denormal_fp_math_f32_invalid() "denormal-fp-math-f32"="foo,ieee" { - ret float 1.0 -} diff --git a/llvm/test/Verifier/denormal_fpenv.ll b/llvm/test/Verifier/denormal_fpenv.ll new file mode 100644 index 0000000000000..0e4ad7c083c11 --- /dev/null +++ b/llvm/test/Verifier/denormal_fpenv.ll @@ -0,0 +1,10 @@ +; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s + +declare void @func() + +; CHECK: denormal_fpenv attribute may not apply to call sites +; CHECK-NEXT: call void @func() #0 +define void @no_callsites() { + call void @func() denormal_fpenv(preservesign) + ret void +} diff --git a/llvm/test/Verifier/issue176674.ll b/llvm/test/Verifier/issue176674.ll new file mode 100644 index 0000000000000..c5221b1bb0cf3 --- /dev/null +++ b/llvm/test/Verifier/issue176674.ll @@ -0,0 +1,9 @@ +; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: %v = call <4 x i32> @llvm.x86.sse2.pshuflw.128(<4 x i32> zeroinitializer, i8 0) +; CHECK: LLVM ERROR: Unexpected intrinsic + +define void @test(ptr %a) { + %v = call <4 x i32> @llvm.x86.sse2.pshuflw.128(<4 x i32> zeroinitializer, i8 0) + store <4 x i32> %v, ptr %a + ret void +} diff --git a/llvm/test/Verifier/issue176674_1.ll b/llvm/test/Verifier/issue176674_1.ll new file mode 100644 index 0000000000000..d5c92aa26bc39 --- /dev/null +++ b/llvm/test/Verifier/issue176674_1.ll @@ -0,0 +1,9 @@ +; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: %v = call <4 x i32> @llvm.x86.sse2.pshufl.w(<4 x i32> zeroinitializer, i8 0) +; CHECK: LLVM ERROR: Intrinsic has invalid signature + +define void @test(ptr %a) { + %v = call <4 x i32> @llvm.x86.sse2.pshufl.w(<4 x i32> zeroinitializer, i8 0) + store <4 x i32> %v, ptr %a + ret void +} diff --git a/llvm/test/Verifier/issue176674_2.ll b/llvm/test/Verifier/issue176674_2.ll new file mode 100644 index 0000000000000..e1c73f5e23e7d --- /dev/null +++ b/llvm/test/Verifier/issue176674_2.ll @@ -0,0 +1,9 @@ +; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: %v = call <4 x i32> @llvm.x86.sse2.pshufh.w(<4 x i32> zeroinitializer, i8 0) +; CHECK: LLVM ERROR: Intrinsic has invalid signature + +define void @test(ptr %a) { + %v = call <4 x i32> @llvm.x86.sse2.pshufh.w(<4 x i32> zeroinitializer, i8 0) + store <4 x i32> %v, ptr %a + ret void +} diff --git a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll new file mode 100644 index 0000000000000..1ef134466cfcf --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll @@ -0,0 +1,16 @@ +; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-width=4 \ +; RUN: -disable-output %s 2>&1 | FileCheck %s + +define void @simple(ptr %p, i64 %n) { +entry: + br label %loop +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr i32, ptr %p, i64 %iv + store i32 0, ptr %gep + %iv.next = add i64 %iv, 1 + %cmp = icmp ult i64 %iv.next, %n + br i1 %cmp, label %loop, label %exit +exit: + ret void +} diff --git a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected new file mode 100644 index 0000000000000..5d0cf220faf75 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/vplan.ll.expected @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py +; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-width=4 \ +; RUN: -disable-output %s 2>&1 | FileCheck %s + +define void @simple(ptr %p, i64 %n) { +; CHECK-LABEL: 'simple' +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { +; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF +; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF +; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count +; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = original trip-count +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: EMIT vp<[[VP3]]> = EXPAND SCEV (1 umax %n) +; CHECK-NEXT: Successor(s): scalar.ph, vector.ph +; CHECK-EMPTY: +; CHECK-NEXT: vector.ph: +; CHECK-NEXT: Successor(s): vector loop +; CHECK-EMPTY: +; CHECK-NEXT: vector loop: { +; CHECK-NEXT: vector.body: +; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = CANONICAL-INDUCTION ir<0>, vp<%index.next> +; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]> +; CHECK-NEXT: CLONE ir<%gep> = getelementptr ir<%p>, vp<[[VP5]]> +; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer ir<%gep> +; CHECK-NEXT: WIDEN store vp<[[VP6]]>, ir<0> +; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP4]]>, vp<[[VP1]]> +; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]> +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; CHECK-NEXT: Successor(s): middle.block +; CHECK-EMPTY: +; CHECK-NEXT: middle.block: +; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP3]]>, vp<[[VP2]]> +; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n> +; CHECK-NEXT: Successor(s): ir-bb, scalar.ph +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: No successors +; CHECK-EMPTY: +; CHECK-NEXT: scalar.ph: +; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP2]]>, middle.block ], [ ir<0>, ir-bb ] +; CHECK-NEXT: Successor(s): ir-bb +; CHECK-EMPTY: +; CHECK-NEXT: ir-bb: +; CHECK-NEXT: IR %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] (extra operand: vp<%bc.resume.val> from scalar.ph) +; CHECK-NEXT: IR %gep = getelementptr i32, ptr %p, i64 %iv +; CHECK-NEXT: IR store i32 0, ptr %gep, align 4 +; CHECK-NEXT: IR %iv.next = add i64 %iv, 1 +; CHECK-NEXT: IR %cmp = icmp ult i64 %iv.next, %n +; CHECK-NEXT: No successors +; CHECK-NEXT: } +; +entry: + br label %loop +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr i32, ptr %p, i64 %iv + store i32 0, ptr %gep + %iv.next = add i64 %iv, 1 + %cmp = icmp ult i64 %iv.next, %n + br i1 %cmp, label %loop, label %exit +exit: + ret void +} diff --git a/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/vplan.test b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/vplan.test new file mode 100644 index 0000000000000..8283e5825b881 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/vplan.test @@ -0,0 +1,8 @@ +# REQUIRES: asserts + +## Basic test checking that update_analyze_test_checks.py works correctly for VPlan output +# RUN: cp -f %S/Inputs/vplan.ll %t.ll && %update_analyze_test_checks %t.ll +# RUN: diff -u %t.ll %S/Inputs/vplan.ll.expected +## Check that running the script again does not change the result: +# RUN: %update_analyze_test_checks %t.ll +# RUN: diff -u %t.ll %S/Inputs/vplan.ll.expected diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected index 88cb03e85204a..8c563d569fbc3 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected @@ -34,7 +34,7 @@ define i64 @test2(i32 %i) nounwind readnone { ; MIR-NEXT: {{ $}} ; MIR-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi ; MIR-NEXT: [[ADD32rm:%[0-9]+]]:gr32 = ADD32rm [[COPY]], %stack.0.loc, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (dereferenceable load (s32) from %ir.loc) -; MIR-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[ADD32rm]], %subreg.sub_32bit +; MIR-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[ADD32rm]], %subreg.sub_32bit ; MIR-NEXT: $rax = COPY [[SUBREG_TO_REG]] ; MIR-NEXT: RET 0, $rax %loc = alloca i32 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected index 0175556cd17ea..ddb3e73f02cca 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected @@ -28,21 +28,21 @@ define i64 @i64_test(i64 %i) nounwind readnone { define i64 @i32_test(i32 %i) nounwind readnone { ; PIC-LABEL: i32_test: -; PIC: SelectionDAG has 15 nodes: +; PIC: SelectionDAG has 14 nodes: ; PIC-NEXT: t0: ch,glue = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 ; PIC-NEXT: t7: i32,i32,ch = ADD32rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6> +; PIC-NEXT: t8: i64 = SUBREG_TO_REG t7, TargetConstant:i32<6> ; PIC-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 ; PIC-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; PIC-EMPTY: ; ; WIN-LABEL: i32_test: -; WIN: SelectionDAG has 15 nodes: +; WIN: SelectionDAG has 14 nodes: ; WIN-NEXT: t0: ch,glue = EntryToken ; WIN-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 ; WIN-NEXT: t7: i32,i32,ch = ADD32rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6> +; WIN-NEXT: t8: i64 = SUBREG_TO_REG t7, TargetConstant:i32<6> ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; WIN-EMPTY: @@ -55,24 +55,24 @@ define i64 @i32_test(i32 %i) nounwind readnone { define i64 @i16_test(i16 %i) nounwind readnone { ; PIC-LABEL: i16_test: -; PIC: SelectionDAG has 18 nodes: +; PIC: SelectionDAG has 17 nodes: ; PIC-NEXT: t0: ch,glue = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 ; PIC-NEXT: t3: i16 = EXTRACT_SUBREG t2, TargetConstant:i32<4> ; PIC-NEXT: t8: i16,i32,ch = ADD16rm t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t15: i32 = MOVZX32rr16 t8 -; PIC-NEXT: t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6> +; PIC-NEXT: t14: i32 = MOVZX32rr16 t8 +; PIC-NEXT: t9: i64 = SUBREG_TO_REG t14, TargetConstant:i32<6> ; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9 ; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1 ; PIC-EMPTY: ; ; WIN-LABEL: i16_test: -; WIN: SelectionDAG has 16 nodes: +; WIN: SelectionDAG has 15 nodes: ; WIN-NEXT: t0: ch,glue = EntryToken ; WIN-NEXT: t2: i16,ch = CopyFromReg t0, Register:i16 %0 ; WIN-NEXT: t7: i16,i32,ch = ADD16rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t14: i32 = MOVZX32rr16 t7 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6> +; WIN-NEXT: t13: i32 = MOVZX32rr16 t7 +; WIN-NEXT: t8: i64 = SUBREG_TO_REG t13, TargetConstant:i32<6> ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; WIN-EMPTY: @@ -85,24 +85,24 @@ define i64 @i16_test(i16 %i) nounwind readnone { define i64 @i8_test(i8 %i) nounwind readnone { ; PIC-LABEL: i8_test: -; PIC: SelectionDAG has 18 nodes: +; PIC: SelectionDAG has 17 nodes: ; PIC-NEXT: t0: ch,glue = EntryToken ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 ; PIC-NEXT: t3: i8 = EXTRACT_SUBREG t2, TargetConstant:i32<1> ; PIC-NEXT: t8: i8,i32,ch = ADD8rm t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t15: i32 = MOVZX32rr8 t8 -; PIC-NEXT: t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6> +; PIC-NEXT: t14: i32 = MOVZX32rr8 t8 +; PIC-NEXT: t9: i64 = SUBREG_TO_REG t14, TargetConstant:i32<6> ; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9 ; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1 ; PIC-EMPTY: ; ; WIN-LABEL: i8_test: -; WIN: SelectionDAG has 16 nodes: +; WIN: SelectionDAG has 15 nodes: ; WIN-NEXT: t0: ch,glue = EntryToken ; WIN-NEXT: t2: i8,ch = CopyFromReg t0, Register:i8 %0 ; WIN-NEXT: t7: i8,i32,ch = ADD8rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t14: i32 = MOVZX32rr8 t7 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6> +; WIN-NEXT: t13: i32 = MOVZX32rr8 t7 +; WIN-NEXT: t8: i64 = SUBREG_TO_REG t13, TargetConstant:i32<6> ; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 ; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 ; WIN-EMPTY: diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll index ef601189855b4..aac338e825840 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll @@ -95,7 +95,7 @@ for.end: ; preds = %for.cond.cleanup ret void, !dbg !62 } -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } attributes #2 = { nounwind } diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected index 4bae52e7b3815..f7ad99b55e072 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.expected @@ -165,7 +165,7 @@ for.end: ; preds = %for.cond.cleanup ret void, !dbg !62 } -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } attributes #2 = { nounwind } diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected index 12c6e4eee0147..097fb90dc3f9c 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.expected @@ -167,7 +167,7 @@ for.end: ; preds = %for.cond.cleanup ret void, !dbg !62 } -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } attributes #2 = { nounwind } diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected index d67a303236369..0e23016cd2e60 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.globals.expected @@ -167,7 +167,7 @@ for.end: ; preds = %for.cond.cleanup ret void, !dbg !62 } -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } attributes #2 = { nounwind } @@ -239,7 +239,7 @@ attributes #2 = { nounwind } !61 = !DILocation(line: 10, column: 12, scope: !45) !62 = !DILocation(line: 11, column: 1, scope: !41) ;. -; CHECK: attributes #[[ATTR0]] = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +; CHECK: attributes #[[ATTR0]] = { nounwind denormal_fpenv(ieee) uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } ; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } ; CHECK: attributes #[[ATTR2]] = { nounwind } ;. diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected index 4bae52e7b3815..f7ad99b55e072 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.noglobals.expected @@ -165,7 +165,7 @@ for.end: ; preds = %for.cond.cleanup ret void, !dbg !62 } -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } attributes #2 = { nounwind } diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected index fb3a76f305e6a..762af848e14ba 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values_dbgrecords.ll.funcsig.transitiveglobals.expected @@ -165,7 +165,7 @@ for.end: ; preds = %for.cond.cleanup ret void, !dbg !62 } -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" denormal_fpenv(ieee) "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } attributes #2 = { nounwind } diff --git a/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir b/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir index 07f2d350ffd9c..9823983f0f0bb 100644 --- a/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir +++ b/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir @@ -2,11 +2,65 @@ # RUN: llc -mtriple=amdgcn --passes='regallocfast,regallocfast,regallocfast' --print-pipeline-passes --filetype=null %s | FileCheck %s --check-prefix=PASS # RUN: not llc -mtriple=amdgcn --passes='regallocfast' --print-pipeline-passes --filetype=null %s 2>&1 | FileCheck %s --check-prefix=BAD-FILTER +# Test default behavior at -O0: uses fast allocator +# RUN: llc -mtriple=amdgcn -enable-new-pm -O0 -print-pipeline-passes -filetype=null %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-O0 + +# Test default behavior at -O2: uses greedy allocator +# RUN: llc -mtriple=amdgcn -enable-new-pm -O2 -print-pipeline-passes -filetype=null %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-O2 + +# Test AMDGPU-specific NPM regalloc options +# RUN: llc -mtriple=amdgcn -enable-new-pm -sgpr-regalloc-npm=fast -wwm-regalloc-npm=fast -vgpr-regalloc-npm=fast -print-pipeline-passes -filetype=null %s 2>&1 | FileCheck %s --check-prefix=NPM-FAST +# RUN: llc -mtriple=amdgcn -enable-new-pm -O3 -sgpr-regalloc-npm=greedy -wwm-regalloc-npm=greedy -vgpr-regalloc-npm=greedy -print-pipeline-passes -filetype=null %s 2>&1 | FileCheck %s --check-prefix=NPM-GREEDY +# RUN: llc -mtriple=amdgcn -enable-new-pm -O3 -sgpr-regalloc-npm=fast -print-pipeline-passes -filetype=null %s 2>&1 | FileCheck %s --check-prefix=NPM-MIXED + +# Test error cases for unsupported allocators +# RUN: not llc -mtriple=amdgcn -enable-new-pm -sgpr-regalloc-npm=basic -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR-BASIC +# RUN: not llc -mtriple=amdgcn -enable-new-pm -vgpr-regalloc-npm=pbqp -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR-PBQP + +# Test error when legacy PM options are used with NPM +# RUN: not llc -mtriple=amdgcn -enable-new-pm -sgpr-regalloc=greedy -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR-LEGACY + +# Test error when generic --regalloc-npm is used with AMDGPU +# RUN: not llc -mtriple=amdgcn -enable-new-pm -regalloc-npm=fast -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR-GENERIC + # PASS: regallocfast # PASS: regallocfast # PASS: regallocfast # BAD-FILTER: invalid regallocfast register filter 'bad-filter' +# At -O0, default uses fast allocator for all register classes. +# DEFAULT-O0: regallocfast +# DEFAULT-O2: greedy +# DEFAULT-O2: greedy + +# NPM-FAST: regallocfast +# NPM-GREEDY: greedy +# NPM-GREEDY: greedy + +# At -O3, default is greedy. With -sgpr-regalloc-npm=fast, SGPR uses fast, +# but WWM and VGPR still use greedy. +# NPM-MIXED: regallocfast +# NPM-MIXED: greedy + +# Error messages for unsupported allocators. +# ERR-BASIC: unsupported register allocator 'basic' for SGPR registers +# ERR-PBQP: unsupported register allocator 'pbqp' for VGPR registers + +# Error message for legacy PM options with NPM. +# ERR-LEGACY: -sgpr-regalloc, -vgpr-regalloc, and -wwm-regalloc are legacy PM options + +# Error message for generic --regalloc-npm with AMDGPU. +# ERR-GENERIC: -regalloc-npm not supported for amdgcn --- name: f ... diff --git a/llvm/test/tools/llvm-ir2vec/Inputs/input.ll b/llvm/test/tools/llvm-ir2vec/Inputs/input.ll index 1ca881faa0141..93e77be51b8e9 100644 --- a/llvm/test/tools/llvm-ir2vec/Inputs/input.ll +++ b/llvm/test/tools/llvm-ir2vec/Inputs/input.ll @@ -3,3 +3,27 @@ entry: %sum = add i32 %a, %b ret i32 %sum } + +define i32 @multiply(i32 %x, i32 %y) { +entry: + %prod = mul i32 %x, %y + ret i32 %prod +} + +define i32 @conditional(i32 %n) { +entry: + %cmp = icmp sgt i32 %n, 0 + br i1 %cmp, label %positive, label %negative + +positive: + %pos_val = add i32 %n, 10 + br label %exit + +negative: + %neg_val = sub i32 %n, 10 + br label %exit + +exit: + %result = phi i32 [ %pos_val, %positive ], [ %neg_val, %negative ] + ret i32 %result +} diff --git a/llvm/test/tools/llvm-ir2vec/bindings/ir2vec-bindings.py b/llvm/test/tools/llvm-ir2vec/bindings/ir2vec-bindings.py index 4038277667a47..a0d61e4808292 100644 --- a/llvm/test/tools/llvm-ir2vec/bindings/ir2vec-bindings.py +++ b/llvm/test/tools/llvm-ir2vec/bindings/ir2vec-bindings.py @@ -12,5 +12,38 @@ print("SUCCESS: Tool initialized") print(f"Tool type: {type(tool).__name__}") + # Test getFuncEmbMap + print("\n=== Function Embeddings ===") + func_emb_map = tool.getFuncEmbMap() + + # Sorting the function names for fixed-ordered output + for func_name in sorted(func_emb_map.keys()): + emb = func_emb_map[func_name] + print(f"Function: {func_name}") + print(f" Embedding: {emb.tolist()}") + + # Test getFuncEmb for individual functions + print("\n=== Single Function Embeddings ===") + + # Test valid function names + for func_name in ["add", "multiply", "conditional"]: + func_emb = tool.getFuncEmb(func_name) + print(f"Function: {func_name}") + print(f" Embedding: {func_emb.tolist()}") + # CHECK: SUCCESS: Tool initialized # CHECK: Tool type: IR2VecTool +# CHECK: === Function Embeddings === +# CHECK: Function: add +# CHECK-NEXT: Embedding: [38.0, 40.0, 42.0] +# CHECK: Function: conditional +# CHECK-NEXT: Embedding: [413.20000000298023, 421.20000000298023, 429.20000000298023] +# CHECK: Function: multiply +# CHECK-NEXT: Embedding: [50.0, 52.0, 54.0] +# CHECK: === Single Function Embeddings === +# CHECK: Function: add +# CHECK-NEXT: Embedding: [38.0, 40.0, 42.0] +# CHECK: Function: multiply +# CHECK-NEXT: Embedding: [50.0, 52.0, 54.0] +# CHECK: Function: conditional +# CHECK-NEXT: Embedding: [413.20000000298023, 421.20000000298023, 429.20000000298023] diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s index dc4122ab19293..e7d76cf49e06d 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-arithmetic.s @@ -2330,685 +2330,685 @@ vwsub.wx v8, v16, x30 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VI vadd.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VI vadd.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VV vadd.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VV vadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADD_VX vadd.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADD_VX vadd.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VV vsub.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSUB_VV vsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSUB_VX vsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSUB_VX vsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VVM vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VVM vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VXM vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VXM vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VADC_VIM vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VADC_VIM vadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VVM vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSBC_VXM vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VV vwaddu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_VV vwaddu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_VX vwaddu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_VX vwaddu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VV vwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_VV vwadd.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_VX vwadd.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_VX vwadd.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VV vwsubu.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_VV vwsubu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_VX vwsubu.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_VX vwsubu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VV vwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_VV vwsub.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_VX vwsub.vx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_VX vwsub.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAADDU_VV vaaddu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu @@ -3362,533 +3362,533 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VALU VASUB_VX vasub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VI vmadc.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VI vmadc.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VIM vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VIM vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VV vmadc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VV vmadc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VVM vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VVM vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VX vmadc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VX vmadc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMADC_VXM vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMADC_VXM vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VV vmsbc.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VV vmsbc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VX vmsbc.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VX vmsbc.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VI vrsub.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VRSUB_VI vrsub.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VRSUB_VX vrsub.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VRSUB_VX vrsub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSADDU_VI vsaddu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu @@ -4330,245 +4330,245 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSUB_VX vssub.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WV vwaddu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_WV vwaddu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADDU_WX vwaddu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADDU_WX vwaddu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WV vwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_WV vwadd.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWADD_WX vwadd.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWADD_WX vwadd.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WV vwsubu.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_WV vwsubu.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUBU_WX vwsubu.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUBU_WX vwsubu.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WV vwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_WV vwsub.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VWSUB_WX vwsub.wx v8, v16, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VWSUB_WX vwsub.wx v8, v16, t5 # CHECK: Resources: # CHECK-NEXT: [0.0] - Andes45ALU @@ -4591,7 +4591,7 @@ vwsub.wx v8, v16, x30 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] -# CHECK-NEXT: - - 1120.00 - - - - - - 1120.00 - - - - - - - +# CHECK-NEXT: - - 1120.00 - - - - - - 2616.00 - - - - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: @@ -4604,11 +4604,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4616,29 +4616,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4648,11 +4648,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4660,29 +4660,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4692,11 +4692,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4704,29 +4704,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadd.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadd.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4736,11 +4736,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4748,29 +4748,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4780,11 +4780,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4792,29 +4792,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4824,11 +4824,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4836,29 +4836,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4868,11 +4868,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4880,29 +4880,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4912,11 +4912,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4924,29 +4924,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4956,11 +4956,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4968,29 +4968,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5000,11 +5000,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5012,29 +5012,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5042,29 +5042,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5072,29 +5072,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5102,29 +5102,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5132,29 +5132,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5162,29 +5162,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5192,29 +5192,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5222,29 +5222,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5252,29 +5252,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vaaddu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5636,11 +5636,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5648,29 +5648,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5680,11 +5680,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5692,29 +5692,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5724,11 +5724,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5736,29 +5736,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5768,11 +5768,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5780,29 +5780,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5812,11 +5812,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5824,29 +5824,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5856,11 +5856,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5868,29 +5868,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmadc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5900,11 +5900,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5912,29 +5912,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5944,11 +5944,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -5956,29 +5956,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -5988,11 +5988,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6000,29 +6000,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6032,11 +6032,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6044,29 +6044,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsbc.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6076,11 +6076,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6088,29 +6088,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vrsub.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6120,11 +6120,11 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -6132,29 +6132,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vrsub.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vrsub.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsaddu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6602,29 +6602,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6632,29 +6632,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwaddu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwaddu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6662,29 +6662,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6692,29 +6692,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwadd.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwadd.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6722,29 +6722,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6752,29 +6752,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsubu.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsubu.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6782,29 +6782,29 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -6812,26 +6812,26 @@ vwsub.wx v8, v16, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vwsub.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vwsub.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vwsub.wx v8, v16, t5 diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s index 3445098403df3..c7eec08847b14 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-bitwise.s @@ -1486,581 +1486,581 @@ vssrl.vx v8, v8, x30 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VV vand.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VV vand.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VX vand.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VX vand.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VAND_VI vand.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VAND_VI vand.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VV vor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VV vor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VX vor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VX vor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VOR_VI vor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VOR_VI vor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VV vxor.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VV vxor.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VX vxor.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VX vxor.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VXOR_VI vxor.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VXOR_VI vxor.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WV vnsra.wv v8, v16, v24 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WV vnsra.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WX vnsra.wx v8, v16, t5 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WX vnsra.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRA_WI vnsra.wi v8, v16, 12 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRA_WI vnsra.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WV vnsrl.wv v8, v16, v24 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WV vnsrl.wv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WX vnsrl.wx v8, v16, t5 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WX vnsrl.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 2.00 3 Andes45VALU[2] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 4.00 3 Andes45VALU[4] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNSRL_WI vnsrl.wi v8, v16, 12 +# CHECK-NEXT: 1 3 8.00 3 Andes45VALU[8] VNSRL_WI vnsrl.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIPU_WI vnclipu.wi v8, v16, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu @@ -2242,401 +2242,401 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VALU VNCLIP_WX vnclip.wx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VI vsll.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VI vsll.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VV vsll.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VV vsll.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSLL_VX vsll.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSLL_VX vsll.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VI vsra.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VI vsra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VV vsra.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VV vsra.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRA_VX vsra.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRA_VX vsra.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VI vsrl.vi v8, v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VI vsrl.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VV vsrl.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VV vsrl.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSRL_VX vsrl.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VSRL_VX vsrl.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSSRA_VI vssra.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu @@ -2923,7 +2923,7 @@ vssrl.vx v8, v8, x30 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] -# CHECK-NEXT: - - 708.00 - - - - - - 708.00 - - - - - - - +# CHECK-NEXT: - - 708.00 - - - - - - 1698.00 - - - - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: @@ -2936,11 +2936,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2948,29 +2948,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2980,11 +2980,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2992,29 +2992,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3024,11 +3024,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3036,29 +3036,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vand.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vand.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3068,11 +3068,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3080,29 +3080,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3112,11 +3112,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3124,29 +3124,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3156,11 +3156,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3168,29 +3168,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3200,11 +3200,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3212,29 +3212,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3244,11 +3244,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3256,29 +3256,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3288,11 +3288,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3300,29 +3300,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vxor.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vxor.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3330,29 +3330,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3360,29 +3360,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3390,29 +3390,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsra.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsra.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3420,29 +3420,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3450,29 +3450,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3480,29 +3480,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnsrl.wi v8, v16, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vnsrl.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vnclipu.wi v8, v16, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3692,11 +3692,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3704,29 +3704,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3736,11 +3736,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3748,29 +3748,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3780,11 +3780,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3792,29 +3792,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsll.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsll.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3824,11 +3824,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3836,29 +3836,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3868,11 +3868,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3880,29 +3880,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3912,11 +3912,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3924,29 +3924,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsra.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsra.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3956,11 +3956,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3968,29 +3968,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4000,11 +4000,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4012,29 +4012,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -4044,11 +4044,11 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -4056,29 +4056,29 @@ vssrl.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsrl.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vsrl.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vssra.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s index 7aaa351bbbc3e..1f671b4174532 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-comparison.s @@ -934,885 +934,885 @@ vmslt.vx v8, v8, x30 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VV vmseq.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VV vmseq.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VX vmseq.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VX vmseq.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSEQ_VI vmseq.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSEQ_VI vmseq.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VV vmsle.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VV vmsle.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VX vmsle.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VX vmsle.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLE_VI vmsle.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLE_VI vmsle.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VV vmsleu.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VV vmsleu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VX vmsleu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VX vmsleu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLEU_VI vmsleu.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLEU_VI vmsleu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VV vmsne.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VV vmsne.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VX vmsne.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VX vmsne.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSNE_VI vmsne.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSNE_VI vmsne.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VI vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGTU_VX vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VI vmsgt.vi v8, v8, 12 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGT_VI vmsgt.vi v8, v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSGT_VX vmsgt.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSGT_VX vmsgt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VV vmsltu.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLTU_VV vmsltu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLTU_VX vmsltu.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLTU_VX vmsltu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VV vmslt.vv v8, v8, v8 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLT_VV vmslt.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 3 1.00 3 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VALU[2] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 6 4.00 6 Andes45VALU[4] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMSLT_VX vmslt.vx v8, v8, t5 +# CHECK-NEXT: 1 10 8.00 10 Andes45VALU[8] VMSLT_VX vmslt.vx v8, v8, t5 # CHECK: Resources: # CHECK-NEXT: [0.0] - Andes45ALU @@ -1835,7 +1835,7 @@ vmslt.vx v8, v8, x30 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] -# CHECK-NEXT: - - 440.00 - - - - - - 440.00 - - - - - - - +# CHECK-NEXT: - - 440.00 - - - - - - 1320.00 - - - - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: @@ -1848,11 +1848,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1860,29 +1860,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1892,11 +1892,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1904,29 +1904,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1936,11 +1936,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1948,29 +1948,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmseq.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmseq.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1980,11 +1980,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1992,29 +1992,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2024,11 +2024,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2036,29 +2036,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2068,11 +2068,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2080,29 +2080,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsle.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsle.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2112,11 +2112,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2124,29 +2124,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2156,11 +2156,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2168,29 +2168,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2200,11 +2200,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2212,29 +2212,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsleu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsleu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2244,11 +2244,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2256,29 +2256,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2288,11 +2288,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2300,29 +2300,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2332,11 +2332,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2344,29 +2344,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsne.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsne.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2376,11 +2376,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2388,29 +2388,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgtu.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2420,11 +2420,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2432,29 +2432,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgtu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgtu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2464,11 +2464,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2476,29 +2476,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vi v8, v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgt.vi v8, v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2508,11 +2508,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2520,29 +2520,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsgt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsgt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2552,11 +2552,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2564,29 +2564,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsltu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2596,11 +2596,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2608,29 +2608,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmsltu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmsltu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2640,11 +2640,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2652,29 +2652,29 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2684,11 +2684,11 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2696,26 +2696,26 @@ vmslt.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmslt.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmslt.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmslt.vx v8, v8, t5 diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s index f7273e5851d81..f81e529da2718 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-conversion.s @@ -623,117 +623,117 @@ vfwcvt.xu.f.v v8, v16 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF2 vsext.vf2 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VSEXT_VF2 vsext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF2 vzext.vf2 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VZEXT_VF2 vzext.vf2 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF4 vsext.vf4 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VSEXT_VF4 vsext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF4 vzext.vf4 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VZEXT_VF4 vzext.vf4 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF8 vsext.vf8 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VSEXT_VF8 vsext.vf8 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF8 vsext.vf8 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VSEXT_VF8 vsext.vf8 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF8 vsext.vf8 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VSEXT_VF8 vsext.vf8 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VSEXT_VF8 vsext.vf8 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VSEXT_VF8 vsext.vf8 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF8 vzext.vf8 v8, v16 +# CHECK-NEXT: 1 2 1.00 2 Andes45VPERMUT VZEXT_VF8 vzext.vf8 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF8 vzext.vf8 v8, v16 +# CHECK-NEXT: 1 2 2.00 2 Andes45VPERMUT[2] VZEXT_VF8 vzext.vf8 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF8 vzext.vf8 v8, v16 +# CHECK-NEXT: 1 2 4.00 2 Andes45VPERMUT[4] VZEXT_VF8 vzext.vf8 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VZEXT_VF8 vzext.vf8 v8, v16 +# CHECK-NEXT: 1 2 8.00 2 Andes45VPERMUT[8] VZEXT_VF8 vzext.vf8 v8, v16 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFCVT_F_XU_V vfcvt.f.xu.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -1206,122 +1206,122 @@ vfwcvt.xu.f.v v8, v16 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] -# CHECK-NEXT: - - 281.00 - - - - - - 56.00 - - 225.00 - - - - +# CHECK-NEXT: - - 281.00 - - - - - - - - - 225.00 - - - 188.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf2 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf2 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf4 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf4 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf8 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vsext.vf8 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf8 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vsext.vf8 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf8 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vsext.vf8 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vsext.vf8 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vsext.vf8 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf8 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vzext.vf8 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf8 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 2.00 vzext.vf8 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf8 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 4.00 vzext.vf8 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vzext.vf8 v8, v16 +# CHECK-NEXT: - - - - - - - - - - - - - - - - 8.00 vzext.vf8 v8, v16 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfcvt.f.xu.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s index 7f5df0694a4c5..a90365722ff88 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-fma.s @@ -763,567 +763,567 @@ vfwnmsac.vv v8, v16, v24 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VV vmacc.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VV vmacc.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMACC_VX vmacc.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMACC_VX vmacc.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VV vmadd.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VV vmadd.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMADD_VX vmadd.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMADD_VX vmadd.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VV vnmsac.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VV vnmsac.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSAC_VX vnmsac.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSAC_VX vnmsac.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VV vnmsub.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VV vnmsub.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VNMSUB_VX vnmsub.vx v8, s0, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VNMSUB_VX vnmsub.vx v8, s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VV vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VV vwmaccu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCU_VX vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCU_VX vwmaccu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VV vwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VV vwmacc.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACC_VX vwmacc.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACC_VX vwmacc.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VV vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCSU_VX vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMACCUS_VX vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VFWMACC_VF vfwmacc.vf v8, fa6, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -1490,7 +1490,7 @@ vfwnmsac.vv v8, v16, v24 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] -# CHECK-NEXT: - - 353.00 - - - - - - - - - - - 353.00 - - +# CHECK-NEXT: - - 353.00 - - - - - - - - - - - 936.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: @@ -1503,11 +1503,11 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1515,29 +1515,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1547,11 +1547,11 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1559,29 +1559,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmacc.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmacc.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1591,11 +1591,11 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1603,29 +1603,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1635,11 +1635,11 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1647,29 +1647,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmadd.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmadd.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1679,11 +1679,11 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1691,29 +1691,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1723,11 +1723,11 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1735,29 +1735,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsac.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsac.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1767,11 +1767,11 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1779,29 +1779,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1811,11 +1811,11 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1823,29 +1823,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vnmsub.vx v8, s0, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vnmsub.vx v8, s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1853,29 +1853,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1883,29 +1883,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1913,29 +1913,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1943,29 +1943,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmacc.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmacc.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1973,29 +1973,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2003,29 +2003,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccsu.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccsu.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2033,29 +2033,29 @@ vfwnmsac.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmaccus.vx v8, a6, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmaccus.vx v8, a6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s index e9fa22065fd37..fef4a09fba800 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-minmax.s @@ -394,357 +394,357 @@ vminu.vx v8, v8, x30 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VV vmax.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAX_VV vmax.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAX_VX vmax.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAX_VX vmax.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VV vmaxu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAXU_VV vmaxu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMAXU_VX vmaxu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMAXU_VX vmaxu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VV vmin.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMIN_VV vmin.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMIN_VX vmin.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMIN_VX vmin.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VV vminu.vv v8, v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMINU_VV vminu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMINU_VX vminu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMINU_VX vminu.vx v8, v8, t5 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMINU_VX vminu.vx v8, v8, t5 # CHECK: Resources: # CHECK-NEXT: [0.0] - Andes45ALU @@ -767,7 +767,7 @@ vminu.vx v8, v8, x30 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] -# CHECK-NEXT: - - 176.00 - - - - - - 176.00 - - - - - - - +# CHECK-NEXT: - - 176.00 - - - - - - 528.00 - - - - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: @@ -780,11 +780,11 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -792,29 +792,29 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -824,11 +824,11 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -836,29 +836,29 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmax.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmax.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -868,11 +868,11 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -880,29 +880,29 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmaxu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -912,11 +912,11 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -924,29 +924,29 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmaxu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmaxu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -956,11 +956,11 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -968,29 +968,29 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmin.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1000,11 +1000,11 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1012,29 +1012,29 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmin.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmin.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1044,11 +1044,11 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1056,29 +1056,29 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -1088,11 +1088,11 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -1100,26 +1100,26 @@ vminu.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vminu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vminu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vminu.vx v8, v8, t5 diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s index 0405f8463299f..20ec9c811ef84 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-mul-div.s @@ -1030,889 +1030,889 @@ vsmul.vx v8, v8, x30 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VV vmul.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VV vmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMUL_VX vmul.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMUL_VX vmul.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VV vdiv.vv v8, v8, v8 +# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VDIV_VV vdiv.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIV_VX vdiv.vx v8, v8, t5 +# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VDIV_VX vdiv.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VV vdivu.vv v8, v8, v8 +# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VDIVU_VV vdivu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VDIVU_VX vdivu.vx v8, v8, t5 +# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VDIVU_VX vdivu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VV vrem.vv v8, v8, v8 +# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VREM_VV vrem.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREM_VX vrem.vx v8, v8, t5 +# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VREM_VX vrem.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VV vremu.vv v8, v8, v8 +# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VREMU_VV vremu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 11.00 12 Andes45VDIV[11] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 21.00 12 Andes45VDIV[21] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 41.00 12 Andes45VDIV[41] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 12 81.00 12 Andes45VDIV[81] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 19.00 20 Andes45VDIV[19] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 37.00 20 Andes45VDIV[37] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 73.00 20 Andes45VDIV[73] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 20 145.00 20 Andes45VDIV[145] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 35.00 36 Andes45VDIV[35] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 69.00 36 Andes45VDIV[69] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 137.00 36 Andes45VDIV[137] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 36 273.00 36 Andes45VDIV[273] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 68 67.00 68 Andes45VDIV[67] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 68 133.00 68 Andes45VDIV[133] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 68 265.00 68 Andes45VDIV[265] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VDIV VREMU_VX vremu.vx v8, v8, t5 +# CHECK-NEXT: 1 68 529.00 68 Andes45VDIV[529] VREMU_VX vremu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VV vmulh.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VV vmulh.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULH_VX vmulh.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULH_VX vmulh.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VV vmulhu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VV vmulhu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHU_VX vmulhu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHU_VX vmulhu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VV vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VV vmulhsu.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VMULHSU_VX vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VMULHSU_VX vmulhsu.vx v8, v8, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VV vwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VV vwmul.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMUL_VX vwmul.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMUL_VX vwmul.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VV vwmulu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VV vwmulu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULU_VX vwmulu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULU_VX vwmulu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VV vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VV vwmulsu.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 1.00 4 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 2.00 4 Andes45VMAC[2] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 4.00 4 Andes45VMAC[4] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VWMULSU_VX vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: 1 4 8.00 4 Andes45VMAC[8] VWMULSU_VX vwmulsu.vx v8, v16, t5 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VMAC VSMUL_VV vsmul.vv v8, v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu @@ -2023,7 +2023,7 @@ vsmul.vx v8, v8, x30 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] -# CHECK-NEXT: - - 486.00 - - - - - - - 176.00 - - - 310.00 - - +# CHECK-NEXT: - - 486.00 - - - - - - - 16336.00 - - - 860.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: @@ -2036,11 +2036,11 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2048,29 +2048,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2080,11 +2080,11 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2092,381 +2092,381 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmul.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmul.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vdiv.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdiv.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vdiv.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdivu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdivu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vdivu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vdivu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - 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CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vremu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vremu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 11.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 21.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 41.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 81.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 19.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 37.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 73.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 145.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 35.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 69.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 137.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 273.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 67.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 133.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 265.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - vremu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - 529.00 - - - - - - vremu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2476,11 +2476,11 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2488,29 +2488,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2520,11 +2520,11 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2532,29 +2532,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulh.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulh.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2564,11 +2564,11 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2576,29 +2576,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2608,11 +2608,11 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2620,29 +2620,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2652,11 +2652,11 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2664,29 +2664,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vv v8, v8, v8 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2696,11 +2696,11 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2708,29 +2708,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vmulhsu.vx v8, v8, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vmulhsu.vx v8, v8, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2738,29 +2738,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2768,29 +2768,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmul.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmul.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2798,29 +2798,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2828,29 +2828,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2858,29 +2858,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vv v8, v16, v24 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vv v8, v16, v24 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2888,29 +2888,29 @@ vsmul.vx v8, v8, x30 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vwmulsu.vx v8, v16, t5 +# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - vwmulsu.vx v8, v16, t5 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - vsmul.vv v8, v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s index 40ca2678c30cc..82f6c4acfd072 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-permutation.s @@ -1206,137 +1206,137 @@ vfslide1up.vf v8, v16, ft0 # CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_V vmv.v.v v8, v8 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_V vmv.v.v v8, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_X vmv.v.x v8, s0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_X vmv.v.x v8, s0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMV_V_I vmv.v.i v8, 12 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMV_V_I vmv.v.i v8, 12 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VMV_X_S vmv.x.s s0, v8 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu @@ -2128,137 +2128,137 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VPERMUT VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VIM vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VVM vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, mf8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, mf2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m1, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 1.00 2 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 2.00 2 Andes45VALU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 4.00 2 Andes45VALU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: 1 1 1.00 1 Andes45VALU VMERGE_VXM vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: 1 2 8.00 2 Andes45VALU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: 1 1 1.00 1 Andes45VFMIS VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0 # CHECK-NEXT: 1 1 1.00 U 1 Andes45CSR VSETVLI vsetvli t3, zero, e16, mf4, tu, mu @@ -2371,7 +2371,7 @@ vfslide1up.vf v8, v16, ft0 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] -# CHECK-NEXT: - - 572.00 - - - - - - 132.00 - - 15.00 - - 22.00 403.00 +# CHECK-NEXT: - - 572.00 - - - - - - 396.00 - - 15.00 - - 22.00 403.00 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: @@ -2384,11 +2384,11 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2396,29 +2396,29 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.v v8, v8 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.v v8, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2428,11 +2428,11 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2440,29 +2440,29 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.x v8, s0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.x v8, s0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -2472,11 +2472,11 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -2484,29 +2484,29 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmv.v.i v8, 12 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmv.v.i v8, 12 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 vmv.x.s s0, v8 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3306,11 +3306,11 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3318,29 +3318,29 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vim v8, v8, 12, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vim v8, v8, 12, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3350,11 +3350,11 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3362,29 +3362,29 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vvm v8, v8, v8, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu @@ -3394,11 +3394,11 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu @@ -3406,29 +3406,29 @@ vfslide1up.vf v8, v16, ft0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 2.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 4.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu -# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 +# CHECK-NEXT: - - - - - - - - - 8.00 - - - - - - - vmerge.vxm v8, v8, t5, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu # CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - vfmerge.vfm v8, v8, ft0, v0 # CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test new file mode 100644 index 0000000000000..68128557b7d7b --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/atomic.test @@ -0,0 +1,224 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../Inputs/atomic.s | FileCheck %s + +# CHECK: Resources: +# CHECK-NEXT: [0] - SMTX100_BQ:2 +# CHECK-NEXT: [1] - SMTX100_FQ:4 SMTX100_FQ0, SMTX100_FQ0, SMTX100_FQ1, SMTX100_FQ1 +# CHECK-NEXT: [2] - SMTX100_FQ0:2 +# CHECK-NEXT: [3] - SMTX100_FQ1:2 +# CHECK-NEXT: [4] - SMTX100_IQ:4 SMTX100_IQ0, SMTX100_IQ0, SMTX100_IQ1, SMTX100_IQ1 +# CHECK-NEXT: [5] - SMTX100_IQ0:2 +# CHECK-NEXT: [6] - SMTX100_IQ1:2 +# CHECK-NEXT: [7] - SMTX100_LSQ:4 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) +# CHECK-NEXT: [7]: Bypass Latency +# CHECK-NEXT: [8]: Resources ( | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, | [] | [, %t-detect.txt ; RUN: diff %t-specify.txt %t-detect.txt +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1170 -filetype=obj -O0 -o %t.o %s +; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1170 %t.o > %t-specify.txt +; RUN: llvm-objdump -D %t.o > %t-detect.txt +; RUN: diff %t-specify.txt %t-detect.txt + ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1153 -filetype=obj -O0 -o %t.o %s ; RUN: llvm-objdump -D --arch-name=amdgcn --mcpu=gfx1153 %t.o > %t-specify.txt ; RUN: llvm-objdump -D %t.o > %t-detect.txt diff --git a/llvm/test/tools/llvm-objdump/ELF/AVR/lit.local.cfg b/llvm/test/tools/llvm-objdump/ELF/AVR/lit.local.cfg new file mode 100644 index 0000000000000..1724fb233c169 --- /dev/null +++ b/llvm/test/tools/llvm-objdump/ELF/AVR/lit.local.cfg @@ -0,0 +1,2 @@ +if not "AVR" in config.root.targets: + config.unsupported = True diff --git a/llvm/test/tools/llvm-objdump/ELF/AVR/mattr.test b/llvm/test/tools/llvm-objdump/ELF/AVR/mattr.test new file mode 100644 index 0000000000000..40b8f34bb6767 --- /dev/null +++ b/llvm/test/tools/llvm-objdump/ELF/AVR/mattr.test @@ -0,0 +1,55 @@ +## When --mattr and --mcpu are both empty, disassemble ELF with e_flags derived feature. +# RUN: yaml2obj -DARCH_ARCHVERSION=EF_AVR_ARCH_AVR1 %s -o %t.avr1 +# RUN: llvm-objdump -d %t.avr1 | FileCheck %s --check-prefix=AVR1 +# RUN: yaml2obj -DARCH_ARCHVERSION=EF_AVR_ARCH_AVR3 %s -o %t.avr3 +# RUN: llvm-objdump -d %t.avr3 | FileCheck %s --check-prefix=ALL + +## The mask is being correctly applied before the version is determined. +# RUN: yaml2obj -DARCH_ARCHVERSION='EF_AVR_ARCH_AVR3, EF_AVR_LINKRELAX_PREPARED' %s -o %t.multiflag +# RUN: llvm-objdump -d %t.multiflag | FileCheck %s --check-prefix=ALL + +## If --mattr or --mcpu is specified, don't default to the file's e_flags derived feature. +# RUN: llvm-objdump -d --mattr=+avr3 %t.avr1 | FileCheck %s --check-prefix=ALL +# RUN: llvm-objdump -d --mcpu=avr3 %t.avr1 | FileCheck %s --check-prefix=ALL +# RUN: llvm-objdump -d --mattr=+avr1 %t.avr3 | FileCheck %s --check-prefix=AVR1 +# RUN: llvm-objdump -d --mcpu=avr1 %t.avr3 | FileCheck %s --check-prefix=AVR1 + +## If the file's e_flags doesn't representing an AVR version, default to "avr0". +# RUN: yaml2obj -DARCH_ARCHVERSION=EF_AVR_LINKRELAX_PREPARED %s -o %t.noarchversion +# RUN: llvm-objdump -d %t.noarchversion 2>&1 | FileCheck -DFILE=%t.noarchversion -DVERSION=0x0 %s --check-prefixes=AVR0,INVALIDARCHINFO + +## If file's e_flags is unrecognised, default to "avr0". +# RUN: yaml2obj -DARCH_ARCHVERSION='EF_AVR_ARCH_AVR1, EF_AVR_ARCH_AVR6' %s -o %t.invalid +# RUN: llvm-objdump -d %t.invalid 2>&1 | FileCheck -DFILE=%t.invalid -DVERSION=0x7 %s --check-prefixes=AVR0,INVALIDARCHINFO + +# AVR1: <_start>: +# AVR1-COUNT-2: +# AVR1-NEXT: lpm +# AVR1-NEXT: rjmp .-2 + +# ALL: <_start>: +# ALL-NEXT: call 0x0 +# ALL-NEXT: jmp 0x0 +# ALL-NEXT: lpm +# ALL-NEXT: rjmp .-2 + +# INVALIDARCHINFO: warning: '[[FILE]]': unrecognised AVR version, [[VERSION]]: defaulting to avr0 +# AVR0: <_start>: +# AVR0-COUNT-3: + +--- !ELF +FileHeader: + Class: ELFCLASS32 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_AVR + Flags: [ [[ARCH_ARCHVERSION]] ] +Sections: + - Name: .text + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC, SHF_EXECINSTR ] + Content: 0E9400000C940000C895FFCF +Symbols: + - Name: _start + Section: .text + Binding: STB_GLOBAL diff --git a/llvm/test/tools/llvm-profgen/Inputs/coff-profile.exe b/llvm/test/tools/llvm-profgen/Inputs/coff-profile.exe index a4c36a346633a..485f5ff966522 100644 Binary files a/llvm/test/tools/llvm-profgen/Inputs/coff-profile.exe and b/llvm/test/tools/llvm-profgen/Inputs/coff-profile.exe differ diff --git a/llvm/test/tools/llvm-profgen/Inputs/coff-profile.pdb b/llvm/test/tools/llvm-profgen/Inputs/coff-profile.pdb new file mode 100644 index 0000000000000..fb6a11e2d8dd8 Binary files /dev/null and b/llvm/test/tools/llvm-profgen/Inputs/coff-profile.pdb differ diff --git a/llvm/test/tools/llvm-profgen/coff-profile.test b/llvm/test/tools/llvm-profgen/coff-profile.test index eb8ce02b86668..3a0468679e3e9 100644 --- a/llvm/test/tools/llvm-profgen/coff-profile.test +++ b/llvm/test/tools/llvm-profgen/coff-profile.test @@ -8,6 +8,11 @@ ; RUN: llvm-profgen --format=text --perfscript=%S/Inputs/coff-profile.perfscript --binary=%t.dir/coff-profile.exe --debug-binary=%S/Inputs/coff-profile.exe --output=%t ; RUN: FileCheck %s --input-file %t --check-prefix=PROBE +; RUN: llvm-objcopy --strip-debug %S/Inputs/coff-profile.exe %t.dir/coff-profile.exe +; RUN: cp %S/Inputs/coff-profile.pdb %t.dir +; RUN: llvm-profgen --format=text --perfscript=%S/Inputs/coff-profile.perfscript --binary=%t.dir/coff-profile.exe --output=%t +; RUN: FileCheck %s --input-file %t --check-prefix=PROBE + DWARF: main:31341:0 DWARF-NEXT: 0: 0 DWARF-NEXT: 3: 0 @@ -27,12 +32,14 @@ DWARF-NEXT: 1.1: 31 DWARF-NEXT: 1.2: 31 DWARF-NEXT: 2: 31 DWARF-NEXT: 3: 31 +DWARF-NEXT: 65530: 0 DWARF-NEXT: 5: ?work2@?$MyClass@GH@MyNameSpace1@@QEAAXQEAGH@Z:28303 DWARF-NEXT: 0: ?work@?$MyClass@GH@MyNameSpace1@@AEAAXQEAGHH@Z:28303 DWARF-NEXT: 1.1: 341 DWARF-NEXT: 1.2: 341 DWARF-NEXT: 2: 341 DWARF-NEXT: 3: 341 +DWARF-NEXT: 65530: 0 DWARF-NEXT: 7: ?print@MyNameSpace2@@YAXPEAGH@Z:0 DWARF-NEXT: 1: 0 diff --git a/llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test b/llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test index f6786a606f833..bb9955f520a14 100644 --- a/llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test +++ b/llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test @@ -433,6 +433,15 @@ # RUN: yaml2obj %s -o %t -DABI_VERSION=2 -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1153 # RUN: llvm-readobj -h %t | FileCheck %s --check-prefixes=ALL,KNOWN-ABI-VERSION,SINGLE-FLAG --match-full-lines -DABI_VERSION=2 -DFILE=%t -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1153 -DFLAG_VALUE=0x58 +# RUN: yaml2obj %s -o %t -DABI_VERSION=0 -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1170 +# RUN: llvm-readobj -h %t | FileCheck %s --check-prefixes=ALL,KNOWN-ABI-VERSION,SINGLE-FLAG --match-full-lines -DABI_VERSION=0 -DFILE=%t -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1170 -DFLAG_VALUE=0x5D + +# RUN: yaml2obj %s -o %t -DABI_VERSION=1 -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1170 +# RUN: llvm-readobj -h %t | FileCheck %s --check-prefixes=ALL,KNOWN-ABI-VERSION,SINGLE-FLAG --match-full-lines -DABI_VERSION=1 -DFILE=%t -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1170 -DFLAG_VALUE=0x5D + +# RUN: yaml2obj %s -o %t -DABI_VERSION=2 -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1170 +# RUN: llvm-readobj -h %t | FileCheck %s --check-prefixes=ALL,KNOWN-ABI-VERSION,SINGLE-FLAG --match-full-lines -DABI_VERSION=2 -DFILE=%t -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1170 -DFLAG_VALUE=0x5D + # RUN: yaml2obj %s -o %t -DABI_VERSION=0 -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1200 # RUN: llvm-readobj -h %t | FileCheck %s --check-prefixes=ALL,KNOWN-ABI-VERSION,SINGLE-FLAG --match-full-lines -DABI_VERSION=0 -DFILE=%t -DFLAG_NAME=EF_AMDGPU_MACH_AMDGCN_GFX1200 -DFLAG_VALUE=0x48 diff --git a/llvm/test/tools/llvm-readobj/ELF/unwind-sdata8.test b/llvm/test/tools/llvm-readobj/ELF/unwind-sdata8.test new file mode 100644 index 0000000000000..64f6f779d0058 --- /dev/null +++ b/llvm/test/tools/llvm-readobj/ELF/unwind-sdata8.test @@ -0,0 +1,112 @@ +## Check we can parse .eh_frame_hdr with sdata8 encoding (used for large binaries). +## Header uses eh_frame_ptr_enc=0x1c (pcrel|sdata8) and table_enc=0x3c (datarel|sdata8). +# RUN: yaml2obj --docnum=1 %s -o %t.sdata8 +# RUN: llvm-readelf --unwind %t.sdata8 | FileCheck %s --check-prefix=SDATA8 + +# SDATA8: EHFrameHeader { +# SDATA8-NEXT: Address: 0x1000 +# SDATA8-NEXT: Offset: 0x78 +# SDATA8-NEXT: Size: 0x30 +# SDATA8-NEXT: Corresponding Section: .eh_frame_hdr +# SDATA8-NEXT: Header { +# SDATA8-NEXT: version: 1 +# SDATA8-NEXT: eh_frame_ptr_enc: 0x1c +# SDATA8-NEXT: fde_count_enc: 0x3 +# SDATA8-NEXT: table_enc: 0x3c +# SDATA8-NEXT: eh_frame_ptr: 0x1030 +# SDATA8-NEXT: fde_count: 2 +# SDATA8-NEXT: entry 0 { +# SDATA8-NEXT: initial_location: 0x2000 +# SDATA8-NEXT: address: 0x1048 +# SDATA8-NEXT: } +# SDATA8-NEXT: entry 1 { +# SDATA8-NEXT: initial_location: 0x2001 +# SDATA8-NEXT: address: 0x1068 +# SDATA8-NEXT: } +# SDATA8-NEXT: } +# SDATA8-NEXT: } + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .eh_frame_hdr + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Address: 0x1000 + AddressAlign: 4 +## Header: version=1, eh_frame_ptr_enc=0x1c (pcrel|sdata8), +## fde_count_enc=0x03 (udata4), table_enc=0x3c (datarel|sdata8) +## eh_frame_ptr: 0x2c (8 bytes) -> points to 0x1004 + 0x2c = 0x1030 +## fde_count: 2 (4 bytes) +## entry 0: initial_location=0x1000 (0x2000-0x1000), address=0x48 (0x1048-0x1000) +## entry 1: initial_location=0x1001 (0x2001-0x1000), address=0x68 (0x1068-0x1000) + Content: 011c033c2c00000000000000020000000010000000000000480000000000000001100000000000006800000000000000 +ProgramHeaders: + - Type: PT_GNU_EH_FRAME + Flags: [ PF_R ] + VAddr: 0x1000 + PAddr: 0x1000 + MemSize: 0x30 + FileSize: 0x30 + FirstSec: .eh_frame_hdr + LastSec: .eh_frame_hdr + +## Check we can parse .eh_frame_hdr with mixed encoding: sdata8 for eh_frame_ptr, sdata4 for table. +# RUN: yaml2obj --docnum=2 %s -o %t.mixed +# RUN: llvm-readelf --unwind %t.mixed | FileCheck %s --check-prefix=MIXED + +# MIXED: EHFrameHeader { +# MIXED-NEXT: Address: 0x1000 +# MIXED-NEXT: Offset: 0x78 +# MIXED-NEXT: Size: 0x20 +# MIXED-NEXT: Corresponding Section: .eh_frame_hdr +# MIXED-NEXT: Header { +# MIXED-NEXT: version: 1 +# MIXED-NEXT: eh_frame_ptr_enc: 0x1c +# MIXED-NEXT: fde_count_enc: 0x3 +# MIXED-NEXT: table_enc: 0x3b +# MIXED-NEXT: eh_frame_ptr: 0x1020 +# MIXED-NEXT: fde_count: 2 +# MIXED-NEXT: entry 0 { +# MIXED-NEXT: initial_location: 0x2000 +# MIXED-NEXT: address: 0x1030 +# MIXED-NEXT: } +# MIXED-NEXT: entry 1 { +# MIXED-NEXT: initial_location: 0x2001 +# MIXED-NEXT: address: 0x1050 +# MIXED-NEXT: } +# MIXED-NEXT: } +# MIXED-NEXT: } + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .eh_frame_hdr + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Address: 0x1000 + AddressAlign: 4 +## Header: version=1, eh_frame_ptr_enc=0x1c (pcrel|sdata8), +## fde_count_enc=0x03 (udata4), table_enc=0x3b (datarel|sdata4) +## eh_frame_ptr: 0x1c (8 bytes) -> points to 0x1004 + 0x1c = 0x1020 +## fde_count: 2 (4 bytes) +## entry 0: initial_location=0x1000 (4 bytes), address=0x30 (4 bytes) +## entry 1: initial_location=0x1001 (4 bytes), address=0x50 (4 bytes) + Content: 011c033b1c000000000000000200000000100000300000000110000050000000 +ProgramHeaders: + - Type: PT_GNU_EH_FRAME + Flags: [ PF_R ] + VAddr: 0x1000 + PAddr: 0x1000 + MemSize: 0x20 + FileSize: 0x20 + FirstSec: .eh_frame_hdr + LastSec: .eh_frame_hdr diff --git a/llvm/test/tools/llvm-readobj/ELF/unwind.test b/llvm/test/tools/llvm-readobj/ELF/unwind.test index 2e51ec2a61a63..16e347908fc02 100644 --- a/llvm/test/tools/llvm-readobj/ELF/unwind.test +++ b/llvm/test/tools/llvm-readobj/ELF/unwind.test @@ -358,3 +358,36 @@ ProgramHeaders: # BROKEN-CONTENT2-NEXT: Size: [[SIZE]] # BROKEN-CONTENT2-NEXT: Corresponding Section: # BROKEN-CONTENT2-NEXT: error: '[[FILE]]': program header [index 0] has a p_offset ([[OFFSET]]) + p_filesz ([[SIZE]]) that cannot be represented + +## Check we report an error for an unsupported table_enc encoding. +# RUN: yaml2obj --docnum=5 %s -o %t.badtableenc +# RUN: not llvm-readelf --unwind %t.badtableenc 2>&1 | FileCheck %s -DFILE=%t.badtableenc --check-prefix=BAD-TABLE-ENC + +# BAD-TABLE-ENC: EHFrameHeader { +# BAD-TABLE-ENC-NEXT: Address: 0x1000 +# BAD-TABLE-ENC: table_enc: 0xfe +# BAD-TABLE-ENC-NEXT: error: '[[FILE]]': unexpected encoding table_enc 0xfe + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_X86_64 +Sections: + - Name: .eh_frame_hdr + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Address: 0x1000 + AddressAlign: 4 +## Header with invalid table_enc (0xfe) + Content: 011b03fe00000000 +ProgramHeaders: + - Type: PT_GNU_EH_FRAME + Flags: [ PF_R ] + VAddr: 0x1000 + PAddr: 0x1000 + MemSize: 0x8 + FileSize: 0x8 + FirstSec: .eh_frame_hdr + LastSec: .eh_frame_hdr diff --git a/llvm/test/tools/obj2yaml/ELF/bb-addr-map-pgo-analysis-map.yaml b/llvm/test/tools/obj2yaml/ELF/bb-addr-map-pgo-analysis-map.yaml index 645507af080cb..2b55b2a383f2f 100644 --- a/llvm/test/tools/obj2yaml/ELF/bb-addr-map-pgo-analysis-map.yaml +++ b/llvm/test/tools/obj2yaml/ELF/bb-addr-map-pgo-analysis-map.yaml @@ -14,7 +14,7 @@ # VALID-NEXT: - Name: .llvm_bb_addr_map # VALID-NEXT: Type: SHT_LLVM_BB_ADDR_MAP # VALID-NEXT: Entries: -# VALID-NEXT: - Version: 2 +# VALID-NEXT: - Version: 5 # VALID-NEXT: Feature: 0x87 ## The 'BaseAddress' field is omitted when it's zero. # VALID-NEXT: BBRanges: @@ -31,7 +31,7 @@ # VALID-NEXT: AddressOffset: 0xFFFFFFFFFFFFFFF7 # VALID-NEXT: Size: 0xFFFFFFFFFFFFFFF8 # VALID-NEXT: Metadata: 0xFFFFFFFFFFFFFFF9 -# VALID-NEXT: - Version: 2 +# VALID-NEXT: - Version: 5 # VALID-NEXT: Feature: 0xA # VALID-NEXT: BBRanges: # VALID-NEXT: - BaseAddress: 0xFFFFFFFFFFFFFF20 @@ -74,7 +74,7 @@ Sections: Type: SHT_LLVM_BB_ADDR_MAP ShSize: [[SIZE=]] Entries: - - Version: 2 + - Version: 5 Feature: 0x87 BBRanges: - BaseAddress: 0x0 @@ -91,7 +91,7 @@ Sections: AddressOffset: 0xFFFFFFFFFFFFFFF7 Size: 0xFFFFFFFFFFFFFFF8 Metadata: 0xFFFFFFFFFFFFFFF9 - - Version: 2 + - Version: 5 Feature: 0xA BBRanges: - BaseAddress: 0xFFFFFFFFFFFFFF20 diff --git a/llvm/tools/llvm-ir2vec/Bindings/PyIR2Vec.cpp b/llvm/tools/llvm-ir2vec/Bindings/PyIR2Vec.cpp index 530adee8e052e..5032a053ce7b6 100644 --- a/llvm/tools/llvm-ir2vec/Bindings/PyIR2Vec.cpp +++ b/llvm/tools/llvm-ir2vec/Bindings/PyIR2Vec.cpp @@ -13,6 +13,7 @@ #include "llvm/Support/SourceMgr.h" #include +#include #include #include @@ -42,12 +43,18 @@ class PyIR2VecTool { std::unique_ptr Ctx; std::unique_ptr M; std::unique_ptr Tool; + IR2VecKind OutputEmbeddingMode; public: PyIR2VecTool(const std::string &Filename, const std::string &Mode, const std::string &VocabPath) { - if (Mode != "sym" && Mode != "fa") + OutputEmbeddingMode = [](const std::string &Mode) -> IR2VecKind { + if (Mode == "sym") + return IR2VecKind::Symbolic; + if (Mode == "fa") + return IR2VecKind::FlowAware; throw nb::value_error("Invalid mode. Use 'sym' or 'fa'"); + }(Mode); if (VocabPath.empty()) throw nb::value_error("Empty Vocab Path not allowed"); @@ -62,6 +69,56 @@ class PyIR2VecTool { .c_str()); } } + + nb::dict getFuncEmbMap() { + auto ToolFuncEmbMap = Tool->getFunctionEmbeddingsMap(OutputEmbeddingMode); + + if (!ToolFuncEmbMap) + throw nb::value_error(toString(ToolFuncEmbMap.takeError()).c_str()); + + nb::dict NbFuncEmbMap; + + for (const auto &[FuncPtr, FuncEmb] : *ToolFuncEmbMap) { + auto FuncEmbVec = FuncEmb.getData(); + double *NbFuncEmbVec = new double[FuncEmbVec.size()]; + std::copy(FuncEmbVec.begin(), FuncEmbVec.end(), NbFuncEmbVec); + + auto NbArray = nb::ndarray( + NbFuncEmbVec, {FuncEmbVec.size()}, + nb::capsule(NbFuncEmbVec, [](void *P) noexcept { + delete[] static_cast(P); + })); + + NbFuncEmbMap[nb::str(FuncPtr->getName().str().c_str())] = NbArray; + } + + return NbFuncEmbMap; + } + + nb::ndarray getFuncEmb(const std::string &FuncName) { + const Function *F = M->getFunction(FuncName); + + if (!F) + throw nb::value_error( + ("Function '" + FuncName + "' not found in module").c_str()); + + auto ToolFuncEmb = Tool->getFunctionEmbedding(*F, OutputEmbeddingMode); + + if (!ToolFuncEmb) + throw nb::value_error(toString(ToolFuncEmb.takeError()).c_str()); + + auto FuncEmbVec = ToolFuncEmb->getData(); + double *NbFuncEmbVec = new double[FuncEmbVec.size()]; + std::copy(FuncEmbVec.begin(), FuncEmbVec.end(), NbFuncEmbVec); + + auto NbArray = nb::ndarray( + NbFuncEmbVec, {FuncEmbVec.size()}, + nb::capsule(NbFuncEmbVec, [](void *P) noexcept { + delete[] static_cast(P); + })); + + return NbArray; + } }; } // namespace @@ -72,7 +129,15 @@ NB_MODULE(ir2vec, m) { nb::class_(m, "IR2VecTool") .def(nb::init(), - nb::arg("filename"), nb::arg("mode"), nb::arg("vocabPath")); + nb::arg("filename"), nb::arg("mode"), nb::arg("vocabPath")) + .def("getFuncEmbMap", &PyIR2VecTool::getFuncEmbMap, + "Generate function-level embeddings for all functions\n" + "Returns: dict[str, ndarray[float64]] - " + "{function_name: embedding}") + .def("getFuncEmb", &PyIR2VecTool::getFuncEmb, nb::arg("funcName"), + "Generate embedding for a single function by name\n" + "Args: funcName (str) - IR-Name of the function\n" + "Returns: ndarray[float64] - Function embedding vector"); m.def( "initEmbedding", diff --git a/llvm/tools/llvm-ir2vec/lib/Utils.cpp b/llvm/tools/llvm-ir2vec/lib/Utils.cpp index 190d9259e45b3..50b71d6c134d6 100644 --- a/llvm/tools/llvm-ir2vec/lib/Utils.cpp +++ b/llvm/tools/llvm-ir2vec/lib/Utils.cpp @@ -26,6 +26,7 @@ #include "llvm/IR/Type.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Errc.h" +#include "llvm/Support/Error.h" #include "llvm/Support/raw_ostream.h" #include "llvm/CodeGen/MIR2Vec.h" @@ -151,9 +152,48 @@ void IR2VecTool::writeEntitiesToStream(raw_ostream &OS) { OS << Entities[EntityID] << '\t' << EntityID << '\n'; } +Expected IR2VecTool::getFunctionEmbedding(const Function &F, + IR2VecKind Kind) const { + if (!Vocab || !Vocab->isValid()) + return createStringError( + errc::invalid_argument, + "Vocabulary is not valid. IR2VecTool not initialized."); + + if (F.isDeclaration()) + return createStringError(errc::invalid_argument, + "Function is a declaration."); + + auto Emb = Embedder::create(Kind, F, *Vocab); + if (!Emb) + return createStringError(errc::invalid_argument, + "Failed to create embedder for function '%s'.", + F.getName().str().c_str()); + + return Emb->getFunctionVector(); +} + +Expected +IR2VecTool::getFunctionEmbeddingsMap(IR2VecKind Kind) const { + if (!Vocab || !Vocab->isValid()) + return createStringError( + errc::invalid_argument, + "Vocabulary is not valid. IR2VecTool not initialized."); + + FuncEmbMap Result; + + for (const Function &F : M.getFunctionDefs()) { + auto Emb = getFunctionEmbedding(F, Kind); + if (!Emb) + return Emb.takeError(); + Result.try_emplace(&F, std::move(*Emb)); + } + + return Result; +} + void IR2VecTool::writeEmbeddingsToStream(raw_ostream &OS, EmbeddingLevel Level) const { - if (!Vocab->isValid()) { + if (!Vocab || !Vocab->isValid()) { WithColor::error(errs(), ToolName) << "Vocabulary is not valid. IR2VecTool not initialized.\n"; return; @@ -170,6 +210,7 @@ void IR2VecTool::writeEmbeddingsToStream(const Function &F, raw_ostream &OS, << "Vocabulary is not valid. IR2VecTool not initialized.\n"; return; } + if (F.isDeclaration()) { OS << "Function " << F.getName() << " is a declaration, skipping.\n"; return; diff --git a/llvm/tools/llvm-ir2vec/lib/Utils.h b/llvm/tools/llvm-ir2vec/lib/Utils.h index d9715b03c3082..d535f5fd5bb74 100644 --- a/llvm/tools/llvm-ir2vec/lib/Utils.h +++ b/llvm/tools/llvm-ir2vec/lib/Utils.h @@ -16,6 +16,7 @@ #define LLVM_TOOLS_LLVM_IR2VEC_UTILS_UTILS_H #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/Analysis/IR2Vec.h" #include "llvm/CodeGen/MIR2Vec.h" #include "llvm/CodeGen/MIRParser/MIRParser.h" @@ -72,6 +73,7 @@ struct TripletResult { /// Entity mappings: [entity_name] using EntityList = std::vector; +using FuncEmbMap = DenseMap; namespace ir2vec { @@ -112,6 +114,13 @@ class IR2VecTool { /// Returns EntityList containing all entity strings static EntityList collectEntityMappings(); + // Get embedding for a single function + Expected getFunctionEmbedding(const Function &F, + IR2VecKind Kind) const; + + /// Get embeddings for all functions in the module + Expected getFunctionEmbeddingsMap(IR2VecKind Kind) const; + /// Dump entity ID to string mappings static void writeEntitiesToStream(raw_ostream &OS); diff --git a/llvm/tools/llvm-objcopy/CommonOpts.td b/llvm/tools/llvm-objcopy/CommonOpts.td index 7359e628582d2..76bc00285f962 100644 --- a/llvm/tools/llvm-objcopy/CommonOpts.td +++ b/llvm/tools/llvm-objcopy/CommonOpts.td @@ -50,7 +50,8 @@ def p : Flag<["-"], "p">, def strip_all : Flag<["--"], "strip-all">, HelpText<"For ELF, remove all symbols and non-alloc sections not within " "segments, except for .gnu.warning*, .ARM.attribute, and the section name table. " - "For COFF and Mach-O, remove all symbols, debug sections, and relocations">; + "For COFF and Mach-O, remove all symbols, debug sections, and relocations. " + "For WebAssembly, remove all custom sections except for metadata.code.*">; def strip_all_gnu : Flag<["--"], "strip-all-gnu">, diff --git a/llvm/tools/llvm-objdump/SourcePrinter.cpp b/llvm/tools/llvm-objdump/SourcePrinter.cpp index a4891a3620ee9..a92b955a49cde 100644 --- a/llvm/tools/llvm-objdump/SourcePrinter.cpp +++ b/llvm/tools/llvm-objdump/SourcePrinter.cpp @@ -688,7 +688,7 @@ void SourcePrinter::printSourceLine(formatted_raw_ostream &OS, printLines(OS, Address, LineInfo, Delimiter, LEP); if (PrintSource) printSources(OS, LineInfo, ObjectFilename, Delimiter, LEP); - OldLineInfo = LineInfo; + OldLineInfo = std::move(LineInfo); } void SourcePrinter::printLines(formatted_raw_ostream &OS, diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp index aebe33eddfbe9..87e1847f39ae1 100644 --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -73,6 +73,7 @@ #include "llvm/Support/TargetSelect.h" #include "llvm/Support/WithColor.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/TargetParser/AVRTargetParser.h" #include "llvm/TargetParser/Host.h" #include "llvm/TargetParser/Triple.h" #include @@ -2683,6 +2684,21 @@ static void disassembleObject(ObjectFile *Obj, bool InlineRelocs, Features.AddFeature(MAttrs[I]); } else if (MCPU.empty() && Obj->makeTriple().isAArch64()) { Features.AddFeature("+all"); + } else if (MCPU.empty() && Obj->makeTriple().isAVR()) { + if (const auto *Elf = dyn_cast(Obj)) { + if (Expected VersionOrErr = AVR::getFeatureSetFromEFlag( + Elf->getPlatformFlags() & ELF::EF_AVR_ARCH_MASK)) { + Features.AddFeature('+' + *VersionOrErr); + } else { + // If the architecture version cannot be determined from ELF flags, + // fall back to the baseline "avr0" ISA. The AVR disassembler + // requires a valid feature specification to function correctly. + reportWarning(toString(VersionOrErr.takeError()) + + ": defaulting to avr0", + Obj->getFileName()); + Features.AddFeature("+avr0"); + } + } } if (MCPU.empty()) diff --git a/llvm/tools/llvm-pdbutil/BytesOutputStyle.cpp b/llvm/tools/llvm-pdbutil/BytesOutputStyle.cpp index 4c851e14a12dd..3adc6593ac884 100644 --- a/llvm/tools/llvm-pdbutil/BytesOutputStyle.cpp +++ b/llvm/tools/llvm-pdbutil/BytesOutputStyle.cpp @@ -370,7 +370,7 @@ static void iterateModules(PDBFile &File, LinePrinter &P, uint32_t IndentLevel, Callback); } else { uint32_t Count = Modules.getModuleCount(); - uint32_t Digits = NumDigits(Count); + uint32_t Digits = NumDigitsBase10(Count); for (uint32_t I = 0; I < Count; ++I) { iterateOneModule(File, P, Modules, I, Digits, IndentLevel, Callback); } diff --git a/llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp b/llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp index d836d98e1b0d0..4e6b411a45216 100644 --- a/llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp +++ b/llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp @@ -363,16 +363,16 @@ Error DumpOutputStyle::dumpStreamSummary() { for (uint32_t StreamIdx = 0; StreamIdx < StreamCount; ++StreamIdx) { P.formatLine( "Stream {0} ({1} bytes): [{2}]", - fmt_align(StreamIdx, AlignStyle::Right, NumDigits(StreamCount)), + fmt_align(StreamIdx, AlignStyle::Right, NumDigitsBase10(StreamCount)), fmt_align(getPdb().getStreamByteSize(StreamIdx), AlignStyle::Right, - NumDigits(MaxStreamSize)), + NumDigitsBase10(MaxStreamSize)), StreamPurposes[StreamIdx].getLongName()); if (opts::dump::DumpStreamBlocks) { auto Blocks = getPdb().getStreamBlockList(StreamIdx); std::vector BV(Blocks.begin(), Blocks.end()); P.formatLine(" {0} Blocks: [{1}]", - fmt_repeat(' ', NumDigits(StreamCount)), + fmt_repeat(' ', NumDigitsBase10(StreamCount)), make_range(BV.begin(), BV.end())); } } @@ -572,7 +572,7 @@ Error DumpOutputStyle::dumpSymbolStats() { if (StreamIdx == kInvalidStreamIndex) { P.formatLine( "Mod {0} (debug info not present): [{1}]", - fmt_align(Modi, AlignStyle::Right, NumDigits(ModCount)), + fmt_align(Modi, AlignStyle::Right, NumDigitsBase10(ModCount)), Desc.getModuleName()); return Error::success(); } @@ -749,11 +749,11 @@ Error DumpOutputStyle::dumpUdtStats() { // separators. StringRef CountHeader("Count"); StringRef SizeHeader("Size"); - size_t CD = NumDigits(UdtStats.Totals.Count); + size_t CD = NumDigitsBase10(UdtStats.Totals.Count); CD += (CD - 1) / 3; CD = std::max(CD, CountHeader.size()); - size_t SD = NumDigits(UdtStats.Totals.Size); + size_t SD = NumDigitsBase10(UdtStats.Totals.Size); SD += (SD - 1) / 3; SD = std::max(SD, SizeHeader.size()); @@ -1071,7 +1071,7 @@ Error DumpOutputStyle::dumpStringTableFromPdb() { P.formatLine("Empty"); else { auto MaxID = llvm::max_element(IS->name_ids()); - uint32_t Digits = NumDigits(*MaxID); + uint32_t Digits = NumDigitsBase10(*MaxID); P.formatLine("{0} | {1}", fmt_align("ID", AlignStyle::Right, Digits), "String"); @@ -1205,7 +1205,8 @@ dumpFullTypeStream(LinePrinter &Printer, LazyRandomTypeCollection &Types, TpiStream *Stream, bool Bytes, bool Extras) { Printer.formatLine("Showing {0:N} records", NumTypeRecords); - uint32_t Width = NumDigits(TypeIndex::FirstNonSimpleIndex + NumTypeRecords); + uint32_t Width = + NumDigitsBase10(TypeIndex::FirstNonSimpleIndex + NumTypeRecords); MinimalTypeDumpVisitor V(Printer, Width + 2, Bytes, Extras, Types, RefTracker, NumHashBuckets, HashValues, Stream); @@ -1221,8 +1222,8 @@ static void dumpPartialTypeStream(LinePrinter &Printer, TypeReferenceTracker *RefTracker, TpiStream &Stream, ArrayRef TiList, bool Bytes, bool Extras, bool Deps) { - uint32_t Width = - NumDigits(TypeIndex::FirstNonSimpleIndex + Stream.getNumTypeRecords()); + uint32_t Width = NumDigitsBase10(TypeIndex::FirstNonSimpleIndex + + Stream.getNumTypeRecords()); MinimalTypeDumpVisitor V(Printer, Width + 2, Bytes, Extras, Types, RefTracker, Stream.getNumHashBuckets(), Stream.getHashValues(), diff --git a/llvm/tools/llvm-pdbutil/MinimalTypeDumper.cpp b/llvm/tools/llvm-pdbutil/MinimalTypeDumper.cpp index db3a752d58165..5f0f95b3775e6 100644 --- a/llvm/tools/llvm-pdbutil/MinimalTypeDumper.cpp +++ b/llvm/tools/llvm-pdbutil/MinimalTypeDumper.cpp @@ -309,7 +309,7 @@ Error MinimalTypeDumpVisitor::visitKnownRecord(CVType &CVR, return Error::success(); auto Max = llvm::max_element(Indices); - uint32_t W = NumDigits(Max->getIndex()) + 2; + uint32_t W = NumDigitsBase10(Max->getIndex()) + 2; for (auto I : Indices) P.formatLine("{0}: `{1}`", fmt_align(I, AlignStyle::Right, W), @@ -324,7 +324,7 @@ Error MinimalTypeDumpVisitor::visitKnownRecord(CVType &CVR, return Error::success(); auto Max = llvm::max_element(Indices); - uint32_t W = NumDigits(Max->getIndex()) + 2; + uint32_t W = NumDigitsBase10(Max->getIndex()) + 2; for (auto I : Indices) P.formatLine("{0}: `{1}`", fmt_align(I, AlignStyle::Right, W), @@ -494,7 +494,7 @@ Error MinimalTypeDumpVisitor::visitKnownRecord(CVType &CVR, return Error::success(); auto Max = llvm::max_element(Indices); - uint32_t W = NumDigits(Max->getIndex()) + 2; + uint32_t W = NumDigitsBase10(Max->getIndex()) + 2; for (auto I : Indices) P.formatLine("{0}: `{1}`", fmt_align(I, AlignStyle::Right, W), diff --git a/llvm/tools/llvm-profgen/CMakeLists.txt b/llvm/tools/llvm-profgen/CMakeLists.txt index 354c63f409ffe..a28cbbd6d7cbd 100644 --- a/llvm/tools/llvm-profgen/CMakeLists.txt +++ b/llvm/tools/llvm-profgen/CMakeLists.txt @@ -4,6 +4,7 @@ set(LLVM_LINK_COMPONENTS AllTargetsDisassemblers AllTargetsInfos DebugInfoDWARF + DebugInfoPDB Core MC IPO diff --git a/llvm/tools/llvm-profgen/ProfiledBinary.cpp b/llvm/tools/llvm-profgen/ProfiledBinary.cpp index ad301d09f7dab..915e991e4068c 100644 --- a/llvm/tools/llvm-profgen/ProfiledBinary.cpp +++ b/llvm/tools/llvm-profgen/ProfiledBinary.cpp @@ -11,6 +11,9 @@ #include "MissingFrameInferrer.h" #include "Options.h" #include "ProfileGenerator.h" +#include "llvm/DebugInfo/PDB/IPDBSession.h" +#include "llvm/DebugInfo/PDB/PDB.h" +#include "llvm/DebugInfo/PDB/PDBSymbolFunc.h" #include "llvm/DebugInfo/Symbolize/SymbolizableModule.h" #include "llvm/Demangle/Demangle.h" #include "llvm/IR/DebugInfoMetadata.h" @@ -39,10 +42,8 @@ cl::opt ShowSourceLocations("show-source-locations", cl::opt LoadFunctionFromSymbol( "load-function-from-symbol", cl::init(true), - cl::desc( - "Gather additional binary function info from symbols (e.g. .symtab) in " - "case dwarf info is incomplete. Only support binaries in ELF format " - "with pseudo probe, for other formats, this flag will be a no-op."), + cl::desc("Gather additional binary function info from symbols (e.g. " + "symtab) in case dwarf info is incomplete."), cl::cat(ProfGenCategory)); static cl::opt @@ -867,19 +868,43 @@ void ProfiledBinary::loadSymbolsFromSymtab(const ObjectFile *Obj) { // Compiler/LTO internal ".llvm.", ".part.", ".isra.", ".constprop.", ".lto_priv."}); StringRef FileName = Obj->getFileName(); - // Only apply this to ELF binary. e.g. COFF file format doesn't have `size` - // field in the symbol table. - bool IsELFObject = isa(Obj); - if (!IsELFObject) - return; + + // COFF symtab does not have size field. Try to load size from PDB instead. + std::unique_ptr PDBSession; + if (auto *COFFObj = dyn_cast(Obj)) { + if (auto E = pdb::loadDataForEXE(pdb::PDB_ReaderType::Native, FileName, + PDBSession)) { + StringRef PdbPath; + const codeview::DebugInfo *PdbInfo; + if (auto Err = COFFObj->getDebugPDBInfo(PdbInfo, PdbPath)) + consumeError(std::move(Err)); + + auto Style = PdbPath.starts_with("/") ? sys::path::Style::posix + : sys::path::Style::windows; + WithColor::warning() << "Cannot load PDB file " + << sys::path::filename(PdbPath, Style) << " for " + << FileName << ": " << E << "\n"; + consumeError(std::move(E)); + } else { + PDBSession->setLoadAddress(FirstLoadableAddress); + } + } + for (const SymbolRef &Symbol : Obj->symbols()) { const SymbolRef::Type Type = unwrapOrError(Symbol.getType(), FileName); const uint64_t StartAddr = unwrapOrError(Symbol.getAddress(), FileName); const StringRef Name = unwrapOrError(Symbol.getName(), FileName); uint64_t Size = 0; - if (LLVM_LIKELY(IsELFObject)) { + if (isa(Obj)) { ELFSymbolRef ElfSymbol(Symbol); Size = ElfSymbol.getSize(); + } else if (PDBSession) { + if (std::unique_ptr Sym = PDBSession->findSymbolByAddress( + StartAddr, pdb::PDB_SymType::Function)) { + auto FuncSym = cast(std::move(Sym)); + if (StartAddr == FuncSym->getVirtualAddress()) + Size = FuncSym->getLength(); + } } if (Size == 0 || Type != SymbolRef::ST_Function) @@ -915,15 +940,15 @@ void ProfiledBinary::loadSymbolsFromSymtab(const ObjectFile *Obj) { FRange.EndAddress = EndAddr; } else if (SymName != Range->getFuncName()) { - // Function range already found from DWARF, but the symbol name from - // symbol table is inconsistent with debug info. Log this discrepancy and - // the alternative function GUID. + // Function range already found from DWARF or symtab, but the symbol name + // from symbol table is inconsistent with the existing name associated + // with the range. Log this discrepancy and the alternative function GUID. if (ShowDetailedWarning) WithColor::warning() << "Conflicting name for symbol " << Name << " with range (" << format("%8" PRIx64, StartAddr) << ", " << format("%8" PRIx64, EndAddr) << ")" - << ", but the DWARF symbol " << Range->getFuncName() + << ", but the existing symbol " << Range->getFuncName() << " indicates an overlapping range (" << format("%8" PRIx64, Range->StartAddress) << ", " << format("%8" PRIx64, Range->EndAddress) << ")\n"; @@ -937,12 +962,13 @@ void ProfiledBinary::loadSymbolsFromSymtab(const ObjectFile *Obj) { } else if (StartAddr != Range->StartAddress && EndAddr != Range->EndAddress) { - // Function already found in DWARF, but the address range from symbol - // table conflicts/overlaps with the debug info. + // Function already found in DWARF or symtab, but the address range from + // symbol table conflicts/overlaps with the existing one. WithColor::warning() << "Conflicting range for symbol " << Name << " with range (" << format("%8" PRIx64, StartAddr) << ", " << format("%8" PRIx64, EndAddr) << ")" - << ", but the DWARF symbol " << Range->getFuncName() + << ", but the existing symbol " + << Range->getFuncName() << " indicates another range (" << format("%8" PRIx64, Range->StartAddress) << ", " << format("%8" PRIx64, Range->EndAddress) << ")\n"; diff --git a/llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h b/llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h index 85c4165de4aa9..3a454807172e0 100644 --- a/llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h +++ b/llvm/tools/llvm-readobj/DwarfCFIEHPrinter.h @@ -129,7 +129,12 @@ void PrinterContext::printEHFrameHdr(const Elf_Phdr *EHFramePHdr) const { uint64_t EHFramePtrEnc = DE.getU8(&Offset); W.startLine() << format("eh_frame_ptr_enc: 0x%" PRIx64 "\n", EHFramePtrEnc); - if (EHFramePtrEnc != (dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4)) + unsigned EHFramePtrSize = 0; + if (EHFramePtrEnc == (dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4)) + EHFramePtrSize = 4; + else if (EHFramePtrEnc == (dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8)) + EHFramePtrSize = 8; + else reportError(object::createError("unexpected encoding eh_frame_ptr_enc"), ObjF.getFileName()); @@ -141,11 +146,18 @@ void PrinterContext::printEHFrameHdr(const Elf_Phdr *EHFramePHdr) const { uint64_t TableEnc = DE.getU8(&Offset); W.startLine() << format("table_enc: 0x%" PRIx64 "\n", TableEnc); - if (TableEnc != (dwarf::DW_EH_PE_datarel | dwarf::DW_EH_PE_sdata4)) - reportError(object::createError("unexpected encoding table_enc"), + unsigned TableEntrySize = 0; + if (TableEnc == (dwarf::DW_EH_PE_datarel | dwarf::DW_EH_PE_sdata4)) + TableEntrySize = 4; + else if (TableEnc == (dwarf::DW_EH_PE_datarel | dwarf::DW_EH_PE_sdata8)) + TableEntrySize = 8; + else + reportError(object::createError("unexpected encoding table_enc 0x" + + Twine::utohexstr(TableEnc)), ObjF.getFileName()); - auto EHFramePtr = DE.getSigned(&Offset, 4) + EHFrameHdrAddress + 4; + auto EHFramePtr = + DE.getSigned(&Offset, EHFramePtrSize) + EHFrameHdrAddress + 4; W.startLine() << format("eh_frame_ptr: 0x%" PRIx64 "\n", EHFramePtr); auto FDECount = DE.getUnsigned(&Offset, 4); @@ -153,12 +165,13 @@ void PrinterContext::printEHFrameHdr(const Elf_Phdr *EHFramePHdr) const { unsigned NumEntries = 0; uint64_t PrevPC = 0; - while (Offset + 8 <= EHFramePHdr->p_memsz && NumEntries < FDECount) { + while (Offset + 2 * TableEntrySize <= EHFramePHdr->p_memsz && + NumEntries < FDECount) { DictScope D(W, std::string("entry ") + std::to_string(NumEntries)); - auto InitialPC = DE.getSigned(&Offset, 4) + EHFrameHdrAddress; + auto InitialPC = DE.getSigned(&Offset, TableEntrySize) + EHFrameHdrAddress; W.startLine() << format("initial_location: 0x%" PRIx64 "\n", InitialPC); - auto Address = DE.getSigned(&Offset, 4) + EHFrameHdrAddress; + auto Address = DE.getSigned(&Offset, TableEntrySize) + EHFrameHdrAddress; W.startLine() << format("address: 0x%" PRIx64 "\n", Address); if (InitialPC < PrevPC) diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp index a7e10718942dd..fe6dd0297ff6b 100644 --- a/llvm/tools/llvm-readobj/ELFDumper.cpp +++ b/llvm/tools/llvm-readobj/ELFDumper.cpp @@ -1664,6 +1664,7 @@ const EnumEntry ElfHeaderMipsFlags[] = { ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX1151, "gfx1151"), \ ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX1152, "gfx1152"), \ ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX1153, "gfx1153"), \ + ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX1170, "gfx1170"), \ ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX1200, "gfx1200"), \ ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX1201, "gfx1201"), \ ENUM_ENT(EF_AMDGPU_MACH_AMDGCN_GFX1250, "gfx1250"), \ diff --git a/llvm/tools/llvm-remarkutil/RemarkInstructionMix.cpp b/llvm/tools/llvm-remarkutil/RemarkInstructionMix.cpp index 7c8ac474c0fdb..62310440ef4fb 100644 --- a/llvm/tools/llvm-remarkutil/RemarkInstructionMix.cpp +++ b/llvm/tools/llvm-remarkutil/RemarkInstructionMix.cpp @@ -111,7 +111,7 @@ static Error tryInstructionMix() { Mix.begin(), Mix.end(), 1, [](unsigned MaxValue, const MixEntry &Elt) { return std::max(MaxValue, Elt.second); }); - unsigned ValueWidth = std::log10(MaxValue) + 1; + unsigned ValueWidth = NumDigitsBase10(MaxValue); FOS << "Instruction"; FOS.PadToColumn(MaxMnemonic + 1) << "Count\n"; FOS << "-----------"; diff --git a/llvm/tools/obj2yaml/elf2yaml.cpp b/llvm/tools/obj2yaml/elf2yaml.cpp index 4364d15a8b455..83d828dfb81c8 100644 --- a/llvm/tools/obj2yaml/elf2yaml.cpp +++ b/llvm/tools/obj2yaml/elf2yaml.cpp @@ -900,7 +900,7 @@ ELFDumper::dumpBBAddrMapSection(const Elf_Shdr *Shdr) { while (Cur && Cur.tell() < Content.size()) { if (Shdr->sh_type == ELF::SHT_LLVM_BB_ADDR_MAP) { Version = Data.getU8(Cur); - if (Cur && Version > 4) + if (Cur && Version > 5) return createStringError( errc::invalid_argument, "invalid SHT_LLVM_BB_ADDR_MAP section version: " + diff --git a/llvm/tools/obj2yaml/offload2yaml.cpp b/llvm/tools/obj2yaml/offload2yaml.cpp index 2b63e1278cd22..47e86f75514c0 100644 --- a/llvm/tools/obj2yaml/offload2yaml.cpp +++ b/llvm/tools/obj2yaml/offload2yaml.cpp @@ -16,49 +16,49 @@ using namespace llvm; namespace { -void populateYAML(OffloadYAML::Binary &YAMLBinary, object::OffloadBinary &OB, +void populateYAML(OffloadYAML::Binary &YAMLBinary, + ArrayRef> OBinaries, UniqueStringSaver Saver) { - YAMLBinary.Members.emplace_back(); - auto &Member = YAMLBinary.Members.back(); - Member.ImageKind = OB.getImageKind(); - Member.OffloadKind = OB.getOffloadKind(); - Member.Flags = OB.getFlags(); - if (!OB.strings().empty()) { - Member.StringEntries = std::vector(); - for (const auto &Entry : OB.strings()) - Member.StringEntries->emplace_back(OffloadYAML::Binary::StringEntry( - {Saver.save(Entry.first), Saver.save(Entry.second)})); + for (const auto &OBinaryPtr : OBinaries) { + object::OffloadBinary &OB = *OBinaryPtr; + + YAMLBinary.Members.emplace_back(); + auto &Member = YAMLBinary.Members.back(); + Member.ImageKind = OB.getImageKind(); + Member.OffloadKind = OB.getOffloadKind(); + Member.Flags = OB.getFlags(); + if (!OB.strings().empty()) { + Member.StringEntries = std::vector(); + for (const auto &StringEntry : OB.strings()) + Member.StringEntries->emplace_back(OffloadYAML::Binary::StringEntry( + {Saver.save(StringEntry.first), Saver.save(StringEntry.second)})); + } + + if (!OB.getImage().empty()) + Member.Content = arrayRefFromStringRef(OB.getImage()); } - - if (!OB.getImage().empty()) - Member.Content = arrayRefFromStringRef(OB.getImage()); } Expected dump(MemoryBufferRef Source, UniqueStringSaver Saver) { - Expected> OB = - object::OffloadBinary::create(Source); - if (!OB) - return OB.takeError(); - std::unique_ptr YAMLBinary = std::make_unique(); YAMLBinary->Members = std::vector(); uint64_t Offset = 0; - while (Offset < (*OB)->getMemoryBufferRef().getBufferSize()) { + while (Offset < Source.getBufferSize()) { MemoryBufferRef Buffer = MemoryBufferRef( - (*OB)->getData().drop_front(Offset), (*OB)->getFileName()); - auto BinaryOrErr = object::OffloadBinary::create(Buffer); - if (!BinaryOrErr) - return BinaryOrErr.takeError(); - - object::OffloadBinary &Binary = **BinaryOrErr; + Source.getBuffer().drop_front(Offset), Source.getBufferIdentifier()); + auto BinariesOrErr = object::OffloadBinary::create(Buffer); + if (!BinariesOrErr) + return BinariesOrErr.takeError(); - populateYAML(*YAMLBinary, Binary, Saver); + SmallVector> &Binaries = + *BinariesOrErr; + populateYAML(*YAMLBinary, Binaries, Saver); - Offset += Binary.getSize(); + Offset += Binaries[0]->getSize(); } return YAMLBinary.release(); diff --git a/llvm/unittests/ADT/FloatingPointMode.cpp b/llvm/unittests/ADT/FloatingPointMode.cpp index cbdd64aeb00cd..3f9e71a16f523 100644 --- a/llvm/unittests/ADT/FloatingPointMode.cpp +++ b/llvm/unittests/ADT/FloatingPointMode.cpp @@ -25,6 +25,10 @@ TEST(FloatingPointModeTest, ParseDenormalFPAttributeComponent) { parseDenormalFPAttributeComponent("preserve-sign")); EXPECT_EQ(DenormalMode::PositiveZero, parseDenormalFPAttributeComponent("positive-zero")); + EXPECT_EQ(DenormalMode::PreserveSign, + parseDenormalFPAttributeComponent("preservesign")); + EXPECT_EQ(DenormalMode::PositiveZero, + parseDenormalFPAttributeComponent("positivezero")); EXPECT_EQ(DenormalMode::Dynamic, parseDenormalFPAttributeComponent("dynamic")); EXPECT_EQ(DenormalMode::Invalid, parseDenormalFPAttributeComponent("foo")); @@ -102,10 +106,16 @@ TEST(FloatingPointModeTest, RenderDenormalFPAttribute) { EXPECT_EQ( "preserve-sign,preserve-sign", DenormalMode(DenormalMode::PreserveSign, DenormalMode::PreserveSign).str()); + EXPECT_EQ("preserve-sign,preserve-sign", + DenormalMode(DenormalMode::PreserveSign, DenormalMode::PreserveSign) + .str()); EXPECT_EQ( "positive-zero,positive-zero", DenormalMode(DenormalMode::PositiveZero, DenormalMode::PositiveZero).str()); + EXPECT_EQ("positive-zero,positive-zero", + DenormalMode(DenormalMode::PositiveZero, DenormalMode::PositiveZero) + .str()); EXPECT_EQ( "ieee,preserve-sign", diff --git a/llvm/unittests/AsmParser/AsmParserTest.cpp b/llvm/unittests/AsmParser/AsmParserTest.cpp index f67ed150817f2..1ef1fa36ebdcf 100644 --- a/llvm/unittests/AsmParser/AsmParserTest.cpp +++ b/llvm/unittests/AsmParser/AsmParserTest.cpp @@ -495,9 +495,9 @@ TEST(AsmParserTest, DIExpressionBodyAtBeginningWithSlotMappingParsing) { } while (false) TEST(AsmParserTest, ParserObjectLocations) { - StringRef Source = "define i32 @main() {\n" + StringRef Source = "define i32 @main(i32 %arg, i64) {\n" "entry:\n" - " %a = add i32 1, 2\n" + " %a = add i32 1, %arg\n" " ret i32 %a\n" "}\n"; LLVMContext Ctx; @@ -527,17 +527,36 @@ TEST(AsmParserTest, ParserObjectLocations) { ParserContext.getBlockAtLocation(*MaybeEntryBBLoc)); SmallVector InstructionLocations = { - FileLocRange(FileLoc{2, 4}, FileLoc{2, 21}), + FileLocRange(FileLoc{2, 4}, FileLoc{2, 24}), FileLocRange(FileLoc{3, 4}, FileLoc{3, 14})}; for (const auto &[Inst, ExpectedLoc] : zip(EntryBB, InstructionLocations)) { - auto MaybeInstLoc = ParserContext.getInstructionLocation(&Inst); + auto MaybeInstLoc = ParserContext.getInstructionOrArgumentLocation(&Inst); ASSERT_TRUE(MaybeMainLoc.has_value()); auto InstLoc = MaybeInstLoc.value(); ASSERT_EQ_LOC(InstLoc, ExpectedLoc); - ASSERT_EQ(ParserContext.getInstructionAtLocation(MaybeInstLoc->Start), - ParserContext.getInstructionAtLocation(*MaybeInstLoc)); + ASSERT_EQ( + ParserContext.getInstructionOrArgumentAtLocation(MaybeInstLoc->Start), + ParserContext.getInstructionOrArgumentAtLocation(*MaybeInstLoc)); } + + SmallVector> FunctionArgumentLocations = { + FileLocRange(FileLoc{0, 21}, FileLoc{0, 25}), std::nullopt}; + for (const auto &[Arg, ExpectedLoc] : + zip(MainFn->args(), FunctionArgumentLocations)) { + auto MaybeArgLoc = ParserContext.getInstructionOrArgumentLocation(&Arg); + ASSERT_EQ(MaybeArgLoc.has_value(), ExpectedLoc.has_value()); + if (!ExpectedLoc.has_value()) + continue; + auto ArgLoc = MaybeArgLoc.value(); + ASSERT_EQ_LOC(ArgLoc, ExpectedLoc.value()); + ASSERT_EQ(ParserContext.getInstructionOrArgumentAtLocation(ArgLoc.Start), + ParserContext.getInstructionOrArgumentAtLocation(ArgLoc)); + } + ASSERT_EQ(&*MainFn->arg_begin(), + ParserContext.getValueReferencedAtLocation(FileLoc(2, 22))); + ASSERT_EQ(&*EntryBB.begin(), + ParserContext.getValueReferencedAtLocation(FileLoc(3, 13))); } } // end anonymous namespace diff --git a/llvm/unittests/CAS/BuiltinObjectHasherTest.cpp b/llvm/unittests/CAS/BuiltinObjectHasherTest.cpp new file mode 100644 index 0000000000000..23243bd07a1bc --- /dev/null +++ b/llvm/unittests/CAS/BuiltinObjectHasherTest.cpp @@ -0,0 +1,49 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/CAS/BuiltinObjectHasher.h" +#include "llvm/Support/BLAKE3.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Testing/Support/Error.h" +#include "gtest/gtest.h" + +using namespace llvm; +using namespace llvm::cas; + +using HasherT = BLAKE3; +using HashType = BuiltinObjectHasher::HashT; + +TEST(BuiltinObjectHasherTest, Basic) { + unittest::TempFile TmpFile("somefile.o", /*Suffix=*/"", /*Contents=*/"", + /*Unique=*/true); + { + std::error_code EC; + raw_fd_stream Out(TmpFile.path(), EC); + ASSERT_FALSE(EC); + SmallVector Data; + for (unsigned i = 1; i != 201; ++i) { + Data.push_back(i); + } + for (unsigned i = 0; i != 1000; ++i) { + Out.write(Data.data(), Data.size()); + } + } + + ErrorOr> MB = + MemoryBuffer::getFile(TmpFile.path()); + ASSERT_TRUE(!!MB); + ASSERT_NE(*MB, nullptr); + + HashType Hash1 = + BuiltinObjectHasher::hashObject({}, (*MB)->getBuffer()); + std::optional Hash2; + ASSERT_THAT_ERROR( + BuiltinObjectHasher::hashFile(TmpFile.path()).moveInto(Hash2), + Succeeded()); + EXPECT_EQ(Hash1, *Hash2); +} diff --git a/llvm/unittests/CAS/CMakeLists.txt b/llvm/unittests/CAS/CMakeLists.txt index 11def9be5e04c..1bee2324d06c0 100644 --- a/llvm/unittests/CAS/CMakeLists.txt +++ b/llvm/unittests/CAS/CMakeLists.txt @@ -1,4 +1,5 @@ set(ONDISK_CAS_TEST_SOURCES + BuiltinObjectHasherTest.cpp BuiltinUnifiedCASDatabasesTest.cpp OnDiskCASLoggerTest.cpp OnDiskGraphDBTest.cpp diff --git a/llvm/unittests/CAS/OnDiskCASLoggerTest.cpp b/llvm/unittests/CAS/OnDiskCASLoggerTest.cpp index a9aff7bdd328b..7357a976f5f50 100644 --- a/llvm/unittests/CAS/OnDiskCASLoggerTest.cpp +++ b/llvm/unittests/CAS/OnDiskCASLoggerTest.cpp @@ -8,6 +8,7 @@ #include "llvm/CAS/OnDiskCASLogger.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ConvertUTF.h" #include "llvm/Support/Error.h" #include "llvm/Support/LineIterator.h" #include "llvm/Support/MemoryBuffer.h" @@ -17,12 +18,70 @@ #include "llvm/Testing/Support/Error.h" #include "llvm/Testing/Support/SupportHelpers.h" #include "gtest/gtest.h" +#if defined(__APPLE__) +#include +#elif !defined(_MSC_VER) +// Forward declare environ in case it's not provided by stdlib.h. +extern char **environ; +#endif using namespace llvm; using namespace llvm::cas; using namespace llvm::cas::ondisk; using namespace llvm::sys; +class OnDiskCASLoggerTest : public testing::Test { + std::vector EnvTable; + std::vector EnvStorage; + +protected: + void SetUp() override { + auto EnvP = [] { +#if defined(_WIN32) + _wgetenv(L"TMP"); // Populate _wenviron, initially is null + return _wenviron; +#elif defined(__APPLE__) + return *_NSGetEnviron(); +#else + return environ; +#endif + }(); + ASSERT_TRUE(EnvP); + + auto prepareEnvVar = [this](decltype(*EnvP) Var) -> StringRef { +#if defined(_WIN32) + // On Windows convert UTF16 encoded variable to UTF8 + auto Len = wcslen(Var); + ArrayRef Ref{reinterpret_cast(Var), + Len * sizeof(*Var)}; + EnvStorage.emplace_back(); + auto convStatus = llvm::convertUTF16ToUTF8String(Ref, EnvStorage.back()); + EXPECT_TRUE(convStatus); + return EnvStorage.back(); +#else + (void)this; + return StringRef(Var); +#endif + }; + + while (*EnvP != nullptr) { + auto S = prepareEnvVar(*EnvP); + if (!StringRef(S).starts_with("GTEST_")) + EnvTable.emplace_back(S); + ++EnvP; + } + } + + void TearDown() override { + EnvTable.clear(); + EnvStorage.clear(); + } + + void addEnvVar(StringRef Var) { EnvTable.emplace_back(Var); } + + ArrayRef getEnviron() const { return EnvTable; } +}; + #ifndef _WIN32 // windows doesn't support logging yet. static void writeToLog(OnDiskCASLogger *Logger, int NumOpens, int NumEntries) { @@ -97,7 +156,7 @@ static Error checkLog(StringRef Dir) { return Error::success(); } -TEST(OnDiskCASLoggerTest, MultiThread) { +TEST_F(OnDiskCASLoggerTest, MultiThread) { unittest::TempDir Dir("OnDiskCASLoggerTest_MultiThread", /*Unique=*/true); llvm::DefaultThreadPool Pool(llvm::hardware_concurrency()); @@ -133,7 +192,7 @@ static cl::opt CASLogDir("cas-log-dir"); // From TestMain.cpp. extern const char *TestMainArgv0; -TEST(OnDiskCASLoggerTest, MultiProcess) { +TEST_F(OnDiskCASLoggerTest, MultiProcess) { if (!CASLogDir.empty()) { // Child process. std::unique_ptr Logger; @@ -160,8 +219,8 @@ TEST(OnDiskCASLoggerTest, MultiProcess) { SmallVector PIs; for (int I = 0; I < 5; ++I) { bool ExecutionFailed; - auto PI = ExecuteNoWait(Executable, Argv, ArrayRef{}, {}, 0, - &Error, &ExecutionFailed); + auto PI = ExecuteNoWait(Executable, Argv, getEnviron(), {}, 0, &Error, + &ExecutionFailed); ASSERT_FALSE(ExecutionFailed) << Error; PIs.push_back(std::move(PI)); } diff --git a/llvm/unittests/CAS/OnDiskCommonUtils.h b/llvm/unittests/CAS/OnDiskCommonUtils.h index 48a1830f9b219..770f5acbc4749 100644 --- a/llvm/unittests/CAS/OnDiskCommonUtils.h +++ b/llvm/unittests/CAS/OnDiskCommonUtils.h @@ -46,6 +46,21 @@ inline HashType digest(StringRef Data) { return HasherT::hash(arrayRefFromStringRef(Data)); } +inline HashType digestFile(StringRef FilePath) { + std::optional Digest; + EXPECT_THAT_ERROR( + BuiltinObjectHasher::hashFile(FilePath).moveInto(Digest), + Succeeded()); + return *Digest; +} + +inline ObjectID digestFile(OnDiskGraphDB &DB, StringRef FilePath) { + HashType Digest = digestFile(FilePath); + std::optional ID; + EXPECT_THAT_ERROR(DB.getReference(Digest).moveInto(ID), Succeeded()); + return *ID; +} + inline ValueType valueFromString(StringRef S) { ValueType Val = {}; llvm::copy(S.substr(0, sizeof(Val)), Val.data()); diff --git a/llvm/unittests/CAS/OnDiskGraphDBTest.cpp b/llvm/unittests/CAS/OnDiskGraphDBTest.cpp index a4df3c5f6f2b3..4ecb6b6a1e864 100644 --- a/llvm/unittests/CAS/OnDiskGraphDBTest.cpp +++ b/llvm/unittests/CAS/OnDiskGraphDBTest.cpp @@ -8,6 +8,9 @@ #include "CASTestConfig.h" #include "OnDiskCommonUtils.h" +#include "llvm/Support/Alignment.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/Process.h" #include "llvm/Testing/Support/Error.h" #include "llvm/Testing/Support/SupportHelpers.h" #include "gtest/gtest.h" @@ -293,6 +296,211 @@ TEST_F(OnDiskCASTest, OnDiskGraphDBFaultInPolicyConflict) { OnDiskGraphDB::FaultInPolicy::SingleNode); } +static std::unique_ptr createLargeFile(char initChar) { + auto TmpFile = std::make_unique( + "largefile.o", /*Suffix=*/"", /*Contents=*/"", + /*Unique=*/true); + StringRef Path = TmpFile->path(); + std::error_code EC; + raw_fd_stream Out(Path, EC); + EXPECT_FALSE(EC); + SmallString<200> Data; + Data += initChar; + for (unsigned i = 1; i != 200; ++i) { + Data += i; + } + for (unsigned i = 0; i != 1000; ++i) { + Out.write(Data.data(), Data.size()); + } + return TmpFile; +} + +static std::unique_ptr +createLargePageAlignedFile(char initChar) { + auto TmpFile = std::make_unique( + "largepagealignedfile.o", /*Suffix=*/"", /*Contents=*/"", + /*Unique=*/true); + StringRef Path = TmpFile->path(); + std::error_code EC; + raw_fd_stream Out(Path, EC); + EXPECT_FALSE(EC); + SmallString<256> Data; + Data += initChar; + for (unsigned i = 1; i != sys::Process::getPageSizeEstimate(); ++i) { + Data += char(i); + } + for (unsigned i = 0; i != 64; ++i) { + Out.write(Data.data(), Data.size()); + } + Out.close(); + uint64_t FileSize; + EC = sys::fs::file_size(Path, FileSize); + EXPECT_FALSE(EC); + assert(isAligned(Align(sys::Process::getPageSizeEstimate()), FileSize)); + return TmpFile; +} + +TEST_F(OnDiskCASTest, OnDiskGraphDBFaultInLargeFile) { + auto runCommonTests = + [](function_ref(char)> createFileFn) { + unittest::TempDir TempUpstream("ondiskcas-upstream", /*Unique=*/true); + std::unique_ptr UpstreamDB; + ASSERT_THAT_ERROR( + OnDiskGraphDB::open(TempUpstream.path(), "blake3", sizeof(HashType)) + .moveInto(UpstreamDB), + Succeeded()); + + auto TmpFile = createFileFn('a'); + auto Path = TmpFile->path(); + HashType FileDigest = digestFile(Path); + std::optional UpstrID; + ASSERT_THAT_ERROR( + UpstreamDB->getReference(FileDigest).moveInto(UpstrID), + Succeeded()); + ASSERT_THAT_ERROR(UpstreamDB->storeFile(*UpstrID, Path), Succeeded()); + + unittest::TempDir Temp("ondiskcas", /*Unique=*/true); + std::unique_ptr DB; + ASSERT_THAT_ERROR( + OnDiskGraphDB::open(Temp.path(), "blake3", sizeof(HashType), + UpstreamDB.get(), /*Logger=*/nullptr, + OnDiskGraphDB::FaultInPolicy::SingleNode) + .moveInto(DB), + Succeeded()); + + std::optional ID1; + ASSERT_THAT_ERROR(DB->getReference(FileDigest).moveInto(ID1), + Succeeded()); + std::optional Obj; + ASSERT_THAT_ERROR(DB->load(*ID1).moveInto(Obj), Succeeded()); + ASSERT_TRUE(Obj.has_value()); + + std::optional ID2; + ASSERT_THAT_ERROR( + store(*DB, toStringRef(DB->getObjectData(*Obj)), {}).moveInto(ID2), + Succeeded()); + ASSERT_TRUE(ID2.has_value()); + EXPECT_EQ(*ID1, *ID2); + }; + + runCommonTests(createLargeFile); + runCommonTests(createLargePageAlignedFile); +} + +TEST_F(OnDiskCASTest, OnDiskGraphDBFileAPIs) { + unittest::TempDir Temp("ondiskcas", /*Unique=*/true); + std::unique_ptr DB; + ASSERT_THAT_ERROR( + OnDiskGraphDB::open(Temp.path(), "blake3", sizeof(HashType)).moveInto(DB), + Succeeded()); + + SmallVector, 4> TempFiles; + + // Create a file with small size and and controlling the initial byte so + // caller can create different contents. + auto createSmallFile = [&TempFiles](char initChar) -> StringRef { + TempFiles.push_back(std::make_unique( + "smallfile.o", /*Suffix=*/"", /*Contents=*/"", + /*Unique=*/true)); + StringRef Path = TempFiles.back()->path(); + std::error_code EC; + raw_fd_stream Out(Path, EC); + EXPECT_FALSE(EC); + SmallString<200> Data; + Data += initChar; + for (unsigned i = 1; i != 200; ++i) { + Data += i; + } + Out.write(Data.data(), Data.size()); + return Path; + }; + + auto createLargeFile = [&TempFiles](char initChar) -> StringRef { + TempFiles.push_back(::createLargeFile(initChar)); + return TempFiles.back()->path(); + }; + + auto createLargePageAlignedFile = [&TempFiles](char initChar) -> StringRef { + TempFiles.push_back(::createLargePageAlignedFile(initChar)); + return TempFiles.back()->path(); + }; + + auto runCommonTests = + [&DB](function_ref createFileFn, + function_ref + additionalChecks) { + { + auto FilePath = createFileFn('a'); + ObjectID ID1 = digestFile(*DB, FilePath); + ASSERT_THAT_ERROR(DB->storeFile(ID1, FilePath), Succeeded()); + EXPECT_TRUE(sys::fs::exists(FilePath)); + + std::optional Obj; + ASSERT_THAT_ERROR(DB->load(ID1).moveInto(Obj), Succeeded()); + EXPECT_TRUE(DB->getObjectRefs(*Obj).empty()); + ArrayRef Contents = DB->getObjectData(*Obj); + EXPECT_EQ(Contents.data()[Contents.size()], '\0'); + ObjectID ID2 = digest(*DB, toStringRef(Contents), {}); + EXPECT_EQ(ID1, ID2); + + auto FBD = DB->getInternalFileBackedObjectData(*Obj); + EXPECT_EQ(FBD.Data, Contents); + additionalChecks(FBD); + } + }; + + auto checkSmallFile = [](const OnDiskGraphDB::FileBackedData &FBD) { + EXPECT_FALSE(FBD.FileInfo.has_value()); + }; + + auto checkLargeFile = [](const OnDiskGraphDB::FileBackedData &FBD) { + ASSERT_TRUE(FBD.FileInfo.has_value()); + EXPECT_FALSE(FBD.FileInfo->IsFileNulTerminated); + ErrorOr> MB = + MemoryBuffer::getFile(FBD.FileInfo->FilePath); + ASSERT_TRUE(!!MB); + ASSERT_NE(*MB, nullptr); + EXPECT_EQ((*MB)->getBuffer(), toStringRef(FBD.Data)); + }; + + auto checkLargePageAlignedFile = + [](const OnDiskGraphDB::FileBackedData &FBD) { + ASSERT_TRUE(FBD.FileInfo.has_value()); + EXPECT_TRUE(FBD.FileInfo->IsFileNulTerminated); + ErrorOr> MB = + MemoryBuffer::getFile(FBD.FileInfo->FilePath); + ASSERT_TRUE(!!MB); + ASSERT_NE(*MB, nullptr); + EXPECT_EQ((*MB)->getBuffer().back(), '\0'); + EXPECT_EQ((*MB)->getBuffer().drop_back(1), toStringRef(FBD.Data)); + }; + + runCommonTests(createSmallFile, checkSmallFile); + runCommonTests(createLargeFile, checkLargeFile); + runCommonTests(createLargePageAlignedFile, checkLargePageAlignedFile); + + // Check non-leaf node. + { + std::optional ID1; + ASSERT_THAT_ERROR(store(*DB, "hello", {}).moveInto(ID1), Succeeded()); + + auto Path = createLargeFile('r'); + ErrorOr> MB = MemoryBuffer::getFile(Path); + ASSERT_TRUE(!!MB); + ASSERT_NE(*MB, nullptr); + std::optional ID2; + ASSERT_THAT_ERROR(store(*DB, (*MB)->getBuffer(), *ID1).moveInto(ID2), + Succeeded()); + + std::optional Obj; + ASSERT_THAT_ERROR(DB->load(*ID2).moveInto(Obj), Succeeded()); + ArrayRef Contents = DB->getObjectData(*Obj); + auto FBD = DB->getInternalFileBackedObjectData(*Obj); + EXPECT_EQ(FBD.Data, Contents); + EXPECT_FALSE(FBD.FileInfo.has_value()); + } +} + #if defined(EXPENSIVE_CHECKS) && !defined(_WIN32) TEST_F(OnDiskCASTest, OnDiskGraphDBSpaceLimit) { setMaxOnDiskCASMappingSize(); diff --git a/llvm/unittests/IR/AttributesTest.cpp b/llvm/unittests/IR/AttributesTest.cpp index 50270024f20f0..5e795ef771713 100644 --- a/llvm/unittests/IR/AttributesTest.cpp +++ b/llvm/unittests/IR/AttributesTest.cpp @@ -344,6 +344,36 @@ TEST(Attributes, ConstantRangeAttributeCAPI) { } } +TEST(Attributes, DenormalFPEnvAttributeCAPI) { + LLVMContext C; + LLVMContextRef CtxC = wrap(&C); + { + LLVMAttributeRef CAttr = LLVMCreateDenormalFPEnvAttribute( + CtxC, LLVMDenormalModeKindIEEE, LLVMDenormalModeKindIEEE, + LLVMDenormalModeKindPreserveSign, LLVMDenormalModeKindPreserveSign); + + Attribute OutAttr = unwrap(CAttr); + + EXPECT_EQ(OutAttr.getDenormalFPEnv(), + DenormalFPEnv(DenormalMode::getIEEE(), + DenormalMode::getPreserveSign())); + } + + { + LLVMAttributeRef CAttr = LLVMCreateDenormalFPEnvAttribute( + CtxC, LLVMDenormalModeKindDynamic, LLVMDenormalModeKindPositiveZero, + LLVMDenormalModeKindPreserveSign, LLVMDenormalModeKindIEEE); + + Attribute OutAttr = unwrap(CAttr); + + EXPECT_EQ( + OutAttr.getDenormalFPEnv(), + DenormalFPEnv( + DenormalMode(DenormalMode::Dynamic, DenormalMode::PositiveZero), + DenormalMode(DenormalMode::PreserveSign, DenormalMode::IEEE))); + } +} + TEST(Attributes, CalleeAttributes) { const char *IRString = R"IR( declare void @f1(i32 %i) diff --git a/llvm/unittests/Object/OffloadingTest.cpp b/llvm/unittests/Object/OffloadingTest.cpp index 18c9efaceed06..b6ad6b69f25fc 100644 --- a/llvm/unittests/Object/OffloadingTest.cpp +++ b/llvm/unittests/Object/OffloadingTest.cpp @@ -50,7 +50,9 @@ TEST(OffloadingTest, checkOffloadingBinary) { FAIL(); // Make sure we get the same data out. - auto &Binary = **BinaryOrErr; + auto &Binaries = *BinaryOrErr; + ASSERT_EQ(Binaries.size(), 1u); + auto &Binary = *Binaries[0]; ASSERT_EQ(Data.TheImageKind, Binary.getImageKind()); ASSERT_EQ(Data.TheOffloadKind, Binary.getOffloadKind()); ASSERT_EQ(Data.Flags, Binary.getFlags()); @@ -65,3 +67,209 @@ TEST(OffloadingTest, checkOffloadingBinary) { EXPECT_TRUE(Binary.getSize() % OffloadBinary::getAlignment() == 0); EXPECT_TRUE(Binary.getSize() == BinaryBuffer->getBuffer().size()); } + +static std::unique_ptr +createMultiEntryBinary(size_t NumEntries, + SmallVectorImpl &StringStorage) { + // Reserve space to prevent reallocation which would invalidate StringRefs. + // Each entry needs: "id", id_value, "arch", arch_value, image_content = 5 + // strings. + StringStorage.reserve(NumEntries * 5); + + SmallVector Images; + + for (size_t i = 0; i < NumEntries; ++i) { + OffloadBinary::OffloadingImage Data; + Data.TheImageKind = static_cast(i % IMG_LAST); + Data.TheOffloadKind = static_cast(i % OFK_LAST); + + MapVector StringData; + + StringStorage.push_back("id"); + StringStorage.push_back(std::to_string(i)); + StringData[StringStorage[StringStorage.size() - 2]] = + StringStorage[StringStorage.size() - 1]; + + StringStorage.push_back("arch"); + StringStorage.push_back("gpu" + std::to_string(i)); + StringData[StringStorage[StringStorage.size() - 2]] = + StringStorage[StringStorage.size() - 1]; + + Data.StringData = StringData; + + // Make the last entry metadata-only (no image) + if (i == NumEntries - 1) { + Data.Flags = OIF_Metadata; + Data.Image = MemoryBuffer::getMemBuffer("", "", false); + } else { + Data.Flags = i * 100; + StringStorage.push_back("ImageData" + std::to_string(i)); + Data.Image = MemoryBuffer::getMemBuffer(StringStorage.back(), "", false); + } + + Images.push_back(std::move(Data)); + } + + return MemoryBuffer::getMemBufferCopy(OffloadBinary::write(Images)); +} + +// Test multi-entry binaries and extraction without index (get all entries). +TEST(OffloadingTest, checkMultiEntryBinaryExtraction) { + const size_t NumEntries = 5; + SmallVector StringStorage; + auto BinaryBuffer = createMultiEntryBinary(NumEntries, StringStorage); + + // Test extracting all entries (no index). + auto BinariesOrErr = OffloadBinary::create(*BinaryBuffer); + ASSERT_THAT_EXPECTED(BinariesOrErr, Succeeded()); + + auto &Binaries = *BinariesOrErr; + ASSERT_EQ(Binaries.size(), NumEntries) + << "Expected all entries when no index provided"; + + // Verify each entry. + for (size_t i = 0; i < NumEntries; ++i) { + auto &Binary = *Binaries[i]; + EXPECT_EQ(Binary.getImageKind(), static_cast(i % IMG_LAST)); + EXPECT_EQ(Binary.getOffloadKind(), static_cast(i % OFK_LAST)); + EXPECT_EQ(Binary.getIndex(), i); + + std::string ExpectedId = std::to_string(i); + std::string ExpectedArch = "gpu" + std::to_string(i); + EXPECT_EQ(Binary.getString("id"), ExpectedId); + EXPECT_EQ(Binary.getString("arch"), ExpectedArch); + + // Last entry is metadata-only. + if (i == NumEntries - 1) { + EXPECT_EQ(Binary.getFlags(), OIF_Metadata); + EXPECT_TRUE(Binary.getImage().empty()); + } else { + EXPECT_EQ(Binary.getFlags(), i * 100); + std::string ExpectedImage = "ImageData" + std::to_string(i); + EXPECT_EQ(Binary.getImage(), ExpectedImage); + } + } + + // Ensure the size and alignment of the data is correct. + EXPECT_TRUE(Binaries[0]->getSize() % OffloadBinary::getAlignment() == 0); + EXPECT_TRUE(Binaries[0]->getSize() == BinaryBuffer->getBuffer().size()); +} + +// Test index-based extraction from multi-entry binary. +TEST(OffloadingTest, checkIndexBasedExtraction) { + const size_t NumEntries = 5; + SmallVector StringStorage; + auto BinaryBuffer = createMultiEntryBinary(NumEntries, StringStorage); + + // Test extracting specific indices. + for (uint64_t i = 0; i < NumEntries; ++i) { + auto BinariesOrErr = OffloadBinary::create(*BinaryBuffer, i); + ASSERT_THAT_EXPECTED(BinariesOrErr, Succeeded()); + + auto &Binaries = *BinariesOrErr; + ASSERT_EQ(Binaries.size(), 1u) << "Expected single entry when using index"; + + auto &Binary = *Binaries[0]; + EXPECT_EQ(Binary.getImageKind(), static_cast(i % IMG_LAST)); + EXPECT_EQ(Binary.getOffloadKind(), static_cast(i % OFK_LAST)); + EXPECT_EQ(Binary.getIndex(), i); + + std::string ExpectedId = std::to_string(i); + std::string ExpectedArch = "gpu" + std::to_string(i); + EXPECT_EQ(Binary.getString("id"), ExpectedId); + EXPECT_EQ(Binary.getString("arch"), ExpectedArch); + + // Last entry is metadata-only. + if (i == NumEntries - 1) { + EXPECT_EQ(Binary.getFlags(), OIF_Metadata); + EXPECT_TRUE(Binary.getImage().empty()); + } else { + EXPECT_EQ(Binary.getFlags(), i * 100); + std::string ExpectedImage = "ImageData" + std::to_string(i); + EXPECT_EQ(Binary.getImage(), ExpectedImage); + } + } + + // Test out-of-bounds index. + auto OutOfBoundsOrErr = OffloadBinary::create(*BinaryBuffer, NumEntries + 10); + EXPECT_THAT_EXPECTED(OutOfBoundsOrErr, Failed()); +} + +TEST(OffloadingTest, checkEdgeCases) { + // Test with empty string data. + { + OffloadBinary::OffloadingImage Data; + Data.TheImageKind = IMG_Object; + Data.TheOffloadKind = OFK_OpenMP; + Data.Flags = 0; + Data.StringData = MapVector(); // Empty + + std::string ImageContent = "TestImage"; + Data.Image = MemoryBuffer::getMemBuffer(ImageContent, "", false); + + auto BinaryBuffer = + MemoryBuffer::getMemBufferCopy(OffloadBinary::write(Data)); + auto BinariesOrErr = OffloadBinary::create(*BinaryBuffer); + ASSERT_THAT_EXPECTED(BinariesOrErr, Succeeded()); + + auto &Binaries = *BinariesOrErr; + ASSERT_EQ(Binaries.size(), 1u); + EXPECT_TRUE(Binaries[0]->strings().empty()); + EXPECT_EQ(Binaries[0]->getImage(), ImageContent); + } + + // Test with empty image data. + { + std::string Key = "test"; + std::string Value = "value"; + + OffloadBinary::OffloadingImage Data; + Data.TheImageKind = IMG_Object; + Data.TheOffloadKind = OFK_SYCL; + Data.Flags = 0; + + MapVector StringData; + StringData[Key] = Value; + Data.StringData = StringData; + + Data.Image = MemoryBuffer::getMemBuffer("", "", false); // Empty image + + auto BinaryBuffer = + MemoryBuffer::getMemBufferCopy(OffloadBinary::write(Data)); + auto BinariesOrErr = OffloadBinary::create(*BinaryBuffer); + ASSERT_THAT_EXPECTED(BinariesOrErr, Succeeded()); + + auto &Binaries = *BinariesOrErr; + ASSERT_EQ(Binaries.size(), 1u); + EXPECT_TRUE(Binaries[0]->getImage().empty()); + EXPECT_EQ(Binaries[0]->getString("test"), "value"); + } + + // Test with large string values. + { + std::string Key = "large_key"; + std::string LargeValue(4096, 'X'); // Large value + std::string ImageContent = "Image"; + + OffloadBinary::OffloadingImage Data; + Data.TheImageKind = IMG_Bitcode; + Data.TheOffloadKind = OFK_OpenMP; + Data.Flags = 0; + + MapVector StringData; + StringData[Key] = LargeValue; + Data.StringData = StringData; + + Data.Image = MemoryBuffer::getMemBuffer(ImageContent, "", false); + + auto BinaryBuffer = + MemoryBuffer::getMemBufferCopy(OffloadBinary::write(Data)); + auto BinariesOrErr = OffloadBinary::create(*BinaryBuffer); + ASSERT_THAT_EXPECTED(BinariesOrErr, Succeeded()); + + auto &Binaries = *BinariesOrErr; + ASSERT_EQ(Binaries.size(), 1u); + EXPECT_EQ(Binaries[0]->getString("large_key"), LargeValue); + EXPECT_EQ(Binaries[0]->getString("large_key").size(), 4096u); + } +} diff --git a/llvm/unittests/Support/MathExtrasTest.cpp b/llvm/unittests/Support/MathExtrasTest.cpp index 5cb85fc55da92..27e8b26e8801d 100644 --- a/llvm/unittests/Support/MathExtrasTest.cpp +++ b/llvm/unittests/Support/MathExtrasTest.cpp @@ -692,4 +692,19 @@ TYPED_TEST(OverflowTest, MulResultZero) { EXPECT_FALSE(MulOverflow(0, -5, Result)); EXPECT_EQ(Result, TypeParam(0)); } + +TEST(MathExtras, NumDigitsBase10) { + EXPECT_EQ(NumDigitsBase10(0), 1); + EXPECT_EQ(NumDigitsBase10(1), 1); + + uint64_t Val = 10; + for (int i = 2; i <= 20; i++) { + EXPECT_EQ(NumDigitsBase10(Val - 1), i - 1); + EXPECT_EQ(NumDigitsBase10(Val), i); + Val *= 10; + } + + EXPECT_EQ(NumDigitsBase10(std::numeric_limits::max()), 20); +} + } // namespace diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index c07551e6cff00..fa09135136889 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1397,6 +1397,7 @@ Experimental extensions zibi 0.1 zicfilp 1.0 This is a long dummy description zicfiss 1.0 + zvabd 0.7 zvbc32e 0.7 zvfbfa 0.1 zvfofp8min 0.2 diff --git a/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp index f778568dd373a..5778c67ab5bf9 100644 --- a/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp +++ b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp @@ -7,6 +7,8 @@ //===----------------------------------------------------------------------===// #include "llvm/TargetParser/RISCVTargetParser.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" #include "gtest/gtest.h" using namespace llvm; @@ -36,4 +38,133 @@ TEST(RISCVVType, CheckSameRatioLMUL) { RISCVVType::getSameRatioLMUL( RISCVVType::getSEWLMULRatio(8, RISCVVType::LMUL_F4), 16)); } + +TEST(RISCVTuneFeature, AllTuneFeatures) { + SmallVector AllTuneFeatures; + RISCV::getAllTuneFeatures(AllTuneFeatures); + // Only allowed subtarget features that are explicitly marked by + // special TableGen class. + EXPECT_EQ(AllTuneFeatures.size(), 19U); + for (auto F : + {"conditional-cmv-fusion", "disable-latency-sched-heuristic", + "disable-misched-load-clustering", "disable-misched-store-clustering", + "disable-postmisched-load-clustering", + "disable-postmisched-store-clustering", "single-element-vec-fp64", + "no-default-unroll", "no-sink-splat-operands", "use-postra-scheduler", + "predictable-select-expensive", "prefer-vsetvli-over-read-vlenb", + "prefer-w-inst", "short-forward-branch-ialu", + "short-forward-branch-iminmax", "short-forward-branch-imul", + "short-forward-branch-iload", "vl-dependent-latency", + "vxrm-pipeline-flush"}) + EXPECT_TRUE(is_contained(AllTuneFeatures, F)); +} + +TEST(RISCVTuneFeature, LegalTuneFeatureStrings) { + SmallVector Result; + EXPECT_FALSE(errorToBool(RISCV::parseTuneFeatureString( + /*ProcName=*/"", + "prefer-w-inst,no-short-forward-branch-ialu,vl-dependent-latency", + Result))); + EXPECT_TRUE(is_contained(Result, "+prefer-w-inst")); + EXPECT_TRUE(is_contained(Result, "+vl-dependent-latency")); + EXPECT_TRUE(is_contained(Result, "-short-forward-branch-ialu")); + EXPECT_TRUE(is_contained(Result, "-short-forward-branch-iminmax")); + EXPECT_TRUE(is_contained(Result, "-short-forward-branch-imul")); + EXPECT_TRUE(is_contained(Result, "-short-forward-branch-iload")); + + Result.clear(); + // Test inverse implied features. + EXPECT_FALSE(errorToBool(RISCV::parseTuneFeatureString( + /*ProcName=*/"", + "no-short-forward-branch-imul,short-forward-branch-iminmax", Result))); + EXPECT_TRUE(is_contained(Result, "+short-forward-branch-iminmax")); + EXPECT_TRUE(is_contained(Result, "+short-forward-branch-ialu")); + EXPECT_TRUE(is_contained(Result, "-short-forward-branch-imul")); + + Result.clear(); + // Test custom directive names. + EXPECT_FALSE(errorToBool( + RISCV::parseTuneFeatureString(/*ProcName=*/"", + "enable-default-unroll,no-sink-splat-" + "operands,enable-latency-sched-heuristic", + Result))); + EXPECT_TRUE(is_contained(Result, "+no-sink-splat-operands")); + EXPECT_TRUE(is_contained(Result, "-no-default-unroll")); + EXPECT_TRUE(is_contained(Result, "-disable-latency-sched-heuristic")); +} + +TEST(RISCVTuneFeature, IgnoreUnrecognizedTuneFeature) { + SmallVector Result; + auto Err = RISCV::parseTuneFeatureString(/*ProcName=*/"", + "32bit,prefer-w-inst", Result); + // This should be an warning. + EXPECT_TRUE(Err.isA()); + EXPECT_EQ(toString(std::move(Err)), + "unrecognized tune feature directive '32bit'"); + EXPECT_TRUE(is_contained(Result, "+prefer-w-inst")); +} + +TEST(RISCVTuneFeature, DuplicatedFeatures) { + SmallVector Result; + EXPECT_EQ(toString(RISCV::parseTuneFeatureString( + /*ProcName=*/"", "prefer-w-inst,prefer-w-inst", Result)), + "cannot specify more than one instance of 'prefer-w-inst'"); + + EXPECT_EQ(toString(RISCV::parseTuneFeatureString( + /*ProcName=*/"", + "prefer-w-inst,no-prefer-w-inst,short-forward-branch-imul,no-" + "short-forward-branch-imul", + Result)), + "Feature(s) 'prefer-w-inst', 'short-forward-branch-imul' cannot " + "appear in both positive and negative directives"); + + // The error message should show the feature name for those using custom + // directives. + EXPECT_EQ( + toString(RISCV::parseTuneFeatureString( + /*ProcName=*/"", + "disable-latency-sched-heuristic,enable-latency-sched-heuristic", + Result)), + "Feature(s) 'disable-latency-sched-heuristic' cannot appear in both " + "positive and negative directives"); + + EXPECT_EQ( + toString(RISCV::parseTuneFeatureString( + /*ProcName=*/"", + "short-forward-branch-imul,no-short-forward-branch-ialu", Result)), + "Feature(s) 'short-forward-branch-imul', 'short-forward-branch-ialu' " + "were implied by both positive and negative directives"); +} + +TEST(RISCVTuneFeature, ProcConfigurableFeatures) { + SmallVector Result; + EXPECT_FALSE(errorToBool(RISCV::parseTuneFeatureString( + "sifive-x280", "single-element-vec-fp64", Result))); + EXPECT_TRUE(is_contained(Result, "+single-element-vec-fp64")); + + Result.clear(); + EXPECT_EQ( + toString(RISCV::parseTuneFeatureString( + "sifive-x280", "single-element-vec-fp64,prefer-w-inst", Result)), + "Directive 'prefer-w-inst' is not allowed to be used with processor " + "'sifive-x280'"); +} + +TEST(RISCVTuneFeature, AllProcConfigurableFeatures) { + SmallVector Result; + RISCV::getCPUConfigurableTuneFeatures("sifive-x280", Result); + EXPECT_TRUE(is_contained(Result, "single-element-vec-fp64")); + EXPECT_TRUE(is_contained(Result, "full-vec-fp64")); + EXPECT_EQ(Result.size(), 2U); + + Result.clear(); + RISCV::getCPUConfigurableTuneFeatures("sifive-x390", Result); + EXPECT_TRUE(is_contained(Result, "single-element-vec-fp64")); + EXPECT_TRUE(is_contained(Result, "full-vec-fp64")); + EXPECT_EQ(Result.size(), 2U); + + Result.clear(); + RISCV::getCPUConfigurableTuneFeatures("rocket", Result); + EXPECT_TRUE(Result.empty()); +} } // namespace diff --git a/llvm/unittests/TargetParser/TripleTest.cpp b/llvm/unittests/TargetParser/TripleTest.cpp index 762b464cfec5b..7070193c0a129 100644 --- a/llvm/unittests/TargetParser/TripleTest.cpp +++ b/llvm/unittests/TargetParser/TripleTest.cpp @@ -1748,6 +1748,26 @@ TEST(TripleTest, Normalization) { Triple::normalize("wasm32-wasi")); // wasm32-unknown-wasi EXPECT_EQ("wasm64-unknown-wasi", Triple::normalize("wasm64-wasi")); // wasm64-unknown-wasi + + // Firmware should only be allowed for the Apple vendor + EXPECT_DEATH(Triple::normalize("arm-none-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-unknown-firmware"), ""); + EXPECT_EQ("arm-apple-firmware", Triple::normalize("arm-apple-firmware")); + EXPECT_DEATH(Triple::normalize("arm-pc-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-scei-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-sie-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-fsl-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-ibm-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-img-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-mti-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-nvidia-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-csr-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-amd-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-mesa-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-suse-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-oe-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-intel-firmware"), ""); + EXPECT_DEATH(Triple::normalize("arm-meta-firmware"), ""); } TEST(TripleTest, MutateName) { diff --git a/llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp b/llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp index 00d9e9ff81e05..0856ac698e5a0 100644 --- a/llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp +++ b/llvm/unittests/Transforms/Utils/BasicBlockUtilsTest.cpp @@ -354,6 +354,37 @@ define void @foo() { } #endif +TEST(BasicBlockUtils, splitBlockBefore2) { + LLVMContext C; + std::unique_ptr M = parseIR(C, R"IR( +define void @split-block-before-test(i1 %flag) { +entry: + br label %loop + +loop: + br i1 %flag, label %loop, label %exit + +exit: + ret void +} +)IR"); + Function *F = M->getFunction("split-block-before-test"); + DominatorTree DT(*F); + LoopInfo LI(DT); + + EXPECT_TRUE(DT.verify()); + LI.verify(DT); + auto *LoopBB = getBasicBlockByName(*F, "loop"); + DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Eager); + auto *New = splitBlockBefore(LoopBB, LoopBB->getFirstInsertionPt(), &DTU, &LI, + /* MemorySSAUpdater */ nullptr, + LoopBB->getName() + ".split"); + + EXPECT_TRUE(DT.verify()); + LI.verify(DT); + EXPECT_EQ(LI.getLoopFor(New)->getHeader(), New); +} + TEST(BasicBlockUtils, NoUnreachableBlocksToEliminate) { LLVMContext C; std::unique_ptr M = parseIR(C, R"IR( @@ -378,6 +409,31 @@ define i32 @no_unreachable(i1 %cond) { EXPECT_TRUE(DT.verify()); } +TEST(BasicBlockUtils, splitBlockBefore) { + LLVMContext C; + std::unique_ptr M = parseIR(C, R"IR( +define i32 @basic_func(i1 %cond) { +entry: + br i1 %cond, label %bb0, label %bb1 +bb0: + br label %bb1 +bb1: + %phi = phi i32 [ 0, %entry ], [ 1, %bb0 ] + ret i32 %phi +} +)IR"); + Function *F = M->getFunction("basic_func"); + DominatorTree DT(*F); + DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Eager); + BasicBlock *EntryBB = &F->getEntryBlock(); + Instruction *TI = EntryBB->getTerminator(); + + // Make sure the dominator tree is properly updated if calling this on the + // entry block. + splitBlockBefore(EntryBB, TI, &DTU, nullptr, nullptr); + EXPECT_TRUE(DTU.getDomTree().verify()); +} + TEST(BasicBlockUtils, SplitBlockPredecessors) { LLVMContext C; std::unique_ptr M = parseIR(C, R"IR( diff --git a/llvm/unittests/Transforms/Utils/CloningTest.cpp b/llvm/unittests/Transforms/Utils/CloningTest.cpp index 545ca7c16af71..8c138be840ed7 100644 --- a/llvm/unittests/Transforms/Utils/CloningTest.cpp +++ b/llvm/unittests/Transforms/Utils/CloningTest.cpp @@ -808,6 +808,145 @@ TEST(CloneFunction, CloneFunctionWithSubprograms) { EXPECT_FALSE(verifyModule(*ImplModule, &errs())); } +TEST(CloneFunction, CloneFunctionWithRetainedNodes) { + StringRef ImplAssembly = R"( + declare void @llvm.dbg.declare(metadata, metadata, metadata) + + define void @test() !dbg !3 { + call void @llvm.dbg.declare(metadata ptr poison, metadata !5, metadata !DIExpression()), !dbg !7 + call void @llvm.dbg.declare(metadata ptr poison, metadata !25, metadata !DIExpression()), !dbg !7 + call void @llvm.dbg.declare(metadata ptr poison, metadata !28, metadata !DIExpression()), !dbg !8 + call void @llvm.dbg.declare(metadata ptr poison, metadata !30, metadata !DIExpression()), !dbg !8 + ret void + } + + declare void @cloned() + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!2} + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, enums: !{!14}) + !1 = !DIFile(filename: "test.cpp", directory: "") + !2 = !{i32 1, !"Debug Info Version", i32 3} + !3 = distinct !DISubprogram(name: "test", scope: !1, unit: !0, retainedNodes: !9) + !4 = distinct !DISubprogram(name: "inlined", scope: !1, unit: !0, retainedNodes: !{!5}) + !5 = !DILocalVariable(name: "awaitables", scope: !4, type: !23) + !6 = distinct !DILexicalBlock(scope: !4, file: !1, line: 1) + !7 = !DILocation(line: 1, scope: !6, inlinedAt: !8) + !8 = !DILocation(line: 10, scope: !3) + !9 = !{!15, !17, !18, !23, !26, !28, !30} + !14 = distinct !DICompositeType(tag: DW_TAG_enumeration_type, scope: !0, file: !1, line: 13, size: 200, elements: !{}) + !15 = !DILocalVariable(name: "a", scope: !3) + !16 = distinct !DICompositeType(tag: DW_TAG_enumeration_type, scope: !3, file: !1, line: 13, size: 208, elements: !{}) + !17 = !DIImportedEntity(tag: DW_TAG_imported_declaration, name: "imported_l", file: !1, line: 14, scope: !3, entity: !16) + !18 = !DILabel(scope: !3, name: "l", file: !1, line: 22) + !22 = !DIBasicType(name: "real", size: 32, align: 32, encoding: DW_ATE_float) + !23 = !DIDerivedType(name: "local_float", tag: DW_TAG_const_type, baseType: !22, scope: !3) + !float_type = !{!23} + !25 = !DILocalVariable(name: "inlined2", scope: !4, type: !23) + !inlined2 = !{!25} + !26 = distinct !DICompositeType(tag: DW_TAG_enumeration_type, name: "mystruct", scope: !3, file: !1, line: 13, size: 208, elements: !{}) + !27 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !26, size: 64) + !28 = !DILocalVariable(name: "ptr", scope: !3, type: !27) + !29 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !27) + !30 = !DILocalVariable(name: "const_ptr", scope: !3, type: !29) + )"; + + LLVMContext Context; + SMDiagnostic Error; + + auto ImplModule = parseAssemblyString(ImplAssembly, Error, Context); + EXPECT_TRUE(ImplModule != nullptr); + auto *Func = ImplModule->getFunction("test"); + EXPECT_TRUE(Func != nullptr); + auto *ClonedFunc = ImplModule->getFunction("cloned"); + EXPECT_TRUE(ClonedFunc != nullptr); + + EXPECT_FALSE(verifyModule(*ImplModule, &errs())); + + ValueToValueMapTy VMap; + SmallVector Returns; + ClonedCodeInfo CCI; + CloneFunctionInto(ClonedFunc, Func, VMap, + CloneFunctionChangeType::GlobalChanges, Returns, "", &CCI); + + EXPECT_FALSE(verifyModule(*ImplModule, &errs())); + + // Check that retained and local types are copied. + DISubprogram *FuncSP = Func->getSubprogram(); + DISubprogram *ClonedSP = ClonedFunc->getSubprogram(); + EXPECT_NE(FuncSP, nullptr); + EXPECT_NE(ClonedSP, nullptr); + EXPECT_EQ(FuncSP->getRetainedNodes().size(), 7u); + EXPECT_EQ(FuncSP->getRetainedNodes().size(), + ClonedSP->getRetainedNodes().size()); + + // Ensure that Orig node is a clone of Copy by checking that they are + // different objects with the same name. + auto CheckNodeIsCloned = [](auto *Orig, auto *Copy) { + EXPECT_FALSE(Orig->getName().empty()); + EXPECT_EQ(Orig->getName(), Copy->getName()); + + // Check that node was copied. + EXPECT_NE(Orig, Copy); + }; + + // Check that retained nodes are cloned. + unsigned I = 0; + auto CheckRetainedNode = [&](auto *Node) { + // The order of retained nodes should be preserved. + auto *Copy = + cast>(ClonedSP->getRetainedNodes()[I]); + + CheckNodeIsCloned(Node, Copy); + + ++I; + }; + FuncSP->forEachRetainedNode(CheckRetainedNode, CheckRetainedNode, + CheckRetainedNode, CheckRetainedNode); + + auto ToDerived = [](const DIType *Ty) { return cast(Ty); }; + + // Check that derived type (pointer type) referencing local type is remapped + // in the cloned function even though it doesn't have an explicit scope. + auto CheckPointerTypeIsCloned = [&](const DIType *PtrTy, + const DIType *PtrTyCopy) { + auto *PointerType = ToDerived(PtrTy); + auto *PointerTypeCopy = ToDerived(PtrTyCopy); + ASSERT_EQ(PointerType->getBaseType()->getName(), "mystruct"); + ASSERT_EQ(PointerType->getScope(), nullptr); + CheckNodeIsCloned(PointerType->getBaseType(), + PointerTypeCopy->getBaseType()); + }; + auto *PointerOrig = cast(FuncSP->getRetainedNodes()[5]); + auto *PointerCopy = cast(ClonedSP->getRetainedNodes()[5]); + ASSERT_EQ(PointerOrig->getName(), "ptr"); + CheckPointerTypeIsCloned(PointerOrig->getType(), PointerCopy->getType()); + + // Check that scopeless derived type (const type) referencing scopeless + // derived type (pointer type) referencing local type gets cloned. + auto *ConstPointerOrig = cast(FuncSP->getRetainedNodes()[6]); + auto *ConstPointerCopy = + cast(ClonedSP->getRetainedNodes()[6]); + ASSERT_EQ(ConstPointerOrig->getName(), "const_ptr"); + auto *ConstPointerTypeOrig = ToDerived(ConstPointerOrig->getType()); + auto *ConstPointerTypeCopy = ToDerived(ConstPointerCopy->getType()); + ASSERT_NE(ConstPointerOrig, ConstPointerCopy); + CheckPointerTypeIsCloned(ToDerived(ConstPointerTypeOrig)->getBaseType(), + ToDerived(ConstPointerTypeCopy)->getBaseType()); + + auto *FloatType = dyn_cast( + ImplModule->getNamedMetadata("float_type")->getOperand(0)); + EXPECT_EQ(FloatType->getName(), "local_float"); + EXPECT_TRUE(VMap.MD().contains(FloatType)); + EXPECT_NE(FloatType, VMap.MD()[FloatType]); + + auto *Inlined2 = dyn_cast( + ImplModule->getNamedMetadata("inlined2")->getOperand(0)); + EXPECT_EQ(Inlined2->getName(), "inlined2"); + EXPECT_TRUE(VMap.MD().contains(Inlined2)); + EXPECT_EQ(Inlined2, VMap.MD()[Inlined2]); +} + TEST(CloneFunction, CloneFunctionWithInlinedSubprograms) { StringRef ImplAssembly = R"( declare void @llvm.dbg.declare(metadata, metadata, metadata) diff --git a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp index 9b1e7c0af7c8c..5f33f0593e05f 100644 --- a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp @@ -136,7 +136,9 @@ TEST_F(VPInstructionTest, setOperand) { IntegerType *Int32 = IntegerType::get(C, 32); VPValue *VPV1 = getPlan().getOrAddLiveIn(ConstantInt::get(Int32, 1)); VPValue *VPV2 = getPlan().getOrAddLiveIn(ConstantInt::get(Int32, 2)); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {VPV1, VPV2}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {VPV1, VPV2}, + VPIRFlags::getDefaultFlags(Instruction::Add)); EXPECT_EQ(1u, VPV1->getNumUsers()); EXPECT_EQ(I1, *VPV1->user_begin()); EXPECT_EQ(1u, VPV2->getNumUsers()); @@ -179,7 +181,9 @@ TEST_F(VPInstructionTest, replaceAllUsesWith) { IntegerType *Int32 = IntegerType::get(C, 32); VPValue *VPV1 = getPlan().getOrAddLiveIn(ConstantInt::get(Int32, 1)); VPValue *VPV2 = getPlan().getOrAddLiveIn(ConstantInt::get(Int32, 2)); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {VPV1, VPV2}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {VPV1, VPV2}, + VPIRFlags::getDefaultFlags(Instruction::Add)); // Replace all uses of VPV1 with VPV3. VPValue *VPV3 = getPlan().getOrAddLiveIn(ConstantInt::get(Int32, 3)); @@ -210,7 +214,9 @@ TEST_F(VPInstructionTest, replaceAllUsesWith) { EXPECT_EQ(0u, VPV2->getNumUsers()); EXPECT_EQ(0u, VPV3->getNumUsers()); - VPInstruction *I2 = new VPInstruction(Instruction::Add, {VPV1, VPV2}); + VPInstruction *I2 = + new VPInstruction(Instruction::Add, {VPV1, VPV2}, + VPIRFlags::getDefaultFlags(Instruction::Add)); EXPECT_EQ(3u, VPV1->getNumUsers()); VPV1->replaceAllUsesWith(VPV3); EXPECT_EQ(3u, VPV3->getNumUsers()); @@ -223,7 +229,9 @@ TEST_F(VPInstructionTest, releaseOperandsAtDeletion) { IntegerType *Int32 = IntegerType::get(C, 32); VPValue *VPV1 = getPlan().getOrAddLiveIn(ConstantInt::get(Int32, 1)); VPValue *VPV2 = getPlan().getOrAddLiveIn(ConstantInt::get(Int32, 1)); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {VPV1, VPV2}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {VPV1, VPV2}, + VPIRFlags::getDefaultFlags(Instruction::Add)); EXPECT_EQ(1u, VPV1->getNumUsers()); EXPECT_EQ(I1, *VPV1->user_begin()); @@ -388,11 +396,27 @@ TEST_F(VPBasicBlockTest, TraversingIteratorTest) { // Successors of R1. SmallVector FromIterator( - VPAllSuccessorsIterator(R1), - VPAllSuccessorsIterator::end(R1)); + VPHierarchicalChildrenIterator(R1), + VPHierarchicalChildrenIterator::end(R1)); EXPECT_EQ(1u, FromIterator.size()); EXPECT_EQ(R1BB1, FromIterator[0]); + // Predecessors of R1. + FromIterator.clear(); + copy(VPHierarchicalChildrenIterator(R1), + VPHierarchicalChildrenIterator::end(R1), + std::back_inserter(FromIterator)); + EXPECT_EQ(1u, FromIterator.size()); + EXPECT_EQ(R1BB4, FromIterator[0]); + + // Predecessors of R1BB1. + FromIterator.clear(); + copy(VPHierarchicalChildrenIterator(R1BB1), + VPHierarchicalChildrenIterator::end(R1BB1), + std::back_inserter(FromIterator)); + EXPECT_EQ(1u, FromIterator.size()); + EXPECT_EQ(VPBB0, FromIterator[0]); + // Depth-first. VPBlockDeepTraversalWrapper Start(R1); FromIterator.clear(); @@ -407,6 +431,21 @@ TEST_F(VPBasicBlockTest, TraversingIteratorTest) { EXPECT_EQ(R2BB2, FromIterator[6]); EXPECT_EQ(R1BB3, FromIterator[7]); + // Depth-first on the inverse graph (traverse predecessors). + FromIterator.clear(); + copy(depth_first>(R2), + std::back_inserter(FromIterator)); + EXPECT_EQ(9u, FromIterator.size()); + EXPECT_EQ(R2, FromIterator[0]); + EXPECT_EQ(R2BB2, FromIterator[1]); + EXPECT_EQ(R2BB1, FromIterator[2]); + EXPECT_EQ(R1, FromIterator[3]); + EXPECT_EQ(R1BB4, FromIterator[4]); + EXPECT_EQ(R1BB2, FromIterator[5]); + EXPECT_EQ(R1BB1, FromIterator[6]); + EXPECT_EQ(VPBB0, FromIterator[7]); + EXPECT_EQ(R1BB3, FromIterator[8]); + // const VPBasicBlocks only. FromIterator.clear(); copy(VPBlockUtils::blocksOnly(depth_first(Start)), @@ -725,8 +764,12 @@ TEST_F(VPBasicBlockTest, print) { VPValue *Val = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 1)); VPBasicBlock *VPBB0 = Plan.getEntry(); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {Val, Val}); - VPInstruction *I2 = new VPInstruction(Instruction::Sub, {I1, Val}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {Val, Val}, + VPIRFlags::getDefaultFlags(Instruction::Add)); + VPInstruction *I2 = + new VPInstruction(Instruction::Sub, {I1, Val}, + VPIRFlags::getDefaultFlags(Instruction::Sub)); VPInstruction *I3 = new VPInstruction(Instruction::Store, {I1, I2}); VPBasicBlock *VPBB1 = Plan.createVPBasicBlock(""); @@ -735,7 +778,8 @@ TEST_F(VPBasicBlockTest, print) { VPBB1->appendRecipe(I3); VPBB1->setName("bb1"); - VPInstruction *I4 = new VPInstruction(Instruction::Mul, {I2, I1}); + VPInstruction *I4 = new VPInstruction( + Instruction::Mul, {I2, I1}, VPIRFlags::getDefaultFlags(Instruction::Mul)); VPInstruction *I5 = new VPInstruction(Instruction::Freeze, {I4}); VPBasicBlock *VPBB2 = Plan.createVPBasicBlock(""); VPBB2->appendRecipe(I4); @@ -836,7 +880,9 @@ TEST_F(VPBasicBlockTest, printPlanWithVFsAndUFs) { VPValue *Val = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 1)); VPBasicBlock *VPBB0 = Plan.getEntry(); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {Val, Val}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {Val, Val}, + VPIRFlags::getDefaultFlags(Instruction::Add)); VPBasicBlock *VPBB1 = Plan.createVPBasicBlock(""); VPBB1->appendRecipe(I1); VPBB1->setName("bb1"); @@ -922,8 +968,12 @@ TEST_F(VPBasicBlockTest, cloneAndPrint) { IntegerType *Int32 = IntegerType::get(C, 32); VPValue *Val = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 1)); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {Val, Val}); - VPInstruction *I2 = new VPInstruction(Instruction::Sub, {I1, Val}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {Val, Val}, + VPIRFlags::getDefaultFlags(Instruction::Add)); + VPInstruction *I2 = + new VPInstruction(Instruction::Sub, {I1, Val}, + VPIRFlags::getDefaultFlags(Instruction::Sub)); VPInstruction *I3 = new VPInstruction(Instruction::Store, {I1, I2}); VPBasicBlock *VPBB1 = Plan.createVPBasicBlock(""); @@ -994,7 +1044,8 @@ TEST_F(VPRecipeTest, CastVPInstructionToVPUser) { VPlan &Plan = getPlan(); VPValue *Op1 = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 1)); VPValue *Op2 = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 2)); - VPInstruction Recipe(Instruction::Add, {Op1, Op2}); + VPInstruction Recipe(Instruction::Add, {Op1, Op2}, + VPIRFlags::getDefaultFlags(Instruction::Add)); checkVPRecipeCastImpl(&Recipe); } @@ -1067,7 +1118,8 @@ TEST_F(VPRecipeTest, CastVPWidenCastRecipeToVPUser) { IntegerType *Int64 = IntegerType::get(C, 64); auto *Cast = CastInst::CreateZExtOrBitCast(PoisonValue::get(Int32), Int64); VPValue *Op1 = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 1)); - VPWidenCastRecipe Recipe(Instruction::ZExt, Op1, Int64, Cast); + VPWidenCastRecipe Recipe(Instruction::ZExt, Op1, Int64, Cast, + VPIRFlags::getDefaultFlags(Instruction::ZExt)); checkVPRecipeCastImpl(&Recipe); delete Cast; @@ -1095,7 +1147,7 @@ TEST_F(VPRecipeTest, CastVPBlendRecipeToVPUser) { Args.push_back(I1); Args.push_back(I2); Args.push_back(M2); - VPBlendRecipe Recipe(Phi, Args, {}); + VPBlendRecipe Recipe(Phi, Args, {}, {}); checkVPRecipeCastImpl(&Recipe); @@ -1381,7 +1433,8 @@ TEST_F(VPRecipeTest, MayHaveSideEffectsAndMayReadWriteMemory) { { VPValue *Op1 = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 1)); VPValue *Op2 = Plan.getOrAddLiveIn(ConstantInt::get(Int32, 2)); - VPInstruction VPInst(Instruction::Add, {Op1, Op2}); + VPInstruction VPInst(Instruction::Add, {Op1, Op2}, + VPIRFlags::getDefaultFlags(Instruction::Add)); VPRecipeBase &Recipe = VPInst; EXPECT_FALSE(Recipe.mayHaveSideEffects()); EXPECT_FALSE(Recipe.mayReadFromMemory()); @@ -1474,8 +1527,11 @@ TEST_F(VPRecipeTest, dumpRecipeUnnamedVPValuesInPlan) { VPValue *ExtVPV2 = Plan.getOrAddLiveIn(AI); Args.push_back(ExtVPV1); Args.push_back(ExtVPV2); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {ExtVPV1, ExtVPV2}); - VPInstruction *I2 = new VPInstruction(Instruction::Mul, {I1, I1}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {ExtVPV1, ExtVPV2}, + VPIRFlags::getDefaultFlags(Instruction::Add)); + VPInstruction *I2 = new VPInstruction( + Instruction::Mul, {I1, I1}, VPIRFlags::getDefaultFlags(Instruction::Mul)); VPBB1->appendRecipe(I1); VPBB1->appendRecipe(I2); @@ -1534,8 +1590,11 @@ TEST_F(VPRecipeTest, dumpRecipeUnnamedVPValuesNotInPlanOrBlock) { VPValue *ExtVPV1 = getPlan().getOrAddLiveIn(ConstantInt::get(Int32, 1)); VPValue *ExtVPV2 = getPlan().getOrAddLiveIn(AI); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {ExtVPV1, ExtVPV2}); - VPInstruction *I2 = new VPInstruction(Instruction::Mul, {I1, I1}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {ExtVPV1, ExtVPV2}, + VPIRFlags::getDefaultFlags(Instruction::Add)); + VPInstruction *I2 = new VPInstruction( + Instruction::Mul, {I1, I1}, VPIRFlags::getDefaultFlags(Instruction::Mul)); // Check printing I1. { @@ -1642,8 +1701,9 @@ TEST(VPDoubleValueDefTest, traverseUseLists) { VPDoubleValueDef DoubleValueDef({&Op0, &Op1}); // Create a new users of the defined values. - VPInstruction I1(Instruction::Add, {DoubleValueDef.getVPValue(0), - DoubleValueDef.getVPValue(1)}); + VPInstruction I1(Instruction::Add, + {DoubleValueDef.getVPValue(0), DoubleValueDef.getVPValue(1)}, + VPIRFlags::getDefaultFlags(Instruction::Add)); VPInstruction I2(Instruction::Freeze, {DoubleValueDef.getVPValue(0)}); VPInstruction I3(Instruction::Freeze, {DoubleValueDef.getVPValue(1)}); diff --git a/llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp index 897c08b66563e..f07ee94105ff8 100644 --- a/llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp @@ -22,8 +22,12 @@ namespace { TEST_F(VPVerifierTest, VPInstructionUseBeforeDefSameBB) { VPlan &Plan = getPlan(); VPIRValue *Zero = Plan.getConstantInt(32, 0); - VPInstruction *DefI = new VPInstruction(Instruction::Add, {Zero, Zero}); - VPInstruction *UseI = new VPInstruction(Instruction::Sub, {DefI, Zero}); + VPInstruction *DefI = + new VPInstruction(Instruction::Add, {Zero, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Add)); + VPInstruction *UseI = + new VPInstruction(Instruction::Sub, {DefI, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Sub)); auto *CanIV = new VPCanonicalIVPHIRecipe(Zero, {}); VPBasicBlock *VPBB1 = Plan.getEntry(); @@ -57,8 +61,12 @@ TEST_F(VPVerifierTest, VPInstructionUseBeforeDefSameBB) { TEST_F(VPVerifierTest, VPInstructionUseBeforeDefDifferentBB) { VPlan &Plan = getPlan(); VPIRValue *Zero = Plan.getConstantInt(32, 0); - VPInstruction *DefI = new VPInstruction(Instruction::Add, {Zero, Zero}); - VPInstruction *UseI = new VPInstruction(Instruction::Sub, {DefI, Zero}); + VPInstruction *DefI = + new VPInstruction(Instruction::Add, {Zero, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Add)); + VPInstruction *UseI = + new VPInstruction(Instruction::Sub, {DefI, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Sub)); auto *CanIV = new VPCanonicalIVPHIRecipe(Zero, {}); VPInstruction *BranchOnCond = new VPInstruction(VPInstruction::BranchOnCond, {CanIV}); @@ -99,11 +107,13 @@ TEST_F(VPVerifierTest, VPBlendUseBeforeDefDifferentBB) { auto *Phi = PHINode::Create(Int32, 1); VPIRValue *Zero = Plan.getConstantInt(Int32, 0); - VPInstruction *DefI = new VPInstruction(Instruction::Add, {Zero, Zero}); + VPInstruction *DefI = + new VPInstruction(Instruction::Add, {Zero, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Add)); auto *CanIV = new VPCanonicalIVPHIRecipe(Zero, {}); VPInstruction *BranchOnCond = new VPInstruction(VPInstruction::BranchOnCond, {CanIV}); - auto *Blend = new VPBlendRecipe(Phi, {DefI, Plan.getTrue()}, {}); + auto *Blend = new VPBlendRecipe(Phi, {DefI, Plan.getTrue()}, {}, {}); VPBasicBlock *VPBB1 = Plan.getEntry(); VPBasicBlock *VPBB2 = Plan.createVPBasicBlock(""); @@ -153,8 +163,10 @@ TEST_F(VPVerifierTest, VPPhiIncomingValueDoesntDominateIncomingBlock) { VPBasicBlock *VPBB3 = Plan.createVPBasicBlock(""); VPBasicBlock *VPBB4 = Plan.createVPBasicBlock(""); - VPInstruction *DefI = new VPInstruction(Instruction::Add, {Zero, Zero}); - VPPhi *Phi = new VPPhi({DefI}, {}); + VPInstruction *DefI = + new VPInstruction(Instruction::Add, {Zero, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Add)); + VPPhi *Phi = new VPPhi({DefI}, {}, {}); VPBB2->appendRecipe(Phi); VPBB2->appendRecipe(DefI); auto *CanIV = new VPCanonicalIVPHIRecipe(Zero, {}); @@ -185,7 +197,9 @@ TEST_F(VPVerifierTest, VPPhiIncomingValueDoesntDominateIncomingBlock) { TEST_F(VPVerifierTest, DuplicateSuccessorsOutsideRegion) { VPlan &Plan = getPlan(); VPIRValue *Zero = Plan.getConstantInt(32, 0); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {Zero, Zero}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {Zero, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Add)); auto *CanIV = new VPCanonicalIVPHIRecipe(Zero, {}); VPInstruction *BranchOnCond = new VPInstruction(VPInstruction::BranchOnCond, {CanIV}); @@ -219,7 +233,9 @@ TEST_F(VPVerifierTest, DuplicateSuccessorsOutsideRegion) { TEST_F(VPVerifierTest, DuplicateSuccessorsInsideRegion) { VPlan &Plan = getPlan(); VPIRValue *Zero = Plan.getConstantInt(32, 0); - VPInstruction *I1 = new VPInstruction(Instruction::Add, {Zero, Zero}); + VPInstruction *I1 = + new VPInstruction(Instruction::Add, {Zero, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Add)); auto *CanIV = new VPCanonicalIVPHIRecipe(Zero, {}); VPInstruction *BranchOnCond = new VPInstruction(VPInstruction::BranchOnCond, {CanIV}); @@ -263,7 +279,9 @@ TEST_F(VPVerifierTest, BlockOutsideRegionWithParent) { auto *CanIV = new VPCanonicalIVPHIRecipe(Zero, {}); VPBB2->appendRecipe(CanIV); - VPInstruction *DefI = new VPInstruction(Instruction::Add, {Zero, Zero}); + VPInstruction *DefI = + new VPInstruction(Instruction::Add, {Zero, Zero}, + VPIRFlags::getDefaultFlags(Instruction::Add)); VPInstruction *BranchOnCond = new VPInstruction(VPInstruction::BranchOnCond, {DefI}); diff --git a/llvm/utils/FileCheck/FileCheck.cpp b/llvm/utils/FileCheck/FileCheck.cpp index 8c109ccab4dc6..12fdbfd45279d 100644 --- a/llvm/utils/FileCheck/FileCheck.cpp +++ b/llvm/utils/FileCheck/FileCheck.cpp @@ -594,7 +594,7 @@ static void DumpAnnotatedInput(raw_ostream &OS, const FileCheckRequest &Req, unsigned LineCount = InputFileText.count('\n'); if (InputFileEnd[-1] != '\n') ++LineCount; - unsigned LineNoWidth = std::log10(LineCount) + 1; + unsigned LineNoWidth = NumDigitsBase10(LineCount); // +3 below adds spaces (1) to the left of the (right-aligned) line numbers // on input lines and (2) to the right of the (left-aligned) labels on // annotation lines so that input lines and annotation lines are more diff --git a/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp b/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp index 9fed5920a019f..5a2b2f89d5582 100644 --- a/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp +++ b/llvm/utils/TableGen/Basic/IntrinsicEmitter.cpp @@ -22,6 +22,7 @@ #include "llvm/Support/ModRef.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/TableGen/CodeGenHelpers.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/StringToOffsetTable.h" @@ -157,13 +158,17 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints, } // Generate a complete header for target specific intrinsics. + std::optional IfDef; + std::optional IncGuard; + std::optional NS; + if (IntrinsicPrefix.empty()) { - OS << "#ifdef GET_INTRINSIC_ENUM_VALUES\n"; + IfDef.emplace(OS, "GET_INTRINSIC_ENUM_VALUES"); } else { std::string UpperPrefix = StringRef(IntrinsicPrefix).upper(); - OS << formatv("#ifndef LLVM_IR_INTRINSIC_{}_ENUMS_H\n", UpperPrefix); - OS << formatv("#define LLVM_IR_INTRINSIC_{}_ENUMS_H\n", UpperPrefix); - OS << "namespace llvm::Intrinsic {\n"; + IncGuard.emplace( + OS, formatv("LLVM_IR_INTRINSIC_{}_ENUMS_H", UpperPrefix).str()); + NS.emplace(OS, "llvm::Intrinsic"); OS << formatv("enum {}Intrinsics : unsigned {{\n", UpperPrefix); } @@ -188,34 +193,27 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints, } // Emit num_intrinsics into the target neutral enum. - if (IntrinsicPrefix.empty()) { + if (IntrinsicPrefix.empty()) OS << formatv(" num_intrinsics = {}\n", Ints.size() + 1); - OS << "#endif\n\n"; - } else { - OS << R"(}; // enum -} // namespace llvm::Intrinsic -#endif - -)"; - } + else + OS << "}; // enum\n"; } void IntrinsicEmitter::EmitArgKind(raw_ostream &OS) { if (!IntrinsicPrefix.empty()) return; + IfDefEmitter IfDef(OS, "GET_INTRINSIC_ARGKIND"); OS << "// llvm::Intrinsic::IITDescriptor::ArgKind.\n"; - OS << "#ifdef GET_INTRINSIC_ARGKIND\n"; if (const auto RecArgKind = Records.getDef("ArgKind")) { for (const auto &RV : RecArgKind->getValues()) OS << " AK_" << RV.getName() << " = " << *RV.getValue() << ",\n"; } else { OS << "#error \"ArgKind is not defined\"\n"; } - OS << "#endif\n\n"; } void IntrinsicEmitter::EmitIITInfo(raw_ostream &OS) { - OS << "#ifdef GET_INTRINSIC_IITINFO\n"; + IfDefEmitter IfDef(OS, "GET_INTRINSIC_IITINFO"); std::array RecsByNumber; auto IIT_Base = Records.getAllDerivedDefinitionsIfDefined("IIT_Base"); for (const Record *Rec : IIT_Base) { @@ -232,13 +230,12 @@ void IntrinsicEmitter::EmitIITInfo(raw_ostream &OS) { } else { OS << "#error \"class IIT_Base is not defined\"\n"; } - OS << "#endif\n\n"; } void IntrinsicEmitter::EmitTargetInfo(const CodeGenIntrinsicTable &Ints, raw_ostream &OS) { + IfDefEmitter IfDef(OS, "GET_INTRINSIC_TARGET_DATA"); OS << R"(// Target mapping. -#ifdef GET_INTRINSIC_TARGET_DATA struct IntrinsicTargetInfo { StringLiteral Name; size_t Offset; @@ -248,10 +245,7 @@ static constexpr IntrinsicTargetInfo TargetInfos[] = { )"; for (const auto [Name, Offset, Count] : Ints.getTargets()) OS << formatv(" {{\"{}\", {}, {}},\n", Name, Offset, Count); - OS << R"(}; -#endif - -)"; + OS << "};\n"; } /// Helper function to emit a bit table for intrinsic properties. @@ -260,8 +254,8 @@ void IntrinsicEmitter::EmitIntrinsicBitTable( const CodeGenIntrinsicTable &Ints, raw_ostream &OS, StringRef Guard, StringRef TableName, StringRef Comment, function_ref GetProperty) { + IfDefEmitter IfDef(OS, Guard); OS << formatv("// {}\n", Comment); - OS << formatv("#ifdef {}\n", Guard); OS << formatv("static constexpr uint8_t {}[] = {{\n", TableName); OS << " 0\n "; for (auto [I, Int] : enumerate(Ints)) { @@ -274,7 +268,6 @@ void IntrinsicEmitter::EmitIntrinsicBitTable( } OS << "\n};\n\n"; OS << formatv("return ({}[id/8] & (1 << (id%8))) != 0;\n", TableName); - OS << formatv("#endif // {}\n\n", Guard); } void IntrinsicEmitter::EmitIntrinsicToNameTable( @@ -286,8 +279,8 @@ void IntrinsicEmitter::EmitIntrinsicToNameTable( for (const auto &Int : Ints) Table.GetOrAddStringOffset(Int.Name); + IfDefEmitter IfDef(OS, "GET_INTRINSIC_NAME_TABLE"); OS << R"(// Intrinsic ID to name table. -#ifdef GET_INTRINSIC_NAME_TABLE // Note that entry #0 is the invalid intrinsic! )"; @@ -303,12 +296,7 @@ static constexpr unsigned IntrinsicNameOffsetTable[] = { for (const auto &Int : Ints) OS << formatv(" {}, // {}\n", Table.GetStringOffset(Int.Name), Int.Name); - OS << R"( -}; // IntrinsicNameOffsetTable - -#endif - -)"; + OS << "\n}; // IntrinsicNameOffsetTable\n"; } void IntrinsicEmitter::EmitIntrinsicToOverloadTable( @@ -354,9 +342,9 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints, using FixedEncodingTy = std::conditional_t; constexpr unsigned FixedEncodingBits = sizeof(FixedEncodingTy) * CHAR_BIT; + constexpr unsigned MSBPosition = FixedEncodingBits - 1; // Mask with all bits 1 except the most significant bit. - const unsigned Mask = (1U << (FixedEncodingBits - 1)) - 1; - const unsigned MSBPostion = FixedEncodingBits - 1; + constexpr unsigned Mask = (1U << MSBPosition) - 1; StringRef FixedEncodingTypeName = Use16BitFixedEncoding ? "uint16_t" : "uint32_t"; @@ -374,7 +362,7 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints, // Check to see if we can encode it into a 16/32 bit word. std::optional Result = encodePacked(TypeSig); - if (Result && (*Result & Mask) == Result) { + if (Result && (*Result & Mask) == *Result) { FixedEncodings.push_back(static_cast(*Result)); continue; } @@ -387,9 +375,10 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints, LongEncodingTable.layout(); + IfDefEmitter IfDef(OS, "GET_INTRINSIC_GENERATOR_GLOBAL"); OS << formatv(R"(// Global intrinsic function declaration type table. -#ifdef GET_INTRINSIC_GENERATOR_GLOBAL -static constexpr {} IIT_Table[] = {{ +using FixedEncodingTy = {}; +static constexpr FixedEncodingTy IIT_Table[] = {{ )", FixedEncodingTypeName); @@ -410,7 +399,7 @@ static constexpr {} IIT_Table[] = {{ // Otherwise, emit the offset into the long encoding table. We emit it this // way so that it is easier to read the offset in the .def file. - OS << formatv("(1U<<{}) | {}, ", MSBPostion, Offset); + OS << formatv("(1U<<{}) | {}, ", MSBPosition, Offset); } OS << "0\n};\n\n"; @@ -425,7 +414,6 @@ static constexpr {} IIT_Table[] = {{ LongEncodingTable.emit( OS, [](raw_ostream &OS, unsigned char C) { OS << (unsigned)C; }); OS << " 255\n};\n"; - OS << "#endif\n\n"; // End of GET_INTRINSIC_GENERATOR_GLOBAL } /// Returns the effective MemoryEffects for intrinsic \p Int. @@ -524,8 +512,8 @@ static StringRef getArgAttrEnumName(CodeGenIntrinsic::ArgAttrKind Kind) { /// EmitAttributes - This emits the Intrinsic::getAttributes method. void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints, raw_ostream &OS) { + IfDefEmitter IfDef(OS, "GET_INTRINSIC_ATTRIBUTES"); OS << R"(// Add parameter attributes that are not common to all intrinsics. -#ifdef GET_INTRINSIC_ATTRIBUTES static AttributeSet getIntrinsicArgAttributeSet(LLVMContext &C, unsigned ID, Type *ArgType) { unsigned BitWidth = ArgType->getScalarSizeInBits(); @@ -666,10 +654,6 @@ static AttributeSet getIntrinsicFnAttributeSet(LLVMContext &C, unsigned ID) { AttributesMapDataBitSize = 8; else if (AttributesMapDataBitSize > 64) PrintFatalError("Packed ID of IntrinsicsToAttributesMap exceeds 64b!"); - else if (AttributesMapDataBitSize > 16) - PrintWarning("Packed ID of IntrinsicsToAttributesMap exceeds 16b, " - "this may cause performance drop (pr106809), " - "please consider redesigning intrinsic sets!"); // Assign a packed ID for each intrinsic. The lower bits will be its // "argument attribute ID" (index in UniqAttributes) and upper bits will be @@ -825,8 +809,6 @@ AttributeSet Intrinsic::getFnAttributes(LLVMContext &C, ID id) {{ return AttributeSet(); return getIntrinsicFnAttributeSet(C, FnAttrID); } -#endif // GET_INTRINSIC_ATTRIBUTES - )", UniqAttributesBitSize, MaxNumAttrs, NoFunctionAttrsID, NoFunctionAttrsID); @@ -843,8 +825,8 @@ void IntrinsicEmitter::EmitIntrinsicToPrettyPrintTable( void IntrinsicEmitter::EmitPrettyPrintArguments( const CodeGenIntrinsicTable &Ints, raw_ostream &OS) { + IfDefEmitter IfDef(OS, "GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS"); OS << R"( -#ifdef GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS void Intrinsic::printImmArg(ID IID, unsigned ArgIdx, raw_ostream &OS, const Constant *ImmArgVal) { using namespace Intrinsic; switch (IID) { @@ -873,9 +855,7 @@ void Intrinsic::printImmArg(ID IID, unsigned ArgIdx, raw_ostream &OS, const Cons OS << R"( default: break; } -} -#endif // GET_INTRINSIC_PRETTY_PRINT_ARGUMENTS -)"; +})"; } void IntrinsicEmitter::EmitIntrinsicToBuiltinMap( @@ -930,25 +910,22 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap( } } + IfDefEmitter IfDef( + OS, + formatv("GET_LLVM_INTRINSIC_FOR_{}_BUILTIN", UpperCompilerName).str()); OS << formatv(R"( // Get the LLVM intrinsic that corresponds to a builtin. This is used by the // C front-end. The builtin name is passed in as BuiltinName, and a target // prefix (e.g. 'ppc') is passed in as TargetPrefix. -#ifdef GET_LLVM_INTRINSIC_FOR_{}_BUILTIN Intrinsic::ID Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix, StringRef BuiltinName) {{ using namespace Intrinsic; )", - UpperCompilerName, CompilerName); + CompilerName); if (BuiltinMap.empty()) { - OS << formatv(R"( - return not_intrinsic; - } -#endif // GET_LLVM_INTRINSIC_FOR_{}_BUILTIN -)", - UpperCompilerName); + OS << "return not_intrinsic;\n"; return; } @@ -1035,7 +1012,7 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix, } // If a target independent builtin was not found, lookup the target specific. - OS << formatv(R"( + OS << R"( auto TI = lower_bound(TargetTable, TargetPrefix); if (TI == std::end(TargetTable) || TI->TargetPrefix != TargetPrefix) return not_intrinsic; @@ -1048,10 +1025,7 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix, return not_intrinsic; return II->IntrinsicID; } -#endif // GET_LLVM_INTRINSIC_FOR_{}_BUILTIN - -)", - UpperCompilerName); +)"; } static TableGen::Emitter::OptClass> diff --git a/llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp index f7959376adc4a..24f122b4cb178 100644 --- a/llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/Basic/RISCVTargetDefEmitter.cpp @@ -13,8 +13,11 @@ #include "llvm/ADT/DenseSet.h" #include "llvm/Support/Format.h" +#include "llvm/Support/FormatVariadic.h" #include "llvm/Support/RISCVISAUtils.h" +#include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" +#include "llvm/TableGen/StringToOffsetTable.h" #include "llvm/TableGen/TableGenBackend.h" using namespace llvm; @@ -259,7 +262,118 @@ static void emitRISCVExtensionBitmask(const RecordKeeper &RK, raw_ostream &OS) { << "},\n"; } OS << "};\n"; - OS << "#endif\n"; + OS << "#endif\n\n"; +} + +static void emitRISCVTuneFeatures(const RecordKeeper &RK, + StringToOffsetTable &StrTable, + raw_ostream &OS) { + std::vector TuneFeatureRecords = + RK.getAllDerivedDefinitionsIfDefined("RISCVTuneFeature"); + + // {Post Directive Idx, Neg Directive Idx, TuneFeature Record} + SmallVector> + TuneFeatureDirectives; + // {Directive Idx -> Original Record} + // This is primarily for diagnosing purposes -- when there is a duplication, + // we are able to pointed out the previous definition. + DenseMap DirectiveToRecord; + // A list of {Feature Name, Implied Feature Name} + SmallVector> ImpliedFeatureList; + + for (const auto *R : TuneFeatureRecords) { + // Preemptively insert feature name into the string table because we know + // it will be used later. + StringRef FeatureName = R->getValueAsString("Name"); + StrTable.GetOrAddStringOffset(FeatureName); + + StringRef PosName = R->getValueAsString("PositiveDirectiveName"); + StringRef NegName = R->getValueAsString("NegativeDirectiveName"); + unsigned PosIdx = StrTable.GetOrAddStringOffset(PosName); + if (auto [ItEntry, Inserted] = DirectiveToRecord.try_emplace(PosIdx, R); + !Inserted) { + PrintError(R, "RISC-V tune feature positive directive '" + + Twine(PosName) + "' was already defined"); + PrintFatalNote(ItEntry->second, "Previously defined here"); + } + unsigned NegIdx = StrTable.GetOrAddStringOffset(NegName); + if (auto [ItEntry, Inserted] = DirectiveToRecord.try_emplace(NegIdx, R); + !Inserted) { + PrintError(R, "RISC-V tune feature negative directive '" + + Twine(NegName) + "' was already defined"); + PrintFatalNote(ItEntry->second, "Previously defined here"); + } + + TuneFeatureDirectives.emplace_back(PosIdx, NegIdx, R); + } + + for (const auto *R : TuneFeatureRecords) { + std::vector Implies = R->getValueAsListOfDefs("Implies"); + for (const auto *ImpliedRecord : Implies) { + StringRef CurrFeatureName = R->getValueAsString("Name"); + StringRef ImpliedFeatureName = ImpliedRecord->getValueAsString("Name"); + + ImpliedFeatureList.emplace_back(CurrFeatureName, ImpliedFeatureName); + } + } + + OS << "#ifdef GET_TUNE_FEATURES\n"; + OS << "#undef GET_TUNE_FEATURES\n\n"; + + StrTable.EmitStringTableDef(OS, "TuneFeatureStrings"); + OS << "\n"; + + OS << "static constexpr RISCVTuneFeature TuneFeatures[] = {\n"; + for (const auto &[PosIdx, NegIdx, R] : TuneFeatureDirectives) { + StringRef FeatureName = R->getValueAsString("Name"); + OS.indent(4) << formatv("{{ {0}, {1}, {2} },\t// '{3}'\n", PosIdx, NegIdx, + *StrTable.GetStringOffset(FeatureName), + FeatureName); + } + OS << "};\n\n"; + + OS << "static constexpr RISCVImpliedTuneFeature ImpliedTuneFeatures[] = {\n"; + for (auto [Feature, ImpliedFeature] : ImpliedFeatureList) + OS.indent(4) << formatv("{{ {0}, {1} }, // '{2}' -> '{3}'\n", + *StrTable.GetStringOffset(Feature), + *StrTable.GetStringOffset(ImpliedFeature), Feature, + ImpliedFeature); + OS << "};\n\n"; + + OS << "#endif // GET_TUNE_FEATURES\n\n"; +} + +static void +emitRISCVConfigurableTuneFeatures(const RecordKeeper &RK, + const StringToOffsetTable &StrTable, + raw_ostream &OS) { + std::vector AllProcModels = + RK.getAllDerivedDefinitionsIfDefined("ProcessorModel"); + + OS << "#ifdef GET_CONFIGURABLE_TUNE_FEATURES\n"; + OS << "#undef GET_CONFIGURABLE_TUNE_FEATURES\n\n"; + + OS << "static constexpr RISCVConfigurableTuneFeatures " + "ConfigurableTuneFeatures[] = {\n"; + + for (const Record *Proc : AllProcModels) { + StringRef ProcName = Proc->getValueAsString("Name"); + std::vector TuneFeatures = + Proc->getValueAsListOfDefs("ConfigurableTuneFeatures"); + for (const Record *TF : TuneFeatures) { + unsigned PosDirectiveIdx = *StrTable.GetStringOffset( + TF->getValueAsString("PositiveDirectiveName")); + unsigned NegDirectiveIdx = *StrTable.GetStringOffset( + TF->getValueAsString("NegativeDirectiveName")); + OS.indent(4) << formatv("{{ {{ \"{0}\" }, {1} },\n", ProcName, + PosDirectiveIdx); + OS.indent(4) << formatv("{{ {{ \"{0}\" }, {1} },\n", ProcName, + NegDirectiveIdx); + } + } + + OS << "};\n\n"; + OS << "#endif // GET_CONFIGURABLE_TUNE_FEATURES\n"; } static void emitRiscvTargetDef(const RecordKeeper &RK, raw_ostream &OS) { @@ -267,6 +381,10 @@ static void emitRiscvTargetDef(const RecordKeeper &RK, raw_ostream &OS) { emitRISCVProfiles(RK, OS); emitRISCVProcs(RK, OS); emitRISCVExtensionBitmask(RK, OS); + + StringToOffsetTable TuneFeatureStrTable; + emitRISCVTuneFeatures(RK, TuneFeatureStrTable, OS); + emitRISCVConfigurableTuneFeatures(RK, TuneFeatureStrTable, OS); } static TableGen::Emitter::Opt X("gen-riscv-target-def", emitRiscvTargetDef, diff --git a/llvm/utils/TableGen/Basic/TargetLibraryInfoEmitter.cpp b/llvm/utils/TableGen/Basic/TargetLibraryInfoEmitter.cpp index 253d9df44421a..0aff464e08c5b 100644 --- a/llvm/utils/TableGen/Basic/TargetLibraryInfoEmitter.cpp +++ b/llvm/utils/TableGen/Basic/TargetLibraryInfoEmitter.cpp @@ -10,6 +10,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/TableGen/CodeGenHelpers.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/SetTheory.h" @@ -56,13 +57,11 @@ TargetLibraryInfoEmitter::TargetLibraryInfoEmitter(const RecordKeeper &R) // function. void TargetLibraryInfoEmitter::emitTargetLibraryInfoEnum( raw_ostream &OS) const { - OS << "#ifdef GET_TARGET_LIBRARY_INFO_ENUM\n"; - OS << "#undef GET_TARGET_LIBRARY_INFO_ENUM\n"; + IfDefEmitter IfDef(OS, "GET_TARGET_LIBRARY_INFO_ENUM"); OS << "enum LibFunc : unsigned {\n"; OS.indent(2) << "NotLibFunc = 0,\n"; - for (const auto *R : AllTargetLibcalls) { + for (const auto *R : AllTargetLibcalls) OS.indent(2) << "LibFunc_" << R->getName() << ",\n"; - } OS.indent(2) << "NumLibFuncs,\n"; OS.indent(2) << "End_LibFunc = NumLibFuncs,\n"; if (AllTargetLibcalls.size()) { @@ -72,7 +71,6 @@ void TargetLibraryInfoEmitter::emitTargetLibraryInfoEnum( OS.indent(2) << "Begin_LibFunc = NotLibFunc,\n"; } OS << "};\n"; - OS << "#endif\n\n"; } // The names of the functions are stored in a long string, along with support @@ -86,37 +84,37 @@ void TargetLibraryInfoEmitter::emitTargetLibraryInfoStringTable( for (const auto *R : AllTargetLibcalls) Table.GetOrAddStringOffset(R->getValueAsString("String")); - OS << "#ifdef GET_TARGET_LIBRARY_INFO_STRING_TABLE\n"; - OS << "#undef GET_TARGET_LIBRARY_INFO_STRING_TABLE\n"; - Table.EmitStringTableDef(OS, "StandardNamesStrTable"); - OS << "\n"; size_t NumEl = AllTargetLibcalls.size() + 1; - OS << "const llvm::StringTable::Offset " - "TargetLibraryInfoImpl::StandardNamesOffsets[" - << NumEl - << "] = " - "{\n"; - OS.indent(2) << "0, //\n"; - for (const auto *R : AllTargetLibcalls) { - StringRef Str = R->getValueAsString("String"); - OS.indent(2) << Table.GetStringOffset(Str) << ", // " << Str << "\n"; + + { + IfDefEmitter IfDef(OS, "GET_TARGET_LIBRARY_INFO_STRING_TABLE"); + Table.EmitStringTableDef(OS, "StandardNamesStrTable"); + OS << "\n"; + OS << "const llvm::StringTable::Offset " + "TargetLibraryInfoImpl::StandardNamesOffsets[" + << NumEl + << "] = " + "{\n"; + OS.indent(2) << "0, //\n"; + for (const auto *R : AllTargetLibcalls) { + StringRef Str = R->getValueAsString("String"); + OS.indent(2) << Table.GetStringOffset(Str) << ", // " << Str << "\n"; + } + OS << "};\n"; + OS << "const uint8_t TargetLibraryInfoImpl::StandardNamesSizeTable[" + << NumEl << "] = {\n"; + OS << " 0,\n"; + for (const auto *R : AllTargetLibcalls) + OS.indent(2) << R->getValueAsString("String").size() << ",\n"; + OS << "};\n"; } - OS << "};\n"; - OS << "const uint8_t TargetLibraryInfoImpl::StandardNamesSizeTable[" << NumEl - << "] = {\n"; - OS << " 0,\n"; - for (const auto *R : AllTargetLibcalls) - OS.indent(2) << R->getValueAsString("String").size() << ",\n"; - OS << "};\n"; - OS << "#endif\n\n"; - OS << "#ifdef GET_TARGET_LIBRARY_INFO_IMPL_DECL\n"; - OS << "#undef GET_TARGET_LIBRARY_INFO_IMPL_DECL\n"; + + IfDefEmitter IfDef(OS, "GET_TARGET_LIBRARY_INFO_IMPL_DECL"); OS << "LLVM_ABI static const llvm::StringTable StandardNamesStrTable;\n"; OS << "LLVM_ABI static const llvm::StringTable::Offset StandardNamesOffsets[" << NumEl << "];\n"; OS << "LLVM_ABI static const uint8_t StandardNamesSizeTable[" << NumEl << "];\n"; - OS << "#endif\n\n"; } // Since there are much less type signatures then library functions, the type @@ -152,13 +150,11 @@ void TargetLibraryInfoEmitter::emitTargetLibraryInfoSignatureTable( SignatureTable.add(GetSignature(R)); SignatureTable.layout(); - OS << "#ifdef GET_TARGET_LIBRARY_INFO_SIGNATURE_TABLE\n"; - OS << "#undef GET_TARGET_LIBRARY_INFO_SIGNATURE_TABLE\n"; + IfDefEmitter IfDef(OS, "GET_TARGET_LIBRARY_INFO_SIGNATURE_TABLE"); OS << "enum FuncArgTypeID : char {\n"; OS.indent(2) << "NoFuncArgType = 0,\n"; - for (const auto *R : FuncTypeArgs) { + for (const auto *R : FuncTypeArgs) OS.indent(2) << R->getName() << ",\n"; - } OS << "};\n"; OS << "static const FuncArgTypeID SignatureTable[] = {\n"; SignatureTable.emit(OS, [](raw_ostream &OS, StringRef E) { OS << E; }); @@ -170,7 +166,6 @@ void TargetLibraryInfoEmitter::emitTargetLibraryInfoSignatureTable( << R->getName() << "\n"; } OS << "};\n"; - OS << "#endif\n\n"; } void TargetLibraryInfoEmitter::run(raw_ostream &OS) { diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp index 1dce0baa5f898..15b8949a92d44 100644 --- a/llvm/utils/TableGen/CompressInstEmitter.cpp +++ b/llvm/utils/TableGen/CompressInstEmitter.cpp @@ -72,6 +72,7 @@ #include "llvm/ADT/StringMap.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/TableGen/CodeGenHelpers.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" @@ -608,15 +609,19 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS, raw_string_ostream Func(F); raw_string_ostream FuncH(FH); - if (EType == EmitterType::Compress) - OS << "\n#ifdef GEN_COMPRESS_INSTR\n" - << "#undef GEN_COMPRESS_INSTR\n\n"; - else if (EType == EmitterType::Uncompress) - OS << "\n#ifdef GEN_UNCOMPRESS_INSTR\n" - << "#undef GEN_UNCOMPRESS_INSTR\n\n"; - else if (EType == EmitterType::CheckCompress) - OS << "\n#ifdef GEN_CHECK_COMPRESS_INSTR\n" - << "#undef GEN_CHECK_COMPRESS_INSTR\n\n"; + auto GetEmitterGuard = [EType]() -> StringRef { + switch (EType) { + case EmitterType::Compress: + return "GEN_COMPRESS_INSTR"; + case EmitterType::Uncompress: + return "GEN_UNCOMPRESS_INSTR"; + case EmitterType::CheckCompress: + return "GEN_CHECK_COMPRESS_INSTR"; + } + llvm_unreachable("Invalid emitter type"); + }; + + IfDefEmitter IfDef(OS, GetEmitterGuard()); if (EType == EmitterType::Compress) { FuncH << "static bool compressInst(MCInst &OutInst,\n"; @@ -638,12 +643,6 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS, if (CompressPatterns.empty()) { OS << FH; OS.indent(2) << "return false;\n}\n"; - if (EType == EmitterType::Compress) - OS << "\n#endif //GEN_COMPRESS_INSTR\n"; - else if (EType == EmitterType::Uncompress) - OS << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n"; - else if (EType == EmitterType::CheckCompress) - OS << "\n#endif //GEN_CHECK_COMPRESS_INSTR\n\n"; return; } @@ -940,13 +939,6 @@ void CompressInstEmitter::emitCompressInstEmitter(raw_ostream &OS, OS << FH; OS << F; - - if (EType == EmitterType::Compress) - OS << "\n#endif //GEN_COMPRESS_INSTR\n"; - else if (EType == EmitterType::Uncompress) - OS << "\n#endif //GEN_UNCOMPRESS_INSTR\n\n"; - else if (EType == EmitterType::CheckCompress) - OS << "\n#endif //GEN_CHECK_COMPRESS_INSTR\n\n"; } void CompressInstEmitter::run(raw_ostream &OS) { diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp index 9bb5a8415ba19..1058e7567805d 100644 --- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "Basic/SDNodeProperties.h" +#include "Basic/SequenceToOffsetTable.h" #include "Common/CodeGenDAGPatterns.h" #include "Common/CodeGenInstruction.h" #include "Common/CodeGenRegisters.h" @@ -73,6 +74,8 @@ class MatcherTableEmitter { std::map ValueTypeMap; + SequenceToOffsetTable> OperandTable; + unsigned getPatternIdxFromTable(std::string &&P, std::string &&include_loc) { const auto [It, Inserted] = VecPatterns.try_emplace(std::move(P), VecPatterns.size()); @@ -85,7 +88,8 @@ class MatcherTableEmitter { public: MatcherTableEmitter(const Matcher *TheMatcher, const CodeGenDAGPatterns &cgp) - : CGP(cgp), OpcodeCounts(Matcher::HighestKind + 1, 0) { + : CGP(cgp), OpcodeCounts(Matcher::HighestKind + 1, 0), + OperandTable(std::nullopt) { // Record the usage of ComplexPattern. MapVector ComplexPatternUsage; // Record the usage of PatternPredicate. @@ -111,11 +115,26 @@ class MatcherTableEmitter { ++PatternPredicateUsage[CPPM->getPredicate()]; else if (auto *PM = dyn_cast(N)) ++PredicateUsage[PM->getPredicate().getOrigPatFragRecord()]; + + if (const auto *EN = dyn_cast(N)) { + ArrayRef Ops = EN->getOperandList(); + std::vector OpBytes; + for (unsigned Op : Ops) { + uint8_t Buffer[5]; + unsigned Len = encodeULEB128(Op, Buffer); + for (unsigned i = 0; i < Len; ++i) + OpBytes.push_back(Buffer[i]); + } + OperandTable.add(OpBytes); + } + N = N->getNext(); } }; Statistic(TheMatcher); + OperandTable.layout(); + // Sort ComplexPatterns by usage. std::vector> ComplexPatternList( ComplexPatternUsage.begin(), ComplexPatternUsage.end()); @@ -172,6 +191,8 @@ class MatcherTableEmitter { unsigned EmitMatcherList(const Matcher *N, const unsigned Indent, unsigned StartIdx, raw_ostream &OS); + void EmitOperandLists(raw_ostream &OS); + unsigned SizeMatcherList(Matcher *N, raw_ostream &OS); void EmitPredicateFunctions(raw_ostream &OS); @@ -1112,21 +1133,42 @@ unsigned MatcherTableEmitter::EmitMatcher(const Matcher *N, } } - OS << ' ' << EN->getNumOperands(); + unsigned NumOps = EN->getNumOperands(); + OS << ' ' << NumOps; if (!OmitComments) OS << "/*#Ops*/"; OS << ','; + unsigned NumOperandBytes = 0; - for (unsigned i = 0, e = EN->getNumOperands(); i != e; ++i) { + if (NumOps != 0) { + std::vector OpBytes; + for (unsigned i = 0, e = EN->getNumOperands(); i != e; ++i) { + uint8_t Buffer[5]; + unsigned Len = encodeULEB128(EN->getOperand(i), Buffer); + for (unsigned i = 0; i < Len; ++i) + OpBytes.push_back(Buffer[i]); + } + unsigned Index = OperandTable.get(OpBytes); OS << ' '; - NumOperandBytes += EmitVBRValue(EN->getOperand(i), OS); + if (!OmitComments) + OS << "/*OperandList*/"; + NumOperandBytes = EmitVBRValue(Index, OS); } if (!OmitComments) { + // Print the operand #'s. + ArrayRef Ops = EN->getOperandList(); + OS << " // Ops ="; + if (Ops.empty()) + OS << " None"; + else + for (unsigned OpNo : Ops) + OS << " #" << OpNo; + // Print the result #'s for EmitNode. if (const EmitNodeMatcher *E = dyn_cast(EN)) { if (unsigned NumResults = EN->getNumVTs()) { - OS << " // Results ="; + OS << " Results ="; unsigned First = E->getFirstResultSlot(); for (unsigned i = 0; i != NumResults; ++i) OS << " #" << First + i; @@ -1209,6 +1251,10 @@ unsigned MatcherTableEmitter::EmitMatcherList(const Matcher *N, return Size; } +void MatcherTableEmitter::EmitOperandLists(raw_ostream &OS) { + OperandTable.emit(OS, [](raw_ostream &OS, uint8_t O) { OS << (unsigned)O; }); +} + void MatcherTableEmitter::EmitNodePredicatesFunction( const std::vector &Preds, StringRef Decl, raw_ostream &OS) { if (Preds.empty()) @@ -1544,9 +1590,14 @@ void llvm::EmitMatcherTable(Matcher *TheMatcher, const CodeGenDAGPatterns &CGP, MatcherEmitter.EmitHistogram(OS); + OS << " static const uint8_t OperandLists[] = {\n"; + MatcherEmitter.EmitOperandLists(OS); + OS << " };\n\n"; + OS << " #undef COVERAGE_IDX_VAL\n"; OS << " #undef TARGET_VAL\n"; - OS << " SelectCodeCommon(N, MatcherTable, sizeof(MatcherTable));\n"; + OS << " SelectCodeCommon(N, MatcherTable, sizeof(MatcherTable),\n"; + OS << " OperandLists);\n"; OS << "}\n"; EndEmitFunction(OS); diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp index 5d41b7dc3c311..664c3009ff504 100644 --- a/llvm/utils/TableGen/DecoderEmitter.cpp +++ b/llvm/utils/TableGen/DecoderEmitter.cpp @@ -656,8 +656,14 @@ static std::vector getIslands(const KnownBits &EncodingBits, if (!IsFiltered && IsKnown) { if (OnIsland) { // Accumulate island bits. - FieldVal |= static_cast(EncodingBits.One[I]) - << (I - StartBit); + const unsigned BitNo = I - StartBit; + FieldVal |= static_cast(EncodingBits.One[I]) << (BitNo); + // If island becomes larger than 64-bits complete the island and start a + // new one + if (BitNo >= 63) { + Islands.push_back({StartBit, 64, FieldVal}); + OnIsland = false; + } } else { // Onto an island. StartBit = I; diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index 84024ec086808..15b5ae24bd5d1 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -1849,19 +1849,19 @@ Error GlobalISelEmitter::constrainOperands(action_iterator InsertPt, // an explicitly given register class, we'll use that. Otherwise, we will // fail. const CodeGenRegisterClass *SubClass = - inferRegClassFromPattern(Dst.getChild(1)); + inferRegClassFromPattern(Dst.getChild(0)); if (!SubClass) return failedImport( - "Cannot infer register class from SUBREG_TO_REG child #1"); + "Cannot infer register class from SUBREG_TO_REG child #0"); // We don't have a child to look at that might have a super register node. const CodeGenRegisterClass *SuperClass = - inferSuperRegisterClass(Dst.getExtType(0), Dst.getChild(2)); + inferSuperRegisterClass(Dst.getExtType(0), Dst.getChild(1)); if (!SuperClass) return failedImport( "Cannot infer register class for SUBREG_TO_REG operand #0"); M.insertAction(InsertPt, InsnID, 0, *SuperClass); - M.insertAction(InsertPt, InsnID, 2, + M.insertAction(InsertPt, InsnID, 1, *SubClass); } else if (DstIName == "REG_SEQUENCE") { const CodeGenRegisterClass *SuperClass = @@ -2004,10 +2004,10 @@ GlobalISelEmitter::inferRegClassFromInstructionPattern(const TreePatternNode &N, } if (InstName == "SUBREG_TO_REG") { - // (outs $super_dst), (ins $super_src, $sub_src, $sub_idx) + // (outs $super_dst), (ins $sub_src, $sub_idx) // Find a register class that supports both the specified sub-register // index and the type of the instruction's result. - return inferSuperRegisterClass(N.getExtType(0), N.getChild(2)); + return inferSuperRegisterClass(N.getExtType(0), N.getChild(1)); } // Handle destination record types that we can safely infer a register class diff --git a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp index 93bdea665d5c9..742a73cf4b025 100644 --- a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp +++ b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp @@ -41,6 +41,7 @@ #include "Common/CodeGenTarget.h" #include "Common/PredicateExpander.h" #include "llvm/Support/Debug.h" +#include "llvm/TableGen/CodeGenHelpers.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" @@ -78,26 +79,21 @@ class MacroFusionPredicatorEmitter { void MacroFusionPredicatorEmitter::emitMacroFusionDecl( ArrayRef Fusions, PredicateExpander &PE, raw_ostream &OS) { - OS << "#ifdef GET_" << Target.getName() << "_MACRO_FUSION_PRED_DECL\n"; - OS << "#undef GET_" << Target.getName() << "_MACRO_FUSION_PRED_DECL\n\n"; - OS << "namespace llvm {\n"; + IfDefEmitter IfDef( + OS, ("GET_" + Target.getName() + "_MACRO_FUSION_PRED_DECL").str()); + NamespaceEmitter LlvmNS(OS, "llvm"); - for (const Record *Fusion : Fusions) { + for (const Record *Fusion : Fusions) OS << "bool is" << Fusion->getName() << "(const TargetInstrInfo &, " - << "const TargetSubtargetInfo &, " - << "const MachineInstr *, " + << "const TargetSubtargetInfo &, const MachineInstr *, " << "const MachineInstr &);\n"; - } - - OS << "} // end namespace llvm\n"; - OS << "\n#endif\n"; } void MacroFusionPredicatorEmitter::emitMacroFusionImpl( ArrayRef Fusions, PredicateExpander &PE, raw_ostream &OS) { - OS << "#ifdef GET_" << Target.getName() << "_MACRO_FUSION_PRED_IMPL\n"; - OS << "#undef GET_" << Target.getName() << "_MACRO_FUSION_PRED_IMPL\n\n"; - OS << "namespace llvm {\n"; + IfDefEmitter IfDef( + OS, ("GET_" + Target.getName() + "_MACRO_FUSION_PRED_IMPL").str()); + NamespaceEmitter LlvmNS(OS, "llvm"); for (const Record *Fusion : Fusions) { std::vector Predicates = @@ -117,9 +113,6 @@ void MacroFusionPredicatorEmitter::emitMacroFusionImpl( OS.indent(2) << "return true;\n"; OS << "}\n"; } - - OS << "} // end namespace llvm\n"; - OS << "\n#endif\n"; } void MacroFusionPredicatorEmitter::emitPredicates( diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp index 271888ba26820..1aa20015549b1 100644 --- a/llvm/utils/TableGen/RegisterBankEmitter.cpp +++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp @@ -17,6 +17,7 @@ #include "llvm/ADT/BitVector.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" +#include "llvm/TableGen/CodeGenHelpers.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TGTimer.h" @@ -47,6 +48,7 @@ class RegisterBank { /// Get the human-readable name for the bank. StringRef getName() const { return TheDef.getValueAsString("Name"); } + /// Get the name of the enumerator in the ID enumeration. std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); @@ -110,11 +112,11 @@ class RegisterBankEmitter { const CodeGenTarget Target; const RecordKeeper &Records; - void emitHeader(raw_ostream &OS, const StringRef TargetName, + void emitHeader(raw_ostream &OS, StringRef TargetName, ArrayRef Banks); - void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName, + void emitBaseClassDefinition(raw_ostream &OS, StringRef TargetName, ArrayRef Banks); - void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName, + void emitBaseClassImplementation(raw_ostream &OS, StringRef TargetName, ArrayRef Banks); public: @@ -127,27 +129,27 @@ class RegisterBankEmitter { /// Emit code to declare the ID enumeration and external global instance /// variables. -void RegisterBankEmitter::emitHeader(raw_ostream &OS, - const StringRef TargetName, +void RegisterBankEmitter::emitHeader(raw_ostream &OS, StringRef TargetName, ArrayRef Banks) { + IfDefEmitter IfDef(OS, "GET_REGBANK_DECLARATIONS"); + NamespaceEmitter NS(OS, ("llvm::" + TargetName).str()); + // RegisterBankInfo.h - OS << "namespace llvm {\n" - << "namespace " << TargetName << " {\n" - << "enum : unsigned {\n"; + OS << "enum : unsigned {\n"; OS << " InvalidRegBankID = ~0u,\n"; unsigned ID = 0; for (const auto &Bank : Banks) OS << " " << Bank.getEnumeratorName() << " = " << ID++ << ",\n"; OS << " NumRegisterBanks,\n" - << "};\n" - << "} // end namespace " << TargetName << "\n" - << "} // end namespace llvm\n"; + << "};\n"; } /// Emit declarations of the GenRegisterBankInfo class. void RegisterBankEmitter::emitBaseClassDefinition( - raw_ostream &OS, const StringRef TargetName, ArrayRef Banks) { + raw_ostream &OS, StringRef TargetName, ArrayRef Banks) { + IfDefEmitter IfDef(OS, "GET_TARGET_REGBANK_CLASS"); + OS << "private:\n" << " static const RegisterBank *RegBanks[];\n" << " static const unsigned Sizes[];\n\n" @@ -221,44 +223,46 @@ void RegisterBankEmitter::emitBaseClassImplementation( const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); const CodeGenHwModes &CGH = Target.getHwModes(); - OS << "namespace llvm {\n" - << "namespace " << TargetName << " {\n"; - for (const auto &Bank : Banks) { - std::vector> RCsGroupedByWord( - (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); - - for (const auto &RC : Bank.register_classes()) - RCsGroupedByWord[RC->EnumValue / 32].push_back(RC); - - OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n"; - unsigned LowestIdxInWord = 0; - for (const auto &RCs : RCsGroupedByWord) { - OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) - << "\n"; - for (const auto &RC : RCs) { - OS << " (1u << (" << RC->getQualifiedIdName() << " - " - << LowestIdxInWord << ")) |\n"; + IfDefEmitter IfDef(OS, "GET_TARGET_REGBANK_IMPL"); + NamespaceEmitter LlvmNS(OS, "llvm"); + + { + NamespaceEmitter TargetNS(OS, TargetName); + for (const auto &Bank : Banks) { + std::vector> RCsGroupedByWord( + (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); + + for (const auto &RC : Bank.register_classes()) + RCsGroupedByWord[RC->EnumValue / 32].push_back(RC); + + OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n"; + unsigned LowestIdxInWord = 0; + for (const auto &RCs : RCsGroupedByWord) { + OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) + << "\n"; + for (const auto &RC : RCs) { + OS << " (1u << (" << RC->getQualifiedIdName() << " - " + << LowestIdxInWord << ")) |\n"; + } + OS << " 0,\n"; + LowestIdxInWord += 32; } - OS << " 0,\n"; - LowestIdxInWord += 32; + OS << "};\n"; } - OS << "};\n"; - } - OS << "\n"; + OS << "\n"; - for (const auto &Bank : Banks) { - std::string QualifiedBankID = - (TargetName + "::" + Bank.getEnumeratorName()).str(); - OS << "constexpr RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ " - << QualifiedBankID << ", /* Name */ \"" << Bank.getName() << "\", " - << "/* CoveredRegClasses */ " << Bank.getCoverageArrayName() - << ", /* NumRegClasses */ " - << RegisterClassHierarchy.getRegClasses().size() << ");\n"; - } - OS << "} // end namespace " << TargetName << "\n" - << "\n"; + for (const auto &Bank : Banks) { + std::string QualifiedBankID = + (TargetName + "::" + Bank.getEnumeratorName()).str(); + OS << "constexpr RegisterBank " << Bank.getInstanceVarName() + << "(/* ID */ " << QualifiedBankID << ", /* Name */ \"" + << Bank.getName() << "\", " << "/* CoveredRegClasses */ " + << Bank.getCoverageArrayName() << ", /* NumRegClasses */ " + << RegisterClassHierarchy.getRegClasses().size() << ");\n"; + } + } // End target namespace. - OS << "const RegisterBank *" << TargetName + OS << "\nconst RegisterBank *" << TargetName << "GenRegisterBankInfo::RegBanks[] = {\n"; for (const auto &Bank : Banks) OS << " &" << TargetName << "::" << Bank.getInstanceVarName() << ",\n"; @@ -322,7 +326,7 @@ void RegisterBankEmitter::emitBaseClassImplementation( E.RBIdName = "InvalidRegBankID"; } } - OS << "const RegisterBank &\n" + OS << "\nconst RegisterBank &\n" << TargetName << "GenRegisterBankInfo::getRegBankFromRegClass" "(const TargetRegisterClass &RC, LLT) const {\n"; @@ -377,8 +381,6 @@ void RegisterBankEmitter::emitBaseClassImplementation( "class ID " "0x\").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());\n" "}\n"; - - OS << "} // end namespace llvm\n"; } void RegisterBankEmitter::run(raw_ostream &OS) { @@ -424,18 +426,9 @@ void RegisterBankEmitter::run(raw_ostream &OS) { Timer.startTimer("Emit output"); emitSourceFileHeader("Register Bank Source Fragments", OS); - OS << "#ifdef GET_REGBANK_DECLARATIONS\n" - << "#undef GET_REGBANK_DECLARATIONS\n"; emitHeader(OS, TargetName, Banks); - OS << "#endif // GET_REGBANK_DECLARATIONS\n\n" - << "#ifdef GET_TARGET_REGBANK_CLASS\n" - << "#undef GET_TARGET_REGBANK_CLASS\n"; emitBaseClassDefinition(OS, TargetName, Banks); - OS << "#endif // GET_TARGET_REGBANK_CLASS\n\n" - << "#ifdef GET_TARGET_REGBANK_IMPL\n" - << "#undef GET_TARGET_REGBANK_IMPL\n"; emitBaseClassImplementation(OS, TargetName, Banks); - OS << "#endif // GET_TARGET_REGBANK_IMPL\n"; } static TableGen::Emitter::OptClass diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index 548c1503f4647..3da01d8a6b7aa 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -30,6 +30,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/Format.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/TableGen/CodeGenHelpers.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/SetTheory.h" @@ -102,10 +103,8 @@ class RegisterInfoEmitter { static void emitInclude(StringRef FilenamePrefix, StringRef IncludeFile, StringRef GuardMacro, raw_ostream &OS) { - OS << "#ifdef " << GuardMacro << '\n'; - OS << "#undef " << GuardMacro << '\n'; + IfDefEmitter IfDed(OS, GuardMacro); OS << "#include \"" << FilenamePrefix << IncludeFile << "\"\n"; - OS << "#endif\n\n"; } // runEnums - Print out enum values for all of the registers. @@ -122,41 +121,36 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, raw_ostream &MainOS, emitSourceFileHeader("Target Register Enum Values", OS); - OS << "namespace llvm {\n\n"; + NamespaceEmitter LlvmNS(OS, "llvm"); OS << "class MCRegisterClass;\n" << "extern const MCRegisterClass " << Target.getName() << "MCRegisterClasses[];\n\n"; - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; - OS << "enum : unsigned {\n NoRegister,\n"; + { + NamespaceEmitter RegNS(OS, Namespace); + OS << "enum : unsigned {\n NoRegister,\n"; - for (const auto &Reg : Registers) - OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; - assert(Registers.size() == Registers.back().EnumValue && - "Register enum value mismatch!"); - OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n"; - OS << "};\n"; - if (!Namespace.empty()) - OS << "} // end namespace " << Namespace << "\n"; + for (const auto &Reg : Registers) + OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; + assert(Registers.size() == Registers.back().EnumValue && + "Register enum value mismatch!"); + OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n"; + OS << "};\n"; + } const auto &RegisterClasses = RegBank.getRegClasses(); if (!RegisterClasses.empty()) { - // RegisterClass enums are stored as uint16_t in the tables. assert(RegisterClasses.size() <= 0xffff && "Too many register classes to fit in tables"); OS << "\n// Register classes\n\n"; - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; + NamespaceEmitter RegNS(OS, Namespace); OS << "enum {\n"; for (const auto &RC : RegisterClasses) OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; OS << "\n};\n"; - if (!Namespace.empty()) - OS << "} // end namespace " << Namespace << "\n\n"; } ArrayRef RegAltNameIndices = Target.getRegAltNameIndices(); @@ -164,47 +158,36 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, raw_ostream &MainOS, // emit anything. if (RegAltNameIndices.size() > 1) { OS << "\n// Register alternate name indices\n\n"; - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; + NamespaceEmitter RegNS(OS, Namespace); OS << "enum {\n"; for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; OS << "};\n"; - if (!Namespace.empty()) - OS << "} // end namespace " << Namespace << "\n\n"; } auto &SubRegIndices = RegBank.getSubRegIndices(); if (!SubRegIndices.empty()) { OS << "\n// Subregister indices\n\n"; - std::string Namespace = SubRegIndices.front().getNamespace(); - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; + NamespaceEmitter SubRegNS(OS, SubRegIndices.front().getNamespace()); OS << "enum : uint16_t {\n NoSubRegister,\n"; unsigned i = 0; for (const auto &Idx : SubRegIndices) OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; OS << " NUM_TARGET_SUBREGS\n};\n"; - if (!Namespace.empty()) - OS << "} // end namespace " << Namespace << "\n\n"; } - OS << "// Register pressure sets enum.\n"; - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; - OS << "enum RegisterPressureSets {\n"; - unsigned NumSets = RegBank.getNumRegPressureSets(); - for (unsigned i = 0; i < NumSets; ++i) { - const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); - OS << " " << RegUnits.Name << " = " << i << ",\n"; + { + OS << "// Register pressure sets enum.\n"; + NamespaceEmitter RegNS(OS, Namespace); + OS << "enum RegisterPressureSets {\n"; + unsigned NumSets = RegBank.getNumRegPressureSets(); + for (unsigned i = 0; i < NumSets; ++i) { + const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); + OS << " " << RegUnits.Name << " = " << i << ",\n"; + } + OS << "};\n"; } - OS << "};\n"; - if (!Namespace.empty()) - OS << "} // end namespace " << Namespace << '\n'; - OS << '\n'; - - OS << "} // end namespace llvm\n\n"; } static void printInt(raw_ostream &OS, int Val) { OS << Val; } @@ -982,7 +965,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS, LaneMaskSeqs.layout(); SubRegIdxSeqs.layout(); - OS << "namespace llvm {\n\n"; + NamespaceEmitter LlvmNS(OS, "llvm"); const std::string &TargetName = Target.getName().str(); @@ -1063,40 +1046,40 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS, const auto &RegisterClasses = RegBank.getRegClasses(); - // Loop over all of the register classes... emitting each one. - OS << "namespace { // Register classes...\n"; - SequenceToOffsetTable RegClassStrings; - // Emit the register enum value arrays for each RegisterClass - for (const auto &RC : RegisterClasses) { - ArrayRef Order = RC.getOrder(); - - // Give the register class a legal C name if it's anonymous. - const std::string &Name = RC.getName(); + // Loop over all of the register classes... emitting each one. + { + AnonNamespaceEmitter AnonNS(OS); + OS << "// Register classes...\n"; - RegClassStrings.add(Name); + // Emit the register enum value arrays for each RegisterClass + for (const auto &RC : RegisterClasses) { + ArrayRef Order = RC.getOrder(); - // Emit the register list now (unless it would be a zero-length array). - if (!Order.empty()) { - OS << " // " << Name << " Register Class...\n" - << " const MCPhysReg " << Name << "[] = {\n "; - for (const Record *Reg : Order) { - OS << getQualifiedName(Reg) << ", "; - } - OS << "\n };\n\n"; + // Give the register class a legal C name if it's anonymous. + const std::string &Name = RC.getName(); - OS << " // " << Name << " Bit set.\n" - << " const uint8_t " << Name << "Bits[] = {\n "; - BitVectorEmitter BVE; - for (const Record *Reg : Order) { - BVE.add(RegBank.getReg(Reg)->EnumValue); + RegClassStrings.add(Name); + + // Emit the register list now (unless it would be a zero-length array). + if (!Order.empty()) { + OS << " // " << Name << " Register Class...\n" + << " const MCPhysReg " << Name << "[] = {\n "; + for (const Record *Reg : Order) + OS << getQualifiedName(Reg) << ", "; + OS << "\n };\n\n"; + + OS << " // " << Name << " Bit set.\n" + << " const uint8_t " << Name << "Bits[] = {\n "; + BitVectorEmitter BVE; + for (const Record *Reg : Order) + BVE.add(RegBank.getReg(Reg)->EnumValue); + BVE.print(OS); + OS << "\n };\n\n"; } - BVE.print(OS); - OS << "\n };\n\n"; } } - OS << "} // end anonymous namespace\n\n"; RegClassStrings.layout(); RegClassStrings.emitStringLiteralDef( @@ -1155,8 +1138,6 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS, EmitRegMapping(OS, Regs, false); OS << "}\n\n"; - - OS << "} // end namespace llvm\n\n"; } void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS, @@ -1170,7 +1151,7 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS, OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; - OS << "namespace llvm {\n\n"; + NamespaceEmitter LlvmNS(OS, "llvm"); OS << "class " << TargetName << "FrameLowering;\n\n"; @@ -1228,18 +1209,15 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS, OS << "};\n\n"; if (!RegisterClasses.empty()) { - OS << "namespace " << RegisterClasses.front().Namespace - << " { // Register classes\n"; + NamespaceEmitter RegClassNS(OS, RegisterClasses.front().Namespace); + OS << "// Register classes\n"; for (const auto &RC : RegisterClasses) { - const std::string &Name = RC.getName(); - // Output the extern for the instance. - OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; + OS << " extern const TargetRegisterClass " << RC.getName() + << "RegClass;\n"; } - OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; } - OS << "} // end namespace llvm\n\n"; } // @@ -1252,7 +1230,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS, emitSourceFileHeader("Target Register and Register Classes Information", OS); - OS << "namespace llvm {\n\n"; + NamespaceEmitter LlvmNS(OS, "llvm"); // Get access to MCRegisterClass data. OS << "extern const MCRegisterClass " << Target.getName() @@ -1453,8 +1431,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS, } // Now emit the actual value-initialized register class instances. - OS << "\nnamespace " << RegisterClasses.front().Namespace - << " { // Register class instances\n"; + NamespaceEmitter RegClassNS(OS, RegisterClasses.front().Namespace); + OS << "// Register class instances\n"; for (const auto &RC : RegisterClasses) { OS << " extern const TargetRegisterClass " << RC.getName() @@ -1481,16 +1459,15 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS, OS << RC.getName() << "GetRawAllocationOrder\n"; OS << " };\n\n"; } - - OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; } - OS << "\nnamespace {\n"; - OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; - for (const auto &RC : RegisterClasses) - OS << " &" << RC.getQualifiedName() << "RegClass,\n"; - OS << " };\n"; - OS << "} // end anonymous namespace\n"; + { + AnonNamespaceEmitter AnonNS(OS); + OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; + for (const auto &RC : RegisterClasses) + OS << " &" << RC.getQualifiedName() << "RegClass,\n"; + OS << " };\n"; + } // Emit extra information about registers. const std::string &TargetName = Target.getName().str(); @@ -1862,8 +1839,6 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS, << " return static_cast(\n" << " MF.getSubtarget().getFrameLowering());\n" << "}\n\n"; - - OS << "} // end namespace llvm\n\n"; } TableGenOutputFiles RegisterInfoEmitter::run(StringRef FilenamePrefix) { diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp index 0dc8c92a5a37a..88aa6bf8e9242 100644 --- a/llvm/utils/TableGen/SearchableTableEmitter.cpp +++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp @@ -430,10 +430,9 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table, std::string LastRepr = primaryRepresentation( Index.Loc, Field, IndexRows.back()->getValueInit(Field.Name)); std::string TS = - '(' + searchableFieldType(Table, Index, Field, TypeInStaticStruct) + - ')'; - OS << " if (" << TS << Field.Name << " != std::clamp(" << TS << Field.Name - << ", " << TS << FirstRepr << ", " << TS << LastRepr << "))\n"; + searchableFieldType(Table, Index, Field, TypeInStaticStruct); + OS << " if ((" << TS << ")" << Field.Name << " != std::clamp<" << TS + << ">(" << Field.Name << ", " << FirstRepr << ", " << LastRepr << "))\n"; OS << " return nullptr;\n\n"; if (IsContiguous && !Index.EarlyOut) { diff --git a/llvm/utils/TableGen/X86MnemonicTables.cpp b/llvm/utils/TableGen/X86MnemonicTables.cpp index 7851919bd7387..b9c40659a07fe 100644 --- a/llvm/utils/TableGen/X86MnemonicTables.cpp +++ b/llvm/utils/TableGen/X86MnemonicTables.cpp @@ -14,6 +14,7 @@ #include "Common/CodeGenInstruction.h" #include "Common/CodeGenTarget.h" #include "X86RecognizableInstr.h" +#include "llvm/TableGen/CodeGenHelpers.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" @@ -34,11 +35,10 @@ class X86MnemonicTablesEmitter { void X86MnemonicTablesEmitter::run(raw_ostream &OS) { emitSourceFileHeader("X86 Mnemonic tables", OS); - OS << "namespace llvm {\nnamespace X86 {\n\n"; const Record *AsmWriter = Target.getAsmWriter(); unsigned Variant = AsmWriter->getValueAsInt("Variant"); - // Hold all instructions grouped by mnemonic + // Hold all instructions grouped by mnemonic. StringMap> MnemonicToCGInstrMap; for (const CodeGenInstruction *I : Target.getInstructions()) { @@ -49,39 +49,39 @@ void X86MnemonicTablesEmitter::run(raw_ostream &OS) { X86Disassembler::RecognizableInstrBase RI(*I); if (!RI.shouldBeEmitted()) continue; - if ( // Non-parsable instruction defs contain prefix as part of AsmString + if ( // Non-parsable instruction defs contain prefix as part of AsmString. Def->getValueAsString("AsmVariantName") == "NonParsable" || - // Skip prefix byte + // Skip prefix byte. RI.Form == X86Local::PrefixByte) continue; std::string Mnemonic = X86Disassembler::getMnemonic(I, Variant); MnemonicToCGInstrMap[Mnemonic].push_back(I); } - OS << "#ifdef GET_X86_MNEMONIC_TABLES_H\n"; - OS << "#undef GET_X86_MNEMONIC_TABLES_H\n\n"; - for (StringRef Mnemonic : MnemonicToCGInstrMap.keys()) - OS << "bool is" << Mnemonic << "(unsigned Opcode);\n"; - OS << "#endif // GET_X86_MNEMONIC_TABLES_H\n\n"; + { + IfDefEmitter IfDef(OS, "GET_X86_MNEMONIC_TABLES_H"); + NamespaceEmitter NS(OS, "llvm::X86"); + for (StringRef Mnemonic : MnemonicToCGInstrMap.keys()) + OS << "bool is" << Mnemonic << "(unsigned Opcode);\n"; + } - OS << "#ifdef GET_X86_MNEMONIC_TABLES_CPP\n"; - OS << "#undef GET_X86_MNEMONIC_TABLES_CPP\n\n"; - for (StringRef Mnemonic : MnemonicToCGInstrMap.keys()) { - OS << "bool is" << Mnemonic << "(unsigned Opcode) {\n"; - auto Mnemonics = MnemonicToCGInstrMap[Mnemonic]; - if (Mnemonics.size() == 1) { - const CodeGenInstruction *CGI = *Mnemonics.begin(); - OS << "\treturn Opcode == " << CGI->getName() << ";\n}\n\n"; - } else { - OS << "\tswitch (Opcode) {\n"; - for (const CodeGenInstruction *CGI : Mnemonics) { - OS << "\tcase " << CGI->getName() << ":\n"; + { + IfDefEmitter IfDef(OS, "GET_X86_MNEMONIC_TABLES_CPP"); + NamespaceEmitter NS(OS, "llvm::X86"); + for (StringRef Mnemonic : MnemonicToCGInstrMap.keys()) { + OS << "bool is" << Mnemonic << "(unsigned Opcode) {\n"; + const auto &Mnemonics = MnemonicToCGInstrMap[Mnemonic]; + if (Mnemonics.size() == 1) { + const CodeGenInstruction *CGI = Mnemonics.front(); + OS << " return Opcode == " << CGI->getName() << ";\n}\n\n"; + } else { + OS << " switch (Opcode) {\n"; + for (const CodeGenInstruction *CGI : Mnemonics) + OS << " case " << CGI->getName() << ":\n"; + OS << " return true;\n }\n return false;\n}\n\n"; } - OS << "\t\treturn true;\n\t}\n\treturn false;\n}\n\n"; } } - OS << "#endif // GET_X86_MNEMONIC_TABLES_CPP\n\n"; - OS << "} // end namespace X86\n} // end namespace llvm"; } static TableGen::Emitter::OptClass diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py index cd15994326f98..9cca0a7ad5d38 100644 --- a/llvm/utils/UpdateTestChecks/common.py +++ b/llvm/utils/UpdateTestChecks/common.py @@ -1184,6 +1184,7 @@ def get_ir_regex(self): # Create a FileCheck variable name based on an IR name. def get_value_name(self, var: str, check_prefix: str): var = var.replace("!", "") + var = var.replace("%", "") if self.replace_number_with_counter: assert var replacement = self.variable_mapping.get(var, None) @@ -1412,15 +1413,23 @@ def make_analyze_generalizer(version): NamelessValue( r"GRP", "#", - r"", + r"group", r"0x[0-9a-f]+", None, replace_number_with_counter=True, ), + NamelessValue( + r"VP", + r"vp", + r"vp<", + r"%[0-9]+", + None, + ir_suffix=r">", + ), ] prefix = r"(\s*)" - suffix = r"(\)?:)" + suffix = r"([,\s\(\)\}\]:]|\Z)" return GeneralizerInfo( version, GeneralizerInfo.MODE_ANALYZE, values, prefix, suffix @@ -2268,7 +2277,9 @@ def add_checks( "{} {}-EMPTY:".format(comment_marker, checkprefix) ) else: - check_suffix = "-NEXT" if not is_filtered else "" + # TODO: Remove once only -vplan-print-after is supported. + check_next = not is_filtered and "VPlan" not in func_line + check_suffix = "-NEXT" if check_next else "" output_lines.append( "{} {}{}: {}".format( comment_marker, checkprefix, check_suffix, func_line diff --git a/llvm/utils/git/code-format-helper.py b/llvm/utils/git/code-format-helper.py index f6b28f480b8a2..1e8c332554a8e 100755 --- a/llvm/utils/git/code-format-helper.py +++ b/llvm/utils/git/code-format-helper.py @@ -124,7 +124,7 @@ def update_pr(self, comment_text: str, args: FormatArgs, create_new: bool) -> No import github from github import IssueComment, PullRequest - repo = github.Github(args.token).get_repo(args.repo) + repo = github.Github(auth=github.Auth.Token(args.token)).get_repo(args.repo) pr = repo.get_issue(args.issue_number).as_pull_request() comment_text = self.comment_tag + "\n\n" + comment_text diff --git a/llvm/utils/git/code-lint-helper.py b/llvm/utils/git/code-lint-helper.py index 6f2afc9b2ad06..954ed45713ade 100644 --- a/llvm/utils/git/code-lint-helper.py +++ b/llvm/utils/git/code-lint-helper.py @@ -111,7 +111,7 @@ def find_comment(self, pr: Any) -> Any: def update_pr(self, comment_text: str, args: LintArgs, create_new: bool) -> None: assert args.repo is not None - repo = github.Github(args.token).get_repo(args.repo) + repo = github.Github(auth=github.Auth.Token(args.token)).get_repo(args.repo) pr = repo.get_issue(args.issue_number).as_pull_request() comment_text = f"{self.comment_tag}\n\n{comment_text}" diff --git a/llvm/utils/git/github-automation.py b/llvm/utils/git/github-automation.py index b766aa505a62e..6414a073d9c4b 100755 --- a/llvm/utils/git/github-automation.py +++ b/llvm/utils/git/github-automation.py @@ -66,8 +66,10 @@ def team_name(self) -> str: return self._team_name def __init__(self, token: str, repo: str, issue_number: int, label_name: str): - self.repo = github.Github(token).get_repo(repo) - self.org = github.Github(token).get_organization(self.repo.organization.login) + self.repo = github.Github(auth=github.Auth.Token(token)).get_repo(repo) + self.org = github.Github(auth=github.Auth.Token(token)).get_organization( + self.repo.organization.login + ) self.issue = self.repo.get_issue(issue_number) self._team_name = "issue-subscribers-{}".format(label_name).lower() @@ -111,8 +113,10 @@ def team_name(self) -> str: return self._team_name def __init__(self, token: str, repo: str, pr_number: int, label_name: str): - self.repo = github.Github(token).get_repo(repo) - self.org = github.Github(token).get_organization(self.repo.organization.login) + self.repo = github.Github(auth=github.Auth.Token(token)).get_repo(repo) + self.org = github.Github(auth=github.Auth.Token(token)).get_organization( + self.repo.organization.login + ) self.pr = self.repo.get_issue(pr_number).as_pull_request() self._team_name = "pr-subscribers-{}".format( label_name.replace("+", "x") @@ -230,7 +234,7 @@ class PRGreeter: COMMENT_TAG = "\n" def __init__(self, token: str, repo: str, pr_number: int): - repo = github.Github(token).get_repo(repo) + repo = github.Github(auth=github.Auth.Token(token)).get_repo(repo) self.pr = repo.get_issue(pr_number).as_pull_request() def run(self) -> bool: @@ -260,7 +264,7 @@ def run(self) -> bool: class CommitRequestGreeter: def __init__(self, token: str, repo: str, issue_number: int): - self.repo = github.Github(token).get_repo(repo) + self.repo = github.Github(auth=github.Auth.Token(token)).get_repo(repo) self.issue = self.repo.get_issue(issue_number) def run(self) -> bool: @@ -323,7 +327,7 @@ class PRBuildbotInformation: COMMENT_TAG = "\n" def __init__(self, token: str, repo: str, pr_number: int, author: str): - repo = github.Github(token).get_repo(repo) + repo = github.Github(auth=github.Auth.Token(token)).get_repo(repo) self.pr = repo.get_issue(pr_number).as_pull_request() self.author = author @@ -460,7 +464,9 @@ def requested_by(self) -> str: @property def repo(self) -> github.Repository.Repository: - return github.Github(self.token).get_repo(self.repo_name) + return github.Github(auth=github.Auth.Token(self.token)).get_repo( + self.repo_name + ) @property def issue(self) -> github.Issue.Issue: @@ -725,7 +731,9 @@ def create_pull_request( https://docs.github.com/en/get-started/quickstart/github-glossary#base-branch https://docs.github.com/en/get-started/quickstart/github-glossary#compare-branch """ - repo = github.Github(self.token).get_repo(self.repo_name) + repo = github.Github(auth=github.Auth.Token(self.token)).get_repo( + self.repo_name + ) issue_ref = "{}#{}".format(self.repo_name, self.issue_number) pull = None release_branch_for_issue = self.release_branch_for_issue @@ -800,7 +808,7 @@ def execute_command(self) -> bool: def request_release_note(token: str, repo_name: str, pr_number: int): - repo = github.Github(token).get_repo(repo_name) + repo = github.Github(auth=github.Auth.Token(token)).get_repo(repo_name) pr = repo.get_issue(pr_number).as_pull_request() submitter = pr.user.login if submitter == "llvmbot": diff --git a/llvm/utils/git/requirements.txt b/llvm/utils/git/requirements.txt index 51c489ad7abfa..80b47c7ce4de3 100644 --- a/llvm/utils/git/requirements.txt +++ b/llvm/utils/git/requirements.txt @@ -1,5 +1,5 @@ # -# This file is autogenerated by pip-compile with Python 3.14 +# This file is autogenerated by pip-compile with Python 3.13 # by the following command: # # pip-compile --generate-hashes --output-file=requirements.txt requirements.txt.in @@ -10,74 +10,91 @@ certifi==2024.8.30 \ # via # -r requirements.txt.in # requests -cffi==1.17.1 \ - --hash=sha256:045d61c734659cc045141be4bae381a41d89b741f795af1dd018bfb532fd0df8 \ - --hash=sha256:0984a4925a435b1da406122d4d7968dd861c1385afe3b45ba82b750f229811e2 \ - --hash=sha256:0e2b1fac190ae3ebfe37b979cc1ce69c81f4e4fe5746bb401dca63a9062cdaf1 \ - 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--hash=sha256:5fed36fccc0612a53f1d4d9a816b50a36702c28a2aa880cb8a122b3466638743 \ + --hash=sha256:61d028e90346df14fedc3d1e5441df818d095f3b87d286825dfcbd6459b7ef63 \ + --hash=sha256:66f011380d0e49ed280c789fbd08ff0d40968ee7b665575489afa95c98196ab5 \ + --hash=sha256:6824f87845e3396029f3820c206e459ccc91760e8fa24422f8b0c3d1731cbec5 \ + --hash=sha256:6c6c373cfc5c83a975506110d17457138c8c63016b563cc9ed6e056a82f13ce4 \ + --hash=sha256:6d02d6655b0e54f54c4ef0b94eb6be0607b70853c45ce98bd278dc7de718be5d \ + --hash=sha256:6d50360be4546678fc1b79ffe7a66265e28667840010348dd69a314145807a1b \ + --hash=sha256:730cacb21e1bdff3ce90babf007d0a0917cc3e6492f336c2f0134101e0944f93 \ + --hash=sha256:737fe7d37e1a1bffe70bd5754ea763a62a066dc5913ca57e957824b72a85e205 \ + --hash=sha256:74a03b9698e198d47562765773b4a8309919089150a0bb17d829ad7b44b60d27 \ + --hash=sha256:7553fb2090d71822f02c629afe6042c299edf91ba1bf94951165613553984512 \ + --hash=sha256:7a66c7204d8869299919db4d5069a82f1561581af12b11b3c9f48c584eb8743d \ + --hash=sha256:7cc09976e8b56f8cebd752f7113ad07752461f48a58cbba644139015ac24954c \ + --hash=sha256:81afed14892743bbe14dacb9e36d9e0e504cd204e0b165062c488942b9718037 \ + --hash=sha256:8941aaadaf67246224cee8c3803777eed332a19d909b47e29c9842ef1e79ac26 \ + --hash=sha256:89472c9762729b5ae1ad974b777416bfda4ac5642423fa93bd57a09204712322 \ + --hash=sha256:8ea985900c5c95ce9db1745f7933eeef5d314f0565b27625d9a10ec9881e1bfb \ + --hash=sha256:8eca2a813c1cb7ad4fb74d368c2ffbbb4789d377ee5bb8df98373c2cc0dee76c \ + --hash=sha256:92b68146a71df78564e4ef48af17551a5ddd142e5190cdf2c5624d0c3ff5b2e8 \ + --hash=sha256:9332088d75dc3241c702d852d4671613136d90fa6881da7d770a483fd05248b4 \ + --hash=sha256:94698a9c5f91f9d138526b48fe26a199609544591f859c870d477351dc7b2414 \ + --hash=sha256:9a67fc9e8eb39039280526379fb3a70023d77caec1852002b4da7e8b270c4dd9 \ + --hash=sha256:9de40a7b0323d889cf8d23d1ef214f565ab154443c42737dfe52ff82cf857664 \ + --hash=sha256:a05d0c237b3349096d3981b727493e22147f934b20f6f125a3eba8f994bec4a9 \ + --hash=sha256:afb8db5439b81cf9c9d0c80404b60c3cc9c3add93e114dcae767f1477cb53775 \ + --hash=sha256:b18a3ed7d5b3bd8d9ef7a8cb226502c6bf8308df1525e1cc676c3680e7176739 \ + --hash=sha256:b1e74d11748e7e98e2f426ab176d4ed720a64412b6a15054378afdb71e0f37dc \ + --hash=sha256:b21e08af67b8a103c71a250401c78d5e0893beff75e28c53c98f4de42f774062 \ + --hash=sha256:b4c854ef3adc177950a8dfc81a86f5115d2abd545751a304c5bcf2c2c7283cfe \ + --hash=sha256:b882b3df248017dba09d6b16defe9b5c407fe32fc7c65a9c69798e6175601be9 \ + --hash=sha256:baf5215e0ab74c16e2dd324e8ec067ef59e41125d3eade2b863d294fd5035c92 \ + --hash=sha256:c649e3a33450ec82378822b3dad03cc228b8f5963c0c12fc3b1e0ab940f768a5 \ + --hash=sha256:c654de545946e0db659b3400168c9ad31b5d29593291482c43e3564effbcee13 \ + --hash=sha256:c6638687455baf640e37344fe26d37c404db8b80d037c3d29f58fe8d1c3b194d \ + --hash=sha256:c8d3b5532fc71b7a77c09192b4a5a200ea992702734a2e9279a37f2478236f26 \ + --hash=sha256:cb527a79772e5ef98fb1d700678fe031e353e765d1ca2d409c92263c6d43e09f \ + --hash=sha256:cf364028c016c03078a23b503f02058f1814320a56ad535686f90565636a9495 \ + --hash=sha256:d48a880098c96020b02d5a1f7d9251308510ce8858940e6fa99ece33f610838b \ + --hash=sha256:d68b6cef7827e8641e8ef16f4494edda8b36104d79773a334beaa1e3521430f6 \ + --hash=sha256:d9b29c1f0ae438d5ee9acb31cadee00a58c46cc9c0b2f9038c6b0b3470877a8c \ + --hash=sha256:d9b97165e8aed9272a6bb17c01e3cc5871a594a446ebedc996e2397a1c1ea8ef \ + --hash=sha256:da68248800ad6320861f129cd9c1bf96ca849a2771a59e0344e88681905916f5 \ + --hash=sha256:da902562c3e9c550df360bfa53c035b2f241fed6d9aef119048073680ace4a18 \ + --hash=sha256:dbd5c7a25a7cb98f5ca55d258b103a2054f859a46ae11aaf23134f9cc0d356ad \ + --hash=sha256:dd4f05f54a52fb558f1ba9f528228066954fee3ebe629fc1660d874d040ae5a3 \ + --hash=sha256:de8dad4425a6ca6e4e5e297b27b5c824ecc7581910bf9aee86cb6835e6812aa7 \ + --hash=sha256:e11e82b744887154b182fd3e7e8512418446501191994dbf9c9fc1f32cc8efd5 \ + --hash=sha256:e6e73b9e02893c764e7e8d5bb5ce277f1a009cd5243f8228f75f842bf937c534 \ + --hash=sha256:f73b96c41e3b2adedc34a7356e64c8eb96e03a3782b535e043a986276ce12a49 \ + --hash=sha256:f93fd8e5c8c0a4aa1f424d6173f14a892044054871c771f8566e4008eaa359d2 \ + --hash=sha256:fc33c5141b55ed366cfaad382df24fe7dcbc686de5be719b207bb248e3053dc5 \ + --hash=sha256:fc7de24befaeae77ba923797c7c87834c73648a05a4bde34b3b7e5588973a453 \ + --hash=sha256:fe562eb1a64e67dd297ccc4f5addea2501664954f2692b69a76449ec7913ecbf # via # cryptography # pynacl @@ -234,18 +251,35 @@ pyjwt[crypto]==2.9.0 \ --hash=sha256:3b02fb0f44517787776cf48f2ae25d8e14f300e6d7545a4315cee571a415e850 \ --hash=sha256:7e1e5b56cc735432a7369cbfa0efe50fa113ebecdc04ae6922deba8b84582d0c # via pygithub -pynacl==1.5.0 \ - --hash=sha256:06b8f6fa7f5de8d5d2f7573fe8c863c051225a27b61e6860fd047b1775807858 \ - --hash=sha256:0c84947a22519e013607c9be43706dd42513f9e6ae5d39d3613ca1e142fba44d \ - --hash=sha256:20f42270d27e1b6a29f54032090b972d97f0a1b0948cc52392041ef7831fee93 \ - --hash=sha256:401002a4aaa07c9414132aaed7f6836ff98f59277a234704ff66878c2ee4a0d1 \ - --hash=sha256:52cb72a79269189d4e0dc537556f4740f7f0a9ec41c1322598799b0bdad4ef92 \ - --hash=sha256:61f642bf2378713e2c2e1de73444a3778e5f0a38be6fee0fe532fe30060282ff \ - --hash=sha256:8ac7448f09ab85811607bdd21ec2464495ac8b7c66d146bf545b0f08fb9220ba \ - --hash=sha256:a36d4a9dda1f19ce6e03c9a784a2921a4b726b02e1c736600ca9c22029474394 \ - --hash=sha256:a422368fc821589c228f4c49438a368831cb5bbc0eab5ebe1d7fac9dded6567b \ - --hash=sha256:e46dae94e34b085175f8abb3b0aaa7da40767865ac82c928eeb9e57e1ea8a543 - # via pygithub +pynacl==1.6.2 \ + --hash=sha256:018494d6d696ae03c7e656e5e74cdfd8ea1326962cc401bcf018f1ed8436811c \ + --hash=sha256:04316d1fc625d860b6c162fff704eb8426b1a8bcd3abacea11142cbd99a6b574 \ + --hash=sha256:22de65bb9010a725b0dac248f353bb072969c94fa8d6b1f34b87d7953cf7bbe4 \ + --hash=sha256:26bfcd00dcf2cf160f122186af731ae30ab120c18e8375684ec2670dccd28130 \ + --hash=sha256:2fef529ef3ee487ad8113d287a593fa26f48ee3620d92ecc6f1d09ea38e0709b \ + --hash=sha256:320ef68a41c87547c91a8b58903c9caa641ab01e8512ce291085b5fe2fcb7590 \ + --hash=sha256:3bffb6d0f6becacb6526f8f42adfb5efb26337056ee0831fb9a7044d1a964444 \ + --hash=sha256:44081faff368d6c5553ccf55322ef2819abb40e25afaec7e740f159f74813634 \ + --hash=sha256:46065496ab748469cdd999246d17e301b2c24ae2fdf739132e580a0e94c94a87 \ + --hash=sha256:5811c72b473b2f38f7e2a3dc4f8642e3a3e9b5e7317266e4ced1fba85cae41aa \ + --hash=sha256:622d7b07cc5c02c666795792931b50c91f3ce3c2649762efb1ef0d5684c81594 \ + --hash=sha256:62985f233210dee6548c223301b6c25440852e13d59a8b81490203c3227c5ba0 \ + --hash=sha256:68be3a09455743ff9505491220b64440ced8973fe930f270c8e07ccfa25b1f9e \ + --hash=sha256:834a43af110f743a754448463e8fd61259cd4ab5bbedcf70f9dabad1d28a394c \ + --hash=sha256:8845c0631c0be43abdd865511c41eab235e0be69c81dc66a50911594198679b0 \ + --hash=sha256:8a66d6fb6ae7661c58995f9c6435bda2b1e68b54b598a6a10247bfcdadac996c \ + --hash=sha256:8b097553b380236d51ed11356c953bf8ce36a29a3e596e934ecabe76c985a577 \ + --hash=sha256:a84bf1c20339d06dc0c85d9aea9637a24f718f375d861b2668b2f9f96fa51145 \ + --hash=sha256:a9f9932d8d2811ce1a8ffa79dcbdf3970e7355b5c8eb0c1a881a57e7f7d96e88 \ + --hash=sha256:bc4a36b28dd72fb4845e5d8f9760610588a96d5a51f01d84d8c6ff9849968c14 \ + --hash=sha256:c8a231e36ec2cab018c4ad4358c386e36eede0319a0c41fed24f840b1dac59f6 \ + --hash=sha256:c949ea47e4206af7c8f604b8278093b674f7c79ed0d4719cc836902bf4517465 \ + --hash=sha256:d071c6a9a4c94d79eb665db4ce5cedc537faf74f2355e4d502591d850d3913c0 \ + --hash=sha256:d29bfe37e20e015a7d8b23cfc8bd6aa7909c92a1b8f41ee416bbb3e79ef182b2 \ + --hash=sha256:fe9847ca47d287af41e82be1dd5e23023d3c31a951da134121ab02e42ac218c9 + # via + # -r requirements.txt.in + # pygithub requests==2.32.3 \ --hash=sha256:55365417734eb18255590a9ff9eb97e9e1da868d4ccd6402399eaf68af20a760 \ --hash=sha256:70761cfe03c773ceb22aa2f671b4757976145175cdfca038c02654d061d6dcc6 diff --git a/llvm/utils/git/requirements.txt.in b/llvm/utils/git/requirements.txt.in index dfd6d0637a545..c62e6a0d11b0d 100644 --- a/llvm/utils/git/requirements.txt.in +++ b/llvm/utils/git/requirements.txt.in @@ -10,3 +10,4 @@ PyGithub==2.4.0 # >=1.59.1 For WorkflowRun.name # (variables in graphql query). GitPython>=3.1.32 # https://security.snyk.io/vuln/SNYK-PYTHON-GITPYTHON-5840584 lit>=18.1.8 # No entry on snyk as of 2026-12-01 +pynacl>=1.6.2 # I had trouble installing 1.5.0 on ARM Windows. diff --git a/llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn index 9b0618ded23a1..a893296f1f64f 100644 --- a/llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn @@ -15,6 +15,7 @@ static_library("Analysis") { "AnnexKDetection.cpp", "BodyFarm.cpp", "CFG.cpp", + "CFGBackEdges.cpp", "CFGReachabilityAnalysis.cpp", "CFGStmtMap.cpp", "CallGraph.cpp", diff --git a/llvm/utils/gn/secondary/clang/lib/Analysis/LifetimeSafety/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Analysis/LifetimeSafety/BUILD.gn index 0fe700ece87f3..3d38faec399cb 100644 --- a/llvm/utils/gn/secondary/clang/lib/Analysis/LifetimeSafety/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Analysis/LifetimeSafety/BUILD.gn @@ -16,6 +16,7 @@ static_library("LifetimeSafety") { "LiveOrigins.cpp", "LoanPropagation.cpp", "Loans.cpp", + "MovedLoans.cpp", "Origins.cpp", ] } diff --git a/llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn index f9c72a5909654..6cee87e919bcc 100644 --- a/llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn @@ -16,6 +16,7 @@ static_library("Scalable") { "Model/EntityIdTable.cpp", "Model/EntityName.cpp", "Serialization/SerializationFormat.cpp", + "Serialization/SerializationFormatRegistry.cpp", "TUSummary/ExtractorRegistry.cpp", ] } diff --git a/llvm/utils/gn/secondary/clang/lib/Parse/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Parse/BUILD.gn index 370a7ce92f090..f96e7ea429cf5 100644 --- a/llvm/utils/gn/secondary/clang/lib/Parse/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Parse/BUILD.gn @@ -28,6 +28,7 @@ static_library("Parse") { "ParseOpenACC.cpp", "ParseOpenMP.cpp", "ParsePragma.cpp", + "ParseReflect.cpp", "ParseStmt.cpp", "ParseStmtAsm.cpp", "ParseTemplate.cpp", diff --git a/llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn index e2a5955f2267e..3464c524190fa 100644 --- a/llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/StaticAnalyzer/Checkers/BUILD.gn @@ -95,6 +95,7 @@ static_library("Checkers") { "ObjCSelfInitChecker.cpp", "ObjCSuperDeallocChecker.cpp", "ObjCUnusedIVarsChecker.cpp", + "OpaqueSTLFunctionsModeling.cpp", "PaddingChecker.cpp", "PointerArithChecker.cpp", "PointerSubChecker.cpp", diff --git a/llvm/utils/gn/secondary/clang/unittests/Analysis/BUILD.gn b/llvm/utils/gn/secondary/clang/unittests/Analysis/BUILD.gn index ac2ce0c59c6b3..4bf4cddf98f36 100644 --- a/llvm/utils/gn/secondary/clang/unittests/Analysis/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/unittests/Analysis/BUILD.gn @@ -13,6 +13,7 @@ unittest("ClangAnalysisTests") { "//llvm/lib/Support", ] sources = [ + "CFGBackEdgesTest.cpp", "CFGDominatorTree.cpp", "CFGTest.cpp", "CloneDetectionTest.cpp", diff --git a/llvm/utils/gn/secondary/clang/unittests/Analysis/Scalable/BUILD.gn b/llvm/utils/gn/secondary/clang/unittests/Analysis/Scalable/BUILD.gn index 29684803144b4..703c5ca25d603 100644 --- a/llvm/utils/gn/secondary/clang/unittests/Analysis/Scalable/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/unittests/Analysis/Scalable/BUILD.gn @@ -11,14 +11,18 @@ unittest("ClangScalableAnalysisTests") { "//clang/lib/Tooling", "//llvm/lib/Support", ] + include_dirs = [ "." ] sources = [ "ASTEntityMappingTest.cpp", "BuildNamespaceTest.cpp", "EntityIdTableTest.cpp", "EntityIdTest.cpp", "EntityNameTest.cpp", + "Registries/FancyAnalysisData.cpp", + "Registries/MockSerializationFormat.cpp", "Registries/MockSummaryExtractor1.cpp", "Registries/MockSummaryExtractor2.cpp", + "Registries/SerializationFormatRegistryTest.cpp", "Registries/SummaryExtractorRegistryTest.cpp", "SummaryNameTest.cpp", ] diff --git a/llvm/utils/gn/secondary/compiler-rt/gen_dynamic_list.gni b/llvm/utils/gn/secondary/compiler-rt/gen_dynamic_list.gni new file mode 100644 index 0000000000000..c134400108434 --- /dev/null +++ b/llvm/utils/gn/secondary/compiler-rt/gen_dynamic_list.gni @@ -0,0 +1,40 @@ +import("//compiler-rt/target.gni") + +template("gen_dynamic_list") { + if (current_os != "mac" && current_os != "win") { + lib_path = "$crt_current_out_dir/libclang_rt.${invoker.lib_name}$crt_current_target_suffix.a" + nm = "//llvm/tools/llvm-nm($host_toolchain)" + action(target_name) { + script = "//compiler-rt/lib/sanitizer_common/scripts/gen_dynamic_list.py" + deps = [ + invoker.lib, + nm, + ] + outputs = [ "$lib_path.syms" ] + args = [ rebase_path(lib_path, root_build_dir) ] + args += [ + "--nm-executable", + rebase_path(get_label_info(nm, "root_out_dir") + "/bin/llvm-nm", + root_build_dir), + "-o", + rebase_path("$lib_path.syms", root_build_dir), + ] + if (defined(invoker.extra)) { + sources = [ invoker.extra ] + args += [ + "--extra", + rebase_path(invoker.extra, root_build_dir), + ] + } + } + } else { + source_set(target_name) { + } + not_needed(invoker, + [ + "extra", + "lib_name", + "lib", + ]) + } +} diff --git a/llvm/utils/gn/secondary/compiler-rt/gen_version_script.gni b/llvm/utils/gn/secondary/compiler-rt/gen_version_script.gni index e981c8bdf4a5d..22dab72d302c1 100644 --- a/llvm/utils/gn/secondary/compiler-rt/gen_version_script.gni +++ b/llvm/utils/gn/secondary/compiler-rt/gen_version_script.gni @@ -2,6 +2,7 @@ import("//compiler-rt/target.gni") template("gen_version_script") { if (current_os != "mac" && current_os != "win") { + nm = "//llvm/tools/llvm-nm($host_toolchain)" action(target_name) { script = "//compiler-rt/lib/sanitizer_common/scripts/gen_dynamic_list.py" sources = [ invoker.extra ] @@ -19,7 +20,8 @@ template("gen_version_script") { } args += [ "--nm-executable", - "nm", + rebase_path(get_label_info(nm, "root_out_dir") + "/bin/llvm-nm", + root_build_dir), "-o", rebase_path(invoker.output, root_build_dir), ] diff --git a/llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni b/llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni index e2f91ad38cdc1..2ac71aa8e8367 100644 --- a/llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni +++ b/llvm/utils/gn/secondary/compiler-rt/lib/builtins/sources.gni @@ -339,6 +339,10 @@ if (current_cpu == "arm") { "arm/aeabi_memset.S", "arm/aeabi_uidivmod.S", "arm/aeabi_uldivmod.S", + "arm/aeabi_uread4.S", + "arm/aeabi_uread8.S", + "arm/aeabi_uwrite4.S", + "arm/aeabi_uwrite8.S", "arm/bswapdi2.S", "arm/bswapsi2.S", "arm/clzdi2.S", @@ -504,6 +508,9 @@ if (current_cpu == "ppc64") { "ppc/gcc_qsub.c", "ppc/multc3.c", ] + if (current_os == "aix") { + builtins_sources += [ "ppc/init_ifuncs.c" ] + } } if (current_cpu == "riscv" || current_cpu == "riscv64") { diff --git a/llvm/utils/gn/secondary/compiler-rt/lib/ubsan/BUILD.gn b/llvm/utils/gn/secondary/compiler-rt/lib/ubsan/BUILD.gn index c331193ca94c9..541b86ad0970e 100644 --- a/llvm/utils/gn/secondary/compiler-rt/lib/ubsan/BUILD.gn +++ b/llvm/utils/gn/secondary/compiler-rt/lib/ubsan/BUILD.gn @@ -1,3 +1,4 @@ +import("//compiler-rt/gen_dynamic_list.gni") import("//compiler-rt/gen_version_script.gni") import("//compiler-rt/target.gni") @@ -5,9 +6,15 @@ group("ubsan") { deps = [ ":ubsan_shared", ":ubsan_static", + ":ubsan_static_dynamic_list", ] if (current_os != "mac") { - deps += [ ":ubsan_static_cxx" ] + deps += [ + ":ubsan_loop_detect", + ":ubsan_loop_detect_dynamic_list", + ":ubsan_static_cxx", + ":ubsan_static_cxx_dynamic_list", + ] } } @@ -108,7 +115,32 @@ static_library("ubsan_static") { } } +gen_dynamic_list("ubsan_static_dynamic_list") { + extra = "ubsan.syms.extra" + lib = ":ubsan_static" + lib_name = "ubsan_standalone" +} + if (current_os != "mac") { + static_library("ubsan_loop_detect") { + output_dir = crt_current_out_dir + output_name = "clang_rt.ubsan_loop_detect$crt_current_target_suffix" + complete_static_lib = true + configs -= [ + "//llvm/utils/gn/build:llvm_code", + "//llvm/utils/gn/build:no_rtti", + "//llvm/utils/gn/build:thin_archive", + ] + configs += [ "//llvm/utils/gn/build:crt_code" ] + sources = [ "ubsan_loop_detect.cpp" ] + deps = [ "//compiler-rt/include($host_toolchain)" ] + } + + gen_dynamic_list("ubsan_loop_detect_dynamic_list") { + lib = ":ubsan_loop_detect" + lib_name = "ubsan_loop_detect" + } + static_library("ubsan_static_cxx") { output_dir = crt_current_out_dir output_name = "clang_rt.ubsan_standalone_cxx$crt_current_target_suffix" @@ -120,6 +152,12 @@ if (current_os != "mac") { configs += [ "//llvm/utils/gn/build:crt_code" ] deps = [ ":cxx_sources" ] } + + gen_dynamic_list("ubsan_static_cxx_dynamic_list") { + extra = "ubsan.syms.extra" + lib = ":ubsan_static_cxx" + lib_name = "ubsan_standalone_cxx" + } } shared_library("ubsan_shared") { diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn index 969e0c2c370ae..81084d8d092a8 100644 --- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn @@ -1142,6 +1142,7 @@ if (current_toolchain == default_toolchain) { "__iterator/aliasing_iterator.h", "__iterator/back_insert_iterator.h", "__iterator/bounded_iter.h", + "__iterator/capacity_aware_iterator.h", "__iterator/common_iterator.h", "__iterator/concepts.h", "__iterator/counted_iterator.h", diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn index b3217fe02570b..669a39f9c94ac 100644 --- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn +++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn @@ -43,7 +43,6 @@ static_library("Utility") { "RegisterContextDarwin_x86_64.cpp", "RegisterContextDummy.cpp", "RegisterContextFreeBSD_i386.cpp", - "RegisterContextFreeBSD_mips64.cpp", "RegisterContextFreeBSD_powerpc.cpp", "RegisterContextFreeBSD_x86_64.cpp", "RegisterContextHistory.cpp", @@ -60,7 +59,6 @@ static_library("Utility") { "RegisterContextPOSIX_arm.cpp", "RegisterContextPOSIX_arm64.cpp", "RegisterContextPOSIX_loongarch64.cpp", - "RegisterContextPOSIX_mips64.cpp", "RegisterContextPOSIX_powerpc.cpp", "RegisterContextPOSIX_ppc64le.cpp", "RegisterContextPOSIX_riscv32.cpp", diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn index 1a1e9ca867e6c..bf924cb642f1b 100644 --- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn +++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn @@ -19,7 +19,6 @@ static_library("elf-core") { "RegisterContextPOSIXCore_arm.cpp", "RegisterContextPOSIXCore_arm64.cpp", "RegisterContextPOSIXCore_loongarch64.cpp", - "RegisterContextPOSIXCore_mips64.cpp", "RegisterContextPOSIXCore_powerpc.cpp", "RegisterContextPOSIXCore_ppc64le.cpp", "RegisterContextPOSIXCore_riscv32.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/CAS/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/CAS/BUILD.gn index 547ea818df82b..8579e8b0a9c32 100644 --- a/llvm/utils/gn/secondary/llvm/lib/CAS/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/CAS/BUILD.gn @@ -4,6 +4,7 @@ static_library("CAS") { "ActionCache.cpp", "ActionCaches.cpp", "BuiltinCAS.cpp", + "BuiltinObjectHasher.cpp", "BuiltinUnifiedCASDatabases.cpp", "CASNodeSchema.cpp", "DatabaseFile.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn index d078403135963..00c98383a5440 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn @@ -149,6 +149,7 @@ static_library("LLVMAMDGPUCodeGen") { "AMDGPUGlobalISelDivergenceLowering.cpp", "AMDGPUGlobalISelUtils.cpp", "AMDGPUHSAMetadataStreamer.cpp", + "AMDGPUHazardLatency.cpp", "AMDGPUIGroupLP.cpp", "AMDGPUISelDAGToDAG.cpp", "AMDGPUISelLowering.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn index 976f6dec25b72..c9ad9b6ceab61 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn @@ -68,6 +68,7 @@ static_library("LLVMHexagonCodeGen") { "HexagonGenMemAbsolute.cpp", "HexagonGenMux.cpp", "HexagonGenPredicate.cpp", + "HexagonGlobalRegion.cpp", "HexagonHardwareLoops.cpp", "HexagonHazardRecognizer.cpp", "HexagonISelDAGToDAG.cpp", @@ -75,6 +76,7 @@ static_library("LLVMHexagonCodeGen") { "HexagonISelLowering.cpp", "HexagonISelLoweringHVX.cpp", "HexagonInstrInfo.cpp", + "HexagonLiveVariables.cpp", "HexagonLoadStoreWidening.cpp", "HexagonLoopAlign.cpp", "HexagonLoopIdiomRecognition.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn index c368cfe46405e..6530f35b45b55 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn @@ -90,6 +90,7 @@ static_library("LLVMPowerPCCodeGen") { "PPCMachineScheduler.cpp", "PPCMacroFusion.cpp", "PPCPreEmitPeephole.cpp", + "PPCPrepareIFuncsOnAIX.cpp", "PPCReduceCRLogicals.cpp", "PPCRegisterInfo.cpp", "PPCSelectionDAGInfo.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn index 11a57fcb008cd..4b90fc1986589 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn @@ -12,6 +12,39 @@ tablegen("WebAssemblyGenFastISel") { td_file = "WebAssembly.td" } +tablegen("WebAssemblyGenGlobalISel") { + visibility = [ ":LLVMWebAssemblyCodeGen" ] + args = [ "-gen-global-isel" ] + td_file = "WebAssemblyGISel.td" +} + +tablegen("WebAssemblyGenPostLegalizeGICombiner") { + visibility = [ ":LLVMWebAssemblyCodeGen" ] + args = [ + "-gen-global-isel-combiner", + "-combiners=WebAssemblyPostLegalizerCombiner", + ] + td_file = "WebAssemblyGISel.td" +} + +tablegen("WebAssemblyGenPreLegalizeGICombiner") { + visibility = [ ":LLVMWebAssemblyCodeGen" ] + args = [ + "-gen-global-isel-combiner", + "-combiners=WebAssemblyPreLegalizerCombiner", + ] + td_file = "WebAssemblyGISel.td" +} + +tablegen("WebAssemblyGenRegisterBank") { + visibility = [ + ":LLVMWebAssemblyCodeGen", + "//llvm/unittests/Target/WebAssembly:WebAssemblyTests", + ] + args = [ "-gen-register-bank" ] + td_file = "WebAssembly.td" +} + tablegen("WebAssemblyGenSDNodeInfo") { visibility = [ ":LLVMWebAssemblyCodeGen" ] args = [ "-gen-sd-node-info" ] @@ -22,6 +55,10 @@ static_library("LLVMWebAssemblyCodeGen") { deps = [ ":WebAssemblyGenDAGISel", ":WebAssemblyGenFastISel", + ":WebAssemblyGenGlobalISel", + ":WebAssemblyGenPostLegalizeGICombiner", + ":WebAssemblyGenPreLegalizeGICombiner", + ":WebAssemblyGenRegisterBank", ":WebAssemblyGenSDNodeInfo", "MCTargetDesc", "TargetInfo", @@ -39,6 +76,12 @@ static_library("LLVMWebAssemblyCodeGen") { ] include_dirs = [ "." ] sources = [ + "GISel/WebAssemblyCallLowering.cpp", + "GISel/WebAssemblyInstructionSelector.cpp", + "GISel/WebAssemblyLegalizerInfo.cpp", + "GISel/WebAssemblyPostLegalizerCombiner.cpp", + "GISel/WebAssemblyPreLegalizerCombiner.cpp", + "GISel/WebAssemblyRegisterBankInfo.cpp", "WebAssemblyAddMissingPrototypes.cpp", "WebAssemblyArgumentMove.cpp", "WebAssemblyAsmPrinter.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn index 9c8eb695989fb..ffa050a088206 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn @@ -57,6 +57,15 @@ tablegen("X86GenPreLegalizeGICombiner") { td_file = "X86.td" } +tablegen("X86GenPostLegalizeGICombiner") { + visibility = [ ":LLVMX86CodeGen" ] + args = [ + "-gen-global-isel-combiner", + "-combiners=X86PostLegalizerCombiner", + ] + td_file = "X86.td" +} + static_library("LLVMX86CodeGen") { deps = [ ":X86GenCallingConv", @@ -65,8 +74,9 @@ static_library("LLVMX86CodeGen") { ":X86GenFoldTables", ":X86GenGlobalISel", ":X86GenInstrMapping", - ":X86GenRegisterBank", + ":X86GenPostLegalizeGICombiner", ":X86GenPreLegalizeGICombiner", + ":X86GenRegisterBank", "MCTargetDesc", "TargetInfo", "//llvm/include/llvm/Config:llvm-config", @@ -90,6 +100,7 @@ static_library("LLVMX86CodeGen") { "GISel/X86CallLowering.cpp", "GISel/X86InstructionSelector.cpp", "GISel/X86LegalizerInfo.cpp", + "GISel/X86PostLegalizerCombiner.cpp", "GISel/X86PreLegalizerCombiner.cpp", "GISel/X86RegisterBankInfo.cpp", "X86ArgumentStackSlotRebase.cpp", @@ -98,6 +109,7 @@ static_library("LLVMX86CodeGen") { "X86AvoidTrailingCall.cpp", "X86CallFrameOptimization.cpp", "X86CallingConv.cpp", + "X86CleanupLocalDynamicTLS.cpp", "X86CmovConversion.cpp", "X86CodeGenPassBuilder.cpp", "X86CompressEVEX.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/CAS/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/CAS/BUILD.gn index cbffe9838e58c..904a3cfbd2136 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/CAS/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/CAS/BUILD.gn @@ -9,6 +9,7 @@ unittest("CASTests") { ] sources = [ "ActionCacheTest.cpp", + "BuiltinObjectHasherTest.cpp", "CASTestConfig.cpp", "NamedValuesSchemaTest.cpp", "ObjectStoreTest.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/Target/WebAssembly/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Target/WebAssembly/BUILD.gn index d94bd364f8173..9cab2f14db817 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/Target/WebAssembly/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/Target/WebAssembly/BUILD.gn @@ -8,6 +8,7 @@ unittest("WebAssemblyTests") { "//llvm/lib/MC", "//llvm/lib/Support", "//llvm/lib/Target/WebAssembly:LLVMWebAssemblyCodeGen", + "//llvm/lib/Target/WebAssembly:WebAssemblyGenRegisterBank", "//llvm/lib/Target/WebAssembly/MCTargetDesc", "//llvm/lib/Target/WebAssembly/TargetInfo", "//llvm/lib/TargetParser", diff --git a/llvm/utils/mlgo-utils/mlgo/corpus/extract_ir_lib.py b/llvm/utils/mlgo-utils/mlgo/corpus/extract_ir_lib.py index f434e59524bbf..386dede34ad11 100644 --- a/llvm/utils/mlgo-utils/mlgo/corpus/extract_ir_lib.py +++ b/llvm/utils/mlgo-utils/mlgo/corpus/extract_ir_lib.py @@ -122,7 +122,7 @@ def _get_extraction_bc_command( def _extract_clang_artifacts( self, llvm_objcopy_path: str, - cmd_filter: str, + cmd_filter: Optional[str], is_thinlto: bool, cmd_section_name: str, bitcode_section_name: str, @@ -343,7 +343,7 @@ def run_extraction( objs: List[TrainingIRExtractor], num_workers: int, llvm_objcopy_path: str, - cmd_filter: str, + cmd_filter: Optional[str], thinlto_build: str, cmd_section_name: str, bitcode_section_name: str, diff --git a/llvm/utils/profcheck-xfail.txt b/llvm/utils/profcheck-xfail.txt index 414b47d08683d..f8526550257cf 100644 --- a/llvm/utils/profcheck-xfail.txt +++ b/llvm/utils/profcheck-xfail.txt @@ -130,6 +130,7 @@ Transforms/ExpandIRInsts/X86/udiv129.ll Transforms/ExpandIRInsts/X86/urem129.ll Transforms/ExpandIRInsts/X86/vector.ll Transforms/ExpandIRInsts/X86/expand-fp-convert-small.ll +Transforms/ExpandIRInsts/X86/expand-int-convert-small.ll Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptosi129.ll Transforms/ExpandIRInsts/X86/expand-large-fp-convert-fptoui129.ll Transforms/ExpandIRInsts/X86/expand-large-fp-convert-si129tofp.ll @@ -207,13 +208,9 @@ Transforms/IndVarSimplify/invalidate-modified-lcssa-phi.ll Transforms/IndVarSimplify/pr45835.ll Transforms/IndVarSimplify/preserving-debugloc-rem-div.ll Transforms/InstCombine/2004-09-20-BadLoadCombine.ll -Transforms/InstCombine/2005-04-07-UDivSelectCrash.ll -Transforms/InstCombine/add-shl-mul-umax.ll Transforms/InstCombine/and2.ll Transforms/InstCombine/and-fcmp.ll Transforms/InstCombine/and-or-icmps.ll -Transforms/InstCombine/apint-div1.ll -Transforms/InstCombine/apint-div2.ll Transforms/InstCombine/atomic.ll Transforms/InstCombine/binop-cast.ll Transforms/InstCombine/binop-select-cast-of-select-cond.ll @@ -224,9 +221,6 @@ Transforms/InstCombine/canonicalize-clamp-like-pattern-between-negative-and-posi Transforms/InstCombine/canonicalize-clamp-like-pattern-between-zero-and-positive-threshold.ll Transforms/InstCombine/cast-mul-select.ll Transforms/InstCombine/clamp-to-minmax.ll -Transforms/InstCombine/cttz.ll -Transforms/InstCombine/div.ll -Transforms/InstCombine/div-shift.ll Transforms/InstCombine/fabs.ll Transforms/InstCombine/fcmp-select.ll Transforms/InstCombine/ffs-1.ll @@ -258,7 +252,6 @@ Transforms/InstCombine/minmax-fp.ll Transforms/InstCombine/minmax-intrinsics.ll Transforms/InstCombine/mul-inseltpoison.ll Transforms/InstCombine/mul.ll -Transforms/InstCombine/mul-pow2.ll Transforms/InstCombine/multiple-uses-load-bitcast-select.ll Transforms/InstCombine/nested-select.ll Transforms/InstCombine/or-fcmp.ll diff --git a/llvm/utils/release/github-upload-release.py b/llvm/utils/release/github-upload-release.py index 2d8fb4531eb51..8aa39d3600c19 100755 --- a/llvm/utils/release/github-upload-release.py +++ b/llvm/utils/release/github-upload-release.py @@ -280,7 +280,7 @@ def uncomment_download_links(repo, release_version): args = parser.parse_args() -gh = github.Github(args.token) +gh = github.Github(auth=github.Auth.Token(args.token)) llvm_org = gh.get_organization("llvm") llvm_repo = llvm_org.get_repo("llvm-project") @@ -291,7 +291,7 @@ def uncomment_download_links(repo, release_version): # Validate that this user is allowed to modify releases. user = gh.get_user(args.user) team = ( - github.Github(args.user_token) + github.Github(auth=github.Auth.Token(args.user_token)) .get_organization("llvm") .get_team_by_slug("llvm-release-managers") ) diff --git a/llvm/utils/update_analyze_test_checks.py b/llvm/utils/update_analyze_test_checks.py index fa287110053e2..bd249a53f458f 100755 --- a/llvm/utils/update_analyze_test_checks.py +++ b/llvm/utils/update_analyze_test_checks.py @@ -41,6 +41,27 @@ from UpdateTestChecks import common +def extract_vplan(raw_output): + """ + Extract a VPlan block from loop-vectorize debug output using brace-depth + tracking. + TODO: Remove once only -vplan-print-after is supported. + """ + result = [] + brace_depth = 0 + for line in raw_output.splitlines(): + if not brace_depth and line.startswith("VPlan 'Initial VPlan"): + brace_depth = 1 + result.append(line) + continue + if brace_depth: + brace_depth += line.count("{") - line.count("}") + result.append(line) + if brace_depth == 0: + break + return "\n".join(result) if result else None + + def update_test(opt_basename: str, ti: common.TestInfo): triple_in_ir = None for l in ti.input_lines: @@ -99,6 +120,14 @@ def update_test(opt_basename: str, ti: common.TestInfo): raw_tool_outputs = common.invoke_tool(ti.args.opt_binary, opt_args, ti.path) + # Detect VPlan output for LV pass. Don't use VPlan mode if filters are + # active since the user is likely filtering to specific LV debug lines + # (e.g., cost model). + is_vplan_output = ( + not ti.args.filters + and re.search(r"VPlan 'Initial VPlan", raw_tool_outputs) is not None + ) + regex_map = { r"Printing analysis ": common.ANALYZE_FUNCTION_RE, r"(LV|LDist|HashRecognize): Checking a loop in ": common.LOOP_PASS_DEBUG_RE, @@ -108,9 +137,19 @@ def update_test(opt_basename: str, ti: common.TestInfo): if re.search(split_by, raw_tool_outputs) is None: continue for raw_tool_output in re.split(split_by, raw_tool_outputs): + if is_vplan_output: + vplan_output = extract_vplan(raw_tool_output) + if not vplan_output: + continue + # Reconstruct minimal output: function header line + VPlan + func_header = raw_tool_output.split("\n")[0] + raw_tool_output = "\n".join([func_header, vplan_output]) + + # For VPlan mode, don't scrub whitespace - preserve exact alignment + scrubber = (lambda body: body) if is_vplan_output else common.scrub_body builder.process_run_line( regex, - common.scrub_body, + scrubber, raw_tool_output, prefixes, ) diff --git a/mlir/.clang-tidy b/mlir/.clang-tidy index eb8cbbeb9723c..0d4a4b1214837 100644 --- a/mlir/.clang-tidy +++ b/mlir/.clang-tidy @@ -58,3 +58,5 @@ CheckOptions: value: camelBack - key: readability-identifier-naming.VariableCase value: camelBack + - key: modernize-use-using.IgnoreExternC + value: true diff --git a/mlir/include/mlir-c/ExtensibleDialect.h b/mlir/include/mlir-c/ExtensibleDialect.h new file mode 100644 index 0000000000000..98457805f57c0 --- /dev/null +++ b/mlir/include/mlir-c/ExtensibleDialect.h @@ -0,0 +1,76 @@ +//===-- mlir-c/ExtensibleDialect.h - Extensible dialect APIs -----*- C -*-====// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM +// Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This header provides APIs for extensible dialects. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_C_EXTENSIBLEDIALECT_H +#define MLIR_C_EXTENSIBLEDIALECT_H + +#include "mlir-c/IR.h" +#include "mlir-c/Support.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//===----------------------------------------------------------------------===// +/// Opaque type declarations (see mlir-c/IR.h for more details). +//===----------------------------------------------------------------------===// + +#define DEFINE_C_API_STRUCT(name, storage) \ + struct name { \ + storage *ptr; \ + }; \ + typedef struct name name + +DEFINE_C_API_STRUCT(MlirDynamicOpTrait, void); + +/// Attach a dynamic op trait to the given operation name. +/// Note that the operation name must be modeled by dynamic dialect and must be +/// registered. +/// The ownership of the trait will be transferred to the operation name +/// after this call. +MLIR_CAPI_EXPORTED bool +mlirDynamicOpTraitAttach(MlirDynamicOpTrait dynamicOpTrait, + MlirStringRef opName, MlirContext context); + +/// Get the dynamic op trait that indicates the operation is a terminator. +MLIR_CAPI_EXPORTED MlirDynamicOpTrait mlirDynamicOpTraitGetIsTerminator(void); + +/// Get the dynamic op trait that indicates regions have no terminator. +MLIR_CAPI_EXPORTED MlirDynamicOpTrait mlirDynamicOpTraitGetNoTerminator(void); + +/// Destroy the dynamic op trait. +MLIR_CAPI_EXPORTED void +mlirDynamicOpTraitDestroy(MlirDynamicOpTrait dynamicOpTrait); + +typedef struct { + /// Optional constructor for the user data. + /// Set to nullptr to disable it. + void (*construct)(void *userData); + /// Optional destructor for the user data. + /// Set to nullptr to disable it. + void (*destruct)(void *userData); + /// The callback function to verify the operation. + MlirLogicalResult (*verifyTrait)(MlirOperation op, void *userData); + /// The callback function to verify the operation with access to regions. + MlirLogicalResult (*verifyRegionTrait)(MlirOperation op, void *userData); +} MlirDynamicOpTraitCallbacks; + +/// Create a custom dynamic op trait with the given type ID and callbacks. +MLIR_CAPI_EXPORTED MlirDynamicOpTrait mlirDynamicOpTraitCreate( + MlirTypeID typeID, MlirDynamicOpTraitCallbacks callbacks, void *userData); + +#ifdef __cplusplus +} +#endif + +#endif // MLIR_C_EXTENSIBLEDIALECT_H diff --git a/mlir/include/mlir-c/Support.h b/mlir/include/mlir-c/Support.h index 6abd8894227c3..26da8eee022c5 100644 --- a/mlir/include/mlir-c/Support.h +++ b/mlir/include/mlir-c/Support.h @@ -60,6 +60,9 @@ extern "C" { /// Re-export llvm::ThreadPool so as to avoid including the LLVM C API directly. DEFINE_C_API_STRUCT(MlirLlvmThreadPool, void); +/// Re-export llvm::raw_fd_ostream so as to avoid including the LLVM C API +/// directly. +DEFINE_C_API_STRUCT(MlirLlvmRawFdOStream, void); DEFINE_C_API_STRUCT(MlirTypeID, const void); DEFINE_C_API_STRUCT(MlirTypeIDAllocator, void); @@ -153,6 +156,35 @@ MLIR_CAPI_EXPORTED MlirLlvmThreadPool mlirLlvmThreadPoolCreate(void); /// Destroy an LLVM thread pool. MLIR_CAPI_EXPORTED void mlirLlvmThreadPoolDestroy(MlirLlvmThreadPool pool); +//===----------------------------------------------------------------------===// +// MlirLlvmRawFdOStream. +//===----------------------------------------------------------------------===// + +/// Create a raw_fd_ostream for the given path. This wrapper is needed because +/// std::ostream does not provide the file sharing semantics required on +/// Windows. +/// - `path`: output file path. +/// - `binary`: controls text vs binary mode. +/// - `errorCallback`: called with an error message on failure (optional). +/// - `userData`: forwarded to `errorCallback` so it can copy the error message +/// into caller-owned storage (e.g., a `std::string`). +/// On failure, returns a null stream and invokes the optional error callback +/// with the error message. +MLIR_CAPI_EXPORTED MlirLlvmRawFdOStream +mlirLlvmRawFdOStreamCreate(const char *path, bool binary, + MlirStringCallback errorCallback, void *userData); + +/// Write a string to a raw_fd_ostream created with mlirLlvmRawFdOStreamCreate. +MLIR_CAPI_EXPORTED void mlirLlvmRawFdOStreamWrite(MlirLlvmRawFdOStream stream, + MlirStringRef string); + +/// Checks if a raw_fd_ostream is null. +MLIR_CAPI_EXPORTED bool mlirLlvmRawFdOStreamIsNull(MlirLlvmRawFdOStream stream); + +/// Destroy a raw_fd_ostream created with mlirLlvmRawFdOStreamCreate. +MLIR_CAPI_EXPORTED void +mlirLlvmRawFdOStreamDestroy(MlirLlvmRawFdOStream stream); + //===----------------------------------------------------------------------===// // TypeID API. //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Bindings/Python/Diagnostics.h b/mlir/include/mlir/Bindings/Python/Diagnostics.h index 167002d561931..b18f5673f0e3b 100644 --- a/mlir/include/mlir/Bindings/Python/Diagnostics.h +++ b/mlir/include/mlir/Bindings/Python/Diagnostics.h @@ -11,10 +11,10 @@ #include "mlir-c/Diagnostics.h" #include "mlir-c/IR.h" -#include "llvm/Support/raw_ostream.h" #include #include +#include #include namespace mlir { @@ -30,29 +30,30 @@ class CollectDiagnosticsToStringScope { /*deleteUserData=*/nullptr); } ~CollectDiagnosticsToStringScope() { - assert(message.empty() && "unchecked error message"); + assert(messageStream.str().empty() && "unchecked error message"); mlirContextDetachDiagnosticHandler(context, handlerID); } [[nodiscard]] std::string takeMessage() { - std::string newMessage; - std::swap(message, newMessage); + std::string newMessage = messageStream.str(); + messageStream.str(""); + messageStream.clear(); return newMessage; } private: static MlirLogicalResult handler(MlirDiagnostic diag, void *data) { auto printer = +[](MlirStringRef message, void *data) { - *static_cast(data) + *static_cast(data) << std::string_view(message.data, message.length); }; MlirLocation loc = mlirDiagnosticGetLocation(diag); - *static_cast(data) << "at "; + *static_cast(data) << "at "; mlirLocationPrint(loc, printer, data); - *static_cast(data) << ": "; + *static_cast(data) << ": "; mlirDiagnosticPrint(diag, printer, data); for (intptr_t i = 0; i < mlirDiagnosticGetNumNotes(diag); i++) { - *static_cast(data) << "\n"; + *static_cast(data) << "\n"; MlirDiagnostic note = mlirDiagnosticGetNote(diag, i); handler(note, data); } @@ -62,8 +63,7 @@ class CollectDiagnosticsToStringScope { MlirContext context; MlirDiagnosticHandlerID handlerID; - std::string message; - llvm::raw_string_ostream messageStream{message}; + std::ostringstream messageStream; }; } // namespace python diff --git a/mlir/include/mlir/Bindings/Python/Globals.h b/mlir/include/mlir/Bindings/Python/Globals.h index 6a722575c4e48..23cccdd36279a 100644 --- a/mlir/include/mlir/Bindings/Python/Globals.h +++ b/mlir/include/mlir/Bindings/Python/Globals.h @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include @@ -20,10 +22,7 @@ #include "mlir/Bindings/Python/NanobindUtils.h" #include "mlir/CAPI/Support.h" -#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/ADT/StringSet.h" #include "llvm/Support/Regex.h" namespace mlir { @@ -60,7 +59,7 @@ class MLIR_PYTHON_API_EXPORTED PyGlobals { /// Note that this returns void because it is expected that the module /// contains calls to decorators and helpers that register the salient /// entities. Returns true if dialect is successfully loaded. - bool loadDialectModule(llvm::StringRef dialectNamespace); + bool loadDialectModule(std::string_view dialectNamespace); /// Adds a user-friendly Attribute builder. /// Raises an exception if the mapping already exists and replace == false. @@ -121,13 +120,13 @@ class MLIR_PYTHON_API_EXPORTED PyGlobals { /// name. Note that this may trigger a load of the dialect, which can /// arbitrarily re-enter. std::optional - lookupOperationClass(llvm::StringRef operationName); + lookupOperationClass(std::string_view operationName); /// Looks up a registered operation adaptor class by operation /// name. Note that this may trigger a load of the dialect, which can /// arbitrarily re-enter. std::optional - lookupOpAdaptorClass(llvm::StringRef operationName); + lookupOpAdaptorClass(std::string_view operationName); class MLIR_PYTHON_API_EXPORTED TracebackLoc { public: @@ -143,7 +142,7 @@ class MLIR_PYTHON_API_EXPORTED PyGlobals { void registerTracebackFileExclusion(const std::string &file); - bool isUserTracebackFilename(llvm::StringRef file); + bool isUserTracebackFilename(std::string_view file); static constexpr size_t kMaxFrames = 512; @@ -157,7 +156,7 @@ class MLIR_PYTHON_API_EXPORTED PyGlobals { bool rebuildUserTracebackIncludeRegex = false; std::regex userTracebackExcludeRegex; bool rebuildUserTracebackExcludeRegex = false; - llvm::StringMap isUserTracebackFilenameCache; + std::unordered_map isUserTracebackFilenameCache; }; TracebackLoc &getTracebackLoc() { return tracebackLoc; } @@ -193,20 +192,24 @@ class MLIR_PYTHON_API_EXPORTED PyGlobals { /// Module name prefixes to search under for dialect implementation modules. std::vector dialectSearchPrefixes; /// Map of dialect namespace to external dialect class object. - llvm::StringMap dialectClassMap; + std::unordered_map dialectClassMap; /// Map of full operation name to external operation class object. - llvm::StringMap operationClassMap; + std::unordered_map operationClassMap; /// Map of full operation name to external operation adaptor class object. - llvm::StringMap opAdaptorClassMap; + std::unordered_map opAdaptorClassMap; /// Map of attribute ODS name to custom builder. - llvm::StringMap attributeBuilderMap; + std::unordered_map attributeBuilderMap; /// Map of MlirTypeID to custom type caster. - llvm::DenseMap typeCasterMap; + std::unordered_map + typeCasterMap; /// Map of MlirTypeID to custom value caster. - llvm::DenseMap valueCasterMap; + std::unordered_map + valueCasterMap; /// Set of dialect namespaces that we have attempted to import implementation /// modules for. - llvm::StringSet<> loadedDialectModules; + std::unordered_set loadedDialectModules; TracebackLoc tracebackLoc; TypeIDAllocator typeIDAllocator; diff --git a/mlir/include/mlir/Bindings/Python/IRAttributes.h b/mlir/include/mlir/Bindings/Python/IRAttributes.h index 5ff9afd0875f1..d5d5548602114 100644 --- a/mlir/include/mlir/Bindings/Python/IRAttributes.h +++ b/mlir/include/mlir/Bindings/Python/IRAttributes.h @@ -13,6 +13,7 @@ #include #include #include +#include #include "mlir-c/BuiltinAttributes.h" #include "mlir-c/BuiltinTypes.h" @@ -31,13 +32,13 @@ struct nb_buffer_info { ssize_t size = 0; const char *format = nullptr; ssize_t ndim = 0; - SmallVector shape; - SmallVector strides; + std::vector shape; + std::vector strides; bool readonly = false; nb_buffer_info( void *ptr, ssize_t itemsize, const char *format, ssize_t ndim, - SmallVector shape_in, SmallVector strides_in, + std::vector shape_in, std::vector strides_in, bool readonly = false, std::unique_ptr owned_view_in = std::unique_ptr(nullptr, nullptr)); @@ -462,11 +463,11 @@ class MLIR_PYTHON_API_EXPORTED PyDenseElementsAttribute Type *data = static_cast( const_cast(mlirDenseElementsAttrGetRawData(*this))); // Prepare the shape for the buffer_info. - SmallVector shape; + std::vector shape; for (intptr_t i = 0; i < rank; ++i) shape.push_back(mlirShapedTypeGetDimSize(shapedType, i)); // Prepare the strides for the buffer_info. - SmallVector strides; + std::vector strides; if (mlirDenseElementsAttrIsSplat(*this)) { // Splats are special, only the single value is stored. strides.assign(rank, 0); diff --git a/mlir/include/mlir/Bindings/Python/IRCore.h b/mlir/include/mlir/Bindings/Python/IRCore.h index 4bb49e6bc245d..e551a49bb34a8 100644 --- a/mlir/include/mlir/Bindings/Python/IRCore.h +++ b/mlir/include/mlir/Bindings/Python/IRCore.h @@ -23,6 +23,7 @@ #include "mlir-c/BuiltinAttributes.h" #include "mlir-c/Debug.h" #include "mlir-c/Diagnostics.h" +#include "mlir-c/ExtensibleDialect.h" #include "mlir-c/IR.h" #include "mlir-c/IntegerSet.h" #include "mlir-c/Support.h" @@ -1844,6 +1845,30 @@ class MLIR_PYTHON_API_EXPORTED PyOpAdaptor { PyOpAttributeMap attributes; }; +class MLIR_PYTHON_API_EXPORTED PyDynamicOpTrait { +public: + static bool attach(const nanobind::object &opName, + const nanobind::object &target, PyMlirContext &context); + + static void bind(nanobind::module_ &m); +}; + +namespace PyDynamicOpTraits { + +class MLIR_PYTHON_API_EXPORTED IsTerminator : public PyDynamicOpTrait { +public: + static bool attach(const nanobind::object &opName, PyMlirContext &context); + static void bind(nanobind::module_ &m); +}; + +class MLIR_PYTHON_API_EXPORTED NoTerminator : public PyDynamicOpTrait { +public: + static bool attach(const nanobind::object &opName, PyMlirContext &context); + static void bind(nanobind::module_ &m); +}; + +} // namespace PyDynamicOpTraits + MLIR_PYTHON_API_EXPORTED MlirValue getUniqueResult(MlirOperation operation); MLIR_PYTHON_API_EXPORTED void populateIRCore(nanobind::module_ &m); MLIR_PYTHON_API_EXPORTED void populateRoot(nanobind::module_ &m); diff --git a/mlir/include/mlir/Bindings/Python/NanobindAdaptors.h b/mlir/include/mlir/Bindings/Python/NanobindAdaptors.h index 6594670abaaa7..918030824c409 100644 --- a/mlir/include/mlir/Bindings/Python/NanobindAdaptors.h +++ b/mlir/include/mlir/Bindings/Python/NanobindAdaptors.h @@ -30,7 +30,7 @@ #include "mlir/Bindings/Python/Nanobind.h" #include "mlir-c/Bindings/Python/Interop.h" // This is expected after nanobind. // clang-format on -#include "llvm/ADT/Twine.h" +#include "mlir/Bindings/Python/NanobindUtils.h" namespace mlir { namespace python { @@ -550,10 +550,9 @@ class mlir_attribute_subclass : public pure_subclass { !isaFunction(rawAttribute)) { auto origRepr = nanobind::cast(nanobind::repr(otherAttribute)); - throw std::invalid_argument( - (llvm::Twine("Cannot cast attribute to ") + captureTypeName + - " (from " + origRepr + ")") - .str()); + throw std::invalid_argument(nanobind::detail::join( + "Cannot cast attribute to ", captureTypeName, " (from ", + origRepr, ")")); } nanobind::object self = superCls.attr("__new__")(cls, otherAttribute); return self; @@ -633,10 +632,9 @@ class mlir_type_subclass : public pure_subclass { !isaFunction(rawType)) { auto origRepr = nanobind::cast(nanobind::repr(otherType)); - throw std::invalid_argument((llvm::Twine("Cannot cast type to ") + - captureTypeName + " (from " + - origRepr + ")") - .str()); + throw std::invalid_argument( + nanobind::detail::join("Cannot cast type to ", captureTypeName, + " (from ", origRepr, ")")); } nanobind::object self = superCls.attr("__new__")(cls, otherType); return self; @@ -720,10 +718,9 @@ class mlir_value_subclass : public pure_subclass { !isaFunction(rawValue)) { auto origRepr = nanobind::cast(nanobind::repr(otherValue)); - throw std::invalid_argument((llvm::Twine("Cannot cast value to ") + - captureValueName + " (from " + - origRepr + ")") - .str()); + throw std::invalid_argument(nanobind::detail::join( + "Cannot cast value to ", captureValueName, " (from ", origRepr, + ")")); } nanobind::object self = superCls.attr("__new__")(cls, otherValue); return self; diff --git a/mlir/include/mlir/Bindings/Python/NanobindUtils.h b/mlir/include/mlir/Bindings/Python/NanobindUtils.h index 215daf245b902..2bd1025c49c36 100644 --- a/mlir/include/mlir/Bindings/Python/NanobindUtils.h +++ b/mlir/include/mlir/Bindings/Python/NanobindUtils.h @@ -12,13 +12,11 @@ #include "mlir-c/Support.h" #include "mlir/Bindings/Python/Nanobind.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/ADT/Twine.h" -#include "llvm/Support/DataTypes.h" -#include "llvm/Support/raw_ostream.h" +#include +#include #include +#include #include #include @@ -34,6 +32,18 @@ struct std::iterator_traits { namespace mlir { namespace python { +struct MlirTypeIDHash { + size_t operator()(MlirTypeID typeID) const { + return mlirTypeIDHashValue(typeID); + } +}; + +struct MlirTypeIDEqual { + bool operator()(MlirTypeID lhs, MlirTypeID rhs) const { + return mlirTypeIDEqual(lhs, rhs); + } +}; + /// CRTP template for special wrapper types that are allowed to be passed in as /// 'None' function arguments and can be resolved by some global mechanic if /// so. Such types will raise an error if this global resolution fails, and @@ -71,6 +81,14 @@ class Defaulting { namespace nanobind { namespace detail { +/// Helper function to concatenate arguments into a `std::string`. +template +inline std::string join(const Ts &...args) { + std::ostringstream oss; + (oss << ... << args); + return oss.str(); +} + template struct MlirDefaultingCaster { NB_TYPE_CASTER(DefaultingTy, const_name(DefaultingTy::kTypeDescription)) @@ -134,6 +152,17 @@ struct PyPrintAccumulator { } }; +/// RAII wrapper for MlirLlvmRawFdOStream that ensures destruction on scope +/// exit. +struct RAIIMlirLlvmRawFdOStream : MlirLlvmRawFdOStream { + RAIIMlirLlvmRawFdOStream(MlirLlvmRawFdOStream stream) + : MlirLlvmRawFdOStream(stream) {} + RAIIMlirLlvmRawFdOStream(const RAIIMlirLlvmRawFdOStream &) = delete; + RAIIMlirLlvmRawFdOStream & + operator=(const RAIIMlirLlvmRawFdOStream &) = delete; + ~RAIIMlirLlvmRawFdOStream() { mlirLlvmRawFdOStreamDestroy(*this); } +}; + /// Accumulates into a file, either writing text (default) /// or binary. The file may be a Python file-like object or a path to a file. class PyFileAccumulator { @@ -142,13 +171,19 @@ class PyFileAccumulator { : binary(binary) { std::string filePath; if (nanobind::try_cast(fileOrStringObject, filePath)) { - std::error_code ec; - writeTarget.emplace(filePath, ec); - if (ec) { + std::string errorMessage; + auto errorCallback = +[](MlirStringRef message, void *userData) { + auto *storage = static_cast(userData); + storage->assign(message.data, message.length); + }; + MlirLlvmRawFdOStream stream = mlirLlvmRawFdOStreamCreate( + filePath.c_str(), binary, errorCallback, &errorMessage); + if (mlirLlvmRawFdOStreamIsNull(stream)) { throw nanobind::value_error( - (std::string("Unable to open file for writing: ") + ec.message()) + (std::string("Unable to open file for writing: ") + errorMessage) .c_str()); } + writeTarget.emplace(stream); } else { writeTarget.emplace(fileOrStringObject.attr("write")); } @@ -156,7 +191,7 @@ class PyFileAccumulator { MlirStringCallback getCallback() { return writeTarget.index() == 0 ? getPyWriteCallback() - : getOstreamCallback(); + : getOStreamCallback(); } void *getUserData() { return this; } @@ -178,15 +213,15 @@ class PyFileAccumulator { }; } - MlirStringCallback getOstreamCallback() { + MlirStringCallback getOStreamCallback() { return [](MlirStringRef part, void *userData) { PyFileAccumulator *accum = static_cast(userData); - std::get(accum->writeTarget) - .write(part.data, part.length); + mlirLlvmRawFdOStreamWrite( + std::get(accum->writeTarget), part); }; } - std::variant writeTarget; + std::variant writeTarget; bool binary; }; @@ -271,8 +306,12 @@ class Sliceable { /// Trait to check if T provides a `maybeDownCast` method. /// Note, you need the & to detect inherited members. - template - using has_maybe_downcast = decltype(&T::maybeDownCast); + template + struct has_maybe_downcast : std::false_type {}; + + template + struct has_maybe_downcast> + : std::true_type {}; /// Returns the element at the given slice index. Supports negative indices /// by taking elements in inverse order. Returns a nullptr object if out @@ -285,7 +324,7 @@ class Sliceable { return {}; } - if constexpr (llvm::is_detected::value) + if constexpr (has_maybe_downcast::value) return static_cast(this) ->getRawElement(linearizeIndex(index)) .maybeDownCast(); @@ -297,7 +336,7 @@ class Sliceable { /// Returns a new instance of the pseudo-container restricted to the given /// slice. Returns a nullptr object on failure. nanobind::object getItemSlice(PyObject *slice) { - ssize_t start, stop, extraStep, sliceLength; + Py_ssize_t start, stop, extraStep, sliceLength; if (PySlice_GetIndicesEx(slice, length, &start, &stop, &extraStep, &sliceLength) != 0) { PyErr_SetString(PyExc_IndexError, "index out of range"); @@ -412,25 +451,4 @@ class Sliceable { } // namespace mlir -namespace llvm { - -template <> -struct DenseMapInfo { - static inline MlirTypeID getEmptyKey() { - auto *pointer = llvm::DenseMapInfo::getEmptyKey(); - return mlirTypeIDCreate(pointer); - } - static inline MlirTypeID getTombstoneKey() { - auto *pointer = llvm::DenseMapInfo::getTombstoneKey(); - return mlirTypeIDCreate(pointer); - } - static inline unsigned getHashValue(const MlirTypeID &val) { - return mlirTypeIDHashValue(val); - } - static inline bool isEqual(const MlirTypeID &lhs, const MlirTypeID &rhs) { - return mlirTypeIDEqual(lhs, rhs); - } -}; -} // namespace llvm - #endif // MLIR_BINDINGS_PYTHON_PYBINDUTILS_H diff --git a/mlir/include/mlir/CAPI/Support.h b/mlir/include/mlir/CAPI/Support.h index 89a460375f936..0951175c428d2 100644 --- a/mlir/include/mlir/CAPI/Support.h +++ b/mlir/include/mlir/CAPI/Support.h @@ -23,6 +23,7 @@ namespace llvm { class ThreadPoolInterface; +class raw_fd_ostream; } // namespace llvm /// Converts a StringRef into its MLIR C API equivalent. @@ -46,6 +47,7 @@ inline llvm::LogicalResult unwrap(MlirLogicalResult res) { } DEFINE_C_API_PTR_METHODS(MlirLlvmThreadPool, llvm::ThreadPoolInterface) +DEFINE_C_API_PTR_METHODS(MlirLlvmRawFdOStream, llvm::raw_fd_ostream) DEFINE_C_API_METHODS(MlirTypeID, mlir::TypeID) DEFINE_C_API_PTR_METHODS(MlirTypeIDAllocator, mlir::TypeIDAllocator) diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td index 24e40f40c2031..fd1729fa171de 100644 --- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td +++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td @@ -33,6 +33,17 @@ def AnyIntegerOrFloat : AnyTypeOf<[AnySignlessInteger, AnyFloat], "Integer or Fl def AnyIntegerOrFloatOr1DVector : AnyTypeOf<[AnyIntegerOrFloat, FixedVectorOfRankAndType<[1], [AnyIntegerOrFloat]>]>; +// Types with element width up to 64 bits, used to keep dpp operands legal. +def AMDGPU_IntOrFloatWidthLeq64 : Type< + CPred<"$_self.isIntOrFloat() && $_self.getIntOrFloatBitWidth() <= 64">, + "integer or float with element bitwidth <= 64">; + +def AMDGPU_IntOrFloatOr1DVectorWidthLeq64 : + AnyTypeOf<[ + AMDGPU_IntOrFloatWidthLeq64, + FixedVectorOfRankAndType<[1], [AMDGPU_IntOrFloatWidthLeq64]> + ]>; + //===----------------------------------------------------------------------===// // AMDGPU Op definitions //===----------------------------------------------------------------------===// @@ -643,8 +654,8 @@ def AMDGPU_RawBufferAtomicUminOp : def AMDGPU_DPPOp : AMDGPU_Op<"dpp", [Pure, SameTypeOperands, AllTypesMatch<["result", "old", "src"]>]>, - Arguments<(ins AnyType:$old, - AnyType:$src, + Arguments<(ins AMDGPU_IntOrFloatOr1DVectorWidthLeq64:$old, + AMDGPU_IntOrFloatOr1DVectorWidthLeq64:$src, AMDGPU_DPPPermAttr:$kind, OptionalAttr>:$permArgument, DefaultValuedAttr:$row_mask, @@ -1541,4 +1552,220 @@ def AMDGPU_TensorStoreFromLDSOp : }]; } +//===----------------------------------------------------------------------===// +// In-LDS Barrier Operations +// +// General note: any of these operations that impact memory have read and write +// effects as a crude model of their atomic nature - we don't want "reads" +// being hoisted out of loops. +//===----------------------------------------------------------------------===// + +def AMDGPU_DsBarrierInitOp : + AMDGPU_Op<"ds_barrier_init">, + Arguments<(ins Arg, "barrier(s)", + [MemRead, MemWrite]>:$base, + Variadic:$indices, + I32:$participants)> { + let summary = "Initialize an in-LDS barrier."; + let description = [{ + Given the location `!amdgpu.ds_barrier_state` in LDS (as specified by `base` and `indices`), + initialize the barrier structure so that the pending and init counts are equal to + `participants - 1`, which will have its high bits masked off, and its phase is equal to 0. + + Note that we subtract 1 from `participants` when constructing the barrier state + to provide clearer high-level semantics. + + The subtraction means that, when the `participant`th arrival occurs, the phase will change. + In practical terms, this means that you can use (for example) the number of subgroups or + waves per workgroup as `participants`, instead of manually needing to remove one. + + While the write of the initial state will be performed atomically, no synchronization + between waves will be performed by this operation. + + Example: + ```mlir + amdgpu.ds_barrier_init %barrier[], %c32 : memref>, i32 + ``` + + This operation is only available on gfx1250+. + }]; + + let assemblyFormat = [{ + $base `[` $indices `]` `,` $participants attr-dict `:` type($base) `,` type($participants) + }]; + + let hasVerifier = 1; +} + +def AMDGPU_DsBarrierPollStateOp : + AMDGPU_Op<"ds_barrier_poll_state">, + Arguments<(ins Arg, "barrier(s)", + [MemRead, MemWrite]>:$base, + Variadic:$indices)>, + Results<(outs AMDGPU_DsBarrierStateType:$out)> { + let summary = "Atomically read the state of an in-LDS barrier."; + let description = [{ + Atomically read and return the state of the barrier at `base[indices...]`. + + This will ultimately act like a `memref.load`, but this operation will ensure + that appropriate atomic orderings and syncscopes are set. + + Example: + ```mlir + %state = amdgpu.ds_barrier_poll_state %barrier[] : memref> -> !amdgpu.ds_barrier_state + ``` + + This operation is only available on gfx1250+. + }]; + + let assemblyFormat = [{ + $base `[` $indices `]` attr-dict `:` type($base) `->` type($out) + }]; + + let hasVerifier = 1; +} + +def AMDGPU_DsAsyncBarrierArriveOp : + AMDGPU_Op<"ds_async_barrier_arrive">, + Arguments<(ins Arg, "barrier(s)", + [MemRead, MemWrite]>:$base, + Variadic:$indices)> { + let summary = "Asynchronously arrive at an in-LDS barrier."; + let description = [{ + Add a arrival to the LDS barrier at `base[indices]` to the sequence of pending + asynchronous memory operations. + + This will add an "asynchronous memory operation" to the in-order list of pending + asynchronous loads from global memory to LDS. When the queue of such operations + issued before this operation is complete, the specified barrier will be arrived at, + decrementing the pending count by 1 **per lane that executes it** and rolling + over the phase if applicable. + + This operation does not return the old barrier state. + + Example: + ```mlir + amdgpu.ds_async_barrier_arrive %barrier[] : memref> + ``` + + This operation is only available on gfx1250+. + }]; + + let assemblyFormat = [{ + $base `[` $indices `]` attr-dict `:` type($base) + }]; + + let hasVerifier = 1; +} + +def AMDGPU_DsBarrierArriveOp : + AMDGPU_Op<"ds_barrier_arrive">, + Arguments<(ins Arg, "barrier(s)", + [MemRead, MemWrite]>:$base, + Variadic:$indices, + I64:$count)>, + Results<(outs AMDGPU_DsBarrierStateType:$out)> { + let summary = "Arrive at an in-LDS barrier and return old state."; + let description = [{ + Atomically arrive at the LDS barrier at `base[indices]` and decrement it by `count`, + rolling over the phase if needed and returning the old barrier state. + + `count` is the number of participants that should be subtracted from the barrier's + pending count **per lane that executes the operation**. + + Example: + ```mlir + %old_state = amdgpu.ds_barrier_arrive %barrier[], %c1 : memref>, i64 -> !amdgpu.ds_barrier_state + ``` + + This operation is only available on gfx1250+. + }]; + + let assemblyFormat = [{ + $base `[` $indices `]` `,` $count attr-dict `:` type($base) `,` type($count) `->` type($out) + }]; + + let hasVerifier = 1; +} + +def AMDGPU_DsBarrierStatePhaseOp : + AMDGPU_Op<"ds_barrier_state_phase", [Pure]>, + Arguments<(ins AMDGPU_DsBarrierStateType:$state)>, + Results<(outs I32:$res)> { + let summary = "Extract the phase of a barrier state."; + let description = [{ + Extract the phase of the `!amdgpu.ds_barrier_state` `state` as a 32-bit value. + + Example: + ```mlir + %phase = amdgpu.ds_barrier_state_phase %state : !amdgpu.ds_barrier_state -> i32 + ``` + }]; + + let assemblyFormat = [{ + $state attr-dict `:` type($state) `->` type($res) + }]; +} + +def AMDGPU_DsBarrierStatePendingCountOp : + AMDGPU_Op<"ds_barrier_state_pending_count", [Pure]>, + Arguments<(ins AMDGPU_DsBarrierStateType:$state)>, + Results<(outs I32:$res)> { + let summary = "Extract the pending count of a barrier state."; + let description = [{ + Extract the pending count of the `!amdgpu.ds_barrier_state` `state` as a 32-bit value. + + Example: + ```mlir + %pending = amdgpu.ds_barrier_state_pending_count %state : !amdgpu.ds_barrier_state -> i32 + ``` + }]; + + let assemblyFormat = [{ + $state attr-dict `:` type($state) `->` type($res) + }]; +} + +def AMDGPU_DsBarrierStateInitCountOp : + AMDGPU_Op<"ds_barrier_state_init_count", [Pure]>, + Arguments<(ins AMDGPU_DsBarrierStateType:$state)>, + Results<(outs I32:$res)> { + let summary = "Extract the init count of a barrier state."; + let description = [{ + Extract the init count of the `!amdgpu.ds_barrier_state` `state` as a 32-bit value. + + Example: + ```mlir + %init = amdgpu.ds_barrier_state_init_count %state : !amdgpu.ds_barrier_state -> i32 + ``` + }]; + + let assemblyFormat = [{ + $state attr-dict `:` type($state) `->` type($res) + }]; +} + +def AMDGPU_DsBarrierStatePhaseParity : + AMDGPU_Op<"ds_barrier_state_phase_parity", [Pure]>, + Arguments<(ins AMDGPU_DsBarrierStateType:$state)>, + Results<(outs I1:$res)> { + let summary = "Extract the phase parity of a barrier state."; + let description = [{ + Return the parity of the phase of the `!amdgpu.ds_barrier_state` `state`. + + This is intended to simplify the case where the barrier is being used to repeatedly + track completion of a task where the precise value of the phase won't mater, only that + it changed since (or as a result of) the arrival. + + Example: + ```mlir + %parity = amdgpu.ds_barrier_state_phase_parity %state : !amdgpu.ds_barrier_state -> i1 + ``` + }]; + + let assemblyFormat = [{ + $state attr-dict `:` type($state) `->` type($res) + }]; +} + #endif // MLIR_DIALECT_AMDGPU_IR_AMDGPUOPS_TD diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUTypes.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUTypes.td index 3ea1ba35815c3..aa76bff8ded80 100644 --- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUTypes.td +++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUTypes.td @@ -11,6 +11,7 @@ include "mlir/Dialect/AMDGPU/IR/AMDGPUBase.td" include "mlir/IR/AttrTypeBase.td" +include "mlir/IR/BuiltinTypeInterfaces.td" //===----------------------------------------------------------------------===// // AMDGPU Type definitions @@ -69,4 +70,28 @@ def AMDGPU_TDMDescriptorType : AMDGPU_Type<"TDMDescriptor", "tdm_descriptor"> { }]; } +def AMDGPU_DsBarrierStateType : AMDGPU_Type<"DsBarrierState", "ds_barrier_state", + [MemRefElementTypeInterface]> { + let summary = "State of an in-LDS barrier."; + let description = [{ + Type that encodes the state of an in-LDS barrier as used by the atomic barrier + instructions introduced on gfx1250. + + It consists of a 28-bit count of the number of pending arrivals at the barrier (the + *pending count*) in bits [27:0], a 4-bit *phase* in bits [31:28], and the 32-bit count + to re-initialize the pending count to on phase change (the *init count*) in bits [63:32]. + + When an instruction (either one of the explicit arrival primitives or tensor data + movement) *arrives* at such a barrier, the pending count is decremented. If this + decrement would cause the pending count to underflow, the count is instead reset + to the init count and the phase is decremented (wrapping back to 0). When the + phase is decremented, sleeping waves are woken up so they can check the barrier. + + The barrier state resides in LDS, but an old barrier state can be returned from atomic + arrival instructions or though atomic loads. + + This feature is not available prior to gfx1250. + }]; +} + #endif // MLIR_DIALECT_AMDGPU_IR_AMDGPUTYPES_TD diff --git a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td index 77d780425c3c3..c8754954c181d 100644 --- a/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td +++ b/mlir/include/mlir/Dialect/Arith/IR/ArithOps.td @@ -1742,7 +1742,9 @@ class BooleanConditionOrMatchingShape : PredOpTrait< condition # " is signless i1 or has matching shape", Or<[TypeIsPred, - AllShapesMatch<[condition, result]>.predicate]>>; + And<[SubstLeaves<"$_self", "$" # condition # ".getType()", IsShapedTypePred>, + SubstLeaves<"$_self", "$" # result # ".getType()", IsShapedTypePred>, + AllShapesMatch<[condition, result]>.predicate]>]>>; def SelectOp : Arith_Op<"select", [Pure, AllTypesMatch<["true_value", "false_value", "result"]>, diff --git a/mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h b/mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h index ea158914e445b..90857358437a1 100644 --- a/mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h +++ b/mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h @@ -182,8 +182,15 @@ LogicalResult promoteBufferResultsToOutParams(ModuleOp module, const BufferResultsToOutParamsOpts &options); +/// Options for dropping equivalent memref buffer results. +struct DropBufferResultsOpts { + /// If true, signatures of public functions are modified. + bool modifyPublicFunctions = false; +}; + /// Drop all memref function results that are equivalent to a function argument. -LogicalResult dropEquivalentBufferResults(ModuleOp module); +LogicalResult dropEquivalentBufferResults( + ModuleOp module, DropBufferResultsOpts options = DropBufferResultsOpts()); /// Creates a pass that promotes heap-based allocations to stack-based ones. /// Only buffers smaller with `isSmallAlloc(alloc) == true` are promoted. diff --git a/mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td b/mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td index 1eb692586bcfc..cd28bd6cf73a5 100644 --- a/mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.td @@ -276,6 +276,11 @@ def DropEquivalentBufferResultsPass Note: If a bbArg buffer is not returned directly but casted to beforehand, the buffer is still considered equivalent. }]; + let options = [ + Option<"modifyPublicFunctions", "modify-public-functions", "bool", + /*default=*/"false", "Modify function signatures of public " + "functions.">, + ]; let dependentDialects = ["memref::MemRefDialect"]; } diff --git a/mlir/include/mlir/Dialect/EmitC/Transforms/Passes.td b/mlir/include/mlir/Dialect/EmitC/Transforms/Passes.td index 1893c101e735b..40ecef33448d7 100644 --- a/mlir/include/mlir/Dialect/EmitC/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/EmitC/Transforms/Passes.td @@ -25,7 +25,8 @@ def WrapFuncInClassPass : Pass<"wrap-emitc-func-in-class"> { let description = [{ This pass transforms `emitc.func` operations into `emitc.class` operations. Function arguments become fields of the class, and the function body is moved - to a new `execute` method within the class. + to a new member method within the class. By default, this is `operator()()`. + If the corresponding function argument has attributes (accessed via `argAttrs`), these attributes are attached to the field operation. Otherwise, the field is created without additional attributes. @@ -41,7 +42,7 @@ def WrapFuncInClassPass : Pass<"wrap-emitc-func-in-class"> { // becomes emitc.class @modelClass { emitc.field @input_tensor : !emitc.array<1xf32> {emitc.opaque = "input_tensor"} - emitc.func @execute() { + emitc.func @operator() { %0 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t %1 = get_field @input_tensor : !emitc.array<1xf32> %2 = subscript %1[%0] : (!emitc.array<1xf32>, !emitc.size_t) -> !emitc.lvalue @@ -51,6 +52,12 @@ def WrapFuncInClassPass : Pass<"wrap-emitc-func-in-class"> { ``` }]; let dependentDialects = ["emitc::EmitCDialect"]; + let options = [ + Option<"funcName", "func-name", "std::string", + /*default=*/[{"operator()"}], + "The name of the newly generated member function with body " + "matching the input function."> + ]; } #endif // MLIR_DIALECT_EMITC_TRANSFORMS_PASSES diff --git a/mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h b/mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h index bdf6d0985e6db..962bdb3c032bf 100644 --- a/mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h +++ b/mlir/include/mlir/Dialect/EmitC/Transforms/Transforms.h @@ -28,8 +28,11 @@ ExpressionOp createExpression(Operation *op, OpBuilder &builder); /// Populates `patterns` with expression-related patterns. void populateExpressionPatterns(RewritePatternSet &patterns); -/// Populates 'patterns' with func-related patterns. -void populateFuncPatterns(RewritePatternSet &patterns); +//===----------------------------------------------------------------------===// +// The WrapFuncInClass pass. +//===----------------------------------------------------------------------===// + +void populateWrapFuncInClass(RewritePatternSet &patterns, StringRef fName); } // namespace emitc } // namespace mlir diff --git a/mlir/include/mlir/Dialect/GPU/IR/GPUOps.td b/mlir/include/mlir/Dialect/GPU/IR/GPUOps.td index 7891cf19ac921..48de1a8bf118e 100644 --- a/mlir/include/mlir/Dialect/GPU/IR/GPUOps.td +++ b/mlir/include/mlir/Dialect/GPU/IR/GPUOps.td @@ -348,8 +348,14 @@ def GPU_SubgroupSizeOp : GPU_Op<"subgroup_size", [ } def GPU_OptionalDimSizeHintAttr : ConfinedAttr, - [AttrConstraint.predicate]>, - "with 3 elements (if present)">]>; + [AttrConstraint.predicate, + CPred<"([](mlir::Attribute a) { " + " auto arr = ::llvm::cast<::mlir::DenseI32ArrayAttr>(a).asArrayRef();" + " return ::llvm::all_of(arr, [](int32_t v) { return v >= 1; });" + "})($_self)">]>]>, + "with 3 elements (if present) and all elements >= 1" + >] +>; def GPU_GPUFuncOp : GPU_Op<"func", [ HasParent<"GPUModuleOp">, AutomaticAllocationScope, FunctionOpInterface, @@ -1226,7 +1232,7 @@ def GPU_AllReduceOp : GPU_Op<"all_reduce", def AnyIntegerOrFloatOr1DVector : AnyTypeOf<[AnyIntegerOrFloat, FixedVectorOfRankAndType<[1], [AnyIntegerOrFloat]>]>; -def GPU_SubgroupReduceOp : GPU_Op<"subgroup_reduce", [SameOperandsAndResultType]> { +def GPU_SubgroupReduceOp : GPU_Op<"subgroup_reduce", [SameOperandsAndResultType, NoMemoryEffect]> { let summary = "Reduce values among subgroup."; let description = [{ The `subgroup_reduce` op reduces the values of lanes (work items) across a diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td index f21a03976dd86..0bcf8a4d6bb34 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td @@ -944,6 +944,18 @@ def LLVM_MemoryEffectsAttr : LLVM_Attr<"MemoryEffects", "memory_effects"> { let assemblyFormat = "`<` struct(params) `>`"; } +//===----------------------------------------------------------------------===// +// DenormalFPEnvAttr +//===----------------------------------------------------------------------===// + +def LLVM_DenormalFPEnvAttr : LLVM_Attr<"DenormalFPEnv", "denormal_fpenv"> { + let parameters = (ins "DenormalModeKind":$default_output_mode, + "DenormalModeKind":$default_input_mode, + "DenormalModeKind":$float_output_mode, + "DenormalModeKind":$float_input_mode); + let assemblyFormat = "`<` struct(params) `>`"; +} + //===----------------------------------------------------------------------===// // AliasScopeDomainAttr //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td index e2edab44153ca..6125ac0e328dd 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td @@ -806,6 +806,32 @@ def RoundingModeAttr : LLVM_EnumAttr< def ValidRoundingModeAttr : ConfinedAttr]>; +//===----------------------------------------------------------------------===// +// DenormalModeKind +//===----------------------------------------------------------------------===// + +def DenormalModeIEEE : LLVM_EnumAttrCase<"IEEE", "ieee", "IEEE", 0>; +def DenormalModePreserveSign + : LLVM_EnumAttrCase<"PreserveSign", "preservesign", "PreserveSign", 1>; +def DenormalModePositiveZero + : LLVM_EnumAttrCase<"PositiveZero", "positivezero", "PositiveZero", 2>; +def DenormalModeDynamic : LLVM_EnumAttrCase<"Dynamic", "dynamic", "Dynamic", 3>; +// Needed as llvm::DenormalModeKind defines this. +def DenormalModeInvalid + : LLVM_EnumAttrCase<"Invalid", "invalid", "Invalid", -1>; + +def DenormalModeKindAttr : LLVM_EnumAttr< + "DenormalModeKind", + "::llvm::DenormalMode::DenormalModeKind", + "LLVM Denormal Mode Kinds", + [DenormalModeIEEE, + DenormalModePreserveSign, + DenormalModePositiveZero, + DenormalModeDynamic, + DenormalModeInvalid]> { + let cppNamespace = "::mlir::LLVM"; +} + //===----------------------------------------------------------------------===// // FPExceptionBehavior //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td index 3bf4875678a9d..0957f751bf44b 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td @@ -799,6 +799,13 @@ def LLVM_CallOp UnitAttr:$cold, UnitAttr:$noduplicate, UnitAttr:$no_caller_saved_registers, UnitAttr:$nocallback, OptionalAttr:$modular_format, + OptionalAttr:$nobuiltins, + OptionalAttr:$allocsize, + UnitAttr:$optsize, UnitAttr:$minsize, + UnitAttr:$nobuiltin, UnitAttr:$save_reg_params, + OptionalAttr:$zero_call_used_regs, + OptionalAttr:$trap_func_name, + OptionalAttr:$default_func_attrs, VariadicOfVariadic:$op_bundle_operands, DenseI32ArrayAttr:$op_bundle_sizes, OptionalAttr:$op_bundle_tags, @@ -1956,7 +1963,7 @@ def LLVM_LLVMFuncOp : LLVM_Op<"func", [ UnitAttr:$dso_local, DefaultValuedAttr:$CConv, OptionalAttr:$comdat, - OptionalAttr:$convergent, + UnitAttr:$convergent, OptionalAttr:$personality, OptionalAttr:$garbageCollector, OptionalAttr:$passthrough, @@ -1965,15 +1972,10 @@ def LLVM_LLVMFuncOp : LLVM_Op<"func", [ OptionalAttr:$function_entry_count, OptionalAttr:$memory_effects, DefaultValuedAttr:$visibility_, - OptionalAttr:$arm_streaming, - OptionalAttr:$arm_locally_streaming, - OptionalAttr:$arm_streaming_compatible, - OptionalAttr:$arm_new_za, - OptionalAttr:$arm_in_za, - OptionalAttr:$arm_out_za, - OptionalAttr:$arm_inout_za, - OptionalAttr:$arm_preserves_za, - OptionalAttr:$section, + UnitAttr:$arm_streaming, UnitAttr:$arm_locally_streaming, + UnitAttr:$arm_streaming_compatible, UnitAttr:$arm_new_za, + UnitAttr:$arm_in_za, UnitAttr:$arm_out_za, UnitAttr:$arm_inout_za, + UnitAttr:$arm_preserves_za, OptionalAttr:$section, OptionalAttr:$unnamed_addr, OptionalAttr:$alignment, OptionalAttr:$vscale_range, @@ -1983,28 +1985,24 @@ def LLVM_LLVMFuncOp : LLVM_Op<"func", [ OptionalAttr:$reciprocal_estimates, OptionalAttr:$prefer_vector_width, OptionalAttr:$target_features, - OptionalAttr:$no_infs_fp_math, OptionalAttr:$no_nans_fp_math, OptionalAttr:$no_signed_zeros_fp_math, - OptionalAttr:$denormal_fp_math, - OptionalAttr:$denormal_fp_math_f32, + OptionalAttr:$denormal_fpenv, OptionalAttr:$fp_contract, OptionalAttr:$instrument_function_entry, OptionalAttr:$instrument_function_exit, - OptionalAttr:$no_inline, - OptionalAttr:$always_inline, - OptionalAttr:$inline_hint, - OptionalAttr:$no_unwind, - OptionalAttr:$will_return, - OptionalAttr:$noreturn, - OptionalAttr:$optimize_none, - OptionalAttr:$returns_twice, - OptionalAttr:$hot, - OptionalAttr:$cold, - OptionalAttr:$noduplicate, - OptionalAttr:$no_caller_saved_registers, - OptionalAttr:$nocallback, - OptionalAttr:$modular_format, + UnitAttr:$no_inline, UnitAttr:$always_inline, UnitAttr:$inline_hint, + UnitAttr:$no_unwind, UnitAttr:$will_return, UnitAttr:$noreturn, + UnitAttr:$optimize_none, UnitAttr:$returns_twice, UnitAttr:$hot, + UnitAttr:$cold, UnitAttr:$noduplicate, UnitAttr:$no_caller_saved_registers, + UnitAttr:$nocallback, OptionalAttr:$modular_format, + OptionalAttr:$nobuiltins, + OptionalAttr:$allocsize, + OptionalAttr:$optsize, + OptionalAttr:$minsize, + OptionalAttr:$save_reg_params, + OptionalAttr:$zero_call_used_regs, + OptionalAttr:$default_func_attrs, OptionalAttr:$vec_type_hint, OptionalAttr:$work_group_size_hint, OptionalAttr:$reqd_work_group_size, diff --git a/mlir/include/mlir/Dialect/MPI/IR/MPIOps.td b/mlir/include/mlir/Dialect/MPI/IR/MPIOps.td index b24c12459475e..d9e47ea3f6bfe 100644 --- a/mlir/include/mlir/Dialect/MPI/IR/MPIOps.td +++ b/mlir/include/mlir/Dialect/MPI/IR/MPIOps.td @@ -96,6 +96,7 @@ def MPI_CommSizeOp : MPI_Op<"comm_size", [Pure]> { ); let assemblyFormat = "`(` $comm `)` attr-dict `:` type(results)"; + let hasCanonicalizer = 1; } //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/MPI/IR/Utils.h b/mlir/include/mlir/Dialect/MPI/IR/Utils.h new file mode 100644 index 0000000000000..76ff4841d89bc --- /dev/null +++ b/mlir/include/mlir/Dialect/MPI/IR/Utils.h @@ -0,0 +1,44 @@ +//===- Utils.h - MPI dialect --------------------------------------*- C++-*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifndef MLIR_DIALECT_MPI_IR_UTILS_H_ +#define MLIR_DIALECT_MPI_IR_UTILS_H_ + +#include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/DLTI/DLTI.h" +#include "mlir/Dialect/MPI/IR/MPI.h" +#include "mlir/IR/PatternMatch.h" + +namespace mlir { +namespace mpi { +template +LogicalResult FoldToDLTIConst(OpT op, const char *key, + mlir::PatternRewriter &b) { + auto comm = op.getComm(); + if (!comm.template getDefiningOp()) + return mlir::failure(); + + // Try to get DLTI attribute for MPI:comm_world_rank + // If found, set worldRank to the value of the attribute. + auto dltiAttr = dlti::query(op, {key}, false); + if (failed(dltiAttr)) + return mlir::failure(); + if (!isa(dltiAttr.value())) + return op->emitError() << "Expected an integer attribute for " << key; + Value res = arith::ConstantOp::create( + b, op.getLoc(), b.getI32Type(), + b.getI32IntegerAttr(cast(dltiAttr.value()).getInt())); + if (Value retVal = op.getRetval()) + b.replaceOp(op, {retVal, res}); + else + b.replaceOp(op, res); + return mlir::success(); +} +} // namespace mpi +} // namespace mlir + +#endif // MLIR_DIALECT_MPI_IR_UTILS_H_ diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td index 9114d9c1f0ac1..286b07941a03c 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td @@ -23,6 +23,29 @@ include "mlir/Dialect/OpenMP/OpenMPOpBase.td" include "mlir/IR/SymbolInterfaces.td" include "mlir/IR/BuiltinAttributes.td" +//===----------------------------------------------------------------------===// +// V5.2: [12.5.1] `affinity` clause +//===----------------------------------------------------------------------===// + +class OpenMP_AffinityClauseSkip< + bit traits = false, bit arguments = false, bit assemblyFormat = false, + bit description = false, bit extraClassDeclaration = false> + : OpenMP_Clause { + let arguments = (ins Variadic:$affinity_vars); + + let optAssemblyFormat = [{ + `affinity` `(` custom($affinity_vars, type($affinity_vars)) `)` + }]; + + let description = [{ + The `affinity` clause specifies a locator list used as a hint for task + placement / scheduling affinity. + }]; +} + +def OpenMP_AffinityClause : OpenMP_AffinityClauseSkip<>; + //===----------------------------------------------------------------------===// // V5.2: [6.3] `align` clause //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td index dfec6609e1161..49a724fd5446e 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td @@ -905,9 +905,9 @@ def TaskOp traits = [AttrSizedOperandSegments, AutomaticAllocationScope, OutlineableOpenMPOpInterface], clauses = [ - // TODO: Complete clause list (affinity, detach). - OpenMP_AllocateClause, OpenMP_DependClause, - OpenMP_FinalClause, OpenMP_IfClause, + // TODO: Complete clause list (detach). + OpenMP_AffinityClause, OpenMP_AllocateClause, + OpenMP_DependClause, OpenMP_FinalClause, OpenMP_IfClause, OpenMP_InReductionClause, OpenMP_MergeableClause, OpenMP_PriorityClause, OpenMP_PrivateClause, OpenMP_UntiedClause, OpenMP_DetachClause], diff --git a/mlir/include/mlir/Dialect/SCF/IR/SCF.h b/mlir/include/mlir/Dialect/SCF/IR/SCF.h index de60ed99dd336..e754a04b0903a 100644 --- a/mlir/include/mlir/Dialect/SCF/IR/SCF.h +++ b/mlir/include/mlir/Dialect/SCF/IR/SCF.h @@ -20,7 +20,6 @@ #include "mlir/IR/RegionKindInterface.h" #include "mlir/Interfaces/ControlFlowInterfaces.h" #include "mlir/Interfaces/DestinationStyleOpInterface.h" -#include "mlir/Interfaces/ExecutionProgressOpInterface.h" #include "mlir/Interfaces/InferTypeOpInterface.h" #include "mlir/Interfaces/LoopLikeInterface.h" #include "mlir/Interfaces/ParallelCombiningOpInterface.h" diff --git a/mlir/include/mlir/Dialect/SCF/IR/SCFOps.td b/mlir/include/mlir/Dialect/SCF/IR/SCFOps.td index b259e33f1d75f..a08cf3c95e6ce 100644 --- a/mlir/include/mlir/Dialect/SCF/IR/SCFOps.td +++ b/mlir/include/mlir/Dialect/SCF/IR/SCFOps.td @@ -18,7 +18,6 @@ include "mlir/Interfaces/LoopLikeInterface.td" include "mlir/IR/RegionKindInterface.td" include "mlir/Dialect/SCF/IR/DeviceMappingInterface.td" include "mlir/Interfaces/DestinationStyleOpInterface.td" -include "mlir/Interfaces/ExecutionProgressOpInterface.td" include "mlir/Interfaces/InferTypeOpInterface.td" include "mlir/Interfaces/ParallelCombiningOpInterface.td" include "mlir/Interfaces/SideEffectInterfaces.td" @@ -41,7 +40,7 @@ def SCF_Dialect : Dialect { and then lowered to some final target like LLVM or SPIR-V. }]; - let dependentDialects = ["arith::ArithDialect", "ub::UBDialect"]; + let dependentDialects = ["arith::ArithDialect"]; } // Base class for SCF dialect ops. @@ -162,8 +161,6 @@ def ForOp : SCF_Op<"for", ConditionallySpeculatable, DeclareOpInterfaceMethods, - DeclareOpInterfaceMethods, SingleBlockImplicitTerminator<"scf::YieldOp">, RecursiveMemoryEffects]> { let summary = "for operation"; @@ -268,8 +265,7 @@ def ForOp : SCF_Op<"for", AnySignlessIntegerOrIndex:$upperBound, AnySignlessIntegerOrIndex:$step, Variadic:$initArgs, - UnitAttr:$unsignedCmp, - DefaultValuedAttr:$mustProgress); + UnitAttr:$unsignedCmp); let results = (outs Variadic:$results); let regions = (region SizedRegion<1>:$region); @@ -990,7 +986,6 @@ def WhileOp : SCF_Op<"while", ["getEntrySuccessorOperands", "getSuccessorInputs"]>, DeclareOpInterfaceMethods, - DeclareOpInterfaceMethods, RecursiveMemoryEffects, SingleBlock]> { let summary = "a generic 'while' loop"; let description = [{ @@ -1106,18 +1101,14 @@ def WhileOp : SCF_Op<"while", ``` }]; - let arguments = (ins Variadic:$inits, - DefaultValuedAttr:$mustProgress); + let arguments = (ins Variadic:$inits); let results = (outs Variadic:$results); let regions = (region SizedRegion<1>:$before, SizedRegion<1>:$after); - let skipDefaultBuilders = 1; let builders = [ OpBuilder<(ins "TypeRange":$resultTypes, "ValueRange":$inits, "function_ref":$beforeBuilder, - "function_ref":$afterBuilder)>, - OpBuilder<(ins "TypeRange":$resultTypes, "ValueRange":$inits, - CArg<"bool", "true">:$mustProgress)> + "function_ref":$afterBuilder)> ]; let extraClassDeclaration = [{ diff --git a/mlir/include/mlir/Dialect/SCF/Utils/Utils.h b/mlir/include/mlir/Dialect/SCF/Utils/Utils.h index 881125bd0da2f..c85f3b02c4a44 100644 --- a/mlir/include/mlir/Dialect/SCF/Utils/Utils.h +++ b/mlir/include/mlir/Dialect/SCF/Utils/Utils.h @@ -251,8 +251,7 @@ FailureOr parallelLoopUnrollByFactors( /// Get constant trip counts for each of the induction variables of the given /// loop operation. If any of the loop's trip counts is not constant, return an /// empty vector. -/// TODO(#178506): Should return SmallVector for correct signedness. -llvm::SmallVector +llvm::SmallVector getConstLoopTripCounts(mlir::LoopLikeOpInterface loopOp); } // namespace mlir diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td index 65771b602e0d0..e07b1ffd92f07 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td @@ -238,8 +238,8 @@ def SPIRV_FRemOp : SPIRV_ArithmeticBinaryOp<"FRem", SPIRV_Float, []> { #### Example: ```mlir - %4 = spirv.FRemOp %0, %1 : f32 - %5 = spirv.FRemOp %2, %3 : vector<4xf32> + %4 = spirv.FRem %0, %1 : f32 + %5 = spirv.FRem %2, %3 : vector<4xf32> ``` }]; } @@ -260,8 +260,8 @@ def SPIRV_FSubOp : SPIRV_ArithmeticBinaryOpWithCoopMatrix<"FSub", SPIRV_Float, [ #### Example: ```mlir - %4 = spirv.FRemOp %0, %1 : f32 - %5 = spirv.FRemOp %2, %3 : vector<4xf32> + %4 = spirv.FSub %0, %1 : f32 + %5 = spirv.FSub %2, %3 : vector<4xf32> ``` }]; } diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td index 88f902110b861..202fa0ad60d2f 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td @@ -443,8 +443,8 @@ def SPIRV_AtomicIIncrementOp : SPIRV_AtomicUpdateOp<"AtomicIIncrement", []> { #### Example: ```mlir - %0 = spirv.AtomicIncrement %pointer : - !spirv.ptr + %0 = spirv.AtomicIIncrement %pointer : + !spirv.ptr ``` }]; } diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td index 8b9f51d38374c..2f189c64300ae 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td @@ -360,6 +360,7 @@ def SPV_EXT_shader_image_int64 : I32EnumAttrCase<"SPV_EXT_shader_image def SPV_EXT_shader_atomic_float16_add : I32EnumAttrCase<"SPV_EXT_shader_atomic_float16_add", 1011>; def SPV_EXT_mesh_shader : I32EnumAttrCase<"SPV_EXT_mesh_shader", 1012>; def SPV_EXT_replicated_composites : I32EnumAttrCase<"SPV_EXT_replicated_composites", 1013>; +def SPV_EXT_float8 : I32EnumAttrCase<"SPV_EXT_float8", 1014>; def SPV_AMD_gpu_shader_half_float_fetch : I32EnumAttrCase<"SPV_AMD_gpu_shader_half_float_fetch", 2000>; def SPV_AMD_shader_ballot : I32EnumAttrCase<"SPV_AMD_shader_ballot", 2001>; @@ -449,7 +450,7 @@ def SPIRV_ExtensionAttr : SPV_EXT_shader_stencil_export, SPV_EXT_shader_viewport_index_layer, SPV_EXT_shader_atomic_float_add, SPV_EXT_shader_atomic_float_min_max, SPV_EXT_shader_image_int64, SPV_EXT_shader_atomic_float16_add, - SPV_EXT_mesh_shader, SPV_EXT_replicated_composites, + SPV_EXT_mesh_shader, SPV_EXT_replicated_composites, SPV_EXT_float8, SPV_ARM_tensors, SPV_ARM_graph, SPV_AMD_gpu_shader_half_float_fetch, SPV_AMD_shader_ballot, SPV_AMD_shader_explicit_vertex_parameter, SPV_AMD_shader_fragment_mask, @@ -1486,6 +1487,12 @@ def SPIRV_C_CacheControlsINTEL : I32EnumAttrCase<"CacheControlsINTEL", 6441> { ]; } +def SPIRV_C_Float8EXT : I32EnumAttrCase<"Float8EXT", 4212> { + list availability = [ + Extension<[SPV_EXT_float8]> + ]; +} + def SPIRV_CapabilityAttr : SPIRV_I32EnumAttr<"Capability", "valid SPIR-V Capability", "capability", [ SPIRV_C_Matrix, SPIRV_C_Addresses, SPIRV_C_Linkage, SPIRV_C_Kernel, SPIRV_C_Float16, @@ -1583,7 +1590,7 @@ def SPIRV_CapabilityAttr : SPIRV_C_ShaderStereoViewNV, SPIRV_C_Bfloat16ConversionINTEL, SPIRV_C_CacheControlsINTEL, SPIRV_C_BFloat16TypeKHR, SPIRV_C_BFloat16DotProductKHR, SPIRV_C_BFloat16CooperativeMatrixKHR, - SPIRV_C_TensorFloat32RoundingINTEL + SPIRV_C_TensorFloat32RoundingINTEL, SPIRV_C_Float8EXT ]>; def SPIRV_AM_Logical : I32EnumAttrCase<"Logical", 0>; @@ -3287,9 +3294,24 @@ def SPIRV_FPE_BFloat16KHR : I32EnumAttrCase<"BFloat16KHR", 0> { Capability<[SPIRV_C_BFloat16TypeKHR]> ]; } + +def SPIRV_FPE_Float8E4M3EXT : I32EnumAttrCase<"Float8E4M3EXT", 4214> { + list availability = [ + Capability<[SPIRV_C_Float8EXT]> + ]; +} + +def SPIRV_FPE_Float8E5M2EXT : I32EnumAttrCase<"Float8E5M2EXT", 4215> { + list availability = [ + Capability<[SPIRV_C_Float8EXT]> + ]; +} + def SPIRV_FPEncodingAttr : SPIRV_I32EnumAttr<"FPEncoding", "valid SPIR-V FPEncoding", "f_p_encoding", [ - SPIRV_FPE_BFloat16KHR + SPIRV_FPE_BFloat16KHR, + SPIRV_FPE_Float8E4M3EXT, + SPIRV_FPE_Float8E5M2EXT, ]>; def SPIRV_FC_None : I32BitEnumAttrCaseNone<"None">; @@ -4248,9 +4270,11 @@ def SPIRV_Int32 : TypeAlias; def SPIRV_Float16 : TypeAlias; def SPIRV_Float32 : TypeAlias; def SPIRV_BFloat16KHR : TypeAlias; +def SPIRV_Float8E4M3EXT : TypeAlias; +def SPIRV_Float8E5M2EXT : TypeAlias; def SPIRV_Float : FloatOfWidths<[16, 32, 64]>; def SPIRV_Float16or32 : FloatOfWidths<[16, 32]>; -def SPIRV_AnyFloat : AnyTypeOf<[SPIRV_Float, SPIRV_BFloat16KHR]>; +def SPIRV_AnyFloat : AnyTypeOf<[SPIRV_Float, SPIRV_BFloat16KHR, SPIRV_Float8E4M3EXT, SPIRV_Float8E5M2EXT]>; def SPIRV_Vector : VectorOfRankAndLengthAndType<[1], [2, 3, 4, 8, 16], [SPIRV_Bool, SPIRV_Integer, SPIRV_AnyFloat]>; // Component type check is done in the type parser for the following SPIR-V diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td index a5c8aa8fb450c..f05030dfb5d57 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCastOps.td @@ -212,8 +212,8 @@ def SPIRV_FConvertOp : SPIRV_CastOp<"FConvert", #### Example: ```mlir - %1 = spirv.FConvertOp %0 : f32 to f64 - %3 = spirv.FConvertOp %2 : vector<3xf32> to vector<3xf64> + %1 = spirv.FConvert %0 : f32 to f64 + %3 = spirv.FConvert %2 : vector<3xf32> to vector<3xf64> ``` }]; } @@ -240,8 +240,8 @@ def SPIRV_SConvertOp : SPIRV_CastOp<"SConvert", #### Example: ```mlir - %1 = spirv.SConvertOp %0 : i32 to i64 - %3 = spirv.SConvertOp %2 : vector<3xi32> to vector<3xi64> + %1 = spirv.SConvert %0 : i32 to i64 + %3 = spirv.SConvert %2 : vector<3xi32> to vector<3xi64> ``` }]; } @@ -269,8 +269,8 @@ def SPIRV_UConvertOp : SPIRV_CastOp<"UConvert", #### Example: ```mlir - %1 = spirv.UConvertOp %0 : i32 to i64 - %3 = spirv.UConvertOp %2 : vector<3xi32> to vector<3xi64> + %1 = spirv.UConvert %0 : i32 to i64 + %3 = spirv.UConvert %2 : vector<3xi32> to vector<3xi64> ``` }]; } @@ -390,7 +390,7 @@ def SPIRV_PtrCastToGenericOp : SPIRV_Op<"PtrCastToGeneric", [Pure]> { #### Example: ```mlir - %1 = spirv.PtrCastToGenericOp %0 : !spirv.ptr to + %1 = spirv.PtrCastToGeneric %0 : !spirv.ptr to !spirv.ptr ``` }]; @@ -433,8 +433,8 @@ def SPIRV_GenericCastToPtrOp : SPIRV_Op<"GenericCastToPtr", [Pure]> { #### Example: ```mlir - %1 = spirv.GenericCastToPtrOp %0 : !spirv.ptr to - !spirv.ptr + %1 = spirv.GenericCastToPtr %0 : !spirv.ptr to + !spirv.ptr ``` }]; @@ -482,8 +482,8 @@ def SPIRV_GenericCastToPtrExplicitOp : SPIRV_Op<"GenericCastToPtrExplicit", [Pur #### Example: ```mlir - %1 = spirv.GenericCastToPtrExplicitOp %0 : !spirv.ptr to - !spirv.ptr + %1 = spirv.GenericCastToPtrExplicit %0 : !spirv.ptr to + !spirv.ptr ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td index 269db1b61c7ad..981131484498d 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCompositeOps.td @@ -255,7 +255,7 @@ def SPIRV_VectorInsertDynamicOp : SPIRV_Op<"VectorInsertDynamic", [ ```mlir %scalar = ... : f32 - %2 = spirv.VectorInsertDynamic %scalar %0[%1] : f32, vector<8xf32>, i32 + %2 = spirv.VectorInsertDynamic %scalar, %0[%1] : vector<8xf32>, i32 ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td index a8743b196bfe7..400e37432f388 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGroupOps.td @@ -104,8 +104,8 @@ def SPIRV_GroupBroadcastOp : SPIRV_Op<"GroupBroadcast", %vector_value = ... : vector<4xf32> %scalar_localid = ... : i32 %vector_localid = ... : vector<3xi32> - %0 = spirv.GroupBroadcast "Subgroup" %scalar_value, %scalar_localid : f32, i32 - %1 = spirv.GroupBroadcast "Workgroup" %vector_value, %vector_localid : + %0 = spirv.GroupBroadcast %scalar_value, %scalar_localid : f32, i32 + %1 = spirv.GroupBroadcast %vector_value, %vector_localid : vector<4xf32>, vector<3xi32> ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td index 37df66372f51c..784eb40141b74 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVNonUniformOps.td @@ -239,8 +239,8 @@ def SPIRV_GroupNonUniformBroadcastOp : SPIRV_Op<"GroupNonUniformBroadcast", %scalar_value = ... : f32 %vector_value = ... : vector<4xf32> %id = ... : i32 - %0 = spirv.GroupNonUniformBroadcast "Subgroup" %scalar_value, %id : f32, i32 - %1 = spirv.GroupNonUniformBroadcast "Workgroup" %vector_value, %id : + %0 = spirv.GroupNonUniformBroadcast %scalar_value, %id : f32, i32 + %1 = spirv.GroupNonUniformBroadcast %vector_value, %id : vector<4xf32>, i32 ``` }]; @@ -283,7 +283,7 @@ def SPIRV_GroupNonUniformElectOp : SPIRV_Op<"GroupNonUniformElect", []> { #### Example: ```mlir - %0 = spirv.GroupNonUniformElect : i1 + %0 = spirv.GroupNonUniformElect : i1 ``` }]; @@ -1406,7 +1406,7 @@ def SPIRV_GroupNonUniformRotateKHROp : SPIRV_Op<"GroupNonUniformRotateKHR", [ %four = spirv.Constant 4 : i32 %0 = spirv.GroupNonUniformRotateKHR %value, %delta : f32, i32 -> f32 %1 = spirv.GroupNonUniformRotateKHR %value, %delta, - clustersize(%four) : f32, i32, i32 -> f32 + cluster_size(%four) : f32, i32, i32 -> f32 ``` }]; @@ -1462,7 +1462,7 @@ def SPIRV_GroupNonUniformAllOp : SPIRV_Op<"GroupNonUniformAll", [ ```mlir %predicate = ... : i1 - %0 = spirv.GroupNonUniformAll "Subgroup" %predicate : i1 + %0 = spirv.GroupNonUniformAll %predicate : i1 ``` }]; @@ -1518,7 +1518,7 @@ def SPIRV_GroupNonUniformAnyOp : SPIRV_Op<"GroupNonUniformAny", [ ```mlir %predicate = ... : i1 - %0 = spirv.GroupNonUniformAny "Subgroup" %predicate : i1 + %0 = spirv.GroupNonUniformAny %predicate : i1 ``` }]; diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td index 82d3ce1dcaeb4..9959f0bec781e 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td @@ -437,7 +437,7 @@ def SPIRV_GlobalVariableOp : SPIRV_Op<"GlobalVariable", [InModuleScope, Symbol]> #### Example: ```mlir - spirv.GlobalVariable @var0 : !spirv.ptr @var0 + spirv.GlobalVariable @var0 : !spirv.ptr spirv.GlobalVariable @var1 initializer(@var0) : !spirv.ptr spirv.GlobalVariable @var2 bind(1, 2) : !spirv.ptr spirv.GlobalVariable @var3 built_in("GlobalInvocationId") : !spirv.ptr, Input> diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td index d69e215e05205..61e8ea2c9ebc8 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td @@ -524,8 +524,7 @@ def SPIRV_TosaMaxPool2DOp : SPIRV_TosaOpWithResult<"MaxPool2D", 7, [Pure, let description = [{ Performs a max pooling over the given input tensor. A sliding window of size given by is passed over the input tensor, with the - maximum value being placed in the - output tensor. + maximum value being placed in the output tensor. References: * https://github.khronos.org/SPIRV-Registry/extended/TOSA.001000.1.html#_max_pool2d @@ -574,7 +573,7 @@ def SPIRV_TosaRFFT2DOp : SPIRV_TosaOpWithComplexResult<"RFFT2D", 8, [Pure]> { Performs a batched 2D real-valued Fast Fourier Transform over the input where the input tensor consists of real values producing complex valued output. The complex output values will be split into the output_real and output_imag - tensor arguments. RFFT2D takes advantage of Hermitian symmetry to only + tensor arguments. This operator takes advantage of Hermitian symmetry to only calculate the first half of the final output axis. Implementations may choose to skip calculation of the imaginary values at (0,0), (0,W/2), (H/2,0), and (H/2, W/2). If the calculation is skipped, the result at that location must be @@ -694,4 +693,174 @@ def SPIRV_TosaTransposeConv2DOp : SPIRV_TosaOpWithResult<"TransposeConv2D", 9, [ } +def SPIRV_TosaClampOp : SPIRV_TosaOpWithResult<"Clamp", 10, [Pure, + AllTypesMatch<["input", "output"]>, + AllElementTypesMatch<["input", "output", "min_val", "max_val"]>]> { + let summary = "Computes Clamp(min, max)."; + + let description = [{ + Clamp to an arbitrary minimum and maximum value. + Maximum and minimum values are specified as values in the range of the + input type. + No zero point subtraction is done to the values, thus to clamp to the zero + point value, the zero point itself should be supplied as the minimum value. + + References: + * https://github.khronos.org/SPIRV-Registry/extended/TOSA.001000.1.html#_clamp + * https://www.mlplatform.org/tosa/tosa_spec_1_0_1.html#_clamp + + #### Example: + ```mlir + %3 = spirv.Tosa.Clamp min_val = -102 : i8, max_val = -100 : i8, nan_mode = , %arg0 : !spirv.arm.tensor<27x44x55xi8> -> !spirv.arm.tensor<27x44x55xi8> + %3 = spirv.Tosa.Clamp min_val = -1.19339396E+38 : f32, max_val = 2.38255944E+38 : f32, nan_mode = , %arg0 : !spirv.arm.tensor<18x5x17x6xf32> -> !spirv.arm.tensor<18x5x17x6xf32> + ``` + }]; + + let arguments = (ins + SPIRV_TosaNumericalAttr: $min_val, + SPIRV_TosaNumericalAttr: $max_val, + SPIRV_TosaExtNaNPropagationModeAttr: $nan_mode, + SPIRV_TosaNumerical_TensorArm: $input + ); + + let results = (outs + SPIRV_TosaNumerical_TensorArm: $output + ); + + let assemblyFormat = [{ + `min_val` `=` $min_val `,` + `max_val` `=` $max_val `,` + `nan_mode` `=` $nan_mode `,` + $input + attr-dict `:` type(operands) `->` type(results) + }]; + + let extraClassDeclaration = extraBaseClassDeclaration#[{ + ::mlir::spirv::TensorArmType getInputType() { + return cast<::mlir::spirv::TensorArmType>(getInput().getType()); + } + }]; +} + + +def SPIRV_TosaErfOp : SPIRV_TosaOpWithResult<"Erf", 11, [Pure, + AllTypesMatch<["input", "output"]>]> { + let summary = "Gauss Error Function."; + + let description = [{ + Gauss Error Function: $ erf(x) = \frac{2}{\sqrt{\pi}} \int_{0}^{x} e^{-t^2} dt $ + For quantized integer data types, the `spirv.Tosa.Table` operator should be used instead. + + References: + * https://github.khronos.org/SPIRV-Registry/extended/TOSA.001000.1.html#_erf + * https://www.mlplatform.org/tosa/tosa_spec_1_0_1.html#_erf + + #### Example: + ```mlir + %0 = spirv.Tosa.Erf %arg0 : !spirv.arm.tensor<47x38x51xf32> -> !spirv.arm.tensor<47x38x51xf32> + ``` + }]; + + let arguments = (ins + SPIRV_TosaFloat_TensorArm: $input + ); + + let results = (outs + SPIRV_TosaFloat_TensorArm: $output + ); + + let assemblyFormat = [{ + $input + attr-dict `:` type(operands) `->` type(results) + }]; + + let extraClassDeclaration = extraBaseClassDeclaration#[{ + ::mlir::spirv::TensorArmType getInputType() { + return cast<::mlir::spirv::TensorArmType>(getInput().getType()); + } + }]; +} + + +def SPIRV_TosaSigmoidOp : SPIRV_TosaOpWithResult<"Sigmoid", 12, [Pure, + AllTypesMatch<["input", "output"]>]> { + let summary = "Sigmoid operator."; + + let description = [{ + Applies the sigmoid logistic function to each element of the input tensor: + $ sigmoid(x) = \frac{1}{1 + e^{-x}} $. + + For quantized integer data types, the `spirv.Tosa.Table` operator should be used instead. + + References: + * https://github.khronos.org/SPIRV-Registry/extended/TOSA.001000.1.html#_sigmoid + * https://www.mlplatform.org/tosa/tosa_spec_1_0_1.html#_sigmoid + + #### Example: + ```mlir + %0 = spirv.Tosa.Sigmoid %arg0 : !spirv.arm.tensor<28x43x45xf32> -> !spirv.arm.tensor<28x43x45xf32> + ``` + }]; + + let arguments = (ins + SPIRV_TosaFloat_TensorArm: $input + ); + + let results = (outs + SPIRV_TosaFloat_TensorArm: $output + ); + + let assemblyFormat = [{ + $input + attr-dict `:` type(operands) `->` type(results) + }]; + + let extraClassDeclaration = extraBaseClassDeclaration#[{ + ::mlir::spirv::TensorArmType getInputType() { + return cast<::mlir::spirv::TensorArmType>(getInput().getType()); + } + }]; +} + + +def SPIRV_TosaTanhOp : SPIRV_TosaOpWithResult<"Tanh", 13, [Pure, + AllTypesMatch<["input", "output"]>]> { + let summary = "Hyperbolic Tangent operator."; + + let description = [{ + Elementwise Parameterized Hyperbolic Tangent: $ tanh(x) = \frac{1 - e^{-2x}}{1 + e^{-2x}} $. + + For quantized integer data types, the `spirv.Tosa.Table` operator should be used instead. + + References: + * https://github.khronos.org/SPIRV-Registry/extended/TOSA.001000.1.html#_tanh + * https://www.mlplatform.org/tosa/tosa_spec_1_0_1.html#_tanh + + #### Example: + ```mlir + %0 = spirv.Tosa.Tanh %arg0 : !spirv.arm.tensor<46x50x36xf16> -> !spirv.arm.tensor<46x50x36xf16> + ``` + }]; + + let arguments = (ins + SPIRV_TosaFloat_TensorArm: $input + ); + + let results = (outs + SPIRV_TosaFloat_TensorArm: $output + ); + + let assemblyFormat = [{ + $input + attr-dict `:` type(operands) `->` type(results) + }]; + + let extraClassDeclaration = extraBaseClassDeclaration#[{ + ::mlir::spirv::TensorArmType getInputType() { + return cast<::mlir::spirv::TensorArmType>(getInput().getType()); + } + }]; +} + + #endif // MLIR_DIALECT_SPIRV_IR_TOSA_OPS diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td index db4ad8064fc11..5fe3bc53618f4 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td @@ -23,6 +23,7 @@ def SPIRV_TosaAny : AnyTypeOf<[SPIRV_TosaNumerical, SPIRV_Bool]>; def SPIRV_TensorArmAxisAttr : ConfinedAttr]>; def SPIRV_BoolConstAttr : ConfinedAttr; +def SPIRV_TosaNumericalAttr: AnyAttrOf<[I8Attr, I16Attr, I32Attr, I64Attr, F16Attr, F32Attr, BF16Attr]>; // TensorARM Types @@ -44,6 +45,7 @@ def SPIRV_TosaNumerical_TensorArm4D : TensorArmRankOf<[SPIRV_TosaNumerical], [4] def SPIRV_TosaNumerical_TensorArm5D : TensorArmRankOf<[SPIRV_TosaNumerical], [5]>; def SPIRV_TosaNumerical_TensorArm : TensorArmRankOf<[SPIRV_TosaNumerical], [1, 2, 3, 4, 5, 6]>; +def SPIRV_TosaFloat_TensorArm : TensorArmRankOf<[SPIRV_TosaFloat], [1, 2, 3, 4, 5, 6]>; def SPIRV_Int32_TensorArmUpTo5D : TensorArmRankOf<[SPIRV_Int32], [1, 2, 3, 4, 5]>; class Is1DTensorArmOfLength allowedLengths> : diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h index aac5ef17370b2..2c54e95ef11b8 100644 --- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h +++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTypes.h @@ -84,9 +84,9 @@ class ScalarType : public SPIRVType { static bool classof(Type type); - /// Returns true if the given integer type is valid for the SPIR-V dialect. - static bool isValid(FloatType); /// Returns true if the given float type is valid for the SPIR-V dialect. + static bool isValid(FloatType); + /// Returns true if the given integer type is valid for the SPIR-V dialect. static bool isValid(IntegerType); }; diff --git a/mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td b/mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td index 8b10c00008865..455b5541d550f 100644 --- a/mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td +++ b/mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td @@ -1077,7 +1077,7 @@ class Tensor_ReassociativeReshapeOp traits = []> : Tensor_Op, Pure])>, - Results<(outs AnyTensor:$result)> { + Results<(outs AnyRankedTensor:$result)> { code commonExtraClassDeclaration = [{ static StringRef getReassociationAttrStrName() { return "reassociation"; } @@ -1133,7 +1133,7 @@ def Tensor_ExpandShapeOp : Tensor_ReassociativeReshapeOp<"expand_shape"> { ``` }]; - let arguments = (ins AnyTensor:$src, IndexListArrayAttr:$reassociation, + let arguments = (ins AnyRankedTensor:$src, IndexListArrayAttr:$reassociation, Variadic:$output_shape, DenseI64ArrayAttr:$static_output_shape); @@ -1191,7 +1191,7 @@ def Tensor_ExpandShapeOp : Tensor_ReassociativeReshapeOp<"expand_shape"> { def Tensor_CollapseShapeOp : Tensor_ReassociativeReshapeOp<"collapse_shape"> { let summary = "operation to produce a tensor with a smaller rank"; - let arguments = (ins AnyTensor:$src, IndexListArrayAttr:$reassociation); + let arguments = (ins AnyRankedTensor:$src, IndexListArrayAttr:$reassociation); let description = [{ The `tensor.collapse_shape` op produces a new tensor of lower (or equal) rank whose dimension sizes are a reassociation of the original `src` dimensions. diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc index 009775293a987..a4eb3dd12bd54 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc @@ -371,7 +371,10 @@ profileComplianceMap = { {{i32T, i32T, i32T}, SpecificationVersion::V_1_0}}}, {{Profile::pro_fp}, {{{fp16T, i32T, fp16T}, SpecificationVersion::V_1_0}, - {{fp32T, i32T, fp32T}, SpecificationVersion::V_1_0}}}}}, + {{fp32T, i32T, fp32T}, SpecificationVersion::V_1_0}}}, + {{Profile::pro_fp, Profile::pro_int}, + {{{boolT, i32T, boolT}, SpecificationVersion::V_1_1_DRAFT}}, + anyOf}}}, {"tosa.scatter", {{{Profile::pro_int}, {{{i8T, i32T, i8T, i8T}, SpecificationVersion::V_1_0}, @@ -379,7 +382,12 @@ profileComplianceMap = { {{i32T, i32T, i32T, i32T}, SpecificationVersion::V_1_0}}}, {{Profile::pro_fp}, {{{fp16T, i32T, fp16T, fp16T}, SpecificationVersion::V_1_0}, - {{fp32T, i32T, fp32T, fp32T}, SpecificationVersion::V_1_0}}}}}, + {{fp32T, i32T, fp32T, fp32T}, SpecificationVersion::V_1_0}}}, + {{Profile::pro_fp, Profile::pro_int}, + { + {{boolT, i32T, boolT, boolT}, SpecificationVersion::V_1_1_DRAFT}, + }, + anyOf}}}, {"tosa.resize", {{{Profile::pro_int}, {{{i8T, i32T}, SpecificationVersion::V_1_0}, @@ -402,7 +410,8 @@ profileComplianceMap = { {{i32T, i8T}, SpecificationVersion::V_1_0}, {{i32T, i16T}, SpecificationVersion::V_1_0}}}, {{Profile::pro_fp}, - {{{i8T, fp16T}, SpecificationVersion::V_1_0}, + {{{boolT, fp32T}, SpecificationVersion::V_1_1_DRAFT}, + {{i8T, fp16T}, SpecificationVersion::V_1_0}, {{i8T, fp32T}, SpecificationVersion::V_1_0}, {{i16T, fp16T}, SpecificationVersion::V_1_0}, {{i16T, fp32T}, SpecificationVersion::V_1_0}, @@ -415,7 +424,8 @@ profileComplianceMap = { {{fp32T, i8T}, SpecificationVersion::V_1_0}, {{fp32T, i16T}, SpecificationVersion::V_1_0}, {{fp32T, i32T}, SpecificationVersion::V_1_0}, - {{fp32T, fp16T}, SpecificationVersion::V_1_0}}}}}, + {{fp32T, fp16T}, SpecificationVersion::V_1_0}, + {{fp32T, boolT}, SpecificationVersion::V_1_1_DRAFT}}}}}, {"tosa.rescale", {{{Profile::pro_int}, {{{i8T, i8T, i8T, i8T}, SpecificationVersion::V_1_0}, @@ -824,7 +834,8 @@ extensionComplianceMap = { {{i32T, i64T, i32T}, SpecificationVersion::V_1_1_DRAFT}, {{i64T, i64T, i64T}, SpecificationVersion::V_1_1_DRAFT}, {{fp16T, i64T, fp16T}, SpecificationVersion::V_1_1_DRAFT}, - {{fp32T, i64T, fp32T}, SpecificationVersion::V_1_1_DRAFT}}}, + {{fp32T, i64T, fp32T}, SpecificationVersion::V_1_1_DRAFT}, + {{boolT, i64T, boolT}, SpecificationVersion::V_1_1_DRAFT}}}, {{Extension::fp8e4m3, Extension::int64}, {{{fp8e4m3T, i64T, fp8e4m3T}, SpecificationVersion::V_1_1_DRAFT}}, allOf}, @@ -847,7 +858,8 @@ extensionComplianceMap = { {{i32T, i64T, i32T, i32T}, SpecificationVersion::V_1_1_DRAFT}, {{i64T, i64T, i64T, i64T}, SpecificationVersion::V_1_1_DRAFT}, {{fp16T, i64T, fp16T, fp16T}, SpecificationVersion::V_1_1_DRAFT}, - {{fp32T, i64T, fp32T, fp32T}, SpecificationVersion::V_1_1_DRAFT}}}, + {{fp32T, i64T, fp32T, fp32T}, SpecificationVersion::V_1_1_DRAFT}, + {{boolT, i64T, boolT, boolT}, SpecificationVersion::V_1_1_DRAFT}}}, {{Extension::fp8e4m3, Extension::int64}, {{{fp8e4m3T, i64T, fp8e4m3T, fp8e4m3T}, SpecificationVersion::V_1_1_DRAFT}}, @@ -876,7 +888,9 @@ extensionComplianceMap = { {{fp32T, bf16T}, SpecificationVersion::V_1_0}}}, {{Extension::int64}, {{{i32T, i64T}, SpecificationVersion::V_1_1_DRAFT}, - {{i64T, i32T}, SpecificationVersion::V_1_1_DRAFT}}}, + {{i64T, i32T}, SpecificationVersion::V_1_1_DRAFT}, + {{boolT, i64T}, SpecificationVersion::V_1_1_DRAFT}, + {{i64T, boolT}, SpecificationVersion::V_1_1_DRAFT}}}, {{Extension::bf16, Extension::fp8e4m3}, {{{bf16T, fp8e4m3T}, SpecificationVersion::V_1_0}, {{fp8e4m3T, bf16T}, SpecificationVersion::V_1_0}}, diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td b/mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td index 57fd1d2d20aa8..cbcc2a017ac3a 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td @@ -159,6 +159,8 @@ def Tosa_DivCeilShapeOp : Tosa_ElementwiseShapeOp<"div_ceil_shape", [Pure]> { ); let results = (outs Tosa_Shape:$output); + + let hasFolder = 1; } //===----------------------------------------------------------------------===// @@ -177,6 +179,8 @@ def Tosa_DivFloorShapeOp : Tosa_ElementwiseShapeOp<"div_floor_shape", [Pure]> { ); let results = (outs Tosa_Shape:$output); + + let hasFolder = 1; } //===----------------------------------------------------------------------===// @@ -246,6 +250,8 @@ def Tosa_MaxShapeOp : Tosa_ElementwiseShapeOp<"max_shape", [Pure]> { ); let results = (outs Tosa_Shape:$output); + + let hasFolder = 1; } //===----------------------------------------------------------------------===// @@ -264,6 +270,8 @@ def Tosa_MinShapeOp : Tosa_ElementwiseShapeOp<"min_shape", [Pure]> { ); let results = (outs Tosa_Shape:$output); + + let hasFolder = 1; } //===----------------------------------------------------------------------===// @@ -282,6 +290,8 @@ def Tosa_ModShapeOp : Tosa_ElementwiseShapeOp<"mod_shape", [Pure]> { ); let results = (outs Tosa_Shape:$output); + + let hasFolder = 1; } //===----------------------------------------------------------------------===// @@ -300,6 +310,8 @@ def Tosa_MulShapeOp : Tosa_ElementwiseShapeOp<"mul_shape", [Pure]> { ); let results = (outs Tosa_Shape:$output); + + let hasFolder = 1; } //===----------------------------------------------------------------------===// @@ -339,6 +351,8 @@ def Tosa_SubShapeOp : Tosa_ElementwiseShapeOp<"sub_shape", [Pure]> { ); let results = (outs Tosa_Shape:$output); + + let hasFolder = 1; } //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/UB/IR/UBOps.h b/mlir/include/mlir/Dialect/UB/IR/UBOps.h index 281bd3ed4e805..21de5cb0c182a 100644 --- a/mlir/include/mlir/Dialect/UB/IR/UBOps.h +++ b/mlir/include/mlir/Dialect/UB/IR/UBOps.h @@ -12,7 +12,6 @@ #include "mlir/Bytecode/BytecodeOpInterface.h" #include "mlir/IR/Dialect.h" #include "mlir/IR/OpImplementation.h" -#include "mlir/IR/PatternMatch.h" #include "mlir/Interfaces/SideEffectInterfaces.h" #include "mlir/Dialect/UB/IR/UBOpsInterfaces.h.inc" @@ -25,13 +24,4 @@ #include "mlir/Dialect/UB/IR/UBOpsDialect.h.inc" -namespace mlir::ub { -/// Populate a canonicalization pattern that erases "must progress" region -/// branch ops that loop infinitely and replaces their results with poison -/// values. -void populateEraseInfiniteRegionBranchLoopPattern(RewritePatternSet &patterns, - StringRef opName, - PatternBenefit benefit = 1); -} // namespace mlir::ub - #endif // MLIR_DIALECT_UB_IR_OPS_H diff --git a/mlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h b/mlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h index 64c125024d906..525663e5cd6c5 100644 --- a/mlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h +++ b/mlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h @@ -332,11 +332,13 @@ struct ComposeCollapseOfExpandOp : public OpRewritePattern { // the first dynamic size. Value result = dynamicSizes[0]; for (Value v : llvm::drop_begin(dynamicSizes)) - result = arith::MulIOp::create(rewriter, loc, result, v); + result = arith::MulIOp::create(rewriter, loc, result, v, + arith::IntegerOverflowFlags::nsw); if (numStaticElems != 1) { result = arith::MulIOp::create( rewriter, loc, result, - arith::ConstantIndexOp::create(rewriter, loc, numStaticElems)); + arith::ConstantIndexOp::create(rewriter, loc, numStaticElems), + arith::IntegerOverflowFlags::nsw); } newOutputShape.push_back(result); } @@ -370,7 +372,8 @@ struct ComposeExpandOfCollapseOp : public OpRewritePattern { if (hasNonIdentityLayout(expandOp.getSrc().getType()) || hasNonIdentityLayout(collapseOp.getSrc().getType()) || hasNonIdentityLayout(collapseOp.getResult().getType())) { - if (CastOpTy::areCastCompatible(srcType, resultType)) { + if (srcType.hasStaticShape() && + CastOpTy::areCastCompatible(srcType, resultType)) { rewriter.replaceOpWithNewOp(expandOp, resultType, collapseOp.getSrc()); return success(); diff --git a/mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td b/mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td index 03d25505dc65c..c9668fe30e648 100644 --- a/mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td +++ b/mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td @@ -539,4 +539,22 @@ def ApplySinkVectorMemPatternsOp : Op]> { + let description = [{ + Collect patterns to rewrite contiguous row-major vector.transfer_read or + vector.transfer_write operations to a 1D operation. + }]; + + let arguments = (ins + DefaultValuedAttr::max()">:$target_vector_bitwidth + ); + + let assemblyFormat = [{ + (`target_vector_bitwidth` `=` $target_vector_bitwidth^)? attr-dict + }]; +} + #endif // VECTOR_TRANSFORM_OPS diff --git a/mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h b/mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h index 7bd96c8a6d1a1..efa3c6d8ac238 100644 --- a/mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h +++ b/mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h @@ -42,7 +42,7 @@ namespace vector { /// /// [ContractionOpToDotLowering] /// Progressively lower a `vector.contract` with row-major matmul semantics to -/// linearized `vector.extract` + `vector.reduce` + `vector.insert`. +/// linearized `vector.extract` + `vector.reduction` + `vector.insert`. /// /// [ContractionOpToOuterProductOpLowering] /// Progressively lower a `vector.contract` with row-major matmul semantics to diff --git a/mlir/include/mlir/Dialect/X86Vector/X86Vector.td b/mlir/include/mlir/Dialect/X86Vector/X86Vector.td index 468242d1c2780..cd16a36a6ee0b 100644 --- a/mlir/include/mlir/Dialect/X86Vector/X86Vector.td +++ b/mlir/include/mlir/Dialect/X86Vector/X86Vector.td @@ -343,6 +343,58 @@ def CvtPackedF32ToBF16Op : AVX512_Op<"cvt.packed.f32_to_bf16", [Pure, }]; } +//===----------------------------------------------------------------------===// +// AVX10 op definitions +//===----------------------------------------------------------------------===// + +// Operation that is part of the input dialect. +class AVX10_Op traits = []> : + Op {} + +//----------------------------------------------------------------------------// +// AVX10 Int8 Dot +//----------------------------------------------------------------------------// + +def AVX10DotInt8Op : AVX10_Op<"dot.i8", [Pure, + X86IntrinsicOpInterface, + AllTypesMatch<["a", "b"]>, + AllTypesMatch<["w", "dst"]>, + TypesMatchWith<"`a` has four times elements as `w`", + "w", "a", + "VectorType::get({::llvm::cast($_self).getShape()[0] * 4}, " + "IntegerType::get($_self.getContext(), 8))"> + ]> { + let summary = "AVX10 Dot Int8 op"; + let description = [{ + The `dot` op is an AVX10-Int8 specific op that can lower to the proper + LLVMAVX10-INT8 operation `llvm.vpdpbssd.512`. + + Multiply groups of 4 adjacent pairs of signed 8-bit integers in `a` with + corresponding signed 8-bit integers in `b`, producing 4 intermediate signed 16-bit + results. Sum these 4 results with the corresponding 32-bit integer in `w`, and + store the packed 32-bit results in `dst`. + + Example: + ```mlir + %dst = x86vector.avx10.dot.i8 %w, %a, %b : vector<64xi8> -> vector<16xi32> + ``` + }]; + let arguments = (ins VectorOfLengthAndType<[16], [I32]>:$w, + VectorOfLengthAndType<[64], [I8]>:$a, + VectorOfLengthAndType<[64], [I8]>:$b + ); + let results = (outs VectorOfLengthAndType<[16], [I32]>:$dst); + let assemblyFormat = + "$w `,` $a `,` $b attr-dict `:` type($a) `->` type($w)"; + + let extraClassDeclaration = [{ + std::string getIntrinsicName() { + return "llvm.x86.avx10.vpdpbssd.512"; + } + }]; +} + + //===----------------------------------------------------------------------===// // AVX op definitions //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td index c146105c6b826..898fb7e1d8e6d 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td @@ -226,16 +226,31 @@ def DistributeLayoutAttr: AttrInterface<"DistributeLayoutAttr"> { InterfaceMethod<"Derive a new layout with sg_data, inst_data and lane_data set to 1 for the specified unit dims", "xegpu::DistributeLayoutAttr", "setUnitDimData", - /*args=*/(ins "const llvm::SetVector": $unitDims)>, + /*args=*/(ins "const SmallVector": $unitDims)>, InterfaceMethod<"Derive a new layout with sg_lane and lane_layout set to 1 for the specified unit dims", "xegpu::DistributeLayoutAttr", "setUnitDimLayout", - /*args=*/(ins "const llvm::SetVector": $unitDims)>, + /*args=*/(ins "const SmallVector": $unitDims)>, InterfaceMethod<[{Delinearizes a linear ID into its multidimensional indices based on the effective layout level.}], "FailureOr>", "delinearizeId", (ins "OpBuilder &": $builder, "Location":$loc, "Value":$linearId)>, + InterfaceMethod<[{Derive a new layout with sg_data, inst_data and lane_data set to the + specified values for the given dimension. Passing -1 for any parameter + preserves its original value.}], + "xegpu::DistributeLayoutAttr", + "setDimData", + (ins "int64_t": $dim, + "int64_t": $sgData, + "int64_t": $instData, + "int64_t": $laneData)>, + InterfaceMethod<[{Derive a new layout by collapsing dimensions. + `dimGroup` specifies a group of adjacent dimensions that are collapsed into + a single dimension in the derived layout.}], + "xegpu::DistributeLayoutAttr", + "collapseDims", + (ins "SmallVector": $dimGroup)>, InterfaceMethod<[{Generates instructions to compute multidimensional coordinates for dist units assigned to a level identified by linearId. The shape parameter represents the higher-level problem size. Each level may access @@ -501,10 +516,20 @@ def XeGPU_LayoutAttr : XeGPUAttr<"Layout", "layout", [DistributeLayoutAttr]> { } //set the layout for the sepcified unit dims: sg_data, inst_data and lane_data to 1 - DistributeLayoutAttr setUnitDimData(SetVector unitDims) const; + DistributeLayoutAttr setUnitDimData(SmallVector unitDims) const; //set the layout for the sepcified unit dims: sg_lane and lane_layout to 1 - DistributeLayoutAttr setUnitDimLayout(SetVector unitDims) const; + DistributeLayoutAttr setUnitDimLayout(SmallVector unitDims) const; + + // Derive a new layout with sg_data, inst_data and lane_data set to the + // specified values for the given dimension. Passing -1 for any parameter + // preserves its original value. + DistributeLayoutAttr setDimData(int64_t dim, int64_t sgData, int64_t instData, int64_t laneData); + + // Derive a new layout by collapsing dimensions. + // `dimGroup` specifies a group of adjacent dimensions + // that are collapsed into a single dimension in the derived layout. + DistributeLayoutAttr collapseDims(SmallVector dimGroup); /// Delinearizes a linear ID into its multidimensional indices /// based on the effective level of the layout. @@ -672,10 +697,20 @@ def XeGPU_SliceAttr : XeGPUAttr<"Slice", "slice", [DistributeLayoutAttr]> { } //set the layout for the sepcified unit dims: sg_data, inst_data and lane_data to 1 - DistributeLayoutAttr setUnitDimData(SetVector unitDims) const; + DistributeLayoutAttr setUnitDimData(SmallVector unitDims) const; //set the layout for the sepcified unit dims: sg_lane and lane_layout to 1 - DistributeLayoutAttr setUnitDimLayout(SetVector unitDims) const; + DistributeLayoutAttr setUnitDimLayout(SmallVector unitDims) const; + + // Derive a new layout with sg_data, inst_data and lane_data set to the + // specified values for the given dimension. Passing -1 for any parameter + // preserves its original value. + DistributeLayoutAttr setDimData(int64_t dim, int64_t sgData, int64_t instData, int64_t laneData); + + // Derive a new layout by collapsing dimensions. + // `dimGroup` specifies a group of adjacent dimensions + // that are collapsed into a single dimension in the derived layout. + DistributeLayoutAttr collapseDims(SmallVector dimGroup); /// flatten a nested SliceAttr, e.g., for 2-level nested SliceAttr /// #xegpu.slice<#xegpu.slice<#xegpu.layout, dims = [0]>, dims = [0]> diff --git a/mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h b/mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h index fede329990be4..ea01975da582f 100644 --- a/mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h +++ b/mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h @@ -103,12 +103,6 @@ void populateXeGPUSgToWiDistributeTypeConversionAndLegality( void populateXeGPUUnrollPatterns(RewritePatternSet &patterns, const UnrollOptions &options); -enum class LayoutKind { Lane, InstData, Subgroup }; -LogicalResult propagateLayouts(OpBuilder &builder, Operation *target, - LayoutKind layoutKind, bool printOnly = false); - -LogicalResult resolveLayoutConflicts(Operation *target); - } // namespace xegpu } // namespace mlir diff --git a/mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h b/mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h new file mode 100644 index 0000000000000..182607c22c584 --- /dev/null +++ b/mlir/include/mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h @@ -0,0 +1,168 @@ +//===- XeGPULayoutImpl.h - Layout utility functions ------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_DIALECT_XEGPU_UTILS_XeGPULayoutImpl_H_ +#define MLIR_DIALECT_XEGPU_UTILS_XeGPULayoutImpl_H_ + +#include "mlir/Dialect/XeGPU/IR/XeGPU.h" +#include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h" +#include "mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/OpDefinition.h" + +namespace mlir { + +class VectorType; +class OpOperand; +class OpResult; +class OpBuilder; +class ValueRange; +class TypeConverter; +class OpFoldResult; + +namespace xegpu { +class DistributeLayoutAttr; +class LayoutAttr; +class TensorDescType; +} // namespace xegpu + +namespace xegpu { + +enum class LayoutKind { Lane, InstData, Subgroup }; + +LogicalResult propagateLayouts(OpBuilder &builder, Operation *target, + LayoutKind layoutKind, bool printOnly = false); + +LogicalResult resolveLayoutConflicts(Operation *target); + +/// [to-be-deprecated] Set the DistributeLayoutAttr for each OpOperand and +/// OpResult of of the given operation. If the operation contains regions, it is +/// also applied recursively to the contained operations operation. +/// TODO: To be replaced by recoverTemporaryLayouts() +void recoverTemporaryLayoutsDeprecated(Operation *op); + +/// Attach layout attributes to all vector-type operands of operations within +/// the given operation's nested region. Reports an error if any vector operand +/// lacks a layout attribute. +bool recoverTemporaryLayouts(Operation *rootOp); + +/// Removes the LayoutAttr for a given OpOperand or OpResult if it exists. +template || + std::is_same_v>> +void removeLayoutAttr(const T &operandOrResult); + +/// Removes the DistributeLayoutAttr for each OpOperand and OpResult of the +/// given operation if they exist. If the operation contains regions, it is also +/// applied recursively to the contained operations +void removeLayoutAttrs(Operation *op); + +/// Updates the NamedAttribute sequence by dropping sg-layout and +/// sg-data information from any DistributeLayoutAttr found. +SmallVector +dropSgLayoutAndDataOnAttrs(ArrayRef attrs); + +/// Updates the NamedAttribute sequence by dropping inst-data information from +/// any DistributeLayoutAttr found. +SmallVector dropInstDataOnAttrs(ArrayRef attrs); + +/// Infers the source layout attribute for a broadcast operation given the +/// result layout attribute, result shape, and source shape. +DistributeLayoutAttr inferBroadcastSourceLayout(DistributeLayoutAttr resLayout, + ArrayRef resShape, + ArrayRef srcShape); + +/// Infers the source layout attribute for a reduction operation given the +/// result layout attribute and reduced dims. +DistributeLayoutAttr +inferMultiReductionSourceLayout(DistributeLayoutAttr resLayout, + SmallVector reduceDims); + +/// Infers the source layout attribute for a bitcast operation given the +/// result layout attribute, result element type bitwidth, and source element +/// type bitwidth. +DistributeLayoutAttr inferBitCastSourceLayout(DistributeLayoutAttr resLayout, + int resElemTyBitWidth, + int srcElemTyBitWidth); + +/// Infers the source layout attribute for a shape cast operation given the +/// result layout attribute, result shape, and source shape. +DistributeLayoutAttr inferShapeCastSourceLayout(DistributeLayoutAttr resLayout, + ArrayRef resShape, + ArrayRef srcShape); + +/// Infers the source layout attribute for an insert strided slice operation +/// given the result layout attribute, result shape, and source shape. Removes +/// leading dimensions from the result layout to match the source shape size. +DistributeLayoutAttr +inferInsertStridedSliceSourceLayout(DistributeLayoutAttr resLayout, + ArrayRef resShape, + ArrayRef srcShape); + +/// Sets up layout for reduction operations by creating a SliceAttr for the +/// result. +/// +/// This function first attempts to construct a source layout that, when +/// sliced along reduction dimensions, produces a result layout compatible +/// with the consumer's preferred layout. This minimizes data redistribution +/// overhead. The SliceAttr for the result is then created based on the +/// derived source layout and the specified reduction dimensions. +SliceAttr setupMultiReductionResultLayout(LayoutKind layoutKind, + VectorType srcVectorTy, + DistributeLayoutAttr consumerLayout, + SmallVector reductionDims, + const uArch::uArch *uArch); + +/// Setup the result layout attribute for a bitcast operation based on element +/// type bitwidths. This ensures the source layout can always be derived from +/// the result layout. +/// +/// When casting from a narrower to a wider element type (srcElemTyBitWidth < +/// resElemTyBitWidth), the result layout's innermost dimension data sizes +/// (inst_data, lane_data) are scaled up by the bitwidth ratio. This maintains +/// the invariant that the source layout can be recovered by adjusting the +/// result layout based on bitwidth ratio of input vs output. +DistributeLayoutAttr setupBitCastResultLayout( + LayoutKind layoutKind, VectorType srcVectorTy, VectorType resVectorTy, + DistributeLayoutAttr consumerLayout, const uArch::uArch *uArch); + +/// Sets up the result layout for an insert strided slice operation. +/// Creates a result layout based on the specified layout kind (InstData or +/// Lane). +DistributeLayoutAttr setupInsertStridedSliceResultLayout( + LayoutKind layoutKind, VectorType srcVectorTy, VectorType resVectorTy, + DistributeLayoutAttr consumerLayout, const uArch::uArch *uArch); + +/// Sets up the anchor layout for a load gather operation. +DistributeLayoutAttr +setupLoadGatherAnchorLayout(LayoutKind layoutKind, VectorType vectorTy, + int chunkSize, DistributeLayoutAttr consumerLayout, + const uArch::uArch *uArch); + +/// Sets up the anchor layout for load matrix operation. +DistributeLayoutAttr +setupLoadMatrixAnchorLayout(LayoutKind layoutKind, VectorType vectorTy, + DistributeLayoutAttr consumerLayout, + const uArch::uArch *uArch); + +/// Sets up the anchor layout for a store scatter operation. +DistributeLayoutAttr setupStoreScatterAnchorLayout(LayoutKind layoutKind, + VectorType vectorTy, + int chunkSize, + const uArch::uArch *uArch); + +/// Sets up the anchor layout for a store matrix operation. +DistributeLayoutAttr setupStoreMatrixAnchorLayout(LayoutKind layoutKind, + VectorType vectorTy, + const uArch::uArch *uArch); + +} // namespace xegpu + +} // namespace mlir + +#endif // MLIR_DIALECT_XEGPU_UTILS_XEGPUUTILS_H_ diff --git a/mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h b/mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h index 700db5f9dd9be..4443f86d1e4e2 100644 --- a/mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h +++ b/mlir/include/mlir/Dialect/XeGPU/Utils/XeGPUUtils.h @@ -137,12 +137,6 @@ template int getLargestDivisor(T dim, ArrayRef candidates, ArrayRef candidateMultiples = {}); -/// Return the attribute name for the OpOperand to attach DistributeLayoutAttr -std::string getTemporaryLayoutName(const OpOperand &operand); - -/// Return the attribute name for the OpResult to attach DistributeLayoutAttr -std::string getTemporaryLayoutName(const OpResult result); - /// Retrieves the DistributeLayoutAttr associated with a given Value. For /// TensorDescType values, the DistributeLayoutAttr is extracted from the /// TensorDescType itself. For other values, it is obtained from the attributes @@ -155,26 +149,6 @@ DistributeLayoutAttr getDistributeLayoutAttr(const Value value); /// found, it will check the operand itself and its defining op. DistributeLayoutAttr getDistributeLayoutAttr(const OpOperand &opr); -/// Removes the LayoutAttr for a given OpOperand or OpResult if it exists. -template || - std::is_same_v>> -void removeLayoutAttr(const T &operandOrResult); - -/// Removes the DistributeLayoutAttr for each OpOperand and OpResult of the -/// given operation if they exist. If the operation contains regions, it is also -/// applied recursively to the contained operations -void removeLayoutAttrs(Operation *op); - -/// Updates the NamedAttribute sequence by dropping sg-layout and -/// sg-data information from any DistributeLayoutAttr found. -SmallVector -dropSgLayoutAndDataOnAttrs(ArrayRef attrs); - -/// Updates the NamedAttribute sequence by dropping inst-data information from -/// any DistributeLayoutAttr found. -SmallVector dropInstDataOnAttrs(ArrayRef attrs); - /// [to-be-deprecated] Sets the DistributeLayoutAttr for a given OpResult /// user should use setAnchorLayout instead void setDistributeLayoutAttr(const OpResult &Result, @@ -185,6 +159,12 @@ void setDistributeLayoutAttr(const OpResult &Result, void setDistributeLayoutAttr(const OpOperand &opr, const DistributeLayoutAttr layout); +/// Return the attribute name for the OpOperand to attach DistributeLayoutAttr +std::string getTemporaryLayoutName(const OpOperand &operand); + +/// Return the attribute name for the OpResult to attach DistributeLayoutAttr +std::string getTemporaryLayoutName(const OpResult result); + /// get and set distribute layout attribute for non-anchor operations /// (and offsets/masks of load/store ops before we get rid of their temp attrs) template src, ArrayRef dst, + SmallVector &expandedUnitDims); + +// Checks if dst shape is an expansion of src shape where each dimension in src +// is split into one or more consecutive dimensions in dst +bool matchSplitDimExpansion(ArrayRef src, ArrayRef dst, + SmallVector> &splitDimGroups); + } // namespace xegpu } // namespace mlir diff --git a/mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h b/mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h index 29e75b57f4a5f..0341e4248767a 100644 --- a/mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h +++ b/mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h @@ -215,26 +215,20 @@ struct SubgroupMatrixMultiplyAcc : public Instruction, const unsigned packedFormatBitSizeB; }; -struct StoreScatterInstruction : public Instruction { - StoreScatterInstruction() - : Instruction(InstructionKind::StoreScatter, InstructionScope::Lane) {} - static bool classof(const Instruction *B) { - return B->getInstructionKind() == InstructionKind::StoreScatter; - } +struct SpirvLoadGatherInstruction : public LoadGatherInstructionInterface { + int32_t getMaxLaneLoadSize(int32_t bitWidth) const override { return 16; } +}; - // SPIRV restricts vector size - int32_t getMaxLaneLoadStoreSize() const { return 16; } +struct SpirvStoreScatterInstruction : public StoreScatterInstructionInterface { + int32_t getMaxLaneStoreSize(int32_t bitWidth) const override { return 16; } }; -struct LoadGatherInstruction : public Instruction { - LoadGatherInstruction() - : Instruction(InstructionKind::LoadGather, InstructionScope::Lane) {} - static bool classof(const Instruction *B) { - return B->getInstructionKind() == InstructionKind::LoadGather; - } +struct LoadMatrixInstruction : public LoadMatrixInstructionInterface { + int32_t getMaxLaneLoadSize(int32_t bitWidth) const override { return 16; } +}; - // SPIRV restricts vector size - int32_t getMaxLaneLoadStoreSize() const { return 16; } +struct StoreMatrixInstruction : public StoreMatrixInstructionInterface { + int32_t getMaxLaneStoreSize(int32_t bitWidth) const override { return 16; } }; //===----------------------------------------------------------------------===// @@ -247,11 +241,13 @@ struct PVCuArch final : public Xe2Plus { static const Subgroup2DBlockLoadInstruction loadNdInst; static const Subgroup2DBlockStoreInstruction storeNdInst; static const Subgroup2DBlockPrefetchInstruction prefetchNdInst; - static const StoreScatterInstruction storeScatterInst; - static const LoadGatherInstruction loadGatherInst; - static const Instruction *arr[] = {&dpasInst, &loadNdInst, - &storeNdInst, &prefetchNdInst, - &storeScatterInst, &loadGatherInst}; + static const SpirvStoreScatterInstruction storeScatterInst; + static const SpirvLoadGatherInstruction loadGatherInst; + static const StoreMatrixInstruction storeMatrixInst; + static const LoadMatrixInstruction loadMatrixInst; + static const Instruction *arr[] = { + &dpasInst, &loadNdInst, &storeNdInst, &prefetchNdInst, + &storeScatterInst, &loadGatherInst, &storeMatrixInst, &loadMatrixInst}; return arr; } @@ -273,8 +269,8 @@ struct BMGuArch : public Xe2Plus { static const Subgroup2DBlockLoadInstruction loadNdInst; static const Subgroup2DBlockStoreInstruction storeNdInst; static const Subgroup2DBlockPrefetchInstruction prefetchNdInst; - static const StoreScatterInstruction storeScatterInst; - static const LoadGatherInstruction loadGatherInst; + static const SpirvStoreScatterInstruction storeScatterInst; + static const SpirvLoadGatherInstruction loadGatherInst; static const Instruction *arr[] = {&dpasInst, &loadNdInst, &storeNdInst, &prefetchNdInst, &storeScatterInst, &loadGatherInst}; diff --git a/mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h b/mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h index db1984b2edb1d..0c8673e602c46 100644 --- a/mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h +++ b/mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h @@ -40,7 +40,9 @@ enum class InstructionKind { Subgroup2DBlockLoad, // Subgroup-level 2D block load instruction Subgroup2DBlockPrefetch, // Subgroup-level 2D block prefetch instruction StoreScatter, // Lane-level store (scalar, vector) - LoadGather // Lane-level load (scalar, vector) + LoadGather, // Lane-level load (scalar, vector) + StoreMatrix, // Lane-level matrix store to slm + LoadMatrix // Lane-level matrix load to slm // @TODO: Add more instructions as needed }; @@ -71,6 +73,10 @@ struct Instruction { return "store"; case InstructionKind::LoadGather: return "load"; + case InstructionKind::StoreMatrix: + return "store_matrix"; + case InstructionKind::LoadMatrix: + return "load_matrix"; } llvm_unreachable("Unknown InstructionKind"); } @@ -250,6 +256,54 @@ struct MMAInstructionInterface { virtual ~MMAInstructionInterface() = default; }; +//===----------------------------------------------------------------------===// +// Common instructions (shared across architectures) +//===----------------------------------------------------------------------===// + +struct LoadGatherInstructionInterface : public Instruction { + LoadGatherInstructionInterface() + : Instruction(InstructionKind::LoadGather, InstructionScope::Lane) {} + static bool classof(const Instruction *B) { + return B->getInstructionKind() == InstructionKind::LoadGather; + } + + virtual int32_t getMaxLaneLoadSize(int32_t bitWidth) const = 0; + virtual ~LoadGatherInstructionInterface() = default; +}; + +struct StoreScatterInstructionInterface : public Instruction { + StoreScatterInstructionInterface() + : Instruction(InstructionKind::StoreScatter, InstructionScope::Lane) {} + static bool classof(const Instruction *B) { + return B->getInstructionKind() == InstructionKind::StoreScatter; + } + + virtual int32_t getMaxLaneStoreSize(int32_t bitWidth) const = 0; + virtual ~StoreScatterInstructionInterface() = default; +}; + +struct LoadMatrixInstructionInterface : public Instruction { + LoadMatrixInstructionInterface() + : Instruction(InstructionKind::LoadMatrix, InstructionScope::Lane) {} + static bool classof(const Instruction *B) { + return B->getInstructionKind() == InstructionKind::LoadMatrix; + } + + virtual int32_t getMaxLaneLoadSize(int32_t bitWidth) const = 0; + virtual ~LoadMatrixInstructionInterface() = default; +}; + +struct StoreMatrixInstructionInterface : public Instruction { + StoreMatrixInstructionInterface() + : Instruction(InstructionKind::StoreMatrix, InstructionScope::Lane) {} + static bool classof(const Instruction *B) { + return B->getInstructionKind() == InstructionKind::StoreMatrix; + } + + virtual int32_t getMaxLaneStoreSize(int32_t bitWidth) const = 0; + virtual ~StoreMatrixInstructionInterface() = default; +}; + } // namespace uArch } // namespace xegpu } // namespace mlir diff --git a/mlir/include/mlir/IR/Builders.h b/mlir/include/mlir/IR/Builders.h index 3ba6818204ba0..a6cb1456544b9 100644 --- a/mlir/include/mlir/IR/Builders.h +++ b/mlir/include/mlir/IR/Builders.h @@ -62,6 +62,8 @@ class Builder { // Types. FloatType getF8E8M0Type(); + FloatType getF8E4M3FNType(); + FloatType getF8E5M2Type(); FloatType getBF16Type(); FloatType getF16Type(); FloatType getTF32Type(); diff --git a/mlir/include/mlir/IR/CommonAttrConstraints.td b/mlir/include/mlir/IR/CommonAttrConstraints.td index 8ac1a2ea21422..ba6cf55a8fb9e 100644 --- a/mlir/include/mlir/IR/CommonAttrConstraints.td +++ b/mlir/include/mlir/IR/CommonAttrConstraints.td @@ -334,9 +334,17 @@ class FloatAttrBase : let returnType = [{ ::llvm::APFloat }]; } +def F16Attr : FloatAttrBase; def F32Attr : FloatAttrBase; def F64Attr : FloatAttrBase; +def BF16Attr : TypedAttrBase($_self)">, + CPred<"::llvm::cast<::mlir::FloatAttr>($_self).getType().isBF16()">]>, + "16-bit bfloat attribute"> { + let returnType = [{ ::llvm::APFloat }]; +} + // An attribute backed by a string type. class StringBasedAttr : Attr { let constBuilderCall = "$_builder.getStringAttr($0)"; diff --git a/mlir/include/mlir/IR/Remarks.h b/mlir/include/mlir/IR/Remarks.h index 3102542731b33..eb0518e203d36 100644 --- a/mlir/include/mlir/IR/Remarks.h +++ b/mlir/include/mlir/IR/Remarks.h @@ -89,12 +89,13 @@ class Remark { public: Remark(RemarkKind remarkKind, DiagnosticSeverity severity, Location loc, RemarkOpts opts) - : remarkKind(remarkKind), functionName(opts.functionName), loc(loc), - categoryName(opts.categoryName), subCategoryName(opts.subCategoryName), - remarkName(opts.remarkName) { + : remarkKind(remarkKind), functionName(opts.functionName.str()), loc(loc), + categoryName(opts.categoryName.str()), + subCategoryName(opts.subCategoryName.str()), + remarkName(opts.remarkName.str()) { if (!categoryName.empty() && !subCategoryName.empty()) { (llvm::Twine(categoryName) + ":" + subCategoryName) - .toStringRef(fullCategoryName); + .toVector(fullCategoryName); } } @@ -183,21 +184,25 @@ class Remark { /// Keeps the MLIR diagnostic kind, which is used to determine the /// diagnostic kind in the LLVM remark streamer. RemarkKind remarkKind; - /// Name of the convering function like interface - StringRef functionName; + /// Name of the covering function like interface. + /// Stored as std::string to ensure the Remark owns its data. + std::string functionName; Location loc; - /// Sub category passname e.g., "Unroll" or "UnrollAndJam" - StringRef categoryName; + /// Category name e.g., "Unroll" or "UnrollAndJam". + /// Stored as std::string to ensure the Remark owns its data. + std::string categoryName; - /// Sub category name "Loop Optimizer" - StringRef subCategoryName; + /// Sub category name e.g., "Loop Optimizer". + /// Stored as std::string to ensure the Remark owns its data. + std::string subCategoryName; /// Combined name for category and sub-category SmallString<64> fullCategoryName; - /// Remark identifier - StringRef remarkName; + /// Remark identifier. + /// Stored as std::string to ensure the Remark owns its data. + std::string remarkName; /// Args collected via the streaming interface. SmallVector args; diff --git a/mlir/include/mlir/IR/Types.h b/mlir/include/mlir/IR/Types.h index 4ffdbfa5b1224..97583a93f6157 100644 --- a/mlir/include/mlir/IR/Types.h +++ b/mlir/include/mlir/IR/Types.h @@ -116,6 +116,9 @@ class Type { bool isF64() const; bool isF80() const; bool isF128() const; + bool isF8E4M3FN() const; + bool isF8E5M2() const; + /// Return true if this is an float type (with the specified width). bool isFloat() const; bool isFloat(unsigned width) const; diff --git a/mlir/include/mlir/Interfaces/CMakeLists.txt b/mlir/include/mlir/Interfaces/CMakeLists.txt index e0c75aee29c00..eb96a68861116 100644 --- a/mlir/include/mlir/Interfaces/CMakeLists.txt +++ b/mlir/include/mlir/Interfaces/CMakeLists.txt @@ -4,7 +4,6 @@ add_mlir_interface(CastInterfaces) add_mlir_interface(ControlFlowInterfaces) add_mlir_interface(DerivedAttributeOpInterface) add_mlir_interface(DestinationStyleOpInterface) -add_mlir_interface(ExecutionProgressOpInterface) add_mlir_interface(FunctionInterfaces) add_mlir_interface(IndexingMapOpInterface) add_mlir_interface(InferIntRangeInterface) diff --git a/mlir/include/mlir/Interfaces/ControlFlowInterfaces.h b/mlir/include/mlir/Interfaces/ControlFlowInterfaces.h index 33e139f6b0cea..a76dce6f2ffc5 100644 --- a/mlir/include/mlir/Interfaces/ControlFlowInterfaces.h +++ b/mlir/include/mlir/Interfaces/ControlFlowInterfaces.h @@ -314,11 +314,6 @@ Region *getEnclosingRepetitiveRegion(Operation *op); /// exists. Region *getEnclosingRepetitiveRegion(Value value); -/// Return "true" if the given region branch op is guaranteed to loop -/// infinitely. Every path starting from "parent" enters the region, but the -/// "parent" is not reachable from there. -bool isGuaranteedToLoopInfinitely(RegionBranchOpInterface op); - /// Populate canonicalization patterns that simplify successor operands/inputs /// of region branch operations. Only operations with the given name are /// matched. @@ -364,13 +359,6 @@ void populateRegionBranchOpInterfaceInliningPattern( PatternMatcherFn matcherFn = detail::defaultMatcherFn, PatternBenefit benefit = 1); -/// Return all successor regions when branching from the given region branch -/// point. This helper functions extracts all constant operand values and -/// passes them to the `RegionBranchOpInterface`. -SmallVector -getSuccessorRegionsWithAttrs(RegionBranchOpInterface op, - RegionBranchPoint point); - //===----------------------------------------------------------------------===// // ControlFlow Traits //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Interfaces/ControlFlowInterfaces.td b/mlir/include/mlir/Interfaces/ControlFlowInterfaces.td index 1dacde297efa2..8975b1235a7e3 100644 --- a/mlir/include/mlir/Interfaces/ControlFlowInterfaces.td +++ b/mlir/include/mlir/Interfaces/ControlFlowInterfaces.td @@ -350,7 +350,7 @@ def RegionBranchOpInterface : OpInterface<"RegionBranchOpInterface"> { "bool", "areTypesCompatible", (ins "::mlir::Type":$lhs, "::mlir::Type":$rhs), [{}], /*defaultImplementation=*/[{ return lhs == rhs; }] - > + >, ]; let verify = [{ diff --git a/mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.h b/mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.h deleted file mode 100644 index f1427b7e4175a..0000000000000 --- a/mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.h +++ /dev/null @@ -1,25 +0,0 @@ -//===- ExecutionProgressOpInterface.h ---------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef MLIR_INTERFACES_EXECUTIONPROGRESSOPINTERFACE_H_ -#define MLIR_INTERFACES_EXECUTIONPROGRESSOPINTERFACE_H_ - -#include "mlir/IR/OpDefinition.h" - -#include "mlir/Interfaces/ExecutionProgressOpInterface.h.inc" - -namespace mlir { -/// Return "true" if the operation must progress. Operations that do not -/// implement the ExecutionProgressOpInterface are treated conservatively: they -/// may not necessarily progress (i.e., return "false"). For ops that do -/// implement the interface, the "must progress" property is queried from the -/// interface. -bool mustProgress(Operation *op); -} // namespace mlir - -#endif // MLIR_INTERFACES_EXECUTIONPROGRESSOPINTERFACE_H_ diff --git a/mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.td b/mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.td deleted file mode 100644 index 4b7923ce3612e..0000000000000 --- a/mlir/include/mlir/Interfaces/ExecutionProgressOpInterface.td +++ /dev/null @@ -1,48 +0,0 @@ -//===- ExecutionProgressOpInterface.td - Interface Decl. -*- tablegen -*---===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This is the definition file for the ExecutionProgressOpInterface. -// -//===----------------------------------------------------------------------===// - -#ifndef MLIR_INTERFACES_EXECUTION_PROGRESS_OP_INTERFACE -#define MLIR_INTERFACES_EXECUTION_PROGRESS_OP_INTERFACE - -include "mlir/IR/OpBase.td" - -def ExecutionProgressOpInterface : OpInterface<"ExecutionProgressOpInterface"> { - let description = [{ - This interface models execution progress properties of operations. - }]; - let cppNamespace = "::mlir"; - let methods = [ - InterfaceMethod< - /*desc=*/[{ - Operations that "must progress" are required to return normally (control - flow reaches the next operation) or interact with the environment in an - observable way (e.g., volatile memory access, I/O, synchronization or - program termination). If a "must progress" op executes indefinitely - without any observable interaction, it may be erased. - - See LLVM "llvm.loop.mustprogress" / "mustprogress" function attribute - for more details. - - Operations must progress by default. - }], - /*retTy=*/"bool", - /*methodName=*/"mustProgress", - /*args=*/(ins), - /*methodBody=*/"", - /*defaultImplementation=*/[{ - return true; - }] - > - ]; -} - -#endif // MLIR_INTERFACES_EXECUTION_PROGRESS_OP_INTERFACE diff --git a/mlir/include/mlir/Target/LLVM/ROCDL/Utils.h b/mlir/include/mlir/Target/LLVM/ROCDL/Utils.h index 302ff6e7b8575..7f64f280cd507 100644 --- a/mlir/include/mlir/Target/LLVM/ROCDL/Utils.h +++ b/mlir/include/mlir/Target/LLVM/ROCDL/Utils.h @@ -49,7 +49,7 @@ assembleIsa(StringRef isa, StringRef targetTriple, StringRef chip, StringRef features, function_ref emitError); FailureOr> -linkObjectCode(ArrayRef objectCode, StringRef toolkitPath, +linkObjectCode(ArrayRef objectCode, StringRef lldPath, function_ref emitError); /// Base class for all ROCDL serializations from GPU modules into binary diff --git a/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h b/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h index 039ac8e2e1911..c67bb57985bd0 100644 --- a/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h +++ b/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h @@ -349,6 +349,32 @@ class ModuleTranslation { SymbolTableCollection &symbolTable() { return symbolTableCollection; } + // A helper callback that takes an attribute, and if it is a StringAttr, + // properly converts it to the 'no-builtin-VALUE' form. + static std::optional convertNoBuiltin(llvm::LLVMContext &ctx, + mlir::Attribute a); + + static std::optional + convertDefaultFuncAttr(llvm::LLVMContext &ctx, + mlir::NamedAttribute namedAttr); + + /// A template that takes a collection-like attribute, and converts it via a + /// user provided callback, then adds each element as function attributes to + /// the provided operation. + template + void convertFunctionAttrCollection(AttrsTy attrs, Operation *op, + const Converter &conv) { + if (!attrs) + return; + for (auto elt : attrs) { + std::optional result = conv(getLLVMContext(), elt); + if (result) + op->addFnAttr(*result); + } + } + + llvm::Attribute convertAllocsizeAttr(DenseI32ArrayAttr allocsizeAttr); + private: ModuleTranslation(Operation *module, std::unique_ptr llvmModule); diff --git a/mlir/include/mlir/Transforms/RegionUtils.h b/mlir/include/mlir/Transforms/RegionUtils.h index f78d0bfbe0725..f8db72aabefe3 100644 --- a/mlir/include/mlir/Transforms/RegionUtils.h +++ b/mlir/include/mlir/Transforms/RegionUtils.h @@ -71,11 +71,18 @@ SmallVector makeRegionIsolatedFromAbove( llvm::function_ref cloneOperationIntoRegion = [](Operation *) { return false; }); -/// Move SSA values used within an operation before an insertion point, -/// so that the operation itself (or its replacement) can be moved to -/// the insertion point. Current support is only for movement of -/// dependencies of `op` before `insertionPoint` in the same basic block. -/// Any side-effecting operations in the dependency chain pessimistically +/// Move the operation dependencies (producers) of `op` before `insertionPoint`, +/// so that `op` itself can subsequently be moved. This includes transitive +/// dependencies. Supports movement within the same block or from nested regions +/// to an outer block. +/// +/// The following conditions cause the move to fail: +/// - `insertionPoint` does not dominate `op`. +/// - Movement across an isolated-from-above region boundary. +/// - A dependency uses a block argument that wouldn't dominate +/// `insertionPoint`. +/// - `insertionPoint` is itself a dependency of `op` (cycle). +/// - Any side-effecting operations in the dependency chain pessimistically /// blocks movement. LogicalResult moveOperationDependencies(RewriterBase &rewriter, Operation *op, Operation *insertionPoint, @@ -83,11 +90,19 @@ LogicalResult moveOperationDependencies(RewriterBase &rewriter, Operation *op, LogicalResult moveOperationDependencies(RewriterBase &rewriter, Operation *op, Operation *insertionPoint); -/// Move definitions of `values` before an insertion point. Current support is -/// only for movement of definitions within the same basic block. Note that this -/// is an all-or-nothing approach. Either definitions of all values are moved -/// before insertion point, or none of them are. Any side-effecting operations -/// in the producer chain pessimistically blocks movement. +/// Move definitions of `values` (and their transitive dependencies) before +/// `insertionPoint`. Supports movement within the same block or from nested +/// regions to an outer block. +/// +/// This is all-or-nothing: either all definitions are moved, or none are. +/// +/// The following conditions cause the move to fail: +/// - Any value is a block argument (cannot be moved). +/// - Any side-effecting operations in the dependency chain. +/// - Movement across an isolated-from-above region boundary. +/// - A dependency uses a block argument that wouldn't dominate +/// `insertionPoint`. +/// - `insertionPoint` is itself a dependency (cycle). LogicalResult moveValueDefinitions(RewriterBase &rewriter, ValueRange values, Operation *insertionPoint, DominanceInfo &dominance); diff --git a/mlir/lib/Analysis/DataFlow/DeadCodeAnalysis.cpp b/mlir/lib/Analysis/DataFlow/DeadCodeAnalysis.cpp index 3ce0f94e0c6da..936b0c678f20c 100644 --- a/mlir/lib/Analysis/DataFlow/DeadCodeAnalysis.cpp +++ b/mlir/lib/Analysis/DataFlow/DeadCodeAnalysis.cpp @@ -149,6 +149,14 @@ LogicalResult DeadCodeAnalysis::initialize(Operation *top) { << OpWithFlags(top, OpPrintingFlags().skipRegions()); } + // If the top level op is a callable, we cannot identify all of its callers. + if (isa(top)) { + auto *state = getOrCreate(getProgramPointAfter(top)); + propagateIfChanged(state, state->setHasUnknownPredecessors()); + LDBG() << "[init] Marked callable root as having unknown predecessors: " + << OpWithFlags(top, OpPrintingFlags().skipRegions()); + } + // Mark as overdefined the predecessors of symbol callables with potentially // unknown predecessors. initializeSymbolCallables(top); diff --git a/mlir/lib/Bindings/Python/DialectLLVM.cpp b/mlir/lib/Bindings/Python/DialectLLVM.cpp index 0c579cf261eca..dc06d0a3bf671 100644 --- a/mlir/lib/Bindings/Python/DialectLLVM.cpp +++ b/mlir/lib/Bindings/Python/DialectLLVM.cpp @@ -20,7 +20,6 @@ namespace nb = nanobind; using namespace nanobind::literals; -using namespace llvm; using namespace mlir; using namespace mlir::python::nanobind_adaptors; @@ -135,7 +134,7 @@ struct StructType : PyConcreteType { return std::nullopt; MlirStringRef stringRef = mlirLLVMStructTypeGetIdentifier(type); - return StringRef(stringRef.data, stringRef.length).str(); + return std::string(stringRef.data, stringRef.length); }); c.def_prop_ro("body", [](const StructType &type) -> nb::object { diff --git a/mlir/lib/Bindings/Python/ExecutionEngineModule.cpp b/mlir/lib/Bindings/Python/ExecutionEngineModule.cpp index 01b7930deffd2..76dbd54ef0467 100644 --- a/mlir/lib/Bindings/Python/ExecutionEngineModule.cpp +++ b/mlir/lib/Bindings/Python/ExecutionEngineModule.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +#include + #include "mlir-c/ExecutionEngine.h" #include "mlir/Bindings/Python/IRCore.h" #include "mlir/Bindings/Python/Nanobind.h" @@ -83,7 +85,8 @@ NB_MODULE(_mlirExecutionEngine, m) { [](PyExecutionEngine &self, PyModule &module, int optLevel, const std::vector &sharedLibPaths, bool enableObjectDump, bool enablePIC) { - llvm::SmallVector libPaths; + std::vector libPaths; + libPaths.reserve(sharedLibPaths.size()); for (const std::string &path : sharedLibPaths) libPaths.push_back({path.c_str(), path.length()}); MlirExecutionEngine executionEngine = mlirExecutionEngineCreate( diff --git a/mlir/lib/Bindings/Python/Globals.cpp b/mlir/lib/Bindings/Python/Globals.cpp index 3d7ee3d30656e..d39ebfa1f518c 100644 --- a/mlir/lib/Bindings/Python/Globals.cpp +++ b/mlir/lib/Bindings/Python/Globals.cpp @@ -46,10 +46,12 @@ PyGlobals &PyGlobals::get() { return *instance; } -bool PyGlobals::loadDialectModule(llvm::StringRef dialectNamespace) { +bool PyGlobals::loadDialectModule(std::string_view dialectNamespace) { { nb::ft_lock_guard lock(mutex); - if (loadedDialectModules.contains(dialectNamespace)) + std::string dialectNamespaceStr(dialectNamespace); + if (loadedDialectModules.find(dialectNamespaceStr) != + loadedDialectModules.end()) return true; } // Since re-entrancy is possible, make a copy of the search prefixes. @@ -75,7 +77,7 @@ bool PyGlobals::loadDialectModule(llvm::StringRef dialectNamespace) { // Note: Iterator cannot be shared from prior to loading, since re-entrancy // may have occurred, which may do anything. nb::ft_lock_guard lock(mutex); - loadedDialectModules.insert(dialectNamespace); + loadedDialectModules.insert(std::string(dialectNamespace)); return true; } @@ -84,11 +86,10 @@ void PyGlobals::registerAttributeBuilder(const std::string &attributeKind, nb::ft_lock_guard lock(mutex); nb::object &found = attributeBuilderMap[attributeKind]; if (found && !replace) { - throw std::runtime_error((llvm::Twine("Attribute builder for '") + - attributeKind + - "' is already registered with func: " + - nb::cast(nb::str(found))) - .str()); + throw std::runtime_error( + nanobind::detail::join("Attribute builder for '", attributeKind, + "' is already registered with func: ", + nb::cast(nb::str(found)))); } found = std::move(pyFunc); } @@ -118,9 +119,8 @@ void PyGlobals::registerDialectImpl(const std::string &dialectNamespace, nb::ft_lock_guard lock(mutex); nb::object &found = dialectClassMap[dialectNamespace]; if (found) { - throw std::runtime_error((llvm::Twine("Dialect namespace '") + - dialectNamespace + "' is already registered.") - .str()); + throw std::runtime_error(nanobind::detail::join( + "Dialect namespace '", dialectNamespace, "' is already registered.")); } found = std::move(pyClass); } @@ -130,9 +130,8 @@ void PyGlobals::registerOperationImpl(const std::string &operationName, nb::ft_lock_guard lock(mutex); nb::object &found = operationClassMap[operationName]; if (found && !replace) { - throw std::runtime_error((llvm::Twine("Operation '") + operationName + - "' is already registered.") - .str()); + throw std::runtime_error(nanobind::detail::join( + "Operation '", operationName, "' is already registered.")); } found = std::move(pyClass); } @@ -142,9 +141,8 @@ void PyGlobals::registerOpAdaptorImpl(const std::string &operationName, nb::ft_lock_guard lock(mutex); nb::object &found = opAdaptorClassMap[operationName]; if (found && !replace) { - throw std::runtime_error((llvm::Twine("Operation adaptor of '") + - operationName + "' is already registered.") - .str()); + throw std::runtime_error(nanobind::detail::join( + "Operation adaptor of '", operationName, "' is already registered.")); } found = std::move(pyClass); } @@ -189,8 +187,8 @@ std::optional PyGlobals::lookupValueCaster(MlirTypeID mlirTypeID, std::optional PyGlobals::lookupDialectClass(const std::string &dialectNamespace) { // Make sure dialect module is loaded. - if (!loadDialectModule(dialectNamespace)) - return std::nullopt; + (void)loadDialectModule(dialectNamespace); + nb::ft_lock_guard lock(mutex); const auto foundIt = dialectClassMap.find(dialectNamespace); if (foundIt != dialectClassMap.end()) { @@ -202,15 +200,15 @@ PyGlobals::lookupDialectClass(const std::string &dialectNamespace) { } std::optional -PyGlobals::lookupOperationClass(llvm::StringRef operationName) { +PyGlobals::lookupOperationClass(std::string_view operationName) { // Make sure dialect module is loaded. - auto split = operationName.split('.'); - llvm::StringRef dialectNamespace = split.first; - if (!loadDialectModule(dialectNamespace)) - return std::nullopt; + std::string_view dialectNamespace = + operationName.substr(0, operationName.find('.')); + (void)loadDialectModule(dialectNamespace); nb::ft_lock_guard lock(mutex); - auto foundIt = operationClassMap.find(operationName); + std::string operationNameStr(operationName); + auto foundIt = operationClassMap.find(operationNameStr); if (foundIt != operationClassMap.end()) { assert(foundIt->second && "OpView is defined"); return foundIt->second; @@ -220,15 +218,15 @@ PyGlobals::lookupOperationClass(llvm::StringRef operationName) { } std::optional -PyGlobals::lookupOpAdaptorClass(llvm::StringRef operationName) { +PyGlobals::lookupOpAdaptorClass(std::string_view operationName) { // Make sure dialect module is loaded. - auto split = operationName.split('.'); - llvm::StringRef dialectNamespace = split.first; - if (!loadDialectModule(dialectNamespace)) - return std::nullopt; + std::string_view dialectNamespace = + operationName.substr(0, operationName.find('.')); + (void)loadDialectModule(dialectNamespace); nb::ft_lock_guard lock(mutex); - auto foundIt = opAdaptorClassMap.find(operationName); + std::string operationNameStr(operationName); + auto foundIt = opAdaptorClassMap.find(operationNameStr); if (foundIt != opAdaptorClassMap.end()) { assert(foundIt->second && "OpAdaptor is defined"); return foundIt->second; @@ -282,7 +280,7 @@ void PyGlobals::TracebackLoc::registerTracebackFileExclusion( } bool PyGlobals::TracebackLoc::isUserTracebackFilename( - const llvm::StringRef file) { + const std::string_view file) { nanobind::ft_lock_guard lock(mutex); if (rebuildUserTracebackIncludeRegex) { userTracebackIncludeRegex.assign( @@ -296,13 +294,14 @@ bool PyGlobals::TracebackLoc::isUserTracebackFilename( rebuildUserTracebackExcludeRegex = false; isUserTracebackFilenameCache.clear(); } - if (!isUserTracebackFilenameCache.contains(file)) { - std::string fileStr = file.str(); + std::string fileStr(file); + const auto foundIt = isUserTracebackFilenameCache.find(fileStr); + if (foundIt == isUserTracebackFilenameCache.end()) { bool include = std::regex_search(fileStr, userTracebackIncludeRegex); bool exclude = std::regex_search(fileStr, userTracebackExcludeRegex); - isUserTracebackFilenameCache[file] = include || !exclude; + isUserTracebackFilenameCache[fileStr] = include || !exclude; } - return isUserTracebackFilenameCache[file]; + return isUserTracebackFilenameCache[fileStr]; } } // namespace MLIR_BINDINGS_PYTHON_DOMAIN } // namespace python diff --git a/mlir/lib/Bindings/Python/IRAffine.cpp b/mlir/lib/Bindings/Python/IRAffine.cpp index 2e760e6e6f830..131481b830c4d 100644 --- a/mlir/lib/Bindings/Python/IRAffine.cpp +++ b/mlir/lib/Bindings/Python/IRAffine.cpp @@ -8,8 +8,10 @@ #include #include +#include #include #include +#include #include #include @@ -23,19 +25,11 @@ #include "mlir-c/IntegerSet.h" #include "mlir/Bindings/Python/Nanobind.h" #include "mlir/Support/LLVM.h" -#include "llvm/ADT/Hashing.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/ADT/Twine.h" namespace nb = nanobind; using namespace mlir; using namespace mlir::python::MLIR_BINDINGS_PYTHON_DOMAIN; -using llvm::SmallVector; -using llvm::StringRef; -using llvm::Twine; - static const char kDumpDocstring[] = R"(Dumps a debug representation of the object to stderr.)"; @@ -44,22 +38,19 @@ static const char kDumpDocstring[] = /// Throws errors in case of failure, using "action" to describe what the caller /// was attempting to do. template -static void pyListToVector(const nb::list &list, - llvm::SmallVectorImpl &result, - StringRef action) { +static void pyListToVector(const nb::list &list, std::vector &result, + std::string_view action) { result.reserve(nb::len(list)); for (nb::handle item : list) { try { result.push_back(nb::cast(item)); } catch (nb::cast_error &err) { - std::string msg = (llvm::Twine("Invalid expression when ") + action + - " (" + err.what() + ")") - .str(); + std::string msg = nanobind::detail::join("Invalid expression when ", + action, " (", err.what(), ")"); throw std::runtime_error(msg.c_str()); } catch (std::runtime_error &err) { - std::string msg = (llvm::Twine("Invalid expression (None?) when ") + - action + " (" + err.what() + ")") - .str(); + std::string msg = nanobind::detail::join( + "Invalid expression (None?) when ", action, " (", err.what(), ")"); throw std::runtime_error(msg.c_str()); } } @@ -67,7 +58,7 @@ static void pyListToVector(const nb::list &list, template static bool isPermutation(const std::vector &permutation) { - llvm::SmallVector seen(permutation.size(), false); + std::vector seen(permutation.size(), false); for (auto val : permutation) { if (val < permutation.size()) { if (seen[val]) @@ -106,11 +97,11 @@ class PyConcreteAffineExpr : public BaseTy { static MlirAffineExpr castFrom(PyAffineExpr &orig) { if (!DerivedTy::isaFunction(orig)) { auto origRepr = nb::cast(nb::repr(nb::cast(orig))); - throw nb::value_error((Twine("Cannot cast affine expression to ") + - DerivedTy::pyClassName + " (from " + origRepr + - ")") - .str() - .c_str()); + throw nb::value_error( + nanobind::detail::join("Cannot cast affine expression to ", + DerivedTy::pyClassName, " (from ", origRepr, + ")") + .c_str()); } return orig; } @@ -602,7 +593,7 @@ void populateIRAffine(nb::module_ &m) { }) .def("__hash__", [](PyAffineExpr &self) { - return static_cast(llvm::hash_value(self.get().ptr)); + return std::hash{}(self.get().ptr); }) .def_prop_ro( "context", @@ -739,12 +730,12 @@ void populateIRAffine(nb::module_ &m) { }) .def("__hash__", [](PyAffineMap &self) { - return static_cast(llvm::hash_value(self.get().ptr)); + return std::hash{}(self.get().ptr); }) .def_static( "compress_unused_symbols", [](const nb::list &affineMaps, DefaultingPyMlirContext context) { - SmallVector maps; + std::vector maps; pyListToVector( affineMaps, maps, "attempting to create an AffineMap"); std::vector compressed(affineMaps.size()); @@ -772,7 +763,7 @@ void populateIRAffine(nb::module_ &m) { "get", [](intptr_t dimCount, intptr_t symbolCount, const nb::list &exprs, DefaultingPyMlirContext context) { - SmallVector affineExprs; + std::vector affineExprs; pyListToVector( exprs, affineExprs, "attempting to create an AffineMap"); MlirAffineMap map = @@ -925,7 +916,7 @@ void populateIRAffine(nb::module_ &m) { }) .def("__hash__", [](PyIntegerSet &self) { - return static_cast(llvm::hash_value(self.get().ptr)); + return std::hash{}(self.get().ptr); }) .def_prop_ro( "context", @@ -946,17 +937,14 @@ void populateIRAffine(nb::module_ &m) { if (exprs.size() == 0) throw nb::value_error("Expected non-empty list of constraints"); - // Copy over to a SmallVector because std::vector has a - // specialization for booleans that packs data and does not - // expose a `bool *`. - SmallVector flags(eqFlags.begin(), eqFlags.end()); - - SmallVector affineExprs; + // std::vector does not expose a bool* data pointer. + std::vector flags(eqFlags.begin(), eqFlags.end()); + std::vector affineExprs; pyListToVector(exprs, affineExprs, "attempting to create an IntegerSet"); MlirIntegerSet set = mlirIntegerSetGet( context->get(), numDims, numSymbols, exprs.size(), - affineExprs.data(), flags.data()); + affineExprs.data(), reinterpret_cast(flags.data())); return PyIntegerSet(context->getRef(), set); }, nb::arg("num_dims"), nb::arg("num_symbols"), nb::arg("exprs"), @@ -987,7 +975,8 @@ void populateIRAffine(nb::module_ &m) { "Expected the number of symbol replacement expressions " "to match that of symbols"); - SmallVector dimAffineExprs, symbolAffineExprs; + std::vector dimAffineExprs; + std::vector symbolAffineExprs; pyListToVector( dimExprs, dimAffineExprs, "attempting to create an IntegerSet by replacing dimensions"); diff --git a/mlir/lib/Bindings/Python/IRAttributes.cpp b/mlir/lib/Bindings/Python/IRAttributes.cpp index 05c0c5e825df3..c271497fcc9f8 100644 --- a/mlir/lib/Bindings/Python/IRAttributes.cpp +++ b/mlir/lib/Bindings/Python/IRAttributes.cpp @@ -6,12 +6,14 @@ // //===----------------------------------------------------------------------===// +#include #include #include #include #include #include #include +#include #include "mlir-c/BuiltinAttributes.h" #include "mlir-c/BuiltinTypes.h" @@ -21,15 +23,12 @@ #include "mlir/Bindings/Python/NanobindAdaptors.h" #include "mlir/Bindings/Python/NanobindUtils.h" #include "llvm/ADT/ScopeExit.h" -#include "llvm/Support/raw_ostream.h" namespace nb = nanobind; using namespace nanobind::literals; using namespace mlir; using namespace mlir::python::MLIR_BINDINGS_PYTHON_DOMAIN; -using llvm::SmallVector; - //------------------------------------------------------------------------------ // Docstrings (trivial, non-duplicated docstrings are included inline). //------------------------------------------------------------------------------ @@ -129,7 +128,7 @@ namespace MLIR_BINDINGS_PYTHON_DOMAIN { nb_buffer_info::nb_buffer_info( void *ptr, ssize_t itemsize, const char *format, ssize_t ndim, - SmallVector shape_in, SmallVector strides_in, + std::vector shape_in, std::vector strides_in, bool readonly, std::unique_ptr owned_view_in) : ptr(ptr), itemsize(itemsize), format(format), ndim(ndim), @@ -255,7 +254,7 @@ void PyArrayAttribute::bindDerived(ClassTy &c) { c.def_static( "get", [](const nb::list &attributes, DefaultingPyMlirContext context) { - SmallVector mlirAttributes; + std::vector mlirAttributes; mlirAttributes.reserve(nb::len(attributes)); for (auto attribute : attributes) { mlirAttributes.push_back(pyTryCast(attribute)); @@ -465,7 +464,7 @@ PySymbolRefAttribute::fromList(const std::vector &symbols, throw std::runtime_error("SymbolRefAttr must be composed of at least " "one symbol."); MlirStringRef rootSymbol = toMlirStringRef(symbols[0]); - SmallVector referenceAttrs; + std::vector referenceAttrs; for (size_t i = 1; i < symbols.size(); ++i) { referenceAttrs.push_back( mlirFlatSymbolRefAttrGet(context.get(), toMlirStringRef(symbols[i]))); @@ -566,22 +565,21 @@ PyDenseElementsAttribute::getFromList(const nb::list &attributes, if ((!mlirTypeIsAShaped(*explicitType) || !mlirShapedTypeHasStaticShape(*explicitType))) { - std::string message; - llvm::raw_string_ostream os(message); - os << "Expected a static ShapedType for the shaped_type parameter: " - << nb::cast(nb::repr(nb::cast(*explicitType))); + std::string message = nanobind::detail::join( + "Expected a static ShapedType for the shaped_type parameter: ", + nb::cast(nb::repr(nb::cast(*explicitType)))); throw nb::value_error(message.c_str()); } shapedType = *explicitType; } else { - SmallVector shape = {static_cast(numAttributes)}; + std::vector shape = {static_cast(numAttributes)}; shapedType = mlirRankedTensorTypeGet( shape.size(), shape.data(), mlirAttributeGetType(pyTryCast(attributes[0])), mlirAttributeGetNull()); } - SmallVector mlirAttributes; + std::vector mlirAttributes; mlirAttributes.reserve(numAttributes); for (const nb::handle &attribute : attributes) { MlirAttribute mlirAttribute = pyTryCast(attribute); @@ -589,12 +587,11 @@ PyDenseElementsAttribute::getFromList(const nb::list &attributes, mlirAttributes.push_back(mlirAttribute); if (!mlirTypeEqual(mlirShapedTypeGetElementType(shapedType), attrType)) { - std::string message; - llvm::raw_string_ostream os(message); - os << "All attributes must be of the same type and match " - << "the type parameter: expected=" - << nb::cast(nb::repr(nb::cast(shapedType))) - << ", but got=" << nb::cast(nb::repr(nb::cast(attrType))); + std::string message = nanobind::detail::join( + "All attributes must be of the same type and match the type " + "parameter: expected=", + nb::cast(nb::repr(nb::cast(shapedType))), + ", but got=", nb::cast(nb::repr(nb::cast(attrType)))); throw nb::value_error(message.c_str()); } } @@ -810,11 +807,11 @@ bool PyDenseElementsAttribute::isSignedIntegerFormat(std::string_view format) { MlirType PyDenseElementsAttribute::getShapedType( std::optional bulkLoadElementType, std::optional> explicitShape, Py_buffer &view) { - SmallVector shape; + std::vector shape; if (explicitShape) { - shape.append(explicitShape->begin(), explicitShape->end()); + shape.insert(shape.end(), explicitShape->begin(), explicitShape->end()); } else { - shape.append(view.shape, view.shape + view.ndim); + shape.insert(shape.end(), view.shape, view.shape + view.ndim); } if (mlirTypeIsAShaped(*bulkLoadElementType)) { @@ -1199,7 +1196,7 @@ void PyDictAttribute::bindDerived(ClassTy &c) { c.def_static( "get", [](const nb::dict &attributes, DefaultingPyMlirContext context) { - SmallVector mlirNamedAttributes; + std::vector mlirNamedAttributes; mlirNamedAttributes.reserve(attributes.size()); for (std::pair it : attributes) { auto &mlirAttr = nb::cast(it.second); @@ -1303,7 +1300,7 @@ void PyStridedLayoutAttribute::bindDerived(ClassTy &c) { [](int64_t rank, DefaultingPyMlirContext ctx) { auto dynamic = mlirShapedTypeGetDynamicStrideOrOffset(); std::vector strides(rank); - llvm::fill(strides, dynamic); + std::fill(strides.begin(), strides.end(), dynamic); MlirAttribute attr = mlirStridedLayoutAttrGet( ctx->get(), dynamic, strides.size(), strides.data()); return PyStridedLayoutAttribute(ctx->getRef(), attr); diff --git a/mlir/lib/Bindings/Python/IRCore.cpp b/mlir/lib/Bindings/Python/IRCore.cpp index 7f34343eba6c9..6f03f334e34b4 100644 --- a/mlir/lib/Bindings/Python/IRCore.cpp +++ b/mlir/lib/Bindings/Python/IRCore.cpp @@ -16,17 +16,18 @@ #include "mlir-c/BuiltinAttributes.h" #include "mlir-c/Debug.h" #include "mlir-c/Diagnostics.h" +#include "mlir-c/ExtensibleDialect.h" #include "mlir-c/IR.h" #include "mlir-c/Support.h" #include #include -#include #include namespace nb = nanobind; using namespace nb::literals; using namespace mlir; +using nanobind::detail::join; static const char kModuleParseDocstring[] = R"(Parses a module's assembly format from a string. @@ -49,14 +50,6 @@ operations. // Utilities. //------------------------------------------------------------------------------ -/// Local helper to concatenate arguments into a `std::string`. -template -static std::string join(const Ts &...args) { - std::ostringstream oss; - (oss << ... << args); - return oss.str(); -} - /// Local helper to compute std::hash for a value. template static size_t hash(const T &value) { @@ -2521,6 +2514,119 @@ void PyOpAdaptor::bind(nb::module_ &m) { "Returns the attributes of the adaptor."); } +static MlirLogicalResult verifyTraitByMethod(MlirOperation op, void *userData, + const char *methodName) { + nb::handle targetObj(static_cast(userData)); + if (!nb::hasattr(targetObj, methodName)) { + return mlirLogicalResultSuccess(); + } + PyMlirContextRef ctx = PyMlirContext::forContext(mlirOperationGetContext(op)); + nb::object opView = PyOperation::forOperation(ctx, op)->createOpView(); + bool success = nb::cast(targetObj.attr(methodName)(opView)); + return success ? mlirLogicalResultSuccess() : mlirLogicalResultFailure(); +}; + +static bool attachOpTrait(const nb::object &opName, MlirDynamicOpTrait trait, + PyMlirContext &context) { + std::string opNameStr; + if (opName.is_type()) { + opNameStr = nb::cast(opName.attr("OPERATION_NAME")); + } else if (nb::isinstance(opName)) { + opNameStr = nb::cast(opName); + } else { + throw nb::type_error("the root argument must be a type or a string"); + } + + return mlirDynamicOpTraitAttach( + trait, MlirStringRef{opNameStr.data(), opNameStr.size()}, context.get()); +} + +bool PyDynamicOpTrait::attach(const nb::object &opName, + const nb::object &target, + PyMlirContext &context) { + if (!nb::hasattr(target, "verify") && !nb::hasattr(target, "verify_region")) + throw nb::type_error( + "the target object must have at least one of 'verify' or " + "'verify_region' methods"); + + MlirDynamicOpTraitCallbacks callbacks; + callbacks.construct = [](void *userData) { + nb::handle(static_cast(userData)).inc_ref(); + }; + callbacks.destruct = [](void *userData) { + nb::handle(static_cast(userData)).dec_ref(); + }; + + callbacks.verifyTrait = [](MlirOperation op, + void *userData) -> MlirLogicalResult { + return verifyTraitByMethod(op, userData, "verify"); + }; + callbacks.verifyRegionTrait = [](MlirOperation op, + void *userData) -> MlirLogicalResult { + return verifyTraitByMethod(op, userData, "verify_region"); + }; + + constexpr const char *typeIDAttr = "_TYPE_ID"; + if (!nb::hasattr(target, typeIDAttr)) { + nb::setattr(target, typeIDAttr, + nb::cast(PyTypeID(PyGlobals::get().allocateTypeID()))); + } + MlirDynamicOpTrait trait = mlirDynamicOpTraitCreate( + nb::cast(target.attr(typeIDAttr)).get(), callbacks, + static_cast(target.ptr())); + return attachOpTrait(opName, trait, context); +} + +void PyDynamicOpTrait::bind(nb::module_ &m) { + nb::class_ cls(m, "DynamicOpTrait"); + cls.attr("attach") = classmethod( + [](const nb::object &cls, const nb::object &opName, nb::object target, + DefaultingPyMlirContext context) { + if (target.is_none()) + target = cls; + return PyDynamicOpTrait::attach(opName, target, *context.get()); + }, + nb::arg("cls"), nb::arg("op_name"), nb::arg("target").none() = nb::none(), + nb::arg("context").none() = nb::none(), + "Attach the dynamic op trait subclass to the given operation name."); +} + +bool PyDynamicOpTraits::IsTerminator::attach(const nb::object &opName, + PyMlirContext &context) { + MlirDynamicOpTrait trait = mlirDynamicOpTraitGetIsTerminator(); + return attachOpTrait(opName, trait, context); +} + +void PyDynamicOpTraits::IsTerminator::bind(nb::module_ &m) { + nb::class_ cls( + m, "IsTerminatorTrait"); + cls.attr("attach") = classmethod( + [](const nb::object &cls, const nb::object &opName, + DefaultingPyMlirContext context) { + return PyDynamicOpTraits::IsTerminator::attach(opName, *context.get()); + }, + "Attach IsTerminator trait to the given operation name.", nb::arg("cls"), + nb::arg("op_name"), nb::arg("context").none() = nb::none()); +} + +bool PyDynamicOpTraits::NoTerminator::attach(const nb::object &opName, + PyMlirContext &context) { + MlirDynamicOpTrait trait = mlirDynamicOpTraitGetNoTerminator(); + return attachOpTrait(opName, trait, context); +} + +void PyDynamicOpTraits::NoTerminator::bind(nb::module_ &m) { + nb::class_ cls( + m, "NoTerminatorTrait"); + cls.attr("attach") = classmethod( + [](const nb::object &cls, const nb::object &opName, + DefaultingPyMlirContext context) { + return PyDynamicOpTraits::NoTerminator::attach(opName, *context.get()); + }, + "Attach NoTerminator trait to the given operation name.", nb::arg("cls"), + nb::arg("op_name"), nb::arg("context").none() = nb::none()); +} + } // namespace MLIR_BINDINGS_PYTHON_DOMAIN } // namespace python } // namespace mlir @@ -4844,6 +4950,11 @@ void populateIRCore(nb::module_ &m) { // Attribute builder getter. PyAttrBuilderMap::bind(m); + + // Extensible Dialect + PyDynamicOpTrait::bind(m); + PyDynamicOpTraits::IsTerminator::bind(m); + PyDynamicOpTraits::NoTerminator::bind(m); } } // namespace MLIR_BINDINGS_PYTHON_DOMAIN } // namespace python diff --git a/mlir/lib/Bindings/Python/IRInterfaces.cpp b/mlir/lib/Bindings/Python/IRInterfaces.cpp index 09112d4989ae4..be60426473e0d 100644 --- a/mlir/lib/Bindings/Python/IRInterfaces.cpp +++ b/mlir/lib/Bindings/Python/IRInterfaces.cpp @@ -18,8 +18,6 @@ #include "mlir-c/Support.h" #include "mlir/Bindings/Python/IRCore.h" #include "mlir/Bindings/Python/Nanobind.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SmallVector.h" namespace nb = nanobind; @@ -48,10 +46,10 @@ its return shaped type components. Raises ValueError on failure.)"; namespace { -/// Takes in an optional ist of operands and converts them into a SmallVector -/// of MlirVlaues. Returns an empty SmallVector if the list is empty. -llvm::SmallVector wrapOperands(std::optional operandList) { - llvm::SmallVector mlirOperands; +/// Takes in an optional ist of operands and converts them into a std::vector +/// of MlirVlaues. Returns an empty std::vector if the list is empty. +std::vector wrapOperands(std::optional operandList) { + std::vector mlirOperands; if (!operandList || operandList->size() == 0) { return mlirOperands; @@ -59,13 +57,15 @@ llvm::SmallVector wrapOperands(std::optional operandList) { // Note: as the list may contain other lists this may not be final size. mlirOperands.reserve(operandList->size()); - for (const auto &&it : llvm::enumerate(*operandList)) { - if (it.value().is_none()) + for (size_t i = 0, e = operandList->size(); i < e; ++i) { + nb::handle operand = (*operandList)[i]; + intptr_t index = static_cast(i); + if (operand.is_none()) continue; PyValue *val; try { - val = nb::cast(it.value()); + val = nb::cast(operand); if (!val) throw nb::cast_error(); mlirOperands.push_back(val->get()); @@ -76,7 +76,7 @@ llvm::SmallVector wrapOperands(std::optional operandList) { } try { - auto vals = nb::cast(it.value()); + auto vals = nb::cast(operand); for (nb::handle v : vals) { try { val = nb::cast(v); @@ -85,19 +85,19 @@ llvm::SmallVector wrapOperands(std::optional operandList) { mlirOperands.push_back(val->get()); } catch (nb::cast_error &err) { throw nb::value_error( - (llvm::Twine("Operand ") + llvm::Twine(it.index()) + - " must be a Value or Sequence of Values (" + err.what() + ")") - .str() + nanobind::detail::join("Operand ", index, + " must be a Value or Sequence of Values (", + err.what(), ")") .c_str()); } } continue; } catch (nb::cast_error &err) { - throw nb::value_error((llvm::Twine("Operand ") + llvm::Twine(it.index()) + - " must be a Value or Sequence of Values (" + - err.what() + ")") - .str() - .c_str()); + throw nb::value_error( + nanobind::detail::join("Operand ", index, + " must be a Value or Sequence of Values (", + err.what(), ")") + .c_str()); } throw nb::cast_error(); @@ -106,11 +106,11 @@ llvm::SmallVector wrapOperands(std::optional operandList) { return mlirOperands; } -/// Takes in an optional vector of PyRegions and returns a SmallVector of -/// MlirRegion. Returns an empty SmallVector if the list is empty. -llvm::SmallVector +/// Takes in an optional vector of PyRegions and returns a std::vector of +/// MlirRegion. Returns an empty std::vector if the list is empty. +std::vector wrapRegions(std::optional> regions) { - llvm::SmallVector mlirRegions; + std::vector mlirRegions; if (regions) { mlirRegions.reserve(regions->size()); @@ -273,9 +273,8 @@ class PyInferTypeOpInterface std::optional> regions, DefaultingPyMlirContext context, DefaultingPyLocation location) { - llvm::SmallVector mlirOperands = - wrapOperands(std::move(operandList)); - llvm::SmallVector mlirRegions = wrapRegions(std::move(regions)); + std::vector mlirOperands = wrapOperands(std::move(operandList)); + std::vector mlirRegions = wrapRegions(std::move(regions)); std::vector inferredTypes; PyMlirContext &pyContext = context.resolve(); @@ -430,9 +429,8 @@ class PyInferShapedTypeOpInterface std::optional attributes, void *properties, std::optional> regions, DefaultingPyMlirContext context, DefaultingPyLocation location) { - llvm::SmallVector mlirOperands = - wrapOperands(std::move(operandList)); - llvm::SmallVector mlirRegions = wrapRegions(std::move(regions)); + std::vector mlirOperands = wrapOperands(std::move(operandList)); + std::vector mlirRegions = wrapRegions(std::move(regions)); std::vector inferredShapedTypeComponents; PyMlirContext &pyContext = context.resolve(); diff --git a/mlir/lib/Bindings/Python/IRTypes.cpp b/mlir/lib/Bindings/Python/IRTypes.cpp index 94327f67e050e..a8e60f099ef67 100644 --- a/mlir/lib/Bindings/Python/IRTypes.cpp +++ b/mlir/lib/Bindings/Python/IRTypes.cpp @@ -24,7 +24,6 @@ using namespace mlir; using namespace mlir::python::MLIR_BINDINGS_PYTHON_DOMAIN; using llvm::SmallVector; -using llvm::Twine; namespace mlir { namespace python { @@ -311,10 +310,10 @@ void PyComplexType::bindDerived(ClassTy &c) { return PyComplexType(elementType.getContext(), t); } throw nb::value_error( - (Twine("invalid '") + - nb::cast(nb::repr(nb::cast(elementType))) + - "' and expected floating point or integer type.") - .str() + nanobind::detail::join( + "invalid '", + nb::cast(nb::repr(nb::cast(elementType))), + "' and expected floating point or integer type.") .c_str()); }, "Create a complex type"); diff --git a/mlir/lib/CAPI/IR/CMakeLists.txt b/mlir/lib/CAPI/IR/CMakeLists.txt index 36f28520d6757..d78f9d9735aa3 100644 --- a/mlir/lib/CAPI/IR/CMakeLists.txt +++ b/mlir/lib/CAPI/IR/CMakeLists.txt @@ -6,6 +6,7 @@ add_mlir_upstream_c_api_library(MLIRCAPIIR BuiltinTypes.cpp Diagnostics.cpp DialectHandle.cpp + ExtensibleDialect.cpp IntegerSet.cpp IR.cpp Pass.cpp diff --git a/mlir/lib/CAPI/IR/ExtensibleDialect.cpp b/mlir/lib/CAPI/IR/ExtensibleDialect.cpp new file mode 100644 index 0000000000000..f3239d996a0e6 --- /dev/null +++ b/mlir/lib/CAPI/IR/ExtensibleDialect.cpp @@ -0,0 +1,87 @@ +//===- ExtensibleDialect - C API for MLIR Extensible Dialect --------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir-c/ExtensibleDialect.h" +#include "mlir/CAPI/IR.h" +#include "mlir/CAPI/Support.h" +#include "mlir/IR/ExtensibleDialect.h" +#include "mlir/IR/OperationSupport.h" + +using namespace mlir; + +DEFINE_C_API_PTR_METHODS(MlirDynamicOpTrait, DynamicOpTrait) + +bool mlirDynamicOpTraitAttach(MlirDynamicOpTrait dynamicOpTrait, + MlirStringRef opName, MlirContext context) { + std::optional opNameFound = + RegisteredOperationName::lookup(unwrap(opName), unwrap(context)); + assert(opNameFound && "operation name must be registered in the context"); + + // The original getImpl() is protected, so we create a small helper struct + // here. + struct RegisteredOperationNameWithImpl : RegisteredOperationName { + Impl *getImpl() { return RegisteredOperationName::getImpl(); } + }; + OperationName::Impl *impl = + static_cast(*opNameFound).getImpl(); + + std::unique_ptr trait(unwrap(dynamicOpTrait)); + // TODO: we should check whether the `impl` is a DynamicOpDefinition here + // via llvm-style RTTI. + return static_cast(impl)->addTrait(std::move(trait)); +} + +MlirDynamicOpTrait mlirDynamicOpTraitGetIsTerminator() { + return wrap(new DynamicOpTraits::IsTerminator()); +} + +MlirDynamicOpTrait mlirDynamicOpTraitGetNoTerminator() { + return wrap(new DynamicOpTraits::NoTerminator()); +} + +void mlirDynamicOpTraitDestroy(MlirDynamicOpTrait dynamicOpTrait) { + delete unwrap(dynamicOpTrait); +} + +namespace mlir { + +class ExternalDynamicOpTrait : public DynamicOpTrait { +public: + ExternalDynamicOpTrait(TypeID typeID, MlirDynamicOpTraitCallbacks callbacks, + void *userData) + : typeID(typeID), callbacks(callbacks), userData(userData) { + if (callbacks.construct) + callbacks.construct(userData); + } + ~ExternalDynamicOpTrait() { + if (callbacks.destruct) + callbacks.destruct(userData); + } + + LogicalResult verifyTrait(Operation *op) const override { + return unwrap(callbacks.verifyTrait(wrap(op), userData)); + }; + LogicalResult verifyRegionTrait(Operation *op) const override { + return unwrap(callbacks.verifyRegionTrait(wrap(op), userData)); + }; + + TypeID getTypeID() const override { return typeID; }; + +private: + TypeID typeID; + MlirDynamicOpTraitCallbacks callbacks; + void *userData; +}; + +} // namespace mlir + +MlirDynamicOpTrait mlirDynamicOpTraitCreate( + MlirTypeID typeID, MlirDynamicOpTraitCallbacks callbacks, void *userData) { + return wrap( + new mlir::ExternalDynamicOpTrait(unwrap(typeID), callbacks, userData)); +} diff --git a/mlir/lib/CAPI/IR/Support.cpp b/mlir/lib/CAPI/IR/Support.cpp index 3311131fc2bc8..3a41fb2a00a85 100644 --- a/mlir/lib/CAPI/IR/Support.cpp +++ b/mlir/lib/CAPI/IR/Support.cpp @@ -8,9 +8,12 @@ #include "mlir/CAPI/Support.h" #include "llvm/ADT/StringRef.h" +#include "llvm/Support/FileSystem.h" #include "llvm/Support/ThreadPool.h" +#include "llvm/Support/raw_ostream.h" #include +#include MlirStringRef mlirStringRefCreateFromCString(const char *str) { return mlirStringRefCreate(str, strlen(str)); @@ -32,6 +35,41 @@ void mlirLlvmThreadPoolDestroy(MlirLlvmThreadPool threadPool) { delete unwrap(threadPool); } +//===----------------------------------------------------------------------===// +// LLVM raw_fd_ostream API. +//===----------------------------------------------------------------------===// + +MlirLlvmRawFdOStream +mlirLlvmRawFdOStreamCreate(const char *path, bool binary, + MlirStringCallback errorCallback, void *userData) { + std::error_code ec; + auto flags = binary ? llvm::sys::fs::OF_None : llvm::sys::fs::OF_Text; + auto *stream = new llvm::raw_fd_ostream(path, ec, flags); + if (ec) { + delete stream; + if (errorCallback) { + std::string message = ec.message(); + errorCallback(mlirStringRefCreate(message.data(), message.size()), + userData); + } + return wrap(static_cast(nullptr)); + } + return wrap(stream); +} + +void mlirLlvmRawFdOStreamWrite(MlirLlvmRawFdOStream stream, + MlirStringRef string) { + unwrap(stream)->write(string.data, string.length); +} + +bool mlirLlvmRawFdOStreamIsNull(MlirLlvmRawFdOStream stream) { + return !stream.ptr; +} + +void mlirLlvmRawFdOStreamDestroy(MlirLlvmRawFdOStream stream) { + delete unwrap(stream); +} + //===----------------------------------------------------------------------===// // TypeID API. //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp index e7dd8ea6f9149..b433b7fd61fb1 100644 --- a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp +++ b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp @@ -2602,6 +2602,257 @@ struct AMDGPUPermlaneLowering : public ConvertOpToLLVMPattern { } }; +//===----------------------------------------------------------------------===// +// In-LDS Barrier Operations +//===----------------------------------------------------------------------===// + +// Bit layout of ds_barrier_state (as i64): +// [63:32] init count (32 bits) +// [31:28] phase (4 bits) +// [27:0] pending count (28 bits) +constexpr int32_t kDsBarrierPendingCountBitWidth = 28; +constexpr int32_t kDsBarrierPhasePos = kDsBarrierPendingCountBitWidth; +constexpr int32_t kDsBarrierInitCountPos = 32; +constexpr int32_t kDsBarrierPendingCountMask = + (1 << kDsBarrierPendingCountBitWidth) - 1; + +struct DsBarrierInitOpLowering + : public ConvertOpToLLVMPattern { + Chipset chipset; + + DsBarrierInitOpLowering(const LLVMTypeConverter &converter, Chipset chipset) + : ConvertOpToLLVMPattern(converter), chipset(chipset) {} + + LogicalResult + matchAndRewrite(DsBarrierInitOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + if (chipset < kGfx1250) + return op->emitOpError("only supported on gfx1250+"); + + Location loc = op.getLoc(); + Type i64 = rewriter.getI64Type(); + + MemRefType memrefType = cast(op.getBase().getType()); + Value ptr = getStridedElementPtr(rewriter, loc, memrefType, + adaptor.getBase(), adaptor.getIndices()); + + // Note: We give participants as the number of arrivals that have to occur + // before the phase changes. Hardware changes the phase when updating the + // pending count would underflow, so we subtract 1 to get the behavior we're + // looking for. + Value initCount = + LLVM::SubOp::create(rewriter, loc, adaptor.getParticipants(), + createI32Constant(rewriter, loc, 1)); + + // Just a bit of paranoia, but this also allows for configurable width if + // that becomes a thing. + Value countMask = + createI32Constant(rewriter, loc, kDsBarrierPendingCountMask); + Value maskedCount32 = + LLVM::AndOp::create(rewriter, loc, initCount, countMask); + Value maskedCount = LLVM::ZExtOp::create(rewriter, loc, i64, maskedCount32); + + Value initCountShifted = LLVM::ShlOp::create( + rewriter, loc, maskedCount, + createI64Constant(rewriter, loc, kDsBarrierInitCountPos)); + Value barrierState = + LLVM::OrOp::create(rewriter, loc, initCountShifted, maskedCount); + + LLVM::StoreOp::create( + rewriter, loc, barrierState, ptr, /*alignment=*/8, /*isVolatile=*/false, + /*isNonTemporal=*/false, + /*isInvariantGroup=*/false, LLVM::AtomicOrdering::release, + /*syncscope=*/"workgroup"); + + rewriter.eraseOp(op); + return success(); + } +}; + +struct DsBarrierPollStateOpLowering + : public ConvertOpToLLVMPattern { + Chipset chipset; + + DsBarrierPollStateOpLowering(const LLVMTypeConverter &converter, + Chipset chipset) + : ConvertOpToLLVMPattern(converter), + chipset(chipset) {} + + LogicalResult + matchAndRewrite(DsBarrierPollStateOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + if (chipset < kGfx1250) + return op->emitOpError("only supported on gfx1250+"); + + Location loc = op.getLoc(); + Type i64 = rewriter.getI64Type(); + + MemRefType memrefType = cast(op.getBase().getType()); + Value ptr = getStridedElementPtr(rewriter, loc, memrefType, + adaptor.getBase(), adaptor.getIndices()); + + // Atomic load with workgroup scope and acquire ordering should be what + // we're looking for. + rewriter.replaceOpWithNewOp( + op, i64, ptr, /*alignment=*/8, /*volatile_=*/false, + /*nontemporal=*/false, /*invariant=*/false, + /*invariantGroup=*/false, LLVM::AtomicOrdering::acquire, + /*syncscope=*/"workgroup"); + return success(); + } +}; + +struct DsAsyncBarrierArriveOpLowering + : public ConvertOpToLLVMPattern { + Chipset chipset; + + DsAsyncBarrierArriveOpLowering(const LLVMTypeConverter &converter, + Chipset chipset) + : ConvertOpToLLVMPattern(converter), + chipset(chipset) {} + + LogicalResult + matchAndRewrite(DsAsyncBarrierArriveOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + if (chipset < kGfx1250) + return op->emitOpError("only supported on gfx1250+"); + + Location loc = op.getLoc(); + + MemRefType memrefType = cast(op.getBase().getType()); + Value ptr = getStridedElementPtr(rewriter, loc, memrefType, + adaptor.getBase(), adaptor.getIndices()); + + rewriter.replaceOpWithNewOp( + op, ptr, /*alias_scopes=*/nullptr, /*noalias_scopes=*/nullptr, + /*tbaa=*/nullptr); + return success(); + } +}; + +struct DsBarrierArriveOpLowering + : public ConvertOpToLLVMPattern { + Chipset chipset; + + DsBarrierArriveOpLowering(const LLVMTypeConverter &converter, Chipset chipset) + : ConvertOpToLLVMPattern(converter), chipset(chipset) { + } + + LogicalResult + matchAndRewrite(DsBarrierArriveOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + if (chipset < kGfx1250) + return op->emitOpError("only supported on gfx1250+"); + + Location loc = op.getLoc(); + Type i64 = rewriter.getI64Type(); + + MemRefType memrefType = cast(op.getBase().getType()); + Value ptr = getStridedElementPtr(rewriter, loc, memrefType, + adaptor.getBase(), adaptor.getIndices()); + + rewriter.replaceOpWithNewOp( + op, i64, ptr, adaptor.getCount(), /*alias_scopes=*/nullptr, + /*noalias_scopes=*/nullptr, /*tbaa=*/nullptr); + return success(); + } +}; + +struct DsBarrierStatePhaseOpLowering + : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(DsBarrierStatePhaseOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Type i32 = rewriter.getI32Type(); + + Value state = adaptor.getState(); + + Value noInitCount = LLVM::TruncOp::create(rewriter, loc, i32, state); + Value phase = LLVM::LShrOp::create( + rewriter, loc, noInitCount, + createI32Constant(rewriter, loc, kDsBarrierPhasePos)); + + rewriter.replaceOp(op, phase); + return success(); + } +}; + +struct DsBarrierStatePendingCountOpLowering + : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(DsBarrierStatePendingCountOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Type i32 = rewriter.getI32Type(); + + Value state = adaptor.getState(); + + Value noInitCount = LLVM::TruncOp::create(rewriter, loc, i32, state); + Value pendingCount = LLVM::AndOp::create( + rewriter, loc, noInitCount, + createI32Constant(rewriter, loc, + static_cast(kDsBarrierPendingCountMask))); + + rewriter.replaceOp(op, pendingCount); + return success(); + } +}; + +struct DsBarrierStateInitCountOpLowering + : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(DsBarrierStateInitCountOp op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Type i32 = rewriter.getI32Type(); + + Value state = adaptor.getState(); + + Value initCountI64 = LLVM::LShrOp::create( + rewriter, loc, state, + createI64Constant(rewriter, loc, kDsBarrierInitCountPos)); + Value initCount = LLVM::TruncOp::create(rewriter, loc, i32, initCountI64); + + rewriter.replaceOp(op, initCount); + return success(); + } +}; + +struct DsBarrierStatePhaseParityLowering + : public ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + LogicalResult + matchAndRewrite(DsBarrierStatePhaseParity op, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + Type i1 = rewriter.getI1Type(); + + Value state = adaptor.getState(); + + Value noInitCount = + LLVM::TruncOp::create(rewriter, loc, rewriter.getI32Type(), state); + Value phase = LLVM::LShrOp::create( + rewriter, loc, noInitCount, + createI32Constant(rewriter, loc, kDsBarrierPhasePos)); + Value parity = LLVM::TruncOp::create(rewriter, loc, i1, phase); + + rewriter.replaceOp(op, parity); + return success(); + } +}; + +//===----------------------------------------------------------------------===// +// Tensor Data Mover (TDM) +//===----------------------------------------------------------------------===// + static Value setValueAtOffset(ConversionPatternRewriter &rewriter, Location loc, Value accumulator, Value value, int64_t shift) { shift = shift % 32; @@ -3505,6 +3756,9 @@ void mlir::populateAMDGPUTypeAndAttributeConversions( } return TypeConverter::AttributeConversionResult::abort(); }); + typeConverter.addConversion([&](DsBarrierStateType type) -> Type { + return IntegerType::get(type.getContext(), 64); + }); typeConverter.addConversion([&](TDMBaseType type) -> Type { Type i32 = IntegerType::get(type.getContext(), 32); return typeConverter.convertType(VectorType::get(4, i32)); @@ -3574,7 +3828,12 @@ void mlir::populateAMDGPUToROCDLConversionPatterns(LLVMTypeConverter &converter, AMDGPUTensorLoadStoreOpLowering, AMDGPUTensorLoadStoreOpLowering>( - converter, chipset); - patterns.add(converter); + ROCDL::TensorStoreFromLDSOp>, + DsBarrierInitOpLowering, DsBarrierPollStateOpLowering, + DsAsyncBarrierArriveOpLowering, DsBarrierArriveOpLowering>(converter, + chipset); + patterns.add(converter); } diff --git a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp index 69a83468cfa84..096554d53e031 100644 --- a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp +++ b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp @@ -170,6 +170,67 @@ struct GPUSubgroupSizeOpToROCDL : ConvertOpToLLVMPattern { const amdgpu::Chipset chipset; }; +struct GPUSubgroupIdOpToROCDL : ConvertOpToLLVMPattern { + using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; + + GPUSubgroupIdOpToROCDL(const LLVMTypeConverter &converter, + amdgpu::Chipset chipset) + : ConvertOpToLLVMPattern(converter), chipset(chipset) { + } + + LogicalResult + matchAndRewrite(gpu::SubgroupIdOp op, gpu::SubgroupIdOp::Adaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Location loc = op.getLoc(); + auto int32Type = rewriter.getI32Type(); + + Value subgroupId; + if (chipset.majorVersion >= 12) { + // For gfx12+, use the hardware wave.id register directly. + LLVM::ConstantRangeAttr bounds; + if (auto upperBoundAttr = op.getUpperBoundAttr()) + bounds = rewriter.getAttr( + /*bitWidth=*/32, /*lower=*/0, + /*upper=*/upperBoundAttr.getInt()); + subgroupId = ROCDL::WaveId::create(rewriter, loc, int32Type, bounds); + } else { + // For older architectures, compute: + // subgroup_id = linearized_thread_id / subgroup_size + // where linearized_thread_id = tid.x + dim.x * (tid.y + dim.y * tid.z) + Value tidX = ROCDL::ThreadIdXOp::create(rewriter, loc, int32Type); + Value tidY = ROCDL::ThreadIdYOp::create(rewriter, loc, int32Type); + Value tidZ = ROCDL::ThreadIdZOp::create(rewriter, loc, int32Type); + Value dimX = ROCDL::BlockDimXOp::create(rewriter, loc, int32Type); + Value dimY = ROCDL::BlockDimYOp::create(rewriter, loc, int32Type); + + // linearized = tid.x + dim.x * (tid.y + dim.y * tid.z) + // Thread IDs and dimensions are non-negative and small, so use nuw+nsw. + auto flags = + LLVM::IntegerOverflowFlags::nsw | LLVM::IntegerOverflowFlags::nuw; + Value dimYxTidZ = + LLVM::MulOp::create(rewriter, loc, int32Type, dimY, tidZ, flags); + Value tidYPlusDimYxTidZ = + LLVM::AddOp::create(rewriter, loc, int32Type, tidY, dimYxTidZ, flags); + Value dimXxInner = LLVM::MulOp::create(rewriter, loc, int32Type, dimX, + tidYPlusDimYxTidZ, flags); + Value linearized = LLVM::AddOp::create(rewriter, loc, int32Type, tidX, + dimXxInner, flags); + + Value subgroupSize = + ROCDL::WavefrontSizeOp::create(rewriter, loc, int32Type); + subgroupId = LLVM::UDivOp::create(rewriter, loc, int32Type, linearized, + subgroupSize); + } + + subgroupId = + truncOrExtToLLVMType(rewriter, loc, subgroupId, *getTypeConverter()); + rewriter.replaceOp(op, subgroupId); + return success(); + } + + const amdgpu::Chipset chipset; +}; + static bool isSupportedReadLaneType(Type type) { // https://llvm.org/docs/AMDGPUUsage.html#llvm-ir-intrinsics if (isa(converter); - patterns.add(converter, - chipset); + patterns.add(converter, chipset); populateMathToROCDLConversionPatterns(converter, patterns, chipset); } diff --git a/mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp b/mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp index 4a1c5d1f7846c..0dbc0a126a5c6 100644 --- a/mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp +++ b/mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp @@ -20,6 +20,7 @@ #include "mlir/Dialect/LLVMIR/LLVMDialect.h" #include "mlir/Dialect/LLVMIR/LLVMTypes.h" #include "mlir/Dialect/MPI/IR/MPI.h" +#include "mlir/Dialect/MPI/IR/Utils.h" #include "mlir/Transforms/DialectConversion.h" #include @@ -51,7 +52,8 @@ static LLVM::LLVMFuncOp getOrDefineFunction(ModuleOp &moduleOp, std::pair getRawPtrAndSize(const Location loc, ConversionPatternRewriter &rewriter, - Value memRef, Type elType) { + Value memRef, int64_t rank, + Type elType) { Type ptrType = LLVM::LLVMPointerType::get(rewriter.getContext()); Value dataPtr = LLVM::ExtractValueOp::create(rewriter, loc, ptrType, memRef, 1); @@ -59,11 +61,16 @@ std::pair getRawPtrAndSize(const Location loc, rewriter.getI64Type(), memRef, 2); Value resPtr = LLVM::GEPOp::create(rewriter, loc, ptrType, elType, dataPtr, offset); - Value size; + Value size = LLVM::ConstantOp::create(rewriter, loc, rewriter.getI32Type(), + rewriter.getIndexAttr(1)); if (cast(memRef.getType()).getBody().size() > 3) { - size = LLVM::ExtractValueOp::create(rewriter, loc, memRef, - ArrayRef{3, 0}); - size = LLVM::TruncOp::create(rewriter, loc, rewriter.getI32Type(), size); + for (int64_t i = 0; i < rank; ++i) { + Value dim = LLVM::ExtractValueOp::create(rewriter, loc, memRef, + ArrayRef{3, i}); + dim = LLVM::TruncOp::create(rewriter, loc, rewriter.getI32Type(), dim); + size = + LLVM::MulOp::create(rewriter, loc, rewriter.getI32Type(), dim, size); + } } else { size = arith::ConstantIntOp::create(rewriter, loc, 1, 32); } @@ -396,7 +403,7 @@ class OMPIImplTraits : public MPIImplTraits { }; std::unique_ptr MPIImplTraits::get(ModuleOp &moduleOp) { - auto attr = dlti::query(*&moduleOp, {"MPI:Implementation"}, true); + auto attr = dlti::query(moduleOp, {"MPI:Implementation"}, false); if (failed(attr)) return std::make_unique(moduleOp); auto strAttr = dyn_cast(attr.value()); @@ -608,6 +615,17 @@ struct CommRankOpLowering : public ConvertOpToLLVMPattern { // CommSizeOpLowering //===----------------------------------------------------------------------===// +static Value createOrFoldCommSize(ConversionPatternRewriter &rewriter, + Location loc, Value commOrg, + Value commAdapt) { + auto i32 = rewriter.getI32Type(); + auto nRanksOp = mpi::CommSizeOp::create(rewriter, loc, i32, commOrg); + if (succeeded(FoldToDLTIConst(nRanksOp, "MPI:comm_world_size", rewriter))) + return nRanksOp.getSize(); + rewriter.eraseOp(nRanksOp); + return mpi::CommSizeOp::create(rewriter, loc, i32, commAdapt).getSize(); +} + struct CommSizeOpLowering : public ConvertOpToLLVMPattern { using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern; @@ -634,7 +652,7 @@ struct CommSizeOpLowering : public ConvertOpToLLVMPattern { LLVM::LLVMFunctionType::get(i32, {comm.getType(), ptrType}); // get or create function declaration: LLVM::LLVMFuncOp initDecl = getOrDefineFunction( - moduleOp, loc, rewriter, "MPI_Comm_Size", SizeFuncType); + moduleOp, loc, rewriter, "MPI_Comm_size", SizeFuncType); // replace with function call auto one = LLVM::ConstantOp::create(rewriter, loc, i32, 1); @@ -675,6 +693,7 @@ struct SendOpLowering : public ConvertOpToLLVMPattern { MLIRContext *context = rewriter.getContext(); Type i32 = rewriter.getI32Type(); Type elemType = op.getRef().getType().getElementType(); + int64_t rank = op.getRef().getType().getRank(); // ptrType `!llvm.ptr` Type ptrType = LLVM::LLVMPointerType::get(context); @@ -684,7 +703,7 @@ struct SendOpLowering : public ConvertOpToLLVMPattern { // get MPI_COMM_WORLD, dataType and pointer auto [dataPtr, size] = - getRawPtrAndSize(loc, rewriter, adaptor.getRef(), elemType); + getRawPtrAndSize(loc, rewriter, adaptor.getRef(), rank, elemType); auto mpiTraits = MPIImplTraits::get(moduleOp); Value dataType = mpiTraits->getDataType(loc, rewriter, elemType); Value comm = mpiTraits->castComm(loc, rewriter, adaptor.getComm()); @@ -727,6 +746,7 @@ struct RecvOpLowering : public ConvertOpToLLVMPattern { Type i32 = rewriter.getI32Type(); Type i64 = rewriter.getI64Type(); Type elemType = op.getRef().getType().getElementType(); + int64_t rank = op.getRef().getType().getRank(); // ptrType `!llvm.ptr` Type ptrType = LLVM::LLVMPointerType::get(context); @@ -736,7 +756,7 @@ struct RecvOpLowering : public ConvertOpToLLVMPattern { // get MPI_COMM_WORLD, dataType, status_ignore and pointer auto [dataPtr, size] = - getRawPtrAndSize(loc, rewriter, adaptor.getRef(), elemType); + getRawPtrAndSize(loc, rewriter, adaptor.getRef(), rank, elemType); auto mpiTraits = MPIImplTraits::get(moduleOp); Value dataType = mpiTraits->getDataType(loc, rewriter, elemType); Value comm = mpiTraits->castComm(loc, rewriter, adaptor.getComm()); @@ -782,10 +802,12 @@ struct AllGatherOpLowering : public ConvertOpToLLVMPattern { MLIRContext *context = rewriter.getContext(); Type sElemType = op.getSendbuf().getType().getElementType(); Type rElemType = op.getRecvbuf().getType().getElementType(); + int64_t sRank = op.getSendbuf().getType().getRank(); + int64_t rRank = op.getRecvbuf().getType().getRank(); auto [sendPtr, sendSize] = - getRawPtrAndSize(loc, rewriter, adaptor.getSendbuf(), sElemType); + getRawPtrAndSize(loc, rewriter, adaptor.getSendbuf(), sRank, sElemType); auto [recvPtr, recvSize] = - getRawPtrAndSize(loc, rewriter, adaptor.getRecvbuf(), rElemType); + getRawPtrAndSize(loc, rewriter, adaptor.getRecvbuf(), rRank, rElemType); auto moduleOp = op->getParentOfType(); auto mpiTraits = MPIImplTraits::get(moduleOp); @@ -808,8 +830,7 @@ struct AllGatherOpLowering : public ConvertOpToLLVMPattern { // count_recv is the number of elements received from each rank, not total Value nRanks = - mpi::CommSizeOp::create(rewriter, loc, i32, adaptor.getComm()) - .getSize(); + createOrFoldCommSize(rewriter, loc, op.getComm(), adaptor.getComm()); Value recvCountPerRank = LLVM::UDivOp::create(rewriter, loc, i32, recvSize, nRanks); @@ -843,15 +864,17 @@ struct AllReduceOpLowering : public ConvertOpToLLVMPattern { Type i32 = rewriter.getI32Type(); Type i64 = rewriter.getI64Type(); Type elemType = op.getSendbuf().getType().getElementType(); + int64_t sRank = op.getSendbuf().getType().getRank(); + int64_t rRank = op.getRecvbuf().getType().getRank(); // ptrType `!llvm.ptr` Type ptrType = LLVM::LLVMPointerType::get(context); auto moduleOp = op->getParentOfType(); auto mpiTraits = MPIImplTraits::get(moduleOp); auto [sendPtr, sendSize] = - getRawPtrAndSize(loc, rewriter, adaptor.getSendbuf(), elemType); + getRawPtrAndSize(loc, rewriter, adaptor.getSendbuf(), sRank, elemType); auto [recvPtr, recvSize] = - getRawPtrAndSize(loc, rewriter, adaptor.getRecvbuf(), elemType); + getRawPtrAndSize(loc, rewriter, adaptor.getRecvbuf(), rRank, elemType); // If input and output are the same, request in-place operation. if (adaptor.getSendbuf() == adaptor.getRecvbuf()) { diff --git a/mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp b/mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp index 87ae28892fcf7..c765ad5a579c8 100644 --- a/mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp +++ b/mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp @@ -30,6 +30,7 @@ #include "mlir/Dialect/Shard/Transforms/Transforms.h" #include "mlir/Dialect/Tensor/IR/Tensor.h" #include "mlir/Dialect/Utils/StaticValueUtils.h" +#include "mlir/IR/AffineMap.h" #include "mlir/IR/Builders.h" #include "mlir/IR/BuiltinAttributes.h" #include "mlir/IR/BuiltinTypes.h" @@ -620,6 +621,13 @@ struct ConvertAllReduceOp : public CommOpPattern { struct ConvertAllGatherOp : public CommOpPattern { using CommOpPattern::CommOpPattern; + // shard.allgather concatenates along a specified gather-axis. + // mpi.allgather always concatenates along the first dimension and + // there is no MPI operation that allows gathering along an arbitrary axis. + // Hence, if gather-axis!=0, we need to create a temporary buffer + // where we gather along the first dimension and then copy from that + // buffer to the final output along the specified gather-axis. + LogicalResult matchAndRewrite(AllGatherOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { @@ -637,19 +645,95 @@ struct ConvertAllGatherOp : public CommOpPattern { if (!memref::isStaticShapeAndContiguousRowMajor(outType)) return op.emitError( "Expected static shaped memref in contiguous row-major layout."); + int64_t gatherAxis = adaptor.getGatherAxisAttr().getInt(); + auto ctx = op->getContext(); // Get the right communicator Value comm = getComm(*gridOp, adaptor.getGridAxes(), iBuilder); - // Allocate output buffer - Value output = memref::AllocOp::create(iBuilder, outType); + + Value nRanks = + mpi::CommSizeOp::create(iBuilder, iBuilder.getI32Type(), comm) + .getSize(); + nRanks = + arith::IndexCastOp::create(iBuilder, iBuilder.getIndexType(), nRanks); + + Value tmpOutput, gatherDimSz; + if (gatherAxis == 0) { + tmpOutput = memref::AllocOp::create(iBuilder, outType); + } else { + // MPI's allgather always concatenates along the first dimension. + // Create a memref type for the output buffer with adjusted (expanded) + // shape. + SmallVector gatherShape(1, ShapedType::kDynamic); + llvm::append_range(gatherShape, outType.getShape()); + gatherShape[gatherAxis + 1] = ShapedType::kDynamic; + MemRefType gatherType = + MemRefType::get(gatherShape, outType.getElementType()); + gatherDimSz = arith::ConstantIndexOp::create( + iBuilder, outType.getDimSize(gatherAxis)); + gatherDimSz = arith::DivSIOp::create(iBuilder, iBuilder.getIndexType(), + gatherDimSz, nRanks); + // Allocate output buffer + tmpOutput = + memref::AllocOp::create(iBuilder, gatherType, {nRanks, gatherDimSz}); + } // Create the MPI AllGather operation. - mpi::AllGatherOp::create(iBuilder, TypeRange(), input, output, comm); + mpi::AllGatherOp::create(iBuilder, TypeRange(), input, tmpOutput, comm); + + // If gather-axis!=0, copy from gathered buffer to output with the right + // layout. + Value finalOutput = tmpOutput; + if (gatherAxis != 0) { + int64_t nSrcDims = cast(tmpOutput.getType()).getRank(); + assert(nSrcDims == outType.getRank() + 1 && + "Expected gathered type to have rank one more than output type."); + + // Create affine map for copying from gathered buffer to output. + SmallVector dims; + dims.reserve(nSrcDims); + for (unsigned i = 0; i < nSrcDims; ++i) + dims.emplace_back(getAffineDimExpr(i, ctx)); + AffineExpr s = getAffineSymbolExpr(0, ctx); + SmallVector results; + results.reserve(nSrcDims); + for (unsigned i = 0; i < nSrcDims - 1; ++i) { + if (i == gatherAxis) + results.emplace_back(dims[0] * s + dims[gatherAxis + 1]); + else + results.emplace_back(dims[i + 1]); + } + auto affineMap = AffineMap::get(nSrcDims, /*symbols=*/1, results, ctx); + + finalOutput = memref::AllocOp::create(iBuilder, outType); + + // Now build a loop nest to copy from gathered buffer to finalOutput + // It would be nicer to just use a memref.transpose/collapse_shape op but + // these currently only support simpler cases. + Value zero = arith::ConstantIndexOp::create(iBuilder, 0); + SmallVector lbs(nSrcDims, zero); + SmallVector ubs; + for (int64_t d = 0; d < nSrcDims; ++d) + ubs.emplace_back(memref::DimOp::create(iBuilder, tmpOutput, d)); + SmallVector steps(nSrcDims, 1); + auto emitCopy = [&](OpBuilder &builder, Location loc, ValueRange ivs) { + Value v = memref::LoadOp::create(iBuilder, tmpOutput, ivs); + // set symbol value + SmallVector ivss(ivs.begin(), ivs.end()); + ivss.emplace_back(gatherDimSz); + affine::AffineStoreOp::create(iBuilder, v, finalOutput, affineMap, + ivss); + }; + affine::buildAffineLoopNest(iBuilder, op->getLoc(), lbs, ubs, steps, + emitCopy); + + memref::DeallocOp::create(iBuilder, tmpOutput); + } // If the destination is a tensor, cast it to a tensor if (isa(op.getType())) - output = bufferization::ToTensorOp::create(iBuilder, op.getType(), output, - true); - rewriter.replaceOp(op, output); + finalOutput = bufferization::ToTensorOp::create(iBuilder, op.getType(), + finalOutput, true); + rewriter.replaceOp(op, finalOutput); return success(); } }; diff --git a/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp b/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp index 98434357f826f..53585fd34c504 100644 --- a/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp +++ b/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp @@ -95,42 +95,75 @@ static bool contractSupportsMMAMatrixType(vector::ContractionOp contract, return true; } -// Return true if the given map represents a transposed matrix load, -// i.e. (d0, d1, ...) -> (dn-1, dn-2). -static bool isTransposeMatrixLoadMap(AffineMap permutationMap) { +// Test whether the permutation map's first result corresponds to its last +// dimension. +// +// In contexts where we only accept maps that have the last (most minor) +// dimension as exactly one of the two results, this is sufficient to classify +// whether it represents a transpose. +static bool isFirstResultLastMapDimension(AffineMap permutationMap) { MLIRContext *ctx = permutationMap.getContext(); - // Local OpBuilder is fine here, we just build attributes. - OpBuilder b(ctx); - auto nDim = permutationMap.getNumDims(); - AffineExpr zero = b.getAffineConstantExpr(0); - if (nDim < 2) { - // Support transposed+broadcasted cases: affine_map<(d0) -> (d0, 0)>. - AffineExpr dim0 = b.getAffineDimExpr(0); - return permutationMap == AffineMap::get(1, 0, {dim0, zero}, ctx); - } - - AffineExpr innerDim = b.getAffineDimExpr(nDim - 1); - AffineExpr outerDim = b.getAffineDimExpr(nDim - 2); - // Support both transposed and transposed+broadcasted cases. - return permutationMap == AffineMap::get(nDim, 0, {innerDim, outerDim}, ctx) || - permutationMap == AffineMap::get(nDim, 0, {innerDim, zero}, ctx); + const unsigned nDim = permutationMap.getNumDims(); + if (0 == nDim || permutationMap.getResults().empty()) + return false; + return permutationMap.getResult(0) == getAffineDimExpr(nDim - 1, ctx); } -// Return the stide for the second-to-last dimension of |type| if it is a memref -// and has a constant stride. -static std::optional getStaticallyKnownRowStride(ShapedType type) { +// Return the `leadDimension` (row stride) implied by |permutationMap| for +// |type|, if |type| is a memref with a statically-known layout. +// +// The `leadDimension` is the stride (in elements) between consecutive rows in +// the 2D view described by |permutationMap|. This helper supports the subset +// of maps permitted by vector.transfer_read: +// - Exactly 2 results. +// - Each result is either an affine dimension or the constant 0 (broadcast). +// +// Constraints: +// - Requires the most minor memref stride to be 1. +// +// Broadcast: +// - If either result is constant 0, the implied `leadDimension` is 0. +static std::optional +getStaticallyKnownRowStride(ShapedType type, AffineMap permutationMap) { auto memrefType = dyn_cast(type); if (!memrefType) - return false; + return std::nullopt; // If the memref is 0 or 1D the horizontal stride is 0. if (memrefType.getRank() < 2) return 0; int64_t offset = 0; - SmallVector strides; + SmallVector strides; if (failed(memrefType.getStridesAndOffset(strides, offset)) || strides.back() != 1) return std::nullopt; - int64_t stride = strides[strides.size() - 2]; + + if (permutationMap.getNumResults() != 2) + return std::nullopt; + + unsigned strideIndex = strides.size(); + + for (AffineExpr result : permutationMap.getResults()) { + if (auto cst = dyn_cast(result)) { + // Constant value must be zero. + if (0 != cst.getValue()) + return std::nullopt; + // A broadcast result forces row stride to 0. + return 0; + } + auto dim = dyn_cast(result); + // Only Dim & Const results are supported. + if (!dim) + return std::nullopt; + strideIndex = std::min(strideIndex, dim.getPosition()); + } + + // Structural validity check: ensure that the map selects at least one + // dimension more major than the most minor dimension. This also excludes + // degenerate cases where both results map to the most minor dimension. + if (strideIndex + 1 >= strides.size()) + return std::nullopt; + + const int64_t stride = strides[strideIndex]; if (stride == ShapedType::kDynamic) return std::nullopt; return stride; @@ -141,7 +174,9 @@ static bool transferReadSupportsMMAMatrixType(vector::TransferReadOp readOp) { if (readOp.getMask() || readOp.hasOutOfBoundsDim() || readOp.getVectorType().getRank() != 2) return false; - if (!getStaticallyKnownRowStride(readOp.getShapedType())) + + AffineMap permutationMap = readOp.getPermutationMap(); + if (!getStaticallyKnownRowStride(readOp.getShapedType(), permutationMap)) return false; // Only allow integer types if the signedness can be inferred. @@ -150,14 +185,9 @@ static bool transferReadSupportsMMAMatrixType(vector::TransferReadOp readOp) { !isa(*readOp->user_begin()))) return false; - AffineMap map = readOp.getPermutationMap(); MLIRContext *ctx = readOp.getContext(); - AffineExpr innerDim = getAffineDimExpr(map.getNumDims() - 1, ctx); - AffineExpr zero = getAffineConstantExpr(0, ctx); - auto broadcastInnerDim = - AffineMap::get(map.getNumDims(), 0, {zero, innerDim}, ctx); - return map.isMinorIdentity() || map == broadcastInnerDim || - isTransposeMatrixLoadMap(map); + AffineExpr innerDim = getAffineDimExpr(permutationMap.getNumDims() - 1, ctx); + return llvm::is_contained(permutationMap.getResults(), innerDim); } // Return true if the transfer op can be converted to a MMA matrix store. @@ -170,12 +200,18 @@ transferWriteSupportsMMAMatrixType(vector::TransferWriteOp writeOp) { if (writeOp.getMask() || writeOp.hasOutOfBoundsDim() || writeOp.getVectorType().getRank() != 2) return false; - if (!getStaticallyKnownRowStride(writeOp.getShapedType())) + + AffineMap permutationMap = writeOp.getPermutationMap(); + std::optional stride = + getStaticallyKnownRowStride(writeOp.getShapedType(), permutationMap); + // Stride of zero means broadcast which is not permitted for writes. + if (!stride.has_value() || stride.value() == 0) return false; + + MLIRContext *ctx = writeOp.getContext(); + AffineExpr innerDim = getAffineDimExpr(permutationMap.getNumDims() - 1, ctx); // TODO: Support transpose once it is added to GPU dialect ops. - if (!writeOp.getPermutationMap().isMinorIdentity()) - return false; - return true; + return permutationMap.getResult(1) == innerDim; } /// Return true if the constant is a splat to a 2D vector so that it can be @@ -547,21 +583,19 @@ convertTransferReadOp(RewriterBase &rewriter, vector::TransferReadOp op, assert(transferReadSupportsMMAMatrixType(op) && "expected convertible operation"); + AffineMap permutationMap = op.getPermutationMap(); std::optional stride = - getStaticallyKnownRowStride(op.getShapedType()); + getStaticallyKnownRowStride(op.getShapedType(), permutationMap); if (!stride.has_value()) { LDBG() << "no stride"; return rewriter.notifyMatchFailure(op, "no stride"); } - AffineMap map = op.getPermutationMap(); - bool isTranspose = isTransposeMatrixLoadMap(map); - - // Handle broadcast by setting the stride to 0. - if (auto cstExpr = dyn_cast(map.getResult(isTranspose))) { - assert(cstExpr.getValue() == 0); - stride = 0; - } + // transferReadSupportsMMAMatrixType ensures that either of the map results is + // the most minor dimension. Under this constraint, whether the map represents + // a transposed view can be inferred from whether the first result is the most + // minor memref dimension. + const bool isTranspose = isFirstResultLastMapDimension(permutationMap); Value mappingResult = op.getResult(); auto elType = op.getVectorType().getElementType(); @@ -597,7 +631,7 @@ convertTransferWriteOp(RewriterBase &rewriter, vector::TransferWriteOp op, assert(transferWriteSupportsMMAMatrixType(op)); std::optional stride = - getStaticallyKnownRowStride(op.getShapedType()); + getStaticallyKnownRowStride(op.getShapedType(), op.getPermutationMap()); if (!stride.has_value()) { LDBG() << "no stride"; return rewriter.notifyMatchFailure(op, "no stride"); diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp index 05d541fe80356..093951896db4c 100644 --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -1234,9 +1234,64 @@ class VectorInsertOpConversion bool insertIntoInnermostDim = static_cast(positionVec.size()) == destVectorType.getRank(); +// Bounds checking: Validate that indices are within range + for (auto [idx, pos] : llvm::enumerate(positionVec)) { + int64_t dimSize = destVectorType.getDimSize(idx); + + if (auto attr = dyn_cast(pos)) { + // Static index: validate at compile time + int64_t constIdx = cast(attr).getInt(); + // Allow -1 as poison index, otherwise must be in range [0, dimSize) + if (constIdx != -1 && (constIdx < 0 || constIdx >= dimSize)) { + return rewriter.notifyMatchFailure( + insertOp, + "vector.insert position out of bounds: index " + + std::to_string(constIdx) + " for dimension " + + std::to_string(idx) + " with size " + std::to_string(dimSize)); + } + } else { + // Dynamic index: check if it's a constant SSA value + Value dynamicIdx = cast(pos); + if (auto cst = dynamicIdx.getDefiningOp()) { + int64_t idx_val = cst.value(); + if (idx_val < 0 || idx_val >= dimSize) { + return rewriter.notifyMatchFailure( + insertOp, + "vector.insert position out of bounds (const SSA): index " + + std::to_string(idx_val) + " for dimension " + + std::to_string(idx) + " with size " + std::to_string(dimSize)); + } + } + // Note: Non-constant dynamic indices cannot be validated at compile time + } + } + ArrayRef positionOf1DVectorWithinAggregate( positionVec.begin(), insertIntoInnermostDim ? positionVec.size() - 1 : positionVec.size()); + + if (isNestedAggregate) { + std::optional> maybeAggPos; + maybeAggPos = + mlir::getConstantIntValues(positionOf1DVectorWithinAggregate); + if (!maybeAggPos) { + return rewriter.notifyMatchFailure( + insertOp, + "non-constant aggregate position for extract/insertvalue"); + } + + // Bounds check against the aggregate dimensions we index into. + for (int64_t i = 0, e = static_cast(maybeAggPos->size()); i < e; + ++i) { + int64_t idx = (*maybeAggPos)[i]; + int64_t dim = destVectorType.getDimSize(i); + if (idx < 0 || idx >= dim) { + return rewriter.notifyMatchFailure( + insertOp, "out-of-bounds aggregate position"); + } + } + } + OpFoldResult positionOfScalarWithin1DVector; if (destVectorType.getRank() == 0) { // Since the LLVM type converter converts 0D vectors to 1D vectors, we @@ -1258,7 +1313,7 @@ class VectorInsertOpConversion // Aggregate case: the destination for the InsertElementOp needs to be // extracted from the aggregate. if (!llvm::all_of(positionOf1DVectorWithinAggregate, - llvm::IsaPred)) { + [](OpFoldResult ofr) { return ofr.is(); })) { // llvm.extractvalue does not support dynamic dimensions. return failure(); } @@ -1279,6 +1334,11 @@ class VectorInsertOpConversion Value result = sourceAggregate; if (isNestedAggregate) { + if (!llvm::all_of(positionOf1DVectorWithinAggregate, + [](OpFoldResult ofr) { return ofr.is(); })) { + // llvm.insertvalue does not support dynamic dimensions. + return failure(); + } result = LLVM::InsertValueOp::create( rewriter, loc, adaptor.getDest(), sourceAggregate, getAsIntegers(positionOf1DVectorWithinAggregate)); diff --git a/mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp b/mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp index 8a06271eadd84..6df209438447b 100644 --- a/mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp +++ b/mlir/lib/Conversion/XeGPUToXeVM/XeGPUToXeVM.cpp @@ -1056,8 +1056,8 @@ struct ConvertXeGPUToXeVMPass // If the element type is index, convert it to i64. if (llvm::isa(elemType)) elemType = IntegerType::get(&getContext(), 64); - // If the vector is a scalar or has a single element, return the element - if (rank < 1 || type.getNumElements() == 1) + // If the vector rank is 0 or has a single element, return the element + if (rank == 0 || type.getNumElements() == 1) return elemType; // Otherwise, convert the vector to a flat vector type. int64_t sum = llvm::product_of(type.getShape()); @@ -1085,9 +1085,12 @@ struct ConvertXeGPUToXeVMPass // add materialization casts to handle them. // Materialization to convert memref to i64 or i32 depending on global/SLM - auto memrefMaterializationCast = [](OpBuilder &builder, Type type, - ValueRange inputs, - Location loc) -> Value { + // Applies only to target materialization. + // Note: int type to memref materialization is not required as xegpu ops + // currently do not produce memrefs as result. + auto memrefToIntMaterializationCast = [](OpBuilder &builder, Type type, + ValueRange inputs, + Location loc) -> Value { if (inputs.size() != 1) return {}; auto input = inputs.front(); @@ -1146,9 +1149,12 @@ struct ConvertXeGPUToXeVMPass }; // Materialization to convert ui64 to i64 - auto ui64MaterializationCast = [](OpBuilder &builder, Type type, - ValueRange inputs, - Location loc) -> Value { + // Applies only to target materialization. + // Note: i64 to ui64 materialization is not required as xegpu ops + // currently do not produce ui64 as result. + auto ui64ToI64MaterializationCast = [](OpBuilder &builder, Type type, + ValueRange inputs, + Location loc) -> Value { if (inputs.size() != 1) return {}; auto input = inputs.front(); @@ -1163,9 +1169,12 @@ struct ConvertXeGPUToXeVMPass }; // Materialization to convert ui32 to i32 - auto ui32MaterializationCast = [](OpBuilder &builder, Type type, - ValueRange inputs, - Location loc) -> Value { + // Applies only to target materialization. + // Note: i32 to ui32 materialization is not required as xegpu ops + // currently do not produce ui32 as result. + auto ui32ToI32MaterializationCast = [](OpBuilder &builder, Type type, + ValueRange inputs, + Location loc) -> Value { if (inputs.size() != 1) return {}; auto input = inputs.front(); @@ -1180,25 +1189,17 @@ struct ConvertXeGPUToXeVMPass }; // Materialization to convert - // - single element 1D vector to scalar // - bitcast vector of same rank // - shape vector of different rank but same element type - auto vectorMaterializationCast = [](OpBuilder &builder, Type type, - ValueRange inputs, - Location loc) -> Value { + // Applies to both source and target materialization. + auto vectorToVectorMaterializationCast = [](OpBuilder &builder, Type type, + ValueRange inputs, + Location loc) -> Value { if (inputs.size() != 1) return {}; auto input = inputs.front(); if (auto vecTy = dyn_cast(input.getType())) { - if (vecTy.getNumElements() == 1) { - // If the vector has a single element, return the element type. - Value cast = - vector::ExtractOp::create(builder, loc, input, 0).getResult(); - if (vecTy.getElementType() == builder.getIndexType()) - cast = arith::IndexCastUIOp::create(builder, loc, type, cast) - .getResult(); - return cast; - } else if (auto targetVecTy = dyn_cast(type)) { + if (auto targetVecTy = dyn_cast(type)) { // If the target type is a vector of same rank, // bitcast to the target type. if (targetVecTy.getRank() == vecTy.getRank()) @@ -1215,34 +1216,79 @@ struct ConvertXeGPUToXeVMPass return {}; }; + // Materialization to convert + // - single element vector to single element of vector element type + // Applies only to target materialization. + auto vectorToSingleElementMaterializationCast = + [](OpBuilder &builder, Type type, ValueRange inputs, + Location loc) -> Value { + if (inputs.size() != 1) + return {}; + auto input = inputs.front(); + if (auto vecTy = dyn_cast(input.getType())) { + if (type == vecTy.getElementType() || + ((vecTy.getElementType() == builder.getIndexType()) && + type.isInteger())) { + // If the vector rank is 0 or has a single element, + // extract scalar of target type. + auto rank = vecTy.getRank(); + Value cast; + if (rank == 0) { + cast = + vector::ExtractOp::create(builder, loc, input, {}).getResult(); + } else { + cast = vector::ExtractOp::create(builder, loc, input, + SmallVector(rank, 0)) + .getResult(); + } + if (type != vecTy.getElementType()) + cast = arith::IndexCastUIOp::create(builder, loc, type, cast) + .getResult(); + return cast; + } + } + return {}; + }; + + // Materialization to convert + // - single element of vector element type to single element vector // If result type of original op is single element vector and lowered type // is scalar. This materialization cast creates a single element vector by // broadcasting the scalar value. - auto singleElementVectorMaterializationCast = + // Applies only to source materialization. + auto singleElementToVectorMaterializationCast = [](OpBuilder &builder, Type type, ValueRange inputs, Location loc) -> Value { if (inputs.size() != 1) return {}; auto input = inputs.front(); - if (input.getType().isIntOrIndexOrFloat()) { - // If the input is a scalar, and the target type is a vector of single - // element, create a single element vector by broadcasting. - if (auto vecTy = dyn_cast(type)) { - if (vecTy.getNumElements() == 1) { + // If the target type is a vector of rank 0 or single element vector + // of element type matching input type, broadcast input to target type. + if (auto vecTy = dyn_cast(type)) { + if (vecTy.getRank() == 0 || vecTy.getNumElements() == 1) { + if (input.getType() == vecTy.getElementType()) { return vector::BroadcastOp::create(builder, loc, vecTy, input) .getResult(); + } else if (vecTy.getElementType() == builder.getIndexType()) { + Value cast = arith::IndexCastUIOp::create( + builder, loc, builder.getIndexType(), input) + .getResult(); + return vector::BroadcastOp::create(builder, loc, vecTy, cast) + .getResult(); } } } return {}; }; typeConverter.addSourceMaterialization( - singleElementVectorMaterializationCast); - typeConverter.addSourceMaterialization(vectorMaterializationCast); - typeConverter.addTargetMaterialization(memrefMaterializationCast); - typeConverter.addTargetMaterialization(ui32MaterializationCast); - typeConverter.addTargetMaterialization(ui64MaterializationCast); - typeConverter.addTargetMaterialization(vectorMaterializationCast); + singleElementToVectorMaterializationCast); + typeConverter.addSourceMaterialization(vectorToVectorMaterializationCast); + typeConverter.addTargetMaterialization(memrefToIntMaterializationCast); + typeConverter.addTargetMaterialization(ui32ToI32MaterializationCast); + typeConverter.addTargetMaterialization(ui64ToI64MaterializationCast); + typeConverter.addTargetMaterialization( + vectorToSingleElementMaterializationCast); + typeConverter.addTargetMaterialization(vectorToVectorMaterializationCast); ConversionTarget target(getContext()); target.addLegalDialect { } }; +static bool isExtractingContiguousSlice(LLVM::ShuffleVectorOp op) { + if (op.getV1() != op.getV2()) + return false; + auto maskAttr = op.getMask(); + int64_t firstIndex = maskAttr[0]; + for (int64_t i = 1; i < static_cast(maskAttr.size()); ++i) { + int64_t index = maskAttr[i]; + if (index != firstIndex + i) + return false; + } + return true; +} + +// Input vector of a shuffle vector op extracting a contiguous slice is an +// illegal vector in SPIRV kernel if the vector size is > 16 elements. +// To legalize this case, keep applying the following transformations until no +// more match: +// 1. keep hoisting the shuffle vector op past unary element-wise operations +// start with fpext, fptrunc and bitcast for now. +// 2. merge with another shuffle vector op +// 3. merge with load as a smaller load +class HandleVectorExtractPattern + : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + void initialize() { setHasBoundedRewriteRecursion(); } + + LogicalResult matchAndRewrite(LLVM::ShuffleVectorOp op, + PatternRewriter &rewriter) const override { + + if (!isExtractingContiguousSlice(op)) + return failure(); + + auto mask = op.getMask(); + auto loc = op.getLoc(); + auto ty = op.getType(); + // Check source operand to determine rewrite pattern. + auto src = op.getV1(); + // 1. Hoist past unary element-wise operations + if (auto srcOp = src.getDefiningOp()) { + if (isa(srcOp) || isa(srcOp)) { + Value srcInput = srcOp->getOperand(0); + // Create new shuffle vector op with unary input as source. + auto srcVecTy = dyn_cast(srcInput.getType()); + auto newShuffleVecTy = + VectorType::get(mask.size(), srcVecTy.getElementType()); + auto newShuffle = LLVM::ShuffleVectorOp::create( + rewriter, loc, newShuffleVecTy, srcInput, srcInput, mask); + // Create new unary op with new shuffle as input. + Value newUnaryOp; + if (isa(srcOp)) { + newUnaryOp = LLVM::FPExtOp::create(rewriter, loc, ty, newShuffle); + } else { + newUnaryOp = LLVM::FPTruncOp::create(rewriter, loc, ty, newShuffle); + } + rewriter.replaceOp(op, newUnaryOp); + } else if (isa(srcOp)) { + Value srcInput = srcOp->getOperand(0); + // Create new shuffle vector op with unary input as source. + auto srcInputVecTy = dyn_cast(srcInput.getType()); + auto srcInputSize = srcInputVecTy.getNumElements(); + auto srcResVecTy = dyn_cast(srcOp->getResult(0).getType()); + auto srcResSize = srcResVecTy.getNumElements(); + auto maskSize = static_cast(mask.size()); + if (srcInputSize > srcResSize) { + return failure(); + } + if (srcResSize % srcInputSize != 0) { + return failure(); + } + auto maskScale = srcResSize / srcInputSize; + if (maskScale != 1) { + if (mask[0] % maskScale != 0) { + return failure(); + } + // Create a new mask that maps to the source vector + SmallVector newMask; + int32_t newMaskSize = maskSize / maskScale; + int32_t maskStart = mask[0] / maskScale; + for (int32_t i = 0; i < newMaskSize; ++i) { + newMask.push_back(maskStart + i); + } + mask = newMask; + } + auto newShuffleVecTy = + VectorType::get(srcInputSize, srcInputVecTy.getElementType()); + auto newShuffle = LLVM::ShuffleVectorOp::create( + rewriter, loc, newShuffleVecTy, srcInput, srcInput, mask); + // Create new unary op with new shuffle as input. + auto newBitcast = + LLVM::BitcastOp::create(rewriter, loc, ty, newShuffle); + rewriter.replaceOp(op, newBitcast); + } else if (isa(srcOp)) { + // 2. Merge with another shuffle vector op + auto srcShuffle = cast(srcOp); + auto srcMask = srcShuffle.getMask(); + SmallVector combinedMask; + for (auto index : mask) { + combinedMask.push_back(srcMask[index]); + } + auto newShuffle = LLVM::ShuffleVectorOp::create( + rewriter, loc, ty, srcShuffle.getV1(), srcShuffle.getV1(), + DenseI32ArrayAttr::get(rewriter.getContext(), combinedMask)); + rewriter.replaceOp(op, newShuffle); + } else if (isa(srcOp)) { + // 3. Merge with load as a smaller load + auto loadOp = cast(srcOp); + auto loadPtr = loadOp.getAddr(); + auto loadTy = dyn_cast(loadOp.getType()); + auto elemTy = loadTy.getElementType(); + auto firstIndex = mask[0]; + auto newVecTy = VectorType::get(mask.size(), elemTy); + // GEPOp is needed if first index is not zero + if (firstIndex) { + auto newPtr = LLVM::GEPOp::create( + rewriter, loc, + LLVM::LLVMPointerType::get(rewriter.getContext(), + loadPtr.getType().getAddressSpace()), + elemTy, loadPtr, ArrayRef{firstIndex}); + auto newLoad = LLVM::LoadOp::create(rewriter, loc, newVecTy, newPtr); + rewriter.replaceOp(op, newLoad); + } else { + auto newLoad = LLVM::LoadOp::create(rewriter, loc, newVecTy, loadPtr); + rewriter.replaceOp(op, newLoad); + } + } else { + return failure(); + } + } + return success(); + } +}; + //===----------------------------------------------------------------------===// // Pass Definition //===----------------------------------------------------------------------===// @@ -877,28 +1010,22 @@ struct ConvertXeVMToLLVMPass if (failed(applyPartialConversion(getOperation(), target, std::move(patterns)))) signalPassFailure(); - } -}; -} // namespace -//===----------------------------------------------------------------------===// -// ConvertToLLVMPatternInterface implementation -//===----------------------------------------------------------------------===// - -namespace { -/// Implement the interface to convert XeVM to LLVM. -struct XeVMToLLVMDialectInterface : public ConvertToLLVMPatternInterface { - using ConvertToLLVMPatternInterface::ConvertToLLVMPatternInterface; - void loadDependentDialects(MLIRContext *context) const final { - context->loadDialect(); - } - - /// Hook for derived dialect interface to provide conversion patterns - /// and mark dialect legal for the conversion target. - void populateConvertToLLVMConversionPatterns( - ConversionTarget &target, LLVMTypeConverter &typeConverter, - RewritePatternSet &patterns) const final { - populateXeVMToLLVMConversionPatterns(target, patterns); + // Apply in-dialect lowerings to handle illegal vectors + { + RewritePatternSet vectorPatterns(&getContext()); + vectorPatterns.add(&getContext()); + GreedyRewriteConfig config{}; + // folding can remove ops with temporary attributes used to + // represent LLVM metadata, so disable it here. + // Effectively just this single pattern is applied without any + // op folding patterns from dialects. + config.enableFolding(false); + // config.setMaxIterations(GreedyRewriteConfig::kNoLimit); + // config.setMaxNumRewrites(GreedyRewriteConfig::kNoLimit); + (void)applyPatternsGreedily(getOperation(), std::move(vectorPatterns), + config); + } } }; } // namespace @@ -937,9 +1064,3 @@ void ::mlir::populateXeVMToLLVMConversionPatterns(ConversionTarget &target, SubgroupOpWorkitemOpToOCLPattern>( patterns.getContext()); } - -void ::mlir::registerConvertXeVMToLLVMInterface(DialectRegistry ®istry) { - registry.addExtension(+[](MLIRContext *ctx, XeVMDialect *dialect) { - dialect->addInterfaces(); - }); -} diff --git a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp index 87a813a31608d..f9f11c1f9e540 100644 --- a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp +++ b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp @@ -674,12 +674,6 @@ LogicalResult SparseMFMAOp::verify() { // DPPOp //===----------------------------------------------------------------------===// LogicalResult DPPOp::verify() { - Type srcType = getSrc().getType(); - if (srcType.getIntOrFloatBitWidth() > 64) { - return emitOpError("integer and floating point types larger than 64 bits " - "are not supported"); - } - DPPPerm kind = getKind(); Attribute permArgument = getPermArgument().value_or(Attribute{}); @@ -1208,5 +1202,34 @@ void ScaledMFMAOp::getCanonicalizationPatterns(RewritePatternSet &results, results.add(context); } +//===----------------------------------------------------------------------===// +// In-LDS Barrier Operations (gfx1250+) +//===----------------------------------------------------------------------===// + +template +static LogicalResult verifyDsBarrierOpCommon(T &op) { + MemRefType memrefType = llvm::cast(op.getBase().getType()); + if (!hasWorkgroupMemorySpace(memrefType.getMemorySpace())) + return op.emitOpError("barrier must be in workgroup (LDS) memory"); + + return success(); +} + +LogicalResult DsBarrierInitOp::verify() { + return verifyDsBarrierOpCommon(*this); +} + +LogicalResult DsBarrierPollStateOp::verify() { + return verifyDsBarrierOpCommon(*this); +} + +LogicalResult DsAsyncBarrierArriveOp::verify() { + return verifyDsBarrierOpCommon(*this); +} + +LogicalResult DsBarrierArriveOp::verify() { + return verifyDsBarrierOpCommon(*this); +} + #define GET_OP_CLASSES #include "mlir/Dialect/AMDGPU/IR/AMDGPU.cpp.inc" diff --git a/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp b/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp index e350ab4348271..4e9f10b2c525c 100644 --- a/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp +++ b/mlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp @@ -515,7 +515,7 @@ using namespace vector; /// Comparing to the non-vector-dimension case, two additional things are done /// during vectorization of such loops: /// - The resulting vector returned from the loop is reduced to a scalar using -/// `vector.reduce`. +/// `vector.reduction`. /// - In some cases a mask is applied to the vector yielded at the end of the /// loop to prevent garbage values from being written to the accumulator. /// @@ -1645,7 +1645,7 @@ vectorizeLoopNest(std::vector> &loops, } // Replace results of reduction loops with the scalar values computed using - // `vector.reduce` or similar ops. + // `vector.reduction` or similar ops. for (auto resPair : state.loopResultScalarReplacement) resPair.first.replaceAllUsesWith(resPair.second); diff --git a/mlir/lib/Dialect/Bufferization/Transforms/DropEquivalentBufferResults.cpp b/mlir/lib/Dialect/Bufferization/Transforms/DropEquivalentBufferResults.cpp index bc1799099de31..e724af312652d 100644 --- a/mlir/lib/Dialect/Bufferization/Transforms/DropEquivalentBufferResults.cpp +++ b/mlir/lib/Dialect/Bufferization/Transforms/DropEquivalentBufferResults.cpp @@ -74,8 +74,8 @@ static bool operandsEqualFuncArgument(ArrayRef operands, return true; } -LogicalResult -mlir::bufferization::dropEquivalentBufferResults(ModuleOp module) { +LogicalResult mlir::bufferization::dropEquivalentBufferResults( + ModuleOp module, DropBufferResultsOpts options) { IRRewriter rewriter(module.getContext()); DenseMap> callerMap; @@ -83,13 +83,18 @@ mlir::bufferization::dropEquivalentBufferResults(ModuleOp module) { module.walk([&](func::CallOp callOp) { if (func::FuncOp calledFunc = dyn_cast_or_null(callOp.resolveCallable())) { - if (!calledFunc.isPublic() && !calledFunc.isExternal()) + if (calledFunc.isPublic() && !options.modifyPublicFunctions) + return WalkResult::advance(); + if (!calledFunc.isExternal()) callerMap[calledFunc].insert(callOp); } + return WalkResult::advance(); }); for (auto funcOp : module.getOps()) { - if (funcOp.isExternal() || funcOp.isPublic()) + if (funcOp.isPublic() && !options.modifyPublicFunctions) + continue; + if (funcOp.isExternal()) continue; SmallVector returnOps = getReturnOps(funcOp); if (returnOps.empty()) @@ -166,9 +171,18 @@ namespace { struct DropEquivalentBufferResultsPass : bufferization::impl::DropEquivalentBufferResultsPassBase< DropEquivalentBufferResultsPass> { + using Base::Base; + void runOnOperation() override { - if (failed(bufferization::dropEquivalentBufferResults(getOperation()))) + // Convert pass options. + options.modifyPublicFunctions = modifyPublicFunctions; + + if (failed(bufferization::dropEquivalentBufferResults(getOperation(), + options))) return signalPassFailure(); } + +private: + bufferization::DropBufferResultsOpts options; }; } // namespace diff --git a/mlir/lib/Dialect/EmitC/Transforms/WrapFuncInClass.cpp b/mlir/lib/Dialect/EmitC/Transforms/WrapFuncInClass.cpp index 06d7e07005f8a..fc8acd616ba70 100644 --- a/mlir/lib/Dialect/EmitC/Transforms/WrapFuncInClass.cpp +++ b/mlir/lib/Dialect/EmitC/Transforms/WrapFuncInClass.cpp @@ -31,7 +31,7 @@ struct WrapFuncInClassPass Operation *rootOp = getOperation(); RewritePatternSet patterns(&getContext()); - populateFuncPatterns(patterns); + populateWrapFuncInClass(patterns, funcName); walkAndApplyPatterns(rootOp, std::move(patterns)); } @@ -43,8 +43,8 @@ struct WrapFuncInClassPass class WrapFuncInClass : public OpRewritePattern { public: - WrapFuncInClass(MLIRContext *context) - : OpRewritePattern(context) {} + WrapFuncInClass(MLIRContext *context, StringRef funcName) + : OpRewritePattern(context), funcName(funcName) {} LogicalResult matchAndRewrite(emitc::FuncOp funcOp, PatternRewriter &rewriter) const override { @@ -76,7 +76,7 @@ class WrapFuncInClass : public OpRewritePattern { FunctionType funcType = funcOp.getFunctionType(); Location loc = funcOp.getLoc(); FuncOp newFuncOp = - emitc::FuncOp::create(rewriter, loc, ("execute"), funcType); + emitc::FuncOp::create(rewriter, loc, (funcName), funcType); rewriter.createBlock(&newFuncOp.getBody()); newFuncOp.getBody().takeBody(funcOp.getBody()); @@ -102,8 +102,14 @@ class WrapFuncInClass : public OpRewritePattern { rewriter.replaceOp(funcOp, newClassOp); return success(); } + +private: + /// Name of the newly generated member function with body matching the input + /// function. + std::string funcName; }; -void mlir::emitc::populateFuncPatterns(RewritePatternSet &patterns) { - patterns.add(patterns.getContext()); +void mlir::emitc::populateWrapFuncInClass(RewritePatternSet &patterns, + StringRef funcName) { + patterns.add(patterns.getContext(), funcName); } diff --git a/mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp b/mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp index f7fff8e1fd4cf..d6a4dae4c5c32 100644 --- a/mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp +++ b/mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "mlir/Conversion/AffineToStandard/AffineToStandard.h" +#include "mlir/Conversion/GPUCommon/GPUCommonPass.h" #include "mlir/Conversion/MathToXeVM/MathToXeVM.h" #include "mlir/Conversion/Passes.h" #include "mlir/Conversion/SCFToControlFlow/SCFToControlFlow.h" @@ -60,26 +61,36 @@ void buildPreGPUCommonPassPipeline( //===----------------------------------------------------------------------===// void buildGPUPassPipeline(OpPassManager &pm, const mlir::gpu::GPUToXeVMPipelineOptions &options) { + xegpu::XeGPUPropagateLayoutOptions laneLayoutOptions; + laneLayoutOptions.layoutKind = "lane"; + pm.addNestedPass(createCSEPass()); + pm.addNestedPass(createGpuXeVMAttachTarget()); if (options.xegpuOpLevel == "workgroup") { + xegpu::XeGPUPropagateLayoutOptions sgLayoutOptions; + sgLayoutOptions.layoutKind = "subgroup"; + pm.addNestedPass( + xegpu::createXeGPUPropagateLayout(sgLayoutOptions)); pm.addNestedPass(xegpu::createXeGPUWgToSgDistribute()); pm.addNestedPass(createCSEPass()); - xegpu::XeGPUPropagateLayoutOptions layoutOptions; - layoutOptions.layoutKind = "inst"; + pm.addNestedPass(createLowerAffinePass()); + pm.addNestedPass(createCSEPass()); + xegpu::XeGPUPropagateLayoutOptions instDataOptions; + instDataOptions.layoutKind = "inst"; pm.addNestedPass( - xegpu::createXeGPUPropagateLayout(layoutOptions)); + xegpu::createXeGPUPropagateLayout(instDataOptions)); pm.addNestedPass(xegpu::createXeGPUBlocking()); pm.addNestedPass(createCanonicalizerPass()); pm.addNestedPass(createCSEPass()); } if (options.xegpuOpLevel == "subgroup" || options.xegpuOpLevel == "workgroup") { - xegpu::XeGPUPropagateLayoutOptions layoutOptions; - layoutOptions.layoutKind = "lane"; pm.addNestedPass( - xegpu::createXeGPUPropagateLayout(layoutOptions)); + xegpu::createXeGPUPropagateLayout(laneLayoutOptions)); pm.addNestedPass(xegpu::createXeGPUPeepHoleOptimizer()); + pm.addNestedPass(createCanonicalizerPass()); + pm.addNestedPass(createCSEPass()); pm.addNestedPass( - xegpu::createXeGPUPropagateLayout(layoutOptions)); + xegpu::createXeGPUPropagateLayout(laneLayoutOptions)); pm.addNestedPass(xegpu::createXeGPUSubgroupDistribute()); pm.addNestedPass(createCanonicalizerPass()); pm.addNestedPass(createCSEPass()); @@ -119,6 +130,8 @@ void buildPostGPUCommonPassPipeline( pm.addPass(createReconcileUnrealizedCastsPass()); pm.addNestedPass(createCanonicalizerPass()); pm.addNestedPass(createCSEPass()); + // XeVM-to-LLVM must be the last pass before gpu-module-to-binary. + pm.addNestedPass(createConvertXeVMToLLVMPass()); // gpu-module-to-binary { GpuModuleToBinaryPassOptions gpuToModuleBinOptions; diff --git a/mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp b/mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp index ba4703550a3d1..821311a1df5e6 100644 --- a/mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp +++ b/mlir/lib/Dialect/GPU/Transforms/EliminateBarriers.cpp @@ -23,6 +23,7 @@ #include "mlir/Dialect/Vector/IR/VectorOps.h" #include "mlir/IR/Operation.h" #include "mlir/Transforms/GreedyPatternRewriteDriver.h" +#include "llvm/ADT/SetOperations.h" #include "llvm/ADT/TypeSwitch.h" #include "llvm/Support/Debug.h" #include "llvm/Support/DebugLog.h" @@ -78,14 +79,121 @@ static void addAllValuelessEffects( effects.emplace_back(MemoryEffects::Effect::get()); } +/// Looks through known "view-like" ops to find the base memref. +static Value getBase(Value v) { + while (Operation *definingOp = v.getDefiningOp()) { + if (auto viewLike = dyn_cast(definingOp)) { + v = viewLike.getViewSource(); + continue; + } + if (auto transposeOp = dyn_cast(definingOp)) { + v = transposeOp.getIn(); + continue; + } + break; + } + return v; +} + +/// Returns `true` if accesses to the given memory space could potentially be +/// fenced by a barrier synchronizing on the given `fencedAddressSpaces`. If +/// the set of address spaces is not given, it is equal to all possible address +/// spaces. Memory spaces that are not `#gpu.address_space` are deemed to +/// overlap with all GPU address spaces. +static bool isAddressSpacePotentiallyFenced( + Attribute memorySpace, + std::optional> fencedAddressSpaces) { + if (!fencedAddressSpaces) + return true; + + auto gpuMemSpace = dyn_cast_if_present(memorySpace); + if (!gpuMemSpace) + return true; + + // Check if this GPU address space is in the fenced set. + return llvm::is_contained(*fencedAddressSpaces, gpuMemSpace); +} + +/// Succeeds if the effect operates on a memref whose memory space +/// could be one of the given fenced address spaces. This will both look at the +/// address space of the effect's operand and of the view-like operations that +/// define that memref, so as to inspect any memory-space casts or similar +/// operations (like amdgpu buffer casts) that may provide more information. +/// This assumes that directly-conflicting casts (that is, for example, casting +/// a memref in global memory to make it one in workspace memory) can't happen. +static LogicalResult effectMightAffectAddressSpaces( + const MemoryEffects::EffectInstance &effect, + std::optional> fencedAddressSpaces) { + if (!fencedAddressSpaces) + return success(); + + Value value = effect.getValue(); + if (!value) + return success(); + + auto mightMatch = [&](Value v) { + auto memrefType = dyn_cast(v.getType()); + if (!memrefType) + return true; + return isAddressSpacePotentiallyFenced(memrefType.getMemorySpace(), + fencedAddressSpaces); + }; + + if (!mightMatch(value)) + return failure(); + + Value base = value; + while (auto viewLike = base.getDefiningOp()) { + base = viewLike.getViewSource(); + // We assume that we won't see directly incompatible casts, like global => + // flat/null => workspace. + if (!mightMatch(base)) + return failure(); + } + + return success(); +} + +/// Returns `true` if `op` is a `BarrierOp` that fences any address spaces that +/// could overlap with the given fenced address spaces. +static bool isBarrierWithCommonFencedMemory( + Operation *op, + std::optional> fencedAddressSpaces) { + auto barrier = dyn_cast(op); + if (!barrier) + return false; + + std::optional otherFencedSpaces = barrier.getAddressSpaces(); + // Barriers with unspecified fencing fence everything. + if (!otherFencedSpaces) + return true; + // While barriers that fence nothing can't close off our search. + if (otherFencedSpaces->empty()) + return false; + + // If we fence all memory, we've got fencing in common with anything but the + // non-merory barrier. + if (!fencedAddressSpaces) + return true; + + return llvm::any_of( + otherFencedSpaces->getAsRange(), + [&](auto a) { return llvm::is_contained(*fencedAddressSpaces, a); }); +} + /// Collect the memory effects of the given op in 'effects'. Returns 'true' if /// it could extract the effect information from the op, otherwise returns /// 'false' and conservatively populates the list with all possible effects -/// associated with no particular value or symbol. -static bool -collectEffects(Operation *op, - SmallVectorImpl &effects, - bool ignoreBarriers = true) { +/// associated with no particular value or symbol. `fencedAddressSpaces` is, +/// if given, the set of GPU memory spaces that are being synchronized by the +/// barrier being syrchronized - memory operations where the value being +/// impacted is known and either it or its base value have an address space that +/// is known to be distinct from the ones being synchronized on will not be +/// included in the effect set. +static bool collectEffects( + Operation *op, SmallVectorImpl &effects, + std::optional> fencedAddressSpaces, + bool ignoreBarriers = true) { // Skip over barriers to avoid infinite recursion (those barriers would ask // this barrier again). if (ignoreBarriers && isa(op)) @@ -98,14 +206,20 @@ collectEffects(Operation *op, if (auto iface = dyn_cast(op)) { SmallVector localEffects; iface.getEffects(localEffects); - llvm::append_range(effects, localEffects); + // Filter out effects that cannot affect the fenced address spaces. + for (const MemoryEffects::EffectInstance &effect : localEffects) { + if (succeeded( + effectMightAffectAddressSpaces(effect, fencedAddressSpaces))) + effects.push_back(effect); + } return true; } if (op->hasTrait()) { for (auto ®ion : op->getRegions()) { for (auto &block : region) { for (auto &innerOp : block) - if (!collectEffects(&innerOp, effects, ignoreBarriers)) + if (!collectEffects(&innerOp, effects, fencedAddressSpaces, + ignoreBarriers)) return false; } } @@ -120,22 +234,22 @@ collectEffects(Operation *op, /// Get all effects before the given operation caused by other operations in the /// same block. That is, this will not consider operations beyond the block. -static bool -getEffectsBeforeInBlock(Operation *op, - SmallVectorImpl &effects, - bool stopAtBarrier) { +static bool getEffectsBeforeInBlock( + Operation *op, SmallVectorImpl &effects, + std::optional> fencedAddressSpaces, + bool stopAtBarrier) { if (op == &op->getBlock()->front()) return true; for (Operation *it = op->getPrevNode(); it != nullptr; it = it->getPrevNode()) { - if (isa(it)) { + if (isBarrierWithCommonFencedMemory(it, fencedAddressSpaces)) { if (stopAtBarrier) return true; continue; } - if (!collectEffects(it, effects)) + if (!collectEffects(it, effects, fencedAddressSpaces)) return false; } return true; @@ -147,10 +261,10 @@ getEffectsBeforeInBlock(Operation *op, /// set. Returns `true` if the memory effects added to `effects` are exact, /// `false` if they are a conservative over-approximation. The latter means that /// `effects` contain instances not associated with a specific value. -static bool -getEffectsBefore(Operation *op, - SmallVectorImpl &effects, - bool stopAtBarrier) { +static bool getEffectsBefore( + Operation *op, SmallVectorImpl &effects, + std::optional> fencedAddressSpaces, + bool stopAtBarrier) { if (!op->getBlock()) return true; @@ -162,7 +276,7 @@ getEffectsBefore(Operation *op, } // Collect all effects before the op. - getEffectsBeforeInBlock(op, effects, stopAtBarrier); + getEffectsBeforeInBlock(op, effects, fencedAddressSpaces, stopAtBarrier); // Stop if reached the parallel region boundary. if (isParallelRegionBoundary(op->getParentOp())) @@ -171,7 +285,7 @@ getEffectsBefore(Operation *op, Operation *parent = op->getParentOp(); // Otherwise, keep collecting above the parent operation. if (!parent->hasTrait() && - !getEffectsBefore(parent, effects, stopAtBarrier)) + !getEffectsBefore(parent, effects, fencedAddressSpaces, stopAtBarrier)) return false; // If the op is loop-like, collect effects from the trailing operations until @@ -191,7 +305,7 @@ getEffectsBefore(Operation *op, if (isSequentialLoopLike(parent)) { // Assuming loop terminators have no side effects. return getEffectsBeforeInBlock(op->getBlock()->getTerminator(), effects, - /*stopAtBarrier=*/true); + fencedAddressSpaces, /*stopAtBarrier=*/true); } // If the parent operation is not guaranteed to execute its (single-block) @@ -201,7 +315,7 @@ getEffectsBefore(Operation *op, op->getParentOp()->walk([&](Operation *in) { if (conservative) return WalkResult::interrupt(); - if (!collectEffects(in, effects)) { + if (!collectEffects(in, effects, fencedAddressSpaces)) { conservative = true; return WalkResult::interrupt(); } @@ -213,21 +327,21 @@ getEffectsBefore(Operation *op, /// Get all effects after the given operation caused by other operations in the /// same block. That is, this will not consider operations beyond the block. -static bool -getEffectsAfterInBlock(Operation *op, - SmallVectorImpl &effects, - bool stopAtBarrier) { +static bool getEffectsAfterInBlock( + Operation *op, SmallVectorImpl &effects, + std::optional> fencedAddressSpaces, + bool stopAtBarrier) { if (op == &op->getBlock()->back()) return true; for (Operation *it = op->getNextNode(); it != nullptr; it = it->getNextNode()) { - if (isa(it)) { + if (isBarrierWithCommonFencedMemory(it, fencedAddressSpaces)) { if (stopAtBarrier) return true; continue; } - if (!collectEffects(it, effects)) + if (!collectEffects(it, effects, fencedAddressSpaces)) return false; } return true; @@ -239,10 +353,10 @@ getEffectsAfterInBlock(Operation *op, /// set. Returns `true` if the memory effects added to `effects` are exact, /// `false` if they are a conservative over-approximation. The latter means that /// `effects` contain instances not associated with a specific value. -static bool -getEffectsAfter(Operation *op, - SmallVectorImpl &effects, - bool stopAtBarrier) { +static bool getEffectsAfter( + Operation *op, SmallVectorImpl &effects, + std::optional> fencedAddressSpaces, + bool stopAtBarrier) { if (!op->getBlock()) return true; @@ -254,7 +368,7 @@ getEffectsAfter(Operation *op, } // Collect all effects after the op. - getEffectsAfterInBlock(op, effects, stopAtBarrier); + getEffectsAfterInBlock(op, effects, fencedAddressSpaces, stopAtBarrier); Operation *parent = op->getParentOp(); // Stop if reached the parallel region boundary. @@ -264,7 +378,7 @@ getEffectsAfter(Operation *op, // Otherwise, keep collecting below the parent operation. // Don't look into, for example, neighboring functions if (!parent->hasTrait() && - !getEffectsAfter(parent, effects, stopAtBarrier)) + !getEffectsAfter(parent, effects, fencedAddressSpaces, stopAtBarrier)) return false; // If the op is loop-like, collect effects from the leading operations until @@ -282,11 +396,14 @@ getEffectsAfter(Operation *op, // operation `op2` at iteration `i-1` and the side effects must be ordered // appropriately. if (isSequentialLoopLike(parent)) { - if (isa(op->getBlock()->front())) + if (isBarrierWithCommonFencedMemory(&op->getBlock()->front(), + fencedAddressSpaces)) return true; - bool exact = collectEffects(&op->getBlock()->front(), effects); + bool exact = + collectEffects(&op->getBlock()->front(), effects, fencedAddressSpaces); return getEffectsAfterInBlock(&op->getBlock()->front(), effects, + fencedAddressSpaces, /*stopAtBarrier=*/true) && exact; } @@ -298,7 +415,7 @@ getEffectsAfter(Operation *op, op->getParentOp()->walk([&](Operation *in) { if (conservative) return WalkResult::interrupt(); - if (!collectEffects(in, effects)) { + if (!collectEffects(in, effects, fencedAddressSpaces)) { conservative = true; return WalkResult::interrupt(); } @@ -308,35 +425,6 @@ getEffectsAfter(Operation *op, return !conservative; } -/// Looks through known "view-like" ops to find the base memref. -static Value getBase(Value v) { - while (true) { - Operation *definingOp = v.getDefiningOp(); - if (!definingOp) - break; - - bool shouldContinue = - TypeSwitch(v.getDefiningOp()) - .Case( - [&](auto op) { - v = op.getSource(); - return true; - }) - .Case([&](memref::TransposeOp op) { - v = op.getIn(); - return true; - }) - .Case([&](auto op) { - v = op.getSrc(); - return true; - }) - .Default(false); - if (!shouldContinue) - break; - } - return v; -} - /// Returns `true` if the value is defined as a function argument. static bool isFunctionArgument(Value v) { auto arg = dyn_cast(v); @@ -352,8 +440,6 @@ static Value propagatesCapture(Operation *op) { [](ViewLikeOpInterface viewLike) { return viewLike.getViewSource(); }) .Case([](CastOpInterface castLike) { return castLike->getOperand(0); }) .Case([](memref::TransposeOp transpose) { return transpose.getIn(); }) - .Case( - [](auto op) { return op.getSrc(); }) .Default(nullptr); } @@ -584,11 +670,29 @@ class BarrierElimination final : public OpRewritePattern { LDBG() << "checking the necessity of: " << barrier << " " << barrier.getLoc(); + std::optional fencedMemSpaces = barrier.getAddressSpaces(); + if (fencedMemSpaces && fencedMemSpaces->empty()) { + LDBG() + << "barrier is not used to synchronize memory accesses, retain it\n"; + return failure(); + } + + // Convert the fenced address spaces to the proper type for passing through. + SmallVector fencedSpacesStorage; + std::optional> fencedSpaces; + if (fencedMemSpaces) { + fencedSpacesStorage = llvm::map_to_vector( + *fencedMemSpaces, llvm::CastTo); + fencedSpaces = fencedSpacesStorage; + } + SmallVector beforeEffects; - getEffectsBefore(barrier, beforeEffects, /*stopAtBarrier=*/true); + getEffectsBefore(barrier, beforeEffects, fencedSpaces, + /*stopAtBarrier=*/true); SmallVector afterEffects; - getEffectsAfter(barrier, afterEffects, /*stopAtBarrier=*/true); + getEffectsAfter(barrier, afterEffects, fencedSpaces, + /*stopAtBarrier=*/true); if (!haveConflictingEffects(beforeEffects, afterEffects)) { LDBG() << "the surrounding barriers are sufficient, removing " << barrier; diff --git a/mlir/lib/Dialect/GPU/Transforms/PromoteShuffleToAMDGPU.cpp b/mlir/lib/Dialect/GPU/Transforms/PromoteShuffleToAMDGPU.cpp index 67cef8af1e3b5..01da26f88a84d 100644 --- a/mlir/lib/Dialect/GPU/Transforms/PromoteShuffleToAMDGPU.cpp +++ b/mlir/lib/Dialect/GPU/Transforms/PromoteShuffleToAMDGPU.cpp @@ -54,7 +54,8 @@ struct PromoteShuffleToSwizzlePattern Location loc = op.getLoc(); Value res = amdgpu::SwizzleBitModeOp::create( - rewriter, loc, op.getResult(0).getType(), op.getValue(), /*andMask=*/31, + rewriter, loc, op.getResult(0).getType(), op.getValue(), + /*and_mask=*/31, /*orMask=*/0, /*xorMask=*/offsetValue); Value valid = arith::ConstantIntOp::create(rewriter, loc, 1, /*width*/ 1); rewriter.replaceOp(op, {res, valid}); diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp index fa7e9e53cfec7..4c67720654f83 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp @@ -998,7 +998,11 @@ void CallOp::build(OpBuilder &builder, OperationState &state, TypeRange results, /*noreturn=*/nullptr, /*returns_twice=*/nullptr, /*hot=*/nullptr, /*cold=*/nullptr, /*noduplicate=*/nullptr, /*no_caller_saved_registers=*/nullptr, /*nocallback=*/nullptr, - /*modular_format=*/nullptr, + /*modular_format=*/nullptr, /*nobuiltins=*/nullptr, + /*allocsize=*/nullptr, /*optsize=*/nullptr, /*minsize=*/nullptr, + /*nobuiltin=*/nullptr, /*save_reg_params=*/nullptr, + /*zero_call_used_regs=*/nullptr, /*trap_func_name=*/nullptr, + /*default_func_attrs=*/nullptr, /*op_bundle_operands=*/{}, /*op_bundle_tags=*/{}, /*arg_attrs=*/nullptr, /*res_attrs=*/nullptr, /*access_groups=*/nullptr, /*alias_scopes=*/nullptr, @@ -1033,7 +1037,11 @@ void CallOp::build(OpBuilder &builder, OperationState &state, /*returns_twice=*/nullptr, /*hot=*/nullptr, /*cold=*/nullptr, /*noduplicate=*/nullptr, /*no_caller_saved_registers=*/nullptr, /*nocallback=*/nullptr, - /*modular_format=*/nullptr, + /*modular_format=*/nullptr, /*nobuiltins=*/nullptr, + /*allocsize=*/nullptr, /*optsize=*/nullptr, /*minsize=*/nullptr, + /*nobuiltin=*/nullptr, /*save_reg_params=*/nullptr, + /*zero_call_used_regs=*/nullptr, /*trap_func_name=*/nullptr, + /*default_func_attrs=*/nullptr, /*op_bundle_operands=*/{}, /*op_bundle_tags=*/{}, /*arg_attrs=*/nullptr, /*res_attrs=*/nullptr, /*access_groups=*/nullptr, @@ -1054,7 +1062,11 @@ void CallOp::build(OpBuilder &builder, OperationState &state, /*returns_twice=*/nullptr, /*hot=*/nullptr, /*cold=*/nullptr, /*noduplicate=*/nullptr, /*no_caller_saved_registers=*/nullptr, /*nocallback=*/nullptr, - /*modular_format=*/nullptr, + /*modular_format=*/nullptr, /*nobuiltins=*/nullptr, + /*allocsize=*/nullptr, /*optsize=*/nullptr, /*minsize=*/nullptr, + /*nobuiltin=*/nullptr, /*save_reg_params=*/nullptr, + /*zero_call_used_regs=*/nullptr, /*trap_func_name=*/nullptr, + /*default_func_attrs=*/nullptr, /*op_bundle_operands=*/{}, /*op_bundle_tags=*/{}, /*arg_attrs=*/nullptr, /*res_attrs=*/nullptr, /*access_groups=*/nullptr, /*alias_scopes=*/nullptr, @@ -1075,7 +1087,11 @@ void CallOp::build(OpBuilder &builder, OperationState &state, LLVMFuncOp func, /*returns_twice=*/nullptr, /*hot=*/nullptr, /*cold=*/nullptr, /*noduplicate=*/nullptr, /*no_caller_saved_registers=*/nullptr, /*nocallback=*/nullptr, - /*modular_format=*/nullptr, + /*modular_format=*/nullptr, /*nobuiltins=*/nullptr, + /*allocsize=*/nullptr, /*optsize=*/nullptr, /*minsize=*/nullptr, + /*nobuiltin=*/nullptr, /*save_reg_params=*/nullptr, + /*zero_call_used_regs=*/nullptr, /*trap_func_name=*/nullptr, + /*default_func_attrs=*/nullptr, /*op_bundle_operands=*/{}, /*op_bundle_tags=*/{}, /*access_groups=*/nullptr, /*alias_scopes=*/nullptr, /*arg_attrs=*/nullptr, /*res_attrs=*/nullptr, diff --git a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp index 24579f6aa0217..7ac759f635f87 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp @@ -3848,8 +3848,12 @@ struct Conv1DGenerator const int64_t srcWidth = srcElementType.getIntOrFloatBitWidth(); const int64_t dstWidth = dstElementType.getIntOrFloatBitWidth(); - const Type dstType = - cast(val.getType()).cloneWith(std::nullopt, dstElementType); + // Handle both shaped as well as scalar types. + Type dstType; + if (auto shapedType = dyn_cast(val.getType())) + dstType = shapedType.cloneWith(std::nullopt, dstElementType); + else + dstType = dstElementType; if (isa(srcElementType) && isa(dstElementType)) { return arith::SIToFPOp::create(rewriter, loc, dstType, val); @@ -3888,6 +3892,8 @@ struct Conv1DGenerator // convolution. Value conv1dSliceAsOuterProduct(RewriterBase &rewriter, Location loc, Value lhs, Value rhs, Value res) { + lhs = promote(rewriter, loc, lhs, res.getType()); + rhs = promote(rewriter, loc, rhs, res.getType()); return vector::OuterProductOp::create(rewriter, loc, res.getType(), lhs, rhs, res, vector::CombiningKind::ADD); } diff --git a/mlir/lib/Dialect/MPI/IR/MPIOps.cpp b/mlir/lib/Dialect/MPI/IR/MPIOps.cpp index f52c3f99189d2..6cca853071dc2 100644 --- a/mlir/lib/Dialect/MPI/IR/MPIOps.cpp +++ b/mlir/lib/Dialect/MPI/IR/MPIOps.cpp @@ -6,12 +6,11 @@ // //===----------------------------------------------------------------------===// -#include "mlir/Dialect/DLTI/DLTI.h" #include "mlir/Dialect/MPI/IR/MPI.h" +#include "mlir/Dialect/MPI/IR/Utils.h" #include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/IR/Builders.h" #include "mlir/IR/BuiltinAttributes.h" -#include "mlir/IR/PatternMatch.h" using namespace mlir; using namespace mlir::mpi; @@ -45,31 +44,20 @@ struct FoldCast final : public mlir::OpRewritePattern { struct FoldRank final : public mlir::OpRewritePattern { using mlir::OpRewritePattern::OpRewritePattern; - LogicalResult matchAndRewrite(mlir::mpi::CommRankOp op, mlir::PatternRewriter &b) const override { - auto comm = op.getComm(); - if (!comm.getDefiningOp()) - return mlir::failure(); - - // Try to get DLTI attribute for MPI:comm_world_rank - // If found, set worldRank to the value of the attribute. - auto dltiAttr = dlti::query(op, {"MPI:comm_world_rank"}, false); - if (failed(dltiAttr)) - return mlir::failure(); - if (!isa(dltiAttr.value())) - return op->emitError() - << "Expected an integer attribute for MPI:comm_world_rank"; - Value res = arith::ConstantIndexOp::create( - b, op.getLoc(), cast(dltiAttr.value()).getInt()); - if (Value retVal = op.getRetval()) - b.replaceOp(op, {retVal, res}); - else - b.replaceOp(op, res); - return mlir::success(); + return FoldToDLTIConst(op, "MPI:comm_world_rank", b); } }; +struct FoldSize final : public mlir::OpRewritePattern { + using mlir::OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(mlir::mpi::CommSizeOp op, + mlir::PatternRewriter &b) const override { + return FoldToDLTIConst(op, "MPI:comm_world_size", b); + } +}; } // namespace void mlir::mpi::SendOp::getCanonicalizationPatterns( @@ -97,6 +85,11 @@ void mlir::mpi::CommRankOp::getCanonicalizationPatterns( results.add(context); } +void mlir::mpi::CommSizeOp::getCanonicalizationPatterns( + mlir::RewritePatternSet &results, mlir::MLIRContext *context) { + results.add(context); +} + //===----------------------------------------------------------------------===// // TableGen'd op method definitions //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp b/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp index 4ac8505c1223a..496cad5219cae 100644 --- a/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp +++ b/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp @@ -766,7 +766,7 @@ bool CastOp::areCastCompatible(TypeRange inputs, TypeRange outputs) { if (!checkCompatible(aOffset, bOffset)) return false; for (const auto &[index, aStride] : enumerate(aStrides)) { - if (aT.getDimSize(index) == 1) + if (aT.getDimSize(index) == 1 || bT.getDimSize(index) == 1) continue; if (!checkCompatible(aStride, bStrides[index])) return false; diff --git a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp index c3916219d1c93..e8eebc2a1a4c6 100644 --- a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp +++ b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp @@ -3137,9 +3137,10 @@ LogicalResult DeclareReductionOp::verifyRegions() { void TaskOp::build(OpBuilder &builder, OperationState &state, const TaskOperands &clauses) { MLIRContext *ctx = builder.getContext(); - TaskOp::build(builder, state, clauses.allocateVars, clauses.allocatorVars, - makeArrayAttr(ctx, clauses.dependKinds), clauses.dependVars, - clauses.final, clauses.ifExpr, clauses.inReductionVars, + TaskOp::build(builder, state, clauses.affinityVars, clauses.allocateVars, + clauses.allocatorVars, makeArrayAttr(ctx, clauses.dependKinds), + clauses.dependVars, clauses.final, clauses.ifExpr, + clauses.inReductionVars, makeDenseBoolArrayAttr(ctx, clauses.inReductionByref), makeArrayAttr(ctx, clauses.inReductionSyms), clauses.mergeable, clauses.priority, /*private_vars=*/clauses.privateVars, @@ -4534,6 +4535,32 @@ static void printUniformClause(OpAsmPrinter &p, Operation *op, } } +//===----------------------------------------------------------------------===// +// Parser and printer for Affinity Clause +//===----------------------------------------------------------------------===// + +static ParseResult parseAffinityClause( + OpAsmParser &parser, + SmallVectorImpl &affinityVars, + SmallVectorImpl &affinityTypes) { + return parser.parseCommaSeparatedList([&]() -> ParseResult { + if (parser.parseOperand(affinityVars.emplace_back()) || + parser.parseColonType(affinityTypes.emplace_back())) + return failure(); + return success(); + }); +} + +static void printAffinityClause(OpAsmPrinter &p, Operation *op, + ValueRange affinityVars, + TypeRange affinityTypes) { + for (unsigned i = 0; i < affinityVars.size(); ++i) { + if (i) + p << ", "; + p << affinityVars[i] << " : " << affinityTypes[i]; + } +} + #define GET_ATTRDEF_CLASSES #include "mlir/Dialect/OpenMP/OpenMPOpsAttributes.cpp.inc" diff --git a/mlir/lib/Dialect/SCF/IR/CMakeLists.txt b/mlir/lib/Dialect/SCF/IR/CMakeLists.txt index 8c3b93b3c580b..b111117410ba3 100644 --- a/mlir/lib/Dialect/SCF/IR/CMakeLists.txt +++ b/mlir/lib/Dialect/SCF/IR/CMakeLists.txt @@ -13,13 +13,11 @@ add_mlir_dialect_library(MLIRSCFDialect MLIRArithDialect MLIRControlFlowDialect MLIRDialectUtils - MLIRExecutionProgressOpInterface MLIRFunctionInterfaces MLIRIR MLIRLoopLikeInterface MLIRSideEffectInterfaces MLIRTensorDialect - MLIRUBDialect MLIRValueBoundsOpInterface MLIRTransformUtils ) diff --git a/mlir/lib/Dialect/SCF/IR/SCF.cpp b/mlir/lib/Dialect/SCF/IR/SCF.cpp index 6d8765f7de536..c46a0577c4b96 100644 --- a/mlir/lib/Dialect/SCF/IR/SCF.cpp +++ b/mlir/lib/Dialect/SCF/IR/SCF.cpp @@ -16,7 +16,6 @@ #include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/Dialect/SCF/IR/DeviceMappingInterface.h" #include "mlir/Dialect/Tensor/IR/Tensor.h" -#include "mlir/Dialect/UB/IR/UBOps.h" #include "mlir/IR/BuiltinAttributes.h" #include "mlir/IR/IRMapping.h" #include "mlir/IR/Matchers.h" @@ -510,10 +509,8 @@ void ForOp::print(OpAsmPrinter &p) { p.printRegion(getRegion(), /*printEntryBlockArgs=*/false, /*printBlockTerminators=*/!getInitArgs().empty()); - SmallVector elidedAttrs = {getUnsignedCmpAttrName().strref()}; - if (getMustProgress()) // true is default, elide it - elidedAttrs.push_back(getMustProgressAttrName().strref()); - p.printOptionalAttrDict((*this)->getAttrs(), elidedAttrs); + p.printOptionalAttrDict((*this)->getAttrs(), + /*elidedAttrs=*/getUnsignedCmpAttrName().strref()); } ParseResult ForOp::parse(OpAsmParser &parser, OperationState &result) { @@ -694,24 +691,6 @@ void ForOp::getSuccessorRegions(RegionBranchPoint point, } } - // Infinite loops (lb < ub and step size 0) enter the loop body and never - // leave it. - std::optional> lbCst = - getConstantAPIntValue(getLowerBound()); - std::optional> ubCst = - getConstantAPIntValue(getUpperBound()); - std::optional> stepCst = - getConstantAPIntValue(getStep()); - if (lbCst.has_value() && ubCst.has_value() && stepCst.has_value()) { - bool atLeastOneIteration = - (getUnsignedCmp() && lbCst->first.ult(ubCst->first)) || - (!getUnsignedCmp() && lbCst->first.slt(ubCst->first)); - if (atLeastOneIteration && stepCst->first.isZero()) { - regions.push_back(RegionSuccessor(&getRegion())); - return; - } - } - // Both the operation itself and the region may be branching into the body or // back into the operation itself. It is possible for loop not to enter the // body. @@ -724,8 +703,6 @@ ValueRange ForOp::getSuccessorInputs(RegionSuccessor successor) { : ValueRange(getRegionIterArgs()); } -bool ForOp::mustProgress() { return getMustProgress(); } - SmallVector ForallOp::getLoopRegions() { return {&getRegion()}; } /// Promotes the loop body of a forallOp to its containing block if it can be @@ -1027,8 +1004,6 @@ void ForOp::getCanonicalizationPatterns(RewritePatternSet &results, auto forOp = cast(blockArg.getOwner()->getParentOp()); return forOp.getLowerBound(); }); - ub::populateEraseInfiniteRegionBranchLoopPattern(results, - ForOp::getOperationName()); } std::optional ForOp::getConstantStep() { @@ -3235,16 +3210,6 @@ void WhileOp::build(::mlir::OpBuilder &odsBuilder, afterBuilder(odsBuilder, odsState.location, afterBlock->getArguments()); } -void WhileOp::build(::mlir::OpBuilder &odsBuilder, - ::mlir::OperationState &odsState, TypeRange resultTypes, - ValueRange inits, bool mustProgress) { - odsState.addOperands(inits); - for (unsigned i = 0; i < 2; ++i) - (void)odsState.addRegion(); - odsState.addTypes(resultTypes); - odsState.addAttribute("mustProgress", odsBuilder.getBoolAttr(mustProgress)); -} - ConditionOp WhileOp::getConditionOp() { return cast(getBeforeBody()->getTerminator()); } @@ -3308,8 +3273,6 @@ ValueRange WhileOp::getSuccessorInputs(RegionSuccessor successor) { llvm_unreachable("invalid region successor"); } -bool WhileOp::mustProgress() { return getMustProgress(); } - SmallVector WhileOp::getLoopRegions() { return {&getBefore(), &getAfter()}; } @@ -3369,10 +3332,7 @@ void scf::WhileOp::print(OpAsmPrinter &p) { p.printRegion(getBefore(), /*printEntryBlockArgs=*/false); p << " do "; p.printRegion(getAfter()); - SmallVector elidedAttrs; - if (getMustProgress()) // true is default, elide it - elidedAttrs.push_back(getMustProgressAttrName().strref()); - p.printOptionalAttrDictWithKeyword((*this)->getAttrs(), elidedAttrs); + p.printOptionalAttrDictWithKeyword((*this)->getAttrs()); } /// Verifies that two ranges of types match, i.e. have the same number of @@ -3748,8 +3708,6 @@ void WhileOp::getCanonicalizationPatterns(RewritePatternSet &results, results, WhileOp::getOperationName()); populateRegionBranchOpInterfaceInliningPattern(results, WhileOp::getOperationName()); - ub::populateEraseInfiniteRegionBranchLoopPattern(results, - WhileOp::getOperationName()); } //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp b/mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp index 152fb226993e9..ddcbda86cf1f3 100644 --- a/mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp +++ b/mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp @@ -49,9 +49,8 @@ struct ForLoopLoweringPattern : public OpRewritePattern { SmallVector initArgs; initArgs.push_back(forOp.getLowerBound()); llvm::append_range(initArgs, forOp.getInitArgs()); - auto whileOp = - WhileOp::create(rewriter, forOp.getLoc(), lcvTypes, initArgs); - whileOp->setAttrs(forOp->getAttrDictionary()); + auto whileOp = WhileOp::create(rewriter, forOp.getLoc(), lcvTypes, initArgs, + forOp->getAttrs()); // 'before' region contains the loop condition and forwarding of iteration // arguments to the 'after' region. diff --git a/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp b/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp index 4d22a5e97ba4a..8bfc9e9dfad3d 100644 --- a/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp +++ b/mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp @@ -1509,6 +1509,14 @@ FailureOr> mlir::scf::yieldReplacementForFusedProducer( auto tilableOp = cast(originalOwner); // b. get iterDomain Offset and Sizes based on sliceOp tile SmallVector iterDomainOffset, iterDomainSizes; + // Set insertion point before any operations that might create new SSA + // values used in offset/size computations. This ensures all values created + // by getIterationDomainTileFromResultTile and getResultTilePosition + // dominate the extract_slice operations created later. + if (auto tiledDestStyleOp = + dyn_cast(tiledOwner)) { + rewriter.setInsertionPoint(tiledDestStyleOp); + } // skip tensor.pack/unpack/pad, which expects single opResult if (tilableOp->getNumResults() > 1 && failed(tilableOp.getIterationDomainTileFromResultTile( @@ -1550,7 +1558,6 @@ FailureOr> mlir::scf::yieldReplacementForFusedProducer( // necessary if (auto tiledDestStyleOp = dyn_cast(tiledOwner)) { - rewriter.setInsertionPoint(tiledDestStyleOp); for (const auto &&[index, newRegionArg] : llvm::enumerate(newRegionIterArgs)) { auto destSlice = tensor::ExtractSliceOp::create( diff --git a/mlir/lib/Dialect/SCF/Utils/Utils.cpp b/mlir/lib/Dialect/SCF/Utils/Utils.cpp index 3892904646da7..f8a4f057c9f0d 100644 --- a/mlir/lib/Dialect/SCF/Utils/Utils.cpp +++ b/mlir/lib/Dialect/SCF/Utils/Utils.cpp @@ -391,18 +391,14 @@ FailureOr mlir::loopUnrollByFactor( int64_t ubCst = getConstantIntValue(forOp.getUpperBound()).value(); int64_t stepCst = getConstantIntValue(forOp.getStep()).value(); if (unrollFactor == 1) { - if (*constTripCount == 1 && + if (constTripCount->isOne() && failed(forOp.promoteIfSingleIteration(rewriter))) return failure(); return UnrolledLoopInfo{forOp, std::nullopt}; } - // TODO(#178506): This may overflow for large trip counts. Should use - // uint64_t. - int64_t tripCountEvenMultiple = - constTripCount->getZExtValue() - - (constTripCount->getZExtValue() % unrollFactor); - // TODO(#178506): This may overflow when computing upperBoundUnrolledCst. + uint64_t tripCount = constTripCount->getZExtValue(); + uint64_t tripCountEvenMultiple = tripCount - tripCount % unrollFactor; int64_t upperBoundUnrolledCst = lbCst + tripCountEvenMultiple * stepCst; int64_t stepUnrolledCst = stepCst * unrollFactor; @@ -504,7 +500,7 @@ LogicalResult mlir::loopUnrollFull(scf::ForOp forOp) { const APInt &tripCount = *mayBeConstantTripCount; if (tripCount.isZero()) return success(); - if (tripCount.getZExtValue() == 1) + if (tripCount.isOne()) return forOp.promoteIfSingleIteration(rewriter); return loopUnrollByFactor(forOp, tripCount.getZExtValue()); } @@ -552,12 +548,13 @@ LogicalResult mlir::loopUnrollJamByFactor(scf::ForOp forOp, LDBG() << "failed to unroll and jam: trip count could not be determined"; return failure(); } - if (unrollJamFactor > tripCount->getZExtValue()) { + uint64_t tripCountValue = tripCount->getZExtValue(); + if (unrollJamFactor > tripCountValue) { LDBG() << "unroll and jam factor is greater than trip count, set factor to " "trip " "count"; - unrollJamFactor = tripCount->getZExtValue(); - } else if (tripCount->getZExtValue() % unrollJamFactor != 0) { + unrollJamFactor = tripCountValue; + } else if (tripCountValue % unrollJamFactor != 0) { LDBG() << "failed to unroll and jam: unsupported trip count that is not a " "multiple of unroll jam factor"; return failure(); @@ -1563,23 +1560,21 @@ bool mlir::isPerfectlyNestedForLoops( return true; } -llvm::SmallVector +llvm::SmallVector mlir::getConstLoopTripCounts(mlir::LoopLikeOpInterface loopOp) { std::optional> loBnds = loopOp.getLoopLowerBounds(); std::optional> upBnds = loopOp.getLoopUpperBounds(); std::optional> steps = loopOp.getLoopSteps(); if (!loBnds || !upBnds || !steps) return {}; - // TODO(#178506): The result should be SmallVector and use uint64_t - // for trip counts. - llvm::SmallVector tripCounts; + llvm::SmallVector tripCounts; for (auto [lb, ub, step] : llvm::zip(*loBnds, *upBnds, *steps)) { // TODO(#178506): Signedness is not handled correctly here. std::optional numIter = constantTripCount( lb, ub, step, /*isSigned=*/true, scf::computeUbMinusLb); if (!numIter) return {}; - tripCounts.push_back(numIter->getZExtValue()); + tripCounts.push_back(*numIter); } return tripCounts; } @@ -1610,7 +1605,7 @@ FailureOr mlir::parallelLoopUnrollByFactors( // Make sure that the unroll factors divide the iteration space evenly // TODO: Support unrolling loops with dynamic iteration spaces. - const llvm::SmallVector tripCounts = getConstLoopTripCounts(op); + const llvm::SmallVector tripCounts = getConstLoopTripCounts(op); if (tripCounts.empty()) return rewriter.notifyMatchFailure( op, "Failed to compute constant trip counts for the loop. Note that " @@ -1618,7 +1613,7 @@ FailureOr mlir::parallelLoopUnrollByFactors( for (unsigned dimIdx = firstLoopDimIdx; dimIdx < numLoops; dimIdx++) { const uint64_t unrollFactor = unrollFactors[dimIdx - firstLoopDimIdx]; - if (tripCounts[dimIdx] % unrollFactor) + if (tripCounts[dimIdx].urem(unrollFactor) != 0) return rewriter.notifyMatchFailure( op, "Unroll factors don't divide the iteration space evenly"); } diff --git a/mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp b/mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp index 4d0aedca27d42..5c2d538a00b17 100644 --- a/mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/ControlFlowOps.cpp @@ -360,6 +360,14 @@ static bool hasOtherMerge(Region ®ion) { }); } +/// Returns true if types yielded by `spirv.mlir.merge` in the region match +/// those returned by the `op`. +static bool returnTypesMatch(Region ®ion, Operation *op) { + auto mergeOps = region.getOps(); + Operation *mergeOp = llvm::getSingleElement(mergeOps); + return llvm::equal(mergeOp->getOperandTypes(), op->getResultTypes()); +} + LogicalResult LoopOp::verifyRegions() { auto *op = getOperation(); @@ -445,6 +453,10 @@ LogicalResult LoopOp::verifyRegions() { } } + if (!returnTypesMatch(region, op)) + return emitOpError( + "result types do not match types yielded with `spirv.mlir.merge`"); + return success(); } @@ -609,6 +621,10 @@ LogicalResult SelectionOp::verifyRegions() { if (region.hasOneBlock()) return emitOpError("must have a selection header block"); + if (!returnTypesMatch(region, op)) + return emitOpError( + "result types do not match types yielded with `spirv.mlir.merge`"); + return success(); } diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp index 9ab3bdc6ab102..2bae0d23c9f00 100644 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.cpp @@ -251,9 +251,8 @@ struct MulExtendedFold final : OpRewritePattern { {lhsAttr, rhsAttr}, [](const APInt &a, const APInt &b) { if (IsSigned) { return llvm::APIntOps::mulhs(a, b); - } else { - return llvm::APIntOps::mulhu(a, b); } + return llvm::APIntOps::mulhu(a, b); }); if (!highBits) diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp index 7c3bfd72115e6..78f33c238d414 100644 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp @@ -167,11 +167,11 @@ static Type parseAndVerifyType(SPIRVDialect const &dialect, if (parser.parseType(type)) return Type(); - // Allow SPIR-V dialect types + // Allow SPIR-V dialect types. if (&type.getDialect() == &dialect) return type; - // Check other allowed types + // Check other allowed types. if (auto t = dyn_cast(type)) { // TODO: All float types are allowed for now, but this should be fixed. } else if (auto t = dyn_cast(type)) { @@ -186,12 +186,23 @@ static Type parseAndVerifyType(SPIRVDialect const &dialect, parser.emitError(typeLoc, "only 1-D vector allowed but found ") << t; return Type(); } + if (t.getNumElements() < 2) { + parser.emitError(typeLoc, "SPIR-V does not allow one-element vectors"); + return Type(); + } if (t.getNumElements() > 4) { parser.emitError( typeLoc, "vector length has to be less than or equal to 4 but found ") << t.getNumElements(); return Type(); } + if (!isa(t.getElementType())) { + parser.emitError( + typeLoc, + "vector element type must be a SPIR-V scalar type but found ") + << t.getElementType(); + return Type(); + } } else if (auto t = dyn_cast(type)) { if (!isa(t.getElementType())) { parser.emitError( diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp index 342a47cdefbf0..63b51d1836f75 100644 --- a/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp +++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVTypes.cpp @@ -551,6 +551,11 @@ void TypeExtensionVisitor::addConcrete(ScalarType type) { extensions.push_back(ext); } + if (isa(type)) { + static constexpr auto ext = Extension::SPV_EXT_float8; + extensions.push_back(ext); + } + // 8- or 16-bit integer/floating-point numbers will require extra extensions // to appear in interface storage classes. See SPV_KHR_16bit_storage and // SPV_KHR_8bit_storage for more details. @@ -648,6 +653,15 @@ void TypeCapabilityVisitor::addConcrete(ScalarType type) { } else { assert(isa(type)); switch (bitwidth) { + case 8: { + if (isa(type)) { + static constexpr auto cap = Capability::Float8EXT; + capabilities.push_back(cap); + } else { + llvm_unreachable("invalid 8-bit float type to getCapabilities"); + } + break; + } case 16: { if (isa(type)) { static constexpr auto cap = Capability::BFloat16TypeKHR; diff --git a/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp b/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp index d885d2c871e3f..d837947e0dc3b 100644 --- a/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp +++ b/mlir/lib/Dialect/Tensor/IR/TensorOps.cpp @@ -2041,6 +2041,16 @@ static LogicalResult verifyTensorReshapeOp(TensorReshapeOp op, verifyReshapeLikeTypes(op, expandedType, collapsedType, isExpansion))) return failure(); + // Reshape must preserve the number of elements when statically known. + if (expandedType.hasStaticShape() && collapsedType.hasStaticShape()) { + int64_t expandedNumElements = expandedType.getNumElements(); + int64_t collapsedNumElements = collapsedType.getNumElements(); + if (expandedNumElements != collapsedNumElements) { + return op.emitOpError("number of elements must be preserved: ") + << expandedNumElements << " != " << collapsedNumElements; + } + } + auto maps = op.getReassociationMaps(); RankedTensorType expectedType = CollapseShapeOp::inferCollapsedType(expandedType, maps); @@ -2051,8 +2061,8 @@ static LogicalResult verifyTensorReshapeOp(TensorReshapeOp op, } LogicalResult ExpandShapeOp::verify() { - auto srcType = getSrcType(); - auto resultType = getResultType(); + RankedTensorType srcType = getSrc().getType(); + RankedTensorType resultType = getResult().getType(); if ((int64_t)getStaticOutputShape().size() != resultType.getRank()) return emitOpError("expected number of static shape dims to be equal to " @@ -2077,7 +2087,10 @@ LogicalResult CollapseShapeOp::verify() { [](ReassociationIndices group) { return group.empty(); })) { return op.emitOpError("reassociation indices must not be empty"); } - return verifyTensorReshapeOp(*this, getSrcType(), getResultType()); + RankedTensorType srcType = op.getSrc().getType(); + RankedTensorType resultType = op.getResult().getType(); + + return verifyTensorReshapeOp(op, srcType, resultType); } namespace { diff --git a/mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp b/mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp index 07a0b6742d48a..42033ce8a3b02 100644 --- a/mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp +++ b/mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp @@ -986,7 +986,7 @@ binaryFolder(DenseElementsAttr lhs, DenseElementsAttr rhs, ShapedType returnTy, return {}; } -struct FoldAddAdaptor { +struct AddFoldAdaptor { static FailureOr fold(const APInt &lhs, const APInt &rhs, const bool isUnsigned) { bool overflow; @@ -1002,7 +1002,7 @@ struct FoldAddAdaptor { } }; -struct FoldSubAdaptor { +struct SubFoldAdaptor { static FailureOr fold(const APInt &lhs, const APInt &rhs, const bool isUnsigned) { bool overflow; @@ -1018,7 +1018,131 @@ struct FoldSubAdaptor { } }; -struct FoldGreaterAdaptor { +struct MulFoldAdaptor { + static FailureOr fold(const APInt &lhs, const APInt &rhs, + const bool isUnsigned) { + + const unsigned originalWidth = lhs.getBitWidth(); + + // Check same type + if (lhs.getBitWidth() != rhs.getBitWidth()) { + return failure(); + } + + // If either is `0` + if (lhs == 0 || rhs == 0) + return APInt::getZero(originalWidth); + + bool overflow = false; + APInt const result = + isUnsigned ? lhs.umul_ov(rhs, overflow) : lhs.smul_ov(rhs, overflow); + + if (overflow) + return failure(); + + return result.trunc(originalWidth); + } + + static FailureOr fold(const APFloat &lhs, const APFloat &rhs) { + return lhs * rhs; + } +}; + +static bool signsDiffer(const APInt &a, const APInt &b) { + return a.isNegative() != b.isNegative(); +} + +template +struct DivFoldAdaptor { + static FailureOr fold(const APInt &lhs, const APInt &rhs, + bool isUnsigned) { + if (lhs.getBitWidth() != rhs.getBitWidth()) + return failure(); + if (rhs.isZero()) + return failure(); + + if (isUnsigned) { + APInt q{}; + APInt r{}; + APInt::udivrem(lhs, rhs, q, r); + if (!r.isZero() && Ceil) { + return q + 1; + } + return q; + } + + // Signed: start from trunc-toward-zero, then adjust to ceil. + bool overflow{false}; + APInt const q = lhs.sdiv_ov(rhs, overflow); + if (overflow) + return failure(); + APInt const r = lhs.srem(rhs); + + if (Ceil && !r.isZero() && !signsDiffer(lhs, rhs)) { + // Same sign => exact quotient is positive; trunc is below ceil => + // increment q. + return q + 1; + } + return q; + } + + static FailureOr fold(const APFloat &lhs, const APFloat &rhs) { + return lhs / rhs; + } +}; + +struct ModFoldAdaptor { + static FailureOr fold(const APInt &lhs, const APInt &rhs, + bool isUnsigned) { + if (lhs.getBitWidth() != rhs.getBitWidth()) + return failure(); + if (lhs.isNegative() || (!rhs.isStrictlyPositive())) + return failure(); + + if (isUnsigned) { + return lhs.urem(rhs); + } + + return lhs.srem(rhs); + } + + static FailureOr fold(const APFloat &lhs, const APFloat &rhs) { + auto t = lhs; + auto const r = t.mod(rhs); + if (llvm::APFloatBase::opStatus::opOK == r) { + return t; + } + return failure(); + } +}; + +struct MaxFoldAdaptor { + static FailureOr fold(const APInt &lhs, const APInt &rhs, + bool isUnsigned) { + if (lhs.getBitWidth() != rhs.getBitWidth()) + return failure(); + return lhs.getSExtValue() >= rhs.getSExtValue() ? lhs : rhs; + } + + static FailureOr fold(const APFloat &lhs, const APFloat &rhs) { + return lhs >= rhs ? lhs : rhs; + } +}; + +struct MinFoldAdaptor { + static FailureOr fold(const APInt &lhs, const APInt &rhs, + bool isUnsigned) { + if (lhs.getBitWidth() != rhs.getBitWidth()) + return failure(); + return lhs.getSExtValue() <= rhs.getSExtValue() ? lhs : rhs; + } + + static FailureOr fold(const APFloat &lhs, const APFloat &rhs) { + return lhs <= rhs ? lhs : rhs; + } +}; + +struct GreaterFoldAdaptor { static FailureOr fold(const APInt &lhs, const APInt &rhs, const bool isUnsigned) { return isUnsigned ? APInt(1, lhs.ugt(rhs)) : APInt(1, lhs.sgt(rhs)); @@ -1029,7 +1153,7 @@ struct FoldGreaterAdaptor { } }; -struct FoldGreaterEqualAdaptor { +struct GreaterEqualFoldAdaptor { static FailureOr fold(const APInt &lhs, const APInt &rhs, const bool isUnsigned) { return isUnsigned ? APInt(1, lhs.uge(rhs)) : APInt(1, lhs.sge(rhs)); @@ -1040,7 +1164,7 @@ struct FoldGreaterEqualAdaptor { } }; -struct FoldEqualAdaptor { +struct EqualFoldAdaptor { static FailureOr fold(const APInt &lhs, const APInt &rhs, const bool isUnsigned) { return APInt(1, lhs == rhs); @@ -1097,7 +1221,7 @@ OpFoldResult AddOp::fold(FoldAdaptor adaptor) { if (!lhsAttr || !rhsAttr) return {}; - return binaryFolder(lhsAttr, rhsAttr, resultTy); + return binaryFolder(lhsAttr, rhsAttr, resultTy); } OpFoldResult ArgMaxOp::fold(FoldAdaptor adaptor) { @@ -1149,8 +1273,12 @@ OpFoldResult IntDivOp::fold(FoldAdaptor adaptor) { APInt l = lhsAttr.getSplatValue(); APInt r = rhsAttr.getSplatValue(); if (!r.isZero()) { - APInt result = l.sdiv(r); - return DenseElementsAttr::get(resultTy, result); + auto intTy = dyn_cast(resultETy); + auto const result = + DivFoldAdaptor::fold(l, r, intTy.isUnsigned()); + if (failed(result)) + return {}; + return DenseElementsAttr::get(resultTy, result.value()); } } @@ -1162,7 +1290,11 @@ namespace { // return nullopt if result is not in range of int32_t when shift > 0 std::optional mulInt(APInt lhs, APInt rhs, int32_t shift, unsigned bitwidth) { - APInt result = lhs.sext(64) * rhs.sext(64); + bool overflow = false; + APInt result = lhs.sext(64).smul_ov(rhs.sext(64), overflow); + + if (overflow) + return std::nullopt; if (shift > 0) { auto round = APInt(64, 1) << (shift - 1); @@ -1278,7 +1410,7 @@ OpFoldResult SubOp::fold(FoldAdaptor adaptor) { if (!lhsAttr || !rhsAttr) return {}; - return binaryFolder(lhsAttr, rhsAttr, resultTy); + return binaryFolder(lhsAttr, rhsAttr, resultTy); } OpFoldResult GreaterOp::fold(FoldAdaptor adaptor) { @@ -1291,7 +1423,7 @@ OpFoldResult GreaterOp::fold(FoldAdaptor adaptor) { if (!lhsAttr || !rhsAttr) return {}; - return binaryFolder(lhsAttr, rhsAttr, resultTy); + return binaryFolder(lhsAttr, rhsAttr, resultTy); } OpFoldResult GreaterEqualOp::fold(FoldAdaptor adaptor) { @@ -1304,7 +1436,7 @@ OpFoldResult GreaterEqualOp::fold(FoldAdaptor adaptor) { if (!lhsAttr || !rhsAttr) return {}; - return binaryFolder(lhsAttr, rhsAttr, resultTy); + return binaryFolder(lhsAttr, rhsAttr, resultTy); } OpFoldResult EqualOp::fold(FoldAdaptor adaptor) { @@ -1327,7 +1459,7 @@ OpFoldResult EqualOp::fold(FoldAdaptor adaptor) { if (!lhsAttr || !rhsAttr) return {}; - return binaryFolder(lhsAttr, rhsAttr, resultTy); + return binaryFolder(lhsAttr, rhsAttr, resultTy); } OpFoldResult CastOp::fold(FoldAdaptor adaptor) { @@ -1750,18 +1882,19 @@ OpFoldResult tosa::ReciprocalOp::fold(FoldAdaptor adaptor) { return {}; } -OpFoldResult tosa::AddShapeOp::fold(FoldAdaptor adaptor) { +template +OpFoldResult binaryFold(Op *op) { auto input1ConstShape = - dyn_cast(getInput1().getDefiningOp()); + dyn_cast(op->getInput1().getDefiningOp()); auto input2ConstShape = - dyn_cast(getInput2().getDefiningOp()); + dyn_cast(op->getInput2().getDefiningOp()); if (!input1ConstShape || !input2ConstShape) return {}; const auto input1Attr = cast(input1ConstShape.getValues()); const auto input2Attr = cast(input2ConstShape.getValues()); - return binaryFolder( + return binaryFolder( input1Attr, input2Attr, input1Attr.getType(), /*foldDenseValues=*/true); } @@ -1779,3 +1912,35 @@ OpFoldResult tosa::DimOp::fold(FoldAdaptor adaptor) { RankedTensorType::get(/*rank=*/1, builder.getIndexType()); return DenseElementsAttr::get(resultAttrTy, dimSize); } + +OpFoldResult tosa::AddShapeOp::fold(FoldAdaptor adaptor) { + return binaryFold(this); +} + +OpFoldResult tosa::SubShapeOp::fold(FoldAdaptor adaptor) { + return binaryFold(this); +} + +OpFoldResult tosa::MulShapeOp::fold(FoldAdaptor adaptor) { + return binaryFold(this); +} + +OpFoldResult tosa::DivCeilShapeOp::fold(FoldAdaptor adaptor) { + return binaryFold>(this); +} + +OpFoldResult tosa::DivFloorShapeOp::fold(FoldAdaptor adaptor) { + return binaryFold>(this); +} + +OpFoldResult tosa::ModShapeOp::fold(FoldAdaptor adaptor) { + return binaryFold(this); +} + +OpFoldResult tosa::MaxShapeOp::fold(FoldAdaptor adaptor) { + return binaryFold(this); +} + +OpFoldResult tosa::MinShapeOp::fold(FoldAdaptor adaptor) { + return binaryFold(this); +} diff --git a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp index 5438cd73aef54..798fc360d8439 100644 --- a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp +++ b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp @@ -1481,6 +1481,19 @@ static void buildVariableOp(OpBuilder &builder, OperationState &result, //===----------------------------------------------------------------------===// // TOSA Operator Return Type Inference. //===----------------------------------------------------------------------===// +static FailureOr resolveBroadcastDim(const int64_t dim1, + const int64_t dim2) { + if (dim1 == 1) + return dim2; + if (dim2 == 1) + return dim1; + + if (ShapedType::isStatic(dim1) && ShapedType::isStatic(dim2) && dim1 != dim2) + return failure(); + + // Prefer static dimension over dynamic + return ShapedType::isDynamic(dim1) ? dim2 : dim1; +} static LogicalResult resolveBroadcastShape(const ValueShapeRange &operands, SmallVector &outShape) { @@ -1504,15 +1517,12 @@ static LogicalResult resolveBroadcastShape(const ValueShapeRange &operands, for (size_t i = 0, e = shape.getRank(); i < e; ++i) { auto dim1 = outShape[i + rankDiff]; auto dim2 = shape.getDimSize(i); - auto resolvedDim = dim1; - if (dim1 == 1) { - resolvedDim = dim2; - } else if (dim2 == 1) { - resolvedDim = dim1; - } else if (dim1 != dim2) { + const FailureOr maybeResolvedDim = + resolveBroadcastDim(dim1, dim2); + if (failed(maybeResolvedDim)) return failure(); - } + const int64_t resolvedDim = *maybeResolvedDim; outShape[i + rankDiff] = resolvedDim; } } @@ -4913,6 +4923,15 @@ LogicalResult tosa::ConcatShapeOp::verify() { cast(getResult().getType()); const int64_t outputRank = outShapeType.getRank(); const Operation::operand_range inputList = getInput(); + + if (inputList.size() == 0) + return emitOpError("requires at least one input shape"); + + if (llvm::any_of(inputList, [](Value v) { + return cast(v.getType()).getRank() == 0; + })) + return emitOpError("requires all inputs shapes have a rank greater than 0"); + const int64_t inputsRank = llvm::accumulate(inputList, 0, [](int64_t acc, const Value &input) { const tosa::shapeType inShapeType = diff --git a/mlir/lib/Dialect/UB/IR/CMakeLists.txt b/mlir/lib/Dialect/UB/IR/CMakeLists.txt index 3baac5045b8db..84125ea0b5718 100644 --- a/mlir/lib/Dialect/UB/IR/CMakeLists.txt +++ b/mlir/lib/Dialect/UB/IR/CMakeLists.txt @@ -5,13 +5,9 @@ add_mlir_dialect_library(MLIRUBDialect ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/UB DEPENDS - MLIRControlFlowInterfaces MLIRUBOpsIncGen MLIRUBOpsInterfacesIncGen LINK_LIBS PUBLIC - MLIRControlFlowInterfaces MLIRIR - MLIRExecutionProgressOpInterface - MLIRSideEffectInterfaces ) diff --git a/mlir/lib/Dialect/UB/IR/UBOps.cpp b/mlir/lib/Dialect/UB/IR/UBOps.cpp index 9c8ad2ddb2c6a..ee523f9522953 100644 --- a/mlir/lib/Dialect/UB/IR/UBOps.cpp +++ b/mlir/lib/Dialect/UB/IR/UBOps.cpp @@ -8,8 +8,6 @@ #include "mlir/Dialect/UB/IR/UBOps.h" #include "mlir/Conversion/ConvertToLLVM/ToLLVMInterface.h" -#include "mlir/Interfaces/ControlFlowInterfaces.h" -#include "mlir/Interfaces/ExecutionProgressOpInterface.h" #include "mlir/Transforms/InliningUtils.h" #include "mlir/IR/Builders.h" @@ -68,40 +66,3 @@ OpFoldResult PoisonOp::fold(FoldAdaptor /*adaptor*/) { return getValue(); } #define GET_OP_CLASSES #include "mlir/Dialect/UB/IR/UBOps.cpp.inc" - -namespace { -/// Canonicalization pattern for RegionBranchOpInterface ops that loop -/// infinitely. Such ops are replaced with poisoned values if they "must -/// progress". -struct EraseInfiniteRegionBranchLoop : public RewritePattern { - EraseInfiniteRegionBranchLoop(MLIRContext *context, StringRef name, - PatternBenefit benefit = 1) - : RewritePattern(name, benefit, context) {} - - LogicalResult matchAndRewrite(Operation *op, - PatternRewriter &rewriter) const override { - auto regionBranchOp = cast(op); - if (!mustProgress(op)) - return rewriter.notifyMatchFailure( - op, "only loops that must progress are removed"); - if (!wouldOpBeTriviallyDead(op)) - return rewriter.notifyMatchFailure(op, - "only trivially dead ops are removed"); - if (!isGuaranteedToLoopInfinitely(regionBranchOp)) - return rewriter.notifyMatchFailure( - op, "only loops that loop infinitely are removed"); - SmallVector replacements = - llvm::map_to_vector(op->getResultTypes(), [&](Type type) { - return PoisonOp::create(rewriter, op->getLoc(), type).getResult(); - }); - rewriter.replaceOp(op, replacements); - return success(); - } -}; -} // namespace - -void mlir::ub::populateEraseInfiniteRegionBranchLoopPattern( - RewritePatternSet &patterns, StringRef opName, PatternBenefit benefit) { - patterns.add(patterns.getContext(), opName, - benefit); -} diff --git a/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp b/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp index 7faa222a9e574..ab85b92920f32 100644 --- a/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp +++ b/mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp @@ -227,6 +227,12 @@ void transform::ApplySinkVectorMemPatternsOp::populatePatterns( vector::populateSinkVectorMemOpsPatterns(patterns); } +void transform::ApplyFlattenVectorTransferOpsPatternsOp::populatePatterns( + RewritePatternSet &patterns) { + vector::populateFlattenVectorTransferPatterns(patterns, + getTargetVectorBitwidth()); +} + //===----------------------------------------------------------------------===// // Transform op registration //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp b/mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp index efe8d14b3532a..14fbdd2243676 100644 --- a/mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp @@ -253,12 +253,12 @@ class ContractionOpToOuterProductOpLowering /// %bt = vector.transpose %b, [1, 0] /// %aRow0 = vector.extract %a[0] /// %btRow0 = vector.extract %bt[0] -/// %c00 = vector.reduce %atRow0, %bRow0 +/// %c00 = vector.reduction %atRow0, %bRow0 /// %out00 = vector.insert %c00, %out[0, 0] /// ... /// %aRowLast = vector.extract %at[M-1] /// %btRowLast = vector.extract %b[N-1] -/// %cLastLast = vector.reduce %atRowLast, %bRowLast +/// %cLastLast = vector.reduction %atRowLast, %bRowLast /// %outcLastLast = vector.insert %cLastLast, %out[M-1, N-1] /// ``` /// diff --git a/mlir/lib/Dialect/X86Vector/Transforms/VectorContractToPackedTypeDotProduct.cpp b/mlir/lib/Dialect/X86Vector/Transforms/VectorContractToPackedTypeDotProduct.cpp index a00a3e5bdd766..89aa53307b95d 100644 --- a/mlir/lib/Dialect/X86Vector/Transforms/VectorContractToPackedTypeDotProduct.cpp +++ b/mlir/lib/Dialect/X86Vector/Transforms/VectorContractToPackedTypeDotProduct.cpp @@ -113,10 +113,11 @@ struct VectorContractToPackedTypeDotProduct "RHS) dim and acc dim of size 4/8/16."); if (lhsTy.getElementType().isSignlessInteger(8) && nonUnitDim != 4 && - nonUnitDim != 8 && nonUnitDimAcc.front() == nonUnitDim) + nonUnitDim != 8 && nonUnitDim != 16 && + nonUnitDimAcc.front() == nonUnitDim) return rewriter.notifyMatchFailure( contractOp, "Int8 dot-product operation expects non-unit (LHR or " - "RHS) dim and acc dim of size 4/8."); + "RHS) dim and acc dim of size 4/8/16."); auto loc = contractOp.getLoc(); auto castAcc = vector::ShapeCastOp::create( @@ -159,10 +160,19 @@ struct VectorContractToPackedTypeDotProduct } if (lhsTy.getElementType().isSignlessInteger(8)) { - dp = x86vector::DotInt8Op::create( - rewriter, loc, - VectorType::get(nonUnitDimRhs.front(), rewriter.getIntegerType(32)), - castAcc, bitcastLhsPkType, castRhs); + if (nonUnitDimAcc.front() == 16) { + dp = x86vector::AVX10DotInt8Op::create( + rewriter, loc, + VectorType::get(nonUnitDimRhs.front(), + rewriter.getIntegerType(32)), + castAcc, bitcastLhsPkType, castRhs); + } else { + dp = x86vector::DotInt8Op::create( + rewriter, loc, + VectorType::get(nonUnitDimRhs.front(), + rewriter.getIntegerType(32)), + castAcc, bitcastLhsPkType, castRhs); + } } } else { auto castLhs = vector::ShapeCastOp::create( @@ -192,10 +202,19 @@ struct VectorContractToPackedTypeDotProduct } if (lhsTy.getElementType().isSignlessInteger(8)) { - dp = x86vector::DotInt8Op::create( - rewriter, loc, - VectorType::get(nonUnitDimLhs.front(), rewriter.getIntegerType(32)), - castAcc, castLhs, bitcastRhsPkType); + if (nonUnitDimAcc.front() == 16) { + dp = x86vector::AVX10DotInt8Op::create( + rewriter, loc, + VectorType::get(nonUnitDimLhs.front(), + rewriter.getIntegerType(32)), + castAcc, castLhs, bitcastRhsPkType); + } else { + dp = x86vector::DotInt8Op::create( + rewriter, loc, + VectorType::get(nonUnitDimLhs.front(), + rewriter.getIntegerType(32)), + castAcc, castLhs, bitcastRhsPkType); + } } } diff --git a/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp b/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp index 217065b12c598..d99557e68f0ec 100644 --- a/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp +++ b/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp @@ -398,7 +398,7 @@ bool LayoutAttr::isEqualTo(const xegpu::DistributeLayoutAttr &other) { // set the layout for unit dims: sg_data, inst_data and lane_data to 1 DistributeLayoutAttr -LayoutAttr::setUnitDimData(SetVector unitDims) const { +LayoutAttr::setUnitDimData(SmallVector unitDims) const { auto sgDataOpt = getSgData(); auto instDataOpt = getInstData(); auto laneDataOpt = getLaneData(); @@ -407,15 +407,14 @@ LayoutAttr::setUnitDimData(SetVector unitDims) const { SmallVector instData; SmallVector laneData; - if (sgDataOpt) { + if (sgDataOpt) sgData = llvm::to_vector(sgDataOpt.asArrayRef()); - } - if (instDataOpt) { + + if (instDataOpt) instData = llvm::to_vector(instDataOpt.asArrayRef()); - } - if (laneDataOpt) { + + if (laneDataOpt) laneData = llvm::to_vector(laneDataOpt.asArrayRef()); - } for (auto dim : unitDims) { if (dim < static_cast(sgData.size())) @@ -440,19 +439,17 @@ LayoutAttr::setUnitDimData(SetVector unitDims) const { // set the layout for the sepcified unit dims: sg_lane and lane_layout to 1 DistributeLayoutAttr -LayoutAttr::setUnitDimLayout(SetVector unitDims) const { +LayoutAttr::setUnitDimLayout(SmallVector unitDims) const { auto sgLayoutOpt = getSgLayout(); auto laneLayoutOpt = getLaneLayout(); SmallVector sgLayout; SmallVector laneLayout; - if (sgLayoutOpt) { + if (sgLayoutOpt) sgLayout = llvm::to_vector(sgLayoutOpt.asArrayRef()); - } - if (laneLayoutOpt) { + if (laneLayoutOpt) laneLayout = llvm::to_vector(laneLayoutOpt.asArrayRef()); - } for (auto dim : unitDims) { if (dim < static_cast(sgLayout.size())) @@ -471,6 +468,174 @@ LayoutAttr::setUnitDimLayout(SetVector unitDims) const { getLaneData(), getOrder()); } +// Derive a new layout with sg_data, inst_data and lane_data set to the +// specified values for the given dimension +DistributeLayoutAttr LayoutAttr::setDimData(int64_t dim, int64_t sgData, + int64_t instData, + int64_t laneData) { + + SmallVector sgDataVec = getEffectiveSgDataAsInt(); + SmallVector instDataVec = getEffectiveInstDataAsInt(); + SmallVector laneDataVec = getEffectiveLaneDataAsInt(); + + if (dim < static_cast(sgDataVec.size()) && sgData != -1) + sgDataVec[dim] = sgData; + if (dim < static_cast(instDataVec.size()) && instData != -1) + instDataVec[dim] = instData; + if (dim < static_cast(laneDataVec.size()) && laneData != -1) + laneDataVec[dim] = laneData; + + SmallVector sgDataVec32(sgDataVec.begin(), sgDataVec.end()); + SmallVector instDataVec32(instDataVec.begin(), instDataVec.end()); + SmallVector laneDataVec32(laneDataVec.begin(), laneDataVec.end()); + + return LayoutAttr::get( + getContext(), getSgLayout(), + sgDataVec.empty() ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), sgDataVec32), + instDataVec.empty() ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), instDataVec32), + getLaneLayout(), + laneDataVec.empty() ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), laneDataVec32), + getOrder()); +} + +// Derive a new layout by collapsing dimensions. +// `dimGroup` specifies a group of adjacent dimensions +// that are collapsed into a single dimension in the derived layout. +DistributeLayoutAttr LayoutAttr::collapseDims(SmallVector dimGroup) { + + SmallVector sgLayout = getEffectiveSgLayoutAsInt(); + SmallVector sgData = getEffectiveSgDataAsInt(); + SmallVector instData = getEffectiveInstDataAsInt(); + SmallVector laneLayout = getEffectiveLaneLayoutAsInt(); + SmallVector laneData = getEffectiveLaneDataAsInt(); + + DenseI32ArrayAttr orderAttr = getOrder(); + SmallVector orderVec; + if (orderAttr && !orderAttr.empty()) { + orderVec = llvm::to_vector( + llvm::map_range(orderAttr.asArrayRef(), + [](int32_t idx) { return static_cast(idx); })); + } + + SmallVector sortedDimGroup = dimGroup; + llvm::sort(sortedDimGroup); + int64_t dimBeforeCurrent = -1; + for (auto dimIdx : sortedDimGroup) { + // when order is present, adjacency dims are on order values like [3, 2, 1, + // 0] in decreasing order otherwise based on dim indices like [0, 1, 2, 3] + // in increasing order + if (dimBeforeCurrent >= 0) { + if (!orderVec.empty()) { + int64_t orderBefore = orderVec[dimBeforeCurrent]; + int64_t orderCurrent = orderVec[dimIdx]; + if (orderBefore != (orderCurrent - 1)) + llvm::report_fatal_error( + "dimensions being collapsed must be adjacent in order"); + } else { + if (dimIdx != (dimBeforeCurrent + 1)) + llvm::report_fatal_error( + "dimensions being collapsed must be adjacent"); + } + } + dimBeforeCurrent = dimIdx; + } + + int firstDim = sortedDimGroup.front(); + + // collapse the dimensions in dimGroup into one dimension by multiplying their + // sizes together + + if (!sgLayout.empty()) { + int64_t collapsedSglayout = 1, collapsedSgData = 1; + for (auto dimIdx : dimGroup) { + collapsedSglayout *= sgLayout[dimIdx]; + collapsedSgData *= sgData[dimIdx]; + } + for (auto dimIdx : llvm::reverse(sortedDimGroup)) { + sgLayout.erase(sgLayout.begin() + dimIdx, sgLayout.begin() + dimIdx + 1); + sgData.erase(sgData.begin() + dimIdx, sgData.begin() + dimIdx + 1); + } + sgLayout.insert(sgLayout.begin() + firstDim, collapsedSglayout); + sgData.insert(sgData.begin() + firstDim, collapsedSgData); + } + + if (!instData.empty()) { + int64_t collapsedInstData = 1; + for (auto dimIdx : dimGroup) + collapsedInstData *= instData[dimIdx]; + for (auto dimIdx : llvm::reverse(sortedDimGroup)) + instData.erase(instData.begin() + dimIdx, instData.begin() + dimIdx + 1); + instData.insert(instData.begin() + firstDim, collapsedInstData); + } + + if (!laneLayout.empty()) { + int64_t collapsedLaneLayout = 1, collapsedLaneData = 1; + for (auto dimIdx : dimGroup) { + collapsedLaneLayout *= laneLayout[dimIdx]; + collapsedLaneData *= laneData[dimIdx]; + } + for (auto dimIdx : llvm::reverse(sortedDimGroup)) { + laneLayout.erase(laneLayout.begin() + dimIdx, + laneLayout.begin() + dimIdx + 1); + laneData.erase(laneData.begin() + dimIdx, laneData.begin() + dimIdx + 1); + } + laneLayout.insert(laneLayout.begin() + firstDim, collapsedLaneLayout); + laneData.insert(laneData.begin() + firstDim, collapsedLaneData); + } + + // go through the values inside collapsedOrder, and re-map the order values + // to be in range of [0, N-1] where N is the number of dimensions in + // collapsed shape for exmaple, collapse dim group {2, 3} of order[1, 2, 3, + // 4] to new order[1, 3, 4]. the loop below remaps it to [1, 2, 3]. + SmallVector collapsedOrder; + if (!orderVec.empty()) { + + for (auto dimIdx : llvm::reverse(sortedDimGroup)) { + if (dimIdx != firstDim) + orderVec.erase(orderVec.begin() + dimIdx, + orderVec.begin() + dimIdx + 1); + } + + // say we have orderVec = {5, 3, 2, 1, 0} + // Create indices [0, 1, 2, 3, 4] + SmallVector indices = + llvm::to_vector(llvm::seq(0, orderVec.size())); + + // Sort indices based on corresponding values + llvm::sort(indices, + [&](size_t a, size_t b) { return orderVec[a] < orderVec[b]; }); + collapsedOrder = llvm::to_vector(llvm::map_range( + indices, [&](size_t i) { return static_cast(i); })); + } + + // Create collapsed layout + SmallVector sgLayout32(sgLayout.begin(), sgLayout.end()); + SmallVector sgData32(sgData.begin(), sgData.end()); + SmallVector instData32(instData.begin(), instData.end()); + SmallVector laneLayout32(laneLayout.begin(), laneLayout.end()); + SmallVector laneData32(laneData.begin(), laneData.end()); + + auto collapsedLayout = xegpu::LayoutAttr::get( + getContext(), + sgLayout32.empty() ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), sgLayout32), + sgData32.empty() ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), sgData32), + instData32.empty() ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), instData32), + laneLayout32.empty() ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), laneLayout32), + laneData32.empty() ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), laneData32), + collapsedOrder.empty() + ? DenseI32ArrayAttr() + : DenseI32ArrayAttr::get(getContext(), collapsedOrder)); + return collapsedLayout; +} + //===----------------------------------------------------------------------===// // XeGPU_SliceAttr //===----------------------------------------------------------------------===// @@ -624,12 +789,12 @@ bool SliceAttr::isEqualTo(const xegpu::DistributeLayoutAttr &other) { // shape is of rank 2, if we want to set unit dim [0] in sliced space, it maps // to dim [0] in parent space; if we want to set unit dim [1] in sliced space, // it maps to dim [2] in parent space. -static SetVector -mapSlicedDimsToParentSpace(const SetVector &dimsToMap, +static SmallVector +mapSlicedDimsToParentSpace(const SmallVector &dimsToMap, ArrayRef sliceDims) { - // Rather than recovering the exact parent rank, we compute a safe upper bound - // so that dimsToMap can be adjusted safely. This upper bound is defined as - // max(dimsToMap, sliceDims) + 1 + sliceDims.size(). + // Rather than recovering the exact parent rank, we compute a safe upper + // bound so that dimsToMap can be adjusted safely. This upper bound is + // defined as max(dimsToMap, sliceDims) + 1 + sliceDims.size(). int64_t maxDim = -1; maxDim = std::max(maxDim, *std::max_element(sliceDims.begin(), sliceDims.end())); @@ -648,10 +813,10 @@ mapSlicedDimsToParentSpace(const SetVector &dimsToMap, } // Map unit dims from sliced space to parent space - SetVector adjustUnitDims; + SmallVector adjustUnitDims; for (auto dim : dimsToMap) { int64_t mappedDim = remainingDims[dim]; - adjustUnitDims.insert(mappedDim); + adjustUnitDims.push_back(mappedDim); } return adjustUnitDims; @@ -659,12 +824,12 @@ mapSlicedDimsToParentSpace(const SetVector &dimsToMap, // set the layout for unit dims: sg_data, inst_data and lane_data to 1 DistributeLayoutAttr -SliceAttr::setUnitDimData(SetVector unitDims) const { +SliceAttr::setUnitDimData(SmallVector unitDims) const { DistributeLayoutAttr parentLayout = getParent(); ArrayRef sliceDims = getDims().asArrayRef(); - SetVector adjustUnitDims = + SmallVector adjustUnitDims = mapSlicedDimsToParentSpace(unitDims, sliceDims); return SliceAttr::get(getContext(), @@ -673,18 +838,51 @@ SliceAttr::setUnitDimData(SetVector unitDims) const { // set the layout for the sepcified unit dims: sg_lane and lane_layout to 1 DistributeLayoutAttr -SliceAttr::setUnitDimLayout(SetVector unitDims) const { +SliceAttr::setUnitDimLayout(SmallVector unitDims) const { DistributeLayoutAttr parentLayout = getParent(); ArrayRef sliceDims = getDims().asArrayRef(); - SetVector adjustUnitDims = + SmallVector adjustUnitDims = mapSlicedDimsToParentSpace(unitDims, sliceDims); return SliceAttr::get( getContext(), parentLayout.setUnitDimLayout(adjustUnitDims), getDims()); } +// Derive a new layout with sg_data, inst_data and lane_data set to the +// specified values for the given dimension +DistributeLayoutAttr SliceAttr::setDimData(int64_t dim, int64_t sgData, + int64_t instData, int64_t laneData) { + ArrayRef sliceDims = getDims().asArrayRef(); + auto parent = getParent(); + + SmallVector dimSet; + dimSet.push_back(dim); + SmallVector adjustDims = + mapSlicedDimsToParentSpace(dimSet, sliceDims); + return SliceAttr::get( + getContext(), + parent.setDimData(adjustDims[0], sgData, instData, laneData), getDims()); +} + +// Derive a new layout by collapsing dimensions. +// `dimGroup` specifies a group of adjacent dimensions +// that are collapsed into a single dimension in the derived layout. +DistributeLayoutAttr SliceAttr::collapseDims(SmallVector dimGroup) { + + // Map the sliced dims from parent space to collapsed space + SmallVector sliceDims = llvm::to_vector(getDims().asArrayRef()); + + SmallVector dimsInParentSpace = + mapSlicedDimsToParentSpace(dimGroup, sliceDims); + + auto collapsedParent = getParent().collapseDims(dimsInParentSpace); + + return SliceAttr::get(getContext(), collapsedParent, + DenseI64ArrayAttr::get(getContext(), sliceDims)); +} + //===----------------------------------------------------------------------===// // XeGPU_RangeAttr //===----------------------------------------------------------------------===// @@ -820,7 +1018,8 @@ TensorDescType::verify(llvm::function_ref emitError, return emitError() << "unsupported element type " << elementType << ": expected integer or float"; - // for gather and scatter ops, Low-precision types are packed in 32-bit units. + // for gather and scatter ops, Low-precision types are packed in 32-bit + // units. unsigned bitWidth = elementType.getIntOrFloatBitWidth(); int chunkAlignmentFactor = bitWidth < xegpu::uArch::generalPackedFormatBitSize diff --git a/mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt b/mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt index 47a3f371164fd..cf99c3a68e7f8 100644 --- a/mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt +++ b/mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt @@ -8,6 +8,7 @@ add_mlir_dialect_library(MLIRXeGPUTransforms XeGPUPropagateLayout.cpp XeGPUVectorLinearize.cpp XeGPUPeepHoleOptimizer.cpp + XeGPULayoutImpl.cpp ADDITIONAL_HEADER_DIRS ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/XeGPU diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp index c00b7d42d48a6..6faa25cf49df9 100644 --- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp +++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp @@ -12,6 +12,7 @@ #include "mlir/Dialect/Vector/Transforms/VectorTransforms.h" #include "mlir/Dialect/XeGPU/IR/XeGPU.h" #include "mlir/Dialect/XeGPU/Transforms/Transforms.h" +#include "mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h" #include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h" #include "mlir/Interfaces/LoopLikeInterface.h" #include "mlir/Pass/PassManager.h" @@ -286,13 +287,10 @@ void XeGPUBlockingPass::runOnOperation() { MLIRContext *ctx = &getContext(); Operation *op = getOperation(); - // TODO-LayoutRefactor: unify the local propagation for layout preprocessing - // replace the function with recoverTemporaryLayouts - // if (!xegpu::recoverTemporaryLayouts(op)) { - // signalPassFailure(); - // return; - // } - xegpu::recoverTemporaryLayoutsDeprecated(op); + if (!xegpu::recoverTemporaryLayouts(op)) { + signalPassFailure(); + return; + } auto getTileShapeAndCount = [](llvm::ArrayRef shape, xegpu::LayoutAttr layout) { diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp new file mode 100644 index 0000000000000..a4e47fca96d34 --- /dev/null +++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPULayoutImpl.cpp @@ -0,0 +1,855 @@ +//===---- XeGPULayoutImpl.cpp - MLIR Utilities for XeGPUOps +//------------------===// +// +// Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements layout utility functions for XeGPU dialect +// transformation. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" +#include "mlir/Dialect/GPU/IR/GPUDialect.h" +#include "mlir/Dialect/LLVMIR/XeVMDialect.h" +#include "mlir/Dialect/SCF/Transforms/Patterns.h" +#include "mlir/Dialect/Utils/IndexingUtils.h" +#include "mlir/Dialect/XeGPU/IR/XeGPU.h" +#include "mlir/IR/Builders.h" +#include "mlir/IR/Operation.h" +#include "mlir/IR/ValueRange.h" +#include "mlir/Interfaces/LoopLikeInterface.h" +#include "mlir/Transforms/DialectConversion.h" +#include "llvm/Support/FormatVariadic.h" +#include +#include + +using namespace mlir; + +void xegpu::recoverTemporaryLayoutsDeprecated(Operation *op) { + op->walk([&](Operation *nestOp) { + for (OpOperand &opr : nestOp->getOpOperands()) { + auto layout = getDistributeLayoutAttr(opr.get()); + setDistributeLayoutAttr(opr, layout); + } + + for (OpResult result : nestOp->getOpResults()) { + auto layout = getDistributeLayoutAttr(result); + setDistributeLayoutAttr(result, layout); + } + }); +} + +SmallVector +xegpu::dropSgLayoutAndDataOnAttrs(ArrayRef attrs) { + SmallVector out; + out.reserve(attrs.size()); + + for (auto attr : attrs) { + if (auto dist = dyn_cast(attr.getValue())) { + auto newLayout = dist.dropSgLayoutAndData(); + if (newLayout) + out.emplace_back(attr.getName(), newLayout); + } else { + out.push_back(attr); + } + } + + return out; +} + +SmallVector +xegpu::dropInstDataOnAttrs(ArrayRef attrs) { + SmallVector out; + out.reserve(attrs.size()); + + for (auto attr : attrs) { + if (auto dist = dyn_cast(attr.getValue())) { + auto newLayout = dist.dropInstData(); + if (newLayout) + out.emplace_back(attr.getName(), newLayout); + } else { + out.push_back(attr); + } + } + + return out; +} + +// Attach layout attributes to all vector-type operands of operations within +// the given operation's region. Reports an error if any vector operand lacks +// a layout attribute. +bool xegpu::recoverTemporaryLayouts(Operation *rootOp) { + auto result = rootOp->walk([&](Operation *op) { + for (OpOperand &operand : op->getOpOperands()) { + // Layouts are needed for vector type only. + if (!isa(operand.get().getType())) + continue; + // Skip block arguments since they don't have defining ops to attach + // layout attributes to + if (isa(operand.get())) + continue; + auto layout = xegpu::getDistributeLayoutAttr(operand.get()); + if (!layout) { + op->emitWarning("Could not find layout attribute for operand ") + << operand.getOperandNumber() << " of operation " << op->getName(); + continue; + } + xegpu::setDistributeLayoutAttr(operand, layout); + } + return WalkResult::advance(); + }); + return !result.wasInterrupted(); +} + +template +void xegpu::removeLayoutAttr(const T &operandOrResult) { + Operation *owner = operandOrResult.getOwner(); + std::string name = xegpu::getTemporaryLayoutName(operandOrResult); + if (owner->hasAttrOfType(name)) + owner->removeAttr(name); +} + +// Explicit instantiation for OpResult +template void +xegpu::removeLayoutAttr(const mlir::OpResult &result); + +// Explicit instantiation for OpOperand +template void +xegpu::removeLayoutAttr(const mlir::OpOperand &operand); + +void xegpu::removeLayoutAttrs(Operation *op) { + op->walk([&](Operation *nestOp) { + // Remove all attributes of DistributeLayoutAttr type + SmallVector attrsToRemove; + for (auto namedAttr : nestOp->getAttrs()) { + if (isa(namedAttr.getValue())) + attrsToRemove.push_back(namedAttr.getName()); + } + for (auto attrName : attrsToRemove) + nestOp->removeAttr(attrName); + }); +} + +/// Infers the source layout attribute for a broadcast operation given the +/// result layout attribute, result shape, source shape. +xegpu::DistributeLayoutAttr +xegpu::inferBroadcastSourceLayout(xegpu::DistributeLayoutAttr resLayout, + ArrayRef resShape, + ArrayRef srcShape) { + + SmallVector bcastDims; + auto returnLayout = resLayout; + + // Handling broadcast from low-rank to high-rank (e.g., 1D to 2D) case. + int dimDiff = resShape.size() - srcShape.size(); + + if (dimDiff > 0) { + // Adding the missing leading dims + for (int i = 0; i < dimDiff; i++) + bcastDims.push_back(i); + + // Create a slice layout for the source + returnLayout = xegpu::SliceAttr::get( + resLayout.getContext(), resLayout, + DenseI64ArrayAttr::get(resLayout.getContext(), bcastDims)); + } + return returnLayout; +} + +/// Infers the source layout attribute for a reduction operation given the +/// result layout attribute and reduced dims. +xegpu::DistributeLayoutAttr +xegpu::inferMultiReductionSourceLayout(xegpu::DistributeLayoutAttr resLayout, + SmallVector reduceDims) { + + assert(isa(resLayout) && + "reduction result layout must be slice layout"); + + xegpu::SliceAttr sliceLayout = dyn_cast(resLayout); + + assert((reduceDims == sliceLayout.getDims().asArrayRef()) && + "reduction dims must match with slice dims"); + + return sliceLayout.getParent(); +} + +/// Infers the source layout attribute for a bitcast operation given the +/// result layout attribute, result element type bitwidth, and source element +/// type bitwidth. +xegpu::DistributeLayoutAttr +xegpu::inferBitCastSourceLayout(xegpu::DistributeLayoutAttr resLayout, + int resElemTyBitWidth, int srcElemTyBitWidth) { + + SmallVector sgData = resLayout.getEffectiveSgDataAsInt(); + SmallVector instData = resLayout.getEffectiveInstDataAsInt(); + SmallVector laneData = resLayout.getEffectiveLaneDataAsInt(); + size_t sgDataSize = sgData.size(); + size_t instDataSize = instData.size(); + size_t laneDataSize = laneData.size(); + int64_t sgDataValue = -1; + int64_t instDataValue = -1; + int64_t laneDataValue = -1; + int64_t dim = resLayout.getRank() - 1; + + if (srcElemTyBitWidth <= resElemTyBitWidth) { + int bitWidthRatio = resElemTyBitWidth / srcElemTyBitWidth; + if (sgDataSize) + sgDataValue = sgData.back() * bitWidthRatio; + if (instDataSize) + instDataValue = instData.back() * bitWidthRatio; + if (laneDataSize) + laneDataValue = laneData.back() * bitWidthRatio; + } else { + int bitWidthRatio = srcElemTyBitWidth / resElemTyBitWidth; + if (sgDataSize) { + assert((sgData.back() % bitWidthRatio) == 0 && + "sgData not divisible by bitWidthRatio"); + sgDataValue = sgData.back() / bitWidthRatio; + } + if (instDataSize) { + assert((instData.back() % bitWidthRatio) == 0 && + "instData not divisible by bitWidthRatio"); + instDataValue = instData.back() / bitWidthRatio; + } + if (laneDataSize) { + assert((laneData.back() % bitWidthRatio) == 0 && + "laneData not divisible by bitWidthRatio"); + laneDataValue = laneData.back() / bitWidthRatio; + } + } + + xegpu::DistributeLayoutAttr finalSrcLayout; + finalSrcLayout = + resLayout.setDimData(dim, sgDataValue, instDataValue, laneDataValue); + + return finalSrcLayout; +} + +/// Infers the source layout attribute for an insert strided slice operation +/// given the result layout attribute, result shape, and source shape. Removes +/// leading dimensions from the result layout to match the source shape size. +xegpu::DistributeLayoutAttr xegpu::inferInsertStridedSliceSourceLayout( + xegpu::DistributeLayoutAttr resLayout, ArrayRef resShape, + ArrayRef srcShape) { + + int srcShapeSize = srcShape.size(); + int resShapeSize = resShape.size(); + int dimDiff = resShapeSize - srcShapeSize; + + assert(isa(resLayout) && + "insertStridedSlice result layout must be plain layout"); + auto context = resLayout.getContext(); + auto resInstData = resLayout.getEffectiveInstDataAsInt(); + auto resLaneLayout = resLayout.getEffectiveLaneLayoutAsInt(); + auto resLaneData = resLayout.getEffectiveLaneDataAsInt(); + + if (resInstData.size() != 0) { + SmallVector inferredInstData(srcShapeSize); + for (int i = 0; i < srcShapeSize; i++) + inferredInstData[i] = resInstData[i + dimDiff]; + return xegpu::LayoutAttr::get(context, inferredInstData); + } + + if (resLaneLayout.size() != 0) { + SmallVector inferredLaneLayout(srcShapeSize); + SmallVector inferredLaneData(srcShapeSize); + for (int i = 0; i < srcShapeSize; i++) { + inferredLaneLayout[i] = resLaneLayout[i + dimDiff]; + inferredLaneData[i] = resLaneData[i + dimDiff]; + } + return xegpu::LayoutAttr::get(context, inferredLaneLayout, + inferredLaneData); + } + return nullptr; +} + +/// Infers the source layout attribute for a shape cast operation given the +/// result layout attribute, result shape, and source shape. +xegpu::DistributeLayoutAttr +xegpu::inferShapeCastSourceLayout(xegpu::DistributeLayoutAttr resLayout, + ArrayRef resShape, + ArrayRef srcShape) { + + // There are three use cases: + // 1. expand dims of low-rank dimensions (e.g., 1D to 2D): to set up the + // tensor before broadcast + // 2. split dim of a high-rank dimension (e.g., 1D to 2D): to setup tensor + // for multi-stage reduction + // 3. combines all dims to a single dim and put in the innermost dim in 2d as + // [1, combinedData] or [combinedData]. Say, [2, 4, 8] -> [1, 64] or [64] + // Use cases are only supported after workgroup distribution, + // like cross-sg reduction saves multidimension data to + // 1D slm buffer, shapecast inserted by cse/canonicalization passes. + + // Use case 1: Shapes only differ by expanding unit dimensions, for broadcast + SmallVector expandedUnitDims; + + if (xegpu::matchUnitDimExpansion(srcShape, resShape, expandedUnitDims)) { + // create a slice layout for the source by removing the expanded unit dims + auto sliceDimsAttr = DenseI64ArrayAttr::get( + resLayout.getContext(), ArrayRef(expandedUnitDims)); + auto srcLayout = + xegpu::SliceAttr::get(resLayout.getContext(), resLayout, sliceDimsAttr); + return srcLayout; + } + + // Use case 2: Dim split from source to result, for multi-stage reduction + SmallVector> splitDimGroups; + if (xegpu::matchSplitDimExpansion(srcShape, resShape, splitDimGroups)) { + auto srcLayout = resLayout; + for (const auto &dimGroup : splitDimGroups) + srcLayout = srcLayout.collapseDims(dimGroup); + + return srcLayout; + } + + // Use case 3: Collaspse to innermost dim, for cross-sg reduction to SLM + auto matchCollapseToInnermostDim = [&](ArrayRef src, + ArrayRef dst) -> bool { + // only one non-unit dim in dst which is the innermost dim + if ((dst.size() != 2) && (dst.size() != 1)) + return false; + int64_t srcSize = std::accumulate(src.begin(), src.end(), 1LL, + std::multiplies()); + if (dst.size() == 1) + return (dst[0] == srcSize); + return (dst[0] == 1) && (dst[1] == srcSize); + }; + + if (matchCollapseToInnermostDim(srcShape, resShape)) { + int srcShapeSize = srcShape.size(); + int resShapeSize = resShape.size(); + auto context = resLayout.getContext(); + auto resInstData = resLayout.getEffectiveInstDataAsInt(); + auto resLaneLayout = resLayout.getEffectiveLaneLayoutAsInt(); + auto resLaneData = resLayout.getEffectiveLaneDataAsInt(); + + // Extract layout info from result's innermost dimension and apply to + // source's innermost dimension while setting all other dimensions to 1. + // The inferred layout is restricted by srcShape to ensure it fits within + // the source dimensions. + // Examples 1: + // srcShape=[8, 16, 32], resShape=[1, 4096] + // resInstData=[1, 16] + // -> inferredInstData=[1, 1, min(16, 32)]=[1, 1, 16] + // Examples 2: + // srcShape=[4, 8, 64], resShape=[2048] + // resLaneLayout=[16], resLaneData=[2] + // -> inferredLaneLayout=[1, 1, 16] + // -> inferredLaneData=[1, 1, min(2, 64/16)]=[1, 1, 2] + + if (resInstData.size() != 0) { + // assert resInstData must be 1 for all but the innermost dim + for (int i = 0; i < resShapeSize - 1; i++) { + assert(resInstData[i] == 1 && + "only innermost dim can have non-unit instData"); + } + SmallVector inferredInstData(srcShapeSize, 1); + inferredInstData[srcShapeSize - 1] = + std::min(resInstData[resShapeSize - 1], srcShape[srcShapeSize - 1]); + return xegpu::LayoutAttr::get(context, inferredInstData); + } + + if (resLaneLayout.size() != 0) { + for (int i = 0; i < resShapeSize - 1; i++) { + assert(resLaneData[i] == 1 && + "only innermost dim can have non-unit instData"); + } + assert(srcShape.back() % resLaneLayout.back() == 0 && + "source innermost dim must be >= result lane layout"); + SmallVector inferredLaneLayout(srcShapeSize, 1); + SmallVector inferredLaneData(srcShapeSize, 1); + inferredLaneLayout.back() = resLaneLayout.back(); + inferredLaneData.back() = std::min( + resLaneData.back(), srcShape.back() / inferredLaneLayout.back()); + return xegpu::LayoutAttr::get(context, inferredLaneLayout, + inferredLaneData); + } + } + llvm_unreachable("running into unsupported shape cast scenarios"); + return nullptr; +} + +/// Sets up layout for reduction operations by creating a SliceAttr for the +/// result. +/// +/// Algorithm Overview: +/// This function attempts to construct a source layout that, when sliced along +/// reduction dimensions, produces a result layout compatible with the +/// consumer layout. +/// +/// For subgroup layouts, it first tries to align the source layout's subgroup +/// layout and data with the consumer's layout on non-reduction dimensions. +/// Then, it distributes remaining subgroups across reduction dimensions. This +/// avoids subgroup data redistribution overhead between the reduced result and +/// its consumer. +/// +/// InstData requries {1, ..., min(maxReduceVectorSize, srcShape),subgroupSize} +/// Lane Layout requires {1, ..., 1, subgroupSize} +/// Lane data requires {1, ..., min(maxReduceVectorSize, srcShape), 1} +/// +/// Examples: +/// 1. Subgroup layout - Row reduction on 2D tensor: +/// srcShape=[32, 64], reductionDims=[1], resShape=[32], subgroupSize=16, +/// workgroupSize=32 +/// Consumer Layout: +/// #xegpu.slice<#xegpu.layout, dims = +/// [1]>} Result: srcLayout with sgLayout=[4, 8], sgData=[8, 8] (matches +/// consumer on non-reduction dim, minimizing data redistribution on +/// reduction dim) +/// 2. Subgroup layout - Same example above but consumer has different layout: +/// sgLayout=[32], sgData=[1] +/// Result: srcLayout with sgLayout=[32,1], sgData=[1, 64] +/// (distributes all subgroups on non reduction dim) +/// +/// 2. InstData layout - Column reduction: +/// srcShape=[32, 64], reductionDims=[0], subgroupSize=16 +/// Result: instData=[1, 16] (maxReduceVectorSize=1, subgroupSize on +/// innermost) +/// +/// 3. Lane layout - Multi-dimensional reduction: +/// srcShape=[16, 32, 64], reductionDims=[1], subgroupSize=16 +/// Result: laneLayout=[1, 1, 16], laneData=[1, 1, 1] +/// (subgroupSize on innermost dim, max vector size on reduction dim) + +xegpu::SliceAttr xegpu::setupMultiReductionResultLayout( + xegpu::LayoutKind layoutKind, VectorType srcVecTy, + DistributeLayoutAttr consumerLayout, SmallVector reductionDims, + const xegpu::uArch::uArch *uArch) { + + auto srcShape = srcVecTy.getShape(); + int srcRank = srcShape.size(); + auto context = consumerLayout.getContext(); + + // Reduction layout requires at least 2D tensors + if (srcRank < 2) + return nullptr; + + // Helper lambda to convert int64 vectors to int32 DenseArrayAttr + auto toInt32Attr = [&](ArrayRef vec) { + SmallVector vec32(vec.begin(), vec.end()); + return DenseI32ArrayAttr::get(context, vec32); + }; + + // Extract original plain layout for workgroup/subgroup size recovery + xegpu::SliceAttr consumerSliceLayout = + dyn_cast(consumerLayout); + DistributeLayoutAttr plainLayout = + consumerSliceLayout ? consumerSliceLayout.flatten().getParent() + : consumerLayout; + + const int subgroupSize = uArch->getSubgroupSize(); + int64_t maxReduceVectorSize = 1; // could extend to spirv vector Size + + xegpu::DistributeLayoutAttr srcLayout; + + if (layoutKind == xegpu::LayoutKind::Subgroup) { + auto sgLayoutVec = plainLayout.getEffectiveSgLayoutAsInt(); + const int workgroupSize = std::accumulate( + sgLayoutVec.begin(), sgLayoutVec.end(), 1, std::multiplies()); + SmallVector sgLayout(srcRank), sgData(srcRank); + SmallVector consumerSgLayout = + consumerLayout.getEffectiveSgLayoutAsInt(); + int remainingSgCount = workgroupSize; + int consumerIdx = consumerSgLayout.size() - 1; + + // First pass: Match consumer's layout on non-reduction dimensions + for (int i = srcRank - 1; i >= 0; i--) { + if (!llvm::is_contained(reductionDims, i) && consumerIdx >= 0) { + sgLayout[i] = consumerSgLayout[consumerIdx]; + assert((srcShape[i] % sgLayout[i] == 0) && + "source shape not divisible by consumer sg_layout"); + sgData[i] = srcShape[i] / sgLayout[i]; + remainingSgCount /= sgLayout[i]; + consumerIdx--; + } + } + + // Second pass: Distribute remaining subgroups across reduction dimensions + for (int i = srcRank - 1; i >= 0; i--) { + if (llvm::is_contained(reductionDims, i)) { + sgLayout[i] = + std::min(srcShape[i], static_cast(remainingSgCount)); + assert((srcShape[i] % sgLayout[i] == 0) && + "source shape not divisible by sg_layout"); + sgData[i] = srcShape[i] / sgLayout[i]; + remainingSgCount /= sgLayout[i]; + } + } + + assert(remainingSgCount == 1 && "not all subgroups distributed"); + srcLayout = xegpu::LayoutAttr::get( + context, toInt32Attr(sgLayout), toInt32Attr(sgData), + /*inst_data =*/nullptr, /*lane_layout =*/nullptr, + /*lane_data =*/nullptr, /*order =*/nullptr); + + } else if (layoutKind == xegpu::LayoutKind::InstData) { + + SmallVector instData(srcRank, 1); + instData[srcRank - 2] = + std::min(maxReduceVectorSize, srcShape[srcRank - 2]); + instData[srcRank - 1] = subgroupSize; + srcLayout = xegpu::LayoutAttr::get(context, toInt32Attr(instData)); + + } else if (layoutKind == xegpu::LayoutKind::Lane) { + + SmallVector laneLayout(srcRank, 1), laneData(srcRank, 1); + laneLayout[srcRank - 1] = subgroupSize; + laneData[srcRank - 2] = + std::min(maxReduceVectorSize, srcShape[srcRank - 2]); + srcLayout = xegpu::LayoutAttr::get(context, toInt32Attr(laneLayout), + toInt32Attr(laneData), + consumerLayout.getOrder()); + } + + return xegpu::SliceAttr::get(context, srcLayout, + DenseI64ArrayAttr::get(context, reductionDims)); +} + +/// Sets up the result layout for a bitcast operation. +/// When casting to a smaller bitwidth, adjusts the layout dimensions (sgData, +/// instData, or laneData) by multiplying by the bitwidth ratio to ensure the +/// result layout can be correctly divided back to the source layout during +/// inference. +/// +/// Examples: +/// 1. Casting f32 -> f16 (32-bit to 16-bit, bitWidthRatio = 2): +/// Consumer layout: instData=[1, 16], subgroupSize=16 +/// Source shape: [8, 32] +/// Result layout: instData=[1, 32] (16 * 2) +/// The innermost dimension is multiplied by 2 to maintain consistency. +/// +/// 2. Casting f32 -> i8 (32-bit to 8-bit, bitWidthRatio = 4): +/// Consumer instData=[1, 16], subgroupSize=16 +/// Source shape: [4, 128] +/// adjust the instData from [1, 16] to [1, 16 * 4 = 64] +/// +/// 3. Casting i8 -> i32 (8-bit to 32-bit, bitWidthRatio = 1/4): +/// Consumer layout: laneLayout=[1, 16], laneData=[1, 4] +/// No adjustment needed - returns consumer layout directly. +/// +xegpu::DistributeLayoutAttr xegpu::setupBitCastResultLayout( + xegpu::LayoutKind layoutKind, VectorType srcVecTy, VectorType resVecTy, + DistributeLayoutAttr consumerLayout, const xegpu::uArch::uArch *uArch) { + + int srcElemTyBitWidth = srcVecTy.getElementType().getIntOrFloatBitWidth(); + int resElemTyBitWidth = resVecTy.getElementType().getIntOrFloatBitWidth(); + + ArrayRef srcShape = srcVecTy.getShape(); + SmallVector sgData = consumerLayout.getEffectiveSgDataAsInt(); + SmallVector instData = consumerLayout.getEffectiveInstDataAsInt(); + SmallVector laneData = consumerLayout.getEffectiveLaneDataAsInt(); + size_t dim = srcShape.size() - 1; + int64_t sgDataValue = -1; + int64_t instDataValue = -1; + int64_t laneDataValue = -1; + + const int subgroupSize = uArch->getSubgroupSize(); + + if (srcElemTyBitWidth > resElemTyBitWidth) { + // When casting to a smaller bitwidth, multiply the result layout + // accordingly to ensure it can be divided by the ratio back to the + // source layout. + int bitWidthRatio = srcElemTyBitWidth / resElemTyBitWidth; + int innermostDimLaneLayout = subgroupSize; + if (layoutKind == xegpu::LayoutKind::Subgroup) { + assert(sgData.size() == srcShape.size() && + "sgData must be available for all dimensions"); + sgDataValue = sgData[dim]; + } else if (layoutKind == xegpu::LayoutKind::InstData) { + assert(instData.size() == srcShape.size() && + "instData must be available for all dimensions"); + instDataValue = instData[dim]; + // Adjust instDataValue so it still fits within an instruction after + // dividing by bitWidthRatio + while ((instDataValue <= srcShape[dim]) && + (instDataValue % (innermostDimLaneLayout * bitWidthRatio) != 0)) + instDataValue *= 2; + assert((srcShape[dim] % instDataValue) == 0 && + "srcShape, instData, and lanelayout for innermost must be 2^n !"); + } else if (layoutKind == xegpu::LayoutKind::Lane) { + assert(laneData.size() == srcShape.size() && + "laneData must be available for all dimensions"); + laneDataValue = laneData[dim]; + while ((laneDataValue <= srcShape[dim]) && + (laneDataValue % bitWidthRatio != 0)) + laneDataValue *= 2; + } + // Now set only instData and laneData, preserving sgData + xegpu::DistributeLayoutAttr resLayout; + resLayout = consumerLayout.setDimData(dim, sgDataValue, instDataValue, + laneDataValue); + return resLayout; + } + return consumerLayout; +} + +/// Sets up the result layout for an insert strided slice operation. +/// Creates a result layout based on the specified layout kind (InstData or +/// Lane). +/// Subgroup layout is currently not supported for this operation. +/// InstData layout is first set to be {1, .., subgroupSize}. +/// Lane layout is first set to be {1, ..., subgroupSize} with lane data {1, +/// ..., 1}. The instData and laneData is then adjusted to contain packed data, +/// by checking if the consumerLayout's innermost dimension. +/// +/// Examples: +/// 1. InstData layout without packing: +/// resShape=[8, 32], subgroupSize=16, bitwidth=32 +/// packingFactor=1, packedDataSize=16 +/// consumerLayout: instData=[1, 16] +/// Result: instData=[1, 16] +/// +/// 2. InstData layout with packing: +/// resShape=[8, 64], subgroupSize=16, bitwidth=8, packingFactor=4 +/// consumerLayout: instData=[1, 64] +/// Result: instData=[1, 64] (adjusted for packed data) +/// +/// 3. Lane layout without packing: +/// resShape=[4, 64], subgroupSize=16, bitwidth=32 +/// consumerLayout: laneLayout=[1, 16], laneData=[1, 1] +/// Result: laneLayout=[1, 16], laneData=[1, 1] +/// +/// 4. Lane layout with packing: +/// resShape=[4, 64], subgroupSize=16, bitwidth=16, packingFactor=2 +/// consumerLayout: laneLayout=[1, 16], laneData=[1, 2] +/// Result: laneLayout=[1, 16], laneData=[1, 2] (adjusted for packed data) +xegpu::DistributeLayoutAttr xegpu::setupInsertStridedSliceResultLayout( + xegpu::LayoutKind layoutKind, VectorType srcVectorTy, + VectorType resVectorTy, xegpu::DistributeLayoutAttr consumerLayout, + const xegpu::uArch::uArch *uArch) { + + xegpu::DistributeLayoutAttr requiredResLayout; + auto subgroupSize = uArch->getSubgroupSize(); + auto context = resVectorTy.getContext(); + auto resShape = resVectorTy.getShape(); + int resShapeSize = resShape.size(); + auto srcShape = srcVectorTy.getShape(); + SmallVector consumerInstData = + consumerLayout.getEffectiveInstDataAsInt(); + SmallVector consumerLaneData = + consumerLayout.getEffectiveLaneDataAsInt(); + + SmallVector instData(resShapeSize, 1); + SmallVector laneLayout(resShapeSize, 1); + SmallVector laneData(resShapeSize, 1); + + const unsigned packingSize{uArch->getGeneralPackedFormatBitSize()}; + unsigned bitwidth = resVectorTy.getElementType().getIntOrFloatBitWidth(); + int packingFactor = bitwidth < packingSize ? packingSize / bitwidth : 1; + int packedDataSize = subgroupSize * packingFactor; + + if (layoutKind == xegpu::LayoutKind::Subgroup) { + assert(true && + "subgroup layout assignment not supported for insertStridedSlice."); + } else if (layoutKind == xegpu::LayoutKind::InstData) { + assert(srcShape.back() >= subgroupSize && + "source innermost dim must be >= subgroupSize"); + instData.back() = subgroupSize; + if (consumerInstData.back() == packedDataSize && + srcShape.back() >= packedDataSize) + instData.back() = packedDataSize; + requiredResLayout = xegpu::LayoutAttr::get(context, instData); + } else if (layoutKind == xegpu::LayoutKind::Lane) { + laneLayout.back() = subgroupSize; + laneData.back() = 1; + if (consumerLaneData.back() == packingFactor && + srcShape.back() >= packedDataSize) + laneData.back() = packingFactor; + requiredResLayout = xegpu::LayoutAttr::get(context, laneLayout, laneData); + } + return requiredResLayout; +} + +/// Sets up the anchor layout for load gather and load matrix operation. +/// load matrix lowers to load gather and 1d block load. All of them share the +/// same layout setup logic. +/// For Subgroup layout, uses the consumer layout directly. +/// non-chunked loads: +/// InstData = {1, ..., min(consumer, maxLaneLoadSize * subgroupSize)} +/// LaneLayout = {1, ..., subgroupSize} +/// lane_data = {1, ..., min(consumer, maxLaneLoadSize)} +/// chunked loads: +/// InstData = {subgroupSize, min(consumer, maxLaneLoadSize)} +/// LaneLayout = {subgroupSize, 1} +/// lane_data={1,min(consumer, maxLaneLoadSize)} +static xegpu::DistributeLayoutAttr setupGenericLoadAnchorLayout( + xegpu::LayoutKind layoutKind, mlir::MLIRContext *context, + xegpu::DistributeLayoutAttr consumerLayout, bool isChunkedLoad, + int maxChunkSize, int valShapeSize, int subgroupSize) { + + if (layoutKind == xegpu::LayoutKind::Subgroup) + return consumerLayout; + + SmallVector consumerInstData = + consumerLayout.getEffectiveInstDataAsInt(); + SmallVector consumerLaneData = + consumerLayout.getEffectiveLaneDataAsInt(); + + SmallVector instData(valShapeSize, 1); + SmallVector laneLayout(valShapeSize, 1); + SmallVector laneData(valShapeSize, 1); + + if (!isChunkedLoad) { + if (layoutKind == xegpu::LayoutKind::InstData) { + instData[valShapeSize - 1] = + std::min(static_cast(consumerInstData[valShapeSize - 1]), + maxChunkSize * subgroupSize); + return xegpu::LayoutAttr::get(context, instData); + } else if (layoutKind == xegpu::LayoutKind::Lane) { + laneLayout.back() = subgroupSize; + laneData.back() = + std::min(static_cast(consumerLaneData.back()), maxChunkSize); + return xegpu::LayoutAttr::get(context, laneLayout, laneData); + } + } else { + assert(valShapeSize == 2 && "Chunked Store must access 2D tensor tile."); + if (layoutKind == xegpu::LayoutKind::InstData) { + instData[0] = subgroupSize; + instData[1] = + std::min(static_cast(consumerInstData[1]), maxChunkSize); + return xegpu::LayoutAttr::get(context, instData); + } else if (layoutKind == xegpu::LayoutKind::Lane) { + laneLayout[0] = subgroupSize; + laneData[1] = + std::min(static_cast(consumerLaneData[1]), maxChunkSize); + return xegpu::LayoutAttr::get(context, laneLayout, laneData); + } + } + return nullptr; +} + +/// Sets up the anchor layout for a load gather operation. +xegpu::DistributeLayoutAttr xegpu::setupLoadGatherAnchorLayout( + xegpu::LayoutKind layoutKind, VectorType resVecTy, int chunkSize, + xegpu::DistributeLayoutAttr consumerLayout, const uArch::uArch *uArch) { + + const int subgroupSize = uArch->getSubgroupSize(); + int resShapeSize = resVecTy.getShape().size(); + auto context = resVecTy.getContext(); + auto elemBitWidth = resVecTy.getElementType().getIntOrFloatBitWidth(); + + const auto *uArchInstruction = + dyn_cast( + uArch->getInstruction(xegpu::uArch::InstructionKind::LoadGather)); + int maxChunkSize = uArchInstruction->getMaxLaneLoadSize(elemBitWidth); + + return setupGenericLoadAnchorLayout(layoutKind, context, consumerLayout, + (chunkSize > 1), maxChunkSize, + resShapeSize, subgroupSize); +} + +/// Sets up the anchor layout for load matrix operation. +/// TODO: enhance load matrix to indicate lowering to chunked load or not. +xegpu::DistributeLayoutAttr +xegpu::setupLoadMatrixAnchorLayout(xegpu::LayoutKind layoutKind, + VectorType resVecTy, + xegpu::DistributeLayoutAttr consumerLayout, + const xegpu::uArch::uArch *uArch) { + + const int subgroupSize = uArch->getSubgroupSize(); + int resShapeSize = resVecTy.getShape().size(); + auto context = resVecTy.getContext(); + auto elemBitWidth = resVecTy.getElementType().getIntOrFloatBitWidth(); + + const auto *uArchInstruction = dyn_cast( + uArch->getInstruction(xegpu::uArch::InstructionKind::LoadMatrix)); + int maxChunkSize = uArchInstruction->getMaxLaneLoadSize(elemBitWidth); + return setupGenericLoadAnchorLayout(layoutKind, context, consumerLayout, + false, maxChunkSize, resShapeSize, + subgroupSize); +} + +/// Sets up the anchor layout for store scatter and store matrix operation. +/// store matrix lowers to store scatter and 1d block store. All of them share +/// the same layout setup logic. For Subgroup layout, not support yet. +/// non-chunked stores: +/// InstData = {1, ..., subgroupSize} +/// LaneLayout = {1, ..., subgroupSize} +/// lane_data = {1, ..., 1} +/// chunked stores: +/// InstData = {subgroupSize, min(srcVec, maxLaneStoreSize)} +/// LaneLayout = {subgroupSize, 1} +/// lane_data={1,min(srcVec, maxLaneStoreSize)} +static xegpu::DistributeLayoutAttr +setupGenericStoreAnchorLayout(xegpu::LayoutKind layoutKind, + mlir::MLIRContext *context, bool isChunkedStore, + int maxChunkSize, ArrayRef srcShape, + int subgroupSize) { + + int srcShapeSize = srcShape.size(); + SmallVector instData(srcShapeSize, 1); + SmallVector laneLayout(srcShapeSize, 1); + SmallVector laneData(srcShapeSize, 1); + + if (layoutKind == xegpu::LayoutKind::Subgroup) { + assert(true && + "subgroup layout assignment not supported for storeScatter."); + return nullptr; + } + + if (!isChunkedStore) { + if (layoutKind == xegpu::LayoutKind::InstData) { + instData[srcShapeSize - 1] = subgroupSize; + return xegpu::LayoutAttr::get(context, instData); + } else if (layoutKind == xegpu::LayoutKind::Lane) { + laneLayout[srcShapeSize - 1] = subgroupSize; + return xegpu::LayoutAttr::get(context, laneLayout, laneData); + } + } else { + assert(srcShapeSize == 2 && "Chunked Store must access 2D tensor tile."); + if (layoutKind == xegpu::LayoutKind::InstData) { + instData[0] = subgroupSize; + instData[1] = std::min(static_cast(srcShape[1]), maxChunkSize); + return xegpu::LayoutAttr::get(context, instData); + } else if (layoutKind == xegpu::LayoutKind::Lane) { + laneLayout[0] = subgroupSize; + laneData[1] = std::min(static_cast(srcShape[1]), maxChunkSize); + return xegpu::LayoutAttr::get(context, laneLayout, laneData); + } + } + return nullptr; +} + +/// Sets up the anchor layout for a store scatter operation. +xegpu::DistributeLayoutAttr +xegpu::setupStoreScatterAnchorLayout(xegpu::LayoutKind layoutKind, + VectorType srcVecTy, int chunkSize, + const uArch::uArch *uArch) { + + const int subgroupSize = uArch->getSubgroupSize(); + ArrayRef srcShape = srcVecTy.getShape(); + auto context = srcVecTy.getContext(); + auto elemBitWidth = srcVecTy.getElementType().getIntOrFloatBitWidth(); + + const auto *uArchInstruction = + dyn_cast( + uArch->getInstruction(xegpu::uArch::InstructionKind::StoreScatter)); + int maxChunkSize = uArchInstruction->getMaxLaneStoreSize(elemBitWidth); + return setupGenericStoreAnchorLayout(layoutKind, context, (chunkSize > 1), + maxChunkSize, srcShape, subgroupSize); +} + +/// Sets up the anchor layout for a store matrix operation. +xegpu::DistributeLayoutAttr +xegpu::setupStoreMatrixAnchorLayout(xegpu::LayoutKind layoutKind, + VectorType srcVecTy, + const xegpu::uArch::uArch *uArch) { + + const int subgroupSize = uArch->getSubgroupSize(); + ArrayRef srcShape = srcVecTy.getShape(); + auto context = srcVecTy.getContext(); + auto elemBitWidth = srcVecTy.getElementType().getIntOrFloatBitWidth(); + + const auto *uArchInstruction = dyn_cast( + uArch->getInstruction(xegpu::uArch::InstructionKind::StoreMatrix)); + int maxChunkSize = uArchInstruction->getMaxLaneStoreSize(elemBitWidth); + + return setupGenericStoreAnchorLayout(layoutKind, context, false, maxChunkSize, + srcShape, subgroupSize); +} \ No newline at end of file diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp index 6a3e533fb2df4..8694bca974df1 100644 --- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp +++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp @@ -16,6 +16,7 @@ #include "mlir/Dialect/XeGPU/IR/XeGPU.h" #include "mlir/Dialect/XeGPU/Transforms/Passes.h" #include "mlir/Dialect/XeGPU/Transforms/Transforms.h" +#include "mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h" #include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h" #include "mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h" #include "mlir/Dialect/XeGPU/uArch/uArchBase.h" diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp index 96fdced39d9ab..ccfab7350e351 100644 --- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp +++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp @@ -15,7 +15,7 @@ #include "mlir/Dialect/Vector/IR/VectorOps.h" #include "mlir/Dialect/XeGPU/IR/XeGPU.h" #include "mlir/Dialect/XeGPU/Transforms/Passes.h" -#include "mlir/Dialect/XeGPU/Transforms/Transforms.h" +#include "mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h" #include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h" #include "mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h" #include "mlir/IR/Attributes.h" @@ -127,6 +127,7 @@ struct LayoutInfo { } Attribute get() { return storage; } + void set(const xegpu::DistributeLayoutAttr &layout) { storage = layout; } }; SmallVector LayoutInfo::getLaneLayout() const { @@ -307,27 +308,6 @@ static LayoutInfo getSIMTLayoutInfoBlockIO(Ty ty, ty.getContext(), {1, uArch->getSubgroupSize()}, {1, packingFactor})); } -/// Helper to get the default layout for a vector type. -static LayoutInfo getSIMTLayoutInfoScatterIO(VectorType vectorTy, - const xegpu::uArch::uArch *uArch) { - // Expecting a 1D or 2D vector. - assert((vectorTy.getRank() == 1 || vectorTy.getRank() == 2) && - "Expected 1D or 2D vector."); - // Expecting int or float element type. - assert(vectorTy.getElementType().isIntOrFloat() && - "Expected int or float element type."); - // If the rank is 1, then return default layout for 1D vector. - const unsigned packingSize{uArch->getGeneralPackedFormatBitSize()}; - if (vectorTy.getRank() == 1) - return getDefaultSIMTLayoutInfo(vectorTy.getContext(), 1, uArch); - // Packing factor is determined by the element type bitwidth. - unsigned bitwidth = vectorTy.getElementType().getIntOrFloatBitWidth(); - int packingFactor = bitwidth < packingSize ? packingSize / bitwidth : 1; - return LayoutInfo(xegpu::LayoutAttr::get(vectorTy.getContext(), - {uArch->getSubgroupSize(), 1}, - {1, packingFactor})); -} - /// Helper Function to get the expected layouts for DPAS operands. `lane_data` /// is set according to the following criteria: /// * For A operand, the data must be packed in minimum @@ -417,11 +397,27 @@ class LayoutInfoPropagation void visitShapeCastOp(vector::ShapeCastOp shapeCast, ArrayRef operands, ArrayRef results); + void + visitInsertStridedSliceOp(vector::InsertStridedSliceOp insertStridedSlice, + ArrayRef operands, + ArrayRef results); + + void visitLoadMatrixOp(xegpu::LoadMatrixOp load, + ArrayRef operands, + ArrayRef results); void visitStoreMatrixOp(xegpu::StoreMatrixOp store, ArrayRef operands, ArrayRef results); + void visitLoadGatherOp(xegpu::LoadMatrixOp load, + ArrayRef operands, + ArrayRef results); + + void visitStoreScatterOp(xegpu::StoreMatrixOp store, + ArrayRef operands, + ArrayRef results); + bool hasParamsOfLayoutKind(xegpu::DistributeLayoutAttr anchorLayout); public: @@ -497,6 +493,12 @@ LogicalResult LayoutInfoPropagation::visitOperation( .Case([&](vector::ShapeCastOp shapeCastOp) { visitShapeCastOp(shapeCastOp, operands, results); }) + .Case([&](vector::InsertStridedSliceOp insertStridedSliceOp) { + visitInsertStridedSliceOp(insertStridedSliceOp, operands, results); + }) + .Case([&](xegpu::LoadMatrixOp loadMatrixOp) { + visitLoadMatrixOp(loadMatrixOp, operands, results); + }) .Case([&](xegpu::StoreMatrixOp storeMatrixOp) { visitStoreMatrixOp(storeMatrixOp, operands, results); }) @@ -646,32 +648,45 @@ void LayoutInfoPropagation::visitVectorMultiReductionOp( ArrayRef operands, ArrayRef results) { // The layout of the result must be present. - LayoutInfo resultLayout = results[0]->getValue(); - if (!resultLayout.isAssigned()) - return; - // We only consider 2D -> 1D reductions at this point. - VectorType resultTy = llvm::dyn_cast(reduction.getDestType()); - if (!resultTy || resultTy.getRank() != 1) { - reduction.emitWarning("Expecting output type to be 1D vector."); + LayoutInfo resLayoutInfo = results[0]->getValue(); + if (!resLayoutInfo.isAssigned()) return; - } + + VectorType sourceTy = reduction.getSourceVectorType(); + SmallVector reductionDims(reduction.getReductionDims()); + auto uArch = getUArch(xegpu::getChipStr(reduction).value_or("")); - // Given that the result is 1D, the layout of the operand should be 2D with - // default layout. - LayoutInfo operandLayout = getDefaultSIMTLayoutInfo( - reduction->getContext(), 2, uArch->getSubgroupSize()); - propagateIfChanged(operands[0], operands[0]->meet(operandLayout)); + auto consumerLayoutAttr = + dyn_cast(resLayoutInfo.get()); + + // The result layout represents the layout requirements of the operation. + // it is recorded to anchor layout or temporary layout. + // it must be honored for current op and may conflict with the layout + // propagated from consumer op, the conflict is resolved in later phase by + // converting the required result layout to the consumer layout + auto requiredResLayoutAttr = xegpu::setupMultiReductionResultLayout( + layoutKind, sourceTy, consumerLayoutAttr, reductionDims, uArch); + + xegpu::setTemporaryLayout(reduction->getResult(0), requiredResLayoutAttr); + + // derive the source layout from the dominant layout and reduction dims + auto srcLayoutAttr = xegpu::inferMultiReductionSourceLayout( + requiredResLayoutAttr, reductionDims); + + propagateIfChanged(operands[0], operands[0]->meet(LayoutInfo(srcLayoutAttr))); // Accumulator should have the same layout as the result. - propagateIfChanged(operands[1], operands[1]->meet(resultLayout)); + propagateIfChanged(operands[1], + operands[1]->meet(LayoutInfo(requiredResLayoutAttr))); } void LayoutInfoPropagation::visitVectorBroadCastOp( vector::BroadcastOp broadcast, ArrayRef operands, ArrayRef results) { // The layout of the result must be present. - LayoutInfo resultLayout = results[0]->getValue(); - if (!resultLayout.isAssigned()) + LayoutInfo resLayoutInfo = results[0]->getValue(); + if (!resLayoutInfo.isAssigned()) return; + // Only consider vector to vector broadcasts for now. VectorType resultTy = broadcast.getResultVectorType(); VectorType sourceTy = dyn_cast(broadcast.getSourceType()); @@ -679,55 +694,41 @@ void LayoutInfoPropagation::visitVectorBroadCastOp( if (!sourceTy) return; - // Hanlding broadcast from low-rank to high-rank (e.g., 1D to 2D) case. - if (sourceTy.getRank() != resultTy.getRank()) { - auto sourceDims = sourceTy.getShape(); - auto resultDims = resultTy.getShape(); - SmallVector bcastDims; - auto dimDiff = resultTy.getRank() - sourceTy.getRank(); - // adding the missing leading dims - for (int i = 0; i < dimDiff; i++) - bcastDims.push_back(i); - - // for the rest dims in the resultTy, if sourceTy dim is 1, then it's - // broadcasted dim - for (size_t i = 0; i < sourceDims.size(); i++) - if ((sourceDims[i] == 1) && (resultDims[i + dimDiff] != 1)) - bcastDims.push_back(i + dimDiff); - - // create a slice layout for the source - xegpu::SliceAttr sliceLayout = xegpu::SliceAttr::get( - broadcast->getContext(), - cast(resultLayout.get()), - DenseI64ArrayAttr::get(broadcast->getContext(), bcastDims)); - - propagateIfChanged(operands[0], operands[0]->meet(LayoutInfo(sliceLayout))); - return; - } - propagateIfChanged(operands[0], operands[0]->meet(resultLayout)); + auto srcShape = sourceTy.getShape(); + auto resShape = resultTy.getShape(); + + size_t dimDiff = resultTy.getRank() - sourceTy.getRank(); + for (size_t i = 0; i < srcShape.size(); i++) + if ((srcShape[i] == 1) && (resShape[i + dimDiff] != 1)) + broadcast.emitWarning("broadcast must either from low-rank or same-rank " + "with unit-dim, mixed scenario is not supported!"); + + auto resultLayoutAttr = + dyn_cast(resLayoutInfo.get()); + + xegpu::DistributeLayoutAttr srcLayoutAttr = + xegpu::inferBroadcastSourceLayout(resultLayoutAttr, resShape, srcShape); + + propagateIfChanged(operands[0], operands[0]->meet(LayoutInfo(srcLayoutAttr))); + return; } void LayoutInfoPropagation::visitShapeCastOp( vector::ShapeCastOp shapeCast, ArrayRef operands, ArrayRef results) { // The layout of the result must be present. - LayoutInfo resultLayout = results[0]->getValue(); - if (!resultLayout.isAssigned()) + LayoutInfo resLayoutInfo = results[0]->getValue(); + if (!resLayoutInfo.isAssigned()) return; - VectorType sourceTy = shapeCast.getSourceVectorType(); - VectorType resultTy = shapeCast.getResultVectorType(); - // Shape cast layout propagation only supports 1D -> 2D shape casts. - // TODO: Support kD -> nD shape casts (k < n, n >= 2) where expanded dims are - // unit dimensions and non-unit dims match. - if (sourceTy.getRank() != 1 || resultTy.getRank() != 2) { - shapeCast.emitWarning("Expecting shape cast to be 1D -> 2D."); - return; - } - int64_t slicedDim = resultTy.getShape()[0] == 1 ? 0 : 1; - xegpu::SliceAttr sliceLayout = xegpu::SliceAttr::get( - shapeCast->getContext(), cast(resultLayout.get()), - DenseI64ArrayAttr::get(shapeCast->getContext(), {slicedDim})); - propagateIfChanged(operands[0], operands[0]->meet(LayoutInfo(sliceLayout))); + ArrayRef resShape = shapeCast.getResultVectorType().getShape(); + ArrayRef srcShape = shapeCast.getSourceVectorType().getShape(); + auto resultLayoutAttr = + dyn_cast(resLayoutInfo.get()); + + xegpu::DistributeLayoutAttr srcLayoutAttr = + xegpu::inferShapeCastSourceLayout(resultLayoutAttr, resShape, srcShape); + + propagateIfChanged(operands[0], operands[0]->meet(LayoutInfo(srcLayoutAttr))); } /// Propagate the layout of the result tensor to the source tensor descriptor @@ -748,7 +749,6 @@ void LayoutInfoPropagation::visitUpdateNdOffsetOp( void LayoutInfoPropagation::visitDpasOp( xegpu::DpasOp dpas, ArrayRef operands, ArrayRef results) { - LayoutInfo dpasALayout; LayoutInfo dpasBLayout; LayoutInfo dpasCDLayout; @@ -945,7 +945,6 @@ void LayoutInfoPropagation::visitDpasOp( void LayoutInfoPropagation::visitStoreNdOp( xegpu::StoreNdOp store, ArrayRef operands, ArrayRef results) { - LayoutInfo storeLayout; xegpu::DistributeLayoutAttr anchorLayout = store.getLayoutAttr(); if (hasParamsOfLayoutKind(anchorLayout)) { @@ -986,7 +985,7 @@ void LayoutInfoPropagation::visitStoreNdOp( storeLayout = getSIMTLayoutInfoBlockIO(store.getValueType(), uArch, uArchInstruction->getPackedFormatBitSize()); - else { // LayoutKind::Subgroup + else { // xegpu::LayoutKind::Subgroup auto sgSize = uArch->getSubgroupSize(); auto numSgOrErr = getNumSg(store, sgSize); if (failed(numSgOrErr)) { @@ -1026,7 +1025,6 @@ void LayoutInfoPropagation::visitStoreNdOp( void LayoutInfoPropagation::visitLoadNdOp( xegpu::LoadNdOp load, ArrayRef operands, ArrayRef results) { - LayoutInfo loadLayout; xegpu::DistributeLayoutAttr anchorLayout = load.getLayoutAttr(); if (hasParamsOfLayoutKind(anchorLayout)) { @@ -1072,66 +1070,60 @@ void LayoutInfoPropagation::visitVectorBitcastOp( vector::BitCastOp bitcast, ArrayRef operands, ArrayRef results) { // Need the layout of bitcast result to propagate to the operands. - LayoutInfo resultLayout = results[0]->getValue(); - if (!resultLayout.isAssigned()) - return; - int inElemTyBitWidth = - bitcast.getSourceVectorType().getElementType().getIntOrFloatBitWidth(); - int outElemTyBitWidth = - bitcast.getResultVectorType().getElementType().getIntOrFloatBitWidth(); - // If the element bit widths are the same, then the layout does not change. - if (inElemTyBitWidth == outElemTyBitWidth) { - propagateIfChanged(operands[0], operands[0]->meet(resultLayout)); + LayoutInfo resLayoutInfo = results[0]->getValue(); + if (!resLayoutInfo.isAssigned()) return; - } - // Check if the result layout is valid. i.e. result vector can be distributed. - auto resultLaneLayout = resultLayout.getLaneLayout(); - auto resultLaneData = resultLayout.getLaneData(); - if (failed(xegpu::getDistributedVectorType( - bitcast.getResultVectorType(), - xegpu::LayoutAttr::get(bitcast->getContext(), resultLaneLayout, - resultLaneData)))) { - bitcast.emitWarning( - "Result vector type can not be evenly distributed across lanes."); - return; - } - int64_t rank = bitcast.getSourceVectorType().getRank(); - // Bitcast is a `narrowing` if the input element type bit width larger than - // the output element type bit width. eg. f32 -> f16 is a narrowing bitcast. - bool isNarrowing = inElemTyBitWidth > outElemTyBitWidth; - int bitCastRatio = isNarrowing ? inElemTyBitWidth / outElemTyBitWidth - : outElemTyBitWidth / inElemTyBitWidth; - SmallVector sourceLaneLayout = - resultLayout.getLaneLayout(); // Lane layout does not change for bitcast. - SmallVector outData = resultLayout.getLaneData(); - - // TODO: Currently we assume that bitcasts does not require cross lane - // communication. So each lane must own the required number of elements to - // perform the bitcast locally without cross-lane communication. - int outInnerBitsPerLane = outData[rank - 1] * outElemTyBitWidth; - if (outInnerBitsPerLane < inElemTyBitWidth) { - bitcast.emitWarning( - "Narrowing bitcast with cross lane communication is not supported."); - return; - } - // Check if each lane owns a single element in all dimensions except the - // innermost dimension. - SmallVector sourceLaneData(outData.begin(), outData.end() - 1); - if (llvm::any_of(sourceLaneData, [](int64_t d) { return d != 1; })) { - bitcast.emitWarning("Each lane must not own multiple elements in any " - "dimension other than " - "the innermost dimension."); + + auto srcVecType = bitcast.getSourceVectorType(); + auto resVecType = bitcast.getResultVectorType(); + + auto consumerLayoutAttr = + dyn_cast(resLayoutInfo.get()); + auto uArch = getUArch(xegpu::getChipStr(bitcast).value_or("")); + auto requiredResLayoutAttr = setupBitCastResultLayout( + layoutKind, srcVecType, resVecType, consumerLayoutAttr, uArch); + + xegpu::setTemporaryLayout(bitcast->getResult(0), requiredResLayoutAttr); + + int inElemTyBitWidth = srcVecType.getElementType().getIntOrFloatBitWidth(); + int outElemTyBitWidth = resVecType.getElementType().getIntOrFloatBitWidth(); + + // derive the source layout from the dominant layout and reduction dims + auto srcLayoutAttr = xegpu::inferBitCastSourceLayout( + requiredResLayoutAttr, outElemTyBitWidth, inElemTyBitWidth); + + propagateIfChanged(operands[0], operands[0]->meet(LayoutInfo(srcLayoutAttr))); +} + +void LayoutInfoPropagation::visitInsertStridedSliceOp( + vector::InsertStridedSliceOp insertStridedSlice, + ArrayRef operands, + ArrayRef results) { + // The layout of the result must be present. + LayoutInfo resLayoutInfo = results[0]->getValue(); + if (!resLayoutInfo.isAssigned()) return; - } - // Decide lane data based on whether the bitcast is narrowing or widening. - int64_t innerMostLaneData = isNarrowing ? outData[rank - 1] / bitCastRatio - : outData[rank - 1] * bitCastRatio; - sourceLaneData.push_back(innerMostLaneData); - - propagateIfChanged( - operands[0], - operands[0]->meet(LayoutInfo(xegpu::LayoutAttr::get( - bitcast->getContext(), sourceLaneLayout, sourceLaneData)))); + + auto srcVecType = insertStridedSlice.getSourceVectorType(); + auto resVecType = insertStridedSlice.getDestVectorType(); + + auto consumerLayoutAttr = + dyn_cast(resLayoutInfo.get()); + auto uArch = getUArch(xegpu::getChipStr(insertStridedSlice).value_or("")); + + auto requiredResLayoutAttr = xegpu::setupInsertStridedSliceResultLayout( + layoutKind, srcVecType, resVecType, consumerLayoutAttr, uArch); + + xegpu::setTemporaryLayout(insertStridedSlice->getResult(0), + requiredResLayoutAttr); + + auto srcLayoutAttr = xegpu::inferInsertStridedSliceSourceLayout( + requiredResLayoutAttr, resVecType.getShape(), srcVecType.getShape()); + + propagateIfChanged(operands[0], operands[0]->meet(LayoutInfo(srcLayoutAttr))); + propagateIfChanged(operands[1], + operands[1]->meet(LayoutInfo(requiredResLayoutAttr))); + return; } /// Propagate the layout of the result to the tensor descriptor, mask and offset @@ -1139,96 +1131,56 @@ void LayoutInfoPropagation::visitVectorBitcastOp( void LayoutInfoPropagation::visitLoadGatherOp( xegpu::LoadGatherOp load, ArrayRef operands, ArrayRef results) { - - LayoutInfo loadLayout; - LayoutInfo maskLayout; + xegpu::DistributeLayoutAttr requiredAnchorLayoutAttr; + xegpu::DistributeLayoutAttr anchorLayoutAttr = load.getLayoutAttr(); auto uArch = getUArch(getChipStr(load).value_or("")); - const int subgroupSize = uArch->getSubgroupSize(); - xegpu::DistributeLayoutAttr anchorLayout = load.getLayoutAttr(); - if (hasParamsOfLayoutKind(anchorLayout)) { - loadLayout = LayoutInfo(anchorLayout); - maskLayout = loadLayout; - } else { - LayoutInfo valueLayout = results[0]->getValue(); - // Need the layout of the value to propagate to the tensor descriptor. - if (!valueLayout.isAssigned()) - return; + auto subgroupSize = uArch->getSubgroupSize(); + VectorType resVecTy = load.getValueType(); + int chunkSize = load.getChunkSize().value_or(1); - auto resAttr = dyn_cast(valueLayout.get()); - auto instDataIncoming = resAttr.getEffectiveInstDataAsInt(); - if (auto sliceAttr = dyn_cast(resAttr)) - instDataIncoming = SmallVector( - cast(sliceAttr.flatten().getParent()) - .getInstData() - .asArrayRef()); + LayoutInfo resLayoutInfo = results[0]->getValue(); + if (!resLayoutInfo.isAssigned()) + return; + auto consumerLayoutAttr = + dyn_cast(resLayoutInfo.get()); - VectorType payloadTy = load.getValueType(); - if (!payloadTy) { + if (hasParamsOfLayoutKind(anchorLayoutAttr)) { + requiredAnchorLayoutAttr = anchorLayoutAttr; + } else { + if (!resVecTy) { load.emitWarning("Not propagating, non-vector payload supplied."); return; } - const auto *uArchInstruction = - dyn_cast( - uArch->getInstruction(xegpu::uArch::InstructionKind::LoadGather)); - - // Check if value inst_data complies with uArch - if (layoutKind == xegpu::LayoutKind::InstData) { - // Each lane loads either one element - SmallVector instDataUarch{subgroupSize}; - // Or multiple elements as 2D with lane's elements in the inner dimension - if (payloadTy.getRank() != 1) { - if (payloadTy.getRank() != 2) { - load.emitWarning("Expected 2D payload for LoadGatherOp."); - return; - } - instDataUarch.push_back( - (std::min(static_cast(payloadTy.getShape().back()), - uArchInstruction->getMaxLaneLoadStoreSize()))); - } - // If inst data does not match, enforce the uArch-based one - if (!llvm::equal(instDataIncoming, instDataUarch)) { - xegpu::LayoutAttr sourceAttr = dyn_cast(resAttr); - if (auto sliceAttr = dyn_cast(resAttr)) { - sourceAttr = cast(sliceAttr.flatten().getParent()); - } - assert(sourceAttr); - xegpu::DistributeLayoutAttr updatedLayoutAttr = xegpu::LayoutAttr::get( - load.getContext(), sourceAttr.getSgLayout(), sourceAttr.getSgData(), - DenseI32ArrayAttr::get(load.getContext(), instDataUarch), - sourceAttr.getLaneLayout(), sourceAttr.getLaneData(), - sourceAttr.getOrder()); - - if (auto sliceAttr = dyn_cast(resAttr)) - updatedLayoutAttr = xegpu::SliceAttr::get( - load.getContext(), updatedLayoutAttr, sliceAttr.getDims()); - valueLayout = LayoutInfo(updatedLayoutAttr); - } - } - loadLayout = valueLayout; - load.setLayoutAttr(dyn_cast(loadLayout.get())); + requiredAnchorLayoutAttr = xegpu::setupLoadGatherAnchorLayout( + layoutKind, resVecTy, chunkSize, consumerLayoutAttr, uArch); + load.setLayoutAttr(requiredAnchorLayoutAttr); } - // If no user-defined anchor or we deal with a chunked op, set the default - // mask layout. - // Rank 1 data : Keep the mask layout aligned with data. - // Rank >1 data: Enforce the default xegpu 1D layout for mask. - if (!hasParamsOfLayoutKind(anchorLayout) || - load.getValueType().getRank() > 1) { + auto maskLayoutAttr = requiredAnchorLayoutAttr; + // Special handling mask layout for chunked ops: Enforce the default xegpu 1D + // layout for mask. + if (chunkSize > 1) { if (layoutKind == xegpu::LayoutKind::InstData) - maskLayout = LayoutInfo( - xegpu::LayoutAttr::get(load->getContext(), {subgroupSize})); + maskLayoutAttr = + xegpu::LayoutAttr::get(load->getContext(), {subgroupSize}); else if (layoutKind == xegpu::LayoutKind::Lane) - maskLayout = - getDefaultSIMTLayoutInfo(load->getContext(), 1, subgroupSize); + maskLayoutAttr = + xegpu::LayoutAttr::get(load->getContext(), {subgroupSize}, {1}); + else + assert(false && + "chunked StoreScatterOp should not be used at workgroup level"); } + LayoutInfo maskLayoutInfo = LayoutInfo(maskLayoutAttr); + auto loadLayoutInfo = LayoutInfo(requiredAnchorLayoutAttr); + // Propagate the new layout to the tensor descriptor operand. if (isa(load.getSourceType())) - propagateIfChanged(operands[0], operands[0]->meet(loadLayout)); + propagateIfChanged(operands[0], operands[0]->meet(loadLayoutInfo)); // Propagate the new layout to the mask and optional offset operand. - propagateIfChanged(operands[1], operands[1]->meet(maskLayout)); + propagateIfChanged(operands[1], operands[1]->meet(maskLayoutInfo)); if (load.getOffsets()) - propagateIfChanged(operands[2], operands[2]->meet(maskLayout)); + propagateIfChanged(operands[2], operands[2]->meet(maskLayoutInfo)); } /// Propagate the layout of the descriptor to the vector offset operand in @@ -1253,107 +1205,97 @@ void LayoutInfoPropagation::visitStoreScatterOp( xegpu::StoreScatterOp storeScatter, ArrayRef operands, ArrayRef results) { - LayoutInfo payloadLayout; - LayoutInfo maskLayout; - xegpu::DistributeLayoutAttr anchorLayout = storeScatter.getLayoutAttr(); + xegpu::DistributeLayoutAttr requiredAnchorLayoutAttr; + xegpu::DistributeLayoutAttr anchorLayoutAttr = storeScatter.getLayoutAttr(); auto uArch = getUArch(getChipStr(storeScatter).value_or("")); - const int subgroupSize = uArch->getSubgroupSize(); + auto subgroupSize = uArch->getSubgroupSize(); + VectorType srcVecTy = storeScatter.getValueType(); + int chunkSize = storeScatter.getChunkSize().value_or(1); - if (hasParamsOfLayoutKind(anchorLayout)) { - payloadLayout = LayoutInfo(anchorLayout); - maskLayout = payloadLayout; + if (hasParamsOfLayoutKind(anchorLayoutAttr)) { + requiredAnchorLayoutAttr = anchorLayoutAttr; } else { - // Currently, for 2D StoreScatterOp we expect that the height dimension of - // the tensor descriptor is equal to the subgroup size. This is ensured by - // the op verifier. - VectorType payloadTy = storeScatter.getValueType(); - if (!payloadTy) { + if (!srcVecTy) { storeScatter.emitWarning("Not propagating, non-vector payload supplied."); return; } - - if (layoutKind == xegpu::LayoutKind::InstData) { - const auto *uArchInstruction = - dyn_cast(uArch->getInstruction( - xegpu::uArch::InstructionKind::StoreScatter)); - const int subgroupSize = uArch->getSubgroupSize(); - SmallVector instDataUarch{subgroupSize}; - if (payloadTy.getRank() != 1) { - if (payloadTy.getRank() != 2) { - storeScatter.emitWarning("Expected 2D payload for StoreScatterOp."); - return; - } - instDataUarch.push_back( - (std::min(static_cast(payloadTy.getShape().back()), - uArchInstruction->getMaxLaneLoadStoreSize()))); - } - payloadLayout = LayoutInfo( - xegpu::LayoutAttr::get(storeScatter.getContext(), instDataUarch)); - } else { - auto payloadShape = payloadTy.getShape(); - if (payloadShape.size() > 1) - assert(payloadShape[0] == subgroupSize && - "Expected the first dimension of 2D tensor descriptor to be " - "equal to " - "subgroup size."); - payloadLayout = getSIMTLayoutInfoScatterIO(payloadTy, uArch); - } - - storeScatter.setLayoutAttr( - dyn_cast(payloadLayout.get())); + requiredAnchorLayoutAttr = xegpu::setupStoreScatterAnchorLayout( + layoutKind, srcVecTy, chunkSize, uArch); + storeScatter.setLayoutAttr(requiredAnchorLayoutAttr); } - // If no user-defined anchor or we deal with a chunked op, set the default - // mask layout. - // Rank 1 data : Keep the mask layout aligned with data. - // Rank >1 data: Enforce the default xegpu 1D layout for mask. - if (!hasParamsOfLayoutKind(anchorLayout) || - storeScatter.getValueType().getRank() > 1) { + LayoutInfo srcLayoutInfo = LayoutInfo(requiredAnchorLayoutAttr); + auto maskLayoutAttr = requiredAnchorLayoutAttr; + // Special handling mask layout for chunked ops: Enforce the default xegpu 1D + // layout for mask. + if (chunkSize > 1) { if (layoutKind == xegpu::LayoutKind::InstData) - maskLayout = LayoutInfo( - xegpu::LayoutAttr::get(storeScatter->getContext(), {subgroupSize})); + maskLayoutAttr = + xegpu::LayoutAttr::get(storeScatter->getContext(), {subgroupSize}); else if (layoutKind == xegpu::LayoutKind::Lane) - maskLayout = - getDefaultSIMTLayoutInfo(storeScatter->getContext(), 1, subgroupSize); + maskLayoutAttr = xegpu::LayoutAttr::get(storeScatter->getContext(), + {subgroupSize}, {1}); + else + assert(false && + "chunked StoreScatterOp should not be used at workgroup level"); } + LayoutInfo maskLayoutInfo = LayoutInfo(maskLayoutAttr); + // Propagate the payload operand layout - propagateIfChanged(operands[0], operands[0]->meet(payloadLayout)); + propagateIfChanged(operands[0], operands[0]->meet(srcLayoutInfo)); // Propagate the destination (if tdesc) operand layout if (isa(storeScatter.getDestType())) - propagateIfChanged(operands[1], operands[1]->meet(payloadLayout)); + propagateIfChanged(operands[1], operands[1]->meet(srcLayoutInfo)); // Propagate the new layout to the mask and optional offset operand. - propagateIfChanged(operands[2], operands[2]->meet(maskLayout)); + propagateIfChanged(operands[2], operands[2]->meet(maskLayoutInfo)); if (storeScatter.getOffsets()) - propagateIfChanged(operands[3], operands[3]->meet(maskLayout)); + propagateIfChanged(operands[3], operands[3]->meet(maskLayoutInfo)); +} + +void LayoutInfoPropagation::visitLoadMatrixOp( + xegpu::LoadMatrixOp loadMatrixOp, ArrayRef operands, + ArrayRef results) { + + LayoutInfo resLayoutInfo = results[0]->getValue(); + auto consumerLayoutAttr = + dyn_cast(resLayoutInfo.get()); + + xegpu::DistributeLayoutAttr anchorLayout = loadMatrixOp.getLayoutAttr(); + + // only need to set anchor layout, no need to porpagate to memdesc and + // offset + if (!hasParamsOfLayoutKind(anchorLayout)) { + VectorType resVecTy = + llvm::cast(loadMatrixOp.getRes().getType()); + assert(resVecTy.getRank() == 2 && "Expecting 2D vector for store matrix."); + auto uArch = getUArch(getChipStr(loadMatrixOp).value_or("")); + auto requiredAnchorLayoutAttr = xegpu::setupLoadMatrixAnchorLayout( + layoutKind, resVecTy, consumerLayoutAttr, uArch); + loadMatrixOp.setLayoutAttr(requiredAnchorLayoutAttr); + } } // Store matrix is a flavor of scattered store for 2D shapes. void LayoutInfoPropagation::visitStoreMatrixOp( xegpu::StoreMatrixOp storeMatrix, ArrayRef operands, ArrayRef results) { - Value operand = storeMatrix.getData(); - unsigned index = - std::distance(storeMatrix.operand_begin(), - llvm::find(storeMatrix->getOperands(), operand)); - xegpu::DistributeLayoutAttr anchorLayout = storeMatrix.getLayoutAttr(); LayoutInfo layout; if (hasParamsOfLayoutKind(anchorLayout)) { layout = LayoutInfo(anchorLayout); } else { - VectorType payloadTy = llvm::cast(operand.getType()); - assert(payloadTy.getRank() == 2 && "Expecting 2D vector for store matrix."); + VectorType srcVecTy = + llvm::cast(storeMatrix.getData().getType()); + assert(srcVecTy.getRank() == 2 && "Expecting 2D vector for store matrix."); auto uArch = getUArch(getChipStr(storeMatrix).value_or("")); - SmallVector instData = {1, uArch->getSubgroupSize()}; - if (layoutKind == xegpu::LayoutKind::InstData) - layout = LayoutInfo( - xegpu::LayoutAttr::get(storeMatrix.getContext(), instData)); - else - layout = getSIMTLayoutInfoScatterIO(payloadTy, uArch); + auto requiredAnchorLayoutAttr = + xegpu::setupStoreMatrixAnchorLayout(layoutKind, srcVecTy, uArch); + storeMatrix.setLayoutAttr(requiredAnchorLayoutAttr); + layout = LayoutInfo(requiredAnchorLayoutAttr); } - propagateIfChanged(operands[index], operands[index]->meet(layout)); + propagateIfChanged(operands[0], operands[0]->meet(layout)); } namespace { @@ -1733,10 +1675,24 @@ LogicalResult xegpu::propagateLayouts(OpBuilder &builder, Operation *target, LayoutInfo layout = analysis.getLayoutInfo(val); if (!layout.isAssigned()) return {}; + if (auto opResult = dyn_cast(val)) { + + Operation *defOp = opResult.getDefiningOp(); + if (auto anchorOp = dyn_cast(defOp)) { + auto anchorLayout = anchorOp.getAnchorLayout(); + if (anchorLayout != nullptr) + return anchorLayout; + } + xegpu::DistributeLayoutAttr requiredResLayoutAttr = + xegpu::getTemporaryLayout(opResult); + if (requiredResLayoutAttr != nullptr) + return requiredResLayoutAttr; + } xegpu::DistributeLayoutAttr layoutAttr = cast(layout.get()); if (layout.isSliceLayout()) return cast(layoutAttr); + return cast(layoutAttr); }; diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp index a8ed5a289f84a..5cd9772204590 100644 --- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp +++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp @@ -14,6 +14,7 @@ #include "mlir/Dialect/XeGPU/IR/XeGPU.h" #include "mlir/Dialect/XeGPU/Transforms/Passes.h" #include "mlir/Dialect/XeGPU/Transforms/Transforms.h" +#include "mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h" #include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h" #include "mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h" #include "mlir/IR/AffineMap.h" @@ -1532,8 +1533,9 @@ struct VectorBroadcastDistribution : public gpu::WarpDistributionPattern { } // case 2: source and result have same rank if (rankDiff == 0) { - SetVector broadcastUnitDims = - broadcastOp.computeBroadcastedUnitDims(); + auto broadcastUnitDimsSet = broadcastOp.computeBroadcastedUnitDims(); + SmallVector broadcastUnitDims(broadcastUnitDimsSet.begin(), + broadcastUnitDimsSet.end()); bool isEqualTo = sourceLayout.isEqualTo(resultLayout); if (!isEqualTo) return rewriter.notifyMatchFailure( @@ -1611,19 +1613,6 @@ struct VectorShapeCastDistribution : public gpu::WarpDistributionPattern { warpOp, "the source or result of shape_cast op lacks distribution layout"); - // For rank reducing or increasing shape_cast ops, the lower rank layout - // must be a slice of higher rank layout. - int64_t sourceRank = shapeCastOp.getSourceVectorType().getRank(); - int64_t resultRank = shapeCastOp.getResultVectorType().getRank(); - if (sourceRank < resultRank && !sourceLayout.isSliceOf(resultLayout)) - return rewriter.notifyMatchFailure( - warpOp, "shape_cast is rank reducing but source layout is not a " - "slice of result layout"); - if (sourceRank > resultRank && !resultLayout.isSliceOf(sourceLayout)) - return rewriter.notifyMatchFailure( - warpOp, "shape_cast is rank increasing but result layout is not a " - "slice of source layout"); - FailureOr sourceDistTypeOrFailure = getDistVecTypeBasedOnLaneLayout(sourceLayout, shapeCastOp.getSourceVectorType()); @@ -1902,8 +1891,8 @@ struct MemrefExtractAlignedPointerAsIndexDistribution final auto newExtractOp = memref::ExtractAlignedPointerAsIndexOp::create( rewriter, newWarpOp.getLoc(), extractOp.getType(), newWarpOp.getResult(newRetIndices[0])); - Value distributedVal = newWarpOp.getResult(operandIdx); - rewriter.replaceAllUsesWith(distributedVal, newExtractOp.getResult()); + Value resultVal = newWarpOp.getResult(operandIdx); + rewriter.replaceAllUsesWith(resultVal, newExtractOp.getResult()); return success(); } }; diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp index 8f4e2bb0451d8..2b1bd4d73a576 100644 --- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp +++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp @@ -15,6 +15,7 @@ #include "mlir/Dialect/Utils/IndexingUtils.h" #include "mlir/Dialect/XeGPU/IR/XeGPU.h" #include "mlir/Dialect/XeGPU/Transforms/Transforms.h" +#include "mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h" #include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/DebugLog.h" diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp index 45a002b63abd6..cd6bc9ac4b8e0 100644 --- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp +++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp @@ -19,6 +19,7 @@ #include "mlir/Dialect/Utils/IndexingUtils.h" #include "mlir/Dialect/XeGPU/IR/XeGPU.h" #include "mlir/Dialect/XeGPU/Transforms/Transforms.h" +#include "mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h" #include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h" #include "mlir/Transforms/DialectConversion.h" #include @@ -510,8 +511,6 @@ struct WgToSgVectorBroadcastOp for (auto operand : adaptor.getOperands().front()) { auto newBroadcast = vector::BroadcastOp::create(rewriter, op.getLoc(), newResultType, operand); - xegpu::setTemporaryLayout(newBroadcast->getResult(0), - layout.dropSgLayoutAndData()); newBroadcastOps.push_back(newBroadcast.getResult()); } @@ -563,10 +562,9 @@ struct WgToSgElementwiseOp : public ConversionPattern { OperationState state(op->getLoc(), op->getName()); state.addOperands(opOperands); state.addTypes(newResultType); - // Copy all attributes, but update "layout_result_0" to drop - // sgLayout/sgData - state.addAttributes(xegpu::dropSgLayoutAndDataOnAttrs(op->getAttrs())); + state.addAttributes(op->getAttrs()); Operation *newOp = rewriter.create(state); + xegpu::removeLayoutAttrs(newOp); newResults.push_back(newOp->getResult(0)); } @@ -748,24 +746,17 @@ struct WgToSgArithConstantOp : public OpConversionPattern { Location loc = op.getLoc(); auto eltType = vecType.getElementType(); - auto setLayout = [&](Value val) { - xegpu::setTemporaryLayout(llvm::dyn_cast(val), - layout.dropSgLayoutAndData()); - }; - if (vecAttr.isSplat()) { // Splat: single value for all subgroups Attribute singleVal = vecAttr.getSplatValue(); auto sgAttr = DenseElementsAttr::get(newType, singleVal); auto cstOp = arith::ConstantOp::create(rewriter, loc, newType, sgAttr); - setLayout(cstOp->getResult(0)); rewriter.replaceOp(op, cstOp); return success(); } else if (sgShape == wgShape) { // if the entire vector is shared by all // subgroups, don't distribute auto newConstOp = arith::ConstantOp::create(rewriter, op.getLoc(), vecType, vecAttr); - setLayout(newConstOp->getResult(0)); rewriter.replaceOp(op, newConstOp); return success(); } else { @@ -867,9 +858,6 @@ struct WgToSgArithConstantOp : public OpConversionPattern { rewriter, loc, baseConstVec.getType(), mulOffset); auto finalConst = arith::AddIOp::create(rewriter, loc, baseConstVec, bcastOffset); - setLayout(baseConstVec); - setLayout(bcastOffset); - setLayout(finalConst); newConstOps.push_back(finalConst); } rewriter.replaceOpWithMultiple(op, {newConstOps}); @@ -925,7 +913,6 @@ struct WgToSgLoadGatherOpWithOffset rewriter, loc, newTy, op.getSource(), offsets, mask, chunkSizeAttr, op.getL1HintAttr(), op.getL2HintAttr(), op.getL3HintAttr(), newLayout); - newLoadOp.setAnchorLayout(newLayout); newLoadOps.push_back(newLoadOp); } rewriter.replaceOpWithMultiple(op, {newLoadOps}); @@ -971,17 +958,10 @@ struct WgToSgStoreScatterOpWithOffset auto chunkSizeAttr = rewriter.getI64IntegerAttr(chunkSize); for (auto [val, offs, mask] : llvm::zip( adaptor.getValue(), adaptor.getOffsets(), adaptor.getMask())) { - auto store = xegpu::StoreScatterOp::create( - rewriter, loc, val, op.getDest(), offs, mask, chunkSizeAttr, - op.getL1HintAttr(), op.getL2HintAttr(), op.getL3HintAttr(), - layout.dropSgLayoutAndData()); - // Update the layout attribute to drop sg_layout and sg_data. - for (OpOperand &operand : store->getOpOperands()) { - // Skip for operand one (memref) - if (operand.getOperandNumber() == 1) - continue; - xegpu::setTemporaryLayout(operand, layout.dropSgLayoutAndData()); - } + xegpu::StoreScatterOp::create(rewriter, loc, val, op.getDest(), offs, + mask, chunkSizeAttr, op.getL1HintAttr(), + op.getL2HintAttr(), op.getL3HintAttr(), + layout.dropSgLayoutAndData()); } rewriter.eraseOp(op); return success(); @@ -1073,12 +1053,6 @@ struct WgToSgVectorStepOp : public OpConversionPattern { vector::BroadcastOp::create(rewriter, loc, newTy, offsets[0]); auto finalSteps = arith::AddIOp::create(rewriter, loc, steps, bcastOffset); - xegpu::setTemporaryLayout(steps->getResult(0), - layout.dropSgLayoutAndData()); - xegpu::setTemporaryLayout(bcastOffset->getResult(0), - layout.dropSgLayoutAndData()); - xegpu::setTemporaryLayout(finalSteps->getResult(0), - layout.dropSgLayoutAndData()); newOps.push_back(finalSteps); } @@ -1113,27 +1087,10 @@ struct WgToSgVectorShapeCastOp return failure(); ArrayRef srcShape = srcType.getShape(); - llvm::SetVector expandedUnitDims; - - // Check if shapes only differ by expanding unit dimensions (like - // expand_dims) - auto checkOnlyExpandUnitDims = [&](ArrayRef src, - ArrayRef dst) -> bool { - // All unit dimensions in dst that don't appear in src are the expanded - // unit dimensions - size_t srcIdx = 0; - for (size_t dstIdx = 0; dstIdx < dst.size(); ++dstIdx) - if (srcIdx < src.size() && src[srcIdx] == dst[dstIdx]) - srcIdx++; - else if (dst[dstIdx] == 1) - expandedUnitDims.insert(dstIdx); - else - return false; - return srcIdx == src.size(); - }; - xegpu::DistributeLayoutAttr layoutToDistribute = layout; - if (checkOnlyExpandUnitDims(srcShape, wgShape)) { + xegpu::DistributeLayoutAttr layoutToDistribute = layout; + SmallVector expandedUnitDims; + if (xegpu::matchUnitDimExpansion(srcShape, wgShape, expandedUnitDims)) { xegpu::DistributeLayoutAttr sourceLayout = xegpu::getTemporaryLayout(op->getOpOperand(0)); @@ -1166,8 +1123,6 @@ struct WgToSgVectorShapeCastOp for (auto src : adaptor.getSource()) { auto newShapeCast = vector::ShapeCastOp::create(rewriter, op.getLoc(), newResultType, src); - xegpu::setTemporaryLayout(newShapeCast->getResult(0), - layout.dropSgLayoutAndData()); newShapeCastOps.push_back(newShapeCast.getResult()); } @@ -1402,9 +1357,6 @@ struct WgToSgMultiDimReductionOp for (auto localResult : localReductions) { auto finalResult = vector::makeArithReduction( rewriter, loc, op.getKind(), localResult, adaptor.getAcc()[0]); - if (auto defOp = finalResult.getDefiningOp()) - xegpu::setDistributeLayoutAttr(defOp->getResult(0), - layout.dropSgLayoutAndData()); results.push_back(finalResult); } rewriter.replaceOpWithMultiple(op, {results}); @@ -1488,15 +1440,8 @@ struct WgToSgMultiDimReductionOp SmallVector storeOffsets2D = {rowOffsetStore, colOffset}; - auto storeMatrixLayout = xegpu::SliceAttr::get( - rewriter.getContext(), - xegpu::LayoutAttr::get(rewriter.getContext(), /*sg_layout =*/nullptr, - /*sg_data =*/nullptr, - /*inst_data =*/nullptr, /*lane_layout =*/nullptr, - /*lane_data =*/nullptr, /*order =*/nullptr), - dyn_cast(layout).getDims()); xegpu::StoreMatrixOp::create(rewriter, loc, storeData, memDesc.getResult(), - storeOffsets2D, /*layout=*/storeMatrixLayout); + storeOffsets2D, /*layout=*/nullptr); gpu::BarrierOp::create(rewriter, loc); @@ -1548,10 +1493,6 @@ struct WgToSgMultiDimReductionOp auto finalResult = vector::makeArithReduction( rewriter, loc, op.getKind(), finalReduce.getResult(), accToAdd); - if (auto defOp = finalResult.getDefiningOp()) - xegpu::setDistributeLayoutAttr(defOp->getResult(0), - layout.dropSgLayoutAndData()); - rewriter.replaceOp(op, finalResult); return success(); } @@ -1611,8 +1552,6 @@ struct WgToSgVectorTransposeOp for (auto src : adaptor.getVector()) { auto newTranspose = vector::TransposeOp::create( rewriter, op.getLoc(), newResultType, src, permutation); - xegpu::setTemporaryLayout(newTranspose->getResult(0), - layout.dropSgLayoutAndData()); newTransposeOps.push_back(newTranspose.getResult()); } @@ -1681,8 +1620,6 @@ struct WgToSgVectorMaskOp : public OpConversionPattern { auto newCreateMaskOp = vector::CreateMaskOp::create(rewriter, loc, resultType, maskOperands); - xegpu::setTemporaryLayout(newCreateMaskOp->getResult(0), - layout.dropSgLayoutAndData()); newCreateMaskOps.push_back(newCreateMaskOp.getResult()); } @@ -1723,12 +1660,11 @@ struct XeGPUWgToSgDistributePass void XeGPUWgToSgDistributePass::runOnOperation() { - // TODO-LayoutRefactor: unify the local propagation for layout preprocessing - // Operation *op = getOperation(); - // if (!xegpu::recoverTemporaryLayouts(op)) { - // signalPassFailure(); - // return; - // } + Operation *op = getOperation(); + if (!xegpu::recoverTemporaryLayouts(op)) { + signalPassFailure(); + return; + } // Track existing UnrealizedConversionCastOps SmallVector existingCastOps; @@ -1911,22 +1847,4 @@ void XeGPUWgToSgDistributePass::runOnOperation() { if (failed( applyPartialConversion(getOperation(), target, std::move(patterns)))) return signalPassFailure(); - - // Remove sg_layout and sg_data attributes from the Layout - // attribute for each VectorType result of the operation. - // For Structured Control Flow ops, the layout is simply removed, - // since in 1:N case, the layout for new results are missing. - // Layout propagation pass will activated. - getOperation()->walk([](Operation *op) { - for (OpResult result : op->getOpResults()) { - std::string name = xegpu::getTemporaryLayoutName(result); - if (auto layout = op->getAttrOfType(name)) { - op->removeAttr(name); - if (!isa(op)) { - if (auto newLayout = layout.dropSgLayoutAndData()) - op->setAttr(name, newLayout); - } - } - } - }); } diff --git a/mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp b/mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp index 7e28c756f2d72..c47fd92fe46d7 100644 --- a/mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp +++ b/mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp @@ -366,111 +366,6 @@ template void xegpu::setTemporaryLayout( const mlir::OpOperand &operand, const mlir::xegpu::DistributeLayoutAttr layout); -void xegpu::recoverTemporaryLayoutsDeprecated(Operation *op) { - op->walk([&](Operation *nestOp) { - for (OpOperand &opr : nestOp->getOpOperands()) { - auto layout = getDistributeLayoutAttr(opr.get()); - setDistributeLayoutAttr(opr, layout); - } - - for (OpResult result : nestOp->getOpResults()) { - auto layout = getDistributeLayoutAttr(result); - setDistributeLayoutAttr(result, layout); - } - }); -} - -/// Attach layout attributes to all vector-type operands of operations within -/// the given operation's region. Reports an error if any vector operand lacks -/// a layout attribute. -bool xegpu::recoverTemporaryLayouts(Operation *rootOp) { - auto result = rootOp->walk([&](Operation *op) { - for (OpOperand &operand : op->getOpOperands()) { - // Layouts are needed for vector type only. - if (!isa(operand.get().getType())) - continue; - auto layout = xegpu::getDistributeLayoutAttr(operand.get()); - if (!layout) { - op->emitWarning("Could not find layout attribute for operand ") - << operand.getOperandNumber() << " of operation " << op->getName(); - continue; - } - xegpu::setDistributeLayoutAttr(operand, layout); - } - return WalkResult::advance(); - }); - return !result.wasInterrupted(); -} - -template -void xegpu::removeLayoutAttr(const T &operandOrResult) { - Operation *owner = operandOrResult.getOwner(); - std::string name = xegpu::getTemporaryLayoutName(operandOrResult); - if (owner->hasAttrOfType(name)) - owner->removeAttr(name); -} - -SmallVector -xegpu::dropSgLayoutAndDataOnAttrs(ArrayRef attrs) { - SmallVector out; - out.reserve(attrs.size()); - - for (auto attr : attrs) { - if (auto dist = dyn_cast(attr.getValue())) { - auto newLayout = dist.dropSgLayoutAndData(); - if (newLayout) - out.emplace_back(attr.getName(), newLayout); - } else { - out.push_back(attr); - } - } - - return out; -} - -SmallVector -xegpu::dropInstDataOnAttrs(ArrayRef attrs) { - SmallVector out; - out.reserve(attrs.size()); - - for (auto attr : attrs) { - if (auto dist = dyn_cast(attr.getValue())) { - auto newLayout = dist.dropInstData(); - if (newLayout) - out.emplace_back(attr.getName(), newLayout); - } else { - out.push_back(attr); - } - } - - return out; -} - -// Explicit instantiation for OpResult -template void -xegpu::removeLayoutAttr(const mlir::OpResult &result); - -// Explicit instantiation for OpOperand -template void -xegpu::removeLayoutAttr(const mlir::OpOperand &operand); - -void xegpu::removeLayoutAttrs(Operation *op) { - op->walk([&](Operation *nestOp) { - for (OpOperand &opr : nestOp->getOpOperands()) - removeLayoutAttr(opr); - for (OpResult result : nestOp->getOpResults()) - removeLayoutAttr(result); - if (op->hasAttrOfType("layout")) - op->removeAttr("layout"); - if (op->hasAttrOfType("layout_a")) - op->removeAttr("layout_a"); - if (op->hasAttrOfType("layout_b")) - op->removeAttr("layout_b"); - if (op->hasAttrOfType("layout_cd")) - op->removeAttr("layout_cd"); - }); -} - SmallVector xegpu::extractVectorsWithShapeFromValue(OpBuilder &builder, Location loc, Value value, ArrayRef shape) { @@ -786,3 +681,58 @@ bool xegpu::requireTranspose(const xegpu::LayoutAttr layout, return false; return laneLayout[0] == uArch->getSubgroupSize() && laneLayout[1] == 1; } + +// Check if dst shape is an expansion of src shape by inserting unit dimensions. +// Returns true if all dimensions in src match corresponding dimensions in dst +// (after skipping unit dimensions), and populates expandedUnitDims with the +// indices of the unit dimensions in dst that were added (not present in src). +// Example: src=[2,3], dst=[1,2,3,1] -> true, expandedUnitDims=[0,3] +bool xegpu::matchUnitDimExpansion(ArrayRef src, ArrayRef dst, + SmallVector &expandedUnitDims) { + // All unit dimensions in dst that don't appear in src are the expanded + // unit dimensions + size_t srcIdx = 0; + for (size_t dstIdx = 0; dstIdx < dst.size(); ++dstIdx) + if (srcIdx < src.size() && src[srcIdx] == dst[dstIdx]) + srcIdx++; + else if (dst[dstIdx] == 1) + expandedUnitDims.push_back(dstIdx); + else + return false; + return srcIdx == src.size(); +} + +// Checks if dst shape is an expansion of src shape where each dimension in src +// is split into one or more consecutive dimensions in dst whose product equals +// the original dimension. Populates splitDimGroups with groups of dst indices +// that correspond to each src dimension. Example: src=[6,4], dst=[2,3,2,2] -> +// true +bool xegpu::matchSplitDimExpansion( + ArrayRef src, ArrayRef dst, + SmallVector> &splitDimGroups) { + // each dim in src can be mapped to one or more dims in dst whose product + // equals to the src dim + size_t srcIdx = 0; + int64_t accumulatedSize = 1; + SmallVector currentDstDims; + + splitDimGroups.clear(); + for (size_t dstIdx = 0; dstIdx < dst.size(); ++dstIdx) { + if (srcIdx >= src.size()) + return false; + accumulatedSize *= dst[dstIdx]; + currentDstDims.push_back(dstIdx); + + if (accumulatedSize == src[srcIdx]) { + // Record the mapping: srcIdx -> currentDstDims + splitDimGroups.push_back(currentDstDims); + // move to next src dim + srcIdx++; + accumulatedSize = 1; + currentDstDims.clear(); + } else if (accumulatedSize > src[srcIdx]) { + return false; + } + } + return srcIdx == src.size(); +} diff --git a/mlir/lib/IR/Builders.cpp b/mlir/lib/IR/Builders.cpp index 8f199b60fccdc..cf64954751d5e 100644 --- a/mlir/lib/IR/Builders.cpp +++ b/mlir/lib/IR/Builders.cpp @@ -34,6 +34,10 @@ Location Builder::getFusedLoc(ArrayRef locs, Attribute metadata) { FloatType Builder::getF8E8M0Type() { return Float8E8M0FNUType::get(context); } +FloatType Builder::getF8E4M3FNType() { return Float8E4M3FNType::get(context); } + +FloatType Builder::getF8E5M2Type() { return Float8E5M2Type::get(context); } + FloatType Builder::getBF16Type() { return BFloat16Type::get(context); } FloatType Builder::getF16Type() { return Float16Type::get(context); } diff --git a/mlir/lib/IR/SymbolTable.cpp b/mlir/lib/IR/SymbolTable.cpp index 9f5dd2c9e3b72..4e191e7d612ad 100644 --- a/mlir/lib/IR/SymbolTable.cpp +++ b/mlir/lib/IR/SymbolTable.cpp @@ -413,30 +413,24 @@ static LogicalResult lookupSymbolInImpl( assert(symbolTableOp->hasTrait()); // Lookup the root reference for this symbol. - symbolTableOp = lookupSymbolFn(symbolTableOp, symbol.getRootReference()); - if (!symbolTableOp) + auto *symbolOp = lookupSymbolFn(symbolTableOp, symbol.getRootReference()); + if (!symbolOp) return failure(); - symbols.push_back(symbolTableOp); + symbols.push_back(symbolOp); - // If there are no nested references, just return the root symbol directly. - ArrayRef nestedRefs = symbol.getNestedReferences(); - if (nestedRefs.empty()) - return success(); - - // Verify that the root is also a symbol table. - if (!symbolTableOp->hasTrait()) - return failure(); - - // Otherwise, lookup each of the nested non-leaf references and ensure that - // each corresponds to a valid symbol table. - for (FlatSymbolRefAttr ref : nestedRefs.drop_back()) { - symbolTableOp = lookupSymbolFn(symbolTableOp, ref.getAttr()); - if (!symbolTableOp || !symbolTableOp->hasTrait()) + // Lookup each of the nested references. + for (FlatSymbolRefAttr ref : symbol.getNestedReferences()) { + // Check that we have a valid symbol table to lookup ref. + if (!symbolOp->hasTrait()) + return failure(); + symbolOp = lookupSymbolFn(symbolOp, ref.getAttr()); + // If the nested symbol is private, lookup failed. + if (!symbolOp || SymbolTable::getSymbolVisibility(symbolOp) == + SymbolTable::Visibility::Private) return failure(); - symbols.push_back(symbolTableOp); + symbols.push_back(symbolOp); } - symbols.push_back(lookupSymbolFn(symbolTableOp, symbol.getLeafReference())); - return success(symbols.back()); + return success(); } LogicalResult diff --git a/mlir/lib/IR/Types.cpp b/mlir/lib/IR/Types.cpp index 765b787d3d17a..ec10a5ce9e2e7 100644 --- a/mlir/lib/IR/Types.cpp +++ b/mlir/lib/IR/Types.cpp @@ -41,6 +41,8 @@ bool Type::isF32() const { return llvm::isa(*this); } bool Type::isF64() const { return llvm::isa(*this); } bool Type::isF80() const { return llvm::isa(*this); } bool Type::isF128() const { return llvm::isa(*this); } +bool Type::isF8E4M3FN() const { return llvm::isa(*this); } +bool Type::isF8E5M2() const { return llvm::isa(*this); } bool Type::isFloat() const { return llvm::isa(*this); } diff --git a/mlir/lib/Interfaces/CMakeLists.txt b/mlir/lib/Interfaces/CMakeLists.txt index 7919d64b4cc47..ad3e2b61be418 100644 --- a/mlir/lib/Interfaces/CMakeLists.txt +++ b/mlir/lib/Interfaces/CMakeLists.txt @@ -6,7 +6,6 @@ set(LLVM_OPTIONAL_SOURCES DataLayoutInterfaces.cpp DerivedAttributeOpInterface.cpp DestinationStyleOpInterface.cpp - ExecutionProgressOpInterface.cpp FunctionImplementation.cpp FunctionInterfaces.cpp IndexingMapOpInterface.cpp @@ -50,7 +49,6 @@ add_mlir_interface_library(ControlFlowInterfaces) add_mlir_interface_library(DataLayoutInterfaces) add_mlir_interface_library(DerivedAttributeOpInterface) add_mlir_interface_library(DestinationStyleOpInterface) -add_mlir_interface_library(ExecutionProgressOpInterface) add_mlir_library(MLIRFunctionInterfaces FunctionInterfaces.cpp diff --git a/mlir/lib/Interfaces/ControlFlowInterfaces.cpp b/mlir/lib/Interfaces/ControlFlowInterfaces.cpp index 873685368d996..2f95531455b2b 100644 --- a/mlir/lib/Interfaces/ControlFlowInterfaces.cpp +++ b/mlir/lib/Interfaces/ControlFlowInterfaces.cpp @@ -577,49 +577,6 @@ Region *mlir::getEnclosingRepetitiveRegion(Value value) { return nullptr; } -/// Return "true" if the given region branch op is guaranteed to loop -/// infinitely. Every path starting from "parent" enters the region, but the -/// "parent" is not reachable from there. -bool mlir::isGuaranteedToLoopInfinitely(RegionBranchOpInterface op) { - llvm::SmallDenseSet visited; - - // Path starts with "parent". - SmallVector worklist; - worklist.push_back(RegionBranchPoint::parent()); - bool enteredRegion = false; - while (!worklist.empty()) { - RegionBranchPoint next = worklist.pop_back_val(); - SmallVector successors = - getSuccessorRegionsWithAttrs(op, next); - for (RegionSuccessor successor : successors) { - if (successor.isParent()) { - // Found path that ends with "parent". - return false; - } - enteredRegion = true; - Region *region = successor.getSuccessor(); - if (!visited.insert(region).second) { - // We have already visited this region. - continue; - } - for (Block &block : *region) { - auto terminator = - dyn_cast(block.back()); - if (!terminator) { - // Region has no RegionBranchTerminatorOpInterface terminator. E.g., - // the terminator could be a "ub.unreachable" op or a "cf.br" op. - continue; - } - worklist.push_back(RegionBranchPoint(terminator)); - } - } - } - // We visited all paths through the region branch op and the parent was not - // reached. If we visited at least one region, it means that we got stuck - // inside the region branch op, indicating an infinite loop. - return enteredRegion; -} - /// Return "true" if `a` can be used in lieu of `b`, where `b` is a region /// successor input and `a` is a "reachable value" of `b`. Reachable values /// are successor operand values that are (maybe transitively) forwarded to @@ -722,36 +679,6 @@ static llvm::SmallDenseSet computeReachableValuesFromSuccessorInput( return reachableValues; } -/// Given a range of values, return a vector of attributes of the same size, -/// where the i-th attribute is the constant value of the i-th value. If a -/// value is not constant, the corresponding attribute is null. -static SmallVector extractConstants(ValueRange values) { - return llvm::map_to_vector(values, [](Value value) { - Attribute attr; - matchPattern(value, m_Constant(&attr)); - return attr; - }); -} - -/// Return all successor regions when branching from the given region branch -/// point. This helper functions extracts all constant operand values and -/// passes them to the `RegionBranchOpInterface`. -SmallVector -mlir::getSuccessorRegionsWithAttrs(RegionBranchOpInterface op, - RegionBranchPoint point) { - SmallVector successors; - if (point.isParent()) { - op.getEntrySuccessorRegions(extractConstants(op->getOperands()), - successors); - return successors; - } - RegionBranchTerminatorOpInterface terminator = - point.getTerminatorPredecessorOrNull(); - terminator.getSuccessorRegions(extractConstants(terminator->getOperands()), - successors); - return successors; -} - namespace { /// Try to make successor inputs dead by replacing their uses with values that /// are not successor inputs. This pattern enables additional canonicalization @@ -1118,6 +1045,36 @@ struct RemoveDuplicateSuccessorInputUses : public RewritePattern { } }; +/// Given a range of values, return a vector of attributes of the same size, +/// where the i-th attribute is the constant value of the i-th value. If a +/// value is not constant, the corresponding attribute is null. +static SmallVector extractConstants(ValueRange values) { + return llvm::map_to_vector(values, [](Value value) { + Attribute attr; + matchPattern(value, m_Constant(&attr)); + return attr; + }); +} + +/// Return all successor regions when branching from the given region branch +/// point. This helper functions extracts all constant operand values and +/// passes them to the `RegionBranchOpInterface`. +static SmallVector +getSuccessorRegionsWithAttrs(RegionBranchOpInterface op, + RegionBranchPoint point) { + SmallVector successors; + if (point.isParent()) { + op.getEntrySuccessorRegions(extractConstants(op->getOperands()), + successors); + return successors; + } + RegionBranchTerminatorOpInterface terminator = + point.getTerminatorPredecessorOrNull(); + terminator.getSuccessorRegions(extractConstants(terminator->getOperands()), + successors); + return successors; +} + /// Find the single acyclic path through the given region branch op. Return an /// empty vector if no such path or multiple such paths exist. /// diff --git a/mlir/lib/Interfaces/ExecutionProgressOpInterface.cpp b/mlir/lib/Interfaces/ExecutionProgressOpInterface.cpp deleted file mode 100644 index b19e8539612ef..0000000000000 --- a/mlir/lib/Interfaces/ExecutionProgressOpInterface.cpp +++ /dev/null @@ -1,23 +0,0 @@ -//===- ExecutionProgressOpInterface.cpp -- Execution Progress Interface ---===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Interfaces/ExecutionProgressOpInterface.h" - -using namespace mlir; - -namespace mlir { -#include "mlir/Interfaces/ExecutionProgressOpInterface.cpp.inc" -} // namespace mlir - -bool mlir::mustProgress(Operation *op) { - auto executionProgressOpInterface = - dyn_cast(op); - if (!executionProgressOpInterface) - return false; - return executionProgressOpInterface.mustProgress(); -} diff --git a/mlir/lib/RegisterAllExtensions.cpp b/mlir/lib/RegisterAllExtensions.cpp index d5693db23225a..14cfb7b5ac352 100644 --- a/mlir/lib/RegisterAllExtensions.cpp +++ b/mlir/lib/RegisterAllExtensions.cpp @@ -32,7 +32,6 @@ #include "mlir/Conversion/SCFToEmitC/SCFToEmitC.h" #include "mlir/Conversion/UBToLLVM/UBToLLVM.h" #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" -#include "mlir/Conversion/XeVMToLLVM/XeVMToLLVM.h" #include "mlir/Dialect/AMX/Transforms.h" #include "mlir/Dialect/Affine/TransformOps/AffineTransformOps.h" #include "mlir/Dialect/ArmNeon/TransformOps/ArmNeonVectorTransformOps.h" @@ -95,7 +94,6 @@ void mlir::registerAllExtensions(DialectRegistry ®istry) { gpu::registerConvertGpuToLLVMInterface(registry); NVVM::registerConvertGpuToNVVMInterface(registry); vector::registerConvertVectorToLLVMInterface(registry); - registerConvertXeVMToLLVMInterface(registry); // Register all transform dialect extensions. affine::registerTransformDialectExtension(registry); diff --git a/mlir/lib/Rewrite/ByteCode.cpp b/mlir/lib/Rewrite/ByteCode.cpp index ede7d8a4006fc..cf00216288115 100644 --- a/mlir/lib/Rewrite/ByteCode.cpp +++ b/mlir/lib/Rewrite/ByteCode.cpp @@ -1741,6 +1741,36 @@ void ByteCodeExecutor::executeForEach() { selectJump(size_t(0)); return; } + case PDLValue::Kind::Value: { + unsigned &index = loopIndex[read()]; + ValueRange range = valueRangeMemory[rangeIndex]; + assert(index <= range.size() && "iterated past the end"); + if (index < range.size()) { + LLVM_DEBUG(llvm::dbgs() << " * Result: " << range[index] << "\n"); + value = range[index].getAsOpaquePointer(); + break; + } + + LLVM_DEBUG(llvm::dbgs() << " * Done\n"); + index = 0; + selectJump(size_t(0)); + return; + } + case PDLValue::Kind::Type: { + unsigned &index = loopIndex[read()]; + TypeRange range = typeRangeMemory[rangeIndex]; + assert(index <= range.size() && "iterated past the end"); + if (index < range.size()) { + LLVM_DEBUG(llvm::dbgs() << " * Result: " << range[index] << "\n"); + value = range[index].getAsOpaquePointer(); + break; + } + + LLVM_DEBUG(llvm::dbgs() << " * Done\n"); + index = 0; + selectJump(size_t(0)); + return; + } default: llvm_unreachable("unexpected `ForEach` value kind"); } diff --git a/mlir/lib/TableGen/AttrOrTypeDef.cpp b/mlir/lib/TableGen/AttrOrTypeDef.cpp index 4659265e24bda..bf835a860cd5b 100644 --- a/mlir/lib/TableGen/AttrOrTypeDef.cpp +++ b/mlir/lib/TableGen/AttrOrTypeDef.cpp @@ -190,9 +190,11 @@ bool AttrOrTypeDef::genVerifyDecl() const { } bool AttrOrTypeDef::genVerifyInvariantsImpl() const { - return any_of(parameters, [](const AttrOrTypeParameter &p) { - return p.getConstraint() != std::nullopt; - }); + return any_of(parameters, + [](const AttrOrTypeParameter &p) { + return p.getConstraint() != std::nullopt; + }) || + any_of(traits, [](const Trait &t) { return isa(&t); }); } std::optional AttrOrTypeDef::getExtraDecls() const { diff --git a/mlir/lib/Target/LLVM/ROCDL/Target.cpp b/mlir/lib/Target/LLVM/ROCDL/Target.cpp index 60962efca8290..e3b34c5d34c41 100644 --- a/mlir/lib/Target/LLVM/ROCDL/Target.cpp +++ b/mlir/lib/Target/LLVM/ROCDL/Target.cpp @@ -336,7 +336,7 @@ mlir::ROCDL::assembleIsa(StringRef isa, StringRef targetTriple, StringRef chip, } FailureOr> -mlir::ROCDL::linkObjectCode(ArrayRef objectCode, StringRef toolkitPath, +mlir::ROCDL::linkObjectCode(ArrayRef objectCode, StringRef lldPath, function_ref emitError) { // Save the ISA binary to a temp file. int tempIsaBinaryFd = -1; @@ -361,8 +361,6 @@ mlir::ROCDL::linkObjectCode(ArrayRef objectCode, StringRef toolkitPath, llvm::FileRemover cleanupHsaco(tempHsacoFilename); - llvm::SmallString<128> lldPath(toolkitPath); - llvm::sys::path::append(lldPath, "llvm", "bin", "ld.lld"); int lldResult = llvm::sys::ExecuteAndWait( lldPath, {"ld.lld", "-shared", tempIsaBinaryFilename, "-o", tempHsacoFilename}); @@ -392,8 +390,10 @@ SerializeGPUModuleBase::compileToBinary(StringRef serializedISA) { return failure(); // Link the object code. + llvm::SmallString<128> lldPath(toolkitPath); + llvm::sys::path::append(lldPath, "llvm", "bin", "ld.lld"); FailureOr> linkedCode = - ROCDL::linkObjectCode(*isaBinary, toolkitPath, errCallback); + ROCDL::linkObjectCode(*isaBinary, lldPath, errCallback); if (failed(linkedCode)) return failure(); diff --git a/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp index e32719f10d7c1..36cbcd370364f 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp @@ -423,6 +423,15 @@ convertOperationImpl(Operation &opInst, llvm::IRBuilderBase &builder, call->addFnAttr(llvm::Attribute::WillReturn); if (callOp.getNoreturnAttr()) call->addFnAttr(llvm::Attribute::NoReturn); + if (callOp.getOptsizeAttr()) + call->addFnAttr(llvm::Attribute::OptimizeForSize); + if (callOp.getMinsizeAttr()) + call->addFnAttr(llvm::Attribute::MinSize); + if (callOp.getSaveRegParamsAttr()) + call->addFnAttr(llvm::Attribute::get(moduleTranslation.getLLVMContext(), + "save-reg-params")); + if (callOp.getNobuiltinAttr()) + call->addFnAttr(llvm::Attribute::NoBuiltin); if (callOp.getReturnsTwiceAttr()) call->addFnAttr(llvm::Attribute::ReturnsTwice); if (callOp.getColdAttr()) @@ -446,6 +455,32 @@ convertOperationImpl(Operation &opInst, llvm::IRBuilderBase &builder, call->addFnAttr(llvm::Attribute::get(moduleTranslation.getLLVMContext(), "modular-format", modFormat.getValue())); + if (StringAttr zcsr = callOp.getZeroCallUsedRegsAttr()) + call->addFnAttr(llvm::Attribute::get(moduleTranslation.getLLVMContext(), + "zero-call-used-regs", + zcsr.getValue())); + if (StringAttr trapFunc = callOp.getTrapFuncNameAttr()) + call->addFnAttr(llvm::Attribute::get(moduleTranslation.getLLVMContext(), + "trap-func-name", + trapFunc.getValue())); + + if (ArrayAttr noBuiltins = callOp.getNobuiltinsAttr()) { + if (noBuiltins.empty()) + call->addFnAttr(llvm::Attribute::get(moduleTranslation.getLLVMContext(), + "no-builtins")); + + moduleTranslation.convertFunctionAttrCollection( + noBuiltins, call, ModuleTranslation::convertNoBuiltin); + } + + moduleTranslation.convertFunctionAttrCollection( + callOp.getDefaultFuncAttrsAttr(), call, + ModuleTranslation::convertDefaultFuncAttr); + + if (llvm::Attribute attr = + moduleTranslation.convertAllocsizeAttr(callOp.getAllocsizeAttr()); + attr.isValid()) + call->addFnAttr(attr); if (failed(moduleTranslation.convertArgAndResultAttrs(callOp, call))) return failure(); diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp index f04d614633965..4844cc99b5c38 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp @@ -321,6 +321,10 @@ static LogicalResult checkImplementationStatus(Operation &op) { << " operation"; }; + auto checkAffinity = [&todo](auto op, LogicalResult &result) { + if (!op.getAffinityVars().empty()) + result = todo("affinity"); + }; auto checkAllocate = [&todo](auto op, LogicalResult &result) { if (!op.getAllocateVars().empty() || !op.getAllocatorVars().empty()) result = todo("allocate"); @@ -329,10 +333,6 @@ static LogicalResult checkImplementationStatus(Operation &op) { if (op.getBare()) result = todo("ompx_bare"); }; - auto checkCollapse = [&todo](auto op, LogicalResult &result) { - if (op.getCollapseNumLoops() > 1) - result = todo("collapse"); - }; auto checkDepend = [&todo](auto op, LogicalResult &result) { if (!op.getDependVars().empty() || op.getDependKinds()) result = todo("depend"); @@ -396,10 +396,6 @@ static LogicalResult checkImplementationStatus(Operation &op) { checkAllocate(op, result); checkOrder(op, result); }) - .Case([&](omp::LoopNestOp op) { - if (mlir::isa(op.getOperation()->getParentOp())) - checkCollapse(op, result); - }) .Case([&](omp::OrderedRegionOp op) { checkParLevelSimd(op, result); }) .Case([&](omp::SectionsOp op) { checkAllocate(op, result); @@ -417,6 +413,7 @@ static LogicalResult checkImplementationStatus(Operation &op) { checkThreadLimit(op, result); }) .Case([&](omp::TaskOp op) { + checkAffinity(op, result); checkAllocate(op, result); checkInReduction(op, result); }) @@ -2800,6 +2797,84 @@ convertOmpTaskloopOp(Operation &opInst, llvm::IRBuilderBase &builder, return loopInfo; }; + Operation::operand_range lowerBounds = loopOp.getLoopLowerBounds(); + Operation::operand_range upperBounds = loopOp.getLoopUpperBounds(); + Operation::operand_range steps = loopOp.getLoopSteps(); + llvm::Type *boundType = + moduleTranslation.lookupValue(lowerBounds[0])->getType(); + llvm::Value *lbVal = nullptr; + llvm::Value *ubVal = builder.getIntN(boundType->getIntegerBitWidth(), 1); + llvm::Value *stepVal = nullptr; + if (loopOp.getCollapseNumLoops() > 1) { + // In cases where Collapse is used with Taskloop, the upper bound of the + // iteration space needs to be recalculated to cater for the collapsed loop. + // The Collapsed Loop UpperBound is the product of all collapsed + // loop's tripcount. + // The LowerBound for collapsed loops is always 1. When the loops are + // collapsed, it will reset the bounds and introduce processing to ensure + // the index's are presented as expected. As this happens after creating + // Taskloop, these bounds need predicting. Example: + // !$omp taskloop collapse(2) + // do i = 1, 10 + // do j = 1, 5 + // .. + // end do + // end do + // This loop above has a total of 50 iterations, so the lb will be 1, and + // the ub will be 50. collapseLoops in OMPIRBuilder then handles ensuring + // that i and j are properly presented when used in the loop. + for (uint64_t i = 0; i < loopOp.getCollapseNumLoops(); i++) { + llvm::Value *loopLb = moduleTranslation.lookupValue(lowerBounds[i]); + llvm::Value *loopUb = moduleTranslation.lookupValue(upperBounds[i]); + llvm::Value *loopStep = moduleTranslation.lookupValue(steps[i]); + // In some cases, such as where the ub is less than the lb so the loop + // steps down, the calculation for the loopTripCount is swapped. To ensure + // the correct value is found, calculate both UB - LB and LB - UB then + // select which value to use depending on how the loop has been + // configured. + llvm::Value *loopLbMinusOne = builder.CreateSub( + loopLb, builder.getIntN(boundType->getIntegerBitWidth(), 1)); + llvm::Value *loopUbMinusOne = builder.CreateSub( + loopUb, builder.getIntN(boundType->getIntegerBitWidth(), 1)); + llvm::Value *boundsCmp = builder.CreateICmpSLT(loopLb, loopUb); + llvm::Value *ubMinusLb = builder.CreateSub(loopUb, loopLbMinusOne); + llvm::Value *lbMinusUb = builder.CreateSub(loopLb, loopUbMinusOne); + llvm::Value *loopTripCount = + builder.CreateSelect(boundsCmp, ubMinusLb, lbMinusUb); + loopTripCount = builder.CreateBinaryIntrinsic( + llvm::Intrinsic::abs, loopTripCount, builder.getFalse()); + // For loops that have a step value not equal to 1, we need to adjust the + // trip count to ensure the correct number of iterations for the loop is + // captured. + llvm::Value *loopTripCountDivStep = + builder.CreateSDiv(loopTripCount, loopStep); + loopTripCountDivStep = builder.CreateBinaryIntrinsic( + llvm::Intrinsic::abs, loopTripCountDivStep, builder.getFalse()); + llvm::Value *loopTripCountRem = + builder.CreateSRem(loopTripCount, loopStep); + loopTripCountRem = builder.CreateBinaryIntrinsic( + llvm::Intrinsic::abs, loopTripCountRem, builder.getFalse()); + llvm::Value *needsRoundUp = builder.CreateICmpNE( + loopTripCountRem, + builder.getIntN(loopTripCountRem->getType()->getIntegerBitWidth(), + 0)); + loopTripCount = + builder.CreateAdd(loopTripCountDivStep, + builder.CreateZExtOrTrunc( + needsRoundUp, loopTripCountDivStep->getType())); + ubVal = builder.CreateMul(ubVal, loopTripCount); + } + lbVal = builder.getIntN(boundType->getIntegerBitWidth(), 1); + stepVal = builder.getIntN(boundType->getIntegerBitWidth(), 1); + } else { + lbVal = moduleTranslation.lookupValue(lowerBounds[0]); + ubVal = moduleTranslation.lookupValue(upperBounds[0]); + stepVal = moduleTranslation.lookupValue(steps[0]); + } + assert(lbVal != nullptr && "Expected value for lbVal"); + assert(ubVal != nullptr && "Expected value for ubVal"); + assert(stepVal != nullptr && "Expected value for stepVal"); + llvm::Value *ifCond = nullptr; llvm::Value *grainsize = nullptr; int sched = 0; // default @@ -2832,15 +2907,13 @@ convertOmpTaskloopOp(Operation &opInst, llvm::IRBuilderBase &builder, llvm::OpenMPIRBuilder::LocationDescription ompLoc(builder); llvm::OpenMPIRBuilder::InsertPointOrErrorTy afterIP = moduleTranslation.getOpenMPBuilder()->createTaskloop( - ompLoc, allocaIP, bodyCB, loopInfo, - moduleTranslation.lookupValue(loopOp.getLoopLowerBounds()[0]), - moduleTranslation.lookupValue(loopOp.getLoopUpperBounds()[0]), - moduleTranslation.lookupValue(loopOp.getLoopSteps()[0]), + ompLoc, allocaIP, bodyCB, loopInfo, lbVal, ubVal, stepVal, taskloopOp.getUntied(), ifCond, grainsize, taskloopOp.getNogroup(), sched, moduleTranslation.lookupValue(taskloopOp.getFinal()), taskloopOp.getMergeable(), moduleTranslation.lookupValue(taskloopOp.getPriority()), - taskDupOrNull, taskStructMgr.getStructPtr()); + loopOp.getCollapseNumLoops(), taskDupOrNull, + taskStructMgr.getStructPtr()); if (failed(handleError(afterIP, opInst))) return failure(); diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp index deaeb98d9abdc..8f3c2759d6f64 100644 --- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp @@ -1419,10 +1419,10 @@ LogicalResult ModuleImport::convertIFunc(llvm::GlobalIFunc *ifunc) { /// Converts LLVM string, integer, and enum attributes into MLIR attributes, /// skipping those in `attributesToSkip` and emitting a warning at `loc` for /// any other unsupported attributes. -static ArrayAttr -convertLLVMAttributesToMLIR(Location loc, MLIRContext *context, - llvm::AttributeSet attributes, - ArrayRef attributesToSkip = {}) { +static ArrayAttr convertLLVMAttributesToMLIR( + Location loc, MLIRContext *context, llvm::AttributeSet attributes, + ArrayRef attributesToSkip = {}, + ArrayRef attributePrefixesToSkip = {}) { SmallVector mlirAttributes; for (llvm::Attribute attr : attributes) { StringRef attrName; @@ -1433,6 +1433,13 @@ convertLLVMAttributesToMLIR(Location loc, MLIRContext *context, if (llvm::is_contained(attributesToSkip, attrName)) continue; + auto attrNameStartsWith = [attrName](StringLiteral sl) { + return attrName.starts_with(sl); + }; + if (attributePrefixesToSkip.end() != + llvm::find_if(attributePrefixesToSkip, attrNameStartsWith)) + continue; + auto keyAttr = StringAttr::get(context, attrName); if (attr.isStringAttribute()) { StringRef val = attr.getValueAsString(); @@ -2641,6 +2648,23 @@ static void processMemoryEffects(llvm::Function *func, LLVMFuncOp funcOp) { funcOp.setMemoryEffectsAttr(memAttr); } +static void processDenormalFPEnv(llvm::Function *func, LLVMFuncOp funcOp) { + llvm::DenormalFPEnv denormalFpEnv = func->getDenormalFPEnv(); + // Only set the attr when it does not match the default value. + if (denormalFpEnv == llvm::DenormalFPEnv::getDefault()) + return; + + llvm::DenormalMode defaultMode = denormalFpEnv.DefaultMode; + llvm::DenormalMode floatMode = denormalFpEnv.F32Mode; + + auto denormalFpEnvAttr = DenormalFPEnvAttr::get( + funcOp.getContext(), convertDenormalModeKindFromLLVM(defaultMode.Output), + convertDenormalModeKindFromLLVM(defaultMode.Input), + convertDenormalModeKindFromLLVM(floatMode.Output), + convertDenormalModeKindFromLLVM(floatMode.Input)); + funcOp.setDenormalFpenvAttr(denormalFpEnvAttr); +} + // List of LLVM IR attributes that map to an explicit attribute on the MLIR // LLVMFuncOp. static constexpr std::array kExplicitLLVMFuncOpAttributes{ @@ -2652,11 +2676,10 @@ static constexpr std::array kExplicitLLVMFuncOpAttributes{ StringLiteral("aarch64_pstate_sm_body"), StringLiteral("aarch64_pstate_sm_compatible"), StringLiteral("aarch64_pstate_sm_enabled"), + StringLiteral("allocsize"), StringLiteral("alwaysinline"), StringLiteral("cold"), StringLiteral("convergent"), - StringLiteral("denormal-fp-math"), - StringLiteral("denormal-fp-math-f32"), StringLiteral("fp-contract"), StringLiteral("frame-pointer"), StringLiteral("hot"), @@ -2665,33 +2688,91 @@ static constexpr std::array kExplicitLLVMFuncOpAttributes{ StringLiteral("instrument-function-exit"), StringLiteral("modular-format"), StringLiteral("memory"), + StringLiteral("minsize"), StringLiteral("no_caller_saved_registers"), - StringLiteral("no-infs-fp-math"), StringLiteral("no-nans-fp-math"), StringLiteral("no-signed-zeros-fp-math"), + StringLiteral("no-builtins"), StringLiteral("nocallback"), StringLiteral("noduplicate"), StringLiteral("noinline"), StringLiteral("noreturn"), StringLiteral("nounwind"), StringLiteral("optnone"), + StringLiteral("optsize"), StringLiteral("returns_twice"), + StringLiteral("save-reg-params"), StringLiteral("target-features"), + StringLiteral("trap-func-name"), StringLiteral("tune-cpu"), StringLiteral("uwtable"), StringLiteral("vscale_range"), StringLiteral("willreturn"), + StringLiteral("zero-call-used-regs"), + StringLiteral("denormal_fpenv"), +}; + +// List of LLVM IR attributes that are handled by prefix to map onto an MLIR +// LLVMFuncOp. +static constexpr std::array kExplicitLLVMFuncOpAttributePrefixes{ + StringLiteral("no-builtin-"), }; +template +static void convertNoBuiltinAttrs(MLIRContext *ctx, + const llvm::AttributeSet &attrs, + OpTy target) { + // 'no-builtins' is the complete collection, and overrides all the rest. + if (attrs.hasAttribute("no-builtins")) { + target.setNobuiltinsAttr(ArrayAttr::get(ctx, {})); + return; + } + + llvm::SetVector nbAttrs; + for (llvm::Attribute attr : attrs) { + // Attributes that are part of llvm directly (that is, have an AttributeKind + // in the enum) shouldn't be checked. + if (attr.hasKindAsEnum()) + continue; + + StringRef val = attr.getKindAsString(); + + if (val.starts_with("no-builtin-")) + nbAttrs.insert( + StringAttr::get(ctx, val.drop_front(sizeof("no-builtin-") - 1))); + } + + if (!nbAttrs.empty()) + target.setNobuiltinsAttr(ArrayAttr::get(ctx, nbAttrs.getArrayRef())); +} + +template +static void convertAllocsizeAttr(MLIRContext *ctx, + const llvm::AttributeSet &attrs, OpTy target) { + llvm::Attribute attr = attrs.getAttribute(llvm::Attribute::AllocSize); + if (!attr.isValid()) + return; + + auto [elemSize, numElems] = attr.getAllocSizeArgs(); + if (numElems) { + target.setAllocsizeAttr( + DenseI32ArrayAttr::get(ctx, {static_cast(elemSize), + static_cast(*numElems)})); + } else { + target.setAllocsizeAttr( + DenseI32ArrayAttr::get(ctx, {static_cast(elemSize)})); + } +} + /// Converts LLVM attributes from `func` into MLIR attributes and adds them /// to `funcOp` as passthrough attributes, skipping those listed in /// `kExplicitLLVMFuncAttributes`. static void processPassthroughAttrs(llvm::Function *func, LLVMFuncOp funcOp) { llvm::AttributeSet funcAttrs = func->getAttributes().getAttributes( llvm::AttributeList::AttrIndex::FunctionIndex); - ArrayAttr passthroughAttr = - convertLLVMAttributesToMLIR(funcOp.getLoc(), funcOp.getContext(), - funcAttrs, kExplicitLLVMFuncOpAttributes); + ArrayAttr passthroughAttr = convertLLVMAttributesToMLIR( + funcOp.getLoc(), funcOp.getContext(), funcAttrs, + kExplicitLLVMFuncOpAttributes, kExplicitLLVMFuncOpAttributePrefixes); if (!passthroughAttr.empty()) funcOp.setPassthroughAttr(passthroughAttr); } @@ -2699,6 +2780,7 @@ static void processPassthroughAttrs(llvm::Function *func, LLVMFuncOp funcOp) { void ModuleImport::processFunctionAttributes(llvm::Function *func, LLVMFuncOp funcOp) { processMemoryEffects(func, funcOp); + processDenormalFPEnv(func, funcOp); processPassthroughAttrs(func, funcOp); if (func->hasFnAttribute(llvm::Attribute::NoInline)) @@ -2717,6 +2799,12 @@ void ModuleImport::processFunctionAttributes(llvm::Function *func, funcOp.setWillReturn(true); if (func->hasFnAttribute(llvm::Attribute::NoReturn)) funcOp.setNoreturn(true); + if (func->hasFnAttribute(llvm::Attribute::OptimizeForSize)) + funcOp.setOptsize(true); + if (func->hasFnAttribute("save-reg-params")) + funcOp.setSaveRegParams(true); + if (func->hasFnAttribute(llvm::Attribute::MinSize)) + funcOp.setMinsize(true); if (func->hasFnAttribute(llvm::Attribute::ReturnsTwice)) funcOp.setReturnsTwice(true); if (func->hasFnAttribute(llvm::Attribute::Cold)) @@ -2732,6 +2820,10 @@ void ModuleImport::processFunctionAttributes(llvm::Function *func, if (llvm::Attribute attr = func->getFnAttribute("modular-format"); attr.isStringAttribute()) funcOp.setModularFormat(StringAttr::get(context, attr.getValueAsString())); + if (llvm::Attribute attr = func->getFnAttribute("zero-call-used-regs"); + attr.isStringAttribute()) + funcOp.setZeroCallUsedRegsAttr( + StringAttr::get(context, attr.getValueAsString())); if (func->hasFnAttribute("aarch64_pstate_sm_enabled")) funcOp.setArmStreaming(true); @@ -2751,6 +2843,9 @@ void ModuleImport::processFunctionAttributes(llvm::Function *func, else if (func->hasFnAttribute("aarch64_preserves_za")) funcOp.setArmPreservesZa(true); + convertNoBuiltinAttrs(context, func->getAttributes().getFnAttrs(), funcOp); + convertAllocsizeAttr(context, func->getAttributes().getFnAttrs(), funcOp); + llvm::Attribute attr = func->getFnAttribute(llvm::Attribute::VScaleRange); if (attr.isValid()) { MLIRContext *context = funcOp.getContext(); @@ -2792,10 +2887,6 @@ void ModuleImport::processFunctionAttributes(llvm::Function *func, attr.isStringAttribute()) funcOp.setPreferVectorWidth(attr.getValueAsString()); - if (llvm::Attribute attr = func->getFnAttribute("no-infs-fp-math"); - attr.isStringAttribute()) - funcOp.setNoInfsFpMath(attr.getValueAsBool()); - if (llvm::Attribute attr = func->getFnAttribute("no-nans-fp-math"); attr.isStringAttribute()) funcOp.setNoNansFpMath(attr.getValueAsBool()); @@ -2814,16 +2905,6 @@ void ModuleImport::processFunctionAttributes(llvm::Function *func, attr.isStringAttribute()) funcOp.setNoSignedZerosFpMath(attr.getValueAsBool()); - if (llvm::Attribute attr = func->getFnAttribute("denormal-fp-math"); - attr.isStringAttribute()) - funcOp.setDenormalFpMathAttr( - StringAttr::get(context, attr.getValueAsString())); - - if (llvm::Attribute attr = func->getFnAttribute("denormal-fp-math-f32"); - attr.isStringAttribute()) - funcOp.setDenormalFpMathF32Attr( - StringAttr::get(context, attr.getValueAsString())); - if (llvm::Attribute attr = func->getFnAttribute("fp-contract"); attr.isStringAttribute()) funcOp.setFpContractAttr(StringAttr::get(context, attr.getValueAsString())); @@ -2953,6 +3034,12 @@ LogicalResult ModuleImport::convertCallAttributes(llvm::CallInst *inst, op.setNoUnwind(callAttrs.getFnAttr(llvm::Attribute::NoUnwind).isValid()); op.setWillReturn(callAttrs.getFnAttr(llvm::Attribute::WillReturn).isValid()); op.setNoreturn(callAttrs.getFnAttr(llvm::Attribute::NoReturn).isValid()); + op.setOptsize( + callAttrs.getFnAttr(llvm::Attribute::OptimizeForSize).isValid()); + op.setSaveRegParams(callAttrs.getFnAttr("save-reg-params").isValid()); + op.setNobuiltin(callAttrs.getFnAttr(llvm::Attribute::NoBuiltin).isValid()); + op.setMinsize(callAttrs.getFnAttr(llvm::Attribute::MinSize).isValid()); + op.setReturnsTwice( callAttrs.getFnAttr(llvm::Attribute::ReturnsTwice).isValid()); op.setHot(callAttrs.getFnAttr(llvm::Attribute::Hot).isValid()); @@ -2966,6 +3053,13 @@ LogicalResult ModuleImport::convertCallAttributes(llvm::CallInst *inst, if (llvm::Attribute attr = callAttrs.getFnAttr("modular-format"); attr.isStringAttribute()) op.setModularFormat(StringAttr::get(context, attr.getValueAsString())); + if (llvm::Attribute attr = callAttrs.getFnAttr("zero-call-used-regs"); + attr.isStringAttribute()) + op.setZeroCallUsedRegsAttr( + StringAttr::get(context, attr.getValueAsString())); + if (llvm::Attribute attr = callAttrs.getFnAttr("trap-func-name"); + attr.isStringAttribute()) + op.setTrapFuncNameAttr(StringAttr::get(context, attr.getValueAsString())); op.setNoInline(callAttrs.getFnAttr(llvm::Attribute::NoInline).isValid()); op.setAlwaysInline( callAttrs.getFnAttr(llvm::Attribute::AlwaysInline).isValid()); @@ -2991,6 +3085,9 @@ LogicalResult ModuleImport::convertCallAttributes(llvm::CallInst *inst, if (!memAttr.isReadWrite()) op.setMemoryEffectsAttr(memAttr); + convertNoBuiltinAttrs(op.getContext(), callAttrs.getFnAttrs(), op); + convertAllocsizeAttr(op.getContext(), callAttrs.getFnAttrs(), op); + return convertCallBaseAttributes(inst, op); } diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp index 437701a48e460..c8cdb7bd793d9 100644 --- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp @@ -1516,6 +1516,7 @@ LogicalResult ModuleTranslation::convertOneFunction(LLVMFuncOp func) { valueMapping.clear(); branchMapping.clear(); llvm::Function *llvmFunc = lookupFunction(func.getName()); + llvm::LLVMContext &llvmContext = llvmFunc->getContext(); // Add function arguments to the value remapping table. for (auto [mlirArg, llvmArg] : @@ -1568,9 +1569,6 @@ LogicalResult ModuleTranslation::convertOneFunction(LLVMFuncOp func) { getLLVMContext(), attr->getMinRange().getInt(), attr->getMaxRange().getInt())); - if (auto noInfsFpMath = func.getNoInfsFpMath()) - llvmFunc->addFnAttr("no-infs-fp-math", llvm::toStringRef(*noInfsFpMath)); - if (auto noNansFpMath = func.getNoNansFpMath()) llvmFunc->addFnAttr("no-nans-fp-math", llvm::toStringRef(*noNansFpMath)); @@ -1578,12 +1576,6 @@ LogicalResult ModuleTranslation::convertOneFunction(LLVMFuncOp func) { llvmFunc->addFnAttr("no-signed-zeros-fp-math", llvm::toStringRef(*noSignedZerosFpMath)); - if (auto denormalFpMath = func.getDenormalFpMath()) - llvmFunc->addFnAttr("denormal-fp-math", *denormalFpMath); - - if (auto denormalFpMathF32 = func.getDenormalFpMathF32()) - llvmFunc->addFnAttr("denormal-fp-math-f32", *denormalFpMathF32); - if (auto fpContract = func.getFpContract()) llvmFunc->addFnAttr("fp-contract", *fpContract); @@ -1594,7 +1586,6 @@ LogicalResult ModuleTranslation::convertOneFunction(LLVMFuncOp func) { llvmFunc->addFnAttr("instrument-function-exit", *instrumentFunctionExit); // First, create all blocks so we can jump to them. - llvm::LLVMContext &llvmContext = llvmFunc->getContext(); for (auto &bb : func) { auto *llvmBB = llvm::BasicBlock::Create(llvmContext); llvmBB->insertInto(llvmFunc); @@ -1659,9 +1650,42 @@ static void convertFunctionMemoryAttributes(LLVMFuncOp func, llvmFunc->setMemoryEffects(newMemEffects); } +llvm::Attribute +ModuleTranslation::convertAllocsizeAttr(DenseI32ArrayAttr allocSizeAttr) { + if (!allocSizeAttr || allocSizeAttr.empty()) + return llvm::Attribute{}; + + unsigned elemSize = static_cast(allocSizeAttr[0]); + std::optional numElems; + if (allocSizeAttr.size() > 1) + numElems = static_cast(allocSizeAttr[1]); + + return llvm::Attribute::getWithAllocSizeArgs(getLLVMContext(), elemSize, + numElems); +} +static void convertDenormalFPEnvAttribute(LLVMFuncOp func, + llvm::AttrBuilder &Attrs) { + std::optional denormalFpEnv = func.getDenormalFpenv(); + if (!denormalFpEnv) + return; + + llvm::DenormalMode DefaultMode( + convertDenormalModeKindToLLVM(denormalFpEnv->getDefaultOutputMode()), + convertDenormalModeKindToLLVM(denormalFpEnv->getDefaultInputMode())); + llvm::DenormalMode FloatMode( + convertDenormalModeKindToLLVM(denormalFpEnv->getFloatOutputMode()), + convertDenormalModeKindToLLVM(denormalFpEnv->getFloatInputMode())); + + llvm::DenormalFPEnv FPEnv(DefaultMode, FloatMode); + Attrs.addDenormalFPEnvAttr(FPEnv); +} + /// Converts function attributes from `func` and attaches them to `llvmFunc`. -static void convertFunctionAttributes(LLVMFuncOp func, +static void convertFunctionAttributes(ModuleTranslation &mod, LLVMFuncOp func, llvm::Function *llvmFunc) { + // FIXME: Use AttrBuilder far all cases + llvm::AttrBuilder AttrBuilder(llvmFunc->getContext()); + if (func.getNoInlineAttr()) llvmFunc->addFnAttr(llvm::Attribute::NoInline); if (func.getAlwaysInlineAttr()) @@ -1686,6 +1710,12 @@ static void convertFunctionAttributes(LLVMFuncOp func, llvmFunc->addFnAttr(llvm::Attribute::WillReturn); if (func.getNoreturnAttr()) llvmFunc->addFnAttr(llvm::Attribute::NoReturn); + if (func.getOptsizeAttr()) + llvmFunc->addFnAttr(llvm::Attribute::OptimizeForSize); + if (func.getMinsizeAttr()) + llvmFunc->addFnAttr(llvm::Attribute::MinSize); + if (func.getSaveRegParamsAttr()) + llvmFunc->addFnAttr("save-reg-params"); if (func.getNoCallerSavedRegistersAttr()) llvmFunc->addFnAttr("no_caller_saved_registers"); if (func.getNocallbackAttr()) @@ -1700,7 +1730,28 @@ static void convertFunctionAttributes(LLVMFuncOp func, if (UWTableKindAttr uwTableKindAttr = func.getUwtableKindAttr()) llvmFunc->setUWTableKind( convertUWTableKindToLLVM(uwTableKindAttr.getUwtableKind())); + if (StringAttr zcsr = func.getZeroCallUsedRegsAttr()) + llvmFunc->addFnAttr("zero-call-used-regs", zcsr.getValue()); + + if (ArrayAttr noBuiltins = func.getNobuiltinsAttr()) { + if (noBuiltins.empty()) + llvmFunc->addFnAttr("no-builtins"); + + mod.convertFunctionAttrCollection(noBuiltins, llvmFunc, + ModuleTranslation::convertNoBuiltin); + } + + mod.convertFunctionAttrCollection(func.getDefaultFuncAttrsAttr(), llvmFunc, + ModuleTranslation::convertDefaultFuncAttr); + + if (llvm::Attribute attr = mod.convertAllocsizeAttr(func.getAllocsizeAttr()); + attr.isValid()) + llvmFunc->addFnAttr(attr); + convertFunctionMemoryAttributes(func, llvmFunc); + + convertDenormalFPEnvAttribute(func, AttrBuilder); + llvmFunc->addFnAttrs(AttrBuilder); } /// Converts function attributes from `func` and attaches them to `llvmFunc`. @@ -1836,6 +1887,26 @@ LogicalResult ModuleTranslation::convertArgAndResultAttrs( return success(); } +std::optional +ModuleTranslation::convertNoBuiltin(llvm::LLVMContext &ctx, mlir::Attribute a) { + if (auto str = dyn_cast(a)) + return llvm::Attribute::get(ctx, ("no-builtin-" + str.getValue()).str()); + return std::nullopt; +} + +std::optional +ModuleTranslation::convertDefaultFuncAttr(llvm::LLVMContext &ctx, + mlir::NamedAttribute namedAttr) { + StringAttr name = namedAttr.getName(); + Attribute value = namedAttr.getValue(); + + if (auto strVal = dyn_cast(value)) + return llvm::Attribute::get(ctx, name.getValue(), strVal.getValue()); + if (mlir::isa(value)) + return llvm::Attribute::get(ctx, name.getValue()); + return std::nullopt; +} + FailureOr ModuleTranslation::convertParameterAttrs(Location loc, DictionaryAttr paramAttrs) { @@ -1869,7 +1940,7 @@ LogicalResult ModuleTranslation::convertFunctionSignatures() { addRuntimePreemptionSpecifier(function.getDsoLocal(), llvmFunc); // Convert function attributes. - convertFunctionAttributes(function, llvmFunc); + convertFunctionAttributes(*this, function, llvmFunc); // Convert function kernel attributes to metadata. convertFunctionKernelAttributes(function, llvmFunc, *this); diff --git a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp index 8d1f9c26fe596..3ceaa9189898d 100644 --- a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp +++ b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp @@ -1094,30 +1094,38 @@ LogicalResult spirv::Deserializer::processType(spirv::Opcode opcode, uint32_t bitWidth = operands[1]; Type floatTy; - switch (bitWidth) { - case 16: - floatTy = opBuilder.getF16Type(); - break; - case 32: - floatTy = opBuilder.getF32Type(); - break; - case 64: - floatTy = opBuilder.getF64Type(); - break; - default: - return emitError(unknownLoc, "unsupported OpTypeFloat bitwidth: ") - << bitWidth; + if (operands.size() == 2) { + switch (bitWidth) { + case 16: + floatTy = opBuilder.getF16Type(); + break; + case 32: + floatTy = opBuilder.getF32Type(); + break; + case 64: + floatTy = opBuilder.getF64Type(); + break; + default: + return emitError(unknownLoc, "unsupported OpTypeFloat bitwidth: ") + << bitWidth; + } } if (operands.size() == 3) { - if (spirv::FPEncoding(operands[2]) != spirv::FPEncoding::BFloat16KHR) + if (spirv::FPEncoding(operands[2]) == spirv::FPEncoding::BFloat16KHR && + bitWidth == 16) + floatTy = opBuilder.getBF16Type(); + else if (spirv::FPEncoding(operands[2]) == + spirv::FPEncoding::Float8E4M3EXT && + bitWidth == 8) + floatTy = opBuilder.getF8E4M3FNType(); + else if (spirv::FPEncoding(operands[2]) == + spirv::FPEncoding::Float8E5M2EXT && + bitWidth == 8) + floatTy = opBuilder.getF8E5M2Type(); + else return emitError(unknownLoc, "unsupported OpTypeFloat FP encoding: ") - << operands[2]; - if (bitWidth != 16) - return emitError(unknownLoc, - "invalid OpTypeFloat bitwidth for bfloat16 encoding: ") - << bitWidth << " (expected 16)"; - floatTy = opBuilder.getBF16Type(); + << operands[2] << " and bitWidth " << bitWidth; } typeMap[operands[0]] = floatTy; @@ -1734,6 +1742,12 @@ LogicalResult spirv::Deserializer::processConstant(ArrayRef operands, } else if (floatType.isBF16()) { APInt data(16, operands[2]); value = APFloat(APFloat::BFloat(), data); + } else if (floatType.isF8E4M3FN()) { + APInt data(8, operands[2]); + value = APFloat(APFloat::Float8E4M3FN(), data); + } else if (floatType.isF8E5M2()) { + APInt data(8, operands[2]); + value = APFloat(APFloat::Float8E5M2(), data); } auto attr = opBuilder.getFloatAttr(floatType, value); diff --git a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp index 840c9c990f9c6..d9ffc4131d3c3 100644 --- a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp +++ b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp @@ -599,6 +599,15 @@ LogicalResult Serializer::prepareBasicType( if (floatType.isBF16()) { operands.push_back(static_cast(spirv::FPEncoding::BFloat16KHR)); } + if (floatType.isF8E4M3FN()) { + operands.push_back( + static_cast(spirv::FPEncoding::Float8E4M3EXT)); + } + if (floatType.isF8E5M2()) { + operands.push_back( + static_cast(spirv::FPEncoding::Float8E5M2EXT)); + } + return success(); } @@ -1253,8 +1262,10 @@ uint32_t Serializer::prepareConstantFp(Location loc, FloatAttr floatAttr, } words = llvm::bit_cast(value.convertToDouble()); encodeInstructionInto(typesGlobalValues, opcode, {typeID, resultID, words.word1, words.word2}); - } else if (semantics == &APFloat::IEEEhalf() || - semantics == &APFloat::BFloat()) { + } else if (llvm::is_contained({&APFloat::IEEEhalf(), &APFloat::BFloat(), + &APFloat::Float8E4M3FN(), + &APFloat::Float8E5M2()}, + semantics)) { uint32_t word = static_cast(value.bitcastToAPInt().getZExtValue()); encodeInstructionInto(typesGlobalValues, opcode, {typeID, resultID, word}); diff --git a/mlir/lib/Transforms/Utils/RegionUtils.cpp b/mlir/lib/Transforms/Utils/RegionUtils.cpp index 29f059a966903..5406a51d2ab7f 100644 --- a/mlir/lib/Transforms/Utils/RegionUtils.cpp +++ b/mlir/lib/Transforms/Utils/RegionUtils.cpp @@ -1096,31 +1096,105 @@ LogicalResult mlir::simplifyRegions(RewriterBase &rewriter, // Move operation dependencies //===---------------------------------------------------------------------===// +/// Check if moving operations in the slice before `insertionPoint` would break +/// dominance due to block argument operands. Returns true if all block args +/// dominate the insertion point (no issue), false otherwise. If `failingOp` is +/// provided, it will be set to the first problematic op. +/// +/// For operands defined by ops: either the defining op is in the slice (so +/// dominance preserved), or it already dominates insertionPoint (otherwise it +/// would be in the slice). So we only need to check block argument operands, +/// both as direct operands and as values captured inside regions. +static bool blockArgsDominateInsertionPoint( + const llvm::SetVector &slice, Operation *insertionPoint, + DominanceInfo &dominance, Operation **failingOp = nullptr) { + Block *insertionBlock = insertionPoint->getBlock(); + + // Returns true if the block arg dominates, false otherwise. Sets failingOp + // on failure. + auto argDominates = [&](BlockArgument arg, Operation *op) { + Block *argBlock = arg.getOwner(); + bool dominates = argBlock == insertionBlock || + dominance.dominates(argBlock, insertionBlock); + if (!dominates && failingOp) + *failingOp = op; + return dominates; + }; + + for (Operation *op : slice) { + // Check direct operands. + for (Value operand : op->getOperands()) { + auto arg = dyn_cast(operand); + if (!arg) + continue; + if (!argDominates(arg, op)) + return false; + } + + // Check block arguments captured inside regions. Process one region at a + // time to enable early exit without collecting values from all regions. + for (Region ®ion : op->getRegions()) { + SetVector capturedValues; + getUsedValuesDefinedAbove(region, region, capturedValues); + for (Value val : capturedValues) { + auto arg = dyn_cast(val); + if (!arg) + continue; + if (!argDominates(arg, op)) + return false; + } + } + } + return true; +} + +/// Check if any region between an operation and an ancestor block is +/// isolated from above. If so, moving the operation out would break +/// the isolation semantics. +static bool hasIsolatedRegionBetween(Operation *op, Block *ancestorBlock) { + Region *ancestorRegion = ancestorBlock->getParent(); + + // Walk up from the op's region to find if there's an isolated region + // between the op and the ancestor. + Region *region = op->getParentRegion(); + while (region && region != ancestorRegion) { + Operation *parentOp = region->getParentOp(); + if (!parentOp) + break; + + if (parentOp->hasTrait()) + return true; + + region = parentOp->getParentRegion(); + } + return false; +} + LogicalResult mlir::moveOperationDependencies(RewriterBase &rewriter, Operation *op, Operation *insertionPoint, DominanceInfo &dominance) { - // Currently unsupported case where the op and insertion point are - // in different basic blocks. - if (op->getBlock() != insertionPoint->getBlock()) { - return rewriter.notifyMatchFailure( - op, "unsupported case where operation and insertion point are not in " - "the same basic block"); - } - // If `insertionPoint` does not dominate `op`, do nothing + Block *insertionBlock = insertionPoint->getBlock(); + + // If `insertionPoint` does not dominate `op`, do nothing. if (!dominance.properlyDominates(insertionPoint, op)) { return rewriter.notifyMatchFailure(op, "insertion point does not dominate op"); } + // Verify we're not crossing an isolated region. + if (hasIsolatedRegionBetween(op, insertionBlock)) { + return rewriter.notifyMatchFailure( + op, "cannot move operation across isolated-from-above region"); + } + // Find the backward slice of operation for each `Value` the operation // depends on. Prune the slice to only include operations not already // dominated by the `insertionPoint`. BackwardSliceOptions options; options.inclusive = false; options.omitUsesFromAbove = false; - // Since current support is to only move within a same basic block, - // the slices dont need to look past block arguments. + // Block arguments cannot be moved; dominance check handles this case. options.omitBlockArguments = true; bool dependsOnSideEffectingOp = false; options.filter = [&](Operation *sliceBoundaryOp) { @@ -1158,6 +1232,15 @@ LogicalResult mlir::moveOperationDependencies(RewriterBase &rewriter, "cannot move dependencies before operation in backward slice of op"); } + // Verify no operation in the slice uses a block argument that wouldn't + // dominate at the new location. + Operation *badOp = nullptr; + if (!blockArgsDominateInsertionPoint(slice, insertionPoint, dominance, + &badOp)) { + return rewriter.notifyMatchFailure( + badOp, "moving op would break dominance for block argument operand"); + } + // We should move the slice in topological order, but `getBackwardSlice` // already does that. So no need to sort again. for (Operation *op : slice) { @@ -1188,13 +1271,26 @@ LogicalResult mlir::moveValueDefinitions(RewriterBase &rewriter, insertionPoint, "unsupported case of moving block argument before insertion point"); } - // Check for currently unsupported case if the insertion point is in a - // different block. - if (value.getDefiningOp()->getBlock() != insertionPoint->getBlock()) { + + Block *insertionBlock = insertionPoint->getBlock(); + Operation *definingOp = value.getDefiningOp(); + Block *definingBlock = definingOp->getBlock(); + + // Verify we're not crossing an isolated region. + if (hasIsolatedRegionBetween(definingOp, insertionBlock)) { return rewriter.notifyMatchFailure( insertionPoint, - "unsupported case of moving definition of value before an insertion " - "point in a different basic block"); + "cannot move value definition across isolated-from-above region"); + } + + // Verify the insertion point's block dominates the defining block, + // otherwise we're trying to move "backwards" in the CFG which doesn't + // make sense. + if (!dominance.dominates(insertionBlock, definingBlock)) { + return rewriter.notifyMatchFailure( + insertionPoint, + "insertion point block does not dominate the value's defining " + "block"); } prunedValues.push_back(value); } @@ -1205,8 +1301,9 @@ LogicalResult mlir::moveValueDefinitions(RewriterBase &rewriter, BackwardSliceOptions options; options.inclusive = true; options.omitUsesFromAbove = false; - // Since current support is to only move within a same basic block, - // the slices dont need to look past block arguments. + // Block arguments cannot be moved, so we stop the slice computation there. + // If an op uses a block argument that wouldn't dominate at the new location, + // the dominance check will catch it. options.omitBlockArguments = true; bool dependsOnSideEffectingOp = false; options.filter = [&](Operation *sliceBoundaryOp) { @@ -1243,9 +1340,20 @@ LogicalResult mlir::moveValueDefinitions(RewriterBase &rewriter, "cannot move dependencies before operation in backward slice of op"); } - // Sort operations topologically before moving. + // Sort operations topologically. This is needed because we call + // getBackwardSlice multiple times (once per value), and the combined slice + // may not be in topological order when independent subgraphs interleave. mlir::topologicalSort(slice); + // Verify no operation in the slice uses a block argument that wouldn't + // dominate at the new location. + Operation *badOp = nullptr; + if (!blockArgsDominateInsertionPoint(slice, insertionPoint, dominance, + &badOp)) { + return rewriter.notifyMatchFailure( + badOp, "moving op would break dominance for block argument operand"); + } + for (Operation *op : slice) rewriter.moveOpBefore(op, insertionPoint); return success(); diff --git a/mlir/python/CMakeLists.txt b/mlir/python/CMakeLists.txt index 8ab145ada85dd..50143f700f5a1 100644 --- a/mlir/python/CMakeLists.txt +++ b/mlir/python/CMakeLists.txt @@ -325,6 +325,15 @@ declare_mlir_dialect_extension_python_bindings( "../../include/mlir/Dialect/Vector/Transforms/VectorTransformsBase.td" ) +declare_mlir_dialect_extension_python_bindings( + ADD_TO_PARENT MLIRPythonSources.Dialects + ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir" + TD_FILE dialects/X86VectorTransformOps.td + SOURCES + dialects/transform/x86vector.py + DIALECT_NAME transform + EXTENSION_NAME x86vector_transform) + declare_mlir_dialect_extension_python_bindings( ADD_TO_PARENT MLIRPythonSources.Dialects ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir" @@ -510,6 +519,13 @@ declare_mlir_dialect_python_bindings( GEN_ENUM_BINDINGS_TD_FILE "dialects/VectorAttributes.td") +declare_mlir_dialect_python_bindings( + ADD_TO_PARENT MLIRPythonSources.Dialects + ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir" + TD_FILE dialects/X86Vector.td + SOURCES dialects/x86vector.py + DIALECT_NAME x86vector) + declare_mlir_dialect_python_bindings( ADD_TO_PARENT MLIRPythonSources.Dialects ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir" diff --git a/libclc/clc/lib/spirv/math/clc_runtime_has_hw_fma32.cl b/mlir/python/mlir/dialects/X86Vector.td similarity index 55% rename from libclc/clc/lib/spirv/math/clc_runtime_has_hw_fma32.cl rename to mlir/python/mlir/dialects/X86Vector.td index 2f6ad2c5175dd..d8a846bf9e905 100644 --- a/libclc/clc/lib/spirv/math/clc_runtime_has_hw_fma32.cl +++ b/mlir/python/mlir/dialects/X86Vector.td @@ -1,4 +1,4 @@ -//===----------------------------------------------------------------------===// +//===-- X86Vector.td - Entry point for x86vector bindings --*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,4 +6,9 @@ // //===----------------------------------------------------------------------===// -bool __clc_runtime_has_hw_fma32() { return false; } +#ifndef PYTHON_BINDINGS_X86VECTOR +#define PYTHON_BINDINGS_X86VECTOR + +include "mlir/Dialect/X86Vector/X86Vector.td" + +#endif // PYTHON_BINDINGS_X86VECTOR diff --git a/mlir/python/mlir/dialects/X86VectorTransformOps.td b/mlir/python/mlir/dialects/X86VectorTransformOps.td new file mode 100644 index 0000000000000..ad6a693923703 --- /dev/null +++ b/mlir/python/mlir/dialects/X86VectorTransformOps.td @@ -0,0 +1,14 @@ +//===-- X86VectorTransformOps.td ---------------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef PYTHON_BINDINGS_X86VECTORTRANSFORMOPS +#define PYTHON_BINDINGS_X86VECTORTRANSFORMOPS + +include "mlir/Dialect/X86Vector/TransformOps/X86VectorTransformOps.td" + +#endif // PYTHON_BINDINGS_X86VECTORTRANSFORMOPS diff --git a/mlir/python/mlir/dialects/ext.py b/mlir/python/mlir/dialects/ext.py index 237c27bf62f77..251d4831cb331 100644 --- a/mlir/python/mlir/dialects/ext.py +++ b/mlir/python/mlir/dialects/ext.py @@ -29,10 +29,13 @@ "Dialect", "Operand", "Result", + "Region", + "Operation", ] Operand = ir.Value Result = ir.OpResult +Region = ir.Region class ConstraintLoweringContext: @@ -102,7 +105,6 @@ class FieldDef: """ name: str - constraint: Any variadicity: Variadicity @staticmethod @@ -117,38 +119,50 @@ def from_type_hint(name, type_) -> "FieldDef": origin = get_origin(type_) if origin is ir.OpResult: - return ResultDef(name, get_args(type_)[0], variadicity) + return ResultDef(name, variadicity, get_args(type_)[0]) elif origin is ir.Value: - return OperandDef(name, get_args(type_)[0], variadicity) + return OperandDef(name, variadicity, get_args(type_)[0]) elif issubclass(origin or type_, ir.Attribute): - return AttributeDef(name, type_, variadicity) + return AttributeDef(name, variadicity, type_) + elif type_ is ir.Region: + return RegionDef(name, variadicity) raise TypeError(f"unsupported type in operation definition: {type_}") @dataclass class OperandDef(FieldDef): - pass + constraint: Any @dataclass class ResultDef(FieldDef): - pass + constraint: Any @dataclass class AttributeDef(FieldDef): + constraint: Any + + def __post_init__(self): + if self.variadicity != Variadicity.single: + raise ValueError("optional attribute is not currently supported") + + +@dataclass +class RegionDef(FieldDef): def __post_init__(self): if self.variadicity != Variadicity.single: - raise ValueError("optional attribute is not supported in IRDL") + raise ValueError("optional region is not currently supported") def partition_fields( fields: List[FieldDef], -) -> Tuple[List[OperandDef], List[AttributeDef], List[ResultDef]]: +) -> Tuple[List[OperandDef], List[AttributeDef], List[ResultDef], List[RegionDef]]: operands = [i for i in fields if isinstance(i, OperandDef)] attrs = [i for i in fields if isinstance(i, AttributeDef)] results = [i for i in fields if isinstance(i, ResultDef)] - return operands, attrs, results + regions = [i for i in fields if isinstance(i, RegionDef)] + return operands, attrs, results, regions def normalize_value_range( @@ -216,6 +230,11 @@ def __init_subclass__(cls, *, name: str = None, **kwargs): if not name: return + if not hasattr(cls, "_dialect_name") or not hasattr(cls, "_dialect_obj"): + raise RuntimeError( + "Operation subclasses must inherit from a Dialect's Operation subclass" + ) + op_name = name cls._op_name = op_name dialect_name = cls._dialect_name @@ -223,10 +242,11 @@ def __init_subclass__(cls, *, name: str = None, **kwargs): cls._generate_class_attributes(dialect_name, op_name, fields) cls._generate_init_method(fields) - operands, attrs, results = partition_fields(fields) + operands, attrs, results, regions = partition_fields(fields) cls._generate_attr_properties(attrs) cls._generate_operand_properties(operands) cls._generate_result_properties(results) + cls._generate_region_properties(regions) dialect_obj.operations.append(cls) @@ -254,7 +274,9 @@ def _generate_init_signature( ) # results are placed at the beginning of the parameter list, # but operands and attributes can appear in any relative order. - args = result_args + [i for i in fields if not isinstance(i, ResultDef)] + args = result_args + [ + i for i in fields if not isinstance(i, ResultDef | RegionDef) + ] positional_args = [ i.name for i in args if i.variadicity != Variadicity.optional ] @@ -272,7 +294,7 @@ def _generate_init_signature( @classmethod def _generate_init_method(cls, fields: List[FieldDef]) -> None: - operands, attrs, results = partition_fields(fields) + operands, attrs, results, regions = partition_fields(fields) inferred_types = [infer_type(i.constraint) for i in results] # we infer result types only when all result types can be inferred @@ -299,7 +321,7 @@ def __init__(*args, **kwargs): for attr in attrs if args[attr.name] is not None ) - _regions = None + _regions = len(regions) or None _ods_successors = None self = args["self"] super(Operation, self).__init__( @@ -323,13 +345,13 @@ def __init__(*args, **kwargs): def _generate_class_attributes( cls, dialect_name: str, op_name: str, fields: List[FieldDef] ) -> None: - operands, attrs, results = partition_fields(fields) + operands, attrs, results, regions = partition_fields(fields) operand_segments = cls._generate_segments(operands) result_segments = cls._generate_segments(results) cls.OPERATION_NAME = f"{dialect_name}.{op_name}" - cls._ODS_REGIONS = (0, True) + cls._ODS_REGIONS = (len(regions), True) cls._ODS_OPERAND_SEGMENTS = operand_segments cls._ODS_RESULT_SEGMENTS = result_segments @@ -342,6 +364,15 @@ def _generate_attr_properties(cls, attrs: List[AttributeDef]) -> None: property(lambda self, name=attr.name: self.attributes[name]), ) + @classmethod + def _generate_region_properties(cls, regions: List[RegionDef]) -> None: + for i, region in enumerate(regions): + setattr( + cls, + region.name, + property(lambda self, i=i: self.regions[i]), + ) + @classmethod def _generate_operand_properties(cls, operands: List[OperandDef]) -> None: for i, operand in enumerate(operands): @@ -379,7 +410,7 @@ def getter(self, i=i, result=result): @classmethod def _emit_operation(cls) -> None: ctx = ConstraintLoweringContext() - operands, attrs, results = partition_fields(cls._fields) + operands, attrs, results, regions = partition_fields(cls._fields) op = irdl.operation_(cls._op_name) with ir.InsertionPoint(op.body): @@ -400,6 +431,11 @@ def _emit_operation(cls) -> None: [i.name for i in results], [i.variadicity for i in results], ) + if regions: + irdl.regions_( + [irdl.region([]) for _ in regions], + [i.name for i in regions], + ) class Dialect(ir.Dialect): diff --git a/mlir/python/mlir/dialects/transform/x86vector.py b/mlir/python/mlir/dialects/transform/x86vector.py new file mode 100644 index 0000000000000..cccd300522797 --- /dev/null +++ b/mlir/python/mlir/dialects/transform/x86vector.py @@ -0,0 +1,5 @@ +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +from .._x86vector_transform_ops_gen import * diff --git a/mlir/python/mlir/dialects/x86vector.py b/mlir/python/mlir/dialects/x86vector.py new file mode 100644 index 0000000000000..eddc93dbe6460 --- /dev/null +++ b/mlir/python/mlir/dialects/x86vector.py @@ -0,0 +1,6 @@ +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +from ._x86vector_ops_gen import * +from ._x86vector_ops_gen import _Dialect diff --git a/mlir/test/Analysis/DataFlow/test-dead-code-analysis-func.mlir b/mlir/test/Analysis/DataFlow/test-dead-code-analysis-func.mlir new file mode 100644 index 0000000000000..b9c1e72e5be56 --- /dev/null +++ b/mlir/test/Analysis/DataFlow/test-dead-code-analysis-func.mlir @@ -0,0 +1,12 @@ +// RUN: mlir-opt --pass-pipeline="builtin.module(func.func(test-dead-code-analysis))" 2>&1 %s | FileCheck %s + +// Test that when dead code analysis is run on a single function, we correctly +// identify that we do not know all of the predecessors. +// CHECK: foo: +// CHECK-NEXT: region #0 +// CHECK-NEXT: ^bb0 = live +// CHECK-NEXT: op_preds: predecessors: (none) +func.func @foo(%arg0: i32) -> i32 + attributes {tag = "foo"} { + return {a} %arg0 : i32 +} diff --git a/mlir/test/CAPI/ir.c b/mlir/test/CAPI/ir.c index 7608ad1b968ef..c2caae4e795f3 100644 --- a/mlir/test/CAPI/ir.c +++ b/mlir/test/CAPI/ir.c @@ -320,7 +320,7 @@ int collectStats(MlirOperation operation) { // clang-format off // CHECK-LABEL: @stats // CHECK: Number of operations: 12 - // CHECK: Number of attributes: 6 + // CHECK: Number of attributes: 5 // CHECK: Number of blocks: 3 // CHECK: Number of regions: 3 // CHECK: Number of values: 9 diff --git a/mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir b/mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir index 7eb7ddeab13a4..af12cfdd9a633 100644 --- a/mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir +++ b/mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir @@ -760,8 +760,6 @@ func.func @tensor_store_from_lds(%desc: !amdgpu.tdm_descriptor) { func.return } -// ----- - // CHECK-LABEL: func @make_gather_dma_descriptor // CHECK-SAME: (%[[BASE:.+]]: !amdgpu.tdm_gather_base, %[[INDICES:.+]]: vector<13xi16>) func.func @make_gather_dma_descriptor(%base: !amdgpu.tdm_gather_base, %indices: vector<13xi16>) -> !amdgpu.tdm_descriptor { @@ -868,3 +866,95 @@ func.func @make_gather_dma_descriptor(%base: !amdgpu.tdm_gather_base, func.return %descriptor : !amdgpu.tdm_descriptor } +/// LDS barriers + +// CHECK-LABEL: func @ds_barrier_init +func.func @ds_barrier_init(%barrier: memref>, %participants: i32) { + // CHECK: [[CAST:%.*]] = builtin.unrealized_conversion_cast %arg0 + // CHECK: [[PTR:%.*]] = llvm.extractvalue [[CAST]][1] + // CHECK: [[C1:%.*]] = llvm.mlir.constant(1 : i32) + // CHECK: [[SUB:%.*]] = llvm.sub %arg1, [[C1]] + // CHECK: [[MASK:%.*]] = llvm.mlir.constant(268435455 : i32) + // CHECK: [[MASKED:%.*]] = llvm.and [[SUB]], [[MASK]] + // CHECK: [[ZEXT:%.*]] = llvm.zext [[MASKED]] : i32 to i64 + // CHECK: [[C32:%.*]] = llvm.mlir.constant(32 : i64) + // CHECK: [[INIT_SHIFT:%.*]] = llvm.shl [[ZEXT]], [[C32]] + // CHECK: [[STATE:%.*]] = llvm.or [[INIT_SHIFT]], [[ZEXT]] + // CHECK: llvm.store [[STATE]], [[PTR]] atomic syncscope("workgroup") release + amdgpu.ds_barrier_init %barrier[], %participants : memref>, i32 + func.return +} + +// CHECK-LABEL: func @ds_barrier_poll_state +func.func @ds_barrier_poll_state(%barrier: memref>) -> !amdgpu.ds_barrier_state { + // CHECK: [[CAST:%.*]] = builtin.unrealized_conversion_cast %arg0 + // CHECK: [[PTR:%.*]] = llvm.extractvalue [[CAST]][1] + // CHECK: [[LOADED:%.*]] = llvm.load [[PTR]] atomic syncscope("workgroup") acquire + // CHECK: builtin.unrealized_conversion_cast [[LOADED]] + %state = amdgpu.ds_barrier_poll_state %barrier[] : memref> -> !amdgpu.ds_barrier_state + func.return %state : !amdgpu.ds_barrier_state +} + +// CHECK-LABEL: func @ds_async_barrier_arrive +func.func @ds_async_barrier_arrive(%barrier: memref>) { + // CHECK: [[CAST:%.*]] = builtin.unrealized_conversion_cast %arg0 + // CHECK: [[PTR:%.*]] = llvm.extractvalue [[CAST]][1] + // CHECK: rocdl.ds.atomic.async.barrier.arrive.b64 [[PTR]] : !llvm.ptr<3> + amdgpu.ds_async_barrier_arrive %barrier[] : memref> + func.return +} + +// CHECK-LABEL: func @ds_barrier_arrive +func.func @ds_barrier_arrive(%barrier: memref>, %count: i64) -> !amdgpu.ds_barrier_state { + // CHECK: [[CAST:%.*]] = builtin.unrealized_conversion_cast %arg0 + // CHECK: [[PTR:%.*]] = llvm.extractvalue [[CAST]][1] + // CHECK: [[OLD:%.*]] = rocdl.ds.atomic.barrier.arrive.rtn.b64 [[PTR]], %arg1 : !llvm.ptr<3>, i64 -> i64 + // CHECK: builtin.unrealized_conversion_cast [[OLD]] + %old_state = amdgpu.ds_barrier_arrive %barrier[], %count : memref>, i64 -> !amdgpu.ds_barrier_state + func.return %old_state : !amdgpu.ds_barrier_state +} + +// CHECK-LABEL: func @ds_barrier_state_phase +func.func @ds_barrier_state_phase(%state: !amdgpu.ds_barrier_state) -> i32 { + // CHECK: [[CAST:%.*]] = builtin.unrealized_conversion_cast %arg0 + // CHECK: [[TRUNC:%.*]] = llvm.trunc [[CAST]] : i64 to i32 + // CHECK: [[C28:%.*]] = llvm.mlir.constant(28 : i32) + // CHECK: [[PHASE:%.*]] = llvm.lshr [[TRUNC]], [[C28]] + // CHECK: return [[PHASE]] + %phase = amdgpu.ds_barrier_state_phase %state : !amdgpu.ds_barrier_state -> i32 + func.return %phase : i32 +} + +// CHECK-LABEL: func @ds_barrier_state_pending_count +func.func @ds_barrier_state_pending_count(%state: !amdgpu.ds_barrier_state) -> i32 { + // CHECK: [[CAST:%.*]] = builtin.unrealized_conversion_cast %arg0 + // CHECK: [[TRUNC:%.*]] = llvm.trunc [[CAST]] : i64 to i32 + // CHECK: [[MASK:%.*]] = llvm.mlir.constant(268435455 : i32) + // CHECK: [[COUNT:%.*]] = llvm.and [[TRUNC]], [[MASK]] + // CHECK: return [[COUNT]] + %pending = amdgpu.ds_barrier_state_pending_count %state : !amdgpu.ds_barrier_state -> i32 + func.return %pending : i32 +} + +// CHECK-LABEL: func @ds_barrier_state_init_count +func.func @ds_barrier_state_init_count(%state: !amdgpu.ds_barrier_state) -> i32 { + // CHECK: [[CAST:%.*]] = builtin.unrealized_conversion_cast %arg0 + // CHECK: [[C32:%.*]] = llvm.mlir.constant(32 : i64) + // CHECK: [[SHIFTED:%.*]] = llvm.lshr [[CAST]], [[C32]] + // CHECK: [[COUNT:%.*]] = llvm.trunc [[SHIFTED]] : i64 to i32 + // CHECK: return [[COUNT]] + %init = amdgpu.ds_barrier_state_init_count %state : !amdgpu.ds_barrier_state -> i32 + func.return %init : i32 +} + +// CHECK-LABEL: func @ds_barrier_state_phase_parity +func.func @ds_barrier_state_phase_parity(%state: !amdgpu.ds_barrier_state) -> i1 { + // CHECK: [[CAST:%.*]] = builtin.unrealized_conversion_cast %arg0 + // CHECK: [[TRUNC:%.*]] = llvm.trunc [[CAST]] : i64 to i32 + // CHECK: [[C28:%.*]] = llvm.mlir.constant(28 : i32) + // CHECK: [[SHIFTED:%.*]] = llvm.lshr [[TRUNC]], [[C28]] + // CHECK: [[PARITY:%.*]] = llvm.trunc [[SHIFTED]] : i32 to i1 + // CHECK: return [[PARITY]] + %parity = amdgpu.ds_barrier_state_phase_parity %state : !amdgpu.ds_barrier_state -> i1 + func.return %parity : i1 +} diff --git a/mlir/test/Conversion/ConvertToSPIRV/gpu.mlir b/mlir/test/Conversion/ConvertToSPIRV/gpu.mlir index 3e197c076be6a..6163f3464d1cc 100644 --- a/mlir/test/Conversion/ConvertToSPIRV/gpu.mlir +++ b/mlir/test/Conversion/ConvertToSPIRV/gpu.mlir @@ -27,11 +27,12 @@ module attributes { gpu.module @kernels { // CHECK-LABEL: spirv.func @subgroup_reduce - // CHECK-SAME: (%[[ARG0:.*]]: f32) + // CHECK-SAME: (%[[ARG0:.*]]: f32, [[BUF:.*]]: !spirv.ptr{{[^)]*}}) // CHECK: %{{.*}} = spirv.GroupNonUniformFAdd %[[ARG0]] : f32 -> f32 - gpu.func @subgroup_reduce(%arg0 : f32) kernel + gpu.func @subgroup_reduce(%arg0 : f32, %buf : memref) kernel attributes {spirv.entry_point_abi = #spirv.entry_point_abi} { %reduced = gpu.subgroup_reduce add %arg0 {} : (f32) -> (f32) + memref.store %reduced, %buf[] : memref gpu.return } } diff --git a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir index 55ee508aa9f55..ac091664fe7da 100644 --- a/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir +++ b/mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir @@ -644,39 +644,45 @@ gpu.module @test_module_29 { gpu.module @test_module_30 { // CHECK-LABEL: func @subgroup_reduce_add - gpu.func @subgroup_reduce_add(%arg0 : i32) { + gpu.func @subgroup_reduce_add(%arg0 : i32, %buf : memref) { // CHECK: nvvm.redux.sync add {{.*}} %result = gpu.subgroup_reduce add %arg0 uniform {} : (i32) -> (i32) + memref.store %result, %buf[] : memref gpu.return } // CHECK-LABEL: @subgroup_reduce_minsi - gpu.func @subgroup_reduce_minsi(%arg0 : i32) { + gpu.func @subgroup_reduce_minsi(%arg0 : i32, %buf : memref) { // CHECK: nvvm.redux.sync min {{.*}} %result = gpu.subgroup_reduce minsi %arg0 uniform {} : (i32) -> (i32) + memref.store %result, %buf[] : memref gpu.return } // CHECK-LABEL: @subgroup_reduce_maxsi - gpu.func @subgroup_reduce_maxsi(%arg0 : i32) { + gpu.func @subgroup_reduce_maxsi(%arg0 : i32, %buf : memref) { // CHECK: nvvm.redux.sync max {{.*}} %result = gpu.subgroup_reduce maxsi %arg0 uniform {} : (i32) -> (i32) + memref.store %result, %buf[] : memref gpu.return } // CHECK-LABEL: func @subgroup_reduce_and - gpu.func @subgroup_reduce_and(%arg0 : i32) { + gpu.func @subgroup_reduce_and(%arg0 : i32, %buf : memref) { // CHECK: nvvm.redux.sync and {{.*}} %result = gpu.subgroup_reduce and %arg0 uniform {} : (i32) -> (i32) + memref.store %result, %buf[] : memref gpu.return } // CHECK-LABEL: @subgroup_reduce_or - gpu.func @subgroup_reduce_or(%arg0 : i32) { + gpu.func @subgroup_reduce_or(%arg0 : i32, %buf : memref) { // CHECK: nvvm.redux.sync or {{.*}} %result = gpu.subgroup_reduce or %arg0 uniform {} : (i32) -> (i32) + memref.store %result, %buf[] : memref gpu.return } // CHECK-LABEL: @subgroup_reduce_xor - gpu.func @subgroup_reduce_xor(%arg0 : i32) { + gpu.func @subgroup_reduce_xor(%arg0 : i32, %buf : memref) { // CHECK: nvvm.redux.sync xor {{.*}} %result = gpu.subgroup_reduce xor %arg0 uniform {} : (i32) -> (i32) + memref.store %result, %buf[] : memref gpu.return } } diff --git a/mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-subgroup-id.mlir b/mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-subgroup-id.mlir new file mode 100644 index 0000000000000..030eb0e5eb181 --- /dev/null +++ b/mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-subgroup-id.mlir @@ -0,0 +1,40 @@ +// RUN: mlir-opt %s -convert-gpu-to-rocdl='chipset=gfx942' | FileCheck %s --check-prefixes=CHECK,GFX9 +// RUN: mlir-opt %s -convert-gpu-to-rocdl='chipset=gfx1201' | FileCheck %s --check-prefixes=CHECK,GFX12 + +gpu.module @test_module { +// CHECK-LABEL: func @subgroup_id() +func.func @subgroup_id() -> index { + // GFX12: rocdl.wave.id : i32 + // GFX12: llvm.sext %{{.*}} : i32 to i64 + + // GFX9-DAG: rocdl.workitem.id.x : i32 + // GFX9-DAG: rocdl.workitem.id.y : i32 + // GFX9-DAG: rocdl.workitem.id.z : i32 + // GFX9-DAG: rocdl.workgroup.dim.x : i32 + // GFX9-DAG: rocdl.workgroup.dim.y : i32 + // GFX9-DAG: llvm.mul %{{.*}}, %{{.*}} overflow + // GFX9-DAG: llvm.add %{{.*}}, %{{.*}} overflow + // GFX9: rocdl.wavefrontsize : i32 + // GFX9: llvm.udiv + // GFX9: llvm.sext %{{.*}} : i32 to i64 + %subgroupId = gpu.subgroup_id : index + func.return %subgroupId : index +} + +// CHECK-LABEL: func @subgroup_id_with_upper_bound() +func.func @subgroup_id_with_upper_bound() -> index { + // GFX12: rocdl.wave.id range : i32 + // GFX12: llvm.sext %{{.*}} : i32 to i64 + + // GFX9-DAG: rocdl.workitem.id.x : i32 + // GFX9-DAG: rocdl.workitem.id.y : i32 + // GFX9-DAG: rocdl.workitem.id.z : i32 + // GFX9-DAG: rocdl.workgroup.dim.x : i32 + // GFX9-DAG: rocdl.workgroup.dim.y : i32 + // GFX9: rocdl.wavefrontsize : i32 + // GFX9: llvm.udiv + // GFX9: llvm.sext %{{.*}} : i32 to i64 + %subgroupId = gpu.subgroup_id upper_bound 4 : index + func.return %subgroupId : index +} +} diff --git a/mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir b/mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir index 4c1beee2fe144..9ec81c53b41f8 100644 --- a/mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir +++ b/mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir @@ -4,7 +4,7 @@ // CHECK: module attributes {dlti.map = #dlti.map<"MPI:Implementation" = "MPICH">} { // CHECK: llvm.func @MPI_Finalize() -> i32 // CHECK: llvm.func @MPI_Allreduce(!llvm.ptr, !llvm.ptr, i32, i32, i32, i32) -> i32 -// CHECK: llvm.func @MPI_Comm_Size(i32, !llvm.ptr) -> i32 +// CHECK: llvm.func @MPI_Comm_size(i32, !llvm.ptr) -> i32 // CHECK: llvm.func @MPI_Allgather(!llvm.ptr, i32, i32, !llvm.ptr, i32, i32, i32) -> i32 // CHECK: llvm.func @MPI_Comm_split(i32, i32, i32, !llvm.ptr) -> i32 // CHECK: llvm.func @MPI_Recv(!llvm.ptr, i32, i32, i32, i32, i32, !llvm.ptr) -> i32 @@ -40,7 +40,8 @@ module attributes {dlti.map = #dlti.map<"MPI:Implementation" = "MPICH">} { // CHECK: [[v14:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v15:%.*]] = llvm.getelementptr [[v13]][[[v14]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v16:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v17:%.*]] = llvm.trunc [[v16]] : i64 to i32 + // CHECK: [[v17a:%.*]] = llvm.trunc [[v16]] : i64 to i32 + // CHECK: [[v17:%.*]] = llvm.mul [[v17a]] // CHECK: [[v18:%.*]] = llvm.mlir.constant(1275069450 : i32) : i32 // CHECK: [[comm_1:%.*]] = llvm.trunc [[comm]] : i64 to i32 // CHECK: [[v20:%.*]] = llvm.call @MPI_Send([[v15]], [[v17]], [[v18]], [[v12]], [[v12]], [[comm_1]]) : (!llvm.ptr, i32, i32, i32, i32, i32) -> i32 @@ -50,7 +51,8 @@ module attributes {dlti.map = #dlti.map<"MPI:Implementation" = "MPICH">} { // CHECK: [[v22:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v23:%.*]] = llvm.getelementptr [[v21]][[[v22]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v24:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v25:%.*]] = llvm.trunc [[v24]] : i64 to i32 + // CHECK: [[v25a:%.*]] = llvm.trunc [[v24]] : i64 to i32 + // CHECK: [[v25:%.*]] = llvm.mul [[v25a]] // CHECK: [[v26:%.*]] = llvm.mlir.constant(1275069450 : i32) : i32 // CHECK: [[comm_2:%.*]] = llvm.trunc [[comm]] : i64 to i32 // CHECK: [[v28:%.*]] = llvm.call @MPI_Send([[v23]], [[v25]], [[v26]], [[v12]], [[v12]], [[comm_2]]) : (!llvm.ptr, i32, i32, i32, i32, i32) -> i32 @@ -60,7 +62,8 @@ module attributes {dlti.map = #dlti.map<"MPI:Implementation" = "MPICH">} { // CHECK: [[v30:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v31:%.*]] = llvm.getelementptr [[v29]][[[v30]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v32:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v33:%.*]] = llvm.trunc [[v32]] : i64 to i32 + // CHECK: [[v33a:%.*]] = llvm.trunc [[v32]] : i64 to i32 + // CHECK: [[v33:%.*]] = llvm.mul [[v33a]] // CHECK: [[v34:%.*]] = llvm.mlir.constant(1275069450 : i32) : i32 // CHECK: [[comm_3:%.*]] = llvm.trunc [[comm]] : i64 to i32 // CHECK: [[v36:%.*]] = llvm.mlir.constant(1 : i64) : i64 @@ -72,7 +75,8 @@ module attributes {dlti.map = #dlti.map<"MPI:Implementation" = "MPICH">} { // CHECK: [[v40:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v41:%.*]] = llvm.getelementptr [[v39]][[[v40]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v42:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v43:%.*]] = llvm.trunc [[v42]] : i64 to i32 + // CHECK: [[v43a:%.*]] = llvm.trunc [[v42]] : i64 to i32 + // CHECK: [[v43:%.*]] = llvm.mul [[v43a]] // CHECK: [[v44:%.*]] = llvm.mlir.constant(1275069450 : i32) : i32 // CHECK: [[comm_4:%.*]] = llvm.trunc [[comm]] : i64 to i32 // CHECK: [[v46:%.*]] = llvm.mlir.constant(1 : i64) : i64 @@ -91,6 +95,7 @@ module attributes {dlti.map = #dlti.map<"MPI:Implementation" = "MPICH">} { // CHECK: [[v57:%.*]] = llvm.load [[v55]] : !llvm.ptr -> i32 %split = mpi.comm_split(%comm, %color, %key) : !mpi.comm + // CHECK: llvm.call @MPI_Comm_size // CHECK: llvm.call @MPI_Allgather({{.*}} : (!llvm.ptr, i32, i32, !llvm.ptr, i32, i32, i32) -> i32 %err3 = mpi.allgather(%arg0, %arg0, %comm) : memref<100xf32>, memref<100xf32> -> !mpi.retval @@ -98,12 +103,14 @@ module attributes {dlti.map = #dlti.map<"MPI:Implementation" = "MPICH">} { // CHECK: [[v60:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v61:%.*]] = llvm.getelementptr [[v59]][[[v60]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v62:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v63:%.*]] = llvm.trunc [[v62]] : i64 to i32 + // CHECK: [[v63a:%.*]] = llvm.trunc [[v62]] : i64 to i32 + // CHECK: [[v63:%.*]] = llvm.mul [[v63a]] // CHECK: [[v64:%.*]] = llvm.extractvalue [[v5]][1] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v65:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v66:%.*]] = llvm.getelementptr [[v64]][[[v65]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v67:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v68:%.*]] = llvm.trunc [[v67]] : i64 to i32 + // CHECK: [[v68a:%.*]] = llvm.trunc [[v67]] : i64 to i32 + // CHECK: [[v68:%.*]] = llvm.mul [[v68a]] // CHECK: [[ip:%.*]] = llvm.mlir.constant(-1 : i64) : i64 // CHECK: [[ipp:%.*]] = llvm.inttoptr [[ip]] : i64 to !llvm.ptr // CHECK: [[v69:%.*]] = llvm.mlir.constant(1275069450 : i32) : i32 @@ -127,7 +134,7 @@ module attributes {dlti.map = #dlti.map<"MPI:Implementation" = "MPICH">} { // CHECK: llvm.func @MPI_Comm_split(!llvm.ptr, i32, i32, !llvm.ptr) -> i32 // CHECK: llvm.func @MPI_Allreduce(!llvm.ptr, !llvm.ptr, i32, !llvm.ptr, !llvm.ptr, !llvm.ptr) -> i32 // CHECK: llvm.mlir.global external @ompi_mpi_sum() {addr_space = 0 : i32} : !llvm.struct<"ompi_predefined_op_t", opaque> -// CHECK: llvm.func @MPI_Comm_Size(!llvm.ptr, !llvm.ptr) -> i32 +// CHECK: llvm.func @MPI_Comm_size(!llvm.ptr, !llvm.ptr) -> i32 // CHECK: llvm.func @MPI_Allgather(!llvm.ptr, i32, !llvm.ptr, !llvm.ptr, i32, !llvm.ptr, !llvm.ptr) -> i32 // CHECK: llvm.func @MPI_Recv(!llvm.ptr, i32, !llvm.ptr, i32, i32, !llvm.ptr, !llvm.ptr) -> i32 // CHECK: llvm.func @MPI_Send(!llvm.ptr, i32, !llvm.ptr, i32, i32, !llvm.ptr) -> i32 @@ -164,7 +171,8 @@ module attributes { dlti.map = #dlti.map<"MPI:Implementation" = "OpenMPI"> } { // CHECK: [[v14:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v15:%.*]] = llvm.getelementptr [[v13]][[[v14]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v16:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v17:%.*]] = llvm.trunc [[v16]] : i64 to i32 + // CHECK: [[v17a:%.*]] = llvm.trunc [[v16]] : i64 to i32 + // CHECK: [[v17:%.*]] = llvm.mul [[v17a]] // CHECK: [[v18:%.*]] = llvm.mlir.addressof @ompi_mpi_float : !llvm.ptr // CHECK: [[v19:%.*]] = llvm.inttoptr [[comm]] : i64 to !llvm.ptr // CHECK: [[v20:%.*]] = llvm.call @MPI_Send([[v15]], [[v17]], [[v18]], [[v12]], [[v12]], [[v19]]) : (!llvm.ptr, i32, !llvm.ptr, i32, i32, !llvm.ptr) -> i32 @@ -174,7 +182,8 @@ module attributes { dlti.map = #dlti.map<"MPI:Implementation" = "OpenMPI"> } { // CHECK: [[v22:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v23:%.*]] = llvm.getelementptr [[v21]][[[v22]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v24:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v25:%.*]] = llvm.trunc [[v24]] : i64 to i32 + // CHECK: [[v25a:%.*]] = llvm.trunc [[v24]] : i64 to i32 + // CHECK: [[v25:%.*]] = llvm.mul [[v25a]] // CHECK: [[v26:%.*]] = llvm.mlir.addressof @ompi_mpi_float : !llvm.ptr // CHECK: [[v27:%.*]] = llvm.inttoptr [[comm]] : i64 to !llvm.ptr // CHECK: [[v28:%.*]] = llvm.call @MPI_Send([[v23]], [[v25]], [[v26]], [[v12]], [[v12]], [[v27]]) : (!llvm.ptr, i32, !llvm.ptr, i32, i32, !llvm.ptr) -> i32 @@ -184,7 +193,8 @@ module attributes { dlti.map = #dlti.map<"MPI:Implementation" = "OpenMPI"> } { // CHECK: [[v30:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v31:%.*]] = llvm.getelementptr [[v29]][[[v30]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v32:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v33:%.*]] = llvm.trunc [[v32]] : i64 to i32 + // CHECK: [[v33a:%.*]] = llvm.trunc [[v32]] : i64 to i32 + // CHECK: [[v33:%.*]] = llvm.mul [[v33a]] // CHECK: [[v34:%.*]] = llvm.mlir.addressof @ompi_mpi_float : !llvm.ptr // CHECK: [[v35:%.*]] = llvm.inttoptr [[comm]] : i64 to !llvm.ptr // CHECK: [[v36:%.*]] = llvm.mlir.constant(0 : i64) : i64 @@ -196,7 +206,8 @@ module attributes { dlti.map = #dlti.map<"MPI:Implementation" = "OpenMPI"> } { // CHECK: [[v40:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v41:%.*]] = llvm.getelementptr [[v39]][[[v40]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v42:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v43:%.*]] = llvm.trunc [[v42]] : i64 to i32 + // CHECK: [[v43a:%.*]] = llvm.trunc [[v42]] : i64 to i32 + // CHECK: [[v43:%.*]] = llvm.mul [[v43a]] // CHECK: [[v44:%.*]] = llvm.mlir.addressof @ompi_mpi_float : !llvm.ptr // CHECK: [[v45:%.*]] = llvm.inttoptr [[comm]] : i64 to !llvm.ptr // CHECK: [[v46:%.*]] = llvm.mlir.constant(0 : i64) : i64 @@ -204,7 +215,7 @@ module attributes { dlti.map = #dlti.map<"MPI:Implementation" = "OpenMPI"> } { // CHECK: [[v48:%.*]] = llvm.call @MPI_Recv([[v41]], [[v43]], [[v44]], [[v12]], [[v12]], [[v45]], [[v47]]) : (!llvm.ptr, i32, !llvm.ptr, i32, i32, !llvm.ptr, !llvm.ptr) -> i32 %2 = mpi.recv(%arg0, %rank, %rank, %comm) : memref<100xf32>, i32, i32 -> !mpi.retval - // CHECK: llvm.call @MPI_Comm_Size({{.*}}) : (!llvm.ptr, !llvm.ptr) -> i32 + // CHECK: llvm.call @MPI_Comm_size({{.*}}) : (!llvm.ptr, !llvm.ptr) -> i32 // CHECK: llvm.udiv {{.*}} : i32 // CHECK: llvm.call @MPI_Allgather({{.*}} : (!llvm.ptr, i32, !llvm.ptr, !llvm.ptr, i32, !llvm.ptr, !llvm.ptr) -> i32 mpi.allgather(%arg0, %arg0, %comm) : memref<100xf32>, memref<100xf32> @@ -213,12 +224,14 @@ module attributes { dlti.map = #dlti.map<"MPI:Implementation" = "OpenMPI"> } { // CHECK: [[v50:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v51:%.*]] = llvm.getelementptr [[v49]][[[v50]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v52:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v53:%.*]] = llvm.trunc [[v52]] : i64 to i32 + // CHECK: [[v53a:%.*]] = llvm.trunc [[v52]] : i64 to i32 + // CHECK: [[v53:%.*]] = llvm.mul [[v53a]] // CHECK: [[v54:%.*]] = llvm.extractvalue [[v5]][1] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v55:%.*]] = llvm.extractvalue [[v5]][2] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> // CHECK: [[v56:%.*]] = llvm.getelementptr [[v54]][[[v55]]] : (!llvm.ptr, i64) -> !llvm.ptr, f32 // CHECK: [[v57:%.*]] = llvm.extractvalue [[v5]][3, 0] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> - // CHECK: [[v58:%.*]] = llvm.trunc [[v57]] : i64 to i32 + // CHECK: [[v58a:%.*]] = llvm.trunc [[v57]] : i64 to i32 + // CHECK: [[v58:%.*]] = llvm.mul [[v58a]] // CHECK: [[ip:%.*]] = llvm.mlir.constant(1 : i64) : i64 // CHECK: [[ipp:%.*]] = llvm.inttoptr [[ip]] : i64 to !llvm.ptr // CHECK: [[v59:%.*]] = llvm.mlir.addressof @ompi_mpi_float : !llvm.ptr @@ -244,3 +257,18 @@ module attributes { dlti.map = #dlti.map<"MPI:Implementation" = "OpenMPI"> } { return } } + +// ----- + +module attributes {mpi.dlti = #dlti.map<"MPI:Implementation" = "MPICH", "MPI:comm_world_size" = 4, "MPI:comm_world_rank" = 1> } { + // CHECK: llvm.func @mpi_test_fold + func.func @mpi_test_fold(%arg0: memref<100xf32>) { + // CHECK: [[comm:%.*]] = llvm.mlir.constant(1140850688 : i64) : i64 + %comm = mpi.comm_world : !mpi.comm + + // CHECK-NOT: llvm.call @MPI_Comm_size + // CHECK: llvm.call @MPI_Allgather({{.*}} : (!llvm.ptr, i32, i32, !llvm.ptr, i32, i32, i32) -> i32 + %err3 = mpi.allgather(%arg0, %arg0, %comm) : memref<100xf32>, memref<100xf32> -> !mpi.retval + return + } +} diff --git a/mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir b/mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir index 9a8ad5eea1c7b..4ac4a69dd5b18 100644 --- a/mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir +++ b/mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir @@ -155,14 +155,28 @@ module attributes { mpi.dlti = #dlti.map<"MPI:comm_world_rank" = 7> } { %arg0 : tensor<3x4xf32>) -> tensor<3x20xf32> { // CHECK-DAG: [[vc2_i32:%.*]] = arith.constant 2 : i32 // CHECK-DAG: [[vc1_i32:%.*]] = arith.constant 1 : i32 + // CHECK-DAG: [[vc20:%.*]] = arith.constant 20 : index // CHECK: [[v0:%.*]] = bufferization.to_buffer [[varg0]] : tensor<3x4xf32> to memref<3x4xf32> // CHECK: [[v1:%.*]] = mpi.comm_world : !mpi.comm // CHECK: [[vnewcomm:%.*]] = mpi.comm_split([[v1]], [[vc1_i32]], [[vc2_i32]]) : !mpi.comm - // CHECK: [[valloc:%.*]] = memref.alloc() : memref<3x20xf32> - // CHECK: mpi.allgather([[v0]], [[valloc]], [[vnewcomm]]) : memref<3x4xf32>, memref<3x20xf32> - // CHECK: [[v2:%.*]] = bufferization.to_tensor [[valloc]] restrict : memref<3x20xf32> to tensor<3x20xf32> + // CHECK: [[vsize:%.*]] = mpi.comm_size([[vnewcomm]]) : i32 + // CHECK: [[v2:%.*]] = arith.index_cast [[vsize]] : i32 to index + // CHECK: [[v3:%.*]] = arith.divsi [[vc20]], [[v2]] : index + // CHECK: [[valloc:%.*]] = memref.alloc([[v2]], [[v3]]) : memref + // CHECK: mpi.allgather([[v0]], [[valloc]], [[vnewcomm]]) : memref<3x4xf32>, memref + // CHECK: [[valloc_0:%.*]] = memref.alloc() : memref<3x20xf32> + // CHECK: affine.for [[varg1:%.*]] = 0 to [[v2]] { + // CHECK: affine.for [[varg2:%.*]] = 0 to 3 { + // CHECK: affine.for [[varg3:%.*]] = 0 to [[v3]] { + // CHECK: [[v5:%.*]] = memref.load [[valloc]][[[varg1]], [[varg2]], [[varg3]]] : memref + // CHECK: affine.store [[v5]], [[valloc_0]][[[varg2]], [[varg1]] * symbol([[v3]]) + [[varg3]]] : memref<3x20xf32> + // CHECK: } + // CHECK: } + // CHECK: } + // CHECK: memref.dealloc [[valloc]] : memref + // CHECK: [[v4:%.*]] = bufferization.to_tensor [[valloc_0]] restrict : memref<3x20xf32> to tensor<3x20xf32> %0 = shard.all_gather %arg0 on @grid0 grid_axes = [2] gather_axis = 1 : tensor<3x4xf32> -> tensor<3x20xf32> - // CHECK: return [[v2]] : tensor<3x20xf32> + // CHECK: return [[v4]] : tensor<3x20xf32> return %0 : tensor<3x20xf32> } @@ -173,12 +187,26 @@ module attributes { mpi.dlti = #dlti.map<"MPI:comm_world_rank" = 7> } { %arg0 : memref<3x4xf32>) -> memref<3x20xf32> { // CHECK-DAG: [[vc1_i32:%.*]] = arith.constant 1 : i32 // CHECK-DAG: [[vc2_i32:%.*]] = arith.constant 2 : i32 + // CHECK-DAG: [[vc20:%.*]] = arith.constant 20 : index // CHECK: [[v0:%.*]] = mpi.comm_world : !mpi.comm // CHECK: [[vnewcomm:%.*]] = mpi.comm_split([[v0]], [[vc1_i32]], [[vc2_i32]]) : !mpi.comm - // CHECK: [[valloc:%.*]] = memref.alloc() : memref<3x20xf32> - // CHECK: mpi.allgather([[varg0]], [[valloc]], [[vnewcomm]]) : memref<3x4xf32>, memref<3x20xf32> + // CHECK: [[vsize:%.*]] = mpi.comm_size([[vnewcomm]]) : i32 + // CHECK: [[v1:%.*]] = arith.index_cast [[vsize]] : i32 to index + // CHECK: [[v2:%.*]] = arith.divsi [[vc20]], [[v1]] : index + // CHECK: [[valloc:%.*]] = memref.alloc([[v1]], [[v2]]) : memref + // CHECK: mpi.allgather([[varg0]], [[valloc]], [[vnewcomm]]) : memref<3x4xf32>, memref + // CHECK: [[valloc_0:%.*]] = memref.alloc() : memref<3x20xf32> + // CHECK: affine.for [[varg1:%.*]] = 0 to [[v1]] { + // CHECK: affine.for [[varg2:%.*]] = 0 to 3 { + // CHECK: affine.for [[varg3:%.*]] = 0 to [[v2]] { + // CHECK: [[v3:%.*]] = memref.load [[valloc]][[[varg1]], [[varg2]], [[varg3]]] : memref + // CHECK: affine.store [[v3]], [[valloc_0]][[[varg2]], [[varg1]] * symbol([[v2]]) + [[varg3]]] : memref<3x20xf32> + // CHECK: } + // CHECK: } + // CHECK: } + // CHECK: memref.dealloc [[valloc]] : memref %0 = shard.all_gather %arg0 on @grid0 grid_axes = [2] gather_axis = 1 : memref<3x4xf32> -> memref<3x20xf32> - // CHECK: return [[valloc]] : memref<3x20xf32> + // CHECK: return [[valloc_0]] : memref<3x20xf32> return %0 : memref<3x20xf32> } } @@ -410,3 +438,61 @@ func.func @return_sharding_offs(%arg0: tensor) -> (tensor, !sh // CHECK: return [[varg0]], [[vcast]], [[vcast_6]], [[vcast_7]] : tensor, tensor, tensor, tensor return %arg0, %sharding : tensor, !shard.sharding } + +// ----- +shard.grid @grid_1d_4(shape = 4) +// CHECK-LABEL: func.func @mlp_1dgrid( +// CHECK-SAME: [[varg0:%.*]]: tensor<512x512xf32>, [[varg1:%.*]]: tensor<2048x256xf32>, [[varg2:%.*]]: tensor<256x2048xf32>) -> tensor<512x2048xf32> +func.func @mlp_1dgrid(%arg0: tensor<512x512xf32>, %arg1: tensor<2048x256xf32>, %arg2: tensor<256x2048xf32>) -> tensor<512x2048xf32> attributes {llvm.emit_c_interface} { + // CHECK: [[vcst:%.*]] = arith.constant 0.000000e+00 : f32 + %cst = arith.constant 0.000000e+00 : f32 + %c0 = arith.constant 0 : index + // CHECK: [[v0:%.*]] = bufferization.to_buffer [[varg0]] : tensor<512x512xf32> to memref<512x512xf32> + // CHECK: [[v1:%.*]] = mpi.comm_world : !mpi.comm + // CHECK: [[vsize:%.*]] = mpi.comm_size + // CHECK: [[v2:%.*]] = arith.index_cast [[vsize]] : i32 to index + // CHECK: [[v3:%.*]] = arith.divsi + // CHECK: [[valloc:%.*]] = memref.alloc([[v2]], [[v3]]) : memref + // CHECK: mpi.allgather([[v0]], [[valloc]], [[v1]]) : memref<512x512xf32>, memref + // CHECK: [[valloc_0:%.*]] = memref.alloc() : memref<512x2048xf32> + // CHECK: affine.for [[varg3:%.*]] = 0 to [[v2]] { + // CHECK: affine.for [[varg4:%.*]] = 0 to 512 { + // CHECK: affine.for [[varg5:%.*]] = 0 to [[v3]] { + // CHECK: [[v19:%.*]] = memref.load [[valloc]][[[varg3]], [[varg4]], [[varg5]]] : memref + // CHECK: affine.store [[v19]], [[valloc_0]][[[varg4]], [[varg3]] * symbol([[v3]]) + [[varg5]]] : memref<512x2048xf32> + // CHECK: memref.dealloc [[valloc]] : memref + // CHECK: [[v4:%.*]] = bufferization.to_tensor [[valloc_0]] restrict : memref<512x2048xf32> to tensor<512x2048xf32> + %all_gather = shard.all_gather %arg0 on @grid_1d_4 grid_axes = [0] gather_axis = 1 : tensor<512x512xf32> -> tensor<512x2048xf32> + // CHECK: [[v5:%.*]] = tensor.empty() : tensor<512x256xf32> + %0 = tensor.empty() : tensor<512x256xf32> + // CHECK: [[v6:%.*]] = linalg.fill ins([[vcst]] : f32) outs([[v5]] : tensor<512x256xf32>) -> tensor<512x256xf32> + %1 = linalg.fill ins(%cst : f32) outs(%0 : tensor<512x256xf32>) -> tensor<512x256xf32> + // CHECK: [[v7:%.*]] = linalg.matmul ins([[v4]], [[varg1]] : tensor<512x2048xf32>, tensor<2048x256xf32>) outs([[v6]] : tensor<512x256xf32>) -> tensor<512x256xf32> + %2 = linalg.matmul ins(%all_gather, %arg1 : tensor<512x2048xf32>, tensor<2048x256xf32>) outs(%1 : tensor<512x256xf32>) -> tensor<512x256xf32> + // CHECK: [[v8:%.*]] = tosa.sigmoid [[v7]] : (tensor<512x256xf32>) -> tensor<512x256xf32> + %3 = tosa.sigmoid %2 : (tensor<512x256xf32>) -> tensor<512x256xf32> + %4 = tensor.empty() : tensor<512x2048xf32> + %5 = linalg.fill ins(%cst : f32) outs(%4 : tensor<512x2048xf32>) -> tensor<512x2048xf32> + %proc_linear_idx = shard.process_multi_index on @grid_1d_4 axes = [0] : index + %grid_shape = shard.grid_shape @grid_1d_4 axes = [0] : index + %6 = arith.cmpi eq, %proc_linear_idx, %c0 : index + // CHECK: [[v14:%.*]] = scf.if + %7 = scf.if %6 -> (tensor<512x2048xf32>) { + scf.yield %5 : tensor<512x2048xf32> + } else { + %9 = tensor.empty() : tensor<512x2048xf32> + %10 = linalg.fill ins(%cst : f32) outs(%9 : tensor<512x2048xf32>) -> tensor<512x2048xf32> + scf.yield %10 : tensor<512x2048xf32> + } + // CHECK: [[v15:%.*]] = linalg.matmul ins([[v8]], [[varg2]] : tensor<512x256xf32>, tensor<256x2048xf32>) outs([[v14]] : tensor<512x2048xf32>) -> tensor<512x2048xf32> + %8 = linalg.matmul ins(%3, %arg2 : tensor<512x256xf32>, tensor<256x2048xf32>) outs(%7 : tensor<512x2048xf32>) -> tensor<512x2048xf32> + // CHECK: [[v16:%.*]] = bufferization.to_buffer + // CHECK: [[valloc_1:%.*]] = memref.alloc() : memref<512x2048xf32> + // CHECK: linalg.copy ins([[v16]] : memref<512x2048xf32>) outs([[valloc_1]] : memref<512x2048xf32>) + // CHECK: [[v17:%.*]] = mpi.comm_world : !mpi.comm + // CHECK: mpi.allreduce([[valloc_1]], [[valloc_1]], MPI_SUM, [[v17]]) : memref<512x2048xf32>, memref<512x2048xf32> + // CHECK: [[v18:%.*]] = bufferization.to_tensor [[valloc_1]] restrict : memref<512x2048xf32> to tensor<512x2048xf32> + %all_reduce = shard.all_reduce %8 on @grid_1d_4 grid_axes = [0] : tensor<512x2048xf32> -> tensor<512x2048xf32> + // CHECK: return [[v18]] : tensor<512x2048xf32> + return %all_reduce : tensor<512x2048xf32> +} diff --git a/mlir/test/Conversion/VectorToGPU/vector-to-mma-ops.mlir b/mlir/test/Conversion/VectorToGPU/vector-to-mma-ops.mlir index ef72901750479..bf858789c7e07 100644 --- a/mlir/test/Conversion/VectorToGPU/vector-to-mma-ops.mlir +++ b/mlir/test/Conversion/VectorToGPU/vector-to-mma-ops.mlir @@ -1,5 +1,21 @@ // RUN: mlir-opt %s -pass-pipeline="builtin.module(func.func(convert-vector-to-gpu),canonicalize)" --split-input-file | FileCheck %s +// ----- + +// The pass currently only works for 2D vector transfers. +// CHECK-LABEL: func @no_convert_3d +// CHECK-NOT: gpu +func.func @no_convert_3d(%arg0: memref<2x2x2xf16>) { + %c0 = arith.constant 0 : index + %cst = arith.constant 0.0 : f16 + %A = vector.transfer_read %arg0[%c0, %c0, %c0], %cst {in_bounds = [true, true, true]} : memref<2x2x2xf16>, vector<2x2x2xf16> + %B = arith.addf %A, %A : vector<2x2x2xf16> + vector.transfer_write %B, %arg0[%c0, %c0, %c0] {in_bounds = [true, true, true]} : vector<2x2x2xf16>, memref<2x2x2xf16> + return +} + +// ----- + #map0 = affine_map<(d0, d1) -> (d1, d0)> #map1 = affine_map<(d0, d1, d2) -> (d0, d2)> #map2 = affine_map<(d0, d1, d2) -> (d1, d2)> @@ -555,3 +571,94 @@ func.func @addf(%arg0: memref<16x16xf16>, %arg1: memref<16x16xf16>, %arg2: memre vector.transfer_write %C, %arg2[%c0, %c0] {in_bounds = [true, true]} : vector<16x16xf16>, memref<16x16xf16> return } + +// ----- + +// CHECK-LABEL: func @matmul_with_strides +// CHECK-DAG: %[[A:.+]] = gpu.subgroup_mma_load_matrix %{{.*}}[%{{.*}}, %{{.*}}] {leadDimension = 16 : index} : memref<16x16xf16> -> !gpu.mma_matrix<16x16xf16, "AOp"> +// CHECK-DAG: %[[B:.+]] = gpu.subgroup_mma_load_matrix %{{.*}}[%{{.*}}, %{{.*}}, %{{.*}}] {leadDimension = 96 : index} : memref<16x6x16xf16> -> !gpu.mma_matrix<16x16xf16, "BOp"> +// CHECK-DAG: %[[C:.+]] = gpu.subgroup_mma_load_matrix %{{.*}}[%{{.*}}, %{{.*}}] {leadDimension = 144 : index} : memref<16x9x16xf16> -> !gpu.mma_matrix<16x16xf16, "COp"> +// CHECK: %[[D:.+]] = gpu.subgroup_mma_compute %[[A]], %[[B]], %[[C]] : !gpu.mma_matrix<16x16xf16, "AOp">, !gpu.mma_matrix<16x16xf16, "BOp"> -> !gpu.mma_matrix<16x16xf16, "COp"> +// CHECK: gpu.subgroup_mma_store_matrix %[[D]], %{{.*}}[%{{.*}}, %{{.*}}, %{{.*}}] {leadDimension = 144 : index} : !gpu.mma_matrix<16x16xf16, "COp">, memref<16x9x16xf16> +func.func @matmul_with_strides(%arg0: memref<16x16xf16>, %arg1: memref<16x6x16xf16>, %arg2: memref<16x9x16xf16>) { + %cst_0 = arith.constant dense<0.000000e+00> : vector<16x16xf16> + %c0 = arith.constant 0 : index + %cst = arith.constant 0.000000e+00 : f16 + %A = vector.transfer_read %arg0[%c0, %c0], %cst {in_bounds = [true, true]} : memref<16x16xf16>, vector<16x16xf16> + %B = vector.transfer_read %arg1[%c0, %c0, %c0], %cst {permutation_map = affine_map<(d0, d1, d2) -> (d0, d2)>, in_bounds = [true, true]} : memref<16x6x16xf16>, vector<16x16xf16> + %C = vector.transfer_read %arg2[%c0, %c0, %c0], %cst {in_bounds = [true, true], permutation_map = affine_map<(d0, d1, d2) -> (d0, d2)>} : memref<16x9x16xf16>, vector<16x16xf16> + %D = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d2, d1)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind} %A, %B, %C : vector<16x16xf16>, vector<16x16xf16> into vector<16x16xf16> + vector.transfer_write %D, %arg2[%c0, %c0, %c0] {in_bounds = [true, true], permutation_map = affine_map<(d0, d1, d2) -> (d0, d2)>} : vector<16x16xf16>, memref<16x9x16xf16> + return +} + +// ----- + +// CHECK-LABEL: func @read_transpose_with_strides_3d +func.func @read_transpose_with_strides_3d(%arg0: memref<5x7x3xf16>, %arg1: memref<2x5x3xf16>, %arg2: memref<3x5xf16>) { + %c0 = arith.constant 0 : index + %cst = arith.constant 0.0 : f16 + // CHECK: gpu.subgroup_mma_load_matrix %{{.*}} {leadDimension = 21 : index, transpose} : memref<5x7x3xf16> -> !gpu.mma_matrix<3x5xf16, "COp"> + %A = vector.transfer_read %arg0[%c0, %c0, %c0], %cst {in_bounds = [true, true], permutation_map = affine_map<(d0, d1, d2) -> (d2, d0)>} : memref<5x7x3xf16>, vector<3x5xf16> + // CHECK: gpu.subgroup_mma_load_matrix %{{.*}} {leadDimension = 3 : index, transpose} : memref<2x5x3xf16> -> !gpu.mma_matrix<3x5xf16, "COp"> + %B = vector.transfer_read %arg1[%c0, %c0, %c0], %cst {in_bounds = [true, true], permutation_map = affine_map<(d0, d1, d2) -> (d2, d1)>} : memref<2x5x3xf16>, vector<3x5xf16> + %C = arith.addf %A, %B : vector<3x5xf16> + vector.transfer_write %C, %arg2[%c0, %c0] {in_bounds = [true, true]} : vector<3x5xf16>, memref<3x5xf16> + return +} + +// ----- + +// CHECK-LABEL: func @read_transpose_with_strides_4d +func.func @read_transpose_with_strides_4d(%arg0: memref<5x7x11x3xf16>, %arg1: memref<2x5x11x3xf16>, %arg2: memref<3x5xf16>) { + %c0 = arith.constant 0 : index + %cst = arith.constant 0.0 : f16 + // CHECK: gpu.subgroup_mma_load_matrix %{{.*}} {leadDimension = 231 : index, transpose} : memref<5x7x11x3xf16> -> !gpu.mma_matrix<3x5xf16, "COp"> + %A = vector.transfer_read %arg0[%c0, %c0, %c0, %c0], %cst {in_bounds = [true, true], permutation_map = affine_map<(d0, d1, d2, d3) -> (d3, d0)>} : memref<5x7x11x3xf16>, vector<3x5xf16> + // CHECK: gpu.subgroup_mma_load_matrix %{{.*}} {leadDimension = 33 : index, transpose} : memref<2x5x11x3xf16> -> !gpu.mma_matrix<3x5xf16, "COp"> + %B = vector.transfer_read %arg1[%c0, %c0, %c0, %c0], %cst {in_bounds = [true, true], permutation_map = affine_map<(d0, d1, d2, d3) -> (d3, d1)>} : memref<2x5x11x3xf16>, vector<3x5xf16> + %C = arith.addf %A, %B : vector<3x5xf16> + vector.transfer_write %C, %arg2[%c0, %c0] {in_bounds = [true, true]} : vector<3x5xf16>, memref<3x5xf16> + return +} + +// ----- + +// CHECK-LABEL: func @no_convert_read_transpose_not_last_dim +// CHECK-NOT: gpu +func.func @no_convert_read_transpose_not_last_dim(%arg0: memref<2x2x2xf16>, %arg1: memref<2x2xf16>) { + %c0 = arith.constant 0 : index + %cst = arith.constant 0.0 : f16 + // Legal map, but does not map the last memref dim so should not be lowered to an MMA load. + %A = vector.transfer_read %arg0[%c0, %c0, %c0], %cst {in_bounds = [true, true], permutation_map = affine_map<(d0, d1, d2) -> (d1, d0)>} : memref<2x2x2xf16>, vector<2x2xf16> + %B = arith.addf %A, %A : vector<2x2xf16> + vector.transfer_write %B, %arg1[%c0, %c0] {in_bounds = [true, true]} : vector<2x2xf16>, memref<2x2xf16> + return +} + +// ----- + +// Transpose write is not supported. +// CHECK-LABEL: func @no_convert_write_transpose +// CHECK-NOT: gpu +func.func @no_convert_write_transpose(%arg0: memref<2x2xf16>) { + %c0 = arith.constant 0 : index + %cst = arith.constant 0.0 : f16 + %A = vector.transfer_read %arg0[%c0, %c0], %cst {in_bounds = [true, true]} : memref<2x2xf16>, vector<2x2xf16> + %B = arith.addf %A, %A : vector<2x2xf16> + vector.transfer_write %B, %arg0[%c0, %c0] {in_bounds = [true, true], permutation_map = affine_map<(d0, d1) -> (d1, d0)>} : vector<2x2xf16>, memref<2x2xf16> + return +} + +// ----- + +// CHECK-LABEL: func @read_transpose_with_broadcast_3d +func.func @read_transpose_with_broadcast_3d(%arg0: memref<2x2x2xf16>, %arg1: memref<2x2xf16>) { + %c0 = arith.constant 0 : index + %cst = arith.constant 0.0 : f16 + // CHECK: gpu.subgroup_mma_load_matrix %{{.*}} {leadDimension = 0 : index, transpose} : memref<2x2x2xf16> -> !gpu.mma_matrix<2x2xf16, "COp"> + %A = vector.transfer_read %arg0[%c0, %c0, %c0], %cst {in_bounds = [true, true], permutation_map = affine_map<(d0, d1, d2) -> (d2, 0)>} : memref<2x2x2xf16>, vector<2x2xf16> + %B = arith.addf %A, %A : vector<2x2xf16> + vector.transfer_write %B, %arg1[%c0, %c0] {in_bounds = [true, true]} : vector<2x2xf16>, memref<2x2xf16> + return +} diff --git a/mlir/test/Conversion/XeGPUToXeVM/materializecast.mlir b/mlir/test/Conversion/XeGPUToXeVM/materializecast.mlir index 2a2b99f57cabd..969c369cd17e8 100644 --- a/mlir/test/Conversion/XeGPUToXeVM/materializecast.mlir +++ b/mlir/test/Conversion/XeGPUToXeVM/materializecast.mlir @@ -61,3 +61,32 @@ gpu.module @materializecast { } } +// ----- +gpu.module @materializecast [#xevm.target]{ + // CHECK-LABEL: gpu.func @materialize_element_to_2D_single_element_vector + gpu.func @materialize_element_to_2D_single_element_vector(%dst: memref<128xf32>) kernel { + %c0 = arith.constant 0 : index + %alloca_11 = memref.alloca() : memref<512xi8, 3> + %49 = xegpu.create_mem_desc %alloca_11 : memref<512xi8, 3> -> !xegpu.mem_desc<8x16xf32> + // CHECK: %[[LOAD:.*]] = llvm.load %{{.+}} : !llvm.ptr<3> -> f32 + // CHECK: %[[BCST:.*]] = vector.broadcast %[[LOAD]] : f32 to vector<1x1xf32> + %50 = xegpu.load_matrix %49[%c0, %c0] : !xegpu.mem_desc<8x16xf32>, index, index -> vector<1x1xf32> + %51 = vector.shape_cast %50 : vector<1x1xf32> to vector<1xf32> + vector.store %51, %dst[%c0] : memref<128xf32>, vector<1xf32> + gpu.return + } +} + +// ----- +gpu.module @materializecast [#xevm.target]{ + // CHECK-LABEL: gpu.func @materialize_2D_single_element_vector_to_element + gpu.func @materialize_2D_single_element_vector_to_element(%dst: memref<512xi8, 3>) kernel { + %c0 = arith.constant 0 : index + %c0_f32 = arith.constant dense<0.0> : vector<1x1xf32> + %49 = xegpu.create_mem_desc %dst : memref<512xi8, 3> -> !xegpu.mem_desc<8x16xf32> + // CHECK: %[[EXTR:.*]] = vector.extract %{{.+}}[0, 0] : f32 from vector<1x1xf32> + // CHECK: llvm.store %[[EXTR]], %{{.+}} : f32, !llvm.ptr<3> + xegpu.store_matrix %c0_f32, %49[%c0, %c0] : vector<1x1xf32>, !xegpu.mem_desc<8x16xf32>, index, index + gpu.return + } +} diff --git a/mlir/test/Conversion/XeVMToLLVM/legalize_large_vector.mlir b/mlir/test/Conversion/XeVMToLLVM/legalize_large_vector.mlir new file mode 100644 index 0000000000000..150f6dba5cbaa --- /dev/null +++ b/mlir/test/Conversion/XeVMToLLVM/legalize_large_vector.mlir @@ -0,0 +1,51 @@ +// RUN: mlir-opt --convert-xevm-to-llvm --split-input-file %s | FileCheck %s + +module @test_illegal_vector { + // CHECK-LABEL: llvm.func @test_illegal_vector + // CHECK: %[[ARG0:.*]]: !llvm.ptr, %[[ARG1:.*]]: !llvm.ptr, %[[ARG2:.*]]: !llvm.ptr, %[[ARG3:.*]]: !llvm.ptr, %[[ARG4:.*]]: !llvm.ptr + llvm.func @test_illegal_vector(%arg0: !llvm.ptr, %arg1: !llvm.ptr, %arg2: !llvm.ptr, %arg3: !llvm.ptr, %arg4: !llvm.ptr) { + // CHECK: %[[LOAD0:.*]] = llvm.load %[[ARG0]] : !llvm.ptr -> vector<8xi16> + // CHECK: %[[BITCAST0:.*]] = llvm.bitcast %[[LOAD0]] : vector<8xi16> to vector<8xf16> + // CHECK: %[[FPEXT0:.*]] = llvm.fpext %[[BITCAST0]] : vector<8xf16> to vector<8xf32> + // CHECK: %[[GEP0:.*]] = llvm.getelementptr %[[ARG0]][8] : (!llvm.ptr) -> !llvm.ptr, i16 + // CHECK: %[[LOAD1:.*]] = llvm.load %[[GEP0]] : !llvm.ptr -> vector<8xi16> + // CHECK: %[[BITCAST1:.*]] = llvm.bitcast %[[LOAD1]] : vector<8xi16> to vector<8xf16> + // CHECK: %[[FPEXT1:.*]] = llvm.fpext %[[BITCAST1]] : vector<8xf16> to vector<8xf32> + // CHECK: %[[BITCAST2:.*]] = llvm.bitcast %[[FPEXT0]] : vector<8xf32> to vector<8xi32> + // CHECK: llvm.store %[[BITCAST2]], %[[ARG1]] : vector<8xi32>, !llvm.ptr + // CHECK: %[[BITCAST3:.*]] = llvm.bitcast %[[FPEXT1]] : vector<8xf32> to vector<8xi32> + // CHECK: llvm.store %[[BITCAST3]], %[[ARG2]] : vector<8xi32>, !llvm.ptr + // CHECK: %[[GEP1:.*]] = llvm.getelementptr %[[ARG0]][16] : (!llvm.ptr) -> !llvm.ptr, i16 + // CHECK: %[[LOAD2:.*]] = llvm.load %[[GEP1]] : !llvm.ptr -> vector<8xi16> + // CHECK: %[[BITCAST4:.*]] = llvm.bitcast %[[LOAD2]] : vector<8xi16> to vector<8xf16> + // CHECK: %[[FPEXT2:.*]] = llvm.fpext %[[BITCAST4]] : vector<8xf16> to vector<8xf32> + // CHECK: %[[GEP2:.*]] = llvm.getelementptr %[[ARG0]][24] : (!llvm.ptr) -> !llvm.ptr, i16 + // CHECK: %[[LOAD3:.*]] = llvm.load %[[GEP2]] : !llvm.ptr -> vector<8xi16> + // CHECK: %[[BITCAST5:.*]] = llvm.bitcast %[[LOAD3]] : vector<8xi16> to vector<8xf16> + // CHECK: %[[FPEXT3:.*]] = llvm.fpext %[[BITCAST5]] : vector<8xf16> to vector<8xf32> + // CHECK: %[[BITCAST6:.*]] = llvm.bitcast %[[FPEXT2]] : vector<8xf32> to vector<8xi32> + // CHECK: llvm.store %[[BITCAST6]], %[[ARG3]] : vector<8xi32>, !llvm.ptr + // CHECK: %[[BITCAST7:.*]] = llvm.bitcast %[[FPEXT3]] : vector<8xf32> to vector<8xi32> + // CHECK: llvm.store %[[BITCAST7]], %[[ARG4]] : vector<8xi32>, !llvm.ptr + // CHECK: llvm.return + %0 = llvm.load %arg0 : !llvm.ptr -> vector<32xi16> + %1 = llvm.bitcast %0 : vector<32xi16> to vector<32xf16> + %2 = llvm.shufflevector %1, %1 [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] : vector<32xf16> + %3 = llvm.shufflevector %1, %1 [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31] : vector<32xf16> + %4 = llvm.fpext %2 : vector<16xf16> to vector<16xf32> + %5 = llvm.fpext %3 : vector<16xf16> to vector<16xf32> + %6 = llvm.shufflevector %4, %4 [0, 1, 2, 3, 4, 5, 6, 7] : vector<16xf32> + %7 = llvm.shufflevector %4, %4 [8, 9, 10, 11, 12, 13, 14, 15] : vector<16xf32> + %8 = llvm.bitcast %6 : vector<8xf32> to vector<8xi32> + llvm.store %8, %arg1 : vector<8xi32>, !llvm.ptr + %9 = llvm.bitcast %7 : vector<8xf32> to vector<8xi32> + llvm.store %9, %arg2 : vector<8xi32>, !llvm.ptr + %10 = llvm.shufflevector %5, %5 [0, 1, 2, 3, 4, 5, 6, 7] : vector<16xf32> + %11 = llvm.shufflevector %5, %5 [8, 9, 10, 11, 12, 13, 14, 15] : vector<16xf32> + %12 = llvm.bitcast %10 : vector<8xf32> to vector<8xi32> + llvm.store %12, %arg3 : vector<8xi32>, !llvm.ptr + %13 = llvm.bitcast %11 : vector<8xf32> to vector<8xi32> + llvm.store %13, %arg4 : vector<8xi32>, !llvm.ptr + llvm.return + } +} diff --git a/mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir b/mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir index 7f01526cb0a06..06a0ff5e7484b 100644 --- a/mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir +++ b/mlir/test/Conversion/XeVMToLLVM/xevm-to-llvm.mlir @@ -1,21 +1,17 @@ // RUN: mlir-opt --convert-xevm-to-llvm --split-input-file %s | FileCheck %s -// Same below, but using the `ConvertToLLVMPatternInterface` entry point -// and the generic `convert-to-llvm` pass. -// RUN: mlir-opt --convert-to-llvm --split-input-file %s | FileCheck %s - // CHECK-LABEL: llvm.func spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt( // CHECK-SAME: !llvm.ptr<1> {llvm.nonnull, llvm.readonly}, i32, i32, i32, vector<2xi32>, // CHECK-SAME: !llvm.ptr {llvm.nonnull, llvm.writeonly}) attributes {no_unwind, will_return} // CHECK: llvm.func @blockload2d(%[[ARG0:.*]]: !llvm.ptr<1>, // CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32) llvm.func @blockload2d(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<8xi16> { + // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32> // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i32 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32> // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32> - // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i16 : (i32) -> !llvm.ptr // CHECK: llvm.call spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x1cPU3AS1viiiDv2_iPt( // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]]) @@ -51,12 +47,12 @@ llvm.func @blockload2d_cache_control(%a: !llvm.ptr<1>, %base_width_a: i32, %base // CHECK: llvm.func @blockload2d_v_blocks(%[[ARG0:.*]]: !llvm.ptr<1>, // CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32) llvm.func @blockload2d_v_blocks(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<16xi16> { + // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(16 : i32) : i32 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32> // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i32 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32> // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32> - // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(16 : i32) : i32 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i16 : (i32) -> !llvm.ptr // CHECK: llvm.call spir_funccc @_Z41intel_sub_group_2d_block_read_16b_8r16x2cPU3AS1viiiDv2_iPt( // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]]) @@ -80,12 +76,12 @@ llvm.func @blockload2d_v_blocks(%a: !llvm.ptr<1>, %base_width_a: i32, %base_heig // CHECK: llvm.func @blockload2d_pack_register(%[[ARG0:.*]]: !llvm.ptr<1>, // CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32) llvm.func @blockload2d_pack_register(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<8xi32> { + // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32> // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i32 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32> // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32> - // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i32 : (i32) -> !llvm.ptr // CHECK: llvm.call spir_funccc @_Z52intel_sub_group_2d_block_read_transform_16b_16r16x1cPU3AS1viiiDv2_iPj( // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]]) @@ -109,12 +105,12 @@ llvm.func @blockload2d_pack_register(%a: !llvm.ptr<1>, %base_width_a: i32, %base // CHECK: llvm.func @blockload2d_transpose(%[[ARG0:.*]]: !llvm.ptr<1>, // CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32) llvm.func @blockload2d_transpose(%a: !llvm.ptr<1>, %base_width_a: i32, %base_height_a: i32, %base_pitch_a: i32, %x: i32, %y: i32) -> vector<8xi32> { + // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32> // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i32 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32> // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32> - // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i32 : (i32) -> !llvm.ptr // CHECK: llvm.call spir_funccc @_Z51intel_sub_group_2d_block_read_transpose_32b_16r8x1cPU3AS1viiiDv2_iPj( // CHECK-SAME: %[[ARG0]], %[[ARG1]], %[[ARG2]], %[[ARG3]], %[[VAR4]], %[[VAR6]]) @@ -138,12 +134,12 @@ llvm.func @blockload2d_transpose(%a: !llvm.ptr<1>, %base_width_a: i32, %base_hei // CHECK: llvm.func @blockstore2d(%[[ARG0:.*]]: !llvm.ptr<1>, // CHECK-SAME: %[[ARG1:.*]]: i32, %[[ARG2:.*]]: i32, %[[ARG3:.*]]: i32, %[[ARG4:.*]]: i32, %[[ARG5:.*]]: i32, %[[ARG6:.*]]: vector<8xi32>) { llvm.func @blockstore2d(%c: !llvm.ptr<1>, %base_width_c: i32, %base_height_c: i32, %base_pitch_c: i32, %x: i32, %y: i32, %c_result_casted: vector<8xi32>) { + // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32 // CHECK: %[[VAR0:.*]] = llvm.mlir.undef : vector<2xi32> // CHECK: %[[VAR1:.*]] = llvm.mlir.constant(0 : i32) : i32 // CHECK: %[[VAR2:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[VAR3:.*]] = llvm.insertelement %[[ARG4]], %[[VAR0]][%[[VAR1]] : i32] : vector<2xi32> // CHECK: %[[VAR4:.*]] = llvm.insertelement %[[ARG5]], %[[VAR3]][%[[VAR2]] : i32] : vector<2xi32> - // CHECK: %[[VAR5:.*]] = llvm.mlir.constant(8 : i32) : i32 // CHECK: %[[VAR6:.*]] = llvm.alloca %[[VAR5]] x i32 : (i32) -> !llvm.ptr // CHECK: llvm.store %[[ARG6]], %[[VAR6]] : vector<8xi32>, !llvm.ptr // CHECK: llvm.call spir_funccc @_Z42intel_sub_group_2d_block_write_32b_8r16x1cPU3AS1viiiDv2_iPj( diff --git a/mlir/test/Dialect/AMDGPU/invalid.mlir b/mlir/test/Dialect/AMDGPU/invalid.mlir index 1299f3b14b14f..4429e4758f51c 100644 --- a/mlir/test/Dialect/AMDGPU/invalid.mlir +++ b/mlir/test/Dialect/AMDGPU/invalid.mlir @@ -516,3 +516,35 @@ func.func @sparse_mfma_wrong_dest_count(%a: vector<4xf16>, %b: vector<8xf16>, %c %d = amdgpu.sparse_mfma 16x16x32 %a * %b + %c sparse(%idx : vector<4xi8>) : vector<4xf16>, vector<8xf16>, vector<16xf32> func.return %d : vector<16xf32> } + +// ----- + +func.func @dpp_rejects_scalable(%a: vector<[16]x[16]xi8>, %b: vector<[16]x[16]xi8>) { + // expected-error @+1 {{fixed-length vector of integer or float with element bitwidth <= 64 values of ranks 1}} + %0 = amdgpu.dpp %a %b row_shl(1 : i32) : vector<[16]x[16]xi8> + func.return +} + +// ----- + +func.func @ds_barrier_init_non_workgroup(%barrier: memref, %participants: i32) { + // expected-error@+1 {{'amdgpu.ds_barrier_init' op barrier must be in workgroup (LDS) memory}} + amdgpu.ds_barrier_init %barrier[], %participants : memref, i32 + func.return +} + +// ----- + +func.func @ds_barrier_poll_state_non_workgroup(%barrier: memref>) -> !amdgpu.ds_barrier_state { + // expected-error@+1 {{'amdgpu.ds_barrier_poll_state' op barrier must be in workgroup (LDS) memory}} + %state = amdgpu.ds_barrier_poll_state %barrier[] : memref> -> !amdgpu.ds_barrier_state + func.return %state : !amdgpu.ds_barrier_state +} + +// ----- + +func.func @ds_barrier_arrive_non_workgroup(%barrier: memref>, %count: i64) -> !amdgpu.ds_barrier_state { + // expected-error@+1 {{'amdgpu.ds_barrier_arrive' op barrier must be in workgroup (LDS) memory}} + %old_state = amdgpu.ds_barrier_arrive %barrier[], %count : memref>, i64 -> !amdgpu.ds_barrier_state + func.return %old_state : !amdgpu.ds_barrier_state +} diff --git a/mlir/test/Dialect/AMDGPU/ops.mlir b/mlir/test/Dialect/AMDGPU/ops.mlir index 2b3234ef8510d..5011891ed39d2 100644 --- a/mlir/test/Dialect/AMDGPU/ops.mlir +++ b/mlir/test/Dialect/AMDGPU/ops.mlir @@ -801,3 +801,32 @@ func.func @wmma_scale(%fp8_src: vector<64xf8E4M3FN>, %fp6_alt_src: vector<64xf6E %5 = amdgpu.scaled_wmma 32x16x128 (%scale_vec4_e4m3 * %fp4_src_a) * (%scale_vec4_e4m3 * %fp4_src_b) + %dst1 {a_first_scale_lane = 0 : i32, b_first_scale_lane = 0 : i32} : vector<4xf8E4M3FN>, vector<128xf4E2M1FN>, vector<4xf8E4M3FN>, vector<64xf4E2M1FN>, vector<16xf32> func.return } + +// CHECK-LABEL: func.func @dpp_vector_src_does_not_assert +// CHECK: amdgpu.dpp +func.func @dpp_vector_src_does_not_assert(%tile: vector<256xi8>, %pop: vector<256xi8>) { + %r = amdgpu.dpp %pop %tile row_shl(1 : i32) : vector<256xi8> + func.return +} + +// CHECK-LABEL: func @ds_barrier_ops +// CHECK-SAME: ([[BARRIER:%.*]]: memref>, [[COUNT:%.*]]: i64, [[PARTICIPANTS:%.*]]: i32) +func.func @ds_barrier_ops(%barrier: memref>, %count: i64, %participants: i32) { + // CHECK: amdgpu.ds_barrier_init [[BARRIER]][], [[PARTICIPANTS]] : memref>, i32 + amdgpu.ds_barrier_init %barrier[], %participants : memref>, i32 + // CHECK: [[STATE:%.*]] = amdgpu.ds_barrier_poll_state [[BARRIER]][] : memref> -> !amdgpu.ds_barrier_state + %state = amdgpu.ds_barrier_poll_state %barrier[] : memref> -> !amdgpu.ds_barrier_state + // CHECK: amdgpu.ds_async_barrier_arrive [[BARRIER]][] : memref> + amdgpu.ds_async_barrier_arrive %barrier[] : memref> + // CHECK: [[OLD_STATE:%.*]] = amdgpu.ds_barrier_arrive [[BARRIER]][], [[COUNT]] : memref>, i64 -> !amdgpu.ds_barrier_state + %old_state = amdgpu.ds_barrier_arrive %barrier[], %count : memref>, i64 -> !amdgpu.ds_barrier_state + // CHECK: [[PHASE:%.*]] = amdgpu.ds_barrier_state_phase [[STATE]] : !amdgpu.ds_barrier_state -> i32 + %phase = amdgpu.ds_barrier_state_phase %state : !amdgpu.ds_barrier_state -> i32 + // CHECK: [[PENDING:%.*]] = amdgpu.ds_barrier_state_pending_count [[STATE]] : !amdgpu.ds_barrier_state -> i32 + %pending = amdgpu.ds_barrier_state_pending_count %state : !amdgpu.ds_barrier_state -> i32 + // CHECK: [[INIT:%.*]] = amdgpu.ds_barrier_state_init_count [[STATE]] : !amdgpu.ds_barrier_state -> i32 + %init = amdgpu.ds_barrier_state_init_count %state : !amdgpu.ds_barrier_state -> i32 + // CHECK: [[PARITY:%.*]] = amdgpu.ds_barrier_state_phase_parity [[STATE]] : !amdgpu.ds_barrier_state -> i1 + %parity = amdgpu.ds_barrier_state_phase_parity %state : !amdgpu.ds_barrier_state -> i1 + func.return +} diff --git a/mlir/test/Dialect/Arith/invalid.mlir b/mlir/test/Dialect/Arith/invalid.mlir index 2e3debcb263c0..70b23e56a712c 100644 --- a/mlir/test/Dialect/Arith/invalid.mlir +++ b/mlir/test/Dialect/Arith/invalid.mlir @@ -869,3 +869,11 @@ func.func @bitcast_index_1(%arg0 : index) -> i64 { %0 = arith.bitcast %arg0 : index to i64 return %0 : i64 } + +// ----- + +func.func @select_vector_condition_scalar_operands(%arg0: vector<1xi1>, %arg1: i32) { + // expected-error @+1 {{'arith.select' op failed to verify that condition is signless i1 or has matching shape}} + %0 = arith.select %arg0, %arg1, %arg1 : vector<1xi1>, i32 + return +} diff --git a/mlir/test/Dialect/Bufferization/Transforms/drop-equivalent-buffer-results.mlir b/mlir/test/Dialect/Bufferization/Transforms/drop-equivalent-buffer-results.mlir new file mode 100644 index 0000000000000..b20188af43bf5 --- /dev/null +++ b/mlir/test/Dialect/Bufferization/Transforms/drop-equivalent-buffer-results.mlir @@ -0,0 +1,106 @@ +// RUN: mlir-opt -drop-equivalent-buffer-results -split-input-file %s | FileCheck %s +// RUN: mlir-opt -drop-equivalent-buffer-results=modify-public-functions=1 -split-input-file %s | \ +// RUN: FileCheck %s --check-prefix=MODIFY-PUBLIC + + +// CHECK-LABEL: func private @single_buffer_return({{.*}}) { +// CHECK: return + +!type = memref> +func.func private @single_buffer_return(%buf: !type, %val: f32, %idx: index) -> !type { + memref.store %val, %buf[%idx] : !type + return %buf : !type +} + +// CHECK-LABEL: func @caller( +// CHECK-SAME: %[[BUF:.+]]: memref>, +// CHECK: call @single_buffer_return(%[[BUF]]{{.*}}-> () +// CHECK: %[[LOADED:.+]] = memref.load %[[BUF]] +// CHECK: return %[[LOADED]] + +func.func @caller(%buf: !type, %val: f32, %idx: index) -> f32 { + %0 = call @single_buffer_return(%buf, %val, %idx) : (!type, f32, index) -> (!type) + %1 = memref.load %0[%idx] : !type + return %1 : f32 +} + +// ----- + +// CHECK-LABEL: func private @multiple_buffer_returns({{.*}}) { +// CHECK: return + +!type = memref> +!type1 = memref +func.func private @multiple_buffer_returns( + %buf: !type, %buf1: !type1, %val: f32, %idx: index) -> (!type1, !type) { + memref.store %val, %buf[%idx] : !type + memref.store %val, %buf1[%idx, %idx] : !type1 + return %buf1, %buf : !type1, !type +} + +// ----- + +// CHECK-LABEL: func private @multiple_mixed_returns({{.*}}) -> i32 { +// CHECK: %[[CST:.+]] = arith.constant 1 : i32 +// CHECK: return %[[CST]] : i32 + +!type = memref> +!type1 = memref +func.func private @multiple_mixed_returns( + %buf: !type, %buf1: !type1, %val: f32, %idx: index) -> (!type1, i32, !type) { + memref.store %val, %buf[%idx] : !type + memref.store %val, %buf1[%idx, %idx] : !type1 + %cst = arith.constant 1 : i32 + return %buf1, %cst, %buf : !type1, i32, !type +} + +// ----- + +// Ensure public functions remain unchanged by default. +// CHECK-LABEL: func @public_function( +// CHECK-SAME: %[[BUF:.+]]: memref>, +// CHECK-SAME: ) -> memref> { +// CHECK: return %[[BUF]] + +// When explicitly requested, public functions can be modified. +// MODIFY-PUBLIC-LABEL: func @public_function( +// MODIFY-PUBLIC-SAME: %[[BUF:.+]]: memref>, +// MODIFY-PUBLIC-SAME: ) { +// MODIFY-PUBLIC: return + +!type = memref> +func.func @public_function( + %buf: !type, %val: f32, %idx: index) -> !type { + memref.store %val, %buf[%idx] : !type + return %buf : !type +} + +// CHECK-LABEL: func @caller( +// CHECK-SAME: %[[IN_BUF:.+]]: memref>, +// CHECK: %[[RET_VAL:.+]] = call @public_function(%[[IN_BUF]]{{.*}}-> memref +// CHECK: %[[LOADED:.+]] = memref.load %[[RET_VAL]] +// CHECK: return %[[LOADED]] + +// MODIFY-PUBLIC-LABEL: func @caller( +// MODIFY-PUBLIC-SAME: %[[IN_BUF:.+]]: memref>, +// MODIFY-PUBLIC: call @public_function(%[[IN_BUF]]{{.*}}-> () +// MODIFY-PUBLIC: %[[LOADED:.*]] = memref.load %[[IN_BUF]] +// MODIFY-PUBLIC: return %[[LOADED]] + +func.func @caller(%buf: !type, %val: f32, %idx: index) -> f32 { + %0 = call @public_function(%buf, %val, %idx) : (!type, f32, index) -> (!type) + %1 = memref.load %0[%idx] : !type + return %1 : f32 +} + +// ----- + +// CHECK-LABEL: func private @negative_external_function( +// CHECK-SAME: -> memref> + +// Ensure external function remains unchanged. +// MODIFY-PUBLIC-LABEL: func private @negative_external_function( +// MODIFY-PUBLIC-SAME: -> memref> + +!type = memref> +func.func private @negative_external_function(%arg0: !type) -> !type diff --git a/mlir/test/Dialect/EmitC/tosa/lit.local.cfg b/mlir/test/Dialect/EmitC/tosa/lit.local.cfg new file mode 100644 index 0000000000000..848972126d7e8 --- /dev/null +++ b/mlir/test/Dialect/EmitC/tosa/lit.local.cfg @@ -0,0 +1,2 @@ +# Skip files with TD sequences that are used for RUN lines +config.excludes = ["td.mlir"] diff --git a/mlir/test/Conversion/ConvertToEmitC/tosa.mlir b/mlir/test/Dialect/EmitC/tosa/ops.mlir similarity index 79% rename from mlir/test/Conversion/ConvertToEmitC/tosa.mlir rename to mlir/test/Dialect/EmitC/tosa/ops.mlir index 158018374e72c..9f08a95438dfe 100644 --- a/mlir/test/Conversion/ConvertToEmitC/tosa.mlir +++ b/mlir/test/Dialect/EmitC/tosa/ops.mlir @@ -5,7 +5,6 @@ // DEFINE: one-shot-bufferize{\ // DEFINE: bufferize-function-boundaries\ // DEFINE: function-boundary-type-conversion=identity-layout-map\ -// DEFINE: buffer-alignment=0\ // DEFINE: },\ // DEFINE: buffer-results-to-out-params{\ // DEFINE: hoist-static-allocs=true\ @@ -18,9 +17,12 @@ // DEFINE: )" // RUN: mlir-opt --pass-pipeline=%{pipeline} %s | FileCheck %s -// ----- -// CHECK: emitc.func private @main(%[[ARG0:.*]]: !emitc.array<2xf32>, %[[ARG1:.*]]: !emitc.array<2xf32>, %[[RES:.*]]: !emitc.array<2xf32>) +// RUN: mlir-opt -split-input-file \ +// RUN: -transform-preload-library='transform-library-paths=%p/td.mlir' \ +// RUN: -transform-interpreter %s -test-transform-dialect-erase-schedule | mlir-opt -convert-to-emitc | FileCheck %s + +// CHECK: emitc.func private @add(%[[ARG0:.*]]: !emitc.array<2xf32>, %[[ARG1:.*]]: !emitc.array<2xf32>, %[[RES:.*]]: !emitc.array<2xf32>) // CHECK-DAG: %[[C0:.*]] = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t // CHECK-DAG: %[[C1:.*]] = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t // CHECK-DAG: %[[C2:.*]] = "emitc.constant"() <{value = 2 : index}> : () -> !emitc.size_t @@ -35,7 +37,7 @@ // CHECK-NEXT: } // CHECK-NEXT: return // CHECK-NEXT: } -func.func private @main(%arg0: tensor<2xf32>, %arg1: tensor<2xf32>) -> tensor<2xf32> { +func.func private @add(%arg0: tensor<2xf32>, %arg1: tensor<2xf32>) -> tensor<2xf32> { %0 = tosa.add %arg0, %arg1 : (tensor<2xf32>, tensor<2xf32>) -> tensor<2xf32> return %0 : tensor<2xf32> } diff --git a/mlir/test/Dialect/EmitC/tosa/td.mlir b/mlir/test/Dialect/EmitC/tosa/td.mlir new file mode 100644 index 0000000000000..97bb878dc7945 --- /dev/null +++ b/mlir/test/Dialect/EmitC/tosa/td.mlir @@ -0,0 +1,44 @@ +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%module: + !transform.any_op{transform.consumed}) { + // 1. TOSA --> Linalg + %func_h_1 = transform.structured.match ops{["func.func"]} in %module : (!transform.any_op) -> !transform.any_op + transform.apply_registered_pass "tosa-to-linalg" + to %func_h_1 : (!transform.any_op) -> !transform.any_op + + // 2. Bufferize + // As per BufferizationEnums.td, value 1 for `LayoutMapOption` corresponds + // to `IdentityLayoutMap`. + %module_bufferized = transform.bufferization.one_shot_bufferize %module + { bufferize_function_boundaries=true, + function_boundary_type_conversion = 1 : i32} + : (!transform.any_op) -> !transform.op<"builtin.module"> + + // 3. Apply BufferResultsToOutParams - otherwise the following error is raised: + // * "error: 'emitc.func' op cannot return array type" + // "hoist-static-allocs" is an optional optimization step. + %func_h_2 = transform.structured.match ops{["func.func"]} in %module_bufferized : (!transform.op<"builtin.module">) -> !transform.any_op + %module_h_1 = transform.get_parent_op %func_h_2 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %module_results_as_out_param = transform.apply_registered_pass "buffer-results-to-out-params" + with options = { "hoist-static-allocs" = true } + to %module_h_1 : (!transform.any_op) -> !transform.any_op + + %module_final_no_linalg = transform.apply_registered_pass "convert-linalg-to-loops" + to %module_results_as_out_param : (!transform.any_op) -> !transform.any_op + + // 4. Canonicalize - not strictly required + transform.apply_patterns to %module_final_no_linalg { + transform.apply_patterns.canonicalization + } : !transform.any_op + + // FIXME: This causes a crash, hence its commented out. See: + // * https://github.com/llvm/llvm-project/issues/179247 + // %func_h_3 = transform.structured.match ops{["func.func"]} in %module_final_no_linalg + // : (!transform.any_op) -> !transform.any_op + // %module_h_2 = transform.get_parent_op %func_h_3 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + // transform.apply_registered_pass "convert-to-emitc" to %module_h_2 + // : (!transform.any_op) -> !transform.op<"builtin.module"> + + transform.yield + } +} diff --git a/mlir/test/Dialect/EmitC/wrap-func-in-class.mlir b/mlir/test/Dialect/EmitC/wrap-func-in-class.mlir index 809febd0267b1..cb5f99d31e9da 100644 --- a/mlir/test/Dialect/EmitC/wrap-func-in-class.mlir +++ b/mlir/test/Dialect/EmitC/wrap-func-in-class.mlir @@ -1,20 +1,22 @@ // RUN: mlir-opt %s -wrap-emitc-func-in-class -split-input-file | FileCheck %s +// RUN: mlir-opt %s -wrap-emitc-func-in-class=func-name=execute -split-input-file | FileCheck %s --check-prefixes=EXECUTE emitc.func @foo(%arg0 : !emitc.array<1xf32>) { emitc.call_opaque "bar" (%arg0) : (!emitc.array<1xf32>) -> () emitc.return } -// CHECK: module { // CHECK: emitc.class @fooClass { // CHECK: emitc.field @fieldName0 : !emitc.array<1xf32> -// CHECK: emitc.func @execute() { +// CHECK: emitc.func @"operator()"() { // CHECK: %0 = get_field @fieldName0 : !emitc.array<1xf32> // CHECK: call_opaque "bar"(%0) : (!emitc.array<1xf32>) -> () // CHECK: return // CHECK: } // CHECK: } -// CHECK: } + +// EXECUTE-NOT: operator +// EXECUTE: execute() // ----- @@ -34,12 +36,11 @@ module attributes { } { } } -// CHECK: module { // CHECK: emitc.class @modelClass { // CHECK: emitc.field @fieldName0 : !emitc.array<1xf32> {emitc.name_hint = "another_feature"} // CHECK: emitc.field @fieldName1 : !emitc.array<1xf32> {emitc.name_hint = "some_feature"} // CHECK: emitc.field @fieldName2 : !emitc.array<1xf32> {emitc.name_hint = "output_0"} -// CHECK: emitc.func @execute() { +// CHECK: emitc.func @"operator()"() { // CHECK: get_field @fieldName0 : !emitc.array<1xf32> // CHECK: get_field @fieldName1 : !emitc.array<1xf32> // CHECK: get_field @fieldName2 : !emitc.array<1xf32> @@ -54,4 +55,6 @@ module attributes { } { // CHECK: return // CHECK: } // CHECK: } -// CHECK: } + +// EXECUTE-NOT: operator +// EXECUTE: execute() diff --git a/mlir/test/Dialect/GPU/barrier-elimination.mlir b/mlir/test/Dialect/GPU/barrier-elimination.mlir index 7f6619adcd78f..b9ceb8a8d424b 100644 --- a/mlir/test/Dialect/GPU/barrier-elimination.mlir +++ b/mlir/test/Dialect/GPU/barrier-elimination.mlir @@ -106,6 +106,34 @@ func.func @read_read_write_loop_trailing_sync(%arg0: memref, %arg1: f32) return } +// CHECK-LABEL: @read_read_write_loop_trailing_sync_non_memory_barrier +func.func @read_read_write_loop_trailing_sync_non_memory_barrier(%arg0: memref, %arg1: f32) attributes {__parallel_region_boundary_for_test} { + %c0 = arith.constant 0 : index + %c42 = arith.constant 42 : index + %c1 = arith.constant 1 : index + scf.for %i = %c0 to %c42 step %c1 { + // CHECK: load + %0 = memref.load %arg0[%i] : memref + // This can't be removed because it's a barrier that isn't fencing memory. We + // don't know why it's here, so we leave it alone. + // CHECK: gpu.barrier memfence [] + gpu.barrier memfence [] + // However, this can be removed as with the previoius example. + // CHECK-NOT: gpu.barrier + gpu.barrier + // CHECK: load + %1 = memref.load %arg0[%i] : memref + %2 = arith.addf %0, %1 : f32 + // CHECK: gpu.barrier + gpu.barrier + // CHECK: store + memref.store %2, %arg0[%i] : memref + // CHECK: gpu.barrier + gpu.barrier + } + return +} + // CHECK-LABEL: @write_write_noalias func.func @write_write_noalias(%arg0: index, %arg1: f32) -> (memref<42xf32>, memref<10xf32>) attributes {__parallel_region_boundary_for_test} { @@ -199,3 +227,182 @@ func.func @nested_loop_barrier_only() attributes {__parallel_region_boundary_for } return } + + +// CHECK-LABEL: @workgroup_barrier_global_memory +func.func @workgroup_barrier_global_memory( + %global: memref>, + %idx: index, %val: f32) -> f32 +attributes {__parallel_region_boundary_for_test} { + // CHECK: store + memref.store %val, %global[%idx] : memref> + // The barrier only fences workgroup memory, so the global memory write/read + // conflict doesn't matter - barrier can be removed. + // CHECK-NOT: gpu.barrier + gpu.barrier memfence [#gpu.address_space] + // CHECK: load + %0 = memref.load %global[%idx] : memref> + return %0 : f32 +} + + +// CHECK-LABEL: @workgroup_barrier_workgroup_memory +func.func @workgroup_barrier_workgroup_memory( + %workgroup: memref>, + %idx: index, %val: f32) -> f32 +attributes {__parallel_region_boundary_for_test} { + // CHECK: store + memref.store %val, %workgroup[%idx] : memref> + // The barrier fences workgroup memory and there's a write/read conflict on + // workgroup memory - barrier must be retained. + // CHECK: gpu.barrier memfence [#gpu.address_space] + gpu.barrier memfence [#gpu.address_space] + // CHECK: load + %0 = memref.load %workgroup[%idx] : memref> + return %0 : f32 +} + +// Two barriers with non-overlapping address space sets: the inner workgroup +// barrier should not stop at the outer global barrier. +// CHECK-LABEL: @non_overlapping_barriers +func.func @non_overlapping_barriers( + %global: memref>, + %idx: index, %val: f32) -> f32 +attributes {__parallel_region_boundary_for_test} { + // CHECK: store + memref.store %val, %global[%idx] : memref> + // This global barrier guards the write/read on global memory. + // CHECK: gpu.barrier memfence [#gpu.address_space] + gpu.barrier memfence [#gpu.address_space] + // This workgroup barrier can be removed, but shouldn't cause the barrier above + // to be removed. + // CHECK-NOT: gpu.barrier memfence [#gpu.address_space] + gpu.barrier memfence [#gpu.address_space] + // CHECK: load + %0 = memref.load %global[%idx] : memref> + return %0 : f32 +} + +// CHECK-LABEL: @unknown_address_space +func.func @unknown_address_space( + %unknown: memref, + %idx: index, %val: f32) -> f32 +attributes {__parallel_region_boundary_for_test} { + // CHECK: store + memref.store %val, %unknown[%idx] : memref + // This barrier cannot be removed because the unknown-memory-space memref could + // point to workgroup memory. + // CHECK: gpu.barrier memfence [#gpu.address_space] + gpu.barrier memfence [#gpu.address_space] + // CHECK: load + %0 = memref.load %unknown[%idx] : memref + return %0 : f32 +} + +// CHECK-LABEL: @mixed_address_spaces +func.func @mixed_address_spaces( + %global: memref>, + %workgroup: memref>, + %idx: index, %val: f32) -> f32 +attributes {__parallel_region_boundary_for_test} { + // CHECK: store + memref.store %val, %global[%idx] : memref> + // CHECK: store + memref.store %val, %workgroup[%idx] : memref> + // Barrier fences both global and workgroup. There are conflicts on at least one of them, + // so the barrier must be retained. + // CHECK: gpu.barrier memfence [#gpu.address_space, #gpu.address_space] + gpu.barrier memfence [#gpu.address_space, #gpu.address_space] + // CHECK: load + %0 = memref.load %global[%idx] : memref> + // CHECK: load + %1 = memref.load %workgroup[%idx] : memref> + %2 = arith.addf %0, %1 : f32 + return %2 : f32 +} + +// CHECK-LABEL: @full_barrier_with_global_conflict +func.func @full_barrier_with_global_conflict( + %global: memref>, + %idx: index, %val: f32) -> f32 +attributes {__parallel_region_boundary_for_test} { + // CHECK: store + memref.store %val, %global[%idx] : memref> + // CHECK: gpu.barrier{{$}} + gpu.barrier + // CHECK: load + %0 = memref.load %global[%idx] : memref> + return %0 : f32 +} + +// CHECK-LABEL: @barrier_fencing_nothing_removed +func.func @barrier_fencing_nothing_removed() +attributes {__parallel_region_boundary_for_test} { + // CHECK-NOT: gpu.barrier + gpu.barrier + return +} + +// CHECK-LABEL: @empty_barrrier_retained +func.func @empty_barrrier_retained() +attributes {__parallel_region_boundary_for_test} { + // CHECK: gpu.barrier memfence [] + gpu.barrier memfence [] + return +} + +// CHECK-LABEL: @read_write_loop_no_workgroup +func.func @read_write_loop_no_workgroup(%arg0: memref>, %arg1: f32) attributes {__parallel_region_boundary_for_test} { + %c0 = arith.constant 0 : index + %c42 = arith.constant 42 : index + %c1 = arith.constant 1 : index + // CHECK: scf.for + scf.for %i = %c0 to %c42 step %c1 { + // Barrier can be eliminated because it only fences workgroup memory, which + // this loop does not use. + // CHECK-NOT: gpu.barrier + gpu.barrier memfence [#gpu.address_space] + // CHECK: load + %0 = memref.load %arg0[%i] : memref> + %1 = arith.addf %0, %0 : f32 + // Fences workgroup memory and so has no efect here. + // CHECK-NOT: gpu.barrier + gpu.barrier memfence [#gpu.address_space] + // CHECK: store + memref.store %0, %arg0[%i] : memref> + } + return +} + +// CHECK-LABEL: @global_barrier_buffer_cast +func.func @global_barrier_buffer_cast( + %global: memref>, + %idx: index, %val: f32) -> f32 +attributes {__parallel_region_boundary_for_test} { + // CHECK: store + memref.store %val, %global[%idx] : memref> + // The buffer cast below shouldn't make this barrier go away + // CHECK: gpu.barrier memfence [#gpu.address_space] + gpu.barrier memfence [#gpu.address_space] + %cast = amdgpu.fat_raw_buffer_cast %global : memref> to memref> + // CHECK: load + %0 = memref.load %cast[%idx] : memref> + return %0 : f32 +} + +// CHECK-LABEL: @workgroup_barrier_buffer_cast +func.func @workgroup_barrier_buffer_cast( + %global: memref>, + %idx: index, %val: f32) -> f32 +attributes {__parallel_region_boundary_for_test} { + // CHECK: store + memref.store %val, %global[%idx] : memref> + // The amdgpu buffer resource is formed from global memory, and so can't alias + // workgroup memory, so this barrier can be eliminated. + // CHECK-NOT: gpu.barrierw + gpu.barrier memfence [#gpu.address_space] + %cast = amdgpu.fat_raw_buffer_cast %global : memref> to memref> + // CHECK: load + %0 = memref.load %cast[%idx] : memref> + return %0 : f32 +} diff --git a/mlir/test/Dialect/GPU/invalid.mlir b/mlir/test/Dialect/GPU/invalid.mlir index ad6ad7338ff38..6e67d682703ec 100644 --- a/mlir/test/Dialect/GPU/invalid.mlir +++ b/mlir/test/Dialect/GPU/invalid.mlir @@ -135,7 +135,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { gpu.module @kernels { // expected-note@+1 {{see the kernel definition here}} - memref.global "private" @kernel_1 : memref<4xi32> + memref.global @kernel_1 : memref<4xi32> } func.func @launch_func_undefined_function(%sz : index) { @@ -816,7 +816,7 @@ module attributes {gpu.container_module} { module attributes {gpu.container_module} { gpu.module @kernel { - // expected-error@+1 {{'gpu.func' op attribute 'known_block_size' failed to satisfy constraint: i32 dense array attribute with 3 elements (if present)}} + // expected-error@+1 {{'gpu.func' op attribute 'known_block_size' failed to satisfy constraint: i32 dense array attribute with 3 elements (if present) and all elements >= 1}} gpu.func @kernel() kernel attributes {known_block_size = array} { gpu.return } @@ -825,6 +825,17 @@ module attributes {gpu.container_module} { // ----- +module attributes {gpu.container_module} { + gpu.module @kernel { + // expected-error@+1 {{'gpu.func' op attribute 'known_block_size' failed to satisfy constraint: i32 dense array attribute with 3 elements (if present) and all elements >= 1}} + gpu.func @kernel() kernel attributes {known_block_size = array} { + gpu.return + } + } +} + +// ----- + module { // expected-error@+1 {{'func.func' op gpu.known_block_size must contain exactly 3 elements}} func.func @kernel() attributes {gpu.known_block_size = array} { diff --git a/mlir/test/Dialect/LLVMIR/func.mlir b/mlir/test/Dialect/LLVMIR/func.mlir index e57a54cb43267..8af1e52485425 100644 --- a/mlir/test/Dialect/LLVMIR/func.mlir +++ b/mlir/test/Dialect/LLVMIR/func.mlir @@ -372,6 +372,54 @@ module { llvm.return } + llvm.func @no_builtins_all() attributes { nobuiltins = [] } { + // CHECK: @no_builtins_all + // CHECK-SAME: attributes {nobuiltins = []} + llvm.return + } + + llvm.func @no_builtins_2() attributes { nobuiltins = ["foo", "bar"] } { + // CHECK: @no_builtins_2 + // CHECK-SAME: attributes {nobuiltins = ["foo", "bar"]} + llvm.return + } + + llvm.func @alloc_size_one(%arg: i32, %arg2: i32, %arg3: i32, %args4: i32) attributes { allocsize = array} { + // CHECK: @alloc_size_one + // CHECK-SAME: attributes {allocsize = array} + llvm.return + } + + llvm.func @alloc_size_two(%arg: i32, %arg2: i32, %arg3: i32, %args4: i32) attributes { allocsize = array } { + // CHECK: @alloc_size_two + // CHECK-SAME: attributes {allocsize = array} + llvm.return + } + + llvm.func @minsize_optsize() attributes { minsize, optsize } { + // CHECK: @minsize_optsize + // CHECK-SAME: attributes {minsize, optsize} + llvm.return + } + + llvm.func @save_reg_params() attributes { save_reg_params } { + // CHECK: @save_reg_params + // CHECK-SAME: attributes {save_reg_params} + llvm.return + } + + llvm.func @zero_call_used_regs() attributes { zero_call_used_regs="used-gpr-arg"} { + // CHECK: @zero_call_used_regs + // CHECK-SAME: attributes {zero_call_used_regs = "used-gpr-arg"} + llvm.return + } + + llvm.func @default_func_attrs() attributes {default_func_attrs={key="value",justKey}} { + // CHECK: @default_func_attrs + // CHECK-SAME: attributes {default_func_attrs = {justKey, key = "value"}} + llvm.return + } + } // ----- diff --git a/mlir/test/Dialect/LLVMIR/roundtrip.mlir b/mlir/test/Dialect/LLVMIR/roundtrip.mlir index c97574f41e8a4..c680d0d98ac5f 100644 --- a/mlir/test/Dialect/LLVMIR/roundtrip.mlir +++ b/mlir/test/Dialect/LLVMIR/roundtrip.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt -verify-roundtrip %s +// RUN: mlir-opt -verify-roundtrip %s | FileCheck %s // CHECK-LABEL: func @baz @@ -149,6 +149,39 @@ func.func @ops(%arg0: i32, %arg1: f32, // CHECK: llvm.call @baz() {memory = #llvm.memory_effects} : () -> () llvm.call @baz() {memory = #llvm.memory_effects} : () -> () +// CHECK: llvm.call @baz() {nobuiltins = []} : () -> () + llvm.call @baz() {nobuiltins = []} : () -> () + +// CHECK: llvm.call @baz() {nobuiltins = ["asdf", "defg"]} : () -> () + llvm.call @baz() {nobuiltins = ["asdf", "defg"]} : () -> () + +// CHECK: llvm.call @baz() {allocsize = array} : () -> () + llvm.call @baz() {allocsize = array} : () -> () + +// CHECK: llvm.call @baz() {allocsize = array} : () -> () + llvm.call @baz() {allocsize = array} : () -> () + +// CHECK: llvm.call @baz() {minsize} : () -> () + llvm.call @baz() {minsize} : () -> () + +// CHECK: llvm.call @baz() {optsize} : () -> () + llvm.call @baz() {optsize} : () -> () + +// CHECK: llvm.call @baz() {nobuiltin} : () -> () + llvm.call @baz() {nobuiltin} : () -> () + +// CHECK: llvm.call @baz() {save_reg_params} : () -> () + llvm.call @baz() {save_reg_params} : () -> () + +// CHECK: llvm.call @baz() {zero_call_used_regs = "all"} : () -> () + llvm.call @baz() {zero_call_used_regs="all"} : () -> () + +// CHECK: llvm.call @baz() {zero_call_used_regs = "thing"} : () -> () + llvm.call @baz() {zero_call_used_regs="thing"} : () -> () + +// CHECK: llvm.call @baz() {default_func_attrs = {justKey, key = "value"}} : () -> () + llvm.call @baz() {default_func_attrs={justKey, key = "value"}} : () -> () + // Terminator operations and their successors. // // CHECK: llvm.br ^[[BB1:.*]] diff --git a/mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns.mlir b/mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns.mlir index f8781ff5452d9..97b27befd44e2 100644 --- a/mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns.mlir +++ b/mlir/test/Dialect/Linalg/vectorization/convolution-with-patterns.mlir @@ -678,6 +678,59 @@ module attributes {transform.with_named_sequence} { // ----- +// Test for mixed precision hanlding of 1D non-channeled convolution. +func.func @conv1d_mixed_precision_bf16_f32(%input: tensor<5xbf16>, %filter: tensor<2xbf16>, %output: tensor<4xf32>) -> tensor<4xf32> { + %0 = linalg.conv_1d ins(%input, %filter : tensor<5xbf16>, tensor<2xbf16>) + outs(%output : tensor<4xf32>) -> tensor<4xf32> + return %0 : tensor<4xf32> +} + +// CHECK: func @conv1d_mixed_precision_bf16_f32 +// CHECK-SAME: (%[[INPUT:.+]]: tensor<5xbf16>, %[[FILTER:.+]]: tensor<2xbf16>, %[[OUTPUT:.+]]: tensor<4xf32>) + +// CHECK-DAG: %[[C0:.+]] = arith.constant 0 : index +// CHECK-DAG: %[[F0:.+]] = arith.constant 0.000000e+00 : f32 +// CHECK-DAG: %[[BF0:.+]] = arith.constant 0.000000e+00 : bf16 + +/// Read the whole data in one shot. +// CHECK-DAG: %[[V_INPUT_R:.+]] = vector.transfer_read %[[INPUT]][%[[C0]]], %[[BF0]] +// CHECK-DAG: %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]]], %[[BF0]] +// CHECK-DAG: %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]]], %[[F0]] + +// CHECK: %[[V_INPUT_0:.+]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [0], sizes = [4], strides = [1]} : vector<5xbf16> to vector<4xbf16> +// CHECK: %[[V_INPUT_1:.+]] = vector.extract_strided_slice %[[V_INPUT_R]] +// CHECK-SAME: {offsets = [1], sizes = [4], strides = [1]} : vector<5xbf16> to vector<4xbf16> + +// CHECK: %[[V_FILTER_0:.+]] = vector.extract %[[V_FILTER_R]][0] : bf16 from vector<2xbf16> +// CHECK: %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][1] : bf16 from vector<2xbf16> + +/// Extend input and filter to f32 and then perform outerproduct. +/// kw == 0 +// CHECK: %[[V_INPUT_0_F32:.+]] = arith.extf %[[V_INPUT_0]] : vector<4xbf16> to vector<4xf32> +// CHECK: %[[V_FILTER_0_F32:.+]] = arith.extf %[[V_FILTER_0]] : bf16 to f32 +// CHECK: %[[RES_0:.+]] = vector.outerproduct %[[V_INPUT_0_F32]], %[[V_FILTER_0_F32]], %[[V_OUTPUT_R]] {kind = #vector.kind} +// CHECK-SAME: : vector<4xf32>, f32 +/// kw == 1 +// CHECK: %[[V_INPUT_1_F32:.+]] = arith.extf %[[V_INPUT_1]] : vector<4xbf16> to vector<4xf32> +// CHECK: %[[V_FILTER_1_F32:.+]] = arith.extf %[[V_FILTER_1]] : bf16 to f32 +// CHECK: %[[RES_1:.+]] = vector.outerproduct %[[V_INPUT_1_F32]], %[[V_FILTER_1_F32]], %[[RES_0]] {kind = #vector.kind} +// CHECK-SAME: : vector<4xf32>, f32 + +// Write the result back in one shot. +// CHECK: vector.transfer_write %[[RES_1]], %[[OUTPUT]][%[[C0]]] + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["linalg.conv_1d", "linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + +// ----- + func.func @depthwise_conv1d_nwc_wc_3x5x4xf32_memref(%input: memref<3x5x4xf32>, %filter: memref<2x4xf32>, %output: memref<3x2x4xf32>) { linalg.depthwise_conv_1d_nwc_wc {dilations = dense<2> : tensor<1xi64>, strides = dense<1> : tensor<1xi64>} @@ -801,8 +854,10 @@ func.func @conv_1d_nwc_wcf_mixed_type_memref(%input: memref<1x2x3xf16>, %filter: // CHECK: %[[V_FILTER_R:.+]] = vector.transfer_read %[[FILTER]][%[[C0]], %[[C0]], %[[C0]]] // CHECK: %[[V_OUTPUT_R:.+]] = vector.transfer_read %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]] // CHECK: %[[V_FILTER_1:.+]] = vector.extract %[[V_FILTER_R]][0] : vector<3x2xf16> from vector<1x3x2xf16> -// CHECK: %[[CONT:.*]] = vector.contract -// {{.*}} %[[V_INPUT_R]], %[[V_FILTER_1]], %[[V_OUTPUT_R]] : vector<1x2x3xf16>, vector<3x2xf16> into vector<1x2x2xf32> +// CHECK: %[[V_INPUT_F32:.+]] = arith.extf %[[V_INPUT_R]] : vector<1x2x3xf16> to vector<1x2x3xf32> +// CHECK: %[[V_FILTER_F32:.+]] = arith.extf %[[V_FILTER_1]] : vector<3x2xf16> to vector<3x2xf32> +// CHECK: %[[CONT:.+]] = vector.contract +// CHECK-SAME: %[[V_INPUT_F32]], %[[V_FILTER_F32]], %[[V_OUTPUT_R]] : vector<1x2x3xf32>, vector<3x2xf32> into vector<1x2x2xf32> // CHECK: vector.transfer_write %[[CONT]], %[[OUTPUT]][%[[C0]], %[[C0]], %[[C0]]] module attributes {transform.with_named_sequence} { diff --git a/mlir/test/Dialect/MPI/canonicalize.mlir b/mlir/test/Dialect/MPI/canonicalize.mlir new file mode 100644 index 0000000000000..3523d46e21219 --- /dev/null +++ b/mlir/test/Dialect/MPI/canonicalize.mlir @@ -0,0 +1,14 @@ +// RUN: mlir-opt %s -canonicalize | mlir-opt | FileCheck %s + +module attributes {mpi.dlti = #dlti.map<"MPI:comm_world_size" = 12, "MPI:comm_world_rank" = 5> } { + // CHECK-LABEL: func.func @mpi_test + func.func @mpi_test(%ref : memref<100xf32>) -> (i32, i32) { + %comm = mpi.comm_world : !mpi.comm + // CHECK: [[s:%.*]] = arith.constant 12 : i32 + %sz = mpi.comm_size(%comm) : i32 + // CHECK: [[r:%.*]] = arith.constant 5 : i32 + %rk = mpi.comm_rank(%comm) : i32 + // CHECK: return [[s]], [[r]] : i32, i32 + return %sz, %rk : i32, i32 + } +} diff --git a/mlir/test/Dialect/MemRef/canonicalize.mlir b/mlir/test/Dialect/MemRef/canonicalize.mlir index 17afd9a15b60d..3cfea1e8cd961 100644 --- a/mlir/test/Dialect/MemRef/canonicalize.mlir +++ b/mlir/test/Dialect/MemRef/canonicalize.mlir @@ -1385,6 +1385,21 @@ func.func @expand_collapse_do_not_fold_to_cast(%m: memref<1x3x2x384xui8, strided // ----- +// CHECK-LABEL: func @expand_collapse_dynamic_do_not_fold_to_cast( +// CHECK-NOT: memref.cast + +func.func @expand_collapse_dynamic_do_not_fold_to_cast(%m: memref<1x?x1x32xsi8, strided<[?, 32, 32, 1]>>, %dyn_size: index) + -> (memref<1x1x?x32xsi8, strided<[?, ?, 32, 1]>>) + { + %0 = memref.collapse_shape %m [[0], [1, 2], [3]] + : memref<1x?x1x32xsi8, strided<[?, 32, 32, 1]>> into memref<1x?x32xsi8, strided<[?, 32, 1]>> + %1 = memref.expand_shape %0 [[0, 1], [2], [3]] output_shape [1, 1, %dyn_size, 32] + : memref<1x?x32xsi8, strided<[?, 32, 1]>> into memref<1x1x?x32xsi8, strided<[?, ?, 32, 1]>> + return %1 : memref<1x1x?x32xsi8, strided<[?, ?, 32, 1]>> +} + +// ----- + // CHECK-LABEL: func @fold_trivial_subviews( // CHECK-SAME: %[[m:.*]]: memref> // CHECK: %[[subview:.*]] = memref.subview %[[m]][5] diff --git a/mlir/test/Dialect/MemRef/ops.mlir b/mlir/test/Dialect/MemRef/ops.mlir index cddc79f693b11..14ac6a03d6ae0 100644 --- a/mlir/test/Dialect/MemRef/ops.mlir +++ b/mlir/test/Dialect/MemRef/ops.mlir @@ -211,7 +211,7 @@ func.func @memref_alloca_scope() { } // CHECK-LABEL: func @memref_cast(%arg0 -func.func @memref_cast(%arg0: memref<4xf32>, %arg1 : memref, %arg2 : memref<64x16x4xf32, strided<[64, 4, 1], offset: 0>>) { +func.func @memref_cast(%arg0: memref<4xf32>, %arg1 : memref, %arg2 : memref<64x16x4xf32, strided<[64, 4, 1], offset: 0>>, %arg3 : memref<4x1x8xf32, strided<[32, 16, 1]>>, %arg4 : memref<4x?x8xf32, strided<[32, 8, 1]>>) { // CHECK: memref.cast %{{.*}} : memref<4xf32> to memref %0 = memref.cast %arg0 : memref<4xf32> to memref @@ -229,6 +229,12 @@ func.func @memref_cast(%arg0: memref<4xf32>, %arg1 : memref, %arg2 : memr // CHECK: memref.cast %{{.*}} : memref<*xf32> to memref<4xf32> %5 = memref.cast %4 : memref<*xf32> to memref<4xf32> + + // CHECK: memref.cast %{{.*}} : memref<4x1x8xf32, strided<[32, 16, 1]>> to memref<4x?x8xf32, strided<[32, 8, 1]>> + %6 = memref.cast %arg3 : memref<4x1x8xf32, strided<[32, 16, 1]>> to memref<4x?x8xf32, strided<[32, 8, 1]>> + + // CHECK: memref.cast %{{.*}} : memref<4x?x8xf32, strided<[32, 8, 1]>> to memref<4x1x8xf32, strided<[32, 16, 1]>> + %7 = memref.cast %arg4 : memref<4x?x8xf32, strided<[32, 8, 1]>> to memref<4x1x8xf32, strided<[32, 16, 1]>> return } diff --git a/mlir/test/Dialect/OpenMP/ops.mlir b/mlir/test/Dialect/OpenMP/ops.mlir index 1e8c9bdeb33ae..5c2849cc9b5ea 100644 --- a/mlir/test/Dialect/OpenMP/ops.mlir +++ b/mlir/test/Dialect/OpenMP/ops.mlir @@ -3520,3 +3520,33 @@ func.func @omp_declare_simd_all_clauses(%a: f64, %b: f64, inbranch return } + +// CHECK-LABEL: func.func @task_affinity_single +func.func @task_affinity_single() { + // CHECK: %[[A:.*]] = memref.alloca() : memref<100xi32> + // CHECK: omp.task affinity(%[[A]] : memref<100xi32>) { + // CHECK: omp.terminator + // CHECK: } + // CHECK: return + %a = memref.alloca() : memref<100xi32> + omp.task affinity(%a : memref<100xi32>) { + omp.terminator + } + return +} + +// CHECK-LABEL: func.func @task_affinity_multi +func.func @task_affinity_multi() { + // CHECK: %[[A:.*]] = memref.alloca() : memref<64xi32> + // CHECK: %[[B:.*]] = memref.alloca() : memref<8xf64> + // CHECK: omp.task affinity(%[[A]] : memref<64xi32>, %[[B]] : memref<8xf64>) { + // CHECK: omp.terminator + // CHECK: } + // CHECK: return + %a = memref.alloca() : memref<64xi32> + %b = memref.alloca() : memref<8xf64> + omp.task affinity(%a : memref<64xi32>, %b : memref<8xf64>) { + omp.terminator + } + return +} diff --git a/mlir/test/Dialect/SCF/canonicalize.mlir b/mlir/test/Dialect/SCF/canonicalize.mlir index e9f9e1a964963..f65046ecee6da 100644 --- a/mlir/test/Dialect/SCF/canonicalize.mlir +++ b/mlir/test/Dialect/SCF/canonicalize.mlir @@ -2284,54 +2284,3 @@ func.func @iter_args_cycles_non_cycle_start(%lb : index, %ub : index, %step : in } return %res#0, %res#1, %res#2 : i32, i32, i32 } - -// ----- - -// CHECK-LABEL: @erase_infinite_scf_for_loop -// CHECK: %[[poison:.*]] = ub.poison : index -// CHECK: return %[[poison]] -func.func @erase_infinite_scf_for_loop(%init: index) -> index { - %lb = arith.constant 3 : index - %ub = arith.constant 4 : index - %step = arith.constant 0 : index - %res = scf.for %iv = %lb to %ub step %step iter_args(%iter = %init) -> index { - %0 = arith.addi %iter, %iter : index - scf.yield %0 : index - } - return %res : index -} - -// ----- - -// CHECK-LABEL: @do_not_erase_infinite_loop_with_side_effect -// CHECK: %[[res:.*]] = scf.for -// CHECK: vector.print -// CHECK: return %[[res]] -func.func @do_not_erase_infinite_loop_with_side_effect(%init: index) -> index { - %lb = arith.constant 3 : index - %ub = arith.constant 4 : index - %step = arith.constant 0 : index - %res = scf.for %iv = %lb to %ub step %step iter_args(%iter = %init) -> index { - %0 = arith.addi %iter, %iter : index - vector.print %0 : index - scf.yield %0 : index - } - return %res : index -} - -// ----- - -// CHECK-LABEL: @erase_infinite_scf_while_loop -// CHECK: %[[poison:.*]] = ub.poison : index -// CHECK: return %[[poison]] -func.func @erase_infinite_scf_while_loop(%init: index) -> index { - %res = scf.while (%arg0 = %init) : (index) -> (index) { - %true = arith.constant true - scf.condition(%true) %arg0 : index - } do { - ^bb0(%arg1: index): - %0 = arith.addi %arg1, %arg1 : index - scf.yield %0 : index - } - return %res : index -} diff --git a/mlir/test/Dialect/SCF/ops.mlir b/mlir/test/Dialect/SCF/ops.mlir index bee08216165b0..5930a1df04266 100644 --- a/mlir/test/Dialect/SCF/ops.mlir +++ b/mlir/test/Dialect/SCF/ops.mlir @@ -12,7 +12,7 @@ func.func @std_for(%arg0 : index, %arg1 : index, %arg2 : index) { %max_cmp = arith.cmpi sge, %i0, %i1 : index %max = arith.select %max_cmp, %i0, %i1 : index scf.for %i2 = %min to %max step %i1 { - } {mustProgress = false} + } } } return @@ -25,7 +25,6 @@ func.func @std_for(%arg0 : index, %arg1 : index, %arg2 : index) { // CHECK-NEXT: %{{.*}} = arith.cmpi sge, %{{.*}}, %{{.*}} : index // CHECK-NEXT: %{{.*}} = arith.select %{{.*}}, %{{.*}}, %{{.*}} : index // CHECK-NEXT: scf.for %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}} { -// CHECK-NEXT: } {mustProgress = false} func.func @std_for_i32(%arg0 : i32, %arg1 : i32, %arg2 : i32) { scf.for %i0 = %arg0 to %arg1 step %arg2 : i32 { @@ -281,8 +280,8 @@ func.func @while() { %5:2 = "test.some_operation"(%arg2, %arg3): (i64, f64) -> (i32, f32) // CHECK: scf.yield %{{.*}}, %{{.*}} : i32, f32 scf.yield %5#0, %5#1 : i32, f32 - // CHECK: attributes {foo = "bar", mustProgress = false} - } attributes {foo="bar", mustProgress=false} + // CHECK: attributes {foo = "bar"} + } attributes {foo="bar"} return } diff --git a/mlir/test/Dialect/SPIRV/IR/arithmetic-ops.mlir b/mlir/test/Dialect/SPIRV/IR/arithmetic-ops.mlir index c703274bda579..7f1b84123151a 100644 --- a/mlir/test/Dialect/SPIRV/IR/arithmetic-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/arithmetic-ops.mlir @@ -348,7 +348,7 @@ func.func @dot(%arg0: vector<4xf32>, %arg1: vector<4xf32>) -> f16 { // ----- func.func @dot(%arg0: vector<4xi32>, %arg1: vector<4xi32>) -> i32 { - // expected-error @+1 {{'spirv.Dot' op operand #0 must be fixed-length vector of 16/32/64-bit float or BFloat16 values of length 2/3/4/8/16}} + // expected-error @+1 {{'spirv.Dot' op operand #0 must be fixed-length vector of 16/32/64-bit float or BFloat16 or Float8E4M3 or Float8E5M2 values of length 2/3/4/8/16}} %0 = spirv.Dot %arg0, %arg1 : vector<4xi32> -> i32 return %0 : i32 } diff --git a/mlir/test/Dialect/SPIRV/IR/composite-ops.mlir b/mlir/test/Dialect/SPIRV/IR/composite-ops.mlir index 9323518f50373..6e4126172f670 100644 --- a/mlir/test/Dialect/SPIRV/IR/composite-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/composite-ops.mlir @@ -100,7 +100,7 @@ func.func @composite_construct_vector_wrong_count(%arg0: f32, %arg1: f32, %arg2 // ----- func.func @composite_construct_vector_rank_two(%arg0: vector<2x2xi1>, %arg1: vector<2x2xi1>) -> vector<4x2xi1> { - // expected-error @+1 {{op operand #0 must be variadic of void or bool or 8/16/32/64-bit integer or 16/32/64-bit float or BFloat16 or vector of bool or 8/16/32/64-bit integer or 16/32/64-bit float or BFloat16 values of length 2/3/4/8/16 of ranks 1 or any SPIR-V pointer type or any SPIR-V array type or any SPIR-V runtime array type or any SPIR-V struct type or any SPIR-V cooperative matrix type or any SPIR-V matrix type or any SPIR-V sampled image type or any SPIR-V image type or any SPIR-V tensorArm type, but got 'vector<2x2xi1>'}} + // expected-error @+1 {{ op operand #0 must be variadic of void or bool or 8/16/32/64-bit integer or 16/32/64-bit float or BFloat16 or Float8E4M3 or Float8E5M2 or vector of bool or 8/16/32/64-bit integer or 16/32/64-bit float or BFloat16 or Float8E4M3 or Float8E5M2 values of length 2/3/4/8/16 of ranks 1 or any SPIR-V pointer type or any SPIR-V array type or any SPIR-V runtime array type or any SPIR-V struct type or any SPIR-V cooperative matrix type or any SPIR-V matrix type or any SPIR-V sampled image type or any SPIR-V image type or any SPIR-V tensorArm type, but got 'vector<2x2xi1>'}} %0 = spirv.CompositeConstruct %arg0, %arg1 : (vector<2x2xi1>, vector<2x2xi1>) -> vector<4x2xi1> return %0: vector<4x2xi1> } diff --git a/mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir b/mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir index b70bb40dae97f..81dce9822db48 100644 --- a/mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir @@ -496,6 +496,62 @@ func.func @loop_yield(%count : i32) -> () { // ----- +func.func @loop_yield_result_type_mismatch(%count : i32) -> () { + %zero = spirv.Constant 0: i32 + %one = spirv.Constant 1: i32 + + // expected-error@+1{{result types do not match types yielded with `spirv.mlir.merge`}} + %final_i = spirv.mlir.loop -> f32 { + spirv.Branch ^header(%zero: i32) + + ^header(%i : i32): + %cmp = spirv.SLessThan %i, %count : i32 + spirv.BranchConditional %cmp, ^body, ^merge + + ^body: + spirv.Branch ^continue + + ^continue: + %new_i = spirv.IAdd %i, %one : i32 + spirv.Branch ^header(%new_i: i32) + + ^merge: + spirv.mlir.merge %i : i32 + } + + return +} + +// ----- + +func.func @loop_yield_result_count_mismatch(%count : i32) -> () { + %zero = spirv.Constant 0: i32 + %one = spirv.Constant 1: i32 + + // expected-error@+1{{result types do not match types yielded with `spirv.mlir.merge`}} + %final_i = spirv.mlir.loop -> i32 { + spirv.Branch ^header(%zero: i32) + + ^header(%i : i32): + %cmp = spirv.SLessThan %i, %count : i32 + spirv.BranchConditional %cmp, ^body, ^merge + + ^body: + spirv.Branch ^continue + + ^continue: + %new_i = spirv.IAdd %i, %one : i32 + spirv.Branch ^header(%new_i: i32) + + ^merge: + spirv.mlir.merge %i, %i : i32, i32 + } + + return +} + +// ----- + //===----------------------------------------------------------------------===// // spirv.mlir.merge //===----------------------------------------------------------------------===// @@ -922,6 +978,57 @@ func.func @selection_yield(%cond: i1) -> () { // ----- +func.func @selection_yield_result_type_mismatch(%cond: i1) -> () { + %zero = spirv.Constant 0: i32 + + // expected-error@+1{{result types do not match types yielded with `spirv.mlir.merge`}} + %yield:2 = spirv.mlir.selection -> f32, f32 { + spirv.BranchConditional %cond, ^then, ^else + + ^then: + %one = spirv.Constant 1: i32 + %three = spirv.Constant 3: i32 + spirv.Branch ^merge(%one, %three : i32, i32) + + ^else: + %two = spirv.Constant 2: i32 + %four = spirv.Constant 4 : i32 + spirv.Branch ^merge(%two, %four : i32, i32) + + ^merge(%merged_1_2: i32, %merged_3_4: i32): + spirv.mlir.merge %merged_1_2, %merged_3_4 : i32, i32 + } + + spirv.Return +} + +// ----- + +func.func @selection_yield_result_count_mismatch(%cond: i1) -> () { + %zero = spirv.Constant 0: i32 + + // expected-error@+1{{result types do not match types yielded with `spirv.mlir.merge`}} + %yield:2 = spirv.mlir.selection -> f32, f32 { + spirv.BranchConditional %cond, ^then, ^else + + ^then: + %one = spirv.Constant 1: i32 + spirv.Branch ^merge(%one :i32) + + ^else: + %two = spirv.Constant 2: i32 + spirv.Branch ^merge(%two : i32) + + ^merge(%merged_1_2: i32): + spirv.mlir.merge %merged_1_2 : i32 + } + + spirv.Return +} + +// ----- + + //===----------------------------------------------------------------------===// // spirv.Unreachable //===----------------------------------------------------------------------===// diff --git a/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir b/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir index 2c5dc8b9f3b0f..7e37826795d83 100644 --- a/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/structure-ops.mlir @@ -170,7 +170,7 @@ func.func @coop_matrix_const_wrong_type() -> () { //===----------------------------------------------------------------------===// func.func @ccr_result_not_composite() -> () { - // expected-error @+1 {{op result #0 must be vector of bool or 8/16/32/64-bit integer or 16/32/64-bit float or BFloat16 values of length 2/3/4/8/16 of ranks 1 or any SPIR-V array type or any SPIR-V runtime array type or any SPIR-V struct type or any SPIR-V cooperative matrix type or any SPIR-V matrix type or any SPIR-V tensorArm type, but got 'i32'}} + // expected-error @+1 {{op result #0 must be vector of bool or 8/16/32/64-bit integer or 16/32/64-bit float or BFloat16 or Float8E4M3 or Float8E5M2 values of length 2/3/4/8/16 of ranks 1 or any SPIR-V array type or any SPIR-V runtime array type or any SPIR-V struct type or any SPIR-V cooperative matrix type or any SPIR-V matrix type or any SPIR-V tensorArm type, but got 'i32'}} %0 = spirv.EXT.ConstantCompositeReplicate [1 : i32] : i32 return } @@ -360,7 +360,7 @@ spirv.module Logical GLSL450 requires #spirv.vce { } // ----- -spirv.module Logical GLSL450 requires #spirv.vce { +spirv.module Logical GLSL450 requires #spirv.vce { // expected-error @+1 {{'spirv.module' cannot contain external functions without 'Import' linkage_attributes (LinkageAttributes)}} spirv.func @outside.func.without.linkage(%arg0 : i8) -> () "Pure" spirv.func @inside.func() -> () "Pure" attributes {} {spirv.Return} @@ -477,7 +477,7 @@ spirv.module Logical GLSL450 requires #spirv.vce { // CHECK: linkage_attributes = #spirv.linkage_attributes> spirv.GlobalVariable @var1 { linkage_attributes=#spirv.linkage_attributes< - linkage_name="outSideGlobalVar1", + linkage_name="outSideGlobalVar1", linkage_type= > } : !spirv.ptr diff --git a/mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir b/mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir index 56cd6d6900fdb..dd18a3a2ae788 100644 --- a/mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir +++ b/mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir @@ -410,8 +410,24 @@ spirv.ARM.Graph @matmul_invalid_input_output_element_type_combination(%arg0: !sp // spirv.TOSA.MaxPool2D //===----------------------------------------------------------------------===// -spirv.ARM.Graph @maxpool2d_int(%arg0: !spirv.arm.tensor<1x3x65537x1xi8>) -> (!spirv.arm.tensor<1x2x32769x1xi16>) { +spirv.ARM.Graph @maxpool2d_input_output_different_element_types(%arg0: !spirv.arm.tensor<1x3x65537x1xi8>) -> (!spirv.arm.tensor<1x2x32769x1xi16>) { // expected-error @+1 {{op failed to verify that all of {input, output} have same element type}} %4 = spirv.Tosa.MaxPool2D kernel = [3, 2], stride = [1, 2], pad = [1, 0, 0, 1], nan_mode = , %arg0 : !spirv.arm.tensor<1x3x65537x1xi8> -> !spirv.arm.tensor<1x2x32769x1xi16> spirv.ARM.GraphOutputs %4 : !spirv.arm.tensor<1x2x32769x1xi16> } + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Clamp +//===----------------------------------------------------------------------===// + +spirv.ARM.Graph @clamp_min_val_different_element_type_wrt_input_output(%arg0: !spirv.arm.tensor<27x44x55xi8>) -> (!spirv.arm.tensor<27x44x55xi8>) { + // expected-error @+1 {{op failed to verify that all of {input, output, min_val, max_val} have same element type}} + %3 = spirv.Tosa.Clamp min_val = -102 : i16, max_val = -100 : i8, nan_mode = , %arg0 : !spirv.arm.tensor<27x44x55xi8> -> !spirv.arm.tensor<27x44x55xi8> + spirv.ARM.GraphOutputs %3 : !spirv.arm.tensor<27x44x55xi8> +} + +spirv.ARM.Graph @clamp_max_val_different_element_type_wrt_input_output(%arg0: !spirv.arm.tensor<27x44x55xi8>) -> (!spirv.arm.tensor<27x44x55xi8>) { + // expected-error @+1 {{op failed to verify that all of {input, output, min_val, max_val} have same element type}} + %3 = spirv.Tosa.Clamp min_val = -102 : i8, max_val = -100 : i16, nan_mode = , %arg0 : !spirv.arm.tensor<27x44x55xi8> -> !spirv.arm.tensor<27x44x55xi8> + spirv.ARM.GraphOutputs %3 : !spirv.arm.tensor<27x44x55xi8> +} diff --git a/mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir b/mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir index 1a43e2c95c530..a9f7bc2b8ef7d 100644 --- a/mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir +++ b/mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir @@ -229,3 +229,58 @@ spirv.ARM.Graph @transposeconv2d_fp(%arg0: !spirv.arm.tensor<10x24x9x13xf16>, %a // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<10x25x65x14xf16> spirv.ARM.GraphOutputs %6 : !spirv.arm.tensor<10x25x65x14xf16> } + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Clamp - PRO-INT +//===----------------------------------------------------------------------===// + +spirv.ARM.Graph @clamp_int(%arg0: !spirv.arm.tensor<27x44x55xi8>) -> (!spirv.arm.tensor<27x44x55xi8>) { + // CHECK: {{%.*}} = spirv.Tosa.Clamp min_val = -102 : i8, max_val = -100 : i8, nan_mode = , %arg0 : !spirv.arm.tensor<27x44x55xi8> -> !spirv.arm.tensor<27x44x55xi8> + %3 = spirv.Tosa.Clamp min_val = -102 : i8, max_val = -100 : i8, nan_mode = , %arg0 : !spirv.arm.tensor<27x44x55xi8> -> !spirv.arm.tensor<27x44x55xi8> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<27x44x55xi8> + spirv.ARM.GraphOutputs %3 : !spirv.arm.tensor<27x44x55xi8> +} + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Clamp - PRO-FP +//===----------------------------------------------------------------------===// + +spirv.ARM.Graph @clamp_fp(%arg0: !spirv.arm.tensor<18x5x17x6xf32>) -> (!spirv.arm.tensor<18x5x17x6xf32>) { + // CHECK: {{%.*}} = spirv.Tosa.Clamp min_val = -1.19339396E+38 : f32, max_val = 2.38255944E+38 : f32, nan_mode = , %arg0 : !spirv.arm.tensor<18x5x17x6xf32> -> !spirv.arm.tensor<18x5x17x6xf32> + %3 = spirv.Tosa.Clamp min_val = -1.19339396E+38 : f32, max_val = 2.38255944E+38 : f32, nan_mode = , %arg0 : !spirv.arm.tensor<18x5x17x6xf32> -> !spirv.arm.tensor<18x5x17x6xf32> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<18x5x17x6xf32> + spirv.ARM.GraphOutputs %3 : !spirv.arm.tensor<18x5x17x6xf32> +} + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Erf - PRO-FP +//===----------------------------------------------------------------------===// + +spirv.ARM.Graph @erf_fp(%arg0: !spirv.arm.tensor<47x38x51xf32>) -> (!spirv.arm.tensor<47x38x51xf32>) { + // CHECK: {{%.*}} = spirv.Tosa.Erf %arg0 : !spirv.arm.tensor<47x38x51xf32> -> !spirv.arm.tensor<47x38x51xf32> + %0 = spirv.Tosa.Erf %arg0 : !spirv.arm.tensor<47x38x51xf32> -> !spirv.arm.tensor<47x38x51xf32> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<47x38x51xf32> + spirv.ARM.GraphOutputs %0 : !spirv.arm.tensor<47x38x51xf32> +} + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Sigmoid - PRO-FP +//===----------------------------------------------------------------------===// + +spirv.ARM.Graph @sigmoid_fp(%arg0: !spirv.arm.tensor<28x43x45xf32>) -> (!spirv.arm.tensor<28x43x45xf32>) { + // CHECK: {{%.*}} = spirv.Tosa.Sigmoid %arg0 : !spirv.arm.tensor<28x43x45xf32> -> !spirv.arm.tensor<28x43x45xf32> + %0 = spirv.Tosa.Sigmoid %arg0 : !spirv.arm.tensor<28x43x45xf32> -> !spirv.arm.tensor<28x43x45xf32> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<28x43x45xf32> + spirv.ARM.GraphOutputs %0 : !spirv.arm.tensor<28x43x45xf32> +} + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Tanh - PRO-FP +//===----------------------------------------------------------------------===// + +spirv.ARM.Graph @tanh_fp(%arg0: !spirv.arm.tensor<46x50x36xf16>) -> (!spirv.arm.tensor<46x50x36xf16>) { + // CHECK: {{%.*}} = spirv.Tosa.Tanh %arg0 : !spirv.arm.tensor<46x50x36xf16> -> !spirv.arm.tensor<46x50x36xf16> + %0 = spirv.Tosa.Tanh %arg0 : !spirv.arm.tensor<46x50x36xf16> -> !spirv.arm.tensor<46x50x36xf16> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<46x50x36xf16> + spirv.ARM.GraphOutputs %0 : !spirv.arm.tensor<46x50x36xf16> +} diff --git a/mlir/test/Dialect/SPIRV/IR/types.mlir b/mlir/test/Dialect/SPIRV/IR/types.mlir index f350e56255983..98509fb376acf 100644 --- a/mlir/test/Dialect/SPIRV/IR/types.mlir +++ b/mlir/test/Dialect/SPIRV/IR/types.mlir @@ -120,6 +120,16 @@ func.func private @unknown_storage_class(!spirv.ptr) -> ( // ----- +// expected-error @+1 {{SPIR-V does not allow one-element vectors}} +func.func private @invalid_ptr_to_vector_one_element(!spirv.ptr, SomeStorageClass>) -> () + +// ----- + +// expected-error @+1 {{vector element type must be a SPIR-V scalar type}} +func.func private @invalid_ptr_to_vector_index(!spirv.ptr, SomeStorageClass>) -> () + +// ----- + //===----------------------------------------------------------------------===// // RuntimeArrayType //===----------------------------------------------------------------------===// @@ -631,3 +641,15 @@ func.func private @arm_tensor_type_unranked(!spirv.arm.tensor<*xi32>) -> () // expected-error @+1 {{arm.tensors do not support zero dimensions}} func.func private @arm_tensor_type_zero_dim(!spirv.arm.tensor<0xi32>) -> () + +// ----- + +//===----------------------------------------------------------------------===// +// Float8_EXT +//===----------------------------------------------------------------------===// + +// CHECK: func private @type_f8E4M3FN(f8E4M3FN) +func.func private @type_f8E4M3FN(f8E4M3FN) -> () + +// CHECK: func private @type_f8E5M2(f8E5M2) +func.func private @type_f8E5M2(f8E5M2) -> () diff --git a/mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir b/mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir index 56e26eee83ff9..0a413e5036be9 100644 --- a/mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir +++ b/mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir @@ -55,18 +55,6 @@ spirv.module Logical GLSL450 requires #spirv.vce>> } - spirv.func @array_of_one_splat_array_of_vector_of_one_i32() -> !spirv.array<1 x !spirv.array<2 x vector<1xi32>>> "None" { - // CHECK: {{%.*}} = spirv.EXT.ConstantCompositeReplicate [dense<1> : vector<1xi32>] : !spirv.array<1 x !spirv.array<2 x vector<1xi32> - %cst = spirv.Constant [[dense<1> : vector<1xi32>], [dense<1> : vector<1xi32>]] : !spirv.array<1 x !spirv.array<2 x vector<1xi32>>> - spirv.ReturnValue %cst : !spirv.array<1 x !spirv.array<2 x vector<1xi32>>> - } - - spirv.func @splat_array_of_array_of_one_vector_of_one_i32() -> (!spirv.array<2 x !spirv.array<1 x vector<1xi32>>>) "None" { - // CHECK: {{%.*}} = spirv.EXT.ConstantCompositeReplicate [dense<1> : vector<1xi32>] : !spirv.array<2 x !spirv.array<1 x vector<1xi32>>> - %0 = spirv.Constant [[dense<1> : vector<1xi32>], [dense<1> : vector<1xi32>]] : !spirv.array<2 x !spirv.array<1 x vector<1xi32>>> - spirv.ReturnValue %0 : !spirv.array<2 x !spirv.array<1 x vector<1xi32>>> - } - spirv.func @array_of_one_array_of_one_splat_vector_of_i32() -> (!spirv.array<1 x !spirv.array<1 x vector<2xi32>>>) "None" { // CHECK: {{%.*}} = spirv.EXT.ConstantCompositeReplicate [1 : i32] : !spirv.array<1 x !spirv.array<1 x vector<2xi32>>> %0 = spirv.Constant [[dense<1> : vector<2xi32>]] : !spirv.array<1 x !spirv.array<1 x vector<2xi32>>> @@ -133,18 +121,6 @@ spirv.module Logical GLSL450 requires #spirv.vce>> } - spirv.func @array_of_one_splat_array_of_vector_of_one_f32() -> !spirv.array<1 x !spirv.array<2 x vector<1xf32>>> "None" { - // CHECK: {{%.*}} = spirv.EXT.ConstantCompositeReplicate [dense<1.000000e+00> : vector<1xf32>] : !spirv.array<1 x !spirv.array<2 x vector<1xf32> - %cst = spirv.Constant [[dense<1.0> : vector<1xf32>], [dense<1.0> : vector<1xf32>]] : !spirv.array<1 x !spirv.array<2 x vector<1xf32>>> - spirv.ReturnValue %cst : !spirv.array<1 x !spirv.array<2 x vector<1xf32>>> - } - - spirv.func @splat_array_of_array_of_one_vector_of_one_f32() -> (!spirv.array<2 x !spirv.array<1 x vector<1xf32>>>) "None" { - // CHECK: {{%.*}} = spirv.EXT.ConstantCompositeReplicate [dense<1.000000e+00> : vector<1xf32>] : !spirv.array<2 x !spirv.array<1 x vector<1xf32>>> - %0 = spirv.Constant [[dense<1.0> : vector<1xf32>], [dense<1.0> : vector<1xf32>]] : !spirv.array<2 x !spirv.array<1 x vector<1xf32>>> - spirv.ReturnValue %0 : !spirv.array<2 x !spirv.array<1 x vector<1xf32>>> - } - spirv.func @array_of_one_array_of_one_splat_vector_of_f32() -> (!spirv.array<1 x !spirv.array<1 x vector<2xf32>>>) "None" { // CHECK: {{%.*}} = spirv.EXT.ConstantCompositeReplicate [1.000000e+00 : f32] : !spirv.array<1 x !spirv.array<1 x vector<2xf32>>> %0 = spirv.Constant [[dense<1.0> : vector<2xf32>]] : !spirv.array<1 x !spirv.array<1 x vector<2xf32>>> @@ -210,12 +186,6 @@ spirv.module Logical GLSL450 requires #spirv.vce : vector<2xi32>]] : !spirv.array<1 x !spirv.array<1 x vector<2xi32>>> spirv.ReturnValue %0 : !spirv.array<1 x !spirv.array<1 x vector<2xi32>>> } - - spirv.func @array_of_one_array_of_one_vector_of_one_i32() -> (!spirv.array<1 x !spirv.array<1 x vector<1xi32>>>) "None" { - // CHECK-NOT spirv.EXT.ConstantCompositeReplicate - %0 = spirv.Constant [[dense<1> : vector<1xi32>]] : !spirv.array<1 x !spirv.array<1 x vector<1xi32>>> - spirv.ReturnValue %0 : !spirv.array<1 x !spirv.array<1 x vector<1xi32>>> - } } // ----- diff --git a/mlir/test/Dialect/Shard/partition.mlir b/mlir/test/Dialect/Shard/partition.mlir index 0f293a39608e3..cd9fa2215e0ee 100644 --- a/mlir/test/Dialect/Shard/partition.mlir +++ b/mlir/test/Dialect/Shard/partition.mlir @@ -3,6 +3,7 @@ // RUN: %s | FileCheck %s shard.grid @grid_1d(shape = 2) +shard.grid @grid_1d_4(shape = 4) // CHECK-LABEL: func @return_sharding func.func @return_sharding( @@ -204,8 +205,6 @@ func.func @incomplete_sharding( return %3 : tensor<8x16xf32> } -shard.grid @grid_1d_4(shape = 4) - // CHECK-LABEL: func @ew_chain_with_halo func.func @ew_chain_with_halo( // CHECK-SAME: %[[IN1:[A-Za-z0-9_]+]]: tensor<5x16xf32> @@ -318,3 +317,56 @@ func.func @test_reduce_1d(%arg0: tensor<6x6xi32>) -> (tensor<6xi32>) { // CHECK: return %[[reduced]] : tensor<3xi32> return %sharded_ret : tensor<6xi32> } + +// CHECK-LABEL: func.func @mlp_1dgrid +// CHECK-SAME: [[varg0:%.*]]: tensor<512x512xf32>, [[varg1:%.*]]: tensor<2048x256xf32>, [[varg2:%.*]]: tensor<256x2048xf32>) -> tensor<512x2048xf32> +func.func @mlp_1dgrid(%arg0: tensor<512x2048xf32>, %arg1: tensor<2048x1024xf32>, %arg2: tensor<1024x2048xf32>) -> tensor<512x2048xf32> attributes {llvm.emit_c_interface} { + // CHECK: [[vcst:%.*]] = arith.constant 0.000000e+00 : f32 + %sharding = shard.sharding @grid_1d_4 split_axes = [[], [0]] : !shard.sharding + %sharding_0 = shard.sharding @grid_1d_4 split_axes = [[0], []] : !shard.sharding + %sharding_1 = shard.sharding @grid_1d_4 split_axes = [[]] : !shard.sharding + %sharding_2 = shard.sharding @grid_1d_4 split_axes = [[], [0]] : !shard.sharding + %sharding_3 = shard.sharding @grid_1d_4 split_axes = [[], [0]] : !shard.sharding + %sharding_4 = shard.sharding @grid_1d_4 split_axes = [[0], []] : !shard.sharding + %sharding_5 = shard.sharding @grid_1d_4 split_axes = [[]] : !shard.sharding + %sharding_annotated = shard.shard %arg0 to %sharding_2 : tensor<512x2048xf32> + %sharding_annotated_6 = shard.shard %arg1 to %sharding_3 : tensor<2048x1024xf32> + %sharding_annotated_7 = shard.shard %arg2 to %sharding_4 : tensor<1024x2048xf32> + // CHECK-DAG: [[v0:%.*]] = tensor.empty() : tensor<512x256xf32> + %0 = tensor.empty() : tensor<512x1024xf32> + %sharding_annotated_8 = shard.shard %0 to %sharding : tensor<512x1024xf32> + %cst = arith.constant 0.000000e+00 : f32 + %sharding_annotated_9 = shard.shard %sharding_annotated_8 to %sharding annotate_for_users : tensor<512x1024xf32> + // CHECK-DAG: [[v1:%.*]] = linalg.fill ins([[vcst]] : f32) outs([[v0]] : tensor<512x256xf32>) -> tensor<512x256xf32> + %1 = linalg.fill ins(%cst : f32) outs(%sharding_annotated_9 : tensor<512x1024xf32>) -> tensor<512x1024xf32> + %sharding_annotated_10 = shard.shard %1 to %sharding : tensor<512x1024xf32> + // CHECK-DAG: [[vall_gather:%.*]] = shard.all_gather [[varg0]] on @grid_1d_4 grid_axes = [0] gather_axis = 1 : tensor<512x512xf32> -> tensor<512x2048xf32> + %sharding_annotated_11 = shard.shard %sharding_annotated to %sharding_1 annotate_for_users : tensor<512x2048xf32> + %sharding_annotated_12 = shard.shard %sharding_annotated_6 to %sharding annotate_for_users : tensor<2048x1024xf32> + %sharding_annotated_13 = shard.shard %sharding_annotated_10 to %sharding annotate_for_users : tensor<512x1024xf32> + // CHECK: [[v2:%.*]] = linalg.matmul ins([[vall_gather]], [[varg1]] : tensor<512x2048xf32>, tensor<2048x256xf32>) outs([[v1]] : tensor<512x256xf32>) -> tensor<512x256xf32> + %2 = linalg.matmul ins(%sharding_annotated_11, %sharding_annotated_12 : tensor<512x2048xf32>, tensor<2048x1024xf32>) outs(%sharding_annotated_13 : tensor<512x1024xf32>) -> tensor<512x1024xf32> + %sharding_annotated_14 = shard.shard %2 to %sharding : tensor<512x1024xf32> + %sharding_annotated_15 = shard.shard %sharding_annotated_14 to %sharding annotate_for_users : tensor<512x1024xf32> + // CHECK: [[v3:%.*]] = tosa.sigmoid [[v2]] : (tensor<512x256xf32>) -> tensor<512x256xf32> + %3 = tosa.sigmoid %sharding_annotated_15 : (tensor<512x1024xf32>) -> tensor<512x1024xf32> + %sharding_annotated_16 = shard.shard %3 to %sharding : tensor<512x1024xf32> + // CHECK: [[v9:%.*]] = tensor.empty() : tensor<512x2048xf32> + %4 = tensor.empty() : tensor<512x2048xf32> + %sharding_annotated_17 = shard.shard %4 to %sharding_1 : tensor<512x2048xf32> + %sharding_annotated_18 = shard.shard %sharding_annotated_17 to %sharding_1 annotate_for_users : tensor<512x2048xf32> + // CHECK: [[v10:%.*]] = linalg.fill ins([[vcst]] : f32) outs([[v9]] : tensor<512x2048xf32>) -> tensor<512x2048xf32> + %5 = linalg.fill ins(%cst : f32) outs(%sharding_annotated_18 : tensor<512x2048xf32>) -> tensor<512x2048xf32> + %sharding_annotated_19 = shard.shard %5 to %sharding_1 : tensor<512x2048xf32> + %sharding_annotated_20 = shard.shard %sharding_annotated_16 to %sharding annotate_for_users : tensor<512x1024xf32> + %sharding_annotated_21 = shard.shard %sharding_annotated_7 to %sharding_0 annotate_for_users : tensor<1024x2048xf32> + %sharding_annotated_22 = shard.shard %sharding_annotated_19 to %sharding_1 annotate_for_users : tensor<512x2048xf32> + // CHECK: [[v7:%.*]] = scf.if + // CHECK: [[v8:%.*]] = linalg.matmul ins([[v3]], [[varg2]] : tensor<512x256xf32>, tensor<256x2048xf32>) outs([[v7]] : tensor<512x2048xf32>) -> tensor<512x2048xf32> + %6 = linalg.matmul ins(%sharding_annotated_20, %sharding_annotated_21 : tensor<512x1024xf32>, tensor<1024x2048xf32>) outs(%sharding_annotated_22 : tensor<512x2048xf32>) -> tensor<512x2048xf32> + %sharding_annotated_23 = shard.shard %6 to %sharding_1 : tensor<512x2048xf32> + // CHECK: [[vall_reduce:%.*]] = shard.all_reduce [[v8]] on @grid_1d_4 grid_axes = [0] : tensor<512x2048xf32> -> tensor<512x2048xf32> + %sharding_annotated_24 = shard.shard %sharding_annotated_23 to %sharding_5 annotate_for_users : tensor<512x2048xf32> + // CHECK: return [[vall_reduce]] : tensor<512x2048xf32> + return %sharding_annotated_24 : tensor<512x2048xf32> +} diff --git a/mlir/test/Dialect/Tensor/canonicalize.mlir b/mlir/test/Dialect/Tensor/canonicalize.mlir index f85831b6f4cab..7a2d53c0c5850 100644 --- a/mlir/test/Dialect/Tensor/canonicalize.mlir +++ b/mlir/test/Dialect/Tensor/canonicalize.mlir @@ -1281,7 +1281,7 @@ func.func @compose_collapse_of_expand_partially_dynamic(%arg0: tensor, %a // CHECK-SAME: %[[ORIG_D2:.[a-zA-Z0-9]+]] // CHECK-SAME: %[[ORIG_D3:.[a-zA-Z0-9]+]] // CHECK-DAG: %[[C32:.+]] = arith.constant 32 -// CHECK: %[[COLLAPSED_D2:.+]] = arith.muli %[[ORIG_D3]], %[[C32]] +// CHECK: %[[COLLAPSED_D2:.+]] = arith.muli %[[ORIG_D3]], %[[C32]] overflow // CHECK: %[[RESULT:.+]] = tensor.expand_shape %[[SRC]] // CHECK-SAME: [0, 1, 2] // CHECK-SAME: output_shape [8, %[[ORIG_D2]], %[[COLLAPSED_D2]]] diff --git a/mlir/test/Dialect/Tensor/invalid.mlir b/mlir/test/Dialect/Tensor/invalid.mlir index 63be5493e8935..0483dcaa3c6f0 100644 --- a/mlir/test/Dialect/Tensor/invalid.mlir +++ b/mlir/test/Dialect/Tensor/invalid.mlir @@ -690,3 +690,29 @@ func.func @test_empty_reassociation(%arg0: tensor<1x?xf32>) -> tensor return %0 : tensor } +// ----- + +func.func @collapse_shape_requires_ranked_tensor(%arg0: tensor<*xf32>) { + // expected-error@+1 {{custom op 'tensor.collapse_shape' invalid kind of type specified: expected builtin.tensor, but found 'tensor<*xf32>'}} + %0 = tensor.collapse_shape %arg0 [[0]] : tensor<*xf32> into tensor + return +} + +// ----- + +func.func @expand_shape_requires_ranked_tensor(%arg0: tensor<*xf32>) { + // expected-error@+1 {{custom op 'tensor.expand_shape' invalid kind of type specified: expected builtin.tensor, but found 'tensor<*xf32>'}} + %0 = tensor.expand_shape %arg0 [[0]] output_shape [1] : tensor<*xf32> into tensor<1xf32> + return +} + +// ----- + + +func.func @no_fold_invalid_collapse() -> tensor { + %c = arith.constant dense<[1, 2, 3]> : tensor<3xi64> + // expected-error@below {{'tensor.collapse_shape' op number of elements must be preserved: 3 != 1}} + %0 = tensor.collapse_shape %c [] : tensor<3xi64> into tensor + return %0 : tensor +} + diff --git a/mlir/test/Dialect/Tosa/constant_folding.mlir b/mlir/test/Dialect/Tosa/constant_folding.mlir index 4cb9a46e5d049..c3186279a30ae 100644 --- a/mlir/test/Dialect/Tosa/constant_folding.mlir +++ b/mlir/test/Dialect/Tosa/constant_folding.mlir @@ -695,6 +695,17 @@ func.func @test_fold_dim(%arg0: tensor<6xi32>) -> !tosa.shape<1> { // ----- +// CHECK-LABEL: @test_fold_sub_shape +// CHECK: tosa.const_shape {values = dense<[2, 4, 6, 8, 10, 12]> : tensor<6xindex>} : () -> !tosa.shape<6> +func.func @test_fold_sub_shape() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[12, 22, 32, 42, 52, 62]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[10, 18, 26, 34, 42, 50]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.sub_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + // CHECK-LABEL: @test_no_fold_dim_unranked_input // CHECK: tosa.dim func.func @test_no_fold_dim_unranked_input(%arg0: tensor<*xi32>) -> !tosa.shape<1> { @@ -704,9 +715,185 @@ func.func @test_no_fold_dim_unranked_input(%arg0: tensor<*xi32>) -> !tosa.shape< // ----- +// CHECK-LABEL: @test_no_fold_sub_shape_positive_overflow +// CHECK: tosa.sub_shape +func.func @test_no_fold_sub_shape_positive_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[1, 2, 3, 4, 5, 9223372036854775807]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 3, 4, 5, -1]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.sub_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + // CHECK-LABEL: @test_no_fold_dim_dynamic // CHECK: tosa.dim func.func @test_no_fold_dim_dynamic(%arg0: tensor<4x?xi32>) -> !tosa.shape<1> { %dim = tosa.dim %arg0 {axis = 1 : i32} : (tensor<4x?xi32>) -> !tosa.shape<1> return %dim : !tosa.shape<1> } + +// ----- + +// CHECK-LABEL: @test_no_fold_sub_shape_negative_overflow +// CHECK: tosa.sub_shape +func.func @test_no_fold_sub_shape_negative_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[1, 2, 3, 4, 5, -9223372036854775808]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 3, 4, 5, 1]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.sub_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_fold_mul_shape +// CHECK: tosa.const_shape {values = dense<[2, 4, 6, 8, 10, 12]> : tensor<6xindex>} : () -> !tosa.shape<6> +func.func @test_fold_mul_shape() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[2, 2, 3, 4, 2, 3]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 2, 2, 5, 4]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.mul_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_no_fold_mul_shape_positive_overflow +// CHECK: tosa.mul_shape +func.func @test_no_fold_mul_shape_positive_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[1, 2, 3, 4, 5, 9223372036854775807]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 3, 4, 5, 2]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.mul_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_no_fold_mul_shape_negative_overflow +// CHECK: tosa.mul_shape +func.func @test_no_fold_mul_shape_negative_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[1, 2, 3, 4, 5, -9223372036854775808]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 3, 4, 5, 2]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.mul_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_fold_div_ceil_shape +// CHECK: tosa.const_shape {values = dense<[2, 4, 6, 8, 10, 12]> : tensor<6xindex>} : () -> !tosa.shape<6> +func.func @test_fold_div_ceil_shape() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[2, 7, 11, 22, 47, 46]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 2, 3, 5, 4]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.div_ceil_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_no_fold_div_ceil_shape_positive_overflow +// CHECK: tosa.div_ceil_shape +func.func @test_no_fold_div_ceil_shape_positive_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[2, 7, 11, 22, 47, 9223372036854775807]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 2, 3, 5, 0]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.div_ceil_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_no_fold_div_ceil_shape_negative_overflow +// CHECK: tosa.div_ceil_shape +func.func @test_no_fold_div_ceil_shape_negative_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[2, 7, 11, 22, 47, -9223372036854775808]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 2, 3, 5, 0]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.div_ceil_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_fold_div_floor_shape +// CHECK: tosa.const_shape {values = dense<[2, 3, 5, 7, 9, 11]> : tensor<6xindex>} : () -> !tosa.shape<6> +func.func @test_fold_div_floor_shape() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[2, 7, 11, 22, 47, 46]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 2, 3, 5, 4]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.div_floor_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_no_fold_div_floor_shape_positive_overflow +// CHECK: tosa.div_floor_shape +func.func @test_no_fold_div_floor_shape_positive_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[2, 7, 11, 22, 47, 9223372036854775807]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 2, 3, 5, 0]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.div_floor_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_no_fold_div_floor_shape_negative_overflow +// CHECK: tosa.div_floor_shape +func.func @test_no_fold_div_floor_shape_negative_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[2, 7, 11, 22, 47, -9223372036854775808]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[1, 2, 2, 3, 5, 0]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.div_floor_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_fold_mod_shape +// CHECK: tosa.const_shape {values = dense<[2, 1, 5, 7, 9, 11]> : tensor<6xindex>} : () -> !tosa.shape<6> +func.func @test_fold_mod_shape() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[24, 7, 65, 33, 39, 39]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[11, 2, 12, 13, 15, 14]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.mod_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_no_fold_mod_shape_positive_overflow +// CHECK: tosa.mod_shape +func.func @test_no_fold_mod_shape_positive_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[24, 7, 65, 33, 39, 9223372036854775807]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[11, 2, 12, 13, 15, 0]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.mod_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_no_fold_mod_shape_negative_overflow +// CHECK: tosa.mod_shape +func.func @test_no_fold_mod_shape_negative_overflow() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[24, 7, 65, 33, 39, -9223372036854775808]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[11, 2, 12, 13, 15, 0]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.mod_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_max_shape +// CHECK: tosa.const_shape {values = dense<[24, 7, 65, 33, 39, 5]> : tensor<6xindex>} : () -> !tosa.shape<6> +func.func @test_max_shape() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[24, 7, 65, 33, 39, 1]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[11, 2, 12, 13, 15, 5]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.max_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} + +// ----- + +// CHECK-LABEL: @test_min_shape +// CHECK: tosa.const_shape {values = dense<[11, 2, 12, 13, 15, 1]> : tensor<6xindex>} : () -> !tosa.shape<6> +func.func @test_min_shape() -> !tosa.shape<6> { + %a = tosa.const_shape {values = dense<[24, 7, 65, 33, 39, 1]> : tensor<6xindex>} : () -> !tosa.shape<6> + %b = tosa.const_shape {values = dense<[11, 2, 12, 13, 15, 5]> : tensor<6xindex>} : () -> !tosa.shape<6> + %c = tosa.min_shape %a, %b : (!tosa.shape<6>, !tosa.shape<6>) -> !tosa.shape<6> + return %c : !tosa.shape<6> +} diff --git a/mlir/test/Dialect/Tosa/level_check.mlir b/mlir/test/Dialect/Tosa/level_check.mlir index 216f05a484927..739af6bcac2d8 100644 --- a/mlir/test/Dialect/Tosa/level_check.mlir +++ b/mlir/test/Dialect/Tosa/level_check.mlir @@ -1693,34 +1693,6 @@ func.func @test_dim(%arg0: tensor<1x2x3x4x5x6x7x8xi32>) -> !tosa.shape<1> { // ----- -func.func @test_concat_shape_invalid_list_size() { - %0 = tosa.const_shape {values = dense<[]> : tensor<0xindex>} : () -> !tosa.shape<0> - // expected-error@+1 {{'tosa.concat_shape' op failed level check: length(tensor_list_shape(input)) <= MAX_TENSOR_LIST_SIZE (64), got 65}} - %1 = tosa.concat_shape %0, %0, %0, %0, %0, %0, %0, %0, - %0, %0, %0, %0, %0, %0, %0, %0, - %0, %0, %0, %0, %0, %0, %0, %0, - %0, %0, %0, %0, %0, %0, %0, %0, - %0, %0, %0, %0, %0, %0, %0, %0, - %0, %0, %0, %0, %0, %0, %0, %0, - %0, %0, %0, %0, %0, %0, %0, %0, - %0, %0, %0, %0, %0, %0, %0, %0, - %0 : - ( - !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, - !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, - !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, - !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, - !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, - !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, - !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, - !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>, - !tosa.shape<0> - ) -> !tosa.shape<0> - return -} - -// ----- - func.func @test_exp2_shape_invalid_rank() -> !tosa.shape<17> { %0 = tosa.const_shape {values = dense<0> : tensor<17xindex>} : () -> !tosa.shape<17> // expected-error@+1 {{'tosa.exp2_shape' op failed shape type level check: '!tosa.shape<17>' exceeds MAX_SHAPE_LEN}} diff --git a/mlir/test/Dialect/Tosa/ops.mlir b/mlir/test/Dialect/Tosa/ops.mlir index 44cfd5cfc9400..56811891e8f95 100644 --- a/mlir/test/Dialect/Tosa/ops.mlir +++ b/mlir/test/Dialect/Tosa/ops.mlir @@ -1499,16 +1499,6 @@ func.func @test_concat_shape() -> !tosa.shape<5> { return %3 : !tosa.shape<5> } -// ----- -// CHECK-LABEL: test_concat_shape_rank_0 -func.func @test_concat_shape_rank_0() -> !tosa.shape<0> { - %0 = tosa.const_shape {values = dense<[]> : tensor<0xindex>} : () -> !tosa.shape<0> - %1 = tosa.const_shape {values = dense<[]> : tensor<0xindex>} : () -> !tosa.shape<0> - %2 = tosa.const_shape {values = dense<[]> : tensor<0xindex>} : () -> !tosa.shape<0> - %3 = tosa.concat_shape %0, %1, %2 : (!tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>) -> !tosa.shape<0> - return %3 : !tosa.shape<0> -} - // ----- // CHECK-LABEL: test_slice_shape func.func @test_slice_shape() -> !tosa.shape<3> { diff --git a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir index bc5f41b1af304..0deb31dab1c6f 100644 --- a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir +++ b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir @@ -251,6 +251,24 @@ func.func @test_binary_i1(%arg0 : tensor<4xi1>, %arg1 : tensor<1xi1>) -> () { // ----- +// CHECK-LABEL: @test_dynamic_binary_broadcast +func.func @test_dynamic_binary_broadcast(%arg0: tensor<1x?xf32>, %arg1: tensor<2x1xf32>) -> tensor<*xi1> { + // CHECK tosa.equal %arg0, %arg1 : (tensor<1x?xf32>, tensor<2x1xf32>) -> tensor<2x?xi1> + %0 = tosa.equal %arg0, %arg1 : (tensor<1x?xf32>, tensor<2x1xf32>) -> tensor<*xi1> + return %0 : tensor<*xi1> +} + +// ----- + +// CHECK-LABEL: @test_resolvable_dynamic_binary_broadcast +func.func @test_resolvable_dynamic_binary_broadcast(%arg0: tensor<1x?xf32>, %arg1: tensor<2x4xf32>) -> tensor<*xi1> { + // CHECK tosa.equal %arg0, %arg1 : (tensor<1x?xf32>, tensor<2x4xf32>) -> tensor<2x4xi1> + %0 = tosa.equal %arg0, %arg1 : (tensor<1x?xf32>, tensor<2x4xf32>) -> tensor<*xi1> + return %0 : tensor<*xi1> +} + +// ----- + // CHECK-LABEL: @test_select_i32 func.func @test_select_i32(%arg0 : tensor<4xi1>, %arg1 : tensor<1xi32>, %arg2 : tensor<4xi32>) -> () { // CHECK: tosa.select %arg0, %arg1, %arg2 : (tensor<4xi1>, tensor<1xi32>, tensor<4xi32>) -> tensor<4xi32> diff --git a/mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir b/mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir index fe38e2f61b2e8..fbd935d56fcc6 100644 --- a/mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir +++ b/mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir @@ -62,6 +62,70 @@ func.func @test_transpose_conv2d_fp8_acc32(%arg0: tensor<1x32x32x8xf8E5M2>, %arg // ----- +func.func @test_gather_bool_i64(%arg0: tensor<13x21x3xi1>, %arg1: tensor<13x26xi64>) -> tensor<13x26x3xi1> { + // expected-error@+1 {{'tosa.gather' op illegal: requires [int64] but not enabled in target}} + %0 = tosa.gather %arg0, %arg1 : (tensor<13x21x3xi1>, tensor<13x26xi64>) -> tensor<13x26x3xi1> + return %0 : tensor<13x26x3xi1> +} + +// ----- + +func.func @test_gather_bool_i32(%arg0: tensor<13x21x3xi1>, %arg1: tensor<13x26xi32>) -> tensor<13x26x3xi1> { + // expected-error@+1 {{'tosa.gather' op illegal: the target specification version (1.0) is not backwards compatible with the op compliance specification version (1.1)}} + %0 = tosa.gather %arg0, %arg1 : (tensor<13x21x3xi1>, tensor<13x26xi32>) -> tensor<13x26x3xi1> + return %0 : tensor<13x26x3xi1> +} + +// ----- + +func.func @test_scatter_bool_i64(%arg0: tensor<13x52x3xi1>, %arg1: tensor<13x26xi64>, %arg2: tensor<13x26x3xi1>) -> tensor<13x52x3xi1> { + // expected-error@+1 {{'tosa.scatter' op illegal: requires [int64] but not enabled in target}} + %0 = tosa.scatter %arg0, %arg1, %arg2 : (tensor<13x52x3xi1>, tensor<13x26xi64>, tensor<13x26x3xi1>) -> tensor<13x52x3xi1> + return %0 : tensor<13x52x3xi1> +} + +// ----- + +func.func @test_scatter_bool_i32(%arg0: tensor<13x52x3xi1>, %arg1: tensor<13x26xi32>, %arg2: tensor<13x26x3xi1>) -> tensor<13x52x3xi1> { + // expected-error@+1 {{'tosa.scatter' op illegal: the target specification version (1.0) is not backwards compatible with the op compliance specification version (1.1)}} + %0 = tosa.scatter %arg0, %arg1, %arg2 : (tensor<13x52x3xi1>, tensor<13x26xi32>, tensor<13x26x3xi1>) -> tensor<13x52x3xi1> + return %0 : tensor<13x52x3xi1> +} + +// ----- + +func.func @test_cast_bool_fp32(%arg0: tensor<13x21x3xi1>) -> tensor<13x21x3xf32> { + // expected-error@+1 {{'tosa.cast' op illegal: the target specification version (1.0) is not backwards compatible with the op compliance specification version (1.1)}} + %0 = tosa.cast %arg0 : (tensor<13x21x3xi1>) -> tensor<13x21x3xf32> + return %0 : tensor<13x21x3xf32> +} + +// ----- + +func.func @test_cast_bool_i64(%arg0: tensor<13x21x3xi1>) -> tensor<13x21x3xi64> { + // expected-error@+1 {{'tosa.cast' op illegal: requires [int64] but not enabled in target}} + %0 = tosa.cast %arg0 : (tensor<13x21x3xi1>) -> tensor<13x21x3xi64> + return %0 : tensor<13x21x3xi64> +} + +// ----- + +func.func @test_cast_fp32_bool(%arg0: tensor<13x21x3xf32>) -> tensor<13x21x3xi1> { + // expected-error@+1 {{'tosa.cast' op illegal: the target specification version (1.0) is not backwards compatible with the op compliance specification version (1.1)}} + %0 = tosa.cast %arg0 : (tensor<13x21x3xf32>) -> tensor<13x21x3xi1> + return %0 : tensor<13x21x3xi1> +} + +// ----- + +func.func @test_cast_i64_bool(%arg0: tensor<13x21x3xi64>) -> tensor<13x21x3xi1> { + // expected-error@+1 {{'tosa.cast' op illegal: requires [int64] but not enabled in target}} + %0 = tosa.cast %arg0 : (tensor<13x21x3xi64>) -> tensor<13x21x3xi1> + return %0 : tensor<13x21x3xi1> +} + +// ----- + func.func @test_dyanmic_dims(%arg0: tensor) -> tensor { // expected-error@+1 {{'tosa.argmax' op failed level check: operand shape dimension cannot be dynamic when targeting TOSA specification version 1.0 or below}} %0 = tosa.argmax %arg0 { axis = 1 : i32 } : (tensor) -> tensor diff --git a/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir b/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir index 97fb14927f7e8..72269d21f3d98 100644 --- a/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir +++ b/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir @@ -183,6 +183,70 @@ func.func @test_scatter_const_indices_int64(%arg0: tensor<2x52x3xf32>, %arg2: te // ----- +// CHECK-LABEL: test_gather_bool_i64 +func.func @test_gather_bool_i64(%arg0: tensor<13x21x3xi1>, %arg1: tensor<13x26xi64>) -> tensor<13x26x3xi1> { + %0 = tosa.gather %arg0, %arg1 : (tensor<13x21x3xi1>, tensor<13x26xi64>) -> tensor<13x26x3xi1> + return %0 : tensor<13x26x3xi1> +} + +// ----- + +// CHECK-LABEL: test_gather_bool_i32 +func.func @test_gather_bool_i32(%arg0: tensor<13x21x3xi1>, %arg1: tensor<13x26xi32>) -> tensor<13x26x3xi1> { + %0 = tosa.gather %arg0, %arg1 : (tensor<13x21x3xi1>, tensor<13x26xi32>) -> tensor<13x26x3xi1> + return %0 : tensor<13x26x3xi1> +} + +// ----- + +// CHECK-LABEL: test_scatter_bool_i64 +func.func @test_scatter_bool_i64(%arg0: tensor<13x52x3xi1>, %arg1: tensor<13x26xi64>, %arg2: tensor<13x26x3xi1>) -> tensor<13x52x3xi1> { + %0 = tosa.scatter %arg0, %arg1, %arg2 : (tensor<13x52x3xi1>, tensor<13x26xi64>, tensor<13x26x3xi1>) -> tensor<13x52x3xi1> + return %0 : tensor<13x52x3xi1> +} + +// ----- + +// CHECK-LABEL: test_scatter_bool_i32 +func.func @test_scatter_bool_i32(%arg0: tensor<13x52x3xi1>, %arg1: tensor<13x26xi32>, %arg2: tensor<13x26x3xi1>) -> tensor<13x52x3xi1> { + %0 = tosa.scatter %arg0, %arg1, %arg2 : (tensor<13x52x3xi1>, tensor<13x26xi32>, tensor<13x26x3xi1>) -> tensor<13x52x3xi1> + return %0 : tensor<13x52x3xi1> +} + +// ----- + +// CHECK-LABEL: test_cast_bool_fp32 +func.func @test_cast_bool_fp32(%arg0: tensor<13x21x3xi1>) -> tensor<13x21x3xf32> { + %0 = tosa.cast %arg0 : (tensor<13x21x3xi1>) -> tensor<13x21x3xf32> + return %0 : tensor<13x21x3xf32> +} + +// ----- + +// CHECK-LABEL: test_cast_bool_i64 +func.func @test_cast_bool_i64(%arg0: tensor<13x21x3xi1>) -> tensor<13x21x3xi64> { + %0 = tosa.cast %arg0 : (tensor<13x21x3xi1>) -> tensor<13x21x3xi64> + return %0 : tensor<13x21x3xi64> +} + +// ----- + +// CHECK-LABEL: test_cast_fp32_bool +func.func @test_cast_fp32_bool(%arg0: tensor<13x21x3xf32>) -> tensor<13x21x3xi1> { + %0 = tosa.cast %arg0 : (tensor<13x21x3xf32>) -> tensor<13x21x3xi1> + return %0 : tensor<13x21x3xi1> +} + +// ----- + +// CHECK-LABEL: test_cast_i64_bool +func.func @test_cast_i64_bool(%arg0: tensor<13x21x3xi64>) -> tensor<13x21x3xi1> { + %0 = tosa.cast %arg0 : (tensor<13x21x3xi64>) -> tensor<13x21x3xi1> + return %0 : tensor<13x21x3xi1> +} + +// ----- + // CHECK-LABEL: test_dynamic_dims func.func @test_dynamic_dims(%arg0: tensor) -> tensor { %0 = tosa.argmax %arg0 { axis = 1 : i32 } : (tensor) -> tensor @@ -250,4 +314,4 @@ func.func @test_assert_equal_shape() { %1 = tosa.const_shape {values = dense<[5, 2]> : tensor<2xindex>} : () -> !tosa.shape<2> tosa.assert_equal_shape %0, %1 {allow_broadcast = true} : (!tosa.shape<2>, !tosa.shape<2>) -> () return -} \ No newline at end of file +} diff --git a/mlir/test/Dialect/Tosa/verifier.mlir b/mlir/test/Dialect/Tosa/verifier.mlir index 742bae3847da5..3621c25005862 100644 --- a/mlir/test/Dialect/Tosa/verifier.mlir +++ b/mlir/test/Dialect/Tosa/verifier.mlir @@ -1284,6 +1284,25 @@ func.func @test_concat_shape_rank_mismatch() -> !tosa.shape<4> { // ----- +func.func @test_concat_shape_no_inputs() -> !tosa.shape<0> { + // expected-error@+1 {{'tosa.concat_shape' op requires at least one input shape}} + %0 = tosa.concat_shape {} : () -> !tosa.shape<0> + return %0 : !tosa.shape<0> +} + +// ----- + +func.func @test_concat_shape_rank_0() -> !tosa.shape<0> { + %0 = tosa.const_shape {values = dense<[]> : tensor<0xindex>} : () -> !tosa.shape<0> + %1 = tosa.const_shape {values = dense<[]> : tensor<0xindex>} : () -> !tosa.shape<0> + %2 = tosa.const_shape {values = dense<[]> : tensor<0xindex>} : () -> !tosa.shape<0> + // expected-error@+1 {{'tosa.concat_shape' op requires all inputs shapes have a rank greater than 0}} + %3 = tosa.concat_shape %0, %1, %2 : (!tosa.shape<0>, !tosa.shape<0>, !tosa.shape<0>) -> !tosa.shape<0> + return %3 : !tosa.shape<0> +} + +// ----- + func.func @test_slice_shape_negative_start() -> !tosa.shape<3> { %0 = tosa.const_shape {values = dense<[4, 5, 6, 7, 8, 9]> : tensor<6xindex>} : () -> !tosa.shape<6> %1 = "tosa.const"() {values = dense<-1> : tensor<1xi32>} : () -> tensor<1xi32> diff --git a/mlir/test/Dialect/Vector/transform-vector.mlir b/mlir/test/Dialect/Vector/transform-vector.mlir index 524a4f429211b..9b22c383aa225 100644 --- a/mlir/test/Dialect/Vector/transform-vector.mlir +++ b/mlir/test/Dialect/Vector/transform-vector.mlir @@ -137,3 +137,35 @@ module attributes {transform.with_named_sequence} { transform.yield } } + +// ----- + +func.func @flatten_transfer_ops(%arg0: memref<16x16xf32>, %arg1: vector<8xf32>) -> vector<8xf32> { + %c0 = arith.constant 0 : index + %c8 = arith.constant 8 : index + %b0 = ub.poison : f32 + %0 = vector.transfer_read %arg0[%c0, %c0], %b0 {in_bounds = [true, true]} : memref<16x16xf32>, vector<1x8xf32> + %1 = vector.transfer_read %arg0[%c0, %c8], %b0 {in_bounds = [true, true]} : memref<16x16xf32>, vector<1x8xf32> + %2 = vector.shape_cast %0 : vector<1x8xf32> to vector<8xf32> + %3 = vector.shape_cast %1 : vector<1x8xf32> to vector<8xf32> + %4 = vector.fma %2, %3, %arg1 : vector<8xf32> + return %4 : vector<8xf32> +} + +// CHECK-LABEL: @flatten_transfer_ops +// CHECK-NOT: vector.transfer_read {{.*}}, vector<1x8xf32> +// CHECK-NOT: vector.transfer_read {{.*}}, vector<1x8xf32> +// CHECK: vector.transfer_read {{.*}}, vector<8xf32> +// CHECK-NEXT: vector.transfer_read {{.*}}, vector<8xf32> +// CHECK-NOT: vector.shape_cast +// CHECK-NOT: vector.shape_cast + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op + transform.apply_patterns to %func { + transform.apply_patterns.vector.flatten_vector_transfer_ops + } : !transform.any_op + transform.yield + } +} diff --git a/mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir b/mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir index 72dc899f4f0a6..6868b55095461 100644 --- a/mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir +++ b/mlir/test/Dialect/X86Vector/legalize-for-llvm.mlir @@ -95,6 +95,14 @@ func.func @avx512bf16_cvt_packed_f32_to_bf16_512( return %0 : vector<16xbf16> } +// CHECK-LABEL: func @avx10_dot_i8_512 +func.func @avx10_dot_i8_512(%w: vector<16xi32>, %a: vector<64xi8>, + %b: vector<64xi8>) -> vector<16xi32> { + // CHECK: llvm.call_intrinsic "llvm.x86.avx10.vpdpbssd.512" + %0 = x86vector.avx10.dot.i8 %w, %a, %b : vector<64xi8> -> vector<16xi32> + return %0 : vector<16xi32> +} + // CHECK-LABEL: func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_128 func.func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_128( %a: memref<8xbf16>) -> vector<4xf32> diff --git a/mlir/test/Dialect/X86Vector/roundtrip.mlir b/mlir/test/Dialect/X86Vector/roundtrip.mlir index 959177b27c7ea..672c32c9c3cc3 100644 --- a/mlir/test/Dialect/X86Vector/roundtrip.mlir +++ b/mlir/test/Dialect/X86Vector/roundtrip.mlir @@ -94,6 +94,14 @@ func.func @avx512bf16_cvt_packed_f32_to_bf16_512( return %0 : vector<16xbf16> } +// CHECK-LABEL: func @avx10_dot_i8_512 +func.func @avx10_dot_i8_512(%w: vector<16xi32>, %a: vector<64xi8>, + %b: vector<64xi8>) -> vector<16xi32> { + // CHECK: x86vector.avx10.dot.i8 {{.*}} : vector<64xi8> -> vector<16xi32> + %0 = x86vector.avx10.dot.i8 %w, %a, %b : vector<64xi8> -> vector<16xi32> + return %0 : vector<16xi32> +} + // CHECK-LABEL: func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_128 func.func @avxbf16_cvt_packed_even_indexed_bf16_to_f32_128( %a: memref<8xbf16>) -> vector<4xf32> diff --git a/mlir/test/Dialect/X86Vector/vector-contract-to-packed-type-dotproduct.mlir b/mlir/test/Dialect/X86Vector/vector-contract-to-packed-type-dotproduct.mlir index 65676cbae772c..e26a575e2bc90 100644 --- a/mlir/test/Dialect/X86Vector/vector-contract-to-packed-type-dotproduct.mlir +++ b/mlir/test/Dialect/X86Vector/vector-contract-to-packed-type-dotproduct.mlir @@ -68,6 +68,75 @@ module attributes {transform.with_named_sequence} { // ----- +!vecA = vector<1x1x1x4xi8> +!vecB = vector<1x1x16x4xi8> +!vecC = vector<1x16xi32> +#map = affine_map<(d0, d4, d1, d2, d3) -> (d0, d1, d3, d4)> +#map1 = affine_map<(d0, d4, d1, d2, d3) -> (d0, d3, d2, d4)> +#map2 = affine_map<(d0, d4, d1, d2, d3) -> (d1, d2)> +func.func @brgemm_to_avx10int8dp( + %arg0: !vecA, %arg1: !vecB, %arg2: !vecC) -> !vecC +{ + %0 = vector.contract { + indexing_maps = [#map, #map1, #map2], + iterator_types = ["reduction", "reduction", "parallel", "parallel", "reduction"], + kind = #vector.kind} + %arg0, %arg1, %arg2 + : !vecA, !vecB into !vecC + return %0 : !vecC +} + +// CHECK-LABEL: @brgemm_to_avx10int8dp +// CHECK: vector.broadcast +// CHECK: x86vector.avx10.dot.i8 + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op + transform.apply_patterns to %func { + transform.apply_patterns.x86vector.vector_contract_to_packed_type_dot_product + } : !transform.any_op + transform.yield + } +} + +// ----- + +!vecA = vector<1x16x1x4xi8> +!vecB = vector<1x1x1x4xi8> +!vecC = vector<1x16x1xi32> +#map = affine_map<(d0, d4, d1, d2, d3) -> (d0, d1, d3, d4)> +#map1 = affine_map<(d0, d4, d1, d2, d3) -> (d0, d3, d2, d4)> +#map2 = affine_map<(d0, d4, d1, d2, d3) -> (d0, d1, d2)> +func.func @batch_matmul_avx10int8dp_bcst_B( + %arg0: !vecA, %arg1: !vecB, %arg2: !vecC) -> !vecC +{ + %0 = vector.contract { + indexing_maps = [#map, #map1, #map2], + iterator_types = ["parallel", "reduction", "parallel", "parallel", "reduction"], + kind = #vector.kind} + %arg0, %arg1, %arg2 + : !vecA, !vecB into !vecC + return %0 : !vecC +} + + +// CHECK-LABEL: @batch_matmul_avx10int8dp_bcst_B +// CHECK: vector.broadcast +// CHECK: x86vector.avx10.dot.i8 + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %func = transform.structured.match ops{["func.func"]} in %arg1 : (!transform.any_op) -> !transform.any_op + transform.apply_patterns to %func { + transform.apply_patterns.x86vector.vector_contract_to_packed_type_dot_product + } : !transform.any_op + transform.yield + } +} + +// ----- + !vecA = vector<1x1x1x4xi8> !vecB = vector<1x1x8x4xi8> !vecC = vector<1x8xi32> @@ -615,8 +684,8 @@ module attributes {transform.with_named_sequence} { // ----- !vecA = vector<1x1x1x4xi8> -!vecB = vector<1x1x16x4xi8> -!vecC = vector<1x1x16xi32> +!vecB = vector<1x1x32x4xi8> +!vecC = vector<1x1x32xi32> #map = affine_map<(d0, d4, d1, d2, d3) -> (d0, d1, d3, d4)> #map1 = affine_map<(d0, d4, d1, d2, d3) -> (d0, d3, d2, d4)> #map2 = affine_map<(d0, d4, d1, d2, d3) -> (d0, d1, d2)> @@ -634,6 +703,7 @@ func.func @negative_wrong_vector_shape_int8( // CHECK-LABEL: @negative_wrong_vector_shape_int8 // CHECK-NOT: x86vector.avx.dot.i8 +// CHECK-NOT: x86vector.avx10.dot.i8 // CHECK: vector.contract module attributes {transform.with_named_sequence} { diff --git a/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir b/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir index 9de2881d05d0b..b6c172ecf4ae0 100644 --- a/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir +++ b/mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir @@ -217,7 +217,7 @@ gpu.module @test { // CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<1024xf32>) { // CHECK: %{{.*}} = arith.constant {layout_result_0 = #xegpu.layout} dense : vector<16xi1> // CHECK: %{{.*}} = arith.constant {layout_result_0 = #xegpu.layout} dense<12> : vector<16xindex> -// CHECK: %[[LOADED:.*]] = xegpu.load %[[ARG0]][%{{.*}}], %{{.*}} <{layout = #xegpu.slice<#xegpu.layout, dims = [0]>}> : +// CHECK: %[[LOADED:.*]] = xegpu.load %[[ARG0]][%{{.*}}], %{{.*}} <{layout = #xegpu.layout}> : // CHECK-SAME: memref<1024xf32>, vector<16xindex>, vector<16xi1> -> vector<16xf32> // CHECK: %[[BCAST:.*]] = vector.broadcast %[[LOADED]] {layout_result_0 = #xegpu.layout} : vector<16xf32> to vector<16x16xf32> // CHECK: xegpu.store %[[BCAST]], %[[ARG0]][%{{.*}}], %{{.*}} <{chunk_size = 16 : i64, layout = #xegpu.layout}> : @@ -234,3 +234,89 @@ func.func @scatter_ops_chunksize_slice(%src: memref<1024xf32>) { return } } + +// ----- +gpu.module @test { +// CHECK-LABEL: func.func @insert_strided_slice_inst_data_no_packing( +// CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<8x32xf32>) { +// CHECK: %[[CST_SMALL:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<1.000000e+00> : vector<4x16xf32> +// CHECK: %[[CST_LARGE:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<0.000000e+00> : vector<8x32xf32> +// CHECK: %[[INSERT:.*]] = vector.insert_strided_slice %[[CST_SMALL]], %[[CST_LARGE]] {layout_result_0 = #xegpu.layout, offsets = [0, 0], strides = [1, 1]} : vector<4x16xf32> into vector<8x32xf32> +// CHECK: %[[TDESC:.*]] = xegpu.create_nd_tdesc %[[ARG0]][{{.*}}] : memref<8x32xf32> -> !xegpu.tensor_desc<8x32xf32, #xegpu.layout> +// CHECK: xegpu.store_nd %[[INSERT]], %[[TDESC]] <{layout = #xegpu.layout}> : vector<8x32xf32>, !xegpu.tensor_desc<8x32xf32, #xegpu.layout> +func.func @insert_strided_slice_inst_data_no_packing(%arg0: memref<8x32xf32>) { + %c0 = arith.constant 0 : index + %cst_small = arith.constant dense<1.0> : vector<4x16xf32> + %cst_large = arith.constant dense<0.0> : vector<8x32xf32> + %insert = vector.insert_strided_slice %cst_small, %cst_large {offsets = [0, 0], strides = [1, 1]} : vector<4x16xf32> into vector<8x32xf32> + %tdesc = xegpu.create_nd_tdesc %arg0[%c0, %c0] : memref<8x32xf32> -> !xegpu.tensor_desc<8x32xf32> + xegpu.store_nd %insert, %tdesc : vector<8x32xf32>, !xegpu.tensor_desc<8x32xf32> + return +} +} + +// ----- +gpu.module @test { +// CHECK-LABEL: func.func @insert_strided_slice_inst_data_with_packing( +// CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<8x64xi8>) { +// CHECK: %[[CST_SMALL:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<1> : vector<4x64xi8> +// CHECK: %[[CST_LARGE:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<0> : vector<8x64xi8> +// CHECK: %[[INSERT:.*]] = vector.insert_strided_slice %[[CST_SMALL]], %[[CST_LARGE]] {layout_result_0 = #xegpu.layout, offsets = [0, 0], strides = [1, 1]} : vector<4x64xi8> into vector<8x64xi8> +func.func @insert_strided_slice_inst_data_with_packing(%arg0: memref<8x64xi8>) { + %c0 = arith.constant 0 : index + %cst_small = arith.constant dense<1> : vector<4x64xi8> + %cst_large = arith.constant dense<0> : vector<8x64xi8> + %insert = vector.insert_strided_slice %cst_small, %cst_large {offsets = [0, 0], strides = [1, 1]} : vector<4x64xi8> into vector<8x64xi8> + %tdesc = xegpu.create_nd_tdesc %arg0[%c0, %c0] : memref<8x64xi8> -> !xegpu.tensor_desc<8x64xi8, #xegpu.layout> + xegpu.store_nd %insert, %tdesc <{layout = #xegpu.layout}>: vector<8x64xi8>, !xegpu.tensor_desc<8x64xi8, #xegpu.layout> + return +} +} + +// ----- +gpu.module @test { +// CHECK-LABEL: func.func @vector_shape_cast_expand_non_unit_dims( +// CHECK: %[[LOAD:.*]] = xegpu.load %arg0[%[[STEP:.*]]], %[[CST:.*]] <{layout = #xegpu.layout}> : memref<1024xf16>, vector<1024xindex>, vector<1024xi1> -> vector<1024xf16> +// CHECK: %[[CAST:.*]] = vector.shape_cast %[[LOAD]] {layout_result_0 = #xegpu.layout} : vector<1024xf16> to vector<8x8x16xf16> +// CHECK: %[[CST_0:.*]] = arith.constant {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} dense<0.000000e+00> : vector<8x16xf16> +// CHECK: %[[CST_1:.*]] = arith.constant {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} dense<0.000000e+00> : vector<16xf16> +// CHECK: %[[REDUCE_0:.*]] = vector.multi_reduction , %[[CAST]], %[[CST_0]] {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} [0] : vector<8x8x16xf16> to vector<8x16xf16> +// CHECK: %[[REDUCE_1:.*]] = vector.multi_reduction , %[[REDUCE_0]], %[[CST_1]] {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} [0] : vector<8x16xf16> to vector<16xf16> +func.func @vector_shape_cast_expand_non_unit_dims(%arg0: memref<1024xf16>, %arg1: memref<16xf16>) { + %cst = arith.constant dense : vector<1024xi1> + %0 = vector.step : vector<1024xindex> + %1 = xegpu.load %arg0[%0], %cst : memref<1024xf16>, vector<1024xindex>, vector<1024xi1> -> vector<1024xf16> + %2 = vector.shape_cast %1 : vector<1024xf16> to vector<8x8x16xf16> + %cst_0 = arith.constant dense<0.000000e+00> : vector<8x16xf16> + %cst_1 = arith.constant dense<0.000000e+00> : vector<16xf16> + %3 = vector.multi_reduction , %2, %cst_0 [0] : vector<8x8x16xf16> to vector<8x16xf16> + %4 = vector.multi_reduction , %3, %cst_1 [0] : vector<8x16xf16> to vector<16xf16> + %cst_2 = arith.constant dense : vector<16xi1> + %cst_3 = arith.constant dense<1> : vector<16xindex> + xegpu.store %4, %arg1[%cst_3], %cst_2 <{layout = #xegpu.layout}> : vector<16xf16>, memref<16xf16>, vector<16xindex>, vector<16xi1> + return + } +} + +// ----- +gpu.module @test { +// CHECK-LABEL: func.func @vector_shape_cast_expand_and_merge( +// CHECK: %[[CST:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense : vector<256xi1> +// CHECK: %[[STEP:.*]] = vector.step {layout_result_0 = #xegpu.layout} : vector<256xindex> +// CHECK: %[[LOAD:.*]] = xegpu.load %arg0[%[[STEP]]], %[[CST]] <{layout = #xegpu.layout}> : memref<256xf16>, vector<256xindex>, vector<256xi1> -> vector<256xf16> +// CHECK: %[[CAST_0:.*]] = vector.shape_cast %[[LOAD]] {layout_result_0 = #xegpu.layout} : vector<256xf16> to vector<2x4x32xf16> +// CHECK: %[[CAST_1:.*]] = vector.shape_cast %[[CAST_0]] {layout_result_0 = #xegpu.layout} : vector<2x4x32xf16> to vector<1x256xf16> +// CHECK: %[[CAST_2:.*]] = vector.shape_cast %[[CAST_1]] {layout_result_0 = #xegpu.layout} : vector<1x256xf16> to vector<256xf16> +// CHECK: xegpu.store %[[CAST_2]], %arg1[%[[STEP]]], %[[CST]] <{layout = #xegpu.layout}> : vector<256xf16>, memref<256xf16>, vector<256xindex>, vector<256xi1> +func.func @vector_shape_cast_expand_and_merge(%arg0: memref<256xf16>, %arg1: memref<256xf16>) { + %cst = arith.constant dense : vector<256xi1> + %0 = vector.step : vector<256xindex> + %1 = xegpu.load %arg0[%0], %cst : memref<256xf16>, vector<256xindex>, vector<256xi1> -> vector<256xf16> + %2 = vector.shape_cast %1 : vector<256xf16> to vector<2x4x32xf16> + + %4 = vector.shape_cast %2 : vector<2x4x32xf16> to vector<1x256xf16> + %5 = vector.shape_cast %4 : vector<1x256xf16> to vector<256xf16> + xegpu.store %5, %arg1[%0], %cst <{layout = #xegpu.layout}> : vector<256xf16>, memref<256xf16>, vector<256xindex>, vector<256xi1> + return + } +} diff --git a/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir b/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir index 29e5b51627fb6..190b54912488f 100644 --- a/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir +++ b/mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir @@ -123,3 +123,44 @@ gpu.module @test { gpu.return } } + +// ----- +gpu.module @test { +// CHECK-LABEL: vector_row_reduction +// CHECK: %[[REDUCE:.*]] = vector.multi_reduction , %{{.*}}, %{{.*}} {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [1]>} + gpu.func @vector_row_reduction(%src: memref<32x64xf32>, %dst: memref<32xf32>) kernel attributes + {known_block_size = array} { + %cst = arith.constant dense<0.000000e+00> : vector<32xf32> + %tdesc_src = xegpu.create_nd_tdesc %src : memref<32x64xf32> -> !xegpu.tensor_desc<32x64xf32> + %load = xegpu.load_nd %tdesc_src : !xegpu.tensor_desc<32x64xf32> -> vector<32x64xf32> + %reduce = vector.multi_reduction , %load, %cst [1] : vector<32x64xf32> to vector<32xf32> + %tdesc_dst = xegpu.create_nd_tdesc %dst : memref<32xf32> -> !xegpu.tensor_desc<32xf32, #xegpu.layout> + xegpu.store_nd %reduce, %tdesc_dst <{layout = #xegpu.layout}> + : vector<32xf32>, !xegpu.tensor_desc<32xf32, #xegpu.layout> + gpu.return + } +} + +// ----- +gpu.module @test { +// CHECK-LABEL: vector_nest_reduction + gpu.func @vector_nest_reduction(%src: memref<32x128xf32>, %dst: memref<32xf32>) kernel attributes + {known_block_size = array} { + %cst = arith.constant dense<0.000000e+00> : vector<32xf32> + %cst1 = arith.constant dense<0.000000e+00> : vector<32x128xf32> + %tdesc_src = xegpu.create_nd_tdesc %src : memref<32x128xf32> -> !xegpu.tensor_desc<32x128xf32> + %load = xegpu.load_nd %tdesc_src : !xegpu.tensor_desc<32x128xf32> -> vector<32x128xf32> + %bcast1 = vector.broadcast %load: vector<32x128xf32> to vector<4x32x128xf32> + + // CHECK: %[[BCAST1:.*]] = vector.broadcast %{{.*}} {layout_result_0 = #xegpu.layout} : vector<32x128xf32> to vector<4x32x128xf32> + // CHECK: %[[BCAST:.*]] = vector.multi_reduction , %[[BCAST1]], %{{.*}} {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} [0] : vector<4x32x128xf32> to vector<32x128xf32> + // CHECK: %[[REDUCE:.*]] = vector.multi_reduction , %[[BCAST]], %{{.*}} {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [1]>} [1] : vector<32x128xf32> to vector<32xf32> + + %bcast = vector.multi_reduction , %bcast1, %cst1 [0]: vector<4x32x128xf32> to vector<32x128xf32> + %reduce = vector.multi_reduction , %bcast, %cst [1] : vector<32x128xf32> to vector<32xf32> + %mask = arith.constant dense<1>: vector<32xi1> + %offset = vector.step : vector<32xindex> + xegpu.store %reduce, %dst[%offset], %mask {layout = #xegpu.slice<#xegpu.layout, dims = [1]>} : vector<32xf32>, memref<32xf32>, vector<32xindex>, vector<32xi1> + gpu.return + } +} \ No newline at end of file diff --git a/mlir/test/Dialect/XeGPU/propagate-layout.mlir b/mlir/test/Dialect/XeGPU/propagate-layout.mlir index f4859fe324b19..17c9ec131ed70 100644 --- a/mlir/test/Dialect/XeGPU/propagate-layout.mlir +++ b/mlir/test/Dialect/XeGPU/propagate-layout.mlir @@ -104,21 +104,18 @@ func.func @extf_truncf(%arg0: !xegpu.tensor_desc<8x16xf16>, %arg1: !xegpu.tensor gpu.module @test { // CHECK-LABEL: func.func @load_gather_with_chunksize( // CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<8x16xf16>, %[[ARG1:[0-9a-zA-Z]+]]: memref<256xf16>, %[[ARG2:[0-9a-zA-Z]+]]: memref<8x16xf32>) { -// CHECK: %[[CST:.*]] = arith.constant {layout_result_0 = #xegpu.layout} +// CHECK: %[[OFFSET:.*]] = arith.constant {layout_result_0 = #xegpu.layout} // CHECK-SAME: dense<[0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240]> : vector<16xindex> -// CHECK-NEXT: %[[CST0:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense : vector<16xi1> -// CHECK-NEXT: %[[T2:.*]] = xegpu.create_tdesc %[[ARG1]], %[[CST]] : memref<256xf16>, vector<16xindex> -> -// CHECK-SAME: !xegpu.tensor_desc<16x16xf16, #xegpu.scatter_tdesc_attr, #xegpu.layout> -// CHECK-NEXT: %{{.*}} = xegpu.load %[[T2]], %[[CST0]] <{layout = #xegpu.layout}> -// CHECK-SAME: !xegpu.tensor_desc<16x16xf16, #xegpu.scatter_tdesc_attr, #xegpu.layout>, vector<16xi1> -> vector<16x16xf16> +// CHECK-NEXT: %[[MASK:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense : vector<16xi1> +// CHECK-NEXT: %{{.*}} = xegpu.load %arg1[%[[OFFSET]]], %[[MASK]] <{chunk_size = 16 : i64, layout = #xegpu.layout}> : memref<256xf16>, vector<16xindex>, vector<16xi1> -> vector<16x16xf16> func.func @load_gather_with_chunksize(%arg0: memref<8x16xf16>, %arg1: memref<256xf16>, %arg2: memref<8x16xf32>) { %c0 = arith.constant 0 : index %0 = xegpu.create_nd_tdesc %arg0[%c0, %c0] : memref<8x16xf16> -> !xegpu.tensor_desc<8x16xf16> %1 = xegpu.load_nd %0 : !xegpu.tensor_desc<8x16xf16> -> vector<8x16xf16> - %cst = arith.constant dense<[0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240]> : vector<16xindex> - %cst_0 = arith.constant dense : vector<16xi1> - %2 = xegpu.create_tdesc %arg1, %cst : memref<256xf16>, vector<16xindex> -> !xegpu.tensor_desc<16x16xf16, #xegpu.scatter_tdesc_attr> - %3 = xegpu.load %2, %cst_0 : !xegpu.tensor_desc<16x16xf16, #xegpu.scatter_tdesc_attr>, vector<16xi1> -> vector<16x16xf16> + %offset = arith.constant dense<[0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240]> : vector<16xindex> + %mask = arith.constant dense : vector<16xi1> + %3 = xegpu.load %arg1[%offset], %mask <{chunk_size=16}> + : memref<256xf16>, vector<16xindex>, vector<16xi1> -> vector<16x16xf16> %4 = vector.transpose %3, [1, 0] : vector<16x16xf16> to vector<16x16xf16> %5 = xegpu.dpas %1, %4 : vector<8x16xf16>, vector<16x16xf16> -> vector<8x16xf32> %6 = xegpu.create_nd_tdesc %arg2[%c0, %c0] : memref<8x16xf32> -> !xegpu.tensor_desc<8x16xf32> @@ -151,16 +148,15 @@ func.func @load_gather_1d(%arg0: memref<256xf32>, %arg1: !xegpu.tensor_desc<16xf gpu.module @test { // CHECK-LABEL: func.func @store_scatter_with_chunksize( // CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<128xf32>) { -// CHECK: %[[T0:.*]] = xegpu.create_tdesc %[[ARG0]], %{{.*}} : memref<128xf32>, vector<16xindex> -> -// CHECK-SAME: !xegpu.tensor_desc<16x8xf32, #xegpu.scatter_tdesc_attr, #xegpu.layout> -// CHECK-NEXT: xegpu.store %{{.*}}, %[[T0]], %{{.*}} : vector<16x8xf32>, !xegpu.tensor_desc<16x8xf32, #xegpu.scatter_tdesc_attr, -// CHECK-SAME: #xegpu.layout>, vector<16xi1> +// CHECK-NEXT: %[[CST:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<1.000000e+00> : vector<16x8xf32> +// CHECK-NEXT: %[[CST_0:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense : vector<16xi1> +// CHECK-NEXT: %[[CST_1:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<[0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240]> : vector<16xindex> +// CHECK-NEXT: xegpu.store %[[CST]], %[[ARG0]][%[[CST_1]]], %[[CST_0]] <{chunk_size = 8 : i64, layout = #xegpu.layout}> : vector<16x8xf32>, memref<128xf32>, vector<16xindex>, vector<16xi1> func.func @store_scatter_with_chunksize(%arg0: memref<128xf32>) { - %cst = arith.constant dense<1.000000e+00> : vector<16x8xf32> - %cst_0 = arith.constant dense : vector<16xi1> - %cst_1 = arith.constant dense<[0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240]> : vector<16xindex> - %0 = xegpu.create_tdesc %arg0, %cst_1 : memref<128xf32>, vector<16xindex> -> !xegpu.tensor_desc<16x8xf32, #xegpu.scatter_tdesc_attr> - xegpu.store %cst, %0, %cst_0 : vector<16x8xf32>, !xegpu.tensor_desc<16x8xf32, #xegpu.scatter_tdesc_attr>, vector<16xi1> + %val = arith.constant dense<1.000000e+00> : vector<16x8xf32> + %mask = arith.constant dense : vector<16xi1> + %offset = arith.constant dense<[0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240]> : vector<16xindex> + xegpu.store %val, %arg0[%offset], %mask <{chunk_size = 8}>: vector<16x8xf32>, memref<128xf32>, vector<16xindex>, vector<16xi1> return } } @@ -184,9 +180,9 @@ gpu.module @test { // CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<256xf16>) { // CHECK: %[[MASK:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense : vector<16xi1> // CHECK: %[[OFFSETS:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<12> : vector<16xindex> -// CHECK: %[[LOAD_VEC:.*]] = xegpu.load %[[ARG0]][%[[OFFSETS]]], %[[MASK]] <{chunk_size = 8 : i64, layout = #xegpu.layout}> +// CHECK: %[[LOAD_VEC:.*]] = xegpu.load %[[ARG0]][%[[OFFSETS]]], %[[MASK]] <{chunk_size = 8 : i64, layout = #xegpu.layout}> // CHECK-SAME: memref<256xf16>, vector<16xindex>, vector<16xi1> -> vector<16x8xf16> -// CHECK: xegpu.store %[[LOAD_VEC]], %[[ARG0]][%[[OFFSETS]]], %[[MASK]] <{chunk_size = 8 : i64, layout = #xegpu.layout}> : vector<16x8xf16>, memref<256xf16>, vector<16xindex>, vector<16xi1> +// CHECK: xegpu.store %[[LOAD_VEC]], %[[ARG0]][%[[OFFSETS]]], %[[MASK]] <{chunk_size = 8 : i64, layout = #xegpu.layout}> : vector<16x8xf16>, memref<256xf16>, vector<16xindex>, vector<16xi1> func.func @scatter_ops_chunksize(%src: memref<256xf16>) { %1 = arith.constant dense<1>: vector<16xi1> %offset = arith.constant dense<12> : vector<16xindex> @@ -320,8 +316,9 @@ func.func @vector_bitcast_i16_to_i32(%arg0: memref<8x32xi16>, %arg1: memref<8x16 // ----- gpu.module @test { // CHECK-LABEL: func.func @vector_bitcast_require_cross_lane_shuffle( -// CHECK: %[[LOAD:.*]] = xegpu.load_nd %{{.*}} : !xegpu.tensor_desc<8x16xi32> -> vector<8x16xi32> -// CHECK: %{{.*}} = vector.bitcast %[[LOAD]] {layout_result_0 = #xegpu.layout} +// CHECK: %[[LOAD:.*]] = xegpu.load_nd %{{.*}} <{layout = #xegpu.layout}> +// CHECK-SAME: !xegpu.tensor_desc<8x16xi32, #xegpu.layout> +// CHECK: %{{.*}} = vector.bitcast %[[LOAD]] {layout_result_0 = #xegpu.layout} // CHECK-SAME: vector<8x16xi32> to vector<8x32xi16> func.func @vector_bitcast_require_cross_lane_shuffle(%arg0: memref<8x16xi32>, %arg1: memref<8x32xi16>) { %c0 = arith.constant 0 : index @@ -483,7 +480,7 @@ func.func @if_multiple_uses(%arg0: !xegpu.tensor_desc<8x16xf16>, %arg1: !xegpu.t gpu.module @test { // CHECK-LABEL: func.func @vector_outer_reduction( // CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: vector<16x16xf32>, %[[ARG1:[0-9a-zA-Z]+]]: !xegpu.tensor_desc<16xf32, #xegpu.layout>) { -// CHECK: %{{.*}} = vector.multi_reduction , %[[ARG0]], %{{.*}} {layout_result_0 = #xegpu.layout} [0] : vector<16x16xf32> to vector<16xf32> +// CHECK: %{{.*}} = vector.multi_reduction , %[[ARG0]], %{{.*}} {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} [0] : vector<16x16xf32> to vector<16xf32> func.func @vector_outer_reduction(%arg0: vector<16x16xf32>, %arg1: !xegpu.tensor_desc<16xf32>) { %cst = arith.constant dense<0.000000e+00> : vector<16xf32> %0 = vector.multi_reduction , %arg0, %cst [0] : vector<16x16xf32> to vector<16xf32> @@ -495,7 +492,7 @@ func.func @vector_outer_reduction(%arg0: vector<16x16xf32>, %arg1: !xegpu.tensor gpu.module @test { // CHECK-LABEL: func.func @vector_inner_reduction( // CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: vector<16x16xf32>, %[[ARG1:[0-9a-zA-Z]+]]: !xegpu.tensor_desc<16xf32, #xegpu.layout>) { -// CHECK: %{{.*}} = vector.multi_reduction , %[[ARG0]], %{{.*}} {layout_result_0 = #xegpu.layout} [1] : vector<16x16xf32> to vector<16xf32> +// CHECK: %{{.*}} = vector.multi_reduction , %[[ARG0]], %{{.*}} {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [1]>} [1] : vector<16x16xf32> to vector<16xf32> func.func @vector_inner_reduction(%arg0: vector<16x16xf32>, %arg1: !xegpu.tensor_desc<16xf32>) { %cst = arith.constant dense<0.000000e+00> : vector<16xf32> %0 = vector.multi_reduction , %arg0, %cst [1] : vector<16x16xf32> to vector<16xf32> @@ -642,6 +639,52 @@ func.func @vector_shape_cast_1d_to_2d_dim0_broadcasted(%arg0: !xegpu.tensor_desc } // ----- gpu.module @test { +// CHECK-LABEL: func.func @vector_shape_cast_expand_non_unit_dims( +// CHECK: %[[LOAD:.*]] = xegpu.load %arg0[%[[STEP:.*]]], %[[CST:.*]] <{layout = #xegpu.layout}> : memref<1024xf16>, vector<1024xindex>, vector<1024xi1> -> vector<1024xf16> +// CHECK: %[[CAST:.*]] = vector.shape_cast %[[LOAD]] {layout_result_0 = #xegpu.layout} : vector<1024xf16> to vector<8x8x16xf16> +// CHECK: %[[CST_0:.*]] = arith.constant {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} dense<0.000000e+00> : vector<8x16xf16> +// CHECK: %[[CST_1:.*]] = arith.constant {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} dense<0.000000e+00> : vector<16xf16> +// CHECK: %[[REDUCE_0:.*]] = vector.multi_reduction , %[[CAST]], %[[CST_0]] {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} [0] : vector<8x8x16xf16> to vector<8x16xf16> +// CHECK: %[[REDUCE_1:.*]] = vector.multi_reduction , %[[REDUCE_0]], %[[CST_1]] {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} [0] : vector<8x16xf16> to vector<16xf16> +func.func @vector_shape_cast_expand_non_unit_dims(%arg0: memref<1024xf16>, %arg1: memref<16xf16>) { + %cst = arith.constant dense : vector<1024xi1> + %0 = vector.step : vector<1024xindex> + %1 = xegpu.load %arg0[%0], %cst : memref<1024xf16>, vector<1024xindex>, vector<1024xi1> -> vector<1024xf16> + %2 = vector.shape_cast %1 : vector<1024xf16> to vector<8x8x16xf16> + %cst_0 = arith.constant dense<0.000000e+00> : vector<8x16xf16> + %cst_1 = arith.constant dense<0.000000e+00> : vector<16xf16> + %3 = vector.multi_reduction , %2, %cst_0 [0] : vector<8x8x16xf16> to vector<8x16xf16> + %4 = vector.multi_reduction , %3, %cst_1 [0] : vector<8x16xf16> to vector<16xf16> + %cst_2 = arith.constant dense : vector<16xi1> + %cst_3 = arith.constant dense<1> : vector<16xindex> + xegpu.store %4, %arg1[%cst_3], %cst_2 <{layout = #xegpu.layout}> : vector<16xf16>, memref<16xf16>, vector<16xindex>, vector<16xi1> + return + } +} +// ----- +gpu.module @test { +// CHECK-LABEL: func.func @vector_shape_cast_expand_and_merge( +// CHECK: %[[CST:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense : vector<256xi1> +// CHECK: %[[STEP:.*]] = vector.step {layout_result_0 = #xegpu.layout} : vector<256xindex> +// CHECK: %[[LOAD:.*]] = xegpu.load %arg0[%[[STEP]]], %[[CST]] <{layout = #xegpu.layout}> : memref<256xf16>, vector<256xindex>, vector<256xi1> -> vector<256xf16> +// CHECK: %[[CAST_0:.*]] = vector.shape_cast %[[LOAD]] {layout_result_0 = #xegpu.layout} : vector<256xf16> to vector<2x4x32xf16> +// CHECK: %[[CAST_1:.*]] = vector.shape_cast %[[CAST_0]] {layout_result_0 = #xegpu.layout} : vector<2x4x32xf16> to vector<1x256xf16> +// CHECK: %[[CAST_2:.*]] = vector.shape_cast %[[CAST_1]] {layout_result_0 = #xegpu.layout} : vector<1x256xf16> to vector<256xf16> +// CHECK: xegpu.store %[[CAST_2]], %arg1[%[[STEP]]], %[[CST]] <{layout = #xegpu.layout}> : vector<256xf16>, memref<256xf16>, vector<256xindex>, vector<256xi1> +func.func @vector_shape_cast_expand_and_merge(%arg0: memref<256xf16>, %arg1: memref<256xf16>) { + %cst = arith.constant dense : vector<256xi1> + %0 = vector.step : vector<256xindex> + %1 = xegpu.load %arg0[%0], %cst : memref<256xf16>, vector<256xindex>, vector<256xi1> -> vector<256xf16> + %2 = vector.shape_cast %1 : vector<256xf16> to vector<2x4x32xf16> + + %4 = vector.shape_cast %2 : vector<2x4x32xf16> to vector<1x256xf16> + %5 = vector.shape_cast %4 : vector<1x256xf16> to vector<256xf16> + xegpu.store %5, %arg1[%0], %cst <{layout = #xegpu.layout}> : vector<256xf16>, memref<256xf16>, vector<256xindex>, vector<256xi1> + return + } +} +// ----- +gpu.module @test { // CHECK-LABEL: func.func @vector_broadcast_1d_to_2d_broadcast_along_row( // CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: !xegpu.tensor_desc<16x16xf16, #xegpu.layout>, // CHECK-SAME: %[[ARG1:[0-9a-zA-Z]+]]: !xegpu.tensor_desc<16x16xf16, #xegpu.layout>) { @@ -702,12 +745,50 @@ func.func @vector_broadcast_scalar_to_vector(%arg0: !xegpu.tensor_desc<16x16xf16 // ----- gpu.module @test { // CHECK-LABEL: func.func @store_matrix( -// CHECK: %[[CST:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<0.000000e+00> : vector<16x16xf16> -// CHECK-NEXT: xegpu.store_matrix %[[CST]], %arg0[8, 8] : vector<16x16xf16>, !xegpu.mem_desc<16x64xf16> - +// CHECK: %[[CST:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<0.000000e+00> : vector<16x16xf16> +// CHECK-NEXT: xegpu.store_matrix %[[CST]], %arg0[8, 8] <{layout = #xegpu.layout}> func.func @store_matrix(%arg0: !xegpu.mem_desc<16x64xf16>) { %cst = arith.constant dense<0.0000> : vector<16x16xf16> xegpu.store_matrix %cst, %arg0[8, 8]: vector<16x16xf16>, !xegpu.mem_desc<16x64xf16> return } } + +// ----- +gpu.module @test { +// CHECK-LABEL: func.func @insert_strided_slice_lane_layout_no_packing( +// CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<4x64xf32>) { +// CHECK: %[[CST_SMALL:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<1.000000e+00> : vector<2x32xf32> +// CHECK: %[[CST_LARGE:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<0.000000e+00> : vector<4x64xf32> +// CHECK: %[[INSERT:.*]] = vector.insert_strided_slice %[[CST_SMALL]], %[[CST_LARGE]] {layout_result_0 = #xegpu.layout, offsets = [0, 0], strides = [1, 1]} : vector<2x32xf32> into vector<4x64xf32> +// CHECK: %[[TDESC:.*]] = xegpu.create_nd_tdesc %[[ARG0]][{{.*}}] : memref<4x64xf32> -> !xegpu.tensor_desc<4x64xf32, #xegpu.layout> +// CHECK: xegpu.store_nd %[[INSERT]], %[[TDESC]] <{layout = #xegpu.layout}> : vector<4x64xf32>, !xegpu.tensor_desc<4x64xf32, #xegpu.layout> +func.func @insert_strided_slice_lane_layout_no_packing(%arg0: memref<4x64xf32>) { + %c0 = arith.constant 0 : index + %cst_small = arith.constant dense<1.0> : vector<2x32xf32> + %cst_large = arith.constant dense<0.0> : vector<4x64xf32> + %insert = vector.insert_strided_slice %cst_small, %cst_large {offsets = [0, 0], strides = [1, 1]} : vector<2x32xf32> into vector<4x64xf32> + %tdesc = xegpu.create_nd_tdesc %arg0[%c0, %c0] : memref<4x64xf32> -> !xegpu.tensor_desc<4x64xf32> + xegpu.store_nd %insert, %tdesc : vector<4x64xf32>, !xegpu.tensor_desc<4x64xf32> + return +} +} + +// ----- +gpu.module @test { +// CHECK-LABEL: func.func @insert_strided_slice_lane_layout_with_packing( +// CHECK-SAME: %[[ARG0:[0-9a-zA-Z]+]]: memref<4x64xf16>) { +// CHECK: %[[CST_SMALL:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<1.000000e+00> : vector<2x32xf16> +// CHECK: %[[CST_LARGE:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<0.000000e+00> : vector<4x64xf16> +// CHECK: %[[INSERT:.*]] = vector.insert_strided_slice %[[CST_SMALL]], %[[CST_LARGE]] {layout_result_0 = #xegpu.layout, offsets = [0, 0], strides = [1, 1]} : vector<2x32xf16> into vector<4x64xf16> +func.func @insert_strided_slice_lane_layout_with_packing(%arg0: memref<4x64xf16>) { + %c0 = arith.constant 0 : index + %cst_small = arith.constant dense<1.0> : vector<2x32xf16> + %cst_large = arith.constant dense<0.0> : vector<4x64xf16> + %insert = vector.insert_strided_slice %cst_small, %cst_large {offsets = [0, 0], strides = [1, 1]} : vector<2x32xf16> into vector<4x64xf16> + %tdesc = xegpu.create_nd_tdesc %arg0[%c0, %c0] : memref<4x64xf16> -> !xegpu.tensor_desc<4x64xf16, #xegpu.layout> + xegpu.store_nd %insert, %tdesc <{layout = #xegpu.layout}>: vector<4x64xf16>, !xegpu.tensor_desc<4x64xf16, #xegpu.layout> + return +} +} + diff --git a/mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir b/mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir index a99f850de6175..81f25cc85359f 100644 --- a/mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir +++ b/mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir @@ -486,7 +486,36 @@ gpu.func @memref_extract_aligned_pointer_as_index(%arg0 : memref<256x256xf16>, % gpu.return } +// CHECK-LABEL: gpu.func @memref_alloca( +// CHECK-NEXT: %[[ALLOCA:.*]] = memref.alloca() : memref<2048xi8, 3> +// CHECK-NEXT: %[[INTPTR:.*]] = memref.extract_aligned_pointer_as_index %[[ALLOCA]] : memref<2048xi8, 3> -> index +// CHECK-NEXT: %[[CAST:.*]] = arith.index_cast %[[INTPTR]] : index to i64 +gpu.func @memref_alloca(%laneid: index) { + %r = gpu.warp_execute_on_lane_0(%laneid)[16] -> (memref<2048xi8, 3>) { + %alloca = memref.alloca() : memref<2048xi8, 3> + gpu.yield %alloca : memref<2048xi8, 3> + } + %ptr = memref.extract_aligned_pointer_as_index %r : memref<2048xi8, 3> -> index + %ptr_i64 = arith.index_cast %ptr : index to i64 + "some_user_op"(%ptr_i64) : (i64) -> () + gpu.return +} +// CHECK-LABEL: gpu.func @create_memdesc( +// CHECK: %[[W:.*]]:2 = gpu.warp_execute_on_lane_0(%{{.*}})[16] -> (!xegpu.mem_desc<4x128xf32>, memref<2048xi8, 3>) { +// CHECK: gpu.yield %{{.*}}, %{{.*}} : !xegpu.mem_desc<4x128xf32>, memref<2048xi8, 3> +// CHECK-NEXT: } +// CHECK-NEXT: %[[MDesc:.*]] = xegpu.create_mem_desc %[[W]]#1 : memref<2048xi8, 3> -> !xegpu.mem_desc<4x128xf32> +gpu.func @create_memdesc(%laneid: index, %arg0 : memref<2048xi8, 3>) { + %c0 = arith.constant 0 : index + %r = gpu.warp_execute_on_lane_0(%laneid)[16] -> (!xegpu.mem_desc<4x128xf32>) { + %mdesc = xegpu.create_mem_desc %arg0 : memref<2048xi8, 3> -> !xegpu.mem_desc<4x128xf32> + gpu.yield %mdesc : !xegpu.mem_desc<4x128xf32> + } + %25 = xegpu.load_matrix %r[%c0, %c0]: !xegpu.mem_desc<4x128xf32>, index, index -> vector<1x16xf32> + "some_user_op"(%25) : (vector<1x16xf32>) -> () + gpu.return +} // CHECK-LABEL: gpu.func @vector_transpose( // CHECK: %[[W:.*]]:2 = gpu.warp_execute_on_lane_0(%{{.*}})[16] -> (vector<2x1xf32>, vector<1x2xf32>) { @@ -582,16 +611,15 @@ gpu.func @vector_shapecast_rank_reducing(%laneid: index) { } -// NOTE: Layouts are still valid, but distribution still requires a slice layout for the operand. -// -// CHECK-LABEL: gpu.func @vector_shapecast_unsupported -// CHECK: %[[W:.*]] = gpu.warp_execute_on_lane_0(%{{.*}})[16] -> (vector<1x1xf32>) { -// CHECK: %[[T1:.*]] = vector.shape_cast %{{.*}} : vector<16xf32> to vector<1x16xf32> -// CHECK: gpu.yield %[[T1]] : vector<1x16xf32> +// CHECK-LABEL: gpu.func @vector_shapecast_rank_increasing_without_slicing_layout +// CHECK: %[[W:.*]]:2 = gpu.warp_execute_on_lane_0(%{{.*}})[16] -> (vector<1x1xf32>, vector<1xf32>) { +// CHECK: %[[T1:.*]] = vector.shape_cast %{{.*}} {layout_operand_0 = #xegpu.layout, layout_result_0 = #xegpu.layout} : vector<16xf32> to vector<1x16xf32> +// CHECK: gpu.yield %[[T1]], %{{.*}} : vector<1x16xf32>, vector<16xf32> // CHECK: } -// CHECK: "some_user_op"(%[[W]]) : (vector<1x1xf32>) -> () +// CHECK: %{{.*}} = vector.shape_cast %[[W]]#1 : vector<1xf32> to vector<1x1xf32> // CHECK: gpu.return -gpu.func @vector_shapecast_unsupported(%laneid: index) { +gpu.module @xevm_module{ +gpu.func @vector_shapecast_rank_increasing_without_slicing_layout(%laneid: index) { %r = gpu.warp_execute_on_lane_0(%laneid)[16] -> (vector<1x1xf32>) { %cst = "some_op"() {layout_result_0 = #xegpu.layout } @@ -607,6 +635,7 @@ gpu.func @vector_shapecast_unsupported(%laneid: index) { "some_user_op"(%r) : (vector<1x1xf32>) -> () gpu.return } +} // CHECK-LABEL: gpu.func @vector_extract_strided_slice_distributed_dim_fully_extracted diff --git a/mlir/test/Dialect/XeGPU/xegpu-blocking.mlir b/mlir/test/Dialect/XeGPU/xegpu-blocking.mlir index 0b6e30e6f95f0..68f6e8e1ec955 100644 --- a/mlir/test/Dialect/XeGPU/xegpu-blocking.mlir +++ b/mlir/test/Dialect/XeGPU/xegpu-blocking.mlir @@ -34,7 +34,9 @@ gpu.module @test_kernel { %b_next_tdesc = xegpu.update_nd_offset %arg1, [%c32, %c0] : !xegpu.tensor_desc<32x32xf16, #b> scf.yield %a_next_tdesc, %b_next_tdesc, %c : !xegpu.tensor_desc<16x32xf16, #a>, !xegpu.tensor_desc<32x32xf16, #b>, vector<16x32xf32> - } + } {layout_result_0 = #a, + layout_result_1 = #b, + layout_result_2 = #c} //CHECK-COUNT-4: xegpu.store_nd {{.*}} : vector<8x16xf32>, !xegpu.tensor_desc<8x16xf32, #xegpu.layout> xegpu.store_nd %out#2, %c_tdesc {layout = #c}: vector<16x32xf32>, !xegpu.tensor_desc<16x32xf32, #c> gpu.return @@ -75,7 +77,9 @@ gpu.module @test_kernel { %b_next_tdesc = xegpu.update_nd_offset %arg1, [%c32, %c0] : !xegpu.tensor_desc<32x32xf16, #l2> scf.yield %a_next_tdesc, %b_next_tdesc, %c : !xegpu.tensor_desc<16x32xf16, #l1>, !xegpu.tensor_desc<32x32xf16, #l2>, vector<16x32xf32> - } + } {layout_result_0 = #l1, + layout_result_1 = #l2, + layout_result_2 = #l1} //CHECK-COUNT-4: xegpu.store_nd {{.*}} : vector<8x16xf32>, !xegpu.tensor_desc<8x16xf32> xegpu.store_nd %out#2, %c_tdesc {layout = #l1}: vector<16x32xf32>, !xegpu.tensor_desc<16x32xf32, #l1> gpu.return @@ -118,7 +122,9 @@ gpu.module @test_kernel { %b_next_tdesc = xegpu.update_nd_offset %arg1, [%c32, %c0] : !xegpu.tensor_desc<16x32xf16, #l2> scf.yield %a_next_tdesc, %b_next_tdesc, %c : !xegpu.tensor_desc<8x16xf16, #l1>, !xegpu.tensor_desc<16x32xf16, #l2>, vector<8x32xf32> - } + } {layout_result_0 = #l1, + layout_result_1 = #l2, + layout_result_2 = #l1} //CHECK-COUNT-2: xegpu.store_nd {{.*}} : vector<8x16xf32>, !xegpu.tensor_desc<8x16xf32> xegpu.store_nd %out#2, %c_tdesc {layout = #l1}: vector<8x32xf32>, !xegpu.tensor_desc<8x32xf32, #l1> gpu.return @@ -162,7 +168,9 @@ gpu.module @test_kernel { %b_next_tdesc = xegpu.update_nd_offset %arg1, [%c32, %c0] : !xegpu.tensor_desc<32x32xf16, #b> scf.yield %a_next_tdesc, %b_next_tdesc, %c : !xegpu.tensor_desc<16x32xf16, #a>, !xegpu.tensor_desc<32x32xf16, #b>, vector<16x32xf32> - } + } {layout_result_0 = #a, + layout_result_1 = #b, + layout_result_2 = #c} //CHECK-COUNT-4: xegpu.store_nd {{.*}} : vector<8x16xf32>, !xegpu.tensor_desc<8x16xf32, #xegpu.layout> xegpu.store_nd %out#2, %c_tdesc {layout = #c}: vector<16x32xf32>, !xegpu.tensor_desc<16x32xf32, #c> gpu.return @@ -252,7 +260,7 @@ gpu.module @test_kernel { #r = #xegpu.layout gpu.module @test_kernel { gpu.func @reduce_dim_0(%a: memref<16x512xf32>, %b: memref<512xf32>) kernel attributes {VectorComputeFunctionINTEL, spirv.entry_point_abi = #spirv.entry_point_abi<>} { - %acc = arith.constant dense<0.0> : vector<64xf32> + %acc = arith.constant {layout_result_0 = #r} dense<0.0> : vector<64xf32> %c64 = arith.constant 64 : index %block_id_x = gpu.block_id x %m = arith.muli %block_id_x, %c64 : index @@ -274,7 +282,7 @@ gpu.module @test_kernel { gpu.func @reduce_dim_1(%a: memref<512x32xf32>, %b: memref<512xf32>) kernel attributes {VectorComputeFunctionINTEL, spirv.entry_point_abi = #spirv.entry_point_abi<>} { %c1 = arith.constant 1 : index %c32 = arith.constant 32 : index - %acc = arith.constant dense<0.0> : vector<32xf32> + %acc = arith.constant {layout_result_0 = #r} dense<0.0> : vector<32xf32> %block_id_x = gpu.block_id x %block_id_y = gpu.block_id y @@ -324,7 +332,7 @@ gpu.module @test_kernel { %m = arith.muli %block_id_x, %c32 : index %0 = xegpu.create_nd_tdesc %a[%m] : memref<512xf32> -> !xegpu.tensor_desc<32xf32, #r> %1 = xegpu.load_nd %0 {layout = #r}: !xegpu.tensor_desc<32xf32, #r> -> vector<32xf32> - %11 = vector.shape_cast %1 : vector<32xf32> to vector<32x1xf32> + %11 = vector.shape_cast %1 {layout_result_0 = #l} : vector<32xf32> to vector<32x1xf32> // CHECK-COUNT-8: vector.broadcast {{.*}}: vector<16x1xf32> to vector<16x16xf32> %2 = vector.broadcast %11 {layout_result_0 = #l} : vector<32x1xf32> to vector<32x64xf32> %3 = xegpu.create_nd_tdesc %b[0, %m] : memref<16x512xf32> -> !xegpu.tensor_desc<32x64xf32, #l> @@ -358,7 +366,7 @@ gpu.module @test_kernel { gpu.func @test_vector_constant_mask(%src: ui64, %dst: ui64) { //CHECK: arith.constant dense : vector<16xi1> %mask = vector.constant_mask [32] {layout_result_0 = #l} : vector<32xi1> - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #l} dense<[ 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, @@ -377,7 +385,7 @@ gpu.module @test_kernel { %c16 = arith.constant 16 : index //CHECK-COUNT-2: vector.create_mask {{.*}} : vector<16xi1> %mask = vector.create_mask %c16 {layout_result_0 = #l} : vector<32xi1> - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #l} dense<[ 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, @@ -418,7 +426,7 @@ gpu.module @test_kernel { gpu.func @test_prefetch_load_store_update(%src: ui64) { - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #xegpu.layout} dense<[ 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, @@ -428,7 +436,7 @@ gpu.module @test_kernel { %tdesc = xegpu.create_tdesc %src, %cst : ui64, vector<32xindex> -> !xegpu.tensor_desc<32xf32, #xegpu.scatter_tdesc_attr<>, #xegpu.layout> xegpu.prefetch %tdesc {layout = #xegpu.layout}: !xegpu.tensor_desc<32xf32, #xegpu.scatter_tdesc_attr<>, #xegpu.layout> - %delta = arith.constant dense<[ + %delta = arith.constant {layout_result_0 = #xegpu.layout} dense<[ 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64, 128, 128, 128, 128, 128, 128, 128, 128, @@ -438,11 +446,11 @@ gpu.module @test_kernel { : !xegpu.tensor_desc<32xf32, #xegpu.scatter_tdesc_attr<>, #xegpu.layout>, vector<32xindex> %c17 = arith.constant 17: index - %mask = vector.create_mask %c17: vector<32xi1> + %mask = vector.create_mask %c17 {layout_result_0 = #xegpu.layout} : vector<32xi1> %ld_vec = xegpu.load %new_tdesc, %mask {layout = #xegpu.layout}: !xegpu.tensor_desc<32xf32, #xegpu.scatter_tdesc_attr<>, #xegpu.layout>, vector<32xi1> -> vector<32xf32> - %st_vec = arith.addf %ld_vec, %ld_vec : vector<32xf32> + %st_vec = arith.addf %ld_vec, %ld_vec {layout_result_0 = #xegpu.layout} : vector<32xf32> xegpu.store %st_vec, %tdesc, %mask {layout = #xegpu.layout}: vector<32xf32>, !xegpu.tensor_desc<32xf32, #xegpu.scatter_tdesc_attr<>, #xegpu.layout>, @@ -465,7 +473,7 @@ gpu.module @test_kernel { gpu.func @test_prefetch_load_store_update_chunk(%src: ui64) { - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #xegpu.layout} dense<[ 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, @@ -475,7 +483,7 @@ gpu.module @test_kernel { %tdesc = xegpu.create_tdesc %src, %cst : ui64, vector<32xindex> -> !xegpu.tensor_desc<32x4xf32, #xegpu.scatter_tdesc_attr, #xegpu.layout> xegpu.prefetch %tdesc {layout = #xegpu.layout}: !xegpu.tensor_desc<32x4xf32, #xegpu.scatter_tdesc_attr, #xegpu.layout> - %delta = arith.constant dense<[ + %delta = arith.constant {layout_result_0 = #xegpu.layout} dense<[ 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 64, 128, 128, 128, 128, 128, 128, 128, 128, @@ -485,11 +493,11 @@ gpu.module @test_kernel { : !xegpu.tensor_desc<32x4xf32, #xegpu.scatter_tdesc_attr, #xegpu.layout>, vector<32xindex> %c17 = arith.constant 17: index - %mask = vector.create_mask %c17: vector<32xi1> + %mask = vector.create_mask %c17 {layout_result_0 = #xegpu.layout} : vector<32xi1> %ld_vec = xegpu.load %new_tdesc, %mask <{l1_hint = #xegpu.cache_hint, l2_hint = #xegpu.cache_hint, layout = #xegpu.layout}>: !xegpu.tensor_desc<32x4xf32, #xegpu.scatter_tdesc_attr, #xegpu.layout>, vector<32xi1> -> vector<32x4xf32> - %st_vec = arith.addf %ld_vec, %ld_vec : vector<32x4xf32> + %st_vec = arith.addf %ld_vec, %ld_vec {layout_result_0 = #xegpu.layout} : vector<32x4xf32> xegpu.store %st_vec, %tdesc, %mask <{l1_hint = #xegpu.cache_hint, l2_hint = #xegpu.cache_hint, layout = #xegpu.layout}>: vector<32x4xf32>, !xegpu.tensor_desc<32x4xf32, #xegpu.scatter_tdesc_attr, #xegpu.layout>, @@ -521,7 +529,7 @@ gpu.module @test_kernel { gpu.func @test_3d_scattered_tensor_desc(%src: ui64) { - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #l} dense<[ [0, 8, 16, 24, 32, 40, 48, 56], [64, 72, 80, 88, 96, 104, 112, 120], [128, 136, 144, 152, 160, 168, 176, 184], @@ -531,7 +539,7 @@ gpu.module @test_kernel { %tdesc = xegpu.create_tdesc %src, %cst : ui64, vector<4x8xindex> -> !xegpu.tensor_desc<4x8x4xf32, #xegpu.scatter_tdesc_attr, #l> xegpu.prefetch %tdesc {layout = #l}: !xegpu.tensor_desc<4x8x4xf32, #xegpu.scatter_tdesc_attr, #l> - %delta = arith.constant dense<[ + %delta = arith.constant {layout_result_0 = #l} dense<[ [32, 32, 32, 32, 32, 32, 32, 32], [32, 32, 32, 32, 32, 32, 32, 64], [128, 128, 128, 128, 128, 128, 128, 128], @@ -541,7 +549,7 @@ gpu.module @test_kernel { : !xegpu.tensor_desc<4x8x4xf32, #xegpu.scatter_tdesc_attr, #l>, vector<4x8xindex> %c4 = arith.constant 4: index - %mask = vector.create_mask %c4, %c4: vector<4x8xi1> + %mask = vector.create_mask %c4, %c4 {layout_result_0 = #l}: vector<4x8xi1> %ld_vec = xegpu.load %new_tdesc, %mask <{l1_hint = #xegpu.cache_hint, l2_hint = #xegpu.cache_hint, layout = #l}>: !xegpu.tensor_desc<4x8x4xf32, #xegpu.scatter_tdesc_attr, #l>, vector<4x8xi1> -> vector<4x8x4xf32> @@ -643,7 +651,7 @@ gpu.module @test_kernel { // CHECK-LABEL: load_with_offsets // CHECK-COUNT-2: xegpu.load {{.*}}[{{.*}}], {{.*}} <{chunk_size = 1 : i64, l1_hint = #xegpu.cache_hint}> : ui64, vector<16xindex>, vector<16xi1> -> vector<16xf32> gpu.func @load_with_offsets(%src: ui64) -> vector<32xf32> { - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #xegpu.layout} dense<[ 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, @@ -651,7 +659,7 @@ gpu.module @test_kernel { ]> : vector<32xindex> %c17 = arith.constant 17: index - %mask = vector.create_mask %c17: vector<32xi1> + %mask = vector.create_mask %c17 {layout_result_0 = #xegpu.layout}: vector<32xi1> %ld = xegpu.load %src[%cst], %mask {chunk_size = 1, layout = #xegpu.layout, l1_hint = #xegpu.cache_hint} : ui64, vector<32xindex>, vector<32xi1> -> vector<32xf32> gpu.return %ld : vector<32xf32> @@ -663,7 +671,7 @@ gpu.module @test_kernel { // CHECK-LABEL: store_with_offsets // CHECK-COUNT-2: xegpu.store {{.*}}[{{.*}}], {{.*}} <{chunk_size = 1 : i64, l1_hint = #xegpu.cache_hint}> : vector<16xf32>, ui64, vector<16xindex>, vector<16xi1> gpu.func @store_with_offsets(%src: ui64) { - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #xegpu.layout} dense<[ 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, @@ -671,9 +679,9 @@ gpu.module @test_kernel { ]> : vector<32xindex> %c17 = arith.constant 17: index - %mask = vector.create_mask %c17: vector<32xi1> + %mask = vector.create_mask %c17 {layout_result_0 = #xegpu.layout}: vector<32xi1> - %st_vec = arith.constant dense<1023.0>: vector<32xf32> + %st_vec = arith.constant {layout_result_0 = #xegpu.layout} dense<1023.0>: vector<32xf32> xegpu.store %st_vec, %src[%cst], %mask {chunk_size = 1, layout = #xegpu.layout, l1_hint = #xegpu.cache_hint} : vector<32xf32>, ui64, vector<32xindex>, vector<32xi1> gpu.return @@ -690,7 +698,7 @@ gpu.module @test_kernel { // CHECK: [[cst3:%.+]] = arith.constant dense<[0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120]> : vector<16xindex> // CHECK-COUNT-4: xegpu.load {{.*}}[{{.*}}], {{.*}} <{chunk_size = 2 : i64, l1_hint = #xegpu.cache_hint}> : ui64, vector<16xindex>, vector<16xi1> -> vector<16x2xf32> gpu.func @load_with_offsets_chunk(%src: ui64) -> vector<32x4xf32> { - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #xegpu.layout} dense<[ 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, @@ -698,7 +706,7 @@ gpu.module @test_kernel { ]> : vector<32xindex> %c17 = arith.constant 17: index - %mask = vector.create_mask %c17: vector<32xi1> + %mask = vector.create_mask %c17 {layout_result_0 = #xegpu.layout}: vector<32xi1> %ld = xegpu.load %src[%cst], %mask {chunk_size = 4, layout = #xegpu.layout, l1_hint = #xegpu.cache_hint} : ui64, vector<32xindex>, vector<32xi1> -> vector<32x4xf32> gpu.return %ld : vector<32x4xf32> } @@ -714,7 +722,7 @@ gpu.module @test_kernel { // CHECK: [[cst3:%.+]] = arith.constant dense<[0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120]> : vector<16xindex> // CHECK-COUNT-4: xegpu.store {{.*}}[{{.*}}], {{.*}} <{chunk_size = 2 : i64, l1_hint = #xegpu.cache_hint}> : vector<16x2xf32>, ui64, vector<16xindex>, vector<16xi1> gpu.func @store_with_offsets_chunk(%src: ui64) { - %cst = arith.constant dense<[ + %cst = arith.constant {layout_result_0 = #xegpu.layout} dense<[ 0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, @@ -722,9 +730,9 @@ gpu.module @test_kernel { ]> : vector<32xindex> %c17 = arith.constant 17: index - %mask = vector.create_mask %c17: vector<32xi1> + %mask = vector.create_mask %c17 {layout_result_0 = #xegpu.layout}: vector<32xi1> - %st_vec = arith.constant dense<1023.>: vector<32x4xf32> + %st_vec = arith.constant {layout_result_0 = #xegpu.layout} dense<1023.>: vector<32x4xf32> xegpu.store %st_vec, %src[%cst], %mask {chunk_size = 4, layout = #xegpu.layout, l1_hint = #xegpu.cache_hint} : vector<32x4xf32>, ui64, vector<32xindex>, vector<32xi1> gpu.return } diff --git a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir index 6e9711442b92d..762530e5d189f 100644 --- a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir +++ b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-elemwise.mlir @@ -27,11 +27,11 @@ gpu.module @test_elementwise_ops { %load_a = xegpu.load_nd %tdesc_a {layout = #xegpu.layout} : !xegpu.tensor_desc<24x32xf32, #xegpu.layout> -> vector<24x32xf32> - // CHECK: math.exp {{.*}} {layout_result_0 = #xegpu.layout} : vector<12x8xf32> + // CHECK: math.exp {{.*}} : vector<12x8xf32> %exp = math.exp %load_a {layout_result_0 = #xegpu.layout} : vector<24x32xf32> - // CHECK: arith.negf {{.*}} {layout_result_0 = #xegpu.layout} : vector<12x8xf32> + // CHECK: arith.negf {{.*}} : vector<12x8xf32> %negf = arith.negf %load_a {layout_result_0 = #xegpu.layout} : vector<24x32xf32> @@ -50,13 +50,11 @@ gpu.module @test_elementwise_ops { %load_b = xegpu.load_nd %tdesc_b {layout = #xegpu.layout} : !xegpu.tensor_desc<24x32xf32, #xegpu.layout> -> vector<24x32xf32> - // CHECK: arith.addf {{.*}}, {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<12x8xf32> + // CHECK: arith.addf {{.*}}, {{.*}} : vector<12x8xf32> %addf = arith.addf %load_a, %load_b {layout_result_0 = #xegpu.layout} : vector<24x32xf32> - // CHECK: math.powf {{.*}}, {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<12x8xf32> + // CHECK: math.powf {{.*}}, {{.*}} : vector<12x8xf32> %powf = math.powf %load_a, %load_b {layout_result_0 = #xegpu.layout} : vector<24x32xf32> @@ -80,13 +78,11 @@ gpu.module @test_elementwise_ops { %load_c = xegpu.load_nd %tdesc_c {layout = #xegpu.layout} : !xegpu.tensor_desc<24x32xi1, #xegpu.layout> -> vector<24x32xi1> - // CHECK: arith.select {{.*}}, {{.*}}, {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<12x8xi1>, vector<12x8xf32> + // CHECK: arith.select {{.*}}, {{.*}}, {{.*}} : vector<12x8xi1>, vector<12x8xf32> %select = arith.select %load_c, %load_a, %load_b {layout_result_0 = #xegpu.layout} : vector<24x32xi1>, vector<24x32xf32> - // CHECK: math.fma {{.*}}, {{.*}}, {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<12x8xf32> + // CHECK: math.fma {{.*}}, {{.*}}, {{.*}} : vector<12x8xf32> %fma = math.fma %load_a, %load_b, %load_a {layout_result_0 = #xegpu.layout} : vector<24x32xf32> @@ -105,13 +101,11 @@ gpu.module @test_elementwise_ops { %load_b = xegpu.load_nd %tdesc_b {layout = #xegpu.layout} : !xegpu.tensor_desc<24x32xi32, #xegpu.layout> -> vector<24x32xi32> - // CHECK: arith.truncf {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<12x8xf32> to vector<12x8xf16> + // CHECK: arith.truncf {{.*}} : vector<12x8xf32> to vector<12x8xf16> %truncf = arith.truncf %load_a {layout_result_0 = #xegpu.layout} : vector<24x32xf32> to vector<24x32xf16> - // CHECK: arith.bitcast {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<12x8xi32> to vector<12x8xf32> + // CHECK: arith.bitcast {{.*}} : vector<12x8xi32> to vector<12x8xf32> %bitcast = arith.bitcast %load_b {layout_result_0 = #xegpu.layout} : vector<24x32xi32> to vector<24x32xf32> @@ -140,13 +134,11 @@ gpu.module @test_elementwise_ops { %load_d = xegpu.load_nd %tdesc_d {layout = #xegpu.layout} : !xegpu.tensor_desc<24x32xi32, #xegpu.layout> -> vector<24x32xi32> - // CHECK: arith.cmpf ult, {{.*}}, {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<12x8xf32> + // CHECK: arith.cmpf ult, {{.*}}, {{.*}} : vector<12x8xf32> %cmpf = arith.cmpf ult, %load_a, %load_b {layout_result_0 = #xegpu.layout} : vector<24x32xf32> - // CHECK: arith.cmpi eq, {{.*}}, {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<12x8xi32> + // CHECK: arith.cmpi eq, {{.*}}, {{.*}} : vector<12x8xi32> %cmpi = arith.cmpi eq, %load_c, %load_d {layout_result_0 = #xegpu.layout} : vector<24x32xi32> @@ -166,12 +158,12 @@ gpu.module @test_elementwise_ops { %load_b = xegpu.load_nd %tdesc_b {layout = #xegpu.layout} : !xegpu.tensor_desc<24x32xf32, #xegpu.layout> -> vector<24x32xf32> - // CHECK-COUNT-12: arith.negf {{.*}} {layout_result_0 = #xegpu.layout} : vector<2x2xf32> + // CHECK-COUNT-12: arith.negf {{.*}} : vector<2x2xf32> // CHECK-NOT: arith.negf %negf = arith.negf %load_a {layout_result_0 = #xegpu.layout} : vector<24x32xf32> - // CHECK-COUNT-12: math.powf {{.*}}, {{.*}} {layout_result_0 = #xegpu.layout} : vector<2x2xf32> + // CHECK-COUNT-12: math.powf {{.*}}, {{.*}} : vector<2x2xf32> // CHECK-NOT: math.powf %powf = math.powf %load_a, %load_b {layout_result_0 = #xegpu.layout} @@ -179,3 +171,4 @@ gpu.module @test_elementwise_ops { gpu.return } } + diff --git a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir index 6b8b4f282b744..e89cb52ee02f5 100644 --- a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir +++ b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-rr.mlir @@ -116,7 +116,7 @@ gpu.module @test_round_robin_assignment { %load = xegpu.load_nd %tdesc {layout = #xegpu.layout} : !xegpu.tensor_desc<128x1xf32, #xegpu.layout> -> vector<128x1xf32> - // CHECK-COUNT-2: vector.broadcast {{.*}} {layout_result_0 = #xegpu.layout} : vector<16x1xf32> to vector<16x32xf32> + // CHECK-COUNT-2: vector.broadcast {{.*}} : vector<16x1xf32> to vector<16x32xf32> // CHECK-NOT: vector.broadcast %broadcast = vector.broadcast %load {layout_result_0 = #xegpu.layout} diff --git a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir index 4b11270373f95..ecdfdb9ad34c5 100644 --- a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir +++ b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir @@ -26,14 +26,14 @@ gpu.module @test_distribution { // CHECK-LABEL: store_nd_with_offset gpu.func @store_nd_with_offset(%src: memref<256x128xf32>) { - // CHECK-COUNT-4: xegpu.store_nd %{{.*}}, {{%.*}}[{{%.*}}, {{%.*}}] : vector<16x16xf32>, !xegpu.tensor_desc<16x16xf32, #xegpu.layout> + // CHECK-COUNT-4: xegpu.store_nd %{{.*}}, {{%.*}}[{{%.*}}, {{%.*}}] <{layout = #xegpu.layout}> : vector<16x16xf32>, !xegpu.tensor_desc<16x16xf32, #xegpu.layout> // CHECK-NOT: xegpu.store_nd %tdesc = xegpu.create_nd_tdesc %src: memref<256x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.layout> %load = xegpu.load_nd %tdesc[0, 0] {layout = #xegpu.layout} : !xegpu.tensor_desc<256x128xf32, #xegpu.layout> -> vector<256x128xf32> - xegpu.store_nd %load, %tdesc[0, 0] + xegpu.store_nd %load, %tdesc[0, 0] {layout = #xegpu.layout} : vector<256x128xf32>, !xegpu.tensor_desc<256x128xf32, #xegpu.layout> gpu.return } @@ -126,7 +126,7 @@ gpu.module @test_distribution { %load = xegpu.load_nd %tdesc[0, 0] {layout = #xegpu.layout} : !xegpu.tensor_desc<256x128xf32, #xegpu.layout> -> vector<256x128xf32> - // CHECK-COUNT-2: vector.transpose {{.*}}, [1, 0] {layout_result_0 = #xegpu.layout} : vector<32x16xf32> to vector<16x32xf32> + // CHECK-COUNT-2: vector.transpose {{.*}}, [1, 0] : vector<32x16xf32> to vector<16x32xf32> // CHECK-NOT: vector.transpose %trans = vector.transpose %load, [1, 0] {layout_result_0 = #xegpu.layout} : vector<256x128xf32> to vector<128x256xf32> gpu.return @@ -149,13 +149,13 @@ gpu.module @test_distribution { } // CHECK-LABEL: distribute_shapecast_expandunitdims_broadcast - // CHECK: %[[CAST:.*]] = vector.shape_cast %[[REDUCE:.*]] {layout_result_0 = #xegpu.layout} : vector<8xf32> to vector<8x1xf32> - // CHECK: %[[BCAST:.*]] = vector.broadcast %[[CAST]] {layout_result_0 = #xegpu.layout} : vector<8x1xf32> to vector<8x128xf32> + // CHECK: %[[CAST:.*]] = vector.shape_cast %[[REDUCE:.*]] : vector<8xf32> to vector<8x1xf32> + // CHECK: %[[BCAST:.*]] = vector.broadcast %[[CAST]] : vector<8x1xf32> to vector<8x128xf32> gpu.func @distribute_shapecast_expandunitdims_broadcast(%arg0: memref<4096x128xf32>, %arg1: memref<4096x128xf32>) { %cst_0 = arith.constant {layout_result_0=#xegpu.slice<#xegpu.layout, dims = [1]>} dense<0xFF800000> : vector<256xf32> %block_id_x = gpu.block_id x %0 = xegpu.create_nd_tdesc %arg0 : memref<4096x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.block_tdesc_attr, #xegpu.layout> - %1 = xegpu.load_nd %0[%block_id_x, 0] : !xegpu.tensor_desc<256x128xf32, #xegpu.block_tdesc_attr, #xegpu.layout> -> vector<256x128xf32> + %1 = xegpu.load_nd %0[%block_id_x, 0] {layout = #xegpu.layout} : !xegpu.tensor_desc<256x128xf32, #xegpu.block_tdesc_attr, #xegpu.layout> -> vector<256x128xf32> %2 = vector.multi_reduction , %1, %cst_0 {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [1]>} [1] : vector<256x128xf32> to vector<256xf32> %3 = vector.shape_cast %2 {layout_result_0 = #xegpu.layout, layout_operand_0 = #xegpu.slice<#xegpu.layout, dims = [1]>} : vector<256xf32> to vector<256x1xf32> %4 = vector.broadcast %3 {layout_result_0 = #xegpu.layout} : vector<256x1xf32>to vector<256x128xf32> diff --git a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir index 1fc2328d09046..69a2ca7c49c2d 100644 --- a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir +++ b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir @@ -58,7 +58,7 @@ gpu.module @test_distribution { // CHECK-LABEL: store_nd_with_offsets // CHECK-SAME: %[[ARG_0:.*]]: memref<256x128xf32> gpu.func @store_nd_with_offsets(%src: memref<256x128xf32>) { - //CHECK: xegpu.store_nd %{{.*}}, {{%.*}}[{{%.*}}, {{%.*}}] : vector<32x32xf32>, !xegpu.tensor_desc<32x32xf32, #xegpu.layout> + //CHECK: xegpu.store_nd %{{.*}}, {{%.*}}[{{%.*}}, {{%.*}}] <{layout = #xegpu.layout}> : vector<32x32xf32>, !xegpu.tensor_desc<32x32xf32, #xegpu.layout> %tdesc = xegpu.create_nd_tdesc %src: memref<256x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.layout> %load = xegpu.load_nd %tdesc[0, 0] {layout = #xegpu.layout} @@ -130,17 +130,6 @@ gpu.module @test_distribution { gpu.return } - // CHECK-LABEL: dpas_with_no_create_nd_desc - gpu.func @dpas_with_no_create_nd_desc(%a: vector<256x128xf32>, %b: vector<128x256xf32>) { - // CHECK-NOT: vector<32x32xf32> - %dpas = xegpu.dpas %a, %b - {layout_a = #xegpu.layout, - layout_b = #xegpu.layout, - layout_cd = #xegpu.layout} - : vector<256x128xf32>, vector<128x256xf32> -> vector<256x256xf32> - gpu.return - } - // CHECK-LABEL: broadcast_dim1 // CHECK-SAME: %[[ARG_0:.*]]: memref<256x1xf32> gpu.func @broadcast_dim1(%src: memref<256x1xf32>) { @@ -149,8 +138,7 @@ gpu.module @test_distribution { %load = xegpu.load_nd %tdesc[0, 0] {layout = #xegpu.layout} : !xegpu.tensor_desc<256x1xf32, #xegpu.layout> -> vector<256x1xf32> - // CHECK: vector.broadcast {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<32x1xf32> to vector<32x32xf32> + // CHECK: vector.broadcast {{.*}} : vector<32x1xf32> to vector<32x32xf32> %broadcast = vector.broadcast %load {layout_result_0 = #xegpu.layout} : vector<256x1xf32> to vector<256x32xf32> @@ -165,8 +153,7 @@ gpu.module @test_distribution { %load = xegpu.load_nd %tdesc[0, 0] {layout = #xegpu.layout} : !xegpu.tensor_desc<1x128xf32, #xegpu.layout> -> vector<1x128xf32> - // CHECK: vector.broadcast {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<1x32xf32> to vector<32x32xf32> + // CHECK: vector.broadcast {{.*}} : vector<1x32xf32> to vector<32x32xf32> %broadcast = vector.broadcast %load {layout_result_0 = #xegpu.layout} : vector<1x128xf32> to vector<32x128xf32> @@ -204,7 +191,7 @@ gpu.module @test_distribution { // CHECK: [[b:%.+]] = xegpu.load_nd [[DESC_B]][{{%.*}}, {{%.*}}] : !xegpu.tensor_desc<128x16xf16> -> vector<128x16xf16> // CHECK: scf.yield [[a]], [[b]], [[c]] : vector<16x128xf16>, vector<128x16xf16>, vector<16x16xf32> %8:3 = scf.for %arg3 = %c0 to %c1024 step %c128 iter_args(%arg4 = %6, %arg5 = %7, %arg6 = %5) - -> (vector<128x128xf16>, vector<128x128xf16>, vector<128x128xf32>) { + -> (vector<128x128xf16>, vector<128x128xf16>, vector<128x128xf32>) { // load_nd with offset inside loop %9 = xegpu.dpas %arg4, %arg5, %arg6 {layout_a = #xegpu.layout, @@ -214,9 +201,11 @@ gpu.module @test_distribution { %10 = xegpu.load_nd %3[%arg3, %c0] {layout = #xegpu.layout}: !xegpu.tensor_desc<128x128xf16, #xegpu.layout> -> vector<128x128xf16> %11 = xegpu.load_nd %4[%c0, %arg3] {layout = #xegpu.layout}: !xegpu.tensor_desc<128x128xf16, #xegpu.layout> -> vector<128x128xf16> scf.yield %10, %11, %9 : vector<128x128xf16>, vector<128x128xf16>, vector<128x128xf32> - } + } {layout_result_0 = #xegpu.layout, + layout_result_1 = #xegpu.layout, + layout_result_2 = #xegpu.layout} // store_nd with offset - xegpu.store_nd %8#2, %2[%0, %1] : vector<128x128xf32>, !xegpu.tensor_desc<128x128xf32, #xegpu.layout> + xegpu.store_nd %8#2, %2[%0, %1] {layout = #xegpu.layout} : vector<128x128xf32>, !xegpu.tensor_desc<128x128xf32, #xegpu.layout> gpu.return } @@ -303,9 +292,9 @@ gpu.module @test_distribution { // CHECK-LABEL: @store_scatter // CHECK-SAME: %[[ARG0:.*]]: memref<256xf16> gpu.func @store_scatter(%dest : memref<256xf16>) { - // CHECK: %[[VAL:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<2.550000e+01> : vector<8xf16> - // CHECK: %[[CST:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense<0> : vector<8xindex> - // CHECK: %[[MASK:.*]] = arith.constant {layout_result_0 = #xegpu.layout} dense : vector<8xi1> + // CHECK: %[[VAL:.*]] = arith.constant dense<2.550000e+01> : vector<8xf16> + // CHECK: %[[CST:.*]] = arith.constant dense<0> : vector<8xindex> + // CHECK: %[[MASK:.*]] = arith.constant dense : vector<8xi1> // CHECK: xegpu.store %[[VAL]], %[[ARG0]][%[[CST]]], %[[MASK]] <{chunk_size = 1 : i64, l1_hint = #xegpu.cache_hint, layout = #xegpu.layout}> // CHECK-SAME: : vector<8xf16>, memref<256xf16>, vector<8xindex>, vector<8xi1> %val = arith.constant {layout_result_0 = #xegpu.layout} dense<25.5> : vector<256xf16> @@ -489,7 +478,7 @@ gpu.module @test_distribution { %load = xegpu.load_nd %tdesc[0, 0] {layout = #xegpu.layout} : !xegpu.tensor_desc<256x32xf32, #xegpu.layout> -> vector<256x32xf32> - //CHECK: vector.transpose {{.*}}, [1, 0] {layout_result_0 = #xegpu.layout} : vector<64x32xf32> to vector<32x64xf32> + //CHECK: vector.transpose {{.*}}, [1, 0] : vector<64x32xf32> to vector<32x64xf32> %trans = vector.transpose %load, [1, 0] {layout_result_0 = #xegpu.layout} : vector<256x32xf32> to vector<32x256xf32> gpu.return } @@ -645,7 +634,7 @@ gpu.module @test_distribution { // CHECK-SAME: memref<4096xf32>, vector<32xindex>, vector<32xi1> -> vector<32xf32> %3 = xegpu.load %2[%offset], %mask {chunk_size = 1, layout = #xegpu.slice<#xegpu.layout, dims = [0]> } : memref<4096xf32>, vector<256xindex>, vector<256xi1> -> vector<256xf32> - // CHECK: %[[BROADCAST:.*]] = vector.broadcast %[[LOAD]] {layout_result_0 = #xegpu.layout} : vector<32xf32> to vector<32x32xf32> + // CHECK: %[[BROADCAST:.*]] = vector.broadcast %[[LOAD]] : vector<32xf32> to vector<32x32xf32> %4 = vector.broadcast %3 {layout_result_0 = #xegpu.layout} : vector<256xf32> to vector<256x256xf32> gpu.return @@ -674,7 +663,7 @@ gpu.module @test_distribution { // CHECK-DAG: %[[MUL3:.*]] = arith.muli %[[AFFINE3]], %[[C1:.*]] : index // CHECK-DAG: %[[ADD2:.*]] = arith.addi %[[ADD1]], %[[MUL3]] : index // CHECK-DAG: %[[COL_OFFSET:.*]] = arith.muli %[[ADD2]], %[[C32:.*]] : index - // CHECK-DAG: xegpu.store_matrix %[[SHAPE_CAST]], %[[MEM_DESC]][%[[ROW_OFFSET]], %[[COL_OFFSET]]] <{layout = #xegpu.slice<#xegpu.layout<>, dims = [1]>}>: vector<1x32xf32>, !xegpu.mem_desc<32x32xf32>, index, index + // CHECK-DAG: xegpu.store_matrix %[[SHAPE_CAST]], %[[MEM_DESC]][%[[ROW_OFFSET]], %[[COL_OFFSET]]] : vector<1x32xf32>, !xegpu.mem_desc<32x32xf32>, index, index // CHECK-DAG: gpu.barrier // CHECK-DAG: %[[LOAD_SLM:.*]] = xegpu.load_matrix %[[MEM_DESC]][%[[C0:.*]], %[[COL_OFFSET]]] : !xegpu.mem_desc<32x32xf32>, index, index -> vector<32x32xf32> // CHECK-DAG: %[[CST_3:.*]] = arith.constant dense<0.000000e+00> : vector<32xf32> @@ -717,7 +706,7 @@ gpu.module @test_distribution { // CHECK-DAG: %[[MUL4:.*]] = arith.muli {{.*}}, %[[C1:.*]] : index // CHECK-DAG: %[[ADD1:.*]] = arith.addi %[[C0:.*]], %[[MUL4]] : index // CHECK-DAG: %[[COL_OFFSET:.*]] = arith.muli %[[ADD1]], %[[C32:.*]] : index - // CHECK-DAG: xegpu.store_matrix %[[SHAPE_CAST]], %[[MEM_DESC]][%[[ROW_OFFSET]], %[[COL_OFFSET]]] <{layout = #xegpu.slice<#xegpu.layout<>, dims = [0]>}>: vector<1x32xf32>, !xegpu.mem_desc<8x128xf32>, index, index + // CHECK-DAG: xegpu.store_matrix %[[SHAPE_CAST]], %[[MEM_DESC]][%[[ROW_OFFSET]], %[[COL_OFFSET]]] : vector<1x32xf32>, !xegpu.mem_desc<8x128xf32>, index, index // CHECK-DAG: gpu.barrier // CHECK-DAG: %[[LOAD_SLM:.*]] = xegpu.load_matrix %[[MEM_DESC]][%[[C0:.*]], %[[COL_OFFSET]]] : !xegpu.mem_desc<8x128xf32>, index, index -> vector<8x32xf32> // CHECK-DAG: %[[CST_CROSS_SG_1:.*]] = arith.constant dense<0.000000e+00> : vector<32xf32> @@ -726,7 +715,7 @@ gpu.module @test_distribution { %cst = arith.constant {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} dense<0.0> : vector<128xf32> %tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<256x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.layout> - %load = xegpu.load_nd %tdesc + %load = xegpu.load_nd %tdesc {layout = #xegpu.layout} : !xegpu.tensor_desc<256x128xf32, #xegpu.layout> -> vector<256x128xf32> %reduce = vector.multi_reduction , %load, %cst {layout_result_0 = #xegpu.slice<#xegpu.layout, dims = [0]>} [0] @@ -766,7 +755,7 @@ gpu.module @test_distribution { // CHECK-DAG: %[[MUL4:.*]] = arith.muli {{.*}}, %[[C2:.*]] : index // CHECK-DAG: %[[ADD3:.*]] = arith.addi %[[ADD2]], %[[MUL4]] : index // CHECK-DAG: %[[COL_OFFSET:.*]] = arith.muli %[[ADD3]], %[[C1:.*]] : index - // CHECK-DAG: xegpu.store_matrix %[[SHAPE_CAST]], %[[MEM_DESC]][%[[ROW_OFFSET]], %[[COL_OFFSET]]] <{layout = #xegpu.slice<#xegpu.layout<>, dims = [2, 3]>}>: vector<1x1xf32>, !xegpu.mem_desc<16x4xf32>, index, index + // CHECK-DAG: xegpu.store_matrix %[[SHAPE_CAST]], %[[MEM_DESC]][%[[ROW_OFFSET]], %[[COL_OFFSET]]] : vector<1x1xf32>, !xegpu.mem_desc<16x4xf32>, index, index // CHECK-DAG: gpu.barrier // CHECK-DAG: %[[LOAD_SLM:.*]] = xegpu.load_matrix %[[MEM_DESC]][%[[C0:.*]], %[[COL_OFFSET]]] : !xegpu.mem_desc<16x4xf32>, index, index -> vector<16x1xf32> // CHECK-DAG: %[[CST_3:.*]] = arith.constant dense<0.000000e+00> : vector<1xf32> @@ -810,7 +799,7 @@ gpu.module @test_distribution { // CHECK-DAG: %[[MUL4:.*]] = arith.muli {{.*}}, %[[C2:.*]] : index // CHECK-DAG: %[[ADD3:.*]] = arith.addi %[[ADD2]], %[[MUL4]] : index // CHECK-DAG: %[[COL_OFFSET:.*]] = arith.muli %[[ADD3]], %[[C256:.*]] : index - // CHECK-DAG: xegpu.store_matrix %[[SHAPE_CAST]], %[[MEM_DESC]][%[[ROW_OFFSET]], %[[COL_OFFSET]]] <{layout = #xegpu.slice<#xegpu.layout<>, dims = [2, 3]>}>: vector<1x256xf32>, !xegpu.mem_desc<16x1024xf32>, index, index + // CHECK-DAG: xegpu.store_matrix %[[SHAPE_CAST]], %[[MEM_DESC]][%[[ROW_OFFSET]], %[[COL_OFFSET]]] : vector<1x256xf32>, !xegpu.mem_desc<16x1024xf32>, index, index // CHECK-DAG: gpu.barrier // CHECK-DAG: %[[LOAD_SLM:.*]] = xegpu.load_matrix %[[MEM_DESC]][%[[C0:.*]], %[[COL_OFFSET]]] : !xegpu.mem_desc<16x1024xf32>, index, index -> vector<16x256xf32> // CHECK-DAG: %[[CST_3:.*]] = arith.constant dense<0.000000e+00> : vector<256xf32> diff --git a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir index 4f29a686d301f..467c53fa20f94 100644 --- a/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir +++ b/mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir @@ -63,7 +63,7 @@ gpu.module @test_1_1_assignment { // CHECK-SAME: : vector<32x32xf32>, !xegpu.tensor_desc<32x32xf32, #xegpu.layout> %tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<256x128xf32> -> !xegpu.tensor_desc<256x128xf32, #xegpu.layout> - %load = xegpu.load_nd %tdesc + %load = xegpu.load_nd %tdesc {layout = #xegpu.layout} : !xegpu.tensor_desc<256x128xf32, #xegpu.layout> -> vector<256x128xf32> xegpu.store_nd %load, %tdesc @@ -141,27 +141,15 @@ gpu.module @test_1_1_assignment { gpu.return } - // CHECK-LABEL: dpas_with_no_create_nd_desc - gpu.func @dpas_with_no_create_nd_desc(%a: vector<256x128xf32>, %b: vector<128x256xf32>) { - // CHECK-NOT: vector<32x32xf32> - %dpas = xegpu.dpas %a, %b - {layout_a = #xegpu.layout, - layout_b = #xegpu.layout, - layout_cd = #xegpu.layout} - : vector<256x128xf32>, vector<128x256xf32> -> vector<256x256xf32> - gpu.return - } - // CHECK-LABEL: broadcast_dim1 // CHECK-SAME: %[[ARG_0:.*]]: memref<256x1xf32> gpu.func @broadcast_dim1(%src: memref<256x1xf32>) { %tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<256x1xf32> -> !xegpu.tensor_desc<256x1xf32, #xegpu.layout> - %load = xegpu.load_nd %tdesc + %load = xegpu.load_nd %tdesc {layout = #xegpu.layout} : !xegpu.tensor_desc<256x1xf32, #xegpu.layout> -> vector<256x1xf32> - // CHECK: vector.broadcast {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<32x1xf32> to vector<32x32xf32> + // CHECK: vector.broadcast {{.*}} : vector<32x1xf32> to vector<32x32xf32> %broadcast = vector.broadcast %load {layout_result_0 = #xegpu.layout} : vector<256x1xf32> to vector<256x32xf32> @@ -173,11 +161,10 @@ gpu.module @test_1_1_assignment { gpu.func @broadcast_dim0(%src: memref<1x128xf32>) { %tdesc = xegpu.create_nd_tdesc %src[0, 0] : memref<1x128xf32> -> !xegpu.tensor_desc<1x128xf32, #xegpu.layout> - %load = xegpu.load_nd %tdesc + %load = xegpu.load_nd %tdesc {layout = #xegpu.layout} : !xegpu.tensor_desc<1x128xf32, #xegpu.layout> -> vector<1x128xf32> - // CHECK: vector.broadcast {{.*}} {layout_result_0 = #xegpu.layout} - // CHECK-SAME: : vector<1x32xf32> to vector<32x32xf32> + // CHECK: vector.broadcast {{.*}} : vector<1x32xf32> to vector<32x32xf32> %broadcast = vector.broadcast %load {layout_result_0 = #xegpu.layout} : vector<1x128xf32> to vector<32x128xf32> @@ -222,7 +209,9 @@ gpu.module @test_1_1_assignment { %12 = xegpu.update_nd_offset %arg5, [%c128, %c0] : !xegpu.tensor_desc<128x128xf16, #xegpu.layout> scf.yield %11, %12, %10 : !xegpu.tensor_desc<128x128xf16, #xegpu.layout>, !xegpu.tensor_desc<128x128xf16, #xegpu.layout>, vector<128x128xf32> - } + } {layout_result_0 = #xegpu.layout, + layout_result_1 = #xegpu.layout, + layout_result_2 = #xegpu.layout} %7 = xegpu.create_nd_tdesc %arg2[%0, %1] : memref<1024x1024xf32> -> !xegpu.tensor_desc<128x128xf32, #xegpu.layout> xegpu.store_nd %6#2, %7 {layout = #xegpu.layout } : vector<128x128xf32>, !xegpu.tensor_desc<128x128xf32, #xegpu.layout> @@ -288,7 +277,7 @@ gpu.module @test_1_1_assignment { %id = gpu.subgroup_id : index %t = xegpu.create_nd_tdesc %arg0[0] : memref<1024xf32> -> !xegpu.tensor_desc<256xf32, #xegpu.layout> - %d = xegpu.load_nd %t : !xegpu.tensor_desc<256xf32, #xegpu.layout> -> vector<256xf32> + %d = xegpu.load_nd %t {layout = #xegpu.layout} : !xegpu.tensor_desc<256xf32, #xegpu.layout> -> vector<256xf32> %0 = arith.cmpi eq, %id, %c10 : index // CHECK-LABEL: scf.if @@ -340,7 +329,7 @@ gpu.module @test_1_1_assignment { // CHECK: %[[SUB:.*]] = index.sub %{{.*}}, %[[C2]] %tdesc = xegpu.create_nd_tdesc %src2[0, 0] : memref<128x64xf32> -> !xegpu.tensor_desc<128x64xf32, #xegpu.layout> - %load = xegpu.load_nd %tdesc + %load = xegpu.load_nd %tdesc {layout = #xegpu.layout} : !xegpu.tensor_desc<128x64xf32, #xegpu.layout> -> vector<128x64xf32> %exp = math.exp %load {layout_result_0 = #xegpu.layout} : vector<128x64xf32> @@ -369,7 +358,7 @@ gpu.module @test_1_1_assignment { // CHECK: %[[SUB:.*]] = index.sub %{{.*}}, %[[C3]] %td = xegpu.create_nd_tdesc %src1[0, 0] : memref<128x64xf32> -> !xegpu.tensor_desc<128x64xf32, #xegpu.layout> - %ld = xegpu.load_nd %td + %ld = xegpu.load_nd %td {layout = #xegpu.layout} : !xegpu.tensor_desc<128x64xf32, #xegpu.layout> -> vector<128x64xf32> %exp = math.exp %ld {layout_result_0 = #xegpu.layout} : vector<128x64xf32> diff --git a/mlir/test/IR/test-symbol-uses.mlir b/mlir/test/IR/test-symbol-uses.mlir index 54e3ef1812510..d9d839e9fc307 100644 --- a/mlir/test/IR/test-symbol-uses.mlir +++ b/mlir/test/IR/test-symbol-uses.mlir @@ -68,3 +68,28 @@ func.func @symbol_bar() { "foo.possibly_unknown_symbol_table"() ({ }) : () -> () } + +// ----- + +module { + // expected-remark@below {{symbol has 2 uses}} + module @inner_module { + // expected-remark@below {{symbol has 1 uses}} + func.func private @private_inner() + // expected-remark@below {{symbol has 1 uses}} + func.func nested @nested_inner() + } + + + // expected-remark@below {{symbol has no uses}} + // expected-remark@below {{symbol contains 2 nested references}} + func.func @outer_caller() { + // expected-remark@below {{found use of symbol : @inner_module::@nested_inner : "inner_module"}} + // expected-remark@below {{found use of symbol : @inner_module::@nested_inner : "nested_inner"}} + "foo.op"() { use = @inner_module::@nested_inner } : () -> () + // expected-remark@below {{failed to resolve use of symbol : @inner_module::@private_inner : "inner_module"}} + // expected-remark@below {{failed to resolve use of symbol : @inner_module::@private_inner : "private_inner"}} + "foo.op"() { use = @inner_module::@private_inner } : () -> () + return + } +} diff --git a/mlir/test/IR/test-verifiers-type.mlir b/mlir/test/IR/test-verifiers-type.mlir index 6512a1b9c8711..a6a5fa3d4fc9f 100644 --- a/mlir/test/IR/test-verifiers-type.mlir +++ b/mlir/test/IR/test-verifiers-type.mlir @@ -22,3 +22,51 @@ // expected-error @below{{failed to verify 'elementType': VectorElementTypeInterface instance}} "test.type_producer"() : () -> vector> + +// ----- + +// Test PredTypeTrait with single parameter - valid case. +// CHECK: "test.type_producer"() : () -> !test.type_pred_trait<5> +"test.type_producer"() : () -> !test.type_pred_trait<5> + +// ----- + +// Test PredTypeTrait with single parameter - invalid case (zero is not positive). +// expected-error @below{{failed to verify that value must be positive}} +"test.type_producer"() : () -> !test.type_pred_trait<0> + +// ----- + +// Test PredTypeTrait with multiple parameters - valid case (5 >= 3). +// CHECK: "test.type_producer"() : () -> !test.type_pred_trait_multi<5, 3> +"test.type_producer"() : () -> !test.type_pred_trait_multi<5, 3> + +// ----- + +// Test PredTypeTrait with multiple parameters - edge case (3 >= 3). +// CHECK: "test.type_producer"() : () -> !test.type_pred_trait_multi<3, 3> +"test.type_producer"() : () -> !test.type_pred_trait_multi<3, 3> + +// ----- + +// Test PredTypeTrait with multiple parameters - invalid case (2 < 5). +// expected-error @below{{failed to verify that value must be at least min}} +"test.type_producer"() : () -> !test.type_pred_trait_multi<2, 5> + +// ----- + +// Test combined parameter constraint + PredTypeTrait - valid case. +// CHECK: "test.type_producer"() : () -> !test.type_pred_trait_combined<3, [1, 2, 3], i32> +"test.type_producer"() : () -> !test.type_pred_trait_combined<3, [1, 2, 3], i32> + +// ----- + +// Test combined - parameter type constraint fails (f16 not in [I16, I32]). +// expected-error @below{{failed to verify 'elementType': 16-bit signless integer or 32-bit signless integer}} +"test.type_producer"() : () -> !test.type_pred_trait_combined<2, [1, 2], f16> + +// ----- + +// Test combined - PredTypeTrait fails (count 2 != elements.size() 3). +// expected-error @below{{failed to verify that count must match number of elements}} +"test.type_producer"() : () -> !test.type_pred_trait_combined<2, [1, 2, 3], i16> diff --git a/mlir/test/Interfaces/TilingInterface/tile-fuse-and-yield-using-scfforall.mlir b/mlir/test/Interfaces/TilingInterface/tile-fuse-and-yield-using-scfforall.mlir index 8fc8f3245be15..3de6c9cb2b398 100644 --- a/mlir/test/Interfaces/TilingInterface/tile-fuse-and-yield-using-scfforall.mlir +++ b/mlir/test/Interfaces/TilingInterface/tile-fuse-and-yield-using-scfforall.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt -transform-interpreter -cse -split-input-file %s | FileCheck %s +// RUN: mlir-opt -transform-interpreter -cse -canonicalize -split-input-file %s | FileCheck %s func.func @gemm_gemm_fusion_yield_both(%lhs0 : tensor, %rhs0 : tensor, %rhs1 : tensor, %init0 : tensor, %init1 : tensor) @@ -58,3 +58,71 @@ module attributes {transform.with_named_sequence} { // CHECK: tensor.parallel_insert_slice %[[GEMM1_TILE]] into %[[ITERARG0]][%[[IV]], 0] // CHECK: tensor.parallel_insert_slice %[[GEMM0_TILE]] into %[[ITERARG1]][%[[IV]], 0] // CHECK: return %[[RESULT]]#1, %[[RESULT]]#0 + +// ----- + +func.func @fuse_pack_consumer_into_multi_output_generic( + %input: tensor<32x1024xf32>) -> (tensor<32x1024xf32>, tensor<2x512x16x2xi8>) { + %c0_i8 = arith.constant 0 : i8 + %output_f32 = tensor.empty() : tensor<32x1024xf32> + %output_i8 = tensor.empty() : tensor<32x1024xi8> + %pack_dest = tensor.empty() : tensor<2x512x16x2xi8> + + %gen:2 = linalg.generic { + indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>, + affine_map<(d0, d1) -> (d0, d1)>, + affine_map<(d0, d1) -> (d0, d1)>], + iterator_types = ["parallel", "parallel"] + } ins(%input : tensor<32x1024xf32>) + outs(%output_f32, %output_i8 : tensor<32x1024xf32>, tensor<32x1024xi8>) { + ^bb0(%in: f32, %out_f: f32, %out_i: i8): + %q = arith.fptoui %in : f32 to i8 + linalg.yield %in, %q : f32, i8 + } -> (tensor<32x1024xf32>, tensor<32x1024xi8>) + + %pack = linalg.pack %gen#1 + padding_value(%c0_i8 : i8) + inner_dims_pos = [0, 1] + inner_tiles = [16, 2] + into %pack_dest : tensor<32x1024xi8> -> tensor<2x512x16x2xi8> + + return %gen#0, %pack : tensor<32x1024xf32>, tensor<2x512x16x2xi8> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { + %pack = transform.structured.match ops{["linalg.pack"]} in %arg0 + : (!transform.any_op) -> !transform.any_op + %a, %b = transform.test.fuse_and_yield %pack [1] use_forall true + : (!transform.any_op) -> (!transform.any_op, !transform.any_op) + transform.yield + } +} +// CHECK: #[[$MAP0:.+]] = affine_map<(d0) -> (d0 * 16)> +// CHECK: #[[$MAP1:.+]] = affine_map<(d0) -> (d0 * -16 + 32, 16)> +// CHECK: #[[$MAP2:.+]] = affine_map<(d0, d1) -> (d0, d1)> +// CHECK: func.func @fuse_pack_consumer_into_multi_output_generic( +// CHECK-SAME: %[[INPUT:[a-zA-Z0-9]+]]: tensor<32x1024xf32>) +// CHECK-DAG: %[[C0_I8:.+]] = arith.constant 0 : i8 +// CHECK-DAG: %[[OUTPUT_F32:.+]] = tensor.empty() : tensor<32x1024xf32> +// CHECK-DAG: %[[OUTPUT_I8:.+]] = tensor.empty() : tensor<32x1024xi8> +// CHECK-DAG: %[[PACK_DEST:.+]] = tensor.empty() : tensor<2x512x16x2xi8> +// CHECK: %[[RESULT:.+]]:2 = scf.forall (%[[IV:.+]]) in (2) +// CHECK-SAME: shared_outs(%[[ITERARG0:[a-zA-Z0-9]+]] = %[[PACK_DEST]], %[[ITERARG1:[a-zA-Z0-9]+]] = %[[OUTPUT_F32]]) +// CHECK: %[[OFFSET:.+]] = affine.apply #[[$MAP0]](%[[IV]]) +// CHECK: %[[SIZE:.+]] = affine.min #[[$MAP1]](%[[IV]]) +// CHECK-DAG: %[[INPUT_TILE:.+]] = tensor.extract_slice %[[INPUT]][%[[OFFSET]], 0] [%[[SIZE]], 1024] +// CHECK-DAG: %[[F32_TILE:.+]] = tensor.extract_slice %[[ITERARG1]][%[[OFFSET]], 0] [%[[SIZE]], 1024] +// CHECK-DAG: %[[I8_TILE:.+]] = tensor.extract_slice %[[OUTPUT_I8]][%[[OFFSET]], 0] [%[[SIZE]], 1024] +// CHECK: %[[GENERIC_TILE:.+]]:2 = linalg.generic +// CHECK-SAME: ins(%[[INPUT_TILE]] : +// CHECK-SAME: outs(%[[F32_TILE]], %[[I8_TILE]] : +// CHECK-DAG: %[[PACK_DEST_TILE:.+]] = tensor.extract_slice %[[ITERARG0]][%[[IV]], 0, 0, 0] [1, 512, 16, 2] +// CHECK: %[[PACK_TILE:.+]] = linalg.pack %[[GENERIC_TILE]]#1 +// CHECK-SAME: padding_value(%[[C0_I8]] : i8) +// CHECK-SAME: inner_dims_pos = [0, 1] inner_tiles = [16, 2] +// CHECK-SAME: into %[[PACK_DEST_TILE]] +// CHECK: scf.forall.in_parallel { +// CHECK: tensor.parallel_insert_slice %[[PACK_TILE]] into %[[ITERARG0]][%[[IV]], 0, 0, 0] [1, 512, 16, 2] +// CHECK: tensor.parallel_insert_slice %[[GENERIC_TILE]]#0 into %[[ITERARG1]][%[[OFFSET]], 0] [%[[SIZE]], 1024] +// CHECK: return %[[RESULT]]#1, %[[RESULT]]#0 diff --git a/mlir/test/Rewrite/pdl-bytecode.mlir b/mlir/test/Rewrite/pdl-bytecode.mlir index 8221f009a659f..844f832cd22c6 100644 --- a/mlir/test/Rewrite/pdl-bytecode.mlir +++ b/mlir/test/Rewrite/pdl-bytecode.mlir @@ -956,6 +956,92 @@ module @ir attributes { test.foreach } { // ----- +// Test pdl_interp.foreach over a range of types. +module @patterns { + pdl_interp.func @matcher(%root : !pdl.operation) { + pdl_interp.check_operation_name of %root is "test.success_op" -> ^pat, ^end + + ^pat: + %results = pdl_interp.get_results of %root : !pdl.range + %types = pdl_interp.get_value_type of %results : !pdl.range + // Iterate over the types of the results of the root op + pdl_interp.foreach %type : !pdl.type in %types { + // Only match if the type is i64, verifying we introspect all types + // but only trigger one rewrite + pdl_interp.check_type %type is i64 -> ^record, ^cont + ^record: + pdl_interp.record_match @rewriters::@success(%root, %type : !pdl.operation, !pdl.type) : benefit(1), loc([%root]) -> ^cont + ^cont: + pdl_interp.continue + } -> ^end + + ^end: + pdl_interp.finalize + } + + module @rewriters { + pdl_interp.func @success(%root : !pdl.operation, %type : !pdl.type) { + // Create an op for the matched i64 type + pdl_interp.create_operation "test.type_found" -> (%type : !pdl.type) + pdl_interp.erase %root + pdl_interp.finalize + } + } +} +// CHECK-LABEL: test.foreach_type +// CHECK: "test.type_found"() : () -> i64 +// CHECK-NOT: "test.type_found" +module @ir attributes { test.foreach_type } { + "test.success_op"() : () -> (i32, i64) +} +// ----- + +// Test pdl_interp.foreach over a range of values returned by native constraint. +module @patterns { + pdl_interp.func @matcher(%root : !pdl.operation) { + pdl_interp.check_operation_name of %root is "test.success_op" -> ^pat, ^end + + ^pat: + %values = pdl_interp.apply_constraint "op_constr_return_value_range"(%root : !pdl.operation) : !pdl.range -> ^loop, ^end + + ^loop: + pdl_interp.foreach %val : !pdl.value in %values { + %type = pdl_interp.get_value_type of %val : !pdl.type + // Only match if the type is f16, verifying we introspect all values + // but only trigger one rewrite + pdl_interp.check_type %type is f16 -> ^record, ^cont + ^record: + pdl_interp.record_match @rewriters::@success(%root, %val : !pdl.operation, !pdl.value) : benefit(1), loc([%root]) -> ^cont + ^cont: + pdl_interp.continue + } -> ^end + + ^end: + pdl_interp.finalize + } + + module @rewriters { + pdl_interp.func @success(%root : !pdl.operation, %val : !pdl.value) { + %type = pdl_interp.get_value_type of %val : !pdl.type + pdl_interp.create_operation "test.value_found"(%val : !pdl.value) -> (%type : !pdl.type) + pdl_interp.erase %root + pdl_interp.finalize + } + } +} + +// CHECK-LABEL: test.foreach_value +// CHECK: %[[VAL1:.*]] = "test.input1" +// CHECK: "test.value_found"(%[[VAL1]]) : (f16) -> f16 +// CHECK-NOT: "test.value_found" +module @ir attributes { test.foreach_value } { + %0 = "test.input0"() : () -> f32 + %1 = "test.input1"() : () -> f16 + "test.success_op"(%0, %1) : (f32, f16) -> () +} + +// ----- + //===----------------------------------------------------------------------===// // pdl_interp::GetUsersOp //===----------------------------------------------------------------------===// diff --git a/mlir/test/Target/LLVMIR/Import/function-attributes.ll b/mlir/test/Target/LLVMIR/Import/function-attributes.ll index 153912fbae34a..60347ec010fc7 100644 --- a/mlir/test/Target/LLVMIR/Import/function-attributes.ll +++ b/mlir/test/Target/LLVMIR/Import/function-attributes.ll @@ -303,18 +303,6 @@ declare void @align_decl() align 64 ; // ----- -; CHECK-LABEL: @func_attr_no_infs_fp_math_true -; CHECK-SAME: attributes {no_infs_fp_math = true} -declare void @func_attr_no_infs_fp_math_true() "no-infs-fp-math"="true" - -; // ----- - -; CHECK-LABEL: @func_attr_no_infs_fp_math_false -; CHECK-SAME: attributes {no_infs_fp_math = false} -declare void @func_attr_no_infs_fp_math_false() "no-infs-fp-math"="false" - -; // ----- - ; CHECK-LABEL: @func_attr_no_nans_fp_math_true ; CHECK-SAME: attributes {no_nans_fp_math = true} declare void @func_attr_no_nans_fp_math_true() "no-nans-fp-math"="true" @@ -339,15 +327,20 @@ declare void @func_attr_no_signed_zeros_fp_math_false() "no-signed-zeros-fp-math ; // ----- -; CHECK-LABEL: @func_attr_denormal_fp_math_ieee -; CHECK-SAME: attributes {denormal_fp_math = "ieee"} -declare void @func_attr_denormal_fp_math_ieee() "denormal-fp-math"="ieee" +; CHECK-LABEL: @func_attr_denormal_fp_math_ieee(){{$}} +declare void @func_attr_denormal_fp_math_ieee() denormal_fpenv(ieee) ; // ----- ; CHECK-LABEL: @func_attr_denormal_fp_math_f32_preserve_sign -; CHECK-SAME: attributes {denormal_fp_math_f32 = "preserve-sign"} -declare void @func_attr_denormal_fp_math_f32_preserve_sign() "denormal-fp-math-f32"="preserve-sign" +; CHECK-SAME: attributes {denormal_fpenv = #llvm.denormal_fpenv} +declare void @func_attr_denormal_fp_math_f32_preserve_sign() denormal_fpenv(float: preservesign) + +; // ----- + +; CHECK-LABEL: @func_attr_mixed_denormal_modes +; CHECK: attributes {denormal_fpenv = #llvm.denormal_fpenv} +declare void @func_attr_mixed_denormal_modes() denormal_fpenv(dynamic|preservesign, float: preservesign|dynamic) ; // ----- @@ -459,5 +452,61 @@ declare void @modular_format_attribute(i32) "modular-format" = "Ident,1,1,Foo,Ba // ----- +; CHECK-LABEL: @no_builtins_all +; CHECK-SAME: attributes {nobuiltins = []} +declare void @no_builtins_all() "no-builtins" + +// ----- + +; CHECK-LABEL: @no_builtins_2 +; CHECK-SAME: attributes {nobuiltins = ["asdf", "defg"]} +declare void @no_builtins_2() "no-builtin-asdf" "no-builtin-defg" + +// ----- + +; CHECK-LABEL: @alloc_size_1 +; CHECK-SAME: attributes {allocsize = array} +declare void @alloc_size_1(i32) allocsize(0) + +// ----- + +; CHECK-LABEL: @alloc_size_2 +; CHECK-SAME: attributes {allocsize = array} +declare void @alloc_size_2(i32, i32) allocsize(0, 1) + +// ----- + +; CHECK-LABEL: @minsize +; CHECK-SAME: attributes {minsize} +declare void @minsize() minsize + +// ----- + +; CHECK-LABEL: @optsize +; CHECK-SAME: attributes {optsize} +declare void @optsize() optsize + +// ----- + +; CHECK-LABEL: @save_reg_params +; CHECK-SAME: attributes {save_reg_params} +declare void @save_reg_params() "save-reg-params" + +// ----- + +; CHECK-LABEL: @zero_call_used_regs +; CHECK-SAME: attributes {zero_call_used_regs = "skip"} +declare void @zero_call_used_regs() "zero-call-used-regs"="skip" + +// ----- + +; Note: the 'default-func-attrs' aren't recoverable due to the way they lower +; to LLVM-IR, so they are handled on import as passthrough attributes. +; CHECK-LABEL: @default_func_attrs +; CHECK-SAME: attributes {passthrough = {{\[}}["key", "value"], "keyOnly"]} +declare void @default_func_attrs() "key"="value" "keyOnly" + +// ----- + ; expected-warning @unknown {{'preallocated' attribute is invalid on current operation, skipping it}} declare void @test() preallocated(i32) diff --git a/mlir/test/Target/LLVMIR/Import/instructions.ll b/mlir/test/Target/LLVMIR/Import/instructions.ll index 9b3ad17c31a28..22a274049ecf4 100644 --- a/mlir/test/Target/LLVMIR/Import/instructions.ll +++ b/mlir/test/Target/LLVMIR/Import/instructions.ll @@ -798,6 +798,140 @@ define void @call_modular_format() { ; CHECK: llvm.func @f() declare void @f() +; CHECK-LABEL: @call_nobuiltins_all +define void @call_nobuiltins_all() { +; CHECK: llvm.call @f() {nobuiltins = []} + call void @f() "no-builtins" + ret void +} + +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + +; CHECK-LABEL: @call_nobuiltins_2 +define void @call_nobuiltins_2() { +; CHECK: llvm.call @f() {nobuiltins = ["asdf", "ghij"]} + call void @f() "no-builtin-asdf" "no-builtin-ghij" + ret void +} + + +; // ----- + +; CHECK: llvm.func @f(i32, i32) +declare void @f(i32, i32) + +; CHECK-LABEL: @call_alloc_size_1 +define void @call_alloc_size_1() { +; CHECK: llvm.call @f({{.*}}) {allocsize = array} + call void @f(i32 0, i32 0) allocsize(0) + ret void +} +; // ----- + +; CHECK: llvm.func @f(i32, i32) +declare void @f(i32, i32) + +; CHECK-LABEL: @call_alloc_size_2 +define void @call_alloc_size_2() { +; CHECK: llvm.call @f({{.*}}) {allocsize = array} + call void @f(i32 0, i32 0) allocsize(1, 0) + ret void +} +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + +; CHECK-LABEL: @call_minsize +define void @call_minsize() { +; CHECK: llvm.call @f() {minsize} + call void @f() minsize + ret void +} + +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + +; CHECK-LABEL: @call_optsize +define void @call_optsize() { +; CHECK: llvm.call @f() {optsize} + call void @f() optsize + ret void +} + +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + +; CHECK-LABEL: @call_save_reg_params +define void @call_save_reg_params() { +; CHECK: llvm.call @f() {save_reg_params} + call void @f() "save-reg-params" + ret void +} + +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + +; CHECK-LABEL: @call_zero_call_used_regs +define void @call_zero_call_used_regs() { +; CHECK: llvm.call @f() {zero_call_used_regs = "used"} + call void @f() "zero-call-used-regs"="used" + ret void +} + +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + +; CHECK-LABEL: @call_trap_func_name +define void @call_trap_func_name() { +; CHECK: llvm.call @f() {trap_func_name = "something"} + call void @f() "trap-func-name"="something" + ret void +} + +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + +; Note: the 'default-func-attrs' aren't recoverable due to the way they lower +; to LLVM-IR, and 'call' operations don't have passthrough, so these would be +; lost in translation. +; CHECK-LABEL: @call_default_func_attrs +define void @call_default_func_attrs() { +; CHECK: llvm.call @f() : () -> () + call void @f() "key"="value" "key" + ret void +} + +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + +; CHECK-LABEL: @call_nobuiltin +define void @call_nobuiltin() { +; CHECK: llvm.call @f() {nobuiltin} + call void @f() nobuiltin + ret void +} + +; // ----- + +; CHECK: llvm.func @f() +declare void @f() + ; CHECK-LABEL: @call_memory_effects define void @call_memory_effects() { ; CHECK: llvm.call @f() {memory_effects = #llvm.memory_effects} diff --git a/mlir/test/Target/LLVMIR/fp-math-function-attributes.mlir b/mlir/test/Target/LLVMIR/fp-math-function-attributes.mlir index f76a6cf9d6fa1..19317a16467dd 100644 --- a/mlir/test/Target/LLVMIR/fp-math-function-attributes.mlir +++ b/mlir/test/Target/LLVMIR/fp-math-function-attributes.mlir @@ -1,23 +1,5 @@ // RUN: mlir-translate -mlir-to-llvmir -split-input-file %s | FileCheck %s -// CHECK-LABEL: define void @no_infs_fp_math_func_true() -// CHECK-SAME: #[[ATTRS:[0-9]+]] -llvm.func @no_infs_fp_math_func_true() attributes {no_infs_fp_math = true} { - llvm.return -} -// CHECK: attributes #[[ATTRS]] = { "no-infs-fp-math"="true" } - -// ----- - -// CHECK-LABEL: define void @no_infs_fp_math_func_false() -// CHECK-SAME: #[[ATTRS:[0-9]+]] -llvm.func @no_infs_fp_math_func_false() attributes {no_infs_fp_math = false} { - llvm.return -} -// CHECK: attributes #[[ATTRS]] = { "no-infs-fp-math"="false" } - -// ----- - // CHECK-LABEL: define void @no_nans_fp_math_func_true() // CHECK-SAME: #[[ATTRS:[0-9]+]] llvm.func @no_nans_fp_math_func_true() attributes {no_nans_fp_math = true} { @@ -56,19 +38,37 @@ llvm.func @no_signed_zeros_fp_math_func_false() attributes {no_signed_zeros_fp_m // CHECK-LABEL: define void @denormal_fp_math_func_ieee() // CHECK-SAME: #[[ATTRS:[0-9]+]] -llvm.func @denormal_fp_math_func_ieee() attributes {denormal_fp_math = "ieee"} { +llvm.func @denormal_fp_math_func_ieee() attributes { denormal_fpenv = #llvm.denormal_fpenv} { llvm.return } -// CHECK: attributes #[[ATTRS]] = { "denormal-fp-math"="ieee" } +// CHECK: attributes #[[ATTRS]] = { denormal_fpenv(ieee) } // ----- // CHECK-LABEL: define void @denormal_fp_math_f32_func_preserve_sign() // CHECK-SAME: #[[ATTRS:[0-9]+]] -llvm.func @denormal_fp_math_f32_func_preserve_sign() attributes {denormal_fp_math_f32 = "preserve-sign"} { +llvm.func @denormal_fp_math_f32_func_preserve_sign() attributes {denormal_fpenv = #llvm.denormal_fpenv} { + llvm.return +} +// CHECK: attributes #[[ATTRS]] = { denormal_fpenv(float: preservesign) } + +// ----- + +// CHECK-LABEL: define void @denormal_fp_math_dynamic_f32_func_preserve_sign() +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @denormal_fp_math_dynamic_f32_func_preserve_sign() attributes {denormal_fpenv = #llvm.denormal_fpenv} { + llvm.return +} +// CHECK: attributes #[[ATTRS]] = { denormal_fpenv(dynamic, float: preservesign) } + +// ----- + +// CHECK-LABEL: define void @denormal_fp_math_mixed_modes() +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @denormal_fp_math_mixed_modes() attributes {denormal_fpenv = #llvm.denormal_fpenv} { llvm.return } -// CHECK: attributes #[[ATTRS]] = { "denormal-fp-math-f32"="preserve-sign" } +// CHECK: attributes #[[ATTRS]] = { denormal_fpenv(dynamic|positivezero, float: dynamic|ieee) } // ----- diff --git a/mlir/test/Target/LLVMIR/llvmir.mlir b/mlir/test/Target/LLVMIR/llvmir.mlir index 978199fbfb1a1..4fb5285584a89 100644 --- a/mlir/test/Target/LLVMIR/llvmir.mlir +++ b/mlir/test/Target/LLVMIR/llvmir.mlir @@ -2719,6 +2719,300 @@ llvm.func @modular_format(%arg : i32) attributes { modular_format = "ident,1,1,f // ----- +// CHECK-LABEL: @no_builtins_all +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @no_builtins_all() attributes { nobuiltins = [] } { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: no-builtins + +// ----- + +// CHECK-LABEL: @no_builtins_2 +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @no_builtins_2() attributes { nobuiltins = ["asdf", "defg"] } { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: no-builtin-asdf +// CHECK-SAME: no-builtin-defg + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @no_builtins_call_all +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @no_builtins_call_all() { + llvm.call @f() {nobuiltins = [] } : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: no-builtins + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @no_builtins_call_2 +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @no_builtins_call_2() { + llvm.call @f() {nobuiltins = ["asdf", "defg"] } : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: no-builtin-asdf +// CHECK-SAME: no-builtin-defg + +// ----- + +// CHECK-LABEL: @allocsize_1 +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @allocsize_1(%arg: i32, %arg2: i32) attributes { allocsize = array } { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: allocsize(1) + +// ----- + +// CHECK-LABEL: @allocsize_2 +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @allocsize_2(%arg: i32, %arg2: i32) attributes { allocsize = array } { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: allocsize(0,1) + +// ----- + +llvm.func @f(i32, i32) + +// CHECK-LABEL: @allocsize_call_1 +// CHECK: call void @f({{.*}}) #[[ATTRS:[0-9]+]] +llvm.func @allocsize_call_1() { + %0 = llvm.mlir.constant(0 : i32) : i32 + llvm.call @f(%0, %0) {allocsize = array } : (i32, i32) -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: allocsize(1) + +// ----- + +llvm.func @f(i32, i32) + +// CHECK-LABEL: @allocsize_call_2 +// CHECK: call void @f({{.*}}) #[[ATTRS:[0-9]+]] +llvm.func @allocsize_call_2() { + %0 = llvm.mlir.constant(0 : i32) : i32 + llvm.call @f(%0, %0) {allocsize = array } : (i32, i32) -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: allocsize(1,0) + +// ----- + +// CHECK-LABEL: @minsize +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @minsize() attributes { minsize } { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: minsize + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @minsize_call +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @minsize_call() { + llvm.call @f() {minsize} : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: minsize + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @optsize +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @optsize() attributes { optsize } { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: optsize + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @optsize_call +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @optsize_call() { + llvm.call @f() {optsize} : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: optsize + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @save_reg_params +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @save_reg_params() attributes { save_reg_params } { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "save-reg-params" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @save_reg_params_call +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @save_reg_params_call() { + llvm.call @f() {save_reg_params} : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "save-reg-params" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @zero_call_used_regs_1 +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @zero_call_used_regs_1() attributes { zero_call_used_regs = "skip"} { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "zero-call-used-regs"="skip" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @zero_call_used_regs_2 +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @zero_call_used_regs_2() attributes { zero_call_used_regs = "all"} { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "zero-call-used-regs"="all" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @zero_call_used_regs_call_1 +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @zero_call_used_regs_call_1() { + llvm.call @f() {zero_call_used_regs="used_gpr_all"} : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "zero-call-used-regs"="used_gpr_all" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @zero_call_used_regs_call_2 +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @zero_call_used_regs_call_2() { + llvm.call @f() {zero_call_used_regs="used"} : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "zero-call-used-regs"="used" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @trap_func_name_call +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @trap_func_name_call() { + llvm.call @f() {trap_func_name="whatever"} : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "trap-func-name"="whatever" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @default_func_attrs +// CHECK-SAME: #[[ATTRS:[0-9]+]] +llvm.func @default_func_attrs() attributes {default_func_attrs={key="value", justKey}} { + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "justKey" +// CHECK-SAME: "key"="value" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @default_func_attrs +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @default_func_attrs_call() { + llvm.call @f() {default_func_attrs={key="value", justKey}} : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: "justKey" +// CHECK-SAME: "key"="value" + +// ----- + +llvm.func @f() + +// CHECK-LABEL: @nobuiltin_call +// CHECK: call void @f() #[[ATTRS:[0-9]+]] +llvm.func @nobuiltin_call() { + llvm.call @f() {nobuiltin} : () -> () + llvm.return +} + +// CHECK: #[[ATTRS]] +// CHECK-SAME: nobuiltin + +// ----- + llvm.func @f() // CHECK-LABEL: @convergent_call diff --git a/mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir b/mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir new file mode 100644 index 0000000000000..84b4a0e71c36f --- /dev/null +++ b/mlir/test/Target/LLVMIR/omptarget-teams-distribute-reduction-array-descriptor.mlir @@ -0,0 +1,129 @@ +// RUN: mlir-translate -mlir-to-llvmir -split-input-file %s | FileCheck --check-prefixes=AMDGCN,NVPTX %s + +// Minimal MLIR to exercise array byref reduction descriptor handling in +// target teams distribute parallel do. + +module attributes {dlti.dl_spec = #dlti.dl_spec<"dlti.alloca_memory_space" = 5 : ui64, "dlti.global_memory_space" = 1 : ui64>, llvm.target_triple = "amdgcn-amd-amdhsa", omp.is_gpu = true, omp.is_target_device = true} { + omp.declare_reduction @add_reduction_byref_box_4xi32 : !llvm.ptr attributes {byref_element_type = !llvm.array<4 x i32>} alloc { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> : (i64) -> !llvm.ptr<5> + %2 = llvm.addrspacecast %1 : !llvm.ptr<5> to !llvm.ptr + omp.yield(%2 : !llvm.ptr) + } init { + ^bb0(%arg0: !llvm.ptr, %arg1: !llvm.ptr): + omp.yield(%arg1 : !llvm.ptr) + } combiner { + ^bb0(%arg0: !llvm.ptr, %arg1: !llvm.ptr): + omp.yield(%arg0 : !llvm.ptr) + } data_ptr_ptr { + ^bb0(%arg0: !llvm.ptr): + %0 = llvm.getelementptr %arg0[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> + omp.yield(%0 : !llvm.ptr) + } + + llvm.func @test_array_reduction_() attributes {omp.declare_target = #omp.declaretarget} { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x !llvm.array<4 x i32> : (i64) -> !llvm.ptr<5> + %2 = llvm.addrspacecast %1 : !llvm.ptr<5> to !llvm.ptr + %3 = omp.map.info var_ptr(%2 : !llvm.ptr, !llvm.array<4 x i32>) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "red_array"} + omp.target map_entries(%3 -> %arg0 : !llvm.ptr) { + %4 = llvm.mlir.constant(1 : i32) : i32 + %5 = llvm.mlir.constant(1000 : i32) : i32 + omp.teams reduction(byref @add_reduction_byref_box_4xi32 %arg0 -> %arg1 : !llvm.ptr) { + omp.parallel { + omp.distribute { + omp.wsloop { + omp.loop_nest (%iv) : i32 = (%4) to (%5) inclusive step (%4) { + omp.yield + } + } {omp.composite} + } {omp.composite} + omp.terminator + } {omp.composite} + omp.terminator + } + omp.terminator + } + llvm.return + } +} + +// Verify descriptor is copied via memcpy and base_ptr is updated in all helpers +// AMDGCN-LABEL: define internal void @_omp_reduction_shuffle_and_reduce_func +// AMDGCN: call void @llvm.memcpy{{.*}}(ptr {{.*}}, ptr {{.*}}, i64 {{[0-9]+}}, i1 false) +// AMDGCN: getelementptr {{.*}} ptr {{%.*}}, i32 0, i32 0 +// AMDGCN: store ptr {{%.*}}, ptr + +// AMDGCN-LABEL: define internal void @_omp_reduction_list_to_global_reduce_func +// AMDGCN: call void @llvm.memcpy{{.*}}(ptr {{.*}}, ptr {{.*}}, i64 {{[0-9]+}}, i1 false) +// AMDGCN: getelementptr {{.*}} ptr {{%.*}}, i32 0, i32 0 +// AMDGCN: store ptr {{%.*}}, ptr + +// AMDGCN-LABEL: define internal void @_omp_reduction_global_to_list_copy_func +// AMDGCN: call void @llvm.memcpy{{.*}}(ptr {{.*}}, ptr {{.*}}, i64 {{[0-9]+}}, i1 false) +// AMDGCN: getelementptr {{.*}} ptr {{%.*}}, i32 0, i32 0 +// AMDGCN: store ptr {{%.*}}, ptr + +// ----- + +module attributes {llvm.target_triple = "nvptx64-nvidia-cuda", omp.is_gpu = true, omp.is_target_device = true} { + omp.declare_reduction @add_reduction_byref_box_4xi32 : !llvm.ptr attributes {byref_element_type = !llvm.array<4 x i32>} alloc { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> : (i64) -> !llvm.ptr<5> + %2 = llvm.addrspacecast %1 : !llvm.ptr<5> to !llvm.ptr + omp.yield(%2 : !llvm.ptr) + } init { + ^bb0(%arg0: !llvm.ptr, %arg1: !llvm.ptr): + omp.yield(%arg1 : !llvm.ptr) + } combiner { + ^bb0(%arg0: !llvm.ptr, %arg1: !llvm.ptr): + omp.yield(%arg0 : !llvm.ptr) + } data_ptr_ptr { + ^bb0(%arg0: !llvm.ptr): + %0 = llvm.getelementptr %arg0[0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> + omp.yield(%0 : !llvm.ptr) + } + + llvm.func @test_array_reduction_() attributes {omp.declare_target = #omp.declaretarget} { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x !llvm.array<4 x i32> : (i64) -> !llvm.ptr<5> + %2 = llvm.addrspacecast %1 : !llvm.ptr<5> to !llvm.ptr + %3 = omp.map.info var_ptr(%2 : !llvm.ptr, !llvm.array<4 x i32>) map_clauses(tofrom) capture(ByRef) -> !llvm.ptr {name = "red_array"} + omp.target map_entries(%3 -> %arg0 : !llvm.ptr) { + %4 = llvm.mlir.constant(1 : i32) : i32 + %5 = llvm.mlir.constant(1000 : i32) : i32 + omp.teams reduction(byref @add_reduction_byref_box_4xi32 %arg0 -> %arg1 : !llvm.ptr) { + omp.parallel { + omp.distribute { + omp.wsloop { + omp.loop_nest (%iv) : i32 = (%4) to (%5) inclusive step (%4) { + omp.yield + } + } {omp.composite} + } {omp.composite} + omp.terminator + } {omp.composite} + omp.terminator + } + omp.terminator + } + llvm.return + } +} + +// Verify descriptor is copied via memcpy and base_ptr is updated in all helpers +// NVPTX-LABEL: define internal void @_omp_reduction_shuffle_and_reduce_func +// NVPTX: call void @llvm.memcpy{{.*}}(ptr {{.*}}, ptr {{.*}}, i64 {{[0-9]+}}, i1 false) +// NVPTX: getelementptr {{.*}} ptr {{%.*}}, i32 0, i32 0 +// NVPTX: store ptr {{%.*}}, ptr + +// NVPTX-LABEL: define internal void @_omp_reduction_list_to_global_reduce_func +// NVPTX: call void @llvm.memcpy{{.*}}(ptr {{.*}}, ptr {{.*}}, i64 {{[0-9]+}}, i1 false) +// NVPTX: getelementptr {{.*}} ptr {{%.*}}, i32 0, i32 0 +// NVPTX: store ptr {{%.*}}, ptr + +// NVPTX-LABEL: define internal void @_omp_reduction_global_to_list_copy_func +// NVPTX: call void @llvm.memcpy{{.*}}(ptr {{.*}}, ptr {{.*}}, i64 {{[0-9]+}}, i1 false) +// NVPTX: getelementptr {{.*}} ptr {{%.*}}, i32 0, i32 0 +// NVPTX: store ptr {{%.*}}, ptr + diff --git a/mlir/test/Target/LLVMIR/openmp-simd-guided.mlir b/mlir/test/Target/LLVMIR/openmp-simd-guided.mlir new file mode 100644 index 0000000000000..ac46b4a56ba32 --- /dev/null +++ b/mlir/test/Target/LLVMIR/openmp-simd-guided.mlir @@ -0,0 +1,23 @@ +// Ensure that schedule can be used with the guided kind-type and simd construct +// RUN: mlir-translate -mlir-to-llvmir -split-input-file %s | FileCheck %s + +omp.private {type = private} @_QFEi_private_i32 : i32 +llvm.func @test_simd_guided() { + %0 = llvm.mlir.constant (1 : i64) : i64 + %c1_i32 = llvm.mlir.constant (1 : i32) : i32 + %c64_i32 = llvm.mlir.constant (64 : i32) : i32 + %c0_i32 = llvm.mlir.constant (0 : i32) : i32 + %c4_i32 = llvm.mlir.constant (4 : i32) : i32 + %1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr + omp.wsloop schedule(guided = %c4_i32 : i32, simd) { + omp.simd linear(%1 = %c1_i32 : !llvm.ptr) private(@_QFEi_private_i32 %1 -> %arg0 : !llvm.ptr) { + omp.loop_nest (%arg1) : i32 = (%c0_i32) to (%c64_i32) inclusive step (%c1_i32) { + omp.yield + } + } {linear_var_types = [i32], omp.composite} + } {omp.composite} + llvm.return +} + +// CHECK: %[[omp_global_thread_num:.*]] = call i32 @__kmpc_global_thread_num(ptr @1) +// CHECK: call void @__kmpc_dispatch_init_4u(ptr @1, i32 %[[omp_global_thread_num]], i32 1073741870, i32 1, i32 65, i32 1, i32 4) diff --git a/mlir/test/Target/LLVMIR/openmp-taskloop-collapse.mlir b/mlir/test/Target/LLVMIR/openmp-taskloop-collapse.mlir new file mode 100644 index 0000000000000..f0abff7e38869 --- /dev/null +++ b/mlir/test/Target/LLVMIR/openmp-taskloop-collapse.mlir @@ -0,0 +1,331 @@ +// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s + +omp.private {type = private} @_QFtestEi_private_i32 : i32 + +omp.private {type = firstprivate} @_QFtestEa_firstprivate_i32 : i32 copy { +^bb0(%arg0: !llvm.ptr, %arg1: !llvm.ptr): + %0 = llvm.load %arg0 : !llvm.ptr -> i32 + llvm.store %0, %arg1 : i32, !llvm.ptr + omp.yield(%arg1 : !llvm.ptr) +} + + +llvm.func @_QPtest() { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr + %2 = llvm.alloca %0 x i32 {bindc_name = "j"} : (i64) -> !llvm.ptr + %3 = llvm.alloca %0 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr + %6 = llvm.mlir.constant(20 : i32) : i32 + llvm.store %6, %3 : i32, !llvm.ptr + %c1_i32 = llvm.mlir.constant(1 :i32) : i32 + %c5_i32 = llvm.mlir.constant(5 : i32) : i32 + %c10_i32 = llvm.mlir.constant(10 : i32) : i32 + omp.taskloop private(@_QFtestEa_firstprivate_i32 %3 -> %arg0, @_QFtestEi_private_i32 %1 -> %arg1 : !llvm.ptr, !llvm.ptr) { + omp.loop_nest (%arg2, %arg3) : i32 = (%c1_i32, %c1_i32) to (%c10_i32, %c5_i32) inclusive step (%c1_i32, %c1_i32) collapse(2) { + llvm.store %arg2, %arg1 : i32, !llvm.ptr + %10 = llvm.load %arg0 : !llvm.ptr -> i32 + %11 = llvm.mlir.constant(1 : i32) : i32 + %12 = llvm.add %10, %11 : i32 + llvm.store %12, %arg0 : i32, !llvm.ptr + omp.yield + } + } + llvm.return +} + +// CHECK: %[[structArg:.*]] = alloca { i64, i64, i64, ptr }, align 8 +// CHECK: %[[ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[structArg]], i32 0, i32 1 +// CHECK: store i64 50, ptr %[[ub]], align 4 + +// CHECK: %[[VAL_1:.*]] = load ptr, ptr %0, align 8 +// CHECK: %[[gep_task_lb:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 0 +// CHECK: %[[task_lb:.*]] = load i64, ptr %[[gep_task_lb]], align 4 +// CHECK: %[[gep_task_ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 1 +// CHECK: %[[task_ub:.*]] = load i64, ptr %gep_ub.val, align 4 + +// CHECK: %[[VAL_3:.*]] = sub i64 %[[task_ub]], %[[task_lb]] +// CHECK: %[[VAL_4:.*]] = sdiv i64 %[[VAL_3]], 1 +// CHECK: %[[trip_cnt:.*]] = add i64 %[[VAL_4]], 1 +// CHECK: %[[VAL_6:.*]] = trunc i64 %[[task_lb]] to i32 + +// CHECK: %[[VAL_7:.*]] = sub i32 %[[VAL_6]], 1 +// CHECK: %[[VAL_8:.*]] = add i32 %omp_collapsed.iv, %[[VAL_7]] +// CHECK: %[[VAL_9:.*]] = urem i32 %[[VAL_8]], 5 +// CHECK: %[[VAL_10:.*]] = udiv i32 %[[VAL_8]], 5 +// CHECK: %[[VAL_11:.*]] = mul i32 %[[VAL_10]], 1 +// CHECK: %[[VAL_12:.*]] = add i32 %[[VAL_11]], 1 +// CHECK: %[[VAL_13:.*]] = mul i32 %[[VAL_9]], 1 +// CHECK: %[[VAL_14:.*]] = add i32 %[[VAL_13]], 1 + +// ----- + +llvm.func @_QPtest2() { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr + %2 = llvm.alloca %0 x i32 {bindc_name = "j"} : (i64) -> !llvm.ptr + %3 = llvm.alloca %0 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr + %6 = llvm.mlir.constant(20 : i32) : i32 + llvm.store %6, %3 : i32, !llvm.ptr + %c1_i32 = llvm.mlir.constant(1 :i32) : i32 + %c2_i32 = llvm.mlir.constant(2 : i32) : i32 + %c5_i32 = llvm.mlir.constant(5 : i32) : i32 + %c10_i32 = llvm.mlir.constant(10 : i32) : i32 + omp.taskloop private(@_QFtestEa_firstprivate_i32 %3 -> %arg0, @_QFtestEi_private_i32 %1 -> %arg1 : !llvm.ptr, !llvm.ptr) { + omp.loop_nest (%arg2, %arg3, %arg4) : i32 = (%c1_i32, %c1_i32, %c2_i32) to (%c10_i32, %c5_i32, %c5_i32) inclusive step (%c1_i32, %c1_i32, %c1_i32) collapse(3) { + llvm.store %arg2, %arg1 : i32, !llvm.ptr + %10 = llvm.load %arg0 : !llvm.ptr -> i32 + %11 = llvm.mlir.constant(1 : i32) : i32 + %12 = llvm.add %10, %11 : i32 + llvm.store %12, %arg0 : i32, !llvm.ptr + omp.yield + } + } + llvm.return +} + +// CHECK: %[[structArg:.*]] = alloca { i64, i64, i64, ptr }, align 8 +// CHECK: %[[ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[structArg]], i32 0, i32 1 +// CHECK: store i64 200, ptr %[[ub]], align 4 + +// CHECK: %[[VAL_1:.*]] = load ptr, ptr %0, align 8 +// CHECK: %[[gep_task_lb:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 0 +// CHECK: %[[task_lb:.*]] = load i64, ptr %[[gep_task_lb]], align 4 +// CHECK: %[[gep_task_ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 1 +// CHECK: %[[task_ub:.*]] = load i64, ptr %gep_ub.val, align 4 + +// CHECK: %[[VAL_3:.*]] = sub i64 %[[task_ub]], %[[task_lb]] +// CHECK: %[[VAL_4:.*]] = sdiv i64 %[[VAL_3]], 1 +// CHECK: %[[trip_cnt:.*]] = add i64 %[[VAL_4]], 1 +// CHECK: %[[VAL_6:.*]] = trunc i64 %[[task_lb]] to i32 + +// CHECK: %[[VAL_7:.*]] = sub i32 %[[VAL_6]], 1 +// CHECK: %[[VAL_8:.*]] = add i32 %omp_collapsed.iv, %[[VAL_7]] +// CHECK: %[[VAL_9:.*]] = urem i32 %[[VAL_8]], 4 +// CHECK: %[[VAL_10:.*]] = udiv i32 %[[VAL_8]], 4 +// CHECK: %[[VAL_11:.*]] = urem i32 %[[VAL_10]], 5 +// CHECK: %[[VAL_12:.*]] = udiv i32 %[[VAL_10]], 5 +// CHECK: %[[VAL_13:.*]] = mul i32 %[[VAL_12]], 1 +// CHECK: %[[VAL_14:.*]] = add i32 %[[VAL_13]], 1 +// CHECK: %[[VAL_15:.*]] = mul i32 %[[VAL_11]], 1 +// CHECK: %[[VAL_16:.*]] = add i32 %[[VAL_15]], 1 +// CHECK: %[[VAL_17:.*]] = mul i32 %[[VAL_9]], 1 +// CHECK: %[[VAL_18:.*]] = add i32 %[[VAL_17]], 2 + +// ----- + +llvm.func @_QPtest3() { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr + %2 = llvm.alloca %0 x i32 {bindc_name = "j"} : (i64) -> !llvm.ptr + %3 = llvm.alloca %0 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr + %6 = llvm.mlir.constant(20 : i32) : i32 + llvm.store %6, %3 : i32, !llvm.ptr + %c1_i32 = llvm.mlir.constant(1 :i32) : i32 + %c2_i32 = llvm.mlir.constant(2 : i32) : i32 + %c5_i32 = llvm.mlir.constant(5 : i32) : i32 + %c10_i32 = llvm.mlir.constant(10 : i32) : i32 + %c20_i32 = llvm.mlir.constant(20 : i32) : i32 + omp.taskloop private(@_QFtestEa_firstprivate_i32 %3 -> %arg0, @_QFtestEi_private_i32 %1 -> %arg1 : !llvm.ptr, !llvm.ptr) { + omp.loop_nest (%arg2, %arg3) : i32 = (%c10_i32, %c1_i32) to (%c20_i32, %c5_i32) inclusive step (%c1_i32, %c1_i32) collapse(2) { + llvm.store %arg2, %arg1 : i32, !llvm.ptr + %10 = llvm.load %arg0 : !llvm.ptr -> i32 + %11 = llvm.mlir.constant(1 : i32) : i32 + %12 = llvm.add %10, %11 : i32 + llvm.store %12, %arg0 : i32, !llvm.ptr + omp.yield + } + } + llvm.return +} + +// CHECK: %[[structArg:.*]] = alloca { i64, i64, i64, ptr }, align 8 +// CHECK: %[[ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[structArg]], i32 0, i32 1 +// CHECK: store i64 55, ptr %[[ub]], align 4 + +// CHECK: %[[VAL_1:.*]] = load ptr, ptr %0, align 8 +// CHECK: %[[gep_task_lb:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 0 +// CHECK: %[[task_lb:.*]] = load i64, ptr %[[gep_task_lb]], align 4 +// CHECK: %[[gep_task_ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 1 +// CHECK: %[[task_ub:.*]] = load i64, ptr %[[gep_task_ub]], align 4 + +// CHECK: %[[VAL_3:.*]] = sub i64 %[[task_ub]], %[[task_lb]] +// CHECK: %[[VAL_4:.*]] = sdiv i64 %[[VAL_3]], 1 +// CHECK: %[[trip_cnt:.*]] = add i64 %[[VAL_4]], 1 +// CHECK: %[[VAL_5:.*]] = trunc i64 %[[trip_cnt]] to i32 +// CHECK: %6 = trunc i64 %[[task_lb]] to i32 + +// CHECK: %[[VAL_7:.*]] = sub i32 %[[VAL_6]], 1 +// CHECK: %[[VAL_8:.*]] = add i32 %omp_collapsed.iv, %[[VAL_7]] +// CHECK: %[[VAL_9:.*]] = urem i32 %[[VAL_8]], 5 +// CHECK: %[[VAL_10:.*]] = udiv i32 %[[VAL_8]], 5 + +// CHECK: %[[VAL_11:.*]] = mul i32 %[[VAL_10]], 1 +// CHECK: %[[VAL_12:.*]] = add i32 %[[VAL_11]], 10 + +// CHECK: %[[VAL_13:.*]] = mul i32 %[[VAL_9]], 1 +// CHECK: %[[VAL_14:.*]] = add i32 %[[VAL_13]], 1 + +// ----- + +llvm.func @_QPtest4() { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr + %2 = llvm.alloca %0 x i32 {bindc_name = "j"} : (i64) -> !llvm.ptr + %3 = llvm.alloca %0 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr + %6 = llvm.mlir.constant(20 : i32) : i32 + llvm.store %6, %3 : i32, !llvm.ptr + %c1_i32 = llvm.mlir.constant(1 :i32) : i32 + %c2_i32 = llvm.mlir.constant(2 : i32) : i32 + %c3_i32 = llvm.mlir.constant(3 : i32) : i32 + %c5_i32 = llvm.mlir.constant(5 : i32) : i32 + %c10_i32 = llvm.mlir.constant(10 : i32) : i32 + %c15_i32 = llvm.mlir.constant(15 : i32) : i32 + omp.taskloop private(@_QFtestEa_firstprivate_i32 %3 -> %arg0, @_QFtestEi_private_i32 %1 -> %arg1 : !llvm.ptr, !llvm.ptr) { + omp.loop_nest (%arg2, %arg3) : i32 = (%c2_i32, %c5_i32) to (%c10_i32, %c15_i32) inclusive step (%c2_i32, %c3_i32) collapse(2) { + llvm.store %arg2, %arg1 : i32, !llvm.ptr + %10 = llvm.load %arg0 : !llvm.ptr -> i32 + %11 = llvm.mlir.constant(1 : i32) : i32 + %12 = llvm.add %10, %11 : i32 + llvm.store %12, %arg0 : i32, !llvm.ptr + omp.yield + } + } + llvm.return +} + +// CHECK: %[[structArg:.*]] = alloca { i64, i64, i64, ptr }, align 8 +// CHECK: %[[ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[structArg]], i32 0, i32 1 +// CHECK: store i64 20, ptr %[[ub]], align 4 + +// CHECK: %[[VAL_1:.*]] = load ptr, ptr %0, align 8 +// CHECK: %[[gep_task_lb:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 0 +// CHECK: %[[task_lb:.*]] = load i64, ptr %[[gep_task_lb]], align 4 +// CHECK: %[[gep_task_ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 1 +// CHECK: %[[task_ub:.*]] = load i64, ptr %[[gep_task_ub]], align 4 + +// CHECK: %[[VAL_3:.*]] = sub i64 %[[task_ub]], %[[task_lb]] +// CHECK: %[[VAL_4:.*]] = sdiv i64 %[[VAL_3]], 1 +// CHECK: %[[trip_cnt:.*]] = add i64 %[[VAL_4]], 1 +// CHECK: %[[VAL_5:.*]] = trunc i64 %[[trip_cnt]] to i32 +// CHECK: %6 = trunc i64 %[[task_lb]] to i32 + +// CHECK: %[[VAL_7:.*]] = sub i32 %[[VAL_6]], 1 +// CHECK: %[[VAL_8:.*]] = add i32 %omp_collapsed.iv, %[[VAL_7]] +// CHECK: %[[VAL_9:.*]] = urem i32 %[[VAL_8]], 4 +// CHECK: %[[VAL_10:.*]] = udiv i32 %[[VAL_8]], 4 + +// CHECK: %[[VAL_11:.*]] = mul i32 %[[VAL_10]], 2 +// CHECK: %[[VAL_12:.*]] = add i32 %[[VAL_11]], 2 + +// CHECK: %[[VAL_13:.*]] = mul i32 %[[VAL_9]], 3 +// CHECK: %[[VAL_14:.*]] = add i32 %[[VAL_13]], 5 + + +// ----- + +llvm.func @_QPtest5() { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr + %2 = llvm.alloca %0 x i32 {bindc_name = "j"} : (i64) -> !llvm.ptr + %3 = llvm.alloca %0 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr + %6 = llvm.mlir.constant(20 : i32) : i32 + llvm.store %6, %3 : i32, !llvm.ptr + %cneg2_i32 = llvm.mlir.constant(-2: i32) : i32 + %c1_i32 = llvm.mlir.constant(1 :i32) : i32 + %c2_i32 = llvm.mlir.constant(2 : i32) : i32 + %c3_i32 = llvm.mlir.constant(3 : i32) : i32 + %c5_i32 = llvm.mlir.constant(5 : i32) : i32 + %c10_i32 = llvm.mlir.constant(10 : i32) : i32 + %c15_i32 = llvm.mlir.constant(15 : i32) : i32 + omp.taskloop private(@_QFtestEa_firstprivate_i32 %3 -> %arg0, @_QFtestEi_private_i32 %1 -> %arg1 : !llvm.ptr, !llvm.ptr) { + omp.loop_nest (%arg2, %arg3) : i32 = (%cneg2_i32, %c5_i32) to (%c10_i32, %c15_i32) inclusive step (%c2_i32, %c3_i32) collapse(2) { + llvm.store %arg2, %arg1 : i32, !llvm.ptr + %10 = llvm.load %arg0 : !llvm.ptr -> i32 + %11 = llvm.mlir.constant(1 : i32) : i32 + %12 = llvm.add %10, %11 : i32 + llvm.store %12, %arg0 : i32, !llvm.ptr + omp.yield + } + } + llvm.return +} + +// CHECK: %[[structArg:.*]] = alloca { i64, i64, i64, ptr }, align 8 +// CHECK: %[[ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[structArg]], i32 0, i32 1 +// CHECK: store i64 28, ptr %[[ub]], align 4 + +// CHECK: %[[VAL_1:.*]] = load ptr, ptr %0, align 8 +// CHECK: %[[gep_task_lb:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 0 +// CHECK: %[[task_lb:.*]] = load i64, ptr %[[gep_task_lb]], align 4 +// CHECK: %[[gep_task_ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 1 +// CHECK: %[[task_ub:.*]] = load i64, ptr %[[gep_task_ub]], align 4 + +// CHECK: %[[VAL_3:.*]] = sub i64 %[[task_ub]], %[[task_lb]] +// CHECK: %[[VAL_4:.*]] = sdiv i64 %[[VAL_3]], 1 +// CHECK: %[[trip_cnt:.*]] = add i64 %[[VAL_4]], 1 +// CHECK: %[[VAL_5:.*]] = trunc i64 %[[trip_cnt]] to i32 +// CHECK: %6 = trunc i64 %[[task_lb]] to i32 + +// CHECK: %[[VAL_7:.*]] = sub i32 %[[VAL_6]], 1 +// CHECK: %[[VAL_8:.*]] = add i32 %omp_collapsed.iv, %[[VAL_7]] +// CHECK: %[[VAL_9:.*]] = urem i32 %[[VAL_8]], 4 +// CHECK: %[[VAL_10:.*]] = udiv i32 %[[VAL_8]], 4 + +// CHECK: %[[VAL_11:.*]] = mul i32 %[[VAL_10]], 2 +// CHECK: %[[VAL_12:.*]] = add i32 %[[VAL_11]], -2 + +// CHECK: %[[VAL_13:.*]] = mul i32 %[[VAL_9]], 3 +// CHECK: %[[VAL_14:.*]] = add i32 %[[VAL_13]], 5 + +// ----- + +llvm.func @_QPtest6() { + %0 = llvm.mlir.constant(1 : i64) : i64 + %1 = llvm.alloca %0 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr + %2 = llvm.alloca %0 x i32 {bindc_name = "j"} : (i64) -> !llvm.ptr + %3 = llvm.alloca %0 x i32 {bindc_name = "a"} : (i64) -> !llvm.ptr + %6 = llvm.mlir.constant(20 : i32) : i32 + llvm.store %6, %3 : i32, !llvm.ptr + %cneg1_i32 = llvm.mlir.constant(-1: i32) : i32 + %c1_i32 = llvm.mlir.constant(1 :i32) : i32 + %c5_i32 = llvm.mlir.constant(5 : i32) : i32 + %c10_i32 = llvm.mlir.constant(10 : i32) : i32 + omp.taskloop private(@_QFtestEa_firstprivate_i32 %3 -> %arg0, @_QFtestEi_private_i32 %1 -> %arg1 : !llvm.ptr, !llvm.ptr) { + omp.loop_nest (%arg2, %arg3) : i32 = (%c10_i32, %c1_i32) to (%c5_i32, %c5_i32) inclusive step (%cneg1_i32, %c1_i32) collapse(2) { + llvm.store %arg2, %arg1 : i32, !llvm.ptr + %10 = llvm.load %arg0 : !llvm.ptr -> i32 + %11 = llvm.mlir.constant(1 : i32) : i32 + %12 = llvm.add %10, %11 : i32 + llvm.store %12, %arg0 : i32, !llvm.ptr + omp.yield + } + } + llvm.return +} + +// CHECK: %[[structArg:.*]] = alloca { i64, i64, i64, ptr }, align 8 +// CHECK: %[[ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[structArg]], i32 0, i32 1 +// CHECK: store i64 30, ptr %[[ub]], align 4 + +// CHECK: %[[VAL_1:.*]] = load ptr, ptr %0, align 8 +// CHECK: %[[gep_task_lb:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 0 +// CHECK: %[[task_lb:.*]] = load i64, ptr %[[gep_task_lb]], align 4 +// CHECK: %[[gep_task_ub:.*]] = getelementptr { i64, i64, i64, ptr }, ptr %[[VAL_1]], i32 0, i32 1 +// CHECK: %[[task_ub:.*]] = load i64, ptr %[[gep_task_ub]], align 4 + +// CHECK: %[[VAL_3:.*]] = sub i64 %[[task_ub]], %[[task_lb]] +// CHECK: %[[VAL_4:.*]] = sdiv i64 %[[VAL_3]], 1 +// CHECK: %[[trip_cnt:.*]] = add i64 %[[VAL_4]], 1 +// CHECK: %[[VAL_5:.*]] = trunc i64 %[[trip_cnt]] to i32 +// CHECK: %6 = trunc i64 %[[task_lb]] to i32 + +// CHECK: %[[VAL_7:.*]] = sub i32 %[[VAL_6]], 1 +// CHECK: %[[VAL_8:.*]] = add i32 %omp_collapsed.iv, %[[VAL_7]] +// CHECK: %[[VAL_9:.*]] = urem i32 %[[VAL_8]], 5 +// CHECK: %[[VAL_10:.*]] = udiv i32 %[[VAL_8]], 5 + +// CHECK: %[[VAL_11:.*]] = mul i32 %[[VAL_10]], -1 +// CHECK: %[[VAL_12:.*]] = add i32 %[[VAL_11]], 10 + +// CHECK: %[[VAL_13:.*]] = mul i32 %[[VAL_9]], 1 +// CHECK: %[[VAL_14:.*]] = add i32 %[[VAL_13]], 1 diff --git a/mlir/test/Target/LLVMIR/openmp-todo.mlir b/mlir/test/Target/LLVMIR/openmp-todo.mlir index 36338e5cb1bed..9a10ad74baeb6 100644 --- a/mlir/test/Target/LLVMIR/openmp-todo.mlir +++ b/mlir/test/Target/LLVMIR/openmp-todo.mlir @@ -322,20 +322,6 @@ llvm.func @taskloop_allocate(%lb : i32, %ub : i32, %step : i32, %x : !llvm.ptr) llvm.return } -// ----- - -llvm.func @taskloop_collapse(%lb : i32, %ub : i32, %step : i32, %lb1 : i32, %ub1 : i32, %step1 : i32) { - // expected-error@below {{LLVM Translation failed for operation: omp.taskloop}} - omp.taskloop { - // expected-error@below {{not yet implemented: Unhandled clause collapse in omp.loop_nest operation}} - // expected-error@below {{LLVM Translation failed for operation: omp.loop_nest}} - omp.loop_nest (%iv, %iv1) : i32 = (%lb, %lb1) to (%ub, %ub1) inclusive step (%step, %step1) collapse(2) { - omp.yield - } - } - llvm.return -} - // ----- omp.declare_reduction @add_reduction_i32 : i32 init { ^bb0(%arg0: i32): @@ -487,3 +473,13 @@ llvm.func @wsloop_order(%lb : i32, %ub : i32, %step : i32) { } llvm.return } + +// ----- +llvm.func @task_affinity(%x : !llvm.ptr) { + // expected-error@below {{not yet implemented: Unhandled clause affinity in omp.task operation}} + // expected-error@below {{LLVM Translation failed for operation: omp.task}} + omp.task affinity(%x : !llvm.ptr) { + omp.terminator + } + llvm.return +} diff --git a/mlir/test/Target/LLVMIR/x86vector.mlir b/mlir/test/Target/LLVMIR/x86vector.mlir index 74ae2424964b1..aad4a60720328 100644 --- a/mlir/test/Target/LLVMIR/x86vector.mlir +++ b/mlir/test/Target/LLVMIR/x86vector.mlir @@ -109,6 +109,14 @@ func.func @LLVM_x86_avx512bf16_cvtneps2bf16_512( return %0 : vector<16xbf16> } +// CHECK-LABEL: define <16 x i32> @LLVM_x86_avx10_vpdpbssd_512 +func.func @LLVM_x86_avx10_vpdpbssd_512(%w: vector<16xi32>, %a: vector<64xi8>, + %b: vector<64xi8>) -> vector<16xi32> { + // CHECK: call <16 x i32> @llvm.x86.avx10.vpdpbssd.512( + %0 = x86vector.avx10.dot.i8 %w, %a, %b : vector<64xi8> -> vector<16xi32> + return %0 : vector<16xi32> +} + // CHECK-LABEL: define <4 x float> @LLVM_x86_avxbf16_vcvtneebf162ps128 func.func @LLVM_x86_avxbf16_vcvtneebf162ps128( %a: memref<8xbf16>) -> vector<4xf32> diff --git a/mlir/test/Target/SPIRV/constant.mlir b/mlir/test/Target/SPIRV/constant.mlir index 4838d3c510757..cc7c93824c6e3 100644 --- a/mlir/test/Target/SPIRV/constant.mlir +++ b/mlir/test/Target/SPIRV/constant.mlir @@ -5,8 +5,8 @@ // we cannot use splits. spirv.module Logical Vulkan requires #spirv.vce { + [VulkanMemoryModel, Shader, Int64, Int16, Int8, Float64, Float16, BFloat16TypeKHR, Float8EXT, CooperativeMatrixKHR, Linkage], + [SPV_KHR_vulkan_memory_model, SPV_KHR_cooperative_matrix, SPV_KHR_bfloat16, SPV_EXT_float8]> { // CHECK-LABEL: @bool_const spirv.func @bool_const() -> () "None" { // CHECK: spirv.Constant true @@ -161,6 +161,42 @@ spirv.module Logical Vulkan requires #spirv.vce () "None" { + // CHECK: spirv.Constant 5.120000e+02 : bf16 + %0 = spirv.Constant 512. : bf16 + // CHECK: spirv.Constant -5.120000e+02 : bf16 + %1 = spirv.Constant -512. : bf16 + + %2 = spirv.FConvert %0 : bf16 to f32 + %3 = spirv.FConvert %1 : bf16 to f32 + spirv.Return + } + + // CHECK-LABEL: @f8E4M3FN + spirv.func @f8E4M3FN() -> () "None" { + // CHECK: spirv.Constant 1.280000e+02 : f8E4M3FN + %0 = spirv.Constant 127. : f8E4M3FN + // CHECK: spirv.Constant -1.280000e+02 : f8E4M3FN + %1 = spirv.Constant -127. : f8E4M3FN + + %2 = spirv.FConvert %0 : f8E4M3FN to f32 + %3 = spirv.FConvert %1 : f8E4M3FN to f32 + spirv.Return + } + + // CHECK-LABEL: @f8E5M2 + spirv.func @f8E5M2() -> () "None" { + // CHECK: spirv.Constant 1.280000e+02 : f8E5M2 + %0 = spirv.Constant 127. : f8E5M2 + // CHECK: spirv.Constant -1.280000e+02 : f8E5M2 + %1 = spirv.Constant -127. : f8E5M2 + + %2 = spirv.FConvert %0 : f8E5M2 to f32 + %3 = spirv.FConvert %1 : f8E5M2 to f32 + spirv.Return + } + // CHECK-LABEL: @bool_vector_const spirv.func @bool_vector_const() -> () "None" { // CHECK: spirv.Constant dense : vector<2xi1> diff --git a/mlir/test/Target/SPIRV/tosa-ops.mlir b/mlir/test/Target/SPIRV/tosa-ops.mlir index 1d219b855bec1..9f2ff1c31cbc5 100644 --- a/mlir/test/Target/SPIRV/tosa-ops.mlir +++ b/mlir/test/Target/SPIRV/tosa-ops.mlir @@ -396,3 +396,98 @@ spirv.module Logical Vulkan requires #spirv.vce } } + +// ----- + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Clamp - PRO-INT +//===----------------------------------------------------------------------===// + +// CHECK: spirv.module Logical Vulkan requires #spirv.vce +spirv.module Logical Vulkan requires #spirv.vce { + spirv.GlobalVariable @clamp_int_arg_0 bind(0, 0) : !spirv.ptr, UniformConstant> + spirv.GlobalVariable @clamp_int_res_0 bind(1, 0) : !spirv.ptr, UniformConstant> + spirv.ARM.GraphEntryPoint @clamp_int, @clamp_int_arg_0, @clamp_int_res_0 + spirv.ARM.Graph @clamp_int(%arg0: !spirv.arm.tensor<27x44x55xi8>) -> (!spirv.arm.tensor<27x44x55xi8>) { + // CHECK: {{%.*}} = spirv.Tosa.Clamp min_val = -102 : i8, max_val = -100 : i8, nan_mode = , %arg0 : !spirv.arm.tensor<27x44x55xi8> -> !spirv.arm.tensor<27x44x55xi8> + %3 = spirv.Tosa.Clamp min_val = -102 : i8, max_val = -100 : i8, nan_mode = , %arg0 : !spirv.arm.tensor<27x44x55xi8> -> !spirv.arm.tensor<27x44x55xi8> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<27x44x55xi8> + spirv.ARM.GraphOutputs %3 : !spirv.arm.tensor<27x44x55xi8> + } +} + +// ----- + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Clamp - PRO-FP +//===----------------------------------------------------------------------===// + +// CHECK: spirv.module Logical Vulkan requires #spirv.vce +spirv.module Logical Vulkan requires #spirv.vce { + spirv.GlobalVariable @clamp_fp_arg_0 bind(0, 0) : !spirv.ptr, UniformConstant> + spirv.GlobalVariable @clamp_fp_res_0 bind(1, 0) : !spirv.ptr, UniformConstant> + spirv.ARM.GraphEntryPoint @clamp_fp, @clamp_fp_arg_0, @clamp_fp_res_0 + spirv.ARM.Graph @clamp_fp(%arg0: !spirv.arm.tensor<18x5x17x6xf32>) -> (!spirv.arm.tensor<18x5x17x6xf32>) { + // CHECK: {{%.*}} = spirv.Tosa.Clamp min_val = -1.19339396E+38 : f32, max_val = 2.38255944E+38 : f32, nan_mode = , %arg0 : !spirv.arm.tensor<18x5x17x6xf32> -> !spirv.arm.tensor<18x5x17x6xf32> + %3 = spirv.Tosa.Clamp min_val = -1.19339396E+38 : f32, max_val = 2.38255944E+38 : f32, nan_mode = , %arg0 : !spirv.arm.tensor<18x5x17x6xf32> -> !spirv.arm.tensor<18x5x17x6xf32> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<18x5x17x6xf32> + spirv.ARM.GraphOutputs %3 : !spirv.arm.tensor<18x5x17x6xf32> + } +} + +// ----- + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Erf - PRO-FP +//===----------------------------------------------------------------------===// + +// CHECK: spirv.module Logical Vulkan requires #spirv.vce +spirv.module Logical Vulkan requires #spirv.vce { + spirv.GlobalVariable @erf_fp_arg_0 bind(0, 0) : !spirv.ptr, UniformConstant> + spirv.GlobalVariable @erf_fp_res_0 bind(1, 0) : !spirv.ptr, UniformConstant> + spirv.ARM.GraphEntryPoint @erf_fp, @erf_fp_arg_0, @erf_fp_res_0 + spirv.ARM.Graph @erf_fp(%arg0: !spirv.arm.tensor<47x38x51xf32>) -> (!spirv.arm.tensor<47x38x51xf32>) { + // CHECK: {{%.*}} = spirv.Tosa.Erf %arg0 : !spirv.arm.tensor<47x38x51xf32> -> !spirv.arm.tensor<47x38x51xf32> + %0 = spirv.Tosa.Erf %arg0 : !spirv.arm.tensor<47x38x51xf32> -> !spirv.arm.tensor<47x38x51xf32> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<47x38x51xf32> + spirv.ARM.GraphOutputs %0 : !spirv.arm.tensor<47x38x51xf32> + } +} + +// ----- + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Sigmoid - PRO-FP +//===----------------------------------------------------------------------===// + +// CHECK: spirv.module Logical Vulkan requires #spirv.vce +spirv.module Logical Vulkan requires #spirv.vce { + spirv.GlobalVariable @sigmoid_fp_arg_0 bind(0, 0) : !spirv.ptr, UniformConstant> + spirv.GlobalVariable @sigmoid_fp_res_0 bind(1, 0) : !spirv.ptr, UniformConstant> + spirv.ARM.GraphEntryPoint @sigmoid_fp, @sigmoid_fp_arg_0, @sigmoid_fp_res_0 + spirv.ARM.Graph @sigmoid_fp(%arg0: !spirv.arm.tensor<28x43x45xf32>) -> (!spirv.arm.tensor<28x43x45xf32>) { + // CHECK: {{%.*}} = spirv.Tosa.Sigmoid %arg0 : !spirv.arm.tensor<28x43x45xf32> -> !spirv.arm.tensor<28x43x45xf32> + %0 = spirv.Tosa.Sigmoid %arg0 : !spirv.arm.tensor<28x43x45xf32> -> !spirv.arm.tensor<28x43x45xf32> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<28x43x45xf32> + spirv.ARM.GraphOutputs %0 : !spirv.arm.tensor<28x43x45xf32> + } +} + +// ----- + +//===----------------------------------------------------------------------===// +// spirv.TOSA.Tanh - PRO-FP +//===----------------------------------------------------------------------===// + +// CHECK: spirv.module Logical Vulkan requires #spirv.vce +spirv.module Logical Vulkan requires #spirv.vce { + spirv.GlobalVariable @tanh_fp_arg_0 bind(0, 0) : !spirv.ptr, UniformConstant> + spirv.GlobalVariable @tanh_fp_res_0 bind(1, 0) : !spirv.ptr, UniformConstant> + spirv.ARM.GraphEntryPoint @tanh_fp, @tanh_fp_arg_0, @tanh_fp_res_0 + spirv.ARM.Graph @tanh_fp(%arg0: !spirv.arm.tensor<46x50x36xf16>) -> (!spirv.arm.tensor<46x50x36xf16>) { + // CHECK: {{%.*}} = spirv.Tosa.Tanh %arg0 : !spirv.arm.tensor<46x50x36xf16> -> !spirv.arm.tensor<46x50x36xf16> + %0 = spirv.Tosa.Tanh %arg0 : !spirv.arm.tensor<46x50x36xf16> -> !spirv.arm.tensor<46x50x36xf16> + // CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<46x50x36xf16> + spirv.ARM.GraphOutputs %0 : !spirv.arm.tensor<46x50x36xf16> + } +} diff --git a/mlir/test/Transforms/move-operation-deps.mlir b/mlir/test/Transforms/move-operation-deps.mlir index c6ef358e69822..f8e3430157247 100644 --- a/mlir/test/Transforms/move-operation-deps.mlir +++ b/mlir/test/Transforms/move-operation-deps.mlir @@ -454,24 +454,28 @@ module attributes {transform.with_named_sequence} { // ----- -// Do not move across basic blocks -func.func @no_move_across_basic_blocks() -> (index, index) { - %0 = "unmoved_op"() : () -> (index) - %1 = "before"() : () -> (index) - cf.br ^bb0(%0 : index) - ^bb0(%arg0 : index) : - %2 = arith.addi %arg0, %arg0 {moved_op} : index - return %1, %2 : index, index +// Successfully move operation between blocks in the same region. +// The function argument %arg0 dominates all blocks, so the move is valid. +func.func @move_between_blocks_same_region(%arg0 : index, %cond : i1) -> index { + %0 = "before"() : () -> (index) + cf.cond_br %cond, ^bb1, ^bb2(%arg0 : index) +^bb1: + %1 = arith.addi %arg0, %arg0 {to_move} : index + cf.br ^bb2(%1 : index) +^bb2(%result : index): + return %result : index } +// CHECK-LABEL: func @move_between_blocks_same_region +// CHECK: %[[MOVED:.+]] = arith.addi {{.*}} {to_move} +// CHECK: "before" module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { %op1 = transform.structured.match ops{["before"]} in %arg0 : (!transform.any_op) -> !transform.any_op - %op2 = transform.structured.match ops{["arith.addi"]} in %arg0 + %op2 = transform.structured.match attributes{to_move} in %arg0 : (!transform.any_op) -> !transform.any_op %v1 = transform.get_result %op2[0] : (!transform.any_op) -> !transform.any_value - // expected-remark@+1{{unsupported case of moving definition of value before an insertion point in a different basic block}} transform.test.move_value_defns %v1 before %op1 : (!transform.any_value), !transform.any_op transform.yield @@ -480,22 +484,36 @@ module attributes {transform.with_named_sequence} { // ----- -func.func @move_isolated_from_above(%arg0 : index) -> () { - %1 = "before"() : () -> (index) - %2 = arith.addi %arg0, %arg0 {moved0} : index - %3 = arith.muli %2, %2 {moved1} : index - return + +//===----------------------------------------------------------------------===// +// Cross-region move tests +//===----------------------------------------------------------------------===// + +// Move multiple values with dependencies out of nested region +func.func @move_chain_out_of_region(%arg0 : index, %cond : i1) -> index { + %0 = "before"() : () -> (index) + %1 = scf.if %cond -> index { + %2 = arith.addi %arg0, %arg0 {dep1} : index + %3 = arith.muli %2, %2 {dep2} : index + %4 = arith.subi %3, %arg0 {to_move} : index + scf.yield %4 : index + } else { + scf.yield %arg0 : index + } + return %1 : index } -// CHECK-LABEL: func @move_isolated_from_above( -// CHECK: %[[MOVED0:.+]] = arith.addi {{.*}} {moved0} -// CHECK: %[[MOVED1:.+]] = arith.muli %[[MOVED0]], %[[MOVED0]] {moved1} -// CHECK: %[[BEFORE:.+]] = "before" +// CHECK-LABEL: func @move_chain_out_of_region( +// CHECK: arith.addi {{.*}} {dep1} +// CHECK: arith.muli {{.*}} {dep2} +// CHECK: arith.subi {{.*}} {to_move} +// CHECK: "before" +// CHECK: scf.if module attributes {transform.with_named_sequence} { transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { %op1 = transform.structured.match ops{["before"]} in %arg0 : (!transform.any_op) -> !transform.any_op - %op2 = transform.structured.match ops{["arith.muli"]} in %arg0 + %op2 = transform.structured.match attributes{to_move} in %arg0 : (!transform.any_op) -> !transform.any_op %v1 = transform.get_result %op2[0] : (!transform.any_op) -> !transform.any_value transform.test.move_value_defns %v1 before %op1 @@ -551,3 +569,204 @@ module attributes {transform.with_named_sequence} { transform.yield } } + +// ----- + +// Can move op using outer loop's IV when staying within outer loop +func.func @move_op_using_outer_loop_iv(%lb : index, %ub : index, %step : index) -> index { + %result = scf.for %outer_iv = %lb to %ub step %step iter_args(%acc = %lb) -> index { + %before = "before"() : () -> (index) + scf.for %inner_iv = %lb to %ub step %step { + // Uses outer_iv which dominates within the outer loop body + %x = arith.addi %outer_iv, %outer_iv {to_move} : index + "use"(%x) : (index) -> () + } + scf.yield %acc : index + } + return %result : index +} +// CHECK-LABEL: func @move_op_using_outer_loop_iv( +// CHECK: scf.for %[[OUTER_IV:[a-zA-Z0-9_]+]] = +// CHECK: arith.addi %[[OUTER_IV]], %[[OUTER_IV]] {to_move} +// CHECK: "before" +// CHECK: scf.for + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { + %op1 = transform.structured.match ops{["before"]} in %arg0 + : (!transform.any_op) -> !transform.any_op + %op2 = transform.structured.match attributes{to_move} in %arg0 + : (!transform.any_op) -> !transform.any_op + %v1 = transform.get_result %op2[0] : (!transform.any_op) -> !transform.any_value + transform.test.move_value_defns %v1 before %op1 + : (!transform.any_value), !transform.any_op + transform.yield + } +} + +// ----- + +// Move out of doubly nested non-isolated region +func.func @move_out_of_doubly_nested_region(%arg0 : index, %cond1 : i1, %cond2 : i1) -> index { + %0 = "before"() : () -> (index) + %1 = scf.if %cond1 -> index { + %2 = scf.if %cond2 -> index { + %3 = arith.addi %arg0, %arg0 {to_move} : index + scf.yield %3 : index + } else { + scf.yield %arg0 : index + } + scf.yield %2 : index + } else { + scf.yield %arg0 : index + } + return %1 : index +} +// CHECK-LABEL: func @move_out_of_doubly_nested_region( +// CHECK: %[[MOVED:.+]] = arith.addi {{.*}} {to_move} +// CHECK: %[[BEFORE:.+]] = "before" +// CHECK: scf.if +// CHECK: scf.if +// CHECK: scf.yield %[[MOVED]] + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { + %op1 = transform.structured.match ops{["before"]} in %arg0 + : (!transform.any_op) -> !transform.any_op + %op2 = transform.structured.match attributes{to_move} in %arg0 + : (!transform.any_op) -> !transform.any_op + %v1 = transform.get_result %op2[0] : (!transform.any_op) -> !transform.any_value + transform.test.move_value_defns %v1 before %op1 + : (!transform.any_value), !transform.any_op + transform.yield + } +} + +// ----- + +// Move operand deps out of nested region +func.func @move_operand_deps_out_of_region(%arg0 : index, %cond : i1) -> index { + %0 = "before"() : () -> (index) + %1 = scf.if %cond -> index { + %2 = arith.addi %arg0, %arg0 {dep} : index + %3 = "foo"(%2) {target} : (index) -> (index) + scf.yield %3 : index + } else { + scf.yield %arg0 : index + } + return %1 : index +} +// CHECK-LABEL: func @move_operand_deps_out_of_region( +// CHECK: %[[DEP:.+]] = arith.addi {{.*}} {dep} +// CHECK: %[[BEFORE:.+]] = "before" +// CHECK: scf.if +// CHECK: "foo"(%[[DEP]]) {target} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { + %op1 = transform.structured.match ops{["foo"]} in %arg0 + : (!transform.any_op) -> !transform.any_op + %op2 = transform.structured.match ops{["before"]} in %arg0 + : (!transform.any_op) -> !transform.any_op + transform.test.move_operand_deps %op1 before %op2 + : !transform.any_op, !transform.any_op + transform.yield + } +} + +// ----- + +// Cannot move op that depends on loop induction variable (block argument) +func.func @cannot_move_op_using_loop_iv(%arg0 : index, %lb : index, %ub : index, %step : index) -> index { + %0 = "before"() : () -> (index) + %1 = scf.for %iv = %lb to %ub step %step iter_args(%acc = %arg0) -> index { + %2 = arith.addi %iv, %iv {to_move} : index + %3 = arith.addi %acc, %2 : index + scf.yield %3 : index + } + return %1 : index +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { + %op1 = transform.structured.match ops{["before"]} in %arg0 + : (!transform.any_op) -> !transform.any_op + %op2 = transform.structured.match attributes{to_move} in %arg0 + : (!transform.any_op) -> !transform.any_op + %v1 = transform.get_result %op2[0] : (!transform.any_op) -> !transform.any_value + // expected-remark@+1{{moving op would break dominance for block argument operand}} + transform.test.move_value_defns %v1 before %op1 + : (!transform.any_value), !transform.any_op + transform.yield + } +} + +// ----- + +// Cannot move out of an isolated-from-above region, even when op is in a +// non-isolated region nested inside the isolated region +func.func @cannot_move_out_of_isolated_region(%arg0 : index, %cond : i1) -> index { + %0 = "before"() : () -> (index) + %1 = "test.isolated_one_region_op"(%arg0, %cond) ({ + ^bb0(%inner_arg: index, %inner_cond: i1): + // scf.if is NOT isolated, but it's inside an isolated region + %2 = scf.if %inner_cond -> index { + %3 = arith.addi %inner_arg, %inner_arg {to_move} : index + scf.yield %3 : index + } else { + scf.yield %inner_arg : index + } + "test.region_yield"(%2) : (index) -> () + }) : (index, i1) -> (index) + return %1 : index +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { + %op1 = transform.structured.match ops{["before"]} in %arg0 + : (!transform.any_op) -> !transform.any_op + %op2 = transform.structured.match attributes{to_move} in %arg0 + : (!transform.any_op) -> !transform.any_op + %v1 = transform.get_result %op2[0] : (!transform.any_op) -> !transform.any_value + // expected-remark@+1{{cannot move value definition across isolated-from-above region}} + transform.test.move_value_defns %v1 before %op1 + : (!transform.any_value), !transform.any_op + transform.yield + } +} + +// ----- + +// Fail when trying to move an operation whose region captures a block argument +// that wouldn't dominate at the insertion point. +func.func @captured_block_arg_does_not_dominate(%arg0 : f32, %cond : i1) -> f32 { + %0 = arith.addf %arg0, %arg0 {before} : f32 + cf.br ^bb1(%0 : f32) +^bb1(%bbArg : f32): + // scf.if will be part of the slice that needs to move. + // It has a region that captures %bbArg from bb1. + // Moving it before the {before} op in the entry block would be invalid + // because %bbArg (a block argument of bb1) doesn't dominate the entry block. + %1 = scf.if %cond -> f32 { + %inner = arith.addf %bbArg, %bbArg : f32 + scf.yield %inner : f32 + } else { + scf.yield %bbArg : f32 + } + %2 = arith.mulf %1, %1 {target} : f32 + return %2 : f32 +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg0 : !transform.any_op {transform.readonly}) { + %op1 = transform.structured.match attributes{before} in %arg0 + : (!transform.any_op) -> !transform.any_op + %op2 = transform.structured.match attributes{target} in %arg0 + : (!transform.any_op) -> !transform.any_op + %v1 = transform.get_result %op2[0] : (!transform.any_op) -> !transform.any_value + // expected-remark@+1{{moving op would break dominance for block argument operand}} + transform.test.move_value_defns %v1 before %op1 + : (!transform.any_value), !transform.any_op + transform.yield + } +} diff --git a/mlir/test/lib/Dialect/SPIRV/TestEntryPointAbi.cpp b/mlir/test/lib/Dialect/SPIRV/TestEntryPointAbi.cpp index 0e8dfb8e3ee9a..f492d7cd87d83 100644 --- a/mlir/test/lib/Dialect/SPIRV/TestEntryPointAbi.cpp +++ b/mlir/test/lib/Dialect/SPIRV/TestEntryPointAbi.cpp @@ -1,4 +1,4 @@ -//===- TestAvailability.cpp - Test pass for setting Entry point ABI info --===// +//===- TestEntryPointAbi.cpp - Test pass for setting Entry point ABI info -===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/mlir/test/lib/Dialect/Test/TestTypeDefs.td b/mlir/test/lib/Dialect/Test/TestTypeDefs.td index d840339a09266..964792ceebc07 100644 --- a/mlir/test/lib/Dialect/Test/TestTypeDefs.td +++ b/mlir/test/lib/Dialect/Test/TestTypeDefs.td @@ -406,6 +406,36 @@ def TestTypeVerification : Test_Type<"TestTypeVerification"> { let assemblyFormat = "`<` $param `>`"; } +// Test type with PredTypeTrait - single parameter predicate. +def TestTypePredTrait : Test_Type<"TestTypePredTrait", + [PredTypeTrait<"value must be positive", CPred<"$value > 0">>]> { + let parameters = (ins "unsigned":$value); + let mnemonic = "type_pred_trait"; + let assemblyFormat = "`<` $value `>`"; +} + +// Test type with PredTypeTrait - two parameter predicate. +def TestTypePredTraitMultiParam : Test_Type<"TestTypePredTraitMultiParam", + [PredTypeTrait<"value must be at least min", + CPred<"$value >= $minValue">>]> { + let parameters = (ins "unsigned":$value, "unsigned":$minValue); + let mnemonic = "type_pred_trait_multi"; + let assemblyFormat = "`<` $value `,` $minValue `>`"; +} + +// Test type combining parameter type constraints with PredTypeTrait. +def TestTypePredTraitCombined : Test_Type<"TestTypePredTraitCombined", + [PredTypeTrait<"count must match number of elements", + CPred<"$count == $elements.size()">>]> { + let parameters = (ins + "unsigned":$count, + ArrayRefParameter<"int64_t">:$elements, + AnyTypeOf<[I16, I32]>:$elementType + ); + let mnemonic = "type_pred_trait_combined"; + let assemblyFormat = "`<` $count `,` `[` $elements `]` `,` $elementType `>`"; +} + def TestTypeOpAsmTypeInterface : Test_Type<"TestTypeOpAsmTypeInterface", [DeclareTypeInterfaceMethods]> { let mnemonic = "op_asm_type_interface"; diff --git a/mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp b/mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp index 405e974500e08..20bcb24a301e6 100644 --- a/mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp +++ b/mlir/test/lib/Dialect/XeGPU/TestXeGPUTransforms.cpp @@ -14,6 +14,7 @@ #include "mlir/Dialect/Vector/Transforms/VectorTransforms.h" #include "mlir/Dialect/XeGPU/IR/XeGPU.h" #include "mlir/Dialect/XeGPU/Transforms/Transforms.h" +#include "mlir/Dialect/XeGPU/Transforms/XeGPULayoutImpl.h" #include "mlir/Dialect/XeGPU/Utils/XeGPUUtils.h" #include "mlir/IR/BuiltinTypes.h" #include "mlir/IR/Value.h" diff --git a/mlir/test/lib/IR/TestSymbolUses.cpp b/mlir/test/lib/IR/TestSymbolUses.cpp index e841e142c6563..24f7d8505bebd 100644 --- a/mlir/test/lib/IR/TestSymbolUses.cpp +++ b/mlir/test/lib/IR/TestSymbolUses.cpp @@ -60,6 +60,10 @@ struct SymbolUsesPass symbolUse.getUser()->emitRemark() << "found use of symbol : " << symbolUse.getSymbolRef() << " : " << symbol.getNameAttr(); + } else { + symbolUse.getUser()->emitRemark() + << "failed to resolve use of symbol : " << symbolUse.getSymbolRef() + << " : " << symbol.getNameAttr(); } } symbol->emitRemark() << "symbol has " << llvm::size(*symbolUses) << " uses"; diff --git a/mlir/test/lib/Rewrite/TestPDLByteCode.cpp b/mlir/test/lib/Rewrite/TestPDLByteCode.cpp index e5783c96f44e4..1e3d0186eb1c9 100644 --- a/mlir/test/lib/Rewrite/TestPDLByteCode.cpp +++ b/mlir/test/lib/Rewrite/TestPDLByteCode.cpp @@ -81,6 +81,19 @@ static LogicalResult customTypeRangeResultConstraint(PatternRewriter &rewriter, return failure(); } +// Custom constraint that returns a value range if the op is named +// test.success_op +static LogicalResult customValueRangeResultConstraint(PatternRewriter &rewriter, + PDLResultList &results, + ArrayRef args) { + auto *op = args[0].cast(); + if (op->getName().getStringRef() == "test.success_op") { + results.push_back(op->getOperands()); // Returns ValueRange + return success(); + } + return failure(); +} + // Custom creator invoked from PDL. static Operation *customCreate(PatternRewriter &rewriter, Operation *op) { return rewriter.create(OperationState(op->getLoc(), "test.success")); @@ -161,6 +174,8 @@ struct TestPDLByteCodePass customConstraintFailure); pdlPattern.registerConstraintFunction("op_constr_return_type_range", customTypeRangeResultConstraint); + pdlPattern.registerConstraintFunction("op_constr_return_value_range", + customValueRangeResultConstraint); pdlPattern.registerRewriteFunction("creator", customCreate); pdlPattern.registerRewriteFunction("var_creator", customVariadicResultCreate); diff --git a/mlir/test/python/dialects/ext.py b/mlir/test/python/dialects/ext.py index 483953ddfde51..d24a94bc8baf8 100644 --- a/mlir/test/python/dialects/ext.py +++ b/mlir/test/python/dialects/ext.py @@ -76,6 +76,8 @@ class AddOp(MyInt.Operation, name="add"): print(add1._ODS_OPERAND_SEGMENTS) # CHECK: None print(add1._ODS_RESULT_SEGMENTS) + # CHECK: (0, True) + print(add1._ODS_REGIONS) # CHECK: %0 = "myint.constant"() {value = 2 : i32} : () -> i32 print(add1.lhs.owner) # CHECK: %1 = "myint.constant"() {value = 3 : i32} : () -> i32 @@ -338,3 +340,152 @@ class TypeVarOp(Test.Operation, name="type_var"): except TypeError as e: # CHECK：too many positional arguments print(e) + + +# CHECK: TEST: testExtDialectWithRegion +@run +def testExtDialectWithRegion(): + class TestRegion(Dialect, name="ext_region"): + pass + + class IfOp(TestRegion.Operation, name="if"): + cond: Operand[IntegerType[1]] + result: Result[Any] + then: Region + else_: Region + + class YieldOp(TestRegion.Operation, name="yield"): + value: Operand[Any] + + class NoTermOp(TestRegion.Operation, name="no_term"): + body: Region + + with Context(), Location.unknown(): + TestRegion.load() + # CHECK: irdl.dialect @ext_region { + # CHECK: irdl.operation @if { + # CHECK: %0 = irdl.is i1 + # CHECK: irdl.operands(cond: %0) + # CHECK: %1 = irdl.any + # CHECK: irdl.results(result: %1) + # CHECK: %2 = irdl.region + # CHECK: %3 = irdl.region + # CHECK: irdl.regions(then: %2, else_: %3) + # CHECK: } + # CHECK: irdl.operation @yield { + # CHECK: %0 = irdl.any + # CHECK: irdl.operands(value: %0) + # CHECK: } + # CHECK: irdl.operation @no_term { + # CHECK: %0 = irdl.region + # CHECK: irdl.regions(body: %0) + # CHECK: } + # CHECK: } + print(TestRegion._mlir_module) + + IsTerminatorTrait.attach(YieldOp) + NoTerminatorTrait.attach(NoTermOp) + + class ParentIsIfTrait(DynamicOpTrait): + @staticmethod + def verify(op) -> bool: + if not isinstance(op.parent.opview, IfOp): + op.location.emit_error( + f"{op.name} should be put inside {IfOp.OPERATION_NAME}" + ) + return False + return True + + ParentIsIfTrait.attach(YieldOp) + + # CHECK: (self, /, result, cond, *, loc=None, ip=None) + print(IfOp.__init__.__signature__) + + # CHECK: None None + print(IfOp._ODS_OPERAND_SEGMENTS, IfOp._ODS_RESULT_SEGMENTS) + # CHECK: (2, True) + print(IfOp._ODS_REGIONS) + + module = Module.create() + with InsertionPoint(module.body): + i1 = IntegerType.get_signless(1) + i32 = IntegerType.get_signless(32) + cond = arith.constant(i1, 1) + + if_ = IfOp(i32, cond) + if_.then.blocks.append() + if_.else_.blocks.append() + + with InsertionPoint(if_.then.blocks[0]): + v = arith.constant(i32, 2) + YieldOp(v) + + with InsertionPoint(if_.else_.blocks[0]): + v = arith.constant(i32, 3) + YieldOp(v) + + nt = NoTermOp() + nt.body.blocks.append() + + with InsertionPoint(nt.body.blocks[0]): + arith.constant(i32, 4) + # No terminator here + + assert module.operation.verify() + # CHECK: module { + # CHECK: %true = arith.constant true + # CHECK: %0 = "ext_region.if"(%true) ({ + # CHECK: %c2_i32 = arith.constant 2 : i32 + # CHECK: "ext_region.yield"(%c2_i32) : (i32) -> () + # CHECK: }, { + # CHECK: %c3_i32 = arith.constant 3 : i32 + # CHECK: "ext_region.yield"(%c3_i32) : (i32) -> () + # CHECK: }) : (i1) -> i32 + # CHECK: "ext_region.no_term"() ({ + # CHECK: %c4_i32 = arith.constant 4 : i32 + # CHECK: }) : () -> () + # CHECK: } + print(module) + + # CHECK: %c2_i32 = arith.constant 2 : i32 + print(if_.then.blocks[0]) + # CHECK: %c3_i32 = arith.constant 3 : i32 + print(if_.else_.blocks[0]) + + # CHECK-LABEL: Testing violation cases + print("Testing violation cases:") + + module = Module.create() + with InsertionPoint(module.body): + i1 = IntegerType.get_signless(1) + i32 = IntegerType.get_signless(32) + cond = arith.constant(i1, 1) + + if_ = IfOp(i32, cond) + if_.then.blocks.append() + if_.else_.blocks.append() + + with InsertionPoint(if_.then.blocks[0]): + v = arith.constant(i32, 2) + + with InsertionPoint(if_.else_.blocks[0]): + v = arith.constant(i32, 3) + + try: + module.operation.verify() + except Exception as e: + # CHECK: Verification failed: + # CHECK: block with no terminator + print(e) + + module = Module.create() + with InsertionPoint(module.body): + v = arith.constant(i32, 2) + YieldOp(v) + + try: + module.operation.verify() + except Exception as e: + # CHECK: Verification failed: + # CHECK: ext_region.yield should be put inside ext_region.if + print(e) diff --git a/mlir/test/python/dialects/transform_vector_ext.py b/mlir/test/python/dialects/transform_vector_ext.py index 0cd9333dc1218..2bcb2a2ac5812 100644 --- a/mlir/test/python/dialects/transform_vector_ext.py +++ b/mlir/test/python/dialects/transform_vector_ext.py @@ -67,6 +67,9 @@ def configurable_patterns(): # CHECK-SAME: max_transfer_rank = 3 # CHECK-SAME: full_unroll = true vector.ApplyTransferToScfPatternsOp(max_transfer_rank=3, full_unroll=True) + # CHECK: transform.apply_patterns.vector.flatten_vector_transfer_ops + # CHECK-SAME: target_vector_bitwidth = 1 + vector.ApplyFlattenVectorTransferOpsPatternsOp(target_vector_bitwidth=1) @run_apply_patterns diff --git a/mlir/test/python/dialects/transform_x86vector_ext.py b/mlir/test/python/dialects/transform_x86vector_ext.py new file mode 100644 index 0000000000000..ad8dab8175ef2 --- /dev/null +++ b/mlir/test/python/dialects/transform_x86vector_ext.py @@ -0,0 +1,40 @@ +# RUN: %PYTHON %s | FileCheck %s + +from mlir.ir import * +from mlir.dialects import transform +from mlir.dialects.transform import x86vector + + +def run_apply_patterns(f): + with Context(), Location.unknown(): + module = Module.create() + with InsertionPoint(module.body): + sequence = transform.SequenceOp( + transform.FailurePropagationMode.Propagate, + [], + transform.AnyOpType.get(), + ) + with InsertionPoint(sequence.body): + apply = transform.ApplyPatternsOp(sequence.bodyTarget) + with InsertionPoint(apply.patterns): + f() + transform.YieldOp() + print("\nTEST:", f.__name__) + print(module) + return f + + +@run_apply_patterns +def non_configurable_patterns(): + # CHECK-LABEL: TEST: non_configurable_patterns + # CHECK: apply_patterns + # CHECK: transform.apply_patterns.x86vector.vector_contract_to_fma + x86vector.ApplyVectorContractToFMAPatternsOp() + # CHECK: transform.apply_patterns.x86vector.vector_contract_to_packed_type_dot_product + x86vector.ApplyVectorContractToPackedTypeDotProductPatternsOp() + # CHECK: transform.apply_patterns.x86vector.vector_contract_bf16_to_fma + x86vector.ApplyVectorContractBF16ToFMAPatternsOp() + # CHECK: transform.apply_patterns.x86vector.sink_vector_producer_ops + x86vector.ApplySinkVectorProducerOpsPatternsOp() + # CHECK: transform.apply_patterns.x86vector.shuffle_vector_fma_ops + x86vector.ApplyShuffleVectorFMAOpsPatternsOp() diff --git a/mlir/test/python/dialects/x86vector.py b/mlir/test/python/dialects/x86vector.py new file mode 100644 index 0000000000000..c270727078a20 --- /dev/null +++ b/mlir/test/python/dialects/x86vector.py @@ -0,0 +1,76 @@ +# RUN: %PYTHON %s | FileCheck %s + +from mlir.ir import * +import mlir.dialects.builtin as builtin +import mlir.dialects.func as func +import mlir.dialects.x86vector as x86vector + + +def run(f): + print("\nTEST:", f.__name__) + with Context(), Location.unknown(): + f() + return f + + +# CHECK-LABEL: TEST: testAvxOp +@run +def testAvxOp(): + module = Module.create() + with InsertionPoint(module.body): + + @func.FuncOp.from_py_func(MemRefType.get((1,), BF16Type.get())) + def avx_op(arg): + return x86vector.BcstToPackedF32Op( + a=arg, dst=VectorType.get((8,), F32Type.get()) + ) + + # CHECK-LABEL: func @avx_op( + # CHECK-SAME: %[[ARG:.+]]: memref<1xbf16>) -> vector<8xf32> { + # CHECK: %[[VAL:.+]] = x86vector.avx.bcst_to_f32.packed %[[ARG]] + # CHECK: return %[[VAL]] : vector<8xf32> + # CHECK: } + print(module) + + +# CHECK-LABEL: TEST: testAvx512Op +@run +def testAvx512Op(): + module = Module.create() + with InsertionPoint(module.body): + + @func.FuncOp.from_py_func(VectorType.get((8,), F32Type.get())) + def avx512_op(arg): + return x86vector.CvtPackedF32ToBF16Op( + a=arg, dst=VectorType.get((8,), BF16Type.get()) + ) + + # CHECK-LABEL: func @avx512_op( + # CHECK-SAME: %[[ARG:.+]]: vector<8xf32>) -> vector<8xbf16> { + # CHECK: %[[VAL:.+]] = x86vector.avx512.cvt.packed.f32_to_bf16 %[[ARG]] + # CHECK: return %[[VAL]] : vector<8xbf16> + # CHECK: } + print(module) + + +# CHECK-LABEL: TEST: testAvx10Op +@run +def testAvx10Op(): + module = Module.create() + with InsertionPoint(module.body): + + @func.FuncOp.from_py_func( + VectorType.get((16,), IntegerType.get(32)), + VectorType.get((64,), IntegerType.get(8)), + VectorType.get((64,), IntegerType.get(8)), + ) + def avx10_op(*args): + return x86vector.AVX10DotInt8Op(w=args[0], a=args[1], b=args[2]) + + # CHECK-LABEL: func @avx10_op( + # CHECK-SAME: %[[W:.+]]: vector<16xi32>, %[[A:.+]]: vector<64xi8>, + # CHECK-SAME: %[[B:.+]]: vector<64xi8>) -> vector<16xi32> { + # CHECK: %[[VAL:.+]] = x86vector.avx10.dot.i8 %[[W]], %[[A]], %[[B]] + # CHECK: return %[[VAL]] : vector<16xi32> + # CHECK: } + print(module) diff --git a/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp b/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp index 80c523f793594..031e03071842f 100644 --- a/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp +++ b/mlir/tools/mlir-tblgen/AttrOrTypeDefGen.cpp @@ -246,12 +246,16 @@ void DefGen::createParentWithTraits() { ? strfmt("{0}::{1}", def.getStorageNamespace(), def.getStorageClassName()) : strfmt("::mlir::{0}Storage", valueType)); - SmallVector traitNames = - llvm::map_to_vector(def.getTraits(), [](auto &trait) { - return isa(&trait) - ? cast(&trait)->getFullyQualifiedTraitName() - : cast(&trait)->getFullyQualifiedTraitName(); - }); + SmallVector traitNames; + for (auto &trait : def.getTraits()) { + // Skip PredTrait as it doesn't generate a C++ trait class. + if (isa(&trait)) + continue; + traitNames.push_back( + isa(&trait) + ? cast(&trait)->getFullyQualifiedTraitName() + : cast(&trait)->getFullyQualifiedTraitName()); + } for (auto &traitName : traitNames) defParent.addTemplateParam(traitName); @@ -386,6 +390,26 @@ void DefGen::emitInvariantsVerifierImpl() { param.getName(), constraint->getSummary()) << "\n"; } + { + // Generate verification for PredTraits. + FmtContext traitCtx; + for (auto it : llvm::enumerate(def.getParameters())) { + // Note: Skip over the first method parameter (`emitError`). + traitCtx.addSubst(it.value().getName(), + builderParams[it.index() + 1].getName()); + } + for (const Trait &trait : def.getTraits()) { + if (auto *t = dyn_cast(&trait)) { + verifier->body() << tgfmt( + "if (!($0)) {\n" + " emitError() << \"failed to verify that $1\";\n" + " return ::mlir::failure();\n" + "}\n", + &traitCtx, tgfmt(t->getPredTemplate(), &traitCtx), t->getSummary()); + } + } + } + verifier->body() << "return ::mlir::success();"; } diff --git a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp index 9cb48934b2c10..34edd4df49d8e 100644 --- a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp +++ b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp @@ -558,9 +558,10 @@ static void emitAttributeSerialization(const Attribute &attr, os << tabs << " return failure();\n"; os << tabs << " }\n"; os << tabs << formatv(" {0}.push_back(attrTypeID);\n", operandList); - } else if (llvm::is_contained( - {"SPIRV_BoolConstAttr", "SPIRV_TensorArmAxisAttr"}, - attr.getAttrDefName())) { + } else if (llvm::is_contained({"SPIRV_BoolConstAttr", + "SPIRV_TensorArmAxisAttr", + "SPIRV_TosaNumericalAttr"}, + attr.getAttrDefName())) { os << tabs << formatv( " {0}.push_back(prepareConstantScalar({1}.getLoc(), attr));\n", @@ -864,7 +865,9 @@ static void emitAttributeDeserialization(const Attribute &attr, << formatv("{0}.push_back(opBuilder.getNamedAttr(\"{1}\", " "TypeAttr::get(getType({2}[{3}++]))));\n", attrList, attrName, words, wordIndex); - } else if (attr.getAttrDefName() == "SPIRV_BoolConstAttr" || + } else if (llvm::is_contained( + {"SPIRV_BoolConstAttr", "SPIRV_TosaNumericalAttr"}, + attr.getAttrDefName()) || attr.getAttrDefName().contains("TensorArm")) { os << tabs << formatv("std::optional> c = " diff --git a/mlir/unittests/IR/RemarkTest.cpp b/mlir/unittests/IR/RemarkTest.cpp index dca86632071d4..df8e8c8cc066b 100644 --- a/mlir/unittests/IR/RemarkTest.cpp +++ b/mlir/unittests/IR/RemarkTest.cpp @@ -409,4 +409,83 @@ TEST(Remark, TestArgWithAttribute) { EXPECT_FALSE(argWithoutAttr.getAttribute()); // Returns null Attribute EXPECT_EQ(argWithoutAttr.val, "Value"); } + +// Test that Remark correctly owns its string data and doesn't have +// use-after-free issues when the original strings go out of scope. +// This is particularly important for RemarkEmittingPolicyFinal which +// stores remarks and emits them later during finalize(). +TEST(Remark, TestRemarkOwnsStringData) { + testing::internal::CaptureStderr(); + + // These are the expected values we'll check for in the output. + // They must match what we create in the inner scope below. + const char *expectedCategory = "DynamicCategory"; + const char *expectedName = "DynamicRemarkName"; + const char *expectedFunction = "dynamicFunction"; + const char *expectedMessage = "Dynamic message content"; + + { + MLIRContext context; + Location loc = FileLineColLoc::get(&context, "test.cpp", 42, 10); + + // Setup with RemarkEmittingPolicyFinal - this stores remarks and emits + // them only when the engine is destroyed (during finalize). + // Note: The 'passed' filter must be set for remark::passed() to emit. + mlir::remark::RemarkCategories cats{ + /*all=*/std::nullopt, + /*passed=*/expectedCategory, // Enable passed remarks for this category + /*missed=*/std::nullopt, + /*analysis=*/std::nullopt, + /*failed=*/std::nullopt}; + + std::unique_ptr policy = + std::make_unique(); + LogicalResult isEnabled = remark::enableOptimizationRemarks( + context, std::make_unique(), std::move(policy), cats, + /*printAsEmitRemarks=*/true); + ASSERT_TRUE(succeeded(isEnabled)) << "Failed to enable remark engine"; + + // Create dynamic strings in an inner scope that will go out of scope + // BEFORE the RemarkEngine is destroyed and finalize() is called. + { + std::string dynamicCategory(expectedCategory); + std::string dynamicName(expectedName); + std::string dynamicFunction(expectedFunction); + std::string dynamicSubCategory("DynamicSubCategory"); + std::string dynamicMessage(expectedMessage); + + // Emit a remark with all dynamic strings + remark::passed(loc, remark::RemarkOpts::name(dynamicName) + .category(dynamicCategory) + .subCategory(dynamicSubCategory) + .function(dynamicFunction)) + << dynamicMessage; + + // dynamicCategory, dynamicName, dynamicFunction, dynamicSubCategory, + // and dynamicMessage all go out of scope here! + } + + // At this point, all the dynamic strings have been destroyed. + // The Remark stored in RemarkEmittingPolicyFinal must have its own + // copies of the string data, otherwise we'd have dangling pointers. + + // Context destruction triggers RemarkEngine destruction, which calls + // finalize() on the policy, which then emits the stored remarks. + // If Remark doesn't own its strings, this would crash or produce garbage. + } + + llvm::errs().flush(); + std::string errOut = ::testing::internal::GetCapturedStderr(); + + // Verify the output contains our expected strings - this proves the + // Remark correctly copied and owns the string data. + EXPECT_NE(errOut.find(expectedCategory), std::string::npos) + << "Expected category not found in output. Got: " << errOut; + EXPECT_NE(errOut.find(expectedName), std::string::npos) + << "Expected name not found in output. Got: " << errOut; + EXPECT_NE(errOut.find(expectedFunction), std::string::npos) + << "Expected function not found in output. Got: " << errOut; + EXPECT_NE(errOut.find(expectedMessage), std::string::npos) + << "Expected message not found in output. Got: " << errOut; +} } // namespace diff --git a/offload/CMakeLists.txt b/offload/CMakeLists.txt index 81e246d9f8892..1cb3c62954c43 100644 --- a/offload/CMakeLists.txt +++ b/offload/CMakeLists.txt @@ -16,6 +16,10 @@ endif() if(APPLE OR WIN32 OR WASM) message(WARNING "libomptarget cannot be built on Windows and MacOS X!") return() +elseif("${LLVM_DEFAULT_TARGET_TRIPLE}" MATCHES "^(amdgcn|nvptx|spirv)" OR + "${CMAKE_CXX_COMPILER_TARGET}" MATCHES "^(amdgcn|nvptx|spirv)") + message(WARNING "offload cannot be built on GPU targets yet.") + return() elseif(NOT "cxx_std_17" IN_LIST CMAKE_CXX_COMPILE_FEATURES) message(WARNING "Host compiler must support C++17 to build libomptarget!") return() diff --git a/offload/libomptarget/DeviceImage.cpp b/offload/libomptarget/DeviceImage.cpp index e5b4bf5526437..23a0629860060 100644 --- a/offload/libomptarget/DeviceImage.cpp +++ b/offload/libomptarget/DeviceImage.cpp @@ -30,15 +30,21 @@ DeviceImageTy::DeviceImageTy(__tgt_bin_desc &BinaryDesc, llvm::StringRef ImageStr(static_cast(Image.ImageStart), utils::getPtrDiff(Image.ImageEnd, Image.ImageStart)); - auto BinaryOrErr = + auto BinariesOrErr = llvm::object::OffloadBinary::create(llvm::MemoryBufferRef(ImageStr, "")); - if (!BinaryOrErr) { - consumeError(BinaryOrErr.takeError()); + if (!BinariesOrErr) { + consumeError(BinariesOrErr.takeError()); return; } - Binary = std::move(*BinaryOrErr); + auto &Binaries = *BinariesOrErr; + if (Binaries.empty()) + return; + + // Offload Binary V2 supports multiple images, but in this context we only + // expect one image per Offload Binary. + Binary = std::move(Binaries[0]); void *Begin = const_cast( static_cast(Binary->getImage().bytes_begin())); void *End = const_cast( diff --git a/offload/plugins-nextgen/common/CMakeLists.txt b/offload/plugins-nextgen/common/CMakeLists.txt index ea0910abf95d5..23000783270f8 100644 --- a/offload/plugins-nextgen/common/CMakeLists.txt +++ b/offload/plugins-nextgen/common/CMakeLists.txt @@ -37,7 +37,7 @@ target_link_libraries(PluginCommon PRIVATE llvm-libc-common-utilities) # Define the TARGET_NAME and DEBUG_PREFIX. target_compile_definitions(PluginCommon PRIVATE - TARGET_NAME="PluginInterface" + TARGET_NAME=PluginInterface DEBUG_PREFIX="PluginInterface" ) diff --git a/offload/plugins-nextgen/common/include/RPC.h b/offload/plugins-nextgen/common/include/RPC.h index 148bbf406578f..a4c6008ea5794 100644 --- a/offload/plugins-nextgen/common/include/RPC.h +++ b/offload/plugins-nextgen/common/include/RPC.h @@ -17,6 +17,7 @@ #define OPENMP_LIBOMPTARGET_PLUGINS_NEXTGEN_COMMON_RPC_H #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SetVector.h" #include "llvm/Support/Error.h" #include @@ -80,6 +81,9 @@ struct RPCServerTy { /// Mutex that guards accesses to the buffers and device array. std::mutex BufferMutex{}; + /// A list of callbacks the server will attempt to handle. + llvm::SmallSetVector Callbacks; + /// A helper class for running the user thread that handles the RPC interface. /// Because we only need to check the RPC server while any kernels are /// working, we track submission / completion events to allow the thread to @@ -101,6 +105,9 @@ struct RPCServerTy { /// A reference to the main server's mutex. std::mutex &BufferMutex; + /// A reference to the main server's callbacks. + llvm::SmallSetVector &Callbacks; + /// A reference to all the RPC interfaces that the server is handling. llvm::ArrayRef Buffers; @@ -109,9 +116,11 @@ struct RPCServerTy { /// Initialize the worker thread to run in the background. ServerThread(void *Buffers[], plugin::GenericDeviceTy *Devices[], - size_t Length, std::mutex &BufferMutex) + size_t Length, std::mutex &BufferMutex, + llvm::SmallSetVector &Callbacks) : Running(false), NumUsers(0), CV(), Mutex(), BufferMutex(BufferMutex), - Buffers(Buffers, Length), Devices(Devices, Length) {} + Callbacks(Callbacks), Buffers(Buffers, Length), + Devices(Devices, Length) {} ~ServerThread() { assert(!Running && "Thread not shut down explicitly\n"); } diff --git a/offload/plugins-nextgen/common/src/RPC.cpp b/offload/plugins-nextgen/common/src/RPC.cpp index 8e2f28f40a053..234bd10614654 100644 --- a/offload/plugins-nextgen/common/src/RPC.cpp +++ b/offload/plugins-nextgen/common/src/RPC.cpp @@ -21,12 +21,6 @@ using namespace llvm; using namespace omp; using namespace target; -// List of user generated callbacks for the RPC server. -static llvm::SmallVector &getRPCCallbacks() { - static llvm::SmallVector Callbacks; - return Callbacks; -} - template rpc::Status handleOffloadOpcodes(plugin::GenericDeviceTy &Device, rpc::Server::Port &Port) { @@ -89,8 +83,10 @@ static rpc::Status handleOffloadOpcodes(plugin::GenericDeviceTy &Device, return rpc::RPC_ERROR; } -static rpc::Status runServer(plugin::GenericDeviceTy &Device, void *Buffer, - bool &ClientInUse) { +static rpc::Status +runServer(plugin::GenericDeviceTy &Device, void *Buffer, + llvm::SmallSetVector &Callbacks, + bool &ClientInUse) { const uint64_t NumPorts = std::min(Device.requestedRPCPortCount(), rpc::MAX_PORT_COUNT); rpc::Server Server(NumPorts, Buffer); @@ -103,7 +99,7 @@ static rpc::Status runServer(plugin::GenericDeviceTy &Device, void *Buffer, rpc::Status Status = rpc::RPC_UNHANDLED_OPCODE; const uint32_t NumLanes = Device.getWarpSize(); - for (RPCServerTy::RPCServerCallbackTy Callback : getRPCCallbacks()) { + for (RPCServerTy::RPCServerCallbackTy Callback : Callbacks) { Status = static_cast(Callback(&*Port, NumLanes)); if (Status != rpc::RPC_UNHANDLED_OPCODE) break; @@ -169,7 +165,8 @@ void RPCServerTy::ServerThread::run() { continue; // If running the server failed, print a message but keep running. - if (runServer(*Device, Buffer, ClientInUse) != rpc::RPC_SUCCESS) + if (runServer(*Device, Buffer, Callbacks, ClientInUse) != + rpc::RPC_SUCCESS) FAILURE_MESSAGE("Unhandled or invalid RPC opcode!"); } } @@ -182,7 +179,8 @@ RPCServerTy::RPCServerTy(plugin::GenericPluginTy &Plugin) Devices(std::make_unique( Plugin.getNumDevices())), Thread(new ServerThread(Buffers.get(), Devices.get(), - Plugin.getNumDevices(), BufferMutex)) {} + Plugin.getNumDevices(), BufferMutex, Callbacks)) { +} llvm::Error RPCServerTy::startThread() { Thread->startThread(); @@ -246,5 +244,5 @@ Error RPCServerTy::deinitDevice(plugin::GenericDeviceTy &Device) { void RPCServerTy::registerCallback(RPCServerCallbackTy FnPtr) { std::lock_guard Lock(BufferMutex); - getRPCCallbacks().push_back(FnPtr); + Callbacks.insert(FnPtr); } diff --git a/offload/test/mapping/map_both_pointer_pointee.c b/offload/test/mapping/map_both_pointer_pointee.c index 9ba0e0e5e6401..0462beaf184df 100644 --- a/offload/test/mapping/map_both_pointer_pointee.c +++ b/offload/test/mapping/map_both_pointer_pointee.c @@ -3,8 +3,6 @@ // REQUIRES: unified_shared_memory // UNSUPPORTED: amdgcn-amd-amdhsa // -// FIXME: https://github.com/llvm/llvm-project/issues/161265 -// XFAIL: nvidiagpu // XFAIL: intelgpu #pragma omp declare target diff --git a/offload/test/mapping/map_ptr_and_star_local.c b/offload/test/mapping/map_ptr_and_star_local.c index f8962d1beffc4..fdbf8a82b3712 100644 --- a/offload/test/mapping/map_ptr_and_star_local.c +++ b/offload/test/mapping/map_ptr_and_star_local.c @@ -2,8 +2,7 @@ // REQUIRES: libc // -// FIXME: https://github.com/llvm/llvm-project/issues/161265 -// XFAIL: gpu +// XFAIL: intelgpu #include #include diff --git a/offload/test/mapping/map_structptr_and_member_global.c b/offload/test/mapping/map_structptr_and_member_global.c index 7336b7c85ca1d..28cb54387f9d3 100644 --- a/offload/test/mapping/map_structptr_and_member_global.c +++ b/offload/test/mapping/map_structptr_and_member_global.c @@ -2,8 +2,7 @@ // REQUIRES: libc // -// FIXME: https://github.com/llvm/llvm-project/issues/161265 -// XFAIL: gpu +// XFAIL: intelgpu #include #include diff --git a/offload/test/mapping/map_structptr_and_member_local.c b/offload/test/mapping/map_structptr_and_member_local.c index 5936a7c73d48f..fa0d524eb5210 100644 --- a/offload/test/mapping/map_structptr_and_member_local.c +++ b/offload/test/mapping/map_structptr_and_member_local.c @@ -2,8 +2,7 @@ // REQUIRES: libc // -// FIXME: https://github.com/llvm/llvm-project/issues/161265 -// XFAIL: gpu +// XFAIL: intelgpu #include #include diff --git a/offload/test/offloading/fortran/basic-target-parallel-do.f90 b/offload/test/offloading/fortran/basic-target-parallel-do.f90 index f97d4085ac395..ee86b69a279f3 100644 --- a/offload/test/offloading/fortran/basic-target-parallel-do.f90 +++ b/offload/test/offloading/fortran/basic-target-parallel-do.f90 @@ -25,5 +25,5 @@ program main end program main -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: number of errors: 0 diff --git a/offload/test/offloading/fortran/basic-target-parallel-reduction.f90 b/offload/test/offloading/fortran/basic-target-parallel-reduction.f90 index cb84bcd3462cf..5300eb0df49c6 100644 --- a/offload/test/offloading/fortran/basic-target-parallel-reduction.f90 +++ b/offload/test/offloading/fortran/basic-target-parallel-reduction.f90 @@ -23,5 +23,5 @@ program main end program main -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: number of errors: 0 diff --git a/offload/test/offloading/fortran/basic-target-teams-parallel-reduction.f90 b/offload/test/offloading/fortran/basic-target-teams-parallel-reduction.f90 index fab4950452478..496449dc714ae 100644 --- a/offload/test/offloading/fortran/basic-target-teams-parallel-reduction.f90 +++ b/offload/test/offloading/fortran/basic-target-teams-parallel-reduction.f90 @@ -23,5 +23,5 @@ program main end program main -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: number of errors: 0 diff --git a/offload/test/offloading/fortran/default-mapper-nested-derived-type.f90 b/offload/test/offloading/fortran/default-mapper-nested-derived-type.f90 index 5d69fa072fd63..e54110f7e5d60 100644 --- a/offload/test/offloading/fortran/default-mapper-nested-derived-type.f90 +++ b/offload/test/offloading/fortran/default-mapper-nested-derived-type.f90 @@ -31,4 +31,4 @@ program test_omp_target_map_bug_v5 deallocate(config%derived_field%alloc_field) end program test_omp_target_map_bug_v5 -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} diff --git a/offload/test/offloading/fortran/do-concurrent-to-omp-saxpy-2d.f90 b/offload/test/offloading/fortran/do-concurrent-to-omp-saxpy-2d.f90 index c6f576acb90b6..2f1526c126e97 100644 --- a/offload/test/offloading/fortran/do-concurrent-to-omp-saxpy-2d.f90 +++ b/offload/test/offloading/fortran/do-concurrent-to-omp-saxpy-2d.f90 @@ -47,7 +47,7 @@ program main deallocate(x,y) end program main -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: plausibility check: ! CHECK: y(1,1) 4.0 ! CHECK: y(n,m) 4.0 diff --git a/offload/test/offloading/fortran/do-concurrent-to-omp-saxpy.f90 b/offload/test/offloading/fortran/do-concurrent-to-omp-saxpy.f90 index e094a1d7459ef..91eedd3afae3c 100644 --- a/offload/test/offloading/fortran/do-concurrent-to-omp-saxpy.f90 +++ b/offload/test/offloading/fortran/do-concurrent-to-omp-saxpy.f90 @@ -47,7 +47,7 @@ program main deallocate(x,y) end program main -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: plausibility check: ! CHECK: y(1) 4.0 ! CHECK: y(n) 4.0 diff --git a/offload/test/offloading/fortran/explicit-and-implicit-record-field-mapping.f90 b/offload/test/offloading/fortran/explicit-and-implicit-record-field-mapping.f90 index b619774514b2c..6ec9ffd0264bf 100644 --- a/offload/test/offloading/fortran/explicit-and-implicit-record-field-mapping.f90 +++ b/offload/test/offloading/fortran/explicit-and-implicit-record-field-mapping.f90 @@ -79,5 +79,5 @@ program reproducer print *, "======= Test Passed! =======" end program reproducer -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: ======= Test Passed! ======= diff --git a/offload/test/offloading/fortran/implicit-record-field-mapping.f90 b/offload/test/offloading/fortran/implicit-record-field-mapping.f90 index 29894941c424b..9c93ee0166e25 100644 --- a/offload/test/offloading/fortran/implicit-record-field-mapping.f90 +++ b/offload/test/offloading/fortran/implicit-record-field-mapping.f90 @@ -48,5 +48,5 @@ program test_implicit_field_mapping endif end program -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: Test succeeded! diff --git a/offload/test/offloading/fortran/target-custom-reduction-derivedtype.f90 b/offload/test/offloading/fortran/target-custom-reduction-derivedtype.f90 index cc390cf0881f3..c0aaa357eb746 100644 --- a/offload/test/offloading/fortran/target-custom-reduction-derivedtype.f90 +++ b/offload/test/offloading/fortran/target-custom-reduction-derivedtype.f90 @@ -83,6 +83,6 @@ program main end program main -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: PASSED diff --git a/offload/test/offloading/fortran/target-no-loop.f90 b/offload/test/offloading/fortran/target-no-loop.f90 index 0cebfbc008b54..93b4a1bba7bc6 100644 --- a/offload/test/offloading/fortran/target-no-loop.f90 +++ b/offload/test/offloading/fortran/target-no-loop.f90 @@ -82,17 +82,17 @@ program main end program main -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode ! CHECK: info: #Args: 3 Teams x Thrds: 64x 16 -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} SPMD mode +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} SPMD mode ! CHECK: info: #Args: 3 Teams x Thrds: 3x 16 {{.*}} -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode ! CHECK: info: #Args: 3 Teams x Thrds: 64x 16 {{.*}} -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} SPMD mode +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} SPMD mode ! CHECK: info: #Args: 3 Teams x Thrds: 1x 16 -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} Generic mode +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} Generic mode ! CHECK: info: #Args: 3 Teams x Thrds: 16x 16 {{.*}} -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} SPMD mode +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} SPMD mode ! CHECK: info: #Args: 4 Teams x Thrds: 16x 16 {{.*}} ! CHECK: number of errors: 0 diff --git a/offload/test/offloading/fortran/target-parallel-do-collapse.f90 b/offload/test/offloading/fortran/target-parallel-do-collapse.f90 index d68ea944484c4..619ba340d5f27 100644 --- a/offload/test/offloading/fortran/target-parallel-do-collapse.f90 +++ b/offload/test/offloading/fortran/target-parallel-do-collapse.f90 @@ -34,6 +34,6 @@ program main end program main -! CHECK: "PluginInterface" device {{[0-9]+}} info: Launching kernel {{.*}} +! CHECK: PluginInterface device {{[0-9]+}} info: Launching kernel {{.*}} ! CHECK: number of errors: 0 diff --git a/offload/test/offloading/ompx_bare.c b/offload/test/offloading/ompx_bare.c index 9589d72de3cd8..432e4359ed161 100644 --- a/offload/test/offloading/ompx_bare.c +++ b/offload/test/offloading/ompx_bare.c @@ -16,7 +16,9 @@ int main(int argc, char *argv[]) { const int N = num_blocks * block_size; int *data = (int *)malloc(N * sizeof(int)); - // CHECK: "PluginInterface" device 0 info: Launching kernel __omp_offloading_{{.*}} with [64,1,1] blocks and [64,1,1] threads in BARE mode + // CHECK: PluginInterface device 0 info: Launching kernel + // CHECK-SAME: __omp_offloading_{{.*}} with [64,1,1] blocks and [64,1,1] + // CHECK-SAME: threads in BARE mode #pragma omp target teams ompx_bare num_teams(num_blocks) thread_limit(block_size) map(from: data[0:N]) { diff --git a/offload/test/offloading/ompx_bare_multi_dim.cpp b/offload/test/offloading/ompx_bare_multi_dim.cpp index 924810a44b076..46d5f03b44692 100644 --- a/offload/test/offloading/ompx_bare_multi_dim.cpp +++ b/offload/test/offloading/ompx_bare_multi_dim.cpp @@ -10,7 +10,9 @@ #include #include -// CHECK: "PluginInterface" device 0 info: Launching kernel __omp_offloading_{{.*}} with [2,4,6] blocks and [32,4,2] threads in BARE mode +// CHECK: PluginInterface device 0 info: Launching kernel +// CHECK-SAME: __omp_offloading_{{.*}} with [2,4,6] blocks and [32,4,2] threads +// CHECK-SAME: in BARE mode int main(int argc, char *argv[]) { int bs[3] = {32u, 4u, 2u}; diff --git a/offload/test/unified_shared_memory/api.c b/offload/test/unified_shared_memory/api.c index 243060b4e55d0..93e5ac111359a 100644 --- a/offload/test/unified_shared_memory/api.c +++ b/offload/test/unified_shared_memory/api.c @@ -1,8 +1,6 @@ // RUN: %libomptarget-compile-generic // RUN: env HSA_XNACK=1 \ // RUN: %libomptarget-run-generic | %fcheck-generic -// XFAIL: nvptx64-nvidia-cuda -// XFAIL: nvptx64-nvidia-cuda-LTO // REQUIRES: unified_shared_memory // XFAIL: intelgpu diff --git a/offload/test/unified_shared_memory/close_enter_exit.c b/offload/test/unified_shared_memory/close_enter_exit.c index f040039f6b1a0..35980c0d734b6 100644 --- a/offload/test/unified_shared_memory/close_enter_exit.c +++ b/offload/test/unified_shared_memory/close_enter_exit.c @@ -5,9 +5,6 @@ // REQUIRES: unified_shared_memory // UNSUPPORTED: clang-6, clang-7, clang-8, clang-9 -// Fails on nvptx with error: an illegal memory access was encountered -// XFAIL: nvptx64-nvidia-cuda -// XFAIL: nvptx64-nvidia-cuda-LTO // XFAIL: intelgpu #include diff --git a/openmp/device/src/LibC.cpp b/openmp/device/src/LibC.cpp index 83f9233d94803..905f341ee88a2 100644 --- a/openmp/device/src/LibC.cpp +++ b/openmp/device/src/LibC.cpp @@ -8,7 +8,7 @@ #include "LibC.h" -#if defined(__AMDGPU__) && !defined(OMPTARGET_HAS_LIBC) +#if !defined(__NVPTX__) && !defined(OMPTARGET_HAS_LIBC) extern "C" int vprintf(const char *format, __builtin_va_list) { return -1; } #else extern "C" int vprintf(const char *format, __builtin_va_list); diff --git a/openmp/runtime/CMakeLists.txt b/openmp/runtime/CMakeLists.txt index 9332ca30128d8..dc2f2be079bf3 100644 --- a/openmp/runtime/CMakeLists.txt +++ b/openmp/runtime/CMakeLists.txt @@ -152,6 +152,10 @@ else() "Appended user specified linked libs flags. (e.g., -lm)") endif() +if("${LIBOMP_ARCH}" STREQUAL "mips" OR "${LIBOMP_ARCH}" STREQUAL "mips64") + set(LIBOMP_LIBFLAGS "${LIBOMP_LIBFLAGS} -latomic") +endif() + # Should the libomp library and generated headers be copied into the original source exports/ directory # Turning this to FALSE aids parallel builds to not interfere with each other. # Currently, the testsuite module expects the just built OpenMP library to be located inside the exports/ diff --git a/polly/lib/CodeGen/BlockGenerators.cpp b/polly/lib/CodeGen/BlockGenerators.cpp index b87c40c94243e..9d3e2bfea8713 100644 --- a/polly/lib/CodeGen/BlockGenerators.cpp +++ b/polly/lib/CodeGen/BlockGenerators.cpp @@ -778,12 +778,12 @@ void BlockGenerator::generateScalarStores( Val = getNewValue(Stmt, Val, BBMap, LTS, L); assert((!isa(Val) || - DT.dominates(cast(Val)->getParent(), - Builder.GetInsertBlock())) && + GenDT->dominates(cast(Val)->getParent(), + Builder.GetInsertBlock())) && "Domination violation"); assert((!isa(Address) || - DT.dominates(cast(Address)->getParent(), - Builder.GetInsertBlock())) && + GenDT->dominates(cast(Address)->getParent(), + Builder.GetInsertBlock())) && "Domination violation"); Builder.CreateStore(Val, Address); diff --git a/polly/lib/CodeGen/IslNodeBuilder.cpp b/polly/lib/CodeGen/IslNodeBuilder.cpp index c286066032625..299c98b21d702 100644 --- a/polly/lib/CodeGen/IslNodeBuilder.cpp +++ b/polly/lib/CodeGen/IslNodeBuilder.cpp @@ -807,8 +807,6 @@ IslNodeBuilder::createNewAccesses(ScopStmt *Stmt, // isl cannot generate an index expression for access-nothing accesses. isl::set AccDomain = PWAccRel.domain(); - isl::set Context = S.getContext(); - AccDomain = AccDomain.intersect_params(Context); if (AccDomain.is_empty()) continue; diff --git a/polly/lib/CodeGen/LoopGeneratorsGOMP.cpp b/polly/lib/CodeGen/LoopGeneratorsGOMP.cpp index 7b6d63a8ae186..82b255d2e43af 100644 --- a/polly/lib/CodeGen/LoopGeneratorsGOMP.cpp +++ b/polly/lib/CodeGen/LoopGeneratorsGOMP.cpp @@ -148,7 +148,7 @@ ParallelLoopGeneratorGOMP::createSubFn(Value *Stride, AllocaInst *StructData, "polly.par.UBAdjusted"); Builder.CreateBr(CheckNextBB); - Builder.SetInsertPoint(--Builder.GetInsertPoint()); + Builder.SetInsertPoint(std::prev(Builder.GetInsertPoint())); BasicBlock *AfterBB; Value *IV = createLoop(LB, UB, Stride, Builder, *SubFnLI, *SubFnDT, AfterBB, diff --git a/polly/lib/CodeGen/LoopGeneratorsKMP.cpp b/polly/lib/CodeGen/LoopGeneratorsKMP.cpp index 0973191e003c9..dfeea989f6c0b 100644 --- a/polly/lib/CodeGen/LoopGeneratorsKMP.cpp +++ b/polly/lib/CodeGen/LoopGeneratorsKMP.cpp @@ -282,7 +282,7 @@ ParallelLoopGeneratorKMP::createSubFn(Value *SequentialLoopStride, } Builder.CreateBr(CheckNextBB); - Builder.SetInsertPoint(--Builder.GetInsertPoint()); + Builder.SetInsertPoint(std::prev(Builder.GetInsertPoint())); BasicBlock *AfterBB; Value *IV = createLoop(LB, UB, SequentialLoopStride, Builder, *SubFnLI, *SubFnDT, AfterBB, ICmpInst::ICMP_SLE, nullptr, true, diff --git a/polly/lib/External/isl/GIT_HEAD_ID b/polly/lib/External/isl/GIT_HEAD_ID index 4c9925a417b1e..4b3a0dd01b24b 100644 --- a/polly/lib/External/isl/GIT_HEAD_ID +++ b/polly/lib/External/isl/GIT_HEAD_ID @@ -1 +1 @@ -isl-0.27 +isl-0.27-78-gfc484e00 diff --git a/polly/lib/External/isl/doc/user.pod b/polly/lib/External/isl/doc/user.pod index 3e9e0b88146a1..3be07f0102486 100644 --- a/polly/lib/External/isl/doc/user.pod +++ b/polly/lib/External/isl/doc/user.pod @@ -469,8 +469,8 @@ Use the system clang libraries installed in I. =back -It is best to use the latest release of the clang libraries (16.0), -although any release since 3.5 should work as well. +It is best to use the latest release of the clang libraries (21.1), +although any release since 3.9 should work as well. Note that if you build the clang libraries from source, then you need to make sure they are also installed (using C). If the compiler that was used to compile the clang libraries @@ -5247,6 +5247,9 @@ return true if the objects are not the same. __isl_keep isl_multi_id *mi2); #include + isl_bool isl_multi_val_is_equal( + __isl_keep isl_multi_val *mv1, + __isl_keep isl_multi_val *mv2); isl_bool isl_multi_val_plain_is_equal( __isl_keep isl_multi_val *mv1, __isl_keep isl_multi_val *mv2); @@ -6450,9 +6453,17 @@ variables, then the result of these operations is currently undefined. __isl_take isl_map *map, __isl_take isl_map_list *list); + #include + __isl_give isl_union_set * + isl_union_set_plain_unshifted_simple_hull( + __isl_take isl_union_set *uset); + #include __isl_give isl_union_map *isl_union_map_simple_hull( __isl_take isl_union_map *umap); + __isl_give isl_union_map * + isl_union_map_plain_unshifted_simple_hull( + __isl_take isl_union_map *umap); These functions compute a single basic set or relation that contains the whole input set or relation. @@ -6553,6 +6564,14 @@ The box can be copied and freed using the following functions. __isl_null isl_fixed_box *isl_fixed_box_free( __isl_take isl_fixed_box *box); +The following function checks whether two C objects +are obviously the same. + + #include + isl_bool isl_fixed_box_plain_is_equal( + __isl_keep isl_fixed_box *box1, + __isl_keep isl_fixed_box *box2); + An object of type C can be read from input using the following function. diff --git a/polly/lib/External/isl/include/isl/arg.h b/polly/lib/External/isl/include/isl/arg.h index edbd81e12dd08..5de33ca1475c3 100644 --- a/polly/lib/External/isl/include/isl/arg.h +++ b/polly/lib/External/isl/include/isl/arg.h @@ -288,6 +288,8 @@ struct isl_args { #define ISL_ARG_ALL (1 << 0) #define ISL_ARG_SKIP_HELP (1 << 1) +int isl_arg_str_list_append(int *n, const char ***list, const char *s); + void isl_args_set_defaults(struct isl_args *args, void *opt); void isl_args_free(struct isl_args *args, void *opt); int isl_args_parse(struct isl_args *args, int argc, char **argv, void *opt, diff --git a/polly/lib/External/isl/include/isl/cpp-checked.h b/polly/lib/External/isl/include/isl/cpp-checked.h index 678fcb7c1f6b2..909a78b779e7e 100644 --- a/polly/lib/External/isl/include/isl/cpp-checked.h +++ b/polly/lib/External/isl/include/isl/cpp-checked.h @@ -1742,6 +1742,7 @@ class fixed_box { inline boolean is_valid() const; inline isl::checked::multi_aff offset() const; inline isl::checked::multi_aff get_offset() const; + inline boolean plain_is_equal(const isl::checked::fixed_box &box2) const; inline isl::checked::multi_val size() const; inline isl::checked::multi_val get_size() const; inline isl::checked::space space() const; @@ -2586,6 +2587,7 @@ class multi_val { inline isl::checked::multi_val flat_range_product(isl::checked::multi_val multi2) const; inline boolean has_range_tuple_id() const; inline boolean involves_nan() const; + inline boolean is_equal(const isl::checked::multi_val &mv2) const; inline isl::checked::val_list list() const; inline isl::checked::val_list get_list() const; inline isl::checked::multi_val max(isl::checked::multi_val multi2) const; @@ -9037,6 +9039,12 @@ isl::checked::multi_aff fixed_box::get_offset() const return offset(); } +boolean fixed_box::plain_is_equal(const isl::checked::fixed_box &box2) const +{ + auto res = isl_fixed_box_plain_is_equal(get(), box2.get()); + return manage(res); +} + isl::checked::multi_val fixed_box::size() const { auto res = isl_fixed_box_get_size(get()); @@ -12843,6 +12851,12 @@ boolean multi_val::involves_nan() const return manage(res); } +boolean multi_val::is_equal(const isl::checked::multi_val &mv2) const +{ + auto res = isl_multi_val_is_equal(get(), mv2.get()); + return manage(res); +} + isl::checked::val_list multi_val::list() const { auto res = isl_multi_val_get_list(get()); diff --git a/polly/lib/External/isl/include/isl/cpp.h b/polly/lib/External/isl/include/isl/cpp.h index 3a529b60c50f2..3793a4f555dcc 100644 --- a/polly/lib/External/isl/include/isl/cpp.h +++ b/polly/lib/External/isl/include/isl/cpp.h @@ -1808,6 +1808,7 @@ class fixed_box { inline bool is_valid() const; inline isl::multi_aff offset() const; inline isl::multi_aff get_offset() const; + inline bool plain_is_equal(const isl::fixed_box &box2) const; inline isl::multi_val size() const; inline isl::multi_val get_size() const; inline isl::space space() const; @@ -2652,6 +2653,7 @@ class multi_val { inline isl::multi_val flat_range_product(isl::multi_val multi2) const; inline bool has_range_tuple_id() const; inline bool involves_nan() const; + inline bool is_equal(const isl::multi_val &mv2) const; inline isl::val_list list() const; inline isl::val_list get_list() const; inline isl::multi_val max(isl::multi_val multi2) const; @@ -10929,6 +10931,18 @@ isl::multi_aff fixed_box::get_offset() const return offset(); } +bool fixed_box::plain_is_equal(const isl::fixed_box &box2) const +{ + if (!ptr || box2.is_null()) + exception::throw_invalid("NULL input", __FILE__, __LINE__); + auto saved_ctx = ctx(); + options_scoped_set_on_error saved_on_error(saved_ctx, exception::on_error); + auto res = isl_fixed_box_plain_is_equal(get(), box2.get()); + if (res < 0) + exception::throw_last_error(saved_ctx); + return res; +} + isl::multi_val fixed_box::size() const { if (!ptr) @@ -17158,6 +17172,18 @@ bool multi_val::involves_nan() const return res; } +bool multi_val::is_equal(const isl::multi_val &mv2) const +{ + if (!ptr || mv2.is_null()) + exception::throw_invalid("NULL input", __FILE__, __LINE__); + auto saved_ctx = ctx(); + options_scoped_set_on_error saved_on_error(saved_ctx, exception::on_error); + auto res = isl_multi_val_is_equal(get(), mv2.get()); + if (res < 0) + exception::throw_last_error(saved_ctx); + return res; +} + isl::val_list multi_val::list() const { if (!ptr) diff --git a/polly/lib/External/isl/include/isl/ctx.h b/polly/lib/External/isl/include/isl/ctx.h index 22c64841e3bcc..0ab9ebd37de61 100644 --- a/polly/lib/External/isl/include/isl/ctx.h +++ b/polly/lib/External/isl/include/isl/ctx.h @@ -12,6 +12,7 @@ #include #include +#include #include @@ -85,7 +86,7 @@ typedef enum { isl_stat_error = -1, isl_stat_ok = 0 } isl_stat; -isl_stat isl_stat_non_null(void *obj); +isl_stat isl_stat_non_null(const void *obj); typedef enum { isl_bool_error = -1, isl_bool_false = 0, @@ -240,6 +241,21 @@ isl_stat prefix ## _set_ ## field(isl_ctx *ctx, const char *val) \ return isl_stat_ok; \ } +#define ISL_CTX_APPEND_STR_LIST_DEF(prefix,st,args,field_n,field) \ +isl_stat prefix ## _append_ ## field(isl_ctx *ctx, const char *val) \ +{ \ + st *options; \ + options = isl_ctx_peek_ ## prefix(ctx); \ + if (!options) \ + isl_die(ctx, isl_error_invalid, \ + "isl_ctx does not reference " #prefix, \ + return isl_stat_error); \ + if (!val) \ + return isl_stat_error; \ + return isl_arg_str_list_append(&options->field_n, \ + &options->field, val); \ +} + #define ISL_CTX_GET_BOOL_DEF(prefix,st,args,field) \ ISL_CTX_GET_INT_DEF(prefix,st,args,field) diff --git a/polly/lib/External/isl/include/isl/fixed_box.h b/polly/lib/External/isl/include/isl/fixed_box.h index 2debfd0334915..68d9d158a4594 100644 --- a/polly/lib/External/isl/include/isl/fixed_box.h +++ b/polly/lib/External/isl/include/isl/fixed_box.h @@ -31,6 +31,10 @@ __isl_give isl_multi_val *isl_fixed_box_get_size(__isl_keep isl_fixed_box *box); __isl_give isl_fixed_box *isl_fixed_box_copy(__isl_keep isl_fixed_box *box); __isl_null isl_fixed_box *isl_fixed_box_free(__isl_take isl_fixed_box *box); +__isl_export +isl_bool isl_fixed_box_plain_is_equal(__isl_keep isl_fixed_box *box1, + __isl_keep isl_fixed_box *box2); + __isl_constructor __isl_give isl_fixed_box *isl_fixed_box_read_from_str(isl_ctx *ctx, const char *str); diff --git a/polly/lib/External/isl/include/isl/union_map.h b/polly/lib/External/isl/include/isl/union_map.h index c17c27d74e2ed..e71c03009717e 100644 --- a/polly/lib/External/isl/include/isl/union_map.h +++ b/polly/lib/External/isl/include/isl/union_map.h @@ -82,6 +82,8 @@ __isl_give isl_union_map *isl_union_map_remove_redundancies( __isl_take isl_union_map *umap); __isl_give isl_union_map *isl_union_map_simple_hull( __isl_take isl_union_map *umap); +__isl_give isl_union_map *isl_union_map_plain_unshifted_simple_hull( + __isl_take isl_union_map *umap); __isl_export __isl_give isl_union_map *isl_union_map_coalesce( __isl_take isl_union_map *umap); diff --git a/polly/lib/External/isl/include/isl/union_set.h b/polly/lib/External/isl/include/isl/union_set.h index b86196de41e93..792ef93e2615a 100644 --- a/polly/lib/External/isl/include/isl/union_set.h +++ b/polly/lib/External/isl/include/isl/union_set.h @@ -52,6 +52,8 @@ __isl_give isl_union_set *isl_union_set_remove_redundancies( __isl_take isl_union_set *uset); __isl_give isl_union_set *isl_union_set_simple_hull( __isl_take isl_union_set *uset); +__isl_give isl_union_set *isl_union_set_plain_unshifted_simple_hull( + __isl_take isl_union_set *uset); __isl_export __isl_give isl_union_set *isl_union_set_coalesce( __isl_take isl_union_set *uset); diff --git a/polly/lib/External/isl/include/isl/val.h b/polly/lib/External/isl/include/isl/val.h index 942207db91674..b0f0aeaddce5a 100644 --- a/polly/lib/External/isl/include/isl/val.h +++ b/polly/lib/External/isl/include/isl/val.h @@ -153,6 +153,9 @@ __isl_give isl_printer *isl_printer_print_val(__isl_take isl_printer *p, void isl_val_dump(__isl_keep isl_val *v); __isl_give char *isl_val_to_str(__isl_keep isl_val *v); +__isl_export +isl_bool isl_multi_val_is_equal(__isl_keep isl_multi_val *mv1, + __isl_keep isl_multi_val *mv2); isl_bool isl_multi_val_is_zero(__isl_keep isl_multi_val *mv); __isl_overload diff --git a/polly/lib/External/isl/interface/configure.ac b/polly/lib/External/isl/interface/configure.ac index b61822bad802a..da3daa34dfbf5 100644 --- a/polly/lib/External/isl/interface/configure.ac +++ b/polly/lib/External/isl/interface/configure.ac @@ -25,7 +25,7 @@ LT_INIT AX_DETECT_CLANG AC_SUBST([CONFIG_STATUS_DEPENDENCIES], [$LLVM_CONFIG]) -AC_CONFIG_HEADERS(isl_config.h) +AC_CONFIG_HEADERS(isl_config.h include/isl-interface/config.h) AC_CONFIG_FILES(Makefile) AC_OUTPUT diff --git a/polly/lib/External/isl/interface/cpp.cc b/polly/lib/External/isl/interface/cpp.cc index d5c08ebf25f0f..12b0c4d3bc7c8 100644 --- a/polly/lib/External/isl/interface/cpp.cc +++ b/polly/lib/External/isl/interface/cpp.cc @@ -689,12 +689,12 @@ std::string cpp_type_printer::generate_callback_args(int arg, QualType type, int num_params; callback = generator::extract_prototype(type); - num_params = callback->getNumArgs(); + num_params = callback->getNumParams(); if (cpp) num_params--; for (long i = 0; i < num_params; i++) { - QualType type = callback->getArgType(i); + QualType type = callback->getParamType(i); if (cpp) type_str += param(arg + 1 + i, type); diff --git a/polly/lib/External/isl/interface/extract_interface.cc b/polly/lib/External/isl/interface/extract_interface.cc index cb09c531626ce..4521de166d2ea 100644 --- a/polly/lib/External/isl/interface/extract_interface.cc +++ b/polly/lib/External/isl/interface/extract_interface.cc @@ -38,52 +38,24 @@ #include #include #include -#ifdef HAVE_ADT_OWNINGPTR_H -#include -#else #include -#endif -#ifdef HAVE_LLVM_OPTION_ARG_H -#include -#endif #include #include -#ifdef HAVE_TARGETPARSER_HOST_H -#include -#else -#include -#endif #include -#include #include -#include +#include #include -#include -#include -#include -#include -#include -#include -#include #include -#include -#ifdef HAVE_BASIC_DIAGNOSTICOPTIONS_H -#include -#else -#include -#endif #include #include #include -#ifdef HAVE_LEX_PREPROCESSOROPTIONS_H #include -#else -#include -#endif #include #include #include +#include "isl-interface/clang_wrap.h" + #include "extract_interface.h" #include "generator.h" #include "python.h" @@ -98,10 +70,6 @@ using namespace clang::driver; using namespace llvm::opt; #endif -#ifdef HAVE_ADT_OWNINGPTR_H -#define unique_ptr llvm::OwningPtr -#endif - static llvm::cl::opt InputFilename(llvm::cl::Positional, llvm::cl::Required, llvm::cl::desc("")); static llvm::cl::list Includes("I", @@ -113,9 +81,6 @@ static llvm::cl::opt OutputLanguage(llvm::cl::Required, llvm::cl::desc("Bindings to generate"), llvm::cl::value_desc("name")); -static const char *ResourceDir = - CLANG_PREFIX "/lib/clang/" CLANG_VERSION_STRING; - /* Does decl have an attribute of the following form? * * __attribute__((annotate("name"))) @@ -179,360 +144,59 @@ struct MyASTConsumer : public ASTConsumer { } }; -#ifdef USE_ARRAYREF - -#ifdef HAVE_CXXISPRODUCTION -static Driver *construct_driver(const char *binary, DiagnosticsEngine &Diags) -{ - return new Driver(binary, llvm::sys::getDefaultTargetTriple(), - "", false, false, Diags); -} -#elif defined(HAVE_ISPRODUCTION) -static Driver *construct_driver(const char *binary, DiagnosticsEngine &Diags) -{ - return new Driver(binary, llvm::sys::getDefaultTargetTriple(), - "", false, Diags); -} -#elif defined(DRIVER_CTOR_TAKES_DEFAULTIMAGENAME) -static Driver *construct_driver(const char *binary, DiagnosticsEngine &Diags) -{ - return new Driver(binary, llvm::sys::getDefaultTargetTriple(), - "", Diags); -} -#else -static Driver *construct_driver(const char *binary, DiagnosticsEngine &Diags) -{ - return new Driver(binary, llvm::sys::getDefaultTargetTriple(), Diags); -} -#endif - -namespace clang { namespace driver { class Job; } } - -/* Clang changed its API from 3.5 to 3.6 and once more in 3.7. - * We fix this with a simple overloaded function here. +/* A class specializing the Wrap helper class for + * extracting the isl interface. */ -struct ClangAPI { - static Job *command(Job *J) { return J; } - static Job *command(Job &J) { return &J; } - static Command *command(Command &C) { return &C; } +struct Extractor : public isl::clang::Wrap { + virtual TextDiagnosticPrinter *construct_printer() override; + virtual void suppress_errors(DiagnosticsEngine &Diags) override; + virtual void add_paths(HeaderSearchOptions &HSO) override; + virtual void add_macros(PreprocessorOptions &PO) override; + virtual void handle_error() override; + virtual bool handle(CompilerInstance *Clang) override; }; -#ifdef CREATE_FROM_ARGS_TAKES_ARRAYREF - -/* Call CompilerInvocation::CreateFromArgs with the right arguments. - * In this case, an ArrayRef. - */ -static void create_from_args(CompilerInvocation &invocation, - const ArgStringList *args, DiagnosticsEngine &Diags) -{ - CompilerInvocation::CreateFromArgs(invocation, *args, Diags); -} - -#else - -/* Call CompilerInvocation::CreateFromArgs with the right arguments. - * In this case, two "const char *" pointers. +/* Construct a TextDiagnosticPrinter. */ -static void create_from_args(CompilerInvocation &invocation, - const ArgStringList *args, DiagnosticsEngine &Diags) +TextDiagnosticPrinter *Extractor::construct_printer(void) { - CompilerInvocation::CreateFromArgs(invocation, args->data() + 1, - args->data() + args->size(), - Diags); + return new TextDiagnosticPrinter(llvm::errs(), getDiagnosticOptions()); } -#endif - -#ifdef CLANG_SYSROOT -/* Set sysroot if required. - * - * If CLANG_SYSROOT is defined, then set it to this value. +/* Suppress any errors, if needed. */ -static void set_sysroot(ArgStringList &args) -{ - args.push_back("-isysroot"); - args.push_back(CLANG_SYSROOT); -} -#else -/* Set sysroot if required. - * - * If CLANG_SYSROOT is not defined, then it does not need to be set. - */ -static void set_sysroot(ArgStringList &args) -{ -} -#endif - -/* Create a CompilerInvocation object that stores the command line - * arguments constructed by the driver. - * The arguments are mainly useful for setting up the system include - * paths on newer clangs and on some platforms. - */ -static CompilerInvocation *construct_invocation(const char *filename, - DiagnosticsEngine &Diags) -{ - const char *binary = CLANG_PREFIX"/bin/clang"; - const unique_ptr driver(construct_driver(binary, Diags)); - std::vector Argv; - Argv.push_back(binary); - Argv.push_back(filename); - const unique_ptr compilation( - driver->BuildCompilation(llvm::ArrayRef(Argv))); - JobList &Jobs = compilation->getJobs(); - - Command *cmd = cast(ClangAPI::command(*Jobs.begin())); - if (strcmp(cmd->getCreator().getName(), "clang")) - return NULL; - - ArgStringList args = cmd->getArguments(); - set_sysroot(args); - - CompilerInvocation *invocation = new CompilerInvocation; - create_from_args(*invocation, &args, Diags); - return invocation; -} - -#else - -static CompilerInvocation *construct_invocation(const char *filename, - DiagnosticsEngine &Diags) -{ - return NULL; -} - -#endif - -#ifdef HAVE_BASIC_DIAGNOSTICOPTIONS_H - -static TextDiagnosticPrinter *construct_printer(void) -{ - return new TextDiagnosticPrinter(llvm::errs(), new DiagnosticOptions()); -} - -#else - -static TextDiagnosticPrinter *construct_printer(void) -{ - DiagnosticOptions DO; - return new TextDiagnosticPrinter(llvm::errs(), DO); -} - -#endif - -#ifdef CREATETARGETINFO_TAKES_SHARED_PTR - -static TargetInfo *create_target_info(CompilerInstance *Clang, - DiagnosticsEngine &Diags) -{ - shared_ptr TO = Clang->getInvocation().TargetOpts; - TO->Triple = llvm::sys::getDefaultTargetTriple(); - return TargetInfo::CreateTargetInfo(Diags, TO); -} - -#elif defined(CREATETARGETINFO_TAKES_POINTER) - -static TargetInfo *create_target_info(CompilerInstance *Clang, - DiagnosticsEngine &Diags) -{ - TargetOptions &TO = Clang->getTargetOpts(); - TO.Triple = llvm::sys::getDefaultTargetTriple(); - return TargetInfo::CreateTargetInfo(Diags, &TO); -} - -#else - -static TargetInfo *create_target_info(CompilerInstance *Clang, - DiagnosticsEngine &Diags) +void Extractor::suppress_errors(DiagnosticsEngine &Diags) { - TargetOptions &TO = Clang->getTargetOpts(); - TO.Triple = llvm::sys::getDefaultTargetTriple(); - return TargetInfo::CreateTargetInfo(Diags, TO); } -#endif - -#ifdef CREATEDIAGNOSTICS_TAKES_ARG - -static void create_diagnostics(CompilerInstance *Clang) -{ - Clang->createDiagnostics(0, NULL, construct_printer()); -} - -#else - -static void create_diagnostics(CompilerInstance *Clang) -{ - Clang->createDiagnostics(construct_printer()); -} - -#endif - -#ifdef CREATEPREPROCESSOR_TAKES_TUKIND - -static void create_preprocessor(CompilerInstance *Clang) -{ - Clang->createPreprocessor(TU_Complete); -} - -#else - -static void create_preprocessor(CompilerInstance *Clang) -{ - Clang->createPreprocessor(); -} - -#endif - -#ifdef ADDPATH_TAKES_4_ARGUMENTS - -/* Add "Path" to the header search options. - * - * Do not take into account sysroot, i.e., set ignoreSysRoot to true. +/* Add required search paths to "HSO". */ -void add_path(HeaderSearchOptions &HSO, string Path) +void Extractor::add_paths(HeaderSearchOptions &HSO) { - HSO.AddPath(Path, frontend::Angled, false, true); -} - -#else - -/* Add "Path" to the header search options. - * - * Do not take into account sysroot, i.e., set IsSysRootRelative to false. - */ -void add_path(HeaderSearchOptions &HSO, string Path) -{ - HSO.AddPath(Path, frontend::Angled, true, false, false); -} - -#endif - -#ifdef HAVE_SETMAINFILEID - -template -static void create_main_file_id(SourceManager &SM, const T &file) -{ - SM.setMainFileID(SM.createFileID(file, SourceLocation(), - SrcMgr::C_User)); -} - -#else - -static void create_main_file_id(SourceManager &SM, const FileEntry *file) -{ - SM.createMainFileID(file); -} - -#endif - -#ifdef SETLANGDEFAULTS_TAKES_5_ARGUMENTS - -#include "set_lang_defaults_arg4.h" - -static void set_lang_defaults(CompilerInstance *Clang) -{ - PreprocessorOptions &PO = Clang->getPreprocessorOpts(); - TargetOptions &TO = Clang->getTargetOpts(); - llvm::Triple T(TO.Triple); - SETLANGDEFAULTS::setLangDefaults(Clang->getLangOpts(), IK_C, T, - setLangDefaultsArg4(PO), - LangStandard::lang_unspecified); -} - -#else - -static void set_lang_defaults(CompilerInstance *Clang) -{ - CompilerInvocation::setLangDefaults(Clang->getLangOpts(), IK_C, - LangStandard::lang_unspecified); -} - -#endif - -#ifdef SETINVOCATION_TAKES_SHARED_PTR - -static void set_invocation(CompilerInstance *Clang, - CompilerInvocation *invocation) -{ - Clang->setInvocation(std::make_shared(*invocation)); -} - -#else - -static void set_invocation(CompilerInstance *Clang, - CompilerInvocation *invocation) -{ - Clang->setInvocation(invocation); -} - -#endif - -/* Helper function for ignore_error that only gets enabled if T - * (which is either const FileEntry * or llvm::ErrorOr) - * has getError method, i.e., if it is llvm::ErrorOr. - */ -template -static const FileEntry *ignore_error_helper(const T obj, int, - int[1][sizeof(obj.getError())]) -{ - return *obj; -} - -/* Helper function for ignore_error that is always enabled, - * but that only gets selected if the variant above is not enabled, - * i.e., if T is const FileEntry *. - */ -template -static const FileEntry *ignore_error_helper(const T obj, long, void *) -{ - return obj; + for (llvm::cl::list::size_type i = 0; i < Includes.size(); ++i) + isl::clang::add_path(HSO, Includes[i]); } -/* Given either a const FileEntry * or a llvm::ErrorOr, - * extract out the const FileEntry *. +/* Add required macro definitions to "PO". */ -template -static const FileEntry *ignore_error(const T obj) +void Extractor::add_macros(PreprocessorOptions &PO) { - return ignore_error_helper(obj, 0, NULL); + PO.addMacroDef("__isl_give=__attribute__((annotate(\"isl_give\")))"); + PO.addMacroDef("__isl_keep=__attribute__((annotate(\"isl_keep\")))"); + PO.addMacroDef("__isl_take=__attribute__((annotate(\"isl_take\")))"); + PO.addMacroDef("__isl_export=__attribute__((annotate(\"isl_export\")))"); + PO.addMacroDef("__isl_overload=" + "__attribute__((annotate(\"isl_overload\"))) " + "__attribute__((annotate(\"isl_export\")))"); + PO.addMacroDef("__isl_constructor=__attribute__((annotate(\"isl_constructor\"))) __attribute__((annotate(\"isl_export\")))"); + PO.addMacroDef("__isl_subclass(super)=__attribute__((annotate(\"isl_subclass(\" #super \")\"))) __attribute__((annotate(\"isl_export\")))"); } -/* This is identical to std::void_t in C++17. - */ -template< class... > -using void_t = void; - -/* A template class with value true if "T" has a getFileRef method. +/* Handle an error opening the file. */ -template -struct HasGetFileRef : public std::false_type {}; -template -struct HasGetFileRef> : - public std::true_type {}; - -/* Return the FileEntryRef/FileEntry corresponding to the given file name - * in the given compiler instances, ignoring any error. - * - * If T (= FileManager) has a getFileRef method, then call that and - * return a FileEntryRef. - * Otherwise, call getFile and return a FileEntry (pointer). - */ -template ::value, bool>::type = true> -static auto getFile(T& obj, const std::string &filename) - -> decltype(*obj.getFileRef(filename)) -{ - auto file = obj.getFileRef(filename); - assert(file); - return *file; -} -template ::value, bool>::type = true> -static const FileEntry *getFile(T& obj, const std::string &filename) +void Extractor::handle_error() { - const FileEntry *file = ignore_error(obj.getFile(filename)); - assert(file); - return file; + assert(false); } /* Create an interface generator for the selected language and @@ -567,64 +231,36 @@ static void generate(MyASTConsumer &consumer, SourceManager &SM) gen->generate(); } -int main(int argc, char *argv[]) +/* Parse the current source file, returning true if no error was encountered. + */ +bool Extractor::handle(CompilerInstance *Clang) { - llvm::cl::ParseCommandLineOptions(argc, argv); - - CompilerInstance *Clang = new CompilerInstance(); - create_diagnostics(Clang); - DiagnosticsEngine &Diags = Clang->getDiagnostics(); - Diags.setSuppressSystemWarnings(true); - TargetInfo *target = create_target_info(Clang, Diags); - Clang->setTarget(target); - set_lang_defaults(Clang); - CompilerInvocation *invocation = - construct_invocation(InputFilename.c_str(), Diags); - if (invocation) - set_invocation(Clang, invocation); - Clang->createFileManager(); - Clang->createSourceManager(Clang->getFileManager()); - HeaderSearchOptions &HSO = Clang->getHeaderSearchOpts(); - LangOptions &LO = Clang->getLangOpts(); - PreprocessorOptions &PO = Clang->getPreprocessorOpts(); - HSO.ResourceDir = ResourceDir; - - for (llvm::cl::list::size_type i = 0; i < Includes.size(); ++i) - add_path(HSO, Includes[i]); - - PO.addMacroDef("__isl_give=__attribute__((annotate(\"isl_give\")))"); - PO.addMacroDef("__isl_keep=__attribute__((annotate(\"isl_keep\")))"); - PO.addMacroDef("__isl_take=__attribute__((annotate(\"isl_take\")))"); - PO.addMacroDef("__isl_export=__attribute__((annotate(\"isl_export\")))"); - PO.addMacroDef("__isl_overload=" - "__attribute__((annotate(\"isl_overload\"))) " - "__attribute__((annotate(\"isl_export\")))"); - PO.addMacroDef("__isl_constructor=__attribute__((annotate(\"isl_constructor\"))) __attribute__((annotate(\"isl_export\")))"); - PO.addMacroDef("__isl_subclass(super)=__attribute__((annotate(\"isl_subclass(\" #super \")\"))) __attribute__((annotate(\"isl_export\")))"); - - create_preprocessor(Clang); Preprocessor &PP = Clang->getPreprocessor(); - - PP.getBuiltinInfo().initializeBuiltins(PP.getIdentifierTable(), LO); - - auto file = getFile(Clang->getFileManager(), InputFilename); - create_main_file_id(Clang->getSourceManager(), file); - - Clang->createASTContext(); MyASTConsumer consumer; Sema *sema = new Sema(PP, Clang->getASTContext(), consumer); - Diags.getClient()->BeginSourceFile(LO, &PP); + DiagnosticsEngine &Diags = Clang->getDiagnostics(); + Diags.getClient()->BeginSourceFile(Clang->getLangOpts(), &PP); ParseAST(*sema); Diags.getClient()->EndSourceFile(); generate(consumer, Clang->getSourceManager()); delete sema; - delete Clang; + + return !Diags.hasErrorOccurred(); +} + +int main(int argc, char *argv[]) +{ + llvm::cl::ParseCommandLineOptions(argc, argv); + + Extractor extractor; + bool ok = extractor.invoke(InputFilename.c_str()); + llvm::llvm_shutdown(); - if (Diags.hasErrorOccurred()) + if (!ok) return EXIT_FAILURE; return EXIT_SUCCESS; } diff --git a/polly/lib/External/isl/interface/generator.cc b/polly/lib/External/isl/interface/generator.cc index 4b9890325ccb0..ce09b32399c17 100644 --- a/polly/lib/External/isl/interface/generator.cc +++ b/polly/lib/External/isl/interface/generator.cc @@ -796,7 +796,7 @@ const FunctionProtoType *generator::extract_prototype(QualType type) */ int generator::prototype_n_args(QualType type) { - return extract_prototype(type)->getNumArgs(); + return extract_prototype(type)->getNumParams(); } /* Return the function name suffix for the type of "param". diff --git a/polly/lib/External/isl/interface/include/isl-interface/clang_wrap.h b/polly/lib/External/isl/interface/include/isl-interface/clang_wrap.h new file mode 100644 index 0000000000000..4ad8299be128a --- /dev/null +++ b/polly/lib/External/isl/interface/include/isl-interface/clang_wrap.h @@ -0,0 +1,425 @@ +#include + +#include + +#ifdef HAVE_LLVM_OPTION_ARG_H +#include +#endif +#ifdef HAVE_TARGETPARSER_HOST_H +#include +#else +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace clang { namespace driver { class Job; } } + +namespace isl { +namespace clang { + +using namespace ::clang; +using namespace ::clang::driver; +#ifdef HAVE_LLVM_OPTION_ARG_H +using namespace llvm::opt; +#endif + +#ifndef ISL_CLANG_RESOURCE_DIR +#define ISL_CLANG_RESOURCE_DIR \ + ISL_CLANG_PREFIX "/lib/clang/" CLANG_VERSION_STRING +#endif +static const char *ResourceDir = ISL_CLANG_RESOURCE_DIR; + +static Driver *construct_driver(const char *binary, DiagnosticsEngine &Diags) +{ + return new Driver(binary, llvm::sys::getDefaultTargetTriple(), Diags); +} + +/* Clang changed its API from 3.5 to 3.6 and once more in 3.7. + * We fix this with a simple overloaded function here. + */ +struct ClangAPI { + static Job *command(Job *J) { return J; } + static Job *command(Job &J) { return &J; } + static Command *command(Command &C) { return &C; } +}; + +#ifdef CREATE_FROM_ARGS_TAKES_ARRAYREF + +/* Call CompilerInvocation::CreateFromArgs with the right arguments. + * In this case, an ArrayRef. + */ +static void create_from_args(CompilerInvocation &invocation, + const ArgStringList *args, DiagnosticsEngine &Diags) +{ + CompilerInvocation::CreateFromArgs(invocation, *args, Diags); +} + +#else + +/* Call CompilerInvocation::CreateFromArgs with the right arguments. + * In this case, two "const char *" pointers. + */ +static void create_from_args(CompilerInvocation &invocation, + const ArgStringList *args, DiagnosticsEngine &Diags) +{ + CompilerInvocation::CreateFromArgs(invocation, args->data() + 1, + args->data() + args->size(), + Diags); +} + +#endif + +#ifdef ISL_CLANG_SYSROOT +/* Set sysroot if required. + * + * If ISL_CLANG_SYSROOT is defined, then set it to this value. + */ +static void set_sysroot(ArgStringList &args) +{ + args.push_back("-isysroot"); + args.push_back(ISL_CLANG_SYSROOT); +} +#else +/* Set sysroot if required. + * + * If ISL_CLANG_SYSROOT is not defined, then it does not need to be set. + */ +static void set_sysroot(ArgStringList &args) +{ +} +#endif + +/* Create a CompilerInvocation object that stores the command line + * arguments constructed by the driver. + * The arguments are mainly useful for setting up the system include + * paths on newer clangs and on some platforms. + */ +static void construct_invocation(CompilerInstance *Clang, + const char *filename, DiagnosticsEngine &Diags) +{ + const char *binary = ISL_CLANG_PREFIX"/bin/clang"; + const std::unique_ptr driver(construct_driver(binary, Diags)); + std::vector Argv; + Argv.push_back(binary); + Argv.push_back(filename); + const std::unique_ptr compilation( + driver->BuildCompilation(llvm::ArrayRef(Argv))); + JobList &Jobs = compilation->getJobs(); + + Command *cmd = cast(ClangAPI::command(*Jobs.begin())); + if (strcmp(cmd->getCreator().getName(), "clang")) + return; + + ArgStringList args = cmd->getArguments(); + set_sysroot(args); + + create_from_args(Clang->getInvocation(), &args, Diags); +} + +#ifdef CREATETARGETINFO_TAKES_SHARED_PTR + +static TargetInfo *create_target_info(CompilerInstance *Clang, + DiagnosticsEngine &Diags) +{ + std::shared_ptr TO = Clang->getInvocation().TargetOpts; + TO->Triple = llvm::sys::getDefaultTargetTriple(); + return TargetInfo::CreateTargetInfo(Diags, TO); +} + +#else + +static TargetInfo *create_target_info(CompilerInstance *Clang, + DiagnosticsEngine &Diags) +{ + TargetOptions &TO = Clang->getTargetOpts(); + TO.Triple = llvm::sys::getDefaultTargetTriple(); + return TargetInfo::CreateTargetInfo(Diags, TO); +} + +#endif + +#ifdef CREATEDIAGNOSTICS_TAKES_VFS + +static void create_diagnostics(CompilerInstance *Clang) +{ + Clang->createDiagnostics(*llvm::vfs::getRealFileSystem()); +} + +#else + +static void create_diagnostics(CompilerInstance *Clang) +{ + Clang->createDiagnostics(); +} + +#endif + +static void create_preprocessor(CompilerInstance *Clang) +{ + Clang->createPreprocessor(TU_Complete); +} + +/* Add "Path" to the header search options. + * + * Do not take into account sysroot, i.e., set ignoreSysRoot to true. + */ +static void add_path(HeaderSearchOptions &HSO, std::string Path) +{ + HSO.AddPath(Path, frontend::Angled, false, true); +} + +template +static void create_main_file_id(SourceManager &SM, const T &file) +{ + SM.setMainFileID(SM.createFileID(file, SourceLocation(), + SrcMgr::C_User)); +} + +#ifdef SETLANGDEFAULTS_TAKES_5_ARGUMENTS + +#include "isl-interface/set_lang_defaults_arg4.h" + +static void set_lang_defaults(CompilerInstance *Clang) +{ + PreprocessorOptions &PO = Clang->getPreprocessorOpts(); + TargetOptions &TO = Clang->getTargetOpts(); + llvm::Triple T(TO.Triple); + SETLANGDEFAULTS::setLangDefaults(Clang->getLangOpts(), IK_C, T, + setLangDefaultsArg4(PO), + LangStandard::lang_unspecified); +} + +#else + +static void set_lang_defaults(CompilerInstance *Clang) +{ + CompilerInvocation::setLangDefaults(Clang->getLangOpts(), IK_C, + LangStandard::lang_unspecified); +} + +#endif + +/* Helper function for ignore_error that only gets enabled if T + * (which is either const FileEntry * or llvm::ErrorOr) + * has getError method, i.e., if it is llvm::ErrorOr. + */ +template +static const FileEntry *ignore_error_helper(const T obj, int, + int[1][sizeof(obj.getError())]) +{ + return *obj; +} + +/* Helper function for ignore_error that is always enabled, + * but that only gets selected if the variant above is not enabled, + * i.e., if T is const FileEntry *. + */ +template +static const FileEntry *ignore_error_helper(const T obj, long, void *) +{ + return obj; +} + +/* Given either a const FileEntry * or a llvm::ErrorOr, + * extract out the const FileEntry *. + */ +template +static const FileEntry *ignore_error(const T obj) +{ + return ignore_error_helper(obj, 0, NULL); +} + +/* Define a template class "CLASS" with value true + * if "EXPR" is valid for its template argument (available as "U" in "EXPR"). + */ +#define ISL_VALID_EXPR_FOR_TEMPLATE_ARG(CLASS, EXPR) \ +template \ +struct CLASS { \ +private: \ + template \ + static auto test(int) -> decltype(EXPR, std::true_type()); \ + \ + template \ + static std::false_type test(...); \ + \ +public: \ + using type = decltype(test(0)); \ + static constexpr bool value = type::value; \ +}; + +/* A template class with value true if the template argument + * has a getFileRef method. + */ +ISL_VALID_EXPR_FOR_TEMPLATE_ARG(HasGetFileRef, + std::declval().getFileRef(std::declval())) + +/* Return a wrapper around the FileEntryRef/FileEntry + * corresponding to the given file name. The wrapper evaluates + * to false if an error occurs. + * + * If T (= FileManager) has a getFileRef method, then call that and + * return an llvm::Expected. + * Otherwise, call getFile and return a FileEntry (pointer) embedded + * in an llvm::ErrorOr. + */ +template ::value, bool>::type = true> +static auto getFile(T& obj, const std::string &filename) + -> decltype(obj.getFileRef(filename)) +{ + return obj.getFileRef(filename); +} +template ::value, bool>::type = true> +static llvm::ErrorOr getFile(T& obj, + const std::string &filename) +{ + const FileEntry *file = ignore_error(obj.getFile(filename)); + if (!file) + return std::error_code(); + return file; +} + +/* A template class with value true if the constructor of the template argument + * takes a reference to a DiagnosticOptions object. + */ +ISL_VALID_EXPR_FOR_TEMPLATE_ARG(TakesDiagnosticOptionsRef, + new U(llvm::errs(), std::declval())) + +/* Return the type of the DiagnosticOptions argument of the constructor of "T". + * + * If TakesDiagnosticOptionsRef holds, then this is a reference + * to a DiagnosticOptions object. + * Otherwise, it is a pointer to such an object. + */ +template ::value, + bool>::type = true> +static DiagnosticOptions &diag_opts_type(); +template ::value, + bool>::type = true> +static DiagnosticOptions *diag_opts_type(); + +/* A helper class handling the invocation of clang on a file and + * allowing a derived class to perform the actual parsing + * in an overridden handle() method. + * Other virtual methods allow different kinds of configuration. + */ +struct Wrap { + /* The type of the DiagnosticOptions argument + * of the TextDiagnosticPrinter constructor. + */ + using DiagOptsType = decltype(diag_opts_type()); + /* A local DiagnosticOptions object that is used + * if TextDiagnosticPrinter takes a reference + * to a DiagnosticOptions object. + */ + DiagnosticOptions DiagOpts; + + /* Return a valid DiagnosticOptions argument + * for the constructor of "T". + * If "T" takes a reference, then + * this is a reference to the DiagOpts field. + * Otherwise, it is a pointer to a new object. + */ + template ::value, + bool>::type = true> + DiagnosticOptions &getDiagOpts() { + return DiagOpts; + } + template ::value, + bool>::type = true> + DiagnosticOptions *getDiagOpts() { + return new DiagnosticOptions(); + } + + /* Return a valid DiagnosticOptions argument for + * the TextDiagnosticPrinter constructor. + * If TextDiagnosticPrinter takes a reference, then + * this is a reference to the DiagOpts field. + * Otherwise, it is a pointer to a new object. + */ + DiagOptsType getDiagnosticOptions() { + return getDiagOpts(); + } + + /* Construct a TextDiagnosticPrinter. */ + virtual TextDiagnosticPrinter *construct_printer() = 0; + /* Suppress any errors, if needed. */ + virtual void suppress_errors(DiagnosticsEngine &Diags) = 0; + /* Add required search paths to "HSO". */ + virtual void add_paths(HeaderSearchOptions &HSO) = 0; + /* Add required macro definitions to "PO". */ + virtual void add_macros(PreprocessorOptions &PO) = 0; + /* Handle an error opening the file. */ + virtual void handle_error() = 0; + /* Parse the file, returning true if no error was encountered. */ + virtual bool handle(CompilerInstance *Clang) = 0; + + /* Invoke clang on "filename", passing control to the handle() method + * for parsing. + */ + bool invoke(const char *filename) { + CompilerInstance *Clang = new CompilerInstance(); + create_diagnostics(Clang); + DiagnosticsEngine &Diags = Clang->getDiagnostics(); + Diags.setSuppressSystemWarnings(true); + suppress_errors(Diags); + TargetInfo *target = create_target_info(Clang, Diags); + Clang->setTarget(target); + set_lang_defaults(Clang); + construct_invocation(Clang, filename, Diags); + Diags.setClient(construct_printer()); + Clang->createFileManager(); + Clang->createSourceManager(Clang->getFileManager()); + HeaderSearchOptions &HSO = Clang->getHeaderSearchOpts(); + LangOptions &LO = Clang->getLangOpts(); + PreprocessorOptions &PO = Clang->getPreprocessorOpts(); + HSO.ResourceDir = ResourceDir; + HSO.AddPath(ISL_CLANG_RESOURCE_DIR "/include", + clang::frontend::System, false, false); + + add_paths(HSO); + add_macros(PO); + + create_preprocessor(Clang); + Preprocessor &PP = Clang->getPreprocessor(); + + PP.getBuiltinInfo().initializeBuiltins(PP.getIdentifierTable(), + LO); + auto file = getFile(Clang->getFileManager(), filename); + if (!file) { + handle_error(); + delete Clang; + return false; + } + create_main_file_id(Clang->getSourceManager(), *file); + + Clang->createASTContext(); + bool ok = handle(Clang); + delete Clang; + + return ok; + } +}; + +} +} diff --git a/polly/lib/External/isl/interface/include/isl-interface/config.h.in b/polly/lib/External/isl/interface/include/isl-interface/config.h.in new file mode 100644 index 0000000000000..adc3ab27075cd --- /dev/null +++ b/polly/lib/External/isl/interface/include/isl-interface/config.h.in @@ -0,0 +1,16 @@ +#ifndef ISL_CLANG_WRAP_CONFIG_H +#define ISL_CLANG_WRAP_CONFIG_H + +#undef CREATE_FROM_ARGS_TAKES_ARRAYREF +#undef CREATEDIAGNOSTICS_TAKES_VFS +#undef CREATETARGETINFO_TAKES_SHARED_PTR +#undef HAVE_LLVM_OPTION_ARG_H +#undef HAVE_TARGETPARSER_HOST_H +#undef IK_C +#undef ISL_CLANG_PREFIX +#undef ISL_CLANG_RESOURCE_DIR +#undef ISL_CLANG_SYSROOT +#undef SETLANGDEFAULTS +#undef SETLANGDEFAULTS_TAKES_5_ARGUMENTS + +#endif diff --git a/polly/lib/External/isl/interface/set_lang_defaults_arg4.h b/polly/lib/External/isl/interface/include/isl-interface/set_lang_defaults_arg4.h similarity index 100% rename from polly/lib/External/isl/interface/set_lang_defaults_arg4.h rename to polly/lib/External/isl/interface/include/isl-interface/set_lang_defaults_arg4.h diff --git a/polly/lib/External/isl/interface/isl.py.core b/polly/lib/External/isl/interface/isl.py.core index c4edc579cae5f..128899c7eecc5 100644 --- a/polly/lib/External/isl/interface/isl.py.core +++ b/polly/lib/External/isl/interface/isl.py.core @@ -12850,6 +12850,22 @@ class fixed_box(object): return obj def get_offset(arg0): return arg0.offset() + def plain_is_equal(arg0, arg1): + try: + if not arg0.__class__ is fixed_box: + arg0 = fixed_box(arg0) + except: + raise + try: + if not arg1.__class__ is fixed_box: + arg1 = fixed_box(arg1) + except: + raise + ctx = arg0.ctx + res = isl.isl_fixed_box_plain_is_equal(arg0.ptr, arg1.ptr) + if res < 0: + raise Error + return bool(res) def size(arg0): try: if not arg0.__class__ is fixed_box: @@ -12880,6 +12896,7 @@ isl.isl_fixed_box_read_from_str.argtypes = [Context, c_char_p] isl.isl_fixed_box_is_valid.argtypes = [c_void_p] isl.isl_fixed_box_get_offset.restype = c_void_p isl.isl_fixed_box_get_offset.argtypes = [c_void_p] +isl.isl_fixed_box_plain_is_equal.argtypes = [c_void_p, c_void_p] isl.isl_fixed_box_get_size.restype = c_void_p isl.isl_fixed_box_get_size.argtypes = [c_void_p] isl.isl_fixed_box_get_space.restype = c_void_p @@ -13889,6 +13906,22 @@ class multi_val(object): if res < 0: raise Error return bool(res) + def is_equal(arg0, arg1): + try: + if not arg0.__class__ is multi_val: + arg0 = multi_val(arg0) + except: + raise + try: + if not arg1.__class__ is multi_val: + arg1 = multi_val(arg1) + except: + raise + ctx = arg0.ctx + res = isl.isl_multi_val_is_equal(arg0.ptr, arg1.ptr) + if res < 0: + raise Error + return bool(res) def list(arg0): try: if not arg0.__class__ is multi_val: @@ -14164,6 +14197,7 @@ isl.isl_multi_val_flat_range_product.restype = c_void_p isl.isl_multi_val_flat_range_product.argtypes = [c_void_p, c_void_p] isl.isl_multi_val_has_range_tuple_id.argtypes = [c_void_p] isl.isl_multi_val_involves_nan.argtypes = [c_void_p] +isl.isl_multi_val_is_equal.argtypes = [c_void_p, c_void_p] isl.isl_multi_val_get_list.restype = c_void_p isl.isl_multi_val_get_list.argtypes = [c_void_p] isl.isl_multi_val_max.restype = c_void_p diff --git a/polly/lib/External/isl/interface/plain_cpp.cc b/polly/lib/External/isl/interface/plain_cpp.cc index ac68b8c4c6cff..dc4b2ebf54d4f 100644 --- a/polly/lib/External/isl/interface/plain_cpp.cc +++ b/polly/lib/External/isl/interface/plain_cpp.cc @@ -1936,7 +1936,7 @@ void plain_cpp_generator::impl_printer::print_callback_body(int indent, callback = extract_prototype(ptype); rtype = callback->getReturnType(); - num_params = callback->getNumArgs(); + num_params = callback->getNumParams(); last_idx = ::to_string(num_params - 1); diff --git a/polly/lib/External/isl/interface/python.cc b/polly/lib/External/isl/interface/python.cc index e4a8288631297..23f47db397325 100644 --- a/polly/lib/External/isl/interface/python.cc +++ b/polly/lib/External/isl/interface/python.cc @@ -215,7 +215,7 @@ void python_generator::print_callback(ParmVarDecl *param, int arg) QualType type = param->getOriginalType(); const FunctionProtoType *fn = extract_prototype(type); QualType return_type = fn->getReturnType(); - unsigned n_arg = fn->getNumArgs(); + unsigned n_arg = fn->getNumParams(); printf(" exc_info = [None]\n"); printf(" fn = CFUNCTYPE("); @@ -224,7 +224,7 @@ void python_generator::print_callback(ParmVarDecl *param, int arg) else printf("c_void_p"); for (unsigned i = 0; i < n_arg - 1; ++i) { - if (!is_isl_type(fn->getArgType(i))) + if (!is_isl_type(fn->getParamType(i))) die("Argument has non-isl type"); printf(", c_void_p"); } @@ -238,11 +238,11 @@ void python_generator::print_callback(ParmVarDecl *param, int arg) printf("):\n"); for (unsigned i = 0; i < n_arg - 1; ++i) { string arg_type; - arg_type = type2python(extract_type(fn->getArgType(i))); + arg_type = type2python(extract_type(fn->getParamType(i))); printf(" cb_arg%d = %s(ctx=arg0.ctx, ptr=", i, arg_type.c_str()); if (!callback_takes_argument(param, i)) - print_copy(fn->getArgType(i)); + print_copy(fn->getParamType(i)); printf("(cb_arg%d))\n", i); } printf(" try:\n"); diff --git a/polly/lib/External/isl/interface/template_cpp.cc b/polly/lib/External/isl/interface/template_cpp.cc index b62e3b5cce01c..7cde8af27ecb2 100644 --- a/polly/lib/External/isl/interface/template_cpp.cc +++ b/polly/lib/External/isl/interface/template_cpp.cc @@ -1647,7 +1647,7 @@ static int total_params(const Method &method) auto callback_type = callback->getType(); auto proto = generator::extract_prototype(callback_type); - n += proto->getNumArgs() - 1; + n += proto->getNumParams() - 1; n -= 1; } @@ -1729,10 +1729,10 @@ static void print_callback_args(std::ostream &os, const std::function &print_arg) { - auto n_arg = callback->getNumArgs() - 1; + auto n_arg = callback->getNumParams() - 1; Method::print_arg_list(os, 0, n_arg, [&] (int i) { - auto type = callback->getArgType(i); + auto type = callback->getParamType(i); auto name = "arg" + std::to_string(i); auto cpptype = type_printer.param(shift + i, type); @@ -2709,7 +2709,7 @@ const std::string callback_name(const Method &method) auto type = method.callbacks.at(0)->getType(); auto callback = cpp_generator::extract_prototype(type); - auto arg_type = plain_type(callback->getArgType(0)); + auto arg_type = plain_type(callback->getParamType(0)); return generator::drop_suffix(method.name, "_" + arg_type); } diff --git a/polly/lib/External/isl/isl_arg.c b/polly/lib/External/isl/isl_arg.c index 8a9e26d1c62ec..43bd0d100e04c 100644 --- a/polly/lib/External/isl/isl_arg.c +++ b/polly/lib/External/isl/isl_arg.c @@ -974,19 +974,25 @@ static int parse_str_option(struct isl_arg *decl, char **arg, return 0; } -static int isl_arg_str_list_append(struct isl_arg *decl, void *opt, +int isl_arg_str_list_append(int *n, const char ***list, const char *s) +{ + const char **new_list; + + new_list = realloc(*list, (*n + 1) * sizeof(char *)); + if (!new_list) + return -1; + *list = new_list; + new_list[*n] = strdup(s); + return isl_stat_non_null(new_list[(*n)++]); +} + +static int arg_str_list_append(struct isl_arg *decl, void *opt, const char *s) { int *n = (int *)(((char *) opt) + decl->u.str_list.offset_n); - char **list = *(char ***)(((char *) opt) + decl->offset); + const char ***list = (const char ***)(((char *) opt) + decl->offset); - list = realloc(list, (*n + 1) * sizeof(char *)); - if (!list) - return -1; - *(char ***)(((char *) opt) + decl->offset) = list; - list[*n] = strdup(s); - (*n)++; - return 0; + return isl_arg_str_list_append(n, list, s); } static int parse_str_list_option(struct isl_arg *decl, char **arg, @@ -1000,12 +1006,12 @@ static int parse_str_list_option(struct isl_arg *decl, char **arg, return 0; if (has_argument) { - isl_arg_str_list_append(decl, opt, s); + arg_str_list_append(decl, opt, s); return 1; } if (arg[1]) { - isl_arg_str_list_append(decl, opt, arg[1]); + arg_str_list_append(decl, opt, arg[1]); return 2; } diff --git a/polly/lib/External/isl/isl_ast_codegen.c b/polly/lib/External/isl/isl_ast_codegen.c index 8275827a874d6..11b09dc595480 100644 --- a/polly/lib/External/isl/isl_ast_codegen.c +++ b/polly/lib/External/isl/isl_ast_codegen.c @@ -149,17 +149,28 @@ static __isl_give isl_ast_graft *at_each_domain(__isl_take isl_ast_graft *graft, static isl_stat add_domain(__isl_take isl_map *executed, struct isl_generate_domain_data *data) { + isl_bool disjoint; isl_ast_build *build; isl_ast_graft *graft; isl_ast_graft_list *list; - isl_set *guard, *pending; + isl_set *guard, *pending, *domain; + + guard = isl_map_domain(isl_map_copy(executed)); + guard = isl_set_compute_divs(guard); + domain = isl_ast_build_get_domain(data->build); + disjoint = isl_set_is_disjoint(guard, domain); + isl_set_free(domain); + + if (disjoint < 0 || disjoint) { + isl_set_free(guard); + isl_map_free(executed); + return isl_stat_non_error_bool(disjoint); + } build = isl_ast_build_copy(data->build); pending = isl_ast_build_get_pending(build); build = isl_ast_build_replace_pending_by_guard(build, pending); - guard = isl_map_domain(isl_map_copy(executed)); - guard = isl_set_compute_divs(guard); guard = isl_set_coalesce_preserve(guard); guard = isl_set_gist(guard, isl_ast_build_get_generated(build)); guard = isl_ast_build_specialize(build, guard); diff --git a/polly/lib/External/isl/isl_box.c b/polly/lib/External/isl/isl_box.c index c674af0d37623..31a477f1edb70 100644 --- a/polly/lib/External/isl/isl_box.c +++ b/polly/lib/External/isl/isl_box.c @@ -207,27 +207,65 @@ isl_bool isl_fixed_box_is_valid(__isl_keep isl_fixed_box *box) /* Return the offsets of the box "box". */ -__isl_give isl_multi_aff *isl_fixed_box_get_offset( +static __isl_keep isl_multi_aff *isl_fixed_box_peek_offset( __isl_keep isl_fixed_box *box) { if (!box) return NULL; - return isl_multi_aff_copy(box->offset); + return box->offset; +} + +/* Return a copy of the offsets of the box "box". + */ +__isl_give isl_multi_aff *isl_fixed_box_get_offset( + __isl_keep isl_fixed_box *box) +{ + return isl_multi_aff_copy(isl_fixed_box_peek_offset(box)); } /* Return the sizes of the box "box". */ -__isl_give isl_multi_val *isl_fixed_box_get_size(__isl_keep isl_fixed_box *box) +static __isl_keep isl_multi_val *isl_fixed_box_peek_size( + __isl_keep isl_fixed_box *box) { if (!box) return NULL; - return isl_multi_val_copy(box->size); + return box->size; +} + +/* Return a copy of the sizes of the box "box". + */ +__isl_give isl_multi_val *isl_fixed_box_get_size(__isl_keep isl_fixed_box *box) +{ + return isl_multi_val_copy(isl_fixed_box_peek_size(box)); +} + +/* Is "box1" obviously equal to "box2"? + * + * That is, does it have the same size and obviously the same offset? + */ +isl_bool isl_fixed_box_plain_is_equal(__isl_keep isl_fixed_box *box1, + __isl_keep isl_fixed_box *box2) +{ + isl_multi_aff *offset1, *offset2; + isl_multi_val *size1, *size2; + isl_bool equal; + + size1 = isl_fixed_box_peek_size(box1); + size2 = isl_fixed_box_peek_size(box2); + equal = isl_multi_val_is_equal(size1, size2); + if (equal < 0 || !equal) + return equal; + + offset1 = isl_fixed_box_peek_offset(box1); + offset2 = isl_fixed_box_peek_offset(box2); + return isl_multi_aff_plain_is_equal(offset1, offset2); } /* Data used in set_dim_extent and compute_size_in_direction. * * "bset" is a wrapped copy of the basic map that has the selected - * output dimension as range. + * output dimension as range, without any contraction. * "pos" is the position of the variable representing the output dimension, * i.e., the variable for which the size should be computed. This variable * is also the last variable in "bset". @@ -235,34 +273,167 @@ __isl_give isl_multi_val *isl_fixed_box_get_size(__isl_keep isl_fixed_box *box) * (infinity if no offset was found so far). * "offset" is the offset corresponding to the best size * (NULL if no offset was found so far). + * + * If "expand" is not NULL, then it maps a contracted version of "bset" + * to the original "bset", while "domain_map" maps the space of "bset" + * to the domain of the wrapped map. */ struct isl_size_info { isl_basic_set *bset; isl_size pos; isl_val *size; isl_aff *offset; + + isl_multi_aff *expand; + isl_multi_aff *domain_map; }; +/* Detect any stride in the single output dimension of "map" and + * set the fields of "info" used in exploiting this stride. + * If no (non-trivial) stride can be found, then set those fields to NULL. + * + * If there is a non-trivial stride, then the single output dimension i + * is of the form + * + * i = offset + stride * i' + * + * Construct a function that maps i' to i. + * Note that the offset may depend on the domain of the map, + * so it needs to be of the form + * + * [D -> [i']] -> [i] + * + * In fact, it is more convenient for the function to be of the form + * + * [D -> [i']] -> [D -> [i]] + * + * First construct helper functions + * + * [D -> [i]] -> D + * [D -> [i]] -> [i] + * + * Plug in [D -> [i]] -> D into the offset (defined on D) to obtain + * the offset defined on [D -> [i]] and add stride times [D -> [i]] -> [i]. + * This produces the function + * + * [D -> [i']] = [offset + stride i'] + * + * Combine it with [D -> [i]] -> D again to obtain the desired result. + */ +static __isl_give isl_map *isl_size_info_detect_stride( + struct isl_size_info *info, __isl_take isl_map *map) +{ + isl_stride_info *si; + isl_val *stride; + isl_aff *offset; + isl_bool is_one; + isl_multi_aff *domain_map, *id; + isl_multi_aff *expand; + + info->expand = NULL; + info->domain_map = NULL; + + si = isl_map_get_range_stride_info(map, 0); + stride = isl_stride_info_get_stride(si); + is_one = isl_val_is_one(stride); + if (is_one < 0 || is_one) { + isl_val_free(stride); + isl_stride_info_free(si); + return is_one < 0 ? isl_map_free(map) : map; + } + offset = isl_stride_info_get_offset(si); + isl_stride_info_free(si); + + domain_map = isl_space_domain_map_multi_aff(isl_aff_get_space(offset)); + id = isl_space_range_map_multi_aff(isl_aff_get_space(offset)); + offset = isl_aff_pullback_multi_aff(offset, + isl_multi_aff_copy(domain_map)); + + expand = isl_multi_aff_scale_val(id, stride); + expand = isl_multi_aff_add(expand, isl_multi_aff_from_aff(offset)); + expand = isl_multi_aff_range_product(isl_multi_aff_copy(domain_map), + expand); + info->expand = expand; + info->domain_map = domain_map; + + if (!expand || !domain_map) + return isl_map_free(map); + + return map; +} + +/* If any stride was detected in the single output dimension + * in the wrapped map in "bset" (i.e., if info->expand is set), + * then plug in the expansion to obtain a description in terms + * of an output dimension without stride. + * Otherwise, return the original "bset". + */ +static __isl_give isl_basic_set *isl_size_info_contract( + struct isl_size_info *info, __isl_take isl_basic_set *bset) +{ + if (!info->expand) + return bset; + + bset = isl_basic_set_preimage_multi_aff(bset, + isl_multi_aff_copy(info->expand)); + + return bset; +} + +/* Given an affine function "aff" that maps the space of "bset" + * to a value in the (possibly) contracted space, + * expand it back to the original space. + * The value of "aff" only depends on the domain of wrapped relation + * inside "bset". + * + * If info->expand is not set, then no contraction was applied and + * "aff" is returned. + * + * Otherwise, combine "aff" of the form [D -> [*]] -> [v'(D)] + * with [D -> [*]] -> D to obtain [D -> [*]] -> [D -> [v'(D)]]. + * Apply the expansion [D -> [i']] = [D -> [offset + stride * i']] + * to obtain [D -> [*]] -> [D -> [offset + stride * v'(D)]] and + * extract out [D -> [*]] -> [offset + stride * v'(D)]. + */ +static __isl_give isl_aff *isl_size_info_expand( + struct isl_size_info *info, __isl_take isl_aff *aff) +{ + isl_multi_aff *ma; + + if (!info->expand) + return aff; + + ma = isl_multi_aff_from_aff(aff); + ma = isl_multi_aff_range_product(isl_multi_aff_copy(info->domain_map), + ma); + ma = isl_multi_aff_pullback_multi_aff(isl_multi_aff_copy(info->expand), + ma); + ma = isl_multi_aff_range_factor_range(ma); + aff = isl_multi_aff_get_at(ma, 0); + isl_multi_aff_free(ma); + + return aff; +} + +/* Free all memory allocated for "info". + */ +static void isl_size_info_clear(struct isl_size_info *info) +{ + isl_val_free(info->size); + isl_aff_free(info->offset); + isl_basic_set_free(info->bset); + + isl_multi_aff_free(info->expand); + isl_multi_aff_free(info->domain_map); +} + /* Is "c" a suitable bound on dimension "pos" for use as a lower bound * of a fixed-size range. * In particular, it needs to be a lower bound on "pos". - * In order for the final offset not to be too complicated, - * the constraint itself should also not involve any integer divisions. */ static isl_bool is_suitable_bound(__isl_keep isl_constraint *c, unsigned pos) { - isl_size n_div; - isl_bool is_bound, any_divs; - - is_bound = isl_constraint_is_lower_bound(c, isl_dim_set, pos); - if (is_bound < 0 || !is_bound) - return is_bound; - - n_div = isl_constraint_dim(c, isl_dim_div); - if (n_div < 0) - return isl_bool_error; - any_divs = isl_constraint_involves_dims(c, isl_dim_div, 0, n_div); - return isl_bool_not(any_divs); + return isl_constraint_is_lower_bound(c, isl_dim_set, pos); } /* Given a constraint from the basic set describing the bounds on @@ -271,6 +442,10 @@ static isl_bool is_suitable_bound(__isl_keep isl_constraint *c, unsigned pos) * upper bound. If so, and if this bound is smaller than any bound * derived from earlier constraints, set the size to this bound on * the expression and the lower bound to ceil(b(x)/m). + * + * If any contraction was applied, then the lower bound ceil(b(x)/m) + * is defined in the contracted space, so it needs to be expanded + * first before applying it to the original space. */ static isl_stat compute_size_in_direction(__isl_take isl_constraint *c, void *user) @@ -289,6 +464,7 @@ static isl_stat compute_size_in_direction(__isl_take isl_constraint *c, aff = isl_constraint_get_bound(c, isl_dim_set, info->pos); aff = isl_aff_ceil(aff); + aff = isl_size_info_expand(info, aff); lb = isl_aff_copy(aff); @@ -326,10 +502,17 @@ static isl_stat compute_size_in_direction(__isl_take isl_constraint *c, * then invalidate the box. Otherwise, set the offset and size * in the given direction by those that correspond to the smallest size. * + * If the output dimension is strided, then scale it down before + * looking for lower bounds. The size computation is however performed + * in the original space. + * * Note that while evaluating the size corresponding to a lower bound, * an affine expression is constructed from the lower bound. * This lower bound may therefore not have any unknown local variables. * Eliminate any unknown local variables up front. + * Furthermore, the lower bound can clearly not involve + * (any local variables that involve) the output dimension itself, + * so any such local variables are eliminated as well. * No such restriction needs to be imposed on the set over which * the size is computed. */ @@ -347,14 +530,18 @@ static __isl_give isl_fixed_box *set_dim_extent(__isl_take isl_fixed_box *box, ctx = isl_map_get_ctx(map); map = isl_map_copy(map); map = isl_map_project_onto(map, isl_dim_out, pos, 1); + map = isl_size_info_detect_stride(&info, map); info.size = isl_val_infty(ctx); info.offset = NULL; info.pos = isl_map_dim(map, isl_dim_in); info.bset = isl_basic_map_wrap(isl_map_simple_hull(map)); bset = isl_basic_set_copy(info.bset); + bset = isl_size_info_contract(&info, bset); bset = isl_basic_set_remove_unknown_divs(bset); if (info.pos < 0) bset = isl_basic_set_free(bset); + bset = isl_basic_set_remove_divs_involving_dims(bset, isl_dim_set, + info.pos, 1); if (isl_basic_set_foreach_constraint(bset, &compute_size_in_direction, &info) < 0) box = isl_fixed_box_free(box); @@ -367,9 +554,7 @@ static __isl_give isl_fixed_box *set_dim_extent(__isl_take isl_fixed_box *box, info.offset, info.size); else box = isl_fixed_box_invalidate(box); - isl_val_free(info.size); - isl_aff_free(info.offset); - isl_basic_set_free(info.bset); + isl_size_info_clear(&info); return box; } diff --git a/polly/lib/External/isl/isl_ctx.c b/polly/lib/External/isl/isl_ctx.c index dd189922fd726..a9afbe7ebd988 100644 --- a/polly/lib/External/isl/isl_ctx.c +++ b/polly/lib/External/isl/isl_ctx.c @@ -31,7 +31,7 @@ isl_stat isl_stat_non_error_bool(isl_bool b) * That is, return isl_stat_ok if "obj" is non_NULL and * isl_stat_error otherwise. */ -isl_stat isl_stat_non_null(void *obj) +isl_stat isl_stat_non_null(const void *obj) { if (obj != NULL) return isl_stat_ok; diff --git a/polly/lib/External/isl/isl_map_simplify.c b/polly/lib/External/isl/isl_map_simplify.c index ab41883bbc55e..869a2086633a7 100644 --- a/polly/lib/External/isl/isl_map_simplify.c +++ b/polly/lib/External/isl/isl_map_simplify.c @@ -71,6 +71,17 @@ static void swap_inequality(__isl_keep isl_basic_map *bmap, int a, int b) } } +/* Scale down the inequality constraint "ineq" of length "len" + * by a factor of "f". + * All the coefficients, except the constant term, + * are assumed to be multiples of "f". + */ +static void scale_down_inequality(isl_int *ineq, isl_int f, unsigned len) +{ + isl_int_fdiv_q(ineq[0], ineq[0], f); + isl_seq_scale_down(ineq + 1, ineq + 1, f, len); +} + /* Scale down the inequality constraint "ineq" of length "len" * by a factor of "f". * All the coefficients, except the constant term, @@ -81,7 +92,7 @@ static void swap_inequality(__isl_keep isl_basic_map *bmap, int a, int b) * If scaling is performed then take into account that the constraint * is modified (not simply based on an equality constraint). */ -static __isl_give isl_basic_map *scale_down_inequality( +static __isl_give isl_basic_map *scale_down_bmap_inequality( __isl_take isl_basic_map *bmap, int ineq, isl_int f, unsigned len) { if (!bmap) @@ -90,8 +101,7 @@ static __isl_give isl_basic_map *scale_down_inequality( if (isl_int_is_zero(f) || isl_int_is_one(f)) return bmap; - isl_int_fdiv_q(bmap->ineq[ineq][0], bmap->ineq[ineq][0], f); - isl_seq_scale_down(bmap->ineq[ineq] + 1, bmap->ineq[ineq] + 1, f, len); + scale_down_inequality(bmap->ineq[ineq], f, len); bmap = isl_basic_map_modify_inequality(bmap, 0); @@ -144,7 +154,7 @@ __isl_give isl_basic_map *isl_basic_map_normalize_constraints( } if (ISL_F_ISSET(bmap, ISL_BASIC_MAP_RATIONAL)) isl_int_gcd(gcd, gcd, bmap->ineq[i][0]); - bmap = scale_down_inequality(bmap, i, gcd, total); + bmap = scale_down_bmap_inequality(bmap, i, gcd, total); if (!bmap) goto error; } @@ -399,7 +409,7 @@ static __isl_give isl_basic_map *eliminate_var_using_equality( mark_progress(progress); isl_seq_elim(bmap->ineq[k], eq, 1+pos, 1+total, NULL); isl_seq_gcd(bmap->ineq[k], 1 + total, &ctx->normalize_gcd); - bmap = scale_down_inequality(bmap, k, ctx->normalize_gcd, + bmap = scale_down_bmap_inequality(bmap, k, ctx->normalize_gcd, total); bmap = isl_basic_map_modify_inequality(bmap, equivalent); if (!bmap) @@ -886,6 +896,47 @@ static isl_bool constraint_index_is_redundant(struct isl_constraint_index *ci, return isl_int_ge(ineq[0], (*ci->index[h])[0]); } +/* Look for pairs of inequality constraints in "bmap" + * that are opposite to each other apart from the constant term. + * "ci" contains a hash table of the inequality constraints of "bmap". + * Return an array of size equal to the number of inequality constraints + * with as entries either + * - zero, if the constraint has no opposite, or + * - 1 + the position of the opposite constraint. + */ +static int *detect_opposites(struct isl_constraint_index *ci, + __isl_keep isl_basic_map *bmap) +{ + isl_size n_ineq; + int k, l, h; + isl_ctx *ctx; + int *opposite; + + n_ineq = isl_basic_map_n_inequality(bmap); + if (n_ineq < 0) + return NULL; + ctx = isl_basic_map_get_ctx(bmap); + opposite = isl_calloc_array(ctx, int, n_ineq); + if (!opposite) + return NULL; + + for (k = 0; k < n_ineq - 1; ++k) { + if (opposite[k]) + continue; + isl_seq_neg(bmap->ineq[k] + 1, bmap->ineq[k] + 1, ci->total); + h = hash_index(ci, bmap, k); + isl_seq_neg(bmap->ineq[k] + 1, bmap->ineq[k] + 1, ci->total); + if (!ci->index[h]) + continue; + l = ci->index[h] - &bmap->ineq[0]; + + opposite[k] = 1 + l; + opposite[l] = 1 + k; + } + + return opposite; +} + /* If we can eliminate more than one div, then we need to make * sure we do it from last div to first div, in order not to * change the position of the other divs that still need to @@ -1263,12 +1314,12 @@ static __isl_give isl_basic_map *normalize_divs(__isl_take isl_basic_map *bmap, } static __isl_give isl_basic_map *set_div_from_lower_bound( - __isl_take isl_basic_map *bmap, int div, int ineq) + __isl_take isl_basic_map *bmap, int div, isl_int *ineq) { unsigned total = isl_basic_map_offset(bmap, isl_dim_div); - isl_seq_neg(bmap->div[div] + 1, bmap->ineq[ineq], total + bmap->n_div); - isl_int_set(bmap->div[div][0], bmap->ineq[ineq][total + div]); + isl_seq_neg(bmap->div[div] + 1, ineq, total + bmap->n_div); + isl_int_set(bmap->div[div][0], ineq[total + div]); isl_int_add(bmap->div[div][1], bmap->div[div][1], bmap->div[div][0]); isl_int_sub_ui(bmap->div[div][1], bmap->div[div][1], 1); isl_int_set_si(bmap->div[div][1 + total + div], 0); @@ -1283,36 +1334,43 @@ static __isl_give isl_basic_map *set_div_from_lower_bound( * terms of the unknown div. */ static isl_bool ok_to_set_div_from_bound(__isl_keep isl_basic_map *bmap, - int div, int ineq) + int div, isl_int *ineq) { int j; - unsigned total = isl_basic_map_offset(bmap, isl_dim_div); + isl_size v_div = isl_basic_map_var_offset(bmap, isl_dim_div); + isl_size n_div = isl_basic_map_dim(bmap, isl_dim_div); + + if (v_div < 0 || n_div < 0) + return isl_bool_error; /* Not defined in terms of unknown divs */ - for (j = 0; j < bmap->n_div; ++j) { + for (j = 0; j < n_div; ++j) { + isl_bool unknown; + if (div == j) continue; - if (isl_int_is_zero(bmap->ineq[ineq][total + j])) + if (isl_int_is_zero(ineq[1 + v_div + j])) continue; - if (isl_int_is_zero(bmap->div[j][0])) - return isl_bool_false; + unknown = isl_basic_map_div_is_marked_unknown(bmap, j); + if (unknown < 0 || unknown) + return isl_bool_not(unknown); } /* No other div defined in terms of this one => avoid loops */ - for (j = 0; j < bmap->n_div; ++j) { + for (j = 0; j < n_div; ++j) { if (div == j) continue; if (isl_int_is_zero(bmap->div[j][0])) continue; - if (!isl_int_is_zero(bmap->div[j][1 + total + div])) + if (!isl_int_is_zero(bmap->div[j][1 + 1 + v_div + div])) return isl_bool_false; } return isl_bool_true; } -/* Would an expression for div "div" based on inequality "ineq" of "bmap" - * be a better expression than the current one? +/* Would an expression for div "div" based on inequality "ineq" + * be a better expression than the current one in "bmap"? * * If we do not have any expression yet, then any expression would be better. * Otherwise we check if the last variable involved in the inequality @@ -1320,28 +1378,52 @@ static isl_bool ok_to_set_div_from_bound(__isl_keep isl_basic_map *bmap, * than the last variable involved in the current div expression. */ static isl_bool better_div_constraint(__isl_keep isl_basic_map *bmap, - int div, int ineq) + int div, isl_int *ineq) { unsigned total = isl_basic_map_offset(bmap, isl_dim_div); isl_size n_div = isl_basic_map_dim(bmap, isl_dim_div); int last_div; int last_ineq; + isl_bool unknown; if (n_div < 0) return isl_bool_error; - if (isl_int_is_zero(bmap->div[div][0])) - return isl_bool_true; + unknown = isl_basic_map_div_is_marked_unknown(bmap, div); + if (unknown < 0 || unknown) + return unknown; - if (isl_seq_any_non_zero(bmap->ineq[ineq] + total + div + 1, - n_div - (div + 1))) + if (isl_seq_any_non_zero(ineq + total + div + 1, n_div - (div + 1))) return isl_bool_false; - last_ineq = isl_seq_last_non_zero(bmap->ineq[ineq], total + div); + last_ineq = isl_seq_last_non_zero(ineq, total + div); last_div = isl_seq_last_non_zero(bmap->div[div] + 1, total + n_div); return last_ineq < last_div; } +/* Given a lower bound "ineq" on local variable "div" of "bmap" + * that could in theory be used to define an integer division expression, + * do so if it is better than the current expression (if any) and + * if there is no risk of introducing circular definitions. + * Set *progress if anything is changed. + */ +static __isl_give isl_basic_map *set_div_from_lower_bound_if_better( + __isl_take isl_basic_map *bmap, int div, isl_int *ineq, int *progress) +{ + isl_bool set_div; + + set_div = better_div_constraint(bmap, div, ineq); + if (set_div >= 0 && set_div) + set_div = ok_to_set_div_from_bound(bmap, div, ineq); + if (set_div < 0) + return isl_basic_map_free(bmap); + if (!set_div) + return bmap; + bmap = set_div_from_lower_bound(bmap, div, ineq); + mark_progress(progress); + return bmap; +} + /* Is the sequence of "len" coefficients "ineq" equal to "res" * plus some non-trivial coefficients that are all a multiple of some number * greater than "sum"? @@ -1691,7 +1773,7 @@ static __isl_give isl_basic_map *check_for_residues( continue; isl_seq_sub(bmap->ineq[i], bmap->ineq[c], 1 + total); - bmap = scale_down_inequality(bmap, i, ctx->normalize_gcd, + bmap = scale_down_bmap_inequality(bmap, i, ctx->normalize_gcd, total); if (!bmap) return NULL; @@ -1701,6 +1783,260 @@ static __isl_give isl_basic_map *check_for_residues( return bmap; } +/* Given constraints of the form + * + * -n f + g + m n e + c1 >= 0 (l) + * g + c3 >= 0 (i) + * -g + c4 >= 0 (j) + * + * with e the local variable at position "div", + * does the following condition hold? + * + * c3 + c4 + (c1 - c3) % n < m n + * + * "v_div" is the position of the first local variable. + */ +static int is_residue_div_pair(__isl_take isl_basic_map *bmap, + int l, int div, unsigned v_div, int i, int j, isl_int n) +{ + isl_int tmp; + int ok; + + isl_int_init(tmp); + isl_int_sub(tmp, bmap->ineq[l][0], bmap->ineq[i][0]); + isl_int_fdiv_r(tmp, tmp, n); + isl_int_add(tmp, tmp, bmap->ineq[i][0]); + isl_int_add(tmp, tmp, bmap->ineq[j][0]); + ok = isl_int_lt(tmp, bmap->ineq[l][1 + v_div + div]); + isl_int_clear(tmp); + + return ok; +} + +/* Given a lower bound constraint at position "l" of "bmap" + * on local variable "div" such that the sum of the constant terms + * of this constraint and the corresponding upper bound is equal to "sum", + * as well as a separate pair of opposite constraints "i" and "j" + * such that the sum of their constant terms is smaller than + * the coefficient of "div" in "l", + * check if this pair can be used to derive a reduced expression + * for the local variable. + * "total" is the total number of variables. + * "v_div" is the position of the first local variable. + * Set *progress if anything is changed. + * + * In particular, let l be the constraint + * + * -n f + g + m n e + c1 >= 0 + * + * The opposite constraint is + * + * n f - g - m n e + c2 >= 0 + * + * with c1 + c2 equal to "sum". + * + * The constraints i and j are of the form + * + * h + c3 >= 0 + * -h + c4 >= 0 + * + * with c3 + c4 < m n. + * First check that h is equal to g for some n greater than "sum". + * The constraints i and j are then of the form + * + * g + c3 >= 0 + * -g + c4 >= 0 + * + * From constraint "l" and its opposite, + * + * g + m n e - c2 <= n f <= g + m n e + c1 + * + * combined with the fact that c1 + c2 < n, the following expression + * can be obtained: + * + * f = floor((g + m n e + c1)/n) = floor((g + c1)/n) + m e + * + * Replacing c1 with + * + * c1 = c3 + (c1 - c3) = c3 + n floor((c1 - c3)/n) + (c1 - c3) % n + * + * results in + * + * f = floor((g + c3 + (c1 - c3) % n)/n) + floor((c1 - c3)/n) + m e + * + * From the constraints i and j, together with c3 + c4 < m n, + * + * 0 <= g + c3 < m n + * + * Since (c1 - c3) % n is non-negative, + * + * 0 <= g + c3 + (c1 - c3) % n + * + * holds as well. However, + * + * g + c3 + (c1 - c3) % n < m n + * + * may not necessarily hold. It is however the case if + * + * c3 + c4 + (c1 - c3) % n < m n + * + * holds, which is checked in is_residue_div_pair. + * + * Given + * + * 0 <= g + c3 + (c1 - c3) % n < m n + * + * also + * + * 0 <= floor((g + c3 + (c1 - c3) % n) / n) < m + * + * holds. + * + * So, + * + * f = floor((g + c3 + (c1 - c3) % n)/n) + floor((c1 - c3)/n) + m e + * + * and + * + * 0 <= floor((g + c3 + (c1 - c3) % n) / n) < m + * + * This means + * + * f - floor((c1 - c3)/n) + * + * is equal to a multiple of m plus a value between 0 and m - 1. + * That is, + * + * e = floor((f - floor((c1 - c3)/n))/m) + * + * Construct the inequality constraint + * + * -n f + m n e + c1 - c3 >= 0 + * + * scale it down to + * + * -f + m e + floor((c1 - c3)/n) >= 0 + * + * and add m - 1, to obtain + * + * -f + m e + floor((c1 - c3)/n) + m - 1 >= 0 + * + * This constraint can then be used by set_div_from_lower_bound_if_better + * to obtain + * + * e = floor((f - floor((c1 - c3)/n))/m) + * + * Adding m - 1 is needed to be able to reuse set_div_from_lower_bound, + * which subtracts this amount from the constraint (by adding it + * to the negated constraint). + */ +static __isl_give isl_basic_map *set_residue_div(__isl_take isl_basic_map *bmap, + int l, isl_int sum, int div, + unsigned v_div, unsigned total, int i, int j, int *progress) +{ + isl_ctx *ctx; + isl_vec *v; + + if (!bmap) + return NULL; + + ctx = isl_basic_map_get_ctx(bmap); + if (!is_residue(bmap->ineq[i], bmap->ineq[l], sum, total, + &ctx->normalize_gcd)) + return bmap; + + if (!is_residue_div_pair(bmap, l, div, v_div, i, j, ctx->normalize_gcd)) + return bmap; + + v = isl_vec_alloc(ctx, 1 + total); + if (!v) + return isl_basic_map_free(bmap); + isl_seq_cpy(v->el, bmap->ineq[l], 1 + total); + isl_seq_sub(v->el, bmap->ineq[i], 1 + total); + scale_down_inequality(v->el, ctx->normalize_gcd, total); + isl_int_add(v->el[0], v->el[0], v->el[1 + v_div + div]); + isl_int_sub_ui(v->el[0], v->el[0], 1); + bmap = set_div_from_lower_bound_if_better(bmap, div, v->el, progress); + isl_vec_free(v); + + return bmap; +} + +/* Given a lower bound constraint at position "l" of "bmap" + * on local variable "div" such that the sum of the constant terms + * of this constraint and the corresponding upper bound is equal to "sum", + * check if some other pair of constraints can be found in "opposite" + * that can be used to derive a reduced expression for the local variable. + * "opposite" describes all pairs of opposite constraints. + * It is an array of size equal to the number of inequality constraints + * with as entries either + * - zero, if the constraint has no opposite, or + * - 1 + the position of the opposite constraint. + * Set *progress if anything is changed. + * + * In particular, let l be the constraint + * + * -n f + g + m n e + c1 >= 0 + * + * The opposite constraint is + * + * n f - g - m n e + c2 >= 0 + * + * with c1 + c2 equal to "sum". + * + * Look for a pair of constraints + * + * g + c3 >= 0 + * -g + c4 >= 0 + * + * with c3 + c4 < m n that can be used to obtain a reduced expression for e. + * First look for any pair of constraints with constant terms + * that satisfy c3 + c4 < m n and then check whether either of them + * can be used in this way. + */ +static __isl_give isl_basic_map *check_for_residue_div( + __isl_take isl_basic_map *bmap, int *opposite, int l, isl_int sum, + int div, int *progress) +{ + int i; + isl_size n, v_div, total; + isl_ctx *ctx; + + v_div = isl_basic_map_var_offset(bmap, isl_dim_div); + total = isl_basic_map_dim(bmap, isl_dim_all); + n = isl_basic_map_n_inequality(bmap); + if (v_div < 0 || total < 0 || n < 0) + return isl_basic_map_free(bmap); + + ctx = isl_basic_map_get_ctx(bmap); + for (i = 0; i < n; ++i) { + int j; + + if (i == l) + continue; + if (!opposite[i]) + continue; + j = opposite[i] - 1; + if (j < i) + continue; + if (j == l) + continue; + if (!isl_int_is_zero(bmap->ineq[i][1 + v_div + div])) + continue; + isl_int_add(ctx->normalize_gcd, + bmap->ineq[i][0], bmap->ineq[j][0]); + if (isl_int_ge(ctx->normalize_gcd, + bmap->ineq[l][1 + v_div + div])) + continue; + bmap = set_residue_div(bmap, l, sum, div, v_div, total, i, j, + progress); + bmap = set_residue_div(bmap, l, sum, div, v_div, total, j, i, + progress); + } + + return bmap; +} + /* Given two constraints "k" and "l" that are opposite to each other, * except for the constant term, check if we can use them * to obtain an expression for one of the hitherto unknown divs or @@ -1708,46 +2044,66 @@ static __isl_give isl_basic_map *check_for_residues( * "sum" is the sum of the constant terms of the constraints. * If this sum is strictly smaller than the coefficient of one * of the divs, then this pair can be used to define the div. - * To avoid the introduction of circular definitions of divs, we - * do not use the pair if the resulting expression would refer to - * any other undefined divs or if any known div is defined in - * terms of the unknown div. + * Use the lower bound of this pair if it is better than + * any previously known expression and + * if there is no risk of introducing circular definitions. + * If, moreover, this coefficient is a non-trivial multiple + * of a value greater than the sum and if some other pair of constraints + * can be found that can be used to eliminate coefficients + * that are not a multiple of this value, then a more simplified + * expression can be obtained. + * "opposite" describes all pairs of opposite constraints. + * It is an array of size equal to the number of inequality constraints + * with as entries either + * - zero, if the constraint has no opposite, or + * - 1 + the position of the opposite constraint. */ static __isl_give isl_basic_map *check_for_div_constraints( - __isl_take isl_basic_map *bmap, int k, int l, isl_int sum, - int *progress) + __isl_take isl_basic_map *bmap, int *opposite, + int k, int l, isl_int sum, int *progress) { int i; unsigned total = isl_basic_map_offset(bmap, isl_dim_div); + isl_size n_div = isl_basic_map_dim(bmap, isl_dim_div); - for (i = 0; i < bmap->n_div; ++i) { - isl_bool set_div; + if (n_div < 0) + return isl_basic_map_free(bmap); + + for (i = 0; i < n_div; ++i) { + int div_set = 0; + int c; if (isl_int_is_zero(bmap->ineq[k][total + i])) continue; - if (isl_int_abs_ge(sum, bmap->ineq[k][total + i])) - continue; - set_div = better_div_constraint(bmap, i, k); - if (set_div >= 0 && set_div) - set_div = ok_to_set_div_from_bound(bmap, i, k); - if (set_div < 0) - return isl_basic_map_free(bmap); - if (!set_div) - break; if (isl_int_is_pos(bmap->ineq[k][total + i])) - bmap = set_div_from_lower_bound(bmap, i, k); + c = k; else - bmap = set_div_from_lower_bound(bmap, i, l); + c = l; + if (isl_int_ge(sum, bmap->ineq[c][total + i])) + continue; + bmap = check_for_residue_div(bmap, opposite, c, sum, i, + &div_set); + bmap = set_div_from_lower_bound_if_better(bmap, i, + bmap->ineq[c], &div_set); + if (!bmap) + return NULL; + if (!div_set) + continue; mark_progress(progress); break; } return bmap; } -/* Look for pairs of constraints that have equal or opposite coefficients. - * For each pair of constraints with equal coefficients, only keep - * the one which imposes the most stringent constraint, i.e., - * the one with the smallest constant term. +/* Exploit the pairs of inequality constraints of "bmap" + * with opposite coefficients. They are described by "opposite", + * an array of size equal to the number of inequality constraints + * with as entries either + * - zero, if the constraint has no opposite, or + * - 1 + the position of the opposite constraint. + * Detect (better) integer division expressions if "detect_divs" is set. + * Set *progress if any progress is made. + * * For each pair of constraints with opposite coefficients, * consider the sum of the constant terms. * If the sum is smaller than zero, then the constraints conflict. @@ -1757,51 +2113,33 @@ static __isl_give isl_basic_map *check_for_div_constraints( * can be used to simplify any other constraints and/or, * if "detect_divs" is set, whether a (better) integer division definition * can be read off from the pair. + * + * Only check each pair once (with k < l). */ -__isl_give isl_basic_map *isl_basic_map_remove_duplicate_constraints( - __isl_take isl_basic_map *bmap, int *progress, int detect_divs) +static __isl_give isl_basic_map *exploit_opposite_constraints( + __isl_take isl_basic_map *bmap, int *opposite, + int *progress, int detect_divs) { - struct isl_constraint_index ci; - int k, l, h; - isl_size total = isl_basic_map_dim(bmap, isl_dim_all); + int k, l; isl_int sum; - if (total < 0 || bmap->n_ineq <= 1) - return bmap; - - if (create_constraint_index(&ci, bmap) < 0) + if (!opposite) return bmap; - - h = isl_seq_get_hash_bits(bmap->ineq[0] + 1, total, ci.bits); - ci.index[h] = &bmap->ineq[0]; - for (k = 1; k < bmap->n_ineq; ++k) { - h = hash_index(&ci, bmap, k); - if (!ci.index[h]) { - ci.index[h] = &bmap->ineq[k]; - continue; - } - l = ci.index[h] - &bmap->ineq[0]; - if (isl_int_lt(bmap->ineq[k][0], bmap->ineq[l][0])) - swap_inequality(bmap, k, l); - isl_basic_map_drop_inequality(bmap, k); - --k; - } isl_int_init(sum); for (k = 0; bmap && k < bmap->n_ineq-1; ++k) { - isl_seq_neg(bmap->ineq[k]+1, bmap->ineq[k]+1, total); - h = hash_index(&ci, bmap, k); - isl_seq_neg(bmap->ineq[k]+1, bmap->ineq[k]+1, total); - if (!ci.index[h]) + if (!opposite[k]) + continue; + l = opposite[k] - 1; + if (l < k) continue; - l = ci.index[h] - &bmap->ineq[0]; isl_int_add(sum, bmap->ineq[k][0], bmap->ineq[l][0]); if (isl_int_is_pos(sum)) { int residue = 0; bmap = check_for_residues(bmap, k, l, sum, &residue); if (detect_divs) - bmap = check_for_div_constraints(bmap, k, l, - sum, progress); + bmap = check_for_div_constraints(bmap, opposite, + k, l, sum, progress); if (!residue) continue; mark_progress(progress); @@ -1821,11 +2159,54 @@ __isl_give isl_basic_map *isl_basic_map_remove_duplicate_constraints( break; } isl_int_clear(sum); + free(opposite); - constraint_index_free(&ci); return bmap; } +/* Look for pairs of constraints that have equal or opposite coefficients. + * Detect (better) integer division expressions if "detect_divs" is set. + * + * For each pair of constraints with equal coefficients, only keep + * the one which imposes the most stringent constraint, i.e., + * the one with the smallest constant term. + * Detect opposite constraints and handle them + * in exploit_opposite_constraints. + */ +__isl_give isl_basic_map *isl_basic_map_remove_duplicate_constraints( + __isl_take isl_basic_map *bmap, int *progress, int detect_divs) +{ + struct isl_constraint_index ci; + int k, l, h; + isl_size total = isl_basic_map_dim(bmap, isl_dim_all); + int *opposite; + + if (total < 0 || bmap->n_ineq <= 1) + return bmap; + + if (create_constraint_index(&ci, bmap) < 0) + return bmap; + + h = isl_seq_get_hash_bits(bmap->ineq[0] + 1, total, ci.bits); + ci.index[h] = &bmap->ineq[0]; + for (k = 1; k < bmap->n_ineq; ++k) { + h = hash_index(&ci, bmap, k); + if (!ci.index[h]) { + ci.index[h] = &bmap->ineq[k]; + continue; + } + l = ci.index[h] - &bmap->ineq[0]; + if (isl_int_lt(bmap->ineq[k][0], bmap->ineq[l][0])) + swap_inequality(bmap, k, l); + isl_basic_map_drop_inequality(bmap, k); + --k; + } + opposite = detect_opposites(&ci, bmap); + constraint_index_free(&ci); + return exploit_opposite_constraints(bmap, opposite, progress, + detect_divs); +} + /* Detect all pairs of inequalities that form an equality. * * isl_basic_map_remove_duplicate_constraints detects at most one such pair. @@ -5636,11 +6017,13 @@ static __isl_give isl_basic_map *isl_basic_map_drop_redundant_divs_ineq( if (defined) set_div = isl_bool_false; else - set_div = ok_to_set_div_from_bound(bmap, i, last_pos); + set_div = ok_to_set_div_from_bound(bmap, i, + bmap->ineq[last_pos]); if (set_div < 0) return isl_basic_map_free(bmap); if (set_div) { - bmap = set_div_from_lower_bound(bmap, i, last_pos); + bmap = set_div_from_lower_bound(bmap, i, + bmap->ineq[last_pos]); return drop_redundant_divs_again(bmap, pairs, 1); } pairs[i] = 0; @@ -6087,8 +6470,14 @@ __isl_give isl_basic_map *isl_basic_map_reduce_coefficients( ISL_F_CLR(bmap, ISL_BASIC_MAP_NO_REDUNDANT); bmap = isl_basic_map_detect_inequality_pairs(bmap, &progress); if (progress) { + isl_bool empty; + bmap = isl_basic_map_gauss(bmap, NULL); - bmap = reduce_coefficients(bmap, &data); + empty = isl_basic_map_plain_is_empty(bmap); + if (empty < 0) + goto error; + if (!empty) + bmap = reduce_coefficients(bmap, &data); bmap = eliminate_divs_eq(bmap, &progress); } } diff --git a/polly/lib/External/isl/isl_test.c b/polly/lib/External/isl/isl_test.c index 7cd51c32d83ac..85bda485790bb 100644 --- a/polly/lib/External/isl/isl_test.c +++ b/polly/lib/External/isl/isl_test.c @@ -1567,63 +1567,6 @@ static int test_simple_hull(struct isl_ctx *ctx) return 0; } -/* Inputs for isl_set_get_simple_fixed_box_hull tests. - * "set" is the input set. - * "offset" is the expected box offset. - * "size" is the expected box size. - */ -static struct { - const char *set; - const char *offset; - const char *size; -} box_hull_tests[] = { - { "{ S[x, y] : 0 <= x, y < 10 }", "{ S[0, 0] }", "{ S[10, 10] }" }, - { "[N] -> { S[x, y] : N <= x, y < N + 10 }", - "[N] -> { S[N, N] }", "{ S[10, 10] }" }, - { "{ S[x, y] : 0 <= x + y, x - y < 10 }", - "{ S[0, -4] }", "{ S[10, 9] }" }, - { "{ [i=0:10] : exists (e0, e1: 3e1 >= 1 + 2e0 and " - "8e1 <= -1 + 5i - 5e0 and 2e1 >= 1 + 2i - 5e0) }", - "{ [3] }", "{ [8] }" }, - { "[N] -> { [w = 0:17] : exists (e0: w < 2N and " - "-1 + w <= e0 <= w and 2e0 >= N + w and w <= 2e0 <= 15 + w) }", - "[N] -> { [N] }", "{ [9] }" }, -}; - -/* Perform basic isl_set_get_simple_fixed_box_hull tests. - */ -static int test_box_hull(struct isl_ctx *ctx) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(box_hull_tests); ++i) { - const char *str; - isl_stat r; - isl_set *set; - isl_multi_aff *offset; - isl_multi_val *size; - isl_fixed_box *box; - - set = isl_set_read_from_str(ctx, box_hull_tests[i].set); - box = isl_set_get_simple_fixed_box_hull(set); - offset = isl_fixed_box_get_offset(box); - size = isl_fixed_box_get_size(box); - str = box_hull_tests[i].offset; - r = multi_aff_check_plain_equal(offset, str); - str = box_hull_tests[i].size; - if (r >= 0) - r = multi_val_check_plain_equal(size, str); - isl_multi_aff_free(offset); - isl_multi_val_free(size); - isl_fixed_box_free(box); - isl_set_free(set); - if (r < 0) - return -1; - } - - return 0; -} - void test_convex_hull_case(struct isl_ctx *ctx, const char *name) { char *filename; @@ -10800,7 +10743,6 @@ struct { { "recession cone", &test_recession_cone }, { "affine hull", &test_affine_hull }, { "simple_hull", &test_simple_hull }, - { "box hull", &test_box_hull }, { "coalesce", &test_coalesce }, { "factorize", &test_factorize }, { "subset", &test_subset }, diff --git a/polly/lib/External/isl/isl_test2.cc b/polly/lib/External/isl/isl_test2.cc index 62ffa5a6a5ed7..0e03a7b3b67c6 100644 --- a/polly/lib/External/isl/isl_test2.cc +++ b/polly/lib/External/isl/isl_test2.cc @@ -101,6 +101,9 @@ struct ternary { * The spelling depends on the isl type and * in particular on whether an equality method is available or * whether only obvious equality can be tested. + * + * Since isl::multi_val has both an is_equal and a plain_is_equal, + * use a specific overload for isl::multi_val that calls is_equal. */ template ().is_equal(std::declval()))>::type = true> @@ -114,6 +117,10 @@ static bool is_equal(const T &a, const T &b) { return a.plain_is_equal(b); } +static bool is_equal(const isl::multi_val &a, const isl::multi_val &b) +{ + return a.is_equal(b); +} /* A helper macro for throwing an isl::exception_invalid with message "msg". */ @@ -431,6 +438,52 @@ static void test_fixed_power(isl::ctx ctx) }); } +/* Perform basic simple fixed box hull tests. + */ +static void test_box_hull(isl::ctx ctx) +{ + C(&isl::set::simple_fixed_box_hull, { + { "{ S[x, y] : 0 <= x, y < 10 }", + "{ offset: { S[0, 0] }, size: { S[10, 10] } }" }, + { "[N] -> { S[x, y] : N <= x, y < N + 10 }", + "{ offset: [N] -> { S[(N), (N)] }, size: { S[10, 10] } }" }, + { "{ S[x, y] : 0 <= x + y, x - y < 10 }", + "{ offset: { S[0, -4] }, size: { S[10, 9] } }" }, + { "{ [i=0:10] : exists (e0, e1: 3e1 >= 1 + 2e0 and " + "8e1 <= -1 + 5i - 5e0 and 2e1 >= 1 + 2i - 5e0) }", + "{ offset: { [3] }, size: { [8] } }" }, + { "[N] -> { [w = 0:17] : exists (e0: w < 2N and " + "-1 + w <= e0 <= w and 2e0 >= N + w and w <= 2e0 <= 15 + w) }", + "{ offset: [N] -> { [N] }, size: { [9] } }" }, + { "[N] -> { [N//2:N//2+4] }", + "{ offset: [N] -> { [N//2] }, size: { [5] } }" }, + { "[N] -> { [N//2+N//3:N//2+N//3+4] }", + "{ offset: [N] -> { [N//2+N//3] }, size: { [5] } }" }, + { "[N] -> { [a=0:59, b=0:1] : 15N - a <= 60b <= 59 + 15N - a and " + "-22 + 20b <= 20*floor((-1 + 15N - a)/60) < 20b and " + "60*floor((-1 + 15N - a)/60) <= -46 + 15N - a }", + "{ offset: [N] -> { [(15*((N) mod 4)), (floor((N)/4))] }, " + "size: { [15, 1] } }" }, + { "{ [i=-3:7] : i mod 4 = 0 }", + "{ offset: { [(0)] }, size: { [5] } }" }, + { "[N] -> { [i, N - 4i] : -14 + N <= 16i <= 1 + N }", + "{ offset: [N] -> { [(floor((1 + N)/16)), " + "(4 + N + 4*floor((-2 - N)/16))] }, " + "size: { [1, 1] } }" }, + }); + + C(&isl::map::range_simple_fixed_box_hull, { + { "{ [N] -> [i, N - 4i] : -14 + N <= 16i <= 1 + N }", + "{ offset: { [N] -> [(floor((1 + N)/16)), " + "(4 + N + 4*floor((-2 - N)/16))] }, " + "size: { [1, 1] } }" }, + { "{ [N] -> [i, j] : 4j = N - i and -1 + 3N <= 4i <= 14 + 3N }", + "{ offset: { [N] -> [(4 + N + 4*floor((-2 - N)/16)), " + "(floor((1 + N)/16))] }, " + "size: { [1, 1] } }" }, + }); +} + /* Perform some basic intersection tests. */ static void test_intersect(isl::ctx ctx) @@ -913,6 +966,7 @@ static std::vector> tests = { "conversion", &test_conversion }, { "preimage", &test_preimage }, { "fixed power", &test_fixed_power }, + { "box hull", &test_box_hull }, { "intersect", &test_intersect }, { "lexmin", &test_lexmin }, { "gist", &test_gist }, diff --git a/polly/lib/External/isl/isl_union_map.c b/polly/lib/External/isl/isl_union_map.c index 5a0f40ecc391c..c8393f5e36403 100644 --- a/polly/lib/External/isl/isl_union_map.c +++ b/polly/lib/External/isl/isl_union_map.c @@ -2198,6 +2198,45 @@ __isl_give isl_union_set *isl_union_set_simple_hull( return isl_union_map_simple_hull(uset); } +/* Compute a superset of the convex hull of "map" that is described + * by only the constraints in the constituents of "map" and + * return the result as an isl_map. + * In particular, the result is composed of constraints that appear + * in each of the basic maps of "map". + */ +static __isl_give isl_map *isl_map_plain_unshifted_simple_hull_map( + __isl_take isl_map *map) +{ + return isl_map_from_basic_map(isl_map_plain_unshifted_simple_hull(map)); +} + +/* For each map in "umap", compute a superset of the convex hull + * that is described by only the constraints in the constituents of that map and + * collect the results. + * In particular, each result is composed of constraints that appear + * in each of the basic maps of the corresponding map. + */ +__isl_give isl_union_map *isl_union_map_plain_unshifted_simple_hull( + __isl_take isl_union_map *umap) +{ + return total(umap, &isl_map_plain_unshifted_simple_hull_map); +} + +/* For each set in "uset", compute a superset of the convex hull + * that is described by only the constraints in the constituents of that set and + * collect the results. + * In particular, each result is composed of constraints that appear + * in each of the basic sets of the corresponding set. + */ +__isl_give isl_union_set *isl_union_set_plain_unshifted_simple_hull( + __isl_take isl_union_set *uset) +{ + isl_union_map *umap; + + umap = isl_union_map_plain_unshifted_simple_hull(uset_to_umap(uset)); + return uset_from_umap(umap); +} + static __isl_give isl_union_map *inplace(__isl_take isl_union_map *umap, __isl_give isl_map *(*fn)(__isl_take isl_map *)) { diff --git a/polly/lib/External/isl/isl_val.c b/polly/lib/External/isl/isl_val.c index 8b77622d7fb2e..8baafe2f364df 100644 --- a/polly/lib/External/isl/isl_val.c +++ b/polly/lib/External/isl/isl_val.c @@ -1589,6 +1589,17 @@ __isl_give isl_val *isl_val_zero_on_domain(__isl_take isl_local_space *ls) #include #include +/* Is "mv1" equal to "mv2"? + * + * Call the generic isl_multi_val_plain_is_equal, which compares values + * using isl_val_plain_is_equal, i.e., isl_val_eq. + */ +isl_bool isl_multi_val_is_equal(__isl_keep isl_multi_val *mv1, + __isl_keep isl_multi_val *mv2) +{ + return isl_multi_val_plain_is_equal(mv1, mv2); +} + /* Does "mv" consist of only zeros? */ isl_bool isl_multi_val_is_zero(__isl_keep isl_multi_val *mv) diff --git a/polly/lib/External/isl/test_inputs/codegen/polly.c b/polly/lib/External/isl/test_inputs/codegen/polly.c new file mode 100644 index 0000000000000..fd6a9139842ff --- /dev/null +++ b/polly/lib/External/isl/test_inputs/codegen/polly.c @@ -0,0 +1,19 @@ +if (p_0 >= p_1 + 1) { + for (int c0 = 0; c0 <= p_1 - 4 * floord(p_1 + 2, 4); c0 += 1) + Stmt2(c0); + if (4 * floord(p_1 + 2, 4) >= p_1 + 1) + for (int c0 = 0; c0 <= p_1 - 4 * floord(p_1 + 2, 4) + 4; c0 += 1) + Stmt2(c0); +} else if (p_0 >= p_1 + 4 * floord(p_0 - p_1, 4) + 1) { + for (int c0 = 0; c0 <= p_0 - 4 * floord(p_0 + 2, 4); c0 += 1) + Stmt2(c0); + if (4 * floord(p_0 + 2, 4) >= p_0 + 1) + for (int c0 = 0; c0 <= p_0 - 4 * floord(p_0 + 2, 4) + 4; c0 += 1) + Stmt2(c0); +} else if (4 * floord(p_0 + 2, 4) >= p_0 + 1) { + for (int c0 = 0; c0 <= p_0 - 4 * floord(p_0 + 2, 4) + 4; c0 += 1) + Stmt2(c0); +} else { + for (int c0 = 0; c0 <= p_0 - 4 * floord(p_0 + 2, 4); c0 += 1) + Stmt2(c0); +} diff --git a/polly/lib/External/isl/test_inputs/codegen/polly.st b/polly/lib/External/isl/test_inputs/codegen/polly.st new file mode 100644 index 0000000000000..5c5b519d5499f --- /dev/null +++ b/polly/lib/External/isl/test_inputs/codegen/polly.st @@ -0,0 +1,7 @@ +# A Polly generated test case that would cause a failure +# in isl_basic_map_reduce_coefficients in an earlier version of isl. +domain: "[p_0, p_1] -> { Stmt2[i0] : i0 >= 0 and ((p_1 < p_0 and 4*floor((2 + p_1)/4) <= p_1 - i0) or (p_1 >= p_0 and 4*floor((p_0 - p_1)/4) < p_0 - p_1 and 4*floor((2 + p_0)/4) <= p_0 - i0) or (p_1 < p_0 and p_1 < 4*floor((2 + p_1)/4) <= 4 + p_1 - i0 and 4*floor((p_0 - p_1)/4) < p_0 - p_1) or (p_1 >= p_0 and 4*floor((p_0 - p_1)/4) < p_0 - p_1 and p_0 < 4*floor((2 + p_0)/4) <= 4 + p_0 - i0) or ((2 + p_0) mod 4 = 6 + p_1 + 4*floor((-1 - p_1)/4) and p_1 >= p_0 and -4 - p_1 + i0 <= 4*floor((-1 - p_1)/4) <= -3 - p_1) or ((2 + p_0) mod 4 = 2 + p_1 + 4*floor((1 - p_1)/4) and p_1 >= p_0 and 4*floor((1 - p_1)/4) >= -4 - p_1 + i0 and 4*floor((1 - p_1)/4) < -p_1) or ((-p_0 + p_1) mod 4 = 0 and p_1 <= -4 + p_0 and p_1 < 4*floor((2 + p_1)/4) <= 4 + p_1 - i0)) }" +child: + context: "[p_0, p_1] -> { [] : p_0 >= -2147483648 and p_0 <= 2147483647 and p_1 >= -2147483648 and p_1 <= 2147483647 }" + child: + schedule: "[p_0, p_1] -> [{ Stmt2[i0] -> [(i0)] }]" diff --git a/polly/lib/External/isl/test_inputs/codegen/polly2.c b/polly/lib/External/isl/test_inputs/codegen/polly2.c new file mode 100644 index 0000000000000..6cf990c3ae216 --- /dev/null +++ b/polly/lib/External/isl/test_inputs/codegen/polly2.c @@ -0,0 +1,2 @@ +for (int c0 = 0; c0 <= 1; c0 += 1) + Stmt_for_body9_us94_last(c0); diff --git a/polly/lib/External/isl/test_inputs/codegen/polly2.st b/polly/lib/External/isl/test_inputs/codegen/polly2.st new file mode 100644 index 0000000000000..a8746e655ad22 --- /dev/null +++ b/polly/lib/External/isl/test_inputs/codegen/polly2.st @@ -0,0 +1,12 @@ +# A Polly generated test case that would cause a failure +# to handle void expression in an earlier version of isl. +domain: "[e] -> { Stmt_for_body9_us94_last[i0] : 0 <= i0 <= 1; Stmt_cond_false30_us97[i0] : e = 0 and 0 <= i0 <= 1 }" +child: + context: "[e] -> { [] : (e > 0 and e <= 127) or (e >= -128 and e < 0) }" + child: + schedule: "[e] -> [{ Stmt_for_body9_us94_last[i0] -> [(i0)]; Stmt_cond_false30_us97[i0] -> [(i0)] }]" + child: + sequence: + - filter: "[e] -> { Stmt_for_body9_us94_last[i0] }" + - filter: "[e] -> { Stmt_cond_false30_us97[i0] }" + diff --git a/polly/lib/Support/DumpFunctionPass.cpp b/polly/lib/Support/DumpFunctionPass.cpp index 9565e2156aee6..4483b86ca2583 100644 --- a/polly/lib/Support/DumpFunctionPass.cpp +++ b/polly/lib/Support/DumpFunctionPass.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "polly/Support/DumpFunctionPass.h" +#include "polly/Support/PollyDebug.h" #include "llvm/IR/Module.h" #include "llvm/IR/PassInstrumentation.h" #include "llvm/Support/Debug.h" @@ -35,8 +36,8 @@ static void runDumpFunction(llvm::Function &F, StringRef Suffix) { StringRef ModuleName = M->getName(); StringRef Stem = sys::path::stem(ModuleName); std::string Dumpfile = (Twine(Stem) + "-" + FName + Suffix + ".ll").str(); - LLVM_DEBUG(dbgs() << "Dumping function '" << FName << "' to '" << Dumpfile - << "'...\n"); + POLLY_DEBUG(dbgs() << "Dumping function '" << FName << "' to '" << Dumpfile + << "'...\n"); ValueToValueMapTy VMap; auto ShouldCloneDefinition = [&F](const GlobalValue *GV) -> bool { @@ -46,7 +47,7 @@ static void runDumpFunction(llvm::Function &F, StringRef Suffix) { Function *NewF = cast(VMap.lookup(&F)); assert(NewF && "Expected selected function to be cloned"); - LLVM_DEBUG(dbgs() << "Global DCE...\n"); + POLLY_DEBUG(dbgs() << "Global DCE...\n"); // Stop F itself from being pruned GlobalValue::LinkageTypes OrigLinkage = NewF->getLinkage(); @@ -67,7 +68,7 @@ static void runDumpFunction(llvm::Function &F, StringRef Suffix) { // Restore old linkage NewF->setLinkage(OrigLinkage); - LLVM_DEBUG(dbgs() << "Write to file '" << Dumpfile << "'...\n"); + POLLY_DEBUG(dbgs() << "Write to file '" << Dumpfile << "'...\n"); std::unique_ptr Out; std::error_code EC; @@ -79,7 +80,7 @@ static void runDumpFunction(llvm::Function &F, StringRef Suffix) { CM->print(Out->os(), nullptr); Out->keep(); - LLVM_DEBUG(dbgs() << "Dump file " << Dumpfile << " written successfully\n"); + POLLY_DEBUG(dbgs() << "Dump file " << Dumpfile << " written successfully\n"); } } // namespace diff --git a/polly/lib/Support/DumpModulePass.cpp b/polly/lib/Support/DumpModulePass.cpp index 2eaa0707fe571..ab413e502e27f 100644 --- a/polly/lib/Support/DumpModulePass.cpp +++ b/polly/lib/Support/DumpModulePass.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "polly/Support/DumpModulePass.h" +#include "polly/Support/PollyDebug.h" #include "llvm/IR/Module.h" #include "llvm/Support/Debug.h" #include "llvm/Support/FileSystem.h" @@ -33,7 +34,7 @@ static void runDumpModule(llvm::Module &M, StringRef Filename, bool IsSuffix) { } else { Dumpfile = Filename.str(); } - LLVM_DEBUG(dbgs() << "Dumping module to " << Dumpfile << '\n'); + POLLY_DEBUG(dbgs() << "Dumping module to " << Dumpfile << '\n'); std::unique_ptr Out; std::error_code EC; diff --git a/polly/test/CodeGen/OpenMP/issue179135.ll b/polly/test/CodeGen/OpenMP/issue179135.ll new file mode 100644 index 0000000000000..77bb86dde23df --- /dev/null +++ b/polly/test/CodeGen/OpenMP/issue179135.ll @@ -0,0 +1,32 @@ +; RUN: opt %loadNPMPolly '--passes=polly-custom' --polly-parallel -S < %s | FileCheck %s + +; https://github.com/llvm/llvm-project/issues/179135 +; CHECK: @func_polly_subfn( + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" + +define void @func(ptr %arg, i32 %arg1) { +bb: + br label %bb2 + +bb2: ; preds = %bb9, %bb + %i = phi i64 [ 0, %bb ], [ %i10, %bb9 ] + br label %bb3 + +bb3: ; preds = %bb3, %bb2 + %i4 = phi i64 [ 0, %bb2 ], [ %i7, %bb3 ] + %i5 = phi i32 [ 0, %bb2 ], [ %arg1, %bb3 ] + %i6 = getelementptr i32, ptr %arg, i64 %i + store i32 %i5, ptr %i6, align 4 + %i7 = add i64 %i4, 1 + %i8 = icmp eq i64 %i4, 1 + br i1 %i8, label %bb9, label %bb3 + +bb9: ; preds = %bb3 + %i10 = add i64 %i, 1 + %i11 = icmp eq i64 %i, 1 + br i1 %i11, label %bb12, label %bb2 + +bb12: ; preds = %bb9 + ret void +} diff --git a/polly/test/CodeGen/empty_domain_in_context.ll b/polly/test/CodeGen/empty_domain_in_context.ll deleted file mode 100644 index f6c39eb0517bc..0000000000000 --- a/polly/test/CodeGen/empty_domain_in_context.ll +++ /dev/null @@ -1,86 +0,0 @@ -; RUN: opt %loadNPMPolly '-passes=polly-custom' -S < %s | FileCheck %s -; -; llvm.org/PR35362 -; isl codegen does not allow to generate isl_ast_expr from pw_aff which have an -; empty domain. This happens in this case because the pw_aff's domain is -; excluded by the SCoP's parameter context. - -target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" - -@c = external local_unnamed_addr global i8 -@a = external local_unnamed_addr global i16 -@b = external local_unnamed_addr global i8 - -define void @fn1() { -entry: - %a.promoted = load i16, ptr @a - br label %for.cond - -for.cond: ; preds = %for.cond3.for.end_crit_edge, %entry - %inc.lcssa17 = phi i16 [ 0, %for.cond3.for.end_crit_edge ], [ %a.promoted, %entry ] - br label %for.body - -for.body: ; preds = %for.cond - %conv = zext i16 %inc.lcssa17 to i32 - %div = udiv i32 -286702568, %conv - br i1 undef, label %if.end, label %if.then - -if.then: ; preds = %for.body - unreachable - -if.end: ; preds = %for.body - br label %for.body5.lr.ph - -for.body5.lr.ph: ; preds = %if.end - %tmp = load i8, ptr @b, align 1 - %cmp = icmp eq i32 %div, 1 - br i1 %cmp, label %for.body5.lr.ph.split.us, label %for.body5.lr.ph.split - -for.body5.lr.ph.split.us: ; preds = %for.body5.lr.ph - br label %lor.end.us.peel - -lor.end.us.peel: ; preds = %for.body5.lr.ph.split.us - %inc.us.peel = add i16 %inc.lcssa17, 1 - br i1 false, label %for.cond3.for.end_crit_edge, label %for.body5.us.peel.next - -for.body5.us.peel.next: ; preds = %lor.end.us.peel - br label %lor.end.us - -lor.end.us: ; preds = %lor.end.us, %for.body5.us.peel.next - %tmp1 = phi i16 [ %inc.us.peel, %for.body5.us.peel.next ], [ %inc.us, %lor.end.us ] - %inc.us = add i16 %tmp1, 1 - %tobool4.us = icmp eq i16 %inc.us, 0 - br i1 %tobool4.us, label %for.cond3.for.end_crit_edge, label %lor.end.us - -for.body5.lr.ph.split: ; preds = %for.body5.lr.ph - br label %lor.end.peel - -lor.end.peel: ; preds = %for.body5.lr.ph.split - %inc.peel = add i16 %inc.lcssa17, 1 - br i1 false, label %for.cond3.for.end_crit_edge, label %for.body5.peel.next - -for.body5.peel.next: ; preds = %lor.end.peel - br label %lor.end - -lor.end: ; preds = %lor.end, %for.body5.peel.next - %tmp2 = phi i16 [ %inc.peel, %for.body5.peel.next ], [ %inc, %lor.end ] - %inc = add i16 %tmp2, 1 - %tobool4 = icmp eq i16 %inc, 0 - br i1 %tobool4, label %for.cond3.for.end_crit_edge, label %lor.end - -for.cond3.for.end_crit_edge: ; preds = %lor.end, %lor.end.peel, %lor.end.us, %lor.end.us.peel - %tmp3 = phi i8 [ %tmp, %lor.end.us.peel ], [ %tmp, %lor.end.peel ], [ %tmp, %lor.end.us ], [ %tmp, %lor.end ] - store i8 4, ptr @c - br label %for.cond -} - - -; The reference to @b should have been generated from an isl_ast_expr. -; Because isl is unable to generate it in this case, the code generator -; resorted to use the pointer argument of %tmp = load ... . -; It is not important since this code will never be executed. - -; CHECK: polly.stmt.lor.end.us.peel: -; CHECK-NEXT: %tmp_p_scalar_2 = load i8, ptr @b -; CHECK-NEXT: store i8 %tmp_p_scalar_2, ptr %tmp3.phiops -; CHECK-NEXT: br label %polly.merge diff --git a/utils/bazel/MODULE.bazel.lock b/utils/bazel/MODULE.bazel.lock index 7070fd2fa9c61..b01e8474f70e0 100644 --- a/utils/bazel/MODULE.bazel.lock +++ b/utils/bazel/MODULE.bazel.lock @@ -234,7 +234,7 @@ "moduleExtensions": { "//:extensions.bzl%llvm_repos_extension": { "general": { - "bzlTransitiveDigest": "9jGazpNxASw0pQCCKAMsxGYnVBJH8Mkddp3w7yRm6eU=", + "bzlTransitiveDigest": "DqyjXvFpPyfsmyt58EuR0v0Xy+nPN74iTGxjOW99OcQ=", "usagesDigest": "X0yUkkWyxQ2Y5oZVDkRSE/K4YkDWo1IjhHsL+1weKyU=", "recordedFileInputs": {}, "recordedDirentsInputs": {}, @@ -300,7 +300,8 @@ "repoRuleId": "@@bazel_tools//tools/build_defs/repo:http.bzl%http_archive", "attributes": { "urls": [ - "https://versaweb.dl.sourceforge.net/project/perfmon2/libpfm4/libpfm-4.13.0.tar.gz" + "https://versaweb.dl.sourceforge.net/project/perfmon2/libpfm4/libpfm-4.13.0.tar.gz", + "https://sourceforge.net/projects/perfmon2/files/libpfm4/libpfm-4.13.0.tar.gz" ], "sha256": "d18b97764c755528c1051d376e33545d0eb60c6ebf85680436813fa5b04cc3d1", "strip_prefix": "libpfm-4.13.0", diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 83b752ce1214b..ae7228c52d3c0 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -2339,6 +2339,7 @@ libc_support_library( name = "__support_math_acosh_float_constants", hdrs = ["src/__support/math/acosh_float_constants.h"], deps = [ + ":__support_macros_attributes", ":__support_macros_config", ], ) @@ -2831,6 +2832,7 @@ libc_support_library( name = "__support_math_exp_float_constants", hdrs = ["src/__support/math/exp_float_constants.h"], deps = [ + ":__support_macros_attributes", ":__support_macros_config", ], ) @@ -2908,6 +2910,29 @@ libc_support_library( ], ) +libc_support_library( + name = "__support_math_f16fmaf", + hdrs = ["src/__support/math/f16fmaf.h"], + deps = [ + ":__support_common", + ":__support_fputil_fma", + ":__support_macros_config", + ":llvm_libc_macros_float16_macros", + ], +) + +libc_support_library( + name = "__support_math_f16fmaf128", + hdrs = ["src/__support/math/f16fmaf128.h"], + deps = [ + ":__support_common", + ":__support_fputil_fma", + ":__support_macros_config", + ":llvm_libc_macros_float16_macros", + ":llvm_libc_types_float128", + ], +) + libc_support_library( name = "__support_math_f16fmal", hdrs = ["src/__support/math/f16fmal.h"], @@ -2919,6 +2944,16 @@ libc_support_library( ], ) +libc_support_library( + name = "__support_math_ffmal", + hdrs = ["src/__support/math/ffmal.h"], + deps = [ + ":__support_common", + ":__support_fputil_fma", + ":__support_macros_config", + ], +) + libc_support_library( name = "__support_math_frexpf128", hdrs = ["src/__support/math/frexpf128.h"], @@ -3476,6 +3511,21 @@ libc_support_library( ], ) +libc_support_library( + name = "__support_math_sqrtf128", + hdrs = ["src/__support/math/sqrtf128.h"], + deps = [ + ":__support_common", + ":__support_cpp_bit", + ":__support_fputil_fenv_impl", + ":__support_fputil_fp_bits", + ":__support_fputil_rounding_mode", + ":__support_macros_optimization", + ":__support_uint128", + ":llvm_libc_types_float128", + ], +) + libc_support_library( name = "__support_math_logf16", hdrs = ["src/__support/math/logf16.h"], @@ -4438,14 +4488,14 @@ libc_math_function( libc_math_function( name = "f16fmaf", additional_deps = [ - ":__support_fputil_fma", + ":__support_math_f16fmaf", ], ) libc_math_function( name = "f16fmaf128", additional_deps = [ - ":__support_fputil_fma", + ":__support_math_f16fmaf128", ], ) @@ -4543,7 +4593,7 @@ libc_math_function( libc_math_function( name = "ffmal", additional_deps = [ - ":__support_fputil_fma", + ":__support_math_ffmal", ], ) @@ -5401,7 +5451,7 @@ libc_math_function( libc_math_function( name = "sqrtf128", additional_deps = [ - ":__support_fputil_sqrt", + ":__support_math_sqrtf128", ], ) diff --git a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel index 56e64f48d29ad..47222860ea494 100644 --- a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel @@ -138,6 +138,7 @@ expand_template( # Defaults that could be configurable if needed "#cmakedefine01 LLDB_ENABLE_POSIX": "#define LLDB_ENABLE_POSIX 1", + "#cmakedefine01 LLDB_ENABLE_PROTOCOL_SERVERS": "#define LLDB_ENABLE_PROTOCOL_SERVERS 1", "#cmakedefine LLDB_GLOBAL_INIT_DIRECTORY R\"(${LLDB_GLOBAL_INIT_DIRECTORY})\"": "#define LLDB_GLOBAL_INIT_DIRECTORY \"\"", "${LLDB_INSTALL_LIBDIR_BASENAME}": "lib", "${LLDB_BUG_REPORT_URL}": "", @@ -285,11 +286,10 @@ cc_library( name = "DataFormatters", srcs = glob([ "source/DataFormatters/**/*.cpp", - "source/DataFormatters/**/*.h", ]), hdrs = glob(["include/lldb/DataFormatters/**/*.h"]), includes = ["include"], - textual_hdrs = glob(["source/DataFormatters/**/*.def"]), + textual_hdrs = glob(["include/lldb/DataFormatters/**/*.def"]), deps = [ ":CoreHeaders", ":Headers", @@ -758,6 +758,27 @@ cc_library( includes = ["include"], ) +cc_library( + name = "ProtocolHeaders", + hdrs = glob(["include/lldb/Protocol/**/*.h"]), + includes = ["include"], + deps = [ + ":Headers", + "//llvm:Telemetry", + ], +) + +cc_library( + name = "ProtocolMCP", + srcs = glob(["source/Protocol/MCP/*.cpp"]), + deps = [ + ":Host", + ":ProtocolHeaders", + ":Utility", + "//llvm:Support", + ], +) + cc_library( name = "Utility", srcs = glob(["source/Utility/**/*.cpp"]), diff --git a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel index 769f9f8bf9933..830fe47da20df 100644 --- a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel @@ -136,6 +136,22 @@ cc_library( ], ) +cc_library( + name = "PluginProtocolServerMCP", + srcs = glob(["Protocol/MCP/*.cpp"]), + hdrs = glob(["Protocol/MCP/*.h"]), + deps = [ + "//lldb:CoreHeaders", + "//lldb:Headers", + "//lldb:Host", + "//lldb:InterpreterHeaders", + "//lldb:ProtocolHeaders", + "//lldb:ProtocolMCP", + "//lldb:Utility", + "//llvm:Support", + ], +) + cc_library( name = "PluginTypeSystemClang", srcs = glob(["TypeSystem/Clang/*.cpp"]), diff --git a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl index 2a8bba52c2a6a..acbbb6f440c8b 100644 --- a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl +++ b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/plugin_config.bzl @@ -71,6 +71,7 @@ DEFAULT_PLUGINS = [ "ProcessElfCore", "ProcessMachCore", "ProcessMinidump", + "ProtocolServerMCP", "RegisterTypeBuilderClang", "ScriptedProcess", "StructuredDataDarwinLog", diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index e83a237a5397f..22d562260537b 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -501,13 +501,28 @@ cc_library( ) cc_library( - name = "BinaryFormat", - srcs = glob([ - "lib/BinaryFormat/*.cpp", - ]), - hdrs = glob([ - "include/llvm/BinaryFormat/*.h", + name = "BinaryFormatELF", + srcs = [ + "include/llvm/TargetParser/Triple.h", + "lib/BinaryFormat/ELF.cpp", + ], + hdrs = ["include/llvm/BinaryFormat/ELF.h"], + copts = llvm_copts, + includes = ["include"], + textual_hdrs = glob([ + "include/llvm/BinaryFormat/*.def", + "include/llvm/BinaryFormat/ELFRelocs/*.def", ]), + deps = [":Support"], +) + +cc_library( + name = "BinaryFormat", + srcs = glob( + include = ["lib/BinaryFormat/*.cpp"], + exclude = ["lib/BinaryFormat/ELF.cpp"], + ), + hdrs = glob(["include/llvm/BinaryFormat/*.h"]), copts = llvm_copts, includes = ["include"], textual_hdrs = glob([ @@ -515,6 +530,7 @@ cc_library( "include/llvm/BinaryFormat/ELFRelocs/*.def", ]), deps = [ + ":BinaryFormatELF", ":PPCTargetParser", ":Support", ":TargetParser", @@ -1507,6 +1523,13 @@ td_library( ]), ) +td_library( + name = "WebAssemblyTargetTdFiles", + srcs = glob([ + "lib/Target/WebAssembly/**/*.td", + ]), +) + gentbl_cc_library( name = "RISCVTargetParserDefGen", tbl_outs = {"include/llvm/TargetParser/RISCVTargetParserDef.inc": ["-gen-riscv-target-def"]}, @@ -1545,9 +1568,7 @@ cc_library( cc_library( name = "TargetParser", srcs = glob( - [ - "lib/TargetParser/*.cpp", - ], + include = ["lib/TargetParser/*.cpp"], exclude = ["lib/TargetParser/PPCTargetParser.cpp"], ) + select({ "@platforms//os:windows": glob([ @@ -1557,9 +1578,7 @@ cc_library( "lib/TargetParser/Unix/*.inc", ]), }), - hdrs = glob([ - "include/llvm/TargetParser/*.h", - ]), + hdrs = glob(["include/llvm/TargetParser/*.h"]), copts = llvm_copts, includes = ["include"], textual_hdrs = [ @@ -1572,6 +1591,7 @@ cc_library( "include/llvm/TargetParser/*.def", ]), deps = [ + ":BinaryFormatELF", ":Support", ":config", ], @@ -3321,6 +3341,10 @@ llvm_target_lib_list = [lib for lib in [ "name": "WebAssembly", "short_name": "WebAssembly", "tbl_outs": [ + ( + ["-gen-register-bank"], + "lib/Target/WebAssembly/WebAssemblyGenRegisterBank.inc", + ), ( ["-gen-disassembler"], "lib/Target/WebAssembly/WebAssemblyGenDisassemblerTables.inc", @@ -3368,6 +3392,9 @@ llvm_target_lib_list = [lib for lib in [ "lib/Target/WebAssembly/WebAssemblyGenSDNodeInfo.inc", ), ], + "tbl_deps": [ + ":webassembly_isel_target_gen", + ], }, { "name": "X86", @@ -3429,6 +3456,13 @@ llvm_target_lib_list = [lib for lib in [ ], "lib/Target/X86/X86GenPreLegalizeGICombiner.inc", ), + ( + [ + "-gen-global-isel-combiner", + "-combiners=X86PostLegalizerCombiner", + ], + "lib/Target/X86/X86GenPostLegalizeGICombiner.inc", + ), ( ["-gen-callingconv"], "lib/Target/X86/X86GenCallingConv.inc", @@ -3667,6 +3701,28 @@ gentbl_cc_library( ], ) +gentbl_cc_library( + name = "webassembly_isel_target_gen", + strip_include_prefix = "lib/Target/WebAssembly", + tbl_outs = { + "lib/Target/WebAssembly/WebAssemblyGenGlobalISel.inc": ["-gen-global-isel"], + "lib/Target/WebAssembly/WebAssemblyGenPreLegalizeGICombiner.inc": [ + "-gen-global-isel-combiner", + "-combiners=WebAssemblyPreLegalizerCombiner", + ], + "lib/Target/WebAssembly/WebAssemblyGenPostLegalizeGICombiner.inc": [ + "-gen-global-isel-combiner", + "-combiners=WebAssemblyPostLegalizerCombiner", + ], + }, + tblgen = ":llvm-tblgen", + td_file = "lib/Target/WebAssembly/WebAssemblyGISel.td", + deps = [ + ":CommonTargetTdFiles", + ":WebAssemblyTargetTdFiles", + ], +) + [[ [gentbl_cc_library( name = target["name"] + "CommonTableGen", @@ -5867,6 +5923,7 @@ cc_binary( ":AllTargetsDisassemblers", ":Core", ":DebugInfoDWARF", + ":DebugInfoPDB", ":Demangle", ":IPO", ":MC", diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 8907f8827bb47..f68e1f2ff801a 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -15,6 +15,7 @@ load( "cc_headers_only", "if_cuda_available", "mlir_c_api_cc_library", + "nanobind_pyi_genrule", ) load(":linalggen.bzl", "genlinalg") load(":tblgen.bzl", "gentbl_cc_library", "td_library") @@ -1419,6 +1420,30 @@ cc_binary( ], ) +##---------------------------------------------------------------------------## +# Python stub generation for native extensions. +##---------------------------------------------------------------------------## + +py_binary( + name = "stubgen_runner", + srcs = ["stubgen_runner.py"], + data = ["@nanobind//:src/stubgen.py"], + visibility = ["//visibility:private"], + deps = ["@rules_python//python/runfiles"], +) + +nanobind_pyi_genrule( + name = "_mlir_pyi", + outs = [ + "_mlir/__init__.pyi", + "_mlir/ir.pyi", + "_mlir/passmanager.pyi", + "_mlir/rewrite.pyi", + ], + module_name = "_mlir", + deps = [":_mlir.so"], +) + ##---------------------------------------------------------------------------## td_library( @@ -1719,6 +1744,7 @@ td_library( ], includes = ["include"], deps = [ + ":BuiltinDialectTdFiles", ":InferTypeOpInterfaceTdFiles", ":OpBaseTdFiles", ":SideEffectInterfacesTdFiles", @@ -3961,6 +3987,7 @@ cc_library( ":ArithUtils", ":ControlFlowInterfaces", ":DialectUtils", + ":FuncDialect", ":FunctionInterfaces", ":GPUDialect", ":GPUUtils", @@ -3981,6 +4008,7 @@ cc_library( ":XeGPUPassIncGen", ":XeGPUUtils", ":XeGPUuArch", + ":XeVMDialect", "//llvm:Support", ], ) @@ -4569,6 +4597,7 @@ cc_library( ":SideEffectInterfaces", ":TensorDialect", ":TransformUtils", + ":UBDialect", ":ValueBoundsOpInterface", ":ViewLikeInterface", "//llvm:Support", @@ -13755,6 +13784,7 @@ cc_library( hdrs = glob(["include/mlir/Dialect/MPI/IR/*.h"]), includes = ["include"], deps = [ + ":ArithDialect", ":BytecodeOpInterface", ":DLTIDialect", ":IR", @@ -14514,6 +14544,7 @@ cc_library( includes = ["include"], deps = [ ":BytecodeOpInterface", + ":ControlFlowInterfaces", ":ConvertToLLVMInterface", ":IR", ":InliningUtils", diff --git a/utils/bazel/llvm-project-overlay/mlir/build_defs.bzl b/utils/bazel/llvm-project-overlay/mlir/build_defs.bzl index 5a3a776258b06..0d3073891d301 100644 --- a/utils/bazel/llvm-project-overlay/mlir/build_defs.bzl +++ b/utils/bazel/llvm-project-overlay/mlir/build_defs.bzl @@ -72,3 +72,24 @@ def mlir_c_api_cc_library( alwayslink = True, **kwargs ) + +def nanobind_pyi_genrule(name, module_name, outs, deps, visibility = None): + """Generates .pyi stub file(s) for a nanobind extension module. + + Args: + name: Name of the generated target. + module_name: Name of the module to generate stubs for (e.g., "_mlir"). + outs: List of expected output .pyi files. + deps: All .so modules to load (including the target module). + visibility: Visibility for the generated .pyi file(s). + """ + deps_arg = ",".join(["$(location " + d + ")" for d in deps]) + + native.genrule( + name = name, + srcs = deps, + outs = outs, + cmd = "$(location :stubgen_runner) --module " + module_name + " --deps " + deps_arg + " -o $(RULEDIR)", + tools = [":stubgen_runner"], + visibility = visibility, + ) diff --git a/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel index 912fcd33b4a2a..676d6703081b1 100644 --- a/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/python/BUILD.bazel @@ -523,6 +523,34 @@ filegroup( ], ) +##---------------------------------------------------------------------------## +# X86Vector dialect. +##---------------------------------------------------------------------------## + +gentbl_filegroup( + name = "X86VectorPyGen", + tbl_outs = { + "mlir/dialects/_x86vector_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=x86vector", + ], + }, + tblgen = "//mlir:mlir-tblgen", + td_file = "mlir/dialects/X86Vector.td", + deps = [ + "//mlir:OpBaseTdFiles", + "//mlir:X86VectorTdFiles", + ], +) + +filegroup( + name = "X86VectorPyFiles", + srcs = [ + "mlir/dialects/x86vector.py", + ":X86VectorPyGen", + ], +) + ##---------------------------------------------------------------------------## # IRDL dialect. ##---------------------------------------------------------------------------## @@ -1332,6 +1360,20 @@ gentbl_filegroup( ], ) +gentbl_filegroup( + name = "X86VectorTransformOpsPyGen", + tbl_outs = {"mlir/dialects/_x86vector_transform_ops_gen.py": [ + "-gen-python-op-bindings", + "-bind-dialect=transform", + "-dialect-extension=x86vector_transform", + ]}, + tblgen = "//mlir:mlir-tblgen", + td_file = "mlir/dialects/X86VectorTransformOps.td", + deps = [ + "//mlir:X86VectorTransformOpsTdFiles", + ], +) + gentbl_filegroup( name = "GPUTransformOpsPyGen", tbl_outs = {"mlir/dialects/_gpu_transform_ops_gen.py": [ @@ -1542,6 +1584,7 @@ filegroup( ":TransformSMTExtensionOpsPyGen", ":VectorTransformEnumPyGen", ":VectorTransformOpsPyGen", + ":X86VectorTransformOpsPyGen", ":XeGPUTransformOpsPyGen", ], ) diff --git a/utils/bazel/llvm-project-overlay/mlir/stubgen_runner.py b/utils/bazel/llvm-project-overlay/mlir/stubgen_runner.py new file mode 100644 index 0000000000000..9fb08425cbb1c --- /dev/null +++ b/utils/bazel/llvm-project-overlay/mlir/stubgen_runner.py @@ -0,0 +1,54 @@ +#!/usr/bin/env python3 +"""Generates .pyi stubs for nanobind extensions using nanobind's stubgen.""" + +import argparse +import ctypes +import importlib.util +import sys +from pathlib import Path + +from python.runfiles import Runfiles + + +def load_extension(path: Path): + """Load an extension module from a .so file with RTLD_GLOBAL.""" + module_name = path.stem.removesuffix(".abi3") + + # Load with RTLD_GLOBAL so symbols are available to dependent extensions. + ctypes.CDLL(str(path), mode=ctypes.RTLD_GLOBAL) + + spec = importlib.util.spec_from_file_location(module_name, path) + if spec is None or spec.loader is None: + sys.exit(f"Failed to load extension from {path}") + + module = importlib.util.module_from_spec(spec) + sys.modules[module_name] = module + spec.loader.exec_module(module) + return module_name + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument( + "--module", required=True, help="Module name to generate stubs for" + ) + parser.add_argument( + "--deps", required=True, help="Comma-separated .so files to load" + ) + parser.add_argument("-o", "--output", required=True, help="Output directory") + args = parser.parse_args() + + for dep_path in args.deps.split(","): + load_extension(Path(dep_path).resolve()) + + runfiles = Runfiles.Create() + stubgen_path = runfiles.Rlocation("+llvm_repos_extension+nanobind/src/stubgen.py") + spec = importlib.util.spec_from_file_location("stubgen", stubgen_path) + stubgen = importlib.util.module_from_spec(spec) + sys.modules["stubgen"] = stubgen + spec.loader.exec_module(stubgen) + stubgen.main(["-m", args.module, "-r", "-O", args.output]) + + +if __name__ == "__main__": + main() diff --git a/utils/bazel/llvm-project-overlay/mlir/test/Dialect/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/test/Dialect/BUILD.bazel index 6a0af96e96831..39f2199b5224e 100644 --- a/utils/bazel/llvm-project-overlay/mlir/test/Dialect/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/test/Dialect/BUILD.bazel @@ -9,6 +9,7 @@ package(default_visibility = ["//visibility:public"]) name = "%s.test" % src, srcs = [src], data = [ + "EmitC/tosa/td.mlir", "Vector/td/unroll-elements.mlir", "Vector/td/xfer-drop-unit-dims.mlir", "Vector/vector-sink-transform.mlir", @@ -29,6 +30,7 @@ package(default_visibility = ["//visibility:public"]) for src in glob( include = ["**/*.mlir"], exclude = [ + "EmitC/tosa/td.mlir", "IRDL/*.irdl.mlir", "Linalg/td/*.mlir", "Linalg/transpose-matmul-*.mlir", diff --git a/utils/bazel/llvm-project-overlay/mlir/test/Interfaces/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/test/Interfaces/BUILD.bazel new file mode 100644 index 0000000000000..ef41be3ebc865 --- /dev/null +++ b/utils/bazel/llvm-project-overlay/mlir/test/Interfaces/BUILD.bazel @@ -0,0 +1,20 @@ +load("//llvm:lit_test.bzl", "lit_test") + +licenses(["notice"]) + +package(default_visibility = ["//visibility:public"]) + +[ + lit_test( + name = "%s.test" % src, + srcs = [src], + data = [ + "//llvm:llvm-symbolizer", + "//mlir:mlir-opt", + "//mlir/test:lit_data", + ], + ) + for src in glob( + include = ["**/*.mlir"], + ) +] diff --git a/utils/bazel/third_party_build/nanobind.BUILD b/utils/bazel/third_party_build/nanobind.BUILD index 41296d9034fda..c33fb71471aea 100644 --- a/utils/bazel/third_party_build/nanobind.BUILD +++ b/utils/bazel/third_party_build/nanobind.BUILD @@ -1,5 +1,7 @@ load("@rules_cc//cc:defs.bzl", "cc_library") +exports_files(["src/stubgen.py"]) + cc_library( name = "nanobind", srcs = glob(